diff options
Diffstat (limited to 'include')
310 files changed, 0 insertions, 64047 deletions
diff --git a/include/asm-cris/Kbuild b/include/asm-cris/Kbuild deleted file mode 100644 index d5b631935ec8..000000000000 --- a/include/asm-cris/Kbuild +++ /dev/null | |||
| @@ -1,11 +0,0 @@ | |||
| 1 | include include/asm-generic/Kbuild.asm | ||
| 2 | |||
| 3 | header-y += arch-v10/ | ||
| 4 | header-y += arch-v32/ | ||
| 5 | |||
| 6 | header-y += ethernet.h | ||
| 7 | header-y += rtc.h | ||
| 8 | header-y += sync_serial.h | ||
| 9 | |||
| 10 | unifdef-y += etraxgpio.h | ||
| 11 | unifdef-y += rs485.h | ||
diff --git a/include/asm-cris/arch-v10/Kbuild b/include/asm-cris/arch-v10/Kbuild deleted file mode 100644 index 7a192e1290b1..000000000000 --- a/include/asm-cris/arch-v10/Kbuild +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | header-y += user.h | ||
| 2 | header-y += svinto.h | ||
| 3 | header-y += sv_addr_ag.h | ||
| 4 | header-y += sv_addr.agh | ||
diff --git a/include/asm-cris/arch-v10/atomic.h b/include/asm-cris/arch-v10/atomic.h deleted file mode 100644 index 6ef5e7d09024..000000000000 --- a/include/asm-cris/arch-v10/atomic.h +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_ATOMIC__ | ||
| 2 | #define __ASM_CRIS_ARCH_ATOMIC__ | ||
| 3 | |||
| 4 | #define cris_atomic_save(addr, flags) local_irq_save(flags); | ||
| 5 | #define cris_atomic_restore(addr, flags) local_irq_restore(flags); | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h deleted file mode 100644 index be85f6de25d3..000000000000 --- a/include/asm-cris/arch-v10/bitops.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* asm/arch/bitops.h for Linux/CRISv10 */ | ||
| 2 | |||
| 3 | #ifndef _CRIS_ARCH_BITOPS_H | ||
| 4 | #define _CRIS_ARCH_BITOPS_H | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Helper functions for the core of the ff[sz] functions, wrapping the | ||
| 8 | * syntactically awkward asms. The asms compute the number of leading | ||
| 9 | * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped | ||
| 10 | * number. They differ in that the first function also inverts all bits | ||
| 11 | * in the input. | ||
| 12 | */ | ||
| 13 | static inline unsigned long cris_swapnwbrlz(unsigned long w) | ||
| 14 | { | ||
| 15 | /* Let's just say we return the result in the same register as the | ||
| 16 | input. Saying we clobber the input but can return the result | ||
| 17 | in another register: | ||
| 18 | ! __asm__ ("swapnwbr %2\n\tlz %2,%0" | ||
| 19 | ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w)); | ||
| 20 | confuses gcc (sched.c, gcc from cris-dist-1.14). */ | ||
| 21 | |||
| 22 | unsigned long res; | ||
| 23 | __asm__ ("swapnwbr %0 \n\t" | ||
| 24 | "lz %0,%0" | ||
| 25 | : "=r" (res) : "0" (w)); | ||
| 26 | return res; | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline unsigned long cris_swapwbrlz(unsigned long w) | ||
| 30 | { | ||
| 31 | unsigned res; | ||
| 32 | __asm__ ("swapwbr %0 \n\t" | ||
| 33 | "lz %0,%0" | ||
| 34 | : "=r" (res) | ||
| 35 | : "0" (w)); | ||
| 36 | return res; | ||
| 37 | } | ||
| 38 | |||
| 39 | /* | ||
| 40 | * ffz = Find First Zero in word. Undefined if no zero exists, | ||
| 41 | * so code should check against ~0UL first.. | ||
| 42 | */ | ||
| 43 | static inline unsigned long ffz(unsigned long w) | ||
| 44 | { | ||
| 45 | return cris_swapnwbrlz(w); | ||
| 46 | } | ||
| 47 | |||
| 48 | /** | ||
| 49 | * __ffs - find first bit in word. | ||
| 50 | * @word: The word to search | ||
| 51 | * | ||
| 52 | * Undefined if no bit exists, so code should check against 0 first. | ||
| 53 | */ | ||
| 54 | static inline unsigned long __ffs(unsigned long word) | ||
| 55 | { | ||
| 56 | return cris_swapnwbrlz(~word); | ||
| 57 | } | ||
| 58 | |||
| 59 | /** | ||
| 60 | * ffs - find first bit set | ||
| 61 | * @x: the word to search | ||
| 62 | * | ||
| 63 | * This is defined the same way as | ||
| 64 | * the libc and compiler builtin ffs routines, therefore | ||
| 65 | * differs in spirit from the above ffz (man ffs). | ||
| 66 | */ | ||
| 67 | |||
| 68 | static inline unsigned long kernel_ffs(unsigned long w) | ||
| 69 | { | ||
| 70 | return w ? cris_swapwbrlz (w) + 1 : 0; | ||
| 71 | } | ||
| 72 | |||
| 73 | #endif | ||
diff --git a/include/asm-cris/arch-v10/bug.h b/include/asm-cris/arch-v10/bug.h deleted file mode 100644 index 3485d6b34bb0..000000000000 --- a/include/asm-cris/arch-v10/bug.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRISv10_ARCH_BUG_H | ||
| 2 | #define __ASM_CRISv10_ARCH_BUG_H | ||
| 3 | |||
| 4 | #include <linux/stringify.h> | ||
| 5 | |||
| 6 | #ifdef CONFIG_BUG | ||
| 7 | #ifdef CONFIG_DEBUG_BUGVERBOSE | ||
| 8 | /* The BUG() macro is used for marking obviously incorrect code paths. | ||
| 9 | * It will cause a message with the file name and line number to be printed, | ||
| 10 | * and then cause an oops. The message is actually printed by handle_BUG() | ||
| 11 | * in arch/cris/kernel/traps.c, and the reason we use this method of storing | ||
| 12 | * the file name and line number is that we do not want to affect the registers | ||
| 13 | * by calling printk() before causing the oops. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define BUG_PREFIX 0x0D7F | ||
| 17 | #define BUG_MAGIC 0x00001234 | ||
| 18 | |||
| 19 | struct bug_frame { | ||
| 20 | unsigned short prefix; | ||
| 21 | unsigned int magic; | ||
| 22 | unsigned short clear; | ||
| 23 | unsigned short movu; | ||
| 24 | unsigned short line; | ||
| 25 | unsigned short jump; | ||
| 26 | unsigned char *filename; | ||
| 27 | }; | ||
| 28 | |||
| 29 | #if 0 | ||
| 30 | /* Unfortunately this version of the macro does not work due to a problem | ||
| 31 | * with the compiler (aka a bug) when compiling with -O2, which sometimes | ||
| 32 | * erroneously causes the second input to be stored in a register... | ||
| 33 | */ | ||
| 34 | #define BUG() \ | ||
| 35 | __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ | ||
| 36 | "movu.w %0,$r0\n\t" \ | ||
| 37 | "jump %1\n\t" \ | ||
| 38 | : : "i" (__LINE__), "i" (__FILE__)) | ||
| 39 | #else | ||
| 40 | /* This version will have to do for now, until the compiler is fixed. | ||
| 41 | * The drawbacks of this version are that the file name will appear multiple | ||
| 42 | * times in the .rodata section, and that __LINE__ and __FILE__ can probably | ||
| 43 | * not be used like this with newer versions of gcc. | ||
| 44 | */ | ||
| 45 | #define BUG() \ | ||
| 46 | __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ | ||
| 47 | "movu.w " __stringify(__LINE__) ",$r0\n\t"\ | ||
| 48 | "jump 0f\n\t" \ | ||
| 49 | ".section .rodata\n" \ | ||
| 50 | "0:\t.string \"" __FILE__ "\"\n\t" \ | ||
| 51 | ".previous") | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #else | ||
| 55 | |||
| 56 | /* This just causes an oops. */ | ||
| 57 | #define BUG() (*(int *)0 = 0) | ||
| 58 | |||
| 59 | #endif | ||
| 60 | |||
| 61 | #define HAVE_ARCH_BUG | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #include <asm-generic/bug.h> | ||
| 65 | |||
| 66 | #endif | ||
diff --git a/include/asm-cris/arch-v10/byteorder.h b/include/asm-cris/arch-v10/byteorder.h deleted file mode 100644 index 255b646b7fa8..000000000000 --- a/include/asm-cris/arch-v10/byteorder.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_BYTEORDER_H | ||
| 2 | #define _CRIS_ARCH_BYTEORDER_H | ||
| 3 | |||
| 4 | #include <asm/types.h> | ||
| 5 | #include <linux/compiler.h> | ||
| 6 | |||
| 7 | /* we just define these two (as we can do the swap in a single | ||
| 8 | * asm instruction in CRIS) and the arch-independent files will put | ||
| 9 | * them together into ntohl etc. | ||
| 10 | */ | ||
| 11 | |||
| 12 | static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) | ||
| 13 | { | ||
| 14 | __asm__ ("swapwb %0" : "=r" (x) : "0" (x)); | ||
| 15 | |||
| 16 | return(x); | ||
| 17 | } | ||
| 18 | |||
| 19 | static inline __attribute_const__ __u16 ___arch__swab16(__u16 x) | ||
| 20 | { | ||
| 21 | __asm__ ("swapb %0" : "=r" (x) : "0" (x)); | ||
| 22 | |||
| 23 | return(x); | ||
| 24 | } | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-cris/arch-v10/cache.h b/include/asm-cris/arch-v10/cache.h deleted file mode 100644 index aea27184d2d2..000000000000 --- a/include/asm-cris/arch-v10/cache.h +++ /dev/null | |||
| @@ -1,8 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_CACHE_H | ||
| 2 | #define _ASM_ARCH_CACHE_H | ||
| 3 | |||
| 4 | /* Etrax 100LX have 32-byte cache-lines. */ | ||
| 5 | #define L1_CACHE_BYTES 32 | ||
| 6 | #define L1_CACHE_SHIFT 5 | ||
| 7 | |||
| 8 | #endif /* _ASM_ARCH_CACHE_H */ | ||
diff --git a/include/asm-cris/arch-v10/checksum.h b/include/asm-cris/arch-v10/checksum.h deleted file mode 100644 index b8000c5d7fe1..000000000000 --- a/include/asm-cris/arch-v10/checksum.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_CHECKSUM_H | ||
| 2 | #define _CRIS_ARCH_CHECKSUM_H | ||
| 3 | |||
| 4 | /* Checksum some values used in TCP/UDP headers. | ||
| 5 | * | ||
| 6 | * The gain by doing this in asm is that C will not generate carry-additions | ||
| 7 | * for the 32-bit components of the checksum, so otherwise we would have had | ||
| 8 | * to split all of those into 16-bit components, then add. | ||
| 9 | */ | ||
| 10 | |||
| 11 | static inline __wsum | ||
| 12 | csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, | ||
| 13 | unsigned short proto, __wsum sum) | ||
| 14 | { | ||
| 15 | __wsum res; | ||
| 16 | __asm__ ("add.d %2, %0\n\t" | ||
| 17 | "ax\n\t" | ||
| 18 | "add.d %3, %0\n\t" | ||
| 19 | "ax\n\t" | ||
| 20 | "add.d %4, %0\n\t" | ||
| 21 | "ax\n\t" | ||
| 22 | "addq 0, %0\n" | ||
| 23 | : "=r" (res) | ||
| 24 | : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8)); | ||
| 25 | |||
| 26 | return res; | ||
| 27 | } | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-cris/arch-v10/delay.h b/include/asm-cris/arch-v10/delay.h deleted file mode 100644 index 39481f6e0c30..000000000000 --- a/include/asm-cris/arch-v10/delay.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_DELAY_H | ||
| 2 | #define _CRIS_ARCH_DELAY_H | ||
| 3 | |||
| 4 | static inline void __delay(int loops) | ||
| 5 | { | ||
| 6 | __asm__ __volatile__ ( | ||
| 7 | "move.d %0,$r9\n\t" | ||
| 8 | "beq 2f\n\t" | ||
| 9 | "subq 1,$r9\n\t" | ||
| 10 | "1:\n\t" | ||
| 11 | "bne 1b\n\t" | ||
| 12 | "subq 1,$r9\n" | ||
| 13 | "2:" | ||
| 14 | : : "g" (loops) : "r9"); | ||
| 15 | } | ||
| 16 | |||
| 17 | #endif /* defined(_CRIS_ARCH_DELAY_H) */ | ||
| 18 | |||
| 19 | |||
| 20 | |||
diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h deleted file mode 100644 index ecb9dba6fa4f..000000000000 --- a/include/asm-cris/arch-v10/dma.h +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | /* Defines for using and allocating dma channels. */ | ||
| 2 | |||
| 3 | #ifndef _ASM_ARCH_DMA_H | ||
| 4 | #define _ASM_ARCH_DMA_H | ||
| 5 | |||
| 6 | #define MAX_DMA_CHANNELS 10 | ||
| 7 | |||
| 8 | /* dma0 and dma1 used for network (ethernet) */ | ||
| 9 | #define NETWORK_TX_DMA_NBR 0 | ||
| 10 | #define NETWORK_RX_DMA_NBR 1 | ||
| 11 | |||
| 12 | /* dma2 and dma3 shared by par0, scsi0, ser2 and ata */ | ||
| 13 | #define PAR0_TX_DMA_NBR 2 | ||
| 14 | #define PAR0_RX_DMA_NBR 3 | ||
| 15 | #define SCSI0_TX_DMA_NBR 2 | ||
| 16 | #define SCSI0_RX_DMA_NBR 3 | ||
| 17 | #define SER2_TX_DMA_NBR 2 | ||
| 18 | #define SER2_RX_DMA_NBR 3 | ||
| 19 | #define ATA_TX_DMA_NBR 2 | ||
| 20 | #define ATA_RX_DMA_NBR 3 | ||
| 21 | |||
| 22 | /* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ | ||
| 23 | #define PAR1_TX_DMA_NBR 4 | ||
| 24 | #define PAR1_RX_DMA_NBR 5 | ||
| 25 | #define SCSI1_TX_DMA_NBR 4 | ||
| 26 | #define SCSI1_RX_DMA_NBR 5 | ||
| 27 | #define SER3_TX_DMA_NBR 4 | ||
| 28 | #define SER3_RX_DMA_NBR 5 | ||
| 29 | #define EXTDMA0_TX_DMA_NBR 4 | ||
| 30 | #define EXTDMA0_RX_DMA_NBR 5 | ||
| 31 | |||
| 32 | /* dma6 and dma7 shared by ser0, extdma1 and mem2mem */ | ||
| 33 | #define SER0_TX_DMA_NBR 6 | ||
| 34 | #define SER0_RX_DMA_NBR 7 | ||
| 35 | #define EXTDMA1_TX_DMA_NBR 6 | ||
| 36 | #define EXTDMA1_RX_DMA_NBR 7 | ||
| 37 | #define MEM2MEM_TX_DMA_NBR 6 | ||
| 38 | #define MEM2MEM_RX_DMA_NBR 7 | ||
| 39 | |||
| 40 | /* dma8 and dma9 shared by ser1 and usb */ | ||
| 41 | #define SER1_TX_DMA_NBR 8 | ||
| 42 | #define SER1_RX_DMA_NBR 9 | ||
| 43 | #define USB_TX_DMA_NBR 8 | ||
| 44 | #define USB_RX_DMA_NBR 9 | ||
| 45 | |||
| 46 | #endif | ||
| 47 | |||
| 48 | enum dma_owner | ||
| 49 | { | ||
| 50 | dma_eth, | ||
| 51 | dma_ser0, | ||
| 52 | dma_ser1, /* Async and sync */ | ||
| 53 | dma_ser2, | ||
| 54 | dma_ser3, /* Async and sync */ | ||
| 55 | dma_ata, | ||
| 56 | dma_par0, | ||
| 57 | dma_par1, | ||
| 58 | dma_ext0, | ||
| 59 | dma_ext1, | ||
| 60 | dma_int6, | ||
| 61 | dma_int7, | ||
| 62 | dma_usb, | ||
| 63 | dma_scsi0, | ||
| 64 | dma_scsi1 | ||
| 65 | }; | ||
| 66 | |||
| 67 | /* Masks used by cris_request_dma options: */ | ||
| 68 | #define DMA_VERBOSE_ON_ERROR (1<<0) | ||
| 69 | #define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR) | ||
| 70 | |||
| 71 | int cris_request_dma(unsigned int dmanr, const char * device_id, | ||
| 72 | unsigned options, enum dma_owner owner); | ||
| 73 | |||
| 74 | void cris_free_dma(unsigned int dmanr, const char * device_id); | ||
diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h deleted file mode 100644 index 1c38ee728b17..000000000000 --- a/include/asm-cris/arch-v10/elf.h +++ /dev/null | |||
| @@ -1,81 +0,0 @@ | |||
| 1 | #ifndef __ASMCRIS_ARCH_ELF_H | ||
| 2 | #define __ASMCRIS_ARCH_ELF_H | ||
| 3 | |||
| 4 | #define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 | ||
| 5 | |||
| 6 | /* | ||
| 7 | * This is used to ensure we don't load something for the wrong architecture. | ||
| 8 | */ | ||
| 9 | #define elf_check_arch(x) \ | ||
| 10 | ((x)->e_machine == EM_CRIS \ | ||
| 11 | && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ | ||
| 12 | || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) | ||
| 13 | |||
| 14 | /* | ||
| 15 | * ELF register definitions.. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <asm/ptrace.h> | ||
| 19 | |||
| 20 | /* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program | ||
| 21 | starts (a register; assume first param register for CRIS) | ||
| 22 | contains a pointer to a function which might be | ||
| 23 | registered using `atexit'. This provides a mean for the | ||
| 24 | dynamic linker to call DT_FINI functions for shared libraries | ||
| 25 | that have been loaded before the code runs. | ||
| 26 | |||
| 27 | A value of 0 tells we have no such handler. */ | ||
| 28 | |||
| 29 | /* Explicitly set registers to 0 to increase determinism. */ | ||
| 30 | #define ELF_PLAT_INIT(_r, load_addr) do { \ | ||
| 31 | (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ | ||
| 32 | (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ | ||
| 33 | (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ | ||
| 34 | (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ | ||
| 35 | } while (0) | ||
| 36 | |||
| 37 | /* The additional layer below is because the stack pointer is missing in | ||
| 38 | the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t, | ||
| 39 | and should be filled in according to the layout of the user_regs_struct | ||
| 40 | struct; regs is a pt_regs struct. We dump all registers, though several are | ||
| 41 | obviously unnecessary. That way there's less need for intelligence at | ||
| 42 | the receiving end (i.e. gdb). */ | ||
| 43 | #define ELF_CORE_COPY_REGS(pr_reg, regs) \ | ||
| 44 | pr_reg[0] = regs->r0; \ | ||
| 45 | pr_reg[1] = regs->r1; \ | ||
| 46 | pr_reg[2] = regs->r2; \ | ||
| 47 | pr_reg[3] = regs->r3; \ | ||
| 48 | pr_reg[4] = regs->r4; \ | ||
| 49 | pr_reg[5] = regs->r5; \ | ||
| 50 | pr_reg[6] = regs->r6; \ | ||
| 51 | pr_reg[7] = regs->r7; \ | ||
| 52 | pr_reg[8] = regs->r8; \ | ||
| 53 | pr_reg[9] = regs->r9; \ | ||
| 54 | pr_reg[10] = regs->r10; \ | ||
| 55 | pr_reg[11] = regs->r11; \ | ||
| 56 | pr_reg[12] = regs->r12; \ | ||
| 57 | pr_reg[13] = regs->r13; \ | ||
| 58 | pr_reg[14] = rdusp(); /* sp */ \ | ||
| 59 | pr_reg[15] = regs->irp; /* pc */ \ | ||
| 60 | pr_reg[16] = 0; /* p0 */ \ | ||
| 61 | pr_reg[17] = rdvr(); /* vr */ \ | ||
| 62 | pr_reg[18] = 0; /* p2 */ \ | ||
| 63 | pr_reg[19] = 0; /* p3 */ \ | ||
| 64 | pr_reg[20] = 0; /* p4 */ \ | ||
| 65 | pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \ | ||
| 66 | pr_reg[22] = 0; /* p6 */ \ | ||
| 67 | pr_reg[23] = regs->mof; /* mof */ \ | ||
| 68 | pr_reg[24] = 0; /* p8 */ \ | ||
| 69 | pr_reg[25] = 0; /* ibr */ \ | ||
| 70 | pr_reg[26] = 0; /* irp */ \ | ||
| 71 | pr_reg[27] = regs->srp; /* srp */ \ | ||
| 72 | pr_reg[28] = 0; /* bar */ \ | ||
| 73 | pr_reg[29] = regs->dccr; /* dccr */ \ | ||
| 74 | pr_reg[30] = 0; /* brp */ \ | ||
| 75 | pr_reg[31] = rdusp(); /* usp */ \ | ||
| 76 | pr_reg[32] = 0; /* csrinstr */ \ | ||
| 77 | pr_reg[33] = 0; /* csraddr */ \ | ||
| 78 | pr_reg[34] = 0; /* csrdata */ | ||
| 79 | |||
| 80 | |||
| 81 | #endif | ||
diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h deleted file mode 100644 index c08c24265299..000000000000 --- a/include/asm-cris/arch-v10/io.h +++ /dev/null | |||
| @@ -1,199 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_CRIS_IO_H | ||
| 2 | #define _ASM_ARCH_CRIS_IO_H | ||
| 3 | |||
| 4 | #include <asm/arch/svinto.h> | ||
| 5 | |||
| 6 | /* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ | ||
| 7 | |||
| 8 | extern unsigned long gen_config_ii_shadow; | ||
| 9 | extern unsigned long port_g_data_shadow; | ||
| 10 | extern unsigned char port_pa_dir_shadow; | ||
| 11 | extern unsigned char port_pa_data_shadow; | ||
| 12 | extern unsigned char port_pb_i2c_shadow; | ||
| 13 | extern unsigned char port_pb_config_shadow; | ||
| 14 | extern unsigned char port_pb_dir_shadow; | ||
| 15 | extern unsigned char port_pb_data_shadow; | ||
| 16 | extern unsigned long r_timer_ctrl_shadow; | ||
| 17 | |||
| 18 | extern unsigned long port_cse1_shadow; | ||
| 19 | extern unsigned long port_csp0_shadow; | ||
| 20 | extern unsigned long port_csp4_shadow; | ||
| 21 | |||
| 22 | extern volatile unsigned long *port_cse1_addr; | ||
| 23 | extern volatile unsigned long *port_csp0_addr; | ||
| 24 | extern volatile unsigned long *port_csp4_addr; | ||
| 25 | |||
| 26 | /* macro for setting regs through a shadow - | ||
| 27 | * r = register name (like R_PORT_PA_DATA) | ||
| 28 | * s = shadow name (like port_pa_data_shadow) | ||
| 29 | * b = bit number | ||
| 30 | * v = value (0 or 1) | ||
| 31 | */ | ||
| 32 | |||
| 33 | #define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b)) | ||
| 34 | |||
| 35 | /* The LED's on various Etrax-based products are set differently. */ | ||
| 36 | |||
| 37 | #if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM) | ||
| 38 | #undef CONFIG_ETRAX_PA_LEDS | ||
| 39 | #undef CONFIG_ETRAX_PB_LEDS | ||
| 40 | #undef CONFIG_ETRAX_CSP0_LEDS | ||
| 41 | #define CRIS_LED_NETWORK_SET_G(x) | ||
| 42 | #define CRIS_LED_NETWORK_SET_R(x) | ||
| 43 | #define CRIS_LED_ACTIVE_SET_G(x) | ||
| 44 | #define CRIS_LED_ACTIVE_SET_R(x) | ||
| 45 | #define CRIS_LED_DISK_WRITE(x) | ||
| 46 | #define CRIS_LED_DISK_READ(x) | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #if !defined(CONFIG_ETRAX_CSP0_LEDS) | ||
| 50 | #define CRIS_LED_BIT_SET(x) | ||
| 51 | #define CRIS_LED_BIT_CLR(x) | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #define CRIS_LED_OFF 0x00 | ||
| 55 | #define CRIS_LED_GREEN 0x01 | ||
| 56 | #define CRIS_LED_RED 0x02 | ||
| 57 | #define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) | ||
| 58 | |||
| 59 | #if defined(CONFIG_ETRAX_NO_LEDS) | ||
| 60 | #define CRIS_LED_NETWORK_SET(x) | ||
| 61 | #else | ||
| 62 | #if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R | ||
| 63 | #define CRIS_LED_NETWORK_SET(x) \ | ||
| 64 | do { \ | ||
| 65 | CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ | ||
| 66 | } while (0) | ||
| 67 | #else | ||
| 68 | #define CRIS_LED_NETWORK_SET(x) \ | ||
| 69 | do { \ | ||
| 70 | CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ | ||
| 71 | CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \ | ||
| 72 | } while (0) | ||
| 73 | #endif | ||
| 74 | #if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R | ||
| 75 | #define CRIS_LED_ACTIVE_SET(x) \ | ||
| 76 | do { \ | ||
| 77 | CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ | ||
| 78 | } while (0) | ||
| 79 | #else | ||
| 80 | #define CRIS_LED_ACTIVE_SET(x) \ | ||
| 81 | do { \ | ||
| 82 | CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ | ||
| 83 | CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ | ||
| 84 | } while (0) | ||
| 85 | #endif | ||
| 86 | #endif | ||
| 87 | |||
| 88 | #ifdef CONFIG_ETRAX_PA_LEDS | ||
| 89 | #define CRIS_LED_NETWORK_SET_G(x) \ | ||
| 90 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) | ||
| 91 | #define CRIS_LED_NETWORK_SET_R(x) \ | ||
| 92 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) | ||
| 93 | #define CRIS_LED_ACTIVE_SET_G(x) \ | ||
| 94 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) | ||
| 95 | #define CRIS_LED_ACTIVE_SET_R(x) \ | ||
| 96 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) | ||
| 97 | #define CRIS_LED_DISK_WRITE(x) \ | ||
| 98 | do{\ | ||
| 99 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ | ||
| 100 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ | ||
| 101 | }while(0) | ||
| 102 | #define CRIS_LED_DISK_READ(x) \ | ||
| 103 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \ | ||
| 104 | CONFIG_ETRAX_LED3G, !(x)) | ||
| 105 | #endif | ||
| 106 | |||
| 107 | #ifdef CONFIG_ETRAX_PB_LEDS | ||
| 108 | #define CRIS_LED_NETWORK_SET_G(x) \ | ||
| 109 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) | ||
| 110 | #define CRIS_LED_NETWORK_SET_R(x) \ | ||
| 111 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) | ||
| 112 | #define CRIS_LED_ACTIVE_SET_G(x) \ | ||
| 113 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) | ||
| 114 | #define CRIS_LED_ACTIVE_SET_R(x) \ | ||
| 115 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) | ||
| 116 | #define CRIS_LED_DISK_WRITE(x) \ | ||
| 117 | do{\ | ||
| 118 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ | ||
| 119 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ | ||
| 120 | }while(0) | ||
| 121 | #define CRIS_LED_DISK_READ(x) \ | ||
| 122 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \ | ||
| 123 | CONFIG_ETRAX_LED3G, !(x)) | ||
| 124 | #endif | ||
| 125 | |||
| 126 | #ifdef CONFIG_ETRAX_CSP0_LEDS | ||
| 127 | #define CONFIGURABLE_LEDS\ | ||
| 128 | ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\ | ||
| 129 | (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\ | ||
| 130 | (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\ | ||
| 131 | (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\ | ||
| 132 | (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\ | ||
| 133 | (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\ | ||
| 134 | (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\ | ||
| 135 | (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\ | ||
| 136 | (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ | ||
| 137 | (1 << CONFIG_ETRAX_LED12R )) | ||
| 138 | |||
| 139 | #define CRIS_LED_NETWORK_SET_G(x) \ | ||
| 140 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) | ||
| 141 | #define CRIS_LED_NETWORK_SET_R(x) \ | ||
| 142 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) | ||
| 143 | #define CRIS_LED_ACTIVE_SET_G(x) \ | ||
| 144 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) | ||
| 145 | #define CRIS_LED_ACTIVE_SET_R(x) \ | ||
| 146 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) | ||
| 147 | #define CRIS_LED_DISK_WRITE(x) \ | ||
| 148 | do{\ | ||
| 149 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ | ||
| 150 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ | ||
| 151 | }while(0) | ||
| 152 | #define CRIS_LED_DISK_READ(x) \ | ||
| 153 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) | ||
| 154 | #define CRIS_LED_BIT_SET(x)\ | ||
| 155 | do{\ | ||
| 156 | if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ | ||
| 157 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ | ||
| 158 | }while(0) | ||
| 159 | #define CRIS_LED_BIT_CLR(x)\ | ||
| 160 | do{\ | ||
| 161 | if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ | ||
| 162 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ | ||
| 163 | }while(0) | ||
| 164 | #endif | ||
| 165 | |||
| 166 | # | ||
| 167 | #ifdef CONFIG_ETRAX_SOFT_SHUTDOWN | ||
| 168 | #define SOFT_SHUTDOWN() \ | ||
| 169 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1) | ||
| 170 | #else | ||
| 171 | #define SOFT_SHUTDOWN() | ||
| 172 | #endif | ||
| 173 | |||
| 174 | /* Console I/O for simulated etrax100. Use #ifdef so erroneous | ||
| 175 | use will be evident. */ | ||
| 176 | #ifdef CONFIG_SVINTO_SIM | ||
| 177 | /* Let's use the ucsim interface since it lets us do write(2, ...) */ | ||
| 178 | #define SIMCOUT(s,len) \ | ||
| 179 | asm ("moveq 4,$r9 \n\t" \ | ||
| 180 | "moveq 2,$r10 \n\t" \ | ||
| 181 | "move.d %0,$r11 \n\t" \ | ||
| 182 | "move.d %1,$r12 \n\t" \ | ||
| 183 | "push $irp \n\t" \ | ||
| 184 | "move 0f,$irp \n\t" \ | ||
| 185 | "jump -6809 \n" \ | ||
| 186 | "0: \n\t" \ | ||
| 187 | "pop $irp" \ | ||
| 188 | : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory") | ||
| 189 | #define TRACE_ON() __extension__ \ | ||
| 190 | ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \ | ||
| 191 | (255)); _Foofoo; }) | ||
| 192 | |||
| 193 | #define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0) | ||
| 194 | #define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0) | ||
| 195 | #define CRIS_CYCLES() __extension__ \ | ||
| 196 | ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;}) | ||
| 197 | #endif /* ! defined CONFIG_SVINTO_SIM */ | ||
| 198 | |||
| 199 | #endif | ||
diff --git a/include/asm-cris/arch-v10/io_interface_mux.h b/include/asm-cris/arch-v10/io_interface_mux.h deleted file mode 100644 index d92500080883..000000000000 --- a/include/asm-cris/arch-v10/io_interface_mux.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* IO interface mux allocator for ETRAX100LX. | ||
| 2 | * Copyright 2004, Axis Communications AB | ||
| 3 | * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $ | ||
| 4 | */ | ||
| 5 | |||
| 6 | |||
| 7 | #ifndef _IO_INTERFACE_MUX_H | ||
| 8 | #define _IO_INTERFACE_MUX_H | ||
| 9 | |||
| 10 | |||
| 11 | /* C.f. ETRAX100LX Designer's Reference 20.9 */ | ||
| 12 | |||
| 13 | /* The order in enum must match the order of interfaces[] in | ||
| 14 | * io_interface_mux.c */ | ||
| 15 | enum cris_io_interface { | ||
| 16 | /* Begin Non-multiplexed interfaces */ | ||
| 17 | if_eth = 0, | ||
| 18 | if_serial_0, | ||
| 19 | /* End Non-multiplexed interfaces */ | ||
| 20 | if_serial_1, | ||
| 21 | if_serial_2, | ||
| 22 | if_serial_3, | ||
| 23 | if_sync_serial_1, | ||
| 24 | if_sync_serial_3, | ||
| 25 | if_shared_ram, | ||
| 26 | if_shared_ram_w, | ||
| 27 | if_par_0, | ||
| 28 | if_par_1, | ||
| 29 | if_par_w, | ||
| 30 | if_scsi8_0, | ||
| 31 | if_scsi8_1, | ||
| 32 | if_scsi_w, | ||
| 33 | if_ata, | ||
| 34 | if_csp, | ||
| 35 | if_i2c, | ||
| 36 | if_usb_1, | ||
| 37 | if_usb_2, | ||
| 38 | /* GPIO pins */ | ||
| 39 | if_gpio_grp_a, | ||
| 40 | if_gpio_grp_b, | ||
| 41 | if_gpio_grp_c, | ||
| 42 | if_gpio_grp_d, | ||
| 43 | if_gpio_grp_e, | ||
| 44 | if_gpio_grp_f, | ||
| 45 | if_max_interfaces, | ||
| 46 | if_unclaimed | ||
| 47 | }; | ||
| 48 | |||
| 49 | int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id); | ||
| 50 | |||
| 51 | void cris_free_io_interface(enum cris_io_interface ioif); | ||
| 52 | |||
| 53 | /* port can be 'a', 'b' or 'g' */ | ||
| 54 | int cris_io_interface_allocate_pins(const enum cris_io_interface ioif, | ||
| 55 | const char port, | ||
| 56 | const unsigned start_bit, | ||
| 57 | const unsigned stop_bit); | ||
| 58 | |||
| 59 | /* port can be 'a', 'b' or 'g' */ | ||
| 60 | int cris_io_interface_free_pins(const enum cris_io_interface ioif, | ||
| 61 | const char port, | ||
| 62 | const unsigned start_bit, | ||
| 63 | const unsigned stop_bit); | ||
| 64 | |||
| 65 | int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available, | ||
| 66 | const unsigned int gpio_out_available, | ||
| 67 | const unsigned char pa_available, | ||
| 68 | const unsigned char pb_available)); | ||
| 69 | |||
| 70 | void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, | ||
| 71 | const unsigned int gpio_out_available, | ||
| 72 | const unsigned char pa_available, | ||
| 73 | const unsigned char pb_available)); | ||
| 74 | |||
| 75 | #endif /* _IO_INTERFACE_MUX_H */ | ||
diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h deleted file mode 100644 index b1128a9984ae..000000000000 --- a/include/asm-cris/arch-v10/irq.h +++ /dev/null | |||
| @@ -1,160 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Interrupt handling assembler and defines for Linux/CRISv10 | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _ASM_ARCH_IRQ_H | ||
| 6 | #define _ASM_ARCH_IRQ_H | ||
| 7 | |||
| 8 | #include <asm/arch/sv_addr_ag.h> | ||
| 9 | |||
| 10 | #define NR_IRQS 32 | ||
| 11 | |||
| 12 | /* The first vector number used for IRQs in v10 is really 0x20 */ | ||
| 13 | /* but all the code and constants are offseted to make 0 the first */ | ||
| 14 | #define FIRST_IRQ 0 | ||
| 15 | |||
| 16 | #define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */ | ||
| 17 | #define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */ | ||
| 18 | #define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */ | ||
| 19 | #define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */ | ||
| 20 | /* mio, ata, par0, scsi0 on 4 */ | ||
| 21 | /* par1, scsi1 on 5 */ | ||
| 22 | #define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */ | ||
| 23 | |||
| 24 | #define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */ | ||
| 25 | #define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */ | ||
| 26 | /* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */ | ||
| 27 | #define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0) | ||
| 28 | #define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1) | ||
| 29 | |||
| 30 | /* dma0-9 is irq 16..25 */ | ||
| 31 | /* 16,17: network */ | ||
| 32 | #define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0) | ||
| 33 | #define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1) | ||
| 34 | #define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR | ||
| 35 | #define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR | ||
| 36 | |||
| 37 | /* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */ | ||
| 38 | #define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2) | ||
| 39 | #define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3) | ||
| 40 | #define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR | ||
| 41 | #define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR | ||
| 42 | |||
| 43 | /* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ | ||
| 44 | #define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4) | ||
| 45 | #define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5) | ||
| 46 | #define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR | ||
| 47 | #define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR | ||
| 48 | |||
| 49 | /* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */ | ||
| 50 | #define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6) | ||
| 51 | #define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7) | ||
| 52 | #define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR | ||
| 53 | #define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR | ||
| 54 | #define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR | ||
| 55 | #define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR | ||
| 56 | |||
| 57 | /* 24,25: dma8 and dma9 shared by ser1 and usb */ | ||
| 58 | #define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8) | ||
| 59 | #define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9) | ||
| 60 | #define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR | ||
| 61 | #define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR | ||
| 62 | #define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR | ||
| 63 | #define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR | ||
| 64 | |||
| 65 | /* usb: controller at irq 31 + uses DMA8 and DMA9 */ | ||
| 66 | #define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb) | ||
| 67 | |||
| 68 | /* our fine, global, etrax irq vector! the pointer lives in the head.S file. */ | ||
| 69 | |||
| 70 | typedef void (*irqvectptr)(void); | ||
| 71 | |||
| 72 | struct etrax_interrupt_vector { | ||
| 73 | irqvectptr v[256]; | ||
| 74 | }; | ||
| 75 | |||
| 76 | extern struct etrax_interrupt_vector *etrax_irv; | ||
| 77 | void set_int_vector(int n, irqvectptr addr); | ||
| 78 | void set_break_vector(int n, irqvectptr addr); | ||
| 79 | |||
| 80 | #define __STR(x) #x | ||
| 81 | #define STR(x) __STR(x) | ||
| 82 | |||
| 83 | /* SAVE_ALL saves registers so they match pt_regs */ | ||
| 84 | |||
| 85 | #define SAVE_ALL \ | ||
| 86 | "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \ | ||
| 87 | "push $srp\n\t" /* push subroutine return pointer */ \ | ||
| 88 | "push $dccr\n\t" /* push condition codes */ \ | ||
| 89 | "push $mof\n\t" /* push multiply overflow reg */ \ | ||
| 90 | "di\n\t" /* need to disable irq's at this point */\ | ||
| 91 | "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \ | ||
| 92 | "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \ | ||
| 93 | "push $r10\n\t" /* push orig_r10 */ \ | ||
| 94 | "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */ | ||
| 95 | |||
| 96 | /* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */ | ||
| 97 | |||
| 98 | #define BLOCK_IRQ(mask,nr) \ | ||
| 99 | "move.d " #mask ",$r0\n\t" \ | ||
| 100 | "move.d $r0,[0xb00000d8]\n\t" | ||
| 101 | |||
| 102 | #define UNBLOCK_IRQ(mask) \ | ||
| 103 | "move.d " #mask ",$r0\n\t" \ | ||
| 104 | "move.d $r0,[0xb00000dc]\n\t" | ||
| 105 | |||
| 106 | #define IRQ_NAME2(nr) nr##_interrupt(void) | ||
| 107 | #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) | ||
| 108 | #define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr) | ||
| 109 | #define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr) | ||
| 110 | |||
| 111 | /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls | ||
| 112 | * do_IRQ (with irq disabled still). after that it unblocks and jumps to | ||
| 113 | * ret_from_intr (entry.S) | ||
| 114 | * | ||
| 115 | * The reason the IRQ is blocked is to allow an sti() before the handler which | ||
| 116 | * will acknowledge the interrupt is run. | ||
| 117 | */ | ||
| 118 | |||
| 119 | #define BUILD_IRQ(nr,mask) \ | ||
| 120 | void IRQ_NAME(nr); \ | ||
| 121 | __asm__ ( \ | ||
| 122 | ".text\n\t" \ | ||
| 123 | "IRQ" #nr "_interrupt:\n\t" \ | ||
| 124 | SAVE_ALL \ | ||
| 125 | BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ | ||
| 126 | "moveq "#nr",$r10\n\t" \ | ||
| 127 | "move.d $sp,$r11\n\t" \ | ||
| 128 | "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ | ||
| 129 | UNBLOCK_IRQ(mask) \ | ||
| 130 | "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ | ||
| 131 | "jump ret_from_intr\n\t"); | ||
| 132 | |||
| 133 | /* This is subtle. The timer interrupt is crucial and it should not be disabled for | ||
| 134 | * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would | ||
| 135 | * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK. | ||
| 136 | * If the softirq's take too much time to run, the timer irq won't run and the | ||
| 137 | * watchdog will kill us. | ||
| 138 | * | ||
| 139 | * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq | ||
| 140 | * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed | ||
| 141 | * it here, we would not get the multiple_irq at all. | ||
| 142 | * | ||
| 143 | * The non-blocking here is based on the knowledge that the timer interrupt is | ||
| 144 | * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not | ||
| 145 | * be an sti() before the timer irq handler is run to acknowledge the interrupt. | ||
| 146 | */ | ||
| 147 | |||
| 148 | #define BUILD_TIMER_IRQ(nr,mask) \ | ||
| 149 | void IRQ_NAME(nr); \ | ||
| 150 | __asm__ ( \ | ||
| 151 | ".text\n\t" \ | ||
| 152 | "IRQ" #nr "_interrupt:\n\t" \ | ||
| 153 | SAVE_ALL \ | ||
| 154 | "moveq "#nr",$r10\n\t" \ | ||
| 155 | "move.d $sp,$r11\n\t" \ | ||
| 156 | "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ | ||
| 157 | "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ | ||
| 158 | "jump ret_from_intr\n\t"); | ||
| 159 | |||
| 160 | #endif | ||
diff --git a/include/asm-cris/arch-v10/memmap.h b/include/asm-cris/arch-v10/memmap.h deleted file mode 100644 index 13f3b971407f..000000000000 --- a/include/asm-cris/arch-v10/memmap.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_MEMMAP_H | ||
| 2 | #define _ASM_ARCH_MEMMAP_H | ||
| 3 | |||
| 4 | #define MEM_CSE0_START (0x00000000) | ||
| 5 | #define MEM_CSE0_SIZE (0x04000000) | ||
| 6 | #define MEM_CSE1_START (0x04000000) | ||
| 7 | #define MEM_CSE1_SIZE (0x04000000) | ||
| 8 | #define MEM_CSR0_START (0x08000000) | ||
| 9 | #define MEM_CSR1_START (0x0c000000) | ||
| 10 | #define MEM_CSP0_START (0x10000000) | ||
| 11 | #define MEM_CSP1_START (0x14000000) | ||
| 12 | #define MEM_CSP2_START (0x18000000) | ||
| 13 | #define MEM_CSP3_START (0x1c000000) | ||
| 14 | #define MEM_CSP4_START (0x20000000) | ||
| 15 | #define MEM_CSP5_START (0x24000000) | ||
| 16 | #define MEM_CSP6_START (0x28000000) | ||
| 17 | #define MEM_CSP7_START (0x2c000000) | ||
| 18 | #define MEM_DRAM_START (0x40000000) | ||
| 19 | |||
| 20 | #define MEM_NON_CACHEABLE (0x80000000) | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h deleted file mode 100644 index df84f1716e6b..000000000000 --- a/include/asm-cris/arch-v10/mmu.h +++ /dev/null | |||
| @@ -1,109 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * CRIS MMU constants and PTE layout | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _CRIS_ARCH_MMU_H | ||
| 6 | #define _CRIS_ARCH_MMU_H | ||
| 7 | |||
| 8 | /* type used in struct mm to couple an MMU context to an active mm */ | ||
| 9 | |||
| 10 | typedef struct | ||
| 11 | { | ||
| 12 | unsigned int page_id; | ||
| 13 | } mm_context_t; | ||
| 14 | |||
| 15 | /* kernel memory segments */ | ||
| 16 | |||
| 17 | #define KSEG_F 0xf0000000UL | ||
| 18 | #define KSEG_E 0xe0000000UL | ||
| 19 | #define KSEG_D 0xd0000000UL | ||
| 20 | #define KSEG_C 0xc0000000UL | ||
| 21 | #define KSEG_B 0xb0000000UL | ||
| 22 | #define KSEG_A 0xa0000000UL | ||
| 23 | #define KSEG_9 0x90000000UL | ||
| 24 | #define KSEG_8 0x80000000UL | ||
| 25 | #define KSEG_7 0x70000000UL | ||
| 26 | #define KSEG_6 0x60000000UL | ||
| 27 | #define KSEG_5 0x50000000UL | ||
| 28 | #define KSEG_4 0x40000000UL | ||
| 29 | #define KSEG_3 0x30000000UL | ||
| 30 | #define KSEG_2 0x20000000UL | ||
| 31 | #define KSEG_1 0x10000000UL | ||
| 32 | #define KSEG_0 0x00000000UL | ||
| 33 | |||
| 34 | /* CRIS PTE bits (see R_TLB_LO in the register description) | ||
| 35 | * | ||
| 36 | * Bit: 31-13 12-------4 3 2 1 0 | ||
| 37 | * ________________________________________________ | ||
| 38 | * | pfn | reserved | global | valid | kernel | we | | ||
| 39 | * |_____|__________|________|_______|________|_____| | ||
| 40 | * | ||
| 41 | * (pfn = physical frame number) | ||
| 42 | */ | ||
| 43 | |||
| 44 | /* Real HW-based PTE bits. We use some synonym names so that | ||
| 45 | * things become less confusing in combination with the SW-based | ||
| 46 | * bits further below. | ||
| 47 | * | ||
| 48 | */ | ||
| 49 | |||
| 50 | #define _PAGE_WE (1<<0) /* page is write-enabled */ | ||
| 51 | #define _PAGE_SILENT_WRITE (1<<0) /* synonym */ | ||
| 52 | #define _PAGE_KERNEL (1<<1) /* page is kernel only */ | ||
| 53 | #define _PAGE_VALID (1<<2) /* page is valid */ | ||
| 54 | #define _PAGE_SILENT_READ (1<<2) /* synonym */ | ||
| 55 | #define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ | ||
| 56 | |||
| 57 | /* Bits the HW doesn't care about but the kernel uses them in SW */ | ||
| 58 | |||
| 59 | #define _PAGE_PRESENT (1<<4) /* page present in memory */ | ||
| 60 | #define _PAGE_FILE (1<<5) /* set: pagecache, unset: swap (when !PRESENT) */ | ||
| 61 | #define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */ | ||
| 62 | #define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */ | ||
| 63 | #define _PAGE_READ (1<<7) /* read-enabled */ | ||
| 64 | #define _PAGE_WRITE (1<<8) /* write-enabled */ | ||
| 65 | |||
| 66 | /* Define some higher level generic page attributes. */ | ||
| 67 | |||
| 68 | #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) | ||
| 69 | #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) | ||
| 70 | |||
| 71 | #define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) | ||
| 72 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) | ||
| 73 | |||
| 74 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) | ||
| 75 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ | ||
| 76 | _PAGE_ACCESSED) | ||
| 77 | #define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW | ||
| 78 | #define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) | ||
| 79 | #define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ | ||
| 80 | _PAGE_PRESENT | __READABLE | __WRITEABLE) | ||
| 81 | #define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) | ||
| 82 | |||
| 83 | /* | ||
| 84 | * CRIS can't do page protection for execute, and considers read the same. | ||
| 85 | * Also, write permissions imply read permissions. This is the closest we can | ||
| 86 | * get.. | ||
| 87 | */ | ||
| 88 | |||
| 89 | #define __P000 PAGE_NONE | ||
| 90 | #define __P001 PAGE_READONLY | ||
| 91 | #define __P010 PAGE_COPY | ||
| 92 | #define __P011 PAGE_COPY | ||
| 93 | #define __P100 PAGE_READONLY | ||
| 94 | #define __P101 PAGE_READONLY | ||
| 95 | #define __P110 PAGE_COPY | ||
| 96 | #define __P111 PAGE_COPY | ||
| 97 | |||
| 98 | #define __S000 PAGE_NONE | ||
| 99 | #define __S001 PAGE_READONLY | ||
| 100 | #define __S010 PAGE_SHARED | ||
| 101 | #define __S011 PAGE_SHARED | ||
| 102 | #define __S100 PAGE_READONLY | ||
| 103 | #define __S101 PAGE_READONLY | ||
| 104 | #define __S110 PAGE_SHARED | ||
| 105 | #define __S111 PAGE_SHARED | ||
| 106 | |||
| 107 | #define PTE_FILE_MAX_BITS 26 | ||
| 108 | |||
| 109 | #endif | ||
diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h deleted file mode 100644 index 675b51d85639..000000000000 --- a/include/asm-cris/arch-v10/offset.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | #ifndef __ASM_OFFSETS_H__ | ||
| 2 | #define __ASM_OFFSETS_H__ | ||
| 3 | /* | ||
| 4 | * DO NOT MODIFY. | ||
| 5 | * | ||
| 6 | * This file was generated by arch/cris/Makefile | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */ | ||
| 11 | #define PT_r13 8 /* offsetof(struct pt_regs, r13) */ | ||
| 12 | #define PT_r12 12 /* offsetof(struct pt_regs, r12) */ | ||
| 13 | #define PT_r11 16 /* offsetof(struct pt_regs, r11) */ | ||
| 14 | #define PT_r10 20 /* offsetof(struct pt_regs, r10) */ | ||
| 15 | #define PT_r9 24 /* offsetof(struct pt_regs, r9) */ | ||
| 16 | #define PT_mof 64 /* offsetof(struct pt_regs, mof) */ | ||
| 17 | #define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */ | ||
| 18 | #define PT_srp 72 /* offsetof(struct pt_regs, srp) */ | ||
| 19 | |||
| 20 | #define TI_task 0 /* offsetof(struct thread_info, task) */ | ||
| 21 | #define TI_flags 8 /* offsetof(struct thread_info, flags) */ | ||
| 22 | #define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ | ||
| 23 | |||
| 24 | #define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ | ||
| 25 | #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ | ||
| 26 | #define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ | ||
| 27 | |||
| 28 | #define TASK_pid 141 /* offsetof(struct task_struct, pid) */ | ||
| 29 | |||
| 30 | #define LCLONE_VM 256 /* CLONE_VM */ | ||
| 31 | #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/include/asm-cris/arch-v10/page.h b/include/asm-cris/arch-v10/page.h deleted file mode 100644 index ffafc99c3472..000000000000 --- a/include/asm-cris/arch-v10/page.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_PAGE_H | ||
| 2 | #define _CRIS_ARCH_PAGE_H | ||
| 3 | |||
| 4 | |||
| 5 | #ifdef __KERNEL__ | ||
| 6 | |||
| 7 | /* This handles the memory map.. */ | ||
| 8 | #ifdef CONFIG_CRIS_LOW_MAP | ||
| 9 | #define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */ | ||
| 10 | #else | ||
| 11 | #define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */ | ||
| 12 | #endif | ||
| 13 | |||
| 14 | /* macros to convert between really physical and virtual addresses | ||
| 15 | * by stripping a selected bit, we can convert between KSEG_x and | ||
| 16 | * 0x40000000 where the DRAM really resides | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifdef CONFIG_CRIS_LOW_MAP | ||
| 20 | /* we have DRAM virtually at 0x6 */ | ||
| 21 | #define __pa(x) ((unsigned long)(x) & 0xdfffffff) | ||
| 22 | #define __va(x) ((void *)((unsigned long)(x) | 0x20000000)) | ||
| 23 | #else | ||
| 24 | /* we have DRAM virtually at 0xc */ | ||
| 25 | #define __pa(x) ((unsigned long)(x) & 0x7fffffff) | ||
| 26 | #define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #endif | ||
| 30 | #endif | ||
diff --git a/include/asm-cris/arch-v10/pgtable.h b/include/asm-cris/arch-v10/pgtable.h deleted file mode 100644 index 2a2576d1fc97..000000000000 --- a/include/asm-cris/arch-v10/pgtable.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_PGTABLE_H | ||
| 2 | #define _CRIS_ARCH_PGTABLE_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Kernels own virtual memory area. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifdef CONFIG_CRIS_LOW_MAP | ||
| 9 | #define VMALLOC_START KSEG_7 | ||
| 10 | #define VMALLOC_END KSEG_8 | ||
| 11 | #else | ||
| 12 | #define VMALLOC_START KSEG_D | ||
| 13 | #define VMALLOC_END KSEG_E | ||
| 14 | #endif | ||
| 15 | |||
| 16 | #endif | ||
| 17 | |||
diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h deleted file mode 100644 index cc692c7a0660..000000000000 --- a/include/asm-cris/arch-v10/processor.h +++ /dev/null | |||
| @@ -1,70 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_PROCESSOR_H | ||
| 2 | #define __ASM_CRIS_ARCH_PROCESSOR_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Default implementation of macro that returns current | ||
| 6 | * instruction pointer ("program counter"). | ||
| 7 | */ | ||
| 8 | #define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; }) | ||
| 9 | |||
| 10 | /* CRIS has no problems with write protection */ | ||
| 11 | #define wp_works_ok 1 | ||
| 12 | |||
| 13 | /* CRIS thread_struct. this really has nothing to do with the processor itself, since | ||
| 14 | * CRIS does not do any hardware task-switching, but it's here for legacy reasons. | ||
| 15 | * The thread_struct here is used when task-switching using _resume defined in entry.S. | ||
| 16 | * The offsets here are hardcoded into _resume - if you change this struct, you need to | ||
| 17 | * change them as well!!! | ||
| 18 | */ | ||
| 19 | |||
| 20 | struct thread_struct { | ||
| 21 | unsigned long ksp; /* kernel stack pointer */ | ||
| 22 | unsigned long usp; /* user stack pointer */ | ||
| 23 | unsigned long dccr; /* saved flag register */ | ||
| 24 | }; | ||
| 25 | |||
| 26 | /* | ||
| 27 | * User space process size. This is hardcoded into a few places, | ||
| 28 | * so don't change it unless you know what you are doing. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifdef CONFIG_CRIS_LOW_MAP | ||
| 32 | #define TASK_SIZE (0x50000000UL) /* 1.25 GB */ | ||
| 33 | #else | ||
| 34 | #define TASK_SIZE (0xA0000000UL) /* 2.56 GB */ | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #define INIT_THREAD { \ | ||
| 38 | 0, 0, 0x20 } /* ccr = int enable, nothing else */ | ||
| 39 | |||
| 40 | #define KSTK_EIP(tsk) \ | ||
| 41 | ({ \ | ||
| 42 | unsigned long eip = 0; \ | ||
| 43 | unsigned long regs = (unsigned long)task_pt_regs(tsk); \ | ||
| 44 | if (regs > PAGE_SIZE && \ | ||
| 45 | virt_addr_valid(regs)) \ | ||
| 46 | eip = ((struct pt_regs *)regs)->irp; \ | ||
| 47 | eip; \ | ||
| 48 | }) | ||
| 49 | |||
| 50 | /* give the thread a program location | ||
| 51 | * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8) | ||
| 52 | * switch user-stackpointer | ||
| 53 | */ | ||
| 54 | |||
| 55 | #define start_thread(regs, ip, usp) do { \ | ||
| 56 | set_fs(USER_DS); \ | ||
| 57 | regs->irp = ip; \ | ||
| 58 | regs->dccr |= 1 << U_DCCR_BITNR; \ | ||
| 59 | wrusp(usp); \ | ||
| 60 | } while(0) | ||
| 61 | |||
| 62 | /* Called when handling a kernel bus fault fixup. | ||
| 63 | * | ||
| 64 | * After a fixup we do not want to return by restoring the CPU-state | ||
| 65 | * anymore, so switch frame-types (see ptrace.h) | ||
| 66 | */ | ||
| 67 | #define arch_fixup(regs) \ | ||
| 68 | regs->frametype = CRIS_FRAME_NORMAL; | ||
| 69 | |||
| 70 | #endif | ||
diff --git a/include/asm-cris/arch-v10/ptrace.h b/include/asm-cris/arch-v10/ptrace.h deleted file mode 100644 index 2f464eab3a51..000000000000 --- a/include/asm-cris/arch-v10/ptrace.h +++ /dev/null | |||
| @@ -1,119 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_PTRACE_H | ||
| 2 | #define _CRIS_ARCH_PTRACE_H | ||
| 3 | |||
| 4 | /* Frame types */ | ||
| 5 | |||
| 6 | #define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */ | ||
| 7 | #define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return | ||
| 8 | path */ | ||
| 9 | |||
| 10 | /* Register numbers in the ptrace system call interface */ | ||
| 11 | |||
| 12 | #define PT_FRAMETYPE 0 | ||
| 13 | #define PT_ORIG_R10 1 | ||
| 14 | #define PT_R13 2 | ||
| 15 | #define PT_R12 3 | ||
| 16 | #define PT_R11 4 | ||
| 17 | #define PT_R10 5 | ||
| 18 | #define PT_R9 6 | ||
| 19 | #define PT_R8 7 | ||
| 20 | #define PT_R7 8 | ||
| 21 | #define PT_R6 9 | ||
| 22 | #define PT_R5 10 | ||
| 23 | #define PT_R4 11 | ||
| 24 | #define PT_R3 12 | ||
| 25 | #define PT_R2 13 | ||
| 26 | #define PT_R1 14 | ||
| 27 | #define PT_R0 15 | ||
| 28 | #define PT_MOF 16 | ||
| 29 | #define PT_DCCR 17 | ||
| 30 | #define PT_SRP 18 | ||
| 31 | #define PT_IRP 19 /* This is actually the debugged process' PC */ | ||
| 32 | #define PT_CSRINSTR 20 /* CPU Status record remnants - | ||
| 33 | valid if frametype == busfault */ | ||
| 34 | #define PT_CSRADDR 21 | ||
| 35 | #define PT_CSRDATA 22 | ||
| 36 | #define PT_USP 23 /* special case - USP is not in the pt_regs */ | ||
| 37 | #define PT_MAX 23 | ||
| 38 | |||
| 39 | /* Condition code bit numbers. The same numbers apply to CCR of course, | ||
| 40 | but we use DCCR everywhere else, so let's try and be consistent. */ | ||
| 41 | #define C_DCCR_BITNR 0 | ||
| 42 | #define V_DCCR_BITNR 1 | ||
| 43 | #define Z_DCCR_BITNR 2 | ||
| 44 | #define N_DCCR_BITNR 3 | ||
| 45 | #define X_DCCR_BITNR 4 | ||
| 46 | #define I_DCCR_BITNR 5 | ||
| 47 | #define B_DCCR_BITNR 6 | ||
| 48 | #define M_DCCR_BITNR 7 | ||
| 49 | #define U_DCCR_BITNR 8 | ||
| 50 | #define P_DCCR_BITNR 9 | ||
| 51 | #define F_DCCR_BITNR 10 | ||
| 52 | |||
| 53 | /* pt_regs not only specifices the format in the user-struct during | ||
| 54 | * ptrace but is also the frame format used in the kernel prologue/epilogues | ||
| 55 | * themselves | ||
| 56 | */ | ||
| 57 | |||
| 58 | struct pt_regs { | ||
| 59 | unsigned long frametype; /* type of stackframe */ | ||
| 60 | unsigned long orig_r10; | ||
| 61 | /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */ | ||
| 62 | unsigned long r13; | ||
| 63 | unsigned long r12; | ||
| 64 | unsigned long r11; | ||
| 65 | unsigned long r10; | ||
| 66 | unsigned long r9; | ||
| 67 | unsigned long r8; | ||
| 68 | unsigned long r7; | ||
| 69 | unsigned long r6; | ||
| 70 | unsigned long r5; | ||
| 71 | unsigned long r4; | ||
| 72 | unsigned long r3; | ||
| 73 | unsigned long r2; | ||
| 74 | unsigned long r1; | ||
| 75 | unsigned long r0; | ||
| 76 | unsigned long mof; | ||
| 77 | unsigned long dccr; | ||
| 78 | unsigned long srp; | ||
| 79 | unsigned long irp; /* This is actually the debugged process' PC */ | ||
| 80 | unsigned long csrinstr; | ||
| 81 | unsigned long csraddr; | ||
| 82 | unsigned long csrdata; | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) | ||
| 86 | * when doing a context-switch. it is used (apart from in resume) when a new | ||
| 87 | * thread is made and we need to make _resume (which is starting it for the | ||
| 88 | * first time) realise what is going on. | ||
| 89 | * | ||
| 90 | * Actually, the use is very close to the thread struct (TSS) in that both the | ||
| 91 | * switch_stack and the TSS are used to keep thread stuff when switching in | ||
| 92 | * _resume. | ||
| 93 | */ | ||
| 94 | |||
| 95 | struct switch_stack { | ||
| 96 | unsigned long r9; | ||
| 97 | unsigned long r8; | ||
| 98 | unsigned long r7; | ||
| 99 | unsigned long r6; | ||
| 100 | unsigned long r5; | ||
| 101 | unsigned long r4; | ||
| 102 | unsigned long r3; | ||
| 103 | unsigned long r2; | ||
| 104 | unsigned long r1; | ||
| 105 | unsigned long r0; | ||
| 106 | unsigned long return_ip; /* ip that _resume will return to */ | ||
| 107 | }; | ||
| 108 | |||
| 109 | #ifdef __KERNEL__ | ||
| 110 | |||
| 111 | /* bit 8 is user-mode flag */ | ||
| 112 | #define user_mode(regs) (((regs)->dccr & 0x100) != 0) | ||
| 113 | #define instruction_pointer(regs) ((regs)->irp) | ||
| 114 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 115 | extern void show_regs(struct pt_regs *); | ||
| 116 | |||
| 117 | #endif /* __KERNEL__ */ | ||
| 118 | |||
| 119 | #endif | ||
diff --git a/include/asm-cris/arch-v10/sv_addr.agh b/include/asm-cris/arch-v10/sv_addr.agh deleted file mode 100644 index 6ac3a7bc9760..000000000000 --- a/include/asm-cris/arch-v10/sv_addr.agh +++ /dev/null | |||
| @@ -1,7306 +0,0 @@ | |||
| 1 | /* | ||
| 2 | !* This file was automatically generated by /n/asic/bin/reg_macro_gen | ||
| 3 | !* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. | ||
| 4 | !* Editing within this file is thus not recommended, | ||
| 5 | !* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. | ||
| 6 | !*/ | ||
| 7 | |||
| 8 | |||
| 9 | /* | ||
| 10 | !* Bus interface configuration registers | ||
| 11 | !*/ | ||
| 12 | |||
| 13 | #define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) | ||
| 14 | #define R_WAITSTATES__pcs4_7_zw__BITNR 30 | ||
| 15 | #define R_WAITSTATES__pcs4_7_zw__WIDTH 2 | ||
| 16 | #define R_WAITSTATES__pcs4_7_ew__BITNR 28 | ||
| 17 | #define R_WAITSTATES__pcs4_7_ew__WIDTH 2 | ||
| 18 | #define R_WAITSTATES__pcs4_7_lw__BITNR 24 | ||
| 19 | #define R_WAITSTATES__pcs4_7_lw__WIDTH 4 | ||
| 20 | #define R_WAITSTATES__pcs0_3_zw__BITNR 22 | ||
| 21 | #define R_WAITSTATES__pcs0_3_zw__WIDTH 2 | ||
| 22 | #define R_WAITSTATES__pcs0_3_ew__BITNR 20 | ||
| 23 | #define R_WAITSTATES__pcs0_3_ew__WIDTH 2 | ||
| 24 | #define R_WAITSTATES__pcs0_3_lw__BITNR 16 | ||
| 25 | #define R_WAITSTATES__pcs0_3_lw__WIDTH 4 | ||
| 26 | #define R_WAITSTATES__sram_zw__BITNR 14 | ||
| 27 | #define R_WAITSTATES__sram_zw__WIDTH 2 | ||
| 28 | #define R_WAITSTATES__sram_ew__BITNR 12 | ||
| 29 | #define R_WAITSTATES__sram_ew__WIDTH 2 | ||
| 30 | #define R_WAITSTATES__sram_lw__BITNR 8 | ||
| 31 | #define R_WAITSTATES__sram_lw__WIDTH 4 | ||
| 32 | #define R_WAITSTATES__flash_zw__BITNR 6 | ||
| 33 | #define R_WAITSTATES__flash_zw__WIDTH 2 | ||
| 34 | #define R_WAITSTATES__flash_ew__BITNR 4 | ||
| 35 | #define R_WAITSTATES__flash_ew__WIDTH 2 | ||
| 36 | #define R_WAITSTATES__flash_lw__BITNR 0 | ||
| 37 | #define R_WAITSTATES__flash_lw__WIDTH 4 | ||
| 38 | |||
| 39 | #define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) | ||
| 40 | #define R_BUS_CONFIG__sram_type__BITNR 9 | ||
| 41 | #define R_BUS_CONFIG__sram_type__WIDTH 1 | ||
| 42 | #define R_BUS_CONFIG__sram_type__cwe 1 | ||
| 43 | #define R_BUS_CONFIG__sram_type__bwe 0 | ||
| 44 | #define R_BUS_CONFIG__dma_burst__BITNR 8 | ||
| 45 | #define R_BUS_CONFIG__dma_burst__WIDTH 1 | ||
| 46 | #define R_BUS_CONFIG__dma_burst__burst16 1 | ||
| 47 | #define R_BUS_CONFIG__dma_burst__burst32 0 | ||
| 48 | #define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 | ||
| 49 | #define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 | ||
| 50 | #define R_BUS_CONFIG__pcs4_7_wr__ext 1 | ||
| 51 | #define R_BUS_CONFIG__pcs4_7_wr__norm 0 | ||
| 52 | #define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 | ||
| 53 | #define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 | ||
| 54 | #define R_BUS_CONFIG__pcs0_3_wr__ext 1 | ||
| 55 | #define R_BUS_CONFIG__pcs0_3_wr__norm 0 | ||
| 56 | #define R_BUS_CONFIG__sram_wr__BITNR 5 | ||
| 57 | #define R_BUS_CONFIG__sram_wr__WIDTH 1 | ||
| 58 | #define R_BUS_CONFIG__sram_wr__ext 1 | ||
| 59 | #define R_BUS_CONFIG__sram_wr__norm 0 | ||
| 60 | #define R_BUS_CONFIG__flash_wr__BITNR 4 | ||
| 61 | #define R_BUS_CONFIG__flash_wr__WIDTH 1 | ||
| 62 | #define R_BUS_CONFIG__flash_wr__ext 1 | ||
| 63 | #define R_BUS_CONFIG__flash_wr__norm 0 | ||
| 64 | #define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 | ||
| 65 | #define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 | ||
| 66 | #define R_BUS_CONFIG__pcs4_7_bw__bw32 1 | ||
| 67 | #define R_BUS_CONFIG__pcs4_7_bw__bw16 0 | ||
| 68 | #define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 | ||
| 69 | #define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 | ||
| 70 | #define R_BUS_CONFIG__pcs0_3_bw__bw32 1 | ||
| 71 | #define R_BUS_CONFIG__pcs0_3_bw__bw16 0 | ||
| 72 | #define R_BUS_CONFIG__sram_bw__BITNR 1 | ||
| 73 | #define R_BUS_CONFIG__sram_bw__WIDTH 1 | ||
| 74 | #define R_BUS_CONFIG__sram_bw__bw32 1 | ||
| 75 | #define R_BUS_CONFIG__sram_bw__bw16 0 | ||
| 76 | #define R_BUS_CONFIG__flash_bw__BITNR 0 | ||
| 77 | #define R_BUS_CONFIG__flash_bw__WIDTH 1 | ||
| 78 | #define R_BUS_CONFIG__flash_bw__bw32 1 | ||
| 79 | #define R_BUS_CONFIG__flash_bw__bw16 0 | ||
| 80 | |||
| 81 | #define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) | ||
| 82 | #define R_BUS_STATUS__pll_lock_tm__BITNR 5 | ||
| 83 | #define R_BUS_STATUS__pll_lock_tm__WIDTH 1 | ||
| 84 | #define R_BUS_STATUS__pll_lock_tm__expired 0 | ||
| 85 | #define R_BUS_STATUS__pll_lock_tm__counting 1 | ||
| 86 | #define R_BUS_STATUS__both_faults__BITNR 4 | ||
| 87 | #define R_BUS_STATUS__both_faults__WIDTH 1 | ||
| 88 | #define R_BUS_STATUS__both_faults__no 0 | ||
| 89 | #define R_BUS_STATUS__both_faults__yes 1 | ||
| 90 | #define R_BUS_STATUS__bsen___BITNR 3 | ||
| 91 | #define R_BUS_STATUS__bsen___WIDTH 1 | ||
| 92 | #define R_BUS_STATUS__bsen___enable 0 | ||
| 93 | #define R_BUS_STATUS__bsen___disable 1 | ||
| 94 | #define R_BUS_STATUS__boot__BITNR 1 | ||
| 95 | #define R_BUS_STATUS__boot__WIDTH 2 | ||
| 96 | #define R_BUS_STATUS__boot__uncached 0 | ||
| 97 | #define R_BUS_STATUS__boot__serial 1 | ||
| 98 | #define R_BUS_STATUS__boot__network 2 | ||
| 99 | #define R_BUS_STATUS__boot__parallel 3 | ||
| 100 | #define R_BUS_STATUS__flashw__BITNR 0 | ||
| 101 | #define R_BUS_STATUS__flashw__WIDTH 1 | ||
| 102 | #define R_BUS_STATUS__flashw__bw32 1 | ||
| 103 | #define R_BUS_STATUS__flashw__bw16 0 | ||
| 104 | |||
| 105 | #define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) | ||
| 106 | #define R_DRAM_TIMING__sdram__BITNR 31 | ||
| 107 | #define R_DRAM_TIMING__sdram__WIDTH 1 | ||
| 108 | #define R_DRAM_TIMING__sdram__enable 1 | ||
| 109 | #define R_DRAM_TIMING__sdram__disable 0 | ||
| 110 | #define R_DRAM_TIMING__ref__BITNR 14 | ||
| 111 | #define R_DRAM_TIMING__ref__WIDTH 2 | ||
| 112 | #define R_DRAM_TIMING__ref__e52us 0 | ||
| 113 | #define R_DRAM_TIMING__ref__e13us 1 | ||
| 114 | #define R_DRAM_TIMING__ref__e8700ns 2 | ||
| 115 | #define R_DRAM_TIMING__ref__disable 3 | ||
| 116 | #define R_DRAM_TIMING__rp__BITNR 12 | ||
| 117 | #define R_DRAM_TIMING__rp__WIDTH 2 | ||
| 118 | #define R_DRAM_TIMING__rs__BITNR 10 | ||
| 119 | #define R_DRAM_TIMING__rs__WIDTH 2 | ||
| 120 | #define R_DRAM_TIMING__rh__BITNR 8 | ||
| 121 | #define R_DRAM_TIMING__rh__WIDTH 2 | ||
| 122 | #define R_DRAM_TIMING__w__BITNR 7 | ||
| 123 | #define R_DRAM_TIMING__w__WIDTH 1 | ||
| 124 | #define R_DRAM_TIMING__w__norm 0 | ||
| 125 | #define R_DRAM_TIMING__w__ext 1 | ||
| 126 | #define R_DRAM_TIMING__c__BITNR 6 | ||
| 127 | #define R_DRAM_TIMING__c__WIDTH 1 | ||
| 128 | #define R_DRAM_TIMING__c__norm 0 | ||
| 129 | #define R_DRAM_TIMING__c__ext 1 | ||
| 130 | #define R_DRAM_TIMING__cz__BITNR 4 | ||
| 131 | #define R_DRAM_TIMING__cz__WIDTH 2 | ||
| 132 | #define R_DRAM_TIMING__cp__BITNR 2 | ||
| 133 | #define R_DRAM_TIMING__cp__WIDTH 2 | ||
| 134 | #define R_DRAM_TIMING__cw__BITNR 0 | ||
| 135 | #define R_DRAM_TIMING__cw__WIDTH 2 | ||
| 136 | |||
| 137 | #define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) | ||
| 138 | #define R_SDRAM_TIMING__sdram__BITNR 31 | ||
| 139 | #define R_SDRAM_TIMING__sdram__WIDTH 1 | ||
| 140 | #define R_SDRAM_TIMING__sdram__enable 1 | ||
| 141 | #define R_SDRAM_TIMING__sdram__disable 0 | ||
| 142 | #define R_SDRAM_TIMING__mrs_data__BITNR 16 | ||
| 143 | #define R_SDRAM_TIMING__mrs_data__WIDTH 15 | ||
| 144 | #define R_SDRAM_TIMING__ref__BITNR 14 | ||
| 145 | #define R_SDRAM_TIMING__ref__WIDTH 2 | ||
| 146 | #define R_SDRAM_TIMING__ref__e52us 0 | ||
| 147 | #define R_SDRAM_TIMING__ref__e13us 1 | ||
| 148 | #define R_SDRAM_TIMING__ref__e6500ns 2 | ||
| 149 | #define R_SDRAM_TIMING__ref__disable 3 | ||
| 150 | #define R_SDRAM_TIMING__ddr__BITNR 13 | ||
| 151 | #define R_SDRAM_TIMING__ddr__WIDTH 1 | ||
| 152 | #define R_SDRAM_TIMING__ddr__on 1 | ||
| 153 | #define R_SDRAM_TIMING__ddr__off 0 | ||
| 154 | #define R_SDRAM_TIMING__clk100__BITNR 12 | ||
| 155 | #define R_SDRAM_TIMING__clk100__WIDTH 1 | ||
| 156 | #define R_SDRAM_TIMING__clk100__on 1 | ||
| 157 | #define R_SDRAM_TIMING__clk100__off 0 | ||
| 158 | #define R_SDRAM_TIMING__ps__BITNR 11 | ||
| 159 | #define R_SDRAM_TIMING__ps__WIDTH 1 | ||
| 160 | #define R_SDRAM_TIMING__ps__on 1 | ||
| 161 | #define R_SDRAM_TIMING__ps__off 0 | ||
| 162 | #define R_SDRAM_TIMING__cmd__BITNR 9 | ||
| 163 | #define R_SDRAM_TIMING__cmd__WIDTH 2 | ||
| 164 | #define R_SDRAM_TIMING__cmd__pre 3 | ||
| 165 | #define R_SDRAM_TIMING__cmd__ref 2 | ||
| 166 | #define R_SDRAM_TIMING__cmd__mrs 1 | ||
| 167 | #define R_SDRAM_TIMING__cmd__nop 0 | ||
| 168 | #define R_SDRAM_TIMING__pde__BITNR 8 | ||
| 169 | #define R_SDRAM_TIMING__pde__WIDTH 1 | ||
| 170 | #define R_SDRAM_TIMING__rc__BITNR 6 | ||
| 171 | #define R_SDRAM_TIMING__rc__WIDTH 2 | ||
| 172 | #define R_SDRAM_TIMING__rp__BITNR 4 | ||
| 173 | #define R_SDRAM_TIMING__rp__WIDTH 2 | ||
| 174 | #define R_SDRAM_TIMING__rcd__BITNR 2 | ||
| 175 | #define R_SDRAM_TIMING__rcd__WIDTH 2 | ||
| 176 | #define R_SDRAM_TIMING__cl__BITNR 0 | ||
| 177 | #define R_SDRAM_TIMING__cl__WIDTH 2 | ||
| 178 | |||
| 179 | #define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) | ||
| 180 | #define R_DRAM_CONFIG__wmm1__BITNR 31 | ||
| 181 | #define R_DRAM_CONFIG__wmm1__WIDTH 1 | ||
| 182 | #define R_DRAM_CONFIG__wmm1__wmm 1 | ||
| 183 | #define R_DRAM_CONFIG__wmm1__norm 0 | ||
| 184 | #define R_DRAM_CONFIG__wmm0__BITNR 30 | ||
| 185 | #define R_DRAM_CONFIG__wmm0__WIDTH 1 | ||
| 186 | #define R_DRAM_CONFIG__wmm0__wmm 1 | ||
| 187 | #define R_DRAM_CONFIG__wmm0__norm 0 | ||
| 188 | #define R_DRAM_CONFIG__sh1__BITNR 27 | ||
| 189 | #define R_DRAM_CONFIG__sh1__WIDTH 3 | ||
| 190 | #define R_DRAM_CONFIG__sh0__BITNR 24 | ||
| 191 | #define R_DRAM_CONFIG__sh0__WIDTH 3 | ||
| 192 | #define R_DRAM_CONFIG__w__BITNR 23 | ||
| 193 | #define R_DRAM_CONFIG__w__WIDTH 1 | ||
| 194 | #define R_DRAM_CONFIG__w__bw16 0 | ||
| 195 | #define R_DRAM_CONFIG__w__bw32 1 | ||
| 196 | #define R_DRAM_CONFIG__c__BITNR 22 | ||
| 197 | #define R_DRAM_CONFIG__c__WIDTH 1 | ||
| 198 | #define R_DRAM_CONFIG__c__byte 0 | ||
| 199 | #define R_DRAM_CONFIG__c__bank 1 | ||
| 200 | #define R_DRAM_CONFIG__e__BITNR 21 | ||
| 201 | #define R_DRAM_CONFIG__e__WIDTH 1 | ||
| 202 | #define R_DRAM_CONFIG__e__fast 0 | ||
| 203 | #define R_DRAM_CONFIG__e__edo 1 | ||
| 204 | #define R_DRAM_CONFIG__group_sel__BITNR 16 | ||
| 205 | #define R_DRAM_CONFIG__group_sel__WIDTH 5 | ||
| 206 | #define R_DRAM_CONFIG__group_sel__grp0 0 | ||
| 207 | #define R_DRAM_CONFIG__group_sel__grp1 1 | ||
| 208 | #define R_DRAM_CONFIG__group_sel__bit9 9 | ||
| 209 | #define R_DRAM_CONFIG__group_sel__bit10 10 | ||
| 210 | #define R_DRAM_CONFIG__group_sel__bit11 11 | ||
| 211 | #define R_DRAM_CONFIG__group_sel__bit12 12 | ||
| 212 | #define R_DRAM_CONFIG__group_sel__bit13 13 | ||
| 213 | #define R_DRAM_CONFIG__group_sel__bit14 14 | ||
| 214 | #define R_DRAM_CONFIG__group_sel__bit15 15 | ||
| 215 | #define R_DRAM_CONFIG__group_sel__bit16 16 | ||
| 216 | #define R_DRAM_CONFIG__group_sel__bit17 17 | ||
| 217 | #define R_DRAM_CONFIG__group_sel__bit18 18 | ||
| 218 | #define R_DRAM_CONFIG__group_sel__bit19 19 | ||
| 219 | #define R_DRAM_CONFIG__group_sel__bit20 20 | ||
| 220 | #define R_DRAM_CONFIG__group_sel__bit21 21 | ||
| 221 | #define R_DRAM_CONFIG__group_sel__bit22 22 | ||
| 222 | #define R_DRAM_CONFIG__group_sel__bit23 23 | ||
| 223 | #define R_DRAM_CONFIG__group_sel__bit24 24 | ||
| 224 | #define R_DRAM_CONFIG__group_sel__bit25 25 | ||
| 225 | #define R_DRAM_CONFIG__group_sel__bit26 26 | ||
| 226 | #define R_DRAM_CONFIG__group_sel__bit27 27 | ||
| 227 | #define R_DRAM_CONFIG__group_sel__bit28 28 | ||
| 228 | #define R_DRAM_CONFIG__group_sel__bit29 29 | ||
| 229 | #define R_DRAM_CONFIG__ca1__BITNR 13 | ||
| 230 | #define R_DRAM_CONFIG__ca1__WIDTH 3 | ||
| 231 | #define R_DRAM_CONFIG__bank23sel__BITNR 8 | ||
| 232 | #define R_DRAM_CONFIG__bank23sel__WIDTH 5 | ||
| 233 | #define R_DRAM_CONFIG__bank23sel__bank0 0 | ||
| 234 | #define R_DRAM_CONFIG__bank23sel__bank1 1 | ||
| 235 | #define R_DRAM_CONFIG__bank23sel__bit9 9 | ||
| 236 | #define R_DRAM_CONFIG__bank23sel__bit10 10 | ||
| 237 | #define R_DRAM_CONFIG__bank23sel__bit11 11 | ||
| 238 | #define R_DRAM_CONFIG__bank23sel__bit12 12 | ||
| 239 | #define R_DRAM_CONFIG__bank23sel__bit13 13 | ||
| 240 | #define R_DRAM_CONFIG__bank23sel__bit14 14 | ||
| 241 | #define R_DRAM_CONFIG__bank23sel__bit15 15 | ||
| 242 | #define R_DRAM_CONFIG__bank23sel__bit16 16 | ||
| 243 | #define R_DRAM_CONFIG__bank23sel__bit17 17 | ||
| 244 | #define R_DRAM_CONFIG__bank23sel__bit18 18 | ||
| 245 | #define R_DRAM_CONFIG__bank23sel__bit19 19 | ||
| 246 | #define R_DRAM_CONFIG__bank23sel__bit20 20 | ||
| 247 | #define R_DRAM_CONFIG__bank23sel__bit21 21 | ||
| 248 | #define R_DRAM_CONFIG__bank23sel__bit22 22 | ||
| 249 | #define R_DRAM_CONFIG__bank23sel__bit23 23 | ||
| 250 | #define R_DRAM_CONFIG__bank23sel__bit24 24 | ||
| 251 | #define R_DRAM_CONFIG__bank23sel__bit25 25 | ||
| 252 | #define R_DRAM_CONFIG__bank23sel__bit26 26 | ||
| 253 | #define R_DRAM_CONFIG__bank23sel__bit27 27 | ||
| 254 | #define R_DRAM_CONFIG__bank23sel__bit28 28 | ||
| 255 | #define R_DRAM_CONFIG__bank23sel__bit29 29 | ||
| 256 | #define R_DRAM_CONFIG__ca0__BITNR 5 | ||
| 257 | #define R_DRAM_CONFIG__ca0__WIDTH 3 | ||
| 258 | #define R_DRAM_CONFIG__bank01sel__BITNR 0 | ||
| 259 | #define R_DRAM_CONFIG__bank01sel__WIDTH 5 | ||
| 260 | #define R_DRAM_CONFIG__bank01sel__bank0 0 | ||
| 261 | #define R_DRAM_CONFIG__bank01sel__bank1 1 | ||
| 262 | #define R_DRAM_CONFIG__bank01sel__bit9 9 | ||
| 263 | #define R_DRAM_CONFIG__bank01sel__bit10 10 | ||
| 264 | #define R_DRAM_CONFIG__bank01sel__bit11 11 | ||
| 265 | #define R_DRAM_CONFIG__bank01sel__bit12 12 | ||
| 266 | #define R_DRAM_CONFIG__bank01sel__bit13 13 | ||
| 267 | #define R_DRAM_CONFIG__bank01sel__bit14 14 | ||
| 268 | #define R_DRAM_CONFIG__bank01sel__bit15 15 | ||
| 269 | #define R_DRAM_CONFIG__bank01sel__bit16 16 | ||
| 270 | #define R_DRAM_CONFIG__bank01sel__bit17 17 | ||
| 271 | #define R_DRAM_CONFIG__bank01sel__bit18 18 | ||
| 272 | #define R_DRAM_CONFIG__bank01sel__bit19 19 | ||
| 273 | #define R_DRAM_CONFIG__bank01sel__bit20 20 | ||
| 274 | #define R_DRAM_CONFIG__bank01sel__bit21 21 | ||
| 275 | #define R_DRAM_CONFIG__bank01sel__bit22 22 | ||
| 276 | #define R_DRAM_CONFIG__bank01sel__bit23 23 | ||
| 277 | #define R_DRAM_CONFIG__bank01sel__bit24 24 | ||
| 278 | #define R_DRAM_CONFIG__bank01sel__bit25 25 | ||
| 279 | #define R_DRAM_CONFIG__bank01sel__bit26 26 | ||
| 280 | #define R_DRAM_CONFIG__bank01sel__bit27 27 | ||
| 281 | #define R_DRAM_CONFIG__bank01sel__bit28 28 | ||
| 282 | #define R_DRAM_CONFIG__bank01sel__bit29 29 | ||
| 283 | |||
| 284 | #define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) | ||
| 285 | #define R_SDRAM_CONFIG__wmm1__BITNR 31 | ||
| 286 | #define R_SDRAM_CONFIG__wmm1__WIDTH 1 | ||
| 287 | #define R_SDRAM_CONFIG__wmm1__wmm 1 | ||
| 288 | #define R_SDRAM_CONFIG__wmm1__norm 0 | ||
| 289 | #define R_SDRAM_CONFIG__wmm0__BITNR 30 | ||
| 290 | #define R_SDRAM_CONFIG__wmm0__WIDTH 1 | ||
| 291 | #define R_SDRAM_CONFIG__wmm0__wmm 1 | ||
| 292 | #define R_SDRAM_CONFIG__wmm0__norm 0 | ||
| 293 | #define R_SDRAM_CONFIG__sh1__BITNR 27 | ||
| 294 | #define R_SDRAM_CONFIG__sh1__WIDTH 3 | ||
| 295 | #define R_SDRAM_CONFIG__sh0__BITNR 24 | ||
| 296 | #define R_SDRAM_CONFIG__sh0__WIDTH 3 | ||
| 297 | #define R_SDRAM_CONFIG__w__BITNR 23 | ||
| 298 | #define R_SDRAM_CONFIG__w__WIDTH 1 | ||
| 299 | #define R_SDRAM_CONFIG__w__bw16 0 | ||
| 300 | #define R_SDRAM_CONFIG__w__bw32 1 | ||
| 301 | #define R_SDRAM_CONFIG__type1__BITNR 22 | ||
| 302 | #define R_SDRAM_CONFIG__type1__WIDTH 1 | ||
| 303 | #define R_SDRAM_CONFIG__type1__bank2 0 | ||
| 304 | #define R_SDRAM_CONFIG__type1__bank4 1 | ||
| 305 | #define R_SDRAM_CONFIG__type0__BITNR 21 | ||
| 306 | #define R_SDRAM_CONFIG__type0__WIDTH 1 | ||
| 307 | #define R_SDRAM_CONFIG__type0__bank2 0 | ||
| 308 | #define R_SDRAM_CONFIG__type0__bank4 1 | ||
| 309 | #define R_SDRAM_CONFIG__group_sel__BITNR 16 | ||
| 310 | #define R_SDRAM_CONFIG__group_sel__WIDTH 5 | ||
| 311 | #define R_SDRAM_CONFIG__group_sel__grp0 0 | ||
| 312 | #define R_SDRAM_CONFIG__group_sel__grp1 1 | ||
| 313 | #define R_SDRAM_CONFIG__group_sel__bit9 9 | ||
| 314 | #define R_SDRAM_CONFIG__group_sel__bit10 10 | ||
| 315 | #define R_SDRAM_CONFIG__group_sel__bit11 11 | ||
| 316 | #define R_SDRAM_CONFIG__group_sel__bit12 12 | ||
| 317 | #define R_SDRAM_CONFIG__group_sel__bit13 13 | ||
| 318 | #define R_SDRAM_CONFIG__group_sel__bit14 14 | ||
| 319 | #define R_SDRAM_CONFIG__group_sel__bit15 15 | ||
| 320 | #define R_SDRAM_CONFIG__group_sel__bit16 16 | ||
| 321 | #define R_SDRAM_CONFIG__group_sel__bit17 17 | ||
| 322 | #define R_SDRAM_CONFIG__group_sel__bit18 18 | ||
| 323 | #define R_SDRAM_CONFIG__group_sel__bit19 19 | ||
| 324 | #define R_SDRAM_CONFIG__group_sel__bit20 20 | ||
| 325 | #define R_SDRAM_CONFIG__group_sel__bit21 21 | ||
| 326 | #define R_SDRAM_CONFIG__group_sel__bit22 22 | ||
| 327 | #define R_SDRAM_CONFIG__group_sel__bit23 23 | ||
| 328 | #define R_SDRAM_CONFIG__group_sel__bit24 24 | ||
| 329 | #define R_SDRAM_CONFIG__group_sel__bit25 25 | ||
| 330 | #define R_SDRAM_CONFIG__group_sel__bit26 26 | ||
| 331 | #define R_SDRAM_CONFIG__group_sel__bit27 27 | ||
| 332 | #define R_SDRAM_CONFIG__group_sel__bit28 28 | ||
| 333 | #define R_SDRAM_CONFIG__group_sel__bit29 29 | ||
| 334 | #define R_SDRAM_CONFIG__ca1__BITNR 13 | ||
| 335 | #define R_SDRAM_CONFIG__ca1__WIDTH 3 | ||
| 336 | #define R_SDRAM_CONFIG__bank_sel1__BITNR 8 | ||
| 337 | #define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 | ||
| 338 | #define R_SDRAM_CONFIG__bank_sel1__bit9 9 | ||
| 339 | #define R_SDRAM_CONFIG__bank_sel1__bit10 10 | ||
| 340 | #define R_SDRAM_CONFIG__bank_sel1__bit11 11 | ||
| 341 | #define R_SDRAM_CONFIG__bank_sel1__bit12 12 | ||
| 342 | #define R_SDRAM_CONFIG__bank_sel1__bit13 13 | ||
| 343 | #define R_SDRAM_CONFIG__bank_sel1__bit14 14 | ||
| 344 | #define R_SDRAM_CONFIG__bank_sel1__bit15 15 | ||
| 345 | #define R_SDRAM_CONFIG__bank_sel1__bit16 16 | ||
| 346 | #define R_SDRAM_CONFIG__bank_sel1__bit17 17 | ||
| 347 | #define R_SDRAM_CONFIG__bank_sel1__bit18 18 | ||
| 348 | #define R_SDRAM_CONFIG__bank_sel1__bit19 19 | ||
| 349 | #define R_SDRAM_CONFIG__bank_sel1__bit20 20 | ||
| 350 | #define R_SDRAM_CONFIG__bank_sel1__bit21 21 | ||
| 351 | #define R_SDRAM_CONFIG__bank_sel1__bit22 22 | ||
| 352 | #define R_SDRAM_CONFIG__bank_sel1__bit23 23 | ||
| 353 | #define R_SDRAM_CONFIG__bank_sel1__bit24 24 | ||
| 354 | #define R_SDRAM_CONFIG__bank_sel1__bit25 25 | ||
| 355 | #define R_SDRAM_CONFIG__bank_sel1__bit26 26 | ||
| 356 | #define R_SDRAM_CONFIG__bank_sel1__bit27 27 | ||
| 357 | #define R_SDRAM_CONFIG__bank_sel1__bit28 28 | ||
| 358 | #define R_SDRAM_CONFIG__bank_sel1__bit29 29 | ||
| 359 | #define R_SDRAM_CONFIG__ca0__BITNR 5 | ||
| 360 | #define R_SDRAM_CONFIG__ca0__WIDTH 3 | ||
| 361 | #define R_SDRAM_CONFIG__bank_sel0__BITNR 0 | ||
| 362 | #define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 | ||
| 363 | #define R_SDRAM_CONFIG__bank_sel0__bit9 9 | ||
| 364 | #define R_SDRAM_CONFIG__bank_sel0__bit10 10 | ||
| 365 | #define R_SDRAM_CONFIG__bank_sel0__bit11 11 | ||
| 366 | #define R_SDRAM_CONFIG__bank_sel0__bit12 12 | ||
| 367 | #define R_SDRAM_CONFIG__bank_sel0__bit13 13 | ||
| 368 | #define R_SDRAM_CONFIG__bank_sel0__bit14 14 | ||
| 369 | #define R_SDRAM_CONFIG__bank_sel0__bit15 15 | ||
| 370 | #define R_SDRAM_CONFIG__bank_sel0__bit16 16 | ||
| 371 | #define R_SDRAM_CONFIG__bank_sel0__bit17 17 | ||
| 372 | #define R_SDRAM_CONFIG__bank_sel0__bit18 18 | ||
| 373 | #define R_SDRAM_CONFIG__bank_sel0__bit19 19 | ||
| 374 | #define R_SDRAM_CONFIG__bank_sel0__bit20 20 | ||
| 375 | #define R_SDRAM_CONFIG__bank_sel0__bit21 21 | ||
| 376 | #define R_SDRAM_CONFIG__bank_sel0__bit22 22 | ||
| 377 | #define R_SDRAM_CONFIG__bank_sel0__bit23 23 | ||
| 378 | #define R_SDRAM_CONFIG__bank_sel0__bit24 24 | ||
| 379 | #define R_SDRAM_CONFIG__bank_sel0__bit25 25 | ||
| 380 | #define R_SDRAM_CONFIG__bank_sel0__bit26 26 | ||
| 381 | #define R_SDRAM_CONFIG__bank_sel0__bit27 27 | ||
| 382 | #define R_SDRAM_CONFIG__bank_sel0__bit28 28 | ||
| 383 | #define R_SDRAM_CONFIG__bank_sel0__bit29 29 | ||
| 384 | |||
| 385 | /* | ||
| 386 | !* External DMA registers | ||
| 387 | !*/ | ||
| 388 | |||
| 389 | #define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) | ||
| 390 | #define R_EXT_DMA_0_CMD__cnt__BITNR 23 | ||
| 391 | #define R_EXT_DMA_0_CMD__cnt__WIDTH 1 | ||
| 392 | #define R_EXT_DMA_0_CMD__cnt__enable 1 | ||
| 393 | #define R_EXT_DMA_0_CMD__cnt__disable 0 | ||
| 394 | #define R_EXT_DMA_0_CMD__rqpol__BITNR 22 | ||
| 395 | #define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 | ||
| 396 | #define R_EXT_DMA_0_CMD__rqpol__ahigh 0 | ||
| 397 | #define R_EXT_DMA_0_CMD__rqpol__alow 1 | ||
| 398 | #define R_EXT_DMA_0_CMD__apol__BITNR 21 | ||
| 399 | #define R_EXT_DMA_0_CMD__apol__WIDTH 1 | ||
| 400 | #define R_EXT_DMA_0_CMD__apol__ahigh 0 | ||
| 401 | #define R_EXT_DMA_0_CMD__apol__alow 1 | ||
| 402 | #define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 | ||
| 403 | #define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 | ||
| 404 | #define R_EXT_DMA_0_CMD__rq_ack__burst 0 | ||
| 405 | #define R_EXT_DMA_0_CMD__rq_ack__handsh 1 | ||
| 406 | #define R_EXT_DMA_0_CMD__wid__BITNR 18 | ||
| 407 | #define R_EXT_DMA_0_CMD__wid__WIDTH 2 | ||
| 408 | #define R_EXT_DMA_0_CMD__wid__byte 0 | ||
| 409 | #define R_EXT_DMA_0_CMD__wid__word 1 | ||
| 410 | #define R_EXT_DMA_0_CMD__wid__dword 2 | ||
| 411 | #define R_EXT_DMA_0_CMD__dir__BITNR 17 | ||
| 412 | #define R_EXT_DMA_0_CMD__dir__WIDTH 1 | ||
| 413 | #define R_EXT_DMA_0_CMD__dir__input 0 | ||
| 414 | #define R_EXT_DMA_0_CMD__dir__output 1 | ||
| 415 | #define R_EXT_DMA_0_CMD__run__BITNR 16 | ||
| 416 | #define R_EXT_DMA_0_CMD__run__WIDTH 1 | ||
| 417 | #define R_EXT_DMA_0_CMD__run__start 1 | ||
| 418 | #define R_EXT_DMA_0_CMD__run__stop 0 | ||
| 419 | #define R_EXT_DMA_0_CMD__trf_count__BITNR 0 | ||
| 420 | #define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 | ||
| 421 | |||
| 422 | #define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) | ||
| 423 | #define R_EXT_DMA_0_STAT__run__BITNR 16 | ||
| 424 | #define R_EXT_DMA_0_STAT__run__WIDTH 1 | ||
| 425 | #define R_EXT_DMA_0_STAT__run__start 1 | ||
| 426 | #define R_EXT_DMA_0_STAT__run__stop 0 | ||
| 427 | #define R_EXT_DMA_0_STAT__trf_count__BITNR 0 | ||
| 428 | #define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 | ||
| 429 | |||
| 430 | #define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) | ||
| 431 | #define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 | ||
| 432 | #define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 | ||
| 433 | |||
| 434 | #define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) | ||
| 435 | #define R_EXT_DMA_1_CMD__cnt__BITNR 23 | ||
| 436 | #define R_EXT_DMA_1_CMD__cnt__WIDTH 1 | ||
| 437 | #define R_EXT_DMA_1_CMD__cnt__enable 1 | ||
| 438 | #define R_EXT_DMA_1_CMD__cnt__disable 0 | ||
| 439 | #define R_EXT_DMA_1_CMD__rqpol__BITNR 22 | ||
| 440 | #define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 | ||
| 441 | #define R_EXT_DMA_1_CMD__rqpol__ahigh 0 | ||
| 442 | #define R_EXT_DMA_1_CMD__rqpol__alow 1 | ||
| 443 | #define R_EXT_DMA_1_CMD__apol__BITNR 21 | ||
| 444 | #define R_EXT_DMA_1_CMD__apol__WIDTH 1 | ||
| 445 | #define R_EXT_DMA_1_CMD__apol__ahigh 0 | ||
| 446 | #define R_EXT_DMA_1_CMD__apol__alow 1 | ||
| 447 | #define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 | ||
| 448 | #define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 | ||
| 449 | #define R_EXT_DMA_1_CMD__rq_ack__burst 0 | ||
| 450 | #define R_EXT_DMA_1_CMD__rq_ack__handsh 1 | ||
| 451 | #define R_EXT_DMA_1_CMD__wid__BITNR 18 | ||
| 452 | #define R_EXT_DMA_1_CMD__wid__WIDTH 2 | ||
| 453 | #define R_EXT_DMA_1_CMD__wid__byte 0 | ||
| 454 | #define R_EXT_DMA_1_CMD__wid__word 1 | ||
| 455 | #define R_EXT_DMA_1_CMD__wid__dword 2 | ||
| 456 | #define R_EXT_DMA_1_CMD__dir__BITNR 17 | ||
| 457 | #define R_EXT_DMA_1_CMD__dir__WIDTH 1 | ||
| 458 | #define R_EXT_DMA_1_CMD__dir__input 0 | ||
| 459 | #define R_EXT_DMA_1_CMD__dir__output 1 | ||
| 460 | #define R_EXT_DMA_1_CMD__run__BITNR 16 | ||
| 461 | #define R_EXT_DMA_1_CMD__run__WIDTH 1 | ||
| 462 | #define R_EXT_DMA_1_CMD__run__start 1 | ||
| 463 | #define R_EXT_DMA_1_CMD__run__stop 0 | ||
| 464 | #define R_EXT_DMA_1_CMD__trf_count__BITNR 0 | ||
| 465 | #define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 | ||
| 466 | |||
| 467 | #define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) | ||
| 468 | #define R_EXT_DMA_1_STAT__run__BITNR 16 | ||
| 469 | #define R_EXT_DMA_1_STAT__run__WIDTH 1 | ||
| 470 | #define R_EXT_DMA_1_STAT__run__start 1 | ||
| 471 | #define R_EXT_DMA_1_STAT__run__stop 0 | ||
| 472 | #define R_EXT_DMA_1_STAT__trf_count__BITNR 0 | ||
| 473 | #define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 | ||
| 474 | |||
| 475 | #define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) | ||
| 476 | #define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 | ||
| 477 | #define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 | ||
| 478 | |||
| 479 | /* | ||
| 480 | !* Timer registers | ||
| 481 | !*/ | ||
| 482 | |||
| 483 | #define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) | ||
| 484 | #define R_TIMER_CTRL__timerdiv1__BITNR 24 | ||
| 485 | #define R_TIMER_CTRL__timerdiv1__WIDTH 8 | ||
| 486 | #define R_TIMER_CTRL__timerdiv0__BITNR 16 | ||
| 487 | #define R_TIMER_CTRL__timerdiv0__WIDTH 8 | ||
| 488 | #define R_TIMER_CTRL__presc_timer1__BITNR 15 | ||
| 489 | #define R_TIMER_CTRL__presc_timer1__WIDTH 1 | ||
| 490 | #define R_TIMER_CTRL__presc_timer1__normal 0 | ||
| 491 | #define R_TIMER_CTRL__presc_timer1__prescale 1 | ||
| 492 | #define R_TIMER_CTRL__i1__BITNR 14 | ||
| 493 | #define R_TIMER_CTRL__i1__WIDTH 1 | ||
| 494 | #define R_TIMER_CTRL__i1__clr 1 | ||
| 495 | #define R_TIMER_CTRL__i1__nop 0 | ||
| 496 | #define R_TIMER_CTRL__tm1__BITNR 12 | ||
| 497 | #define R_TIMER_CTRL__tm1__WIDTH 2 | ||
| 498 | #define R_TIMER_CTRL__tm1__stop_ld 0 | ||
| 499 | #define R_TIMER_CTRL__tm1__freeze 1 | ||
| 500 | #define R_TIMER_CTRL__tm1__run 2 | ||
| 501 | #define R_TIMER_CTRL__tm1__reserved 3 | ||
| 502 | #define R_TIMER_CTRL__clksel1__BITNR 8 | ||
| 503 | #define R_TIMER_CTRL__clksel1__WIDTH 4 | ||
| 504 | #define R_TIMER_CTRL__clksel1__c300Hz 0 | ||
| 505 | #define R_TIMER_CTRL__clksel1__c600Hz 1 | ||
| 506 | #define R_TIMER_CTRL__clksel1__c1200Hz 2 | ||
| 507 | #define R_TIMER_CTRL__clksel1__c2400Hz 3 | ||
| 508 | #define R_TIMER_CTRL__clksel1__c4800Hz 4 | ||
| 509 | #define R_TIMER_CTRL__clksel1__c9600Hz 5 | ||
| 510 | #define R_TIMER_CTRL__clksel1__c19k2Hz 6 | ||
| 511 | #define R_TIMER_CTRL__clksel1__c38k4Hz 7 | ||
| 512 | #define R_TIMER_CTRL__clksel1__c57k6Hz 8 | ||
| 513 | #define R_TIMER_CTRL__clksel1__c115k2Hz 9 | ||
| 514 | #define R_TIMER_CTRL__clksel1__c230k4Hz 10 | ||
| 515 | #define R_TIMER_CTRL__clksel1__c460k8Hz 11 | ||
| 516 | #define R_TIMER_CTRL__clksel1__c921k6Hz 12 | ||
| 517 | #define R_TIMER_CTRL__clksel1__c1843k2Hz 13 | ||
| 518 | #define R_TIMER_CTRL__clksel1__c6250kHz 14 | ||
| 519 | #define R_TIMER_CTRL__clksel1__cascade0 15 | ||
| 520 | #define R_TIMER_CTRL__presc_ext__BITNR 7 | ||
| 521 | #define R_TIMER_CTRL__presc_ext__WIDTH 1 | ||
| 522 | #define R_TIMER_CTRL__presc_ext__prescale 0 | ||
| 523 | #define R_TIMER_CTRL__presc_ext__external 1 | ||
| 524 | #define R_TIMER_CTRL__i0__BITNR 6 | ||
| 525 | #define R_TIMER_CTRL__i0__WIDTH 1 | ||
| 526 | #define R_TIMER_CTRL__i0__clr 1 | ||
| 527 | #define R_TIMER_CTRL__i0__nop 0 | ||
| 528 | #define R_TIMER_CTRL__tm0__BITNR 4 | ||
| 529 | #define R_TIMER_CTRL__tm0__WIDTH 2 | ||
| 530 | #define R_TIMER_CTRL__tm0__stop_ld 0 | ||
| 531 | #define R_TIMER_CTRL__tm0__freeze 1 | ||
| 532 | #define R_TIMER_CTRL__tm0__run 2 | ||
| 533 | #define R_TIMER_CTRL__tm0__reserved 3 | ||
| 534 | #define R_TIMER_CTRL__clksel0__BITNR 0 | ||
| 535 | #define R_TIMER_CTRL__clksel0__WIDTH 4 | ||
| 536 | #define R_TIMER_CTRL__clksel0__c300Hz 0 | ||
| 537 | #define R_TIMER_CTRL__clksel0__c600Hz 1 | ||
| 538 | #define R_TIMER_CTRL__clksel0__c1200Hz 2 | ||
| 539 | #define R_TIMER_CTRL__clksel0__c2400Hz 3 | ||
| 540 | #define R_TIMER_CTRL__clksel0__c4800Hz 4 | ||
| 541 | #define R_TIMER_CTRL__clksel0__c9600Hz 5 | ||
| 542 | #define R_TIMER_CTRL__clksel0__c19k2Hz 6 | ||
| 543 | #define R_TIMER_CTRL__clksel0__c38k4Hz 7 | ||
| 544 | #define R_TIMER_CTRL__clksel0__c57k6Hz 8 | ||
| 545 | #define R_TIMER_CTRL__clksel0__c115k2Hz 9 | ||
| 546 | #define R_TIMER_CTRL__clksel0__c230k4Hz 10 | ||
| 547 | #define R_TIMER_CTRL__clksel0__c460k8Hz 11 | ||
| 548 | #define R_TIMER_CTRL__clksel0__c921k6Hz 12 | ||
| 549 | #define R_TIMER_CTRL__clksel0__c1843k2Hz 13 | ||
| 550 | #define R_TIMER_CTRL__clksel0__c6250kHz 14 | ||
| 551 | #define R_TIMER_CTRL__clksel0__flexible 15 | ||
| 552 | |||
| 553 | #define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) | ||
| 554 | #define R_TIMER_DATA__timer1__BITNR 24 | ||
| 555 | #define R_TIMER_DATA__timer1__WIDTH 8 | ||
| 556 | #define R_TIMER_DATA__timer0__BITNR 16 | ||
| 557 | #define R_TIMER_DATA__timer0__WIDTH 8 | ||
| 558 | #define R_TIMER_DATA__clkdiv_high__BITNR 8 | ||
| 559 | #define R_TIMER_DATA__clkdiv_high__WIDTH 8 | ||
| 560 | #define R_TIMER_DATA__clkdiv_low__BITNR 0 | ||
| 561 | #define R_TIMER_DATA__clkdiv_low__WIDTH 8 | ||
| 562 | |||
| 563 | #define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) | ||
| 564 | #define R_TIMER01_DATA__count__BITNR 0 | ||
| 565 | #define R_TIMER01_DATA__count__WIDTH 16 | ||
| 566 | |||
| 567 | #define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) | ||
| 568 | #define R_TIMER0_DATA__count__BITNR 0 | ||
| 569 | #define R_TIMER0_DATA__count__WIDTH 8 | ||
| 570 | |||
| 571 | #define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) | ||
| 572 | #define R_TIMER1_DATA__count__BITNR 0 | ||
| 573 | #define R_TIMER1_DATA__count__WIDTH 8 | ||
| 574 | |||
| 575 | #define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) | ||
| 576 | #define R_WATCHDOG__key__BITNR 1 | ||
| 577 | #define R_WATCHDOG__key__WIDTH 3 | ||
| 578 | #define R_WATCHDOG__enable__BITNR 0 | ||
| 579 | #define R_WATCHDOG__enable__WIDTH 1 | ||
| 580 | #define R_WATCHDOG__enable__stop 0 | ||
| 581 | #define R_WATCHDOG__enable__start 1 | ||
| 582 | |||
| 583 | #define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) | ||
| 584 | #define R_CLOCK_PRESCALE__ser_presc__BITNR 16 | ||
| 585 | #define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 | ||
| 586 | #define R_CLOCK_PRESCALE__tim_presc__BITNR 0 | ||
| 587 | #define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 | ||
| 588 | |||
| 589 | #define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) | ||
| 590 | #define R_SERIAL_PRESCALE__ser_presc__BITNR 0 | ||
| 591 | #define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 | ||
| 592 | |||
| 593 | #define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) | ||
| 594 | #define R_TIMER_PRESCALE__tim_presc__BITNR 0 | ||
| 595 | #define R_TIMER_PRESCALE__tim_presc__WIDTH 16 | ||
| 596 | |||
| 597 | #define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) | ||
| 598 | #define R_PRESCALE_STATUS__ser_status__BITNR 16 | ||
| 599 | #define R_PRESCALE_STATUS__ser_status__WIDTH 16 | ||
| 600 | #define R_PRESCALE_STATUS__tim_status__BITNR 0 | ||
| 601 | #define R_PRESCALE_STATUS__tim_status__WIDTH 16 | ||
| 602 | |||
| 603 | #define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) | ||
| 604 | #define R_SER_PRESC_STATUS__ser_status__BITNR 0 | ||
| 605 | #define R_SER_PRESC_STATUS__ser_status__WIDTH 16 | ||
| 606 | |||
| 607 | #define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) | ||
| 608 | #define R_TIM_PRESC_STATUS__tim_status__BITNR 0 | ||
| 609 | #define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 | ||
| 610 | |||
| 611 | #define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) | ||
| 612 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 | ||
| 613 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 | ||
| 614 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 | ||
| 615 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 | ||
| 616 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 | ||
| 617 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 | ||
| 618 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 | ||
| 619 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 | ||
| 620 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 | ||
| 621 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 | ||
| 622 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 | ||
| 623 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 | ||
| 624 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 | ||
| 625 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 | ||
| 626 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 | ||
| 627 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 | ||
| 628 | #define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 | ||
| 629 | #define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 | ||
| 630 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 | ||
| 631 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 | ||
| 632 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 | ||
| 633 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 | ||
| 634 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 | ||
| 635 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 | ||
| 636 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 | ||
| 637 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 | ||
| 638 | #define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 | ||
| 639 | #define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 | ||
| 640 | #define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 | ||
| 641 | #define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 | ||
| 642 | #define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 | ||
| 643 | #define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 | ||
| 644 | #define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 | ||
| 645 | #define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 | ||
| 646 | |||
| 647 | /* | ||
| 648 | !* Shared RAM interface registers | ||
| 649 | !*/ | ||
| 650 | |||
| 651 | #define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) | ||
| 652 | #define R_SHARED_RAM_CONFIG__width__BITNR 3 | ||
| 653 | #define R_SHARED_RAM_CONFIG__width__WIDTH 1 | ||
| 654 | #define R_SHARED_RAM_CONFIG__width__byte 0 | ||
| 655 | #define R_SHARED_RAM_CONFIG__width__word 1 | ||
| 656 | #define R_SHARED_RAM_CONFIG__enable__BITNR 2 | ||
| 657 | #define R_SHARED_RAM_CONFIG__enable__WIDTH 1 | ||
| 658 | #define R_SHARED_RAM_CONFIG__enable__yes 1 | ||
| 659 | #define R_SHARED_RAM_CONFIG__enable__no 0 | ||
| 660 | #define R_SHARED_RAM_CONFIG__pint__BITNR 1 | ||
| 661 | #define R_SHARED_RAM_CONFIG__pint__WIDTH 1 | ||
| 662 | #define R_SHARED_RAM_CONFIG__pint__int 1 | ||
| 663 | #define R_SHARED_RAM_CONFIG__pint__nop 0 | ||
| 664 | #define R_SHARED_RAM_CONFIG__clri__BITNR 0 | ||
| 665 | #define R_SHARED_RAM_CONFIG__clri__WIDTH 1 | ||
| 666 | #define R_SHARED_RAM_CONFIG__clri__clr 1 | ||
| 667 | #define R_SHARED_RAM_CONFIG__clri__nop 0 | ||
| 668 | |||
| 669 | #define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) | ||
| 670 | #define R_SHARED_RAM_ADDR__base_addr__BITNR 8 | ||
| 671 | #define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 | ||
| 672 | |||
| 673 | /* | ||
| 674 | !* General config registers | ||
| 675 | !*/ | ||
| 676 | |||
| 677 | #define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) | ||
| 678 | #define R_GEN_CONFIG__par_w__BITNR 31 | ||
| 679 | #define R_GEN_CONFIG__par_w__WIDTH 1 | ||
| 680 | #define R_GEN_CONFIG__par_w__select 1 | ||
| 681 | #define R_GEN_CONFIG__par_w__disable 0 | ||
| 682 | #define R_GEN_CONFIG__usb2__BITNR 30 | ||
| 683 | #define R_GEN_CONFIG__usb2__WIDTH 1 | ||
| 684 | #define R_GEN_CONFIG__usb2__select 1 | ||
| 685 | #define R_GEN_CONFIG__usb2__disable 0 | ||
| 686 | #define R_GEN_CONFIG__usb1__BITNR 29 | ||
| 687 | #define R_GEN_CONFIG__usb1__WIDTH 1 | ||
| 688 | #define R_GEN_CONFIG__usb1__select 1 | ||
| 689 | #define R_GEN_CONFIG__usb1__disable 0 | ||
| 690 | #define R_GEN_CONFIG__g24dir__BITNR 27 | ||
| 691 | #define R_GEN_CONFIG__g24dir__WIDTH 1 | ||
| 692 | #define R_GEN_CONFIG__g24dir__in 0 | ||
| 693 | #define R_GEN_CONFIG__g24dir__out 1 | ||
| 694 | #define R_GEN_CONFIG__g16_23dir__BITNR 26 | ||
| 695 | #define R_GEN_CONFIG__g16_23dir__WIDTH 1 | ||
| 696 | #define R_GEN_CONFIG__g16_23dir__in 0 | ||
| 697 | #define R_GEN_CONFIG__g16_23dir__out 1 | ||
| 698 | #define R_GEN_CONFIG__g8_15dir__BITNR 25 | ||
| 699 | #define R_GEN_CONFIG__g8_15dir__WIDTH 1 | ||
| 700 | #define R_GEN_CONFIG__g8_15dir__in 0 | ||
| 701 | #define R_GEN_CONFIG__g8_15dir__out 1 | ||
| 702 | #define R_GEN_CONFIG__g0dir__BITNR 24 | ||
| 703 | #define R_GEN_CONFIG__g0dir__WIDTH 1 | ||
| 704 | #define R_GEN_CONFIG__g0dir__in 0 | ||
| 705 | #define R_GEN_CONFIG__g0dir__out 1 | ||
| 706 | #define R_GEN_CONFIG__dma9__BITNR 23 | ||
| 707 | #define R_GEN_CONFIG__dma9__WIDTH 1 | ||
| 708 | #define R_GEN_CONFIG__dma9__usb 0 | ||
| 709 | #define R_GEN_CONFIG__dma9__serial1 1 | ||
| 710 | #define R_GEN_CONFIG__dma8__BITNR 22 | ||
| 711 | #define R_GEN_CONFIG__dma8__WIDTH 1 | ||
| 712 | #define R_GEN_CONFIG__dma8__usb 0 | ||
| 713 | #define R_GEN_CONFIG__dma8__serial1 1 | ||
| 714 | #define R_GEN_CONFIG__dma7__BITNR 20 | ||
| 715 | #define R_GEN_CONFIG__dma7__WIDTH 2 | ||
| 716 | #define R_GEN_CONFIG__dma7__unused 0 | ||
| 717 | #define R_GEN_CONFIG__dma7__serial0 1 | ||
| 718 | #define R_GEN_CONFIG__dma7__extdma1 2 | ||
| 719 | #define R_GEN_CONFIG__dma7__intdma6 3 | ||
| 720 | #define R_GEN_CONFIG__dma6__BITNR 18 | ||
| 721 | #define R_GEN_CONFIG__dma6__WIDTH 2 | ||
| 722 | #define R_GEN_CONFIG__dma6__unused 0 | ||
| 723 | #define R_GEN_CONFIG__dma6__serial0 1 | ||
| 724 | #define R_GEN_CONFIG__dma6__extdma1 2 | ||
| 725 | #define R_GEN_CONFIG__dma6__intdma7 3 | ||
| 726 | #define R_GEN_CONFIG__dma5__BITNR 16 | ||
| 727 | #define R_GEN_CONFIG__dma5__WIDTH 2 | ||
| 728 | #define R_GEN_CONFIG__dma5__par1 0 | ||
| 729 | #define R_GEN_CONFIG__dma5__scsi1 1 | ||
| 730 | #define R_GEN_CONFIG__dma5__serial3 2 | ||
| 731 | #define R_GEN_CONFIG__dma5__extdma0 3 | ||
| 732 | #define R_GEN_CONFIG__dma4__BITNR 14 | ||
| 733 | #define R_GEN_CONFIG__dma4__WIDTH 2 | ||
| 734 | #define R_GEN_CONFIG__dma4__par1 0 | ||
| 735 | #define R_GEN_CONFIG__dma4__scsi1 1 | ||
| 736 | #define R_GEN_CONFIG__dma4__serial3 2 | ||
| 737 | #define R_GEN_CONFIG__dma4__extdma0 3 | ||
| 738 | #define R_GEN_CONFIG__dma3__BITNR 12 | ||
| 739 | #define R_GEN_CONFIG__dma3__WIDTH 2 | ||
| 740 | #define R_GEN_CONFIG__dma3__par0 0 | ||
| 741 | #define R_GEN_CONFIG__dma3__scsi0 1 | ||
| 742 | #define R_GEN_CONFIG__dma3__serial2 2 | ||
| 743 | #define R_GEN_CONFIG__dma3__ata 3 | ||
| 744 | #define R_GEN_CONFIG__dma2__BITNR 10 | ||
| 745 | #define R_GEN_CONFIG__dma2__WIDTH 2 | ||
| 746 | #define R_GEN_CONFIG__dma2__par0 0 | ||
| 747 | #define R_GEN_CONFIG__dma2__scsi0 1 | ||
| 748 | #define R_GEN_CONFIG__dma2__serial2 2 | ||
| 749 | #define R_GEN_CONFIG__dma2__ata 3 | ||
| 750 | #define R_GEN_CONFIG__mio_w__BITNR 9 | ||
| 751 | #define R_GEN_CONFIG__mio_w__WIDTH 1 | ||
| 752 | #define R_GEN_CONFIG__mio_w__select 1 | ||
| 753 | #define R_GEN_CONFIG__mio_w__disable 0 | ||
| 754 | #define R_GEN_CONFIG__ser3__BITNR 8 | ||
| 755 | #define R_GEN_CONFIG__ser3__WIDTH 1 | ||
| 756 | #define R_GEN_CONFIG__ser3__select 1 | ||
| 757 | #define R_GEN_CONFIG__ser3__disable 0 | ||
| 758 | #define R_GEN_CONFIG__par1__BITNR 7 | ||
| 759 | #define R_GEN_CONFIG__par1__WIDTH 1 | ||
| 760 | #define R_GEN_CONFIG__par1__select 1 | ||
| 761 | #define R_GEN_CONFIG__par1__disable 0 | ||
| 762 | #define R_GEN_CONFIG__scsi0w__BITNR 6 | ||
| 763 | #define R_GEN_CONFIG__scsi0w__WIDTH 1 | ||
| 764 | #define R_GEN_CONFIG__scsi0w__select 1 | ||
| 765 | #define R_GEN_CONFIG__scsi0w__disable 0 | ||
| 766 | #define R_GEN_CONFIG__scsi1__BITNR 5 | ||
| 767 | #define R_GEN_CONFIG__scsi1__WIDTH 1 | ||
| 768 | #define R_GEN_CONFIG__scsi1__select 1 | ||
| 769 | #define R_GEN_CONFIG__scsi1__disable 0 | ||
| 770 | #define R_GEN_CONFIG__mio__BITNR 4 | ||
| 771 | #define R_GEN_CONFIG__mio__WIDTH 1 | ||
| 772 | #define R_GEN_CONFIG__mio__select 1 | ||
| 773 | #define R_GEN_CONFIG__mio__disable 0 | ||
| 774 | #define R_GEN_CONFIG__ser2__BITNR 3 | ||
| 775 | #define R_GEN_CONFIG__ser2__WIDTH 1 | ||
| 776 | #define R_GEN_CONFIG__ser2__select 1 | ||
| 777 | #define R_GEN_CONFIG__ser2__disable 0 | ||
| 778 | #define R_GEN_CONFIG__par0__BITNR 2 | ||
| 779 | #define R_GEN_CONFIG__par0__WIDTH 1 | ||
| 780 | #define R_GEN_CONFIG__par0__select 1 | ||
| 781 | #define R_GEN_CONFIG__par0__disable 0 | ||
| 782 | #define R_GEN_CONFIG__ata__BITNR 1 | ||
| 783 | #define R_GEN_CONFIG__ata__WIDTH 1 | ||
| 784 | #define R_GEN_CONFIG__ata__select 1 | ||
| 785 | #define R_GEN_CONFIG__ata__disable 0 | ||
| 786 | #define R_GEN_CONFIG__scsi0__BITNR 0 | ||
| 787 | #define R_GEN_CONFIG__scsi0__WIDTH 1 | ||
| 788 | #define R_GEN_CONFIG__scsi0__select 1 | ||
| 789 | #define R_GEN_CONFIG__scsi0__disable 0 | ||
| 790 | |||
| 791 | #define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) | ||
| 792 | #define R_GEN_CONFIG_II__sermode3__BITNR 6 | ||
| 793 | #define R_GEN_CONFIG_II__sermode3__WIDTH 1 | ||
| 794 | #define R_GEN_CONFIG_II__sermode3__async 0 | ||
| 795 | #define R_GEN_CONFIG_II__sermode3__sync 1 | ||
| 796 | #define R_GEN_CONFIG_II__sermode1__BITNR 4 | ||
| 797 | #define R_GEN_CONFIG_II__sermode1__WIDTH 1 | ||
| 798 | #define R_GEN_CONFIG_II__sermode1__async 0 | ||
| 799 | #define R_GEN_CONFIG_II__sermode1__sync 1 | ||
| 800 | #define R_GEN_CONFIG_II__ext_clk__BITNR 2 | ||
| 801 | #define R_GEN_CONFIG_II__ext_clk__WIDTH 1 | ||
| 802 | #define R_GEN_CONFIG_II__ext_clk__select 1 | ||
| 803 | #define R_GEN_CONFIG_II__ext_clk__disable 0 | ||
| 804 | #define R_GEN_CONFIG_II__ser2__BITNR 1 | ||
| 805 | #define R_GEN_CONFIG_II__ser2__WIDTH 1 | ||
| 806 | #define R_GEN_CONFIG_II__ser2__select 1 | ||
| 807 | #define R_GEN_CONFIG_II__ser2__disable 0 | ||
| 808 | #define R_GEN_CONFIG_II__ser3__BITNR 0 | ||
| 809 | #define R_GEN_CONFIG_II__ser3__WIDTH 1 | ||
| 810 | #define R_GEN_CONFIG_II__ser3__select 1 | ||
| 811 | #define R_GEN_CONFIG_II__ser3__disable 0 | ||
| 812 | |||
| 813 | #define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) | ||
| 814 | #define R_PORT_G_DATA__data__BITNR 0 | ||
| 815 | #define R_PORT_G_DATA__data__WIDTH 32 | ||
| 816 | |||
| 817 | /* | ||
| 818 | !* General port configuration registers | ||
| 819 | !*/ | ||
| 820 | |||
| 821 | #define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) | ||
| 822 | #define R_PORT_PA_SET__dir7__BITNR 15 | ||
| 823 | #define R_PORT_PA_SET__dir7__WIDTH 1 | ||
| 824 | #define R_PORT_PA_SET__dir7__input 0 | ||
| 825 | #define R_PORT_PA_SET__dir7__output 1 | ||
| 826 | #define R_PORT_PA_SET__dir6__BITNR 14 | ||
| 827 | #define R_PORT_PA_SET__dir6__WIDTH 1 | ||
| 828 | #define R_PORT_PA_SET__dir6__input 0 | ||
| 829 | #define R_PORT_PA_SET__dir6__output 1 | ||
| 830 | #define R_PORT_PA_SET__dir5__BITNR 13 | ||
| 831 | #define R_PORT_PA_SET__dir5__WIDTH 1 | ||
| 832 | #define R_PORT_PA_SET__dir5__input 0 | ||
| 833 | #define R_PORT_PA_SET__dir5__output 1 | ||
| 834 | #define R_PORT_PA_SET__dir4__BITNR 12 | ||
| 835 | #define R_PORT_PA_SET__dir4__WIDTH 1 | ||
| 836 | #define R_PORT_PA_SET__dir4__input 0 | ||
| 837 | #define R_PORT_PA_SET__dir4__output 1 | ||
| 838 | #define R_PORT_PA_SET__dir3__BITNR 11 | ||
| 839 | #define R_PORT_PA_SET__dir3__WIDTH 1 | ||
| 840 | #define R_PORT_PA_SET__dir3__input 0 | ||
| 841 | #define R_PORT_PA_SET__dir3__output 1 | ||
| 842 | #define R_PORT_PA_SET__dir2__BITNR 10 | ||
| 843 | #define R_PORT_PA_SET__dir2__WIDTH 1 | ||
| 844 | #define R_PORT_PA_SET__dir2__input 0 | ||
| 845 | #define R_PORT_PA_SET__dir2__output 1 | ||
| 846 | #define R_PORT_PA_SET__dir1__BITNR 9 | ||
| 847 | #define R_PORT_PA_SET__dir1__WIDTH 1 | ||
| 848 | #define R_PORT_PA_SET__dir1__input 0 | ||
| 849 | #define R_PORT_PA_SET__dir1__output 1 | ||
| 850 | #define R_PORT_PA_SET__dir0__BITNR 8 | ||
| 851 | #define R_PORT_PA_SET__dir0__WIDTH 1 | ||
| 852 | #define R_PORT_PA_SET__dir0__input 0 | ||
| 853 | #define R_PORT_PA_SET__dir0__output 1 | ||
| 854 | #define R_PORT_PA_SET__data_out__BITNR 0 | ||
| 855 | #define R_PORT_PA_SET__data_out__WIDTH 8 | ||
| 856 | |||
| 857 | #define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) | ||
| 858 | #define R_PORT_PA_DATA__data_out__BITNR 0 | ||
| 859 | #define R_PORT_PA_DATA__data_out__WIDTH 8 | ||
| 860 | |||
| 861 | #define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) | ||
| 862 | #define R_PORT_PA_DIR__dir7__BITNR 7 | ||
| 863 | #define R_PORT_PA_DIR__dir7__WIDTH 1 | ||
| 864 | #define R_PORT_PA_DIR__dir7__input 0 | ||
| 865 | #define R_PORT_PA_DIR__dir7__output 1 | ||
| 866 | #define R_PORT_PA_DIR__dir6__BITNR 6 | ||
| 867 | #define R_PORT_PA_DIR__dir6__WIDTH 1 | ||
| 868 | #define R_PORT_PA_DIR__dir6__input 0 | ||
| 869 | #define R_PORT_PA_DIR__dir6__output 1 | ||
| 870 | #define R_PORT_PA_DIR__dir5__BITNR 5 | ||
| 871 | #define R_PORT_PA_DIR__dir5__WIDTH 1 | ||
| 872 | #define R_PORT_PA_DIR__dir5__input 0 | ||
| 873 | #define R_PORT_PA_DIR__dir5__output 1 | ||
| 874 | #define R_PORT_PA_DIR__dir4__BITNR 4 | ||
| 875 | #define R_PORT_PA_DIR__dir4__WIDTH 1 | ||
| 876 | #define R_PORT_PA_DIR__dir4__input 0 | ||
| 877 | #define R_PORT_PA_DIR__dir4__output 1 | ||
| 878 | #define R_PORT_PA_DIR__dir3__BITNR 3 | ||
| 879 | #define R_PORT_PA_DIR__dir3__WIDTH 1 | ||
| 880 | #define R_PORT_PA_DIR__dir3__input 0 | ||
| 881 | #define R_PORT_PA_DIR__dir3__output 1 | ||
| 882 | #define R_PORT_PA_DIR__dir2__BITNR 2 | ||
| 883 | #define R_PORT_PA_DIR__dir2__WIDTH 1 | ||
| 884 | #define R_PORT_PA_DIR__dir2__input 0 | ||
| 885 | #define R_PORT_PA_DIR__dir2__output 1 | ||
| 886 | #define R_PORT_PA_DIR__dir1__BITNR 1 | ||
| 887 | #define R_PORT_PA_DIR__dir1__WIDTH 1 | ||
| 888 | #define R_PORT_PA_DIR__dir1__input 0 | ||
| 889 | #define R_PORT_PA_DIR__dir1__output 1 | ||
| 890 | #define R_PORT_PA_DIR__dir0__BITNR 0 | ||
| 891 | #define R_PORT_PA_DIR__dir0__WIDTH 1 | ||
| 892 | #define R_PORT_PA_DIR__dir0__input 0 | ||
| 893 | #define R_PORT_PA_DIR__dir0__output 1 | ||
| 894 | |||
| 895 | #define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) | ||
| 896 | #define R_PORT_PA_READ__data_in__BITNR 0 | ||
| 897 | #define R_PORT_PA_READ__data_in__WIDTH 8 | ||
| 898 | |||
| 899 | #define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) | ||
| 900 | #define R_PORT_PB_SET__syncser3__BITNR 29 | ||
| 901 | #define R_PORT_PB_SET__syncser3__WIDTH 1 | ||
| 902 | #define R_PORT_PB_SET__syncser3__port_cs 0 | ||
| 903 | #define R_PORT_PB_SET__syncser3__ss3extra 1 | ||
| 904 | #define R_PORT_PB_SET__syncser1__BITNR 28 | ||
| 905 | #define R_PORT_PB_SET__syncser1__WIDTH 1 | ||
| 906 | #define R_PORT_PB_SET__syncser1__port_cs 0 | ||
| 907 | #define R_PORT_PB_SET__syncser1__ss1extra 1 | ||
| 908 | #define R_PORT_PB_SET__i2c_en__BITNR 27 | ||
| 909 | #define R_PORT_PB_SET__i2c_en__WIDTH 1 | ||
| 910 | #define R_PORT_PB_SET__i2c_en__off 0 | ||
| 911 | #define R_PORT_PB_SET__i2c_en__on 1 | ||
| 912 | #define R_PORT_PB_SET__i2c_d__BITNR 26 | ||
| 913 | #define R_PORT_PB_SET__i2c_d__WIDTH 1 | ||
| 914 | #define R_PORT_PB_SET__i2c_clk__BITNR 25 | ||
| 915 | #define R_PORT_PB_SET__i2c_clk__WIDTH 1 | ||
| 916 | #define R_PORT_PB_SET__i2c_oe___BITNR 24 | ||
| 917 | #define R_PORT_PB_SET__i2c_oe___WIDTH 1 | ||
| 918 | #define R_PORT_PB_SET__i2c_oe___enable 0 | ||
| 919 | #define R_PORT_PB_SET__i2c_oe___disable 1 | ||
| 920 | #define R_PORT_PB_SET__cs7__BITNR 23 | ||
| 921 | #define R_PORT_PB_SET__cs7__WIDTH 1 | ||
| 922 | #define R_PORT_PB_SET__cs7__port 0 | ||
| 923 | #define R_PORT_PB_SET__cs7__cs 1 | ||
| 924 | #define R_PORT_PB_SET__cs6__BITNR 22 | ||
| 925 | #define R_PORT_PB_SET__cs6__WIDTH 1 | ||
| 926 | #define R_PORT_PB_SET__cs6__port 0 | ||
| 927 | #define R_PORT_PB_SET__cs6__cs 1 | ||
| 928 | #define R_PORT_PB_SET__cs5__BITNR 21 | ||
| 929 | #define R_PORT_PB_SET__cs5__WIDTH 1 | ||
| 930 | #define R_PORT_PB_SET__cs5__port 0 | ||
| 931 | #define R_PORT_PB_SET__cs5__cs 1 | ||
| 932 | #define R_PORT_PB_SET__cs4__BITNR 20 | ||
| 933 | #define R_PORT_PB_SET__cs4__WIDTH 1 | ||
| 934 | #define R_PORT_PB_SET__cs4__port 0 | ||
| 935 | #define R_PORT_PB_SET__cs4__cs 1 | ||
| 936 | #define R_PORT_PB_SET__cs3__BITNR 19 | ||
| 937 | #define R_PORT_PB_SET__cs3__WIDTH 1 | ||
| 938 | #define R_PORT_PB_SET__cs3__port 0 | ||
| 939 | #define R_PORT_PB_SET__cs3__cs 1 | ||
| 940 | #define R_PORT_PB_SET__cs2__BITNR 18 | ||
| 941 | #define R_PORT_PB_SET__cs2__WIDTH 1 | ||
| 942 | #define R_PORT_PB_SET__cs2__port 0 | ||
| 943 | #define R_PORT_PB_SET__cs2__cs 1 | ||
| 944 | #define R_PORT_PB_SET__scsi1__BITNR 17 | ||
| 945 | #define R_PORT_PB_SET__scsi1__WIDTH 1 | ||
| 946 | #define R_PORT_PB_SET__scsi1__port_cs 0 | ||
| 947 | #define R_PORT_PB_SET__scsi1__enph 1 | ||
| 948 | #define R_PORT_PB_SET__scsi0__BITNR 16 | ||
| 949 | #define R_PORT_PB_SET__scsi0__WIDTH 1 | ||
| 950 | #define R_PORT_PB_SET__scsi0__port_cs 0 | ||
| 951 | #define R_PORT_PB_SET__scsi0__enph 1 | ||
| 952 | #define R_PORT_PB_SET__dir7__BITNR 15 | ||
| 953 | #define R_PORT_PB_SET__dir7__WIDTH 1 | ||
| 954 | #define R_PORT_PB_SET__dir7__input 0 | ||
| 955 | #define R_PORT_PB_SET__dir7__output 1 | ||
| 956 | #define R_PORT_PB_SET__dir6__BITNR 14 | ||
| 957 | #define R_PORT_PB_SET__dir6__WIDTH 1 | ||
| 958 | #define R_PORT_PB_SET__dir6__input 0 | ||
| 959 | #define R_PORT_PB_SET__dir6__output 1 | ||
| 960 | #define R_PORT_PB_SET__dir5__BITNR 13 | ||
| 961 | #define R_PORT_PB_SET__dir5__WIDTH 1 | ||
| 962 | #define R_PORT_PB_SET__dir5__input 0 | ||
| 963 | #define R_PORT_PB_SET__dir5__output 1 | ||
| 964 | #define R_PORT_PB_SET__dir4__BITNR 12 | ||
| 965 | #define R_PORT_PB_SET__dir4__WIDTH 1 | ||
| 966 | #define R_PORT_PB_SET__dir4__input 0 | ||
| 967 | #define R_PORT_PB_SET__dir4__output 1 | ||
| 968 | #define R_PORT_PB_SET__dir3__BITNR 11 | ||
| 969 | #define R_PORT_PB_SET__dir3__WIDTH 1 | ||
| 970 | #define R_PORT_PB_SET__dir3__input 0 | ||
| 971 | #define R_PORT_PB_SET__dir3__output 1 | ||
| 972 | #define R_PORT_PB_SET__dir2__BITNR 10 | ||
| 973 | #define R_PORT_PB_SET__dir2__WIDTH 1 | ||
| 974 | #define R_PORT_PB_SET__dir2__input 0 | ||
| 975 | #define R_PORT_PB_SET__dir2__output 1 | ||
| 976 | #define R_PORT_PB_SET__dir1__BITNR 9 | ||
| 977 | #define R_PORT_PB_SET__dir1__WIDTH 1 | ||
| 978 | #define R_PORT_PB_SET__dir1__input 0 | ||
| 979 | #define R_PORT_PB_SET__dir1__output 1 | ||
| 980 | #define R_PORT_PB_SET__dir0__BITNR 8 | ||
| 981 | #define R_PORT_PB_SET__dir0__WIDTH 1 | ||
| 982 | #define R_PORT_PB_SET__dir0__input 0 | ||
| 983 | #define R_PORT_PB_SET__dir0__output 1 | ||
| 984 | #define R_PORT_PB_SET__data_out__BITNR 0 | ||
| 985 | #define R_PORT_PB_SET__data_out__WIDTH 8 | ||
| 986 | |||
| 987 | #define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) | ||
| 988 | #define R_PORT_PB_DATA__data_out__BITNR 0 | ||
| 989 | #define R_PORT_PB_DATA__data_out__WIDTH 8 | ||
| 990 | |||
| 991 | #define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) | ||
| 992 | #define R_PORT_PB_DIR__dir7__BITNR 7 | ||
| 993 | #define R_PORT_PB_DIR__dir7__WIDTH 1 | ||
| 994 | #define R_PORT_PB_DIR__dir7__input 0 | ||
| 995 | #define R_PORT_PB_DIR__dir7__output 1 | ||
| 996 | #define R_PORT_PB_DIR__dir6__BITNR 6 | ||
| 997 | #define R_PORT_PB_DIR__dir6__WIDTH 1 | ||
| 998 | #define R_PORT_PB_DIR__dir6__input 0 | ||
| 999 | #define R_PORT_PB_DIR__dir6__output 1 | ||
| 1000 | #define R_PORT_PB_DIR__dir5__BITNR 5 | ||
| 1001 | #define R_PORT_PB_DIR__dir5__WIDTH 1 | ||
| 1002 | #define R_PORT_PB_DIR__dir5__input 0 | ||
| 1003 | #define R_PORT_PB_DIR__dir5__output 1 | ||
| 1004 | #define R_PORT_PB_DIR__dir4__BITNR 4 | ||
| 1005 | #define R_PORT_PB_DIR__dir4__WIDTH 1 | ||
| 1006 | #define R_PORT_PB_DIR__dir4__input 0 | ||
| 1007 | #define R_PORT_PB_DIR__dir4__output 1 | ||
| 1008 | #define R_PORT_PB_DIR__dir3__BITNR 3 | ||
| 1009 | #define R_PORT_PB_DIR__dir3__WIDTH 1 | ||
| 1010 | #define R_PORT_PB_DIR__dir3__input 0 | ||
| 1011 | #define R_PORT_PB_DIR__dir3__output 1 | ||
| 1012 | #define R_PORT_PB_DIR__dir2__BITNR 2 | ||
| 1013 | #define R_PORT_PB_DIR__dir2__WIDTH 1 | ||
| 1014 | #define R_PORT_PB_DIR__dir2__input 0 | ||
| 1015 | #define R_PORT_PB_DIR__dir2__output 1 | ||
| 1016 | #define R_PORT_PB_DIR__dir1__BITNR 1 | ||
| 1017 | #define R_PORT_PB_DIR__dir1__WIDTH 1 | ||
| 1018 | #define R_PORT_PB_DIR__dir1__input 0 | ||
| 1019 | #define R_PORT_PB_DIR__dir1__output 1 | ||
| 1020 | #define R_PORT_PB_DIR__dir0__BITNR 0 | ||
| 1021 | #define R_PORT_PB_DIR__dir0__WIDTH 1 | ||
| 1022 | #define R_PORT_PB_DIR__dir0__input 0 | ||
| 1023 | #define R_PORT_PB_DIR__dir0__output 1 | ||
| 1024 | |||
| 1025 | #define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) | ||
| 1026 | #define R_PORT_PB_CONFIG__cs7__BITNR 7 | ||
| 1027 | #define R_PORT_PB_CONFIG__cs7__WIDTH 1 | ||
| 1028 | #define R_PORT_PB_CONFIG__cs7__port 0 | ||
| 1029 | #define R_PORT_PB_CONFIG__cs7__cs 1 | ||
| 1030 | #define R_PORT_PB_CONFIG__cs6__BITNR 6 | ||
| 1031 | #define R_PORT_PB_CONFIG__cs6__WIDTH 1 | ||
| 1032 | #define R_PORT_PB_CONFIG__cs6__port 0 | ||
| 1033 | #define R_PORT_PB_CONFIG__cs6__cs 1 | ||
| 1034 | #define R_PORT_PB_CONFIG__cs5__BITNR 5 | ||
| 1035 | #define R_PORT_PB_CONFIG__cs5__WIDTH 1 | ||
| 1036 | #define R_PORT_PB_CONFIG__cs5__port 0 | ||
| 1037 | #define R_PORT_PB_CONFIG__cs5__cs 1 | ||
| 1038 | #define R_PORT_PB_CONFIG__cs4__BITNR 4 | ||
| 1039 | #define R_PORT_PB_CONFIG__cs4__WIDTH 1 | ||
| 1040 | #define R_PORT_PB_CONFIG__cs4__port 0 | ||
| 1041 | #define R_PORT_PB_CONFIG__cs4__cs 1 | ||
| 1042 | #define R_PORT_PB_CONFIG__cs3__BITNR 3 | ||
| 1043 | #define R_PORT_PB_CONFIG__cs3__WIDTH 1 | ||
| 1044 | #define R_PORT_PB_CONFIG__cs3__port 0 | ||
| 1045 | #define R_PORT_PB_CONFIG__cs3__cs 1 | ||
| 1046 | #define R_PORT_PB_CONFIG__cs2__BITNR 2 | ||
| 1047 | #define R_PORT_PB_CONFIG__cs2__WIDTH 1 | ||
| 1048 | #define R_PORT_PB_CONFIG__cs2__port 0 | ||
| 1049 | #define R_PORT_PB_CONFIG__cs2__cs 1 | ||
| 1050 | #define R_PORT_PB_CONFIG__scsi1__BITNR 1 | ||
| 1051 | #define R_PORT_PB_CONFIG__scsi1__WIDTH 1 | ||
| 1052 | #define R_PORT_PB_CONFIG__scsi1__port_cs 0 | ||
| 1053 | #define R_PORT_PB_CONFIG__scsi1__enph 1 | ||
| 1054 | #define R_PORT_PB_CONFIG__scsi0__BITNR 0 | ||
| 1055 | #define R_PORT_PB_CONFIG__scsi0__WIDTH 1 | ||
| 1056 | #define R_PORT_PB_CONFIG__scsi0__port_cs 0 | ||
| 1057 | #define R_PORT_PB_CONFIG__scsi0__enph 1 | ||
| 1058 | |||
| 1059 | #define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) | ||
| 1060 | #define R_PORT_PB_I2C__syncser3__BITNR 5 | ||
| 1061 | #define R_PORT_PB_I2C__syncser3__WIDTH 1 | ||
| 1062 | #define R_PORT_PB_I2C__syncser3__port_cs 0 | ||
| 1063 | #define R_PORT_PB_I2C__syncser3__ss3extra 1 | ||
| 1064 | #define R_PORT_PB_I2C__syncser1__BITNR 4 | ||
| 1065 | #define R_PORT_PB_I2C__syncser1__WIDTH 1 | ||
| 1066 | #define R_PORT_PB_I2C__syncser1__port_cs 0 | ||
| 1067 | #define R_PORT_PB_I2C__syncser1__ss1extra 1 | ||
| 1068 | #define R_PORT_PB_I2C__i2c_en__BITNR 3 | ||
| 1069 | #define R_PORT_PB_I2C__i2c_en__WIDTH 1 | ||
| 1070 | #define R_PORT_PB_I2C__i2c_en__off 0 | ||
| 1071 | #define R_PORT_PB_I2C__i2c_en__on 1 | ||
| 1072 | #define R_PORT_PB_I2C__i2c_d__BITNR 2 | ||
| 1073 | #define R_PORT_PB_I2C__i2c_d__WIDTH 1 | ||
| 1074 | #define R_PORT_PB_I2C__i2c_clk__BITNR 1 | ||
| 1075 | #define R_PORT_PB_I2C__i2c_clk__WIDTH 1 | ||
| 1076 | #define R_PORT_PB_I2C__i2c_oe___BITNR 0 | ||
| 1077 | #define R_PORT_PB_I2C__i2c_oe___WIDTH 1 | ||
| 1078 | #define R_PORT_PB_I2C__i2c_oe___enable 0 | ||
| 1079 | #define R_PORT_PB_I2C__i2c_oe___disable 1 | ||
| 1080 | |||
| 1081 | #define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) | ||
| 1082 | #define R_PORT_PB_READ__data_in__BITNR 0 | ||
| 1083 | #define R_PORT_PB_READ__data_in__WIDTH 8 | ||
| 1084 | |||
| 1085 | /* | ||
| 1086 | !* Serial port registers | ||
| 1087 | !*/ | ||
| 1088 | |||
| 1089 | #define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) | ||
| 1090 | #define R_SERIAL0_CTRL__tr_baud__BITNR 28 | ||
| 1091 | #define R_SERIAL0_CTRL__tr_baud__WIDTH 4 | ||
| 1092 | #define R_SERIAL0_CTRL__tr_baud__c300Hz 0 | ||
| 1093 | #define R_SERIAL0_CTRL__tr_baud__c600Hz 1 | ||
| 1094 | #define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 | ||
| 1095 | #define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 | ||
| 1096 | #define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 | ||
| 1097 | #define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 | ||
| 1098 | #define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 | ||
| 1099 | #define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 | ||
| 1100 | #define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 | ||
| 1101 | #define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 | ||
| 1102 | #define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 | ||
| 1103 | #define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 | ||
| 1104 | #define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 | ||
| 1105 | #define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 | ||
| 1106 | #define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 | ||
| 1107 | #define R_SERIAL0_CTRL__tr_baud__reserved 15 | ||
| 1108 | #define R_SERIAL0_CTRL__rec_baud__BITNR 24 | ||
| 1109 | #define R_SERIAL0_CTRL__rec_baud__WIDTH 4 | ||
| 1110 | #define R_SERIAL0_CTRL__rec_baud__c300Hz 0 | ||
| 1111 | #define R_SERIAL0_CTRL__rec_baud__c600Hz 1 | ||
| 1112 | #define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 | ||
| 1113 | #define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 | ||
| 1114 | #define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 | ||
| 1115 | #define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 | ||
| 1116 | #define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 | ||
| 1117 | #define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 | ||
| 1118 | #define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 | ||
| 1119 | #define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 | ||
| 1120 | #define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 | ||
| 1121 | #define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 | ||
| 1122 | #define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 | ||
| 1123 | #define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 | ||
| 1124 | #define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 | ||
| 1125 | #define R_SERIAL0_CTRL__rec_baud__reserved 15 | ||
| 1126 | #define R_SERIAL0_CTRL__dma_err__BITNR 23 | ||
| 1127 | #define R_SERIAL0_CTRL__dma_err__WIDTH 1 | ||
| 1128 | #define R_SERIAL0_CTRL__dma_err__stop 0 | ||
| 1129 | #define R_SERIAL0_CTRL__dma_err__ignore 1 | ||
| 1130 | #define R_SERIAL0_CTRL__rec_enable__BITNR 22 | ||
| 1131 | #define R_SERIAL0_CTRL__rec_enable__WIDTH 1 | ||
| 1132 | #define R_SERIAL0_CTRL__rec_enable__disable 0 | ||
| 1133 | #define R_SERIAL0_CTRL__rec_enable__enable 1 | ||
| 1134 | #define R_SERIAL0_CTRL__rts___BITNR 21 | ||
| 1135 | #define R_SERIAL0_CTRL__rts___WIDTH 1 | ||
| 1136 | #define R_SERIAL0_CTRL__rts___active 0 | ||
| 1137 | #define R_SERIAL0_CTRL__rts___inactive 1 | ||
| 1138 | #define R_SERIAL0_CTRL__sampling__BITNR 20 | ||
| 1139 | #define R_SERIAL0_CTRL__sampling__WIDTH 1 | ||
| 1140 | #define R_SERIAL0_CTRL__sampling__middle 0 | ||
| 1141 | #define R_SERIAL0_CTRL__sampling__majority 1 | ||
| 1142 | #define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 | ||
| 1143 | #define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 | ||
| 1144 | #define R_SERIAL0_CTRL__rec_stick_par__normal 0 | ||
| 1145 | #define R_SERIAL0_CTRL__rec_stick_par__stick 1 | ||
| 1146 | #define R_SERIAL0_CTRL__rec_par__BITNR 18 | ||
| 1147 | #define R_SERIAL0_CTRL__rec_par__WIDTH 1 | ||
| 1148 | #define R_SERIAL0_CTRL__rec_par__even 0 | ||
| 1149 | #define R_SERIAL0_CTRL__rec_par__odd 1 | ||
| 1150 | #define R_SERIAL0_CTRL__rec_par_en__BITNR 17 | ||
| 1151 | #define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 | ||
| 1152 | #define R_SERIAL0_CTRL__rec_par_en__disable 0 | ||
| 1153 | #define R_SERIAL0_CTRL__rec_par_en__enable 1 | ||
| 1154 | #define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 | ||
| 1155 | #define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 | ||
| 1156 | #define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1157 | #define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1158 | #define R_SERIAL0_CTRL__txd__BITNR 15 | ||
| 1159 | #define R_SERIAL0_CTRL__txd__WIDTH 1 | ||
| 1160 | #define R_SERIAL0_CTRL__tr_enable__BITNR 14 | ||
| 1161 | #define R_SERIAL0_CTRL__tr_enable__WIDTH 1 | ||
| 1162 | #define R_SERIAL0_CTRL__tr_enable__disable 0 | ||
| 1163 | #define R_SERIAL0_CTRL__tr_enable__enable 1 | ||
| 1164 | #define R_SERIAL0_CTRL__auto_cts__BITNR 13 | ||
| 1165 | #define R_SERIAL0_CTRL__auto_cts__WIDTH 1 | ||
| 1166 | #define R_SERIAL0_CTRL__auto_cts__disabled 0 | ||
| 1167 | #define R_SERIAL0_CTRL__auto_cts__active 1 | ||
| 1168 | #define R_SERIAL0_CTRL__stop_bits__BITNR 12 | ||
| 1169 | #define R_SERIAL0_CTRL__stop_bits__WIDTH 1 | ||
| 1170 | #define R_SERIAL0_CTRL__stop_bits__one_bit 0 | ||
| 1171 | #define R_SERIAL0_CTRL__stop_bits__two_bits 1 | ||
| 1172 | #define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 | ||
| 1173 | #define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 | ||
| 1174 | #define R_SERIAL0_CTRL__tr_stick_par__normal 0 | ||
| 1175 | #define R_SERIAL0_CTRL__tr_stick_par__stick 1 | ||
| 1176 | #define R_SERIAL0_CTRL__tr_par__BITNR 10 | ||
| 1177 | #define R_SERIAL0_CTRL__tr_par__WIDTH 1 | ||
| 1178 | #define R_SERIAL0_CTRL__tr_par__even 0 | ||
| 1179 | #define R_SERIAL0_CTRL__tr_par__odd 1 | ||
| 1180 | #define R_SERIAL0_CTRL__tr_par_en__BITNR 9 | ||
| 1181 | #define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 | ||
| 1182 | #define R_SERIAL0_CTRL__tr_par_en__disable 0 | ||
| 1183 | #define R_SERIAL0_CTRL__tr_par_en__enable 1 | ||
| 1184 | #define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 | ||
| 1185 | #define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 | ||
| 1186 | #define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1187 | #define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1188 | #define R_SERIAL0_CTRL__data_out__BITNR 0 | ||
| 1189 | #define R_SERIAL0_CTRL__data_out__WIDTH 8 | ||
| 1190 | |||
| 1191 | #define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) | ||
| 1192 | #define R_SERIAL0_BAUD__tr_baud__BITNR 4 | ||
| 1193 | #define R_SERIAL0_BAUD__tr_baud__WIDTH 4 | ||
| 1194 | #define R_SERIAL0_BAUD__tr_baud__c300Hz 0 | ||
| 1195 | #define R_SERIAL0_BAUD__tr_baud__c600Hz 1 | ||
| 1196 | #define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 | ||
| 1197 | #define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 | ||
| 1198 | #define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 | ||
| 1199 | #define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 | ||
| 1200 | #define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 | ||
| 1201 | #define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 | ||
| 1202 | #define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 | ||
| 1203 | #define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 | ||
| 1204 | #define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 | ||
| 1205 | #define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 | ||
| 1206 | #define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 | ||
| 1207 | #define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 | ||
| 1208 | #define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 | ||
| 1209 | #define R_SERIAL0_BAUD__tr_baud__reserved 15 | ||
| 1210 | #define R_SERIAL0_BAUD__rec_baud__BITNR 0 | ||
| 1211 | #define R_SERIAL0_BAUD__rec_baud__WIDTH 4 | ||
| 1212 | #define R_SERIAL0_BAUD__rec_baud__c300Hz 0 | ||
| 1213 | #define R_SERIAL0_BAUD__rec_baud__c600Hz 1 | ||
| 1214 | #define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 | ||
| 1215 | #define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 | ||
| 1216 | #define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 | ||
| 1217 | #define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 | ||
| 1218 | #define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 | ||
| 1219 | #define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 | ||
| 1220 | #define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 | ||
| 1221 | #define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 | ||
| 1222 | #define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 | ||
| 1223 | #define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 | ||
| 1224 | #define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 | ||
| 1225 | #define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 | ||
| 1226 | #define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 | ||
| 1227 | #define R_SERIAL0_BAUD__rec_baud__reserved 15 | ||
| 1228 | |||
| 1229 | #define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) | ||
| 1230 | #define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 | ||
| 1231 | #define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 | ||
| 1232 | #define R_SERIAL0_REC_CTRL__dma_err__stop 0 | ||
| 1233 | #define R_SERIAL0_REC_CTRL__dma_err__ignore 1 | ||
| 1234 | #define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 | ||
| 1235 | #define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 | ||
| 1236 | #define R_SERIAL0_REC_CTRL__rec_enable__disable 0 | ||
| 1237 | #define R_SERIAL0_REC_CTRL__rec_enable__enable 1 | ||
| 1238 | #define R_SERIAL0_REC_CTRL__rts___BITNR 5 | ||
| 1239 | #define R_SERIAL0_REC_CTRL__rts___WIDTH 1 | ||
| 1240 | #define R_SERIAL0_REC_CTRL__rts___active 0 | ||
| 1241 | #define R_SERIAL0_REC_CTRL__rts___inactive 1 | ||
| 1242 | #define R_SERIAL0_REC_CTRL__sampling__BITNR 4 | ||
| 1243 | #define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 | ||
| 1244 | #define R_SERIAL0_REC_CTRL__sampling__middle 0 | ||
| 1245 | #define R_SERIAL0_REC_CTRL__sampling__majority 1 | ||
| 1246 | #define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 | ||
| 1247 | #define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 | ||
| 1248 | #define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 | ||
| 1249 | #define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 | ||
| 1250 | #define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 | ||
| 1251 | #define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 | ||
| 1252 | #define R_SERIAL0_REC_CTRL__rec_par__even 0 | ||
| 1253 | #define R_SERIAL0_REC_CTRL__rec_par__odd 1 | ||
| 1254 | #define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 | ||
| 1255 | #define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 | ||
| 1256 | #define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 | ||
| 1257 | #define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 | ||
| 1258 | #define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 | ||
| 1259 | #define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 | ||
| 1260 | #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1261 | #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1262 | |||
| 1263 | #define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) | ||
| 1264 | #define R_SERIAL0_TR_CTRL__txd__BITNR 7 | ||
| 1265 | #define R_SERIAL0_TR_CTRL__txd__WIDTH 1 | ||
| 1266 | #define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 | ||
| 1267 | #define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 | ||
| 1268 | #define R_SERIAL0_TR_CTRL__tr_enable__disable 0 | ||
| 1269 | #define R_SERIAL0_TR_CTRL__tr_enable__enable 1 | ||
| 1270 | #define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 | ||
| 1271 | #define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 | ||
| 1272 | #define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 | ||
| 1273 | #define R_SERIAL0_TR_CTRL__auto_cts__active 1 | ||
| 1274 | #define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 | ||
| 1275 | #define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 | ||
| 1276 | #define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 | ||
| 1277 | #define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 | ||
| 1278 | #define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 | ||
| 1279 | #define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 | ||
| 1280 | #define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 | ||
| 1281 | #define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 | ||
| 1282 | #define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 | ||
| 1283 | #define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 | ||
| 1284 | #define R_SERIAL0_TR_CTRL__tr_par__even 0 | ||
| 1285 | #define R_SERIAL0_TR_CTRL__tr_par__odd 1 | ||
| 1286 | #define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 | ||
| 1287 | #define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 | ||
| 1288 | #define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 | ||
| 1289 | #define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 | ||
| 1290 | #define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 | ||
| 1291 | #define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 | ||
| 1292 | #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1293 | #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1294 | |||
| 1295 | #define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) | ||
| 1296 | #define R_SERIAL0_TR_DATA__data_out__BITNR 0 | ||
| 1297 | #define R_SERIAL0_TR_DATA__data_out__WIDTH 8 | ||
| 1298 | |||
| 1299 | #define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) | ||
| 1300 | #define R_SERIAL0_READ__xoff_detect__BITNR 15 | ||
| 1301 | #define R_SERIAL0_READ__xoff_detect__WIDTH 1 | ||
| 1302 | #define R_SERIAL0_READ__xoff_detect__no_xoff 0 | ||
| 1303 | #define R_SERIAL0_READ__xoff_detect__xoff 1 | ||
| 1304 | #define R_SERIAL0_READ__cts___BITNR 14 | ||
| 1305 | #define R_SERIAL0_READ__cts___WIDTH 1 | ||
| 1306 | #define R_SERIAL0_READ__cts___active 0 | ||
| 1307 | #define R_SERIAL0_READ__cts___inactive 1 | ||
| 1308 | #define R_SERIAL0_READ__tr_ready__BITNR 13 | ||
| 1309 | #define R_SERIAL0_READ__tr_ready__WIDTH 1 | ||
| 1310 | #define R_SERIAL0_READ__tr_ready__full 0 | ||
| 1311 | #define R_SERIAL0_READ__tr_ready__ready 1 | ||
| 1312 | #define R_SERIAL0_READ__rxd__BITNR 12 | ||
| 1313 | #define R_SERIAL0_READ__rxd__WIDTH 1 | ||
| 1314 | #define R_SERIAL0_READ__overrun__BITNR 11 | ||
| 1315 | #define R_SERIAL0_READ__overrun__WIDTH 1 | ||
| 1316 | #define R_SERIAL0_READ__overrun__no 0 | ||
| 1317 | #define R_SERIAL0_READ__overrun__yes 1 | ||
| 1318 | #define R_SERIAL0_READ__par_err__BITNR 10 | ||
| 1319 | #define R_SERIAL0_READ__par_err__WIDTH 1 | ||
| 1320 | #define R_SERIAL0_READ__par_err__no 0 | ||
| 1321 | #define R_SERIAL0_READ__par_err__yes 1 | ||
| 1322 | #define R_SERIAL0_READ__framing_err__BITNR 9 | ||
| 1323 | #define R_SERIAL0_READ__framing_err__WIDTH 1 | ||
| 1324 | #define R_SERIAL0_READ__framing_err__no 0 | ||
| 1325 | #define R_SERIAL0_READ__framing_err__yes 1 | ||
| 1326 | #define R_SERIAL0_READ__data_avail__BITNR 8 | ||
| 1327 | #define R_SERIAL0_READ__data_avail__WIDTH 1 | ||
| 1328 | #define R_SERIAL0_READ__data_avail__no 0 | ||
| 1329 | #define R_SERIAL0_READ__data_avail__yes 1 | ||
| 1330 | #define R_SERIAL0_READ__data_in__BITNR 0 | ||
| 1331 | #define R_SERIAL0_READ__data_in__WIDTH 8 | ||
| 1332 | |||
| 1333 | #define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) | ||
| 1334 | #define R_SERIAL0_STATUS__xoff_detect__BITNR 7 | ||
| 1335 | #define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 | ||
| 1336 | #define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 | ||
| 1337 | #define R_SERIAL0_STATUS__xoff_detect__xoff 1 | ||
| 1338 | #define R_SERIAL0_STATUS__cts___BITNR 6 | ||
| 1339 | #define R_SERIAL0_STATUS__cts___WIDTH 1 | ||
| 1340 | #define R_SERIAL0_STATUS__cts___active 0 | ||
| 1341 | #define R_SERIAL0_STATUS__cts___inactive 1 | ||
| 1342 | #define R_SERIAL0_STATUS__tr_ready__BITNR 5 | ||
| 1343 | #define R_SERIAL0_STATUS__tr_ready__WIDTH 1 | ||
| 1344 | #define R_SERIAL0_STATUS__tr_ready__full 0 | ||
| 1345 | #define R_SERIAL0_STATUS__tr_ready__ready 1 | ||
| 1346 | #define R_SERIAL0_STATUS__rxd__BITNR 4 | ||
| 1347 | #define R_SERIAL0_STATUS__rxd__WIDTH 1 | ||
| 1348 | #define R_SERIAL0_STATUS__overrun__BITNR 3 | ||
| 1349 | #define R_SERIAL0_STATUS__overrun__WIDTH 1 | ||
| 1350 | #define R_SERIAL0_STATUS__overrun__no 0 | ||
| 1351 | #define R_SERIAL0_STATUS__overrun__yes 1 | ||
| 1352 | #define R_SERIAL0_STATUS__par_err__BITNR 2 | ||
| 1353 | #define R_SERIAL0_STATUS__par_err__WIDTH 1 | ||
| 1354 | #define R_SERIAL0_STATUS__par_err__no 0 | ||
| 1355 | #define R_SERIAL0_STATUS__par_err__yes 1 | ||
| 1356 | #define R_SERIAL0_STATUS__framing_err__BITNR 1 | ||
| 1357 | #define R_SERIAL0_STATUS__framing_err__WIDTH 1 | ||
| 1358 | #define R_SERIAL0_STATUS__framing_err__no 0 | ||
| 1359 | #define R_SERIAL0_STATUS__framing_err__yes 1 | ||
| 1360 | #define R_SERIAL0_STATUS__data_avail__BITNR 0 | ||
| 1361 | #define R_SERIAL0_STATUS__data_avail__WIDTH 1 | ||
| 1362 | #define R_SERIAL0_STATUS__data_avail__no 0 | ||
| 1363 | #define R_SERIAL0_STATUS__data_avail__yes 1 | ||
| 1364 | |||
| 1365 | #define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) | ||
| 1366 | #define R_SERIAL0_REC_DATA__data_in__BITNR 0 | ||
| 1367 | #define R_SERIAL0_REC_DATA__data_in__WIDTH 8 | ||
| 1368 | |||
| 1369 | #define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) | ||
| 1370 | #define R_SERIAL0_XOFF__tx_stop__BITNR 9 | ||
| 1371 | #define R_SERIAL0_XOFF__tx_stop__WIDTH 1 | ||
| 1372 | #define R_SERIAL0_XOFF__tx_stop__enable 0 | ||
| 1373 | #define R_SERIAL0_XOFF__tx_stop__stop 1 | ||
| 1374 | #define R_SERIAL0_XOFF__auto_xoff__BITNR 8 | ||
| 1375 | #define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 | ||
| 1376 | #define R_SERIAL0_XOFF__auto_xoff__disable 0 | ||
| 1377 | #define R_SERIAL0_XOFF__auto_xoff__enable 1 | ||
| 1378 | #define R_SERIAL0_XOFF__xoff_char__BITNR 0 | ||
| 1379 | #define R_SERIAL0_XOFF__xoff_char__WIDTH 8 | ||
| 1380 | |||
| 1381 | #define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) | ||
| 1382 | #define R_SERIAL1_CTRL__tr_baud__BITNR 28 | ||
| 1383 | #define R_SERIAL1_CTRL__tr_baud__WIDTH 4 | ||
| 1384 | #define R_SERIAL1_CTRL__tr_baud__c300Hz 0 | ||
| 1385 | #define R_SERIAL1_CTRL__tr_baud__c600Hz 1 | ||
| 1386 | #define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 | ||
| 1387 | #define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 | ||
| 1388 | #define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 | ||
| 1389 | #define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 | ||
| 1390 | #define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 | ||
| 1391 | #define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 | ||
| 1392 | #define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 | ||
| 1393 | #define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 | ||
| 1394 | #define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 | ||
| 1395 | #define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 | ||
| 1396 | #define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 | ||
| 1397 | #define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 | ||
| 1398 | #define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 | ||
| 1399 | #define R_SERIAL1_CTRL__tr_baud__reserved 15 | ||
| 1400 | #define R_SERIAL1_CTRL__rec_baud__BITNR 24 | ||
| 1401 | #define R_SERIAL1_CTRL__rec_baud__WIDTH 4 | ||
| 1402 | #define R_SERIAL1_CTRL__rec_baud__c300Hz 0 | ||
| 1403 | #define R_SERIAL1_CTRL__rec_baud__c600Hz 1 | ||
| 1404 | #define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 | ||
| 1405 | #define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 | ||
| 1406 | #define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 | ||
| 1407 | #define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 | ||
| 1408 | #define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 | ||
| 1409 | #define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 | ||
| 1410 | #define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 | ||
| 1411 | #define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 | ||
| 1412 | #define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 | ||
| 1413 | #define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 | ||
| 1414 | #define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 | ||
| 1415 | #define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 | ||
| 1416 | #define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 | ||
| 1417 | #define R_SERIAL1_CTRL__rec_baud__reserved 15 | ||
| 1418 | #define R_SERIAL1_CTRL__dma_err__BITNR 23 | ||
| 1419 | #define R_SERIAL1_CTRL__dma_err__WIDTH 1 | ||
| 1420 | #define R_SERIAL1_CTRL__dma_err__stop 0 | ||
| 1421 | #define R_SERIAL1_CTRL__dma_err__ignore 1 | ||
| 1422 | #define R_SERIAL1_CTRL__rec_enable__BITNR 22 | ||
| 1423 | #define R_SERIAL1_CTRL__rec_enable__WIDTH 1 | ||
| 1424 | #define R_SERIAL1_CTRL__rec_enable__disable 0 | ||
| 1425 | #define R_SERIAL1_CTRL__rec_enable__enable 1 | ||
| 1426 | #define R_SERIAL1_CTRL__rts___BITNR 21 | ||
| 1427 | #define R_SERIAL1_CTRL__rts___WIDTH 1 | ||
| 1428 | #define R_SERIAL1_CTRL__rts___active 0 | ||
| 1429 | #define R_SERIAL1_CTRL__rts___inactive 1 | ||
| 1430 | #define R_SERIAL1_CTRL__sampling__BITNR 20 | ||
| 1431 | #define R_SERIAL1_CTRL__sampling__WIDTH 1 | ||
| 1432 | #define R_SERIAL1_CTRL__sampling__middle 0 | ||
| 1433 | #define R_SERIAL1_CTRL__sampling__majority 1 | ||
| 1434 | #define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 | ||
| 1435 | #define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 | ||
| 1436 | #define R_SERIAL1_CTRL__rec_stick_par__normal 0 | ||
| 1437 | #define R_SERIAL1_CTRL__rec_stick_par__stick 1 | ||
| 1438 | #define R_SERIAL1_CTRL__rec_par__BITNR 18 | ||
| 1439 | #define R_SERIAL1_CTRL__rec_par__WIDTH 1 | ||
| 1440 | #define R_SERIAL1_CTRL__rec_par__even 0 | ||
| 1441 | #define R_SERIAL1_CTRL__rec_par__odd 1 | ||
| 1442 | #define R_SERIAL1_CTRL__rec_par_en__BITNR 17 | ||
| 1443 | #define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 | ||
| 1444 | #define R_SERIAL1_CTRL__rec_par_en__disable 0 | ||
| 1445 | #define R_SERIAL1_CTRL__rec_par_en__enable 1 | ||
| 1446 | #define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 | ||
| 1447 | #define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 | ||
| 1448 | #define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1449 | #define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1450 | #define R_SERIAL1_CTRL__txd__BITNR 15 | ||
| 1451 | #define R_SERIAL1_CTRL__txd__WIDTH 1 | ||
| 1452 | #define R_SERIAL1_CTRL__tr_enable__BITNR 14 | ||
| 1453 | #define R_SERIAL1_CTRL__tr_enable__WIDTH 1 | ||
| 1454 | #define R_SERIAL1_CTRL__tr_enable__disable 0 | ||
| 1455 | #define R_SERIAL1_CTRL__tr_enable__enable 1 | ||
| 1456 | #define R_SERIAL1_CTRL__auto_cts__BITNR 13 | ||
| 1457 | #define R_SERIAL1_CTRL__auto_cts__WIDTH 1 | ||
| 1458 | #define R_SERIAL1_CTRL__auto_cts__disabled 0 | ||
| 1459 | #define R_SERIAL1_CTRL__auto_cts__active 1 | ||
| 1460 | #define R_SERIAL1_CTRL__stop_bits__BITNR 12 | ||
| 1461 | #define R_SERIAL1_CTRL__stop_bits__WIDTH 1 | ||
| 1462 | #define R_SERIAL1_CTRL__stop_bits__one_bit 0 | ||
| 1463 | #define R_SERIAL1_CTRL__stop_bits__two_bits 1 | ||
| 1464 | #define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 | ||
| 1465 | #define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 | ||
| 1466 | #define R_SERIAL1_CTRL__tr_stick_par__normal 0 | ||
| 1467 | #define R_SERIAL1_CTRL__tr_stick_par__stick 1 | ||
| 1468 | #define R_SERIAL1_CTRL__tr_par__BITNR 10 | ||
| 1469 | #define R_SERIAL1_CTRL__tr_par__WIDTH 1 | ||
| 1470 | #define R_SERIAL1_CTRL__tr_par__even 0 | ||
| 1471 | #define R_SERIAL1_CTRL__tr_par__odd 1 | ||
| 1472 | #define R_SERIAL1_CTRL__tr_par_en__BITNR 9 | ||
| 1473 | #define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 | ||
| 1474 | #define R_SERIAL1_CTRL__tr_par_en__disable 0 | ||
| 1475 | #define R_SERIAL1_CTRL__tr_par_en__enable 1 | ||
| 1476 | #define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 | ||
| 1477 | #define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 | ||
| 1478 | #define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1479 | #define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1480 | #define R_SERIAL1_CTRL__data_out__BITNR 0 | ||
| 1481 | #define R_SERIAL1_CTRL__data_out__WIDTH 8 | ||
| 1482 | |||
| 1483 | #define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) | ||
| 1484 | #define R_SERIAL1_BAUD__tr_baud__BITNR 4 | ||
| 1485 | #define R_SERIAL1_BAUD__tr_baud__WIDTH 4 | ||
| 1486 | #define R_SERIAL1_BAUD__tr_baud__c300Hz 0 | ||
| 1487 | #define R_SERIAL1_BAUD__tr_baud__c600Hz 1 | ||
| 1488 | #define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 | ||
| 1489 | #define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 | ||
| 1490 | #define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 | ||
| 1491 | #define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 | ||
| 1492 | #define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 | ||
| 1493 | #define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 | ||
| 1494 | #define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 | ||
| 1495 | #define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 | ||
| 1496 | #define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 | ||
| 1497 | #define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 | ||
| 1498 | #define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 | ||
| 1499 | #define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 | ||
| 1500 | #define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 | ||
| 1501 | #define R_SERIAL1_BAUD__tr_baud__reserved 15 | ||
| 1502 | #define R_SERIAL1_BAUD__rec_baud__BITNR 0 | ||
| 1503 | #define R_SERIAL1_BAUD__rec_baud__WIDTH 4 | ||
| 1504 | #define R_SERIAL1_BAUD__rec_baud__c300Hz 0 | ||
| 1505 | #define R_SERIAL1_BAUD__rec_baud__c600Hz 1 | ||
| 1506 | #define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 | ||
| 1507 | #define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 | ||
| 1508 | #define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 | ||
| 1509 | #define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 | ||
| 1510 | #define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 | ||
| 1511 | #define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 | ||
| 1512 | #define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 | ||
| 1513 | #define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 | ||
| 1514 | #define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 | ||
| 1515 | #define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 | ||
| 1516 | #define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 | ||
| 1517 | #define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 | ||
| 1518 | #define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 | ||
| 1519 | #define R_SERIAL1_BAUD__rec_baud__reserved 15 | ||
| 1520 | |||
| 1521 | #define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) | ||
| 1522 | #define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 | ||
| 1523 | #define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 | ||
| 1524 | #define R_SERIAL1_REC_CTRL__dma_err__stop 0 | ||
| 1525 | #define R_SERIAL1_REC_CTRL__dma_err__ignore 1 | ||
| 1526 | #define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 | ||
| 1527 | #define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 | ||
| 1528 | #define R_SERIAL1_REC_CTRL__rec_enable__disable 0 | ||
| 1529 | #define R_SERIAL1_REC_CTRL__rec_enable__enable 1 | ||
| 1530 | #define R_SERIAL1_REC_CTRL__rts___BITNR 5 | ||
| 1531 | #define R_SERIAL1_REC_CTRL__rts___WIDTH 1 | ||
| 1532 | #define R_SERIAL1_REC_CTRL__rts___active 0 | ||
| 1533 | #define R_SERIAL1_REC_CTRL__rts___inactive 1 | ||
| 1534 | #define R_SERIAL1_REC_CTRL__sampling__BITNR 4 | ||
| 1535 | #define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 | ||
| 1536 | #define R_SERIAL1_REC_CTRL__sampling__middle 0 | ||
| 1537 | #define R_SERIAL1_REC_CTRL__sampling__majority 1 | ||
| 1538 | #define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 | ||
| 1539 | #define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 | ||
| 1540 | #define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 | ||
| 1541 | #define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 | ||
| 1542 | #define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 | ||
| 1543 | #define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 | ||
| 1544 | #define R_SERIAL1_REC_CTRL__rec_par__even 0 | ||
| 1545 | #define R_SERIAL1_REC_CTRL__rec_par__odd 1 | ||
| 1546 | #define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 | ||
| 1547 | #define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 | ||
| 1548 | #define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 | ||
| 1549 | #define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 | ||
| 1550 | #define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 | ||
| 1551 | #define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 | ||
| 1552 | #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1553 | #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1554 | |||
| 1555 | #define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) | ||
| 1556 | #define R_SERIAL1_TR_CTRL__txd__BITNR 7 | ||
| 1557 | #define R_SERIAL1_TR_CTRL__txd__WIDTH 1 | ||
| 1558 | #define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 | ||
| 1559 | #define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 | ||
| 1560 | #define R_SERIAL1_TR_CTRL__tr_enable__disable 0 | ||
| 1561 | #define R_SERIAL1_TR_CTRL__tr_enable__enable 1 | ||
| 1562 | #define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 | ||
| 1563 | #define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 | ||
| 1564 | #define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 | ||
| 1565 | #define R_SERIAL1_TR_CTRL__auto_cts__active 1 | ||
| 1566 | #define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 | ||
| 1567 | #define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 | ||
| 1568 | #define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 | ||
| 1569 | #define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 | ||
| 1570 | #define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 | ||
| 1571 | #define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 | ||
| 1572 | #define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 | ||
| 1573 | #define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 | ||
| 1574 | #define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 | ||
| 1575 | #define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 | ||
| 1576 | #define R_SERIAL1_TR_CTRL__tr_par__even 0 | ||
| 1577 | #define R_SERIAL1_TR_CTRL__tr_par__odd 1 | ||
| 1578 | #define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 | ||
| 1579 | #define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 | ||
| 1580 | #define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 | ||
| 1581 | #define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 | ||
| 1582 | #define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 | ||
| 1583 | #define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 | ||
| 1584 | #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1585 | #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1586 | |||
| 1587 | #define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) | ||
| 1588 | #define R_SERIAL1_TR_DATA__data_out__BITNR 0 | ||
| 1589 | #define R_SERIAL1_TR_DATA__data_out__WIDTH 8 | ||
| 1590 | |||
| 1591 | #define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) | ||
| 1592 | #define R_SERIAL1_READ__xoff_detect__BITNR 15 | ||
| 1593 | #define R_SERIAL1_READ__xoff_detect__WIDTH 1 | ||
| 1594 | #define R_SERIAL1_READ__xoff_detect__no_xoff 0 | ||
| 1595 | #define R_SERIAL1_READ__xoff_detect__xoff 1 | ||
| 1596 | #define R_SERIAL1_READ__cts___BITNR 14 | ||
| 1597 | #define R_SERIAL1_READ__cts___WIDTH 1 | ||
| 1598 | #define R_SERIAL1_READ__cts___active 0 | ||
| 1599 | #define R_SERIAL1_READ__cts___inactive 1 | ||
| 1600 | #define R_SERIAL1_READ__tr_ready__BITNR 13 | ||
| 1601 | #define R_SERIAL1_READ__tr_ready__WIDTH 1 | ||
| 1602 | #define R_SERIAL1_READ__tr_ready__full 0 | ||
| 1603 | #define R_SERIAL1_READ__tr_ready__ready 1 | ||
| 1604 | #define R_SERIAL1_READ__rxd__BITNR 12 | ||
| 1605 | #define R_SERIAL1_READ__rxd__WIDTH 1 | ||
| 1606 | #define R_SERIAL1_READ__overrun__BITNR 11 | ||
| 1607 | #define R_SERIAL1_READ__overrun__WIDTH 1 | ||
| 1608 | #define R_SERIAL1_READ__overrun__no 0 | ||
| 1609 | #define R_SERIAL1_READ__overrun__yes 1 | ||
| 1610 | #define R_SERIAL1_READ__par_err__BITNR 10 | ||
| 1611 | #define R_SERIAL1_READ__par_err__WIDTH 1 | ||
| 1612 | #define R_SERIAL1_READ__par_err__no 0 | ||
| 1613 | #define R_SERIAL1_READ__par_err__yes 1 | ||
| 1614 | #define R_SERIAL1_READ__framing_err__BITNR 9 | ||
| 1615 | #define R_SERIAL1_READ__framing_err__WIDTH 1 | ||
| 1616 | #define R_SERIAL1_READ__framing_err__no 0 | ||
| 1617 | #define R_SERIAL1_READ__framing_err__yes 1 | ||
| 1618 | #define R_SERIAL1_READ__data_avail__BITNR 8 | ||
| 1619 | #define R_SERIAL1_READ__data_avail__WIDTH 1 | ||
| 1620 | #define R_SERIAL1_READ__data_avail__no 0 | ||
| 1621 | #define R_SERIAL1_READ__data_avail__yes 1 | ||
| 1622 | #define R_SERIAL1_READ__data_in__BITNR 0 | ||
| 1623 | #define R_SERIAL1_READ__data_in__WIDTH 8 | ||
| 1624 | |||
| 1625 | #define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) | ||
| 1626 | #define R_SERIAL1_STATUS__xoff_detect__BITNR 7 | ||
| 1627 | #define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 | ||
| 1628 | #define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 | ||
| 1629 | #define R_SERIAL1_STATUS__xoff_detect__xoff 1 | ||
| 1630 | #define R_SERIAL1_STATUS__cts___BITNR 6 | ||
| 1631 | #define R_SERIAL1_STATUS__cts___WIDTH 1 | ||
| 1632 | #define R_SERIAL1_STATUS__cts___active 0 | ||
| 1633 | #define R_SERIAL1_STATUS__cts___inactive 1 | ||
| 1634 | #define R_SERIAL1_STATUS__tr_ready__BITNR 5 | ||
| 1635 | #define R_SERIAL1_STATUS__tr_ready__WIDTH 1 | ||
| 1636 | #define R_SERIAL1_STATUS__tr_ready__full 0 | ||
| 1637 | #define R_SERIAL1_STATUS__tr_ready__ready 1 | ||
| 1638 | #define R_SERIAL1_STATUS__rxd__BITNR 4 | ||
| 1639 | #define R_SERIAL1_STATUS__rxd__WIDTH 1 | ||
| 1640 | #define R_SERIAL1_STATUS__overrun__BITNR 3 | ||
| 1641 | #define R_SERIAL1_STATUS__overrun__WIDTH 1 | ||
| 1642 | #define R_SERIAL1_STATUS__overrun__no 0 | ||
| 1643 | #define R_SERIAL1_STATUS__overrun__yes 1 | ||
| 1644 | #define R_SERIAL1_STATUS__par_err__BITNR 2 | ||
| 1645 | #define R_SERIAL1_STATUS__par_err__WIDTH 1 | ||
| 1646 | #define R_SERIAL1_STATUS__par_err__no 0 | ||
| 1647 | #define R_SERIAL1_STATUS__par_err__yes 1 | ||
| 1648 | #define R_SERIAL1_STATUS__framing_err__BITNR 1 | ||
| 1649 | #define R_SERIAL1_STATUS__framing_err__WIDTH 1 | ||
| 1650 | #define R_SERIAL1_STATUS__framing_err__no 0 | ||
| 1651 | #define R_SERIAL1_STATUS__framing_err__yes 1 | ||
| 1652 | #define R_SERIAL1_STATUS__data_avail__BITNR 0 | ||
| 1653 | #define R_SERIAL1_STATUS__data_avail__WIDTH 1 | ||
| 1654 | #define R_SERIAL1_STATUS__data_avail__no 0 | ||
| 1655 | #define R_SERIAL1_STATUS__data_avail__yes 1 | ||
| 1656 | |||
| 1657 | #define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) | ||
| 1658 | #define R_SERIAL1_REC_DATA__data_in__BITNR 0 | ||
| 1659 | #define R_SERIAL1_REC_DATA__data_in__WIDTH 8 | ||
| 1660 | |||
| 1661 | #define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) | ||
| 1662 | #define R_SERIAL1_XOFF__tx_stop__BITNR 9 | ||
| 1663 | #define R_SERIAL1_XOFF__tx_stop__WIDTH 1 | ||
| 1664 | #define R_SERIAL1_XOFF__tx_stop__enable 0 | ||
| 1665 | #define R_SERIAL1_XOFF__tx_stop__stop 1 | ||
| 1666 | #define R_SERIAL1_XOFF__auto_xoff__BITNR 8 | ||
| 1667 | #define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 | ||
| 1668 | #define R_SERIAL1_XOFF__auto_xoff__disable 0 | ||
| 1669 | #define R_SERIAL1_XOFF__auto_xoff__enable 1 | ||
| 1670 | #define R_SERIAL1_XOFF__xoff_char__BITNR 0 | ||
| 1671 | #define R_SERIAL1_XOFF__xoff_char__WIDTH 8 | ||
| 1672 | |||
| 1673 | #define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) | ||
| 1674 | #define R_SERIAL2_CTRL__tr_baud__BITNR 28 | ||
| 1675 | #define R_SERIAL2_CTRL__tr_baud__WIDTH 4 | ||
| 1676 | #define R_SERIAL2_CTRL__tr_baud__c300Hz 0 | ||
| 1677 | #define R_SERIAL2_CTRL__tr_baud__c600Hz 1 | ||
| 1678 | #define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 | ||
| 1679 | #define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 | ||
| 1680 | #define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 | ||
| 1681 | #define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 | ||
| 1682 | #define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 | ||
| 1683 | #define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 | ||
| 1684 | #define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 | ||
| 1685 | #define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 | ||
| 1686 | #define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 | ||
| 1687 | #define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 | ||
| 1688 | #define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 | ||
| 1689 | #define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 | ||
| 1690 | #define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 | ||
| 1691 | #define R_SERIAL2_CTRL__tr_baud__reserved 15 | ||
| 1692 | #define R_SERIAL2_CTRL__rec_baud__BITNR 24 | ||
| 1693 | #define R_SERIAL2_CTRL__rec_baud__WIDTH 4 | ||
| 1694 | #define R_SERIAL2_CTRL__rec_baud__c300Hz 0 | ||
| 1695 | #define R_SERIAL2_CTRL__rec_baud__c600Hz 1 | ||
| 1696 | #define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 | ||
| 1697 | #define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 | ||
| 1698 | #define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 | ||
| 1699 | #define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 | ||
| 1700 | #define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 | ||
| 1701 | #define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 | ||
| 1702 | #define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 | ||
| 1703 | #define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 | ||
| 1704 | #define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 | ||
| 1705 | #define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 | ||
| 1706 | #define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 | ||
| 1707 | #define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 | ||
| 1708 | #define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 | ||
| 1709 | #define R_SERIAL2_CTRL__rec_baud__reserved 15 | ||
| 1710 | #define R_SERIAL2_CTRL__dma_err__BITNR 23 | ||
| 1711 | #define R_SERIAL2_CTRL__dma_err__WIDTH 1 | ||
| 1712 | #define R_SERIAL2_CTRL__dma_err__stop 0 | ||
| 1713 | #define R_SERIAL2_CTRL__dma_err__ignore 1 | ||
| 1714 | #define R_SERIAL2_CTRL__rec_enable__BITNR 22 | ||
| 1715 | #define R_SERIAL2_CTRL__rec_enable__WIDTH 1 | ||
| 1716 | #define R_SERIAL2_CTRL__rec_enable__disable 0 | ||
| 1717 | #define R_SERIAL2_CTRL__rec_enable__enable 1 | ||
| 1718 | #define R_SERIAL2_CTRL__rts___BITNR 21 | ||
| 1719 | #define R_SERIAL2_CTRL__rts___WIDTH 1 | ||
| 1720 | #define R_SERIAL2_CTRL__rts___active 0 | ||
| 1721 | #define R_SERIAL2_CTRL__rts___inactive 1 | ||
| 1722 | #define R_SERIAL2_CTRL__sampling__BITNR 20 | ||
| 1723 | #define R_SERIAL2_CTRL__sampling__WIDTH 1 | ||
| 1724 | #define R_SERIAL2_CTRL__sampling__middle 0 | ||
| 1725 | #define R_SERIAL2_CTRL__sampling__majority 1 | ||
| 1726 | #define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 | ||
| 1727 | #define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 | ||
| 1728 | #define R_SERIAL2_CTRL__rec_stick_par__normal 0 | ||
| 1729 | #define R_SERIAL2_CTRL__rec_stick_par__stick 1 | ||
| 1730 | #define R_SERIAL2_CTRL__rec_par__BITNR 18 | ||
| 1731 | #define R_SERIAL2_CTRL__rec_par__WIDTH 1 | ||
| 1732 | #define R_SERIAL2_CTRL__rec_par__even 0 | ||
| 1733 | #define R_SERIAL2_CTRL__rec_par__odd 1 | ||
| 1734 | #define R_SERIAL2_CTRL__rec_par_en__BITNR 17 | ||
| 1735 | #define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 | ||
| 1736 | #define R_SERIAL2_CTRL__rec_par_en__disable 0 | ||
| 1737 | #define R_SERIAL2_CTRL__rec_par_en__enable 1 | ||
| 1738 | #define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 | ||
| 1739 | #define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 | ||
| 1740 | #define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1741 | #define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1742 | #define R_SERIAL2_CTRL__txd__BITNR 15 | ||
| 1743 | #define R_SERIAL2_CTRL__txd__WIDTH 1 | ||
| 1744 | #define R_SERIAL2_CTRL__tr_enable__BITNR 14 | ||
| 1745 | #define R_SERIAL2_CTRL__tr_enable__WIDTH 1 | ||
| 1746 | #define R_SERIAL2_CTRL__tr_enable__disable 0 | ||
| 1747 | #define R_SERIAL2_CTRL__tr_enable__enable 1 | ||
| 1748 | #define R_SERIAL2_CTRL__auto_cts__BITNR 13 | ||
| 1749 | #define R_SERIAL2_CTRL__auto_cts__WIDTH 1 | ||
| 1750 | #define R_SERIAL2_CTRL__auto_cts__disabled 0 | ||
| 1751 | #define R_SERIAL2_CTRL__auto_cts__active 1 | ||
| 1752 | #define R_SERIAL2_CTRL__stop_bits__BITNR 12 | ||
| 1753 | #define R_SERIAL2_CTRL__stop_bits__WIDTH 1 | ||
| 1754 | #define R_SERIAL2_CTRL__stop_bits__one_bit 0 | ||
| 1755 | #define R_SERIAL2_CTRL__stop_bits__two_bits 1 | ||
| 1756 | #define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 | ||
| 1757 | #define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 | ||
| 1758 | #define R_SERIAL2_CTRL__tr_stick_par__normal 0 | ||
| 1759 | #define R_SERIAL2_CTRL__tr_stick_par__stick 1 | ||
| 1760 | #define R_SERIAL2_CTRL__tr_par__BITNR 10 | ||
| 1761 | #define R_SERIAL2_CTRL__tr_par__WIDTH 1 | ||
| 1762 | #define R_SERIAL2_CTRL__tr_par__even 0 | ||
| 1763 | #define R_SERIAL2_CTRL__tr_par__odd 1 | ||
| 1764 | #define R_SERIAL2_CTRL__tr_par_en__BITNR 9 | ||
| 1765 | #define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 | ||
| 1766 | #define R_SERIAL2_CTRL__tr_par_en__disable 0 | ||
| 1767 | #define R_SERIAL2_CTRL__tr_par_en__enable 1 | ||
| 1768 | #define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 | ||
| 1769 | #define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 | ||
| 1770 | #define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1771 | #define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1772 | #define R_SERIAL2_CTRL__data_out__BITNR 0 | ||
| 1773 | #define R_SERIAL2_CTRL__data_out__WIDTH 8 | ||
| 1774 | |||
| 1775 | #define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) | ||
| 1776 | #define R_SERIAL2_BAUD__tr_baud__BITNR 4 | ||
| 1777 | #define R_SERIAL2_BAUD__tr_baud__WIDTH 4 | ||
| 1778 | #define R_SERIAL2_BAUD__tr_baud__c300Hz 0 | ||
| 1779 | #define R_SERIAL2_BAUD__tr_baud__c600Hz 1 | ||
| 1780 | #define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 | ||
| 1781 | #define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 | ||
| 1782 | #define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 | ||
| 1783 | #define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 | ||
| 1784 | #define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 | ||
| 1785 | #define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 | ||
| 1786 | #define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 | ||
| 1787 | #define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 | ||
| 1788 | #define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 | ||
| 1789 | #define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 | ||
| 1790 | #define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 | ||
| 1791 | #define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 | ||
| 1792 | #define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 | ||
| 1793 | #define R_SERIAL2_BAUD__tr_baud__reserved 15 | ||
| 1794 | #define R_SERIAL2_BAUD__rec_baud__BITNR 0 | ||
| 1795 | #define R_SERIAL2_BAUD__rec_baud__WIDTH 4 | ||
| 1796 | #define R_SERIAL2_BAUD__rec_baud__c300Hz 0 | ||
| 1797 | #define R_SERIAL2_BAUD__rec_baud__c600Hz 1 | ||
| 1798 | #define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 | ||
| 1799 | #define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 | ||
| 1800 | #define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 | ||
| 1801 | #define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 | ||
| 1802 | #define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 | ||
| 1803 | #define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 | ||
| 1804 | #define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 | ||
| 1805 | #define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 | ||
| 1806 | #define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 | ||
| 1807 | #define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 | ||
| 1808 | #define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 | ||
| 1809 | #define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 | ||
| 1810 | #define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 | ||
| 1811 | #define R_SERIAL2_BAUD__rec_baud__reserved 15 | ||
| 1812 | |||
| 1813 | #define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) | ||
| 1814 | #define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 | ||
| 1815 | #define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 | ||
| 1816 | #define R_SERIAL2_REC_CTRL__dma_err__stop 0 | ||
| 1817 | #define R_SERIAL2_REC_CTRL__dma_err__ignore 1 | ||
| 1818 | #define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 | ||
| 1819 | #define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 | ||
| 1820 | #define R_SERIAL2_REC_CTRL__rec_enable__disable 0 | ||
| 1821 | #define R_SERIAL2_REC_CTRL__rec_enable__enable 1 | ||
| 1822 | #define R_SERIAL2_REC_CTRL__rts___BITNR 5 | ||
| 1823 | #define R_SERIAL2_REC_CTRL__rts___WIDTH 1 | ||
| 1824 | #define R_SERIAL2_REC_CTRL__rts___active 0 | ||
| 1825 | #define R_SERIAL2_REC_CTRL__rts___inactive 1 | ||
| 1826 | #define R_SERIAL2_REC_CTRL__sampling__BITNR 4 | ||
| 1827 | #define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 | ||
| 1828 | #define R_SERIAL2_REC_CTRL__sampling__middle 0 | ||
| 1829 | #define R_SERIAL2_REC_CTRL__sampling__majority 1 | ||
| 1830 | #define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 | ||
| 1831 | #define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 | ||
| 1832 | #define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 | ||
| 1833 | #define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 | ||
| 1834 | #define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 | ||
| 1835 | #define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 | ||
| 1836 | #define R_SERIAL2_REC_CTRL__rec_par__even 0 | ||
| 1837 | #define R_SERIAL2_REC_CTRL__rec_par__odd 1 | ||
| 1838 | #define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 | ||
| 1839 | #define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 | ||
| 1840 | #define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 | ||
| 1841 | #define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 | ||
| 1842 | #define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 | ||
| 1843 | #define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 | ||
| 1844 | #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1845 | #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1846 | |||
| 1847 | #define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) | ||
| 1848 | #define R_SERIAL2_TR_CTRL__txd__BITNR 7 | ||
| 1849 | #define R_SERIAL2_TR_CTRL__txd__WIDTH 1 | ||
| 1850 | #define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 | ||
| 1851 | #define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 | ||
| 1852 | #define R_SERIAL2_TR_CTRL__tr_enable__disable 0 | ||
| 1853 | #define R_SERIAL2_TR_CTRL__tr_enable__enable 1 | ||
| 1854 | #define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 | ||
| 1855 | #define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 | ||
| 1856 | #define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 | ||
| 1857 | #define R_SERIAL2_TR_CTRL__auto_cts__active 1 | ||
| 1858 | #define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 | ||
| 1859 | #define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 | ||
| 1860 | #define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 | ||
| 1861 | #define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 | ||
| 1862 | #define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 | ||
| 1863 | #define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 | ||
| 1864 | #define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 | ||
| 1865 | #define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 | ||
| 1866 | #define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 | ||
| 1867 | #define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 | ||
| 1868 | #define R_SERIAL2_TR_CTRL__tr_par__even 0 | ||
| 1869 | #define R_SERIAL2_TR_CTRL__tr_par__odd 1 | ||
| 1870 | #define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 | ||
| 1871 | #define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 | ||
| 1872 | #define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 | ||
| 1873 | #define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 | ||
| 1874 | #define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 | ||
| 1875 | #define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 | ||
| 1876 | #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1877 | #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1878 | |||
| 1879 | #define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) | ||
| 1880 | #define R_SERIAL2_TR_DATA__data_out__BITNR 0 | ||
| 1881 | #define R_SERIAL2_TR_DATA__data_out__WIDTH 8 | ||
| 1882 | |||
| 1883 | #define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) | ||
| 1884 | #define R_SERIAL2_READ__xoff_detect__BITNR 15 | ||
| 1885 | #define R_SERIAL2_READ__xoff_detect__WIDTH 1 | ||
| 1886 | #define R_SERIAL2_READ__xoff_detect__no_xoff 0 | ||
| 1887 | #define R_SERIAL2_READ__xoff_detect__xoff 1 | ||
| 1888 | #define R_SERIAL2_READ__cts___BITNR 14 | ||
| 1889 | #define R_SERIAL2_READ__cts___WIDTH 1 | ||
| 1890 | #define R_SERIAL2_READ__cts___active 0 | ||
| 1891 | #define R_SERIAL2_READ__cts___inactive 1 | ||
| 1892 | #define R_SERIAL2_READ__tr_ready__BITNR 13 | ||
| 1893 | #define R_SERIAL2_READ__tr_ready__WIDTH 1 | ||
| 1894 | #define R_SERIAL2_READ__tr_ready__full 0 | ||
| 1895 | #define R_SERIAL2_READ__tr_ready__ready 1 | ||
| 1896 | #define R_SERIAL2_READ__rxd__BITNR 12 | ||
| 1897 | #define R_SERIAL2_READ__rxd__WIDTH 1 | ||
| 1898 | #define R_SERIAL2_READ__overrun__BITNR 11 | ||
| 1899 | #define R_SERIAL2_READ__overrun__WIDTH 1 | ||
| 1900 | #define R_SERIAL2_READ__overrun__no 0 | ||
| 1901 | #define R_SERIAL2_READ__overrun__yes 1 | ||
| 1902 | #define R_SERIAL2_READ__par_err__BITNR 10 | ||
| 1903 | #define R_SERIAL2_READ__par_err__WIDTH 1 | ||
| 1904 | #define R_SERIAL2_READ__par_err__no 0 | ||
| 1905 | #define R_SERIAL2_READ__par_err__yes 1 | ||
| 1906 | #define R_SERIAL2_READ__framing_err__BITNR 9 | ||
| 1907 | #define R_SERIAL2_READ__framing_err__WIDTH 1 | ||
| 1908 | #define R_SERIAL2_READ__framing_err__no 0 | ||
| 1909 | #define R_SERIAL2_READ__framing_err__yes 1 | ||
| 1910 | #define R_SERIAL2_READ__data_avail__BITNR 8 | ||
| 1911 | #define R_SERIAL2_READ__data_avail__WIDTH 1 | ||
| 1912 | #define R_SERIAL2_READ__data_avail__no 0 | ||
| 1913 | #define R_SERIAL2_READ__data_avail__yes 1 | ||
| 1914 | #define R_SERIAL2_READ__data_in__BITNR 0 | ||
| 1915 | #define R_SERIAL2_READ__data_in__WIDTH 8 | ||
| 1916 | |||
| 1917 | #define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) | ||
| 1918 | #define R_SERIAL2_STATUS__xoff_detect__BITNR 7 | ||
| 1919 | #define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 | ||
| 1920 | #define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 | ||
| 1921 | #define R_SERIAL2_STATUS__xoff_detect__xoff 1 | ||
| 1922 | #define R_SERIAL2_STATUS__cts___BITNR 6 | ||
| 1923 | #define R_SERIAL2_STATUS__cts___WIDTH 1 | ||
| 1924 | #define R_SERIAL2_STATUS__cts___active 0 | ||
| 1925 | #define R_SERIAL2_STATUS__cts___inactive 1 | ||
| 1926 | #define R_SERIAL2_STATUS__tr_ready__BITNR 5 | ||
| 1927 | #define R_SERIAL2_STATUS__tr_ready__WIDTH 1 | ||
| 1928 | #define R_SERIAL2_STATUS__tr_ready__full 0 | ||
| 1929 | #define R_SERIAL2_STATUS__tr_ready__ready 1 | ||
| 1930 | #define R_SERIAL2_STATUS__rxd__BITNR 4 | ||
| 1931 | #define R_SERIAL2_STATUS__rxd__WIDTH 1 | ||
| 1932 | #define R_SERIAL2_STATUS__overrun__BITNR 3 | ||
| 1933 | #define R_SERIAL2_STATUS__overrun__WIDTH 1 | ||
| 1934 | #define R_SERIAL2_STATUS__overrun__no 0 | ||
| 1935 | #define R_SERIAL2_STATUS__overrun__yes 1 | ||
| 1936 | #define R_SERIAL2_STATUS__par_err__BITNR 2 | ||
| 1937 | #define R_SERIAL2_STATUS__par_err__WIDTH 1 | ||
| 1938 | #define R_SERIAL2_STATUS__par_err__no 0 | ||
| 1939 | #define R_SERIAL2_STATUS__par_err__yes 1 | ||
| 1940 | #define R_SERIAL2_STATUS__framing_err__BITNR 1 | ||
| 1941 | #define R_SERIAL2_STATUS__framing_err__WIDTH 1 | ||
| 1942 | #define R_SERIAL2_STATUS__framing_err__no 0 | ||
| 1943 | #define R_SERIAL2_STATUS__framing_err__yes 1 | ||
| 1944 | #define R_SERIAL2_STATUS__data_avail__BITNR 0 | ||
| 1945 | #define R_SERIAL2_STATUS__data_avail__WIDTH 1 | ||
| 1946 | #define R_SERIAL2_STATUS__data_avail__no 0 | ||
| 1947 | #define R_SERIAL2_STATUS__data_avail__yes 1 | ||
| 1948 | |||
| 1949 | #define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) | ||
| 1950 | #define R_SERIAL2_REC_DATA__data_in__BITNR 0 | ||
| 1951 | #define R_SERIAL2_REC_DATA__data_in__WIDTH 8 | ||
| 1952 | |||
| 1953 | #define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) | ||
| 1954 | #define R_SERIAL2_XOFF__tx_stop__BITNR 9 | ||
| 1955 | #define R_SERIAL2_XOFF__tx_stop__WIDTH 1 | ||
| 1956 | #define R_SERIAL2_XOFF__tx_stop__enable 0 | ||
| 1957 | #define R_SERIAL2_XOFF__tx_stop__stop 1 | ||
| 1958 | #define R_SERIAL2_XOFF__auto_xoff__BITNR 8 | ||
| 1959 | #define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 | ||
| 1960 | #define R_SERIAL2_XOFF__auto_xoff__disable 0 | ||
| 1961 | #define R_SERIAL2_XOFF__auto_xoff__enable 1 | ||
| 1962 | #define R_SERIAL2_XOFF__xoff_char__BITNR 0 | ||
| 1963 | #define R_SERIAL2_XOFF__xoff_char__WIDTH 8 | ||
| 1964 | |||
| 1965 | #define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) | ||
| 1966 | #define R_SERIAL3_CTRL__tr_baud__BITNR 28 | ||
| 1967 | #define R_SERIAL3_CTRL__tr_baud__WIDTH 4 | ||
| 1968 | #define R_SERIAL3_CTRL__tr_baud__c300Hz 0 | ||
| 1969 | #define R_SERIAL3_CTRL__tr_baud__c600Hz 1 | ||
| 1970 | #define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 | ||
| 1971 | #define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 | ||
| 1972 | #define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 | ||
| 1973 | #define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 | ||
| 1974 | #define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 | ||
| 1975 | #define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 | ||
| 1976 | #define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 | ||
| 1977 | #define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 | ||
| 1978 | #define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 | ||
| 1979 | #define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 | ||
| 1980 | #define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 | ||
| 1981 | #define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 | ||
| 1982 | #define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 | ||
| 1983 | #define R_SERIAL3_CTRL__tr_baud__reserved 15 | ||
| 1984 | #define R_SERIAL3_CTRL__rec_baud__BITNR 24 | ||
| 1985 | #define R_SERIAL3_CTRL__rec_baud__WIDTH 4 | ||
| 1986 | #define R_SERIAL3_CTRL__rec_baud__c300Hz 0 | ||
| 1987 | #define R_SERIAL3_CTRL__rec_baud__c600Hz 1 | ||
| 1988 | #define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 | ||
| 1989 | #define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 | ||
| 1990 | #define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 | ||
| 1991 | #define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 | ||
| 1992 | #define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 | ||
| 1993 | #define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 | ||
| 1994 | #define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 | ||
| 1995 | #define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 | ||
| 1996 | #define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 | ||
| 1997 | #define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 | ||
| 1998 | #define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 | ||
| 1999 | #define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 | ||
| 2000 | #define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 | ||
| 2001 | #define R_SERIAL3_CTRL__rec_baud__reserved 15 | ||
| 2002 | #define R_SERIAL3_CTRL__dma_err__BITNR 23 | ||
| 2003 | #define R_SERIAL3_CTRL__dma_err__WIDTH 1 | ||
| 2004 | #define R_SERIAL3_CTRL__dma_err__stop 0 | ||
| 2005 | #define R_SERIAL3_CTRL__dma_err__ignore 1 | ||
| 2006 | #define R_SERIAL3_CTRL__rec_enable__BITNR 22 | ||
| 2007 | #define R_SERIAL3_CTRL__rec_enable__WIDTH 1 | ||
| 2008 | #define R_SERIAL3_CTRL__rec_enable__disable 0 | ||
| 2009 | #define R_SERIAL3_CTRL__rec_enable__enable 1 | ||
| 2010 | #define R_SERIAL3_CTRL__rts___BITNR 21 | ||
| 2011 | #define R_SERIAL3_CTRL__rts___WIDTH 1 | ||
| 2012 | #define R_SERIAL3_CTRL__rts___active 0 | ||
| 2013 | #define R_SERIAL3_CTRL__rts___inactive 1 | ||
| 2014 | #define R_SERIAL3_CTRL__sampling__BITNR 20 | ||
| 2015 | #define R_SERIAL3_CTRL__sampling__WIDTH 1 | ||
| 2016 | #define R_SERIAL3_CTRL__sampling__middle 0 | ||
| 2017 | #define R_SERIAL3_CTRL__sampling__majority 1 | ||
| 2018 | #define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 | ||
| 2019 | #define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 | ||
| 2020 | #define R_SERIAL3_CTRL__rec_stick_par__normal 0 | ||
| 2021 | #define R_SERIAL3_CTRL__rec_stick_par__stick 1 | ||
| 2022 | #define R_SERIAL3_CTRL__rec_par__BITNR 18 | ||
| 2023 | #define R_SERIAL3_CTRL__rec_par__WIDTH 1 | ||
| 2024 | #define R_SERIAL3_CTRL__rec_par__even 0 | ||
| 2025 | #define R_SERIAL3_CTRL__rec_par__odd 1 | ||
| 2026 | #define R_SERIAL3_CTRL__rec_par_en__BITNR 17 | ||
| 2027 | #define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 | ||
| 2028 | #define R_SERIAL3_CTRL__rec_par_en__disable 0 | ||
| 2029 | #define R_SERIAL3_CTRL__rec_par_en__enable 1 | ||
| 2030 | #define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 | ||
| 2031 | #define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 | ||
| 2032 | #define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 | ||
| 2033 | #define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 | ||
| 2034 | #define R_SERIAL3_CTRL__txd__BITNR 15 | ||
| 2035 | #define R_SERIAL3_CTRL__txd__WIDTH 1 | ||
| 2036 | #define R_SERIAL3_CTRL__tr_enable__BITNR 14 | ||
| 2037 | #define R_SERIAL3_CTRL__tr_enable__WIDTH 1 | ||
| 2038 | #define R_SERIAL3_CTRL__tr_enable__disable 0 | ||
| 2039 | #define R_SERIAL3_CTRL__tr_enable__enable 1 | ||
| 2040 | #define R_SERIAL3_CTRL__auto_cts__BITNR 13 | ||
| 2041 | #define R_SERIAL3_CTRL__auto_cts__WIDTH 1 | ||
| 2042 | #define R_SERIAL3_CTRL__auto_cts__disabled 0 | ||
| 2043 | #define R_SERIAL3_CTRL__auto_cts__active 1 | ||
| 2044 | #define R_SERIAL3_CTRL__stop_bits__BITNR 12 | ||
| 2045 | #define R_SERIAL3_CTRL__stop_bits__WIDTH 1 | ||
| 2046 | #define R_SERIAL3_CTRL__stop_bits__one_bit 0 | ||
| 2047 | #define R_SERIAL3_CTRL__stop_bits__two_bits 1 | ||
| 2048 | #define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 | ||
| 2049 | #define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 | ||
| 2050 | #define R_SERIAL3_CTRL__tr_stick_par__normal 0 | ||
| 2051 | #define R_SERIAL3_CTRL__tr_stick_par__stick 1 | ||
| 2052 | #define R_SERIAL3_CTRL__tr_par__BITNR 10 | ||
| 2053 | #define R_SERIAL3_CTRL__tr_par__WIDTH 1 | ||
| 2054 | #define R_SERIAL3_CTRL__tr_par__even 0 | ||
| 2055 | #define R_SERIAL3_CTRL__tr_par__odd 1 | ||
| 2056 | #define R_SERIAL3_CTRL__tr_par_en__BITNR 9 | ||
| 2057 | #define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 | ||
| 2058 | #define R_SERIAL3_CTRL__tr_par_en__disable 0 | ||
| 2059 | #define R_SERIAL3_CTRL__tr_par_en__enable 1 | ||
| 2060 | #define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 | ||
| 2061 | #define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 | ||
| 2062 | #define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 | ||
| 2063 | #define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 | ||
| 2064 | #define R_SERIAL3_CTRL__data_out__BITNR 0 | ||
| 2065 | #define R_SERIAL3_CTRL__data_out__WIDTH 8 | ||
| 2066 | |||
| 2067 | #define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) | ||
| 2068 | #define R_SERIAL3_BAUD__tr_baud__BITNR 4 | ||
| 2069 | #define R_SERIAL3_BAUD__tr_baud__WIDTH 4 | ||
| 2070 | #define R_SERIAL3_BAUD__tr_baud__c300Hz 0 | ||
| 2071 | #define R_SERIAL3_BAUD__tr_baud__c600Hz 1 | ||
| 2072 | #define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 | ||
| 2073 | #define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 | ||
| 2074 | #define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 | ||
| 2075 | #define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 | ||
| 2076 | #define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 | ||
| 2077 | #define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 | ||
| 2078 | #define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 | ||
| 2079 | #define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 | ||
| 2080 | #define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 | ||
| 2081 | #define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 | ||
| 2082 | #define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 | ||
| 2083 | #define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 | ||
| 2084 | #define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 | ||
| 2085 | #define R_SERIAL3_BAUD__tr_baud__reserved 15 | ||
| 2086 | #define R_SERIAL3_BAUD__rec_baud__BITNR 0 | ||
| 2087 | #define R_SERIAL3_BAUD__rec_baud__WIDTH 4 | ||
| 2088 | #define R_SERIAL3_BAUD__rec_baud__c300Hz 0 | ||
| 2089 | #define R_SERIAL3_BAUD__rec_baud__c600Hz 1 | ||
| 2090 | #define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 | ||
| 2091 | #define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 | ||
| 2092 | #define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 | ||
| 2093 | #define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 | ||
| 2094 | #define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 | ||
| 2095 | #define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 | ||
| 2096 | #define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 | ||
| 2097 | #define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 | ||
| 2098 | #define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 | ||
| 2099 | #define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 | ||
| 2100 | #define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 | ||
| 2101 | #define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 | ||
| 2102 | #define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 | ||
| 2103 | #define R_SERIAL3_BAUD__rec_baud__reserved 15 | ||
| 2104 | |||
| 2105 | #define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) | ||
| 2106 | #define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 | ||
| 2107 | #define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 | ||
| 2108 | #define R_SERIAL3_REC_CTRL__dma_err__stop 0 | ||
| 2109 | #define R_SERIAL3_REC_CTRL__dma_err__ignore 1 | ||
| 2110 | #define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 | ||
| 2111 | #define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 | ||
| 2112 | #define R_SERIAL3_REC_CTRL__rec_enable__disable 0 | ||
| 2113 | #define R_SERIAL3_REC_CTRL__rec_enable__enable 1 | ||
| 2114 | #define R_SERIAL3_REC_CTRL__rts___BITNR 5 | ||
| 2115 | #define R_SERIAL3_REC_CTRL__rts___WIDTH 1 | ||
| 2116 | #define R_SERIAL3_REC_CTRL__rts___active 0 | ||
| 2117 | #define R_SERIAL3_REC_CTRL__rts___inactive 1 | ||
| 2118 | #define R_SERIAL3_REC_CTRL__sampling__BITNR 4 | ||
| 2119 | #define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 | ||
| 2120 | #define R_SERIAL3_REC_CTRL__sampling__middle 0 | ||
| 2121 | #define R_SERIAL3_REC_CTRL__sampling__majority 1 | ||
| 2122 | #define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 | ||
| 2123 | #define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 | ||
| 2124 | #define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 | ||
| 2125 | #define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 | ||
| 2126 | #define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 | ||
| 2127 | #define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 | ||
| 2128 | #define R_SERIAL3_REC_CTRL__rec_par__even 0 | ||
| 2129 | #define R_SERIAL3_REC_CTRL__rec_par__odd 1 | ||
| 2130 | #define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 | ||
| 2131 | #define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 | ||
| 2132 | #define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 | ||
| 2133 | #define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 | ||
| 2134 | #define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 | ||
| 2135 | #define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 | ||
| 2136 | #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 | ||
| 2137 | #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 | ||
| 2138 | |||
| 2139 | #define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) | ||
| 2140 | #define R_SERIAL3_TR_CTRL__txd__BITNR 7 | ||
| 2141 | #define R_SERIAL3_TR_CTRL__txd__WIDTH 1 | ||
| 2142 | #define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 | ||
| 2143 | #define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 | ||
| 2144 | #define R_SERIAL3_TR_CTRL__tr_enable__disable 0 | ||
| 2145 | #define R_SERIAL3_TR_CTRL__tr_enable__enable 1 | ||
| 2146 | #define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 | ||
| 2147 | #define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 | ||
| 2148 | #define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 | ||
| 2149 | #define R_SERIAL3_TR_CTRL__auto_cts__active 1 | ||
| 2150 | #define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 | ||
| 2151 | #define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 | ||
| 2152 | #define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 | ||
| 2153 | #define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 | ||
| 2154 | #define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 | ||
| 2155 | #define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 | ||
| 2156 | #define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 | ||
| 2157 | #define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 | ||
| 2158 | #define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 | ||
| 2159 | #define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 | ||
| 2160 | #define R_SERIAL3_TR_CTRL__tr_par__even 0 | ||
| 2161 | #define R_SERIAL3_TR_CTRL__tr_par__odd 1 | ||
| 2162 | #define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 | ||
| 2163 | #define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 | ||
| 2164 | #define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 | ||
| 2165 | #define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 | ||
| 2166 | #define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 | ||
| 2167 | #define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 | ||
| 2168 | #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 | ||
| 2169 | #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 | ||
| 2170 | |||
| 2171 | #define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) | ||
| 2172 | #define R_SERIAL3_TR_DATA__data_out__BITNR 0 | ||
| 2173 | #define R_SERIAL3_TR_DATA__data_out__WIDTH 8 | ||
| 2174 | |||
| 2175 | #define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) | ||
| 2176 | #define R_SERIAL3_READ__xoff_detect__BITNR 15 | ||
| 2177 | #define R_SERIAL3_READ__xoff_detect__WIDTH 1 | ||
| 2178 | #define R_SERIAL3_READ__xoff_detect__no_xoff 0 | ||
| 2179 | #define R_SERIAL3_READ__xoff_detect__xoff 1 | ||
| 2180 | #define R_SERIAL3_READ__cts___BITNR 14 | ||
| 2181 | #define R_SERIAL3_READ__cts___WIDTH 1 | ||
| 2182 | #define R_SERIAL3_READ__cts___active 0 | ||
| 2183 | #define R_SERIAL3_READ__cts___inactive 1 | ||
| 2184 | #define R_SERIAL3_READ__tr_ready__BITNR 13 | ||
| 2185 | #define R_SERIAL3_READ__tr_ready__WIDTH 1 | ||
| 2186 | #define R_SERIAL3_READ__tr_ready__full 0 | ||
| 2187 | #define R_SERIAL3_READ__tr_ready__ready 1 | ||
| 2188 | #define R_SERIAL3_READ__rxd__BITNR 12 | ||
| 2189 | #define R_SERIAL3_READ__rxd__WIDTH 1 | ||
| 2190 | #define R_SERIAL3_READ__overrun__BITNR 11 | ||
| 2191 | #define R_SERIAL3_READ__overrun__WIDTH 1 | ||
| 2192 | #define R_SERIAL3_READ__overrun__no 0 | ||
| 2193 | #define R_SERIAL3_READ__overrun__yes 1 | ||
| 2194 | #define R_SERIAL3_READ__par_err__BITNR 10 | ||
| 2195 | #define R_SERIAL3_READ__par_err__WIDTH 1 | ||
| 2196 | #define R_SERIAL3_READ__par_err__no 0 | ||
| 2197 | #define R_SERIAL3_READ__par_err__yes 1 | ||
| 2198 | #define R_SERIAL3_READ__framing_err__BITNR 9 | ||
| 2199 | #define R_SERIAL3_READ__framing_err__WIDTH 1 | ||
| 2200 | #define R_SERIAL3_READ__framing_err__no 0 | ||
| 2201 | #define R_SERIAL3_READ__framing_err__yes 1 | ||
| 2202 | #define R_SERIAL3_READ__data_avail__BITNR 8 | ||
| 2203 | #define R_SERIAL3_READ__data_avail__WIDTH 1 | ||
| 2204 | #define R_SERIAL3_READ__data_avail__no 0 | ||
| 2205 | #define R_SERIAL3_READ__data_avail__yes 1 | ||
| 2206 | #define R_SERIAL3_READ__data_in__BITNR 0 | ||
| 2207 | #define R_SERIAL3_READ__data_in__WIDTH 8 | ||
| 2208 | |||
| 2209 | #define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) | ||
| 2210 | #define R_SERIAL3_STATUS__xoff_detect__BITNR 7 | ||
| 2211 | #define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 | ||
| 2212 | #define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 | ||
| 2213 | #define R_SERIAL3_STATUS__xoff_detect__xoff 1 | ||
| 2214 | #define R_SERIAL3_STATUS__cts___BITNR 6 | ||
| 2215 | #define R_SERIAL3_STATUS__cts___WIDTH 1 | ||
| 2216 | #define R_SERIAL3_STATUS__cts___active 0 | ||
| 2217 | #define R_SERIAL3_STATUS__cts___inactive 1 | ||
| 2218 | #define R_SERIAL3_STATUS__tr_ready__BITNR 5 | ||
| 2219 | #define R_SERIAL3_STATUS__tr_ready__WIDTH 1 | ||
| 2220 | #define R_SERIAL3_STATUS__tr_ready__full 0 | ||
| 2221 | #define R_SERIAL3_STATUS__tr_ready__ready 1 | ||
| 2222 | #define R_SERIAL3_STATUS__rxd__BITNR 4 | ||
| 2223 | #define R_SERIAL3_STATUS__rxd__WIDTH 1 | ||
| 2224 | #define R_SERIAL3_STATUS__overrun__BITNR 3 | ||
| 2225 | #define R_SERIAL3_STATUS__overrun__WIDTH 1 | ||
| 2226 | #define R_SERIAL3_STATUS__overrun__no 0 | ||
| 2227 | #define R_SERIAL3_STATUS__overrun__yes 1 | ||
| 2228 | #define R_SERIAL3_STATUS__par_err__BITNR 2 | ||
| 2229 | #define R_SERIAL3_STATUS__par_err__WIDTH 1 | ||
| 2230 | #define R_SERIAL3_STATUS__par_err__no 0 | ||
| 2231 | #define R_SERIAL3_STATUS__par_err__yes 1 | ||
| 2232 | #define R_SERIAL3_STATUS__framing_err__BITNR 1 | ||
| 2233 | #define R_SERIAL3_STATUS__framing_err__WIDTH 1 | ||
| 2234 | #define R_SERIAL3_STATUS__framing_err__no 0 | ||
| 2235 | #define R_SERIAL3_STATUS__framing_err__yes 1 | ||
| 2236 | #define R_SERIAL3_STATUS__data_avail__BITNR 0 | ||
| 2237 | #define R_SERIAL3_STATUS__data_avail__WIDTH 1 | ||
| 2238 | #define R_SERIAL3_STATUS__data_avail__no 0 | ||
| 2239 | #define R_SERIAL3_STATUS__data_avail__yes 1 | ||
| 2240 | |||
| 2241 | #define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) | ||
| 2242 | #define R_SERIAL3_REC_DATA__data_in__BITNR 0 | ||
| 2243 | #define R_SERIAL3_REC_DATA__data_in__WIDTH 8 | ||
| 2244 | |||
| 2245 | #define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) | ||
| 2246 | #define R_SERIAL3_XOFF__tx_stop__BITNR 9 | ||
| 2247 | #define R_SERIAL3_XOFF__tx_stop__WIDTH 1 | ||
| 2248 | #define R_SERIAL3_XOFF__tx_stop__enable 0 | ||
| 2249 | #define R_SERIAL3_XOFF__tx_stop__stop 1 | ||
| 2250 | #define R_SERIAL3_XOFF__auto_xoff__BITNR 8 | ||
| 2251 | #define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 | ||
| 2252 | #define R_SERIAL3_XOFF__auto_xoff__disable 0 | ||
| 2253 | #define R_SERIAL3_XOFF__auto_xoff__enable 1 | ||
| 2254 | #define R_SERIAL3_XOFF__xoff_char__BITNR 0 | ||
| 2255 | #define R_SERIAL3_XOFF__xoff_char__WIDTH 8 | ||
| 2256 | |||
| 2257 | #define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) | ||
| 2258 | #define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 | ||
| 2259 | #define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 | ||
| 2260 | #define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 | ||
| 2261 | #define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 | ||
| 2262 | #define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 | ||
| 2263 | #define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 | ||
| 2264 | #define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 | ||
| 2265 | #define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 | ||
| 2266 | #define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 | ||
| 2267 | #define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 | ||
| 2268 | #define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 | ||
| 2269 | #define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 | ||
| 2270 | #define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 | ||
| 2271 | #define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 | ||
| 2272 | #define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 | ||
| 2273 | #define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 | ||
| 2274 | #define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 | ||
| 2275 | #define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 | ||
| 2276 | #define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 | ||
| 2277 | #define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 | ||
| 2278 | #define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 | ||
| 2279 | #define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 | ||
| 2280 | #define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 | ||
| 2281 | #define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 | ||
| 2282 | #define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 | ||
| 2283 | #define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 | ||
| 2284 | #define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 | ||
| 2285 | #define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 | ||
| 2286 | #define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 | ||
| 2287 | #define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 | ||
| 2288 | #define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 | ||
| 2289 | #define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 | ||
| 2290 | #define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 | ||
| 2291 | #define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 | ||
| 2292 | #define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 | ||
| 2293 | #define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 | ||
| 2294 | #define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 | ||
| 2295 | #define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 | ||
| 2296 | #define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 | ||
| 2297 | #define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 | ||
| 2298 | #define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 | ||
| 2299 | #define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 | ||
| 2300 | #define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 | ||
| 2301 | #define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 | ||
| 2302 | #define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 | ||
| 2303 | #define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 | ||
| 2304 | #define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 | ||
| 2305 | #define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 | ||
| 2306 | |||
| 2307 | /* | ||
| 2308 | !* Network interface registers | ||
| 2309 | !*/ | ||
| 2310 | |||
| 2311 | #define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) | ||
| 2312 | #define R_NETWORK_SA_0__ma0_low__BITNR 0 | ||
| 2313 | #define R_NETWORK_SA_0__ma0_low__WIDTH 32 | ||
| 2314 | |||
| 2315 | #define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) | ||
| 2316 | #define R_NETWORK_SA_1__ma1_low__BITNR 16 | ||
| 2317 | #define R_NETWORK_SA_1__ma1_low__WIDTH 16 | ||
| 2318 | #define R_NETWORK_SA_1__ma0_high__BITNR 0 | ||
| 2319 | #define R_NETWORK_SA_1__ma0_high__WIDTH 16 | ||
| 2320 | |||
| 2321 | #define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) | ||
| 2322 | #define R_NETWORK_SA_2__ma1_high__BITNR 0 | ||
| 2323 | #define R_NETWORK_SA_2__ma1_high__WIDTH 32 | ||
| 2324 | |||
| 2325 | #define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) | ||
| 2326 | #define R_NETWORK_GA_0__ga_low__BITNR 0 | ||
| 2327 | #define R_NETWORK_GA_0__ga_low__WIDTH 32 | ||
| 2328 | |||
| 2329 | #define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) | ||
| 2330 | #define R_NETWORK_GA_1__ga_high__BITNR 0 | ||
| 2331 | #define R_NETWORK_GA_1__ga_high__WIDTH 32 | ||
| 2332 | |||
| 2333 | #define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) | ||
| 2334 | #define R_NETWORK_REC_CONFIG__max_size__BITNR 10 | ||
| 2335 | #define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 | ||
| 2336 | #define R_NETWORK_REC_CONFIG__max_size__size1518 0 | ||
| 2337 | #define R_NETWORK_REC_CONFIG__max_size__size1522 1 | ||
| 2338 | #define R_NETWORK_REC_CONFIG__duplex__BITNR 9 | ||
| 2339 | #define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 | ||
| 2340 | #define R_NETWORK_REC_CONFIG__duplex__full 1 | ||
| 2341 | #define R_NETWORK_REC_CONFIG__duplex__half 0 | ||
| 2342 | #define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 | ||
| 2343 | #define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 | ||
| 2344 | #define R_NETWORK_REC_CONFIG__bad_crc__receive 1 | ||
| 2345 | #define R_NETWORK_REC_CONFIG__bad_crc__discard 0 | ||
| 2346 | #define R_NETWORK_REC_CONFIG__oversize__BITNR 7 | ||
| 2347 | #define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 | ||
| 2348 | #define R_NETWORK_REC_CONFIG__oversize__receive 1 | ||
| 2349 | #define R_NETWORK_REC_CONFIG__oversize__discard 0 | ||
| 2350 | #define R_NETWORK_REC_CONFIG__undersize__BITNR 6 | ||
| 2351 | #define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 | ||
| 2352 | #define R_NETWORK_REC_CONFIG__undersize__receive 1 | ||
| 2353 | #define R_NETWORK_REC_CONFIG__undersize__discard 0 | ||
| 2354 | #define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 | ||
| 2355 | #define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 | ||
| 2356 | #define R_NETWORK_REC_CONFIG__all_roots__receive 1 | ||
| 2357 | #define R_NETWORK_REC_CONFIG__all_roots__discard 0 | ||
| 2358 | #define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 | ||
| 2359 | #define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 | ||
| 2360 | #define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 | ||
| 2361 | #define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 | ||
| 2362 | #define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 | ||
| 2363 | #define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 | ||
| 2364 | #define R_NETWORK_REC_CONFIG__broadcast__receive 1 | ||
| 2365 | #define R_NETWORK_REC_CONFIG__broadcast__discard 0 | ||
| 2366 | #define R_NETWORK_REC_CONFIG__individual__BITNR 2 | ||
| 2367 | #define R_NETWORK_REC_CONFIG__individual__WIDTH 1 | ||
| 2368 | #define R_NETWORK_REC_CONFIG__individual__receive 1 | ||
| 2369 | #define R_NETWORK_REC_CONFIG__individual__discard 0 | ||
| 2370 | #define R_NETWORK_REC_CONFIG__ma1__BITNR 1 | ||
| 2371 | #define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 | ||
| 2372 | #define R_NETWORK_REC_CONFIG__ma1__enable 1 | ||
| 2373 | #define R_NETWORK_REC_CONFIG__ma1__disable 0 | ||
| 2374 | #define R_NETWORK_REC_CONFIG__ma0__BITNR 0 | ||
| 2375 | #define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 | ||
| 2376 | #define R_NETWORK_REC_CONFIG__ma0__enable 1 | ||
| 2377 | #define R_NETWORK_REC_CONFIG__ma0__disable 0 | ||
| 2378 | |||
| 2379 | #define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) | ||
| 2380 | #define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 | ||
| 2381 | #define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 | ||
| 2382 | #define R_NETWORK_GEN_CONFIG__loopback__on 1 | ||
| 2383 | #define R_NETWORK_GEN_CONFIG__loopback__off 0 | ||
| 2384 | #define R_NETWORK_GEN_CONFIG__frame__BITNR 4 | ||
| 2385 | #define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 | ||
| 2386 | #define R_NETWORK_GEN_CONFIG__frame__tokenr 1 | ||
| 2387 | #define R_NETWORK_GEN_CONFIG__frame__ether 0 | ||
| 2388 | #define R_NETWORK_GEN_CONFIG__vg__BITNR 3 | ||
| 2389 | #define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 | ||
| 2390 | #define R_NETWORK_GEN_CONFIG__vg__on 1 | ||
| 2391 | #define R_NETWORK_GEN_CONFIG__vg__off 0 | ||
| 2392 | #define R_NETWORK_GEN_CONFIG__phy__BITNR 1 | ||
| 2393 | #define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 | ||
| 2394 | #define R_NETWORK_GEN_CONFIG__phy__sni 0 | ||
| 2395 | #define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 | ||
| 2396 | #define R_NETWORK_GEN_CONFIG__phy__mii_err 2 | ||
| 2397 | #define R_NETWORK_GEN_CONFIG__phy__mii_req 3 | ||
| 2398 | #define R_NETWORK_GEN_CONFIG__enable__BITNR 0 | ||
| 2399 | #define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 | ||
| 2400 | #define R_NETWORK_GEN_CONFIG__enable__on 1 | ||
| 2401 | #define R_NETWORK_GEN_CONFIG__enable__off 0 | ||
| 2402 | |||
| 2403 | #define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) | ||
| 2404 | #define R_NETWORK_TR_CTRL__clr_error__BITNR 8 | ||
| 2405 | #define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 | ||
| 2406 | #define R_NETWORK_TR_CTRL__clr_error__clr 1 | ||
| 2407 | #define R_NETWORK_TR_CTRL__clr_error__nop 0 | ||
| 2408 | #define R_NETWORK_TR_CTRL__delay__BITNR 5 | ||
| 2409 | #define R_NETWORK_TR_CTRL__delay__WIDTH 1 | ||
| 2410 | #define R_NETWORK_TR_CTRL__delay__d2us 1 | ||
| 2411 | #define R_NETWORK_TR_CTRL__delay__none 0 | ||
| 2412 | #define R_NETWORK_TR_CTRL__cancel__BITNR 4 | ||
| 2413 | #define R_NETWORK_TR_CTRL__cancel__WIDTH 1 | ||
| 2414 | #define R_NETWORK_TR_CTRL__cancel__do 1 | ||
| 2415 | #define R_NETWORK_TR_CTRL__cancel__dont 0 | ||
| 2416 | #define R_NETWORK_TR_CTRL__cd__BITNR 3 | ||
| 2417 | #define R_NETWORK_TR_CTRL__cd__WIDTH 1 | ||
| 2418 | #define R_NETWORK_TR_CTRL__cd__enable 0 | ||
| 2419 | #define R_NETWORK_TR_CTRL__cd__disable 1 | ||
| 2420 | #define R_NETWORK_TR_CTRL__cd__ack_col 0 | ||
| 2421 | #define R_NETWORK_TR_CTRL__cd__ack_crs 1 | ||
| 2422 | #define R_NETWORK_TR_CTRL__retry__BITNR 2 | ||
| 2423 | #define R_NETWORK_TR_CTRL__retry__WIDTH 1 | ||
| 2424 | #define R_NETWORK_TR_CTRL__retry__enable 0 | ||
| 2425 | #define R_NETWORK_TR_CTRL__retry__disable 1 | ||
| 2426 | #define R_NETWORK_TR_CTRL__pad__BITNR 1 | ||
| 2427 | #define R_NETWORK_TR_CTRL__pad__WIDTH 1 | ||
| 2428 | #define R_NETWORK_TR_CTRL__pad__enable 1 | ||
| 2429 | #define R_NETWORK_TR_CTRL__pad__disable 0 | ||
| 2430 | #define R_NETWORK_TR_CTRL__crc__BITNR 0 | ||
| 2431 | #define R_NETWORK_TR_CTRL__crc__WIDTH 1 | ||
| 2432 | #define R_NETWORK_TR_CTRL__crc__enable 0 | ||
| 2433 | #define R_NETWORK_TR_CTRL__crc__disable 1 | ||
| 2434 | |||
| 2435 | #define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) | ||
| 2436 | #define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 | ||
| 2437 | #define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 | ||
| 2438 | #define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 | ||
| 2439 | #define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 | ||
| 2440 | #define R_NETWORK_MGM_CTRL__mdck__BITNR 2 | ||
| 2441 | #define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 | ||
| 2442 | #define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 | ||
| 2443 | #define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 | ||
| 2444 | #define R_NETWORK_MGM_CTRL__mdoe__enable 1 | ||
| 2445 | #define R_NETWORK_MGM_CTRL__mdoe__disable 0 | ||
| 2446 | #define R_NETWORK_MGM_CTRL__mdio__BITNR 0 | ||
| 2447 | #define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 | ||
| 2448 | |||
| 2449 | #define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) | ||
| 2450 | #define R_NETWORK_STAT__rxd_pins__BITNR 4 | ||
| 2451 | #define R_NETWORK_STAT__rxd_pins__WIDTH 4 | ||
| 2452 | #define R_NETWORK_STAT__rxer__BITNR 3 | ||
| 2453 | #define R_NETWORK_STAT__rxer__WIDTH 1 | ||
| 2454 | #define R_NETWORK_STAT__underrun__BITNR 2 | ||
| 2455 | #define R_NETWORK_STAT__underrun__WIDTH 1 | ||
| 2456 | #define R_NETWORK_STAT__underrun__yes 1 | ||
| 2457 | #define R_NETWORK_STAT__underrun__no 0 | ||
| 2458 | #define R_NETWORK_STAT__exc_col__BITNR 1 | ||
| 2459 | #define R_NETWORK_STAT__exc_col__WIDTH 1 | ||
| 2460 | #define R_NETWORK_STAT__exc_col__yes 1 | ||
| 2461 | #define R_NETWORK_STAT__exc_col__no 0 | ||
| 2462 | #define R_NETWORK_STAT__mdio__BITNR 0 | ||
| 2463 | #define R_NETWORK_STAT__mdio__WIDTH 1 | ||
| 2464 | |||
| 2465 | #define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) | ||
| 2466 | #define R_REC_COUNTERS__congestion__BITNR 24 | ||
| 2467 | #define R_REC_COUNTERS__congestion__WIDTH 8 | ||
| 2468 | #define R_REC_COUNTERS__oversize__BITNR 16 | ||
| 2469 | #define R_REC_COUNTERS__oversize__WIDTH 8 | ||
| 2470 | #define R_REC_COUNTERS__alignment_error__BITNR 8 | ||
| 2471 | #define R_REC_COUNTERS__alignment_error__WIDTH 8 | ||
| 2472 | #define R_REC_COUNTERS__crc_error__BITNR 0 | ||
| 2473 | #define R_REC_COUNTERS__crc_error__WIDTH 8 | ||
| 2474 | |||
| 2475 | #define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) | ||
| 2476 | #define R_TR_COUNTERS__deferred__BITNR 24 | ||
| 2477 | #define R_TR_COUNTERS__deferred__WIDTH 8 | ||
| 2478 | #define R_TR_COUNTERS__late_col__BITNR 16 | ||
| 2479 | #define R_TR_COUNTERS__late_col__WIDTH 8 | ||
| 2480 | #define R_TR_COUNTERS__multiple_col__BITNR 8 | ||
| 2481 | #define R_TR_COUNTERS__multiple_col__WIDTH 8 | ||
| 2482 | #define R_TR_COUNTERS__single_col__BITNR 0 | ||
| 2483 | #define R_TR_COUNTERS__single_col__WIDTH 8 | ||
| 2484 | |||
| 2485 | #define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) | ||
| 2486 | #define R_PHY_COUNTERS__sqe_test_error__BITNR 8 | ||
| 2487 | #define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 | ||
| 2488 | #define R_PHY_COUNTERS__carrier_loss__BITNR 0 | ||
| 2489 | #define R_PHY_COUNTERS__carrier_loss__WIDTH 8 | ||
| 2490 | |||
| 2491 | /* | ||
| 2492 | !* Parallel printer port registers | ||
| 2493 | !*/ | ||
| 2494 | |||
| 2495 | #define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) | ||
| 2496 | #define R_PAR0_CTRL_DATA__peri_int__BITNR 24 | ||
| 2497 | #define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 | ||
| 2498 | #define R_PAR0_CTRL_DATA__peri_int__ack 1 | ||
| 2499 | #define R_PAR0_CTRL_DATA__peri_int__nop 0 | ||
| 2500 | #define R_PAR0_CTRL_DATA__oe__BITNR 20 | ||
| 2501 | #define R_PAR0_CTRL_DATA__oe__WIDTH 1 | ||
| 2502 | #define R_PAR0_CTRL_DATA__oe__enable 1 | ||
| 2503 | #define R_PAR0_CTRL_DATA__oe__disable 0 | ||
| 2504 | #define R_PAR0_CTRL_DATA__seli__BITNR 19 | ||
| 2505 | #define R_PAR0_CTRL_DATA__seli__WIDTH 1 | ||
| 2506 | #define R_PAR0_CTRL_DATA__seli__active 1 | ||
| 2507 | #define R_PAR0_CTRL_DATA__seli__inactive 0 | ||
| 2508 | #define R_PAR0_CTRL_DATA__autofd__BITNR 18 | ||
| 2509 | #define R_PAR0_CTRL_DATA__autofd__WIDTH 1 | ||
| 2510 | #define R_PAR0_CTRL_DATA__autofd__active 1 | ||
| 2511 | #define R_PAR0_CTRL_DATA__autofd__inactive 0 | ||
| 2512 | #define R_PAR0_CTRL_DATA__strb__BITNR 17 | ||
| 2513 | #define R_PAR0_CTRL_DATA__strb__WIDTH 1 | ||
| 2514 | #define R_PAR0_CTRL_DATA__strb__active 1 | ||
| 2515 | #define R_PAR0_CTRL_DATA__strb__inactive 0 | ||
| 2516 | #define R_PAR0_CTRL_DATA__init__BITNR 16 | ||
| 2517 | #define R_PAR0_CTRL_DATA__init__WIDTH 1 | ||
| 2518 | #define R_PAR0_CTRL_DATA__init__active 1 | ||
| 2519 | #define R_PAR0_CTRL_DATA__init__inactive 0 | ||
| 2520 | #define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 | ||
| 2521 | #define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 | ||
| 2522 | #define R_PAR0_CTRL_DATA__ecp_cmd__command 1 | ||
| 2523 | #define R_PAR0_CTRL_DATA__ecp_cmd__data 0 | ||
| 2524 | #define R_PAR0_CTRL_DATA__data__BITNR 0 | ||
| 2525 | #define R_PAR0_CTRL_DATA__data__WIDTH 8 | ||
| 2526 | |||
| 2527 | #define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) | ||
| 2528 | #define R_PAR0_CTRL__ctrl__BITNR 0 | ||
| 2529 | #define R_PAR0_CTRL__ctrl__WIDTH 5 | ||
| 2530 | |||
| 2531 | #define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) | ||
| 2532 | #define R_PAR0_STATUS_DATA__mode__BITNR 29 | ||
| 2533 | #define R_PAR0_STATUS_DATA__mode__WIDTH 3 | ||
| 2534 | #define R_PAR0_STATUS_DATA__mode__manual 0 | ||
| 2535 | #define R_PAR0_STATUS_DATA__mode__centronics 1 | ||
| 2536 | #define R_PAR0_STATUS_DATA__mode__fastbyte 2 | ||
| 2537 | #define R_PAR0_STATUS_DATA__mode__nibble 3 | ||
| 2538 | #define R_PAR0_STATUS_DATA__mode__byte 4 | ||
| 2539 | #define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 | ||
| 2540 | #define R_PAR0_STATUS_DATA__mode__ecp_rev 6 | ||
| 2541 | #define R_PAR0_STATUS_DATA__mode__off 7 | ||
| 2542 | #define R_PAR0_STATUS_DATA__mode__epp_wr1 5 | ||
| 2543 | #define R_PAR0_STATUS_DATA__mode__epp_wr2 6 | ||
| 2544 | #define R_PAR0_STATUS_DATA__mode__epp_wr3 7 | ||
| 2545 | #define R_PAR0_STATUS_DATA__mode__epp_rd 0 | ||
| 2546 | #define R_PAR0_STATUS_DATA__perr__BITNR 28 | ||
| 2547 | #define R_PAR0_STATUS_DATA__perr__WIDTH 1 | ||
| 2548 | #define R_PAR0_STATUS_DATA__perr__active 1 | ||
| 2549 | #define R_PAR0_STATUS_DATA__perr__inactive 0 | ||
| 2550 | #define R_PAR0_STATUS_DATA__ack__BITNR 27 | ||
| 2551 | #define R_PAR0_STATUS_DATA__ack__WIDTH 1 | ||
| 2552 | #define R_PAR0_STATUS_DATA__ack__active 0 | ||
| 2553 | #define R_PAR0_STATUS_DATA__ack__inactive 1 | ||
| 2554 | #define R_PAR0_STATUS_DATA__busy__BITNR 26 | ||
| 2555 | #define R_PAR0_STATUS_DATA__busy__WIDTH 1 | ||
| 2556 | #define R_PAR0_STATUS_DATA__busy__active 1 | ||
| 2557 | #define R_PAR0_STATUS_DATA__busy__inactive 0 | ||
| 2558 | #define R_PAR0_STATUS_DATA__fault__BITNR 25 | ||
| 2559 | #define R_PAR0_STATUS_DATA__fault__WIDTH 1 | ||
| 2560 | #define R_PAR0_STATUS_DATA__fault__active 0 | ||
| 2561 | #define R_PAR0_STATUS_DATA__fault__inactive 1 | ||
| 2562 | #define R_PAR0_STATUS_DATA__sel__BITNR 24 | ||
| 2563 | #define R_PAR0_STATUS_DATA__sel__WIDTH 1 | ||
| 2564 | #define R_PAR0_STATUS_DATA__sel__active 1 | ||
| 2565 | #define R_PAR0_STATUS_DATA__sel__inactive 0 | ||
| 2566 | #define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 | ||
| 2567 | #define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 | ||
| 2568 | #define R_PAR0_STATUS_DATA__ext_mode__enable 1 | ||
| 2569 | #define R_PAR0_STATUS_DATA__ext_mode__disable 0 | ||
| 2570 | #define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 | ||
| 2571 | #define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 | ||
| 2572 | #define R_PAR0_STATUS_DATA__ecp_16__active 1 | ||
| 2573 | #define R_PAR0_STATUS_DATA__ecp_16__inactive 0 | ||
| 2574 | #define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 | ||
| 2575 | #define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 | ||
| 2576 | #define R_PAR0_STATUS_DATA__tr_rdy__ready 1 | ||
| 2577 | #define R_PAR0_STATUS_DATA__tr_rdy__busy 0 | ||
| 2578 | #define R_PAR0_STATUS_DATA__dav__BITNR 16 | ||
| 2579 | #define R_PAR0_STATUS_DATA__dav__WIDTH 1 | ||
| 2580 | #define R_PAR0_STATUS_DATA__dav__data 1 | ||
| 2581 | #define R_PAR0_STATUS_DATA__dav__nodata 0 | ||
| 2582 | #define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 | ||
| 2583 | #define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 | ||
| 2584 | #define R_PAR0_STATUS_DATA__ecp_cmd__command 1 | ||
| 2585 | #define R_PAR0_STATUS_DATA__ecp_cmd__data 0 | ||
| 2586 | #define R_PAR0_STATUS_DATA__data__BITNR 0 | ||
| 2587 | #define R_PAR0_STATUS_DATA__data__WIDTH 8 | ||
| 2588 | |||
| 2589 | #define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) | ||
| 2590 | #define R_PAR0_STATUS__mode__BITNR 13 | ||
| 2591 | #define R_PAR0_STATUS__mode__WIDTH 3 | ||
| 2592 | #define R_PAR0_STATUS__mode__manual 0 | ||
| 2593 | #define R_PAR0_STATUS__mode__centronics 1 | ||
| 2594 | #define R_PAR0_STATUS__mode__fastbyte 2 | ||
| 2595 | #define R_PAR0_STATUS__mode__nibble 3 | ||
| 2596 | #define R_PAR0_STATUS__mode__byte 4 | ||
| 2597 | #define R_PAR0_STATUS__mode__ecp_fwd 5 | ||
| 2598 | #define R_PAR0_STATUS__mode__ecp_rev 6 | ||
| 2599 | #define R_PAR0_STATUS__mode__off 7 | ||
| 2600 | #define R_PAR0_STATUS__mode__epp_wr1 5 | ||
| 2601 | #define R_PAR0_STATUS__mode__epp_wr2 6 | ||
| 2602 | #define R_PAR0_STATUS__mode__epp_wr3 7 | ||
| 2603 | #define R_PAR0_STATUS__mode__epp_rd 0 | ||
| 2604 | #define R_PAR0_STATUS__perr__BITNR 12 | ||
| 2605 | #define R_PAR0_STATUS__perr__WIDTH 1 | ||
| 2606 | #define R_PAR0_STATUS__perr__active 1 | ||
| 2607 | #define R_PAR0_STATUS__perr__inactive 0 | ||
| 2608 | #define R_PAR0_STATUS__ack__BITNR 11 | ||
| 2609 | #define R_PAR0_STATUS__ack__WIDTH 1 | ||
| 2610 | #define R_PAR0_STATUS__ack__active 0 | ||
| 2611 | #define R_PAR0_STATUS__ack__inactive 1 | ||
| 2612 | #define R_PAR0_STATUS__busy__BITNR 10 | ||
| 2613 | #define R_PAR0_STATUS__busy__WIDTH 1 | ||
| 2614 | #define R_PAR0_STATUS__busy__active 1 | ||
| 2615 | #define R_PAR0_STATUS__busy__inactive 0 | ||
| 2616 | #define R_PAR0_STATUS__fault__BITNR 9 | ||
| 2617 | #define R_PAR0_STATUS__fault__WIDTH 1 | ||
| 2618 | #define R_PAR0_STATUS__fault__active 0 | ||
| 2619 | #define R_PAR0_STATUS__fault__inactive 1 | ||
| 2620 | #define R_PAR0_STATUS__sel__BITNR 8 | ||
| 2621 | #define R_PAR0_STATUS__sel__WIDTH 1 | ||
| 2622 | #define R_PAR0_STATUS__sel__active 1 | ||
| 2623 | #define R_PAR0_STATUS__sel__inactive 0 | ||
| 2624 | #define R_PAR0_STATUS__ext_mode__BITNR 7 | ||
| 2625 | #define R_PAR0_STATUS__ext_mode__WIDTH 1 | ||
| 2626 | #define R_PAR0_STATUS__ext_mode__enable 1 | ||
| 2627 | #define R_PAR0_STATUS__ext_mode__disable 0 | ||
| 2628 | #define R_PAR0_STATUS__ecp_16__BITNR 6 | ||
| 2629 | #define R_PAR0_STATUS__ecp_16__WIDTH 1 | ||
| 2630 | #define R_PAR0_STATUS__ecp_16__active 1 | ||
| 2631 | #define R_PAR0_STATUS__ecp_16__inactive 0 | ||
| 2632 | #define R_PAR0_STATUS__tr_rdy__BITNR 1 | ||
| 2633 | #define R_PAR0_STATUS__tr_rdy__WIDTH 1 | ||
| 2634 | #define R_PAR0_STATUS__tr_rdy__ready 1 | ||
| 2635 | #define R_PAR0_STATUS__tr_rdy__busy 0 | ||
| 2636 | #define R_PAR0_STATUS__dav__BITNR 0 | ||
| 2637 | #define R_PAR0_STATUS__dav__WIDTH 1 | ||
| 2638 | #define R_PAR0_STATUS__dav__data 1 | ||
| 2639 | #define R_PAR0_STATUS__dav__nodata 0 | ||
| 2640 | |||
| 2641 | #define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) | ||
| 2642 | #define R_PAR_ECP16_DATA__data__BITNR 0 | ||
| 2643 | #define R_PAR_ECP16_DATA__data__WIDTH 16 | ||
| 2644 | |||
| 2645 | #define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) | ||
| 2646 | #define R_PAR0_CONFIG__ioe__BITNR 25 | ||
| 2647 | #define R_PAR0_CONFIG__ioe__WIDTH 1 | ||
| 2648 | #define R_PAR0_CONFIG__ioe__inv 1 | ||
| 2649 | #define R_PAR0_CONFIG__ioe__noninv 0 | ||
| 2650 | #define R_PAR0_CONFIG__iseli__BITNR 24 | ||
| 2651 | #define R_PAR0_CONFIG__iseli__WIDTH 1 | ||
| 2652 | #define R_PAR0_CONFIG__iseli__inv 1 | ||
| 2653 | #define R_PAR0_CONFIG__iseli__noninv 0 | ||
| 2654 | #define R_PAR0_CONFIG__iautofd__BITNR 23 | ||
| 2655 | #define R_PAR0_CONFIG__iautofd__WIDTH 1 | ||
| 2656 | #define R_PAR0_CONFIG__iautofd__inv 1 | ||
| 2657 | #define R_PAR0_CONFIG__iautofd__noninv 0 | ||
| 2658 | #define R_PAR0_CONFIG__istrb__BITNR 22 | ||
| 2659 | #define R_PAR0_CONFIG__istrb__WIDTH 1 | ||
| 2660 | #define R_PAR0_CONFIG__istrb__inv 1 | ||
| 2661 | #define R_PAR0_CONFIG__istrb__noninv 0 | ||
| 2662 | #define R_PAR0_CONFIG__iinit__BITNR 21 | ||
| 2663 | #define R_PAR0_CONFIG__iinit__WIDTH 1 | ||
| 2664 | #define R_PAR0_CONFIG__iinit__inv 1 | ||
| 2665 | #define R_PAR0_CONFIG__iinit__noninv 0 | ||
| 2666 | #define R_PAR0_CONFIG__iperr__BITNR 20 | ||
| 2667 | #define R_PAR0_CONFIG__iperr__WIDTH 1 | ||
| 2668 | #define R_PAR0_CONFIG__iperr__inv 1 | ||
| 2669 | #define R_PAR0_CONFIG__iperr__noninv 0 | ||
| 2670 | #define R_PAR0_CONFIG__iack__BITNR 19 | ||
| 2671 | #define R_PAR0_CONFIG__iack__WIDTH 1 | ||
| 2672 | #define R_PAR0_CONFIG__iack__inv 1 | ||
| 2673 | #define R_PAR0_CONFIG__iack__noninv 0 | ||
| 2674 | #define R_PAR0_CONFIG__ibusy__BITNR 18 | ||
| 2675 | #define R_PAR0_CONFIG__ibusy__WIDTH 1 | ||
| 2676 | #define R_PAR0_CONFIG__ibusy__inv 1 | ||
| 2677 | #define R_PAR0_CONFIG__ibusy__noninv 0 | ||
| 2678 | #define R_PAR0_CONFIG__ifault__BITNR 17 | ||
| 2679 | #define R_PAR0_CONFIG__ifault__WIDTH 1 | ||
| 2680 | #define R_PAR0_CONFIG__ifault__inv 1 | ||
| 2681 | #define R_PAR0_CONFIG__ifault__noninv 0 | ||
| 2682 | #define R_PAR0_CONFIG__isel__BITNR 16 | ||
| 2683 | #define R_PAR0_CONFIG__isel__WIDTH 1 | ||
| 2684 | #define R_PAR0_CONFIG__isel__inv 1 | ||
| 2685 | #define R_PAR0_CONFIG__isel__noninv 0 | ||
| 2686 | #define R_PAR0_CONFIG__ext_mode__BITNR 11 | ||
| 2687 | #define R_PAR0_CONFIG__ext_mode__WIDTH 1 | ||
| 2688 | #define R_PAR0_CONFIG__ext_mode__enable 1 | ||
| 2689 | #define R_PAR0_CONFIG__ext_mode__disable 0 | ||
| 2690 | #define R_PAR0_CONFIG__wide__BITNR 10 | ||
| 2691 | #define R_PAR0_CONFIG__wide__WIDTH 1 | ||
| 2692 | #define R_PAR0_CONFIG__wide__enable 1 | ||
| 2693 | #define R_PAR0_CONFIG__wide__disable 0 | ||
| 2694 | #define R_PAR0_CONFIG__dma__BITNR 9 | ||
| 2695 | #define R_PAR0_CONFIG__dma__WIDTH 1 | ||
| 2696 | #define R_PAR0_CONFIG__dma__enable 1 | ||
| 2697 | #define R_PAR0_CONFIG__dma__disable 0 | ||
| 2698 | #define R_PAR0_CONFIG__rle_in__BITNR 8 | ||
| 2699 | #define R_PAR0_CONFIG__rle_in__WIDTH 1 | ||
| 2700 | #define R_PAR0_CONFIG__rle_in__enable 1 | ||
| 2701 | #define R_PAR0_CONFIG__rle_in__disable 0 | ||
| 2702 | #define R_PAR0_CONFIG__rle_out__BITNR 7 | ||
| 2703 | #define R_PAR0_CONFIG__rle_out__WIDTH 1 | ||
| 2704 | #define R_PAR0_CONFIG__rle_out__enable 1 | ||
| 2705 | #define R_PAR0_CONFIG__rle_out__disable 0 | ||
| 2706 | #define R_PAR0_CONFIG__enable__BITNR 6 | ||
| 2707 | #define R_PAR0_CONFIG__enable__WIDTH 1 | ||
| 2708 | #define R_PAR0_CONFIG__enable__on 1 | ||
| 2709 | #define R_PAR0_CONFIG__enable__reset 0 | ||
| 2710 | #define R_PAR0_CONFIG__force__BITNR 5 | ||
| 2711 | #define R_PAR0_CONFIG__force__WIDTH 1 | ||
| 2712 | #define R_PAR0_CONFIG__force__on 1 | ||
| 2713 | #define R_PAR0_CONFIG__force__off 0 | ||
| 2714 | #define R_PAR0_CONFIG__ign_ack__BITNR 4 | ||
| 2715 | #define R_PAR0_CONFIG__ign_ack__WIDTH 1 | ||
| 2716 | #define R_PAR0_CONFIG__ign_ack__ignore 1 | ||
| 2717 | #define R_PAR0_CONFIG__ign_ack__wait 0 | ||
| 2718 | #define R_PAR0_CONFIG__oe_ack__BITNR 3 | ||
| 2719 | #define R_PAR0_CONFIG__oe_ack__WIDTH 1 | ||
| 2720 | #define R_PAR0_CONFIG__oe_ack__wait_oe 1 | ||
| 2721 | #define R_PAR0_CONFIG__oe_ack__dont_wait 0 | ||
| 2722 | #define R_PAR0_CONFIG__oe_ack__epp_addr 1 | ||
| 2723 | #define R_PAR0_CONFIG__oe_ack__epp_data 0 | ||
| 2724 | #define R_PAR0_CONFIG__epp_addr_data__BITNR 3 | ||
| 2725 | #define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 | ||
| 2726 | #define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 | ||
| 2727 | #define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 | ||
| 2728 | #define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 | ||
| 2729 | #define R_PAR0_CONFIG__epp_addr_data__epp_data 0 | ||
| 2730 | #define R_PAR0_CONFIG__mode__BITNR 0 | ||
| 2731 | #define R_PAR0_CONFIG__mode__WIDTH 3 | ||
| 2732 | #define R_PAR0_CONFIG__mode__manual 0 | ||
| 2733 | #define R_PAR0_CONFIG__mode__centronics 1 | ||
| 2734 | #define R_PAR0_CONFIG__mode__fastbyte 2 | ||
| 2735 | #define R_PAR0_CONFIG__mode__nibble 3 | ||
| 2736 | #define R_PAR0_CONFIG__mode__byte 4 | ||
| 2737 | #define R_PAR0_CONFIG__mode__ecp_fwd 5 | ||
| 2738 | #define R_PAR0_CONFIG__mode__ecp_rev 6 | ||
| 2739 | #define R_PAR0_CONFIG__mode__off 7 | ||
| 2740 | #define R_PAR0_CONFIG__mode__epp_wr1 5 | ||
| 2741 | #define R_PAR0_CONFIG__mode__epp_wr2 6 | ||
| 2742 | #define R_PAR0_CONFIG__mode__epp_wr3 7 | ||
| 2743 | #define R_PAR0_CONFIG__mode__epp_rd 0 | ||
| 2744 | |||
| 2745 | #define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) | ||
| 2746 | #define R_PAR0_DELAY__fine_hold__BITNR 21 | ||
| 2747 | #define R_PAR0_DELAY__fine_hold__WIDTH 3 | ||
| 2748 | #define R_PAR0_DELAY__hold__BITNR 16 | ||
| 2749 | #define R_PAR0_DELAY__hold__WIDTH 5 | ||
| 2750 | #define R_PAR0_DELAY__fine_strb__BITNR 13 | ||
| 2751 | #define R_PAR0_DELAY__fine_strb__WIDTH 3 | ||
| 2752 | #define R_PAR0_DELAY__strobe__BITNR 8 | ||
| 2753 | #define R_PAR0_DELAY__strobe__WIDTH 5 | ||
| 2754 | #define R_PAR0_DELAY__fine_setup__BITNR 5 | ||
| 2755 | #define R_PAR0_DELAY__fine_setup__WIDTH 3 | ||
| 2756 | #define R_PAR0_DELAY__setup__BITNR 0 | ||
| 2757 | #define R_PAR0_DELAY__setup__WIDTH 5 | ||
| 2758 | |||
| 2759 | #define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) | ||
| 2760 | #define R_PAR1_CTRL_DATA__peri_int__BITNR 24 | ||
| 2761 | #define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 | ||
| 2762 | #define R_PAR1_CTRL_DATA__peri_int__ack 1 | ||
| 2763 | #define R_PAR1_CTRL_DATA__peri_int__nop 0 | ||
| 2764 | #define R_PAR1_CTRL_DATA__oe__BITNR 20 | ||
| 2765 | #define R_PAR1_CTRL_DATA__oe__WIDTH 1 | ||
| 2766 | #define R_PAR1_CTRL_DATA__oe__enable 1 | ||
| 2767 | #define R_PAR1_CTRL_DATA__oe__disable 0 | ||
| 2768 | #define R_PAR1_CTRL_DATA__seli__BITNR 19 | ||
| 2769 | #define R_PAR1_CTRL_DATA__seli__WIDTH 1 | ||
| 2770 | #define R_PAR1_CTRL_DATA__seli__active 1 | ||
| 2771 | #define R_PAR1_CTRL_DATA__seli__inactive 0 | ||
| 2772 | #define R_PAR1_CTRL_DATA__autofd__BITNR 18 | ||
| 2773 | #define R_PAR1_CTRL_DATA__autofd__WIDTH 1 | ||
| 2774 | #define R_PAR1_CTRL_DATA__autofd__active 1 | ||
| 2775 | #define R_PAR1_CTRL_DATA__autofd__inactive 0 | ||
| 2776 | #define R_PAR1_CTRL_DATA__strb__BITNR 17 | ||
| 2777 | #define R_PAR1_CTRL_DATA__strb__WIDTH 1 | ||
| 2778 | #define R_PAR1_CTRL_DATA__strb__active 1 | ||
| 2779 | #define R_PAR1_CTRL_DATA__strb__inactive 0 | ||
| 2780 | #define R_PAR1_CTRL_DATA__init__BITNR 16 | ||
| 2781 | #define R_PAR1_CTRL_DATA__init__WIDTH 1 | ||
| 2782 | #define R_PAR1_CTRL_DATA__init__active 1 | ||
| 2783 | #define R_PAR1_CTRL_DATA__init__inactive 0 | ||
| 2784 | #define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 | ||
| 2785 | #define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 | ||
| 2786 | #define R_PAR1_CTRL_DATA__ecp_cmd__command 1 | ||
| 2787 | #define R_PAR1_CTRL_DATA__ecp_cmd__data 0 | ||
| 2788 | #define R_PAR1_CTRL_DATA__data__BITNR 0 | ||
| 2789 | #define R_PAR1_CTRL_DATA__data__WIDTH 8 | ||
| 2790 | |||
| 2791 | #define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) | ||
| 2792 | #define R_PAR1_CTRL__ctrl__BITNR 0 | ||
| 2793 | #define R_PAR1_CTRL__ctrl__WIDTH 5 | ||
| 2794 | |||
| 2795 | #define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) | ||
| 2796 | #define R_PAR1_STATUS_DATA__mode__BITNR 29 | ||
| 2797 | #define R_PAR1_STATUS_DATA__mode__WIDTH 3 | ||
| 2798 | #define R_PAR1_STATUS_DATA__mode__manual 0 | ||
| 2799 | #define R_PAR1_STATUS_DATA__mode__centronics 1 | ||
| 2800 | #define R_PAR1_STATUS_DATA__mode__fastbyte 2 | ||
| 2801 | #define R_PAR1_STATUS_DATA__mode__nibble 3 | ||
| 2802 | #define R_PAR1_STATUS_DATA__mode__byte 4 | ||
| 2803 | #define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 | ||
| 2804 | #define R_PAR1_STATUS_DATA__mode__ecp_rev 6 | ||
| 2805 | #define R_PAR1_STATUS_DATA__mode__off 7 | ||
| 2806 | #define R_PAR1_STATUS_DATA__mode__epp_wr1 5 | ||
| 2807 | #define R_PAR1_STATUS_DATA__mode__epp_wr2 6 | ||
| 2808 | #define R_PAR1_STATUS_DATA__mode__epp_wr3 7 | ||
| 2809 | #define R_PAR1_STATUS_DATA__mode__epp_rd 0 | ||
| 2810 | #define R_PAR1_STATUS_DATA__perr__BITNR 28 | ||
| 2811 | #define R_PAR1_STATUS_DATA__perr__WIDTH 1 | ||
| 2812 | #define R_PAR1_STATUS_DATA__perr__active 1 | ||
| 2813 | #define R_PAR1_STATUS_DATA__perr__inactive 0 | ||
| 2814 | #define R_PAR1_STATUS_DATA__ack__BITNR 27 | ||
| 2815 | #define R_PAR1_STATUS_DATA__ack__WIDTH 1 | ||
| 2816 | #define R_PAR1_STATUS_DATA__ack__active 0 | ||
| 2817 | #define R_PAR1_STATUS_DATA__ack__inactive 1 | ||
| 2818 | #define R_PAR1_STATUS_DATA__busy__BITNR 26 | ||
| 2819 | #define R_PAR1_STATUS_DATA__busy__WIDTH 1 | ||
| 2820 | #define R_PAR1_STATUS_DATA__busy__active 1 | ||
| 2821 | #define R_PAR1_STATUS_DATA__busy__inactive 0 | ||
| 2822 | #define R_PAR1_STATUS_DATA__fault__BITNR 25 | ||
| 2823 | #define R_PAR1_STATUS_DATA__fault__WIDTH 1 | ||
| 2824 | #define R_PAR1_STATUS_DATA__fault__active 0 | ||
| 2825 | #define R_PAR1_STATUS_DATA__fault__inactive 1 | ||
| 2826 | #define R_PAR1_STATUS_DATA__sel__BITNR 24 | ||
| 2827 | #define R_PAR1_STATUS_DATA__sel__WIDTH 1 | ||
| 2828 | #define R_PAR1_STATUS_DATA__sel__active 1 | ||
| 2829 | #define R_PAR1_STATUS_DATA__sel__inactive 0 | ||
| 2830 | #define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 | ||
| 2831 | #define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 | ||
| 2832 | #define R_PAR1_STATUS_DATA__ext_mode__enable 1 | ||
| 2833 | #define R_PAR1_STATUS_DATA__ext_mode__disable 0 | ||
| 2834 | #define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 | ||
| 2835 | #define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 | ||
| 2836 | #define R_PAR1_STATUS_DATA__tr_rdy__ready 1 | ||
| 2837 | #define R_PAR1_STATUS_DATA__tr_rdy__busy 0 | ||
| 2838 | #define R_PAR1_STATUS_DATA__dav__BITNR 16 | ||
| 2839 | #define R_PAR1_STATUS_DATA__dav__WIDTH 1 | ||
| 2840 | #define R_PAR1_STATUS_DATA__dav__data 1 | ||
| 2841 | #define R_PAR1_STATUS_DATA__dav__nodata 0 | ||
| 2842 | #define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 | ||
| 2843 | #define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 | ||
| 2844 | #define R_PAR1_STATUS_DATA__ecp_cmd__command 1 | ||
| 2845 | #define R_PAR1_STATUS_DATA__ecp_cmd__data 0 | ||
| 2846 | #define R_PAR1_STATUS_DATA__data__BITNR 0 | ||
| 2847 | #define R_PAR1_STATUS_DATA__data__WIDTH 8 | ||
| 2848 | |||
| 2849 | #define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) | ||
| 2850 | #define R_PAR1_STATUS__mode__BITNR 13 | ||
| 2851 | #define R_PAR1_STATUS__mode__WIDTH 3 | ||
| 2852 | #define R_PAR1_STATUS__mode__manual 0 | ||
| 2853 | #define R_PAR1_STATUS__mode__centronics 1 | ||
| 2854 | #define R_PAR1_STATUS__mode__fastbyte 2 | ||
| 2855 | #define R_PAR1_STATUS__mode__nibble 3 | ||
| 2856 | #define R_PAR1_STATUS__mode__byte 4 | ||
| 2857 | #define R_PAR1_STATUS__mode__ecp_fwd 5 | ||
| 2858 | #define R_PAR1_STATUS__mode__ecp_rev 6 | ||
| 2859 | #define R_PAR1_STATUS__mode__off 7 | ||
| 2860 | #define R_PAR1_STATUS__mode__epp_wr1 5 | ||
| 2861 | #define R_PAR1_STATUS__mode__epp_wr2 6 | ||
| 2862 | #define R_PAR1_STATUS__mode__epp_wr3 7 | ||
| 2863 | #define R_PAR1_STATUS__mode__epp_rd 0 | ||
| 2864 | #define R_PAR1_STATUS__perr__BITNR 12 | ||
| 2865 | #define R_PAR1_STATUS__perr__WIDTH 1 | ||
| 2866 | #define R_PAR1_STATUS__perr__active 1 | ||
| 2867 | #define R_PAR1_STATUS__perr__inactive 0 | ||
| 2868 | #define R_PAR1_STATUS__ack__BITNR 11 | ||
| 2869 | #define R_PAR1_STATUS__ack__WIDTH 1 | ||
| 2870 | #define R_PAR1_STATUS__ack__active 0 | ||
| 2871 | #define R_PAR1_STATUS__ack__inactive 1 | ||
| 2872 | #define R_PAR1_STATUS__busy__BITNR 10 | ||
| 2873 | #define R_PAR1_STATUS__busy__WIDTH 1 | ||
| 2874 | #define R_PAR1_STATUS__busy__active 1 | ||
| 2875 | #define R_PAR1_STATUS__busy__inactive 0 | ||
| 2876 | #define R_PAR1_STATUS__fault__BITNR 9 | ||
| 2877 | #define R_PAR1_STATUS__fault__WIDTH 1 | ||
| 2878 | #define R_PAR1_STATUS__fault__active 0 | ||
| 2879 | #define R_PAR1_STATUS__fault__inactive 1 | ||
| 2880 | #define R_PAR1_STATUS__sel__BITNR 8 | ||
| 2881 | #define R_PAR1_STATUS__sel__WIDTH 1 | ||
| 2882 | #define R_PAR1_STATUS__sel__active 1 | ||
| 2883 | #define R_PAR1_STATUS__sel__inactive 0 | ||
| 2884 | #define R_PAR1_STATUS__ext_mode__BITNR 7 | ||
| 2885 | #define R_PAR1_STATUS__ext_mode__WIDTH 1 | ||
| 2886 | #define R_PAR1_STATUS__ext_mode__enable 1 | ||
| 2887 | #define R_PAR1_STATUS__ext_mode__disable 0 | ||
| 2888 | #define R_PAR1_STATUS__tr_rdy__BITNR 1 | ||
| 2889 | #define R_PAR1_STATUS__tr_rdy__WIDTH 1 | ||
| 2890 | #define R_PAR1_STATUS__tr_rdy__ready 1 | ||
| 2891 | #define R_PAR1_STATUS__tr_rdy__busy 0 | ||
| 2892 | #define R_PAR1_STATUS__dav__BITNR 0 | ||
| 2893 | #define R_PAR1_STATUS__dav__WIDTH 1 | ||
| 2894 | #define R_PAR1_STATUS__dav__data 1 | ||
| 2895 | #define R_PAR1_STATUS__dav__nodata 0 | ||
| 2896 | |||
| 2897 | #define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) | ||
| 2898 | #define R_PAR1_CONFIG__ioe__BITNR 25 | ||
| 2899 | #define R_PAR1_CONFIG__ioe__WIDTH 1 | ||
| 2900 | #define R_PAR1_CONFIG__ioe__inv 1 | ||
| 2901 | #define R_PAR1_CONFIG__ioe__noninv 0 | ||
| 2902 | #define R_PAR1_CONFIG__iseli__BITNR 24 | ||
| 2903 | #define R_PAR1_CONFIG__iseli__WIDTH 1 | ||
| 2904 | #define R_PAR1_CONFIG__iseli__inv 1 | ||
| 2905 | #define R_PAR1_CONFIG__iseli__noninv 0 | ||
| 2906 | #define R_PAR1_CONFIG__iautofd__BITNR 23 | ||
| 2907 | #define R_PAR1_CONFIG__iautofd__WIDTH 1 | ||
| 2908 | #define R_PAR1_CONFIG__iautofd__inv 1 | ||
| 2909 | #define R_PAR1_CONFIG__iautofd__noninv 0 | ||
| 2910 | #define R_PAR1_CONFIG__istrb__BITNR 22 | ||
| 2911 | #define R_PAR1_CONFIG__istrb__WIDTH 1 | ||
| 2912 | #define R_PAR1_CONFIG__istrb__inv 1 | ||
| 2913 | #define R_PAR1_CONFIG__istrb__noninv 0 | ||
| 2914 | #define R_PAR1_CONFIG__iinit__BITNR 21 | ||
| 2915 | #define R_PAR1_CONFIG__iinit__WIDTH 1 | ||
| 2916 | #define R_PAR1_CONFIG__iinit__inv 1 | ||
| 2917 | #define R_PAR1_CONFIG__iinit__noninv 0 | ||
| 2918 | #define R_PAR1_CONFIG__iperr__BITNR 20 | ||
| 2919 | #define R_PAR1_CONFIG__iperr__WIDTH 1 | ||
| 2920 | #define R_PAR1_CONFIG__iperr__inv 1 | ||
| 2921 | #define R_PAR1_CONFIG__iperr__noninv 0 | ||
| 2922 | #define R_PAR1_CONFIG__iack__BITNR 19 | ||
| 2923 | #define R_PAR1_CONFIG__iack__WIDTH 1 | ||
| 2924 | #define R_PAR1_CONFIG__iack__inv 1 | ||
| 2925 | #define R_PAR1_CONFIG__iack__noninv 0 | ||
| 2926 | #define R_PAR1_CONFIG__ibusy__BITNR 18 | ||
| 2927 | #define R_PAR1_CONFIG__ibusy__WIDTH 1 | ||
| 2928 | #define R_PAR1_CONFIG__ibusy__inv 1 | ||
| 2929 | #define R_PAR1_CONFIG__ibusy__noninv 0 | ||
| 2930 | #define R_PAR1_CONFIG__ifault__BITNR 17 | ||
| 2931 | #define R_PAR1_CONFIG__ifault__WIDTH 1 | ||
| 2932 | #define R_PAR1_CONFIG__ifault__inv 1 | ||
| 2933 | #define R_PAR1_CONFIG__ifault__noninv 0 | ||
| 2934 | #define R_PAR1_CONFIG__isel__BITNR 16 | ||
| 2935 | #define R_PAR1_CONFIG__isel__WIDTH 1 | ||
| 2936 | #define R_PAR1_CONFIG__isel__inv 1 | ||
| 2937 | #define R_PAR1_CONFIG__isel__noninv 0 | ||
| 2938 | #define R_PAR1_CONFIG__ext_mode__BITNR 11 | ||
| 2939 | #define R_PAR1_CONFIG__ext_mode__WIDTH 1 | ||
| 2940 | #define R_PAR1_CONFIG__ext_mode__enable 1 | ||
| 2941 | #define R_PAR1_CONFIG__ext_mode__disable 0 | ||
| 2942 | #define R_PAR1_CONFIG__dma__BITNR 9 | ||
| 2943 | #define R_PAR1_CONFIG__dma__WIDTH 1 | ||
| 2944 | #define R_PAR1_CONFIG__dma__enable 1 | ||
| 2945 | #define R_PAR1_CONFIG__dma__disable 0 | ||
| 2946 | #define R_PAR1_CONFIG__rle_in__BITNR 8 | ||
| 2947 | #define R_PAR1_CONFIG__rle_in__WIDTH 1 | ||
| 2948 | #define R_PAR1_CONFIG__rle_in__enable 1 | ||
| 2949 | #define R_PAR1_CONFIG__rle_in__disable 0 | ||
| 2950 | #define R_PAR1_CONFIG__rle_out__BITNR 7 | ||
| 2951 | #define R_PAR1_CONFIG__rle_out__WIDTH 1 | ||
| 2952 | #define R_PAR1_CONFIG__rle_out__enable 1 | ||
| 2953 | #define R_PAR1_CONFIG__rle_out__disable 0 | ||
| 2954 | #define R_PAR1_CONFIG__enable__BITNR 6 | ||
| 2955 | #define R_PAR1_CONFIG__enable__WIDTH 1 | ||
| 2956 | #define R_PAR1_CONFIG__enable__on 1 | ||
| 2957 | #define R_PAR1_CONFIG__enable__reset 0 | ||
| 2958 | #define R_PAR1_CONFIG__force__BITNR 5 | ||
| 2959 | #define R_PAR1_CONFIG__force__WIDTH 1 | ||
| 2960 | #define R_PAR1_CONFIG__force__on 1 | ||
| 2961 | #define R_PAR1_CONFIG__force__off 0 | ||
| 2962 | #define R_PAR1_CONFIG__ign_ack__BITNR 4 | ||
| 2963 | #define R_PAR1_CONFIG__ign_ack__WIDTH 1 | ||
| 2964 | #define R_PAR1_CONFIG__ign_ack__ignore 1 | ||
| 2965 | #define R_PAR1_CONFIG__ign_ack__wait 0 | ||
| 2966 | #define R_PAR1_CONFIG__oe_ack__BITNR 3 | ||
| 2967 | #define R_PAR1_CONFIG__oe_ack__WIDTH 1 | ||
| 2968 | #define R_PAR1_CONFIG__oe_ack__wait_oe 1 | ||
| 2969 | #define R_PAR1_CONFIG__oe_ack__dont_wait 0 | ||
| 2970 | #define R_PAR1_CONFIG__oe_ack__epp_addr 1 | ||
| 2971 | #define R_PAR1_CONFIG__oe_ack__epp_data 0 | ||
| 2972 | #define R_PAR1_CONFIG__epp_addr_data__BITNR 3 | ||
| 2973 | #define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 | ||
| 2974 | #define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 | ||
| 2975 | #define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 | ||
| 2976 | #define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 | ||
| 2977 | #define R_PAR1_CONFIG__epp_addr_data__epp_data 0 | ||
| 2978 | #define R_PAR1_CONFIG__mode__BITNR 0 | ||
| 2979 | #define R_PAR1_CONFIG__mode__WIDTH 3 | ||
| 2980 | #define R_PAR1_CONFIG__mode__manual 0 | ||
| 2981 | #define R_PAR1_CONFIG__mode__centronics 1 | ||
| 2982 | #define R_PAR1_CONFIG__mode__fastbyte 2 | ||
| 2983 | #define R_PAR1_CONFIG__mode__nibble 3 | ||
| 2984 | #define R_PAR1_CONFIG__mode__byte 4 | ||
| 2985 | #define R_PAR1_CONFIG__mode__ecp_fwd 5 | ||
| 2986 | #define R_PAR1_CONFIG__mode__ecp_rev 6 | ||
| 2987 | #define R_PAR1_CONFIG__mode__off 7 | ||
| 2988 | #define R_PAR1_CONFIG__mode__epp_wr1 5 | ||
| 2989 | #define R_PAR1_CONFIG__mode__epp_wr2 6 | ||
| 2990 | #define R_PAR1_CONFIG__mode__epp_wr3 7 | ||
| 2991 | #define R_PAR1_CONFIG__mode__epp_rd 0 | ||
| 2992 | |||
| 2993 | #define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) | ||
| 2994 | #define R_PAR1_DELAY__fine_hold__BITNR 21 | ||
| 2995 | #define R_PAR1_DELAY__fine_hold__WIDTH 3 | ||
| 2996 | #define R_PAR1_DELAY__hold__BITNR 16 | ||
| 2997 | #define R_PAR1_DELAY__hold__WIDTH 5 | ||
| 2998 | #define R_PAR1_DELAY__fine_strb__BITNR 13 | ||
| 2999 | #define R_PAR1_DELAY__fine_strb__WIDTH 3 | ||
| 3000 | #define R_PAR1_DELAY__strobe__BITNR 8 | ||
| 3001 | #define R_PAR1_DELAY__strobe__WIDTH 5 | ||
| 3002 | #define R_PAR1_DELAY__fine_setup__BITNR 5 | ||
| 3003 | #define R_PAR1_DELAY__fine_setup__WIDTH 3 | ||
| 3004 | #define R_PAR1_DELAY__setup__BITNR 0 | ||
| 3005 | #define R_PAR1_DELAY__setup__WIDTH 5 | ||
| 3006 | |||
| 3007 | /* | ||
| 3008 | !* ATA interface registers | ||
| 3009 | !*/ | ||
| 3010 | |||
| 3011 | #define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) | ||
| 3012 | #define R_ATA_CTRL_DATA__sel__BITNR 30 | ||
| 3013 | #define R_ATA_CTRL_DATA__sel__WIDTH 2 | ||
| 3014 | #define R_ATA_CTRL_DATA__cs1__BITNR 29 | ||
| 3015 | #define R_ATA_CTRL_DATA__cs1__WIDTH 1 | ||
| 3016 | #define R_ATA_CTRL_DATA__cs1__active 1 | ||
| 3017 | #define R_ATA_CTRL_DATA__cs1__inactive 0 | ||
| 3018 | #define R_ATA_CTRL_DATA__cs0__BITNR 28 | ||
| 3019 | #define R_ATA_CTRL_DATA__cs0__WIDTH 1 | ||
| 3020 | #define R_ATA_CTRL_DATA__cs0__active 1 | ||
| 3021 | #define R_ATA_CTRL_DATA__cs0__inactive 0 | ||
| 3022 | #define R_ATA_CTRL_DATA__addr__BITNR 25 | ||
| 3023 | #define R_ATA_CTRL_DATA__addr__WIDTH 3 | ||
| 3024 | #define R_ATA_CTRL_DATA__rw__BITNR 24 | ||
| 3025 | #define R_ATA_CTRL_DATA__rw__WIDTH 1 | ||
| 3026 | #define R_ATA_CTRL_DATA__rw__read 1 | ||
| 3027 | #define R_ATA_CTRL_DATA__rw__write 0 | ||
| 3028 | #define R_ATA_CTRL_DATA__src_dst__BITNR 23 | ||
| 3029 | #define R_ATA_CTRL_DATA__src_dst__WIDTH 1 | ||
| 3030 | #define R_ATA_CTRL_DATA__src_dst__dma 1 | ||
| 3031 | #define R_ATA_CTRL_DATA__src_dst__register 0 | ||
| 3032 | #define R_ATA_CTRL_DATA__handsh__BITNR 22 | ||
| 3033 | #define R_ATA_CTRL_DATA__handsh__WIDTH 1 | ||
| 3034 | #define R_ATA_CTRL_DATA__handsh__dma 1 | ||
| 3035 | #define R_ATA_CTRL_DATA__handsh__pio 0 | ||
| 3036 | #define R_ATA_CTRL_DATA__multi__BITNR 21 | ||
| 3037 | #define R_ATA_CTRL_DATA__multi__WIDTH 1 | ||
| 3038 | #define R_ATA_CTRL_DATA__multi__on 1 | ||
| 3039 | #define R_ATA_CTRL_DATA__multi__off 0 | ||
| 3040 | #define R_ATA_CTRL_DATA__dma_size__BITNR 20 | ||
| 3041 | #define R_ATA_CTRL_DATA__dma_size__WIDTH 1 | ||
| 3042 | #define R_ATA_CTRL_DATA__dma_size__byte 1 | ||
| 3043 | #define R_ATA_CTRL_DATA__dma_size__word 0 | ||
| 3044 | #define R_ATA_CTRL_DATA__data__BITNR 0 | ||
| 3045 | #define R_ATA_CTRL_DATA__data__WIDTH 16 | ||
| 3046 | |||
| 3047 | #define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) | ||
| 3048 | #define R_ATA_STATUS_DATA__busy__BITNR 18 | ||
| 3049 | #define R_ATA_STATUS_DATA__busy__WIDTH 1 | ||
| 3050 | #define R_ATA_STATUS_DATA__busy__yes 1 | ||
| 3051 | #define R_ATA_STATUS_DATA__busy__no 0 | ||
| 3052 | #define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 | ||
| 3053 | #define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 | ||
| 3054 | #define R_ATA_STATUS_DATA__tr_rdy__ready 1 | ||
| 3055 | #define R_ATA_STATUS_DATA__tr_rdy__busy 0 | ||
| 3056 | #define R_ATA_STATUS_DATA__dav__BITNR 16 | ||
| 3057 | #define R_ATA_STATUS_DATA__dav__WIDTH 1 | ||
| 3058 | #define R_ATA_STATUS_DATA__dav__data 1 | ||
| 3059 | #define R_ATA_STATUS_DATA__dav__nodata 0 | ||
| 3060 | #define R_ATA_STATUS_DATA__data__BITNR 0 | ||
| 3061 | #define R_ATA_STATUS_DATA__data__WIDTH 16 | ||
| 3062 | |||
| 3063 | #define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) | ||
| 3064 | #define R_ATA_CONFIG__enable__BITNR 25 | ||
| 3065 | #define R_ATA_CONFIG__enable__WIDTH 1 | ||
| 3066 | #define R_ATA_CONFIG__enable__on 1 | ||
| 3067 | #define R_ATA_CONFIG__enable__off 0 | ||
| 3068 | #define R_ATA_CONFIG__dma_strobe__BITNR 20 | ||
| 3069 | #define R_ATA_CONFIG__dma_strobe__WIDTH 5 | ||
| 3070 | #define R_ATA_CONFIG__dma_hold__BITNR 15 | ||
| 3071 | #define R_ATA_CONFIG__dma_hold__WIDTH 5 | ||
| 3072 | #define R_ATA_CONFIG__pio_setup__BITNR 10 | ||
| 3073 | #define R_ATA_CONFIG__pio_setup__WIDTH 5 | ||
| 3074 | #define R_ATA_CONFIG__pio_strobe__BITNR 5 | ||
| 3075 | #define R_ATA_CONFIG__pio_strobe__WIDTH 5 | ||
| 3076 | #define R_ATA_CONFIG__pio_hold__BITNR 0 | ||
| 3077 | #define R_ATA_CONFIG__pio_hold__WIDTH 5 | ||
| 3078 | |||
| 3079 | #define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) | ||
| 3080 | #define R_ATA_TRANSFER_CNT__count__BITNR 0 | ||
| 3081 | #define R_ATA_TRANSFER_CNT__count__WIDTH 17 | ||
| 3082 | |||
| 3083 | /* | ||
| 3084 | !* SCSI registers | ||
| 3085 | !*/ | ||
| 3086 | |||
| 3087 | #define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) | ||
| 3088 | #define R_SCSI0_CTRL__id_type__BITNR 31 | ||
| 3089 | #define R_SCSI0_CTRL__id_type__WIDTH 1 | ||
| 3090 | #define R_SCSI0_CTRL__id_type__software 1 | ||
| 3091 | #define R_SCSI0_CTRL__id_type__hardware 0 | ||
| 3092 | #define R_SCSI0_CTRL__sel_timeout__BITNR 24 | ||
| 3093 | #define R_SCSI0_CTRL__sel_timeout__WIDTH 7 | ||
| 3094 | #define R_SCSI0_CTRL__synch_per__BITNR 16 | ||
| 3095 | #define R_SCSI0_CTRL__synch_per__WIDTH 8 | ||
| 3096 | #define R_SCSI0_CTRL__rst__BITNR 15 | ||
| 3097 | #define R_SCSI0_CTRL__rst__WIDTH 1 | ||
| 3098 | #define R_SCSI0_CTRL__rst__yes 1 | ||
| 3099 | #define R_SCSI0_CTRL__rst__no 0 | ||
| 3100 | #define R_SCSI0_CTRL__atn__BITNR 14 | ||
| 3101 | #define R_SCSI0_CTRL__atn__WIDTH 1 | ||
| 3102 | #define R_SCSI0_CTRL__atn__yes 1 | ||
| 3103 | #define R_SCSI0_CTRL__atn__no 0 | ||
| 3104 | #define R_SCSI0_CTRL__my_id__BITNR 9 | ||
| 3105 | #define R_SCSI0_CTRL__my_id__WIDTH 4 | ||
| 3106 | #define R_SCSI0_CTRL__target_id__BITNR 4 | ||
| 3107 | #define R_SCSI0_CTRL__target_id__WIDTH 4 | ||
| 3108 | #define R_SCSI0_CTRL__fast_20__BITNR 3 | ||
| 3109 | #define R_SCSI0_CTRL__fast_20__WIDTH 1 | ||
| 3110 | #define R_SCSI0_CTRL__fast_20__yes 1 | ||
| 3111 | #define R_SCSI0_CTRL__fast_20__no 0 | ||
| 3112 | #define R_SCSI0_CTRL__bus_width__BITNR 2 | ||
| 3113 | #define R_SCSI0_CTRL__bus_width__WIDTH 1 | ||
| 3114 | #define R_SCSI0_CTRL__bus_width__wide 1 | ||
| 3115 | #define R_SCSI0_CTRL__bus_width__narrow 0 | ||
| 3116 | #define R_SCSI0_CTRL__synch__BITNR 1 | ||
| 3117 | #define R_SCSI0_CTRL__synch__WIDTH 1 | ||
| 3118 | #define R_SCSI0_CTRL__synch__synch 1 | ||
| 3119 | #define R_SCSI0_CTRL__synch__asynch 0 | ||
| 3120 | #define R_SCSI0_CTRL__enable__BITNR 0 | ||
| 3121 | #define R_SCSI0_CTRL__enable__WIDTH 1 | ||
| 3122 | #define R_SCSI0_CTRL__enable__on 1 | ||
| 3123 | #define R_SCSI0_CTRL__enable__off 0 | ||
| 3124 | |||
| 3125 | #define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) | ||
| 3126 | #define R_SCSI0_CMD_DATA__parity_in__BITNR 26 | ||
| 3127 | #define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 | ||
| 3128 | #define R_SCSI0_CMD_DATA__parity_in__on 0 | ||
| 3129 | #define R_SCSI0_CMD_DATA__parity_in__off 1 | ||
| 3130 | #define R_SCSI0_CMD_DATA__skip__BITNR 25 | ||
| 3131 | #define R_SCSI0_CMD_DATA__skip__WIDTH 1 | ||
| 3132 | #define R_SCSI0_CMD_DATA__skip__on 1 | ||
| 3133 | #define R_SCSI0_CMD_DATA__skip__off 0 | ||
| 3134 | #define R_SCSI0_CMD_DATA__clr_status__BITNR 24 | ||
| 3135 | #define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 | ||
| 3136 | #define R_SCSI0_CMD_DATA__clr_status__yes 1 | ||
| 3137 | #define R_SCSI0_CMD_DATA__clr_status__nop 0 | ||
| 3138 | #define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 | ||
| 3139 | #define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 | ||
| 3140 | #define R_SCSI0_CMD_DATA__command__BITNR 16 | ||
| 3141 | #define R_SCSI0_CMD_DATA__command__WIDTH 4 | ||
| 3142 | #define R_SCSI0_CMD_DATA__command__full_din_1 0 | ||
| 3143 | #define R_SCSI0_CMD_DATA__command__full_dout_1 1 | ||
| 3144 | #define R_SCSI0_CMD_DATA__command__full_stat_1 2 | ||
| 3145 | #define R_SCSI0_CMD_DATA__command__resel_din 3 | ||
| 3146 | #define R_SCSI0_CMD_DATA__command__resel_dout 4 | ||
| 3147 | #define R_SCSI0_CMD_DATA__command__resel_stat 5 | ||
| 3148 | #define R_SCSI0_CMD_DATA__command__arb_only 6 | ||
| 3149 | #define R_SCSI0_CMD_DATA__command__full_din_3 8 | ||
| 3150 | #define R_SCSI0_CMD_DATA__command__full_dout_3 9 | ||
| 3151 | #define R_SCSI0_CMD_DATA__command__full_stat_3 10 | ||
| 3152 | #define R_SCSI0_CMD_DATA__command__man_data_in 11 | ||
| 3153 | #define R_SCSI0_CMD_DATA__command__man_data_out 12 | ||
| 3154 | #define R_SCSI0_CMD_DATA__command__man_rat 13 | ||
| 3155 | #define R_SCSI0_CMD_DATA__data_out__BITNR 0 | ||
| 3156 | #define R_SCSI0_CMD_DATA__data_out__WIDTH 16 | ||
| 3157 | |||
| 3158 | #define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) | ||
| 3159 | #define R_SCSI0_DATA__data_out__BITNR 0 | ||
| 3160 | #define R_SCSI0_DATA__data_out__WIDTH 16 | ||
| 3161 | |||
| 3162 | #define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) | ||
| 3163 | #define R_SCSI0_CMD__asynch_setup__BITNR 4 | ||
| 3164 | #define R_SCSI0_CMD__asynch_setup__WIDTH 4 | ||
| 3165 | #define R_SCSI0_CMD__command__BITNR 0 | ||
| 3166 | #define R_SCSI0_CMD__command__WIDTH 4 | ||
| 3167 | #define R_SCSI0_CMD__command__full_din_1 0 | ||
| 3168 | #define R_SCSI0_CMD__command__full_dout_1 1 | ||
| 3169 | #define R_SCSI0_CMD__command__full_stat_1 2 | ||
| 3170 | #define R_SCSI0_CMD__command__resel_din 3 | ||
| 3171 | #define R_SCSI0_CMD__command__resel_dout 4 | ||
| 3172 | #define R_SCSI0_CMD__command__resel_stat 5 | ||
| 3173 | #define R_SCSI0_CMD__command__arb_only 6 | ||
| 3174 | #define R_SCSI0_CMD__command__full_din_3 8 | ||
| 3175 | #define R_SCSI0_CMD__command__full_dout_3 9 | ||
| 3176 | #define R_SCSI0_CMD__command__full_stat_3 10 | ||
| 3177 | #define R_SCSI0_CMD__command__man_data_in 11 | ||
| 3178 | #define R_SCSI0_CMD__command__man_data_out 12 | ||
| 3179 | #define R_SCSI0_CMD__command__man_rat 13 | ||
| 3180 | |||
| 3181 | #define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) | ||
| 3182 | #define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 | ||
| 3183 | #define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 | ||
| 3184 | #define R_SCSI0_STATUS_CTRL__parity_in__on 0 | ||
| 3185 | #define R_SCSI0_STATUS_CTRL__parity_in__off 1 | ||
| 3186 | #define R_SCSI0_STATUS_CTRL__skip__BITNR 1 | ||
| 3187 | #define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 | ||
| 3188 | #define R_SCSI0_STATUS_CTRL__skip__on 1 | ||
| 3189 | #define R_SCSI0_STATUS_CTRL__skip__off 0 | ||
| 3190 | #define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 | ||
| 3191 | #define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 | ||
| 3192 | #define R_SCSI0_STATUS_CTRL__clr_status__yes 1 | ||
| 3193 | #define R_SCSI0_STATUS_CTRL__clr_status__nop 0 | ||
| 3194 | |||
| 3195 | #define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) | ||
| 3196 | #define R_SCSI0_STATUS__tst_arb_won__BITNR 23 | ||
| 3197 | #define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 | ||
| 3198 | #define R_SCSI0_STATUS__tst_resel__BITNR 22 | ||
| 3199 | #define R_SCSI0_STATUS__tst_resel__WIDTH 1 | ||
| 3200 | #define R_SCSI0_STATUS__parity_error__BITNR 21 | ||
| 3201 | #define R_SCSI0_STATUS__parity_error__WIDTH 1 | ||
| 3202 | #define R_SCSI0_STATUS__bus_reset__BITNR 20 | ||
| 3203 | #define R_SCSI0_STATUS__bus_reset__WIDTH 1 | ||
| 3204 | #define R_SCSI0_STATUS__bus_reset__yes 1 | ||
| 3205 | #define R_SCSI0_STATUS__bus_reset__no 0 | ||
| 3206 | #define R_SCSI0_STATUS__resel_target__BITNR 15 | ||
| 3207 | #define R_SCSI0_STATUS__resel_target__WIDTH 4 | ||
| 3208 | #define R_SCSI0_STATUS__resel__BITNR 14 | ||
| 3209 | #define R_SCSI0_STATUS__resel__WIDTH 1 | ||
| 3210 | #define R_SCSI0_STATUS__resel__yes 1 | ||
| 3211 | #define R_SCSI0_STATUS__resel__no 0 | ||
| 3212 | #define R_SCSI0_STATUS__curr_phase__BITNR 11 | ||
| 3213 | #define R_SCSI0_STATUS__curr_phase__WIDTH 3 | ||
| 3214 | #define R_SCSI0_STATUS__curr_phase__ph_undef 0 | ||
| 3215 | #define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 | ||
| 3216 | #define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 | ||
| 3217 | #define R_SCSI0_STATUS__curr_phase__ph_status 3 | ||
| 3218 | #define R_SCSI0_STATUS__curr_phase__ph_command 2 | ||
| 3219 | #define R_SCSI0_STATUS__curr_phase__ph_data_in 5 | ||
| 3220 | #define R_SCSI0_STATUS__curr_phase__ph_data_out 4 | ||
| 3221 | #define R_SCSI0_STATUS__curr_phase__ph_resel 1 | ||
| 3222 | #define R_SCSI0_STATUS__last_seq_step__BITNR 6 | ||
| 3223 | #define R_SCSI0_STATUS__last_seq_step__WIDTH 5 | ||
| 3224 | #define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 | ||
| 3225 | #define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 | ||
| 3226 | #define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 | ||
| 3227 | #define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 | ||
| 3228 | #define R_SCSI0_STATUS__last_seq_step__st_manual 28 | ||
| 3229 | #define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 | ||
| 3230 | #define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 | ||
| 3231 | #define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 | ||
| 3232 | #define R_SCSI0_STATUS__last_seq_step__st_answer 3 | ||
| 3233 | #define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 | ||
| 3234 | #define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 | ||
| 3235 | #define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 | ||
| 3236 | #define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 | ||
| 3237 | #define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 | ||
| 3238 | #define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 | ||
| 3239 | #define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 | ||
| 3240 | #define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 | ||
| 3241 | #define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 | ||
| 3242 | #define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 | ||
| 3243 | #define R_SCSI0_STATUS__last_seq_step__st_iwr 27 | ||
| 3244 | #define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 | ||
| 3245 | #define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 | ||
| 3246 | #define R_SCSI0_STATUS__last_seq_step__st_cc 31 | ||
| 3247 | #define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 | ||
| 3248 | #define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 | ||
| 3249 | #define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 | ||
| 3250 | #define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 | ||
| 3251 | #define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 | ||
| 3252 | #define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 | ||
| 3253 | #define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 | ||
| 3254 | #define R_SCSI0_STATUS__valid_status__BITNR 5 | ||
| 3255 | #define R_SCSI0_STATUS__valid_status__WIDTH 1 | ||
| 3256 | #define R_SCSI0_STATUS__valid_status__yes 1 | ||
| 3257 | #define R_SCSI0_STATUS__valid_status__no 0 | ||
| 3258 | #define R_SCSI0_STATUS__seq_status__BITNR 0 | ||
| 3259 | #define R_SCSI0_STATUS__seq_status__WIDTH 5 | ||
| 3260 | #define R_SCSI0_STATUS__seq_status__info_seq_complete 0 | ||
| 3261 | #define R_SCSI0_STATUS__seq_status__info_parity_error 1 | ||
| 3262 | #define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 | ||
| 3263 | #define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 | ||
| 3264 | #define R_SCSI0_STATUS__seq_status__info_arb_lost 4 | ||
| 3265 | #define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 | ||
| 3266 | #define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 | ||
| 3267 | #define R_SCSI0_STATUS__seq_status__info_illegal_op 7 | ||
| 3268 | #define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 | ||
| 3269 | #define R_SCSI0_STATUS__seq_status__info_reselected 9 | ||
| 3270 | #define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 | ||
| 3271 | #define R_SCSI0_STATUS__seq_status__info_bus_reset 11 | ||
| 3272 | #define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 | ||
| 3273 | #define R_SCSI0_STATUS__seq_status__info_bus_free 13 | ||
| 3274 | |||
| 3275 | #define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) | ||
| 3276 | #define R_SCSI0_DATA_IN__data_in__BITNR 0 | ||
| 3277 | #define R_SCSI0_DATA_IN__data_in__WIDTH 16 | ||
| 3278 | |||
| 3279 | #define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) | ||
| 3280 | #define R_SCSI1_CTRL__id_type__BITNR 31 | ||
| 3281 | #define R_SCSI1_CTRL__id_type__WIDTH 1 | ||
| 3282 | #define R_SCSI1_CTRL__id_type__software 1 | ||
| 3283 | #define R_SCSI1_CTRL__id_type__hardware 0 | ||
| 3284 | #define R_SCSI1_CTRL__sel_timeout__BITNR 24 | ||
| 3285 | #define R_SCSI1_CTRL__sel_timeout__WIDTH 7 | ||
| 3286 | #define R_SCSI1_CTRL__synch_per__BITNR 16 | ||
| 3287 | #define R_SCSI1_CTRL__synch_per__WIDTH 8 | ||
| 3288 | #define R_SCSI1_CTRL__rst__BITNR 15 | ||
| 3289 | #define R_SCSI1_CTRL__rst__WIDTH 1 | ||
| 3290 | #define R_SCSI1_CTRL__rst__yes 1 | ||
| 3291 | #define R_SCSI1_CTRL__rst__no 0 | ||
| 3292 | #define R_SCSI1_CTRL__atn__BITNR 14 | ||
| 3293 | #define R_SCSI1_CTRL__atn__WIDTH 1 | ||
| 3294 | #define R_SCSI1_CTRL__atn__yes 1 | ||
| 3295 | #define R_SCSI1_CTRL__atn__no 0 | ||
| 3296 | #define R_SCSI1_CTRL__my_id__BITNR 9 | ||
| 3297 | #define R_SCSI1_CTRL__my_id__WIDTH 4 | ||
| 3298 | #define R_SCSI1_CTRL__target_id__BITNR 4 | ||
| 3299 | #define R_SCSI1_CTRL__target_id__WIDTH 4 | ||
| 3300 | #define R_SCSI1_CTRL__fast_20__BITNR 3 | ||
| 3301 | #define R_SCSI1_CTRL__fast_20__WIDTH 1 | ||
| 3302 | #define R_SCSI1_CTRL__fast_20__yes 1 | ||
| 3303 | #define R_SCSI1_CTRL__fast_20__no 0 | ||
| 3304 | #define R_SCSI1_CTRL__bus_width__BITNR 2 | ||
| 3305 | #define R_SCSI1_CTRL__bus_width__WIDTH 1 | ||
| 3306 | #define R_SCSI1_CTRL__bus_width__wide 1 | ||
| 3307 | #define R_SCSI1_CTRL__bus_width__narrow 0 | ||
| 3308 | #define R_SCSI1_CTRL__synch__BITNR 1 | ||
| 3309 | #define R_SCSI1_CTRL__synch__WIDTH 1 | ||
| 3310 | #define R_SCSI1_CTRL__synch__synch 1 | ||
| 3311 | #define R_SCSI1_CTRL__synch__asynch 0 | ||
| 3312 | #define R_SCSI1_CTRL__enable__BITNR 0 | ||
| 3313 | #define R_SCSI1_CTRL__enable__WIDTH 1 | ||
| 3314 | #define R_SCSI1_CTRL__enable__on 1 | ||
| 3315 | #define R_SCSI1_CTRL__enable__off 0 | ||
| 3316 | |||
| 3317 | #define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) | ||
| 3318 | #define R_SCSI1_CMD_DATA__parity_in__BITNR 26 | ||
| 3319 | #define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 | ||
| 3320 | #define R_SCSI1_CMD_DATA__parity_in__on 0 | ||
| 3321 | #define R_SCSI1_CMD_DATA__parity_in__off 1 | ||
| 3322 | #define R_SCSI1_CMD_DATA__skip__BITNR 25 | ||
| 3323 | #define R_SCSI1_CMD_DATA__skip__WIDTH 1 | ||
| 3324 | #define R_SCSI1_CMD_DATA__skip__on 1 | ||
| 3325 | #define R_SCSI1_CMD_DATA__skip__off 0 | ||
| 3326 | #define R_SCSI1_CMD_DATA__clr_status__BITNR 24 | ||
| 3327 | #define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 | ||
| 3328 | #define R_SCSI1_CMD_DATA__clr_status__yes 1 | ||
| 3329 | #define R_SCSI1_CMD_DATA__clr_status__nop 0 | ||
| 3330 | #define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 | ||
| 3331 | #define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 | ||
| 3332 | #define R_SCSI1_CMD_DATA__command__BITNR 16 | ||
| 3333 | #define R_SCSI1_CMD_DATA__command__WIDTH 4 | ||
| 3334 | #define R_SCSI1_CMD_DATA__command__full_din_1 0 | ||
| 3335 | #define R_SCSI1_CMD_DATA__command__full_dout_1 1 | ||
| 3336 | #define R_SCSI1_CMD_DATA__command__full_stat_1 2 | ||
| 3337 | #define R_SCSI1_CMD_DATA__command__resel_din 3 | ||
| 3338 | #define R_SCSI1_CMD_DATA__command__resel_dout 4 | ||
| 3339 | #define R_SCSI1_CMD_DATA__command__resel_stat 5 | ||
| 3340 | #define R_SCSI1_CMD_DATA__command__arb_only 6 | ||
| 3341 | #define R_SCSI1_CMD_DATA__command__full_din_3 8 | ||
| 3342 | #define R_SCSI1_CMD_DATA__command__full_dout_3 9 | ||
| 3343 | #define R_SCSI1_CMD_DATA__command__full_stat_3 10 | ||
| 3344 | #define R_SCSI1_CMD_DATA__command__man_data_in 11 | ||
| 3345 | #define R_SCSI1_CMD_DATA__command__man_data_out 12 | ||
| 3346 | #define R_SCSI1_CMD_DATA__command__man_rat 13 | ||
| 3347 | #define R_SCSI1_CMD_DATA__data_out__BITNR 0 | ||
| 3348 | #define R_SCSI1_CMD_DATA__data_out__WIDTH 16 | ||
| 3349 | |||
| 3350 | #define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) | ||
| 3351 | #define R_SCSI1_DATA__data_out__BITNR 0 | ||
| 3352 | #define R_SCSI1_DATA__data_out__WIDTH 16 | ||
| 3353 | |||
| 3354 | #define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) | ||
| 3355 | #define R_SCSI1_CMD__asynch_setup__BITNR 4 | ||
| 3356 | #define R_SCSI1_CMD__asynch_setup__WIDTH 4 | ||
| 3357 | #define R_SCSI1_CMD__command__BITNR 0 | ||
| 3358 | #define R_SCSI1_CMD__command__WIDTH 4 | ||
| 3359 | #define R_SCSI1_CMD__command__full_din_1 0 | ||
| 3360 | #define R_SCSI1_CMD__command__full_dout_1 1 | ||
| 3361 | #define R_SCSI1_CMD__command__full_stat_1 2 | ||
| 3362 | #define R_SCSI1_CMD__command__resel_din 3 | ||
| 3363 | #define R_SCSI1_CMD__command__resel_dout 4 | ||
| 3364 | #define R_SCSI1_CMD__command__resel_stat 5 | ||
| 3365 | #define R_SCSI1_CMD__command__arb_only 6 | ||
| 3366 | #define R_SCSI1_CMD__command__full_din_3 8 | ||
| 3367 | #define R_SCSI1_CMD__command__full_dout_3 9 | ||
| 3368 | #define R_SCSI1_CMD__command__full_stat_3 10 | ||
| 3369 | #define R_SCSI1_CMD__command__man_data_in 11 | ||
| 3370 | #define R_SCSI1_CMD__command__man_data_out 12 | ||
| 3371 | #define R_SCSI1_CMD__command__man_rat 13 | ||
| 3372 | |||
| 3373 | #define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) | ||
| 3374 | #define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 | ||
| 3375 | #define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 | ||
| 3376 | #define R_SCSI1_STATUS_CTRL__parity_in__on 0 | ||
| 3377 | #define R_SCSI1_STATUS_CTRL__parity_in__off 1 | ||
| 3378 | #define R_SCSI1_STATUS_CTRL__skip__BITNR 1 | ||
| 3379 | #define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 | ||
| 3380 | #define R_SCSI1_STATUS_CTRL__skip__on 1 | ||
| 3381 | #define R_SCSI1_STATUS_CTRL__skip__off 0 | ||
| 3382 | #define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 | ||
| 3383 | #define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 | ||
| 3384 | #define R_SCSI1_STATUS_CTRL__clr_status__yes 1 | ||
| 3385 | #define R_SCSI1_STATUS_CTRL__clr_status__nop 0 | ||
| 3386 | |||
| 3387 | #define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) | ||
| 3388 | #define R_SCSI1_STATUS__tst_arb_won__BITNR 23 | ||
| 3389 | #define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 | ||
| 3390 | #define R_SCSI1_STATUS__tst_resel__BITNR 22 | ||
| 3391 | #define R_SCSI1_STATUS__tst_resel__WIDTH 1 | ||
| 3392 | #define R_SCSI1_STATUS__parity_error__BITNR 21 | ||
| 3393 | #define R_SCSI1_STATUS__parity_error__WIDTH 1 | ||
| 3394 | #define R_SCSI1_STATUS__bus_reset__BITNR 20 | ||
| 3395 | #define R_SCSI1_STATUS__bus_reset__WIDTH 1 | ||
| 3396 | #define R_SCSI1_STATUS__bus_reset__yes 1 | ||
| 3397 | #define R_SCSI1_STATUS__bus_reset__no 0 | ||
| 3398 | #define R_SCSI1_STATUS__resel_target__BITNR 15 | ||
| 3399 | #define R_SCSI1_STATUS__resel_target__WIDTH 4 | ||
| 3400 | #define R_SCSI1_STATUS__resel__BITNR 14 | ||
| 3401 | #define R_SCSI1_STATUS__resel__WIDTH 1 | ||
| 3402 | #define R_SCSI1_STATUS__resel__yes 1 | ||
| 3403 | #define R_SCSI1_STATUS__resel__no 0 | ||
| 3404 | #define R_SCSI1_STATUS__curr_phase__BITNR 11 | ||
| 3405 | #define R_SCSI1_STATUS__curr_phase__WIDTH 3 | ||
| 3406 | #define R_SCSI1_STATUS__curr_phase__ph_undef 0 | ||
| 3407 | #define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 | ||
| 3408 | #define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 | ||
| 3409 | #define R_SCSI1_STATUS__curr_phase__ph_status 3 | ||
| 3410 | #define R_SCSI1_STATUS__curr_phase__ph_command 2 | ||
| 3411 | #define R_SCSI1_STATUS__curr_phase__ph_data_in 5 | ||
| 3412 | #define R_SCSI1_STATUS__curr_phase__ph_data_out 4 | ||
| 3413 | #define R_SCSI1_STATUS__curr_phase__ph_resel 1 | ||
| 3414 | #define R_SCSI1_STATUS__last_seq_step__BITNR 6 | ||
| 3415 | #define R_SCSI1_STATUS__last_seq_step__WIDTH 5 | ||
| 3416 | #define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 | ||
| 3417 | #define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 | ||
| 3418 | #define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 | ||
| 3419 | #define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 | ||
| 3420 | #define R_SCSI1_STATUS__last_seq_step__st_manual 28 | ||
| 3421 | #define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 | ||
| 3422 | #define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 | ||
| 3423 | #define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 | ||
| 3424 | #define R_SCSI1_STATUS__last_seq_step__st_answer 3 | ||
| 3425 | #define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 | ||
| 3426 | #define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 | ||
| 3427 | #define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 | ||
| 3428 | #define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 | ||
| 3429 | #define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 | ||
| 3430 | #define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 | ||
| 3431 | #define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 | ||
| 3432 | #define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 | ||
| 3433 | #define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 | ||
| 3434 | #define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 | ||
| 3435 | #define R_SCSI1_STATUS__last_seq_step__st_iwr 27 | ||
| 3436 | #define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 | ||
| 3437 | #define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 | ||
| 3438 | #define R_SCSI1_STATUS__last_seq_step__st_cc 31 | ||
| 3439 | #define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 | ||
| 3440 | #define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 | ||
| 3441 | #define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 | ||
| 3442 | #define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 | ||
| 3443 | #define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 | ||
| 3444 | #define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 | ||
| 3445 | #define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 | ||
| 3446 | #define R_SCSI1_STATUS__valid_status__BITNR 5 | ||
| 3447 | #define R_SCSI1_STATUS__valid_status__WIDTH 1 | ||
| 3448 | #define R_SCSI1_STATUS__valid_status__yes 1 | ||
| 3449 | #define R_SCSI1_STATUS__valid_status__no 0 | ||
| 3450 | #define R_SCSI1_STATUS__seq_status__BITNR 0 | ||
| 3451 | #define R_SCSI1_STATUS__seq_status__WIDTH 5 | ||
| 3452 | #define R_SCSI1_STATUS__seq_status__info_seq_complete 0 | ||
| 3453 | #define R_SCSI1_STATUS__seq_status__info_parity_error 1 | ||
| 3454 | #define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 | ||
| 3455 | #define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 | ||
| 3456 | #define R_SCSI1_STATUS__seq_status__info_arb_lost 4 | ||
| 3457 | #define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 | ||
| 3458 | #define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 | ||
| 3459 | #define R_SCSI1_STATUS__seq_status__info_illegal_op 7 | ||
| 3460 | #define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 | ||
| 3461 | #define R_SCSI1_STATUS__seq_status__info_reselected 9 | ||
| 3462 | #define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 | ||
| 3463 | #define R_SCSI1_STATUS__seq_status__info_bus_reset 11 | ||
| 3464 | #define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 | ||
| 3465 | #define R_SCSI1_STATUS__seq_status__info_bus_free 13 | ||
| 3466 | |||
| 3467 | #define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) | ||
| 3468 | #define R_SCSI1_DATA_IN__data_in__BITNR 0 | ||
| 3469 | #define R_SCSI1_DATA_IN__data_in__WIDTH 16 | ||
| 3470 | |||
| 3471 | /* | ||
| 3472 | !* Interrupt mask and status registers | ||
| 3473 | !*/ | ||
| 3474 | |||
| 3475 | #define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) | ||
| 3476 | #define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 | ||
| 3477 | #define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 | ||
| 3478 | #define R_IRQ_MASK0_RD__nmi_pin__active 1 | ||
| 3479 | #define R_IRQ_MASK0_RD__nmi_pin__inactive 0 | ||
| 3480 | #define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 | ||
| 3481 | #define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 | ||
| 3482 | #define R_IRQ_MASK0_RD__watchdog_nmi__active 1 | ||
| 3483 | #define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 | ||
| 3484 | #define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 | ||
| 3485 | #define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 | ||
| 3486 | #define R_IRQ_MASK0_RD__sqe_test_error__active 1 | ||
| 3487 | #define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 | ||
| 3488 | #define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 | ||
| 3489 | #define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 | ||
| 3490 | #define R_IRQ_MASK0_RD__carrier_loss__active 1 | ||
| 3491 | #define R_IRQ_MASK0_RD__carrier_loss__inactive 0 | ||
| 3492 | #define R_IRQ_MASK0_RD__deferred__BITNR 27 | ||
| 3493 | #define R_IRQ_MASK0_RD__deferred__WIDTH 1 | ||
| 3494 | #define R_IRQ_MASK0_RD__deferred__active 1 | ||
| 3495 | #define R_IRQ_MASK0_RD__deferred__inactive 0 | ||
| 3496 | #define R_IRQ_MASK0_RD__late_col__BITNR 26 | ||
| 3497 | #define R_IRQ_MASK0_RD__late_col__WIDTH 1 | ||
| 3498 | #define R_IRQ_MASK0_RD__late_col__active 1 | ||
| 3499 | #define R_IRQ_MASK0_RD__late_col__inactive 0 | ||
| 3500 | #define R_IRQ_MASK0_RD__multiple_col__BITNR 25 | ||
| 3501 | #define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 | ||
| 3502 | #define R_IRQ_MASK0_RD__multiple_col__active 1 | ||
| 3503 | #define R_IRQ_MASK0_RD__multiple_col__inactive 0 | ||
| 3504 | #define R_IRQ_MASK0_RD__single_col__BITNR 24 | ||
| 3505 | #define R_IRQ_MASK0_RD__single_col__WIDTH 1 | ||
| 3506 | #define R_IRQ_MASK0_RD__single_col__active 1 | ||
| 3507 | #define R_IRQ_MASK0_RD__single_col__inactive 0 | ||
| 3508 | #define R_IRQ_MASK0_RD__congestion__BITNR 23 | ||
| 3509 | #define R_IRQ_MASK0_RD__congestion__WIDTH 1 | ||
| 3510 | #define R_IRQ_MASK0_RD__congestion__active 1 | ||
| 3511 | #define R_IRQ_MASK0_RD__congestion__inactive 0 | ||
| 3512 | #define R_IRQ_MASK0_RD__oversize__BITNR 22 | ||
| 3513 | #define R_IRQ_MASK0_RD__oversize__WIDTH 1 | ||
| 3514 | #define R_IRQ_MASK0_RD__oversize__active 1 | ||
| 3515 | #define R_IRQ_MASK0_RD__oversize__inactive 0 | ||
| 3516 | #define R_IRQ_MASK0_RD__alignment_error__BITNR 21 | ||
| 3517 | #define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 | ||
| 3518 | #define R_IRQ_MASK0_RD__alignment_error__active 1 | ||
| 3519 | #define R_IRQ_MASK0_RD__alignment_error__inactive 0 | ||
| 3520 | #define R_IRQ_MASK0_RD__crc_error__BITNR 20 | ||
| 3521 | #define R_IRQ_MASK0_RD__crc_error__WIDTH 1 | ||
| 3522 | #define R_IRQ_MASK0_RD__crc_error__active 1 | ||
| 3523 | #define R_IRQ_MASK0_RD__crc_error__inactive 0 | ||
| 3524 | #define R_IRQ_MASK0_RD__overrun__BITNR 19 | ||
| 3525 | #define R_IRQ_MASK0_RD__overrun__WIDTH 1 | ||
| 3526 | #define R_IRQ_MASK0_RD__overrun__active 1 | ||
| 3527 | #define R_IRQ_MASK0_RD__overrun__inactive 0 | ||
| 3528 | #define R_IRQ_MASK0_RD__underrun__BITNR 18 | ||
| 3529 | #define R_IRQ_MASK0_RD__underrun__WIDTH 1 | ||
| 3530 | #define R_IRQ_MASK0_RD__underrun__active 1 | ||
| 3531 | #define R_IRQ_MASK0_RD__underrun__inactive 0 | ||
| 3532 | #define R_IRQ_MASK0_RD__excessive_col__BITNR 17 | ||
| 3533 | #define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 | ||
| 3534 | #define R_IRQ_MASK0_RD__excessive_col__active 1 | ||
| 3535 | #define R_IRQ_MASK0_RD__excessive_col__inactive 0 | ||
| 3536 | #define R_IRQ_MASK0_RD__mdio__BITNR 16 | ||
| 3537 | #define R_IRQ_MASK0_RD__mdio__WIDTH 1 | ||
| 3538 | #define R_IRQ_MASK0_RD__mdio__active 1 | ||
| 3539 | #define R_IRQ_MASK0_RD__mdio__inactive 0 | ||
| 3540 | #define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 | ||
| 3541 | #define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 | ||
| 3542 | #define R_IRQ_MASK0_RD__ata_drq3__active 1 | ||
| 3543 | #define R_IRQ_MASK0_RD__ata_drq3__inactive 0 | ||
| 3544 | #define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 | ||
| 3545 | #define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 | ||
| 3546 | #define R_IRQ_MASK0_RD__ata_drq2__active 1 | ||
| 3547 | #define R_IRQ_MASK0_RD__ata_drq2__inactive 0 | ||
| 3548 | #define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 | ||
| 3549 | #define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 | ||
| 3550 | #define R_IRQ_MASK0_RD__ata_drq1__active 1 | ||
| 3551 | #define R_IRQ_MASK0_RD__ata_drq1__inactive 0 | ||
| 3552 | #define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 | ||
| 3553 | #define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 | ||
| 3554 | #define R_IRQ_MASK0_RD__ata_drq0__active 1 | ||
| 3555 | #define R_IRQ_MASK0_RD__ata_drq0__inactive 0 | ||
| 3556 | #define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 | ||
| 3557 | #define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 | ||
| 3558 | #define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 | ||
| 3559 | #define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 | ||
| 3560 | #define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 | ||
| 3561 | #define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 | ||
| 3562 | #define R_IRQ_MASK0_RD__ata_irq3__active 1 | ||
| 3563 | #define R_IRQ_MASK0_RD__ata_irq3__inactive 0 | ||
| 3564 | #define R_IRQ_MASK0_RD__par0_peri__BITNR 10 | ||
| 3565 | #define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 | ||
| 3566 | #define R_IRQ_MASK0_RD__par0_peri__active 1 | ||
| 3567 | #define R_IRQ_MASK0_RD__par0_peri__inactive 0 | ||
| 3568 | #define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 | ||
| 3569 | #define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 | ||
| 3570 | #define R_IRQ_MASK0_RD__ata_irq2__active 1 | ||
| 3571 | #define R_IRQ_MASK0_RD__ata_irq2__inactive 0 | ||
| 3572 | #define R_IRQ_MASK0_RD__par0_data__BITNR 9 | ||
| 3573 | #define R_IRQ_MASK0_RD__par0_data__WIDTH 1 | ||
| 3574 | #define R_IRQ_MASK0_RD__par0_data__active 1 | ||
| 3575 | #define R_IRQ_MASK0_RD__par0_data__inactive 0 | ||
| 3576 | #define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 | ||
| 3577 | #define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 | ||
| 3578 | #define R_IRQ_MASK0_RD__ata_irq1__active 1 | ||
| 3579 | #define R_IRQ_MASK0_RD__ata_irq1__inactive 0 | ||
| 3580 | #define R_IRQ_MASK0_RD__par0_ready__BITNR 8 | ||
| 3581 | #define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 | ||
| 3582 | #define R_IRQ_MASK0_RD__par0_ready__active 1 | ||
| 3583 | #define R_IRQ_MASK0_RD__par0_ready__inactive 0 | ||
| 3584 | #define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 | ||
| 3585 | #define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 | ||
| 3586 | #define R_IRQ_MASK0_RD__ata_irq0__active 1 | ||
| 3587 | #define R_IRQ_MASK0_RD__ata_irq0__inactive 0 | ||
| 3588 | #define R_IRQ_MASK0_RD__mio__BITNR 8 | ||
| 3589 | #define R_IRQ_MASK0_RD__mio__WIDTH 1 | ||
| 3590 | #define R_IRQ_MASK0_RD__mio__active 1 | ||
| 3591 | #define R_IRQ_MASK0_RD__mio__inactive 0 | ||
| 3592 | #define R_IRQ_MASK0_RD__scsi0__BITNR 8 | ||
| 3593 | #define R_IRQ_MASK0_RD__scsi0__WIDTH 1 | ||
| 3594 | #define R_IRQ_MASK0_RD__scsi0__active 1 | ||
| 3595 | #define R_IRQ_MASK0_RD__scsi0__inactive 0 | ||
| 3596 | #define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 | ||
| 3597 | #define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 | ||
| 3598 | #define R_IRQ_MASK0_RD__ata_dmaend__active 1 | ||
| 3599 | #define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 | ||
| 3600 | #define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 | ||
| 3601 | #define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 | ||
| 3602 | #define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 | ||
| 3603 | #define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 | ||
| 3604 | #define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 | ||
| 3605 | #define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 | ||
| 3606 | #define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 | ||
| 3607 | #define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 | ||
| 3608 | #define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 | ||
| 3609 | #define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 | ||
| 3610 | #define R_IRQ_MASK0_RD__ext_dma1__active 1 | ||
| 3611 | #define R_IRQ_MASK0_RD__ext_dma1__inactive 0 | ||
| 3612 | #define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 | ||
| 3613 | #define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 | ||
| 3614 | #define R_IRQ_MASK0_RD__ext_dma0__active 1 | ||
| 3615 | #define R_IRQ_MASK0_RD__ext_dma0__inactive 0 | ||
| 3616 | #define R_IRQ_MASK0_RD__timer1__BITNR 1 | ||
| 3617 | #define R_IRQ_MASK0_RD__timer1__WIDTH 1 | ||
| 3618 | #define R_IRQ_MASK0_RD__timer1__active 1 | ||
| 3619 | #define R_IRQ_MASK0_RD__timer1__inactive 0 | ||
| 3620 | #define R_IRQ_MASK0_RD__timer0__BITNR 0 | ||
| 3621 | #define R_IRQ_MASK0_RD__timer0__WIDTH 1 | ||
| 3622 | #define R_IRQ_MASK0_RD__timer0__active 1 | ||
| 3623 | #define R_IRQ_MASK0_RD__timer0__inactive 0 | ||
| 3624 | |||
| 3625 | #define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) | ||
| 3626 | #define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 | ||
| 3627 | #define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 | ||
| 3628 | #define R_IRQ_MASK0_CLR__nmi_pin__clr 1 | ||
| 3629 | #define R_IRQ_MASK0_CLR__nmi_pin__nop 0 | ||
| 3630 | #define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 | ||
| 3631 | #define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 | ||
| 3632 | #define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 | ||
| 3633 | #define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 | ||
| 3634 | #define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 | ||
| 3635 | #define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 | ||
| 3636 | #define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 | ||
| 3637 | #define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 | ||
| 3638 | #define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 | ||
| 3639 | #define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 | ||
| 3640 | #define R_IRQ_MASK0_CLR__carrier_loss__clr 1 | ||
| 3641 | #define R_IRQ_MASK0_CLR__carrier_loss__nop 0 | ||
| 3642 | #define R_IRQ_MASK0_CLR__deferred__BITNR 27 | ||
| 3643 | #define R_IRQ_MASK0_CLR__deferred__WIDTH 1 | ||
| 3644 | #define R_IRQ_MASK0_CLR__deferred__clr 1 | ||
| 3645 | #define R_IRQ_MASK0_CLR__deferred__nop 0 | ||
| 3646 | #define R_IRQ_MASK0_CLR__late_col__BITNR 26 | ||
| 3647 | #define R_IRQ_MASK0_CLR__late_col__WIDTH 1 | ||
| 3648 | #define R_IRQ_MASK0_CLR__late_col__clr 1 | ||
| 3649 | #define R_IRQ_MASK0_CLR__late_col__nop 0 | ||
| 3650 | #define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 | ||
| 3651 | #define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 | ||
| 3652 | #define R_IRQ_MASK0_CLR__multiple_col__clr 1 | ||
| 3653 | #define R_IRQ_MASK0_CLR__multiple_col__nop 0 | ||
| 3654 | #define R_IRQ_MASK0_CLR__single_col__BITNR 24 | ||
| 3655 | #define R_IRQ_MASK0_CLR__single_col__WIDTH 1 | ||
| 3656 | #define R_IRQ_MASK0_CLR__single_col__clr 1 | ||
| 3657 | #define R_IRQ_MASK0_CLR__single_col__nop 0 | ||
| 3658 | #define R_IRQ_MASK0_CLR__congestion__BITNR 23 | ||
| 3659 | #define R_IRQ_MASK0_CLR__congestion__WIDTH 1 | ||
| 3660 | #define R_IRQ_MASK0_CLR__congestion__clr 1 | ||
| 3661 | #define R_IRQ_MASK0_CLR__congestion__nop 0 | ||
| 3662 | #define R_IRQ_MASK0_CLR__oversize__BITNR 22 | ||
| 3663 | #define R_IRQ_MASK0_CLR__oversize__WIDTH 1 | ||
| 3664 | #define R_IRQ_MASK0_CLR__oversize__clr 1 | ||
| 3665 | #define R_IRQ_MASK0_CLR__oversize__nop 0 | ||
| 3666 | #define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 | ||
| 3667 | #define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 | ||
| 3668 | #define R_IRQ_MASK0_CLR__alignment_error__clr 1 | ||
| 3669 | #define R_IRQ_MASK0_CLR__alignment_error__nop 0 | ||
| 3670 | #define R_IRQ_MASK0_CLR__crc_error__BITNR 20 | ||
| 3671 | #define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 | ||
| 3672 | #define R_IRQ_MASK0_CLR__crc_error__clr 1 | ||
| 3673 | #define R_IRQ_MASK0_CLR__crc_error__nop 0 | ||
| 3674 | #define R_IRQ_MASK0_CLR__overrun__BITNR 19 | ||
| 3675 | #define R_IRQ_MASK0_CLR__overrun__WIDTH 1 | ||
| 3676 | #define R_IRQ_MASK0_CLR__overrun__clr 1 | ||
| 3677 | #define R_IRQ_MASK0_CLR__overrun__nop 0 | ||
| 3678 | #define R_IRQ_MASK0_CLR__underrun__BITNR 18 | ||
| 3679 | #define R_IRQ_MASK0_CLR__underrun__WIDTH 1 | ||
| 3680 | #define R_IRQ_MASK0_CLR__underrun__clr 1 | ||
| 3681 | #define R_IRQ_MASK0_CLR__underrun__nop 0 | ||
| 3682 | #define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 | ||
| 3683 | #define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 | ||
| 3684 | #define R_IRQ_MASK0_CLR__excessive_col__clr 1 | ||
| 3685 | #define R_IRQ_MASK0_CLR__excessive_col__nop 0 | ||
| 3686 | #define R_IRQ_MASK0_CLR__mdio__BITNR 16 | ||
| 3687 | #define R_IRQ_MASK0_CLR__mdio__WIDTH 1 | ||
| 3688 | #define R_IRQ_MASK0_CLR__mdio__clr 1 | ||
| 3689 | #define R_IRQ_MASK0_CLR__mdio__nop 0 | ||
| 3690 | #define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 | ||
| 3691 | #define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 | ||
| 3692 | #define R_IRQ_MASK0_CLR__ata_drq3__clr 1 | ||
| 3693 | #define R_IRQ_MASK0_CLR__ata_drq3__nop 0 | ||
| 3694 | #define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 | ||
| 3695 | #define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 | ||
| 3696 | #define R_IRQ_MASK0_CLR__ata_drq2__clr 1 | ||
| 3697 | #define R_IRQ_MASK0_CLR__ata_drq2__nop 0 | ||
| 3698 | #define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 | ||
| 3699 | #define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 | ||
| 3700 | #define R_IRQ_MASK0_CLR__ata_drq1__clr 1 | ||
| 3701 | #define R_IRQ_MASK0_CLR__ata_drq1__nop 0 | ||
| 3702 | #define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 | ||
| 3703 | #define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 | ||
| 3704 | #define R_IRQ_MASK0_CLR__ata_drq0__clr 1 | ||
| 3705 | #define R_IRQ_MASK0_CLR__ata_drq0__nop 0 | ||
| 3706 | #define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 | ||
| 3707 | #define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 | ||
| 3708 | #define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 | ||
| 3709 | #define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 | ||
| 3710 | #define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 | ||
| 3711 | #define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 | ||
| 3712 | #define R_IRQ_MASK0_CLR__ata_irq3__clr 1 | ||
| 3713 | #define R_IRQ_MASK0_CLR__ata_irq3__nop 0 | ||
| 3714 | #define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 | ||
| 3715 | #define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 | ||
| 3716 | #define R_IRQ_MASK0_CLR__par0_peri__clr 1 | ||
| 3717 | #define R_IRQ_MASK0_CLR__par0_peri__nop 0 | ||
| 3718 | #define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 | ||
| 3719 | #define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 | ||
| 3720 | #define R_IRQ_MASK0_CLR__ata_irq2__clr 1 | ||
| 3721 | #define R_IRQ_MASK0_CLR__ata_irq2__nop 0 | ||
| 3722 | #define R_IRQ_MASK0_CLR__par0_data__BITNR 9 | ||
| 3723 | #define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 | ||
| 3724 | #define R_IRQ_MASK0_CLR__par0_data__clr 1 | ||
| 3725 | #define R_IRQ_MASK0_CLR__par0_data__nop 0 | ||
| 3726 | #define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 | ||
| 3727 | #define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 | ||
| 3728 | #define R_IRQ_MASK0_CLR__ata_irq1__clr 1 | ||
| 3729 | #define R_IRQ_MASK0_CLR__ata_irq1__nop 0 | ||
| 3730 | #define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 | ||
| 3731 | #define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 | ||
| 3732 | #define R_IRQ_MASK0_CLR__par0_ready__clr 1 | ||
| 3733 | #define R_IRQ_MASK0_CLR__par0_ready__nop 0 | ||
| 3734 | #define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 | ||
| 3735 | #define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 | ||
| 3736 | #define R_IRQ_MASK0_CLR__ata_irq0__clr 1 | ||
| 3737 | #define R_IRQ_MASK0_CLR__ata_irq0__nop 0 | ||
| 3738 | #define R_IRQ_MASK0_CLR__mio__BITNR 8 | ||
| 3739 | #define R_IRQ_MASK0_CLR__mio__WIDTH 1 | ||
| 3740 | #define R_IRQ_MASK0_CLR__mio__clr 1 | ||
| 3741 | #define R_IRQ_MASK0_CLR__mio__nop 0 | ||
| 3742 | #define R_IRQ_MASK0_CLR__scsi0__BITNR 8 | ||
| 3743 | #define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 | ||
| 3744 | #define R_IRQ_MASK0_CLR__scsi0__clr 1 | ||
| 3745 | #define R_IRQ_MASK0_CLR__scsi0__nop 0 | ||
| 3746 | #define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 | ||
| 3747 | #define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 | ||
| 3748 | #define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 | ||
| 3749 | #define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 | ||
| 3750 | #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 | ||
| 3751 | #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 | ||
| 3752 | #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 | ||
| 3753 | #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 | ||
| 3754 | #define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 | ||
| 3755 | #define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 | ||
| 3756 | #define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 | ||
| 3757 | #define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 | ||
| 3758 | #define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 | ||
| 3759 | #define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 | ||
| 3760 | #define R_IRQ_MASK0_CLR__ext_dma1__clr 1 | ||
| 3761 | #define R_IRQ_MASK0_CLR__ext_dma1__nop 0 | ||
| 3762 | #define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 | ||
| 3763 | #define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 | ||
| 3764 | #define R_IRQ_MASK0_CLR__ext_dma0__clr 1 | ||
| 3765 | #define R_IRQ_MASK0_CLR__ext_dma0__nop 0 | ||
| 3766 | #define R_IRQ_MASK0_CLR__timer1__BITNR 1 | ||
| 3767 | #define R_IRQ_MASK0_CLR__timer1__WIDTH 1 | ||
| 3768 | #define R_IRQ_MASK0_CLR__timer1__clr 1 | ||
| 3769 | #define R_IRQ_MASK0_CLR__timer1__nop 0 | ||
| 3770 | #define R_IRQ_MASK0_CLR__timer0__BITNR 0 | ||
| 3771 | #define R_IRQ_MASK0_CLR__timer0__WIDTH 1 | ||
| 3772 | #define R_IRQ_MASK0_CLR__timer0__clr 1 | ||
| 3773 | #define R_IRQ_MASK0_CLR__timer0__nop 0 | ||
| 3774 | |||
| 3775 | #define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) | ||
| 3776 | #define R_IRQ_READ0__nmi_pin__BITNR 31 | ||
| 3777 | #define R_IRQ_READ0__nmi_pin__WIDTH 1 | ||
| 3778 | #define R_IRQ_READ0__nmi_pin__active 1 | ||
| 3779 | #define R_IRQ_READ0__nmi_pin__inactive 0 | ||
| 3780 | #define R_IRQ_READ0__watchdog_nmi__BITNR 30 | ||
| 3781 | #define R_IRQ_READ0__watchdog_nmi__WIDTH 1 | ||
| 3782 | #define R_IRQ_READ0__watchdog_nmi__active 1 | ||
| 3783 | #define R_IRQ_READ0__watchdog_nmi__inactive 0 | ||
| 3784 | #define R_IRQ_READ0__sqe_test_error__BITNR 29 | ||
| 3785 | #define R_IRQ_READ0__sqe_test_error__WIDTH 1 | ||
| 3786 | #define R_IRQ_READ0__sqe_test_error__active 1 | ||
| 3787 | #define R_IRQ_READ0__sqe_test_error__inactive 0 | ||
| 3788 | #define R_IRQ_READ0__carrier_loss__BITNR 28 | ||
| 3789 | #define R_IRQ_READ0__carrier_loss__WIDTH 1 | ||
| 3790 | #define R_IRQ_READ0__carrier_loss__active 1 | ||
| 3791 | #define R_IRQ_READ0__carrier_loss__inactive 0 | ||
| 3792 | #define R_IRQ_READ0__deferred__BITNR 27 | ||
| 3793 | #define R_IRQ_READ0__deferred__WIDTH 1 | ||
| 3794 | #define R_IRQ_READ0__deferred__active 1 | ||
| 3795 | #define R_IRQ_READ0__deferred__inactive 0 | ||
| 3796 | #define R_IRQ_READ0__late_col__BITNR 26 | ||
| 3797 | #define R_IRQ_READ0__late_col__WIDTH 1 | ||
| 3798 | #define R_IRQ_READ0__late_col__active 1 | ||
| 3799 | #define R_IRQ_READ0__late_col__inactive 0 | ||
| 3800 | #define R_IRQ_READ0__multiple_col__BITNR 25 | ||
| 3801 | #define R_IRQ_READ0__multiple_col__WIDTH 1 | ||
| 3802 | #define R_IRQ_READ0__multiple_col__active 1 | ||
| 3803 | #define R_IRQ_READ0__multiple_col__inactive 0 | ||
| 3804 | #define R_IRQ_READ0__single_col__BITNR 24 | ||
| 3805 | #define R_IRQ_READ0__single_col__WIDTH 1 | ||
| 3806 | #define R_IRQ_READ0__single_col__active 1 | ||
| 3807 | #define R_IRQ_READ0__single_col__inactive 0 | ||
| 3808 | #define R_IRQ_READ0__congestion__BITNR 23 | ||
| 3809 | #define R_IRQ_READ0__congestion__WIDTH 1 | ||
| 3810 | #define R_IRQ_READ0__congestion__active 1 | ||
| 3811 | #define R_IRQ_READ0__congestion__inactive 0 | ||
| 3812 | #define R_IRQ_READ0__oversize__BITNR 22 | ||
| 3813 | #define R_IRQ_READ0__oversize__WIDTH 1 | ||
| 3814 | #define R_IRQ_READ0__oversize__active 1 | ||
| 3815 | #define R_IRQ_READ0__oversize__inactive 0 | ||
| 3816 | #define R_IRQ_READ0__alignment_error__BITNR 21 | ||
| 3817 | #define R_IRQ_READ0__alignment_error__WIDTH 1 | ||
| 3818 | #define R_IRQ_READ0__alignment_error__active 1 | ||
| 3819 | #define R_IRQ_READ0__alignment_error__inactive 0 | ||
| 3820 | #define R_IRQ_READ0__crc_error__BITNR 20 | ||
| 3821 | #define R_IRQ_READ0__crc_error__WIDTH 1 | ||
| 3822 | #define R_IRQ_READ0__crc_error__active 1 | ||
| 3823 | #define R_IRQ_READ0__crc_error__inactive 0 | ||
| 3824 | #define R_IRQ_READ0__overrun__BITNR 19 | ||
| 3825 | #define R_IRQ_READ0__overrun__WIDTH 1 | ||
| 3826 | #define R_IRQ_READ0__overrun__active 1 | ||
| 3827 | #define R_IRQ_READ0__overrun__inactive 0 | ||
| 3828 | #define R_IRQ_READ0__underrun__BITNR 18 | ||
| 3829 | #define R_IRQ_READ0__underrun__WIDTH 1 | ||
| 3830 | #define R_IRQ_READ0__underrun__active 1 | ||
| 3831 | #define R_IRQ_READ0__underrun__inactive 0 | ||
| 3832 | #define R_IRQ_READ0__excessive_col__BITNR 17 | ||
| 3833 | #define R_IRQ_READ0__excessive_col__WIDTH 1 | ||
| 3834 | #define R_IRQ_READ0__excessive_col__active 1 | ||
| 3835 | #define R_IRQ_READ0__excessive_col__inactive 0 | ||
| 3836 | #define R_IRQ_READ0__mdio__BITNR 16 | ||
| 3837 | #define R_IRQ_READ0__mdio__WIDTH 1 | ||
| 3838 | #define R_IRQ_READ0__mdio__active 1 | ||
| 3839 | #define R_IRQ_READ0__mdio__inactive 0 | ||
| 3840 | #define R_IRQ_READ0__ata_drq3__BITNR 15 | ||
| 3841 | #define R_IRQ_READ0__ata_drq3__WIDTH 1 | ||
| 3842 | #define R_IRQ_READ0__ata_drq3__active 1 | ||
| 3843 | #define R_IRQ_READ0__ata_drq3__inactive 0 | ||
| 3844 | #define R_IRQ_READ0__ata_drq2__BITNR 14 | ||
| 3845 | #define R_IRQ_READ0__ata_drq2__WIDTH 1 | ||
| 3846 | #define R_IRQ_READ0__ata_drq2__active 1 | ||
| 3847 | #define R_IRQ_READ0__ata_drq2__inactive 0 | ||
| 3848 | #define R_IRQ_READ0__ata_drq1__BITNR 13 | ||
| 3849 | #define R_IRQ_READ0__ata_drq1__WIDTH 1 | ||
| 3850 | #define R_IRQ_READ0__ata_drq1__active 1 | ||
| 3851 | #define R_IRQ_READ0__ata_drq1__inactive 0 | ||
| 3852 | #define R_IRQ_READ0__ata_drq0__BITNR 12 | ||
| 3853 | #define R_IRQ_READ0__ata_drq0__WIDTH 1 | ||
| 3854 | #define R_IRQ_READ0__ata_drq0__active 1 | ||
| 3855 | #define R_IRQ_READ0__ata_drq0__inactive 0 | ||
| 3856 | #define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 | ||
| 3857 | #define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 | ||
| 3858 | #define R_IRQ_READ0__par0_ecp_cmd__active 1 | ||
| 3859 | #define R_IRQ_READ0__par0_ecp_cmd__inactive 0 | ||
| 3860 | #define R_IRQ_READ0__ata_irq3__BITNR 11 | ||
| 3861 | #define R_IRQ_READ0__ata_irq3__WIDTH 1 | ||
| 3862 | #define R_IRQ_READ0__ata_irq3__active 1 | ||
| 3863 | #define R_IRQ_READ0__ata_irq3__inactive 0 | ||
| 3864 | #define R_IRQ_READ0__par0_peri__BITNR 10 | ||
| 3865 | #define R_IRQ_READ0__par0_peri__WIDTH 1 | ||
| 3866 | #define R_IRQ_READ0__par0_peri__active 1 | ||
| 3867 | #define R_IRQ_READ0__par0_peri__inactive 0 | ||
| 3868 | #define R_IRQ_READ0__ata_irq2__BITNR 10 | ||
| 3869 | #define R_IRQ_READ0__ata_irq2__WIDTH 1 | ||
| 3870 | #define R_IRQ_READ0__ata_irq2__active 1 | ||
| 3871 | #define R_IRQ_READ0__ata_irq2__inactive 0 | ||
| 3872 | #define R_IRQ_READ0__par0_data__BITNR 9 | ||
| 3873 | #define R_IRQ_READ0__par0_data__WIDTH 1 | ||
| 3874 | #define R_IRQ_READ0__par0_data__active 1 | ||
| 3875 | #define R_IRQ_READ0__par0_data__inactive 0 | ||
| 3876 | #define R_IRQ_READ0__ata_irq1__BITNR 9 | ||
| 3877 | #define R_IRQ_READ0__ata_irq1__WIDTH 1 | ||
| 3878 | #define R_IRQ_READ0__ata_irq1__active 1 | ||
| 3879 | #define R_IRQ_READ0__ata_irq1__inactive 0 | ||
| 3880 | #define R_IRQ_READ0__par0_ready__BITNR 8 | ||
| 3881 | #define R_IRQ_READ0__par0_ready__WIDTH 1 | ||
| 3882 | #define R_IRQ_READ0__par0_ready__active 1 | ||
| 3883 | #define R_IRQ_READ0__par0_ready__inactive 0 | ||
| 3884 | #define R_IRQ_READ0__ata_irq0__BITNR 8 | ||
| 3885 | #define R_IRQ_READ0__ata_irq0__WIDTH 1 | ||
| 3886 | #define R_IRQ_READ0__ata_irq0__active 1 | ||
| 3887 | #define R_IRQ_READ0__ata_irq0__inactive 0 | ||
| 3888 | #define R_IRQ_READ0__mio__BITNR 8 | ||
| 3889 | #define R_IRQ_READ0__mio__WIDTH 1 | ||
| 3890 | #define R_IRQ_READ0__mio__active 1 | ||
| 3891 | #define R_IRQ_READ0__mio__inactive 0 | ||
| 3892 | #define R_IRQ_READ0__scsi0__BITNR 8 | ||
| 3893 | #define R_IRQ_READ0__scsi0__WIDTH 1 | ||
| 3894 | #define R_IRQ_READ0__scsi0__active 1 | ||
| 3895 | #define R_IRQ_READ0__scsi0__inactive 0 | ||
| 3896 | #define R_IRQ_READ0__ata_dmaend__BITNR 7 | ||
| 3897 | #define R_IRQ_READ0__ata_dmaend__WIDTH 1 | ||
| 3898 | #define R_IRQ_READ0__ata_dmaend__active 1 | ||
| 3899 | #define R_IRQ_READ0__ata_dmaend__inactive 0 | ||
| 3900 | #define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 | ||
| 3901 | #define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 | ||
| 3902 | #define R_IRQ_READ0__irq_ext_vector_nr__active 1 | ||
| 3903 | #define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 | ||
| 3904 | #define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 | ||
| 3905 | #define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 | ||
| 3906 | #define R_IRQ_READ0__irq_int_vector_nr__active 1 | ||
| 3907 | #define R_IRQ_READ0__irq_int_vector_nr__inactive 0 | ||
| 3908 | #define R_IRQ_READ0__ext_dma1__BITNR 3 | ||
| 3909 | #define R_IRQ_READ0__ext_dma1__WIDTH 1 | ||
| 3910 | #define R_IRQ_READ0__ext_dma1__active 1 | ||
| 3911 | #define R_IRQ_READ0__ext_dma1__inactive 0 | ||
| 3912 | #define R_IRQ_READ0__ext_dma0__BITNR 2 | ||
| 3913 | #define R_IRQ_READ0__ext_dma0__WIDTH 1 | ||
| 3914 | #define R_IRQ_READ0__ext_dma0__active 1 | ||
| 3915 | #define R_IRQ_READ0__ext_dma0__inactive 0 | ||
| 3916 | #define R_IRQ_READ0__timer1__BITNR 1 | ||
| 3917 | #define R_IRQ_READ0__timer1__WIDTH 1 | ||
| 3918 | #define R_IRQ_READ0__timer1__active 1 | ||
| 3919 | #define R_IRQ_READ0__timer1__inactive 0 | ||
| 3920 | #define R_IRQ_READ0__timer0__BITNR 0 | ||
| 3921 | #define R_IRQ_READ0__timer0__WIDTH 1 | ||
| 3922 | #define R_IRQ_READ0__timer0__active 1 | ||
| 3923 | #define R_IRQ_READ0__timer0__inactive 0 | ||
| 3924 | |||
| 3925 | #define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) | ||
| 3926 | #define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 | ||
| 3927 | #define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 | ||
| 3928 | #define R_IRQ_MASK0_SET__nmi_pin__set 1 | ||
| 3929 | #define R_IRQ_MASK0_SET__nmi_pin__nop 0 | ||
| 3930 | #define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 | ||
| 3931 | #define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 | ||
| 3932 | #define R_IRQ_MASK0_SET__watchdog_nmi__set 1 | ||
| 3933 | #define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 | ||
| 3934 | #define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 | ||
| 3935 | #define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 | ||
| 3936 | #define R_IRQ_MASK0_SET__sqe_test_error__set 1 | ||
| 3937 | #define R_IRQ_MASK0_SET__sqe_test_error__nop 0 | ||
| 3938 | #define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 | ||
| 3939 | #define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 | ||
| 3940 | #define R_IRQ_MASK0_SET__carrier_loss__set 1 | ||
| 3941 | #define R_IRQ_MASK0_SET__carrier_loss__nop 0 | ||
| 3942 | #define R_IRQ_MASK0_SET__deferred__BITNR 27 | ||
| 3943 | #define R_IRQ_MASK0_SET__deferred__WIDTH 1 | ||
| 3944 | #define R_IRQ_MASK0_SET__deferred__set 1 | ||
| 3945 | #define R_IRQ_MASK0_SET__deferred__nop 0 | ||
| 3946 | #define R_IRQ_MASK0_SET__late_col__BITNR 26 | ||
| 3947 | #define R_IRQ_MASK0_SET__late_col__WIDTH 1 | ||
| 3948 | #define R_IRQ_MASK0_SET__late_col__set 1 | ||
| 3949 | #define R_IRQ_MASK0_SET__late_col__nop 0 | ||
| 3950 | #define R_IRQ_MASK0_SET__multiple_col__BITNR 25 | ||
| 3951 | #define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 | ||
| 3952 | #define R_IRQ_MASK0_SET__multiple_col__set 1 | ||
| 3953 | #define R_IRQ_MASK0_SET__multiple_col__nop 0 | ||
| 3954 | #define R_IRQ_MASK0_SET__single_col__BITNR 24 | ||
| 3955 | #define R_IRQ_MASK0_SET__single_col__WIDTH 1 | ||
| 3956 | #define R_IRQ_MASK0_SET__single_col__set 1 | ||
| 3957 | #define R_IRQ_MASK0_SET__single_col__nop 0 | ||
| 3958 | #define R_IRQ_MASK0_SET__congestion__BITNR 23 | ||
| 3959 | #define R_IRQ_MASK0_SET__congestion__WIDTH 1 | ||
| 3960 | #define R_IRQ_MASK0_SET__congestion__set 1 | ||
| 3961 | #define R_IRQ_MASK0_SET__congestion__nop 0 | ||
| 3962 | #define R_IRQ_MASK0_SET__oversize__BITNR 22 | ||
| 3963 | #define R_IRQ_MASK0_SET__oversize__WIDTH 1 | ||
| 3964 | #define R_IRQ_MASK0_SET__oversize__set 1 | ||
| 3965 | #define R_IRQ_MASK0_SET__oversize__nop 0 | ||
| 3966 | #define R_IRQ_MASK0_SET__alignment_error__BITNR 21 | ||
| 3967 | #define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 | ||
| 3968 | #define R_IRQ_MASK0_SET__alignment_error__set 1 | ||
| 3969 | #define R_IRQ_MASK0_SET__alignment_error__nop 0 | ||
| 3970 | #define R_IRQ_MASK0_SET__crc_error__BITNR 20 | ||
| 3971 | #define R_IRQ_MASK0_SET__crc_error__WIDTH 1 | ||
| 3972 | #define R_IRQ_MASK0_SET__crc_error__set 1 | ||
| 3973 | #define R_IRQ_MASK0_SET__crc_error__nop 0 | ||
| 3974 | #define R_IRQ_MASK0_SET__overrun__BITNR 19 | ||
| 3975 | #define R_IRQ_MASK0_SET__overrun__WIDTH 1 | ||
| 3976 | #define R_IRQ_MASK0_SET__overrun__set 1 | ||
| 3977 | #define R_IRQ_MASK0_SET__overrun__nop 0 | ||
| 3978 | #define R_IRQ_MASK0_SET__underrun__BITNR 18 | ||
| 3979 | #define R_IRQ_MASK0_SET__underrun__WIDTH 1 | ||
| 3980 | #define R_IRQ_MASK0_SET__underrun__set 1 | ||
| 3981 | #define R_IRQ_MASK0_SET__underrun__nop 0 | ||
| 3982 | #define R_IRQ_MASK0_SET__excessive_col__BITNR 17 | ||
| 3983 | #define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 | ||
| 3984 | #define R_IRQ_MASK0_SET__excessive_col__set 1 | ||
| 3985 | #define R_IRQ_MASK0_SET__excessive_col__nop 0 | ||
| 3986 | #define R_IRQ_MASK0_SET__mdio__BITNR 16 | ||
| 3987 | #define R_IRQ_MASK0_SET__mdio__WIDTH 1 | ||
| 3988 | #define R_IRQ_MASK0_SET__mdio__set 1 | ||
| 3989 | #define R_IRQ_MASK0_SET__mdio__nop 0 | ||
| 3990 | #define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 | ||
| 3991 | #define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 | ||
| 3992 | #define R_IRQ_MASK0_SET__ata_drq3__set 1 | ||
| 3993 | #define R_IRQ_MASK0_SET__ata_drq3__nop 0 | ||
| 3994 | #define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 | ||
| 3995 | #define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 | ||
| 3996 | #define R_IRQ_MASK0_SET__ata_drq2__set 1 | ||
| 3997 | #define R_IRQ_MASK0_SET__ata_drq2__nop 0 | ||
| 3998 | #define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 | ||
| 3999 | #define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 | ||
| 4000 | #define R_IRQ_MASK0_SET__ata_drq1__set 1 | ||
| 4001 | #define R_IRQ_MASK0_SET__ata_drq1__nop 0 | ||
| 4002 | #define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 | ||
| 4003 | #define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 | ||
| 4004 | #define R_IRQ_MASK0_SET__ata_drq0__set 1 | ||
| 4005 | #define R_IRQ_MASK0_SET__ata_drq0__nop 0 | ||
| 4006 | #define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 | ||
| 4007 | #define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 | ||
| 4008 | #define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 | ||
| 4009 | #define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 | ||
| 4010 | #define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 | ||
| 4011 | #define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 | ||
| 4012 | #define R_IRQ_MASK0_SET__ata_irq3__set 1 | ||
| 4013 | #define R_IRQ_MASK0_SET__ata_irq3__nop 0 | ||
| 4014 | #define R_IRQ_MASK0_SET__par0_peri__BITNR 10 | ||
| 4015 | #define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 | ||
| 4016 | #define R_IRQ_MASK0_SET__par0_peri__set 1 | ||
| 4017 | #define R_IRQ_MASK0_SET__par0_peri__nop 0 | ||
| 4018 | #define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 | ||
| 4019 | #define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 | ||
| 4020 | #define R_IRQ_MASK0_SET__ata_irq2__set 1 | ||
| 4021 | #define R_IRQ_MASK0_SET__ata_irq2__nop 0 | ||
| 4022 | #define R_IRQ_MASK0_SET__par0_data__BITNR 9 | ||
| 4023 | #define R_IRQ_MASK0_SET__par0_data__WIDTH 1 | ||
| 4024 | #define R_IRQ_MASK0_SET__par0_data__set 1 | ||
| 4025 | #define R_IRQ_MASK0_SET__par0_data__nop 0 | ||
| 4026 | #define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 | ||
| 4027 | #define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 | ||
| 4028 | #define R_IRQ_MASK0_SET__ata_irq1__set 1 | ||
| 4029 | #define R_IRQ_MASK0_SET__ata_irq1__nop 0 | ||
| 4030 | #define R_IRQ_MASK0_SET__par0_ready__BITNR 8 | ||
| 4031 | #define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 | ||
| 4032 | #define R_IRQ_MASK0_SET__par0_ready__set 1 | ||
| 4033 | #define R_IRQ_MASK0_SET__par0_ready__nop 0 | ||
| 4034 | #define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 | ||
| 4035 | #define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 | ||
| 4036 | #define R_IRQ_MASK0_SET__ata_irq0__set 1 | ||
| 4037 | #define R_IRQ_MASK0_SET__ata_irq0__nop 0 | ||
| 4038 | #define R_IRQ_MASK0_SET__mio__BITNR 8 | ||
| 4039 | #define R_IRQ_MASK0_SET__mio__WIDTH 1 | ||
| 4040 | #define R_IRQ_MASK0_SET__mio__set 1 | ||
| 4041 | #define R_IRQ_MASK0_SET__mio__nop 0 | ||
| 4042 | #define R_IRQ_MASK0_SET__scsi0__BITNR 8 | ||
| 4043 | #define R_IRQ_MASK0_SET__scsi0__WIDTH 1 | ||
| 4044 | #define R_IRQ_MASK0_SET__scsi0__set 1 | ||
| 4045 | #define R_IRQ_MASK0_SET__scsi0__nop 0 | ||
| 4046 | #define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 | ||
| 4047 | #define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 | ||
| 4048 | #define R_IRQ_MASK0_SET__ata_dmaend__set 1 | ||
| 4049 | #define R_IRQ_MASK0_SET__ata_dmaend__nop 0 | ||
| 4050 | #define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 | ||
| 4051 | #define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 | ||
| 4052 | #define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 | ||
| 4053 | #define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 | ||
| 4054 | #define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 | ||
| 4055 | #define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 | ||
| 4056 | #define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 | ||
| 4057 | #define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 | ||
| 4058 | #define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 | ||
| 4059 | #define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 | ||
| 4060 | #define R_IRQ_MASK0_SET__ext_dma1__set 1 | ||
| 4061 | #define R_IRQ_MASK0_SET__ext_dma1__nop 0 | ||
| 4062 | #define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 | ||
| 4063 | #define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 | ||
| 4064 | #define R_IRQ_MASK0_SET__ext_dma0__set 1 | ||
| 4065 | #define R_IRQ_MASK0_SET__ext_dma0__nop 0 | ||
| 4066 | #define R_IRQ_MASK0_SET__timer1__BITNR 1 | ||
| 4067 | #define R_IRQ_MASK0_SET__timer1__WIDTH 1 | ||
| 4068 | #define R_IRQ_MASK0_SET__timer1__set 1 | ||
| 4069 | #define R_IRQ_MASK0_SET__timer1__nop 0 | ||
| 4070 | #define R_IRQ_MASK0_SET__timer0__BITNR 0 | ||
| 4071 | #define R_IRQ_MASK0_SET__timer0__WIDTH 1 | ||
| 4072 | #define R_IRQ_MASK0_SET__timer0__set 1 | ||
| 4073 | #define R_IRQ_MASK0_SET__timer0__nop 0 | ||
| 4074 | |||
| 4075 | #define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) | ||
| 4076 | #define R_IRQ_MASK1_RD__sw_int7__BITNR 31 | ||
| 4077 | #define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 | ||
| 4078 | #define R_IRQ_MASK1_RD__sw_int7__active 1 | ||
| 4079 | #define R_IRQ_MASK1_RD__sw_int7__inactive 0 | ||
| 4080 | #define R_IRQ_MASK1_RD__sw_int6__BITNR 30 | ||
| 4081 | #define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 | ||
| 4082 | #define R_IRQ_MASK1_RD__sw_int6__active 1 | ||
| 4083 | #define R_IRQ_MASK1_RD__sw_int6__inactive 0 | ||
| 4084 | #define R_IRQ_MASK1_RD__sw_int5__BITNR 29 | ||
| 4085 | #define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 | ||
| 4086 | #define R_IRQ_MASK1_RD__sw_int5__active 1 | ||
| 4087 | #define R_IRQ_MASK1_RD__sw_int5__inactive 0 | ||
| 4088 | #define R_IRQ_MASK1_RD__sw_int4__BITNR 28 | ||
| 4089 | #define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 | ||
| 4090 | #define R_IRQ_MASK1_RD__sw_int4__active 1 | ||
| 4091 | #define R_IRQ_MASK1_RD__sw_int4__inactive 0 | ||
| 4092 | #define R_IRQ_MASK1_RD__sw_int3__BITNR 27 | ||
| 4093 | #define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 | ||
| 4094 | #define R_IRQ_MASK1_RD__sw_int3__active 1 | ||
| 4095 | #define R_IRQ_MASK1_RD__sw_int3__inactive 0 | ||
| 4096 | #define R_IRQ_MASK1_RD__sw_int2__BITNR 26 | ||
| 4097 | #define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 | ||
| 4098 | #define R_IRQ_MASK1_RD__sw_int2__active 1 | ||
| 4099 | #define R_IRQ_MASK1_RD__sw_int2__inactive 0 | ||
| 4100 | #define R_IRQ_MASK1_RD__sw_int1__BITNR 25 | ||
| 4101 | #define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 | ||
| 4102 | #define R_IRQ_MASK1_RD__sw_int1__active 1 | ||
| 4103 | #define R_IRQ_MASK1_RD__sw_int1__inactive 0 | ||
| 4104 | #define R_IRQ_MASK1_RD__sw_int0__BITNR 24 | ||
| 4105 | #define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 | ||
| 4106 | #define R_IRQ_MASK1_RD__sw_int0__active 1 | ||
| 4107 | #define R_IRQ_MASK1_RD__sw_int0__inactive 0 | ||
| 4108 | #define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 | ||
| 4109 | #define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 | ||
| 4110 | #define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 | ||
| 4111 | #define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 | ||
| 4112 | #define R_IRQ_MASK1_RD__par1_peri__BITNR 18 | ||
| 4113 | #define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 | ||
| 4114 | #define R_IRQ_MASK1_RD__par1_peri__active 1 | ||
| 4115 | #define R_IRQ_MASK1_RD__par1_peri__inactive 0 | ||
| 4116 | #define R_IRQ_MASK1_RD__par1_data__BITNR 17 | ||
| 4117 | #define R_IRQ_MASK1_RD__par1_data__WIDTH 1 | ||
| 4118 | #define R_IRQ_MASK1_RD__par1_data__active 1 | ||
| 4119 | #define R_IRQ_MASK1_RD__par1_data__inactive 0 | ||
| 4120 | #define R_IRQ_MASK1_RD__par1_ready__BITNR 16 | ||
| 4121 | #define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 | ||
| 4122 | #define R_IRQ_MASK1_RD__par1_ready__active 1 | ||
| 4123 | #define R_IRQ_MASK1_RD__par1_ready__inactive 0 | ||
| 4124 | #define R_IRQ_MASK1_RD__scsi1__BITNR 16 | ||
| 4125 | #define R_IRQ_MASK1_RD__scsi1__WIDTH 1 | ||
| 4126 | #define R_IRQ_MASK1_RD__scsi1__active 1 | ||
| 4127 | #define R_IRQ_MASK1_RD__scsi1__inactive 0 | ||
| 4128 | #define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 | ||
| 4129 | #define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 | ||
| 4130 | #define R_IRQ_MASK1_RD__ser3_ready__active 1 | ||
| 4131 | #define R_IRQ_MASK1_RD__ser3_ready__inactive 0 | ||
| 4132 | #define R_IRQ_MASK1_RD__ser3_data__BITNR 14 | ||
| 4133 | #define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 | ||
| 4134 | #define R_IRQ_MASK1_RD__ser3_data__active 1 | ||
| 4135 | #define R_IRQ_MASK1_RD__ser3_data__inactive 0 | ||
| 4136 | #define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 | ||
| 4137 | #define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 | ||
| 4138 | #define R_IRQ_MASK1_RD__ser2_ready__active 1 | ||
| 4139 | #define R_IRQ_MASK1_RD__ser2_ready__inactive 0 | ||
| 4140 | #define R_IRQ_MASK1_RD__ser2_data__BITNR 12 | ||
| 4141 | #define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 | ||
| 4142 | #define R_IRQ_MASK1_RD__ser2_data__active 1 | ||
| 4143 | #define R_IRQ_MASK1_RD__ser2_data__inactive 0 | ||
| 4144 | #define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 | ||
| 4145 | #define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 | ||
| 4146 | #define R_IRQ_MASK1_RD__ser1_ready__active 1 | ||
| 4147 | #define R_IRQ_MASK1_RD__ser1_ready__inactive 0 | ||
| 4148 | #define R_IRQ_MASK1_RD__ser1_data__BITNR 10 | ||
| 4149 | #define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 | ||
| 4150 | #define R_IRQ_MASK1_RD__ser1_data__active 1 | ||
| 4151 | #define R_IRQ_MASK1_RD__ser1_data__inactive 0 | ||
| 4152 | #define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 | ||
| 4153 | #define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 | ||
| 4154 | #define R_IRQ_MASK1_RD__ser0_ready__active 1 | ||
| 4155 | #define R_IRQ_MASK1_RD__ser0_ready__inactive 0 | ||
| 4156 | #define R_IRQ_MASK1_RD__ser0_data__BITNR 8 | ||
| 4157 | #define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 | ||
| 4158 | #define R_IRQ_MASK1_RD__ser0_data__active 1 | ||
| 4159 | #define R_IRQ_MASK1_RD__ser0_data__inactive 0 | ||
| 4160 | #define R_IRQ_MASK1_RD__pa7__BITNR 7 | ||
| 4161 | #define R_IRQ_MASK1_RD__pa7__WIDTH 1 | ||
| 4162 | #define R_IRQ_MASK1_RD__pa7__active 1 | ||
| 4163 | #define R_IRQ_MASK1_RD__pa7__inactive 0 | ||
| 4164 | #define R_IRQ_MASK1_RD__pa6__BITNR 6 | ||
| 4165 | #define R_IRQ_MASK1_RD__pa6__WIDTH 1 | ||
| 4166 | #define R_IRQ_MASK1_RD__pa6__active 1 | ||
| 4167 | #define R_IRQ_MASK1_RD__pa6__inactive 0 | ||
| 4168 | #define R_IRQ_MASK1_RD__pa5__BITNR 5 | ||
| 4169 | #define R_IRQ_MASK1_RD__pa5__WIDTH 1 | ||
| 4170 | #define R_IRQ_MASK1_RD__pa5__active 1 | ||
| 4171 | #define R_IRQ_MASK1_RD__pa5__inactive 0 | ||
| 4172 | #define R_IRQ_MASK1_RD__pa4__BITNR 4 | ||
| 4173 | #define R_IRQ_MASK1_RD__pa4__WIDTH 1 | ||
| 4174 | #define R_IRQ_MASK1_RD__pa4__active 1 | ||
| 4175 | #define R_IRQ_MASK1_RD__pa4__inactive 0 | ||
| 4176 | #define R_IRQ_MASK1_RD__pa3__BITNR 3 | ||
| 4177 | #define R_IRQ_MASK1_RD__pa3__WIDTH 1 | ||
| 4178 | #define R_IRQ_MASK1_RD__pa3__active 1 | ||
| 4179 | #define R_IRQ_MASK1_RD__pa3__inactive 0 | ||
| 4180 | #define R_IRQ_MASK1_RD__pa2__BITNR 2 | ||
| 4181 | #define R_IRQ_MASK1_RD__pa2__WIDTH 1 | ||
| 4182 | #define R_IRQ_MASK1_RD__pa2__active 1 | ||
| 4183 | #define R_IRQ_MASK1_RD__pa2__inactive 0 | ||
| 4184 | #define R_IRQ_MASK1_RD__pa1__BITNR 1 | ||
| 4185 | #define R_IRQ_MASK1_RD__pa1__WIDTH 1 | ||
| 4186 | #define R_IRQ_MASK1_RD__pa1__active 1 | ||
| 4187 | #define R_IRQ_MASK1_RD__pa1__inactive 0 | ||
| 4188 | #define R_IRQ_MASK1_RD__pa0__BITNR 0 | ||
| 4189 | #define R_IRQ_MASK1_RD__pa0__WIDTH 1 | ||
| 4190 | #define R_IRQ_MASK1_RD__pa0__active 1 | ||
| 4191 | #define R_IRQ_MASK1_RD__pa0__inactive 0 | ||
| 4192 | |||
| 4193 | #define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) | ||
| 4194 | #define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 | ||
| 4195 | #define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 | ||
| 4196 | #define R_IRQ_MASK1_CLR__sw_int7__clr 1 | ||
| 4197 | #define R_IRQ_MASK1_CLR__sw_int7__nop 0 | ||
| 4198 | #define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 | ||
| 4199 | #define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 | ||
| 4200 | #define R_IRQ_MASK1_CLR__sw_int6__clr 1 | ||
| 4201 | #define R_IRQ_MASK1_CLR__sw_int6__nop 0 | ||
| 4202 | #define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 | ||
| 4203 | #define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 | ||
| 4204 | #define R_IRQ_MASK1_CLR__sw_int5__clr 1 | ||
| 4205 | #define R_IRQ_MASK1_CLR__sw_int5__nop 0 | ||
| 4206 | #define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 | ||
| 4207 | #define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 | ||
| 4208 | #define R_IRQ_MASK1_CLR__sw_int4__clr 1 | ||
| 4209 | #define R_IRQ_MASK1_CLR__sw_int4__nop 0 | ||
| 4210 | #define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 | ||
| 4211 | #define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 | ||
| 4212 | #define R_IRQ_MASK1_CLR__sw_int3__clr 1 | ||
| 4213 | #define R_IRQ_MASK1_CLR__sw_int3__nop 0 | ||
| 4214 | #define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 | ||
| 4215 | #define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 | ||
| 4216 | #define R_IRQ_MASK1_CLR__sw_int2__clr 1 | ||
| 4217 | #define R_IRQ_MASK1_CLR__sw_int2__nop 0 | ||
| 4218 | #define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 | ||
| 4219 | #define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 | ||
| 4220 | #define R_IRQ_MASK1_CLR__sw_int1__clr 1 | ||
| 4221 | #define R_IRQ_MASK1_CLR__sw_int1__nop 0 | ||
| 4222 | #define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 | ||
| 4223 | #define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 | ||
| 4224 | #define R_IRQ_MASK1_CLR__sw_int0__clr 1 | ||
| 4225 | #define R_IRQ_MASK1_CLR__sw_int0__nop 0 | ||
| 4226 | #define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 | ||
| 4227 | #define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 | ||
| 4228 | #define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 | ||
| 4229 | #define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 | ||
| 4230 | #define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 | ||
| 4231 | #define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 | ||
| 4232 | #define R_IRQ_MASK1_CLR__par1_peri__clr 1 | ||
| 4233 | #define R_IRQ_MASK1_CLR__par1_peri__nop 0 | ||
| 4234 | #define R_IRQ_MASK1_CLR__par1_data__BITNR 17 | ||
| 4235 | #define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 | ||
| 4236 | #define R_IRQ_MASK1_CLR__par1_data__clr 1 | ||
| 4237 | #define R_IRQ_MASK1_CLR__par1_data__nop 0 | ||
| 4238 | #define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 | ||
| 4239 | #define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 | ||
| 4240 | #define R_IRQ_MASK1_CLR__par1_ready__clr 1 | ||
| 4241 | #define R_IRQ_MASK1_CLR__par1_ready__nop 0 | ||
| 4242 | #define R_IRQ_MASK1_CLR__scsi1__BITNR 16 | ||
| 4243 | #define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 | ||
| 4244 | #define R_IRQ_MASK1_CLR__scsi1__clr 1 | ||
| 4245 | #define R_IRQ_MASK1_CLR__scsi1__nop 0 | ||
| 4246 | #define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 | ||
| 4247 | #define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 | ||
| 4248 | #define R_IRQ_MASK1_CLR__ser3_ready__clr 1 | ||
| 4249 | #define R_IRQ_MASK1_CLR__ser3_ready__nop 0 | ||
| 4250 | #define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 | ||
| 4251 | #define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 | ||
| 4252 | #define R_IRQ_MASK1_CLR__ser3_data__clr 1 | ||
| 4253 | #define R_IRQ_MASK1_CLR__ser3_data__nop 0 | ||
| 4254 | #define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 | ||
| 4255 | #define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 | ||
| 4256 | #define R_IRQ_MASK1_CLR__ser2_ready__clr 1 | ||
| 4257 | #define R_IRQ_MASK1_CLR__ser2_ready__nop 0 | ||
| 4258 | #define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 | ||
| 4259 | #define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 | ||
| 4260 | #define R_IRQ_MASK1_CLR__ser2_data__clr 1 | ||
| 4261 | #define R_IRQ_MASK1_CLR__ser2_data__nop 0 | ||
| 4262 | #define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 | ||
| 4263 | #define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 | ||
| 4264 | #define R_IRQ_MASK1_CLR__ser1_ready__clr 1 | ||
| 4265 | #define R_IRQ_MASK1_CLR__ser1_ready__nop 0 | ||
| 4266 | #define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 | ||
| 4267 | #define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 | ||
| 4268 | #define R_IRQ_MASK1_CLR__ser1_data__clr 1 | ||
| 4269 | #define R_IRQ_MASK1_CLR__ser1_data__nop 0 | ||
| 4270 | #define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 | ||
| 4271 | #define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 | ||
| 4272 | #define R_IRQ_MASK1_CLR__ser0_ready__clr 1 | ||
| 4273 | #define R_IRQ_MASK1_CLR__ser0_ready__nop 0 | ||
| 4274 | #define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 | ||
| 4275 | #define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 | ||
| 4276 | #define R_IRQ_MASK1_CLR__ser0_data__clr 1 | ||
| 4277 | #define R_IRQ_MASK1_CLR__ser0_data__nop 0 | ||
| 4278 | #define R_IRQ_MASK1_CLR__pa7__BITNR 7 | ||
| 4279 | #define R_IRQ_MASK1_CLR__pa7__WIDTH 1 | ||
| 4280 | #define R_IRQ_MASK1_CLR__pa7__clr 1 | ||
| 4281 | #define R_IRQ_MASK1_CLR__pa7__nop 0 | ||
| 4282 | #define R_IRQ_MASK1_CLR__pa6__BITNR 6 | ||
| 4283 | #define R_IRQ_MASK1_CLR__pa6__WIDTH 1 | ||
| 4284 | #define R_IRQ_MASK1_CLR__pa6__clr 1 | ||
| 4285 | #define R_IRQ_MASK1_CLR__pa6__nop 0 | ||
| 4286 | #define R_IRQ_MASK1_CLR__pa5__BITNR 5 | ||
| 4287 | #define R_IRQ_MASK1_CLR__pa5__WIDTH 1 | ||
| 4288 | #define R_IRQ_MASK1_CLR__pa5__clr 1 | ||
| 4289 | #define R_IRQ_MASK1_CLR__pa5__nop 0 | ||
| 4290 | #define R_IRQ_MASK1_CLR__pa4__BITNR 4 | ||
| 4291 | #define R_IRQ_MASK1_CLR__pa4__WIDTH 1 | ||
| 4292 | #define R_IRQ_MASK1_CLR__pa4__clr 1 | ||
| 4293 | #define R_IRQ_MASK1_CLR__pa4__nop 0 | ||
| 4294 | #define R_IRQ_MASK1_CLR__pa3__BITNR 3 | ||
| 4295 | #define R_IRQ_MASK1_CLR__pa3__WIDTH 1 | ||
| 4296 | #define R_IRQ_MASK1_CLR__pa3__clr 1 | ||
| 4297 | #define R_IRQ_MASK1_CLR__pa3__nop 0 | ||
| 4298 | #define R_IRQ_MASK1_CLR__pa2__BITNR 2 | ||
| 4299 | #define R_IRQ_MASK1_CLR__pa2__WIDTH 1 | ||
| 4300 | #define R_IRQ_MASK1_CLR__pa2__clr 1 | ||
| 4301 | #define R_IRQ_MASK1_CLR__pa2__nop 0 | ||
| 4302 | #define R_IRQ_MASK1_CLR__pa1__BITNR 1 | ||
| 4303 | #define R_IRQ_MASK1_CLR__pa1__WIDTH 1 | ||
| 4304 | #define R_IRQ_MASK1_CLR__pa1__clr 1 | ||
| 4305 | #define R_IRQ_MASK1_CLR__pa1__nop 0 | ||
| 4306 | #define R_IRQ_MASK1_CLR__pa0__BITNR 0 | ||
| 4307 | #define R_IRQ_MASK1_CLR__pa0__WIDTH 1 | ||
| 4308 | #define R_IRQ_MASK1_CLR__pa0__clr 1 | ||
| 4309 | #define R_IRQ_MASK1_CLR__pa0__nop 0 | ||
| 4310 | |||
| 4311 | #define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) | ||
| 4312 | #define R_IRQ_READ1__sw_int7__BITNR 31 | ||
| 4313 | #define R_IRQ_READ1__sw_int7__WIDTH 1 | ||
| 4314 | #define R_IRQ_READ1__sw_int7__active 1 | ||
| 4315 | #define R_IRQ_READ1__sw_int7__inactive 0 | ||
| 4316 | #define R_IRQ_READ1__sw_int6__BITNR 30 | ||
| 4317 | #define R_IRQ_READ1__sw_int6__WIDTH 1 | ||
| 4318 | #define R_IRQ_READ1__sw_int6__active 1 | ||
| 4319 | #define R_IRQ_READ1__sw_int6__inactive 0 | ||
| 4320 | #define R_IRQ_READ1__sw_int5__BITNR 29 | ||
| 4321 | #define R_IRQ_READ1__sw_int5__WIDTH 1 | ||
| 4322 | #define R_IRQ_READ1__sw_int5__active 1 | ||
| 4323 | #define R_IRQ_READ1__sw_int5__inactive 0 | ||
| 4324 | #define R_IRQ_READ1__sw_int4__BITNR 28 | ||
| 4325 | #define R_IRQ_READ1__sw_int4__WIDTH 1 | ||
| 4326 | #define R_IRQ_READ1__sw_int4__active 1 | ||
| 4327 | #define R_IRQ_READ1__sw_int4__inactive 0 | ||
| 4328 | #define R_IRQ_READ1__sw_int3__BITNR 27 | ||
| 4329 | #define R_IRQ_READ1__sw_int3__WIDTH 1 | ||
| 4330 | #define R_IRQ_READ1__sw_int3__active 1 | ||
| 4331 | #define R_IRQ_READ1__sw_int3__inactive 0 | ||
| 4332 | #define R_IRQ_READ1__sw_int2__BITNR 26 | ||
| 4333 | #define R_IRQ_READ1__sw_int2__WIDTH 1 | ||
| 4334 | #define R_IRQ_READ1__sw_int2__active 1 | ||
| 4335 | #define R_IRQ_READ1__sw_int2__inactive 0 | ||
| 4336 | #define R_IRQ_READ1__sw_int1__BITNR 25 | ||
| 4337 | #define R_IRQ_READ1__sw_int1__WIDTH 1 | ||
| 4338 | #define R_IRQ_READ1__sw_int1__active 1 | ||
| 4339 | #define R_IRQ_READ1__sw_int1__inactive 0 | ||
| 4340 | #define R_IRQ_READ1__sw_int0__BITNR 24 | ||
| 4341 | #define R_IRQ_READ1__sw_int0__WIDTH 1 | ||
| 4342 | #define R_IRQ_READ1__sw_int0__active 1 | ||
| 4343 | #define R_IRQ_READ1__sw_int0__inactive 0 | ||
| 4344 | #define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 | ||
| 4345 | #define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 | ||
| 4346 | #define R_IRQ_READ1__par1_ecp_cmd__active 1 | ||
| 4347 | #define R_IRQ_READ1__par1_ecp_cmd__inactive 0 | ||
| 4348 | #define R_IRQ_READ1__par1_peri__BITNR 18 | ||
| 4349 | #define R_IRQ_READ1__par1_peri__WIDTH 1 | ||
| 4350 | #define R_IRQ_READ1__par1_peri__active 1 | ||
| 4351 | #define R_IRQ_READ1__par1_peri__inactive 0 | ||
| 4352 | #define R_IRQ_READ1__par1_data__BITNR 17 | ||
| 4353 | #define R_IRQ_READ1__par1_data__WIDTH 1 | ||
| 4354 | #define R_IRQ_READ1__par1_data__active 1 | ||
| 4355 | #define R_IRQ_READ1__par1_data__inactive 0 | ||
| 4356 | #define R_IRQ_READ1__par1_ready__BITNR 16 | ||
| 4357 | #define R_IRQ_READ1__par1_ready__WIDTH 1 | ||
| 4358 | #define R_IRQ_READ1__par1_ready__active 1 | ||
| 4359 | #define R_IRQ_READ1__par1_ready__inactive 0 | ||
| 4360 | #define R_IRQ_READ1__scsi1__BITNR 16 | ||
| 4361 | #define R_IRQ_READ1__scsi1__WIDTH 1 | ||
| 4362 | #define R_IRQ_READ1__scsi1__active 1 | ||
| 4363 | #define R_IRQ_READ1__scsi1__inactive 0 | ||
| 4364 | #define R_IRQ_READ1__ser3_ready__BITNR 15 | ||
| 4365 | #define R_IRQ_READ1__ser3_ready__WIDTH 1 | ||
| 4366 | #define R_IRQ_READ1__ser3_ready__active 1 | ||
| 4367 | #define R_IRQ_READ1__ser3_ready__inactive 0 | ||
| 4368 | #define R_IRQ_READ1__ser3_data__BITNR 14 | ||
| 4369 | #define R_IRQ_READ1__ser3_data__WIDTH 1 | ||
| 4370 | #define R_IRQ_READ1__ser3_data__active 1 | ||
| 4371 | #define R_IRQ_READ1__ser3_data__inactive 0 | ||
| 4372 | #define R_IRQ_READ1__ser2_ready__BITNR 13 | ||
| 4373 | #define R_IRQ_READ1__ser2_ready__WIDTH 1 | ||
| 4374 | #define R_IRQ_READ1__ser2_ready__active 1 | ||
| 4375 | #define R_IRQ_READ1__ser2_ready__inactive 0 | ||
| 4376 | #define R_IRQ_READ1__ser2_data__BITNR 12 | ||
| 4377 | #define R_IRQ_READ1__ser2_data__WIDTH 1 | ||
| 4378 | #define R_IRQ_READ1__ser2_data__active 1 | ||
| 4379 | #define R_IRQ_READ1__ser2_data__inactive 0 | ||
| 4380 | #define R_IRQ_READ1__ser1_ready__BITNR 11 | ||
| 4381 | #define R_IRQ_READ1__ser1_ready__WIDTH 1 | ||
| 4382 | #define R_IRQ_READ1__ser1_ready__active 1 | ||
| 4383 | #define R_IRQ_READ1__ser1_ready__inactive 0 | ||
| 4384 | #define R_IRQ_READ1__ser1_data__BITNR 10 | ||
| 4385 | #define R_IRQ_READ1__ser1_data__WIDTH 1 | ||
| 4386 | #define R_IRQ_READ1__ser1_data__active 1 | ||
| 4387 | #define R_IRQ_READ1__ser1_data__inactive 0 | ||
| 4388 | #define R_IRQ_READ1__ser0_ready__BITNR 9 | ||
| 4389 | #define R_IRQ_READ1__ser0_ready__WIDTH 1 | ||
| 4390 | #define R_IRQ_READ1__ser0_ready__active 1 | ||
| 4391 | #define R_IRQ_READ1__ser0_ready__inactive 0 | ||
| 4392 | #define R_IRQ_READ1__ser0_data__BITNR 8 | ||
| 4393 | #define R_IRQ_READ1__ser0_data__WIDTH 1 | ||
| 4394 | #define R_IRQ_READ1__ser0_data__active 1 | ||
| 4395 | #define R_IRQ_READ1__ser0_data__inactive 0 | ||
| 4396 | #define R_IRQ_READ1__pa7__BITNR 7 | ||
| 4397 | #define R_IRQ_READ1__pa7__WIDTH 1 | ||
| 4398 | #define R_IRQ_READ1__pa7__active 1 | ||
| 4399 | #define R_IRQ_READ1__pa7__inactive 0 | ||
| 4400 | #define R_IRQ_READ1__pa6__BITNR 6 | ||
| 4401 | #define R_IRQ_READ1__pa6__WIDTH 1 | ||
| 4402 | #define R_IRQ_READ1__pa6__active 1 | ||
| 4403 | #define R_IRQ_READ1__pa6__inactive 0 | ||
| 4404 | #define R_IRQ_READ1__pa5__BITNR 5 | ||
| 4405 | #define R_IRQ_READ1__pa5__WIDTH 1 | ||
| 4406 | #define R_IRQ_READ1__pa5__active 1 | ||
| 4407 | #define R_IRQ_READ1__pa5__inactive 0 | ||
| 4408 | #define R_IRQ_READ1__pa4__BITNR 4 | ||
| 4409 | #define R_IRQ_READ1__pa4__WIDTH 1 | ||
| 4410 | #define R_IRQ_READ1__pa4__active 1 | ||
| 4411 | #define R_IRQ_READ1__pa4__inactive 0 | ||
| 4412 | #define R_IRQ_READ1__pa3__BITNR 3 | ||
| 4413 | #define R_IRQ_READ1__pa3__WIDTH 1 | ||
| 4414 | #define R_IRQ_READ1__pa3__active 1 | ||
| 4415 | #define R_IRQ_READ1__pa3__inactive 0 | ||
| 4416 | #define R_IRQ_READ1__pa2__BITNR 2 | ||
| 4417 | #define R_IRQ_READ1__pa2__WIDTH 1 | ||
| 4418 | #define R_IRQ_READ1__pa2__active 1 | ||
| 4419 | #define R_IRQ_READ1__pa2__inactive 0 | ||
| 4420 | #define R_IRQ_READ1__pa1__BITNR 1 | ||
| 4421 | #define R_IRQ_READ1__pa1__WIDTH 1 | ||
| 4422 | #define R_IRQ_READ1__pa1__active 1 | ||
| 4423 | #define R_IRQ_READ1__pa1__inactive 0 | ||
| 4424 | #define R_IRQ_READ1__pa0__BITNR 0 | ||
| 4425 | #define R_IRQ_READ1__pa0__WIDTH 1 | ||
| 4426 | #define R_IRQ_READ1__pa0__active 1 | ||
| 4427 | #define R_IRQ_READ1__pa0__inactive 0 | ||
| 4428 | |||
| 4429 | #define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) | ||
| 4430 | #define R_IRQ_MASK1_SET__sw_int7__BITNR 31 | ||
| 4431 | #define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 | ||
| 4432 | #define R_IRQ_MASK1_SET__sw_int7__set 1 | ||
| 4433 | #define R_IRQ_MASK1_SET__sw_int7__nop 0 | ||
| 4434 | #define R_IRQ_MASK1_SET__sw_int6__BITNR 30 | ||
| 4435 | #define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 | ||
| 4436 | #define R_IRQ_MASK1_SET__sw_int6__set 1 | ||
| 4437 | #define R_IRQ_MASK1_SET__sw_int6__nop 0 | ||
| 4438 | #define R_IRQ_MASK1_SET__sw_int5__BITNR 29 | ||
| 4439 | #define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 | ||
| 4440 | #define R_IRQ_MASK1_SET__sw_int5__set 1 | ||
| 4441 | #define R_IRQ_MASK1_SET__sw_int5__nop 0 | ||
| 4442 | #define R_IRQ_MASK1_SET__sw_int4__BITNR 28 | ||
| 4443 | #define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 | ||
| 4444 | #define R_IRQ_MASK1_SET__sw_int4__set 1 | ||
| 4445 | #define R_IRQ_MASK1_SET__sw_int4__nop 0 | ||
| 4446 | #define R_IRQ_MASK1_SET__sw_int3__BITNR 27 | ||
| 4447 | #define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 | ||
| 4448 | #define R_IRQ_MASK1_SET__sw_int3__set 1 | ||
| 4449 | #define R_IRQ_MASK1_SET__sw_int3__nop 0 | ||
| 4450 | #define R_IRQ_MASK1_SET__sw_int2__BITNR 26 | ||
| 4451 | #define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 | ||
| 4452 | #define R_IRQ_MASK1_SET__sw_int2__set 1 | ||
| 4453 | #define R_IRQ_MASK1_SET__sw_int2__nop 0 | ||
| 4454 | #define R_IRQ_MASK1_SET__sw_int1__BITNR 25 | ||
| 4455 | #define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 | ||
| 4456 | #define R_IRQ_MASK1_SET__sw_int1__set 1 | ||
| 4457 | #define R_IRQ_MASK1_SET__sw_int1__nop 0 | ||
| 4458 | #define R_IRQ_MASK1_SET__sw_int0__BITNR 24 | ||
| 4459 | #define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 | ||
| 4460 | #define R_IRQ_MASK1_SET__sw_int0__set 1 | ||
| 4461 | #define R_IRQ_MASK1_SET__sw_int0__nop 0 | ||
| 4462 | #define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 | ||
| 4463 | #define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 | ||
| 4464 | #define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 | ||
| 4465 | #define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 | ||
| 4466 | #define R_IRQ_MASK1_SET__par1_peri__BITNR 18 | ||
| 4467 | #define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 | ||
| 4468 | #define R_IRQ_MASK1_SET__par1_peri__set 1 | ||
| 4469 | #define R_IRQ_MASK1_SET__par1_peri__nop 0 | ||
| 4470 | #define R_IRQ_MASK1_SET__par1_data__BITNR 17 | ||
| 4471 | #define R_IRQ_MASK1_SET__par1_data__WIDTH 1 | ||
| 4472 | #define R_IRQ_MASK1_SET__par1_data__set 1 | ||
| 4473 | #define R_IRQ_MASK1_SET__par1_data__nop 0 | ||
| 4474 | #define R_IRQ_MASK1_SET__par1_ready__BITNR 16 | ||
| 4475 | #define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 | ||
| 4476 | #define R_IRQ_MASK1_SET__par1_ready__set 1 | ||
| 4477 | #define R_IRQ_MASK1_SET__par1_ready__nop 0 | ||
| 4478 | #define R_IRQ_MASK1_SET__scsi1__BITNR 16 | ||
| 4479 | #define R_IRQ_MASK1_SET__scsi1__WIDTH 1 | ||
| 4480 | #define R_IRQ_MASK1_SET__scsi1__set 1 | ||
| 4481 | #define R_IRQ_MASK1_SET__scsi1__nop 0 | ||
| 4482 | #define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 | ||
| 4483 | #define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 | ||
| 4484 | #define R_IRQ_MASK1_SET__ser3_ready__set 1 | ||
| 4485 | #define R_IRQ_MASK1_SET__ser3_ready__nop 0 | ||
| 4486 | #define R_IRQ_MASK1_SET__ser3_data__BITNR 14 | ||
| 4487 | #define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 | ||
| 4488 | #define R_IRQ_MASK1_SET__ser3_data__set 1 | ||
| 4489 | #define R_IRQ_MASK1_SET__ser3_data__nop 0 | ||
| 4490 | #define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 | ||
| 4491 | #define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 | ||
| 4492 | #define R_IRQ_MASK1_SET__ser2_ready__set 1 | ||
| 4493 | #define R_IRQ_MASK1_SET__ser2_ready__nop 0 | ||
| 4494 | #define R_IRQ_MASK1_SET__ser2_data__BITNR 12 | ||
| 4495 | #define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 | ||
| 4496 | #define R_IRQ_MASK1_SET__ser2_data__set 1 | ||
| 4497 | #define R_IRQ_MASK1_SET__ser2_data__nop 0 | ||
| 4498 | #define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 | ||
| 4499 | #define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 | ||
| 4500 | #define R_IRQ_MASK1_SET__ser1_ready__set 1 | ||
| 4501 | #define R_IRQ_MASK1_SET__ser1_ready__nop 0 | ||
| 4502 | #define R_IRQ_MASK1_SET__ser1_data__BITNR 10 | ||
| 4503 | #define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 | ||
| 4504 | #define R_IRQ_MASK1_SET__ser1_data__set 1 | ||
| 4505 | #define R_IRQ_MASK1_SET__ser1_data__nop 0 | ||
| 4506 | #define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 | ||
| 4507 | #define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 | ||
| 4508 | #define R_IRQ_MASK1_SET__ser0_ready__set 1 | ||
| 4509 | #define R_IRQ_MASK1_SET__ser0_ready__nop 0 | ||
| 4510 | #define R_IRQ_MASK1_SET__ser0_data__BITNR 8 | ||
| 4511 | #define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 | ||
| 4512 | #define R_IRQ_MASK1_SET__ser0_data__set 1 | ||
| 4513 | #define R_IRQ_MASK1_SET__ser0_data__nop 0 | ||
| 4514 | #define R_IRQ_MASK1_SET__pa7__BITNR 7 | ||
| 4515 | #define R_IRQ_MASK1_SET__pa7__WIDTH 1 | ||
| 4516 | #define R_IRQ_MASK1_SET__pa7__set 1 | ||
| 4517 | #define R_IRQ_MASK1_SET__pa7__nop 0 | ||
| 4518 | #define R_IRQ_MASK1_SET__pa6__BITNR 6 | ||
| 4519 | #define R_IRQ_MASK1_SET__pa6__WIDTH 1 | ||
| 4520 | #define R_IRQ_MASK1_SET__pa6__set 1 | ||
| 4521 | #define R_IRQ_MASK1_SET__pa6__nop 0 | ||
| 4522 | #define R_IRQ_MASK1_SET__pa5__BITNR 5 | ||
| 4523 | #define R_IRQ_MASK1_SET__pa5__WIDTH 1 | ||
| 4524 | #define R_IRQ_MASK1_SET__pa5__set 1 | ||
| 4525 | #define R_IRQ_MASK1_SET__pa5__nop 0 | ||
| 4526 | #define R_IRQ_MASK1_SET__pa4__BITNR 4 | ||
| 4527 | #define R_IRQ_MASK1_SET__pa4__WIDTH 1 | ||
| 4528 | #define R_IRQ_MASK1_SET__pa4__set 1 | ||
| 4529 | #define R_IRQ_MASK1_SET__pa4__nop 0 | ||
| 4530 | #define R_IRQ_MASK1_SET__pa3__BITNR 3 | ||
| 4531 | #define R_IRQ_MASK1_SET__pa3__WIDTH 1 | ||
| 4532 | #define R_IRQ_MASK1_SET__pa3__set 1 | ||
| 4533 | #define R_IRQ_MASK1_SET__pa3__nop 0 | ||
| 4534 | #define R_IRQ_MASK1_SET__pa2__BITNR 2 | ||
| 4535 | #define R_IRQ_MASK1_SET__pa2__WIDTH 1 | ||
| 4536 | #define R_IRQ_MASK1_SET__pa2__set 1 | ||
| 4537 | #define R_IRQ_MASK1_SET__pa2__nop 0 | ||
| 4538 | #define R_IRQ_MASK1_SET__pa1__BITNR 1 | ||
| 4539 | #define R_IRQ_MASK1_SET__pa1__WIDTH 1 | ||
| 4540 | #define R_IRQ_MASK1_SET__pa1__set 1 | ||
| 4541 | #define R_IRQ_MASK1_SET__pa1__nop 0 | ||
| 4542 | #define R_IRQ_MASK1_SET__pa0__BITNR 0 | ||
| 4543 | #define R_IRQ_MASK1_SET__pa0__WIDTH 1 | ||
| 4544 | #define R_IRQ_MASK1_SET__pa0__set 1 | ||
| 4545 | #define R_IRQ_MASK1_SET__pa0__nop 0 | ||
| 4546 | |||
| 4547 | #define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) | ||
| 4548 | #define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 | ||
| 4549 | #define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 | ||
| 4550 | #define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 | ||
| 4551 | #define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 | ||
| 4552 | #define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 | ||
| 4553 | #define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 | ||
| 4554 | #define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 | ||
| 4555 | #define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 | ||
| 4556 | #define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 | ||
| 4557 | #define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 | ||
| 4558 | #define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 | ||
| 4559 | #define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 | ||
| 4560 | #define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 | ||
| 4561 | #define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 | ||
| 4562 | #define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 | ||
| 4563 | #define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 | ||
| 4564 | #define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 | ||
| 4565 | #define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 | ||
| 4566 | #define R_IRQ_MASK2_RD__dma9_eop__active 1 | ||
| 4567 | #define R_IRQ_MASK2_RD__dma9_eop__inactive 0 | ||
| 4568 | #define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 | ||
| 4569 | #define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 | ||
| 4570 | #define R_IRQ_MASK2_RD__dma9_descr__active 1 | ||
| 4571 | #define R_IRQ_MASK2_RD__dma9_descr__inactive 0 | ||
| 4572 | #define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 | ||
| 4573 | #define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 | ||
| 4574 | #define R_IRQ_MASK2_RD__dma8_eop__active 1 | ||
| 4575 | #define R_IRQ_MASK2_RD__dma8_eop__inactive 0 | ||
| 4576 | #define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 | ||
| 4577 | #define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 | ||
| 4578 | #define R_IRQ_MASK2_RD__dma8_descr__active 1 | ||
| 4579 | #define R_IRQ_MASK2_RD__dma8_descr__inactive 0 | ||
| 4580 | #define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 | ||
| 4581 | #define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 | ||
| 4582 | #define R_IRQ_MASK2_RD__dma7_eop__active 1 | ||
| 4583 | #define R_IRQ_MASK2_RD__dma7_eop__inactive 0 | ||
| 4584 | #define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 | ||
| 4585 | #define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 | ||
| 4586 | #define R_IRQ_MASK2_RD__dma7_descr__active 1 | ||
| 4587 | #define R_IRQ_MASK2_RD__dma7_descr__inactive 0 | ||
| 4588 | #define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 | ||
| 4589 | #define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 | ||
| 4590 | #define R_IRQ_MASK2_RD__dma6_eop__active 1 | ||
| 4591 | #define R_IRQ_MASK2_RD__dma6_eop__inactive 0 | ||
| 4592 | #define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 | ||
| 4593 | #define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 | ||
| 4594 | #define R_IRQ_MASK2_RD__dma6_descr__active 1 | ||
| 4595 | #define R_IRQ_MASK2_RD__dma6_descr__inactive 0 | ||
| 4596 | #define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 | ||
| 4597 | #define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 | ||
| 4598 | #define R_IRQ_MASK2_RD__dma5_eop__active 1 | ||
| 4599 | #define R_IRQ_MASK2_RD__dma5_eop__inactive 0 | ||
| 4600 | #define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 | ||
| 4601 | #define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 | ||
| 4602 | #define R_IRQ_MASK2_RD__dma5_descr__active 1 | ||
| 4603 | #define R_IRQ_MASK2_RD__dma5_descr__inactive 0 | ||
| 4604 | #define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 | ||
| 4605 | #define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 | ||
| 4606 | #define R_IRQ_MASK2_RD__dma4_eop__active 1 | ||
| 4607 | #define R_IRQ_MASK2_RD__dma4_eop__inactive 0 | ||
| 4608 | #define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 | ||
| 4609 | #define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 | ||
| 4610 | #define R_IRQ_MASK2_RD__dma4_descr__active 1 | ||
| 4611 | #define R_IRQ_MASK2_RD__dma4_descr__inactive 0 | ||
| 4612 | #define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 | ||
| 4613 | #define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 | ||
| 4614 | #define R_IRQ_MASK2_RD__dma3_eop__active 1 | ||
| 4615 | #define R_IRQ_MASK2_RD__dma3_eop__inactive 0 | ||
| 4616 | #define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 | ||
| 4617 | #define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 | ||
| 4618 | #define R_IRQ_MASK2_RD__dma3_descr__active 1 | ||
| 4619 | #define R_IRQ_MASK2_RD__dma3_descr__inactive 0 | ||
| 4620 | #define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 | ||
| 4621 | #define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 | ||
| 4622 | #define R_IRQ_MASK2_RD__dma2_eop__active 1 | ||
| 4623 | #define R_IRQ_MASK2_RD__dma2_eop__inactive 0 | ||
| 4624 | #define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 | ||
| 4625 | #define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 | ||
| 4626 | #define R_IRQ_MASK2_RD__dma2_descr__active 1 | ||
| 4627 | #define R_IRQ_MASK2_RD__dma2_descr__inactive 0 | ||
| 4628 | #define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 | ||
| 4629 | #define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 | ||
| 4630 | #define R_IRQ_MASK2_RD__dma1_eop__active 1 | ||
| 4631 | #define R_IRQ_MASK2_RD__dma1_eop__inactive 0 | ||
| 4632 | #define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 | ||
| 4633 | #define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 | ||
| 4634 | #define R_IRQ_MASK2_RD__dma1_descr__active 1 | ||
| 4635 | #define R_IRQ_MASK2_RD__dma1_descr__inactive 0 | ||
| 4636 | #define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 | ||
| 4637 | #define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 | ||
| 4638 | #define R_IRQ_MASK2_RD__dma0_eop__active 1 | ||
| 4639 | #define R_IRQ_MASK2_RD__dma0_eop__inactive 0 | ||
| 4640 | #define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 | ||
| 4641 | #define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 | ||
| 4642 | #define R_IRQ_MASK2_RD__dma0_descr__active 1 | ||
| 4643 | #define R_IRQ_MASK2_RD__dma0_descr__inactive 0 | ||
| 4644 | |||
| 4645 | #define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) | ||
| 4646 | #define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 | ||
| 4647 | #define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 | ||
| 4648 | #define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 | ||
| 4649 | #define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 | ||
| 4650 | #define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 | ||
| 4651 | #define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 | ||
| 4652 | #define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 | ||
| 4653 | #define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 | ||
| 4654 | #define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 | ||
| 4655 | #define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 | ||
| 4656 | #define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 | ||
| 4657 | #define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 | ||
| 4658 | #define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 | ||
| 4659 | #define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 | ||
| 4660 | #define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 | ||
| 4661 | #define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 | ||
| 4662 | #define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 | ||
| 4663 | #define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 | ||
| 4664 | #define R_IRQ_MASK2_CLR__dma9_eop__clr 1 | ||
| 4665 | #define R_IRQ_MASK2_CLR__dma9_eop__nop 0 | ||
| 4666 | #define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 | ||
| 4667 | #define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 | ||
| 4668 | #define R_IRQ_MASK2_CLR__dma9_descr__clr 1 | ||
| 4669 | #define R_IRQ_MASK2_CLR__dma9_descr__nop 0 | ||
| 4670 | #define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 | ||
| 4671 | #define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 | ||
| 4672 | #define R_IRQ_MASK2_CLR__dma8_eop__clr 1 | ||
| 4673 | #define R_IRQ_MASK2_CLR__dma8_eop__nop 0 | ||
| 4674 | #define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 | ||
| 4675 | #define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 | ||
| 4676 | #define R_IRQ_MASK2_CLR__dma8_descr__clr 1 | ||
| 4677 | #define R_IRQ_MASK2_CLR__dma8_descr__nop 0 | ||
| 4678 | #define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 | ||
| 4679 | #define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 | ||
| 4680 | #define R_IRQ_MASK2_CLR__dma7_eop__clr 1 | ||
| 4681 | #define R_IRQ_MASK2_CLR__dma7_eop__nop 0 | ||
| 4682 | #define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 | ||
| 4683 | #define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 | ||
| 4684 | #define R_IRQ_MASK2_CLR__dma7_descr__clr 1 | ||
| 4685 | #define R_IRQ_MASK2_CLR__dma7_descr__nop 0 | ||
| 4686 | #define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 | ||
| 4687 | #define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 | ||
| 4688 | #define R_IRQ_MASK2_CLR__dma6_eop__clr 1 | ||
| 4689 | #define R_IRQ_MASK2_CLR__dma6_eop__nop 0 | ||
| 4690 | #define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 | ||
| 4691 | #define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 | ||
| 4692 | #define R_IRQ_MASK2_CLR__dma6_descr__clr 1 | ||
| 4693 | #define R_IRQ_MASK2_CLR__dma6_descr__nop 0 | ||
| 4694 | #define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 | ||
| 4695 | #define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 | ||
| 4696 | #define R_IRQ_MASK2_CLR__dma5_eop__clr 1 | ||
| 4697 | #define R_IRQ_MASK2_CLR__dma5_eop__nop 0 | ||
| 4698 | #define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 | ||
| 4699 | #define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 | ||
| 4700 | #define R_IRQ_MASK2_CLR__dma5_descr__clr 1 | ||
| 4701 | #define R_IRQ_MASK2_CLR__dma5_descr__nop 0 | ||
| 4702 | #define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 | ||
| 4703 | #define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 | ||
| 4704 | #define R_IRQ_MASK2_CLR__dma4_eop__clr 1 | ||
| 4705 | #define R_IRQ_MASK2_CLR__dma4_eop__nop 0 | ||
| 4706 | #define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 | ||
| 4707 | #define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 | ||
| 4708 | #define R_IRQ_MASK2_CLR__dma4_descr__clr 1 | ||
| 4709 | #define R_IRQ_MASK2_CLR__dma4_descr__nop 0 | ||
| 4710 | #define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 | ||
| 4711 | #define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 | ||
| 4712 | #define R_IRQ_MASK2_CLR__dma3_eop__clr 1 | ||
| 4713 | #define R_IRQ_MASK2_CLR__dma3_eop__nop 0 | ||
| 4714 | #define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 | ||
| 4715 | #define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 | ||
| 4716 | #define R_IRQ_MASK2_CLR__dma3_descr__clr 1 | ||
| 4717 | #define R_IRQ_MASK2_CLR__dma3_descr__nop 0 | ||
| 4718 | #define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 | ||
| 4719 | #define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 | ||
| 4720 | #define R_IRQ_MASK2_CLR__dma2_eop__clr 1 | ||
| 4721 | #define R_IRQ_MASK2_CLR__dma2_eop__nop 0 | ||
| 4722 | #define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 | ||
| 4723 | #define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 | ||
| 4724 | #define R_IRQ_MASK2_CLR__dma2_descr__clr 1 | ||
| 4725 | #define R_IRQ_MASK2_CLR__dma2_descr__nop 0 | ||
| 4726 | #define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 | ||
| 4727 | #define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 | ||
| 4728 | #define R_IRQ_MASK2_CLR__dma1_eop__clr 1 | ||
| 4729 | #define R_IRQ_MASK2_CLR__dma1_eop__nop 0 | ||
| 4730 | #define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 | ||
| 4731 | #define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 | ||
| 4732 | #define R_IRQ_MASK2_CLR__dma1_descr__clr 1 | ||
| 4733 | #define R_IRQ_MASK2_CLR__dma1_descr__nop 0 | ||
| 4734 | #define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 | ||
| 4735 | #define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 | ||
| 4736 | #define R_IRQ_MASK2_CLR__dma0_eop__clr 1 | ||
| 4737 | #define R_IRQ_MASK2_CLR__dma0_eop__nop 0 | ||
| 4738 | #define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 | ||
| 4739 | #define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 | ||
| 4740 | #define R_IRQ_MASK2_CLR__dma0_descr__clr 1 | ||
| 4741 | #define R_IRQ_MASK2_CLR__dma0_descr__nop 0 | ||
| 4742 | |||
| 4743 | #define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) | ||
| 4744 | #define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 | ||
| 4745 | #define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 | ||
| 4746 | #define R_IRQ_READ2__dma8_sub3_descr__active 1 | ||
| 4747 | #define R_IRQ_READ2__dma8_sub3_descr__inactive 0 | ||
| 4748 | #define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 | ||
| 4749 | #define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 | ||
| 4750 | #define R_IRQ_READ2__dma8_sub2_descr__active 1 | ||
| 4751 | #define R_IRQ_READ2__dma8_sub2_descr__inactive 0 | ||
| 4752 | #define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 | ||
| 4753 | #define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 | ||
| 4754 | #define R_IRQ_READ2__dma8_sub1_descr__active 1 | ||
| 4755 | #define R_IRQ_READ2__dma8_sub1_descr__inactive 0 | ||
| 4756 | #define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 | ||
| 4757 | #define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 | ||
| 4758 | #define R_IRQ_READ2__dma8_sub0_descr__active 1 | ||
| 4759 | #define R_IRQ_READ2__dma8_sub0_descr__inactive 0 | ||
| 4760 | #define R_IRQ_READ2__dma9_eop__BITNR 19 | ||
| 4761 | #define R_IRQ_READ2__dma9_eop__WIDTH 1 | ||
| 4762 | #define R_IRQ_READ2__dma9_eop__active 1 | ||
| 4763 | #define R_IRQ_READ2__dma9_eop__inactive 0 | ||
| 4764 | #define R_IRQ_READ2__dma9_descr__BITNR 18 | ||
| 4765 | #define R_IRQ_READ2__dma9_descr__WIDTH 1 | ||
| 4766 | #define R_IRQ_READ2__dma9_descr__active 1 | ||
| 4767 | #define R_IRQ_READ2__dma9_descr__inactive 0 | ||
| 4768 | #define R_IRQ_READ2__dma8_eop__BITNR 17 | ||
| 4769 | #define R_IRQ_READ2__dma8_eop__WIDTH 1 | ||
| 4770 | #define R_IRQ_READ2__dma8_eop__active 1 | ||
| 4771 | #define R_IRQ_READ2__dma8_eop__inactive 0 | ||
| 4772 | #define R_IRQ_READ2__dma8_descr__BITNR 16 | ||
| 4773 | #define R_IRQ_READ2__dma8_descr__WIDTH 1 | ||
| 4774 | #define R_IRQ_READ2__dma8_descr__active 1 | ||
| 4775 | #define R_IRQ_READ2__dma8_descr__inactive 0 | ||
| 4776 | #define R_IRQ_READ2__dma7_eop__BITNR 15 | ||
| 4777 | #define R_IRQ_READ2__dma7_eop__WIDTH 1 | ||
| 4778 | #define R_IRQ_READ2__dma7_eop__active 1 | ||
| 4779 | #define R_IRQ_READ2__dma7_eop__inactive 0 | ||
| 4780 | #define R_IRQ_READ2__dma7_descr__BITNR 14 | ||
| 4781 | #define R_IRQ_READ2__dma7_descr__WIDTH 1 | ||
| 4782 | #define R_IRQ_READ2__dma7_descr__active 1 | ||
| 4783 | #define R_IRQ_READ2__dma7_descr__inactive 0 | ||
| 4784 | #define R_IRQ_READ2__dma6_eop__BITNR 13 | ||
| 4785 | #define R_IRQ_READ2__dma6_eop__WIDTH 1 | ||
| 4786 | #define R_IRQ_READ2__dma6_eop__active 1 | ||
| 4787 | #define R_IRQ_READ2__dma6_eop__inactive 0 | ||
| 4788 | #define R_IRQ_READ2__dma6_descr__BITNR 12 | ||
| 4789 | #define R_IRQ_READ2__dma6_descr__WIDTH 1 | ||
| 4790 | #define R_IRQ_READ2__dma6_descr__active 1 | ||
| 4791 | #define R_IRQ_READ2__dma6_descr__inactive 0 | ||
| 4792 | #define R_IRQ_READ2__dma5_eop__BITNR 11 | ||
| 4793 | #define R_IRQ_READ2__dma5_eop__WIDTH 1 | ||
| 4794 | #define R_IRQ_READ2__dma5_eop__active 1 | ||
| 4795 | #define R_IRQ_READ2__dma5_eop__inactive 0 | ||
| 4796 | #define R_IRQ_READ2__dma5_descr__BITNR 10 | ||
| 4797 | #define R_IRQ_READ2__dma5_descr__WIDTH 1 | ||
| 4798 | #define R_IRQ_READ2__dma5_descr__active 1 | ||
| 4799 | #define R_IRQ_READ2__dma5_descr__inactive 0 | ||
| 4800 | #define R_IRQ_READ2__dma4_eop__BITNR 9 | ||
| 4801 | #define R_IRQ_READ2__dma4_eop__WIDTH 1 | ||
| 4802 | #define R_IRQ_READ2__dma4_eop__active 1 | ||
| 4803 | #define R_IRQ_READ2__dma4_eop__inactive 0 | ||
| 4804 | #define R_IRQ_READ2__dma4_descr__BITNR 8 | ||
| 4805 | #define R_IRQ_READ2__dma4_descr__WIDTH 1 | ||
| 4806 | #define R_IRQ_READ2__dma4_descr__active 1 | ||
| 4807 | #define R_IRQ_READ2__dma4_descr__inactive 0 | ||
| 4808 | #define R_IRQ_READ2__dma3_eop__BITNR 7 | ||
| 4809 | #define R_IRQ_READ2__dma3_eop__WIDTH 1 | ||
| 4810 | #define R_IRQ_READ2__dma3_eop__active 1 | ||
| 4811 | #define R_IRQ_READ2__dma3_eop__inactive 0 | ||
| 4812 | #define R_IRQ_READ2__dma3_descr__BITNR 6 | ||
| 4813 | #define R_IRQ_READ2__dma3_descr__WIDTH 1 | ||
| 4814 | #define R_IRQ_READ2__dma3_descr__active 1 | ||
| 4815 | #define R_IRQ_READ2__dma3_descr__inactive 0 | ||
| 4816 | #define R_IRQ_READ2__dma2_eop__BITNR 5 | ||
| 4817 | #define R_IRQ_READ2__dma2_eop__WIDTH 1 | ||
| 4818 | #define R_IRQ_READ2__dma2_eop__active 1 | ||
| 4819 | #define R_IRQ_READ2__dma2_eop__inactive 0 | ||
| 4820 | #define R_IRQ_READ2__dma2_descr__BITNR 4 | ||
| 4821 | #define R_IRQ_READ2__dma2_descr__WIDTH 1 | ||
| 4822 | #define R_IRQ_READ2__dma2_descr__active 1 | ||
| 4823 | #define R_IRQ_READ2__dma2_descr__inactive 0 | ||
| 4824 | #define R_IRQ_READ2__dma1_eop__BITNR 3 | ||
| 4825 | #define R_IRQ_READ2__dma1_eop__WIDTH 1 | ||
| 4826 | #define R_IRQ_READ2__dma1_eop__active 1 | ||
| 4827 | #define R_IRQ_READ2__dma1_eop__inactive 0 | ||
| 4828 | #define R_IRQ_READ2__dma1_descr__BITNR 2 | ||
| 4829 | #define R_IRQ_READ2__dma1_descr__WIDTH 1 | ||
| 4830 | #define R_IRQ_READ2__dma1_descr__active 1 | ||
| 4831 | #define R_IRQ_READ2__dma1_descr__inactive 0 | ||
| 4832 | #define R_IRQ_READ2__dma0_eop__BITNR 1 | ||
| 4833 | #define R_IRQ_READ2__dma0_eop__WIDTH 1 | ||
| 4834 | #define R_IRQ_READ2__dma0_eop__active 1 | ||
| 4835 | #define R_IRQ_READ2__dma0_eop__inactive 0 | ||
| 4836 | #define R_IRQ_READ2__dma0_descr__BITNR 0 | ||
| 4837 | #define R_IRQ_READ2__dma0_descr__WIDTH 1 | ||
| 4838 | #define R_IRQ_READ2__dma0_descr__active 1 | ||
| 4839 | #define R_IRQ_READ2__dma0_descr__inactive 0 | ||
| 4840 | |||
| 4841 | #define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) | ||
| 4842 | #define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 | ||
| 4843 | #define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 | ||
| 4844 | #define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 | ||
| 4845 | #define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 | ||
| 4846 | #define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 | ||
| 4847 | #define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 | ||
| 4848 | #define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 | ||
| 4849 | #define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 | ||
| 4850 | #define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 | ||
| 4851 | #define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 | ||
| 4852 | #define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 | ||
| 4853 | #define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 | ||
| 4854 | #define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 | ||
| 4855 | #define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 | ||
| 4856 | #define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 | ||
| 4857 | #define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 | ||
| 4858 | #define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 | ||
| 4859 | #define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 | ||
| 4860 | #define R_IRQ_MASK2_SET__dma9_eop__set 1 | ||
| 4861 | #define R_IRQ_MASK2_SET__dma9_eop__nop 0 | ||
| 4862 | #define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 | ||
| 4863 | #define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 | ||
| 4864 | #define R_IRQ_MASK2_SET__dma9_descr__set 1 | ||
| 4865 | #define R_IRQ_MASK2_SET__dma9_descr__nop 0 | ||
| 4866 | #define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 | ||
| 4867 | #define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 | ||
| 4868 | #define R_IRQ_MASK2_SET__dma8_eop__set 1 | ||
| 4869 | #define R_IRQ_MASK2_SET__dma8_eop__nop 0 | ||
| 4870 | #define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 | ||
| 4871 | #define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 | ||
| 4872 | #define R_IRQ_MASK2_SET__dma8_descr__set 1 | ||
| 4873 | #define R_IRQ_MASK2_SET__dma8_descr__nop 0 | ||
| 4874 | #define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 | ||
| 4875 | #define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 | ||
| 4876 | #define R_IRQ_MASK2_SET__dma7_eop__set 1 | ||
| 4877 | #define R_IRQ_MASK2_SET__dma7_eop__nop 0 | ||
| 4878 | #define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 | ||
| 4879 | #define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 | ||
| 4880 | #define R_IRQ_MASK2_SET__dma7_descr__set 1 | ||
| 4881 | #define R_IRQ_MASK2_SET__dma7_descr__nop 0 | ||
| 4882 | #define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 | ||
| 4883 | #define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 | ||
| 4884 | #define R_IRQ_MASK2_SET__dma6_eop__set 1 | ||
| 4885 | #define R_IRQ_MASK2_SET__dma6_eop__nop 0 | ||
| 4886 | #define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 | ||
| 4887 | #define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 | ||
| 4888 | #define R_IRQ_MASK2_SET__dma6_descr__set 1 | ||
| 4889 | #define R_IRQ_MASK2_SET__dma6_descr__nop 0 | ||
| 4890 | #define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 | ||
| 4891 | #define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 | ||
| 4892 | #define R_IRQ_MASK2_SET__dma5_eop__set 1 | ||
| 4893 | #define R_IRQ_MASK2_SET__dma5_eop__nop 0 | ||
| 4894 | #define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 | ||
| 4895 | #define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 | ||
| 4896 | #define R_IRQ_MASK2_SET__dma5_descr__set 1 | ||
| 4897 | #define R_IRQ_MASK2_SET__dma5_descr__nop 0 | ||
| 4898 | #define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 | ||
| 4899 | #define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 | ||
| 4900 | #define R_IRQ_MASK2_SET__dma4_eop__set 1 | ||
| 4901 | #define R_IRQ_MASK2_SET__dma4_eop__nop 0 | ||
| 4902 | #define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 | ||
| 4903 | #define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 | ||
| 4904 | #define R_IRQ_MASK2_SET__dma4_descr__set 1 | ||
| 4905 | #define R_IRQ_MASK2_SET__dma4_descr__nop 0 | ||
| 4906 | #define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 | ||
| 4907 | #define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 | ||
| 4908 | #define R_IRQ_MASK2_SET__dma3_eop__set 1 | ||
| 4909 | #define R_IRQ_MASK2_SET__dma3_eop__nop 0 | ||
| 4910 | #define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 | ||
| 4911 | #define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 | ||
| 4912 | #define R_IRQ_MASK2_SET__dma3_descr__set 1 | ||
| 4913 | #define R_IRQ_MASK2_SET__dma3_descr__nop 0 | ||
| 4914 | #define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 | ||
| 4915 | #define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 | ||
| 4916 | #define R_IRQ_MASK2_SET__dma2_eop__set 1 | ||
| 4917 | #define R_IRQ_MASK2_SET__dma2_eop__nop 0 | ||
| 4918 | #define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 | ||
| 4919 | #define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 | ||
| 4920 | #define R_IRQ_MASK2_SET__dma2_descr__set 1 | ||
| 4921 | #define R_IRQ_MASK2_SET__dma2_descr__nop 0 | ||
| 4922 | #define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 | ||
| 4923 | #define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 | ||
| 4924 | #define R_IRQ_MASK2_SET__dma1_eop__set 1 | ||
| 4925 | #define R_IRQ_MASK2_SET__dma1_eop__nop 0 | ||
| 4926 | #define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 | ||
| 4927 | #define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 | ||
| 4928 | #define R_IRQ_MASK2_SET__dma1_descr__set 1 | ||
| 4929 | #define R_IRQ_MASK2_SET__dma1_descr__nop 0 | ||
| 4930 | #define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 | ||
| 4931 | #define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 | ||
| 4932 | #define R_IRQ_MASK2_SET__dma0_eop__set 1 | ||
| 4933 | #define R_IRQ_MASK2_SET__dma0_eop__nop 0 | ||
| 4934 | #define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 | ||
| 4935 | #define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 | ||
| 4936 | #define R_IRQ_MASK2_SET__dma0_descr__set 1 | ||
| 4937 | #define R_IRQ_MASK2_SET__dma0_descr__nop 0 | ||
| 4938 | |||
| 4939 | #define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) | ||
| 4940 | #define R_VECT_MASK_RD__usb__BITNR 31 | ||
| 4941 | #define R_VECT_MASK_RD__usb__WIDTH 1 | ||
| 4942 | #define R_VECT_MASK_RD__usb__active 1 | ||
| 4943 | #define R_VECT_MASK_RD__usb__inactive 0 | ||
| 4944 | #define R_VECT_MASK_RD__dma9__BITNR 25 | ||
| 4945 | #define R_VECT_MASK_RD__dma9__WIDTH 1 | ||
| 4946 | #define R_VECT_MASK_RD__dma9__active 1 | ||
| 4947 | #define R_VECT_MASK_RD__dma9__inactive 0 | ||
| 4948 | #define R_VECT_MASK_RD__dma8__BITNR 24 | ||
| 4949 | #define R_VECT_MASK_RD__dma8__WIDTH 1 | ||
| 4950 | #define R_VECT_MASK_RD__dma8__active 1 | ||
| 4951 | #define R_VECT_MASK_RD__dma8__inactive 0 | ||
| 4952 | #define R_VECT_MASK_RD__dma7__BITNR 23 | ||
| 4953 | #define R_VECT_MASK_RD__dma7__WIDTH 1 | ||
| 4954 | #define R_VECT_MASK_RD__dma7__active 1 | ||
| 4955 | #define R_VECT_MASK_RD__dma7__inactive 0 | ||
| 4956 | #define R_VECT_MASK_RD__dma6__BITNR 22 | ||
| 4957 | #define R_VECT_MASK_RD__dma6__WIDTH 1 | ||
| 4958 | #define R_VECT_MASK_RD__dma6__active 1 | ||
| 4959 | #define R_VECT_MASK_RD__dma6__inactive 0 | ||
| 4960 | #define R_VECT_MASK_RD__dma5__BITNR 21 | ||
| 4961 | #define R_VECT_MASK_RD__dma5__WIDTH 1 | ||
| 4962 | #define R_VECT_MASK_RD__dma5__active 1 | ||
| 4963 | #define R_VECT_MASK_RD__dma5__inactive 0 | ||
| 4964 | #define R_VECT_MASK_RD__dma4__BITNR 20 | ||
| 4965 | #define R_VECT_MASK_RD__dma4__WIDTH 1 | ||
| 4966 | #define R_VECT_MASK_RD__dma4__active 1 | ||
| 4967 | #define R_VECT_MASK_RD__dma4__inactive 0 | ||
| 4968 | #define R_VECT_MASK_RD__dma3__BITNR 19 | ||
| 4969 | #define R_VECT_MASK_RD__dma3__WIDTH 1 | ||
| 4970 | #define R_VECT_MASK_RD__dma3__active 1 | ||
| 4971 | #define R_VECT_MASK_RD__dma3__inactive 0 | ||
| 4972 | #define R_VECT_MASK_RD__dma2__BITNR 18 | ||
| 4973 | #define R_VECT_MASK_RD__dma2__WIDTH 1 | ||
| 4974 | #define R_VECT_MASK_RD__dma2__active 1 | ||
| 4975 | #define R_VECT_MASK_RD__dma2__inactive 0 | ||
| 4976 | #define R_VECT_MASK_RD__dma1__BITNR 17 | ||
| 4977 | #define R_VECT_MASK_RD__dma1__WIDTH 1 | ||
| 4978 | #define R_VECT_MASK_RD__dma1__active 1 | ||
| 4979 | #define R_VECT_MASK_RD__dma1__inactive 0 | ||
| 4980 | #define R_VECT_MASK_RD__dma0__BITNR 16 | ||
| 4981 | #define R_VECT_MASK_RD__dma0__WIDTH 1 | ||
| 4982 | #define R_VECT_MASK_RD__dma0__active 1 | ||
| 4983 | #define R_VECT_MASK_RD__dma0__inactive 0 | ||
| 4984 | #define R_VECT_MASK_RD__ext_dma1__BITNR 13 | ||
| 4985 | #define R_VECT_MASK_RD__ext_dma1__WIDTH 1 | ||
| 4986 | #define R_VECT_MASK_RD__ext_dma1__active 1 | ||
| 4987 | #define R_VECT_MASK_RD__ext_dma1__inactive 0 | ||
| 4988 | #define R_VECT_MASK_RD__ext_dma0__BITNR 12 | ||
| 4989 | #define R_VECT_MASK_RD__ext_dma0__WIDTH 1 | ||
| 4990 | #define R_VECT_MASK_RD__ext_dma0__active 1 | ||
| 4991 | #define R_VECT_MASK_RD__ext_dma0__inactive 0 | ||
| 4992 | #define R_VECT_MASK_RD__pa__BITNR 11 | ||
| 4993 | #define R_VECT_MASK_RD__pa__WIDTH 1 | ||
| 4994 | #define R_VECT_MASK_RD__pa__active 1 | ||
| 4995 | #define R_VECT_MASK_RD__pa__inactive 0 | ||
| 4996 | #define R_VECT_MASK_RD__irq_intnr__BITNR 10 | ||
| 4997 | #define R_VECT_MASK_RD__irq_intnr__WIDTH 1 | ||
| 4998 | #define R_VECT_MASK_RD__irq_intnr__active 1 | ||
| 4999 | #define R_VECT_MASK_RD__irq_intnr__inactive 0 | ||
| 5000 | #define R_VECT_MASK_RD__sw__BITNR 9 | ||
| 5001 | #define R_VECT_MASK_RD__sw__WIDTH 1 | ||
| 5002 | #define R_VECT_MASK_RD__sw__active 1 | ||
| 5003 | #define R_VECT_MASK_RD__sw__inactive 0 | ||
| 5004 | #define R_VECT_MASK_RD__serial__BITNR 8 | ||
| 5005 | #define R_VECT_MASK_RD__serial__WIDTH 1 | ||
| 5006 | #define R_VECT_MASK_RD__serial__active 1 | ||
| 5007 | #define R_VECT_MASK_RD__serial__inactive 0 | ||
| 5008 | #define R_VECT_MASK_RD__snmp__BITNR 7 | ||
| 5009 | #define R_VECT_MASK_RD__snmp__WIDTH 1 | ||
| 5010 | #define R_VECT_MASK_RD__snmp__active 1 | ||
| 5011 | #define R_VECT_MASK_RD__snmp__inactive 0 | ||
| 5012 | #define R_VECT_MASK_RD__network__BITNR 6 | ||
| 5013 | #define R_VECT_MASK_RD__network__WIDTH 1 | ||
| 5014 | #define R_VECT_MASK_RD__network__active 1 | ||
| 5015 | #define R_VECT_MASK_RD__network__inactive 0 | ||
| 5016 | #define R_VECT_MASK_RD__scsi1__BITNR 5 | ||
| 5017 | #define R_VECT_MASK_RD__scsi1__WIDTH 1 | ||
| 5018 | #define R_VECT_MASK_RD__scsi1__active 1 | ||
| 5019 | #define R_VECT_MASK_RD__scsi1__inactive 0 | ||
| 5020 | #define R_VECT_MASK_RD__par1__BITNR 5 | ||
| 5021 | #define R_VECT_MASK_RD__par1__WIDTH 1 | ||
| 5022 | #define R_VECT_MASK_RD__par1__active 1 | ||
| 5023 | #define R_VECT_MASK_RD__par1__inactive 0 | ||
| 5024 | #define R_VECT_MASK_RD__scsi0__BITNR 4 | ||
| 5025 | #define R_VECT_MASK_RD__scsi0__WIDTH 1 | ||
| 5026 | #define R_VECT_MASK_RD__scsi0__active 1 | ||
| 5027 | #define R_VECT_MASK_RD__scsi0__inactive 0 | ||
| 5028 | #define R_VECT_MASK_RD__par0__BITNR 4 | ||
| 5029 | #define R_VECT_MASK_RD__par0__WIDTH 1 | ||
| 5030 | #define R_VECT_MASK_RD__par0__active 1 | ||
| 5031 | #define R_VECT_MASK_RD__par0__inactive 0 | ||
| 5032 | #define R_VECT_MASK_RD__ata__BITNR 4 | ||
| 5033 | #define R_VECT_MASK_RD__ata__WIDTH 1 | ||
| 5034 | #define R_VECT_MASK_RD__ata__active 1 | ||
| 5035 | #define R_VECT_MASK_RD__ata__inactive 0 | ||
| 5036 | #define R_VECT_MASK_RD__mio__BITNR 4 | ||
| 5037 | #define R_VECT_MASK_RD__mio__WIDTH 1 | ||
| 5038 | #define R_VECT_MASK_RD__mio__active 1 | ||
| 5039 | #define R_VECT_MASK_RD__mio__inactive 0 | ||
| 5040 | #define R_VECT_MASK_RD__timer1__BITNR 3 | ||
| 5041 | #define R_VECT_MASK_RD__timer1__WIDTH 1 | ||
| 5042 | #define R_VECT_MASK_RD__timer1__active 1 | ||
| 5043 | #define R_VECT_MASK_RD__timer1__inactive 0 | ||
| 5044 | #define R_VECT_MASK_RD__timer0__BITNR 2 | ||
| 5045 | #define R_VECT_MASK_RD__timer0__WIDTH 1 | ||
| 5046 | #define R_VECT_MASK_RD__timer0__active 1 | ||
| 5047 | #define R_VECT_MASK_RD__timer0__inactive 0 | ||
| 5048 | #define R_VECT_MASK_RD__nmi__BITNR 1 | ||
| 5049 | #define R_VECT_MASK_RD__nmi__WIDTH 1 | ||
| 5050 | #define R_VECT_MASK_RD__nmi__active 1 | ||
| 5051 | #define R_VECT_MASK_RD__nmi__inactive 0 | ||
| 5052 | #define R_VECT_MASK_RD__some__BITNR 0 | ||
| 5053 | #define R_VECT_MASK_RD__some__WIDTH 1 | ||
| 5054 | #define R_VECT_MASK_RD__some__active 1 | ||
| 5055 | #define R_VECT_MASK_RD__some__inactive 0 | ||
| 5056 | |||
| 5057 | #define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) | ||
| 5058 | #define R_VECT_MASK_CLR__usb__BITNR 31 | ||
| 5059 | #define R_VECT_MASK_CLR__usb__WIDTH 1 | ||
| 5060 | #define R_VECT_MASK_CLR__usb__clr 1 | ||
| 5061 | #define R_VECT_MASK_CLR__usb__nop 0 | ||
| 5062 | #define R_VECT_MASK_CLR__dma9__BITNR 25 | ||
| 5063 | #define R_VECT_MASK_CLR__dma9__WIDTH 1 | ||
| 5064 | #define R_VECT_MASK_CLR__dma9__clr 1 | ||
| 5065 | #define R_VECT_MASK_CLR__dma9__nop 0 | ||
| 5066 | #define R_VECT_MASK_CLR__dma8__BITNR 24 | ||
| 5067 | #define R_VECT_MASK_CLR__dma8__WIDTH 1 | ||
| 5068 | #define R_VECT_MASK_CLR__dma8__clr 1 | ||
| 5069 | #define R_VECT_MASK_CLR__dma8__nop 0 | ||
| 5070 | #define R_VECT_MASK_CLR__dma7__BITNR 23 | ||
| 5071 | #define R_VECT_MASK_CLR__dma7__WIDTH 1 | ||
| 5072 | #define R_VECT_MASK_CLR__dma7__clr 1 | ||
| 5073 | #define R_VECT_MASK_CLR__dma7__nop 0 | ||
| 5074 | #define R_VECT_MASK_CLR__dma6__BITNR 22 | ||
| 5075 | #define R_VECT_MASK_CLR__dma6__WIDTH 1 | ||
| 5076 | #define R_VECT_MASK_CLR__dma6__clr 1 | ||
| 5077 | #define R_VECT_MASK_CLR__dma6__nop 0 | ||
| 5078 | #define R_VECT_MASK_CLR__dma5__BITNR 21 | ||
| 5079 | #define R_VECT_MASK_CLR__dma5__WIDTH 1 | ||
| 5080 | #define R_VECT_MASK_CLR__dma5__clr 1 | ||
| 5081 | #define R_VECT_MASK_CLR__dma5__nop 0 | ||
| 5082 | #define R_VECT_MASK_CLR__dma4__BITNR 20 | ||
| 5083 | #define R_VECT_MASK_CLR__dma4__WIDTH 1 | ||
| 5084 | #define R_VECT_MASK_CLR__dma4__clr 1 | ||
| 5085 | #define R_VECT_MASK_CLR__dma4__nop 0 | ||
| 5086 | #define R_VECT_MASK_CLR__dma3__BITNR 19 | ||
| 5087 | #define R_VECT_MASK_CLR__dma3__WIDTH 1 | ||
| 5088 | #define R_VECT_MASK_CLR__dma3__clr 1 | ||
| 5089 | #define R_VECT_MASK_CLR__dma3__nop 0 | ||
| 5090 | #define R_VECT_MASK_CLR__dma2__BITNR 18 | ||
| 5091 | #define R_VECT_MASK_CLR__dma2__WIDTH 1 | ||
| 5092 | #define R_VECT_MASK_CLR__dma2__clr 1 | ||
| 5093 | #define R_VECT_MASK_CLR__dma2__nop 0 | ||
| 5094 | #define R_VECT_MASK_CLR__dma1__BITNR 17 | ||
| 5095 | #define R_VECT_MASK_CLR__dma1__WIDTH 1 | ||
| 5096 | #define R_VECT_MASK_CLR__dma1__clr 1 | ||
| 5097 | #define R_VECT_MASK_CLR__dma1__nop 0 | ||
| 5098 | #define R_VECT_MASK_CLR__dma0__BITNR 16 | ||
| 5099 | #define R_VECT_MASK_CLR__dma0__WIDTH 1 | ||
| 5100 | #define R_VECT_MASK_CLR__dma0__clr 1 | ||
| 5101 | #define R_VECT_MASK_CLR__dma0__nop 0 | ||
| 5102 | #define R_VECT_MASK_CLR__ext_dma1__BITNR 13 | ||
| 5103 | #define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 | ||
| 5104 | #define R_VECT_MASK_CLR__ext_dma1__clr 1 | ||
| 5105 | #define R_VECT_MASK_CLR__ext_dma1__nop 0 | ||
| 5106 | #define R_VECT_MASK_CLR__ext_dma0__BITNR 12 | ||
| 5107 | #define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 | ||
| 5108 | #define R_VECT_MASK_CLR__ext_dma0__clr 1 | ||
| 5109 | #define R_VECT_MASK_CLR__ext_dma0__nop 0 | ||
| 5110 | #define R_VECT_MASK_CLR__pa__BITNR 11 | ||
| 5111 | #define R_VECT_MASK_CLR__pa__WIDTH 1 | ||
| 5112 | #define R_VECT_MASK_CLR__pa__clr 1 | ||
| 5113 | #define R_VECT_MASK_CLR__pa__nop 0 | ||
| 5114 | #define R_VECT_MASK_CLR__irq_intnr__BITNR 10 | ||
| 5115 | #define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 | ||
| 5116 | #define R_VECT_MASK_CLR__irq_intnr__clr 1 | ||
| 5117 | #define R_VECT_MASK_CLR__irq_intnr__nop 0 | ||
| 5118 | #define R_VECT_MASK_CLR__sw__BITNR 9 | ||
| 5119 | #define R_VECT_MASK_CLR__sw__WIDTH 1 | ||
| 5120 | #define R_VECT_MASK_CLR__sw__clr 1 | ||
| 5121 | #define R_VECT_MASK_CLR__sw__nop 0 | ||
| 5122 | #define R_VECT_MASK_CLR__serial__BITNR 8 | ||
| 5123 | #define R_VECT_MASK_CLR__serial__WIDTH 1 | ||
| 5124 | #define R_VECT_MASK_CLR__serial__clr 1 | ||
| 5125 | #define R_VECT_MASK_CLR__serial__nop 0 | ||
| 5126 | #define R_VECT_MASK_CLR__snmp__BITNR 7 | ||
| 5127 | #define R_VECT_MASK_CLR__snmp__WIDTH 1 | ||
| 5128 | #define R_VECT_MASK_CLR__snmp__clr 1 | ||
| 5129 | #define R_VECT_MASK_CLR__snmp__nop 0 | ||
| 5130 | #define R_VECT_MASK_CLR__network__BITNR 6 | ||
| 5131 | #define R_VECT_MASK_CLR__network__WIDTH 1 | ||
| 5132 | #define R_VECT_MASK_CLR__network__clr 1 | ||
| 5133 | #define R_VECT_MASK_CLR__network__nop 0 | ||
| 5134 | #define R_VECT_MASK_CLR__scsi1__BITNR 5 | ||
| 5135 | #define R_VECT_MASK_CLR__scsi1__WIDTH 1 | ||
| 5136 | #define R_VECT_MASK_CLR__scsi1__clr 1 | ||
| 5137 | #define R_VECT_MASK_CLR__scsi1__nop 0 | ||
| 5138 | #define R_VECT_MASK_CLR__par1__BITNR 5 | ||
| 5139 | #define R_VECT_MASK_CLR__par1__WIDTH 1 | ||
| 5140 | #define R_VECT_MASK_CLR__par1__clr 1 | ||
| 5141 | #define R_VECT_MASK_CLR__par1__nop 0 | ||
| 5142 | #define R_VECT_MASK_CLR__scsi0__BITNR 4 | ||
| 5143 | #define R_VECT_MASK_CLR__scsi0__WIDTH 1 | ||
| 5144 | #define R_VECT_MASK_CLR__scsi0__clr 1 | ||
| 5145 | #define R_VECT_MASK_CLR__scsi0__nop 0 | ||
| 5146 | #define R_VECT_MASK_CLR__par0__BITNR 4 | ||
| 5147 | #define R_VECT_MASK_CLR__par0__WIDTH 1 | ||
| 5148 | #define R_VECT_MASK_CLR__par0__clr 1 | ||
| 5149 | #define R_VECT_MASK_CLR__par0__nop 0 | ||
| 5150 | #define R_VECT_MASK_CLR__ata__BITNR 4 | ||
| 5151 | #define R_VECT_MASK_CLR__ata__WIDTH 1 | ||
| 5152 | #define R_VECT_MASK_CLR__ata__clr 1 | ||
| 5153 | #define R_VECT_MASK_CLR__ata__nop 0 | ||
| 5154 | #define R_VECT_MASK_CLR__mio__BITNR 4 | ||
| 5155 | #define R_VECT_MASK_CLR__mio__WIDTH 1 | ||
| 5156 | #define R_VECT_MASK_CLR__mio__clr 1 | ||
| 5157 | #define R_VECT_MASK_CLR__mio__nop 0 | ||
| 5158 | #define R_VECT_MASK_CLR__timer1__BITNR 3 | ||
| 5159 | #define R_VECT_MASK_CLR__timer1__WIDTH 1 | ||
| 5160 | #define R_VECT_MASK_CLR__timer1__clr 1 | ||
| 5161 | #define R_VECT_MASK_CLR__timer1__nop 0 | ||
| 5162 | #define R_VECT_MASK_CLR__timer0__BITNR 2 | ||
| 5163 | #define R_VECT_MASK_CLR__timer0__WIDTH 1 | ||
| 5164 | #define R_VECT_MASK_CLR__timer0__clr 1 | ||
| 5165 | #define R_VECT_MASK_CLR__timer0__nop 0 | ||
| 5166 | #define R_VECT_MASK_CLR__nmi__BITNR 1 | ||
| 5167 | #define R_VECT_MASK_CLR__nmi__WIDTH 1 | ||
| 5168 | #define R_VECT_MASK_CLR__nmi__clr 1 | ||
| 5169 | #define R_VECT_MASK_CLR__nmi__nop 0 | ||
| 5170 | #define R_VECT_MASK_CLR__some__BITNR 0 | ||
| 5171 | #define R_VECT_MASK_CLR__some__WIDTH 1 | ||
| 5172 | #define R_VECT_MASK_CLR__some__clr 1 | ||
| 5173 | #define R_VECT_MASK_CLR__some__nop 0 | ||
| 5174 | |||
| 5175 | #define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) | ||
| 5176 | #define R_VECT_READ__usb__BITNR 31 | ||
| 5177 | #define R_VECT_READ__usb__WIDTH 1 | ||
| 5178 | #define R_VECT_READ__usb__active 1 | ||
| 5179 | #define R_VECT_READ__usb__inactive 0 | ||
| 5180 | #define R_VECT_READ__dma9__BITNR 25 | ||
| 5181 | #define R_VECT_READ__dma9__WIDTH 1 | ||
| 5182 | #define R_VECT_READ__dma9__active 1 | ||
| 5183 | #define R_VECT_READ__dma9__inactive 0 | ||
| 5184 | #define R_VECT_READ__dma8__BITNR 24 | ||
| 5185 | #define R_VECT_READ__dma8__WIDTH 1 | ||
| 5186 | #define R_VECT_READ__dma8__active 1 | ||
| 5187 | #define R_VECT_READ__dma8__inactive 0 | ||
| 5188 | #define R_VECT_READ__dma7__BITNR 23 | ||
| 5189 | #define R_VECT_READ__dma7__WIDTH 1 | ||
| 5190 | #define R_VECT_READ__dma7__active 1 | ||
| 5191 | #define R_VECT_READ__dma7__inactive 0 | ||
| 5192 | #define R_VECT_READ__dma6__BITNR 22 | ||
| 5193 | #define R_VECT_READ__dma6__WIDTH 1 | ||
| 5194 | #define R_VECT_READ__dma6__active 1 | ||
| 5195 | #define R_VECT_READ__dma6__inactive 0 | ||
| 5196 | #define R_VECT_READ__dma5__BITNR 21 | ||
| 5197 | #define R_VECT_READ__dma5__WIDTH 1 | ||
| 5198 | #define R_VECT_READ__dma5__active 1 | ||
| 5199 | #define R_VECT_READ__dma5__inactive 0 | ||
| 5200 | #define R_VECT_READ__dma4__BITNR 20 | ||
| 5201 | #define R_VECT_READ__dma4__WIDTH 1 | ||
| 5202 | #define R_VECT_READ__dma4__active 1 | ||
| 5203 | #define R_VECT_READ__dma4__inactive 0 | ||
| 5204 | #define R_VECT_READ__dma3__BITNR 19 | ||
| 5205 | #define R_VECT_READ__dma3__WIDTH 1 | ||
| 5206 | #define R_VECT_READ__dma3__active 1 | ||
| 5207 | #define R_VECT_READ__dma3__inactive 0 | ||
| 5208 | #define R_VECT_READ__dma2__BITNR 18 | ||
| 5209 | #define R_VECT_READ__dma2__WIDTH 1 | ||
| 5210 | #define R_VECT_READ__dma2__active 1 | ||
| 5211 | #define R_VECT_READ__dma2__inactive 0 | ||
| 5212 | #define R_VECT_READ__dma1__BITNR 17 | ||
| 5213 | #define R_VECT_READ__dma1__WIDTH 1 | ||
| 5214 | #define R_VECT_READ__dma1__active 1 | ||
| 5215 | #define R_VECT_READ__dma1__inactive 0 | ||
| 5216 | #define R_VECT_READ__dma0__BITNR 16 | ||
| 5217 | #define R_VECT_READ__dma0__WIDTH 1 | ||
| 5218 | #define R_VECT_READ__dma0__active 1 | ||
| 5219 | #define R_VECT_READ__dma0__inactive 0 | ||
| 5220 | #define R_VECT_READ__ext_dma1__BITNR 13 | ||
| 5221 | #define R_VECT_READ__ext_dma1__WIDTH 1 | ||
| 5222 | #define R_VECT_READ__ext_dma1__active 1 | ||
| 5223 | #define R_VECT_READ__ext_dma1__inactive 0 | ||
| 5224 | #define R_VECT_READ__ext_dma0__BITNR 12 | ||
| 5225 | #define R_VECT_READ__ext_dma0__WIDTH 1 | ||
| 5226 | #define R_VECT_READ__ext_dma0__active 1 | ||
| 5227 | #define R_VECT_READ__ext_dma0__inactive 0 | ||
| 5228 | #define R_VECT_READ__pa__BITNR 11 | ||
| 5229 | #define R_VECT_READ__pa__WIDTH 1 | ||
| 5230 | #define R_VECT_READ__pa__active 1 | ||
| 5231 | #define R_VECT_READ__pa__inactive 0 | ||
| 5232 | #define R_VECT_READ__irq_intnr__BITNR 10 | ||
| 5233 | #define R_VECT_READ__irq_intnr__WIDTH 1 | ||
| 5234 | #define R_VECT_READ__irq_intnr__active 1 | ||
| 5235 | #define R_VECT_READ__irq_intnr__inactive 0 | ||
| 5236 | #define R_VECT_READ__sw__BITNR 9 | ||
| 5237 | #define R_VECT_READ__sw__WIDTH 1 | ||
| 5238 | #define R_VECT_READ__sw__active 1 | ||
| 5239 | #define R_VECT_READ__sw__inactive 0 | ||
| 5240 | #define R_VECT_READ__serial__BITNR 8 | ||
| 5241 | #define R_VECT_READ__serial__WIDTH 1 | ||
| 5242 | #define R_VECT_READ__serial__active 1 | ||
| 5243 | #define R_VECT_READ__serial__inactive 0 | ||
| 5244 | #define R_VECT_READ__snmp__BITNR 7 | ||
| 5245 | #define R_VECT_READ__snmp__WIDTH 1 | ||
| 5246 | #define R_VECT_READ__snmp__active 1 | ||
| 5247 | #define R_VECT_READ__snmp__inactive 0 | ||
| 5248 | #define R_VECT_READ__network__BITNR 6 | ||
| 5249 | #define R_VECT_READ__network__WIDTH 1 | ||
| 5250 | #define R_VECT_READ__network__active 1 | ||
| 5251 | #define R_VECT_READ__network__inactive 0 | ||
| 5252 | #define R_VECT_READ__scsi1__BITNR 5 | ||
| 5253 | #define R_VECT_READ__scsi1__WIDTH 1 | ||
| 5254 | #define R_VECT_READ__scsi1__active 1 | ||
| 5255 | #define R_VECT_READ__scsi1__inactive 0 | ||
| 5256 | #define R_VECT_READ__par1__BITNR 5 | ||
| 5257 | #define R_VECT_READ__par1__WIDTH 1 | ||
| 5258 | #define R_VECT_READ__par1__active 1 | ||
| 5259 | #define R_VECT_READ__par1__inactive 0 | ||
| 5260 | #define R_VECT_READ__scsi0__BITNR 4 | ||
| 5261 | #define R_VECT_READ__scsi0__WIDTH 1 | ||
| 5262 | #define R_VECT_READ__scsi0__active 1 | ||
| 5263 | #define R_VECT_READ__scsi0__inactive 0 | ||
| 5264 | #define R_VECT_READ__par0__BITNR 4 | ||
| 5265 | #define R_VECT_READ__par0__WIDTH 1 | ||
| 5266 | #define R_VECT_READ__par0__active 1 | ||
| 5267 | #define R_VECT_READ__par0__inactive 0 | ||
| 5268 | #define R_VECT_READ__ata__BITNR 4 | ||
| 5269 | #define R_VECT_READ__ata__WIDTH 1 | ||
| 5270 | #define R_VECT_READ__ata__active 1 | ||
| 5271 | #define R_VECT_READ__ata__inactive 0 | ||
| 5272 | #define R_VECT_READ__mio__BITNR 4 | ||
| 5273 | #define R_VECT_READ__mio__WIDTH 1 | ||
| 5274 | #define R_VECT_READ__mio__active 1 | ||
| 5275 | #define R_VECT_READ__mio__inactive 0 | ||
| 5276 | #define R_VECT_READ__timer1__BITNR 3 | ||
| 5277 | #define R_VECT_READ__timer1__WIDTH 1 | ||
| 5278 | #define R_VECT_READ__timer1__active 1 | ||
| 5279 | #define R_VECT_READ__timer1__inactive 0 | ||
| 5280 | #define R_VECT_READ__timer0__BITNR 2 | ||
| 5281 | #define R_VECT_READ__timer0__WIDTH 1 | ||
| 5282 | #define R_VECT_READ__timer0__active 1 | ||
| 5283 | #define R_VECT_READ__timer0__inactive 0 | ||
| 5284 | #define R_VECT_READ__nmi__BITNR 1 | ||
| 5285 | #define R_VECT_READ__nmi__WIDTH 1 | ||
| 5286 | #define R_VECT_READ__nmi__active 1 | ||
| 5287 | #define R_VECT_READ__nmi__inactive 0 | ||
| 5288 | #define R_VECT_READ__some__BITNR 0 | ||
| 5289 | #define R_VECT_READ__some__WIDTH 1 | ||
| 5290 | #define R_VECT_READ__some__active 1 | ||
| 5291 | #define R_VECT_READ__some__inactive 0 | ||
| 5292 | |||
| 5293 | #define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) | ||
| 5294 | #define R_VECT_MASK_SET__usb__BITNR 31 | ||
| 5295 | #define R_VECT_MASK_SET__usb__WIDTH 1 | ||
| 5296 | #define R_VECT_MASK_SET__usb__set 1 | ||
| 5297 | #define R_VECT_MASK_SET__usb__nop 0 | ||
| 5298 | #define R_VECT_MASK_SET__dma9__BITNR 25 | ||
| 5299 | #define R_VECT_MASK_SET__dma9__WIDTH 1 | ||
| 5300 | #define R_VECT_MASK_SET__dma9__set 1 | ||
| 5301 | #define R_VECT_MASK_SET__dma9__nop 0 | ||
| 5302 | #define R_VECT_MASK_SET__dma8__BITNR 24 | ||
| 5303 | #define R_VECT_MASK_SET__dma8__WIDTH 1 | ||
| 5304 | #define R_VECT_MASK_SET__dma8__set 1 | ||
| 5305 | #define R_VECT_MASK_SET__dma8__nop 0 | ||
| 5306 | #define R_VECT_MASK_SET__dma7__BITNR 23 | ||
| 5307 | #define R_VECT_MASK_SET__dma7__WIDTH 1 | ||
| 5308 | #define R_VECT_MASK_SET__dma7__set 1 | ||
| 5309 | #define R_VECT_MASK_SET__dma7__nop 0 | ||
| 5310 | #define R_VECT_MASK_SET__dma6__BITNR 22 | ||
| 5311 | #define R_VECT_MASK_SET__dma6__WIDTH 1 | ||
| 5312 | #define R_VECT_MASK_SET__dma6__set 1 | ||
| 5313 | #define R_VECT_MASK_SET__dma6__nop 0 | ||
| 5314 | #define R_VECT_MASK_SET__dma5__BITNR 21 | ||
| 5315 | #define R_VECT_MASK_SET__dma5__WIDTH 1 | ||
| 5316 | #define R_VECT_MASK_SET__dma5__set 1 | ||
| 5317 | #define R_VECT_MASK_SET__dma5__nop 0 | ||
| 5318 | #define R_VECT_MASK_SET__dma4__BITNR 20 | ||
| 5319 | #define R_VECT_MASK_SET__dma4__WIDTH 1 | ||
| 5320 | #define R_VECT_MASK_SET__dma4__set 1 | ||
| 5321 | #define R_VECT_MASK_SET__dma4__nop 0 | ||
| 5322 | #define R_VECT_MASK_SET__dma3__BITNR 19 | ||
| 5323 | #define R_VECT_MASK_SET__dma3__WIDTH 1 | ||
| 5324 | #define R_VECT_MASK_SET__dma3__set 1 | ||
| 5325 | #define R_VECT_MASK_SET__dma3__nop 0 | ||
| 5326 | #define R_VECT_MASK_SET__dma2__BITNR 18 | ||
| 5327 | #define R_VECT_MASK_SET__dma2__WIDTH 1 | ||
| 5328 | #define R_VECT_MASK_SET__dma2__set 1 | ||
| 5329 | #define R_VECT_MASK_SET__dma2__nop 0 | ||
| 5330 | #define R_VECT_MASK_SET__dma1__BITNR 17 | ||
| 5331 | #define R_VECT_MASK_SET__dma1__WIDTH 1 | ||
| 5332 | #define R_VECT_MASK_SET__dma1__set 1 | ||
| 5333 | #define R_VECT_MASK_SET__dma1__nop 0 | ||
| 5334 | #define R_VECT_MASK_SET__dma0__BITNR 16 | ||
| 5335 | #define R_VECT_MASK_SET__dma0__WIDTH 1 | ||
| 5336 | #define R_VECT_MASK_SET__dma0__set 1 | ||
| 5337 | #define R_VECT_MASK_SET__dma0__nop 0 | ||
| 5338 | #define R_VECT_MASK_SET__ext_dma1__BITNR 13 | ||
| 5339 | #define R_VECT_MASK_SET__ext_dma1__WIDTH 1 | ||
| 5340 | #define R_VECT_MASK_SET__ext_dma1__set 1 | ||
| 5341 | #define R_VECT_MASK_SET__ext_dma1__nop 0 | ||
| 5342 | #define R_VECT_MASK_SET__ext_dma0__BITNR 12 | ||
| 5343 | #define R_VECT_MASK_SET__ext_dma0__WIDTH 1 | ||
| 5344 | #define R_VECT_MASK_SET__ext_dma0__set 1 | ||
| 5345 | #define R_VECT_MASK_SET__ext_dma0__nop 0 | ||
| 5346 | #define R_VECT_MASK_SET__pa__BITNR 11 | ||
| 5347 | #define R_VECT_MASK_SET__pa__WIDTH 1 | ||
| 5348 | #define R_VECT_MASK_SET__pa__set 1 | ||
| 5349 | #define R_VECT_MASK_SET__pa__nop 0 | ||
| 5350 | #define R_VECT_MASK_SET__irq_intnr__BITNR 10 | ||
| 5351 | #define R_VECT_MASK_SET__irq_intnr__WIDTH 1 | ||
| 5352 | #define R_VECT_MASK_SET__irq_intnr__set 1 | ||
| 5353 | #define R_VECT_MASK_SET__irq_intnr__nop 0 | ||
| 5354 | #define R_VECT_MASK_SET__sw__BITNR 9 | ||
| 5355 | #define R_VECT_MASK_SET__sw__WIDTH 1 | ||
| 5356 | #define R_VECT_MASK_SET__sw__set 1 | ||
| 5357 | #define R_VECT_MASK_SET__sw__nop 0 | ||
| 5358 | #define R_VECT_MASK_SET__serial__BITNR 8 | ||
| 5359 | #define R_VECT_MASK_SET__serial__WIDTH 1 | ||
| 5360 | #define R_VECT_MASK_SET__serial__set 1 | ||
| 5361 | #define R_VECT_MASK_SET__serial__nop 0 | ||
| 5362 | #define R_VECT_MASK_SET__snmp__BITNR 7 | ||
| 5363 | #define R_VECT_MASK_SET__snmp__WIDTH 1 | ||
| 5364 | #define R_VECT_MASK_SET__snmp__set 1 | ||
| 5365 | #define R_VECT_MASK_SET__snmp__nop 0 | ||
| 5366 | #define R_VECT_MASK_SET__network__BITNR 6 | ||
| 5367 | #define R_VECT_MASK_SET__network__WIDTH 1 | ||
| 5368 | #define R_VECT_MASK_SET__network__set 1 | ||
| 5369 | #define R_VECT_MASK_SET__network__nop 0 | ||
| 5370 | #define R_VECT_MASK_SET__scsi1__BITNR 5 | ||
| 5371 | #define R_VECT_MASK_SET__scsi1__WIDTH 1 | ||
| 5372 | #define R_VECT_MASK_SET__scsi1__set 1 | ||
| 5373 | #define R_VECT_MASK_SET__scsi1__nop 0 | ||
| 5374 | #define R_VECT_MASK_SET__par1__BITNR 5 | ||
| 5375 | #define R_VECT_MASK_SET__par1__WIDTH 1 | ||
| 5376 | #define R_VECT_MASK_SET__par1__set 1 | ||
| 5377 | #define R_VECT_MASK_SET__par1__nop 0 | ||
| 5378 | #define R_VECT_MASK_SET__scsi0__BITNR 4 | ||
| 5379 | #define R_VECT_MASK_SET__scsi0__WIDTH 1 | ||
| 5380 | #define R_VECT_MASK_SET__scsi0__set 1 | ||
| 5381 | #define R_VECT_MASK_SET__scsi0__nop 0 | ||
| 5382 | #define R_VECT_MASK_SET__par0__BITNR 4 | ||
| 5383 | #define R_VECT_MASK_SET__par0__WIDTH 1 | ||
| 5384 | #define R_VECT_MASK_SET__par0__set 1 | ||
| 5385 | #define R_VECT_MASK_SET__par0__nop 0 | ||
| 5386 | #define R_VECT_MASK_SET__ata__BITNR 4 | ||
| 5387 | #define R_VECT_MASK_SET__ata__WIDTH 1 | ||
| 5388 | #define R_VECT_MASK_SET__ata__set 1 | ||
| 5389 | #define R_VECT_MASK_SET__ata__nop 0 | ||
| 5390 | #define R_VECT_MASK_SET__mio__BITNR 4 | ||
| 5391 | #define R_VECT_MASK_SET__mio__WIDTH 1 | ||
| 5392 | #define R_VECT_MASK_SET__mio__set 1 | ||
| 5393 | #define R_VECT_MASK_SET__mio__nop 0 | ||
| 5394 | #define R_VECT_MASK_SET__timer1__BITNR 3 | ||
| 5395 | #define R_VECT_MASK_SET__timer1__WIDTH 1 | ||
| 5396 | #define R_VECT_MASK_SET__timer1__set 1 | ||
| 5397 | #define R_VECT_MASK_SET__timer1__nop 0 | ||
| 5398 | #define R_VECT_MASK_SET__timer0__BITNR 2 | ||
| 5399 | #define R_VECT_MASK_SET__timer0__WIDTH 1 | ||
| 5400 | #define R_VECT_MASK_SET__timer0__set 1 | ||
| 5401 | #define R_VECT_MASK_SET__timer0__nop 0 | ||
| 5402 | #define R_VECT_MASK_SET__nmi__BITNR 1 | ||
| 5403 | #define R_VECT_MASK_SET__nmi__WIDTH 1 | ||
| 5404 | #define R_VECT_MASK_SET__nmi__set 1 | ||
| 5405 | #define R_VECT_MASK_SET__nmi__nop 0 | ||
| 5406 | #define R_VECT_MASK_SET__some__BITNR 0 | ||
| 5407 | #define R_VECT_MASK_SET__some__WIDTH 1 | ||
| 5408 | #define R_VECT_MASK_SET__some__set 1 | ||
| 5409 | #define R_VECT_MASK_SET__some__nop 0 | ||
| 5410 | |||
| 5411 | /* | ||
| 5412 | !* DMA registers | ||
| 5413 | !*/ | ||
| 5414 | |||
| 5415 | #define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) | ||
| 5416 | #define R_SET_EOP__ch9_eop__BITNR 3 | ||
| 5417 | #define R_SET_EOP__ch9_eop__WIDTH 1 | ||
| 5418 | #define R_SET_EOP__ch9_eop__set 1 | ||
| 5419 | #define R_SET_EOP__ch9_eop__nop 0 | ||
| 5420 | #define R_SET_EOP__ch7_eop__BITNR 2 | ||
| 5421 | #define R_SET_EOP__ch7_eop__WIDTH 1 | ||
| 5422 | #define R_SET_EOP__ch7_eop__set 1 | ||
| 5423 | #define R_SET_EOP__ch7_eop__nop 0 | ||
| 5424 | #define R_SET_EOP__ch5_eop__BITNR 1 | ||
| 5425 | #define R_SET_EOP__ch5_eop__WIDTH 1 | ||
| 5426 | #define R_SET_EOP__ch5_eop__set 1 | ||
| 5427 | #define R_SET_EOP__ch5_eop__nop 0 | ||
| 5428 | #define R_SET_EOP__ch3_eop__BITNR 0 | ||
| 5429 | #define R_SET_EOP__ch3_eop__WIDTH 1 | ||
| 5430 | #define R_SET_EOP__ch3_eop__set 1 | ||
| 5431 | #define R_SET_EOP__ch3_eop__nop 0 | ||
| 5432 | |||
| 5433 | #define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) | ||
| 5434 | #define R_DMA_CH0_HWSW__hw__BITNR 16 | ||
| 5435 | #define R_DMA_CH0_HWSW__hw__WIDTH 16 | ||
| 5436 | #define R_DMA_CH0_HWSW__sw__BITNR 0 | ||
| 5437 | #define R_DMA_CH0_HWSW__sw__WIDTH 16 | ||
| 5438 | |||
| 5439 | #define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) | ||
| 5440 | #define R_DMA_CH0_DESCR__descr__BITNR 0 | ||
| 5441 | #define R_DMA_CH0_DESCR__descr__WIDTH 32 | ||
| 5442 | |||
| 5443 | #define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) | ||
| 5444 | #define R_DMA_CH0_NEXT__next__BITNR 0 | ||
| 5445 | #define R_DMA_CH0_NEXT__next__WIDTH 32 | ||
| 5446 | |||
| 5447 | #define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) | ||
| 5448 | #define R_DMA_CH0_BUF__buf__BITNR 0 | ||
| 5449 | #define R_DMA_CH0_BUF__buf__WIDTH 32 | ||
| 5450 | |||
| 5451 | #define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) | ||
| 5452 | #define R_DMA_CH0_FIRST__first__BITNR 0 | ||
| 5453 | #define R_DMA_CH0_FIRST__first__WIDTH 32 | ||
| 5454 | |||
| 5455 | #define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) | ||
| 5456 | #define R_DMA_CH0_CMD__cmd__BITNR 0 | ||
| 5457 | #define R_DMA_CH0_CMD__cmd__WIDTH 3 | ||
| 5458 | #define R_DMA_CH0_CMD__cmd__hold 0 | ||
| 5459 | #define R_DMA_CH0_CMD__cmd__start 1 | ||
| 5460 | #define R_DMA_CH0_CMD__cmd__restart 3 | ||
| 5461 | #define R_DMA_CH0_CMD__cmd__continue 3 | ||
| 5462 | #define R_DMA_CH0_CMD__cmd__reset 4 | ||
| 5463 | |||
| 5464 | #define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) | ||
| 5465 | #define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 | ||
| 5466 | #define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5467 | #define R_DMA_CH0_CLR_INTR__clr_eop__do 1 | ||
| 5468 | #define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 | ||
| 5469 | #define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 | ||
| 5470 | #define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5471 | #define R_DMA_CH0_CLR_INTR__clr_descr__do 1 | ||
| 5472 | #define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 | ||
| 5473 | |||
| 5474 | #define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) | ||
| 5475 | #define R_DMA_CH0_STATUS__avail__BITNR 0 | ||
| 5476 | #define R_DMA_CH0_STATUS__avail__WIDTH 7 | ||
| 5477 | |||
| 5478 | #define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) | ||
| 5479 | #define R_DMA_CH1_HWSW__hw__BITNR 16 | ||
| 5480 | #define R_DMA_CH1_HWSW__hw__WIDTH 16 | ||
| 5481 | #define R_DMA_CH1_HWSW__sw__BITNR 0 | ||
| 5482 | #define R_DMA_CH1_HWSW__sw__WIDTH 16 | ||
| 5483 | |||
| 5484 | #define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) | ||
| 5485 | #define R_DMA_CH1_DESCR__descr__BITNR 0 | ||
| 5486 | #define R_DMA_CH1_DESCR__descr__WIDTH 32 | ||
| 5487 | |||
| 5488 | #define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) | ||
| 5489 | #define R_DMA_CH1_NEXT__next__BITNR 0 | ||
| 5490 | #define R_DMA_CH1_NEXT__next__WIDTH 32 | ||
| 5491 | |||
| 5492 | #define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) | ||
| 5493 | #define R_DMA_CH1_BUF__buf__BITNR 0 | ||
| 5494 | #define R_DMA_CH1_BUF__buf__WIDTH 32 | ||
| 5495 | |||
| 5496 | #define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) | ||
| 5497 | #define R_DMA_CH1_FIRST__first__BITNR 0 | ||
| 5498 | #define R_DMA_CH1_FIRST__first__WIDTH 32 | ||
| 5499 | |||
| 5500 | #define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) | ||
| 5501 | #define R_DMA_CH1_CMD__cmd__BITNR 0 | ||
| 5502 | #define R_DMA_CH1_CMD__cmd__WIDTH 3 | ||
| 5503 | #define R_DMA_CH1_CMD__cmd__hold 0 | ||
| 5504 | #define R_DMA_CH1_CMD__cmd__start 1 | ||
| 5505 | #define R_DMA_CH1_CMD__cmd__restart 3 | ||
| 5506 | #define R_DMA_CH1_CMD__cmd__continue 3 | ||
| 5507 | #define R_DMA_CH1_CMD__cmd__reset 4 | ||
| 5508 | |||
| 5509 | #define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) | ||
| 5510 | #define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 | ||
| 5511 | #define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5512 | #define R_DMA_CH1_CLR_INTR__clr_eop__do 1 | ||
| 5513 | #define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 | ||
| 5514 | #define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 | ||
| 5515 | #define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5516 | #define R_DMA_CH1_CLR_INTR__clr_descr__do 1 | ||
| 5517 | #define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 | ||
| 5518 | |||
| 5519 | #define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) | ||
| 5520 | #define R_DMA_CH1_STATUS__avail__BITNR 0 | ||
| 5521 | #define R_DMA_CH1_STATUS__avail__WIDTH 7 | ||
| 5522 | |||
| 5523 | #define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) | ||
| 5524 | #define R_DMA_CH2_HWSW__hw__BITNR 16 | ||
| 5525 | #define R_DMA_CH2_HWSW__hw__WIDTH 16 | ||
| 5526 | #define R_DMA_CH2_HWSW__sw__BITNR 0 | ||
| 5527 | #define R_DMA_CH2_HWSW__sw__WIDTH 16 | ||
| 5528 | |||
| 5529 | #define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) | ||
| 5530 | #define R_DMA_CH2_DESCR__descr__BITNR 0 | ||
| 5531 | #define R_DMA_CH2_DESCR__descr__WIDTH 32 | ||
| 5532 | |||
| 5533 | #define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) | ||
| 5534 | #define R_DMA_CH2_NEXT__next__BITNR 0 | ||
| 5535 | #define R_DMA_CH2_NEXT__next__WIDTH 32 | ||
| 5536 | |||
| 5537 | #define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) | ||
| 5538 | #define R_DMA_CH2_BUF__buf__BITNR 0 | ||
| 5539 | #define R_DMA_CH2_BUF__buf__WIDTH 32 | ||
| 5540 | |||
| 5541 | #define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) | ||
| 5542 | #define R_DMA_CH2_FIRST__first__BITNR 0 | ||
| 5543 | #define R_DMA_CH2_FIRST__first__WIDTH 32 | ||
| 5544 | |||
| 5545 | #define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) | ||
| 5546 | #define R_DMA_CH2_CMD__cmd__BITNR 0 | ||
| 5547 | #define R_DMA_CH2_CMD__cmd__WIDTH 3 | ||
| 5548 | #define R_DMA_CH2_CMD__cmd__hold 0 | ||
| 5549 | #define R_DMA_CH2_CMD__cmd__start 1 | ||
| 5550 | #define R_DMA_CH2_CMD__cmd__restart 3 | ||
| 5551 | #define R_DMA_CH2_CMD__cmd__continue 3 | ||
| 5552 | #define R_DMA_CH2_CMD__cmd__reset 4 | ||
| 5553 | |||
| 5554 | #define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) | ||
| 5555 | #define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 | ||
| 5556 | #define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5557 | #define R_DMA_CH2_CLR_INTR__clr_eop__do 1 | ||
| 5558 | #define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 | ||
| 5559 | #define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 | ||
| 5560 | #define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5561 | #define R_DMA_CH2_CLR_INTR__clr_descr__do 1 | ||
| 5562 | #define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 | ||
| 5563 | |||
| 5564 | #define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) | ||
| 5565 | #define R_DMA_CH2_STATUS__avail__BITNR 0 | ||
| 5566 | #define R_DMA_CH2_STATUS__avail__WIDTH 7 | ||
| 5567 | |||
| 5568 | #define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) | ||
| 5569 | #define R_DMA_CH3_HWSW__hw__BITNR 16 | ||
| 5570 | #define R_DMA_CH3_HWSW__hw__WIDTH 16 | ||
| 5571 | #define R_DMA_CH3_HWSW__sw__BITNR 0 | ||
| 5572 | #define R_DMA_CH3_HWSW__sw__WIDTH 16 | ||
| 5573 | |||
| 5574 | #define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) | ||
| 5575 | #define R_DMA_CH3_DESCR__descr__BITNR 0 | ||
| 5576 | #define R_DMA_CH3_DESCR__descr__WIDTH 32 | ||
| 5577 | |||
| 5578 | #define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) | ||
| 5579 | #define R_DMA_CH3_NEXT__next__BITNR 0 | ||
| 5580 | #define R_DMA_CH3_NEXT__next__WIDTH 32 | ||
| 5581 | |||
| 5582 | #define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) | ||
| 5583 | #define R_DMA_CH3_BUF__buf__BITNR 0 | ||
| 5584 | #define R_DMA_CH3_BUF__buf__WIDTH 32 | ||
| 5585 | |||
| 5586 | #define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) | ||
| 5587 | #define R_DMA_CH3_FIRST__first__BITNR 0 | ||
| 5588 | #define R_DMA_CH3_FIRST__first__WIDTH 32 | ||
| 5589 | |||
| 5590 | #define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) | ||
| 5591 | #define R_DMA_CH3_CMD__cmd__BITNR 0 | ||
| 5592 | #define R_DMA_CH3_CMD__cmd__WIDTH 3 | ||
| 5593 | #define R_DMA_CH3_CMD__cmd__hold 0 | ||
| 5594 | #define R_DMA_CH3_CMD__cmd__start 1 | ||
| 5595 | #define R_DMA_CH3_CMD__cmd__restart 3 | ||
| 5596 | #define R_DMA_CH3_CMD__cmd__continue 3 | ||
| 5597 | #define R_DMA_CH3_CMD__cmd__reset 4 | ||
| 5598 | |||
| 5599 | #define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) | ||
| 5600 | #define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 | ||
| 5601 | #define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5602 | #define R_DMA_CH3_CLR_INTR__clr_eop__do 1 | ||
| 5603 | #define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 | ||
| 5604 | #define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 | ||
| 5605 | #define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5606 | #define R_DMA_CH3_CLR_INTR__clr_descr__do 1 | ||
| 5607 | #define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 | ||
| 5608 | |||
| 5609 | #define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) | ||
| 5610 | #define R_DMA_CH3_STATUS__avail__BITNR 0 | ||
| 5611 | #define R_DMA_CH3_STATUS__avail__WIDTH 7 | ||
| 5612 | |||
| 5613 | #define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) | ||
| 5614 | #define R_DMA_CH4_HWSW__hw__BITNR 16 | ||
| 5615 | #define R_DMA_CH4_HWSW__hw__WIDTH 16 | ||
| 5616 | #define R_DMA_CH4_HWSW__sw__BITNR 0 | ||
| 5617 | #define R_DMA_CH4_HWSW__sw__WIDTH 16 | ||
| 5618 | |||
| 5619 | #define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) | ||
| 5620 | #define R_DMA_CH4_DESCR__descr__BITNR 0 | ||
| 5621 | #define R_DMA_CH4_DESCR__descr__WIDTH 32 | ||
| 5622 | |||
| 5623 | #define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) | ||
| 5624 | #define R_DMA_CH4_NEXT__next__BITNR 0 | ||
| 5625 | #define R_DMA_CH4_NEXT__next__WIDTH 32 | ||
| 5626 | |||
| 5627 | #define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) | ||
| 5628 | #define R_DMA_CH4_BUF__buf__BITNR 0 | ||
| 5629 | #define R_DMA_CH4_BUF__buf__WIDTH 32 | ||
| 5630 | |||
| 5631 | #define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) | ||
| 5632 | #define R_DMA_CH4_FIRST__first__BITNR 0 | ||
| 5633 | #define R_DMA_CH4_FIRST__first__WIDTH 32 | ||
| 5634 | |||
| 5635 | #define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) | ||
| 5636 | #define R_DMA_CH4_CMD__cmd__BITNR 0 | ||
| 5637 | #define R_DMA_CH4_CMD__cmd__WIDTH 3 | ||
| 5638 | #define R_DMA_CH4_CMD__cmd__hold 0 | ||
| 5639 | #define R_DMA_CH4_CMD__cmd__start 1 | ||
| 5640 | #define R_DMA_CH4_CMD__cmd__restart 3 | ||
| 5641 | #define R_DMA_CH4_CMD__cmd__continue 3 | ||
| 5642 | #define R_DMA_CH4_CMD__cmd__reset 4 | ||
| 5643 | |||
| 5644 | #define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) | ||
| 5645 | #define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 | ||
| 5646 | #define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5647 | #define R_DMA_CH4_CLR_INTR__clr_eop__do 1 | ||
| 5648 | #define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 | ||
| 5649 | #define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 | ||
| 5650 | #define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5651 | #define R_DMA_CH4_CLR_INTR__clr_descr__do 1 | ||
| 5652 | #define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 | ||
| 5653 | |||
| 5654 | #define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) | ||
| 5655 | #define R_DMA_CH4_STATUS__avail__BITNR 0 | ||
| 5656 | #define R_DMA_CH4_STATUS__avail__WIDTH 7 | ||
| 5657 | |||
| 5658 | #define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) | ||
| 5659 | #define R_DMA_CH5_HWSW__hw__BITNR 16 | ||
| 5660 | #define R_DMA_CH5_HWSW__hw__WIDTH 16 | ||
| 5661 | #define R_DMA_CH5_HWSW__sw__BITNR 0 | ||
| 5662 | #define R_DMA_CH5_HWSW__sw__WIDTH 16 | ||
| 5663 | |||
| 5664 | #define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) | ||
| 5665 | #define R_DMA_CH5_DESCR__descr__BITNR 0 | ||
| 5666 | #define R_DMA_CH5_DESCR__descr__WIDTH 32 | ||
| 5667 | |||
| 5668 | #define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) | ||
| 5669 | #define R_DMA_CH5_NEXT__next__BITNR 0 | ||
| 5670 | #define R_DMA_CH5_NEXT__next__WIDTH 32 | ||
| 5671 | |||
| 5672 | #define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) | ||
| 5673 | #define R_DMA_CH5_BUF__buf__BITNR 0 | ||
| 5674 | #define R_DMA_CH5_BUF__buf__WIDTH 32 | ||
| 5675 | |||
| 5676 | #define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) | ||
| 5677 | #define R_DMA_CH5_FIRST__first__BITNR 0 | ||
| 5678 | #define R_DMA_CH5_FIRST__first__WIDTH 32 | ||
| 5679 | |||
| 5680 | #define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) | ||
| 5681 | #define R_DMA_CH5_CMD__cmd__BITNR 0 | ||
| 5682 | #define R_DMA_CH5_CMD__cmd__WIDTH 3 | ||
| 5683 | #define R_DMA_CH5_CMD__cmd__hold 0 | ||
| 5684 | #define R_DMA_CH5_CMD__cmd__start 1 | ||
| 5685 | #define R_DMA_CH5_CMD__cmd__restart 3 | ||
| 5686 | #define R_DMA_CH5_CMD__cmd__continue 3 | ||
| 5687 | #define R_DMA_CH5_CMD__cmd__reset 4 | ||
| 5688 | |||
| 5689 | #define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) | ||
| 5690 | #define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 | ||
| 5691 | #define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5692 | #define R_DMA_CH5_CLR_INTR__clr_eop__do 1 | ||
| 5693 | #define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 | ||
| 5694 | #define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 | ||
| 5695 | #define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5696 | #define R_DMA_CH5_CLR_INTR__clr_descr__do 1 | ||
| 5697 | #define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 | ||
| 5698 | |||
| 5699 | #define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) | ||
| 5700 | #define R_DMA_CH5_STATUS__avail__BITNR 0 | ||
| 5701 | #define R_DMA_CH5_STATUS__avail__WIDTH 7 | ||
| 5702 | |||
| 5703 | #define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) | ||
| 5704 | #define R_DMA_CH6_HWSW__hw__BITNR 16 | ||
| 5705 | #define R_DMA_CH6_HWSW__hw__WIDTH 16 | ||
| 5706 | #define R_DMA_CH6_HWSW__sw__BITNR 0 | ||
| 5707 | #define R_DMA_CH6_HWSW__sw__WIDTH 16 | ||
| 5708 | |||
| 5709 | #define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) | ||
| 5710 | #define R_DMA_CH6_DESCR__descr__BITNR 0 | ||
| 5711 | #define R_DMA_CH6_DESCR__descr__WIDTH 32 | ||
| 5712 | |||
| 5713 | #define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) | ||
| 5714 | #define R_DMA_CH6_NEXT__next__BITNR 0 | ||
| 5715 | #define R_DMA_CH6_NEXT__next__WIDTH 32 | ||
| 5716 | |||
| 5717 | #define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) | ||
| 5718 | #define R_DMA_CH6_BUF__buf__BITNR 0 | ||
| 5719 | #define R_DMA_CH6_BUF__buf__WIDTH 32 | ||
| 5720 | |||
| 5721 | #define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) | ||
| 5722 | #define R_DMA_CH6_FIRST__first__BITNR 0 | ||
| 5723 | #define R_DMA_CH6_FIRST__first__WIDTH 32 | ||
| 5724 | |||
| 5725 | #define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) | ||
| 5726 | #define R_DMA_CH6_CMD__cmd__BITNR 0 | ||
| 5727 | #define R_DMA_CH6_CMD__cmd__WIDTH 3 | ||
| 5728 | #define R_DMA_CH6_CMD__cmd__hold 0 | ||
| 5729 | #define R_DMA_CH6_CMD__cmd__start 1 | ||
| 5730 | #define R_DMA_CH6_CMD__cmd__restart 3 | ||
| 5731 | #define R_DMA_CH6_CMD__cmd__continue 3 | ||
| 5732 | #define R_DMA_CH6_CMD__cmd__reset 4 | ||
| 5733 | |||
| 5734 | #define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) | ||
| 5735 | #define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 | ||
| 5736 | #define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5737 | #define R_DMA_CH6_CLR_INTR__clr_eop__do 1 | ||
| 5738 | #define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 | ||
| 5739 | #define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 | ||
| 5740 | #define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5741 | #define R_DMA_CH6_CLR_INTR__clr_descr__do 1 | ||
| 5742 | #define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 | ||
| 5743 | |||
| 5744 | #define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) | ||
| 5745 | #define R_DMA_CH6_STATUS__avail__BITNR 0 | ||
| 5746 | #define R_DMA_CH6_STATUS__avail__WIDTH 7 | ||
| 5747 | |||
| 5748 | #define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) | ||
| 5749 | #define R_DMA_CH7_HWSW__hw__BITNR 16 | ||
| 5750 | #define R_DMA_CH7_HWSW__hw__WIDTH 16 | ||
| 5751 | #define R_DMA_CH7_HWSW__sw__BITNR 0 | ||
| 5752 | #define R_DMA_CH7_HWSW__sw__WIDTH 16 | ||
| 5753 | |||
| 5754 | #define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) | ||
| 5755 | #define R_DMA_CH7_DESCR__descr__BITNR 0 | ||
| 5756 | #define R_DMA_CH7_DESCR__descr__WIDTH 32 | ||
| 5757 | |||
| 5758 | #define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) | ||
| 5759 | #define R_DMA_CH7_NEXT__next__BITNR 0 | ||
| 5760 | #define R_DMA_CH7_NEXT__next__WIDTH 32 | ||
| 5761 | |||
| 5762 | #define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) | ||
| 5763 | #define R_DMA_CH7_BUF__buf__BITNR 0 | ||
| 5764 | #define R_DMA_CH7_BUF__buf__WIDTH 32 | ||
| 5765 | |||
| 5766 | #define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) | ||
| 5767 | #define R_DMA_CH7_FIRST__first__BITNR 0 | ||
| 5768 | #define R_DMA_CH7_FIRST__first__WIDTH 32 | ||
| 5769 | |||
| 5770 | #define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) | ||
| 5771 | #define R_DMA_CH7_CMD__cmd__BITNR 0 | ||
| 5772 | #define R_DMA_CH7_CMD__cmd__WIDTH 3 | ||
| 5773 | #define R_DMA_CH7_CMD__cmd__hold 0 | ||
| 5774 | #define R_DMA_CH7_CMD__cmd__start 1 | ||
| 5775 | #define R_DMA_CH7_CMD__cmd__restart 3 | ||
| 5776 | #define R_DMA_CH7_CMD__cmd__continue 3 | ||
| 5777 | #define R_DMA_CH7_CMD__cmd__reset 4 | ||
| 5778 | |||
| 5779 | #define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) | ||
| 5780 | #define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 | ||
| 5781 | #define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5782 | #define R_DMA_CH7_CLR_INTR__clr_eop__do 1 | ||
| 5783 | #define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 | ||
| 5784 | #define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 | ||
| 5785 | #define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5786 | #define R_DMA_CH7_CLR_INTR__clr_descr__do 1 | ||
| 5787 | #define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 | ||
| 5788 | |||
| 5789 | #define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) | ||
| 5790 | #define R_DMA_CH7_STATUS__avail__BITNR 0 | ||
| 5791 | #define R_DMA_CH7_STATUS__avail__WIDTH 7 | ||
| 5792 | |||
| 5793 | #define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) | ||
| 5794 | #define R_DMA_CH8_HWSW__hw__BITNR 16 | ||
| 5795 | #define R_DMA_CH8_HWSW__hw__WIDTH 16 | ||
| 5796 | #define R_DMA_CH8_HWSW__sw__BITNR 0 | ||
| 5797 | #define R_DMA_CH8_HWSW__sw__WIDTH 16 | ||
| 5798 | |||
| 5799 | #define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) | ||
| 5800 | #define R_DMA_CH8_DESCR__descr__BITNR 0 | ||
| 5801 | #define R_DMA_CH8_DESCR__descr__WIDTH 32 | ||
| 5802 | |||
| 5803 | #define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) | ||
| 5804 | #define R_DMA_CH8_NEXT__next__BITNR 0 | ||
| 5805 | #define R_DMA_CH8_NEXT__next__WIDTH 32 | ||
| 5806 | |||
| 5807 | #define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) | ||
| 5808 | #define R_DMA_CH8_BUF__buf__BITNR 0 | ||
| 5809 | #define R_DMA_CH8_BUF__buf__WIDTH 32 | ||
| 5810 | |||
| 5811 | #define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) | ||
| 5812 | #define R_DMA_CH8_FIRST__first__BITNR 0 | ||
| 5813 | #define R_DMA_CH8_FIRST__first__WIDTH 32 | ||
| 5814 | |||
| 5815 | #define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) | ||
| 5816 | #define R_DMA_CH8_CMD__cmd__BITNR 0 | ||
| 5817 | #define R_DMA_CH8_CMD__cmd__WIDTH 3 | ||
| 5818 | #define R_DMA_CH8_CMD__cmd__hold 0 | ||
| 5819 | #define R_DMA_CH8_CMD__cmd__start 1 | ||
| 5820 | #define R_DMA_CH8_CMD__cmd__restart 3 | ||
| 5821 | #define R_DMA_CH8_CMD__cmd__continue 3 | ||
| 5822 | #define R_DMA_CH8_CMD__cmd__reset 4 | ||
| 5823 | |||
| 5824 | #define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) | ||
| 5825 | #define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 | ||
| 5826 | #define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5827 | #define R_DMA_CH8_CLR_INTR__clr_eop__do 1 | ||
| 5828 | #define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 | ||
| 5829 | #define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 | ||
| 5830 | #define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5831 | #define R_DMA_CH8_CLR_INTR__clr_descr__do 1 | ||
| 5832 | #define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 | ||
| 5833 | |||
| 5834 | #define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) | ||
| 5835 | #define R_DMA_CH8_STATUS__avail__BITNR 0 | ||
| 5836 | #define R_DMA_CH8_STATUS__avail__WIDTH 7 | ||
| 5837 | |||
| 5838 | #define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) | ||
| 5839 | #define R_DMA_CH8_SUB__sub__BITNR 0 | ||
| 5840 | #define R_DMA_CH8_SUB__sub__WIDTH 32 | ||
| 5841 | |||
| 5842 | #define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) | ||
| 5843 | #define R_DMA_CH8_NEP__nep__BITNR 0 | ||
| 5844 | #define R_DMA_CH8_NEP__nep__WIDTH 32 | ||
| 5845 | |||
| 5846 | #define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) | ||
| 5847 | #define R_DMA_CH8_SUB0_EP__ep__BITNR 0 | ||
| 5848 | #define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 | ||
| 5849 | |||
| 5850 | #define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) | ||
| 5851 | #define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 | ||
| 5852 | #define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 | ||
| 5853 | #define R_DMA_CH8_SUB0_CMD__cmd__stop 0 | ||
| 5854 | #define R_DMA_CH8_SUB0_CMD__cmd__start 1 | ||
| 5855 | |||
| 5856 | #define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) | ||
| 5857 | #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 | ||
| 5858 | #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5859 | #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 | ||
| 5860 | #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 | ||
| 5861 | |||
| 5862 | #define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) | ||
| 5863 | #define R_DMA_CH8_SUB1_EP__ep__BITNR 0 | ||
| 5864 | #define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 | ||
| 5865 | |||
| 5866 | #define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) | ||
| 5867 | #define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 | ||
| 5868 | #define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 | ||
| 5869 | #define R_DMA_CH8_SUB1_CMD__cmd__stop 0 | ||
| 5870 | #define R_DMA_CH8_SUB1_CMD__cmd__start 1 | ||
| 5871 | |||
| 5872 | #define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) | ||
| 5873 | #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 | ||
| 5874 | #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5875 | #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 | ||
| 5876 | #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 | ||
| 5877 | |||
| 5878 | #define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) | ||
| 5879 | #define R_DMA_CH8_SUB2_EP__ep__BITNR 0 | ||
| 5880 | #define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 | ||
| 5881 | |||
| 5882 | #define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) | ||
| 5883 | #define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 | ||
| 5884 | #define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 | ||
| 5885 | #define R_DMA_CH8_SUB2_CMD__cmd__stop 0 | ||
| 5886 | #define R_DMA_CH8_SUB2_CMD__cmd__start 1 | ||
| 5887 | |||
| 5888 | #define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) | ||
| 5889 | #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 | ||
| 5890 | #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5891 | #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 | ||
| 5892 | #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 | ||
| 5893 | |||
| 5894 | #define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) | ||
| 5895 | #define R_DMA_CH8_SUB3_EP__ep__BITNR 0 | ||
| 5896 | #define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 | ||
| 5897 | |||
| 5898 | #define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) | ||
| 5899 | #define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 | ||
| 5900 | #define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 | ||
| 5901 | #define R_DMA_CH8_SUB3_CMD__cmd__stop 0 | ||
| 5902 | #define R_DMA_CH8_SUB3_CMD__cmd__start 1 | ||
| 5903 | |||
| 5904 | #define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) | ||
| 5905 | #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 | ||
| 5906 | #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5907 | #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 | ||
| 5908 | #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 | ||
| 5909 | |||
| 5910 | #define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) | ||
| 5911 | #define R_DMA_CH9_HWSW__hw__BITNR 16 | ||
| 5912 | #define R_DMA_CH9_HWSW__hw__WIDTH 16 | ||
| 5913 | #define R_DMA_CH9_HWSW__sw__BITNR 0 | ||
| 5914 | #define R_DMA_CH9_HWSW__sw__WIDTH 16 | ||
| 5915 | |||
| 5916 | #define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) | ||
| 5917 | #define R_DMA_CH9_DESCR__descr__BITNR 0 | ||
| 5918 | #define R_DMA_CH9_DESCR__descr__WIDTH 32 | ||
| 5919 | |||
| 5920 | #define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) | ||
| 5921 | #define R_DMA_CH9_NEXT__next__BITNR 0 | ||
| 5922 | #define R_DMA_CH9_NEXT__next__WIDTH 32 | ||
| 5923 | |||
| 5924 | #define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) | ||
| 5925 | #define R_DMA_CH9_BUF__buf__BITNR 0 | ||
| 5926 | #define R_DMA_CH9_BUF__buf__WIDTH 32 | ||
| 5927 | |||
| 5928 | #define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) | ||
| 5929 | #define R_DMA_CH9_FIRST__first__BITNR 0 | ||
| 5930 | #define R_DMA_CH9_FIRST__first__WIDTH 32 | ||
| 5931 | |||
| 5932 | #define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) | ||
| 5933 | #define R_DMA_CH9_CMD__cmd__BITNR 0 | ||
| 5934 | #define R_DMA_CH9_CMD__cmd__WIDTH 3 | ||
| 5935 | #define R_DMA_CH9_CMD__cmd__hold 0 | ||
| 5936 | #define R_DMA_CH9_CMD__cmd__start 1 | ||
| 5937 | #define R_DMA_CH9_CMD__cmd__restart 3 | ||
| 5938 | #define R_DMA_CH9_CMD__cmd__continue 3 | ||
| 5939 | #define R_DMA_CH9_CMD__cmd__reset 4 | ||
| 5940 | |||
| 5941 | #define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) | ||
| 5942 | #define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 | ||
| 5943 | #define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5944 | #define R_DMA_CH9_CLR_INTR__clr_eop__do 1 | ||
| 5945 | #define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 | ||
| 5946 | #define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 | ||
| 5947 | #define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5948 | #define R_DMA_CH9_CLR_INTR__clr_descr__do 1 | ||
| 5949 | #define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 | ||
| 5950 | |||
| 5951 | #define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) | ||
| 5952 | #define R_DMA_CH9_STATUS__avail__BITNR 0 | ||
| 5953 | #define R_DMA_CH9_STATUS__avail__WIDTH 7 | ||
| 5954 | |||
| 5955 | /* | ||
| 5956 | !* Test mode registers | ||
| 5957 | !*/ | ||
| 5958 | |||
| 5959 | #define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) | ||
| 5960 | #define R_TEST_MODE__single_step__BITNR 19 | ||
| 5961 | #define R_TEST_MODE__single_step__WIDTH 1 | ||
| 5962 | #define R_TEST_MODE__single_step__on 1 | ||
| 5963 | #define R_TEST_MODE__single_step__off 0 | ||
| 5964 | #define R_TEST_MODE__step_wr__BITNR 18 | ||
| 5965 | #define R_TEST_MODE__step_wr__WIDTH 1 | ||
| 5966 | #define R_TEST_MODE__step_wr__on 1 | ||
| 5967 | #define R_TEST_MODE__step_wr__off 0 | ||
| 5968 | #define R_TEST_MODE__step_rd__BITNR 17 | ||
| 5969 | #define R_TEST_MODE__step_rd__WIDTH 1 | ||
| 5970 | #define R_TEST_MODE__step_rd__on 1 | ||
| 5971 | #define R_TEST_MODE__step_rd__off 0 | ||
| 5972 | #define R_TEST_MODE__step_fetch__BITNR 16 | ||
| 5973 | #define R_TEST_MODE__step_fetch__WIDTH 1 | ||
| 5974 | #define R_TEST_MODE__step_fetch__on 1 | ||
| 5975 | #define R_TEST_MODE__step_fetch__off 0 | ||
| 5976 | #define R_TEST_MODE__mmu_test__BITNR 12 | ||
| 5977 | #define R_TEST_MODE__mmu_test__WIDTH 1 | ||
| 5978 | #define R_TEST_MODE__mmu_test__on 1 | ||
| 5979 | #define R_TEST_MODE__mmu_test__off 0 | ||
| 5980 | #define R_TEST_MODE__usb_test__BITNR 11 | ||
| 5981 | #define R_TEST_MODE__usb_test__WIDTH 1 | ||
| 5982 | #define R_TEST_MODE__usb_test__on 1 | ||
| 5983 | #define R_TEST_MODE__usb_test__off 0 | ||
| 5984 | #define R_TEST_MODE__scsi_timer_test__BITNR 10 | ||
| 5985 | #define R_TEST_MODE__scsi_timer_test__WIDTH 1 | ||
| 5986 | #define R_TEST_MODE__scsi_timer_test__on 1 | ||
| 5987 | #define R_TEST_MODE__scsi_timer_test__off 0 | ||
| 5988 | #define R_TEST_MODE__backoff__BITNR 9 | ||
| 5989 | #define R_TEST_MODE__backoff__WIDTH 1 | ||
| 5990 | #define R_TEST_MODE__backoff__on 1 | ||
| 5991 | #define R_TEST_MODE__backoff__off 0 | ||
| 5992 | #define R_TEST_MODE__snmp_test__BITNR 8 | ||
| 5993 | #define R_TEST_MODE__snmp_test__WIDTH 1 | ||
| 5994 | #define R_TEST_MODE__snmp_test__on 1 | ||
| 5995 | #define R_TEST_MODE__snmp_test__off 0 | ||
| 5996 | #define R_TEST_MODE__snmp_inc__BITNR 7 | ||
| 5997 | #define R_TEST_MODE__snmp_inc__WIDTH 1 | ||
| 5998 | #define R_TEST_MODE__snmp_inc__do 1 | ||
| 5999 | #define R_TEST_MODE__snmp_inc__dont 0 | ||
| 6000 | #define R_TEST_MODE__ser_loop__BITNR 6 | ||
| 6001 | #define R_TEST_MODE__ser_loop__WIDTH 1 | ||
| 6002 | #define R_TEST_MODE__ser_loop__on 1 | ||
| 6003 | #define R_TEST_MODE__ser_loop__off 0 | ||
| 6004 | #define R_TEST_MODE__baudrate__BITNR 5 | ||
| 6005 | #define R_TEST_MODE__baudrate__WIDTH 1 | ||
| 6006 | #define R_TEST_MODE__baudrate__on 1 | ||
| 6007 | #define R_TEST_MODE__baudrate__off 0 | ||
| 6008 | #define R_TEST_MODE__timer__BITNR 3 | ||
| 6009 | #define R_TEST_MODE__timer__WIDTH 2 | ||
| 6010 | #define R_TEST_MODE__timer__off 0 | ||
| 6011 | #define R_TEST_MODE__timer__even 1 | ||
| 6012 | #define R_TEST_MODE__timer__odd 2 | ||
| 6013 | #define R_TEST_MODE__timer__all 3 | ||
| 6014 | #define R_TEST_MODE__cache_test__BITNR 2 | ||
| 6015 | #define R_TEST_MODE__cache_test__WIDTH 1 | ||
| 6016 | #define R_TEST_MODE__cache_test__normal 0 | ||
| 6017 | #define R_TEST_MODE__cache_test__test 1 | ||
| 6018 | #define R_TEST_MODE__tag_test__BITNR 1 | ||
| 6019 | #define R_TEST_MODE__tag_test__WIDTH 1 | ||
| 6020 | #define R_TEST_MODE__tag_test__normal 0 | ||
| 6021 | #define R_TEST_MODE__tag_test__test 1 | ||
| 6022 | #define R_TEST_MODE__cache_enable__BITNR 0 | ||
| 6023 | #define R_TEST_MODE__cache_enable__WIDTH 1 | ||
| 6024 | #define R_TEST_MODE__cache_enable__enable 1 | ||
| 6025 | #define R_TEST_MODE__cache_enable__disable 0 | ||
| 6026 | |||
| 6027 | #define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) | ||
| 6028 | #define R_SINGLE_STEP__single_step__BITNR 3 | ||
| 6029 | #define R_SINGLE_STEP__single_step__WIDTH 1 | ||
| 6030 | #define R_SINGLE_STEP__single_step__on 1 | ||
| 6031 | #define R_SINGLE_STEP__single_step__off 0 | ||
| 6032 | #define R_SINGLE_STEP__step_wr__BITNR 2 | ||
| 6033 | #define R_SINGLE_STEP__step_wr__WIDTH 1 | ||
| 6034 | #define R_SINGLE_STEP__step_wr__on 1 | ||
| 6035 | #define R_SINGLE_STEP__step_wr__off 0 | ||
| 6036 | #define R_SINGLE_STEP__step_rd__BITNR 1 | ||
| 6037 | #define R_SINGLE_STEP__step_rd__WIDTH 1 | ||
| 6038 | #define R_SINGLE_STEP__step_rd__on 1 | ||
| 6039 | #define R_SINGLE_STEP__step_rd__off 0 | ||
| 6040 | #define R_SINGLE_STEP__step_fetch__BITNR 0 | ||
| 6041 | #define R_SINGLE_STEP__step_fetch__WIDTH 1 | ||
| 6042 | #define R_SINGLE_STEP__step_fetch__on 1 | ||
| 6043 | #define R_SINGLE_STEP__step_fetch__off 0 | ||
| 6044 | |||
| 6045 | /* | ||
| 6046 | !* USB interface control registers | ||
| 6047 | !*/ | ||
| 6048 | |||
| 6049 | #define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) | ||
| 6050 | #define R_USB_REVISION__major__BITNR 4 | ||
| 6051 | #define R_USB_REVISION__major__WIDTH 4 | ||
| 6052 | #define R_USB_REVISION__minor__BITNR 0 | ||
| 6053 | #define R_USB_REVISION__minor__WIDTH 4 | ||
| 6054 | |||
| 6055 | #define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) | ||
| 6056 | #define R_USB_COMMAND__port_sel__BITNR 6 | ||
| 6057 | #define R_USB_COMMAND__port_sel__WIDTH 2 | ||
| 6058 | #define R_USB_COMMAND__port_sel__nop 0 | ||
| 6059 | #define R_USB_COMMAND__port_sel__port1 1 | ||
| 6060 | #define R_USB_COMMAND__port_sel__port2 2 | ||
| 6061 | #define R_USB_COMMAND__port_sel__both 3 | ||
| 6062 | #define R_USB_COMMAND__port_cmd__BITNR 4 | ||
| 6063 | #define R_USB_COMMAND__port_cmd__WIDTH 2 | ||
| 6064 | #define R_USB_COMMAND__port_cmd__reset 0 | ||
| 6065 | #define R_USB_COMMAND__port_cmd__disable 1 | ||
| 6066 | #define R_USB_COMMAND__port_cmd__suspend 2 | ||
| 6067 | #define R_USB_COMMAND__port_cmd__resume 3 | ||
| 6068 | #define R_USB_COMMAND__busy__BITNR 3 | ||
| 6069 | #define R_USB_COMMAND__busy__WIDTH 1 | ||
| 6070 | #define R_USB_COMMAND__busy__no 0 | ||
| 6071 | #define R_USB_COMMAND__busy__yes 1 | ||
| 6072 | #define R_USB_COMMAND__ctrl_cmd__BITNR 0 | ||
| 6073 | #define R_USB_COMMAND__ctrl_cmd__WIDTH 3 | ||
| 6074 | #define R_USB_COMMAND__ctrl_cmd__nop 0 | ||
| 6075 | #define R_USB_COMMAND__ctrl_cmd__reset 1 | ||
| 6076 | #define R_USB_COMMAND__ctrl_cmd__deconfig 2 | ||
| 6077 | #define R_USB_COMMAND__ctrl_cmd__host_config 3 | ||
| 6078 | #define R_USB_COMMAND__ctrl_cmd__dev_config 4 | ||
| 6079 | #define R_USB_COMMAND__ctrl_cmd__host_nop 5 | ||
| 6080 | #define R_USB_COMMAND__ctrl_cmd__host_run 6 | ||
| 6081 | #define R_USB_COMMAND__ctrl_cmd__host_stop 7 | ||
| 6082 | |||
| 6083 | #define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) | ||
| 6084 | #define R_USB_COMMAND_DEV__port_sel__BITNR 6 | ||
| 6085 | #define R_USB_COMMAND_DEV__port_sel__WIDTH 2 | ||
| 6086 | #define R_USB_COMMAND_DEV__port_sel__nop 0 | ||
| 6087 | #define R_USB_COMMAND_DEV__port_sel__dummy1 1 | ||
| 6088 | #define R_USB_COMMAND_DEV__port_sel__dummy2 2 | ||
| 6089 | #define R_USB_COMMAND_DEV__port_sel__any 3 | ||
| 6090 | #define R_USB_COMMAND_DEV__port_cmd__BITNR 4 | ||
| 6091 | #define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 | ||
| 6092 | #define R_USB_COMMAND_DEV__port_cmd__active 0 | ||
| 6093 | #define R_USB_COMMAND_DEV__port_cmd__passive 1 | ||
| 6094 | #define R_USB_COMMAND_DEV__port_cmd__nop 2 | ||
| 6095 | #define R_USB_COMMAND_DEV__port_cmd__wakeup 3 | ||
| 6096 | #define R_USB_COMMAND_DEV__busy__BITNR 3 | ||
| 6097 | #define R_USB_COMMAND_DEV__busy__WIDTH 1 | ||
| 6098 | #define R_USB_COMMAND_DEV__busy__no 0 | ||
| 6099 | #define R_USB_COMMAND_DEV__busy__yes 1 | ||
| 6100 | #define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 | ||
| 6101 | #define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 | ||
| 6102 | #define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 | ||
| 6103 | #define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 | ||
| 6104 | #define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 | ||
| 6105 | #define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 | ||
| 6106 | #define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 | ||
| 6107 | #define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 | ||
| 6108 | #define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 | ||
| 6109 | #define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 | ||
| 6110 | |||
| 6111 | #define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) | ||
| 6112 | #define R_USB_STATUS__ourun__BITNR 5 | ||
| 6113 | #define R_USB_STATUS__ourun__WIDTH 1 | ||
| 6114 | #define R_USB_STATUS__ourun__no 0 | ||
| 6115 | #define R_USB_STATUS__ourun__yes 1 | ||
| 6116 | #define R_USB_STATUS__perror__BITNR 4 | ||
| 6117 | #define R_USB_STATUS__perror__WIDTH 1 | ||
| 6118 | #define R_USB_STATUS__perror__no 0 | ||
| 6119 | #define R_USB_STATUS__perror__yes 1 | ||
| 6120 | #define R_USB_STATUS__device_mode__BITNR 3 | ||
| 6121 | #define R_USB_STATUS__device_mode__WIDTH 1 | ||
| 6122 | #define R_USB_STATUS__device_mode__no 0 | ||
| 6123 | #define R_USB_STATUS__device_mode__yes 1 | ||
| 6124 | #define R_USB_STATUS__host_mode__BITNR 2 | ||
| 6125 | #define R_USB_STATUS__host_mode__WIDTH 1 | ||
| 6126 | #define R_USB_STATUS__host_mode__no 0 | ||
| 6127 | #define R_USB_STATUS__host_mode__yes 1 | ||
| 6128 | #define R_USB_STATUS__started__BITNR 1 | ||
| 6129 | #define R_USB_STATUS__started__WIDTH 1 | ||
| 6130 | #define R_USB_STATUS__started__no 0 | ||
| 6131 | #define R_USB_STATUS__started__yes 1 | ||
| 6132 | #define R_USB_STATUS__running__BITNR 0 | ||
| 6133 | #define R_USB_STATUS__running__WIDTH 1 | ||
| 6134 | #define R_USB_STATUS__running__no 0 | ||
| 6135 | #define R_USB_STATUS__running__yes 1 | ||
| 6136 | |||
| 6137 | #define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) | ||
| 6138 | #define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 | ||
| 6139 | #define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 | ||
| 6140 | #define R_USB_IRQ_MASK_SET__iso_eof__nop 0 | ||
| 6141 | #define R_USB_IRQ_MASK_SET__iso_eof__set 1 | ||
| 6142 | #define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 | ||
| 6143 | #define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 | ||
| 6144 | #define R_USB_IRQ_MASK_SET__intr_eof__nop 0 | ||
| 6145 | #define R_USB_IRQ_MASK_SET__intr_eof__set 1 | ||
| 6146 | #define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 | ||
| 6147 | #define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 | ||
| 6148 | #define R_USB_IRQ_MASK_SET__iso_eot__nop 0 | ||
| 6149 | #define R_USB_IRQ_MASK_SET__iso_eot__set 1 | ||
| 6150 | #define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 | ||
| 6151 | #define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 | ||
| 6152 | #define R_USB_IRQ_MASK_SET__intr_eot__nop 0 | ||
| 6153 | #define R_USB_IRQ_MASK_SET__intr_eot__set 1 | ||
| 6154 | #define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 | ||
| 6155 | #define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 | ||
| 6156 | #define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 | ||
| 6157 | #define R_USB_IRQ_MASK_SET__ctl_eot__set 1 | ||
| 6158 | #define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 | ||
| 6159 | #define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 | ||
| 6160 | #define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 | ||
| 6161 | #define R_USB_IRQ_MASK_SET__bulk_eot__set 1 | ||
| 6162 | #define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 | ||
| 6163 | #define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 | ||
| 6164 | #define R_USB_IRQ_MASK_SET__epid_attn__nop 0 | ||
| 6165 | #define R_USB_IRQ_MASK_SET__epid_attn__set 1 | ||
| 6166 | #define R_USB_IRQ_MASK_SET__sof__BITNR 2 | ||
| 6167 | #define R_USB_IRQ_MASK_SET__sof__WIDTH 1 | ||
| 6168 | #define R_USB_IRQ_MASK_SET__sof__nop 0 | ||
| 6169 | #define R_USB_IRQ_MASK_SET__sof__set 1 | ||
| 6170 | #define R_USB_IRQ_MASK_SET__port_status__BITNR 1 | ||
| 6171 | #define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 | ||
| 6172 | #define R_USB_IRQ_MASK_SET__port_status__nop 0 | ||
| 6173 | #define R_USB_IRQ_MASK_SET__port_status__set 1 | ||
| 6174 | #define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 | ||
| 6175 | #define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 | ||
| 6176 | #define R_USB_IRQ_MASK_SET__ctl_status__nop 0 | ||
| 6177 | #define R_USB_IRQ_MASK_SET__ctl_status__set 1 | ||
| 6178 | |||
| 6179 | #define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) | ||
| 6180 | #define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 | ||
| 6181 | #define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 | ||
| 6182 | #define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 | ||
| 6183 | #define R_USB_IRQ_MASK_READ__iso_eof__pend 1 | ||
| 6184 | #define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 | ||
| 6185 | #define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 | ||
| 6186 | #define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 | ||
| 6187 | #define R_USB_IRQ_MASK_READ__intr_eof__pend 1 | ||
| 6188 | #define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 | ||
| 6189 | #define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 | ||
| 6190 | #define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 | ||
| 6191 | #define R_USB_IRQ_MASK_READ__iso_eot__pend 1 | ||
| 6192 | #define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 | ||
| 6193 | #define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 | ||
| 6194 | #define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 | ||
| 6195 | #define R_USB_IRQ_MASK_READ__intr_eot__pend 1 | ||
| 6196 | #define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 | ||
| 6197 | #define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 | ||
| 6198 | #define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 | ||
| 6199 | #define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 | ||
| 6200 | #define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 | ||
| 6201 | #define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 | ||
| 6202 | #define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 | ||
| 6203 | #define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 | ||
| 6204 | #define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 | ||
| 6205 | #define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 | ||
| 6206 | #define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 | ||
| 6207 | #define R_USB_IRQ_MASK_READ__epid_attn__pend 1 | ||
| 6208 | #define R_USB_IRQ_MASK_READ__sof__BITNR 2 | ||
| 6209 | #define R_USB_IRQ_MASK_READ__sof__WIDTH 1 | ||
| 6210 | #define R_USB_IRQ_MASK_READ__sof__no_pend 0 | ||
| 6211 | #define R_USB_IRQ_MASK_READ__sof__pend 1 | ||
| 6212 | #define R_USB_IRQ_MASK_READ__port_status__BITNR 1 | ||
| 6213 | #define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 | ||
| 6214 | #define R_USB_IRQ_MASK_READ__port_status__no_pend 0 | ||
| 6215 | #define R_USB_IRQ_MASK_READ__port_status__pend 1 | ||
| 6216 | #define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 | ||
| 6217 | #define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 | ||
| 6218 | #define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 | ||
| 6219 | #define R_USB_IRQ_MASK_READ__ctl_status__pend 1 | ||
| 6220 | |||
| 6221 | #define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) | ||
| 6222 | #define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 | ||
| 6223 | #define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 | ||
| 6224 | #define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 | ||
| 6225 | #define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 | ||
| 6226 | #define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 | ||
| 6227 | #define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 | ||
| 6228 | #define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 | ||
| 6229 | #define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 | ||
| 6230 | #define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 | ||
| 6231 | #define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 | ||
| 6232 | #define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 | ||
| 6233 | #define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 | ||
| 6234 | #define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 | ||
| 6235 | #define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 | ||
| 6236 | #define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 | ||
| 6237 | #define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 | ||
| 6238 | #define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 | ||
| 6239 | #define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 | ||
| 6240 | #define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 | ||
| 6241 | #define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 | ||
| 6242 | #define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 | ||
| 6243 | #define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 | ||
| 6244 | #define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 | ||
| 6245 | #define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 | ||
| 6246 | #define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 | ||
| 6247 | #define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 | ||
| 6248 | #define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 | ||
| 6249 | #define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 | ||
| 6250 | #define R_USB_IRQ_MASK_CLR__sof__BITNR 2 | ||
| 6251 | #define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 | ||
| 6252 | #define R_USB_IRQ_MASK_CLR__sof__nop 0 | ||
| 6253 | #define R_USB_IRQ_MASK_CLR__sof__clr 1 | ||
| 6254 | #define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 | ||
| 6255 | #define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 | ||
| 6256 | #define R_USB_IRQ_MASK_CLR__port_status__nop 0 | ||
| 6257 | #define R_USB_IRQ_MASK_CLR__port_status__clr 1 | ||
| 6258 | #define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 | ||
| 6259 | #define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 | ||
| 6260 | #define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 | ||
| 6261 | #define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 | ||
| 6262 | |||
| 6263 | #define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) | ||
| 6264 | #define R_USB_IRQ_READ__iso_eof__BITNR 13 | ||
| 6265 | #define R_USB_IRQ_READ__iso_eof__WIDTH 1 | ||
| 6266 | #define R_USB_IRQ_READ__iso_eof__no_pend 0 | ||
| 6267 | #define R_USB_IRQ_READ__iso_eof__pend 1 | ||
| 6268 | #define R_USB_IRQ_READ__intr_eof__BITNR 12 | ||
| 6269 | #define R_USB_IRQ_READ__intr_eof__WIDTH 1 | ||
| 6270 | #define R_USB_IRQ_READ__intr_eof__no_pend 0 | ||
| 6271 | #define R_USB_IRQ_READ__intr_eof__pend 1 | ||
| 6272 | #define R_USB_IRQ_READ__iso_eot__BITNR 11 | ||
| 6273 | #define R_USB_IRQ_READ__iso_eot__WIDTH 1 | ||
| 6274 | #define R_USB_IRQ_READ__iso_eot__no_pend 0 | ||
| 6275 | #define R_USB_IRQ_READ__iso_eot__pend 1 | ||
| 6276 | #define R_USB_IRQ_READ__intr_eot__BITNR 10 | ||
| 6277 | #define R_USB_IRQ_READ__intr_eot__WIDTH 1 | ||
| 6278 | #define R_USB_IRQ_READ__intr_eot__no_pend 0 | ||
| 6279 | #define R_USB_IRQ_READ__intr_eot__pend 1 | ||
| 6280 | #define R_USB_IRQ_READ__ctl_eot__BITNR 9 | ||
| 6281 | #define R_USB_IRQ_READ__ctl_eot__WIDTH 1 | ||
| 6282 | #define R_USB_IRQ_READ__ctl_eot__no_pend 0 | ||
| 6283 | #define R_USB_IRQ_READ__ctl_eot__pend 1 | ||
| 6284 | #define R_USB_IRQ_READ__bulk_eot__BITNR 8 | ||
| 6285 | #define R_USB_IRQ_READ__bulk_eot__WIDTH 1 | ||
| 6286 | #define R_USB_IRQ_READ__bulk_eot__no_pend 0 | ||
| 6287 | #define R_USB_IRQ_READ__bulk_eot__pend 1 | ||
| 6288 | #define R_USB_IRQ_READ__epid_attn__BITNR 3 | ||
| 6289 | #define R_USB_IRQ_READ__epid_attn__WIDTH 1 | ||
| 6290 | #define R_USB_IRQ_READ__epid_attn__no_pend 0 | ||
| 6291 | #define R_USB_IRQ_READ__epid_attn__pend 1 | ||
| 6292 | #define R_USB_IRQ_READ__sof__BITNR 2 | ||
| 6293 | #define R_USB_IRQ_READ__sof__WIDTH 1 | ||
| 6294 | #define R_USB_IRQ_READ__sof__no_pend 0 | ||
| 6295 | #define R_USB_IRQ_READ__sof__pend 1 | ||
| 6296 | #define R_USB_IRQ_READ__port_status__BITNR 1 | ||
| 6297 | #define R_USB_IRQ_READ__port_status__WIDTH 1 | ||
| 6298 | #define R_USB_IRQ_READ__port_status__no_pend 0 | ||
| 6299 | #define R_USB_IRQ_READ__port_status__pend 1 | ||
| 6300 | #define R_USB_IRQ_READ__ctl_status__BITNR 0 | ||
| 6301 | #define R_USB_IRQ_READ__ctl_status__WIDTH 1 | ||
| 6302 | #define R_USB_IRQ_READ__ctl_status__no_pend 0 | ||
| 6303 | #define R_USB_IRQ_READ__ctl_status__pend 1 | ||
| 6304 | |||
| 6305 | #define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) | ||
| 6306 | #define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 | ||
| 6307 | #define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 | ||
| 6308 | #define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 | ||
| 6309 | #define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 | ||
| 6310 | #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 | ||
| 6311 | #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 | ||
| 6312 | #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 | ||
| 6313 | #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 | ||
| 6314 | #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 | ||
| 6315 | #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 | ||
| 6316 | #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 | ||
| 6317 | #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 | ||
| 6318 | #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 | ||
| 6319 | #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 | ||
| 6320 | #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 | ||
| 6321 | #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 | ||
| 6322 | #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 | ||
| 6323 | #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 | ||
| 6324 | #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 | ||
| 6325 | #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 | ||
| 6326 | #define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 | ||
| 6327 | #define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 | ||
| 6328 | #define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 | ||
| 6329 | #define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 | ||
| 6330 | #define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 | ||
| 6331 | #define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 | ||
| 6332 | #define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 | ||
| 6333 | #define R_USB_IRQ_MASK_SET_DEV__sof__set 1 | ||
| 6334 | #define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 | ||
| 6335 | #define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 | ||
| 6336 | #define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 | ||
| 6337 | #define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 | ||
| 6338 | #define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 | ||
| 6339 | #define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 | ||
| 6340 | #define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 | ||
| 6341 | #define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 | ||
| 6342 | |||
| 6343 | #define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) | ||
| 6344 | #define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 | ||
| 6345 | #define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 | ||
| 6346 | #define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 | ||
| 6347 | #define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 | ||
| 6348 | #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 | ||
| 6349 | #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 | ||
| 6350 | #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 | ||
| 6351 | #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 | ||
| 6352 | #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 | ||
| 6353 | #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 | ||
| 6354 | #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 | ||
| 6355 | #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 | ||
| 6356 | #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 | ||
| 6357 | #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 | ||
| 6358 | #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 | ||
| 6359 | #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 | ||
| 6360 | #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 | ||
| 6361 | #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 | ||
| 6362 | #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 | ||
| 6363 | #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 | ||
| 6364 | #define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 | ||
| 6365 | #define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 | ||
| 6366 | #define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 | ||
| 6367 | #define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 | ||
| 6368 | #define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 | ||
| 6369 | #define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 | ||
| 6370 | #define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 | ||
| 6371 | #define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 | ||
| 6372 | #define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 | ||
| 6373 | #define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 | ||
| 6374 | #define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 | ||
| 6375 | #define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 | ||
| 6376 | #define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 | ||
| 6377 | #define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 | ||
| 6378 | #define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 | ||
| 6379 | #define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 | ||
| 6380 | |||
| 6381 | #define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) | ||
| 6382 | #define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 | ||
| 6383 | #define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 | ||
| 6384 | #define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 | ||
| 6385 | #define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 | ||
| 6386 | #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 | ||
| 6387 | #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 | ||
| 6388 | #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 | ||
| 6389 | #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 | ||
| 6390 | #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 | ||
| 6391 | #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 | ||
| 6392 | #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 | ||
| 6393 | #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 | ||
| 6394 | #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 | ||
| 6395 | #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 | ||
| 6396 | #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 | ||
| 6397 | #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 | ||
| 6398 | #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 | ||
| 6399 | #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 | ||
| 6400 | #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 | ||
| 6401 | #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 | ||
| 6402 | #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 | ||
| 6403 | #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 | ||
| 6404 | #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 | ||
| 6405 | #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 | ||
| 6406 | #define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 | ||
| 6407 | #define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 | ||
| 6408 | #define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 | ||
| 6409 | #define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 | ||
| 6410 | #define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 | ||
| 6411 | #define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 | ||
| 6412 | #define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 | ||
| 6413 | #define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 | ||
| 6414 | #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 | ||
| 6415 | #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 | ||
| 6416 | #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 | ||
| 6417 | #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 | ||
| 6418 | |||
| 6419 | #define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) | ||
| 6420 | #define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 | ||
| 6421 | #define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 | ||
| 6422 | #define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 | ||
| 6423 | #define R_USB_IRQ_READ_DEV__out_eot__pend 1 | ||
| 6424 | #define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 | ||
| 6425 | #define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 | ||
| 6426 | #define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 | ||
| 6427 | #define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 | ||
| 6428 | #define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 | ||
| 6429 | #define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 | ||
| 6430 | #define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 | ||
| 6431 | #define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 | ||
| 6432 | #define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 | ||
| 6433 | #define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 | ||
| 6434 | #define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 | ||
| 6435 | #define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 | ||
| 6436 | #define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 | ||
| 6437 | #define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 | ||
| 6438 | #define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 | ||
| 6439 | #define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 | ||
| 6440 | #define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 | ||
| 6441 | #define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 | ||
| 6442 | #define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 | ||
| 6443 | #define R_USB_IRQ_READ_DEV__epid_attn__pend 1 | ||
| 6444 | #define R_USB_IRQ_READ_DEV__sof__BITNR 2 | ||
| 6445 | #define R_USB_IRQ_READ_DEV__sof__WIDTH 1 | ||
| 6446 | #define R_USB_IRQ_READ_DEV__sof__no_pend 0 | ||
| 6447 | #define R_USB_IRQ_READ_DEV__sof__pend 1 | ||
| 6448 | #define R_USB_IRQ_READ_DEV__port_status__BITNR 1 | ||
| 6449 | #define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 | ||
| 6450 | #define R_USB_IRQ_READ_DEV__port_status__no_pend 0 | ||
| 6451 | #define R_USB_IRQ_READ_DEV__port_status__pend 1 | ||
| 6452 | #define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 | ||
| 6453 | #define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 | ||
| 6454 | #define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 | ||
| 6455 | #define R_USB_IRQ_READ_DEV__ctl_status__pend 1 | ||
| 6456 | |||
| 6457 | #define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) | ||
| 6458 | #define R_USB_FM_NUMBER__value__BITNR 0 | ||
| 6459 | #define R_USB_FM_NUMBER__value__WIDTH 32 | ||
| 6460 | |||
| 6461 | #define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) | ||
| 6462 | #define R_USB_FM_INTERVAL__fixed__BITNR 6 | ||
| 6463 | #define R_USB_FM_INTERVAL__fixed__WIDTH 8 | ||
| 6464 | #define R_USB_FM_INTERVAL__adj__BITNR 0 | ||
| 6465 | #define R_USB_FM_INTERVAL__adj__WIDTH 6 | ||
| 6466 | |||
| 6467 | #define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) | ||
| 6468 | #define R_USB_FM_REMAINING__value__BITNR 0 | ||
| 6469 | #define R_USB_FM_REMAINING__value__WIDTH 14 | ||
| 6470 | |||
| 6471 | #define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) | ||
| 6472 | #define R_USB_FM_PSTART__value__BITNR 0 | ||
| 6473 | #define R_USB_FM_PSTART__value__WIDTH 14 | ||
| 6474 | |||
| 6475 | #define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) | ||
| 6476 | #define R_USB_RH_STATUS__babble2__BITNR 7 | ||
| 6477 | #define R_USB_RH_STATUS__babble2__WIDTH 1 | ||
| 6478 | #define R_USB_RH_STATUS__babble2__no 0 | ||
| 6479 | #define R_USB_RH_STATUS__babble2__yes 1 | ||
| 6480 | #define R_USB_RH_STATUS__babble1__BITNR 6 | ||
| 6481 | #define R_USB_RH_STATUS__babble1__WIDTH 1 | ||
| 6482 | #define R_USB_RH_STATUS__babble1__no 0 | ||
| 6483 | #define R_USB_RH_STATUS__babble1__yes 1 | ||
| 6484 | #define R_USB_RH_STATUS__bus1__BITNR 4 | ||
| 6485 | #define R_USB_RH_STATUS__bus1__WIDTH 2 | ||
| 6486 | #define R_USB_RH_STATUS__bus1__SE0 0 | ||
| 6487 | #define R_USB_RH_STATUS__bus1__Diff0 1 | ||
| 6488 | #define R_USB_RH_STATUS__bus1__Diff1 2 | ||
| 6489 | #define R_USB_RH_STATUS__bus1__SE1 3 | ||
| 6490 | #define R_USB_RH_STATUS__bus2__BITNR 2 | ||
| 6491 | #define R_USB_RH_STATUS__bus2__WIDTH 2 | ||
| 6492 | #define R_USB_RH_STATUS__bus2__SE0 0 | ||
| 6493 | #define R_USB_RH_STATUS__bus2__Diff0 1 | ||
| 6494 | #define R_USB_RH_STATUS__bus2__Diff1 2 | ||
| 6495 | #define R_USB_RH_STATUS__bus2__SE1 3 | ||
| 6496 | #define R_USB_RH_STATUS__nports__BITNR 0 | ||
| 6497 | #define R_USB_RH_STATUS__nports__WIDTH 2 | ||
| 6498 | |||
| 6499 | #define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) | ||
| 6500 | #define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 | ||
| 6501 | #define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 | ||
| 6502 | #define R_USB_RH_PORT_STATUS_1__speed__full 0 | ||
| 6503 | #define R_USB_RH_PORT_STATUS_1__speed__low 1 | ||
| 6504 | #define R_USB_RH_PORT_STATUS_1__power__BITNR 8 | ||
| 6505 | #define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 | ||
| 6506 | #define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 | ||
| 6507 | #define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 | ||
| 6508 | #define R_USB_RH_PORT_STATUS_1__reset__no 0 | ||
| 6509 | #define R_USB_RH_PORT_STATUS_1__reset__yes 1 | ||
| 6510 | #define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 | ||
| 6511 | #define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 | ||
| 6512 | #define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 | ||
| 6513 | #define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 | ||
| 6514 | #define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 | ||
| 6515 | #define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 | ||
| 6516 | #define R_USB_RH_PORT_STATUS_1__suspended__no 0 | ||
| 6517 | #define R_USB_RH_PORT_STATUS_1__suspended__yes 1 | ||
| 6518 | #define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 | ||
| 6519 | #define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 | ||
| 6520 | #define R_USB_RH_PORT_STATUS_1__enabled__no 0 | ||
| 6521 | #define R_USB_RH_PORT_STATUS_1__enabled__yes 1 | ||
| 6522 | #define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 | ||
| 6523 | #define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 | ||
| 6524 | #define R_USB_RH_PORT_STATUS_1__connected__no 0 | ||
| 6525 | #define R_USB_RH_PORT_STATUS_1__connected__yes 1 | ||
| 6526 | |||
| 6527 | #define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) | ||
| 6528 | #define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 | ||
| 6529 | #define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 | ||
| 6530 | #define R_USB_RH_PORT_STATUS_2__speed__full 0 | ||
| 6531 | #define R_USB_RH_PORT_STATUS_2__speed__low 1 | ||
| 6532 | #define R_USB_RH_PORT_STATUS_2__power__BITNR 8 | ||
| 6533 | #define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 | ||
| 6534 | #define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 | ||
| 6535 | #define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 | ||
| 6536 | #define R_USB_RH_PORT_STATUS_2__reset__no 0 | ||
| 6537 | #define R_USB_RH_PORT_STATUS_2__reset__yes 1 | ||
| 6538 | #define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 | ||
| 6539 | #define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 | ||
| 6540 | #define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 | ||
| 6541 | #define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 | ||
| 6542 | #define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 | ||
| 6543 | #define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 | ||
| 6544 | #define R_USB_RH_PORT_STATUS_2__suspended__no 0 | ||
| 6545 | #define R_USB_RH_PORT_STATUS_2__suspended__yes 1 | ||
| 6546 | #define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 | ||
| 6547 | #define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 | ||
| 6548 | #define R_USB_RH_PORT_STATUS_2__enabled__no 0 | ||
| 6549 | #define R_USB_RH_PORT_STATUS_2__enabled__yes 1 | ||
| 6550 | #define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 | ||
| 6551 | #define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 | ||
| 6552 | #define R_USB_RH_PORT_STATUS_2__connected__no 0 | ||
| 6553 | #define R_USB_RH_PORT_STATUS_2__connected__yes 1 | ||
| 6554 | |||
| 6555 | #define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) | ||
| 6556 | #define R_USB_EPT_INDEX__value__BITNR 0 | ||
| 6557 | #define R_USB_EPT_INDEX__value__WIDTH 5 | ||
| 6558 | |||
| 6559 | #define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) | ||
| 6560 | #define R_USB_EPT_DATA__valid__BITNR 31 | ||
| 6561 | #define R_USB_EPT_DATA__valid__WIDTH 1 | ||
| 6562 | #define R_USB_EPT_DATA__valid__no 0 | ||
| 6563 | #define R_USB_EPT_DATA__valid__yes 1 | ||
| 6564 | #define R_USB_EPT_DATA__hold__BITNR 30 | ||
| 6565 | #define R_USB_EPT_DATA__hold__WIDTH 1 | ||
| 6566 | #define R_USB_EPT_DATA__hold__no 0 | ||
| 6567 | #define R_USB_EPT_DATA__hold__yes 1 | ||
| 6568 | #define R_USB_EPT_DATA__error_count_in__BITNR 28 | ||
| 6569 | #define R_USB_EPT_DATA__error_count_in__WIDTH 2 | ||
| 6570 | #define R_USB_EPT_DATA__t_in__BITNR 27 | ||
| 6571 | #define R_USB_EPT_DATA__t_in__WIDTH 1 | ||
| 6572 | #define R_USB_EPT_DATA__low_speed__BITNR 26 | ||
| 6573 | #define R_USB_EPT_DATA__low_speed__WIDTH 1 | ||
| 6574 | #define R_USB_EPT_DATA__low_speed__no 0 | ||
| 6575 | #define R_USB_EPT_DATA__low_speed__yes 1 | ||
| 6576 | #define R_USB_EPT_DATA__port__BITNR 24 | ||
| 6577 | #define R_USB_EPT_DATA__port__WIDTH 2 | ||
| 6578 | #define R_USB_EPT_DATA__port__any 0 | ||
| 6579 | #define R_USB_EPT_DATA__port__p1 1 | ||
| 6580 | #define R_USB_EPT_DATA__port__p2 2 | ||
| 6581 | #define R_USB_EPT_DATA__port__undef 3 | ||
| 6582 | #define R_USB_EPT_DATA__error_code__BITNR 22 | ||
| 6583 | #define R_USB_EPT_DATA__error_code__WIDTH 2 | ||
| 6584 | #define R_USB_EPT_DATA__error_code__no_error 0 | ||
| 6585 | #define R_USB_EPT_DATA__error_code__stall 1 | ||
| 6586 | #define R_USB_EPT_DATA__error_code__bus_error 2 | ||
| 6587 | #define R_USB_EPT_DATA__error_code__buffer_error 3 | ||
| 6588 | #define R_USB_EPT_DATA__t_out__BITNR 21 | ||
| 6589 | #define R_USB_EPT_DATA__t_out__WIDTH 1 | ||
| 6590 | #define R_USB_EPT_DATA__error_count_out__BITNR 19 | ||
| 6591 | #define R_USB_EPT_DATA__error_count_out__WIDTH 2 | ||
| 6592 | #define R_USB_EPT_DATA__max_len__BITNR 11 | ||
| 6593 | #define R_USB_EPT_DATA__max_len__WIDTH 7 | ||
| 6594 | #define R_USB_EPT_DATA__ep__BITNR 7 | ||
| 6595 | #define R_USB_EPT_DATA__ep__WIDTH 4 | ||
| 6596 | #define R_USB_EPT_DATA__dev__BITNR 0 | ||
| 6597 | #define R_USB_EPT_DATA__dev__WIDTH 7 | ||
| 6598 | |||
| 6599 | #define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) | ||
| 6600 | #define R_USB_EPT_DATA_ISO__valid__BITNR 31 | ||
| 6601 | #define R_USB_EPT_DATA_ISO__valid__WIDTH 1 | ||
| 6602 | #define R_USB_EPT_DATA_ISO__valid__no 0 | ||
| 6603 | #define R_USB_EPT_DATA_ISO__valid__yes 1 | ||
| 6604 | #define R_USB_EPT_DATA_ISO__port__BITNR 24 | ||
| 6605 | #define R_USB_EPT_DATA_ISO__port__WIDTH 2 | ||
| 6606 | #define R_USB_EPT_DATA_ISO__port__any 0 | ||
| 6607 | #define R_USB_EPT_DATA_ISO__port__p1 1 | ||
| 6608 | #define R_USB_EPT_DATA_ISO__port__p2 2 | ||
| 6609 | #define R_USB_EPT_DATA_ISO__port__undef 3 | ||
| 6610 | #define R_USB_EPT_DATA_ISO__error_code__BITNR 22 | ||
| 6611 | #define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 | ||
| 6612 | #define R_USB_EPT_DATA_ISO__error_code__no_error 0 | ||
| 6613 | #define R_USB_EPT_DATA_ISO__error_code__stall 1 | ||
| 6614 | #define R_USB_EPT_DATA_ISO__error_code__bus_error 2 | ||
| 6615 | #define R_USB_EPT_DATA_ISO__error_code__TBD3 3 | ||
| 6616 | #define R_USB_EPT_DATA_ISO__max_len__BITNR 11 | ||
| 6617 | #define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 | ||
| 6618 | #define R_USB_EPT_DATA_ISO__ep__BITNR 7 | ||
| 6619 | #define R_USB_EPT_DATA_ISO__ep__WIDTH 4 | ||
| 6620 | #define R_USB_EPT_DATA_ISO__dev__BITNR 0 | ||
| 6621 | #define R_USB_EPT_DATA_ISO__dev__WIDTH 7 | ||
| 6622 | |||
| 6623 | #define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) | ||
| 6624 | #define R_USB_EPT_DATA_DEV__valid__BITNR 31 | ||
| 6625 | #define R_USB_EPT_DATA_DEV__valid__WIDTH 1 | ||
| 6626 | #define R_USB_EPT_DATA_DEV__valid__no 0 | ||
| 6627 | #define R_USB_EPT_DATA_DEV__valid__yes 1 | ||
| 6628 | #define R_USB_EPT_DATA_DEV__hold__BITNR 30 | ||
| 6629 | #define R_USB_EPT_DATA_DEV__hold__WIDTH 1 | ||
| 6630 | #define R_USB_EPT_DATA_DEV__hold__no 0 | ||
| 6631 | #define R_USB_EPT_DATA_DEV__hold__yes 1 | ||
| 6632 | #define R_USB_EPT_DATA_DEV__stall__BITNR 29 | ||
| 6633 | #define R_USB_EPT_DATA_DEV__stall__WIDTH 1 | ||
| 6634 | #define R_USB_EPT_DATA_DEV__stall__no 0 | ||
| 6635 | #define R_USB_EPT_DATA_DEV__stall__yes 1 | ||
| 6636 | #define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 | ||
| 6637 | #define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 | ||
| 6638 | #define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 | ||
| 6639 | #define R_USB_EPT_DATA_DEV__iso_resp__yes 1 | ||
| 6640 | #define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 | ||
| 6641 | #define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 | ||
| 6642 | #define R_USB_EPT_DATA_DEV__ctrl__no 0 | ||
| 6643 | #define R_USB_EPT_DATA_DEV__ctrl__yes 1 | ||
| 6644 | #define R_USB_EPT_DATA_DEV__iso__BITNR 26 | ||
| 6645 | #define R_USB_EPT_DATA_DEV__iso__WIDTH 1 | ||
| 6646 | #define R_USB_EPT_DATA_DEV__iso__no 0 | ||
| 6647 | #define R_USB_EPT_DATA_DEV__iso__yes 1 | ||
| 6648 | #define R_USB_EPT_DATA_DEV__port__BITNR 24 | ||
| 6649 | #define R_USB_EPT_DATA_DEV__port__WIDTH 2 | ||
| 6650 | #define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 | ||
| 6651 | #define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 | ||
| 6652 | #define R_USB_EPT_DATA_DEV__t__BITNR 21 | ||
| 6653 | #define R_USB_EPT_DATA_DEV__t__WIDTH 1 | ||
| 6654 | #define R_USB_EPT_DATA_DEV__max_len__BITNR 11 | ||
| 6655 | #define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 | ||
| 6656 | #define R_USB_EPT_DATA_DEV__ep__BITNR 7 | ||
| 6657 | #define R_USB_EPT_DATA_DEV__ep__WIDTH 4 | ||
| 6658 | #define R_USB_EPT_DATA_DEV__dev__BITNR 0 | ||
| 6659 | #define R_USB_EPT_DATA_DEV__dev__WIDTH 7 | ||
| 6660 | |||
| 6661 | #define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) | ||
| 6662 | #define R_USB_SNMP_TERROR__value__BITNR 0 | ||
| 6663 | #define R_USB_SNMP_TERROR__value__WIDTH 32 | ||
| 6664 | |||
| 6665 | #define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) | ||
| 6666 | #define R_USB_EPID_ATTN__value__BITNR 0 | ||
| 6667 | #define R_USB_EPID_ATTN__value__WIDTH 32 | ||
| 6668 | |||
| 6669 | #define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) | ||
| 6670 | #define R_USB_PORT1_DISABLE__disable__BITNR 0 | ||
| 6671 | #define R_USB_PORT1_DISABLE__disable__WIDTH 1 | ||
| 6672 | #define R_USB_PORT1_DISABLE__disable__yes 0 | ||
| 6673 | #define R_USB_PORT1_DISABLE__disable__no 1 | ||
| 6674 | |||
| 6675 | #define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) | ||
| 6676 | #define R_USB_PORT2_DISABLE__disable__BITNR 0 | ||
| 6677 | #define R_USB_PORT2_DISABLE__disable__WIDTH 1 | ||
| 6678 | #define R_USB_PORT2_DISABLE__disable__yes 0 | ||
| 6679 | #define R_USB_PORT2_DISABLE__disable__no 1 | ||
| 6680 | |||
| 6681 | /* | ||
| 6682 | !* MMU registers | ||
| 6683 | !*/ | ||
| 6684 | |||
| 6685 | #define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) | ||
| 6686 | #define R_MMU_CONFIG__mmu_enable__BITNR 31 | ||
| 6687 | #define R_MMU_CONFIG__mmu_enable__WIDTH 1 | ||
| 6688 | #define R_MMU_CONFIG__mmu_enable__enable 1 | ||
| 6689 | #define R_MMU_CONFIG__mmu_enable__disable 0 | ||
| 6690 | #define R_MMU_CONFIG__inv_excp__BITNR 18 | ||
| 6691 | #define R_MMU_CONFIG__inv_excp__WIDTH 1 | ||
| 6692 | #define R_MMU_CONFIG__inv_excp__enable 1 | ||
| 6693 | #define R_MMU_CONFIG__inv_excp__disable 0 | ||
| 6694 | #define R_MMU_CONFIG__acc_excp__BITNR 17 | ||
| 6695 | #define R_MMU_CONFIG__acc_excp__WIDTH 1 | ||
| 6696 | #define R_MMU_CONFIG__acc_excp__enable 1 | ||
| 6697 | #define R_MMU_CONFIG__acc_excp__disable 0 | ||
| 6698 | #define R_MMU_CONFIG__we_excp__BITNR 16 | ||
| 6699 | #define R_MMU_CONFIG__we_excp__WIDTH 1 | ||
| 6700 | #define R_MMU_CONFIG__we_excp__enable 1 | ||
| 6701 | #define R_MMU_CONFIG__we_excp__disable 0 | ||
| 6702 | #define R_MMU_CONFIG__seg_f__BITNR 15 | ||
| 6703 | #define R_MMU_CONFIG__seg_f__WIDTH 1 | ||
| 6704 | #define R_MMU_CONFIG__seg_f__seg 1 | ||
| 6705 | #define R_MMU_CONFIG__seg_f__page 0 | ||
| 6706 | #define R_MMU_CONFIG__seg_e__BITNR 14 | ||
| 6707 | #define R_MMU_CONFIG__seg_e__WIDTH 1 | ||
| 6708 | #define R_MMU_CONFIG__seg_e__seg 1 | ||
| 6709 | #define R_MMU_CONFIG__seg_e__page 0 | ||
| 6710 | #define R_MMU_CONFIG__seg_d__BITNR 13 | ||
| 6711 | #define R_MMU_CONFIG__seg_d__WIDTH 1 | ||
| 6712 | #define R_MMU_CONFIG__seg_d__seg 1 | ||
| 6713 | #define R_MMU_CONFIG__seg_d__page 0 | ||
| 6714 | #define R_MMU_CONFIG__seg_c__BITNR 12 | ||
| 6715 | #define R_MMU_CONFIG__seg_c__WIDTH 1 | ||
| 6716 | #define R_MMU_CONFIG__seg_c__seg 1 | ||
| 6717 | #define R_MMU_CONFIG__seg_c__page 0 | ||
| 6718 | #define R_MMU_CONFIG__seg_b__BITNR 11 | ||
| 6719 | #define R_MMU_CONFIG__seg_b__WIDTH 1 | ||
| 6720 | #define R_MMU_CONFIG__seg_b__seg 1 | ||
| 6721 | #define R_MMU_CONFIG__seg_b__page 0 | ||
| 6722 | #define R_MMU_CONFIG__seg_a__BITNR 10 | ||
| 6723 | #define R_MMU_CONFIG__seg_a__WIDTH 1 | ||
| 6724 | #define R_MMU_CONFIG__seg_a__seg 1 | ||
| 6725 | #define R_MMU_CONFIG__seg_a__page 0 | ||
| 6726 | #define R_MMU_CONFIG__seg_9__BITNR 9 | ||
| 6727 | #define R_MMU_CONFIG__seg_9__WIDTH 1 | ||
| 6728 | #define R_MMU_CONFIG__seg_9__seg 1 | ||
| 6729 | #define R_MMU_CONFIG__seg_9__page 0 | ||
| 6730 | #define R_MMU_CONFIG__seg_8__BITNR 8 | ||
| 6731 | #define R_MMU_CONFIG__seg_8__WIDTH 1 | ||
| 6732 | #define R_MMU_CONFIG__seg_8__seg 1 | ||
| 6733 | #define R_MMU_CONFIG__seg_8__page 0 | ||
| 6734 | #define R_MMU_CONFIG__seg_7__BITNR 7 | ||
| 6735 | #define R_MMU_CONFIG__seg_7__WIDTH 1 | ||
| 6736 | #define R_MMU_CONFIG__seg_7__seg 1 | ||
| 6737 | #define R_MMU_CONFIG__seg_7__page 0 | ||
| 6738 | #define R_MMU_CONFIG__seg_6__BITNR 6 | ||
| 6739 | #define R_MMU_CONFIG__seg_6__WIDTH 1 | ||
| 6740 | #define R_MMU_CONFIG__seg_6__seg 1 | ||
| 6741 | #define R_MMU_CONFIG__seg_6__page 0 | ||
| 6742 | #define R_MMU_CONFIG__seg_5__BITNR 5 | ||
| 6743 | #define R_MMU_CONFIG__seg_5__WIDTH 1 | ||
| 6744 | #define R_MMU_CONFIG__seg_5__seg 1 | ||
| 6745 | #define R_MMU_CONFIG__seg_5__page 0 | ||
| 6746 | #define R_MMU_CONFIG__seg_4__BITNR 4 | ||
| 6747 | #define R_MMU_CONFIG__seg_4__WIDTH 1 | ||
| 6748 | #define R_MMU_CONFIG__seg_4__seg 1 | ||
| 6749 | #define R_MMU_CONFIG__seg_4__page 0 | ||
| 6750 | #define R_MMU_CONFIG__seg_3__BITNR 3 | ||
| 6751 | #define R_MMU_CONFIG__seg_3__WIDTH 1 | ||
| 6752 | #define R_MMU_CONFIG__seg_3__seg 1 | ||
| 6753 | #define R_MMU_CONFIG__seg_3__page 0 | ||
| 6754 | #define R_MMU_CONFIG__seg_2__BITNR 2 | ||
| 6755 | #define R_MMU_CONFIG__seg_2__WIDTH 1 | ||
| 6756 | #define R_MMU_CONFIG__seg_2__seg 1 | ||
| 6757 | #define R_MMU_CONFIG__seg_2__page 0 | ||
| 6758 | #define R_MMU_CONFIG__seg_1__BITNR 1 | ||
| 6759 | #define R_MMU_CONFIG__seg_1__WIDTH 1 | ||
| 6760 | #define R_MMU_CONFIG__seg_1__seg 1 | ||
| 6761 | #define R_MMU_CONFIG__seg_1__page 0 | ||
| 6762 | #define R_MMU_CONFIG__seg_0__BITNR 0 | ||
| 6763 | #define R_MMU_CONFIG__seg_0__WIDTH 1 | ||
| 6764 | #define R_MMU_CONFIG__seg_0__seg 1 | ||
| 6765 | #define R_MMU_CONFIG__seg_0__page 0 | ||
| 6766 | |||
| 6767 | #define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) | ||
| 6768 | #define R_MMU_KSEG__seg_f__BITNR 15 | ||
| 6769 | #define R_MMU_KSEG__seg_f__WIDTH 1 | ||
| 6770 | #define R_MMU_KSEG__seg_f__seg 1 | ||
| 6771 | #define R_MMU_KSEG__seg_f__page 0 | ||
| 6772 | #define R_MMU_KSEG__seg_e__BITNR 14 | ||
| 6773 | #define R_MMU_KSEG__seg_e__WIDTH 1 | ||
| 6774 | #define R_MMU_KSEG__seg_e__seg 1 | ||
| 6775 | #define R_MMU_KSEG__seg_e__page 0 | ||
| 6776 | #define R_MMU_KSEG__seg_d__BITNR 13 | ||
| 6777 | #define R_MMU_KSEG__seg_d__WIDTH 1 | ||
| 6778 | #define R_MMU_KSEG__seg_d__seg 1 | ||
| 6779 | #define R_MMU_KSEG__seg_d__page 0 | ||
| 6780 | #define R_MMU_KSEG__seg_c__BITNR 12 | ||
| 6781 | #define R_MMU_KSEG__seg_c__WIDTH 1 | ||
| 6782 | #define R_MMU_KSEG__seg_c__seg 1 | ||
| 6783 | #define R_MMU_KSEG__seg_c__page 0 | ||
| 6784 | #define R_MMU_KSEG__seg_b__BITNR 11 | ||
| 6785 | #define R_MMU_KSEG__seg_b__WIDTH 1 | ||
| 6786 | #define R_MMU_KSEG__seg_b__seg 1 | ||
| 6787 | #define R_MMU_KSEG__seg_b__page 0 | ||
| 6788 | #define R_MMU_KSEG__seg_a__BITNR 10 | ||
| 6789 | #define R_MMU_KSEG__seg_a__WIDTH 1 | ||
| 6790 | #define R_MMU_KSEG__seg_a__seg 1 | ||
| 6791 | #define R_MMU_KSEG__seg_a__page 0 | ||
| 6792 | #define R_MMU_KSEG__seg_9__BITNR 9 | ||
| 6793 | #define R_MMU_KSEG__seg_9__WIDTH 1 | ||
| 6794 | #define R_MMU_KSEG__seg_9__seg 1 | ||
| 6795 | #define R_MMU_KSEG__seg_9__page 0 | ||
| 6796 | #define R_MMU_KSEG__seg_8__BITNR 8 | ||
| 6797 | #define R_MMU_KSEG__seg_8__WIDTH 1 | ||
| 6798 | #define R_MMU_KSEG__seg_8__seg 1 | ||
| 6799 | #define R_MMU_KSEG__seg_8__page 0 | ||
| 6800 | #define R_MMU_KSEG__seg_7__BITNR 7 | ||
| 6801 | #define R_MMU_KSEG__seg_7__WIDTH 1 | ||
| 6802 | #define R_MMU_KSEG__seg_7__seg 1 | ||
| 6803 | #define R_MMU_KSEG__seg_7__page 0 | ||
| 6804 | #define R_MMU_KSEG__seg_6__BITNR 6 | ||
| 6805 | #define R_MMU_KSEG__seg_6__WIDTH 1 | ||
| 6806 | #define R_MMU_KSEG__seg_6__seg 1 | ||
| 6807 | #define R_MMU_KSEG__seg_6__page 0 | ||
| 6808 | #define R_MMU_KSEG__seg_5__BITNR 5 | ||
| 6809 | #define R_MMU_KSEG__seg_5__WIDTH 1 | ||
| 6810 | #define R_MMU_KSEG__seg_5__seg 1 | ||
| 6811 | #define R_MMU_KSEG__seg_5__page 0 | ||
| 6812 | #define R_MMU_KSEG__seg_4__BITNR 4 | ||
| 6813 | #define R_MMU_KSEG__seg_4__WIDTH 1 | ||
| 6814 | #define R_MMU_KSEG__seg_4__seg 1 | ||
| 6815 | #define R_MMU_KSEG__seg_4__page 0 | ||
| 6816 | #define R_MMU_KSEG__seg_3__BITNR 3 | ||
| 6817 | #define R_MMU_KSEG__seg_3__WIDTH 1 | ||
| 6818 | #define R_MMU_KSEG__seg_3__seg 1 | ||
| 6819 | #define R_MMU_KSEG__seg_3__page 0 | ||
| 6820 | #define R_MMU_KSEG__seg_2__BITNR 2 | ||
| 6821 | #define R_MMU_KSEG__seg_2__WIDTH 1 | ||
| 6822 | #define R_MMU_KSEG__seg_2__seg 1 | ||
| 6823 | #define R_MMU_KSEG__seg_2__page 0 | ||
| 6824 | #define R_MMU_KSEG__seg_1__BITNR 1 | ||
| 6825 | #define R_MMU_KSEG__seg_1__WIDTH 1 | ||
| 6826 | #define R_MMU_KSEG__seg_1__seg 1 | ||
| 6827 | #define R_MMU_KSEG__seg_1__page 0 | ||
| 6828 | #define R_MMU_KSEG__seg_0__BITNR 0 | ||
| 6829 | #define R_MMU_KSEG__seg_0__WIDTH 1 | ||
| 6830 | #define R_MMU_KSEG__seg_0__seg 1 | ||
| 6831 | #define R_MMU_KSEG__seg_0__page 0 | ||
| 6832 | |||
| 6833 | #define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) | ||
| 6834 | #define R_MMU_CTRL__inv_excp__BITNR 2 | ||
| 6835 | #define R_MMU_CTRL__inv_excp__WIDTH 1 | ||
| 6836 | #define R_MMU_CTRL__inv_excp__enable 1 | ||
| 6837 | #define R_MMU_CTRL__inv_excp__disable 0 | ||
| 6838 | #define R_MMU_CTRL__acc_excp__BITNR 1 | ||
| 6839 | #define R_MMU_CTRL__acc_excp__WIDTH 1 | ||
| 6840 | #define R_MMU_CTRL__acc_excp__enable 1 | ||
| 6841 | #define R_MMU_CTRL__acc_excp__disable 0 | ||
| 6842 | #define R_MMU_CTRL__we_excp__BITNR 0 | ||
| 6843 | #define R_MMU_CTRL__we_excp__WIDTH 1 | ||
| 6844 | #define R_MMU_CTRL__we_excp__enable 1 | ||
| 6845 | #define R_MMU_CTRL__we_excp__disable 0 | ||
| 6846 | |||
| 6847 | #define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) | ||
| 6848 | #define R_MMU_ENABLE__mmu_enable__BITNR 7 | ||
| 6849 | #define R_MMU_ENABLE__mmu_enable__WIDTH 1 | ||
| 6850 | #define R_MMU_ENABLE__mmu_enable__enable 1 | ||
| 6851 | #define R_MMU_ENABLE__mmu_enable__disable 0 | ||
| 6852 | |||
| 6853 | #define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) | ||
| 6854 | #define R_MMU_KBASE_LO__base_7__BITNR 28 | ||
| 6855 | #define R_MMU_KBASE_LO__base_7__WIDTH 4 | ||
| 6856 | #define R_MMU_KBASE_LO__base_6__BITNR 24 | ||
| 6857 | #define R_MMU_KBASE_LO__base_6__WIDTH 4 | ||
| 6858 | #define R_MMU_KBASE_LO__base_5__BITNR 20 | ||
| 6859 | #define R_MMU_KBASE_LO__base_5__WIDTH 4 | ||
| 6860 | #define R_MMU_KBASE_LO__base_4__BITNR 16 | ||
| 6861 | #define R_MMU_KBASE_LO__base_4__WIDTH 4 | ||
| 6862 | #define R_MMU_KBASE_LO__base_3__BITNR 12 | ||
| 6863 | #define R_MMU_KBASE_LO__base_3__WIDTH 4 | ||
| 6864 | #define R_MMU_KBASE_LO__base_2__BITNR 8 | ||
| 6865 | #define R_MMU_KBASE_LO__base_2__WIDTH 4 | ||
| 6866 | #define R_MMU_KBASE_LO__base_1__BITNR 4 | ||
| 6867 | #define R_MMU_KBASE_LO__base_1__WIDTH 4 | ||
| 6868 | #define R_MMU_KBASE_LO__base_0__BITNR 0 | ||
| 6869 | #define R_MMU_KBASE_LO__base_0__WIDTH 4 | ||
| 6870 | |||
| 6871 | #define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) | ||
| 6872 | #define R_MMU_KBASE_HI__base_f__BITNR 28 | ||
| 6873 | #define R_MMU_KBASE_HI__base_f__WIDTH 4 | ||
| 6874 | #define R_MMU_KBASE_HI__base_e__BITNR 24 | ||
| 6875 | #define R_MMU_KBASE_HI__base_e__WIDTH 4 | ||
| 6876 | #define R_MMU_KBASE_HI__base_d__BITNR 20 | ||
| 6877 | #define R_MMU_KBASE_HI__base_d__WIDTH 4 | ||
| 6878 | #define R_MMU_KBASE_HI__base_c__BITNR 16 | ||
| 6879 | #define R_MMU_KBASE_HI__base_c__WIDTH 4 | ||
| 6880 | #define R_MMU_KBASE_HI__base_b__BITNR 12 | ||
| 6881 | #define R_MMU_KBASE_HI__base_b__WIDTH 4 | ||
| 6882 | #define R_MMU_KBASE_HI__base_a__BITNR 8 | ||
| 6883 | #define R_MMU_KBASE_HI__base_a__WIDTH 4 | ||
| 6884 | #define R_MMU_KBASE_HI__base_9__BITNR 4 | ||
| 6885 | #define R_MMU_KBASE_HI__base_9__WIDTH 4 | ||
| 6886 | #define R_MMU_KBASE_HI__base_8__BITNR 0 | ||
| 6887 | #define R_MMU_KBASE_HI__base_8__WIDTH 4 | ||
| 6888 | |||
| 6889 | #define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) | ||
| 6890 | #define R_MMU_CONTEXT__page_id__BITNR 0 | ||
| 6891 | #define R_MMU_CONTEXT__page_id__WIDTH 6 | ||
| 6892 | |||
| 6893 | #define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) | ||
| 6894 | #define R_MMU_CAUSE__vpn__BITNR 13 | ||
| 6895 | #define R_MMU_CAUSE__vpn__WIDTH 19 | ||
| 6896 | #define R_MMU_CAUSE__miss_excp__BITNR 12 | ||
| 6897 | #define R_MMU_CAUSE__miss_excp__WIDTH 1 | ||
| 6898 | #define R_MMU_CAUSE__miss_excp__yes 1 | ||
| 6899 | #define R_MMU_CAUSE__miss_excp__no 0 | ||
| 6900 | #define R_MMU_CAUSE__inv_excp__BITNR 11 | ||
| 6901 | #define R_MMU_CAUSE__inv_excp__WIDTH 1 | ||
| 6902 | #define R_MMU_CAUSE__inv_excp__yes 1 | ||
| 6903 | #define R_MMU_CAUSE__inv_excp__no 0 | ||
| 6904 | #define R_MMU_CAUSE__acc_excp__BITNR 10 | ||
| 6905 | #define R_MMU_CAUSE__acc_excp__WIDTH 1 | ||
| 6906 | #define R_MMU_CAUSE__acc_excp__yes 1 | ||
| 6907 | #define R_MMU_CAUSE__acc_excp__no 0 | ||
| 6908 | #define R_MMU_CAUSE__we_excp__BITNR 9 | ||
| 6909 | #define R_MMU_CAUSE__we_excp__WIDTH 1 | ||
| 6910 | #define R_MMU_CAUSE__we_excp__yes 1 | ||
| 6911 | #define R_MMU_CAUSE__we_excp__no 0 | ||
| 6912 | #define R_MMU_CAUSE__wr_rd__BITNR 8 | ||
| 6913 | #define R_MMU_CAUSE__wr_rd__WIDTH 1 | ||
| 6914 | #define R_MMU_CAUSE__wr_rd__write 1 | ||
| 6915 | #define R_MMU_CAUSE__wr_rd__read 0 | ||
| 6916 | #define R_MMU_CAUSE__page_id__BITNR 0 | ||
| 6917 | #define R_MMU_CAUSE__page_id__WIDTH 6 | ||
| 6918 | |||
| 6919 | #define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) | ||
| 6920 | #define R_TLB_SELECT__index__BITNR 0 | ||
| 6921 | #define R_TLB_SELECT__index__WIDTH 6 | ||
| 6922 | |||
| 6923 | #define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) | ||
| 6924 | #define R_TLB_LO__pfn__BITNR 13 | ||
| 6925 | #define R_TLB_LO__pfn__WIDTH 19 | ||
| 6926 | #define R_TLB_LO__global__BITNR 3 | ||
| 6927 | #define R_TLB_LO__global__WIDTH 1 | ||
| 6928 | #define R_TLB_LO__global__yes 1 | ||
| 6929 | #define R_TLB_LO__global__no 0 | ||
| 6930 | #define R_TLB_LO__valid__BITNR 2 | ||
| 6931 | #define R_TLB_LO__valid__WIDTH 1 | ||
| 6932 | #define R_TLB_LO__valid__yes 1 | ||
| 6933 | #define R_TLB_LO__valid__no 0 | ||
| 6934 | #define R_TLB_LO__kernel__BITNR 1 | ||
| 6935 | #define R_TLB_LO__kernel__WIDTH 1 | ||
| 6936 | #define R_TLB_LO__kernel__yes 1 | ||
| 6937 | #define R_TLB_LO__kernel__no 0 | ||
| 6938 | #define R_TLB_LO__we__BITNR 0 | ||
| 6939 | #define R_TLB_LO__we__WIDTH 1 | ||
| 6940 | #define R_TLB_LO__we__yes 1 | ||
| 6941 | #define R_TLB_LO__we__no 0 | ||
| 6942 | |||
| 6943 | #define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) | ||
| 6944 | #define R_TLB_HI__vpn__BITNR 13 | ||
| 6945 | #define R_TLB_HI__vpn__WIDTH 19 | ||
| 6946 | #define R_TLB_HI__page_id__BITNR 0 | ||
| 6947 | #define R_TLB_HI__page_id__WIDTH 6 | ||
| 6948 | |||
| 6949 | /* | ||
| 6950 | !* Syncrounous serial port registers | ||
| 6951 | !*/ | ||
| 6952 | |||
| 6953 | #define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) | ||
| 6954 | #define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 | ||
| 6955 | #define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 | ||
| 6956 | |||
| 6957 | #define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) | ||
| 6958 | #define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 | ||
| 6959 | #define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 | ||
| 6960 | |||
| 6961 | #define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) | ||
| 6962 | #define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 | ||
| 6963 | #define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 | ||
| 6964 | |||
| 6965 | #define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) | ||
| 6966 | #define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 | ||
| 6967 | #define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 | ||
| 6968 | #define R_SYNC_SERIAL1_STATUS__rec_status__running 0 | ||
| 6969 | #define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 | ||
| 6970 | #define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 | ||
| 6971 | #define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 | ||
| 6972 | #define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 | ||
| 6973 | #define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 | ||
| 6974 | #define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 | ||
| 6975 | #define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 | ||
| 6976 | #define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 | ||
| 6977 | #define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 | ||
| 6978 | #define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 | ||
| 6979 | #define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 | ||
| 6980 | #define R_SYNC_SERIAL1_STATUS__pin_1__low 0 | ||
| 6981 | #define R_SYNC_SERIAL1_STATUS__pin_1__high 1 | ||
| 6982 | #define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 | ||
| 6983 | #define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 | ||
| 6984 | #define R_SYNC_SERIAL1_STATUS__pin_0__low 0 | ||
| 6985 | #define R_SYNC_SERIAL1_STATUS__pin_0__high 1 | ||
| 6986 | #define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 | ||
| 6987 | #define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 | ||
| 6988 | #define R_SYNC_SERIAL1_STATUS__underflow__no 0 | ||
| 6989 | #define R_SYNC_SERIAL1_STATUS__underflow__yes 1 | ||
| 6990 | #define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 | ||
| 6991 | #define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 | ||
| 6992 | #define R_SYNC_SERIAL1_STATUS__overrun__no 0 | ||
| 6993 | #define R_SYNC_SERIAL1_STATUS__overrun__yes 1 | ||
| 6994 | #define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 | ||
| 6995 | #define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 | ||
| 6996 | #define R_SYNC_SERIAL1_STATUS__data_avail__no 0 | ||
| 6997 | #define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 | ||
| 6998 | #define R_SYNC_SERIAL1_STATUS__data__BITNR 0 | ||
| 6999 | #define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 | ||
| 7000 | |||
| 7001 | #define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) | ||
| 7002 | #define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 | ||
| 7003 | #define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 | ||
| 7004 | |||
| 7005 | #define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) | ||
| 7006 | #define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 | ||
| 7007 | #define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 | ||
| 7008 | |||
| 7009 | #define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) | ||
| 7010 | #define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 | ||
| 7011 | #define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 | ||
| 7012 | |||
| 7013 | #define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) | ||
| 7014 | #define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 | ||
| 7015 | #define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 | ||
| 7016 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 | ||
| 7017 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 | ||
| 7018 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 | ||
| 7019 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 | ||
| 7020 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 | ||
| 7021 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 | ||
| 7022 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 | ||
| 7023 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 | ||
| 7024 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 | ||
| 7025 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 | ||
| 7026 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 | ||
| 7027 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 | ||
| 7028 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 | ||
| 7029 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 | ||
| 7030 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 | ||
| 7031 | #define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 | ||
| 7032 | #define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 | ||
| 7033 | #define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 | ||
| 7034 | #define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 | ||
| 7035 | #define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 | ||
| 7036 | #define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 | ||
| 7037 | #define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 | ||
| 7038 | #define R_SYNC_SERIAL1_CTRL__mode__master_output 0 | ||
| 7039 | #define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 | ||
| 7040 | #define R_SYNC_SERIAL1_CTRL__mode__master_input 2 | ||
| 7041 | #define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 | ||
| 7042 | #define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 | ||
| 7043 | #define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 | ||
| 7044 | #define R_SYNC_SERIAL1_CTRL__error__BITNR 23 | ||
| 7045 | #define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 | ||
| 7046 | #define R_SYNC_SERIAL1_CTRL__error__normal 0 | ||
| 7047 | #define R_SYNC_SERIAL1_CTRL__error__ignore 1 | ||
| 7048 | #define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 | ||
| 7049 | #define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 | ||
| 7050 | #define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 | ||
| 7051 | #define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 | ||
| 7052 | #define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 | ||
| 7053 | #define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 | ||
| 7054 | #define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 | ||
| 7055 | #define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 | ||
| 7056 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 | ||
| 7057 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 | ||
| 7058 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 | ||
| 7059 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 | ||
| 7060 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 | ||
| 7061 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 | ||
| 7062 | #define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 | ||
| 7063 | #define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 | ||
| 7064 | #define R_SYNC_SERIAL1_CTRL__f_sync__on 0 | ||
| 7065 | #define R_SYNC_SERIAL1_CTRL__f_sync__off 1 | ||
| 7066 | #define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 | ||
| 7067 | #define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 | ||
| 7068 | #define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 | ||
| 7069 | #define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 | ||
| 7070 | #define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 | ||
| 7071 | #define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 | ||
| 7072 | #define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 | ||
| 7073 | #define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 | ||
| 7074 | #define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 | ||
| 7075 | #define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 | ||
| 7076 | #define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 | ||
| 7077 | #define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 | ||
| 7078 | #define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 | ||
| 7079 | #define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 | ||
| 7080 | #define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 | ||
| 7081 | #define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 | ||
| 7082 | #define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 | ||
| 7083 | #define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 | ||
| 7084 | #define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 | ||
| 7085 | #define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 | ||
| 7086 | #define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 | ||
| 7087 | #define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 | ||
| 7088 | #define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 | ||
| 7089 | #define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 | ||
| 7090 | #define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 | ||
| 7091 | #define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 | ||
| 7092 | #define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 | ||
| 7093 | #define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 | ||
| 7094 | #define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 | ||
| 7095 | #define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 | ||
| 7096 | #define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 | ||
| 7097 | #define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 | ||
| 7098 | #define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 | ||
| 7099 | #define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 | ||
| 7100 | #define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 | ||
| 7101 | #define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 | ||
| 7102 | #define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 | ||
| 7103 | #define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 | ||
| 7104 | #define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 | ||
| 7105 | #define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 | ||
| 7106 | #define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 | ||
| 7107 | #define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 | ||
| 7108 | #define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 | ||
| 7109 | #define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 | ||
| 7110 | #define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 | ||
| 7111 | #define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 | ||
| 7112 | #define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 | ||
| 7113 | #define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 | ||
| 7114 | #define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 | ||
| 7115 | #define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 | ||
| 7116 | #define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 | ||
| 7117 | #define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 | ||
| 7118 | #define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 | ||
| 7119 | #define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 | ||
| 7120 | #define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 | ||
| 7121 | #define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 | ||
| 7122 | #define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 | ||
| 7123 | #define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 | ||
| 7124 | #define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 | ||
| 7125 | #define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 | ||
| 7126 | #define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 | ||
| 7127 | #define R_SYNC_SERIAL1_CTRL__def_out0__high 1 | ||
| 7128 | #define R_SYNC_SERIAL1_CTRL__def_out0__low 0 | ||
| 7129 | |||
| 7130 | #define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) | ||
| 7131 | #define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 | ||
| 7132 | #define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 | ||
| 7133 | |||
| 7134 | #define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) | ||
| 7135 | #define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 | ||
| 7136 | #define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 | ||
| 7137 | |||
| 7138 | #define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) | ||
| 7139 | #define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 | ||
| 7140 | #define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 | ||
| 7141 | |||
| 7142 | #define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) | ||
| 7143 | #define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 | ||
| 7144 | #define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 | ||
| 7145 | #define R_SYNC_SERIAL3_STATUS__rec_status__running 0 | ||
| 7146 | #define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 | ||
| 7147 | #define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 | ||
| 7148 | #define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 | ||
| 7149 | #define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 | ||
| 7150 | #define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 | ||
| 7151 | #define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 | ||
| 7152 | #define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 | ||
| 7153 | #define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 | ||
| 7154 | #define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 | ||
| 7155 | #define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 | ||
| 7156 | #define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 | ||
| 7157 | #define R_SYNC_SERIAL3_STATUS__pin_1__low 0 | ||
| 7158 | #define R_SYNC_SERIAL3_STATUS__pin_1__high 1 | ||
| 7159 | #define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 | ||
| 7160 | #define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 | ||
| 7161 | #define R_SYNC_SERIAL3_STATUS__pin_0__low 0 | ||
| 7162 | #define R_SYNC_SERIAL3_STATUS__pin_0__high 1 | ||
| 7163 | #define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 | ||
| 7164 | #define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 | ||
| 7165 | #define R_SYNC_SERIAL3_STATUS__underflow__no 0 | ||
| 7166 | #define R_SYNC_SERIAL3_STATUS__underflow__yes 1 | ||
| 7167 | #define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 | ||
| 7168 | #define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 | ||
| 7169 | #define R_SYNC_SERIAL3_STATUS__overrun__no 0 | ||
| 7170 | #define R_SYNC_SERIAL3_STATUS__overrun__yes 1 | ||
| 7171 | #define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 | ||
| 7172 | #define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 | ||
| 7173 | #define R_SYNC_SERIAL3_STATUS__data_avail__no 0 | ||
| 7174 | #define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 | ||
| 7175 | #define R_SYNC_SERIAL3_STATUS__data__BITNR 0 | ||
| 7176 | #define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 | ||
| 7177 | |||
| 7178 | #define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) | ||
| 7179 | #define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 | ||
| 7180 | #define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 | ||
| 7181 | |||
| 7182 | #define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) | ||
| 7183 | #define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 | ||
| 7184 | #define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 | ||
| 7185 | |||
| 7186 | #define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) | ||
| 7187 | #define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 | ||
| 7188 | #define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 | ||
| 7189 | |||
| 7190 | #define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) | ||
| 7191 | #define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 | ||
| 7192 | #define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 | ||
| 7193 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 | ||
| 7194 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 | ||
| 7195 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 | ||
| 7196 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 | ||
| 7197 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 | ||
| 7198 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 | ||
| 7199 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 | ||
| 7200 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 | ||
| 7201 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 | ||
| 7202 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 | ||
| 7203 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 | ||
| 7204 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 | ||
| 7205 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 | ||
| 7206 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 | ||
| 7207 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 | ||
| 7208 | #define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 | ||
| 7209 | #define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 | ||
| 7210 | #define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 | ||
| 7211 | #define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 | ||
| 7212 | #define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 | ||
| 7213 | #define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 | ||
| 7214 | #define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 | ||
| 7215 | #define R_SYNC_SERIAL3_CTRL__mode__master_output 0 | ||
| 7216 | #define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 | ||
| 7217 | #define R_SYNC_SERIAL3_CTRL__mode__master_input 2 | ||
| 7218 | #define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 | ||
| 7219 | #define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 | ||
| 7220 | #define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 | ||
| 7221 | #define R_SYNC_SERIAL3_CTRL__error__BITNR 23 | ||
| 7222 | #define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 | ||
| 7223 | #define R_SYNC_SERIAL3_CTRL__error__normal 0 | ||
| 7224 | #define R_SYNC_SERIAL3_CTRL__error__ignore 1 | ||
| 7225 | #define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 | ||
| 7226 | #define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 | ||
| 7227 | #define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 | ||
| 7228 | #define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 | ||
| 7229 | #define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 | ||
| 7230 | #define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 | ||
| 7231 | #define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 | ||
| 7232 | #define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 | ||
| 7233 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 | ||
| 7234 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 | ||
| 7235 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 | ||
| 7236 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 | ||
| 7237 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 | ||
| 7238 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 | ||
| 7239 | #define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 | ||
| 7240 | #define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 | ||
| 7241 | #define R_SYNC_SERIAL3_CTRL__f_sync__on 0 | ||
| 7242 | #define R_SYNC_SERIAL3_CTRL__f_sync__off 1 | ||
| 7243 | #define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 | ||
| 7244 | #define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 | ||
| 7245 | #define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 | ||
| 7246 | #define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 | ||
| 7247 | #define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 | ||
| 7248 | #define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 | ||
| 7249 | #define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 | ||
| 7250 | #define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 | ||
| 7251 | #define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 | ||
| 7252 | #define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 | ||
| 7253 | #define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 | ||
| 7254 | #define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 | ||
| 7255 | #define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 | ||
| 7256 | #define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 | ||
| 7257 | #define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 | ||
| 7258 | #define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 | ||
| 7259 | #define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 | ||
| 7260 | #define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 | ||
| 7261 | #define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 | ||
| 7262 | #define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 | ||
| 7263 | #define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 | ||
| 7264 | #define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 | ||
| 7265 | #define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 | ||
| 7266 | #define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 | ||
| 7267 | #define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 | ||
| 7268 | #define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 | ||
| 7269 | #define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 | ||
| 7270 | #define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 | ||
| 7271 | #define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 | ||
| 7272 | #define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 | ||
| 7273 | #define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 | ||
| 7274 | #define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 | ||
| 7275 | #define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 | ||
| 7276 | #define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 | ||
| 7277 | #define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 | ||
| 7278 | #define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 | ||
| 7279 | #define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 | ||
| 7280 | #define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 | ||
| 7281 | #define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 | ||
| 7282 | #define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 | ||
| 7283 | #define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 | ||
| 7284 | #define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 | ||
| 7285 | #define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 | ||
| 7286 | #define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 | ||
| 7287 | #define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 | ||
| 7288 | #define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 | ||
| 7289 | #define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 | ||
| 7290 | #define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 | ||
| 7291 | #define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 | ||
| 7292 | #define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 | ||
| 7293 | #define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 | ||
| 7294 | #define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 | ||
| 7295 | #define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 | ||
| 7296 | #define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 | ||
| 7297 | #define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 | ||
| 7298 | #define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 | ||
| 7299 | #define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 | ||
| 7300 | #define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 | ||
| 7301 | #define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 | ||
| 7302 | #define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 | ||
| 7303 | #define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 | ||
| 7304 | #define R_SYNC_SERIAL3_CTRL__def_out0__high 1 | ||
| 7305 | #define R_SYNC_SERIAL3_CTRL__def_out0__low 0 | ||
| 7306 | |||
diff --git a/include/asm-cris/arch-v10/sv_addr_ag.h b/include/asm-cris/arch-v10/sv_addr_ag.h deleted file mode 100644 index e4a6b68b8982..000000000000 --- a/include/asm-cris/arch-v10/sv_addr_ag.h +++ /dev/null | |||
| @@ -1,139 +0,0 @@ | |||
| 1 | /*!************************************************************************** | ||
| 2 | *! | ||
| 3 | *! MACROS: | ||
| 4 | *! IO_MASK(reg,field) | ||
| 5 | *! IO_STATE(reg,field,state) | ||
| 6 | *! IO_EXTRACT(reg,field,val) | ||
| 7 | *! IO_STATE_VALUE(reg,field,state) | ||
| 8 | *! IO_BITNR(reg,field) | ||
| 9 | *! IO_WIDTH(reg,field) | ||
| 10 | *! IO_FIELD(reg,field,val) | ||
| 11 | *! IO_RD(reg) | ||
| 12 | *! All moderegister addresses and fields of these. | ||
| 13 | *! | ||
| 14 | *!**************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef __sv_addr_ag_h__ | ||
| 17 | #define __sv_addr_ag_h__ | ||
| 18 | |||
| 19 | |||
| 20 | #define __test_sv_addr__ 0 | ||
| 21 | |||
| 22 | /*------------------------------------------------------------ | ||
| 23 | !* General macros to manipulate moderegisters. | ||
| 24 | !*-----------------------------------------------------------*/ | ||
| 25 | |||
| 26 | /* IO_MASK returns a mask for a specified bitfield in a register. | ||
| 27 | Note that this macro doesn't work when field width is 32 bits. */ | ||
| 28 | #define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) | ||
| 29 | #define IO_MASK_(reg_, field_) \ | ||
| 30 | ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) | ||
| 31 | |||
| 32 | /* IO_STATE returns a constant corresponding to a one of the symbolic | ||
| 33 | states that the bitfield can have. (Shifted to correct position) */ | ||
| 34 | #define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) | ||
| 35 | #define IO_STATE_(reg_, field_, _state) \ | ||
| 36 | ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) | ||
| 37 | |||
| 38 | /* IO_EXTRACT returns the masked and shifted value corresponding to the | ||
| 39 | bitfield can have. */ | ||
| 40 | #define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) | ||
| 41 | #define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ | ||
| 42 | - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) | ||
| 43 | |||
| 44 | /* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic | ||
| 45 | states that the bitfield can have. (Not shifted) */ | ||
| 46 | #define IO_STATE_VALUE(reg, field, state) \ | ||
| 47 | IO_STATE_VALUE_ (reg##_, field##_, _##state) | ||
| 48 | #define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) | ||
| 49 | |||
| 50 | /* IO_FIELD shifts the val parameter to be aligned with the bitfield | ||
| 51 | specified. */ | ||
| 52 | #define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) | ||
| 53 | #define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) | ||
| 54 | |||
| 55 | /* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is | ||
| 56 | LSB and the returned bitnumber is LSB of the field. */ | ||
| 57 | #define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) | ||
| 58 | #define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) | ||
| 59 | |||
| 60 | /* IO_WIDTH returns the width, in bits, of a bitfield. */ | ||
| 61 | #define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) | ||
| 62 | #define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) | ||
| 63 | |||
| 64 | /*--- Obsolete. Kept for backw compatibility. ---*/ | ||
| 65 | /* Reads (or writes) a byte/uword/udword from the specified mode | ||
| 66 | register. */ | ||
| 67 | #define IO_RD(reg) (*(volatile u32*)(reg)) | ||
| 68 | #define IO_RD_B(reg) (*(volatile u8*)(reg)) | ||
| 69 | #define IO_RD_W(reg) (*(volatile u16*)(reg)) | ||
| 70 | #define IO_RD_D(reg) (*(volatile u32*)(reg)) | ||
| 71 | |||
| 72 | /*------------------------------------------------------------ | ||
| 73 | !* Start addresses of the different memory areas. | ||
| 74 | !*-----------------------------------------------------------*/ | ||
| 75 | |||
| 76 | #define MEM_CSE0_START (0x00000000) | ||
| 77 | #define MEM_CSE0_SIZE (0x04000000) | ||
| 78 | #define MEM_CSE1_START (0x04000000) | ||
| 79 | #define MEM_CSE1_SIZE (0x04000000) | ||
| 80 | #define MEM_CSR0_START (0x08000000) | ||
| 81 | #define MEM_CSR1_START (0x0c000000) | ||
| 82 | #define MEM_CSP0_START (0x10000000) | ||
| 83 | #define MEM_CSP1_START (0x14000000) | ||
| 84 | #define MEM_CSP2_START (0x18000000) | ||
| 85 | #define MEM_CSP3_START (0x1c000000) | ||
| 86 | #define MEM_CSP4_START (0x20000000) | ||
| 87 | #define MEM_CSP5_START (0x24000000) | ||
| 88 | #define MEM_CSP6_START (0x28000000) | ||
| 89 | #define MEM_CSP7_START (0x2c000000) | ||
| 90 | #define MEM_DRAM_START (0x40000000) | ||
| 91 | |||
| 92 | #define MEM_NON_CACHEABLE (0x80000000) | ||
| 93 | |||
| 94 | /*------------------------------------------------------------ | ||
| 95 | !* Type casts used in mode register macros, making pointer | ||
| 96 | !* dereferencing possible. Empty in assembler. | ||
| 97 | !*-----------------------------------------------------------*/ | ||
| 98 | |||
| 99 | #ifndef __ASSEMBLER__ | ||
| 100 | # define IO_TYPECAST_UDWORD (volatile u32*) | ||
| 101 | # define IO_TYPECAST_RO_UDWORD (const volatile u32*) | ||
| 102 | # define IO_TYPECAST_UWORD (volatile u16*) | ||
| 103 | # define IO_TYPECAST_RO_UWORD (const volatile u16*) | ||
| 104 | # define IO_TYPECAST_BYTE (volatile u8*) | ||
| 105 | # define IO_TYPECAST_RO_BYTE (const volatile u8*) | ||
| 106 | #else | ||
| 107 | # define IO_TYPECAST_UDWORD | ||
| 108 | # define IO_TYPECAST_RO_UDWORD | ||
| 109 | # define IO_TYPECAST_UWORD | ||
| 110 | # define IO_TYPECAST_RO_UWORD | ||
| 111 | # define IO_TYPECAST_BYTE | ||
| 112 | # define IO_TYPECAST_RO_BYTE | ||
| 113 | #endif | ||
| 114 | |||
| 115 | /*------------------------------------------------------------*/ | ||
| 116 | |||
| 117 | #include "sv_addr.agh" | ||
| 118 | |||
| 119 | #if __test_sv_addr__ | ||
| 120 | /* IO_MASK( R_BUS_CONFIG , CE ) */ | ||
| 121 | IO_MASK( R_WAITSTATES , SRAM_WS ) | ||
| 122 | IO_MASK( R_TEST , W32 ) | ||
| 123 | |||
| 124 | IO_STATE( R_BUS_CONFIG, CE, DISABLE ) | ||
| 125 | IO_STATE( R_BUS_CONFIG, CE, ENABLE ) | ||
| 126 | |||
| 127 | IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) | ||
| 128 | |||
| 129 | IO_MASK( R_DRAM_TIMING, REF ) | ||
| 130 | |||
| 131 | IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) | ||
| 132 | |||
| 133 | IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) | ||
| 134 | == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) | ||
| 135 | #endif | ||
| 136 | |||
| 137 | |||
| 138 | #endif /* ifndef __sv_addr_ag_h__ */ | ||
| 139 | |||
diff --git a/include/asm-cris/arch-v10/svinto.h b/include/asm-cris/arch-v10/svinto.h deleted file mode 100644 index 0881a1af7cee..000000000000 --- a/include/asm-cris/arch-v10/svinto.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_SVINTO_H | ||
| 2 | #define _ASM_CRIS_SVINTO_H | ||
| 3 | |||
| 4 | #include "sv_addr_ag.h" | ||
| 5 | |||
| 6 | extern unsigned int genconfig_shadow; /* defined and set in head.S */ | ||
| 7 | |||
| 8 | /* dma stuff */ | ||
| 9 | |||
| 10 | enum { /* Available in: */ | ||
| 11 | d_eol = (1 << 0), /* flags */ | ||
| 12 | d_eop = (1 << 1), /* flags & status */ | ||
| 13 | d_wait = (1 << 2), /* flags */ | ||
| 14 | d_int = (1 << 3), /* flags */ | ||
| 15 | d_txerr = (1 << 4), /* flags */ | ||
| 16 | d_stop = (1 << 4), /* status */ | ||
| 17 | d_ecp = (1 << 4), /* flags & status */ | ||
| 18 | d_pri = (1 << 5), /* flags & status */ | ||
| 19 | d_alignerr = (1 << 6), /* status */ | ||
| 20 | d_crcerr = (1 << 7) /* status */ | ||
| 21 | }; | ||
| 22 | |||
| 23 | /* Do remember that DMA does not go through the MMU and needs | ||
| 24 | * a real physical address, not an address virtually mapped or | ||
| 25 | * paged. Therefore the buf/next ptrs below are unsigned long instead | ||
| 26 | * of void * to give a warning if you try to put a pointer directly | ||
| 27 | * to them instead of going through virt_to_phys/phys_to_virt. | ||
| 28 | */ | ||
| 29 | |||
| 30 | typedef struct etrax_dma_descr { | ||
| 31 | unsigned short sw_len; /* 0-1 */ | ||
| 32 | unsigned short ctrl; /* 2-3 */ | ||
| 33 | unsigned long next; /* 4-7 */ | ||
| 34 | unsigned long buf; /* 8-11 */ | ||
| 35 | unsigned short hw_len; /* 12-13 */ | ||
| 36 | unsigned char status; /* 14 */ | ||
| 37 | unsigned char fifo_len; /* 15 */ | ||
| 38 | } etrax_dma_descr; | ||
| 39 | |||
| 40 | |||
| 41 | /* Use this for constant numbers only */ | ||
| 42 | #define RESET_DMA_NUM( n ) \ | ||
| 43 | *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) | ||
| 44 | |||
| 45 | /* Use this for constant numbers or symbols, | ||
| 46 | * having two macros makes it possible to use constant expressions. | ||
| 47 | */ | ||
| 48 | #define RESET_DMA( n ) RESET_DMA_NUM( n ) | ||
| 49 | |||
| 50 | |||
| 51 | /* Use this for constant numbers only */ | ||
| 52 | #define WAIT_DMA_NUM( n ) \ | ||
| 53 | while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ | ||
| 54 | IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) | ||
| 55 | |||
| 56 | /* Use this for constant numbers or symbols | ||
| 57 | * having two macros makes it possible to use constant expressions. | ||
| 58 | */ | ||
| 59 | #define WAIT_DMA( n ) WAIT_DMA_NUM( n ) | ||
| 60 | |||
| 61 | extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); | ||
| 62 | extern void flush_etrax_cache(void); | ||
| 63 | |||
| 64 | #endif | ||
diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h deleted file mode 100644 index 4a9cd36c9e16..000000000000 --- a/include/asm-cris/arch-v10/system.h +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_SYSTEM_H | ||
| 2 | #define __ASM_CRIS_ARCH_SYSTEM_H | ||
| 3 | |||
| 4 | |||
| 5 | /* read the CPU version register */ | ||
| 6 | |||
| 7 | static inline unsigned long rdvr(void) { | ||
| 8 | unsigned char vr; | ||
| 9 | __asm__ volatile ("move $vr,%0" : "=rm" (vr)); | ||
| 10 | return vr; | ||
| 11 | } | ||
| 12 | |||
| 13 | #define cris_machine_name "cris" | ||
| 14 | |||
| 15 | /* read/write the user-mode stackpointer */ | ||
| 16 | |||
| 17 | static inline unsigned long rdusp(void) { | ||
| 18 | unsigned long usp; | ||
| 19 | __asm__ __volatile__("move $usp,%0" : "=rm" (usp)); | ||
| 20 | return usp; | ||
| 21 | } | ||
| 22 | |||
| 23 | #define wrusp(usp) \ | ||
| 24 | __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp)) | ||
| 25 | |||
| 26 | /* read the current stackpointer */ | ||
| 27 | |||
| 28 | static inline unsigned long rdsp(void) { | ||
| 29 | unsigned long sp; | ||
| 30 | __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp)); | ||
| 31 | return sp; | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline unsigned long _get_base(char * addr) | ||
| 35 | { | ||
| 36 | return 0; | ||
| 37 | } | ||
| 38 | |||
| 39 | #define nop() __asm__ __volatile__ ("nop"); | ||
| 40 | |||
| 41 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | ||
| 42 | #define tas(ptr) (xchg((ptr),1)) | ||
| 43 | |||
| 44 | struct __xchg_dummy { unsigned long a[100]; }; | ||
| 45 | #define __xg(x) ((struct __xchg_dummy *)(x)) | ||
| 46 | |||
| 47 | /* interrupt control.. */ | ||
| 48 | #define local_save_flags(x) __asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory"); | ||
| 49 | #define local_irq_restore(x) __asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory"); | ||
| 50 | #define local_irq_disable() __asm__ __volatile__ ( "di" : : :"memory"); | ||
| 51 | #define local_irq_enable() __asm__ __volatile__ ( "ei" : : :"memory"); | ||
| 52 | |||
| 53 | #define irqs_disabled() \ | ||
| 54 | ({ \ | ||
| 55 | unsigned long flags; \ | ||
| 56 | local_save_flags(flags); \ | ||
| 57 | !(flags & (1<<5)); \ | ||
| 58 | }) | ||
| 59 | |||
| 60 | /* For spinlocks etc */ | ||
| 61 | #define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory"); | ||
| 62 | |||
| 63 | #endif | ||
diff --git a/include/asm-cris/arch-v10/thread_info.h b/include/asm-cris/arch-v10/thread_info.h deleted file mode 100644 index 218f4152d3e5..000000000000 --- a/include/asm-cris/arch-v10/thread_info.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_THREAD_INFO_H | ||
| 2 | #define _ASM_ARCH_THREAD_INFO_H | ||
| 3 | |||
| 4 | /* how to get the thread information struct from C */ | ||
| 5 | static inline struct thread_info *current_thread_info(void) | ||
| 6 | { | ||
| 7 | struct thread_info *ti; | ||
| 8 | __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL)); | ||
| 9 | return ti; | ||
| 10 | } | ||
| 11 | |||
| 12 | #endif | ||
diff --git a/include/asm-cris/arch-v10/timex.h b/include/asm-cris/arch-v10/timex.h deleted file mode 100644 index e48447d94faf..000000000000 --- a/include/asm-cris/arch-v10/timex.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Use prescale timer at 25000 Hz instead of the baudrate timer at | ||
| 3 | * 19200 to get rid of the 64ppm to fast timer (and we get better | ||
| 4 | * resolution within a jiffie as well. | ||
| 5 | */ | ||
| 6 | #ifndef _ASM_CRIS_ARCH_TIMEX_H | ||
| 7 | #define _ASM_CRIS_ARCH_TIMEX_H | ||
| 8 | |||
| 9 | /* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */ | ||
| 10 | /* If you change anything here you must check time.c as well... */ | ||
| 11 | #define PRESCALE_FREQ 25000000 | ||
| 12 | #define PRESCALE_VALUE 1000 | ||
| 13 | #define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */ | ||
| 14 | /* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/ | ||
| 15 | #define TIMER0_FREQ (CLOCK_TICK_RATE) | ||
| 16 | #define TIMER0_CLKSEL flexible | ||
| 17 | #define TIMER0_DIV (TIMER0_FREQ/(HZ)) | ||
| 18 | |||
| 19 | |||
| 20 | #define GET_JIFFIES_USEC() \ | ||
| 21 | ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV ) | ||
| 22 | |||
| 23 | unsigned long get_ns_in_jiffie(void); | ||
| 24 | |||
| 25 | static inline unsigned long get_us_in_jiffie_highres(void) | ||
| 26 | { | ||
| 27 | return get_ns_in_jiffie()/1000; | ||
| 28 | } | ||
| 29 | |||
| 30 | #endif | ||
diff --git a/include/asm-cris/arch-v10/tlb.h b/include/asm-cris/arch-v10/tlb.h deleted file mode 100644 index 31525bbe75c3..000000000000 --- a/include/asm-cris/arch-v10/tlb.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_TLB_H | ||
| 2 | #define _CRIS_ARCH_TLB_H | ||
| 3 | |||
| 4 | /* The TLB can host up to 64 different mm contexts at the same time. | ||
| 5 | * The last page_id is never running - it is used as an invalid page_id | ||
| 6 | * so we can make TLB entries that will never match. | ||
| 7 | */ | ||
| 8 | #define NUM_TLB_ENTRIES 64 | ||
| 9 | #define NUM_PAGEID 64 | ||
| 10 | #define INVALID_PAGEID 63 | ||
| 11 | #define NO_CONTEXT -1 | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/include/asm-cris/arch-v10/uaccess.h b/include/asm-cris/arch-v10/uaccess.h deleted file mode 100644 index 65b02d9b605a..000000000000 --- a/include/asm-cris/arch-v10/uaccess.h +++ /dev/null | |||
| @@ -1,660 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Authors: Bjorn Wesen (bjornw@axis.com) | ||
| 3 | * Hans-Peter Nilsson (hp@axis.com) | ||
| 4 | * | ||
| 5 | */ | ||
| 6 | #ifndef _CRIS_ARCH_UACCESS_H | ||
| 7 | #define _CRIS_ARCH_UACCESS_H | ||
| 8 | |||
| 9 | /* | ||
| 10 | * We don't tell gcc that we are accessing memory, but this is OK | ||
| 11 | * because we do not write to any memory gcc knows about, so there | ||
| 12 | * are no aliasing issues. | ||
| 13 | * | ||
| 14 | * Note that PC at a fault is the address *after* the faulting | ||
| 15 | * instruction. | ||
| 16 | */ | ||
| 17 | #define __put_user_asm(x, addr, err, op) \ | ||
| 18 | __asm__ __volatile__( \ | ||
| 19 | " "op" %1,[%2]\n" \ | ||
| 20 | "2:\n" \ | ||
| 21 | " .section .fixup,\"ax\"\n" \ | ||
| 22 | "3: move.d %3,%0\n" \ | ||
| 23 | " jump 2b\n" \ | ||
| 24 | " .previous\n" \ | ||
| 25 | " .section __ex_table,\"a\"\n" \ | ||
| 26 | " .dword 2b,3b\n" \ | ||
| 27 | " .previous\n" \ | ||
| 28 | : "=r" (err) \ | ||
| 29 | : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 30 | |||
| 31 | #define __put_user_asm_64(x, addr, err) \ | ||
| 32 | __asm__ __volatile__( \ | ||
| 33 | " move.d %M1,[%2]\n" \ | ||
| 34 | "2: move.d %H1,[%2+4]\n" \ | ||
| 35 | "4:\n" \ | ||
| 36 | " .section .fixup,\"ax\"\n" \ | ||
| 37 | "3: move.d %3,%0\n" \ | ||
| 38 | " jump 4b\n" \ | ||
| 39 | " .previous\n" \ | ||
| 40 | " .section __ex_table,\"a\"\n" \ | ||
| 41 | " .dword 2b,3b\n" \ | ||
| 42 | " .dword 4b,3b\n" \ | ||
| 43 | " .previous\n" \ | ||
| 44 | : "=r" (err) \ | ||
| 45 | : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 46 | |||
| 47 | /* See comment before __put_user_asm. */ | ||
| 48 | |||
| 49 | #define __get_user_asm(x, addr, err, op) \ | ||
| 50 | __asm__ __volatile__( \ | ||
| 51 | " "op" [%2],%1\n" \ | ||
| 52 | "2:\n" \ | ||
| 53 | " .section .fixup,\"ax\"\n" \ | ||
| 54 | "3: move.d %3,%0\n" \ | ||
| 55 | " moveq 0,%1\n" \ | ||
| 56 | " jump 2b\n" \ | ||
| 57 | " .previous\n" \ | ||
| 58 | " .section __ex_table,\"a\"\n" \ | ||
| 59 | " .dword 2b,3b\n" \ | ||
| 60 | " .previous\n" \ | ||
| 61 | : "=r" (err), "=r" (x) \ | ||
| 62 | : "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 63 | |||
| 64 | #define __get_user_asm_64(x, addr, err) \ | ||
| 65 | __asm__ __volatile__( \ | ||
| 66 | " move.d [%2],%M1\n" \ | ||
| 67 | "2: move.d [%2+4],%H1\n" \ | ||
| 68 | "4:\n" \ | ||
| 69 | " .section .fixup,\"ax\"\n" \ | ||
| 70 | "3: move.d %3,%0\n" \ | ||
| 71 | " moveq 0,%1\n" \ | ||
| 72 | " jump 4b\n" \ | ||
| 73 | " .previous\n" \ | ||
| 74 | " .section __ex_table,\"a\"\n" \ | ||
| 75 | " .dword 2b,3b\n" \ | ||
| 76 | " .dword 4b,3b\n" \ | ||
| 77 | " .previous\n" \ | ||
| 78 | : "=r" (err), "=r" (x) \ | ||
| 79 | : "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Copy a null terminated string from userspace. | ||
| 83 | * | ||
| 84 | * Must return: | ||
| 85 | * -EFAULT for an exception | ||
| 86 | * count if we hit the buffer limit | ||
| 87 | * bytes copied if we hit a null byte | ||
| 88 | * (without the null byte) | ||
| 89 | */ | ||
| 90 | static inline long | ||
| 91 | __do_strncpy_from_user(char *dst, const char *src, long count) | ||
| 92 | { | ||
| 93 | long res; | ||
| 94 | |||
| 95 | if (count == 0) | ||
| 96 | return 0; | ||
| 97 | |||
| 98 | /* | ||
| 99 | * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. | ||
| 100 | * So do we. | ||
| 101 | * | ||
| 102 | * This code is deduced from: | ||
| 103 | * | ||
| 104 | * char tmp2; | ||
| 105 | * long tmp1, tmp3 | ||
| 106 | * tmp1 = count; | ||
| 107 | * while ((*dst++ = (tmp2 = *src++)) != 0 | ||
| 108 | * && --tmp1) | ||
| 109 | * ; | ||
| 110 | * | ||
| 111 | * res = count - tmp1; | ||
| 112 | * | ||
| 113 | * with tweaks. | ||
| 114 | */ | ||
| 115 | |||
| 116 | __asm__ __volatile__ ( | ||
| 117 | " move.d %3,%0\n" | ||
| 118 | " move.b [%2+],$r9\n" | ||
| 119 | "1: beq 2f\n" | ||
| 120 | " move.b $r9,[%1+]\n" | ||
| 121 | |||
| 122 | " subq 1,%0\n" | ||
| 123 | " bne 1b\n" | ||
| 124 | " move.b [%2+],$r9\n" | ||
| 125 | |||
| 126 | "2: sub.d %3,%0\n" | ||
| 127 | " neg.d %0,%0\n" | ||
| 128 | "3:\n" | ||
| 129 | " .section .fixup,\"ax\"\n" | ||
| 130 | "4: move.d %7,%0\n" | ||
| 131 | " jump 3b\n" | ||
| 132 | |||
| 133 | /* There's one address for a fault at the first move, and | ||
| 134 | two possible PC values for a fault at the second move, | ||
| 135 | being a delay-slot filler. However, the branch-target | ||
| 136 | for the second move is the same as the first address. | ||
| 137 | Just so you don't get confused... */ | ||
| 138 | " .previous\n" | ||
| 139 | " .section __ex_table,\"a\"\n" | ||
| 140 | " .dword 1b,4b\n" | ||
| 141 | " .dword 2b,4b\n" | ||
| 142 | " .previous" | ||
| 143 | : "=r" (res), "=r" (dst), "=r" (src), "=r" (count) | ||
| 144 | : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) | ||
| 145 | : "r9"); | ||
| 146 | |||
| 147 | return res; | ||
| 148 | } | ||
| 149 | |||
| 150 | /* A few copy asms to build up the more complex ones from. | ||
| 151 | |||
| 152 | Note again, a post-increment is performed regardless of whether a bus | ||
| 153 | fault occurred in that instruction, and PC for a faulted insn is the | ||
| 154 | address *after* the insn. */ | ||
| 155 | |||
| 156 | #define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 157 | __asm__ __volatile__ ( \ | ||
| 158 | COPY \ | ||
| 159 | "1:\n" \ | ||
| 160 | " .section .fixup,\"ax\"\n" \ | ||
| 161 | FIXUP \ | ||
| 162 | " jump 1b\n" \ | ||
| 163 | " .previous\n" \ | ||
| 164 | " .section __ex_table,\"a\"\n" \ | ||
| 165 | TENTRY \ | ||
| 166 | " .previous\n" \ | ||
| 167 | : "=r" (to), "=r" (from), "=r" (ret) \ | ||
| 168 | : "0" (to), "1" (from), "2" (ret) \ | ||
| 169 | : "r9", "memory") | ||
| 170 | |||
| 171 | #define __asm_copy_from_user_1(to, from, ret) \ | ||
| 172 | __asm_copy_user_cont(to, from, ret, \ | ||
| 173 | " move.b [%1+],$r9\n" \ | ||
| 174 | "2: move.b $r9,[%0+]\n", \ | ||
| 175 | "3: addq 1,%2\n" \ | ||
| 176 | " clear.b [%0+]\n", \ | ||
| 177 | " .dword 2b,3b\n") | ||
| 178 | |||
| 179 | #define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 180 | __asm_copy_user_cont(to, from, ret, \ | ||
| 181 | " move.w [%1+],$r9\n" \ | ||
| 182 | "2: move.w $r9,[%0+]\n" COPY, \ | ||
| 183 | "3: addq 2,%2\n" \ | ||
| 184 | " clear.w [%0+]\n" FIXUP, \ | ||
| 185 | " .dword 2b,3b\n" TENTRY) | ||
| 186 | |||
| 187 | #define __asm_copy_from_user_2(to, from, ret) \ | ||
| 188 | __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") | ||
| 189 | |||
| 190 | #define __asm_copy_from_user_3(to, from, ret) \ | ||
| 191 | __asm_copy_from_user_2x_cont(to, from, ret, \ | ||
| 192 | " move.b [%1+],$r9\n" \ | ||
| 193 | "4: move.b $r9,[%0+]\n", \ | ||
| 194 | "5: addq 1,%2\n" \ | ||
| 195 | " clear.b [%0+]\n", \ | ||
| 196 | " .dword 4b,5b\n") | ||
| 197 | |||
| 198 | #define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 199 | __asm_copy_user_cont(to, from, ret, \ | ||
| 200 | " move.d [%1+],$r9\n" \ | ||
| 201 | "2: move.d $r9,[%0+]\n" COPY, \ | ||
| 202 | "3: addq 4,%2\n" \ | ||
| 203 | " clear.d [%0+]\n" FIXUP, \ | ||
| 204 | " .dword 2b,3b\n" TENTRY) | ||
| 205 | |||
| 206 | #define __asm_copy_from_user_4(to, from, ret) \ | ||
| 207 | __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") | ||
| 208 | |||
| 209 | #define __asm_copy_from_user_5(to, from, ret) \ | ||
| 210 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 211 | " move.b [%1+],$r9\n" \ | ||
| 212 | "4: move.b $r9,[%0+]\n", \ | ||
| 213 | "5: addq 1,%2\n" \ | ||
| 214 | " clear.b [%0+]\n", \ | ||
| 215 | " .dword 4b,5b\n") | ||
| 216 | |||
| 217 | #define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 218 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 219 | " move.w [%1+],$r9\n" \ | ||
| 220 | "4: move.w $r9,[%0+]\n" COPY, \ | ||
| 221 | "5: addq 2,%2\n" \ | ||
| 222 | " clear.w [%0+]\n" FIXUP, \ | ||
| 223 | " .dword 4b,5b\n" TENTRY) | ||
| 224 | |||
| 225 | #define __asm_copy_from_user_6(to, from, ret) \ | ||
| 226 | __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") | ||
| 227 | |||
| 228 | #define __asm_copy_from_user_7(to, from, ret) \ | ||
| 229 | __asm_copy_from_user_6x_cont(to, from, ret, \ | ||
| 230 | " move.b [%1+],$r9\n" \ | ||
| 231 | "6: move.b $r9,[%0+]\n", \ | ||
| 232 | "7: addq 1,%2\n" \ | ||
| 233 | " clear.b [%0+]\n", \ | ||
| 234 | " .dword 6b,7b\n") | ||
| 235 | |||
| 236 | #define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 237 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 238 | " move.d [%1+],$r9\n" \ | ||
| 239 | "4: move.d $r9,[%0+]\n" COPY, \ | ||
| 240 | "5: addq 4,%2\n" \ | ||
| 241 | " clear.d [%0+]\n" FIXUP, \ | ||
| 242 | " .dword 4b,5b\n" TENTRY) | ||
| 243 | |||
| 244 | #define __asm_copy_from_user_8(to, from, ret) \ | ||
| 245 | __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") | ||
| 246 | |||
| 247 | #define __asm_copy_from_user_9(to, from, ret) \ | ||
| 248 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 249 | " move.b [%1+],$r9\n" \ | ||
| 250 | "6: move.b $r9,[%0+]\n", \ | ||
| 251 | "7: addq 1,%2\n" \ | ||
| 252 | " clear.b [%0+]\n", \ | ||
| 253 | " .dword 6b,7b\n") | ||
| 254 | |||
| 255 | #define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 256 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 257 | " move.w [%1+],$r9\n" \ | ||
| 258 | "6: move.w $r9,[%0+]\n" COPY, \ | ||
| 259 | "7: addq 2,%2\n" \ | ||
| 260 | " clear.w [%0+]\n" FIXUP, \ | ||
| 261 | " .dword 6b,7b\n" TENTRY) | ||
| 262 | |||
| 263 | #define __asm_copy_from_user_10(to, from, ret) \ | ||
| 264 | __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") | ||
| 265 | |||
| 266 | #define __asm_copy_from_user_11(to, from, ret) \ | ||
| 267 | __asm_copy_from_user_10x_cont(to, from, ret, \ | ||
| 268 | " move.b [%1+],$r9\n" \ | ||
| 269 | "8: move.b $r9,[%0+]\n", \ | ||
| 270 | "9: addq 1,%2\n" \ | ||
| 271 | " clear.b [%0+]\n", \ | ||
| 272 | " .dword 8b,9b\n") | ||
| 273 | |||
| 274 | #define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 275 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 276 | " move.d [%1+],$r9\n" \ | ||
| 277 | "6: move.d $r9,[%0+]\n" COPY, \ | ||
| 278 | "7: addq 4,%2\n" \ | ||
| 279 | " clear.d [%0+]\n" FIXUP, \ | ||
| 280 | " .dword 6b,7b\n" TENTRY) | ||
| 281 | |||
| 282 | #define __asm_copy_from_user_12(to, from, ret) \ | ||
| 283 | __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") | ||
| 284 | |||
| 285 | #define __asm_copy_from_user_13(to, from, ret) \ | ||
| 286 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 287 | " move.b [%1+],$r9\n" \ | ||
| 288 | "8: move.b $r9,[%0+]\n", \ | ||
| 289 | "9: addq 1,%2\n" \ | ||
| 290 | " clear.b [%0+]\n", \ | ||
| 291 | " .dword 8b,9b\n") | ||
| 292 | |||
| 293 | #define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 294 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 295 | " move.w [%1+],$r9\n" \ | ||
| 296 | "8: move.w $r9,[%0+]\n" COPY, \ | ||
| 297 | "9: addq 2,%2\n" \ | ||
| 298 | " clear.w [%0+]\n" FIXUP, \ | ||
| 299 | " .dword 8b,9b\n" TENTRY) | ||
| 300 | |||
| 301 | #define __asm_copy_from_user_14(to, from, ret) \ | ||
| 302 | __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") | ||
| 303 | |||
| 304 | #define __asm_copy_from_user_15(to, from, ret) \ | ||
| 305 | __asm_copy_from_user_14x_cont(to, from, ret, \ | ||
| 306 | " move.b [%1+],$r9\n" \ | ||
| 307 | "10: move.b $r9,[%0+]\n", \ | ||
| 308 | "11: addq 1,%2\n" \ | ||
| 309 | " clear.b [%0+]\n", \ | ||
| 310 | " .dword 10b,11b\n") | ||
| 311 | |||
| 312 | #define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 313 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 314 | " move.d [%1+],$r9\n" \ | ||
| 315 | "8: move.d $r9,[%0+]\n" COPY, \ | ||
| 316 | "9: addq 4,%2\n" \ | ||
| 317 | " clear.d [%0+]\n" FIXUP, \ | ||
| 318 | " .dword 8b,9b\n" TENTRY) | ||
| 319 | |||
| 320 | #define __asm_copy_from_user_16(to, from, ret) \ | ||
| 321 | __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") | ||
| 322 | |||
| 323 | #define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 324 | __asm_copy_from_user_16x_cont(to, from, ret, \ | ||
| 325 | " move.d [%1+],$r9\n" \ | ||
| 326 | "10: move.d $r9,[%0+]\n" COPY, \ | ||
| 327 | "11: addq 4,%2\n" \ | ||
| 328 | " clear.d [%0+]\n" FIXUP, \ | ||
| 329 | " .dword 10b,11b\n" TENTRY) | ||
| 330 | |||
| 331 | #define __asm_copy_from_user_20(to, from, ret) \ | ||
| 332 | __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") | ||
| 333 | |||
| 334 | #define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 335 | __asm_copy_from_user_20x_cont(to, from, ret, \ | ||
| 336 | " move.d [%1+],$r9\n" \ | ||
| 337 | "12: move.d $r9,[%0+]\n" COPY, \ | ||
| 338 | "13: addq 4,%2\n" \ | ||
| 339 | " clear.d [%0+]\n" FIXUP, \ | ||
| 340 | " .dword 12b,13b\n" TENTRY) | ||
| 341 | |||
| 342 | #define __asm_copy_from_user_24(to, from, ret) \ | ||
| 343 | __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") | ||
| 344 | |||
| 345 | /* And now, the to-user ones. */ | ||
| 346 | |||
| 347 | #define __asm_copy_to_user_1(to, from, ret) \ | ||
| 348 | __asm_copy_user_cont(to, from, ret, \ | ||
| 349 | " move.b [%1+],$r9\n" \ | ||
| 350 | " move.b $r9,[%0+]\n2:\n", \ | ||
| 351 | "3: addq 1,%2\n", \ | ||
| 352 | " .dword 2b,3b\n") | ||
| 353 | |||
| 354 | #define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 355 | __asm_copy_user_cont(to, from, ret, \ | ||
| 356 | " move.w [%1+],$r9\n" \ | ||
| 357 | " move.w $r9,[%0+]\n2:\n" COPY, \ | ||
| 358 | "3: addq 2,%2\n" FIXUP, \ | ||
| 359 | " .dword 2b,3b\n" TENTRY) | ||
| 360 | |||
| 361 | #define __asm_copy_to_user_2(to, from, ret) \ | ||
| 362 | __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") | ||
| 363 | |||
| 364 | #define __asm_copy_to_user_3(to, from, ret) \ | ||
| 365 | __asm_copy_to_user_2x_cont(to, from, ret, \ | ||
| 366 | " move.b [%1+],$r9\n" \ | ||
| 367 | " move.b $r9,[%0+]\n4:\n", \ | ||
| 368 | "5: addq 1,%2\n", \ | ||
| 369 | " .dword 4b,5b\n") | ||
| 370 | |||
| 371 | #define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 372 | __asm_copy_user_cont(to, from, ret, \ | ||
| 373 | " move.d [%1+],$r9\n" \ | ||
| 374 | " move.d $r9,[%0+]\n2:\n" COPY, \ | ||
| 375 | "3: addq 4,%2\n" FIXUP, \ | ||
| 376 | " .dword 2b,3b\n" TENTRY) | ||
| 377 | |||
| 378 | #define __asm_copy_to_user_4(to, from, ret) \ | ||
| 379 | __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") | ||
| 380 | |||
| 381 | #define __asm_copy_to_user_5(to, from, ret) \ | ||
| 382 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 383 | " move.b [%1+],$r9\n" \ | ||
| 384 | " move.b $r9,[%0+]\n4:\n", \ | ||
| 385 | "5: addq 1,%2\n", \ | ||
| 386 | " .dword 4b,5b\n") | ||
| 387 | |||
| 388 | #define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 389 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 390 | " move.w [%1+],$r9\n" \ | ||
| 391 | " move.w $r9,[%0+]\n4:\n" COPY, \ | ||
| 392 | "5: addq 2,%2\n" FIXUP, \ | ||
| 393 | " .dword 4b,5b\n" TENTRY) | ||
| 394 | |||
| 395 | #define __asm_copy_to_user_6(to, from, ret) \ | ||
| 396 | __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") | ||
| 397 | |||
| 398 | #define __asm_copy_to_user_7(to, from, ret) \ | ||
| 399 | __asm_copy_to_user_6x_cont(to, from, ret, \ | ||
| 400 | " move.b [%1+],$r9\n" \ | ||
| 401 | " move.b $r9,[%0+]\n6:\n", \ | ||
| 402 | "7: addq 1,%2\n", \ | ||
| 403 | " .dword 6b,7b\n") | ||
| 404 | |||
| 405 | #define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 406 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 407 | " move.d [%1+],$r9\n" \ | ||
| 408 | " move.d $r9,[%0+]\n4:\n" COPY, \ | ||
| 409 | "5: addq 4,%2\n" FIXUP, \ | ||
| 410 | " .dword 4b,5b\n" TENTRY) | ||
| 411 | |||
| 412 | #define __asm_copy_to_user_8(to, from, ret) \ | ||
| 413 | __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") | ||
| 414 | |||
| 415 | #define __asm_copy_to_user_9(to, from, ret) \ | ||
| 416 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 417 | " move.b [%1+],$r9\n" \ | ||
| 418 | " move.b $r9,[%0+]\n6:\n", \ | ||
| 419 | "7: addq 1,%2\n", \ | ||
| 420 | " .dword 6b,7b\n") | ||
| 421 | |||
| 422 | #define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 423 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 424 | " move.w [%1+],$r9\n" \ | ||
| 425 | " move.w $r9,[%0+]\n6:\n" COPY, \ | ||
| 426 | "7: addq 2,%2\n" FIXUP, \ | ||
| 427 | " .dword 6b,7b\n" TENTRY) | ||
| 428 | |||
| 429 | #define __asm_copy_to_user_10(to, from, ret) \ | ||
| 430 | __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") | ||
| 431 | |||
| 432 | #define __asm_copy_to_user_11(to, from, ret) \ | ||
| 433 | __asm_copy_to_user_10x_cont(to, from, ret, \ | ||
| 434 | " move.b [%1+],$r9\n" \ | ||
| 435 | " move.b $r9,[%0+]\n8:\n", \ | ||
| 436 | "9: addq 1,%2\n", \ | ||
| 437 | " .dword 8b,9b\n") | ||
| 438 | |||
| 439 | #define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 440 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 441 | " move.d [%1+],$r9\n" \ | ||
| 442 | " move.d $r9,[%0+]\n6:\n" COPY, \ | ||
| 443 | "7: addq 4,%2\n" FIXUP, \ | ||
| 444 | " .dword 6b,7b\n" TENTRY) | ||
| 445 | |||
| 446 | #define __asm_copy_to_user_12(to, from, ret) \ | ||
| 447 | __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") | ||
| 448 | |||
| 449 | #define __asm_copy_to_user_13(to, from, ret) \ | ||
| 450 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 451 | " move.b [%1+],$r9\n" \ | ||
| 452 | " move.b $r9,[%0+]\n8:\n", \ | ||
| 453 | "9: addq 1,%2\n", \ | ||
| 454 | " .dword 8b,9b\n") | ||
| 455 | |||
| 456 | #define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 457 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 458 | " move.w [%1+],$r9\n" \ | ||
| 459 | " move.w $r9,[%0+]\n8:\n" COPY, \ | ||
| 460 | "9: addq 2,%2\n" FIXUP, \ | ||
| 461 | " .dword 8b,9b\n" TENTRY) | ||
| 462 | |||
| 463 | #define __asm_copy_to_user_14(to, from, ret) \ | ||
| 464 | __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") | ||
| 465 | |||
| 466 | #define __asm_copy_to_user_15(to, from, ret) \ | ||
| 467 | __asm_copy_to_user_14x_cont(to, from, ret, \ | ||
| 468 | " move.b [%1+],$r9\n" \ | ||
| 469 | " move.b $r9,[%0+]\n10:\n", \ | ||
| 470 | "11: addq 1,%2\n", \ | ||
| 471 | " .dword 10b,11b\n") | ||
| 472 | |||
| 473 | #define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 474 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 475 | " move.d [%1+],$r9\n" \ | ||
| 476 | " move.d $r9,[%0+]\n8:\n" COPY, \ | ||
| 477 | "9: addq 4,%2\n" FIXUP, \ | ||
| 478 | " .dword 8b,9b\n" TENTRY) | ||
| 479 | |||
| 480 | #define __asm_copy_to_user_16(to, from, ret) \ | ||
| 481 | __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") | ||
| 482 | |||
| 483 | #define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 484 | __asm_copy_to_user_16x_cont(to, from, ret, \ | ||
| 485 | " move.d [%1+],$r9\n" \ | ||
| 486 | " move.d $r9,[%0+]\n10:\n" COPY, \ | ||
| 487 | "11: addq 4,%2\n" FIXUP, \ | ||
| 488 | " .dword 10b,11b\n" TENTRY) | ||
| 489 | |||
| 490 | #define __asm_copy_to_user_20(to, from, ret) \ | ||
| 491 | __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") | ||
| 492 | |||
| 493 | #define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 494 | __asm_copy_to_user_20x_cont(to, from, ret, \ | ||
| 495 | " move.d [%1+],$r9\n" \ | ||
| 496 | " move.d $r9,[%0+]\n12:\n" COPY, \ | ||
| 497 | "13: addq 4,%2\n" FIXUP, \ | ||
| 498 | " .dword 12b,13b\n" TENTRY) | ||
| 499 | |||
| 500 | #define __asm_copy_to_user_24(to, from, ret) \ | ||
| 501 | __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") | ||
| 502 | |||
| 503 | /* Define a few clearing asms with exception handlers. */ | ||
| 504 | |||
| 505 | /* This frame-asm is like the __asm_copy_user_cont one, but has one less | ||
| 506 | input. */ | ||
| 507 | |||
| 508 | #define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 509 | __asm__ __volatile__ ( \ | ||
| 510 | CLEAR \ | ||
| 511 | "1:\n" \ | ||
| 512 | " .section .fixup,\"ax\"\n" \ | ||
| 513 | FIXUP \ | ||
| 514 | " jump 1b\n" \ | ||
| 515 | " .previous\n" \ | ||
| 516 | " .section __ex_table,\"a\"\n" \ | ||
| 517 | TENTRY \ | ||
| 518 | " .previous" \ | ||
| 519 | : "=r" (to), "=r" (ret) \ | ||
| 520 | : "0" (to), "1" (ret) \ | ||
| 521 | : "memory") | ||
| 522 | |||
| 523 | #define __asm_clear_1(to, ret) \ | ||
| 524 | __asm_clear(to, ret, \ | ||
| 525 | " clear.b [%0+]\n2:\n", \ | ||
| 526 | "3: addq 1,%1\n", \ | ||
| 527 | " .dword 2b,3b\n") | ||
| 528 | |||
| 529 | #define __asm_clear_2(to, ret) \ | ||
| 530 | __asm_clear(to, ret, \ | ||
| 531 | " clear.w [%0+]\n2:\n", \ | ||
| 532 | "3: addq 2,%1\n", \ | ||
| 533 | " .dword 2b,3b\n") | ||
| 534 | |||
| 535 | #define __asm_clear_3(to, ret) \ | ||
| 536 | __asm_clear(to, ret, \ | ||
| 537 | " clear.w [%0+]\n" \ | ||
| 538 | "2: clear.b [%0+]\n3:\n", \ | ||
| 539 | "4: addq 2,%1\n" \ | ||
| 540 | "5: addq 1,%1\n", \ | ||
| 541 | " .dword 2b,4b\n" \ | ||
| 542 | " .dword 3b,5b\n") | ||
| 543 | |||
| 544 | #define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 545 | __asm_clear(to, ret, \ | ||
| 546 | " clear.d [%0+]\n2:\n" CLEAR, \ | ||
| 547 | "3: addq 4,%1\n" FIXUP, \ | ||
| 548 | " .dword 2b,3b\n" TENTRY) | ||
| 549 | |||
| 550 | #define __asm_clear_4(to, ret) \ | ||
| 551 | __asm_clear_4x_cont(to, ret, "", "", "") | ||
| 552 | |||
| 553 | #define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 554 | __asm_clear_4x_cont(to, ret, \ | ||
| 555 | " clear.d [%0+]\n4:\n" CLEAR, \ | ||
| 556 | "5: addq 4,%1\n" FIXUP, \ | ||
| 557 | " .dword 4b,5b\n" TENTRY) | ||
| 558 | |||
| 559 | #define __asm_clear_8(to, ret) \ | ||
| 560 | __asm_clear_8x_cont(to, ret, "", "", "") | ||
| 561 | |||
| 562 | #define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 563 | __asm_clear_8x_cont(to, ret, \ | ||
| 564 | " clear.d [%0+]\n6:\n" CLEAR, \ | ||
| 565 | "7: addq 4,%1\n" FIXUP, \ | ||
| 566 | " .dword 6b,7b\n" TENTRY) | ||
| 567 | |||
| 568 | #define __asm_clear_12(to, ret) \ | ||
| 569 | __asm_clear_12x_cont(to, ret, "", "", "") | ||
| 570 | |||
| 571 | #define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 572 | __asm_clear_12x_cont(to, ret, \ | ||
| 573 | " clear.d [%0+]\n8:\n" CLEAR, \ | ||
| 574 | "9: addq 4,%1\n" FIXUP, \ | ||
| 575 | " .dword 8b,9b\n" TENTRY) | ||
| 576 | |||
| 577 | #define __asm_clear_16(to, ret) \ | ||
| 578 | __asm_clear_16x_cont(to, ret, "", "", "") | ||
| 579 | |||
| 580 | #define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 581 | __asm_clear_16x_cont(to, ret, \ | ||
| 582 | " clear.d [%0+]\n10:\n" CLEAR, \ | ||
| 583 | "11: addq 4,%1\n" FIXUP, \ | ||
| 584 | " .dword 10b,11b\n" TENTRY) | ||
| 585 | |||
| 586 | #define __asm_clear_20(to, ret) \ | ||
| 587 | __asm_clear_20x_cont(to, ret, "", "", "") | ||
| 588 | |||
| 589 | #define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 590 | __asm_clear_20x_cont(to, ret, \ | ||
| 591 | " clear.d [%0+]\n12:\n" CLEAR, \ | ||
| 592 | "13: addq 4,%1\n" FIXUP, \ | ||
| 593 | " .dword 12b,13b\n" TENTRY) | ||
| 594 | |||
| 595 | #define __asm_clear_24(to, ret) \ | ||
| 596 | __asm_clear_24x_cont(to, ret, "", "", "") | ||
| 597 | |||
| 598 | /* | ||
| 599 | * Return the size of a string (including the ending 0) | ||
| 600 | * | ||
| 601 | * Return length of string in userspace including terminating 0 | ||
| 602 | * or 0 for error. Return a value greater than N if too long. | ||
| 603 | */ | ||
| 604 | |||
| 605 | static inline long | ||
| 606 | strnlen_user(const char *s, long n) | ||
| 607 | { | ||
| 608 | long res, tmp1; | ||
| 609 | |||
| 610 | if (!access_ok(VERIFY_READ, s, 0)) | ||
| 611 | return 0; | ||
| 612 | |||
| 613 | /* | ||
| 614 | * This code is deduced from: | ||
| 615 | * | ||
| 616 | * tmp1 = n; | ||
| 617 | * while (tmp1-- > 0 && *s++) | ||
| 618 | * ; | ||
| 619 | * | ||
| 620 | * res = n - tmp1; | ||
| 621 | * | ||
| 622 | * (with tweaks). | ||
| 623 | */ | ||
| 624 | |||
| 625 | __asm__ __volatile__ ( | ||
| 626 | " move.d %1,$r9\n" | ||
| 627 | "0:\n" | ||
| 628 | " ble 1f\n" | ||
| 629 | " subq 1,$r9\n" | ||
| 630 | |||
| 631 | " test.b [%0+]\n" | ||
| 632 | " bne 0b\n" | ||
| 633 | " test.d $r9\n" | ||
| 634 | "1:\n" | ||
| 635 | " move.d %1,%0\n" | ||
| 636 | " sub.d $r9,%0\n" | ||
| 637 | "2:\n" | ||
| 638 | " .section .fixup,\"ax\"\n" | ||
| 639 | |||
| 640 | "3: clear.d %0\n" | ||
| 641 | " jump 2b\n" | ||
| 642 | |||
| 643 | /* There's one address for a fault at the first move, and | ||
| 644 | two possible PC values for a fault at the second move, | ||
| 645 | being a delay-slot filler. However, the branch-target | ||
| 646 | for the second move is the same as the first address. | ||
| 647 | Just so you don't get confused... */ | ||
| 648 | " .previous\n" | ||
| 649 | " .section __ex_table,\"a\"\n" | ||
| 650 | " .dword 0b,3b\n" | ||
| 651 | " .dword 1b,3b\n" | ||
| 652 | " .previous\n" | ||
| 653 | : "=r" (res), "=r" (tmp1) | ||
| 654 | : "0" (s), "1" (n) | ||
| 655 | : "r9"); | ||
| 656 | |||
| 657 | return res; | ||
| 658 | } | ||
| 659 | |||
| 660 | #endif | ||
diff --git a/include/asm-cris/arch-v10/unistd.h b/include/asm-cris/arch-v10/unistd.h deleted file mode 100644 index d1a38b9e6264..000000000000 --- a/include/asm-cris/arch-v10/unistd.h +++ /dev/null | |||
| @@ -1,148 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_UNISTD_H_ | ||
| 2 | #define _ASM_CRIS_ARCH_UNISTD_H_ | ||
| 3 | |||
| 4 | /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ | ||
| 5 | /* | ||
| 6 | * Don't remove the .ifnc tests; they are an insurance against | ||
| 7 | * any hard-to-spot gcc register allocation bugs. | ||
| 8 | */ | ||
| 9 | #define _syscall0(type,name) \ | ||
| 10 | type name(void) \ | ||
| 11 | { \ | ||
| 12 | register long __a __asm__ ("r10"); \ | ||
| 13 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 14 | __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ | ||
| 15 | ".err\n\t" \ | ||
| 16 | ".endif\n\t" \ | ||
| 17 | "break 13" \ | ||
| 18 | : "=r" (__a) \ | ||
| 19 | : "r" (__n_)); \ | ||
| 20 | if (__a >= 0) \ | ||
| 21 | return (type) __a; \ | ||
| 22 | errno = -__a; \ | ||
| 23 | return (type) -1; \ | ||
| 24 | } | ||
| 25 | |||
| 26 | #define _syscall1(type,name,type1,arg1) \ | ||
| 27 | type name(type1 arg1) \ | ||
| 28 | { \ | ||
| 29 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 30 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 31 | __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ | ||
| 32 | ".err\n\t" \ | ||
| 33 | ".endif\n\t" \ | ||
| 34 | "break 13" \ | ||
| 35 | : "=r" (__a) \ | ||
| 36 | : "r" (__n_), "0" (__a)); \ | ||
| 37 | if (__a >= 0) \ | ||
| 38 | return (type) __a; \ | ||
| 39 | errno = -__a; \ | ||
| 40 | return (type) -1; \ | ||
| 41 | } | ||
| 42 | |||
| 43 | #define _syscall2(type,name,type1,arg1,type2,arg2) \ | ||
| 44 | type name(type1 arg1,type2 arg2) \ | ||
| 45 | { \ | ||
| 46 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 47 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 48 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 49 | __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ | ||
| 50 | ".err\n\t" \ | ||
| 51 | ".endif\n\t" \ | ||
| 52 | "break 13" \ | ||
| 53 | : "=r" (__a) \ | ||
| 54 | : "r" (__n_), "0" (__a), "r" (__b)); \ | ||
| 55 | if (__a >= 0) \ | ||
| 56 | return (type) __a; \ | ||
| 57 | errno = -__a; \ | ||
| 58 | return (type) -1; \ | ||
| 59 | } | ||
| 60 | |||
| 61 | #define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ | ||
| 62 | type name(type1 arg1,type2 arg2,type3 arg3) \ | ||
| 63 | { \ | ||
| 64 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 65 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 66 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 67 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 68 | __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ | ||
| 69 | ".err\n\t" \ | ||
| 70 | ".endif\n\t" \ | ||
| 71 | "break 13" \ | ||
| 72 | : "=r" (__a) \ | ||
| 73 | : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ | ||
| 74 | if (__a >= 0) \ | ||
| 75 | return (type) __a; \ | ||
| 76 | errno = -__a; \ | ||
| 77 | return (type) -1; \ | ||
| 78 | } | ||
| 79 | |||
| 80 | #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ | ||
| 81 | type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ | ||
| 82 | { \ | ||
| 83 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 84 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 85 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 86 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 87 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 88 | __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ | ||
| 89 | ".err\n\t" \ | ||
| 90 | ".endif\n\t" \ | ||
| 91 | "break 13" \ | ||
| 92 | : "=r" (__a) \ | ||
| 93 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 94 | "r" (__c), "r" (__d)); \ | ||
| 95 | if (__a >= 0) \ | ||
| 96 | return (type) __a; \ | ||
| 97 | errno = -__a; \ | ||
| 98 | return (type) -1; \ | ||
| 99 | } | ||
| 100 | |||
| 101 | #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ | ||
| 102 | type5,arg5) \ | ||
| 103 | type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ | ||
| 104 | { \ | ||
| 105 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 106 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 107 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 108 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 109 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 110 | __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ | ||
| 111 | ".err\n\t" \ | ||
| 112 | ".endif\n\t" \ | ||
| 113 | "move %6,$mof\n\t" \ | ||
| 114 | "break 13" \ | ||
| 115 | : "=r" (__a) \ | ||
| 116 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 117 | "r" (__c), "r" (__d), "g" (arg5)); \ | ||
| 118 | if (__a >= 0) \ | ||
| 119 | return (type) __a; \ | ||
| 120 | errno = -__a; \ | ||
| 121 | return (type) -1; \ | ||
| 122 | } | ||
| 123 | |||
| 124 | #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ | ||
| 125 | type5,arg5,type6,arg6) \ | ||
| 126 | type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ | ||
| 127 | { \ | ||
| 128 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 129 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 130 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 131 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 132 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 133 | __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ | ||
| 134 | ".err\n\t" \ | ||
| 135 | ".endif\n\t" \ | ||
| 136 | "move %6,$mof\n\tmove %7,$srp\n\t" \ | ||
| 137 | "break 13" \ | ||
| 138 | : "=r" (__a) \ | ||
| 139 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 140 | "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\ | ||
| 141 | : "srp"); \ | ||
| 142 | if (__a >= 0) \ | ||
| 143 | return (type) __a; \ | ||
| 144 | errno = -__a; \ | ||
| 145 | return (type) -1; \ | ||
| 146 | } | ||
| 147 | |||
| 148 | #endif | ||
diff --git a/include/asm-cris/arch-v10/user.h b/include/asm-cris/arch-v10/user.h deleted file mode 100644 index 9303ea77c915..000000000000 --- a/include/asm-cris/arch-v10/user.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_USER_H | ||
| 2 | #define __ASM_CRIS_ARCH_USER_H | ||
| 3 | |||
| 4 | /* User mode registers, used for core dumps. In order to keep ELF_NGREG | ||
| 5 | sensible we let all registers be 32 bits. The csr registers are included | ||
| 6 | for future use. */ | ||
| 7 | struct user_regs_struct { | ||
| 8 | unsigned long r0; /* General registers. */ | ||
| 9 | unsigned long r1; | ||
| 10 | unsigned long r2; | ||
| 11 | unsigned long r3; | ||
| 12 | unsigned long r4; | ||
| 13 | unsigned long r5; | ||
| 14 | unsigned long r6; | ||
| 15 | unsigned long r7; | ||
| 16 | unsigned long r8; | ||
| 17 | unsigned long r9; | ||
| 18 | unsigned long r10; | ||
| 19 | unsigned long r11; | ||
| 20 | unsigned long r12; | ||
| 21 | unsigned long r13; | ||
| 22 | unsigned long sp; /* Stack pointer. */ | ||
| 23 | unsigned long pc; /* Program counter. */ | ||
| 24 | unsigned long p0; /* Constant zero (only 8 bits). */ | ||
| 25 | unsigned long vr; /* Version register (only 8 bits). */ | ||
| 26 | unsigned long p2; /* Reserved. */ | ||
| 27 | unsigned long p3; /* Reserved. */ | ||
| 28 | unsigned long p4; /* Constant zero (only 16 bits). */ | ||
| 29 | unsigned long ccr; /* Condition code register (only 16 bits). */ | ||
| 30 | unsigned long p6; /* Reserved. */ | ||
| 31 | unsigned long mof; /* Multiply overflow register. */ | ||
| 32 | unsigned long p8; /* Constant zero. */ | ||
| 33 | unsigned long ibr; /* Not accessible. */ | ||
| 34 | unsigned long irp; /* Not accessible. */ | ||
| 35 | unsigned long srp; /* Subroutine return pointer. */ | ||
| 36 | unsigned long bar; /* Not accessible. */ | ||
| 37 | unsigned long dccr; /* Dword condition code register. */ | ||
| 38 | unsigned long brp; /* Not accessible. */ | ||
| 39 | unsigned long usp; /* User-mode stack pointer. Same as sp when | ||
| 40 | in user mode. */ | ||
| 41 | unsigned long csrinstr; /* Internal status registers. */ | ||
| 42 | unsigned long csraddr; | ||
| 43 | unsigned long csrdata; | ||
| 44 | }; | ||
| 45 | |||
| 46 | #endif | ||
diff --git a/include/asm-cris/arch-v32/Kbuild b/include/asm-cris/arch-v32/Kbuild deleted file mode 100644 index 35f2fc4f993e..000000000000 --- a/include/asm-cris/arch-v32/Kbuild +++ /dev/null | |||
| @@ -1,2 +0,0 @@ | |||
| 1 | header-y += user.h | ||
| 2 | header-y += cryptocop.h | ||
diff --git a/include/asm-cris/arch-v32/arbiter.h b/include/asm-cris/arch-v32/arbiter.h deleted file mode 100644 index 081a911d7af1..000000000000 --- a/include/asm-cris/arch-v32/arbiter.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_ARBITER_H | ||
| 2 | #define _ASM_CRIS_ARCH_ARBITER_H | ||
| 3 | |||
| 4 | #define EXT_REGION 0 | ||
| 5 | #define INT_REGION 1 | ||
| 6 | |||
| 7 | typedef void (watch_callback)(void); | ||
| 8 | |||
| 9 | enum | ||
| 10 | { | ||
| 11 | arbiter_all_dmas = 0x3ff, | ||
| 12 | arbiter_cpu = 0xc00, | ||
| 13 | arbiter_all_clients = 0x3fff | ||
| 14 | }; | ||
| 15 | |||
| 16 | enum | ||
| 17 | { | ||
| 18 | arbiter_all_read = 0x55, | ||
| 19 | arbiter_all_write = 0xaa, | ||
| 20 | arbiter_all_accesses = 0xff | ||
| 21 | }; | ||
| 22 | |||
| 23 | int crisv32_arbiter_allocate_bandwidth(int client, int region, | ||
| 24 | unsigned long bandwidth); | ||
| 25 | int crisv32_arbiter_watch(unsigned long start, unsigned long size, | ||
| 26 | unsigned long clients, unsigned long accesses, | ||
| 27 | watch_callback* cb); | ||
| 28 | int crisv32_arbiter_unwatch(int id); | ||
| 29 | |||
| 30 | #endif | ||
diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h deleted file mode 100644 index 852ceff8013f..000000000000 --- a/include/asm-cris/arch-v32/atomic.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_ATOMIC__ | ||
| 2 | #define __ASM_CRIS_ARCH_ATOMIC__ | ||
| 3 | |||
| 4 | #include <linux/spinlock_types.h> | ||
| 5 | |||
| 6 | extern void cris_spin_unlock(void *l, int val); | ||
| 7 | extern void cris_spin_lock(void *l); | ||
| 8 | extern int cris_spin_trylock(void* l); | ||
| 9 | |||
| 10 | #ifndef CONFIG_SMP | ||
| 11 | #define cris_atomic_save(addr, flags) local_irq_save(flags); | ||
| 12 | #define cris_atomic_restore(addr, flags) local_irq_restore(flags); | ||
| 13 | #else | ||
| 14 | |||
| 15 | extern spinlock_t cris_atomic_locks[]; | ||
| 16 | #define LOCK_COUNT 128 | ||
| 17 | #define HASH_ADDR(a) (((int)a) & 127) | ||
| 18 | |||
| 19 | #define cris_atomic_save(addr, flags) \ | ||
| 20 | local_irq_save(flags); \ | ||
| 21 | cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock); | ||
| 22 | |||
| 23 | #define cris_atomic_restore(addr, flags) \ | ||
| 24 | { \ | ||
| 25 | spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ | ||
| 26 | __asm__ volatile ("move.d %1,%0" \ | ||
| 27 | : "=m" (lock->raw_lock.slock) \ | ||
| 28 | : "r" (1) \ | ||
| 29 | : "memory"); \ | ||
| 30 | local_irq_restore(flags); \ | ||
| 31 | } | ||
| 32 | |||
| 33 | #endif | ||
| 34 | |||
| 35 | #endif | ||
| 36 | |||
diff --git a/include/asm-cris/arch-v32/bitops.h b/include/asm-cris/arch-v32/bitops.h deleted file mode 100644 index 147689d6b624..000000000000 --- a/include/asm-cris/arch-v32/bitops.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_BITOPS_H | ||
| 2 | #define _ASM_CRIS_ARCH_BITOPS_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Helper functions for the core of the ff[sz] functions. They compute the | ||
| 6 | * number of leading zeroes of a bits-in-byte, byte-in-word and | ||
| 7 | * word-in-dword-swapped number. They differ in that the first function also | ||
| 8 | * inverts all bits in the input. | ||
| 9 | */ | ||
| 10 | |||
| 11 | static inline unsigned long | ||
| 12 | cris_swapnwbrlz(unsigned long w) | ||
| 13 | { | ||
| 14 | unsigned long res; | ||
| 15 | |||
| 16 | __asm__ __volatile__ ("swapnwbr %0\n\t" | ||
| 17 | "lz %0,%0" | ||
| 18 | : "=r" (res) : "0" (w)); | ||
| 19 | |||
| 20 | return res; | ||
| 21 | } | ||
| 22 | |||
| 23 | static inline unsigned long | ||
| 24 | cris_swapwbrlz(unsigned long w) | ||
| 25 | { | ||
| 26 | unsigned long res; | ||
| 27 | |||
| 28 | __asm__ __volatile__ ("swapwbr %0\n\t" | ||
| 29 | "lz %0,%0" | ||
| 30 | : "=r" (res) : "0" (w)); | ||
| 31 | |||
| 32 | return res; | ||
| 33 | } | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Find First Zero in word. Undefined if no zero exist, so the caller should | ||
| 37 | * check against ~0 first. | ||
| 38 | */ | ||
| 39 | static inline unsigned long | ||
| 40 | ffz(unsigned long w) | ||
| 41 | { | ||
| 42 | return cris_swapnwbrlz(w); | ||
| 43 | } | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Find First Set bit in word. Undefined if no 1 exist, so the caller | ||
| 47 | * should check against 0 first. | ||
| 48 | */ | ||
| 49 | static inline unsigned long | ||
| 50 | __ffs(unsigned long w) | ||
| 51 | { | ||
| 52 | return cris_swapnwbrlz(~w); | ||
| 53 | } | ||
| 54 | |||
| 55 | /* | ||
| 56 | * Find First Bit that is set. | ||
| 57 | */ | ||
| 58 | static inline unsigned long | ||
| 59 | kernel_ffs(unsigned long w) | ||
| 60 | { | ||
| 61 | return w ? cris_swapwbrlz (w) + 1 : 0; | ||
| 62 | } | ||
| 63 | |||
| 64 | #endif /* _ASM_CRIS_ARCH_BITOPS_H */ | ||
diff --git a/include/asm-cris/arch-v32/bug.h b/include/asm-cris/arch-v32/bug.h deleted file mode 100644 index 0f211e135248..000000000000 --- a/include/asm-cris/arch-v32/bug.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRISv32_ARCH_BUG_H | ||
| 2 | #define __ASM_CRISv32_ARCH_BUG_H | ||
| 3 | |||
| 4 | #include <linux/stringify.h> | ||
| 5 | |||
| 6 | #ifdef CONFIG_BUG | ||
| 7 | #ifdef CONFIG_DEBUG_BUGVERBOSE | ||
| 8 | /* | ||
| 9 | * The penalty for the in-band code path will be the size of break 14. | ||
| 10 | * All other stuff is done out-of-band with exception handlers. | ||
| 11 | */ | ||
| 12 | #define BUG() \ | ||
| 13 | __asm__ __volatile__ ("0: break 14\n\t" \ | ||
| 14 | ".section .fixup,\"ax\"\n" \ | ||
| 15 | "1:\n\t" \ | ||
| 16 | "move.d %0, $r10\n\t" \ | ||
| 17 | "move.d %1, $r11\n\t" \ | ||
| 18 | "jump do_BUG\n\t" \ | ||
| 19 | "nop\n\t" \ | ||
| 20 | ".previous\n\t" \ | ||
| 21 | ".section __ex_table,\"a\"\n\t" \ | ||
| 22 | ".dword 0b, 1b\n\t" \ | ||
| 23 | ".previous\n\t" \ | ||
| 24 | : : "ri" (__FILE__), "i" (__LINE__)) | ||
| 25 | #else | ||
| 26 | #define BUG() __asm__ __volatile__ ("break 14\n\t") | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #define HAVE_ARCH_BUG | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #include <asm-generic/bug.h> | ||
| 33 | #endif | ||
diff --git a/include/asm-cris/arch-v32/byteorder.h b/include/asm-cris/arch-v32/byteorder.h deleted file mode 100644 index 6ef8fb4a35f2..000000000000 --- a/include/asm-cris/arch-v32/byteorder.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_BYTEORDER_H | ||
| 2 | #define _ASM_CRIS_ARCH_BYTEORDER_H | ||
| 3 | |||
| 4 | #include <asm/types.h> | ||
| 5 | |||
| 6 | static inline __const__ __u32 | ||
| 7 | ___arch__swab32(__u32 x) | ||
| 8 | { | ||
| 9 | __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x)); | ||
| 10 | return (x); | ||
| 11 | } | ||
| 12 | |||
| 13 | static inline __const__ __u16 | ||
| 14 | ___arch__swab16(__u16 x) | ||
| 15 | { | ||
| 16 | __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x)); | ||
| 17 | return (x); | ||
| 18 | } | ||
| 19 | |||
| 20 | #endif /* _ASM_CRIS_ARCH_BYTEORDER_H */ | ||
diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h deleted file mode 100644 index b3d752dfe15b..000000000000 --- a/include/asm-cris/arch-v32/cache.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_CACHE_H | ||
| 2 | #define _ASM_CRIS_ARCH_CACHE_H | ||
| 3 | |||
| 4 | #include <asm/arch/hwregs/dma.h> | ||
| 5 | |||
| 6 | /* A cache-line is 32 bytes. */ | ||
| 7 | #define L1_CACHE_BYTES 32 | ||
| 8 | #define L1_CACHE_SHIFT 5 | ||
| 9 | |||
| 10 | void flush_dma_list(dma_descr_data *descr); | ||
| 11 | void flush_dma_descr(dma_descr_data *descr, int flush_buf); | ||
| 12 | |||
| 13 | #define flush_dma_context(c) \ | ||
| 14 | flush_dma_list(phys_to_virt((c)->saved_data)); | ||
| 15 | |||
| 16 | void cris_flush_cache_range(void *buf, unsigned long len); | ||
| 17 | void cris_flush_cache(void); | ||
| 18 | |||
| 19 | #endif /* _ASM_CRIS_ARCH_CACHE_H */ | ||
diff --git a/include/asm-cris/arch-v32/checksum.h b/include/asm-cris/arch-v32/checksum.h deleted file mode 100644 index e5dcfce6e0dc..000000000000 --- a/include/asm-cris/arch-v32/checksum.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_CHECKSUM_H | ||
| 2 | #define _ASM_CRIS_ARCH_CHECKSUM_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Check values used in TCP/UDP headers. | ||
| 6 | * | ||
| 7 | * The gain of doing this in assembler instead of C, is that C doesn't | ||
| 8 | * generate carry-additions for the 32-bit components of the | ||
| 9 | * checksum. Which means it would be necessary to split all those into | ||
| 10 | * 16-bit components and then add. | ||
| 11 | */ | ||
| 12 | static inline __wsum | ||
| 13 | csum_tcpudp_nofold(__be32 saddr, __be32 daddr, | ||
| 14 | unsigned short len, unsigned short proto, __wsum sum) | ||
| 15 | { | ||
| 16 | __wsum res; | ||
| 17 | |||
| 18 | __asm__ __volatile__ ("add.d %2, %0\n\t" | ||
| 19 | "addc %3, %0\n\t" | ||
| 20 | "addc %4, %0\n\t" | ||
| 21 | "addc 0, %0\n\t" | ||
| 22 | : "=r" (res) | ||
| 23 | : "0" (sum), "r" (daddr), "r" (saddr), \ | ||
| 24 | "r" ((len + proto) << 8)); | ||
| 25 | |||
| 26 | return res; | ||
| 27 | } | ||
| 28 | |||
| 29 | #endif /* _ASM_CRIS_ARCH_CHECKSUM_H */ | ||
diff --git a/include/asm-cris/arch-v32/cryptocop.h b/include/asm-cris/arch-v32/cryptocop.h deleted file mode 100644 index dfa1f66fb987..000000000000 --- a/include/asm-cris/arch-v32/cryptocop.h +++ /dev/null | |||
| @@ -1,272 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * The device /dev/cryptocop is accessible using this driver using | ||
| 3 | * CRYPTOCOP_MAJOR (254) and minor number 0. | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef CRYPTOCOP_H | ||
| 7 | #define CRYPTOCOP_H | ||
| 8 | |||
| 9 | #include <linux/uio.h> | ||
| 10 | |||
| 11 | |||
| 12 | #define CRYPTOCOP_SESSION_ID_NONE (0) | ||
| 13 | |||
| 14 | typedef unsigned long long int cryptocop_session_id; | ||
| 15 | |||
| 16 | /* cryptocop ioctls */ | ||
| 17 | #define ETRAXCRYPTOCOP_IOCTYPE (250) | ||
| 18 | |||
| 19 | #define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) | ||
| 20 | #define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) | ||
| 21 | #define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) | ||
| 22 | #define CRYPTOCOP_IO_MAXNR (3) | ||
| 23 | |||
| 24 | typedef enum { | ||
| 25 | cryptocop_cipher_des = 0, | ||
| 26 | cryptocop_cipher_3des = 1, | ||
| 27 | cryptocop_cipher_aes = 2, | ||
| 28 | cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ | ||
| 29 | cryptocop_cipher_none | ||
| 30 | } cryptocop_cipher_type; | ||
| 31 | |||
| 32 | typedef enum { | ||
| 33 | cryptocop_digest_sha1 = 0, | ||
| 34 | cryptocop_digest_md5 = 1, | ||
| 35 | cryptocop_digest_none | ||
| 36 | } cryptocop_digest_type; | ||
| 37 | |||
| 38 | typedef enum { | ||
| 39 | cryptocop_csum_le = 0, | ||
| 40 | cryptocop_csum_be = 1, | ||
| 41 | cryptocop_csum_none | ||
| 42 | } cryptocop_csum_type; | ||
| 43 | |||
| 44 | typedef enum { | ||
| 45 | cryptocop_cipher_mode_ecb = 0, | ||
| 46 | cryptocop_cipher_mode_cbc, | ||
| 47 | cryptocop_cipher_mode_none | ||
| 48 | } cryptocop_cipher_mode; | ||
| 49 | |||
| 50 | typedef enum { | ||
| 51 | cryptocop_3des_eee = 0, | ||
| 52 | cryptocop_3des_eed = 1, | ||
| 53 | cryptocop_3des_ede = 2, | ||
| 54 | cryptocop_3des_edd = 3, | ||
| 55 | cryptocop_3des_dee = 4, | ||
| 56 | cryptocop_3des_ded = 5, | ||
| 57 | cryptocop_3des_dde = 6, | ||
| 58 | cryptocop_3des_ddd = 7 | ||
| 59 | } cryptocop_3des_mode; | ||
| 60 | |||
| 61 | /* Usermode accessible (ioctl) operations. */ | ||
| 62 | struct strcop_session_op{ | ||
| 63 | cryptocop_session_id ses_id; | ||
| 64 | |||
| 65 | cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ | ||
| 66 | |||
| 67 | cryptocop_cipher_mode cmode; /* ECB, CBC, none */ | ||
| 68 | cryptocop_3des_mode des3_mode; | ||
| 69 | |||
| 70 | cryptocop_digest_type digest; /* MD5, SHA1, none */ | ||
| 71 | |||
| 72 | cryptocop_csum_type csum; /* BE, LE, none */ | ||
| 73 | |||
| 74 | unsigned char *key; | ||
| 75 | size_t keylen; | ||
| 76 | }; | ||
| 77 | |||
| 78 | #define CRYPTOCOP_CSUM_LENGTH (2) | ||
| 79 | #define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ | ||
| 80 | #define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ | ||
| 81 | #define CRYPTOCOP_MAX_KEY_LENGTH (32) | ||
| 82 | |||
| 83 | struct strcop_crypto_op{ | ||
| 84 | cryptocop_session_id ses_id; | ||
| 85 | |||
| 86 | /* Indata. */ | ||
| 87 | unsigned char *indata; | ||
| 88 | size_t inlen; /* Total indata length. */ | ||
| 89 | |||
| 90 | /* Cipher configuration. */ | ||
| 91 | unsigned char do_cipher:1; | ||
| 92 | unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ | ||
| 93 | unsigned char cipher_explicit:1; | ||
| 94 | size_t cipher_start; | ||
| 95 | size_t cipher_len; | ||
| 96 | /* cipher_iv is used if do_cipher and cipher_explicit and the cipher | ||
| 97 | mode is CBC. The length is controlled by the type of cipher, | ||
| 98 | e.g. DES/3DES 8 octets and AES 16 octets. */ | ||
| 99 | unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; | ||
| 100 | /* Outdata. */ | ||
| 101 | unsigned char *cipher_outdata; | ||
| 102 | size_t cipher_outlen; | ||
| 103 | |||
| 104 | /* digest configuration. */ | ||
| 105 | unsigned char do_digest:1; | ||
| 106 | size_t digest_start; | ||
| 107 | size_t digest_len; | ||
| 108 | /* Outdata. The actual length is determined by the type of the digest. */ | ||
| 109 | unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; | ||
| 110 | |||
| 111 | /* Checksum configuration. */ | ||
| 112 | unsigned char do_csum:1; | ||
| 113 | size_t csum_start; | ||
| 114 | size_t csum_len; | ||
| 115 | /* Outdata. */ | ||
| 116 | unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; | ||
| 117 | }; | ||
| 118 | |||
| 119 | |||
| 120 | |||
| 121 | #ifdef __KERNEL__ | ||
| 122 | |||
| 123 | /********** The API to use from inside the kernel. ************/ | ||
| 124 | |||
| 125 | #include <asm/arch/hwregs/dma.h> | ||
| 126 | |||
| 127 | typedef enum { | ||
| 128 | cryptocop_alg_csum = 0, | ||
| 129 | cryptocop_alg_mem2mem, | ||
| 130 | cryptocop_alg_md5, | ||
| 131 | cryptocop_alg_sha1, | ||
| 132 | cryptocop_alg_des, | ||
| 133 | cryptocop_alg_3des, | ||
| 134 | cryptocop_alg_aes, | ||
| 135 | cryptocop_no_alg, | ||
| 136 | } cryptocop_algorithm; | ||
| 137 | |||
| 138 | typedef u8 cryptocop_tfrm_id; | ||
| 139 | |||
| 140 | |||
| 141 | struct cryptocop_operation; | ||
| 142 | |||
| 143 | typedef void (cryptocop_callback)(struct cryptocop_operation*, void*); | ||
| 144 | |||
| 145 | struct cryptocop_transform_init { | ||
| 146 | cryptocop_algorithm alg; | ||
| 147 | /* Keydata for ciphers. */ | ||
| 148 | unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH]; | ||
| 149 | unsigned int keylen; | ||
| 150 | cryptocop_cipher_mode cipher_mode; | ||
| 151 | cryptocop_3des_mode tdes_mode; | ||
| 152 | cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */ | ||
| 153 | |||
| 154 | cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */ | ||
| 155 | struct cryptocop_transform_init *next; | ||
| 156 | }; | ||
| 157 | |||
| 158 | |||
| 159 | typedef enum { | ||
| 160 | cryptocop_source_dma = 0, | ||
| 161 | cryptocop_source_des, | ||
| 162 | cryptocop_source_3des, | ||
| 163 | cryptocop_source_aes, | ||
| 164 | cryptocop_source_md5, | ||
| 165 | cryptocop_source_sha1, | ||
| 166 | cryptocop_source_csum, | ||
| 167 | cryptocop_source_none, | ||
| 168 | } cryptocop_source; | ||
| 169 | |||
| 170 | |||
| 171 | struct cryptocop_desc_cfg { | ||
| 172 | cryptocop_tfrm_id tid; | ||
| 173 | cryptocop_source src; | ||
| 174 | unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */ | ||
| 175 | struct cryptocop_desc_cfg *next; | ||
| 176 | }; | ||
| 177 | |||
| 178 | struct cryptocop_desc { | ||
| 179 | size_t length; | ||
| 180 | struct cryptocop_desc_cfg *cfg; | ||
| 181 | struct cryptocop_desc *next; | ||
| 182 | }; | ||
| 183 | |||
| 184 | |||
| 185 | /* Flags for cryptocop_tfrm_cfg */ | ||
| 186 | #define CRYPTOCOP_NO_FLAG (0x00) | ||
| 187 | #define CRYPTOCOP_ENCRYPT (0x01) | ||
| 188 | #define CRYPTOCOP_DECRYPT (0x02) | ||
| 189 | #define CRYPTOCOP_EXPLICIT_IV (0x04) | ||
| 190 | |||
| 191 | struct cryptocop_tfrm_cfg { | ||
| 192 | cryptocop_tfrm_id tid; | ||
| 193 | |||
| 194 | unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */ | ||
| 195 | |||
| 196 | /* CBC initialisation vector for cihers. */ | ||
| 197 | u8 iv[CRYPTOCOP_MAX_IV_LENGTH]; | ||
| 198 | |||
| 199 | /* The position in output where to write the transform output. The order | ||
| 200 | in which the driver writes the output is unspecified, hence if several | ||
| 201 | transforms write on the same positions in the output the result is | ||
| 202 | unspecified. */ | ||
| 203 | size_t inject_ix; | ||
| 204 | |||
| 205 | struct cryptocop_tfrm_cfg *next; | ||
| 206 | }; | ||
| 207 | |||
| 208 | |||
| 209 | |||
| 210 | struct cryptocop_dma_list_operation{ | ||
| 211 | /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in | ||
| 212 | struct cryptocop_operation must be set for the driver to use them. outlist, | ||
| 213 | out_data_buf, inlist and in_data_buf must all be physical addresses since they will | ||
| 214 | be loaded to DMA . */ | ||
| 215 | dma_descr_data *outlist; /* Out from memory to the co-processor. */ | ||
| 216 | char *out_data_buf; | ||
| 217 | dma_descr_data *inlist; /* In from the co-processor to memory. */ | ||
| 218 | char *in_data_buf; | ||
| 219 | |||
| 220 | cryptocop_3des_mode tdes_mode; | ||
| 221 | cryptocop_csum_type csum_mode; | ||
| 222 | }; | ||
| 223 | |||
| 224 | |||
| 225 | struct cryptocop_tfrm_operation{ | ||
| 226 | /* Operation configuration, if not 'use_dmalists' is set. */ | ||
| 227 | struct cryptocop_tfrm_cfg *tfrm_cfg; | ||
| 228 | struct cryptocop_desc *desc; | ||
| 229 | |||
| 230 | struct iovec *indata; | ||
| 231 | size_t incount; | ||
| 232 | size_t inlen; /* Total inlength. */ | ||
| 233 | |||
| 234 | struct iovec *outdata; | ||
| 235 | size_t outcount; | ||
| 236 | size_t outlen; /* Total outlength. */ | ||
| 237 | }; | ||
| 238 | |||
| 239 | |||
| 240 | struct cryptocop_operation { | ||
| 241 | cryptocop_callback *cb; | ||
| 242 | void *cb_data; | ||
| 243 | |||
| 244 | cryptocop_session_id sid; | ||
| 245 | |||
| 246 | /* The status of the operation when returned to consumer. */ | ||
| 247 | int operation_status; /* 0, -EAGAIN */ | ||
| 248 | |||
| 249 | /* Flags */ | ||
| 250 | unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */ | ||
| 251 | unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */ | ||
| 252 | unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */ | ||
| 253 | |||
| 254 | union{ | ||
| 255 | struct cryptocop_dma_list_operation list_op; | ||
| 256 | struct cryptocop_tfrm_operation tfrm_op; | ||
| 257 | }; | ||
| 258 | }; | ||
| 259 | |||
| 260 | |||
| 261 | int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag); | ||
| 262 | int cryptocop_free_session(cryptocop_session_id sid); | ||
| 263 | |||
| 264 | int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation); | ||
| 265 | |||
| 266 | int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); | ||
| 267 | |||
| 268 | int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); | ||
| 269 | |||
| 270 | #endif /* __KERNEL__ */ | ||
| 271 | |||
| 272 | #endif /* CRYPTOCOP_H */ | ||
diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h deleted file mode 100644 index e9fda03810a9..000000000000 --- a/include/asm-cris/arch-v32/delay.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_DELAY_H | ||
| 2 | #define _ASM_CRIS_ARCH_DELAY_H | ||
| 3 | |||
| 4 | extern void cris_delay10ns(u32 n10ns); | ||
| 5 | #define udelay(u) cris_delay10ns((u)*100) | ||
| 6 | #define ndelay(n) cris_delay10ns(((n)+9)/10) | ||
| 7 | |||
| 8 | /* | ||
| 9 | * Not used anymore for udelay or ndelay. Referenced by | ||
| 10 | * e.g. init/calibrate.c. All other references are likely bugs; | ||
| 11 | * should be replaced by mdelay, udelay or ndelay. | ||
| 12 | */ | ||
| 13 | |||
| 14 | static inline void | ||
| 15 | __delay(int loops) | ||
| 16 | { | ||
| 17 | __asm__ __volatile__ ( | ||
| 18 | "move.d %0, $r9\n\t" | ||
| 19 | "beq 2f\n\t" | ||
| 20 | "subq 1, $r9\n\t" | ||
| 21 | "1:\n\t" | ||
| 22 | "bne 1b\n\t" | ||
| 23 | "subq 1, $r9\n" | ||
| 24 | "2:" | ||
| 25 | : : "g" (loops) : "r9"); | ||
| 26 | } | ||
| 27 | |||
| 28 | #endif /* _ASM_CRIS_ARCH_DELAY_H */ | ||
diff --git a/include/asm-cris/arch-v32/dma.h b/include/asm-cris/arch-v32/dma.h deleted file mode 100644 index 3674081389fd..000000000000 --- a/include/asm-cris/arch-v32/dma.h +++ /dev/null | |||
| @@ -1,79 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_CRIS_DMA_H | ||
| 2 | #define _ASM_ARCH_CRIS_DMA_H | ||
| 3 | |||
| 4 | /* Defines for using and allocating dma channels. */ | ||
| 5 | |||
| 6 | #define MAX_DMA_CHANNELS 10 | ||
| 7 | |||
| 8 | #define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ | ||
| 9 | #define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ | ||
| 10 | |||
| 11 | #define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ | ||
| 12 | #define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ | ||
| 13 | |||
| 14 | #define ATA_TX_DMA_NBR 2 /* ATA interface out. */ | ||
| 15 | #define ATA_RX_DMA_NBR 3 /* ATA interface in. */ | ||
| 16 | |||
| 17 | #define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ | ||
| 18 | #define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ | ||
| 19 | |||
| 20 | #define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ | ||
| 21 | #define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ | ||
| 22 | |||
| 23 | #define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ | ||
| 24 | #define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ | ||
| 25 | |||
| 26 | #define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ | ||
| 27 | #define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ | ||
| 28 | |||
| 29 | #define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ | ||
| 30 | #define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ | ||
| 31 | |||
| 32 | #define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ | ||
| 33 | #define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ | ||
| 34 | |||
| 35 | #define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ | ||
| 36 | #define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ | ||
| 37 | |||
| 38 | #define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ | ||
| 39 | #define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ | ||
| 40 | |||
| 41 | #define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ | ||
| 42 | #define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ | ||
| 43 | |||
| 44 | #define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ | ||
| 45 | #define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ | ||
| 46 | |||
| 47 | #define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ | ||
| 48 | #define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ | ||
| 49 | |||
| 50 | enum dma_owner | ||
| 51 | { | ||
| 52 | dma_eth0, | ||
| 53 | dma_eth1, | ||
| 54 | dma_iop0, | ||
| 55 | dma_iop1, | ||
| 56 | dma_ser0, | ||
| 57 | dma_ser1, | ||
| 58 | dma_ser2, | ||
| 59 | dma_ser3, | ||
| 60 | dma_sser0, | ||
| 61 | dma_sser1, | ||
| 62 | dma_ata, | ||
| 63 | dma_strp, | ||
| 64 | dma_ext0, | ||
| 65 | dma_ext1, | ||
| 66 | dma_ext2, | ||
| 67 | dma_ext3 | ||
| 68 | }; | ||
| 69 | |||
| 70 | int crisv32_request_dma(unsigned int dmanr, const char * device_id, | ||
| 71 | unsigned options, unsigned bandwidth, enum dma_owner owner); | ||
| 72 | void crisv32_free_dma(unsigned int dmanr); | ||
| 73 | |||
| 74 | /* Masks used by crisv32_request_dma options: */ | ||
| 75 | #define DMA_VERBOSE_ON_ERROR 1 | ||
| 76 | #define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) | ||
| 77 | #define DMA_INT_MEM 4 | ||
| 78 | |||
| 79 | #endif /* _ASM_ARCH_CRIS_DMA_H */ | ||
diff --git a/include/asm-cris/arch-v32/elf.h b/include/asm-cris/arch-v32/elf.h deleted file mode 100644 index 1324e505a4d8..000000000000 --- a/include/asm-cris/arch-v32/elf.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ELF_H | ||
| 2 | #define _ASM_CRIS_ELF_H | ||
| 3 | |||
| 4 | #define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 | ||
| 5 | |||
| 6 | /* | ||
| 7 | * This is used to ensure we don't load something for the wrong architecture. | ||
| 8 | */ | ||
| 9 | #define elf_check_arch(x) \ | ||
| 10 | ((x)->e_machine == EM_CRIS \ | ||
| 11 | && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ | ||
| 12 | || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) | ||
| 13 | |||
| 14 | /* CRISv32 ELF register definitions. */ | ||
| 15 | |||
| 16 | #include <asm/ptrace.h> | ||
| 17 | |||
| 18 | /* Explicitly zero out registers to increase determinism. */ | ||
| 19 | #define ELF_PLAT_INIT(_r, load_addr) do { \ | ||
| 20 | (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ | ||
| 21 | (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ | ||
| 22 | (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ | ||
| 23 | (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ | ||
| 24 | (_r)->acr = 0; \ | ||
| 25 | } while (0) | ||
| 26 | |||
| 27 | /* | ||
| 28 | * An executable for which elf_read_implies_exec() returns TRUE will | ||
| 29 | * have the READ_IMPLIES_EXEC personality flag set automatically. | ||
| 30 | */ | ||
| 31 | #define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) | ||
| 32 | |||
| 33 | /* | ||
| 34 | * This is basically a pt_regs with the additional definition | ||
| 35 | * of the stack pointer since it's needed in a core dump. | ||
| 36 | * pr_regs is a elf_gregset_t and should be filled according | ||
| 37 | * to the layout of user_regs_struct. | ||
| 38 | */ | ||
| 39 | #define ELF_CORE_COPY_REGS(pr_reg, regs) \ | ||
| 40 | pr_reg[0] = regs->r0; \ | ||
| 41 | pr_reg[1] = regs->r1; \ | ||
| 42 | pr_reg[2] = regs->r2; \ | ||
| 43 | pr_reg[3] = regs->r3; \ | ||
| 44 | pr_reg[4] = regs->r4; \ | ||
| 45 | pr_reg[5] = regs->r5; \ | ||
| 46 | pr_reg[6] = regs->r6; \ | ||
| 47 | pr_reg[7] = regs->r7; \ | ||
| 48 | pr_reg[8] = regs->r8; \ | ||
| 49 | pr_reg[9] = regs->r9; \ | ||
| 50 | pr_reg[10] = regs->r10; \ | ||
| 51 | pr_reg[11] = regs->r11; \ | ||
| 52 | pr_reg[12] = regs->r12; \ | ||
| 53 | pr_reg[13] = regs->r13; \ | ||
| 54 | pr_reg[14] = rdusp(); /* SP */ \ | ||
| 55 | pr_reg[15] = regs->acr; /* ACR */ \ | ||
| 56 | pr_reg[16] = 0; /* BZ */ \ | ||
| 57 | pr_reg[17] = rdvr(); /* VR */ \ | ||
| 58 | pr_reg[18] = 0; /* PID */ \ | ||
| 59 | pr_reg[19] = regs->srs; /* SRS */ \ | ||
| 60 | pr_reg[20] = 0; /* WZ */ \ | ||
| 61 | pr_reg[21] = regs->exs; /* EXS */ \ | ||
| 62 | pr_reg[22] = regs->eda; /* EDA */ \ | ||
| 63 | pr_reg[23] = regs->mof; /* MOF */ \ | ||
| 64 | pr_reg[24] = 0; /* DZ */ \ | ||
| 65 | pr_reg[25] = 0; /* EBP */ \ | ||
| 66 | pr_reg[26] = regs->erp; /* ERP */ \ | ||
| 67 | pr_reg[27] = regs->srp; /* SRP */ \ | ||
| 68 | pr_reg[28] = 0; /* NRP */ \ | ||
| 69 | pr_reg[29] = regs->ccs; /* CCS */ \ | ||
| 70 | pr_reg[30] = rdusp(); /* USP */ \ | ||
| 71 | pr_reg[31] = regs->spc; /* SPC */ \ | ||
| 72 | |||
| 73 | #endif /* _ASM_CRIS_ELF_H */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile deleted file mode 100644 index f9a05d2aa061..000000000000 --- a/include/asm-cris/arch-v32/hwregs/Makefile +++ /dev/null | |||
| @@ -1,186 +0,0 @@ | |||
| 1 | # Makefile to generate or copy the latest register definitions | ||
| 2 | # and related datastructures and helpermacros. | ||
| 3 | # The offical place for these files is at: | ||
| 4 | RELEASE ?= r1_alfa5 | ||
| 5 | OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ | ||
| 6 | |||
| 7 | # which is updated on each new release. | ||
| 8 | INCL_ASMFILES = | ||
| 9 | INCL_FILES = ata_defs.h | ||
| 10 | INCL_FILES += bif_core_defs.h | ||
| 11 | INCL_ASMFILES += bif_core_defs_asm.h | ||
| 12 | INCL_FILES += bif_slave_defs.h | ||
| 13 | #INCL_FILES += bif_slave_ext_defs.h | ||
| 14 | INCL_FILES += config_defs.h | ||
| 15 | INCL_ASMFILES += config_defs_asm.h | ||
| 16 | INCL_FILES += cpu_vect.h | ||
| 17 | #INCL_FILES += cris_defs.h | ||
| 18 | #INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h | ||
| 19 | INCL_FILES += dma.h | ||
| 20 | INCL_FILES += dma_defs.h | ||
| 21 | INCL_FILES += eth_defs.h | ||
| 22 | INCL_FILES += extmem_defs.h | ||
| 23 | INCL_FILES += gio_defs.h | ||
| 24 | INCL_ASMFILES += gio_defs_asm.h | ||
| 25 | INCL_FILES += intr_vect.h | ||
| 26 | INCL_FILES += intr_vect_defs.h | ||
| 27 | INCL_ASMFILES += intr_vect_defs_asm.h | ||
| 28 | INCL_FILES += marb_bp_defs.h | ||
| 29 | INCL_FILES += marb_defs.h | ||
| 30 | INCL_ASMFILES += mmu_defs_asm.h | ||
| 31 | #INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h | ||
| 32 | #INCL_FILES += par_defs.h # No useful content | ||
| 33 | INCL_FILES += pinmux_defs.h | ||
| 34 | INCL_FILES += reg_map.h | ||
| 35 | INCL_ASMFILES += reg_map_asm.h | ||
| 36 | INCL_FILES += reg_rdwr.h | ||
| 37 | INCL_FILES += ser_defs.h | ||
| 38 | #INCL_FILES += spec_reg.h # In handcrafted supp_reg.h | ||
| 39 | INCL_FILES += sser_defs.h | ||
| 40 | INCL_FILES += strcop_defs.h | ||
| 41 | #INCL_FILES += strcop.h # Where is this? | ||
| 42 | INCL_FILES += strmux_defs.h | ||
| 43 | #INCL_FILES += supp_reg.h # Handcrafted instead | ||
| 44 | INCL_FILES += timer_defs.h | ||
| 45 | |||
| 46 | REGDESC = | ||
| 47 | REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r | ||
| 48 | REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r | ||
| 49 | REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r | ||
| 50 | #REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r | ||
| 51 | REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r | ||
| 52 | REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r | ||
| 53 | REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r | ||
| 54 | REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r | ||
| 55 | REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r | ||
| 56 | REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r | ||
| 57 | REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r | ||
| 58 | REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r | ||
| 59 | #REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r | ||
| 60 | REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r | ||
| 61 | REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r | ||
| 62 | REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r | ||
| 63 | REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r | ||
| 64 | REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r | ||
| 65 | #REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r | ||
| 66 | |||
| 67 | |||
| 68 | BASEDIR = /n/asic/design | ||
| 69 | DESIGNDIR = /n/asic/projects/guinness/design | ||
| 70 | RDES2C = /n/asic/bin/rdes2c | ||
| 71 | RDES2C = /n/asic/design/tools/rdesc/rdes2c | ||
| 72 | RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr | ||
| 73 | RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt | ||
| 74 | |||
| 75 | ## all - Just print help - you probably want to do 'make gen' | ||
| 76 | all: help | ||
| 77 | |||
| 78 | # Disable implicit rule that may generate deleted files from RCS/ directory. | ||
| 79 | %.r: | ||
| 80 | |||
| 81 | %.h: | ||
| 82 | |||
| 83 | ## help - This help | ||
| 84 | help: | ||
| 85 | @grep '^## ' Makefile | ||
| 86 | |||
| 87 | ## gen - Generate include files | ||
| 88 | gen: $(INCL_FILES) $(INCL_ASMFILES) | ||
| 89 | |||
| 90 | ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r | ||
| 91 | $(RDES2C) $< | ||
| 92 | config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r | ||
| 93 | $(RDES2C) $< | ||
| 94 | config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r | ||
| 95 | $(RDES2C) -asm $< | ||
| 96 | # Can't generate cpu_vect.h yet | ||
| 97 | #cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ???? | ||
| 98 | # $(RDES2INTR) $< | ||
| 99 | cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h | ||
| 100 | cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ | ||
| 101 | dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r | ||
| 102 | $(RDES2C) $< | ||
| 103 | $(BASEDIR)/core/dma/sw/dma.h: | ||
| 104 | dma.h: $(BASEDIR)/core/dma/sw/dma.h | ||
| 105 | cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ | ||
| 106 | eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r | ||
| 107 | $(RDES2C) $< | ||
| 108 | extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r | ||
| 109 | $(RDES2C) $< | ||
| 110 | gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r | ||
| 111 | $(RDES2C) $< | ||
| 112 | intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r | ||
| 113 | $(RDES2C) $< | ||
| 114 | intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r | ||
| 115 | $(RDES2C) -asm $< | ||
| 116 | # Can't generate intr_vect.h yet | ||
| 117 | #intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r | ||
| 118 | # $(RDES2INTR) $< | ||
| 119 | intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h | ||
| 120 | cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ | ||
| 121 | mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r | ||
| 122 | $(RDES2C) -asm $< | ||
| 123 | par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r | ||
| 124 | $(RDES2C) $< | ||
| 125 | |||
| 126 | # From /n/asic/projects/guinness/design/ | ||
| 127 | reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap | ||
| 128 | $(RDES2C) -base 0xb0000000 $^ | ||
| 129 | reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap | ||
| 130 | $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^ | ||
| 131 | |||
| 132 | reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h | ||
| 133 | cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ | ||
| 134 | |||
| 135 | ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r | ||
| 136 | $(RDES2C) $< | ||
| 137 | strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r | ||
| 138 | $(RDES2C) $< | ||
| 139 | strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h | ||
| 140 | cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ | ||
| 141 | strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r | ||
| 142 | $(RDES2C) $< | ||
| 143 | timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r | ||
| 144 | $(RDES2C) $< | ||
| 145 | usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r | ||
| 146 | $(RDES2C) $< | ||
| 147 | |||
| 148 | ## copy - Copy files from official location | ||
| 149 | copy: | ||
| 150 | @for HFILE in $(INCL_FILES); do \ | ||
| 151 | echo " $$HFILE"; \ | ||
| 152 | cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ | ||
| 153 | done | ||
| 154 | @for HFILE in $(INCL_ASMFILES); do \ | ||
| 155 | echo " $$HFILE"; \ | ||
| 156 | cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ | ||
| 157 | done | ||
| 158 | ## ls_official - List official location | ||
| 159 | ls_official: | ||
| 160 | (cd $(OFFICIAL_INCDIR); ls -l *.h ) | ||
| 161 | |||
| 162 | ## diff_official - Diff current directory with official location | ||
| 163 | diff_official: | ||
| 164 | diff . $(OFFICIAL_INCDIR) | ||
| 165 | |||
| 166 | ## doc - Generate .axw files from register description. | ||
| 167 | doc: $(REGDESC) | ||
| 168 | for RDES in $^; do \ | ||
| 169 | $(RDES2TXT) $$RDES; \ | ||
| 170 | done | ||
| 171 | |||
| 172 | .PHONY: axw | ||
| 173 | ## %.axw - Generate the specified .axw file (doesn't work for all files | ||
| 174 | ## due to inconsistent naming ir .r files. | ||
| 175 | %.axw: axw | ||
| 176 | @for RDES in $(REGDESC); do \ | ||
| 177 | if echo "$$RDES" | grep $* ; then \ | ||
| 178 | $(RDES2TXT) $$RDES; \ | ||
| 179 | fi \ | ||
| 180 | done | ||
| 181 | |||
| 182 | .PHONY: clean | ||
| 183 | ## clean - Remove .h files and .axw files. | ||
| 184 | clean: | ||
| 185 | rm -rf $(INCL_FILES) *.axw | ||
| 186 | |||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h deleted file mode 100644 index 866191418f9c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h +++ /dev/null | |||
| @@ -1,222 +0,0 @@ | |||
| 1 | #ifndef __ata_defs_asm_h | ||
| 2 | #define __ata_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/ata/rtl/ata_regs.r | ||
| 7 | * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:25 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r | ||
| 11 | * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_ctrl0, scope ata, type rw */ | ||
| 57 | #define reg_ata_rw_ctrl0___pio_hold___lsb 0 | ||
| 58 | #define reg_ata_rw_ctrl0___pio_hold___width 6 | ||
| 59 | #define reg_ata_rw_ctrl0___pio_strb___lsb 6 | ||
| 60 | #define reg_ata_rw_ctrl0___pio_strb___width 6 | ||
| 61 | #define reg_ata_rw_ctrl0___pio_setup___lsb 12 | ||
| 62 | #define reg_ata_rw_ctrl0___pio_setup___width 6 | ||
| 63 | #define reg_ata_rw_ctrl0___dma_hold___lsb 18 | ||
| 64 | #define reg_ata_rw_ctrl0___dma_hold___width 6 | ||
| 65 | #define reg_ata_rw_ctrl0___dma_strb___lsb 24 | ||
| 66 | #define reg_ata_rw_ctrl0___dma_strb___width 6 | ||
| 67 | #define reg_ata_rw_ctrl0___rst___lsb 30 | ||
| 68 | #define reg_ata_rw_ctrl0___rst___width 1 | ||
| 69 | #define reg_ata_rw_ctrl0___rst___bit 30 | ||
| 70 | #define reg_ata_rw_ctrl0___en___lsb 31 | ||
| 71 | #define reg_ata_rw_ctrl0___en___width 1 | ||
| 72 | #define reg_ata_rw_ctrl0___en___bit 31 | ||
| 73 | #define reg_ata_rw_ctrl0_offset 12 | ||
| 74 | |||
| 75 | /* Register rw_ctrl1, scope ata, type rw */ | ||
| 76 | #define reg_ata_rw_ctrl1___udma_tcyc___lsb 0 | ||
| 77 | #define reg_ata_rw_ctrl1___udma_tcyc___width 4 | ||
| 78 | #define reg_ata_rw_ctrl1___udma_tdvs___lsb 4 | ||
| 79 | #define reg_ata_rw_ctrl1___udma_tdvs___width 4 | ||
| 80 | #define reg_ata_rw_ctrl1_offset 16 | ||
| 81 | |||
| 82 | /* Register rw_ctrl2, scope ata, type rw */ | ||
| 83 | #define reg_ata_rw_ctrl2___data___lsb 0 | ||
| 84 | #define reg_ata_rw_ctrl2___data___width 16 | ||
| 85 | #define reg_ata_rw_ctrl2___dma_size___lsb 19 | ||
| 86 | #define reg_ata_rw_ctrl2___dma_size___width 1 | ||
| 87 | #define reg_ata_rw_ctrl2___dma_size___bit 19 | ||
| 88 | #define reg_ata_rw_ctrl2___multi___lsb 20 | ||
| 89 | #define reg_ata_rw_ctrl2___multi___width 1 | ||
| 90 | #define reg_ata_rw_ctrl2___multi___bit 20 | ||
| 91 | #define reg_ata_rw_ctrl2___hsh___lsb 21 | ||
| 92 | #define reg_ata_rw_ctrl2___hsh___width 2 | ||
| 93 | #define reg_ata_rw_ctrl2___trf_mode___lsb 23 | ||
| 94 | #define reg_ata_rw_ctrl2___trf_mode___width 1 | ||
| 95 | #define reg_ata_rw_ctrl2___trf_mode___bit 23 | ||
| 96 | #define reg_ata_rw_ctrl2___rw___lsb 24 | ||
| 97 | #define reg_ata_rw_ctrl2___rw___width 1 | ||
| 98 | #define reg_ata_rw_ctrl2___rw___bit 24 | ||
| 99 | #define reg_ata_rw_ctrl2___addr___lsb 25 | ||
| 100 | #define reg_ata_rw_ctrl2___addr___width 3 | ||
| 101 | #define reg_ata_rw_ctrl2___cs0___lsb 28 | ||
| 102 | #define reg_ata_rw_ctrl2___cs0___width 1 | ||
| 103 | #define reg_ata_rw_ctrl2___cs0___bit 28 | ||
| 104 | #define reg_ata_rw_ctrl2___cs1___lsb 29 | ||
| 105 | #define reg_ata_rw_ctrl2___cs1___width 1 | ||
| 106 | #define reg_ata_rw_ctrl2___cs1___bit 29 | ||
| 107 | #define reg_ata_rw_ctrl2___sel___lsb 30 | ||
| 108 | #define reg_ata_rw_ctrl2___sel___width 2 | ||
| 109 | #define reg_ata_rw_ctrl2_offset 0 | ||
| 110 | |||
| 111 | /* Register rs_stat_data, scope ata, type rs */ | ||
| 112 | #define reg_ata_rs_stat_data___data___lsb 0 | ||
| 113 | #define reg_ata_rs_stat_data___data___width 16 | ||
| 114 | #define reg_ata_rs_stat_data___dav___lsb 16 | ||
| 115 | #define reg_ata_rs_stat_data___dav___width 1 | ||
| 116 | #define reg_ata_rs_stat_data___dav___bit 16 | ||
| 117 | #define reg_ata_rs_stat_data___busy___lsb 17 | ||
| 118 | #define reg_ata_rs_stat_data___busy___width 1 | ||
| 119 | #define reg_ata_rs_stat_data___busy___bit 17 | ||
| 120 | #define reg_ata_rs_stat_data_offset 4 | ||
| 121 | |||
| 122 | /* Register r_stat_data, scope ata, type r */ | ||
| 123 | #define reg_ata_r_stat_data___data___lsb 0 | ||
| 124 | #define reg_ata_r_stat_data___data___width 16 | ||
| 125 | #define reg_ata_r_stat_data___dav___lsb 16 | ||
| 126 | #define reg_ata_r_stat_data___dav___width 1 | ||
| 127 | #define reg_ata_r_stat_data___dav___bit 16 | ||
| 128 | #define reg_ata_r_stat_data___busy___lsb 17 | ||
| 129 | #define reg_ata_r_stat_data___busy___width 1 | ||
| 130 | #define reg_ata_r_stat_data___busy___bit 17 | ||
| 131 | #define reg_ata_r_stat_data_offset 8 | ||
| 132 | |||
| 133 | /* Register rw_trf_cnt, scope ata, type rw */ | ||
| 134 | #define reg_ata_rw_trf_cnt___cnt___lsb 0 | ||
| 135 | #define reg_ata_rw_trf_cnt___cnt___width 17 | ||
| 136 | #define reg_ata_rw_trf_cnt_offset 20 | ||
| 137 | |||
| 138 | /* Register r_stat_misc, scope ata, type r */ | ||
| 139 | #define reg_ata_r_stat_misc___crc___lsb 0 | ||
| 140 | #define reg_ata_r_stat_misc___crc___width 16 | ||
| 141 | #define reg_ata_r_stat_misc_offset 24 | ||
| 142 | |||
| 143 | /* Register rw_intr_mask, scope ata, type rw */ | ||
| 144 | #define reg_ata_rw_intr_mask___bus0___lsb 0 | ||
| 145 | #define reg_ata_rw_intr_mask___bus0___width 1 | ||
| 146 | #define reg_ata_rw_intr_mask___bus0___bit 0 | ||
| 147 | #define reg_ata_rw_intr_mask___bus1___lsb 1 | ||
| 148 | #define reg_ata_rw_intr_mask___bus1___width 1 | ||
| 149 | #define reg_ata_rw_intr_mask___bus1___bit 1 | ||
| 150 | #define reg_ata_rw_intr_mask___bus2___lsb 2 | ||
| 151 | #define reg_ata_rw_intr_mask___bus2___width 1 | ||
| 152 | #define reg_ata_rw_intr_mask___bus2___bit 2 | ||
| 153 | #define reg_ata_rw_intr_mask___bus3___lsb 3 | ||
| 154 | #define reg_ata_rw_intr_mask___bus3___width 1 | ||
| 155 | #define reg_ata_rw_intr_mask___bus3___bit 3 | ||
| 156 | #define reg_ata_rw_intr_mask_offset 28 | ||
| 157 | |||
| 158 | /* Register rw_ack_intr, scope ata, type rw */ | ||
| 159 | #define reg_ata_rw_ack_intr___bus0___lsb 0 | ||
| 160 | #define reg_ata_rw_ack_intr___bus0___width 1 | ||
| 161 | #define reg_ata_rw_ack_intr___bus0___bit 0 | ||
| 162 | #define reg_ata_rw_ack_intr___bus1___lsb 1 | ||
| 163 | #define reg_ata_rw_ack_intr___bus1___width 1 | ||
| 164 | #define reg_ata_rw_ack_intr___bus1___bit 1 | ||
| 165 | #define reg_ata_rw_ack_intr___bus2___lsb 2 | ||
| 166 | #define reg_ata_rw_ack_intr___bus2___width 1 | ||
| 167 | #define reg_ata_rw_ack_intr___bus2___bit 2 | ||
| 168 | #define reg_ata_rw_ack_intr___bus3___lsb 3 | ||
| 169 | #define reg_ata_rw_ack_intr___bus3___width 1 | ||
| 170 | #define reg_ata_rw_ack_intr___bus3___bit 3 | ||
| 171 | #define reg_ata_rw_ack_intr_offset 32 | ||
| 172 | |||
| 173 | /* Register r_intr, scope ata, type r */ | ||
| 174 | #define reg_ata_r_intr___bus0___lsb 0 | ||
| 175 | #define reg_ata_r_intr___bus0___width 1 | ||
| 176 | #define reg_ata_r_intr___bus0___bit 0 | ||
| 177 | #define reg_ata_r_intr___bus1___lsb 1 | ||
| 178 | #define reg_ata_r_intr___bus1___width 1 | ||
| 179 | #define reg_ata_r_intr___bus1___bit 1 | ||
| 180 | #define reg_ata_r_intr___bus2___lsb 2 | ||
| 181 | #define reg_ata_r_intr___bus2___width 1 | ||
| 182 | #define reg_ata_r_intr___bus2___bit 2 | ||
| 183 | #define reg_ata_r_intr___bus3___lsb 3 | ||
| 184 | #define reg_ata_r_intr___bus3___width 1 | ||
| 185 | #define reg_ata_r_intr___bus3___bit 3 | ||
| 186 | #define reg_ata_r_intr_offset 36 | ||
| 187 | |||
| 188 | /* Register r_masked_intr, scope ata, type r */ | ||
| 189 | #define reg_ata_r_masked_intr___bus0___lsb 0 | ||
| 190 | #define reg_ata_r_masked_intr___bus0___width 1 | ||
| 191 | #define reg_ata_r_masked_intr___bus0___bit 0 | ||
| 192 | #define reg_ata_r_masked_intr___bus1___lsb 1 | ||
| 193 | #define reg_ata_r_masked_intr___bus1___width 1 | ||
| 194 | #define reg_ata_r_masked_intr___bus1___bit 1 | ||
| 195 | #define reg_ata_r_masked_intr___bus2___lsb 2 | ||
| 196 | #define reg_ata_r_masked_intr___bus2___width 1 | ||
| 197 | #define reg_ata_r_masked_intr___bus2___bit 2 | ||
| 198 | #define reg_ata_r_masked_intr___bus3___lsb 3 | ||
| 199 | #define reg_ata_r_masked_intr___bus3___width 1 | ||
| 200 | #define reg_ata_r_masked_intr___bus3___bit 3 | ||
| 201 | #define reg_ata_r_masked_intr_offset 40 | ||
| 202 | |||
| 203 | |||
| 204 | /* Constants */ | ||
| 205 | #define regk_ata_active 0x00000001 | ||
| 206 | #define regk_ata_byte 0x00000001 | ||
| 207 | #define regk_ata_data 0x00000001 | ||
| 208 | #define regk_ata_dma 0x00000001 | ||
| 209 | #define regk_ata_inactive 0x00000000 | ||
| 210 | #define regk_ata_no 0x00000000 | ||
| 211 | #define regk_ata_nodata 0x00000000 | ||
| 212 | #define regk_ata_pio 0x00000000 | ||
| 213 | #define regk_ata_rd 0x00000001 | ||
| 214 | #define regk_ata_reg 0x00000000 | ||
| 215 | #define regk_ata_rw_ctrl0_default 0x00000000 | ||
| 216 | #define regk_ata_rw_ctrl2_default 0x00000000 | ||
| 217 | #define regk_ata_rw_intr_mask_default 0x00000000 | ||
| 218 | #define regk_ata_udma 0x00000002 | ||
| 219 | #define regk_ata_word 0x00000000 | ||
| 220 | #define regk_ata_wr 0x00000000 | ||
| 221 | #define regk_ata_yes 0x00000001 | ||
| 222 | #endif /* __ata_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index c686cb335621..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h +++ /dev/null | |||
| @@ -1,319 +0,0 @@ | |||
| 1 | #ifndef __bif_core_defs_asm_h | ||
| 2 | #define __bif_core_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_core_regs.r | ||
| 7 | * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r | ||
| 11 | * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_grp1_cfg, scope bif_core, type rw */ | ||
| 57 | #define reg_bif_core_rw_grp1_cfg___lw___lsb 0 | ||
| 58 | #define reg_bif_core_rw_grp1_cfg___lw___width 6 | ||
| 59 | #define reg_bif_core_rw_grp1_cfg___ew___lsb 6 | ||
| 60 | #define reg_bif_core_rw_grp1_cfg___ew___width 3 | ||
| 61 | #define reg_bif_core_rw_grp1_cfg___zw___lsb 9 | ||
| 62 | #define reg_bif_core_rw_grp1_cfg___zw___width 3 | ||
| 63 | #define reg_bif_core_rw_grp1_cfg___aw___lsb 12 | ||
| 64 | #define reg_bif_core_rw_grp1_cfg___aw___width 2 | ||
| 65 | #define reg_bif_core_rw_grp1_cfg___dw___lsb 14 | ||
| 66 | #define reg_bif_core_rw_grp1_cfg___dw___width 2 | ||
| 67 | #define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 | ||
| 68 | #define reg_bif_core_rw_grp1_cfg___ewb___width 2 | ||
| 69 | #define reg_bif_core_rw_grp1_cfg___bw___lsb 18 | ||
| 70 | #define reg_bif_core_rw_grp1_cfg___bw___width 1 | ||
| 71 | #define reg_bif_core_rw_grp1_cfg___bw___bit 18 | ||
| 72 | #define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 | ||
| 73 | #define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 | ||
| 74 | #define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 | ||
| 75 | #define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 | ||
| 76 | #define reg_bif_core_rw_grp1_cfg___erc_en___width 1 | ||
| 77 | #define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 | ||
| 78 | #define reg_bif_core_rw_grp1_cfg___mode___lsb 21 | ||
| 79 | #define reg_bif_core_rw_grp1_cfg___mode___width 1 | ||
| 80 | #define reg_bif_core_rw_grp1_cfg___mode___bit 21 | ||
| 81 | #define reg_bif_core_rw_grp1_cfg_offset 0 | ||
| 82 | |||
| 83 | /* Register rw_grp2_cfg, scope bif_core, type rw */ | ||
| 84 | #define reg_bif_core_rw_grp2_cfg___lw___lsb 0 | ||
| 85 | #define reg_bif_core_rw_grp2_cfg___lw___width 6 | ||
| 86 | #define reg_bif_core_rw_grp2_cfg___ew___lsb 6 | ||
| 87 | #define reg_bif_core_rw_grp2_cfg___ew___width 3 | ||
| 88 | #define reg_bif_core_rw_grp2_cfg___zw___lsb 9 | ||
| 89 | #define reg_bif_core_rw_grp2_cfg___zw___width 3 | ||
| 90 | #define reg_bif_core_rw_grp2_cfg___aw___lsb 12 | ||
| 91 | #define reg_bif_core_rw_grp2_cfg___aw___width 2 | ||
| 92 | #define reg_bif_core_rw_grp2_cfg___dw___lsb 14 | ||
| 93 | #define reg_bif_core_rw_grp2_cfg___dw___width 2 | ||
| 94 | #define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 | ||
| 95 | #define reg_bif_core_rw_grp2_cfg___ewb___width 2 | ||
| 96 | #define reg_bif_core_rw_grp2_cfg___bw___lsb 18 | ||
| 97 | #define reg_bif_core_rw_grp2_cfg___bw___width 1 | ||
| 98 | #define reg_bif_core_rw_grp2_cfg___bw___bit 18 | ||
| 99 | #define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 | ||
| 100 | #define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 | ||
| 101 | #define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 | ||
| 102 | #define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 | ||
| 103 | #define reg_bif_core_rw_grp2_cfg___erc_en___width 1 | ||
| 104 | #define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 | ||
| 105 | #define reg_bif_core_rw_grp2_cfg___mode___lsb 21 | ||
| 106 | #define reg_bif_core_rw_grp2_cfg___mode___width 1 | ||
| 107 | #define reg_bif_core_rw_grp2_cfg___mode___bit 21 | ||
| 108 | #define reg_bif_core_rw_grp2_cfg_offset 4 | ||
| 109 | |||
| 110 | /* Register rw_grp3_cfg, scope bif_core, type rw */ | ||
| 111 | #define reg_bif_core_rw_grp3_cfg___lw___lsb 0 | ||
| 112 | #define reg_bif_core_rw_grp3_cfg___lw___width 6 | ||
| 113 | #define reg_bif_core_rw_grp3_cfg___ew___lsb 6 | ||
| 114 | #define reg_bif_core_rw_grp3_cfg___ew___width 3 | ||
| 115 | #define reg_bif_core_rw_grp3_cfg___zw___lsb 9 | ||
| 116 | #define reg_bif_core_rw_grp3_cfg___zw___width 3 | ||
| 117 | #define reg_bif_core_rw_grp3_cfg___aw___lsb 12 | ||
| 118 | #define reg_bif_core_rw_grp3_cfg___aw___width 2 | ||
| 119 | #define reg_bif_core_rw_grp3_cfg___dw___lsb 14 | ||
| 120 | #define reg_bif_core_rw_grp3_cfg___dw___width 2 | ||
| 121 | #define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 | ||
| 122 | #define reg_bif_core_rw_grp3_cfg___ewb___width 2 | ||
| 123 | #define reg_bif_core_rw_grp3_cfg___bw___lsb 18 | ||
| 124 | #define reg_bif_core_rw_grp3_cfg___bw___width 1 | ||
| 125 | #define reg_bif_core_rw_grp3_cfg___bw___bit 18 | ||
| 126 | #define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 | ||
| 127 | #define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 | ||
| 128 | #define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 | ||
| 129 | #define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 | ||
| 130 | #define reg_bif_core_rw_grp3_cfg___erc_en___width 1 | ||
| 131 | #define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 | ||
| 132 | #define reg_bif_core_rw_grp3_cfg___mode___lsb 21 | ||
| 133 | #define reg_bif_core_rw_grp3_cfg___mode___width 1 | ||
| 134 | #define reg_bif_core_rw_grp3_cfg___mode___bit 21 | ||
| 135 | #define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 | ||
| 136 | #define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 | ||
| 137 | #define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 | ||
| 138 | #define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 | ||
| 139 | #define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 | ||
| 140 | #define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 | ||
| 141 | #define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 | ||
| 142 | #define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 | ||
| 143 | #define reg_bif_core_rw_grp3_cfg_offset 8 | ||
| 144 | |||
| 145 | /* Register rw_grp4_cfg, scope bif_core, type rw */ | ||
| 146 | #define reg_bif_core_rw_grp4_cfg___lw___lsb 0 | ||
| 147 | #define reg_bif_core_rw_grp4_cfg___lw___width 6 | ||
| 148 | #define reg_bif_core_rw_grp4_cfg___ew___lsb 6 | ||
| 149 | #define reg_bif_core_rw_grp4_cfg___ew___width 3 | ||
| 150 | #define reg_bif_core_rw_grp4_cfg___zw___lsb 9 | ||
| 151 | #define reg_bif_core_rw_grp4_cfg___zw___width 3 | ||
| 152 | #define reg_bif_core_rw_grp4_cfg___aw___lsb 12 | ||
| 153 | #define reg_bif_core_rw_grp4_cfg___aw___width 2 | ||
| 154 | #define reg_bif_core_rw_grp4_cfg___dw___lsb 14 | ||
| 155 | #define reg_bif_core_rw_grp4_cfg___dw___width 2 | ||
| 156 | #define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 | ||
| 157 | #define reg_bif_core_rw_grp4_cfg___ewb___width 2 | ||
| 158 | #define reg_bif_core_rw_grp4_cfg___bw___lsb 18 | ||
| 159 | #define reg_bif_core_rw_grp4_cfg___bw___width 1 | ||
| 160 | #define reg_bif_core_rw_grp4_cfg___bw___bit 18 | ||
| 161 | #define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 | ||
| 162 | #define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 | ||
| 163 | #define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 | ||
| 164 | #define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 | ||
| 165 | #define reg_bif_core_rw_grp4_cfg___erc_en___width 1 | ||
| 166 | #define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 | ||
| 167 | #define reg_bif_core_rw_grp4_cfg___mode___lsb 21 | ||
| 168 | #define reg_bif_core_rw_grp4_cfg___mode___width 1 | ||
| 169 | #define reg_bif_core_rw_grp4_cfg___mode___bit 21 | ||
| 170 | #define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 | ||
| 171 | #define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 | ||
| 172 | #define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 | ||
| 173 | #define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 | ||
| 174 | #define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 | ||
| 175 | #define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 | ||
| 176 | #define reg_bif_core_rw_grp4_cfg_offset 12 | ||
| 177 | |||
| 178 | /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ | ||
| 179 | #define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 | ||
| 180 | #define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 | ||
| 181 | #define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 | ||
| 182 | #define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 | ||
| 183 | #define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 | ||
| 184 | #define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 | ||
| 185 | #define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 | ||
| 186 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 | ||
| 187 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 | ||
| 188 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 | ||
| 189 | #define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 | ||
| 190 | #define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 | ||
| 191 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 | ||
| 192 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 | ||
| 193 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 | ||
| 194 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 | ||
| 195 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 | ||
| 196 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 | ||
| 197 | #define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 | ||
| 198 | #define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 | ||
| 199 | #define reg_bif_core_rw_sdram_cfg_grp0_offset 16 | ||
| 200 | |||
| 201 | /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ | ||
| 202 | #define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 | ||
| 203 | #define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 | ||
| 204 | #define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 | ||
| 205 | #define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 | ||
| 206 | #define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 | ||
| 207 | #define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 | ||
| 208 | #define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 | ||
| 209 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 | ||
| 210 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 | ||
| 211 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 | ||
| 212 | #define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 | ||
| 213 | #define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 | ||
| 214 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 | ||
| 215 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 | ||
| 216 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 | ||
| 217 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 | ||
| 218 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 | ||
| 219 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 | ||
| 220 | #define reg_bif_core_rw_sdram_cfg_grp1_offset 20 | ||
| 221 | |||
| 222 | /* Register rw_sdram_timing, scope bif_core, type rw */ | ||
| 223 | #define reg_bif_core_rw_sdram_timing___cl___lsb 0 | ||
| 224 | #define reg_bif_core_rw_sdram_timing___cl___width 3 | ||
| 225 | #define reg_bif_core_rw_sdram_timing___rcd___lsb 3 | ||
| 226 | #define reg_bif_core_rw_sdram_timing___rcd___width 3 | ||
| 227 | #define reg_bif_core_rw_sdram_timing___rp___lsb 6 | ||
| 228 | #define reg_bif_core_rw_sdram_timing___rp___width 3 | ||
| 229 | #define reg_bif_core_rw_sdram_timing___rc___lsb 9 | ||
| 230 | #define reg_bif_core_rw_sdram_timing___rc___width 2 | ||
| 231 | #define reg_bif_core_rw_sdram_timing___dpl___lsb 11 | ||
| 232 | #define reg_bif_core_rw_sdram_timing___dpl___width 2 | ||
| 233 | #define reg_bif_core_rw_sdram_timing___pde___lsb 13 | ||
| 234 | #define reg_bif_core_rw_sdram_timing___pde___width 1 | ||
| 235 | #define reg_bif_core_rw_sdram_timing___pde___bit 13 | ||
| 236 | #define reg_bif_core_rw_sdram_timing___ref___lsb 14 | ||
| 237 | #define reg_bif_core_rw_sdram_timing___ref___width 2 | ||
| 238 | #define reg_bif_core_rw_sdram_timing___cpd___lsb 16 | ||
| 239 | #define reg_bif_core_rw_sdram_timing___cpd___width 1 | ||
| 240 | #define reg_bif_core_rw_sdram_timing___cpd___bit 16 | ||
| 241 | #define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 | ||
| 242 | #define reg_bif_core_rw_sdram_timing___sdcke___width 1 | ||
| 243 | #define reg_bif_core_rw_sdram_timing___sdcke___bit 17 | ||
| 244 | #define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 | ||
| 245 | #define reg_bif_core_rw_sdram_timing___sdclk___width 1 | ||
| 246 | #define reg_bif_core_rw_sdram_timing___sdclk___bit 18 | ||
| 247 | #define reg_bif_core_rw_sdram_timing_offset 24 | ||
| 248 | |||
| 249 | /* Register rw_sdram_cmd, scope bif_core, type rw */ | ||
| 250 | #define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 | ||
| 251 | #define reg_bif_core_rw_sdram_cmd___cmd___width 3 | ||
| 252 | #define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 | ||
| 253 | #define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 | ||
| 254 | #define reg_bif_core_rw_sdram_cmd_offset 28 | ||
| 255 | |||
| 256 | /* Register rs_sdram_ref_stat, scope bif_core, type rs */ | ||
| 257 | #define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 | ||
| 258 | #define reg_bif_core_rs_sdram_ref_stat___ok___width 1 | ||
| 259 | #define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 | ||
| 260 | #define reg_bif_core_rs_sdram_ref_stat_offset 32 | ||
| 261 | |||
| 262 | /* Register r_sdram_ref_stat, scope bif_core, type r */ | ||
| 263 | #define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 | ||
| 264 | #define reg_bif_core_r_sdram_ref_stat___ok___width 1 | ||
| 265 | #define reg_bif_core_r_sdram_ref_stat___ok___bit 0 | ||
| 266 | #define reg_bif_core_r_sdram_ref_stat_offset 36 | ||
| 267 | |||
| 268 | |||
| 269 | /* Constants */ | ||
| 270 | #define regk_bif_core_bank2 0x00000000 | ||
| 271 | #define regk_bif_core_bank4 0x00000001 | ||
| 272 | #define regk_bif_core_bit10 0x0000000a | ||
| 273 | #define regk_bif_core_bit11 0x0000000b | ||
| 274 | #define regk_bif_core_bit12 0x0000000c | ||
| 275 | #define regk_bif_core_bit13 0x0000000d | ||
| 276 | #define regk_bif_core_bit14 0x0000000e | ||
| 277 | #define regk_bif_core_bit15 0x0000000f | ||
| 278 | #define regk_bif_core_bit16 0x00000010 | ||
| 279 | #define regk_bif_core_bit17 0x00000011 | ||
| 280 | #define regk_bif_core_bit18 0x00000012 | ||
| 281 | #define regk_bif_core_bit19 0x00000013 | ||
| 282 | #define regk_bif_core_bit20 0x00000014 | ||
| 283 | #define regk_bif_core_bit21 0x00000015 | ||
| 284 | #define regk_bif_core_bit22 0x00000016 | ||
| 285 | #define regk_bif_core_bit23 0x00000017 | ||
| 286 | #define regk_bif_core_bit24 0x00000018 | ||
| 287 | #define regk_bif_core_bit25 0x00000019 | ||
| 288 | #define regk_bif_core_bit26 0x0000001a | ||
| 289 | #define regk_bif_core_bit27 0x0000001b | ||
| 290 | #define regk_bif_core_bit28 0x0000001c | ||
| 291 | #define regk_bif_core_bit29 0x0000001d | ||
| 292 | #define regk_bif_core_bit9 0x00000009 | ||
| 293 | #define regk_bif_core_bw16 0x00000001 | ||
| 294 | #define regk_bif_core_bw32 0x00000000 | ||
| 295 | #define regk_bif_core_bwe 0x00000000 | ||
| 296 | #define regk_bif_core_cwe 0x00000001 | ||
| 297 | #define regk_bif_core_e15us 0x00000001 | ||
| 298 | #define regk_bif_core_e7800ns 0x00000002 | ||
| 299 | #define regk_bif_core_grp0 0x00000000 | ||
| 300 | #define regk_bif_core_grp1 0x00000001 | ||
| 301 | #define regk_bif_core_mrs 0x00000003 | ||
| 302 | #define regk_bif_core_no 0x00000000 | ||
| 303 | #define regk_bif_core_none 0x00000000 | ||
| 304 | #define regk_bif_core_nop 0x00000000 | ||
| 305 | #define regk_bif_core_off 0x00000000 | ||
| 306 | #define regk_bif_core_pre 0x00000002 | ||
| 307 | #define regk_bif_core_r_sdram_ref_stat_default 0x00000001 | ||
| 308 | #define regk_bif_core_rd 0x00000002 | ||
| 309 | #define regk_bif_core_ref 0x00000001 | ||
| 310 | #define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 | ||
| 311 | #define regk_bif_core_rw_grp1_cfg_default 0x000006cf | ||
| 312 | #define regk_bif_core_rw_grp2_cfg_default 0x000006cf | ||
| 313 | #define regk_bif_core_rw_grp3_cfg_default 0x000006cf | ||
| 314 | #define regk_bif_core_rw_grp4_cfg_default 0x000006cf | ||
| 315 | #define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 | ||
| 316 | #define regk_bif_core_slf 0x00000004 | ||
| 317 | #define regk_bif_core_wr 0x00000001 | ||
| 318 | #define regk_bif_core_yes 0x00000001 | ||
| 319 | #endif /* __bif_core_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h deleted file mode 100644 index 71532aa18168..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h +++ /dev/null | |||
| @@ -1,495 +0,0 @@ | |||
| 1 | #ifndef __bif_dma_defs_asm_h | ||
| 2 | #define __bif_dma_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_dma_regs.r | ||
| 7 | * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r | ||
| 11 | * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_ch0_ctrl, scope bif_dma, type rw */ | ||
| 57 | #define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 | ||
| 58 | #define reg_bif_dma_rw_ch0_ctrl___bw___width 2 | ||
| 59 | #define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 | ||
| 60 | #define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 | ||
| 61 | #define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 | ||
| 62 | #define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 | ||
| 63 | #define reg_bif_dma_rw_ch0_ctrl___cont___width 1 | ||
| 64 | #define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 | ||
| 65 | #define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 | ||
| 66 | #define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 | ||
| 67 | #define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 | ||
| 68 | #define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 | ||
| 69 | #define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 | ||
| 70 | #define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 | ||
| 71 | #define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 | ||
| 72 | #define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 | ||
| 73 | #define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 | ||
| 74 | #define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 | ||
| 75 | #define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 | ||
| 76 | #define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 | ||
| 77 | #define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 | ||
| 78 | #define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 | ||
| 79 | #define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 | ||
| 80 | #define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 | ||
| 81 | #define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 | ||
| 82 | #define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 | ||
| 83 | #define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 | ||
| 84 | #define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 | ||
| 85 | #define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 | ||
| 86 | #define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 | ||
| 87 | #define reg_bif_dma_rw_ch0_ctrl_offset 0 | ||
| 88 | |||
| 89 | /* Register rw_ch0_addr, scope bif_dma, type rw */ | ||
| 90 | #define reg_bif_dma_rw_ch0_addr___addr___lsb 0 | ||
| 91 | #define reg_bif_dma_rw_ch0_addr___addr___width 32 | ||
| 92 | #define reg_bif_dma_rw_ch0_addr_offset 4 | ||
| 93 | |||
| 94 | /* Register rw_ch0_start, scope bif_dma, type rw */ | ||
| 95 | #define reg_bif_dma_rw_ch0_start___run___lsb 0 | ||
| 96 | #define reg_bif_dma_rw_ch0_start___run___width 1 | ||
| 97 | #define reg_bif_dma_rw_ch0_start___run___bit 0 | ||
| 98 | #define reg_bif_dma_rw_ch0_start_offset 8 | ||
| 99 | |||
| 100 | /* Register rw_ch0_cnt, scope bif_dma, type rw */ | ||
| 101 | #define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 | ||
| 102 | #define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 | ||
| 103 | #define reg_bif_dma_rw_ch0_cnt_offset 12 | ||
| 104 | |||
| 105 | /* Register r_ch0_stat, scope bif_dma, type r */ | ||
| 106 | #define reg_bif_dma_r_ch0_stat___cnt___lsb 0 | ||
| 107 | #define reg_bif_dma_r_ch0_stat___cnt___width 16 | ||
| 108 | #define reg_bif_dma_r_ch0_stat___run___lsb 31 | ||
| 109 | #define reg_bif_dma_r_ch0_stat___run___width 1 | ||
| 110 | #define reg_bif_dma_r_ch0_stat___run___bit 31 | ||
| 111 | #define reg_bif_dma_r_ch0_stat_offset 16 | ||
| 112 | |||
| 113 | /* Register rw_ch1_ctrl, scope bif_dma, type rw */ | ||
| 114 | #define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 | ||
| 115 | #define reg_bif_dma_rw_ch1_ctrl___bw___width 2 | ||
| 116 | #define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 | ||
| 117 | #define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 | ||
| 118 | #define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 | ||
| 119 | #define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 | ||
| 120 | #define reg_bif_dma_rw_ch1_ctrl___cont___width 1 | ||
| 121 | #define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 | ||
| 122 | #define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 | ||
| 123 | #define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 | ||
| 124 | #define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 | ||
| 125 | #define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 | ||
| 126 | #define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 | ||
| 127 | #define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 | ||
| 128 | #define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 | ||
| 129 | #define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 | ||
| 130 | #define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 | ||
| 131 | #define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 | ||
| 132 | #define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 | ||
| 133 | #define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 | ||
| 134 | #define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 | ||
| 135 | #define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 | ||
| 136 | #define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 | ||
| 137 | #define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 | ||
| 138 | #define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 | ||
| 139 | #define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 | ||
| 140 | #define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 | ||
| 141 | #define reg_bif_dma_rw_ch1_ctrl_offset 32 | ||
| 142 | |||
| 143 | /* Register rw_ch1_addr, scope bif_dma, type rw */ | ||
| 144 | #define reg_bif_dma_rw_ch1_addr___addr___lsb 0 | ||
| 145 | #define reg_bif_dma_rw_ch1_addr___addr___width 32 | ||
| 146 | #define reg_bif_dma_rw_ch1_addr_offset 36 | ||
| 147 | |||
| 148 | /* Register rw_ch1_start, scope bif_dma, type rw */ | ||
| 149 | #define reg_bif_dma_rw_ch1_start___run___lsb 0 | ||
| 150 | #define reg_bif_dma_rw_ch1_start___run___width 1 | ||
| 151 | #define reg_bif_dma_rw_ch1_start___run___bit 0 | ||
| 152 | #define reg_bif_dma_rw_ch1_start_offset 40 | ||
| 153 | |||
| 154 | /* Register rw_ch1_cnt, scope bif_dma, type rw */ | ||
| 155 | #define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 | ||
| 156 | #define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 | ||
| 157 | #define reg_bif_dma_rw_ch1_cnt_offset 44 | ||
| 158 | |||
| 159 | /* Register r_ch1_stat, scope bif_dma, type r */ | ||
| 160 | #define reg_bif_dma_r_ch1_stat___cnt___lsb 0 | ||
| 161 | #define reg_bif_dma_r_ch1_stat___cnt___width 16 | ||
| 162 | #define reg_bif_dma_r_ch1_stat___run___lsb 31 | ||
| 163 | #define reg_bif_dma_r_ch1_stat___run___width 1 | ||
| 164 | #define reg_bif_dma_r_ch1_stat___run___bit 31 | ||
| 165 | #define reg_bif_dma_r_ch1_stat_offset 48 | ||
| 166 | |||
| 167 | /* Register rw_ch2_ctrl, scope bif_dma, type rw */ | ||
| 168 | #define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 | ||
| 169 | #define reg_bif_dma_rw_ch2_ctrl___bw___width 2 | ||
| 170 | #define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 | ||
| 171 | #define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 | ||
| 172 | #define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 | ||
| 173 | #define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 | ||
| 174 | #define reg_bif_dma_rw_ch2_ctrl___cont___width 1 | ||
| 175 | #define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 | ||
| 176 | #define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 | ||
| 177 | #define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 | ||
| 178 | #define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 | ||
| 179 | #define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 | ||
| 180 | #define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 | ||
| 181 | #define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 | ||
| 182 | #define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 | ||
| 183 | #define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 | ||
| 184 | #define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 | ||
| 185 | #define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 | ||
| 186 | #define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 | ||
| 187 | #define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 | ||
| 188 | #define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 | ||
| 189 | #define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 | ||
| 190 | #define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 | ||
| 191 | #define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 | ||
| 192 | #define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 | ||
| 193 | #define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 | ||
| 194 | #define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 | ||
| 195 | #define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 | ||
| 196 | #define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 | ||
| 197 | #define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 | ||
| 198 | #define reg_bif_dma_rw_ch2_ctrl_offset 64 | ||
| 199 | |||
| 200 | /* Register rw_ch2_addr, scope bif_dma, type rw */ | ||
| 201 | #define reg_bif_dma_rw_ch2_addr___addr___lsb 0 | ||
| 202 | #define reg_bif_dma_rw_ch2_addr___addr___width 32 | ||
| 203 | #define reg_bif_dma_rw_ch2_addr_offset 68 | ||
| 204 | |||
| 205 | /* Register rw_ch2_start, scope bif_dma, type rw */ | ||
| 206 | #define reg_bif_dma_rw_ch2_start___run___lsb 0 | ||
| 207 | #define reg_bif_dma_rw_ch2_start___run___width 1 | ||
| 208 | #define reg_bif_dma_rw_ch2_start___run___bit 0 | ||
| 209 | #define reg_bif_dma_rw_ch2_start_offset 72 | ||
| 210 | |||
| 211 | /* Register rw_ch2_cnt, scope bif_dma, type rw */ | ||
| 212 | #define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 | ||
| 213 | #define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 | ||
| 214 | #define reg_bif_dma_rw_ch2_cnt_offset 76 | ||
| 215 | |||
| 216 | /* Register r_ch2_stat, scope bif_dma, type r */ | ||
| 217 | #define reg_bif_dma_r_ch2_stat___cnt___lsb 0 | ||
| 218 | #define reg_bif_dma_r_ch2_stat___cnt___width 16 | ||
| 219 | #define reg_bif_dma_r_ch2_stat___run___lsb 31 | ||
| 220 | #define reg_bif_dma_r_ch2_stat___run___width 1 | ||
| 221 | #define reg_bif_dma_r_ch2_stat___run___bit 31 | ||
| 222 | #define reg_bif_dma_r_ch2_stat_offset 80 | ||
| 223 | |||
| 224 | /* Register rw_ch3_ctrl, scope bif_dma, type rw */ | ||
| 225 | #define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 | ||
| 226 | #define reg_bif_dma_rw_ch3_ctrl___bw___width 2 | ||
| 227 | #define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 | ||
| 228 | #define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 | ||
| 229 | #define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 | ||
| 230 | #define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 | ||
| 231 | #define reg_bif_dma_rw_ch3_ctrl___cont___width 1 | ||
| 232 | #define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 | ||
| 233 | #define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 | ||
| 234 | #define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 | ||
| 235 | #define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 | ||
| 236 | #define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 | ||
| 237 | #define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 | ||
| 238 | #define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 | ||
| 239 | #define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 | ||
| 240 | #define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 | ||
| 241 | #define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 | ||
| 242 | #define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 | ||
| 243 | #define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 | ||
| 244 | #define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 | ||
| 245 | #define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 | ||
| 246 | #define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 | ||
| 247 | #define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 | ||
| 248 | #define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 | ||
| 249 | #define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 | ||
| 250 | #define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 | ||
| 251 | #define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 | ||
| 252 | #define reg_bif_dma_rw_ch3_ctrl_offset 96 | ||
| 253 | |||
| 254 | /* Register rw_ch3_addr, scope bif_dma, type rw */ | ||
| 255 | #define reg_bif_dma_rw_ch3_addr___addr___lsb 0 | ||
| 256 | #define reg_bif_dma_rw_ch3_addr___addr___width 32 | ||
| 257 | #define reg_bif_dma_rw_ch3_addr_offset 100 | ||
| 258 | |||
| 259 | /* Register rw_ch3_start, scope bif_dma, type rw */ | ||
| 260 | #define reg_bif_dma_rw_ch3_start___run___lsb 0 | ||
| 261 | #define reg_bif_dma_rw_ch3_start___run___width 1 | ||
| 262 | #define reg_bif_dma_rw_ch3_start___run___bit 0 | ||
| 263 | #define reg_bif_dma_rw_ch3_start_offset 104 | ||
| 264 | |||
| 265 | /* Register rw_ch3_cnt, scope bif_dma, type rw */ | ||
| 266 | #define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 | ||
| 267 | #define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 | ||
| 268 | #define reg_bif_dma_rw_ch3_cnt_offset 108 | ||
| 269 | |||
| 270 | /* Register r_ch3_stat, scope bif_dma, type r */ | ||
| 271 | #define reg_bif_dma_r_ch3_stat___cnt___lsb 0 | ||
| 272 | #define reg_bif_dma_r_ch3_stat___cnt___width 16 | ||
| 273 | #define reg_bif_dma_r_ch3_stat___run___lsb 31 | ||
| 274 | #define reg_bif_dma_r_ch3_stat___run___width 1 | ||
| 275 | #define reg_bif_dma_r_ch3_stat___run___bit 31 | ||
| 276 | #define reg_bif_dma_r_ch3_stat_offset 112 | ||
| 277 | |||
| 278 | /* Register rw_intr_mask, scope bif_dma, type rw */ | ||
| 279 | #define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 | ||
| 280 | #define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 | ||
| 281 | #define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 | ||
| 282 | #define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 | ||
| 283 | #define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 | ||
| 284 | #define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 | ||
| 285 | #define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 | ||
| 286 | #define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 | ||
| 287 | #define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 | ||
| 288 | #define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 | ||
| 289 | #define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 | ||
| 290 | #define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 | ||
| 291 | #define reg_bif_dma_rw_intr_mask_offset 128 | ||
| 292 | |||
| 293 | /* Register rw_ack_intr, scope bif_dma, type rw */ | ||
| 294 | #define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 | ||
| 295 | #define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 | ||
| 296 | #define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 | ||
| 297 | #define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 | ||
| 298 | #define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 | ||
| 299 | #define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 | ||
| 300 | #define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 | ||
| 301 | #define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 | ||
| 302 | #define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 | ||
| 303 | #define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 | ||
| 304 | #define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 | ||
| 305 | #define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 | ||
| 306 | #define reg_bif_dma_rw_ack_intr_offset 132 | ||
| 307 | |||
| 308 | /* Register r_intr, scope bif_dma, type r */ | ||
| 309 | #define reg_bif_dma_r_intr___ext_dma0___lsb 0 | ||
| 310 | #define reg_bif_dma_r_intr___ext_dma0___width 1 | ||
| 311 | #define reg_bif_dma_r_intr___ext_dma0___bit 0 | ||
| 312 | #define reg_bif_dma_r_intr___ext_dma1___lsb 1 | ||
| 313 | #define reg_bif_dma_r_intr___ext_dma1___width 1 | ||
| 314 | #define reg_bif_dma_r_intr___ext_dma1___bit 1 | ||
| 315 | #define reg_bif_dma_r_intr___ext_dma2___lsb 2 | ||
| 316 | #define reg_bif_dma_r_intr___ext_dma2___width 1 | ||
| 317 | #define reg_bif_dma_r_intr___ext_dma2___bit 2 | ||
| 318 | #define reg_bif_dma_r_intr___ext_dma3___lsb 3 | ||
| 319 | #define reg_bif_dma_r_intr___ext_dma3___width 1 | ||
| 320 | #define reg_bif_dma_r_intr___ext_dma3___bit 3 | ||
| 321 | #define reg_bif_dma_r_intr_offset 136 | ||
| 322 | |||
| 323 | /* Register r_masked_intr, scope bif_dma, type r */ | ||
| 324 | #define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 | ||
| 325 | #define reg_bif_dma_r_masked_intr___ext_dma0___width 1 | ||
| 326 | #define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 | ||
| 327 | #define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 | ||
| 328 | #define reg_bif_dma_r_masked_intr___ext_dma1___width 1 | ||
| 329 | #define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 | ||
| 330 | #define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 | ||
| 331 | #define reg_bif_dma_r_masked_intr___ext_dma2___width 1 | ||
| 332 | #define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 | ||
| 333 | #define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 | ||
| 334 | #define reg_bif_dma_r_masked_intr___ext_dma3___width 1 | ||
| 335 | #define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 | ||
| 336 | #define reg_bif_dma_r_masked_intr_offset 140 | ||
| 337 | |||
| 338 | /* Register rw_pin0_cfg, scope bif_dma, type rw */ | ||
| 339 | #define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 | ||
| 340 | #define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 | ||
| 341 | #define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 | ||
| 342 | #define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 | ||
| 343 | #define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 | ||
| 344 | #define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 | ||
| 345 | #define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 | ||
| 346 | #define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 | ||
| 347 | #define reg_bif_dma_rw_pin0_cfg_offset 160 | ||
| 348 | |||
| 349 | /* Register rw_pin1_cfg, scope bif_dma, type rw */ | ||
| 350 | #define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 | ||
| 351 | #define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 | ||
| 352 | #define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 | ||
| 353 | #define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 | ||
| 354 | #define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 | ||
| 355 | #define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 | ||
| 356 | #define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 | ||
| 357 | #define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 | ||
| 358 | #define reg_bif_dma_rw_pin1_cfg_offset 164 | ||
| 359 | |||
| 360 | /* Register rw_pin2_cfg, scope bif_dma, type rw */ | ||
| 361 | #define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 | ||
| 362 | #define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 | ||
| 363 | #define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 | ||
| 364 | #define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 | ||
| 365 | #define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 | ||
| 366 | #define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 | ||
| 367 | #define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 | ||
| 368 | #define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 | ||
| 369 | #define reg_bif_dma_rw_pin2_cfg_offset 168 | ||
| 370 | |||
| 371 | /* Register rw_pin3_cfg, scope bif_dma, type rw */ | ||
| 372 | #define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 | ||
| 373 | #define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 | ||
| 374 | #define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 | ||
| 375 | #define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 | ||
| 376 | #define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 | ||
| 377 | #define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 | ||
| 378 | #define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 | ||
| 379 | #define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 | ||
| 380 | #define reg_bif_dma_rw_pin3_cfg_offset 172 | ||
| 381 | |||
| 382 | /* Register rw_pin4_cfg, scope bif_dma, type rw */ | ||
| 383 | #define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 | ||
| 384 | #define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 | ||
| 385 | #define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 | ||
| 386 | #define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 | ||
| 387 | #define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 | ||
| 388 | #define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 | ||
| 389 | #define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 | ||
| 390 | #define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 | ||
| 391 | #define reg_bif_dma_rw_pin4_cfg_offset 176 | ||
| 392 | |||
| 393 | /* Register rw_pin5_cfg, scope bif_dma, type rw */ | ||
| 394 | #define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 | ||
| 395 | #define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 | ||
| 396 | #define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 | ||
| 397 | #define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 | ||
| 398 | #define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 | ||
| 399 | #define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 | ||
| 400 | #define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 | ||
| 401 | #define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 | ||
| 402 | #define reg_bif_dma_rw_pin5_cfg_offset 180 | ||
| 403 | |||
| 404 | /* Register rw_pin6_cfg, scope bif_dma, type rw */ | ||
| 405 | #define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 | ||
| 406 | #define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 | ||
| 407 | #define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 | ||
| 408 | #define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 | ||
| 409 | #define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 | ||
| 410 | #define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 | ||
| 411 | #define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 | ||
| 412 | #define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 | ||
| 413 | #define reg_bif_dma_rw_pin6_cfg_offset 184 | ||
| 414 | |||
| 415 | /* Register rw_pin7_cfg, scope bif_dma, type rw */ | ||
| 416 | #define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 | ||
| 417 | #define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 | ||
| 418 | #define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 | ||
| 419 | #define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 | ||
| 420 | #define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 | ||
| 421 | #define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 | ||
| 422 | #define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 | ||
| 423 | #define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 | ||
| 424 | #define reg_bif_dma_rw_pin7_cfg_offset 188 | ||
| 425 | |||
| 426 | /* Register r_pin_stat, scope bif_dma, type r */ | ||
| 427 | #define reg_bif_dma_r_pin_stat___pin0___lsb 0 | ||
| 428 | #define reg_bif_dma_r_pin_stat___pin0___width 1 | ||
| 429 | #define reg_bif_dma_r_pin_stat___pin0___bit 0 | ||
| 430 | #define reg_bif_dma_r_pin_stat___pin1___lsb 1 | ||
| 431 | #define reg_bif_dma_r_pin_stat___pin1___width 1 | ||
| 432 | #define reg_bif_dma_r_pin_stat___pin1___bit 1 | ||
| 433 | #define reg_bif_dma_r_pin_stat___pin2___lsb 2 | ||
| 434 | #define reg_bif_dma_r_pin_stat___pin2___width 1 | ||
| 435 | #define reg_bif_dma_r_pin_stat___pin2___bit 2 | ||
| 436 | #define reg_bif_dma_r_pin_stat___pin3___lsb 3 | ||
| 437 | #define reg_bif_dma_r_pin_stat___pin3___width 1 | ||
| 438 | #define reg_bif_dma_r_pin_stat___pin3___bit 3 | ||
| 439 | #define reg_bif_dma_r_pin_stat___pin4___lsb 4 | ||
| 440 | #define reg_bif_dma_r_pin_stat___pin4___width 1 | ||
| 441 | #define reg_bif_dma_r_pin_stat___pin4___bit 4 | ||
| 442 | #define reg_bif_dma_r_pin_stat___pin5___lsb 5 | ||
| 443 | #define reg_bif_dma_r_pin_stat___pin5___width 1 | ||
| 444 | #define reg_bif_dma_r_pin_stat___pin5___bit 5 | ||
| 445 | #define reg_bif_dma_r_pin_stat___pin6___lsb 6 | ||
| 446 | #define reg_bif_dma_r_pin_stat___pin6___width 1 | ||
| 447 | #define reg_bif_dma_r_pin_stat___pin6___bit 6 | ||
| 448 | #define reg_bif_dma_r_pin_stat___pin7___lsb 7 | ||
| 449 | #define reg_bif_dma_r_pin_stat___pin7___width 1 | ||
| 450 | #define reg_bif_dma_r_pin_stat___pin7___bit 7 | ||
| 451 | #define reg_bif_dma_r_pin_stat_offset 192 | ||
| 452 | |||
| 453 | |||
| 454 | /* Constants */ | ||
| 455 | #define regk_bif_dma_as_master 0x00000001 | ||
| 456 | #define regk_bif_dma_as_slave 0x00000001 | ||
| 457 | #define regk_bif_dma_burst1 0x00000000 | ||
| 458 | #define regk_bif_dma_burst8 0x00000001 | ||
| 459 | #define regk_bif_dma_bw16 0x00000001 | ||
| 460 | #define regk_bif_dma_bw32 0x00000002 | ||
| 461 | #define regk_bif_dma_bw8 0x00000000 | ||
| 462 | #define regk_bif_dma_dack 0x00000006 | ||
| 463 | #define regk_bif_dma_dack_inv 0x00000007 | ||
| 464 | #define regk_bif_dma_force 0x00000001 | ||
| 465 | #define regk_bif_dma_hi 0x00000003 | ||
| 466 | #define regk_bif_dma_inv 0x00000003 | ||
| 467 | #define regk_bif_dma_lo 0x00000002 | ||
| 468 | #define regk_bif_dma_master 0x00000001 | ||
| 469 | #define regk_bif_dma_no 0x00000000 | ||
| 470 | #define regk_bif_dma_norm 0x00000002 | ||
| 471 | #define regk_bif_dma_off 0x00000000 | ||
| 472 | #define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 | ||
| 473 | #define regk_bif_dma_rw_ch0_start_default 0x00000000 | ||
| 474 | #define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 | ||
| 475 | #define regk_bif_dma_rw_ch1_start_default 0x00000000 | ||
| 476 | #define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 | ||
| 477 | #define regk_bif_dma_rw_ch2_start_default 0x00000000 | ||
| 478 | #define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 | ||
| 479 | #define regk_bif_dma_rw_ch3_start_default 0x00000000 | ||
| 480 | #define regk_bif_dma_rw_intr_mask_default 0x00000000 | ||
| 481 | #define regk_bif_dma_rw_pin0_cfg_default 0x00000000 | ||
| 482 | #define regk_bif_dma_rw_pin1_cfg_default 0x00000000 | ||
| 483 | #define regk_bif_dma_rw_pin2_cfg_default 0x00000000 | ||
| 484 | #define regk_bif_dma_rw_pin3_cfg_default 0x00000000 | ||
| 485 | #define regk_bif_dma_rw_pin4_cfg_default 0x00000000 | ||
| 486 | #define regk_bif_dma_rw_pin5_cfg_default 0x00000000 | ||
| 487 | #define regk_bif_dma_rw_pin6_cfg_default 0x00000000 | ||
| 488 | #define regk_bif_dma_rw_pin7_cfg_default 0x00000000 | ||
| 489 | #define regk_bif_dma_slave 0x00000002 | ||
| 490 | #define regk_bif_dma_sreq 0x00000006 | ||
| 491 | #define regk_bif_dma_sreq_inv 0x00000007 | ||
| 492 | #define regk_bif_dma_tc 0x00000004 | ||
| 493 | #define regk_bif_dma_tc_inv 0x00000005 | ||
| 494 | #define regk_bif_dma_yes 0x00000001 | ||
| 495 | #endif /* __bif_dma_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h deleted file mode 100644 index 031f33a365bb..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h +++ /dev/null | |||
| @@ -1,249 +0,0 @@ | |||
| 1 | #ifndef __bif_slave_defs_asm_h | ||
| 2 | #define __bif_slave_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_slave_regs.r | ||
| 7 | * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:34 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r | ||
| 11 | * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_slave_cfg, scope bif_slave, type rw */ | ||
| 57 | #define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 | ||
| 58 | #define reg_bif_slave_rw_slave_cfg___slave_id___width 3 | ||
| 59 | #define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 | ||
| 60 | #define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 | ||
| 61 | #define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 | ||
| 62 | #define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 | ||
| 63 | #define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 | ||
| 64 | #define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 | ||
| 65 | #define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 | ||
| 66 | #define reg_bif_slave_rw_slave_cfg___loopback___width 1 | ||
| 67 | #define reg_bif_slave_rw_slave_cfg___loopback___bit 5 | ||
| 68 | #define reg_bif_slave_rw_slave_cfg___dis___lsb 6 | ||
| 69 | #define reg_bif_slave_rw_slave_cfg___dis___width 1 | ||
| 70 | #define reg_bif_slave_rw_slave_cfg___dis___bit 6 | ||
| 71 | #define reg_bif_slave_rw_slave_cfg_offset 0 | ||
| 72 | |||
| 73 | /* Register r_slave_mode, scope bif_slave, type r */ | ||
| 74 | #define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 | ||
| 75 | #define reg_bif_slave_r_slave_mode___ch0_mode___width 1 | ||
| 76 | #define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 | ||
| 77 | #define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 | ||
| 78 | #define reg_bif_slave_r_slave_mode___ch1_mode___width 1 | ||
| 79 | #define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 | ||
| 80 | #define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 | ||
| 81 | #define reg_bif_slave_r_slave_mode___ch2_mode___width 1 | ||
| 82 | #define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 | ||
| 83 | #define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 | ||
| 84 | #define reg_bif_slave_r_slave_mode___ch3_mode___width 1 | ||
| 85 | #define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 | ||
| 86 | #define reg_bif_slave_r_slave_mode_offset 4 | ||
| 87 | |||
| 88 | /* Register rw_ch0_cfg, scope bif_slave, type rw */ | ||
| 89 | #define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 | ||
| 90 | #define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 | ||
| 91 | #define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 | ||
| 92 | #define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 | ||
| 93 | #define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 | ||
| 94 | #define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 | ||
| 95 | #define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 | ||
| 96 | #define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 | ||
| 97 | #define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 | ||
| 98 | #define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 | ||
| 99 | #define reg_bif_slave_rw_ch0_cfg_offset 16 | ||
| 100 | |||
| 101 | /* Register rw_ch1_cfg, scope bif_slave, type rw */ | ||
| 102 | #define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 | ||
| 103 | #define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 | ||
| 104 | #define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 | ||
| 105 | #define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 | ||
| 106 | #define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 | ||
| 107 | #define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 | ||
| 108 | #define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 | ||
| 109 | #define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 | ||
| 110 | #define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 | ||
| 111 | #define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 | ||
| 112 | #define reg_bif_slave_rw_ch1_cfg_offset 20 | ||
| 113 | |||
| 114 | /* Register rw_ch2_cfg, scope bif_slave, type rw */ | ||
| 115 | #define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 | ||
| 116 | #define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 | ||
| 117 | #define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 | ||
| 118 | #define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 | ||
| 119 | #define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 | ||
| 120 | #define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 | ||
| 121 | #define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 | ||
| 122 | #define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 | ||
| 123 | #define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 | ||
| 124 | #define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 | ||
| 125 | #define reg_bif_slave_rw_ch2_cfg_offset 24 | ||
| 126 | |||
| 127 | /* Register rw_ch3_cfg, scope bif_slave, type rw */ | ||
| 128 | #define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 | ||
| 129 | #define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 | ||
| 130 | #define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 | ||
| 131 | #define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 | ||
| 132 | #define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 | ||
| 133 | #define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 | ||
| 134 | #define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 | ||
| 135 | #define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 | ||
| 136 | #define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 | ||
| 137 | #define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 | ||
| 138 | #define reg_bif_slave_rw_ch3_cfg_offset 28 | ||
| 139 | |||
| 140 | /* Register rw_arb_cfg, scope bif_slave, type rw */ | ||
| 141 | #define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 | ||
| 142 | #define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 | ||
| 143 | #define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 | ||
| 144 | #define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 | ||
| 145 | #define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 | ||
| 146 | #define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 | ||
| 147 | #define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 | ||
| 148 | #define reg_bif_slave_rw_arb_cfg___release___lsb 7 | ||
| 149 | #define reg_bif_slave_rw_arb_cfg___release___width 2 | ||
| 150 | #define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 | ||
| 151 | #define reg_bif_slave_rw_arb_cfg___acquire___width 1 | ||
| 152 | #define reg_bif_slave_rw_arb_cfg___acquire___bit 9 | ||
| 153 | #define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 | ||
| 154 | #define reg_bif_slave_rw_arb_cfg___settle_time___width 2 | ||
| 155 | #define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 | ||
| 156 | #define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 | ||
| 157 | #define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 | ||
| 158 | #define reg_bif_slave_rw_arb_cfg_offset 32 | ||
| 159 | |||
| 160 | /* Register r_arb_stat, scope bif_slave, type r */ | ||
| 161 | #define reg_bif_slave_r_arb_stat___init_mode___lsb 0 | ||
| 162 | #define reg_bif_slave_r_arb_stat___init_mode___width 1 | ||
| 163 | #define reg_bif_slave_r_arb_stat___init_mode___bit 0 | ||
| 164 | #define reg_bif_slave_r_arb_stat___mode___lsb 1 | ||
| 165 | #define reg_bif_slave_r_arb_stat___mode___width 1 | ||
| 166 | #define reg_bif_slave_r_arb_stat___mode___bit 1 | ||
| 167 | #define reg_bif_slave_r_arb_stat___brin___lsb 2 | ||
| 168 | #define reg_bif_slave_r_arb_stat___brin___width 1 | ||
| 169 | #define reg_bif_slave_r_arb_stat___brin___bit 2 | ||
| 170 | #define reg_bif_slave_r_arb_stat___brout___lsb 3 | ||
| 171 | #define reg_bif_slave_r_arb_stat___brout___width 1 | ||
| 172 | #define reg_bif_slave_r_arb_stat___brout___bit 3 | ||
| 173 | #define reg_bif_slave_r_arb_stat___bg___lsb 4 | ||
| 174 | #define reg_bif_slave_r_arb_stat___bg___width 1 | ||
| 175 | #define reg_bif_slave_r_arb_stat___bg___bit 4 | ||
| 176 | #define reg_bif_slave_r_arb_stat_offset 36 | ||
| 177 | |||
| 178 | /* Register rw_intr_mask, scope bif_slave, type rw */ | ||
| 179 | #define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 | ||
| 180 | #define reg_bif_slave_rw_intr_mask___bus_release___width 1 | ||
| 181 | #define reg_bif_slave_rw_intr_mask___bus_release___bit 0 | ||
| 182 | #define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 | ||
| 183 | #define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 | ||
| 184 | #define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 | ||
| 185 | #define reg_bif_slave_rw_intr_mask_offset 64 | ||
| 186 | |||
| 187 | /* Register rw_ack_intr, scope bif_slave, type rw */ | ||
| 188 | #define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 | ||
| 189 | #define reg_bif_slave_rw_ack_intr___bus_release___width 1 | ||
| 190 | #define reg_bif_slave_rw_ack_intr___bus_release___bit 0 | ||
| 191 | #define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 | ||
| 192 | #define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 | ||
| 193 | #define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 | ||
| 194 | #define reg_bif_slave_rw_ack_intr_offset 68 | ||
| 195 | |||
| 196 | /* Register r_intr, scope bif_slave, type r */ | ||
| 197 | #define reg_bif_slave_r_intr___bus_release___lsb 0 | ||
| 198 | #define reg_bif_slave_r_intr___bus_release___width 1 | ||
| 199 | #define reg_bif_slave_r_intr___bus_release___bit 0 | ||
| 200 | #define reg_bif_slave_r_intr___bus_acquire___lsb 1 | ||
| 201 | #define reg_bif_slave_r_intr___bus_acquire___width 1 | ||
| 202 | #define reg_bif_slave_r_intr___bus_acquire___bit 1 | ||
| 203 | #define reg_bif_slave_r_intr_offset 72 | ||
| 204 | |||
| 205 | /* Register r_masked_intr, scope bif_slave, type r */ | ||
| 206 | #define reg_bif_slave_r_masked_intr___bus_release___lsb 0 | ||
| 207 | #define reg_bif_slave_r_masked_intr___bus_release___width 1 | ||
| 208 | #define reg_bif_slave_r_masked_intr___bus_release___bit 0 | ||
| 209 | #define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 | ||
| 210 | #define reg_bif_slave_r_masked_intr___bus_acquire___width 1 | ||
| 211 | #define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 | ||
| 212 | #define reg_bif_slave_r_masked_intr_offset 76 | ||
| 213 | |||
| 214 | |||
| 215 | /* Constants */ | ||
| 216 | #define regk_bif_slave_active_hi 0x00000003 | ||
| 217 | #define regk_bif_slave_active_lo 0x00000002 | ||
| 218 | #define regk_bif_slave_addr 0x00000000 | ||
| 219 | #define regk_bif_slave_always 0x00000001 | ||
| 220 | #define regk_bif_slave_at_idle 0x00000002 | ||
| 221 | #define regk_bif_slave_burst_end 0x00000003 | ||
| 222 | #define regk_bif_slave_dma 0x00000001 | ||
| 223 | #define regk_bif_slave_hi 0x00000003 | ||
| 224 | #define regk_bif_slave_inv 0x00000001 | ||
| 225 | #define regk_bif_slave_lo 0x00000002 | ||
| 226 | #define regk_bif_slave_local 0x00000001 | ||
| 227 | #define regk_bif_slave_master 0x00000000 | ||
| 228 | #define regk_bif_slave_mode_reg 0x00000001 | ||
| 229 | #define regk_bif_slave_no 0x00000000 | ||
| 230 | #define regk_bif_slave_norm 0x00000000 | ||
| 231 | #define regk_bif_slave_on_access 0x00000000 | ||
| 232 | #define regk_bif_slave_rw_arb_cfg_default 0x00000000 | ||
| 233 | #define regk_bif_slave_rw_ch0_cfg_default 0x00000000 | ||
| 234 | #define regk_bif_slave_rw_ch1_cfg_default 0x00000000 | ||
| 235 | #define regk_bif_slave_rw_ch2_cfg_default 0x00000000 | ||
| 236 | #define regk_bif_slave_rw_ch3_cfg_default 0x00000000 | ||
| 237 | #define regk_bif_slave_rw_intr_mask_default 0x00000000 | ||
| 238 | #define regk_bif_slave_rw_slave_cfg_default 0x00000000 | ||
| 239 | #define regk_bif_slave_shared 0x00000000 | ||
| 240 | #define regk_bif_slave_slave 0x00000001 | ||
| 241 | #define regk_bif_slave_t0ns 0x00000003 | ||
| 242 | #define regk_bif_slave_t10ns 0x00000002 | ||
| 243 | #define regk_bif_slave_t20ns 0x00000003 | ||
| 244 | #define regk_bif_slave_t30ns 0x00000002 | ||
| 245 | #define regk_bif_slave_t40ns 0x00000001 | ||
| 246 | #define regk_bif_slave_t50ns 0x00000000 | ||
| 247 | #define regk_bif_slave_yes 0x00000001 | ||
| 248 | #define regk_bif_slave_z 0x00000004 | ||
| 249 | #endif /* __bif_slave_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h deleted file mode 100644 index e98476332e1f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h +++ /dev/null | |||
| @@ -1,131 +0,0 @@ | |||
| 1 | #ifndef __config_defs_asm_h | ||
| 2 | #define __config_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../rtl/config_regs.r | ||
| 7 | * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp | ||
| 8 | * last modfied: Thu Mar 4 12:34:39 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r | ||
| 11 | * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register r_bootsel, scope config, type r */ | ||
| 57 | #define reg_config_r_bootsel___boot_mode___lsb 0 | ||
| 58 | #define reg_config_r_bootsel___boot_mode___width 3 | ||
| 59 | #define reg_config_r_bootsel___full_duplex___lsb 3 | ||
| 60 | #define reg_config_r_bootsel___full_duplex___width 1 | ||
| 61 | #define reg_config_r_bootsel___full_duplex___bit 3 | ||
| 62 | #define reg_config_r_bootsel___user___lsb 4 | ||
| 63 | #define reg_config_r_bootsel___user___width 1 | ||
| 64 | #define reg_config_r_bootsel___user___bit 4 | ||
| 65 | #define reg_config_r_bootsel___pll___lsb 5 | ||
| 66 | #define reg_config_r_bootsel___pll___width 1 | ||
| 67 | #define reg_config_r_bootsel___pll___bit 5 | ||
| 68 | #define reg_config_r_bootsel___flash_bw___lsb 6 | ||
| 69 | #define reg_config_r_bootsel___flash_bw___width 1 | ||
| 70 | #define reg_config_r_bootsel___flash_bw___bit 6 | ||
| 71 | #define reg_config_r_bootsel_offset 0 | ||
| 72 | |||
| 73 | /* Register rw_clk_ctrl, scope config, type rw */ | ||
| 74 | #define reg_config_rw_clk_ctrl___pll___lsb 0 | ||
| 75 | #define reg_config_rw_clk_ctrl___pll___width 1 | ||
| 76 | #define reg_config_rw_clk_ctrl___pll___bit 0 | ||
| 77 | #define reg_config_rw_clk_ctrl___cpu___lsb 1 | ||
| 78 | #define reg_config_rw_clk_ctrl___cpu___width 1 | ||
| 79 | #define reg_config_rw_clk_ctrl___cpu___bit 1 | ||
| 80 | #define reg_config_rw_clk_ctrl___iop___lsb 2 | ||
| 81 | #define reg_config_rw_clk_ctrl___iop___width 1 | ||
| 82 | #define reg_config_rw_clk_ctrl___iop___bit 2 | ||
| 83 | #define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 | ||
| 84 | #define reg_config_rw_clk_ctrl___dma01_eth0___width 1 | ||
| 85 | #define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 | ||
| 86 | #define reg_config_rw_clk_ctrl___dma23___lsb 4 | ||
| 87 | #define reg_config_rw_clk_ctrl___dma23___width 1 | ||
| 88 | #define reg_config_rw_clk_ctrl___dma23___bit 4 | ||
| 89 | #define reg_config_rw_clk_ctrl___dma45___lsb 5 | ||
| 90 | #define reg_config_rw_clk_ctrl___dma45___width 1 | ||
| 91 | #define reg_config_rw_clk_ctrl___dma45___bit 5 | ||
| 92 | #define reg_config_rw_clk_ctrl___dma67___lsb 6 | ||
| 93 | #define reg_config_rw_clk_ctrl___dma67___width 1 | ||
| 94 | #define reg_config_rw_clk_ctrl___dma67___bit 6 | ||
| 95 | #define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 | ||
| 96 | #define reg_config_rw_clk_ctrl___dma89_strcop___width 1 | ||
| 97 | #define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 | ||
| 98 | #define reg_config_rw_clk_ctrl___bif___lsb 8 | ||
| 99 | #define reg_config_rw_clk_ctrl___bif___width 1 | ||
| 100 | #define reg_config_rw_clk_ctrl___bif___bit 8 | ||
| 101 | #define reg_config_rw_clk_ctrl___fix_io___lsb 9 | ||
| 102 | #define reg_config_rw_clk_ctrl___fix_io___width 1 | ||
| 103 | #define reg_config_rw_clk_ctrl___fix_io___bit 9 | ||
| 104 | #define reg_config_rw_clk_ctrl_offset 4 | ||
| 105 | |||
| 106 | /* Register rw_pad_ctrl, scope config, type rw */ | ||
| 107 | #define reg_config_rw_pad_ctrl___usb_susp___lsb 0 | ||
| 108 | #define reg_config_rw_pad_ctrl___usb_susp___width 1 | ||
| 109 | #define reg_config_rw_pad_ctrl___usb_susp___bit 0 | ||
| 110 | #define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 | ||
| 111 | #define reg_config_rw_pad_ctrl___phyrst_n___width 1 | ||
| 112 | #define reg_config_rw_pad_ctrl___phyrst_n___bit 1 | ||
| 113 | #define reg_config_rw_pad_ctrl_offset 8 | ||
| 114 | |||
| 115 | |||
| 116 | /* Constants */ | ||
| 117 | #define regk_config_bw16 0x00000000 | ||
| 118 | #define regk_config_bw32 0x00000001 | ||
| 119 | #define regk_config_master 0x00000005 | ||
| 120 | #define regk_config_nand 0x00000003 | ||
| 121 | #define regk_config_net_rx 0x00000001 | ||
| 122 | #define regk_config_net_tx_rx 0x00000002 | ||
| 123 | #define regk_config_no 0x00000000 | ||
| 124 | #define regk_config_none 0x00000007 | ||
| 125 | #define regk_config_nor 0x00000000 | ||
| 126 | #define regk_config_rw_clk_ctrl_default 0x00000002 | ||
| 127 | #define regk_config_rw_pad_ctrl_default 0x00000000 | ||
| 128 | #define regk_config_ser 0x00000004 | ||
| 129 | #define regk_config_slave 0x00000006 | ||
| 130 | #define regk_config_yes 0x00000001 | ||
| 131 | #endif /* __config_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version | ||
| 2 | from ../../inst/crisp/doc/cpu_vect.r | ||
| 3 | version . */ | ||
| 4 | |||
| 5 | #ifndef _______INST_CRISP_DOC_CPU_VECT_R | ||
| 6 | #define _______INST_CRISP_DOC_CPU_VECT_R | ||
| 7 | #define NMI_INTR_VECT 0x00 | ||
| 8 | #define RESERVED_1_INTR_VECT 0x01 | ||
| 9 | #define RESERVED_2_INTR_VECT 0x02 | ||
| 10 | #define SINGLE_STEP_INTR_VECT 0x03 | ||
| 11 | #define INSTR_TLB_REFILL_INTR_VECT 0x04 | ||
| 12 | #define INSTR_TLB_INV_INTR_VECT 0x05 | ||
| 13 | #define INSTR_TLB_ACC_INTR_VECT 0x06 | ||
| 14 | #define TLB_EX_INTR_VECT 0x07 | ||
| 15 | #define DATA_TLB_REFILL_INTR_VECT 0x08 | ||
| 16 | #define DATA_TLB_INV_INTR_VECT 0x09 | ||
| 17 | #define DATA_TLB_ACC_INTR_VECT 0x0a | ||
| 18 | #define DATA_TLB_WE_INTR_VECT 0x0b | ||
| 19 | #define HW_BP_INTR_VECT 0x0c | ||
| 20 | #define RESERVED_D_INTR_VECT 0x0d | ||
| 21 | #define RESERVED_E_INTR_VECT 0x0e | ||
| 22 | #define RESERVED_F_INTR_VECT 0x0f | ||
| 23 | #define BREAK_0_INTR_VECT 0x10 | ||
| 24 | #define BREAK_1_INTR_VECT 0x11 | ||
| 25 | #define BREAK_2_INTR_VECT 0x12 | ||
| 26 | #define BREAK_3_INTR_VECT 0x13 | ||
| 27 | #define BREAK_4_INTR_VECT 0x14 | ||
| 28 | #define BREAK_5_INTR_VECT 0x15 | ||
| 29 | #define BREAK_6_INTR_VECT 0x16 | ||
| 30 | #define BREAK_7_INTR_VECT 0x17 | ||
| 31 | #define BREAK_8_INTR_VECT 0x18 | ||
| 32 | #define BREAK_9_INTR_VECT 0x19 | ||
| 33 | #define BREAK_10_INTR_VECT 0x1a | ||
| 34 | #define BREAK_11_INTR_VECT 0x1b | ||
| 35 | #define BREAK_12_INTR_VECT 0x1c | ||
| 36 | #define BREAK_13_INTR_VECT 0x1d | ||
| 37 | #define BREAK_14_INTR_VECT 0x1e | ||
| 38 | #define BREAK_15_INTR_VECT 0x1f | ||
| 39 | #define MULTIPLE_INTR_VECT 0x30 | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h deleted file mode 100644 index 7f768db272e2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h +++ /dev/null | |||
| @@ -1,114 +0,0 @@ | |||
| 1 | #ifndef __cris_defs_asm_h | ||
| 2 | #define __cris_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/crisp/doc/cris.r | ||
| 7 | * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:39 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r | ||
| 11 | * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_gc_cfg, scope cris, type rw */ | ||
| 57 | #define reg_cris_rw_gc_cfg___ic___lsb 0 | ||
| 58 | #define reg_cris_rw_gc_cfg___ic___width 1 | ||
| 59 | #define reg_cris_rw_gc_cfg___ic___bit 0 | ||
| 60 | #define reg_cris_rw_gc_cfg___dc___lsb 1 | ||
| 61 | #define reg_cris_rw_gc_cfg___dc___width 1 | ||
| 62 | #define reg_cris_rw_gc_cfg___dc___bit 1 | ||
| 63 | #define reg_cris_rw_gc_cfg___im___lsb 2 | ||
| 64 | #define reg_cris_rw_gc_cfg___im___width 1 | ||
| 65 | #define reg_cris_rw_gc_cfg___im___bit 2 | ||
| 66 | #define reg_cris_rw_gc_cfg___dm___lsb 3 | ||
| 67 | #define reg_cris_rw_gc_cfg___dm___width 1 | ||
| 68 | #define reg_cris_rw_gc_cfg___dm___bit 3 | ||
| 69 | #define reg_cris_rw_gc_cfg___gb___lsb 4 | ||
| 70 | #define reg_cris_rw_gc_cfg___gb___width 1 | ||
| 71 | #define reg_cris_rw_gc_cfg___gb___bit 4 | ||
| 72 | #define reg_cris_rw_gc_cfg___gk___lsb 5 | ||
| 73 | #define reg_cris_rw_gc_cfg___gk___width 1 | ||
| 74 | #define reg_cris_rw_gc_cfg___gk___bit 5 | ||
| 75 | #define reg_cris_rw_gc_cfg___gp___lsb 6 | ||
| 76 | #define reg_cris_rw_gc_cfg___gp___width 1 | ||
| 77 | #define reg_cris_rw_gc_cfg___gp___bit 6 | ||
| 78 | #define reg_cris_rw_gc_cfg_offset 0 | ||
| 79 | |||
| 80 | /* Register rw_gc_ccs, scope cris, type rw */ | ||
| 81 | #define reg_cris_rw_gc_ccs_offset 4 | ||
| 82 | |||
| 83 | /* Register rw_gc_srs, scope cris, type rw */ | ||
| 84 | #define reg_cris_rw_gc_srs___srs___lsb 0 | ||
| 85 | #define reg_cris_rw_gc_srs___srs___width 8 | ||
| 86 | #define reg_cris_rw_gc_srs_offset 8 | ||
| 87 | |||
| 88 | /* Register rw_gc_nrp, scope cris, type rw */ | ||
| 89 | #define reg_cris_rw_gc_nrp_offset 12 | ||
| 90 | |||
| 91 | /* Register rw_gc_exs, scope cris, type rw */ | ||
| 92 | #define reg_cris_rw_gc_exs_offset 16 | ||
| 93 | |||
| 94 | /* Register rw_gc_eda, scope cris, type rw */ | ||
| 95 | #define reg_cris_rw_gc_eda_offset 20 | ||
| 96 | |||
| 97 | /* Register rw_gc_r0, scope cris, type rw */ | ||
| 98 | #define reg_cris_rw_gc_r0_offset 32 | ||
| 99 | |||
| 100 | /* Register rw_gc_r1, scope cris, type rw */ | ||
| 101 | #define reg_cris_rw_gc_r1_offset 36 | ||
| 102 | |||
| 103 | /* Register rw_gc_r2, scope cris, type rw */ | ||
| 104 | #define reg_cris_rw_gc_r2_offset 40 | ||
| 105 | |||
| 106 | /* Register rw_gc_r3, scope cris, type rw */ | ||
| 107 | #define reg_cris_rw_gc_r3_offset 44 | ||
| 108 | |||
| 109 | |||
| 110 | /* Constants */ | ||
| 111 | #define regk_cris_no 0x00000000 | ||
| 112 | #define regk_cris_rw_gc_cfg_default 0x00000000 | ||
| 113 | #define regk_cris_yes 0x00000001 | ||
| 114 | #endif /* __cris_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h deleted file mode 100644 index 7d3689a6f80d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | #define RW_GC_CFG 0 | ||
| 2 | #define RW_GC_CCS 1 | ||
| 3 | #define RW_GC_SRS 2 | ||
| 4 | #define RW_GC_NRP 3 | ||
| 5 | #define RW_GC_EXS 4 | ||
| 6 | #define RW_GC_EDA 5 | ||
| 7 | #define RW_GC_R0 8 | ||
| 8 | #define RW_GC_R1 9 | ||
| 9 | #define RW_GC_R2 10 | ||
| 10 | #define RW_GC_R3 11 | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h deleted file mode 100644 index 0cb71bc127ae..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h +++ /dev/null | |||
| @@ -1,368 +0,0 @@ | |||
| 1 | #ifndef __dma_defs_asm_h | ||
| 2 | #define __dma_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r | ||
| 7 | * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:51 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r | ||
| 11 | * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_data, scope dma, type rw */ | ||
| 57 | #define reg_dma_rw_data_offset 0 | ||
| 58 | |||
| 59 | /* Register rw_data_next, scope dma, type rw */ | ||
| 60 | #define reg_dma_rw_data_next_offset 4 | ||
| 61 | |||
| 62 | /* Register rw_data_buf, scope dma, type rw */ | ||
| 63 | #define reg_dma_rw_data_buf_offset 8 | ||
| 64 | |||
| 65 | /* Register rw_data_ctrl, scope dma, type rw */ | ||
| 66 | #define reg_dma_rw_data_ctrl___eol___lsb 0 | ||
| 67 | #define reg_dma_rw_data_ctrl___eol___width 1 | ||
| 68 | #define reg_dma_rw_data_ctrl___eol___bit 0 | ||
| 69 | #define reg_dma_rw_data_ctrl___out_eop___lsb 3 | ||
| 70 | #define reg_dma_rw_data_ctrl___out_eop___width 1 | ||
| 71 | #define reg_dma_rw_data_ctrl___out_eop___bit 3 | ||
| 72 | #define reg_dma_rw_data_ctrl___intr___lsb 4 | ||
| 73 | #define reg_dma_rw_data_ctrl___intr___width 1 | ||
| 74 | #define reg_dma_rw_data_ctrl___intr___bit 4 | ||
| 75 | #define reg_dma_rw_data_ctrl___wait___lsb 5 | ||
| 76 | #define reg_dma_rw_data_ctrl___wait___width 1 | ||
| 77 | #define reg_dma_rw_data_ctrl___wait___bit 5 | ||
| 78 | #define reg_dma_rw_data_ctrl_offset 12 | ||
| 79 | |||
| 80 | /* Register rw_data_stat, scope dma, type rw */ | ||
| 81 | #define reg_dma_rw_data_stat___in_eop___lsb 3 | ||
| 82 | #define reg_dma_rw_data_stat___in_eop___width 1 | ||
| 83 | #define reg_dma_rw_data_stat___in_eop___bit 3 | ||
| 84 | #define reg_dma_rw_data_stat_offset 16 | ||
| 85 | |||
| 86 | /* Register rw_data_md, scope dma, type rw */ | ||
| 87 | #define reg_dma_rw_data_md___md___lsb 0 | ||
| 88 | #define reg_dma_rw_data_md___md___width 16 | ||
| 89 | #define reg_dma_rw_data_md_offset 20 | ||
| 90 | |||
| 91 | /* Register rw_data_md_s, scope dma, type rw */ | ||
| 92 | #define reg_dma_rw_data_md_s___md_s___lsb 0 | ||
| 93 | #define reg_dma_rw_data_md_s___md_s___width 16 | ||
| 94 | #define reg_dma_rw_data_md_s_offset 24 | ||
| 95 | |||
| 96 | /* Register rw_data_after, scope dma, type rw */ | ||
| 97 | #define reg_dma_rw_data_after_offset 28 | ||
| 98 | |||
| 99 | /* Register rw_ctxt, scope dma, type rw */ | ||
| 100 | #define reg_dma_rw_ctxt_offset 32 | ||
| 101 | |||
| 102 | /* Register rw_ctxt_next, scope dma, type rw */ | ||
| 103 | #define reg_dma_rw_ctxt_next_offset 36 | ||
| 104 | |||
| 105 | /* Register rw_ctxt_ctrl, scope dma, type rw */ | ||
| 106 | #define reg_dma_rw_ctxt_ctrl___eol___lsb 0 | ||
| 107 | #define reg_dma_rw_ctxt_ctrl___eol___width 1 | ||
| 108 | #define reg_dma_rw_ctxt_ctrl___eol___bit 0 | ||
| 109 | #define reg_dma_rw_ctxt_ctrl___intr___lsb 4 | ||
| 110 | #define reg_dma_rw_ctxt_ctrl___intr___width 1 | ||
| 111 | #define reg_dma_rw_ctxt_ctrl___intr___bit 4 | ||
| 112 | #define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 | ||
| 113 | #define reg_dma_rw_ctxt_ctrl___store_mode___width 1 | ||
| 114 | #define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 | ||
| 115 | #define reg_dma_rw_ctxt_ctrl___en___lsb 7 | ||
| 116 | #define reg_dma_rw_ctxt_ctrl___en___width 1 | ||
| 117 | #define reg_dma_rw_ctxt_ctrl___en___bit 7 | ||
| 118 | #define reg_dma_rw_ctxt_ctrl_offset 40 | ||
| 119 | |||
| 120 | /* Register rw_ctxt_stat, scope dma, type rw */ | ||
| 121 | #define reg_dma_rw_ctxt_stat___dis___lsb 7 | ||
| 122 | #define reg_dma_rw_ctxt_stat___dis___width 1 | ||
| 123 | #define reg_dma_rw_ctxt_stat___dis___bit 7 | ||
| 124 | #define reg_dma_rw_ctxt_stat_offset 44 | ||
| 125 | |||
| 126 | /* Register rw_ctxt_md0, scope dma, type rw */ | ||
| 127 | #define reg_dma_rw_ctxt_md0___md0___lsb 0 | ||
| 128 | #define reg_dma_rw_ctxt_md0___md0___width 16 | ||
| 129 | #define reg_dma_rw_ctxt_md0_offset 48 | ||
| 130 | |||
| 131 | /* Register rw_ctxt_md0_s, scope dma, type rw */ | ||
| 132 | #define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 | ||
| 133 | #define reg_dma_rw_ctxt_md0_s___md0_s___width 16 | ||
| 134 | #define reg_dma_rw_ctxt_md0_s_offset 52 | ||
| 135 | |||
| 136 | /* Register rw_ctxt_md1, scope dma, type rw */ | ||
| 137 | #define reg_dma_rw_ctxt_md1_offset 56 | ||
| 138 | |||
| 139 | /* Register rw_ctxt_md1_s, scope dma, type rw */ | ||
| 140 | #define reg_dma_rw_ctxt_md1_s_offset 60 | ||
| 141 | |||
| 142 | /* Register rw_ctxt_md2, scope dma, type rw */ | ||
| 143 | #define reg_dma_rw_ctxt_md2_offset 64 | ||
| 144 | |||
| 145 | /* Register rw_ctxt_md2_s, scope dma, type rw */ | ||
| 146 | #define reg_dma_rw_ctxt_md2_s_offset 68 | ||
| 147 | |||
| 148 | /* Register rw_ctxt_md3, scope dma, type rw */ | ||
| 149 | #define reg_dma_rw_ctxt_md3_offset 72 | ||
| 150 | |||
| 151 | /* Register rw_ctxt_md3_s, scope dma, type rw */ | ||
| 152 | #define reg_dma_rw_ctxt_md3_s_offset 76 | ||
| 153 | |||
| 154 | /* Register rw_ctxt_md4, scope dma, type rw */ | ||
| 155 | #define reg_dma_rw_ctxt_md4_offset 80 | ||
| 156 | |||
| 157 | /* Register rw_ctxt_md4_s, scope dma, type rw */ | ||
| 158 | #define reg_dma_rw_ctxt_md4_s_offset 84 | ||
| 159 | |||
| 160 | /* Register rw_saved_data, scope dma, type rw */ | ||
| 161 | #define reg_dma_rw_saved_data_offset 88 | ||
| 162 | |||
| 163 | /* Register rw_saved_data_buf, scope dma, type rw */ | ||
| 164 | #define reg_dma_rw_saved_data_buf_offset 92 | ||
| 165 | |||
| 166 | /* Register rw_group, scope dma, type rw */ | ||
| 167 | #define reg_dma_rw_group_offset 96 | ||
| 168 | |||
| 169 | /* Register rw_group_next, scope dma, type rw */ | ||
| 170 | #define reg_dma_rw_group_next_offset 100 | ||
| 171 | |||
| 172 | /* Register rw_group_ctrl, scope dma, type rw */ | ||
| 173 | #define reg_dma_rw_group_ctrl___eol___lsb 0 | ||
| 174 | #define reg_dma_rw_group_ctrl___eol___width 1 | ||
| 175 | #define reg_dma_rw_group_ctrl___eol___bit 0 | ||
| 176 | #define reg_dma_rw_group_ctrl___tol___lsb 1 | ||
| 177 | #define reg_dma_rw_group_ctrl___tol___width 1 | ||
| 178 | #define reg_dma_rw_group_ctrl___tol___bit 1 | ||
| 179 | #define reg_dma_rw_group_ctrl___bol___lsb 2 | ||
| 180 | #define reg_dma_rw_group_ctrl___bol___width 1 | ||
| 181 | #define reg_dma_rw_group_ctrl___bol___bit 2 | ||
| 182 | #define reg_dma_rw_group_ctrl___intr___lsb 4 | ||
| 183 | #define reg_dma_rw_group_ctrl___intr___width 1 | ||
| 184 | #define reg_dma_rw_group_ctrl___intr___bit 4 | ||
| 185 | #define reg_dma_rw_group_ctrl___en___lsb 7 | ||
| 186 | #define reg_dma_rw_group_ctrl___en___width 1 | ||
| 187 | #define reg_dma_rw_group_ctrl___en___bit 7 | ||
| 188 | #define reg_dma_rw_group_ctrl_offset 104 | ||
| 189 | |||
| 190 | /* Register rw_group_stat, scope dma, type rw */ | ||
| 191 | #define reg_dma_rw_group_stat___dis___lsb 7 | ||
| 192 | #define reg_dma_rw_group_stat___dis___width 1 | ||
| 193 | #define reg_dma_rw_group_stat___dis___bit 7 | ||
| 194 | #define reg_dma_rw_group_stat_offset 108 | ||
| 195 | |||
| 196 | /* Register rw_group_md, scope dma, type rw */ | ||
| 197 | #define reg_dma_rw_group_md___md___lsb 0 | ||
| 198 | #define reg_dma_rw_group_md___md___width 16 | ||
| 199 | #define reg_dma_rw_group_md_offset 112 | ||
| 200 | |||
| 201 | /* Register rw_group_md_s, scope dma, type rw */ | ||
| 202 | #define reg_dma_rw_group_md_s___md_s___lsb 0 | ||
| 203 | #define reg_dma_rw_group_md_s___md_s___width 16 | ||
| 204 | #define reg_dma_rw_group_md_s_offset 116 | ||
| 205 | |||
| 206 | /* Register rw_group_up, scope dma, type rw */ | ||
| 207 | #define reg_dma_rw_group_up_offset 120 | ||
| 208 | |||
| 209 | /* Register rw_group_down, scope dma, type rw */ | ||
| 210 | #define reg_dma_rw_group_down_offset 124 | ||
| 211 | |||
| 212 | /* Register rw_cmd, scope dma, type rw */ | ||
| 213 | #define reg_dma_rw_cmd___cont_data___lsb 0 | ||
| 214 | #define reg_dma_rw_cmd___cont_data___width 1 | ||
| 215 | #define reg_dma_rw_cmd___cont_data___bit 0 | ||
| 216 | #define reg_dma_rw_cmd_offset 128 | ||
| 217 | |||
| 218 | /* Register rw_cfg, scope dma, type rw */ | ||
| 219 | #define reg_dma_rw_cfg___en___lsb 0 | ||
| 220 | #define reg_dma_rw_cfg___en___width 1 | ||
| 221 | #define reg_dma_rw_cfg___en___bit 0 | ||
| 222 | #define reg_dma_rw_cfg___stop___lsb 1 | ||
| 223 | #define reg_dma_rw_cfg___stop___width 1 | ||
| 224 | #define reg_dma_rw_cfg___stop___bit 1 | ||
| 225 | #define reg_dma_rw_cfg_offset 132 | ||
| 226 | |||
| 227 | /* Register rw_stat, scope dma, type rw */ | ||
| 228 | #define reg_dma_rw_stat___mode___lsb 0 | ||
| 229 | #define reg_dma_rw_stat___mode___width 5 | ||
| 230 | #define reg_dma_rw_stat___list_state___lsb 5 | ||
| 231 | #define reg_dma_rw_stat___list_state___width 3 | ||
| 232 | #define reg_dma_rw_stat___stream_cmd_src___lsb 8 | ||
| 233 | #define reg_dma_rw_stat___stream_cmd_src___width 8 | ||
| 234 | #define reg_dma_rw_stat___buf___lsb 24 | ||
| 235 | #define reg_dma_rw_stat___buf___width 8 | ||
| 236 | #define reg_dma_rw_stat_offset 136 | ||
| 237 | |||
| 238 | /* Register rw_intr_mask, scope dma, type rw */ | ||
| 239 | #define reg_dma_rw_intr_mask___group___lsb 0 | ||
| 240 | #define reg_dma_rw_intr_mask___group___width 1 | ||
| 241 | #define reg_dma_rw_intr_mask___group___bit 0 | ||
| 242 | #define reg_dma_rw_intr_mask___ctxt___lsb 1 | ||
| 243 | #define reg_dma_rw_intr_mask___ctxt___width 1 | ||
| 244 | #define reg_dma_rw_intr_mask___ctxt___bit 1 | ||
| 245 | #define reg_dma_rw_intr_mask___data___lsb 2 | ||
| 246 | #define reg_dma_rw_intr_mask___data___width 1 | ||
| 247 | #define reg_dma_rw_intr_mask___data___bit 2 | ||
| 248 | #define reg_dma_rw_intr_mask___in_eop___lsb 3 | ||
| 249 | #define reg_dma_rw_intr_mask___in_eop___width 1 | ||
| 250 | #define reg_dma_rw_intr_mask___in_eop___bit 3 | ||
| 251 | #define reg_dma_rw_intr_mask___stream_cmd___lsb 4 | ||
| 252 | #define reg_dma_rw_intr_mask___stream_cmd___width 1 | ||
| 253 | #define reg_dma_rw_intr_mask___stream_cmd___bit 4 | ||
| 254 | #define reg_dma_rw_intr_mask_offset 140 | ||
| 255 | |||
| 256 | /* Register rw_ack_intr, scope dma, type rw */ | ||
| 257 | #define reg_dma_rw_ack_intr___group___lsb 0 | ||
| 258 | #define reg_dma_rw_ack_intr___group___width 1 | ||
| 259 | #define reg_dma_rw_ack_intr___group___bit 0 | ||
| 260 | #define reg_dma_rw_ack_intr___ctxt___lsb 1 | ||
| 261 | #define reg_dma_rw_ack_intr___ctxt___width 1 | ||
| 262 | #define reg_dma_rw_ack_intr___ctxt___bit 1 | ||
| 263 | #define reg_dma_rw_ack_intr___data___lsb 2 | ||
| 264 | #define reg_dma_rw_ack_intr___data___width 1 | ||
| 265 | #define reg_dma_rw_ack_intr___data___bit 2 | ||
| 266 | #define reg_dma_rw_ack_intr___in_eop___lsb 3 | ||
| 267 | #define reg_dma_rw_ack_intr___in_eop___width 1 | ||
| 268 | #define reg_dma_rw_ack_intr___in_eop___bit 3 | ||
| 269 | #define reg_dma_rw_ack_intr___stream_cmd___lsb 4 | ||
| 270 | #define reg_dma_rw_ack_intr___stream_cmd___width 1 | ||
| 271 | #define reg_dma_rw_ack_intr___stream_cmd___bit 4 | ||
| 272 | #define reg_dma_rw_ack_intr_offset 144 | ||
| 273 | |||
| 274 | /* Register r_intr, scope dma, type r */ | ||
| 275 | #define reg_dma_r_intr___group___lsb 0 | ||
| 276 | #define reg_dma_r_intr___group___width 1 | ||
| 277 | #define reg_dma_r_intr___group___bit 0 | ||
| 278 | #define reg_dma_r_intr___ctxt___lsb 1 | ||
| 279 | #define reg_dma_r_intr___ctxt___width 1 | ||
| 280 | #define reg_dma_r_intr___ctxt___bit 1 | ||
| 281 | #define reg_dma_r_intr___data___lsb 2 | ||
| 282 | #define reg_dma_r_intr___data___width 1 | ||
| 283 | #define reg_dma_r_intr___data___bit 2 | ||
| 284 | #define reg_dma_r_intr___in_eop___lsb 3 | ||
| 285 | #define reg_dma_r_intr___in_eop___width 1 | ||
| 286 | #define reg_dma_r_intr___in_eop___bit 3 | ||
| 287 | #define reg_dma_r_intr___stream_cmd___lsb 4 | ||
| 288 | #define reg_dma_r_intr___stream_cmd___width 1 | ||
| 289 | #define reg_dma_r_intr___stream_cmd___bit 4 | ||
| 290 | #define reg_dma_r_intr_offset 148 | ||
| 291 | |||
| 292 | /* Register r_masked_intr, scope dma, type r */ | ||
| 293 | #define reg_dma_r_masked_intr___group___lsb 0 | ||
| 294 | #define reg_dma_r_masked_intr___group___width 1 | ||
| 295 | #define reg_dma_r_masked_intr___group___bit 0 | ||
| 296 | #define reg_dma_r_masked_intr___ctxt___lsb 1 | ||
| 297 | #define reg_dma_r_masked_intr___ctxt___width 1 | ||
| 298 | #define reg_dma_r_masked_intr___ctxt___bit 1 | ||
| 299 | #define reg_dma_r_masked_intr___data___lsb 2 | ||
| 300 | #define reg_dma_r_masked_intr___data___width 1 | ||
| 301 | #define reg_dma_r_masked_intr___data___bit 2 | ||
| 302 | #define reg_dma_r_masked_intr___in_eop___lsb 3 | ||
| 303 | #define reg_dma_r_masked_intr___in_eop___width 1 | ||
| 304 | #define reg_dma_r_masked_intr___in_eop___bit 3 | ||
| 305 | #define reg_dma_r_masked_intr___stream_cmd___lsb 4 | ||
| 306 | #define reg_dma_r_masked_intr___stream_cmd___width 1 | ||
| 307 | #define reg_dma_r_masked_intr___stream_cmd___bit 4 | ||
| 308 | #define reg_dma_r_masked_intr_offset 152 | ||
| 309 | |||
| 310 | /* Register rw_stream_cmd, scope dma, type rw */ | ||
| 311 | #define reg_dma_rw_stream_cmd___cmd___lsb 0 | ||
| 312 | #define reg_dma_rw_stream_cmd___cmd___width 10 | ||
| 313 | #define reg_dma_rw_stream_cmd___n___lsb 16 | ||
| 314 | #define reg_dma_rw_stream_cmd___n___width 8 | ||
| 315 | #define reg_dma_rw_stream_cmd___busy___lsb 31 | ||
| 316 | #define reg_dma_rw_stream_cmd___busy___width 1 | ||
| 317 | #define reg_dma_rw_stream_cmd___busy___bit 31 | ||
| 318 | #define reg_dma_rw_stream_cmd_offset 156 | ||
| 319 | |||
| 320 | |||
| 321 | /* Constants */ | ||
| 322 | #define regk_dma_ack_pkt 0x00000100 | ||
| 323 | #define regk_dma_anytime 0x00000001 | ||
| 324 | #define regk_dma_array 0x00000008 | ||
| 325 | #define regk_dma_burst 0x00000020 | ||
| 326 | #define regk_dma_client 0x00000002 | ||
| 327 | #define regk_dma_copy_next 0x00000010 | ||
| 328 | #define regk_dma_copy_up 0x00000020 | ||
| 329 | #define regk_dma_data_at_eol 0x00000001 | ||
| 330 | #define regk_dma_dis_c 0x00000010 | ||
| 331 | #define regk_dma_dis_g 0x00000020 | ||
| 332 | #define regk_dma_idle 0x00000001 | ||
| 333 | #define regk_dma_intern 0x00000004 | ||
| 334 | #define regk_dma_load_c 0x00000200 | ||
| 335 | #define regk_dma_load_c_n 0x00000280 | ||
| 336 | #define regk_dma_load_c_next 0x00000240 | ||
| 337 | #define regk_dma_load_d 0x00000140 | ||
| 338 | #define regk_dma_load_g 0x00000300 | ||
| 339 | #define regk_dma_load_g_down 0x000003c0 | ||
| 340 | #define regk_dma_load_g_next 0x00000340 | ||
| 341 | #define regk_dma_load_g_up 0x00000380 | ||
| 342 | #define regk_dma_next_en 0x00000010 | ||
| 343 | #define regk_dma_next_pkt 0x00000010 | ||
| 344 | #define regk_dma_no 0x00000000 | ||
| 345 | #define regk_dma_only_at_wait 0x00000000 | ||
| 346 | #define regk_dma_restore 0x00000020 | ||
| 347 | #define regk_dma_rst 0x00000001 | ||
| 348 | #define regk_dma_running 0x00000004 | ||
| 349 | #define regk_dma_rw_cfg_default 0x00000000 | ||
| 350 | #define regk_dma_rw_cmd_default 0x00000000 | ||
| 351 | #define regk_dma_rw_intr_mask_default 0x00000000 | ||
| 352 | #define regk_dma_rw_stat_default 0x00000101 | ||
| 353 | #define regk_dma_rw_stream_cmd_default 0x00000000 | ||
| 354 | #define regk_dma_save_down 0x00000020 | ||
| 355 | #define regk_dma_save_up 0x00000020 | ||
| 356 | #define regk_dma_set_reg 0x00000050 | ||
| 357 | #define regk_dma_set_w_size1 0x00000190 | ||
| 358 | #define regk_dma_set_w_size2 0x000001a0 | ||
| 359 | #define regk_dma_set_w_size4 0x000001c0 | ||
| 360 | #define regk_dma_stopped 0x00000002 | ||
| 361 | #define regk_dma_store_c 0x00000002 | ||
| 362 | #define regk_dma_store_descr 0x00000000 | ||
| 363 | #define regk_dma_store_g 0x00000004 | ||
| 364 | #define regk_dma_store_md 0x00000001 | ||
| 365 | #define regk_dma_sw 0x00000008 | ||
| 366 | #define regk_dma_update_down 0x00000020 | ||
| 367 | #define regk_dma_yes 0x00000001 | ||
| 368 | #endif /* __dma_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h deleted file mode 100644 index c9f49864831b..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h +++ /dev/null | |||
| @@ -1,498 +0,0 @@ | |||
| 1 | #ifndef __eth_defs_asm_h | ||
| 2 | #define __eth_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/eth/rtl/eth_regs.r | ||
| 7 | * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp | ||
| 8 | * last modfied: Mon Apr 11 16:07:03 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r | ||
| 11 | * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_ma0_lo, scope eth, type rw */ | ||
| 57 | #define reg_eth_rw_ma0_lo___addr___lsb 0 | ||
| 58 | #define reg_eth_rw_ma0_lo___addr___width 32 | ||
| 59 | #define reg_eth_rw_ma0_lo_offset 0 | ||
| 60 | |||
| 61 | /* Register rw_ma0_hi, scope eth, type rw */ | ||
| 62 | #define reg_eth_rw_ma0_hi___addr___lsb 0 | ||
| 63 | #define reg_eth_rw_ma0_hi___addr___width 16 | ||
| 64 | #define reg_eth_rw_ma0_hi_offset 4 | ||
| 65 | |||
| 66 | /* Register rw_ma1_lo, scope eth, type rw */ | ||
| 67 | #define reg_eth_rw_ma1_lo___addr___lsb 0 | ||
| 68 | #define reg_eth_rw_ma1_lo___addr___width 32 | ||
| 69 | #define reg_eth_rw_ma1_lo_offset 8 | ||
| 70 | |||
| 71 | /* Register rw_ma1_hi, scope eth, type rw */ | ||
| 72 | #define reg_eth_rw_ma1_hi___addr___lsb 0 | ||
| 73 | #define reg_eth_rw_ma1_hi___addr___width 16 | ||
| 74 | #define reg_eth_rw_ma1_hi_offset 12 | ||
| 75 | |||
| 76 | /* Register rw_ga_lo, scope eth, type rw */ | ||
| 77 | #define reg_eth_rw_ga_lo___table___lsb 0 | ||
| 78 | #define reg_eth_rw_ga_lo___table___width 32 | ||
| 79 | #define reg_eth_rw_ga_lo_offset 16 | ||
| 80 | |||
| 81 | /* Register rw_ga_hi, scope eth, type rw */ | ||
| 82 | #define reg_eth_rw_ga_hi___table___lsb 0 | ||
| 83 | #define reg_eth_rw_ga_hi___table___width 32 | ||
| 84 | #define reg_eth_rw_ga_hi_offset 20 | ||
| 85 | |||
| 86 | /* Register rw_gen_ctrl, scope eth, type rw */ | ||
| 87 | #define reg_eth_rw_gen_ctrl___en___lsb 0 | ||
| 88 | #define reg_eth_rw_gen_ctrl___en___width 1 | ||
| 89 | #define reg_eth_rw_gen_ctrl___en___bit 0 | ||
| 90 | #define reg_eth_rw_gen_ctrl___phy___lsb 1 | ||
| 91 | #define reg_eth_rw_gen_ctrl___phy___width 2 | ||
| 92 | #define reg_eth_rw_gen_ctrl___protocol___lsb 3 | ||
| 93 | #define reg_eth_rw_gen_ctrl___protocol___width 1 | ||
| 94 | #define reg_eth_rw_gen_ctrl___protocol___bit 3 | ||
| 95 | #define reg_eth_rw_gen_ctrl___loopback___lsb 4 | ||
| 96 | #define reg_eth_rw_gen_ctrl___loopback___width 1 | ||
| 97 | #define reg_eth_rw_gen_ctrl___loopback___bit 4 | ||
| 98 | #define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 | ||
| 99 | #define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 | ||
| 100 | #define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 | ||
| 101 | #define reg_eth_rw_gen_ctrl_offset 24 | ||
| 102 | |||
| 103 | /* Register rw_rec_ctrl, scope eth, type rw */ | ||
| 104 | #define reg_eth_rw_rec_ctrl___ma0___lsb 0 | ||
| 105 | #define reg_eth_rw_rec_ctrl___ma0___width 1 | ||
| 106 | #define reg_eth_rw_rec_ctrl___ma0___bit 0 | ||
| 107 | #define reg_eth_rw_rec_ctrl___ma1___lsb 1 | ||
| 108 | #define reg_eth_rw_rec_ctrl___ma1___width 1 | ||
| 109 | #define reg_eth_rw_rec_ctrl___ma1___bit 1 | ||
| 110 | #define reg_eth_rw_rec_ctrl___individual___lsb 2 | ||
| 111 | #define reg_eth_rw_rec_ctrl___individual___width 1 | ||
| 112 | #define reg_eth_rw_rec_ctrl___individual___bit 2 | ||
| 113 | #define reg_eth_rw_rec_ctrl___broadcast___lsb 3 | ||
| 114 | #define reg_eth_rw_rec_ctrl___broadcast___width 1 | ||
| 115 | #define reg_eth_rw_rec_ctrl___broadcast___bit 3 | ||
| 116 | #define reg_eth_rw_rec_ctrl___undersize___lsb 4 | ||
| 117 | #define reg_eth_rw_rec_ctrl___undersize___width 1 | ||
| 118 | #define reg_eth_rw_rec_ctrl___undersize___bit 4 | ||
| 119 | #define reg_eth_rw_rec_ctrl___oversize___lsb 5 | ||
| 120 | #define reg_eth_rw_rec_ctrl___oversize___width 1 | ||
| 121 | #define reg_eth_rw_rec_ctrl___oversize___bit 5 | ||
| 122 | #define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 | ||
| 123 | #define reg_eth_rw_rec_ctrl___bad_crc___width 1 | ||
| 124 | #define reg_eth_rw_rec_ctrl___bad_crc___bit 6 | ||
| 125 | #define reg_eth_rw_rec_ctrl___duplex___lsb 7 | ||
| 126 | #define reg_eth_rw_rec_ctrl___duplex___width 1 | ||
| 127 | #define reg_eth_rw_rec_ctrl___duplex___bit 7 | ||
| 128 | #define reg_eth_rw_rec_ctrl___max_size___lsb 8 | ||
| 129 | #define reg_eth_rw_rec_ctrl___max_size___width 1 | ||
| 130 | #define reg_eth_rw_rec_ctrl___max_size___bit 8 | ||
| 131 | #define reg_eth_rw_rec_ctrl_offset 28 | ||
| 132 | |||
| 133 | /* Register rw_tr_ctrl, scope eth, type rw */ | ||
| 134 | #define reg_eth_rw_tr_ctrl___crc___lsb 0 | ||
| 135 | #define reg_eth_rw_tr_ctrl___crc___width 1 | ||
| 136 | #define reg_eth_rw_tr_ctrl___crc___bit 0 | ||
| 137 | #define reg_eth_rw_tr_ctrl___pad___lsb 1 | ||
| 138 | #define reg_eth_rw_tr_ctrl___pad___width 1 | ||
| 139 | #define reg_eth_rw_tr_ctrl___pad___bit 1 | ||
| 140 | #define reg_eth_rw_tr_ctrl___retry___lsb 2 | ||
| 141 | #define reg_eth_rw_tr_ctrl___retry___width 1 | ||
| 142 | #define reg_eth_rw_tr_ctrl___retry___bit 2 | ||
| 143 | #define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 | ||
| 144 | #define reg_eth_rw_tr_ctrl___ignore_col___width 1 | ||
| 145 | #define reg_eth_rw_tr_ctrl___ignore_col___bit 3 | ||
| 146 | #define reg_eth_rw_tr_ctrl___cancel___lsb 4 | ||
| 147 | #define reg_eth_rw_tr_ctrl___cancel___width 1 | ||
| 148 | #define reg_eth_rw_tr_ctrl___cancel___bit 4 | ||
| 149 | #define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 | ||
| 150 | #define reg_eth_rw_tr_ctrl___hsh_delay___width 1 | ||
| 151 | #define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 | ||
| 152 | #define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 | ||
| 153 | #define reg_eth_rw_tr_ctrl___ignore_crs___width 1 | ||
| 154 | #define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 | ||
| 155 | #define reg_eth_rw_tr_ctrl_offset 32 | ||
| 156 | |||
| 157 | /* Register rw_clr_err, scope eth, type rw */ | ||
| 158 | #define reg_eth_rw_clr_err___clr___lsb 0 | ||
| 159 | #define reg_eth_rw_clr_err___clr___width 1 | ||
| 160 | #define reg_eth_rw_clr_err___clr___bit 0 | ||
| 161 | #define reg_eth_rw_clr_err_offset 36 | ||
| 162 | |||
| 163 | /* Register rw_mgm_ctrl, scope eth, type rw */ | ||
| 164 | #define reg_eth_rw_mgm_ctrl___mdio___lsb 0 | ||
| 165 | #define reg_eth_rw_mgm_ctrl___mdio___width 1 | ||
| 166 | #define reg_eth_rw_mgm_ctrl___mdio___bit 0 | ||
| 167 | #define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 | ||
| 168 | #define reg_eth_rw_mgm_ctrl___mdoe___width 1 | ||
| 169 | #define reg_eth_rw_mgm_ctrl___mdoe___bit 1 | ||
| 170 | #define reg_eth_rw_mgm_ctrl___mdc___lsb 2 | ||
| 171 | #define reg_eth_rw_mgm_ctrl___mdc___width 1 | ||
| 172 | #define reg_eth_rw_mgm_ctrl___mdc___bit 2 | ||
| 173 | #define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 | ||
| 174 | #define reg_eth_rw_mgm_ctrl___phyclk___width 1 | ||
| 175 | #define reg_eth_rw_mgm_ctrl___phyclk___bit 3 | ||
| 176 | #define reg_eth_rw_mgm_ctrl___txdata___lsb 4 | ||
| 177 | #define reg_eth_rw_mgm_ctrl___txdata___width 4 | ||
| 178 | #define reg_eth_rw_mgm_ctrl___txen___lsb 8 | ||
| 179 | #define reg_eth_rw_mgm_ctrl___txen___width 1 | ||
| 180 | #define reg_eth_rw_mgm_ctrl___txen___bit 8 | ||
| 181 | #define reg_eth_rw_mgm_ctrl_offset 40 | ||
| 182 | |||
| 183 | /* Register r_stat, scope eth, type r */ | ||
| 184 | #define reg_eth_r_stat___mdio___lsb 0 | ||
| 185 | #define reg_eth_r_stat___mdio___width 1 | ||
| 186 | #define reg_eth_r_stat___mdio___bit 0 | ||
| 187 | #define reg_eth_r_stat___exc_col___lsb 1 | ||
| 188 | #define reg_eth_r_stat___exc_col___width 1 | ||
| 189 | #define reg_eth_r_stat___exc_col___bit 1 | ||
| 190 | #define reg_eth_r_stat___urun___lsb 2 | ||
| 191 | #define reg_eth_r_stat___urun___width 1 | ||
| 192 | #define reg_eth_r_stat___urun___bit 2 | ||
| 193 | #define reg_eth_r_stat___phyclk___lsb 3 | ||
| 194 | #define reg_eth_r_stat___phyclk___width 1 | ||
| 195 | #define reg_eth_r_stat___phyclk___bit 3 | ||
| 196 | #define reg_eth_r_stat___txdata___lsb 4 | ||
| 197 | #define reg_eth_r_stat___txdata___width 4 | ||
| 198 | #define reg_eth_r_stat___txen___lsb 8 | ||
| 199 | #define reg_eth_r_stat___txen___width 1 | ||
| 200 | #define reg_eth_r_stat___txen___bit 8 | ||
| 201 | #define reg_eth_r_stat___col___lsb 9 | ||
| 202 | #define reg_eth_r_stat___col___width 1 | ||
| 203 | #define reg_eth_r_stat___col___bit 9 | ||
| 204 | #define reg_eth_r_stat___crs___lsb 10 | ||
| 205 | #define reg_eth_r_stat___crs___width 1 | ||
| 206 | #define reg_eth_r_stat___crs___bit 10 | ||
| 207 | #define reg_eth_r_stat___txclk___lsb 11 | ||
| 208 | #define reg_eth_r_stat___txclk___width 1 | ||
| 209 | #define reg_eth_r_stat___txclk___bit 11 | ||
| 210 | #define reg_eth_r_stat___rxdata___lsb 12 | ||
| 211 | #define reg_eth_r_stat___rxdata___width 4 | ||
| 212 | #define reg_eth_r_stat___rxer___lsb 16 | ||
| 213 | #define reg_eth_r_stat___rxer___width 1 | ||
| 214 | #define reg_eth_r_stat___rxer___bit 16 | ||
| 215 | #define reg_eth_r_stat___rxdv___lsb 17 | ||
| 216 | #define reg_eth_r_stat___rxdv___width 1 | ||
| 217 | #define reg_eth_r_stat___rxdv___bit 17 | ||
| 218 | #define reg_eth_r_stat___rxclk___lsb 18 | ||
| 219 | #define reg_eth_r_stat___rxclk___width 1 | ||
| 220 | #define reg_eth_r_stat___rxclk___bit 18 | ||
| 221 | #define reg_eth_r_stat_offset 44 | ||
| 222 | |||
| 223 | /* Register rs_rec_cnt, scope eth, type rs */ | ||
| 224 | #define reg_eth_rs_rec_cnt___crc_err___lsb 0 | ||
| 225 | #define reg_eth_rs_rec_cnt___crc_err___width 8 | ||
| 226 | #define reg_eth_rs_rec_cnt___align_err___lsb 8 | ||
| 227 | #define reg_eth_rs_rec_cnt___align_err___width 8 | ||
| 228 | #define reg_eth_rs_rec_cnt___oversize___lsb 16 | ||
| 229 | #define reg_eth_rs_rec_cnt___oversize___width 8 | ||
| 230 | #define reg_eth_rs_rec_cnt___congestion___lsb 24 | ||
| 231 | #define reg_eth_rs_rec_cnt___congestion___width 8 | ||
| 232 | #define reg_eth_rs_rec_cnt_offset 48 | ||
| 233 | |||
| 234 | /* Register r_rec_cnt, scope eth, type r */ | ||
| 235 | #define reg_eth_r_rec_cnt___crc_err___lsb 0 | ||
| 236 | #define reg_eth_r_rec_cnt___crc_err___width 8 | ||
| 237 | #define reg_eth_r_rec_cnt___align_err___lsb 8 | ||
| 238 | #define reg_eth_r_rec_cnt___align_err___width 8 | ||
| 239 | #define reg_eth_r_rec_cnt___oversize___lsb 16 | ||
| 240 | #define reg_eth_r_rec_cnt___oversize___width 8 | ||
| 241 | #define reg_eth_r_rec_cnt___congestion___lsb 24 | ||
| 242 | #define reg_eth_r_rec_cnt___congestion___width 8 | ||
| 243 | #define reg_eth_r_rec_cnt_offset 52 | ||
| 244 | |||
| 245 | /* Register rs_tr_cnt, scope eth, type rs */ | ||
| 246 | #define reg_eth_rs_tr_cnt___single_col___lsb 0 | ||
| 247 | #define reg_eth_rs_tr_cnt___single_col___width 8 | ||
| 248 | #define reg_eth_rs_tr_cnt___mult_col___lsb 8 | ||
| 249 | #define reg_eth_rs_tr_cnt___mult_col___width 8 | ||
| 250 | #define reg_eth_rs_tr_cnt___late_col___lsb 16 | ||
| 251 | #define reg_eth_rs_tr_cnt___late_col___width 8 | ||
| 252 | #define reg_eth_rs_tr_cnt___deferred___lsb 24 | ||
| 253 | #define reg_eth_rs_tr_cnt___deferred___width 8 | ||
| 254 | #define reg_eth_rs_tr_cnt_offset 56 | ||
| 255 | |||
| 256 | /* Register r_tr_cnt, scope eth, type r */ | ||
| 257 | #define reg_eth_r_tr_cnt___single_col___lsb 0 | ||
| 258 | #define reg_eth_r_tr_cnt___single_col___width 8 | ||
| 259 | #define reg_eth_r_tr_cnt___mult_col___lsb 8 | ||
| 260 | #define reg_eth_r_tr_cnt___mult_col___width 8 | ||
| 261 | #define reg_eth_r_tr_cnt___late_col___lsb 16 | ||
| 262 | #define reg_eth_r_tr_cnt___late_col___width 8 | ||
| 263 | #define reg_eth_r_tr_cnt___deferred___lsb 24 | ||
| 264 | #define reg_eth_r_tr_cnt___deferred___width 8 | ||
| 265 | #define reg_eth_r_tr_cnt_offset 60 | ||
| 266 | |||
| 267 | /* Register rs_phy_cnt, scope eth, type rs */ | ||
| 268 | #define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 | ||
| 269 | #define reg_eth_rs_phy_cnt___carrier_loss___width 8 | ||
| 270 | #define reg_eth_rs_phy_cnt___sqe_err___lsb 8 | ||
| 271 | #define reg_eth_rs_phy_cnt___sqe_err___width 8 | ||
| 272 | #define reg_eth_rs_phy_cnt_offset 64 | ||
| 273 | |||
| 274 | /* Register r_phy_cnt, scope eth, type r */ | ||
| 275 | #define reg_eth_r_phy_cnt___carrier_loss___lsb 0 | ||
| 276 | #define reg_eth_r_phy_cnt___carrier_loss___width 8 | ||
| 277 | #define reg_eth_r_phy_cnt___sqe_err___lsb 8 | ||
| 278 | #define reg_eth_r_phy_cnt___sqe_err___width 8 | ||
| 279 | #define reg_eth_r_phy_cnt_offset 68 | ||
| 280 | |||
| 281 | /* Register rw_test_ctrl, scope eth, type rw */ | ||
| 282 | #define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 | ||
| 283 | #define reg_eth_rw_test_ctrl___snmp_inc___width 1 | ||
| 284 | #define reg_eth_rw_test_ctrl___snmp_inc___bit 0 | ||
| 285 | #define reg_eth_rw_test_ctrl___snmp___lsb 1 | ||
| 286 | #define reg_eth_rw_test_ctrl___snmp___width 1 | ||
| 287 | #define reg_eth_rw_test_ctrl___snmp___bit 1 | ||
| 288 | #define reg_eth_rw_test_ctrl___backoff___lsb 2 | ||
| 289 | #define reg_eth_rw_test_ctrl___backoff___width 1 | ||
| 290 | #define reg_eth_rw_test_ctrl___backoff___bit 2 | ||
| 291 | #define reg_eth_rw_test_ctrl_offset 72 | ||
| 292 | |||
| 293 | /* Register rw_intr_mask, scope eth, type rw */ | ||
| 294 | #define reg_eth_rw_intr_mask___crc___lsb 0 | ||
| 295 | #define reg_eth_rw_intr_mask___crc___width 1 | ||
| 296 | #define reg_eth_rw_intr_mask___crc___bit 0 | ||
| 297 | #define reg_eth_rw_intr_mask___align___lsb 1 | ||
| 298 | #define reg_eth_rw_intr_mask___align___width 1 | ||
| 299 | #define reg_eth_rw_intr_mask___align___bit 1 | ||
| 300 | #define reg_eth_rw_intr_mask___oversize___lsb 2 | ||
| 301 | #define reg_eth_rw_intr_mask___oversize___width 1 | ||
| 302 | #define reg_eth_rw_intr_mask___oversize___bit 2 | ||
| 303 | #define reg_eth_rw_intr_mask___congestion___lsb 3 | ||
| 304 | #define reg_eth_rw_intr_mask___congestion___width 1 | ||
| 305 | #define reg_eth_rw_intr_mask___congestion___bit 3 | ||
| 306 | #define reg_eth_rw_intr_mask___single_col___lsb 4 | ||
| 307 | #define reg_eth_rw_intr_mask___single_col___width 1 | ||
| 308 | #define reg_eth_rw_intr_mask___single_col___bit 4 | ||
| 309 | #define reg_eth_rw_intr_mask___mult_col___lsb 5 | ||
| 310 | #define reg_eth_rw_intr_mask___mult_col___width 1 | ||
| 311 | #define reg_eth_rw_intr_mask___mult_col___bit 5 | ||
| 312 | #define reg_eth_rw_intr_mask___late_col___lsb 6 | ||
| 313 | #define reg_eth_rw_intr_mask___late_col___width 1 | ||
| 314 | #define reg_eth_rw_intr_mask___late_col___bit 6 | ||
| 315 | #define reg_eth_rw_intr_mask___deferred___lsb 7 | ||
| 316 | #define reg_eth_rw_intr_mask___deferred___width 1 | ||
| 317 | #define reg_eth_rw_intr_mask___deferred___bit 7 | ||
| 318 | #define reg_eth_rw_intr_mask___carrier_loss___lsb 8 | ||
| 319 | #define reg_eth_rw_intr_mask___carrier_loss___width 1 | ||
| 320 | #define reg_eth_rw_intr_mask___carrier_loss___bit 8 | ||
| 321 | #define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 | ||
| 322 | #define reg_eth_rw_intr_mask___sqe_test_err___width 1 | ||
| 323 | #define reg_eth_rw_intr_mask___sqe_test_err___bit 9 | ||
| 324 | #define reg_eth_rw_intr_mask___orun___lsb 10 | ||
| 325 | #define reg_eth_rw_intr_mask___orun___width 1 | ||
| 326 | #define reg_eth_rw_intr_mask___orun___bit 10 | ||
| 327 | #define reg_eth_rw_intr_mask___urun___lsb 11 | ||
| 328 | #define reg_eth_rw_intr_mask___urun___width 1 | ||
| 329 | #define reg_eth_rw_intr_mask___urun___bit 11 | ||
| 330 | #define reg_eth_rw_intr_mask___excessive_col___lsb 12 | ||
| 331 | #define reg_eth_rw_intr_mask___excessive_col___width 1 | ||
| 332 | #define reg_eth_rw_intr_mask___excessive_col___bit 12 | ||
| 333 | #define reg_eth_rw_intr_mask___mdio___lsb 13 | ||
| 334 | #define reg_eth_rw_intr_mask___mdio___width 1 | ||
| 335 | #define reg_eth_rw_intr_mask___mdio___bit 13 | ||
| 336 | #define reg_eth_rw_intr_mask_offset 76 | ||
| 337 | |||
| 338 | /* Register rw_ack_intr, scope eth, type rw */ | ||
| 339 | #define reg_eth_rw_ack_intr___crc___lsb 0 | ||
| 340 | #define reg_eth_rw_ack_intr___crc___width 1 | ||
| 341 | #define reg_eth_rw_ack_intr___crc___bit 0 | ||
| 342 | #define reg_eth_rw_ack_intr___align___lsb 1 | ||
| 343 | #define reg_eth_rw_ack_intr___align___width 1 | ||
| 344 | #define reg_eth_rw_ack_intr___align___bit 1 | ||
| 345 | #define reg_eth_rw_ack_intr___oversize___lsb 2 | ||
| 346 | #define reg_eth_rw_ack_intr___oversize___width 1 | ||
| 347 | #define reg_eth_rw_ack_intr___oversize___bit 2 | ||
| 348 | #define reg_eth_rw_ack_intr___congestion___lsb 3 | ||
| 349 | #define reg_eth_rw_ack_intr___congestion___width 1 | ||
| 350 | #define reg_eth_rw_ack_intr___congestion___bit 3 | ||
| 351 | #define reg_eth_rw_ack_intr___single_col___lsb 4 | ||
| 352 | #define reg_eth_rw_ack_intr___single_col___width 1 | ||
| 353 | #define reg_eth_rw_ack_intr___single_col___bit 4 | ||
| 354 | #define reg_eth_rw_ack_intr___mult_col___lsb 5 | ||
| 355 | #define reg_eth_rw_ack_intr___mult_col___width 1 | ||
| 356 | #define reg_eth_rw_ack_intr___mult_col___bit 5 | ||
| 357 | #define reg_eth_rw_ack_intr___late_col___lsb 6 | ||
| 358 | #define reg_eth_rw_ack_intr___late_col___width 1 | ||
| 359 | #define reg_eth_rw_ack_intr___late_col___bit 6 | ||
| 360 | #define reg_eth_rw_ack_intr___deferred___lsb 7 | ||
| 361 | #define reg_eth_rw_ack_intr___deferred___width 1 | ||
| 362 | #define reg_eth_rw_ack_intr___deferred___bit 7 | ||
| 363 | #define reg_eth_rw_ack_intr___carrier_loss___lsb 8 | ||
| 364 | #define reg_eth_rw_ack_intr___carrier_loss___width 1 | ||
| 365 | #define reg_eth_rw_ack_intr___carrier_loss___bit 8 | ||
| 366 | #define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 | ||
| 367 | #define reg_eth_rw_ack_intr___sqe_test_err___width 1 | ||
| 368 | #define reg_eth_rw_ack_intr___sqe_test_err___bit 9 | ||
| 369 | #define reg_eth_rw_ack_intr___orun___lsb 10 | ||
| 370 | #define reg_eth_rw_ack_intr___orun___width 1 | ||
| 371 | #define reg_eth_rw_ack_intr___orun___bit 10 | ||
| 372 | #define reg_eth_rw_ack_intr___urun___lsb 11 | ||
| 373 | #define reg_eth_rw_ack_intr___urun___width 1 | ||
| 374 | #define reg_eth_rw_ack_intr___urun___bit 11 | ||
| 375 | #define reg_eth_rw_ack_intr___excessive_col___lsb 12 | ||
| 376 | #define reg_eth_rw_ack_intr___excessive_col___width 1 | ||
| 377 | #define reg_eth_rw_ack_intr___excessive_col___bit 12 | ||
| 378 | #define reg_eth_rw_ack_intr___mdio___lsb 13 | ||
| 379 | #define reg_eth_rw_ack_intr___mdio___width 1 | ||
| 380 | #define reg_eth_rw_ack_intr___mdio___bit 13 | ||
| 381 | #define reg_eth_rw_ack_intr_offset 80 | ||
| 382 | |||
| 383 | /* Register r_intr, scope eth, type r */ | ||
| 384 | #define reg_eth_r_intr___crc___lsb 0 | ||
| 385 | #define reg_eth_r_intr___crc___width 1 | ||
| 386 | #define reg_eth_r_intr___crc___bit 0 | ||
| 387 | #define reg_eth_r_intr___align___lsb 1 | ||
| 388 | #define reg_eth_r_intr___align___width 1 | ||
| 389 | #define reg_eth_r_intr___align___bit 1 | ||
| 390 | #define reg_eth_r_intr___oversize___lsb 2 | ||
| 391 | #define reg_eth_r_intr___oversize___width 1 | ||
| 392 | #define reg_eth_r_intr___oversize___bit 2 | ||
| 393 | #define reg_eth_r_intr___congestion___lsb 3 | ||
| 394 | #define reg_eth_r_intr___congestion___width 1 | ||
| 395 | #define reg_eth_r_intr___congestion___bit 3 | ||
| 396 | #define reg_eth_r_intr___single_col___lsb 4 | ||
| 397 | #define reg_eth_r_intr___single_col___width 1 | ||
| 398 | #define reg_eth_r_intr___single_col___bit 4 | ||
| 399 | #define reg_eth_r_intr___mult_col___lsb 5 | ||
| 400 | #define reg_eth_r_intr___mult_col___width 1 | ||
| 401 | #define reg_eth_r_intr___mult_col___bit 5 | ||
| 402 | #define reg_eth_r_intr___late_col___lsb 6 | ||
| 403 | #define reg_eth_r_intr___late_col___width 1 | ||
| 404 | #define reg_eth_r_intr___late_col___bit 6 | ||
| 405 | #define reg_eth_r_intr___deferred___lsb 7 | ||
| 406 | #define reg_eth_r_intr___deferred___width 1 | ||
| 407 | #define reg_eth_r_intr___deferred___bit 7 | ||
| 408 | #define reg_eth_r_intr___carrier_loss___lsb 8 | ||
| 409 | #define reg_eth_r_intr___carrier_loss___width 1 | ||
| 410 | #define reg_eth_r_intr___carrier_loss___bit 8 | ||
| 411 | #define reg_eth_r_intr___sqe_test_err___lsb 9 | ||
| 412 | #define reg_eth_r_intr___sqe_test_err___width 1 | ||
| 413 | #define reg_eth_r_intr___sqe_test_err___bit 9 | ||
| 414 | #define reg_eth_r_intr___orun___lsb 10 | ||
| 415 | #define reg_eth_r_intr___orun___width 1 | ||
| 416 | #define reg_eth_r_intr___orun___bit 10 | ||
| 417 | #define reg_eth_r_intr___urun___lsb 11 | ||
| 418 | #define reg_eth_r_intr___urun___width 1 | ||
| 419 | #define reg_eth_r_intr___urun___bit 11 | ||
| 420 | #define reg_eth_r_intr___excessive_col___lsb 12 | ||
| 421 | #define reg_eth_r_intr___excessive_col___width 1 | ||
| 422 | #define reg_eth_r_intr___excessive_col___bit 12 | ||
| 423 | #define reg_eth_r_intr___mdio___lsb 13 | ||
| 424 | #define reg_eth_r_intr___mdio___width 1 | ||
| 425 | #define reg_eth_r_intr___mdio___bit 13 | ||
| 426 | #define reg_eth_r_intr_offset 84 | ||
| 427 | |||
| 428 | /* Register r_masked_intr, scope eth, type r */ | ||
| 429 | #define reg_eth_r_masked_intr___crc___lsb 0 | ||
| 430 | #define reg_eth_r_masked_intr___crc___width 1 | ||
| 431 | #define reg_eth_r_masked_intr___crc___bit 0 | ||
| 432 | #define reg_eth_r_masked_intr___align___lsb 1 | ||
| 433 | #define reg_eth_r_masked_intr___align___width 1 | ||
| 434 | #define reg_eth_r_masked_intr___align___bit 1 | ||
| 435 | #define reg_eth_r_masked_intr___oversize___lsb 2 | ||
| 436 | #define reg_eth_r_masked_intr___oversize___width 1 | ||
| 437 | #define reg_eth_r_masked_intr___oversize___bit 2 | ||
| 438 | #define reg_eth_r_masked_intr___congestion___lsb 3 | ||
| 439 | #define reg_eth_r_masked_intr___congestion___width 1 | ||
| 440 | #define reg_eth_r_masked_intr___congestion___bit 3 | ||
| 441 | #define reg_eth_r_masked_intr___single_col___lsb 4 | ||
| 442 | #define reg_eth_r_masked_intr___single_col___width 1 | ||
| 443 | #define reg_eth_r_masked_intr___single_col___bit 4 | ||
| 444 | #define reg_eth_r_masked_intr___mult_col___lsb 5 | ||
| 445 | #define reg_eth_r_masked_intr___mult_col___width 1 | ||
| 446 | #define reg_eth_r_masked_intr___mult_col___bit 5 | ||
| 447 | #define reg_eth_r_masked_intr___late_col___lsb 6 | ||
| 448 | #define reg_eth_r_masked_intr___late_col___width 1 | ||
| 449 | #define reg_eth_r_masked_intr___late_col___bit 6 | ||
| 450 | #define reg_eth_r_masked_intr___deferred___lsb 7 | ||
| 451 | #define reg_eth_r_masked_intr___deferred___width 1 | ||
| 452 | #define reg_eth_r_masked_intr___deferred___bit 7 | ||
| 453 | #define reg_eth_r_masked_intr___carrier_loss___lsb 8 | ||
| 454 | #define reg_eth_r_masked_intr___carrier_loss___width 1 | ||
| 455 | #define reg_eth_r_masked_intr___carrier_loss___bit 8 | ||
| 456 | #define reg_eth_r_masked_intr___sqe_test_err___lsb 9 | ||
| 457 | #define reg_eth_r_masked_intr___sqe_test_err___width 1 | ||
| 458 | #define reg_eth_r_masked_intr___sqe_test_err___bit 9 | ||
| 459 | #define reg_eth_r_masked_intr___orun___lsb 10 | ||
| 460 | #define reg_eth_r_masked_intr___orun___width 1 | ||
| 461 | #define reg_eth_r_masked_intr___orun___bit 10 | ||
| 462 | #define reg_eth_r_masked_intr___urun___lsb 11 | ||
| 463 | #define reg_eth_r_masked_intr___urun___width 1 | ||
| 464 | #define reg_eth_r_masked_intr___urun___bit 11 | ||
| 465 | #define reg_eth_r_masked_intr___excessive_col___lsb 12 | ||
| 466 | #define reg_eth_r_masked_intr___excessive_col___width 1 | ||
| 467 | #define reg_eth_r_masked_intr___excessive_col___bit 12 | ||
| 468 | #define reg_eth_r_masked_intr___mdio___lsb 13 | ||
| 469 | #define reg_eth_r_masked_intr___mdio___width 1 | ||
| 470 | #define reg_eth_r_masked_intr___mdio___bit 13 | ||
| 471 | #define reg_eth_r_masked_intr_offset 88 | ||
| 472 | |||
| 473 | |||
| 474 | /* Constants */ | ||
| 475 | #define regk_eth_discard 0x00000000 | ||
| 476 | #define regk_eth_ether 0x00000000 | ||
| 477 | #define regk_eth_full 0x00000001 | ||
| 478 | #define regk_eth_half 0x00000000 | ||
| 479 | #define regk_eth_hsh 0x00000001 | ||
| 480 | #define regk_eth_mii 0x00000001 | ||
| 481 | #define regk_eth_mii_clk 0x00000000 | ||
| 482 | #define regk_eth_mii_rec 0x00000002 | ||
| 483 | #define regk_eth_no 0x00000000 | ||
| 484 | #define regk_eth_rec 0x00000001 | ||
| 485 | #define regk_eth_rw_ga_hi_default 0x00000000 | ||
| 486 | #define regk_eth_rw_ga_lo_default 0x00000000 | ||
| 487 | #define regk_eth_rw_gen_ctrl_default 0x00000000 | ||
| 488 | #define regk_eth_rw_intr_mask_default 0x00000000 | ||
| 489 | #define regk_eth_rw_ma0_hi_default 0x00000000 | ||
| 490 | #define regk_eth_rw_ma0_lo_default 0x00000000 | ||
| 491 | #define regk_eth_rw_ma1_hi_default 0x00000000 | ||
| 492 | #define regk_eth_rw_ma1_lo_default 0x00000000 | ||
| 493 | #define regk_eth_rw_mgm_ctrl_default 0x00000000 | ||
| 494 | #define regk_eth_rw_test_ctrl_default 0x00000000 | ||
| 495 | #define regk_eth_size1518 0x00000000 | ||
| 496 | #define regk_eth_size1522 0x00000001 | ||
| 497 | #define regk_eth_yes 0x00000001 | ||
| 498 | #endif /* __eth_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index 35356bc08629..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h +++ /dev/null | |||
| @@ -1,276 +0,0 @@ | |||
| 1 | #ifndef __gio_defs_asm_h | ||
| 2 | #define __gio_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/gio/rtl/gio_regs.r | ||
| 7 | * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:07:47 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r | ||
| 11 | * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 57 | #define reg_gio_rw_pa_dout___data___lsb 0 | ||
| 58 | #define reg_gio_rw_pa_dout___data___width 8 | ||
| 59 | #define reg_gio_rw_pa_dout_offset 0 | ||
| 60 | |||
| 61 | /* Register r_pa_din, scope gio, type r */ | ||
| 62 | #define reg_gio_r_pa_din___data___lsb 0 | ||
| 63 | #define reg_gio_r_pa_din___data___width 8 | ||
| 64 | #define reg_gio_r_pa_din_offset 4 | ||
| 65 | |||
| 66 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 67 | #define reg_gio_rw_pa_oe___oe___lsb 0 | ||
| 68 | #define reg_gio_rw_pa_oe___oe___width 8 | ||
| 69 | #define reg_gio_rw_pa_oe_offset 8 | ||
| 70 | |||
| 71 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 72 | #define reg_gio_rw_intr_cfg___pa0___lsb 0 | ||
| 73 | #define reg_gio_rw_intr_cfg___pa0___width 3 | ||
| 74 | #define reg_gio_rw_intr_cfg___pa1___lsb 3 | ||
| 75 | #define reg_gio_rw_intr_cfg___pa1___width 3 | ||
| 76 | #define reg_gio_rw_intr_cfg___pa2___lsb 6 | ||
| 77 | #define reg_gio_rw_intr_cfg___pa2___width 3 | ||
| 78 | #define reg_gio_rw_intr_cfg___pa3___lsb 9 | ||
| 79 | #define reg_gio_rw_intr_cfg___pa3___width 3 | ||
| 80 | #define reg_gio_rw_intr_cfg___pa4___lsb 12 | ||
| 81 | #define reg_gio_rw_intr_cfg___pa4___width 3 | ||
| 82 | #define reg_gio_rw_intr_cfg___pa5___lsb 15 | ||
| 83 | #define reg_gio_rw_intr_cfg___pa5___width 3 | ||
| 84 | #define reg_gio_rw_intr_cfg___pa6___lsb 18 | ||
| 85 | #define reg_gio_rw_intr_cfg___pa6___width 3 | ||
| 86 | #define reg_gio_rw_intr_cfg___pa7___lsb 21 | ||
| 87 | #define reg_gio_rw_intr_cfg___pa7___width 3 | ||
| 88 | #define reg_gio_rw_intr_cfg_offset 12 | ||
| 89 | |||
| 90 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 91 | #define reg_gio_rw_intr_mask___pa0___lsb 0 | ||
| 92 | #define reg_gio_rw_intr_mask___pa0___width 1 | ||
| 93 | #define reg_gio_rw_intr_mask___pa0___bit 0 | ||
| 94 | #define reg_gio_rw_intr_mask___pa1___lsb 1 | ||
| 95 | #define reg_gio_rw_intr_mask___pa1___width 1 | ||
| 96 | #define reg_gio_rw_intr_mask___pa1___bit 1 | ||
| 97 | #define reg_gio_rw_intr_mask___pa2___lsb 2 | ||
| 98 | #define reg_gio_rw_intr_mask___pa2___width 1 | ||
| 99 | #define reg_gio_rw_intr_mask___pa2___bit 2 | ||
| 100 | #define reg_gio_rw_intr_mask___pa3___lsb 3 | ||
| 101 | #define reg_gio_rw_intr_mask___pa3___width 1 | ||
| 102 | #define reg_gio_rw_intr_mask___pa3___bit 3 | ||
| 103 | #define reg_gio_rw_intr_mask___pa4___lsb 4 | ||
| 104 | #define reg_gio_rw_intr_mask___pa4___width 1 | ||
| 105 | #define reg_gio_rw_intr_mask___pa4___bit 4 | ||
| 106 | #define reg_gio_rw_intr_mask___pa5___lsb 5 | ||
| 107 | #define reg_gio_rw_intr_mask___pa5___width 1 | ||
| 108 | #define reg_gio_rw_intr_mask___pa5___bit 5 | ||
| 109 | #define reg_gio_rw_intr_mask___pa6___lsb 6 | ||
| 110 | #define reg_gio_rw_intr_mask___pa6___width 1 | ||
| 111 | #define reg_gio_rw_intr_mask___pa6___bit 6 | ||
| 112 | #define reg_gio_rw_intr_mask___pa7___lsb 7 | ||
| 113 | #define reg_gio_rw_intr_mask___pa7___width 1 | ||
| 114 | #define reg_gio_rw_intr_mask___pa7___bit 7 | ||
| 115 | #define reg_gio_rw_intr_mask_offset 16 | ||
| 116 | |||
| 117 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 118 | #define reg_gio_rw_ack_intr___pa0___lsb 0 | ||
| 119 | #define reg_gio_rw_ack_intr___pa0___width 1 | ||
| 120 | #define reg_gio_rw_ack_intr___pa0___bit 0 | ||
| 121 | #define reg_gio_rw_ack_intr___pa1___lsb 1 | ||
| 122 | #define reg_gio_rw_ack_intr___pa1___width 1 | ||
| 123 | #define reg_gio_rw_ack_intr___pa1___bit 1 | ||
| 124 | #define reg_gio_rw_ack_intr___pa2___lsb 2 | ||
| 125 | #define reg_gio_rw_ack_intr___pa2___width 1 | ||
| 126 | #define reg_gio_rw_ack_intr___pa2___bit 2 | ||
| 127 | #define reg_gio_rw_ack_intr___pa3___lsb 3 | ||
| 128 | #define reg_gio_rw_ack_intr___pa3___width 1 | ||
| 129 | #define reg_gio_rw_ack_intr___pa3___bit 3 | ||
| 130 | #define reg_gio_rw_ack_intr___pa4___lsb 4 | ||
| 131 | #define reg_gio_rw_ack_intr___pa4___width 1 | ||
| 132 | #define reg_gio_rw_ack_intr___pa4___bit 4 | ||
| 133 | #define reg_gio_rw_ack_intr___pa5___lsb 5 | ||
| 134 | #define reg_gio_rw_ack_intr___pa5___width 1 | ||
| 135 | #define reg_gio_rw_ack_intr___pa5___bit 5 | ||
| 136 | #define reg_gio_rw_ack_intr___pa6___lsb 6 | ||
| 137 | #define reg_gio_rw_ack_intr___pa6___width 1 | ||
| 138 | #define reg_gio_rw_ack_intr___pa6___bit 6 | ||
| 139 | #define reg_gio_rw_ack_intr___pa7___lsb 7 | ||
| 140 | #define reg_gio_rw_ack_intr___pa7___width 1 | ||
| 141 | #define reg_gio_rw_ack_intr___pa7___bit 7 | ||
| 142 | #define reg_gio_rw_ack_intr_offset 20 | ||
| 143 | |||
| 144 | /* Register r_intr, scope gio, type r */ | ||
| 145 | #define reg_gio_r_intr___pa0___lsb 0 | ||
| 146 | #define reg_gio_r_intr___pa0___width 1 | ||
| 147 | #define reg_gio_r_intr___pa0___bit 0 | ||
| 148 | #define reg_gio_r_intr___pa1___lsb 1 | ||
| 149 | #define reg_gio_r_intr___pa1___width 1 | ||
| 150 | #define reg_gio_r_intr___pa1___bit 1 | ||
| 151 | #define reg_gio_r_intr___pa2___lsb 2 | ||
| 152 | #define reg_gio_r_intr___pa2___width 1 | ||
| 153 | #define reg_gio_r_intr___pa2___bit 2 | ||
| 154 | #define reg_gio_r_intr___pa3___lsb 3 | ||
| 155 | #define reg_gio_r_intr___pa3___width 1 | ||
| 156 | #define reg_gio_r_intr___pa3___bit 3 | ||
| 157 | #define reg_gio_r_intr___pa4___lsb 4 | ||
| 158 | #define reg_gio_r_intr___pa4___width 1 | ||
| 159 | #define reg_gio_r_intr___pa4___bit 4 | ||
| 160 | #define reg_gio_r_intr___pa5___lsb 5 | ||
| 161 | #define reg_gio_r_intr___pa5___width 1 | ||
| 162 | #define reg_gio_r_intr___pa5___bit 5 | ||
| 163 | #define reg_gio_r_intr___pa6___lsb 6 | ||
| 164 | #define reg_gio_r_intr___pa6___width 1 | ||
| 165 | #define reg_gio_r_intr___pa6___bit 6 | ||
| 166 | #define reg_gio_r_intr___pa7___lsb 7 | ||
| 167 | #define reg_gio_r_intr___pa7___width 1 | ||
| 168 | #define reg_gio_r_intr___pa7___bit 7 | ||
| 169 | #define reg_gio_r_intr_offset 24 | ||
| 170 | |||
| 171 | /* Register r_masked_intr, scope gio, type r */ | ||
| 172 | #define reg_gio_r_masked_intr___pa0___lsb 0 | ||
| 173 | #define reg_gio_r_masked_intr___pa0___width 1 | ||
| 174 | #define reg_gio_r_masked_intr___pa0___bit 0 | ||
| 175 | #define reg_gio_r_masked_intr___pa1___lsb 1 | ||
| 176 | #define reg_gio_r_masked_intr___pa1___width 1 | ||
| 177 | #define reg_gio_r_masked_intr___pa1___bit 1 | ||
| 178 | #define reg_gio_r_masked_intr___pa2___lsb 2 | ||
| 179 | #define reg_gio_r_masked_intr___pa2___width 1 | ||
| 180 | #define reg_gio_r_masked_intr___pa2___bit 2 | ||
| 181 | #define reg_gio_r_masked_intr___pa3___lsb 3 | ||
| 182 | #define reg_gio_r_masked_intr___pa3___width 1 | ||
| 183 | #define reg_gio_r_masked_intr___pa3___bit 3 | ||
| 184 | #define reg_gio_r_masked_intr___pa4___lsb 4 | ||
| 185 | #define reg_gio_r_masked_intr___pa4___width 1 | ||
| 186 | #define reg_gio_r_masked_intr___pa4___bit 4 | ||
| 187 | #define reg_gio_r_masked_intr___pa5___lsb 5 | ||
| 188 | #define reg_gio_r_masked_intr___pa5___width 1 | ||
| 189 | #define reg_gio_r_masked_intr___pa5___bit 5 | ||
| 190 | #define reg_gio_r_masked_intr___pa6___lsb 6 | ||
| 191 | #define reg_gio_r_masked_intr___pa6___width 1 | ||
| 192 | #define reg_gio_r_masked_intr___pa6___bit 6 | ||
| 193 | #define reg_gio_r_masked_intr___pa7___lsb 7 | ||
| 194 | #define reg_gio_r_masked_intr___pa7___width 1 | ||
| 195 | #define reg_gio_r_masked_intr___pa7___bit 7 | ||
| 196 | #define reg_gio_r_masked_intr_offset 28 | ||
| 197 | |||
| 198 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 199 | #define reg_gio_rw_pb_dout___data___lsb 0 | ||
| 200 | #define reg_gio_rw_pb_dout___data___width 18 | ||
| 201 | #define reg_gio_rw_pb_dout_offset 32 | ||
| 202 | |||
| 203 | /* Register r_pb_din, scope gio, type r */ | ||
| 204 | #define reg_gio_r_pb_din___data___lsb 0 | ||
| 205 | #define reg_gio_r_pb_din___data___width 18 | ||
| 206 | #define reg_gio_r_pb_din_offset 36 | ||
| 207 | |||
| 208 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 209 | #define reg_gio_rw_pb_oe___oe___lsb 0 | ||
| 210 | #define reg_gio_rw_pb_oe___oe___width 18 | ||
| 211 | #define reg_gio_rw_pb_oe_offset 40 | ||
| 212 | |||
| 213 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 214 | #define reg_gio_rw_pc_dout___data___lsb 0 | ||
| 215 | #define reg_gio_rw_pc_dout___data___width 18 | ||
| 216 | #define reg_gio_rw_pc_dout_offset 48 | ||
| 217 | |||
| 218 | /* Register r_pc_din, scope gio, type r */ | ||
| 219 | #define reg_gio_r_pc_din___data___lsb 0 | ||
| 220 | #define reg_gio_r_pc_din___data___width 18 | ||
| 221 | #define reg_gio_r_pc_din_offset 52 | ||
| 222 | |||
| 223 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 224 | #define reg_gio_rw_pc_oe___oe___lsb 0 | ||
| 225 | #define reg_gio_rw_pc_oe___oe___width 18 | ||
| 226 | #define reg_gio_rw_pc_oe_offset 56 | ||
| 227 | |||
| 228 | /* Register rw_pd_dout, scope gio, type rw */ | ||
| 229 | #define reg_gio_rw_pd_dout___data___lsb 0 | ||
| 230 | #define reg_gio_rw_pd_dout___data___width 18 | ||
| 231 | #define reg_gio_rw_pd_dout_offset 64 | ||
| 232 | |||
| 233 | /* Register r_pd_din, scope gio, type r */ | ||
| 234 | #define reg_gio_r_pd_din___data___lsb 0 | ||
| 235 | #define reg_gio_r_pd_din___data___width 18 | ||
| 236 | #define reg_gio_r_pd_din_offset 68 | ||
| 237 | |||
| 238 | /* Register rw_pd_oe, scope gio, type rw */ | ||
| 239 | #define reg_gio_rw_pd_oe___oe___lsb 0 | ||
| 240 | #define reg_gio_rw_pd_oe___oe___width 18 | ||
| 241 | #define reg_gio_rw_pd_oe_offset 72 | ||
| 242 | |||
| 243 | /* Register rw_pe_dout, scope gio, type rw */ | ||
| 244 | #define reg_gio_rw_pe_dout___data___lsb 0 | ||
| 245 | #define reg_gio_rw_pe_dout___data___width 18 | ||
| 246 | #define reg_gio_rw_pe_dout_offset 80 | ||
| 247 | |||
| 248 | /* Register r_pe_din, scope gio, type r */ | ||
| 249 | #define reg_gio_r_pe_din___data___lsb 0 | ||
| 250 | #define reg_gio_r_pe_din___data___width 18 | ||
| 251 | #define reg_gio_r_pe_din_offset 84 | ||
| 252 | |||
| 253 | /* Register rw_pe_oe, scope gio, type rw */ | ||
| 254 | #define reg_gio_rw_pe_oe___oe___lsb 0 | ||
| 255 | #define reg_gio_rw_pe_oe___oe___width 18 | ||
| 256 | #define reg_gio_rw_pe_oe_offset 88 | ||
| 257 | |||
| 258 | |||
| 259 | /* Constants */ | ||
| 260 | #define regk_gio_anyedge 0x00000007 | ||
| 261 | #define regk_gio_hi 0x00000001 | ||
| 262 | #define regk_gio_lo 0x00000002 | ||
| 263 | #define regk_gio_negedge 0x00000006 | ||
| 264 | #define regk_gio_no 0x00000000 | ||
| 265 | #define regk_gio_off 0x00000000 | ||
| 266 | #define regk_gio_posedge 0x00000005 | ||
| 267 | #define regk_gio_rw_intr_cfg_default 0x00000000 | ||
| 268 | #define regk_gio_rw_intr_mask_default 0x00000000 | ||
| 269 | #define regk_gio_rw_pa_oe_default 0x00000000 | ||
| 270 | #define regk_gio_rw_pb_oe_default 0x00000000 | ||
| 271 | #define regk_gio_rw_pc_oe_default 0x00000000 | ||
| 272 | #define regk_gio_rw_pd_oe_default 0x00000000 | ||
| 273 | #define regk_gio_rw_pe_oe_default 0x00000000 | ||
| 274 | #define regk_gio_set 0x00000003 | ||
| 275 | #define regk_gio_yes 0x00000001 | ||
| 276 | #endif /* __gio_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h deleted file mode 100644 index c8315905c571..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version | ||
| 2 | from ../../inst/intr_vect/rtl/guinness/ivmask.config.r | ||
| 3 | version . */ | ||
| 4 | |||
| 5 | #ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R | ||
| 6 | #define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R | ||
| 7 | #define MEMARB_INTR_VECT 0x31 | ||
| 8 | #define GEN_IO_INTR_VECT 0x32 | ||
| 9 | #define IOP0_INTR_VECT 0x33 | ||
| 10 | #define IOP1_INTR_VECT 0x34 | ||
| 11 | #define IOP2_INTR_VECT 0x35 | ||
| 12 | #define IOP3_INTR_VECT 0x36 | ||
| 13 | #define DMA0_INTR_VECT 0x37 | ||
| 14 | #define DMA1_INTR_VECT 0x38 | ||
| 15 | #define DMA2_INTR_VECT 0x39 | ||
| 16 | #define DMA3_INTR_VECT 0x3a | ||
| 17 | #define DMA4_INTR_VECT 0x3b | ||
| 18 | #define DMA5_INTR_VECT 0x3c | ||
| 19 | #define DMA6_INTR_VECT 0x3d | ||
| 20 | #define DMA7_INTR_VECT 0x3e | ||
| 21 | #define DMA8_INTR_VECT 0x3f | ||
| 22 | #define DMA9_INTR_VECT 0x40 | ||
| 23 | #define ATA_INTR_VECT 0x41 | ||
| 24 | #define SSER0_INTR_VECT 0x42 | ||
| 25 | #define SSER1_INTR_VECT 0x43 | ||
| 26 | #define SER0_INTR_VECT 0x44 | ||
| 27 | #define SER1_INTR_VECT 0x45 | ||
| 28 | #define SER2_INTR_VECT 0x46 | ||
| 29 | #define SER3_INTR_VECT 0x47 | ||
| 30 | #define P21_INTR_VECT 0x48 | ||
| 31 | #define ETH0_INTR_VECT 0x49 | ||
| 32 | #define ETH1_INTR_VECT 0x4a | ||
| 33 | #define TIMER_INTR_VECT 0x4b | ||
| 34 | #define BIF_ARB_INTR_VECT 0x4c | ||
| 35 | #define BIF_DMA_INTR_VECT 0x4d | ||
| 36 | #define EXT_INTR_VECT 0x4e | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h deleted file mode 100644 index 6df2a433b02d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h +++ /dev/null | |||
| @@ -1,355 +0,0 @@ | |||
| 1 | #ifndef __intr_vect_defs_asm_h | ||
| 2 | #define __intr_vect_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r | ||
| 7 | * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:03 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r | ||
| 11 | * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_mask, scope intr_vect, type rw */ | ||
| 57 | #define reg_intr_vect_rw_mask___memarb___lsb 0 | ||
| 58 | #define reg_intr_vect_rw_mask___memarb___width 1 | ||
| 59 | #define reg_intr_vect_rw_mask___memarb___bit 0 | ||
| 60 | #define reg_intr_vect_rw_mask___gen_io___lsb 1 | ||
| 61 | #define reg_intr_vect_rw_mask___gen_io___width 1 | ||
| 62 | #define reg_intr_vect_rw_mask___gen_io___bit 1 | ||
| 63 | #define reg_intr_vect_rw_mask___iop0___lsb 2 | ||
| 64 | #define reg_intr_vect_rw_mask___iop0___width 1 | ||
| 65 | #define reg_intr_vect_rw_mask___iop0___bit 2 | ||
| 66 | #define reg_intr_vect_rw_mask___iop1___lsb 3 | ||
| 67 | #define reg_intr_vect_rw_mask___iop1___width 1 | ||
| 68 | #define reg_intr_vect_rw_mask___iop1___bit 3 | ||
| 69 | #define reg_intr_vect_rw_mask___iop2___lsb 4 | ||
| 70 | #define reg_intr_vect_rw_mask___iop2___width 1 | ||
| 71 | #define reg_intr_vect_rw_mask___iop2___bit 4 | ||
| 72 | #define reg_intr_vect_rw_mask___iop3___lsb 5 | ||
| 73 | #define reg_intr_vect_rw_mask___iop3___width 1 | ||
| 74 | #define reg_intr_vect_rw_mask___iop3___bit 5 | ||
| 75 | #define reg_intr_vect_rw_mask___dma0___lsb 6 | ||
| 76 | #define reg_intr_vect_rw_mask___dma0___width 1 | ||
| 77 | #define reg_intr_vect_rw_mask___dma0___bit 6 | ||
| 78 | #define reg_intr_vect_rw_mask___dma1___lsb 7 | ||
| 79 | #define reg_intr_vect_rw_mask___dma1___width 1 | ||
| 80 | #define reg_intr_vect_rw_mask___dma1___bit 7 | ||
| 81 | #define reg_intr_vect_rw_mask___dma2___lsb 8 | ||
| 82 | #define reg_intr_vect_rw_mask___dma2___width 1 | ||
| 83 | #define reg_intr_vect_rw_mask___dma2___bit 8 | ||
| 84 | #define reg_intr_vect_rw_mask___dma3___lsb 9 | ||
| 85 | #define reg_intr_vect_rw_mask___dma3___width 1 | ||
| 86 | #define reg_intr_vect_rw_mask___dma3___bit 9 | ||
| 87 | #define reg_intr_vect_rw_mask___dma4___lsb 10 | ||
| 88 | #define reg_intr_vect_rw_mask___dma4___width 1 | ||
| 89 | #define reg_intr_vect_rw_mask___dma4___bit 10 | ||
| 90 | #define reg_intr_vect_rw_mask___dma5___lsb 11 | ||
| 91 | #define reg_intr_vect_rw_mask___dma5___width 1 | ||
| 92 | #define reg_intr_vect_rw_mask___dma5___bit 11 | ||
| 93 | #define reg_intr_vect_rw_mask___dma6___lsb 12 | ||
| 94 | #define reg_intr_vect_rw_mask___dma6___width 1 | ||
| 95 | #define reg_intr_vect_rw_mask___dma6___bit 12 | ||
| 96 | #define reg_intr_vect_rw_mask___dma7___lsb 13 | ||
| 97 | #define reg_intr_vect_rw_mask___dma7___width 1 | ||
| 98 | #define reg_intr_vect_rw_mask___dma7___bit 13 | ||
| 99 | #define reg_intr_vect_rw_mask___dma8___lsb 14 | ||
| 100 | #define reg_intr_vect_rw_mask___dma8___width 1 | ||
| 101 | #define reg_intr_vect_rw_mask___dma8___bit 14 | ||
| 102 | #define reg_intr_vect_rw_mask___dma9___lsb 15 | ||
| 103 | #define reg_intr_vect_rw_mask___dma9___width 1 | ||
| 104 | #define reg_intr_vect_rw_mask___dma9___bit 15 | ||
| 105 | #define reg_intr_vect_rw_mask___ata___lsb 16 | ||
| 106 | #define reg_intr_vect_rw_mask___ata___width 1 | ||
| 107 | #define reg_intr_vect_rw_mask___ata___bit 16 | ||
| 108 | #define reg_intr_vect_rw_mask___sser0___lsb 17 | ||
| 109 | #define reg_intr_vect_rw_mask___sser0___width 1 | ||
| 110 | #define reg_intr_vect_rw_mask___sser0___bit 17 | ||
| 111 | #define reg_intr_vect_rw_mask___sser1___lsb 18 | ||
| 112 | #define reg_intr_vect_rw_mask___sser1___width 1 | ||
| 113 | #define reg_intr_vect_rw_mask___sser1___bit 18 | ||
| 114 | #define reg_intr_vect_rw_mask___ser0___lsb 19 | ||
| 115 | #define reg_intr_vect_rw_mask___ser0___width 1 | ||
| 116 | #define reg_intr_vect_rw_mask___ser0___bit 19 | ||
| 117 | #define reg_intr_vect_rw_mask___ser1___lsb 20 | ||
| 118 | #define reg_intr_vect_rw_mask___ser1___width 1 | ||
| 119 | #define reg_intr_vect_rw_mask___ser1___bit 20 | ||
| 120 | #define reg_intr_vect_rw_mask___ser2___lsb 21 | ||
| 121 | #define reg_intr_vect_rw_mask___ser2___width 1 | ||
| 122 | #define reg_intr_vect_rw_mask___ser2___bit 21 | ||
| 123 | #define reg_intr_vect_rw_mask___ser3___lsb 22 | ||
| 124 | #define reg_intr_vect_rw_mask___ser3___width 1 | ||
| 125 | #define reg_intr_vect_rw_mask___ser3___bit 22 | ||
| 126 | #define reg_intr_vect_rw_mask___p21___lsb 23 | ||
| 127 | #define reg_intr_vect_rw_mask___p21___width 1 | ||
| 128 | #define reg_intr_vect_rw_mask___p21___bit 23 | ||
| 129 | #define reg_intr_vect_rw_mask___eth0___lsb 24 | ||
| 130 | #define reg_intr_vect_rw_mask___eth0___width 1 | ||
| 131 | #define reg_intr_vect_rw_mask___eth0___bit 24 | ||
| 132 | #define reg_intr_vect_rw_mask___eth1___lsb 25 | ||
| 133 | #define reg_intr_vect_rw_mask___eth1___width 1 | ||
| 134 | #define reg_intr_vect_rw_mask___eth1___bit 25 | ||
| 135 | #define reg_intr_vect_rw_mask___timer___lsb 26 | ||
| 136 | #define reg_intr_vect_rw_mask___timer___width 1 | ||
| 137 | #define reg_intr_vect_rw_mask___timer___bit 26 | ||
| 138 | #define reg_intr_vect_rw_mask___bif_arb___lsb 27 | ||
| 139 | #define reg_intr_vect_rw_mask___bif_arb___width 1 | ||
| 140 | #define reg_intr_vect_rw_mask___bif_arb___bit 27 | ||
| 141 | #define reg_intr_vect_rw_mask___bif_dma___lsb 28 | ||
| 142 | #define reg_intr_vect_rw_mask___bif_dma___width 1 | ||
| 143 | #define reg_intr_vect_rw_mask___bif_dma___bit 28 | ||
| 144 | #define reg_intr_vect_rw_mask___ext___lsb 29 | ||
| 145 | #define reg_intr_vect_rw_mask___ext___width 1 | ||
| 146 | #define reg_intr_vect_rw_mask___ext___bit 29 | ||
| 147 | #define reg_intr_vect_rw_mask_offset 0 | ||
| 148 | |||
| 149 | /* Register r_vect, scope intr_vect, type r */ | ||
| 150 | #define reg_intr_vect_r_vect___memarb___lsb 0 | ||
| 151 | #define reg_intr_vect_r_vect___memarb___width 1 | ||
| 152 | #define reg_intr_vect_r_vect___memarb___bit 0 | ||
| 153 | #define reg_intr_vect_r_vect___gen_io___lsb 1 | ||
| 154 | #define reg_intr_vect_r_vect___gen_io___width 1 | ||
| 155 | #define reg_intr_vect_r_vect___gen_io___bit 1 | ||
| 156 | #define reg_intr_vect_r_vect___iop0___lsb 2 | ||
| 157 | #define reg_intr_vect_r_vect___iop0___width 1 | ||
| 158 | #define reg_intr_vect_r_vect___iop0___bit 2 | ||
| 159 | #define reg_intr_vect_r_vect___iop1___lsb 3 | ||
| 160 | #define reg_intr_vect_r_vect___iop1___width 1 | ||
| 161 | #define reg_intr_vect_r_vect___iop1___bit 3 | ||
| 162 | #define reg_intr_vect_r_vect___iop2___lsb 4 | ||
| 163 | #define reg_intr_vect_r_vect___iop2___width 1 | ||
| 164 | #define reg_intr_vect_r_vect___iop2___bit 4 | ||
| 165 | #define reg_intr_vect_r_vect___iop3___lsb 5 | ||
| 166 | #define reg_intr_vect_r_vect___iop3___width 1 | ||
| 167 | #define reg_intr_vect_r_vect___iop3___bit 5 | ||
| 168 | #define reg_intr_vect_r_vect___dma0___lsb 6 | ||
| 169 | #define reg_intr_vect_r_vect___dma0___width 1 | ||
| 170 | #define reg_intr_vect_r_vect___dma0___bit 6 | ||
| 171 | #define reg_intr_vect_r_vect___dma1___lsb 7 | ||
| 172 | #define reg_intr_vect_r_vect___dma1___width 1 | ||
| 173 | #define reg_intr_vect_r_vect___dma1___bit 7 | ||
| 174 | #define reg_intr_vect_r_vect___dma2___lsb 8 | ||
| 175 | #define reg_intr_vect_r_vect___dma2___width 1 | ||
| 176 | #define reg_intr_vect_r_vect___dma2___bit 8 | ||
| 177 | #define reg_intr_vect_r_vect___dma3___lsb 9 | ||
| 178 | #define reg_intr_vect_r_vect___dma3___width 1 | ||
| 179 | #define reg_intr_vect_r_vect___dma3___bit 9 | ||
| 180 | #define reg_intr_vect_r_vect___dma4___lsb 10 | ||
| 181 | #define reg_intr_vect_r_vect___dma4___width 1 | ||
| 182 | #define reg_intr_vect_r_vect___dma4___bit 10 | ||
| 183 | #define reg_intr_vect_r_vect___dma5___lsb 11 | ||
| 184 | #define reg_intr_vect_r_vect___dma5___width 1 | ||
| 185 | #define reg_intr_vect_r_vect___dma5___bit 11 | ||
| 186 | #define reg_intr_vect_r_vect___dma6___lsb 12 | ||
| 187 | #define reg_intr_vect_r_vect___dma6___width 1 | ||
| 188 | #define reg_intr_vect_r_vect___dma6___bit 12 | ||
| 189 | #define reg_intr_vect_r_vect___dma7___lsb 13 | ||
| 190 | #define reg_intr_vect_r_vect___dma7___width 1 | ||
| 191 | #define reg_intr_vect_r_vect___dma7___bit 13 | ||
| 192 | #define reg_intr_vect_r_vect___dma8___lsb 14 | ||
| 193 | #define reg_intr_vect_r_vect___dma8___width 1 | ||
| 194 | #define reg_intr_vect_r_vect___dma8___bit 14 | ||
| 195 | #define reg_intr_vect_r_vect___dma9___lsb 15 | ||
| 196 | #define reg_intr_vect_r_vect___dma9___width 1 | ||
| 197 | #define reg_intr_vect_r_vect___dma9___bit 15 | ||
| 198 | #define reg_intr_vect_r_vect___ata___lsb 16 | ||
| 199 | #define reg_intr_vect_r_vect___ata___width 1 | ||
| 200 | #define reg_intr_vect_r_vect___ata___bit 16 | ||
| 201 | #define reg_intr_vect_r_vect___sser0___lsb 17 | ||
| 202 | #define reg_intr_vect_r_vect___sser0___width 1 | ||
| 203 | #define reg_intr_vect_r_vect___sser0___bit 17 | ||
| 204 | #define reg_intr_vect_r_vect___sser1___lsb 18 | ||
| 205 | #define reg_intr_vect_r_vect___sser1___width 1 | ||
| 206 | #define reg_intr_vect_r_vect___sser1___bit 18 | ||
| 207 | #define reg_intr_vect_r_vect___ser0___lsb 19 | ||
| 208 | #define reg_intr_vect_r_vect___ser0___width 1 | ||
| 209 | #define reg_intr_vect_r_vect___ser0___bit 19 | ||
| 210 | #define reg_intr_vect_r_vect___ser1___lsb 20 | ||
| 211 | #define reg_intr_vect_r_vect___ser1___width 1 | ||
| 212 | #define reg_intr_vect_r_vect___ser1___bit 20 | ||
| 213 | #define reg_intr_vect_r_vect___ser2___lsb 21 | ||
| 214 | #define reg_intr_vect_r_vect___ser2___width 1 | ||
| 215 | #define reg_intr_vect_r_vect___ser2___bit 21 | ||
| 216 | #define reg_intr_vect_r_vect___ser3___lsb 22 | ||
| 217 | #define reg_intr_vect_r_vect___ser3___width 1 | ||
| 218 | #define reg_intr_vect_r_vect___ser3___bit 22 | ||
| 219 | #define reg_intr_vect_r_vect___p21___lsb 23 | ||
| 220 | #define reg_intr_vect_r_vect___p21___width 1 | ||
| 221 | #define reg_intr_vect_r_vect___p21___bit 23 | ||
| 222 | #define reg_intr_vect_r_vect___eth0___lsb 24 | ||
| 223 | #define reg_intr_vect_r_vect___eth0___width 1 | ||
| 224 | #define reg_intr_vect_r_vect___eth0___bit 24 | ||
| 225 | #define reg_intr_vect_r_vect___eth1___lsb 25 | ||
| 226 | #define reg_intr_vect_r_vect___eth1___width 1 | ||
| 227 | #define reg_intr_vect_r_vect___eth1___bit 25 | ||
| 228 | #define reg_intr_vect_r_vect___timer___lsb 26 | ||
| 229 | #define reg_intr_vect_r_vect___timer___width 1 | ||
| 230 | #define reg_intr_vect_r_vect___timer___bit 26 | ||
| 231 | #define reg_intr_vect_r_vect___bif_arb___lsb 27 | ||
| 232 | #define reg_intr_vect_r_vect___bif_arb___width 1 | ||
| 233 | #define reg_intr_vect_r_vect___bif_arb___bit 27 | ||
| 234 | #define reg_intr_vect_r_vect___bif_dma___lsb 28 | ||
| 235 | #define reg_intr_vect_r_vect___bif_dma___width 1 | ||
| 236 | #define reg_intr_vect_r_vect___bif_dma___bit 28 | ||
| 237 | #define reg_intr_vect_r_vect___ext___lsb 29 | ||
| 238 | #define reg_intr_vect_r_vect___ext___width 1 | ||
| 239 | #define reg_intr_vect_r_vect___ext___bit 29 | ||
| 240 | #define reg_intr_vect_r_vect_offset 4 | ||
| 241 | |||
| 242 | /* Register r_masked_vect, scope intr_vect, type r */ | ||
| 243 | #define reg_intr_vect_r_masked_vect___memarb___lsb 0 | ||
| 244 | #define reg_intr_vect_r_masked_vect___memarb___width 1 | ||
| 245 | #define reg_intr_vect_r_masked_vect___memarb___bit 0 | ||
| 246 | #define reg_intr_vect_r_masked_vect___gen_io___lsb 1 | ||
| 247 | #define reg_intr_vect_r_masked_vect___gen_io___width 1 | ||
| 248 | #define reg_intr_vect_r_masked_vect___gen_io___bit 1 | ||
| 249 | #define reg_intr_vect_r_masked_vect___iop0___lsb 2 | ||
| 250 | #define reg_intr_vect_r_masked_vect___iop0___width 1 | ||
| 251 | #define reg_intr_vect_r_masked_vect___iop0___bit 2 | ||
| 252 | #define reg_intr_vect_r_masked_vect___iop1___lsb 3 | ||
| 253 | #define reg_intr_vect_r_masked_vect___iop1___width 1 | ||
| 254 | #define reg_intr_vect_r_masked_vect___iop1___bit 3 | ||
| 255 | #define reg_intr_vect_r_masked_vect___iop2___lsb 4 | ||
| 256 | #define reg_intr_vect_r_masked_vect___iop2___width 1 | ||
| 257 | #define reg_intr_vect_r_masked_vect___iop2___bit 4 | ||
| 258 | #define reg_intr_vect_r_masked_vect___iop3___lsb 5 | ||
| 259 | #define reg_intr_vect_r_masked_vect___iop3___width 1 | ||
| 260 | #define reg_intr_vect_r_masked_vect___iop3___bit 5 | ||
| 261 | #define reg_intr_vect_r_masked_vect___dma0___lsb 6 | ||
| 262 | #define reg_intr_vect_r_masked_vect___dma0___width 1 | ||
| 263 | #define reg_intr_vect_r_masked_vect___dma0___bit 6 | ||
| 264 | #define reg_intr_vect_r_masked_vect___dma1___lsb 7 | ||
| 265 | #define reg_intr_vect_r_masked_vect___dma1___width 1 | ||
| 266 | #define reg_intr_vect_r_masked_vect___dma1___bit 7 | ||
| 267 | #define reg_intr_vect_r_masked_vect___dma2___lsb 8 | ||
| 268 | #define reg_intr_vect_r_masked_vect___dma2___width 1 | ||
| 269 | #define reg_intr_vect_r_masked_vect___dma2___bit 8 | ||
| 270 | #define reg_intr_vect_r_masked_vect___dma3___lsb 9 | ||
| 271 | #define reg_intr_vect_r_masked_vect___dma3___width 1 | ||
| 272 | #define reg_intr_vect_r_masked_vect___dma3___bit 9 | ||
| 273 | #define reg_intr_vect_r_masked_vect___dma4___lsb 10 | ||
| 274 | #define reg_intr_vect_r_masked_vect___dma4___width 1 | ||
| 275 | #define reg_intr_vect_r_masked_vect___dma4___bit 10 | ||
| 276 | #define reg_intr_vect_r_masked_vect___dma5___lsb 11 | ||
| 277 | #define reg_intr_vect_r_masked_vect___dma5___width 1 | ||
| 278 | #define reg_intr_vect_r_masked_vect___dma5___bit 11 | ||
| 279 | #define reg_intr_vect_r_masked_vect___dma6___lsb 12 | ||
| 280 | #define reg_intr_vect_r_masked_vect___dma6___width 1 | ||
| 281 | #define reg_intr_vect_r_masked_vect___dma6___bit 12 | ||
| 282 | #define reg_intr_vect_r_masked_vect___dma7___lsb 13 | ||
| 283 | #define reg_intr_vect_r_masked_vect___dma7___width 1 | ||
| 284 | #define reg_intr_vect_r_masked_vect___dma7___bit 13 | ||
| 285 | #define reg_intr_vect_r_masked_vect___dma8___lsb 14 | ||
| 286 | #define reg_intr_vect_r_masked_vect___dma8___width 1 | ||
| 287 | #define reg_intr_vect_r_masked_vect___dma8___bit 14 | ||
| 288 | #define reg_intr_vect_r_masked_vect___dma9___lsb 15 | ||
| 289 | #define reg_intr_vect_r_masked_vect___dma9___width 1 | ||
| 290 | #define reg_intr_vect_r_masked_vect___dma9___bit 15 | ||
| 291 | #define reg_intr_vect_r_masked_vect___ata___lsb 16 | ||
| 292 | #define reg_intr_vect_r_masked_vect___ata___width 1 | ||
| 293 | #define reg_intr_vect_r_masked_vect___ata___bit 16 | ||
| 294 | #define reg_intr_vect_r_masked_vect___sser0___lsb 17 | ||
| 295 | #define reg_intr_vect_r_masked_vect___sser0___width 1 | ||
| 296 | #define reg_intr_vect_r_masked_vect___sser0___bit 17 | ||
| 297 | #define reg_intr_vect_r_masked_vect___sser1___lsb 18 | ||
| 298 | #define reg_intr_vect_r_masked_vect___sser1___width 1 | ||
| 299 | #define reg_intr_vect_r_masked_vect___sser1___bit 18 | ||
| 300 | #define reg_intr_vect_r_masked_vect___ser0___lsb 19 | ||
| 301 | #define reg_intr_vect_r_masked_vect___ser0___width 1 | ||
| 302 | #define reg_intr_vect_r_masked_vect___ser0___bit 19 | ||
| 303 | #define reg_intr_vect_r_masked_vect___ser1___lsb 20 | ||
| 304 | #define reg_intr_vect_r_masked_vect___ser1___width 1 | ||
| 305 | #define reg_intr_vect_r_masked_vect___ser1___bit 20 | ||
| 306 | #define reg_intr_vect_r_masked_vect___ser2___lsb 21 | ||
| 307 | #define reg_intr_vect_r_masked_vect___ser2___width 1 | ||
| 308 | #define reg_intr_vect_r_masked_vect___ser2___bit 21 | ||
| 309 | #define reg_intr_vect_r_masked_vect___ser3___lsb 22 | ||
| 310 | #define reg_intr_vect_r_masked_vect___ser3___width 1 | ||
| 311 | #define reg_intr_vect_r_masked_vect___ser3___bit 22 | ||
| 312 | #define reg_intr_vect_r_masked_vect___p21___lsb 23 | ||
| 313 | #define reg_intr_vect_r_masked_vect___p21___width 1 | ||
| 314 | #define reg_intr_vect_r_masked_vect___p21___bit 23 | ||
| 315 | #define reg_intr_vect_r_masked_vect___eth0___lsb 24 | ||
| 316 | #define reg_intr_vect_r_masked_vect___eth0___width 1 | ||
| 317 | #define reg_intr_vect_r_masked_vect___eth0___bit 24 | ||
| 318 | #define reg_intr_vect_r_masked_vect___eth1___lsb 25 | ||
| 319 | #define reg_intr_vect_r_masked_vect___eth1___width 1 | ||
| 320 | #define reg_intr_vect_r_masked_vect___eth1___bit 25 | ||
| 321 | #define reg_intr_vect_r_masked_vect___timer___lsb 26 | ||
| 322 | #define reg_intr_vect_r_masked_vect___timer___width 1 | ||
| 323 | #define reg_intr_vect_r_masked_vect___timer___bit 26 | ||
| 324 | #define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 | ||
| 325 | #define reg_intr_vect_r_masked_vect___bif_arb___width 1 | ||
| 326 | #define reg_intr_vect_r_masked_vect___bif_arb___bit 27 | ||
| 327 | #define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 | ||
| 328 | #define reg_intr_vect_r_masked_vect___bif_dma___width 1 | ||
| 329 | #define reg_intr_vect_r_masked_vect___bif_dma___bit 28 | ||
| 330 | #define reg_intr_vect_r_masked_vect___ext___lsb 29 | ||
| 331 | #define reg_intr_vect_r_masked_vect___ext___width 1 | ||
| 332 | #define reg_intr_vect_r_masked_vect___ext___bit 29 | ||
| 333 | #define reg_intr_vect_r_masked_vect_offset 8 | ||
| 334 | |||
| 335 | /* Register r_nmi, scope intr_vect, type r */ | ||
| 336 | #define reg_intr_vect_r_nmi___ext___lsb 0 | ||
| 337 | #define reg_intr_vect_r_nmi___ext___width 1 | ||
| 338 | #define reg_intr_vect_r_nmi___ext___bit 0 | ||
| 339 | #define reg_intr_vect_r_nmi___watchdog___lsb 1 | ||
| 340 | #define reg_intr_vect_r_nmi___watchdog___width 1 | ||
| 341 | #define reg_intr_vect_r_nmi___watchdog___bit 1 | ||
| 342 | #define reg_intr_vect_r_nmi_offset 12 | ||
| 343 | |||
| 344 | /* Register r_guru, scope intr_vect, type r */ | ||
| 345 | #define reg_intr_vect_r_guru___jtag___lsb 0 | ||
| 346 | #define reg_intr_vect_r_guru___jtag___width 1 | ||
| 347 | #define reg_intr_vect_r_guru___jtag___bit 0 | ||
| 348 | #define reg_intr_vect_r_guru_offset 16 | ||
| 349 | |||
| 350 | |||
| 351 | /* Constants */ | ||
| 352 | #define regk_intr_vect_off 0x00000000 | ||
| 353 | #define regk_intr_vect_on 0x00000001 | ||
| 354 | #define regk_intr_vect_rw_mask_default 0x00000000 | ||
| 355 | #endif /* __intr_vect_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h deleted file mode 100644 index 0c8084054840..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h +++ /dev/null | |||
| @@ -1,69 +0,0 @@ | |||
| 1 | #ifndef __irq_nmi_defs_asm_h | ||
| 2 | #define __irq_nmi_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../mod/irq_nmi.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Thu Jan 22 09:22:43 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r | ||
| 11 | * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cmd, scope irq_nmi, type rw */ | ||
| 57 | #define reg_irq_nmi_rw_cmd___delay___lsb 0 | ||
| 58 | #define reg_irq_nmi_rw_cmd___delay___width 16 | ||
| 59 | #define reg_irq_nmi_rw_cmd___op___lsb 16 | ||
| 60 | #define reg_irq_nmi_rw_cmd___op___width 2 | ||
| 61 | #define reg_irq_nmi_rw_cmd_offset 0 | ||
| 62 | |||
| 63 | |||
| 64 | /* Constants */ | ||
| 65 | #define regk_irq_nmi_ack_irq 0x00000002 | ||
| 66 | #define regk_irq_nmi_ack_nmi 0x00000003 | ||
| 67 | #define regk_irq_nmi_irq 0x00000000 | ||
| 68 | #define regk_irq_nmi_nmi 0x00000001 | ||
| 69 | #endif /* __irq_nmi_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h deleted file mode 100644 index 45400eb8d389..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h +++ /dev/null | |||
| @@ -1,579 +0,0 @@ | |||
| 1 | #ifndef __marb_defs_asm_h | ||
| 2 | #define __marb_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:12:16 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 11 | * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #define STRIDE_marb_rw_int_slots 4 | ||
| 57 | /* Register rw_int_slots, scope marb, type rw */ | ||
| 58 | #define reg_marb_rw_int_slots___owner___lsb 0 | ||
| 59 | #define reg_marb_rw_int_slots___owner___width 4 | ||
| 60 | #define reg_marb_rw_int_slots_offset 0 | ||
| 61 | |||
| 62 | #define STRIDE_marb_rw_ext_slots 4 | ||
| 63 | /* Register rw_ext_slots, scope marb, type rw */ | ||
| 64 | #define reg_marb_rw_ext_slots___owner___lsb 0 | ||
| 65 | #define reg_marb_rw_ext_slots___owner___width 4 | ||
| 66 | #define reg_marb_rw_ext_slots_offset 256 | ||
| 67 | |||
| 68 | #define STRIDE_marb_rw_regs_slots 4 | ||
| 69 | /* Register rw_regs_slots, scope marb, type rw */ | ||
| 70 | #define reg_marb_rw_regs_slots___owner___lsb 0 | ||
| 71 | #define reg_marb_rw_regs_slots___owner___width 4 | ||
| 72 | #define reg_marb_rw_regs_slots_offset 512 | ||
| 73 | |||
| 74 | /* Register rw_intr_mask, scope marb, type rw */ | ||
| 75 | #define reg_marb_rw_intr_mask___bp0___lsb 0 | ||
| 76 | #define reg_marb_rw_intr_mask___bp0___width 1 | ||
| 77 | #define reg_marb_rw_intr_mask___bp0___bit 0 | ||
| 78 | #define reg_marb_rw_intr_mask___bp1___lsb 1 | ||
| 79 | #define reg_marb_rw_intr_mask___bp1___width 1 | ||
| 80 | #define reg_marb_rw_intr_mask___bp1___bit 1 | ||
| 81 | #define reg_marb_rw_intr_mask___bp2___lsb 2 | ||
| 82 | #define reg_marb_rw_intr_mask___bp2___width 1 | ||
| 83 | #define reg_marb_rw_intr_mask___bp2___bit 2 | ||
| 84 | #define reg_marb_rw_intr_mask___bp3___lsb 3 | ||
| 85 | #define reg_marb_rw_intr_mask___bp3___width 1 | ||
| 86 | #define reg_marb_rw_intr_mask___bp3___bit 3 | ||
| 87 | #define reg_marb_rw_intr_mask_offset 528 | ||
| 88 | |||
| 89 | /* Register rw_ack_intr, scope marb, type rw */ | ||
| 90 | #define reg_marb_rw_ack_intr___bp0___lsb 0 | ||
| 91 | #define reg_marb_rw_ack_intr___bp0___width 1 | ||
| 92 | #define reg_marb_rw_ack_intr___bp0___bit 0 | ||
| 93 | #define reg_marb_rw_ack_intr___bp1___lsb 1 | ||
| 94 | #define reg_marb_rw_ack_intr___bp1___width 1 | ||
| 95 | #define reg_marb_rw_ack_intr___bp1___bit 1 | ||
| 96 | #define reg_marb_rw_ack_intr___bp2___lsb 2 | ||
| 97 | #define reg_marb_rw_ack_intr___bp2___width 1 | ||
| 98 | #define reg_marb_rw_ack_intr___bp2___bit 2 | ||
| 99 | #define reg_marb_rw_ack_intr___bp3___lsb 3 | ||
| 100 | #define reg_marb_rw_ack_intr___bp3___width 1 | ||
| 101 | #define reg_marb_rw_ack_intr___bp3___bit 3 | ||
| 102 | #define reg_marb_rw_ack_intr_offset 532 | ||
| 103 | |||
| 104 | /* Register r_intr, scope marb, type r */ | ||
| 105 | #define reg_marb_r_intr___bp0___lsb 0 | ||
| 106 | #define reg_marb_r_intr___bp0___width 1 | ||
| 107 | #define reg_marb_r_intr___bp0___bit 0 | ||
| 108 | #define reg_marb_r_intr___bp1___lsb 1 | ||
| 109 | #define reg_marb_r_intr___bp1___width 1 | ||
| 110 | #define reg_marb_r_intr___bp1___bit 1 | ||
| 111 | #define reg_marb_r_intr___bp2___lsb 2 | ||
| 112 | #define reg_marb_r_intr___bp2___width 1 | ||
| 113 | #define reg_marb_r_intr___bp2___bit 2 | ||
| 114 | #define reg_marb_r_intr___bp3___lsb 3 | ||
| 115 | #define reg_marb_r_intr___bp3___width 1 | ||
| 116 | #define reg_marb_r_intr___bp3___bit 3 | ||
| 117 | #define reg_marb_r_intr_offset 536 | ||
| 118 | |||
| 119 | /* Register r_masked_intr, scope marb, type r */ | ||
| 120 | #define reg_marb_r_masked_intr___bp0___lsb 0 | ||
| 121 | #define reg_marb_r_masked_intr___bp0___width 1 | ||
| 122 | #define reg_marb_r_masked_intr___bp0___bit 0 | ||
| 123 | #define reg_marb_r_masked_intr___bp1___lsb 1 | ||
| 124 | #define reg_marb_r_masked_intr___bp1___width 1 | ||
| 125 | #define reg_marb_r_masked_intr___bp1___bit 1 | ||
| 126 | #define reg_marb_r_masked_intr___bp2___lsb 2 | ||
| 127 | #define reg_marb_r_masked_intr___bp2___width 1 | ||
| 128 | #define reg_marb_r_masked_intr___bp2___bit 2 | ||
| 129 | #define reg_marb_r_masked_intr___bp3___lsb 3 | ||
| 130 | #define reg_marb_r_masked_intr___bp3___width 1 | ||
| 131 | #define reg_marb_r_masked_intr___bp3___bit 3 | ||
| 132 | #define reg_marb_r_masked_intr_offset 540 | ||
| 133 | |||
| 134 | /* Register rw_stop_mask, scope marb, type rw */ | ||
| 135 | #define reg_marb_rw_stop_mask___dma0___lsb 0 | ||
| 136 | #define reg_marb_rw_stop_mask___dma0___width 1 | ||
| 137 | #define reg_marb_rw_stop_mask___dma0___bit 0 | ||
| 138 | #define reg_marb_rw_stop_mask___dma1___lsb 1 | ||
| 139 | #define reg_marb_rw_stop_mask___dma1___width 1 | ||
| 140 | #define reg_marb_rw_stop_mask___dma1___bit 1 | ||
| 141 | #define reg_marb_rw_stop_mask___dma2___lsb 2 | ||
| 142 | #define reg_marb_rw_stop_mask___dma2___width 1 | ||
| 143 | #define reg_marb_rw_stop_mask___dma2___bit 2 | ||
| 144 | #define reg_marb_rw_stop_mask___dma3___lsb 3 | ||
| 145 | #define reg_marb_rw_stop_mask___dma3___width 1 | ||
| 146 | #define reg_marb_rw_stop_mask___dma3___bit 3 | ||
| 147 | #define reg_marb_rw_stop_mask___dma4___lsb 4 | ||
| 148 | #define reg_marb_rw_stop_mask___dma4___width 1 | ||
| 149 | #define reg_marb_rw_stop_mask___dma4___bit 4 | ||
| 150 | #define reg_marb_rw_stop_mask___dma5___lsb 5 | ||
| 151 | #define reg_marb_rw_stop_mask___dma5___width 1 | ||
| 152 | #define reg_marb_rw_stop_mask___dma5___bit 5 | ||
| 153 | #define reg_marb_rw_stop_mask___dma6___lsb 6 | ||
| 154 | #define reg_marb_rw_stop_mask___dma6___width 1 | ||
| 155 | #define reg_marb_rw_stop_mask___dma6___bit 6 | ||
| 156 | #define reg_marb_rw_stop_mask___dma7___lsb 7 | ||
| 157 | #define reg_marb_rw_stop_mask___dma7___width 1 | ||
| 158 | #define reg_marb_rw_stop_mask___dma7___bit 7 | ||
| 159 | #define reg_marb_rw_stop_mask___dma8___lsb 8 | ||
| 160 | #define reg_marb_rw_stop_mask___dma8___width 1 | ||
| 161 | #define reg_marb_rw_stop_mask___dma8___bit 8 | ||
| 162 | #define reg_marb_rw_stop_mask___dma9___lsb 9 | ||
| 163 | #define reg_marb_rw_stop_mask___dma9___width 1 | ||
| 164 | #define reg_marb_rw_stop_mask___dma9___bit 9 | ||
| 165 | #define reg_marb_rw_stop_mask___cpui___lsb 10 | ||
| 166 | #define reg_marb_rw_stop_mask___cpui___width 1 | ||
| 167 | #define reg_marb_rw_stop_mask___cpui___bit 10 | ||
| 168 | #define reg_marb_rw_stop_mask___cpud___lsb 11 | ||
| 169 | #define reg_marb_rw_stop_mask___cpud___width 1 | ||
| 170 | #define reg_marb_rw_stop_mask___cpud___bit 11 | ||
| 171 | #define reg_marb_rw_stop_mask___iop___lsb 12 | ||
| 172 | #define reg_marb_rw_stop_mask___iop___width 1 | ||
| 173 | #define reg_marb_rw_stop_mask___iop___bit 12 | ||
| 174 | #define reg_marb_rw_stop_mask___slave___lsb 13 | ||
| 175 | #define reg_marb_rw_stop_mask___slave___width 1 | ||
| 176 | #define reg_marb_rw_stop_mask___slave___bit 13 | ||
| 177 | #define reg_marb_rw_stop_mask_offset 544 | ||
| 178 | |||
| 179 | /* Register r_stopped, scope marb, type r */ | ||
| 180 | #define reg_marb_r_stopped___dma0___lsb 0 | ||
| 181 | #define reg_marb_r_stopped___dma0___width 1 | ||
| 182 | #define reg_marb_r_stopped___dma0___bit 0 | ||
| 183 | #define reg_marb_r_stopped___dma1___lsb 1 | ||
| 184 | #define reg_marb_r_stopped___dma1___width 1 | ||
| 185 | #define reg_marb_r_stopped___dma1___bit 1 | ||
| 186 | #define reg_marb_r_stopped___dma2___lsb 2 | ||
| 187 | #define reg_marb_r_stopped___dma2___width 1 | ||
| 188 | #define reg_marb_r_stopped___dma2___bit 2 | ||
| 189 | #define reg_marb_r_stopped___dma3___lsb 3 | ||
| 190 | #define reg_marb_r_stopped___dma3___width 1 | ||
| 191 | #define reg_marb_r_stopped___dma3___bit 3 | ||
| 192 | #define reg_marb_r_stopped___dma4___lsb 4 | ||
| 193 | #define reg_marb_r_stopped___dma4___width 1 | ||
| 194 | #define reg_marb_r_stopped___dma4___bit 4 | ||
| 195 | #define reg_marb_r_stopped___dma5___lsb 5 | ||
| 196 | #define reg_marb_r_stopped___dma5___width 1 | ||
| 197 | #define reg_marb_r_stopped___dma5___bit 5 | ||
| 198 | #define reg_marb_r_stopped___dma6___lsb 6 | ||
| 199 | #define reg_marb_r_stopped___dma6___width 1 | ||
| 200 | #define reg_marb_r_stopped___dma6___bit 6 | ||
| 201 | #define reg_marb_r_stopped___dma7___lsb 7 | ||
| 202 | #define reg_marb_r_stopped___dma7___width 1 | ||
| 203 | #define reg_marb_r_stopped___dma7___bit 7 | ||
| 204 | #define reg_marb_r_stopped___dma8___lsb 8 | ||
| 205 | #define reg_marb_r_stopped___dma8___width 1 | ||
| 206 | #define reg_marb_r_stopped___dma8___bit 8 | ||
| 207 | #define reg_marb_r_stopped___dma9___lsb 9 | ||
| 208 | #define reg_marb_r_stopped___dma9___width 1 | ||
| 209 | #define reg_marb_r_stopped___dma9___bit 9 | ||
| 210 | #define reg_marb_r_stopped___cpui___lsb 10 | ||
| 211 | #define reg_marb_r_stopped___cpui___width 1 | ||
| 212 | #define reg_marb_r_stopped___cpui___bit 10 | ||
| 213 | #define reg_marb_r_stopped___cpud___lsb 11 | ||
| 214 | #define reg_marb_r_stopped___cpud___width 1 | ||
| 215 | #define reg_marb_r_stopped___cpud___bit 11 | ||
| 216 | #define reg_marb_r_stopped___iop___lsb 12 | ||
| 217 | #define reg_marb_r_stopped___iop___width 1 | ||
| 218 | #define reg_marb_r_stopped___iop___bit 12 | ||
| 219 | #define reg_marb_r_stopped___slave___lsb 13 | ||
| 220 | #define reg_marb_r_stopped___slave___width 1 | ||
| 221 | #define reg_marb_r_stopped___slave___bit 13 | ||
| 222 | #define reg_marb_r_stopped_offset 548 | ||
| 223 | |||
| 224 | /* Register rw_no_snoop, scope marb, type rw */ | ||
| 225 | #define reg_marb_rw_no_snoop___dma0___lsb 0 | ||
| 226 | #define reg_marb_rw_no_snoop___dma0___width 1 | ||
| 227 | #define reg_marb_rw_no_snoop___dma0___bit 0 | ||
| 228 | #define reg_marb_rw_no_snoop___dma1___lsb 1 | ||
| 229 | #define reg_marb_rw_no_snoop___dma1___width 1 | ||
| 230 | #define reg_marb_rw_no_snoop___dma1___bit 1 | ||
| 231 | #define reg_marb_rw_no_snoop___dma2___lsb 2 | ||
| 232 | #define reg_marb_rw_no_snoop___dma2___width 1 | ||
| 233 | #define reg_marb_rw_no_snoop___dma2___bit 2 | ||
| 234 | #define reg_marb_rw_no_snoop___dma3___lsb 3 | ||
| 235 | #define reg_marb_rw_no_snoop___dma3___width 1 | ||
| 236 | #define reg_marb_rw_no_snoop___dma3___bit 3 | ||
| 237 | #define reg_marb_rw_no_snoop___dma4___lsb 4 | ||
| 238 | #define reg_marb_rw_no_snoop___dma4___width 1 | ||
| 239 | #define reg_marb_rw_no_snoop___dma4___bit 4 | ||
| 240 | #define reg_marb_rw_no_snoop___dma5___lsb 5 | ||
| 241 | #define reg_marb_rw_no_snoop___dma5___width 1 | ||
| 242 | #define reg_marb_rw_no_snoop___dma5___bit 5 | ||
| 243 | #define reg_marb_rw_no_snoop___dma6___lsb 6 | ||
| 244 | #define reg_marb_rw_no_snoop___dma6___width 1 | ||
| 245 | #define reg_marb_rw_no_snoop___dma6___bit 6 | ||
| 246 | #define reg_marb_rw_no_snoop___dma7___lsb 7 | ||
| 247 | #define reg_marb_rw_no_snoop___dma7___width 1 | ||
| 248 | #define reg_marb_rw_no_snoop___dma7___bit 7 | ||
| 249 | #define reg_marb_rw_no_snoop___dma8___lsb 8 | ||
| 250 | #define reg_marb_rw_no_snoop___dma8___width 1 | ||
| 251 | #define reg_marb_rw_no_snoop___dma8___bit 8 | ||
| 252 | #define reg_marb_rw_no_snoop___dma9___lsb 9 | ||
| 253 | #define reg_marb_rw_no_snoop___dma9___width 1 | ||
| 254 | #define reg_marb_rw_no_snoop___dma9___bit 9 | ||
| 255 | #define reg_marb_rw_no_snoop___cpui___lsb 10 | ||
| 256 | #define reg_marb_rw_no_snoop___cpui___width 1 | ||
| 257 | #define reg_marb_rw_no_snoop___cpui___bit 10 | ||
| 258 | #define reg_marb_rw_no_snoop___cpud___lsb 11 | ||
| 259 | #define reg_marb_rw_no_snoop___cpud___width 1 | ||
| 260 | #define reg_marb_rw_no_snoop___cpud___bit 11 | ||
| 261 | #define reg_marb_rw_no_snoop___iop___lsb 12 | ||
| 262 | #define reg_marb_rw_no_snoop___iop___width 1 | ||
| 263 | #define reg_marb_rw_no_snoop___iop___bit 12 | ||
| 264 | #define reg_marb_rw_no_snoop___slave___lsb 13 | ||
| 265 | #define reg_marb_rw_no_snoop___slave___width 1 | ||
| 266 | #define reg_marb_rw_no_snoop___slave___bit 13 | ||
| 267 | #define reg_marb_rw_no_snoop_offset 832 | ||
| 268 | |||
| 269 | /* Register rw_no_snoop_rq, scope marb, type rw */ | ||
| 270 | #define reg_marb_rw_no_snoop_rq___cpui___lsb 10 | ||
| 271 | #define reg_marb_rw_no_snoop_rq___cpui___width 1 | ||
| 272 | #define reg_marb_rw_no_snoop_rq___cpui___bit 10 | ||
| 273 | #define reg_marb_rw_no_snoop_rq___cpud___lsb 11 | ||
| 274 | #define reg_marb_rw_no_snoop_rq___cpud___width 1 | ||
| 275 | #define reg_marb_rw_no_snoop_rq___cpud___bit 11 | ||
| 276 | #define reg_marb_rw_no_snoop_rq_offset 836 | ||
| 277 | |||
| 278 | |||
| 279 | /* Constants */ | ||
| 280 | #define regk_marb_cpud 0x0000000b | ||
| 281 | #define regk_marb_cpui 0x0000000a | ||
| 282 | #define regk_marb_dma0 0x00000000 | ||
| 283 | #define regk_marb_dma1 0x00000001 | ||
| 284 | #define regk_marb_dma2 0x00000002 | ||
| 285 | #define regk_marb_dma3 0x00000003 | ||
| 286 | #define regk_marb_dma4 0x00000004 | ||
| 287 | #define regk_marb_dma5 0x00000005 | ||
| 288 | #define regk_marb_dma6 0x00000006 | ||
| 289 | #define regk_marb_dma7 0x00000007 | ||
| 290 | #define regk_marb_dma8 0x00000008 | ||
| 291 | #define regk_marb_dma9 0x00000009 | ||
| 292 | #define regk_marb_iop 0x0000000c | ||
| 293 | #define regk_marb_no 0x00000000 | ||
| 294 | #define regk_marb_r_stopped_default 0x00000000 | ||
| 295 | #define regk_marb_rw_ext_slots_default 0x00000000 | ||
| 296 | #define regk_marb_rw_ext_slots_size 0x00000040 | ||
| 297 | #define regk_marb_rw_int_slots_default 0x00000000 | ||
| 298 | #define regk_marb_rw_int_slots_size 0x00000040 | ||
| 299 | #define regk_marb_rw_intr_mask_default 0x00000000 | ||
| 300 | #define regk_marb_rw_no_snoop_default 0x00000000 | ||
| 301 | #define regk_marb_rw_no_snoop_rq_default 0x00000000 | ||
| 302 | #define regk_marb_rw_regs_slots_default 0x00000000 | ||
| 303 | #define regk_marb_rw_regs_slots_size 0x00000004 | ||
| 304 | #define regk_marb_rw_stop_mask_default 0x00000000 | ||
| 305 | #define regk_marb_slave 0x0000000d | ||
| 306 | #define regk_marb_yes 0x00000001 | ||
| 307 | #endif /* __marb_defs_asm_h */ | ||
| 308 | #ifndef __marb_bp_defs_asm_h | ||
| 309 | #define __marb_bp_defs_asm_h | ||
| 310 | |||
| 311 | /* | ||
| 312 | * This file is autogenerated from | ||
| 313 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 314 | * id: <not found> | ||
| 315 | * last modfied: Mon Apr 11 16:12:16 2005 | ||
| 316 | * | ||
| 317 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 318 | * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 319 | * Any changes here will be lost. | ||
| 320 | * | ||
| 321 | * -*- buffer-read-only: t -*- | ||
| 322 | */ | ||
| 323 | |||
| 324 | #ifndef REG_FIELD | ||
| 325 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 326 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 327 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 328 | #endif | ||
| 329 | |||
| 330 | #ifndef REG_STATE | ||
| 331 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 332 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 333 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 334 | #endif | ||
| 335 | |||
| 336 | #ifndef REG_MASK | ||
| 337 | #define REG_MASK( scope, reg, field ) \ | ||
| 338 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 339 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 340 | #endif | ||
| 341 | |||
| 342 | #ifndef REG_LSB | ||
| 343 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 344 | #endif | ||
| 345 | |||
| 346 | #ifndef REG_BIT | ||
| 347 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 348 | #endif | ||
| 349 | |||
| 350 | #ifndef REG_ADDR | ||
| 351 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 352 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 353 | #endif | ||
| 354 | |||
| 355 | #ifndef REG_ADDR_VECT | ||
| 356 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 357 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 358 | STRIDE_##scope##_##reg ) | ||
| 359 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 360 | ((inst) + offs + (index) * stride) | ||
| 361 | #endif | ||
| 362 | |||
| 363 | /* Register rw_first_addr, scope marb_bp, type rw */ | ||
| 364 | #define reg_marb_bp_rw_first_addr_offset 0 | ||
| 365 | |||
| 366 | /* Register rw_last_addr, scope marb_bp, type rw */ | ||
| 367 | #define reg_marb_bp_rw_last_addr_offset 4 | ||
| 368 | |||
| 369 | /* Register rw_op, scope marb_bp, type rw */ | ||
| 370 | #define reg_marb_bp_rw_op___rd___lsb 0 | ||
| 371 | #define reg_marb_bp_rw_op___rd___width 1 | ||
| 372 | #define reg_marb_bp_rw_op___rd___bit 0 | ||
| 373 | #define reg_marb_bp_rw_op___wr___lsb 1 | ||
| 374 | #define reg_marb_bp_rw_op___wr___width 1 | ||
| 375 | #define reg_marb_bp_rw_op___wr___bit 1 | ||
| 376 | #define reg_marb_bp_rw_op___rd_excl___lsb 2 | ||
| 377 | #define reg_marb_bp_rw_op___rd_excl___width 1 | ||
| 378 | #define reg_marb_bp_rw_op___rd_excl___bit 2 | ||
| 379 | #define reg_marb_bp_rw_op___pri_wr___lsb 3 | ||
| 380 | #define reg_marb_bp_rw_op___pri_wr___width 1 | ||
| 381 | #define reg_marb_bp_rw_op___pri_wr___bit 3 | ||
| 382 | #define reg_marb_bp_rw_op___us_rd___lsb 4 | ||
| 383 | #define reg_marb_bp_rw_op___us_rd___width 1 | ||
| 384 | #define reg_marb_bp_rw_op___us_rd___bit 4 | ||
| 385 | #define reg_marb_bp_rw_op___us_wr___lsb 5 | ||
| 386 | #define reg_marb_bp_rw_op___us_wr___width 1 | ||
| 387 | #define reg_marb_bp_rw_op___us_wr___bit 5 | ||
| 388 | #define reg_marb_bp_rw_op___us_rd_excl___lsb 6 | ||
| 389 | #define reg_marb_bp_rw_op___us_rd_excl___width 1 | ||
| 390 | #define reg_marb_bp_rw_op___us_rd_excl___bit 6 | ||
| 391 | #define reg_marb_bp_rw_op___us_pri_wr___lsb 7 | ||
| 392 | #define reg_marb_bp_rw_op___us_pri_wr___width 1 | ||
| 393 | #define reg_marb_bp_rw_op___us_pri_wr___bit 7 | ||
| 394 | #define reg_marb_bp_rw_op_offset 8 | ||
| 395 | |||
| 396 | /* Register rw_clients, scope marb_bp, type rw */ | ||
| 397 | #define reg_marb_bp_rw_clients___dma0___lsb 0 | ||
| 398 | #define reg_marb_bp_rw_clients___dma0___width 1 | ||
| 399 | #define reg_marb_bp_rw_clients___dma0___bit 0 | ||
| 400 | #define reg_marb_bp_rw_clients___dma1___lsb 1 | ||
| 401 | #define reg_marb_bp_rw_clients___dma1___width 1 | ||
| 402 | #define reg_marb_bp_rw_clients___dma1___bit 1 | ||
| 403 | #define reg_marb_bp_rw_clients___dma2___lsb 2 | ||
| 404 | #define reg_marb_bp_rw_clients___dma2___width 1 | ||
| 405 | #define reg_marb_bp_rw_clients___dma2___bit 2 | ||
| 406 | #define reg_marb_bp_rw_clients___dma3___lsb 3 | ||
| 407 | #define reg_marb_bp_rw_clients___dma3___width 1 | ||
| 408 | #define reg_marb_bp_rw_clients___dma3___bit 3 | ||
| 409 | #define reg_marb_bp_rw_clients___dma4___lsb 4 | ||
| 410 | #define reg_marb_bp_rw_clients___dma4___width 1 | ||
| 411 | #define reg_marb_bp_rw_clients___dma4___bit 4 | ||
| 412 | #define reg_marb_bp_rw_clients___dma5___lsb 5 | ||
| 413 | #define reg_marb_bp_rw_clients___dma5___width 1 | ||
| 414 | #define reg_marb_bp_rw_clients___dma5___bit 5 | ||
| 415 | #define reg_marb_bp_rw_clients___dma6___lsb 6 | ||
| 416 | #define reg_marb_bp_rw_clients___dma6___width 1 | ||
| 417 | #define reg_marb_bp_rw_clients___dma6___bit 6 | ||
| 418 | #define reg_marb_bp_rw_clients___dma7___lsb 7 | ||
| 419 | #define reg_marb_bp_rw_clients___dma7___width 1 | ||
| 420 | #define reg_marb_bp_rw_clients___dma7___bit 7 | ||
| 421 | #define reg_marb_bp_rw_clients___dma8___lsb 8 | ||
| 422 | #define reg_marb_bp_rw_clients___dma8___width 1 | ||
| 423 | #define reg_marb_bp_rw_clients___dma8___bit 8 | ||
| 424 | #define reg_marb_bp_rw_clients___dma9___lsb 9 | ||
| 425 | #define reg_marb_bp_rw_clients___dma9___width 1 | ||
| 426 | #define reg_marb_bp_rw_clients___dma9___bit 9 | ||
| 427 | #define reg_marb_bp_rw_clients___cpui___lsb 10 | ||
| 428 | #define reg_marb_bp_rw_clients___cpui___width 1 | ||
| 429 | #define reg_marb_bp_rw_clients___cpui___bit 10 | ||
| 430 | #define reg_marb_bp_rw_clients___cpud___lsb 11 | ||
| 431 | #define reg_marb_bp_rw_clients___cpud___width 1 | ||
| 432 | #define reg_marb_bp_rw_clients___cpud___bit 11 | ||
| 433 | #define reg_marb_bp_rw_clients___iop___lsb 12 | ||
| 434 | #define reg_marb_bp_rw_clients___iop___width 1 | ||
| 435 | #define reg_marb_bp_rw_clients___iop___bit 12 | ||
| 436 | #define reg_marb_bp_rw_clients___slave___lsb 13 | ||
| 437 | #define reg_marb_bp_rw_clients___slave___width 1 | ||
| 438 | #define reg_marb_bp_rw_clients___slave___bit 13 | ||
| 439 | #define reg_marb_bp_rw_clients_offset 12 | ||
| 440 | |||
| 441 | /* Register rw_options, scope marb_bp, type rw */ | ||
| 442 | #define reg_marb_bp_rw_options___wrap___lsb 0 | ||
| 443 | #define reg_marb_bp_rw_options___wrap___width 1 | ||
| 444 | #define reg_marb_bp_rw_options___wrap___bit 0 | ||
| 445 | #define reg_marb_bp_rw_options_offset 16 | ||
| 446 | |||
| 447 | /* Register r_brk_addr, scope marb_bp, type r */ | ||
| 448 | #define reg_marb_bp_r_brk_addr_offset 20 | ||
| 449 | |||
| 450 | /* Register r_brk_op, scope marb_bp, type r */ | ||
| 451 | #define reg_marb_bp_r_brk_op___rd___lsb 0 | ||
| 452 | #define reg_marb_bp_r_brk_op___rd___width 1 | ||
| 453 | #define reg_marb_bp_r_brk_op___rd___bit 0 | ||
| 454 | #define reg_marb_bp_r_brk_op___wr___lsb 1 | ||
| 455 | #define reg_marb_bp_r_brk_op___wr___width 1 | ||
| 456 | #define reg_marb_bp_r_brk_op___wr___bit 1 | ||
| 457 | #define reg_marb_bp_r_brk_op___rd_excl___lsb 2 | ||
| 458 | #define reg_marb_bp_r_brk_op___rd_excl___width 1 | ||
| 459 | #define reg_marb_bp_r_brk_op___rd_excl___bit 2 | ||
| 460 | #define reg_marb_bp_r_brk_op___pri_wr___lsb 3 | ||
| 461 | #define reg_marb_bp_r_brk_op___pri_wr___width 1 | ||
| 462 | #define reg_marb_bp_r_brk_op___pri_wr___bit 3 | ||
| 463 | #define reg_marb_bp_r_brk_op___us_rd___lsb 4 | ||
| 464 | #define reg_marb_bp_r_brk_op___us_rd___width 1 | ||
| 465 | #define reg_marb_bp_r_brk_op___us_rd___bit 4 | ||
| 466 | #define reg_marb_bp_r_brk_op___us_wr___lsb 5 | ||
| 467 | #define reg_marb_bp_r_brk_op___us_wr___width 1 | ||
| 468 | #define reg_marb_bp_r_brk_op___us_wr___bit 5 | ||
| 469 | #define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6 | ||
| 470 | #define reg_marb_bp_r_brk_op___us_rd_excl___width 1 | ||
| 471 | #define reg_marb_bp_r_brk_op___us_rd_excl___bit 6 | ||
| 472 | #define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7 | ||
| 473 | #define reg_marb_bp_r_brk_op___us_pri_wr___width 1 | ||
| 474 | #define reg_marb_bp_r_brk_op___us_pri_wr___bit 7 | ||
| 475 | #define reg_marb_bp_r_brk_op_offset 24 | ||
| 476 | |||
| 477 | /* Register r_brk_clients, scope marb_bp, type r */ | ||
| 478 | #define reg_marb_bp_r_brk_clients___dma0___lsb 0 | ||
| 479 | #define reg_marb_bp_r_brk_clients___dma0___width 1 | ||
| 480 | #define reg_marb_bp_r_brk_clients___dma0___bit 0 | ||
| 481 | #define reg_marb_bp_r_brk_clients___dma1___lsb 1 | ||
| 482 | #define reg_marb_bp_r_brk_clients___dma1___width 1 | ||
| 483 | #define reg_marb_bp_r_brk_clients___dma1___bit 1 | ||
| 484 | #define reg_marb_bp_r_brk_clients___dma2___lsb 2 | ||
| 485 | #define reg_marb_bp_r_brk_clients___dma2___width 1 | ||
| 486 | #define reg_marb_bp_r_brk_clients___dma2___bit 2 | ||
| 487 | #define reg_marb_bp_r_brk_clients___dma3___lsb 3 | ||
| 488 | #define reg_marb_bp_r_brk_clients___dma3___width 1 | ||
| 489 | #define reg_marb_bp_r_brk_clients___dma3___bit 3 | ||
| 490 | #define reg_marb_bp_r_brk_clients___dma4___lsb 4 | ||
| 491 | #define reg_marb_bp_r_brk_clients___dma4___width 1 | ||
| 492 | #define reg_marb_bp_r_brk_clients___dma4___bit 4 | ||
| 493 | #define reg_marb_bp_r_brk_clients___dma5___lsb 5 | ||
| 494 | #define reg_marb_bp_r_brk_clients___dma5___width 1 | ||
| 495 | #define reg_marb_bp_r_brk_clients___dma5___bit 5 | ||
| 496 | #define reg_marb_bp_r_brk_clients___dma6___lsb 6 | ||
| 497 | #define reg_marb_bp_r_brk_clients___dma6___width 1 | ||
| 498 | #define reg_marb_bp_r_brk_clients___dma6___bit 6 | ||
| 499 | #define reg_marb_bp_r_brk_clients___dma7___lsb 7 | ||
| 500 | #define reg_marb_bp_r_brk_clients___dma7___width 1 | ||
| 501 | #define reg_marb_bp_r_brk_clients___dma7___bit 7 | ||
| 502 | #define reg_marb_bp_r_brk_clients___dma8___lsb 8 | ||
| 503 | #define reg_marb_bp_r_brk_clients___dma8___width 1 | ||
| 504 | #define reg_marb_bp_r_brk_clients___dma8___bit 8 | ||
| 505 | #define reg_marb_bp_r_brk_clients___dma9___lsb 9 | ||
| 506 | #define reg_marb_bp_r_brk_clients___dma9___width 1 | ||
| 507 | #define reg_marb_bp_r_brk_clients___dma9___bit 9 | ||
| 508 | #define reg_marb_bp_r_brk_clients___cpui___lsb 10 | ||
| 509 | #define reg_marb_bp_r_brk_clients___cpui___width 1 | ||
| 510 | #define reg_marb_bp_r_brk_clients___cpui___bit 10 | ||
| 511 | #define reg_marb_bp_r_brk_clients___cpud___lsb 11 | ||
| 512 | #define reg_marb_bp_r_brk_clients___cpud___width 1 | ||
| 513 | #define reg_marb_bp_r_brk_clients___cpud___bit 11 | ||
| 514 | #define reg_marb_bp_r_brk_clients___iop___lsb 12 | ||
| 515 | #define reg_marb_bp_r_brk_clients___iop___width 1 | ||
| 516 | #define reg_marb_bp_r_brk_clients___iop___bit 12 | ||
| 517 | #define reg_marb_bp_r_brk_clients___slave___lsb 13 | ||
| 518 | #define reg_marb_bp_r_brk_clients___slave___width 1 | ||
| 519 | #define reg_marb_bp_r_brk_clients___slave___bit 13 | ||
| 520 | #define reg_marb_bp_r_brk_clients_offset 28 | ||
| 521 | |||
| 522 | /* Register r_brk_first_client, scope marb_bp, type r */ | ||
| 523 | #define reg_marb_bp_r_brk_first_client___dma0___lsb 0 | ||
| 524 | #define reg_marb_bp_r_brk_first_client___dma0___width 1 | ||
| 525 | #define reg_marb_bp_r_brk_first_client___dma0___bit 0 | ||
| 526 | #define reg_marb_bp_r_brk_first_client___dma1___lsb 1 | ||
| 527 | #define reg_marb_bp_r_brk_first_client___dma1___width 1 | ||
| 528 | #define reg_marb_bp_r_brk_first_client___dma1___bit 1 | ||
| 529 | #define reg_marb_bp_r_brk_first_client___dma2___lsb 2 | ||
| 530 | #define reg_marb_bp_r_brk_first_client___dma2___width 1 | ||
| 531 | #define reg_marb_bp_r_brk_first_client___dma2___bit 2 | ||
| 532 | #define reg_marb_bp_r_brk_first_client___dma3___lsb 3 | ||
| 533 | #define reg_marb_bp_r_brk_first_client___dma3___width 1 | ||
| 534 | #define reg_marb_bp_r_brk_first_client___dma3___bit 3 | ||
| 535 | #define reg_marb_bp_r_brk_first_client___dma4___lsb 4 | ||
| 536 | #define reg_marb_bp_r_brk_first_client___dma4___width 1 | ||
| 537 | #define reg_marb_bp_r_brk_first_client___dma4___bit 4 | ||
| 538 | #define reg_marb_bp_r_brk_first_client___dma5___lsb 5 | ||
| 539 | #define reg_marb_bp_r_brk_first_client___dma5___width 1 | ||
| 540 | #define reg_marb_bp_r_brk_first_client___dma5___bit 5 | ||
| 541 | #define reg_marb_bp_r_brk_first_client___dma6___lsb 6 | ||
| 542 | #define reg_marb_bp_r_brk_first_client___dma6___width 1 | ||
| 543 | #define reg_marb_bp_r_brk_first_client___dma6___bit 6 | ||
| 544 | #define reg_marb_bp_r_brk_first_client___dma7___lsb 7 | ||
| 545 | #define reg_marb_bp_r_brk_first_client___dma7___width 1 | ||
| 546 | #define reg_marb_bp_r_brk_first_client___dma7___bit 7 | ||
| 547 | #define reg_marb_bp_r_brk_first_client___dma8___lsb 8 | ||
| 548 | #define reg_marb_bp_r_brk_first_client___dma8___width 1 | ||
| 549 | #define reg_marb_bp_r_brk_first_client___dma8___bit 8 | ||
| 550 | #define reg_marb_bp_r_brk_first_client___dma9___lsb 9 | ||
| 551 | #define reg_marb_bp_r_brk_first_client___dma9___width 1 | ||
| 552 | #define reg_marb_bp_r_brk_first_client___dma9___bit 9 | ||
| 553 | #define reg_marb_bp_r_brk_first_client___cpui___lsb 10 | ||
| 554 | #define reg_marb_bp_r_brk_first_client___cpui___width 1 | ||
| 555 | #define reg_marb_bp_r_brk_first_client___cpui___bit 10 | ||
| 556 | #define reg_marb_bp_r_brk_first_client___cpud___lsb 11 | ||
| 557 | #define reg_marb_bp_r_brk_first_client___cpud___width 1 | ||
| 558 | #define reg_marb_bp_r_brk_first_client___cpud___bit 11 | ||
| 559 | #define reg_marb_bp_r_brk_first_client___iop___lsb 12 | ||
| 560 | #define reg_marb_bp_r_brk_first_client___iop___width 1 | ||
| 561 | #define reg_marb_bp_r_brk_first_client___iop___bit 12 | ||
| 562 | #define reg_marb_bp_r_brk_first_client___slave___lsb 13 | ||
| 563 | #define reg_marb_bp_r_brk_first_client___slave___width 1 | ||
| 564 | #define reg_marb_bp_r_brk_first_client___slave___bit 13 | ||
| 565 | #define reg_marb_bp_r_brk_first_client_offset 32 | ||
| 566 | |||
| 567 | /* Register r_brk_size, scope marb_bp, type r */ | ||
| 568 | #define reg_marb_bp_r_brk_size_offset 36 | ||
| 569 | |||
| 570 | /* Register rw_ack, scope marb_bp, type rw */ | ||
| 571 | #define reg_marb_bp_rw_ack_offset 40 | ||
| 572 | |||
| 573 | |||
| 574 | /* Constants */ | ||
| 575 | #define regk_marb_bp_no 0x00000000 | ||
| 576 | #define regk_marb_bp_rw_op_default 0x00000000 | ||
| 577 | #define regk_marb_bp_rw_options_default 0x00000000 | ||
| 578 | #define regk_marb_bp_yes 0x00000001 | ||
| 579 | #endif /* __marb_bp_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h deleted file mode 100644 index 505b7a16d878..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h +++ /dev/null | |||
| @@ -1,212 +0,0 @@ | |||
| 1 | #ifndef __mmu_defs_asm_h | ||
| 2 | #define __mmu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/mmu/doc/mmu_regs.r | ||
| 7 | * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp | ||
| 8 | * last modfied: Mon Apr 11 17:03:20 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r | ||
| 11 | * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_mm_cfg, scope mmu, type rw */ | ||
| 57 | #define reg_mmu_rw_mm_cfg___seg_0___lsb 0 | ||
| 58 | #define reg_mmu_rw_mm_cfg___seg_0___width 1 | ||
| 59 | #define reg_mmu_rw_mm_cfg___seg_0___bit 0 | ||
| 60 | #define reg_mmu_rw_mm_cfg___seg_1___lsb 1 | ||
| 61 | #define reg_mmu_rw_mm_cfg___seg_1___width 1 | ||
| 62 | #define reg_mmu_rw_mm_cfg___seg_1___bit 1 | ||
| 63 | #define reg_mmu_rw_mm_cfg___seg_2___lsb 2 | ||
| 64 | #define reg_mmu_rw_mm_cfg___seg_2___width 1 | ||
| 65 | #define reg_mmu_rw_mm_cfg___seg_2___bit 2 | ||
| 66 | #define reg_mmu_rw_mm_cfg___seg_3___lsb 3 | ||
| 67 | #define reg_mmu_rw_mm_cfg___seg_3___width 1 | ||
| 68 | #define reg_mmu_rw_mm_cfg___seg_3___bit 3 | ||
| 69 | #define reg_mmu_rw_mm_cfg___seg_4___lsb 4 | ||
| 70 | #define reg_mmu_rw_mm_cfg___seg_4___width 1 | ||
| 71 | #define reg_mmu_rw_mm_cfg___seg_4___bit 4 | ||
| 72 | #define reg_mmu_rw_mm_cfg___seg_5___lsb 5 | ||
| 73 | #define reg_mmu_rw_mm_cfg___seg_5___width 1 | ||
| 74 | #define reg_mmu_rw_mm_cfg___seg_5___bit 5 | ||
| 75 | #define reg_mmu_rw_mm_cfg___seg_6___lsb 6 | ||
| 76 | #define reg_mmu_rw_mm_cfg___seg_6___width 1 | ||
| 77 | #define reg_mmu_rw_mm_cfg___seg_6___bit 6 | ||
| 78 | #define reg_mmu_rw_mm_cfg___seg_7___lsb 7 | ||
| 79 | #define reg_mmu_rw_mm_cfg___seg_7___width 1 | ||
| 80 | #define reg_mmu_rw_mm_cfg___seg_7___bit 7 | ||
| 81 | #define reg_mmu_rw_mm_cfg___seg_8___lsb 8 | ||
| 82 | #define reg_mmu_rw_mm_cfg___seg_8___width 1 | ||
| 83 | #define reg_mmu_rw_mm_cfg___seg_8___bit 8 | ||
| 84 | #define reg_mmu_rw_mm_cfg___seg_9___lsb 9 | ||
| 85 | #define reg_mmu_rw_mm_cfg___seg_9___width 1 | ||
| 86 | #define reg_mmu_rw_mm_cfg___seg_9___bit 9 | ||
| 87 | #define reg_mmu_rw_mm_cfg___seg_a___lsb 10 | ||
| 88 | #define reg_mmu_rw_mm_cfg___seg_a___width 1 | ||
| 89 | #define reg_mmu_rw_mm_cfg___seg_a___bit 10 | ||
| 90 | #define reg_mmu_rw_mm_cfg___seg_b___lsb 11 | ||
| 91 | #define reg_mmu_rw_mm_cfg___seg_b___width 1 | ||
| 92 | #define reg_mmu_rw_mm_cfg___seg_b___bit 11 | ||
| 93 | #define reg_mmu_rw_mm_cfg___seg_c___lsb 12 | ||
| 94 | #define reg_mmu_rw_mm_cfg___seg_c___width 1 | ||
| 95 | #define reg_mmu_rw_mm_cfg___seg_c___bit 12 | ||
| 96 | #define reg_mmu_rw_mm_cfg___seg_d___lsb 13 | ||
| 97 | #define reg_mmu_rw_mm_cfg___seg_d___width 1 | ||
| 98 | #define reg_mmu_rw_mm_cfg___seg_d___bit 13 | ||
| 99 | #define reg_mmu_rw_mm_cfg___seg_e___lsb 14 | ||
| 100 | #define reg_mmu_rw_mm_cfg___seg_e___width 1 | ||
| 101 | #define reg_mmu_rw_mm_cfg___seg_e___bit 14 | ||
| 102 | #define reg_mmu_rw_mm_cfg___seg_f___lsb 15 | ||
| 103 | #define reg_mmu_rw_mm_cfg___seg_f___width 1 | ||
| 104 | #define reg_mmu_rw_mm_cfg___seg_f___bit 15 | ||
| 105 | #define reg_mmu_rw_mm_cfg___inv___lsb 16 | ||
| 106 | #define reg_mmu_rw_mm_cfg___inv___width 1 | ||
| 107 | #define reg_mmu_rw_mm_cfg___inv___bit 16 | ||
| 108 | #define reg_mmu_rw_mm_cfg___ex___lsb 17 | ||
| 109 | #define reg_mmu_rw_mm_cfg___ex___width 1 | ||
| 110 | #define reg_mmu_rw_mm_cfg___ex___bit 17 | ||
| 111 | #define reg_mmu_rw_mm_cfg___acc___lsb 18 | ||
| 112 | #define reg_mmu_rw_mm_cfg___acc___width 1 | ||
| 113 | #define reg_mmu_rw_mm_cfg___acc___bit 18 | ||
| 114 | #define reg_mmu_rw_mm_cfg___we___lsb 19 | ||
| 115 | #define reg_mmu_rw_mm_cfg___we___width 1 | ||
| 116 | #define reg_mmu_rw_mm_cfg___we___bit 19 | ||
| 117 | #define reg_mmu_rw_mm_cfg_offset 0 | ||
| 118 | |||
| 119 | /* Register rw_mm_kbase_lo, scope mmu, type rw */ | ||
| 120 | #define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 | ||
| 121 | #define reg_mmu_rw_mm_kbase_lo___base_0___width 4 | ||
| 122 | #define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 | ||
| 123 | #define reg_mmu_rw_mm_kbase_lo___base_1___width 4 | ||
| 124 | #define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 | ||
| 125 | #define reg_mmu_rw_mm_kbase_lo___base_2___width 4 | ||
| 126 | #define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 | ||
| 127 | #define reg_mmu_rw_mm_kbase_lo___base_3___width 4 | ||
| 128 | #define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 | ||
| 129 | #define reg_mmu_rw_mm_kbase_lo___base_4___width 4 | ||
| 130 | #define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 | ||
| 131 | #define reg_mmu_rw_mm_kbase_lo___base_5___width 4 | ||
| 132 | #define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 | ||
| 133 | #define reg_mmu_rw_mm_kbase_lo___base_6___width 4 | ||
| 134 | #define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 | ||
| 135 | #define reg_mmu_rw_mm_kbase_lo___base_7___width 4 | ||
| 136 | #define reg_mmu_rw_mm_kbase_lo_offset 4 | ||
| 137 | |||
| 138 | /* Register rw_mm_kbase_hi, scope mmu, type rw */ | ||
| 139 | #define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 | ||
| 140 | #define reg_mmu_rw_mm_kbase_hi___base_8___width 4 | ||
| 141 | #define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 | ||
| 142 | #define reg_mmu_rw_mm_kbase_hi___base_9___width 4 | ||
| 143 | #define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 | ||
| 144 | #define reg_mmu_rw_mm_kbase_hi___base_a___width 4 | ||
| 145 | #define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 | ||
| 146 | #define reg_mmu_rw_mm_kbase_hi___base_b___width 4 | ||
| 147 | #define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 | ||
| 148 | #define reg_mmu_rw_mm_kbase_hi___base_c___width 4 | ||
| 149 | #define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 | ||
| 150 | #define reg_mmu_rw_mm_kbase_hi___base_d___width 4 | ||
| 151 | #define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 | ||
| 152 | #define reg_mmu_rw_mm_kbase_hi___base_e___width 4 | ||
| 153 | #define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 | ||
| 154 | #define reg_mmu_rw_mm_kbase_hi___base_f___width 4 | ||
| 155 | #define reg_mmu_rw_mm_kbase_hi_offset 8 | ||
| 156 | |||
| 157 | /* Register r_mm_cause, scope mmu, type r */ | ||
| 158 | #define reg_mmu_r_mm_cause___pid___lsb 0 | ||
| 159 | #define reg_mmu_r_mm_cause___pid___width 8 | ||
| 160 | #define reg_mmu_r_mm_cause___op___lsb 8 | ||
| 161 | #define reg_mmu_r_mm_cause___op___width 2 | ||
| 162 | #define reg_mmu_r_mm_cause___vpn___lsb 13 | ||
| 163 | #define reg_mmu_r_mm_cause___vpn___width 19 | ||
| 164 | #define reg_mmu_r_mm_cause_offset 12 | ||
| 165 | |||
| 166 | /* Register rw_mm_tlb_sel, scope mmu, type rw */ | ||
| 167 | #define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 | ||
| 168 | #define reg_mmu_rw_mm_tlb_sel___idx___width 4 | ||
| 169 | #define reg_mmu_rw_mm_tlb_sel___set___lsb 4 | ||
| 170 | #define reg_mmu_rw_mm_tlb_sel___set___width 2 | ||
| 171 | #define reg_mmu_rw_mm_tlb_sel_offset 16 | ||
| 172 | |||
| 173 | /* Register rw_mm_tlb_lo, scope mmu, type rw */ | ||
| 174 | #define reg_mmu_rw_mm_tlb_lo___x___lsb 0 | ||
| 175 | #define reg_mmu_rw_mm_tlb_lo___x___width 1 | ||
| 176 | #define reg_mmu_rw_mm_tlb_lo___x___bit 0 | ||
| 177 | #define reg_mmu_rw_mm_tlb_lo___w___lsb 1 | ||
| 178 | #define reg_mmu_rw_mm_tlb_lo___w___width 1 | ||
| 179 | #define reg_mmu_rw_mm_tlb_lo___w___bit 1 | ||
| 180 | #define reg_mmu_rw_mm_tlb_lo___k___lsb 2 | ||
| 181 | #define reg_mmu_rw_mm_tlb_lo___k___width 1 | ||
| 182 | #define reg_mmu_rw_mm_tlb_lo___k___bit 2 | ||
| 183 | #define reg_mmu_rw_mm_tlb_lo___v___lsb 3 | ||
| 184 | #define reg_mmu_rw_mm_tlb_lo___v___width 1 | ||
| 185 | #define reg_mmu_rw_mm_tlb_lo___v___bit 3 | ||
| 186 | #define reg_mmu_rw_mm_tlb_lo___g___lsb 4 | ||
| 187 | #define reg_mmu_rw_mm_tlb_lo___g___width 1 | ||
| 188 | #define reg_mmu_rw_mm_tlb_lo___g___bit 4 | ||
| 189 | #define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 | ||
| 190 | #define reg_mmu_rw_mm_tlb_lo___pfn___width 19 | ||
| 191 | #define reg_mmu_rw_mm_tlb_lo_offset 20 | ||
| 192 | |||
| 193 | /* Register rw_mm_tlb_hi, scope mmu, type rw */ | ||
| 194 | #define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 | ||
| 195 | #define reg_mmu_rw_mm_tlb_hi___pid___width 8 | ||
| 196 | #define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 | ||
| 197 | #define reg_mmu_rw_mm_tlb_hi___vpn___width 19 | ||
| 198 | #define reg_mmu_rw_mm_tlb_hi_offset 24 | ||
| 199 | |||
| 200 | |||
| 201 | /* Constants */ | ||
| 202 | #define regk_mmu_execute 0x00000000 | ||
| 203 | #define regk_mmu_flush 0x00000003 | ||
| 204 | #define regk_mmu_linear 0x00000001 | ||
| 205 | #define regk_mmu_no 0x00000000 | ||
| 206 | #define regk_mmu_off 0x00000000 | ||
| 207 | #define regk_mmu_on 0x00000001 | ||
| 208 | #define regk_mmu_page 0x00000000 | ||
| 209 | #define regk_mmu_read 0x00000001 | ||
| 210 | #define regk_mmu_write 0x00000002 | ||
| 211 | #define regk_mmu_yes 0x00000001 | ||
| 212 | #endif /* __mmu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h deleted file mode 100644 index 339500bf3bc0..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | #define RW_MM_CFG 0 | ||
| 2 | #define RW_MM_KBASE_LO 1 | ||
| 3 | #define RW_MM_KBASE_HI 2 | ||
| 4 | #define R_MM_CAUSE 3 | ||
| 5 | #define RW_MM_TLB_SEL 4 | ||
| 6 | #define RW_MM_TLB_LO 5 | ||
| 7 | #define RW_MM_TLB_HI 6 | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 13c725e4c774..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h +++ /dev/null | |||
| @@ -1,632 +0,0 @@ | |||
| 1 | #ifndef __pinmux_defs_asm_h | ||
| 2 | #define __pinmux_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 7 | * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:11 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 11 | * id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_pa, scope pinmux, type rw */ | ||
| 57 | #define reg_pinmux_rw_pa___pa0___lsb 0 | ||
| 58 | #define reg_pinmux_rw_pa___pa0___width 1 | ||
| 59 | #define reg_pinmux_rw_pa___pa0___bit 0 | ||
| 60 | #define reg_pinmux_rw_pa___pa1___lsb 1 | ||
| 61 | #define reg_pinmux_rw_pa___pa1___width 1 | ||
| 62 | #define reg_pinmux_rw_pa___pa1___bit 1 | ||
| 63 | #define reg_pinmux_rw_pa___pa2___lsb 2 | ||
| 64 | #define reg_pinmux_rw_pa___pa2___width 1 | ||
| 65 | #define reg_pinmux_rw_pa___pa2___bit 2 | ||
| 66 | #define reg_pinmux_rw_pa___pa3___lsb 3 | ||
| 67 | #define reg_pinmux_rw_pa___pa3___width 1 | ||
| 68 | #define reg_pinmux_rw_pa___pa3___bit 3 | ||
| 69 | #define reg_pinmux_rw_pa___pa4___lsb 4 | ||
| 70 | #define reg_pinmux_rw_pa___pa4___width 1 | ||
| 71 | #define reg_pinmux_rw_pa___pa4___bit 4 | ||
| 72 | #define reg_pinmux_rw_pa___pa5___lsb 5 | ||
| 73 | #define reg_pinmux_rw_pa___pa5___width 1 | ||
| 74 | #define reg_pinmux_rw_pa___pa5___bit 5 | ||
| 75 | #define reg_pinmux_rw_pa___pa6___lsb 6 | ||
| 76 | #define reg_pinmux_rw_pa___pa6___width 1 | ||
| 77 | #define reg_pinmux_rw_pa___pa6___bit 6 | ||
| 78 | #define reg_pinmux_rw_pa___pa7___lsb 7 | ||
| 79 | #define reg_pinmux_rw_pa___pa7___width 1 | ||
| 80 | #define reg_pinmux_rw_pa___pa7___bit 7 | ||
| 81 | #define reg_pinmux_rw_pa___csp2_n___lsb 8 | ||
| 82 | #define reg_pinmux_rw_pa___csp2_n___width 1 | ||
| 83 | #define reg_pinmux_rw_pa___csp2_n___bit 8 | ||
| 84 | #define reg_pinmux_rw_pa___csp3_n___lsb 9 | ||
| 85 | #define reg_pinmux_rw_pa___csp3_n___width 1 | ||
| 86 | #define reg_pinmux_rw_pa___csp3_n___bit 9 | ||
| 87 | #define reg_pinmux_rw_pa___csp5_n___lsb 10 | ||
| 88 | #define reg_pinmux_rw_pa___csp5_n___width 1 | ||
| 89 | #define reg_pinmux_rw_pa___csp5_n___bit 10 | ||
| 90 | #define reg_pinmux_rw_pa___csp6_n___lsb 11 | ||
| 91 | #define reg_pinmux_rw_pa___csp6_n___width 1 | ||
| 92 | #define reg_pinmux_rw_pa___csp6_n___bit 11 | ||
| 93 | #define reg_pinmux_rw_pa___hsh4___lsb 12 | ||
| 94 | #define reg_pinmux_rw_pa___hsh4___width 1 | ||
| 95 | #define reg_pinmux_rw_pa___hsh4___bit 12 | ||
| 96 | #define reg_pinmux_rw_pa___hsh5___lsb 13 | ||
| 97 | #define reg_pinmux_rw_pa___hsh5___width 1 | ||
| 98 | #define reg_pinmux_rw_pa___hsh5___bit 13 | ||
| 99 | #define reg_pinmux_rw_pa___hsh6___lsb 14 | ||
| 100 | #define reg_pinmux_rw_pa___hsh6___width 1 | ||
| 101 | #define reg_pinmux_rw_pa___hsh6___bit 14 | ||
| 102 | #define reg_pinmux_rw_pa___hsh7___lsb 15 | ||
| 103 | #define reg_pinmux_rw_pa___hsh7___width 1 | ||
| 104 | #define reg_pinmux_rw_pa___hsh7___bit 15 | ||
| 105 | #define reg_pinmux_rw_pa_offset 0 | ||
| 106 | |||
| 107 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 108 | #define reg_pinmux_rw_hwprot___ser1___lsb 0 | ||
| 109 | #define reg_pinmux_rw_hwprot___ser1___width 1 | ||
| 110 | #define reg_pinmux_rw_hwprot___ser1___bit 0 | ||
| 111 | #define reg_pinmux_rw_hwprot___ser2___lsb 1 | ||
| 112 | #define reg_pinmux_rw_hwprot___ser2___width 1 | ||
| 113 | #define reg_pinmux_rw_hwprot___ser2___bit 1 | ||
| 114 | #define reg_pinmux_rw_hwprot___ser3___lsb 2 | ||
| 115 | #define reg_pinmux_rw_hwprot___ser3___width 1 | ||
| 116 | #define reg_pinmux_rw_hwprot___ser3___bit 2 | ||
| 117 | #define reg_pinmux_rw_hwprot___sser0___lsb 3 | ||
| 118 | #define reg_pinmux_rw_hwprot___sser0___width 1 | ||
| 119 | #define reg_pinmux_rw_hwprot___sser0___bit 3 | ||
| 120 | #define reg_pinmux_rw_hwprot___sser1___lsb 4 | ||
| 121 | #define reg_pinmux_rw_hwprot___sser1___width 1 | ||
| 122 | #define reg_pinmux_rw_hwprot___sser1___bit 4 | ||
| 123 | #define reg_pinmux_rw_hwprot___ata0___lsb 5 | ||
| 124 | #define reg_pinmux_rw_hwprot___ata0___width 1 | ||
| 125 | #define reg_pinmux_rw_hwprot___ata0___bit 5 | ||
| 126 | #define reg_pinmux_rw_hwprot___ata1___lsb 6 | ||
| 127 | #define reg_pinmux_rw_hwprot___ata1___width 1 | ||
| 128 | #define reg_pinmux_rw_hwprot___ata1___bit 6 | ||
| 129 | #define reg_pinmux_rw_hwprot___ata2___lsb 7 | ||
| 130 | #define reg_pinmux_rw_hwprot___ata2___width 1 | ||
| 131 | #define reg_pinmux_rw_hwprot___ata2___bit 7 | ||
| 132 | #define reg_pinmux_rw_hwprot___ata3___lsb 8 | ||
| 133 | #define reg_pinmux_rw_hwprot___ata3___width 1 | ||
| 134 | #define reg_pinmux_rw_hwprot___ata3___bit 8 | ||
| 135 | #define reg_pinmux_rw_hwprot___ata___lsb 9 | ||
| 136 | #define reg_pinmux_rw_hwprot___ata___width 1 | ||
| 137 | #define reg_pinmux_rw_hwprot___ata___bit 9 | ||
| 138 | #define reg_pinmux_rw_hwprot___eth1___lsb 10 | ||
| 139 | #define reg_pinmux_rw_hwprot___eth1___width 1 | ||
| 140 | #define reg_pinmux_rw_hwprot___eth1___bit 10 | ||
| 141 | #define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 | ||
| 142 | #define reg_pinmux_rw_hwprot___eth1_mgm___width 1 | ||
| 143 | #define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 | ||
| 144 | #define reg_pinmux_rw_hwprot___timer___lsb 12 | ||
| 145 | #define reg_pinmux_rw_hwprot___timer___width 1 | ||
| 146 | #define reg_pinmux_rw_hwprot___timer___bit 12 | ||
| 147 | #define reg_pinmux_rw_hwprot___p21___lsb 13 | ||
| 148 | #define reg_pinmux_rw_hwprot___p21___width 1 | ||
| 149 | #define reg_pinmux_rw_hwprot___p21___bit 13 | ||
| 150 | #define reg_pinmux_rw_hwprot_offset 4 | ||
| 151 | |||
| 152 | /* Register rw_pb_gio, scope pinmux, type rw */ | ||
| 153 | #define reg_pinmux_rw_pb_gio___pb0___lsb 0 | ||
| 154 | #define reg_pinmux_rw_pb_gio___pb0___width 1 | ||
| 155 | #define reg_pinmux_rw_pb_gio___pb0___bit 0 | ||
| 156 | #define reg_pinmux_rw_pb_gio___pb1___lsb 1 | ||
| 157 | #define reg_pinmux_rw_pb_gio___pb1___width 1 | ||
| 158 | #define reg_pinmux_rw_pb_gio___pb1___bit 1 | ||
| 159 | #define reg_pinmux_rw_pb_gio___pb2___lsb 2 | ||
| 160 | #define reg_pinmux_rw_pb_gio___pb2___width 1 | ||
| 161 | #define reg_pinmux_rw_pb_gio___pb2___bit 2 | ||
| 162 | #define reg_pinmux_rw_pb_gio___pb3___lsb 3 | ||
| 163 | #define reg_pinmux_rw_pb_gio___pb3___width 1 | ||
| 164 | #define reg_pinmux_rw_pb_gio___pb3___bit 3 | ||
| 165 | #define reg_pinmux_rw_pb_gio___pb4___lsb 4 | ||
| 166 | #define reg_pinmux_rw_pb_gio___pb4___width 1 | ||
| 167 | #define reg_pinmux_rw_pb_gio___pb4___bit 4 | ||
| 168 | #define reg_pinmux_rw_pb_gio___pb5___lsb 5 | ||
| 169 | #define reg_pinmux_rw_pb_gio___pb5___width 1 | ||
| 170 | #define reg_pinmux_rw_pb_gio___pb5___bit 5 | ||
| 171 | #define reg_pinmux_rw_pb_gio___pb6___lsb 6 | ||
| 172 | #define reg_pinmux_rw_pb_gio___pb6___width 1 | ||
| 173 | #define reg_pinmux_rw_pb_gio___pb6___bit 6 | ||
| 174 | #define reg_pinmux_rw_pb_gio___pb7___lsb 7 | ||
| 175 | #define reg_pinmux_rw_pb_gio___pb7___width 1 | ||
| 176 | #define reg_pinmux_rw_pb_gio___pb7___bit 7 | ||
| 177 | #define reg_pinmux_rw_pb_gio___pb8___lsb 8 | ||
| 178 | #define reg_pinmux_rw_pb_gio___pb8___width 1 | ||
| 179 | #define reg_pinmux_rw_pb_gio___pb8___bit 8 | ||
| 180 | #define reg_pinmux_rw_pb_gio___pb9___lsb 9 | ||
| 181 | #define reg_pinmux_rw_pb_gio___pb9___width 1 | ||
| 182 | #define reg_pinmux_rw_pb_gio___pb9___bit 9 | ||
| 183 | #define reg_pinmux_rw_pb_gio___pb10___lsb 10 | ||
| 184 | #define reg_pinmux_rw_pb_gio___pb10___width 1 | ||
| 185 | #define reg_pinmux_rw_pb_gio___pb10___bit 10 | ||
| 186 | #define reg_pinmux_rw_pb_gio___pb11___lsb 11 | ||
| 187 | #define reg_pinmux_rw_pb_gio___pb11___width 1 | ||
| 188 | #define reg_pinmux_rw_pb_gio___pb11___bit 11 | ||
| 189 | #define reg_pinmux_rw_pb_gio___pb12___lsb 12 | ||
| 190 | #define reg_pinmux_rw_pb_gio___pb12___width 1 | ||
| 191 | #define reg_pinmux_rw_pb_gio___pb12___bit 12 | ||
| 192 | #define reg_pinmux_rw_pb_gio___pb13___lsb 13 | ||
| 193 | #define reg_pinmux_rw_pb_gio___pb13___width 1 | ||
| 194 | #define reg_pinmux_rw_pb_gio___pb13___bit 13 | ||
| 195 | #define reg_pinmux_rw_pb_gio___pb14___lsb 14 | ||
| 196 | #define reg_pinmux_rw_pb_gio___pb14___width 1 | ||
| 197 | #define reg_pinmux_rw_pb_gio___pb14___bit 14 | ||
| 198 | #define reg_pinmux_rw_pb_gio___pb15___lsb 15 | ||
| 199 | #define reg_pinmux_rw_pb_gio___pb15___width 1 | ||
| 200 | #define reg_pinmux_rw_pb_gio___pb15___bit 15 | ||
| 201 | #define reg_pinmux_rw_pb_gio___pb16___lsb 16 | ||
| 202 | #define reg_pinmux_rw_pb_gio___pb16___width 1 | ||
| 203 | #define reg_pinmux_rw_pb_gio___pb16___bit 16 | ||
| 204 | #define reg_pinmux_rw_pb_gio___pb17___lsb 17 | ||
| 205 | #define reg_pinmux_rw_pb_gio___pb17___width 1 | ||
| 206 | #define reg_pinmux_rw_pb_gio___pb17___bit 17 | ||
| 207 | #define reg_pinmux_rw_pb_gio_offset 8 | ||
| 208 | |||
| 209 | /* Register rw_pb_iop, scope pinmux, type rw */ | ||
| 210 | #define reg_pinmux_rw_pb_iop___pb0___lsb 0 | ||
| 211 | #define reg_pinmux_rw_pb_iop___pb0___width 1 | ||
| 212 | #define reg_pinmux_rw_pb_iop___pb0___bit 0 | ||
| 213 | #define reg_pinmux_rw_pb_iop___pb1___lsb 1 | ||
| 214 | #define reg_pinmux_rw_pb_iop___pb1___width 1 | ||
| 215 | #define reg_pinmux_rw_pb_iop___pb1___bit 1 | ||
| 216 | #define reg_pinmux_rw_pb_iop___pb2___lsb 2 | ||
| 217 | #define reg_pinmux_rw_pb_iop___pb2___width 1 | ||
| 218 | #define reg_pinmux_rw_pb_iop___pb2___bit 2 | ||
| 219 | #define reg_pinmux_rw_pb_iop___pb3___lsb 3 | ||
| 220 | #define reg_pinmux_rw_pb_iop___pb3___width 1 | ||
| 221 | #define reg_pinmux_rw_pb_iop___pb3___bit 3 | ||
| 222 | #define reg_pinmux_rw_pb_iop___pb4___lsb 4 | ||
| 223 | #define reg_pinmux_rw_pb_iop___pb4___width 1 | ||
| 224 | #define reg_pinmux_rw_pb_iop___pb4___bit 4 | ||
| 225 | #define reg_pinmux_rw_pb_iop___pb5___lsb 5 | ||
| 226 | #define reg_pinmux_rw_pb_iop___pb5___width 1 | ||
| 227 | #define reg_pinmux_rw_pb_iop___pb5___bit 5 | ||
| 228 | #define reg_pinmux_rw_pb_iop___pb6___lsb 6 | ||
| 229 | #define reg_pinmux_rw_pb_iop___pb6___width 1 | ||
| 230 | #define reg_pinmux_rw_pb_iop___pb6___bit 6 | ||
| 231 | #define reg_pinmux_rw_pb_iop___pb7___lsb 7 | ||
| 232 | #define reg_pinmux_rw_pb_iop___pb7___width 1 | ||
| 233 | #define reg_pinmux_rw_pb_iop___pb7___bit 7 | ||
| 234 | #define reg_pinmux_rw_pb_iop___pb8___lsb 8 | ||
| 235 | #define reg_pinmux_rw_pb_iop___pb8___width 1 | ||
| 236 | #define reg_pinmux_rw_pb_iop___pb8___bit 8 | ||
| 237 | #define reg_pinmux_rw_pb_iop___pb9___lsb 9 | ||
| 238 | #define reg_pinmux_rw_pb_iop___pb9___width 1 | ||
| 239 | #define reg_pinmux_rw_pb_iop___pb9___bit 9 | ||
| 240 | #define reg_pinmux_rw_pb_iop___pb10___lsb 10 | ||
| 241 | #define reg_pinmux_rw_pb_iop___pb10___width 1 | ||
| 242 | #define reg_pinmux_rw_pb_iop___pb10___bit 10 | ||
| 243 | #define reg_pinmux_rw_pb_iop___pb11___lsb 11 | ||
| 244 | #define reg_pinmux_rw_pb_iop___pb11___width 1 | ||
| 245 | #define reg_pinmux_rw_pb_iop___pb11___bit 11 | ||
| 246 | #define reg_pinmux_rw_pb_iop___pb12___lsb 12 | ||
| 247 | #define reg_pinmux_rw_pb_iop___pb12___width 1 | ||
| 248 | #define reg_pinmux_rw_pb_iop___pb12___bit 12 | ||
| 249 | #define reg_pinmux_rw_pb_iop___pb13___lsb 13 | ||
| 250 | #define reg_pinmux_rw_pb_iop___pb13___width 1 | ||
| 251 | #define reg_pinmux_rw_pb_iop___pb13___bit 13 | ||
| 252 | #define reg_pinmux_rw_pb_iop___pb14___lsb 14 | ||
| 253 | #define reg_pinmux_rw_pb_iop___pb14___width 1 | ||
| 254 | #define reg_pinmux_rw_pb_iop___pb14___bit 14 | ||
| 255 | #define reg_pinmux_rw_pb_iop___pb15___lsb 15 | ||
| 256 | #define reg_pinmux_rw_pb_iop___pb15___width 1 | ||
| 257 | #define reg_pinmux_rw_pb_iop___pb15___bit 15 | ||
| 258 | #define reg_pinmux_rw_pb_iop___pb16___lsb 16 | ||
| 259 | #define reg_pinmux_rw_pb_iop___pb16___width 1 | ||
| 260 | #define reg_pinmux_rw_pb_iop___pb16___bit 16 | ||
| 261 | #define reg_pinmux_rw_pb_iop___pb17___lsb 17 | ||
| 262 | #define reg_pinmux_rw_pb_iop___pb17___width 1 | ||
| 263 | #define reg_pinmux_rw_pb_iop___pb17___bit 17 | ||
| 264 | #define reg_pinmux_rw_pb_iop_offset 12 | ||
| 265 | |||
| 266 | /* Register rw_pc_gio, scope pinmux, type rw */ | ||
| 267 | #define reg_pinmux_rw_pc_gio___pc0___lsb 0 | ||
| 268 | #define reg_pinmux_rw_pc_gio___pc0___width 1 | ||
| 269 | #define reg_pinmux_rw_pc_gio___pc0___bit 0 | ||
| 270 | #define reg_pinmux_rw_pc_gio___pc1___lsb 1 | ||
| 271 | #define reg_pinmux_rw_pc_gio___pc1___width 1 | ||
| 272 | #define reg_pinmux_rw_pc_gio___pc1___bit 1 | ||
| 273 | #define reg_pinmux_rw_pc_gio___pc2___lsb 2 | ||
| 274 | #define reg_pinmux_rw_pc_gio___pc2___width 1 | ||
| 275 | #define reg_pinmux_rw_pc_gio___pc2___bit 2 | ||
| 276 | #define reg_pinmux_rw_pc_gio___pc3___lsb 3 | ||
| 277 | #define reg_pinmux_rw_pc_gio___pc3___width 1 | ||
| 278 | #define reg_pinmux_rw_pc_gio___pc3___bit 3 | ||
| 279 | #define reg_pinmux_rw_pc_gio___pc4___lsb 4 | ||
| 280 | #define reg_pinmux_rw_pc_gio___pc4___width 1 | ||
| 281 | #define reg_pinmux_rw_pc_gio___pc4___bit 4 | ||
| 282 | #define reg_pinmux_rw_pc_gio___pc5___lsb 5 | ||
| 283 | #define reg_pinmux_rw_pc_gio___pc5___width 1 | ||
| 284 | #define reg_pinmux_rw_pc_gio___pc5___bit 5 | ||
| 285 | #define reg_pinmux_rw_pc_gio___pc6___lsb 6 | ||
| 286 | #define reg_pinmux_rw_pc_gio___pc6___width 1 | ||
| 287 | #define reg_pinmux_rw_pc_gio___pc6___bit 6 | ||
| 288 | #define reg_pinmux_rw_pc_gio___pc7___lsb 7 | ||
| 289 | #define reg_pinmux_rw_pc_gio___pc7___width 1 | ||
| 290 | #define reg_pinmux_rw_pc_gio___pc7___bit 7 | ||
| 291 | #define reg_pinmux_rw_pc_gio___pc8___lsb 8 | ||
| 292 | #define reg_pinmux_rw_pc_gio___pc8___width 1 | ||
| 293 | #define reg_pinmux_rw_pc_gio___pc8___bit 8 | ||
| 294 | #define reg_pinmux_rw_pc_gio___pc9___lsb 9 | ||
| 295 | #define reg_pinmux_rw_pc_gio___pc9___width 1 | ||
| 296 | #define reg_pinmux_rw_pc_gio___pc9___bit 9 | ||
| 297 | #define reg_pinmux_rw_pc_gio___pc10___lsb 10 | ||
| 298 | #define reg_pinmux_rw_pc_gio___pc10___width 1 | ||
| 299 | #define reg_pinmux_rw_pc_gio___pc10___bit 10 | ||
| 300 | #define reg_pinmux_rw_pc_gio___pc11___lsb 11 | ||
| 301 | #define reg_pinmux_rw_pc_gio___pc11___width 1 | ||
| 302 | #define reg_pinmux_rw_pc_gio___pc11___bit 11 | ||
| 303 | #define reg_pinmux_rw_pc_gio___pc12___lsb 12 | ||
| 304 | #define reg_pinmux_rw_pc_gio___pc12___width 1 | ||
| 305 | #define reg_pinmux_rw_pc_gio___pc12___bit 12 | ||
| 306 | #define reg_pinmux_rw_pc_gio___pc13___lsb 13 | ||
| 307 | #define reg_pinmux_rw_pc_gio___pc13___width 1 | ||
| 308 | #define reg_pinmux_rw_pc_gio___pc13___bit 13 | ||
| 309 | #define reg_pinmux_rw_pc_gio___pc14___lsb 14 | ||
| 310 | #define reg_pinmux_rw_pc_gio___pc14___width 1 | ||
| 311 | #define reg_pinmux_rw_pc_gio___pc14___bit 14 | ||
| 312 | #define reg_pinmux_rw_pc_gio___pc15___lsb 15 | ||
| 313 | #define reg_pinmux_rw_pc_gio___pc15___width 1 | ||
| 314 | #define reg_pinmux_rw_pc_gio___pc15___bit 15 | ||
| 315 | #define reg_pinmux_rw_pc_gio___pc16___lsb 16 | ||
| 316 | #define reg_pinmux_rw_pc_gio___pc16___width 1 | ||
| 317 | #define reg_pinmux_rw_pc_gio___pc16___bit 16 | ||
| 318 | #define reg_pinmux_rw_pc_gio___pc17___lsb 17 | ||
| 319 | #define reg_pinmux_rw_pc_gio___pc17___width 1 | ||
| 320 | #define reg_pinmux_rw_pc_gio___pc17___bit 17 | ||
| 321 | #define reg_pinmux_rw_pc_gio_offset 16 | ||
| 322 | |||
| 323 | /* Register rw_pc_iop, scope pinmux, type rw */ | ||
| 324 | #define reg_pinmux_rw_pc_iop___pc0___lsb 0 | ||
| 325 | #define reg_pinmux_rw_pc_iop___pc0___width 1 | ||
| 326 | #define reg_pinmux_rw_pc_iop___pc0___bit 0 | ||
| 327 | #define reg_pinmux_rw_pc_iop___pc1___lsb 1 | ||
| 328 | #define reg_pinmux_rw_pc_iop___pc1___width 1 | ||
| 329 | #define reg_pinmux_rw_pc_iop___pc1___bit 1 | ||
| 330 | #define reg_pinmux_rw_pc_iop___pc2___lsb 2 | ||
| 331 | #define reg_pinmux_rw_pc_iop___pc2___width 1 | ||
| 332 | #define reg_pinmux_rw_pc_iop___pc2___bit 2 | ||
| 333 | #define reg_pinmux_rw_pc_iop___pc3___lsb 3 | ||
| 334 | #define reg_pinmux_rw_pc_iop___pc3___width 1 | ||
| 335 | #define reg_pinmux_rw_pc_iop___pc3___bit 3 | ||
| 336 | #define reg_pinmux_rw_pc_iop___pc4___lsb 4 | ||
| 337 | #define reg_pinmux_rw_pc_iop___pc4___width 1 | ||
| 338 | #define reg_pinmux_rw_pc_iop___pc4___bit 4 | ||
| 339 | #define reg_pinmux_rw_pc_iop___pc5___lsb 5 | ||
| 340 | #define reg_pinmux_rw_pc_iop___pc5___width 1 | ||
| 341 | #define reg_pinmux_rw_pc_iop___pc5___bit 5 | ||
| 342 | #define reg_pinmux_rw_pc_iop___pc6___lsb 6 | ||
| 343 | #define reg_pinmux_rw_pc_iop___pc6___width 1 | ||
| 344 | #define reg_pinmux_rw_pc_iop___pc6___bit 6 | ||
| 345 | #define reg_pinmux_rw_pc_iop___pc7___lsb 7 | ||
| 346 | #define reg_pinmux_rw_pc_iop___pc7___width 1 | ||
| 347 | #define reg_pinmux_rw_pc_iop___pc7___bit 7 | ||
| 348 | #define reg_pinmux_rw_pc_iop___pc8___lsb 8 | ||
| 349 | #define reg_pinmux_rw_pc_iop___pc8___width 1 | ||
| 350 | #define reg_pinmux_rw_pc_iop___pc8___bit 8 | ||
| 351 | #define reg_pinmux_rw_pc_iop___pc9___lsb 9 | ||
| 352 | #define reg_pinmux_rw_pc_iop___pc9___width 1 | ||
| 353 | #define reg_pinmux_rw_pc_iop___pc9___bit 9 | ||
| 354 | #define reg_pinmux_rw_pc_iop___pc10___lsb 10 | ||
| 355 | #define reg_pinmux_rw_pc_iop___pc10___width 1 | ||
| 356 | #define reg_pinmux_rw_pc_iop___pc10___bit 10 | ||
| 357 | #define reg_pinmux_rw_pc_iop___pc11___lsb 11 | ||
| 358 | #define reg_pinmux_rw_pc_iop___pc11___width 1 | ||
| 359 | #define reg_pinmux_rw_pc_iop___pc11___bit 11 | ||
| 360 | #define reg_pinmux_rw_pc_iop___pc12___lsb 12 | ||
| 361 | #define reg_pinmux_rw_pc_iop___pc12___width 1 | ||
| 362 | #define reg_pinmux_rw_pc_iop___pc12___bit 12 | ||
| 363 | #define reg_pinmux_rw_pc_iop___pc13___lsb 13 | ||
| 364 | #define reg_pinmux_rw_pc_iop___pc13___width 1 | ||
| 365 | #define reg_pinmux_rw_pc_iop___pc13___bit 13 | ||
| 366 | #define reg_pinmux_rw_pc_iop___pc14___lsb 14 | ||
| 367 | #define reg_pinmux_rw_pc_iop___pc14___width 1 | ||
| 368 | #define reg_pinmux_rw_pc_iop___pc14___bit 14 | ||
| 369 | #define reg_pinmux_rw_pc_iop___pc15___lsb 15 | ||
| 370 | #define reg_pinmux_rw_pc_iop___pc15___width 1 | ||
| 371 | #define reg_pinmux_rw_pc_iop___pc15___bit 15 | ||
| 372 | #define reg_pinmux_rw_pc_iop___pc16___lsb 16 | ||
| 373 | #define reg_pinmux_rw_pc_iop___pc16___width 1 | ||
| 374 | #define reg_pinmux_rw_pc_iop___pc16___bit 16 | ||
| 375 | #define reg_pinmux_rw_pc_iop___pc17___lsb 17 | ||
| 376 | #define reg_pinmux_rw_pc_iop___pc17___width 1 | ||
| 377 | #define reg_pinmux_rw_pc_iop___pc17___bit 17 | ||
| 378 | #define reg_pinmux_rw_pc_iop_offset 20 | ||
| 379 | |||
| 380 | /* Register rw_pd_gio, scope pinmux, type rw */ | ||
| 381 | #define reg_pinmux_rw_pd_gio___pd0___lsb 0 | ||
| 382 | #define reg_pinmux_rw_pd_gio___pd0___width 1 | ||
| 383 | #define reg_pinmux_rw_pd_gio___pd0___bit 0 | ||
| 384 | #define reg_pinmux_rw_pd_gio___pd1___lsb 1 | ||
| 385 | #define reg_pinmux_rw_pd_gio___pd1___width 1 | ||
| 386 | #define reg_pinmux_rw_pd_gio___pd1___bit 1 | ||
| 387 | #define reg_pinmux_rw_pd_gio___pd2___lsb 2 | ||
| 388 | #define reg_pinmux_rw_pd_gio___pd2___width 1 | ||
| 389 | #define reg_pinmux_rw_pd_gio___pd2___bit 2 | ||
| 390 | #define reg_pinmux_rw_pd_gio___pd3___lsb 3 | ||
| 391 | #define reg_pinmux_rw_pd_gio___pd3___width 1 | ||
| 392 | #define reg_pinmux_rw_pd_gio___pd3___bit 3 | ||
| 393 | #define reg_pinmux_rw_pd_gio___pd4___lsb 4 | ||
| 394 | #define reg_pinmux_rw_pd_gio___pd4___width 1 | ||
| 395 | #define reg_pinmux_rw_pd_gio___pd4___bit 4 | ||
| 396 | #define reg_pinmux_rw_pd_gio___pd5___lsb 5 | ||
| 397 | #define reg_pinmux_rw_pd_gio___pd5___width 1 | ||
| 398 | #define reg_pinmux_rw_pd_gio___pd5___bit 5 | ||
| 399 | #define reg_pinmux_rw_pd_gio___pd6___lsb 6 | ||
| 400 | #define reg_pinmux_rw_pd_gio___pd6___width 1 | ||
| 401 | #define reg_pinmux_rw_pd_gio___pd6___bit 6 | ||
| 402 | #define reg_pinmux_rw_pd_gio___pd7___lsb 7 | ||
| 403 | #define reg_pinmux_rw_pd_gio___pd7___width 1 | ||
| 404 | #define reg_pinmux_rw_pd_gio___pd7___bit 7 | ||
| 405 | #define reg_pinmux_rw_pd_gio___pd8___lsb 8 | ||
| 406 | #define reg_pinmux_rw_pd_gio___pd8___width 1 | ||
| 407 | #define reg_pinmux_rw_pd_gio___pd8___bit 8 | ||
| 408 | #define reg_pinmux_rw_pd_gio___pd9___lsb 9 | ||
| 409 | #define reg_pinmux_rw_pd_gio___pd9___width 1 | ||
| 410 | #define reg_pinmux_rw_pd_gio___pd9___bit 9 | ||
| 411 | #define reg_pinmux_rw_pd_gio___pd10___lsb 10 | ||
| 412 | #define reg_pinmux_rw_pd_gio___pd10___width 1 | ||
| 413 | #define reg_pinmux_rw_pd_gio___pd10___bit 10 | ||
| 414 | #define reg_pinmux_rw_pd_gio___pd11___lsb 11 | ||
| 415 | #define reg_pinmux_rw_pd_gio___pd11___width 1 | ||
| 416 | #define reg_pinmux_rw_pd_gio___pd11___bit 11 | ||
| 417 | #define reg_pinmux_rw_pd_gio___pd12___lsb 12 | ||
| 418 | #define reg_pinmux_rw_pd_gio___pd12___width 1 | ||
| 419 | #define reg_pinmux_rw_pd_gio___pd12___bit 12 | ||
| 420 | #define reg_pinmux_rw_pd_gio___pd13___lsb 13 | ||
| 421 | #define reg_pinmux_rw_pd_gio___pd13___width 1 | ||
| 422 | #define reg_pinmux_rw_pd_gio___pd13___bit 13 | ||
| 423 | #define reg_pinmux_rw_pd_gio___pd14___lsb 14 | ||
| 424 | #define reg_pinmux_rw_pd_gio___pd14___width 1 | ||
| 425 | #define reg_pinmux_rw_pd_gio___pd14___bit 14 | ||
| 426 | #define reg_pinmux_rw_pd_gio___pd15___lsb 15 | ||
| 427 | #define reg_pinmux_rw_pd_gio___pd15___width 1 | ||
| 428 | #define reg_pinmux_rw_pd_gio___pd15___bit 15 | ||
| 429 | #define reg_pinmux_rw_pd_gio___pd16___lsb 16 | ||
| 430 | #define reg_pinmux_rw_pd_gio___pd16___width 1 | ||
| 431 | #define reg_pinmux_rw_pd_gio___pd16___bit 16 | ||
| 432 | #define reg_pinmux_rw_pd_gio___pd17___lsb 17 | ||
| 433 | #define reg_pinmux_rw_pd_gio___pd17___width 1 | ||
| 434 | #define reg_pinmux_rw_pd_gio___pd17___bit 17 | ||
| 435 | #define reg_pinmux_rw_pd_gio_offset 24 | ||
| 436 | |||
| 437 | /* Register rw_pd_iop, scope pinmux, type rw */ | ||
| 438 | #define reg_pinmux_rw_pd_iop___pd0___lsb 0 | ||
| 439 | #define reg_pinmux_rw_pd_iop___pd0___width 1 | ||
| 440 | #define reg_pinmux_rw_pd_iop___pd0___bit 0 | ||
| 441 | #define reg_pinmux_rw_pd_iop___pd1___lsb 1 | ||
| 442 | #define reg_pinmux_rw_pd_iop___pd1___width 1 | ||
| 443 | #define reg_pinmux_rw_pd_iop___pd1___bit 1 | ||
| 444 | #define reg_pinmux_rw_pd_iop___pd2___lsb 2 | ||
| 445 | #define reg_pinmux_rw_pd_iop___pd2___width 1 | ||
| 446 | #define reg_pinmux_rw_pd_iop___pd2___bit 2 | ||
| 447 | #define reg_pinmux_rw_pd_iop___pd3___lsb 3 | ||
| 448 | #define reg_pinmux_rw_pd_iop___pd3___width 1 | ||
| 449 | #define reg_pinmux_rw_pd_iop___pd3___bit 3 | ||
| 450 | #define reg_pinmux_rw_pd_iop___pd4___lsb 4 | ||
| 451 | #define reg_pinmux_rw_pd_iop___pd4___width 1 | ||
| 452 | #define reg_pinmux_rw_pd_iop___pd4___bit 4 | ||
| 453 | #define reg_pinmux_rw_pd_iop___pd5___lsb 5 | ||
| 454 | #define reg_pinmux_rw_pd_iop___pd5___width 1 | ||
| 455 | #define reg_pinmux_rw_pd_iop___pd5___bit 5 | ||
| 456 | #define reg_pinmux_rw_pd_iop___pd6___lsb 6 | ||
| 457 | #define reg_pinmux_rw_pd_iop___pd6___width 1 | ||
| 458 | #define reg_pinmux_rw_pd_iop___pd6___bit 6 | ||
| 459 | #define reg_pinmux_rw_pd_iop___pd7___lsb 7 | ||
| 460 | #define reg_pinmux_rw_pd_iop___pd7___width 1 | ||
| 461 | #define reg_pinmux_rw_pd_iop___pd7___bit 7 | ||
| 462 | #define reg_pinmux_rw_pd_iop___pd8___lsb 8 | ||
| 463 | #define reg_pinmux_rw_pd_iop___pd8___width 1 | ||
| 464 | #define reg_pinmux_rw_pd_iop___pd8___bit 8 | ||
| 465 | #define reg_pinmux_rw_pd_iop___pd9___lsb 9 | ||
| 466 | #define reg_pinmux_rw_pd_iop___pd9___width 1 | ||
| 467 | #define reg_pinmux_rw_pd_iop___pd9___bit 9 | ||
| 468 | #define reg_pinmux_rw_pd_iop___pd10___lsb 10 | ||
| 469 | #define reg_pinmux_rw_pd_iop___pd10___width 1 | ||
| 470 | #define reg_pinmux_rw_pd_iop___pd10___bit 10 | ||
| 471 | #define reg_pinmux_rw_pd_iop___pd11___lsb 11 | ||
| 472 | #define reg_pinmux_rw_pd_iop___pd11___width 1 | ||
| 473 | #define reg_pinmux_rw_pd_iop___pd11___bit 11 | ||
| 474 | #define reg_pinmux_rw_pd_iop___pd12___lsb 12 | ||
| 475 | #define reg_pinmux_rw_pd_iop___pd12___width 1 | ||
| 476 | #define reg_pinmux_rw_pd_iop___pd12___bit 12 | ||
| 477 | #define reg_pinmux_rw_pd_iop___pd13___lsb 13 | ||
| 478 | #define reg_pinmux_rw_pd_iop___pd13___width 1 | ||
| 479 | #define reg_pinmux_rw_pd_iop___pd13___bit 13 | ||
| 480 | #define reg_pinmux_rw_pd_iop___pd14___lsb 14 | ||
| 481 | #define reg_pinmux_rw_pd_iop___pd14___width 1 | ||
| 482 | #define reg_pinmux_rw_pd_iop___pd14___bit 14 | ||
| 483 | #define reg_pinmux_rw_pd_iop___pd15___lsb 15 | ||
| 484 | #define reg_pinmux_rw_pd_iop___pd15___width 1 | ||
| 485 | #define reg_pinmux_rw_pd_iop___pd15___bit 15 | ||
| 486 | #define reg_pinmux_rw_pd_iop___pd16___lsb 16 | ||
| 487 | #define reg_pinmux_rw_pd_iop___pd16___width 1 | ||
| 488 | #define reg_pinmux_rw_pd_iop___pd16___bit 16 | ||
| 489 | #define reg_pinmux_rw_pd_iop___pd17___lsb 17 | ||
| 490 | #define reg_pinmux_rw_pd_iop___pd17___width 1 | ||
| 491 | #define reg_pinmux_rw_pd_iop___pd17___bit 17 | ||
| 492 | #define reg_pinmux_rw_pd_iop_offset 28 | ||
| 493 | |||
| 494 | /* Register rw_pe_gio, scope pinmux, type rw */ | ||
| 495 | #define reg_pinmux_rw_pe_gio___pe0___lsb 0 | ||
| 496 | #define reg_pinmux_rw_pe_gio___pe0___width 1 | ||
| 497 | #define reg_pinmux_rw_pe_gio___pe0___bit 0 | ||
| 498 | #define reg_pinmux_rw_pe_gio___pe1___lsb 1 | ||
| 499 | #define reg_pinmux_rw_pe_gio___pe1___width 1 | ||
| 500 | #define reg_pinmux_rw_pe_gio___pe1___bit 1 | ||
| 501 | #define reg_pinmux_rw_pe_gio___pe2___lsb 2 | ||
| 502 | #define reg_pinmux_rw_pe_gio___pe2___width 1 | ||
| 503 | #define reg_pinmux_rw_pe_gio___pe2___bit 2 | ||
| 504 | #define reg_pinmux_rw_pe_gio___pe3___lsb 3 | ||
| 505 | #define reg_pinmux_rw_pe_gio___pe3___width 1 | ||
| 506 | #define reg_pinmux_rw_pe_gio___pe3___bit 3 | ||
| 507 | #define reg_pinmux_rw_pe_gio___pe4___lsb 4 | ||
| 508 | #define reg_pinmux_rw_pe_gio___pe4___width 1 | ||
| 509 | #define reg_pinmux_rw_pe_gio___pe4___bit 4 | ||
| 510 | #define reg_pinmux_rw_pe_gio___pe5___lsb 5 | ||
| 511 | #define reg_pinmux_rw_pe_gio___pe5___width 1 | ||
| 512 | #define reg_pinmux_rw_pe_gio___pe5___bit 5 | ||
| 513 | #define reg_pinmux_rw_pe_gio___pe6___lsb 6 | ||
| 514 | #define reg_pinmux_rw_pe_gio___pe6___width 1 | ||
| 515 | #define reg_pinmux_rw_pe_gio___pe6___bit 6 | ||
| 516 | #define reg_pinmux_rw_pe_gio___pe7___lsb 7 | ||
| 517 | #define reg_pinmux_rw_pe_gio___pe7___width 1 | ||
| 518 | #define reg_pinmux_rw_pe_gio___pe7___bit 7 | ||
| 519 | #define reg_pinmux_rw_pe_gio___pe8___lsb 8 | ||
| 520 | #define reg_pinmux_rw_pe_gio___pe8___width 1 | ||
| 521 | #define reg_pinmux_rw_pe_gio___pe8___bit 8 | ||
| 522 | #define reg_pinmux_rw_pe_gio___pe9___lsb 9 | ||
| 523 | #define reg_pinmux_rw_pe_gio___pe9___width 1 | ||
| 524 | #define reg_pinmux_rw_pe_gio___pe9___bit 9 | ||
| 525 | #define reg_pinmux_rw_pe_gio___pe10___lsb 10 | ||
| 526 | #define reg_pinmux_rw_pe_gio___pe10___width 1 | ||
| 527 | #define reg_pinmux_rw_pe_gio___pe10___bit 10 | ||
| 528 | #define reg_pinmux_rw_pe_gio___pe11___lsb 11 | ||
| 529 | #define reg_pinmux_rw_pe_gio___pe11___width 1 | ||
| 530 | #define reg_pinmux_rw_pe_gio___pe11___bit 11 | ||
| 531 | #define reg_pinmux_rw_pe_gio___pe12___lsb 12 | ||
| 532 | #define reg_pinmux_rw_pe_gio___pe12___width 1 | ||
| 533 | #define reg_pinmux_rw_pe_gio___pe12___bit 12 | ||
| 534 | #define reg_pinmux_rw_pe_gio___pe13___lsb 13 | ||
| 535 | #define reg_pinmux_rw_pe_gio___pe13___width 1 | ||
| 536 | #define reg_pinmux_rw_pe_gio___pe13___bit 13 | ||
| 537 | #define reg_pinmux_rw_pe_gio___pe14___lsb 14 | ||
| 538 | #define reg_pinmux_rw_pe_gio___pe14___width 1 | ||
| 539 | #define reg_pinmux_rw_pe_gio___pe14___bit 14 | ||
| 540 | #define reg_pinmux_rw_pe_gio___pe15___lsb 15 | ||
| 541 | #define reg_pinmux_rw_pe_gio___pe15___width 1 | ||
| 542 | #define reg_pinmux_rw_pe_gio___pe15___bit 15 | ||
| 543 | #define reg_pinmux_rw_pe_gio___pe16___lsb 16 | ||
| 544 | #define reg_pinmux_rw_pe_gio___pe16___width 1 | ||
| 545 | #define reg_pinmux_rw_pe_gio___pe16___bit 16 | ||
| 546 | #define reg_pinmux_rw_pe_gio___pe17___lsb 17 | ||
| 547 | #define reg_pinmux_rw_pe_gio___pe17___width 1 | ||
| 548 | #define reg_pinmux_rw_pe_gio___pe17___bit 17 | ||
| 549 | #define reg_pinmux_rw_pe_gio_offset 32 | ||
| 550 | |||
| 551 | /* Register rw_pe_iop, scope pinmux, type rw */ | ||
| 552 | #define reg_pinmux_rw_pe_iop___pe0___lsb 0 | ||
| 553 | #define reg_pinmux_rw_pe_iop___pe0___width 1 | ||
| 554 | #define reg_pinmux_rw_pe_iop___pe0___bit 0 | ||
| 555 | #define reg_pinmux_rw_pe_iop___pe1___lsb 1 | ||
| 556 | #define reg_pinmux_rw_pe_iop___pe1___width 1 | ||
| 557 | #define reg_pinmux_rw_pe_iop___pe1___bit 1 | ||
| 558 | #define reg_pinmux_rw_pe_iop___pe2___lsb 2 | ||
| 559 | #define reg_pinmux_rw_pe_iop___pe2___width 1 | ||
| 560 | #define reg_pinmux_rw_pe_iop___pe2___bit 2 | ||
| 561 | #define reg_pinmux_rw_pe_iop___pe3___lsb 3 | ||
| 562 | #define reg_pinmux_rw_pe_iop___pe3___width 1 | ||
| 563 | #define reg_pinmux_rw_pe_iop___pe3___bit 3 | ||
| 564 | #define reg_pinmux_rw_pe_iop___pe4___lsb 4 | ||
| 565 | #define reg_pinmux_rw_pe_iop___pe4___width 1 | ||
| 566 | #define reg_pinmux_rw_pe_iop___pe4___bit 4 | ||
| 567 | #define reg_pinmux_rw_pe_iop___pe5___lsb 5 | ||
| 568 | #define reg_pinmux_rw_pe_iop___pe5___width 1 | ||
| 569 | #define reg_pinmux_rw_pe_iop___pe5___bit 5 | ||
| 570 | #define reg_pinmux_rw_pe_iop___pe6___lsb 6 | ||
| 571 | #define reg_pinmux_rw_pe_iop___pe6___width 1 | ||
| 572 | #define reg_pinmux_rw_pe_iop___pe6___bit 6 | ||
| 573 | #define reg_pinmux_rw_pe_iop___pe7___lsb 7 | ||
| 574 | #define reg_pinmux_rw_pe_iop___pe7___width 1 | ||
| 575 | #define reg_pinmux_rw_pe_iop___pe7___bit 7 | ||
| 576 | #define reg_pinmux_rw_pe_iop___pe8___lsb 8 | ||
| 577 | #define reg_pinmux_rw_pe_iop___pe8___width 1 | ||
| 578 | #define reg_pinmux_rw_pe_iop___pe8___bit 8 | ||
| 579 | #define reg_pinmux_rw_pe_iop___pe9___lsb 9 | ||
| 580 | #define reg_pinmux_rw_pe_iop___pe9___width 1 | ||
| 581 | #define reg_pinmux_rw_pe_iop___pe9___bit 9 | ||
| 582 | #define reg_pinmux_rw_pe_iop___pe10___lsb 10 | ||
| 583 | #define reg_pinmux_rw_pe_iop___pe10___width 1 | ||
| 584 | #define reg_pinmux_rw_pe_iop___pe10___bit 10 | ||
| 585 | #define reg_pinmux_rw_pe_iop___pe11___lsb 11 | ||
| 586 | #define reg_pinmux_rw_pe_iop___pe11___width 1 | ||
| 587 | #define reg_pinmux_rw_pe_iop___pe11___bit 11 | ||
| 588 | #define reg_pinmux_rw_pe_iop___pe12___lsb 12 | ||
| 589 | #define reg_pinmux_rw_pe_iop___pe12___width 1 | ||
| 590 | #define reg_pinmux_rw_pe_iop___pe12___bit 12 | ||
| 591 | #define reg_pinmux_rw_pe_iop___pe13___lsb 13 | ||
| 592 | #define reg_pinmux_rw_pe_iop___pe13___width 1 | ||
| 593 | #define reg_pinmux_rw_pe_iop___pe13___bit 13 | ||
| 594 | #define reg_pinmux_rw_pe_iop___pe14___lsb 14 | ||
| 595 | #define reg_pinmux_rw_pe_iop___pe14___width 1 | ||
| 596 | #define reg_pinmux_rw_pe_iop___pe14___bit 14 | ||
| 597 | #define reg_pinmux_rw_pe_iop___pe15___lsb 15 | ||
| 598 | #define reg_pinmux_rw_pe_iop___pe15___width 1 | ||
| 599 | #define reg_pinmux_rw_pe_iop___pe15___bit 15 | ||
| 600 | #define reg_pinmux_rw_pe_iop___pe16___lsb 16 | ||
| 601 | #define reg_pinmux_rw_pe_iop___pe16___width 1 | ||
| 602 | #define reg_pinmux_rw_pe_iop___pe16___bit 16 | ||
| 603 | #define reg_pinmux_rw_pe_iop___pe17___lsb 17 | ||
| 604 | #define reg_pinmux_rw_pe_iop___pe17___width 1 | ||
| 605 | #define reg_pinmux_rw_pe_iop___pe17___bit 17 | ||
| 606 | #define reg_pinmux_rw_pe_iop_offset 36 | ||
| 607 | |||
| 608 | /* Register rw_usb_phy, scope pinmux, type rw */ | ||
| 609 | #define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 | ||
| 610 | #define reg_pinmux_rw_usb_phy___en_usb0___width 1 | ||
| 611 | #define reg_pinmux_rw_usb_phy___en_usb0___bit 0 | ||
| 612 | #define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 | ||
| 613 | #define reg_pinmux_rw_usb_phy___en_usb1___width 1 | ||
| 614 | #define reg_pinmux_rw_usb_phy___en_usb1___bit 1 | ||
| 615 | #define reg_pinmux_rw_usb_phy_offset 40 | ||
| 616 | |||
| 617 | |||
| 618 | /* Constants */ | ||
| 619 | #define regk_pinmux_no 0x00000000 | ||
| 620 | #define regk_pinmux_rw_hwprot_default 0x00000000 | ||
| 621 | #define regk_pinmux_rw_pa_default 0x00000000 | ||
| 622 | #define regk_pinmux_rw_pb_gio_default 0x00000000 | ||
| 623 | #define regk_pinmux_rw_pb_iop_default 0x00000000 | ||
| 624 | #define regk_pinmux_rw_pc_gio_default 0x00000000 | ||
| 625 | #define regk_pinmux_rw_pc_iop_default 0x00000000 | ||
| 626 | #define regk_pinmux_rw_pd_gio_default 0x00000000 | ||
| 627 | #define regk_pinmux_rw_pd_iop_default 0x00000000 | ||
| 628 | #define regk_pinmux_rw_pe_gio_default 0x00000000 | ||
| 629 | #define regk_pinmux_rw_pe_iop_default 0x00000000 | ||
| 630 | #define regk_pinmux_rw_usb_phy_default 0x00000000 | ||
| 631 | #define regk_pinmux_yes 0x00000001 | ||
| 632 | #endif /* __pinmux_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 76959b70cd2c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | #ifndef __reg_map_h | ||
| 2 | #define __reg_map_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../mod/fakereg.rmap | ||
| 7 | * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp | ||
| 8 | * last modified: Wed Feb 11 20:53:25 2004 | ||
| 9 | * file: ../../rtl/global.rmap | ||
| 10 | * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp | ||
| 11 | * last modified: Mon Aug 18 17:08:23 2003 | ||
| 12 | * file: ../../mod/modreg.rmap | ||
| 13 | * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp | ||
| 14 | * last modified: Fri Feb 20 16:40:04 2004 | ||
| 15 | * | ||
| 16 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap | ||
| 17 | * id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 18 | * Any changes here will be lost. | ||
| 19 | * | ||
| 20 | * -*- buffer-read-only: t -*- | ||
| 21 | */ | ||
| 22 | #define regi_artpec_mod 0xb7044000 | ||
| 23 | #define regi_ata 0xb0032000 | ||
| 24 | #define regi_ata_mod 0xb7006000 | ||
| 25 | #define regi_barber 0xb701a000 | ||
| 26 | #define regi_bif_core 0xb0014000 | ||
| 27 | #define regi_bif_dma 0xb0016000 | ||
| 28 | #define regi_bif_slave 0xb0018000 | ||
| 29 | #define regi_bif_slave_ext 0xac000000 | ||
| 30 | #define regi_bus_master 0xb703c000 | ||
| 31 | #define regi_config 0xb003c000 | ||
| 32 | #define regi_dma0 0xb0000000 | ||
| 33 | #define regi_dma1 0xb0002000 | ||
| 34 | #define regi_dma2 0xb0004000 | ||
| 35 | #define regi_dma3 0xb0006000 | ||
| 36 | #define regi_dma4 0xb0008000 | ||
| 37 | #define regi_dma5 0xb000a000 | ||
| 38 | #define regi_dma6 0xb000c000 | ||
| 39 | #define regi_dma7 0xb000e000 | ||
| 40 | #define regi_dma8 0xb0010000 | ||
| 41 | #define regi_dma9 0xb0012000 | ||
| 42 | #define regi_eth0 0xb0034000 | ||
| 43 | #define regi_eth1 0xb0036000 | ||
| 44 | #define regi_eth_mod 0xb7004000 | ||
| 45 | #define regi_eth_mod1 0xb701c000 | ||
| 46 | #define regi_eth_strmod 0xb7008000 | ||
| 47 | #define regi_eth_strmod1 0xb7032000 | ||
| 48 | #define regi_ext_dma 0xb703a000 | ||
| 49 | #define regi_ext_mem 0xb7046000 | ||
| 50 | #define regi_gen_io 0xb7016000 | ||
| 51 | #define regi_gio 0xb001a000 | ||
| 52 | #define regi_hook 0xb7000000 | ||
| 53 | #define regi_iop 0xb0020000 | ||
| 54 | #define regi_irq 0xb001c000 | ||
| 55 | #define regi_irq_nmi 0xb701e000 | ||
| 56 | #define regi_marb 0xb003e000 | ||
| 57 | #define regi_marb_bp0 0xb003e240 | ||
| 58 | #define regi_marb_bp1 0xb003e280 | ||
| 59 | #define regi_marb_bp2 0xb003e2c0 | ||
| 60 | #define regi_marb_bp3 0xb003e300 | ||
| 61 | #define regi_nand_mod 0xb7014000 | ||
| 62 | #define regi_p21 0xb002e000 | ||
| 63 | #define regi_p21_mod 0xb7042000 | ||
| 64 | #define regi_pci_mod 0xb7010000 | ||
| 65 | #define regi_pin_test 0xb7018000 | ||
| 66 | #define regi_pinmux 0xb0038000 | ||
| 67 | #define regi_sdram_chk 0xb703e000 | ||
| 68 | #define regi_sdram_mod 0xb7012000 | ||
| 69 | #define regi_ser0 0xb0026000 | ||
| 70 | #define regi_ser1 0xb0028000 | ||
| 71 | #define regi_ser2 0xb002a000 | ||
| 72 | #define regi_ser3 0xb002c000 | ||
| 73 | #define regi_ser_mod0 0xb7020000 | ||
| 74 | #define regi_ser_mod1 0xb7022000 | ||
| 75 | #define regi_ser_mod2 0xb7024000 | ||
| 76 | #define regi_ser_mod3 0xb7026000 | ||
| 77 | #define regi_smif_stat 0xb700e000 | ||
| 78 | #define regi_sser0 0xb0022000 | ||
| 79 | #define regi_sser1 0xb0024000 | ||
| 80 | #define regi_sser_mod0 0xb700a000 | ||
| 81 | #define regi_sser_mod1 0xb700c000 | ||
| 82 | #define regi_strcop 0xb0030000 | ||
| 83 | #define regi_strmux 0xb003a000 | ||
| 84 | #define regi_strmux_tst 0xb7040000 | ||
| 85 | #define regi_tap 0xb7002000 | ||
| 86 | #define regi_timer 0xb001e000 | ||
| 87 | #define regi_timer_mod 0xb7034000 | ||
| 88 | #define regi_trace 0xb0040000 | ||
| 89 | #define regi_usb0 0xb7028000 | ||
| 90 | #define regi_usb1 0xb702a000 | ||
| 91 | #define regi_usb2 0xb702c000 | ||
| 92 | #define regi_usb3 0xb702e000 | ||
| 93 | #define regi_usb_dev 0xb7030000 | ||
| 94 | #define regi_utmi_mod0 0xb7036000 | ||
| 95 | #define regi_utmi_mod1 0xb7038000 | ||
| 96 | #endif /* __reg_map_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h deleted file mode 100644 index 10246f49fb28..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h +++ /dev/null | |||
| @@ -1,142 +0,0 @@ | |||
| 1 | #ifndef __rt_trace_defs_asm_h | ||
| 2 | #define __rt_trace_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/rt_trace/rtl/rt_regs.r | ||
| 7 | * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:14 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r | ||
| 11 | * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope rt_trace, type rw */ | ||
| 57 | #define reg_rt_trace_rw_cfg___en___lsb 0 | ||
| 58 | #define reg_rt_trace_rw_cfg___en___width 1 | ||
| 59 | #define reg_rt_trace_rw_cfg___en___bit 0 | ||
| 60 | #define reg_rt_trace_rw_cfg___mode___lsb 1 | ||
| 61 | #define reg_rt_trace_rw_cfg___mode___width 1 | ||
| 62 | #define reg_rt_trace_rw_cfg___mode___bit 1 | ||
| 63 | #define reg_rt_trace_rw_cfg___owner___lsb 2 | ||
| 64 | #define reg_rt_trace_rw_cfg___owner___width 1 | ||
| 65 | #define reg_rt_trace_rw_cfg___owner___bit 2 | ||
| 66 | #define reg_rt_trace_rw_cfg___wp___lsb 3 | ||
| 67 | #define reg_rt_trace_rw_cfg___wp___width 1 | ||
| 68 | #define reg_rt_trace_rw_cfg___wp___bit 3 | ||
| 69 | #define reg_rt_trace_rw_cfg___stall___lsb 4 | ||
| 70 | #define reg_rt_trace_rw_cfg___stall___width 1 | ||
| 71 | #define reg_rt_trace_rw_cfg___stall___bit 4 | ||
| 72 | #define reg_rt_trace_rw_cfg___wp_start___lsb 8 | ||
| 73 | #define reg_rt_trace_rw_cfg___wp_start___width 7 | ||
| 74 | #define reg_rt_trace_rw_cfg___wp_stop___lsb 16 | ||
| 75 | #define reg_rt_trace_rw_cfg___wp_stop___width 7 | ||
| 76 | #define reg_rt_trace_rw_cfg_offset 0 | ||
| 77 | |||
| 78 | /* Register rw_tap_ctrl, scope rt_trace, type rw */ | ||
| 79 | #define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0 | ||
| 80 | #define reg_rt_trace_rw_tap_ctrl___ack_data___width 1 | ||
| 81 | #define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0 | ||
| 82 | #define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1 | ||
| 83 | #define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1 | ||
| 84 | #define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1 | ||
| 85 | #define reg_rt_trace_rw_tap_ctrl_offset 4 | ||
| 86 | |||
| 87 | /* Register r_tap_stat, scope rt_trace, type r */ | ||
| 88 | #define reg_rt_trace_r_tap_stat___dav___lsb 0 | ||
| 89 | #define reg_rt_trace_r_tap_stat___dav___width 1 | ||
| 90 | #define reg_rt_trace_r_tap_stat___dav___bit 0 | ||
| 91 | #define reg_rt_trace_r_tap_stat___empty___lsb 1 | ||
| 92 | #define reg_rt_trace_r_tap_stat___empty___width 1 | ||
| 93 | #define reg_rt_trace_r_tap_stat___empty___bit 1 | ||
| 94 | #define reg_rt_trace_r_tap_stat_offset 8 | ||
| 95 | |||
| 96 | /* Register rw_tap_data, scope rt_trace, type rw */ | ||
| 97 | #define reg_rt_trace_rw_tap_data_offset 12 | ||
| 98 | |||
| 99 | /* Register rw_tap_hdata, scope rt_trace, type rw */ | ||
| 100 | #define reg_rt_trace_rw_tap_hdata___op___lsb 0 | ||
| 101 | #define reg_rt_trace_rw_tap_hdata___op___width 4 | ||
| 102 | #define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4 | ||
| 103 | #define reg_rt_trace_rw_tap_hdata___sub_op___width 4 | ||
| 104 | #define reg_rt_trace_rw_tap_hdata_offset 16 | ||
| 105 | |||
| 106 | /* Register r_redir, scope rt_trace, type r */ | ||
| 107 | #define reg_rt_trace_r_redir_offset 20 | ||
| 108 | |||
| 109 | |||
| 110 | /* Constants */ | ||
| 111 | #define regk_rt_trace_brk 0x0000000c | ||
| 112 | #define regk_rt_trace_dbg 0x00000003 | ||
| 113 | #define regk_rt_trace_dbgdi 0x00000004 | ||
| 114 | #define regk_rt_trace_dbgdo 0x00000005 | ||
| 115 | #define regk_rt_trace_gmode 0x00000000 | ||
| 116 | #define regk_rt_trace_no 0x00000000 | ||
| 117 | #define regk_rt_trace_nop 0x00000000 | ||
| 118 | #define regk_rt_trace_normal 0x00000000 | ||
| 119 | #define regk_rt_trace_rdmem 0x00000007 | ||
| 120 | #define regk_rt_trace_rdmemb 0x00000009 | ||
| 121 | #define regk_rt_trace_rdpreg 0x00000002 | ||
| 122 | #define regk_rt_trace_rdreg 0x00000001 | ||
| 123 | #define regk_rt_trace_rdsreg 0x00000003 | ||
| 124 | #define regk_rt_trace_redir 0x00000006 | ||
| 125 | #define regk_rt_trace_ret 0x0000000b | ||
| 126 | #define regk_rt_trace_rw_cfg_default 0x00000000 | ||
| 127 | #define regk_rt_trace_trcfg 0x00000001 | ||
| 128 | #define regk_rt_trace_wp 0x00000001 | ||
| 129 | #define regk_rt_trace_wp0 0x00000001 | ||
| 130 | #define regk_rt_trace_wp1 0x00000002 | ||
| 131 | #define regk_rt_trace_wp2 0x00000004 | ||
| 132 | #define regk_rt_trace_wp3 0x00000008 | ||
| 133 | #define regk_rt_trace_wp4 0x00000010 | ||
| 134 | #define regk_rt_trace_wp5 0x00000020 | ||
| 135 | #define regk_rt_trace_wp6 0x00000040 | ||
| 136 | #define regk_rt_trace_wrmem 0x00000008 | ||
| 137 | #define regk_rt_trace_wrmemb 0x0000000a | ||
| 138 | #define regk_rt_trace_wrpreg 0x00000005 | ||
| 139 | #define regk_rt_trace_wrreg 0x00000004 | ||
| 140 | #define regk_rt_trace_wrsreg 0x00000006 | ||
| 141 | #define regk_rt_trace_yes 0x00000001 | ||
| 142 | #endif /* __rt_trace_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h deleted file mode 100644 index 4a2808bdf390..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h +++ /dev/null | |||
| @@ -1,359 +0,0 @@ | |||
| 1 | #ifndef __ser_defs_asm_h | ||
| 2 | #define __ser_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/ser/rtl/ser_regs.r | ||
| 7 | * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:21 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r | ||
| 11 | * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_tr_ctrl, scope ser, type rw */ | ||
| 57 | #define reg_ser_rw_tr_ctrl___base_freq___lsb 0 | ||
| 58 | #define reg_ser_rw_tr_ctrl___base_freq___width 3 | ||
| 59 | #define reg_ser_rw_tr_ctrl___en___lsb 3 | ||
| 60 | #define reg_ser_rw_tr_ctrl___en___width 1 | ||
| 61 | #define reg_ser_rw_tr_ctrl___en___bit 3 | ||
| 62 | #define reg_ser_rw_tr_ctrl___par___lsb 4 | ||
| 63 | #define reg_ser_rw_tr_ctrl___par___width 2 | ||
| 64 | #define reg_ser_rw_tr_ctrl___par_en___lsb 6 | ||
| 65 | #define reg_ser_rw_tr_ctrl___par_en___width 1 | ||
| 66 | #define reg_ser_rw_tr_ctrl___par_en___bit 6 | ||
| 67 | #define reg_ser_rw_tr_ctrl___data_bits___lsb 7 | ||
| 68 | #define reg_ser_rw_tr_ctrl___data_bits___width 1 | ||
| 69 | #define reg_ser_rw_tr_ctrl___data_bits___bit 7 | ||
| 70 | #define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 | ||
| 71 | #define reg_ser_rw_tr_ctrl___stop_bits___width 1 | ||
| 72 | #define reg_ser_rw_tr_ctrl___stop_bits___bit 8 | ||
| 73 | #define reg_ser_rw_tr_ctrl___stop___lsb 9 | ||
| 74 | #define reg_ser_rw_tr_ctrl___stop___width 1 | ||
| 75 | #define reg_ser_rw_tr_ctrl___stop___bit 9 | ||
| 76 | #define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 | ||
| 77 | #define reg_ser_rw_tr_ctrl___rts_delay___width 3 | ||
| 78 | #define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 | ||
| 79 | #define reg_ser_rw_tr_ctrl___rts_setup___width 1 | ||
| 80 | #define reg_ser_rw_tr_ctrl___rts_setup___bit 13 | ||
| 81 | #define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 | ||
| 82 | #define reg_ser_rw_tr_ctrl___auto_rts___width 1 | ||
| 83 | #define reg_ser_rw_tr_ctrl___auto_rts___bit 14 | ||
| 84 | #define reg_ser_rw_tr_ctrl___txd___lsb 15 | ||
| 85 | #define reg_ser_rw_tr_ctrl___txd___width 1 | ||
| 86 | #define reg_ser_rw_tr_ctrl___txd___bit 15 | ||
| 87 | #define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 | ||
| 88 | #define reg_ser_rw_tr_ctrl___auto_cts___width 1 | ||
| 89 | #define reg_ser_rw_tr_ctrl___auto_cts___bit 16 | ||
| 90 | #define reg_ser_rw_tr_ctrl_offset 0 | ||
| 91 | |||
| 92 | /* Register rw_tr_dma_en, scope ser, type rw */ | ||
| 93 | #define reg_ser_rw_tr_dma_en___en___lsb 0 | ||
| 94 | #define reg_ser_rw_tr_dma_en___en___width 1 | ||
| 95 | #define reg_ser_rw_tr_dma_en___en___bit 0 | ||
| 96 | #define reg_ser_rw_tr_dma_en_offset 4 | ||
| 97 | |||
| 98 | /* Register rw_rec_ctrl, scope ser, type rw */ | ||
| 99 | #define reg_ser_rw_rec_ctrl___base_freq___lsb 0 | ||
| 100 | #define reg_ser_rw_rec_ctrl___base_freq___width 3 | ||
| 101 | #define reg_ser_rw_rec_ctrl___en___lsb 3 | ||
| 102 | #define reg_ser_rw_rec_ctrl___en___width 1 | ||
| 103 | #define reg_ser_rw_rec_ctrl___en___bit 3 | ||
| 104 | #define reg_ser_rw_rec_ctrl___par___lsb 4 | ||
| 105 | #define reg_ser_rw_rec_ctrl___par___width 2 | ||
| 106 | #define reg_ser_rw_rec_ctrl___par_en___lsb 6 | ||
| 107 | #define reg_ser_rw_rec_ctrl___par_en___width 1 | ||
| 108 | #define reg_ser_rw_rec_ctrl___par_en___bit 6 | ||
| 109 | #define reg_ser_rw_rec_ctrl___data_bits___lsb 7 | ||
| 110 | #define reg_ser_rw_rec_ctrl___data_bits___width 1 | ||
| 111 | #define reg_ser_rw_rec_ctrl___data_bits___bit 7 | ||
| 112 | #define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 | ||
| 113 | #define reg_ser_rw_rec_ctrl___dma_mode___width 1 | ||
| 114 | #define reg_ser_rw_rec_ctrl___dma_mode___bit 8 | ||
| 115 | #define reg_ser_rw_rec_ctrl___dma_err___lsb 9 | ||
| 116 | #define reg_ser_rw_rec_ctrl___dma_err___width 1 | ||
| 117 | #define reg_ser_rw_rec_ctrl___dma_err___bit 9 | ||
| 118 | #define reg_ser_rw_rec_ctrl___sampling___lsb 10 | ||
| 119 | #define reg_ser_rw_rec_ctrl___sampling___width 1 | ||
| 120 | #define reg_ser_rw_rec_ctrl___sampling___bit 10 | ||
| 121 | #define reg_ser_rw_rec_ctrl___timeout___lsb 11 | ||
| 122 | #define reg_ser_rw_rec_ctrl___timeout___width 3 | ||
| 123 | #define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 | ||
| 124 | #define reg_ser_rw_rec_ctrl___auto_eop___width 1 | ||
| 125 | #define reg_ser_rw_rec_ctrl___auto_eop___bit 14 | ||
| 126 | #define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 | ||
| 127 | #define reg_ser_rw_rec_ctrl___half_duplex___width 1 | ||
| 128 | #define reg_ser_rw_rec_ctrl___half_duplex___bit 15 | ||
| 129 | #define reg_ser_rw_rec_ctrl___rts_n___lsb 16 | ||
| 130 | #define reg_ser_rw_rec_ctrl___rts_n___width 1 | ||
| 131 | #define reg_ser_rw_rec_ctrl___rts_n___bit 16 | ||
| 132 | #define reg_ser_rw_rec_ctrl___loopback___lsb 17 | ||
| 133 | #define reg_ser_rw_rec_ctrl___loopback___width 1 | ||
| 134 | #define reg_ser_rw_rec_ctrl___loopback___bit 17 | ||
| 135 | #define reg_ser_rw_rec_ctrl_offset 8 | ||
| 136 | |||
| 137 | /* Register rw_tr_baud_div, scope ser, type rw */ | ||
| 138 | #define reg_ser_rw_tr_baud_div___div___lsb 0 | ||
| 139 | #define reg_ser_rw_tr_baud_div___div___width 16 | ||
| 140 | #define reg_ser_rw_tr_baud_div_offset 12 | ||
| 141 | |||
| 142 | /* Register rw_rec_baud_div, scope ser, type rw */ | ||
| 143 | #define reg_ser_rw_rec_baud_div___div___lsb 0 | ||
| 144 | #define reg_ser_rw_rec_baud_div___div___width 16 | ||
| 145 | #define reg_ser_rw_rec_baud_div_offset 16 | ||
| 146 | |||
| 147 | /* Register rw_xoff, scope ser, type rw */ | ||
| 148 | #define reg_ser_rw_xoff___chr___lsb 0 | ||
| 149 | #define reg_ser_rw_xoff___chr___width 8 | ||
| 150 | #define reg_ser_rw_xoff___automatic___lsb 8 | ||
| 151 | #define reg_ser_rw_xoff___automatic___width 1 | ||
| 152 | #define reg_ser_rw_xoff___automatic___bit 8 | ||
| 153 | #define reg_ser_rw_xoff_offset 20 | ||
| 154 | |||
| 155 | /* Register rw_xoff_clr, scope ser, type rw */ | ||
| 156 | #define reg_ser_rw_xoff_clr___clr___lsb 0 | ||
| 157 | #define reg_ser_rw_xoff_clr___clr___width 1 | ||
| 158 | #define reg_ser_rw_xoff_clr___clr___bit 0 | ||
| 159 | #define reg_ser_rw_xoff_clr_offset 24 | ||
| 160 | |||
| 161 | /* Register rw_dout, scope ser, type rw */ | ||
| 162 | #define reg_ser_rw_dout___data___lsb 0 | ||
| 163 | #define reg_ser_rw_dout___data___width 8 | ||
| 164 | #define reg_ser_rw_dout_offset 28 | ||
| 165 | |||
| 166 | /* Register rs_stat_din, scope ser, type rs */ | ||
| 167 | #define reg_ser_rs_stat_din___data___lsb 0 | ||
| 168 | #define reg_ser_rs_stat_din___data___width 8 | ||
| 169 | #define reg_ser_rs_stat_din___dav___lsb 16 | ||
| 170 | #define reg_ser_rs_stat_din___dav___width 1 | ||
| 171 | #define reg_ser_rs_stat_din___dav___bit 16 | ||
| 172 | #define reg_ser_rs_stat_din___framing_err___lsb 17 | ||
| 173 | #define reg_ser_rs_stat_din___framing_err___width 1 | ||
| 174 | #define reg_ser_rs_stat_din___framing_err___bit 17 | ||
| 175 | #define reg_ser_rs_stat_din___par_err___lsb 18 | ||
| 176 | #define reg_ser_rs_stat_din___par_err___width 1 | ||
| 177 | #define reg_ser_rs_stat_din___par_err___bit 18 | ||
| 178 | #define reg_ser_rs_stat_din___orun___lsb 19 | ||
| 179 | #define reg_ser_rs_stat_din___orun___width 1 | ||
| 180 | #define reg_ser_rs_stat_din___orun___bit 19 | ||
| 181 | #define reg_ser_rs_stat_din___rec_err___lsb 20 | ||
| 182 | #define reg_ser_rs_stat_din___rec_err___width 1 | ||
| 183 | #define reg_ser_rs_stat_din___rec_err___bit 20 | ||
| 184 | #define reg_ser_rs_stat_din___rxd___lsb 21 | ||
| 185 | #define reg_ser_rs_stat_din___rxd___width 1 | ||
| 186 | #define reg_ser_rs_stat_din___rxd___bit 21 | ||
| 187 | #define reg_ser_rs_stat_din___tr_idle___lsb 22 | ||
| 188 | #define reg_ser_rs_stat_din___tr_idle___width 1 | ||
| 189 | #define reg_ser_rs_stat_din___tr_idle___bit 22 | ||
| 190 | #define reg_ser_rs_stat_din___tr_empty___lsb 23 | ||
| 191 | #define reg_ser_rs_stat_din___tr_empty___width 1 | ||
| 192 | #define reg_ser_rs_stat_din___tr_empty___bit 23 | ||
| 193 | #define reg_ser_rs_stat_din___tr_rdy___lsb 24 | ||
| 194 | #define reg_ser_rs_stat_din___tr_rdy___width 1 | ||
| 195 | #define reg_ser_rs_stat_din___tr_rdy___bit 24 | ||
| 196 | #define reg_ser_rs_stat_din___cts_n___lsb 25 | ||
| 197 | #define reg_ser_rs_stat_din___cts_n___width 1 | ||
| 198 | #define reg_ser_rs_stat_din___cts_n___bit 25 | ||
| 199 | #define reg_ser_rs_stat_din___xoff_detect___lsb 26 | ||
| 200 | #define reg_ser_rs_stat_din___xoff_detect___width 1 | ||
| 201 | #define reg_ser_rs_stat_din___xoff_detect___bit 26 | ||
| 202 | #define reg_ser_rs_stat_din___rts_n___lsb 27 | ||
| 203 | #define reg_ser_rs_stat_din___rts_n___width 1 | ||
| 204 | #define reg_ser_rs_stat_din___rts_n___bit 27 | ||
| 205 | #define reg_ser_rs_stat_din___txd___lsb 28 | ||
| 206 | #define reg_ser_rs_stat_din___txd___width 1 | ||
| 207 | #define reg_ser_rs_stat_din___txd___bit 28 | ||
| 208 | #define reg_ser_rs_stat_din_offset 32 | ||
| 209 | |||
| 210 | /* Register r_stat_din, scope ser, type r */ | ||
| 211 | #define reg_ser_r_stat_din___data___lsb 0 | ||
| 212 | #define reg_ser_r_stat_din___data___width 8 | ||
| 213 | #define reg_ser_r_stat_din___dav___lsb 16 | ||
| 214 | #define reg_ser_r_stat_din___dav___width 1 | ||
| 215 | #define reg_ser_r_stat_din___dav___bit 16 | ||
| 216 | #define reg_ser_r_stat_din___framing_err___lsb 17 | ||
| 217 | #define reg_ser_r_stat_din___framing_err___width 1 | ||
| 218 | #define reg_ser_r_stat_din___framing_err___bit 17 | ||
| 219 | #define reg_ser_r_stat_din___par_err___lsb 18 | ||
| 220 | #define reg_ser_r_stat_din___par_err___width 1 | ||
| 221 | #define reg_ser_r_stat_din___par_err___bit 18 | ||
| 222 | #define reg_ser_r_stat_din___orun___lsb 19 | ||
| 223 | #define reg_ser_r_stat_din___orun___width 1 | ||
| 224 | #define reg_ser_r_stat_din___orun___bit 19 | ||
| 225 | #define reg_ser_r_stat_din___rec_err___lsb 20 | ||
| 226 | #define reg_ser_r_stat_din___rec_err___width 1 | ||
| 227 | #define reg_ser_r_stat_din___rec_err___bit 20 | ||
| 228 | #define reg_ser_r_stat_din___rxd___lsb 21 | ||
| 229 | #define reg_ser_r_stat_din___rxd___width 1 | ||
| 230 | #define reg_ser_r_stat_din___rxd___bit 21 | ||
| 231 | #define reg_ser_r_stat_din___tr_idle___lsb 22 | ||
| 232 | #define reg_ser_r_stat_din___tr_idle___width 1 | ||
| 233 | #define reg_ser_r_stat_din___tr_idle___bit 22 | ||
| 234 | #define reg_ser_r_stat_din___tr_empty___lsb 23 | ||
| 235 | #define reg_ser_r_stat_din___tr_empty___width 1 | ||
| 236 | #define reg_ser_r_stat_din___tr_empty___bit 23 | ||
| 237 | #define reg_ser_r_stat_din___tr_rdy___lsb 24 | ||
| 238 | #define reg_ser_r_stat_din___tr_rdy___width 1 | ||
| 239 | #define reg_ser_r_stat_din___tr_rdy___bit 24 | ||
| 240 | #define reg_ser_r_stat_din___cts_n___lsb 25 | ||
| 241 | #define reg_ser_r_stat_din___cts_n___width 1 | ||
| 242 | #define reg_ser_r_stat_din___cts_n___bit 25 | ||
| 243 | #define reg_ser_r_stat_din___xoff_detect___lsb 26 | ||
| 244 | #define reg_ser_r_stat_din___xoff_detect___width 1 | ||
| 245 | #define reg_ser_r_stat_din___xoff_detect___bit 26 | ||
| 246 | #define reg_ser_r_stat_din___rts_n___lsb 27 | ||
| 247 | #define reg_ser_r_stat_din___rts_n___width 1 | ||
| 248 | #define reg_ser_r_stat_din___rts_n___bit 27 | ||
| 249 | #define reg_ser_r_stat_din___txd___lsb 28 | ||
| 250 | #define reg_ser_r_stat_din___txd___width 1 | ||
| 251 | #define reg_ser_r_stat_din___txd___bit 28 | ||
| 252 | #define reg_ser_r_stat_din_offset 36 | ||
| 253 | |||
| 254 | /* Register rw_rec_eop, scope ser, type rw */ | ||
| 255 | #define reg_ser_rw_rec_eop___set___lsb 0 | ||
| 256 | #define reg_ser_rw_rec_eop___set___width 1 | ||
| 257 | #define reg_ser_rw_rec_eop___set___bit 0 | ||
| 258 | #define reg_ser_rw_rec_eop_offset 40 | ||
| 259 | |||
| 260 | /* Register rw_intr_mask, scope ser, type rw */ | ||
| 261 | #define reg_ser_rw_intr_mask___tr_rdy___lsb 0 | ||
| 262 | #define reg_ser_rw_intr_mask___tr_rdy___width 1 | ||
| 263 | #define reg_ser_rw_intr_mask___tr_rdy___bit 0 | ||
| 264 | #define reg_ser_rw_intr_mask___tr_empty___lsb 1 | ||
| 265 | #define reg_ser_rw_intr_mask___tr_empty___width 1 | ||
| 266 | #define reg_ser_rw_intr_mask___tr_empty___bit 1 | ||
| 267 | #define reg_ser_rw_intr_mask___tr_idle___lsb 2 | ||
| 268 | #define reg_ser_rw_intr_mask___tr_idle___width 1 | ||
| 269 | #define reg_ser_rw_intr_mask___tr_idle___bit 2 | ||
| 270 | #define reg_ser_rw_intr_mask___dav___lsb 3 | ||
| 271 | #define reg_ser_rw_intr_mask___dav___width 1 | ||
| 272 | #define reg_ser_rw_intr_mask___dav___bit 3 | ||
| 273 | #define reg_ser_rw_intr_mask_offset 44 | ||
| 274 | |||
| 275 | /* Register rw_ack_intr, scope ser, type rw */ | ||
| 276 | #define reg_ser_rw_ack_intr___tr_rdy___lsb 0 | ||
| 277 | #define reg_ser_rw_ack_intr___tr_rdy___width 1 | ||
| 278 | #define reg_ser_rw_ack_intr___tr_rdy___bit 0 | ||
| 279 | #define reg_ser_rw_ack_intr___tr_empty___lsb 1 | ||
| 280 | #define reg_ser_rw_ack_intr___tr_empty___width 1 | ||
| 281 | #define reg_ser_rw_ack_intr___tr_empty___bit 1 | ||
| 282 | #define reg_ser_rw_ack_intr___tr_idle___lsb 2 | ||
| 283 | #define reg_ser_rw_ack_intr___tr_idle___width 1 | ||
| 284 | #define reg_ser_rw_ack_intr___tr_idle___bit 2 | ||
| 285 | #define reg_ser_rw_ack_intr___dav___lsb 3 | ||
| 286 | #define reg_ser_rw_ack_intr___dav___width 1 | ||
| 287 | #define reg_ser_rw_ack_intr___dav___bit 3 | ||
| 288 | #define reg_ser_rw_ack_intr_offset 48 | ||
| 289 | |||
| 290 | /* Register r_intr, scope ser, type r */ | ||
| 291 | #define reg_ser_r_intr___tr_rdy___lsb 0 | ||
| 292 | #define reg_ser_r_intr___tr_rdy___width 1 | ||
| 293 | #define reg_ser_r_intr___tr_rdy___bit 0 | ||
| 294 | #define reg_ser_r_intr___tr_empty___lsb 1 | ||
| 295 | #define reg_ser_r_intr___tr_empty___width 1 | ||
| 296 | #define reg_ser_r_intr___tr_empty___bit 1 | ||
| 297 | #define reg_ser_r_intr___tr_idle___lsb 2 | ||
| 298 | #define reg_ser_r_intr___tr_idle___width 1 | ||
| 299 | #define reg_ser_r_intr___tr_idle___bit 2 | ||
| 300 | #define reg_ser_r_intr___dav___lsb 3 | ||
| 301 | #define reg_ser_r_intr___dav___width 1 | ||
| 302 | #define reg_ser_r_intr___dav___bit 3 | ||
| 303 | #define reg_ser_r_intr_offset 52 | ||
| 304 | |||
| 305 | /* Register r_masked_intr, scope ser, type r */ | ||
| 306 | #define reg_ser_r_masked_intr___tr_rdy___lsb 0 | ||
| 307 | #define reg_ser_r_masked_intr___tr_rdy___width 1 | ||
| 308 | #define reg_ser_r_masked_intr___tr_rdy___bit 0 | ||
| 309 | #define reg_ser_r_masked_intr___tr_empty___lsb 1 | ||
| 310 | #define reg_ser_r_masked_intr___tr_empty___width 1 | ||
| 311 | #define reg_ser_r_masked_intr___tr_empty___bit 1 | ||
| 312 | #define reg_ser_r_masked_intr___tr_idle___lsb 2 | ||
| 313 | #define reg_ser_r_masked_intr___tr_idle___width 1 | ||
| 314 | #define reg_ser_r_masked_intr___tr_idle___bit 2 | ||
| 315 | #define reg_ser_r_masked_intr___dav___lsb 3 | ||
| 316 | #define reg_ser_r_masked_intr___dav___width 1 | ||
| 317 | #define reg_ser_r_masked_intr___dav___bit 3 | ||
| 318 | #define reg_ser_r_masked_intr_offset 56 | ||
| 319 | |||
| 320 | |||
| 321 | /* Constants */ | ||
| 322 | #define regk_ser_active 0x00000000 | ||
| 323 | #define regk_ser_bits1 0x00000000 | ||
| 324 | #define regk_ser_bits2 0x00000001 | ||
| 325 | #define regk_ser_bits7 0x00000001 | ||
| 326 | #define regk_ser_bits8 0x00000000 | ||
| 327 | #define regk_ser_del0_5 0x00000000 | ||
| 328 | #define regk_ser_del1 0x00000001 | ||
| 329 | #define regk_ser_del1_5 0x00000002 | ||
| 330 | #define regk_ser_del2 0x00000003 | ||
| 331 | #define regk_ser_del2_5 0x00000004 | ||
| 332 | #define regk_ser_del3 0x00000005 | ||
| 333 | #define regk_ser_del3_5 0x00000006 | ||
| 334 | #define regk_ser_del4 0x00000007 | ||
| 335 | #define regk_ser_even 0x00000000 | ||
| 336 | #define regk_ser_ext 0x00000001 | ||
| 337 | #define regk_ser_f100 0x00000007 | ||
| 338 | #define regk_ser_f29_493 0x00000004 | ||
| 339 | #define regk_ser_f32 0x00000005 | ||
| 340 | #define regk_ser_f32_768 0x00000006 | ||
| 341 | #define regk_ser_ignore 0x00000001 | ||
| 342 | #define regk_ser_inactive 0x00000001 | ||
| 343 | #define regk_ser_majority 0x00000001 | ||
| 344 | #define regk_ser_mark 0x00000002 | ||
| 345 | #define regk_ser_middle 0x00000000 | ||
| 346 | #define regk_ser_no 0x00000000 | ||
| 347 | #define regk_ser_odd 0x00000001 | ||
| 348 | #define regk_ser_off 0x00000000 | ||
| 349 | #define regk_ser_rw_intr_mask_default 0x00000000 | ||
| 350 | #define regk_ser_rw_rec_baud_div_default 0x00000000 | ||
| 351 | #define regk_ser_rw_rec_ctrl_default 0x00010000 | ||
| 352 | #define regk_ser_rw_tr_baud_div_default 0x00000000 | ||
| 353 | #define regk_ser_rw_tr_ctrl_default 0x00008000 | ||
| 354 | #define regk_ser_rw_tr_dma_en_default 0x00000000 | ||
| 355 | #define regk_ser_rw_xoff_default 0x00000000 | ||
| 356 | #define regk_ser_space 0x00000003 | ||
| 357 | #define regk_ser_stop 0x00000000 | ||
| 358 | #define regk_ser_yes 0x00000001 | ||
| 359 | #endif /* __ser_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h deleted file mode 100644 index 27d4d91b3abd..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h +++ /dev/null | |||
| @@ -1,462 +0,0 @@ | |||
| 1 | #ifndef __sser_defs_asm_h | ||
| 2 | #define __sser_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/syncser/rtl/sser_regs.r | ||
| 7 | * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:48 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r | ||
| 11 | * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope sser, type rw */ | ||
| 57 | #define reg_sser_rw_cfg___clk_div___lsb 0 | ||
| 58 | #define reg_sser_rw_cfg___clk_div___width 16 | ||
| 59 | #define reg_sser_rw_cfg___base_freq___lsb 16 | ||
| 60 | #define reg_sser_rw_cfg___base_freq___width 3 | ||
| 61 | #define reg_sser_rw_cfg___gate_clk___lsb 19 | ||
| 62 | #define reg_sser_rw_cfg___gate_clk___width 1 | ||
| 63 | #define reg_sser_rw_cfg___gate_clk___bit 19 | ||
| 64 | #define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 | ||
| 65 | #define reg_sser_rw_cfg___clkgate_ctrl___width 1 | ||
| 66 | #define reg_sser_rw_cfg___clkgate_ctrl___bit 20 | ||
| 67 | #define reg_sser_rw_cfg___clkgate_in___lsb 21 | ||
| 68 | #define reg_sser_rw_cfg___clkgate_in___width 1 | ||
| 69 | #define reg_sser_rw_cfg___clkgate_in___bit 21 | ||
| 70 | #define reg_sser_rw_cfg___clk_dir___lsb 22 | ||
| 71 | #define reg_sser_rw_cfg___clk_dir___width 1 | ||
| 72 | #define reg_sser_rw_cfg___clk_dir___bit 22 | ||
| 73 | #define reg_sser_rw_cfg___clk_od_mode___lsb 23 | ||
| 74 | #define reg_sser_rw_cfg___clk_od_mode___width 1 | ||
| 75 | #define reg_sser_rw_cfg___clk_od_mode___bit 23 | ||
| 76 | #define reg_sser_rw_cfg___out_clk_pol___lsb 24 | ||
| 77 | #define reg_sser_rw_cfg___out_clk_pol___width 1 | ||
| 78 | #define reg_sser_rw_cfg___out_clk_pol___bit 24 | ||
| 79 | #define reg_sser_rw_cfg___out_clk_src___lsb 25 | ||
| 80 | #define reg_sser_rw_cfg___out_clk_src___width 2 | ||
| 81 | #define reg_sser_rw_cfg___clk_in_sel___lsb 27 | ||
| 82 | #define reg_sser_rw_cfg___clk_in_sel___width 1 | ||
| 83 | #define reg_sser_rw_cfg___clk_in_sel___bit 27 | ||
| 84 | #define reg_sser_rw_cfg___hold_pol___lsb 28 | ||
| 85 | #define reg_sser_rw_cfg___hold_pol___width 1 | ||
| 86 | #define reg_sser_rw_cfg___hold_pol___bit 28 | ||
| 87 | #define reg_sser_rw_cfg___prepare___lsb 29 | ||
| 88 | #define reg_sser_rw_cfg___prepare___width 1 | ||
| 89 | #define reg_sser_rw_cfg___prepare___bit 29 | ||
| 90 | #define reg_sser_rw_cfg___en___lsb 30 | ||
| 91 | #define reg_sser_rw_cfg___en___width 1 | ||
| 92 | #define reg_sser_rw_cfg___en___bit 30 | ||
| 93 | #define reg_sser_rw_cfg_offset 0 | ||
| 94 | |||
| 95 | /* Register rw_frm_cfg, scope sser, type rw */ | ||
| 96 | #define reg_sser_rw_frm_cfg___wordrate___lsb 0 | ||
| 97 | #define reg_sser_rw_frm_cfg___wordrate___width 10 | ||
| 98 | #define reg_sser_rw_frm_cfg___rec_delay___lsb 10 | ||
| 99 | #define reg_sser_rw_frm_cfg___rec_delay___width 3 | ||
| 100 | #define reg_sser_rw_frm_cfg___tr_delay___lsb 13 | ||
| 101 | #define reg_sser_rw_frm_cfg___tr_delay___width 3 | ||
| 102 | #define reg_sser_rw_frm_cfg___early_wend___lsb 16 | ||
| 103 | #define reg_sser_rw_frm_cfg___early_wend___width 1 | ||
| 104 | #define reg_sser_rw_frm_cfg___early_wend___bit 16 | ||
| 105 | #define reg_sser_rw_frm_cfg___level___lsb 17 | ||
| 106 | #define reg_sser_rw_frm_cfg___level___width 2 | ||
| 107 | #define reg_sser_rw_frm_cfg___type___lsb 19 | ||
| 108 | #define reg_sser_rw_frm_cfg___type___width 1 | ||
| 109 | #define reg_sser_rw_frm_cfg___type___bit 19 | ||
| 110 | #define reg_sser_rw_frm_cfg___clk_pol___lsb 20 | ||
| 111 | #define reg_sser_rw_frm_cfg___clk_pol___width 1 | ||
| 112 | #define reg_sser_rw_frm_cfg___clk_pol___bit 20 | ||
| 113 | #define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 | ||
| 114 | #define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 | ||
| 115 | #define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 | ||
| 116 | #define reg_sser_rw_frm_cfg___clk_src___lsb 22 | ||
| 117 | #define reg_sser_rw_frm_cfg___clk_src___width 1 | ||
| 118 | #define reg_sser_rw_frm_cfg___clk_src___bit 22 | ||
| 119 | #define reg_sser_rw_frm_cfg___out_off___lsb 23 | ||
| 120 | #define reg_sser_rw_frm_cfg___out_off___width 1 | ||
| 121 | #define reg_sser_rw_frm_cfg___out_off___bit 23 | ||
| 122 | #define reg_sser_rw_frm_cfg___out_on___lsb 24 | ||
| 123 | #define reg_sser_rw_frm_cfg___out_on___width 1 | ||
| 124 | #define reg_sser_rw_frm_cfg___out_on___bit 24 | ||
| 125 | #define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 | ||
| 126 | #define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 | ||
| 127 | #define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 | ||
| 128 | #define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 | ||
| 129 | #define reg_sser_rw_frm_cfg___frame_pin_use___width 2 | ||
| 130 | #define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 | ||
| 131 | #define reg_sser_rw_frm_cfg___status_pin_dir___width 1 | ||
| 132 | #define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 | ||
| 133 | #define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 | ||
| 134 | #define reg_sser_rw_frm_cfg___status_pin_use___width 2 | ||
| 135 | #define reg_sser_rw_frm_cfg_offset 4 | ||
| 136 | |||
| 137 | /* Register rw_tr_cfg, scope sser, type rw */ | ||
| 138 | #define reg_sser_rw_tr_cfg___tr_en___lsb 0 | ||
| 139 | #define reg_sser_rw_tr_cfg___tr_en___width 1 | ||
| 140 | #define reg_sser_rw_tr_cfg___tr_en___bit 0 | ||
| 141 | #define reg_sser_rw_tr_cfg___stop___lsb 1 | ||
| 142 | #define reg_sser_rw_tr_cfg___stop___width 1 | ||
| 143 | #define reg_sser_rw_tr_cfg___stop___bit 1 | ||
| 144 | #define reg_sser_rw_tr_cfg___urun_stop___lsb 2 | ||
| 145 | #define reg_sser_rw_tr_cfg___urun_stop___width 1 | ||
| 146 | #define reg_sser_rw_tr_cfg___urun_stop___bit 2 | ||
| 147 | #define reg_sser_rw_tr_cfg___eop_stop___lsb 3 | ||
| 148 | #define reg_sser_rw_tr_cfg___eop_stop___width 1 | ||
| 149 | #define reg_sser_rw_tr_cfg___eop_stop___bit 3 | ||
| 150 | #define reg_sser_rw_tr_cfg___sample_size___lsb 4 | ||
| 151 | #define reg_sser_rw_tr_cfg___sample_size___width 6 | ||
| 152 | #define reg_sser_rw_tr_cfg___sh_dir___lsb 10 | ||
| 153 | #define reg_sser_rw_tr_cfg___sh_dir___width 1 | ||
| 154 | #define reg_sser_rw_tr_cfg___sh_dir___bit 10 | ||
| 155 | #define reg_sser_rw_tr_cfg___clk_pol___lsb 11 | ||
| 156 | #define reg_sser_rw_tr_cfg___clk_pol___width 1 | ||
| 157 | #define reg_sser_rw_tr_cfg___clk_pol___bit 11 | ||
| 158 | #define reg_sser_rw_tr_cfg___clk_src___lsb 12 | ||
| 159 | #define reg_sser_rw_tr_cfg___clk_src___width 1 | ||
| 160 | #define reg_sser_rw_tr_cfg___clk_src___bit 12 | ||
| 161 | #define reg_sser_rw_tr_cfg___use_dma___lsb 13 | ||
| 162 | #define reg_sser_rw_tr_cfg___use_dma___width 1 | ||
| 163 | #define reg_sser_rw_tr_cfg___use_dma___bit 13 | ||
| 164 | #define reg_sser_rw_tr_cfg___mode___lsb 14 | ||
| 165 | #define reg_sser_rw_tr_cfg___mode___width 2 | ||
| 166 | #define reg_sser_rw_tr_cfg___frm_src___lsb 16 | ||
| 167 | #define reg_sser_rw_tr_cfg___frm_src___width 1 | ||
| 168 | #define reg_sser_rw_tr_cfg___frm_src___bit 16 | ||
| 169 | #define reg_sser_rw_tr_cfg___use60958___lsb 17 | ||
| 170 | #define reg_sser_rw_tr_cfg___use60958___width 1 | ||
| 171 | #define reg_sser_rw_tr_cfg___use60958___bit 17 | ||
| 172 | #define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 | ||
| 173 | #define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 | ||
| 174 | #define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 | ||
| 175 | #define reg_sser_rw_tr_cfg___rate_ctrl___width 1 | ||
| 176 | #define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 | ||
| 177 | #define reg_sser_rw_tr_cfg___use_md___lsb 21 | ||
| 178 | #define reg_sser_rw_tr_cfg___use_md___width 1 | ||
| 179 | #define reg_sser_rw_tr_cfg___use_md___bit 21 | ||
| 180 | #define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 | ||
| 181 | #define reg_sser_rw_tr_cfg___dual_i2s___width 1 | ||
| 182 | #define reg_sser_rw_tr_cfg___dual_i2s___bit 22 | ||
| 183 | #define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 | ||
| 184 | #define reg_sser_rw_tr_cfg___data_pin_use___width 2 | ||
| 185 | #define reg_sser_rw_tr_cfg___od_mode___lsb 25 | ||
| 186 | #define reg_sser_rw_tr_cfg___od_mode___width 1 | ||
| 187 | #define reg_sser_rw_tr_cfg___od_mode___bit 25 | ||
| 188 | #define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 | ||
| 189 | #define reg_sser_rw_tr_cfg___bulk_wspace___width 2 | ||
| 190 | #define reg_sser_rw_tr_cfg_offset 8 | ||
| 191 | |||
| 192 | /* Register rw_rec_cfg, scope sser, type rw */ | ||
| 193 | #define reg_sser_rw_rec_cfg___rec_en___lsb 0 | ||
| 194 | #define reg_sser_rw_rec_cfg___rec_en___width 1 | ||
| 195 | #define reg_sser_rw_rec_cfg___rec_en___bit 0 | ||
| 196 | #define reg_sser_rw_rec_cfg___force_eop___lsb 1 | ||
| 197 | #define reg_sser_rw_rec_cfg___force_eop___width 1 | ||
| 198 | #define reg_sser_rw_rec_cfg___force_eop___bit 1 | ||
| 199 | #define reg_sser_rw_rec_cfg___stop___lsb 2 | ||
| 200 | #define reg_sser_rw_rec_cfg___stop___width 1 | ||
| 201 | #define reg_sser_rw_rec_cfg___stop___bit 2 | ||
| 202 | #define reg_sser_rw_rec_cfg___orun_stop___lsb 3 | ||
| 203 | #define reg_sser_rw_rec_cfg___orun_stop___width 1 | ||
| 204 | #define reg_sser_rw_rec_cfg___orun_stop___bit 3 | ||
| 205 | #define reg_sser_rw_rec_cfg___eop_stop___lsb 4 | ||
| 206 | #define reg_sser_rw_rec_cfg___eop_stop___width 1 | ||
| 207 | #define reg_sser_rw_rec_cfg___eop_stop___bit 4 | ||
| 208 | #define reg_sser_rw_rec_cfg___sample_size___lsb 5 | ||
| 209 | #define reg_sser_rw_rec_cfg___sample_size___width 6 | ||
| 210 | #define reg_sser_rw_rec_cfg___sh_dir___lsb 11 | ||
| 211 | #define reg_sser_rw_rec_cfg___sh_dir___width 1 | ||
| 212 | #define reg_sser_rw_rec_cfg___sh_dir___bit 11 | ||
| 213 | #define reg_sser_rw_rec_cfg___clk_pol___lsb 12 | ||
| 214 | #define reg_sser_rw_rec_cfg___clk_pol___width 1 | ||
| 215 | #define reg_sser_rw_rec_cfg___clk_pol___bit 12 | ||
| 216 | #define reg_sser_rw_rec_cfg___clk_src___lsb 13 | ||
| 217 | #define reg_sser_rw_rec_cfg___clk_src___width 1 | ||
| 218 | #define reg_sser_rw_rec_cfg___clk_src___bit 13 | ||
| 219 | #define reg_sser_rw_rec_cfg___use_dma___lsb 14 | ||
| 220 | #define reg_sser_rw_rec_cfg___use_dma___width 1 | ||
| 221 | #define reg_sser_rw_rec_cfg___use_dma___bit 14 | ||
| 222 | #define reg_sser_rw_rec_cfg___mode___lsb 15 | ||
| 223 | #define reg_sser_rw_rec_cfg___mode___width 2 | ||
| 224 | #define reg_sser_rw_rec_cfg___frm_src___lsb 17 | ||
| 225 | #define reg_sser_rw_rec_cfg___frm_src___width 2 | ||
| 226 | #define reg_sser_rw_rec_cfg___use60958___lsb 19 | ||
| 227 | #define reg_sser_rw_rec_cfg___use60958___width 1 | ||
| 228 | #define reg_sser_rw_rec_cfg___use60958___bit 19 | ||
| 229 | #define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 | ||
| 230 | #define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 | ||
| 231 | #define reg_sser_rw_rec_cfg___slave2_en___lsb 25 | ||
| 232 | #define reg_sser_rw_rec_cfg___slave2_en___width 1 | ||
| 233 | #define reg_sser_rw_rec_cfg___slave2_en___bit 25 | ||
| 234 | #define reg_sser_rw_rec_cfg___slave3_en___lsb 26 | ||
| 235 | #define reg_sser_rw_rec_cfg___slave3_en___width 1 | ||
| 236 | #define reg_sser_rw_rec_cfg___slave3_en___bit 26 | ||
| 237 | #define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 | ||
| 238 | #define reg_sser_rw_rec_cfg___fifo_thr___width 2 | ||
| 239 | #define reg_sser_rw_rec_cfg_offset 12 | ||
| 240 | |||
| 241 | /* Register rw_tr_data, scope sser, type rw */ | ||
| 242 | #define reg_sser_rw_tr_data___data___lsb 0 | ||
| 243 | #define reg_sser_rw_tr_data___data___width 16 | ||
| 244 | #define reg_sser_rw_tr_data___md___lsb 16 | ||
| 245 | #define reg_sser_rw_tr_data___md___width 1 | ||
| 246 | #define reg_sser_rw_tr_data___md___bit 16 | ||
| 247 | #define reg_sser_rw_tr_data_offset 16 | ||
| 248 | |||
| 249 | /* Register r_rec_data, scope sser, type r */ | ||
| 250 | #define reg_sser_r_rec_data___data___lsb 0 | ||
| 251 | #define reg_sser_r_rec_data___data___width 16 | ||
| 252 | #define reg_sser_r_rec_data___md___lsb 16 | ||
| 253 | #define reg_sser_r_rec_data___md___width 1 | ||
| 254 | #define reg_sser_r_rec_data___md___bit 16 | ||
| 255 | #define reg_sser_r_rec_data___ext_clk___lsb 17 | ||
| 256 | #define reg_sser_r_rec_data___ext_clk___width 1 | ||
| 257 | #define reg_sser_r_rec_data___ext_clk___bit 17 | ||
| 258 | #define reg_sser_r_rec_data___status_in___lsb 18 | ||
| 259 | #define reg_sser_r_rec_data___status_in___width 1 | ||
| 260 | #define reg_sser_r_rec_data___status_in___bit 18 | ||
| 261 | #define reg_sser_r_rec_data___frame_in___lsb 19 | ||
| 262 | #define reg_sser_r_rec_data___frame_in___width 1 | ||
| 263 | #define reg_sser_r_rec_data___frame_in___bit 19 | ||
| 264 | #define reg_sser_r_rec_data___din___lsb 20 | ||
| 265 | #define reg_sser_r_rec_data___din___width 1 | ||
| 266 | #define reg_sser_r_rec_data___din___bit 20 | ||
| 267 | #define reg_sser_r_rec_data___data_in___lsb 21 | ||
| 268 | #define reg_sser_r_rec_data___data_in___width 1 | ||
| 269 | #define reg_sser_r_rec_data___data_in___bit 21 | ||
| 270 | #define reg_sser_r_rec_data___clk_in___lsb 22 | ||
| 271 | #define reg_sser_r_rec_data___clk_in___width 1 | ||
| 272 | #define reg_sser_r_rec_data___clk_in___bit 22 | ||
| 273 | #define reg_sser_r_rec_data_offset 20 | ||
| 274 | |||
| 275 | /* Register rw_extra, scope sser, type rw */ | ||
| 276 | #define reg_sser_rw_extra___clkoff_cycles___lsb 0 | ||
| 277 | #define reg_sser_rw_extra___clkoff_cycles___width 20 | ||
| 278 | #define reg_sser_rw_extra___clkoff_en___lsb 20 | ||
| 279 | #define reg_sser_rw_extra___clkoff_en___width 1 | ||
| 280 | #define reg_sser_rw_extra___clkoff_en___bit 20 | ||
| 281 | #define reg_sser_rw_extra___clkon_en___lsb 21 | ||
| 282 | #define reg_sser_rw_extra___clkon_en___width 1 | ||
| 283 | #define reg_sser_rw_extra___clkon_en___bit 21 | ||
| 284 | #define reg_sser_rw_extra___dout_delay___lsb 22 | ||
| 285 | #define reg_sser_rw_extra___dout_delay___width 5 | ||
| 286 | #define reg_sser_rw_extra_offset 24 | ||
| 287 | |||
| 288 | /* Register rw_intr_mask, scope sser, type rw */ | ||
| 289 | #define reg_sser_rw_intr_mask___trdy___lsb 0 | ||
| 290 | #define reg_sser_rw_intr_mask___trdy___width 1 | ||
| 291 | #define reg_sser_rw_intr_mask___trdy___bit 0 | ||
| 292 | #define reg_sser_rw_intr_mask___rdav___lsb 1 | ||
| 293 | #define reg_sser_rw_intr_mask___rdav___width 1 | ||
| 294 | #define reg_sser_rw_intr_mask___rdav___bit 1 | ||
| 295 | #define reg_sser_rw_intr_mask___tidle___lsb 2 | ||
| 296 | #define reg_sser_rw_intr_mask___tidle___width 1 | ||
| 297 | #define reg_sser_rw_intr_mask___tidle___bit 2 | ||
| 298 | #define reg_sser_rw_intr_mask___rstop___lsb 3 | ||
| 299 | #define reg_sser_rw_intr_mask___rstop___width 1 | ||
| 300 | #define reg_sser_rw_intr_mask___rstop___bit 3 | ||
| 301 | #define reg_sser_rw_intr_mask___urun___lsb 4 | ||
| 302 | #define reg_sser_rw_intr_mask___urun___width 1 | ||
| 303 | #define reg_sser_rw_intr_mask___urun___bit 4 | ||
| 304 | #define reg_sser_rw_intr_mask___orun___lsb 5 | ||
| 305 | #define reg_sser_rw_intr_mask___orun___width 1 | ||
| 306 | #define reg_sser_rw_intr_mask___orun___bit 5 | ||
| 307 | #define reg_sser_rw_intr_mask___md_rec___lsb 6 | ||
| 308 | #define reg_sser_rw_intr_mask___md_rec___width 1 | ||
| 309 | #define reg_sser_rw_intr_mask___md_rec___bit 6 | ||
| 310 | #define reg_sser_rw_intr_mask___md_sent___lsb 7 | ||
| 311 | #define reg_sser_rw_intr_mask___md_sent___width 1 | ||
| 312 | #define reg_sser_rw_intr_mask___md_sent___bit 7 | ||
| 313 | #define reg_sser_rw_intr_mask___r958err___lsb 8 | ||
| 314 | #define reg_sser_rw_intr_mask___r958err___width 1 | ||
| 315 | #define reg_sser_rw_intr_mask___r958err___bit 8 | ||
| 316 | #define reg_sser_rw_intr_mask_offset 28 | ||
| 317 | |||
| 318 | /* Register rw_ack_intr, scope sser, type rw */ | ||
| 319 | #define reg_sser_rw_ack_intr___trdy___lsb 0 | ||
| 320 | #define reg_sser_rw_ack_intr___trdy___width 1 | ||
| 321 | #define reg_sser_rw_ack_intr___trdy___bit 0 | ||
| 322 | #define reg_sser_rw_ack_intr___rdav___lsb 1 | ||
| 323 | #define reg_sser_rw_ack_intr___rdav___width 1 | ||
| 324 | #define reg_sser_rw_ack_intr___rdav___bit 1 | ||
| 325 | #define reg_sser_rw_ack_intr___tidle___lsb 2 | ||
| 326 | #define reg_sser_rw_ack_intr___tidle___width 1 | ||
| 327 | #define reg_sser_rw_ack_intr___tidle___bit 2 | ||
| 328 | #define reg_sser_rw_ack_intr___rstop___lsb 3 | ||
| 329 | #define reg_sser_rw_ack_intr___rstop___width 1 | ||
| 330 | #define reg_sser_rw_ack_intr___rstop___bit 3 | ||
| 331 | #define reg_sser_rw_ack_intr___urun___lsb 4 | ||
| 332 | #define reg_sser_rw_ack_intr___urun___width 1 | ||
| 333 | #define reg_sser_rw_ack_intr___urun___bit 4 | ||
| 334 | #define reg_sser_rw_ack_intr___orun___lsb 5 | ||
| 335 | #define reg_sser_rw_ack_intr___orun___width 1 | ||
| 336 | #define reg_sser_rw_ack_intr___orun___bit 5 | ||
| 337 | #define reg_sser_rw_ack_intr___md_rec___lsb 6 | ||
| 338 | #define reg_sser_rw_ack_intr___md_rec___width 1 | ||
| 339 | #define reg_sser_rw_ack_intr___md_rec___bit 6 | ||
| 340 | #define reg_sser_rw_ack_intr___md_sent___lsb 7 | ||
| 341 | #define reg_sser_rw_ack_intr___md_sent___width 1 | ||
| 342 | #define reg_sser_rw_ack_intr___md_sent___bit 7 | ||
| 343 | #define reg_sser_rw_ack_intr___r958err___lsb 8 | ||
| 344 | #define reg_sser_rw_ack_intr___r958err___width 1 | ||
| 345 | #define reg_sser_rw_ack_intr___r958err___bit 8 | ||
| 346 | #define reg_sser_rw_ack_intr_offset 32 | ||
| 347 | |||
| 348 | /* Register r_intr, scope sser, type r */ | ||
| 349 | #define reg_sser_r_intr___trdy___lsb 0 | ||
| 350 | #define reg_sser_r_intr___trdy___width 1 | ||
| 351 | #define reg_sser_r_intr___trdy___bit 0 | ||
| 352 | #define reg_sser_r_intr___rdav___lsb 1 | ||
| 353 | #define reg_sser_r_intr___rdav___width 1 | ||
| 354 | #define reg_sser_r_intr___rdav___bit 1 | ||
| 355 | #define reg_sser_r_intr___tidle___lsb 2 | ||
| 356 | #define reg_sser_r_intr___tidle___width 1 | ||
| 357 | #define reg_sser_r_intr___tidle___bit 2 | ||
| 358 | #define reg_sser_r_intr___rstop___lsb 3 | ||
| 359 | #define reg_sser_r_intr___rstop___width 1 | ||
| 360 | #define reg_sser_r_intr___rstop___bit 3 | ||
| 361 | #define reg_sser_r_intr___urun___lsb 4 | ||
| 362 | #define reg_sser_r_intr___urun___width 1 | ||
| 363 | #define reg_sser_r_intr___urun___bit 4 | ||
| 364 | #define reg_sser_r_intr___orun___lsb 5 | ||
| 365 | #define reg_sser_r_intr___orun___width 1 | ||
| 366 | #define reg_sser_r_intr___orun___bit 5 | ||
| 367 | #define reg_sser_r_intr___md_rec___lsb 6 | ||
| 368 | #define reg_sser_r_intr___md_rec___width 1 | ||
| 369 | #define reg_sser_r_intr___md_rec___bit 6 | ||
| 370 | #define reg_sser_r_intr___md_sent___lsb 7 | ||
| 371 | #define reg_sser_r_intr___md_sent___width 1 | ||
| 372 | #define reg_sser_r_intr___md_sent___bit 7 | ||
| 373 | #define reg_sser_r_intr___r958err___lsb 8 | ||
| 374 | #define reg_sser_r_intr___r958err___width 1 | ||
| 375 | #define reg_sser_r_intr___r958err___bit 8 | ||
| 376 | #define reg_sser_r_intr_offset 36 | ||
| 377 | |||
| 378 | /* Register r_masked_intr, scope sser, type r */ | ||
| 379 | #define reg_sser_r_masked_intr___trdy___lsb 0 | ||
| 380 | #define reg_sser_r_masked_intr___trdy___width 1 | ||
| 381 | #define reg_sser_r_masked_intr___trdy___bit 0 | ||
| 382 | #define reg_sser_r_masked_intr___rdav___lsb 1 | ||
| 383 | #define reg_sser_r_masked_intr___rdav___width 1 | ||
| 384 | #define reg_sser_r_masked_intr___rdav___bit 1 | ||
| 385 | #define reg_sser_r_masked_intr___tidle___lsb 2 | ||
| 386 | #define reg_sser_r_masked_intr___tidle___width 1 | ||
| 387 | #define reg_sser_r_masked_intr___tidle___bit 2 | ||
| 388 | #define reg_sser_r_masked_intr___rstop___lsb 3 | ||
| 389 | #define reg_sser_r_masked_intr___rstop___width 1 | ||
| 390 | #define reg_sser_r_masked_intr___rstop___bit 3 | ||
| 391 | #define reg_sser_r_masked_intr___urun___lsb 4 | ||
| 392 | #define reg_sser_r_masked_intr___urun___width 1 | ||
| 393 | #define reg_sser_r_masked_intr___urun___bit 4 | ||
| 394 | #define reg_sser_r_masked_intr___orun___lsb 5 | ||
| 395 | #define reg_sser_r_masked_intr___orun___width 1 | ||
| 396 | #define reg_sser_r_masked_intr___orun___bit 5 | ||
| 397 | #define reg_sser_r_masked_intr___md_rec___lsb 6 | ||
| 398 | #define reg_sser_r_masked_intr___md_rec___width 1 | ||
| 399 | #define reg_sser_r_masked_intr___md_rec___bit 6 | ||
| 400 | #define reg_sser_r_masked_intr___md_sent___lsb 7 | ||
| 401 | #define reg_sser_r_masked_intr___md_sent___width 1 | ||
| 402 | #define reg_sser_r_masked_intr___md_sent___bit 7 | ||
| 403 | #define reg_sser_r_masked_intr___r958err___lsb 8 | ||
| 404 | #define reg_sser_r_masked_intr___r958err___width 1 | ||
| 405 | #define reg_sser_r_masked_intr___r958err___bit 8 | ||
| 406 | #define reg_sser_r_masked_intr_offset 40 | ||
| 407 | |||
| 408 | |||
| 409 | /* Constants */ | ||
| 410 | #define regk_sser_both 0x00000002 | ||
| 411 | #define regk_sser_bulk 0x00000001 | ||
| 412 | #define regk_sser_clk100 0x00000000 | ||
| 413 | #define regk_sser_clk_in 0x00000000 | ||
| 414 | #define regk_sser_const0 0x00000003 | ||
| 415 | #define regk_sser_dout 0x00000002 | ||
| 416 | #define regk_sser_edge 0x00000000 | ||
| 417 | #define regk_sser_ext 0x00000001 | ||
| 418 | #define regk_sser_ext_clk 0x00000001 | ||
| 419 | #define regk_sser_f100 0x00000000 | ||
| 420 | #define regk_sser_f29_493 0x00000004 | ||
| 421 | #define regk_sser_f32 0x00000005 | ||
| 422 | #define regk_sser_f32_768 0x00000006 | ||
| 423 | #define regk_sser_frm 0x00000003 | ||
| 424 | #define regk_sser_gio0 0x00000000 | ||
| 425 | #define regk_sser_gio1 0x00000001 | ||
| 426 | #define regk_sser_hispeed 0x00000001 | ||
| 427 | #define regk_sser_hold 0x00000002 | ||
| 428 | #define regk_sser_in 0x00000000 | ||
| 429 | #define regk_sser_inf 0x00000003 | ||
| 430 | #define regk_sser_intern 0x00000000 | ||
| 431 | #define regk_sser_intern_clk 0x00000001 | ||
| 432 | #define regk_sser_intern_tb 0x00000000 | ||
| 433 | #define regk_sser_iso 0x00000000 | ||
| 434 | #define regk_sser_level 0x00000001 | ||
| 435 | #define regk_sser_lospeed 0x00000000 | ||
| 436 | #define regk_sser_lsbfirst 0x00000000 | ||
| 437 | #define regk_sser_msbfirst 0x00000001 | ||
| 438 | #define regk_sser_neg 0x00000001 | ||
| 439 | #define regk_sser_neg_lo 0x00000000 | ||
| 440 | #define regk_sser_no 0x00000000 | ||
| 441 | #define regk_sser_no_clk 0x00000007 | ||
| 442 | #define regk_sser_nojitter 0x00000002 | ||
| 443 | #define regk_sser_out 0x00000001 | ||
| 444 | #define regk_sser_pos 0x00000000 | ||
| 445 | #define regk_sser_pos_hi 0x00000001 | ||
| 446 | #define regk_sser_rec 0x00000000 | ||
| 447 | #define regk_sser_rw_cfg_default 0x00000000 | ||
| 448 | #define regk_sser_rw_extra_default 0x00000000 | ||
| 449 | #define regk_sser_rw_frm_cfg_default 0x00000000 | ||
| 450 | #define regk_sser_rw_intr_mask_default 0x00000000 | ||
| 451 | #define regk_sser_rw_rec_cfg_default 0x00000000 | ||
| 452 | #define regk_sser_rw_tr_cfg_default 0x01800000 | ||
| 453 | #define regk_sser_rw_tr_data_default 0x00000000 | ||
| 454 | #define regk_sser_thr16 0x00000001 | ||
| 455 | #define regk_sser_thr32 0x00000002 | ||
| 456 | #define regk_sser_thr8 0x00000000 | ||
| 457 | #define regk_sser_tr 0x00000001 | ||
| 458 | #define regk_sser_ts_out 0x00000003 | ||
| 459 | #define regk_sser_tx_bulk 0x00000002 | ||
| 460 | #define regk_sser_wiresave 0x00000002 | ||
| 461 | #define regk_sser_yes 0x00000001 | ||
| 462 | #endif /* __sser_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h deleted file mode 100644 index 55083e6aec93..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h +++ /dev/null | |||
| @@ -1,84 +0,0 @@ | |||
| 1 | #ifndef __strcop_defs_asm_h | ||
| 2 | #define __strcop_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/strcop/rtl/strcop_regs.r | ||
| 7 | * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:38 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r | ||
| 11 | * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope strcop, type rw */ | ||
| 57 | #define reg_strcop_rw_cfg___td3___lsb 0 | ||
| 58 | #define reg_strcop_rw_cfg___td3___width 1 | ||
| 59 | #define reg_strcop_rw_cfg___td3___bit 0 | ||
| 60 | #define reg_strcop_rw_cfg___td2___lsb 1 | ||
| 61 | #define reg_strcop_rw_cfg___td2___width 1 | ||
| 62 | #define reg_strcop_rw_cfg___td2___bit 1 | ||
| 63 | #define reg_strcop_rw_cfg___td1___lsb 2 | ||
| 64 | #define reg_strcop_rw_cfg___td1___width 1 | ||
| 65 | #define reg_strcop_rw_cfg___td1___bit 2 | ||
| 66 | #define reg_strcop_rw_cfg___ipend___lsb 3 | ||
| 67 | #define reg_strcop_rw_cfg___ipend___width 1 | ||
| 68 | #define reg_strcop_rw_cfg___ipend___bit 3 | ||
| 69 | #define reg_strcop_rw_cfg___ignore_sync___lsb 4 | ||
| 70 | #define reg_strcop_rw_cfg___ignore_sync___width 1 | ||
| 71 | #define reg_strcop_rw_cfg___ignore_sync___bit 4 | ||
| 72 | #define reg_strcop_rw_cfg___en___lsb 5 | ||
| 73 | #define reg_strcop_rw_cfg___en___width 1 | ||
| 74 | #define reg_strcop_rw_cfg___en___bit 5 | ||
| 75 | #define reg_strcop_rw_cfg_offset 0 | ||
| 76 | |||
| 77 | |||
| 78 | /* Constants */ | ||
| 79 | #define regk_strcop_big 0x00000001 | ||
| 80 | #define regk_strcop_d 0x00000001 | ||
| 81 | #define regk_strcop_e 0x00000000 | ||
| 82 | #define regk_strcop_little 0x00000000 | ||
| 83 | #define regk_strcop_rw_cfg_default 0x00000002 | ||
| 84 | #endif /* __strcop_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h deleted file mode 100644 index 69b299920f71..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h +++ /dev/null | |||
| @@ -1,100 +0,0 @@ | |||
| 1 | #ifndef __strmux_defs_asm_h | ||
| 2 | #define __strmux_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/strmux/rtl/guinness/strmux_regs.r | ||
| 7 | * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:43 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r | ||
| 11 | * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope strmux, type rw */ | ||
| 57 | #define reg_strmux_rw_cfg___dma0___lsb 0 | ||
| 58 | #define reg_strmux_rw_cfg___dma0___width 3 | ||
| 59 | #define reg_strmux_rw_cfg___dma1___lsb 3 | ||
| 60 | #define reg_strmux_rw_cfg___dma1___width 3 | ||
| 61 | #define reg_strmux_rw_cfg___dma2___lsb 6 | ||
| 62 | #define reg_strmux_rw_cfg___dma2___width 3 | ||
| 63 | #define reg_strmux_rw_cfg___dma3___lsb 9 | ||
| 64 | #define reg_strmux_rw_cfg___dma3___width 3 | ||
| 65 | #define reg_strmux_rw_cfg___dma4___lsb 12 | ||
| 66 | #define reg_strmux_rw_cfg___dma4___width 3 | ||
| 67 | #define reg_strmux_rw_cfg___dma5___lsb 15 | ||
| 68 | #define reg_strmux_rw_cfg___dma5___width 3 | ||
| 69 | #define reg_strmux_rw_cfg___dma6___lsb 18 | ||
| 70 | #define reg_strmux_rw_cfg___dma6___width 3 | ||
| 71 | #define reg_strmux_rw_cfg___dma7___lsb 21 | ||
| 72 | #define reg_strmux_rw_cfg___dma7___width 3 | ||
| 73 | #define reg_strmux_rw_cfg___dma8___lsb 24 | ||
| 74 | #define reg_strmux_rw_cfg___dma8___width 3 | ||
| 75 | #define reg_strmux_rw_cfg___dma9___lsb 27 | ||
| 76 | #define reg_strmux_rw_cfg___dma9___width 3 | ||
| 77 | #define reg_strmux_rw_cfg_offset 0 | ||
| 78 | |||
| 79 | |||
| 80 | /* Constants */ | ||
| 81 | #define regk_strmux_ata 0x00000003 | ||
| 82 | #define regk_strmux_eth0 0x00000001 | ||
| 83 | #define regk_strmux_eth1 0x00000004 | ||
| 84 | #define regk_strmux_ext0 0x00000001 | ||
| 85 | #define regk_strmux_ext1 0x00000001 | ||
| 86 | #define regk_strmux_ext2 0x00000001 | ||
| 87 | #define regk_strmux_ext3 0x00000001 | ||
| 88 | #define regk_strmux_iop0 0x00000002 | ||
| 89 | #define regk_strmux_iop1 0x00000001 | ||
| 90 | #define regk_strmux_off 0x00000000 | ||
| 91 | #define regk_strmux_p21 0x00000004 | ||
| 92 | #define regk_strmux_rw_cfg_default 0x00000000 | ||
| 93 | #define regk_strmux_ser0 0x00000002 | ||
| 94 | #define regk_strmux_ser1 0x00000002 | ||
| 95 | #define regk_strmux_ser2 0x00000004 | ||
| 96 | #define regk_strmux_ser3 0x00000003 | ||
| 97 | #define regk_strmux_sser0 0x00000003 | ||
| 98 | #define regk_strmux_sser1 0x00000003 | ||
| 99 | #define regk_strmux_strcop 0x00000002 | ||
| 100 | #endif /* __strmux_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index 43146021fc16..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h +++ /dev/null | |||
| @@ -1,229 +0,0 @@ | |||
| 1 | #ifndef __timer_defs_asm_h | ||
| 2 | #define __timer_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/timer/rtl/timer_regs.r | ||
| 7 | * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:53 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r | ||
| 11 | * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_tmr0_div, scope timer, type rw */ | ||
| 57 | #define reg_timer_rw_tmr0_div_offset 0 | ||
| 58 | |||
| 59 | /* Register r_tmr0_data, scope timer, type r */ | ||
| 60 | #define reg_timer_r_tmr0_data_offset 4 | ||
| 61 | |||
| 62 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | ||
| 63 | #define reg_timer_rw_tmr0_ctrl___op___lsb 0 | ||
| 64 | #define reg_timer_rw_tmr0_ctrl___op___width 2 | ||
| 65 | #define reg_timer_rw_tmr0_ctrl___freq___lsb 2 | ||
| 66 | #define reg_timer_rw_tmr0_ctrl___freq___width 3 | ||
| 67 | #define reg_timer_rw_tmr0_ctrl_offset 8 | ||
| 68 | |||
| 69 | /* Register rw_tmr1_div, scope timer, type rw */ | ||
| 70 | #define reg_timer_rw_tmr1_div_offset 16 | ||
| 71 | |||
| 72 | /* Register r_tmr1_data, scope timer, type r */ | ||
| 73 | #define reg_timer_r_tmr1_data_offset 20 | ||
| 74 | |||
| 75 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | ||
| 76 | #define reg_timer_rw_tmr1_ctrl___op___lsb 0 | ||
| 77 | #define reg_timer_rw_tmr1_ctrl___op___width 2 | ||
| 78 | #define reg_timer_rw_tmr1_ctrl___freq___lsb 2 | ||
| 79 | #define reg_timer_rw_tmr1_ctrl___freq___width 3 | ||
| 80 | #define reg_timer_rw_tmr1_ctrl_offset 24 | ||
| 81 | |||
| 82 | /* Register rs_cnt_data, scope timer, type rs */ | ||
| 83 | #define reg_timer_rs_cnt_data___tmr___lsb 0 | ||
| 84 | #define reg_timer_rs_cnt_data___tmr___width 24 | ||
| 85 | #define reg_timer_rs_cnt_data___cnt___lsb 24 | ||
| 86 | #define reg_timer_rs_cnt_data___cnt___width 8 | ||
| 87 | #define reg_timer_rs_cnt_data_offset 32 | ||
| 88 | |||
| 89 | /* Register r_cnt_data, scope timer, type r */ | ||
| 90 | #define reg_timer_r_cnt_data___tmr___lsb 0 | ||
| 91 | #define reg_timer_r_cnt_data___tmr___width 24 | ||
| 92 | #define reg_timer_r_cnt_data___cnt___lsb 24 | ||
| 93 | #define reg_timer_r_cnt_data___cnt___width 8 | ||
| 94 | #define reg_timer_r_cnt_data_offset 36 | ||
| 95 | |||
| 96 | /* Register rw_cnt_cfg, scope timer, type rw */ | ||
| 97 | #define reg_timer_rw_cnt_cfg___clk___lsb 0 | ||
| 98 | #define reg_timer_rw_cnt_cfg___clk___width 2 | ||
| 99 | #define reg_timer_rw_cnt_cfg_offset 40 | ||
| 100 | |||
| 101 | /* Register rw_trig, scope timer, type rw */ | ||
| 102 | #define reg_timer_rw_trig_offset 48 | ||
| 103 | |||
| 104 | /* Register rw_trig_cfg, scope timer, type rw */ | ||
| 105 | #define reg_timer_rw_trig_cfg___tmr___lsb 0 | ||
| 106 | #define reg_timer_rw_trig_cfg___tmr___width 2 | ||
| 107 | #define reg_timer_rw_trig_cfg_offset 52 | ||
| 108 | |||
| 109 | /* Register r_time, scope timer, type r */ | ||
| 110 | #define reg_timer_r_time_offset 56 | ||
| 111 | |||
| 112 | /* Register rw_out, scope timer, type rw */ | ||
| 113 | #define reg_timer_rw_out___tmr___lsb 0 | ||
| 114 | #define reg_timer_rw_out___tmr___width 2 | ||
| 115 | #define reg_timer_rw_out_offset 60 | ||
| 116 | |||
| 117 | /* Register rw_wd_ctrl, scope timer, type rw */ | ||
| 118 | #define reg_timer_rw_wd_ctrl___cnt___lsb 0 | ||
| 119 | #define reg_timer_rw_wd_ctrl___cnt___width 8 | ||
| 120 | #define reg_timer_rw_wd_ctrl___cmd___lsb 8 | ||
| 121 | #define reg_timer_rw_wd_ctrl___cmd___width 1 | ||
| 122 | #define reg_timer_rw_wd_ctrl___cmd___bit 8 | ||
| 123 | #define reg_timer_rw_wd_ctrl___key___lsb 9 | ||
| 124 | #define reg_timer_rw_wd_ctrl___key___width 7 | ||
| 125 | #define reg_timer_rw_wd_ctrl_offset 64 | ||
| 126 | |||
| 127 | /* Register r_wd_stat, scope timer, type r */ | ||
| 128 | #define reg_timer_r_wd_stat___cnt___lsb 0 | ||
| 129 | #define reg_timer_r_wd_stat___cnt___width 8 | ||
| 130 | #define reg_timer_r_wd_stat___cmd___lsb 8 | ||
| 131 | #define reg_timer_r_wd_stat___cmd___width 1 | ||
| 132 | #define reg_timer_r_wd_stat___cmd___bit 8 | ||
| 133 | #define reg_timer_r_wd_stat_offset 68 | ||
| 134 | |||
| 135 | /* Register rw_intr_mask, scope timer, type rw */ | ||
| 136 | #define reg_timer_rw_intr_mask___tmr0___lsb 0 | ||
| 137 | #define reg_timer_rw_intr_mask___tmr0___width 1 | ||
| 138 | #define reg_timer_rw_intr_mask___tmr0___bit 0 | ||
| 139 | #define reg_timer_rw_intr_mask___tmr1___lsb 1 | ||
| 140 | #define reg_timer_rw_intr_mask___tmr1___width 1 | ||
| 141 | #define reg_timer_rw_intr_mask___tmr1___bit 1 | ||
| 142 | #define reg_timer_rw_intr_mask___cnt___lsb 2 | ||
| 143 | #define reg_timer_rw_intr_mask___cnt___width 1 | ||
| 144 | #define reg_timer_rw_intr_mask___cnt___bit 2 | ||
| 145 | #define reg_timer_rw_intr_mask___trig___lsb 3 | ||
| 146 | #define reg_timer_rw_intr_mask___trig___width 1 | ||
| 147 | #define reg_timer_rw_intr_mask___trig___bit 3 | ||
| 148 | #define reg_timer_rw_intr_mask_offset 72 | ||
| 149 | |||
| 150 | /* Register rw_ack_intr, scope timer, type rw */ | ||
| 151 | #define reg_timer_rw_ack_intr___tmr0___lsb 0 | ||
| 152 | #define reg_timer_rw_ack_intr___tmr0___width 1 | ||
| 153 | #define reg_timer_rw_ack_intr___tmr0___bit 0 | ||
| 154 | #define reg_timer_rw_ack_intr___tmr1___lsb 1 | ||
| 155 | #define reg_timer_rw_ack_intr___tmr1___width 1 | ||
| 156 | #define reg_timer_rw_ack_intr___tmr1___bit 1 | ||
| 157 | #define reg_timer_rw_ack_intr___cnt___lsb 2 | ||
| 158 | #define reg_timer_rw_ack_intr___cnt___width 1 | ||
| 159 | #define reg_timer_rw_ack_intr___cnt___bit 2 | ||
| 160 | #define reg_timer_rw_ack_intr___trig___lsb 3 | ||
| 161 | #define reg_timer_rw_ack_intr___trig___width 1 | ||
| 162 | #define reg_timer_rw_ack_intr___trig___bit 3 | ||
| 163 | #define reg_timer_rw_ack_intr_offset 76 | ||
| 164 | |||
| 165 | /* Register r_intr, scope timer, type r */ | ||
| 166 | #define reg_timer_r_intr___tmr0___lsb 0 | ||
| 167 | #define reg_timer_r_intr___tmr0___width 1 | ||
| 168 | #define reg_timer_r_intr___tmr0___bit 0 | ||
| 169 | #define reg_timer_r_intr___tmr1___lsb 1 | ||
| 170 | #define reg_timer_r_intr___tmr1___width 1 | ||
| 171 | #define reg_timer_r_intr___tmr1___bit 1 | ||
| 172 | #define reg_timer_r_intr___cnt___lsb 2 | ||
| 173 | #define reg_timer_r_intr___cnt___width 1 | ||
| 174 | #define reg_timer_r_intr___cnt___bit 2 | ||
| 175 | #define reg_timer_r_intr___trig___lsb 3 | ||
| 176 | #define reg_timer_r_intr___trig___width 1 | ||
| 177 | #define reg_timer_r_intr___trig___bit 3 | ||
| 178 | #define reg_timer_r_intr_offset 80 | ||
| 179 | |||
| 180 | /* Register r_masked_intr, scope timer, type r */ | ||
| 181 | #define reg_timer_r_masked_intr___tmr0___lsb 0 | ||
| 182 | #define reg_timer_r_masked_intr___tmr0___width 1 | ||
| 183 | #define reg_timer_r_masked_intr___tmr0___bit 0 | ||
| 184 | #define reg_timer_r_masked_intr___tmr1___lsb 1 | ||
| 185 | #define reg_timer_r_masked_intr___tmr1___width 1 | ||
| 186 | #define reg_timer_r_masked_intr___tmr1___bit 1 | ||
| 187 | #define reg_timer_r_masked_intr___cnt___lsb 2 | ||
| 188 | #define reg_timer_r_masked_intr___cnt___width 1 | ||
| 189 | #define reg_timer_r_masked_intr___cnt___bit 2 | ||
| 190 | #define reg_timer_r_masked_intr___trig___lsb 3 | ||
| 191 | #define reg_timer_r_masked_intr___trig___width 1 | ||
| 192 | #define reg_timer_r_masked_intr___trig___bit 3 | ||
| 193 | #define reg_timer_r_masked_intr_offset 84 | ||
| 194 | |||
| 195 | /* Register rw_test, scope timer, type rw */ | ||
| 196 | #define reg_timer_rw_test___dis___lsb 0 | ||
| 197 | #define reg_timer_rw_test___dis___width 1 | ||
| 198 | #define reg_timer_rw_test___dis___bit 0 | ||
| 199 | #define reg_timer_rw_test___en___lsb 1 | ||
| 200 | #define reg_timer_rw_test___en___width 1 | ||
| 201 | #define reg_timer_rw_test___en___bit 1 | ||
| 202 | #define reg_timer_rw_test_offset 88 | ||
| 203 | |||
| 204 | |||
| 205 | /* Constants */ | ||
| 206 | #define regk_timer_ext 0x00000001 | ||
| 207 | #define regk_timer_f100 0x00000007 | ||
| 208 | #define regk_timer_f29_493 0x00000004 | ||
| 209 | #define regk_timer_f32 0x00000005 | ||
| 210 | #define regk_timer_f32_768 0x00000006 | ||
| 211 | #define regk_timer_hold 0x00000001 | ||
| 212 | #define regk_timer_ld 0x00000000 | ||
| 213 | #define regk_timer_no 0x00000000 | ||
| 214 | #define regk_timer_off 0x00000000 | ||
| 215 | #define regk_timer_run 0x00000002 | ||
| 216 | #define regk_timer_rw_cnt_cfg_default 0x00000000 | ||
| 217 | #define regk_timer_rw_intr_mask_default 0x00000000 | ||
| 218 | #define regk_timer_rw_out_default 0x00000000 | ||
| 219 | #define regk_timer_rw_test_default 0x00000000 | ||
| 220 | #define regk_timer_rw_tmr0_ctrl_default 0x00000000 | ||
| 221 | #define regk_timer_rw_tmr1_ctrl_default 0x00000000 | ||
| 222 | #define regk_timer_rw_trig_cfg_default 0x00000000 | ||
| 223 | #define regk_timer_start 0x00000001 | ||
| 224 | #define regk_timer_stop 0x00000000 | ||
| 225 | #define regk_timer_time 0x00000001 | ||
| 226 | #define regk_timer_tmr0 0x00000002 | ||
| 227 | #define regk_timer_tmr1 0x00000003 | ||
| 228 | #define regk_timer_yes 0x00000001 | ||
| 229 | #endif /* __timer_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/ata_defs.h b/include/asm-cris/arch-v32/hwregs/ata_defs.h deleted file mode 100644 index 43b6643ff0d3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/ata_defs.h +++ /dev/null | |||
| @@ -1,222 +0,0 @@ | |||
| 1 | #ifndef __ata_defs_h | ||
| 2 | #define __ata_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/ata/rtl/ata_regs.r | ||
| 7 | * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:25 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r | ||
| 11 | * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope ata */ | ||
| 86 | |||
| 87 | /* Register rw_ctrl0, scope ata, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int pio_hold : 6; | ||
| 90 | unsigned int pio_strb : 6; | ||
| 91 | unsigned int pio_setup : 6; | ||
| 92 | unsigned int dma_hold : 6; | ||
| 93 | unsigned int dma_strb : 6; | ||
| 94 | unsigned int rst : 1; | ||
| 95 | unsigned int en : 1; | ||
| 96 | } reg_ata_rw_ctrl0; | ||
| 97 | #define REG_RD_ADDR_ata_rw_ctrl0 12 | ||
| 98 | #define REG_WR_ADDR_ata_rw_ctrl0 12 | ||
| 99 | |||
| 100 | /* Register rw_ctrl1, scope ata, type rw */ | ||
| 101 | typedef struct { | ||
| 102 | unsigned int udma_tcyc : 4; | ||
| 103 | unsigned int udma_tdvs : 4; | ||
| 104 | unsigned int dummy1 : 24; | ||
| 105 | } reg_ata_rw_ctrl1; | ||
| 106 | #define REG_RD_ADDR_ata_rw_ctrl1 16 | ||
| 107 | #define REG_WR_ADDR_ata_rw_ctrl1 16 | ||
| 108 | |||
| 109 | /* Register rw_ctrl2, scope ata, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int data : 16; | ||
| 112 | unsigned int dummy1 : 3; | ||
| 113 | unsigned int dma_size : 1; | ||
| 114 | unsigned int multi : 1; | ||
| 115 | unsigned int hsh : 2; | ||
| 116 | unsigned int trf_mode : 1; | ||
| 117 | unsigned int rw : 1; | ||
| 118 | unsigned int addr : 3; | ||
| 119 | unsigned int cs0 : 1; | ||
| 120 | unsigned int cs1 : 1; | ||
| 121 | unsigned int sel : 2; | ||
| 122 | } reg_ata_rw_ctrl2; | ||
| 123 | #define REG_RD_ADDR_ata_rw_ctrl2 0 | ||
| 124 | #define REG_WR_ADDR_ata_rw_ctrl2 0 | ||
| 125 | |||
| 126 | /* Register rs_stat_data, scope ata, type rs */ | ||
| 127 | typedef struct { | ||
| 128 | unsigned int data : 16; | ||
| 129 | unsigned int dav : 1; | ||
| 130 | unsigned int busy : 1; | ||
| 131 | unsigned int dummy1 : 14; | ||
| 132 | } reg_ata_rs_stat_data; | ||
| 133 | #define REG_RD_ADDR_ata_rs_stat_data 4 | ||
| 134 | |||
| 135 | /* Register r_stat_data, scope ata, type r */ | ||
| 136 | typedef struct { | ||
| 137 | unsigned int data : 16; | ||
| 138 | unsigned int dav : 1; | ||
| 139 | unsigned int busy : 1; | ||
| 140 | unsigned int dummy1 : 14; | ||
| 141 | } reg_ata_r_stat_data; | ||
| 142 | #define REG_RD_ADDR_ata_r_stat_data 8 | ||
| 143 | |||
| 144 | /* Register rw_trf_cnt, scope ata, type rw */ | ||
| 145 | typedef struct { | ||
| 146 | unsigned int cnt : 17; | ||
| 147 | unsigned int dummy1 : 15; | ||
| 148 | } reg_ata_rw_trf_cnt; | ||
| 149 | #define REG_RD_ADDR_ata_rw_trf_cnt 20 | ||
| 150 | #define REG_WR_ADDR_ata_rw_trf_cnt 20 | ||
| 151 | |||
| 152 | /* Register r_stat_misc, scope ata, type r */ | ||
| 153 | typedef struct { | ||
| 154 | unsigned int crc : 16; | ||
| 155 | unsigned int dummy1 : 16; | ||
| 156 | } reg_ata_r_stat_misc; | ||
| 157 | #define REG_RD_ADDR_ata_r_stat_misc 24 | ||
| 158 | |||
| 159 | /* Register rw_intr_mask, scope ata, type rw */ | ||
| 160 | typedef struct { | ||
| 161 | unsigned int bus0 : 1; | ||
| 162 | unsigned int bus1 : 1; | ||
| 163 | unsigned int bus2 : 1; | ||
| 164 | unsigned int bus3 : 1; | ||
| 165 | unsigned int dummy1 : 28; | ||
| 166 | } reg_ata_rw_intr_mask; | ||
| 167 | #define REG_RD_ADDR_ata_rw_intr_mask 28 | ||
| 168 | #define REG_WR_ADDR_ata_rw_intr_mask 28 | ||
| 169 | |||
| 170 | /* Register rw_ack_intr, scope ata, type rw */ | ||
| 171 | typedef struct { | ||
| 172 | unsigned int bus0 : 1; | ||
| 173 | unsigned int bus1 : 1; | ||
| 174 | unsigned int bus2 : 1; | ||
| 175 | unsigned int bus3 : 1; | ||
| 176 | unsigned int dummy1 : 28; | ||
| 177 | } reg_ata_rw_ack_intr; | ||
| 178 | #define REG_RD_ADDR_ata_rw_ack_intr 32 | ||
| 179 | #define REG_WR_ADDR_ata_rw_ack_intr 32 | ||
| 180 | |||
| 181 | /* Register r_intr, scope ata, type r */ | ||
| 182 | typedef struct { | ||
| 183 | unsigned int bus0 : 1; | ||
| 184 | unsigned int bus1 : 1; | ||
| 185 | unsigned int bus2 : 1; | ||
| 186 | unsigned int bus3 : 1; | ||
| 187 | unsigned int dummy1 : 28; | ||
| 188 | } reg_ata_r_intr; | ||
| 189 | #define REG_RD_ADDR_ata_r_intr 36 | ||
| 190 | |||
| 191 | /* Register r_masked_intr, scope ata, type r */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int bus0 : 1; | ||
| 194 | unsigned int bus1 : 1; | ||
| 195 | unsigned int bus2 : 1; | ||
| 196 | unsigned int bus3 : 1; | ||
| 197 | unsigned int dummy1 : 28; | ||
| 198 | } reg_ata_r_masked_intr; | ||
| 199 | #define REG_RD_ADDR_ata_r_masked_intr 40 | ||
| 200 | |||
| 201 | |||
| 202 | /* Constants */ | ||
| 203 | enum { | ||
| 204 | regk_ata_active = 0x00000001, | ||
| 205 | regk_ata_byte = 0x00000001, | ||
| 206 | regk_ata_data = 0x00000001, | ||
| 207 | regk_ata_dma = 0x00000001, | ||
| 208 | regk_ata_inactive = 0x00000000, | ||
| 209 | regk_ata_no = 0x00000000, | ||
| 210 | regk_ata_nodata = 0x00000000, | ||
| 211 | regk_ata_pio = 0x00000000, | ||
| 212 | regk_ata_rd = 0x00000001, | ||
| 213 | regk_ata_reg = 0x00000000, | ||
| 214 | regk_ata_rw_ctrl0_default = 0x00000000, | ||
| 215 | regk_ata_rw_ctrl2_default = 0x00000000, | ||
| 216 | regk_ata_rw_intr_mask_default = 0x00000000, | ||
| 217 | regk_ata_udma = 0x00000002, | ||
| 218 | regk_ata_word = 0x00000000, | ||
| 219 | regk_ata_wr = 0x00000000, | ||
| 220 | regk_ata_yes = 0x00000001 | ||
| 221 | }; | ||
| 222 | #endif /* __ata_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h deleted file mode 100644 index a56608b50359..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h +++ /dev/null | |||
| @@ -1,284 +0,0 @@ | |||
| 1 | #ifndef __bif_core_defs_h | ||
| 2 | #define __bif_core_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_core_regs.r | ||
| 7 | * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r | ||
| 11 | * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_core */ | ||
| 86 | |||
| 87 | /* Register rw_grp1_cfg, scope bif_core, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int lw : 6; | ||
| 90 | unsigned int ew : 3; | ||
| 91 | unsigned int zw : 3; | ||
| 92 | unsigned int aw : 2; | ||
| 93 | unsigned int dw : 2; | ||
| 94 | unsigned int ewb : 2; | ||
| 95 | unsigned int bw : 1; | ||
| 96 | unsigned int wr_extend : 1; | ||
| 97 | unsigned int erc_en : 1; | ||
| 98 | unsigned int mode : 1; | ||
| 99 | unsigned int dummy1 : 10; | ||
| 100 | } reg_bif_core_rw_grp1_cfg; | ||
| 101 | #define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 | ||
| 102 | #define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 | ||
| 103 | |||
| 104 | /* Register rw_grp2_cfg, scope bif_core, type rw */ | ||
| 105 | typedef struct { | ||
| 106 | unsigned int lw : 6; | ||
| 107 | unsigned int ew : 3; | ||
| 108 | unsigned int zw : 3; | ||
| 109 | unsigned int aw : 2; | ||
| 110 | unsigned int dw : 2; | ||
| 111 | unsigned int ewb : 2; | ||
| 112 | unsigned int bw : 1; | ||
| 113 | unsigned int wr_extend : 1; | ||
| 114 | unsigned int erc_en : 1; | ||
| 115 | unsigned int mode : 1; | ||
| 116 | unsigned int dummy1 : 10; | ||
| 117 | } reg_bif_core_rw_grp2_cfg; | ||
| 118 | #define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 | ||
| 119 | #define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 | ||
| 120 | |||
| 121 | /* Register rw_grp3_cfg, scope bif_core, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int lw : 6; | ||
| 124 | unsigned int ew : 3; | ||
| 125 | unsigned int zw : 3; | ||
| 126 | unsigned int aw : 2; | ||
| 127 | unsigned int dw : 2; | ||
| 128 | unsigned int ewb : 2; | ||
| 129 | unsigned int bw : 1; | ||
| 130 | unsigned int wr_extend : 1; | ||
| 131 | unsigned int erc_en : 1; | ||
| 132 | unsigned int mode : 1; | ||
| 133 | unsigned int dummy1 : 2; | ||
| 134 | unsigned int gated_csp0 : 2; | ||
| 135 | unsigned int gated_csp1 : 2; | ||
| 136 | unsigned int gated_csp2 : 2; | ||
| 137 | unsigned int gated_csp3 : 2; | ||
| 138 | } reg_bif_core_rw_grp3_cfg; | ||
| 139 | #define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 | ||
| 140 | #define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 | ||
| 141 | |||
| 142 | /* Register rw_grp4_cfg, scope bif_core, type rw */ | ||
| 143 | typedef struct { | ||
| 144 | unsigned int lw : 6; | ||
| 145 | unsigned int ew : 3; | ||
| 146 | unsigned int zw : 3; | ||
| 147 | unsigned int aw : 2; | ||
| 148 | unsigned int dw : 2; | ||
| 149 | unsigned int ewb : 2; | ||
| 150 | unsigned int bw : 1; | ||
| 151 | unsigned int wr_extend : 1; | ||
| 152 | unsigned int erc_en : 1; | ||
| 153 | unsigned int mode : 1; | ||
| 154 | unsigned int dummy1 : 4; | ||
| 155 | unsigned int gated_csp4 : 2; | ||
| 156 | unsigned int gated_csp5 : 2; | ||
| 157 | unsigned int gated_csp6 : 2; | ||
| 158 | } reg_bif_core_rw_grp4_cfg; | ||
| 159 | #define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 | ||
| 160 | #define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 | ||
| 161 | |||
| 162 | /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int bank_sel : 5; | ||
| 165 | unsigned int ca : 3; | ||
| 166 | unsigned int type : 1; | ||
| 167 | unsigned int bw : 1; | ||
| 168 | unsigned int sh : 3; | ||
| 169 | unsigned int wmm : 1; | ||
| 170 | unsigned int sh16 : 1; | ||
| 171 | unsigned int grp_sel : 5; | ||
| 172 | unsigned int dummy1 : 12; | ||
| 173 | } reg_bif_core_rw_sdram_cfg_grp0; | ||
| 174 | #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 | ||
| 175 | #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 | ||
| 176 | |||
| 177 | /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int bank_sel : 5; | ||
| 180 | unsigned int ca : 3; | ||
| 181 | unsigned int type : 1; | ||
| 182 | unsigned int bw : 1; | ||
| 183 | unsigned int sh : 3; | ||
| 184 | unsigned int wmm : 1; | ||
| 185 | unsigned int sh16 : 1; | ||
| 186 | unsigned int dummy1 : 17; | ||
| 187 | } reg_bif_core_rw_sdram_cfg_grp1; | ||
| 188 | #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 | ||
| 189 | #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 | ||
| 190 | |||
| 191 | /* Register rw_sdram_timing, scope bif_core, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int cl : 3; | ||
| 194 | unsigned int rcd : 3; | ||
| 195 | unsigned int rp : 3; | ||
| 196 | unsigned int rc : 2; | ||
| 197 | unsigned int dpl : 2; | ||
| 198 | unsigned int pde : 1; | ||
| 199 | unsigned int ref : 2; | ||
| 200 | unsigned int cpd : 1; | ||
| 201 | unsigned int sdcke : 1; | ||
| 202 | unsigned int sdclk : 1; | ||
| 203 | unsigned int dummy1 : 13; | ||
| 204 | } reg_bif_core_rw_sdram_timing; | ||
| 205 | #define REG_RD_ADDR_bif_core_rw_sdram_timing 24 | ||
| 206 | #define REG_WR_ADDR_bif_core_rw_sdram_timing 24 | ||
| 207 | |||
| 208 | /* Register rw_sdram_cmd, scope bif_core, type rw */ | ||
| 209 | typedef struct { | ||
| 210 | unsigned int cmd : 3; | ||
| 211 | unsigned int mrs_data : 15; | ||
| 212 | unsigned int dummy1 : 14; | ||
| 213 | } reg_bif_core_rw_sdram_cmd; | ||
| 214 | #define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 | ||
| 215 | #define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 | ||
| 216 | |||
| 217 | /* Register rs_sdram_ref_stat, scope bif_core, type rs */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int ok : 1; | ||
| 220 | unsigned int dummy1 : 31; | ||
| 221 | } reg_bif_core_rs_sdram_ref_stat; | ||
| 222 | #define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 | ||
| 223 | |||
| 224 | /* Register r_sdram_ref_stat, scope bif_core, type r */ | ||
| 225 | typedef struct { | ||
| 226 | unsigned int ok : 1; | ||
| 227 | unsigned int dummy1 : 31; | ||
| 228 | } reg_bif_core_r_sdram_ref_stat; | ||
| 229 | #define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 | ||
| 230 | |||
| 231 | |||
| 232 | /* Constants */ | ||
| 233 | enum { | ||
| 234 | regk_bif_core_bank2 = 0x00000000, | ||
| 235 | regk_bif_core_bank4 = 0x00000001, | ||
| 236 | regk_bif_core_bit10 = 0x0000000a, | ||
| 237 | regk_bif_core_bit11 = 0x0000000b, | ||
| 238 | regk_bif_core_bit12 = 0x0000000c, | ||
| 239 | regk_bif_core_bit13 = 0x0000000d, | ||
| 240 | regk_bif_core_bit14 = 0x0000000e, | ||
| 241 | regk_bif_core_bit15 = 0x0000000f, | ||
| 242 | regk_bif_core_bit16 = 0x00000010, | ||
| 243 | regk_bif_core_bit17 = 0x00000011, | ||
| 244 | regk_bif_core_bit18 = 0x00000012, | ||
| 245 | regk_bif_core_bit19 = 0x00000013, | ||
| 246 | regk_bif_core_bit20 = 0x00000014, | ||
| 247 | regk_bif_core_bit21 = 0x00000015, | ||
| 248 | regk_bif_core_bit22 = 0x00000016, | ||
| 249 | regk_bif_core_bit23 = 0x00000017, | ||
| 250 | regk_bif_core_bit24 = 0x00000018, | ||
| 251 | regk_bif_core_bit25 = 0x00000019, | ||
| 252 | regk_bif_core_bit26 = 0x0000001a, | ||
| 253 | regk_bif_core_bit27 = 0x0000001b, | ||
| 254 | regk_bif_core_bit28 = 0x0000001c, | ||
| 255 | regk_bif_core_bit29 = 0x0000001d, | ||
| 256 | regk_bif_core_bit9 = 0x00000009, | ||
| 257 | regk_bif_core_bw16 = 0x00000001, | ||
| 258 | regk_bif_core_bw32 = 0x00000000, | ||
| 259 | regk_bif_core_bwe = 0x00000000, | ||
| 260 | regk_bif_core_cwe = 0x00000001, | ||
| 261 | regk_bif_core_e15us = 0x00000001, | ||
| 262 | regk_bif_core_e7800ns = 0x00000002, | ||
| 263 | regk_bif_core_grp0 = 0x00000000, | ||
| 264 | regk_bif_core_grp1 = 0x00000001, | ||
| 265 | regk_bif_core_mrs = 0x00000003, | ||
| 266 | regk_bif_core_no = 0x00000000, | ||
| 267 | regk_bif_core_none = 0x00000000, | ||
| 268 | regk_bif_core_nop = 0x00000000, | ||
| 269 | regk_bif_core_off = 0x00000000, | ||
| 270 | regk_bif_core_pre = 0x00000002, | ||
| 271 | regk_bif_core_r_sdram_ref_stat_default = 0x00000001, | ||
| 272 | regk_bif_core_rd = 0x00000002, | ||
| 273 | regk_bif_core_ref = 0x00000001, | ||
| 274 | regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, | ||
| 275 | regk_bif_core_rw_grp1_cfg_default = 0x000006cf, | ||
| 276 | regk_bif_core_rw_grp2_cfg_default = 0x000006cf, | ||
| 277 | regk_bif_core_rw_grp3_cfg_default = 0x000006cf, | ||
| 278 | regk_bif_core_rw_grp4_cfg_default = 0x000006cf, | ||
| 279 | regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, | ||
| 280 | regk_bif_core_slf = 0x00000004, | ||
| 281 | regk_bif_core_wr = 0x00000001, | ||
| 282 | regk_bif_core_yes = 0x00000001 | ||
| 283 | }; | ||
| 284 | #endif /* __bif_core_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h deleted file mode 100644 index b931c1aab679..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h +++ /dev/null | |||
| @@ -1,473 +0,0 @@ | |||
| 1 | #ifndef __bif_dma_defs_h | ||
| 2 | #define __bif_dma_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_dma_regs.r | ||
| 7 | * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r | ||
| 11 | * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_dma */ | ||
| 86 | |||
| 87 | /* Register rw_ch0_ctrl, scope bif_dma, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int bw : 2; | ||
| 90 | unsigned int burst_len : 1; | ||
| 91 | unsigned int cont : 1; | ||
| 92 | unsigned int end_pad : 1; | ||
| 93 | unsigned int cnt : 1; | ||
| 94 | unsigned int dreq_pin : 3; | ||
| 95 | unsigned int dreq_mode : 2; | ||
| 96 | unsigned int tc_in_pin : 3; | ||
| 97 | unsigned int tc_in_mode : 2; | ||
| 98 | unsigned int bus_mode : 2; | ||
| 99 | unsigned int rate_en : 1; | ||
| 100 | unsigned int wr_all : 1; | ||
| 101 | unsigned int dummy1 : 12; | ||
| 102 | } reg_bif_dma_rw_ch0_ctrl; | ||
| 103 | #define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 | ||
| 104 | #define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 | ||
| 105 | |||
| 106 | /* Register rw_ch0_addr, scope bif_dma, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int addr : 32; | ||
| 109 | } reg_bif_dma_rw_ch0_addr; | ||
| 110 | #define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 | ||
| 111 | #define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 | ||
| 112 | |||
| 113 | /* Register rw_ch0_start, scope bif_dma, type rw */ | ||
| 114 | typedef struct { | ||
| 115 | unsigned int run : 1; | ||
| 116 | unsigned int dummy1 : 31; | ||
| 117 | } reg_bif_dma_rw_ch0_start; | ||
| 118 | #define REG_RD_ADDR_bif_dma_rw_ch0_start 8 | ||
| 119 | #define REG_WR_ADDR_bif_dma_rw_ch0_start 8 | ||
| 120 | |||
| 121 | /* Register rw_ch0_cnt, scope bif_dma, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int start_cnt : 16; | ||
| 124 | unsigned int dummy1 : 16; | ||
| 125 | } reg_bif_dma_rw_ch0_cnt; | ||
| 126 | #define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 | ||
| 127 | #define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 | ||
| 128 | |||
| 129 | /* Register r_ch0_stat, scope bif_dma, type r */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int cnt : 16; | ||
| 132 | unsigned int dummy1 : 15; | ||
| 133 | unsigned int run : 1; | ||
| 134 | } reg_bif_dma_r_ch0_stat; | ||
| 135 | #define REG_RD_ADDR_bif_dma_r_ch0_stat 16 | ||
| 136 | |||
| 137 | /* Register rw_ch1_ctrl, scope bif_dma, type rw */ | ||
| 138 | typedef struct { | ||
| 139 | unsigned int bw : 2; | ||
| 140 | unsigned int burst_len : 1; | ||
| 141 | unsigned int cont : 1; | ||
| 142 | unsigned int end_discard : 1; | ||
| 143 | unsigned int cnt : 1; | ||
| 144 | unsigned int dreq_pin : 3; | ||
| 145 | unsigned int dreq_mode : 2; | ||
| 146 | unsigned int tc_in_pin : 3; | ||
| 147 | unsigned int tc_in_mode : 2; | ||
| 148 | unsigned int bus_mode : 2; | ||
| 149 | unsigned int rate_en : 1; | ||
| 150 | unsigned int dummy1 : 13; | ||
| 151 | } reg_bif_dma_rw_ch1_ctrl; | ||
| 152 | #define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 | ||
| 153 | #define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 | ||
| 154 | |||
| 155 | /* Register rw_ch1_addr, scope bif_dma, type rw */ | ||
| 156 | typedef struct { | ||
| 157 | unsigned int addr : 32; | ||
| 158 | } reg_bif_dma_rw_ch1_addr; | ||
| 159 | #define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 | ||
| 160 | #define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 | ||
| 161 | |||
| 162 | /* Register rw_ch1_start, scope bif_dma, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int run : 1; | ||
| 165 | unsigned int dummy1 : 31; | ||
| 166 | } reg_bif_dma_rw_ch1_start; | ||
| 167 | #define REG_RD_ADDR_bif_dma_rw_ch1_start 40 | ||
| 168 | #define REG_WR_ADDR_bif_dma_rw_ch1_start 40 | ||
| 169 | |||
| 170 | /* Register rw_ch1_cnt, scope bif_dma, type rw */ | ||
| 171 | typedef struct { | ||
| 172 | unsigned int start_cnt : 16; | ||
| 173 | unsigned int dummy1 : 16; | ||
| 174 | } reg_bif_dma_rw_ch1_cnt; | ||
| 175 | #define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 | ||
| 176 | #define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 | ||
| 177 | |||
| 178 | /* Register r_ch1_stat, scope bif_dma, type r */ | ||
| 179 | typedef struct { | ||
| 180 | unsigned int cnt : 16; | ||
| 181 | unsigned int dummy1 : 15; | ||
| 182 | unsigned int run : 1; | ||
| 183 | } reg_bif_dma_r_ch1_stat; | ||
| 184 | #define REG_RD_ADDR_bif_dma_r_ch1_stat 48 | ||
| 185 | |||
| 186 | /* Register rw_ch2_ctrl, scope bif_dma, type rw */ | ||
| 187 | typedef struct { | ||
| 188 | unsigned int bw : 2; | ||
| 189 | unsigned int burst_len : 1; | ||
| 190 | unsigned int cont : 1; | ||
| 191 | unsigned int end_pad : 1; | ||
| 192 | unsigned int cnt : 1; | ||
| 193 | unsigned int dreq_pin : 3; | ||
| 194 | unsigned int dreq_mode : 2; | ||
| 195 | unsigned int tc_in_pin : 3; | ||
| 196 | unsigned int tc_in_mode : 2; | ||
| 197 | unsigned int bus_mode : 2; | ||
| 198 | unsigned int rate_en : 1; | ||
| 199 | unsigned int wr_all : 1; | ||
| 200 | unsigned int dummy1 : 12; | ||
| 201 | } reg_bif_dma_rw_ch2_ctrl; | ||
| 202 | #define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 | ||
| 203 | #define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 | ||
| 204 | |||
| 205 | /* Register rw_ch2_addr, scope bif_dma, type rw */ | ||
| 206 | typedef struct { | ||
| 207 | unsigned int addr : 32; | ||
| 208 | } reg_bif_dma_rw_ch2_addr; | ||
| 209 | #define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 | ||
| 210 | #define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 | ||
| 211 | |||
| 212 | /* Register rw_ch2_start, scope bif_dma, type rw */ | ||
| 213 | typedef struct { | ||
| 214 | unsigned int run : 1; | ||
| 215 | unsigned int dummy1 : 31; | ||
| 216 | } reg_bif_dma_rw_ch2_start; | ||
| 217 | #define REG_RD_ADDR_bif_dma_rw_ch2_start 72 | ||
| 218 | #define REG_WR_ADDR_bif_dma_rw_ch2_start 72 | ||
| 219 | |||
| 220 | /* Register rw_ch2_cnt, scope bif_dma, type rw */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int start_cnt : 16; | ||
| 223 | unsigned int dummy1 : 16; | ||
| 224 | } reg_bif_dma_rw_ch2_cnt; | ||
| 225 | #define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 | ||
| 226 | #define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 | ||
| 227 | |||
| 228 | /* Register r_ch2_stat, scope bif_dma, type r */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int cnt : 16; | ||
| 231 | unsigned int dummy1 : 15; | ||
| 232 | unsigned int run : 1; | ||
| 233 | } reg_bif_dma_r_ch2_stat; | ||
| 234 | #define REG_RD_ADDR_bif_dma_r_ch2_stat 80 | ||
| 235 | |||
| 236 | /* Register rw_ch3_ctrl, scope bif_dma, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int bw : 2; | ||
| 239 | unsigned int burst_len : 1; | ||
| 240 | unsigned int cont : 1; | ||
| 241 | unsigned int end_discard : 1; | ||
| 242 | unsigned int cnt : 1; | ||
| 243 | unsigned int dreq_pin : 3; | ||
| 244 | unsigned int dreq_mode : 2; | ||
| 245 | unsigned int tc_in_pin : 3; | ||
| 246 | unsigned int tc_in_mode : 2; | ||
| 247 | unsigned int bus_mode : 2; | ||
| 248 | unsigned int rate_en : 1; | ||
| 249 | unsigned int dummy1 : 13; | ||
| 250 | } reg_bif_dma_rw_ch3_ctrl; | ||
| 251 | #define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 | ||
| 252 | #define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 | ||
| 253 | |||
| 254 | /* Register rw_ch3_addr, scope bif_dma, type rw */ | ||
| 255 | typedef struct { | ||
| 256 | unsigned int addr : 32; | ||
| 257 | } reg_bif_dma_rw_ch3_addr; | ||
| 258 | #define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 | ||
| 259 | #define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 | ||
| 260 | |||
| 261 | /* Register rw_ch3_start, scope bif_dma, type rw */ | ||
| 262 | typedef struct { | ||
| 263 | unsigned int run : 1; | ||
| 264 | unsigned int dummy1 : 31; | ||
| 265 | } reg_bif_dma_rw_ch3_start; | ||
| 266 | #define REG_RD_ADDR_bif_dma_rw_ch3_start 104 | ||
| 267 | #define REG_WR_ADDR_bif_dma_rw_ch3_start 104 | ||
| 268 | |||
| 269 | /* Register rw_ch3_cnt, scope bif_dma, type rw */ | ||
| 270 | typedef struct { | ||
| 271 | unsigned int start_cnt : 16; | ||
| 272 | unsigned int dummy1 : 16; | ||
| 273 | } reg_bif_dma_rw_ch3_cnt; | ||
| 274 | #define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 | ||
| 275 | #define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 | ||
| 276 | |||
| 277 | /* Register r_ch3_stat, scope bif_dma, type r */ | ||
| 278 | typedef struct { | ||
| 279 | unsigned int cnt : 16; | ||
| 280 | unsigned int dummy1 : 15; | ||
| 281 | unsigned int run : 1; | ||
| 282 | } reg_bif_dma_r_ch3_stat; | ||
| 283 | #define REG_RD_ADDR_bif_dma_r_ch3_stat 112 | ||
| 284 | |||
| 285 | /* Register rw_intr_mask, scope bif_dma, type rw */ | ||
| 286 | typedef struct { | ||
| 287 | unsigned int ext_dma0 : 1; | ||
| 288 | unsigned int ext_dma1 : 1; | ||
| 289 | unsigned int ext_dma2 : 1; | ||
| 290 | unsigned int ext_dma3 : 1; | ||
| 291 | unsigned int dummy1 : 28; | ||
| 292 | } reg_bif_dma_rw_intr_mask; | ||
| 293 | #define REG_RD_ADDR_bif_dma_rw_intr_mask 128 | ||
| 294 | #define REG_WR_ADDR_bif_dma_rw_intr_mask 128 | ||
| 295 | |||
| 296 | /* Register rw_ack_intr, scope bif_dma, type rw */ | ||
| 297 | typedef struct { | ||
| 298 | unsigned int ext_dma0 : 1; | ||
| 299 | unsigned int ext_dma1 : 1; | ||
| 300 | unsigned int ext_dma2 : 1; | ||
| 301 | unsigned int ext_dma3 : 1; | ||
| 302 | unsigned int dummy1 : 28; | ||
| 303 | } reg_bif_dma_rw_ack_intr; | ||
| 304 | #define REG_RD_ADDR_bif_dma_rw_ack_intr 132 | ||
| 305 | #define REG_WR_ADDR_bif_dma_rw_ack_intr 132 | ||
| 306 | |||
| 307 | /* Register r_intr, scope bif_dma, type r */ | ||
| 308 | typedef struct { | ||
| 309 | unsigned int ext_dma0 : 1; | ||
| 310 | unsigned int ext_dma1 : 1; | ||
| 311 | unsigned int ext_dma2 : 1; | ||
| 312 | unsigned int ext_dma3 : 1; | ||
| 313 | unsigned int dummy1 : 28; | ||
| 314 | } reg_bif_dma_r_intr; | ||
| 315 | #define REG_RD_ADDR_bif_dma_r_intr 136 | ||
| 316 | |||
| 317 | /* Register r_masked_intr, scope bif_dma, type r */ | ||
| 318 | typedef struct { | ||
| 319 | unsigned int ext_dma0 : 1; | ||
| 320 | unsigned int ext_dma1 : 1; | ||
| 321 | unsigned int ext_dma2 : 1; | ||
| 322 | unsigned int ext_dma3 : 1; | ||
| 323 | unsigned int dummy1 : 28; | ||
| 324 | } reg_bif_dma_r_masked_intr; | ||
| 325 | #define REG_RD_ADDR_bif_dma_r_masked_intr 140 | ||
| 326 | |||
| 327 | /* Register rw_pin0_cfg, scope bif_dma, type rw */ | ||
| 328 | typedef struct { | ||
| 329 | unsigned int master_ch : 2; | ||
| 330 | unsigned int master_mode : 3; | ||
| 331 | unsigned int slave_ch : 2; | ||
| 332 | unsigned int slave_mode : 3; | ||
| 333 | unsigned int dummy1 : 22; | ||
| 334 | } reg_bif_dma_rw_pin0_cfg; | ||
| 335 | #define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 | ||
| 336 | #define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 | ||
| 337 | |||
| 338 | /* Register rw_pin1_cfg, scope bif_dma, type rw */ | ||
| 339 | typedef struct { | ||
| 340 | unsigned int master_ch : 2; | ||
| 341 | unsigned int master_mode : 3; | ||
| 342 | unsigned int slave_ch : 2; | ||
| 343 | unsigned int slave_mode : 3; | ||
| 344 | unsigned int dummy1 : 22; | ||
| 345 | } reg_bif_dma_rw_pin1_cfg; | ||
| 346 | #define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 | ||
| 347 | #define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 | ||
| 348 | |||
| 349 | /* Register rw_pin2_cfg, scope bif_dma, type rw */ | ||
| 350 | typedef struct { | ||
| 351 | unsigned int master_ch : 2; | ||
| 352 | unsigned int master_mode : 3; | ||
| 353 | unsigned int slave_ch : 2; | ||
| 354 | unsigned int slave_mode : 3; | ||
| 355 | unsigned int dummy1 : 22; | ||
| 356 | } reg_bif_dma_rw_pin2_cfg; | ||
| 357 | #define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 | ||
| 358 | #define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 | ||
| 359 | |||
| 360 | /* Register rw_pin3_cfg, scope bif_dma, type rw */ | ||
| 361 | typedef struct { | ||
| 362 | unsigned int master_ch : 2; | ||
| 363 | unsigned int master_mode : 3; | ||
| 364 | unsigned int slave_ch : 2; | ||
| 365 | unsigned int slave_mode : 3; | ||
| 366 | unsigned int dummy1 : 22; | ||
| 367 | } reg_bif_dma_rw_pin3_cfg; | ||
| 368 | #define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 | ||
| 369 | #define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 | ||
| 370 | |||
| 371 | /* Register rw_pin4_cfg, scope bif_dma, type rw */ | ||
| 372 | typedef struct { | ||
| 373 | unsigned int master_ch : 2; | ||
| 374 | unsigned int master_mode : 3; | ||
| 375 | unsigned int slave_ch : 2; | ||
| 376 | unsigned int slave_mode : 3; | ||
| 377 | unsigned int dummy1 : 22; | ||
| 378 | } reg_bif_dma_rw_pin4_cfg; | ||
| 379 | #define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 | ||
| 380 | #define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 | ||
| 381 | |||
| 382 | /* Register rw_pin5_cfg, scope bif_dma, type rw */ | ||
| 383 | typedef struct { | ||
| 384 | unsigned int master_ch : 2; | ||
| 385 | unsigned int master_mode : 3; | ||
| 386 | unsigned int slave_ch : 2; | ||
| 387 | unsigned int slave_mode : 3; | ||
| 388 | unsigned int dummy1 : 22; | ||
| 389 | } reg_bif_dma_rw_pin5_cfg; | ||
| 390 | #define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 | ||
| 391 | #define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 | ||
| 392 | |||
| 393 | /* Register rw_pin6_cfg, scope bif_dma, type rw */ | ||
| 394 | typedef struct { | ||
| 395 | unsigned int master_ch : 2; | ||
| 396 | unsigned int master_mode : 3; | ||
| 397 | unsigned int slave_ch : 2; | ||
| 398 | unsigned int slave_mode : 3; | ||
| 399 | unsigned int dummy1 : 22; | ||
| 400 | } reg_bif_dma_rw_pin6_cfg; | ||
| 401 | #define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 | ||
| 402 | #define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 | ||
| 403 | |||
| 404 | /* Register rw_pin7_cfg, scope bif_dma, type rw */ | ||
| 405 | typedef struct { | ||
| 406 | unsigned int master_ch : 2; | ||
| 407 | unsigned int master_mode : 3; | ||
| 408 | unsigned int slave_ch : 2; | ||
| 409 | unsigned int slave_mode : 3; | ||
| 410 | unsigned int dummy1 : 22; | ||
| 411 | } reg_bif_dma_rw_pin7_cfg; | ||
| 412 | #define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 | ||
| 413 | #define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 | ||
| 414 | |||
| 415 | /* Register r_pin_stat, scope bif_dma, type r */ | ||
| 416 | typedef struct { | ||
| 417 | unsigned int pin0 : 1; | ||
| 418 | unsigned int pin1 : 1; | ||
| 419 | unsigned int pin2 : 1; | ||
| 420 | unsigned int pin3 : 1; | ||
| 421 | unsigned int pin4 : 1; | ||
| 422 | unsigned int pin5 : 1; | ||
| 423 | unsigned int pin6 : 1; | ||
| 424 | unsigned int pin7 : 1; | ||
| 425 | unsigned int dummy1 : 24; | ||
| 426 | } reg_bif_dma_r_pin_stat; | ||
| 427 | #define REG_RD_ADDR_bif_dma_r_pin_stat 192 | ||
| 428 | |||
| 429 | |||
| 430 | /* Constants */ | ||
| 431 | enum { | ||
| 432 | regk_bif_dma_as_master = 0x00000001, | ||
| 433 | regk_bif_dma_as_slave = 0x00000001, | ||
| 434 | regk_bif_dma_burst1 = 0x00000000, | ||
| 435 | regk_bif_dma_burst8 = 0x00000001, | ||
| 436 | regk_bif_dma_bw16 = 0x00000001, | ||
| 437 | regk_bif_dma_bw32 = 0x00000002, | ||
| 438 | regk_bif_dma_bw8 = 0x00000000, | ||
| 439 | regk_bif_dma_dack = 0x00000006, | ||
| 440 | regk_bif_dma_dack_inv = 0x00000007, | ||
| 441 | regk_bif_dma_force = 0x00000001, | ||
| 442 | regk_bif_dma_hi = 0x00000003, | ||
| 443 | regk_bif_dma_inv = 0x00000003, | ||
| 444 | regk_bif_dma_lo = 0x00000002, | ||
| 445 | regk_bif_dma_master = 0x00000001, | ||
| 446 | regk_bif_dma_no = 0x00000000, | ||
| 447 | regk_bif_dma_norm = 0x00000002, | ||
| 448 | regk_bif_dma_off = 0x00000000, | ||
| 449 | regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, | ||
| 450 | regk_bif_dma_rw_ch0_start_default = 0x00000000, | ||
| 451 | regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, | ||
| 452 | regk_bif_dma_rw_ch1_start_default = 0x00000000, | ||
| 453 | regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, | ||
| 454 | regk_bif_dma_rw_ch2_start_default = 0x00000000, | ||
| 455 | regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, | ||
| 456 | regk_bif_dma_rw_ch3_start_default = 0x00000000, | ||
| 457 | regk_bif_dma_rw_intr_mask_default = 0x00000000, | ||
| 458 | regk_bif_dma_rw_pin0_cfg_default = 0x00000000, | ||
| 459 | regk_bif_dma_rw_pin1_cfg_default = 0x00000000, | ||
| 460 | regk_bif_dma_rw_pin2_cfg_default = 0x00000000, | ||
| 461 | regk_bif_dma_rw_pin3_cfg_default = 0x00000000, | ||
| 462 | regk_bif_dma_rw_pin4_cfg_default = 0x00000000, | ||
| 463 | regk_bif_dma_rw_pin5_cfg_default = 0x00000000, | ||
| 464 | regk_bif_dma_rw_pin6_cfg_default = 0x00000000, | ||
| 465 | regk_bif_dma_rw_pin7_cfg_default = 0x00000000, | ||
| 466 | regk_bif_dma_slave = 0x00000002, | ||
| 467 | regk_bif_dma_sreq = 0x00000006, | ||
| 468 | regk_bif_dma_sreq_inv = 0x00000007, | ||
| 469 | regk_bif_dma_tc = 0x00000004, | ||
| 470 | regk_bif_dma_tc_inv = 0x00000005, | ||
| 471 | regk_bif_dma_yes = 0x00000001 | ||
| 472 | }; | ||
| 473 | #endif /* __bif_dma_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h deleted file mode 100644 index d18fc3c9f569..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h +++ /dev/null | |||
| @@ -1,249 +0,0 @@ | |||
| 1 | #ifndef __bif_slave_defs_h | ||
| 2 | #define __bif_slave_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_slave_regs.r | ||
| 7 | * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:34 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r | ||
| 11 | * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_slave */ | ||
| 86 | |||
| 87 | /* Register rw_slave_cfg, scope bif_slave, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int slave_id : 3; | ||
| 90 | unsigned int use_slave_id : 1; | ||
| 91 | unsigned int boot_rdy : 1; | ||
| 92 | unsigned int loopback : 1; | ||
| 93 | unsigned int dis : 1; | ||
| 94 | unsigned int dummy1 : 25; | ||
| 95 | } reg_bif_slave_rw_slave_cfg; | ||
| 96 | #define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 | ||
| 97 | #define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 | ||
| 98 | |||
| 99 | /* Register r_slave_mode, scope bif_slave, type r */ | ||
| 100 | typedef struct { | ||
| 101 | unsigned int ch0_mode : 1; | ||
| 102 | unsigned int ch1_mode : 1; | ||
| 103 | unsigned int ch2_mode : 1; | ||
| 104 | unsigned int ch3_mode : 1; | ||
| 105 | unsigned int dummy1 : 28; | ||
| 106 | } reg_bif_slave_r_slave_mode; | ||
| 107 | #define REG_RD_ADDR_bif_slave_r_slave_mode 4 | ||
| 108 | |||
| 109 | /* Register rw_ch0_cfg, scope bif_slave, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int rd_hold : 2; | ||
| 112 | unsigned int access_mode : 1; | ||
| 113 | unsigned int access_ctrl : 1; | ||
| 114 | unsigned int data_cs : 2; | ||
| 115 | unsigned int dummy1 : 26; | ||
| 116 | } reg_bif_slave_rw_ch0_cfg; | ||
| 117 | #define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 | ||
| 118 | #define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 | ||
| 119 | |||
| 120 | /* Register rw_ch1_cfg, scope bif_slave, type rw */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int rd_hold : 2; | ||
| 123 | unsigned int access_mode : 1; | ||
| 124 | unsigned int access_ctrl : 1; | ||
| 125 | unsigned int data_cs : 2; | ||
| 126 | unsigned int dummy1 : 26; | ||
| 127 | } reg_bif_slave_rw_ch1_cfg; | ||
| 128 | #define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 | ||
| 129 | #define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 | ||
| 130 | |||
| 131 | /* Register rw_ch2_cfg, scope bif_slave, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int rd_hold : 2; | ||
| 134 | unsigned int access_mode : 1; | ||
| 135 | unsigned int access_ctrl : 1; | ||
| 136 | unsigned int data_cs : 2; | ||
| 137 | unsigned int dummy1 : 26; | ||
| 138 | } reg_bif_slave_rw_ch2_cfg; | ||
| 139 | #define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 | ||
| 140 | #define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 | ||
| 141 | |||
| 142 | /* Register rw_ch3_cfg, scope bif_slave, type rw */ | ||
| 143 | typedef struct { | ||
| 144 | unsigned int rd_hold : 2; | ||
| 145 | unsigned int access_mode : 1; | ||
| 146 | unsigned int access_ctrl : 1; | ||
| 147 | unsigned int data_cs : 2; | ||
| 148 | unsigned int dummy1 : 26; | ||
| 149 | } reg_bif_slave_rw_ch3_cfg; | ||
| 150 | #define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 | ||
| 151 | #define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 | ||
| 152 | |||
| 153 | /* Register rw_arb_cfg, scope bif_slave, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int brin_mode : 1; | ||
| 156 | unsigned int brout_mode : 3; | ||
| 157 | unsigned int bg_mode : 3; | ||
| 158 | unsigned int release : 2; | ||
| 159 | unsigned int acquire : 1; | ||
| 160 | unsigned int settle_time : 2; | ||
| 161 | unsigned int dram_ctrl : 1; | ||
| 162 | unsigned int dummy1 : 19; | ||
| 163 | } reg_bif_slave_rw_arb_cfg; | ||
| 164 | #define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 | ||
| 165 | #define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 | ||
| 166 | |||
| 167 | /* Register r_arb_stat, scope bif_slave, type r */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int init_mode : 1; | ||
| 170 | unsigned int mode : 1; | ||
| 171 | unsigned int brin : 1; | ||
| 172 | unsigned int brout : 1; | ||
| 173 | unsigned int bg : 1; | ||
| 174 | unsigned int dummy1 : 27; | ||
| 175 | } reg_bif_slave_r_arb_stat; | ||
| 176 | #define REG_RD_ADDR_bif_slave_r_arb_stat 36 | ||
| 177 | |||
| 178 | /* Register rw_intr_mask, scope bif_slave, type rw */ | ||
| 179 | typedef struct { | ||
| 180 | unsigned int bus_release : 1; | ||
| 181 | unsigned int bus_acquire : 1; | ||
| 182 | unsigned int dummy1 : 30; | ||
| 183 | } reg_bif_slave_rw_intr_mask; | ||
| 184 | #define REG_RD_ADDR_bif_slave_rw_intr_mask 64 | ||
| 185 | #define REG_WR_ADDR_bif_slave_rw_intr_mask 64 | ||
| 186 | |||
| 187 | /* Register rw_ack_intr, scope bif_slave, type rw */ | ||
| 188 | typedef struct { | ||
| 189 | unsigned int bus_release : 1; | ||
| 190 | unsigned int bus_acquire : 1; | ||
| 191 | unsigned int dummy1 : 30; | ||
| 192 | } reg_bif_slave_rw_ack_intr; | ||
| 193 | #define REG_RD_ADDR_bif_slave_rw_ack_intr 68 | ||
| 194 | #define REG_WR_ADDR_bif_slave_rw_ack_intr 68 | ||
| 195 | |||
| 196 | /* Register r_intr, scope bif_slave, type r */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int bus_release : 1; | ||
| 199 | unsigned int bus_acquire : 1; | ||
| 200 | unsigned int dummy1 : 30; | ||
| 201 | } reg_bif_slave_r_intr; | ||
| 202 | #define REG_RD_ADDR_bif_slave_r_intr 72 | ||
| 203 | |||
| 204 | /* Register r_masked_intr, scope bif_slave, type r */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int bus_release : 1; | ||
| 207 | unsigned int bus_acquire : 1; | ||
| 208 | unsigned int dummy1 : 30; | ||
| 209 | } reg_bif_slave_r_masked_intr; | ||
| 210 | #define REG_RD_ADDR_bif_slave_r_masked_intr 76 | ||
| 211 | |||
| 212 | |||
| 213 | /* Constants */ | ||
| 214 | enum { | ||
| 215 | regk_bif_slave_active_hi = 0x00000003, | ||
| 216 | regk_bif_slave_active_lo = 0x00000002, | ||
| 217 | regk_bif_slave_addr = 0x00000000, | ||
| 218 | regk_bif_slave_always = 0x00000001, | ||
| 219 | regk_bif_slave_at_idle = 0x00000002, | ||
| 220 | regk_bif_slave_burst_end = 0x00000003, | ||
| 221 | regk_bif_slave_dma = 0x00000001, | ||
| 222 | regk_bif_slave_hi = 0x00000003, | ||
| 223 | regk_bif_slave_inv = 0x00000001, | ||
| 224 | regk_bif_slave_lo = 0x00000002, | ||
| 225 | regk_bif_slave_local = 0x00000001, | ||
| 226 | regk_bif_slave_master = 0x00000000, | ||
| 227 | regk_bif_slave_mode_reg = 0x00000001, | ||
| 228 | regk_bif_slave_no = 0x00000000, | ||
| 229 | regk_bif_slave_norm = 0x00000000, | ||
| 230 | regk_bif_slave_on_access = 0x00000000, | ||
| 231 | regk_bif_slave_rw_arb_cfg_default = 0x00000000, | ||
| 232 | regk_bif_slave_rw_ch0_cfg_default = 0x00000000, | ||
| 233 | regk_bif_slave_rw_ch1_cfg_default = 0x00000000, | ||
| 234 | regk_bif_slave_rw_ch2_cfg_default = 0x00000000, | ||
| 235 | regk_bif_slave_rw_ch3_cfg_default = 0x00000000, | ||
| 236 | regk_bif_slave_rw_intr_mask_default = 0x00000000, | ||
| 237 | regk_bif_slave_rw_slave_cfg_default = 0x00000000, | ||
| 238 | regk_bif_slave_shared = 0x00000000, | ||
| 239 | regk_bif_slave_slave = 0x00000001, | ||
| 240 | regk_bif_slave_t0ns = 0x00000003, | ||
| 241 | regk_bif_slave_t10ns = 0x00000002, | ||
| 242 | regk_bif_slave_t20ns = 0x00000003, | ||
| 243 | regk_bif_slave_t30ns = 0x00000002, | ||
| 244 | regk_bif_slave_t40ns = 0x00000001, | ||
| 245 | regk_bif_slave_t50ns = 0x00000000, | ||
| 246 | regk_bif_slave_yes = 0x00000001, | ||
| 247 | regk_bif_slave_z = 0x00000004 | ||
| 248 | }; | ||
| 249 | #endif /* __bif_slave_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/config_defs.h b/include/asm-cris/arch-v32/hwregs/config_defs.h deleted file mode 100644 index 45457a4e3817..000000000000 --- a/include/asm-cris/arch-v32/hwregs/config_defs.h +++ /dev/null | |||
| @@ -1,142 +0,0 @@ | |||
| 1 | #ifndef __config_defs_h | ||
| 2 | #define __config_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../rtl/config_regs.r | ||
| 7 | * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp | ||
| 8 | * last modfied: Thu Mar 4 12:34:39 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r | ||
| 11 | * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope config */ | ||
| 86 | |||
| 87 | /* Register r_bootsel, scope config, type r */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int boot_mode : 3; | ||
| 90 | unsigned int full_duplex : 1; | ||
| 91 | unsigned int user : 1; | ||
| 92 | unsigned int pll : 1; | ||
| 93 | unsigned int flash_bw : 1; | ||
| 94 | unsigned int dummy1 : 25; | ||
| 95 | } reg_config_r_bootsel; | ||
| 96 | #define REG_RD_ADDR_config_r_bootsel 0 | ||
| 97 | |||
| 98 | /* Register rw_clk_ctrl, scope config, type rw */ | ||
| 99 | typedef struct { | ||
| 100 | unsigned int pll : 1; | ||
| 101 | unsigned int cpu : 1; | ||
| 102 | unsigned int iop : 1; | ||
| 103 | unsigned int dma01_eth0 : 1; | ||
| 104 | unsigned int dma23 : 1; | ||
| 105 | unsigned int dma45 : 1; | ||
| 106 | unsigned int dma67 : 1; | ||
| 107 | unsigned int dma89_strcop : 1; | ||
| 108 | unsigned int bif : 1; | ||
| 109 | unsigned int fix_io : 1; | ||
| 110 | unsigned int dummy1 : 22; | ||
| 111 | } reg_config_rw_clk_ctrl; | ||
| 112 | #define REG_RD_ADDR_config_rw_clk_ctrl 4 | ||
| 113 | #define REG_WR_ADDR_config_rw_clk_ctrl 4 | ||
| 114 | |||
| 115 | /* Register rw_pad_ctrl, scope config, type rw */ | ||
| 116 | typedef struct { | ||
| 117 | unsigned int usb_susp : 1; | ||
| 118 | unsigned int phyrst_n : 1; | ||
| 119 | unsigned int dummy1 : 30; | ||
| 120 | } reg_config_rw_pad_ctrl; | ||
| 121 | #define REG_RD_ADDR_config_rw_pad_ctrl 8 | ||
| 122 | #define REG_WR_ADDR_config_rw_pad_ctrl 8 | ||
| 123 | |||
| 124 | |||
| 125 | /* Constants */ | ||
| 126 | enum { | ||
| 127 | regk_config_bw16 = 0x00000000, | ||
| 128 | regk_config_bw32 = 0x00000001, | ||
| 129 | regk_config_master = 0x00000005, | ||
| 130 | regk_config_nand = 0x00000003, | ||
| 131 | regk_config_net_rx = 0x00000001, | ||
| 132 | regk_config_net_tx_rx = 0x00000002, | ||
| 133 | regk_config_no = 0x00000000, | ||
| 134 | regk_config_none = 0x00000007, | ||
| 135 | regk_config_nor = 0x00000000, | ||
| 136 | regk_config_rw_clk_ctrl_default = 0x00000002, | ||
| 137 | regk_config_rw_pad_ctrl_default = 0x00000000, | ||
| 138 | regk_config_ser = 0x00000004, | ||
| 139 | regk_config_slave = 0x00000006, | ||
| 140 | regk_config_yes = 0x00000001 | ||
| 141 | }; | ||
| 142 | #endif /* __config_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/include/asm-cris/arch-v32/hwregs/cpu_vect.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version | ||
| 2 | from ../../inst/crisp/doc/cpu_vect.r | ||
| 3 | version . */ | ||
| 4 | |||
| 5 | #ifndef _______INST_CRISP_DOC_CPU_VECT_R | ||
| 6 | #define _______INST_CRISP_DOC_CPU_VECT_R | ||
| 7 | #define NMI_INTR_VECT 0x00 | ||
| 8 | #define RESERVED_1_INTR_VECT 0x01 | ||
| 9 | #define RESERVED_2_INTR_VECT 0x02 | ||
| 10 | #define SINGLE_STEP_INTR_VECT 0x03 | ||
| 11 | #define INSTR_TLB_REFILL_INTR_VECT 0x04 | ||
| 12 | #define INSTR_TLB_INV_INTR_VECT 0x05 | ||
| 13 | #define INSTR_TLB_ACC_INTR_VECT 0x06 | ||
| 14 | #define TLB_EX_INTR_VECT 0x07 | ||
| 15 | #define DATA_TLB_REFILL_INTR_VECT 0x08 | ||
| 16 | #define DATA_TLB_INV_INTR_VECT 0x09 | ||
| 17 | #define DATA_TLB_ACC_INTR_VECT 0x0a | ||
| 18 | #define DATA_TLB_WE_INTR_VECT 0x0b | ||
| 19 | #define HW_BP_INTR_VECT 0x0c | ||
| 20 | #define RESERVED_D_INTR_VECT 0x0d | ||
| 21 | #define RESERVED_E_INTR_VECT 0x0e | ||
| 22 | #define RESERVED_F_INTR_VECT 0x0f | ||
| 23 | #define BREAK_0_INTR_VECT 0x10 | ||
| 24 | #define BREAK_1_INTR_VECT 0x11 | ||
| 25 | #define BREAK_2_INTR_VECT 0x12 | ||
| 26 | #define BREAK_3_INTR_VECT 0x13 | ||
| 27 | #define BREAK_4_INTR_VECT 0x14 | ||
| 28 | #define BREAK_5_INTR_VECT 0x15 | ||
| 29 | #define BREAK_6_INTR_VECT 0x16 | ||
| 30 | #define BREAK_7_INTR_VECT 0x17 | ||
| 31 | #define BREAK_8_INTR_VECT 0x18 | ||
| 32 | #define BREAK_9_INTR_VECT 0x19 | ||
| 33 | #define BREAK_10_INTR_VECT 0x1a | ||
| 34 | #define BREAK_11_INTR_VECT 0x1b | ||
| 35 | #define BREAK_12_INTR_VECT 0x1c | ||
| 36 | #define BREAK_13_INTR_VECT 0x1d | ||
| 37 | #define BREAK_14_INTR_VECT 0x1e | ||
| 38 | #define BREAK_15_INTR_VECT 0x1f | ||
| 39 | #define MULTIPLE_INTR_VECT 0x30 | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h deleted file mode 100644 index 3ce322b5c731..000000000000 --- a/include/asm-cris/arch-v32/hwregs/dma.h +++ /dev/null | |||
| @@ -1,127 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DMA C definitions and help macros | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef dma_h | ||
| 7 | #define dma_h | ||
| 8 | |||
| 9 | /* registers */ /* Really needed, since both are listed in sw.list? */ | ||
| 10 | #include "dma_defs.h" | ||
| 11 | |||
| 12 | |||
| 13 | /* descriptors */ | ||
| 14 | |||
| 15 | // ------------------------------------------------------------ dma_descr_group | ||
| 16 | typedef struct dma_descr_group { | ||
| 17 | struct dma_descr_group *next; | ||
| 18 | unsigned eol : 1; | ||
| 19 | unsigned tol : 1; | ||
| 20 | unsigned bol : 1; | ||
| 21 | unsigned : 1; | ||
| 22 | unsigned intr : 1; | ||
| 23 | unsigned : 2; | ||
| 24 | unsigned en : 1; | ||
| 25 | unsigned : 7; | ||
| 26 | unsigned dis : 1; | ||
| 27 | unsigned md : 16; | ||
| 28 | struct dma_descr_group *up; | ||
| 29 | union { | ||
| 30 | struct dma_descr_context *context; | ||
| 31 | struct dma_descr_group *group; | ||
| 32 | } down; | ||
| 33 | } dma_descr_group; | ||
| 34 | |||
| 35 | // ---------------------------------------------------------- dma_descr_context | ||
| 36 | typedef struct dma_descr_context { | ||
| 37 | struct dma_descr_context *next; | ||
| 38 | unsigned eol : 1; | ||
| 39 | unsigned : 3; | ||
| 40 | unsigned intr : 1; | ||
| 41 | unsigned : 1; | ||
| 42 | unsigned store_mode : 1; | ||
| 43 | unsigned en : 1; | ||
| 44 | unsigned : 7; | ||
| 45 | unsigned dis : 1; | ||
| 46 | unsigned md0 : 16; | ||
| 47 | unsigned md1; | ||
| 48 | unsigned md2; | ||
| 49 | unsigned md3; | ||
| 50 | unsigned md4; | ||
| 51 | struct dma_descr_data *saved_data; | ||
| 52 | char *saved_data_buf; | ||
| 53 | } dma_descr_context; | ||
| 54 | |||
| 55 | // ------------------------------------------------------------- dma_descr_data | ||
| 56 | typedef struct dma_descr_data { | ||
| 57 | struct dma_descr_data *next; | ||
| 58 | char *buf; | ||
| 59 | unsigned eol : 1; | ||
| 60 | unsigned : 2; | ||
| 61 | unsigned out_eop : 1; | ||
| 62 | unsigned intr : 1; | ||
| 63 | unsigned wait : 1; | ||
| 64 | unsigned : 2; | ||
| 65 | unsigned : 3; | ||
| 66 | unsigned in_eop : 1; | ||
| 67 | unsigned : 4; | ||
| 68 | unsigned md : 16; | ||
| 69 | char *after; | ||
| 70 | } dma_descr_data; | ||
| 71 | |||
| 72 | // --------------------------------------------------------------------- macros | ||
| 73 | |||
| 74 | // enable DMA channel | ||
| 75 | #define DMA_ENABLE( inst ) \ | ||
| 76 | do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ | ||
| 77 | e.en = regk_dma_yes; \ | ||
| 78 | REG_WR( dma, inst, rw_cfg, e); } while( 0 ) | ||
| 79 | |||
| 80 | // reset DMA channel | ||
| 81 | #define DMA_RESET( inst ) \ | ||
| 82 | do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ | ||
| 83 | r.en = regk_dma_no; \ | ||
| 84 | REG_WR( dma, inst, rw_cfg, r); } while( 0 ) | ||
| 85 | |||
| 86 | // stop DMA channel | ||
| 87 | #define DMA_STOP( inst ) \ | ||
| 88 | do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ | ||
| 89 | s.stop = regk_dma_yes; \ | ||
| 90 | REG_WR( dma, inst, rw_cfg, s); } while( 0 ) | ||
| 91 | |||
| 92 | // continue DMA channel operation | ||
| 93 | #define DMA_CONTINUE( inst ) \ | ||
| 94 | do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ | ||
| 95 | c.stop = regk_dma_no; \ | ||
| 96 | REG_WR( dma, inst, rw_cfg, c); } while( 0 ) | ||
| 97 | |||
| 98 | // give stream command | ||
| 99 | #define DMA_WR_CMD( inst, cmd_par ) \ | ||
| 100 | do { reg_dma_rw_stream_cmd __x = {0}; \ | ||
| 101 | do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \ | ||
| 102 | __x.cmd = (cmd_par); \ | ||
| 103 | REG_WR(dma, inst, rw_stream_cmd, __x); \ | ||
| 104 | } while (0) | ||
| 105 | |||
| 106 | // load: g,c,d:burst | ||
| 107 | #define DMA_START_GROUP( inst, group_descr ) \ | ||
| 108 | do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ | ||
| 109 | DMA_WR_CMD( inst, regk_dma_load_g ); \ | ||
| 110 | DMA_WR_CMD( inst, regk_dma_load_c ); \ | ||
| 111 | DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ | ||
| 112 | } while( 0 ) | ||
| 113 | |||
| 114 | // load: c,d:burst | ||
| 115 | #define DMA_START_CONTEXT( inst, ctx_descr ) \ | ||
| 116 | do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ | ||
| 117 | DMA_WR_CMD( inst, regk_dma_load_c ); \ | ||
| 118 | DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ | ||
| 119 | } while( 0 ) | ||
| 120 | |||
| 121 | // if the DMA is at the end of the data list, the last data descr is reloaded | ||
| 122 | #define DMA_CONTINUE_DATA( inst ) \ | ||
| 123 | do { reg_dma_rw_cmd c = {0}; \ | ||
| 124 | c.cont_data = regk_dma_yes;\ | ||
| 125 | REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) | ||
| 126 | |||
| 127 | #endif | ||
diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h deleted file mode 100644 index 48ac8cef7ebe..000000000000 --- a/include/asm-cris/arch-v32/hwregs/dma_defs.h +++ /dev/null | |||
| @@ -1,436 +0,0 @@ | |||
| 1 | #ifndef __dma_defs_h | ||
| 2 | #define __dma_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r | ||
| 7 | * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:51 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r | ||
| 11 | * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope dma */ | ||
| 86 | |||
| 87 | /* Register rw_data, scope dma, type rw */ | ||
| 88 | typedef unsigned int reg_dma_rw_data; | ||
| 89 | #define REG_RD_ADDR_dma_rw_data 0 | ||
| 90 | #define REG_WR_ADDR_dma_rw_data 0 | ||
| 91 | |||
| 92 | /* Register rw_data_next, scope dma, type rw */ | ||
| 93 | typedef unsigned int reg_dma_rw_data_next; | ||
| 94 | #define REG_RD_ADDR_dma_rw_data_next 4 | ||
| 95 | #define REG_WR_ADDR_dma_rw_data_next 4 | ||
| 96 | |||
| 97 | /* Register rw_data_buf, scope dma, type rw */ | ||
| 98 | typedef unsigned int reg_dma_rw_data_buf; | ||
| 99 | #define REG_RD_ADDR_dma_rw_data_buf 8 | ||
| 100 | #define REG_WR_ADDR_dma_rw_data_buf 8 | ||
| 101 | |||
| 102 | /* Register rw_data_ctrl, scope dma, type rw */ | ||
| 103 | typedef struct { | ||
| 104 | unsigned int eol : 1; | ||
| 105 | unsigned int dummy1 : 2; | ||
| 106 | unsigned int out_eop : 1; | ||
| 107 | unsigned int intr : 1; | ||
| 108 | unsigned int wait : 1; | ||
| 109 | unsigned int dummy2 : 26; | ||
| 110 | } reg_dma_rw_data_ctrl; | ||
| 111 | #define REG_RD_ADDR_dma_rw_data_ctrl 12 | ||
| 112 | #define REG_WR_ADDR_dma_rw_data_ctrl 12 | ||
| 113 | |||
| 114 | /* Register rw_data_stat, scope dma, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int dummy1 : 3; | ||
| 117 | unsigned int in_eop : 1; | ||
| 118 | unsigned int dummy2 : 28; | ||
| 119 | } reg_dma_rw_data_stat; | ||
| 120 | #define REG_RD_ADDR_dma_rw_data_stat 16 | ||
| 121 | #define REG_WR_ADDR_dma_rw_data_stat 16 | ||
| 122 | |||
| 123 | /* Register rw_data_md, scope dma, type rw */ | ||
| 124 | typedef struct { | ||
| 125 | unsigned int md : 16; | ||
| 126 | unsigned int dummy1 : 16; | ||
| 127 | } reg_dma_rw_data_md; | ||
| 128 | #define REG_RD_ADDR_dma_rw_data_md 20 | ||
| 129 | #define REG_WR_ADDR_dma_rw_data_md 20 | ||
| 130 | |||
| 131 | /* Register rw_data_md_s, scope dma, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int md_s : 16; | ||
| 134 | unsigned int dummy1 : 16; | ||
| 135 | } reg_dma_rw_data_md_s; | ||
| 136 | #define REG_RD_ADDR_dma_rw_data_md_s 24 | ||
| 137 | #define REG_WR_ADDR_dma_rw_data_md_s 24 | ||
| 138 | |||
| 139 | /* Register rw_data_after, scope dma, type rw */ | ||
| 140 | typedef unsigned int reg_dma_rw_data_after; | ||
| 141 | #define REG_RD_ADDR_dma_rw_data_after 28 | ||
| 142 | #define REG_WR_ADDR_dma_rw_data_after 28 | ||
| 143 | |||
| 144 | /* Register rw_ctxt, scope dma, type rw */ | ||
| 145 | typedef unsigned int reg_dma_rw_ctxt; | ||
| 146 | #define REG_RD_ADDR_dma_rw_ctxt 32 | ||
| 147 | #define REG_WR_ADDR_dma_rw_ctxt 32 | ||
| 148 | |||
| 149 | /* Register rw_ctxt_next, scope dma, type rw */ | ||
| 150 | typedef unsigned int reg_dma_rw_ctxt_next; | ||
| 151 | #define REG_RD_ADDR_dma_rw_ctxt_next 36 | ||
| 152 | #define REG_WR_ADDR_dma_rw_ctxt_next 36 | ||
| 153 | |||
| 154 | /* Register rw_ctxt_ctrl, scope dma, type rw */ | ||
| 155 | typedef struct { | ||
| 156 | unsigned int eol : 1; | ||
| 157 | unsigned int dummy1 : 3; | ||
| 158 | unsigned int intr : 1; | ||
| 159 | unsigned int dummy2 : 1; | ||
| 160 | unsigned int store_mode : 1; | ||
| 161 | unsigned int en : 1; | ||
| 162 | unsigned int dummy3 : 24; | ||
| 163 | } reg_dma_rw_ctxt_ctrl; | ||
| 164 | #define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 | ||
| 165 | #define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 | ||
| 166 | |||
| 167 | /* Register rw_ctxt_stat, scope dma, type rw */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int dummy1 : 7; | ||
| 170 | unsigned int dis : 1; | ||
| 171 | unsigned int dummy2 : 24; | ||
| 172 | } reg_dma_rw_ctxt_stat; | ||
| 173 | #define REG_RD_ADDR_dma_rw_ctxt_stat 44 | ||
| 174 | #define REG_WR_ADDR_dma_rw_ctxt_stat 44 | ||
| 175 | |||
| 176 | /* Register rw_ctxt_md0, scope dma, type rw */ | ||
| 177 | typedef struct { | ||
| 178 | unsigned int md0 : 16; | ||
| 179 | unsigned int dummy1 : 16; | ||
| 180 | } reg_dma_rw_ctxt_md0; | ||
| 181 | #define REG_RD_ADDR_dma_rw_ctxt_md0 48 | ||
| 182 | #define REG_WR_ADDR_dma_rw_ctxt_md0 48 | ||
| 183 | |||
| 184 | /* Register rw_ctxt_md0_s, scope dma, type rw */ | ||
| 185 | typedef struct { | ||
| 186 | unsigned int md0_s : 16; | ||
| 187 | unsigned int dummy1 : 16; | ||
| 188 | } reg_dma_rw_ctxt_md0_s; | ||
| 189 | #define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 | ||
| 190 | #define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 | ||
| 191 | |||
| 192 | /* Register rw_ctxt_md1, scope dma, type rw */ | ||
| 193 | typedef unsigned int reg_dma_rw_ctxt_md1; | ||
| 194 | #define REG_RD_ADDR_dma_rw_ctxt_md1 56 | ||
| 195 | #define REG_WR_ADDR_dma_rw_ctxt_md1 56 | ||
| 196 | |||
| 197 | /* Register rw_ctxt_md1_s, scope dma, type rw */ | ||
| 198 | typedef unsigned int reg_dma_rw_ctxt_md1_s; | ||
| 199 | #define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 | ||
| 200 | #define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 | ||
| 201 | |||
| 202 | /* Register rw_ctxt_md2, scope dma, type rw */ | ||
| 203 | typedef unsigned int reg_dma_rw_ctxt_md2; | ||
| 204 | #define REG_RD_ADDR_dma_rw_ctxt_md2 64 | ||
| 205 | #define REG_WR_ADDR_dma_rw_ctxt_md2 64 | ||
| 206 | |||
| 207 | /* Register rw_ctxt_md2_s, scope dma, type rw */ | ||
| 208 | typedef unsigned int reg_dma_rw_ctxt_md2_s; | ||
| 209 | #define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 | ||
| 210 | #define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 | ||
| 211 | |||
| 212 | /* Register rw_ctxt_md3, scope dma, type rw */ | ||
| 213 | typedef unsigned int reg_dma_rw_ctxt_md3; | ||
| 214 | #define REG_RD_ADDR_dma_rw_ctxt_md3 72 | ||
| 215 | #define REG_WR_ADDR_dma_rw_ctxt_md3 72 | ||
| 216 | |||
| 217 | /* Register rw_ctxt_md3_s, scope dma, type rw */ | ||
| 218 | typedef unsigned int reg_dma_rw_ctxt_md3_s; | ||
| 219 | #define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 | ||
| 220 | #define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 | ||
| 221 | |||
| 222 | /* Register rw_ctxt_md4, scope dma, type rw */ | ||
| 223 | typedef unsigned int reg_dma_rw_ctxt_md4; | ||
| 224 | #define REG_RD_ADDR_dma_rw_ctxt_md4 80 | ||
| 225 | #define REG_WR_ADDR_dma_rw_ctxt_md4 80 | ||
| 226 | |||
| 227 | /* Register rw_ctxt_md4_s, scope dma, type rw */ | ||
| 228 | typedef unsigned int reg_dma_rw_ctxt_md4_s; | ||
| 229 | #define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 | ||
| 230 | #define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 | ||
| 231 | |||
| 232 | /* Register rw_saved_data, scope dma, type rw */ | ||
| 233 | typedef unsigned int reg_dma_rw_saved_data; | ||
| 234 | #define REG_RD_ADDR_dma_rw_saved_data 88 | ||
| 235 | #define REG_WR_ADDR_dma_rw_saved_data 88 | ||
| 236 | |||
| 237 | /* Register rw_saved_data_buf, scope dma, type rw */ | ||
| 238 | typedef unsigned int reg_dma_rw_saved_data_buf; | ||
| 239 | #define REG_RD_ADDR_dma_rw_saved_data_buf 92 | ||
| 240 | #define REG_WR_ADDR_dma_rw_saved_data_buf 92 | ||
| 241 | |||
| 242 | /* Register rw_group, scope dma, type rw */ | ||
| 243 | typedef unsigned int reg_dma_rw_group; | ||
| 244 | #define REG_RD_ADDR_dma_rw_group 96 | ||
| 245 | #define REG_WR_ADDR_dma_rw_group 96 | ||
| 246 | |||
| 247 | /* Register rw_group_next, scope dma, type rw */ | ||
| 248 | typedef unsigned int reg_dma_rw_group_next; | ||
| 249 | #define REG_RD_ADDR_dma_rw_group_next 100 | ||
| 250 | #define REG_WR_ADDR_dma_rw_group_next 100 | ||
| 251 | |||
| 252 | /* Register rw_group_ctrl, scope dma, type rw */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int eol : 1; | ||
| 255 | unsigned int tol : 1; | ||
| 256 | unsigned int bol : 1; | ||
| 257 | unsigned int dummy1 : 1; | ||
| 258 | unsigned int intr : 1; | ||
| 259 | unsigned int dummy2 : 2; | ||
| 260 | unsigned int en : 1; | ||
| 261 | unsigned int dummy3 : 24; | ||
| 262 | } reg_dma_rw_group_ctrl; | ||
| 263 | #define REG_RD_ADDR_dma_rw_group_ctrl 104 | ||
| 264 | #define REG_WR_ADDR_dma_rw_group_ctrl 104 | ||
| 265 | |||
| 266 | /* Register rw_group_stat, scope dma, type rw */ | ||
| 267 | typedef struct { | ||
| 268 | unsigned int dummy1 : 7; | ||
| 269 | unsigned int dis : 1; | ||
| 270 | unsigned int dummy2 : 24; | ||
| 271 | } reg_dma_rw_group_stat; | ||
| 272 | #define REG_RD_ADDR_dma_rw_group_stat 108 | ||
| 273 | #define REG_WR_ADDR_dma_rw_group_stat 108 | ||
| 274 | |||
| 275 | /* Register rw_group_md, scope dma, type rw */ | ||
| 276 | typedef struct { | ||
| 277 | unsigned int md : 16; | ||
| 278 | unsigned int dummy1 : 16; | ||
| 279 | } reg_dma_rw_group_md; | ||
| 280 | #define REG_RD_ADDR_dma_rw_group_md 112 | ||
| 281 | #define REG_WR_ADDR_dma_rw_group_md 112 | ||
| 282 | |||
| 283 | /* Register rw_group_md_s, scope dma, type rw */ | ||
| 284 | typedef struct { | ||
| 285 | unsigned int md_s : 16; | ||
| 286 | unsigned int dummy1 : 16; | ||
| 287 | } reg_dma_rw_group_md_s; | ||
| 288 | #define REG_RD_ADDR_dma_rw_group_md_s 116 | ||
| 289 | #define REG_WR_ADDR_dma_rw_group_md_s 116 | ||
| 290 | |||
| 291 | /* Register rw_group_up, scope dma, type rw */ | ||
| 292 | typedef unsigned int reg_dma_rw_group_up; | ||
| 293 | #define REG_RD_ADDR_dma_rw_group_up 120 | ||
| 294 | #define REG_WR_ADDR_dma_rw_group_up 120 | ||
| 295 | |||
| 296 | /* Register rw_group_down, scope dma, type rw */ | ||
| 297 | typedef unsigned int reg_dma_rw_group_down; | ||
| 298 | #define REG_RD_ADDR_dma_rw_group_down 124 | ||
| 299 | #define REG_WR_ADDR_dma_rw_group_down 124 | ||
| 300 | |||
| 301 | /* Register rw_cmd, scope dma, type rw */ | ||
| 302 | typedef struct { | ||
| 303 | unsigned int cont_data : 1; | ||
| 304 | unsigned int dummy1 : 31; | ||
| 305 | } reg_dma_rw_cmd; | ||
| 306 | #define REG_RD_ADDR_dma_rw_cmd 128 | ||
| 307 | #define REG_WR_ADDR_dma_rw_cmd 128 | ||
| 308 | |||
| 309 | /* Register rw_cfg, scope dma, type rw */ | ||
| 310 | typedef struct { | ||
| 311 | unsigned int en : 1; | ||
| 312 | unsigned int stop : 1; | ||
| 313 | unsigned int dummy1 : 30; | ||
| 314 | } reg_dma_rw_cfg; | ||
| 315 | #define REG_RD_ADDR_dma_rw_cfg 132 | ||
| 316 | #define REG_WR_ADDR_dma_rw_cfg 132 | ||
| 317 | |||
| 318 | /* Register rw_stat, scope dma, type rw */ | ||
| 319 | typedef struct { | ||
| 320 | unsigned int mode : 5; | ||
| 321 | unsigned int list_state : 3; | ||
| 322 | unsigned int stream_cmd_src : 8; | ||
| 323 | unsigned int dummy1 : 8; | ||
| 324 | unsigned int buf : 8; | ||
| 325 | } reg_dma_rw_stat; | ||
| 326 | #define REG_RD_ADDR_dma_rw_stat 136 | ||
| 327 | #define REG_WR_ADDR_dma_rw_stat 136 | ||
| 328 | |||
| 329 | /* Register rw_intr_mask, scope dma, type rw */ | ||
| 330 | typedef struct { | ||
| 331 | unsigned int group : 1; | ||
| 332 | unsigned int ctxt : 1; | ||
| 333 | unsigned int data : 1; | ||
| 334 | unsigned int in_eop : 1; | ||
| 335 | unsigned int stream_cmd : 1; | ||
| 336 | unsigned int dummy1 : 27; | ||
| 337 | } reg_dma_rw_intr_mask; | ||
| 338 | #define REG_RD_ADDR_dma_rw_intr_mask 140 | ||
| 339 | #define REG_WR_ADDR_dma_rw_intr_mask 140 | ||
| 340 | |||
| 341 | /* Register rw_ack_intr, scope dma, type rw */ | ||
| 342 | typedef struct { | ||
| 343 | unsigned int group : 1; | ||
| 344 | unsigned int ctxt : 1; | ||
| 345 | unsigned int data : 1; | ||
| 346 | unsigned int in_eop : 1; | ||
| 347 | unsigned int stream_cmd : 1; | ||
| 348 | unsigned int dummy1 : 27; | ||
| 349 | } reg_dma_rw_ack_intr; | ||
| 350 | #define REG_RD_ADDR_dma_rw_ack_intr 144 | ||
| 351 | #define REG_WR_ADDR_dma_rw_ack_intr 144 | ||
| 352 | |||
| 353 | /* Register r_intr, scope dma, type r */ | ||
| 354 | typedef struct { | ||
| 355 | unsigned int group : 1; | ||
| 356 | unsigned int ctxt : 1; | ||
| 357 | unsigned int data : 1; | ||
| 358 | unsigned int in_eop : 1; | ||
| 359 | unsigned int stream_cmd : 1; | ||
| 360 | unsigned int dummy1 : 27; | ||
| 361 | } reg_dma_r_intr; | ||
| 362 | #define REG_RD_ADDR_dma_r_intr 148 | ||
| 363 | |||
| 364 | /* Register r_masked_intr, scope dma, type r */ | ||
| 365 | typedef struct { | ||
| 366 | unsigned int group : 1; | ||
| 367 | unsigned int ctxt : 1; | ||
| 368 | unsigned int data : 1; | ||
| 369 | unsigned int in_eop : 1; | ||
| 370 | unsigned int stream_cmd : 1; | ||
| 371 | unsigned int dummy1 : 27; | ||
| 372 | } reg_dma_r_masked_intr; | ||
| 373 | #define REG_RD_ADDR_dma_r_masked_intr 152 | ||
| 374 | |||
| 375 | /* Register rw_stream_cmd, scope dma, type rw */ | ||
| 376 | typedef struct { | ||
| 377 | unsigned int cmd : 10; | ||
| 378 | unsigned int dummy1 : 6; | ||
| 379 | unsigned int n : 8; | ||
| 380 | unsigned int dummy2 : 7; | ||
| 381 | unsigned int busy : 1; | ||
| 382 | } reg_dma_rw_stream_cmd; | ||
| 383 | #define REG_RD_ADDR_dma_rw_stream_cmd 156 | ||
| 384 | #define REG_WR_ADDR_dma_rw_stream_cmd 156 | ||
| 385 | |||
| 386 | |||
| 387 | /* Constants */ | ||
| 388 | enum { | ||
| 389 | regk_dma_ack_pkt = 0x00000100, | ||
| 390 | regk_dma_anytime = 0x00000001, | ||
| 391 | regk_dma_array = 0x00000008, | ||
| 392 | regk_dma_burst = 0x00000020, | ||
| 393 | regk_dma_client = 0x00000002, | ||
| 394 | regk_dma_copy_next = 0x00000010, | ||
| 395 | regk_dma_copy_up = 0x00000020, | ||
| 396 | regk_dma_data_at_eol = 0x00000001, | ||
| 397 | regk_dma_dis_c = 0x00000010, | ||
| 398 | regk_dma_dis_g = 0x00000020, | ||
| 399 | regk_dma_idle = 0x00000001, | ||
| 400 | regk_dma_intern = 0x00000004, | ||
| 401 | regk_dma_load_c = 0x00000200, | ||
| 402 | regk_dma_load_c_n = 0x00000280, | ||
| 403 | regk_dma_load_c_next = 0x00000240, | ||
| 404 | regk_dma_load_d = 0x00000140, | ||
| 405 | regk_dma_load_g = 0x00000300, | ||
| 406 | regk_dma_load_g_down = 0x000003c0, | ||
| 407 | regk_dma_load_g_next = 0x00000340, | ||
| 408 | regk_dma_load_g_up = 0x00000380, | ||
| 409 | regk_dma_next_en = 0x00000010, | ||
| 410 | regk_dma_next_pkt = 0x00000010, | ||
| 411 | regk_dma_no = 0x00000000, | ||
| 412 | regk_dma_only_at_wait = 0x00000000, | ||
| 413 | regk_dma_restore = 0x00000020, | ||
| 414 | regk_dma_rst = 0x00000001, | ||
| 415 | regk_dma_running = 0x00000004, | ||
| 416 | regk_dma_rw_cfg_default = 0x00000000, | ||
| 417 | regk_dma_rw_cmd_default = 0x00000000, | ||
| 418 | regk_dma_rw_intr_mask_default = 0x00000000, | ||
| 419 | regk_dma_rw_stat_default = 0x00000101, | ||
| 420 | regk_dma_rw_stream_cmd_default = 0x00000000, | ||
| 421 | regk_dma_save_down = 0x00000020, | ||
| 422 | regk_dma_save_up = 0x00000020, | ||
| 423 | regk_dma_set_reg = 0x00000050, | ||
| 424 | regk_dma_set_w_size1 = 0x00000190, | ||
| 425 | regk_dma_set_w_size2 = 0x000001a0, | ||
| 426 | regk_dma_set_w_size4 = 0x000001c0, | ||
| 427 | regk_dma_stopped = 0x00000002, | ||
| 428 | regk_dma_store_c = 0x00000002, | ||
| 429 | regk_dma_store_descr = 0x00000000, | ||
| 430 | regk_dma_store_g = 0x00000004, | ||
| 431 | regk_dma_store_md = 0x00000001, | ||
| 432 | regk_dma_sw = 0x00000008, | ||
| 433 | regk_dma_update_down = 0x00000020, | ||
| 434 | regk_dma_yes = 0x00000001 | ||
| 435 | }; | ||
| 436 | #endif /* __dma_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h deleted file mode 100644 index 90fe8a28894f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/eth_defs.h +++ /dev/null | |||
| @@ -1,378 +0,0 @@ | |||
| 1 | #ifndef __eth_defs_h | ||
| 2 | #define __eth_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: eth.r | ||
| 7 | * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp | ||
| 8 | * last modfied: Mon Jan 9 06:06:41 2006 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/rdes2c eth.r | ||
| 11 | * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope eth */ | ||
| 86 | |||
| 87 | /* Register rw_ma0_lo, scope eth, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int addr : 32; | ||
| 90 | } reg_eth_rw_ma0_lo; | ||
| 91 | #define REG_RD_ADDR_eth_rw_ma0_lo 0 | ||
| 92 | #define REG_WR_ADDR_eth_rw_ma0_lo 0 | ||
| 93 | |||
| 94 | /* Register rw_ma0_hi, scope eth, type rw */ | ||
| 95 | typedef struct { | ||
| 96 | unsigned int addr : 16; | ||
| 97 | unsigned int dummy1 : 16; | ||
| 98 | } reg_eth_rw_ma0_hi; | ||
| 99 | #define REG_RD_ADDR_eth_rw_ma0_hi 4 | ||
| 100 | #define REG_WR_ADDR_eth_rw_ma0_hi 4 | ||
| 101 | |||
| 102 | /* Register rw_ma1_lo, scope eth, type rw */ | ||
| 103 | typedef struct { | ||
| 104 | unsigned int addr : 32; | ||
| 105 | } reg_eth_rw_ma1_lo; | ||
| 106 | #define REG_RD_ADDR_eth_rw_ma1_lo 8 | ||
| 107 | #define REG_WR_ADDR_eth_rw_ma1_lo 8 | ||
| 108 | |||
| 109 | /* Register rw_ma1_hi, scope eth, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int addr : 16; | ||
| 112 | unsigned int dummy1 : 16; | ||
| 113 | } reg_eth_rw_ma1_hi; | ||
| 114 | #define REG_RD_ADDR_eth_rw_ma1_hi 12 | ||
| 115 | #define REG_WR_ADDR_eth_rw_ma1_hi 12 | ||
| 116 | |||
| 117 | /* Register rw_ga_lo, scope eth, type rw */ | ||
| 118 | typedef struct { | ||
| 119 | unsigned int tbl : 32; | ||
| 120 | } reg_eth_rw_ga_lo; | ||
| 121 | #define REG_RD_ADDR_eth_rw_ga_lo 16 | ||
| 122 | #define REG_WR_ADDR_eth_rw_ga_lo 16 | ||
| 123 | |||
| 124 | /* Register rw_ga_hi, scope eth, type rw */ | ||
| 125 | typedef struct { | ||
| 126 | unsigned int tbl : 32; | ||
| 127 | } reg_eth_rw_ga_hi; | ||
| 128 | #define REG_RD_ADDR_eth_rw_ga_hi 20 | ||
| 129 | #define REG_WR_ADDR_eth_rw_ga_hi 20 | ||
| 130 | |||
| 131 | /* Register rw_gen_ctrl, scope eth, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int en : 1; | ||
| 134 | unsigned int phy : 2; | ||
| 135 | unsigned int protocol : 1; | ||
| 136 | unsigned int loopback : 1; | ||
| 137 | unsigned int flow_ctrl : 1; | ||
| 138 | unsigned int gtxclk_out : 1; | ||
| 139 | unsigned int phyrst_n : 1; | ||
| 140 | unsigned int dummy1 : 24; | ||
| 141 | } reg_eth_rw_gen_ctrl; | ||
| 142 | #define REG_RD_ADDR_eth_rw_gen_ctrl 24 | ||
| 143 | #define REG_WR_ADDR_eth_rw_gen_ctrl 24 | ||
| 144 | |||
| 145 | /* Register rw_rec_ctrl, scope eth, type rw */ | ||
| 146 | typedef struct { | ||
| 147 | unsigned int ma0 : 1; | ||
| 148 | unsigned int ma1 : 1; | ||
| 149 | unsigned int individual : 1; | ||
| 150 | unsigned int broadcast : 1; | ||
| 151 | unsigned int undersize : 1; | ||
| 152 | unsigned int oversize : 1; | ||
| 153 | unsigned int bad_crc : 1; | ||
| 154 | unsigned int duplex : 1; | ||
| 155 | unsigned int max_size : 16; | ||
| 156 | unsigned int dummy1 : 8; | ||
| 157 | } reg_eth_rw_rec_ctrl; | ||
| 158 | #define REG_RD_ADDR_eth_rw_rec_ctrl 28 | ||
| 159 | #define REG_WR_ADDR_eth_rw_rec_ctrl 28 | ||
| 160 | |||
| 161 | /* Register rw_tr_ctrl, scope eth, type rw */ | ||
| 162 | typedef struct { | ||
| 163 | unsigned int crc : 1; | ||
| 164 | unsigned int pad : 1; | ||
| 165 | unsigned int retry : 1; | ||
| 166 | unsigned int ignore_col : 1; | ||
| 167 | unsigned int cancel : 1; | ||
| 168 | unsigned int hsh_delay : 1; | ||
| 169 | unsigned int ignore_crs : 1; | ||
| 170 | unsigned int carrier_ext : 1; | ||
| 171 | unsigned int dummy1 : 24; | ||
| 172 | } reg_eth_rw_tr_ctrl; | ||
| 173 | #define REG_RD_ADDR_eth_rw_tr_ctrl 32 | ||
| 174 | #define REG_WR_ADDR_eth_rw_tr_ctrl 32 | ||
| 175 | |||
| 176 | /* Register rw_clr_err, scope eth, type rw */ | ||
| 177 | typedef struct { | ||
| 178 | unsigned int clr : 1; | ||
| 179 | unsigned int dummy1 : 31; | ||
| 180 | } reg_eth_rw_clr_err; | ||
| 181 | #define REG_RD_ADDR_eth_rw_clr_err 36 | ||
| 182 | #define REG_WR_ADDR_eth_rw_clr_err 36 | ||
| 183 | |||
| 184 | /* Register rw_mgm_ctrl, scope eth, type rw */ | ||
| 185 | typedef struct { | ||
| 186 | unsigned int mdio : 1; | ||
| 187 | unsigned int mdoe : 1; | ||
| 188 | unsigned int mdc : 1; | ||
| 189 | unsigned int dummy1 : 29; | ||
| 190 | } reg_eth_rw_mgm_ctrl; | ||
| 191 | #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 | ||
| 192 | #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 | ||
| 193 | |||
| 194 | /* Register r_stat, scope eth, type r */ | ||
| 195 | typedef struct { | ||
| 196 | unsigned int mdio : 1; | ||
| 197 | unsigned int exc_col : 1; | ||
| 198 | unsigned int urun : 1; | ||
| 199 | unsigned int clk_125 : 1; | ||
| 200 | unsigned int dummy1 : 28; | ||
| 201 | } reg_eth_r_stat; | ||
| 202 | #define REG_RD_ADDR_eth_r_stat 44 | ||
| 203 | |||
| 204 | /* Register rs_rec_cnt, scope eth, type rs */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int crc_err : 8; | ||
| 207 | unsigned int align_err : 8; | ||
| 208 | unsigned int oversize : 8; | ||
| 209 | unsigned int congestion : 8; | ||
| 210 | } reg_eth_rs_rec_cnt; | ||
| 211 | #define REG_RD_ADDR_eth_rs_rec_cnt 48 | ||
| 212 | |||
| 213 | /* Register r_rec_cnt, scope eth, type r */ | ||
| 214 | typedef struct { | ||
| 215 | unsigned int crc_err : 8; | ||
| 216 | unsigned int align_err : 8; | ||
| 217 | unsigned int oversize : 8; | ||
| 218 | unsigned int congestion : 8; | ||
| 219 | } reg_eth_r_rec_cnt; | ||
| 220 | #define REG_RD_ADDR_eth_r_rec_cnt 52 | ||
| 221 | |||
| 222 | /* Register rs_tr_cnt, scope eth, type rs */ | ||
| 223 | typedef struct { | ||
| 224 | unsigned int single_col : 8; | ||
| 225 | unsigned int mult_col : 8; | ||
| 226 | unsigned int late_col : 8; | ||
| 227 | unsigned int deferred : 8; | ||
| 228 | } reg_eth_rs_tr_cnt; | ||
| 229 | #define REG_RD_ADDR_eth_rs_tr_cnt 56 | ||
| 230 | |||
| 231 | /* Register r_tr_cnt, scope eth, type r */ | ||
| 232 | typedef struct { | ||
| 233 | unsigned int single_col : 8; | ||
| 234 | unsigned int mult_col : 8; | ||
| 235 | unsigned int late_col : 8; | ||
| 236 | unsigned int deferred : 8; | ||
| 237 | } reg_eth_r_tr_cnt; | ||
| 238 | #define REG_RD_ADDR_eth_r_tr_cnt 60 | ||
| 239 | |||
| 240 | /* Register rs_phy_cnt, scope eth, type rs */ | ||
| 241 | typedef struct { | ||
| 242 | unsigned int carrier_loss : 8; | ||
| 243 | unsigned int sqe_err : 8; | ||
| 244 | unsigned int dummy1 : 16; | ||
| 245 | } reg_eth_rs_phy_cnt; | ||
| 246 | #define REG_RD_ADDR_eth_rs_phy_cnt 64 | ||
| 247 | |||
| 248 | /* Register r_phy_cnt, scope eth, type r */ | ||
| 249 | typedef struct { | ||
| 250 | unsigned int carrier_loss : 8; | ||
| 251 | unsigned int sqe_err : 8; | ||
| 252 | unsigned int dummy1 : 16; | ||
| 253 | } reg_eth_r_phy_cnt; | ||
| 254 | #define REG_RD_ADDR_eth_r_phy_cnt 68 | ||
| 255 | |||
| 256 | /* Register rw_test_ctrl, scope eth, type rw */ | ||
| 257 | typedef struct { | ||
| 258 | unsigned int snmp_inc : 1; | ||
| 259 | unsigned int snmp : 1; | ||
| 260 | unsigned int backoff : 1; | ||
| 261 | unsigned int dummy1 : 29; | ||
| 262 | } reg_eth_rw_test_ctrl; | ||
| 263 | #define REG_RD_ADDR_eth_rw_test_ctrl 72 | ||
| 264 | #define REG_WR_ADDR_eth_rw_test_ctrl 72 | ||
| 265 | |||
| 266 | /* Register rw_intr_mask, scope eth, type rw */ | ||
| 267 | typedef struct { | ||
| 268 | unsigned int crc : 1; | ||
| 269 | unsigned int align : 1; | ||
| 270 | unsigned int oversize : 1; | ||
| 271 | unsigned int congestion : 1; | ||
| 272 | unsigned int single_col : 1; | ||
| 273 | unsigned int mult_col : 1; | ||
| 274 | unsigned int late_col : 1; | ||
| 275 | unsigned int deferred : 1; | ||
| 276 | unsigned int carrier_loss : 1; | ||
| 277 | unsigned int sqe_test_err : 1; | ||
| 278 | unsigned int orun : 1; | ||
| 279 | unsigned int urun : 1; | ||
| 280 | unsigned int exc_col : 1; | ||
| 281 | unsigned int mdio : 1; | ||
| 282 | unsigned int dummy1 : 18; | ||
| 283 | } reg_eth_rw_intr_mask; | ||
| 284 | #define REG_RD_ADDR_eth_rw_intr_mask 76 | ||
| 285 | #define REG_WR_ADDR_eth_rw_intr_mask 76 | ||
| 286 | |||
| 287 | /* Register rw_ack_intr, scope eth, type rw */ | ||
| 288 | typedef struct { | ||
| 289 | unsigned int crc : 1; | ||
| 290 | unsigned int align : 1; | ||
| 291 | unsigned int oversize : 1; | ||
| 292 | unsigned int congestion : 1; | ||
| 293 | unsigned int single_col : 1; | ||
| 294 | unsigned int mult_col : 1; | ||
| 295 | unsigned int late_col : 1; | ||
| 296 | unsigned int deferred : 1; | ||
| 297 | unsigned int carrier_loss : 1; | ||
| 298 | unsigned int sqe_test_err : 1; | ||
| 299 | unsigned int orun : 1; | ||
| 300 | unsigned int urun : 1; | ||
| 301 | unsigned int exc_col : 1; | ||
| 302 | unsigned int mdio : 1; | ||
| 303 | unsigned int dummy1 : 18; | ||
| 304 | } reg_eth_rw_ack_intr; | ||
| 305 | #define REG_RD_ADDR_eth_rw_ack_intr 80 | ||
| 306 | #define REG_WR_ADDR_eth_rw_ack_intr 80 | ||
| 307 | |||
| 308 | /* Register r_intr, scope eth, type r */ | ||
| 309 | typedef struct { | ||
| 310 | unsigned int crc : 1; | ||
| 311 | unsigned int align : 1; | ||
| 312 | unsigned int oversize : 1; | ||
| 313 | unsigned int congestion : 1; | ||
| 314 | unsigned int single_col : 1; | ||
| 315 | unsigned int mult_col : 1; | ||
| 316 | unsigned int late_col : 1; | ||
| 317 | unsigned int deferred : 1; | ||
| 318 | unsigned int carrier_loss : 1; | ||
| 319 | unsigned int sqe_test_err : 1; | ||
| 320 | unsigned int orun : 1; | ||
| 321 | unsigned int urun : 1; | ||
| 322 | unsigned int exc_col : 1; | ||
| 323 | unsigned int mdio : 1; | ||
| 324 | unsigned int dummy1 : 18; | ||
| 325 | } reg_eth_r_intr; | ||
| 326 | #define REG_RD_ADDR_eth_r_intr 84 | ||
| 327 | |||
| 328 | /* Register r_masked_intr, scope eth, type r */ | ||
| 329 | typedef struct { | ||
| 330 | unsigned int crc : 1; | ||
| 331 | unsigned int align : 1; | ||
| 332 | unsigned int oversize : 1; | ||
| 333 | unsigned int congestion : 1; | ||
| 334 | unsigned int single_col : 1; | ||
| 335 | unsigned int mult_col : 1; | ||
| 336 | unsigned int late_col : 1; | ||
| 337 | unsigned int deferred : 1; | ||
| 338 | unsigned int carrier_loss : 1; | ||
| 339 | unsigned int sqe_test_err : 1; | ||
| 340 | unsigned int orun : 1; | ||
| 341 | unsigned int urun : 1; | ||
| 342 | unsigned int exc_col : 1; | ||
| 343 | unsigned int mdio : 1; | ||
| 344 | unsigned int dummy1 : 18; | ||
| 345 | } reg_eth_r_masked_intr; | ||
| 346 | #define REG_RD_ADDR_eth_r_masked_intr 88 | ||
| 347 | |||
| 348 | |||
| 349 | /* Constants */ | ||
| 350 | enum { | ||
| 351 | regk_eth_discard = 0x00000000, | ||
| 352 | regk_eth_ether = 0x00000000, | ||
| 353 | regk_eth_full = 0x00000001, | ||
| 354 | regk_eth_gmii = 0x00000003, | ||
| 355 | regk_eth_gtxclk = 0x00000001, | ||
| 356 | regk_eth_half = 0x00000000, | ||
| 357 | regk_eth_hsh = 0x00000001, | ||
| 358 | regk_eth_mii = 0x00000001, | ||
| 359 | regk_eth_mii_arec = 0x00000002, | ||
| 360 | regk_eth_mii_clk = 0x00000000, | ||
| 361 | regk_eth_no = 0x00000000, | ||
| 362 | regk_eth_phyrst = 0x00000000, | ||
| 363 | regk_eth_rec = 0x00000001, | ||
| 364 | regk_eth_rw_ga_hi_default = 0x00000000, | ||
| 365 | regk_eth_rw_ga_lo_default = 0x00000000, | ||
| 366 | regk_eth_rw_gen_ctrl_default = 0x00000000, | ||
| 367 | regk_eth_rw_intr_mask_default = 0x00000000, | ||
| 368 | regk_eth_rw_ma0_hi_default = 0x00000000, | ||
| 369 | regk_eth_rw_ma0_lo_default = 0x00000000, | ||
| 370 | regk_eth_rw_ma1_hi_default = 0x00000000, | ||
| 371 | regk_eth_rw_ma1_lo_default = 0x00000000, | ||
| 372 | regk_eth_rw_mgm_ctrl_default = 0x00000000, | ||
| 373 | regk_eth_rw_test_ctrl_default = 0x00000000, | ||
| 374 | regk_eth_size1518 = 0x000005ee, | ||
| 375 | regk_eth_size1522 = 0x000005f2, | ||
| 376 | regk_eth_yes = 0x00000001 | ||
| 377 | }; | ||
| 378 | #endif /* __eth_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/include/asm-cris/arch-v32/hwregs/extmem_defs.h deleted file mode 100644 index c47b5ca48ece..000000000000 --- a/include/asm-cris/arch-v32/hwregs/extmem_defs.h +++ /dev/null | |||
| @@ -1,369 +0,0 @@ | |||
| 1 | #ifndef __extmem_defs_h | ||
| 2 | #define __extmem_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/ext_mem/mod/extmem_regs.r | ||
| 7 | * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp | ||
| 8 | * last modfied: Tue Mar 30 22:26:21 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r | ||
| 11 | * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope extmem */ | ||
| 86 | |||
| 87 | /* Register rw_cse0_cfg, scope extmem, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int lw : 6; | ||
| 90 | unsigned int ew : 3; | ||
| 91 | unsigned int zw : 3; | ||
| 92 | unsigned int aw : 2; | ||
| 93 | unsigned int dw : 2; | ||
| 94 | unsigned int ewb : 2; | ||
| 95 | unsigned int bw : 1; | ||
| 96 | unsigned int mode : 1; | ||
| 97 | unsigned int erc_en : 1; | ||
| 98 | unsigned int dummy1 : 6; | ||
| 99 | unsigned int size : 3; | ||
| 100 | unsigned int log : 1; | ||
| 101 | unsigned int en : 1; | ||
| 102 | } reg_extmem_rw_cse0_cfg; | ||
| 103 | #define REG_RD_ADDR_extmem_rw_cse0_cfg 0 | ||
| 104 | #define REG_WR_ADDR_extmem_rw_cse0_cfg 0 | ||
| 105 | |||
| 106 | /* Register rw_cse1_cfg, scope extmem, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int lw : 6; | ||
| 109 | unsigned int ew : 3; | ||
| 110 | unsigned int zw : 3; | ||
| 111 | unsigned int aw : 2; | ||
| 112 | unsigned int dw : 2; | ||
| 113 | unsigned int ewb : 2; | ||
| 114 | unsigned int bw : 1; | ||
| 115 | unsigned int mode : 1; | ||
| 116 | unsigned int erc_en : 1; | ||
| 117 | unsigned int dummy1 : 6; | ||
| 118 | unsigned int size : 3; | ||
| 119 | unsigned int log : 1; | ||
| 120 | unsigned int en : 1; | ||
| 121 | } reg_extmem_rw_cse1_cfg; | ||
| 122 | #define REG_RD_ADDR_extmem_rw_cse1_cfg 4 | ||
| 123 | #define REG_WR_ADDR_extmem_rw_cse1_cfg 4 | ||
| 124 | |||
| 125 | /* Register rw_csr0_cfg, scope extmem, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int lw : 6; | ||
| 128 | unsigned int ew : 3; | ||
| 129 | unsigned int zw : 3; | ||
| 130 | unsigned int aw : 2; | ||
| 131 | unsigned int dw : 2; | ||
| 132 | unsigned int ewb : 2; | ||
| 133 | unsigned int bw : 1; | ||
| 134 | unsigned int mode : 1; | ||
| 135 | unsigned int erc_en : 1; | ||
| 136 | unsigned int dummy1 : 6; | ||
| 137 | unsigned int size : 3; | ||
| 138 | unsigned int log : 1; | ||
| 139 | unsigned int en : 1; | ||
| 140 | } reg_extmem_rw_csr0_cfg; | ||
| 141 | #define REG_RD_ADDR_extmem_rw_csr0_cfg 8 | ||
| 142 | #define REG_WR_ADDR_extmem_rw_csr0_cfg 8 | ||
| 143 | |||
| 144 | /* Register rw_csr1_cfg, scope extmem, type rw */ | ||
| 145 | typedef struct { | ||
| 146 | unsigned int lw : 6; | ||
| 147 | unsigned int ew : 3; | ||
| 148 | unsigned int zw : 3; | ||
| 149 | unsigned int aw : 2; | ||
| 150 | unsigned int dw : 2; | ||
| 151 | unsigned int ewb : 2; | ||
| 152 | unsigned int bw : 1; | ||
| 153 | unsigned int mode : 1; | ||
| 154 | unsigned int erc_en : 1; | ||
| 155 | unsigned int dummy1 : 6; | ||
| 156 | unsigned int size : 3; | ||
| 157 | unsigned int log : 1; | ||
| 158 | unsigned int en : 1; | ||
| 159 | } reg_extmem_rw_csr1_cfg; | ||
| 160 | #define REG_RD_ADDR_extmem_rw_csr1_cfg 12 | ||
| 161 | #define REG_WR_ADDR_extmem_rw_csr1_cfg 12 | ||
| 162 | |||
| 163 | /* Register rw_csp0_cfg, scope extmem, type rw */ | ||
| 164 | typedef struct { | ||
| 165 | unsigned int lw : 6; | ||
| 166 | unsigned int ew : 3; | ||
| 167 | unsigned int zw : 3; | ||
| 168 | unsigned int aw : 2; | ||
| 169 | unsigned int dw : 2; | ||
| 170 | unsigned int ewb : 2; | ||
| 171 | unsigned int bw : 1; | ||
| 172 | unsigned int mode : 1; | ||
| 173 | unsigned int erc_en : 1; | ||
| 174 | unsigned int dummy1 : 6; | ||
| 175 | unsigned int size : 3; | ||
| 176 | unsigned int log : 1; | ||
| 177 | unsigned int en : 1; | ||
| 178 | } reg_extmem_rw_csp0_cfg; | ||
| 179 | #define REG_RD_ADDR_extmem_rw_csp0_cfg 16 | ||
| 180 | #define REG_WR_ADDR_extmem_rw_csp0_cfg 16 | ||
| 181 | |||
| 182 | /* Register rw_csp1_cfg, scope extmem, type rw */ | ||
| 183 | typedef struct { | ||
| 184 | unsigned int lw : 6; | ||
| 185 | unsigned int ew : 3; | ||
| 186 | unsigned int zw : 3; | ||
| 187 | unsigned int aw : 2; | ||
| 188 | unsigned int dw : 2; | ||
| 189 | unsigned int ewb : 2; | ||
| 190 | unsigned int bw : 1; | ||
| 191 | unsigned int mode : 1; | ||
| 192 | unsigned int erc_en : 1; | ||
| 193 | unsigned int dummy1 : 6; | ||
| 194 | unsigned int size : 3; | ||
| 195 | unsigned int log : 1; | ||
| 196 | unsigned int en : 1; | ||
| 197 | } reg_extmem_rw_csp1_cfg; | ||
| 198 | #define REG_RD_ADDR_extmem_rw_csp1_cfg 20 | ||
| 199 | #define REG_WR_ADDR_extmem_rw_csp1_cfg 20 | ||
| 200 | |||
| 201 | /* Register rw_csp2_cfg, scope extmem, type rw */ | ||
| 202 | typedef struct { | ||
| 203 | unsigned int lw : 6; | ||
| 204 | unsigned int ew : 3; | ||
| 205 | unsigned int zw : 3; | ||
| 206 | unsigned int aw : 2; | ||
| 207 | unsigned int dw : 2; | ||
| 208 | unsigned int ewb : 2; | ||
| 209 | unsigned int bw : 1; | ||
| 210 | unsigned int mode : 1; | ||
| 211 | unsigned int erc_en : 1; | ||
| 212 | unsigned int dummy1 : 6; | ||
| 213 | unsigned int size : 3; | ||
| 214 | unsigned int log : 1; | ||
| 215 | unsigned int en : 1; | ||
| 216 | } reg_extmem_rw_csp2_cfg; | ||
| 217 | #define REG_RD_ADDR_extmem_rw_csp2_cfg 24 | ||
| 218 | #define REG_WR_ADDR_extmem_rw_csp2_cfg 24 | ||
| 219 | |||
| 220 | /* Register rw_csp3_cfg, scope extmem, type rw */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int lw : 6; | ||
| 223 | unsigned int ew : 3; | ||
| 224 | unsigned int zw : 3; | ||
| 225 | unsigned int aw : 2; | ||
| 226 | unsigned int dw : 2; | ||
| 227 | unsigned int ewb : 2; | ||
| 228 | unsigned int bw : 1; | ||
| 229 | unsigned int mode : 1; | ||
| 230 | unsigned int erc_en : 1; | ||
| 231 | unsigned int dummy1 : 6; | ||
| 232 | unsigned int size : 3; | ||
| 233 | unsigned int log : 1; | ||
| 234 | unsigned int en : 1; | ||
| 235 | } reg_extmem_rw_csp3_cfg; | ||
| 236 | #define REG_RD_ADDR_extmem_rw_csp3_cfg 28 | ||
| 237 | #define REG_WR_ADDR_extmem_rw_csp3_cfg 28 | ||
| 238 | |||
| 239 | /* Register rw_csp4_cfg, scope extmem, type rw */ | ||
| 240 | typedef struct { | ||
| 241 | unsigned int lw : 6; | ||
| 242 | unsigned int ew : 3; | ||
| 243 | unsigned int zw : 3; | ||
| 244 | unsigned int aw : 2; | ||
| 245 | unsigned int dw : 2; | ||
| 246 | unsigned int ewb : 2; | ||
| 247 | unsigned int bw : 1; | ||
| 248 | unsigned int mode : 1; | ||
| 249 | unsigned int erc_en : 1; | ||
| 250 | unsigned int dummy1 : 6; | ||
| 251 | unsigned int size : 3; | ||
| 252 | unsigned int log : 1; | ||
| 253 | unsigned int en : 1; | ||
| 254 | } reg_extmem_rw_csp4_cfg; | ||
| 255 | #define REG_RD_ADDR_extmem_rw_csp4_cfg 32 | ||
| 256 | #define REG_WR_ADDR_extmem_rw_csp4_cfg 32 | ||
| 257 | |||
| 258 | /* Register rw_csp5_cfg, scope extmem, type rw */ | ||
| 259 | typedef struct { | ||
| 260 | unsigned int lw : 6; | ||
| 261 | unsigned int ew : 3; | ||
| 262 | unsigned int zw : 3; | ||
| 263 | unsigned int aw : 2; | ||
| 264 | unsigned int dw : 2; | ||
| 265 | unsigned int ewb : 2; | ||
| 266 | unsigned int bw : 1; | ||
| 267 | unsigned int mode : 1; | ||
| 268 | unsigned int erc_en : 1; | ||
| 269 | unsigned int dummy1 : 6; | ||
| 270 | unsigned int size : 3; | ||
| 271 | unsigned int log : 1; | ||
| 272 | unsigned int en : 1; | ||
| 273 | } reg_extmem_rw_csp5_cfg; | ||
| 274 | #define REG_RD_ADDR_extmem_rw_csp5_cfg 36 | ||
| 275 | #define REG_WR_ADDR_extmem_rw_csp5_cfg 36 | ||
| 276 | |||
| 277 | /* Register rw_csp6_cfg, scope extmem, type rw */ | ||
| 278 | typedef struct { | ||
| 279 | unsigned int lw : 6; | ||
| 280 | unsigned int ew : 3; | ||
| 281 | unsigned int zw : 3; | ||
| 282 | unsigned int aw : 2; | ||
| 283 | unsigned int dw : 2; | ||
| 284 | unsigned int ewb : 2; | ||
| 285 | unsigned int bw : 1; | ||
| 286 | unsigned int mode : 1; | ||
| 287 | unsigned int erc_en : 1; | ||
| 288 | unsigned int dummy1 : 6; | ||
| 289 | unsigned int size : 3; | ||
| 290 | unsigned int log : 1; | ||
| 291 | unsigned int en : 1; | ||
| 292 | } reg_extmem_rw_csp6_cfg; | ||
| 293 | #define REG_RD_ADDR_extmem_rw_csp6_cfg 40 | ||
| 294 | #define REG_WR_ADDR_extmem_rw_csp6_cfg 40 | ||
| 295 | |||
| 296 | /* Register rw_css_cfg, scope extmem, type rw */ | ||
| 297 | typedef struct { | ||
| 298 | unsigned int lw : 6; | ||
| 299 | unsigned int ew : 3; | ||
| 300 | unsigned int zw : 3; | ||
| 301 | unsigned int aw : 2; | ||
| 302 | unsigned int dw : 2; | ||
| 303 | unsigned int ewb : 2; | ||
| 304 | unsigned int bw : 1; | ||
| 305 | unsigned int mode : 1; | ||
| 306 | unsigned int erc_en : 1; | ||
| 307 | unsigned int dummy1 : 6; | ||
| 308 | unsigned int size : 3; | ||
| 309 | unsigned int log : 1; | ||
| 310 | unsigned int en : 1; | ||
| 311 | } reg_extmem_rw_css_cfg; | ||
| 312 | #define REG_RD_ADDR_extmem_rw_css_cfg 44 | ||
| 313 | #define REG_WR_ADDR_extmem_rw_css_cfg 44 | ||
| 314 | |||
| 315 | /* Register rw_status_handle, scope extmem, type rw */ | ||
| 316 | typedef struct { | ||
| 317 | unsigned int h : 32; | ||
| 318 | } reg_extmem_rw_status_handle; | ||
| 319 | #define REG_RD_ADDR_extmem_rw_status_handle 48 | ||
| 320 | #define REG_WR_ADDR_extmem_rw_status_handle 48 | ||
| 321 | |||
| 322 | /* Register rw_wait_pin, scope extmem, type rw */ | ||
| 323 | typedef struct { | ||
| 324 | unsigned int val : 16; | ||
| 325 | unsigned int dummy1 : 15; | ||
| 326 | unsigned int start : 1; | ||
| 327 | } reg_extmem_rw_wait_pin; | ||
| 328 | #define REG_RD_ADDR_extmem_rw_wait_pin 52 | ||
| 329 | #define REG_WR_ADDR_extmem_rw_wait_pin 52 | ||
| 330 | |||
| 331 | /* Register rw_gated_csp, scope extmem, type rw */ | ||
| 332 | typedef struct { | ||
| 333 | unsigned int dummy1 : 31; | ||
| 334 | unsigned int en : 1; | ||
| 335 | } reg_extmem_rw_gated_csp; | ||
| 336 | #define REG_RD_ADDR_extmem_rw_gated_csp 56 | ||
| 337 | #define REG_WR_ADDR_extmem_rw_gated_csp 56 | ||
| 338 | |||
| 339 | |||
| 340 | /* Constants */ | ||
| 341 | enum { | ||
| 342 | regk_extmem_b16 = 0x00000001, | ||
| 343 | regk_extmem_b32 = 0x00000000, | ||
| 344 | regk_extmem_bwe = 0x00000000, | ||
| 345 | regk_extmem_cwe = 0x00000001, | ||
| 346 | regk_extmem_no = 0x00000000, | ||
| 347 | regk_extmem_rw_cse0_cfg_default = 0x000006cf, | ||
| 348 | regk_extmem_rw_cse1_cfg_default = 0x000006cf, | ||
| 349 | regk_extmem_rw_csp0_cfg_default = 0x000006cf, | ||
| 350 | regk_extmem_rw_csp1_cfg_default = 0x000006cf, | ||
| 351 | regk_extmem_rw_csp2_cfg_default = 0x000006cf, | ||
| 352 | regk_extmem_rw_csp3_cfg_default = 0x000006cf, | ||
| 353 | regk_extmem_rw_csp4_cfg_default = 0x000006cf, | ||
| 354 | regk_extmem_rw_csp5_cfg_default = 0x000006cf, | ||
| 355 | regk_extmem_rw_csp6_cfg_default = 0x000006cf, | ||
| 356 | regk_extmem_rw_csr0_cfg_default = 0x000006cf, | ||
| 357 | regk_extmem_rw_csr1_cfg_default = 0x000006cf, | ||
| 358 | regk_extmem_rw_css_cfg_default = 0x000006cf, | ||
| 359 | regk_extmem_s128KB = 0x00000000, | ||
| 360 | regk_extmem_s16MB = 0x00000005, | ||
| 361 | regk_extmem_s1MB = 0x00000001, | ||
| 362 | regk_extmem_s2MB = 0x00000002, | ||
| 363 | regk_extmem_s32MB = 0x00000006, | ||
| 364 | regk_extmem_s4MB = 0x00000003, | ||
| 365 | regk_extmem_s64MB = 0x00000007, | ||
| 366 | regk_extmem_s8MB = 0x00000004, | ||
| 367 | regk_extmem_yes = 0x00000001 | ||
| 368 | }; | ||
| 369 | #endif /* __extmem_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/gio_defs.h b/include/asm-cris/arch-v32/hwregs/gio_defs.h deleted file mode 100644 index 3e9a0b25366f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/gio_defs.h +++ /dev/null | |||
| @@ -1,295 +0,0 @@ | |||
| 1 | #ifndef __gio_defs_h | ||
| 2 | #define __gio_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/gio/rtl/gio_regs.r | ||
| 7 | * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:07:47 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r | ||
| 11 | * id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope gio */ | ||
| 86 | |||
| 87 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int data : 8; | ||
| 90 | unsigned int dummy1 : 24; | ||
| 91 | } reg_gio_rw_pa_dout; | ||
| 92 | #define REG_RD_ADDR_gio_rw_pa_dout 0 | ||
| 93 | #define REG_WR_ADDR_gio_rw_pa_dout 0 | ||
| 94 | |||
| 95 | /* Register r_pa_din, scope gio, type r */ | ||
| 96 | typedef struct { | ||
| 97 | unsigned int data : 8; | ||
| 98 | unsigned int dummy1 : 24; | ||
| 99 | } reg_gio_r_pa_din; | ||
| 100 | #define REG_RD_ADDR_gio_r_pa_din 4 | ||
| 101 | |||
| 102 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 103 | typedef struct { | ||
| 104 | unsigned int oe : 8; | ||
| 105 | unsigned int dummy1 : 24; | ||
| 106 | } reg_gio_rw_pa_oe; | ||
| 107 | #define REG_RD_ADDR_gio_rw_pa_oe 8 | ||
| 108 | #define REG_WR_ADDR_gio_rw_pa_oe 8 | ||
| 109 | |||
| 110 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int pa0 : 3; | ||
| 113 | unsigned int pa1 : 3; | ||
| 114 | unsigned int pa2 : 3; | ||
| 115 | unsigned int pa3 : 3; | ||
| 116 | unsigned int pa4 : 3; | ||
| 117 | unsigned int pa5 : 3; | ||
| 118 | unsigned int pa6 : 3; | ||
| 119 | unsigned int pa7 : 3; | ||
| 120 | unsigned int dummy1 : 8; | ||
| 121 | } reg_gio_rw_intr_cfg; | ||
| 122 | #define REG_RD_ADDR_gio_rw_intr_cfg 12 | ||
| 123 | #define REG_WR_ADDR_gio_rw_intr_cfg 12 | ||
| 124 | |||
| 125 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int pa0 : 1; | ||
| 128 | unsigned int pa1 : 1; | ||
| 129 | unsigned int pa2 : 1; | ||
| 130 | unsigned int pa3 : 1; | ||
| 131 | unsigned int pa4 : 1; | ||
| 132 | unsigned int pa5 : 1; | ||
| 133 | unsigned int pa6 : 1; | ||
| 134 | unsigned int pa7 : 1; | ||
| 135 | unsigned int dummy1 : 24; | ||
| 136 | } reg_gio_rw_intr_mask; | ||
| 137 | #define REG_RD_ADDR_gio_rw_intr_mask 16 | ||
| 138 | #define REG_WR_ADDR_gio_rw_intr_mask 16 | ||
| 139 | |||
| 140 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 141 | typedef struct { | ||
| 142 | unsigned int pa0 : 1; | ||
| 143 | unsigned int pa1 : 1; | ||
| 144 | unsigned int pa2 : 1; | ||
| 145 | unsigned int pa3 : 1; | ||
| 146 | unsigned int pa4 : 1; | ||
| 147 | unsigned int pa5 : 1; | ||
| 148 | unsigned int pa6 : 1; | ||
| 149 | unsigned int pa7 : 1; | ||
| 150 | unsigned int dummy1 : 24; | ||
| 151 | } reg_gio_rw_ack_intr; | ||
| 152 | #define REG_RD_ADDR_gio_rw_ack_intr 20 | ||
| 153 | #define REG_WR_ADDR_gio_rw_ack_intr 20 | ||
| 154 | |||
| 155 | /* Register r_intr, scope gio, type r */ | ||
| 156 | typedef struct { | ||
| 157 | unsigned int pa0 : 1; | ||
| 158 | unsigned int pa1 : 1; | ||
| 159 | unsigned int pa2 : 1; | ||
| 160 | unsigned int pa3 : 1; | ||
| 161 | unsigned int pa4 : 1; | ||
| 162 | unsigned int pa5 : 1; | ||
| 163 | unsigned int pa6 : 1; | ||
| 164 | unsigned int pa7 : 1; | ||
| 165 | unsigned int dummy1 : 24; | ||
| 166 | } reg_gio_r_intr; | ||
| 167 | #define REG_RD_ADDR_gio_r_intr 24 | ||
| 168 | |||
| 169 | /* Register r_masked_intr, scope gio, type r */ | ||
| 170 | typedef struct { | ||
| 171 | unsigned int pa0 : 1; | ||
| 172 | unsigned int pa1 : 1; | ||
| 173 | unsigned int pa2 : 1; | ||
| 174 | unsigned int pa3 : 1; | ||
| 175 | unsigned int pa4 : 1; | ||
| 176 | unsigned int pa5 : 1; | ||
| 177 | unsigned int pa6 : 1; | ||
| 178 | unsigned int pa7 : 1; | ||
| 179 | unsigned int dummy1 : 24; | ||
| 180 | } reg_gio_r_masked_intr; | ||
| 181 | #define REG_RD_ADDR_gio_r_masked_intr 28 | ||
| 182 | |||
| 183 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int data : 18; | ||
| 186 | unsigned int dummy1 : 14; | ||
| 187 | } reg_gio_rw_pb_dout; | ||
| 188 | #define REG_RD_ADDR_gio_rw_pb_dout 32 | ||
| 189 | #define REG_WR_ADDR_gio_rw_pb_dout 32 | ||
| 190 | |||
| 191 | /* Register r_pb_din, scope gio, type r */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int data : 18; | ||
| 194 | unsigned int dummy1 : 14; | ||
| 195 | } reg_gio_r_pb_din; | ||
| 196 | #define REG_RD_ADDR_gio_r_pb_din 36 | ||
| 197 | |||
| 198 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 199 | typedef struct { | ||
| 200 | unsigned int oe : 18; | ||
| 201 | unsigned int dummy1 : 14; | ||
| 202 | } reg_gio_rw_pb_oe; | ||
| 203 | #define REG_RD_ADDR_gio_rw_pb_oe 40 | ||
| 204 | #define REG_WR_ADDR_gio_rw_pb_oe 40 | ||
| 205 | |||
| 206 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 207 | typedef struct { | ||
| 208 | unsigned int data : 18; | ||
| 209 | unsigned int dummy1 : 14; | ||
| 210 | } reg_gio_rw_pc_dout; | ||
| 211 | #define REG_RD_ADDR_gio_rw_pc_dout 48 | ||
| 212 | #define REG_WR_ADDR_gio_rw_pc_dout 48 | ||
| 213 | |||
| 214 | /* Register r_pc_din, scope gio, type r */ | ||
| 215 | typedef struct { | ||
| 216 | unsigned int data : 18; | ||
| 217 | unsigned int dummy1 : 14; | ||
| 218 | } reg_gio_r_pc_din; | ||
| 219 | #define REG_RD_ADDR_gio_r_pc_din 52 | ||
| 220 | |||
| 221 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 222 | typedef struct { | ||
| 223 | unsigned int oe : 18; | ||
| 224 | unsigned int dummy1 : 14; | ||
| 225 | } reg_gio_rw_pc_oe; | ||
| 226 | #define REG_RD_ADDR_gio_rw_pc_oe 56 | ||
| 227 | #define REG_WR_ADDR_gio_rw_pc_oe 56 | ||
| 228 | |||
| 229 | /* Register rw_pd_dout, scope gio, type rw */ | ||
| 230 | typedef struct { | ||
| 231 | unsigned int data : 18; | ||
| 232 | unsigned int dummy1 : 14; | ||
| 233 | } reg_gio_rw_pd_dout; | ||
| 234 | #define REG_RD_ADDR_gio_rw_pd_dout 64 | ||
| 235 | #define REG_WR_ADDR_gio_rw_pd_dout 64 | ||
| 236 | |||
| 237 | /* Register r_pd_din, scope gio, type r */ | ||
| 238 | typedef struct { | ||
| 239 | unsigned int data : 18; | ||
| 240 | unsigned int dummy1 : 14; | ||
| 241 | } reg_gio_r_pd_din; | ||
| 242 | #define REG_RD_ADDR_gio_r_pd_din 68 | ||
| 243 | |||
| 244 | /* Register rw_pd_oe, scope gio, type rw */ | ||
| 245 | typedef struct { | ||
| 246 | unsigned int oe : 18; | ||
| 247 | unsigned int dummy1 : 14; | ||
| 248 | } reg_gio_rw_pd_oe; | ||
| 249 | #define REG_RD_ADDR_gio_rw_pd_oe 72 | ||
| 250 | #define REG_WR_ADDR_gio_rw_pd_oe 72 | ||
| 251 | |||
| 252 | /* Register rw_pe_dout, scope gio, type rw */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int data : 18; | ||
| 255 | unsigned int dummy1 : 14; | ||
| 256 | } reg_gio_rw_pe_dout; | ||
| 257 | #define REG_RD_ADDR_gio_rw_pe_dout 80 | ||
| 258 | #define REG_WR_ADDR_gio_rw_pe_dout 80 | ||
| 259 | |||
| 260 | /* Register r_pe_din, scope gio, type r */ | ||
| 261 | typedef struct { | ||
| 262 | unsigned int data : 18; | ||
| 263 | unsigned int dummy1 : 14; | ||
| 264 | } reg_gio_r_pe_din; | ||
| 265 | #define REG_RD_ADDR_gio_r_pe_din 84 | ||
| 266 | |||
| 267 | /* Register rw_pe_oe, scope gio, type rw */ | ||
| 268 | typedef struct { | ||
| 269 | unsigned int oe : 18; | ||
| 270 | unsigned int dummy1 : 14; | ||
| 271 | } reg_gio_rw_pe_oe; | ||
| 272 | #define REG_RD_ADDR_gio_rw_pe_oe 88 | ||
| 273 | #define REG_WR_ADDR_gio_rw_pe_oe 88 | ||
| 274 | |||
| 275 | |||
| 276 | /* Constants */ | ||
| 277 | enum { | ||
| 278 | regk_gio_anyedge = 0x00000007, | ||
| 279 | regk_gio_hi = 0x00000001, | ||
| 280 | regk_gio_lo = 0x00000002, | ||
| 281 | regk_gio_negedge = 0x00000006, | ||
| 282 | regk_gio_no = 0x00000000, | ||
| 283 | regk_gio_off = 0x00000000, | ||
| 284 | regk_gio_posedge = 0x00000005, | ||
| 285 | regk_gio_rw_intr_cfg_default = 0x00000000, | ||
| 286 | regk_gio_rw_intr_mask_default = 0x00000000, | ||
| 287 | regk_gio_rw_pa_oe_default = 0x00000000, | ||
| 288 | regk_gio_rw_pb_oe_default = 0x00000000, | ||
| 289 | regk_gio_rw_pc_oe_default = 0x00000000, | ||
| 290 | regk_gio_rw_pd_oe_default = 0x00000000, | ||
| 291 | regk_gio_rw_pe_oe_default = 0x00000000, | ||
| 292 | regk_gio_set = 0x00000003, | ||
| 293 | regk_gio_yes = 0x00000001 | ||
| 294 | }; | ||
| 295 | #endif /* __gio_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h deleted file mode 100644 index 5c1b28fb205d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/intr_vect.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version | ||
| 2 | from ../../inst/intr_vect/rtl/guinness/ivmask.config.r | ||
| 3 | version . */ | ||
| 4 | |||
| 5 | #ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R | ||
| 6 | #define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R | ||
| 7 | #define MEMARB_INTR_VECT 0x31 | ||
| 8 | #define GEN_IO_INTR_VECT 0x32 | ||
| 9 | #define IOP0_INTR_VECT 0x33 | ||
| 10 | #define IOP1_INTR_VECT 0x34 | ||
| 11 | #define IOP2_INTR_VECT 0x35 | ||
| 12 | #define IOP3_INTR_VECT 0x36 | ||
| 13 | #define DMA0_INTR_VECT 0x37 | ||
| 14 | #define DMA1_INTR_VECT 0x38 | ||
| 15 | #define DMA2_INTR_VECT 0x39 | ||
| 16 | #define DMA3_INTR_VECT 0x3a | ||
| 17 | #define DMA4_INTR_VECT 0x3b | ||
| 18 | #define DMA5_INTR_VECT 0x3c | ||
| 19 | #define DMA6_INTR_VECT 0x3d | ||
| 20 | #define DMA7_INTR_VECT 0x3e | ||
| 21 | #define DMA8_INTR_VECT 0x3f | ||
| 22 | #define DMA9_INTR_VECT 0x40 | ||
| 23 | #define ATA_INTR_VECT 0x41 | ||
| 24 | #define SSER0_INTR_VECT 0x42 | ||
| 25 | #define SSER1_INTR_VECT 0x43 | ||
| 26 | #define SER0_INTR_VECT 0x44 | ||
| 27 | #define SER1_INTR_VECT 0x45 | ||
| 28 | #define SER2_INTR_VECT 0x46 | ||
| 29 | #define SER3_INTR_VECT 0x47 | ||
| 30 | #define P21_INTR_VECT 0x48 | ||
| 31 | #define ETH0_INTR_VECT 0x49 | ||
| 32 | #define ETH1_INTR_VECT 0x4a | ||
| 33 | #define TIMER_INTR_VECT 0x4b | ||
| 34 | #define BIF_ARB_INTR_VECT 0x4c | ||
| 35 | #define BIF_DMA_INTR_VECT 0x4d | ||
| 36 | #define EXT_INTR_VECT 0x4e | ||
| 37 | #define IPI_INTR_VECT 0x4f | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/Makefile b/include/asm-cris/arch-v32/hwregs/iop/Makefile deleted file mode 100644 index a90056a095e3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/Makefile +++ /dev/null | |||
| @@ -1,146 +0,0 @@ | |||
| 1 | # $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ | ||
| 2 | # Makefile to generate or copy the latest register definitions | ||
| 3 | # and related datastructures and helpermacros. | ||
| 4 | # The offical place for these files is probably at: | ||
| 5 | RELEASE ?= r1_alfa5 | ||
| 6 | IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ | ||
| 7 | |||
| 8 | IOPROCDIR = /n/asic/design/io/io_proc/rtl | ||
| 9 | |||
| 10 | IOPROCINCL_FILES = | ||
| 11 | IOPROCINCL_FILES2= | ||
| 12 | IOPROCINCL_FILES += iop_crc_par_defs.h | ||
| 13 | IOPROCINCL_FILES += iop_dmc_in_defs.h | ||
| 14 | IOPROCINCL_FILES += iop_dmc_out_defs.h | ||
| 15 | IOPROCINCL_FILES += iop_fifo_in_defs.h | ||
| 16 | IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h | ||
| 17 | IOPROCINCL_FILES += iop_fifo_out_defs.h | ||
| 18 | IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h | ||
| 19 | IOPROCINCL_FILES += iop_mpu_defs.h | ||
| 20 | IOPROCINCL_FILES2+= iop_mpu_macros.h | ||
| 21 | IOPROCINCL_FILES2+= iop_reg_space.h | ||
| 22 | IOPROCINCL_FILES += iop_sap_in_defs.h | ||
| 23 | IOPROCINCL_FILES += iop_sap_out_defs.h | ||
| 24 | IOPROCINCL_FILES += iop_scrc_in_defs.h | ||
| 25 | IOPROCINCL_FILES += iop_scrc_out_defs.h | ||
| 26 | IOPROCINCL_FILES += iop_spu_defs.h | ||
| 27 | # in guiness/ | ||
| 28 | IOPROCINCL_FILES += iop_sw_cfg_defs.h | ||
| 29 | IOPROCINCL_FILES += iop_sw_cpu_defs.h | ||
| 30 | IOPROCINCL_FILES += iop_sw_mpu_defs.h | ||
| 31 | IOPROCINCL_FILES += iop_sw_spu_defs.h | ||
| 32 | # | ||
| 33 | IOPROCINCL_FILES += iop_timer_grp_defs.h | ||
| 34 | IOPROCINCL_FILES += iop_trigger_grp_defs.h | ||
| 35 | # in guiness/ | ||
| 36 | IOPROCINCL_FILES += iop_version_defs.h | ||
| 37 | |||
| 38 | IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES)) | ||
| 39 | IOPROCASMINCL_FILES+= iop_reg_space_asm.h | ||
| 40 | |||
| 41 | |||
| 42 | IOPROCREGDESC = | ||
| 43 | IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r | ||
| 44 | #IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r | ||
| 45 | IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r | ||
| 46 | IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r | ||
| 47 | IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r | ||
| 48 | IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r | ||
| 49 | IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r | ||
| 50 | IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r | ||
| 51 | IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r | ||
| 52 | IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r | ||
| 53 | IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r | ||
| 54 | IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r | ||
| 55 | IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r | ||
| 56 | IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r | ||
| 57 | IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r | ||
| 58 | IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r | ||
| 59 | IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r | ||
| 60 | IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r | ||
| 61 | IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r | ||
| 62 | IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r | ||
| 63 | IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r | ||
| 64 | |||
| 65 | |||
| 66 | RDES2C = /n/asic/bin/rdes2c | ||
| 67 | RDES2C = /n/asic/design/tools/rdesc/rdes2c | ||
| 68 | RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr | ||
| 69 | RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt | ||
| 70 | |||
| 71 | ## all - Just print help - you probably want to do 'make gen' | ||
| 72 | all: help | ||
| 73 | |||
| 74 | ## help - This help | ||
| 75 | help: | ||
| 76 | @grep '^## ' Makefile | ||
| 77 | |||
| 78 | ## gen - Generate include files | ||
| 79 | gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) | ||
| 80 | echo "INCL: $(IOPROCINCL_FILES)" | ||
| 81 | echo "INCL2: $(IOPROCINCL_FILES2)" | ||
| 82 | echo "ASMINCL: $(IOPROCASMINCL_FILES)" | ||
| 83 | |||
| 84 | # From the official location... | ||
| 85 | iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h | ||
| 86 | cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ | ||
| 87 | iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h | ||
| 88 | cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ | ||
| 89 | |||
| 90 | ## copy - Copy files from official location | ||
| 91 | copy: | ||
| 92 | @echo "## Copying and fixing iop files ##" | ||
| 93 | @for HFILE in $(IOPROCINCL_FILES); do \ | ||
| 94 | echo " $$HFILE"; \ | ||
| 95 | cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ | ||
| 96 | done | ||
| 97 | @for HFILE in $(IOPROCINCL_FILES2); do \ | ||
| 98 | echo " $$HFILE"; \ | ||
| 99 | cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ | ||
| 100 | done | ||
| 101 | @echo "## Copying and fixing iop asm files ##" | ||
| 102 | @for HFILE in $(IOPROCASMINCL_FILES); do \ | ||
| 103 | echo " $$HFILE"; \ | ||
| 104 | cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \ | ||
| 105 | done | ||
| 106 | |||
| 107 | # I/O processor files: | ||
| 108 | ## iop - Generate I/O processor include files | ||
| 109 | iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) | ||
| 110 | iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r | ||
| 111 | $(RDES2C) $< | ||
| 112 | iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r | ||
| 113 | $(RDES2C) $< | ||
| 114 | %_defs.h: $(IOPROCDIR)/%.r | ||
| 115 | $(RDES2C) $< | ||
| 116 | %_defs_asm.h: $(IOPROCDIR)/%.r | ||
| 117 | $(RDES2C) -asm $< | ||
| 118 | iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r | ||
| 119 | $(RDES2C) -asm $< | ||
| 120 | |||
| 121 | ## doc - Generate .axw files from register description. | ||
| 122 | doc: $(IOPROCREGDESC) | ||
| 123 | for RDES in $^; do \ | ||
| 124 | $(RDES2TXT) $$RDES; \ | ||
| 125 | done | ||
| 126 | |||
| 127 | .PHONY: axw | ||
| 128 | ## %.axw - Generate the specified .axw file (doesn't work for all files | ||
| 129 | ## due to inconsistent naming of .r files. | ||
| 130 | %.axw: axw | ||
| 131 | @for RDES in $(IOPROCREGDESC); do \ | ||
| 132 | if echo "$$RDES" | grep $* ; then \ | ||
| 133 | $(RDES2TXT) $$RDES; \ | ||
| 134 | fi \ | ||
| 135 | done | ||
| 136 | |||
| 137 | .PHONY: clean | ||
| 138 | ## clean - Remove .h files and .axw files. | ||
| 139 | clean: | ||
| 140 | rm -rf $(IOPROCINCL_FILES) *.axw | ||
| 141 | |||
| 142 | .PHONY: cleandoc | ||
| 143 | ## cleandoc - Remove .axw files. | ||
| 144 | cleandoc: | ||
| 145 | rm -rf *.axw | ||
| 146 | |||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h deleted file mode 100644 index a4b58000c164..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h +++ /dev/null | |||
| @@ -1,171 +0,0 @@ | |||
| 1 | #ifndef __iop_crc_par_defs_asm_h | ||
| 2 | #define __iop_crc_par_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_crc_par.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r | ||
| 11 | * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope iop_crc_par, type rw */ | ||
| 57 | #define reg_iop_crc_par_rw_cfg___mode___lsb 0 | ||
| 58 | #define reg_iop_crc_par_rw_cfg___mode___width 1 | ||
| 59 | #define reg_iop_crc_par_rw_cfg___mode___bit 0 | ||
| 60 | #define reg_iop_crc_par_rw_cfg___crc_out___lsb 1 | ||
| 61 | #define reg_iop_crc_par_rw_cfg___crc_out___width 1 | ||
| 62 | #define reg_iop_crc_par_rw_cfg___crc_out___bit 1 | ||
| 63 | #define reg_iop_crc_par_rw_cfg___rev_out___lsb 2 | ||
| 64 | #define reg_iop_crc_par_rw_cfg___rev_out___width 1 | ||
| 65 | #define reg_iop_crc_par_rw_cfg___rev_out___bit 2 | ||
| 66 | #define reg_iop_crc_par_rw_cfg___inv_out___lsb 3 | ||
| 67 | #define reg_iop_crc_par_rw_cfg___inv_out___width 1 | ||
| 68 | #define reg_iop_crc_par_rw_cfg___inv_out___bit 3 | ||
| 69 | #define reg_iop_crc_par_rw_cfg___trig___lsb 4 | ||
| 70 | #define reg_iop_crc_par_rw_cfg___trig___width 2 | ||
| 71 | #define reg_iop_crc_par_rw_cfg___poly___lsb 6 | ||
| 72 | #define reg_iop_crc_par_rw_cfg___poly___width 3 | ||
| 73 | #define reg_iop_crc_par_rw_cfg_offset 0 | ||
| 74 | |||
| 75 | /* Register rw_init_crc, scope iop_crc_par, type rw */ | ||
| 76 | #define reg_iop_crc_par_rw_init_crc_offset 4 | ||
| 77 | |||
| 78 | /* Register rw_correct_crc, scope iop_crc_par, type rw */ | ||
| 79 | #define reg_iop_crc_par_rw_correct_crc_offset 8 | ||
| 80 | |||
| 81 | /* Register rw_ctrl, scope iop_crc_par, type rw */ | ||
| 82 | #define reg_iop_crc_par_rw_ctrl___en___lsb 0 | ||
| 83 | #define reg_iop_crc_par_rw_ctrl___en___width 1 | ||
| 84 | #define reg_iop_crc_par_rw_ctrl___en___bit 0 | ||
| 85 | #define reg_iop_crc_par_rw_ctrl_offset 12 | ||
| 86 | |||
| 87 | /* Register rw_set_last, scope iop_crc_par, type rw */ | ||
| 88 | #define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0 | ||
| 89 | #define reg_iop_crc_par_rw_set_last___tr_dif___width 1 | ||
| 90 | #define reg_iop_crc_par_rw_set_last___tr_dif___bit 0 | ||
| 91 | #define reg_iop_crc_par_rw_set_last_offset 16 | ||
| 92 | |||
| 93 | /* Register rw_wr1byte, scope iop_crc_par, type rw */ | ||
| 94 | #define reg_iop_crc_par_rw_wr1byte___data___lsb 0 | ||
| 95 | #define reg_iop_crc_par_rw_wr1byte___data___width 8 | ||
| 96 | #define reg_iop_crc_par_rw_wr1byte_offset 20 | ||
| 97 | |||
| 98 | /* Register rw_wr2byte, scope iop_crc_par, type rw */ | ||
| 99 | #define reg_iop_crc_par_rw_wr2byte___data___lsb 0 | ||
| 100 | #define reg_iop_crc_par_rw_wr2byte___data___width 16 | ||
| 101 | #define reg_iop_crc_par_rw_wr2byte_offset 24 | ||
| 102 | |||
| 103 | /* Register rw_wr3byte, scope iop_crc_par, type rw */ | ||
| 104 | #define reg_iop_crc_par_rw_wr3byte___data___lsb 0 | ||
| 105 | #define reg_iop_crc_par_rw_wr3byte___data___width 24 | ||
| 106 | #define reg_iop_crc_par_rw_wr3byte_offset 28 | ||
| 107 | |||
| 108 | /* Register rw_wr4byte, scope iop_crc_par, type rw */ | ||
| 109 | #define reg_iop_crc_par_rw_wr4byte___data___lsb 0 | ||
| 110 | #define reg_iop_crc_par_rw_wr4byte___data___width 32 | ||
| 111 | #define reg_iop_crc_par_rw_wr4byte_offset 32 | ||
| 112 | |||
| 113 | /* Register rw_wr1byte_last, scope iop_crc_par, type rw */ | ||
| 114 | #define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0 | ||
| 115 | #define reg_iop_crc_par_rw_wr1byte_last___data___width 8 | ||
| 116 | #define reg_iop_crc_par_rw_wr1byte_last_offset 36 | ||
| 117 | |||
| 118 | /* Register rw_wr2byte_last, scope iop_crc_par, type rw */ | ||
| 119 | #define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0 | ||
| 120 | #define reg_iop_crc_par_rw_wr2byte_last___data___width 16 | ||
| 121 | #define reg_iop_crc_par_rw_wr2byte_last_offset 40 | ||
| 122 | |||
| 123 | /* Register rw_wr3byte_last, scope iop_crc_par, type rw */ | ||
| 124 | #define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0 | ||
| 125 | #define reg_iop_crc_par_rw_wr3byte_last___data___width 24 | ||
| 126 | #define reg_iop_crc_par_rw_wr3byte_last_offset 44 | ||
| 127 | |||
| 128 | /* Register rw_wr4byte_last, scope iop_crc_par, type rw */ | ||
| 129 | #define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0 | ||
| 130 | #define reg_iop_crc_par_rw_wr4byte_last___data___width 32 | ||
| 131 | #define reg_iop_crc_par_rw_wr4byte_last_offset 48 | ||
| 132 | |||
| 133 | /* Register r_stat, scope iop_crc_par, type r */ | ||
| 134 | #define reg_iop_crc_par_r_stat___err___lsb 0 | ||
| 135 | #define reg_iop_crc_par_r_stat___err___width 1 | ||
| 136 | #define reg_iop_crc_par_r_stat___err___bit 0 | ||
| 137 | #define reg_iop_crc_par_r_stat___busy___lsb 1 | ||
| 138 | #define reg_iop_crc_par_r_stat___busy___width 1 | ||
| 139 | #define reg_iop_crc_par_r_stat___busy___bit 1 | ||
| 140 | #define reg_iop_crc_par_r_stat_offset 52 | ||
| 141 | |||
| 142 | /* Register r_sh_reg, scope iop_crc_par, type r */ | ||
| 143 | #define reg_iop_crc_par_r_sh_reg_offset 56 | ||
| 144 | |||
| 145 | /* Register r_crc, scope iop_crc_par, type r */ | ||
| 146 | #define reg_iop_crc_par_r_crc_offset 60 | ||
| 147 | |||
| 148 | /* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ | ||
| 149 | #define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0 | ||
| 150 | #define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2 | ||
| 151 | #define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64 | ||
| 152 | |||
| 153 | |||
| 154 | /* Constants */ | ||
| 155 | #define regk_iop_crc_par_calc 0x00000001 | ||
| 156 | #define regk_iop_crc_par_ccitt 0x00000002 | ||
| 157 | #define regk_iop_crc_par_check 0x00000000 | ||
| 158 | #define regk_iop_crc_par_crc16 0x00000001 | ||
| 159 | #define regk_iop_crc_par_crc32 0x00000000 | ||
| 160 | #define regk_iop_crc_par_crc5 0x00000003 | ||
| 161 | #define regk_iop_crc_par_crc5_11 0x00000004 | ||
| 162 | #define regk_iop_crc_par_dif_in 0x00000002 | ||
| 163 | #define regk_iop_crc_par_hi 0x00000000 | ||
| 164 | #define regk_iop_crc_par_neg 0x00000002 | ||
| 165 | #define regk_iop_crc_par_no 0x00000000 | ||
| 166 | #define regk_iop_crc_par_pos 0x00000001 | ||
| 167 | #define regk_iop_crc_par_pos_neg 0x00000003 | ||
| 168 | #define regk_iop_crc_par_rw_cfg_default 0x00000000 | ||
| 169 | #define regk_iop_crc_par_rw_ctrl_default 0x00000000 | ||
| 170 | #define regk_iop_crc_par_yes 0x00000001 | ||
| 171 | #endif /* __iop_crc_par_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h deleted file mode 100644 index e7d539feccb1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h +++ /dev/null | |||
| @@ -1,321 +0,0 @@ | |||
| 1 | #ifndef __iop_dmc_in_defs_asm_h | ||
| 2 | #define __iop_dmc_in_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_dmc_in.r | ||
| 7 | * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r | ||
| 11 | * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope iop_dmc_in, type rw */ | ||
| 57 | #define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0 | ||
| 58 | #define reg_iop_dmc_in_rw_cfg___sth_intr___width 3 | ||
| 59 | #define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3 | ||
| 60 | #define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1 | ||
| 61 | #define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3 | ||
| 62 | #define reg_iop_dmc_in_rw_cfg_offset 0 | ||
| 63 | |||
| 64 | /* Register rw_ctrl, scope iop_dmc_in, type rw */ | ||
| 65 | #define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0 | ||
| 66 | #define reg_iop_dmc_in_rw_ctrl___dif_en___width 1 | ||
| 67 | #define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0 | ||
| 68 | #define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1 | ||
| 69 | #define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1 | ||
| 70 | #define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1 | ||
| 71 | #define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2 | ||
| 72 | #define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1 | ||
| 73 | #define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2 | ||
| 74 | #define reg_iop_dmc_in_rw_ctrl_offset 4 | ||
| 75 | |||
| 76 | /* Register r_stat, scope iop_dmc_in, type r */ | ||
| 77 | #define reg_iop_dmc_in_r_stat___dif_en___lsb 0 | ||
| 78 | #define reg_iop_dmc_in_r_stat___dif_en___width 1 | ||
| 79 | #define reg_iop_dmc_in_r_stat___dif_en___bit 0 | ||
| 80 | #define reg_iop_dmc_in_r_stat_offset 8 | ||
| 81 | |||
| 82 | /* Register rw_stream_cmd, scope iop_dmc_in, type rw */ | ||
| 83 | #define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0 | ||
| 84 | #define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10 | ||
| 85 | #define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16 | ||
| 86 | #define reg_iop_dmc_in_rw_stream_cmd___n___width 8 | ||
| 87 | #define reg_iop_dmc_in_rw_stream_cmd_offset 12 | ||
| 88 | |||
| 89 | /* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ | ||
| 90 | #define reg_iop_dmc_in_rw_stream_wr_data_offset 16 | ||
| 91 | |||
| 92 | /* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ | ||
| 93 | #define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20 | ||
| 94 | |||
| 95 | /* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ | ||
| 96 | #define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0 | ||
| 97 | #define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1 | ||
| 98 | #define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0 | ||
| 99 | #define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1 | ||
| 100 | #define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1 | ||
| 101 | #define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1 | ||
| 102 | #define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2 | ||
| 103 | #define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1 | ||
| 104 | #define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2 | ||
| 105 | #define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3 | ||
| 106 | #define reg_iop_dmc_in_rw_stream_ctrl___size___width 3 | ||
| 107 | #define reg_iop_dmc_in_rw_stream_ctrl_offset 24 | ||
| 108 | |||
| 109 | /* Register r_stream_stat, scope iop_dmc_in, type r */ | ||
| 110 | #define reg_iop_dmc_in_r_stream_stat___sth___lsb 0 | ||
| 111 | #define reg_iop_dmc_in_r_stream_stat___sth___width 7 | ||
| 112 | #define reg_iop_dmc_in_r_stream_stat___full___lsb 16 | ||
| 113 | #define reg_iop_dmc_in_r_stream_stat___full___width 1 | ||
| 114 | #define reg_iop_dmc_in_r_stream_stat___full___bit 16 | ||
| 115 | #define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17 | ||
| 116 | #define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1 | ||
| 117 | #define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17 | ||
| 118 | #define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18 | ||
| 119 | #define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1 | ||
| 120 | #define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18 | ||
| 121 | #define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19 | ||
| 122 | #define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1 | ||
| 123 | #define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19 | ||
| 124 | #define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20 | ||
| 125 | #define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1 | ||
| 126 | #define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20 | ||
| 127 | #define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21 | ||
| 128 | #define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1 | ||
| 129 | #define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21 | ||
| 130 | #define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22 | ||
| 131 | #define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1 | ||
| 132 | #define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22 | ||
| 133 | #define reg_iop_dmc_in_r_stream_stat_offset 28 | ||
| 134 | |||
| 135 | /* Register r_data_descr, scope iop_dmc_in, type r */ | ||
| 136 | #define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0 | ||
| 137 | #define reg_iop_dmc_in_r_data_descr___ctrl___width 8 | ||
| 138 | #define reg_iop_dmc_in_r_data_descr___stat___lsb 8 | ||
| 139 | #define reg_iop_dmc_in_r_data_descr___stat___width 8 | ||
| 140 | #define reg_iop_dmc_in_r_data_descr___md___lsb 16 | ||
| 141 | #define reg_iop_dmc_in_r_data_descr___md___width 16 | ||
| 142 | #define reg_iop_dmc_in_r_data_descr_offset 32 | ||
| 143 | |||
| 144 | /* Register r_ctxt_descr, scope iop_dmc_in, type r */ | ||
| 145 | #define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0 | ||
| 146 | #define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8 | ||
| 147 | #define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8 | ||
| 148 | #define reg_iop_dmc_in_r_ctxt_descr___stat___width 8 | ||
| 149 | #define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16 | ||
| 150 | #define reg_iop_dmc_in_r_ctxt_descr___md0___width 16 | ||
| 151 | #define reg_iop_dmc_in_r_ctxt_descr_offset 36 | ||
| 152 | |||
| 153 | /* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ | ||
| 154 | #define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40 | ||
| 155 | |||
| 156 | /* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ | ||
| 157 | #define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44 | ||
| 158 | |||
| 159 | /* Register r_group_descr, scope iop_dmc_in, type r */ | ||
| 160 | #define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0 | ||
| 161 | #define reg_iop_dmc_in_r_group_descr___ctrl___width 8 | ||
| 162 | #define reg_iop_dmc_in_r_group_descr___stat___lsb 8 | ||
| 163 | #define reg_iop_dmc_in_r_group_descr___stat___width 8 | ||
| 164 | #define reg_iop_dmc_in_r_group_descr___md___lsb 16 | ||
| 165 | #define reg_iop_dmc_in_r_group_descr___md___width 16 | ||
| 166 | #define reg_iop_dmc_in_r_group_descr_offset 56 | ||
| 167 | |||
| 168 | /* Register rw_data_descr, scope iop_dmc_in, type rw */ | ||
| 169 | #define reg_iop_dmc_in_rw_data_descr___md___lsb 16 | ||
| 170 | #define reg_iop_dmc_in_rw_data_descr___md___width 16 | ||
| 171 | #define reg_iop_dmc_in_rw_data_descr_offset 60 | ||
| 172 | |||
| 173 | /* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ | ||
| 174 | #define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16 | ||
| 175 | #define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16 | ||
| 176 | #define reg_iop_dmc_in_rw_ctxt_descr_offset 64 | ||
| 177 | |||
| 178 | /* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ | ||
| 179 | #define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68 | ||
| 180 | |||
| 181 | /* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ | ||
| 182 | #define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72 | ||
| 183 | |||
| 184 | /* Register rw_group_descr, scope iop_dmc_in, type rw */ | ||
| 185 | #define reg_iop_dmc_in_rw_group_descr___md___lsb 16 | ||
| 186 | #define reg_iop_dmc_in_rw_group_descr___md___width 16 | ||
| 187 | #define reg_iop_dmc_in_rw_group_descr_offset 84 | ||
| 188 | |||
| 189 | /* Register rw_intr_mask, scope iop_dmc_in, type rw */ | ||
| 190 | #define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0 | ||
| 191 | #define reg_iop_dmc_in_rw_intr_mask___data_md___width 1 | ||
| 192 | #define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0 | ||
| 193 | #define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1 | ||
| 194 | #define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1 | ||
| 195 | #define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1 | ||
| 196 | #define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2 | ||
| 197 | #define reg_iop_dmc_in_rw_intr_mask___group_md___width 1 | ||
| 198 | #define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2 | ||
| 199 | #define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3 | ||
| 200 | #define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1 | ||
| 201 | #define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3 | ||
| 202 | #define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4 | ||
| 203 | #define reg_iop_dmc_in_rw_intr_mask___sth___width 1 | ||
| 204 | #define reg_iop_dmc_in_rw_intr_mask___sth___bit 4 | ||
| 205 | #define reg_iop_dmc_in_rw_intr_mask___full___lsb 5 | ||
| 206 | #define reg_iop_dmc_in_rw_intr_mask___full___width 1 | ||
| 207 | #define reg_iop_dmc_in_rw_intr_mask___full___bit 5 | ||
| 208 | #define reg_iop_dmc_in_rw_intr_mask_offset 88 | ||
| 209 | |||
| 210 | /* Register rw_ack_intr, scope iop_dmc_in, type rw */ | ||
| 211 | #define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0 | ||
| 212 | #define reg_iop_dmc_in_rw_ack_intr___data_md___width 1 | ||
| 213 | #define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0 | ||
| 214 | #define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1 | ||
| 215 | #define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1 | ||
| 216 | #define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1 | ||
| 217 | #define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2 | ||
| 218 | #define reg_iop_dmc_in_rw_ack_intr___group_md___width 1 | ||
| 219 | #define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2 | ||
| 220 | #define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3 | ||
| 221 | #define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1 | ||
| 222 | #define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3 | ||
| 223 | #define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4 | ||
| 224 | #define reg_iop_dmc_in_rw_ack_intr___sth___width 1 | ||
| 225 | #define reg_iop_dmc_in_rw_ack_intr___sth___bit 4 | ||
| 226 | #define reg_iop_dmc_in_rw_ack_intr___full___lsb 5 | ||
| 227 | #define reg_iop_dmc_in_rw_ack_intr___full___width 1 | ||
| 228 | #define reg_iop_dmc_in_rw_ack_intr___full___bit 5 | ||
| 229 | #define reg_iop_dmc_in_rw_ack_intr_offset 92 | ||
| 230 | |||
| 231 | /* Register r_intr, scope iop_dmc_in, type r */ | ||
| 232 | #define reg_iop_dmc_in_r_intr___data_md___lsb 0 | ||
| 233 | #define reg_iop_dmc_in_r_intr___data_md___width 1 | ||
| 234 | #define reg_iop_dmc_in_r_intr___data_md___bit 0 | ||
| 235 | #define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1 | ||
| 236 | #define reg_iop_dmc_in_r_intr___ctxt_md___width 1 | ||
| 237 | #define reg_iop_dmc_in_r_intr___ctxt_md___bit 1 | ||
| 238 | #define reg_iop_dmc_in_r_intr___group_md___lsb 2 | ||
| 239 | #define reg_iop_dmc_in_r_intr___group_md___width 1 | ||
| 240 | #define reg_iop_dmc_in_r_intr___group_md___bit 2 | ||
| 241 | #define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3 | ||
| 242 | #define reg_iop_dmc_in_r_intr___cmd_rdy___width 1 | ||
| 243 | #define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3 | ||
| 244 | #define reg_iop_dmc_in_r_intr___sth___lsb 4 | ||
| 245 | #define reg_iop_dmc_in_r_intr___sth___width 1 | ||
| 246 | #define reg_iop_dmc_in_r_intr___sth___bit 4 | ||
| 247 | #define reg_iop_dmc_in_r_intr___full___lsb 5 | ||
| 248 | #define reg_iop_dmc_in_r_intr___full___width 1 | ||
| 249 | #define reg_iop_dmc_in_r_intr___full___bit 5 | ||
| 250 | #define reg_iop_dmc_in_r_intr_offset 96 | ||
| 251 | |||
| 252 | /* Register r_masked_intr, scope iop_dmc_in, type r */ | ||
| 253 | #define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0 | ||
| 254 | #define reg_iop_dmc_in_r_masked_intr___data_md___width 1 | ||
| 255 | #define reg_iop_dmc_in_r_masked_intr___data_md___bit 0 | ||
| 256 | #define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1 | ||
| 257 | #define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1 | ||
| 258 | #define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1 | ||
| 259 | #define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2 | ||
| 260 | #define reg_iop_dmc_in_r_masked_intr___group_md___width 1 | ||
| 261 | #define reg_iop_dmc_in_r_masked_intr___group_md___bit 2 | ||
| 262 | #define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3 | ||
| 263 | #define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1 | ||
| 264 | #define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3 | ||
| 265 | #define reg_iop_dmc_in_r_masked_intr___sth___lsb 4 | ||
| 266 | #define reg_iop_dmc_in_r_masked_intr___sth___width 1 | ||
| 267 | #define reg_iop_dmc_in_r_masked_intr___sth___bit 4 | ||
| 268 | #define reg_iop_dmc_in_r_masked_intr___full___lsb 5 | ||
| 269 | #define reg_iop_dmc_in_r_masked_intr___full___width 1 | ||
| 270 | #define reg_iop_dmc_in_r_masked_intr___full___bit 5 | ||
| 271 | #define reg_iop_dmc_in_r_masked_intr_offset 100 | ||
| 272 | |||
| 273 | |||
| 274 | /* Constants */ | ||
| 275 | #define regk_iop_dmc_in_ack_pkt 0x00000100 | ||
| 276 | #define regk_iop_dmc_in_array 0x00000008 | ||
| 277 | #define regk_iop_dmc_in_burst 0x00000020 | ||
| 278 | #define regk_iop_dmc_in_copy_next 0x00000010 | ||
| 279 | #define regk_iop_dmc_in_copy_up 0x00000020 | ||
| 280 | #define regk_iop_dmc_in_dis_c 0x00000010 | ||
| 281 | #define regk_iop_dmc_in_dis_g 0x00000020 | ||
| 282 | #define regk_iop_dmc_in_lim1 0x00000000 | ||
| 283 | #define regk_iop_dmc_in_lim16 0x00000004 | ||
| 284 | #define regk_iop_dmc_in_lim2 0x00000001 | ||
| 285 | #define regk_iop_dmc_in_lim32 0x00000005 | ||
| 286 | #define regk_iop_dmc_in_lim4 0x00000002 | ||
| 287 | #define regk_iop_dmc_in_lim64 0x00000006 | ||
| 288 | #define regk_iop_dmc_in_lim8 0x00000003 | ||
| 289 | #define regk_iop_dmc_in_load_c 0x00000200 | ||
| 290 | #define regk_iop_dmc_in_load_c_n 0x00000280 | ||
| 291 | #define regk_iop_dmc_in_load_c_next 0x00000240 | ||
| 292 | #define regk_iop_dmc_in_load_d 0x00000140 | ||
| 293 | #define regk_iop_dmc_in_load_g 0x00000300 | ||
| 294 | #define regk_iop_dmc_in_load_g_down 0x000003c0 | ||
| 295 | #define regk_iop_dmc_in_load_g_next 0x00000340 | ||
| 296 | #define regk_iop_dmc_in_load_g_up 0x00000380 | ||
| 297 | #define regk_iop_dmc_in_next_en 0x00000010 | ||
| 298 | #define regk_iop_dmc_in_next_pkt 0x00000010 | ||
| 299 | #define regk_iop_dmc_in_no 0x00000000 | ||
| 300 | #define regk_iop_dmc_in_restore 0x00000020 | ||
| 301 | #define regk_iop_dmc_in_rw_cfg_default 0x00000000 | ||
| 302 | #define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000 | ||
| 303 | #define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000 | ||
| 304 | #define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000 | ||
| 305 | #define regk_iop_dmc_in_rw_data_descr_default 0x00000000 | ||
| 306 | #define regk_iop_dmc_in_rw_group_descr_default 0x00000000 | ||
| 307 | #define regk_iop_dmc_in_rw_intr_mask_default 0x00000000 | ||
| 308 | #define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000 | ||
| 309 | #define regk_iop_dmc_in_save_down 0x00000020 | ||
| 310 | #define regk_iop_dmc_in_save_up 0x00000020 | ||
| 311 | #define regk_iop_dmc_in_set_reg 0x00000050 | ||
| 312 | #define regk_iop_dmc_in_set_w_size1 0x00000190 | ||
| 313 | #define regk_iop_dmc_in_set_w_size2 0x000001a0 | ||
| 314 | #define regk_iop_dmc_in_set_w_size4 0x000001c0 | ||
| 315 | #define regk_iop_dmc_in_store_c 0x00000002 | ||
| 316 | #define regk_iop_dmc_in_store_descr 0x00000000 | ||
| 317 | #define regk_iop_dmc_in_store_g 0x00000004 | ||
| 318 | #define regk_iop_dmc_in_store_md 0x00000001 | ||
| 319 | #define regk_iop_dmc_in_update_down 0x00000020 | ||
| 320 | #define regk_iop_dmc_in_yes 0x00000001 | ||
| 321 | #endif /* __iop_dmc_in_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h deleted file mode 100644 index 9fe1a8054371..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h +++ /dev/null | |||
| @@ -1,349 +0,0 @@ | |||
| 1 | #ifndef __iop_dmc_out_defs_asm_h | ||
| 2 | #define __iop_dmc_out_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_dmc_out.r | ||
| 7 | * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r | ||
| 11 | * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope iop_dmc_out, type rw */ | ||
| 57 | #define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 | ||
| 58 | #define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 | ||
| 59 | #define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 | ||
| 60 | #define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 | ||
| 61 | #define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 | ||
| 62 | #define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 | ||
| 63 | #define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 | ||
| 64 | #define reg_iop_dmc_out_rw_cfg_offset 0 | ||
| 65 | |||
| 66 | /* Register rw_ctrl, scope iop_dmc_out, type rw */ | ||
| 67 | #define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 | ||
| 68 | #define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 | ||
| 69 | #define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 | ||
| 70 | #define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 | ||
| 71 | #define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 | ||
| 72 | #define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 | ||
| 73 | #define reg_iop_dmc_out_rw_ctrl_offset 4 | ||
| 74 | |||
| 75 | /* Register r_stat, scope iop_dmc_out, type r */ | ||
| 76 | #define reg_iop_dmc_out_r_stat___dif_en___lsb 0 | ||
| 77 | #define reg_iop_dmc_out_r_stat___dif_en___width 1 | ||
| 78 | #define reg_iop_dmc_out_r_stat___dif_en___bit 0 | ||
| 79 | #define reg_iop_dmc_out_r_stat_offset 8 | ||
| 80 | |||
| 81 | /* Register rw_stream_cmd, scope iop_dmc_out, type rw */ | ||
| 82 | #define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 | ||
| 83 | #define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 | ||
| 84 | #define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 | ||
| 85 | #define reg_iop_dmc_out_rw_stream_cmd___n___width 8 | ||
| 86 | #define reg_iop_dmc_out_rw_stream_cmd_offset 12 | ||
| 87 | |||
| 88 | /* Register rs_stream_data, scope iop_dmc_out, type rs */ | ||
| 89 | #define reg_iop_dmc_out_rs_stream_data_offset 16 | ||
| 90 | |||
| 91 | /* Register r_stream_data, scope iop_dmc_out, type r */ | ||
| 92 | #define reg_iop_dmc_out_r_stream_data_offset 20 | ||
| 93 | |||
| 94 | /* Register r_stream_stat, scope iop_dmc_out, type r */ | ||
| 95 | #define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 | ||
| 96 | #define reg_iop_dmc_out_r_stream_stat___dth___width 7 | ||
| 97 | #define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 | ||
| 98 | #define reg_iop_dmc_out_r_stream_stat___dv___width 1 | ||
| 99 | #define reg_iop_dmc_out_r_stream_stat___dv___bit 16 | ||
| 100 | #define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 | ||
| 101 | #define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 | ||
| 102 | #define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 | ||
| 103 | #define reg_iop_dmc_out_r_stream_stat___last___lsb 18 | ||
| 104 | #define reg_iop_dmc_out_r_stream_stat___last___width 1 | ||
| 105 | #define reg_iop_dmc_out_r_stream_stat___last___bit 18 | ||
| 106 | #define reg_iop_dmc_out_r_stream_stat___size___lsb 19 | ||
| 107 | #define reg_iop_dmc_out_r_stream_stat___size___width 3 | ||
| 108 | #define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 | ||
| 109 | #define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 | ||
| 110 | #define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 | ||
| 111 | #define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 | ||
| 112 | #define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 | ||
| 113 | #define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 | ||
| 114 | #define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 | ||
| 115 | #define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 | ||
| 116 | #define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 | ||
| 117 | #define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 | ||
| 118 | #define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 | ||
| 119 | #define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 | ||
| 120 | #define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 | ||
| 121 | #define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 | ||
| 122 | #define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 | ||
| 123 | #define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 | ||
| 124 | #define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 | ||
| 125 | #define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 | ||
| 126 | #define reg_iop_dmc_out_r_stream_stat_offset 24 | ||
| 127 | |||
| 128 | /* Register r_data_descr, scope iop_dmc_out, type r */ | ||
| 129 | #define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 | ||
| 130 | #define reg_iop_dmc_out_r_data_descr___ctrl___width 8 | ||
| 131 | #define reg_iop_dmc_out_r_data_descr___stat___lsb 8 | ||
| 132 | #define reg_iop_dmc_out_r_data_descr___stat___width 8 | ||
| 133 | #define reg_iop_dmc_out_r_data_descr___md___lsb 16 | ||
| 134 | #define reg_iop_dmc_out_r_data_descr___md___width 16 | ||
| 135 | #define reg_iop_dmc_out_r_data_descr_offset 28 | ||
| 136 | |||
| 137 | /* Register r_ctxt_descr, scope iop_dmc_out, type r */ | ||
| 138 | #define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 | ||
| 139 | #define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 | ||
| 140 | #define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 | ||
| 141 | #define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 | ||
| 142 | #define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 | ||
| 143 | #define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 | ||
| 144 | #define reg_iop_dmc_out_r_ctxt_descr_offset 32 | ||
| 145 | |||
| 146 | /* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ | ||
| 147 | #define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 | ||
| 148 | |||
| 149 | /* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ | ||
| 150 | #define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 | ||
| 151 | |||
| 152 | /* Register r_group_descr, scope iop_dmc_out, type r */ | ||
| 153 | #define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 | ||
| 154 | #define reg_iop_dmc_out_r_group_descr___ctrl___width 8 | ||
| 155 | #define reg_iop_dmc_out_r_group_descr___stat___lsb 8 | ||
| 156 | #define reg_iop_dmc_out_r_group_descr___stat___width 8 | ||
| 157 | #define reg_iop_dmc_out_r_group_descr___md___lsb 16 | ||
| 158 | #define reg_iop_dmc_out_r_group_descr___md___width 16 | ||
| 159 | #define reg_iop_dmc_out_r_group_descr_offset 52 | ||
| 160 | |||
| 161 | /* Register rw_data_descr, scope iop_dmc_out, type rw */ | ||
| 162 | #define reg_iop_dmc_out_rw_data_descr___md___lsb 16 | ||
| 163 | #define reg_iop_dmc_out_rw_data_descr___md___width 16 | ||
| 164 | #define reg_iop_dmc_out_rw_data_descr_offset 56 | ||
| 165 | |||
| 166 | /* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ | ||
| 167 | #define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 | ||
| 168 | #define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 | ||
| 169 | #define reg_iop_dmc_out_rw_ctxt_descr_offset 60 | ||
| 170 | |||
| 171 | /* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ | ||
| 172 | #define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 | ||
| 173 | |||
| 174 | /* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ | ||
| 175 | #define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 | ||
| 176 | |||
| 177 | /* Register rw_group_descr, scope iop_dmc_out, type rw */ | ||
| 178 | #define reg_iop_dmc_out_rw_group_descr___md___lsb 16 | ||
| 179 | #define reg_iop_dmc_out_rw_group_descr___md___width 16 | ||
| 180 | #define reg_iop_dmc_out_rw_group_descr_offset 80 | ||
| 181 | |||
| 182 | /* Register rw_intr_mask, scope iop_dmc_out, type rw */ | ||
| 183 | #define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 | ||
| 184 | #define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 | ||
| 185 | #define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 | ||
| 186 | #define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 | ||
| 187 | #define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 | ||
| 188 | #define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 | ||
| 189 | #define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 | ||
| 190 | #define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 | ||
| 191 | #define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 | ||
| 192 | #define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 | ||
| 193 | #define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 | ||
| 194 | #define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 | ||
| 195 | #define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 | ||
| 196 | #define reg_iop_dmc_out_rw_intr_mask___dth___width 1 | ||
| 197 | #define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 | ||
| 198 | #define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 | ||
| 199 | #define reg_iop_dmc_out_rw_intr_mask___dv___width 1 | ||
| 200 | #define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 | ||
| 201 | #define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 | ||
| 202 | #define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 | ||
| 203 | #define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 | ||
| 204 | #define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 | ||
| 205 | #define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 | ||
| 206 | #define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 | ||
| 207 | #define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 | ||
| 208 | #define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 | ||
| 209 | #define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 | ||
| 210 | #define reg_iop_dmc_out_rw_intr_mask_offset 84 | ||
| 211 | |||
| 212 | /* Register rw_ack_intr, scope iop_dmc_out, type rw */ | ||
| 213 | #define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 | ||
| 214 | #define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 | ||
| 215 | #define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 | ||
| 216 | #define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 | ||
| 217 | #define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 | ||
| 218 | #define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 | ||
| 219 | #define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 | ||
| 220 | #define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 | ||
| 221 | #define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 | ||
| 222 | #define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 | ||
| 223 | #define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 | ||
| 224 | #define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 | ||
| 225 | #define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 | ||
| 226 | #define reg_iop_dmc_out_rw_ack_intr___dth___width 1 | ||
| 227 | #define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 | ||
| 228 | #define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 | ||
| 229 | #define reg_iop_dmc_out_rw_ack_intr___dv___width 1 | ||
| 230 | #define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 | ||
| 231 | #define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 | ||
| 232 | #define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 | ||
| 233 | #define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 | ||
| 234 | #define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 | ||
| 235 | #define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 | ||
| 236 | #define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 | ||
| 237 | #define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 | ||
| 238 | #define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 | ||
| 239 | #define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 | ||
| 240 | #define reg_iop_dmc_out_rw_ack_intr_offset 88 | ||
| 241 | |||
| 242 | /* Register r_intr, scope iop_dmc_out, type r */ | ||
| 243 | #define reg_iop_dmc_out_r_intr___data_md___lsb 0 | ||
| 244 | #define reg_iop_dmc_out_r_intr___data_md___width 1 | ||
| 245 | #define reg_iop_dmc_out_r_intr___data_md___bit 0 | ||
| 246 | #define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 | ||
| 247 | #define reg_iop_dmc_out_r_intr___ctxt_md___width 1 | ||
| 248 | #define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 | ||
| 249 | #define reg_iop_dmc_out_r_intr___group_md___lsb 2 | ||
| 250 | #define reg_iop_dmc_out_r_intr___group_md___width 1 | ||
| 251 | #define reg_iop_dmc_out_r_intr___group_md___bit 2 | ||
| 252 | #define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 | ||
| 253 | #define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 | ||
| 254 | #define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 | ||
| 255 | #define reg_iop_dmc_out_r_intr___dth___lsb 4 | ||
| 256 | #define reg_iop_dmc_out_r_intr___dth___width 1 | ||
| 257 | #define reg_iop_dmc_out_r_intr___dth___bit 4 | ||
| 258 | #define reg_iop_dmc_out_r_intr___dv___lsb 5 | ||
| 259 | #define reg_iop_dmc_out_r_intr___dv___width 1 | ||
| 260 | #define reg_iop_dmc_out_r_intr___dv___bit 5 | ||
| 261 | #define reg_iop_dmc_out_r_intr___last_data___lsb 6 | ||
| 262 | #define reg_iop_dmc_out_r_intr___last_data___width 1 | ||
| 263 | #define reg_iop_dmc_out_r_intr___last_data___bit 6 | ||
| 264 | #define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 | ||
| 265 | #define reg_iop_dmc_out_r_intr___trf_lim___width 1 | ||
| 266 | #define reg_iop_dmc_out_r_intr___trf_lim___bit 7 | ||
| 267 | #define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 | ||
| 268 | #define reg_iop_dmc_out_r_intr___cmd_rq___width 1 | ||
| 269 | #define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 | ||
| 270 | #define reg_iop_dmc_out_r_intr_offset 92 | ||
| 271 | |||
| 272 | /* Register r_masked_intr, scope iop_dmc_out, type r */ | ||
| 273 | #define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 | ||
| 274 | #define reg_iop_dmc_out_r_masked_intr___data_md___width 1 | ||
| 275 | #define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 | ||
| 276 | #define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 | ||
| 277 | #define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 | ||
| 278 | #define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 | ||
| 279 | #define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 | ||
| 280 | #define reg_iop_dmc_out_r_masked_intr___group_md___width 1 | ||
| 281 | #define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 | ||
| 282 | #define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 | ||
| 283 | #define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 | ||
| 284 | #define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 | ||
| 285 | #define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 | ||
| 286 | #define reg_iop_dmc_out_r_masked_intr___dth___width 1 | ||
| 287 | #define reg_iop_dmc_out_r_masked_intr___dth___bit 4 | ||
| 288 | #define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 | ||
| 289 | #define reg_iop_dmc_out_r_masked_intr___dv___width 1 | ||
| 290 | #define reg_iop_dmc_out_r_masked_intr___dv___bit 5 | ||
| 291 | #define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 | ||
| 292 | #define reg_iop_dmc_out_r_masked_intr___last_data___width 1 | ||
| 293 | #define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 | ||
| 294 | #define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 | ||
| 295 | #define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 | ||
| 296 | #define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 | ||
| 297 | #define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 | ||
| 298 | #define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 | ||
| 299 | #define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 | ||
| 300 | #define reg_iop_dmc_out_r_masked_intr_offset 96 | ||
| 301 | |||
| 302 | |||
| 303 | /* Constants */ | ||
| 304 | #define regk_iop_dmc_out_ack_pkt 0x00000100 | ||
| 305 | #define regk_iop_dmc_out_array 0x00000008 | ||
| 306 | #define regk_iop_dmc_out_burst 0x00000020 | ||
| 307 | #define regk_iop_dmc_out_copy_next 0x00000010 | ||
| 308 | #define regk_iop_dmc_out_copy_up 0x00000020 | ||
| 309 | #define regk_iop_dmc_out_dis_c 0x00000010 | ||
| 310 | #define regk_iop_dmc_out_dis_g 0x00000020 | ||
| 311 | #define regk_iop_dmc_out_lim1 0x00000000 | ||
| 312 | #define regk_iop_dmc_out_lim16 0x00000004 | ||
| 313 | #define regk_iop_dmc_out_lim2 0x00000001 | ||
| 314 | #define regk_iop_dmc_out_lim32 0x00000005 | ||
| 315 | #define regk_iop_dmc_out_lim4 0x00000002 | ||
| 316 | #define regk_iop_dmc_out_lim64 0x00000006 | ||
| 317 | #define regk_iop_dmc_out_lim8 0x00000003 | ||
| 318 | #define regk_iop_dmc_out_load_c 0x00000200 | ||
| 319 | #define regk_iop_dmc_out_load_c_n 0x00000280 | ||
| 320 | #define regk_iop_dmc_out_load_c_next 0x00000240 | ||
| 321 | #define regk_iop_dmc_out_load_d 0x00000140 | ||
| 322 | #define regk_iop_dmc_out_load_g 0x00000300 | ||
| 323 | #define regk_iop_dmc_out_load_g_down 0x000003c0 | ||
| 324 | #define regk_iop_dmc_out_load_g_next 0x00000340 | ||
| 325 | #define regk_iop_dmc_out_load_g_up 0x00000380 | ||
| 326 | #define regk_iop_dmc_out_next_en 0x00000010 | ||
| 327 | #define regk_iop_dmc_out_next_pkt 0x00000010 | ||
| 328 | #define regk_iop_dmc_out_no 0x00000000 | ||
| 329 | #define regk_iop_dmc_out_restore 0x00000020 | ||
| 330 | #define regk_iop_dmc_out_rw_cfg_default 0x00000000 | ||
| 331 | #define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 | ||
| 332 | #define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 | ||
| 333 | #define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 | ||
| 334 | #define regk_iop_dmc_out_rw_data_descr_default 0x00000000 | ||
| 335 | #define regk_iop_dmc_out_rw_group_descr_default 0x00000000 | ||
| 336 | #define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 | ||
| 337 | #define regk_iop_dmc_out_save_down 0x00000020 | ||
| 338 | #define regk_iop_dmc_out_save_up 0x00000020 | ||
| 339 | #define regk_iop_dmc_out_set_reg 0x00000050 | ||
| 340 | #define regk_iop_dmc_out_set_w_size1 0x00000190 | ||
| 341 | #define regk_iop_dmc_out_set_w_size2 0x000001a0 | ||
| 342 | #define regk_iop_dmc_out_set_w_size4 0x000001c0 | ||
| 343 | #define regk_iop_dmc_out_store_c 0x00000002 | ||
| 344 | #define regk_iop_dmc_out_store_descr 0x00000000 | ||
| 345 | #define regk_iop_dmc_out_store_g 0x00000004 | ||
| 346 | #define regk_iop_dmc_out_store_md 0x00000001 | ||
| 347 | #define regk_iop_dmc_out_update_down 0x00000020 | ||
| 348 | #define regk_iop_dmc_out_yes 0x00000001 | ||
| 349 | #endif /* __iop_dmc_out_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h deleted file mode 100644 index 974dee082f9f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h +++ /dev/null | |||
| @@ -1,234 +0,0 @@ | |||
| 1 | #ifndef __iop_fifo_in_defs_asm_h | ||
| 2 | #define __iop_fifo_in_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_fifo_in.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:07 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r | ||
| 11 | * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope iop_fifo_in, type rw */ | ||
| 57 | #define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0 | ||
| 58 | #define reg_iop_fifo_in_rw_cfg___avail_lim___width 3 | ||
| 59 | #define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3 | ||
| 60 | #define reg_iop_fifo_in_rw_cfg___byte_order___width 2 | ||
| 61 | #define reg_iop_fifo_in_rw_cfg___trig___lsb 5 | ||
| 62 | #define reg_iop_fifo_in_rw_cfg___trig___width 2 | ||
| 63 | #define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7 | ||
| 64 | #define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1 | ||
| 65 | #define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7 | ||
| 66 | #define reg_iop_fifo_in_rw_cfg___mode___lsb 8 | ||
| 67 | #define reg_iop_fifo_in_rw_cfg___mode___width 2 | ||
| 68 | #define reg_iop_fifo_in_rw_cfg_offset 0 | ||
| 69 | |||
| 70 | /* Register rw_ctrl, scope iop_fifo_in, type rw */ | ||
| 71 | #define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0 | ||
| 72 | #define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1 | ||
| 73 | #define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0 | ||
| 74 | #define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1 | ||
| 75 | #define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1 | ||
| 76 | #define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1 | ||
| 77 | #define reg_iop_fifo_in_rw_ctrl_offset 4 | ||
| 78 | |||
| 79 | /* Register r_stat, scope iop_fifo_in, type r */ | ||
| 80 | #define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0 | ||
| 81 | #define reg_iop_fifo_in_r_stat___avail_bytes___width 4 | ||
| 82 | #define reg_iop_fifo_in_r_stat___last___lsb 4 | ||
| 83 | #define reg_iop_fifo_in_r_stat___last___width 8 | ||
| 84 | #define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12 | ||
| 85 | #define reg_iop_fifo_in_r_stat___dif_in_en___width 1 | ||
| 86 | #define reg_iop_fifo_in_r_stat___dif_in_en___bit 12 | ||
| 87 | #define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13 | ||
| 88 | #define reg_iop_fifo_in_r_stat___dif_out_en___width 1 | ||
| 89 | #define reg_iop_fifo_in_r_stat___dif_out_en___bit 13 | ||
| 90 | #define reg_iop_fifo_in_r_stat_offset 8 | ||
| 91 | |||
| 92 | /* Register rs_rd1byte, scope iop_fifo_in, type rs */ | ||
| 93 | #define reg_iop_fifo_in_rs_rd1byte___data___lsb 0 | ||
| 94 | #define reg_iop_fifo_in_rs_rd1byte___data___width 8 | ||
| 95 | #define reg_iop_fifo_in_rs_rd1byte_offset 12 | ||
| 96 | |||
| 97 | /* Register r_rd1byte, scope iop_fifo_in, type r */ | ||
| 98 | #define reg_iop_fifo_in_r_rd1byte___data___lsb 0 | ||
| 99 | #define reg_iop_fifo_in_r_rd1byte___data___width 8 | ||
| 100 | #define reg_iop_fifo_in_r_rd1byte_offset 16 | ||
| 101 | |||
| 102 | /* Register rs_rd2byte, scope iop_fifo_in, type rs */ | ||
| 103 | #define reg_iop_fifo_in_rs_rd2byte___data___lsb 0 | ||
| 104 | #define reg_iop_fifo_in_rs_rd2byte___data___width 16 | ||
| 105 | #define reg_iop_fifo_in_rs_rd2byte_offset 20 | ||
| 106 | |||
| 107 | /* Register r_rd2byte, scope iop_fifo_in, type r */ | ||
| 108 | #define reg_iop_fifo_in_r_rd2byte___data___lsb 0 | ||
| 109 | #define reg_iop_fifo_in_r_rd2byte___data___width 16 | ||
| 110 | #define reg_iop_fifo_in_r_rd2byte_offset 24 | ||
| 111 | |||
| 112 | /* Register rs_rd3byte, scope iop_fifo_in, type rs */ | ||
| 113 | #define reg_iop_fifo_in_rs_rd3byte___data___lsb 0 | ||
| 114 | #define reg_iop_fifo_in_rs_rd3byte___data___width 24 | ||
| 115 | #define reg_iop_fifo_in_rs_rd3byte_offset 28 | ||
| 116 | |||
| 117 | /* Register r_rd3byte, scope iop_fifo_in, type r */ | ||
| 118 | #define reg_iop_fifo_in_r_rd3byte___data___lsb 0 | ||
| 119 | #define reg_iop_fifo_in_r_rd3byte___data___width 24 | ||
| 120 | #define reg_iop_fifo_in_r_rd3byte_offset 32 | ||
| 121 | |||
| 122 | /* Register rs_rd4byte, scope iop_fifo_in, type rs */ | ||
| 123 | #define reg_iop_fifo_in_rs_rd4byte___data___lsb 0 | ||
| 124 | #define reg_iop_fifo_in_rs_rd4byte___data___width 32 | ||
| 125 | #define reg_iop_fifo_in_rs_rd4byte_offset 36 | ||
| 126 | |||
| 127 | /* Register r_rd4byte, scope iop_fifo_in, type r */ | ||
| 128 | #define reg_iop_fifo_in_r_rd4byte___data___lsb 0 | ||
| 129 | #define reg_iop_fifo_in_r_rd4byte___data___width 32 | ||
| 130 | #define reg_iop_fifo_in_r_rd4byte_offset 40 | ||
| 131 | |||
| 132 | /* Register rw_set_last, scope iop_fifo_in, type rw */ | ||
| 133 | #define reg_iop_fifo_in_rw_set_last_offset 44 | ||
| 134 | |||
| 135 | /* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ | ||
| 136 | #define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0 | ||
| 137 | #define reg_iop_fifo_in_rw_strb_dif_in___last___width 2 | ||
| 138 | #define reg_iop_fifo_in_rw_strb_dif_in_offset 48 | ||
| 139 | |||
| 140 | /* Register rw_intr_mask, scope iop_fifo_in, type rw */ | ||
| 141 | #define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0 | ||
| 142 | #define reg_iop_fifo_in_rw_intr_mask___urun___width 1 | ||
| 143 | #define reg_iop_fifo_in_rw_intr_mask___urun___bit 0 | ||
| 144 | #define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1 | ||
| 145 | #define reg_iop_fifo_in_rw_intr_mask___last_data___width 1 | ||
| 146 | #define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1 | ||
| 147 | #define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2 | ||
| 148 | #define reg_iop_fifo_in_rw_intr_mask___dav___width 1 | ||
| 149 | #define reg_iop_fifo_in_rw_intr_mask___dav___bit 2 | ||
| 150 | #define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3 | ||
| 151 | #define reg_iop_fifo_in_rw_intr_mask___avail___width 1 | ||
| 152 | #define reg_iop_fifo_in_rw_intr_mask___avail___bit 3 | ||
| 153 | #define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4 | ||
| 154 | #define reg_iop_fifo_in_rw_intr_mask___orun___width 1 | ||
| 155 | #define reg_iop_fifo_in_rw_intr_mask___orun___bit 4 | ||
| 156 | #define reg_iop_fifo_in_rw_intr_mask_offset 52 | ||
| 157 | |||
| 158 | /* Register rw_ack_intr, scope iop_fifo_in, type rw */ | ||
| 159 | #define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0 | ||
| 160 | #define reg_iop_fifo_in_rw_ack_intr___urun___width 1 | ||
| 161 | #define reg_iop_fifo_in_rw_ack_intr___urun___bit 0 | ||
| 162 | #define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1 | ||
| 163 | #define reg_iop_fifo_in_rw_ack_intr___last_data___width 1 | ||
| 164 | #define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1 | ||
| 165 | #define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2 | ||
| 166 | #define reg_iop_fifo_in_rw_ack_intr___dav___width 1 | ||
| 167 | #define reg_iop_fifo_in_rw_ack_intr___dav___bit 2 | ||
| 168 | #define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3 | ||
| 169 | #define reg_iop_fifo_in_rw_ack_intr___avail___width 1 | ||
| 170 | #define reg_iop_fifo_in_rw_ack_intr___avail___bit 3 | ||
| 171 | #define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4 | ||
| 172 | #define reg_iop_fifo_in_rw_ack_intr___orun___width 1 | ||
| 173 | #define reg_iop_fifo_in_rw_ack_intr___orun___bit 4 | ||
| 174 | #define reg_iop_fifo_in_rw_ack_intr_offset 56 | ||
| 175 | |||
| 176 | /* Register r_intr, scope iop_fifo_in, type r */ | ||
| 177 | #define reg_iop_fifo_in_r_intr___urun___lsb 0 | ||
| 178 | #define reg_iop_fifo_in_r_intr___urun___width 1 | ||
| 179 | #define reg_iop_fifo_in_r_intr___urun___bit 0 | ||
| 180 | #define reg_iop_fifo_in_r_intr___last_data___lsb 1 | ||
| 181 | #define reg_iop_fifo_in_r_intr___last_data___width 1 | ||
| 182 | #define reg_iop_fifo_in_r_intr___last_data___bit 1 | ||
| 183 | #define reg_iop_fifo_in_r_intr___dav___lsb 2 | ||
| 184 | #define reg_iop_fifo_in_r_intr___dav___width 1 | ||
| 185 | #define reg_iop_fifo_in_r_intr___dav___bit 2 | ||
| 186 | #define reg_iop_fifo_in_r_intr___avail___lsb 3 | ||
| 187 | #define reg_iop_fifo_in_r_intr___avail___width 1 | ||
| 188 | #define reg_iop_fifo_in_r_intr___avail___bit 3 | ||
| 189 | #define reg_iop_fifo_in_r_intr___orun___lsb 4 | ||
| 190 | #define reg_iop_fifo_in_r_intr___orun___width 1 | ||
| 191 | #define reg_iop_fifo_in_r_intr___orun___bit 4 | ||
| 192 | #define reg_iop_fifo_in_r_intr_offset 60 | ||
| 193 | |||
| 194 | /* Register r_masked_intr, scope iop_fifo_in, type r */ | ||
| 195 | #define reg_iop_fifo_in_r_masked_intr___urun___lsb 0 | ||
| 196 | #define reg_iop_fifo_in_r_masked_intr___urun___width 1 | ||
| 197 | #define reg_iop_fifo_in_r_masked_intr___urun___bit 0 | ||
| 198 | #define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1 | ||
| 199 | #define reg_iop_fifo_in_r_masked_intr___last_data___width 1 | ||
| 200 | #define reg_iop_fifo_in_r_masked_intr___last_data___bit 1 | ||
| 201 | #define reg_iop_fifo_in_r_masked_intr___dav___lsb 2 | ||
| 202 | #define reg_iop_fifo_in_r_masked_intr___dav___width 1 | ||
| 203 | #define reg_iop_fifo_in_r_masked_intr___dav___bit 2 | ||
| 204 | #define reg_iop_fifo_in_r_masked_intr___avail___lsb 3 | ||
| 205 | #define reg_iop_fifo_in_r_masked_intr___avail___width 1 | ||
| 206 | #define reg_iop_fifo_in_r_masked_intr___avail___bit 3 | ||
| 207 | #define reg_iop_fifo_in_r_masked_intr___orun___lsb 4 | ||
| 208 | #define reg_iop_fifo_in_r_masked_intr___orun___width 1 | ||
| 209 | #define reg_iop_fifo_in_r_masked_intr___orun___bit 4 | ||
| 210 | #define reg_iop_fifo_in_r_masked_intr_offset 64 | ||
| 211 | |||
| 212 | |||
| 213 | /* Constants */ | ||
| 214 | #define regk_iop_fifo_in_dif_in 0x00000002 | ||
| 215 | #define regk_iop_fifo_in_hi 0x00000000 | ||
| 216 | #define regk_iop_fifo_in_neg 0x00000002 | ||
| 217 | #define regk_iop_fifo_in_no 0x00000000 | ||
| 218 | #define regk_iop_fifo_in_order16 0x00000001 | ||
| 219 | #define regk_iop_fifo_in_order24 0x00000002 | ||
| 220 | #define regk_iop_fifo_in_order32 0x00000003 | ||
| 221 | #define regk_iop_fifo_in_order8 0x00000000 | ||
| 222 | #define regk_iop_fifo_in_pos 0x00000001 | ||
| 223 | #define regk_iop_fifo_in_pos_neg 0x00000003 | ||
| 224 | #define regk_iop_fifo_in_rw_cfg_default 0x00000024 | ||
| 225 | #define regk_iop_fifo_in_rw_ctrl_default 0x00000000 | ||
| 226 | #define regk_iop_fifo_in_rw_intr_mask_default 0x00000000 | ||
| 227 | #define regk_iop_fifo_in_rw_set_last_default 0x00000000 | ||
| 228 | #define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000 | ||
| 229 | #define regk_iop_fifo_in_size16 0x00000002 | ||
| 230 | #define regk_iop_fifo_in_size24 0x00000001 | ||
| 231 | #define regk_iop_fifo_in_size32 0x00000000 | ||
| 232 | #define regk_iop_fifo_in_size8 0x00000003 | ||
| 233 | #define regk_iop_fifo_in_yes 0x00000001 | ||
| 234 | #endif /* __iop_fifo_in_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h deleted file mode 100644 index e00fab0c9335..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h +++ /dev/null | |||
| @@ -1,155 +0,0 @@ | |||
| 1 | #ifndef __iop_fifo_in_extra_defs_asm_h | ||
| 2 | #define __iop_fifo_in_extra_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:08 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r | ||
| 11 | * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ | ||
| 57 | #define reg_iop_fifo_in_extra_rw_wr_data_offset 0 | ||
| 58 | |||
| 59 | /* Register r_stat, scope iop_fifo_in_extra, type r */ | ||
| 60 | #define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0 | ||
| 61 | #define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4 | ||
| 62 | #define reg_iop_fifo_in_extra_r_stat___last___lsb 4 | ||
| 63 | #define reg_iop_fifo_in_extra_r_stat___last___width 8 | ||
| 64 | #define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12 | ||
| 65 | #define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1 | ||
| 66 | #define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12 | ||
| 67 | #define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13 | ||
| 68 | #define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1 | ||
| 69 | #define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13 | ||
| 70 | #define reg_iop_fifo_in_extra_r_stat_offset 4 | ||
| 71 | |||
| 72 | /* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ | ||
| 73 | #define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0 | ||
| 74 | #define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2 | ||
| 75 | #define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8 | ||
| 76 | |||
| 77 | /* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ | ||
| 78 | #define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0 | ||
| 79 | #define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1 | ||
| 80 | #define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0 | ||
| 81 | #define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1 | ||
| 82 | #define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1 | ||
| 83 | #define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1 | ||
| 84 | #define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2 | ||
| 85 | #define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1 | ||
| 86 | #define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2 | ||
| 87 | #define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3 | ||
| 88 | #define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1 | ||
| 89 | #define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3 | ||
| 90 | #define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4 | ||
| 91 | #define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1 | ||
| 92 | #define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4 | ||
| 93 | #define reg_iop_fifo_in_extra_rw_intr_mask_offset 12 | ||
| 94 | |||
| 95 | /* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ | ||
| 96 | #define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0 | ||
| 97 | #define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1 | ||
| 98 | #define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0 | ||
| 99 | #define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1 | ||
| 100 | #define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1 | ||
| 101 | #define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1 | ||
| 102 | #define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2 | ||
| 103 | #define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1 | ||
| 104 | #define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2 | ||
| 105 | #define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3 | ||
| 106 | #define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1 | ||
| 107 | #define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3 | ||
| 108 | #define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4 | ||
| 109 | #define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1 | ||
| 110 | #define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4 | ||
| 111 | #define reg_iop_fifo_in_extra_rw_ack_intr_offset 16 | ||
| 112 | |||
| 113 | /* Register r_intr, scope iop_fifo_in_extra, type r */ | ||
| 114 | #define reg_iop_fifo_in_extra_r_intr___urun___lsb 0 | ||
| 115 | #define reg_iop_fifo_in_extra_r_intr___urun___width 1 | ||
| 116 | #define reg_iop_fifo_in_extra_r_intr___urun___bit 0 | ||
| 117 | #define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1 | ||
| 118 | #define reg_iop_fifo_in_extra_r_intr___last_data___width 1 | ||
| 119 | #define reg_iop_fifo_in_extra_r_intr___last_data___bit 1 | ||
| 120 | #define reg_iop_fifo_in_extra_r_intr___dav___lsb 2 | ||
| 121 | #define reg_iop_fifo_in_extra_r_intr___dav___width 1 | ||
| 122 | #define reg_iop_fifo_in_extra_r_intr___dav___bit 2 | ||
| 123 | #define reg_iop_fifo_in_extra_r_intr___avail___lsb 3 | ||
| 124 | #define reg_iop_fifo_in_extra_r_intr___avail___width 1 | ||
| 125 | #define reg_iop_fifo_in_extra_r_intr___avail___bit 3 | ||
| 126 | #define reg_iop_fifo_in_extra_r_intr___orun___lsb 4 | ||
| 127 | #define reg_iop_fifo_in_extra_r_intr___orun___width 1 | ||
| 128 | #define reg_iop_fifo_in_extra_r_intr___orun___bit 4 | ||
| 129 | #define reg_iop_fifo_in_extra_r_intr_offset 20 | ||
| 130 | |||
| 131 | /* Register r_masked_intr, scope iop_fifo_in_extra, type r */ | ||
| 132 | #define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0 | ||
| 133 | #define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1 | ||
| 134 | #define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0 | ||
| 135 | #define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1 | ||
| 136 | #define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1 | ||
| 137 | #define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1 | ||
| 138 | #define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2 | ||
| 139 | #define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1 | ||
| 140 | #define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2 | ||
| 141 | #define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3 | ||
| 142 | #define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1 | ||
| 143 | #define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3 | ||
| 144 | #define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4 | ||
| 145 | #define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1 | ||
| 146 | #define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4 | ||
| 147 | #define reg_iop_fifo_in_extra_r_masked_intr_offset 24 | ||
| 148 | |||
| 149 | |||
| 150 | /* Constants */ | ||
| 151 | #define regk_iop_fifo_in_extra_fifo_in 0x00000002 | ||
| 152 | #define regk_iop_fifo_in_extra_no 0x00000000 | ||
| 153 | #define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000 | ||
| 154 | #define regk_iop_fifo_in_extra_yes 0x00000001 | ||
| 155 | #endif /* __iop_fifo_in_extra_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h deleted file mode 100644 index 9ec5f4a826df..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h +++ /dev/null | |||
| @@ -1,254 +0,0 @@ | |||
| 1 | #ifndef __iop_fifo_out_defs_asm_h | ||
| 2 | #define __iop_fifo_out_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_fifo_out.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:09 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r | ||
| 11 | * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope iop_fifo_out, type rw */ | ||
| 57 | #define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 | ||
| 58 | #define reg_iop_fifo_out_rw_cfg___free_lim___width 3 | ||
| 59 | #define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 | ||
| 60 | #define reg_iop_fifo_out_rw_cfg___byte_order___width 2 | ||
| 61 | #define reg_iop_fifo_out_rw_cfg___trig___lsb 5 | ||
| 62 | #define reg_iop_fifo_out_rw_cfg___trig___width 2 | ||
| 63 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 | ||
| 64 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 | ||
| 65 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 | ||
| 66 | #define reg_iop_fifo_out_rw_cfg___mode___lsb 8 | ||
| 67 | #define reg_iop_fifo_out_rw_cfg___mode___width 2 | ||
| 68 | #define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 | ||
| 69 | #define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 | ||
| 70 | #define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 | ||
| 71 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 | ||
| 72 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 | ||
| 73 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 | ||
| 74 | #define reg_iop_fifo_out_rw_cfg_offset 0 | ||
| 75 | |||
| 76 | /* Register rw_ctrl, scope iop_fifo_out, type rw */ | ||
| 77 | #define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 | ||
| 78 | #define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 | ||
| 79 | #define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 | ||
| 80 | #define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 | ||
| 81 | #define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 | ||
| 82 | #define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 | ||
| 83 | #define reg_iop_fifo_out_rw_ctrl_offset 4 | ||
| 84 | |||
| 85 | /* Register r_stat, scope iop_fifo_out, type r */ | ||
| 86 | #define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 | ||
| 87 | #define reg_iop_fifo_out_r_stat___avail_bytes___width 4 | ||
| 88 | #define reg_iop_fifo_out_r_stat___last___lsb 4 | ||
| 89 | #define reg_iop_fifo_out_r_stat___last___width 8 | ||
| 90 | #define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 | ||
| 91 | #define reg_iop_fifo_out_r_stat___dif_in_en___width 1 | ||
| 92 | #define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 | ||
| 93 | #define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 | ||
| 94 | #define reg_iop_fifo_out_r_stat___dif_out_en___width 1 | ||
| 95 | #define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 | ||
| 96 | #define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 | ||
| 97 | #define reg_iop_fifo_out_r_stat___zero_data_last___width 1 | ||
| 98 | #define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 | ||
| 99 | #define reg_iop_fifo_out_r_stat_offset 8 | ||
| 100 | |||
| 101 | /* Register rw_wr1byte, scope iop_fifo_out, type rw */ | ||
| 102 | #define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 | ||
| 103 | #define reg_iop_fifo_out_rw_wr1byte___data___width 8 | ||
| 104 | #define reg_iop_fifo_out_rw_wr1byte_offset 12 | ||
| 105 | |||
| 106 | /* Register rw_wr2byte, scope iop_fifo_out, type rw */ | ||
| 107 | #define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 | ||
| 108 | #define reg_iop_fifo_out_rw_wr2byte___data___width 16 | ||
| 109 | #define reg_iop_fifo_out_rw_wr2byte_offset 16 | ||
| 110 | |||
| 111 | /* Register rw_wr3byte, scope iop_fifo_out, type rw */ | ||
| 112 | #define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 | ||
| 113 | #define reg_iop_fifo_out_rw_wr3byte___data___width 24 | ||
| 114 | #define reg_iop_fifo_out_rw_wr3byte_offset 20 | ||
| 115 | |||
| 116 | /* Register rw_wr4byte, scope iop_fifo_out, type rw */ | ||
| 117 | #define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 | ||
| 118 | #define reg_iop_fifo_out_rw_wr4byte___data___width 32 | ||
| 119 | #define reg_iop_fifo_out_rw_wr4byte_offset 24 | ||
| 120 | |||
| 121 | /* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ | ||
| 122 | #define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 | ||
| 123 | #define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 | ||
| 124 | #define reg_iop_fifo_out_rw_wr1byte_last_offset 28 | ||
| 125 | |||
| 126 | /* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ | ||
| 127 | #define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 | ||
| 128 | #define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 | ||
| 129 | #define reg_iop_fifo_out_rw_wr2byte_last_offset 32 | ||
| 130 | |||
| 131 | /* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ | ||
| 132 | #define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 | ||
| 133 | #define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 | ||
| 134 | #define reg_iop_fifo_out_rw_wr3byte_last_offset 36 | ||
| 135 | |||
| 136 | /* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ | ||
| 137 | #define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 | ||
| 138 | #define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 | ||
| 139 | #define reg_iop_fifo_out_rw_wr4byte_last_offset 40 | ||
| 140 | |||
| 141 | /* Register rw_set_last, scope iop_fifo_out, type rw */ | ||
| 142 | #define reg_iop_fifo_out_rw_set_last_offset 44 | ||
| 143 | |||
| 144 | /* Register rs_rd_data, scope iop_fifo_out, type rs */ | ||
| 145 | #define reg_iop_fifo_out_rs_rd_data_offset 48 | ||
| 146 | |||
| 147 | /* Register r_rd_data, scope iop_fifo_out, type r */ | ||
| 148 | #define reg_iop_fifo_out_r_rd_data_offset 52 | ||
| 149 | |||
| 150 | /* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ | ||
| 151 | #define reg_iop_fifo_out_rw_strb_dif_out_offset 56 | ||
| 152 | |||
| 153 | /* Register rw_intr_mask, scope iop_fifo_out, type rw */ | ||
| 154 | #define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 | ||
| 155 | #define reg_iop_fifo_out_rw_intr_mask___urun___width 1 | ||
| 156 | #define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 | ||
| 157 | #define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 | ||
| 158 | #define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 | ||
| 159 | #define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 | ||
| 160 | #define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 | ||
| 161 | #define reg_iop_fifo_out_rw_intr_mask___dav___width 1 | ||
| 162 | #define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 | ||
| 163 | #define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 | ||
| 164 | #define reg_iop_fifo_out_rw_intr_mask___free___width 1 | ||
| 165 | #define reg_iop_fifo_out_rw_intr_mask___free___bit 3 | ||
| 166 | #define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 | ||
| 167 | #define reg_iop_fifo_out_rw_intr_mask___orun___width 1 | ||
| 168 | #define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 | ||
| 169 | #define reg_iop_fifo_out_rw_intr_mask_offset 60 | ||
| 170 | |||
| 171 | /* Register rw_ack_intr, scope iop_fifo_out, type rw */ | ||
| 172 | #define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 | ||
| 173 | #define reg_iop_fifo_out_rw_ack_intr___urun___width 1 | ||
| 174 | #define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 | ||
| 175 | #define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 | ||
| 176 | #define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 | ||
| 177 | #define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 | ||
| 178 | #define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 | ||
| 179 | #define reg_iop_fifo_out_rw_ack_intr___dav___width 1 | ||
| 180 | #define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 | ||
| 181 | #define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 | ||
| 182 | #define reg_iop_fifo_out_rw_ack_intr___free___width 1 | ||
| 183 | #define reg_iop_fifo_out_rw_ack_intr___free___bit 3 | ||
| 184 | #define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 | ||
| 185 | #define reg_iop_fifo_out_rw_ack_intr___orun___width 1 | ||
| 186 | #define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 | ||
| 187 | #define reg_iop_fifo_out_rw_ack_intr_offset 64 | ||
| 188 | |||
| 189 | /* Register r_intr, scope iop_fifo_out, type r */ | ||
| 190 | #define reg_iop_fifo_out_r_intr___urun___lsb 0 | ||
| 191 | #define reg_iop_fifo_out_r_intr___urun___width 1 | ||
| 192 | #define reg_iop_fifo_out_r_intr___urun___bit 0 | ||
| 193 | #define reg_iop_fifo_out_r_intr___last_data___lsb 1 | ||
| 194 | #define reg_iop_fifo_out_r_intr___last_data___width 1 | ||
| 195 | #define reg_iop_fifo_out_r_intr___last_data___bit 1 | ||
| 196 | #define reg_iop_fifo_out_r_intr___dav___lsb 2 | ||
| 197 | #define reg_iop_fifo_out_r_intr___dav___width 1 | ||
| 198 | #define reg_iop_fifo_out_r_intr___dav___bit 2 | ||
| 199 | #define reg_iop_fifo_out_r_intr___free___lsb 3 | ||
| 200 | #define reg_iop_fifo_out_r_intr___free___width 1 | ||
| 201 | #define reg_iop_fifo_out_r_intr___free___bit 3 | ||
| 202 | #define reg_iop_fifo_out_r_intr___orun___lsb 4 | ||
| 203 | #define reg_iop_fifo_out_r_intr___orun___width 1 | ||
| 204 | #define reg_iop_fifo_out_r_intr___orun___bit 4 | ||
| 205 | #define reg_iop_fifo_out_r_intr_offset 68 | ||
| 206 | |||
| 207 | /* Register r_masked_intr, scope iop_fifo_out, type r */ | ||
| 208 | #define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 | ||
| 209 | #define reg_iop_fifo_out_r_masked_intr___urun___width 1 | ||
| 210 | #define reg_iop_fifo_out_r_masked_intr___urun___bit 0 | ||
| 211 | #define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 | ||
| 212 | #define reg_iop_fifo_out_r_masked_intr___last_data___width 1 | ||
| 213 | #define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 | ||
| 214 | #define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 | ||
| 215 | #define reg_iop_fifo_out_r_masked_intr___dav___width 1 | ||
| 216 | #define reg_iop_fifo_out_r_masked_intr___dav___bit 2 | ||
| 217 | #define reg_iop_fifo_out_r_masked_intr___free___lsb 3 | ||
| 218 | #define reg_iop_fifo_out_r_masked_intr___free___width 1 | ||
| 219 | #define reg_iop_fifo_out_r_masked_intr___free___bit 3 | ||
| 220 | #define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 | ||
| 221 | #define reg_iop_fifo_out_r_masked_intr___orun___width 1 | ||
| 222 | #define reg_iop_fifo_out_r_masked_intr___orun___bit 4 | ||
| 223 | #define reg_iop_fifo_out_r_masked_intr_offset 72 | ||
| 224 | |||
| 225 | |||
| 226 | /* Constants */ | ||
| 227 | #define regk_iop_fifo_out_hi 0x00000000 | ||
| 228 | #define regk_iop_fifo_out_neg 0x00000002 | ||
| 229 | #define regk_iop_fifo_out_no 0x00000000 | ||
| 230 | #define regk_iop_fifo_out_order16 0x00000001 | ||
| 231 | #define regk_iop_fifo_out_order24 0x00000002 | ||
| 232 | #define regk_iop_fifo_out_order32 0x00000003 | ||
| 233 | #define regk_iop_fifo_out_order8 0x00000000 | ||
| 234 | #define regk_iop_fifo_out_pos 0x00000001 | ||
| 235 | #define regk_iop_fifo_out_pos_neg 0x00000003 | ||
| 236 | #define regk_iop_fifo_out_rw_cfg_default 0x00000024 | ||
| 237 | #define regk_iop_fifo_out_rw_ctrl_default 0x00000000 | ||
| 238 | #define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 | ||
| 239 | #define regk_iop_fifo_out_rw_set_last_default 0x00000000 | ||
| 240 | #define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 | ||
| 241 | #define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 | ||
| 242 | #define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 | ||
| 243 | #define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 | ||
| 244 | #define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 | ||
| 245 | #define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 | ||
| 246 | #define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 | ||
| 247 | #define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 | ||
| 248 | #define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 | ||
| 249 | #define regk_iop_fifo_out_size16 0x00000002 | ||
| 250 | #define regk_iop_fifo_out_size24 0x00000001 | ||
| 251 | #define regk_iop_fifo_out_size32 0x00000000 | ||
| 252 | #define regk_iop_fifo_out_size8 0x00000003 | ||
| 253 | #define regk_iop_fifo_out_yes 0x00000001 | ||
| 254 | #endif /* __iop_fifo_out_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h deleted file mode 100644 index 0f84a50cf77c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h +++ /dev/null | |||
| @@ -1,158 +0,0 @@ | |||
| 1 | #ifndef __iop_fifo_out_extra_defs_asm_h | ||
| 2 | #define __iop_fifo_out_extra_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:10 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r | ||
| 11 | * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ | ||
| 57 | #define reg_iop_fifo_out_extra_rs_rd_data_offset 0 | ||
| 58 | |||
| 59 | /* Register r_rd_data, scope iop_fifo_out_extra, type r */ | ||
| 60 | #define reg_iop_fifo_out_extra_r_rd_data_offset 4 | ||
| 61 | |||
| 62 | /* Register r_stat, scope iop_fifo_out_extra, type r */ | ||
| 63 | #define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0 | ||
| 64 | #define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4 | ||
| 65 | #define reg_iop_fifo_out_extra_r_stat___last___lsb 4 | ||
| 66 | #define reg_iop_fifo_out_extra_r_stat___last___width 8 | ||
| 67 | #define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12 | ||
| 68 | #define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1 | ||
| 69 | #define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12 | ||
| 70 | #define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13 | ||
| 71 | #define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1 | ||
| 72 | #define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13 | ||
| 73 | #define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14 | ||
| 74 | #define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1 | ||
| 75 | #define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14 | ||
| 76 | #define reg_iop_fifo_out_extra_r_stat_offset 8 | ||
| 77 | |||
| 78 | /* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ | ||
| 79 | #define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12 | ||
| 80 | |||
| 81 | /* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ | ||
| 82 | #define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0 | ||
| 83 | #define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1 | ||
| 84 | #define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0 | ||
| 85 | #define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1 | ||
| 86 | #define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1 | ||
| 87 | #define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1 | ||
| 88 | #define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2 | ||
| 89 | #define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1 | ||
| 90 | #define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2 | ||
| 91 | #define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3 | ||
| 92 | #define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1 | ||
| 93 | #define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3 | ||
| 94 | #define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4 | ||
| 95 | #define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1 | ||
| 96 | #define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4 | ||
| 97 | #define reg_iop_fifo_out_extra_rw_intr_mask_offset 16 | ||
| 98 | |||
| 99 | /* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ | ||
| 100 | #define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0 | ||
| 101 | #define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1 | ||
| 102 | #define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0 | ||
| 103 | #define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1 | ||
| 104 | #define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1 | ||
| 105 | #define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1 | ||
| 106 | #define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2 | ||
| 107 | #define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1 | ||
| 108 | #define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2 | ||
| 109 | #define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3 | ||
| 110 | #define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1 | ||
| 111 | #define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3 | ||
| 112 | #define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4 | ||
| 113 | #define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1 | ||
| 114 | #define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4 | ||
| 115 | #define reg_iop_fifo_out_extra_rw_ack_intr_offset 20 | ||
| 116 | |||
| 117 | /* Register r_intr, scope iop_fifo_out_extra, type r */ | ||
| 118 | #define reg_iop_fifo_out_extra_r_intr___urun___lsb 0 | ||
| 119 | #define reg_iop_fifo_out_extra_r_intr___urun___width 1 | ||
| 120 | #define reg_iop_fifo_out_extra_r_intr___urun___bit 0 | ||
| 121 | #define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1 | ||
| 122 | #define reg_iop_fifo_out_extra_r_intr___last_data___width 1 | ||
| 123 | #define reg_iop_fifo_out_extra_r_intr___last_data___bit 1 | ||
| 124 | #define reg_iop_fifo_out_extra_r_intr___dav___lsb 2 | ||
| 125 | #define reg_iop_fifo_out_extra_r_intr___dav___width 1 | ||
| 126 | #define reg_iop_fifo_out_extra_r_intr___dav___bit 2 | ||
| 127 | #define reg_iop_fifo_out_extra_r_intr___free___lsb 3 | ||
| 128 | #define reg_iop_fifo_out_extra_r_intr___free___width 1 | ||
| 129 | #define reg_iop_fifo_out_extra_r_intr___free___bit 3 | ||
| 130 | #define reg_iop_fifo_out_extra_r_intr___orun___lsb 4 | ||
| 131 | #define reg_iop_fifo_out_extra_r_intr___orun___width 1 | ||
| 132 | #define reg_iop_fifo_out_extra_r_intr___orun___bit 4 | ||
| 133 | #define reg_iop_fifo_out_extra_r_intr_offset 24 | ||
| 134 | |||
| 135 | /* Register r_masked_intr, scope iop_fifo_out_extra, type r */ | ||
| 136 | #define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0 | ||
| 137 | #define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1 | ||
| 138 | #define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0 | ||
| 139 | #define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1 | ||
| 140 | #define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1 | ||
| 141 | #define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1 | ||
| 142 | #define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2 | ||
| 143 | #define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1 | ||
| 144 | #define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2 | ||
| 145 | #define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3 | ||
| 146 | #define reg_iop_fifo_out_extra_r_masked_intr___free___width 1 | ||
| 147 | #define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3 | ||
| 148 | #define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4 | ||
| 149 | #define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1 | ||
| 150 | #define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4 | ||
| 151 | #define reg_iop_fifo_out_extra_r_masked_intr_offset 28 | ||
| 152 | |||
| 153 | |||
| 154 | /* Constants */ | ||
| 155 | #define regk_iop_fifo_out_extra_no 0x00000000 | ||
| 156 | #define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000 | ||
| 157 | #define regk_iop_fifo_out_extra_yes 0x00000001 | ||
| 158 | #endif /* __iop_fifo_out_extra_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h deleted file mode 100644 index 80490c82cc29..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h +++ /dev/null | |||
| @@ -1,177 +0,0 @@ | |||
| 1 | #ifndef __iop_mpu_defs_asm_h | ||
| 2 | #define __iop_mpu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_mpu.r | ||
| 7 | * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r | ||
| 11 | * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #define STRIDE_iop_mpu_rw_r 4 | ||
| 57 | /* Register rw_r, scope iop_mpu, type rw */ | ||
| 58 | #define reg_iop_mpu_rw_r_offset 0 | ||
| 59 | |||
| 60 | /* Register rw_ctrl, scope iop_mpu, type rw */ | ||
| 61 | #define reg_iop_mpu_rw_ctrl___en___lsb 0 | ||
| 62 | #define reg_iop_mpu_rw_ctrl___en___width 1 | ||
| 63 | #define reg_iop_mpu_rw_ctrl___en___bit 0 | ||
| 64 | #define reg_iop_mpu_rw_ctrl_offset 128 | ||
| 65 | |||
| 66 | /* Register r_pc, scope iop_mpu, type r */ | ||
| 67 | #define reg_iop_mpu_r_pc___addr___lsb 0 | ||
| 68 | #define reg_iop_mpu_r_pc___addr___width 12 | ||
| 69 | #define reg_iop_mpu_r_pc_offset 132 | ||
| 70 | |||
| 71 | /* Register r_stat, scope iop_mpu, type r */ | ||
| 72 | #define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0 | ||
| 73 | #define reg_iop_mpu_r_stat___instr_reg_busy___width 1 | ||
| 74 | #define reg_iop_mpu_r_stat___instr_reg_busy___bit 0 | ||
| 75 | #define reg_iop_mpu_r_stat___intr_busy___lsb 1 | ||
| 76 | #define reg_iop_mpu_r_stat___intr_busy___width 1 | ||
| 77 | #define reg_iop_mpu_r_stat___intr_busy___bit 1 | ||
| 78 | #define reg_iop_mpu_r_stat___intr_vect___lsb 2 | ||
| 79 | #define reg_iop_mpu_r_stat___intr_vect___width 16 | ||
| 80 | #define reg_iop_mpu_r_stat_offset 136 | ||
| 81 | |||
| 82 | /* Register rw_instr, scope iop_mpu, type rw */ | ||
| 83 | #define reg_iop_mpu_rw_instr_offset 140 | ||
| 84 | |||
| 85 | /* Register rw_immediate, scope iop_mpu, type rw */ | ||
| 86 | #define reg_iop_mpu_rw_immediate_offset 144 | ||
| 87 | |||
| 88 | /* Register r_trace, scope iop_mpu, type r */ | ||
| 89 | #define reg_iop_mpu_r_trace___intr_vect___lsb 0 | ||
| 90 | #define reg_iop_mpu_r_trace___intr_vect___width 16 | ||
| 91 | #define reg_iop_mpu_r_trace___pc___lsb 16 | ||
| 92 | #define reg_iop_mpu_r_trace___pc___width 12 | ||
| 93 | #define reg_iop_mpu_r_trace___en___lsb 28 | ||
| 94 | #define reg_iop_mpu_r_trace___en___width 1 | ||
| 95 | #define reg_iop_mpu_r_trace___en___bit 28 | ||
| 96 | #define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29 | ||
| 97 | #define reg_iop_mpu_r_trace___instr_reg_busy___width 1 | ||
| 98 | #define reg_iop_mpu_r_trace___instr_reg_busy___bit 29 | ||
| 99 | #define reg_iop_mpu_r_trace___intr_busy___lsb 30 | ||
| 100 | #define reg_iop_mpu_r_trace___intr_busy___width 1 | ||
| 101 | #define reg_iop_mpu_r_trace___intr_busy___bit 30 | ||
| 102 | #define reg_iop_mpu_r_trace_offset 148 | ||
| 103 | |||
| 104 | /* Register r_wr_stat, scope iop_mpu, type r */ | ||
| 105 | #define reg_iop_mpu_r_wr_stat___r0___lsb 0 | ||
| 106 | #define reg_iop_mpu_r_wr_stat___r0___width 1 | ||
| 107 | #define reg_iop_mpu_r_wr_stat___r0___bit 0 | ||
| 108 | #define reg_iop_mpu_r_wr_stat___r1___lsb 1 | ||
| 109 | #define reg_iop_mpu_r_wr_stat___r1___width 1 | ||
| 110 | #define reg_iop_mpu_r_wr_stat___r1___bit 1 | ||
| 111 | #define reg_iop_mpu_r_wr_stat___r2___lsb 2 | ||
| 112 | #define reg_iop_mpu_r_wr_stat___r2___width 1 | ||
| 113 | #define reg_iop_mpu_r_wr_stat___r2___bit 2 | ||
| 114 | #define reg_iop_mpu_r_wr_stat___r3___lsb 3 | ||
| 115 | #define reg_iop_mpu_r_wr_stat___r3___width 1 | ||
| 116 | #define reg_iop_mpu_r_wr_stat___r3___bit 3 | ||
| 117 | #define reg_iop_mpu_r_wr_stat___r4___lsb 4 | ||
| 118 | #define reg_iop_mpu_r_wr_stat___r4___width 1 | ||
| 119 | #define reg_iop_mpu_r_wr_stat___r4___bit 4 | ||
| 120 | #define reg_iop_mpu_r_wr_stat___r5___lsb 5 | ||
| 121 | #define reg_iop_mpu_r_wr_stat___r5___width 1 | ||
| 122 | #define reg_iop_mpu_r_wr_stat___r5___bit 5 | ||
| 123 | #define reg_iop_mpu_r_wr_stat___r6___lsb 6 | ||
| 124 | #define reg_iop_mpu_r_wr_stat___r6___width 1 | ||
| 125 | #define reg_iop_mpu_r_wr_stat___r6___bit 6 | ||
| 126 | #define reg_iop_mpu_r_wr_stat___r7___lsb 7 | ||
| 127 | #define reg_iop_mpu_r_wr_stat___r7___width 1 | ||
| 128 | #define reg_iop_mpu_r_wr_stat___r7___bit 7 | ||
| 129 | #define reg_iop_mpu_r_wr_stat___r8___lsb 8 | ||
| 130 | #define reg_iop_mpu_r_wr_stat___r8___width 1 | ||
| 131 | #define reg_iop_mpu_r_wr_stat___r8___bit 8 | ||
| 132 | #define reg_iop_mpu_r_wr_stat___r9___lsb 9 | ||
| 133 | #define reg_iop_mpu_r_wr_stat___r9___width 1 | ||
| 134 | #define reg_iop_mpu_r_wr_stat___r9___bit 9 | ||
| 135 | #define reg_iop_mpu_r_wr_stat___r10___lsb 10 | ||
| 136 | #define reg_iop_mpu_r_wr_stat___r10___width 1 | ||
| 137 | #define reg_iop_mpu_r_wr_stat___r10___bit 10 | ||
| 138 | #define reg_iop_mpu_r_wr_stat___r11___lsb 11 | ||
| 139 | #define reg_iop_mpu_r_wr_stat___r11___width 1 | ||
| 140 | #define reg_iop_mpu_r_wr_stat___r11___bit 11 | ||
| 141 | #define reg_iop_mpu_r_wr_stat___r12___lsb 12 | ||
| 142 | #define reg_iop_mpu_r_wr_stat___r12___width 1 | ||
| 143 | #define reg_iop_mpu_r_wr_stat___r12___bit 12 | ||
| 144 | #define reg_iop_mpu_r_wr_stat___r13___lsb 13 | ||
| 145 | #define reg_iop_mpu_r_wr_stat___r13___width 1 | ||
| 146 | #define reg_iop_mpu_r_wr_stat___r13___bit 13 | ||
| 147 | #define reg_iop_mpu_r_wr_stat___r14___lsb 14 | ||
| 148 | #define reg_iop_mpu_r_wr_stat___r14___width 1 | ||
| 149 | #define reg_iop_mpu_r_wr_stat___r14___bit 14 | ||
| 150 | #define reg_iop_mpu_r_wr_stat___r15___lsb 15 | ||
| 151 | #define reg_iop_mpu_r_wr_stat___r15___width 1 | ||
| 152 | #define reg_iop_mpu_r_wr_stat___r15___bit 15 | ||
| 153 | #define reg_iop_mpu_r_wr_stat_offset 152 | ||
| 154 | |||
| 155 | #define STRIDE_iop_mpu_rw_thread 4 | ||
| 156 | /* Register rw_thread, scope iop_mpu, type rw */ | ||
| 157 | #define reg_iop_mpu_rw_thread___addr___lsb 0 | ||
| 158 | #define reg_iop_mpu_rw_thread___addr___width 12 | ||
| 159 | #define reg_iop_mpu_rw_thread_offset 156 | ||
| 160 | |||
| 161 | #define STRIDE_iop_mpu_rw_intr 4 | ||
| 162 | /* Register rw_intr, scope iop_mpu, type rw */ | ||
| 163 | #define reg_iop_mpu_rw_intr___addr___lsb 0 | ||
| 164 | #define reg_iop_mpu_rw_intr___addr___width 12 | ||
| 165 | #define reg_iop_mpu_rw_intr_offset 196 | ||
| 166 | |||
| 167 | |||
| 168 | /* Constants */ | ||
| 169 | #define regk_iop_mpu_no 0x00000000 | ||
| 170 | #define regk_iop_mpu_r_pc_default 0x00000000 | ||
| 171 | #define regk_iop_mpu_rw_ctrl_default 0x00000000 | ||
| 172 | #define regk_iop_mpu_rw_intr_size 0x00000010 | ||
| 173 | #define regk_iop_mpu_rw_r_size 0x00000010 | ||
| 174 | #define regk_iop_mpu_rw_thread_default 0x00000000 | ||
| 175 | #define regk_iop_mpu_rw_thread_size 0x00000004 | ||
| 176 | #define regk_iop_mpu_yes 0x00000001 | ||
| 177 | #endif /* __iop_mpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index a20b8857b4d0..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* Autogenerated Changes here will be lost! | ||
| 2 | * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg | ||
| 3 | */ | ||
| 4 | #define iop_version 0 | ||
| 5 | #define iop_fifo_in0_extra 64 | ||
| 6 | #define iop_fifo_in1_extra 128 | ||
| 7 | #define iop_fifo_out0_extra 192 | ||
| 8 | #define iop_fifo_out1_extra 256 | ||
| 9 | #define iop_trigger_grp0 320 | ||
| 10 | #define iop_trigger_grp1 384 | ||
| 11 | #define iop_trigger_grp2 448 | ||
| 12 | #define iop_trigger_grp3 512 | ||
| 13 | #define iop_trigger_grp4 576 | ||
| 14 | #define iop_trigger_grp5 640 | ||
| 15 | #define iop_trigger_grp6 704 | ||
| 16 | #define iop_trigger_grp7 768 | ||
| 17 | #define iop_crc_par0 896 | ||
| 18 | #define iop_crc_par1 1024 | ||
| 19 | #define iop_dmc_in0 1152 | ||
| 20 | #define iop_dmc_in1 1280 | ||
| 21 | #define iop_dmc_out0 1408 | ||
| 22 | #define iop_dmc_out1 1536 | ||
| 23 | #define iop_fifo_in0 1664 | ||
| 24 | #define iop_fifo_in1 1792 | ||
| 25 | #define iop_fifo_out0 1920 | ||
| 26 | #define iop_fifo_out1 2048 | ||
| 27 | #define iop_scrc_in0 2176 | ||
| 28 | #define iop_scrc_in1 2304 | ||
| 29 | #define iop_scrc_out0 2432 | ||
| 30 | #define iop_scrc_out1 2560 | ||
| 31 | #define iop_timer_grp0 2688 | ||
| 32 | #define iop_timer_grp1 2816 | ||
| 33 | #define iop_timer_grp2 2944 | ||
| 34 | #define iop_timer_grp3 3072 | ||
| 35 | #define iop_sap_in 3328 | ||
| 36 | #define iop_sap_out 3584 | ||
| 37 | #define iop_spu0 3840 | ||
| 38 | #define iop_spu1 4096 | ||
| 39 | #define iop_sw_cfg 4352 | ||
| 40 | #define iop_sw_cpu 4608 | ||
| 41 | #define iop_sw_mpu 4864 | ||
| 42 | #define iop_sw_spu0 5120 | ||
| 43 | #define iop_sw_spu1 5376 | ||
| 44 | #define iop_mpu 5632 | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index a4a10ff300b3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null | |||
| @@ -1,182 +0,0 @@ | |||
| 1 | #ifndef __iop_sap_in_defs_asm_h | ||
| 2 | #define __iop_sap_in_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_sap_in.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r | ||
| 11 | * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_bus0_sync, scope iop_sap_in, type rw */ | ||
| 57 | #define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0 | ||
| 58 | #define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2 | ||
| 59 | #define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2 | ||
| 60 | #define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3 | ||
| 61 | #define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5 | ||
| 62 | #define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2 | ||
| 63 | #define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7 | ||
| 64 | #define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1 | ||
| 65 | #define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7 | ||
| 66 | #define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8 | ||
| 67 | #define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2 | ||
| 68 | #define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10 | ||
| 69 | #define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3 | ||
| 70 | #define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13 | ||
| 71 | #define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2 | ||
| 72 | #define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15 | ||
| 73 | #define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1 | ||
| 74 | #define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15 | ||
| 75 | #define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16 | ||
| 76 | #define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2 | ||
| 77 | #define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18 | ||
| 78 | #define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3 | ||
| 79 | #define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21 | ||
| 80 | #define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2 | ||
| 81 | #define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23 | ||
| 82 | #define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1 | ||
| 83 | #define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23 | ||
| 84 | #define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24 | ||
| 85 | #define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2 | ||
| 86 | #define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26 | ||
| 87 | #define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3 | ||
| 88 | #define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29 | ||
| 89 | #define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2 | ||
| 90 | #define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31 | ||
| 91 | #define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1 | ||
| 92 | #define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31 | ||
| 93 | #define reg_iop_sap_in_rw_bus0_sync_offset 0 | ||
| 94 | |||
| 95 | /* Register rw_bus1_sync, scope iop_sap_in, type rw */ | ||
| 96 | #define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0 | ||
| 97 | #define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2 | ||
| 98 | #define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2 | ||
| 99 | #define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3 | ||
| 100 | #define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5 | ||
| 101 | #define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2 | ||
| 102 | #define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7 | ||
| 103 | #define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1 | ||
| 104 | #define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7 | ||
| 105 | #define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8 | ||
| 106 | #define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2 | ||
| 107 | #define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10 | ||
| 108 | #define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3 | ||
| 109 | #define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13 | ||
| 110 | #define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2 | ||
| 111 | #define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15 | ||
| 112 | #define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1 | ||
| 113 | #define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15 | ||
| 114 | #define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16 | ||
| 115 | #define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2 | ||
| 116 | #define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18 | ||
| 117 | #define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3 | ||
| 118 | #define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21 | ||
| 119 | #define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2 | ||
| 120 | #define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23 | ||
| 121 | #define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1 | ||
| 122 | #define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23 | ||
| 123 | #define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24 | ||
| 124 | #define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2 | ||
| 125 | #define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26 | ||
| 126 | #define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3 | ||
| 127 | #define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29 | ||
| 128 | #define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2 | ||
| 129 | #define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31 | ||
| 130 | #define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1 | ||
| 131 | #define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31 | ||
| 132 | #define reg_iop_sap_in_rw_bus1_sync_offset 4 | ||
| 133 | |||
| 134 | #define STRIDE_iop_sap_in_rw_gio 4 | ||
| 135 | /* Register rw_gio, scope iop_sap_in, type rw */ | ||
| 136 | #define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 | ||
| 137 | #define reg_iop_sap_in_rw_gio___sync_sel___width 2 | ||
| 138 | #define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 | ||
| 139 | #define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 | ||
| 140 | #define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 | ||
| 141 | #define reg_iop_sap_in_rw_gio___sync_edge___width 2 | ||
| 142 | #define reg_iop_sap_in_rw_gio___delay___lsb 7 | ||
| 143 | #define reg_iop_sap_in_rw_gio___delay___width 1 | ||
| 144 | #define reg_iop_sap_in_rw_gio___delay___bit 7 | ||
| 145 | #define reg_iop_sap_in_rw_gio___logic___lsb 8 | ||
| 146 | #define reg_iop_sap_in_rw_gio___logic___width 2 | ||
| 147 | #define reg_iop_sap_in_rw_gio_offset 8 | ||
| 148 | |||
| 149 | |||
| 150 | /* Constants */ | ||
| 151 | #define regk_iop_sap_in_and 0x00000002 | ||
| 152 | #define regk_iop_sap_in_ext_clk200 0x00000003 | ||
| 153 | #define regk_iop_sap_in_gio1 0x00000000 | ||
| 154 | #define regk_iop_sap_in_gio13 0x00000005 | ||
| 155 | #define regk_iop_sap_in_gio18 0x00000003 | ||
| 156 | #define regk_iop_sap_in_gio19 0x00000004 | ||
| 157 | #define regk_iop_sap_in_gio21 0x00000006 | ||
| 158 | #define regk_iop_sap_in_gio23 0x00000005 | ||
| 159 | #define regk_iop_sap_in_gio29 0x00000007 | ||
| 160 | #define regk_iop_sap_in_gio5 0x00000004 | ||
| 161 | #define regk_iop_sap_in_gio6 0x00000001 | ||
| 162 | #define regk_iop_sap_in_gio7 0x00000002 | ||
| 163 | #define regk_iop_sap_in_inv 0x00000001 | ||
| 164 | #define regk_iop_sap_in_neg 0x00000002 | ||
| 165 | #define regk_iop_sap_in_no 0x00000000 | ||
| 166 | #define regk_iop_sap_in_no_del_ext_clk200 0x00000001 | ||
| 167 | #define regk_iop_sap_in_none 0x00000000 | ||
| 168 | #define regk_iop_sap_in_or 0x00000003 | ||
| 169 | #define regk_iop_sap_in_pos 0x00000001 | ||
| 170 | #define regk_iop_sap_in_pos_neg 0x00000003 | ||
| 171 | #define regk_iop_sap_in_rw_bus0_sync_default 0x02020202 | ||
| 172 | #define regk_iop_sap_in_rw_bus1_sync_default 0x02020202 | ||
| 173 | #define regk_iop_sap_in_rw_gio_default 0x00000002 | ||
| 174 | #define regk_iop_sap_in_rw_gio_size 0x00000020 | ||
| 175 | #define regk_iop_sap_in_timer_grp0_tmr3 0x00000006 | ||
| 176 | #define regk_iop_sap_in_timer_grp1_tmr3 0x00000004 | ||
| 177 | #define regk_iop_sap_in_timer_grp2_tmr3 0x00000005 | ||
| 178 | #define regk_iop_sap_in_timer_grp3_tmr3 0x00000007 | ||
| 179 | #define regk_iop_sap_in_tmr_clk200 0x00000000 | ||
| 180 | #define regk_iop_sap_in_two_clk200 0x00000002 | ||
| 181 | #define regk_iop_sap_in_yes 0x00000001 | ||
| 182 | #endif /* __iop_sap_in_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 0ec727f92a25..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null | |||
| @@ -1,346 +0,0 @@ | |||
| 1 | #ifndef __iop_sap_out_defs_asm_h | ||
| 2 | #define __iop_sap_out_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_sap_out.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r | ||
| 11 | * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
| 57 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 | ||
| 58 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 | ||
| 59 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 | ||
| 60 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 | ||
| 61 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 | ||
| 62 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 | ||
| 63 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 | ||
| 64 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 | ||
| 65 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 | ||
| 66 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 | ||
| 67 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 | ||
| 68 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 | ||
| 69 | #define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 | ||
| 70 | #define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 | ||
| 71 | #define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 | ||
| 72 | #define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 | ||
| 73 | #define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 | ||
| 74 | #define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 | ||
| 75 | #define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 | ||
| 76 | #define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 | ||
| 77 | #define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 | ||
| 78 | #define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 | ||
| 79 | #define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 | ||
| 80 | #define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 | ||
| 81 | #define reg_iop_sap_out_rw_gen_gated_offset 0 | ||
| 82 | |||
| 83 | /* Register rw_bus0, scope iop_sap_out, type rw */ | ||
| 84 | #define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 | ||
| 85 | #define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 | ||
| 86 | #define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 | ||
| 87 | #define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 | ||
| 88 | #define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 | ||
| 89 | #define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 | ||
| 90 | #define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 | ||
| 91 | #define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 | ||
| 92 | #define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 | ||
| 93 | #define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 | ||
| 94 | #define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 | ||
| 95 | #define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 | ||
| 96 | #define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 | ||
| 97 | #define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 | ||
| 98 | #define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 | ||
| 99 | #define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 | ||
| 100 | #define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 | ||
| 101 | #define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 | ||
| 102 | #define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 | ||
| 103 | #define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 | ||
| 104 | #define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 | ||
| 105 | #define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 | ||
| 106 | #define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 | ||
| 107 | #define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 | ||
| 108 | #define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 | ||
| 109 | #define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 | ||
| 110 | #define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 | ||
| 111 | #define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 | ||
| 112 | #define reg_iop_sap_out_rw_bus0_offset 4 | ||
| 113 | |||
| 114 | /* Register rw_bus1, scope iop_sap_out, type rw */ | ||
| 115 | #define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 | ||
| 116 | #define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 | ||
| 117 | #define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 | ||
| 118 | #define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 | ||
| 119 | #define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 | ||
| 120 | #define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 | ||
| 121 | #define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 | ||
| 122 | #define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 | ||
| 123 | #define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 | ||
| 124 | #define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 | ||
| 125 | #define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 | ||
| 126 | #define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 | ||
| 127 | #define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 | ||
| 128 | #define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 | ||
| 129 | #define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 | ||
| 130 | #define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 | ||
| 131 | #define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 | ||
| 132 | #define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 | ||
| 133 | #define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 | ||
| 134 | #define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 | ||
| 135 | #define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 | ||
| 136 | #define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 | ||
| 137 | #define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 | ||
| 138 | #define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 | ||
| 139 | #define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 | ||
| 140 | #define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 | ||
| 141 | #define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 | ||
| 142 | #define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 | ||
| 143 | #define reg_iop_sap_out_rw_bus1_offset 8 | ||
| 144 | |||
| 145 | /* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ | ||
| 146 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 | ||
| 147 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 | ||
| 148 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 | ||
| 149 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 | ||
| 150 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 | ||
| 151 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 | ||
| 152 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 | ||
| 153 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 | ||
| 154 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 | ||
| 155 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 | ||
| 156 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 | ||
| 157 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 | ||
| 158 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 | ||
| 159 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 | ||
| 160 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 | ||
| 161 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 | ||
| 162 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 | ||
| 163 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 | ||
| 164 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 | ||
| 165 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 | ||
| 166 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 | ||
| 167 | #define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 | ||
| 168 | #define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 | ||
| 169 | |||
| 170 | /* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ | ||
| 171 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 | ||
| 172 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 | ||
| 173 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 | ||
| 174 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 | ||
| 175 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 | ||
| 176 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 | ||
| 177 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 | ||
| 178 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 | ||
| 179 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 | ||
| 180 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 | ||
| 181 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 | ||
| 182 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 | ||
| 183 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 | ||
| 184 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 | ||
| 185 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 | ||
| 186 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 | ||
| 187 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 | ||
| 188 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 | ||
| 189 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 | ||
| 190 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 | ||
| 191 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 | ||
| 192 | #define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 | ||
| 193 | #define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 | ||
| 194 | |||
| 195 | /* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ | ||
| 196 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 | ||
| 197 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 | ||
| 198 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 | ||
| 199 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 | ||
| 200 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 | ||
| 201 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 | ||
| 202 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 | ||
| 203 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 | ||
| 204 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 | ||
| 205 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 | ||
| 206 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 | ||
| 207 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 | ||
| 208 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 | ||
| 209 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 | ||
| 210 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 | ||
| 211 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 | ||
| 212 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 | ||
| 213 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 | ||
| 214 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 | ||
| 215 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 | ||
| 216 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 | ||
| 217 | #define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 | ||
| 218 | #define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 | ||
| 219 | |||
| 220 | /* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ | ||
| 221 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 | ||
| 222 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 | ||
| 223 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 | ||
| 224 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 | ||
| 225 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 | ||
| 226 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 | ||
| 227 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 | ||
| 228 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 | ||
| 229 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 | ||
| 230 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 | ||
| 231 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 | ||
| 232 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 | ||
| 233 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 | ||
| 234 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 | ||
| 235 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 | ||
| 236 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 | ||
| 237 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 | ||
| 238 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 | ||
| 239 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 | ||
| 240 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 | ||
| 241 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 | ||
| 242 | #define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 | ||
| 243 | #define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 | ||
| 244 | |||
| 245 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
| 246 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
| 247 | #define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 | ||
| 248 | #define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 | ||
| 249 | #define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 | ||
| 250 | #define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 | ||
| 251 | #define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 | ||
| 252 | #define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 | ||
| 253 | #define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 | ||
| 254 | #define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 | ||
| 255 | #define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 | ||
| 256 | #define reg_iop_sap_out_rw_gio___out_logic___lsb 10 | ||
| 257 | #define reg_iop_sap_out_rw_gio___out_logic___width 1 | ||
| 258 | #define reg_iop_sap_out_rw_gio___out_logic___bit 10 | ||
| 259 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 | ||
| 260 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 | ||
| 261 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 | ||
| 262 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 | ||
| 263 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 | ||
| 264 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 | ||
| 265 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 | ||
| 266 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 | ||
| 267 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 | ||
| 268 | #define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 | ||
| 269 | #define reg_iop_sap_out_rw_gio___oe_logic___width 2 | ||
| 270 | #define reg_iop_sap_out_rw_gio_offset 28 | ||
| 271 | |||
| 272 | |||
| 273 | /* Constants */ | ||
| 274 | #define regk_iop_sap_out_and 0x00000002 | ||
| 275 | #define regk_iop_sap_out_clk0 0x00000000 | ||
| 276 | #define regk_iop_sap_out_clk1 0x00000001 | ||
| 277 | #define regk_iop_sap_out_clk12 0x00000002 | ||
| 278 | #define regk_iop_sap_out_clk2 0x00000002 | ||
| 279 | #define regk_iop_sap_out_clk200 0x00000001 | ||
| 280 | #define regk_iop_sap_out_clk3 0x00000003 | ||
| 281 | #define regk_iop_sap_out_ext 0x00000003 | ||
| 282 | #define regk_iop_sap_out_gated 0x00000004 | ||
| 283 | #define regk_iop_sap_out_gio1 0x00000000 | ||
| 284 | #define regk_iop_sap_out_gio13 0x00000002 | ||
| 285 | #define regk_iop_sap_out_gio13_clk 0x0000000c | ||
| 286 | #define regk_iop_sap_out_gio15 0x00000001 | ||
| 287 | #define regk_iop_sap_out_gio18 0x00000003 | ||
| 288 | #define regk_iop_sap_out_gio18_clk 0x0000000d | ||
| 289 | #define regk_iop_sap_out_gio1_clk 0x00000008 | ||
| 290 | #define regk_iop_sap_out_gio21_clk 0x0000000e | ||
| 291 | #define regk_iop_sap_out_gio23 0x00000002 | ||
| 292 | #define regk_iop_sap_out_gio29_clk 0x0000000f | ||
| 293 | #define regk_iop_sap_out_gio31 0x00000003 | ||
| 294 | #define regk_iop_sap_out_gio5 0x00000001 | ||
| 295 | #define regk_iop_sap_out_gio5_clk 0x00000009 | ||
| 296 | #define regk_iop_sap_out_gio6_clk 0x0000000a | ||
| 297 | #define regk_iop_sap_out_gio7 0x00000000 | ||
| 298 | #define regk_iop_sap_out_gio7_clk 0x0000000b | ||
| 299 | #define regk_iop_sap_out_gio_in13 0x00000001 | ||
| 300 | #define regk_iop_sap_out_gio_in21 0x00000002 | ||
| 301 | #define regk_iop_sap_out_gio_in29 0x00000003 | ||
| 302 | #define regk_iop_sap_out_gio_in5 0x00000000 | ||
| 303 | #define regk_iop_sap_out_inv 0x00000001 | ||
| 304 | #define regk_iop_sap_out_nand 0x00000003 | ||
| 305 | #define regk_iop_sap_out_no 0x00000000 | ||
| 306 | #define regk_iop_sap_out_none 0x00000000 | ||
| 307 | #define regk_iop_sap_out_rw_bus0_default 0x00000000 | ||
| 308 | #define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 | ||
| 309 | #define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 | ||
| 310 | #define regk_iop_sap_out_rw_bus1_default 0x00000000 | ||
| 311 | #define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 | ||
| 312 | #define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 | ||
| 313 | #define regk_iop_sap_out_rw_gen_gated_default 0x00000000 | ||
| 314 | #define regk_iop_sap_out_rw_gio_default 0x00000000 | ||
| 315 | #define regk_iop_sap_out_rw_gio_size 0x00000020 | ||
| 316 | #define regk_iop_sap_out_spu0_gio0 0x00000002 | ||
| 317 | #define regk_iop_sap_out_spu0_gio1 0x00000003 | ||
| 318 | #define regk_iop_sap_out_spu0_gio12 0x00000004 | ||
| 319 | #define regk_iop_sap_out_spu0_gio13 0x00000004 | ||
| 320 | #define regk_iop_sap_out_spu0_gio14 0x00000004 | ||
| 321 | #define regk_iop_sap_out_spu0_gio15 0x00000004 | ||
| 322 | #define regk_iop_sap_out_spu0_gio2 0x00000002 | ||
| 323 | #define regk_iop_sap_out_spu0_gio3 0x00000003 | ||
| 324 | #define regk_iop_sap_out_spu0_gio4 0x00000002 | ||
| 325 | #define regk_iop_sap_out_spu0_gio5 0x00000003 | ||
| 326 | #define regk_iop_sap_out_spu0_gio6 0x00000002 | ||
| 327 | #define regk_iop_sap_out_spu0_gio7 0x00000003 | ||
| 328 | #define regk_iop_sap_out_spu1_gio0 0x00000005 | ||
| 329 | #define regk_iop_sap_out_spu1_gio1 0x00000006 | ||
| 330 | #define regk_iop_sap_out_spu1_gio12 0x00000007 | ||
| 331 | #define regk_iop_sap_out_spu1_gio13 0x00000007 | ||
| 332 | #define regk_iop_sap_out_spu1_gio14 0x00000007 | ||
| 333 | #define regk_iop_sap_out_spu1_gio15 0x00000007 | ||
| 334 | #define regk_iop_sap_out_spu1_gio2 0x00000005 | ||
| 335 | #define regk_iop_sap_out_spu1_gio3 0x00000006 | ||
| 336 | #define regk_iop_sap_out_spu1_gio4 0x00000005 | ||
| 337 | #define regk_iop_sap_out_spu1_gio5 0x00000006 | ||
| 338 | #define regk_iop_sap_out_spu1_gio6 0x00000005 | ||
| 339 | #define regk_iop_sap_out_spu1_gio7 0x00000006 | ||
| 340 | #define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 | ||
| 341 | #define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 | ||
| 342 | #define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 | ||
| 343 | #define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 | ||
| 344 | #define regk_iop_sap_out_tmr 0x00000005 | ||
| 345 | #define regk_iop_sap_out_yes 0x00000001 | ||
| 346 | #endif /* __iop_sap_out_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h deleted file mode 100644 index 2cf5721597fc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h +++ /dev/null | |||
| @@ -1,111 +0,0 @@ | |||
| 1 | #ifndef __iop_scrc_in_defs_asm_h | ||
| 2 | #define __iop_scrc_in_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_scrc_in.r | ||
| 7 | * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r | ||
| 11 | * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope iop_scrc_in, type rw */ | ||
| 57 | #define reg_iop_scrc_in_rw_cfg___trig___lsb 0 | ||
| 58 | #define reg_iop_scrc_in_rw_cfg___trig___width 2 | ||
| 59 | #define reg_iop_scrc_in_rw_cfg_offset 0 | ||
| 60 | |||
| 61 | /* Register rw_ctrl, scope iop_scrc_in, type rw */ | ||
| 62 | #define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 | ||
| 63 | #define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 | ||
| 64 | #define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 | ||
| 65 | #define reg_iop_scrc_in_rw_ctrl_offset 4 | ||
| 66 | |||
| 67 | /* Register r_stat, scope iop_scrc_in, type r */ | ||
| 68 | #define reg_iop_scrc_in_r_stat___err___lsb 0 | ||
| 69 | #define reg_iop_scrc_in_r_stat___err___width 1 | ||
| 70 | #define reg_iop_scrc_in_r_stat___err___bit 0 | ||
| 71 | #define reg_iop_scrc_in_r_stat_offset 8 | ||
| 72 | |||
| 73 | /* Register rw_init_crc, scope iop_scrc_in, type rw */ | ||
| 74 | #define reg_iop_scrc_in_rw_init_crc_offset 12 | ||
| 75 | |||
| 76 | /* Register rs_computed_crc, scope iop_scrc_in, type rs */ | ||
| 77 | #define reg_iop_scrc_in_rs_computed_crc_offset 16 | ||
| 78 | |||
| 79 | /* Register r_computed_crc, scope iop_scrc_in, type r */ | ||
| 80 | #define reg_iop_scrc_in_r_computed_crc_offset 20 | ||
| 81 | |||
| 82 | /* Register rw_crc, scope iop_scrc_in, type rw */ | ||
| 83 | #define reg_iop_scrc_in_rw_crc_offset 24 | ||
| 84 | |||
| 85 | /* Register rw_correct_crc, scope iop_scrc_in, type rw */ | ||
| 86 | #define reg_iop_scrc_in_rw_correct_crc_offset 28 | ||
| 87 | |||
| 88 | /* Register rw_wr1bit, scope iop_scrc_in, type rw */ | ||
| 89 | #define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 | ||
| 90 | #define reg_iop_scrc_in_rw_wr1bit___data___width 2 | ||
| 91 | #define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 | ||
| 92 | #define reg_iop_scrc_in_rw_wr1bit___last___width 2 | ||
| 93 | #define reg_iop_scrc_in_rw_wr1bit_offset 32 | ||
| 94 | |||
| 95 | |||
| 96 | /* Constants */ | ||
| 97 | #define regk_iop_scrc_in_dif_in 0x00000002 | ||
| 98 | #define regk_iop_scrc_in_hi 0x00000000 | ||
| 99 | #define regk_iop_scrc_in_neg 0x00000002 | ||
| 100 | #define regk_iop_scrc_in_no 0x00000000 | ||
| 101 | #define regk_iop_scrc_in_pos 0x00000001 | ||
| 102 | #define regk_iop_scrc_in_pos_neg 0x00000003 | ||
| 103 | #define regk_iop_scrc_in_r_computed_crc_default 0x00000000 | ||
| 104 | #define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 | ||
| 105 | #define regk_iop_scrc_in_rw_cfg_default 0x00000000 | ||
| 106 | #define regk_iop_scrc_in_rw_ctrl_default 0x00000000 | ||
| 107 | #define regk_iop_scrc_in_rw_init_crc_default 0x00000000 | ||
| 108 | #define regk_iop_scrc_in_set0 0x00000000 | ||
| 109 | #define regk_iop_scrc_in_set1 0x00000001 | ||
| 110 | #define regk_iop_scrc_in_yes 0x00000001 | ||
| 111 | #endif /* __iop_scrc_in_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h deleted file mode 100644 index 640a25725f20..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h +++ /dev/null | |||
| @@ -1,105 +0,0 @@ | |||
| 1 | #ifndef __iop_scrc_out_defs_asm_h | ||
| 2 | #define __iop_scrc_out_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_scrc_out.r | ||
| 7 | * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r | ||
| 11 | * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope iop_scrc_out, type rw */ | ||
| 57 | #define reg_iop_scrc_out_rw_cfg___trig___lsb 0 | ||
| 58 | #define reg_iop_scrc_out_rw_cfg___trig___width 2 | ||
| 59 | #define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2 | ||
| 60 | #define reg_iop_scrc_out_rw_cfg___inv_crc___width 1 | ||
| 61 | #define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2 | ||
| 62 | #define reg_iop_scrc_out_rw_cfg_offset 0 | ||
| 63 | |||
| 64 | /* Register rw_ctrl, scope iop_scrc_out, type rw */ | ||
| 65 | #define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0 | ||
| 66 | #define reg_iop_scrc_out_rw_ctrl___strb_src___width 1 | ||
| 67 | #define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0 | ||
| 68 | #define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1 | ||
| 69 | #define reg_iop_scrc_out_rw_ctrl___out_src___width 1 | ||
| 70 | #define reg_iop_scrc_out_rw_ctrl___out_src___bit 1 | ||
| 71 | #define reg_iop_scrc_out_rw_ctrl_offset 4 | ||
| 72 | |||
| 73 | /* Register rw_init_crc, scope iop_scrc_out, type rw */ | ||
| 74 | #define reg_iop_scrc_out_rw_init_crc_offset 8 | ||
| 75 | |||
| 76 | /* Register rw_crc, scope iop_scrc_out, type rw */ | ||
| 77 | #define reg_iop_scrc_out_rw_crc_offset 12 | ||
| 78 | |||
| 79 | /* Register rw_data, scope iop_scrc_out, type rw */ | ||
| 80 | #define reg_iop_scrc_out_rw_data___val___lsb 0 | ||
| 81 | #define reg_iop_scrc_out_rw_data___val___width 1 | ||
| 82 | #define reg_iop_scrc_out_rw_data___val___bit 0 | ||
| 83 | #define reg_iop_scrc_out_rw_data_offset 16 | ||
| 84 | |||
| 85 | /* Register r_computed_crc, scope iop_scrc_out, type r */ | ||
| 86 | #define reg_iop_scrc_out_r_computed_crc_offset 20 | ||
| 87 | |||
| 88 | |||
| 89 | /* Constants */ | ||
| 90 | #define regk_iop_scrc_out_crc 0x00000001 | ||
| 91 | #define regk_iop_scrc_out_data 0x00000000 | ||
| 92 | #define regk_iop_scrc_out_dif 0x00000001 | ||
| 93 | #define regk_iop_scrc_out_hi 0x00000000 | ||
| 94 | #define regk_iop_scrc_out_neg 0x00000002 | ||
| 95 | #define regk_iop_scrc_out_no 0x00000000 | ||
| 96 | #define regk_iop_scrc_out_pos 0x00000001 | ||
| 97 | #define regk_iop_scrc_out_pos_neg 0x00000003 | ||
| 98 | #define regk_iop_scrc_out_reg 0x00000000 | ||
| 99 | #define regk_iop_scrc_out_rw_cfg_default 0x00000000 | ||
| 100 | #define regk_iop_scrc_out_rw_crc_default 0x00000000 | ||
| 101 | #define regk_iop_scrc_out_rw_ctrl_default 0x00000000 | ||
| 102 | #define regk_iop_scrc_out_rw_data_default 0x00000000 | ||
| 103 | #define regk_iop_scrc_out_rw_init_crc_default 0x00000000 | ||
| 104 | #define regk_iop_scrc_out_yes 0x00000001 | ||
| 105 | #endif /* __iop_scrc_out_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h deleted file mode 100644 index bb402c1aa761..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h +++ /dev/null | |||
| @@ -1,573 +0,0 @@ | |||
| 1 | #ifndef __iop_spu_defs_asm_h | ||
| 2 | #define __iop_spu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_spu.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r | ||
| 11 | * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #define STRIDE_iop_spu_rw_r 4 | ||
| 57 | /* Register rw_r, scope iop_spu, type rw */ | ||
| 58 | #define reg_iop_spu_rw_r_offset 0 | ||
| 59 | |||
| 60 | /* Register rw_seq_pc, scope iop_spu, type rw */ | ||
| 61 | #define reg_iop_spu_rw_seq_pc___addr___lsb 0 | ||
| 62 | #define reg_iop_spu_rw_seq_pc___addr___width 12 | ||
| 63 | #define reg_iop_spu_rw_seq_pc_offset 64 | ||
| 64 | |||
| 65 | /* Register rw_fsm_pc, scope iop_spu, type rw */ | ||
| 66 | #define reg_iop_spu_rw_fsm_pc___addr___lsb 0 | ||
| 67 | #define reg_iop_spu_rw_fsm_pc___addr___width 12 | ||
| 68 | #define reg_iop_spu_rw_fsm_pc_offset 68 | ||
| 69 | |||
| 70 | /* Register rw_ctrl, scope iop_spu, type rw */ | ||
| 71 | #define reg_iop_spu_rw_ctrl___fsm___lsb 0 | ||
| 72 | #define reg_iop_spu_rw_ctrl___fsm___width 1 | ||
| 73 | #define reg_iop_spu_rw_ctrl___fsm___bit 0 | ||
| 74 | #define reg_iop_spu_rw_ctrl___en___lsb 1 | ||
| 75 | #define reg_iop_spu_rw_ctrl___en___width 1 | ||
| 76 | #define reg_iop_spu_rw_ctrl___en___bit 1 | ||
| 77 | #define reg_iop_spu_rw_ctrl_offset 72 | ||
| 78 | |||
| 79 | /* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ | ||
| 80 | #define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 | ||
| 81 | #define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 | ||
| 82 | #define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 | ||
| 83 | #define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 | ||
| 84 | #define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 | ||
| 85 | #define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 | ||
| 86 | #define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 | ||
| 87 | #define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 | ||
| 88 | #define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 | ||
| 89 | #define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 | ||
| 90 | #define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 | ||
| 91 | #define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 | ||
| 92 | #define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 | ||
| 93 | #define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 | ||
| 94 | #define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 | ||
| 95 | #define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 | ||
| 96 | #define reg_iop_spu_rw_fsm_inputs3_0_offset 76 | ||
| 97 | |||
| 98 | /* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ | ||
| 99 | #define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 | ||
| 100 | #define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 | ||
| 101 | #define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 | ||
| 102 | #define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 | ||
| 103 | #define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 | ||
| 104 | #define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 | ||
| 105 | #define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 | ||
| 106 | #define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 | ||
| 107 | #define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 | ||
| 108 | #define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 | ||
| 109 | #define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 | ||
| 110 | #define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 | ||
| 111 | #define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 | ||
| 112 | #define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 | ||
| 113 | #define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 | ||
| 114 | #define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 | ||
| 115 | #define reg_iop_spu_rw_fsm_inputs7_4_offset 80 | ||
| 116 | |||
| 117 | /* Register rw_gio_out, scope iop_spu, type rw */ | ||
| 118 | #define reg_iop_spu_rw_gio_out_offset 84 | ||
| 119 | |||
| 120 | /* Register rw_bus0_out, scope iop_spu, type rw */ | ||
| 121 | #define reg_iop_spu_rw_bus0_out_offset 88 | ||
| 122 | |||
| 123 | /* Register rw_bus1_out, scope iop_spu, type rw */ | ||
| 124 | #define reg_iop_spu_rw_bus1_out_offset 92 | ||
| 125 | |||
| 126 | /* Register r_gio_in, scope iop_spu, type r */ | ||
| 127 | #define reg_iop_spu_r_gio_in_offset 96 | ||
| 128 | |||
| 129 | /* Register r_bus0_in, scope iop_spu, type r */ | ||
| 130 | #define reg_iop_spu_r_bus0_in_offset 100 | ||
| 131 | |||
| 132 | /* Register r_bus1_in, scope iop_spu, type r */ | ||
| 133 | #define reg_iop_spu_r_bus1_in_offset 104 | ||
| 134 | |||
| 135 | /* Register rw_gio_out_set, scope iop_spu, type rw */ | ||
| 136 | #define reg_iop_spu_rw_gio_out_set_offset 108 | ||
| 137 | |||
| 138 | /* Register rw_gio_out_clr, scope iop_spu, type rw */ | ||
| 139 | #define reg_iop_spu_rw_gio_out_clr_offset 112 | ||
| 140 | |||
| 141 | /* Register rs_wr_stat, scope iop_spu, type rs */ | ||
| 142 | #define reg_iop_spu_rs_wr_stat___r0___lsb 0 | ||
| 143 | #define reg_iop_spu_rs_wr_stat___r0___width 1 | ||
| 144 | #define reg_iop_spu_rs_wr_stat___r0___bit 0 | ||
| 145 | #define reg_iop_spu_rs_wr_stat___r1___lsb 1 | ||
| 146 | #define reg_iop_spu_rs_wr_stat___r1___width 1 | ||
| 147 | #define reg_iop_spu_rs_wr_stat___r1___bit 1 | ||
| 148 | #define reg_iop_spu_rs_wr_stat___r2___lsb 2 | ||
| 149 | #define reg_iop_spu_rs_wr_stat___r2___width 1 | ||
| 150 | #define reg_iop_spu_rs_wr_stat___r2___bit 2 | ||
| 151 | #define reg_iop_spu_rs_wr_stat___r3___lsb 3 | ||
| 152 | #define reg_iop_spu_rs_wr_stat___r3___width 1 | ||
| 153 | #define reg_iop_spu_rs_wr_stat___r3___bit 3 | ||
| 154 | #define reg_iop_spu_rs_wr_stat___r4___lsb 4 | ||
| 155 | #define reg_iop_spu_rs_wr_stat___r4___width 1 | ||
| 156 | #define reg_iop_spu_rs_wr_stat___r4___bit 4 | ||
| 157 | #define reg_iop_spu_rs_wr_stat___r5___lsb 5 | ||
| 158 | #define reg_iop_spu_rs_wr_stat___r5___width 1 | ||
| 159 | #define reg_iop_spu_rs_wr_stat___r5___bit 5 | ||
| 160 | #define reg_iop_spu_rs_wr_stat___r6___lsb 6 | ||
| 161 | #define reg_iop_spu_rs_wr_stat___r6___width 1 | ||
| 162 | #define reg_iop_spu_rs_wr_stat___r6___bit 6 | ||
| 163 | #define reg_iop_spu_rs_wr_stat___r7___lsb 7 | ||
| 164 | #define reg_iop_spu_rs_wr_stat___r7___width 1 | ||
| 165 | #define reg_iop_spu_rs_wr_stat___r7___bit 7 | ||
| 166 | #define reg_iop_spu_rs_wr_stat___r8___lsb 8 | ||
| 167 | #define reg_iop_spu_rs_wr_stat___r8___width 1 | ||
| 168 | #define reg_iop_spu_rs_wr_stat___r8___bit 8 | ||
| 169 | #define reg_iop_spu_rs_wr_stat___r9___lsb 9 | ||
| 170 | #define reg_iop_spu_rs_wr_stat___r9___width 1 | ||
| 171 | #define reg_iop_spu_rs_wr_stat___r9___bit 9 | ||
| 172 | #define reg_iop_spu_rs_wr_stat___r10___lsb 10 | ||
| 173 | #define reg_iop_spu_rs_wr_stat___r10___width 1 | ||
| 174 | #define reg_iop_spu_rs_wr_stat___r10___bit 10 | ||
| 175 | #define reg_iop_spu_rs_wr_stat___r11___lsb 11 | ||
| 176 | #define reg_iop_spu_rs_wr_stat___r11___width 1 | ||
| 177 | #define reg_iop_spu_rs_wr_stat___r11___bit 11 | ||
| 178 | #define reg_iop_spu_rs_wr_stat___r12___lsb 12 | ||
| 179 | #define reg_iop_spu_rs_wr_stat___r12___width 1 | ||
| 180 | #define reg_iop_spu_rs_wr_stat___r12___bit 12 | ||
| 181 | #define reg_iop_spu_rs_wr_stat___r13___lsb 13 | ||
| 182 | #define reg_iop_spu_rs_wr_stat___r13___width 1 | ||
| 183 | #define reg_iop_spu_rs_wr_stat___r13___bit 13 | ||
| 184 | #define reg_iop_spu_rs_wr_stat___r14___lsb 14 | ||
| 185 | #define reg_iop_spu_rs_wr_stat___r14___width 1 | ||
| 186 | #define reg_iop_spu_rs_wr_stat___r14___bit 14 | ||
| 187 | #define reg_iop_spu_rs_wr_stat___r15___lsb 15 | ||
| 188 | #define reg_iop_spu_rs_wr_stat___r15___width 1 | ||
| 189 | #define reg_iop_spu_rs_wr_stat___r15___bit 15 | ||
| 190 | #define reg_iop_spu_rs_wr_stat_offset 116 | ||
| 191 | |||
| 192 | /* Register r_wr_stat, scope iop_spu, type r */ | ||
| 193 | #define reg_iop_spu_r_wr_stat___r0___lsb 0 | ||
| 194 | #define reg_iop_spu_r_wr_stat___r0___width 1 | ||
| 195 | #define reg_iop_spu_r_wr_stat___r0___bit 0 | ||
| 196 | #define reg_iop_spu_r_wr_stat___r1___lsb 1 | ||
| 197 | #define reg_iop_spu_r_wr_stat___r1___width 1 | ||
| 198 | #define reg_iop_spu_r_wr_stat___r1___bit 1 | ||
| 199 | #define reg_iop_spu_r_wr_stat___r2___lsb 2 | ||
| 200 | #define reg_iop_spu_r_wr_stat___r2___width 1 | ||
| 201 | #define reg_iop_spu_r_wr_stat___r2___bit 2 | ||
| 202 | #define reg_iop_spu_r_wr_stat___r3___lsb 3 | ||
| 203 | #define reg_iop_spu_r_wr_stat___r3___width 1 | ||
| 204 | #define reg_iop_spu_r_wr_stat___r3___bit 3 | ||
| 205 | #define reg_iop_spu_r_wr_stat___r4___lsb 4 | ||
| 206 | #define reg_iop_spu_r_wr_stat___r4___width 1 | ||
| 207 | #define reg_iop_spu_r_wr_stat___r4___bit 4 | ||
| 208 | #define reg_iop_spu_r_wr_stat___r5___lsb 5 | ||
| 209 | #define reg_iop_spu_r_wr_stat___r5___width 1 | ||
| 210 | #define reg_iop_spu_r_wr_stat___r5___bit 5 | ||
| 211 | #define reg_iop_spu_r_wr_stat___r6___lsb 6 | ||
| 212 | #define reg_iop_spu_r_wr_stat___r6___width 1 | ||
| 213 | #define reg_iop_spu_r_wr_stat___r6___bit 6 | ||
| 214 | #define reg_iop_spu_r_wr_stat___r7___lsb 7 | ||
| 215 | #define reg_iop_spu_r_wr_stat___r7___width 1 | ||
| 216 | #define reg_iop_spu_r_wr_stat___r7___bit 7 | ||
| 217 | #define reg_iop_spu_r_wr_stat___r8___lsb 8 | ||
| 218 | #define reg_iop_spu_r_wr_stat___r8___width 1 | ||
| 219 | #define reg_iop_spu_r_wr_stat___r8___bit 8 | ||
| 220 | #define reg_iop_spu_r_wr_stat___r9___lsb 9 | ||
| 221 | #define reg_iop_spu_r_wr_stat___r9___width 1 | ||
| 222 | #define reg_iop_spu_r_wr_stat___r9___bit 9 | ||
| 223 | #define reg_iop_spu_r_wr_stat___r10___lsb 10 | ||
| 224 | #define reg_iop_spu_r_wr_stat___r10___width 1 | ||
| 225 | #define reg_iop_spu_r_wr_stat___r10___bit 10 | ||
| 226 | #define reg_iop_spu_r_wr_stat___r11___lsb 11 | ||
| 227 | #define reg_iop_spu_r_wr_stat___r11___width 1 | ||
| 228 | #define reg_iop_spu_r_wr_stat___r11___bit 11 | ||
| 229 | #define reg_iop_spu_r_wr_stat___r12___lsb 12 | ||
| 230 | #define reg_iop_spu_r_wr_stat___r12___width 1 | ||
| 231 | #define reg_iop_spu_r_wr_stat___r12___bit 12 | ||
| 232 | #define reg_iop_spu_r_wr_stat___r13___lsb 13 | ||
| 233 | #define reg_iop_spu_r_wr_stat___r13___width 1 | ||
| 234 | #define reg_iop_spu_r_wr_stat___r13___bit 13 | ||
| 235 | #define reg_iop_spu_r_wr_stat___r14___lsb 14 | ||
| 236 | #define reg_iop_spu_r_wr_stat___r14___width 1 | ||
| 237 | #define reg_iop_spu_r_wr_stat___r14___bit 14 | ||
| 238 | #define reg_iop_spu_r_wr_stat___r15___lsb 15 | ||
| 239 | #define reg_iop_spu_r_wr_stat___r15___width 1 | ||
| 240 | #define reg_iop_spu_r_wr_stat___r15___bit 15 | ||
| 241 | #define reg_iop_spu_r_wr_stat_offset 120 | ||
| 242 | |||
| 243 | /* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ | ||
| 244 | #define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 | ||
| 245 | |||
| 246 | /* Register r_stat_in, scope iop_spu, type r */ | ||
| 247 | #define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 | ||
| 248 | #define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 | ||
| 249 | #define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 | ||
| 250 | #define reg_iop_spu_r_stat_in___fifo_out_last___width 1 | ||
| 251 | #define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 | ||
| 252 | #define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 | ||
| 253 | #define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 | ||
| 254 | #define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 | ||
| 255 | #define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 | ||
| 256 | #define reg_iop_spu_r_stat_in___fifo_out_all___width 1 | ||
| 257 | #define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 | ||
| 258 | #define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 | ||
| 259 | #define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 | ||
| 260 | #define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 | ||
| 261 | #define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 | ||
| 262 | #define reg_iop_spu_r_stat_in___dmc_out_all___width 1 | ||
| 263 | #define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 | ||
| 264 | #define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 | ||
| 265 | #define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 | ||
| 266 | #define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 | ||
| 267 | #define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 | ||
| 268 | #define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 | ||
| 269 | #define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 | ||
| 270 | #define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 | ||
| 271 | #define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 | ||
| 272 | #define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 | ||
| 273 | #define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 | ||
| 274 | #define reg_iop_spu_r_stat_in___dmc_out_last___width 1 | ||
| 275 | #define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 | ||
| 276 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 | ||
| 277 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 | ||
| 278 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 | ||
| 279 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 | ||
| 280 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 | ||
| 281 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 | ||
| 282 | #define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 | ||
| 283 | #define reg_iop_spu_r_stat_in___pcrc_correct___width 1 | ||
| 284 | #define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 | ||
| 285 | #define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 | ||
| 286 | #define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 | ||
| 287 | #define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 | ||
| 288 | #define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 | ||
| 289 | #define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 | ||
| 290 | #define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 | ||
| 291 | #define reg_iop_spu_r_stat_in___dmc_in_full___width 1 | ||
| 292 | #define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 | ||
| 293 | #define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 | ||
| 294 | #define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 | ||
| 295 | #define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 | ||
| 296 | #define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 | ||
| 297 | #define reg_iop_spu_r_stat_in___spu_gio_out___width 4 | ||
| 298 | #define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 | ||
| 299 | #define reg_iop_spu_r_stat_in___sync_clk12___width 1 | ||
| 300 | #define reg_iop_spu_r_stat_in___sync_clk12___bit 27 | ||
| 301 | #define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 | ||
| 302 | #define reg_iop_spu_r_stat_in___scrc_out_data___width 1 | ||
| 303 | #define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 | ||
| 304 | #define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 | ||
| 305 | #define reg_iop_spu_r_stat_in___scrc_in_err___width 1 | ||
| 306 | #define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 | ||
| 307 | #define reg_iop_spu_r_stat_in___mc_busy___lsb 30 | ||
| 308 | #define reg_iop_spu_r_stat_in___mc_busy___width 1 | ||
| 309 | #define reg_iop_spu_r_stat_in___mc_busy___bit 30 | ||
| 310 | #define reg_iop_spu_r_stat_in___mc_owned___lsb 31 | ||
| 311 | #define reg_iop_spu_r_stat_in___mc_owned___width 1 | ||
| 312 | #define reg_iop_spu_r_stat_in___mc_owned___bit 31 | ||
| 313 | #define reg_iop_spu_r_stat_in_offset 128 | ||
| 314 | |||
| 315 | /* Register r_trigger_in, scope iop_spu, type r */ | ||
| 316 | #define reg_iop_spu_r_trigger_in_offset 132 | ||
| 317 | |||
| 318 | /* Register r_special_stat, scope iop_spu, type r */ | ||
| 319 | #define reg_iop_spu_r_special_stat___c_flag___lsb 0 | ||
| 320 | #define reg_iop_spu_r_special_stat___c_flag___width 1 | ||
| 321 | #define reg_iop_spu_r_special_stat___c_flag___bit 0 | ||
| 322 | #define reg_iop_spu_r_special_stat___v_flag___lsb 1 | ||
| 323 | #define reg_iop_spu_r_special_stat___v_flag___width 1 | ||
| 324 | #define reg_iop_spu_r_special_stat___v_flag___bit 1 | ||
| 325 | #define reg_iop_spu_r_special_stat___z_flag___lsb 2 | ||
| 326 | #define reg_iop_spu_r_special_stat___z_flag___width 1 | ||
| 327 | #define reg_iop_spu_r_special_stat___z_flag___bit 2 | ||
| 328 | #define reg_iop_spu_r_special_stat___n_flag___lsb 3 | ||
| 329 | #define reg_iop_spu_r_special_stat___n_flag___width 1 | ||
| 330 | #define reg_iop_spu_r_special_stat___n_flag___bit 3 | ||
| 331 | #define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 | ||
| 332 | #define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 | ||
| 333 | #define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 | ||
| 334 | #define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 | ||
| 335 | #define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 | ||
| 336 | #define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 | ||
| 337 | #define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 | ||
| 338 | #define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 | ||
| 339 | #define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 | ||
| 340 | #define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 | ||
| 341 | #define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 | ||
| 342 | #define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 | ||
| 343 | #define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 | ||
| 344 | #define reg_iop_spu_r_special_stat___fsm_in0___width 1 | ||
| 345 | #define reg_iop_spu_r_special_stat___fsm_in0___bit 8 | ||
| 346 | #define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 | ||
| 347 | #define reg_iop_spu_r_special_stat___fsm_in1___width 1 | ||
| 348 | #define reg_iop_spu_r_special_stat___fsm_in1___bit 9 | ||
| 349 | #define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 | ||
| 350 | #define reg_iop_spu_r_special_stat___fsm_in2___width 1 | ||
| 351 | #define reg_iop_spu_r_special_stat___fsm_in2___bit 10 | ||
| 352 | #define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 | ||
| 353 | #define reg_iop_spu_r_special_stat___fsm_in3___width 1 | ||
| 354 | #define reg_iop_spu_r_special_stat___fsm_in3___bit 11 | ||
| 355 | #define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 | ||
| 356 | #define reg_iop_spu_r_special_stat___fsm_in4___width 1 | ||
| 357 | #define reg_iop_spu_r_special_stat___fsm_in4___bit 12 | ||
| 358 | #define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 | ||
| 359 | #define reg_iop_spu_r_special_stat___fsm_in5___width 1 | ||
| 360 | #define reg_iop_spu_r_special_stat___fsm_in5___bit 13 | ||
| 361 | #define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 | ||
| 362 | #define reg_iop_spu_r_special_stat___fsm_in6___width 1 | ||
| 363 | #define reg_iop_spu_r_special_stat___fsm_in6___bit 14 | ||
| 364 | #define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 | ||
| 365 | #define reg_iop_spu_r_special_stat___fsm_in7___width 1 | ||
| 366 | #define reg_iop_spu_r_special_stat___fsm_in7___bit 15 | ||
| 367 | #define reg_iop_spu_r_special_stat___event0___lsb 16 | ||
| 368 | #define reg_iop_spu_r_special_stat___event0___width 1 | ||
| 369 | #define reg_iop_spu_r_special_stat___event0___bit 16 | ||
| 370 | #define reg_iop_spu_r_special_stat___event1___lsb 17 | ||
| 371 | #define reg_iop_spu_r_special_stat___event1___width 1 | ||
| 372 | #define reg_iop_spu_r_special_stat___event1___bit 17 | ||
| 373 | #define reg_iop_spu_r_special_stat___event2___lsb 18 | ||
| 374 | #define reg_iop_spu_r_special_stat___event2___width 1 | ||
| 375 | #define reg_iop_spu_r_special_stat___event2___bit 18 | ||
| 376 | #define reg_iop_spu_r_special_stat___event3___lsb 19 | ||
| 377 | #define reg_iop_spu_r_special_stat___event3___width 1 | ||
| 378 | #define reg_iop_spu_r_special_stat___event3___bit 19 | ||
| 379 | #define reg_iop_spu_r_special_stat_offset 136 | ||
| 380 | |||
| 381 | /* Register rw_reg_access, scope iop_spu, type rw */ | ||
| 382 | #define reg_iop_spu_rw_reg_access___addr___lsb 0 | ||
| 383 | #define reg_iop_spu_rw_reg_access___addr___width 13 | ||
| 384 | #define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 | ||
| 385 | #define reg_iop_spu_rw_reg_access___imm_hi___width 16 | ||
| 386 | #define reg_iop_spu_rw_reg_access_offset 140 | ||
| 387 | |||
| 388 | #define STRIDE_iop_spu_rw_event_cfg 4 | ||
| 389 | /* Register rw_event_cfg, scope iop_spu, type rw */ | ||
| 390 | #define reg_iop_spu_rw_event_cfg___addr___lsb 0 | ||
| 391 | #define reg_iop_spu_rw_event_cfg___addr___width 12 | ||
| 392 | #define reg_iop_spu_rw_event_cfg___src___lsb 12 | ||
| 393 | #define reg_iop_spu_rw_event_cfg___src___width 2 | ||
| 394 | #define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 | ||
| 395 | #define reg_iop_spu_rw_event_cfg___eq_en___width 1 | ||
| 396 | #define reg_iop_spu_rw_event_cfg___eq_en___bit 14 | ||
| 397 | #define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 | ||
| 398 | #define reg_iop_spu_rw_event_cfg___eq_inv___width 1 | ||
| 399 | #define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 | ||
| 400 | #define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 | ||
| 401 | #define reg_iop_spu_rw_event_cfg___gt_en___width 1 | ||
| 402 | #define reg_iop_spu_rw_event_cfg___gt_en___bit 16 | ||
| 403 | #define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 | ||
| 404 | #define reg_iop_spu_rw_event_cfg___gt_inv___width 1 | ||
| 405 | #define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 | ||
| 406 | #define reg_iop_spu_rw_event_cfg_offset 144 | ||
| 407 | |||
| 408 | #define STRIDE_iop_spu_rw_event_mask 4 | ||
| 409 | /* Register rw_event_mask, scope iop_spu, type rw */ | ||
| 410 | #define reg_iop_spu_rw_event_mask_offset 160 | ||
| 411 | |||
| 412 | #define STRIDE_iop_spu_rw_event_val 4 | ||
| 413 | /* Register rw_event_val, scope iop_spu, type rw */ | ||
| 414 | #define reg_iop_spu_rw_event_val_offset 176 | ||
| 415 | |||
| 416 | /* Register rw_event_ret, scope iop_spu, type rw */ | ||
| 417 | #define reg_iop_spu_rw_event_ret___addr___lsb 0 | ||
| 418 | #define reg_iop_spu_rw_event_ret___addr___width 12 | ||
| 419 | #define reg_iop_spu_rw_event_ret_offset 192 | ||
| 420 | |||
| 421 | /* Register r_trace, scope iop_spu, type r */ | ||
| 422 | #define reg_iop_spu_r_trace___fsm___lsb 0 | ||
| 423 | #define reg_iop_spu_r_trace___fsm___width 1 | ||
| 424 | #define reg_iop_spu_r_trace___fsm___bit 0 | ||
| 425 | #define reg_iop_spu_r_trace___en___lsb 1 | ||
| 426 | #define reg_iop_spu_r_trace___en___width 1 | ||
| 427 | #define reg_iop_spu_r_trace___en___bit 1 | ||
| 428 | #define reg_iop_spu_r_trace___c_flag___lsb 2 | ||
| 429 | #define reg_iop_spu_r_trace___c_flag___width 1 | ||
| 430 | #define reg_iop_spu_r_trace___c_flag___bit 2 | ||
| 431 | #define reg_iop_spu_r_trace___v_flag___lsb 3 | ||
| 432 | #define reg_iop_spu_r_trace___v_flag___width 1 | ||
| 433 | #define reg_iop_spu_r_trace___v_flag___bit 3 | ||
| 434 | #define reg_iop_spu_r_trace___z_flag___lsb 4 | ||
| 435 | #define reg_iop_spu_r_trace___z_flag___width 1 | ||
| 436 | #define reg_iop_spu_r_trace___z_flag___bit 4 | ||
| 437 | #define reg_iop_spu_r_trace___n_flag___lsb 5 | ||
| 438 | #define reg_iop_spu_r_trace___n_flag___width 1 | ||
| 439 | #define reg_iop_spu_r_trace___n_flag___bit 5 | ||
| 440 | #define reg_iop_spu_r_trace___seq_addr___lsb 6 | ||
| 441 | #define reg_iop_spu_r_trace___seq_addr___width 12 | ||
| 442 | #define reg_iop_spu_r_trace___fsm_addr___lsb 20 | ||
| 443 | #define reg_iop_spu_r_trace___fsm_addr___width 12 | ||
| 444 | #define reg_iop_spu_r_trace_offset 196 | ||
| 445 | |||
| 446 | /* Register r_fsm_trace, scope iop_spu, type r */ | ||
| 447 | #define reg_iop_spu_r_fsm_trace___fsm___lsb 0 | ||
| 448 | #define reg_iop_spu_r_fsm_trace___fsm___width 1 | ||
| 449 | #define reg_iop_spu_r_fsm_trace___fsm___bit 0 | ||
| 450 | #define reg_iop_spu_r_fsm_trace___en___lsb 1 | ||
| 451 | #define reg_iop_spu_r_fsm_trace___en___width 1 | ||
| 452 | #define reg_iop_spu_r_fsm_trace___en___bit 1 | ||
| 453 | #define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 | ||
| 454 | #define reg_iop_spu_r_fsm_trace___tmr_done___width 1 | ||
| 455 | #define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 | ||
| 456 | #define reg_iop_spu_r_fsm_trace___inp0___lsb 3 | ||
| 457 | #define reg_iop_spu_r_fsm_trace___inp0___width 1 | ||
| 458 | #define reg_iop_spu_r_fsm_trace___inp0___bit 3 | ||
| 459 | #define reg_iop_spu_r_fsm_trace___inp1___lsb 4 | ||
| 460 | #define reg_iop_spu_r_fsm_trace___inp1___width 1 | ||
| 461 | #define reg_iop_spu_r_fsm_trace___inp1___bit 4 | ||
| 462 | #define reg_iop_spu_r_fsm_trace___inp2___lsb 5 | ||
| 463 | #define reg_iop_spu_r_fsm_trace___inp2___width 1 | ||
| 464 | #define reg_iop_spu_r_fsm_trace___inp2___bit 5 | ||
| 465 | #define reg_iop_spu_r_fsm_trace___inp3___lsb 6 | ||
| 466 | #define reg_iop_spu_r_fsm_trace___inp3___width 1 | ||
| 467 | #define reg_iop_spu_r_fsm_trace___inp3___bit 6 | ||
| 468 | #define reg_iop_spu_r_fsm_trace___event0___lsb 7 | ||
| 469 | #define reg_iop_spu_r_fsm_trace___event0___width 1 | ||
| 470 | #define reg_iop_spu_r_fsm_trace___event0___bit 7 | ||
| 471 | #define reg_iop_spu_r_fsm_trace___event1___lsb 8 | ||
| 472 | #define reg_iop_spu_r_fsm_trace___event1___width 1 | ||
| 473 | #define reg_iop_spu_r_fsm_trace___event1___bit 8 | ||
| 474 | #define reg_iop_spu_r_fsm_trace___event2___lsb 9 | ||
| 475 | #define reg_iop_spu_r_fsm_trace___event2___width 1 | ||
| 476 | #define reg_iop_spu_r_fsm_trace___event2___bit 9 | ||
| 477 | #define reg_iop_spu_r_fsm_trace___event3___lsb 10 | ||
| 478 | #define reg_iop_spu_r_fsm_trace___event3___width 1 | ||
| 479 | #define reg_iop_spu_r_fsm_trace___event3___bit 10 | ||
| 480 | #define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 | ||
| 481 | #define reg_iop_spu_r_fsm_trace___gio_out___width 8 | ||
| 482 | #define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 | ||
| 483 | #define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 | ||
| 484 | #define reg_iop_spu_r_fsm_trace_offset 200 | ||
| 485 | |||
| 486 | #define STRIDE_iop_spu_rw_brp 4 | ||
| 487 | /* Register rw_brp, scope iop_spu, type rw */ | ||
| 488 | #define reg_iop_spu_rw_brp___addr___lsb 0 | ||
| 489 | #define reg_iop_spu_rw_brp___addr___width 12 | ||
| 490 | #define reg_iop_spu_rw_brp___fsm___lsb 12 | ||
| 491 | #define reg_iop_spu_rw_brp___fsm___width 1 | ||
| 492 | #define reg_iop_spu_rw_brp___fsm___bit 12 | ||
| 493 | #define reg_iop_spu_rw_brp___en___lsb 13 | ||
| 494 | #define reg_iop_spu_rw_brp___en___width 1 | ||
| 495 | #define reg_iop_spu_rw_brp___en___bit 13 | ||
| 496 | #define reg_iop_spu_rw_brp_offset 204 | ||
| 497 | |||
| 498 | |||
| 499 | /* Constants */ | ||
| 500 | #define regk_iop_spu_attn_hi 0x00000005 | ||
| 501 | #define regk_iop_spu_attn_lo 0x00000005 | ||
| 502 | #define regk_iop_spu_attn_r0 0x00000000 | ||
| 503 | #define regk_iop_spu_attn_r1 0x00000001 | ||
| 504 | #define regk_iop_spu_attn_r10 0x00000002 | ||
| 505 | #define regk_iop_spu_attn_r11 0x00000003 | ||
| 506 | #define regk_iop_spu_attn_r12 0x00000004 | ||
| 507 | #define regk_iop_spu_attn_r13 0x00000005 | ||
| 508 | #define regk_iop_spu_attn_r14 0x00000006 | ||
| 509 | #define regk_iop_spu_attn_r15 0x00000007 | ||
| 510 | #define regk_iop_spu_attn_r2 0x00000002 | ||
| 511 | #define regk_iop_spu_attn_r3 0x00000003 | ||
| 512 | #define regk_iop_spu_attn_r4 0x00000004 | ||
| 513 | #define regk_iop_spu_attn_r5 0x00000005 | ||
| 514 | #define regk_iop_spu_attn_r6 0x00000006 | ||
| 515 | #define regk_iop_spu_attn_r7 0x00000007 | ||
| 516 | #define regk_iop_spu_attn_r8 0x00000000 | ||
| 517 | #define regk_iop_spu_attn_r9 0x00000001 | ||
| 518 | #define regk_iop_spu_c 0x00000000 | ||
| 519 | #define regk_iop_spu_flag 0x00000002 | ||
| 520 | #define regk_iop_spu_gio_in 0x00000000 | ||
| 521 | #define regk_iop_spu_gio_out 0x00000005 | ||
| 522 | #define regk_iop_spu_gio_out0 0x00000008 | ||
| 523 | #define regk_iop_spu_gio_out1 0x00000009 | ||
| 524 | #define regk_iop_spu_gio_out2 0x0000000a | ||
| 525 | #define regk_iop_spu_gio_out3 0x0000000b | ||
| 526 | #define regk_iop_spu_gio_out4 0x0000000c | ||
| 527 | #define regk_iop_spu_gio_out5 0x0000000d | ||
| 528 | #define regk_iop_spu_gio_out6 0x0000000e | ||
| 529 | #define regk_iop_spu_gio_out7 0x0000000f | ||
| 530 | #define regk_iop_spu_n 0x00000003 | ||
| 531 | #define regk_iop_spu_no 0x00000000 | ||
| 532 | #define regk_iop_spu_r0 0x00000008 | ||
| 533 | #define regk_iop_spu_r1 0x00000009 | ||
| 534 | #define regk_iop_spu_r10 0x0000000a | ||
| 535 | #define regk_iop_spu_r11 0x0000000b | ||
| 536 | #define regk_iop_spu_r12 0x0000000c | ||
| 537 | #define regk_iop_spu_r13 0x0000000d | ||
| 538 | #define regk_iop_spu_r14 0x0000000e | ||
| 539 | #define regk_iop_spu_r15 0x0000000f | ||
| 540 | #define regk_iop_spu_r2 0x0000000a | ||
| 541 | #define regk_iop_spu_r3 0x0000000b | ||
| 542 | #define regk_iop_spu_r4 0x0000000c | ||
| 543 | #define regk_iop_spu_r5 0x0000000d | ||
| 544 | #define regk_iop_spu_r6 0x0000000e | ||
| 545 | #define regk_iop_spu_r7 0x0000000f | ||
| 546 | #define regk_iop_spu_r8 0x00000008 | ||
| 547 | #define regk_iop_spu_r9 0x00000009 | ||
| 548 | #define regk_iop_spu_reg_hi 0x00000002 | ||
| 549 | #define regk_iop_spu_reg_lo 0x00000002 | ||
| 550 | #define regk_iop_spu_rw_brp_default 0x00000000 | ||
| 551 | #define regk_iop_spu_rw_brp_size 0x00000004 | ||
| 552 | #define regk_iop_spu_rw_ctrl_default 0x00000000 | ||
| 553 | #define regk_iop_spu_rw_event_cfg_size 0x00000004 | ||
| 554 | #define regk_iop_spu_rw_event_mask_size 0x00000004 | ||
| 555 | #define regk_iop_spu_rw_event_val_size 0x00000004 | ||
| 556 | #define regk_iop_spu_rw_gio_out_default 0x00000000 | ||
| 557 | #define regk_iop_spu_rw_r_size 0x00000010 | ||
| 558 | #define regk_iop_spu_rw_reg_access_default 0x00000000 | ||
| 559 | #define regk_iop_spu_stat_in 0x00000002 | ||
| 560 | #define regk_iop_spu_statin_hi 0x00000004 | ||
| 561 | #define regk_iop_spu_statin_lo 0x00000004 | ||
| 562 | #define regk_iop_spu_trig 0x00000003 | ||
| 563 | #define regk_iop_spu_trigger 0x00000006 | ||
| 564 | #define regk_iop_spu_v 0x00000001 | ||
| 565 | #define regk_iop_spu_wsts_gioout_spec 0x00000001 | ||
| 566 | #define regk_iop_spu_xor 0x00000003 | ||
| 567 | #define regk_iop_spu_xor_bus0_r2_0 0x00000000 | ||
| 568 | #define regk_iop_spu_xor_bus0m_r2_0 0x00000002 | ||
| 569 | #define regk_iop_spu_xor_bus1_r3_0 0x00000001 | ||
| 570 | #define regk_iop_spu_xor_bus1m_r3_0 0x00000003 | ||
| 571 | #define regk_iop_spu_yes 0x00000001 | ||
| 572 | #define regk_iop_spu_z 0x00000002 | ||
| 573 | #endif /* __iop_spu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index 3be60f9b024c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null | |||
| @@ -1,1052 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_cfg_defs_asm_h | ||
| 2 | #define __iop_sw_cfg_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:19 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r | ||
| 11 | * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ | ||
| 57 | #define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 | ||
| 58 | #define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 | ||
| 59 | #define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 | ||
| 60 | |||
| 61 | /* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ | ||
| 62 | #define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 | ||
| 63 | #define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 | ||
| 64 | #define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 | ||
| 65 | |||
| 66 | /* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ | ||
| 67 | #define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 | ||
| 68 | #define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 | ||
| 69 | #define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 | ||
| 70 | |||
| 71 | /* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ | ||
| 72 | #define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 | ||
| 73 | #define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 | ||
| 74 | #define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 | ||
| 75 | |||
| 76 | /* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ | ||
| 77 | #define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 | ||
| 78 | #define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 | ||
| 79 | #define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 | ||
| 80 | |||
| 81 | /* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ | ||
| 82 | #define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 | ||
| 83 | #define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 | ||
| 84 | #define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 | ||
| 85 | |||
| 86 | /* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ | ||
| 87 | #define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 | ||
| 88 | #define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 | ||
| 89 | #define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 | ||
| 90 | |||
| 91 | /* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 92 | #define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 | ||
| 93 | #define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 | ||
| 94 | #define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 | ||
| 95 | |||
| 96 | /* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ | ||
| 97 | #define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 | ||
| 98 | #define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 | ||
| 99 | #define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 | ||
| 100 | |||
| 101 | /* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 102 | #define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 | ||
| 103 | #define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 | ||
| 104 | #define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 | ||
| 105 | |||
| 106 | /* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ | ||
| 107 | #define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 | ||
| 108 | #define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 | ||
| 109 | #define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 | ||
| 110 | |||
| 111 | /* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 112 | #define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 | ||
| 113 | #define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 | ||
| 114 | #define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 | ||
| 115 | |||
| 116 | /* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ | ||
| 117 | #define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 | ||
| 118 | #define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 | ||
| 119 | #define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 | ||
| 120 | |||
| 121 | /* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 122 | #define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 | ||
| 123 | #define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 | ||
| 124 | #define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 | ||
| 125 | |||
| 126 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | ||
| 127 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 | ||
| 128 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 | ||
| 129 | #define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 | ||
| 130 | |||
| 131 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | ||
| 132 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 | ||
| 133 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 | ||
| 134 | #define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 | ||
| 135 | |||
| 136 | /* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ | ||
| 137 | #define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 | ||
| 138 | #define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 | ||
| 139 | #define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 | ||
| 140 | |||
| 141 | /* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ | ||
| 142 | #define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 | ||
| 143 | #define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 | ||
| 144 | #define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 | ||
| 145 | |||
| 146 | /* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ | ||
| 147 | #define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 | ||
| 148 | #define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 | ||
| 149 | #define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 | ||
| 150 | |||
| 151 | /* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ | ||
| 152 | #define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 | ||
| 153 | #define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 | ||
| 154 | #define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 | ||
| 155 | |||
| 156 | /* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ | ||
| 157 | #define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 | ||
| 158 | #define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 | ||
| 159 | #define reg_iop_sw_cfg_rw_spu0_owner_offset 80 | ||
| 160 | |||
| 161 | /* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ | ||
| 162 | #define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 | ||
| 163 | #define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 | ||
| 164 | #define reg_iop_sw_cfg_rw_spu1_owner_offset 84 | ||
| 165 | |||
| 166 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 167 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 | ||
| 168 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 | ||
| 169 | #define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 | ||
| 170 | |||
| 171 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 172 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 | ||
| 173 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 | ||
| 174 | #define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 | ||
| 175 | |||
| 176 | /* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ | ||
| 177 | #define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 | ||
| 178 | #define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 | ||
| 179 | #define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 | ||
| 180 | |||
| 181 | /* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ | ||
| 182 | #define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 | ||
| 183 | #define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 | ||
| 184 | #define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 | ||
| 185 | |||
| 186 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 187 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 | ||
| 188 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 | ||
| 189 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 | ||
| 190 | |||
| 191 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 192 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 | ||
| 193 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 | ||
| 194 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 | ||
| 195 | |||
| 196 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | ||
| 197 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 | ||
| 198 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 | ||
| 199 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 | ||
| 200 | |||
| 201 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | ||
| 202 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 | ||
| 203 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 | ||
| 204 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 | ||
| 205 | |||
| 206 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | ||
| 207 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 | ||
| 208 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 | ||
| 209 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 | ||
| 210 | |||
| 211 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | ||
| 212 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 | ||
| 213 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 | ||
| 214 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 | ||
| 215 | |||
| 216 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | ||
| 217 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 | ||
| 218 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 | ||
| 219 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 | ||
| 220 | |||
| 221 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | ||
| 222 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 | ||
| 223 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 | ||
| 224 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 | ||
| 225 | |||
| 226 | /* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ | ||
| 227 | #define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 | ||
| 228 | #define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 | ||
| 229 | #define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 | ||
| 230 | #define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 | ||
| 231 | #define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 | ||
| 232 | #define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 | ||
| 233 | #define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 | ||
| 234 | #define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 | ||
| 235 | #define reg_iop_sw_cfg_rw_bus0_mask_offset 136 | ||
| 236 | |||
| 237 | /* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 238 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 | ||
| 239 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 | ||
| 240 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 | ||
| 241 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 | ||
| 242 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 | ||
| 243 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 | ||
| 244 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 | ||
| 245 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 | ||
| 246 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 | ||
| 247 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 | ||
| 248 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 | ||
| 249 | #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 | ||
| 250 | #define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 | ||
| 251 | |||
| 252 | /* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ | ||
| 253 | #define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 | ||
| 254 | #define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 | ||
| 255 | #define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 | ||
| 256 | #define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 | ||
| 257 | #define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 | ||
| 258 | #define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 | ||
| 259 | #define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 | ||
| 260 | #define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 | ||
| 261 | #define reg_iop_sw_cfg_rw_bus1_mask_offset 144 | ||
| 262 | |||
| 263 | /* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 264 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 | ||
| 265 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 | ||
| 266 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 | ||
| 267 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 | ||
| 268 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 | ||
| 269 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 | ||
| 270 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 | ||
| 271 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 | ||
| 272 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 | ||
| 273 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 | ||
| 274 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 | ||
| 275 | #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 | ||
| 276 | #define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 | ||
| 277 | |||
| 278 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | ||
| 279 | #define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 | ||
| 280 | #define reg_iop_sw_cfg_rw_gio_mask___val___width 32 | ||
| 281 | #define reg_iop_sw_cfg_rw_gio_mask_offset 152 | ||
| 282 | |||
| 283 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 284 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 | ||
| 285 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 | ||
| 286 | #define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 | ||
| 287 | |||
| 288 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | ||
| 289 | #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 | ||
| 290 | #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 | ||
| 291 | #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 | ||
| 292 | #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 | ||
| 293 | #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 | ||
| 294 | #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 | ||
| 295 | #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 | ||
| 296 | #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 | ||
| 297 | #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 | ||
| 298 | #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 | ||
| 299 | #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 | ||
| 300 | #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 | ||
| 301 | #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 | ||
| 302 | #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 | ||
| 303 | #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 | ||
| 304 | #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 | ||
| 305 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 | ||
| 306 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 | ||
| 307 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 | ||
| 308 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 | ||
| 309 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 | ||
| 310 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 | ||
| 311 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 | ||
| 312 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 | ||
| 313 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 | ||
| 314 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 | ||
| 315 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 | ||
| 316 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 | ||
| 317 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 | ||
| 318 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 | ||
| 319 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 | ||
| 320 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 | ||
| 321 | #define reg_iop_sw_cfg_rw_pinmapping_offset 160 | ||
| 322 | |||
| 323 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | ||
| 324 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 | ||
| 325 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 | ||
| 326 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 | ||
| 327 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 | ||
| 328 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 | ||
| 329 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 | ||
| 330 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 | ||
| 331 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 | ||
| 332 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 | ||
| 333 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 | ||
| 334 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 | ||
| 335 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 | ||
| 336 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 | ||
| 337 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 | ||
| 338 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 | ||
| 339 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 | ||
| 340 | #define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 | ||
| 341 | |||
| 342 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 343 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 | ||
| 344 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 | ||
| 345 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 | ||
| 346 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 | ||
| 347 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 | ||
| 348 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 | ||
| 349 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 | ||
| 350 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 | ||
| 351 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 | ||
| 352 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 | ||
| 353 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 | ||
| 354 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 | ||
| 355 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 | ||
| 356 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 | ||
| 357 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 | ||
| 358 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 | ||
| 359 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 | ||
| 360 | |||
| 361 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 362 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 | ||
| 363 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 | ||
| 364 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 | ||
| 365 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 | ||
| 366 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 | ||
| 367 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 | ||
| 368 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 | ||
| 369 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 | ||
| 370 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 | ||
| 371 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 | ||
| 372 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 | ||
| 373 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 | ||
| 374 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 | ||
| 375 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 | ||
| 376 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 | ||
| 377 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 | ||
| 378 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 | ||
| 379 | |||
| 380 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
| 381 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 | ||
| 382 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 | ||
| 383 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 | ||
| 384 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 | ||
| 385 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 | ||
| 386 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 | ||
| 387 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 | ||
| 388 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 | ||
| 389 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 | ||
| 390 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 | ||
| 391 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 | ||
| 392 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 | ||
| 393 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 | ||
| 394 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 | ||
| 395 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 | ||
| 396 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 | ||
| 397 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 | ||
| 398 | |||
| 399 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
| 400 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 | ||
| 401 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 | ||
| 402 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 | ||
| 403 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 | ||
| 404 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 | ||
| 405 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 | ||
| 406 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 | ||
| 407 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 | ||
| 408 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 | ||
| 409 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 | ||
| 410 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 | ||
| 411 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 | ||
| 412 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 | ||
| 413 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 | ||
| 414 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 | ||
| 415 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 | ||
| 416 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 | ||
| 417 | |||
| 418 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | ||
| 419 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 | ||
| 420 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 | ||
| 421 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 | ||
| 422 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 | ||
| 423 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 | ||
| 424 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 | ||
| 425 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 | ||
| 426 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 | ||
| 427 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 | ||
| 428 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 | ||
| 429 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 | ||
| 430 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 | ||
| 431 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 | ||
| 432 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 | ||
| 433 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 | ||
| 434 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 | ||
| 435 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 | ||
| 436 | |||
| 437 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | ||
| 438 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 | ||
| 439 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 | ||
| 440 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 | ||
| 441 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 | ||
| 442 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 | ||
| 443 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 | ||
| 444 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 | ||
| 445 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 | ||
| 446 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 | ||
| 447 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 | ||
| 448 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 | ||
| 449 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 | ||
| 450 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 | ||
| 451 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 | ||
| 452 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 | ||
| 453 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 | ||
| 454 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 | ||
| 455 | |||
| 456 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | ||
| 457 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 | ||
| 458 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 | ||
| 459 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 | ||
| 460 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 | ||
| 461 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 | ||
| 462 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 | ||
| 463 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 | ||
| 464 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 | ||
| 465 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 | ||
| 466 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 | ||
| 467 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 | ||
| 468 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 | ||
| 469 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 | ||
| 470 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 | ||
| 471 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 | ||
| 472 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 | ||
| 473 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 | ||
| 474 | |||
| 475 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | ||
| 476 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 | ||
| 477 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 | ||
| 478 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 | ||
| 479 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 | ||
| 480 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 | ||
| 481 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 | ||
| 482 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 | ||
| 483 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 | ||
| 484 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 | ||
| 485 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 | ||
| 486 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 | ||
| 487 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 | ||
| 488 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 | ||
| 489 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 | ||
| 490 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 | ||
| 491 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 | ||
| 492 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 | ||
| 493 | |||
| 494 | /* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ | ||
| 495 | #define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 | ||
| 496 | #define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 | ||
| 497 | #define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 | ||
| 498 | #define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 | ||
| 499 | #define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 | ||
| 500 | |||
| 501 | /* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ | ||
| 502 | #define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 | ||
| 503 | #define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 | ||
| 504 | #define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 | ||
| 505 | #define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 | ||
| 506 | #define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 | ||
| 507 | |||
| 508 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 509 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 | ||
| 510 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 | ||
| 511 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 | ||
| 512 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 | ||
| 513 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 | ||
| 514 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 | ||
| 515 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 | ||
| 516 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 | ||
| 517 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 | ||
| 518 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 | ||
| 519 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 | ||
| 520 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 | ||
| 521 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 | ||
| 522 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 | ||
| 523 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 | ||
| 524 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 | ||
| 525 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 | ||
| 526 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 | ||
| 527 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 | ||
| 528 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 | ||
| 529 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 | ||
| 530 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 | ||
| 531 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 | ||
| 532 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 | ||
| 533 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 | ||
| 534 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 | ||
| 535 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 | ||
| 536 | |||
| 537 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 538 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 | ||
| 539 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 | ||
| 540 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 | ||
| 541 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 | ||
| 542 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 | ||
| 543 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 | ||
| 544 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 | ||
| 545 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 | ||
| 546 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 | ||
| 547 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 | ||
| 548 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 | ||
| 549 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 | ||
| 550 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 | ||
| 551 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 | ||
| 552 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 | ||
| 553 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 | ||
| 554 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 | ||
| 555 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 | ||
| 556 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 | ||
| 557 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 | ||
| 558 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 | ||
| 559 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 | ||
| 560 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 | ||
| 561 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 | ||
| 562 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 | ||
| 563 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 | ||
| 564 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 | ||
| 565 | |||
| 566 | /* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
| 567 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 | ||
| 568 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 | ||
| 569 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 | ||
| 570 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 | ||
| 571 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 | ||
| 572 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 | ||
| 573 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 | ||
| 574 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 | ||
| 575 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 | ||
| 576 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 | ||
| 577 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 | ||
| 578 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 | ||
| 579 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 | ||
| 580 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 | ||
| 581 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 | ||
| 582 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 | ||
| 583 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 | ||
| 584 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 | ||
| 585 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 | ||
| 586 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 | ||
| 587 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 | ||
| 588 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 | ||
| 589 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 | ||
| 590 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 | ||
| 591 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 | ||
| 592 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 | ||
| 593 | #define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 | ||
| 594 | |||
| 595 | /* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
| 596 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 | ||
| 597 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 | ||
| 598 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 | ||
| 599 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 | ||
| 600 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 | ||
| 601 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 | ||
| 602 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 | ||
| 603 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 | ||
| 604 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 | ||
| 605 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 | ||
| 606 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 | ||
| 607 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 | ||
| 608 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 | ||
| 609 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 | ||
| 610 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 | ||
| 611 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 | ||
| 612 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 | ||
| 613 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 | ||
| 614 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 | ||
| 615 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 | ||
| 616 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 | ||
| 617 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 | ||
| 618 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 | ||
| 619 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 | ||
| 620 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 | ||
| 621 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 | ||
| 622 | #define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 | ||
| 623 | |||
| 624 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | ||
| 625 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 | ||
| 626 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 | ||
| 627 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 | ||
| 628 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 | ||
| 629 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 | ||
| 630 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 | ||
| 631 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 | ||
| 632 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 | ||
| 633 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 | ||
| 634 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 | ||
| 635 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 | ||
| 636 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 | ||
| 637 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 | ||
| 638 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 | ||
| 639 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 | ||
| 640 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 | ||
| 641 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 | ||
| 642 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 | ||
| 643 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 | ||
| 644 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 | ||
| 645 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 | ||
| 646 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 | ||
| 647 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 | ||
| 648 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 | ||
| 649 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 | ||
| 650 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 | ||
| 651 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 | ||
| 652 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 | ||
| 653 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 | ||
| 654 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 | ||
| 655 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 | ||
| 656 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 | ||
| 657 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 | ||
| 658 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 | ||
| 659 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 | ||
| 660 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 | ||
| 661 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 | ||
| 662 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 | ||
| 663 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 | ||
| 664 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 | ||
| 665 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 | ||
| 666 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 | ||
| 667 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 | ||
| 668 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 | ||
| 669 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 | ||
| 670 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 | ||
| 671 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 | ||
| 672 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 | ||
| 673 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 | ||
| 674 | |||
| 675 | /* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 676 | #define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 | ||
| 677 | #define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 | ||
| 678 | #define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 | ||
| 679 | #define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 | ||
| 680 | #define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 | ||
| 681 | #define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 | ||
| 682 | #define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 | ||
| 683 | #define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 | ||
| 684 | #define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 | ||
| 685 | #define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 | ||
| 686 | #define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 | ||
| 687 | #define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 | ||
| 688 | #define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 | ||
| 689 | #define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 | ||
| 690 | #define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 | ||
| 691 | #define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 | ||
| 692 | #define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 | ||
| 693 | |||
| 694 | /* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 695 | #define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 | ||
| 696 | #define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 | ||
| 697 | #define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 | ||
| 698 | #define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 | ||
| 699 | #define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 | ||
| 700 | #define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 | ||
| 701 | #define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 | ||
| 702 | #define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 | ||
| 703 | #define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 | ||
| 704 | #define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 | ||
| 705 | #define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 | ||
| 706 | #define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 | ||
| 707 | #define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 | ||
| 708 | #define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 | ||
| 709 | #define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 | ||
| 710 | #define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 | ||
| 711 | #define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 | ||
| 712 | |||
| 713 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 714 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 | ||
| 715 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 | ||
| 716 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 | ||
| 717 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 | ||
| 718 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 | ||
| 719 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 | ||
| 720 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 | ||
| 721 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 | ||
| 722 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 | ||
| 723 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 | ||
| 724 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 | ||
| 725 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 | ||
| 726 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 | ||
| 727 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 | ||
| 728 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 | ||
| 729 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 | ||
| 730 | #define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 | ||
| 731 | |||
| 732 | |||
| 733 | /* Constants */ | ||
| 734 | #define regk_iop_sw_cfg_a 0x00000001 | ||
| 735 | #define regk_iop_sw_cfg_b 0x00000002 | ||
| 736 | #define regk_iop_sw_cfg_bus0 0x00000000 | ||
| 737 | #define regk_iop_sw_cfg_bus0_rot16 0x00000004 | ||
| 738 | #define regk_iop_sw_cfg_bus0_rot24 0x00000006 | ||
| 739 | #define regk_iop_sw_cfg_bus0_rot8 0x00000002 | ||
| 740 | #define regk_iop_sw_cfg_bus1 0x00000001 | ||
| 741 | #define regk_iop_sw_cfg_bus1_rot16 0x00000005 | ||
| 742 | #define regk_iop_sw_cfg_bus1_rot24 0x00000007 | ||
| 743 | #define regk_iop_sw_cfg_bus1_rot8 0x00000003 | ||
| 744 | #define regk_iop_sw_cfg_clk12 0x00000000 | ||
| 745 | #define regk_iop_sw_cfg_cpu 0x00000000 | ||
| 746 | #define regk_iop_sw_cfg_dmc0 0x00000000 | ||
| 747 | #define regk_iop_sw_cfg_dmc1 0x00000001 | ||
| 748 | #define regk_iop_sw_cfg_gated_clk0 0x00000010 | ||
| 749 | #define regk_iop_sw_cfg_gated_clk1 0x00000011 | ||
| 750 | #define regk_iop_sw_cfg_gated_clk2 0x00000012 | ||
| 751 | #define regk_iop_sw_cfg_gated_clk3 0x00000013 | ||
| 752 | #define regk_iop_sw_cfg_gio0 0x00000004 | ||
| 753 | #define regk_iop_sw_cfg_gio1 0x00000001 | ||
| 754 | #define regk_iop_sw_cfg_gio2 0x00000005 | ||
| 755 | #define regk_iop_sw_cfg_gio3 0x00000002 | ||
| 756 | #define regk_iop_sw_cfg_gio4 0x00000006 | ||
| 757 | #define regk_iop_sw_cfg_gio5 0x00000003 | ||
| 758 | #define regk_iop_sw_cfg_gio6 0x00000007 | ||
| 759 | #define regk_iop_sw_cfg_gio7 0x00000004 | ||
| 760 | #define regk_iop_sw_cfg_gio_in0 0x00000000 | ||
| 761 | #define regk_iop_sw_cfg_gio_in1 0x00000001 | ||
| 762 | #define regk_iop_sw_cfg_gio_in10 0x00000002 | ||
| 763 | #define regk_iop_sw_cfg_gio_in11 0x00000003 | ||
| 764 | #define regk_iop_sw_cfg_gio_in14 0x00000004 | ||
| 765 | #define regk_iop_sw_cfg_gio_in15 0x00000005 | ||
| 766 | #define regk_iop_sw_cfg_gio_in18 0x00000002 | ||
| 767 | #define regk_iop_sw_cfg_gio_in19 0x00000003 | ||
| 768 | #define regk_iop_sw_cfg_gio_in20 0x00000004 | ||
| 769 | #define regk_iop_sw_cfg_gio_in21 0x00000005 | ||
| 770 | #define regk_iop_sw_cfg_gio_in26 0x00000006 | ||
| 771 | #define regk_iop_sw_cfg_gio_in27 0x00000007 | ||
| 772 | #define regk_iop_sw_cfg_gio_in28 0x00000006 | ||
| 773 | #define regk_iop_sw_cfg_gio_in29 0x00000007 | ||
| 774 | #define regk_iop_sw_cfg_gio_in4 0x00000000 | ||
| 775 | #define regk_iop_sw_cfg_gio_in5 0x00000001 | ||
| 776 | #define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 | ||
| 777 | #define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 | ||
| 778 | #define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 | ||
| 779 | #define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 | ||
| 780 | #define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 | ||
| 781 | #define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 | ||
| 782 | #define regk_iop_sw_cfg_mpu 0x00000001 | ||
| 783 | #define regk_iop_sw_cfg_none 0x00000000 | ||
| 784 | #define regk_iop_sw_cfg_par0 0x00000000 | ||
| 785 | #define regk_iop_sw_cfg_par1 0x00000001 | ||
| 786 | #define regk_iop_sw_cfg_pdp_out0 0x00000002 | ||
| 787 | #define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 | ||
| 788 | #define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 | ||
| 789 | #define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 | ||
| 790 | #define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 | ||
| 791 | #define regk_iop_sw_cfg_pdp_out1 0x00000003 | ||
| 792 | #define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 | ||
| 793 | #define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 | ||
| 794 | #define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 | ||
| 795 | #define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 | ||
| 796 | #define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 | ||
| 797 | #define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 | ||
| 798 | #define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 | ||
| 799 | #define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 | ||
| 800 | #define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 | ||
| 801 | #define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 | ||
| 802 | #define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 | ||
| 803 | #define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 | ||
| 804 | #define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 | ||
| 805 | #define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 | ||
| 806 | #define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 | ||
| 807 | #define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 | ||
| 808 | #define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 | ||
| 809 | #define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 | ||
| 810 | #define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 | ||
| 811 | #define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 | ||
| 812 | #define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 | ||
| 813 | #define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 | ||
| 814 | #define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 | ||
| 815 | #define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 | ||
| 816 | #define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 | ||
| 817 | #define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 | ||
| 818 | #define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 | ||
| 819 | #define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 | ||
| 820 | #define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 | ||
| 821 | #define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 | ||
| 822 | #define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 | ||
| 823 | #define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 | ||
| 824 | #define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 | ||
| 825 | #define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 | ||
| 826 | #define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 | ||
| 827 | #define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 | ||
| 828 | #define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 | ||
| 829 | #define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 | ||
| 830 | #define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 | ||
| 831 | #define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 | ||
| 832 | #define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 | ||
| 833 | #define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 | ||
| 834 | #define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 | ||
| 835 | #define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 | ||
| 836 | #define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 | ||
| 837 | #define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 | ||
| 838 | #define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 | ||
| 839 | #define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 | ||
| 840 | #define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 | ||
| 841 | #define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 | ||
| 842 | #define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 | ||
| 843 | #define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 | ||
| 844 | #define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 | ||
| 845 | #define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 | ||
| 846 | #define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 | ||
| 847 | #define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 | ||
| 848 | #define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 | ||
| 849 | #define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 | ||
| 850 | #define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 | ||
| 851 | #define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 | ||
| 852 | #define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 | ||
| 853 | #define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 | ||
| 854 | #define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 | ||
| 855 | #define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 | ||
| 856 | #define regk_iop_sw_cfg_sdp_out0 0x00000008 | ||
| 857 | #define regk_iop_sw_cfg_sdp_out1 0x00000009 | ||
| 858 | #define regk_iop_sw_cfg_size16 0x00000002 | ||
| 859 | #define regk_iop_sw_cfg_size24 0x00000003 | ||
| 860 | #define regk_iop_sw_cfg_size32 0x00000004 | ||
| 861 | #define regk_iop_sw_cfg_size8 0x00000001 | ||
| 862 | #define regk_iop_sw_cfg_spu0 0x00000002 | ||
| 863 | #define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 | ||
| 864 | #define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 | ||
| 865 | #define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 | ||
| 866 | #define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 | ||
| 867 | #define regk_iop_sw_cfg_spu0_g0 0x0000000e | ||
| 868 | #define regk_iop_sw_cfg_spu0_g1 0x0000000e | ||
| 869 | #define regk_iop_sw_cfg_spu0_g2 0x0000000e | ||
| 870 | #define regk_iop_sw_cfg_spu0_g3 0x0000000e | ||
| 871 | #define regk_iop_sw_cfg_spu0_g4 0x0000000e | ||
| 872 | #define regk_iop_sw_cfg_spu0_g5 0x0000000e | ||
| 873 | #define regk_iop_sw_cfg_spu0_g6 0x0000000e | ||
| 874 | #define regk_iop_sw_cfg_spu0_g7 0x0000000e | ||
| 875 | #define regk_iop_sw_cfg_spu0_gio0 0x00000000 | ||
| 876 | #define regk_iop_sw_cfg_spu0_gio1 0x00000001 | ||
| 877 | #define regk_iop_sw_cfg_spu0_gio2 0x00000000 | ||
| 878 | #define regk_iop_sw_cfg_spu0_gio5 0x00000005 | ||
| 879 | #define regk_iop_sw_cfg_spu0_gio6 0x00000006 | ||
| 880 | #define regk_iop_sw_cfg_spu0_gio7 0x00000007 | ||
| 881 | #define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 | ||
| 882 | #define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 | ||
| 883 | #define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a | ||
| 884 | #define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b | ||
| 885 | #define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c | ||
| 886 | #define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d | ||
| 887 | #define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e | ||
| 888 | #define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f | ||
| 889 | #define regk_iop_sw_cfg_spu0_gioout0 0x00000000 | ||
| 890 | #define regk_iop_sw_cfg_spu0_gioout1 0x00000000 | ||
| 891 | #define regk_iop_sw_cfg_spu0_gioout10 0x0000000e | ||
| 892 | #define regk_iop_sw_cfg_spu0_gioout11 0x0000000e | ||
| 893 | #define regk_iop_sw_cfg_spu0_gioout12 0x0000000e | ||
| 894 | #define regk_iop_sw_cfg_spu0_gioout13 0x0000000e | ||
| 895 | #define regk_iop_sw_cfg_spu0_gioout14 0x0000000e | ||
| 896 | #define regk_iop_sw_cfg_spu0_gioout15 0x0000000e | ||
| 897 | #define regk_iop_sw_cfg_spu0_gioout16 0x0000000e | ||
| 898 | #define regk_iop_sw_cfg_spu0_gioout17 0x0000000e | ||
| 899 | #define regk_iop_sw_cfg_spu0_gioout18 0x0000000e | ||
| 900 | #define regk_iop_sw_cfg_spu0_gioout19 0x0000000e | ||
| 901 | #define regk_iop_sw_cfg_spu0_gioout2 0x00000002 | ||
| 902 | #define regk_iop_sw_cfg_spu0_gioout20 0x0000000e | ||
| 903 | #define regk_iop_sw_cfg_spu0_gioout21 0x0000000e | ||
| 904 | #define regk_iop_sw_cfg_spu0_gioout22 0x0000000e | ||
| 905 | #define regk_iop_sw_cfg_spu0_gioout23 0x0000000e | ||
| 906 | #define regk_iop_sw_cfg_spu0_gioout24 0x0000000e | ||
| 907 | #define regk_iop_sw_cfg_spu0_gioout25 0x0000000e | ||
| 908 | #define regk_iop_sw_cfg_spu0_gioout26 0x0000000e | ||
| 909 | #define regk_iop_sw_cfg_spu0_gioout27 0x0000000e | ||
| 910 | #define regk_iop_sw_cfg_spu0_gioout28 0x0000000e | ||
| 911 | #define regk_iop_sw_cfg_spu0_gioout29 0x0000000e | ||
| 912 | #define regk_iop_sw_cfg_spu0_gioout3 0x00000002 | ||
| 913 | #define regk_iop_sw_cfg_spu0_gioout30 0x0000000e | ||
| 914 | #define regk_iop_sw_cfg_spu0_gioout31 0x0000000e | ||
| 915 | #define regk_iop_sw_cfg_spu0_gioout4 0x00000004 | ||
| 916 | #define regk_iop_sw_cfg_spu0_gioout5 0x00000004 | ||
| 917 | #define regk_iop_sw_cfg_spu0_gioout6 0x00000006 | ||
| 918 | #define regk_iop_sw_cfg_spu0_gioout7 0x00000006 | ||
| 919 | #define regk_iop_sw_cfg_spu0_gioout8 0x0000000e | ||
| 920 | #define regk_iop_sw_cfg_spu0_gioout9 0x0000000e | ||
| 921 | #define regk_iop_sw_cfg_spu1 0x00000003 | ||
| 922 | #define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 | ||
| 923 | #define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 | ||
| 924 | #define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 | ||
| 925 | #define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 | ||
| 926 | #define regk_iop_sw_cfg_spu1_g0 0x0000000f | ||
| 927 | #define regk_iop_sw_cfg_spu1_g1 0x0000000f | ||
| 928 | #define regk_iop_sw_cfg_spu1_g2 0x0000000f | ||
| 929 | #define regk_iop_sw_cfg_spu1_g3 0x0000000f | ||
| 930 | #define regk_iop_sw_cfg_spu1_g4 0x0000000f | ||
| 931 | #define regk_iop_sw_cfg_spu1_g5 0x0000000f | ||
| 932 | #define regk_iop_sw_cfg_spu1_g6 0x0000000f | ||
| 933 | #define regk_iop_sw_cfg_spu1_g7 0x0000000f | ||
| 934 | #define regk_iop_sw_cfg_spu1_gio0 0x00000002 | ||
| 935 | #define regk_iop_sw_cfg_spu1_gio1 0x00000003 | ||
| 936 | #define regk_iop_sw_cfg_spu1_gio2 0x00000002 | ||
| 937 | #define regk_iop_sw_cfg_spu1_gio5 0x00000005 | ||
| 938 | #define regk_iop_sw_cfg_spu1_gio6 0x00000006 | ||
| 939 | #define regk_iop_sw_cfg_spu1_gio7 0x00000007 | ||
| 940 | #define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 | ||
| 941 | #define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 | ||
| 942 | #define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a | ||
| 943 | #define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b | ||
| 944 | #define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c | ||
| 945 | #define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d | ||
| 946 | #define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e | ||
| 947 | #define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f | ||
| 948 | #define regk_iop_sw_cfg_spu1_gioout0 0x00000001 | ||
| 949 | #define regk_iop_sw_cfg_spu1_gioout1 0x00000001 | ||
| 950 | #define regk_iop_sw_cfg_spu1_gioout10 0x0000000f | ||
| 951 | #define regk_iop_sw_cfg_spu1_gioout11 0x0000000f | ||
| 952 | #define regk_iop_sw_cfg_spu1_gioout12 0x0000000f | ||
| 953 | #define regk_iop_sw_cfg_spu1_gioout13 0x0000000f | ||
| 954 | #define regk_iop_sw_cfg_spu1_gioout14 0x0000000f | ||
| 955 | #define regk_iop_sw_cfg_spu1_gioout15 0x0000000f | ||
| 956 | #define regk_iop_sw_cfg_spu1_gioout16 0x0000000f | ||
| 957 | #define regk_iop_sw_cfg_spu1_gioout17 0x0000000f | ||
| 958 | #define regk_iop_sw_cfg_spu1_gioout18 0x0000000f | ||
| 959 | #define regk_iop_sw_cfg_spu1_gioout19 0x0000000f | ||
| 960 | #define regk_iop_sw_cfg_spu1_gioout2 0x00000003 | ||
| 961 | #define regk_iop_sw_cfg_spu1_gioout20 0x0000000f | ||
| 962 | #define regk_iop_sw_cfg_spu1_gioout21 0x0000000f | ||
| 963 | #define regk_iop_sw_cfg_spu1_gioout22 0x0000000f | ||
| 964 | #define regk_iop_sw_cfg_spu1_gioout23 0x0000000f | ||
| 965 | #define regk_iop_sw_cfg_spu1_gioout24 0x0000000f | ||
| 966 | #define regk_iop_sw_cfg_spu1_gioout25 0x0000000f | ||
| 967 | #define regk_iop_sw_cfg_spu1_gioout26 0x0000000f | ||
| 968 | #define regk_iop_sw_cfg_spu1_gioout27 0x0000000f | ||
| 969 | #define regk_iop_sw_cfg_spu1_gioout28 0x0000000f | ||
| 970 | #define regk_iop_sw_cfg_spu1_gioout29 0x0000000f | ||
| 971 | #define regk_iop_sw_cfg_spu1_gioout3 0x00000003 | ||
| 972 | #define regk_iop_sw_cfg_spu1_gioout30 0x0000000f | ||
| 973 | #define regk_iop_sw_cfg_spu1_gioout31 0x0000000f | ||
| 974 | #define regk_iop_sw_cfg_spu1_gioout4 0x00000005 | ||
| 975 | #define regk_iop_sw_cfg_spu1_gioout5 0x00000005 | ||
| 976 | #define regk_iop_sw_cfg_spu1_gioout6 0x00000007 | ||
| 977 | #define regk_iop_sw_cfg_spu1_gioout7 0x00000007 | ||
| 978 | #define regk_iop_sw_cfg_spu1_gioout8 0x0000000f | ||
| 979 | #define regk_iop_sw_cfg_spu1_gioout9 0x0000000f | ||
| 980 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 | ||
| 981 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 | ||
| 982 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 | ||
| 983 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 | ||
| 984 | #define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 | ||
| 985 | #define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 | ||
| 986 | #define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 | ||
| 987 | #define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 | ||
| 988 | #define regk_iop_sw_cfg_timer_grp0 0x00000000 | ||
| 989 | #define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 | ||
| 990 | #define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a | ||
| 991 | #define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a | ||
| 992 | #define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a | ||
| 993 | #define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a | ||
| 994 | #define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 | ||
| 995 | #define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 | ||
| 996 | #define regk_iop_sw_cfg_timer_grp1 0x00000000 | ||
| 997 | #define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 | ||
| 998 | #define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b | ||
| 999 | #define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b | ||
| 1000 | #define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b | ||
| 1001 | #define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b | ||
| 1002 | #define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 | ||
| 1003 | #define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 | ||
| 1004 | #define regk_iop_sw_cfg_timer_grp2 0x00000000 | ||
| 1005 | #define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 | ||
| 1006 | #define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c | ||
| 1007 | #define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c | ||
| 1008 | #define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c | ||
| 1009 | #define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c | ||
| 1010 | #define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 | ||
| 1011 | #define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 | ||
| 1012 | #define regk_iop_sw_cfg_timer_grp3 0x00000000 | ||
| 1013 | #define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 | ||
| 1014 | #define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d | ||
| 1015 | #define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d | ||
| 1016 | #define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d | ||
| 1017 | #define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d | ||
| 1018 | #define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 | ||
| 1019 | #define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 | ||
| 1020 | #define regk_iop_sw_cfg_trig0_0 0x00000000 | ||
| 1021 | #define regk_iop_sw_cfg_trig0_1 0x00000000 | ||
| 1022 | #define regk_iop_sw_cfg_trig0_2 0x00000000 | ||
| 1023 | #define regk_iop_sw_cfg_trig0_3 0x00000000 | ||
| 1024 | #define regk_iop_sw_cfg_trig1_0 0x00000000 | ||
| 1025 | #define regk_iop_sw_cfg_trig1_1 0x00000000 | ||
| 1026 | #define regk_iop_sw_cfg_trig1_2 0x00000000 | ||
| 1027 | #define regk_iop_sw_cfg_trig1_3 0x00000000 | ||
| 1028 | #define regk_iop_sw_cfg_trig2_0 0x00000000 | ||
| 1029 | #define regk_iop_sw_cfg_trig2_1 0x00000000 | ||
| 1030 | #define regk_iop_sw_cfg_trig2_2 0x00000000 | ||
| 1031 | #define regk_iop_sw_cfg_trig2_3 0x00000000 | ||
| 1032 | #define regk_iop_sw_cfg_trig3_0 0x00000000 | ||
| 1033 | #define regk_iop_sw_cfg_trig3_1 0x00000000 | ||
| 1034 | #define regk_iop_sw_cfg_trig3_2 0x00000000 | ||
| 1035 | #define regk_iop_sw_cfg_trig3_3 0x00000000 | ||
| 1036 | #define regk_iop_sw_cfg_trig4_0 0x00000001 | ||
| 1037 | #define regk_iop_sw_cfg_trig4_1 0x00000001 | ||
| 1038 | #define regk_iop_sw_cfg_trig4_2 0x00000001 | ||
| 1039 | #define regk_iop_sw_cfg_trig4_3 0x00000001 | ||
| 1040 | #define regk_iop_sw_cfg_trig5_0 0x00000001 | ||
| 1041 | #define regk_iop_sw_cfg_trig5_1 0x00000001 | ||
| 1042 | #define regk_iop_sw_cfg_trig5_2 0x00000001 | ||
| 1043 | #define regk_iop_sw_cfg_trig5_3 0x00000001 | ||
| 1044 | #define regk_iop_sw_cfg_trig6_0 0x00000001 | ||
| 1045 | #define regk_iop_sw_cfg_trig6_1 0x00000001 | ||
| 1046 | #define regk_iop_sw_cfg_trig6_2 0x00000001 | ||
| 1047 | #define regk_iop_sw_cfg_trig6_3 0x00000001 | ||
| 1048 | #define regk_iop_sw_cfg_trig7_0 0x00000001 | ||
| 1049 | #define regk_iop_sw_cfg_trig7_1 0x00000001 | ||
| 1050 | #define regk_iop_sw_cfg_trig7_2 0x00000001 | ||
| 1051 | #define regk_iop_sw_cfg_trig7_3 0x00000001 | ||
| 1052 | #endif /* __iop_sw_cfg_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index db347bcba025..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null | |||
| @@ -1,1758 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_cpu_defs_asm_h | ||
| 2 | #define __iop_sw_cpu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:19 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r | ||
| 11 | * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | ||
| 57 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 58 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 | ||
| 59 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 60 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 | ||
| 61 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 | ||
| 62 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 | ||
| 63 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 | ||
| 64 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 | ||
| 65 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 | ||
| 66 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 | ||
| 67 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 | ||
| 68 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 | ||
| 69 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 | ||
| 70 | #define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 | ||
| 71 | |||
| 72 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | ||
| 73 | #define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 | ||
| 74 | #define reg_iop_sw_cpu_rw_mc_data___val___width 32 | ||
| 75 | #define reg_iop_sw_cpu_rw_mc_data_offset 4 | ||
| 76 | |||
| 77 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | ||
| 78 | #define reg_iop_sw_cpu_rw_mc_addr_offset 8 | ||
| 79 | |||
| 80 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | ||
| 81 | #define reg_iop_sw_cpu_rs_mc_data_offset 12 | ||
| 82 | |||
| 83 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | ||
| 84 | #define reg_iop_sw_cpu_r_mc_data_offset 16 | ||
| 85 | |||
| 86 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | ||
| 87 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 | ||
| 88 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 | ||
| 89 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 | ||
| 90 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 | ||
| 91 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 | ||
| 92 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 | ||
| 93 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 | ||
| 94 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 | ||
| 95 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 | ||
| 96 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 | ||
| 97 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 | ||
| 98 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 | ||
| 99 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 | ||
| 100 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 | ||
| 101 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 | ||
| 102 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 | ||
| 103 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 | ||
| 104 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 | ||
| 105 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 | ||
| 106 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 | ||
| 107 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 | ||
| 108 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 | ||
| 109 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 | ||
| 110 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 | ||
| 111 | #define reg_iop_sw_cpu_r_mc_stat_offset 20 | ||
| 112 | |||
| 113 | /* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 114 | #define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 | ||
| 115 | #define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 | ||
| 116 | #define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 | ||
| 117 | #define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 | ||
| 118 | #define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 | ||
| 119 | #define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 | ||
| 120 | #define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 | ||
| 121 | #define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 | ||
| 122 | #define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 | ||
| 123 | |||
| 124 | /* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ | ||
| 125 | #define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 | ||
| 126 | #define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 | ||
| 127 | #define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 | ||
| 128 | #define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 | ||
| 129 | #define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 | ||
| 130 | #define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 | ||
| 131 | #define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 | ||
| 132 | #define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 | ||
| 133 | #define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 | ||
| 134 | |||
| 135 | /* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 136 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 | ||
| 137 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 | ||
| 138 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 | ||
| 139 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 | ||
| 140 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 | ||
| 141 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 | ||
| 142 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 | ||
| 143 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 | ||
| 144 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 | ||
| 145 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 | ||
| 146 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 | ||
| 147 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 | ||
| 148 | #define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 | ||
| 149 | |||
| 150 | /* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 151 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 | ||
| 152 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 | ||
| 153 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 | ||
| 154 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 | ||
| 155 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 | ||
| 156 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 | ||
| 157 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 | ||
| 158 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 | ||
| 159 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 | ||
| 160 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 | ||
| 161 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 | ||
| 162 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 | ||
| 163 | #define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 | ||
| 164 | |||
| 165 | /* Register r_bus0_in, scope iop_sw_cpu, type r */ | ||
| 166 | #define reg_iop_sw_cpu_r_bus0_in_offset 40 | ||
| 167 | |||
| 168 | /* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 169 | #define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 | ||
| 170 | #define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 | ||
| 171 | #define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 | ||
| 172 | #define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 | ||
| 173 | #define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 | ||
| 174 | #define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 | ||
| 175 | #define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 | ||
| 176 | #define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 | ||
| 177 | #define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 | ||
| 178 | |||
| 179 | /* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ | ||
| 180 | #define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 | ||
| 181 | #define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 | ||
| 182 | #define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 | ||
| 183 | #define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 | ||
| 184 | #define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 | ||
| 185 | #define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 | ||
| 186 | #define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 | ||
| 187 | #define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 | ||
| 188 | #define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 | ||
| 189 | |||
| 190 | /* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 191 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 | ||
| 192 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 | ||
| 193 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 | ||
| 194 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 | ||
| 195 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 | ||
| 196 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 | ||
| 197 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 | ||
| 198 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 | ||
| 199 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 | ||
| 200 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 | ||
| 201 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 | ||
| 202 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 | ||
| 203 | #define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 | ||
| 204 | |||
| 205 | /* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 206 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 | ||
| 207 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 | ||
| 208 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 | ||
| 209 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 | ||
| 210 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 | ||
| 211 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 | ||
| 212 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 | ||
| 213 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 | ||
| 214 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 | ||
| 215 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 | ||
| 216 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 | ||
| 217 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 | ||
| 218 | #define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 | ||
| 219 | |||
| 220 | /* Register r_bus1_in, scope iop_sw_cpu, type r */ | ||
| 221 | #define reg_iop_sw_cpu_r_bus1_in_offset 60 | ||
| 222 | |||
| 223 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 224 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 | ||
| 225 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 | ||
| 226 | #define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 | ||
| 227 | |||
| 228 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | ||
| 229 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 | ||
| 230 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 | ||
| 231 | #define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 | ||
| 232 | |||
| 233 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 234 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 235 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 | ||
| 236 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 | ||
| 237 | |||
| 238 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 239 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 240 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 | ||
| 241 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 | ||
| 242 | |||
| 243 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | ||
| 244 | #define reg_iop_sw_cpu_r_gio_in_offset 80 | ||
| 245 | |||
| 246 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | ||
| 247 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 | ||
| 248 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 | ||
| 249 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 | ||
| 250 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 | ||
| 251 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 | ||
| 252 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 | ||
| 253 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 | ||
| 254 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 | ||
| 255 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 | ||
| 256 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 | ||
| 257 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 | ||
| 258 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 | ||
| 259 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 | ||
| 260 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 | ||
| 261 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 | ||
| 262 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 | ||
| 263 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 | ||
| 264 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 | ||
| 265 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 | ||
| 266 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 | ||
| 267 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 | ||
| 268 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 | ||
| 269 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 | ||
| 270 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 | ||
| 271 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 | ||
| 272 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 | ||
| 273 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 | ||
| 274 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 | ||
| 275 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 | ||
| 276 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 | ||
| 277 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 | ||
| 278 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 | ||
| 279 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 | ||
| 280 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 | ||
| 281 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 | ||
| 282 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 | ||
| 283 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 | ||
| 284 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 | ||
| 285 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 | ||
| 286 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 | ||
| 287 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 | ||
| 288 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 | ||
| 289 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 | ||
| 290 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 | ||
| 291 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 | ||
| 292 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 | ||
| 293 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 | ||
| 294 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 | ||
| 295 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 | ||
| 296 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 | ||
| 297 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 | ||
| 298 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 | ||
| 299 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 | ||
| 300 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 | ||
| 301 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 | ||
| 302 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 | ||
| 303 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 | ||
| 304 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 | ||
| 305 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 | ||
| 306 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 | ||
| 307 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 | ||
| 308 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 | ||
| 309 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 | ||
| 310 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 | ||
| 311 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 | ||
| 312 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 | ||
| 313 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 | ||
| 314 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 | ||
| 315 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 | ||
| 316 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 | ||
| 317 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 | ||
| 318 | #define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 | ||
| 319 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 | ||
| 320 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 | ||
| 321 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 | ||
| 322 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 | ||
| 323 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 | ||
| 324 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 | ||
| 325 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 | ||
| 326 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 | ||
| 327 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 | ||
| 328 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 | ||
| 329 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 | ||
| 330 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 | ||
| 331 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 | ||
| 332 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 | ||
| 333 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 | ||
| 334 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 | ||
| 335 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 | ||
| 336 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 | ||
| 337 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 | ||
| 338 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 | ||
| 339 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 | ||
| 340 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 | ||
| 341 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 | ||
| 342 | #define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 | ||
| 343 | #define reg_iop_sw_cpu_rw_intr0_mask_offset 84 | ||
| 344 | |||
| 345 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | ||
| 346 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 | ||
| 347 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 | ||
| 348 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 | ||
| 349 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 | ||
| 350 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 | ||
| 351 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 | ||
| 352 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 | ||
| 353 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 | ||
| 354 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 | ||
| 355 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 | ||
| 356 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 | ||
| 357 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 | ||
| 358 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 | ||
| 359 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 | ||
| 360 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 | ||
| 361 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 | ||
| 362 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 | ||
| 363 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 | ||
| 364 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 | ||
| 365 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 | ||
| 366 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 | ||
| 367 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 | ||
| 368 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 | ||
| 369 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 | ||
| 370 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 | ||
| 371 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 | ||
| 372 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 | ||
| 373 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 | ||
| 374 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 | ||
| 375 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 | ||
| 376 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 | ||
| 377 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 | ||
| 378 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 | ||
| 379 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 | ||
| 380 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 | ||
| 381 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 | ||
| 382 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 | ||
| 383 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 | ||
| 384 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 | ||
| 385 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 | ||
| 386 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 | ||
| 387 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 | ||
| 388 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 | ||
| 389 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 | ||
| 390 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 | ||
| 391 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 | ||
| 392 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 | ||
| 393 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 | ||
| 394 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 | ||
| 395 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 | ||
| 396 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 | ||
| 397 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 | ||
| 398 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 | ||
| 399 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 | ||
| 400 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 | ||
| 401 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 | ||
| 402 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 | ||
| 403 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 | ||
| 404 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 | ||
| 405 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 | ||
| 406 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 | ||
| 407 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 | ||
| 408 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 | ||
| 409 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 | ||
| 410 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 | ||
| 411 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 | ||
| 412 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 | ||
| 413 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 | ||
| 414 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 | ||
| 415 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 | ||
| 416 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 | ||
| 417 | #define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 | ||
| 418 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 | ||
| 419 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 | ||
| 420 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 | ||
| 421 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 | ||
| 422 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 | ||
| 423 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 | ||
| 424 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 | ||
| 425 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 | ||
| 426 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 | ||
| 427 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 | ||
| 428 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 | ||
| 429 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 | ||
| 430 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 | ||
| 431 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 | ||
| 432 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 | ||
| 433 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 | ||
| 434 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 | ||
| 435 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 | ||
| 436 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 | ||
| 437 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 | ||
| 438 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 | ||
| 439 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 | ||
| 440 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 | ||
| 441 | #define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 | ||
| 442 | #define reg_iop_sw_cpu_rw_ack_intr0_offset 88 | ||
| 443 | |||
| 444 | /* Register r_intr0, scope iop_sw_cpu, type r */ | ||
| 445 | #define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 | ||
| 446 | #define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 | ||
| 447 | #define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 | ||
| 448 | #define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 | ||
| 449 | #define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 | ||
| 450 | #define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 | ||
| 451 | #define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 | ||
| 452 | #define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 | ||
| 453 | #define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 | ||
| 454 | #define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 | ||
| 455 | #define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 | ||
| 456 | #define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 | ||
| 457 | #define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 | ||
| 458 | #define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 | ||
| 459 | #define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 | ||
| 460 | #define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 | ||
| 461 | #define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 | ||
| 462 | #define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 | ||
| 463 | #define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 | ||
| 464 | #define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 | ||
| 465 | #define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 | ||
| 466 | #define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 | ||
| 467 | #define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 | ||
| 468 | #define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 | ||
| 469 | #define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 | ||
| 470 | #define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 | ||
| 471 | #define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 | ||
| 472 | #define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 | ||
| 473 | #define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 | ||
| 474 | #define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 | ||
| 475 | #define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 | ||
| 476 | #define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 | ||
| 477 | #define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 | ||
| 478 | #define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 | ||
| 479 | #define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 | ||
| 480 | #define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 | ||
| 481 | #define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 | ||
| 482 | #define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 | ||
| 483 | #define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 | ||
| 484 | #define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 | ||
| 485 | #define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 | ||
| 486 | #define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 | ||
| 487 | #define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 | ||
| 488 | #define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 | ||
| 489 | #define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 | ||
| 490 | #define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 | ||
| 491 | #define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 | ||
| 492 | #define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 | ||
| 493 | #define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 | ||
| 494 | #define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 | ||
| 495 | #define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 | ||
| 496 | #define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 | ||
| 497 | #define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 | ||
| 498 | #define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 | ||
| 499 | #define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 | ||
| 500 | #define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 | ||
| 501 | #define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 | ||
| 502 | #define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 | ||
| 503 | #define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 | ||
| 504 | #define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 | ||
| 505 | #define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 | ||
| 506 | #define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 | ||
| 507 | #define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 | ||
| 508 | #define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 | ||
| 509 | #define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 | ||
| 510 | #define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 | ||
| 511 | #define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 | ||
| 512 | #define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 | ||
| 513 | #define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 | ||
| 514 | #define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 | ||
| 515 | #define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 | ||
| 516 | #define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 | ||
| 517 | #define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 | ||
| 518 | #define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 | ||
| 519 | #define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 | ||
| 520 | #define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 | ||
| 521 | #define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 | ||
| 522 | #define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 | ||
| 523 | #define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 | ||
| 524 | #define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 | ||
| 525 | #define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 | ||
| 526 | #define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 | ||
| 527 | #define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 | ||
| 528 | #define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 | ||
| 529 | #define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 | ||
| 530 | #define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 | ||
| 531 | #define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 | ||
| 532 | #define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 | ||
| 533 | #define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 | ||
| 534 | #define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 | ||
| 535 | #define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 | ||
| 536 | #define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 | ||
| 537 | #define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 | ||
| 538 | #define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 | ||
| 539 | #define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 | ||
| 540 | #define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 | ||
| 541 | #define reg_iop_sw_cpu_r_intr0_offset 92 | ||
| 542 | |||
| 543 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | ||
| 544 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 | ||
| 545 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 | ||
| 546 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 | ||
| 547 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 | ||
| 548 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 | ||
| 549 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 | ||
| 550 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 | ||
| 551 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 | ||
| 552 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 | ||
| 553 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 | ||
| 554 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 | ||
| 555 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 | ||
| 556 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 | ||
| 557 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 | ||
| 558 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 | ||
| 559 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 | ||
| 560 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 | ||
| 561 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 | ||
| 562 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 | ||
| 563 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 | ||
| 564 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 | ||
| 565 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 | ||
| 566 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 | ||
| 567 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 | ||
| 568 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 | ||
| 569 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 | ||
| 570 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 | ||
| 571 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 | ||
| 572 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 | ||
| 573 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 | ||
| 574 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 | ||
| 575 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 | ||
| 576 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 | ||
| 577 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 | ||
| 578 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 | ||
| 579 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 | ||
| 580 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 | ||
| 581 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 | ||
| 582 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 | ||
| 583 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 | ||
| 584 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 | ||
| 585 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 | ||
| 586 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 | ||
| 587 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 | ||
| 588 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 | ||
| 589 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 | ||
| 590 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 | ||
| 591 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 | ||
| 592 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 | ||
| 593 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 | ||
| 594 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 | ||
| 595 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 | ||
| 596 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 | ||
| 597 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 | ||
| 598 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 | ||
| 599 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 | ||
| 600 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 | ||
| 601 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 | ||
| 602 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 | ||
| 603 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 | ||
| 604 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 | ||
| 605 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 | ||
| 606 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 | ||
| 607 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 | ||
| 608 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 | ||
| 609 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 | ||
| 610 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 | ||
| 611 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 | ||
| 612 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 | ||
| 613 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 | ||
| 614 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 | ||
| 615 | #define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 | ||
| 616 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 | ||
| 617 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 | ||
| 618 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 | ||
| 619 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 | ||
| 620 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 | ||
| 621 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 | ||
| 622 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 | ||
| 623 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 | ||
| 624 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 | ||
| 625 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 | ||
| 626 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 | ||
| 627 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 | ||
| 628 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 | ||
| 629 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 | ||
| 630 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 | ||
| 631 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 | ||
| 632 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 | ||
| 633 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 | ||
| 634 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 | ||
| 635 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 | ||
| 636 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 | ||
| 637 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 | ||
| 638 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 | ||
| 639 | #define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 | ||
| 640 | #define reg_iop_sw_cpu_r_masked_intr0_offset 96 | ||
| 641 | |||
| 642 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | ||
| 643 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 | ||
| 644 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 | ||
| 645 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 | ||
| 646 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 | ||
| 647 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 | ||
| 648 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 | ||
| 649 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 | ||
| 650 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 | ||
| 651 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 | ||
| 652 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 | ||
| 653 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 | ||
| 654 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 | ||
| 655 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 | ||
| 656 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 | ||
| 657 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 | ||
| 658 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 | ||
| 659 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 | ||
| 660 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 | ||
| 661 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 | ||
| 662 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 | ||
| 663 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 | ||
| 664 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 | ||
| 665 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 | ||
| 666 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 | ||
| 667 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 | ||
| 668 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 | ||
| 669 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 | ||
| 670 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 | ||
| 671 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 | ||
| 672 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 | ||
| 673 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 | ||
| 674 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 | ||
| 675 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 | ||
| 676 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 | ||
| 677 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 | ||
| 678 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 | ||
| 679 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 | ||
| 680 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 | ||
| 681 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 | ||
| 682 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 | ||
| 683 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 | ||
| 684 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 | ||
| 685 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 | ||
| 686 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 | ||
| 687 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 | ||
| 688 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 | ||
| 689 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 | ||
| 690 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 | ||
| 691 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 | ||
| 692 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 | ||
| 693 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 | ||
| 694 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 | ||
| 695 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 | ||
| 696 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 | ||
| 697 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 | ||
| 698 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 | ||
| 699 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 | ||
| 700 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 | ||
| 701 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 | ||
| 702 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 | ||
| 703 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 | ||
| 704 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 | ||
| 705 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 | ||
| 706 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 | ||
| 707 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 | ||
| 708 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 | ||
| 709 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 | ||
| 710 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 | ||
| 711 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 | ||
| 712 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 | ||
| 713 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 | ||
| 714 | #define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 | ||
| 715 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 | ||
| 716 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 | ||
| 717 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 | ||
| 718 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 | ||
| 719 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 | ||
| 720 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 | ||
| 721 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 | ||
| 722 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 | ||
| 723 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 | ||
| 724 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 | ||
| 725 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 | ||
| 726 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 | ||
| 727 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 | ||
| 728 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 | ||
| 729 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 | ||
| 730 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 | ||
| 731 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 | ||
| 732 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 | ||
| 733 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 | ||
| 734 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 | ||
| 735 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 | ||
| 736 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 | ||
| 737 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 | ||
| 738 | #define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 | ||
| 739 | #define reg_iop_sw_cpu_rw_intr1_mask_offset 100 | ||
| 740 | |||
| 741 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | ||
| 742 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 | ||
| 743 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 | ||
| 744 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 | ||
| 745 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 | ||
| 746 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 | ||
| 747 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 | ||
| 748 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 | ||
| 749 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 | ||
| 750 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 | ||
| 751 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 | ||
| 752 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 | ||
| 753 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 | ||
| 754 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 | ||
| 755 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 | ||
| 756 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 | ||
| 757 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 | ||
| 758 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 | ||
| 759 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 | ||
| 760 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 | ||
| 761 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 | ||
| 762 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 | ||
| 763 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 | ||
| 764 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 | ||
| 765 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 | ||
| 766 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 | ||
| 767 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 | ||
| 768 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 | ||
| 769 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 | ||
| 770 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 | ||
| 771 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 | ||
| 772 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 | ||
| 773 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 | ||
| 774 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 | ||
| 775 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 | ||
| 776 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 | ||
| 777 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 | ||
| 778 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 | ||
| 779 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 | ||
| 780 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 | ||
| 781 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 | ||
| 782 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 | ||
| 783 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 | ||
| 784 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 | ||
| 785 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 | ||
| 786 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 | ||
| 787 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 | ||
| 788 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 | ||
| 789 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 | ||
| 790 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 | ||
| 791 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 | ||
| 792 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 | ||
| 793 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 | ||
| 794 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 | ||
| 795 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 | ||
| 796 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 | ||
| 797 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 | ||
| 798 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 | ||
| 799 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 | ||
| 800 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 | ||
| 801 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 | ||
| 802 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 | ||
| 803 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 | ||
| 804 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 | ||
| 805 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 | ||
| 806 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 | ||
| 807 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 | ||
| 808 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 | ||
| 809 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 | ||
| 810 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 | ||
| 811 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 | ||
| 812 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 | ||
| 813 | #define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 | ||
| 814 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 | ||
| 815 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 | ||
| 816 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 | ||
| 817 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 | ||
| 818 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 | ||
| 819 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 | ||
| 820 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 | ||
| 821 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 | ||
| 822 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 | ||
| 823 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 | ||
| 824 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 | ||
| 825 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 | ||
| 826 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 | ||
| 827 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 | ||
| 828 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 | ||
| 829 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 | ||
| 830 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 | ||
| 831 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 | ||
| 832 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 | ||
| 833 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 | ||
| 834 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 | ||
| 835 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 | ||
| 836 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 | ||
| 837 | #define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 | ||
| 838 | #define reg_iop_sw_cpu_rw_ack_intr1_offset 104 | ||
| 839 | |||
| 840 | /* Register r_intr1, scope iop_sw_cpu, type r */ | ||
| 841 | #define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 | ||
| 842 | #define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 | ||
| 843 | #define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 | ||
| 844 | #define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 | ||
| 845 | #define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 | ||
| 846 | #define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 | ||
| 847 | #define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 | ||
| 848 | #define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 | ||
| 849 | #define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 | ||
| 850 | #define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 | ||
| 851 | #define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 | ||
| 852 | #define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 | ||
| 853 | #define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 | ||
| 854 | #define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 | ||
| 855 | #define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 | ||
| 856 | #define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 | ||
| 857 | #define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 | ||
| 858 | #define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 | ||
| 859 | #define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 | ||
| 860 | #define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 | ||
| 861 | #define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 | ||
| 862 | #define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 | ||
| 863 | #define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 | ||
| 864 | #define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 | ||
| 865 | #define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 | ||
| 866 | #define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 | ||
| 867 | #define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 | ||
| 868 | #define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 | ||
| 869 | #define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 | ||
| 870 | #define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 | ||
| 871 | #define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 | ||
| 872 | #define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 | ||
| 873 | #define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 | ||
| 874 | #define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 | ||
| 875 | #define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 | ||
| 876 | #define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 | ||
| 877 | #define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 | ||
| 878 | #define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 | ||
| 879 | #define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 | ||
| 880 | #define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 | ||
| 881 | #define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 | ||
| 882 | #define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 | ||
| 883 | #define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 | ||
| 884 | #define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 | ||
| 885 | #define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 | ||
| 886 | #define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 | ||
| 887 | #define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 | ||
| 888 | #define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 | ||
| 889 | #define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 | ||
| 890 | #define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 | ||
| 891 | #define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 | ||
| 892 | #define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 | ||
| 893 | #define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 | ||
| 894 | #define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 | ||
| 895 | #define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 | ||
| 896 | #define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 | ||
| 897 | #define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 | ||
| 898 | #define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 | ||
| 899 | #define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 | ||
| 900 | #define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 | ||
| 901 | #define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 | ||
| 902 | #define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 | ||
| 903 | #define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 | ||
| 904 | #define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 | ||
| 905 | #define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 | ||
| 906 | #define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 | ||
| 907 | #define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 | ||
| 908 | #define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 | ||
| 909 | #define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 | ||
| 910 | #define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 | ||
| 911 | #define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 | ||
| 912 | #define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 | ||
| 913 | #define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 | ||
| 914 | #define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 | ||
| 915 | #define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 | ||
| 916 | #define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 | ||
| 917 | #define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 | ||
| 918 | #define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 | ||
| 919 | #define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 | ||
| 920 | #define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 | ||
| 921 | #define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 | ||
| 922 | #define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 | ||
| 923 | #define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 | ||
| 924 | #define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 | ||
| 925 | #define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 | ||
| 926 | #define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 | ||
| 927 | #define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 | ||
| 928 | #define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 | ||
| 929 | #define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 | ||
| 930 | #define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 | ||
| 931 | #define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 | ||
| 932 | #define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 | ||
| 933 | #define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 | ||
| 934 | #define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 | ||
| 935 | #define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 | ||
| 936 | #define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 | ||
| 937 | #define reg_iop_sw_cpu_r_intr1_offset 108 | ||
| 938 | |||
| 939 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | ||
| 940 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 | ||
| 941 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 | ||
| 942 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 | ||
| 943 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 | ||
| 944 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 | ||
| 945 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 | ||
| 946 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 | ||
| 947 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 | ||
| 948 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 | ||
| 949 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 | ||
| 950 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 | ||
| 951 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 | ||
| 952 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 | ||
| 953 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 | ||
| 954 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 | ||
| 955 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 | ||
| 956 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 | ||
| 957 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 | ||
| 958 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 | ||
| 959 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 | ||
| 960 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 | ||
| 961 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 | ||
| 962 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 | ||
| 963 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 | ||
| 964 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 | ||
| 965 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 | ||
| 966 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 | ||
| 967 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 | ||
| 968 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 | ||
| 969 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 | ||
| 970 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 | ||
| 971 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 | ||
| 972 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 | ||
| 973 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 | ||
| 974 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 | ||
| 975 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 | ||
| 976 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 | ||
| 977 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 | ||
| 978 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 | ||
| 979 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 | ||
| 980 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 | ||
| 981 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 | ||
| 982 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 | ||
| 983 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 | ||
| 984 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 | ||
| 985 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 | ||
| 986 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 | ||
| 987 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 | ||
| 988 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 | ||
| 989 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 | ||
| 990 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 | ||
| 991 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 | ||
| 992 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 | ||
| 993 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 | ||
| 994 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 | ||
| 995 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 | ||
| 996 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 | ||
| 997 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 | ||
| 998 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 | ||
| 999 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 | ||
| 1000 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 | ||
| 1001 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 | ||
| 1002 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 | ||
| 1003 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 | ||
| 1004 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 | ||
| 1005 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 | ||
| 1006 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 | ||
| 1007 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 | ||
| 1008 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 | ||
| 1009 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 | ||
| 1010 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 | ||
| 1011 | #define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 | ||
| 1012 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 | ||
| 1013 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 | ||
| 1014 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 | ||
| 1015 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 | ||
| 1016 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 | ||
| 1017 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 | ||
| 1018 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 | ||
| 1019 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 | ||
| 1020 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 | ||
| 1021 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 | ||
| 1022 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 | ||
| 1023 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 | ||
| 1024 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 | ||
| 1025 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 | ||
| 1026 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 | ||
| 1027 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 | ||
| 1028 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 | ||
| 1029 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 | ||
| 1030 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 | ||
| 1031 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 | ||
| 1032 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 | ||
| 1033 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 | ||
| 1034 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 | ||
| 1035 | #define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 | ||
| 1036 | #define reg_iop_sw_cpu_r_masked_intr1_offset 112 | ||
| 1037 | |||
| 1038 | /* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ | ||
| 1039 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 | ||
| 1040 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 | ||
| 1041 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 | ||
| 1042 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 | ||
| 1043 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 | ||
| 1044 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 | ||
| 1045 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 | ||
| 1046 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 | ||
| 1047 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 | ||
| 1048 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 | ||
| 1049 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 | ||
| 1050 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 | ||
| 1051 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 | ||
| 1052 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 | ||
| 1053 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 | ||
| 1054 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 | ||
| 1055 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 | ||
| 1056 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 | ||
| 1057 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 | ||
| 1058 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 | ||
| 1059 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 | ||
| 1060 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 | ||
| 1061 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 | ||
| 1062 | #define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 | ||
| 1063 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 | ||
| 1064 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 | ||
| 1065 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 | ||
| 1066 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 | ||
| 1067 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 | ||
| 1068 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 | ||
| 1069 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 | ||
| 1070 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 | ||
| 1071 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 | ||
| 1072 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 | ||
| 1073 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 | ||
| 1074 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 | ||
| 1075 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 | ||
| 1076 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 | ||
| 1077 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 | ||
| 1078 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 | ||
| 1079 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 | ||
| 1080 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 | ||
| 1081 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 | ||
| 1082 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 | ||
| 1083 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 | ||
| 1084 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 | ||
| 1085 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 | ||
| 1086 | #define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 | ||
| 1087 | #define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 | ||
| 1088 | #define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 | ||
| 1089 | #define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 | ||
| 1090 | #define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 | ||
| 1091 | #define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 | ||
| 1092 | #define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 | ||
| 1093 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 | ||
| 1094 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 | ||
| 1095 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 | ||
| 1096 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 | ||
| 1097 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 | ||
| 1098 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 | ||
| 1099 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 | ||
| 1100 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 | ||
| 1101 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 | ||
| 1102 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 | ||
| 1103 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 | ||
| 1104 | #define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 | ||
| 1105 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 | ||
| 1106 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 | ||
| 1107 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 | ||
| 1108 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 | ||
| 1109 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 | ||
| 1110 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 | ||
| 1111 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 | ||
| 1112 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 | ||
| 1113 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 | ||
| 1114 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 | ||
| 1115 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 | ||
| 1116 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 | ||
| 1117 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 | ||
| 1118 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 | ||
| 1119 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 | ||
| 1120 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 | ||
| 1121 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 | ||
| 1122 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 | ||
| 1123 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 | ||
| 1124 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 | ||
| 1125 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 | ||
| 1126 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 | ||
| 1127 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 | ||
| 1128 | #define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 | ||
| 1129 | #define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 | ||
| 1130 | #define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 | ||
| 1131 | #define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 | ||
| 1132 | #define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 | ||
| 1133 | #define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 | ||
| 1134 | #define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 | ||
| 1135 | #define reg_iop_sw_cpu_rw_intr2_mask_offset 116 | ||
| 1136 | |||
| 1137 | /* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ | ||
| 1138 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 | ||
| 1139 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 | ||
| 1140 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 | ||
| 1141 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 | ||
| 1142 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 | ||
| 1143 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 | ||
| 1144 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 | ||
| 1145 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 | ||
| 1146 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 | ||
| 1147 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 | ||
| 1148 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 | ||
| 1149 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 | ||
| 1150 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 | ||
| 1151 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 | ||
| 1152 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 | ||
| 1153 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 | ||
| 1154 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 | ||
| 1155 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 | ||
| 1156 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 | ||
| 1157 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 | ||
| 1158 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 | ||
| 1159 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 | ||
| 1160 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 | ||
| 1161 | #define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 | ||
| 1162 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 | ||
| 1163 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 | ||
| 1164 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 | ||
| 1165 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 | ||
| 1166 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 | ||
| 1167 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 | ||
| 1168 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 | ||
| 1169 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 | ||
| 1170 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 | ||
| 1171 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 | ||
| 1172 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 | ||
| 1173 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 | ||
| 1174 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 | ||
| 1175 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 | ||
| 1176 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 | ||
| 1177 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 | ||
| 1178 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 | ||
| 1179 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 | ||
| 1180 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 | ||
| 1181 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 | ||
| 1182 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 | ||
| 1183 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 | ||
| 1184 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 | ||
| 1185 | #define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 | ||
| 1186 | #define reg_iop_sw_cpu_rw_ack_intr2_offset 120 | ||
| 1187 | |||
| 1188 | /* Register r_intr2, scope iop_sw_cpu, type r */ | ||
| 1189 | #define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 | ||
| 1190 | #define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 | ||
| 1191 | #define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 | ||
| 1192 | #define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 | ||
| 1193 | #define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 | ||
| 1194 | #define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 | ||
| 1195 | #define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 | ||
| 1196 | #define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 | ||
| 1197 | #define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 | ||
| 1198 | #define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 | ||
| 1199 | #define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 | ||
| 1200 | #define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 | ||
| 1201 | #define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 | ||
| 1202 | #define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 | ||
| 1203 | #define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 | ||
| 1204 | #define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 | ||
| 1205 | #define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 | ||
| 1206 | #define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 | ||
| 1207 | #define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 | ||
| 1208 | #define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 | ||
| 1209 | #define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 | ||
| 1210 | #define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 | ||
| 1211 | #define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 | ||
| 1212 | #define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 | ||
| 1213 | #define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 | ||
| 1214 | #define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 | ||
| 1215 | #define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 | ||
| 1216 | #define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 | ||
| 1217 | #define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 | ||
| 1218 | #define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 | ||
| 1219 | #define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 | ||
| 1220 | #define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 | ||
| 1221 | #define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 | ||
| 1222 | #define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 | ||
| 1223 | #define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 | ||
| 1224 | #define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 | ||
| 1225 | #define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 | ||
| 1226 | #define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 | ||
| 1227 | #define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 | ||
| 1228 | #define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 | ||
| 1229 | #define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 | ||
| 1230 | #define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 | ||
| 1231 | #define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 | ||
| 1232 | #define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 | ||
| 1233 | #define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 | ||
| 1234 | #define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 | ||
| 1235 | #define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 | ||
| 1236 | #define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 | ||
| 1237 | #define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 | ||
| 1238 | #define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 | ||
| 1239 | #define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 | ||
| 1240 | #define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 | ||
| 1241 | #define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 | ||
| 1242 | #define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 | ||
| 1243 | #define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 | ||
| 1244 | #define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 | ||
| 1245 | #define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 | ||
| 1246 | #define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 | ||
| 1247 | #define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 | ||
| 1248 | #define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 | ||
| 1249 | #define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 | ||
| 1250 | #define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 | ||
| 1251 | #define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 | ||
| 1252 | #define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 | ||
| 1253 | #define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 | ||
| 1254 | #define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 | ||
| 1255 | #define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 | ||
| 1256 | #define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 | ||
| 1257 | #define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 | ||
| 1258 | #define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 | ||
| 1259 | #define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 | ||
| 1260 | #define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 | ||
| 1261 | #define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 | ||
| 1262 | #define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 | ||
| 1263 | #define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 | ||
| 1264 | #define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 | ||
| 1265 | #define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 | ||
| 1266 | #define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 | ||
| 1267 | #define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 | ||
| 1268 | #define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 | ||
| 1269 | #define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 | ||
| 1270 | #define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 | ||
| 1271 | #define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 | ||
| 1272 | #define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 | ||
| 1273 | #define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 | ||
| 1274 | #define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 | ||
| 1275 | #define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 | ||
| 1276 | #define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 | ||
| 1277 | #define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 | ||
| 1278 | #define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 | ||
| 1279 | #define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 | ||
| 1280 | #define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 | ||
| 1281 | #define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 | ||
| 1282 | #define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 | ||
| 1283 | #define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 | ||
| 1284 | #define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 | ||
| 1285 | #define reg_iop_sw_cpu_r_intr2_offset 124 | ||
| 1286 | |||
| 1287 | /* Register r_masked_intr2, scope iop_sw_cpu, type r */ | ||
| 1288 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 | ||
| 1289 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 | ||
| 1290 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 | ||
| 1291 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 | ||
| 1292 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 | ||
| 1293 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 | ||
| 1294 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 | ||
| 1295 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 | ||
| 1296 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 | ||
| 1297 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 | ||
| 1298 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 | ||
| 1299 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 | ||
| 1300 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 | ||
| 1301 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 | ||
| 1302 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 | ||
| 1303 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 | ||
| 1304 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 | ||
| 1305 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 | ||
| 1306 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 | ||
| 1307 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 | ||
| 1308 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 | ||
| 1309 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 | ||
| 1310 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 | ||
| 1311 | #define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 | ||
| 1312 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 | ||
| 1313 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 | ||
| 1314 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 | ||
| 1315 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 | ||
| 1316 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 | ||
| 1317 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 | ||
| 1318 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 | ||
| 1319 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 | ||
| 1320 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 | ||
| 1321 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 | ||
| 1322 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 | ||
| 1323 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 | ||
| 1324 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 | ||
| 1325 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 | ||
| 1326 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 | ||
| 1327 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 | ||
| 1328 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 | ||
| 1329 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 | ||
| 1330 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 | ||
| 1331 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 | ||
| 1332 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 | ||
| 1333 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 | ||
| 1334 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 | ||
| 1335 | #define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 | ||
| 1336 | #define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 | ||
| 1337 | #define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 | ||
| 1338 | #define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 | ||
| 1339 | #define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 | ||
| 1340 | #define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 | ||
| 1341 | #define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 | ||
| 1342 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 | ||
| 1343 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 | ||
| 1344 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 | ||
| 1345 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 | ||
| 1346 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 | ||
| 1347 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 | ||
| 1348 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 | ||
| 1349 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 | ||
| 1350 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 | ||
| 1351 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 | ||
| 1352 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 | ||
| 1353 | #define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 | ||
| 1354 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 | ||
| 1355 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 | ||
| 1356 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 | ||
| 1357 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 | ||
| 1358 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 | ||
| 1359 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 | ||
| 1360 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 | ||
| 1361 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 | ||
| 1362 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 | ||
| 1363 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 | ||
| 1364 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 | ||
| 1365 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 | ||
| 1366 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 | ||
| 1367 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 | ||
| 1368 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 | ||
| 1369 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 | ||
| 1370 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 | ||
| 1371 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 | ||
| 1372 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 | ||
| 1373 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 | ||
| 1374 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 | ||
| 1375 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 | ||
| 1376 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 | ||
| 1377 | #define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 | ||
| 1378 | #define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 | ||
| 1379 | #define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 | ||
| 1380 | #define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 | ||
| 1381 | #define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 | ||
| 1382 | #define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 | ||
| 1383 | #define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 | ||
| 1384 | #define reg_iop_sw_cpu_r_masked_intr2_offset 128 | ||
| 1385 | |||
| 1386 | /* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ | ||
| 1387 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 | ||
| 1388 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 | ||
| 1389 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 | ||
| 1390 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 | ||
| 1391 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 | ||
| 1392 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 | ||
| 1393 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 | ||
| 1394 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 | ||
| 1395 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 | ||
| 1396 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 | ||
| 1397 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 | ||
| 1398 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 | ||
| 1399 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 | ||
| 1400 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 | ||
| 1401 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 | ||
| 1402 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 | ||
| 1403 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 | ||
| 1404 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 | ||
| 1405 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 | ||
| 1406 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 | ||
| 1407 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 | ||
| 1408 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 | ||
| 1409 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 | ||
| 1410 | #define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 | ||
| 1411 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 | ||
| 1412 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 | ||
| 1413 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 | ||
| 1414 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 | ||
| 1415 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 | ||
| 1416 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 | ||
| 1417 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 | ||
| 1418 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 | ||
| 1419 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 | ||
| 1420 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 | ||
| 1421 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 | ||
| 1422 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 | ||
| 1423 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 | ||
| 1424 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 | ||
| 1425 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 | ||
| 1426 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 | ||
| 1427 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 | ||
| 1428 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 | ||
| 1429 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 | ||
| 1430 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 | ||
| 1431 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 | ||
| 1432 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 | ||
| 1433 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 | ||
| 1434 | #define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 | ||
| 1435 | #define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 | ||
| 1436 | #define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 | ||
| 1437 | #define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 | ||
| 1438 | #define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 | ||
| 1439 | #define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 | ||
| 1440 | #define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 | ||
| 1441 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 | ||
| 1442 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 | ||
| 1443 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 | ||
| 1444 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 | ||
| 1445 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 | ||
| 1446 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 | ||
| 1447 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 | ||
| 1448 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 | ||
| 1449 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 | ||
| 1450 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 | ||
| 1451 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 | ||
| 1452 | #define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 | ||
| 1453 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 | ||
| 1454 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 | ||
| 1455 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 | ||
| 1456 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 | ||
| 1457 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 | ||
| 1458 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 | ||
| 1459 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 | ||
| 1460 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 | ||
| 1461 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 | ||
| 1462 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 | ||
| 1463 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 | ||
| 1464 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 | ||
| 1465 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 | ||
| 1466 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 | ||
| 1467 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 | ||
| 1468 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 | ||
| 1469 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 | ||
| 1470 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 | ||
| 1471 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 | ||
| 1472 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 | ||
| 1473 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 | ||
| 1474 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 | ||
| 1475 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 | ||
| 1476 | #define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 | ||
| 1477 | #define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 | ||
| 1478 | #define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 | ||
| 1479 | #define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 | ||
| 1480 | #define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 | ||
| 1481 | #define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 | ||
| 1482 | #define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 | ||
| 1483 | #define reg_iop_sw_cpu_rw_intr3_mask_offset 132 | ||
| 1484 | |||
| 1485 | /* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ | ||
| 1486 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 | ||
| 1487 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 | ||
| 1488 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 | ||
| 1489 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 | ||
| 1490 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 | ||
| 1491 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 | ||
| 1492 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 | ||
| 1493 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 | ||
| 1494 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 | ||
| 1495 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 | ||
| 1496 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 | ||
| 1497 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 | ||
| 1498 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 | ||
| 1499 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 | ||
| 1500 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 | ||
| 1501 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 | ||
| 1502 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 | ||
| 1503 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 | ||
| 1504 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 | ||
| 1505 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 | ||
| 1506 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 | ||
| 1507 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 | ||
| 1508 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 | ||
| 1509 | #define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 | ||
| 1510 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 | ||
| 1511 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 | ||
| 1512 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 | ||
| 1513 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 | ||
| 1514 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 | ||
| 1515 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 | ||
| 1516 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 | ||
| 1517 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 | ||
| 1518 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 | ||
| 1519 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 | ||
| 1520 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 | ||
| 1521 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 | ||
| 1522 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 | ||
| 1523 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 | ||
| 1524 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 | ||
| 1525 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 | ||
| 1526 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 | ||
| 1527 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 | ||
| 1528 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 | ||
| 1529 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 | ||
| 1530 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 | ||
| 1531 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 | ||
| 1532 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 | ||
| 1533 | #define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 | ||
| 1534 | #define reg_iop_sw_cpu_rw_ack_intr3_offset 136 | ||
| 1535 | |||
| 1536 | /* Register r_intr3, scope iop_sw_cpu, type r */ | ||
| 1537 | #define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 | ||
| 1538 | #define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 | ||
| 1539 | #define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 | ||
| 1540 | #define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 | ||
| 1541 | #define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 | ||
| 1542 | #define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 | ||
| 1543 | #define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 | ||
| 1544 | #define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 | ||
| 1545 | #define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 | ||
| 1546 | #define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 | ||
| 1547 | #define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 | ||
| 1548 | #define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 | ||
| 1549 | #define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 | ||
| 1550 | #define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 | ||
| 1551 | #define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 | ||
| 1552 | #define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 | ||
| 1553 | #define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 | ||
| 1554 | #define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 | ||
| 1555 | #define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 | ||
| 1556 | #define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 | ||
| 1557 | #define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 | ||
| 1558 | #define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 | ||
| 1559 | #define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 | ||
| 1560 | #define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 | ||
| 1561 | #define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 | ||
| 1562 | #define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 | ||
| 1563 | #define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 | ||
| 1564 | #define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 | ||
| 1565 | #define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 | ||
| 1566 | #define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 | ||
| 1567 | #define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 | ||
| 1568 | #define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 | ||
| 1569 | #define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 | ||
| 1570 | #define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 | ||
| 1571 | #define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 | ||
| 1572 | #define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 | ||
| 1573 | #define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 | ||
| 1574 | #define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 | ||
| 1575 | #define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 | ||
| 1576 | #define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 | ||
| 1577 | #define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 | ||
| 1578 | #define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 | ||
| 1579 | #define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 | ||
| 1580 | #define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 | ||
| 1581 | #define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 | ||
| 1582 | #define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 | ||
| 1583 | #define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 | ||
| 1584 | #define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 | ||
| 1585 | #define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 | ||
| 1586 | #define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 | ||
| 1587 | #define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 | ||
| 1588 | #define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 | ||
| 1589 | #define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 | ||
| 1590 | #define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 | ||
| 1591 | #define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 | ||
| 1592 | #define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 | ||
| 1593 | #define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 | ||
| 1594 | #define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 | ||
| 1595 | #define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 | ||
| 1596 | #define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 | ||
| 1597 | #define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 | ||
| 1598 | #define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 | ||
| 1599 | #define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 | ||
| 1600 | #define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 | ||
| 1601 | #define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 | ||
| 1602 | #define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 | ||
| 1603 | #define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 | ||
| 1604 | #define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 | ||
| 1605 | #define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 | ||
| 1606 | #define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 | ||
| 1607 | #define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 | ||
| 1608 | #define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 | ||
| 1609 | #define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 | ||
| 1610 | #define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 | ||
| 1611 | #define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 | ||
| 1612 | #define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 | ||
| 1613 | #define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 | ||
| 1614 | #define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 | ||
| 1615 | #define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 | ||
| 1616 | #define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 | ||
| 1617 | #define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 | ||
| 1618 | #define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 | ||
| 1619 | #define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 | ||
| 1620 | #define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 | ||
| 1621 | #define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 | ||
| 1622 | #define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 | ||
| 1623 | #define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 | ||
| 1624 | #define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 | ||
| 1625 | #define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 | ||
| 1626 | #define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 | ||
| 1627 | #define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 | ||
| 1628 | #define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 | ||
| 1629 | #define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 | ||
| 1630 | #define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 | ||
| 1631 | #define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 | ||
| 1632 | #define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 | ||
| 1633 | #define reg_iop_sw_cpu_r_intr3_offset 140 | ||
| 1634 | |||
| 1635 | /* Register r_masked_intr3, scope iop_sw_cpu, type r */ | ||
| 1636 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 | ||
| 1637 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 | ||
| 1638 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 | ||
| 1639 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 | ||
| 1640 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 | ||
| 1641 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 | ||
| 1642 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 | ||
| 1643 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 | ||
| 1644 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 | ||
| 1645 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 | ||
| 1646 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 | ||
| 1647 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 | ||
| 1648 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 | ||
| 1649 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 | ||
| 1650 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 | ||
| 1651 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 | ||
| 1652 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 | ||
| 1653 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 | ||
| 1654 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 | ||
| 1655 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 | ||
| 1656 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 | ||
| 1657 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 | ||
| 1658 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 | ||
| 1659 | #define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 | ||
| 1660 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 | ||
| 1661 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 | ||
| 1662 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 | ||
| 1663 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 | ||
| 1664 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 | ||
| 1665 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 | ||
| 1666 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 | ||
| 1667 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 | ||
| 1668 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 | ||
| 1669 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 | ||
| 1670 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 | ||
| 1671 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 | ||
| 1672 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 | ||
| 1673 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 | ||
| 1674 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 | ||
| 1675 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 | ||
| 1676 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 | ||
| 1677 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 | ||
| 1678 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 | ||
| 1679 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 | ||
| 1680 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 | ||
| 1681 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 | ||
| 1682 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 | ||
| 1683 | #define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 | ||
| 1684 | #define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 | ||
| 1685 | #define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 | ||
| 1686 | #define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 | ||
| 1687 | #define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 | ||
| 1688 | #define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 | ||
| 1689 | #define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 | ||
| 1690 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 | ||
| 1691 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 | ||
| 1692 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 | ||
| 1693 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 | ||
| 1694 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 | ||
| 1695 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 | ||
| 1696 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 | ||
| 1697 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 | ||
| 1698 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 | ||
| 1699 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 | ||
| 1700 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 | ||
| 1701 | #define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 | ||
| 1702 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 | ||
| 1703 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 | ||
| 1704 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 | ||
| 1705 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 | ||
| 1706 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 | ||
| 1707 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 | ||
| 1708 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 | ||
| 1709 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 | ||
| 1710 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 | ||
| 1711 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 | ||
| 1712 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 | ||
| 1713 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 | ||
| 1714 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 | ||
| 1715 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 | ||
| 1716 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 | ||
| 1717 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 | ||
| 1718 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 | ||
| 1719 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 | ||
| 1720 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 | ||
| 1721 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 | ||
| 1722 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 | ||
| 1723 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 | ||
| 1724 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 | ||
| 1725 | #define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 | ||
| 1726 | #define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 | ||
| 1727 | #define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 | ||
| 1728 | #define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 | ||
| 1729 | #define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 | ||
| 1730 | #define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 | ||
| 1731 | #define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 | ||
| 1732 | #define reg_iop_sw_cpu_r_masked_intr3_offset 144 | ||
| 1733 | |||
| 1734 | |||
| 1735 | /* Constants */ | ||
| 1736 | #define regk_iop_sw_cpu_copy 0x00000000 | ||
| 1737 | #define regk_iop_sw_cpu_no 0x00000000 | ||
| 1738 | #define regk_iop_sw_cpu_rd 0x00000002 | ||
| 1739 | #define regk_iop_sw_cpu_reg_copy 0x00000001 | ||
| 1740 | #define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 | ||
| 1741 | #define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 | ||
| 1742 | #define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 | ||
| 1743 | #define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 | ||
| 1744 | #define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 | ||
| 1745 | #define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 | ||
| 1746 | #define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 | ||
| 1747 | #define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 | ||
| 1748 | #define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 | ||
| 1749 | #define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 1750 | #define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 1751 | #define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 | ||
| 1752 | #define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 | ||
| 1753 | #define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 | ||
| 1754 | #define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 | ||
| 1755 | #define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 | ||
| 1756 | #define regk_iop_sw_cpu_wr 0x00000003 | ||
| 1757 | #define regk_iop_sw_cpu_yes 0x00000001 | ||
| 1758 | #endif /* __iop_sw_cpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index ee7dc0435b59..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null | |||
| @@ -1,1776 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_mpu_defs_asm_h | ||
| 2 | #define __iop_sw_mpu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:19 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r | ||
| 11 | * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ | ||
| 57 | #define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 | ||
| 58 | #define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 | ||
| 59 | #define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 | ||
| 60 | |||
| 61 | /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ | ||
| 62 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 63 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 | ||
| 64 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 65 | #define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 | ||
| 66 | #define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 | ||
| 67 | #define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 | ||
| 68 | #define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 | ||
| 69 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 | ||
| 70 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 | ||
| 71 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 | ||
| 72 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 | ||
| 73 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 | ||
| 74 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 | ||
| 75 | #define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 | ||
| 76 | |||
| 77 | /* Register rw_mc_data, scope iop_sw_mpu, type rw */ | ||
| 78 | #define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 | ||
| 79 | #define reg_iop_sw_mpu_rw_mc_data___val___width 32 | ||
| 80 | #define reg_iop_sw_mpu_rw_mc_data_offset 8 | ||
| 81 | |||
| 82 | /* Register rw_mc_addr, scope iop_sw_mpu, type rw */ | ||
| 83 | #define reg_iop_sw_mpu_rw_mc_addr_offset 12 | ||
| 84 | |||
| 85 | /* Register rs_mc_data, scope iop_sw_mpu, type rs */ | ||
| 86 | #define reg_iop_sw_mpu_rs_mc_data_offset 16 | ||
| 87 | |||
| 88 | /* Register r_mc_data, scope iop_sw_mpu, type r */ | ||
| 89 | #define reg_iop_sw_mpu_r_mc_data_offset 20 | ||
| 90 | |||
| 91 | /* Register r_mc_stat, scope iop_sw_mpu, type r */ | ||
| 92 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 | ||
| 93 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 | ||
| 94 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 | ||
| 95 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 | ||
| 96 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 | ||
| 97 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 | ||
| 98 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 | ||
| 99 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 | ||
| 100 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 | ||
| 101 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 | ||
| 102 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 | ||
| 103 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 | ||
| 104 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 | ||
| 105 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 | ||
| 106 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 | ||
| 107 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 | ||
| 108 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 | ||
| 109 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 | ||
| 110 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 | ||
| 111 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 | ||
| 112 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 | ||
| 113 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 | ||
| 114 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 | ||
| 115 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 | ||
| 116 | #define reg_iop_sw_mpu_r_mc_stat_offset 24 | ||
| 117 | |||
| 118 | /* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 119 | #define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 | ||
| 120 | #define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 | ||
| 121 | #define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 | ||
| 122 | #define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 | ||
| 123 | #define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 | ||
| 124 | #define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 | ||
| 125 | #define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 | ||
| 126 | #define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 | ||
| 127 | #define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 | ||
| 128 | |||
| 129 | /* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ | ||
| 130 | #define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 | ||
| 131 | #define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 | ||
| 132 | #define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 | ||
| 133 | #define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 | ||
| 134 | #define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 | ||
| 135 | #define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 | ||
| 136 | #define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 | ||
| 137 | #define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 | ||
| 138 | #define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 | ||
| 139 | |||
| 140 | /* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 141 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 | ||
| 142 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 | ||
| 143 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 | ||
| 144 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 | ||
| 145 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 | ||
| 146 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 | ||
| 147 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 | ||
| 148 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 | ||
| 149 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 | ||
| 150 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 | ||
| 151 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 | ||
| 152 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 | ||
| 153 | #define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 | ||
| 154 | |||
| 155 | /* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 156 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 | ||
| 157 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 | ||
| 158 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 | ||
| 159 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 | ||
| 160 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 | ||
| 161 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 | ||
| 162 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 | ||
| 163 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 | ||
| 164 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 | ||
| 165 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 | ||
| 166 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 | ||
| 167 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 | ||
| 168 | #define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 | ||
| 169 | |||
| 170 | /* Register r_bus0_in, scope iop_sw_mpu, type r */ | ||
| 171 | #define reg_iop_sw_mpu_r_bus0_in_offset 44 | ||
| 172 | |||
| 173 | /* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 174 | #define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 | ||
| 175 | #define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 | ||
| 176 | #define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 | ||
| 177 | #define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 | ||
| 178 | #define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 | ||
| 179 | #define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 | ||
| 180 | #define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 | ||
| 181 | #define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 | ||
| 182 | #define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 | ||
| 183 | |||
| 184 | /* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ | ||
| 185 | #define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 | ||
| 186 | #define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 | ||
| 187 | #define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 | ||
| 188 | #define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 | ||
| 189 | #define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 | ||
| 190 | #define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 | ||
| 191 | #define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 | ||
| 192 | #define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 | ||
| 193 | #define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 | ||
| 194 | |||
| 195 | /* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 196 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 | ||
| 197 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 | ||
| 198 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 | ||
| 199 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 | ||
| 200 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 | ||
| 201 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 | ||
| 202 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 | ||
| 203 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 | ||
| 204 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 | ||
| 205 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 | ||
| 206 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 | ||
| 207 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 | ||
| 208 | #define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 | ||
| 209 | |||
| 210 | /* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 211 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 | ||
| 212 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 | ||
| 213 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 | ||
| 214 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 | ||
| 215 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 | ||
| 216 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 | ||
| 217 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 | ||
| 218 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 | ||
| 219 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 | ||
| 220 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 | ||
| 221 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 | ||
| 222 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 | ||
| 223 | #define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 | ||
| 224 | |||
| 225 | /* Register r_bus1_in, scope iop_sw_mpu, type r */ | ||
| 226 | #define reg_iop_sw_mpu_r_bus1_in_offset 64 | ||
| 227 | |||
| 228 | /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 229 | #define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 | ||
| 230 | #define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 | ||
| 231 | #define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 | ||
| 232 | |||
| 233 | /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ | ||
| 234 | #define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 | ||
| 235 | #define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 | ||
| 236 | #define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 | ||
| 237 | |||
| 238 | /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 239 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 240 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 | ||
| 241 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 | ||
| 242 | |||
| 243 | /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 244 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 245 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 | ||
| 246 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 | ||
| 247 | |||
| 248 | /* Register r_gio_in, scope iop_sw_mpu, type r */ | ||
| 249 | #define reg_iop_sw_mpu_r_gio_in_offset 84 | ||
| 250 | |||
| 251 | /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ | ||
| 252 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 | ||
| 253 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 | ||
| 254 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 | ||
| 255 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 | ||
| 256 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 | ||
| 257 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 | ||
| 258 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 | ||
| 259 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 | ||
| 260 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 | ||
| 261 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 | ||
| 262 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 | ||
| 263 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 | ||
| 264 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 | ||
| 265 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 | ||
| 266 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 | ||
| 267 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 | ||
| 268 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 | ||
| 269 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 | ||
| 270 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 | ||
| 271 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 | ||
| 272 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 | ||
| 273 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 | ||
| 274 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 | ||
| 275 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 | ||
| 276 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 | ||
| 277 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 | ||
| 278 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 | ||
| 279 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 | ||
| 280 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 | ||
| 281 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 | ||
| 282 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 | ||
| 283 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 | ||
| 284 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 | ||
| 285 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 | ||
| 286 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 | ||
| 287 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 | ||
| 288 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 | ||
| 289 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 | ||
| 290 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 | ||
| 291 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 | ||
| 292 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 | ||
| 293 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 | ||
| 294 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 | ||
| 295 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 | ||
| 296 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 | ||
| 297 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 | ||
| 298 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 | ||
| 299 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 | ||
| 300 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 | ||
| 301 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 | ||
| 302 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 | ||
| 303 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 | ||
| 304 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 | ||
| 305 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 | ||
| 306 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 | ||
| 307 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 | ||
| 308 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 | ||
| 309 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 | ||
| 310 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 | ||
| 311 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 | ||
| 312 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 | ||
| 313 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 | ||
| 314 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 | ||
| 315 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 | ||
| 316 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 | ||
| 317 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 | ||
| 318 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 | ||
| 319 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 | ||
| 320 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 | ||
| 321 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 | ||
| 322 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 | ||
| 323 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 | ||
| 324 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 | ||
| 325 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 | ||
| 326 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 | ||
| 327 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 | ||
| 328 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 | ||
| 329 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 | ||
| 330 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 | ||
| 331 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 | ||
| 332 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 | ||
| 333 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 | ||
| 334 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 | ||
| 335 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 | ||
| 336 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 | ||
| 337 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 | ||
| 338 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 | ||
| 339 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 | ||
| 340 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 | ||
| 341 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 | ||
| 342 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 | ||
| 343 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 | ||
| 344 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 | ||
| 345 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 | ||
| 346 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 | ||
| 347 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 | ||
| 348 | #define reg_iop_sw_mpu_rw_cpu_intr_offset 88 | ||
| 349 | |||
| 350 | /* Register r_cpu_intr, scope iop_sw_mpu, type r */ | ||
| 351 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 | ||
| 352 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 | ||
| 353 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 | ||
| 354 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 | ||
| 355 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 | ||
| 356 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 | ||
| 357 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 | ||
| 358 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 | ||
| 359 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 | ||
| 360 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 | ||
| 361 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 | ||
| 362 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 | ||
| 363 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 | ||
| 364 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 | ||
| 365 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 | ||
| 366 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 | ||
| 367 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 | ||
| 368 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 | ||
| 369 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 | ||
| 370 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 | ||
| 371 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 | ||
| 372 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 | ||
| 373 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 | ||
| 374 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 | ||
| 375 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 | ||
| 376 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 | ||
| 377 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 | ||
| 378 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 | ||
| 379 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 | ||
| 380 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 | ||
| 381 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 | ||
| 382 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 | ||
| 383 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 | ||
| 384 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 | ||
| 385 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 | ||
| 386 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 | ||
| 387 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 | ||
| 388 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 | ||
| 389 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 | ||
| 390 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 | ||
| 391 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 | ||
| 392 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 | ||
| 393 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 | ||
| 394 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 | ||
| 395 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 | ||
| 396 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 | ||
| 397 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 | ||
| 398 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 | ||
| 399 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 | ||
| 400 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 | ||
| 401 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 | ||
| 402 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 | ||
| 403 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 | ||
| 404 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 | ||
| 405 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 | ||
| 406 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 | ||
| 407 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 | ||
| 408 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 | ||
| 409 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 | ||
| 410 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 | ||
| 411 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 | ||
| 412 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 | ||
| 413 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 | ||
| 414 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 | ||
| 415 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 | ||
| 416 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 | ||
| 417 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 | ||
| 418 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 | ||
| 419 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 | ||
| 420 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 | ||
| 421 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 | ||
| 422 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 | ||
| 423 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 | ||
| 424 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 | ||
| 425 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 | ||
| 426 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 | ||
| 427 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 | ||
| 428 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 | ||
| 429 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 | ||
| 430 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 | ||
| 431 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 | ||
| 432 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 | ||
| 433 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 | ||
| 434 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 | ||
| 435 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 | ||
| 436 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 | ||
| 437 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 | ||
| 438 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 | ||
| 439 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 | ||
| 440 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 | ||
| 441 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 | ||
| 442 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 | ||
| 443 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 | ||
| 444 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 | ||
| 445 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 | ||
| 446 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 | ||
| 447 | #define reg_iop_sw_mpu_r_cpu_intr_offset 92 | ||
| 448 | |||
| 449 | /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ | ||
| 450 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 | ||
| 451 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 | ||
| 452 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 | ||
| 453 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 | ||
| 454 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 | ||
| 455 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 | ||
| 456 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 | ||
| 457 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 | ||
| 458 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 | ||
| 459 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 | ||
| 460 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 | ||
| 461 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 | ||
| 462 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 | ||
| 463 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 | ||
| 464 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 | ||
| 465 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 | ||
| 466 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 | ||
| 467 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 | ||
| 468 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 | ||
| 469 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 | ||
| 470 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 | ||
| 471 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 | ||
| 472 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 | ||
| 473 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 | ||
| 474 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 | ||
| 475 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 | ||
| 476 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 | ||
| 477 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 | ||
| 478 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 | ||
| 479 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 | ||
| 480 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 | ||
| 481 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 | ||
| 482 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 | ||
| 483 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 | ||
| 484 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 | ||
| 485 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 | ||
| 486 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 | ||
| 487 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 | ||
| 488 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 | ||
| 489 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 | ||
| 490 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 | ||
| 491 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 | ||
| 492 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 | ||
| 493 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 | ||
| 494 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 | ||
| 495 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 | ||
| 496 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 | ||
| 497 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 | ||
| 498 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 | ||
| 499 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 | ||
| 500 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 | ||
| 501 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 | ||
| 502 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 | ||
| 503 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 | ||
| 504 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 | ||
| 505 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 | ||
| 506 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 | ||
| 507 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 | ||
| 508 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 | ||
| 509 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 | ||
| 510 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 | ||
| 511 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 | ||
| 512 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 | ||
| 513 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 | ||
| 514 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 | ||
| 515 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 | ||
| 516 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 | ||
| 517 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 | ||
| 518 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 | ||
| 519 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 | ||
| 520 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 | ||
| 521 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 | ||
| 522 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 | ||
| 523 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 | ||
| 524 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 | ||
| 525 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 | ||
| 526 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 | ||
| 527 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 | ||
| 528 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 | ||
| 529 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 | ||
| 530 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 | ||
| 531 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 | ||
| 532 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 | ||
| 533 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 | ||
| 534 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 | ||
| 535 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 | ||
| 536 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 | ||
| 537 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 | ||
| 538 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 | ||
| 539 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 | ||
| 540 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 | ||
| 541 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 | ||
| 542 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 | ||
| 543 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 | ||
| 544 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 | ||
| 545 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 | ||
| 546 | #define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 | ||
| 547 | |||
| 548 | /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ | ||
| 549 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 | ||
| 550 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 | ||
| 551 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 | ||
| 552 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 | ||
| 553 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 | ||
| 554 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 | ||
| 555 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 | ||
| 556 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 | ||
| 557 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 | ||
| 558 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 | ||
| 559 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 | ||
| 560 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 | ||
| 561 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 | ||
| 562 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 | ||
| 563 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 | ||
| 564 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 | ||
| 565 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 | ||
| 566 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 | ||
| 567 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 | ||
| 568 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 | ||
| 569 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 | ||
| 570 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 | ||
| 571 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 | ||
| 572 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 | ||
| 573 | #define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 | ||
| 574 | |||
| 575 | /* Register r_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 576 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 | ||
| 577 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 | ||
| 578 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 | ||
| 579 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 | ||
| 580 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 | ||
| 581 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 | ||
| 582 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 | ||
| 583 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 | ||
| 584 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 | ||
| 585 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 | ||
| 586 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 | ||
| 587 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 | ||
| 588 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 | ||
| 589 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 | ||
| 590 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 | ||
| 591 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 | ||
| 592 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 | ||
| 593 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 | ||
| 594 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 | ||
| 595 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 | ||
| 596 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 | ||
| 597 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 | ||
| 598 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 | ||
| 599 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 | ||
| 600 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 | ||
| 601 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 | ||
| 602 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 | ||
| 603 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 | ||
| 604 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 | ||
| 605 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 | ||
| 606 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 | ||
| 607 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 | ||
| 608 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 | ||
| 609 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 | ||
| 610 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 | ||
| 611 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 | ||
| 612 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 | ||
| 613 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 | ||
| 614 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 | ||
| 615 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 | ||
| 616 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 | ||
| 617 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 | ||
| 618 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 | ||
| 619 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 | ||
| 620 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 | ||
| 621 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 | ||
| 622 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 | ||
| 623 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 | ||
| 624 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 | ||
| 625 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 | ||
| 626 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 | ||
| 627 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 | ||
| 628 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 | ||
| 629 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 | ||
| 630 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 | ||
| 631 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 | ||
| 632 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 | ||
| 633 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 | ||
| 634 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 | ||
| 635 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 | ||
| 636 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 | ||
| 637 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 | ||
| 638 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 | ||
| 639 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 | ||
| 640 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 | ||
| 641 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 | ||
| 642 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 | ||
| 643 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 | ||
| 644 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 | ||
| 645 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 | ||
| 646 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 | ||
| 647 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 | ||
| 648 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 | ||
| 649 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 | ||
| 650 | #define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 | ||
| 651 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 | ||
| 652 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 | ||
| 653 | #define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 | ||
| 654 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 | ||
| 655 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 | ||
| 656 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 | ||
| 657 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 | ||
| 658 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 | ||
| 659 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 | ||
| 660 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 | ||
| 661 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 | ||
| 662 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 | ||
| 663 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 | ||
| 664 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 | ||
| 665 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 | ||
| 666 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 | ||
| 667 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 | ||
| 668 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 | ||
| 669 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 | ||
| 670 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 | ||
| 671 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 | ||
| 672 | #define reg_iop_sw_mpu_r_intr_grp0_offset 104 | ||
| 673 | |||
| 674 | /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 675 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 | ||
| 676 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 | ||
| 677 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 | ||
| 678 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 | ||
| 679 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 | ||
| 680 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 | ||
| 681 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 | ||
| 682 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 | ||
| 683 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 | ||
| 684 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 | ||
| 685 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 | ||
| 686 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 | ||
| 687 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 | ||
| 688 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 | ||
| 689 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 | ||
| 690 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 | ||
| 691 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 | ||
| 692 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 | ||
| 693 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 | ||
| 694 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 | ||
| 695 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 | ||
| 696 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 | ||
| 697 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 | ||
| 698 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 | ||
| 699 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 | ||
| 700 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 | ||
| 701 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 | ||
| 702 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 | ||
| 703 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 | ||
| 704 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 | ||
| 705 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 | ||
| 706 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 | ||
| 707 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 | ||
| 708 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 | ||
| 709 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 | ||
| 710 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 | ||
| 711 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 | ||
| 712 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 | ||
| 713 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 | ||
| 714 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 | ||
| 715 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 | ||
| 716 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 | ||
| 717 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 | ||
| 718 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 | ||
| 719 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 | ||
| 720 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 | ||
| 721 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 | ||
| 722 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 | ||
| 723 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 | ||
| 724 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 | ||
| 725 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 | ||
| 726 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 | ||
| 727 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 | ||
| 728 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 | ||
| 729 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 | ||
| 730 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 | ||
| 731 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 | ||
| 732 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 | ||
| 733 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 | ||
| 734 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 | ||
| 735 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 | ||
| 736 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 | ||
| 737 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 | ||
| 738 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 | ||
| 739 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 | ||
| 740 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 | ||
| 741 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 | ||
| 742 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 | ||
| 743 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 | ||
| 744 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 | ||
| 745 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 | ||
| 746 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 | ||
| 747 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 | ||
| 748 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 | ||
| 749 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 | ||
| 750 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 | ||
| 751 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 | ||
| 752 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 | ||
| 753 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 | ||
| 754 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 | ||
| 755 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 | ||
| 756 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 | ||
| 757 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 | ||
| 758 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 | ||
| 759 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 | ||
| 760 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 | ||
| 761 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 | ||
| 762 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 | ||
| 763 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 | ||
| 764 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 | ||
| 765 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 | ||
| 766 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 | ||
| 767 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 | ||
| 768 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 | ||
| 769 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 | ||
| 770 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 | ||
| 771 | #define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 | ||
| 772 | |||
| 773 | /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ | ||
| 774 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 | ||
| 775 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 | ||
| 776 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 | ||
| 777 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 | ||
| 778 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 | ||
| 779 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 | ||
| 780 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 | ||
| 781 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 | ||
| 782 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 | ||
| 783 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 | ||
| 784 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 | ||
| 785 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 | ||
| 786 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 | ||
| 787 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 | ||
| 788 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 | ||
| 789 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 | ||
| 790 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 | ||
| 791 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 | ||
| 792 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 | ||
| 793 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 | ||
| 794 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 | ||
| 795 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 | ||
| 796 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 | ||
| 797 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 | ||
| 798 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 | ||
| 799 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 | ||
| 800 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 | ||
| 801 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 | ||
| 802 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 | ||
| 803 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 | ||
| 804 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 | ||
| 805 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 | ||
| 806 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 | ||
| 807 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 | ||
| 808 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 | ||
| 809 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 | ||
| 810 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 | ||
| 811 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 | ||
| 812 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 | ||
| 813 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 | ||
| 814 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 | ||
| 815 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 | ||
| 816 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 | ||
| 817 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 | ||
| 818 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 | ||
| 819 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 | ||
| 820 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 | ||
| 821 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 | ||
| 822 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 | ||
| 823 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 | ||
| 824 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 | ||
| 825 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 | ||
| 826 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 | ||
| 827 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 | ||
| 828 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 | ||
| 829 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 | ||
| 830 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 | ||
| 831 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 | ||
| 832 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 | ||
| 833 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 | ||
| 834 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 | ||
| 835 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 | ||
| 836 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 | ||
| 837 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 | ||
| 838 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 | ||
| 839 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 | ||
| 840 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 | ||
| 841 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 | ||
| 842 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 | ||
| 843 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 | ||
| 844 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 | ||
| 845 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 | ||
| 846 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 | ||
| 847 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 | ||
| 848 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 | ||
| 849 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 | ||
| 850 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 | ||
| 851 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 | ||
| 852 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 | ||
| 853 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 | ||
| 854 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 | ||
| 855 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 | ||
| 856 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 | ||
| 857 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 | ||
| 858 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 | ||
| 859 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 | ||
| 860 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 | ||
| 861 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 | ||
| 862 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 | ||
| 863 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 | ||
| 864 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 | ||
| 865 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 | ||
| 866 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 | ||
| 867 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 | ||
| 868 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 | ||
| 869 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 | ||
| 870 | #define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 | ||
| 871 | |||
| 872 | /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ | ||
| 873 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 | ||
| 874 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 | ||
| 875 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 | ||
| 876 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 | ||
| 877 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 | ||
| 878 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 | ||
| 879 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 | ||
| 880 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 | ||
| 881 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 | ||
| 882 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 | ||
| 883 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 | ||
| 884 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 | ||
| 885 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 | ||
| 886 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 | ||
| 887 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 | ||
| 888 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 | ||
| 889 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 | ||
| 890 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 | ||
| 891 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 | ||
| 892 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 | ||
| 893 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 | ||
| 894 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 | ||
| 895 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 | ||
| 896 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 | ||
| 897 | #define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 | ||
| 898 | |||
| 899 | /* Register r_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 900 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 | ||
| 901 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 | ||
| 902 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 | ||
| 903 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 | ||
| 904 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 | ||
| 905 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 | ||
| 906 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 | ||
| 907 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 | ||
| 908 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 | ||
| 909 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 | ||
| 910 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 | ||
| 911 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 | ||
| 912 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 | ||
| 913 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 | ||
| 914 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 | ||
| 915 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 | ||
| 916 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 | ||
| 917 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 | ||
| 918 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 | ||
| 919 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 | ||
| 920 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 | ||
| 921 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 | ||
| 922 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 | ||
| 923 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 | ||
| 924 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 | ||
| 925 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 | ||
| 926 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 | ||
| 927 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 | ||
| 928 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 | ||
| 929 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 | ||
| 930 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 | ||
| 931 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 | ||
| 932 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 | ||
| 933 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 | ||
| 934 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 | ||
| 935 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 | ||
| 936 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 | ||
| 937 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 | ||
| 938 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 | ||
| 939 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 | ||
| 940 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 | ||
| 941 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 | ||
| 942 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 | ||
| 943 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 | ||
| 944 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 | ||
| 945 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 | ||
| 946 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 | ||
| 947 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 | ||
| 948 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 | ||
| 949 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 | ||
| 950 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 | ||
| 951 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 | ||
| 952 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 | ||
| 953 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 | ||
| 954 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 | ||
| 955 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 | ||
| 956 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 | ||
| 957 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 | ||
| 958 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 | ||
| 959 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 | ||
| 960 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 | ||
| 961 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 | ||
| 962 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 | ||
| 963 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 | ||
| 964 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 | ||
| 965 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 | ||
| 966 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 | ||
| 967 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 | ||
| 968 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 | ||
| 969 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 | ||
| 970 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 | ||
| 971 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 | ||
| 972 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 | ||
| 973 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 | ||
| 974 | #define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 | ||
| 975 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 | ||
| 976 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 | ||
| 977 | #define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 | ||
| 978 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 | ||
| 979 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 | ||
| 980 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 | ||
| 981 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 | ||
| 982 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 | ||
| 983 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 | ||
| 984 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 | ||
| 985 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 | ||
| 986 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 | ||
| 987 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 | ||
| 988 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 | ||
| 989 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 | ||
| 990 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 | ||
| 991 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 | ||
| 992 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 | ||
| 993 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 | ||
| 994 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 | ||
| 995 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 | ||
| 996 | #define reg_iop_sw_mpu_r_intr_grp1_offset 120 | ||
| 997 | |||
| 998 | /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 999 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 | ||
| 1000 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 | ||
| 1001 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 | ||
| 1002 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 | ||
| 1003 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 | ||
| 1004 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 | ||
| 1005 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 | ||
| 1006 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 | ||
| 1007 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 | ||
| 1008 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 | ||
| 1009 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 | ||
| 1010 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 | ||
| 1011 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 | ||
| 1012 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 | ||
| 1013 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 | ||
| 1014 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 | ||
| 1015 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 | ||
| 1016 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 | ||
| 1017 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 | ||
| 1018 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 | ||
| 1019 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 | ||
| 1020 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 | ||
| 1021 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 | ||
| 1022 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 | ||
| 1023 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 | ||
| 1024 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 | ||
| 1025 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 | ||
| 1026 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 | ||
| 1027 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 | ||
| 1028 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 | ||
| 1029 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 | ||
| 1030 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 | ||
| 1031 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 | ||
| 1032 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 | ||
| 1033 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 | ||
| 1034 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 | ||
| 1035 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 | ||
| 1036 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 | ||
| 1037 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 | ||
| 1038 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 | ||
| 1039 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 | ||
| 1040 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 | ||
| 1041 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 | ||
| 1042 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 | ||
| 1043 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 | ||
| 1044 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 | ||
| 1045 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 | ||
| 1046 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 | ||
| 1047 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 | ||
| 1048 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 | ||
| 1049 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 | ||
| 1050 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 | ||
| 1051 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 | ||
| 1052 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 | ||
| 1053 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 | ||
| 1054 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 | ||
| 1055 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 | ||
| 1056 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 | ||
| 1057 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 | ||
| 1058 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 | ||
| 1059 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 | ||
| 1060 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 | ||
| 1061 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 | ||
| 1062 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 | ||
| 1063 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 | ||
| 1064 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 | ||
| 1065 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 | ||
| 1066 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 | ||
| 1067 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 | ||
| 1068 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 | ||
| 1069 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 | ||
| 1070 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 | ||
| 1071 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 | ||
| 1072 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 | ||
| 1073 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 | ||
| 1074 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 | ||
| 1075 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 | ||
| 1076 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 | ||
| 1077 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 | ||
| 1078 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 | ||
| 1079 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 | ||
| 1080 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 | ||
| 1081 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 | ||
| 1082 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 | ||
| 1083 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 | ||
| 1084 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 | ||
| 1085 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 | ||
| 1086 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 | ||
| 1087 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 | ||
| 1088 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 | ||
| 1089 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 | ||
| 1090 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 | ||
| 1091 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 | ||
| 1092 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 | ||
| 1093 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 | ||
| 1094 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 | ||
| 1095 | #define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 | ||
| 1096 | |||
| 1097 | /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ | ||
| 1098 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 | ||
| 1099 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 | ||
| 1100 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 | ||
| 1101 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 | ||
| 1102 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 | ||
| 1103 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 | ||
| 1104 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 | ||
| 1105 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 | ||
| 1106 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 | ||
| 1107 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 | ||
| 1108 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 | ||
| 1109 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 | ||
| 1110 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 | ||
| 1111 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 | ||
| 1112 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 | ||
| 1113 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 | ||
| 1114 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 | ||
| 1115 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 | ||
| 1116 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 | ||
| 1117 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 | ||
| 1118 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 | ||
| 1119 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 | ||
| 1120 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 | ||
| 1121 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 | ||
| 1122 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 | ||
| 1123 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 | ||
| 1124 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 | ||
| 1125 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 | ||
| 1126 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 | ||
| 1127 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 | ||
| 1128 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 | ||
| 1129 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 | ||
| 1130 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 | ||
| 1131 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 | ||
| 1132 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 | ||
| 1133 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 | ||
| 1134 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 | ||
| 1135 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 | ||
| 1136 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 | ||
| 1137 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 | ||
| 1138 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 | ||
| 1139 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 | ||
| 1140 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 | ||
| 1141 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 | ||
| 1142 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 | ||
| 1143 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 | ||
| 1144 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 | ||
| 1145 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 | ||
| 1146 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 | ||
| 1147 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 | ||
| 1148 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 | ||
| 1149 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 | ||
| 1150 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 | ||
| 1151 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 | ||
| 1152 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 | ||
| 1153 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 | ||
| 1154 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 | ||
| 1155 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 | ||
| 1156 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 | ||
| 1157 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 | ||
| 1158 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 | ||
| 1159 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 | ||
| 1160 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 | ||
| 1161 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 | ||
| 1162 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 | ||
| 1163 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 | ||
| 1164 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 | ||
| 1165 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 | ||
| 1166 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 | ||
| 1167 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 | ||
| 1168 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 | ||
| 1169 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 | ||
| 1170 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 | ||
| 1171 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 | ||
| 1172 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 | ||
| 1173 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 | ||
| 1174 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 | ||
| 1175 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 | ||
| 1176 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 | ||
| 1177 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 | ||
| 1178 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 | ||
| 1179 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 | ||
| 1180 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 | ||
| 1181 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 | ||
| 1182 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 | ||
| 1183 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 | ||
| 1184 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 | ||
| 1185 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 | ||
| 1186 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 | ||
| 1187 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 | ||
| 1188 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 | ||
| 1189 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 | ||
| 1190 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 | ||
| 1191 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 | ||
| 1192 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 | ||
| 1193 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 | ||
| 1194 | #define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 | ||
| 1195 | |||
| 1196 | /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ | ||
| 1197 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 | ||
| 1198 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 | ||
| 1199 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 | ||
| 1200 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 | ||
| 1201 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 | ||
| 1202 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 | ||
| 1203 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 | ||
| 1204 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 | ||
| 1205 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 | ||
| 1206 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 | ||
| 1207 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 | ||
| 1208 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 | ||
| 1209 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 | ||
| 1210 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 | ||
| 1211 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 | ||
| 1212 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 | ||
| 1213 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 | ||
| 1214 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 | ||
| 1215 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 | ||
| 1216 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 | ||
| 1217 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 | ||
| 1218 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 | ||
| 1219 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 | ||
| 1220 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 | ||
| 1221 | #define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 | ||
| 1222 | |||
| 1223 | /* Register r_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 1224 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 | ||
| 1225 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 | ||
| 1226 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 | ||
| 1227 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 | ||
| 1228 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 | ||
| 1229 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 | ||
| 1230 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 | ||
| 1231 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 | ||
| 1232 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 | ||
| 1233 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 | ||
| 1234 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 | ||
| 1235 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 | ||
| 1236 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 | ||
| 1237 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 | ||
| 1238 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 | ||
| 1239 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 | ||
| 1240 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 | ||
| 1241 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 | ||
| 1242 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 | ||
| 1243 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 | ||
| 1244 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 | ||
| 1245 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 | ||
| 1246 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 | ||
| 1247 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 | ||
| 1248 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 | ||
| 1249 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 | ||
| 1250 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 | ||
| 1251 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 | ||
| 1252 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 | ||
| 1253 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 | ||
| 1254 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 | ||
| 1255 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 | ||
| 1256 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 | ||
| 1257 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 | ||
| 1258 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 | ||
| 1259 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 | ||
| 1260 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 | ||
| 1261 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 | ||
| 1262 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 | ||
| 1263 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 | ||
| 1264 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 | ||
| 1265 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 | ||
| 1266 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 | ||
| 1267 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 | ||
| 1268 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 | ||
| 1269 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 | ||
| 1270 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 | ||
| 1271 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 | ||
| 1272 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 | ||
| 1273 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 | ||
| 1274 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 | ||
| 1275 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 | ||
| 1276 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 | ||
| 1277 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 | ||
| 1278 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 | ||
| 1279 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 | ||
| 1280 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 | ||
| 1281 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 | ||
| 1282 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 | ||
| 1283 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 | ||
| 1284 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 | ||
| 1285 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 | ||
| 1286 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 | ||
| 1287 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 | ||
| 1288 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 | ||
| 1289 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 | ||
| 1290 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 | ||
| 1291 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 | ||
| 1292 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 | ||
| 1293 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 | ||
| 1294 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 | ||
| 1295 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 | ||
| 1296 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 | ||
| 1297 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 | ||
| 1298 | #define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 | ||
| 1299 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 | ||
| 1300 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 | ||
| 1301 | #define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 | ||
| 1302 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 | ||
| 1303 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 | ||
| 1304 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 | ||
| 1305 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 | ||
| 1306 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 | ||
| 1307 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 | ||
| 1308 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 | ||
| 1309 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 | ||
| 1310 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 | ||
| 1311 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 | ||
| 1312 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 | ||
| 1313 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 | ||
| 1314 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 | ||
| 1315 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 | ||
| 1316 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 | ||
| 1317 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 | ||
| 1318 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 | ||
| 1319 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 | ||
| 1320 | #define reg_iop_sw_mpu_r_intr_grp2_offset 136 | ||
| 1321 | |||
| 1322 | /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 1323 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 | ||
| 1324 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 | ||
| 1325 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 | ||
| 1326 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 | ||
| 1327 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 | ||
| 1328 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 | ||
| 1329 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 | ||
| 1330 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 | ||
| 1331 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 | ||
| 1332 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 | ||
| 1333 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 | ||
| 1334 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 | ||
| 1335 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 | ||
| 1336 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 | ||
| 1337 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 | ||
| 1338 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 | ||
| 1339 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 | ||
| 1340 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 | ||
| 1341 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 | ||
| 1342 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 | ||
| 1343 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 | ||
| 1344 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 | ||
| 1345 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 | ||
| 1346 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 | ||
| 1347 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 | ||
| 1348 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 | ||
| 1349 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 | ||
| 1350 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 | ||
| 1351 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 | ||
| 1352 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 | ||
| 1353 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 | ||
| 1354 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 | ||
| 1355 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 | ||
| 1356 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 | ||
| 1357 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 | ||
| 1358 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 | ||
| 1359 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 | ||
| 1360 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 | ||
| 1361 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 | ||
| 1362 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 | ||
| 1363 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 | ||
| 1364 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 | ||
| 1365 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 | ||
| 1366 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 | ||
| 1367 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 | ||
| 1368 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 | ||
| 1369 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 | ||
| 1370 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 | ||
| 1371 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 | ||
| 1372 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 | ||
| 1373 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 | ||
| 1374 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 | ||
| 1375 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 | ||
| 1376 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 | ||
| 1377 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 | ||
| 1378 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 | ||
| 1379 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 | ||
| 1380 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 | ||
| 1381 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 | ||
| 1382 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 | ||
| 1383 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 | ||
| 1384 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 | ||
| 1385 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 | ||
| 1386 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 | ||
| 1387 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 | ||
| 1388 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 | ||
| 1389 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 | ||
| 1390 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 | ||
| 1391 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 | ||
| 1392 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 | ||
| 1393 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 | ||
| 1394 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 | ||
| 1395 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 | ||
| 1396 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 | ||
| 1397 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 | ||
| 1398 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 | ||
| 1399 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 | ||
| 1400 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 | ||
| 1401 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 | ||
| 1402 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 | ||
| 1403 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 | ||
| 1404 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 | ||
| 1405 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 | ||
| 1406 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 | ||
| 1407 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 | ||
| 1408 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 | ||
| 1409 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 | ||
| 1410 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 | ||
| 1411 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 | ||
| 1412 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 | ||
| 1413 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 | ||
| 1414 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 | ||
| 1415 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 | ||
| 1416 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 | ||
| 1417 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 | ||
| 1418 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 | ||
| 1419 | #define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 | ||
| 1420 | |||
| 1421 | /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ | ||
| 1422 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 | ||
| 1423 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 | ||
| 1424 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 | ||
| 1425 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 | ||
| 1426 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 | ||
| 1427 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 | ||
| 1428 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 | ||
| 1429 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 | ||
| 1430 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 | ||
| 1431 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 | ||
| 1432 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 | ||
| 1433 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 | ||
| 1434 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 | ||
| 1435 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 | ||
| 1436 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 | ||
| 1437 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 | ||
| 1438 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 | ||
| 1439 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 | ||
| 1440 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 | ||
| 1441 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 | ||
| 1442 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 | ||
| 1443 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 | ||
| 1444 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 | ||
| 1445 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 | ||
| 1446 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 | ||
| 1447 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 | ||
| 1448 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 | ||
| 1449 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 | ||
| 1450 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 | ||
| 1451 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 | ||
| 1452 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 | ||
| 1453 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 | ||
| 1454 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 | ||
| 1455 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 | ||
| 1456 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 | ||
| 1457 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 | ||
| 1458 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 | ||
| 1459 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 | ||
| 1460 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 | ||
| 1461 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 | ||
| 1462 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 | ||
| 1463 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 | ||
| 1464 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 | ||
| 1465 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 | ||
| 1466 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 | ||
| 1467 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 | ||
| 1468 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 | ||
| 1469 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 | ||
| 1470 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 | ||
| 1471 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 | ||
| 1472 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 | ||
| 1473 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 | ||
| 1474 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 | ||
| 1475 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 | ||
| 1476 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 | ||
| 1477 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 | ||
| 1478 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 | ||
| 1479 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 | ||
| 1480 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 | ||
| 1481 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 | ||
| 1482 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 | ||
| 1483 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 | ||
| 1484 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 | ||
| 1485 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 | ||
| 1486 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 | ||
| 1487 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 | ||
| 1488 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 | ||
| 1489 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 | ||
| 1490 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 | ||
| 1491 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 | ||
| 1492 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 | ||
| 1493 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 | ||
| 1494 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 | ||
| 1495 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 | ||
| 1496 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 | ||
| 1497 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 | ||
| 1498 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 | ||
| 1499 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 | ||
| 1500 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 | ||
| 1501 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 | ||
| 1502 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 | ||
| 1503 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 | ||
| 1504 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 | ||
| 1505 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 | ||
| 1506 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 | ||
| 1507 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 | ||
| 1508 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 | ||
| 1509 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 | ||
| 1510 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 | ||
| 1511 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 | ||
| 1512 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 | ||
| 1513 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 | ||
| 1514 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 | ||
| 1515 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 | ||
| 1516 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 | ||
| 1517 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 | ||
| 1518 | #define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 | ||
| 1519 | |||
| 1520 | /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ | ||
| 1521 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 | ||
| 1522 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 | ||
| 1523 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 | ||
| 1524 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 | ||
| 1525 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 | ||
| 1526 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 | ||
| 1527 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 | ||
| 1528 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 | ||
| 1529 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 | ||
| 1530 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 | ||
| 1531 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 | ||
| 1532 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 | ||
| 1533 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 | ||
| 1534 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 | ||
| 1535 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 | ||
| 1536 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 | ||
| 1537 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 | ||
| 1538 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 | ||
| 1539 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 | ||
| 1540 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 | ||
| 1541 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 | ||
| 1542 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 | ||
| 1543 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 | ||
| 1544 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 | ||
| 1545 | #define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 | ||
| 1546 | |||
| 1547 | /* Register r_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 1548 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 | ||
| 1549 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 | ||
| 1550 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 | ||
| 1551 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 | ||
| 1552 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 | ||
| 1553 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 | ||
| 1554 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 | ||
| 1555 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 | ||
| 1556 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 | ||
| 1557 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 | ||
| 1558 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 | ||
| 1559 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 | ||
| 1560 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 | ||
| 1561 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 | ||
| 1562 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 | ||
| 1563 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 | ||
| 1564 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 | ||
| 1565 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 | ||
| 1566 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 | ||
| 1567 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 | ||
| 1568 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 | ||
| 1569 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 | ||
| 1570 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 | ||
| 1571 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 | ||
| 1572 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 | ||
| 1573 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 | ||
| 1574 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 | ||
| 1575 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 | ||
| 1576 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 | ||
| 1577 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 | ||
| 1578 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 | ||
| 1579 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 | ||
| 1580 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 | ||
| 1581 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 | ||
| 1582 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 | ||
| 1583 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 | ||
| 1584 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 | ||
| 1585 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 | ||
| 1586 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 | ||
| 1587 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 | ||
| 1588 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 | ||
| 1589 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 | ||
| 1590 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 | ||
| 1591 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 | ||
| 1592 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 | ||
| 1593 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 | ||
| 1594 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 | ||
| 1595 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 | ||
| 1596 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 | ||
| 1597 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 | ||
| 1598 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 | ||
| 1599 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 | ||
| 1600 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 | ||
| 1601 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 | ||
| 1602 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 | ||
| 1603 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 | ||
| 1604 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 | ||
| 1605 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 | ||
| 1606 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 | ||
| 1607 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 | ||
| 1608 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 | ||
| 1609 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 | ||
| 1610 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 | ||
| 1611 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 | ||
| 1612 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 | ||
| 1613 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 | ||
| 1614 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 | ||
| 1615 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 | ||
| 1616 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 | ||
| 1617 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 | ||
| 1618 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 | ||
| 1619 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 | ||
| 1620 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 | ||
| 1621 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 | ||
| 1622 | #define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 | ||
| 1623 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 | ||
| 1624 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 | ||
| 1625 | #define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 | ||
| 1626 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 | ||
| 1627 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 | ||
| 1628 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 | ||
| 1629 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 | ||
| 1630 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 | ||
| 1631 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 | ||
| 1632 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 | ||
| 1633 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 | ||
| 1634 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 | ||
| 1635 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 | ||
| 1636 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 | ||
| 1637 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 | ||
| 1638 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 | ||
| 1639 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 | ||
| 1640 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 | ||
| 1641 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 | ||
| 1642 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 | ||
| 1643 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 | ||
| 1644 | #define reg_iop_sw_mpu_r_intr_grp3_offset 152 | ||
| 1645 | |||
| 1646 | /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 1647 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 | ||
| 1648 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 | ||
| 1649 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 | ||
| 1650 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 | ||
| 1651 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 | ||
| 1652 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 | ||
| 1653 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 | ||
| 1654 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 | ||
| 1655 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 | ||
| 1656 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 | ||
| 1657 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 | ||
| 1658 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 | ||
| 1659 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 | ||
| 1660 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 | ||
| 1661 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 | ||
| 1662 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 | ||
| 1663 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 | ||
| 1664 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 | ||
| 1665 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 | ||
| 1666 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 | ||
| 1667 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 | ||
| 1668 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 | ||
| 1669 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 | ||
| 1670 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 | ||
| 1671 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 | ||
| 1672 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 | ||
| 1673 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 | ||
| 1674 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 | ||
| 1675 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 | ||
| 1676 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 | ||
| 1677 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 | ||
| 1678 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 | ||
| 1679 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 | ||
| 1680 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 | ||
| 1681 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 | ||
| 1682 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 | ||
| 1683 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 | ||
| 1684 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 | ||
| 1685 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 | ||
| 1686 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 | ||
| 1687 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 | ||
| 1688 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 | ||
| 1689 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 | ||
| 1690 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 | ||
| 1691 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 | ||
| 1692 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 | ||
| 1693 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 | ||
| 1694 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 | ||
| 1695 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 | ||
| 1696 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 | ||
| 1697 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 | ||
| 1698 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 | ||
| 1699 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 | ||
| 1700 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 | ||
| 1701 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 | ||
| 1702 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 | ||
| 1703 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 | ||
| 1704 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 | ||
| 1705 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 | ||
| 1706 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 | ||
| 1707 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 | ||
| 1708 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 | ||
| 1709 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 | ||
| 1710 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 | ||
| 1711 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 | ||
| 1712 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 | ||
| 1713 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 | ||
| 1714 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 | ||
| 1715 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 | ||
| 1716 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 | ||
| 1717 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 | ||
| 1718 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 | ||
| 1719 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 | ||
| 1720 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 | ||
| 1721 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 | ||
| 1722 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 | ||
| 1723 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 | ||
| 1724 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 | ||
| 1725 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 | ||
| 1726 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 | ||
| 1727 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 | ||
| 1728 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 | ||
| 1729 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 | ||
| 1730 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 | ||
| 1731 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 | ||
| 1732 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 | ||
| 1733 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 | ||
| 1734 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 | ||
| 1735 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 | ||
| 1736 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 | ||
| 1737 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 | ||
| 1738 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 | ||
| 1739 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 | ||
| 1740 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 | ||
| 1741 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 | ||
| 1742 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 | ||
| 1743 | #define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 | ||
| 1744 | |||
| 1745 | |||
| 1746 | /* Constants */ | ||
| 1747 | #define regk_iop_sw_mpu_copy 0x00000000 | ||
| 1748 | #define regk_iop_sw_mpu_cpu 0x00000000 | ||
| 1749 | #define regk_iop_sw_mpu_mpu 0x00000001 | ||
| 1750 | #define regk_iop_sw_mpu_no 0x00000000 | ||
| 1751 | #define regk_iop_sw_mpu_nop 0x00000000 | ||
| 1752 | #define regk_iop_sw_mpu_rd 0x00000002 | ||
| 1753 | #define regk_iop_sw_mpu_reg_copy 0x00000001 | ||
| 1754 | #define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 | ||
| 1755 | #define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 | ||
| 1756 | #define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 | ||
| 1757 | #define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 | ||
| 1758 | #define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 | ||
| 1759 | #define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 | ||
| 1760 | #define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 | ||
| 1761 | #define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 | ||
| 1762 | #define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 | ||
| 1763 | #define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 1764 | #define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 1765 | #define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 | ||
| 1766 | #define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 | ||
| 1767 | #define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 | ||
| 1768 | #define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 | ||
| 1769 | #define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 | ||
| 1770 | #define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 | ||
| 1771 | #define regk_iop_sw_mpu_set 0x00000001 | ||
| 1772 | #define regk_iop_sw_mpu_spu0 0x00000002 | ||
| 1773 | #define regk_iop_sw_mpu_spu1 0x00000003 | ||
| 1774 | #define regk_iop_sw_mpu_wr 0x00000003 | ||
| 1775 | #define regk_iop_sw_mpu_yes 0x00000001 | ||
| 1776 | #endif /* __iop_sw_mpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 0929f144cfa1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null | |||
| @@ -1,691 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_spu_defs_asm_h | ||
| 2 | #define __iop_sw_spu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:19 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r | ||
| 11 | * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | ||
| 57 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 58 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 | ||
| 59 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 60 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 | ||
| 61 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 | ||
| 62 | #define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 | ||
| 63 | #define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 | ||
| 64 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 | ||
| 65 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 | ||
| 66 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 | ||
| 67 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 | ||
| 68 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 | ||
| 69 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 | ||
| 70 | #define reg_iop_sw_spu_rw_mc_ctrl_offset 0 | ||
| 71 | |||
| 72 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | ||
| 73 | #define reg_iop_sw_spu_rw_mc_data___val___lsb 0 | ||
| 74 | #define reg_iop_sw_spu_rw_mc_data___val___width 32 | ||
| 75 | #define reg_iop_sw_spu_rw_mc_data_offset 4 | ||
| 76 | |||
| 77 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | ||
| 78 | #define reg_iop_sw_spu_rw_mc_addr_offset 8 | ||
| 79 | |||
| 80 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | ||
| 81 | #define reg_iop_sw_spu_rs_mc_data_offset 12 | ||
| 82 | |||
| 83 | /* Register r_mc_data, scope iop_sw_spu, type r */ | ||
| 84 | #define reg_iop_sw_spu_r_mc_data_offset 16 | ||
| 85 | |||
| 86 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | ||
| 87 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 | ||
| 88 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 | ||
| 89 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 | ||
| 90 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 | ||
| 91 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 | ||
| 92 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 | ||
| 93 | #define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 | ||
| 94 | #define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 | ||
| 95 | #define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 | ||
| 96 | #define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 | ||
| 97 | #define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 | ||
| 98 | #define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 | ||
| 99 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 | ||
| 100 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 | ||
| 101 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 | ||
| 102 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 | ||
| 103 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 | ||
| 104 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 | ||
| 105 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 | ||
| 106 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 | ||
| 107 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 | ||
| 108 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 | ||
| 109 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 | ||
| 110 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 | ||
| 111 | #define reg_iop_sw_spu_r_mc_stat_offset 20 | ||
| 112 | |||
| 113 | /* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ | ||
| 114 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 | ||
| 115 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 | ||
| 116 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 | ||
| 117 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 | ||
| 118 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 | ||
| 119 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 | ||
| 120 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 | ||
| 121 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 | ||
| 122 | #define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 | ||
| 123 | |||
| 124 | /* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ | ||
| 125 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 | ||
| 126 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 | ||
| 127 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 | ||
| 128 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 | ||
| 129 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 | ||
| 130 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 | ||
| 131 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 | ||
| 132 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 | ||
| 133 | #define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 | ||
| 134 | |||
| 135 | /* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 136 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 | ||
| 137 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 | ||
| 138 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 | ||
| 139 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 | ||
| 140 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 | ||
| 141 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 | ||
| 142 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 | ||
| 143 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 | ||
| 144 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 | ||
| 145 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 | ||
| 146 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 | ||
| 147 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 | ||
| 148 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 | ||
| 149 | |||
| 150 | /* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 151 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 | ||
| 152 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 | ||
| 153 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 | ||
| 154 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 | ||
| 155 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 | ||
| 156 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 | ||
| 157 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 | ||
| 158 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 | ||
| 159 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 | ||
| 160 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 | ||
| 161 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 | ||
| 162 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 | ||
| 163 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 | ||
| 164 | |||
| 165 | /* Register r_bus0_in, scope iop_sw_spu, type r */ | ||
| 166 | #define reg_iop_sw_spu_r_bus0_in_offset 40 | ||
| 167 | |||
| 168 | /* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ | ||
| 169 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 | ||
| 170 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 | ||
| 171 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 | ||
| 172 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 | ||
| 173 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 | ||
| 174 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 | ||
| 175 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 | ||
| 176 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 | ||
| 177 | #define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 | ||
| 178 | |||
| 179 | /* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ | ||
| 180 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 | ||
| 181 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 | ||
| 182 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 | ||
| 183 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 | ||
| 184 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 | ||
| 185 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 | ||
| 186 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 | ||
| 187 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 | ||
| 188 | #define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 | ||
| 189 | |||
| 190 | /* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 191 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 | ||
| 192 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 | ||
| 193 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 | ||
| 194 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 | ||
| 195 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 | ||
| 196 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 | ||
| 197 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 | ||
| 198 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 | ||
| 199 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 | ||
| 200 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 | ||
| 201 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 | ||
| 202 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 | ||
| 203 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 | ||
| 204 | |||
| 205 | /* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 206 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 | ||
| 207 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 | ||
| 208 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 | ||
| 209 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 | ||
| 210 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 | ||
| 211 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 | ||
| 212 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 | ||
| 213 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 | ||
| 214 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 | ||
| 215 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 | ||
| 216 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 | ||
| 217 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 | ||
| 218 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 | ||
| 219 | |||
| 220 | /* Register r_bus1_in, scope iop_sw_spu, type r */ | ||
| 221 | #define reg_iop_sw_spu_r_bus1_in_offset 60 | ||
| 222 | |||
| 223 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | ||
| 224 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 | ||
| 225 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 | ||
| 226 | #define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 | ||
| 227 | |||
| 228 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | ||
| 229 | #define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 | ||
| 230 | #define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 | ||
| 231 | #define reg_iop_sw_spu_rw_gio_set_mask_offset 68 | ||
| 232 | |||
| 233 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 234 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 235 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 | ||
| 236 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 | ||
| 237 | |||
| 238 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 239 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 240 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 | ||
| 241 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 | ||
| 242 | |||
| 243 | /* Register r_gio_in, scope iop_sw_spu, type r */ | ||
| 244 | #define reg_iop_sw_spu_r_gio_in_offset 80 | ||
| 245 | |||
| 246 | /* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 247 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 | ||
| 248 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 | ||
| 249 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 | ||
| 250 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 | ||
| 251 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 | ||
| 252 | |||
| 253 | /* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 254 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 | ||
| 255 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 | ||
| 256 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 | ||
| 257 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 | ||
| 258 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 | ||
| 259 | |||
| 260 | /* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 261 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 | ||
| 262 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 | ||
| 263 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 | ||
| 264 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 | ||
| 265 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 | ||
| 266 | |||
| 267 | /* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 268 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 | ||
| 269 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 | ||
| 270 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 | ||
| 271 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 | ||
| 272 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 | ||
| 273 | |||
| 274 | /* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 275 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 | ||
| 276 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 | ||
| 277 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 | ||
| 278 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 | ||
| 279 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 | ||
| 280 | |||
| 281 | /* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 282 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 | ||
| 283 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 | ||
| 284 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 | ||
| 285 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 | ||
| 286 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 | ||
| 287 | |||
| 288 | /* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 289 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 | ||
| 290 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 | ||
| 291 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 | ||
| 292 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 | ||
| 293 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 | ||
| 294 | |||
| 295 | /* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 296 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 | ||
| 297 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 | ||
| 298 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 | ||
| 299 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 | ||
| 300 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 | ||
| 301 | |||
| 302 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 303 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 | ||
| 304 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 | ||
| 305 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 | ||
| 306 | |||
| 307 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 308 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 | ||
| 309 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 | ||
| 310 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 | ||
| 311 | |||
| 312 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 313 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 | ||
| 314 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 | ||
| 315 | #define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 | ||
| 316 | |||
| 317 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 318 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 | ||
| 319 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 | ||
| 320 | #define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 | ||
| 321 | |||
| 322 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 323 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 | ||
| 324 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 | ||
| 325 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 | ||
| 326 | |||
| 327 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 328 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 | ||
| 329 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 | ||
| 330 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 | ||
| 331 | |||
| 332 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 333 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 | ||
| 334 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 | ||
| 335 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 | ||
| 336 | |||
| 337 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 338 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 | ||
| 339 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 | ||
| 340 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 | ||
| 341 | |||
| 342 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | ||
| 343 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 | ||
| 344 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 | ||
| 345 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 | ||
| 346 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 | ||
| 347 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 | ||
| 348 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 | ||
| 349 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 | ||
| 350 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 | ||
| 351 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 | ||
| 352 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 | ||
| 353 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 | ||
| 354 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 | ||
| 355 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 | ||
| 356 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 | ||
| 357 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 | ||
| 358 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 | ||
| 359 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 | ||
| 360 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 | ||
| 361 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 | ||
| 362 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 | ||
| 363 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 | ||
| 364 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 | ||
| 365 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 | ||
| 366 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 | ||
| 367 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 | ||
| 368 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 | ||
| 369 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 | ||
| 370 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 | ||
| 371 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 | ||
| 372 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 | ||
| 373 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 | ||
| 374 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 | ||
| 375 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 | ||
| 376 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 | ||
| 377 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 | ||
| 378 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 | ||
| 379 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 | ||
| 380 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 | ||
| 381 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 | ||
| 382 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 | ||
| 383 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 | ||
| 384 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 | ||
| 385 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 | ||
| 386 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 | ||
| 387 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 | ||
| 388 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 | ||
| 389 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 | ||
| 390 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 | ||
| 391 | #define reg_iop_sw_spu_rw_cpu_intr_offset 148 | ||
| 392 | |||
| 393 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | ||
| 394 | #define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 | ||
| 395 | #define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 | ||
| 396 | #define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 | ||
| 397 | #define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 | ||
| 398 | #define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 | ||
| 399 | #define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 | ||
| 400 | #define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 | ||
| 401 | #define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 | ||
| 402 | #define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 | ||
| 403 | #define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 | ||
| 404 | #define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 | ||
| 405 | #define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 | ||
| 406 | #define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 | ||
| 407 | #define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 | ||
| 408 | #define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 | ||
| 409 | #define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 | ||
| 410 | #define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 | ||
| 411 | #define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 | ||
| 412 | #define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 | ||
| 413 | #define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 | ||
| 414 | #define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 | ||
| 415 | #define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 | ||
| 416 | #define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 | ||
| 417 | #define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 | ||
| 418 | #define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 | ||
| 419 | #define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 | ||
| 420 | #define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 | ||
| 421 | #define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 | ||
| 422 | #define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 | ||
| 423 | #define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 | ||
| 424 | #define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 | ||
| 425 | #define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 | ||
| 426 | #define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 | ||
| 427 | #define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 | ||
| 428 | #define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 | ||
| 429 | #define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 | ||
| 430 | #define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 | ||
| 431 | #define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 | ||
| 432 | #define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 | ||
| 433 | #define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 | ||
| 434 | #define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 | ||
| 435 | #define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 | ||
| 436 | #define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 | ||
| 437 | #define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 | ||
| 438 | #define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 | ||
| 439 | #define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 | ||
| 440 | #define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 | ||
| 441 | #define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 | ||
| 442 | #define reg_iop_sw_spu_r_cpu_intr_offset 152 | ||
| 443 | |||
| 444 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | ||
| 445 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 | ||
| 446 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 | ||
| 447 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 | ||
| 448 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 | ||
| 449 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 | ||
| 450 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 | ||
| 451 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 | ||
| 452 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 | ||
| 453 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 | ||
| 454 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 | ||
| 455 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 | ||
| 456 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 | ||
| 457 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 | ||
| 458 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 | ||
| 459 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 | ||
| 460 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 | ||
| 461 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 | ||
| 462 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 | ||
| 463 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 | ||
| 464 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 | ||
| 465 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 | ||
| 466 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 | ||
| 467 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 | ||
| 468 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 | ||
| 469 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 | ||
| 470 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 | ||
| 471 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 | ||
| 472 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 | ||
| 473 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 | ||
| 474 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 | ||
| 475 | #define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 | ||
| 476 | #define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 | ||
| 477 | #define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 | ||
| 478 | #define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 | ||
| 479 | #define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 | ||
| 480 | #define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 | ||
| 481 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 | ||
| 482 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 | ||
| 483 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 | ||
| 484 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 | ||
| 485 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 | ||
| 486 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 | ||
| 487 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 | ||
| 488 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 | ||
| 489 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 | ||
| 490 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 | ||
| 491 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 | ||
| 492 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 | ||
| 493 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 | ||
| 494 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 | ||
| 495 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 | ||
| 496 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 | ||
| 497 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 | ||
| 498 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 | ||
| 499 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 | ||
| 500 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 | ||
| 501 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 | ||
| 502 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 | ||
| 503 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 | ||
| 504 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 | ||
| 505 | #define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 | ||
| 506 | #define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 | ||
| 507 | #define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 | ||
| 508 | #define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 | ||
| 509 | #define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 | ||
| 510 | #define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 | ||
| 511 | #define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 | ||
| 512 | #define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 | ||
| 513 | #define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 | ||
| 514 | #define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 | ||
| 515 | #define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 | ||
| 516 | #define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 | ||
| 517 | #define reg_iop_sw_spu_r_hw_intr_offset 156 | ||
| 518 | |||
| 519 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | ||
| 520 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 | ||
| 521 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 | ||
| 522 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 | ||
| 523 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 | ||
| 524 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 | ||
| 525 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 | ||
| 526 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 | ||
| 527 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 | ||
| 528 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 | ||
| 529 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 | ||
| 530 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 | ||
| 531 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 | ||
| 532 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 | ||
| 533 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 | ||
| 534 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 | ||
| 535 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 | ||
| 536 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 | ||
| 537 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 | ||
| 538 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 | ||
| 539 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 | ||
| 540 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 | ||
| 541 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 | ||
| 542 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 | ||
| 543 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 | ||
| 544 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 | ||
| 545 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 | ||
| 546 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 | ||
| 547 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 | ||
| 548 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 | ||
| 549 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 | ||
| 550 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 | ||
| 551 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 | ||
| 552 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 | ||
| 553 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 | ||
| 554 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 | ||
| 555 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 | ||
| 556 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 | ||
| 557 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 | ||
| 558 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 | ||
| 559 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 | ||
| 560 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 | ||
| 561 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 | ||
| 562 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 | ||
| 563 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 | ||
| 564 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 | ||
| 565 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 | ||
| 566 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 | ||
| 567 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 | ||
| 568 | #define reg_iop_sw_spu_rw_mpu_intr_offset 160 | ||
| 569 | |||
| 570 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | ||
| 571 | #define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 | ||
| 572 | #define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 | ||
| 573 | #define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 | ||
| 574 | #define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 | ||
| 575 | #define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 | ||
| 576 | #define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 | ||
| 577 | #define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 | ||
| 578 | #define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 | ||
| 579 | #define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 | ||
| 580 | #define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 | ||
| 581 | #define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 | ||
| 582 | #define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 | ||
| 583 | #define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 | ||
| 584 | #define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 | ||
| 585 | #define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 | ||
| 586 | #define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 | ||
| 587 | #define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 | ||
| 588 | #define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 | ||
| 589 | #define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 | ||
| 590 | #define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 | ||
| 591 | #define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 | ||
| 592 | #define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 | ||
| 593 | #define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 | ||
| 594 | #define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 | ||
| 595 | #define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 | ||
| 596 | #define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 | ||
| 597 | #define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 | ||
| 598 | #define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 | ||
| 599 | #define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 | ||
| 600 | #define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 | ||
| 601 | #define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 | ||
| 602 | #define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 | ||
| 603 | #define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 | ||
| 604 | #define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 | ||
| 605 | #define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 | ||
| 606 | #define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 | ||
| 607 | #define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 | ||
| 608 | #define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 | ||
| 609 | #define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 | ||
| 610 | #define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 | ||
| 611 | #define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 | ||
| 612 | #define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 | ||
| 613 | #define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 | ||
| 614 | #define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 | ||
| 615 | #define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 | ||
| 616 | #define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 | ||
| 617 | #define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 | ||
| 618 | #define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 | ||
| 619 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 | ||
| 620 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 | ||
| 621 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 | ||
| 622 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 | ||
| 623 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 | ||
| 624 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 | ||
| 625 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 | ||
| 626 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 | ||
| 627 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 | ||
| 628 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 | ||
| 629 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 | ||
| 630 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 | ||
| 631 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 | ||
| 632 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 | ||
| 633 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 | ||
| 634 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 | ||
| 635 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 | ||
| 636 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 | ||
| 637 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 | ||
| 638 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 | ||
| 639 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 | ||
| 640 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 | ||
| 641 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 | ||
| 642 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 | ||
| 643 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 | ||
| 644 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 | ||
| 645 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 | ||
| 646 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 | ||
| 647 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 | ||
| 648 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 | ||
| 649 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 | ||
| 650 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 | ||
| 651 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 | ||
| 652 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 | ||
| 653 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 | ||
| 654 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 | ||
| 655 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 | ||
| 656 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 | ||
| 657 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 | ||
| 658 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 | ||
| 659 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 | ||
| 660 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 | ||
| 661 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 | ||
| 662 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 | ||
| 663 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 | ||
| 664 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 | ||
| 665 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 | ||
| 666 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 | ||
| 667 | #define reg_iop_sw_spu_r_mpu_intr_offset 164 | ||
| 668 | |||
| 669 | |||
| 670 | /* Constants */ | ||
| 671 | #define regk_iop_sw_spu_copy 0x00000000 | ||
| 672 | #define regk_iop_sw_spu_no 0x00000000 | ||
| 673 | #define regk_iop_sw_spu_nop 0x00000000 | ||
| 674 | #define regk_iop_sw_spu_rd 0x00000002 | ||
| 675 | #define regk_iop_sw_spu_reg_copy 0x00000001 | ||
| 676 | #define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 | ||
| 677 | #define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 | ||
| 678 | #define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 | ||
| 679 | #define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 | ||
| 680 | #define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 | ||
| 681 | #define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 | ||
| 682 | #define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 | ||
| 683 | #define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 | ||
| 684 | #define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 | ||
| 685 | #define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 686 | #define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 687 | #define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 | ||
| 688 | #define regk_iop_sw_spu_set 0x00000001 | ||
| 689 | #define regk_iop_sw_spu_wr 0x00000003 | ||
| 690 | #define regk_iop_sw_spu_yes 0x00000001 | ||
| 691 | #endif /* __iop_sw_spu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h deleted file mode 100644 index 7129a9a4bedc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h +++ /dev/null | |||
| @@ -1,237 +0,0 @@ | |||
| 1 | #ifndef __iop_timer_grp_defs_asm_h | ||
| 2 | #define __iop_timer_grp_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_timer_grp.r | ||
| 7 | * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r | ||
| 11 | * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_cfg, scope iop_timer_grp, type rw */ | ||
| 57 | #define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0 | ||
| 58 | #define reg_iop_timer_grp_rw_cfg___clk_src___width 1 | ||
| 59 | #define reg_iop_timer_grp_rw_cfg___clk_src___bit 0 | ||
| 60 | #define reg_iop_timer_grp_rw_cfg___trig___lsb 1 | ||
| 61 | #define reg_iop_timer_grp_rw_cfg___trig___width 2 | ||
| 62 | #define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3 | ||
| 63 | #define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8 | ||
| 64 | #define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11 | ||
| 65 | #define reg_iop_timer_grp_rw_cfg___clk_div___width 8 | ||
| 66 | #define reg_iop_timer_grp_rw_cfg_offset 0 | ||
| 67 | |||
| 68 | /* Register rw_half_period, scope iop_timer_grp, type rw */ | ||
| 69 | #define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0 | ||
| 70 | #define reg_iop_timer_grp_rw_half_period___quota_lo___width 15 | ||
| 71 | #define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15 | ||
| 72 | #define reg_iop_timer_grp_rw_half_period___quota_hi___width 15 | ||
| 73 | #define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30 | ||
| 74 | #define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1 | ||
| 75 | #define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30 | ||
| 76 | #define reg_iop_timer_grp_rw_half_period_offset 4 | ||
| 77 | |||
| 78 | /* Register rw_half_period_len, scope iop_timer_grp, type rw */ | ||
| 79 | #define reg_iop_timer_grp_rw_half_period_len_offset 8 | ||
| 80 | |||
| 81 | #define STRIDE_iop_timer_grp_rw_tmr_cfg 4 | ||
| 82 | /* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ | ||
| 83 | #define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0 | ||
| 84 | #define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3 | ||
| 85 | #define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3 | ||
| 86 | #define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2 | ||
| 87 | #define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5 | ||
| 88 | #define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2 | ||
| 89 | #define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7 | ||
| 90 | #define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1 | ||
| 91 | #define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7 | ||
| 92 | #define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8 | ||
| 93 | #define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2 | ||
| 94 | #define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10 | ||
| 95 | #define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1 | ||
| 96 | #define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10 | ||
| 97 | #define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11 | ||
| 98 | #define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2 | ||
| 99 | #define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13 | ||
| 100 | #define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2 | ||
| 101 | #define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15 | ||
| 102 | #define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1 | ||
| 103 | #define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15 | ||
| 104 | #define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16 | ||
| 105 | #define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1 | ||
| 106 | #define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16 | ||
| 107 | #define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17 | ||
| 108 | #define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1 | ||
| 109 | #define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17 | ||
| 110 | #define reg_iop_timer_grp_rw_tmr_cfg_offset 12 | ||
| 111 | |||
| 112 | #define STRIDE_iop_timer_grp_rw_tmr_len 4 | ||
| 113 | /* Register rw_tmr_len, scope iop_timer_grp, type rw */ | ||
| 114 | #define reg_iop_timer_grp_rw_tmr_len___val___lsb 0 | ||
| 115 | #define reg_iop_timer_grp_rw_tmr_len___val___width 16 | ||
| 116 | #define reg_iop_timer_grp_rw_tmr_len_offset 44 | ||
| 117 | |||
| 118 | /* Register rw_cmd, scope iop_timer_grp, type rw */ | ||
| 119 | #define reg_iop_timer_grp_rw_cmd___rst___lsb 0 | ||
| 120 | #define reg_iop_timer_grp_rw_cmd___rst___width 4 | ||
| 121 | #define reg_iop_timer_grp_rw_cmd___en___lsb 4 | ||
| 122 | #define reg_iop_timer_grp_rw_cmd___en___width 4 | ||
| 123 | #define reg_iop_timer_grp_rw_cmd___dis___lsb 8 | ||
| 124 | #define reg_iop_timer_grp_rw_cmd___dis___width 4 | ||
| 125 | #define reg_iop_timer_grp_rw_cmd___strb___lsb 12 | ||
| 126 | #define reg_iop_timer_grp_rw_cmd___strb___width 4 | ||
| 127 | #define reg_iop_timer_grp_rw_cmd_offset 60 | ||
| 128 | |||
| 129 | /* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ | ||
| 130 | #define reg_iop_timer_grp_r_clk_gen_cnt_offset 64 | ||
| 131 | |||
| 132 | #define STRIDE_iop_timer_grp_rs_tmr_cnt 8 | ||
| 133 | /* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ | ||
| 134 | #define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0 | ||
| 135 | #define reg_iop_timer_grp_rs_tmr_cnt___val___width 16 | ||
| 136 | #define reg_iop_timer_grp_rs_tmr_cnt_offset 68 | ||
| 137 | |||
| 138 | #define STRIDE_iop_timer_grp_r_tmr_cnt 8 | ||
| 139 | /* Register r_tmr_cnt, scope iop_timer_grp, type r */ | ||
| 140 | #define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0 | ||
| 141 | #define reg_iop_timer_grp_r_tmr_cnt___val___width 16 | ||
| 142 | #define reg_iop_timer_grp_r_tmr_cnt_offset 72 | ||
| 143 | |||
| 144 | /* Register rw_intr_mask, scope iop_timer_grp, type rw */ | ||
| 145 | #define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0 | ||
| 146 | #define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1 | ||
| 147 | #define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0 | ||
| 148 | #define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1 | ||
| 149 | #define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1 | ||
| 150 | #define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1 | ||
| 151 | #define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2 | ||
| 152 | #define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1 | ||
| 153 | #define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2 | ||
| 154 | #define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3 | ||
| 155 | #define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1 | ||
| 156 | #define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3 | ||
| 157 | #define reg_iop_timer_grp_rw_intr_mask_offset 100 | ||
| 158 | |||
| 159 | /* Register rw_ack_intr, scope iop_timer_grp, type rw */ | ||
| 160 | #define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0 | ||
| 161 | #define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1 | ||
| 162 | #define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0 | ||
| 163 | #define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1 | ||
| 164 | #define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1 | ||
| 165 | #define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1 | ||
| 166 | #define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2 | ||
| 167 | #define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1 | ||
| 168 | #define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2 | ||
| 169 | #define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3 | ||
| 170 | #define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1 | ||
| 171 | #define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3 | ||
| 172 | #define reg_iop_timer_grp_rw_ack_intr_offset 104 | ||
| 173 | |||
| 174 | /* Register r_intr, scope iop_timer_grp, type r */ | ||
| 175 | #define reg_iop_timer_grp_r_intr___tmr0___lsb 0 | ||
| 176 | #define reg_iop_timer_grp_r_intr___tmr0___width 1 | ||
| 177 | #define reg_iop_timer_grp_r_intr___tmr0___bit 0 | ||
| 178 | #define reg_iop_timer_grp_r_intr___tmr1___lsb 1 | ||
| 179 | #define reg_iop_timer_grp_r_intr___tmr1___width 1 | ||
| 180 | #define reg_iop_timer_grp_r_intr___tmr1___bit 1 | ||
| 181 | #define reg_iop_timer_grp_r_intr___tmr2___lsb 2 | ||
| 182 | #define reg_iop_timer_grp_r_intr___tmr2___width 1 | ||
| 183 | #define reg_iop_timer_grp_r_intr___tmr2___bit 2 | ||
| 184 | #define reg_iop_timer_grp_r_intr___tmr3___lsb 3 | ||
| 185 | #define reg_iop_timer_grp_r_intr___tmr3___width 1 | ||
| 186 | #define reg_iop_timer_grp_r_intr___tmr3___bit 3 | ||
| 187 | #define reg_iop_timer_grp_r_intr_offset 108 | ||
| 188 | |||
| 189 | /* Register r_masked_intr, scope iop_timer_grp, type r */ | ||
| 190 | #define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0 | ||
| 191 | #define reg_iop_timer_grp_r_masked_intr___tmr0___width 1 | ||
| 192 | #define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0 | ||
| 193 | #define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1 | ||
| 194 | #define reg_iop_timer_grp_r_masked_intr___tmr1___width 1 | ||
| 195 | #define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1 | ||
| 196 | #define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2 | ||
| 197 | #define reg_iop_timer_grp_r_masked_intr___tmr2___width 1 | ||
| 198 | #define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2 | ||
| 199 | #define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3 | ||
| 200 | #define reg_iop_timer_grp_r_masked_intr___tmr3___width 1 | ||
| 201 | #define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3 | ||
| 202 | #define reg_iop_timer_grp_r_masked_intr_offset 112 | ||
| 203 | |||
| 204 | |||
| 205 | /* Constants */ | ||
| 206 | #define regk_iop_timer_grp_clk200 0x00000000 | ||
| 207 | #define regk_iop_timer_grp_clk_gen 0x00000002 | ||
| 208 | #define regk_iop_timer_grp_complete 0x00000002 | ||
| 209 | #define regk_iop_timer_grp_div_clk200 0x00000001 | ||
| 210 | #define regk_iop_timer_grp_div_clk_gen 0x00000003 | ||
| 211 | #define regk_iop_timer_grp_ext 0x00000001 | ||
| 212 | #define regk_iop_timer_grp_hi 0x00000000 | ||
| 213 | #define regk_iop_timer_grp_long_period 0x00000001 | ||
| 214 | #define regk_iop_timer_grp_neg 0x00000002 | ||
| 215 | #define regk_iop_timer_grp_no 0x00000000 | ||
| 216 | #define regk_iop_timer_grp_once 0x00000003 | ||
| 217 | #define regk_iop_timer_grp_pause 0x00000001 | ||
| 218 | #define regk_iop_timer_grp_pos 0x00000001 | ||
| 219 | #define regk_iop_timer_grp_pos_neg 0x00000003 | ||
| 220 | #define regk_iop_timer_grp_pulse 0x00000000 | ||
| 221 | #define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004 | ||
| 222 | #define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004 | ||
| 223 | #define regk_iop_timer_grp_rw_cfg_default 0x00000002 | ||
| 224 | #define regk_iop_timer_grp_rw_intr_mask_default 0x00000000 | ||
| 225 | #define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000 | ||
| 226 | #define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900 | ||
| 227 | #define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200 | ||
| 228 | #define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00 | ||
| 229 | #define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004 | ||
| 230 | #define regk_iop_timer_grp_rw_tmr_len_default 0x00000000 | ||
| 231 | #define regk_iop_timer_grp_rw_tmr_len_size 0x00000004 | ||
| 232 | #define regk_iop_timer_grp_short_period 0x00000000 | ||
| 233 | #define regk_iop_timer_grp_stop 0x00000000 | ||
| 234 | #define regk_iop_timer_grp_tmr 0x00000004 | ||
| 235 | #define regk_iop_timer_grp_toggle 0x00000001 | ||
| 236 | #define regk_iop_timer_grp_yes 0x00000001 | ||
| 237 | #endif /* __iop_timer_grp_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h deleted file mode 100644 index 1005d9db80dc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h +++ /dev/null | |||
| @@ -1,157 +0,0 @@ | |||
| 1 | #ifndef __iop_trigger_grp_defs_asm_h | ||
| 2 | #define __iop_trigger_grp_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_trigger_grp.r | ||
| 7 | * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r | ||
| 11 | * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #define STRIDE_iop_trigger_grp_rw_cfg 4 | ||
| 57 | /* Register rw_cfg, scope iop_trigger_grp, type rw */ | ||
| 58 | #define reg_iop_trigger_grp_rw_cfg___action___lsb 0 | ||
| 59 | #define reg_iop_trigger_grp_rw_cfg___action___width 2 | ||
| 60 | #define reg_iop_trigger_grp_rw_cfg___once___lsb 2 | ||
| 61 | #define reg_iop_trigger_grp_rw_cfg___once___width 1 | ||
| 62 | #define reg_iop_trigger_grp_rw_cfg___once___bit 2 | ||
| 63 | #define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 | ||
| 64 | #define reg_iop_trigger_grp_rw_cfg___trig___width 3 | ||
| 65 | #define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 | ||
| 66 | #define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 | ||
| 67 | #define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 | ||
| 68 | #define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 | ||
| 69 | #define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 | ||
| 70 | #define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 | ||
| 71 | #define reg_iop_trigger_grp_rw_cfg_offset 0 | ||
| 72 | |||
| 73 | /* Register rw_cmd, scope iop_trigger_grp, type rw */ | ||
| 74 | #define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 | ||
| 75 | #define reg_iop_trigger_grp_rw_cmd___dis___width 4 | ||
| 76 | #define reg_iop_trigger_grp_rw_cmd___en___lsb 4 | ||
| 77 | #define reg_iop_trigger_grp_rw_cmd___en___width 4 | ||
| 78 | #define reg_iop_trigger_grp_rw_cmd_offset 16 | ||
| 79 | |||
| 80 | /* Register rw_intr_mask, scope iop_trigger_grp, type rw */ | ||
| 81 | #define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 | ||
| 82 | #define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 | ||
| 83 | #define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 | ||
| 84 | #define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 | ||
| 85 | #define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 | ||
| 86 | #define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 | ||
| 87 | #define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 | ||
| 88 | #define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 | ||
| 89 | #define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 | ||
| 90 | #define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 | ||
| 91 | #define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 | ||
| 92 | #define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 | ||
| 93 | #define reg_iop_trigger_grp_rw_intr_mask_offset 20 | ||
| 94 | |||
| 95 | /* Register rw_ack_intr, scope iop_trigger_grp, type rw */ | ||
| 96 | #define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 | ||
| 97 | #define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 | ||
| 98 | #define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 | ||
| 99 | #define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 | ||
| 100 | #define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 | ||
| 101 | #define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 | ||
| 102 | #define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 | ||
| 103 | #define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 | ||
| 104 | #define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 | ||
| 105 | #define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 | ||
| 106 | #define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 | ||
| 107 | #define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 | ||
| 108 | #define reg_iop_trigger_grp_rw_ack_intr_offset 24 | ||
| 109 | |||
| 110 | /* Register r_intr, scope iop_trigger_grp, type r */ | ||
| 111 | #define reg_iop_trigger_grp_r_intr___trig0___lsb 0 | ||
| 112 | #define reg_iop_trigger_grp_r_intr___trig0___width 1 | ||
| 113 | #define reg_iop_trigger_grp_r_intr___trig0___bit 0 | ||
| 114 | #define reg_iop_trigger_grp_r_intr___trig1___lsb 1 | ||
| 115 | #define reg_iop_trigger_grp_r_intr___trig1___width 1 | ||
| 116 | #define reg_iop_trigger_grp_r_intr___trig1___bit 1 | ||
| 117 | #define reg_iop_trigger_grp_r_intr___trig2___lsb 2 | ||
| 118 | #define reg_iop_trigger_grp_r_intr___trig2___width 1 | ||
| 119 | #define reg_iop_trigger_grp_r_intr___trig2___bit 2 | ||
| 120 | #define reg_iop_trigger_grp_r_intr___trig3___lsb 3 | ||
| 121 | #define reg_iop_trigger_grp_r_intr___trig3___width 1 | ||
| 122 | #define reg_iop_trigger_grp_r_intr___trig3___bit 3 | ||
| 123 | #define reg_iop_trigger_grp_r_intr_offset 28 | ||
| 124 | |||
| 125 | /* Register r_masked_intr, scope iop_trigger_grp, type r */ | ||
| 126 | #define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 | ||
| 127 | #define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 | ||
| 128 | #define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 | ||
| 129 | #define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 | ||
| 130 | #define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 | ||
| 131 | #define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 | ||
| 132 | #define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 | ||
| 133 | #define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 | ||
| 134 | #define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 | ||
| 135 | #define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 | ||
| 136 | #define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 | ||
| 137 | #define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 | ||
| 138 | #define reg_iop_trigger_grp_r_masked_intr_offset 32 | ||
| 139 | |||
| 140 | |||
| 141 | /* Constants */ | ||
| 142 | #define regk_iop_trigger_grp_fall 0x00000002 | ||
| 143 | #define regk_iop_trigger_grp_fall_lo 0x00000006 | ||
| 144 | #define regk_iop_trigger_grp_no 0x00000000 | ||
| 145 | #define regk_iop_trigger_grp_off 0x00000000 | ||
| 146 | #define regk_iop_trigger_grp_pulse 0x00000000 | ||
| 147 | #define regk_iop_trigger_grp_rise 0x00000001 | ||
| 148 | #define regk_iop_trigger_grp_rise_fall 0x00000003 | ||
| 149 | #define regk_iop_trigger_grp_rise_fall_hi 0x00000007 | ||
| 150 | #define regk_iop_trigger_grp_rise_fall_lo 0x00000004 | ||
| 151 | #define regk_iop_trigger_grp_rise_hi 0x00000005 | ||
| 152 | #define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 | ||
| 153 | #define regk_iop_trigger_grp_rw_cfg_size 0x00000004 | ||
| 154 | #define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 | ||
| 155 | #define regk_iop_trigger_grp_toggle 0x00000003 | ||
| 156 | #define regk_iop_trigger_grp_yes 0x00000001 | ||
| 157 | #endif /* __iop_trigger_grp_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index e13feb20a7e3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | #ifndef __iop_version_defs_asm_h | ||
| 2 | #define __iop_version_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_version.r | ||
| 7 | * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:44 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r | ||
| 11 | * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register r_version, scope iop_version, type r */ | ||
| 57 | #define reg_iop_version_r_version___nr___lsb 0 | ||
| 58 | #define reg_iop_version_r_version___nr___width 8 | ||
| 59 | #define reg_iop_version_r_version_offset 0 | ||
| 60 | |||
| 61 | |||
| 62 | /* Constants */ | ||
| 63 | #define regk_iop_version_v1_0 0x00000001 | ||
| 64 | #endif /* __iop_version_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h deleted file mode 100644 index 90e4785b6474..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h +++ /dev/null | |||
| @@ -1,232 +0,0 @@ | |||
| 1 | #ifndef __iop_crc_par_defs_h | ||
| 2 | #define __iop_crc_par_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_crc_par.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r | ||
| 11 | * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_crc_par */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope iop_crc_par, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int mode : 1; | ||
| 90 | unsigned int crc_out : 1; | ||
| 91 | unsigned int rev_out : 1; | ||
| 92 | unsigned int inv_out : 1; | ||
| 93 | unsigned int trig : 2; | ||
| 94 | unsigned int poly : 3; | ||
| 95 | unsigned int dummy1 : 23; | ||
| 96 | } reg_iop_crc_par_rw_cfg; | ||
| 97 | #define REG_RD_ADDR_iop_crc_par_rw_cfg 0 | ||
| 98 | #define REG_WR_ADDR_iop_crc_par_rw_cfg 0 | ||
| 99 | |||
| 100 | /* Register rw_init_crc, scope iop_crc_par, type rw */ | ||
| 101 | typedef unsigned int reg_iop_crc_par_rw_init_crc; | ||
| 102 | #define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 | ||
| 103 | #define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 | ||
| 104 | |||
| 105 | /* Register rw_correct_crc, scope iop_crc_par, type rw */ | ||
| 106 | typedef unsigned int reg_iop_crc_par_rw_correct_crc; | ||
| 107 | #define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 | ||
| 108 | #define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 | ||
| 109 | |||
| 110 | /* Register rw_ctrl, scope iop_crc_par, type rw */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int en : 1; | ||
| 113 | unsigned int dummy1 : 31; | ||
| 114 | } reg_iop_crc_par_rw_ctrl; | ||
| 115 | #define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 | ||
| 116 | #define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 | ||
| 117 | |||
| 118 | /* Register rw_set_last, scope iop_crc_par, type rw */ | ||
| 119 | typedef struct { | ||
| 120 | unsigned int tr_dif : 1; | ||
| 121 | unsigned int dummy1 : 31; | ||
| 122 | } reg_iop_crc_par_rw_set_last; | ||
| 123 | #define REG_RD_ADDR_iop_crc_par_rw_set_last 16 | ||
| 124 | #define REG_WR_ADDR_iop_crc_par_rw_set_last 16 | ||
| 125 | |||
| 126 | /* Register rw_wr1byte, scope iop_crc_par, type rw */ | ||
| 127 | typedef struct { | ||
| 128 | unsigned int data : 8; | ||
| 129 | unsigned int dummy1 : 24; | ||
| 130 | } reg_iop_crc_par_rw_wr1byte; | ||
| 131 | #define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 | ||
| 132 | #define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 | ||
| 133 | |||
| 134 | /* Register rw_wr2byte, scope iop_crc_par, type rw */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int data : 16; | ||
| 137 | unsigned int dummy1 : 16; | ||
| 138 | } reg_iop_crc_par_rw_wr2byte; | ||
| 139 | #define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 | ||
| 140 | #define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 | ||
| 141 | |||
| 142 | /* Register rw_wr3byte, scope iop_crc_par, type rw */ | ||
| 143 | typedef struct { | ||
| 144 | unsigned int data : 24; | ||
| 145 | unsigned int dummy1 : 8; | ||
| 146 | } reg_iop_crc_par_rw_wr3byte; | ||
| 147 | #define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 | ||
| 148 | #define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 | ||
| 149 | |||
| 150 | /* Register rw_wr4byte, scope iop_crc_par, type rw */ | ||
| 151 | typedef struct { | ||
| 152 | unsigned int data : 32; | ||
| 153 | } reg_iop_crc_par_rw_wr4byte; | ||
| 154 | #define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 | ||
| 155 | #define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 | ||
| 156 | |||
| 157 | /* Register rw_wr1byte_last, scope iop_crc_par, type rw */ | ||
| 158 | typedef struct { | ||
| 159 | unsigned int data : 8; | ||
| 160 | unsigned int dummy1 : 24; | ||
| 161 | } reg_iop_crc_par_rw_wr1byte_last; | ||
| 162 | #define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 | ||
| 163 | #define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 | ||
| 164 | |||
| 165 | /* Register rw_wr2byte_last, scope iop_crc_par, type rw */ | ||
| 166 | typedef struct { | ||
| 167 | unsigned int data : 16; | ||
| 168 | unsigned int dummy1 : 16; | ||
| 169 | } reg_iop_crc_par_rw_wr2byte_last; | ||
| 170 | #define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 | ||
| 171 | #define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 | ||
| 172 | |||
| 173 | /* Register rw_wr3byte_last, scope iop_crc_par, type rw */ | ||
| 174 | typedef struct { | ||
| 175 | unsigned int data : 24; | ||
| 176 | unsigned int dummy1 : 8; | ||
| 177 | } reg_iop_crc_par_rw_wr3byte_last; | ||
| 178 | #define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 | ||
| 179 | #define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 | ||
| 180 | |||
| 181 | /* Register rw_wr4byte_last, scope iop_crc_par, type rw */ | ||
| 182 | typedef struct { | ||
| 183 | unsigned int data : 32; | ||
| 184 | } reg_iop_crc_par_rw_wr4byte_last; | ||
| 185 | #define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 | ||
| 186 | #define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 | ||
| 187 | |||
| 188 | /* Register r_stat, scope iop_crc_par, type r */ | ||
| 189 | typedef struct { | ||
| 190 | unsigned int err : 1; | ||
| 191 | unsigned int busy : 1; | ||
| 192 | unsigned int dummy1 : 30; | ||
| 193 | } reg_iop_crc_par_r_stat; | ||
| 194 | #define REG_RD_ADDR_iop_crc_par_r_stat 52 | ||
| 195 | |||
| 196 | /* Register r_sh_reg, scope iop_crc_par, type r */ | ||
| 197 | typedef unsigned int reg_iop_crc_par_r_sh_reg; | ||
| 198 | #define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 | ||
| 199 | |||
| 200 | /* Register r_crc, scope iop_crc_par, type r */ | ||
| 201 | typedef unsigned int reg_iop_crc_par_r_crc; | ||
| 202 | #define REG_RD_ADDR_iop_crc_par_r_crc 60 | ||
| 203 | |||
| 204 | /* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int last : 2; | ||
| 207 | unsigned int dummy1 : 30; | ||
| 208 | } reg_iop_crc_par_rw_strb_rec_dif_in; | ||
| 209 | #define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 | ||
| 210 | #define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 | ||
| 211 | |||
| 212 | |||
| 213 | /* Constants */ | ||
| 214 | enum { | ||
| 215 | regk_iop_crc_par_calc = 0x00000001, | ||
| 216 | regk_iop_crc_par_ccitt = 0x00000002, | ||
| 217 | regk_iop_crc_par_check = 0x00000000, | ||
| 218 | regk_iop_crc_par_crc16 = 0x00000001, | ||
| 219 | regk_iop_crc_par_crc32 = 0x00000000, | ||
| 220 | regk_iop_crc_par_crc5 = 0x00000003, | ||
| 221 | regk_iop_crc_par_crc5_11 = 0x00000004, | ||
| 222 | regk_iop_crc_par_dif_in = 0x00000002, | ||
| 223 | regk_iop_crc_par_hi = 0x00000000, | ||
| 224 | regk_iop_crc_par_neg = 0x00000002, | ||
| 225 | regk_iop_crc_par_no = 0x00000000, | ||
| 226 | regk_iop_crc_par_pos = 0x00000001, | ||
| 227 | regk_iop_crc_par_pos_neg = 0x00000003, | ||
| 228 | regk_iop_crc_par_rw_cfg_default = 0x00000000, | ||
| 229 | regk_iop_crc_par_rw_ctrl_default = 0x00000000, | ||
| 230 | regk_iop_crc_par_yes = 0x00000001 | ||
| 231 | }; | ||
| 232 | #endif /* __iop_crc_par_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h deleted file mode 100644 index 76aec6e37f3e..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h +++ /dev/null | |||
| @@ -1,325 +0,0 @@ | |||
| 1 | #ifndef __iop_dmc_in_defs_h | ||
| 2 | #define __iop_dmc_in_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_dmc_in.r | ||
| 7 | * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r | ||
| 11 | * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_dmc_in */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope iop_dmc_in, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int sth_intr : 3; | ||
| 90 | unsigned int last_dis_dif : 1; | ||
| 91 | unsigned int dummy1 : 28; | ||
| 92 | } reg_iop_dmc_in_rw_cfg; | ||
| 93 | #define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 | ||
| 94 | #define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 | ||
| 95 | |||
| 96 | /* Register rw_ctrl, scope iop_dmc_in, type rw */ | ||
| 97 | typedef struct { | ||
| 98 | unsigned int dif_en : 1; | ||
| 99 | unsigned int dif_dis : 1; | ||
| 100 | unsigned int stream_clr : 1; | ||
| 101 | unsigned int dummy1 : 29; | ||
| 102 | } reg_iop_dmc_in_rw_ctrl; | ||
| 103 | #define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 | ||
| 104 | #define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 | ||
| 105 | |||
| 106 | /* Register r_stat, scope iop_dmc_in, type r */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int dif_en : 1; | ||
| 109 | unsigned int dummy1 : 31; | ||
| 110 | } reg_iop_dmc_in_r_stat; | ||
| 111 | #define REG_RD_ADDR_iop_dmc_in_r_stat 8 | ||
| 112 | |||
| 113 | /* Register rw_stream_cmd, scope iop_dmc_in, type rw */ | ||
| 114 | typedef struct { | ||
| 115 | unsigned int cmd : 10; | ||
| 116 | unsigned int dummy1 : 6; | ||
| 117 | unsigned int n : 8; | ||
| 118 | unsigned int dummy2 : 8; | ||
| 119 | } reg_iop_dmc_in_rw_stream_cmd; | ||
| 120 | #define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 | ||
| 121 | #define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 | ||
| 122 | |||
| 123 | /* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ | ||
| 124 | typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; | ||
| 125 | #define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 | ||
| 126 | #define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 | ||
| 127 | |||
| 128 | /* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ | ||
| 129 | typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; | ||
| 130 | #define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 | ||
| 131 | #define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 | ||
| 132 | |||
| 133 | /* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ | ||
| 134 | typedef struct { | ||
| 135 | unsigned int eop : 1; | ||
| 136 | unsigned int wait : 1; | ||
| 137 | unsigned int keep_md : 1; | ||
| 138 | unsigned int size : 3; | ||
| 139 | unsigned int dummy1 : 26; | ||
| 140 | } reg_iop_dmc_in_rw_stream_ctrl; | ||
| 141 | #define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 | ||
| 142 | #define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 | ||
| 143 | |||
| 144 | /* Register r_stream_stat, scope iop_dmc_in, type r */ | ||
| 145 | typedef struct { | ||
| 146 | unsigned int sth : 7; | ||
| 147 | unsigned int dummy1 : 9; | ||
| 148 | unsigned int full : 1; | ||
| 149 | unsigned int last_pkt : 1; | ||
| 150 | unsigned int data_md_valid : 1; | ||
| 151 | unsigned int ctxt_md_valid : 1; | ||
| 152 | unsigned int group_md_valid : 1; | ||
| 153 | unsigned int stream_busy : 1; | ||
| 154 | unsigned int cmd_rdy : 1; | ||
| 155 | unsigned int dummy2 : 9; | ||
| 156 | } reg_iop_dmc_in_r_stream_stat; | ||
| 157 | #define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 | ||
| 158 | |||
| 159 | /* Register r_data_descr, scope iop_dmc_in, type r */ | ||
| 160 | typedef struct { | ||
| 161 | unsigned int ctrl : 8; | ||
| 162 | unsigned int stat : 8; | ||
| 163 | unsigned int md : 16; | ||
| 164 | } reg_iop_dmc_in_r_data_descr; | ||
| 165 | #define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 | ||
| 166 | |||
| 167 | /* Register r_ctxt_descr, scope iop_dmc_in, type r */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int ctrl : 8; | ||
| 170 | unsigned int stat : 8; | ||
| 171 | unsigned int md0 : 16; | ||
| 172 | } reg_iop_dmc_in_r_ctxt_descr; | ||
| 173 | #define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 | ||
| 174 | |||
| 175 | /* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ | ||
| 176 | typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; | ||
| 177 | #define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 | ||
| 178 | |||
| 179 | /* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ | ||
| 180 | typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; | ||
| 181 | #define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 | ||
| 182 | |||
| 183 | /* Register r_group_descr, scope iop_dmc_in, type r */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int ctrl : 8; | ||
| 186 | unsigned int stat : 8; | ||
| 187 | unsigned int md : 16; | ||
| 188 | } reg_iop_dmc_in_r_group_descr; | ||
| 189 | #define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 | ||
| 190 | |||
| 191 | /* Register rw_data_descr, scope iop_dmc_in, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int dummy1 : 16; | ||
| 194 | unsigned int md : 16; | ||
| 195 | } reg_iop_dmc_in_rw_data_descr; | ||
| 196 | #define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 | ||
| 197 | #define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 | ||
| 198 | |||
| 199 | /* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ | ||
| 200 | typedef struct { | ||
| 201 | unsigned int dummy1 : 16; | ||
| 202 | unsigned int md0 : 16; | ||
| 203 | } reg_iop_dmc_in_rw_ctxt_descr; | ||
| 204 | #define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 | ||
| 205 | #define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 | ||
| 206 | |||
| 207 | /* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ | ||
| 208 | typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; | ||
| 209 | #define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 | ||
| 210 | #define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 | ||
| 211 | |||
| 212 | /* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ | ||
| 213 | typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; | ||
| 214 | #define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 | ||
| 215 | #define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 | ||
| 216 | |||
| 217 | /* Register rw_group_descr, scope iop_dmc_in, type rw */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int dummy1 : 16; | ||
| 220 | unsigned int md : 16; | ||
| 221 | } reg_iop_dmc_in_rw_group_descr; | ||
| 222 | #define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 | ||
| 223 | #define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 | ||
| 224 | |||
| 225 | /* Register rw_intr_mask, scope iop_dmc_in, type rw */ | ||
| 226 | typedef struct { | ||
| 227 | unsigned int data_md : 1; | ||
| 228 | unsigned int ctxt_md : 1; | ||
| 229 | unsigned int group_md : 1; | ||
| 230 | unsigned int cmd_rdy : 1; | ||
| 231 | unsigned int sth : 1; | ||
| 232 | unsigned int full : 1; | ||
| 233 | unsigned int dummy1 : 26; | ||
| 234 | } reg_iop_dmc_in_rw_intr_mask; | ||
| 235 | #define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 | ||
| 236 | #define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 | ||
| 237 | |||
| 238 | /* Register rw_ack_intr, scope iop_dmc_in, type rw */ | ||
| 239 | typedef struct { | ||
| 240 | unsigned int data_md : 1; | ||
| 241 | unsigned int ctxt_md : 1; | ||
| 242 | unsigned int group_md : 1; | ||
| 243 | unsigned int cmd_rdy : 1; | ||
| 244 | unsigned int sth : 1; | ||
| 245 | unsigned int full : 1; | ||
| 246 | unsigned int dummy1 : 26; | ||
| 247 | } reg_iop_dmc_in_rw_ack_intr; | ||
| 248 | #define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 | ||
| 249 | #define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 | ||
| 250 | |||
| 251 | /* Register r_intr, scope iop_dmc_in, type r */ | ||
| 252 | typedef struct { | ||
| 253 | unsigned int data_md : 1; | ||
| 254 | unsigned int ctxt_md : 1; | ||
| 255 | unsigned int group_md : 1; | ||
| 256 | unsigned int cmd_rdy : 1; | ||
| 257 | unsigned int sth : 1; | ||
| 258 | unsigned int full : 1; | ||
| 259 | unsigned int dummy1 : 26; | ||
| 260 | } reg_iop_dmc_in_r_intr; | ||
| 261 | #define REG_RD_ADDR_iop_dmc_in_r_intr 96 | ||
| 262 | |||
| 263 | /* Register r_masked_intr, scope iop_dmc_in, type r */ | ||
| 264 | typedef struct { | ||
| 265 | unsigned int data_md : 1; | ||
| 266 | unsigned int ctxt_md : 1; | ||
| 267 | unsigned int group_md : 1; | ||
| 268 | unsigned int cmd_rdy : 1; | ||
| 269 | unsigned int sth : 1; | ||
| 270 | unsigned int full : 1; | ||
| 271 | unsigned int dummy1 : 26; | ||
| 272 | } reg_iop_dmc_in_r_masked_intr; | ||
| 273 | #define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 | ||
| 274 | |||
| 275 | |||
| 276 | /* Constants */ | ||
| 277 | enum { | ||
| 278 | regk_iop_dmc_in_ack_pkt = 0x00000100, | ||
| 279 | regk_iop_dmc_in_array = 0x00000008, | ||
| 280 | regk_iop_dmc_in_burst = 0x00000020, | ||
| 281 | regk_iop_dmc_in_copy_next = 0x00000010, | ||
| 282 | regk_iop_dmc_in_copy_up = 0x00000020, | ||
| 283 | regk_iop_dmc_in_dis_c = 0x00000010, | ||
| 284 | regk_iop_dmc_in_dis_g = 0x00000020, | ||
| 285 | regk_iop_dmc_in_lim1 = 0x00000000, | ||
| 286 | regk_iop_dmc_in_lim16 = 0x00000004, | ||
| 287 | regk_iop_dmc_in_lim2 = 0x00000001, | ||
| 288 | regk_iop_dmc_in_lim32 = 0x00000005, | ||
| 289 | regk_iop_dmc_in_lim4 = 0x00000002, | ||
| 290 | regk_iop_dmc_in_lim64 = 0x00000006, | ||
| 291 | regk_iop_dmc_in_lim8 = 0x00000003, | ||
| 292 | regk_iop_dmc_in_load_c = 0x00000200, | ||
| 293 | regk_iop_dmc_in_load_c_n = 0x00000280, | ||
| 294 | regk_iop_dmc_in_load_c_next = 0x00000240, | ||
| 295 | regk_iop_dmc_in_load_d = 0x00000140, | ||
| 296 | regk_iop_dmc_in_load_g = 0x00000300, | ||
| 297 | regk_iop_dmc_in_load_g_down = 0x000003c0, | ||
| 298 | regk_iop_dmc_in_load_g_next = 0x00000340, | ||
| 299 | regk_iop_dmc_in_load_g_up = 0x00000380, | ||
| 300 | regk_iop_dmc_in_next_en = 0x00000010, | ||
| 301 | regk_iop_dmc_in_next_pkt = 0x00000010, | ||
| 302 | regk_iop_dmc_in_no = 0x00000000, | ||
| 303 | regk_iop_dmc_in_restore = 0x00000020, | ||
| 304 | regk_iop_dmc_in_rw_cfg_default = 0x00000000, | ||
| 305 | regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, | ||
| 306 | regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, | ||
| 307 | regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, | ||
| 308 | regk_iop_dmc_in_rw_data_descr_default = 0x00000000, | ||
| 309 | regk_iop_dmc_in_rw_group_descr_default = 0x00000000, | ||
| 310 | regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, | ||
| 311 | regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, | ||
| 312 | regk_iop_dmc_in_save_down = 0x00000020, | ||
| 313 | regk_iop_dmc_in_save_up = 0x00000020, | ||
| 314 | regk_iop_dmc_in_set_reg = 0x00000050, | ||
| 315 | regk_iop_dmc_in_set_w_size1 = 0x00000190, | ||
| 316 | regk_iop_dmc_in_set_w_size2 = 0x000001a0, | ||
| 317 | regk_iop_dmc_in_set_w_size4 = 0x000001c0, | ||
| 318 | regk_iop_dmc_in_store_c = 0x00000002, | ||
| 319 | regk_iop_dmc_in_store_descr = 0x00000000, | ||
| 320 | regk_iop_dmc_in_store_g = 0x00000004, | ||
| 321 | regk_iop_dmc_in_store_md = 0x00000001, | ||
| 322 | regk_iop_dmc_in_update_down = 0x00000020, | ||
| 323 | regk_iop_dmc_in_yes = 0x00000001 | ||
| 324 | }; | ||
| 325 | #endif /* __iop_dmc_in_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h deleted file mode 100644 index 938a0d4c4604..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h +++ /dev/null | |||
| @@ -1,326 +0,0 @@ | |||
| 1 | #ifndef __iop_dmc_out_defs_h | ||
| 2 | #define __iop_dmc_out_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_dmc_out.r | ||
| 7 | * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r | ||
| 11 | * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_dmc_out */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope iop_dmc_out, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int trf_lim : 16; | ||
| 90 | unsigned int last_at_trf_lim : 1; | ||
| 91 | unsigned int dth_intr : 3; | ||
| 92 | unsigned int dummy1 : 12; | ||
| 93 | } reg_iop_dmc_out_rw_cfg; | ||
| 94 | #define REG_RD_ADDR_iop_dmc_out_rw_cfg 0 | ||
| 95 | #define REG_WR_ADDR_iop_dmc_out_rw_cfg 0 | ||
| 96 | |||
| 97 | /* Register rw_ctrl, scope iop_dmc_out, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int dif_en : 1; | ||
| 100 | unsigned int dif_dis : 1; | ||
| 101 | unsigned int dummy1 : 30; | ||
| 102 | } reg_iop_dmc_out_rw_ctrl; | ||
| 103 | #define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4 | ||
| 104 | #define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4 | ||
| 105 | |||
| 106 | /* Register r_stat, scope iop_dmc_out, type r */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int dif_en : 1; | ||
| 109 | unsigned int dummy1 : 31; | ||
| 110 | } reg_iop_dmc_out_r_stat; | ||
| 111 | #define REG_RD_ADDR_iop_dmc_out_r_stat 8 | ||
| 112 | |||
| 113 | /* Register rw_stream_cmd, scope iop_dmc_out, type rw */ | ||
| 114 | typedef struct { | ||
| 115 | unsigned int cmd : 10; | ||
| 116 | unsigned int dummy1 : 6; | ||
| 117 | unsigned int n : 8; | ||
| 118 | unsigned int dummy2 : 8; | ||
| 119 | } reg_iop_dmc_out_rw_stream_cmd; | ||
| 120 | #define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12 | ||
| 121 | #define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12 | ||
| 122 | |||
| 123 | /* Register rs_stream_data, scope iop_dmc_out, type rs */ | ||
| 124 | typedef unsigned int reg_iop_dmc_out_rs_stream_data; | ||
| 125 | #define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16 | ||
| 126 | |||
| 127 | /* Register r_stream_data, scope iop_dmc_out, type r */ | ||
| 128 | typedef unsigned int reg_iop_dmc_out_r_stream_data; | ||
| 129 | #define REG_RD_ADDR_iop_dmc_out_r_stream_data 20 | ||
| 130 | |||
| 131 | /* Register r_stream_stat, scope iop_dmc_out, type r */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int dth : 7; | ||
| 134 | unsigned int dummy1 : 9; | ||
| 135 | unsigned int dv : 1; | ||
| 136 | unsigned int all_avail : 1; | ||
| 137 | unsigned int last : 1; | ||
| 138 | unsigned int size : 3; | ||
| 139 | unsigned int data_md_valid : 1; | ||
| 140 | unsigned int ctxt_md_valid : 1; | ||
| 141 | unsigned int group_md_valid : 1; | ||
| 142 | unsigned int stream_busy : 1; | ||
| 143 | unsigned int cmd_rdy : 1; | ||
| 144 | unsigned int cmd_rq : 1; | ||
| 145 | unsigned int dummy2 : 4; | ||
| 146 | } reg_iop_dmc_out_r_stream_stat; | ||
| 147 | #define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24 | ||
| 148 | |||
| 149 | /* Register r_data_descr, scope iop_dmc_out, type r */ | ||
| 150 | typedef struct { | ||
| 151 | unsigned int ctrl : 8; | ||
| 152 | unsigned int stat : 8; | ||
| 153 | unsigned int md : 16; | ||
| 154 | } reg_iop_dmc_out_r_data_descr; | ||
| 155 | #define REG_RD_ADDR_iop_dmc_out_r_data_descr 28 | ||
| 156 | |||
| 157 | /* Register r_ctxt_descr, scope iop_dmc_out, type r */ | ||
| 158 | typedef struct { | ||
| 159 | unsigned int ctrl : 8; | ||
| 160 | unsigned int stat : 8; | ||
| 161 | unsigned int md0 : 16; | ||
| 162 | } reg_iop_dmc_out_r_ctxt_descr; | ||
| 163 | #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32 | ||
| 164 | |||
| 165 | /* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ | ||
| 166 | typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1; | ||
| 167 | #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36 | ||
| 168 | |||
| 169 | /* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ | ||
| 170 | typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2; | ||
| 171 | #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40 | ||
| 172 | |||
| 173 | /* Register r_group_descr, scope iop_dmc_out, type r */ | ||
| 174 | typedef struct { | ||
| 175 | unsigned int ctrl : 8; | ||
| 176 | unsigned int stat : 8; | ||
| 177 | unsigned int md : 16; | ||
| 178 | } reg_iop_dmc_out_r_group_descr; | ||
| 179 | #define REG_RD_ADDR_iop_dmc_out_r_group_descr 52 | ||
| 180 | |||
| 181 | /* Register rw_data_descr, scope iop_dmc_out, type rw */ | ||
| 182 | typedef struct { | ||
| 183 | unsigned int dummy1 : 16; | ||
| 184 | unsigned int md : 16; | ||
| 185 | } reg_iop_dmc_out_rw_data_descr; | ||
| 186 | #define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56 | ||
| 187 | #define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56 | ||
| 188 | |||
| 189 | /* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ | ||
| 190 | typedef struct { | ||
| 191 | unsigned int dummy1 : 16; | ||
| 192 | unsigned int md0 : 16; | ||
| 193 | } reg_iop_dmc_out_rw_ctxt_descr; | ||
| 194 | #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60 | ||
| 195 | #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60 | ||
| 196 | |||
| 197 | /* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ | ||
| 198 | typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1; | ||
| 199 | #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 | ||
| 200 | #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 | ||
| 201 | |||
| 202 | /* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ | ||
| 203 | typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2; | ||
| 204 | #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 | ||
| 205 | #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 | ||
| 206 | |||
| 207 | /* Register rw_group_descr, scope iop_dmc_out, type rw */ | ||
| 208 | typedef struct { | ||
| 209 | unsigned int dummy1 : 16; | ||
| 210 | unsigned int md : 16; | ||
| 211 | } reg_iop_dmc_out_rw_group_descr; | ||
| 212 | #define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80 | ||
| 213 | #define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80 | ||
| 214 | |||
| 215 | /* Register rw_intr_mask, scope iop_dmc_out, type rw */ | ||
| 216 | typedef struct { | ||
| 217 | unsigned int data_md : 1; | ||
| 218 | unsigned int ctxt_md : 1; | ||
| 219 | unsigned int group_md : 1; | ||
| 220 | unsigned int cmd_rdy : 1; | ||
| 221 | unsigned int dth : 1; | ||
| 222 | unsigned int dv : 1; | ||
| 223 | unsigned int last_data : 1; | ||
| 224 | unsigned int trf_lim : 1; | ||
| 225 | unsigned int cmd_rq : 1; | ||
| 226 | unsigned int dummy1 : 23; | ||
| 227 | } reg_iop_dmc_out_rw_intr_mask; | ||
| 228 | #define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84 | ||
| 229 | #define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84 | ||
| 230 | |||
| 231 | /* Register rw_ack_intr, scope iop_dmc_out, type rw */ | ||
| 232 | typedef struct { | ||
| 233 | unsigned int data_md : 1; | ||
| 234 | unsigned int ctxt_md : 1; | ||
| 235 | unsigned int group_md : 1; | ||
| 236 | unsigned int cmd_rdy : 1; | ||
| 237 | unsigned int dth : 1; | ||
| 238 | unsigned int dv : 1; | ||
| 239 | unsigned int last_data : 1; | ||
| 240 | unsigned int trf_lim : 1; | ||
| 241 | unsigned int cmd_rq : 1; | ||
| 242 | unsigned int dummy1 : 23; | ||
| 243 | } reg_iop_dmc_out_rw_ack_intr; | ||
| 244 | #define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88 | ||
| 245 | #define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88 | ||
| 246 | |||
| 247 | /* Register r_intr, scope iop_dmc_out, type r */ | ||
| 248 | typedef struct { | ||
| 249 | unsigned int data_md : 1; | ||
| 250 | unsigned int ctxt_md : 1; | ||
| 251 | unsigned int group_md : 1; | ||
| 252 | unsigned int cmd_rdy : 1; | ||
| 253 | unsigned int dth : 1; | ||
| 254 | unsigned int dv : 1; | ||
| 255 | unsigned int last_data : 1; | ||
| 256 | unsigned int trf_lim : 1; | ||
| 257 | unsigned int cmd_rq : 1; | ||
| 258 | unsigned int dummy1 : 23; | ||
| 259 | } reg_iop_dmc_out_r_intr; | ||
| 260 | #define REG_RD_ADDR_iop_dmc_out_r_intr 92 | ||
| 261 | |||
| 262 | /* Register r_masked_intr, scope iop_dmc_out, type r */ | ||
| 263 | typedef struct { | ||
| 264 | unsigned int data_md : 1; | ||
| 265 | unsigned int ctxt_md : 1; | ||
| 266 | unsigned int group_md : 1; | ||
| 267 | unsigned int cmd_rdy : 1; | ||
| 268 | unsigned int dth : 1; | ||
| 269 | unsigned int dv : 1; | ||
| 270 | unsigned int last_data : 1; | ||
| 271 | unsigned int trf_lim : 1; | ||
| 272 | unsigned int cmd_rq : 1; | ||
| 273 | unsigned int dummy1 : 23; | ||
| 274 | } reg_iop_dmc_out_r_masked_intr; | ||
| 275 | #define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96 | ||
| 276 | |||
| 277 | |||
| 278 | /* Constants */ | ||
| 279 | enum { | ||
| 280 | regk_iop_dmc_out_ack_pkt = 0x00000100, | ||
| 281 | regk_iop_dmc_out_array = 0x00000008, | ||
| 282 | regk_iop_dmc_out_burst = 0x00000020, | ||
| 283 | regk_iop_dmc_out_copy_next = 0x00000010, | ||
| 284 | regk_iop_dmc_out_copy_up = 0x00000020, | ||
| 285 | regk_iop_dmc_out_dis_c = 0x00000010, | ||
| 286 | regk_iop_dmc_out_dis_g = 0x00000020, | ||
| 287 | regk_iop_dmc_out_lim1 = 0x00000000, | ||
| 288 | regk_iop_dmc_out_lim16 = 0x00000004, | ||
| 289 | regk_iop_dmc_out_lim2 = 0x00000001, | ||
| 290 | regk_iop_dmc_out_lim32 = 0x00000005, | ||
| 291 | regk_iop_dmc_out_lim4 = 0x00000002, | ||
| 292 | regk_iop_dmc_out_lim64 = 0x00000006, | ||
| 293 | regk_iop_dmc_out_lim8 = 0x00000003, | ||
| 294 | regk_iop_dmc_out_load_c = 0x00000200, | ||
| 295 | regk_iop_dmc_out_load_c_n = 0x00000280, | ||
| 296 | regk_iop_dmc_out_load_c_next = 0x00000240, | ||
| 297 | regk_iop_dmc_out_load_d = 0x00000140, | ||
| 298 | regk_iop_dmc_out_load_g = 0x00000300, | ||
| 299 | regk_iop_dmc_out_load_g_down = 0x000003c0, | ||
| 300 | regk_iop_dmc_out_load_g_next = 0x00000340, | ||
| 301 | regk_iop_dmc_out_load_g_up = 0x00000380, | ||
| 302 | regk_iop_dmc_out_next_en = 0x00000010, | ||
| 303 | regk_iop_dmc_out_next_pkt = 0x00000010, | ||
| 304 | regk_iop_dmc_out_no = 0x00000000, | ||
| 305 | regk_iop_dmc_out_restore = 0x00000020, | ||
| 306 | regk_iop_dmc_out_rw_cfg_default = 0x00000000, | ||
| 307 | regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000, | ||
| 308 | regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000, | ||
| 309 | regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000, | ||
| 310 | regk_iop_dmc_out_rw_data_descr_default = 0x00000000, | ||
| 311 | regk_iop_dmc_out_rw_group_descr_default = 0x00000000, | ||
| 312 | regk_iop_dmc_out_rw_intr_mask_default = 0x00000000, | ||
| 313 | regk_iop_dmc_out_save_down = 0x00000020, | ||
| 314 | regk_iop_dmc_out_save_up = 0x00000020, | ||
| 315 | regk_iop_dmc_out_set_reg = 0x00000050, | ||
| 316 | regk_iop_dmc_out_set_w_size1 = 0x00000190, | ||
| 317 | regk_iop_dmc_out_set_w_size2 = 0x000001a0, | ||
| 318 | regk_iop_dmc_out_set_w_size4 = 0x000001c0, | ||
| 319 | regk_iop_dmc_out_store_c = 0x00000002, | ||
| 320 | regk_iop_dmc_out_store_descr = 0x00000000, | ||
| 321 | regk_iop_dmc_out_store_g = 0x00000004, | ||
| 322 | regk_iop_dmc_out_store_md = 0x00000001, | ||
| 323 | regk_iop_dmc_out_update_down = 0x00000020, | ||
| 324 | regk_iop_dmc_out_yes = 0x00000001 | ||
| 325 | }; | ||
| 326 | #endif /* __iop_dmc_out_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h deleted file mode 100644 index e0c982b263fa..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h +++ /dev/null | |||
| @@ -1,255 +0,0 @@ | |||
| 1 | #ifndef __iop_fifo_in_defs_h | ||
| 2 | #define __iop_fifo_in_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_fifo_in.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:07 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r | ||
| 11 | * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_fifo_in */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope iop_fifo_in, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int avail_lim : 3; | ||
| 90 | unsigned int byte_order : 2; | ||
| 91 | unsigned int trig : 2; | ||
| 92 | unsigned int last_dis_dif_in : 1; | ||
| 93 | unsigned int mode : 2; | ||
| 94 | unsigned int dummy1 : 22; | ||
| 95 | } reg_iop_fifo_in_rw_cfg; | ||
| 96 | #define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 | ||
| 97 | #define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 | ||
| 98 | |||
| 99 | /* Register rw_ctrl, scope iop_fifo_in, type rw */ | ||
| 100 | typedef struct { | ||
| 101 | unsigned int dif_in_en : 1; | ||
| 102 | unsigned int dif_out_en : 1; | ||
| 103 | unsigned int dummy1 : 30; | ||
| 104 | } reg_iop_fifo_in_rw_ctrl; | ||
| 105 | #define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 | ||
| 106 | #define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 | ||
| 107 | |||
| 108 | /* Register r_stat, scope iop_fifo_in, type r */ | ||
| 109 | typedef struct { | ||
| 110 | unsigned int avail_bytes : 4; | ||
| 111 | unsigned int last : 8; | ||
| 112 | unsigned int dif_in_en : 1; | ||
| 113 | unsigned int dif_out_en : 1; | ||
| 114 | unsigned int dummy1 : 18; | ||
| 115 | } reg_iop_fifo_in_r_stat; | ||
| 116 | #define REG_RD_ADDR_iop_fifo_in_r_stat 8 | ||
| 117 | |||
| 118 | /* Register rs_rd1byte, scope iop_fifo_in, type rs */ | ||
| 119 | typedef struct { | ||
| 120 | unsigned int data : 8; | ||
| 121 | unsigned int dummy1 : 24; | ||
| 122 | } reg_iop_fifo_in_rs_rd1byte; | ||
| 123 | #define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 | ||
| 124 | |||
| 125 | /* Register r_rd1byte, scope iop_fifo_in, type r */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int data : 8; | ||
| 128 | unsigned int dummy1 : 24; | ||
| 129 | } reg_iop_fifo_in_r_rd1byte; | ||
| 130 | #define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 | ||
| 131 | |||
| 132 | /* Register rs_rd2byte, scope iop_fifo_in, type rs */ | ||
| 133 | typedef struct { | ||
| 134 | unsigned int data : 16; | ||
| 135 | unsigned int dummy1 : 16; | ||
| 136 | } reg_iop_fifo_in_rs_rd2byte; | ||
| 137 | #define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 | ||
| 138 | |||
| 139 | /* Register r_rd2byte, scope iop_fifo_in, type r */ | ||
| 140 | typedef struct { | ||
| 141 | unsigned int data : 16; | ||
| 142 | unsigned int dummy1 : 16; | ||
| 143 | } reg_iop_fifo_in_r_rd2byte; | ||
| 144 | #define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 | ||
| 145 | |||
| 146 | /* Register rs_rd3byte, scope iop_fifo_in, type rs */ | ||
| 147 | typedef struct { | ||
| 148 | unsigned int data : 24; | ||
| 149 | unsigned int dummy1 : 8; | ||
| 150 | } reg_iop_fifo_in_rs_rd3byte; | ||
| 151 | #define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 | ||
| 152 | |||
| 153 | /* Register r_rd3byte, scope iop_fifo_in, type r */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int data : 24; | ||
| 156 | unsigned int dummy1 : 8; | ||
| 157 | } reg_iop_fifo_in_r_rd3byte; | ||
| 158 | #define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 | ||
| 159 | |||
| 160 | /* Register rs_rd4byte, scope iop_fifo_in, type rs */ | ||
| 161 | typedef struct { | ||
| 162 | unsigned int data : 32; | ||
| 163 | } reg_iop_fifo_in_rs_rd4byte; | ||
| 164 | #define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 | ||
| 165 | |||
| 166 | /* Register r_rd4byte, scope iop_fifo_in, type r */ | ||
| 167 | typedef struct { | ||
| 168 | unsigned int data : 32; | ||
| 169 | } reg_iop_fifo_in_r_rd4byte; | ||
| 170 | #define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 | ||
| 171 | |||
| 172 | /* Register rw_set_last, scope iop_fifo_in, type rw */ | ||
| 173 | typedef unsigned int reg_iop_fifo_in_rw_set_last; | ||
| 174 | #define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 | ||
| 175 | #define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 | ||
| 176 | |||
| 177 | /* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int last : 2; | ||
| 180 | unsigned int dummy1 : 30; | ||
| 181 | } reg_iop_fifo_in_rw_strb_dif_in; | ||
| 182 | #define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 | ||
| 183 | #define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 | ||
| 184 | |||
| 185 | /* Register rw_intr_mask, scope iop_fifo_in, type rw */ | ||
| 186 | typedef struct { | ||
| 187 | unsigned int urun : 1; | ||
| 188 | unsigned int last_data : 1; | ||
| 189 | unsigned int dav : 1; | ||
| 190 | unsigned int avail : 1; | ||
| 191 | unsigned int orun : 1; | ||
| 192 | unsigned int dummy1 : 27; | ||
| 193 | } reg_iop_fifo_in_rw_intr_mask; | ||
| 194 | #define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 | ||
| 195 | #define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 | ||
| 196 | |||
| 197 | /* Register rw_ack_intr, scope iop_fifo_in, type rw */ | ||
| 198 | typedef struct { | ||
| 199 | unsigned int urun : 1; | ||
| 200 | unsigned int last_data : 1; | ||
| 201 | unsigned int dav : 1; | ||
| 202 | unsigned int avail : 1; | ||
| 203 | unsigned int orun : 1; | ||
| 204 | unsigned int dummy1 : 27; | ||
| 205 | } reg_iop_fifo_in_rw_ack_intr; | ||
| 206 | #define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 | ||
| 207 | #define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 | ||
| 208 | |||
| 209 | /* Register r_intr, scope iop_fifo_in, type r */ | ||
| 210 | typedef struct { | ||
| 211 | unsigned int urun : 1; | ||
| 212 | unsigned int last_data : 1; | ||
| 213 | unsigned int dav : 1; | ||
| 214 | unsigned int avail : 1; | ||
| 215 | unsigned int orun : 1; | ||
| 216 | unsigned int dummy1 : 27; | ||
| 217 | } reg_iop_fifo_in_r_intr; | ||
| 218 | #define REG_RD_ADDR_iop_fifo_in_r_intr 60 | ||
| 219 | |||
| 220 | /* Register r_masked_intr, scope iop_fifo_in, type r */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int urun : 1; | ||
| 223 | unsigned int last_data : 1; | ||
| 224 | unsigned int dav : 1; | ||
| 225 | unsigned int avail : 1; | ||
| 226 | unsigned int orun : 1; | ||
| 227 | unsigned int dummy1 : 27; | ||
| 228 | } reg_iop_fifo_in_r_masked_intr; | ||
| 229 | #define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 | ||
| 230 | |||
| 231 | |||
| 232 | /* Constants */ | ||
| 233 | enum { | ||
| 234 | regk_iop_fifo_in_dif_in = 0x00000002, | ||
| 235 | regk_iop_fifo_in_hi = 0x00000000, | ||
| 236 | regk_iop_fifo_in_neg = 0x00000002, | ||
| 237 | regk_iop_fifo_in_no = 0x00000000, | ||
| 238 | regk_iop_fifo_in_order16 = 0x00000001, | ||
| 239 | regk_iop_fifo_in_order24 = 0x00000002, | ||
| 240 | regk_iop_fifo_in_order32 = 0x00000003, | ||
| 241 | regk_iop_fifo_in_order8 = 0x00000000, | ||
| 242 | regk_iop_fifo_in_pos = 0x00000001, | ||
| 243 | regk_iop_fifo_in_pos_neg = 0x00000003, | ||
| 244 | regk_iop_fifo_in_rw_cfg_default = 0x00000024, | ||
| 245 | regk_iop_fifo_in_rw_ctrl_default = 0x00000000, | ||
| 246 | regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, | ||
| 247 | regk_iop_fifo_in_rw_set_last_default = 0x00000000, | ||
| 248 | regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, | ||
| 249 | regk_iop_fifo_in_size16 = 0x00000002, | ||
| 250 | regk_iop_fifo_in_size24 = 0x00000001, | ||
| 251 | regk_iop_fifo_in_size32 = 0x00000000, | ||
| 252 | regk_iop_fifo_in_size8 = 0x00000003, | ||
| 253 | regk_iop_fifo_in_yes = 0x00000001 | ||
| 254 | }; | ||
| 255 | #endif /* __iop_fifo_in_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h deleted file mode 100644 index 798ac95870e9..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h +++ /dev/null | |||
| @@ -1,164 +0,0 @@ | |||
| 1 | #ifndef __iop_fifo_in_extra_defs_h | ||
| 2 | #define __iop_fifo_in_extra_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:08 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r | ||
| 11 | * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_fifo_in_extra */ | ||
| 86 | |||
| 87 | /* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ | ||
| 88 | typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data; | ||
| 89 | #define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0 | ||
| 90 | #define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0 | ||
| 91 | |||
| 92 | /* Register r_stat, scope iop_fifo_in_extra, type r */ | ||
| 93 | typedef struct { | ||
| 94 | unsigned int avail_bytes : 4; | ||
| 95 | unsigned int last : 8; | ||
| 96 | unsigned int dif_in_en : 1; | ||
| 97 | unsigned int dif_out_en : 1; | ||
| 98 | unsigned int dummy1 : 18; | ||
| 99 | } reg_iop_fifo_in_extra_r_stat; | ||
| 100 | #define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4 | ||
| 101 | |||
| 102 | /* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ | ||
| 103 | typedef struct { | ||
| 104 | unsigned int last : 2; | ||
| 105 | unsigned int dummy1 : 30; | ||
| 106 | } reg_iop_fifo_in_extra_rw_strb_dif_in; | ||
| 107 | #define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 | ||
| 108 | #define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 | ||
| 109 | |||
| 110 | /* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int urun : 1; | ||
| 113 | unsigned int last_data : 1; | ||
| 114 | unsigned int dav : 1; | ||
| 115 | unsigned int avail : 1; | ||
| 116 | unsigned int orun : 1; | ||
| 117 | unsigned int dummy1 : 27; | ||
| 118 | } reg_iop_fifo_in_extra_rw_intr_mask; | ||
| 119 | #define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12 | ||
| 120 | #define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12 | ||
| 121 | |||
| 122 | /* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ | ||
| 123 | typedef struct { | ||
| 124 | unsigned int urun : 1; | ||
| 125 | unsigned int last_data : 1; | ||
| 126 | unsigned int dav : 1; | ||
| 127 | unsigned int avail : 1; | ||
| 128 | unsigned int orun : 1; | ||
| 129 | unsigned int dummy1 : 27; | ||
| 130 | } reg_iop_fifo_in_extra_rw_ack_intr; | ||
| 131 | #define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16 | ||
| 132 | #define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16 | ||
| 133 | |||
| 134 | /* Register r_intr, scope iop_fifo_in_extra, type r */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int urun : 1; | ||
| 137 | unsigned int last_data : 1; | ||
| 138 | unsigned int dav : 1; | ||
| 139 | unsigned int avail : 1; | ||
| 140 | unsigned int orun : 1; | ||
| 141 | unsigned int dummy1 : 27; | ||
| 142 | } reg_iop_fifo_in_extra_r_intr; | ||
| 143 | #define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20 | ||
| 144 | |||
| 145 | /* Register r_masked_intr, scope iop_fifo_in_extra, type r */ | ||
| 146 | typedef struct { | ||
| 147 | unsigned int urun : 1; | ||
| 148 | unsigned int last_data : 1; | ||
| 149 | unsigned int dav : 1; | ||
| 150 | unsigned int avail : 1; | ||
| 151 | unsigned int orun : 1; | ||
| 152 | unsigned int dummy1 : 27; | ||
| 153 | } reg_iop_fifo_in_extra_r_masked_intr; | ||
| 154 | #define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24 | ||
| 155 | |||
| 156 | |||
| 157 | /* Constants */ | ||
| 158 | enum { | ||
| 159 | regk_iop_fifo_in_extra_fifo_in = 0x00000002, | ||
| 160 | regk_iop_fifo_in_extra_no = 0x00000000, | ||
| 161 | regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000, | ||
| 162 | regk_iop_fifo_in_extra_yes = 0x00000001 | ||
| 163 | }; | ||
| 164 | #endif /* __iop_fifo_in_extra_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h deleted file mode 100644 index 833e10f02526..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h +++ /dev/null | |||
| @@ -1,278 +0,0 @@ | |||
| 1 | #ifndef __iop_fifo_out_defs_h | ||
| 2 | #define __iop_fifo_out_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_fifo_out.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:09 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r | ||
| 11 | * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_fifo_out */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope iop_fifo_out, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int free_lim : 3; | ||
| 90 | unsigned int byte_order : 2; | ||
| 91 | unsigned int trig : 2; | ||
| 92 | unsigned int last_dis_dif_in : 1; | ||
| 93 | unsigned int mode : 2; | ||
| 94 | unsigned int delay_out_last : 1; | ||
| 95 | unsigned int last_dis_dif_out : 1; | ||
| 96 | unsigned int dummy1 : 20; | ||
| 97 | } reg_iop_fifo_out_rw_cfg; | ||
| 98 | #define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 | ||
| 99 | #define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 | ||
| 100 | |||
| 101 | /* Register rw_ctrl, scope iop_fifo_out, type rw */ | ||
| 102 | typedef struct { | ||
| 103 | unsigned int dif_in_en : 1; | ||
| 104 | unsigned int dif_out_en : 1; | ||
| 105 | unsigned int dummy1 : 30; | ||
| 106 | } reg_iop_fifo_out_rw_ctrl; | ||
| 107 | #define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 | ||
| 108 | #define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 | ||
| 109 | |||
| 110 | /* Register r_stat, scope iop_fifo_out, type r */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int avail_bytes : 4; | ||
| 113 | unsigned int last : 8; | ||
| 114 | unsigned int dif_in_en : 1; | ||
| 115 | unsigned int dif_out_en : 1; | ||
| 116 | unsigned int zero_data_last : 1; | ||
| 117 | unsigned int dummy1 : 17; | ||
| 118 | } reg_iop_fifo_out_r_stat; | ||
| 119 | #define REG_RD_ADDR_iop_fifo_out_r_stat 8 | ||
| 120 | |||
| 121 | /* Register rw_wr1byte, scope iop_fifo_out, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int data : 8; | ||
| 124 | unsigned int dummy1 : 24; | ||
| 125 | } reg_iop_fifo_out_rw_wr1byte; | ||
| 126 | #define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 | ||
| 127 | #define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 | ||
| 128 | |||
| 129 | /* Register rw_wr2byte, scope iop_fifo_out, type rw */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int data : 16; | ||
| 132 | unsigned int dummy1 : 16; | ||
| 133 | } reg_iop_fifo_out_rw_wr2byte; | ||
| 134 | #define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 | ||
| 135 | #define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 | ||
| 136 | |||
| 137 | /* Register rw_wr3byte, scope iop_fifo_out, type rw */ | ||
| 138 | typedef struct { | ||
| 139 | unsigned int data : 24; | ||
| 140 | unsigned int dummy1 : 8; | ||
| 141 | } reg_iop_fifo_out_rw_wr3byte; | ||
| 142 | #define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 | ||
| 143 | #define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 | ||
| 144 | |||
| 145 | /* Register rw_wr4byte, scope iop_fifo_out, type rw */ | ||
| 146 | typedef struct { | ||
| 147 | unsigned int data : 32; | ||
| 148 | } reg_iop_fifo_out_rw_wr4byte; | ||
| 149 | #define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 | ||
| 150 | #define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 | ||
| 151 | |||
| 152 | /* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ | ||
| 153 | typedef struct { | ||
| 154 | unsigned int data : 8; | ||
| 155 | unsigned int dummy1 : 24; | ||
| 156 | } reg_iop_fifo_out_rw_wr1byte_last; | ||
| 157 | #define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 | ||
| 158 | #define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 | ||
| 159 | |||
| 160 | /* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ | ||
| 161 | typedef struct { | ||
| 162 | unsigned int data : 16; | ||
| 163 | unsigned int dummy1 : 16; | ||
| 164 | } reg_iop_fifo_out_rw_wr2byte_last; | ||
| 165 | #define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 | ||
| 166 | #define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 | ||
| 167 | |||
| 168 | /* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ | ||
| 169 | typedef struct { | ||
| 170 | unsigned int data : 24; | ||
| 171 | unsigned int dummy1 : 8; | ||
| 172 | } reg_iop_fifo_out_rw_wr3byte_last; | ||
| 173 | #define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 | ||
| 174 | #define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 | ||
| 175 | |||
| 176 | /* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ | ||
| 177 | typedef struct { | ||
| 178 | unsigned int data : 32; | ||
| 179 | } reg_iop_fifo_out_rw_wr4byte_last; | ||
| 180 | #define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 | ||
| 181 | #define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 | ||
| 182 | |||
| 183 | /* Register rw_set_last, scope iop_fifo_out, type rw */ | ||
| 184 | typedef unsigned int reg_iop_fifo_out_rw_set_last; | ||
| 185 | #define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 | ||
| 186 | #define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 | ||
| 187 | |||
| 188 | /* Register rs_rd_data, scope iop_fifo_out, type rs */ | ||
| 189 | typedef unsigned int reg_iop_fifo_out_rs_rd_data; | ||
| 190 | #define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 | ||
| 191 | |||
| 192 | /* Register r_rd_data, scope iop_fifo_out, type r */ | ||
| 193 | typedef unsigned int reg_iop_fifo_out_r_rd_data; | ||
| 194 | #define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 | ||
| 195 | |||
| 196 | /* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ | ||
| 197 | typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; | ||
| 198 | #define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 | ||
| 199 | #define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 | ||
| 200 | |||
| 201 | /* Register rw_intr_mask, scope iop_fifo_out, type rw */ | ||
| 202 | typedef struct { | ||
| 203 | unsigned int urun : 1; | ||
| 204 | unsigned int last_data : 1; | ||
| 205 | unsigned int dav : 1; | ||
| 206 | unsigned int free : 1; | ||
| 207 | unsigned int orun : 1; | ||
| 208 | unsigned int dummy1 : 27; | ||
| 209 | } reg_iop_fifo_out_rw_intr_mask; | ||
| 210 | #define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 | ||
| 211 | #define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 | ||
| 212 | |||
| 213 | /* Register rw_ack_intr, scope iop_fifo_out, type rw */ | ||
| 214 | typedef struct { | ||
| 215 | unsigned int urun : 1; | ||
| 216 | unsigned int last_data : 1; | ||
| 217 | unsigned int dav : 1; | ||
| 218 | unsigned int free : 1; | ||
| 219 | unsigned int orun : 1; | ||
| 220 | unsigned int dummy1 : 27; | ||
| 221 | } reg_iop_fifo_out_rw_ack_intr; | ||
| 222 | #define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 | ||
| 223 | #define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 | ||
| 224 | |||
| 225 | /* Register r_intr, scope iop_fifo_out, type r */ | ||
| 226 | typedef struct { | ||
| 227 | unsigned int urun : 1; | ||
| 228 | unsigned int last_data : 1; | ||
| 229 | unsigned int dav : 1; | ||
| 230 | unsigned int free : 1; | ||
| 231 | unsigned int orun : 1; | ||
| 232 | unsigned int dummy1 : 27; | ||
| 233 | } reg_iop_fifo_out_r_intr; | ||
| 234 | #define REG_RD_ADDR_iop_fifo_out_r_intr 68 | ||
| 235 | |||
| 236 | /* Register r_masked_intr, scope iop_fifo_out, type r */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int urun : 1; | ||
| 239 | unsigned int last_data : 1; | ||
| 240 | unsigned int dav : 1; | ||
| 241 | unsigned int free : 1; | ||
| 242 | unsigned int orun : 1; | ||
| 243 | unsigned int dummy1 : 27; | ||
| 244 | } reg_iop_fifo_out_r_masked_intr; | ||
| 245 | #define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 | ||
| 246 | |||
| 247 | |||
| 248 | /* Constants */ | ||
| 249 | enum { | ||
| 250 | regk_iop_fifo_out_hi = 0x00000000, | ||
| 251 | regk_iop_fifo_out_neg = 0x00000002, | ||
| 252 | regk_iop_fifo_out_no = 0x00000000, | ||
| 253 | regk_iop_fifo_out_order16 = 0x00000001, | ||
| 254 | regk_iop_fifo_out_order24 = 0x00000002, | ||
| 255 | regk_iop_fifo_out_order32 = 0x00000003, | ||
| 256 | regk_iop_fifo_out_order8 = 0x00000000, | ||
| 257 | regk_iop_fifo_out_pos = 0x00000001, | ||
| 258 | regk_iop_fifo_out_pos_neg = 0x00000003, | ||
| 259 | regk_iop_fifo_out_rw_cfg_default = 0x00000024, | ||
| 260 | regk_iop_fifo_out_rw_ctrl_default = 0x00000000, | ||
| 261 | regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, | ||
| 262 | regk_iop_fifo_out_rw_set_last_default = 0x00000000, | ||
| 263 | regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, | ||
| 264 | regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, | ||
| 265 | regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, | ||
| 266 | regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, | ||
| 267 | regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, | ||
| 268 | regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, | ||
| 269 | regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, | ||
| 270 | regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, | ||
| 271 | regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, | ||
| 272 | regk_iop_fifo_out_size16 = 0x00000002, | ||
| 273 | regk_iop_fifo_out_size24 = 0x00000001, | ||
| 274 | regk_iop_fifo_out_size32 = 0x00000000, | ||
| 275 | regk_iop_fifo_out_size8 = 0x00000003, | ||
| 276 | regk_iop_fifo_out_yes = 0x00000001 | ||
| 277 | }; | ||
| 278 | #endif /* __iop_fifo_out_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h deleted file mode 100644 index 4a840aae84ee..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h +++ /dev/null | |||
| @@ -1,164 +0,0 @@ | |||
| 1 | #ifndef __iop_fifo_out_extra_defs_h | ||
| 2 | #define __iop_fifo_out_extra_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:10 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r | ||
| 11 | * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_fifo_out_extra */ | ||
| 86 | |||
| 87 | /* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ | ||
| 88 | typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data; | ||
| 89 | #define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0 | ||
| 90 | |||
| 91 | /* Register r_rd_data, scope iop_fifo_out_extra, type r */ | ||
| 92 | typedef unsigned int reg_iop_fifo_out_extra_r_rd_data; | ||
| 93 | #define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4 | ||
| 94 | |||
| 95 | /* Register r_stat, scope iop_fifo_out_extra, type r */ | ||
| 96 | typedef struct { | ||
| 97 | unsigned int avail_bytes : 4; | ||
| 98 | unsigned int last : 8; | ||
| 99 | unsigned int dif_in_en : 1; | ||
| 100 | unsigned int dif_out_en : 1; | ||
| 101 | unsigned int zero_data_last : 1; | ||
| 102 | unsigned int dummy1 : 17; | ||
| 103 | } reg_iop_fifo_out_extra_r_stat; | ||
| 104 | #define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8 | ||
| 105 | |||
| 106 | /* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ | ||
| 107 | typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out; | ||
| 108 | #define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 | ||
| 109 | #define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 | ||
| 110 | |||
| 111 | /* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ | ||
| 112 | typedef struct { | ||
| 113 | unsigned int urun : 1; | ||
| 114 | unsigned int last_data : 1; | ||
| 115 | unsigned int dav : 1; | ||
| 116 | unsigned int free : 1; | ||
| 117 | unsigned int orun : 1; | ||
| 118 | unsigned int dummy1 : 27; | ||
| 119 | } reg_iop_fifo_out_extra_rw_intr_mask; | ||
| 120 | #define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16 | ||
| 121 | #define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16 | ||
| 122 | |||
| 123 | /* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ | ||
| 124 | typedef struct { | ||
| 125 | unsigned int urun : 1; | ||
| 126 | unsigned int last_data : 1; | ||
| 127 | unsigned int dav : 1; | ||
| 128 | unsigned int free : 1; | ||
| 129 | unsigned int orun : 1; | ||
| 130 | unsigned int dummy1 : 27; | ||
| 131 | } reg_iop_fifo_out_extra_rw_ack_intr; | ||
| 132 | #define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20 | ||
| 133 | #define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20 | ||
| 134 | |||
| 135 | /* Register r_intr, scope iop_fifo_out_extra, type r */ | ||
| 136 | typedef struct { | ||
| 137 | unsigned int urun : 1; | ||
| 138 | unsigned int last_data : 1; | ||
| 139 | unsigned int dav : 1; | ||
| 140 | unsigned int free : 1; | ||
| 141 | unsigned int orun : 1; | ||
| 142 | unsigned int dummy1 : 27; | ||
| 143 | } reg_iop_fifo_out_extra_r_intr; | ||
| 144 | #define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24 | ||
| 145 | |||
| 146 | /* Register r_masked_intr, scope iop_fifo_out_extra, type r */ | ||
| 147 | typedef struct { | ||
| 148 | unsigned int urun : 1; | ||
| 149 | unsigned int last_data : 1; | ||
| 150 | unsigned int dav : 1; | ||
| 151 | unsigned int free : 1; | ||
| 152 | unsigned int orun : 1; | ||
| 153 | unsigned int dummy1 : 27; | ||
| 154 | } reg_iop_fifo_out_extra_r_masked_intr; | ||
| 155 | #define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28 | ||
| 156 | |||
| 157 | |||
| 158 | /* Constants */ | ||
| 159 | enum { | ||
| 160 | regk_iop_fifo_out_extra_no = 0x00000000, | ||
| 161 | regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000, | ||
| 162 | regk_iop_fifo_out_extra_yes = 0x00000001 | ||
| 163 | }; | ||
| 164 | #endif /* __iop_fifo_out_extra_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h deleted file mode 100644 index c2b0ba1be60f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h +++ /dev/null | |||
| @@ -1,190 +0,0 @@ | |||
| 1 | #ifndef __iop_mpu_defs_h | ||
| 2 | #define __iop_mpu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_mpu.r | ||
| 7 | * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r | ||
| 11 | * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_mpu */ | ||
| 86 | |||
| 87 | #define STRIDE_iop_mpu_rw_r 4 | ||
| 88 | /* Register rw_r, scope iop_mpu, type rw */ | ||
| 89 | typedef unsigned int reg_iop_mpu_rw_r; | ||
| 90 | #define REG_RD_ADDR_iop_mpu_rw_r 0 | ||
| 91 | #define REG_WR_ADDR_iop_mpu_rw_r 0 | ||
| 92 | |||
| 93 | /* Register rw_ctrl, scope iop_mpu, type rw */ | ||
| 94 | typedef struct { | ||
| 95 | unsigned int en : 1; | ||
| 96 | unsigned int dummy1 : 31; | ||
| 97 | } reg_iop_mpu_rw_ctrl; | ||
| 98 | #define REG_RD_ADDR_iop_mpu_rw_ctrl 128 | ||
| 99 | #define REG_WR_ADDR_iop_mpu_rw_ctrl 128 | ||
| 100 | |||
| 101 | /* Register r_pc, scope iop_mpu, type r */ | ||
| 102 | typedef struct { | ||
| 103 | unsigned int addr : 12; | ||
| 104 | unsigned int dummy1 : 20; | ||
| 105 | } reg_iop_mpu_r_pc; | ||
| 106 | #define REG_RD_ADDR_iop_mpu_r_pc 132 | ||
| 107 | |||
| 108 | /* Register r_stat, scope iop_mpu, type r */ | ||
| 109 | typedef struct { | ||
| 110 | unsigned int instr_reg_busy : 1; | ||
| 111 | unsigned int intr_busy : 1; | ||
| 112 | unsigned int intr_vect : 16; | ||
| 113 | unsigned int dummy1 : 14; | ||
| 114 | } reg_iop_mpu_r_stat; | ||
| 115 | #define REG_RD_ADDR_iop_mpu_r_stat 136 | ||
| 116 | |||
| 117 | /* Register rw_instr, scope iop_mpu, type rw */ | ||
| 118 | typedef unsigned int reg_iop_mpu_rw_instr; | ||
| 119 | #define REG_RD_ADDR_iop_mpu_rw_instr 140 | ||
| 120 | #define REG_WR_ADDR_iop_mpu_rw_instr 140 | ||
| 121 | |||
| 122 | /* Register rw_immediate, scope iop_mpu, type rw */ | ||
| 123 | typedef unsigned int reg_iop_mpu_rw_immediate; | ||
| 124 | #define REG_RD_ADDR_iop_mpu_rw_immediate 144 | ||
| 125 | #define REG_WR_ADDR_iop_mpu_rw_immediate 144 | ||
| 126 | |||
| 127 | /* Register r_trace, scope iop_mpu, type r */ | ||
| 128 | typedef struct { | ||
| 129 | unsigned int intr_vect : 16; | ||
| 130 | unsigned int pc : 12; | ||
| 131 | unsigned int en : 1; | ||
| 132 | unsigned int instr_reg_busy : 1; | ||
| 133 | unsigned int intr_busy : 1; | ||
| 134 | unsigned int dummy1 : 1; | ||
| 135 | } reg_iop_mpu_r_trace; | ||
| 136 | #define REG_RD_ADDR_iop_mpu_r_trace 148 | ||
| 137 | |||
| 138 | /* Register r_wr_stat, scope iop_mpu, type r */ | ||
| 139 | typedef struct { | ||
| 140 | unsigned int r0 : 1; | ||
| 141 | unsigned int r1 : 1; | ||
| 142 | unsigned int r2 : 1; | ||
| 143 | unsigned int r3 : 1; | ||
| 144 | unsigned int r4 : 1; | ||
| 145 | unsigned int r5 : 1; | ||
| 146 | unsigned int r6 : 1; | ||
| 147 | unsigned int r7 : 1; | ||
| 148 | unsigned int r8 : 1; | ||
| 149 | unsigned int r9 : 1; | ||
| 150 | unsigned int r10 : 1; | ||
| 151 | unsigned int r11 : 1; | ||
| 152 | unsigned int r12 : 1; | ||
| 153 | unsigned int r13 : 1; | ||
| 154 | unsigned int r14 : 1; | ||
| 155 | unsigned int r15 : 1; | ||
| 156 | unsigned int dummy1 : 16; | ||
| 157 | } reg_iop_mpu_r_wr_stat; | ||
| 158 | #define REG_RD_ADDR_iop_mpu_r_wr_stat 152 | ||
| 159 | |||
| 160 | #define STRIDE_iop_mpu_rw_thread 4 | ||
| 161 | /* Register rw_thread, scope iop_mpu, type rw */ | ||
| 162 | typedef struct { | ||
| 163 | unsigned int addr : 12; | ||
| 164 | unsigned int dummy1 : 20; | ||
| 165 | } reg_iop_mpu_rw_thread; | ||
| 166 | #define REG_RD_ADDR_iop_mpu_rw_thread 156 | ||
| 167 | #define REG_WR_ADDR_iop_mpu_rw_thread 156 | ||
| 168 | |||
| 169 | #define STRIDE_iop_mpu_rw_intr 4 | ||
| 170 | /* Register rw_intr, scope iop_mpu, type rw */ | ||
| 171 | typedef struct { | ||
| 172 | unsigned int addr : 12; | ||
| 173 | unsigned int dummy1 : 20; | ||
| 174 | } reg_iop_mpu_rw_intr; | ||
| 175 | #define REG_RD_ADDR_iop_mpu_rw_intr 196 | ||
| 176 | #define REG_WR_ADDR_iop_mpu_rw_intr 196 | ||
| 177 | |||
| 178 | |||
| 179 | /* Constants */ | ||
| 180 | enum { | ||
| 181 | regk_iop_mpu_no = 0x00000000, | ||
| 182 | regk_iop_mpu_r_pc_default = 0x00000000, | ||
| 183 | regk_iop_mpu_rw_ctrl_default = 0x00000000, | ||
| 184 | regk_iop_mpu_rw_intr_size = 0x00000010, | ||
| 185 | regk_iop_mpu_rw_r_size = 0x00000010, | ||
| 186 | regk_iop_mpu_rw_thread_default = 0x00000000, | ||
| 187 | regk_iop_mpu_rw_thread_size = 0x00000004, | ||
| 188 | regk_iop_mpu_yes = 0x00000001 | ||
| 189 | }; | ||
| 190 | #endif /* __iop_mpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h deleted file mode 100644 index 2ec897ced166..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h +++ /dev/null | |||
| @@ -1,764 +0,0 @@ | |||
| 1 | /* ************************************************************************* */ | ||
| 2 | /* This file is autogenerated by IOPASM Version 1.2 */ | ||
| 3 | /* DO NOT EDIT THIS FILE - All changes will be lost! */ | ||
| 4 | /* ************************************************************************* */ | ||
| 5 | |||
| 6 | |||
| 7 | |||
| 8 | #ifndef __IOP_MPU_MACROS_H__ | ||
| 9 | #define __IOP_MPU_MACROS_H__ | ||
| 10 | |||
| 11 | |||
| 12 | /* ************************************************************************* */ | ||
| 13 | /* REGISTER DEFINITIONS */ | ||
| 14 | /* ************************************************************************* */ | ||
| 15 | #define MPU_R0 (0x0) | ||
| 16 | #define MPU_R1 (0x1) | ||
| 17 | #define MPU_R2 (0x2) | ||
| 18 | #define MPU_R3 (0x3) | ||
| 19 | #define MPU_R4 (0x4) | ||
| 20 | #define MPU_R5 (0x5) | ||
| 21 | #define MPU_R6 (0x6) | ||
| 22 | #define MPU_R7 (0x7) | ||
| 23 | #define MPU_R8 (0x8) | ||
| 24 | #define MPU_R9 (0x9) | ||
| 25 | #define MPU_R10 (0xa) | ||
| 26 | #define MPU_R11 (0xb) | ||
| 27 | #define MPU_R12 (0xc) | ||
| 28 | #define MPU_R13 (0xd) | ||
| 29 | #define MPU_R14 (0xe) | ||
| 30 | #define MPU_R15 (0xf) | ||
| 31 | #define MPU_PC (0x2) | ||
| 32 | #define MPU_WSTS (0x3) | ||
| 33 | #define MPU_JADDR (0x4) | ||
| 34 | #define MPU_IRP (0x5) | ||
| 35 | #define MPU_SRP (0x6) | ||
| 36 | #define MPU_T0 (0x8) | ||
| 37 | #define MPU_T1 (0x9) | ||
| 38 | #define MPU_T2 (0xa) | ||
| 39 | #define MPU_T3 (0xb) | ||
| 40 | #define MPU_I0 (0x10) | ||
| 41 | #define MPU_I1 (0x11) | ||
| 42 | #define MPU_I2 (0x12) | ||
| 43 | #define MPU_I3 (0x13) | ||
| 44 | #define MPU_I4 (0x14) | ||
| 45 | #define MPU_I5 (0x15) | ||
| 46 | #define MPU_I6 (0x16) | ||
| 47 | #define MPU_I7 (0x17) | ||
| 48 | #define MPU_I8 (0x18) | ||
| 49 | #define MPU_I9 (0x19) | ||
| 50 | #define MPU_I10 (0x1a) | ||
| 51 | #define MPU_I11 (0x1b) | ||
| 52 | #define MPU_I12 (0x1c) | ||
| 53 | #define MPU_I13 (0x1d) | ||
| 54 | #define MPU_I14 (0x1e) | ||
| 55 | #define MPU_I15 (0x1f) | ||
| 56 | #define MPU_P2 (0x2) | ||
| 57 | #define MPU_P3 (0x3) | ||
| 58 | #define MPU_P5 (0x5) | ||
| 59 | #define MPU_P6 (0x6) | ||
| 60 | #define MPU_P8 (0x8) | ||
| 61 | #define MPU_P9 (0x9) | ||
| 62 | #define MPU_P10 (0xa) | ||
| 63 | #define MPU_P11 (0xb) | ||
| 64 | #define MPU_P16 (0x10) | ||
| 65 | #define MPU_P17 (0x12) | ||
| 66 | #define MPU_P18 (0x12) | ||
| 67 | #define MPU_P19 (0x13) | ||
| 68 | #define MPU_P20 (0x14) | ||
| 69 | #define MPU_P21 (0x15) | ||
| 70 | #define MPU_P22 (0x16) | ||
| 71 | #define MPU_P23 (0x17) | ||
| 72 | #define MPU_P24 (0x18) | ||
| 73 | #define MPU_P25 (0x19) | ||
| 74 | #define MPU_P26 (0x1a) | ||
| 75 | #define MPU_P27 (0x1b) | ||
| 76 | #define MPU_P28 (0x1c) | ||
| 77 | #define MPU_P29 (0x1d) | ||
| 78 | #define MPU_P30 (0x1e) | ||
| 79 | #define MPU_P31 (0x1f) | ||
| 80 | #define MPU_P1 (0x1) | ||
| 81 | #define MPU_REGA (0x1) | ||
| 82 | |||
| 83 | |||
| 84 | |||
| 85 | /* ************************************************************************* */ | ||
| 86 | /* ADDRESS MACROS */ | ||
| 87 | /* ************************************************************************* */ | ||
| 88 | #define MK_DWORD_ADDR(ADDR) (ADDR >> 2) | ||
| 89 | #define MK_BYTE_ADDR(ADDR) (ADDR) | ||
| 90 | |||
| 91 | |||
| 92 | |||
| 93 | /* ************************************************************************* */ | ||
| 94 | /* INSTRUCTION MACROS */ | ||
| 95 | /* ************************************************************************* */ | ||
| 96 | #define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 97 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 98 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 99 | |||
| 100 | #define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 101 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 102 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 103 | |||
| 104 | #define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 105 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 106 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 107 | |||
| 108 | #define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 109 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 110 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 111 | |||
| 112 | #define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 113 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 114 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 115 | |||
| 116 | #define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 117 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 118 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 119 | |||
| 120 | #define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 121 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 122 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 123 | |||
| 124 | #define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 125 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 126 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 127 | |||
| 128 | #define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 129 | | ((N & ((1 << 16) - 1)) << 0)\ | ||
| 130 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 131 | |||
| 132 | #define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 133 | | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 134 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 135 | |||
| 136 | #define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 137 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 138 | |||
| 139 | #define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 140 | |||
| 141 | #define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 142 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 143 | |||
| 144 | #define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 145 | |||
| 146 | #define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 147 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 148 | |||
| 149 | #define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 150 | |||
| 151 | #define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 152 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 153 | |||
| 154 | #define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 155 | |||
| 156 | #define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 157 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 158 | |||
| 159 | #define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 160 | |||
| 161 | #define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 162 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 163 | |||
| 164 | #define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 165 | |||
| 166 | #define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 167 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 168 | |||
| 169 | #define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 170 | |||
| 171 | #define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 172 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 173 | |||
| 174 | #define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 175 | |||
| 176 | #define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 177 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 178 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 179 | |||
| 180 | #define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 181 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 182 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 183 | |||
| 184 | #define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 185 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 186 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 187 | |||
| 188 | #define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 189 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 190 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 191 | |||
| 192 | #define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 193 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 194 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 195 | |||
| 196 | #define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 197 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 198 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 199 | |||
| 200 | #define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 201 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 202 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 203 | |||
| 204 | #define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 205 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 206 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 207 | |||
| 208 | #define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 209 | | ((N & ((1 << 16) - 1)) << 0)\ | ||
| 210 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 211 | |||
| 212 | #define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 213 | | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 214 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 215 | |||
| 216 | #define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 217 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 218 | |||
| 219 | #define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 220 | |||
| 221 | #define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 222 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 223 | |||
| 224 | #define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 225 | |||
| 226 | #define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 227 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 228 | |||
| 229 | #define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 230 | |||
| 231 | #define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 232 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 233 | |||
| 234 | #define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 235 | |||
| 236 | #define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 237 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 238 | |||
| 239 | #define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 240 | |||
| 241 | #define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 242 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 243 | |||
| 244 | #define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 245 | |||
| 246 | #define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 247 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 248 | |||
| 249 | #define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 250 | |||
| 251 | #define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 252 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 253 | |||
| 254 | #define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 255 | |||
| 256 | #define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0)) | ||
| 257 | |||
| 258 | #define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11)) | ||
| 259 | |||
| 260 | #define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11)) | ||
| 261 | |||
| 262 | #define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 263 | | ((N & ((1 << 5) - 1)) << 21)\ | ||
| 264 | | ((D & ((1 << 16) - 1)) << 0)) | ||
| 265 | |||
| 266 | #define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 267 | | ((N & ((1 << 5) - 1)) << 21)\ | ||
| 268 | | ((D & ((1 << 16) - 1)) << 0)) | ||
| 269 | |||
| 270 | #define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 271 | | ((D & ((1 << 16) - 1)) << 0)) | ||
| 272 | |||
| 273 | #define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 274 | | ((D & ((1 << 16) - 1)) << 0)) | ||
| 275 | |||
| 276 | #define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 277 | | ((D & ((1 << 16) - 1)) << 0)) | ||
| 278 | |||
| 279 | #define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 280 | | ((D & ((1 << 16) - 1)) << 0)) | ||
| 281 | |||
| 282 | #define MPU_DI() (0x40000001) | ||
| 283 | |||
| 284 | #define MPU_EI() (0x40000003) | ||
| 285 | |||
| 286 | #define MPU_HALT() (0x40000002) | ||
| 287 | |||
| 288 | #define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0)) | ||
| 289 | |||
| 290 | #define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11)) | ||
| 291 | |||
| 292 | #define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11)) | ||
| 293 | |||
| 294 | #define MPU_JNT() (0x61000000) | ||
| 295 | |||
| 296 | #define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0)) | ||
| 297 | |||
| 298 | #define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11)) | ||
| 299 | |||
| 300 | #define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11)) | ||
| 301 | |||
| 302 | #define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 303 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 304 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 305 | |||
| 306 | #define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 307 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 308 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 309 | |||
| 310 | #define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 311 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 312 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 313 | |||
| 314 | #define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 315 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 316 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 317 | |||
| 318 | #define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 319 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 320 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 321 | |||
| 322 | #define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 323 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 324 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 325 | |||
| 326 | #define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 327 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 328 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 329 | |||
| 330 | #define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 331 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 332 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 333 | |||
| 334 | #define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 335 | | ((N & ((1 << 16) - 1)) << 0)\ | ||
| 336 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 337 | |||
| 338 | #define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 339 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 340 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 341 | |||
| 342 | #define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 343 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 344 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 345 | |||
| 346 | #define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 347 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 348 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 349 | |||
| 350 | #define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 351 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 352 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 353 | |||
| 354 | #define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 355 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 356 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 357 | |||
| 358 | #define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 359 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 360 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 361 | |||
| 362 | #define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 363 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 364 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 365 | |||
| 366 | #define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 367 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 368 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 369 | |||
| 370 | #define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 371 | | ((N & ((1 << 16) - 1)) << 0)\ | ||
| 372 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 373 | |||
| 374 | #define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 375 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 376 | |||
| 377 | #define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 378 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 379 | |||
| 380 | #define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 381 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 382 | |||
| 383 | #define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 384 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 385 | |||
| 386 | #define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 387 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 388 | |||
| 389 | #define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 390 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 391 | |||
| 392 | #define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 393 | | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 394 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 395 | |||
| 396 | #define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 397 | | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 398 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 399 | |||
| 400 | #define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 401 | | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 402 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 403 | |||
| 404 | #define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 405 | | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 406 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 407 | |||
| 408 | #define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 409 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 410 | |||
| 411 | #define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 412 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 413 | |||
| 414 | #define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 415 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 416 | |||
| 417 | #define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 418 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 419 | |||
| 420 | #define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 421 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 422 | |||
| 423 | #define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 424 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 425 | |||
| 426 | #define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21)) | ||
| 427 | |||
| 428 | #define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF) | ||
| 429 | |||
| 430 | #define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21)) | ||
| 431 | |||
| 432 | #define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF) | ||
| 433 | |||
| 434 | #define MPU_NOP() (0x40000000) | ||
| 435 | |||
| 436 | #define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 437 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 438 | |||
| 439 | #define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 440 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 441 | |||
| 442 | #define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 443 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 444 | |||
| 445 | #define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 446 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 447 | |||
| 448 | #define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 449 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 450 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 451 | |||
| 452 | #define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 453 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 454 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 455 | |||
| 456 | #define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 457 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 458 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 459 | |||
| 460 | #define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 461 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 462 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 463 | |||
| 464 | #define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 465 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 466 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 467 | |||
| 468 | #define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 469 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 470 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 471 | |||
| 472 | #define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 473 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 474 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 475 | |||
| 476 | #define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 477 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 478 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 479 | |||
| 480 | #define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 481 | | ((N & ((1 << 16) - 1)) << 0)\ | ||
| 482 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 483 | |||
| 484 | #define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 485 | | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 486 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 487 | |||
| 488 | #define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 489 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 490 | |||
| 491 | #define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 492 | |||
| 493 | #define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 494 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 495 | |||
| 496 | #define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 497 | |||
| 498 | #define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 499 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 500 | |||
| 501 | #define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 502 | |||
| 503 | #define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 504 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 505 | |||
| 506 | #define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 507 | |||
| 508 | #define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 509 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 510 | |||
| 511 | #define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 512 | |||
| 513 | #define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 514 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 515 | |||
| 516 | #define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 517 | |||
| 518 | #define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 519 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 520 | |||
| 521 | #define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 522 | |||
| 523 | #define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 524 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 525 | |||
| 526 | #define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 527 | |||
| 528 | #define MPU_RET() (0x63003000) | ||
| 529 | |||
| 530 | #define MPU_RETI() (0x63602800) | ||
| 531 | |||
| 532 | #define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\ | ||
| 533 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 534 | |||
| 535 | #define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 536 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 537 | |||
| 538 | #define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 539 | | ((D & ((1 << 11) - 1)) << 0)) | ||
| 540 | |||
| 541 | #define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 542 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 543 | |||
| 544 | #define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\ | ||
| 545 | | ((D & ((1 << 11) - 1)) << 0)) | ||
| 546 | |||
| 547 | #define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 548 | | ((D & ((1 << 5) - 1)) << 16)) | ||
| 549 | |||
| 550 | #define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0)) | ||
| 551 | |||
| 552 | #define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF) | ||
| 553 | |||
| 554 | #define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16)) | ||
| 555 | |||
| 556 | #define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF) | ||
| 557 | |||
| 558 | #define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 559 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 560 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 561 | |||
| 562 | #define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 563 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 564 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 565 | |||
| 566 | #define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 567 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 568 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 569 | |||
| 570 | #define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 571 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 572 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 573 | |||
| 574 | #define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 575 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 576 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 577 | |||
| 578 | #define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 579 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 580 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 581 | |||
| 582 | #define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 583 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 584 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 585 | |||
| 586 | #define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 587 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 588 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 589 | |||
| 590 | #define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 591 | | ((N & ((1 << 16) - 1)) << 0)\ | ||
| 592 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 593 | |||
| 594 | #define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 595 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 596 | |||
| 597 | #define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 598 | |||
| 599 | #define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 600 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 601 | |||
| 602 | #define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 603 | |||
| 604 | #define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 605 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 606 | |||
| 607 | #define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 608 | |||
| 609 | #define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 610 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 611 | |||
| 612 | #define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 613 | |||
| 614 | #define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 615 | | ((D & ((1 << 16) - 1)) << 0)) | ||
| 616 | |||
| 617 | #define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 618 | | ((D & ((1 << 16) - 1)) << 0)) | ||
| 619 | |||
| 620 | #define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 621 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 622 | |||
| 623 | #define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 624 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 625 | |||
| 626 | #define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 627 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 628 | |||
| 629 | #define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 630 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 631 | |||
| 632 | #define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 633 | | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 634 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 635 | |||
| 636 | #define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 637 | | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 638 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 639 | |||
| 640 | #define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 641 | | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 642 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 643 | |||
| 644 | #define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 645 | | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 646 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 647 | |||
| 648 | #define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0)) | ||
| 649 | |||
| 650 | #define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF) | ||
| 651 | |||
| 652 | #define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11)) | ||
| 653 | |||
| 654 | #define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF) | ||
| 655 | |||
| 656 | #define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11)) | ||
| 657 | |||
| 658 | #define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF) | ||
| 659 | |||
| 660 | #define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 661 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 662 | |||
| 663 | #define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 664 | |||
| 665 | #define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\ | ||
| 666 | | ((D & ((1 << 5) - 1)) << 11)) | ||
| 667 | |||
| 668 | #define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 669 | |||
| 670 | #define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 671 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 672 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 673 | |||
| 674 | #define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 675 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 676 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 677 | |||
| 678 | #define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 679 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 680 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 681 | |||
| 682 | #define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 683 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 684 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 685 | |||
| 686 | #define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 687 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 688 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 689 | |||
| 690 | #define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 691 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 692 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 693 | |||
| 694 | #define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 695 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 696 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 697 | |||
| 698 | #define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 699 | | ((N & ((1 << 5) - 1)) << 11)\ | ||
| 700 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 701 | |||
| 702 | #define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 703 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 704 | |||
| 705 | #define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 706 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 707 | |||
| 708 | #define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 709 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 710 | |||
| 711 | #define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\ | ||
| 712 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 713 | |||
| 714 | #define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 715 | | ((N & ((1 << 16) - 1)) << 0)\ | ||
| 716 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 717 | |||
| 718 | #define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\ | ||
| 719 | | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 720 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 721 | |||
| 722 | #define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 723 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 724 | |||
| 725 | #define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 726 | |||
| 727 | #define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 728 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 729 | |||
| 730 | #define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 731 | |||
| 732 | #define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 733 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 734 | |||
| 735 | #define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 736 | |||
| 737 | #define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 738 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 739 | |||
| 740 | #define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 741 | |||
| 742 | #define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 743 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 744 | |||
| 745 | #define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 746 | |||
| 747 | #define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 748 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 749 | |||
| 750 | #define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 751 | |||
| 752 | #define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\ | ||
| 753 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 754 | |||
| 755 | #define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) | ||
| 756 | |||
| 757 | #define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\ | ||
| 758 | | ((D & ((1 << 5) - 1)) << 21)) | ||
| 759 | |||
| 760 | #define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) | ||
| 761 | |||
| 762 | |||
| 763 | #endif /* end of __IOP_MPU_MACROS_H__ */ | ||
| 764 | /* End of iop_mpu_macros.h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h deleted file mode 100644 index 756550f5d6cb..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* Autogenerated Changes here will be lost! | ||
| 2 | * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg | ||
| 3 | */ | ||
| 4 | #define regi_iop_version (regi_iop + 0) | ||
| 5 | #define regi_iop_fifo_in0_extra (regi_iop + 64) | ||
| 6 | #define regi_iop_fifo_in1_extra (regi_iop + 128) | ||
| 7 | #define regi_iop_fifo_out0_extra (regi_iop + 192) | ||
| 8 | #define regi_iop_fifo_out1_extra (regi_iop + 256) | ||
| 9 | #define regi_iop_trigger_grp0 (regi_iop + 320) | ||
| 10 | #define regi_iop_trigger_grp1 (regi_iop + 384) | ||
| 11 | #define regi_iop_trigger_grp2 (regi_iop + 448) | ||
| 12 | #define regi_iop_trigger_grp3 (regi_iop + 512) | ||
| 13 | #define regi_iop_trigger_grp4 (regi_iop + 576) | ||
| 14 | #define regi_iop_trigger_grp5 (regi_iop + 640) | ||
| 15 | #define regi_iop_trigger_grp6 (regi_iop + 704) | ||
| 16 | #define regi_iop_trigger_grp7 (regi_iop + 768) | ||
| 17 | #define regi_iop_crc_par0 (regi_iop + 896) | ||
| 18 | #define regi_iop_crc_par1 (regi_iop + 1024) | ||
| 19 | #define regi_iop_dmc_in0 (regi_iop + 1152) | ||
| 20 | #define regi_iop_dmc_in1 (regi_iop + 1280) | ||
| 21 | #define regi_iop_dmc_out0 (regi_iop + 1408) | ||
| 22 | #define regi_iop_dmc_out1 (regi_iop + 1536) | ||
| 23 | #define regi_iop_fifo_in0 (regi_iop + 1664) | ||
| 24 | #define regi_iop_fifo_in1 (regi_iop + 1792) | ||
| 25 | #define regi_iop_fifo_out0 (regi_iop + 1920) | ||
| 26 | #define regi_iop_fifo_out1 (regi_iop + 2048) | ||
| 27 | #define regi_iop_scrc_in0 (regi_iop + 2176) | ||
| 28 | #define regi_iop_scrc_in1 (regi_iop + 2304) | ||
| 29 | #define regi_iop_scrc_out0 (regi_iop + 2432) | ||
| 30 | #define regi_iop_scrc_out1 (regi_iop + 2560) | ||
| 31 | #define regi_iop_timer_grp0 (regi_iop + 2688) | ||
| 32 | #define regi_iop_timer_grp1 (regi_iop + 2816) | ||
| 33 | #define regi_iop_timer_grp2 (regi_iop + 2944) | ||
| 34 | #define regi_iop_timer_grp3 (regi_iop + 3072) | ||
| 35 | #define regi_iop_sap_in (regi_iop + 3328) | ||
| 36 | #define regi_iop_sap_out (regi_iop + 3584) | ||
| 37 | #define regi_iop_spu0 (regi_iop + 3840) | ||
| 38 | #define regi_iop_spu1 (regi_iop + 4096) | ||
| 39 | #define regi_iop_sw_cfg (regi_iop + 4352) | ||
| 40 | #define regi_iop_sw_cpu (regi_iop + 4608) | ||
| 41 | #define regi_iop_sw_mpu (regi_iop + 4864) | ||
| 42 | #define regi_iop_sw_spu0 (regi_iop + 5120) | ||
| 43 | #define regi_iop_sw_spu1 (regi_iop + 5376) | ||
| 44 | #define regi_iop_mpu (regi_iop + 5632) | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 5548ac10074f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h +++ /dev/null | |||
| @@ -1,179 +0,0 @@ | |||
| 1 | #ifndef __iop_sap_in_defs_h | ||
| 2 | #define __iop_sap_in_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_sap_in.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:08:45 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r | ||
| 11 | * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_sap_in */ | ||
| 86 | |||
| 87 | /* Register rw_bus0_sync, scope iop_sap_in, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int byte0_sel : 2; | ||
| 90 | unsigned int byte0_ext_src : 3; | ||
| 91 | unsigned int byte0_edge : 2; | ||
| 92 | unsigned int byte0_delay : 1; | ||
| 93 | unsigned int byte1_sel : 2; | ||
| 94 | unsigned int byte1_ext_src : 3; | ||
| 95 | unsigned int byte1_edge : 2; | ||
| 96 | unsigned int byte1_delay : 1; | ||
| 97 | unsigned int byte2_sel : 2; | ||
| 98 | unsigned int byte2_ext_src : 3; | ||
| 99 | unsigned int byte2_edge : 2; | ||
| 100 | unsigned int byte2_delay : 1; | ||
| 101 | unsigned int byte3_sel : 2; | ||
| 102 | unsigned int byte3_ext_src : 3; | ||
| 103 | unsigned int byte3_edge : 2; | ||
| 104 | unsigned int byte3_delay : 1; | ||
| 105 | } reg_iop_sap_in_rw_bus0_sync; | ||
| 106 | #define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 | ||
| 107 | #define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 | ||
| 108 | |||
| 109 | /* Register rw_bus1_sync, scope iop_sap_in, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int byte0_sel : 2; | ||
| 112 | unsigned int byte0_ext_src : 3; | ||
| 113 | unsigned int byte0_edge : 2; | ||
| 114 | unsigned int byte0_delay : 1; | ||
| 115 | unsigned int byte1_sel : 2; | ||
| 116 | unsigned int byte1_ext_src : 3; | ||
| 117 | unsigned int byte1_edge : 2; | ||
| 118 | unsigned int byte1_delay : 1; | ||
| 119 | unsigned int byte2_sel : 2; | ||
| 120 | unsigned int byte2_ext_src : 3; | ||
| 121 | unsigned int byte2_edge : 2; | ||
| 122 | unsigned int byte2_delay : 1; | ||
| 123 | unsigned int byte3_sel : 2; | ||
| 124 | unsigned int byte3_ext_src : 3; | ||
| 125 | unsigned int byte3_edge : 2; | ||
| 126 | unsigned int byte3_delay : 1; | ||
| 127 | } reg_iop_sap_in_rw_bus1_sync; | ||
| 128 | #define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 | ||
| 129 | #define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 | ||
| 130 | |||
| 131 | #define STRIDE_iop_sap_in_rw_gio 4 | ||
| 132 | /* Register rw_gio, scope iop_sap_in, type rw */ | ||
| 133 | typedef struct { | ||
| 134 | unsigned int sync_sel : 2; | ||
| 135 | unsigned int sync_ext_src : 3; | ||
| 136 | unsigned int sync_edge : 2; | ||
| 137 | unsigned int delay : 1; | ||
| 138 | unsigned int logic : 2; | ||
| 139 | unsigned int dummy1 : 22; | ||
| 140 | } reg_iop_sap_in_rw_gio; | ||
| 141 | #define REG_RD_ADDR_iop_sap_in_rw_gio 8 | ||
| 142 | #define REG_WR_ADDR_iop_sap_in_rw_gio 8 | ||
| 143 | |||
| 144 | |||
| 145 | /* Constants */ | ||
| 146 | enum { | ||
| 147 | regk_iop_sap_in_and = 0x00000002, | ||
| 148 | regk_iop_sap_in_ext_clk200 = 0x00000003, | ||
| 149 | regk_iop_sap_in_gio1 = 0x00000000, | ||
| 150 | regk_iop_sap_in_gio13 = 0x00000005, | ||
| 151 | regk_iop_sap_in_gio18 = 0x00000003, | ||
| 152 | regk_iop_sap_in_gio19 = 0x00000004, | ||
| 153 | regk_iop_sap_in_gio21 = 0x00000006, | ||
| 154 | regk_iop_sap_in_gio23 = 0x00000005, | ||
| 155 | regk_iop_sap_in_gio29 = 0x00000007, | ||
| 156 | regk_iop_sap_in_gio5 = 0x00000004, | ||
| 157 | regk_iop_sap_in_gio6 = 0x00000001, | ||
| 158 | regk_iop_sap_in_gio7 = 0x00000002, | ||
| 159 | regk_iop_sap_in_inv = 0x00000001, | ||
| 160 | regk_iop_sap_in_neg = 0x00000002, | ||
| 161 | regk_iop_sap_in_no = 0x00000000, | ||
| 162 | regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, | ||
| 163 | regk_iop_sap_in_none = 0x00000000, | ||
| 164 | regk_iop_sap_in_or = 0x00000003, | ||
| 165 | regk_iop_sap_in_pos = 0x00000001, | ||
| 166 | regk_iop_sap_in_pos_neg = 0x00000003, | ||
| 167 | regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, | ||
| 168 | regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, | ||
| 169 | regk_iop_sap_in_rw_gio_default = 0x00000002, | ||
| 170 | regk_iop_sap_in_rw_gio_size = 0x00000020, | ||
| 171 | regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, | ||
| 172 | regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, | ||
| 173 | regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, | ||
| 174 | regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, | ||
| 175 | regk_iop_sap_in_tmr_clk200 = 0x00000000, | ||
| 176 | regk_iop_sap_in_two_clk200 = 0x00000002, | ||
| 177 | regk_iop_sap_in_yes = 0x00000001 | ||
| 178 | }; | ||
| 179 | #endif /* __iop_sap_in_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 273936996183..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h +++ /dev/null | |||
| @@ -1,306 +0,0 @@ | |||
| 1 | #ifndef __iop_sap_out_defs_h | ||
| 2 | #define __iop_sap_out_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_sap_out.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r | ||
| 11 | * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_sap_out */ | ||
| 86 | |||
| 87 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int clk0_src : 2; | ||
| 90 | unsigned int clk0_gate_src : 2; | ||
| 91 | unsigned int clk0_force_src : 3; | ||
| 92 | unsigned int clk1_src : 2; | ||
| 93 | unsigned int clk1_gate_src : 2; | ||
| 94 | unsigned int clk1_force_src : 3; | ||
| 95 | unsigned int clk2_src : 2; | ||
| 96 | unsigned int clk2_gate_src : 2; | ||
| 97 | unsigned int clk2_force_src : 3; | ||
| 98 | unsigned int clk3_src : 2; | ||
| 99 | unsigned int clk3_gate_src : 2; | ||
| 100 | unsigned int clk3_force_src : 3; | ||
| 101 | unsigned int dummy1 : 4; | ||
| 102 | } reg_iop_sap_out_rw_gen_gated; | ||
| 103 | #define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 | ||
| 104 | #define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 | ||
| 105 | |||
| 106 | /* Register rw_bus0, scope iop_sap_out, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int byte0_clk_sel : 3; | ||
| 109 | unsigned int byte0_gated_clk : 2; | ||
| 110 | unsigned int byte0_clk_inv : 1; | ||
| 111 | unsigned int byte1_clk_sel : 3; | ||
| 112 | unsigned int byte1_gated_clk : 2; | ||
| 113 | unsigned int byte1_clk_inv : 1; | ||
| 114 | unsigned int byte2_clk_sel : 3; | ||
| 115 | unsigned int byte2_gated_clk : 2; | ||
| 116 | unsigned int byte2_clk_inv : 1; | ||
| 117 | unsigned int byte3_clk_sel : 3; | ||
| 118 | unsigned int byte3_gated_clk : 2; | ||
| 119 | unsigned int byte3_clk_inv : 1; | ||
| 120 | unsigned int dummy1 : 8; | ||
| 121 | } reg_iop_sap_out_rw_bus0; | ||
| 122 | #define REG_RD_ADDR_iop_sap_out_rw_bus0 4 | ||
| 123 | #define REG_WR_ADDR_iop_sap_out_rw_bus0 4 | ||
| 124 | |||
| 125 | /* Register rw_bus1, scope iop_sap_out, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int byte0_clk_sel : 3; | ||
| 128 | unsigned int byte0_gated_clk : 2; | ||
| 129 | unsigned int byte0_clk_inv : 1; | ||
| 130 | unsigned int byte1_clk_sel : 3; | ||
| 131 | unsigned int byte1_gated_clk : 2; | ||
| 132 | unsigned int byte1_clk_inv : 1; | ||
| 133 | unsigned int byte2_clk_sel : 3; | ||
| 134 | unsigned int byte2_gated_clk : 2; | ||
| 135 | unsigned int byte2_clk_inv : 1; | ||
| 136 | unsigned int byte3_clk_sel : 3; | ||
| 137 | unsigned int byte3_gated_clk : 2; | ||
| 138 | unsigned int byte3_clk_inv : 1; | ||
| 139 | unsigned int dummy1 : 8; | ||
| 140 | } reg_iop_sap_out_rw_bus1; | ||
| 141 | #define REG_RD_ADDR_iop_sap_out_rw_bus1 8 | ||
| 142 | #define REG_WR_ADDR_iop_sap_out_rw_bus1 8 | ||
| 143 | |||
| 144 | /* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ | ||
| 145 | typedef struct { | ||
| 146 | unsigned int byte0_clk_sel : 3; | ||
| 147 | unsigned int byte0_clk_ext : 3; | ||
| 148 | unsigned int byte0_gated_clk : 2; | ||
| 149 | unsigned int byte0_clk_inv : 1; | ||
| 150 | unsigned int byte0_logic : 2; | ||
| 151 | unsigned int byte1_clk_sel : 3; | ||
| 152 | unsigned int byte1_clk_ext : 3; | ||
| 153 | unsigned int byte1_gated_clk : 2; | ||
| 154 | unsigned int byte1_clk_inv : 1; | ||
| 155 | unsigned int byte1_logic : 2; | ||
| 156 | unsigned int dummy1 : 10; | ||
| 157 | } reg_iop_sap_out_rw_bus0_lo_oe; | ||
| 158 | #define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12 | ||
| 159 | #define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12 | ||
| 160 | |||
| 161 | /* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ | ||
| 162 | typedef struct { | ||
| 163 | unsigned int byte2_clk_sel : 3; | ||
| 164 | unsigned int byte2_clk_ext : 3; | ||
| 165 | unsigned int byte2_gated_clk : 2; | ||
| 166 | unsigned int byte2_clk_inv : 1; | ||
| 167 | unsigned int byte2_logic : 2; | ||
| 168 | unsigned int byte3_clk_sel : 3; | ||
| 169 | unsigned int byte3_clk_ext : 3; | ||
| 170 | unsigned int byte3_gated_clk : 2; | ||
| 171 | unsigned int byte3_clk_inv : 1; | ||
| 172 | unsigned int byte3_logic : 2; | ||
| 173 | unsigned int dummy1 : 10; | ||
| 174 | } reg_iop_sap_out_rw_bus0_hi_oe; | ||
| 175 | #define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16 | ||
| 176 | #define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16 | ||
| 177 | |||
| 178 | /* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ | ||
| 179 | typedef struct { | ||
| 180 | unsigned int byte0_clk_sel : 3; | ||
| 181 | unsigned int byte0_clk_ext : 3; | ||
| 182 | unsigned int byte0_gated_clk : 2; | ||
| 183 | unsigned int byte0_clk_inv : 1; | ||
| 184 | unsigned int byte0_logic : 2; | ||
| 185 | unsigned int byte1_clk_sel : 3; | ||
| 186 | unsigned int byte1_clk_ext : 3; | ||
| 187 | unsigned int byte1_gated_clk : 2; | ||
| 188 | unsigned int byte1_clk_inv : 1; | ||
| 189 | unsigned int byte1_logic : 2; | ||
| 190 | unsigned int dummy1 : 10; | ||
| 191 | } reg_iop_sap_out_rw_bus1_lo_oe; | ||
| 192 | #define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20 | ||
| 193 | #define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20 | ||
| 194 | |||
| 195 | /* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ | ||
| 196 | typedef struct { | ||
| 197 | unsigned int byte2_clk_sel : 3; | ||
| 198 | unsigned int byte2_clk_ext : 3; | ||
| 199 | unsigned int byte2_gated_clk : 2; | ||
| 200 | unsigned int byte2_clk_inv : 1; | ||
| 201 | unsigned int byte2_logic : 2; | ||
| 202 | unsigned int byte3_clk_sel : 3; | ||
| 203 | unsigned int byte3_clk_ext : 3; | ||
| 204 | unsigned int byte3_gated_clk : 2; | ||
| 205 | unsigned int byte3_clk_inv : 1; | ||
| 206 | unsigned int byte3_logic : 2; | ||
| 207 | unsigned int dummy1 : 10; | ||
| 208 | } reg_iop_sap_out_rw_bus1_hi_oe; | ||
| 209 | #define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24 | ||
| 210 | #define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24 | ||
| 211 | |||
| 212 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
| 213 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
| 214 | typedef struct { | ||
| 215 | unsigned int out_clk_sel : 3; | ||
| 216 | unsigned int out_clk_ext : 4; | ||
| 217 | unsigned int out_gated_clk : 2; | ||
| 218 | unsigned int out_clk_inv : 1; | ||
| 219 | unsigned int out_logic : 1; | ||
| 220 | unsigned int oe_clk_sel : 3; | ||
| 221 | unsigned int oe_clk_ext : 3; | ||
| 222 | unsigned int oe_gated_clk : 2; | ||
| 223 | unsigned int oe_clk_inv : 1; | ||
| 224 | unsigned int oe_logic : 2; | ||
| 225 | unsigned int dummy1 : 10; | ||
| 226 | } reg_iop_sap_out_rw_gio; | ||
| 227 | #define REG_RD_ADDR_iop_sap_out_rw_gio 28 | ||
| 228 | #define REG_WR_ADDR_iop_sap_out_rw_gio 28 | ||
| 229 | |||
| 230 | |||
| 231 | /* Constants */ | ||
| 232 | enum { | ||
| 233 | regk_iop_sap_out_and = 0x00000002, | ||
| 234 | regk_iop_sap_out_clk0 = 0x00000000, | ||
| 235 | regk_iop_sap_out_clk1 = 0x00000001, | ||
| 236 | regk_iop_sap_out_clk12 = 0x00000002, | ||
| 237 | regk_iop_sap_out_clk2 = 0x00000002, | ||
| 238 | regk_iop_sap_out_clk200 = 0x00000001, | ||
| 239 | regk_iop_sap_out_clk3 = 0x00000003, | ||
| 240 | regk_iop_sap_out_ext = 0x00000003, | ||
| 241 | regk_iop_sap_out_gated = 0x00000004, | ||
| 242 | regk_iop_sap_out_gio1 = 0x00000000, | ||
| 243 | regk_iop_sap_out_gio13 = 0x00000002, | ||
| 244 | regk_iop_sap_out_gio13_clk = 0x0000000c, | ||
| 245 | regk_iop_sap_out_gio15 = 0x00000001, | ||
| 246 | regk_iop_sap_out_gio18 = 0x00000003, | ||
| 247 | regk_iop_sap_out_gio18_clk = 0x0000000d, | ||
| 248 | regk_iop_sap_out_gio1_clk = 0x00000008, | ||
| 249 | regk_iop_sap_out_gio21_clk = 0x0000000e, | ||
| 250 | regk_iop_sap_out_gio23 = 0x00000002, | ||
| 251 | regk_iop_sap_out_gio29_clk = 0x0000000f, | ||
| 252 | regk_iop_sap_out_gio31 = 0x00000003, | ||
| 253 | regk_iop_sap_out_gio5 = 0x00000001, | ||
| 254 | regk_iop_sap_out_gio5_clk = 0x00000009, | ||
| 255 | regk_iop_sap_out_gio6_clk = 0x0000000a, | ||
| 256 | regk_iop_sap_out_gio7 = 0x00000000, | ||
| 257 | regk_iop_sap_out_gio7_clk = 0x0000000b, | ||
| 258 | regk_iop_sap_out_gio_in13 = 0x00000001, | ||
| 259 | regk_iop_sap_out_gio_in21 = 0x00000002, | ||
| 260 | regk_iop_sap_out_gio_in29 = 0x00000003, | ||
| 261 | regk_iop_sap_out_gio_in5 = 0x00000000, | ||
| 262 | regk_iop_sap_out_inv = 0x00000001, | ||
| 263 | regk_iop_sap_out_nand = 0x00000003, | ||
| 264 | regk_iop_sap_out_no = 0x00000000, | ||
| 265 | regk_iop_sap_out_none = 0x00000000, | ||
| 266 | regk_iop_sap_out_rw_bus0_default = 0x00000000, | ||
| 267 | regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000, | ||
| 268 | regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000, | ||
| 269 | regk_iop_sap_out_rw_bus1_default = 0x00000000, | ||
| 270 | regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000, | ||
| 271 | regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000, | ||
| 272 | regk_iop_sap_out_rw_gen_gated_default = 0x00000000, | ||
| 273 | regk_iop_sap_out_rw_gio_default = 0x00000000, | ||
| 274 | regk_iop_sap_out_rw_gio_size = 0x00000020, | ||
| 275 | regk_iop_sap_out_spu0_gio0 = 0x00000002, | ||
| 276 | regk_iop_sap_out_spu0_gio1 = 0x00000003, | ||
| 277 | regk_iop_sap_out_spu0_gio12 = 0x00000004, | ||
| 278 | regk_iop_sap_out_spu0_gio13 = 0x00000004, | ||
| 279 | regk_iop_sap_out_spu0_gio14 = 0x00000004, | ||
| 280 | regk_iop_sap_out_spu0_gio15 = 0x00000004, | ||
| 281 | regk_iop_sap_out_spu0_gio2 = 0x00000002, | ||
| 282 | regk_iop_sap_out_spu0_gio3 = 0x00000003, | ||
| 283 | regk_iop_sap_out_spu0_gio4 = 0x00000002, | ||
| 284 | regk_iop_sap_out_spu0_gio5 = 0x00000003, | ||
| 285 | regk_iop_sap_out_spu0_gio6 = 0x00000002, | ||
| 286 | regk_iop_sap_out_spu0_gio7 = 0x00000003, | ||
| 287 | regk_iop_sap_out_spu1_gio0 = 0x00000005, | ||
| 288 | regk_iop_sap_out_spu1_gio1 = 0x00000006, | ||
| 289 | regk_iop_sap_out_spu1_gio12 = 0x00000007, | ||
| 290 | regk_iop_sap_out_spu1_gio13 = 0x00000007, | ||
| 291 | regk_iop_sap_out_spu1_gio14 = 0x00000007, | ||
| 292 | regk_iop_sap_out_spu1_gio15 = 0x00000007, | ||
| 293 | regk_iop_sap_out_spu1_gio2 = 0x00000005, | ||
| 294 | regk_iop_sap_out_spu1_gio3 = 0x00000006, | ||
| 295 | regk_iop_sap_out_spu1_gio4 = 0x00000005, | ||
| 296 | regk_iop_sap_out_spu1_gio5 = 0x00000006, | ||
| 297 | regk_iop_sap_out_spu1_gio6 = 0x00000005, | ||
| 298 | regk_iop_sap_out_spu1_gio7 = 0x00000006, | ||
| 299 | regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004, | ||
| 300 | regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005, | ||
| 301 | regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006, | ||
| 302 | regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007, | ||
| 303 | regk_iop_sap_out_tmr = 0x00000005, | ||
| 304 | regk_iop_sap_out_yes = 0x00000001 | ||
| 305 | }; | ||
| 306 | #endif /* __iop_sap_out_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h deleted file mode 100644 index 4f0a9a81e737..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h +++ /dev/null | |||
| @@ -1,160 +0,0 @@ | |||
| 1 | #ifndef __iop_scrc_in_defs_h | ||
| 2 | #define __iop_scrc_in_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_scrc_in.r | ||
| 7 | * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r | ||
| 11 | * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_scrc_in */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope iop_scrc_in, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int trig : 2; | ||
| 90 | unsigned int dummy1 : 30; | ||
| 91 | } reg_iop_scrc_in_rw_cfg; | ||
| 92 | #define REG_RD_ADDR_iop_scrc_in_rw_cfg 0 | ||
| 93 | #define REG_WR_ADDR_iop_scrc_in_rw_cfg 0 | ||
| 94 | |||
| 95 | /* Register rw_ctrl, scope iop_scrc_in, type rw */ | ||
| 96 | typedef struct { | ||
| 97 | unsigned int dif_in_en : 1; | ||
| 98 | unsigned int dummy1 : 31; | ||
| 99 | } reg_iop_scrc_in_rw_ctrl; | ||
| 100 | #define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4 | ||
| 101 | #define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4 | ||
| 102 | |||
| 103 | /* Register r_stat, scope iop_scrc_in, type r */ | ||
| 104 | typedef struct { | ||
| 105 | unsigned int err : 1; | ||
| 106 | unsigned int dummy1 : 31; | ||
| 107 | } reg_iop_scrc_in_r_stat; | ||
| 108 | #define REG_RD_ADDR_iop_scrc_in_r_stat 8 | ||
| 109 | |||
| 110 | /* Register rw_init_crc, scope iop_scrc_in, type rw */ | ||
| 111 | typedef unsigned int reg_iop_scrc_in_rw_init_crc; | ||
| 112 | #define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12 | ||
| 113 | #define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12 | ||
| 114 | |||
| 115 | /* Register rs_computed_crc, scope iop_scrc_in, type rs */ | ||
| 116 | typedef unsigned int reg_iop_scrc_in_rs_computed_crc; | ||
| 117 | #define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16 | ||
| 118 | |||
| 119 | /* Register r_computed_crc, scope iop_scrc_in, type r */ | ||
| 120 | typedef unsigned int reg_iop_scrc_in_r_computed_crc; | ||
| 121 | #define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20 | ||
| 122 | |||
| 123 | /* Register rw_crc, scope iop_scrc_in, type rw */ | ||
| 124 | typedef unsigned int reg_iop_scrc_in_rw_crc; | ||
| 125 | #define REG_RD_ADDR_iop_scrc_in_rw_crc 24 | ||
| 126 | #define REG_WR_ADDR_iop_scrc_in_rw_crc 24 | ||
| 127 | |||
| 128 | /* Register rw_correct_crc, scope iop_scrc_in, type rw */ | ||
| 129 | typedef unsigned int reg_iop_scrc_in_rw_correct_crc; | ||
| 130 | #define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28 | ||
| 131 | #define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28 | ||
| 132 | |||
| 133 | /* Register rw_wr1bit, scope iop_scrc_in, type rw */ | ||
| 134 | typedef struct { | ||
| 135 | unsigned int data : 2; | ||
| 136 | unsigned int last : 2; | ||
| 137 | unsigned int dummy1 : 28; | ||
| 138 | } reg_iop_scrc_in_rw_wr1bit; | ||
| 139 | #define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32 | ||
| 140 | #define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32 | ||
| 141 | |||
| 142 | |||
| 143 | /* Constants */ | ||
| 144 | enum { | ||
| 145 | regk_iop_scrc_in_dif_in = 0x00000002, | ||
| 146 | regk_iop_scrc_in_hi = 0x00000000, | ||
| 147 | regk_iop_scrc_in_neg = 0x00000002, | ||
| 148 | regk_iop_scrc_in_no = 0x00000000, | ||
| 149 | regk_iop_scrc_in_pos = 0x00000001, | ||
| 150 | regk_iop_scrc_in_pos_neg = 0x00000003, | ||
| 151 | regk_iop_scrc_in_r_computed_crc_default = 0x00000000, | ||
| 152 | regk_iop_scrc_in_rs_computed_crc_default = 0x00000000, | ||
| 153 | regk_iop_scrc_in_rw_cfg_default = 0x00000000, | ||
| 154 | regk_iop_scrc_in_rw_ctrl_default = 0x00000000, | ||
| 155 | regk_iop_scrc_in_rw_init_crc_default = 0x00000000, | ||
| 156 | regk_iop_scrc_in_set0 = 0x00000000, | ||
| 157 | regk_iop_scrc_in_set1 = 0x00000001, | ||
| 158 | regk_iop_scrc_in_yes = 0x00000001 | ||
| 159 | }; | ||
| 160 | #endif /* __iop_scrc_in_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h deleted file mode 100644 index fd1d6ea1d484..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h +++ /dev/null | |||
| @@ -1,146 +0,0 @@ | |||
| 1 | #ifndef __iop_scrc_out_defs_h | ||
| 2 | #define __iop_scrc_out_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_scrc_out.r | ||
| 7 | * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r | ||
| 11 | * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_scrc_out */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope iop_scrc_out, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int trig : 2; | ||
| 90 | unsigned int inv_crc : 1; | ||
| 91 | unsigned int dummy1 : 29; | ||
| 92 | } reg_iop_scrc_out_rw_cfg; | ||
| 93 | #define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 | ||
| 94 | #define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 | ||
| 95 | |||
| 96 | /* Register rw_ctrl, scope iop_scrc_out, type rw */ | ||
| 97 | typedef struct { | ||
| 98 | unsigned int strb_src : 1; | ||
| 99 | unsigned int out_src : 1; | ||
| 100 | unsigned int dummy1 : 30; | ||
| 101 | } reg_iop_scrc_out_rw_ctrl; | ||
| 102 | #define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 | ||
| 103 | #define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 | ||
| 104 | |||
| 105 | /* Register rw_init_crc, scope iop_scrc_out, type rw */ | ||
| 106 | typedef unsigned int reg_iop_scrc_out_rw_init_crc; | ||
| 107 | #define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 | ||
| 108 | #define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 | ||
| 109 | |||
| 110 | /* Register rw_crc, scope iop_scrc_out, type rw */ | ||
| 111 | typedef unsigned int reg_iop_scrc_out_rw_crc; | ||
| 112 | #define REG_RD_ADDR_iop_scrc_out_rw_crc 12 | ||
| 113 | #define REG_WR_ADDR_iop_scrc_out_rw_crc 12 | ||
| 114 | |||
| 115 | /* Register rw_data, scope iop_scrc_out, type rw */ | ||
| 116 | typedef struct { | ||
| 117 | unsigned int val : 1; | ||
| 118 | unsigned int dummy1 : 31; | ||
| 119 | } reg_iop_scrc_out_rw_data; | ||
| 120 | #define REG_RD_ADDR_iop_scrc_out_rw_data 16 | ||
| 121 | #define REG_WR_ADDR_iop_scrc_out_rw_data 16 | ||
| 122 | |||
| 123 | /* Register r_computed_crc, scope iop_scrc_out, type r */ | ||
| 124 | typedef unsigned int reg_iop_scrc_out_r_computed_crc; | ||
| 125 | #define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 | ||
| 126 | |||
| 127 | |||
| 128 | /* Constants */ | ||
| 129 | enum { | ||
| 130 | regk_iop_scrc_out_crc = 0x00000001, | ||
| 131 | regk_iop_scrc_out_data = 0x00000000, | ||
| 132 | regk_iop_scrc_out_dif = 0x00000001, | ||
| 133 | regk_iop_scrc_out_hi = 0x00000000, | ||
| 134 | regk_iop_scrc_out_neg = 0x00000002, | ||
| 135 | regk_iop_scrc_out_no = 0x00000000, | ||
| 136 | regk_iop_scrc_out_pos = 0x00000001, | ||
| 137 | regk_iop_scrc_out_pos_neg = 0x00000003, | ||
| 138 | regk_iop_scrc_out_reg = 0x00000000, | ||
| 139 | regk_iop_scrc_out_rw_cfg_default = 0x00000000, | ||
| 140 | regk_iop_scrc_out_rw_crc_default = 0x00000000, | ||
| 141 | regk_iop_scrc_out_rw_ctrl_default = 0x00000000, | ||
| 142 | regk_iop_scrc_out_rw_data_default = 0x00000000, | ||
| 143 | regk_iop_scrc_out_rw_init_crc_default = 0x00000000, | ||
| 144 | regk_iop_scrc_out_yes = 0x00000001 | ||
| 145 | }; | ||
| 146 | #endif /* __iop_scrc_out_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h deleted file mode 100644 index 0fda26e2f06f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h +++ /dev/null | |||
| @@ -1,453 +0,0 @@ | |||
| 1 | #ifndef __iop_spu_defs_h | ||
| 2 | #define __iop_spu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_spu.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r | ||
| 11 | * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_spu */ | ||
| 86 | |||
| 87 | #define STRIDE_iop_spu_rw_r 4 | ||
| 88 | /* Register rw_r, scope iop_spu, type rw */ | ||
| 89 | typedef unsigned int reg_iop_spu_rw_r; | ||
| 90 | #define REG_RD_ADDR_iop_spu_rw_r 0 | ||
| 91 | #define REG_WR_ADDR_iop_spu_rw_r 0 | ||
| 92 | |||
| 93 | /* Register rw_seq_pc, scope iop_spu, type rw */ | ||
| 94 | typedef struct { | ||
| 95 | unsigned int addr : 12; | ||
| 96 | unsigned int dummy1 : 20; | ||
| 97 | } reg_iop_spu_rw_seq_pc; | ||
| 98 | #define REG_RD_ADDR_iop_spu_rw_seq_pc 64 | ||
| 99 | #define REG_WR_ADDR_iop_spu_rw_seq_pc 64 | ||
| 100 | |||
| 101 | /* Register rw_fsm_pc, scope iop_spu, type rw */ | ||
| 102 | typedef struct { | ||
| 103 | unsigned int addr : 12; | ||
| 104 | unsigned int dummy1 : 20; | ||
| 105 | } reg_iop_spu_rw_fsm_pc; | ||
| 106 | #define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 | ||
| 107 | #define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 | ||
| 108 | |||
| 109 | /* Register rw_ctrl, scope iop_spu, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int fsm : 1; | ||
| 112 | unsigned int en : 1; | ||
| 113 | unsigned int dummy1 : 30; | ||
| 114 | } reg_iop_spu_rw_ctrl; | ||
| 115 | #define REG_RD_ADDR_iop_spu_rw_ctrl 72 | ||
| 116 | #define REG_WR_ADDR_iop_spu_rw_ctrl 72 | ||
| 117 | |||
| 118 | /* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ | ||
| 119 | typedef struct { | ||
| 120 | unsigned int val0 : 5; | ||
| 121 | unsigned int src0 : 3; | ||
| 122 | unsigned int val1 : 5; | ||
| 123 | unsigned int src1 : 3; | ||
| 124 | unsigned int val2 : 5; | ||
| 125 | unsigned int src2 : 3; | ||
| 126 | unsigned int val3 : 5; | ||
| 127 | unsigned int src3 : 3; | ||
| 128 | } reg_iop_spu_rw_fsm_inputs3_0; | ||
| 129 | #define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 | ||
| 130 | #define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 | ||
| 131 | |||
| 132 | /* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ | ||
| 133 | typedef struct { | ||
| 134 | unsigned int val4 : 5; | ||
| 135 | unsigned int src4 : 3; | ||
| 136 | unsigned int val5 : 5; | ||
| 137 | unsigned int src5 : 3; | ||
| 138 | unsigned int val6 : 5; | ||
| 139 | unsigned int src6 : 3; | ||
| 140 | unsigned int val7 : 5; | ||
| 141 | unsigned int src7 : 3; | ||
| 142 | } reg_iop_spu_rw_fsm_inputs7_4; | ||
| 143 | #define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 | ||
| 144 | #define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 | ||
| 145 | |||
| 146 | /* Register rw_gio_out, scope iop_spu, type rw */ | ||
| 147 | typedef unsigned int reg_iop_spu_rw_gio_out; | ||
| 148 | #define REG_RD_ADDR_iop_spu_rw_gio_out 84 | ||
| 149 | #define REG_WR_ADDR_iop_spu_rw_gio_out 84 | ||
| 150 | |||
| 151 | /* Register rw_bus0_out, scope iop_spu, type rw */ | ||
| 152 | typedef unsigned int reg_iop_spu_rw_bus0_out; | ||
| 153 | #define REG_RD_ADDR_iop_spu_rw_bus0_out 88 | ||
| 154 | #define REG_WR_ADDR_iop_spu_rw_bus0_out 88 | ||
| 155 | |||
| 156 | /* Register rw_bus1_out, scope iop_spu, type rw */ | ||
| 157 | typedef unsigned int reg_iop_spu_rw_bus1_out; | ||
| 158 | #define REG_RD_ADDR_iop_spu_rw_bus1_out 92 | ||
| 159 | #define REG_WR_ADDR_iop_spu_rw_bus1_out 92 | ||
| 160 | |||
| 161 | /* Register r_gio_in, scope iop_spu, type r */ | ||
| 162 | typedef unsigned int reg_iop_spu_r_gio_in; | ||
| 163 | #define REG_RD_ADDR_iop_spu_r_gio_in 96 | ||
| 164 | |||
| 165 | /* Register r_bus0_in, scope iop_spu, type r */ | ||
| 166 | typedef unsigned int reg_iop_spu_r_bus0_in; | ||
| 167 | #define REG_RD_ADDR_iop_spu_r_bus0_in 100 | ||
| 168 | |||
| 169 | /* Register r_bus1_in, scope iop_spu, type r */ | ||
| 170 | typedef unsigned int reg_iop_spu_r_bus1_in; | ||
| 171 | #define REG_RD_ADDR_iop_spu_r_bus1_in 104 | ||
| 172 | |||
| 173 | /* Register rw_gio_out_set, scope iop_spu, type rw */ | ||
| 174 | typedef unsigned int reg_iop_spu_rw_gio_out_set; | ||
| 175 | #define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 | ||
| 176 | #define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 | ||
| 177 | |||
| 178 | /* Register rw_gio_out_clr, scope iop_spu, type rw */ | ||
| 179 | typedef unsigned int reg_iop_spu_rw_gio_out_clr; | ||
| 180 | #define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 | ||
| 181 | #define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 | ||
| 182 | |||
| 183 | /* Register rs_wr_stat, scope iop_spu, type rs */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int r0 : 1; | ||
| 186 | unsigned int r1 : 1; | ||
| 187 | unsigned int r2 : 1; | ||
| 188 | unsigned int r3 : 1; | ||
| 189 | unsigned int r4 : 1; | ||
| 190 | unsigned int r5 : 1; | ||
| 191 | unsigned int r6 : 1; | ||
| 192 | unsigned int r7 : 1; | ||
| 193 | unsigned int r8 : 1; | ||
| 194 | unsigned int r9 : 1; | ||
| 195 | unsigned int r10 : 1; | ||
| 196 | unsigned int r11 : 1; | ||
| 197 | unsigned int r12 : 1; | ||
| 198 | unsigned int r13 : 1; | ||
| 199 | unsigned int r14 : 1; | ||
| 200 | unsigned int r15 : 1; | ||
| 201 | unsigned int dummy1 : 16; | ||
| 202 | } reg_iop_spu_rs_wr_stat; | ||
| 203 | #define REG_RD_ADDR_iop_spu_rs_wr_stat 116 | ||
| 204 | |||
| 205 | /* Register r_wr_stat, scope iop_spu, type r */ | ||
| 206 | typedef struct { | ||
| 207 | unsigned int r0 : 1; | ||
| 208 | unsigned int r1 : 1; | ||
| 209 | unsigned int r2 : 1; | ||
| 210 | unsigned int r3 : 1; | ||
| 211 | unsigned int r4 : 1; | ||
| 212 | unsigned int r5 : 1; | ||
| 213 | unsigned int r6 : 1; | ||
| 214 | unsigned int r7 : 1; | ||
| 215 | unsigned int r8 : 1; | ||
| 216 | unsigned int r9 : 1; | ||
| 217 | unsigned int r10 : 1; | ||
| 218 | unsigned int r11 : 1; | ||
| 219 | unsigned int r12 : 1; | ||
| 220 | unsigned int r13 : 1; | ||
| 221 | unsigned int r14 : 1; | ||
| 222 | unsigned int r15 : 1; | ||
| 223 | unsigned int dummy1 : 16; | ||
| 224 | } reg_iop_spu_r_wr_stat; | ||
| 225 | #define REG_RD_ADDR_iop_spu_r_wr_stat 120 | ||
| 226 | |||
| 227 | /* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ | ||
| 228 | typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; | ||
| 229 | #define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 | ||
| 230 | |||
| 231 | /* Register r_stat_in, scope iop_spu, type r */ | ||
| 232 | typedef struct { | ||
| 233 | unsigned int timer_grp_lo : 4; | ||
| 234 | unsigned int fifo_out_last : 1; | ||
| 235 | unsigned int fifo_out_rdy : 1; | ||
| 236 | unsigned int fifo_out_all : 1; | ||
| 237 | unsigned int fifo_in_rdy : 1; | ||
| 238 | unsigned int dmc_out_all : 1; | ||
| 239 | unsigned int dmc_out_dth : 1; | ||
| 240 | unsigned int dmc_out_eop : 1; | ||
| 241 | unsigned int dmc_out_dv : 1; | ||
| 242 | unsigned int dmc_out_last : 1; | ||
| 243 | unsigned int dmc_out_cmd_rq : 1; | ||
| 244 | unsigned int dmc_out_cmd_rdy : 1; | ||
| 245 | unsigned int pcrc_correct : 1; | ||
| 246 | unsigned int timer_grp_hi : 4; | ||
| 247 | unsigned int dmc_in_sth : 1; | ||
| 248 | unsigned int dmc_in_full : 1; | ||
| 249 | unsigned int dmc_in_cmd_rdy : 1; | ||
| 250 | unsigned int spu_gio_out : 4; | ||
| 251 | unsigned int sync_clk12 : 1; | ||
| 252 | unsigned int scrc_out_data : 1; | ||
| 253 | unsigned int scrc_in_err : 1; | ||
| 254 | unsigned int mc_busy : 1; | ||
| 255 | unsigned int mc_owned : 1; | ||
| 256 | } reg_iop_spu_r_stat_in; | ||
| 257 | #define REG_RD_ADDR_iop_spu_r_stat_in 128 | ||
| 258 | |||
| 259 | /* Register r_trigger_in, scope iop_spu, type r */ | ||
| 260 | typedef unsigned int reg_iop_spu_r_trigger_in; | ||
| 261 | #define REG_RD_ADDR_iop_spu_r_trigger_in 132 | ||
| 262 | |||
| 263 | /* Register r_special_stat, scope iop_spu, type r */ | ||
| 264 | typedef struct { | ||
| 265 | unsigned int c_flag : 1; | ||
| 266 | unsigned int v_flag : 1; | ||
| 267 | unsigned int z_flag : 1; | ||
| 268 | unsigned int n_flag : 1; | ||
| 269 | unsigned int xor_bus0_r2_0 : 1; | ||
| 270 | unsigned int xor_bus1_r3_0 : 1; | ||
| 271 | unsigned int xor_bus0m_r2_0 : 1; | ||
| 272 | unsigned int xor_bus1m_r3_0 : 1; | ||
| 273 | unsigned int fsm_in0 : 1; | ||
| 274 | unsigned int fsm_in1 : 1; | ||
| 275 | unsigned int fsm_in2 : 1; | ||
| 276 | unsigned int fsm_in3 : 1; | ||
| 277 | unsigned int fsm_in4 : 1; | ||
| 278 | unsigned int fsm_in5 : 1; | ||
| 279 | unsigned int fsm_in6 : 1; | ||
| 280 | unsigned int fsm_in7 : 1; | ||
| 281 | unsigned int event0 : 1; | ||
| 282 | unsigned int event1 : 1; | ||
| 283 | unsigned int event2 : 1; | ||
| 284 | unsigned int event3 : 1; | ||
| 285 | unsigned int dummy1 : 12; | ||
| 286 | } reg_iop_spu_r_special_stat; | ||
| 287 | #define REG_RD_ADDR_iop_spu_r_special_stat 136 | ||
| 288 | |||
| 289 | /* Register rw_reg_access, scope iop_spu, type rw */ | ||
| 290 | typedef struct { | ||
| 291 | unsigned int addr : 13; | ||
| 292 | unsigned int dummy1 : 3; | ||
| 293 | unsigned int imm_hi : 16; | ||
| 294 | } reg_iop_spu_rw_reg_access; | ||
| 295 | #define REG_RD_ADDR_iop_spu_rw_reg_access 140 | ||
| 296 | #define REG_WR_ADDR_iop_spu_rw_reg_access 140 | ||
| 297 | |||
| 298 | #define STRIDE_iop_spu_rw_event_cfg 4 | ||
| 299 | /* Register rw_event_cfg, scope iop_spu, type rw */ | ||
| 300 | typedef struct { | ||
| 301 | unsigned int addr : 12; | ||
| 302 | unsigned int src : 2; | ||
| 303 | unsigned int eq_en : 1; | ||
| 304 | unsigned int eq_inv : 1; | ||
| 305 | unsigned int gt_en : 1; | ||
| 306 | unsigned int gt_inv : 1; | ||
| 307 | unsigned int dummy1 : 14; | ||
| 308 | } reg_iop_spu_rw_event_cfg; | ||
| 309 | #define REG_RD_ADDR_iop_spu_rw_event_cfg 144 | ||
| 310 | #define REG_WR_ADDR_iop_spu_rw_event_cfg 144 | ||
| 311 | |||
| 312 | #define STRIDE_iop_spu_rw_event_mask 4 | ||
| 313 | /* Register rw_event_mask, scope iop_spu, type rw */ | ||
| 314 | typedef unsigned int reg_iop_spu_rw_event_mask; | ||
| 315 | #define REG_RD_ADDR_iop_spu_rw_event_mask 160 | ||
| 316 | #define REG_WR_ADDR_iop_spu_rw_event_mask 160 | ||
| 317 | |||
| 318 | #define STRIDE_iop_spu_rw_event_val 4 | ||
| 319 | /* Register rw_event_val, scope iop_spu, type rw */ | ||
| 320 | typedef unsigned int reg_iop_spu_rw_event_val; | ||
| 321 | #define REG_RD_ADDR_iop_spu_rw_event_val 176 | ||
| 322 | #define REG_WR_ADDR_iop_spu_rw_event_val 176 | ||
| 323 | |||
| 324 | /* Register rw_event_ret, scope iop_spu, type rw */ | ||
| 325 | typedef struct { | ||
| 326 | unsigned int addr : 12; | ||
| 327 | unsigned int dummy1 : 20; | ||
| 328 | } reg_iop_spu_rw_event_ret; | ||
| 329 | #define REG_RD_ADDR_iop_spu_rw_event_ret 192 | ||
| 330 | #define REG_WR_ADDR_iop_spu_rw_event_ret 192 | ||
| 331 | |||
| 332 | /* Register r_trace, scope iop_spu, type r */ | ||
| 333 | typedef struct { | ||
| 334 | unsigned int fsm : 1; | ||
| 335 | unsigned int en : 1; | ||
| 336 | unsigned int c_flag : 1; | ||
| 337 | unsigned int v_flag : 1; | ||
| 338 | unsigned int z_flag : 1; | ||
| 339 | unsigned int n_flag : 1; | ||
| 340 | unsigned int seq_addr : 12; | ||
| 341 | unsigned int dummy1 : 2; | ||
| 342 | unsigned int fsm_addr : 12; | ||
| 343 | } reg_iop_spu_r_trace; | ||
| 344 | #define REG_RD_ADDR_iop_spu_r_trace 196 | ||
| 345 | |||
| 346 | /* Register r_fsm_trace, scope iop_spu, type r */ | ||
| 347 | typedef struct { | ||
| 348 | unsigned int fsm : 1; | ||
| 349 | unsigned int en : 1; | ||
| 350 | unsigned int tmr_done : 1; | ||
| 351 | unsigned int inp0 : 1; | ||
| 352 | unsigned int inp1 : 1; | ||
| 353 | unsigned int inp2 : 1; | ||
| 354 | unsigned int inp3 : 1; | ||
| 355 | unsigned int event0 : 1; | ||
| 356 | unsigned int event1 : 1; | ||
| 357 | unsigned int event2 : 1; | ||
| 358 | unsigned int event3 : 1; | ||
| 359 | unsigned int gio_out : 8; | ||
| 360 | unsigned int dummy1 : 1; | ||
| 361 | unsigned int fsm_addr : 12; | ||
| 362 | } reg_iop_spu_r_fsm_trace; | ||
| 363 | #define REG_RD_ADDR_iop_spu_r_fsm_trace 200 | ||
| 364 | |||
| 365 | #define STRIDE_iop_spu_rw_brp 4 | ||
| 366 | /* Register rw_brp, scope iop_spu, type rw */ | ||
| 367 | typedef struct { | ||
| 368 | unsigned int addr : 12; | ||
| 369 | unsigned int fsm : 1; | ||
| 370 | unsigned int en : 1; | ||
| 371 | unsigned int dummy1 : 18; | ||
| 372 | } reg_iop_spu_rw_brp; | ||
| 373 | #define REG_RD_ADDR_iop_spu_rw_brp 204 | ||
| 374 | #define REG_WR_ADDR_iop_spu_rw_brp 204 | ||
| 375 | |||
| 376 | |||
| 377 | /* Constants */ | ||
| 378 | enum { | ||
| 379 | regk_iop_spu_attn_hi = 0x00000005, | ||
| 380 | regk_iop_spu_attn_lo = 0x00000005, | ||
| 381 | regk_iop_spu_attn_r0 = 0x00000000, | ||
| 382 | regk_iop_spu_attn_r1 = 0x00000001, | ||
| 383 | regk_iop_spu_attn_r10 = 0x00000002, | ||
| 384 | regk_iop_spu_attn_r11 = 0x00000003, | ||
| 385 | regk_iop_spu_attn_r12 = 0x00000004, | ||
| 386 | regk_iop_spu_attn_r13 = 0x00000005, | ||
| 387 | regk_iop_spu_attn_r14 = 0x00000006, | ||
| 388 | regk_iop_spu_attn_r15 = 0x00000007, | ||
| 389 | regk_iop_spu_attn_r2 = 0x00000002, | ||
| 390 | regk_iop_spu_attn_r3 = 0x00000003, | ||
| 391 | regk_iop_spu_attn_r4 = 0x00000004, | ||
| 392 | regk_iop_spu_attn_r5 = 0x00000005, | ||
| 393 | regk_iop_spu_attn_r6 = 0x00000006, | ||
| 394 | regk_iop_spu_attn_r7 = 0x00000007, | ||
| 395 | regk_iop_spu_attn_r8 = 0x00000000, | ||
| 396 | regk_iop_spu_attn_r9 = 0x00000001, | ||
| 397 | regk_iop_spu_c = 0x00000000, | ||
| 398 | regk_iop_spu_flag = 0x00000002, | ||
| 399 | regk_iop_spu_gio_in = 0x00000000, | ||
| 400 | regk_iop_spu_gio_out = 0x00000005, | ||
| 401 | regk_iop_spu_gio_out0 = 0x00000008, | ||
| 402 | regk_iop_spu_gio_out1 = 0x00000009, | ||
| 403 | regk_iop_spu_gio_out2 = 0x0000000a, | ||
| 404 | regk_iop_spu_gio_out3 = 0x0000000b, | ||
| 405 | regk_iop_spu_gio_out4 = 0x0000000c, | ||
| 406 | regk_iop_spu_gio_out5 = 0x0000000d, | ||
| 407 | regk_iop_spu_gio_out6 = 0x0000000e, | ||
| 408 | regk_iop_spu_gio_out7 = 0x0000000f, | ||
| 409 | regk_iop_spu_n = 0x00000003, | ||
| 410 | regk_iop_spu_no = 0x00000000, | ||
| 411 | regk_iop_spu_r0 = 0x00000008, | ||
| 412 | regk_iop_spu_r1 = 0x00000009, | ||
| 413 | regk_iop_spu_r10 = 0x0000000a, | ||
| 414 | regk_iop_spu_r11 = 0x0000000b, | ||
| 415 | regk_iop_spu_r12 = 0x0000000c, | ||
| 416 | regk_iop_spu_r13 = 0x0000000d, | ||
| 417 | regk_iop_spu_r14 = 0x0000000e, | ||
| 418 | regk_iop_spu_r15 = 0x0000000f, | ||
| 419 | regk_iop_spu_r2 = 0x0000000a, | ||
| 420 | regk_iop_spu_r3 = 0x0000000b, | ||
| 421 | regk_iop_spu_r4 = 0x0000000c, | ||
| 422 | regk_iop_spu_r5 = 0x0000000d, | ||
| 423 | regk_iop_spu_r6 = 0x0000000e, | ||
| 424 | regk_iop_spu_r7 = 0x0000000f, | ||
| 425 | regk_iop_spu_r8 = 0x00000008, | ||
| 426 | regk_iop_spu_r9 = 0x00000009, | ||
| 427 | regk_iop_spu_reg_hi = 0x00000002, | ||
| 428 | regk_iop_spu_reg_lo = 0x00000002, | ||
| 429 | regk_iop_spu_rw_brp_default = 0x00000000, | ||
| 430 | regk_iop_spu_rw_brp_size = 0x00000004, | ||
| 431 | regk_iop_spu_rw_ctrl_default = 0x00000000, | ||
| 432 | regk_iop_spu_rw_event_cfg_size = 0x00000004, | ||
| 433 | regk_iop_spu_rw_event_mask_size = 0x00000004, | ||
| 434 | regk_iop_spu_rw_event_val_size = 0x00000004, | ||
| 435 | regk_iop_spu_rw_gio_out_default = 0x00000000, | ||
| 436 | regk_iop_spu_rw_r_size = 0x00000010, | ||
| 437 | regk_iop_spu_rw_reg_access_default = 0x00000000, | ||
| 438 | regk_iop_spu_stat_in = 0x00000002, | ||
| 439 | regk_iop_spu_statin_hi = 0x00000004, | ||
| 440 | regk_iop_spu_statin_lo = 0x00000004, | ||
| 441 | regk_iop_spu_trig = 0x00000003, | ||
| 442 | regk_iop_spu_trigger = 0x00000006, | ||
| 443 | regk_iop_spu_v = 0x00000001, | ||
| 444 | regk_iop_spu_wsts_gioout_spec = 0x00000001, | ||
| 445 | regk_iop_spu_xor = 0x00000003, | ||
| 446 | regk_iop_spu_xor_bus0_r2_0 = 0x00000000, | ||
| 447 | regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, | ||
| 448 | regk_iop_spu_xor_bus1_r3_0 = 0x00000001, | ||
| 449 | regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, | ||
| 450 | regk_iop_spu_yes = 0x00000001, | ||
| 451 | regk_iop_spu_z = 0x00000002 | ||
| 452 | }; | ||
| 453 | #endif /* __iop_spu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index d7b6d75884d2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null | |||
| @@ -1,1042 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_cfg_defs_h | ||
| 2 | #define __iop_sw_cfg_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:19 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r | ||
| 11 | * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_sw_cfg */ | ||
| 86 | |||
| 87 | /* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int cfg : 2; | ||
| 90 | unsigned int dummy1 : 30; | ||
| 91 | } reg_iop_sw_cfg_rw_crc_par0_owner; | ||
| 92 | #define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 | ||
| 93 | #define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 | ||
| 94 | |||
| 95 | /* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ | ||
| 96 | typedef struct { | ||
| 97 | unsigned int cfg : 2; | ||
| 98 | unsigned int dummy1 : 30; | ||
| 99 | } reg_iop_sw_cfg_rw_crc_par1_owner; | ||
| 100 | #define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 | ||
| 101 | #define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 | ||
| 102 | |||
| 103 | /* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ | ||
| 104 | typedef struct { | ||
| 105 | unsigned int cfg : 2; | ||
| 106 | unsigned int dummy1 : 30; | ||
| 107 | } reg_iop_sw_cfg_rw_dmc_in0_owner; | ||
| 108 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 | ||
| 109 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 | ||
| 110 | |||
| 111 | /* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ | ||
| 112 | typedef struct { | ||
| 113 | unsigned int cfg : 2; | ||
| 114 | unsigned int dummy1 : 30; | ||
| 115 | } reg_iop_sw_cfg_rw_dmc_in1_owner; | ||
| 116 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 | ||
| 117 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 | ||
| 118 | |||
| 119 | /* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ | ||
| 120 | typedef struct { | ||
| 121 | unsigned int cfg : 2; | ||
| 122 | unsigned int dummy1 : 30; | ||
| 123 | } reg_iop_sw_cfg_rw_dmc_out0_owner; | ||
| 124 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 | ||
| 125 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 | ||
| 126 | |||
| 127 | /* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ | ||
| 128 | typedef struct { | ||
| 129 | unsigned int cfg : 2; | ||
| 130 | unsigned int dummy1 : 30; | ||
| 131 | } reg_iop_sw_cfg_rw_dmc_out1_owner; | ||
| 132 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 | ||
| 133 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 | ||
| 134 | |||
| 135 | /* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ | ||
| 136 | typedef struct { | ||
| 137 | unsigned int cfg : 2; | ||
| 138 | unsigned int dummy1 : 30; | ||
| 139 | } reg_iop_sw_cfg_rw_fifo_in0_owner; | ||
| 140 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 | ||
| 141 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 | ||
| 142 | |||
| 143 | /* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 144 | typedef struct { | ||
| 145 | unsigned int cfg : 2; | ||
| 146 | unsigned int dummy1 : 30; | ||
| 147 | } reg_iop_sw_cfg_rw_fifo_in0_extra_owner; | ||
| 148 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 | ||
| 149 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 | ||
| 150 | |||
| 151 | /* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ | ||
| 152 | typedef struct { | ||
| 153 | unsigned int cfg : 2; | ||
| 154 | unsigned int dummy1 : 30; | ||
| 155 | } reg_iop_sw_cfg_rw_fifo_in1_owner; | ||
| 156 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 | ||
| 157 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 | ||
| 158 | |||
| 159 | /* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 160 | typedef struct { | ||
| 161 | unsigned int cfg : 2; | ||
| 162 | unsigned int dummy1 : 30; | ||
| 163 | } reg_iop_sw_cfg_rw_fifo_in1_extra_owner; | ||
| 164 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 | ||
| 165 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 | ||
| 166 | |||
| 167 | /* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int cfg : 2; | ||
| 170 | unsigned int dummy1 : 30; | ||
| 171 | } reg_iop_sw_cfg_rw_fifo_out0_owner; | ||
| 172 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 | ||
| 173 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 | ||
| 174 | |||
| 175 | /* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 176 | typedef struct { | ||
| 177 | unsigned int cfg : 2; | ||
| 178 | unsigned int dummy1 : 30; | ||
| 179 | } reg_iop_sw_cfg_rw_fifo_out0_extra_owner; | ||
| 180 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 | ||
| 181 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 | ||
| 182 | |||
| 183 | /* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int cfg : 2; | ||
| 186 | unsigned int dummy1 : 30; | ||
| 187 | } reg_iop_sw_cfg_rw_fifo_out1_owner; | ||
| 188 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 | ||
| 189 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 | ||
| 190 | |||
| 191 | /* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int cfg : 2; | ||
| 194 | unsigned int dummy1 : 30; | ||
| 195 | } reg_iop_sw_cfg_rw_fifo_out1_extra_owner; | ||
| 196 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 | ||
| 197 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 | ||
| 198 | |||
| 199 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | ||
| 200 | typedef struct { | ||
| 201 | unsigned int cfg : 2; | ||
| 202 | unsigned int dummy1 : 30; | ||
| 203 | } reg_iop_sw_cfg_rw_sap_in_owner; | ||
| 204 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 | ||
| 205 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 | ||
| 206 | |||
| 207 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | ||
| 208 | typedef struct { | ||
| 209 | unsigned int cfg : 2; | ||
| 210 | unsigned int dummy1 : 30; | ||
| 211 | } reg_iop_sw_cfg_rw_sap_out_owner; | ||
| 212 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 | ||
| 213 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 | ||
| 214 | |||
| 215 | /* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ | ||
| 216 | typedef struct { | ||
| 217 | unsigned int cfg : 2; | ||
| 218 | unsigned int dummy1 : 30; | ||
| 219 | } reg_iop_sw_cfg_rw_scrc_in0_owner; | ||
| 220 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 | ||
| 221 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 | ||
| 222 | |||
| 223 | /* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ | ||
| 224 | typedef struct { | ||
| 225 | unsigned int cfg : 2; | ||
| 226 | unsigned int dummy1 : 30; | ||
| 227 | } reg_iop_sw_cfg_rw_scrc_in1_owner; | ||
| 228 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 | ||
| 229 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 | ||
| 230 | |||
| 231 | /* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ | ||
| 232 | typedef struct { | ||
| 233 | unsigned int cfg : 2; | ||
| 234 | unsigned int dummy1 : 30; | ||
| 235 | } reg_iop_sw_cfg_rw_scrc_out0_owner; | ||
| 236 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 | ||
| 237 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 | ||
| 238 | |||
| 239 | /* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ | ||
| 240 | typedef struct { | ||
| 241 | unsigned int cfg : 2; | ||
| 242 | unsigned int dummy1 : 30; | ||
| 243 | } reg_iop_sw_cfg_rw_scrc_out1_owner; | ||
| 244 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 | ||
| 245 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 | ||
| 246 | |||
| 247 | /* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ | ||
| 248 | typedef struct { | ||
| 249 | unsigned int cfg : 2; | ||
| 250 | unsigned int dummy1 : 30; | ||
| 251 | } reg_iop_sw_cfg_rw_spu0_owner; | ||
| 252 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 | ||
| 253 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 | ||
| 254 | |||
| 255 | /* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ | ||
| 256 | typedef struct { | ||
| 257 | unsigned int cfg : 2; | ||
| 258 | unsigned int dummy1 : 30; | ||
| 259 | } reg_iop_sw_cfg_rw_spu1_owner; | ||
| 260 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 | ||
| 261 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 | ||
| 262 | |||
| 263 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 264 | typedef struct { | ||
| 265 | unsigned int cfg : 2; | ||
| 266 | unsigned int dummy1 : 30; | ||
| 267 | } reg_iop_sw_cfg_rw_timer_grp0_owner; | ||
| 268 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 | ||
| 269 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 | ||
| 270 | |||
| 271 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 272 | typedef struct { | ||
| 273 | unsigned int cfg : 2; | ||
| 274 | unsigned int dummy1 : 30; | ||
| 275 | } reg_iop_sw_cfg_rw_timer_grp1_owner; | ||
| 276 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 | ||
| 277 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 | ||
| 278 | |||
| 279 | /* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ | ||
| 280 | typedef struct { | ||
| 281 | unsigned int cfg : 2; | ||
| 282 | unsigned int dummy1 : 30; | ||
| 283 | } reg_iop_sw_cfg_rw_timer_grp2_owner; | ||
| 284 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 | ||
| 285 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 | ||
| 286 | |||
| 287 | /* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ | ||
| 288 | typedef struct { | ||
| 289 | unsigned int cfg : 2; | ||
| 290 | unsigned int dummy1 : 30; | ||
| 291 | } reg_iop_sw_cfg_rw_timer_grp3_owner; | ||
| 292 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 | ||
| 293 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 | ||
| 294 | |||
| 295 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 296 | typedef struct { | ||
| 297 | unsigned int cfg : 2; | ||
| 298 | unsigned int dummy1 : 30; | ||
| 299 | } reg_iop_sw_cfg_rw_trigger_grp0_owner; | ||
| 300 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 | ||
| 301 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 | ||
| 302 | |||
| 303 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 304 | typedef struct { | ||
| 305 | unsigned int cfg : 2; | ||
| 306 | unsigned int dummy1 : 30; | ||
| 307 | } reg_iop_sw_cfg_rw_trigger_grp1_owner; | ||
| 308 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 | ||
| 309 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 | ||
| 310 | |||
| 311 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | ||
| 312 | typedef struct { | ||
| 313 | unsigned int cfg : 2; | ||
| 314 | unsigned int dummy1 : 30; | ||
| 315 | } reg_iop_sw_cfg_rw_trigger_grp2_owner; | ||
| 316 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 | ||
| 317 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 | ||
| 318 | |||
| 319 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | ||
| 320 | typedef struct { | ||
| 321 | unsigned int cfg : 2; | ||
| 322 | unsigned int dummy1 : 30; | ||
| 323 | } reg_iop_sw_cfg_rw_trigger_grp3_owner; | ||
| 324 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 | ||
| 325 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 | ||
| 326 | |||
| 327 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | ||
| 328 | typedef struct { | ||
| 329 | unsigned int cfg : 2; | ||
| 330 | unsigned int dummy1 : 30; | ||
| 331 | } reg_iop_sw_cfg_rw_trigger_grp4_owner; | ||
| 332 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 | ||
| 333 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 | ||
| 334 | |||
| 335 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | ||
| 336 | typedef struct { | ||
| 337 | unsigned int cfg : 2; | ||
| 338 | unsigned int dummy1 : 30; | ||
| 339 | } reg_iop_sw_cfg_rw_trigger_grp5_owner; | ||
| 340 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 | ||
| 341 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 | ||
| 342 | |||
| 343 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | ||
| 344 | typedef struct { | ||
| 345 | unsigned int cfg : 2; | ||
| 346 | unsigned int dummy1 : 30; | ||
| 347 | } reg_iop_sw_cfg_rw_trigger_grp6_owner; | ||
| 348 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 | ||
| 349 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 | ||
| 350 | |||
| 351 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | ||
| 352 | typedef struct { | ||
| 353 | unsigned int cfg : 2; | ||
| 354 | unsigned int dummy1 : 30; | ||
| 355 | } reg_iop_sw_cfg_rw_trigger_grp7_owner; | ||
| 356 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 | ||
| 357 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 | ||
| 358 | |||
| 359 | /* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ | ||
| 360 | typedef struct { | ||
| 361 | unsigned int byte0 : 8; | ||
| 362 | unsigned int byte1 : 8; | ||
| 363 | unsigned int byte2 : 8; | ||
| 364 | unsigned int byte3 : 8; | ||
| 365 | } reg_iop_sw_cfg_rw_bus0_mask; | ||
| 366 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 | ||
| 367 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 | ||
| 368 | |||
| 369 | /* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 370 | typedef struct { | ||
| 371 | unsigned int byte0 : 1; | ||
| 372 | unsigned int byte1 : 1; | ||
| 373 | unsigned int byte2 : 1; | ||
| 374 | unsigned int byte3 : 1; | ||
| 375 | unsigned int dummy1 : 28; | ||
| 376 | } reg_iop_sw_cfg_rw_bus0_oe_mask; | ||
| 377 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 | ||
| 378 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 | ||
| 379 | |||
| 380 | /* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ | ||
| 381 | typedef struct { | ||
| 382 | unsigned int byte0 : 8; | ||
| 383 | unsigned int byte1 : 8; | ||
| 384 | unsigned int byte2 : 8; | ||
| 385 | unsigned int byte3 : 8; | ||
| 386 | } reg_iop_sw_cfg_rw_bus1_mask; | ||
| 387 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 | ||
| 388 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 | ||
| 389 | |||
| 390 | /* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 391 | typedef struct { | ||
| 392 | unsigned int byte0 : 1; | ||
| 393 | unsigned int byte1 : 1; | ||
| 394 | unsigned int byte2 : 1; | ||
| 395 | unsigned int byte3 : 1; | ||
| 396 | unsigned int dummy1 : 28; | ||
| 397 | } reg_iop_sw_cfg_rw_bus1_oe_mask; | ||
| 398 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 | ||
| 399 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 | ||
| 400 | |||
| 401 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | ||
| 402 | typedef struct { | ||
| 403 | unsigned int val : 32; | ||
| 404 | } reg_iop_sw_cfg_rw_gio_mask; | ||
| 405 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 | ||
| 406 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 | ||
| 407 | |||
| 408 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 409 | typedef struct { | ||
| 410 | unsigned int val : 32; | ||
| 411 | } reg_iop_sw_cfg_rw_gio_oe_mask; | ||
| 412 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 | ||
| 413 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 | ||
| 414 | |||
| 415 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | ||
| 416 | typedef struct { | ||
| 417 | unsigned int bus0_byte0 : 2; | ||
| 418 | unsigned int bus0_byte1 : 2; | ||
| 419 | unsigned int bus0_byte2 : 2; | ||
| 420 | unsigned int bus0_byte3 : 2; | ||
| 421 | unsigned int bus1_byte0 : 2; | ||
| 422 | unsigned int bus1_byte1 : 2; | ||
| 423 | unsigned int bus1_byte2 : 2; | ||
| 424 | unsigned int bus1_byte3 : 2; | ||
| 425 | unsigned int gio3_0 : 2; | ||
| 426 | unsigned int gio7_4 : 2; | ||
| 427 | unsigned int gio11_8 : 2; | ||
| 428 | unsigned int gio15_12 : 2; | ||
| 429 | unsigned int gio19_16 : 2; | ||
| 430 | unsigned int gio23_20 : 2; | ||
| 431 | unsigned int gio27_24 : 2; | ||
| 432 | unsigned int gio31_28 : 2; | ||
| 433 | } reg_iop_sw_cfg_rw_pinmapping; | ||
| 434 | #define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 | ||
| 435 | #define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 | ||
| 436 | |||
| 437 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | ||
| 438 | typedef struct { | ||
| 439 | unsigned int bus0_lo : 3; | ||
| 440 | unsigned int bus0_hi : 3; | ||
| 441 | unsigned int bus0_lo_oe : 3; | ||
| 442 | unsigned int bus0_hi_oe : 3; | ||
| 443 | unsigned int bus1_lo : 3; | ||
| 444 | unsigned int bus1_hi : 3; | ||
| 445 | unsigned int bus1_lo_oe : 3; | ||
| 446 | unsigned int bus1_hi_oe : 3; | ||
| 447 | unsigned int dummy1 : 8; | ||
| 448 | } reg_iop_sw_cfg_rw_bus_out_cfg; | ||
| 449 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 | ||
| 450 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 | ||
| 451 | |||
| 452 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 453 | typedef struct { | ||
| 454 | unsigned int gio0 : 4; | ||
| 455 | unsigned int gio0_oe : 2; | ||
| 456 | unsigned int gio1 : 4; | ||
| 457 | unsigned int gio1_oe : 2; | ||
| 458 | unsigned int gio2 : 4; | ||
| 459 | unsigned int gio2_oe : 2; | ||
| 460 | unsigned int gio3 : 4; | ||
| 461 | unsigned int gio3_oe : 2; | ||
| 462 | unsigned int dummy1 : 8; | ||
| 463 | } reg_iop_sw_cfg_rw_gio_out_grp0_cfg; | ||
| 464 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 | ||
| 465 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 | ||
| 466 | |||
| 467 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 468 | typedef struct { | ||
| 469 | unsigned int gio4 : 4; | ||
| 470 | unsigned int gio4_oe : 2; | ||
| 471 | unsigned int gio5 : 4; | ||
| 472 | unsigned int gio5_oe : 2; | ||
| 473 | unsigned int gio6 : 4; | ||
| 474 | unsigned int gio6_oe : 2; | ||
| 475 | unsigned int gio7 : 4; | ||
| 476 | unsigned int gio7_oe : 2; | ||
| 477 | unsigned int dummy1 : 8; | ||
| 478 | } reg_iop_sw_cfg_rw_gio_out_grp1_cfg; | ||
| 479 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 | ||
| 480 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 | ||
| 481 | |||
| 482 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
| 483 | typedef struct { | ||
| 484 | unsigned int gio8 : 4; | ||
| 485 | unsigned int gio8_oe : 2; | ||
| 486 | unsigned int gio9 : 4; | ||
| 487 | unsigned int gio9_oe : 2; | ||
| 488 | unsigned int gio10 : 4; | ||
| 489 | unsigned int gio10_oe : 2; | ||
| 490 | unsigned int gio11 : 4; | ||
| 491 | unsigned int gio11_oe : 2; | ||
| 492 | unsigned int dummy1 : 8; | ||
| 493 | } reg_iop_sw_cfg_rw_gio_out_grp2_cfg; | ||
| 494 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 | ||
| 495 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 | ||
| 496 | |||
| 497 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
| 498 | typedef struct { | ||
| 499 | unsigned int gio12 : 4; | ||
| 500 | unsigned int gio12_oe : 2; | ||
| 501 | unsigned int gio13 : 4; | ||
| 502 | unsigned int gio13_oe : 2; | ||
| 503 | unsigned int gio14 : 4; | ||
| 504 | unsigned int gio14_oe : 2; | ||
| 505 | unsigned int gio15 : 4; | ||
| 506 | unsigned int gio15_oe : 2; | ||
| 507 | unsigned int dummy1 : 8; | ||
| 508 | } reg_iop_sw_cfg_rw_gio_out_grp3_cfg; | ||
| 509 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 | ||
| 510 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 | ||
| 511 | |||
| 512 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | ||
| 513 | typedef struct { | ||
| 514 | unsigned int gio16 : 4; | ||
| 515 | unsigned int gio16_oe : 2; | ||
| 516 | unsigned int gio17 : 4; | ||
| 517 | unsigned int gio17_oe : 2; | ||
| 518 | unsigned int gio18 : 4; | ||
| 519 | unsigned int gio18_oe : 2; | ||
| 520 | unsigned int gio19 : 4; | ||
| 521 | unsigned int gio19_oe : 2; | ||
| 522 | unsigned int dummy1 : 8; | ||
| 523 | } reg_iop_sw_cfg_rw_gio_out_grp4_cfg; | ||
| 524 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 | ||
| 525 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 | ||
| 526 | |||
| 527 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | ||
| 528 | typedef struct { | ||
| 529 | unsigned int gio20 : 4; | ||
| 530 | unsigned int gio20_oe : 2; | ||
| 531 | unsigned int gio21 : 4; | ||
| 532 | unsigned int gio21_oe : 2; | ||
| 533 | unsigned int gio22 : 4; | ||
| 534 | unsigned int gio22_oe : 2; | ||
| 535 | unsigned int gio23 : 4; | ||
| 536 | unsigned int gio23_oe : 2; | ||
| 537 | unsigned int dummy1 : 8; | ||
| 538 | } reg_iop_sw_cfg_rw_gio_out_grp5_cfg; | ||
| 539 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 | ||
| 540 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 | ||
| 541 | |||
| 542 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | ||
| 543 | typedef struct { | ||
| 544 | unsigned int gio24 : 4; | ||
| 545 | unsigned int gio24_oe : 2; | ||
| 546 | unsigned int gio25 : 4; | ||
| 547 | unsigned int gio25_oe : 2; | ||
| 548 | unsigned int gio26 : 4; | ||
| 549 | unsigned int gio26_oe : 2; | ||
| 550 | unsigned int gio27 : 4; | ||
| 551 | unsigned int gio27_oe : 2; | ||
| 552 | unsigned int dummy1 : 8; | ||
| 553 | } reg_iop_sw_cfg_rw_gio_out_grp6_cfg; | ||
| 554 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 | ||
| 555 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 | ||
| 556 | |||
| 557 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | ||
| 558 | typedef struct { | ||
| 559 | unsigned int gio28 : 4; | ||
| 560 | unsigned int gio28_oe : 2; | ||
| 561 | unsigned int gio29 : 4; | ||
| 562 | unsigned int gio29_oe : 2; | ||
| 563 | unsigned int gio30 : 4; | ||
| 564 | unsigned int gio30_oe : 2; | ||
| 565 | unsigned int gio31 : 4; | ||
| 566 | unsigned int gio31_oe : 2; | ||
| 567 | unsigned int dummy1 : 8; | ||
| 568 | } reg_iop_sw_cfg_rw_gio_out_grp7_cfg; | ||
| 569 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 | ||
| 570 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 | ||
| 571 | |||
| 572 | /* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ | ||
| 573 | typedef struct { | ||
| 574 | unsigned int bus0_in : 2; | ||
| 575 | unsigned int bus1_in : 2; | ||
| 576 | unsigned int dummy1 : 28; | ||
| 577 | } reg_iop_sw_cfg_rw_spu0_cfg; | ||
| 578 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 | ||
| 579 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 | ||
| 580 | |||
| 581 | /* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ | ||
| 582 | typedef struct { | ||
| 583 | unsigned int bus0_in : 2; | ||
| 584 | unsigned int bus1_in : 2; | ||
| 585 | unsigned int dummy1 : 28; | ||
| 586 | } reg_iop_sw_cfg_rw_spu1_cfg; | ||
| 587 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 | ||
| 588 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 | ||
| 589 | |||
| 590 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 591 | typedef struct { | ||
| 592 | unsigned int ext_clk : 3; | ||
| 593 | unsigned int tmr0_en : 1; | ||
| 594 | unsigned int tmr1_en : 1; | ||
| 595 | unsigned int tmr2_en : 1; | ||
| 596 | unsigned int tmr3_en : 1; | ||
| 597 | unsigned int tmr0_dis : 1; | ||
| 598 | unsigned int tmr1_dis : 1; | ||
| 599 | unsigned int tmr2_dis : 1; | ||
| 600 | unsigned int tmr3_dis : 1; | ||
| 601 | unsigned int dummy1 : 21; | ||
| 602 | } reg_iop_sw_cfg_rw_timer_grp0_cfg; | ||
| 603 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 | ||
| 604 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 | ||
| 605 | |||
| 606 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 607 | typedef struct { | ||
| 608 | unsigned int ext_clk : 3; | ||
| 609 | unsigned int tmr0_en : 1; | ||
| 610 | unsigned int tmr1_en : 1; | ||
| 611 | unsigned int tmr2_en : 1; | ||
| 612 | unsigned int tmr3_en : 1; | ||
| 613 | unsigned int tmr0_dis : 1; | ||
| 614 | unsigned int tmr1_dis : 1; | ||
| 615 | unsigned int tmr2_dis : 1; | ||
| 616 | unsigned int tmr3_dis : 1; | ||
| 617 | unsigned int dummy1 : 21; | ||
| 618 | } reg_iop_sw_cfg_rw_timer_grp1_cfg; | ||
| 619 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 | ||
| 620 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 | ||
| 621 | |||
| 622 | /* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
| 623 | typedef struct { | ||
| 624 | unsigned int ext_clk : 3; | ||
| 625 | unsigned int tmr0_en : 1; | ||
| 626 | unsigned int tmr1_en : 1; | ||
| 627 | unsigned int tmr2_en : 1; | ||
| 628 | unsigned int tmr3_en : 1; | ||
| 629 | unsigned int tmr0_dis : 1; | ||
| 630 | unsigned int tmr1_dis : 1; | ||
| 631 | unsigned int tmr2_dis : 1; | ||
| 632 | unsigned int tmr3_dis : 1; | ||
| 633 | unsigned int dummy1 : 21; | ||
| 634 | } reg_iop_sw_cfg_rw_timer_grp2_cfg; | ||
| 635 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 | ||
| 636 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 | ||
| 637 | |||
| 638 | /* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
| 639 | typedef struct { | ||
| 640 | unsigned int ext_clk : 3; | ||
| 641 | unsigned int tmr0_en : 1; | ||
| 642 | unsigned int tmr1_en : 1; | ||
| 643 | unsigned int tmr2_en : 1; | ||
| 644 | unsigned int tmr3_en : 1; | ||
| 645 | unsigned int tmr0_dis : 1; | ||
| 646 | unsigned int tmr1_dis : 1; | ||
| 647 | unsigned int tmr2_dis : 1; | ||
| 648 | unsigned int tmr3_dis : 1; | ||
| 649 | unsigned int dummy1 : 21; | ||
| 650 | } reg_iop_sw_cfg_rw_timer_grp3_cfg; | ||
| 651 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 | ||
| 652 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 | ||
| 653 | |||
| 654 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | ||
| 655 | typedef struct { | ||
| 656 | unsigned int grp0_dis : 1; | ||
| 657 | unsigned int grp0_en : 1; | ||
| 658 | unsigned int grp1_dis : 1; | ||
| 659 | unsigned int grp1_en : 1; | ||
| 660 | unsigned int grp2_dis : 1; | ||
| 661 | unsigned int grp2_en : 1; | ||
| 662 | unsigned int grp3_dis : 1; | ||
| 663 | unsigned int grp3_en : 1; | ||
| 664 | unsigned int grp4_dis : 1; | ||
| 665 | unsigned int grp4_en : 1; | ||
| 666 | unsigned int grp5_dis : 1; | ||
| 667 | unsigned int grp5_en : 1; | ||
| 668 | unsigned int grp6_dis : 1; | ||
| 669 | unsigned int grp6_en : 1; | ||
| 670 | unsigned int grp7_dis : 1; | ||
| 671 | unsigned int grp7_en : 1; | ||
| 672 | unsigned int dummy1 : 16; | ||
| 673 | } reg_iop_sw_cfg_rw_trigger_grps_cfg; | ||
| 674 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 | ||
| 675 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 | ||
| 676 | |||
| 677 | /* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 678 | typedef struct { | ||
| 679 | unsigned int dmc0_usr : 1; | ||
| 680 | unsigned int out_strb : 5; | ||
| 681 | unsigned int in_src : 3; | ||
| 682 | unsigned int in_size : 3; | ||
| 683 | unsigned int in_last : 2; | ||
| 684 | unsigned int in_strb : 4; | ||
| 685 | unsigned int out_src : 1; | ||
| 686 | unsigned int dummy1 : 13; | ||
| 687 | } reg_iop_sw_cfg_rw_pdp0_cfg; | ||
| 688 | #define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 | ||
| 689 | #define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 | ||
| 690 | |||
| 691 | /* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 692 | typedef struct { | ||
| 693 | unsigned int dmc1_usr : 1; | ||
| 694 | unsigned int out_strb : 5; | ||
| 695 | unsigned int in_src : 3; | ||
| 696 | unsigned int in_size : 3; | ||
| 697 | unsigned int in_last : 2; | ||
| 698 | unsigned int in_strb : 4; | ||
| 699 | unsigned int out_src : 1; | ||
| 700 | unsigned int dummy1 : 13; | ||
| 701 | } reg_iop_sw_cfg_rw_pdp1_cfg; | ||
| 702 | #define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 | ||
| 703 | #define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 | ||
| 704 | |||
| 705 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 706 | typedef struct { | ||
| 707 | unsigned int sdp_out0_strb : 3; | ||
| 708 | unsigned int sdp_out1_strb : 3; | ||
| 709 | unsigned int sdp_in0_data : 3; | ||
| 710 | unsigned int sdp_in0_last : 2; | ||
| 711 | unsigned int sdp_in0_strb : 3; | ||
| 712 | unsigned int sdp_in1_data : 3; | ||
| 713 | unsigned int sdp_in1_last : 2; | ||
| 714 | unsigned int sdp_in1_strb : 3; | ||
| 715 | unsigned int dummy1 : 10; | ||
| 716 | } reg_iop_sw_cfg_rw_sdp_cfg; | ||
| 717 | #define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 | ||
| 718 | #define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 | ||
| 719 | |||
| 720 | |||
| 721 | /* Constants */ | ||
| 722 | enum { | ||
| 723 | regk_iop_sw_cfg_a = 0x00000001, | ||
| 724 | regk_iop_sw_cfg_b = 0x00000002, | ||
| 725 | regk_iop_sw_cfg_bus0 = 0x00000000, | ||
| 726 | regk_iop_sw_cfg_bus0_rot16 = 0x00000004, | ||
| 727 | regk_iop_sw_cfg_bus0_rot24 = 0x00000006, | ||
| 728 | regk_iop_sw_cfg_bus0_rot8 = 0x00000002, | ||
| 729 | regk_iop_sw_cfg_bus1 = 0x00000001, | ||
| 730 | regk_iop_sw_cfg_bus1_rot16 = 0x00000005, | ||
| 731 | regk_iop_sw_cfg_bus1_rot24 = 0x00000007, | ||
| 732 | regk_iop_sw_cfg_bus1_rot8 = 0x00000003, | ||
| 733 | regk_iop_sw_cfg_clk12 = 0x00000000, | ||
| 734 | regk_iop_sw_cfg_cpu = 0x00000000, | ||
| 735 | regk_iop_sw_cfg_dmc0 = 0x00000000, | ||
| 736 | regk_iop_sw_cfg_dmc1 = 0x00000001, | ||
| 737 | regk_iop_sw_cfg_gated_clk0 = 0x00000010, | ||
| 738 | regk_iop_sw_cfg_gated_clk1 = 0x00000011, | ||
| 739 | regk_iop_sw_cfg_gated_clk2 = 0x00000012, | ||
| 740 | regk_iop_sw_cfg_gated_clk3 = 0x00000013, | ||
| 741 | regk_iop_sw_cfg_gio0 = 0x00000004, | ||
| 742 | regk_iop_sw_cfg_gio1 = 0x00000001, | ||
| 743 | regk_iop_sw_cfg_gio2 = 0x00000005, | ||
| 744 | regk_iop_sw_cfg_gio3 = 0x00000002, | ||
| 745 | regk_iop_sw_cfg_gio4 = 0x00000006, | ||
| 746 | regk_iop_sw_cfg_gio5 = 0x00000003, | ||
| 747 | regk_iop_sw_cfg_gio6 = 0x00000007, | ||
| 748 | regk_iop_sw_cfg_gio7 = 0x00000004, | ||
| 749 | regk_iop_sw_cfg_gio_in0 = 0x00000000, | ||
| 750 | regk_iop_sw_cfg_gio_in1 = 0x00000001, | ||
| 751 | regk_iop_sw_cfg_gio_in10 = 0x00000002, | ||
| 752 | regk_iop_sw_cfg_gio_in11 = 0x00000003, | ||
| 753 | regk_iop_sw_cfg_gio_in14 = 0x00000004, | ||
| 754 | regk_iop_sw_cfg_gio_in15 = 0x00000005, | ||
| 755 | regk_iop_sw_cfg_gio_in18 = 0x00000002, | ||
| 756 | regk_iop_sw_cfg_gio_in19 = 0x00000003, | ||
| 757 | regk_iop_sw_cfg_gio_in20 = 0x00000004, | ||
| 758 | regk_iop_sw_cfg_gio_in21 = 0x00000005, | ||
| 759 | regk_iop_sw_cfg_gio_in26 = 0x00000006, | ||
| 760 | regk_iop_sw_cfg_gio_in27 = 0x00000007, | ||
| 761 | regk_iop_sw_cfg_gio_in28 = 0x00000006, | ||
| 762 | regk_iop_sw_cfg_gio_in29 = 0x00000007, | ||
| 763 | regk_iop_sw_cfg_gio_in4 = 0x00000000, | ||
| 764 | regk_iop_sw_cfg_gio_in5 = 0x00000001, | ||
| 765 | regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, | ||
| 766 | regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, | ||
| 767 | regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, | ||
| 768 | regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, | ||
| 769 | regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, | ||
| 770 | regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, | ||
| 771 | regk_iop_sw_cfg_mpu = 0x00000001, | ||
| 772 | regk_iop_sw_cfg_none = 0x00000000, | ||
| 773 | regk_iop_sw_cfg_par0 = 0x00000000, | ||
| 774 | regk_iop_sw_cfg_par1 = 0x00000001, | ||
| 775 | regk_iop_sw_cfg_pdp_out0 = 0x00000002, | ||
| 776 | regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, | ||
| 777 | regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, | ||
| 778 | regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, | ||
| 779 | regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, | ||
| 780 | regk_iop_sw_cfg_pdp_out1 = 0x00000003, | ||
| 781 | regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, | ||
| 782 | regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, | ||
| 783 | regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, | ||
| 784 | regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, | ||
| 785 | regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, | ||
| 786 | regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, | ||
| 787 | regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, | ||
| 788 | regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, | ||
| 789 | regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, | ||
| 790 | regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, | ||
| 791 | regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, | ||
| 792 | regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, | ||
| 793 | regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, | ||
| 794 | regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, | ||
| 795 | regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, | ||
| 796 | regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, | ||
| 797 | regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, | ||
| 798 | regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, | ||
| 799 | regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, | ||
| 800 | regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, | ||
| 801 | regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, | ||
| 802 | regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, | ||
| 803 | regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, | ||
| 804 | regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, | ||
| 805 | regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, | ||
| 806 | regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, | ||
| 807 | regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, | ||
| 808 | regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, | ||
| 809 | regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, | ||
| 810 | regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, | ||
| 811 | regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, | ||
| 812 | regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, | ||
| 813 | regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, | ||
| 814 | regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, | ||
| 815 | regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, | ||
| 816 | regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, | ||
| 817 | regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, | ||
| 818 | regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, | ||
| 819 | regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, | ||
| 820 | regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, | ||
| 821 | regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, | ||
| 822 | regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, | ||
| 823 | regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, | ||
| 824 | regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, | ||
| 825 | regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, | ||
| 826 | regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, | ||
| 827 | regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, | ||
| 828 | regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, | ||
| 829 | regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, | ||
| 830 | regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, | ||
| 831 | regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, | ||
| 832 | regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, | ||
| 833 | regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, | ||
| 834 | regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, | ||
| 835 | regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, | ||
| 836 | regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, | ||
| 837 | regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, | ||
| 838 | regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, | ||
| 839 | regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, | ||
| 840 | regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, | ||
| 841 | regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, | ||
| 842 | regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, | ||
| 843 | regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, | ||
| 844 | regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, | ||
| 845 | regk_iop_sw_cfg_sdp_out0 = 0x00000008, | ||
| 846 | regk_iop_sw_cfg_sdp_out1 = 0x00000009, | ||
| 847 | regk_iop_sw_cfg_size16 = 0x00000002, | ||
| 848 | regk_iop_sw_cfg_size24 = 0x00000003, | ||
| 849 | regk_iop_sw_cfg_size32 = 0x00000004, | ||
| 850 | regk_iop_sw_cfg_size8 = 0x00000001, | ||
| 851 | regk_iop_sw_cfg_spu0 = 0x00000002, | ||
| 852 | regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, | ||
| 853 | regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, | ||
| 854 | regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, | ||
| 855 | regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, | ||
| 856 | regk_iop_sw_cfg_spu0_g0 = 0x0000000e, | ||
| 857 | regk_iop_sw_cfg_spu0_g1 = 0x0000000e, | ||
| 858 | regk_iop_sw_cfg_spu0_g2 = 0x0000000e, | ||
| 859 | regk_iop_sw_cfg_spu0_g3 = 0x0000000e, | ||
| 860 | regk_iop_sw_cfg_spu0_g4 = 0x0000000e, | ||
| 861 | regk_iop_sw_cfg_spu0_g5 = 0x0000000e, | ||
| 862 | regk_iop_sw_cfg_spu0_g6 = 0x0000000e, | ||
| 863 | regk_iop_sw_cfg_spu0_g7 = 0x0000000e, | ||
| 864 | regk_iop_sw_cfg_spu0_gio0 = 0x00000000, | ||
| 865 | regk_iop_sw_cfg_spu0_gio1 = 0x00000001, | ||
| 866 | regk_iop_sw_cfg_spu0_gio2 = 0x00000000, | ||
| 867 | regk_iop_sw_cfg_spu0_gio5 = 0x00000005, | ||
| 868 | regk_iop_sw_cfg_spu0_gio6 = 0x00000006, | ||
| 869 | regk_iop_sw_cfg_spu0_gio7 = 0x00000007, | ||
| 870 | regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, | ||
| 871 | regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, | ||
| 872 | regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, | ||
| 873 | regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, | ||
| 874 | regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, | ||
| 875 | regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, | ||
| 876 | regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, | ||
| 877 | regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, | ||
| 878 | regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, | ||
| 879 | regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, | ||
| 880 | regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, | ||
| 881 | regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, | ||
| 882 | regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, | ||
| 883 | regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, | ||
| 884 | regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, | ||
| 885 | regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, | ||
| 886 | regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, | ||
| 887 | regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, | ||
| 888 | regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, | ||
| 889 | regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, | ||
| 890 | regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, | ||
| 891 | regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, | ||
| 892 | regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, | ||
| 893 | regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, | ||
| 894 | regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, | ||
| 895 | regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, | ||
| 896 | regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, | ||
| 897 | regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, | ||
| 898 | regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, | ||
| 899 | regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, | ||
| 900 | regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, | ||
| 901 | regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, | ||
| 902 | regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, | ||
| 903 | regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, | ||
| 904 | regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, | ||
| 905 | regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, | ||
| 906 | regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, | ||
| 907 | regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, | ||
| 908 | regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, | ||
| 909 | regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, | ||
| 910 | regk_iop_sw_cfg_spu1 = 0x00000003, | ||
| 911 | regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, | ||
| 912 | regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, | ||
| 913 | regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, | ||
| 914 | regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, | ||
| 915 | regk_iop_sw_cfg_spu1_g0 = 0x0000000f, | ||
| 916 | regk_iop_sw_cfg_spu1_g1 = 0x0000000f, | ||
| 917 | regk_iop_sw_cfg_spu1_g2 = 0x0000000f, | ||
| 918 | regk_iop_sw_cfg_spu1_g3 = 0x0000000f, | ||
| 919 | regk_iop_sw_cfg_spu1_g4 = 0x0000000f, | ||
| 920 | regk_iop_sw_cfg_spu1_g5 = 0x0000000f, | ||
| 921 | regk_iop_sw_cfg_spu1_g6 = 0x0000000f, | ||
| 922 | regk_iop_sw_cfg_spu1_g7 = 0x0000000f, | ||
| 923 | regk_iop_sw_cfg_spu1_gio0 = 0x00000002, | ||
| 924 | regk_iop_sw_cfg_spu1_gio1 = 0x00000003, | ||
| 925 | regk_iop_sw_cfg_spu1_gio2 = 0x00000002, | ||
| 926 | regk_iop_sw_cfg_spu1_gio5 = 0x00000005, | ||
| 927 | regk_iop_sw_cfg_spu1_gio6 = 0x00000006, | ||
| 928 | regk_iop_sw_cfg_spu1_gio7 = 0x00000007, | ||
| 929 | regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, | ||
| 930 | regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, | ||
| 931 | regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, | ||
| 932 | regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, | ||
| 933 | regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, | ||
| 934 | regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, | ||
| 935 | regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, | ||
| 936 | regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, | ||
| 937 | regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, | ||
| 938 | regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, | ||
| 939 | regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, | ||
| 940 | regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, | ||
| 941 | regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, | ||
| 942 | regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, | ||
| 943 | regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, | ||
| 944 | regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, | ||
| 945 | regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, | ||
| 946 | regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, | ||
| 947 | regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, | ||
| 948 | regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, | ||
| 949 | regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, | ||
| 950 | regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, | ||
| 951 | regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, | ||
| 952 | regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, | ||
| 953 | regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, | ||
| 954 | regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, | ||
| 955 | regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, | ||
| 956 | regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, | ||
| 957 | regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, | ||
| 958 | regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, | ||
| 959 | regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, | ||
| 960 | regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, | ||
| 961 | regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, | ||
| 962 | regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, | ||
| 963 | regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, | ||
| 964 | regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, | ||
| 965 | regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, | ||
| 966 | regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, | ||
| 967 | regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, | ||
| 968 | regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, | ||
| 969 | regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, | ||
| 970 | regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, | ||
| 971 | regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, | ||
| 972 | regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, | ||
| 973 | regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, | ||
| 974 | regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, | ||
| 975 | regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, | ||
| 976 | regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, | ||
| 977 | regk_iop_sw_cfg_timer_grp0 = 0x00000000, | ||
| 978 | regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, | ||
| 979 | regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, | ||
| 980 | regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, | ||
| 981 | regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, | ||
| 982 | regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, | ||
| 983 | regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, | ||
| 984 | regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, | ||
| 985 | regk_iop_sw_cfg_timer_grp1 = 0x00000000, | ||
| 986 | regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, | ||
| 987 | regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, | ||
| 988 | regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, | ||
| 989 | regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, | ||
| 990 | regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, | ||
| 991 | regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, | ||
| 992 | regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, | ||
| 993 | regk_iop_sw_cfg_timer_grp2 = 0x00000000, | ||
| 994 | regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, | ||
| 995 | regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, | ||
| 996 | regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, | ||
| 997 | regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, | ||
| 998 | regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, | ||
| 999 | regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, | ||
| 1000 | regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, | ||
| 1001 | regk_iop_sw_cfg_timer_grp3 = 0x00000000, | ||
| 1002 | regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, | ||
| 1003 | regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, | ||
| 1004 | regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, | ||
| 1005 | regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, | ||
| 1006 | regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, | ||
| 1007 | regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, | ||
| 1008 | regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, | ||
| 1009 | regk_iop_sw_cfg_trig0_0 = 0x00000000, | ||
| 1010 | regk_iop_sw_cfg_trig0_1 = 0x00000000, | ||
| 1011 | regk_iop_sw_cfg_trig0_2 = 0x00000000, | ||
| 1012 | regk_iop_sw_cfg_trig0_3 = 0x00000000, | ||
| 1013 | regk_iop_sw_cfg_trig1_0 = 0x00000000, | ||
| 1014 | regk_iop_sw_cfg_trig1_1 = 0x00000000, | ||
| 1015 | regk_iop_sw_cfg_trig1_2 = 0x00000000, | ||
| 1016 | regk_iop_sw_cfg_trig1_3 = 0x00000000, | ||
| 1017 | regk_iop_sw_cfg_trig2_0 = 0x00000000, | ||
| 1018 | regk_iop_sw_cfg_trig2_1 = 0x00000000, | ||
| 1019 | regk_iop_sw_cfg_trig2_2 = 0x00000000, | ||
| 1020 | regk_iop_sw_cfg_trig2_3 = 0x00000000, | ||
| 1021 | regk_iop_sw_cfg_trig3_0 = 0x00000000, | ||
| 1022 | regk_iop_sw_cfg_trig3_1 = 0x00000000, | ||
| 1023 | regk_iop_sw_cfg_trig3_2 = 0x00000000, | ||
| 1024 | regk_iop_sw_cfg_trig3_3 = 0x00000000, | ||
| 1025 | regk_iop_sw_cfg_trig4_0 = 0x00000001, | ||
| 1026 | regk_iop_sw_cfg_trig4_1 = 0x00000001, | ||
| 1027 | regk_iop_sw_cfg_trig4_2 = 0x00000001, | ||
| 1028 | regk_iop_sw_cfg_trig4_3 = 0x00000001, | ||
| 1029 | regk_iop_sw_cfg_trig5_0 = 0x00000001, | ||
| 1030 | regk_iop_sw_cfg_trig5_1 = 0x00000001, | ||
| 1031 | regk_iop_sw_cfg_trig5_2 = 0x00000001, | ||
| 1032 | regk_iop_sw_cfg_trig5_3 = 0x00000001, | ||
| 1033 | regk_iop_sw_cfg_trig6_0 = 0x00000001, | ||
| 1034 | regk_iop_sw_cfg_trig6_1 = 0x00000001, | ||
| 1035 | regk_iop_sw_cfg_trig6_2 = 0x00000001, | ||
| 1036 | regk_iop_sw_cfg_trig6_3 = 0x00000001, | ||
| 1037 | regk_iop_sw_cfg_trig7_0 = 0x00000001, | ||
| 1038 | regk_iop_sw_cfg_trig7_1 = 0x00000001, | ||
| 1039 | regk_iop_sw_cfg_trig7_2 = 0x00000001, | ||
| 1040 | regk_iop_sw_cfg_trig7_3 = 0x00000001 | ||
| 1041 | }; | ||
| 1042 | #endif /* __iop_sw_cfg_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index 5fed844b19e2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null | |||
| @@ -1,853 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_cpu_defs_h | ||
| 2 | #define __iop_sw_cpu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:19 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r | ||
| 11 | * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_sw_cpu */ | ||
| 86 | |||
| 87 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int keep_owner : 1; | ||
| 90 | unsigned int cmd : 2; | ||
| 91 | unsigned int size : 3; | ||
| 92 | unsigned int wr_spu0_mem : 1; | ||
| 93 | unsigned int wr_spu1_mem : 1; | ||
| 94 | unsigned int dummy1 : 24; | ||
| 95 | } reg_iop_sw_cpu_rw_mc_ctrl; | ||
| 96 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0 | ||
| 97 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0 | ||
| 98 | |||
| 99 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | ||
| 100 | typedef struct { | ||
| 101 | unsigned int val : 32; | ||
| 102 | } reg_iop_sw_cpu_rw_mc_data; | ||
| 103 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4 | ||
| 104 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4 | ||
| 105 | |||
| 106 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | ||
| 107 | typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; | ||
| 108 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8 | ||
| 109 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8 | ||
| 110 | |||
| 111 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | ||
| 112 | typedef unsigned int reg_iop_sw_cpu_rs_mc_data; | ||
| 113 | #define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12 | ||
| 114 | |||
| 115 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | ||
| 116 | typedef unsigned int reg_iop_sw_cpu_r_mc_data; | ||
| 117 | #define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16 | ||
| 118 | |||
| 119 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | ||
| 120 | typedef struct { | ||
| 121 | unsigned int busy_cpu : 1; | ||
| 122 | unsigned int busy_mpu : 1; | ||
| 123 | unsigned int busy_spu0 : 1; | ||
| 124 | unsigned int busy_spu1 : 1; | ||
| 125 | unsigned int owned_by_cpu : 1; | ||
| 126 | unsigned int owned_by_mpu : 1; | ||
| 127 | unsigned int owned_by_spu0 : 1; | ||
| 128 | unsigned int owned_by_spu1 : 1; | ||
| 129 | unsigned int dummy1 : 24; | ||
| 130 | } reg_iop_sw_cpu_r_mc_stat; | ||
| 131 | #define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20 | ||
| 132 | |||
| 133 | /* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 134 | typedef struct { | ||
| 135 | unsigned int byte0 : 8; | ||
| 136 | unsigned int byte1 : 8; | ||
| 137 | unsigned int byte2 : 8; | ||
| 138 | unsigned int byte3 : 8; | ||
| 139 | } reg_iop_sw_cpu_rw_bus0_clr_mask; | ||
| 140 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 | ||
| 141 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 | ||
| 142 | |||
| 143 | /* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ | ||
| 144 | typedef struct { | ||
| 145 | unsigned int byte0 : 8; | ||
| 146 | unsigned int byte1 : 8; | ||
| 147 | unsigned int byte2 : 8; | ||
| 148 | unsigned int byte3 : 8; | ||
| 149 | } reg_iop_sw_cpu_rw_bus0_set_mask; | ||
| 150 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 | ||
| 151 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 | ||
| 152 | |||
| 153 | /* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int byte0 : 1; | ||
| 156 | unsigned int byte1 : 1; | ||
| 157 | unsigned int byte2 : 1; | ||
| 158 | unsigned int byte3 : 1; | ||
| 159 | unsigned int dummy1 : 28; | ||
| 160 | } reg_iop_sw_cpu_rw_bus0_oe_clr_mask; | ||
| 161 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 | ||
| 162 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 | ||
| 163 | |||
| 164 | /* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 165 | typedef struct { | ||
| 166 | unsigned int byte0 : 1; | ||
| 167 | unsigned int byte1 : 1; | ||
| 168 | unsigned int byte2 : 1; | ||
| 169 | unsigned int byte3 : 1; | ||
| 170 | unsigned int dummy1 : 28; | ||
| 171 | } reg_iop_sw_cpu_rw_bus0_oe_set_mask; | ||
| 172 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 | ||
| 173 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 | ||
| 174 | |||
| 175 | /* Register r_bus0_in, scope iop_sw_cpu, type r */ | ||
| 176 | typedef unsigned int reg_iop_sw_cpu_r_bus0_in; | ||
| 177 | #define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40 | ||
| 178 | |||
| 179 | /* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 180 | typedef struct { | ||
| 181 | unsigned int byte0 : 8; | ||
| 182 | unsigned int byte1 : 8; | ||
| 183 | unsigned int byte2 : 8; | ||
| 184 | unsigned int byte3 : 8; | ||
| 185 | } reg_iop_sw_cpu_rw_bus1_clr_mask; | ||
| 186 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 | ||
| 187 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 | ||
| 188 | |||
| 189 | /* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ | ||
| 190 | typedef struct { | ||
| 191 | unsigned int byte0 : 8; | ||
| 192 | unsigned int byte1 : 8; | ||
| 193 | unsigned int byte2 : 8; | ||
| 194 | unsigned int byte3 : 8; | ||
| 195 | } reg_iop_sw_cpu_rw_bus1_set_mask; | ||
| 196 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 | ||
| 197 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 | ||
| 198 | |||
| 199 | /* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 200 | typedef struct { | ||
| 201 | unsigned int byte0 : 1; | ||
| 202 | unsigned int byte1 : 1; | ||
| 203 | unsigned int byte2 : 1; | ||
| 204 | unsigned int byte3 : 1; | ||
| 205 | unsigned int dummy1 : 28; | ||
| 206 | } reg_iop_sw_cpu_rw_bus1_oe_clr_mask; | ||
| 207 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 | ||
| 208 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 | ||
| 209 | |||
| 210 | /* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 211 | typedef struct { | ||
| 212 | unsigned int byte0 : 1; | ||
| 213 | unsigned int byte1 : 1; | ||
| 214 | unsigned int byte2 : 1; | ||
| 215 | unsigned int byte3 : 1; | ||
| 216 | unsigned int dummy1 : 28; | ||
| 217 | } reg_iop_sw_cpu_rw_bus1_oe_set_mask; | ||
| 218 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 | ||
| 219 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 | ||
| 220 | |||
| 221 | /* Register r_bus1_in, scope iop_sw_cpu, type r */ | ||
| 222 | typedef unsigned int reg_iop_sw_cpu_r_bus1_in; | ||
| 223 | #define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60 | ||
| 224 | |||
| 225 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 226 | typedef struct { | ||
| 227 | unsigned int val : 32; | ||
| 228 | } reg_iop_sw_cpu_rw_gio_clr_mask; | ||
| 229 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 | ||
| 230 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 | ||
| 231 | |||
| 232 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | ||
| 233 | typedef struct { | ||
| 234 | unsigned int val : 32; | ||
| 235 | } reg_iop_sw_cpu_rw_gio_set_mask; | ||
| 236 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68 | ||
| 237 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68 | ||
| 238 | |||
| 239 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 240 | typedef struct { | ||
| 241 | unsigned int val : 32; | ||
| 242 | } reg_iop_sw_cpu_rw_gio_oe_clr_mask; | ||
| 243 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 | ||
| 244 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 | ||
| 245 | |||
| 246 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 247 | typedef struct { | ||
| 248 | unsigned int val : 32; | ||
| 249 | } reg_iop_sw_cpu_rw_gio_oe_set_mask; | ||
| 250 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 | ||
| 251 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 | ||
| 252 | |||
| 253 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | ||
| 254 | typedef unsigned int reg_iop_sw_cpu_r_gio_in; | ||
| 255 | #define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80 | ||
| 256 | |||
| 257 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | ||
| 258 | typedef struct { | ||
| 259 | unsigned int mpu_0 : 1; | ||
| 260 | unsigned int mpu_1 : 1; | ||
| 261 | unsigned int mpu_2 : 1; | ||
| 262 | unsigned int mpu_3 : 1; | ||
| 263 | unsigned int mpu_4 : 1; | ||
| 264 | unsigned int mpu_5 : 1; | ||
| 265 | unsigned int mpu_6 : 1; | ||
| 266 | unsigned int mpu_7 : 1; | ||
| 267 | unsigned int mpu_8 : 1; | ||
| 268 | unsigned int mpu_9 : 1; | ||
| 269 | unsigned int mpu_10 : 1; | ||
| 270 | unsigned int mpu_11 : 1; | ||
| 271 | unsigned int mpu_12 : 1; | ||
| 272 | unsigned int mpu_13 : 1; | ||
| 273 | unsigned int mpu_14 : 1; | ||
| 274 | unsigned int mpu_15 : 1; | ||
| 275 | unsigned int spu0_0 : 1; | ||
| 276 | unsigned int spu0_1 : 1; | ||
| 277 | unsigned int spu0_2 : 1; | ||
| 278 | unsigned int spu0_3 : 1; | ||
| 279 | unsigned int spu0_4 : 1; | ||
| 280 | unsigned int spu0_5 : 1; | ||
| 281 | unsigned int spu0_6 : 1; | ||
| 282 | unsigned int spu0_7 : 1; | ||
| 283 | unsigned int spu1_8 : 1; | ||
| 284 | unsigned int spu1_9 : 1; | ||
| 285 | unsigned int spu1_10 : 1; | ||
| 286 | unsigned int spu1_11 : 1; | ||
| 287 | unsigned int spu1_12 : 1; | ||
| 288 | unsigned int spu1_13 : 1; | ||
| 289 | unsigned int spu1_14 : 1; | ||
| 290 | unsigned int spu1_15 : 1; | ||
| 291 | } reg_iop_sw_cpu_rw_intr0_mask; | ||
| 292 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84 | ||
| 293 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84 | ||
| 294 | |||
| 295 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | ||
| 296 | typedef struct { | ||
| 297 | unsigned int mpu_0 : 1; | ||
| 298 | unsigned int mpu_1 : 1; | ||
| 299 | unsigned int mpu_2 : 1; | ||
| 300 | unsigned int mpu_3 : 1; | ||
| 301 | unsigned int mpu_4 : 1; | ||
| 302 | unsigned int mpu_5 : 1; | ||
| 303 | unsigned int mpu_6 : 1; | ||
| 304 | unsigned int mpu_7 : 1; | ||
| 305 | unsigned int mpu_8 : 1; | ||
| 306 | unsigned int mpu_9 : 1; | ||
| 307 | unsigned int mpu_10 : 1; | ||
| 308 | unsigned int mpu_11 : 1; | ||
| 309 | unsigned int mpu_12 : 1; | ||
| 310 | unsigned int mpu_13 : 1; | ||
| 311 | unsigned int mpu_14 : 1; | ||
| 312 | unsigned int mpu_15 : 1; | ||
| 313 | unsigned int spu0_0 : 1; | ||
| 314 | unsigned int spu0_1 : 1; | ||
| 315 | unsigned int spu0_2 : 1; | ||
| 316 | unsigned int spu0_3 : 1; | ||
| 317 | unsigned int spu0_4 : 1; | ||
| 318 | unsigned int spu0_5 : 1; | ||
| 319 | unsigned int spu0_6 : 1; | ||
| 320 | unsigned int spu0_7 : 1; | ||
| 321 | unsigned int spu1_8 : 1; | ||
| 322 | unsigned int spu1_9 : 1; | ||
| 323 | unsigned int spu1_10 : 1; | ||
| 324 | unsigned int spu1_11 : 1; | ||
| 325 | unsigned int spu1_12 : 1; | ||
| 326 | unsigned int spu1_13 : 1; | ||
| 327 | unsigned int spu1_14 : 1; | ||
| 328 | unsigned int spu1_15 : 1; | ||
| 329 | } reg_iop_sw_cpu_rw_ack_intr0; | ||
| 330 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88 | ||
| 331 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88 | ||
| 332 | |||
| 333 | /* Register r_intr0, scope iop_sw_cpu, type r */ | ||
| 334 | typedef struct { | ||
| 335 | unsigned int mpu_0 : 1; | ||
| 336 | unsigned int mpu_1 : 1; | ||
| 337 | unsigned int mpu_2 : 1; | ||
| 338 | unsigned int mpu_3 : 1; | ||
| 339 | unsigned int mpu_4 : 1; | ||
| 340 | unsigned int mpu_5 : 1; | ||
| 341 | unsigned int mpu_6 : 1; | ||
| 342 | unsigned int mpu_7 : 1; | ||
| 343 | unsigned int mpu_8 : 1; | ||
| 344 | unsigned int mpu_9 : 1; | ||
| 345 | unsigned int mpu_10 : 1; | ||
| 346 | unsigned int mpu_11 : 1; | ||
| 347 | unsigned int mpu_12 : 1; | ||
| 348 | unsigned int mpu_13 : 1; | ||
| 349 | unsigned int mpu_14 : 1; | ||
| 350 | unsigned int mpu_15 : 1; | ||
| 351 | unsigned int spu0_0 : 1; | ||
| 352 | unsigned int spu0_1 : 1; | ||
| 353 | unsigned int spu0_2 : 1; | ||
| 354 | unsigned int spu0_3 : 1; | ||
| 355 | unsigned int spu0_4 : 1; | ||
| 356 | unsigned int spu0_5 : 1; | ||
| 357 | unsigned int spu0_6 : 1; | ||
| 358 | unsigned int spu0_7 : 1; | ||
| 359 | unsigned int spu1_8 : 1; | ||
| 360 | unsigned int spu1_9 : 1; | ||
| 361 | unsigned int spu1_10 : 1; | ||
| 362 | unsigned int spu1_11 : 1; | ||
| 363 | unsigned int spu1_12 : 1; | ||
| 364 | unsigned int spu1_13 : 1; | ||
| 365 | unsigned int spu1_14 : 1; | ||
| 366 | unsigned int spu1_15 : 1; | ||
| 367 | } reg_iop_sw_cpu_r_intr0; | ||
| 368 | #define REG_RD_ADDR_iop_sw_cpu_r_intr0 92 | ||
| 369 | |||
| 370 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | ||
| 371 | typedef struct { | ||
| 372 | unsigned int mpu_0 : 1; | ||
| 373 | unsigned int mpu_1 : 1; | ||
| 374 | unsigned int mpu_2 : 1; | ||
| 375 | unsigned int mpu_3 : 1; | ||
| 376 | unsigned int mpu_4 : 1; | ||
| 377 | unsigned int mpu_5 : 1; | ||
| 378 | unsigned int mpu_6 : 1; | ||
| 379 | unsigned int mpu_7 : 1; | ||
| 380 | unsigned int mpu_8 : 1; | ||
| 381 | unsigned int mpu_9 : 1; | ||
| 382 | unsigned int mpu_10 : 1; | ||
| 383 | unsigned int mpu_11 : 1; | ||
| 384 | unsigned int mpu_12 : 1; | ||
| 385 | unsigned int mpu_13 : 1; | ||
| 386 | unsigned int mpu_14 : 1; | ||
| 387 | unsigned int mpu_15 : 1; | ||
| 388 | unsigned int spu0_0 : 1; | ||
| 389 | unsigned int spu0_1 : 1; | ||
| 390 | unsigned int spu0_2 : 1; | ||
| 391 | unsigned int spu0_3 : 1; | ||
| 392 | unsigned int spu0_4 : 1; | ||
| 393 | unsigned int spu0_5 : 1; | ||
| 394 | unsigned int spu0_6 : 1; | ||
| 395 | unsigned int spu0_7 : 1; | ||
| 396 | unsigned int spu1_8 : 1; | ||
| 397 | unsigned int spu1_9 : 1; | ||
| 398 | unsigned int spu1_10 : 1; | ||
| 399 | unsigned int spu1_11 : 1; | ||
| 400 | unsigned int spu1_12 : 1; | ||
| 401 | unsigned int spu1_13 : 1; | ||
| 402 | unsigned int spu1_14 : 1; | ||
| 403 | unsigned int spu1_15 : 1; | ||
| 404 | } reg_iop_sw_cpu_r_masked_intr0; | ||
| 405 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96 | ||
| 406 | |||
| 407 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | ||
| 408 | typedef struct { | ||
| 409 | unsigned int mpu_16 : 1; | ||
| 410 | unsigned int mpu_17 : 1; | ||
| 411 | unsigned int mpu_18 : 1; | ||
| 412 | unsigned int mpu_19 : 1; | ||
| 413 | unsigned int mpu_20 : 1; | ||
| 414 | unsigned int mpu_21 : 1; | ||
| 415 | unsigned int mpu_22 : 1; | ||
| 416 | unsigned int mpu_23 : 1; | ||
| 417 | unsigned int mpu_24 : 1; | ||
| 418 | unsigned int mpu_25 : 1; | ||
| 419 | unsigned int mpu_26 : 1; | ||
| 420 | unsigned int mpu_27 : 1; | ||
| 421 | unsigned int mpu_28 : 1; | ||
| 422 | unsigned int mpu_29 : 1; | ||
| 423 | unsigned int mpu_30 : 1; | ||
| 424 | unsigned int mpu_31 : 1; | ||
| 425 | unsigned int spu0_8 : 1; | ||
| 426 | unsigned int spu0_9 : 1; | ||
| 427 | unsigned int spu0_10 : 1; | ||
| 428 | unsigned int spu0_11 : 1; | ||
| 429 | unsigned int spu0_12 : 1; | ||
| 430 | unsigned int spu0_13 : 1; | ||
| 431 | unsigned int spu0_14 : 1; | ||
| 432 | unsigned int spu0_15 : 1; | ||
| 433 | unsigned int spu1_0 : 1; | ||
| 434 | unsigned int spu1_1 : 1; | ||
| 435 | unsigned int spu1_2 : 1; | ||
| 436 | unsigned int spu1_3 : 1; | ||
| 437 | unsigned int spu1_4 : 1; | ||
| 438 | unsigned int spu1_5 : 1; | ||
| 439 | unsigned int spu1_6 : 1; | ||
| 440 | unsigned int spu1_7 : 1; | ||
| 441 | } reg_iop_sw_cpu_rw_intr1_mask; | ||
| 442 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100 | ||
| 443 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100 | ||
| 444 | |||
| 445 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | ||
| 446 | typedef struct { | ||
| 447 | unsigned int mpu_16 : 1; | ||
| 448 | unsigned int mpu_17 : 1; | ||
| 449 | unsigned int mpu_18 : 1; | ||
| 450 | unsigned int mpu_19 : 1; | ||
| 451 | unsigned int mpu_20 : 1; | ||
| 452 | unsigned int mpu_21 : 1; | ||
| 453 | unsigned int mpu_22 : 1; | ||
| 454 | unsigned int mpu_23 : 1; | ||
| 455 | unsigned int mpu_24 : 1; | ||
| 456 | unsigned int mpu_25 : 1; | ||
| 457 | unsigned int mpu_26 : 1; | ||
| 458 | unsigned int mpu_27 : 1; | ||
| 459 | unsigned int mpu_28 : 1; | ||
| 460 | unsigned int mpu_29 : 1; | ||
| 461 | unsigned int mpu_30 : 1; | ||
| 462 | unsigned int mpu_31 : 1; | ||
| 463 | unsigned int spu0_8 : 1; | ||
| 464 | unsigned int spu0_9 : 1; | ||
| 465 | unsigned int spu0_10 : 1; | ||
| 466 | unsigned int spu0_11 : 1; | ||
| 467 | unsigned int spu0_12 : 1; | ||
| 468 | unsigned int spu0_13 : 1; | ||
| 469 | unsigned int spu0_14 : 1; | ||
| 470 | unsigned int spu0_15 : 1; | ||
| 471 | unsigned int spu1_0 : 1; | ||
| 472 | unsigned int spu1_1 : 1; | ||
| 473 | unsigned int spu1_2 : 1; | ||
| 474 | unsigned int spu1_3 : 1; | ||
| 475 | unsigned int spu1_4 : 1; | ||
| 476 | unsigned int spu1_5 : 1; | ||
| 477 | unsigned int spu1_6 : 1; | ||
| 478 | unsigned int spu1_7 : 1; | ||
| 479 | } reg_iop_sw_cpu_rw_ack_intr1; | ||
| 480 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104 | ||
| 481 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104 | ||
| 482 | |||
| 483 | /* Register r_intr1, scope iop_sw_cpu, type r */ | ||
| 484 | typedef struct { | ||
| 485 | unsigned int mpu_16 : 1; | ||
| 486 | unsigned int mpu_17 : 1; | ||
| 487 | unsigned int mpu_18 : 1; | ||
| 488 | unsigned int mpu_19 : 1; | ||
| 489 | unsigned int mpu_20 : 1; | ||
| 490 | unsigned int mpu_21 : 1; | ||
| 491 | unsigned int mpu_22 : 1; | ||
| 492 | unsigned int mpu_23 : 1; | ||
| 493 | unsigned int mpu_24 : 1; | ||
| 494 | unsigned int mpu_25 : 1; | ||
| 495 | unsigned int mpu_26 : 1; | ||
| 496 | unsigned int mpu_27 : 1; | ||
| 497 | unsigned int mpu_28 : 1; | ||
| 498 | unsigned int mpu_29 : 1; | ||
| 499 | unsigned int mpu_30 : 1; | ||
| 500 | unsigned int mpu_31 : 1; | ||
| 501 | unsigned int spu0_8 : 1; | ||
| 502 | unsigned int spu0_9 : 1; | ||
| 503 | unsigned int spu0_10 : 1; | ||
| 504 | unsigned int spu0_11 : 1; | ||
| 505 | unsigned int spu0_12 : 1; | ||
| 506 | unsigned int spu0_13 : 1; | ||
| 507 | unsigned int spu0_14 : 1; | ||
| 508 | unsigned int spu0_15 : 1; | ||
| 509 | unsigned int spu1_0 : 1; | ||
| 510 | unsigned int spu1_1 : 1; | ||
| 511 | unsigned int spu1_2 : 1; | ||
| 512 | unsigned int spu1_3 : 1; | ||
| 513 | unsigned int spu1_4 : 1; | ||
| 514 | unsigned int spu1_5 : 1; | ||
| 515 | unsigned int spu1_6 : 1; | ||
| 516 | unsigned int spu1_7 : 1; | ||
| 517 | } reg_iop_sw_cpu_r_intr1; | ||
| 518 | #define REG_RD_ADDR_iop_sw_cpu_r_intr1 108 | ||
| 519 | |||
| 520 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | ||
| 521 | typedef struct { | ||
| 522 | unsigned int mpu_16 : 1; | ||
| 523 | unsigned int mpu_17 : 1; | ||
| 524 | unsigned int mpu_18 : 1; | ||
| 525 | unsigned int mpu_19 : 1; | ||
| 526 | unsigned int mpu_20 : 1; | ||
| 527 | unsigned int mpu_21 : 1; | ||
| 528 | unsigned int mpu_22 : 1; | ||
| 529 | unsigned int mpu_23 : 1; | ||
| 530 | unsigned int mpu_24 : 1; | ||
| 531 | unsigned int mpu_25 : 1; | ||
| 532 | unsigned int mpu_26 : 1; | ||
| 533 | unsigned int mpu_27 : 1; | ||
| 534 | unsigned int mpu_28 : 1; | ||
| 535 | unsigned int mpu_29 : 1; | ||
| 536 | unsigned int mpu_30 : 1; | ||
| 537 | unsigned int mpu_31 : 1; | ||
| 538 | unsigned int spu0_8 : 1; | ||
| 539 | unsigned int spu0_9 : 1; | ||
| 540 | unsigned int spu0_10 : 1; | ||
| 541 | unsigned int spu0_11 : 1; | ||
| 542 | unsigned int spu0_12 : 1; | ||
| 543 | unsigned int spu0_13 : 1; | ||
| 544 | unsigned int spu0_14 : 1; | ||
| 545 | unsigned int spu0_15 : 1; | ||
| 546 | unsigned int spu1_0 : 1; | ||
| 547 | unsigned int spu1_1 : 1; | ||
| 548 | unsigned int spu1_2 : 1; | ||
| 549 | unsigned int spu1_3 : 1; | ||
| 550 | unsigned int spu1_4 : 1; | ||
| 551 | unsigned int spu1_5 : 1; | ||
| 552 | unsigned int spu1_6 : 1; | ||
| 553 | unsigned int spu1_7 : 1; | ||
| 554 | } reg_iop_sw_cpu_r_masked_intr1; | ||
| 555 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112 | ||
| 556 | |||
| 557 | /* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ | ||
| 558 | typedef struct { | ||
| 559 | unsigned int mpu_0 : 1; | ||
| 560 | unsigned int mpu_1 : 1; | ||
| 561 | unsigned int mpu_2 : 1; | ||
| 562 | unsigned int mpu_3 : 1; | ||
| 563 | unsigned int mpu_4 : 1; | ||
| 564 | unsigned int mpu_5 : 1; | ||
| 565 | unsigned int mpu_6 : 1; | ||
| 566 | unsigned int mpu_7 : 1; | ||
| 567 | unsigned int spu0_0 : 1; | ||
| 568 | unsigned int spu0_1 : 1; | ||
| 569 | unsigned int spu0_2 : 1; | ||
| 570 | unsigned int spu0_3 : 1; | ||
| 571 | unsigned int spu0_4 : 1; | ||
| 572 | unsigned int spu0_5 : 1; | ||
| 573 | unsigned int spu0_6 : 1; | ||
| 574 | unsigned int spu0_7 : 1; | ||
| 575 | unsigned int dmc_in0 : 1; | ||
| 576 | unsigned int dmc_out0 : 1; | ||
| 577 | unsigned int fifo_in0 : 1; | ||
| 578 | unsigned int fifo_out0 : 1; | ||
| 579 | unsigned int fifo_in0_extra : 1; | ||
| 580 | unsigned int fifo_out0_extra : 1; | ||
| 581 | unsigned int trigger_grp0 : 1; | ||
| 582 | unsigned int trigger_grp1 : 1; | ||
| 583 | unsigned int trigger_grp2 : 1; | ||
| 584 | unsigned int trigger_grp3 : 1; | ||
| 585 | unsigned int trigger_grp4 : 1; | ||
| 586 | unsigned int trigger_grp5 : 1; | ||
| 587 | unsigned int trigger_grp6 : 1; | ||
| 588 | unsigned int trigger_grp7 : 1; | ||
| 589 | unsigned int timer_grp0 : 1; | ||
| 590 | unsigned int timer_grp1 : 1; | ||
| 591 | } reg_iop_sw_cpu_rw_intr2_mask; | ||
| 592 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116 | ||
| 593 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116 | ||
| 594 | |||
| 595 | /* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ | ||
| 596 | typedef struct { | ||
| 597 | unsigned int mpu_0 : 1; | ||
| 598 | unsigned int mpu_1 : 1; | ||
| 599 | unsigned int mpu_2 : 1; | ||
| 600 | unsigned int mpu_3 : 1; | ||
| 601 | unsigned int mpu_4 : 1; | ||
| 602 | unsigned int mpu_5 : 1; | ||
| 603 | unsigned int mpu_6 : 1; | ||
| 604 | unsigned int mpu_7 : 1; | ||
| 605 | unsigned int spu0_0 : 1; | ||
| 606 | unsigned int spu0_1 : 1; | ||
| 607 | unsigned int spu0_2 : 1; | ||
| 608 | unsigned int spu0_3 : 1; | ||
| 609 | unsigned int spu0_4 : 1; | ||
| 610 | unsigned int spu0_5 : 1; | ||
| 611 | unsigned int spu0_6 : 1; | ||
| 612 | unsigned int spu0_7 : 1; | ||
| 613 | unsigned int dummy1 : 16; | ||
| 614 | } reg_iop_sw_cpu_rw_ack_intr2; | ||
| 615 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120 | ||
| 616 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120 | ||
| 617 | |||
| 618 | /* Register r_intr2, scope iop_sw_cpu, type r */ | ||
| 619 | typedef struct { | ||
| 620 | unsigned int mpu_0 : 1; | ||
| 621 | unsigned int mpu_1 : 1; | ||
| 622 | unsigned int mpu_2 : 1; | ||
| 623 | unsigned int mpu_3 : 1; | ||
| 624 | unsigned int mpu_4 : 1; | ||
| 625 | unsigned int mpu_5 : 1; | ||
| 626 | unsigned int mpu_6 : 1; | ||
| 627 | unsigned int mpu_7 : 1; | ||
| 628 | unsigned int spu0_0 : 1; | ||
| 629 | unsigned int spu0_1 : 1; | ||
| 630 | unsigned int spu0_2 : 1; | ||
| 631 | unsigned int spu0_3 : 1; | ||
| 632 | unsigned int spu0_4 : 1; | ||
| 633 | unsigned int spu0_5 : 1; | ||
| 634 | unsigned int spu0_6 : 1; | ||
| 635 | unsigned int spu0_7 : 1; | ||
| 636 | unsigned int dmc_in0 : 1; | ||
| 637 | unsigned int dmc_out0 : 1; | ||
| 638 | unsigned int fifo_in0 : 1; | ||
| 639 | unsigned int fifo_out0 : 1; | ||
| 640 | unsigned int fifo_in0_extra : 1; | ||
| 641 | unsigned int fifo_out0_extra : 1; | ||
| 642 | unsigned int trigger_grp0 : 1; | ||
| 643 | unsigned int trigger_grp1 : 1; | ||
| 644 | unsigned int trigger_grp2 : 1; | ||
| 645 | unsigned int trigger_grp3 : 1; | ||
| 646 | unsigned int trigger_grp4 : 1; | ||
| 647 | unsigned int trigger_grp5 : 1; | ||
| 648 | unsigned int trigger_grp6 : 1; | ||
| 649 | unsigned int trigger_grp7 : 1; | ||
| 650 | unsigned int timer_grp0 : 1; | ||
| 651 | unsigned int timer_grp1 : 1; | ||
| 652 | } reg_iop_sw_cpu_r_intr2; | ||
| 653 | #define REG_RD_ADDR_iop_sw_cpu_r_intr2 124 | ||
| 654 | |||
| 655 | /* Register r_masked_intr2, scope iop_sw_cpu, type r */ | ||
| 656 | typedef struct { | ||
| 657 | unsigned int mpu_0 : 1; | ||
| 658 | unsigned int mpu_1 : 1; | ||
| 659 | unsigned int mpu_2 : 1; | ||
| 660 | unsigned int mpu_3 : 1; | ||
| 661 | unsigned int mpu_4 : 1; | ||
| 662 | unsigned int mpu_5 : 1; | ||
| 663 | unsigned int mpu_6 : 1; | ||
| 664 | unsigned int mpu_7 : 1; | ||
| 665 | unsigned int spu0_0 : 1; | ||
| 666 | unsigned int spu0_1 : 1; | ||
| 667 | unsigned int spu0_2 : 1; | ||
| 668 | unsigned int spu0_3 : 1; | ||
| 669 | unsigned int spu0_4 : 1; | ||
| 670 | unsigned int spu0_5 : 1; | ||
| 671 | unsigned int spu0_6 : 1; | ||
| 672 | unsigned int spu0_7 : 1; | ||
| 673 | unsigned int dmc_in0 : 1; | ||
| 674 | unsigned int dmc_out0 : 1; | ||
| 675 | unsigned int fifo_in0 : 1; | ||
| 676 | unsigned int fifo_out0 : 1; | ||
| 677 | unsigned int fifo_in0_extra : 1; | ||
| 678 | unsigned int fifo_out0_extra : 1; | ||
| 679 | unsigned int trigger_grp0 : 1; | ||
| 680 | unsigned int trigger_grp1 : 1; | ||
| 681 | unsigned int trigger_grp2 : 1; | ||
| 682 | unsigned int trigger_grp3 : 1; | ||
| 683 | unsigned int trigger_grp4 : 1; | ||
| 684 | unsigned int trigger_grp5 : 1; | ||
| 685 | unsigned int trigger_grp6 : 1; | ||
| 686 | unsigned int trigger_grp7 : 1; | ||
| 687 | unsigned int timer_grp0 : 1; | ||
| 688 | unsigned int timer_grp1 : 1; | ||
| 689 | } reg_iop_sw_cpu_r_masked_intr2; | ||
| 690 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128 | ||
| 691 | |||
| 692 | /* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ | ||
| 693 | typedef struct { | ||
| 694 | unsigned int mpu_16 : 1; | ||
| 695 | unsigned int mpu_17 : 1; | ||
| 696 | unsigned int mpu_18 : 1; | ||
| 697 | unsigned int mpu_19 : 1; | ||
| 698 | unsigned int mpu_20 : 1; | ||
| 699 | unsigned int mpu_21 : 1; | ||
| 700 | unsigned int mpu_22 : 1; | ||
| 701 | unsigned int mpu_23 : 1; | ||
| 702 | unsigned int spu1_0 : 1; | ||
| 703 | unsigned int spu1_1 : 1; | ||
| 704 | unsigned int spu1_2 : 1; | ||
| 705 | unsigned int spu1_3 : 1; | ||
| 706 | unsigned int spu1_4 : 1; | ||
| 707 | unsigned int spu1_5 : 1; | ||
| 708 | unsigned int spu1_6 : 1; | ||
| 709 | unsigned int spu1_7 : 1; | ||
| 710 | unsigned int dmc_in1 : 1; | ||
| 711 | unsigned int dmc_out1 : 1; | ||
| 712 | unsigned int fifo_in1 : 1; | ||
| 713 | unsigned int fifo_out1 : 1; | ||
| 714 | unsigned int fifo_in1_extra : 1; | ||
| 715 | unsigned int fifo_out1_extra : 1; | ||
| 716 | unsigned int trigger_grp0 : 1; | ||
| 717 | unsigned int trigger_grp1 : 1; | ||
| 718 | unsigned int trigger_grp2 : 1; | ||
| 719 | unsigned int trigger_grp3 : 1; | ||
| 720 | unsigned int trigger_grp4 : 1; | ||
| 721 | unsigned int trigger_grp5 : 1; | ||
| 722 | unsigned int trigger_grp6 : 1; | ||
| 723 | unsigned int trigger_grp7 : 1; | ||
| 724 | unsigned int timer_grp2 : 1; | ||
| 725 | unsigned int timer_grp3 : 1; | ||
| 726 | } reg_iop_sw_cpu_rw_intr3_mask; | ||
| 727 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132 | ||
| 728 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132 | ||
| 729 | |||
| 730 | /* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ | ||
| 731 | typedef struct { | ||
| 732 | unsigned int mpu_16 : 1; | ||
| 733 | unsigned int mpu_17 : 1; | ||
| 734 | unsigned int mpu_18 : 1; | ||
| 735 | unsigned int mpu_19 : 1; | ||
| 736 | unsigned int mpu_20 : 1; | ||
| 737 | unsigned int mpu_21 : 1; | ||
| 738 | unsigned int mpu_22 : 1; | ||
| 739 | unsigned int mpu_23 : 1; | ||
| 740 | unsigned int spu1_0 : 1; | ||
| 741 | unsigned int spu1_1 : 1; | ||
| 742 | unsigned int spu1_2 : 1; | ||
| 743 | unsigned int spu1_3 : 1; | ||
| 744 | unsigned int spu1_4 : 1; | ||
| 745 | unsigned int spu1_5 : 1; | ||
| 746 | unsigned int spu1_6 : 1; | ||
| 747 | unsigned int spu1_7 : 1; | ||
| 748 | unsigned int dummy1 : 16; | ||
| 749 | } reg_iop_sw_cpu_rw_ack_intr3; | ||
| 750 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136 | ||
| 751 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136 | ||
| 752 | |||
| 753 | /* Register r_intr3, scope iop_sw_cpu, type r */ | ||
| 754 | typedef struct { | ||
| 755 | unsigned int mpu_16 : 1; | ||
| 756 | unsigned int mpu_17 : 1; | ||
| 757 | unsigned int mpu_18 : 1; | ||
| 758 | unsigned int mpu_19 : 1; | ||
| 759 | unsigned int mpu_20 : 1; | ||
| 760 | unsigned int mpu_21 : 1; | ||
| 761 | unsigned int mpu_22 : 1; | ||
| 762 | unsigned int mpu_23 : 1; | ||
| 763 | unsigned int spu1_0 : 1; | ||
| 764 | unsigned int spu1_1 : 1; | ||
| 765 | unsigned int spu1_2 : 1; | ||
| 766 | unsigned int spu1_3 : 1; | ||
| 767 | unsigned int spu1_4 : 1; | ||
| 768 | unsigned int spu1_5 : 1; | ||
| 769 | unsigned int spu1_6 : 1; | ||
| 770 | unsigned int spu1_7 : 1; | ||
| 771 | unsigned int dmc_in1 : 1; | ||
| 772 | unsigned int dmc_out1 : 1; | ||
| 773 | unsigned int fifo_in1 : 1; | ||
| 774 | unsigned int fifo_out1 : 1; | ||
| 775 | unsigned int fifo_in1_extra : 1; | ||
| 776 | unsigned int fifo_out1_extra : 1; | ||
| 777 | unsigned int trigger_grp0 : 1; | ||
| 778 | unsigned int trigger_grp1 : 1; | ||
| 779 | unsigned int trigger_grp2 : 1; | ||
| 780 | unsigned int trigger_grp3 : 1; | ||
| 781 | unsigned int trigger_grp4 : 1; | ||
| 782 | unsigned int trigger_grp5 : 1; | ||
| 783 | unsigned int trigger_grp6 : 1; | ||
| 784 | unsigned int trigger_grp7 : 1; | ||
| 785 | unsigned int timer_grp2 : 1; | ||
| 786 | unsigned int timer_grp3 : 1; | ||
| 787 | } reg_iop_sw_cpu_r_intr3; | ||
| 788 | #define REG_RD_ADDR_iop_sw_cpu_r_intr3 140 | ||
| 789 | |||
| 790 | /* Register r_masked_intr3, scope iop_sw_cpu, type r */ | ||
| 791 | typedef struct { | ||
| 792 | unsigned int mpu_16 : 1; | ||
| 793 | unsigned int mpu_17 : 1; | ||
| 794 | unsigned int mpu_18 : 1; | ||
| 795 | unsigned int mpu_19 : 1; | ||
| 796 | unsigned int mpu_20 : 1; | ||
| 797 | unsigned int mpu_21 : 1; | ||
| 798 | unsigned int mpu_22 : 1; | ||
| 799 | unsigned int mpu_23 : 1; | ||
| 800 | unsigned int spu1_0 : 1; | ||
| 801 | unsigned int spu1_1 : 1; | ||
| 802 | unsigned int spu1_2 : 1; | ||
| 803 | unsigned int spu1_3 : 1; | ||
| 804 | unsigned int spu1_4 : 1; | ||
| 805 | unsigned int spu1_5 : 1; | ||
| 806 | unsigned int spu1_6 : 1; | ||
| 807 | unsigned int spu1_7 : 1; | ||
| 808 | unsigned int dmc_in1 : 1; | ||
| 809 | unsigned int dmc_out1 : 1; | ||
| 810 | unsigned int fifo_in1 : 1; | ||
| 811 | unsigned int fifo_out1 : 1; | ||
| 812 | unsigned int fifo_in1_extra : 1; | ||
| 813 | unsigned int fifo_out1_extra : 1; | ||
| 814 | unsigned int trigger_grp0 : 1; | ||
| 815 | unsigned int trigger_grp1 : 1; | ||
| 816 | unsigned int trigger_grp2 : 1; | ||
| 817 | unsigned int trigger_grp3 : 1; | ||
| 818 | unsigned int trigger_grp4 : 1; | ||
| 819 | unsigned int trigger_grp5 : 1; | ||
| 820 | unsigned int trigger_grp6 : 1; | ||
| 821 | unsigned int trigger_grp7 : 1; | ||
| 822 | unsigned int timer_grp2 : 1; | ||
| 823 | unsigned int timer_grp3 : 1; | ||
| 824 | } reg_iop_sw_cpu_r_masked_intr3; | ||
| 825 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144 | ||
| 826 | |||
| 827 | |||
| 828 | /* Constants */ | ||
| 829 | enum { | ||
| 830 | regk_iop_sw_cpu_copy = 0x00000000, | ||
| 831 | regk_iop_sw_cpu_no = 0x00000000, | ||
| 832 | regk_iop_sw_cpu_rd = 0x00000002, | ||
| 833 | regk_iop_sw_cpu_reg_copy = 0x00000001, | ||
| 834 | regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, | ||
| 835 | regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, | ||
| 836 | regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, | ||
| 837 | regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, | ||
| 838 | regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, | ||
| 839 | regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, | ||
| 840 | regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, | ||
| 841 | regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, | ||
| 842 | regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, | ||
| 843 | regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 844 | regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 845 | regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, | ||
| 846 | regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, | ||
| 847 | regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, | ||
| 848 | regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, | ||
| 849 | regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, | ||
| 850 | regk_iop_sw_cpu_wr = 0x00000003, | ||
| 851 | regk_iop_sw_cpu_yes = 0x00000001 | ||
| 852 | }; | ||
| 853 | #endif /* __iop_sw_cpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index da718f2a8cad..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null | |||
| @@ -1,893 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_mpu_defs_h | ||
| 2 | #define __iop_sw_mpu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:19 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r | ||
| 11 | * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_sw_mpu */ | ||
| 86 | |||
| 87 | /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int cfg : 2; | ||
| 90 | unsigned int dummy1 : 30; | ||
| 91 | } reg_iop_sw_mpu_rw_sw_cfg_owner; | ||
| 92 | #define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 | ||
| 93 | #define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 | ||
| 94 | |||
| 95 | /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ | ||
| 96 | typedef struct { | ||
| 97 | unsigned int keep_owner : 1; | ||
| 98 | unsigned int cmd : 2; | ||
| 99 | unsigned int size : 3; | ||
| 100 | unsigned int wr_spu0_mem : 1; | ||
| 101 | unsigned int wr_spu1_mem : 1; | ||
| 102 | unsigned int dummy1 : 24; | ||
| 103 | } reg_iop_sw_mpu_rw_mc_ctrl; | ||
| 104 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4 | ||
| 105 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4 | ||
| 106 | |||
| 107 | /* Register rw_mc_data, scope iop_sw_mpu, type rw */ | ||
| 108 | typedef struct { | ||
| 109 | unsigned int val : 32; | ||
| 110 | } reg_iop_sw_mpu_rw_mc_data; | ||
| 111 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8 | ||
| 112 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8 | ||
| 113 | |||
| 114 | /* Register rw_mc_addr, scope iop_sw_mpu, type rw */ | ||
| 115 | typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; | ||
| 116 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12 | ||
| 117 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12 | ||
| 118 | |||
| 119 | /* Register rs_mc_data, scope iop_sw_mpu, type rs */ | ||
| 120 | typedef unsigned int reg_iop_sw_mpu_rs_mc_data; | ||
| 121 | #define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16 | ||
| 122 | |||
| 123 | /* Register r_mc_data, scope iop_sw_mpu, type r */ | ||
| 124 | typedef unsigned int reg_iop_sw_mpu_r_mc_data; | ||
| 125 | #define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20 | ||
| 126 | |||
| 127 | /* Register r_mc_stat, scope iop_sw_mpu, type r */ | ||
| 128 | typedef struct { | ||
| 129 | unsigned int busy_cpu : 1; | ||
| 130 | unsigned int busy_mpu : 1; | ||
| 131 | unsigned int busy_spu0 : 1; | ||
| 132 | unsigned int busy_spu1 : 1; | ||
| 133 | unsigned int owned_by_cpu : 1; | ||
| 134 | unsigned int owned_by_mpu : 1; | ||
| 135 | unsigned int owned_by_spu0 : 1; | ||
| 136 | unsigned int owned_by_spu1 : 1; | ||
| 137 | unsigned int dummy1 : 24; | ||
| 138 | } reg_iop_sw_mpu_r_mc_stat; | ||
| 139 | #define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24 | ||
| 140 | |||
| 141 | /* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 142 | typedef struct { | ||
| 143 | unsigned int byte0 : 8; | ||
| 144 | unsigned int byte1 : 8; | ||
| 145 | unsigned int byte2 : 8; | ||
| 146 | unsigned int byte3 : 8; | ||
| 147 | } reg_iop_sw_mpu_rw_bus0_clr_mask; | ||
| 148 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 | ||
| 149 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 | ||
| 150 | |||
| 151 | /* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ | ||
| 152 | typedef struct { | ||
| 153 | unsigned int byte0 : 8; | ||
| 154 | unsigned int byte1 : 8; | ||
| 155 | unsigned int byte2 : 8; | ||
| 156 | unsigned int byte3 : 8; | ||
| 157 | } reg_iop_sw_mpu_rw_bus0_set_mask; | ||
| 158 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 | ||
| 159 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 | ||
| 160 | |||
| 161 | /* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 162 | typedef struct { | ||
| 163 | unsigned int byte0 : 1; | ||
| 164 | unsigned int byte1 : 1; | ||
| 165 | unsigned int byte2 : 1; | ||
| 166 | unsigned int byte3 : 1; | ||
| 167 | unsigned int dummy1 : 28; | ||
| 168 | } reg_iop_sw_mpu_rw_bus0_oe_clr_mask; | ||
| 169 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 | ||
| 170 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 | ||
| 171 | |||
| 172 | /* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 173 | typedef struct { | ||
| 174 | unsigned int byte0 : 1; | ||
| 175 | unsigned int byte1 : 1; | ||
| 176 | unsigned int byte2 : 1; | ||
| 177 | unsigned int byte3 : 1; | ||
| 178 | unsigned int dummy1 : 28; | ||
| 179 | } reg_iop_sw_mpu_rw_bus0_oe_set_mask; | ||
| 180 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 | ||
| 181 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 | ||
| 182 | |||
| 183 | /* Register r_bus0_in, scope iop_sw_mpu, type r */ | ||
| 184 | typedef unsigned int reg_iop_sw_mpu_r_bus0_in; | ||
| 185 | #define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44 | ||
| 186 | |||
| 187 | /* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 188 | typedef struct { | ||
| 189 | unsigned int byte0 : 8; | ||
| 190 | unsigned int byte1 : 8; | ||
| 191 | unsigned int byte2 : 8; | ||
| 192 | unsigned int byte3 : 8; | ||
| 193 | } reg_iop_sw_mpu_rw_bus1_clr_mask; | ||
| 194 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 | ||
| 195 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 | ||
| 196 | |||
| 197 | /* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ | ||
| 198 | typedef struct { | ||
| 199 | unsigned int byte0 : 8; | ||
| 200 | unsigned int byte1 : 8; | ||
| 201 | unsigned int byte2 : 8; | ||
| 202 | unsigned int byte3 : 8; | ||
| 203 | } reg_iop_sw_mpu_rw_bus1_set_mask; | ||
| 204 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 | ||
| 205 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 | ||
| 206 | |||
| 207 | /* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 208 | typedef struct { | ||
| 209 | unsigned int byte0 : 1; | ||
| 210 | unsigned int byte1 : 1; | ||
| 211 | unsigned int byte2 : 1; | ||
| 212 | unsigned int byte3 : 1; | ||
| 213 | unsigned int dummy1 : 28; | ||
| 214 | } reg_iop_sw_mpu_rw_bus1_oe_clr_mask; | ||
| 215 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 | ||
| 216 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 | ||
| 217 | |||
| 218 | /* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 219 | typedef struct { | ||
| 220 | unsigned int byte0 : 1; | ||
| 221 | unsigned int byte1 : 1; | ||
| 222 | unsigned int byte2 : 1; | ||
| 223 | unsigned int byte3 : 1; | ||
| 224 | unsigned int dummy1 : 28; | ||
| 225 | } reg_iop_sw_mpu_rw_bus1_oe_set_mask; | ||
| 226 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 | ||
| 227 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 | ||
| 228 | |||
| 229 | /* Register r_bus1_in, scope iop_sw_mpu, type r */ | ||
| 230 | typedef unsigned int reg_iop_sw_mpu_r_bus1_in; | ||
| 231 | #define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64 | ||
| 232 | |||
| 233 | /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 234 | typedef struct { | ||
| 235 | unsigned int val : 32; | ||
| 236 | } reg_iop_sw_mpu_rw_gio_clr_mask; | ||
| 237 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 | ||
| 238 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 | ||
| 239 | |||
| 240 | /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ | ||
| 241 | typedef struct { | ||
| 242 | unsigned int val : 32; | ||
| 243 | } reg_iop_sw_mpu_rw_gio_set_mask; | ||
| 244 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72 | ||
| 245 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72 | ||
| 246 | |||
| 247 | /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 248 | typedef struct { | ||
| 249 | unsigned int val : 32; | ||
| 250 | } reg_iop_sw_mpu_rw_gio_oe_clr_mask; | ||
| 251 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 | ||
| 252 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 | ||
| 253 | |||
| 254 | /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 255 | typedef struct { | ||
| 256 | unsigned int val : 32; | ||
| 257 | } reg_iop_sw_mpu_rw_gio_oe_set_mask; | ||
| 258 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 | ||
| 259 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 | ||
| 260 | |||
| 261 | /* Register r_gio_in, scope iop_sw_mpu, type r */ | ||
| 262 | typedef unsigned int reg_iop_sw_mpu_r_gio_in; | ||
| 263 | #define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84 | ||
| 264 | |||
| 265 | /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ | ||
| 266 | typedef struct { | ||
| 267 | unsigned int intr0 : 1; | ||
| 268 | unsigned int intr1 : 1; | ||
| 269 | unsigned int intr2 : 1; | ||
| 270 | unsigned int intr3 : 1; | ||
| 271 | unsigned int intr4 : 1; | ||
| 272 | unsigned int intr5 : 1; | ||
| 273 | unsigned int intr6 : 1; | ||
| 274 | unsigned int intr7 : 1; | ||
| 275 | unsigned int intr8 : 1; | ||
| 276 | unsigned int intr9 : 1; | ||
| 277 | unsigned int intr10 : 1; | ||
| 278 | unsigned int intr11 : 1; | ||
| 279 | unsigned int intr12 : 1; | ||
| 280 | unsigned int intr13 : 1; | ||
| 281 | unsigned int intr14 : 1; | ||
| 282 | unsigned int intr15 : 1; | ||
| 283 | unsigned int intr16 : 1; | ||
| 284 | unsigned int intr17 : 1; | ||
| 285 | unsigned int intr18 : 1; | ||
| 286 | unsigned int intr19 : 1; | ||
| 287 | unsigned int intr20 : 1; | ||
| 288 | unsigned int intr21 : 1; | ||
| 289 | unsigned int intr22 : 1; | ||
| 290 | unsigned int intr23 : 1; | ||
| 291 | unsigned int intr24 : 1; | ||
| 292 | unsigned int intr25 : 1; | ||
| 293 | unsigned int intr26 : 1; | ||
| 294 | unsigned int intr27 : 1; | ||
| 295 | unsigned int intr28 : 1; | ||
| 296 | unsigned int intr29 : 1; | ||
| 297 | unsigned int intr30 : 1; | ||
| 298 | unsigned int intr31 : 1; | ||
| 299 | } reg_iop_sw_mpu_rw_cpu_intr; | ||
| 300 | #define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88 | ||
| 301 | #define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88 | ||
| 302 | |||
| 303 | /* Register r_cpu_intr, scope iop_sw_mpu, type r */ | ||
| 304 | typedef struct { | ||
| 305 | unsigned int intr0 : 1; | ||
| 306 | unsigned int intr1 : 1; | ||
| 307 | unsigned int intr2 : 1; | ||
| 308 | unsigned int intr3 : 1; | ||
| 309 | unsigned int intr4 : 1; | ||
| 310 | unsigned int intr5 : 1; | ||
| 311 | unsigned int intr6 : 1; | ||
| 312 | unsigned int intr7 : 1; | ||
| 313 | unsigned int intr8 : 1; | ||
| 314 | unsigned int intr9 : 1; | ||
| 315 | unsigned int intr10 : 1; | ||
| 316 | unsigned int intr11 : 1; | ||
| 317 | unsigned int intr12 : 1; | ||
| 318 | unsigned int intr13 : 1; | ||
| 319 | unsigned int intr14 : 1; | ||
| 320 | unsigned int intr15 : 1; | ||
| 321 | unsigned int intr16 : 1; | ||
| 322 | unsigned int intr17 : 1; | ||
| 323 | unsigned int intr18 : 1; | ||
| 324 | unsigned int intr19 : 1; | ||
| 325 | unsigned int intr20 : 1; | ||
| 326 | unsigned int intr21 : 1; | ||
| 327 | unsigned int intr22 : 1; | ||
| 328 | unsigned int intr23 : 1; | ||
| 329 | unsigned int intr24 : 1; | ||
| 330 | unsigned int intr25 : 1; | ||
| 331 | unsigned int intr26 : 1; | ||
| 332 | unsigned int intr27 : 1; | ||
| 333 | unsigned int intr28 : 1; | ||
| 334 | unsigned int intr29 : 1; | ||
| 335 | unsigned int intr30 : 1; | ||
| 336 | unsigned int intr31 : 1; | ||
| 337 | } reg_iop_sw_mpu_r_cpu_intr; | ||
| 338 | #define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92 | ||
| 339 | |||
| 340 | /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ | ||
| 341 | typedef struct { | ||
| 342 | unsigned int spu0_intr0 : 1; | ||
| 343 | unsigned int spu1_intr0 : 1; | ||
| 344 | unsigned int trigger_grp0 : 1; | ||
| 345 | unsigned int trigger_grp4 : 1; | ||
| 346 | unsigned int timer_grp0 : 1; | ||
| 347 | unsigned int fifo_out0 : 1; | ||
| 348 | unsigned int fifo_out0_extra : 1; | ||
| 349 | unsigned int dmc_out0 : 1; | ||
| 350 | unsigned int spu0_intr1 : 1; | ||
| 351 | unsigned int spu1_intr1 : 1; | ||
| 352 | unsigned int trigger_grp1 : 1; | ||
| 353 | unsigned int trigger_grp5 : 1; | ||
| 354 | unsigned int timer_grp1 : 1; | ||
| 355 | unsigned int fifo_in0 : 1; | ||
| 356 | unsigned int fifo_in0_extra : 1; | ||
| 357 | unsigned int dmc_in0 : 1; | ||
| 358 | unsigned int spu0_intr2 : 1; | ||
| 359 | unsigned int spu1_intr2 : 1; | ||
| 360 | unsigned int trigger_grp2 : 1; | ||
| 361 | unsigned int trigger_grp6 : 1; | ||
| 362 | unsigned int timer_grp2 : 1; | ||
| 363 | unsigned int fifo_out1 : 1; | ||
| 364 | unsigned int fifo_out1_extra : 1; | ||
| 365 | unsigned int dmc_out1 : 1; | ||
| 366 | unsigned int spu0_intr3 : 1; | ||
| 367 | unsigned int spu1_intr3 : 1; | ||
| 368 | unsigned int trigger_grp3 : 1; | ||
| 369 | unsigned int trigger_grp7 : 1; | ||
| 370 | unsigned int timer_grp3 : 1; | ||
| 371 | unsigned int fifo_in1 : 1; | ||
| 372 | unsigned int fifo_in1_extra : 1; | ||
| 373 | unsigned int dmc_in1 : 1; | ||
| 374 | } reg_iop_sw_mpu_rw_intr_grp0_mask; | ||
| 375 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 | ||
| 376 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 | ||
| 377 | |||
| 378 | /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ | ||
| 379 | typedef struct { | ||
| 380 | unsigned int spu0_intr0 : 1; | ||
| 381 | unsigned int spu1_intr0 : 1; | ||
| 382 | unsigned int dummy1 : 6; | ||
| 383 | unsigned int spu0_intr1 : 1; | ||
| 384 | unsigned int spu1_intr1 : 1; | ||
| 385 | unsigned int dummy2 : 6; | ||
| 386 | unsigned int spu0_intr2 : 1; | ||
| 387 | unsigned int spu1_intr2 : 1; | ||
| 388 | unsigned int dummy3 : 6; | ||
| 389 | unsigned int spu0_intr3 : 1; | ||
| 390 | unsigned int spu1_intr3 : 1; | ||
| 391 | unsigned int dummy4 : 6; | ||
| 392 | } reg_iop_sw_mpu_rw_ack_intr_grp0; | ||
| 393 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 | ||
| 394 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 | ||
| 395 | |||
| 396 | /* Register r_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 397 | typedef struct { | ||
| 398 | unsigned int spu0_intr0 : 1; | ||
| 399 | unsigned int spu1_intr0 : 1; | ||
| 400 | unsigned int trigger_grp0 : 1; | ||
| 401 | unsigned int trigger_grp4 : 1; | ||
| 402 | unsigned int timer_grp0 : 1; | ||
| 403 | unsigned int fifo_out0 : 1; | ||
| 404 | unsigned int fifo_out0_extra : 1; | ||
| 405 | unsigned int dmc_out0 : 1; | ||
| 406 | unsigned int spu0_intr1 : 1; | ||
| 407 | unsigned int spu1_intr1 : 1; | ||
| 408 | unsigned int trigger_grp1 : 1; | ||
| 409 | unsigned int trigger_grp5 : 1; | ||
| 410 | unsigned int timer_grp1 : 1; | ||
| 411 | unsigned int fifo_in0 : 1; | ||
| 412 | unsigned int fifo_in0_extra : 1; | ||
| 413 | unsigned int dmc_in0 : 1; | ||
| 414 | unsigned int spu0_intr2 : 1; | ||
| 415 | unsigned int spu1_intr2 : 1; | ||
| 416 | unsigned int trigger_grp2 : 1; | ||
| 417 | unsigned int trigger_grp6 : 1; | ||
| 418 | unsigned int timer_grp2 : 1; | ||
| 419 | unsigned int fifo_out1 : 1; | ||
| 420 | unsigned int fifo_out1_extra : 1; | ||
| 421 | unsigned int dmc_out1 : 1; | ||
| 422 | unsigned int spu0_intr3 : 1; | ||
| 423 | unsigned int spu1_intr3 : 1; | ||
| 424 | unsigned int trigger_grp3 : 1; | ||
| 425 | unsigned int trigger_grp7 : 1; | ||
| 426 | unsigned int timer_grp3 : 1; | ||
| 427 | unsigned int fifo_in1 : 1; | ||
| 428 | unsigned int fifo_in1_extra : 1; | ||
| 429 | unsigned int dmc_in1 : 1; | ||
| 430 | } reg_iop_sw_mpu_r_intr_grp0; | ||
| 431 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104 | ||
| 432 | |||
| 433 | /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 434 | typedef struct { | ||
| 435 | unsigned int spu0_intr0 : 1; | ||
| 436 | unsigned int spu1_intr0 : 1; | ||
| 437 | unsigned int trigger_grp0 : 1; | ||
| 438 | unsigned int trigger_grp4 : 1; | ||
| 439 | unsigned int timer_grp0 : 1; | ||
| 440 | unsigned int fifo_out0 : 1; | ||
| 441 | unsigned int fifo_out0_extra : 1; | ||
| 442 | unsigned int dmc_out0 : 1; | ||
| 443 | unsigned int spu0_intr1 : 1; | ||
| 444 | unsigned int spu1_intr1 : 1; | ||
| 445 | unsigned int trigger_grp1 : 1; | ||
| 446 | unsigned int trigger_grp5 : 1; | ||
| 447 | unsigned int timer_grp1 : 1; | ||
| 448 | unsigned int fifo_in0 : 1; | ||
| 449 | unsigned int fifo_in0_extra : 1; | ||
| 450 | unsigned int dmc_in0 : 1; | ||
| 451 | unsigned int spu0_intr2 : 1; | ||
| 452 | unsigned int spu1_intr2 : 1; | ||
| 453 | unsigned int trigger_grp2 : 1; | ||
| 454 | unsigned int trigger_grp6 : 1; | ||
| 455 | unsigned int timer_grp2 : 1; | ||
| 456 | unsigned int fifo_out1 : 1; | ||
| 457 | unsigned int fifo_out1_extra : 1; | ||
| 458 | unsigned int dmc_out1 : 1; | ||
| 459 | unsigned int spu0_intr3 : 1; | ||
| 460 | unsigned int spu1_intr3 : 1; | ||
| 461 | unsigned int trigger_grp3 : 1; | ||
| 462 | unsigned int trigger_grp7 : 1; | ||
| 463 | unsigned int timer_grp3 : 1; | ||
| 464 | unsigned int fifo_in1 : 1; | ||
| 465 | unsigned int fifo_in1_extra : 1; | ||
| 466 | unsigned int dmc_in1 : 1; | ||
| 467 | } reg_iop_sw_mpu_r_masked_intr_grp0; | ||
| 468 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108 | ||
| 469 | |||
| 470 | /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ | ||
| 471 | typedef struct { | ||
| 472 | unsigned int spu0_intr4 : 1; | ||
| 473 | unsigned int spu1_intr4 : 1; | ||
| 474 | unsigned int trigger_grp0 : 1; | ||
| 475 | unsigned int trigger_grp5 : 1; | ||
| 476 | unsigned int timer_grp0 : 1; | ||
| 477 | unsigned int fifo_in0 : 1; | ||
| 478 | unsigned int fifo_in0_extra : 1; | ||
| 479 | unsigned int dmc_out0 : 1; | ||
| 480 | unsigned int spu0_intr5 : 1; | ||
| 481 | unsigned int spu1_intr5 : 1; | ||
| 482 | unsigned int trigger_grp1 : 1; | ||
| 483 | unsigned int trigger_grp6 : 1; | ||
| 484 | unsigned int timer_grp1 : 1; | ||
| 485 | unsigned int fifo_out1 : 1; | ||
| 486 | unsigned int fifo_out0_extra : 1; | ||
| 487 | unsigned int dmc_in0 : 1; | ||
| 488 | unsigned int spu0_intr6 : 1; | ||
| 489 | unsigned int spu1_intr6 : 1; | ||
| 490 | unsigned int trigger_grp2 : 1; | ||
| 491 | unsigned int trigger_grp7 : 1; | ||
| 492 | unsigned int timer_grp2 : 1; | ||
| 493 | unsigned int fifo_in1 : 1; | ||
| 494 | unsigned int fifo_in1_extra : 1; | ||
| 495 | unsigned int dmc_out1 : 1; | ||
| 496 | unsigned int spu0_intr7 : 1; | ||
| 497 | unsigned int spu1_intr7 : 1; | ||
| 498 | unsigned int trigger_grp3 : 1; | ||
| 499 | unsigned int trigger_grp4 : 1; | ||
| 500 | unsigned int timer_grp3 : 1; | ||
| 501 | unsigned int fifo_out0 : 1; | ||
| 502 | unsigned int fifo_out1_extra : 1; | ||
| 503 | unsigned int dmc_in1 : 1; | ||
| 504 | } reg_iop_sw_mpu_rw_intr_grp1_mask; | ||
| 505 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 | ||
| 506 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 | ||
| 507 | |||
| 508 | /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ | ||
| 509 | typedef struct { | ||
| 510 | unsigned int spu0_intr4 : 1; | ||
| 511 | unsigned int spu1_intr4 : 1; | ||
| 512 | unsigned int dummy1 : 6; | ||
| 513 | unsigned int spu0_intr5 : 1; | ||
| 514 | unsigned int spu1_intr5 : 1; | ||
| 515 | unsigned int dummy2 : 6; | ||
| 516 | unsigned int spu0_intr6 : 1; | ||
| 517 | unsigned int spu1_intr6 : 1; | ||
| 518 | unsigned int dummy3 : 6; | ||
| 519 | unsigned int spu0_intr7 : 1; | ||
| 520 | unsigned int spu1_intr7 : 1; | ||
| 521 | unsigned int dummy4 : 6; | ||
| 522 | } reg_iop_sw_mpu_rw_ack_intr_grp1; | ||
| 523 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 | ||
| 524 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 | ||
| 525 | |||
| 526 | /* Register r_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 527 | typedef struct { | ||
| 528 | unsigned int spu0_intr4 : 1; | ||
| 529 | unsigned int spu1_intr4 : 1; | ||
| 530 | unsigned int trigger_grp0 : 1; | ||
| 531 | unsigned int trigger_grp5 : 1; | ||
| 532 | unsigned int timer_grp0 : 1; | ||
| 533 | unsigned int fifo_in0 : 1; | ||
| 534 | unsigned int fifo_in0_extra : 1; | ||
| 535 | unsigned int dmc_out0 : 1; | ||
| 536 | unsigned int spu0_intr5 : 1; | ||
| 537 | unsigned int spu1_intr5 : 1; | ||
| 538 | unsigned int trigger_grp1 : 1; | ||
| 539 | unsigned int trigger_grp6 : 1; | ||
| 540 | unsigned int timer_grp1 : 1; | ||
| 541 | unsigned int fifo_out1 : 1; | ||
| 542 | unsigned int fifo_out0_extra : 1; | ||
| 543 | unsigned int dmc_in0 : 1; | ||
| 544 | unsigned int spu0_intr6 : 1; | ||
| 545 | unsigned int spu1_intr6 : 1; | ||
| 546 | unsigned int trigger_grp2 : 1; | ||
| 547 | unsigned int trigger_grp7 : 1; | ||
| 548 | unsigned int timer_grp2 : 1; | ||
| 549 | unsigned int fifo_in1 : 1; | ||
| 550 | unsigned int fifo_in1_extra : 1; | ||
| 551 | unsigned int dmc_out1 : 1; | ||
| 552 | unsigned int spu0_intr7 : 1; | ||
| 553 | unsigned int spu1_intr7 : 1; | ||
| 554 | unsigned int trigger_grp3 : 1; | ||
| 555 | unsigned int trigger_grp4 : 1; | ||
| 556 | unsigned int timer_grp3 : 1; | ||
| 557 | unsigned int fifo_out0 : 1; | ||
| 558 | unsigned int fifo_out1_extra : 1; | ||
| 559 | unsigned int dmc_in1 : 1; | ||
| 560 | } reg_iop_sw_mpu_r_intr_grp1; | ||
| 561 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120 | ||
| 562 | |||
| 563 | /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 564 | typedef struct { | ||
| 565 | unsigned int spu0_intr4 : 1; | ||
| 566 | unsigned int spu1_intr4 : 1; | ||
| 567 | unsigned int trigger_grp0 : 1; | ||
| 568 | unsigned int trigger_grp5 : 1; | ||
| 569 | unsigned int timer_grp0 : 1; | ||
| 570 | unsigned int fifo_in0 : 1; | ||
| 571 | unsigned int fifo_in0_extra : 1; | ||
| 572 | unsigned int dmc_out0 : 1; | ||
| 573 | unsigned int spu0_intr5 : 1; | ||
| 574 | unsigned int spu1_intr5 : 1; | ||
| 575 | unsigned int trigger_grp1 : 1; | ||
| 576 | unsigned int trigger_grp6 : 1; | ||
| 577 | unsigned int timer_grp1 : 1; | ||
| 578 | unsigned int fifo_out1 : 1; | ||
| 579 | unsigned int fifo_out0_extra : 1; | ||
| 580 | unsigned int dmc_in0 : 1; | ||
| 581 | unsigned int spu0_intr6 : 1; | ||
| 582 | unsigned int spu1_intr6 : 1; | ||
| 583 | unsigned int trigger_grp2 : 1; | ||
| 584 | unsigned int trigger_grp7 : 1; | ||
| 585 | unsigned int timer_grp2 : 1; | ||
| 586 | unsigned int fifo_in1 : 1; | ||
| 587 | unsigned int fifo_in1_extra : 1; | ||
| 588 | unsigned int dmc_out1 : 1; | ||
| 589 | unsigned int spu0_intr7 : 1; | ||
| 590 | unsigned int spu1_intr7 : 1; | ||
| 591 | unsigned int trigger_grp3 : 1; | ||
| 592 | unsigned int trigger_grp4 : 1; | ||
| 593 | unsigned int timer_grp3 : 1; | ||
| 594 | unsigned int fifo_out0 : 1; | ||
| 595 | unsigned int fifo_out1_extra : 1; | ||
| 596 | unsigned int dmc_in1 : 1; | ||
| 597 | } reg_iop_sw_mpu_r_masked_intr_grp1; | ||
| 598 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124 | ||
| 599 | |||
| 600 | /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ | ||
| 601 | typedef struct { | ||
| 602 | unsigned int spu0_intr8 : 1; | ||
| 603 | unsigned int spu1_intr8 : 1; | ||
| 604 | unsigned int trigger_grp0 : 1; | ||
| 605 | unsigned int trigger_grp6 : 1; | ||
| 606 | unsigned int timer_grp0 : 1; | ||
| 607 | unsigned int fifo_out1 : 1; | ||
| 608 | unsigned int fifo_out1_extra : 1; | ||
| 609 | unsigned int dmc_out0 : 1; | ||
| 610 | unsigned int spu0_intr9 : 1; | ||
| 611 | unsigned int spu1_intr9 : 1; | ||
| 612 | unsigned int trigger_grp1 : 1; | ||
| 613 | unsigned int trigger_grp7 : 1; | ||
| 614 | unsigned int timer_grp1 : 1; | ||
| 615 | unsigned int fifo_in1 : 1; | ||
| 616 | unsigned int fifo_in1_extra : 1; | ||
| 617 | unsigned int dmc_in0 : 1; | ||
| 618 | unsigned int spu0_intr10 : 1; | ||
| 619 | unsigned int spu1_intr10 : 1; | ||
| 620 | unsigned int trigger_grp2 : 1; | ||
| 621 | unsigned int trigger_grp4 : 1; | ||
| 622 | unsigned int timer_grp2 : 1; | ||
| 623 | unsigned int fifo_out0 : 1; | ||
| 624 | unsigned int fifo_out0_extra : 1; | ||
| 625 | unsigned int dmc_out1 : 1; | ||
| 626 | unsigned int spu0_intr11 : 1; | ||
| 627 | unsigned int spu1_intr11 : 1; | ||
| 628 | unsigned int trigger_grp3 : 1; | ||
| 629 | unsigned int trigger_grp5 : 1; | ||
| 630 | unsigned int timer_grp3 : 1; | ||
| 631 | unsigned int fifo_in0 : 1; | ||
| 632 | unsigned int fifo_in0_extra : 1; | ||
| 633 | unsigned int dmc_in1 : 1; | ||
| 634 | } reg_iop_sw_mpu_rw_intr_grp2_mask; | ||
| 635 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 | ||
| 636 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 | ||
| 637 | |||
| 638 | /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ | ||
| 639 | typedef struct { | ||
| 640 | unsigned int spu0_intr8 : 1; | ||
| 641 | unsigned int spu1_intr8 : 1; | ||
| 642 | unsigned int dummy1 : 6; | ||
| 643 | unsigned int spu0_intr9 : 1; | ||
| 644 | unsigned int spu1_intr9 : 1; | ||
| 645 | unsigned int dummy2 : 6; | ||
| 646 | unsigned int spu0_intr10 : 1; | ||
| 647 | unsigned int spu1_intr10 : 1; | ||
| 648 | unsigned int dummy3 : 6; | ||
| 649 | unsigned int spu0_intr11 : 1; | ||
| 650 | unsigned int spu1_intr11 : 1; | ||
| 651 | unsigned int dummy4 : 6; | ||
| 652 | } reg_iop_sw_mpu_rw_ack_intr_grp2; | ||
| 653 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 | ||
| 654 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 | ||
| 655 | |||
| 656 | /* Register r_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 657 | typedef struct { | ||
| 658 | unsigned int spu0_intr8 : 1; | ||
| 659 | unsigned int spu1_intr8 : 1; | ||
| 660 | unsigned int trigger_grp0 : 1; | ||
| 661 | unsigned int trigger_grp6 : 1; | ||
| 662 | unsigned int timer_grp0 : 1; | ||
| 663 | unsigned int fifo_out1 : 1; | ||
| 664 | unsigned int fifo_out1_extra : 1; | ||
| 665 | unsigned int dmc_out0 : 1; | ||
| 666 | unsigned int spu0_intr9 : 1; | ||
| 667 | unsigned int spu1_intr9 : 1; | ||
| 668 | unsigned int trigger_grp1 : 1; | ||
| 669 | unsigned int trigger_grp7 : 1; | ||
| 670 | unsigned int timer_grp1 : 1; | ||
| 671 | unsigned int fifo_in1 : 1; | ||
| 672 | unsigned int fifo_in1_extra : 1; | ||
| 673 | unsigned int dmc_in0 : 1; | ||
| 674 | unsigned int spu0_intr10 : 1; | ||
| 675 | unsigned int spu1_intr10 : 1; | ||
| 676 | unsigned int trigger_grp2 : 1; | ||
| 677 | unsigned int trigger_grp4 : 1; | ||
| 678 | unsigned int timer_grp2 : 1; | ||
| 679 | unsigned int fifo_out0 : 1; | ||
| 680 | unsigned int fifo_out0_extra : 1; | ||
| 681 | unsigned int dmc_out1 : 1; | ||
| 682 | unsigned int spu0_intr11 : 1; | ||
| 683 | unsigned int spu1_intr11 : 1; | ||
| 684 | unsigned int trigger_grp3 : 1; | ||
| 685 | unsigned int trigger_grp5 : 1; | ||
| 686 | unsigned int timer_grp3 : 1; | ||
| 687 | unsigned int fifo_in0 : 1; | ||
| 688 | unsigned int fifo_in0_extra : 1; | ||
| 689 | unsigned int dmc_in1 : 1; | ||
| 690 | } reg_iop_sw_mpu_r_intr_grp2; | ||
| 691 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136 | ||
| 692 | |||
| 693 | /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 694 | typedef struct { | ||
| 695 | unsigned int spu0_intr8 : 1; | ||
| 696 | unsigned int spu1_intr8 : 1; | ||
| 697 | unsigned int trigger_grp0 : 1; | ||
| 698 | unsigned int trigger_grp6 : 1; | ||
| 699 | unsigned int timer_grp0 : 1; | ||
| 700 | unsigned int fifo_out1 : 1; | ||
| 701 | unsigned int fifo_out1_extra : 1; | ||
| 702 | unsigned int dmc_out0 : 1; | ||
| 703 | unsigned int spu0_intr9 : 1; | ||
| 704 | unsigned int spu1_intr9 : 1; | ||
| 705 | unsigned int trigger_grp1 : 1; | ||
| 706 | unsigned int trigger_grp7 : 1; | ||
| 707 | unsigned int timer_grp1 : 1; | ||
| 708 | unsigned int fifo_in1 : 1; | ||
| 709 | unsigned int fifo_in1_extra : 1; | ||
| 710 | unsigned int dmc_in0 : 1; | ||
| 711 | unsigned int spu0_intr10 : 1; | ||
| 712 | unsigned int spu1_intr10 : 1; | ||
| 713 | unsigned int trigger_grp2 : 1; | ||
| 714 | unsigned int trigger_grp4 : 1; | ||
| 715 | unsigned int timer_grp2 : 1; | ||
| 716 | unsigned int fifo_out0 : 1; | ||
| 717 | unsigned int fifo_out0_extra : 1; | ||
| 718 | unsigned int dmc_out1 : 1; | ||
| 719 | unsigned int spu0_intr11 : 1; | ||
| 720 | unsigned int spu1_intr11 : 1; | ||
| 721 | unsigned int trigger_grp3 : 1; | ||
| 722 | unsigned int trigger_grp5 : 1; | ||
| 723 | unsigned int timer_grp3 : 1; | ||
| 724 | unsigned int fifo_in0 : 1; | ||
| 725 | unsigned int fifo_in0_extra : 1; | ||
| 726 | unsigned int dmc_in1 : 1; | ||
| 727 | } reg_iop_sw_mpu_r_masked_intr_grp2; | ||
| 728 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140 | ||
| 729 | |||
| 730 | /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ | ||
| 731 | typedef struct { | ||
| 732 | unsigned int spu0_intr12 : 1; | ||
| 733 | unsigned int spu1_intr12 : 1; | ||
| 734 | unsigned int trigger_grp0 : 1; | ||
| 735 | unsigned int trigger_grp7 : 1; | ||
| 736 | unsigned int timer_grp0 : 1; | ||
| 737 | unsigned int fifo_in1 : 1; | ||
| 738 | unsigned int fifo_in1_extra : 1; | ||
| 739 | unsigned int dmc_out0 : 1; | ||
| 740 | unsigned int spu0_intr13 : 1; | ||
| 741 | unsigned int spu1_intr13 : 1; | ||
| 742 | unsigned int trigger_grp1 : 1; | ||
| 743 | unsigned int trigger_grp4 : 1; | ||
| 744 | unsigned int timer_grp1 : 1; | ||
| 745 | unsigned int fifo_out0 : 1; | ||
| 746 | unsigned int fifo_out0_extra : 1; | ||
| 747 | unsigned int dmc_in0 : 1; | ||
| 748 | unsigned int spu0_intr14 : 1; | ||
| 749 | unsigned int spu1_intr14 : 1; | ||
| 750 | unsigned int trigger_grp2 : 1; | ||
| 751 | unsigned int trigger_grp5 : 1; | ||
| 752 | unsigned int timer_grp2 : 1; | ||
| 753 | unsigned int fifo_in0 : 1; | ||
| 754 | unsigned int fifo_in0_extra : 1; | ||
| 755 | unsigned int dmc_out1 : 1; | ||
| 756 | unsigned int spu0_intr15 : 1; | ||
| 757 | unsigned int spu1_intr15 : 1; | ||
| 758 | unsigned int trigger_grp3 : 1; | ||
| 759 | unsigned int trigger_grp6 : 1; | ||
| 760 | unsigned int timer_grp3 : 1; | ||
| 761 | unsigned int fifo_out1 : 1; | ||
| 762 | unsigned int fifo_out1_extra : 1; | ||
| 763 | unsigned int dmc_in1 : 1; | ||
| 764 | } reg_iop_sw_mpu_rw_intr_grp3_mask; | ||
| 765 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 | ||
| 766 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 | ||
| 767 | |||
| 768 | /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ | ||
| 769 | typedef struct { | ||
| 770 | unsigned int spu0_intr12 : 1; | ||
| 771 | unsigned int spu1_intr12 : 1; | ||
| 772 | unsigned int dummy1 : 6; | ||
| 773 | unsigned int spu0_intr13 : 1; | ||
| 774 | unsigned int spu1_intr13 : 1; | ||
| 775 | unsigned int dummy2 : 6; | ||
| 776 | unsigned int spu0_intr14 : 1; | ||
| 777 | unsigned int spu1_intr14 : 1; | ||
| 778 | unsigned int dummy3 : 6; | ||
| 779 | unsigned int spu0_intr15 : 1; | ||
| 780 | unsigned int spu1_intr15 : 1; | ||
| 781 | unsigned int dummy4 : 6; | ||
| 782 | } reg_iop_sw_mpu_rw_ack_intr_grp3; | ||
| 783 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 | ||
| 784 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 | ||
| 785 | |||
| 786 | /* Register r_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 787 | typedef struct { | ||
| 788 | unsigned int spu0_intr12 : 1; | ||
| 789 | unsigned int spu1_intr12 : 1; | ||
| 790 | unsigned int trigger_grp0 : 1; | ||
| 791 | unsigned int trigger_grp7 : 1; | ||
| 792 | unsigned int timer_grp0 : 1; | ||
| 793 | unsigned int fifo_in1 : 1; | ||
| 794 | unsigned int fifo_in1_extra : 1; | ||
| 795 | unsigned int dmc_out0 : 1; | ||
| 796 | unsigned int spu0_intr13 : 1; | ||
| 797 | unsigned int spu1_intr13 : 1; | ||
| 798 | unsigned int trigger_grp1 : 1; | ||
| 799 | unsigned int trigger_grp4 : 1; | ||
| 800 | unsigned int timer_grp1 : 1; | ||
| 801 | unsigned int fifo_out0 : 1; | ||
| 802 | unsigned int fifo_out0_extra : 1; | ||
| 803 | unsigned int dmc_in0 : 1; | ||
| 804 | unsigned int spu0_intr14 : 1; | ||
| 805 | unsigned int spu1_intr14 : 1; | ||
| 806 | unsigned int trigger_grp2 : 1; | ||
| 807 | unsigned int trigger_grp5 : 1; | ||
| 808 | unsigned int timer_grp2 : 1; | ||
| 809 | unsigned int fifo_in0 : 1; | ||
| 810 | unsigned int fifo_in0_extra : 1; | ||
| 811 | unsigned int dmc_out1 : 1; | ||
| 812 | unsigned int spu0_intr15 : 1; | ||
| 813 | unsigned int spu1_intr15 : 1; | ||
| 814 | unsigned int trigger_grp3 : 1; | ||
| 815 | unsigned int trigger_grp6 : 1; | ||
| 816 | unsigned int timer_grp3 : 1; | ||
| 817 | unsigned int fifo_out1 : 1; | ||
| 818 | unsigned int fifo_out1_extra : 1; | ||
| 819 | unsigned int dmc_in1 : 1; | ||
| 820 | } reg_iop_sw_mpu_r_intr_grp3; | ||
| 821 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152 | ||
| 822 | |||
| 823 | /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 824 | typedef struct { | ||
| 825 | unsigned int spu0_intr12 : 1; | ||
| 826 | unsigned int spu1_intr12 : 1; | ||
| 827 | unsigned int trigger_grp0 : 1; | ||
| 828 | unsigned int trigger_grp7 : 1; | ||
| 829 | unsigned int timer_grp0 : 1; | ||
| 830 | unsigned int fifo_in1 : 1; | ||
| 831 | unsigned int fifo_in1_extra : 1; | ||
| 832 | unsigned int dmc_out0 : 1; | ||
| 833 | unsigned int spu0_intr13 : 1; | ||
| 834 | unsigned int spu1_intr13 : 1; | ||
| 835 | unsigned int trigger_grp1 : 1; | ||
| 836 | unsigned int trigger_grp4 : 1; | ||
| 837 | unsigned int timer_grp1 : 1; | ||
| 838 | unsigned int fifo_out0 : 1; | ||
| 839 | unsigned int fifo_out0_extra : 1; | ||
| 840 | unsigned int dmc_in0 : 1; | ||
| 841 | unsigned int spu0_intr14 : 1; | ||
| 842 | unsigned int spu1_intr14 : 1; | ||
| 843 | unsigned int trigger_grp2 : 1; | ||
| 844 | unsigned int trigger_grp5 : 1; | ||
| 845 | unsigned int timer_grp2 : 1; | ||
| 846 | unsigned int fifo_in0 : 1; | ||
| 847 | unsigned int fifo_in0_extra : 1; | ||
| 848 | unsigned int dmc_out1 : 1; | ||
| 849 | unsigned int spu0_intr15 : 1; | ||
| 850 | unsigned int spu1_intr15 : 1; | ||
| 851 | unsigned int trigger_grp3 : 1; | ||
| 852 | unsigned int trigger_grp6 : 1; | ||
| 853 | unsigned int timer_grp3 : 1; | ||
| 854 | unsigned int fifo_out1 : 1; | ||
| 855 | unsigned int fifo_out1_extra : 1; | ||
| 856 | unsigned int dmc_in1 : 1; | ||
| 857 | } reg_iop_sw_mpu_r_masked_intr_grp3; | ||
| 858 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156 | ||
| 859 | |||
| 860 | |||
| 861 | /* Constants */ | ||
| 862 | enum { | ||
| 863 | regk_iop_sw_mpu_copy = 0x00000000, | ||
| 864 | regk_iop_sw_mpu_cpu = 0x00000000, | ||
| 865 | regk_iop_sw_mpu_mpu = 0x00000001, | ||
| 866 | regk_iop_sw_mpu_no = 0x00000000, | ||
| 867 | regk_iop_sw_mpu_nop = 0x00000000, | ||
| 868 | regk_iop_sw_mpu_rd = 0x00000002, | ||
| 869 | regk_iop_sw_mpu_reg_copy = 0x00000001, | ||
| 870 | regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, | ||
| 871 | regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, | ||
| 872 | regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, | ||
| 873 | regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, | ||
| 874 | regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, | ||
| 875 | regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, | ||
| 876 | regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, | ||
| 877 | regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, | ||
| 878 | regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, | ||
| 879 | regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 880 | regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 881 | regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, | ||
| 882 | regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, | ||
| 883 | regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, | ||
| 884 | regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, | ||
| 885 | regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, | ||
| 886 | regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, | ||
| 887 | regk_iop_sw_mpu_set = 0x00000001, | ||
| 888 | regk_iop_sw_mpu_spu0 = 0x00000002, | ||
| 889 | regk_iop_sw_mpu_spu1 = 0x00000003, | ||
| 890 | regk_iop_sw_mpu_wr = 0x00000003, | ||
| 891 | regk_iop_sw_mpu_yes = 0x00000001 | ||
| 892 | }; | ||
| 893 | #endif /* __iop_sw_mpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index b59dde4bd0d1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null | |||
| @@ -1,552 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_spu_defs_h | ||
| 2 | #define __iop_sw_spu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:10:19 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r | ||
| 11 | * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_sw_spu */ | ||
| 86 | |||
| 87 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int keep_owner : 1; | ||
| 90 | unsigned int cmd : 2; | ||
| 91 | unsigned int size : 3; | ||
| 92 | unsigned int wr_spu0_mem : 1; | ||
| 93 | unsigned int wr_spu1_mem : 1; | ||
| 94 | unsigned int dummy1 : 24; | ||
| 95 | } reg_iop_sw_spu_rw_mc_ctrl; | ||
| 96 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 | ||
| 97 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 | ||
| 98 | |||
| 99 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | ||
| 100 | typedef struct { | ||
| 101 | unsigned int val : 32; | ||
| 102 | } reg_iop_sw_spu_rw_mc_data; | ||
| 103 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 | ||
| 104 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 | ||
| 105 | |||
| 106 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | ||
| 107 | typedef unsigned int reg_iop_sw_spu_rw_mc_addr; | ||
| 108 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 | ||
| 109 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 | ||
| 110 | |||
| 111 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | ||
| 112 | typedef unsigned int reg_iop_sw_spu_rs_mc_data; | ||
| 113 | #define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 | ||
| 114 | |||
| 115 | /* Register r_mc_data, scope iop_sw_spu, type r */ | ||
| 116 | typedef unsigned int reg_iop_sw_spu_r_mc_data; | ||
| 117 | #define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 | ||
| 118 | |||
| 119 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | ||
| 120 | typedef struct { | ||
| 121 | unsigned int busy_cpu : 1; | ||
| 122 | unsigned int busy_mpu : 1; | ||
| 123 | unsigned int busy_spu0 : 1; | ||
| 124 | unsigned int busy_spu1 : 1; | ||
| 125 | unsigned int owned_by_cpu : 1; | ||
| 126 | unsigned int owned_by_mpu : 1; | ||
| 127 | unsigned int owned_by_spu0 : 1; | ||
| 128 | unsigned int owned_by_spu1 : 1; | ||
| 129 | unsigned int dummy1 : 24; | ||
| 130 | } reg_iop_sw_spu_r_mc_stat; | ||
| 131 | #define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 | ||
| 132 | |||
| 133 | /* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ | ||
| 134 | typedef struct { | ||
| 135 | unsigned int byte0 : 8; | ||
| 136 | unsigned int byte1 : 8; | ||
| 137 | unsigned int byte2 : 8; | ||
| 138 | unsigned int byte3 : 8; | ||
| 139 | } reg_iop_sw_spu_rw_bus0_clr_mask; | ||
| 140 | #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 | ||
| 141 | #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 | ||
| 142 | |||
| 143 | /* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ | ||
| 144 | typedef struct { | ||
| 145 | unsigned int byte0 : 8; | ||
| 146 | unsigned int byte1 : 8; | ||
| 147 | unsigned int byte2 : 8; | ||
| 148 | unsigned int byte3 : 8; | ||
| 149 | } reg_iop_sw_spu_rw_bus0_set_mask; | ||
| 150 | #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 | ||
| 151 | #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 | ||
| 152 | |||
| 153 | /* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int byte0 : 1; | ||
| 156 | unsigned int byte1 : 1; | ||
| 157 | unsigned int byte2 : 1; | ||
| 158 | unsigned int byte3 : 1; | ||
| 159 | unsigned int dummy1 : 28; | ||
| 160 | } reg_iop_sw_spu_rw_bus0_oe_clr_mask; | ||
| 161 | #define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 | ||
| 162 | #define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 | ||
| 163 | |||
| 164 | /* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 165 | typedef struct { | ||
| 166 | unsigned int byte0 : 1; | ||
| 167 | unsigned int byte1 : 1; | ||
| 168 | unsigned int byte2 : 1; | ||
| 169 | unsigned int byte3 : 1; | ||
| 170 | unsigned int dummy1 : 28; | ||
| 171 | } reg_iop_sw_spu_rw_bus0_oe_set_mask; | ||
| 172 | #define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 | ||
| 173 | #define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 | ||
| 174 | |||
| 175 | /* Register r_bus0_in, scope iop_sw_spu, type r */ | ||
| 176 | typedef unsigned int reg_iop_sw_spu_r_bus0_in; | ||
| 177 | #define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 | ||
| 178 | |||
| 179 | /* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ | ||
| 180 | typedef struct { | ||
| 181 | unsigned int byte0 : 8; | ||
| 182 | unsigned int byte1 : 8; | ||
| 183 | unsigned int byte2 : 8; | ||
| 184 | unsigned int byte3 : 8; | ||
| 185 | } reg_iop_sw_spu_rw_bus1_clr_mask; | ||
| 186 | #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 | ||
| 187 | #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 | ||
| 188 | |||
| 189 | /* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ | ||
| 190 | typedef struct { | ||
| 191 | unsigned int byte0 : 8; | ||
| 192 | unsigned int byte1 : 8; | ||
| 193 | unsigned int byte2 : 8; | ||
| 194 | unsigned int byte3 : 8; | ||
| 195 | } reg_iop_sw_spu_rw_bus1_set_mask; | ||
| 196 | #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 | ||
| 197 | #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 | ||
| 198 | |||
| 199 | /* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 200 | typedef struct { | ||
| 201 | unsigned int byte0 : 1; | ||
| 202 | unsigned int byte1 : 1; | ||
| 203 | unsigned int byte2 : 1; | ||
| 204 | unsigned int byte3 : 1; | ||
| 205 | unsigned int dummy1 : 28; | ||
| 206 | } reg_iop_sw_spu_rw_bus1_oe_clr_mask; | ||
| 207 | #define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 | ||
| 208 | #define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 | ||
| 209 | |||
| 210 | /* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 211 | typedef struct { | ||
| 212 | unsigned int byte0 : 1; | ||
| 213 | unsigned int byte1 : 1; | ||
| 214 | unsigned int byte2 : 1; | ||
| 215 | unsigned int byte3 : 1; | ||
| 216 | unsigned int dummy1 : 28; | ||
| 217 | } reg_iop_sw_spu_rw_bus1_oe_set_mask; | ||
| 218 | #define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 | ||
| 219 | #define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 | ||
| 220 | |||
| 221 | /* Register r_bus1_in, scope iop_sw_spu, type r */ | ||
| 222 | typedef unsigned int reg_iop_sw_spu_r_bus1_in; | ||
| 223 | #define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 | ||
| 224 | |||
| 225 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | ||
| 226 | typedef struct { | ||
| 227 | unsigned int val : 32; | ||
| 228 | } reg_iop_sw_spu_rw_gio_clr_mask; | ||
| 229 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 | ||
| 230 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 | ||
| 231 | |||
| 232 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | ||
| 233 | typedef struct { | ||
| 234 | unsigned int val : 32; | ||
| 235 | } reg_iop_sw_spu_rw_gio_set_mask; | ||
| 236 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 | ||
| 237 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 | ||
| 238 | |||
| 239 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 240 | typedef struct { | ||
| 241 | unsigned int val : 32; | ||
| 242 | } reg_iop_sw_spu_rw_gio_oe_clr_mask; | ||
| 243 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 | ||
| 244 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 | ||
| 245 | |||
| 246 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 247 | typedef struct { | ||
| 248 | unsigned int val : 32; | ||
| 249 | } reg_iop_sw_spu_rw_gio_oe_set_mask; | ||
| 250 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 | ||
| 251 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 | ||
| 252 | |||
| 253 | /* Register r_gio_in, scope iop_sw_spu, type r */ | ||
| 254 | typedef unsigned int reg_iop_sw_spu_r_gio_in; | ||
| 255 | #define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 | ||
| 256 | |||
| 257 | /* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 258 | typedef struct { | ||
| 259 | unsigned int byte0 : 8; | ||
| 260 | unsigned int byte1 : 8; | ||
| 261 | unsigned int dummy1 : 16; | ||
| 262 | } reg_iop_sw_spu_rw_bus0_clr_mask_lo; | ||
| 263 | #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 | ||
| 264 | #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 | ||
| 265 | |||
| 266 | /* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 267 | typedef struct { | ||
| 268 | unsigned int byte2 : 8; | ||
| 269 | unsigned int byte3 : 8; | ||
| 270 | unsigned int dummy1 : 16; | ||
| 271 | } reg_iop_sw_spu_rw_bus0_clr_mask_hi; | ||
| 272 | #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 | ||
| 273 | #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 | ||
| 274 | |||
| 275 | /* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 276 | typedef struct { | ||
| 277 | unsigned int byte0 : 8; | ||
| 278 | unsigned int byte1 : 8; | ||
| 279 | unsigned int dummy1 : 16; | ||
| 280 | } reg_iop_sw_spu_rw_bus0_set_mask_lo; | ||
| 281 | #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 | ||
| 282 | #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 | ||
| 283 | |||
| 284 | /* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 285 | typedef struct { | ||
| 286 | unsigned int byte2 : 8; | ||
| 287 | unsigned int byte3 : 8; | ||
| 288 | unsigned int dummy1 : 16; | ||
| 289 | } reg_iop_sw_spu_rw_bus0_set_mask_hi; | ||
| 290 | #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 | ||
| 291 | #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 | ||
| 292 | |||
| 293 | /* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 294 | typedef struct { | ||
| 295 | unsigned int byte0 : 8; | ||
| 296 | unsigned int byte1 : 8; | ||
| 297 | unsigned int dummy1 : 16; | ||
| 298 | } reg_iop_sw_spu_rw_bus1_clr_mask_lo; | ||
| 299 | #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 | ||
| 300 | #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 | ||
| 301 | |||
| 302 | /* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 303 | typedef struct { | ||
| 304 | unsigned int byte2 : 8; | ||
| 305 | unsigned int byte3 : 8; | ||
| 306 | unsigned int dummy1 : 16; | ||
| 307 | } reg_iop_sw_spu_rw_bus1_clr_mask_hi; | ||
| 308 | #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 | ||
| 309 | #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 | ||
| 310 | |||
| 311 | /* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 312 | typedef struct { | ||
| 313 | unsigned int byte0 : 8; | ||
| 314 | unsigned int byte1 : 8; | ||
| 315 | unsigned int dummy1 : 16; | ||
| 316 | } reg_iop_sw_spu_rw_bus1_set_mask_lo; | ||
| 317 | #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 | ||
| 318 | #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 | ||
| 319 | |||
| 320 | /* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 321 | typedef struct { | ||
| 322 | unsigned int byte2 : 8; | ||
| 323 | unsigned int byte3 : 8; | ||
| 324 | unsigned int dummy1 : 16; | ||
| 325 | } reg_iop_sw_spu_rw_bus1_set_mask_hi; | ||
| 326 | #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 | ||
| 327 | #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 | ||
| 328 | |||
| 329 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 330 | typedef struct { | ||
| 331 | unsigned int val : 16; | ||
| 332 | unsigned int dummy1 : 16; | ||
| 333 | } reg_iop_sw_spu_rw_gio_clr_mask_lo; | ||
| 334 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 | ||
| 335 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 | ||
| 336 | |||
| 337 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 338 | typedef struct { | ||
| 339 | unsigned int val : 16; | ||
| 340 | unsigned int dummy1 : 16; | ||
| 341 | } reg_iop_sw_spu_rw_gio_clr_mask_hi; | ||
| 342 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 | ||
| 343 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 | ||
| 344 | |||
| 345 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 346 | typedef struct { | ||
| 347 | unsigned int val : 16; | ||
| 348 | unsigned int dummy1 : 16; | ||
| 349 | } reg_iop_sw_spu_rw_gio_set_mask_lo; | ||
| 350 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 | ||
| 351 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 | ||
| 352 | |||
| 353 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 354 | typedef struct { | ||
| 355 | unsigned int val : 16; | ||
| 356 | unsigned int dummy1 : 16; | ||
| 357 | } reg_iop_sw_spu_rw_gio_set_mask_hi; | ||
| 358 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 | ||
| 359 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 | ||
| 360 | |||
| 361 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 362 | typedef struct { | ||
| 363 | unsigned int val : 16; | ||
| 364 | unsigned int dummy1 : 16; | ||
| 365 | } reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; | ||
| 366 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 | ||
| 367 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 | ||
| 368 | |||
| 369 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 370 | typedef struct { | ||
| 371 | unsigned int val : 16; | ||
| 372 | unsigned int dummy1 : 16; | ||
| 373 | } reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; | ||
| 374 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 | ||
| 375 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 | ||
| 376 | |||
| 377 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 378 | typedef struct { | ||
| 379 | unsigned int val : 16; | ||
| 380 | unsigned int dummy1 : 16; | ||
| 381 | } reg_iop_sw_spu_rw_gio_oe_set_mask_lo; | ||
| 382 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 | ||
| 383 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 | ||
| 384 | |||
| 385 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 386 | typedef struct { | ||
| 387 | unsigned int val : 16; | ||
| 388 | unsigned int dummy1 : 16; | ||
| 389 | } reg_iop_sw_spu_rw_gio_oe_set_mask_hi; | ||
| 390 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 | ||
| 391 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 | ||
| 392 | |||
| 393 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | ||
| 394 | typedef struct { | ||
| 395 | unsigned int intr0 : 1; | ||
| 396 | unsigned int intr1 : 1; | ||
| 397 | unsigned int intr2 : 1; | ||
| 398 | unsigned int intr3 : 1; | ||
| 399 | unsigned int intr4 : 1; | ||
| 400 | unsigned int intr5 : 1; | ||
| 401 | unsigned int intr6 : 1; | ||
| 402 | unsigned int intr7 : 1; | ||
| 403 | unsigned int intr8 : 1; | ||
| 404 | unsigned int intr9 : 1; | ||
| 405 | unsigned int intr10 : 1; | ||
| 406 | unsigned int intr11 : 1; | ||
| 407 | unsigned int intr12 : 1; | ||
| 408 | unsigned int intr13 : 1; | ||
| 409 | unsigned int intr14 : 1; | ||
| 410 | unsigned int intr15 : 1; | ||
| 411 | unsigned int dummy1 : 16; | ||
| 412 | } reg_iop_sw_spu_rw_cpu_intr; | ||
| 413 | #define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 | ||
| 414 | #define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 | ||
| 415 | |||
| 416 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | ||
| 417 | typedef struct { | ||
| 418 | unsigned int intr0 : 1; | ||
| 419 | unsigned int intr1 : 1; | ||
| 420 | unsigned int intr2 : 1; | ||
| 421 | unsigned int intr3 : 1; | ||
| 422 | unsigned int intr4 : 1; | ||
| 423 | unsigned int intr5 : 1; | ||
| 424 | unsigned int intr6 : 1; | ||
| 425 | unsigned int intr7 : 1; | ||
| 426 | unsigned int intr8 : 1; | ||
| 427 | unsigned int intr9 : 1; | ||
| 428 | unsigned int intr10 : 1; | ||
| 429 | unsigned int intr11 : 1; | ||
| 430 | unsigned int intr12 : 1; | ||
| 431 | unsigned int intr13 : 1; | ||
| 432 | unsigned int intr14 : 1; | ||
| 433 | unsigned int intr15 : 1; | ||
| 434 | unsigned int dummy1 : 16; | ||
| 435 | } reg_iop_sw_spu_r_cpu_intr; | ||
| 436 | #define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 | ||
| 437 | |||
| 438 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | ||
| 439 | typedef struct { | ||
| 440 | unsigned int trigger_grp0 : 1; | ||
| 441 | unsigned int trigger_grp1 : 1; | ||
| 442 | unsigned int trigger_grp2 : 1; | ||
| 443 | unsigned int trigger_grp3 : 1; | ||
| 444 | unsigned int trigger_grp4 : 1; | ||
| 445 | unsigned int trigger_grp5 : 1; | ||
| 446 | unsigned int trigger_grp6 : 1; | ||
| 447 | unsigned int trigger_grp7 : 1; | ||
| 448 | unsigned int timer_grp0 : 1; | ||
| 449 | unsigned int timer_grp1 : 1; | ||
| 450 | unsigned int timer_grp2 : 1; | ||
| 451 | unsigned int timer_grp3 : 1; | ||
| 452 | unsigned int fifo_out0 : 1; | ||
| 453 | unsigned int fifo_out0_extra : 1; | ||
| 454 | unsigned int fifo_in0 : 1; | ||
| 455 | unsigned int fifo_in0_extra : 1; | ||
| 456 | unsigned int fifo_out1 : 1; | ||
| 457 | unsigned int fifo_out1_extra : 1; | ||
| 458 | unsigned int fifo_in1 : 1; | ||
| 459 | unsigned int fifo_in1_extra : 1; | ||
| 460 | unsigned int dmc_out0 : 1; | ||
| 461 | unsigned int dmc_in0 : 1; | ||
| 462 | unsigned int dmc_out1 : 1; | ||
| 463 | unsigned int dmc_in1 : 1; | ||
| 464 | unsigned int dummy1 : 8; | ||
| 465 | } reg_iop_sw_spu_r_hw_intr; | ||
| 466 | #define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 | ||
| 467 | |||
| 468 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | ||
| 469 | typedef struct { | ||
| 470 | unsigned int intr0 : 1; | ||
| 471 | unsigned int intr1 : 1; | ||
| 472 | unsigned int intr2 : 1; | ||
| 473 | unsigned int intr3 : 1; | ||
| 474 | unsigned int intr4 : 1; | ||
| 475 | unsigned int intr5 : 1; | ||
| 476 | unsigned int intr6 : 1; | ||
| 477 | unsigned int intr7 : 1; | ||
| 478 | unsigned int intr8 : 1; | ||
| 479 | unsigned int intr9 : 1; | ||
| 480 | unsigned int intr10 : 1; | ||
| 481 | unsigned int intr11 : 1; | ||
| 482 | unsigned int intr12 : 1; | ||
| 483 | unsigned int intr13 : 1; | ||
| 484 | unsigned int intr14 : 1; | ||
| 485 | unsigned int intr15 : 1; | ||
| 486 | unsigned int dummy1 : 16; | ||
| 487 | } reg_iop_sw_spu_rw_mpu_intr; | ||
| 488 | #define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 | ||
| 489 | #define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 | ||
| 490 | |||
| 491 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | ||
| 492 | typedef struct { | ||
| 493 | unsigned int intr0 : 1; | ||
| 494 | unsigned int intr1 : 1; | ||
| 495 | unsigned int intr2 : 1; | ||
| 496 | unsigned int intr3 : 1; | ||
| 497 | unsigned int intr4 : 1; | ||
| 498 | unsigned int intr5 : 1; | ||
| 499 | unsigned int intr6 : 1; | ||
| 500 | unsigned int intr7 : 1; | ||
| 501 | unsigned int intr8 : 1; | ||
| 502 | unsigned int intr9 : 1; | ||
| 503 | unsigned int intr10 : 1; | ||
| 504 | unsigned int intr11 : 1; | ||
| 505 | unsigned int intr12 : 1; | ||
| 506 | unsigned int intr13 : 1; | ||
| 507 | unsigned int intr14 : 1; | ||
| 508 | unsigned int intr15 : 1; | ||
| 509 | unsigned int other_spu_intr0 : 1; | ||
| 510 | unsigned int other_spu_intr1 : 1; | ||
| 511 | unsigned int other_spu_intr2 : 1; | ||
| 512 | unsigned int other_spu_intr3 : 1; | ||
| 513 | unsigned int other_spu_intr4 : 1; | ||
| 514 | unsigned int other_spu_intr5 : 1; | ||
| 515 | unsigned int other_spu_intr6 : 1; | ||
| 516 | unsigned int other_spu_intr7 : 1; | ||
| 517 | unsigned int other_spu_intr8 : 1; | ||
| 518 | unsigned int other_spu_intr9 : 1; | ||
| 519 | unsigned int other_spu_intr10 : 1; | ||
| 520 | unsigned int other_spu_intr11 : 1; | ||
| 521 | unsigned int other_spu_intr12 : 1; | ||
| 522 | unsigned int other_spu_intr13 : 1; | ||
| 523 | unsigned int other_spu_intr14 : 1; | ||
| 524 | unsigned int other_spu_intr15 : 1; | ||
| 525 | } reg_iop_sw_spu_r_mpu_intr; | ||
| 526 | #define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 | ||
| 527 | |||
| 528 | |||
| 529 | /* Constants */ | ||
| 530 | enum { | ||
| 531 | regk_iop_sw_spu_copy = 0x00000000, | ||
| 532 | regk_iop_sw_spu_no = 0x00000000, | ||
| 533 | regk_iop_sw_spu_nop = 0x00000000, | ||
| 534 | regk_iop_sw_spu_rd = 0x00000002, | ||
| 535 | regk_iop_sw_spu_reg_copy = 0x00000001, | ||
| 536 | regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, | ||
| 537 | regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, | ||
| 538 | regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, | ||
| 539 | regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, | ||
| 540 | regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, | ||
| 541 | regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, | ||
| 542 | regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, | ||
| 543 | regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, | ||
| 544 | regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, | ||
| 545 | regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 546 | regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 547 | regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, | ||
| 548 | regk_iop_sw_spu_set = 0x00000001, | ||
| 549 | regk_iop_sw_spu_wr = 0x00000003, | ||
| 550 | regk_iop_sw_spu_yes = 0x00000001 | ||
| 551 | }; | ||
| 552 | #endif /* __iop_sw_spu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h deleted file mode 100644 index c994114f3b51..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h +++ /dev/null | |||
| @@ -1,249 +0,0 @@ | |||
| 1 | #ifndef __iop_timer_grp_defs_h | ||
| 2 | #define __iop_timer_grp_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_timer_grp.r | ||
| 7 | * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r | ||
| 11 | * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_timer_grp */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope iop_timer_grp, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int clk_src : 1; | ||
| 90 | unsigned int trig : 2; | ||
| 91 | unsigned int clk_gen_div : 8; | ||
| 92 | unsigned int clk_div : 8; | ||
| 93 | unsigned int dummy1 : 13; | ||
| 94 | } reg_iop_timer_grp_rw_cfg; | ||
| 95 | #define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 | ||
| 96 | #define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 | ||
| 97 | |||
| 98 | /* Register rw_half_period, scope iop_timer_grp, type rw */ | ||
| 99 | typedef struct { | ||
| 100 | unsigned int quota_lo : 15; | ||
| 101 | unsigned int quota_hi : 15; | ||
| 102 | unsigned int quota_hi_sel : 1; | ||
| 103 | unsigned int dummy1 : 1; | ||
| 104 | } reg_iop_timer_grp_rw_half_period; | ||
| 105 | #define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 | ||
| 106 | #define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 | ||
| 107 | |||
| 108 | /* Register rw_half_period_len, scope iop_timer_grp, type rw */ | ||
| 109 | typedef unsigned int reg_iop_timer_grp_rw_half_period_len; | ||
| 110 | #define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 | ||
| 111 | #define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 | ||
| 112 | |||
| 113 | #define STRIDE_iop_timer_grp_rw_tmr_cfg 4 | ||
| 114 | /* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int clk_src : 3; | ||
| 117 | unsigned int strb : 2; | ||
| 118 | unsigned int run_mode : 2; | ||
| 119 | unsigned int out_mode : 1; | ||
| 120 | unsigned int active_on_tmr : 2; | ||
| 121 | unsigned int inv : 1; | ||
| 122 | unsigned int en_by_tmr : 2; | ||
| 123 | unsigned int dis_by_tmr : 2; | ||
| 124 | unsigned int en_only_by_reg : 1; | ||
| 125 | unsigned int dis_only_by_reg : 1; | ||
| 126 | unsigned int rst_at_en_strb : 1; | ||
| 127 | unsigned int dummy1 : 14; | ||
| 128 | } reg_iop_timer_grp_rw_tmr_cfg; | ||
| 129 | #define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 | ||
| 130 | #define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 | ||
| 131 | |||
| 132 | #define STRIDE_iop_timer_grp_rw_tmr_len 4 | ||
| 133 | /* Register rw_tmr_len, scope iop_timer_grp, type rw */ | ||
| 134 | typedef struct { | ||
| 135 | unsigned int val : 16; | ||
| 136 | unsigned int dummy1 : 16; | ||
| 137 | } reg_iop_timer_grp_rw_tmr_len; | ||
| 138 | #define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 | ||
| 139 | #define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 | ||
| 140 | |||
| 141 | /* Register rw_cmd, scope iop_timer_grp, type rw */ | ||
| 142 | typedef struct { | ||
| 143 | unsigned int rst : 4; | ||
| 144 | unsigned int en : 4; | ||
| 145 | unsigned int dis : 4; | ||
| 146 | unsigned int strb : 4; | ||
| 147 | unsigned int dummy1 : 16; | ||
| 148 | } reg_iop_timer_grp_rw_cmd; | ||
| 149 | #define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 | ||
| 150 | #define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 | ||
| 151 | |||
| 152 | /* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ | ||
| 153 | typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; | ||
| 154 | #define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 | ||
| 155 | |||
| 156 | #define STRIDE_iop_timer_grp_rs_tmr_cnt 8 | ||
| 157 | /* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ | ||
| 158 | typedef struct { | ||
| 159 | unsigned int val : 16; | ||
| 160 | unsigned int dummy1 : 16; | ||
| 161 | } reg_iop_timer_grp_rs_tmr_cnt; | ||
| 162 | #define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 | ||
| 163 | |||
| 164 | #define STRIDE_iop_timer_grp_r_tmr_cnt 8 | ||
| 165 | /* Register r_tmr_cnt, scope iop_timer_grp, type r */ | ||
| 166 | typedef struct { | ||
| 167 | unsigned int val : 16; | ||
| 168 | unsigned int dummy1 : 16; | ||
| 169 | } reg_iop_timer_grp_r_tmr_cnt; | ||
| 170 | #define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 | ||
| 171 | |||
| 172 | /* Register rw_intr_mask, scope iop_timer_grp, type rw */ | ||
| 173 | typedef struct { | ||
| 174 | unsigned int tmr0 : 1; | ||
| 175 | unsigned int tmr1 : 1; | ||
| 176 | unsigned int tmr2 : 1; | ||
| 177 | unsigned int tmr3 : 1; | ||
| 178 | unsigned int dummy1 : 28; | ||
| 179 | } reg_iop_timer_grp_rw_intr_mask; | ||
| 180 | #define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 | ||
| 181 | #define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 | ||
| 182 | |||
| 183 | /* Register rw_ack_intr, scope iop_timer_grp, type rw */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int tmr0 : 1; | ||
| 186 | unsigned int tmr1 : 1; | ||
| 187 | unsigned int tmr2 : 1; | ||
| 188 | unsigned int tmr3 : 1; | ||
| 189 | unsigned int dummy1 : 28; | ||
| 190 | } reg_iop_timer_grp_rw_ack_intr; | ||
| 191 | #define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 | ||
| 192 | #define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 | ||
| 193 | |||
| 194 | /* Register r_intr, scope iop_timer_grp, type r */ | ||
| 195 | typedef struct { | ||
| 196 | unsigned int tmr0 : 1; | ||
| 197 | unsigned int tmr1 : 1; | ||
| 198 | unsigned int tmr2 : 1; | ||
| 199 | unsigned int tmr3 : 1; | ||
| 200 | unsigned int dummy1 : 28; | ||
| 201 | } reg_iop_timer_grp_r_intr; | ||
| 202 | #define REG_RD_ADDR_iop_timer_grp_r_intr 108 | ||
| 203 | |||
| 204 | /* Register r_masked_intr, scope iop_timer_grp, type r */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int tmr0 : 1; | ||
| 207 | unsigned int tmr1 : 1; | ||
| 208 | unsigned int tmr2 : 1; | ||
| 209 | unsigned int tmr3 : 1; | ||
| 210 | unsigned int dummy1 : 28; | ||
| 211 | } reg_iop_timer_grp_r_masked_intr; | ||
| 212 | #define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 | ||
| 213 | |||
| 214 | |||
| 215 | /* Constants */ | ||
| 216 | enum { | ||
| 217 | regk_iop_timer_grp_clk200 = 0x00000000, | ||
| 218 | regk_iop_timer_grp_clk_gen = 0x00000002, | ||
| 219 | regk_iop_timer_grp_complete = 0x00000002, | ||
| 220 | regk_iop_timer_grp_div_clk200 = 0x00000001, | ||
| 221 | regk_iop_timer_grp_div_clk_gen = 0x00000003, | ||
| 222 | regk_iop_timer_grp_ext = 0x00000001, | ||
| 223 | regk_iop_timer_grp_hi = 0x00000000, | ||
| 224 | regk_iop_timer_grp_long_period = 0x00000001, | ||
| 225 | regk_iop_timer_grp_neg = 0x00000002, | ||
| 226 | regk_iop_timer_grp_no = 0x00000000, | ||
| 227 | regk_iop_timer_grp_once = 0x00000003, | ||
| 228 | regk_iop_timer_grp_pause = 0x00000001, | ||
| 229 | regk_iop_timer_grp_pos = 0x00000001, | ||
| 230 | regk_iop_timer_grp_pos_neg = 0x00000003, | ||
| 231 | regk_iop_timer_grp_pulse = 0x00000000, | ||
| 232 | regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, | ||
| 233 | regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, | ||
| 234 | regk_iop_timer_grp_rw_cfg_default = 0x00000002, | ||
| 235 | regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, | ||
| 236 | regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, | ||
| 237 | regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, | ||
| 238 | regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, | ||
| 239 | regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, | ||
| 240 | regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, | ||
| 241 | regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, | ||
| 242 | regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, | ||
| 243 | regk_iop_timer_grp_short_period = 0x00000000, | ||
| 244 | regk_iop_timer_grp_stop = 0x00000000, | ||
| 245 | regk_iop_timer_grp_tmr = 0x00000004, | ||
| 246 | regk_iop_timer_grp_toggle = 0x00000001, | ||
| 247 | regk_iop_timer_grp_yes = 0x00000001 | ||
| 248 | }; | ||
| 249 | #endif /* __iop_timer_grp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h deleted file mode 100644 index 36e44282399d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h +++ /dev/null | |||
| @@ -1,170 +0,0 @@ | |||
| 1 | #ifndef __iop_trigger_grp_defs_h | ||
| 2 | #define __iop_trigger_grp_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/iop_trigger_grp.r | ||
| 7 | * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:46 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r | ||
| 11 | * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_trigger_grp */ | ||
| 86 | |||
| 87 | #define STRIDE_iop_trigger_grp_rw_cfg 4 | ||
| 88 | /* Register rw_cfg, scope iop_trigger_grp, type rw */ | ||
| 89 | typedef struct { | ||
| 90 | unsigned int action : 2; | ||
| 91 | unsigned int once : 1; | ||
| 92 | unsigned int trig : 3; | ||
| 93 | unsigned int en_only_by_reg : 1; | ||
| 94 | unsigned int dis_only_by_reg : 1; | ||
| 95 | unsigned int dummy1 : 24; | ||
| 96 | } reg_iop_trigger_grp_rw_cfg; | ||
| 97 | #define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 | ||
| 98 | #define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 | ||
| 99 | |||
| 100 | /* Register rw_cmd, scope iop_trigger_grp, type rw */ | ||
| 101 | typedef struct { | ||
| 102 | unsigned int dis : 4; | ||
| 103 | unsigned int en : 4; | ||
| 104 | unsigned int dummy1 : 24; | ||
| 105 | } reg_iop_trigger_grp_rw_cmd; | ||
| 106 | #define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 | ||
| 107 | #define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 | ||
| 108 | |||
| 109 | /* Register rw_intr_mask, scope iop_trigger_grp, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int trig0 : 1; | ||
| 112 | unsigned int trig1 : 1; | ||
| 113 | unsigned int trig2 : 1; | ||
| 114 | unsigned int trig3 : 1; | ||
| 115 | unsigned int dummy1 : 28; | ||
| 116 | } reg_iop_trigger_grp_rw_intr_mask; | ||
| 117 | #define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 | ||
| 118 | #define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 | ||
| 119 | |||
| 120 | /* Register rw_ack_intr, scope iop_trigger_grp, type rw */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int trig0 : 1; | ||
| 123 | unsigned int trig1 : 1; | ||
| 124 | unsigned int trig2 : 1; | ||
| 125 | unsigned int trig3 : 1; | ||
| 126 | unsigned int dummy1 : 28; | ||
| 127 | } reg_iop_trigger_grp_rw_ack_intr; | ||
| 128 | #define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 | ||
| 129 | #define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 | ||
| 130 | |||
| 131 | /* Register r_intr, scope iop_trigger_grp, type r */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int trig0 : 1; | ||
| 134 | unsigned int trig1 : 1; | ||
| 135 | unsigned int trig2 : 1; | ||
| 136 | unsigned int trig3 : 1; | ||
| 137 | unsigned int dummy1 : 28; | ||
| 138 | } reg_iop_trigger_grp_r_intr; | ||
| 139 | #define REG_RD_ADDR_iop_trigger_grp_r_intr 28 | ||
| 140 | |||
| 141 | /* Register r_masked_intr, scope iop_trigger_grp, type r */ | ||
| 142 | typedef struct { | ||
| 143 | unsigned int trig0 : 1; | ||
| 144 | unsigned int trig1 : 1; | ||
| 145 | unsigned int trig2 : 1; | ||
| 146 | unsigned int trig3 : 1; | ||
| 147 | unsigned int dummy1 : 28; | ||
| 148 | } reg_iop_trigger_grp_r_masked_intr; | ||
| 149 | #define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 | ||
| 150 | |||
| 151 | |||
| 152 | /* Constants */ | ||
| 153 | enum { | ||
| 154 | regk_iop_trigger_grp_fall = 0x00000002, | ||
| 155 | regk_iop_trigger_grp_fall_lo = 0x00000006, | ||
| 156 | regk_iop_trigger_grp_no = 0x00000000, | ||
| 157 | regk_iop_trigger_grp_off = 0x00000000, | ||
| 158 | regk_iop_trigger_grp_pulse = 0x00000000, | ||
| 159 | regk_iop_trigger_grp_rise = 0x00000001, | ||
| 160 | regk_iop_trigger_grp_rise_fall = 0x00000003, | ||
| 161 | regk_iop_trigger_grp_rise_fall_hi = 0x00000007, | ||
| 162 | regk_iop_trigger_grp_rise_fall_lo = 0x00000004, | ||
| 163 | regk_iop_trigger_grp_rise_hi = 0x00000005, | ||
| 164 | regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, | ||
| 165 | regk_iop_trigger_grp_rw_cfg_size = 0x00000004, | ||
| 166 | regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, | ||
| 167 | regk_iop_trigger_grp_toggle = 0x00000003, | ||
| 168 | regk_iop_trigger_grp_yes = 0x00000001 | ||
| 169 | }; | ||
| 170 | #endif /* __iop_trigger_grp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h deleted file mode 100644 index b8d6a910c71c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h +++ /dev/null | |||
| @@ -1,99 +0,0 @@ | |||
| 1 | #ifndef __iop_version_defs_h | ||
| 2 | #define __iop_version_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/io_proc/rtl/guinness/iop_version.r | ||
| 7 | * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:44 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r | ||
| 11 | * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope iop_version */ | ||
| 86 | |||
| 87 | /* Register r_version, scope iop_version, type r */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int nr : 8; | ||
| 90 | unsigned int dummy1 : 24; | ||
| 91 | } reg_iop_version_r_version; | ||
| 92 | #define REG_RD_ADDR_iop_version_r_version 0 | ||
| 93 | |||
| 94 | |||
| 95 | /* Constants */ | ||
| 96 | enum { | ||
| 97 | regk_iop_version_v1_0 = 0x00000001 | ||
| 98 | }; | ||
| 99 | #endif /* __iop_version_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h deleted file mode 100644 index 7b167e3c0572..000000000000 --- a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h +++ /dev/null | |||
| @@ -1,104 +0,0 @@ | |||
| 1 | #ifndef __irq_nmi_defs_h | ||
| 2 | #define __irq_nmi_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../mod/irq_nmi.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Thu Jan 22 09:22:43 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r | ||
| 11 | * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope irq_nmi */ | ||
| 86 | |||
| 87 | /* Register rw_cmd, scope irq_nmi, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int delay : 16; | ||
| 90 | unsigned int op : 2; | ||
| 91 | unsigned int dummy1 : 14; | ||
| 92 | } reg_irq_nmi_rw_cmd; | ||
| 93 | #define REG_RD_ADDR_irq_nmi_rw_cmd 0 | ||
| 94 | #define REG_WR_ADDR_irq_nmi_rw_cmd 0 | ||
| 95 | |||
| 96 | |||
| 97 | /* Constants */ | ||
| 98 | enum { | ||
| 99 | regk_irq_nmi_ack_irq = 0x00000002, | ||
| 100 | regk_irq_nmi_ack_nmi = 0x00000003, | ||
| 101 | regk_irq_nmi_irq = 0x00000000, | ||
| 102 | regk_irq_nmi_nmi = 0x00000001 | ||
| 103 | }; | ||
| 104 | #endif /* __irq_nmi_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h deleted file mode 100644 index a11fdd3cd907..000000000000 --- a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h +++ /dev/null | |||
| @@ -1,205 +0,0 @@ | |||
| 1 | #ifndef __marb_bp_defs_h | ||
| 2 | #define __marb_bp_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Fri Nov 7 15:36:04 2003 | ||
| 9 | * | ||
| 10 | * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 11 | * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | /* C-code for register scope marb_bp */ | ||
| 75 | |||
| 76 | /* Register rw_first_addr, scope marb_bp, type rw */ | ||
| 77 | typedef unsigned int reg_marb_bp_rw_first_addr; | ||
| 78 | #define REG_RD_ADDR_marb_bp_rw_first_addr 0 | ||
| 79 | #define REG_WR_ADDR_marb_bp_rw_first_addr 0 | ||
| 80 | |||
| 81 | /* Register rw_last_addr, scope marb_bp, type rw */ | ||
| 82 | typedef unsigned int reg_marb_bp_rw_last_addr; | ||
| 83 | #define REG_RD_ADDR_marb_bp_rw_last_addr 4 | ||
| 84 | #define REG_WR_ADDR_marb_bp_rw_last_addr 4 | ||
| 85 | |||
| 86 | /* Register rw_op, scope marb_bp, type rw */ | ||
| 87 | typedef struct { | ||
| 88 | unsigned int read : 1; | ||
| 89 | unsigned int write : 1; | ||
| 90 | unsigned int read_excl : 1; | ||
| 91 | unsigned int pri_write : 1; | ||
| 92 | unsigned int us_read : 1; | ||
| 93 | unsigned int us_write : 1; | ||
| 94 | unsigned int us_read_excl : 1; | ||
| 95 | unsigned int us_pri_write : 1; | ||
| 96 | unsigned int dummy1 : 24; | ||
| 97 | } reg_marb_bp_rw_op; | ||
| 98 | #define REG_RD_ADDR_marb_bp_rw_op 8 | ||
| 99 | #define REG_WR_ADDR_marb_bp_rw_op 8 | ||
| 100 | |||
| 101 | /* Register rw_clients, scope marb_bp, type rw */ | ||
| 102 | typedef struct { | ||
| 103 | unsigned int dma0 : 1; | ||
| 104 | unsigned int dma1 : 1; | ||
| 105 | unsigned int dma2 : 1; | ||
| 106 | unsigned int dma3 : 1; | ||
| 107 | unsigned int dma4 : 1; | ||
| 108 | unsigned int dma5 : 1; | ||
| 109 | unsigned int dma6 : 1; | ||
| 110 | unsigned int dma7 : 1; | ||
| 111 | unsigned int dma8 : 1; | ||
| 112 | unsigned int dma9 : 1; | ||
| 113 | unsigned int cpui : 1; | ||
| 114 | unsigned int cpud : 1; | ||
| 115 | unsigned int iop : 1; | ||
| 116 | unsigned int slave : 1; | ||
| 117 | unsigned int dummy1 : 18; | ||
| 118 | } reg_marb_bp_rw_clients; | ||
| 119 | #define REG_RD_ADDR_marb_bp_rw_clients 12 | ||
| 120 | #define REG_WR_ADDR_marb_bp_rw_clients 12 | ||
| 121 | |||
| 122 | /* Register rw_options, scope marb_bp, type rw */ | ||
| 123 | typedef struct { | ||
| 124 | unsigned int wrap : 1; | ||
| 125 | unsigned int dummy1 : 31; | ||
| 126 | } reg_marb_bp_rw_options; | ||
| 127 | #define REG_RD_ADDR_marb_bp_rw_options 16 | ||
| 128 | #define REG_WR_ADDR_marb_bp_rw_options 16 | ||
| 129 | |||
| 130 | /* Register r_break_addr, scope marb_bp, type r */ | ||
| 131 | typedef unsigned int reg_marb_bp_r_break_addr; | ||
| 132 | #define REG_RD_ADDR_marb_bp_r_break_addr 20 | ||
| 133 | |||
| 134 | /* Register r_break_op, scope marb_bp, type r */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int read : 1; | ||
| 137 | unsigned int write : 1; | ||
| 138 | unsigned int read_excl : 1; | ||
| 139 | unsigned int pri_write : 1; | ||
| 140 | unsigned int us_read : 1; | ||
| 141 | unsigned int us_write : 1; | ||
| 142 | unsigned int us_read_excl : 1; | ||
| 143 | unsigned int us_pri_write : 1; | ||
| 144 | unsigned int dummy1 : 24; | ||
| 145 | } reg_marb_bp_r_break_op; | ||
| 146 | #define REG_RD_ADDR_marb_bp_r_break_op 24 | ||
| 147 | |||
| 148 | /* Register r_break_clients, scope marb_bp, type r */ | ||
| 149 | typedef struct { | ||
| 150 | unsigned int dma0 : 1; | ||
| 151 | unsigned int dma1 : 1; | ||
| 152 | unsigned int dma2 : 1; | ||
| 153 | unsigned int dma3 : 1; | ||
| 154 | unsigned int dma4 : 1; | ||
| 155 | unsigned int dma5 : 1; | ||
| 156 | unsigned int dma6 : 1; | ||
| 157 | unsigned int dma7 : 1; | ||
| 158 | unsigned int dma8 : 1; | ||
| 159 | unsigned int dma9 : 1; | ||
| 160 | unsigned int cpui : 1; | ||
| 161 | unsigned int cpud : 1; | ||
| 162 | unsigned int iop : 1; | ||
| 163 | unsigned int slave : 1; | ||
| 164 | unsigned int dummy1 : 18; | ||
| 165 | } reg_marb_bp_r_break_clients; | ||
| 166 | #define REG_RD_ADDR_marb_bp_r_break_clients 28 | ||
| 167 | |||
| 168 | /* Register r_break_first_client, scope marb_bp, type r */ | ||
| 169 | typedef struct { | ||
| 170 | unsigned int dma0 : 1; | ||
| 171 | unsigned int dma1 : 1; | ||
| 172 | unsigned int dma2 : 1; | ||
| 173 | unsigned int dma3 : 1; | ||
| 174 | unsigned int dma4 : 1; | ||
| 175 | unsigned int dma5 : 1; | ||
| 176 | unsigned int dma6 : 1; | ||
| 177 | unsigned int dma7 : 1; | ||
| 178 | unsigned int dma8 : 1; | ||
| 179 | unsigned int dma9 : 1; | ||
| 180 | unsigned int cpui : 1; | ||
| 181 | unsigned int cpud : 1; | ||
| 182 | unsigned int iop : 1; | ||
| 183 | unsigned int slave : 1; | ||
| 184 | unsigned int dummy1 : 18; | ||
| 185 | } reg_marb_bp_r_break_first_client; | ||
| 186 | #define REG_RD_ADDR_marb_bp_r_break_first_client 32 | ||
| 187 | |||
| 188 | /* Register r_break_size, scope marb_bp, type r */ | ||
| 189 | typedef unsigned int reg_marb_bp_r_break_size; | ||
| 190 | #define REG_RD_ADDR_marb_bp_r_break_size 36 | ||
| 191 | |||
| 192 | /* Register rw_ack, scope marb_bp, type rw */ | ||
| 193 | typedef unsigned int reg_marb_bp_rw_ack; | ||
| 194 | #define REG_RD_ADDR_marb_bp_rw_ack 40 | ||
| 195 | #define REG_WR_ADDR_marb_bp_rw_ack 40 | ||
| 196 | |||
| 197 | |||
| 198 | /* Constants */ | ||
| 199 | enum { | ||
| 200 | regk_marb_bp_no = 0x00000000, | ||
| 201 | regk_marb_bp_rw_op_default = 0x00000000, | ||
| 202 | regk_marb_bp_rw_options_default = 0x00000000, | ||
| 203 | regk_marb_bp_yes = 0x00000001 | ||
| 204 | }; | ||
| 205 | #endif /* __marb_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/marb_defs.h b/include/asm-cris/arch-v32/hwregs/marb_defs.h deleted file mode 100644 index 71e8af0bb3a4..000000000000 --- a/include/asm-cris/arch-v32/hwregs/marb_defs.h +++ /dev/null | |||
| @@ -1,475 +0,0 @@ | |||
| 1 | #ifndef __marb_defs_h | ||
| 2 | #define __marb_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:12:16 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 11 | * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope marb */ | ||
| 86 | |||
| 87 | #define STRIDE_marb_rw_int_slots 4 | ||
| 88 | /* Register rw_int_slots, scope marb, type rw */ | ||
| 89 | typedef struct { | ||
| 90 | unsigned int owner : 4; | ||
| 91 | unsigned int dummy1 : 28; | ||
| 92 | } reg_marb_rw_int_slots; | ||
| 93 | #define REG_RD_ADDR_marb_rw_int_slots 0 | ||
| 94 | #define REG_WR_ADDR_marb_rw_int_slots 0 | ||
| 95 | |||
| 96 | #define STRIDE_marb_rw_ext_slots 4 | ||
| 97 | /* Register rw_ext_slots, scope marb, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int owner : 4; | ||
| 100 | unsigned int dummy1 : 28; | ||
| 101 | } reg_marb_rw_ext_slots; | ||
| 102 | #define REG_RD_ADDR_marb_rw_ext_slots 256 | ||
| 103 | #define REG_WR_ADDR_marb_rw_ext_slots 256 | ||
| 104 | |||
| 105 | #define STRIDE_marb_rw_regs_slots 4 | ||
| 106 | /* Register rw_regs_slots, scope marb, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int owner : 4; | ||
| 109 | unsigned int dummy1 : 28; | ||
| 110 | } reg_marb_rw_regs_slots; | ||
| 111 | #define REG_RD_ADDR_marb_rw_regs_slots 512 | ||
| 112 | #define REG_WR_ADDR_marb_rw_regs_slots 512 | ||
| 113 | |||
| 114 | /* Register rw_intr_mask, scope marb, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int bp0 : 1; | ||
| 117 | unsigned int bp1 : 1; | ||
| 118 | unsigned int bp2 : 1; | ||
| 119 | unsigned int bp3 : 1; | ||
| 120 | unsigned int dummy1 : 28; | ||
| 121 | } reg_marb_rw_intr_mask; | ||
| 122 | #define REG_RD_ADDR_marb_rw_intr_mask 528 | ||
| 123 | #define REG_WR_ADDR_marb_rw_intr_mask 528 | ||
| 124 | |||
| 125 | /* Register rw_ack_intr, scope marb, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int bp0 : 1; | ||
| 128 | unsigned int bp1 : 1; | ||
| 129 | unsigned int bp2 : 1; | ||
| 130 | unsigned int bp3 : 1; | ||
| 131 | unsigned int dummy1 : 28; | ||
| 132 | } reg_marb_rw_ack_intr; | ||
| 133 | #define REG_RD_ADDR_marb_rw_ack_intr 532 | ||
| 134 | #define REG_WR_ADDR_marb_rw_ack_intr 532 | ||
| 135 | |||
| 136 | /* Register r_intr, scope marb, type r */ | ||
| 137 | typedef struct { | ||
| 138 | unsigned int bp0 : 1; | ||
| 139 | unsigned int bp1 : 1; | ||
| 140 | unsigned int bp2 : 1; | ||
| 141 | unsigned int bp3 : 1; | ||
| 142 | unsigned int dummy1 : 28; | ||
| 143 | } reg_marb_r_intr; | ||
| 144 | #define REG_RD_ADDR_marb_r_intr 536 | ||
| 145 | |||
| 146 | /* Register r_masked_intr, scope marb, type r */ | ||
| 147 | typedef struct { | ||
| 148 | unsigned int bp0 : 1; | ||
| 149 | unsigned int bp1 : 1; | ||
| 150 | unsigned int bp2 : 1; | ||
| 151 | unsigned int bp3 : 1; | ||
| 152 | unsigned int dummy1 : 28; | ||
| 153 | } reg_marb_r_masked_intr; | ||
| 154 | #define REG_RD_ADDR_marb_r_masked_intr 540 | ||
| 155 | |||
| 156 | /* Register rw_stop_mask, scope marb, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int dma0 : 1; | ||
| 159 | unsigned int dma1 : 1; | ||
| 160 | unsigned int dma2 : 1; | ||
| 161 | unsigned int dma3 : 1; | ||
| 162 | unsigned int dma4 : 1; | ||
| 163 | unsigned int dma5 : 1; | ||
| 164 | unsigned int dma6 : 1; | ||
| 165 | unsigned int dma7 : 1; | ||
| 166 | unsigned int dma8 : 1; | ||
| 167 | unsigned int dma9 : 1; | ||
| 168 | unsigned int cpui : 1; | ||
| 169 | unsigned int cpud : 1; | ||
| 170 | unsigned int iop : 1; | ||
| 171 | unsigned int slave : 1; | ||
| 172 | unsigned int dummy1 : 18; | ||
| 173 | } reg_marb_rw_stop_mask; | ||
| 174 | #define REG_RD_ADDR_marb_rw_stop_mask 544 | ||
| 175 | #define REG_WR_ADDR_marb_rw_stop_mask 544 | ||
| 176 | |||
| 177 | /* Register r_stopped, scope marb, type r */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int dma0 : 1; | ||
| 180 | unsigned int dma1 : 1; | ||
| 181 | unsigned int dma2 : 1; | ||
| 182 | unsigned int dma3 : 1; | ||
| 183 | unsigned int dma4 : 1; | ||
| 184 | unsigned int dma5 : 1; | ||
| 185 | unsigned int dma6 : 1; | ||
| 186 | unsigned int dma7 : 1; | ||
| 187 | unsigned int dma8 : 1; | ||
| 188 | unsigned int dma9 : 1; | ||
| 189 | unsigned int cpui : 1; | ||
| 190 | unsigned int cpud : 1; | ||
| 191 | unsigned int iop : 1; | ||
| 192 | unsigned int slave : 1; | ||
| 193 | unsigned int dummy1 : 18; | ||
| 194 | } reg_marb_r_stopped; | ||
| 195 | #define REG_RD_ADDR_marb_r_stopped 548 | ||
| 196 | |||
| 197 | /* Register rw_no_snoop, scope marb, type rw */ | ||
| 198 | typedef struct { | ||
| 199 | unsigned int dma0 : 1; | ||
| 200 | unsigned int dma1 : 1; | ||
| 201 | unsigned int dma2 : 1; | ||
| 202 | unsigned int dma3 : 1; | ||
| 203 | unsigned int dma4 : 1; | ||
| 204 | unsigned int dma5 : 1; | ||
| 205 | unsigned int dma6 : 1; | ||
| 206 | unsigned int dma7 : 1; | ||
| 207 | unsigned int dma8 : 1; | ||
| 208 | unsigned int dma9 : 1; | ||
| 209 | unsigned int cpui : 1; | ||
| 210 | unsigned int cpud : 1; | ||
| 211 | unsigned int iop : 1; | ||
| 212 | unsigned int slave : 1; | ||
| 213 | unsigned int dummy1 : 18; | ||
| 214 | } reg_marb_rw_no_snoop; | ||
| 215 | #define REG_RD_ADDR_marb_rw_no_snoop 832 | ||
| 216 | #define REG_WR_ADDR_marb_rw_no_snoop 832 | ||
| 217 | |||
| 218 | /* Register rw_no_snoop_rq, scope marb, type rw */ | ||
| 219 | typedef struct { | ||
| 220 | unsigned int dummy1 : 10; | ||
| 221 | unsigned int cpui : 1; | ||
| 222 | unsigned int cpud : 1; | ||
| 223 | unsigned int dummy2 : 20; | ||
| 224 | } reg_marb_rw_no_snoop_rq; | ||
| 225 | #define REG_RD_ADDR_marb_rw_no_snoop_rq 836 | ||
| 226 | #define REG_WR_ADDR_marb_rw_no_snoop_rq 836 | ||
| 227 | |||
| 228 | |||
| 229 | /* Constants */ | ||
| 230 | enum { | ||
| 231 | regk_marb_cpud = 0x0000000b, | ||
| 232 | regk_marb_cpui = 0x0000000a, | ||
| 233 | regk_marb_dma0 = 0x00000000, | ||
| 234 | regk_marb_dma1 = 0x00000001, | ||
| 235 | regk_marb_dma2 = 0x00000002, | ||
| 236 | regk_marb_dma3 = 0x00000003, | ||
| 237 | regk_marb_dma4 = 0x00000004, | ||
| 238 | regk_marb_dma5 = 0x00000005, | ||
| 239 | regk_marb_dma6 = 0x00000006, | ||
| 240 | regk_marb_dma7 = 0x00000007, | ||
| 241 | regk_marb_dma8 = 0x00000008, | ||
| 242 | regk_marb_dma9 = 0x00000009, | ||
| 243 | regk_marb_iop = 0x0000000c, | ||
| 244 | regk_marb_no = 0x00000000, | ||
| 245 | regk_marb_r_stopped_default = 0x00000000, | ||
| 246 | regk_marb_rw_ext_slots_default = 0x00000000, | ||
| 247 | regk_marb_rw_ext_slots_size = 0x00000040, | ||
| 248 | regk_marb_rw_int_slots_default = 0x00000000, | ||
| 249 | regk_marb_rw_int_slots_size = 0x00000040, | ||
| 250 | regk_marb_rw_intr_mask_default = 0x00000000, | ||
| 251 | regk_marb_rw_no_snoop_default = 0x00000000, | ||
| 252 | regk_marb_rw_no_snoop_rq_default = 0x00000000, | ||
| 253 | regk_marb_rw_regs_slots_default = 0x00000000, | ||
| 254 | regk_marb_rw_regs_slots_size = 0x00000004, | ||
| 255 | regk_marb_rw_stop_mask_default = 0x00000000, | ||
| 256 | regk_marb_slave = 0x0000000d, | ||
| 257 | regk_marb_yes = 0x00000001 | ||
| 258 | }; | ||
| 259 | #endif /* __marb_defs_h */ | ||
| 260 | #ifndef __marb_bp_defs_h | ||
| 261 | #define __marb_bp_defs_h | ||
| 262 | |||
| 263 | /* | ||
| 264 | * This file is autogenerated from | ||
| 265 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 266 | * id: <not found> | ||
| 267 | * last modfied: Mon Apr 11 16:12:16 2005 | ||
| 268 | * | ||
| 269 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 270 | * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ | ||
| 271 | * Any changes here will be lost. | ||
| 272 | * | ||
| 273 | * -*- buffer-read-only: t -*- | ||
| 274 | */ | ||
| 275 | /* Main access macros */ | ||
| 276 | #ifndef REG_RD | ||
| 277 | #define REG_RD( scope, inst, reg ) \ | ||
| 278 | REG_READ( reg_##scope##_##reg, \ | ||
| 279 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 280 | #endif | ||
| 281 | |||
| 282 | #ifndef REG_WR | ||
| 283 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 284 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 285 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 286 | #endif | ||
| 287 | |||
| 288 | #ifndef REG_RD_VECT | ||
| 289 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 290 | REG_READ( reg_##scope##_##reg, \ | ||
| 291 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 292 | (index) * STRIDE_##scope##_##reg ) | ||
| 293 | #endif | ||
| 294 | |||
| 295 | #ifndef REG_WR_VECT | ||
| 296 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 297 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 298 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 299 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 300 | #endif | ||
| 301 | |||
| 302 | #ifndef REG_RD_INT | ||
| 303 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 304 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 305 | #endif | ||
| 306 | |||
| 307 | #ifndef REG_WR_INT | ||
| 308 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 309 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 310 | #endif | ||
| 311 | |||
| 312 | #ifndef REG_RD_INT_VECT | ||
| 313 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 314 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 315 | (index) * STRIDE_##scope##_##reg ) | ||
| 316 | #endif | ||
| 317 | |||
| 318 | #ifndef REG_WR_INT_VECT | ||
| 319 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 320 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 321 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 322 | #endif | ||
| 323 | |||
| 324 | #ifndef REG_TYPE_CONV | ||
| 325 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 326 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #ifndef reg_page_size | ||
| 330 | #define reg_page_size 8192 | ||
| 331 | #endif | ||
| 332 | |||
| 333 | #ifndef REG_ADDR | ||
| 334 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 335 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 336 | #endif | ||
| 337 | |||
| 338 | #ifndef REG_ADDR_VECT | ||
| 339 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 340 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 341 | (index) * STRIDE_##scope##_##reg ) | ||
| 342 | #endif | ||
| 343 | |||
| 344 | /* C-code for register scope marb_bp */ | ||
| 345 | |||
| 346 | /* Register rw_first_addr, scope marb_bp, type rw */ | ||
| 347 | typedef unsigned int reg_marb_bp_rw_first_addr; | ||
| 348 | #define REG_RD_ADDR_marb_bp_rw_first_addr 0 | ||
| 349 | #define REG_WR_ADDR_marb_bp_rw_first_addr 0 | ||
| 350 | |||
| 351 | /* Register rw_last_addr, scope marb_bp, type rw */ | ||
| 352 | typedef unsigned int reg_marb_bp_rw_last_addr; | ||
| 353 | #define REG_RD_ADDR_marb_bp_rw_last_addr 4 | ||
| 354 | #define REG_WR_ADDR_marb_bp_rw_last_addr 4 | ||
| 355 | |||
| 356 | /* Register rw_op, scope marb_bp, type rw */ | ||
| 357 | typedef struct { | ||
| 358 | unsigned int rd : 1; | ||
| 359 | unsigned int wr : 1; | ||
| 360 | unsigned int rd_excl : 1; | ||
| 361 | unsigned int pri_wr : 1; | ||
| 362 | unsigned int us_rd : 1; | ||
| 363 | unsigned int us_wr : 1; | ||
| 364 | unsigned int us_rd_excl : 1; | ||
| 365 | unsigned int us_pri_wr : 1; | ||
| 366 | unsigned int dummy1 : 24; | ||
| 367 | } reg_marb_bp_rw_op; | ||
| 368 | #define REG_RD_ADDR_marb_bp_rw_op 8 | ||
| 369 | #define REG_WR_ADDR_marb_bp_rw_op 8 | ||
| 370 | |||
| 371 | /* Register rw_clients, scope marb_bp, type rw */ | ||
| 372 | typedef struct { | ||
| 373 | unsigned int dma0 : 1; | ||
| 374 | unsigned int dma1 : 1; | ||
| 375 | unsigned int dma2 : 1; | ||
| 376 | unsigned int dma3 : 1; | ||
| 377 | unsigned int dma4 : 1; | ||
| 378 | unsigned int dma5 : 1; | ||
| 379 | unsigned int dma6 : 1; | ||
| 380 | unsigned int dma7 : 1; | ||
| 381 | unsigned int dma8 : 1; | ||
| 382 | unsigned int dma9 : 1; | ||
| 383 | unsigned int cpui : 1; | ||
| 384 | unsigned int cpud : 1; | ||
| 385 | unsigned int iop : 1; | ||
| 386 | unsigned int slave : 1; | ||
| 387 | unsigned int dummy1 : 18; | ||
| 388 | } reg_marb_bp_rw_clients; | ||
| 389 | #define REG_RD_ADDR_marb_bp_rw_clients 12 | ||
| 390 | #define REG_WR_ADDR_marb_bp_rw_clients 12 | ||
| 391 | |||
| 392 | /* Register rw_options, scope marb_bp, type rw */ | ||
| 393 | typedef struct { | ||
| 394 | unsigned int wrap : 1; | ||
| 395 | unsigned int dummy1 : 31; | ||
| 396 | } reg_marb_bp_rw_options; | ||
| 397 | #define REG_RD_ADDR_marb_bp_rw_options 16 | ||
| 398 | #define REG_WR_ADDR_marb_bp_rw_options 16 | ||
| 399 | |||
| 400 | /* Register r_brk_addr, scope marb_bp, type r */ | ||
| 401 | typedef unsigned int reg_marb_bp_r_brk_addr; | ||
| 402 | #define REG_RD_ADDR_marb_bp_r_brk_addr 20 | ||
| 403 | |||
| 404 | /* Register r_brk_op, scope marb_bp, type r */ | ||
| 405 | typedef struct { | ||
| 406 | unsigned int rd : 1; | ||
| 407 | unsigned int wr : 1; | ||
| 408 | unsigned int rd_excl : 1; | ||
| 409 | unsigned int pri_wr : 1; | ||
| 410 | unsigned int us_rd : 1; | ||
| 411 | unsigned int us_wr : 1; | ||
| 412 | unsigned int us_rd_excl : 1; | ||
| 413 | unsigned int us_pri_wr : 1; | ||
| 414 | unsigned int dummy1 : 24; | ||
| 415 | } reg_marb_bp_r_brk_op; | ||
| 416 | #define REG_RD_ADDR_marb_bp_r_brk_op 24 | ||
| 417 | |||
| 418 | /* Register r_brk_clients, scope marb_bp, type r */ | ||
| 419 | typedef struct { | ||
| 420 | unsigned int dma0 : 1; | ||
| 421 | unsigned int dma1 : 1; | ||
| 422 | unsigned int dma2 : 1; | ||
| 423 | unsigned int dma3 : 1; | ||
| 424 | unsigned int dma4 : 1; | ||
| 425 | unsigned int dma5 : 1; | ||
| 426 | unsigned int dma6 : 1; | ||
| 427 | unsigned int dma7 : 1; | ||
| 428 | unsigned int dma8 : 1; | ||
| 429 | unsigned int dma9 : 1; | ||
| 430 | unsigned int cpui : 1; | ||
| 431 | unsigned int cpud : 1; | ||
| 432 | unsigned int iop : 1; | ||
| 433 | unsigned int slave : 1; | ||
| 434 | unsigned int dummy1 : 18; | ||
| 435 | } reg_marb_bp_r_brk_clients; | ||
| 436 | #define REG_RD_ADDR_marb_bp_r_brk_clients 28 | ||
| 437 | |||
| 438 | /* Register r_brk_first_client, scope marb_bp, type r */ | ||
| 439 | typedef struct { | ||
| 440 | unsigned int dma0 : 1; | ||
| 441 | unsigned int dma1 : 1; | ||
| 442 | unsigned int dma2 : 1; | ||
| 443 | unsigned int dma3 : 1; | ||
| 444 | unsigned int dma4 : 1; | ||
| 445 | unsigned int dma5 : 1; | ||
| 446 | unsigned int dma6 : 1; | ||
| 447 | unsigned int dma7 : 1; | ||
| 448 | unsigned int dma8 : 1; | ||
| 449 | unsigned int dma9 : 1; | ||
| 450 | unsigned int cpui : 1; | ||
| 451 | unsigned int cpud : 1; | ||
| 452 | unsigned int iop : 1; | ||
| 453 | unsigned int slave : 1; | ||
| 454 | unsigned int dummy1 : 18; | ||
| 455 | } reg_marb_bp_r_brk_first_client; | ||
| 456 | #define REG_RD_ADDR_marb_bp_r_brk_first_client 32 | ||
| 457 | |||
| 458 | /* Register r_brk_size, scope marb_bp, type r */ | ||
| 459 | typedef unsigned int reg_marb_bp_r_brk_size; | ||
| 460 | #define REG_RD_ADDR_marb_bp_r_brk_size 36 | ||
| 461 | |||
| 462 | /* Register rw_ack, scope marb_bp, type rw */ | ||
| 463 | typedef unsigned int reg_marb_bp_rw_ack; | ||
| 464 | #define REG_RD_ADDR_marb_bp_rw_ack 40 | ||
| 465 | #define REG_WR_ADDR_marb_bp_rw_ack 40 | ||
| 466 | |||
| 467 | |||
| 468 | /* Constants */ | ||
| 469 | enum { | ||
| 470 | regk_marb_bp_no = 0x00000000, | ||
| 471 | regk_marb_bp_rw_op_default = 0x00000000, | ||
| 472 | regk_marb_bp_rw_options_default = 0x00000000, | ||
| 473 | regk_marb_bp_yes = 0x00000001 | ||
| 474 | }; | ||
| 475 | #endif /* __marb_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h deleted file mode 100644 index 9d91c2de1b07..000000000000 --- a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h +++ /dev/null | |||
| @@ -1,357 +0,0 @@ | |||
| 1 | #ifndef __pinmux_defs_h | ||
| 2 | #define __pinmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 7 | * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:11 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 11 | * id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope pinmux */ | ||
| 86 | |||
| 87 | /* Register rw_pa, scope pinmux, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int pa0 : 1; | ||
| 90 | unsigned int pa1 : 1; | ||
| 91 | unsigned int pa2 : 1; | ||
| 92 | unsigned int pa3 : 1; | ||
| 93 | unsigned int pa4 : 1; | ||
| 94 | unsigned int pa5 : 1; | ||
| 95 | unsigned int pa6 : 1; | ||
| 96 | unsigned int pa7 : 1; | ||
| 97 | unsigned int csp2_n : 1; | ||
| 98 | unsigned int csp3_n : 1; | ||
| 99 | unsigned int csp5_n : 1; | ||
| 100 | unsigned int csp6_n : 1; | ||
| 101 | unsigned int hsh4 : 1; | ||
| 102 | unsigned int hsh5 : 1; | ||
| 103 | unsigned int hsh6 : 1; | ||
| 104 | unsigned int hsh7 : 1; | ||
| 105 | unsigned int dummy1 : 16; | ||
| 106 | } reg_pinmux_rw_pa; | ||
| 107 | #define REG_RD_ADDR_pinmux_rw_pa 0 | ||
| 108 | #define REG_WR_ADDR_pinmux_rw_pa 0 | ||
| 109 | |||
| 110 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int ser1 : 1; | ||
| 113 | unsigned int ser2 : 1; | ||
| 114 | unsigned int ser3 : 1; | ||
| 115 | unsigned int sser0 : 1; | ||
| 116 | unsigned int sser1 : 1; | ||
| 117 | unsigned int ata0 : 1; | ||
| 118 | unsigned int ata1 : 1; | ||
| 119 | unsigned int ata2 : 1; | ||
| 120 | unsigned int ata3 : 1; | ||
| 121 | unsigned int ata : 1; | ||
| 122 | unsigned int eth1 : 1; | ||
| 123 | unsigned int eth1_mgm : 1; | ||
| 124 | unsigned int timer : 1; | ||
| 125 | unsigned int p21 : 1; | ||
| 126 | unsigned int dummy1 : 18; | ||
| 127 | } reg_pinmux_rw_hwprot; | ||
| 128 | #define REG_RD_ADDR_pinmux_rw_hwprot 4 | ||
| 129 | #define REG_WR_ADDR_pinmux_rw_hwprot 4 | ||
| 130 | |||
| 131 | /* Register rw_pb_gio, scope pinmux, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int pb0 : 1; | ||
| 134 | unsigned int pb1 : 1; | ||
| 135 | unsigned int pb2 : 1; | ||
| 136 | unsigned int pb3 : 1; | ||
| 137 | unsigned int pb4 : 1; | ||
| 138 | unsigned int pb5 : 1; | ||
| 139 | unsigned int pb6 : 1; | ||
| 140 | unsigned int pb7 : 1; | ||
| 141 | unsigned int pb8 : 1; | ||
| 142 | unsigned int pb9 : 1; | ||
| 143 | unsigned int pb10 : 1; | ||
| 144 | unsigned int pb11 : 1; | ||
| 145 | unsigned int pb12 : 1; | ||
| 146 | unsigned int pb13 : 1; | ||
| 147 | unsigned int pb14 : 1; | ||
| 148 | unsigned int pb15 : 1; | ||
| 149 | unsigned int pb16 : 1; | ||
| 150 | unsigned int pb17 : 1; | ||
| 151 | unsigned int dummy1 : 14; | ||
| 152 | } reg_pinmux_rw_pb_gio; | ||
| 153 | #define REG_RD_ADDR_pinmux_rw_pb_gio 8 | ||
| 154 | #define REG_WR_ADDR_pinmux_rw_pb_gio 8 | ||
| 155 | |||
| 156 | /* Register rw_pb_iop, scope pinmux, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int pb0 : 1; | ||
| 159 | unsigned int pb1 : 1; | ||
| 160 | unsigned int pb2 : 1; | ||
| 161 | unsigned int pb3 : 1; | ||
| 162 | unsigned int pb4 : 1; | ||
| 163 | unsigned int pb5 : 1; | ||
| 164 | unsigned int pb6 : 1; | ||
| 165 | unsigned int pb7 : 1; | ||
| 166 | unsigned int pb8 : 1; | ||
| 167 | unsigned int pb9 : 1; | ||
| 168 | unsigned int pb10 : 1; | ||
| 169 | unsigned int pb11 : 1; | ||
| 170 | unsigned int pb12 : 1; | ||
| 171 | unsigned int pb13 : 1; | ||
| 172 | unsigned int pb14 : 1; | ||
| 173 | unsigned int pb15 : 1; | ||
| 174 | unsigned int pb16 : 1; | ||
| 175 | unsigned int pb17 : 1; | ||
| 176 | unsigned int dummy1 : 14; | ||
| 177 | } reg_pinmux_rw_pb_iop; | ||
| 178 | #define REG_RD_ADDR_pinmux_rw_pb_iop 12 | ||
| 179 | #define REG_WR_ADDR_pinmux_rw_pb_iop 12 | ||
| 180 | |||
| 181 | /* Register rw_pc_gio, scope pinmux, type rw */ | ||
| 182 | typedef struct { | ||
| 183 | unsigned int pc0 : 1; | ||
| 184 | unsigned int pc1 : 1; | ||
| 185 | unsigned int pc2 : 1; | ||
| 186 | unsigned int pc3 : 1; | ||
| 187 | unsigned int pc4 : 1; | ||
| 188 | unsigned int pc5 : 1; | ||
| 189 | unsigned int pc6 : 1; | ||
| 190 | unsigned int pc7 : 1; | ||
| 191 | unsigned int pc8 : 1; | ||
| 192 | unsigned int pc9 : 1; | ||
| 193 | unsigned int pc10 : 1; | ||
| 194 | unsigned int pc11 : 1; | ||
| 195 | unsigned int pc12 : 1; | ||
| 196 | unsigned int pc13 : 1; | ||
| 197 | unsigned int pc14 : 1; | ||
| 198 | unsigned int pc15 : 1; | ||
| 199 | unsigned int pc16 : 1; | ||
| 200 | unsigned int pc17 : 1; | ||
| 201 | unsigned int dummy1 : 14; | ||
| 202 | } reg_pinmux_rw_pc_gio; | ||
| 203 | #define REG_RD_ADDR_pinmux_rw_pc_gio 16 | ||
| 204 | #define REG_WR_ADDR_pinmux_rw_pc_gio 16 | ||
| 205 | |||
| 206 | /* Register rw_pc_iop, scope pinmux, type rw */ | ||
| 207 | typedef struct { | ||
| 208 | unsigned int pc0 : 1; | ||
| 209 | unsigned int pc1 : 1; | ||
| 210 | unsigned int pc2 : 1; | ||
| 211 | unsigned int pc3 : 1; | ||
| 212 | unsigned int pc4 : 1; | ||
| 213 | unsigned int pc5 : 1; | ||
| 214 | unsigned int pc6 : 1; | ||
| 215 | unsigned int pc7 : 1; | ||
| 216 | unsigned int pc8 : 1; | ||
| 217 | unsigned int pc9 : 1; | ||
| 218 | unsigned int pc10 : 1; | ||
| 219 | unsigned int pc11 : 1; | ||
| 220 | unsigned int pc12 : 1; | ||
| 221 | unsigned int pc13 : 1; | ||
| 222 | unsigned int pc14 : 1; | ||
| 223 | unsigned int pc15 : 1; | ||
| 224 | unsigned int pc16 : 1; | ||
| 225 | unsigned int pc17 : 1; | ||
| 226 | unsigned int dummy1 : 14; | ||
| 227 | } reg_pinmux_rw_pc_iop; | ||
| 228 | #define REG_RD_ADDR_pinmux_rw_pc_iop 20 | ||
| 229 | #define REG_WR_ADDR_pinmux_rw_pc_iop 20 | ||
| 230 | |||
| 231 | /* Register rw_pd_gio, scope pinmux, type rw */ | ||
| 232 | typedef struct { | ||
| 233 | unsigned int pd0 : 1; | ||
| 234 | unsigned int pd1 : 1; | ||
| 235 | unsigned int pd2 : 1; | ||
| 236 | unsigned int pd3 : 1; | ||
| 237 | unsigned int pd4 : 1; | ||
| 238 | unsigned int pd5 : 1; | ||
| 239 | unsigned int pd6 : 1; | ||
| 240 | unsigned int pd7 : 1; | ||
| 241 | unsigned int pd8 : 1; | ||
| 242 | unsigned int pd9 : 1; | ||
| 243 | unsigned int pd10 : 1; | ||
| 244 | unsigned int pd11 : 1; | ||
| 245 | unsigned int pd12 : 1; | ||
| 246 | unsigned int pd13 : 1; | ||
| 247 | unsigned int pd14 : 1; | ||
| 248 | unsigned int pd15 : 1; | ||
| 249 | unsigned int pd16 : 1; | ||
| 250 | unsigned int pd17 : 1; | ||
| 251 | unsigned int dummy1 : 14; | ||
| 252 | } reg_pinmux_rw_pd_gio; | ||
| 253 | #define REG_RD_ADDR_pinmux_rw_pd_gio 24 | ||
| 254 | #define REG_WR_ADDR_pinmux_rw_pd_gio 24 | ||
| 255 | |||
| 256 | /* Register rw_pd_iop, scope pinmux, type rw */ | ||
| 257 | typedef struct { | ||
| 258 | unsigned int pd0 : 1; | ||
| 259 | unsigned int pd1 : 1; | ||
| 260 | unsigned int pd2 : 1; | ||
| 261 | unsigned int pd3 : 1; | ||
| 262 | unsigned int pd4 : 1; | ||
| 263 | unsigned int pd5 : 1; | ||
| 264 | unsigned int pd6 : 1; | ||
| 265 | unsigned int pd7 : 1; | ||
| 266 | unsigned int pd8 : 1; | ||
| 267 | unsigned int pd9 : 1; | ||
| 268 | unsigned int pd10 : 1; | ||
| 269 | unsigned int pd11 : 1; | ||
| 270 | unsigned int pd12 : 1; | ||
| 271 | unsigned int pd13 : 1; | ||
| 272 | unsigned int pd14 : 1; | ||
| 273 | unsigned int pd15 : 1; | ||
| 274 | unsigned int pd16 : 1; | ||
| 275 | unsigned int pd17 : 1; | ||
| 276 | unsigned int dummy1 : 14; | ||
| 277 | } reg_pinmux_rw_pd_iop; | ||
| 278 | #define REG_RD_ADDR_pinmux_rw_pd_iop 28 | ||
| 279 | #define REG_WR_ADDR_pinmux_rw_pd_iop 28 | ||
| 280 | |||
| 281 | /* Register rw_pe_gio, scope pinmux, type rw */ | ||
| 282 | typedef struct { | ||
| 283 | unsigned int pe0 : 1; | ||
| 284 | unsigned int pe1 : 1; | ||
| 285 | unsigned int pe2 : 1; | ||
| 286 | unsigned int pe3 : 1; | ||
| 287 | unsigned int pe4 : 1; | ||
| 288 | unsigned int pe5 : 1; | ||
| 289 | unsigned int pe6 : 1; | ||
| 290 | unsigned int pe7 : 1; | ||
| 291 | unsigned int pe8 : 1; | ||
| 292 | unsigned int pe9 : 1; | ||
| 293 | unsigned int pe10 : 1; | ||
| 294 | unsigned int pe11 : 1; | ||
| 295 | unsigned int pe12 : 1; | ||
| 296 | unsigned int pe13 : 1; | ||
| 297 | unsigned int pe14 : 1; | ||
| 298 | unsigned int pe15 : 1; | ||
| 299 | unsigned int pe16 : 1; | ||
| 300 | unsigned int pe17 : 1; | ||
| 301 | unsigned int dummy1 : 14; | ||
| 302 | } reg_pinmux_rw_pe_gio; | ||
| 303 | #define REG_RD_ADDR_pinmux_rw_pe_gio 32 | ||
| 304 | #define REG_WR_ADDR_pinmux_rw_pe_gio 32 | ||
| 305 | |||
| 306 | /* Register rw_pe_iop, scope pinmux, type rw */ | ||
| 307 | typedef struct { | ||
| 308 | unsigned int pe0 : 1; | ||
| 309 | unsigned int pe1 : 1; | ||
| 310 | unsigned int pe2 : 1; | ||
| 311 | unsigned int pe3 : 1; | ||
| 312 | unsigned int pe4 : 1; | ||
| 313 | unsigned int pe5 : 1; | ||
| 314 | unsigned int pe6 : 1; | ||
| 315 | unsigned int pe7 : 1; | ||
| 316 | unsigned int pe8 : 1; | ||
| 317 | unsigned int pe9 : 1; | ||
| 318 | unsigned int pe10 : 1; | ||
| 319 | unsigned int pe11 : 1; | ||
| 320 | unsigned int pe12 : 1; | ||
| 321 | unsigned int pe13 : 1; | ||
| 322 | unsigned int pe14 : 1; | ||
| 323 | unsigned int pe15 : 1; | ||
| 324 | unsigned int pe16 : 1; | ||
| 325 | unsigned int pe17 : 1; | ||
| 326 | unsigned int dummy1 : 14; | ||
| 327 | } reg_pinmux_rw_pe_iop; | ||
| 328 | #define REG_RD_ADDR_pinmux_rw_pe_iop 36 | ||
| 329 | #define REG_WR_ADDR_pinmux_rw_pe_iop 36 | ||
| 330 | |||
| 331 | /* Register rw_usb_phy, scope pinmux, type rw */ | ||
| 332 | typedef struct { | ||
| 333 | unsigned int en_usb0 : 1; | ||
| 334 | unsigned int en_usb1 : 1; | ||
| 335 | unsigned int dummy1 : 30; | ||
| 336 | } reg_pinmux_rw_usb_phy; | ||
| 337 | #define REG_RD_ADDR_pinmux_rw_usb_phy 40 | ||
| 338 | #define REG_WR_ADDR_pinmux_rw_usb_phy 40 | ||
| 339 | |||
| 340 | |||
| 341 | /* Constants */ | ||
| 342 | enum { | ||
| 343 | regk_pinmux_no = 0x00000000, | ||
| 344 | regk_pinmux_rw_hwprot_default = 0x00000000, | ||
| 345 | regk_pinmux_rw_pa_default = 0x00000000, | ||
| 346 | regk_pinmux_rw_pb_gio_default = 0x00000000, | ||
| 347 | regk_pinmux_rw_pb_iop_default = 0x00000000, | ||
| 348 | regk_pinmux_rw_pc_gio_default = 0x00000000, | ||
| 349 | regk_pinmux_rw_pc_iop_default = 0x00000000, | ||
| 350 | regk_pinmux_rw_pd_gio_default = 0x00000000, | ||
| 351 | regk_pinmux_rw_pd_iop_default = 0x00000000, | ||
| 352 | regk_pinmux_rw_pe_gio_default = 0x00000000, | ||
| 353 | regk_pinmux_rw_pe_iop_default = 0x00000000, | ||
| 354 | regk_pinmux_rw_usb_phy_default = 0x00000000, | ||
| 355 | regk_pinmux_yes = 0x00000001 | ||
| 356 | }; | ||
| 357 | #endif /* __pinmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h deleted file mode 100644 index 236f91efe7e8..000000000000 --- a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Read/write register macros used by *_defs.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef reg_rdwr_h | ||
| 6 | #define reg_rdwr_h | ||
| 7 | |||
| 8 | #ifndef REG_READ | ||
| 9 | #define REG_READ(type, addr) (*((volatile type *) (addr))) | ||
| 10 | #endif | ||
| 11 | |||
| 12 | #ifndef REG_WRITE | ||
| 13 | #define REG_WRITE(type, addr, val) \ | ||
| 14 | do { *((volatile type *) (addr)) = (val); } while(0) | ||
| 15 | #endif | ||
| 16 | |||
| 17 | #endif | ||
diff --git a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h deleted file mode 100644 index d9f0e924fb23..000000000000 --- a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h +++ /dev/null | |||
| @@ -1,173 +0,0 @@ | |||
| 1 | #ifndef __rt_trace_defs_h | ||
| 2 | #define __rt_trace_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/rt_trace/rtl/rt_regs.r | ||
| 7 | * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:14 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r | ||
| 11 | * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope rt_trace */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope rt_trace, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int en : 1; | ||
| 90 | unsigned int mode : 1; | ||
| 91 | unsigned int owner : 1; | ||
| 92 | unsigned int wp : 1; | ||
| 93 | unsigned int stall : 1; | ||
| 94 | unsigned int dummy1 : 3; | ||
| 95 | unsigned int wp_start : 7; | ||
| 96 | unsigned int dummy2 : 1; | ||
| 97 | unsigned int wp_stop : 7; | ||
| 98 | unsigned int dummy3 : 9; | ||
| 99 | } reg_rt_trace_rw_cfg; | ||
| 100 | #define REG_RD_ADDR_rt_trace_rw_cfg 0 | ||
| 101 | #define REG_WR_ADDR_rt_trace_rw_cfg 0 | ||
| 102 | |||
| 103 | /* Register rw_tap_ctrl, scope rt_trace, type rw */ | ||
| 104 | typedef struct { | ||
| 105 | unsigned int ack_data : 1; | ||
| 106 | unsigned int ack_guru : 1; | ||
| 107 | unsigned int dummy1 : 30; | ||
| 108 | } reg_rt_trace_rw_tap_ctrl; | ||
| 109 | #define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4 | ||
| 110 | #define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4 | ||
| 111 | |||
| 112 | /* Register r_tap_stat, scope rt_trace, type r */ | ||
| 113 | typedef struct { | ||
| 114 | unsigned int dav : 1; | ||
| 115 | unsigned int empty : 1; | ||
| 116 | unsigned int dummy1 : 30; | ||
| 117 | } reg_rt_trace_r_tap_stat; | ||
| 118 | #define REG_RD_ADDR_rt_trace_r_tap_stat 8 | ||
| 119 | |||
| 120 | /* Register rw_tap_data, scope rt_trace, type rw */ | ||
| 121 | typedef unsigned int reg_rt_trace_rw_tap_data; | ||
| 122 | #define REG_RD_ADDR_rt_trace_rw_tap_data 12 | ||
| 123 | #define REG_WR_ADDR_rt_trace_rw_tap_data 12 | ||
| 124 | |||
| 125 | /* Register rw_tap_hdata, scope rt_trace, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int op : 4; | ||
| 128 | unsigned int sub_op : 4; | ||
| 129 | unsigned int dummy1 : 24; | ||
| 130 | } reg_rt_trace_rw_tap_hdata; | ||
| 131 | #define REG_RD_ADDR_rt_trace_rw_tap_hdata 16 | ||
| 132 | #define REG_WR_ADDR_rt_trace_rw_tap_hdata 16 | ||
| 133 | |||
| 134 | /* Register r_redir, scope rt_trace, type r */ | ||
| 135 | typedef unsigned int reg_rt_trace_r_redir; | ||
| 136 | #define REG_RD_ADDR_rt_trace_r_redir 20 | ||
| 137 | |||
| 138 | |||
| 139 | /* Constants */ | ||
| 140 | enum { | ||
| 141 | regk_rt_trace_brk = 0x0000000c, | ||
| 142 | regk_rt_trace_dbg = 0x00000003, | ||
| 143 | regk_rt_trace_dbgdi = 0x00000004, | ||
| 144 | regk_rt_trace_dbgdo = 0x00000005, | ||
| 145 | regk_rt_trace_gmode = 0x00000000, | ||
| 146 | regk_rt_trace_no = 0x00000000, | ||
| 147 | regk_rt_trace_nop = 0x00000000, | ||
| 148 | regk_rt_trace_normal = 0x00000000, | ||
| 149 | regk_rt_trace_rdmem = 0x00000007, | ||
| 150 | regk_rt_trace_rdmemb = 0x00000009, | ||
| 151 | regk_rt_trace_rdpreg = 0x00000002, | ||
| 152 | regk_rt_trace_rdreg = 0x00000001, | ||
| 153 | regk_rt_trace_rdsreg = 0x00000003, | ||
| 154 | regk_rt_trace_redir = 0x00000006, | ||
| 155 | regk_rt_trace_ret = 0x0000000b, | ||
| 156 | regk_rt_trace_rw_cfg_default = 0x00000000, | ||
| 157 | regk_rt_trace_trcfg = 0x00000001, | ||
| 158 | regk_rt_trace_wp = 0x00000001, | ||
| 159 | regk_rt_trace_wp0 = 0x00000001, | ||
| 160 | regk_rt_trace_wp1 = 0x00000002, | ||
| 161 | regk_rt_trace_wp2 = 0x00000004, | ||
| 162 | regk_rt_trace_wp3 = 0x00000008, | ||
| 163 | regk_rt_trace_wp4 = 0x00000010, | ||
| 164 | regk_rt_trace_wp5 = 0x00000020, | ||
| 165 | regk_rt_trace_wp6 = 0x00000040, | ||
| 166 | regk_rt_trace_wrmem = 0x00000008, | ||
| 167 | regk_rt_trace_wrmemb = 0x0000000a, | ||
| 168 | regk_rt_trace_wrpreg = 0x00000005, | ||
| 169 | regk_rt_trace_wrreg = 0x00000004, | ||
| 170 | regk_rt_trace_wrsreg = 0x00000006, | ||
| 171 | regk_rt_trace_yes = 0x00000001 | ||
| 172 | }; | ||
| 173 | #endif /* __rt_trace_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/ser_defs.h b/include/asm-cris/arch-v32/hwregs/ser_defs.h deleted file mode 100644 index 01c2fab97d43..000000000000 --- a/include/asm-cris/arch-v32/hwregs/ser_defs.h +++ /dev/null | |||
| @@ -1,308 +0,0 @@ | |||
| 1 | #ifndef __ser_defs_h | ||
| 2 | #define __ser_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/ser/rtl/ser_regs.r | ||
| 7 | * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:21 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r | ||
| 11 | * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope ser */ | ||
| 86 | |||
| 87 | /* Register rw_tr_ctrl, scope ser, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int base_freq : 3; | ||
| 90 | unsigned int en : 1; | ||
| 91 | unsigned int par : 2; | ||
| 92 | unsigned int par_en : 1; | ||
| 93 | unsigned int data_bits : 1; | ||
| 94 | unsigned int stop_bits : 1; | ||
| 95 | unsigned int stop : 1; | ||
| 96 | unsigned int rts_delay : 3; | ||
| 97 | unsigned int rts_setup : 1; | ||
| 98 | unsigned int auto_rts : 1; | ||
| 99 | unsigned int txd : 1; | ||
| 100 | unsigned int auto_cts : 1; | ||
| 101 | unsigned int dummy1 : 15; | ||
| 102 | } reg_ser_rw_tr_ctrl; | ||
| 103 | #define REG_RD_ADDR_ser_rw_tr_ctrl 0 | ||
| 104 | #define REG_WR_ADDR_ser_rw_tr_ctrl 0 | ||
| 105 | |||
| 106 | /* Register rw_tr_dma_en, scope ser, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int en : 1; | ||
| 109 | unsigned int dummy1 : 31; | ||
| 110 | } reg_ser_rw_tr_dma_en; | ||
| 111 | #define REG_RD_ADDR_ser_rw_tr_dma_en 4 | ||
| 112 | #define REG_WR_ADDR_ser_rw_tr_dma_en 4 | ||
| 113 | |||
| 114 | /* Register rw_rec_ctrl, scope ser, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int base_freq : 3; | ||
| 117 | unsigned int en : 1; | ||
| 118 | unsigned int par : 2; | ||
| 119 | unsigned int par_en : 1; | ||
| 120 | unsigned int data_bits : 1; | ||
| 121 | unsigned int dma_mode : 1; | ||
| 122 | unsigned int dma_err : 1; | ||
| 123 | unsigned int sampling : 1; | ||
| 124 | unsigned int timeout : 3; | ||
| 125 | unsigned int auto_eop : 1; | ||
| 126 | unsigned int half_duplex : 1; | ||
| 127 | unsigned int rts_n : 1; | ||
| 128 | unsigned int loopback : 1; | ||
| 129 | unsigned int dummy1 : 14; | ||
| 130 | } reg_ser_rw_rec_ctrl; | ||
| 131 | #define REG_RD_ADDR_ser_rw_rec_ctrl 8 | ||
| 132 | #define REG_WR_ADDR_ser_rw_rec_ctrl 8 | ||
| 133 | |||
| 134 | /* Register rw_tr_baud_div, scope ser, type rw */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int div : 16; | ||
| 137 | unsigned int dummy1 : 16; | ||
| 138 | } reg_ser_rw_tr_baud_div; | ||
| 139 | #define REG_RD_ADDR_ser_rw_tr_baud_div 12 | ||
| 140 | #define REG_WR_ADDR_ser_rw_tr_baud_div 12 | ||
| 141 | |||
| 142 | /* Register rw_rec_baud_div, scope ser, type rw */ | ||
| 143 | typedef struct { | ||
| 144 | unsigned int div : 16; | ||
| 145 | unsigned int dummy1 : 16; | ||
| 146 | } reg_ser_rw_rec_baud_div; | ||
| 147 | #define REG_RD_ADDR_ser_rw_rec_baud_div 16 | ||
| 148 | #define REG_WR_ADDR_ser_rw_rec_baud_div 16 | ||
| 149 | |||
| 150 | /* Register rw_xoff, scope ser, type rw */ | ||
| 151 | typedef struct { | ||
| 152 | unsigned int chr : 8; | ||
| 153 | unsigned int automatic : 1; | ||
| 154 | unsigned int dummy1 : 23; | ||
| 155 | } reg_ser_rw_xoff; | ||
| 156 | #define REG_RD_ADDR_ser_rw_xoff 20 | ||
| 157 | #define REG_WR_ADDR_ser_rw_xoff 20 | ||
| 158 | |||
| 159 | /* Register rw_xoff_clr, scope ser, type rw */ | ||
| 160 | typedef struct { | ||
| 161 | unsigned int clr : 1; | ||
| 162 | unsigned int dummy1 : 31; | ||
| 163 | } reg_ser_rw_xoff_clr; | ||
| 164 | #define REG_RD_ADDR_ser_rw_xoff_clr 24 | ||
| 165 | #define REG_WR_ADDR_ser_rw_xoff_clr 24 | ||
| 166 | |||
| 167 | /* Register rw_dout, scope ser, type rw */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int data : 8; | ||
| 170 | unsigned int dummy1 : 24; | ||
| 171 | } reg_ser_rw_dout; | ||
| 172 | #define REG_RD_ADDR_ser_rw_dout 28 | ||
| 173 | #define REG_WR_ADDR_ser_rw_dout 28 | ||
| 174 | |||
| 175 | /* Register rs_stat_din, scope ser, type rs */ | ||
| 176 | typedef struct { | ||
| 177 | unsigned int data : 8; | ||
| 178 | unsigned int dummy1 : 8; | ||
| 179 | unsigned int dav : 1; | ||
| 180 | unsigned int framing_err : 1; | ||
| 181 | unsigned int par_err : 1; | ||
| 182 | unsigned int orun : 1; | ||
| 183 | unsigned int rec_err : 1; | ||
| 184 | unsigned int rxd : 1; | ||
| 185 | unsigned int tr_idle : 1; | ||
| 186 | unsigned int tr_empty : 1; | ||
| 187 | unsigned int tr_rdy : 1; | ||
| 188 | unsigned int cts_n : 1; | ||
| 189 | unsigned int xoff_detect : 1; | ||
| 190 | unsigned int rts_n : 1; | ||
| 191 | unsigned int txd : 1; | ||
| 192 | unsigned int dummy2 : 3; | ||
| 193 | } reg_ser_rs_stat_din; | ||
| 194 | #define REG_RD_ADDR_ser_rs_stat_din 32 | ||
| 195 | |||
| 196 | /* Register r_stat_din, scope ser, type r */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int data : 8; | ||
| 199 | unsigned int dummy1 : 8; | ||
| 200 | unsigned int dav : 1; | ||
| 201 | unsigned int framing_err : 1; | ||
| 202 | unsigned int par_err : 1; | ||
| 203 | unsigned int orun : 1; | ||
| 204 | unsigned int rec_err : 1; | ||
| 205 | unsigned int rxd : 1; | ||
| 206 | unsigned int tr_idle : 1; | ||
| 207 | unsigned int tr_empty : 1; | ||
| 208 | unsigned int tr_rdy : 1; | ||
| 209 | unsigned int cts_n : 1; | ||
| 210 | unsigned int xoff_detect : 1; | ||
| 211 | unsigned int rts_n : 1; | ||
| 212 | unsigned int txd : 1; | ||
| 213 | unsigned int dummy2 : 3; | ||
| 214 | } reg_ser_r_stat_din; | ||
| 215 | #define REG_RD_ADDR_ser_r_stat_din 36 | ||
| 216 | |||
| 217 | /* Register rw_rec_eop, scope ser, type rw */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int set : 1; | ||
| 220 | unsigned int dummy1 : 31; | ||
| 221 | } reg_ser_rw_rec_eop; | ||
| 222 | #define REG_RD_ADDR_ser_rw_rec_eop 40 | ||
| 223 | #define REG_WR_ADDR_ser_rw_rec_eop 40 | ||
| 224 | |||
| 225 | /* Register rw_intr_mask, scope ser, type rw */ | ||
| 226 | typedef struct { | ||
| 227 | unsigned int tr_rdy : 1; | ||
| 228 | unsigned int tr_empty : 1; | ||
| 229 | unsigned int tr_idle : 1; | ||
| 230 | unsigned int dav : 1; | ||
| 231 | unsigned int dummy1 : 28; | ||
| 232 | } reg_ser_rw_intr_mask; | ||
| 233 | #define REG_RD_ADDR_ser_rw_intr_mask 44 | ||
| 234 | #define REG_WR_ADDR_ser_rw_intr_mask 44 | ||
| 235 | |||
| 236 | /* Register rw_ack_intr, scope ser, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int tr_rdy : 1; | ||
| 239 | unsigned int tr_empty : 1; | ||
| 240 | unsigned int tr_idle : 1; | ||
| 241 | unsigned int dav : 1; | ||
| 242 | unsigned int dummy1 : 28; | ||
| 243 | } reg_ser_rw_ack_intr; | ||
| 244 | #define REG_RD_ADDR_ser_rw_ack_intr 48 | ||
| 245 | #define REG_WR_ADDR_ser_rw_ack_intr 48 | ||
| 246 | |||
| 247 | /* Register r_intr, scope ser, type r */ | ||
| 248 | typedef struct { | ||
| 249 | unsigned int tr_rdy : 1; | ||
| 250 | unsigned int tr_empty : 1; | ||
| 251 | unsigned int tr_idle : 1; | ||
| 252 | unsigned int dav : 1; | ||
| 253 | unsigned int dummy1 : 28; | ||
| 254 | } reg_ser_r_intr; | ||
| 255 | #define REG_RD_ADDR_ser_r_intr 52 | ||
| 256 | |||
| 257 | /* Register r_masked_intr, scope ser, type r */ | ||
| 258 | typedef struct { | ||
| 259 | unsigned int tr_rdy : 1; | ||
| 260 | unsigned int tr_empty : 1; | ||
| 261 | unsigned int tr_idle : 1; | ||
| 262 | unsigned int dav : 1; | ||
| 263 | unsigned int dummy1 : 28; | ||
| 264 | } reg_ser_r_masked_intr; | ||
| 265 | #define REG_RD_ADDR_ser_r_masked_intr 56 | ||
| 266 | |||
| 267 | |||
| 268 | /* Constants */ | ||
| 269 | enum { | ||
| 270 | regk_ser_active = 0x00000000, | ||
| 271 | regk_ser_bits1 = 0x00000000, | ||
| 272 | regk_ser_bits2 = 0x00000001, | ||
| 273 | regk_ser_bits7 = 0x00000001, | ||
| 274 | regk_ser_bits8 = 0x00000000, | ||
| 275 | regk_ser_del0_5 = 0x00000000, | ||
| 276 | regk_ser_del1 = 0x00000001, | ||
| 277 | regk_ser_del1_5 = 0x00000002, | ||
| 278 | regk_ser_del2 = 0x00000003, | ||
| 279 | regk_ser_del2_5 = 0x00000004, | ||
| 280 | regk_ser_del3 = 0x00000005, | ||
| 281 | regk_ser_del3_5 = 0x00000006, | ||
| 282 | regk_ser_del4 = 0x00000007, | ||
| 283 | regk_ser_even = 0x00000000, | ||
| 284 | regk_ser_ext = 0x00000001, | ||
| 285 | regk_ser_f100 = 0x00000007, | ||
| 286 | regk_ser_f29_493 = 0x00000004, | ||
| 287 | regk_ser_f32 = 0x00000005, | ||
| 288 | regk_ser_f32_768 = 0x00000006, | ||
| 289 | regk_ser_ignore = 0x00000001, | ||
| 290 | regk_ser_inactive = 0x00000001, | ||
| 291 | regk_ser_majority = 0x00000001, | ||
| 292 | regk_ser_mark = 0x00000002, | ||
| 293 | regk_ser_middle = 0x00000000, | ||
| 294 | regk_ser_no = 0x00000000, | ||
| 295 | regk_ser_odd = 0x00000001, | ||
| 296 | regk_ser_off = 0x00000000, | ||
| 297 | regk_ser_rw_intr_mask_default = 0x00000000, | ||
| 298 | regk_ser_rw_rec_baud_div_default = 0x00000000, | ||
| 299 | regk_ser_rw_rec_ctrl_default = 0x00010000, | ||
| 300 | regk_ser_rw_tr_baud_div_default = 0x00000000, | ||
| 301 | regk_ser_rw_tr_ctrl_default = 0x00008000, | ||
| 302 | regk_ser_rw_tr_dma_en_default = 0x00000000, | ||
| 303 | regk_ser_rw_xoff_default = 0x00000000, | ||
| 304 | regk_ser_space = 0x00000003, | ||
| 305 | regk_ser_stop = 0x00000000, | ||
| 306 | regk_ser_yes = 0x00000001 | ||
| 307 | }; | ||
| 308 | #endif /* __ser_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/sser_defs.h b/include/asm-cris/arch-v32/hwregs/sser_defs.h deleted file mode 100644 index 8d1dab218b91..000000000000 --- a/include/asm-cris/arch-v32/hwregs/sser_defs.h +++ /dev/null | |||
| @@ -1,331 +0,0 @@ | |||
| 1 | #ifndef __sser_defs_h | ||
| 2 | #define __sser_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/syncser/rtl/sser_regs.r | ||
| 7 | * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:48 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r | ||
| 11 | * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope sser */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope sser, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int clk_div : 16; | ||
| 90 | unsigned int base_freq : 3; | ||
| 91 | unsigned int gate_clk : 1; | ||
| 92 | unsigned int clkgate_ctrl : 1; | ||
| 93 | unsigned int clkgate_in : 1; | ||
| 94 | unsigned int clk_dir : 1; | ||
| 95 | unsigned int clk_od_mode : 1; | ||
| 96 | unsigned int out_clk_pol : 1; | ||
| 97 | unsigned int out_clk_src : 2; | ||
| 98 | unsigned int clk_in_sel : 1; | ||
| 99 | unsigned int hold_pol : 1; | ||
| 100 | unsigned int prepare : 1; | ||
| 101 | unsigned int en : 1; | ||
| 102 | unsigned int dummy1 : 1; | ||
| 103 | } reg_sser_rw_cfg; | ||
| 104 | #define REG_RD_ADDR_sser_rw_cfg 0 | ||
| 105 | #define REG_WR_ADDR_sser_rw_cfg 0 | ||
| 106 | |||
| 107 | /* Register rw_frm_cfg, scope sser, type rw */ | ||
| 108 | typedef struct { | ||
| 109 | unsigned int wordrate : 10; | ||
| 110 | unsigned int rec_delay : 3; | ||
| 111 | unsigned int tr_delay : 3; | ||
| 112 | unsigned int early_wend : 1; | ||
| 113 | unsigned int level : 2; | ||
| 114 | unsigned int type : 1; | ||
| 115 | unsigned int clk_pol : 1; | ||
| 116 | unsigned int fr_in_rxclk : 1; | ||
| 117 | unsigned int clk_src : 1; | ||
| 118 | unsigned int out_off : 1; | ||
| 119 | unsigned int out_on : 1; | ||
| 120 | unsigned int frame_pin_dir : 1; | ||
| 121 | unsigned int frame_pin_use : 2; | ||
| 122 | unsigned int status_pin_dir : 1; | ||
| 123 | unsigned int status_pin_use : 2; | ||
| 124 | unsigned int dummy1 : 1; | ||
| 125 | } reg_sser_rw_frm_cfg; | ||
| 126 | #define REG_RD_ADDR_sser_rw_frm_cfg 4 | ||
| 127 | #define REG_WR_ADDR_sser_rw_frm_cfg 4 | ||
| 128 | |||
| 129 | /* Register rw_tr_cfg, scope sser, type rw */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int tr_en : 1; | ||
| 132 | unsigned int stop : 1; | ||
| 133 | unsigned int urun_stop : 1; | ||
| 134 | unsigned int eop_stop : 1; | ||
| 135 | unsigned int sample_size : 6; | ||
| 136 | unsigned int sh_dir : 1; | ||
| 137 | unsigned int clk_pol : 1; | ||
| 138 | unsigned int clk_src : 1; | ||
| 139 | unsigned int use_dma : 1; | ||
| 140 | unsigned int mode : 2; | ||
| 141 | unsigned int frm_src : 1; | ||
| 142 | unsigned int use60958 : 1; | ||
| 143 | unsigned int iec60958_ckdiv : 2; | ||
| 144 | unsigned int rate_ctrl : 1; | ||
| 145 | unsigned int use_md : 1; | ||
| 146 | unsigned int dual_i2s : 1; | ||
| 147 | unsigned int data_pin_use : 2; | ||
| 148 | unsigned int od_mode : 1; | ||
| 149 | unsigned int bulk_wspace : 2; | ||
| 150 | unsigned int dummy1 : 4; | ||
| 151 | } reg_sser_rw_tr_cfg; | ||
| 152 | #define REG_RD_ADDR_sser_rw_tr_cfg 8 | ||
| 153 | #define REG_WR_ADDR_sser_rw_tr_cfg 8 | ||
| 154 | |||
| 155 | /* Register rw_rec_cfg, scope sser, type rw */ | ||
| 156 | typedef struct { | ||
| 157 | unsigned int rec_en : 1; | ||
| 158 | unsigned int force_eop : 1; | ||
| 159 | unsigned int stop : 1; | ||
| 160 | unsigned int orun_stop : 1; | ||
| 161 | unsigned int eop_stop : 1; | ||
| 162 | unsigned int sample_size : 6; | ||
| 163 | unsigned int sh_dir : 1; | ||
| 164 | unsigned int clk_pol : 1; | ||
| 165 | unsigned int clk_src : 1; | ||
| 166 | unsigned int use_dma : 1; | ||
| 167 | unsigned int mode : 2; | ||
| 168 | unsigned int frm_src : 2; | ||
| 169 | unsigned int use60958 : 1; | ||
| 170 | unsigned int iec60958_ui_len : 5; | ||
| 171 | unsigned int slave2_en : 1; | ||
| 172 | unsigned int slave3_en : 1; | ||
| 173 | unsigned int fifo_thr : 2; | ||
| 174 | unsigned int dummy1 : 3; | ||
| 175 | } reg_sser_rw_rec_cfg; | ||
| 176 | #define REG_RD_ADDR_sser_rw_rec_cfg 12 | ||
| 177 | #define REG_WR_ADDR_sser_rw_rec_cfg 12 | ||
| 178 | |||
| 179 | /* Register rw_tr_data, scope sser, type rw */ | ||
| 180 | typedef struct { | ||
| 181 | unsigned int data : 16; | ||
| 182 | unsigned int md : 1; | ||
| 183 | unsigned int dummy1 : 15; | ||
| 184 | } reg_sser_rw_tr_data; | ||
| 185 | #define REG_RD_ADDR_sser_rw_tr_data 16 | ||
| 186 | #define REG_WR_ADDR_sser_rw_tr_data 16 | ||
| 187 | |||
| 188 | /* Register r_rec_data, scope sser, type r */ | ||
| 189 | typedef struct { | ||
| 190 | unsigned int data : 16; | ||
| 191 | unsigned int md : 1; | ||
| 192 | unsigned int ext_clk : 1; | ||
| 193 | unsigned int status_in : 1; | ||
| 194 | unsigned int frame_in : 1; | ||
| 195 | unsigned int din : 1; | ||
| 196 | unsigned int data_in : 1; | ||
| 197 | unsigned int clk_in : 1; | ||
| 198 | unsigned int dummy1 : 9; | ||
| 199 | } reg_sser_r_rec_data; | ||
| 200 | #define REG_RD_ADDR_sser_r_rec_data 20 | ||
| 201 | |||
| 202 | /* Register rw_extra, scope sser, type rw */ | ||
| 203 | typedef struct { | ||
| 204 | unsigned int clkoff_cycles : 20; | ||
| 205 | unsigned int clkoff_en : 1; | ||
| 206 | unsigned int clkon_en : 1; | ||
| 207 | unsigned int dout_delay : 5; | ||
| 208 | unsigned int dummy1 : 5; | ||
| 209 | } reg_sser_rw_extra; | ||
| 210 | #define REG_RD_ADDR_sser_rw_extra 24 | ||
| 211 | #define REG_WR_ADDR_sser_rw_extra 24 | ||
| 212 | |||
| 213 | /* Register rw_intr_mask, scope sser, type rw */ | ||
| 214 | typedef struct { | ||
| 215 | unsigned int trdy : 1; | ||
| 216 | unsigned int rdav : 1; | ||
| 217 | unsigned int tidle : 1; | ||
| 218 | unsigned int rstop : 1; | ||
| 219 | unsigned int urun : 1; | ||
| 220 | unsigned int orun : 1; | ||
| 221 | unsigned int md_rec : 1; | ||
| 222 | unsigned int md_sent : 1; | ||
| 223 | unsigned int r958err : 1; | ||
| 224 | unsigned int dummy1 : 23; | ||
| 225 | } reg_sser_rw_intr_mask; | ||
| 226 | #define REG_RD_ADDR_sser_rw_intr_mask 28 | ||
| 227 | #define REG_WR_ADDR_sser_rw_intr_mask 28 | ||
| 228 | |||
| 229 | /* Register rw_ack_intr, scope sser, type rw */ | ||
| 230 | typedef struct { | ||
| 231 | unsigned int trdy : 1; | ||
| 232 | unsigned int rdav : 1; | ||
| 233 | unsigned int tidle : 1; | ||
| 234 | unsigned int rstop : 1; | ||
| 235 | unsigned int urun : 1; | ||
| 236 | unsigned int orun : 1; | ||
| 237 | unsigned int md_rec : 1; | ||
| 238 | unsigned int md_sent : 1; | ||
| 239 | unsigned int r958err : 1; | ||
| 240 | unsigned int dummy1 : 23; | ||
| 241 | } reg_sser_rw_ack_intr; | ||
| 242 | #define REG_RD_ADDR_sser_rw_ack_intr 32 | ||
| 243 | #define REG_WR_ADDR_sser_rw_ack_intr 32 | ||
| 244 | |||
| 245 | /* Register r_intr, scope sser, type r */ | ||
| 246 | typedef struct { | ||
| 247 | unsigned int trdy : 1; | ||
| 248 | unsigned int rdav : 1; | ||
| 249 | unsigned int tidle : 1; | ||
| 250 | unsigned int rstop : 1; | ||
| 251 | unsigned int urun : 1; | ||
| 252 | unsigned int orun : 1; | ||
| 253 | unsigned int md_rec : 1; | ||
| 254 | unsigned int md_sent : 1; | ||
| 255 | unsigned int r958err : 1; | ||
| 256 | unsigned int dummy1 : 23; | ||
| 257 | } reg_sser_r_intr; | ||
| 258 | #define REG_RD_ADDR_sser_r_intr 36 | ||
| 259 | |||
| 260 | /* Register r_masked_intr, scope sser, type r */ | ||
| 261 | typedef struct { | ||
| 262 | unsigned int trdy : 1; | ||
| 263 | unsigned int rdav : 1; | ||
| 264 | unsigned int tidle : 1; | ||
| 265 | unsigned int rstop : 1; | ||
| 266 | unsigned int urun : 1; | ||
| 267 | unsigned int orun : 1; | ||
| 268 | unsigned int md_rec : 1; | ||
| 269 | unsigned int md_sent : 1; | ||
| 270 | unsigned int r958err : 1; | ||
| 271 | unsigned int dummy1 : 23; | ||
| 272 | } reg_sser_r_masked_intr; | ||
| 273 | #define REG_RD_ADDR_sser_r_masked_intr 40 | ||
| 274 | |||
| 275 | |||
| 276 | /* Constants */ | ||
| 277 | enum { | ||
| 278 | regk_sser_both = 0x00000002, | ||
| 279 | regk_sser_bulk = 0x00000001, | ||
| 280 | regk_sser_clk100 = 0x00000000, | ||
| 281 | regk_sser_clk_in = 0x00000000, | ||
| 282 | regk_sser_const0 = 0x00000003, | ||
| 283 | regk_sser_dout = 0x00000002, | ||
| 284 | regk_sser_edge = 0x00000000, | ||
| 285 | regk_sser_ext = 0x00000001, | ||
| 286 | regk_sser_ext_clk = 0x00000001, | ||
| 287 | regk_sser_f100 = 0x00000000, | ||
| 288 | regk_sser_f29_493 = 0x00000004, | ||
| 289 | regk_sser_f32 = 0x00000005, | ||
| 290 | regk_sser_f32_768 = 0x00000006, | ||
| 291 | regk_sser_frm = 0x00000003, | ||
| 292 | regk_sser_gio0 = 0x00000000, | ||
| 293 | regk_sser_gio1 = 0x00000001, | ||
| 294 | regk_sser_hispeed = 0x00000001, | ||
| 295 | regk_sser_hold = 0x00000002, | ||
| 296 | regk_sser_in = 0x00000000, | ||
| 297 | regk_sser_inf = 0x00000003, | ||
| 298 | regk_sser_intern = 0x00000000, | ||
| 299 | regk_sser_intern_clk = 0x00000001, | ||
| 300 | regk_sser_intern_tb = 0x00000000, | ||
| 301 | regk_sser_iso = 0x00000000, | ||
| 302 | regk_sser_level = 0x00000001, | ||
| 303 | regk_sser_lospeed = 0x00000000, | ||
| 304 | regk_sser_lsbfirst = 0x00000000, | ||
| 305 | regk_sser_msbfirst = 0x00000001, | ||
| 306 | regk_sser_neg = 0x00000001, | ||
| 307 | regk_sser_neg_lo = 0x00000000, | ||
| 308 | regk_sser_no = 0x00000000, | ||
| 309 | regk_sser_no_clk = 0x00000007, | ||
| 310 | regk_sser_nojitter = 0x00000002, | ||
| 311 | regk_sser_out = 0x00000001, | ||
| 312 | regk_sser_pos = 0x00000000, | ||
| 313 | regk_sser_pos_hi = 0x00000001, | ||
| 314 | regk_sser_rec = 0x00000000, | ||
| 315 | regk_sser_rw_cfg_default = 0x00000000, | ||
| 316 | regk_sser_rw_extra_default = 0x00000000, | ||
| 317 | regk_sser_rw_frm_cfg_default = 0x00000000, | ||
| 318 | regk_sser_rw_intr_mask_default = 0x00000000, | ||
| 319 | regk_sser_rw_rec_cfg_default = 0x00000000, | ||
| 320 | regk_sser_rw_tr_cfg_default = 0x01800000, | ||
| 321 | regk_sser_rw_tr_data_default = 0x00000000, | ||
| 322 | regk_sser_thr16 = 0x00000001, | ||
| 323 | regk_sser_thr32 = 0x00000002, | ||
| 324 | regk_sser_thr8 = 0x00000000, | ||
| 325 | regk_sser_tr = 0x00000001, | ||
| 326 | regk_sser_ts_out = 0x00000003, | ||
| 327 | regk_sser_tx_bulk = 0x00000002, | ||
| 328 | regk_sser_wiresave = 0x00000002, | ||
| 329 | regk_sser_yes = 0x00000001 | ||
| 330 | }; | ||
| 331 | #endif /* __sser_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/strcop.h b/include/asm-cris/arch-v32/hwregs/strcop.h deleted file mode 100644 index 35131ba466f3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strcop.h +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | // $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $ | ||
| 2 | |||
| 3 | // Streamcop meta-data configuration structs | ||
| 4 | |||
| 5 | struct strcop_meta_out { | ||
| 6 | unsigned char csumsel : 3; | ||
| 7 | unsigned char ciphsel : 3; | ||
| 8 | unsigned char ciphconf : 2; | ||
| 9 | unsigned char hashsel : 3; | ||
| 10 | unsigned char hashconf : 1; | ||
| 11 | unsigned char hashmode : 1; | ||
| 12 | unsigned char decrypt : 1; | ||
| 13 | unsigned char dlkey : 1; | ||
| 14 | unsigned char cbcmode : 1; | ||
| 15 | }; | ||
| 16 | |||
| 17 | struct strcop_meta_in { | ||
| 18 | unsigned char dmasel : 3; | ||
| 19 | unsigned char sync : 1; | ||
| 20 | unsigned char res1 : 5; | ||
| 21 | unsigned char res2; | ||
| 22 | }; | ||
| 23 | |||
| 24 | // Source definitions | ||
| 25 | |||
| 26 | enum { | ||
| 27 | src_none = 0, | ||
| 28 | src_dma = 1, | ||
| 29 | src_des = 2, | ||
| 30 | src_sha1 = 3, | ||
| 31 | src_csum = 4, | ||
| 32 | src_aes = 5, | ||
| 33 | src_md5 = 6, | ||
| 34 | src_res = 7 | ||
| 35 | }; | ||
| 36 | |||
| 37 | // Cipher definitions | ||
| 38 | |||
| 39 | enum { | ||
| 40 | ciph_des = 0, | ||
| 41 | ciph_3des = 1, | ||
| 42 | ciph_aes = 2 | ||
| 43 | }; | ||
| 44 | |||
| 45 | // Hash definitions | ||
| 46 | |||
| 47 | enum { | ||
| 48 | hash_sha1 = 0, | ||
| 49 | hash_md5 = 1 | ||
| 50 | }; | ||
| 51 | |||
| 52 | enum { | ||
| 53 | hash_noiv = 0, | ||
| 54 | hash_iv = 1 | ||
| 55 | }; | ||
| 56 | |||
| 57 | |||
diff --git a/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/include/asm-cris/arch-v32/hwregs/strcop_defs.h deleted file mode 100644 index bd145a49b2c4..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strcop_defs.h +++ /dev/null | |||
| @@ -1,109 +0,0 @@ | |||
| 1 | #ifndef __strcop_defs_h | ||
| 2 | #define __strcop_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/strcop/rtl/strcop_regs.r | ||
| 7 | * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:38 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r | ||
| 11 | * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope strcop */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope strcop, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int td3 : 1; | ||
| 90 | unsigned int td2 : 1; | ||
| 91 | unsigned int td1 : 1; | ||
| 92 | unsigned int ipend : 1; | ||
| 93 | unsigned int ignore_sync : 1; | ||
| 94 | unsigned int en : 1; | ||
| 95 | unsigned int dummy1 : 26; | ||
| 96 | } reg_strcop_rw_cfg; | ||
| 97 | #define REG_RD_ADDR_strcop_rw_cfg 0 | ||
| 98 | #define REG_WR_ADDR_strcop_rw_cfg 0 | ||
| 99 | |||
| 100 | |||
| 101 | /* Constants */ | ||
| 102 | enum { | ||
| 103 | regk_strcop_big = 0x00000001, | ||
| 104 | regk_strcop_d = 0x00000001, | ||
| 105 | regk_strcop_e = 0x00000000, | ||
| 106 | regk_strcop_little = 0x00000000, | ||
| 107 | regk_strcop_rw_cfg_default = 0x00000002 | ||
| 108 | }; | ||
| 109 | #endif /* __strcop_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/hwregs/strmux_defs.h deleted file mode 100644 index 67474855c499..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strmux_defs.h +++ /dev/null | |||
| @@ -1,127 +0,0 @@ | |||
| 1 | #ifndef __strmux_defs_h | ||
| 2 | #define __strmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/strmux/rtl/guinness/strmux_regs.r | ||
| 7 | * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:43 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r | ||
| 11 | * id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope strmux */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope strmux, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int dma0 : 3; | ||
| 90 | unsigned int dma1 : 3; | ||
| 91 | unsigned int dma2 : 3; | ||
| 92 | unsigned int dma3 : 3; | ||
| 93 | unsigned int dma4 : 3; | ||
| 94 | unsigned int dma5 : 3; | ||
| 95 | unsigned int dma6 : 3; | ||
| 96 | unsigned int dma7 : 3; | ||
| 97 | unsigned int dma8 : 3; | ||
| 98 | unsigned int dma9 : 3; | ||
| 99 | unsigned int dummy1 : 2; | ||
| 100 | } reg_strmux_rw_cfg; | ||
| 101 | #define REG_RD_ADDR_strmux_rw_cfg 0 | ||
| 102 | #define REG_WR_ADDR_strmux_rw_cfg 0 | ||
| 103 | |||
| 104 | |||
| 105 | /* Constants */ | ||
| 106 | enum { | ||
| 107 | regk_strmux_ata = 0x00000003, | ||
| 108 | regk_strmux_eth0 = 0x00000001, | ||
| 109 | regk_strmux_eth1 = 0x00000004, | ||
| 110 | regk_strmux_ext0 = 0x00000001, | ||
| 111 | regk_strmux_ext1 = 0x00000001, | ||
| 112 | regk_strmux_ext2 = 0x00000001, | ||
| 113 | regk_strmux_ext3 = 0x00000001, | ||
| 114 | regk_strmux_iop0 = 0x00000002, | ||
| 115 | regk_strmux_iop1 = 0x00000001, | ||
| 116 | regk_strmux_off = 0x00000000, | ||
| 117 | regk_strmux_p21 = 0x00000004, | ||
| 118 | regk_strmux_rw_cfg_default = 0x00000000, | ||
| 119 | regk_strmux_ser0 = 0x00000002, | ||
| 120 | regk_strmux_ser1 = 0x00000002, | ||
| 121 | regk_strmux_ser2 = 0x00000004, | ||
| 122 | regk_strmux_ser3 = 0x00000003, | ||
| 123 | regk_strmux_sser0 = 0x00000003, | ||
| 124 | regk_strmux_sser1 = 0x00000003, | ||
| 125 | regk_strmux_strcop = 0x00000002 | ||
| 126 | }; | ||
| 127 | #endif /* __strmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/supp_reg.h b/include/asm-cris/arch-v32/hwregs/supp_reg.h deleted file mode 100644 index ffe49625ae36..000000000000 --- a/include/asm-cris/arch-v32/hwregs/supp_reg.h +++ /dev/null | |||
| @@ -1,78 +0,0 @@ | |||
| 1 | #ifndef __SUPP_REG_H__ | ||
| 2 | #define __SUPP_REG_H__ | ||
| 3 | |||
| 4 | /* Macros for reading and writing support/special registers. */ | ||
| 5 | |||
| 6 | #ifndef STRINGIFYFY | ||
| 7 | #define STRINGIFYFY(i) #i | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #ifndef STRINGIFY | ||
| 11 | #define STRINGIFY(i) STRINGIFYFY(i) | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #define SPEC_REG_BZ "BZ" | ||
| 15 | #define SPEC_REG_VR "VR" | ||
| 16 | #define SPEC_REG_PID "PID" | ||
| 17 | #define SPEC_REG_SRS "SRS" | ||
| 18 | #define SPEC_REG_WZ "WZ" | ||
| 19 | #define SPEC_REG_EXS "EXS" | ||
| 20 | #define SPEC_REG_EDA "EDA" | ||
| 21 | #define SPEC_REG_MOF "MOF" | ||
| 22 | #define SPEC_REG_DZ "DZ" | ||
| 23 | #define SPEC_REG_EBP "EBP" | ||
| 24 | #define SPEC_REG_ERP "ERP" | ||
| 25 | #define SPEC_REG_SRP "SRP" | ||
| 26 | #define SPEC_REG_NRP "NRP" | ||
| 27 | #define SPEC_REG_CCS "CCS" | ||
| 28 | #define SPEC_REG_USP "USP" | ||
| 29 | #define SPEC_REG_SPC "SPC" | ||
| 30 | |||
| 31 | #define RW_MM_CFG 0 | ||
| 32 | #define RW_MM_KBASE_LO 1 | ||
| 33 | #define RW_MM_KBASE_HI 2 | ||
| 34 | #define RW_MM_CAUSE 3 | ||
| 35 | #define RW_MM_TLB_SEL 4 | ||
| 36 | #define RW_MM_TLB_LO 5 | ||
| 37 | #define RW_MM_TLB_HI 6 | ||
| 38 | #define RW_MM_TLB_PGD 7 | ||
| 39 | |||
| 40 | #define BANK_GC 0 | ||
| 41 | #define BANK_IM 1 | ||
| 42 | #define BANK_DM 2 | ||
| 43 | #define BANK_BP 3 | ||
| 44 | |||
| 45 | #define RW_GC_CFG 0 | ||
| 46 | #define RW_GC_CCS 1 | ||
| 47 | #define RW_GC_SRS 2 | ||
| 48 | #define RW_GC_NRP 3 | ||
| 49 | #define RW_GC_EXS 4 | ||
| 50 | #define RW_GC_R0 8 | ||
| 51 | #define RW_GC_R1 9 | ||
| 52 | |||
| 53 | #define SPEC_REG_WR(r,v) \ | ||
| 54 | __asm__ __volatile__ ("move %0, $" r : : "r" (v)); | ||
| 55 | |||
| 56 | #define SPEC_REG_RD(r,v) \ | ||
| 57 | __asm__ __volatile__ ("move $" r ",%0" : "=r" (v)); | ||
| 58 | |||
| 59 | #define NOP() \ | ||
| 60 | __asm__ __volatile__ ("nop"); | ||
| 61 | |||
| 62 | #define SUPP_BANK_SEL(b) \ | ||
| 63 | SPEC_REG_WR(SPEC_REG_SRS,b); \ | ||
| 64 | NOP(); \ | ||
| 65 | NOP(); \ | ||
| 66 | NOP(); | ||
| 67 | |||
| 68 | #define SUPP_REG_WR(r,v) \ | ||
| 69 | __asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \ | ||
| 70 | "nop\n\t" \ | ||
| 71 | "nop\n\t" \ | ||
| 72 | "nop\n\t" \ | ||
| 73 | : : "r" (v)); | ||
| 74 | |||
| 75 | #define SUPP_REG_RD(r,v) \ | ||
| 76 | __asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v)); | ||
| 77 | |||
| 78 | #endif /* __SUPP_REG_H__ */ | ||
diff --git a/include/asm-cris/arch-v32/intmem.h b/include/asm-cris/arch-v32/intmem.h deleted file mode 100644 index c0ada33bf90f..000000000000 --- a/include/asm-cris/arch-v32/intmem.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_INTMEM_H | ||
| 2 | #define _ASM_CRIS_INTMEM_H | ||
| 3 | |||
| 4 | void* crisv32_intmem_alloc(unsigned size, unsigned align); | ||
| 5 | void crisv32_intmem_free(void* addr); | ||
| 6 | void* crisv32_intmem_phys_to_virt(unsigned long addr); | ||
| 7 | unsigned long crisv32_intmem_virt_to_phys(void *addr); | ||
| 8 | |||
| 9 | #endif /* _ASM_CRIS_ARCH_INTMEM_H */ | ||
diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h deleted file mode 100644 index 6b38912f29ba..000000000000 --- a/include/asm-cris/arch-v32/io.h +++ /dev/null | |||
| @@ -1,136 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_CRIS_IO_H | ||
| 2 | #define _ASM_ARCH_CRIS_IO_H | ||
| 3 | |||
| 4 | #include <linux/spinlock.h> | ||
| 5 | #include <hwregs/reg_map.h> | ||
| 6 | #include <hwregs/reg_rdwr.h> | ||
| 7 | #include <hwregs/gio_defs.h> | ||
| 8 | |||
| 9 | enum crisv32_io_dir | ||
| 10 | { | ||
| 11 | crisv32_io_dir_in = 0, | ||
| 12 | crisv32_io_dir_out = 1 | ||
| 13 | }; | ||
| 14 | |||
| 15 | struct crisv32_ioport | ||
| 16 | { | ||
| 17 | volatile unsigned long *oe; | ||
| 18 | volatile unsigned long *data; | ||
| 19 | volatile unsigned long *data_in; | ||
| 20 | unsigned int pin_count; | ||
| 21 | spinlock_t lock; | ||
| 22 | }; | ||
| 23 | |||
| 24 | struct crisv32_iopin | ||
| 25 | { | ||
| 26 | struct crisv32_ioport* port; | ||
| 27 | int bit; | ||
| 28 | }; | ||
| 29 | |||
| 30 | extern struct crisv32_ioport crisv32_ioports[]; | ||
| 31 | |||
| 32 | extern struct crisv32_iopin crisv32_led1_green; | ||
| 33 | extern struct crisv32_iopin crisv32_led1_red; | ||
| 34 | extern struct crisv32_iopin crisv32_led2_green; | ||
| 35 | extern struct crisv32_iopin crisv32_led2_red; | ||
| 36 | extern struct crisv32_iopin crisv32_led3_green; | ||
| 37 | extern struct crisv32_iopin crisv32_led3_red; | ||
| 38 | |||
| 39 | extern struct crisv32_iopin crisv32_led_net0_green; | ||
| 40 | extern struct crisv32_iopin crisv32_led_net0_red; | ||
| 41 | extern struct crisv32_iopin crisv32_led_net1_green; | ||
| 42 | extern struct crisv32_iopin crisv32_led_net1_red; | ||
| 43 | |||
| 44 | static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val) | ||
| 45 | { | ||
| 46 | long flags; | ||
| 47 | spin_lock_irqsave(&iopin->port->lock, flags); | ||
| 48 | |||
| 49 | if (val) | ||
| 50 | *iopin->port->data |= iopin->bit; | ||
| 51 | else | ||
| 52 | *iopin->port->data &= ~iopin->bit; | ||
| 53 | |||
| 54 | spin_unlock_irqrestore(&iopin->port->lock, flags); | ||
| 55 | } | ||
| 56 | |||
| 57 | static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, | ||
| 58 | enum crisv32_io_dir dir) | ||
| 59 | { | ||
| 60 | long flags; | ||
| 61 | spin_lock_irqsave(&iopin->port->lock, flags); | ||
| 62 | |||
| 63 | if (dir == crisv32_io_dir_in) | ||
| 64 | *iopin->port->oe &= ~iopin->bit; | ||
| 65 | else | ||
| 66 | *iopin->port->oe |= iopin->bit; | ||
| 67 | |||
| 68 | spin_unlock_irqrestore(&iopin->port->lock, flags); | ||
| 69 | } | ||
| 70 | |||
| 71 | static inline int crisv32_io_rd(struct crisv32_iopin* iopin) | ||
| 72 | { | ||
| 73 | return ((*iopin->port->data_in & iopin->bit) ? 1 : 0); | ||
| 74 | } | ||
| 75 | |||
| 76 | int crisv32_io_get(struct crisv32_iopin* iopin, | ||
| 77 | unsigned int port, unsigned int pin); | ||
| 78 | int crisv32_io_get_name(struct crisv32_iopin* iopin, | ||
| 79 | const char *name); | ||
| 80 | |||
| 81 | #define CRIS_LED_OFF 0x00 | ||
| 82 | #define CRIS_LED_GREEN 0x01 | ||
| 83 | #define CRIS_LED_RED 0x02 | ||
| 84 | #define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) | ||
| 85 | |||
| 86 | #if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) | ||
| 87 | #define CRIS_LED_NETWORK_GRP0_SET(x) \ | ||
| 88 | do { \ | ||
| 89 | CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \ | ||
| 90 | CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \ | ||
| 91 | } while (0) | ||
| 92 | #else | ||
| 93 | #define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {} | ||
| 94 | #endif | ||
| 95 | |||
| 96 | #define CRIS_LED_NETWORK_GRP0_SET_G(x) \ | ||
| 97 | crisv32_io_set(&crisv32_led_net0_green, !(x)); | ||
| 98 | |||
| 99 | #define CRIS_LED_NETWORK_GRP0_SET_R(x) \ | ||
| 100 | crisv32_io_set(&crisv32_led_net0_red, !(x)); | ||
| 101 | |||
| 102 | #if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO) | ||
| 103 | #define CRIS_LED_NETWORK_GRP1_SET(x) \ | ||
| 104 | do { \ | ||
| 105 | CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \ | ||
| 106 | CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \ | ||
| 107 | } while (0) | ||
| 108 | #else | ||
| 109 | #define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {} | ||
| 110 | #endif | ||
| 111 | |||
| 112 | #define CRIS_LED_NETWORK_GRP1_SET_G(x) \ | ||
| 113 | crisv32_io_set(&crisv32_led_net1_green, !(x)); | ||
| 114 | |||
| 115 | #define CRIS_LED_NETWORK_GRP1_SET_R(x) \ | ||
| 116 | crisv32_io_set(&crisv32_led_net1_red, !(x)); | ||
| 117 | |||
| 118 | #define CRIS_LED_ACTIVE_SET(x) \ | ||
| 119 | do { \ | ||
| 120 | CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ | ||
| 121 | CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ | ||
| 122 | } while (0) | ||
| 123 | |||
| 124 | #define CRIS_LED_ACTIVE_SET_G(x) \ | ||
| 125 | crisv32_io_set(&crisv32_led2_green, !(x)); | ||
| 126 | #define CRIS_LED_ACTIVE_SET_R(x) \ | ||
| 127 | crisv32_io_set(&crisv32_led2_red, !(x)); | ||
| 128 | #define CRIS_LED_DISK_WRITE(x) \ | ||
| 129 | do{\ | ||
| 130 | crisv32_io_set(&crisv32_led3_green, !(x)); \ | ||
| 131 | crisv32_io_set(&crisv32_led3_red, !(x)); \ | ||
| 132 | }while(0) | ||
| 133 | #define CRIS_LED_DISK_READ(x) \ | ||
| 134 | crisv32_io_set(&crisv32_led3_green, !(x)); | ||
| 135 | |||
| 136 | #endif | ||
diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h deleted file mode 100644 index 9e4c9fbdfddf..000000000000 --- a/include/asm-cris/arch-v32/irq.h +++ /dev/null | |||
| @@ -1,124 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_IRQ_H | ||
| 2 | #define _ASM_ARCH_IRQ_H | ||
| 3 | |||
| 4 | #include <hwregs/intr_vect.h> | ||
| 5 | |||
| 6 | /* Number of non-cpu interrupts. */ | ||
| 7 | #define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */ | ||
| 8 | #define FIRST_IRQ 0x31 /* Exception number for first IRQ */ | ||
| 9 | #define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */ | ||
| 10 | #if NR_REAL_IRQS > 32 | ||
| 11 | #define MACH_IRQS 64 | ||
| 12 | #else | ||
| 13 | #define MACH_IRQS 32 | ||
| 14 | #endif | ||
| 15 | |||
| 16 | #ifndef __ASSEMBLY__ | ||
| 17 | /* Global IRQ vector. */ | ||
| 18 | typedef void (*irqvectptr)(void); | ||
| 19 | |||
| 20 | struct etrax_interrupt_vector { | ||
| 21 | irqvectptr v[256]; | ||
| 22 | }; | ||
| 23 | |||
| 24 | extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ | ||
| 25 | |||
| 26 | void mask_irq(int irq); | ||
| 27 | void unmask_irq(int irq); | ||
| 28 | |||
| 29 | void set_exception_vector(int n, irqvectptr addr); | ||
| 30 | |||
| 31 | /* Save registers so that they match pt_regs. */ | ||
| 32 | #define SAVE_ALL \ | ||
| 33 | "subq 12,$sp\n\t" \ | ||
| 34 | "move $erp,[$sp]\n\t" \ | ||
| 35 | "subq 4,$sp\n\t" \ | ||
| 36 | "move $srp,[$sp]\n\t" \ | ||
| 37 | "subq 4,$sp\n\t" \ | ||
| 38 | "move $ccs,[$sp]\n\t" \ | ||
| 39 | "subq 4,$sp\n\t" \ | ||
| 40 | "move $spc,[$sp]\n\t" \ | ||
| 41 | "subq 4,$sp\n\t" \ | ||
| 42 | "move $mof,[$sp]\n\t" \ | ||
| 43 | "subq 4,$sp\n\t" \ | ||
| 44 | "move $srs,[$sp]\n\t" \ | ||
| 45 | "subq 4,$sp\n\t" \ | ||
| 46 | "move.d $acr,[$sp]\n\t" \ | ||
| 47 | "subq 14*4,$sp\n\t" \ | ||
| 48 | "movem $r13,[$sp]\n\t" \ | ||
| 49 | "subq 4,$sp\n\t" \ | ||
| 50 | "move.d $r10,[$sp]\n" | ||
| 51 | |||
| 52 | #define STR2(x) #x | ||
| 53 | #define STR(x) STR2(x) | ||
| 54 | |||
| 55 | #define IRQ_NAME2(nr) nr##_interrupt(void) | ||
| 56 | #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) | ||
| 57 | |||
| 58 | /* | ||
| 59 | * The reason for setting the S-bit when debugging the kernel is that we want | ||
| 60 | * hardware breakpoints to remain active while we are in an exception handler. | ||
| 61 | * Note that we cannot simply copy S1, since we may come here from user-space, | ||
| 62 | * or any context where the S-bit wasn't set. | ||
| 63 | */ | ||
| 64 | #ifdef CONFIG_ETRAX_KGDB | ||
| 65 | #define KGDB_FIXUP \ | ||
| 66 | "move $ccs, $r10\n\t" \ | ||
| 67 | "or.d (1<<9), $r10\n\t" \ | ||
| 68 | "move $r10, $ccs\n\t" | ||
| 69 | #else | ||
| 70 | #define KGDB_FIXUP "" | ||
| 71 | #endif | ||
| 72 | |||
| 73 | /* | ||
| 74 | * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock | ||
| 75 | * and jump to ret_from_intr which is found in entry.S. | ||
| 76 | * | ||
| 77 | * The reason for blocking the IRQ is to allow an sti() before the handler, | ||
| 78 | * which will acknowledge the interrupt, is run. The actual blocking is made | ||
| 79 | * by crisv32_do_IRQ. | ||
| 80 | */ | ||
| 81 | #define BUILD_IRQ(nr) \ | ||
| 82 | void IRQ_NAME(nr); \ | ||
| 83 | __asm__ ( \ | ||
| 84 | ".text\n\t" \ | ||
| 85 | "IRQ" #nr "_interrupt:\n\t" \ | ||
| 86 | SAVE_ALL \ | ||
| 87 | KGDB_FIXUP \ | ||
| 88 | "move.d "#nr",$r10\n\t" \ | ||
| 89 | "move.d $sp, $r12\n\t" \ | ||
| 90 | "jsr crisv32_do_IRQ\n\t" \ | ||
| 91 | "moveq 1, $r11\n\t" \ | ||
| 92 | "jump ret_from_intr\n\t" \ | ||
| 93 | "nop\n\t"); | ||
| 94 | /* | ||
| 95 | * This is subtle. The timer interrupt is crucial and it should not be disabled | ||
| 96 | * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it | ||
| 97 | * would have been BLOCK'ed, and then softirq's are run before we return here to | ||
| 98 | * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run | ||
| 99 | * and the watchdog will kill us. | ||
| 100 | * | ||
| 101 | * Furthermore, if a lot of other irq's occur before we return here, the | ||
| 102 | * multiple_irq handler is run and it prioritizes the timer interrupt. However | ||
| 103 | * if we had BLOCK'edit here, we would not get the multiple_irq at all. | ||
| 104 | * | ||
| 105 | * The non-blocking here is based on the knowledge that the timer interrupt is | ||
| 106 | * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not | ||
| 107 | * be an sti() before the timer irq handler is run to acknowledge the interrupt. | ||
| 108 | */ | ||
| 109 | #define BUILD_TIMER_IRQ(nr, mask) \ | ||
| 110 | void IRQ_NAME(nr); \ | ||
| 111 | __asm__ ( \ | ||
| 112 | ".text\n\t" \ | ||
| 113 | "IRQ" #nr "_interrupt:\n\t" \ | ||
| 114 | SAVE_ALL \ | ||
| 115 | KGDB_FIXUP \ | ||
| 116 | "move.d "#nr",$r10\n\t" \ | ||
| 117 | "move.d $sp,$r12\n\t" \ | ||
| 118 | "jsr crisv32_do_IRQ\n\t" \ | ||
| 119 | "moveq 0,$r11\n\t" \ | ||
| 120 | "jump ret_from_intr\n\t" \ | ||
| 121 | "nop\n\t"); | ||
| 122 | |||
| 123 | #endif /* __ASSEMBLY__ */ | ||
| 124 | #endif /* _ASM_ARCH_IRQ_H */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/arbiter.h b/include/asm-cris/arch-v32/mach-a3/arbiter.h deleted file mode 100644 index 65e9d6ff0520..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/arbiter.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_ARBITER_H | ||
| 2 | #define _ASM_CRIS_ARCH_ARBITER_H | ||
| 3 | |||
| 4 | #define EXT_REGION 0 | ||
| 5 | #define INT_REGION 1 | ||
| 6 | |||
| 7 | typedef void (watch_callback)(void); | ||
| 8 | |||
| 9 | enum { | ||
| 10 | arbiter_all_dmas = 0x7fe, | ||
| 11 | arbiter_cpu = 0x1800, | ||
| 12 | arbiter_all_clients = 0x7fff | ||
| 13 | }; | ||
| 14 | |||
| 15 | enum { | ||
| 16 | arbiter_bar_all_clients = 0x1ff | ||
| 17 | }; | ||
| 18 | |||
| 19 | enum { | ||
| 20 | arbiter_all_read = 0x55, | ||
| 21 | arbiter_all_write = 0xaa, | ||
| 22 | arbiter_all_accesses = 0xff | ||
| 23 | }; | ||
| 24 | |||
| 25 | #define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli)) | ||
| 26 | |||
| 27 | int crisv32_arbiter_allocate_bandwidth(int client, int region, | ||
| 28 | unsigned long bandwidth); | ||
| 29 | int crisv32_arbiter_watch(unsigned long start, unsigned long size, | ||
| 30 | unsigned long clients, unsigned long accesses, | ||
| 31 | watch_callback * cb); | ||
| 32 | int crisv32_arbiter_unwatch(int id); | ||
| 33 | |||
| 34 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/dma.h b/include/asm-cris/arch-v32/mach-a3/dma.h deleted file mode 100644 index 9e8eb13b601d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/dma.h +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_CRIS_DMA_H | ||
| 2 | #define _ASM_ARCH_CRIS_DMA_H | ||
| 3 | |||
| 4 | /* Defines for using and allocating dma channels. */ | ||
| 5 | |||
| 6 | #define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ | ||
| 7 | |||
| 8 | enum dma_owner { | ||
| 9 | dma_eth, | ||
| 10 | dma_ser0, | ||
| 11 | dma_ser1, | ||
| 12 | dma_ser2, | ||
| 13 | dma_ser3, | ||
| 14 | dma_ser4, | ||
| 15 | dma_iop, | ||
| 16 | dma_sser, | ||
| 17 | dma_strp, | ||
| 18 | dma_h264, | ||
| 19 | dma_jpeg | ||
| 20 | }; | ||
| 21 | |||
| 22 | int crisv32_request_dma(unsigned int dmanr, const char *device_id, | ||
| 23 | unsigned options, unsigned bandwidth, enum dma_owner owner); | ||
| 24 | void crisv32_free_dma(unsigned int dmanr); | ||
| 25 | |||
| 26 | /* Masks used by crisv32_request_dma options: */ | ||
| 27 | #define DMA_VERBOSE_ON_ERROR 1 | ||
| 28 | #define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) | ||
| 29 | #define DMA_INT_MEM 4 | ||
| 30 | |||
| 31 | #endif /* _ASM_ARCH_CRIS_DMA_H */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h deleted file mode 100644 index 02855adf63e8..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h +++ /dev/null | |||
| @@ -1,164 +0,0 @@ | |||
| 1 | #ifndef __clkgen_defs_asm_h | ||
| 2 | #define __clkgen_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: clkgen.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_bootsel, scope clkgen, type r */ | ||
| 54 | #define reg_clkgen_r_bootsel___boot_mode___lsb 0 | ||
| 55 | #define reg_clkgen_r_bootsel___boot_mode___width 5 | ||
| 56 | #define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 | ||
| 57 | #define reg_clkgen_r_bootsel___intern_main_clk___width 1 | ||
| 58 | #define reg_clkgen_r_bootsel___intern_main_clk___bit 5 | ||
| 59 | #define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 | ||
| 60 | #define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 | ||
| 61 | #define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 | ||
| 62 | #define reg_clkgen_r_bootsel_offset 0 | ||
| 63 | |||
| 64 | /* Register rw_clk_ctrl, scope clkgen, type rw */ | ||
| 65 | #define reg_clkgen_rw_clk_ctrl___pll___lsb 0 | ||
| 66 | #define reg_clkgen_rw_clk_ctrl___pll___width 1 | ||
| 67 | #define reg_clkgen_rw_clk_ctrl___pll___bit 0 | ||
| 68 | #define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 | ||
| 69 | #define reg_clkgen_rw_clk_ctrl___cpu___width 1 | ||
| 70 | #define reg_clkgen_rw_clk_ctrl___cpu___bit 1 | ||
| 71 | #define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 | ||
| 72 | #define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 | ||
| 73 | #define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 | ||
| 74 | #define reg_clkgen_rw_clk_ctrl___vin___lsb 3 | ||
| 75 | #define reg_clkgen_rw_clk_ctrl___vin___width 1 | ||
| 76 | #define reg_clkgen_rw_clk_ctrl___vin___bit 3 | ||
| 77 | #define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 | ||
| 78 | #define reg_clkgen_rw_clk_ctrl___sclr___width 1 | ||
| 79 | #define reg_clkgen_rw_clk_ctrl___sclr___bit 4 | ||
| 80 | #define reg_clkgen_rw_clk_ctrl___h264___lsb 5 | ||
| 81 | #define reg_clkgen_rw_clk_ctrl___h264___width 1 | ||
| 82 | #define reg_clkgen_rw_clk_ctrl___h264___bit 5 | ||
| 83 | #define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 | ||
| 84 | #define reg_clkgen_rw_clk_ctrl___ddr2___width 1 | ||
| 85 | #define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 | ||
| 86 | #define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 | ||
| 87 | #define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 | ||
| 88 | #define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 | ||
| 89 | #define reg_clkgen_rw_clk_ctrl___eth___lsb 8 | ||
| 90 | #define reg_clkgen_rw_clk_ctrl___eth___width 1 | ||
| 91 | #define reg_clkgen_rw_clk_ctrl___eth___bit 8 | ||
| 92 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 | ||
| 93 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 | ||
| 94 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 | ||
| 95 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 | ||
| 96 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 | ||
| 97 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 | ||
| 98 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 | ||
| 99 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 | ||
| 100 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 | ||
| 101 | #define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 | ||
| 102 | #define reg_clkgen_rw_clk_ctrl___jpeg___width 1 | ||
| 103 | #define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 | ||
| 104 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 | ||
| 105 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 | ||
| 106 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 | ||
| 107 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 | ||
| 108 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 | ||
| 109 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 | ||
| 110 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 | ||
| 111 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 | ||
| 112 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 | ||
| 113 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 | ||
| 114 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 | ||
| 115 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 | ||
| 116 | #define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 | ||
| 117 | #define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 | ||
| 118 | #define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 | ||
| 119 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 | ||
| 120 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 | ||
| 121 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 | ||
| 122 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 | ||
| 123 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 | ||
| 124 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 | ||
| 125 | #define reg_clkgen_rw_clk_ctrl_offset 4 | ||
| 126 | |||
| 127 | |||
| 128 | /* Constants */ | ||
| 129 | #define regk_clkgen_eth1000_rx 0x0000000c | ||
| 130 | #define regk_clkgen_eth1000_tx 0x0000000e | ||
| 131 | #define regk_clkgen_eth100_rx 0x0000001d | ||
| 132 | #define regk_clkgen_eth100_rx_half 0x0000001c | ||
| 133 | #define regk_clkgen_eth100_tx 0x0000001f | ||
| 134 | #define regk_clkgen_eth100_tx_half 0x0000001e | ||
| 135 | #define regk_clkgen_nand_3_2 0x00000000 | ||
| 136 | #define regk_clkgen_nand_3_2_0x30 0x00000002 | ||
| 137 | #define regk_clkgen_nand_3_2_0x30_pll 0x00000012 | ||
| 138 | #define regk_clkgen_nand_3_2_pll 0x00000010 | ||
| 139 | #define regk_clkgen_nand_3_3 0x00000001 | ||
| 140 | #define regk_clkgen_nand_3_3_0x30 0x00000003 | ||
| 141 | #define regk_clkgen_nand_3_3_0x30_pll 0x00000013 | ||
| 142 | #define regk_clkgen_nand_3_3_pll 0x00000011 | ||
| 143 | #define regk_clkgen_nand_4_2 0x00000004 | ||
| 144 | #define regk_clkgen_nand_4_2_0x30 0x00000006 | ||
| 145 | #define regk_clkgen_nand_4_2_0x30_pll 0x00000016 | ||
| 146 | #define regk_clkgen_nand_4_2_pll 0x00000014 | ||
| 147 | #define regk_clkgen_nand_4_3 0x00000005 | ||
| 148 | #define regk_clkgen_nand_4_3_0x30 0x00000007 | ||
| 149 | #define regk_clkgen_nand_4_3_0x30_pll 0x00000017 | ||
| 150 | #define regk_clkgen_nand_4_3_pll 0x00000015 | ||
| 151 | #define regk_clkgen_nand_5_2 0x00000008 | ||
| 152 | #define regk_clkgen_nand_5_2_0x30 0x0000000a | ||
| 153 | #define regk_clkgen_nand_5_2_0x30_pll 0x0000001a | ||
| 154 | #define regk_clkgen_nand_5_2_pll 0x00000018 | ||
| 155 | #define regk_clkgen_nand_5_3 0x00000009 | ||
| 156 | #define regk_clkgen_nand_5_3_0x30 0x0000000b | ||
| 157 | #define regk_clkgen_nand_5_3_0x30_pll 0x0000001b | ||
| 158 | #define regk_clkgen_nand_5_3_pll 0x00000019 | ||
| 159 | #define regk_clkgen_no 0x00000000 | ||
| 160 | #define regk_clkgen_rw_clk_ctrl_default 0x00000002 | ||
| 161 | #define regk_clkgen_ser 0x0000000d | ||
| 162 | #define regk_clkgen_ser_pll 0x0000000f | ||
| 163 | #define regk_clkgen_yes 0x00000001 | ||
| 164 | #endif /* __clkgen_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h deleted file mode 100644 index b12be03edacb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h +++ /dev/null | |||
| @@ -1,266 +0,0 @@ | |||
| 1 | #ifndef __ddr2_defs_asm_h | ||
| 2 | #define __ddr2_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ddr2.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_cfg, scope ddr2, type rw */ | ||
| 54 | #define reg_ddr2_rw_cfg___col_width___lsb 0 | ||
| 55 | #define reg_ddr2_rw_cfg___col_width___width 4 | ||
| 56 | #define reg_ddr2_rw_cfg___nr_banks___lsb 4 | ||
| 57 | #define reg_ddr2_rw_cfg___nr_banks___width 1 | ||
| 58 | #define reg_ddr2_rw_cfg___nr_banks___bit 4 | ||
| 59 | #define reg_ddr2_rw_cfg___bw___lsb 5 | ||
| 60 | #define reg_ddr2_rw_cfg___bw___width 1 | ||
| 61 | #define reg_ddr2_rw_cfg___bw___bit 5 | ||
| 62 | #define reg_ddr2_rw_cfg___nr_ref___lsb 6 | ||
| 63 | #define reg_ddr2_rw_cfg___nr_ref___width 4 | ||
| 64 | #define reg_ddr2_rw_cfg___ref_interval___lsb 10 | ||
| 65 | #define reg_ddr2_rw_cfg___ref_interval___width 11 | ||
| 66 | #define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 | ||
| 67 | #define reg_ddr2_rw_cfg___odt_ctrl___width 2 | ||
| 68 | #define reg_ddr2_rw_cfg___odt_mem___lsb 23 | ||
| 69 | #define reg_ddr2_rw_cfg___odt_mem___width 1 | ||
| 70 | #define reg_ddr2_rw_cfg___odt_mem___bit 23 | ||
| 71 | #define reg_ddr2_rw_cfg___imp_strength___lsb 24 | ||
| 72 | #define reg_ddr2_rw_cfg___imp_strength___width 1 | ||
| 73 | #define reg_ddr2_rw_cfg___imp_strength___bit 24 | ||
| 74 | #define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 | ||
| 75 | #define reg_ddr2_rw_cfg___auto_imp_cal___width 1 | ||
| 76 | #define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 | ||
| 77 | #define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 | ||
| 78 | #define reg_ddr2_rw_cfg___imp_cal_override___width 1 | ||
| 79 | #define reg_ddr2_rw_cfg___imp_cal_override___bit 26 | ||
| 80 | #define reg_ddr2_rw_cfg___dll_override___lsb 27 | ||
| 81 | #define reg_ddr2_rw_cfg___dll_override___width 1 | ||
| 82 | #define reg_ddr2_rw_cfg___dll_override___bit 27 | ||
| 83 | #define reg_ddr2_rw_cfg_offset 0 | ||
| 84 | |||
| 85 | /* Register rw_timing, scope ddr2, type rw */ | ||
| 86 | #define reg_ddr2_rw_timing___wr___lsb 0 | ||
| 87 | #define reg_ddr2_rw_timing___wr___width 3 | ||
| 88 | #define reg_ddr2_rw_timing___rcd___lsb 3 | ||
| 89 | #define reg_ddr2_rw_timing___rcd___width 3 | ||
| 90 | #define reg_ddr2_rw_timing___rp___lsb 6 | ||
| 91 | #define reg_ddr2_rw_timing___rp___width 3 | ||
| 92 | #define reg_ddr2_rw_timing___ras___lsb 9 | ||
| 93 | #define reg_ddr2_rw_timing___ras___width 4 | ||
| 94 | #define reg_ddr2_rw_timing___rfc___lsb 13 | ||
| 95 | #define reg_ddr2_rw_timing___rfc___width 7 | ||
| 96 | #define reg_ddr2_rw_timing___rc___lsb 20 | ||
| 97 | #define reg_ddr2_rw_timing___rc___width 5 | ||
| 98 | #define reg_ddr2_rw_timing___rtp___lsb 25 | ||
| 99 | #define reg_ddr2_rw_timing___rtp___width 2 | ||
| 100 | #define reg_ddr2_rw_timing___rtw___lsb 27 | ||
| 101 | #define reg_ddr2_rw_timing___rtw___width 3 | ||
| 102 | #define reg_ddr2_rw_timing___wtr___lsb 30 | ||
| 103 | #define reg_ddr2_rw_timing___wtr___width 2 | ||
| 104 | #define reg_ddr2_rw_timing_offset 4 | ||
| 105 | |||
| 106 | /* Register rw_latency, scope ddr2, type rw */ | ||
| 107 | #define reg_ddr2_rw_latency___cas___lsb 0 | ||
| 108 | #define reg_ddr2_rw_latency___cas___width 3 | ||
| 109 | #define reg_ddr2_rw_latency___additive___lsb 3 | ||
| 110 | #define reg_ddr2_rw_latency___additive___width 3 | ||
| 111 | #define reg_ddr2_rw_latency_offset 8 | ||
| 112 | |||
| 113 | /* Register rw_phy_cfg, scope ddr2, type rw */ | ||
| 114 | #define reg_ddr2_rw_phy_cfg___en___lsb 0 | ||
| 115 | #define reg_ddr2_rw_phy_cfg___en___width 1 | ||
| 116 | #define reg_ddr2_rw_phy_cfg___en___bit 0 | ||
| 117 | #define reg_ddr2_rw_phy_cfg_offset 12 | ||
| 118 | |||
| 119 | /* Register rw_phy_ctrl, scope ddr2, type rw */ | ||
| 120 | #define reg_ddr2_rw_phy_ctrl___rst___lsb 0 | ||
| 121 | #define reg_ddr2_rw_phy_ctrl___rst___width 1 | ||
| 122 | #define reg_ddr2_rw_phy_ctrl___rst___bit 0 | ||
| 123 | #define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 | ||
| 124 | #define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 | ||
| 125 | #define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 | ||
| 126 | #define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 | ||
| 127 | #define reg_ddr2_rw_phy_ctrl___cal_start___width 1 | ||
| 128 | #define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 | ||
| 129 | #define reg_ddr2_rw_phy_ctrl_offset 16 | ||
| 130 | |||
| 131 | /* Register rw_ctrl, scope ddr2, type rw */ | ||
| 132 | #define reg_ddr2_rw_ctrl___mrs_data___lsb 0 | ||
| 133 | #define reg_ddr2_rw_ctrl___mrs_data___width 16 | ||
| 134 | #define reg_ddr2_rw_ctrl___cmd___lsb 16 | ||
| 135 | #define reg_ddr2_rw_ctrl___cmd___width 8 | ||
| 136 | #define reg_ddr2_rw_ctrl_offset 20 | ||
| 137 | |||
| 138 | /* Register rw_pwr_down, scope ddr2, type rw */ | ||
| 139 | #define reg_ddr2_rw_pwr_down___self_ref___lsb 0 | ||
| 140 | #define reg_ddr2_rw_pwr_down___self_ref___width 2 | ||
| 141 | #define reg_ddr2_rw_pwr_down___phy_en___lsb 2 | ||
| 142 | #define reg_ddr2_rw_pwr_down___phy_en___width 1 | ||
| 143 | #define reg_ddr2_rw_pwr_down___phy_en___bit 2 | ||
| 144 | #define reg_ddr2_rw_pwr_down_offset 24 | ||
| 145 | |||
| 146 | /* Register r_stat, scope ddr2, type r */ | ||
| 147 | #define reg_ddr2_r_stat___dll_lock___lsb 0 | ||
| 148 | #define reg_ddr2_r_stat___dll_lock___width 1 | ||
| 149 | #define reg_ddr2_r_stat___dll_lock___bit 0 | ||
| 150 | #define reg_ddr2_r_stat___dll_delay_code___lsb 1 | ||
| 151 | #define reg_ddr2_r_stat___dll_delay_code___width 7 | ||
| 152 | #define reg_ddr2_r_stat___imp_cal_done___lsb 8 | ||
| 153 | #define reg_ddr2_r_stat___imp_cal_done___width 1 | ||
| 154 | #define reg_ddr2_r_stat___imp_cal_done___bit 8 | ||
| 155 | #define reg_ddr2_r_stat___imp_cal_fault___lsb 9 | ||
| 156 | #define reg_ddr2_r_stat___imp_cal_fault___width 1 | ||
| 157 | #define reg_ddr2_r_stat___imp_cal_fault___bit 9 | ||
| 158 | #define reg_ddr2_r_stat___cal_imp_pu___lsb 10 | ||
| 159 | #define reg_ddr2_r_stat___cal_imp_pu___width 4 | ||
| 160 | #define reg_ddr2_r_stat___cal_imp_pd___lsb 14 | ||
| 161 | #define reg_ddr2_r_stat___cal_imp_pd___width 4 | ||
| 162 | #define reg_ddr2_r_stat_offset 28 | ||
| 163 | |||
| 164 | /* Register rw_imp_ctrl, scope ddr2, type rw */ | ||
| 165 | #define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 | ||
| 166 | #define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 | ||
| 167 | #define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 | ||
| 168 | #define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 | ||
| 169 | #define reg_ddr2_rw_imp_ctrl_offset 32 | ||
| 170 | |||
| 171 | #define STRIDE_ddr2_rw_dll_ctrl 4 | ||
| 172 | /* Register rw_dll_ctrl, scope ddr2, type rw */ | ||
| 173 | #define reg_ddr2_rw_dll_ctrl___mode___lsb 0 | ||
| 174 | #define reg_ddr2_rw_dll_ctrl___mode___width 1 | ||
| 175 | #define reg_ddr2_rw_dll_ctrl___mode___bit 0 | ||
| 176 | #define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 | ||
| 177 | #define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 | ||
| 178 | #define reg_ddr2_rw_dll_ctrl_offset 36 | ||
| 179 | |||
| 180 | #define STRIDE_ddr2_rw_dqs_dll_ctrl 4 | ||
| 181 | /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ | ||
| 182 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 | ||
| 183 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 | ||
| 184 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 | ||
| 185 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 | ||
| 186 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 | ||
| 187 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 | ||
| 188 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 | ||
| 189 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 | ||
| 190 | #define reg_ddr2_rw_dqs_dll_ctrl_offset 52 | ||
| 191 | |||
| 192 | |||
| 193 | /* Constants */ | ||
| 194 | #define regk_ddr2_al0 0x00000000 | ||
| 195 | #define regk_ddr2_al1 0x00000008 | ||
| 196 | #define regk_ddr2_al2 0x00000010 | ||
| 197 | #define regk_ddr2_al3 0x00000018 | ||
| 198 | #define regk_ddr2_al4 0x00000020 | ||
| 199 | #define regk_ddr2_auto 0x00000003 | ||
| 200 | #define regk_ddr2_bank4 0x00000000 | ||
| 201 | #define regk_ddr2_bank8 0x00000001 | ||
| 202 | #define regk_ddr2_bl4 0x00000002 | ||
| 203 | #define regk_ddr2_bl8 0x00000003 | ||
| 204 | #define regk_ddr2_bt_il 0x00000008 | ||
| 205 | #define regk_ddr2_bt_seq 0x00000000 | ||
| 206 | #define regk_ddr2_bw16 0x00000001 | ||
| 207 | #define regk_ddr2_bw32 0x00000000 | ||
| 208 | #define regk_ddr2_cas2 0x00000020 | ||
| 209 | #define regk_ddr2_cas3 0x00000030 | ||
| 210 | #define regk_ddr2_cas4 0x00000040 | ||
| 211 | #define regk_ddr2_cas5 0x00000050 | ||
| 212 | #define regk_ddr2_deselect 0x000000c0 | ||
| 213 | #define regk_ddr2_dic_weak 0x00000002 | ||
| 214 | #define regk_ddr2_direct 0x00000001 | ||
| 215 | #define regk_ddr2_dis 0x00000000 | ||
| 216 | #define regk_ddr2_dll_dis 0x00000001 | ||
| 217 | #define regk_ddr2_dll_en 0x00000000 | ||
| 218 | #define regk_ddr2_dll_rst 0x00000100 | ||
| 219 | #define regk_ddr2_emrs 0x00000081 | ||
| 220 | #define regk_ddr2_emrs2 0x00000082 | ||
| 221 | #define regk_ddr2_emrs3 0x00000083 | ||
| 222 | #define regk_ddr2_full 0x00000001 | ||
| 223 | #define regk_ddr2_hi_ref_rate 0x00000080 | ||
| 224 | #define regk_ddr2_mrs 0x00000080 | ||
| 225 | #define regk_ddr2_no 0x00000000 | ||
| 226 | #define regk_ddr2_nop 0x000000b8 | ||
| 227 | #define regk_ddr2_ocd_adj 0x00000200 | ||
| 228 | #define regk_ddr2_ocd_default 0x00000380 | ||
| 229 | #define regk_ddr2_ocd_drive0 0x00000100 | ||
| 230 | #define regk_ddr2_ocd_drive1 0x00000080 | ||
| 231 | #define regk_ddr2_ocd_exit 0x00000000 | ||
| 232 | #define regk_ddr2_odt_dis 0x00000000 | ||
| 233 | #define regk_ddr2_offs 0x00000000 | ||
| 234 | #define regk_ddr2_pre 0x00000090 | ||
| 235 | #define regk_ddr2_pre_all 0x00000400 | ||
| 236 | #define regk_ddr2_pwr_down_fast 0x00000000 | ||
| 237 | #define regk_ddr2_pwr_down_slow 0x00001000 | ||
| 238 | #define regk_ddr2_ref 0x00000088 | ||
| 239 | #define regk_ddr2_rtt150 0x00000040 | ||
| 240 | #define regk_ddr2_rtt50 0x00000044 | ||
| 241 | #define regk_ddr2_rtt75 0x00000004 | ||
| 242 | #define regk_ddr2_rw_cfg_default 0x00186000 | ||
| 243 | #define regk_ddr2_rw_dll_ctrl_default 0x00000000 | ||
| 244 | #define regk_ddr2_rw_dll_ctrl_size 0x00000004 | ||
| 245 | #define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 | ||
| 246 | #define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 | ||
| 247 | #define regk_ddr2_rw_latency_default 0x00000000 | ||
| 248 | #define regk_ddr2_rw_phy_cfg_default 0x00000000 | ||
| 249 | #define regk_ddr2_rw_pwr_down_default 0x00000000 | ||
| 250 | #define regk_ddr2_rw_timing_default 0x00000000 | ||
| 251 | #define regk_ddr2_s1Gb 0x0000001a | ||
| 252 | #define regk_ddr2_s256Mb 0x0000000f | ||
| 253 | #define regk_ddr2_s2Gb 0x00000027 | ||
| 254 | #define regk_ddr2_s4Gb 0x00000042 | ||
| 255 | #define regk_ddr2_s512Mb 0x00000015 | ||
| 256 | #define regk_ddr2_temp0_85 0x00000618 | ||
| 257 | #define regk_ddr2_temp85_95 0x0000030c | ||
| 258 | #define regk_ddr2_term150 0x00000002 | ||
| 259 | #define regk_ddr2_term50 0x00000003 | ||
| 260 | #define regk_ddr2_term75 0x00000001 | ||
| 261 | #define regk_ddr2_test 0x00000080 | ||
| 262 | #define regk_ddr2_weak 0x00000000 | ||
| 263 | #define regk_ddr2_wr2 0x00000200 | ||
| 264 | #define regk_ddr2_wr3 0x00000400 | ||
| 265 | #define regk_ddr2_yes 0x00000001 | ||
| 266 | #endif /* __ddr2_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index df6714fda179..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h +++ /dev/null | |||
| @@ -1,849 +0,0 @@ | |||
| 1 | #ifndef __gio_defs_asm_h | ||
| 2 | #define __gio_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: gio.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_pa_din, scope gio, type r */ | ||
| 54 | #define reg_gio_r_pa_din___data___lsb 0 | ||
| 55 | #define reg_gio_r_pa_din___data___width 32 | ||
| 56 | #define reg_gio_r_pa_din_offset 0 | ||
| 57 | |||
| 58 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 59 | #define reg_gio_rw_pa_dout___data___lsb 0 | ||
| 60 | #define reg_gio_rw_pa_dout___data___width 32 | ||
| 61 | #define reg_gio_rw_pa_dout_offset 4 | ||
| 62 | |||
| 63 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 64 | #define reg_gio_rw_pa_oe___oe___lsb 0 | ||
| 65 | #define reg_gio_rw_pa_oe___oe___width 32 | ||
| 66 | #define reg_gio_rw_pa_oe_offset 8 | ||
| 67 | |||
| 68 | /* Register rw_pa_byte0_dout, scope gio, type rw */ | ||
| 69 | #define reg_gio_rw_pa_byte0_dout___data___lsb 0 | ||
| 70 | #define reg_gio_rw_pa_byte0_dout___data___width 8 | ||
| 71 | #define reg_gio_rw_pa_byte0_dout_offset 12 | ||
| 72 | |||
| 73 | /* Register rw_pa_byte0_oe, scope gio, type rw */ | ||
| 74 | #define reg_gio_rw_pa_byte0_oe___oe___lsb 0 | ||
| 75 | #define reg_gio_rw_pa_byte0_oe___oe___width 8 | ||
| 76 | #define reg_gio_rw_pa_byte0_oe_offset 16 | ||
| 77 | |||
| 78 | /* Register rw_pa_byte1_dout, scope gio, type rw */ | ||
| 79 | #define reg_gio_rw_pa_byte1_dout___data___lsb 0 | ||
| 80 | #define reg_gio_rw_pa_byte1_dout___data___width 8 | ||
| 81 | #define reg_gio_rw_pa_byte1_dout_offset 20 | ||
| 82 | |||
| 83 | /* Register rw_pa_byte1_oe, scope gio, type rw */ | ||
| 84 | #define reg_gio_rw_pa_byte1_oe___oe___lsb 0 | ||
| 85 | #define reg_gio_rw_pa_byte1_oe___oe___width 8 | ||
| 86 | #define reg_gio_rw_pa_byte1_oe_offset 24 | ||
| 87 | |||
| 88 | /* Register rw_pa_byte2_dout, scope gio, type rw */ | ||
| 89 | #define reg_gio_rw_pa_byte2_dout___data___lsb 0 | ||
| 90 | #define reg_gio_rw_pa_byte2_dout___data___width 8 | ||
| 91 | #define reg_gio_rw_pa_byte2_dout_offset 28 | ||
| 92 | |||
| 93 | /* Register rw_pa_byte2_oe, scope gio, type rw */ | ||
| 94 | #define reg_gio_rw_pa_byte2_oe___oe___lsb 0 | ||
| 95 | #define reg_gio_rw_pa_byte2_oe___oe___width 8 | ||
| 96 | #define reg_gio_rw_pa_byte2_oe_offset 32 | ||
| 97 | |||
| 98 | /* Register rw_pa_byte3_dout, scope gio, type rw */ | ||
| 99 | #define reg_gio_rw_pa_byte3_dout___data___lsb 0 | ||
| 100 | #define reg_gio_rw_pa_byte3_dout___data___width 8 | ||
| 101 | #define reg_gio_rw_pa_byte3_dout_offset 36 | ||
| 102 | |||
| 103 | /* Register rw_pa_byte3_oe, scope gio, type rw */ | ||
| 104 | #define reg_gio_rw_pa_byte3_oe___oe___lsb 0 | ||
| 105 | #define reg_gio_rw_pa_byte3_oe___oe___width 8 | ||
| 106 | #define reg_gio_rw_pa_byte3_oe_offset 40 | ||
| 107 | |||
| 108 | /* Register r_pb_din, scope gio, type r */ | ||
| 109 | #define reg_gio_r_pb_din___data___lsb 0 | ||
| 110 | #define reg_gio_r_pb_din___data___width 32 | ||
| 111 | #define reg_gio_r_pb_din_offset 44 | ||
| 112 | |||
| 113 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 114 | #define reg_gio_rw_pb_dout___data___lsb 0 | ||
| 115 | #define reg_gio_rw_pb_dout___data___width 32 | ||
| 116 | #define reg_gio_rw_pb_dout_offset 48 | ||
| 117 | |||
| 118 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 119 | #define reg_gio_rw_pb_oe___oe___lsb 0 | ||
| 120 | #define reg_gio_rw_pb_oe___oe___width 32 | ||
| 121 | #define reg_gio_rw_pb_oe_offset 52 | ||
| 122 | |||
| 123 | /* Register rw_pb_byte0_dout, scope gio, type rw */ | ||
| 124 | #define reg_gio_rw_pb_byte0_dout___data___lsb 0 | ||
| 125 | #define reg_gio_rw_pb_byte0_dout___data___width 8 | ||
| 126 | #define reg_gio_rw_pb_byte0_dout_offset 56 | ||
| 127 | |||
| 128 | /* Register rw_pb_byte0_oe, scope gio, type rw */ | ||
| 129 | #define reg_gio_rw_pb_byte0_oe___oe___lsb 0 | ||
| 130 | #define reg_gio_rw_pb_byte0_oe___oe___width 8 | ||
| 131 | #define reg_gio_rw_pb_byte0_oe_offset 60 | ||
| 132 | |||
| 133 | /* Register rw_pb_byte1_dout, scope gio, type rw */ | ||
| 134 | #define reg_gio_rw_pb_byte1_dout___data___lsb 0 | ||
| 135 | #define reg_gio_rw_pb_byte1_dout___data___width 8 | ||
| 136 | #define reg_gio_rw_pb_byte1_dout_offset 64 | ||
| 137 | |||
| 138 | /* Register rw_pb_byte1_oe, scope gio, type rw */ | ||
| 139 | #define reg_gio_rw_pb_byte1_oe___oe___lsb 0 | ||
| 140 | #define reg_gio_rw_pb_byte1_oe___oe___width 8 | ||
| 141 | #define reg_gio_rw_pb_byte1_oe_offset 68 | ||
| 142 | |||
| 143 | /* Register rw_pb_byte2_dout, scope gio, type rw */ | ||
| 144 | #define reg_gio_rw_pb_byte2_dout___data___lsb 0 | ||
| 145 | #define reg_gio_rw_pb_byte2_dout___data___width 8 | ||
| 146 | #define reg_gio_rw_pb_byte2_dout_offset 72 | ||
| 147 | |||
| 148 | /* Register rw_pb_byte2_oe, scope gio, type rw */ | ||
| 149 | #define reg_gio_rw_pb_byte2_oe___oe___lsb 0 | ||
| 150 | #define reg_gio_rw_pb_byte2_oe___oe___width 8 | ||
| 151 | #define reg_gio_rw_pb_byte2_oe_offset 76 | ||
| 152 | |||
| 153 | /* Register rw_pb_byte3_dout, scope gio, type rw */ | ||
| 154 | #define reg_gio_rw_pb_byte3_dout___data___lsb 0 | ||
| 155 | #define reg_gio_rw_pb_byte3_dout___data___width 8 | ||
| 156 | #define reg_gio_rw_pb_byte3_dout_offset 80 | ||
| 157 | |||
| 158 | /* Register rw_pb_byte3_oe, scope gio, type rw */ | ||
| 159 | #define reg_gio_rw_pb_byte3_oe___oe___lsb 0 | ||
| 160 | #define reg_gio_rw_pb_byte3_oe___oe___width 8 | ||
| 161 | #define reg_gio_rw_pb_byte3_oe_offset 84 | ||
| 162 | |||
| 163 | /* Register r_pc_din, scope gio, type r */ | ||
| 164 | #define reg_gio_r_pc_din___data___lsb 0 | ||
| 165 | #define reg_gio_r_pc_din___data___width 16 | ||
| 166 | #define reg_gio_r_pc_din_offset 88 | ||
| 167 | |||
| 168 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 169 | #define reg_gio_rw_pc_dout___data___lsb 0 | ||
| 170 | #define reg_gio_rw_pc_dout___data___width 16 | ||
| 171 | #define reg_gio_rw_pc_dout_offset 92 | ||
| 172 | |||
| 173 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 174 | #define reg_gio_rw_pc_oe___oe___lsb 0 | ||
| 175 | #define reg_gio_rw_pc_oe___oe___width 16 | ||
| 176 | #define reg_gio_rw_pc_oe_offset 96 | ||
| 177 | |||
| 178 | /* Register rw_pc_byte0_dout, scope gio, type rw */ | ||
| 179 | #define reg_gio_rw_pc_byte0_dout___data___lsb 0 | ||
| 180 | #define reg_gio_rw_pc_byte0_dout___data___width 8 | ||
| 181 | #define reg_gio_rw_pc_byte0_dout_offset 100 | ||
| 182 | |||
| 183 | /* Register rw_pc_byte0_oe, scope gio, type rw */ | ||
| 184 | #define reg_gio_rw_pc_byte0_oe___oe___lsb 0 | ||
| 185 | #define reg_gio_rw_pc_byte0_oe___oe___width 8 | ||
| 186 | #define reg_gio_rw_pc_byte0_oe_offset 104 | ||
| 187 | |||
| 188 | /* Register rw_pc_byte1_dout, scope gio, type rw */ | ||
| 189 | #define reg_gio_rw_pc_byte1_dout___data___lsb 0 | ||
| 190 | #define reg_gio_rw_pc_byte1_dout___data___width 8 | ||
| 191 | #define reg_gio_rw_pc_byte1_dout_offset 108 | ||
| 192 | |||
| 193 | /* Register rw_pc_byte1_oe, scope gio, type rw */ | ||
| 194 | #define reg_gio_rw_pc_byte1_oe___oe___lsb 0 | ||
| 195 | #define reg_gio_rw_pc_byte1_oe___oe___width 8 | ||
| 196 | #define reg_gio_rw_pc_byte1_oe_offset 112 | ||
| 197 | |||
| 198 | /* Register r_pd_din, scope gio, type r */ | ||
| 199 | #define reg_gio_r_pd_din___data___lsb 0 | ||
| 200 | #define reg_gio_r_pd_din___data___width 32 | ||
| 201 | #define reg_gio_r_pd_din_offset 116 | ||
| 202 | |||
| 203 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 204 | #define reg_gio_rw_intr_cfg___intr0___lsb 0 | ||
| 205 | #define reg_gio_rw_intr_cfg___intr0___width 3 | ||
| 206 | #define reg_gio_rw_intr_cfg___intr1___lsb 3 | ||
| 207 | #define reg_gio_rw_intr_cfg___intr1___width 3 | ||
| 208 | #define reg_gio_rw_intr_cfg___intr2___lsb 6 | ||
| 209 | #define reg_gio_rw_intr_cfg___intr2___width 3 | ||
| 210 | #define reg_gio_rw_intr_cfg___intr3___lsb 9 | ||
| 211 | #define reg_gio_rw_intr_cfg___intr3___width 3 | ||
| 212 | #define reg_gio_rw_intr_cfg___intr4___lsb 12 | ||
| 213 | #define reg_gio_rw_intr_cfg___intr4___width 3 | ||
| 214 | #define reg_gio_rw_intr_cfg___intr5___lsb 15 | ||
| 215 | #define reg_gio_rw_intr_cfg___intr5___width 3 | ||
| 216 | #define reg_gio_rw_intr_cfg___intr6___lsb 18 | ||
| 217 | #define reg_gio_rw_intr_cfg___intr6___width 3 | ||
| 218 | #define reg_gio_rw_intr_cfg___intr7___lsb 21 | ||
| 219 | #define reg_gio_rw_intr_cfg___intr7___width 3 | ||
| 220 | #define reg_gio_rw_intr_cfg_offset 120 | ||
| 221 | |||
| 222 | /* Register rw_intr_pins, scope gio, type rw */ | ||
| 223 | #define reg_gio_rw_intr_pins___intr0___lsb 0 | ||
| 224 | #define reg_gio_rw_intr_pins___intr0___width 4 | ||
| 225 | #define reg_gio_rw_intr_pins___intr1___lsb 4 | ||
| 226 | #define reg_gio_rw_intr_pins___intr1___width 4 | ||
| 227 | #define reg_gio_rw_intr_pins___intr2___lsb 8 | ||
| 228 | #define reg_gio_rw_intr_pins___intr2___width 4 | ||
| 229 | #define reg_gio_rw_intr_pins___intr3___lsb 12 | ||
| 230 | #define reg_gio_rw_intr_pins___intr3___width 4 | ||
| 231 | #define reg_gio_rw_intr_pins___intr4___lsb 16 | ||
| 232 | #define reg_gio_rw_intr_pins___intr4___width 4 | ||
| 233 | #define reg_gio_rw_intr_pins___intr5___lsb 20 | ||
| 234 | #define reg_gio_rw_intr_pins___intr5___width 4 | ||
| 235 | #define reg_gio_rw_intr_pins___intr6___lsb 24 | ||
| 236 | #define reg_gio_rw_intr_pins___intr6___width 4 | ||
| 237 | #define reg_gio_rw_intr_pins___intr7___lsb 28 | ||
| 238 | #define reg_gio_rw_intr_pins___intr7___width 4 | ||
| 239 | #define reg_gio_rw_intr_pins_offset 124 | ||
| 240 | |||
| 241 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 242 | #define reg_gio_rw_intr_mask___intr0___lsb 0 | ||
| 243 | #define reg_gio_rw_intr_mask___intr0___width 1 | ||
| 244 | #define reg_gio_rw_intr_mask___intr0___bit 0 | ||
| 245 | #define reg_gio_rw_intr_mask___intr1___lsb 1 | ||
| 246 | #define reg_gio_rw_intr_mask___intr1___width 1 | ||
| 247 | #define reg_gio_rw_intr_mask___intr1___bit 1 | ||
| 248 | #define reg_gio_rw_intr_mask___intr2___lsb 2 | ||
| 249 | #define reg_gio_rw_intr_mask___intr2___width 1 | ||
| 250 | #define reg_gio_rw_intr_mask___intr2___bit 2 | ||
| 251 | #define reg_gio_rw_intr_mask___intr3___lsb 3 | ||
| 252 | #define reg_gio_rw_intr_mask___intr3___width 1 | ||
| 253 | #define reg_gio_rw_intr_mask___intr3___bit 3 | ||
| 254 | #define reg_gio_rw_intr_mask___intr4___lsb 4 | ||
| 255 | #define reg_gio_rw_intr_mask___intr4___width 1 | ||
| 256 | #define reg_gio_rw_intr_mask___intr4___bit 4 | ||
| 257 | #define reg_gio_rw_intr_mask___intr5___lsb 5 | ||
| 258 | #define reg_gio_rw_intr_mask___intr5___width 1 | ||
| 259 | #define reg_gio_rw_intr_mask___intr5___bit 5 | ||
| 260 | #define reg_gio_rw_intr_mask___intr6___lsb 6 | ||
| 261 | #define reg_gio_rw_intr_mask___intr6___width 1 | ||
| 262 | #define reg_gio_rw_intr_mask___intr6___bit 6 | ||
| 263 | #define reg_gio_rw_intr_mask___intr7___lsb 7 | ||
| 264 | #define reg_gio_rw_intr_mask___intr7___width 1 | ||
| 265 | #define reg_gio_rw_intr_mask___intr7___bit 7 | ||
| 266 | #define reg_gio_rw_intr_mask___i2c0_done___lsb 8 | ||
| 267 | #define reg_gio_rw_intr_mask___i2c0_done___width 1 | ||
| 268 | #define reg_gio_rw_intr_mask___i2c0_done___bit 8 | ||
| 269 | #define reg_gio_rw_intr_mask___i2c1_done___lsb 9 | ||
| 270 | #define reg_gio_rw_intr_mask___i2c1_done___width 1 | ||
| 271 | #define reg_gio_rw_intr_mask___i2c1_done___bit 9 | ||
| 272 | #define reg_gio_rw_intr_mask_offset 128 | ||
| 273 | |||
| 274 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 275 | #define reg_gio_rw_ack_intr___intr0___lsb 0 | ||
| 276 | #define reg_gio_rw_ack_intr___intr0___width 1 | ||
| 277 | #define reg_gio_rw_ack_intr___intr0___bit 0 | ||
| 278 | #define reg_gio_rw_ack_intr___intr1___lsb 1 | ||
| 279 | #define reg_gio_rw_ack_intr___intr1___width 1 | ||
| 280 | #define reg_gio_rw_ack_intr___intr1___bit 1 | ||
| 281 | #define reg_gio_rw_ack_intr___intr2___lsb 2 | ||
| 282 | #define reg_gio_rw_ack_intr___intr2___width 1 | ||
| 283 | #define reg_gio_rw_ack_intr___intr2___bit 2 | ||
| 284 | #define reg_gio_rw_ack_intr___intr3___lsb 3 | ||
| 285 | #define reg_gio_rw_ack_intr___intr3___width 1 | ||
| 286 | #define reg_gio_rw_ack_intr___intr3___bit 3 | ||
| 287 | #define reg_gio_rw_ack_intr___intr4___lsb 4 | ||
| 288 | #define reg_gio_rw_ack_intr___intr4___width 1 | ||
| 289 | #define reg_gio_rw_ack_intr___intr4___bit 4 | ||
| 290 | #define reg_gio_rw_ack_intr___intr5___lsb 5 | ||
| 291 | #define reg_gio_rw_ack_intr___intr5___width 1 | ||
| 292 | #define reg_gio_rw_ack_intr___intr5___bit 5 | ||
| 293 | #define reg_gio_rw_ack_intr___intr6___lsb 6 | ||
| 294 | #define reg_gio_rw_ack_intr___intr6___width 1 | ||
| 295 | #define reg_gio_rw_ack_intr___intr6___bit 6 | ||
| 296 | #define reg_gio_rw_ack_intr___intr7___lsb 7 | ||
| 297 | #define reg_gio_rw_ack_intr___intr7___width 1 | ||
| 298 | #define reg_gio_rw_ack_intr___intr7___bit 7 | ||
| 299 | #define reg_gio_rw_ack_intr___i2c0_done___lsb 8 | ||
| 300 | #define reg_gio_rw_ack_intr___i2c0_done___width 1 | ||
| 301 | #define reg_gio_rw_ack_intr___i2c0_done___bit 8 | ||
| 302 | #define reg_gio_rw_ack_intr___i2c1_done___lsb 9 | ||
| 303 | #define reg_gio_rw_ack_intr___i2c1_done___width 1 | ||
| 304 | #define reg_gio_rw_ack_intr___i2c1_done___bit 9 | ||
| 305 | #define reg_gio_rw_ack_intr_offset 132 | ||
| 306 | |||
| 307 | /* Register r_intr, scope gio, type r */ | ||
| 308 | #define reg_gio_r_intr___intr0___lsb 0 | ||
| 309 | #define reg_gio_r_intr___intr0___width 1 | ||
| 310 | #define reg_gio_r_intr___intr0___bit 0 | ||
| 311 | #define reg_gio_r_intr___intr1___lsb 1 | ||
| 312 | #define reg_gio_r_intr___intr1___width 1 | ||
| 313 | #define reg_gio_r_intr___intr1___bit 1 | ||
| 314 | #define reg_gio_r_intr___intr2___lsb 2 | ||
| 315 | #define reg_gio_r_intr___intr2___width 1 | ||
| 316 | #define reg_gio_r_intr___intr2___bit 2 | ||
| 317 | #define reg_gio_r_intr___intr3___lsb 3 | ||
| 318 | #define reg_gio_r_intr___intr3___width 1 | ||
| 319 | #define reg_gio_r_intr___intr3___bit 3 | ||
| 320 | #define reg_gio_r_intr___intr4___lsb 4 | ||
| 321 | #define reg_gio_r_intr___intr4___width 1 | ||
| 322 | #define reg_gio_r_intr___intr4___bit 4 | ||
| 323 | #define reg_gio_r_intr___intr5___lsb 5 | ||
| 324 | #define reg_gio_r_intr___intr5___width 1 | ||
| 325 | #define reg_gio_r_intr___intr5___bit 5 | ||
| 326 | #define reg_gio_r_intr___intr6___lsb 6 | ||
| 327 | #define reg_gio_r_intr___intr6___width 1 | ||
| 328 | #define reg_gio_r_intr___intr6___bit 6 | ||
| 329 | #define reg_gio_r_intr___intr7___lsb 7 | ||
| 330 | #define reg_gio_r_intr___intr7___width 1 | ||
| 331 | #define reg_gio_r_intr___intr7___bit 7 | ||
| 332 | #define reg_gio_r_intr___i2c0_done___lsb 8 | ||
| 333 | #define reg_gio_r_intr___i2c0_done___width 1 | ||
| 334 | #define reg_gio_r_intr___i2c0_done___bit 8 | ||
| 335 | #define reg_gio_r_intr___i2c1_done___lsb 9 | ||
| 336 | #define reg_gio_r_intr___i2c1_done___width 1 | ||
| 337 | #define reg_gio_r_intr___i2c1_done___bit 9 | ||
| 338 | #define reg_gio_r_intr_offset 136 | ||
| 339 | |||
| 340 | /* Register r_masked_intr, scope gio, type r */ | ||
| 341 | #define reg_gio_r_masked_intr___intr0___lsb 0 | ||
| 342 | #define reg_gio_r_masked_intr___intr0___width 1 | ||
| 343 | #define reg_gio_r_masked_intr___intr0___bit 0 | ||
| 344 | #define reg_gio_r_masked_intr___intr1___lsb 1 | ||
| 345 | #define reg_gio_r_masked_intr___intr1___width 1 | ||
| 346 | #define reg_gio_r_masked_intr___intr1___bit 1 | ||
| 347 | #define reg_gio_r_masked_intr___intr2___lsb 2 | ||
| 348 | #define reg_gio_r_masked_intr___intr2___width 1 | ||
| 349 | #define reg_gio_r_masked_intr___intr2___bit 2 | ||
| 350 | #define reg_gio_r_masked_intr___intr3___lsb 3 | ||
| 351 | #define reg_gio_r_masked_intr___intr3___width 1 | ||
| 352 | #define reg_gio_r_masked_intr___intr3___bit 3 | ||
| 353 | #define reg_gio_r_masked_intr___intr4___lsb 4 | ||
| 354 | #define reg_gio_r_masked_intr___intr4___width 1 | ||
| 355 | #define reg_gio_r_masked_intr___intr4___bit 4 | ||
| 356 | #define reg_gio_r_masked_intr___intr5___lsb 5 | ||
| 357 | #define reg_gio_r_masked_intr___intr5___width 1 | ||
| 358 | #define reg_gio_r_masked_intr___intr5___bit 5 | ||
| 359 | #define reg_gio_r_masked_intr___intr6___lsb 6 | ||
| 360 | #define reg_gio_r_masked_intr___intr6___width 1 | ||
| 361 | #define reg_gio_r_masked_intr___intr6___bit 6 | ||
| 362 | #define reg_gio_r_masked_intr___intr7___lsb 7 | ||
| 363 | #define reg_gio_r_masked_intr___intr7___width 1 | ||
| 364 | #define reg_gio_r_masked_intr___intr7___bit 7 | ||
| 365 | #define reg_gio_r_masked_intr___i2c0_done___lsb 8 | ||
| 366 | #define reg_gio_r_masked_intr___i2c0_done___width 1 | ||
| 367 | #define reg_gio_r_masked_intr___i2c0_done___bit 8 | ||
| 368 | #define reg_gio_r_masked_intr___i2c1_done___lsb 9 | ||
| 369 | #define reg_gio_r_masked_intr___i2c1_done___width 1 | ||
| 370 | #define reg_gio_r_masked_intr___i2c1_done___bit 9 | ||
| 371 | #define reg_gio_r_masked_intr_offset 140 | ||
| 372 | |||
| 373 | /* Register rw_i2c0_start, scope gio, type rw */ | ||
| 374 | #define reg_gio_rw_i2c0_start___run___lsb 0 | ||
| 375 | #define reg_gio_rw_i2c0_start___run___width 1 | ||
| 376 | #define reg_gio_rw_i2c0_start___run___bit 0 | ||
| 377 | #define reg_gio_rw_i2c0_start_offset 144 | ||
| 378 | |||
| 379 | /* Register rw_i2c0_cfg, scope gio, type rw */ | ||
| 380 | #define reg_gio_rw_i2c0_cfg___en___lsb 0 | ||
| 381 | #define reg_gio_rw_i2c0_cfg___en___width 1 | ||
| 382 | #define reg_gio_rw_i2c0_cfg___en___bit 0 | ||
| 383 | #define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 | ||
| 384 | #define reg_gio_rw_i2c0_cfg___bit_order___width 1 | ||
| 385 | #define reg_gio_rw_i2c0_cfg___bit_order___bit 1 | ||
| 386 | #define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 | ||
| 387 | #define reg_gio_rw_i2c0_cfg___scl_io___width 1 | ||
| 388 | #define reg_gio_rw_i2c0_cfg___scl_io___bit 2 | ||
| 389 | #define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 | ||
| 390 | #define reg_gio_rw_i2c0_cfg___scl_inv___width 1 | ||
| 391 | #define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 | ||
| 392 | #define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 | ||
| 393 | #define reg_gio_rw_i2c0_cfg___sda_io___width 1 | ||
| 394 | #define reg_gio_rw_i2c0_cfg___sda_io___bit 4 | ||
| 395 | #define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 | ||
| 396 | #define reg_gio_rw_i2c0_cfg___sda_idle___width 1 | ||
| 397 | #define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 | ||
| 398 | #define reg_gio_rw_i2c0_cfg_offset 148 | ||
| 399 | |||
| 400 | /* Register rw_i2c0_ctrl, scope gio, type rw */ | ||
| 401 | #define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 | ||
| 402 | #define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 | ||
| 403 | #define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 | ||
| 404 | #define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 | ||
| 405 | #define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 | ||
| 406 | #define reg_gio_rw_i2c0_ctrl___extra_start___width 3 | ||
| 407 | #define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 | ||
| 408 | #define reg_gio_rw_i2c0_ctrl___early_end___width 1 | ||
| 409 | #define reg_gio_rw_i2c0_ctrl___early_end___bit 15 | ||
| 410 | #define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 | ||
| 411 | #define reg_gio_rw_i2c0_ctrl___start_stop___width 1 | ||
| 412 | #define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 | ||
| 413 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 | ||
| 414 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 | ||
| 415 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 | ||
| 416 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 | ||
| 417 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 | ||
| 418 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 | ||
| 419 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 | ||
| 420 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 | ||
| 421 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 | ||
| 422 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 | ||
| 423 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 | ||
| 424 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 | ||
| 425 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 | ||
| 426 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 | ||
| 427 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 | ||
| 428 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 | ||
| 429 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 | ||
| 430 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 | ||
| 431 | #define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 | ||
| 432 | #define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 | ||
| 433 | #define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 | ||
| 434 | #define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 | ||
| 435 | #define reg_gio_rw_i2c0_ctrl___start_bit___width 1 | ||
| 436 | #define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 | ||
| 437 | #define reg_gio_rw_i2c0_ctrl___freq___lsb 25 | ||
| 438 | #define reg_gio_rw_i2c0_ctrl___freq___width 2 | ||
| 439 | #define reg_gio_rw_i2c0_ctrl_offset 152 | ||
| 440 | |||
| 441 | /* Register rw_i2c0_data, scope gio, type rw */ | ||
| 442 | #define reg_gio_rw_i2c0_data___data0___lsb 0 | ||
| 443 | #define reg_gio_rw_i2c0_data___data0___width 8 | ||
| 444 | #define reg_gio_rw_i2c0_data___data1___lsb 8 | ||
| 445 | #define reg_gio_rw_i2c0_data___data1___width 8 | ||
| 446 | #define reg_gio_rw_i2c0_data___data2___lsb 16 | ||
| 447 | #define reg_gio_rw_i2c0_data___data2___width 8 | ||
| 448 | #define reg_gio_rw_i2c0_data___data3___lsb 24 | ||
| 449 | #define reg_gio_rw_i2c0_data___data3___width 8 | ||
| 450 | #define reg_gio_rw_i2c0_data_offset 156 | ||
| 451 | |||
| 452 | /* Register rw_i2c0_data2, scope gio, type rw */ | ||
| 453 | #define reg_gio_rw_i2c0_data2___data4___lsb 0 | ||
| 454 | #define reg_gio_rw_i2c0_data2___data4___width 8 | ||
| 455 | #define reg_gio_rw_i2c0_data2___data5___lsb 8 | ||
| 456 | #define reg_gio_rw_i2c0_data2___data5___width 8 | ||
| 457 | #define reg_gio_rw_i2c0_data2___start_val___lsb 16 | ||
| 458 | #define reg_gio_rw_i2c0_data2___start_val___width 6 | ||
| 459 | #define reg_gio_rw_i2c0_data2___ack_val___lsb 22 | ||
| 460 | #define reg_gio_rw_i2c0_data2___ack_val___width 6 | ||
| 461 | #define reg_gio_rw_i2c0_data2_offset 160 | ||
| 462 | |||
| 463 | /* Register rw_i2c1_start, scope gio, type rw */ | ||
| 464 | #define reg_gio_rw_i2c1_start___run___lsb 0 | ||
| 465 | #define reg_gio_rw_i2c1_start___run___width 1 | ||
| 466 | #define reg_gio_rw_i2c1_start___run___bit 0 | ||
| 467 | #define reg_gio_rw_i2c1_start_offset 164 | ||
| 468 | |||
| 469 | /* Register rw_i2c1_cfg, scope gio, type rw */ | ||
| 470 | #define reg_gio_rw_i2c1_cfg___en___lsb 0 | ||
| 471 | #define reg_gio_rw_i2c1_cfg___en___width 1 | ||
| 472 | #define reg_gio_rw_i2c1_cfg___en___bit 0 | ||
| 473 | #define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 | ||
| 474 | #define reg_gio_rw_i2c1_cfg___bit_order___width 1 | ||
| 475 | #define reg_gio_rw_i2c1_cfg___bit_order___bit 1 | ||
| 476 | #define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 | ||
| 477 | #define reg_gio_rw_i2c1_cfg___scl_io___width 1 | ||
| 478 | #define reg_gio_rw_i2c1_cfg___scl_io___bit 2 | ||
| 479 | #define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 | ||
| 480 | #define reg_gio_rw_i2c1_cfg___scl_inv___width 1 | ||
| 481 | #define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 | ||
| 482 | #define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 | ||
| 483 | #define reg_gio_rw_i2c1_cfg___sda0_io___width 1 | ||
| 484 | #define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 | ||
| 485 | #define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 | ||
| 486 | #define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 | ||
| 487 | #define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 | ||
| 488 | #define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 | ||
| 489 | #define reg_gio_rw_i2c1_cfg___sda1_io___width 1 | ||
| 490 | #define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 | ||
| 491 | #define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 | ||
| 492 | #define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 | ||
| 493 | #define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 | ||
| 494 | #define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 | ||
| 495 | #define reg_gio_rw_i2c1_cfg___sda2_io___width 1 | ||
| 496 | #define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 | ||
| 497 | #define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 | ||
| 498 | #define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 | ||
| 499 | #define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 | ||
| 500 | #define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 | ||
| 501 | #define reg_gio_rw_i2c1_cfg___sda3_io___width 1 | ||
| 502 | #define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 | ||
| 503 | #define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 | ||
| 504 | #define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 | ||
| 505 | #define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 | ||
| 506 | #define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 | ||
| 507 | #define reg_gio_rw_i2c1_cfg___sda_sel___width 2 | ||
| 508 | #define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 | ||
| 509 | #define reg_gio_rw_i2c1_cfg___sen_idle___width 1 | ||
| 510 | #define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 | ||
| 511 | #define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 | ||
| 512 | #define reg_gio_rw_i2c1_cfg___sen_inv___width 1 | ||
| 513 | #define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 | ||
| 514 | #define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 | ||
| 515 | #define reg_gio_rw_i2c1_cfg___sen_sel___width 2 | ||
| 516 | #define reg_gio_rw_i2c1_cfg_offset 168 | ||
| 517 | |||
| 518 | /* Register rw_i2c1_ctrl, scope gio, type rw */ | ||
| 519 | #define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 | ||
| 520 | #define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 | ||
| 521 | #define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 | ||
| 522 | #define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 | ||
| 523 | #define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 | ||
| 524 | #define reg_gio_rw_i2c1_ctrl___extra_start___width 3 | ||
| 525 | #define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 | ||
| 526 | #define reg_gio_rw_i2c1_ctrl___early_end___width 1 | ||
| 527 | #define reg_gio_rw_i2c1_ctrl___early_end___bit 15 | ||
| 528 | #define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 | ||
| 529 | #define reg_gio_rw_i2c1_ctrl___start_stop___width 1 | ||
| 530 | #define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 | ||
| 531 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 | ||
| 532 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 | ||
| 533 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 | ||
| 534 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 | ||
| 535 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 | ||
| 536 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 | ||
| 537 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 | ||
| 538 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 | ||
| 539 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 | ||
| 540 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 | ||
| 541 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 | ||
| 542 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 | ||
| 543 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 | ||
| 544 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 | ||
| 545 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 | ||
| 546 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 | ||
| 547 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 | ||
| 548 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 | ||
| 549 | #define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 | ||
| 550 | #define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 | ||
| 551 | #define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 | ||
| 552 | #define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 | ||
| 553 | #define reg_gio_rw_i2c1_ctrl___start_bit___width 1 | ||
| 554 | #define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 | ||
| 555 | #define reg_gio_rw_i2c1_ctrl___freq___lsb 25 | ||
| 556 | #define reg_gio_rw_i2c1_ctrl___freq___width 2 | ||
| 557 | #define reg_gio_rw_i2c1_ctrl_offset 172 | ||
| 558 | |||
| 559 | /* Register rw_i2c1_data, scope gio, type rw */ | ||
| 560 | #define reg_gio_rw_i2c1_data___data0___lsb 0 | ||
| 561 | #define reg_gio_rw_i2c1_data___data0___width 8 | ||
| 562 | #define reg_gio_rw_i2c1_data___data1___lsb 8 | ||
| 563 | #define reg_gio_rw_i2c1_data___data1___width 8 | ||
| 564 | #define reg_gio_rw_i2c1_data___data2___lsb 16 | ||
| 565 | #define reg_gio_rw_i2c1_data___data2___width 8 | ||
| 566 | #define reg_gio_rw_i2c1_data___data3___lsb 24 | ||
| 567 | #define reg_gio_rw_i2c1_data___data3___width 8 | ||
| 568 | #define reg_gio_rw_i2c1_data_offset 176 | ||
| 569 | |||
| 570 | /* Register rw_i2c1_data2, scope gio, type rw */ | ||
| 571 | #define reg_gio_rw_i2c1_data2___data4___lsb 0 | ||
| 572 | #define reg_gio_rw_i2c1_data2___data4___width 8 | ||
| 573 | #define reg_gio_rw_i2c1_data2___data5___lsb 8 | ||
| 574 | #define reg_gio_rw_i2c1_data2___data5___width 8 | ||
| 575 | #define reg_gio_rw_i2c1_data2___start_val___lsb 16 | ||
| 576 | #define reg_gio_rw_i2c1_data2___start_val___width 6 | ||
| 577 | #define reg_gio_rw_i2c1_data2___ack_val___lsb 22 | ||
| 578 | #define reg_gio_rw_i2c1_data2___ack_val___width 6 | ||
| 579 | #define reg_gio_rw_i2c1_data2_offset 180 | ||
| 580 | |||
| 581 | /* Register r_ppwm_stat, scope gio, type r */ | ||
| 582 | #define reg_gio_r_ppwm_stat___freq___lsb 0 | ||
| 583 | #define reg_gio_r_ppwm_stat___freq___width 2 | ||
| 584 | #define reg_gio_r_ppwm_stat_offset 184 | ||
| 585 | |||
| 586 | /* Register rw_ppwm_data, scope gio, type rw */ | ||
| 587 | #define reg_gio_rw_ppwm_data___data___lsb 0 | ||
| 588 | #define reg_gio_rw_ppwm_data___data___width 8 | ||
| 589 | #define reg_gio_rw_ppwm_data_offset 188 | ||
| 590 | |||
| 591 | /* Register rw_pwm0_ctrl, scope gio, type rw */ | ||
| 592 | #define reg_gio_rw_pwm0_ctrl___mode___lsb 0 | ||
| 593 | #define reg_gio_rw_pwm0_ctrl___mode___width 2 | ||
| 594 | #define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 | ||
| 595 | #define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 | ||
| 596 | #define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 | ||
| 597 | #define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 | ||
| 598 | #define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 | ||
| 599 | #define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 | ||
| 600 | #define reg_gio_rw_pwm0_ctrl_offset 192 | ||
| 601 | |||
| 602 | /* Register rw_pwm0_var, scope gio, type rw */ | ||
| 603 | #define reg_gio_rw_pwm0_var___lo___lsb 0 | ||
| 604 | #define reg_gio_rw_pwm0_var___lo___width 13 | ||
| 605 | #define reg_gio_rw_pwm0_var___hi___lsb 13 | ||
| 606 | #define reg_gio_rw_pwm0_var___hi___width 13 | ||
| 607 | #define reg_gio_rw_pwm0_var_offset 196 | ||
| 608 | |||
| 609 | /* Register rw_pwm0_data, scope gio, type rw */ | ||
| 610 | #define reg_gio_rw_pwm0_data___data___lsb 0 | ||
| 611 | #define reg_gio_rw_pwm0_data___data___width 8 | ||
| 612 | #define reg_gio_rw_pwm0_data_offset 200 | ||
| 613 | |||
| 614 | /* Register rw_pwm1_ctrl, scope gio, type rw */ | ||
| 615 | #define reg_gio_rw_pwm1_ctrl___mode___lsb 0 | ||
| 616 | #define reg_gio_rw_pwm1_ctrl___mode___width 2 | ||
| 617 | #define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 | ||
| 618 | #define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 | ||
| 619 | #define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 | ||
| 620 | #define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 | ||
| 621 | #define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 | ||
| 622 | #define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 | ||
| 623 | #define reg_gio_rw_pwm1_ctrl_offset 204 | ||
| 624 | |||
| 625 | /* Register rw_pwm1_var, scope gio, type rw */ | ||
| 626 | #define reg_gio_rw_pwm1_var___lo___lsb 0 | ||
| 627 | #define reg_gio_rw_pwm1_var___lo___width 13 | ||
| 628 | #define reg_gio_rw_pwm1_var___hi___lsb 13 | ||
| 629 | #define reg_gio_rw_pwm1_var___hi___width 13 | ||
| 630 | #define reg_gio_rw_pwm1_var_offset 208 | ||
| 631 | |||
| 632 | /* Register rw_pwm1_data, scope gio, type rw */ | ||
| 633 | #define reg_gio_rw_pwm1_data___data___lsb 0 | ||
| 634 | #define reg_gio_rw_pwm1_data___data___width 8 | ||
| 635 | #define reg_gio_rw_pwm1_data_offset 212 | ||
| 636 | |||
| 637 | /* Register rw_pwm2_ctrl, scope gio, type rw */ | ||
| 638 | #define reg_gio_rw_pwm2_ctrl___mode___lsb 0 | ||
| 639 | #define reg_gio_rw_pwm2_ctrl___mode___width 2 | ||
| 640 | #define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 | ||
| 641 | #define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 | ||
| 642 | #define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 | ||
| 643 | #define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 | ||
| 644 | #define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 | ||
| 645 | #define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 | ||
| 646 | #define reg_gio_rw_pwm2_ctrl_offset 216 | ||
| 647 | |||
| 648 | /* Register rw_pwm2_var, scope gio, type rw */ | ||
| 649 | #define reg_gio_rw_pwm2_var___lo___lsb 0 | ||
| 650 | #define reg_gio_rw_pwm2_var___lo___width 13 | ||
| 651 | #define reg_gio_rw_pwm2_var___hi___lsb 13 | ||
| 652 | #define reg_gio_rw_pwm2_var___hi___width 13 | ||
| 653 | #define reg_gio_rw_pwm2_var_offset 220 | ||
| 654 | |||
| 655 | /* Register rw_pwm2_data, scope gio, type rw */ | ||
| 656 | #define reg_gio_rw_pwm2_data___data___lsb 0 | ||
| 657 | #define reg_gio_rw_pwm2_data___data___width 8 | ||
| 658 | #define reg_gio_rw_pwm2_data_offset 224 | ||
| 659 | |||
| 660 | /* Register rw_pwm_in_cfg, scope gio, type rw */ | ||
| 661 | #define reg_gio_rw_pwm_in_cfg___pin___lsb 0 | ||
| 662 | #define reg_gio_rw_pwm_in_cfg___pin___width 3 | ||
| 663 | #define reg_gio_rw_pwm_in_cfg_offset 228 | ||
| 664 | |||
| 665 | /* Register r_pwm_in_lo, scope gio, type r */ | ||
| 666 | #define reg_gio_r_pwm_in_lo___data___lsb 0 | ||
| 667 | #define reg_gio_r_pwm_in_lo___data___width 32 | ||
| 668 | #define reg_gio_r_pwm_in_lo_offset 232 | ||
| 669 | |||
| 670 | /* Register r_pwm_in_hi, scope gio, type r */ | ||
| 671 | #define reg_gio_r_pwm_in_hi___data___lsb 0 | ||
| 672 | #define reg_gio_r_pwm_in_hi___data___width 32 | ||
| 673 | #define reg_gio_r_pwm_in_hi_offset 236 | ||
| 674 | |||
| 675 | /* Register r_pwm_in_cnt, scope gio, type r */ | ||
| 676 | #define reg_gio_r_pwm_in_cnt___data___lsb 0 | ||
| 677 | #define reg_gio_r_pwm_in_cnt___data___width 32 | ||
| 678 | #define reg_gio_r_pwm_in_cnt_offset 240 | ||
| 679 | |||
| 680 | |||
| 681 | /* Constants */ | ||
| 682 | #define regk_gio_anyedge 0x00000007 | ||
| 683 | #define regk_gio_f100k 0x00000000 | ||
| 684 | #define regk_gio_f1562 0x00000000 | ||
| 685 | #define regk_gio_f195 0x00000003 | ||
| 686 | #define regk_gio_f1m 0x00000002 | ||
| 687 | #define regk_gio_f390 0x00000002 | ||
| 688 | #define regk_gio_f400k 0x00000001 | ||
| 689 | #define regk_gio_f5m 0x00000003 | ||
| 690 | #define regk_gio_f781 0x00000001 | ||
| 691 | #define regk_gio_hi 0x00000001 | ||
| 692 | #define regk_gio_in 0x00000000 | ||
| 693 | #define regk_gio_intr_pa0 0x00000000 | ||
| 694 | #define regk_gio_intr_pa1 0x00000000 | ||
| 695 | #define regk_gio_intr_pa10 0x00000001 | ||
| 696 | #define regk_gio_intr_pa11 0x00000001 | ||
| 697 | #define regk_gio_intr_pa12 0x00000001 | ||
| 698 | #define regk_gio_intr_pa13 0x00000001 | ||
| 699 | #define regk_gio_intr_pa14 0x00000001 | ||
| 700 | #define regk_gio_intr_pa15 0x00000001 | ||
| 701 | #define regk_gio_intr_pa16 0x00000002 | ||
| 702 | #define regk_gio_intr_pa17 0x00000002 | ||
| 703 | #define regk_gio_intr_pa18 0x00000002 | ||
| 704 | #define regk_gio_intr_pa19 0x00000002 | ||
| 705 | #define regk_gio_intr_pa2 0x00000000 | ||
| 706 | #define regk_gio_intr_pa20 0x00000002 | ||
| 707 | #define regk_gio_intr_pa21 0x00000002 | ||
| 708 | #define regk_gio_intr_pa22 0x00000002 | ||
| 709 | #define regk_gio_intr_pa23 0x00000002 | ||
| 710 | #define regk_gio_intr_pa24 0x00000003 | ||
| 711 | #define regk_gio_intr_pa25 0x00000003 | ||
| 712 | #define regk_gio_intr_pa26 0x00000003 | ||
| 713 | #define regk_gio_intr_pa27 0x00000003 | ||
| 714 | #define regk_gio_intr_pa28 0x00000003 | ||
| 715 | #define regk_gio_intr_pa29 0x00000003 | ||
| 716 | #define regk_gio_intr_pa3 0x00000000 | ||
| 717 | #define regk_gio_intr_pa30 0x00000003 | ||
| 718 | #define regk_gio_intr_pa31 0x00000003 | ||
| 719 | #define regk_gio_intr_pa4 0x00000000 | ||
| 720 | #define regk_gio_intr_pa5 0x00000000 | ||
| 721 | #define regk_gio_intr_pa6 0x00000000 | ||
| 722 | #define regk_gio_intr_pa7 0x00000000 | ||
| 723 | #define regk_gio_intr_pa8 0x00000001 | ||
| 724 | #define regk_gio_intr_pa9 0x00000001 | ||
| 725 | #define regk_gio_intr_pb0 0x00000004 | ||
| 726 | #define regk_gio_intr_pb1 0x00000004 | ||
| 727 | #define regk_gio_intr_pb10 0x00000005 | ||
| 728 | #define regk_gio_intr_pb11 0x00000005 | ||
| 729 | #define regk_gio_intr_pb12 0x00000005 | ||
| 730 | #define regk_gio_intr_pb13 0x00000005 | ||
| 731 | #define regk_gio_intr_pb14 0x00000005 | ||
| 732 | #define regk_gio_intr_pb15 0x00000005 | ||
| 733 | #define regk_gio_intr_pb16 0x00000006 | ||
| 734 | #define regk_gio_intr_pb17 0x00000006 | ||
| 735 | #define regk_gio_intr_pb18 0x00000006 | ||
| 736 | #define regk_gio_intr_pb19 0x00000006 | ||
| 737 | #define regk_gio_intr_pb2 0x00000004 | ||
| 738 | #define regk_gio_intr_pb20 0x00000006 | ||
| 739 | #define regk_gio_intr_pb21 0x00000006 | ||
| 740 | #define regk_gio_intr_pb22 0x00000006 | ||
| 741 | #define regk_gio_intr_pb23 0x00000006 | ||
| 742 | #define regk_gio_intr_pb24 0x00000007 | ||
| 743 | #define regk_gio_intr_pb25 0x00000007 | ||
| 744 | #define regk_gio_intr_pb26 0x00000007 | ||
| 745 | #define regk_gio_intr_pb27 0x00000007 | ||
| 746 | #define regk_gio_intr_pb28 0x00000007 | ||
| 747 | #define regk_gio_intr_pb29 0x00000007 | ||
| 748 | #define regk_gio_intr_pb3 0x00000004 | ||
| 749 | #define regk_gio_intr_pb30 0x00000007 | ||
| 750 | #define regk_gio_intr_pb31 0x00000007 | ||
| 751 | #define regk_gio_intr_pb4 0x00000004 | ||
| 752 | #define regk_gio_intr_pb5 0x00000004 | ||
| 753 | #define regk_gio_intr_pb6 0x00000004 | ||
| 754 | #define regk_gio_intr_pb7 0x00000004 | ||
| 755 | #define regk_gio_intr_pb8 0x00000005 | ||
| 756 | #define regk_gio_intr_pb9 0x00000005 | ||
| 757 | #define regk_gio_intr_pc0 0x00000008 | ||
| 758 | #define regk_gio_intr_pc1 0x00000008 | ||
| 759 | #define regk_gio_intr_pc10 0x00000009 | ||
| 760 | #define regk_gio_intr_pc11 0x00000009 | ||
| 761 | #define regk_gio_intr_pc12 0x00000009 | ||
| 762 | #define regk_gio_intr_pc13 0x00000009 | ||
| 763 | #define regk_gio_intr_pc14 0x00000009 | ||
| 764 | #define regk_gio_intr_pc15 0x00000009 | ||
| 765 | #define regk_gio_intr_pc2 0x00000008 | ||
| 766 | #define regk_gio_intr_pc3 0x00000008 | ||
| 767 | #define regk_gio_intr_pc4 0x00000008 | ||
| 768 | #define regk_gio_intr_pc5 0x00000008 | ||
| 769 | #define regk_gio_intr_pc6 0x00000008 | ||
| 770 | #define regk_gio_intr_pc7 0x00000008 | ||
| 771 | #define regk_gio_intr_pc8 0x00000009 | ||
| 772 | #define regk_gio_intr_pc9 0x00000009 | ||
| 773 | #define regk_gio_intr_pd0 0x0000000c | ||
| 774 | #define regk_gio_intr_pd1 0x0000000c | ||
| 775 | #define regk_gio_intr_pd10 0x0000000d | ||
| 776 | #define regk_gio_intr_pd11 0x0000000d | ||
| 777 | #define regk_gio_intr_pd12 0x0000000d | ||
| 778 | #define regk_gio_intr_pd13 0x0000000d | ||
| 779 | #define regk_gio_intr_pd14 0x0000000d | ||
| 780 | #define regk_gio_intr_pd15 0x0000000d | ||
| 781 | #define regk_gio_intr_pd16 0x0000000e | ||
| 782 | #define regk_gio_intr_pd17 0x0000000e | ||
| 783 | #define regk_gio_intr_pd18 0x0000000e | ||
| 784 | #define regk_gio_intr_pd19 0x0000000e | ||
| 785 | #define regk_gio_intr_pd2 0x0000000c | ||
| 786 | #define regk_gio_intr_pd20 0x0000000e | ||
| 787 | #define regk_gio_intr_pd21 0x0000000e | ||
| 788 | #define regk_gio_intr_pd22 0x0000000e | ||
| 789 | #define regk_gio_intr_pd23 0x0000000e | ||
| 790 | #define regk_gio_intr_pd24 0x0000000f | ||
| 791 | #define regk_gio_intr_pd25 0x0000000f | ||
| 792 | #define regk_gio_intr_pd26 0x0000000f | ||
| 793 | #define regk_gio_intr_pd27 0x0000000f | ||
| 794 | #define regk_gio_intr_pd28 0x0000000f | ||
| 795 | #define regk_gio_intr_pd29 0x0000000f | ||
| 796 | #define regk_gio_intr_pd3 0x0000000c | ||
| 797 | #define regk_gio_intr_pd30 0x0000000f | ||
| 798 | #define regk_gio_intr_pd31 0x0000000f | ||
| 799 | #define regk_gio_intr_pd4 0x0000000c | ||
| 800 | #define regk_gio_intr_pd5 0x0000000c | ||
| 801 | #define regk_gio_intr_pd6 0x0000000c | ||
| 802 | #define regk_gio_intr_pd7 0x0000000c | ||
| 803 | #define regk_gio_intr_pd8 0x0000000d | ||
| 804 | #define regk_gio_intr_pd9 0x0000000d | ||
| 805 | #define regk_gio_lo 0x00000002 | ||
| 806 | #define regk_gio_lsb 0x00000000 | ||
| 807 | #define regk_gio_msb 0x00000001 | ||
| 808 | #define regk_gio_negedge 0x00000006 | ||
| 809 | #define regk_gio_no 0x00000000 | ||
| 810 | #define regk_gio_no_switch 0x0000003f | ||
| 811 | #define regk_gio_none 0x00000007 | ||
| 812 | #define regk_gio_off 0x00000000 | ||
| 813 | #define regk_gio_opendrain 0x00000000 | ||
| 814 | #define regk_gio_out 0x00000001 | ||
| 815 | #define regk_gio_posedge 0x00000005 | ||
| 816 | #define regk_gio_pwm_hfp 0x00000002 | ||
| 817 | #define regk_gio_pwm_pa0 0x00000001 | ||
| 818 | #define regk_gio_pwm_pa19 0x00000004 | ||
| 819 | #define regk_gio_pwm_pa6 0x00000002 | ||
| 820 | #define regk_gio_pwm_pa7 0x00000003 | ||
| 821 | #define regk_gio_pwm_pb26 0x00000005 | ||
| 822 | #define regk_gio_pwm_pd23 0x00000006 | ||
| 823 | #define regk_gio_pwm_pd31 0x00000007 | ||
| 824 | #define regk_gio_pwm_std 0x00000001 | ||
| 825 | #define regk_gio_pwm_var 0x00000003 | ||
| 826 | #define regk_gio_rw_i2c0_cfg_default 0x00000020 | ||
| 827 | #define regk_gio_rw_i2c0_ctrl_default 0x00010000 | ||
| 828 | #define regk_gio_rw_i2c0_start_default 0x00000000 | ||
| 829 | #define regk_gio_rw_i2c1_cfg_default 0x00000aa0 | ||
| 830 | #define regk_gio_rw_i2c1_ctrl_default 0x00010000 | ||
| 831 | #define regk_gio_rw_i2c1_start_default 0x00000000 | ||
| 832 | #define regk_gio_rw_intr_cfg_default 0x00000000 | ||
| 833 | #define regk_gio_rw_intr_mask_default 0x00000000 | ||
| 834 | #define regk_gio_rw_pa_oe_default 0x00000000 | ||
| 835 | #define regk_gio_rw_pb_oe_default 0x00000000 | ||
| 836 | #define regk_gio_rw_pc_oe_default 0x00000000 | ||
| 837 | #define regk_gio_rw_ppwm_data_default 0x00000000 | ||
| 838 | #define regk_gio_rw_pwm0_ctrl_default 0x00000000 | ||
| 839 | #define regk_gio_rw_pwm1_ctrl_default 0x00000000 | ||
| 840 | #define regk_gio_rw_pwm2_ctrl_default 0x00000000 | ||
| 841 | #define regk_gio_rw_pwm_in_cfg_default 0x00000000 | ||
| 842 | #define regk_gio_sda0 0x00000000 | ||
| 843 | #define regk_gio_sda1 0x00000001 | ||
| 844 | #define regk_gio_sda2 0x00000002 | ||
| 845 | #define regk_gio_sda3 0x00000003 | ||
| 846 | #define regk_gio_sen 0x00000000 | ||
| 847 | #define regk_gio_set 0x00000003 | ||
| 848 | #define regk_gio_yes 0x00000001 | ||
| 849 | #endif /* __gio_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index c3dc9c666c46..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h +++ /dev/null | |||
| @@ -1,572 +0,0 @@ | |||
| 1 | #ifndef __pinmux_defs_asm_h | ||
| 2 | #define __pinmux_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: pinmux.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 54 | #define reg_pinmux_rw_hwprot___eth___lsb 0 | ||
| 55 | #define reg_pinmux_rw_hwprot___eth___width 1 | ||
| 56 | #define reg_pinmux_rw_hwprot___eth___bit 0 | ||
| 57 | #define reg_pinmux_rw_hwprot___eth_mdio___lsb 1 | ||
| 58 | #define reg_pinmux_rw_hwprot___eth_mdio___width 1 | ||
| 59 | #define reg_pinmux_rw_hwprot___eth_mdio___bit 1 | ||
| 60 | #define reg_pinmux_rw_hwprot___geth___lsb 2 | ||
| 61 | #define reg_pinmux_rw_hwprot___geth___width 1 | ||
| 62 | #define reg_pinmux_rw_hwprot___geth___bit 2 | ||
| 63 | #define reg_pinmux_rw_hwprot___tg___lsb 3 | ||
| 64 | #define reg_pinmux_rw_hwprot___tg___width 1 | ||
| 65 | #define reg_pinmux_rw_hwprot___tg___bit 3 | ||
| 66 | #define reg_pinmux_rw_hwprot___tg_clk___lsb 4 | ||
| 67 | #define reg_pinmux_rw_hwprot___tg_clk___width 1 | ||
| 68 | #define reg_pinmux_rw_hwprot___tg_clk___bit 4 | ||
| 69 | #define reg_pinmux_rw_hwprot___vout___lsb 5 | ||
| 70 | #define reg_pinmux_rw_hwprot___vout___width 1 | ||
| 71 | #define reg_pinmux_rw_hwprot___vout___bit 5 | ||
| 72 | #define reg_pinmux_rw_hwprot___vout_sync___lsb 6 | ||
| 73 | #define reg_pinmux_rw_hwprot___vout_sync___width 1 | ||
| 74 | #define reg_pinmux_rw_hwprot___vout_sync___bit 6 | ||
| 75 | #define reg_pinmux_rw_hwprot___ser1___lsb 7 | ||
| 76 | #define reg_pinmux_rw_hwprot___ser1___width 1 | ||
| 77 | #define reg_pinmux_rw_hwprot___ser1___bit 7 | ||
| 78 | #define reg_pinmux_rw_hwprot___ser2___lsb 8 | ||
| 79 | #define reg_pinmux_rw_hwprot___ser2___width 1 | ||
| 80 | #define reg_pinmux_rw_hwprot___ser2___bit 8 | ||
| 81 | #define reg_pinmux_rw_hwprot___ser3___lsb 9 | ||
| 82 | #define reg_pinmux_rw_hwprot___ser3___width 1 | ||
| 83 | #define reg_pinmux_rw_hwprot___ser3___bit 9 | ||
| 84 | #define reg_pinmux_rw_hwprot___ser4___lsb 10 | ||
| 85 | #define reg_pinmux_rw_hwprot___ser4___width 1 | ||
| 86 | #define reg_pinmux_rw_hwprot___ser4___bit 10 | ||
| 87 | #define reg_pinmux_rw_hwprot___sser___lsb 11 | ||
| 88 | #define reg_pinmux_rw_hwprot___sser___width 1 | ||
| 89 | #define reg_pinmux_rw_hwprot___sser___bit 11 | ||
| 90 | #define reg_pinmux_rw_hwprot___pwm0___lsb 12 | ||
| 91 | #define reg_pinmux_rw_hwprot___pwm0___width 1 | ||
| 92 | #define reg_pinmux_rw_hwprot___pwm0___bit 12 | ||
| 93 | #define reg_pinmux_rw_hwprot___pwm1___lsb 13 | ||
| 94 | #define reg_pinmux_rw_hwprot___pwm1___width 1 | ||
| 95 | #define reg_pinmux_rw_hwprot___pwm1___bit 13 | ||
| 96 | #define reg_pinmux_rw_hwprot___pwm2___lsb 14 | ||
| 97 | #define reg_pinmux_rw_hwprot___pwm2___width 1 | ||
| 98 | #define reg_pinmux_rw_hwprot___pwm2___bit 14 | ||
| 99 | #define reg_pinmux_rw_hwprot___timer0___lsb 15 | ||
| 100 | #define reg_pinmux_rw_hwprot___timer0___width 1 | ||
| 101 | #define reg_pinmux_rw_hwprot___timer0___bit 15 | ||
| 102 | #define reg_pinmux_rw_hwprot___timer1___lsb 16 | ||
| 103 | #define reg_pinmux_rw_hwprot___timer1___width 1 | ||
| 104 | #define reg_pinmux_rw_hwprot___timer1___bit 16 | ||
| 105 | #define reg_pinmux_rw_hwprot___pio___lsb 17 | ||
| 106 | #define reg_pinmux_rw_hwprot___pio___width 1 | ||
| 107 | #define reg_pinmux_rw_hwprot___pio___bit 17 | ||
| 108 | #define reg_pinmux_rw_hwprot___i2c0___lsb 18 | ||
| 109 | #define reg_pinmux_rw_hwprot___i2c0___width 1 | ||
| 110 | #define reg_pinmux_rw_hwprot___i2c0___bit 18 | ||
| 111 | #define reg_pinmux_rw_hwprot___i2c1___lsb 19 | ||
| 112 | #define reg_pinmux_rw_hwprot___i2c1___width 1 | ||
| 113 | #define reg_pinmux_rw_hwprot___i2c1___bit 19 | ||
| 114 | #define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20 | ||
| 115 | #define reg_pinmux_rw_hwprot___i2c1_sda1___width 1 | ||
| 116 | #define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20 | ||
| 117 | #define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21 | ||
| 118 | #define reg_pinmux_rw_hwprot___i2c1_sda2___width 1 | ||
| 119 | #define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21 | ||
| 120 | #define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22 | ||
| 121 | #define reg_pinmux_rw_hwprot___i2c1_sda3___width 1 | ||
| 122 | #define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22 | ||
| 123 | #define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23 | ||
| 124 | #define reg_pinmux_rw_hwprot___i2c1_sen___width 1 | ||
| 125 | #define reg_pinmux_rw_hwprot___i2c1_sen___bit 23 | ||
| 126 | #define reg_pinmux_rw_hwprot_offset 0 | ||
| 127 | |||
| 128 | /* Register rw_gio_pa, scope pinmux, type rw */ | ||
| 129 | #define reg_pinmux_rw_gio_pa___pa0___lsb 0 | ||
| 130 | #define reg_pinmux_rw_gio_pa___pa0___width 1 | ||
| 131 | #define reg_pinmux_rw_gio_pa___pa0___bit 0 | ||
| 132 | #define reg_pinmux_rw_gio_pa___pa1___lsb 1 | ||
| 133 | #define reg_pinmux_rw_gio_pa___pa1___width 1 | ||
| 134 | #define reg_pinmux_rw_gio_pa___pa1___bit 1 | ||
| 135 | #define reg_pinmux_rw_gio_pa___pa2___lsb 2 | ||
| 136 | #define reg_pinmux_rw_gio_pa___pa2___width 1 | ||
| 137 | #define reg_pinmux_rw_gio_pa___pa2___bit 2 | ||
| 138 | #define reg_pinmux_rw_gio_pa___pa3___lsb 3 | ||
| 139 | #define reg_pinmux_rw_gio_pa___pa3___width 1 | ||
| 140 | #define reg_pinmux_rw_gio_pa___pa3___bit 3 | ||
| 141 | #define reg_pinmux_rw_gio_pa___pa4___lsb 4 | ||
| 142 | #define reg_pinmux_rw_gio_pa___pa4___width 1 | ||
| 143 | #define reg_pinmux_rw_gio_pa___pa4___bit 4 | ||
| 144 | #define reg_pinmux_rw_gio_pa___pa5___lsb 5 | ||
| 145 | #define reg_pinmux_rw_gio_pa___pa5___width 1 | ||
| 146 | #define reg_pinmux_rw_gio_pa___pa5___bit 5 | ||
| 147 | #define reg_pinmux_rw_gio_pa___pa6___lsb 6 | ||
| 148 | #define reg_pinmux_rw_gio_pa___pa6___width 1 | ||
| 149 | #define reg_pinmux_rw_gio_pa___pa6___bit 6 | ||
| 150 | #define reg_pinmux_rw_gio_pa___pa7___lsb 7 | ||
| 151 | #define reg_pinmux_rw_gio_pa___pa7___width 1 | ||
| 152 | #define reg_pinmux_rw_gio_pa___pa7___bit 7 | ||
| 153 | #define reg_pinmux_rw_gio_pa___pa8___lsb 8 | ||
| 154 | #define reg_pinmux_rw_gio_pa___pa8___width 1 | ||
| 155 | #define reg_pinmux_rw_gio_pa___pa8___bit 8 | ||
| 156 | #define reg_pinmux_rw_gio_pa___pa9___lsb 9 | ||
| 157 | #define reg_pinmux_rw_gio_pa___pa9___width 1 | ||
| 158 | #define reg_pinmux_rw_gio_pa___pa9___bit 9 | ||
| 159 | #define reg_pinmux_rw_gio_pa___pa10___lsb 10 | ||
| 160 | #define reg_pinmux_rw_gio_pa___pa10___width 1 | ||
| 161 | #define reg_pinmux_rw_gio_pa___pa10___bit 10 | ||
| 162 | #define reg_pinmux_rw_gio_pa___pa11___lsb 11 | ||
| 163 | #define reg_pinmux_rw_gio_pa___pa11___width 1 | ||
| 164 | #define reg_pinmux_rw_gio_pa___pa11___bit 11 | ||
| 165 | #define reg_pinmux_rw_gio_pa___pa12___lsb 12 | ||
| 166 | #define reg_pinmux_rw_gio_pa___pa12___width 1 | ||
| 167 | #define reg_pinmux_rw_gio_pa___pa12___bit 12 | ||
| 168 | #define reg_pinmux_rw_gio_pa___pa13___lsb 13 | ||
| 169 | #define reg_pinmux_rw_gio_pa___pa13___width 1 | ||
| 170 | #define reg_pinmux_rw_gio_pa___pa13___bit 13 | ||
| 171 | #define reg_pinmux_rw_gio_pa___pa14___lsb 14 | ||
| 172 | #define reg_pinmux_rw_gio_pa___pa14___width 1 | ||
| 173 | #define reg_pinmux_rw_gio_pa___pa14___bit 14 | ||
| 174 | #define reg_pinmux_rw_gio_pa___pa15___lsb 15 | ||
| 175 | #define reg_pinmux_rw_gio_pa___pa15___width 1 | ||
| 176 | #define reg_pinmux_rw_gio_pa___pa15___bit 15 | ||
| 177 | #define reg_pinmux_rw_gio_pa___pa16___lsb 16 | ||
| 178 | #define reg_pinmux_rw_gio_pa___pa16___width 1 | ||
| 179 | #define reg_pinmux_rw_gio_pa___pa16___bit 16 | ||
| 180 | #define reg_pinmux_rw_gio_pa___pa17___lsb 17 | ||
| 181 | #define reg_pinmux_rw_gio_pa___pa17___width 1 | ||
| 182 | #define reg_pinmux_rw_gio_pa___pa17___bit 17 | ||
| 183 | #define reg_pinmux_rw_gio_pa___pa18___lsb 18 | ||
| 184 | #define reg_pinmux_rw_gio_pa___pa18___width 1 | ||
| 185 | #define reg_pinmux_rw_gio_pa___pa18___bit 18 | ||
| 186 | #define reg_pinmux_rw_gio_pa___pa19___lsb 19 | ||
| 187 | #define reg_pinmux_rw_gio_pa___pa19___width 1 | ||
| 188 | #define reg_pinmux_rw_gio_pa___pa19___bit 19 | ||
| 189 | #define reg_pinmux_rw_gio_pa___pa20___lsb 20 | ||
| 190 | #define reg_pinmux_rw_gio_pa___pa20___width 1 | ||
| 191 | #define reg_pinmux_rw_gio_pa___pa20___bit 20 | ||
| 192 | #define reg_pinmux_rw_gio_pa___pa21___lsb 21 | ||
| 193 | #define reg_pinmux_rw_gio_pa___pa21___width 1 | ||
| 194 | #define reg_pinmux_rw_gio_pa___pa21___bit 21 | ||
| 195 | #define reg_pinmux_rw_gio_pa___pa22___lsb 22 | ||
| 196 | #define reg_pinmux_rw_gio_pa___pa22___width 1 | ||
| 197 | #define reg_pinmux_rw_gio_pa___pa22___bit 22 | ||
| 198 | #define reg_pinmux_rw_gio_pa___pa23___lsb 23 | ||
| 199 | #define reg_pinmux_rw_gio_pa___pa23___width 1 | ||
| 200 | #define reg_pinmux_rw_gio_pa___pa23___bit 23 | ||
| 201 | #define reg_pinmux_rw_gio_pa___pa24___lsb 24 | ||
| 202 | #define reg_pinmux_rw_gio_pa___pa24___width 1 | ||
| 203 | #define reg_pinmux_rw_gio_pa___pa24___bit 24 | ||
| 204 | #define reg_pinmux_rw_gio_pa___pa25___lsb 25 | ||
| 205 | #define reg_pinmux_rw_gio_pa___pa25___width 1 | ||
| 206 | #define reg_pinmux_rw_gio_pa___pa25___bit 25 | ||
| 207 | #define reg_pinmux_rw_gio_pa___pa26___lsb 26 | ||
| 208 | #define reg_pinmux_rw_gio_pa___pa26___width 1 | ||
| 209 | #define reg_pinmux_rw_gio_pa___pa26___bit 26 | ||
| 210 | #define reg_pinmux_rw_gio_pa___pa27___lsb 27 | ||
| 211 | #define reg_pinmux_rw_gio_pa___pa27___width 1 | ||
| 212 | #define reg_pinmux_rw_gio_pa___pa27___bit 27 | ||
| 213 | #define reg_pinmux_rw_gio_pa___pa28___lsb 28 | ||
| 214 | #define reg_pinmux_rw_gio_pa___pa28___width 1 | ||
| 215 | #define reg_pinmux_rw_gio_pa___pa28___bit 28 | ||
| 216 | #define reg_pinmux_rw_gio_pa___pa29___lsb 29 | ||
| 217 | #define reg_pinmux_rw_gio_pa___pa29___width 1 | ||
| 218 | #define reg_pinmux_rw_gio_pa___pa29___bit 29 | ||
| 219 | #define reg_pinmux_rw_gio_pa___pa30___lsb 30 | ||
| 220 | #define reg_pinmux_rw_gio_pa___pa30___width 1 | ||
| 221 | #define reg_pinmux_rw_gio_pa___pa30___bit 30 | ||
| 222 | #define reg_pinmux_rw_gio_pa___pa31___lsb 31 | ||
| 223 | #define reg_pinmux_rw_gio_pa___pa31___width 1 | ||
| 224 | #define reg_pinmux_rw_gio_pa___pa31___bit 31 | ||
| 225 | #define reg_pinmux_rw_gio_pa_offset 4 | ||
| 226 | |||
| 227 | /* Register rw_gio_pb, scope pinmux, type rw */ | ||
| 228 | #define reg_pinmux_rw_gio_pb___pb0___lsb 0 | ||
| 229 | #define reg_pinmux_rw_gio_pb___pb0___width 1 | ||
| 230 | #define reg_pinmux_rw_gio_pb___pb0___bit 0 | ||
| 231 | #define reg_pinmux_rw_gio_pb___pb1___lsb 1 | ||
| 232 | #define reg_pinmux_rw_gio_pb___pb1___width 1 | ||
| 233 | #define reg_pinmux_rw_gio_pb___pb1___bit 1 | ||
| 234 | #define reg_pinmux_rw_gio_pb___pb2___lsb 2 | ||
| 235 | #define reg_pinmux_rw_gio_pb___pb2___width 1 | ||
| 236 | #define reg_pinmux_rw_gio_pb___pb2___bit 2 | ||
| 237 | #define reg_pinmux_rw_gio_pb___pb3___lsb 3 | ||
| 238 | #define reg_pinmux_rw_gio_pb___pb3___width 1 | ||
| 239 | #define reg_pinmux_rw_gio_pb___pb3___bit 3 | ||
| 240 | #define reg_pinmux_rw_gio_pb___pb4___lsb 4 | ||
| 241 | #define reg_pinmux_rw_gio_pb___pb4___width 1 | ||
| 242 | #define reg_pinmux_rw_gio_pb___pb4___bit 4 | ||
| 243 | #define reg_pinmux_rw_gio_pb___pb5___lsb 5 | ||
| 244 | #define reg_pinmux_rw_gio_pb___pb5___width 1 | ||
| 245 | #define reg_pinmux_rw_gio_pb___pb5___bit 5 | ||
| 246 | #define reg_pinmux_rw_gio_pb___pb6___lsb 6 | ||
| 247 | #define reg_pinmux_rw_gio_pb___pb6___width 1 | ||
| 248 | #define reg_pinmux_rw_gio_pb___pb6___bit 6 | ||
| 249 | #define reg_pinmux_rw_gio_pb___pb7___lsb 7 | ||
| 250 | #define reg_pinmux_rw_gio_pb___pb7___width 1 | ||
| 251 | #define reg_pinmux_rw_gio_pb___pb7___bit 7 | ||
| 252 | #define reg_pinmux_rw_gio_pb___pb8___lsb 8 | ||
| 253 | #define reg_pinmux_rw_gio_pb___pb8___width 1 | ||
| 254 | #define reg_pinmux_rw_gio_pb___pb8___bit 8 | ||
| 255 | #define reg_pinmux_rw_gio_pb___pb9___lsb 9 | ||
| 256 | #define reg_pinmux_rw_gio_pb___pb9___width 1 | ||
| 257 | #define reg_pinmux_rw_gio_pb___pb9___bit 9 | ||
| 258 | #define reg_pinmux_rw_gio_pb___pb10___lsb 10 | ||
| 259 | #define reg_pinmux_rw_gio_pb___pb10___width 1 | ||
| 260 | #define reg_pinmux_rw_gio_pb___pb10___bit 10 | ||
| 261 | #define reg_pinmux_rw_gio_pb___pb11___lsb 11 | ||
| 262 | #define reg_pinmux_rw_gio_pb___pb11___width 1 | ||
| 263 | #define reg_pinmux_rw_gio_pb___pb11___bit 11 | ||
| 264 | #define reg_pinmux_rw_gio_pb___pb12___lsb 12 | ||
| 265 | #define reg_pinmux_rw_gio_pb___pb12___width 1 | ||
| 266 | #define reg_pinmux_rw_gio_pb___pb12___bit 12 | ||
| 267 | #define reg_pinmux_rw_gio_pb___pb13___lsb 13 | ||
| 268 | #define reg_pinmux_rw_gio_pb___pb13___width 1 | ||
| 269 | #define reg_pinmux_rw_gio_pb___pb13___bit 13 | ||
| 270 | #define reg_pinmux_rw_gio_pb___pb14___lsb 14 | ||
| 271 | #define reg_pinmux_rw_gio_pb___pb14___width 1 | ||
| 272 | #define reg_pinmux_rw_gio_pb___pb14___bit 14 | ||
| 273 | #define reg_pinmux_rw_gio_pb___pb15___lsb 15 | ||
| 274 | #define reg_pinmux_rw_gio_pb___pb15___width 1 | ||
| 275 | #define reg_pinmux_rw_gio_pb___pb15___bit 15 | ||
| 276 | #define reg_pinmux_rw_gio_pb___pb16___lsb 16 | ||
| 277 | #define reg_pinmux_rw_gio_pb___pb16___width 1 | ||
| 278 | #define reg_pinmux_rw_gio_pb___pb16___bit 16 | ||
| 279 | #define reg_pinmux_rw_gio_pb___pb17___lsb 17 | ||
| 280 | #define reg_pinmux_rw_gio_pb___pb17___width 1 | ||
| 281 | #define reg_pinmux_rw_gio_pb___pb17___bit 17 | ||
| 282 | #define reg_pinmux_rw_gio_pb___pb18___lsb 18 | ||
| 283 | #define reg_pinmux_rw_gio_pb___pb18___width 1 | ||
| 284 | #define reg_pinmux_rw_gio_pb___pb18___bit 18 | ||
| 285 | #define reg_pinmux_rw_gio_pb___pb19___lsb 19 | ||
| 286 | #define reg_pinmux_rw_gio_pb___pb19___width 1 | ||
| 287 | #define reg_pinmux_rw_gio_pb___pb19___bit 19 | ||
| 288 | #define reg_pinmux_rw_gio_pb___pb20___lsb 20 | ||
| 289 | #define reg_pinmux_rw_gio_pb___pb20___width 1 | ||
| 290 | #define reg_pinmux_rw_gio_pb___pb20___bit 20 | ||
| 291 | #define reg_pinmux_rw_gio_pb___pb21___lsb 21 | ||
| 292 | #define reg_pinmux_rw_gio_pb___pb21___width 1 | ||
| 293 | #define reg_pinmux_rw_gio_pb___pb21___bit 21 | ||
| 294 | #define reg_pinmux_rw_gio_pb___pb22___lsb 22 | ||
| 295 | #define reg_pinmux_rw_gio_pb___pb22___width 1 | ||
| 296 | #define reg_pinmux_rw_gio_pb___pb22___bit 22 | ||
| 297 | #define reg_pinmux_rw_gio_pb___pb23___lsb 23 | ||
| 298 | #define reg_pinmux_rw_gio_pb___pb23___width 1 | ||
| 299 | #define reg_pinmux_rw_gio_pb___pb23___bit 23 | ||
| 300 | #define reg_pinmux_rw_gio_pb___pb24___lsb 24 | ||
| 301 | #define reg_pinmux_rw_gio_pb___pb24___width 1 | ||
| 302 | #define reg_pinmux_rw_gio_pb___pb24___bit 24 | ||
| 303 | #define reg_pinmux_rw_gio_pb___pb25___lsb 25 | ||
| 304 | #define reg_pinmux_rw_gio_pb___pb25___width 1 | ||
| 305 | #define reg_pinmux_rw_gio_pb___pb25___bit 25 | ||
| 306 | #define reg_pinmux_rw_gio_pb___pb26___lsb 26 | ||
| 307 | #define reg_pinmux_rw_gio_pb___pb26___width 1 | ||
| 308 | #define reg_pinmux_rw_gio_pb___pb26___bit 26 | ||
| 309 | #define reg_pinmux_rw_gio_pb___pb27___lsb 27 | ||
| 310 | #define reg_pinmux_rw_gio_pb___pb27___width 1 | ||
| 311 | #define reg_pinmux_rw_gio_pb___pb27___bit 27 | ||
| 312 | #define reg_pinmux_rw_gio_pb___pb28___lsb 28 | ||
| 313 | #define reg_pinmux_rw_gio_pb___pb28___width 1 | ||
| 314 | #define reg_pinmux_rw_gio_pb___pb28___bit 28 | ||
| 315 | #define reg_pinmux_rw_gio_pb___pb29___lsb 29 | ||
| 316 | #define reg_pinmux_rw_gio_pb___pb29___width 1 | ||
| 317 | #define reg_pinmux_rw_gio_pb___pb29___bit 29 | ||
| 318 | #define reg_pinmux_rw_gio_pb___pb30___lsb 30 | ||
| 319 | #define reg_pinmux_rw_gio_pb___pb30___width 1 | ||
| 320 | #define reg_pinmux_rw_gio_pb___pb30___bit 30 | ||
| 321 | #define reg_pinmux_rw_gio_pb___pb31___lsb 31 | ||
| 322 | #define reg_pinmux_rw_gio_pb___pb31___width 1 | ||
| 323 | #define reg_pinmux_rw_gio_pb___pb31___bit 31 | ||
| 324 | #define reg_pinmux_rw_gio_pb_offset 8 | ||
| 325 | |||
| 326 | /* Register rw_gio_pc, scope pinmux, type rw */ | ||
| 327 | #define reg_pinmux_rw_gio_pc___pc0___lsb 0 | ||
| 328 | #define reg_pinmux_rw_gio_pc___pc0___width 1 | ||
| 329 | #define reg_pinmux_rw_gio_pc___pc0___bit 0 | ||
| 330 | #define reg_pinmux_rw_gio_pc___pc1___lsb 1 | ||
| 331 | #define reg_pinmux_rw_gio_pc___pc1___width 1 | ||
| 332 | #define reg_pinmux_rw_gio_pc___pc1___bit 1 | ||
| 333 | #define reg_pinmux_rw_gio_pc___pc2___lsb 2 | ||
| 334 | #define reg_pinmux_rw_gio_pc___pc2___width 1 | ||
| 335 | #define reg_pinmux_rw_gio_pc___pc2___bit 2 | ||
| 336 | #define reg_pinmux_rw_gio_pc___pc3___lsb 3 | ||
| 337 | #define reg_pinmux_rw_gio_pc___pc3___width 1 | ||
| 338 | #define reg_pinmux_rw_gio_pc___pc3___bit 3 | ||
| 339 | #define reg_pinmux_rw_gio_pc___pc4___lsb 4 | ||
| 340 | #define reg_pinmux_rw_gio_pc___pc4___width 1 | ||
| 341 | #define reg_pinmux_rw_gio_pc___pc4___bit 4 | ||
| 342 | #define reg_pinmux_rw_gio_pc___pc5___lsb 5 | ||
| 343 | #define reg_pinmux_rw_gio_pc___pc5___width 1 | ||
| 344 | #define reg_pinmux_rw_gio_pc___pc5___bit 5 | ||
| 345 | #define reg_pinmux_rw_gio_pc___pc6___lsb 6 | ||
| 346 | #define reg_pinmux_rw_gio_pc___pc6___width 1 | ||
| 347 | #define reg_pinmux_rw_gio_pc___pc6___bit 6 | ||
| 348 | #define reg_pinmux_rw_gio_pc___pc7___lsb 7 | ||
| 349 | #define reg_pinmux_rw_gio_pc___pc7___width 1 | ||
| 350 | #define reg_pinmux_rw_gio_pc___pc7___bit 7 | ||
| 351 | #define reg_pinmux_rw_gio_pc___pc8___lsb 8 | ||
| 352 | #define reg_pinmux_rw_gio_pc___pc8___width 1 | ||
| 353 | #define reg_pinmux_rw_gio_pc___pc8___bit 8 | ||
| 354 | #define reg_pinmux_rw_gio_pc___pc9___lsb 9 | ||
| 355 | #define reg_pinmux_rw_gio_pc___pc9___width 1 | ||
| 356 | #define reg_pinmux_rw_gio_pc___pc9___bit 9 | ||
| 357 | #define reg_pinmux_rw_gio_pc___pc10___lsb 10 | ||
| 358 | #define reg_pinmux_rw_gio_pc___pc10___width 1 | ||
| 359 | #define reg_pinmux_rw_gio_pc___pc10___bit 10 | ||
| 360 | #define reg_pinmux_rw_gio_pc___pc11___lsb 11 | ||
| 361 | #define reg_pinmux_rw_gio_pc___pc11___width 1 | ||
| 362 | #define reg_pinmux_rw_gio_pc___pc11___bit 11 | ||
| 363 | #define reg_pinmux_rw_gio_pc___pc12___lsb 12 | ||
| 364 | #define reg_pinmux_rw_gio_pc___pc12___width 1 | ||
| 365 | #define reg_pinmux_rw_gio_pc___pc12___bit 12 | ||
| 366 | #define reg_pinmux_rw_gio_pc___pc13___lsb 13 | ||
| 367 | #define reg_pinmux_rw_gio_pc___pc13___width 1 | ||
| 368 | #define reg_pinmux_rw_gio_pc___pc13___bit 13 | ||
| 369 | #define reg_pinmux_rw_gio_pc___pc14___lsb 14 | ||
| 370 | #define reg_pinmux_rw_gio_pc___pc14___width 1 | ||
| 371 | #define reg_pinmux_rw_gio_pc___pc14___bit 14 | ||
| 372 | #define reg_pinmux_rw_gio_pc___pc15___lsb 15 | ||
| 373 | #define reg_pinmux_rw_gio_pc___pc15___width 1 | ||
| 374 | #define reg_pinmux_rw_gio_pc___pc15___bit 15 | ||
| 375 | #define reg_pinmux_rw_gio_pc_offset 12 | ||
| 376 | |||
| 377 | /* Register rw_iop_pa, scope pinmux, type rw */ | ||
| 378 | #define reg_pinmux_rw_iop_pa___pa0___lsb 0 | ||
| 379 | #define reg_pinmux_rw_iop_pa___pa0___width 1 | ||
| 380 | #define reg_pinmux_rw_iop_pa___pa0___bit 0 | ||
| 381 | #define reg_pinmux_rw_iop_pa___pa1___lsb 1 | ||
| 382 | #define reg_pinmux_rw_iop_pa___pa1___width 1 | ||
| 383 | #define reg_pinmux_rw_iop_pa___pa1___bit 1 | ||
| 384 | #define reg_pinmux_rw_iop_pa___pa2___lsb 2 | ||
| 385 | #define reg_pinmux_rw_iop_pa___pa2___width 1 | ||
| 386 | #define reg_pinmux_rw_iop_pa___pa2___bit 2 | ||
| 387 | #define reg_pinmux_rw_iop_pa___pa3___lsb 3 | ||
| 388 | #define reg_pinmux_rw_iop_pa___pa3___width 1 | ||
| 389 | #define reg_pinmux_rw_iop_pa___pa3___bit 3 | ||
| 390 | #define reg_pinmux_rw_iop_pa___pa4___lsb 4 | ||
| 391 | #define reg_pinmux_rw_iop_pa___pa4___width 1 | ||
| 392 | #define reg_pinmux_rw_iop_pa___pa4___bit 4 | ||
| 393 | #define reg_pinmux_rw_iop_pa___pa5___lsb 5 | ||
| 394 | #define reg_pinmux_rw_iop_pa___pa5___width 1 | ||
| 395 | #define reg_pinmux_rw_iop_pa___pa5___bit 5 | ||
| 396 | #define reg_pinmux_rw_iop_pa___pa6___lsb 6 | ||
| 397 | #define reg_pinmux_rw_iop_pa___pa6___width 1 | ||
| 398 | #define reg_pinmux_rw_iop_pa___pa6___bit 6 | ||
| 399 | #define reg_pinmux_rw_iop_pa___pa7___lsb 7 | ||
| 400 | #define reg_pinmux_rw_iop_pa___pa7___width 1 | ||
| 401 | #define reg_pinmux_rw_iop_pa___pa7___bit 7 | ||
| 402 | #define reg_pinmux_rw_iop_pa___pa8___lsb 8 | ||
| 403 | #define reg_pinmux_rw_iop_pa___pa8___width 1 | ||
| 404 | #define reg_pinmux_rw_iop_pa___pa8___bit 8 | ||
| 405 | #define reg_pinmux_rw_iop_pa___pa9___lsb 9 | ||
| 406 | #define reg_pinmux_rw_iop_pa___pa9___width 1 | ||
| 407 | #define reg_pinmux_rw_iop_pa___pa9___bit 9 | ||
| 408 | #define reg_pinmux_rw_iop_pa___pa10___lsb 10 | ||
| 409 | #define reg_pinmux_rw_iop_pa___pa10___width 1 | ||
| 410 | #define reg_pinmux_rw_iop_pa___pa10___bit 10 | ||
| 411 | #define reg_pinmux_rw_iop_pa___pa11___lsb 11 | ||
| 412 | #define reg_pinmux_rw_iop_pa___pa11___width 1 | ||
| 413 | #define reg_pinmux_rw_iop_pa___pa11___bit 11 | ||
| 414 | #define reg_pinmux_rw_iop_pa___pa12___lsb 12 | ||
| 415 | #define reg_pinmux_rw_iop_pa___pa12___width 1 | ||
| 416 | #define reg_pinmux_rw_iop_pa___pa12___bit 12 | ||
| 417 | #define reg_pinmux_rw_iop_pa___pa13___lsb 13 | ||
| 418 | #define reg_pinmux_rw_iop_pa___pa13___width 1 | ||
| 419 | #define reg_pinmux_rw_iop_pa___pa13___bit 13 | ||
| 420 | #define reg_pinmux_rw_iop_pa___pa14___lsb 14 | ||
| 421 | #define reg_pinmux_rw_iop_pa___pa14___width 1 | ||
| 422 | #define reg_pinmux_rw_iop_pa___pa14___bit 14 | ||
| 423 | #define reg_pinmux_rw_iop_pa___pa15___lsb 15 | ||
| 424 | #define reg_pinmux_rw_iop_pa___pa15___width 1 | ||
| 425 | #define reg_pinmux_rw_iop_pa___pa15___bit 15 | ||
| 426 | #define reg_pinmux_rw_iop_pa___pa16___lsb 16 | ||
| 427 | #define reg_pinmux_rw_iop_pa___pa16___width 1 | ||
| 428 | #define reg_pinmux_rw_iop_pa___pa16___bit 16 | ||
| 429 | #define reg_pinmux_rw_iop_pa___pa17___lsb 17 | ||
| 430 | #define reg_pinmux_rw_iop_pa___pa17___width 1 | ||
| 431 | #define reg_pinmux_rw_iop_pa___pa17___bit 17 | ||
| 432 | #define reg_pinmux_rw_iop_pa___pa18___lsb 18 | ||
| 433 | #define reg_pinmux_rw_iop_pa___pa18___width 1 | ||
| 434 | #define reg_pinmux_rw_iop_pa___pa18___bit 18 | ||
| 435 | #define reg_pinmux_rw_iop_pa___pa19___lsb 19 | ||
| 436 | #define reg_pinmux_rw_iop_pa___pa19___width 1 | ||
| 437 | #define reg_pinmux_rw_iop_pa___pa19___bit 19 | ||
| 438 | #define reg_pinmux_rw_iop_pa___pa20___lsb 20 | ||
| 439 | #define reg_pinmux_rw_iop_pa___pa20___width 1 | ||
| 440 | #define reg_pinmux_rw_iop_pa___pa20___bit 20 | ||
| 441 | #define reg_pinmux_rw_iop_pa___pa21___lsb 21 | ||
| 442 | #define reg_pinmux_rw_iop_pa___pa21___width 1 | ||
| 443 | #define reg_pinmux_rw_iop_pa___pa21___bit 21 | ||
| 444 | #define reg_pinmux_rw_iop_pa___pa22___lsb 22 | ||
| 445 | #define reg_pinmux_rw_iop_pa___pa22___width 1 | ||
| 446 | #define reg_pinmux_rw_iop_pa___pa22___bit 22 | ||
| 447 | #define reg_pinmux_rw_iop_pa___pa23___lsb 23 | ||
| 448 | #define reg_pinmux_rw_iop_pa___pa23___width 1 | ||
| 449 | #define reg_pinmux_rw_iop_pa___pa23___bit 23 | ||
| 450 | #define reg_pinmux_rw_iop_pa___pa24___lsb 24 | ||
| 451 | #define reg_pinmux_rw_iop_pa___pa24___width 1 | ||
| 452 | #define reg_pinmux_rw_iop_pa___pa24___bit 24 | ||
| 453 | #define reg_pinmux_rw_iop_pa___pa25___lsb 25 | ||
| 454 | #define reg_pinmux_rw_iop_pa___pa25___width 1 | ||
| 455 | #define reg_pinmux_rw_iop_pa___pa25___bit 25 | ||
| 456 | #define reg_pinmux_rw_iop_pa___pa26___lsb 26 | ||
| 457 | #define reg_pinmux_rw_iop_pa___pa26___width 1 | ||
| 458 | #define reg_pinmux_rw_iop_pa___pa26___bit 26 | ||
| 459 | #define reg_pinmux_rw_iop_pa___pa27___lsb 27 | ||
| 460 | #define reg_pinmux_rw_iop_pa___pa27___width 1 | ||
| 461 | #define reg_pinmux_rw_iop_pa___pa27___bit 27 | ||
| 462 | #define reg_pinmux_rw_iop_pa___pa28___lsb 28 | ||
| 463 | #define reg_pinmux_rw_iop_pa___pa28___width 1 | ||
| 464 | #define reg_pinmux_rw_iop_pa___pa28___bit 28 | ||
| 465 | #define reg_pinmux_rw_iop_pa___pa29___lsb 29 | ||
| 466 | #define reg_pinmux_rw_iop_pa___pa29___width 1 | ||
| 467 | #define reg_pinmux_rw_iop_pa___pa29___bit 29 | ||
| 468 | #define reg_pinmux_rw_iop_pa___pa30___lsb 30 | ||
| 469 | #define reg_pinmux_rw_iop_pa___pa30___width 1 | ||
| 470 | #define reg_pinmux_rw_iop_pa___pa30___bit 30 | ||
| 471 | #define reg_pinmux_rw_iop_pa___pa31___lsb 31 | ||
| 472 | #define reg_pinmux_rw_iop_pa___pa31___width 1 | ||
| 473 | #define reg_pinmux_rw_iop_pa___pa31___bit 31 | ||
| 474 | #define reg_pinmux_rw_iop_pa_offset 16 | ||
| 475 | |||
| 476 | /* Register rw_iop_pb, scope pinmux, type rw */ | ||
| 477 | #define reg_pinmux_rw_iop_pb___pb0___lsb 0 | ||
| 478 | #define reg_pinmux_rw_iop_pb___pb0___width 1 | ||
| 479 | #define reg_pinmux_rw_iop_pb___pb0___bit 0 | ||
| 480 | #define reg_pinmux_rw_iop_pb___pb1___lsb 1 | ||
| 481 | #define reg_pinmux_rw_iop_pb___pb1___width 1 | ||
| 482 | #define reg_pinmux_rw_iop_pb___pb1___bit 1 | ||
| 483 | #define reg_pinmux_rw_iop_pb___pb2___lsb 2 | ||
| 484 | #define reg_pinmux_rw_iop_pb___pb2___width 1 | ||
| 485 | #define reg_pinmux_rw_iop_pb___pb2___bit 2 | ||
| 486 | #define reg_pinmux_rw_iop_pb___pb3___lsb 3 | ||
| 487 | #define reg_pinmux_rw_iop_pb___pb3___width 1 | ||
| 488 | #define reg_pinmux_rw_iop_pb___pb3___bit 3 | ||
| 489 | #define reg_pinmux_rw_iop_pb___pb4___lsb 4 | ||
| 490 | #define reg_pinmux_rw_iop_pb___pb4___width 1 | ||
| 491 | #define reg_pinmux_rw_iop_pb___pb4___bit 4 | ||
| 492 | #define reg_pinmux_rw_iop_pb___pb5___lsb 5 | ||
| 493 | #define reg_pinmux_rw_iop_pb___pb5___width 1 | ||
| 494 | #define reg_pinmux_rw_iop_pb___pb5___bit 5 | ||
| 495 | #define reg_pinmux_rw_iop_pb___pb6___lsb 6 | ||
| 496 | #define reg_pinmux_rw_iop_pb___pb6___width 1 | ||
| 497 | #define reg_pinmux_rw_iop_pb___pb6___bit 6 | ||
| 498 | #define reg_pinmux_rw_iop_pb___pb7___lsb 7 | ||
| 499 | #define reg_pinmux_rw_iop_pb___pb7___width 1 | ||
| 500 | #define reg_pinmux_rw_iop_pb___pb7___bit 7 | ||
| 501 | #define reg_pinmux_rw_iop_pb_offset 20 | ||
| 502 | |||
| 503 | /* Register rw_iop_pio, scope pinmux, type rw */ | ||
| 504 | #define reg_pinmux_rw_iop_pio___d0___lsb 0 | ||
| 505 | #define reg_pinmux_rw_iop_pio___d0___width 1 | ||
| 506 | #define reg_pinmux_rw_iop_pio___d0___bit 0 | ||
| 507 | #define reg_pinmux_rw_iop_pio___d1___lsb 1 | ||
| 508 | #define reg_pinmux_rw_iop_pio___d1___width 1 | ||
| 509 | #define reg_pinmux_rw_iop_pio___d1___bit 1 | ||
| 510 | #define reg_pinmux_rw_iop_pio___d2___lsb 2 | ||
| 511 | #define reg_pinmux_rw_iop_pio___d2___width 1 | ||
| 512 | #define reg_pinmux_rw_iop_pio___d2___bit 2 | ||
| 513 | #define reg_pinmux_rw_iop_pio___d3___lsb 3 | ||
| 514 | #define reg_pinmux_rw_iop_pio___d3___width 1 | ||
| 515 | #define reg_pinmux_rw_iop_pio___d3___bit 3 | ||
| 516 | #define reg_pinmux_rw_iop_pio___d4___lsb 4 | ||
| 517 | #define reg_pinmux_rw_iop_pio___d4___width 1 | ||
| 518 | #define reg_pinmux_rw_iop_pio___d4___bit 4 | ||
| 519 | #define reg_pinmux_rw_iop_pio___d5___lsb 5 | ||
| 520 | #define reg_pinmux_rw_iop_pio___d5___width 1 | ||
| 521 | #define reg_pinmux_rw_iop_pio___d5___bit 5 | ||
| 522 | #define reg_pinmux_rw_iop_pio___d6___lsb 6 | ||
| 523 | #define reg_pinmux_rw_iop_pio___d6___width 1 | ||
| 524 | #define reg_pinmux_rw_iop_pio___d6___bit 6 | ||
| 525 | #define reg_pinmux_rw_iop_pio___d7___lsb 7 | ||
| 526 | #define reg_pinmux_rw_iop_pio___d7___width 1 | ||
| 527 | #define reg_pinmux_rw_iop_pio___d7___bit 7 | ||
| 528 | #define reg_pinmux_rw_iop_pio___rd_n___lsb 8 | ||
| 529 | #define reg_pinmux_rw_iop_pio___rd_n___width 1 | ||
| 530 | #define reg_pinmux_rw_iop_pio___rd_n___bit 8 | ||
| 531 | #define reg_pinmux_rw_iop_pio___wr_n___lsb 9 | ||
| 532 | #define reg_pinmux_rw_iop_pio___wr_n___width 1 | ||
| 533 | #define reg_pinmux_rw_iop_pio___wr_n___bit 9 | ||
| 534 | #define reg_pinmux_rw_iop_pio___a0___lsb 10 | ||
| 535 | #define reg_pinmux_rw_iop_pio___a0___width 1 | ||
| 536 | #define reg_pinmux_rw_iop_pio___a0___bit 10 | ||
| 537 | #define reg_pinmux_rw_iop_pio___a1___lsb 11 | ||
| 538 | #define reg_pinmux_rw_iop_pio___a1___width 1 | ||
| 539 | #define reg_pinmux_rw_iop_pio___a1___bit 11 | ||
| 540 | #define reg_pinmux_rw_iop_pio___ce0_n___lsb 12 | ||
| 541 | #define reg_pinmux_rw_iop_pio___ce0_n___width 1 | ||
| 542 | #define reg_pinmux_rw_iop_pio___ce0_n___bit 12 | ||
| 543 | #define reg_pinmux_rw_iop_pio___ce1_n___lsb 13 | ||
| 544 | #define reg_pinmux_rw_iop_pio___ce1_n___width 1 | ||
| 545 | #define reg_pinmux_rw_iop_pio___ce1_n___bit 13 | ||
| 546 | #define reg_pinmux_rw_iop_pio___ce2_n___lsb 14 | ||
| 547 | #define reg_pinmux_rw_iop_pio___ce2_n___width 1 | ||
| 548 | #define reg_pinmux_rw_iop_pio___ce2_n___bit 14 | ||
| 549 | #define reg_pinmux_rw_iop_pio___rdy___lsb 15 | ||
| 550 | #define reg_pinmux_rw_iop_pio___rdy___width 1 | ||
| 551 | #define reg_pinmux_rw_iop_pio___rdy___bit 15 | ||
| 552 | #define reg_pinmux_rw_iop_pio_offset 24 | ||
| 553 | |||
| 554 | /* Register rw_iop_usb, scope pinmux, type rw */ | ||
| 555 | #define reg_pinmux_rw_iop_usb___usb0___lsb 0 | ||
| 556 | #define reg_pinmux_rw_iop_usb___usb0___width 1 | ||
| 557 | #define reg_pinmux_rw_iop_usb___usb0___bit 0 | ||
| 558 | #define reg_pinmux_rw_iop_usb_offset 28 | ||
| 559 | |||
| 560 | |||
| 561 | /* Constants */ | ||
| 562 | #define regk_pinmux_no 0x00000000 | ||
| 563 | #define regk_pinmux_rw_gio_pa_default 0x00000000 | ||
| 564 | #define regk_pinmux_rw_gio_pb_default 0x00000000 | ||
| 565 | #define regk_pinmux_rw_gio_pc_default 0x00000000 | ||
| 566 | #define regk_pinmux_rw_hwprot_default 0x00000000 | ||
| 567 | #define regk_pinmux_rw_iop_pa_default 0x00000000 | ||
| 568 | #define regk_pinmux_rw_iop_pb_default 0x00000000 | ||
| 569 | #define regk_pinmux_rw_iop_pio_default 0x00000000 | ||
| 570 | #define regk_pinmux_rw_iop_usb_default 0x00000001 | ||
| 571 | #define regk_pinmux_yes 0x00000001 | ||
| 572 | #endif /* __pinmux_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h deleted file mode 100644 index 3907ef4921c8..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h +++ /dev/null | |||
| @@ -1,337 +0,0 @@ | |||
| 1 | #ifndef __pio_defs_asm_h | ||
| 2 | #define __pio_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: pio.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_data, scope pio, type rw */ | ||
| 54 | #define reg_pio_rw_data_offset 64 | ||
| 55 | |||
| 56 | /* Register rw_io_access0, scope pio, type rw */ | ||
| 57 | #define reg_pio_rw_io_access0___data___lsb 0 | ||
| 58 | #define reg_pio_rw_io_access0___data___width 8 | ||
| 59 | #define reg_pio_rw_io_access0_offset 0 | ||
| 60 | |||
| 61 | /* Register rw_io_access1, scope pio, type rw */ | ||
| 62 | #define reg_pio_rw_io_access1___data___lsb 0 | ||
| 63 | #define reg_pio_rw_io_access1___data___width 8 | ||
| 64 | #define reg_pio_rw_io_access1_offset 4 | ||
| 65 | |||
| 66 | /* Register rw_io_access2, scope pio, type rw */ | ||
| 67 | #define reg_pio_rw_io_access2___data___lsb 0 | ||
| 68 | #define reg_pio_rw_io_access2___data___width 8 | ||
| 69 | #define reg_pio_rw_io_access2_offset 8 | ||
| 70 | |||
| 71 | /* Register rw_io_access3, scope pio, type rw */ | ||
| 72 | #define reg_pio_rw_io_access3___data___lsb 0 | ||
| 73 | #define reg_pio_rw_io_access3___data___width 8 | ||
| 74 | #define reg_pio_rw_io_access3_offset 12 | ||
| 75 | |||
| 76 | /* Register rw_io_access4, scope pio, type rw */ | ||
| 77 | #define reg_pio_rw_io_access4___data___lsb 0 | ||
| 78 | #define reg_pio_rw_io_access4___data___width 8 | ||
| 79 | #define reg_pio_rw_io_access4_offset 16 | ||
| 80 | |||
| 81 | /* Register rw_io_access5, scope pio, type rw */ | ||
| 82 | #define reg_pio_rw_io_access5___data___lsb 0 | ||
| 83 | #define reg_pio_rw_io_access5___data___width 8 | ||
| 84 | #define reg_pio_rw_io_access5_offset 20 | ||
| 85 | |||
| 86 | /* Register rw_io_access6, scope pio, type rw */ | ||
| 87 | #define reg_pio_rw_io_access6___data___lsb 0 | ||
| 88 | #define reg_pio_rw_io_access6___data___width 8 | ||
| 89 | #define reg_pio_rw_io_access6_offset 24 | ||
| 90 | |||
| 91 | /* Register rw_io_access7, scope pio, type rw */ | ||
| 92 | #define reg_pio_rw_io_access7___data___lsb 0 | ||
| 93 | #define reg_pio_rw_io_access7___data___width 8 | ||
| 94 | #define reg_pio_rw_io_access7_offset 28 | ||
| 95 | |||
| 96 | /* Register rw_io_access8, scope pio, type rw */ | ||
| 97 | #define reg_pio_rw_io_access8___data___lsb 0 | ||
| 98 | #define reg_pio_rw_io_access8___data___width 8 | ||
| 99 | #define reg_pio_rw_io_access8_offset 32 | ||
| 100 | |||
| 101 | /* Register rw_io_access9, scope pio, type rw */ | ||
| 102 | #define reg_pio_rw_io_access9___data___lsb 0 | ||
| 103 | #define reg_pio_rw_io_access9___data___width 8 | ||
| 104 | #define reg_pio_rw_io_access9_offset 36 | ||
| 105 | |||
| 106 | /* Register rw_io_access10, scope pio, type rw */ | ||
| 107 | #define reg_pio_rw_io_access10___data___lsb 0 | ||
| 108 | #define reg_pio_rw_io_access10___data___width 8 | ||
| 109 | #define reg_pio_rw_io_access10_offset 40 | ||
| 110 | |||
| 111 | /* Register rw_io_access11, scope pio, type rw */ | ||
| 112 | #define reg_pio_rw_io_access11___data___lsb 0 | ||
| 113 | #define reg_pio_rw_io_access11___data___width 8 | ||
| 114 | #define reg_pio_rw_io_access11_offset 44 | ||
| 115 | |||
| 116 | /* Register rw_io_access12, scope pio, type rw */ | ||
| 117 | #define reg_pio_rw_io_access12___data___lsb 0 | ||
| 118 | #define reg_pio_rw_io_access12___data___width 8 | ||
| 119 | #define reg_pio_rw_io_access12_offset 48 | ||
| 120 | |||
| 121 | /* Register rw_io_access13, scope pio, type rw */ | ||
| 122 | #define reg_pio_rw_io_access13___data___lsb 0 | ||
| 123 | #define reg_pio_rw_io_access13___data___width 8 | ||
| 124 | #define reg_pio_rw_io_access13_offset 52 | ||
| 125 | |||
| 126 | /* Register rw_io_access14, scope pio, type rw */ | ||
| 127 | #define reg_pio_rw_io_access14___data___lsb 0 | ||
| 128 | #define reg_pio_rw_io_access14___data___width 8 | ||
| 129 | #define reg_pio_rw_io_access14_offset 56 | ||
| 130 | |||
| 131 | /* Register rw_io_access15, scope pio, type rw */ | ||
| 132 | #define reg_pio_rw_io_access15___data___lsb 0 | ||
| 133 | #define reg_pio_rw_io_access15___data___width 8 | ||
| 134 | #define reg_pio_rw_io_access15_offset 60 | ||
| 135 | |||
| 136 | /* Register rw_ce0_cfg, scope pio, type rw */ | ||
| 137 | #define reg_pio_rw_ce0_cfg___lw___lsb 0 | ||
| 138 | #define reg_pio_rw_ce0_cfg___lw___width 6 | ||
| 139 | #define reg_pio_rw_ce0_cfg___ew___lsb 6 | ||
| 140 | #define reg_pio_rw_ce0_cfg___ew___width 3 | ||
| 141 | #define reg_pio_rw_ce0_cfg___zw___lsb 9 | ||
| 142 | #define reg_pio_rw_ce0_cfg___zw___width 3 | ||
| 143 | #define reg_pio_rw_ce0_cfg___aw___lsb 12 | ||
| 144 | #define reg_pio_rw_ce0_cfg___aw___width 2 | ||
| 145 | #define reg_pio_rw_ce0_cfg___mode___lsb 14 | ||
| 146 | #define reg_pio_rw_ce0_cfg___mode___width 2 | ||
| 147 | #define reg_pio_rw_ce0_cfg_offset 68 | ||
| 148 | |||
| 149 | /* Register rw_ce1_cfg, scope pio, type rw */ | ||
| 150 | #define reg_pio_rw_ce1_cfg___lw___lsb 0 | ||
| 151 | #define reg_pio_rw_ce1_cfg___lw___width 6 | ||
| 152 | #define reg_pio_rw_ce1_cfg___ew___lsb 6 | ||
| 153 | #define reg_pio_rw_ce1_cfg___ew___width 3 | ||
| 154 | #define reg_pio_rw_ce1_cfg___zw___lsb 9 | ||
| 155 | #define reg_pio_rw_ce1_cfg___zw___width 3 | ||
| 156 | #define reg_pio_rw_ce1_cfg___aw___lsb 12 | ||
| 157 | #define reg_pio_rw_ce1_cfg___aw___width 2 | ||
| 158 | #define reg_pio_rw_ce1_cfg___mode___lsb 14 | ||
| 159 | #define reg_pio_rw_ce1_cfg___mode___width 2 | ||
| 160 | #define reg_pio_rw_ce1_cfg_offset 72 | ||
| 161 | |||
| 162 | /* Register rw_ce2_cfg, scope pio, type rw */ | ||
| 163 | #define reg_pio_rw_ce2_cfg___lw___lsb 0 | ||
| 164 | #define reg_pio_rw_ce2_cfg___lw___width 6 | ||
| 165 | #define reg_pio_rw_ce2_cfg___ew___lsb 6 | ||
| 166 | #define reg_pio_rw_ce2_cfg___ew___width 3 | ||
| 167 | #define reg_pio_rw_ce2_cfg___zw___lsb 9 | ||
| 168 | #define reg_pio_rw_ce2_cfg___zw___width 3 | ||
| 169 | #define reg_pio_rw_ce2_cfg___aw___lsb 12 | ||
| 170 | #define reg_pio_rw_ce2_cfg___aw___width 2 | ||
| 171 | #define reg_pio_rw_ce2_cfg___mode___lsb 14 | ||
| 172 | #define reg_pio_rw_ce2_cfg___mode___width 2 | ||
| 173 | #define reg_pio_rw_ce2_cfg_offset 76 | ||
| 174 | |||
| 175 | /* Register rw_dout, scope pio, type rw */ | ||
| 176 | #define reg_pio_rw_dout___data___lsb 0 | ||
| 177 | #define reg_pio_rw_dout___data___width 8 | ||
| 178 | #define reg_pio_rw_dout___rd_n___lsb 8 | ||
| 179 | #define reg_pio_rw_dout___rd_n___width 1 | ||
| 180 | #define reg_pio_rw_dout___rd_n___bit 8 | ||
| 181 | #define reg_pio_rw_dout___wr_n___lsb 9 | ||
| 182 | #define reg_pio_rw_dout___wr_n___width 1 | ||
| 183 | #define reg_pio_rw_dout___wr_n___bit 9 | ||
| 184 | #define reg_pio_rw_dout___a0___lsb 10 | ||
| 185 | #define reg_pio_rw_dout___a0___width 1 | ||
| 186 | #define reg_pio_rw_dout___a0___bit 10 | ||
| 187 | #define reg_pio_rw_dout___a1___lsb 11 | ||
| 188 | #define reg_pio_rw_dout___a1___width 1 | ||
| 189 | #define reg_pio_rw_dout___a1___bit 11 | ||
| 190 | #define reg_pio_rw_dout___ce0_n___lsb 12 | ||
| 191 | #define reg_pio_rw_dout___ce0_n___width 1 | ||
| 192 | #define reg_pio_rw_dout___ce0_n___bit 12 | ||
| 193 | #define reg_pio_rw_dout___ce1_n___lsb 13 | ||
| 194 | #define reg_pio_rw_dout___ce1_n___width 1 | ||
| 195 | #define reg_pio_rw_dout___ce1_n___bit 13 | ||
| 196 | #define reg_pio_rw_dout___ce2_n___lsb 14 | ||
| 197 | #define reg_pio_rw_dout___ce2_n___width 1 | ||
| 198 | #define reg_pio_rw_dout___ce2_n___bit 14 | ||
| 199 | #define reg_pio_rw_dout___rdy___lsb 15 | ||
| 200 | #define reg_pio_rw_dout___rdy___width 1 | ||
| 201 | #define reg_pio_rw_dout___rdy___bit 15 | ||
| 202 | #define reg_pio_rw_dout_offset 80 | ||
| 203 | |||
| 204 | /* Register rw_oe, scope pio, type rw */ | ||
| 205 | #define reg_pio_rw_oe___data___lsb 0 | ||
| 206 | #define reg_pio_rw_oe___data___width 8 | ||
| 207 | #define reg_pio_rw_oe___rd_n___lsb 8 | ||
| 208 | #define reg_pio_rw_oe___rd_n___width 1 | ||
| 209 | #define reg_pio_rw_oe___rd_n___bit 8 | ||
| 210 | #define reg_pio_rw_oe___wr_n___lsb 9 | ||
| 211 | #define reg_pio_rw_oe___wr_n___width 1 | ||
| 212 | #define reg_pio_rw_oe___wr_n___bit 9 | ||
| 213 | #define reg_pio_rw_oe___a0___lsb 10 | ||
| 214 | #define reg_pio_rw_oe___a0___width 1 | ||
| 215 | #define reg_pio_rw_oe___a0___bit 10 | ||
| 216 | #define reg_pio_rw_oe___a1___lsb 11 | ||
| 217 | #define reg_pio_rw_oe___a1___width 1 | ||
| 218 | #define reg_pio_rw_oe___a1___bit 11 | ||
| 219 | #define reg_pio_rw_oe___ce0_n___lsb 12 | ||
| 220 | #define reg_pio_rw_oe___ce0_n___width 1 | ||
| 221 | #define reg_pio_rw_oe___ce0_n___bit 12 | ||
| 222 | #define reg_pio_rw_oe___ce1_n___lsb 13 | ||
| 223 | #define reg_pio_rw_oe___ce1_n___width 1 | ||
| 224 | #define reg_pio_rw_oe___ce1_n___bit 13 | ||
| 225 | #define reg_pio_rw_oe___ce2_n___lsb 14 | ||
| 226 | #define reg_pio_rw_oe___ce2_n___width 1 | ||
| 227 | #define reg_pio_rw_oe___ce2_n___bit 14 | ||
| 228 | #define reg_pio_rw_oe___rdy___lsb 15 | ||
| 229 | #define reg_pio_rw_oe___rdy___width 1 | ||
| 230 | #define reg_pio_rw_oe___rdy___bit 15 | ||
| 231 | #define reg_pio_rw_oe_offset 84 | ||
| 232 | |||
| 233 | /* Register rw_man_ctrl, scope pio, type rw */ | ||
| 234 | #define reg_pio_rw_man_ctrl___data___lsb 0 | ||
| 235 | #define reg_pio_rw_man_ctrl___data___width 8 | ||
| 236 | #define reg_pio_rw_man_ctrl___rd_n___lsb 8 | ||
| 237 | #define reg_pio_rw_man_ctrl___rd_n___width 1 | ||
| 238 | #define reg_pio_rw_man_ctrl___rd_n___bit 8 | ||
| 239 | #define reg_pio_rw_man_ctrl___wr_n___lsb 9 | ||
| 240 | #define reg_pio_rw_man_ctrl___wr_n___width 1 | ||
| 241 | #define reg_pio_rw_man_ctrl___wr_n___bit 9 | ||
| 242 | #define reg_pio_rw_man_ctrl___a0___lsb 10 | ||
| 243 | #define reg_pio_rw_man_ctrl___a0___width 1 | ||
| 244 | #define reg_pio_rw_man_ctrl___a0___bit 10 | ||
| 245 | #define reg_pio_rw_man_ctrl___a1___lsb 11 | ||
| 246 | #define reg_pio_rw_man_ctrl___a1___width 1 | ||
| 247 | #define reg_pio_rw_man_ctrl___a1___bit 11 | ||
| 248 | #define reg_pio_rw_man_ctrl___ce0_n___lsb 12 | ||
| 249 | #define reg_pio_rw_man_ctrl___ce0_n___width 1 | ||
| 250 | #define reg_pio_rw_man_ctrl___ce0_n___bit 12 | ||
| 251 | #define reg_pio_rw_man_ctrl___ce1_n___lsb 13 | ||
| 252 | #define reg_pio_rw_man_ctrl___ce1_n___width 1 | ||
| 253 | #define reg_pio_rw_man_ctrl___ce1_n___bit 13 | ||
| 254 | #define reg_pio_rw_man_ctrl___ce2_n___lsb 14 | ||
| 255 | #define reg_pio_rw_man_ctrl___ce2_n___width 1 | ||
| 256 | #define reg_pio_rw_man_ctrl___ce2_n___bit 14 | ||
| 257 | #define reg_pio_rw_man_ctrl___rdy___lsb 15 | ||
| 258 | #define reg_pio_rw_man_ctrl___rdy___width 1 | ||
| 259 | #define reg_pio_rw_man_ctrl___rdy___bit 15 | ||
| 260 | #define reg_pio_rw_man_ctrl_offset 88 | ||
| 261 | |||
| 262 | /* Register r_din, scope pio, type r */ | ||
| 263 | #define reg_pio_r_din___data___lsb 0 | ||
| 264 | #define reg_pio_r_din___data___width 8 | ||
| 265 | #define reg_pio_r_din___rd_n___lsb 8 | ||
| 266 | #define reg_pio_r_din___rd_n___width 1 | ||
| 267 | #define reg_pio_r_din___rd_n___bit 8 | ||
| 268 | #define reg_pio_r_din___wr_n___lsb 9 | ||
| 269 | #define reg_pio_r_din___wr_n___width 1 | ||
| 270 | #define reg_pio_r_din___wr_n___bit 9 | ||
| 271 | #define reg_pio_r_din___a0___lsb 10 | ||
| 272 | #define reg_pio_r_din___a0___width 1 | ||
| 273 | #define reg_pio_r_din___a0___bit 10 | ||
| 274 | #define reg_pio_r_din___a1___lsb 11 | ||
| 275 | #define reg_pio_r_din___a1___width 1 | ||
| 276 | #define reg_pio_r_din___a1___bit 11 | ||
| 277 | #define reg_pio_r_din___ce0_n___lsb 12 | ||
| 278 | #define reg_pio_r_din___ce0_n___width 1 | ||
| 279 | #define reg_pio_r_din___ce0_n___bit 12 | ||
| 280 | #define reg_pio_r_din___ce1_n___lsb 13 | ||
| 281 | #define reg_pio_r_din___ce1_n___width 1 | ||
| 282 | #define reg_pio_r_din___ce1_n___bit 13 | ||
| 283 | #define reg_pio_r_din___ce2_n___lsb 14 | ||
| 284 | #define reg_pio_r_din___ce2_n___width 1 | ||
| 285 | #define reg_pio_r_din___ce2_n___bit 14 | ||
| 286 | #define reg_pio_r_din___rdy___lsb 15 | ||
| 287 | #define reg_pio_r_din___rdy___width 1 | ||
| 288 | #define reg_pio_r_din___rdy___bit 15 | ||
| 289 | #define reg_pio_r_din_offset 92 | ||
| 290 | |||
| 291 | /* Register r_stat, scope pio, type r */ | ||
| 292 | #define reg_pio_r_stat___busy___lsb 0 | ||
| 293 | #define reg_pio_r_stat___busy___width 1 | ||
| 294 | #define reg_pio_r_stat___busy___bit 0 | ||
| 295 | #define reg_pio_r_stat_offset 96 | ||
| 296 | |||
| 297 | /* Register rw_intr_mask, scope pio, type rw */ | ||
| 298 | #define reg_pio_rw_intr_mask___rdy___lsb 0 | ||
| 299 | #define reg_pio_rw_intr_mask___rdy___width 1 | ||
| 300 | #define reg_pio_rw_intr_mask___rdy___bit 0 | ||
| 301 | #define reg_pio_rw_intr_mask_offset 100 | ||
| 302 | |||
| 303 | /* Register rw_ack_intr, scope pio, type rw */ | ||
| 304 | #define reg_pio_rw_ack_intr___rdy___lsb 0 | ||
| 305 | #define reg_pio_rw_ack_intr___rdy___width 1 | ||
| 306 | #define reg_pio_rw_ack_intr___rdy___bit 0 | ||
| 307 | #define reg_pio_rw_ack_intr_offset 104 | ||
| 308 | |||
| 309 | /* Register r_intr, scope pio, type r */ | ||
| 310 | #define reg_pio_r_intr___rdy___lsb 0 | ||
| 311 | #define reg_pio_r_intr___rdy___width 1 | ||
| 312 | #define reg_pio_r_intr___rdy___bit 0 | ||
| 313 | #define reg_pio_r_intr_offset 108 | ||
| 314 | |||
| 315 | /* Register r_masked_intr, scope pio, type r */ | ||
| 316 | #define reg_pio_r_masked_intr___rdy___lsb 0 | ||
| 317 | #define reg_pio_r_masked_intr___rdy___width 1 | ||
| 318 | #define reg_pio_r_masked_intr___rdy___bit 0 | ||
| 319 | #define reg_pio_r_masked_intr_offset 112 | ||
| 320 | |||
| 321 | |||
| 322 | /* Constants */ | ||
| 323 | #define regk_pio_a2 0x00000003 | ||
| 324 | #define regk_pio_no 0x00000000 | ||
| 325 | #define regk_pio_normal 0x00000000 | ||
| 326 | #define regk_pio_rd 0x00000001 | ||
| 327 | #define regk_pio_rw_ce0_cfg_default 0x00000000 | ||
| 328 | #define regk_pio_rw_ce1_cfg_default 0x00000000 | ||
| 329 | #define regk_pio_rw_ce2_cfg_default 0x00000000 | ||
| 330 | #define regk_pio_rw_intr_mask_default 0x00000000 | ||
| 331 | #define regk_pio_rw_man_ctrl_default 0x00000000 | ||
| 332 | #define regk_pio_rw_oe_default 0x00000000 | ||
| 333 | #define regk_pio_wr 0x00000002 | ||
| 334 | #define regk_pio_wr_ce2 0x00000003 | ||
| 335 | #define regk_pio_yes 0x00000001 | ||
| 336 | #define regk_pio_yes_all 0x000000ff | ||
| 337 | #endif /* __pio_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 89439e9610e2..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h +++ /dev/null | |||
| @@ -1,99 +0,0 @@ | |||
| 1 | #ifndef __reg_map_asm_h | ||
| 2 | #define __reg_map_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: reg.rmap | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | #define regi_ccd 0xb0000000 | ||
| 14 | #define regi_ccd_top 0xb0000000 | ||
| 15 | #define regi_ccd_dp 0xb0000400 | ||
| 16 | #define regi_ccd_stat 0xb0000800 | ||
| 17 | #define regi_ccd_tg 0xb0001000 | ||
| 18 | #define regi_cfg 0xb0002000 | ||
| 19 | #define regi_clkgen 0xb0004000 | ||
| 20 | #define regi_ddr2_ctrl 0xb0006000 | ||
| 21 | #define regi_dma0 0xb0008000 | ||
| 22 | #define regi_dma1 0xb000a000 | ||
| 23 | #define regi_dma11 0xb000c000 | ||
| 24 | #define regi_dma2 0xb000e000 | ||
| 25 | #define regi_dma3 0xb0010000 | ||
| 26 | #define regi_dma4 0xb0012000 | ||
| 27 | #define regi_dma5 0xb0014000 | ||
| 28 | #define regi_dma6 0xb0016000 | ||
| 29 | #define regi_dma7 0xb0018000 | ||
| 30 | #define regi_dma9 0xb001a000 | ||
| 31 | #define regi_eth 0xb001c000 | ||
| 32 | #define regi_gio 0xb0020000 | ||
| 33 | #define regi_h264 0xb0022000 | ||
| 34 | #define regi_hist 0xb0026000 | ||
| 35 | #define regi_iop 0xb0028000 | ||
| 36 | #define regi_iop_version 0xb0028000 | ||
| 37 | #define regi_iop_fifo_in_extra 0xb0028040 | ||
| 38 | #define regi_iop_fifo_out_extra 0xb0028080 | ||
| 39 | #define regi_iop_trigger_grp0 0xb00280c0 | ||
| 40 | #define regi_iop_trigger_grp1 0xb0028100 | ||
| 41 | #define regi_iop_trigger_grp2 0xb0028140 | ||
| 42 | #define regi_iop_trigger_grp3 0xb0028180 | ||
| 43 | #define regi_iop_trigger_grp4 0xb00281c0 | ||
| 44 | #define regi_iop_trigger_grp5 0xb0028200 | ||
| 45 | #define regi_iop_trigger_grp6 0xb0028240 | ||
| 46 | #define regi_iop_trigger_grp7 0xb0028280 | ||
| 47 | #define regi_iop_crc_par 0xb0028300 | ||
| 48 | #define regi_iop_dmc_in 0xb0028380 | ||
| 49 | #define regi_iop_dmc_out 0xb0028400 | ||
| 50 | #define regi_iop_fifo_in 0xb0028480 | ||
| 51 | #define regi_iop_fifo_out 0xb0028500 | ||
| 52 | #define regi_iop_scrc_in 0xb0028580 | ||
| 53 | #define regi_iop_scrc_out 0xb0028600 | ||
| 54 | #define regi_iop_timer_grp0 0xb0028680 | ||
| 55 | #define regi_iop_timer_grp1 0xb0028700 | ||
| 56 | #define regi_iop_sap_in 0xb0028800 | ||
| 57 | #define regi_iop_sap_out 0xb0028900 | ||
| 58 | #define regi_iop_spu 0xb0028a00 | ||
| 59 | #define regi_iop_sw_cfg 0xb0028b00 | ||
| 60 | #define regi_iop_sw_cpu 0xb0028c00 | ||
| 61 | #define regi_iop_sw_mpu 0xb0028d00 | ||
| 62 | #define regi_iop_sw_spu 0xb0028e00 | ||
| 63 | #define regi_iop_mpu 0xb0029000 | ||
| 64 | #define regi_irq 0xb002a000 | ||
| 65 | #define regi_jpeg 0xb002c000 | ||
| 66 | #define regi_l2cache 0xb0030000 | ||
| 67 | #define regi_marb_bar 0xb0032000 | ||
| 68 | #define regi_marb_bar_bp0 0xb0032140 | ||
| 69 | #define regi_marb_bar_bp1 0xb0032180 | ||
| 70 | #define regi_marb_bar_bp2 0xb00321c0 | ||
| 71 | #define regi_marb_bar_bp3 0xb0032200 | ||
| 72 | #define regi_marb_foo 0xb0034000 | ||
| 73 | #define regi_marb_foo_bp0 0xb0034280 | ||
| 74 | #define regi_marb_foo_bp1 0xb00342c0 | ||
| 75 | #define regi_marb_foo_bp2 0xb0034300 | ||
| 76 | #define regi_marb_foo_bp3 0xb0034340 | ||
| 77 | #define regi_pinmux 0xb0038000 | ||
| 78 | #define regi_pio 0xb0036000 | ||
| 79 | #define regi_sclr 0xb003a000 | ||
| 80 | #define regi_sclr_fifo 0xb003c000 | ||
| 81 | #define regi_ser0 0xb003e000 | ||
| 82 | #define regi_ser1 0xb0040000 | ||
| 83 | #define regi_ser2 0xb0042000 | ||
| 84 | #define regi_ser3 0xb0044000 | ||
| 85 | #define regi_ser4 0xb0046000 | ||
| 86 | #define regi_sser 0xb0048000 | ||
| 87 | #define regi_strcop 0xb004a000 | ||
| 88 | #define regi_strdma0 0xb004e000 | ||
| 89 | #define regi_strdma1 0xb0050000 | ||
| 90 | #define regi_strdma2 0xb0052000 | ||
| 91 | #define regi_strdma3 0xb0054000 | ||
| 92 | #define regi_strdma5 0xb0056000 | ||
| 93 | #define regi_strmux 0xb004c000 | ||
| 94 | #define regi_timer0 0xb0058000 | ||
| 95 | #define regi_timer1 0xb005a000 | ||
| 96 | #define regi_trace 0xb005c000 | ||
| 97 | #define regi_vin 0xb005e000 | ||
| 98 | #define regi_vout 0xb0060000 | ||
| 99 | #endif /* __reg_map_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index b129e826fc34..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h +++ /dev/null | |||
| @@ -1,228 +0,0 @@ | |||
| 1 | #ifndef __timer_defs_asm_h | ||
| 2 | #define __timer_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: timer.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_tmr0_div, scope timer, type rw */ | ||
| 54 | #define reg_timer_rw_tmr0_div_offset 0 | ||
| 55 | |||
| 56 | /* Register r_tmr0_data, scope timer, type r */ | ||
| 57 | #define reg_timer_r_tmr0_data_offset 4 | ||
| 58 | |||
| 59 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | ||
| 60 | #define reg_timer_rw_tmr0_ctrl___op___lsb 0 | ||
| 61 | #define reg_timer_rw_tmr0_ctrl___op___width 2 | ||
| 62 | #define reg_timer_rw_tmr0_ctrl___freq___lsb 2 | ||
| 63 | #define reg_timer_rw_tmr0_ctrl___freq___width 3 | ||
| 64 | #define reg_timer_rw_tmr0_ctrl_offset 8 | ||
| 65 | |||
| 66 | /* Register rw_tmr1_div, scope timer, type rw */ | ||
| 67 | #define reg_timer_rw_tmr1_div_offset 16 | ||
| 68 | |||
| 69 | /* Register r_tmr1_data, scope timer, type r */ | ||
| 70 | #define reg_timer_r_tmr1_data_offset 20 | ||
| 71 | |||
| 72 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | ||
| 73 | #define reg_timer_rw_tmr1_ctrl___op___lsb 0 | ||
| 74 | #define reg_timer_rw_tmr1_ctrl___op___width 2 | ||
| 75 | #define reg_timer_rw_tmr1_ctrl___freq___lsb 2 | ||
| 76 | #define reg_timer_rw_tmr1_ctrl___freq___width 3 | ||
| 77 | #define reg_timer_rw_tmr1_ctrl_offset 24 | ||
| 78 | |||
| 79 | /* Register rs_cnt_data, scope timer, type rs */ | ||
| 80 | #define reg_timer_rs_cnt_data___tmr___lsb 0 | ||
| 81 | #define reg_timer_rs_cnt_data___tmr___width 24 | ||
| 82 | #define reg_timer_rs_cnt_data___cnt___lsb 24 | ||
| 83 | #define reg_timer_rs_cnt_data___cnt___width 8 | ||
| 84 | #define reg_timer_rs_cnt_data_offset 32 | ||
| 85 | |||
| 86 | /* Register r_cnt_data, scope timer, type r */ | ||
| 87 | #define reg_timer_r_cnt_data___tmr___lsb 0 | ||
| 88 | #define reg_timer_r_cnt_data___tmr___width 24 | ||
| 89 | #define reg_timer_r_cnt_data___cnt___lsb 24 | ||
| 90 | #define reg_timer_r_cnt_data___cnt___width 8 | ||
| 91 | #define reg_timer_r_cnt_data_offset 36 | ||
| 92 | |||
| 93 | /* Register rw_cnt_cfg, scope timer, type rw */ | ||
| 94 | #define reg_timer_rw_cnt_cfg___clk___lsb 0 | ||
| 95 | #define reg_timer_rw_cnt_cfg___clk___width 2 | ||
| 96 | #define reg_timer_rw_cnt_cfg_offset 40 | ||
| 97 | |||
| 98 | /* Register rw_trig, scope timer, type rw */ | ||
| 99 | #define reg_timer_rw_trig_offset 48 | ||
| 100 | |||
| 101 | /* Register rw_trig_cfg, scope timer, type rw */ | ||
| 102 | #define reg_timer_rw_trig_cfg___tmr___lsb 0 | ||
| 103 | #define reg_timer_rw_trig_cfg___tmr___width 2 | ||
| 104 | #define reg_timer_rw_trig_cfg_offset 52 | ||
| 105 | |||
| 106 | /* Register r_time, scope timer, type r */ | ||
| 107 | #define reg_timer_r_time_offset 56 | ||
| 108 | |||
| 109 | /* Register rw_out, scope timer, type rw */ | ||
| 110 | #define reg_timer_rw_out___tmr___lsb 0 | ||
| 111 | #define reg_timer_rw_out___tmr___width 2 | ||
| 112 | #define reg_timer_rw_out_offset 60 | ||
| 113 | |||
| 114 | /* Register rw_wd_ctrl, scope timer, type rw */ | ||
| 115 | #define reg_timer_rw_wd_ctrl___cnt___lsb 0 | ||
| 116 | #define reg_timer_rw_wd_ctrl___cnt___width 8 | ||
| 117 | #define reg_timer_rw_wd_ctrl___cmd___lsb 8 | ||
| 118 | #define reg_timer_rw_wd_ctrl___cmd___width 1 | ||
| 119 | #define reg_timer_rw_wd_ctrl___cmd___bit 8 | ||
| 120 | #define reg_timer_rw_wd_ctrl___key___lsb 9 | ||
| 121 | #define reg_timer_rw_wd_ctrl___key___width 7 | ||
| 122 | #define reg_timer_rw_wd_ctrl_offset 64 | ||
| 123 | |||
| 124 | /* Register r_wd_stat, scope timer, type r */ | ||
| 125 | #define reg_timer_r_wd_stat___cnt___lsb 0 | ||
| 126 | #define reg_timer_r_wd_stat___cnt___width 8 | ||
| 127 | #define reg_timer_r_wd_stat___cmd___lsb 8 | ||
| 128 | #define reg_timer_r_wd_stat___cmd___width 1 | ||
| 129 | #define reg_timer_r_wd_stat___cmd___bit 8 | ||
| 130 | #define reg_timer_r_wd_stat_offset 68 | ||
| 131 | |||
| 132 | /* Register rw_intr_mask, scope timer, type rw */ | ||
| 133 | #define reg_timer_rw_intr_mask___tmr0___lsb 0 | ||
| 134 | #define reg_timer_rw_intr_mask___tmr0___width 1 | ||
| 135 | #define reg_timer_rw_intr_mask___tmr0___bit 0 | ||
| 136 | #define reg_timer_rw_intr_mask___tmr1___lsb 1 | ||
| 137 | #define reg_timer_rw_intr_mask___tmr1___width 1 | ||
| 138 | #define reg_timer_rw_intr_mask___tmr1___bit 1 | ||
| 139 | #define reg_timer_rw_intr_mask___cnt___lsb 2 | ||
| 140 | #define reg_timer_rw_intr_mask___cnt___width 1 | ||
| 141 | #define reg_timer_rw_intr_mask___cnt___bit 2 | ||
| 142 | #define reg_timer_rw_intr_mask___trig___lsb 3 | ||
| 143 | #define reg_timer_rw_intr_mask___trig___width 1 | ||
| 144 | #define reg_timer_rw_intr_mask___trig___bit 3 | ||
| 145 | #define reg_timer_rw_intr_mask_offset 72 | ||
| 146 | |||
| 147 | /* Register rw_ack_intr, scope timer, type rw */ | ||
| 148 | #define reg_timer_rw_ack_intr___tmr0___lsb 0 | ||
| 149 | #define reg_timer_rw_ack_intr___tmr0___width 1 | ||
| 150 | #define reg_timer_rw_ack_intr___tmr0___bit 0 | ||
| 151 | #define reg_timer_rw_ack_intr___tmr1___lsb 1 | ||
| 152 | #define reg_timer_rw_ack_intr___tmr1___width 1 | ||
| 153 | #define reg_timer_rw_ack_intr___tmr1___bit 1 | ||
| 154 | #define reg_timer_rw_ack_intr___cnt___lsb 2 | ||
| 155 | #define reg_timer_rw_ack_intr___cnt___width 1 | ||
| 156 | #define reg_timer_rw_ack_intr___cnt___bit 2 | ||
| 157 | #define reg_timer_rw_ack_intr___trig___lsb 3 | ||
| 158 | #define reg_timer_rw_ack_intr___trig___width 1 | ||
| 159 | #define reg_timer_rw_ack_intr___trig___bit 3 | ||
| 160 | #define reg_timer_rw_ack_intr_offset 76 | ||
| 161 | |||
| 162 | /* Register r_intr, scope timer, type r */ | ||
| 163 | #define reg_timer_r_intr___tmr0___lsb 0 | ||
| 164 | #define reg_timer_r_intr___tmr0___width 1 | ||
| 165 | #define reg_timer_r_intr___tmr0___bit 0 | ||
| 166 | #define reg_timer_r_intr___tmr1___lsb 1 | ||
| 167 | #define reg_timer_r_intr___tmr1___width 1 | ||
| 168 | #define reg_timer_r_intr___tmr1___bit 1 | ||
| 169 | #define reg_timer_r_intr___cnt___lsb 2 | ||
| 170 | #define reg_timer_r_intr___cnt___width 1 | ||
| 171 | #define reg_timer_r_intr___cnt___bit 2 | ||
| 172 | #define reg_timer_r_intr___trig___lsb 3 | ||
| 173 | #define reg_timer_r_intr___trig___width 1 | ||
| 174 | #define reg_timer_r_intr___trig___bit 3 | ||
| 175 | #define reg_timer_r_intr_offset 80 | ||
| 176 | |||
| 177 | /* Register r_masked_intr, scope timer, type r */ | ||
| 178 | #define reg_timer_r_masked_intr___tmr0___lsb 0 | ||
| 179 | #define reg_timer_r_masked_intr___tmr0___width 1 | ||
| 180 | #define reg_timer_r_masked_intr___tmr0___bit 0 | ||
| 181 | #define reg_timer_r_masked_intr___tmr1___lsb 1 | ||
| 182 | #define reg_timer_r_masked_intr___tmr1___width 1 | ||
| 183 | #define reg_timer_r_masked_intr___tmr1___bit 1 | ||
| 184 | #define reg_timer_r_masked_intr___cnt___lsb 2 | ||
| 185 | #define reg_timer_r_masked_intr___cnt___width 1 | ||
| 186 | #define reg_timer_r_masked_intr___cnt___bit 2 | ||
| 187 | #define reg_timer_r_masked_intr___trig___lsb 3 | ||
| 188 | #define reg_timer_r_masked_intr___trig___width 1 | ||
| 189 | #define reg_timer_r_masked_intr___trig___bit 3 | ||
| 190 | #define reg_timer_r_masked_intr_offset 84 | ||
| 191 | |||
| 192 | /* Register rw_test, scope timer, type rw */ | ||
| 193 | #define reg_timer_rw_test___dis___lsb 0 | ||
| 194 | #define reg_timer_rw_test___dis___width 1 | ||
| 195 | #define reg_timer_rw_test___dis___bit 0 | ||
| 196 | #define reg_timer_rw_test___en___lsb 1 | ||
| 197 | #define reg_timer_rw_test___en___width 1 | ||
| 198 | #define reg_timer_rw_test___en___bit 1 | ||
| 199 | #define reg_timer_rw_test_offset 88 | ||
| 200 | |||
| 201 | |||
| 202 | /* Constants */ | ||
| 203 | #define regk_timer_ext 0x00000001 | ||
| 204 | #define regk_timer_f100 0x00000007 | ||
| 205 | #define regk_timer_f29_493 0x00000004 | ||
| 206 | #define regk_timer_f32 0x00000005 | ||
| 207 | #define regk_timer_f32_768 0x00000006 | ||
| 208 | #define regk_timer_f90 0x00000003 | ||
| 209 | #define regk_timer_hold 0x00000001 | ||
| 210 | #define regk_timer_ld 0x00000000 | ||
| 211 | #define regk_timer_no 0x00000000 | ||
| 212 | #define regk_timer_off 0x00000000 | ||
| 213 | #define regk_timer_run 0x00000002 | ||
| 214 | #define regk_timer_rw_cnt_cfg_default 0x00000000 | ||
| 215 | #define regk_timer_rw_intr_mask_default 0x00000000 | ||
| 216 | #define regk_timer_rw_out_default 0x00000000 | ||
| 217 | #define regk_timer_rw_test_default 0x00000000 | ||
| 218 | #define regk_timer_rw_tmr0_ctrl_default 0x00000000 | ||
| 219 | #define regk_timer_rw_tmr1_ctrl_default 0x00000000 | ||
| 220 | #define regk_timer_rw_trig_cfg_default 0x00000000 | ||
| 221 | #define regk_timer_start 0x00000001 | ||
| 222 | #define regk_timer_stop 0x00000000 | ||
| 223 | #define regk_timer_time 0x00000001 | ||
| 224 | #define regk_timer_tmr0 0x00000002 | ||
| 225 | #define regk_timer_tmr1 0x00000003 | ||
| 226 | #define regk_timer_vclk 0x00000002 | ||
| 227 | #define regk_timer_yes 0x00000001 | ||
| 228 | #endif /* __timer_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h deleted file mode 100644 index c1e9ba93b3a3..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h +++ /dev/null | |||
| @@ -1,159 +0,0 @@ | |||
| 1 | #ifndef __clkgen_defs_h | ||
| 2 | #define __clkgen_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: clkgen.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope clkgen */ | ||
| 83 | |||
| 84 | /* Register r_bootsel, scope clkgen, type r */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int boot_mode : 5; | ||
| 87 | unsigned int intern_main_clk : 1; | ||
| 88 | unsigned int extern_usb2_clk : 1; | ||
| 89 | unsigned int dummy1 : 25; | ||
| 90 | } reg_clkgen_r_bootsel; | ||
| 91 | #define REG_RD_ADDR_clkgen_r_bootsel 0 | ||
| 92 | |||
| 93 | /* Register rw_clk_ctrl, scope clkgen, type rw */ | ||
| 94 | typedef struct { | ||
| 95 | unsigned int pll : 1; | ||
| 96 | unsigned int cpu : 1; | ||
| 97 | unsigned int iop_usb : 1; | ||
| 98 | unsigned int vin : 1; | ||
| 99 | unsigned int sclr : 1; | ||
| 100 | unsigned int h264 : 1; | ||
| 101 | unsigned int ddr2 : 1; | ||
| 102 | unsigned int vout_hist : 1; | ||
| 103 | unsigned int eth : 1; | ||
| 104 | unsigned int ccd_tg_200 : 1; | ||
| 105 | unsigned int dma0_1_eth : 1; | ||
| 106 | unsigned int ccd_tg_100 : 1; | ||
| 107 | unsigned int jpeg : 1; | ||
| 108 | unsigned int sser_ser_dma6_7 : 1; | ||
| 109 | unsigned int strdma0_2_video : 1; | ||
| 110 | unsigned int dma2_3_strcop : 1; | ||
| 111 | unsigned int dma4_5_iop : 1; | ||
| 112 | unsigned int dma9_11 : 1; | ||
| 113 | unsigned int memarb_bar_ddr : 1; | ||
| 114 | unsigned int sclr_h264 : 1; | ||
| 115 | unsigned int dummy1 : 12; | ||
| 116 | } reg_clkgen_rw_clk_ctrl; | ||
| 117 | #define REG_RD_ADDR_clkgen_rw_clk_ctrl 4 | ||
| 118 | #define REG_WR_ADDR_clkgen_rw_clk_ctrl 4 | ||
| 119 | |||
| 120 | |||
| 121 | /* Constants */ | ||
| 122 | enum { | ||
| 123 | regk_clkgen_eth1000_rx = 0x0000000c, | ||
| 124 | regk_clkgen_eth1000_tx = 0x0000000e, | ||
| 125 | regk_clkgen_eth100_rx = 0x0000001d, | ||
| 126 | regk_clkgen_eth100_rx_half = 0x0000001c, | ||
| 127 | regk_clkgen_eth100_tx = 0x0000001f, | ||
| 128 | regk_clkgen_eth100_tx_half = 0x0000001e, | ||
| 129 | regk_clkgen_nand_3_2 = 0x00000000, | ||
| 130 | regk_clkgen_nand_3_2_0x30 = 0x00000002, | ||
| 131 | regk_clkgen_nand_3_2_0x30_pll = 0x00000012, | ||
| 132 | regk_clkgen_nand_3_2_pll = 0x00000010, | ||
| 133 | regk_clkgen_nand_3_3 = 0x00000001, | ||
| 134 | regk_clkgen_nand_3_3_0x30 = 0x00000003, | ||
| 135 | regk_clkgen_nand_3_3_0x30_pll = 0x00000013, | ||
| 136 | regk_clkgen_nand_3_3_pll = 0x00000011, | ||
| 137 | regk_clkgen_nand_4_2 = 0x00000004, | ||
| 138 | regk_clkgen_nand_4_2_0x30 = 0x00000006, | ||
| 139 | regk_clkgen_nand_4_2_0x30_pll = 0x00000016, | ||
| 140 | regk_clkgen_nand_4_2_pll = 0x00000014, | ||
| 141 | regk_clkgen_nand_4_3 = 0x00000005, | ||
| 142 | regk_clkgen_nand_4_3_0x30 = 0x00000007, | ||
| 143 | regk_clkgen_nand_4_3_0x30_pll = 0x00000017, | ||
| 144 | regk_clkgen_nand_4_3_pll = 0x00000015, | ||
| 145 | regk_clkgen_nand_5_2 = 0x00000008, | ||
| 146 | regk_clkgen_nand_5_2_0x30 = 0x0000000a, | ||
| 147 | regk_clkgen_nand_5_2_0x30_pll = 0x0000001a, | ||
| 148 | regk_clkgen_nand_5_2_pll = 0x00000018, | ||
| 149 | regk_clkgen_nand_5_3 = 0x00000009, | ||
| 150 | regk_clkgen_nand_5_3_0x30 = 0x0000000b, | ||
| 151 | regk_clkgen_nand_5_3_0x30_pll = 0x0000001b, | ||
| 152 | regk_clkgen_nand_5_3_pll = 0x00000019, | ||
| 153 | regk_clkgen_no = 0x00000000, | ||
| 154 | regk_clkgen_rw_clk_ctrl_default = 0x00000002, | ||
| 155 | regk_clkgen_ser = 0x0000000d, | ||
| 156 | regk_clkgen_ser_pll = 0x0000000f, | ||
| 157 | regk_clkgen_yes = 0x00000001 | ||
| 158 | }; | ||
| 159 | #endif /* __clkgen_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h deleted file mode 100644 index 0f30e8bf946d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h +++ /dev/null | |||
| @@ -1,281 +0,0 @@ | |||
| 1 | #ifndef __ddr2_defs_h | ||
| 2 | #define __ddr2_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ddr2.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope ddr2 */ | ||
| 83 | |||
| 84 | /* Register rw_cfg, scope ddr2, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int col_width : 4; | ||
| 87 | unsigned int nr_banks : 1; | ||
| 88 | unsigned int bw : 1; | ||
| 89 | unsigned int nr_ref : 4; | ||
| 90 | unsigned int ref_interval : 11; | ||
| 91 | unsigned int odt_ctrl : 2; | ||
| 92 | unsigned int odt_mem : 1; | ||
| 93 | unsigned int imp_strength : 1; | ||
| 94 | unsigned int auto_imp_cal : 1; | ||
| 95 | unsigned int imp_cal_override : 1; | ||
| 96 | unsigned int dll_override : 1; | ||
| 97 | unsigned int dummy1 : 4; | ||
| 98 | } reg_ddr2_rw_cfg; | ||
| 99 | #define REG_RD_ADDR_ddr2_rw_cfg 0 | ||
| 100 | #define REG_WR_ADDR_ddr2_rw_cfg 0 | ||
| 101 | |||
| 102 | /* Register rw_timing, scope ddr2, type rw */ | ||
| 103 | typedef struct { | ||
| 104 | unsigned int wr : 3; | ||
| 105 | unsigned int rcd : 3; | ||
| 106 | unsigned int rp : 3; | ||
| 107 | unsigned int ras : 4; | ||
| 108 | unsigned int rfc : 7; | ||
| 109 | unsigned int rc : 5; | ||
| 110 | unsigned int rtp : 2; | ||
| 111 | unsigned int rtw : 3; | ||
| 112 | unsigned int wtr : 2; | ||
| 113 | } reg_ddr2_rw_timing; | ||
| 114 | #define REG_RD_ADDR_ddr2_rw_timing 4 | ||
| 115 | #define REG_WR_ADDR_ddr2_rw_timing 4 | ||
| 116 | |||
| 117 | /* Register rw_latency, scope ddr2, type rw */ | ||
| 118 | typedef struct { | ||
| 119 | unsigned int cas : 3; | ||
| 120 | unsigned int additive : 3; | ||
| 121 | unsigned int dummy1 : 26; | ||
| 122 | } reg_ddr2_rw_latency; | ||
| 123 | #define REG_RD_ADDR_ddr2_rw_latency 8 | ||
| 124 | #define REG_WR_ADDR_ddr2_rw_latency 8 | ||
| 125 | |||
| 126 | /* Register rw_phy_cfg, scope ddr2, type rw */ | ||
| 127 | typedef struct { | ||
| 128 | unsigned int en : 1; | ||
| 129 | unsigned int dummy1 : 31; | ||
| 130 | } reg_ddr2_rw_phy_cfg; | ||
| 131 | #define REG_RD_ADDR_ddr2_rw_phy_cfg 12 | ||
| 132 | #define REG_WR_ADDR_ddr2_rw_phy_cfg 12 | ||
| 133 | |||
| 134 | /* Register rw_phy_ctrl, scope ddr2, type rw */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int rst : 1; | ||
| 137 | unsigned int cal_rst : 1; | ||
| 138 | unsigned int cal_start : 1; | ||
| 139 | unsigned int dummy1 : 29; | ||
| 140 | } reg_ddr2_rw_phy_ctrl; | ||
| 141 | #define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 | ||
| 142 | #define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 | ||
| 143 | |||
| 144 | /* Register rw_ctrl, scope ddr2, type rw */ | ||
| 145 | typedef struct { | ||
| 146 | unsigned int mrs_data : 16; | ||
| 147 | unsigned int cmd : 8; | ||
| 148 | unsigned int dummy1 : 8; | ||
| 149 | } reg_ddr2_rw_ctrl; | ||
| 150 | #define REG_RD_ADDR_ddr2_rw_ctrl 20 | ||
| 151 | #define REG_WR_ADDR_ddr2_rw_ctrl 20 | ||
| 152 | |||
| 153 | /* Register rw_pwr_down, scope ddr2, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int self_ref : 2; | ||
| 156 | unsigned int phy_en : 1; | ||
| 157 | unsigned int dummy1 : 29; | ||
| 158 | } reg_ddr2_rw_pwr_down; | ||
| 159 | #define REG_RD_ADDR_ddr2_rw_pwr_down 24 | ||
| 160 | #define REG_WR_ADDR_ddr2_rw_pwr_down 24 | ||
| 161 | |||
| 162 | /* Register r_stat, scope ddr2, type r */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int dll_lock : 1; | ||
| 165 | unsigned int dll_delay_code : 7; | ||
| 166 | unsigned int imp_cal_done : 1; | ||
| 167 | unsigned int imp_cal_fault : 1; | ||
| 168 | unsigned int cal_imp_pu : 4; | ||
| 169 | unsigned int cal_imp_pd : 4; | ||
| 170 | unsigned int dummy1 : 14; | ||
| 171 | } reg_ddr2_r_stat; | ||
| 172 | #define REG_RD_ADDR_ddr2_r_stat 28 | ||
| 173 | |||
| 174 | /* Register rw_imp_ctrl, scope ddr2, type rw */ | ||
| 175 | typedef struct { | ||
| 176 | unsigned int imp_pu : 4; | ||
| 177 | unsigned int imp_pd : 4; | ||
| 178 | unsigned int dummy1 : 24; | ||
| 179 | } reg_ddr2_rw_imp_ctrl; | ||
| 180 | #define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 | ||
| 181 | #define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 | ||
| 182 | |||
| 183 | #define STRIDE_ddr2_rw_dll_ctrl 4 | ||
| 184 | /* Register rw_dll_ctrl, scope ddr2, type rw */ | ||
| 185 | typedef struct { | ||
| 186 | unsigned int mode : 1; | ||
| 187 | unsigned int clk_delay : 7; | ||
| 188 | unsigned int dummy1 : 24; | ||
| 189 | } reg_ddr2_rw_dll_ctrl; | ||
| 190 | #define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 | ||
| 191 | #define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 | ||
| 192 | |||
| 193 | #define STRIDE_ddr2_rw_dqs_dll_ctrl 4 | ||
| 194 | /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ | ||
| 195 | typedef struct { | ||
| 196 | unsigned int dqs90_delay : 7; | ||
| 197 | unsigned int dqs180_delay : 7; | ||
| 198 | unsigned int dqs270_delay : 7; | ||
| 199 | unsigned int dqs360_delay : 7; | ||
| 200 | unsigned int dummy1 : 4; | ||
| 201 | } reg_ddr2_rw_dqs_dll_ctrl; | ||
| 202 | #define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 | ||
| 203 | #define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 | ||
| 204 | |||
| 205 | |||
| 206 | /* Constants */ | ||
| 207 | enum { | ||
| 208 | regk_ddr2_al0 = 0x00000000, | ||
| 209 | regk_ddr2_al1 = 0x00000008, | ||
| 210 | regk_ddr2_al2 = 0x00000010, | ||
| 211 | regk_ddr2_al3 = 0x00000018, | ||
| 212 | regk_ddr2_al4 = 0x00000020, | ||
| 213 | regk_ddr2_auto = 0x00000003, | ||
| 214 | regk_ddr2_bank4 = 0x00000000, | ||
| 215 | regk_ddr2_bank8 = 0x00000001, | ||
| 216 | regk_ddr2_bl4 = 0x00000002, | ||
| 217 | regk_ddr2_bl8 = 0x00000003, | ||
| 218 | regk_ddr2_bt_il = 0x00000008, | ||
| 219 | regk_ddr2_bt_seq = 0x00000000, | ||
| 220 | regk_ddr2_bw16 = 0x00000001, | ||
| 221 | regk_ddr2_bw32 = 0x00000000, | ||
| 222 | regk_ddr2_cas2 = 0x00000020, | ||
| 223 | regk_ddr2_cas3 = 0x00000030, | ||
| 224 | regk_ddr2_cas4 = 0x00000040, | ||
| 225 | regk_ddr2_cas5 = 0x00000050, | ||
| 226 | regk_ddr2_deselect = 0x000000c0, | ||
| 227 | regk_ddr2_dic_weak = 0x00000002, | ||
| 228 | regk_ddr2_direct = 0x00000001, | ||
| 229 | regk_ddr2_dis = 0x00000000, | ||
| 230 | regk_ddr2_dll_dis = 0x00000001, | ||
| 231 | regk_ddr2_dll_en = 0x00000000, | ||
| 232 | regk_ddr2_dll_rst = 0x00000100, | ||
| 233 | regk_ddr2_emrs = 0x00000081, | ||
| 234 | regk_ddr2_emrs2 = 0x00000082, | ||
| 235 | regk_ddr2_emrs3 = 0x00000083, | ||
| 236 | regk_ddr2_full = 0x00000001, | ||
| 237 | regk_ddr2_hi_ref_rate = 0x00000080, | ||
| 238 | regk_ddr2_mrs = 0x00000080, | ||
| 239 | regk_ddr2_no = 0x00000000, | ||
| 240 | regk_ddr2_nop = 0x000000b8, | ||
| 241 | regk_ddr2_ocd_adj = 0x00000200, | ||
| 242 | regk_ddr2_ocd_default = 0x00000380, | ||
| 243 | regk_ddr2_ocd_drive0 = 0x00000100, | ||
| 244 | regk_ddr2_ocd_drive1 = 0x00000080, | ||
| 245 | regk_ddr2_ocd_exit = 0x00000000, | ||
| 246 | regk_ddr2_odt_dis = 0x00000000, | ||
| 247 | regk_ddr2_offs = 0x00000000, | ||
| 248 | regk_ddr2_pre = 0x00000090, | ||
| 249 | regk_ddr2_pre_all = 0x00000400, | ||
| 250 | regk_ddr2_pwr_down_fast = 0x00000000, | ||
| 251 | regk_ddr2_pwr_down_slow = 0x00001000, | ||
| 252 | regk_ddr2_ref = 0x00000088, | ||
| 253 | regk_ddr2_rtt150 = 0x00000040, | ||
| 254 | regk_ddr2_rtt50 = 0x00000044, | ||
| 255 | regk_ddr2_rtt75 = 0x00000004, | ||
| 256 | regk_ddr2_rw_cfg_default = 0x00186000, | ||
| 257 | regk_ddr2_rw_dll_ctrl_default = 0x00000000, | ||
| 258 | regk_ddr2_rw_dll_ctrl_size = 0x00000004, | ||
| 259 | regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, | ||
| 260 | regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, | ||
| 261 | regk_ddr2_rw_latency_default = 0x00000000, | ||
| 262 | regk_ddr2_rw_phy_cfg_default = 0x00000000, | ||
| 263 | regk_ddr2_rw_pwr_down_default = 0x00000000, | ||
| 264 | regk_ddr2_rw_timing_default = 0x00000000, | ||
| 265 | regk_ddr2_s1Gb = 0x0000001a, | ||
| 266 | regk_ddr2_s256Mb = 0x0000000f, | ||
| 267 | regk_ddr2_s2Gb = 0x00000027, | ||
| 268 | regk_ddr2_s4Gb = 0x00000042, | ||
| 269 | regk_ddr2_s512Mb = 0x00000015, | ||
| 270 | regk_ddr2_temp0_85 = 0x00000618, | ||
| 271 | regk_ddr2_temp85_95 = 0x0000030c, | ||
| 272 | regk_ddr2_term150 = 0x00000002, | ||
| 273 | regk_ddr2_term50 = 0x00000003, | ||
| 274 | regk_ddr2_term75 = 0x00000001, | ||
| 275 | regk_ddr2_test = 0x00000080, | ||
| 276 | regk_ddr2_weak = 0x00000000, | ||
| 277 | regk_ddr2_wr2 = 0x00000200, | ||
| 278 | regk_ddr2_wr3 = 0x00000400, | ||
| 279 | regk_ddr2_yes = 0x00000001 | ||
| 280 | }; | ||
| 281 | #endif /* __ddr2_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h deleted file mode 100644 index 5d88e0db23ae..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h +++ /dev/null | |||
| @@ -1,837 +0,0 @@ | |||
| 1 | #ifndef __gio_defs_h | ||
| 2 | #define __gio_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: gio.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope gio */ | ||
| 83 | |||
| 84 | /* Register r_pa_din, scope gio, type r */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int data : 32; | ||
| 87 | } reg_gio_r_pa_din; | ||
| 88 | #define REG_RD_ADDR_gio_r_pa_din 0 | ||
| 89 | |||
| 90 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 91 | typedef struct { | ||
| 92 | unsigned int data : 32; | ||
| 93 | } reg_gio_rw_pa_dout; | ||
| 94 | #define REG_RD_ADDR_gio_rw_pa_dout 4 | ||
| 95 | #define REG_WR_ADDR_gio_rw_pa_dout 4 | ||
| 96 | |||
| 97 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int oe : 32; | ||
| 100 | } reg_gio_rw_pa_oe; | ||
| 101 | #define REG_RD_ADDR_gio_rw_pa_oe 8 | ||
| 102 | #define REG_WR_ADDR_gio_rw_pa_oe 8 | ||
| 103 | |||
| 104 | /* Register rw_pa_byte0_dout, scope gio, type rw */ | ||
| 105 | typedef struct { | ||
| 106 | unsigned int data : 8; | ||
| 107 | unsigned int dummy1 : 24; | ||
| 108 | } reg_gio_rw_pa_byte0_dout; | ||
| 109 | #define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 | ||
| 110 | #define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 | ||
| 111 | |||
| 112 | /* Register rw_pa_byte0_oe, scope gio, type rw */ | ||
| 113 | typedef struct { | ||
| 114 | unsigned int oe : 8; | ||
| 115 | unsigned int dummy1 : 24; | ||
| 116 | } reg_gio_rw_pa_byte0_oe; | ||
| 117 | #define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 | ||
| 118 | #define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 | ||
| 119 | |||
| 120 | /* Register rw_pa_byte1_dout, scope gio, type rw */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int data : 8; | ||
| 123 | unsigned int dummy1 : 24; | ||
| 124 | } reg_gio_rw_pa_byte1_dout; | ||
| 125 | #define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 | ||
| 126 | #define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 | ||
| 127 | |||
| 128 | /* Register rw_pa_byte1_oe, scope gio, type rw */ | ||
| 129 | typedef struct { | ||
| 130 | unsigned int oe : 8; | ||
| 131 | unsigned int dummy1 : 24; | ||
| 132 | } reg_gio_rw_pa_byte1_oe; | ||
| 133 | #define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 | ||
| 134 | #define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 | ||
| 135 | |||
| 136 | /* Register rw_pa_byte2_dout, scope gio, type rw */ | ||
| 137 | typedef struct { | ||
| 138 | unsigned int data : 8; | ||
| 139 | unsigned int dummy1 : 24; | ||
| 140 | } reg_gio_rw_pa_byte2_dout; | ||
| 141 | #define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 | ||
| 142 | #define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 | ||
| 143 | |||
| 144 | /* Register rw_pa_byte2_oe, scope gio, type rw */ | ||
| 145 | typedef struct { | ||
| 146 | unsigned int oe : 8; | ||
| 147 | unsigned int dummy1 : 24; | ||
| 148 | } reg_gio_rw_pa_byte2_oe; | ||
| 149 | #define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 | ||
| 150 | #define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 | ||
| 151 | |||
| 152 | /* Register rw_pa_byte3_dout, scope gio, type rw */ | ||
| 153 | typedef struct { | ||
| 154 | unsigned int data : 8; | ||
| 155 | unsigned int dummy1 : 24; | ||
| 156 | } reg_gio_rw_pa_byte3_dout; | ||
| 157 | #define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 | ||
| 158 | #define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 | ||
| 159 | |||
| 160 | /* Register rw_pa_byte3_oe, scope gio, type rw */ | ||
| 161 | typedef struct { | ||
| 162 | unsigned int oe : 8; | ||
| 163 | unsigned int dummy1 : 24; | ||
| 164 | } reg_gio_rw_pa_byte3_oe; | ||
| 165 | #define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 | ||
| 166 | #define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 | ||
| 167 | |||
| 168 | /* Register r_pb_din, scope gio, type r */ | ||
| 169 | typedef struct { | ||
| 170 | unsigned int data : 32; | ||
| 171 | } reg_gio_r_pb_din; | ||
| 172 | #define REG_RD_ADDR_gio_r_pb_din 44 | ||
| 173 | |||
| 174 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 175 | typedef struct { | ||
| 176 | unsigned int data : 32; | ||
| 177 | } reg_gio_rw_pb_dout; | ||
| 178 | #define REG_RD_ADDR_gio_rw_pb_dout 48 | ||
| 179 | #define REG_WR_ADDR_gio_rw_pb_dout 48 | ||
| 180 | |||
| 181 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 182 | typedef struct { | ||
| 183 | unsigned int oe : 32; | ||
| 184 | } reg_gio_rw_pb_oe; | ||
| 185 | #define REG_RD_ADDR_gio_rw_pb_oe 52 | ||
| 186 | #define REG_WR_ADDR_gio_rw_pb_oe 52 | ||
| 187 | |||
| 188 | /* Register rw_pb_byte0_dout, scope gio, type rw */ | ||
| 189 | typedef struct { | ||
| 190 | unsigned int data : 8; | ||
| 191 | unsigned int dummy1 : 24; | ||
| 192 | } reg_gio_rw_pb_byte0_dout; | ||
| 193 | #define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 | ||
| 194 | #define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 | ||
| 195 | |||
| 196 | /* Register rw_pb_byte0_oe, scope gio, type rw */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int oe : 8; | ||
| 199 | unsigned int dummy1 : 24; | ||
| 200 | } reg_gio_rw_pb_byte0_oe; | ||
| 201 | #define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 | ||
| 202 | #define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 | ||
| 203 | |||
| 204 | /* Register rw_pb_byte1_dout, scope gio, type rw */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int data : 8; | ||
| 207 | unsigned int dummy1 : 24; | ||
| 208 | } reg_gio_rw_pb_byte1_dout; | ||
| 209 | #define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 | ||
| 210 | #define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 | ||
| 211 | |||
| 212 | /* Register rw_pb_byte1_oe, scope gio, type rw */ | ||
| 213 | typedef struct { | ||
| 214 | unsigned int oe : 8; | ||
| 215 | unsigned int dummy1 : 24; | ||
| 216 | } reg_gio_rw_pb_byte1_oe; | ||
| 217 | #define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 | ||
| 218 | #define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 | ||
| 219 | |||
| 220 | /* Register rw_pb_byte2_dout, scope gio, type rw */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int data : 8; | ||
| 223 | unsigned int dummy1 : 24; | ||
| 224 | } reg_gio_rw_pb_byte2_dout; | ||
| 225 | #define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 | ||
| 226 | #define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 | ||
| 227 | |||
| 228 | /* Register rw_pb_byte2_oe, scope gio, type rw */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int oe : 8; | ||
| 231 | unsigned int dummy1 : 24; | ||
| 232 | } reg_gio_rw_pb_byte2_oe; | ||
| 233 | #define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 | ||
| 234 | #define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 | ||
| 235 | |||
| 236 | /* Register rw_pb_byte3_dout, scope gio, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int data : 8; | ||
| 239 | unsigned int dummy1 : 24; | ||
| 240 | } reg_gio_rw_pb_byte3_dout; | ||
| 241 | #define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 | ||
| 242 | #define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 | ||
| 243 | |||
| 244 | /* Register rw_pb_byte3_oe, scope gio, type rw */ | ||
| 245 | typedef struct { | ||
| 246 | unsigned int oe : 8; | ||
| 247 | unsigned int dummy1 : 24; | ||
| 248 | } reg_gio_rw_pb_byte3_oe; | ||
| 249 | #define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 | ||
| 250 | #define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 | ||
| 251 | |||
| 252 | /* Register r_pc_din, scope gio, type r */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int data : 16; | ||
| 255 | unsigned int dummy1 : 16; | ||
| 256 | } reg_gio_r_pc_din; | ||
| 257 | #define REG_RD_ADDR_gio_r_pc_din 88 | ||
| 258 | |||
| 259 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 260 | typedef struct { | ||
| 261 | unsigned int data : 16; | ||
| 262 | unsigned int dummy1 : 16; | ||
| 263 | } reg_gio_rw_pc_dout; | ||
| 264 | #define REG_RD_ADDR_gio_rw_pc_dout 92 | ||
| 265 | #define REG_WR_ADDR_gio_rw_pc_dout 92 | ||
| 266 | |||
| 267 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 268 | typedef struct { | ||
| 269 | unsigned int oe : 16; | ||
| 270 | unsigned int dummy1 : 16; | ||
| 271 | } reg_gio_rw_pc_oe; | ||
| 272 | #define REG_RD_ADDR_gio_rw_pc_oe 96 | ||
| 273 | #define REG_WR_ADDR_gio_rw_pc_oe 96 | ||
| 274 | |||
| 275 | /* Register rw_pc_byte0_dout, scope gio, type rw */ | ||
| 276 | typedef struct { | ||
| 277 | unsigned int data : 8; | ||
| 278 | unsigned int dummy1 : 24; | ||
| 279 | } reg_gio_rw_pc_byte0_dout; | ||
| 280 | #define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 | ||
| 281 | #define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 | ||
| 282 | |||
| 283 | /* Register rw_pc_byte0_oe, scope gio, type rw */ | ||
| 284 | typedef struct { | ||
| 285 | unsigned int oe : 8; | ||
| 286 | unsigned int dummy1 : 24; | ||
| 287 | } reg_gio_rw_pc_byte0_oe; | ||
| 288 | #define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 | ||
| 289 | #define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 | ||
| 290 | |||
| 291 | /* Register rw_pc_byte1_dout, scope gio, type rw */ | ||
| 292 | typedef struct { | ||
| 293 | unsigned int data : 8; | ||
| 294 | unsigned int dummy1 : 24; | ||
| 295 | } reg_gio_rw_pc_byte1_dout; | ||
| 296 | #define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 | ||
| 297 | #define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 | ||
| 298 | |||
| 299 | /* Register rw_pc_byte1_oe, scope gio, type rw */ | ||
| 300 | typedef struct { | ||
| 301 | unsigned int oe : 8; | ||
| 302 | unsigned int dummy1 : 24; | ||
| 303 | } reg_gio_rw_pc_byte1_oe; | ||
| 304 | #define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 | ||
| 305 | #define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 | ||
| 306 | |||
| 307 | /* Register r_pd_din, scope gio, type r */ | ||
| 308 | typedef struct { | ||
| 309 | unsigned int data : 32; | ||
| 310 | } reg_gio_r_pd_din; | ||
| 311 | #define REG_RD_ADDR_gio_r_pd_din 116 | ||
| 312 | |||
| 313 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 314 | typedef struct { | ||
| 315 | unsigned int intr0 : 3; | ||
| 316 | unsigned int intr1 : 3; | ||
| 317 | unsigned int intr2 : 3; | ||
| 318 | unsigned int intr3 : 3; | ||
| 319 | unsigned int intr4 : 3; | ||
| 320 | unsigned int intr5 : 3; | ||
| 321 | unsigned int intr6 : 3; | ||
| 322 | unsigned int intr7 : 3; | ||
| 323 | unsigned int dummy1 : 8; | ||
| 324 | } reg_gio_rw_intr_cfg; | ||
| 325 | #define REG_RD_ADDR_gio_rw_intr_cfg 120 | ||
| 326 | #define REG_WR_ADDR_gio_rw_intr_cfg 120 | ||
| 327 | |||
| 328 | /* Register rw_intr_pins, scope gio, type rw */ | ||
| 329 | typedef struct { | ||
| 330 | unsigned int intr0 : 4; | ||
| 331 | unsigned int intr1 : 4; | ||
| 332 | unsigned int intr2 : 4; | ||
| 333 | unsigned int intr3 : 4; | ||
| 334 | unsigned int intr4 : 4; | ||
| 335 | unsigned int intr5 : 4; | ||
| 336 | unsigned int intr6 : 4; | ||
| 337 | unsigned int intr7 : 4; | ||
| 338 | } reg_gio_rw_intr_pins; | ||
| 339 | #define REG_RD_ADDR_gio_rw_intr_pins 124 | ||
| 340 | #define REG_WR_ADDR_gio_rw_intr_pins 124 | ||
| 341 | |||
| 342 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 343 | typedef struct { | ||
| 344 | unsigned int intr0 : 1; | ||
| 345 | unsigned int intr1 : 1; | ||
| 346 | unsigned int intr2 : 1; | ||
| 347 | unsigned int intr3 : 1; | ||
| 348 | unsigned int intr4 : 1; | ||
| 349 | unsigned int intr5 : 1; | ||
| 350 | unsigned int intr6 : 1; | ||
| 351 | unsigned int intr7 : 1; | ||
| 352 | unsigned int i2c0_done : 1; | ||
| 353 | unsigned int i2c1_done : 1; | ||
| 354 | unsigned int dummy1 : 22; | ||
| 355 | } reg_gio_rw_intr_mask; | ||
| 356 | #define REG_RD_ADDR_gio_rw_intr_mask 128 | ||
| 357 | #define REG_WR_ADDR_gio_rw_intr_mask 128 | ||
| 358 | |||
| 359 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 360 | typedef struct { | ||
| 361 | unsigned int intr0 : 1; | ||
| 362 | unsigned int intr1 : 1; | ||
| 363 | unsigned int intr2 : 1; | ||
| 364 | unsigned int intr3 : 1; | ||
| 365 | unsigned int intr4 : 1; | ||
| 366 | unsigned int intr5 : 1; | ||
| 367 | unsigned int intr6 : 1; | ||
| 368 | unsigned int intr7 : 1; | ||
| 369 | unsigned int i2c0_done : 1; | ||
| 370 | unsigned int i2c1_done : 1; | ||
| 371 | unsigned int dummy1 : 22; | ||
| 372 | } reg_gio_rw_ack_intr; | ||
| 373 | #define REG_RD_ADDR_gio_rw_ack_intr 132 | ||
| 374 | #define REG_WR_ADDR_gio_rw_ack_intr 132 | ||
| 375 | |||
| 376 | /* Register r_intr, scope gio, type r */ | ||
| 377 | typedef struct { | ||
| 378 | unsigned int intr0 : 1; | ||
| 379 | unsigned int intr1 : 1; | ||
| 380 | unsigned int intr2 : 1; | ||
| 381 | unsigned int intr3 : 1; | ||
| 382 | unsigned int intr4 : 1; | ||
| 383 | unsigned int intr5 : 1; | ||
| 384 | unsigned int intr6 : 1; | ||
| 385 | unsigned int intr7 : 1; | ||
| 386 | unsigned int i2c0_done : 1; | ||
| 387 | unsigned int i2c1_done : 1; | ||
| 388 | unsigned int dummy1 : 22; | ||
| 389 | } reg_gio_r_intr; | ||
| 390 | #define REG_RD_ADDR_gio_r_intr 136 | ||
| 391 | |||
| 392 | /* Register r_masked_intr, scope gio, type r */ | ||
| 393 | typedef struct { | ||
| 394 | unsigned int intr0 : 1; | ||
| 395 | unsigned int intr1 : 1; | ||
| 396 | unsigned int intr2 : 1; | ||
| 397 | unsigned int intr3 : 1; | ||
| 398 | unsigned int intr4 : 1; | ||
| 399 | unsigned int intr5 : 1; | ||
| 400 | unsigned int intr6 : 1; | ||
| 401 | unsigned int intr7 : 1; | ||
| 402 | unsigned int i2c0_done : 1; | ||
| 403 | unsigned int i2c1_done : 1; | ||
| 404 | unsigned int dummy1 : 22; | ||
| 405 | } reg_gio_r_masked_intr; | ||
| 406 | #define REG_RD_ADDR_gio_r_masked_intr 140 | ||
| 407 | |||
| 408 | /* Register rw_i2c0_start, scope gio, type rw */ | ||
| 409 | typedef struct { | ||
| 410 | unsigned int run : 1; | ||
| 411 | unsigned int dummy1 : 31; | ||
| 412 | } reg_gio_rw_i2c0_start; | ||
| 413 | #define REG_RD_ADDR_gio_rw_i2c0_start 144 | ||
| 414 | #define REG_WR_ADDR_gio_rw_i2c0_start 144 | ||
| 415 | |||
| 416 | /* Register rw_i2c0_cfg, scope gio, type rw */ | ||
| 417 | typedef struct { | ||
| 418 | unsigned int en : 1; | ||
| 419 | unsigned int bit_order : 1; | ||
| 420 | unsigned int scl_io : 1; | ||
| 421 | unsigned int scl_inv : 1; | ||
| 422 | unsigned int sda_io : 1; | ||
| 423 | unsigned int sda_idle : 1; | ||
| 424 | unsigned int dummy1 : 26; | ||
| 425 | } reg_gio_rw_i2c0_cfg; | ||
| 426 | #define REG_RD_ADDR_gio_rw_i2c0_cfg 148 | ||
| 427 | #define REG_WR_ADDR_gio_rw_i2c0_cfg 148 | ||
| 428 | |||
| 429 | /* Register rw_i2c0_ctrl, scope gio, type rw */ | ||
| 430 | typedef struct { | ||
| 431 | unsigned int trf_bits : 6; | ||
| 432 | unsigned int switch_dir : 6; | ||
| 433 | unsigned int extra_start : 3; | ||
| 434 | unsigned int early_end : 1; | ||
| 435 | unsigned int start_stop : 1; | ||
| 436 | unsigned int ack_dir0 : 1; | ||
| 437 | unsigned int ack_dir1 : 1; | ||
| 438 | unsigned int ack_dir2 : 1; | ||
| 439 | unsigned int ack_dir3 : 1; | ||
| 440 | unsigned int ack_dir4 : 1; | ||
| 441 | unsigned int ack_dir5 : 1; | ||
| 442 | unsigned int ack_bit : 1; | ||
| 443 | unsigned int start_bit : 1; | ||
| 444 | unsigned int freq : 2; | ||
| 445 | unsigned int dummy1 : 5; | ||
| 446 | } reg_gio_rw_i2c0_ctrl; | ||
| 447 | #define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 | ||
| 448 | #define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 | ||
| 449 | |||
| 450 | /* Register rw_i2c0_data, scope gio, type rw */ | ||
| 451 | typedef struct { | ||
| 452 | unsigned int data0 : 8; | ||
| 453 | unsigned int data1 : 8; | ||
| 454 | unsigned int data2 : 8; | ||
| 455 | unsigned int data3 : 8; | ||
| 456 | } reg_gio_rw_i2c0_data; | ||
| 457 | #define REG_RD_ADDR_gio_rw_i2c0_data 156 | ||
| 458 | #define REG_WR_ADDR_gio_rw_i2c0_data 156 | ||
| 459 | |||
| 460 | /* Register rw_i2c0_data2, scope gio, type rw */ | ||
| 461 | typedef struct { | ||
| 462 | unsigned int data4 : 8; | ||
| 463 | unsigned int data5 : 8; | ||
| 464 | unsigned int start_val : 6; | ||
| 465 | unsigned int ack_val : 6; | ||
| 466 | unsigned int dummy1 : 4; | ||
| 467 | } reg_gio_rw_i2c0_data2; | ||
| 468 | #define REG_RD_ADDR_gio_rw_i2c0_data2 160 | ||
| 469 | #define REG_WR_ADDR_gio_rw_i2c0_data2 160 | ||
| 470 | |||
| 471 | /* Register rw_i2c1_start, scope gio, type rw */ | ||
| 472 | typedef struct { | ||
| 473 | unsigned int run : 1; | ||
| 474 | unsigned int dummy1 : 31; | ||
| 475 | } reg_gio_rw_i2c1_start; | ||
| 476 | #define REG_RD_ADDR_gio_rw_i2c1_start 164 | ||
| 477 | #define REG_WR_ADDR_gio_rw_i2c1_start 164 | ||
| 478 | |||
| 479 | /* Register rw_i2c1_cfg, scope gio, type rw */ | ||
| 480 | typedef struct { | ||
| 481 | unsigned int en : 1; | ||
| 482 | unsigned int bit_order : 1; | ||
| 483 | unsigned int scl_io : 1; | ||
| 484 | unsigned int scl_inv : 1; | ||
| 485 | unsigned int sda0_io : 1; | ||
| 486 | unsigned int sda0_idle : 1; | ||
| 487 | unsigned int sda1_io : 1; | ||
| 488 | unsigned int sda1_idle : 1; | ||
| 489 | unsigned int sda2_io : 1; | ||
| 490 | unsigned int sda2_idle : 1; | ||
| 491 | unsigned int sda3_io : 1; | ||
| 492 | unsigned int sda3_idle : 1; | ||
| 493 | unsigned int sda_sel : 2; | ||
| 494 | unsigned int sen_idle : 1; | ||
| 495 | unsigned int sen_inv : 1; | ||
| 496 | unsigned int sen_sel : 2; | ||
| 497 | unsigned int dummy1 : 14; | ||
| 498 | } reg_gio_rw_i2c1_cfg; | ||
| 499 | #define REG_RD_ADDR_gio_rw_i2c1_cfg 168 | ||
| 500 | #define REG_WR_ADDR_gio_rw_i2c1_cfg 168 | ||
| 501 | |||
| 502 | /* Register rw_i2c1_ctrl, scope gio, type rw */ | ||
| 503 | typedef struct { | ||
| 504 | unsigned int trf_bits : 6; | ||
| 505 | unsigned int switch_dir : 6; | ||
| 506 | unsigned int extra_start : 3; | ||
| 507 | unsigned int early_end : 1; | ||
| 508 | unsigned int start_stop : 1; | ||
| 509 | unsigned int ack_dir0 : 1; | ||
| 510 | unsigned int ack_dir1 : 1; | ||
| 511 | unsigned int ack_dir2 : 1; | ||
| 512 | unsigned int ack_dir3 : 1; | ||
| 513 | unsigned int ack_dir4 : 1; | ||
| 514 | unsigned int ack_dir5 : 1; | ||
| 515 | unsigned int ack_bit : 1; | ||
| 516 | unsigned int start_bit : 1; | ||
| 517 | unsigned int freq : 2; | ||
| 518 | unsigned int dummy1 : 5; | ||
| 519 | } reg_gio_rw_i2c1_ctrl; | ||
| 520 | #define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 | ||
| 521 | #define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 | ||
| 522 | |||
| 523 | /* Register rw_i2c1_data, scope gio, type rw */ | ||
| 524 | typedef struct { | ||
| 525 | unsigned int data0 : 8; | ||
| 526 | unsigned int data1 : 8; | ||
| 527 | unsigned int data2 : 8; | ||
| 528 | unsigned int data3 : 8; | ||
| 529 | } reg_gio_rw_i2c1_data; | ||
| 530 | #define REG_RD_ADDR_gio_rw_i2c1_data 176 | ||
| 531 | #define REG_WR_ADDR_gio_rw_i2c1_data 176 | ||
| 532 | |||
| 533 | /* Register rw_i2c1_data2, scope gio, type rw */ | ||
| 534 | typedef struct { | ||
| 535 | unsigned int data4 : 8; | ||
| 536 | unsigned int data5 : 8; | ||
| 537 | unsigned int start_val : 6; | ||
| 538 | unsigned int ack_val : 6; | ||
| 539 | unsigned int dummy1 : 4; | ||
| 540 | } reg_gio_rw_i2c1_data2; | ||
| 541 | #define REG_RD_ADDR_gio_rw_i2c1_data2 180 | ||
| 542 | #define REG_WR_ADDR_gio_rw_i2c1_data2 180 | ||
| 543 | |||
| 544 | /* Register r_ppwm_stat, scope gio, type r */ | ||
| 545 | typedef struct { | ||
| 546 | unsigned int freq : 2; | ||
| 547 | unsigned int dummy1 : 30; | ||
| 548 | } reg_gio_r_ppwm_stat; | ||
| 549 | #define REG_RD_ADDR_gio_r_ppwm_stat 184 | ||
| 550 | |||
| 551 | /* Register rw_ppwm_data, scope gio, type rw */ | ||
| 552 | typedef struct { | ||
| 553 | unsigned int data : 8; | ||
| 554 | unsigned int dummy1 : 24; | ||
| 555 | } reg_gio_rw_ppwm_data; | ||
| 556 | #define REG_RD_ADDR_gio_rw_ppwm_data 188 | ||
| 557 | #define REG_WR_ADDR_gio_rw_ppwm_data 188 | ||
| 558 | |||
| 559 | /* Register rw_pwm0_ctrl, scope gio, type rw */ | ||
| 560 | typedef struct { | ||
| 561 | unsigned int mode : 2; | ||
| 562 | unsigned int ccd_override : 1; | ||
| 563 | unsigned int ccd_val : 1; | ||
| 564 | unsigned int dummy1 : 28; | ||
| 565 | } reg_gio_rw_pwm0_ctrl; | ||
| 566 | #define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 | ||
| 567 | #define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 | ||
| 568 | |||
| 569 | /* Register rw_pwm0_var, scope gio, type rw */ | ||
| 570 | typedef struct { | ||
| 571 | unsigned int lo : 13; | ||
| 572 | unsigned int hi : 13; | ||
| 573 | unsigned int dummy1 : 6; | ||
| 574 | } reg_gio_rw_pwm0_var; | ||
| 575 | #define REG_RD_ADDR_gio_rw_pwm0_var 196 | ||
| 576 | #define REG_WR_ADDR_gio_rw_pwm0_var 196 | ||
| 577 | |||
| 578 | /* Register rw_pwm0_data, scope gio, type rw */ | ||
| 579 | typedef struct { | ||
| 580 | unsigned int data : 8; | ||
| 581 | unsigned int dummy1 : 24; | ||
| 582 | } reg_gio_rw_pwm0_data; | ||
| 583 | #define REG_RD_ADDR_gio_rw_pwm0_data 200 | ||
| 584 | #define REG_WR_ADDR_gio_rw_pwm0_data 200 | ||
| 585 | |||
| 586 | /* Register rw_pwm1_ctrl, scope gio, type rw */ | ||
| 587 | typedef struct { | ||
| 588 | unsigned int mode : 2; | ||
| 589 | unsigned int ccd_override : 1; | ||
| 590 | unsigned int ccd_val : 1; | ||
| 591 | unsigned int dummy1 : 28; | ||
| 592 | } reg_gio_rw_pwm1_ctrl; | ||
| 593 | #define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 | ||
| 594 | #define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 | ||
| 595 | |||
| 596 | /* Register rw_pwm1_var, scope gio, type rw */ | ||
| 597 | typedef struct { | ||
| 598 | unsigned int lo : 13; | ||
| 599 | unsigned int hi : 13; | ||
| 600 | unsigned int dummy1 : 6; | ||
| 601 | } reg_gio_rw_pwm1_var; | ||
| 602 | #define REG_RD_ADDR_gio_rw_pwm1_var 208 | ||
| 603 | #define REG_WR_ADDR_gio_rw_pwm1_var 208 | ||
| 604 | |||
| 605 | /* Register rw_pwm1_data, scope gio, type rw */ | ||
| 606 | typedef struct { | ||
| 607 | unsigned int data : 8; | ||
| 608 | unsigned int dummy1 : 24; | ||
| 609 | } reg_gio_rw_pwm1_data; | ||
| 610 | #define REG_RD_ADDR_gio_rw_pwm1_data 212 | ||
| 611 | #define REG_WR_ADDR_gio_rw_pwm1_data 212 | ||
| 612 | |||
| 613 | /* Register rw_pwm2_ctrl, scope gio, type rw */ | ||
| 614 | typedef struct { | ||
| 615 | unsigned int mode : 2; | ||
| 616 | unsigned int ccd_override : 1; | ||
| 617 | unsigned int ccd_val : 1; | ||
| 618 | unsigned int dummy1 : 28; | ||
| 619 | } reg_gio_rw_pwm2_ctrl; | ||
| 620 | #define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 | ||
| 621 | #define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 | ||
| 622 | |||
| 623 | /* Register rw_pwm2_var, scope gio, type rw */ | ||
| 624 | typedef struct { | ||
| 625 | unsigned int lo : 13; | ||
| 626 | unsigned int hi : 13; | ||
| 627 | unsigned int dummy1 : 6; | ||
| 628 | } reg_gio_rw_pwm2_var; | ||
| 629 | #define REG_RD_ADDR_gio_rw_pwm2_var 220 | ||
| 630 | #define REG_WR_ADDR_gio_rw_pwm2_var 220 | ||
| 631 | |||
| 632 | /* Register rw_pwm2_data, scope gio, type rw */ | ||
| 633 | typedef struct { | ||
| 634 | unsigned int data : 8; | ||
| 635 | unsigned int dummy1 : 24; | ||
| 636 | } reg_gio_rw_pwm2_data; | ||
| 637 | #define REG_RD_ADDR_gio_rw_pwm2_data 224 | ||
| 638 | #define REG_WR_ADDR_gio_rw_pwm2_data 224 | ||
| 639 | |||
| 640 | /* Register rw_pwm_in_cfg, scope gio, type rw */ | ||
| 641 | typedef struct { | ||
| 642 | unsigned int pin : 3; | ||
| 643 | unsigned int dummy1 : 29; | ||
| 644 | } reg_gio_rw_pwm_in_cfg; | ||
| 645 | #define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 | ||
| 646 | #define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 | ||
| 647 | |||
| 648 | /* Register r_pwm_in_lo, scope gio, type r */ | ||
| 649 | typedef struct { | ||
| 650 | unsigned int data : 32; | ||
| 651 | } reg_gio_r_pwm_in_lo; | ||
| 652 | #define REG_RD_ADDR_gio_r_pwm_in_lo 232 | ||
| 653 | |||
| 654 | /* Register r_pwm_in_hi, scope gio, type r */ | ||
| 655 | typedef struct { | ||
| 656 | unsigned int data : 32; | ||
| 657 | } reg_gio_r_pwm_in_hi; | ||
| 658 | #define REG_RD_ADDR_gio_r_pwm_in_hi 236 | ||
| 659 | |||
| 660 | /* Register r_pwm_in_cnt, scope gio, type r */ | ||
| 661 | typedef struct { | ||
| 662 | unsigned int data : 32; | ||
| 663 | } reg_gio_r_pwm_in_cnt; | ||
| 664 | #define REG_RD_ADDR_gio_r_pwm_in_cnt 240 | ||
| 665 | |||
| 666 | |||
| 667 | /* Constants */ | ||
| 668 | enum { | ||
| 669 | regk_gio_anyedge = 0x00000007, | ||
| 670 | regk_gio_f100k = 0x00000000, | ||
| 671 | regk_gio_f1562 = 0x00000000, | ||
| 672 | regk_gio_f195 = 0x00000003, | ||
| 673 | regk_gio_f1m = 0x00000002, | ||
| 674 | regk_gio_f390 = 0x00000002, | ||
| 675 | regk_gio_f400k = 0x00000001, | ||
| 676 | regk_gio_f5m = 0x00000003, | ||
| 677 | regk_gio_f781 = 0x00000001, | ||
| 678 | regk_gio_hi = 0x00000001, | ||
| 679 | regk_gio_in = 0x00000000, | ||
| 680 | regk_gio_intr_pa0 = 0x00000000, | ||
| 681 | regk_gio_intr_pa1 = 0x00000000, | ||
| 682 | regk_gio_intr_pa10 = 0x00000001, | ||
| 683 | regk_gio_intr_pa11 = 0x00000001, | ||
| 684 | regk_gio_intr_pa12 = 0x00000001, | ||
| 685 | regk_gio_intr_pa13 = 0x00000001, | ||
| 686 | regk_gio_intr_pa14 = 0x00000001, | ||
| 687 | regk_gio_intr_pa15 = 0x00000001, | ||
| 688 | regk_gio_intr_pa16 = 0x00000002, | ||
| 689 | regk_gio_intr_pa17 = 0x00000002, | ||
| 690 | regk_gio_intr_pa18 = 0x00000002, | ||
| 691 | regk_gio_intr_pa19 = 0x00000002, | ||
| 692 | regk_gio_intr_pa2 = 0x00000000, | ||
| 693 | regk_gio_intr_pa20 = 0x00000002, | ||
| 694 | regk_gio_intr_pa21 = 0x00000002, | ||
| 695 | regk_gio_intr_pa22 = 0x00000002, | ||
| 696 | regk_gio_intr_pa23 = 0x00000002, | ||
| 697 | regk_gio_intr_pa24 = 0x00000003, | ||
| 698 | regk_gio_intr_pa25 = 0x00000003, | ||
| 699 | regk_gio_intr_pa26 = 0x00000003, | ||
| 700 | regk_gio_intr_pa27 = 0x00000003, | ||
| 701 | regk_gio_intr_pa28 = 0x00000003, | ||
| 702 | regk_gio_intr_pa29 = 0x00000003, | ||
| 703 | regk_gio_intr_pa3 = 0x00000000, | ||
| 704 | regk_gio_intr_pa30 = 0x00000003, | ||
| 705 | regk_gio_intr_pa31 = 0x00000003, | ||
| 706 | regk_gio_intr_pa4 = 0x00000000, | ||
| 707 | regk_gio_intr_pa5 = 0x00000000, | ||
| 708 | regk_gio_intr_pa6 = 0x00000000, | ||
| 709 | regk_gio_intr_pa7 = 0x00000000, | ||
| 710 | regk_gio_intr_pa8 = 0x00000001, | ||
| 711 | regk_gio_intr_pa9 = 0x00000001, | ||
| 712 | regk_gio_intr_pb0 = 0x00000004, | ||
| 713 | regk_gio_intr_pb1 = 0x00000004, | ||
| 714 | regk_gio_intr_pb10 = 0x00000005, | ||
| 715 | regk_gio_intr_pb11 = 0x00000005, | ||
| 716 | regk_gio_intr_pb12 = 0x00000005, | ||
| 717 | regk_gio_intr_pb13 = 0x00000005, | ||
| 718 | regk_gio_intr_pb14 = 0x00000005, | ||
| 719 | regk_gio_intr_pb15 = 0x00000005, | ||
| 720 | regk_gio_intr_pb16 = 0x00000006, | ||
| 721 | regk_gio_intr_pb17 = 0x00000006, | ||
| 722 | regk_gio_intr_pb18 = 0x00000006, | ||
| 723 | regk_gio_intr_pb19 = 0x00000006, | ||
| 724 | regk_gio_intr_pb2 = 0x00000004, | ||
| 725 | regk_gio_intr_pb20 = 0x00000006, | ||
| 726 | regk_gio_intr_pb21 = 0x00000006, | ||
| 727 | regk_gio_intr_pb22 = 0x00000006, | ||
| 728 | regk_gio_intr_pb23 = 0x00000006, | ||
| 729 | regk_gio_intr_pb24 = 0x00000007, | ||
| 730 | regk_gio_intr_pb25 = 0x00000007, | ||
| 731 | regk_gio_intr_pb26 = 0x00000007, | ||
| 732 | regk_gio_intr_pb27 = 0x00000007, | ||
| 733 | regk_gio_intr_pb28 = 0x00000007, | ||
| 734 | regk_gio_intr_pb29 = 0x00000007, | ||
| 735 | regk_gio_intr_pb3 = 0x00000004, | ||
| 736 | regk_gio_intr_pb30 = 0x00000007, | ||
| 737 | regk_gio_intr_pb31 = 0x00000007, | ||
| 738 | regk_gio_intr_pb4 = 0x00000004, | ||
| 739 | regk_gio_intr_pb5 = 0x00000004, | ||
| 740 | regk_gio_intr_pb6 = 0x00000004, | ||
| 741 | regk_gio_intr_pb7 = 0x00000004, | ||
| 742 | regk_gio_intr_pb8 = 0x00000005, | ||
| 743 | regk_gio_intr_pb9 = 0x00000005, | ||
| 744 | regk_gio_intr_pc0 = 0x00000008, | ||
| 745 | regk_gio_intr_pc1 = 0x00000008, | ||
| 746 | regk_gio_intr_pc10 = 0x00000009, | ||
| 747 | regk_gio_intr_pc11 = 0x00000009, | ||
| 748 | regk_gio_intr_pc12 = 0x00000009, | ||
| 749 | regk_gio_intr_pc13 = 0x00000009, | ||
| 750 | regk_gio_intr_pc14 = 0x00000009, | ||
| 751 | regk_gio_intr_pc15 = 0x00000009, | ||
| 752 | regk_gio_intr_pc2 = 0x00000008, | ||
| 753 | regk_gio_intr_pc3 = 0x00000008, | ||
| 754 | regk_gio_intr_pc4 = 0x00000008, | ||
| 755 | regk_gio_intr_pc5 = 0x00000008, | ||
| 756 | regk_gio_intr_pc6 = 0x00000008, | ||
| 757 | regk_gio_intr_pc7 = 0x00000008, | ||
| 758 | regk_gio_intr_pc8 = 0x00000009, | ||
| 759 | regk_gio_intr_pc9 = 0x00000009, | ||
| 760 | regk_gio_intr_pd0 = 0x0000000c, | ||
| 761 | regk_gio_intr_pd1 = 0x0000000c, | ||
| 762 | regk_gio_intr_pd10 = 0x0000000d, | ||
| 763 | regk_gio_intr_pd11 = 0x0000000d, | ||
| 764 | regk_gio_intr_pd12 = 0x0000000d, | ||
| 765 | regk_gio_intr_pd13 = 0x0000000d, | ||
| 766 | regk_gio_intr_pd14 = 0x0000000d, | ||
| 767 | regk_gio_intr_pd15 = 0x0000000d, | ||
| 768 | regk_gio_intr_pd16 = 0x0000000e, | ||
| 769 | regk_gio_intr_pd17 = 0x0000000e, | ||
| 770 | regk_gio_intr_pd18 = 0x0000000e, | ||
| 771 | regk_gio_intr_pd19 = 0x0000000e, | ||
| 772 | regk_gio_intr_pd2 = 0x0000000c, | ||
| 773 | regk_gio_intr_pd20 = 0x0000000e, | ||
| 774 | regk_gio_intr_pd21 = 0x0000000e, | ||
| 775 | regk_gio_intr_pd22 = 0x0000000e, | ||
| 776 | regk_gio_intr_pd23 = 0x0000000e, | ||
| 777 | regk_gio_intr_pd24 = 0x0000000f, | ||
| 778 | regk_gio_intr_pd25 = 0x0000000f, | ||
| 779 | regk_gio_intr_pd26 = 0x0000000f, | ||
| 780 | regk_gio_intr_pd27 = 0x0000000f, | ||
| 781 | regk_gio_intr_pd28 = 0x0000000f, | ||
| 782 | regk_gio_intr_pd29 = 0x0000000f, | ||
| 783 | regk_gio_intr_pd3 = 0x0000000c, | ||
| 784 | regk_gio_intr_pd30 = 0x0000000f, | ||
| 785 | regk_gio_intr_pd31 = 0x0000000f, | ||
| 786 | regk_gio_intr_pd4 = 0x0000000c, | ||
| 787 | regk_gio_intr_pd5 = 0x0000000c, | ||
| 788 | regk_gio_intr_pd6 = 0x0000000c, | ||
| 789 | regk_gio_intr_pd7 = 0x0000000c, | ||
| 790 | regk_gio_intr_pd8 = 0x0000000d, | ||
| 791 | regk_gio_intr_pd9 = 0x0000000d, | ||
| 792 | regk_gio_lo = 0x00000002, | ||
| 793 | regk_gio_lsb = 0x00000000, | ||
| 794 | regk_gio_msb = 0x00000001, | ||
| 795 | regk_gio_negedge = 0x00000006, | ||
| 796 | regk_gio_no = 0x00000000, | ||
| 797 | regk_gio_no_switch = 0x0000003f, | ||
| 798 | regk_gio_none = 0x00000007, | ||
| 799 | regk_gio_off = 0x00000000, | ||
| 800 | regk_gio_opendrain = 0x00000000, | ||
| 801 | regk_gio_out = 0x00000001, | ||
| 802 | regk_gio_posedge = 0x00000005, | ||
| 803 | regk_gio_pwm_hfp = 0x00000002, | ||
| 804 | regk_gio_pwm_pa0 = 0x00000001, | ||
| 805 | regk_gio_pwm_pa19 = 0x00000004, | ||
| 806 | regk_gio_pwm_pa6 = 0x00000002, | ||
| 807 | regk_gio_pwm_pa7 = 0x00000003, | ||
| 808 | regk_gio_pwm_pb26 = 0x00000005, | ||
| 809 | regk_gio_pwm_pd23 = 0x00000006, | ||
| 810 | regk_gio_pwm_pd31 = 0x00000007, | ||
| 811 | regk_gio_pwm_std = 0x00000001, | ||
| 812 | regk_gio_pwm_var = 0x00000003, | ||
| 813 | regk_gio_rw_i2c0_cfg_default = 0x00000020, | ||
| 814 | regk_gio_rw_i2c0_ctrl_default = 0x00010000, | ||
| 815 | regk_gio_rw_i2c0_start_default = 0x00000000, | ||
| 816 | regk_gio_rw_i2c1_cfg_default = 0x00000aa0, | ||
| 817 | regk_gio_rw_i2c1_ctrl_default = 0x00010000, | ||
| 818 | regk_gio_rw_i2c1_start_default = 0x00000000, | ||
| 819 | regk_gio_rw_intr_cfg_default = 0x00000000, | ||
| 820 | regk_gio_rw_intr_mask_default = 0x00000000, | ||
| 821 | regk_gio_rw_pa_oe_default = 0x00000000, | ||
| 822 | regk_gio_rw_pb_oe_default = 0x00000000, | ||
| 823 | regk_gio_rw_pc_oe_default = 0x00000000, | ||
| 824 | regk_gio_rw_ppwm_data_default = 0x00000000, | ||
| 825 | regk_gio_rw_pwm0_ctrl_default = 0x00000000, | ||
| 826 | regk_gio_rw_pwm1_ctrl_default = 0x00000000, | ||
| 827 | regk_gio_rw_pwm2_ctrl_default = 0x00000000, | ||
| 828 | regk_gio_rw_pwm_in_cfg_default = 0x00000000, | ||
| 829 | regk_gio_sda0 = 0x00000000, | ||
| 830 | regk_gio_sda1 = 0x00000001, | ||
| 831 | regk_gio_sda2 = 0x00000002, | ||
| 832 | regk_gio_sda3 = 0x00000003, | ||
| 833 | regk_gio_sen = 0x00000000, | ||
| 834 | regk_gio_set = 0x00000003, | ||
| 835 | regk_gio_yes = 0x00000001 | ||
| 836 | }; | ||
| 837 | #endif /* __gio_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h deleted file mode 100644 index bea699aa480e..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr | ||
| 2 | from intr_vect.r */ | ||
| 3 | |||
| 4 | #ifndef _INTR_VECT_R | ||
| 5 | #define _INTR_VECT_R | ||
| 6 | #define TIMER0_INTR_VECT 0x31 | ||
| 7 | #define TIMER1_INTR_VECT 0x32 | ||
| 8 | #define DMA0_INTR_VECT 0x33 | ||
| 9 | #define DMA1_INTR_VECT 0x34 | ||
| 10 | #define DMA2_INTR_VECT 0x35 | ||
| 11 | #define DMA3_INTR_VECT 0x36 | ||
| 12 | #define DMA4_INTR_VECT 0x37 | ||
| 13 | #define DMA5_INTR_VECT 0x38 | ||
| 14 | #define DMA6_INTR_VECT 0x39 | ||
| 15 | #define DMA7_INTR_VECT 0x3a | ||
| 16 | #define DMA9_INTR_VECT 0x3b | ||
| 17 | #define DMA11_INTR_VECT 0x3c | ||
| 18 | #define GIO_INTR_VECT 0x3d | ||
| 19 | #define IOP0_INTR_VECT 0x3e | ||
| 20 | #define IOP1_INTR_VECT 0x3f | ||
| 21 | #define SER0_INTR_VECT 0x40 | ||
| 22 | #define SER1_INTR_VECT 0x41 | ||
| 23 | #define SER2_INTR_VECT 0x42 | ||
| 24 | #define SER3_INTR_VECT 0x43 | ||
| 25 | #define SER4_INTR_VECT 0x44 | ||
| 26 | #define SSER_INTR_VECT 0x45 | ||
| 27 | #define STRDMA0_INTR_VECT 0x46 | ||
| 28 | #define STRDMA1_INTR_VECT 0x47 | ||
| 29 | #define STRDMA2_INTR_VECT 0x48 | ||
| 30 | #define STRDMA3_INTR_VECT 0x49 | ||
| 31 | #define STRDMA5_INTR_VECT 0x4a | ||
| 32 | #define VIN_INTR_VECT 0x4b | ||
| 33 | #define VOUT_INTR_VECT 0x4c | ||
| 34 | #define JPEG_INTR_VECT 0x4d | ||
| 35 | #define H264_INTR_VECT 0x4e | ||
| 36 | #define HISTO_INTR_VECT 0x4f | ||
| 37 | #define CCD_INTR_VECT 0x50 | ||
| 38 | #define ETH_INTR_VECT 0x51 | ||
| 39 | #define MEMARB_BAR_INTR_VECT 0x52 | ||
| 40 | #define MEMARB_FOO_INTR_VECT 0x53 | ||
| 41 | #define PIO_INTR_VECT 0x54 | ||
| 42 | #define SCLR_INTR_VECT 0x55 | ||
| 43 | #define SCLR_FIFO_INTR_VECT 0x56 | ||
| 44 | #define IPI_INTR_VECT 0x57 | ||
| 45 | #define NBR_INTR_VECT 0x58 | ||
| 46 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h deleted file mode 100644 index b820f6347c74..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h +++ /dev/null | |||
| @@ -1,341 +0,0 @@ | |||
| 1 | #ifndef __intr_vect_defs_h | ||
| 2 | #define __intr_vect_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: intr_vect.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope intr_vect */ | ||
| 83 | |||
| 84 | |||
| 85 | #define STRIDE_intr_vect_rw_mask 4 | ||
| 86 | /* Register rw_mask0, scope intr_vect, type rw */ | ||
| 87 | typedef struct { | ||
| 88 | unsigned int timer0 : 1; | ||
| 89 | unsigned int timer1 : 1; | ||
| 90 | unsigned int dma0 : 1; | ||
| 91 | unsigned int dma1 : 1; | ||
| 92 | unsigned int dma2 : 1; | ||
| 93 | unsigned int dma3 : 1; | ||
| 94 | unsigned int dma4 : 1; | ||
| 95 | unsigned int dma5 : 1; | ||
| 96 | unsigned int dma6 : 1; | ||
| 97 | unsigned int dma7 : 1; | ||
| 98 | unsigned int dma9 : 1; | ||
| 99 | unsigned int dma11 : 1; | ||
| 100 | unsigned int gio : 1; | ||
| 101 | unsigned int iop0 : 1; | ||
| 102 | unsigned int iop1 : 1; | ||
| 103 | unsigned int ser0 : 1; | ||
| 104 | unsigned int ser1 : 1; | ||
| 105 | unsigned int ser2 : 1; | ||
| 106 | unsigned int ser3 : 1; | ||
| 107 | unsigned int ser4 : 1; | ||
| 108 | unsigned int sser : 1; | ||
| 109 | unsigned int strdma0 : 1; | ||
| 110 | unsigned int strdma1 : 1; | ||
| 111 | unsigned int strdma2 : 1; | ||
| 112 | unsigned int strdma3 : 1; | ||
| 113 | unsigned int strdma5 : 1; | ||
| 114 | unsigned int vin : 1; | ||
| 115 | unsigned int vout : 1; | ||
| 116 | unsigned int jpeg : 1; | ||
| 117 | unsigned int h264 : 1; | ||
| 118 | unsigned int histo : 1; | ||
| 119 | unsigned int ccd : 1; | ||
| 120 | } reg_intr_vect_rw_mask0; | ||
| 121 | #define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0 | ||
| 122 | #define REG_RD_ADDR_intr_vect_rw_mask 0 | ||
| 123 | #define REG_WR_ADDR_intr_vect_rw_mask 0 | ||
| 124 | #define REG_RD_ADDR_intr_vect_rw_mask0 0 | ||
| 125 | #define REG_WR_ADDR_intr_vect_rw_mask0 0 | ||
| 126 | |||
| 127 | #define STRIDE_intr_vect_r_vect 4 | ||
| 128 | /* Register r_vect0, scope intr_vect, type r */ | ||
| 129 | typedef struct { | ||
| 130 | unsigned int timer0 : 1; | ||
| 131 | unsigned int timer1 : 1; | ||
| 132 | unsigned int dma0 : 1; | ||
| 133 | unsigned int dma1 : 1; | ||
| 134 | unsigned int dma2 : 1; | ||
| 135 | unsigned int dma3 : 1; | ||
| 136 | unsigned int dma4 : 1; | ||
| 137 | unsigned int dma5 : 1; | ||
| 138 | unsigned int dma6 : 1; | ||
| 139 | unsigned int dma7 : 1; | ||
| 140 | unsigned int dma9 : 1; | ||
| 141 | unsigned int dma11 : 1; | ||
| 142 | unsigned int gio : 1; | ||
| 143 | unsigned int iop0 : 1; | ||
| 144 | unsigned int iop1 : 1; | ||
| 145 | unsigned int ser0 : 1; | ||
| 146 | unsigned int ser1 : 1; | ||
| 147 | unsigned int ser2 : 1; | ||
| 148 | unsigned int ser3 : 1; | ||
| 149 | unsigned int ser4 : 1; | ||
| 150 | unsigned int sser : 1; | ||
| 151 | unsigned int strdma0 : 1; | ||
| 152 | unsigned int strdma1 : 1; | ||
| 153 | unsigned int strdma2 : 1; | ||
| 154 | unsigned int strdma3 : 1; | ||
| 155 | unsigned int strdma5 : 1; | ||
| 156 | unsigned int vin : 1; | ||
| 157 | unsigned int vout : 1; | ||
| 158 | unsigned int jpeg : 1; | ||
| 159 | unsigned int h264 : 1; | ||
| 160 | unsigned int histo : 1; | ||
| 161 | unsigned int ccd : 1; | ||
| 162 | } reg_intr_vect_r_vect0; | ||
| 163 | #define reg_intr_vect_r_vect reg_intr_vect_r_vect0 | ||
| 164 | #define REG_RD_ADDR_intr_vect_r_vect 8 | ||
| 165 | #define REG_RD_ADDR_intr_vect_r_vect0 8 | ||
| 166 | |||
| 167 | #define STRIDE_intr_vect_r_masked_vect 4 | ||
| 168 | /* Register r_masked_vect0, scope intr_vect, type r */ | ||
| 169 | typedef struct { | ||
| 170 | unsigned int timer0 : 1; | ||
| 171 | unsigned int timer1 : 1; | ||
| 172 | unsigned int dma0 : 1; | ||
| 173 | unsigned int dma1 : 1; | ||
| 174 | unsigned int dma2 : 1; | ||
| 175 | unsigned int dma3 : 1; | ||
| 176 | unsigned int dma4 : 1; | ||
| 177 | unsigned int dma5 : 1; | ||
| 178 | unsigned int dma6 : 1; | ||
| 179 | unsigned int dma7 : 1; | ||
| 180 | unsigned int dma9 : 1; | ||
| 181 | unsigned int dma11 : 1; | ||
| 182 | unsigned int gio : 1; | ||
| 183 | unsigned int iop0 : 1; | ||
| 184 | unsigned int iop1 : 1; | ||
| 185 | unsigned int ser0 : 1; | ||
| 186 | unsigned int ser1 : 1; | ||
| 187 | unsigned int ser2 : 1; | ||
| 188 | unsigned int ser3 : 1; | ||
| 189 | unsigned int ser4 : 1; | ||
| 190 | unsigned int sser : 1; | ||
| 191 | unsigned int strdma0 : 1; | ||
| 192 | unsigned int strdma1 : 1; | ||
| 193 | unsigned int strdma2 : 1; | ||
| 194 | unsigned int strdma3 : 1; | ||
| 195 | unsigned int strdma5 : 1; | ||
| 196 | unsigned int vin : 1; | ||
| 197 | unsigned int vout : 1; | ||
| 198 | unsigned int jpeg : 1; | ||
| 199 | unsigned int h264 : 1; | ||
| 200 | unsigned int histo : 1; | ||
| 201 | unsigned int ccd : 1; | ||
| 202 | } reg_intr_vect_r_masked_vect0; | ||
| 203 | #define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0 | ||
| 204 | #define REG_RD_ADDR_intr_vect_r_masked_vect0 16 | ||
| 205 | #define REG_RD_ADDR_intr_vect_r_masked_vect 16 | ||
| 206 | |||
| 207 | #define STRIDE_intr_vect_rw_xmask 4 | ||
| 208 | /* Register rw_xmask0, scope intr_vect, type rw */ | ||
| 209 | typedef struct { | ||
| 210 | unsigned int timer0 : 1; | ||
| 211 | unsigned int timer1 : 1; | ||
| 212 | unsigned int dma0 : 1; | ||
| 213 | unsigned int dma1 : 1; | ||
| 214 | unsigned int dma2 : 1; | ||
| 215 | unsigned int dma3 : 1; | ||
| 216 | unsigned int dma4 : 1; | ||
| 217 | unsigned int dma5 : 1; | ||
| 218 | unsigned int dma6 : 1; | ||
| 219 | unsigned int dma7 : 1; | ||
| 220 | unsigned int dma9 : 1; | ||
| 221 | unsigned int dma11 : 1; | ||
| 222 | unsigned int gio : 1; | ||
| 223 | unsigned int iop0 : 1; | ||
| 224 | unsigned int iop1 : 1; | ||
| 225 | unsigned int ser0 : 1; | ||
| 226 | unsigned int ser1 : 1; | ||
| 227 | unsigned int ser2 : 1; | ||
| 228 | unsigned int ser3 : 1; | ||
| 229 | unsigned int ser4 : 1; | ||
| 230 | unsigned int sser : 1; | ||
| 231 | unsigned int strdma0 : 1; | ||
| 232 | unsigned int strdma1 : 1; | ||
| 233 | unsigned int strdma2 : 1; | ||
| 234 | unsigned int strdma3 : 1; | ||
| 235 | unsigned int strdma5 : 1; | ||
| 236 | unsigned int vin : 1; | ||
| 237 | unsigned int vout : 1; | ||
| 238 | unsigned int jpeg : 1; | ||
| 239 | unsigned int h264 : 1; | ||
| 240 | unsigned int histo : 1; | ||
| 241 | unsigned int ccd : 1; | ||
| 242 | } reg_intr_vect_rw_xmask0; | ||
| 243 | #define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0 | ||
| 244 | #define REG_RD_ADDR_intr_vect_rw_xmask0 24 | ||
| 245 | #define REG_WR_ADDR_intr_vect_rw_xmask0 24 | ||
| 246 | #define REG_RD_ADDR_intr_vect_rw_xmask 24 | ||
| 247 | #define REG_WR_ADDR_intr_vect_rw_xmask 24 | ||
| 248 | |||
| 249 | /* Register rw_mask1, scope intr_vect, type rw */ | ||
| 250 | typedef struct { | ||
| 251 | unsigned int eth : 1; | ||
| 252 | unsigned int memarb_bar : 1; | ||
| 253 | unsigned int memarb_foo : 1; | ||
| 254 | unsigned int pio : 1; | ||
| 255 | unsigned int sclr : 1; | ||
| 256 | unsigned int sclr_fifo : 1; | ||
| 257 | unsigned int dummy1 : 26; | ||
| 258 | } reg_intr_vect_rw_mask1; | ||
| 259 | #define REG_RD_ADDR_intr_vect_rw_mask1 4 | ||
| 260 | #define REG_WR_ADDR_intr_vect_rw_mask1 4 | ||
| 261 | |||
| 262 | /* Register r_vect1, scope intr_vect, type r */ | ||
| 263 | typedef struct { | ||
| 264 | unsigned int eth : 1; | ||
| 265 | unsigned int memarb_bar : 1; | ||
| 266 | unsigned int memarb_foo : 1; | ||
| 267 | unsigned int pio : 1; | ||
| 268 | unsigned int sclr : 1; | ||
| 269 | unsigned int sclr_fifo : 1; | ||
| 270 | unsigned int dummy1 : 26; | ||
| 271 | } reg_intr_vect_r_vect1; | ||
| 272 | #define REG_RD_ADDR_intr_vect_r_vect1 12 | ||
| 273 | |||
| 274 | /* Register r_masked_vect1, scope intr_vect, type r */ | ||
| 275 | typedef struct { | ||
| 276 | unsigned int eth : 1; | ||
| 277 | unsigned int memarb_bar : 1; | ||
| 278 | unsigned int memarb_foo : 1; | ||
| 279 | unsigned int pio : 1; | ||
| 280 | unsigned int sclr : 1; | ||
| 281 | unsigned int sclr_fifo : 1; | ||
| 282 | unsigned int dummy1 : 26; | ||
| 283 | } reg_intr_vect_r_masked_vect1; | ||
| 284 | #define REG_RD_ADDR_intr_vect_r_masked_vect1 20 | ||
| 285 | |||
| 286 | /* Register rw_xmask1, scope intr_vect, type rw */ | ||
| 287 | typedef struct { | ||
| 288 | unsigned int eth : 1; | ||
| 289 | unsigned int memarb_bar : 1; | ||
| 290 | unsigned int memarb_foo : 1; | ||
| 291 | unsigned int pio : 1; | ||
| 292 | unsigned int sclr : 1; | ||
| 293 | unsigned int sclr_fifo : 1; | ||
| 294 | unsigned int dummy1 : 26; | ||
| 295 | } reg_intr_vect_rw_xmask1; | ||
| 296 | #define REG_RD_ADDR_intr_vect_rw_xmask1 28 | ||
| 297 | #define REG_WR_ADDR_intr_vect_rw_xmask1 28 | ||
| 298 | |||
| 299 | /* Register rw_xmask_ctrl, scope intr_vect, type rw */ | ||
| 300 | typedef struct { | ||
| 301 | unsigned int en : 1; | ||
| 302 | unsigned int dummy1 : 31; | ||
| 303 | } reg_intr_vect_rw_xmask_ctrl; | ||
| 304 | #define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32 | ||
| 305 | #define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32 | ||
| 306 | |||
| 307 | /* Register r_nmi, scope intr_vect, type r */ | ||
| 308 | typedef struct { | ||
| 309 | unsigned int watchdog0 : 1; | ||
| 310 | unsigned int watchdog1 : 1; | ||
| 311 | unsigned int dummy1 : 30; | ||
| 312 | } reg_intr_vect_r_nmi; | ||
| 313 | #define REG_RD_ADDR_intr_vect_r_nmi 64 | ||
| 314 | |||
| 315 | /* Register r_guru, scope intr_vect, type r */ | ||
| 316 | typedef struct { | ||
| 317 | unsigned int jtag : 1; | ||
| 318 | unsigned int dummy1 : 31; | ||
| 319 | } reg_intr_vect_r_guru; | ||
| 320 | #define REG_RD_ADDR_intr_vect_r_guru 68 | ||
| 321 | |||
| 322 | |||
| 323 | /* Register rw_ipi, scope intr_vect, type rw */ | ||
| 324 | typedef struct | ||
| 325 | { | ||
| 326 | unsigned int vector; | ||
| 327 | } reg_intr_vect_rw_ipi; | ||
| 328 | #define REG_RD_ADDR_intr_vect_rw_ipi 72 | ||
| 329 | #define REG_WR_ADDR_intr_vect_rw_ipi 72 | ||
| 330 | |||
| 331 | /* Constants */ | ||
| 332 | enum { | ||
| 333 | regk_intr_vect_no = 0x00000000, | ||
| 334 | regk_intr_vect_rw_mask0_default = 0x00000000, | ||
| 335 | regk_intr_vect_rw_mask1_default = 0x00000000, | ||
| 336 | regk_intr_vect_rw_xmask0_default = 0x00000000, | ||
| 337 | regk_intr_vect_rw_xmask1_default = 0x00000000, | ||
| 338 | regk_intr_vect_rw_xmask_ctrl_default = 0x00000000, | ||
| 339 | regk_intr_vect_yes = 0x00000001 | ||
| 340 | }; | ||
| 341 | #endif /* __intr_vect_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index d75a74e90458..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* Autogenerated Changes here will be lost! | ||
| 2 | * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg | ||
| 3 | */ | ||
| 4 | #define iop_version 0 | ||
| 5 | #define iop_fifo_in_extra 64 | ||
| 6 | #define iop_fifo_out_extra 128 | ||
| 7 | #define iop_trigger_grp0 192 | ||
| 8 | #define iop_trigger_grp1 256 | ||
| 9 | #define iop_trigger_grp2 320 | ||
| 10 | #define iop_trigger_grp3 384 | ||
| 11 | #define iop_trigger_grp4 448 | ||
| 12 | #define iop_trigger_grp5 512 | ||
| 13 | #define iop_trigger_grp6 576 | ||
| 14 | #define iop_trigger_grp7 640 | ||
| 15 | #define iop_crc_par 768 | ||
| 16 | #define iop_dmc_in 896 | ||
| 17 | #define iop_dmc_out 1024 | ||
| 18 | #define iop_fifo_in 1152 | ||
| 19 | #define iop_fifo_out 1280 | ||
| 20 | #define iop_scrc_in 1408 | ||
| 21 | #define iop_scrc_out 1536 | ||
| 22 | #define iop_timer_grp0 1664 | ||
| 23 | #define iop_timer_grp1 1792 | ||
| 24 | #define iop_sap_in 2048 | ||
| 25 | #define iop_sap_out 2304 | ||
| 26 | #define iop_spu 2560 | ||
| 27 | #define iop_sw_cfg 2816 | ||
| 28 | #define iop_sw_cpu 3072 | ||
| 29 | #define iop_sw_mpu 3328 | ||
| 30 | #define iop_sw_spu 3584 | ||
| 31 | #define iop_mpu 4096 | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index 7f90b5a0460d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null | |||
| @@ -1,109 +0,0 @@ | |||
| 1 | #ifndef __iop_sap_in_defs_asm_h | ||
| 2 | #define __iop_sap_in_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sap_in.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #define STRIDE_iop_sap_in_rw_bus_byte 4 | ||
| 54 | /* Register rw_bus_byte, scope iop_sap_in, type rw */ | ||
| 55 | #define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 | ||
| 56 | #define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 | ||
| 57 | #define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 | ||
| 58 | #define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 | ||
| 59 | #define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 | ||
| 60 | #define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 | ||
| 61 | #define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 | ||
| 62 | #define reg_iop_sap_in_rw_bus_byte___delay___width 2 | ||
| 63 | #define reg_iop_sap_in_rw_bus_byte_offset 0 | ||
| 64 | |||
| 65 | #define STRIDE_iop_sap_in_rw_gio 4 | ||
| 66 | /* Register rw_gio, scope iop_sap_in, type rw */ | ||
| 67 | #define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 | ||
| 68 | #define reg_iop_sap_in_rw_gio___sync_sel___width 2 | ||
| 69 | #define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 | ||
| 70 | #define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 | ||
| 71 | #define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 | ||
| 72 | #define reg_iop_sap_in_rw_gio___sync_edge___width 2 | ||
| 73 | #define reg_iop_sap_in_rw_gio___delay___lsb 7 | ||
| 74 | #define reg_iop_sap_in_rw_gio___delay___width 2 | ||
| 75 | #define reg_iop_sap_in_rw_gio___logic___lsb 9 | ||
| 76 | #define reg_iop_sap_in_rw_gio___logic___width 2 | ||
| 77 | #define reg_iop_sap_in_rw_gio_offset 16 | ||
| 78 | |||
| 79 | |||
| 80 | /* Constants */ | ||
| 81 | #define regk_iop_sap_in_and 0x00000002 | ||
| 82 | #define regk_iop_sap_in_ext_clk200 0x00000003 | ||
| 83 | #define regk_iop_sap_in_gio0 0x00000000 | ||
| 84 | #define regk_iop_sap_in_gio12 0x00000003 | ||
| 85 | #define regk_iop_sap_in_gio16 0x00000004 | ||
| 86 | #define regk_iop_sap_in_gio20 0x00000005 | ||
| 87 | #define regk_iop_sap_in_gio24 0x00000006 | ||
| 88 | #define regk_iop_sap_in_gio28 0x00000007 | ||
| 89 | #define regk_iop_sap_in_gio4 0x00000001 | ||
| 90 | #define regk_iop_sap_in_gio8 0x00000002 | ||
| 91 | #define regk_iop_sap_in_inv 0x00000001 | ||
| 92 | #define regk_iop_sap_in_neg 0x00000002 | ||
| 93 | #define regk_iop_sap_in_no 0x00000000 | ||
| 94 | #define regk_iop_sap_in_no_del_ext_clk200 0x00000002 | ||
| 95 | #define regk_iop_sap_in_none 0x00000000 | ||
| 96 | #define regk_iop_sap_in_one 0x00000001 | ||
| 97 | #define regk_iop_sap_in_or 0x00000003 | ||
| 98 | #define regk_iop_sap_in_pos 0x00000001 | ||
| 99 | #define regk_iop_sap_in_pos_neg 0x00000003 | ||
| 100 | #define regk_iop_sap_in_rw_bus_byte_default 0x00000000 | ||
| 101 | #define regk_iop_sap_in_rw_bus_byte_size 0x00000004 | ||
| 102 | #define regk_iop_sap_in_rw_gio_default 0x00000000 | ||
| 103 | #define regk_iop_sap_in_rw_gio_size 0x00000020 | ||
| 104 | #define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 | ||
| 105 | #define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 | ||
| 106 | #define regk_iop_sap_in_tmr_clk200 0x00000001 | ||
| 107 | #define regk_iop_sap_in_two 0x00000002 | ||
| 108 | #define regk_iop_sap_in_two_clk200 0x00000000 | ||
| 109 | #endif /* __iop_sap_in_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 399bd656406b..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null | |||
| @@ -1,276 +0,0 @@ | |||
| 1 | #ifndef __iop_sap_out_defs_asm_h | ||
| 2 | #define __iop_sap_out_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sap_out.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
| 54 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 | ||
| 55 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 | ||
| 56 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 | ||
| 57 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 | ||
| 58 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 | ||
| 59 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 | ||
| 60 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 | ||
| 61 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 | ||
| 62 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 | ||
| 63 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 | ||
| 64 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 | ||
| 65 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 | ||
| 66 | #define reg_iop_sap_out_rw_gen_gated_offset 0 | ||
| 67 | |||
| 68 | /* Register rw_bus, scope iop_sap_out, type rw */ | ||
| 69 | #define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 | ||
| 70 | #define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 | ||
| 71 | #define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 | ||
| 72 | #define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 | ||
| 73 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 | ||
| 74 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 | ||
| 75 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 | ||
| 76 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 | ||
| 77 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 | ||
| 78 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 | ||
| 79 | #define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 | ||
| 80 | #define reg_iop_sap_out_rw_bus___byte0_delay___width 1 | ||
| 81 | #define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 | ||
| 82 | #define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 | ||
| 83 | #define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 | ||
| 84 | #define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 | ||
| 85 | #define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 | ||
| 86 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 | ||
| 87 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 | ||
| 88 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 | ||
| 89 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 | ||
| 90 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 | ||
| 91 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 | ||
| 92 | #define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 | ||
| 93 | #define reg_iop_sap_out_rw_bus___byte1_delay___width 1 | ||
| 94 | #define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 | ||
| 95 | #define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 | ||
| 96 | #define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 | ||
| 97 | #define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 | ||
| 98 | #define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 | ||
| 99 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 | ||
| 100 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 | ||
| 101 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 | ||
| 102 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 | ||
| 103 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 | ||
| 104 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 | ||
| 105 | #define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 | ||
| 106 | #define reg_iop_sap_out_rw_bus___byte2_delay___width 1 | ||
| 107 | #define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 | ||
| 108 | #define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 | ||
| 109 | #define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 | ||
| 110 | #define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 | ||
| 111 | #define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 | ||
| 112 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 | ||
| 113 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 | ||
| 114 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 | ||
| 115 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 | ||
| 116 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 | ||
| 117 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 | ||
| 118 | #define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 | ||
| 119 | #define reg_iop_sap_out_rw_bus___byte3_delay___width 1 | ||
| 120 | #define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 | ||
| 121 | #define reg_iop_sap_out_rw_bus_offset 4 | ||
| 122 | |||
| 123 | /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ | ||
| 124 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 | ||
| 125 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 | ||
| 126 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 | ||
| 127 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 | ||
| 128 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 | ||
| 129 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 | ||
| 130 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 | ||
| 131 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 | ||
| 132 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 | ||
| 133 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 | ||
| 134 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 | ||
| 135 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 | ||
| 136 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 | ||
| 137 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 | ||
| 138 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 | ||
| 139 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 | ||
| 140 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 | ||
| 141 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 | ||
| 142 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 | ||
| 143 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 | ||
| 144 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 | ||
| 145 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 | ||
| 146 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 | ||
| 147 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 | ||
| 148 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 | ||
| 149 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 | ||
| 150 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 | ||
| 151 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 | ||
| 152 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 | ||
| 153 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 | ||
| 154 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 | ||
| 155 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 | ||
| 156 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 | ||
| 157 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 | ||
| 158 | #define reg_iop_sap_out_rw_bus_lo_oe_offset 8 | ||
| 159 | |||
| 160 | /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ | ||
| 161 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 | ||
| 162 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 | ||
| 163 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 | ||
| 164 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 | ||
| 165 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 | ||
| 166 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 | ||
| 167 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 | ||
| 168 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 | ||
| 169 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 | ||
| 170 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 | ||
| 171 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 | ||
| 172 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 | ||
| 173 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 | ||
| 174 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 | ||
| 175 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 | ||
| 176 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 | ||
| 177 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 | ||
| 178 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 | ||
| 179 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 | ||
| 180 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 | ||
| 181 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 | ||
| 182 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 | ||
| 183 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 | ||
| 184 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 | ||
| 185 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 | ||
| 186 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 | ||
| 187 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 | ||
| 188 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 | ||
| 189 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 | ||
| 190 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 | ||
| 191 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 | ||
| 192 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 | ||
| 193 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 | ||
| 194 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 | ||
| 195 | #define reg_iop_sap_out_rw_bus_hi_oe_offset 12 | ||
| 196 | |||
| 197 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
| 198 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
| 199 | #define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 | ||
| 200 | #define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 | ||
| 201 | #define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 | ||
| 202 | #define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 | ||
| 203 | #define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 | ||
| 204 | #define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 | ||
| 205 | #define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 | ||
| 206 | #define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 | ||
| 207 | #define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 | ||
| 208 | #define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 | ||
| 209 | #define reg_iop_sap_out_rw_gio___out_delay___lsb 7 | ||
| 210 | #define reg_iop_sap_out_rw_gio___out_delay___width 1 | ||
| 211 | #define reg_iop_sap_out_rw_gio___out_delay___bit 7 | ||
| 212 | #define reg_iop_sap_out_rw_gio___out_logic___lsb 8 | ||
| 213 | #define reg_iop_sap_out_rw_gio___out_logic___width 2 | ||
| 214 | #define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 | ||
| 215 | #define reg_iop_sap_out_rw_gio___out_logic_src___width 2 | ||
| 216 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 | ||
| 217 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 | ||
| 218 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 | ||
| 219 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 | ||
| 220 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 | ||
| 221 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 | ||
| 222 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 | ||
| 223 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 | ||
| 224 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 | ||
| 225 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 | ||
| 226 | #define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 | ||
| 227 | #define reg_iop_sap_out_rw_gio___oe_delay___width 1 | ||
| 228 | #define reg_iop_sap_out_rw_gio___oe_delay___bit 19 | ||
| 229 | #define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 | ||
| 230 | #define reg_iop_sap_out_rw_gio___oe_logic___width 2 | ||
| 231 | #define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 | ||
| 232 | #define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 | ||
| 233 | #define reg_iop_sap_out_rw_gio_offset 16 | ||
| 234 | |||
| 235 | |||
| 236 | /* Constants */ | ||
| 237 | #define regk_iop_sap_out_always 0x00000001 | ||
| 238 | #define regk_iop_sap_out_and 0x00000002 | ||
| 239 | #define regk_iop_sap_out_clk0 0x00000000 | ||
| 240 | #define regk_iop_sap_out_clk1 0x00000001 | ||
| 241 | #define regk_iop_sap_out_clk12 0x00000004 | ||
| 242 | #define regk_iop_sap_out_clk200 0x00000000 | ||
| 243 | #define regk_iop_sap_out_ext 0x00000002 | ||
| 244 | #define regk_iop_sap_out_gated 0x00000003 | ||
| 245 | #define regk_iop_sap_out_gio0 0x00000000 | ||
| 246 | #define regk_iop_sap_out_gio1 0x00000000 | ||
| 247 | #define regk_iop_sap_out_gio16 0x00000002 | ||
| 248 | #define regk_iop_sap_out_gio17 0x00000002 | ||
| 249 | #define regk_iop_sap_out_gio24 0x00000003 | ||
| 250 | #define regk_iop_sap_out_gio25 0x00000003 | ||
| 251 | #define regk_iop_sap_out_gio8 0x00000001 | ||
| 252 | #define regk_iop_sap_out_gio9 0x00000001 | ||
| 253 | #define regk_iop_sap_out_gio_out10 0x00000005 | ||
| 254 | #define regk_iop_sap_out_gio_out18 0x00000006 | ||
| 255 | #define regk_iop_sap_out_gio_out2 0x00000004 | ||
| 256 | #define regk_iop_sap_out_gio_out26 0x00000007 | ||
| 257 | #define regk_iop_sap_out_inv 0x00000001 | ||
| 258 | #define regk_iop_sap_out_nand 0x00000003 | ||
| 259 | #define regk_iop_sap_out_no 0x00000000 | ||
| 260 | #define regk_iop_sap_out_none 0x00000000 | ||
| 261 | #define regk_iop_sap_out_one 0x00000001 | ||
| 262 | #define regk_iop_sap_out_rw_bus_default 0x00000000 | ||
| 263 | #define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 | ||
| 264 | #define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 | ||
| 265 | #define regk_iop_sap_out_rw_gen_gated_default 0x00000000 | ||
| 266 | #define regk_iop_sap_out_rw_gio_default 0x00000000 | ||
| 267 | #define regk_iop_sap_out_rw_gio_size 0x00000020 | ||
| 268 | #define regk_iop_sap_out_spu_gio6 0x00000002 | ||
| 269 | #define regk_iop_sap_out_spu_gio7 0x00000003 | ||
| 270 | #define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 | ||
| 271 | #define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 | ||
| 272 | #define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 | ||
| 273 | #define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 | ||
| 274 | #define regk_iop_sap_out_tmr200 0x00000001 | ||
| 275 | #define regk_iop_sap_out_yes 0x00000001 | ||
| 276 | #endif /* __iop_sap_out_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index 3b3949b51a66..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null | |||
| @@ -1,739 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_cfg_defs_asm_h | ||
| 2 | #define __iop_sw_cfg_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_cfg.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ | ||
| 54 | #define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 | ||
| 55 | #define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 | ||
| 56 | #define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 | ||
| 57 | |||
| 58 | /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ | ||
| 59 | #define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 | ||
| 60 | #define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 | ||
| 61 | #define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 | ||
| 62 | |||
| 63 | /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ | ||
| 64 | #define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 | ||
| 65 | #define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 | ||
| 66 | #define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 | ||
| 67 | |||
| 68 | /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ | ||
| 69 | #define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 | ||
| 70 | #define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 | ||
| 71 | #define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 | ||
| 72 | |||
| 73 | /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 74 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 | ||
| 75 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 | ||
| 76 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 | ||
| 77 | |||
| 78 | /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ | ||
| 79 | #define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 | ||
| 80 | #define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 | ||
| 81 | #define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 | ||
| 82 | |||
| 83 | /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 84 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 | ||
| 85 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 | ||
| 86 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 | ||
| 87 | |||
| 88 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | ||
| 89 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 | ||
| 90 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 | ||
| 91 | #define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 | ||
| 92 | |||
| 93 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | ||
| 94 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 | ||
| 95 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 | ||
| 96 | #define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 | ||
| 97 | |||
| 98 | /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ | ||
| 99 | #define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 | ||
| 100 | #define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 | ||
| 101 | #define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 | ||
| 102 | |||
| 103 | /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ | ||
| 104 | #define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 | ||
| 105 | #define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 | ||
| 106 | #define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 | ||
| 107 | |||
| 108 | /* Register rw_spu_owner, scope iop_sw_cfg, type rw */ | ||
| 109 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 | ||
| 110 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 | ||
| 111 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 | ||
| 112 | #define reg_iop_sw_cfg_rw_spu_owner_offset 44 | ||
| 113 | |||
| 114 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 115 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 | ||
| 116 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 | ||
| 117 | #define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 | ||
| 118 | |||
| 119 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 120 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 | ||
| 121 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 | ||
| 122 | #define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 | ||
| 123 | |||
| 124 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 125 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 | ||
| 126 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 | ||
| 127 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 | ||
| 128 | |||
| 129 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 130 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 | ||
| 131 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 | ||
| 132 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 | ||
| 133 | |||
| 134 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | ||
| 135 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 | ||
| 136 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 | ||
| 137 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 | ||
| 138 | |||
| 139 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | ||
| 140 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 | ||
| 141 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 | ||
| 142 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 | ||
| 143 | |||
| 144 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | ||
| 145 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 | ||
| 146 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 | ||
| 147 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 | ||
| 148 | |||
| 149 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | ||
| 150 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 | ||
| 151 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 | ||
| 152 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 | ||
| 153 | |||
| 154 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | ||
| 155 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 | ||
| 156 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 | ||
| 157 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 | ||
| 158 | |||
| 159 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | ||
| 160 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 | ||
| 161 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 | ||
| 162 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 | ||
| 163 | |||
| 164 | /* Register rw_bus_mask, scope iop_sw_cfg, type rw */ | ||
| 165 | #define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 | ||
| 166 | #define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 | ||
| 167 | #define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 | ||
| 168 | #define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 | ||
| 169 | #define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 | ||
| 170 | #define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 | ||
| 171 | #define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 | ||
| 172 | #define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 | ||
| 173 | #define reg_iop_sw_cfg_rw_bus_mask_offset 88 | ||
| 174 | |||
| 175 | /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 176 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 | ||
| 177 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 | ||
| 178 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 | ||
| 179 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 | ||
| 180 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 | ||
| 181 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 | ||
| 182 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 | ||
| 183 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 | ||
| 184 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 | ||
| 185 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 | ||
| 186 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 | ||
| 187 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 | ||
| 188 | #define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 | ||
| 189 | |||
| 190 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | ||
| 191 | #define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 | ||
| 192 | #define reg_iop_sw_cfg_rw_gio_mask___val___width 32 | ||
| 193 | #define reg_iop_sw_cfg_rw_gio_mask_offset 96 | ||
| 194 | |||
| 195 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 196 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 | ||
| 197 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 | ||
| 198 | #define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 | ||
| 199 | |||
| 200 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | ||
| 201 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 | ||
| 202 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 | ||
| 203 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 | ||
| 204 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 | ||
| 205 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 | ||
| 206 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 | ||
| 207 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 | ||
| 208 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 | ||
| 209 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 | ||
| 210 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 | ||
| 211 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 | ||
| 212 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 | ||
| 213 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 | ||
| 214 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 | ||
| 215 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 | ||
| 216 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 | ||
| 217 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 | ||
| 218 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 | ||
| 219 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 | ||
| 220 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 | ||
| 221 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 | ||
| 222 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 | ||
| 223 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 | ||
| 224 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 | ||
| 225 | #define reg_iop_sw_cfg_rw_pinmapping_offset 104 | ||
| 226 | |||
| 227 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | ||
| 228 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 | ||
| 229 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 | ||
| 230 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 | ||
| 231 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 | ||
| 232 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 | ||
| 233 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 | ||
| 234 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 | ||
| 235 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 | ||
| 236 | #define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 | ||
| 237 | |||
| 238 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 239 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 | ||
| 240 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 | ||
| 241 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 | ||
| 242 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 | ||
| 243 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 | ||
| 244 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 | ||
| 245 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 | ||
| 246 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 | ||
| 247 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 | ||
| 248 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 | ||
| 249 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 | ||
| 250 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 | ||
| 251 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 | ||
| 252 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 | ||
| 253 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 | ||
| 254 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 | ||
| 255 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 | ||
| 256 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 | ||
| 257 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 | ||
| 258 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 | ||
| 259 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 | ||
| 260 | |||
| 261 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 262 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 | ||
| 263 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 | ||
| 264 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 | ||
| 265 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 | ||
| 266 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 | ||
| 267 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 | ||
| 268 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 | ||
| 269 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 | ||
| 270 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 | ||
| 271 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 | ||
| 272 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 | ||
| 273 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 | ||
| 274 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 | ||
| 275 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 | ||
| 276 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 | ||
| 277 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 | ||
| 278 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 | ||
| 279 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 | ||
| 280 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 | ||
| 281 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 | ||
| 282 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 | ||
| 283 | |||
| 284 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
| 285 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 | ||
| 286 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 | ||
| 287 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 | ||
| 288 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 | ||
| 289 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 | ||
| 290 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 | ||
| 291 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 | ||
| 292 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 | ||
| 293 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 | ||
| 294 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 | ||
| 295 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 | ||
| 296 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 | ||
| 297 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 | ||
| 298 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 | ||
| 299 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 | ||
| 300 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 | ||
| 301 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 | ||
| 302 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 | ||
| 303 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 | ||
| 304 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 | ||
| 305 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 | ||
| 306 | |||
| 307 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
| 308 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 | ||
| 309 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 | ||
| 310 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 | ||
| 311 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 | ||
| 312 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 | ||
| 313 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 | ||
| 314 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 | ||
| 315 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 | ||
| 316 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 | ||
| 317 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 | ||
| 318 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 | ||
| 319 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 | ||
| 320 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 | ||
| 321 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 | ||
| 322 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 | ||
| 323 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 | ||
| 324 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 | ||
| 325 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 | ||
| 326 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 | ||
| 327 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 | ||
| 328 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 | ||
| 329 | |||
| 330 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | ||
| 331 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 | ||
| 332 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 | ||
| 333 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 | ||
| 334 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 | ||
| 335 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 | ||
| 336 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 | ||
| 337 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 | ||
| 338 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 | ||
| 339 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 | ||
| 340 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 | ||
| 341 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 | ||
| 342 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 | ||
| 343 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 | ||
| 344 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 | ||
| 345 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 | ||
| 346 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 | ||
| 347 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 | ||
| 348 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 | ||
| 349 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 | ||
| 350 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 | ||
| 351 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 | ||
| 352 | |||
| 353 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | ||
| 354 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 | ||
| 355 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 | ||
| 356 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 | ||
| 357 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 | ||
| 358 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 | ||
| 359 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 | ||
| 360 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 | ||
| 361 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 | ||
| 362 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 | ||
| 363 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 | ||
| 364 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 | ||
| 365 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 | ||
| 366 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 | ||
| 367 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 | ||
| 368 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 | ||
| 369 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 | ||
| 370 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 | ||
| 371 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 | ||
| 372 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 | ||
| 373 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 | ||
| 374 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 | ||
| 375 | |||
| 376 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | ||
| 377 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 | ||
| 378 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 | ||
| 379 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 | ||
| 380 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 | ||
| 381 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 | ||
| 382 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 | ||
| 383 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 | ||
| 384 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 | ||
| 385 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 | ||
| 386 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 | ||
| 387 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 | ||
| 388 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 | ||
| 389 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 | ||
| 390 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 | ||
| 391 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 | ||
| 392 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 | ||
| 393 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 | ||
| 394 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 | ||
| 395 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 | ||
| 396 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 | ||
| 397 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 | ||
| 398 | |||
| 399 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | ||
| 400 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 | ||
| 401 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 | ||
| 402 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 | ||
| 403 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 | ||
| 404 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 | ||
| 405 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 | ||
| 406 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 | ||
| 407 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 | ||
| 408 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 | ||
| 409 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 | ||
| 410 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 | ||
| 411 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 | ||
| 412 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 | ||
| 413 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 | ||
| 414 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 | ||
| 415 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 | ||
| 416 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 | ||
| 417 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 | ||
| 418 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 | ||
| 419 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 | ||
| 420 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 | ||
| 421 | |||
| 422 | /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ | ||
| 423 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 | ||
| 424 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 | ||
| 425 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 | ||
| 426 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 | ||
| 427 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 | ||
| 428 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 | ||
| 429 | #define reg_iop_sw_cfg_rw_spu_cfg_offset 144 | ||
| 430 | |||
| 431 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 432 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 | ||
| 433 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 | ||
| 434 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 | ||
| 435 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 | ||
| 436 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 | ||
| 437 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 | ||
| 438 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 | ||
| 439 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 | ||
| 440 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 | ||
| 441 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 | ||
| 442 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 | ||
| 443 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 | ||
| 444 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 | ||
| 445 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 | ||
| 446 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 | ||
| 447 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 | ||
| 448 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 | ||
| 449 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 | ||
| 450 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 | ||
| 451 | |||
| 452 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 453 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 | ||
| 454 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 | ||
| 455 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 | ||
| 456 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 | ||
| 457 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 | ||
| 458 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 | ||
| 459 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 | ||
| 460 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 | ||
| 461 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 | ||
| 462 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 | ||
| 463 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 | ||
| 464 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 | ||
| 465 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 | ||
| 466 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 | ||
| 467 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 | ||
| 468 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 | ||
| 469 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 | ||
| 470 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 | ||
| 471 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 | ||
| 472 | |||
| 473 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | ||
| 474 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 | ||
| 475 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 | ||
| 476 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 | ||
| 477 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 | ||
| 478 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 | ||
| 479 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 | ||
| 480 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 | ||
| 481 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 | ||
| 482 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 | ||
| 483 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 | ||
| 484 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 | ||
| 485 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 | ||
| 486 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 | ||
| 487 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 | ||
| 488 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 | ||
| 489 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 | ||
| 490 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 | ||
| 491 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 | ||
| 492 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 | ||
| 493 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 | ||
| 494 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 | ||
| 495 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 | ||
| 496 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 | ||
| 497 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 | ||
| 498 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 | ||
| 499 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 | ||
| 500 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 | ||
| 501 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 | ||
| 502 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 | ||
| 503 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 | ||
| 504 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 | ||
| 505 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 | ||
| 506 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 | ||
| 507 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 | ||
| 508 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 | ||
| 509 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 | ||
| 510 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 | ||
| 511 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 | ||
| 512 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 | ||
| 513 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 | ||
| 514 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 | ||
| 515 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 | ||
| 516 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 | ||
| 517 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 | ||
| 518 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 | ||
| 519 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 | ||
| 520 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 | ||
| 521 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 | ||
| 522 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 | ||
| 523 | |||
| 524 | /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 525 | #define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 | ||
| 526 | #define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 | ||
| 527 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 | ||
| 528 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 | ||
| 529 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 | ||
| 530 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 | ||
| 531 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 | ||
| 532 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 | ||
| 533 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 | ||
| 534 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 | ||
| 535 | #define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 | ||
| 536 | |||
| 537 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 538 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 | ||
| 539 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 | ||
| 540 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 | ||
| 541 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 | ||
| 542 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 | ||
| 543 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 | ||
| 544 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 | ||
| 545 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 | ||
| 546 | #define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 | ||
| 547 | |||
| 548 | |||
| 549 | /* Constants */ | ||
| 550 | #define regk_iop_sw_cfg_a 0x00000001 | ||
| 551 | #define regk_iop_sw_cfg_b 0x00000002 | ||
| 552 | #define regk_iop_sw_cfg_bus 0x00000000 | ||
| 553 | #define regk_iop_sw_cfg_bus_rot16 0x00000002 | ||
| 554 | #define regk_iop_sw_cfg_bus_rot24 0x00000003 | ||
| 555 | #define regk_iop_sw_cfg_bus_rot8 0x00000001 | ||
| 556 | #define regk_iop_sw_cfg_clk12 0x00000000 | ||
| 557 | #define regk_iop_sw_cfg_cpu 0x00000000 | ||
| 558 | #define regk_iop_sw_cfg_gated_clk0 0x0000000e | ||
| 559 | #define regk_iop_sw_cfg_gated_clk1 0x0000000f | ||
| 560 | #define regk_iop_sw_cfg_gio0 0x00000004 | ||
| 561 | #define regk_iop_sw_cfg_gio1 0x00000001 | ||
| 562 | #define regk_iop_sw_cfg_gio2 0x00000005 | ||
| 563 | #define regk_iop_sw_cfg_gio3 0x00000002 | ||
| 564 | #define regk_iop_sw_cfg_gio4 0x00000006 | ||
| 565 | #define regk_iop_sw_cfg_gio5 0x00000003 | ||
| 566 | #define regk_iop_sw_cfg_gio6 0x00000007 | ||
| 567 | #define regk_iop_sw_cfg_gio7 0x00000004 | ||
| 568 | #define regk_iop_sw_cfg_gio_in18 0x00000002 | ||
| 569 | #define regk_iop_sw_cfg_gio_in19 0x00000003 | ||
| 570 | #define regk_iop_sw_cfg_gio_in20 0x00000004 | ||
| 571 | #define regk_iop_sw_cfg_gio_in21 0x00000005 | ||
| 572 | #define regk_iop_sw_cfg_gio_in26 0x00000006 | ||
| 573 | #define regk_iop_sw_cfg_gio_in27 0x00000007 | ||
| 574 | #define regk_iop_sw_cfg_gio_in4 0x00000000 | ||
| 575 | #define regk_iop_sw_cfg_gio_in5 0x00000001 | ||
| 576 | #define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 | ||
| 577 | #define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 | ||
| 578 | #define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 | ||
| 579 | #define regk_iop_sw_cfg_mpu 0x00000001 | ||
| 580 | #define regk_iop_sw_cfg_none 0x00000000 | ||
| 581 | #define regk_iop_sw_cfg_pdp_out 0x00000001 | ||
| 582 | #define regk_iop_sw_cfg_pdp_out_hi 0x00000001 | ||
| 583 | #define regk_iop_sw_cfg_pdp_out_lo 0x00000000 | ||
| 584 | #define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 | ||
| 585 | #define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 | ||
| 586 | #define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 | ||
| 587 | #define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 | ||
| 588 | #define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 | ||
| 589 | #define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 | ||
| 590 | #define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 | ||
| 591 | #define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 | ||
| 592 | #define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 | ||
| 593 | #define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 | ||
| 594 | #define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 | ||
| 595 | #define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 | ||
| 596 | #define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 | ||
| 597 | #define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 | ||
| 598 | #define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 | ||
| 599 | #define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 | ||
| 600 | #define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 | ||
| 601 | #define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 | ||
| 602 | #define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 | ||
| 603 | #define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 | ||
| 604 | #define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 | ||
| 605 | #define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 | ||
| 606 | #define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 | ||
| 607 | #define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 | ||
| 608 | #define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 | ||
| 609 | #define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 | ||
| 610 | #define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 | ||
| 611 | #define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 | ||
| 612 | #define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 | ||
| 613 | #define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 | ||
| 614 | #define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 | ||
| 615 | #define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 | ||
| 616 | #define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 | ||
| 617 | #define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 | ||
| 618 | #define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 | ||
| 619 | #define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 | ||
| 620 | #define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 | ||
| 621 | #define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 | ||
| 622 | #define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 | ||
| 623 | #define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 | ||
| 624 | #define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 | ||
| 625 | #define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 | ||
| 626 | #define regk_iop_sw_cfg_sdp_out 0x00000004 | ||
| 627 | #define regk_iop_sw_cfg_size16 0x00000002 | ||
| 628 | #define regk_iop_sw_cfg_size24 0x00000003 | ||
| 629 | #define regk_iop_sw_cfg_size32 0x00000004 | ||
| 630 | #define regk_iop_sw_cfg_size8 0x00000001 | ||
| 631 | #define regk_iop_sw_cfg_spu 0x00000002 | ||
| 632 | #define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 | ||
| 633 | #define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 | ||
| 634 | #define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 | ||
| 635 | #define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 | ||
| 636 | #define regk_iop_sw_cfg_spu_g0 0x00000007 | ||
| 637 | #define regk_iop_sw_cfg_spu_g1 0x00000007 | ||
| 638 | #define regk_iop_sw_cfg_spu_g2 0x00000007 | ||
| 639 | #define regk_iop_sw_cfg_spu_g3 0x00000007 | ||
| 640 | #define regk_iop_sw_cfg_spu_g4 0x00000007 | ||
| 641 | #define regk_iop_sw_cfg_spu_g5 0x00000007 | ||
| 642 | #define regk_iop_sw_cfg_spu_g6 0x00000007 | ||
| 643 | #define regk_iop_sw_cfg_spu_g7 0x00000007 | ||
| 644 | #define regk_iop_sw_cfg_spu_gio0 0x00000000 | ||
| 645 | #define regk_iop_sw_cfg_spu_gio1 0x00000001 | ||
| 646 | #define regk_iop_sw_cfg_spu_gio5 0x00000005 | ||
| 647 | #define regk_iop_sw_cfg_spu_gio6 0x00000006 | ||
| 648 | #define regk_iop_sw_cfg_spu_gio7 0x00000007 | ||
| 649 | #define regk_iop_sw_cfg_spu_gio_out0 0x00000008 | ||
| 650 | #define regk_iop_sw_cfg_spu_gio_out1 0x00000009 | ||
| 651 | #define regk_iop_sw_cfg_spu_gio_out2 0x0000000a | ||
| 652 | #define regk_iop_sw_cfg_spu_gio_out3 0x0000000b | ||
| 653 | #define regk_iop_sw_cfg_spu_gio_out4 0x0000000c | ||
| 654 | #define regk_iop_sw_cfg_spu_gio_out5 0x0000000d | ||
| 655 | #define regk_iop_sw_cfg_spu_gio_out6 0x0000000e | ||
| 656 | #define regk_iop_sw_cfg_spu_gio_out7 0x0000000f | ||
| 657 | #define regk_iop_sw_cfg_spu_gioout0 0x00000000 | ||
| 658 | #define regk_iop_sw_cfg_spu_gioout1 0x00000000 | ||
| 659 | #define regk_iop_sw_cfg_spu_gioout10 0x00000007 | ||
| 660 | #define regk_iop_sw_cfg_spu_gioout11 0x00000007 | ||
| 661 | #define regk_iop_sw_cfg_spu_gioout12 0x00000007 | ||
| 662 | #define regk_iop_sw_cfg_spu_gioout13 0x00000007 | ||
| 663 | #define regk_iop_sw_cfg_spu_gioout14 0x00000007 | ||
| 664 | #define regk_iop_sw_cfg_spu_gioout15 0x00000007 | ||
| 665 | #define regk_iop_sw_cfg_spu_gioout16 0x00000007 | ||
| 666 | #define regk_iop_sw_cfg_spu_gioout17 0x00000007 | ||
| 667 | #define regk_iop_sw_cfg_spu_gioout18 0x00000007 | ||
| 668 | #define regk_iop_sw_cfg_spu_gioout19 0x00000007 | ||
| 669 | #define regk_iop_sw_cfg_spu_gioout2 0x00000001 | ||
| 670 | #define regk_iop_sw_cfg_spu_gioout20 0x00000007 | ||
| 671 | #define regk_iop_sw_cfg_spu_gioout21 0x00000007 | ||
| 672 | #define regk_iop_sw_cfg_spu_gioout22 0x00000007 | ||
| 673 | #define regk_iop_sw_cfg_spu_gioout23 0x00000007 | ||
| 674 | #define regk_iop_sw_cfg_spu_gioout24 0x00000007 | ||
| 675 | #define regk_iop_sw_cfg_spu_gioout25 0x00000007 | ||
| 676 | #define regk_iop_sw_cfg_spu_gioout26 0x00000007 | ||
| 677 | #define regk_iop_sw_cfg_spu_gioout27 0x00000007 | ||
| 678 | #define regk_iop_sw_cfg_spu_gioout28 0x00000007 | ||
| 679 | #define regk_iop_sw_cfg_spu_gioout29 0x00000007 | ||
| 680 | #define regk_iop_sw_cfg_spu_gioout3 0x00000001 | ||
| 681 | #define regk_iop_sw_cfg_spu_gioout30 0x00000007 | ||
| 682 | #define regk_iop_sw_cfg_spu_gioout31 0x00000007 | ||
| 683 | #define regk_iop_sw_cfg_spu_gioout4 0x00000002 | ||
| 684 | #define regk_iop_sw_cfg_spu_gioout5 0x00000002 | ||
| 685 | #define regk_iop_sw_cfg_spu_gioout6 0x00000003 | ||
| 686 | #define regk_iop_sw_cfg_spu_gioout7 0x00000003 | ||
| 687 | #define regk_iop_sw_cfg_spu_gioout8 0x00000007 | ||
| 688 | #define regk_iop_sw_cfg_spu_gioout9 0x00000007 | ||
| 689 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 | ||
| 690 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 | ||
| 691 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 | ||
| 692 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 | ||
| 693 | #define regk_iop_sw_cfg_timer_grp0 0x00000000 | ||
| 694 | #define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 | ||
| 695 | #define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 | ||
| 696 | #define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 | ||
| 697 | #define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 | ||
| 698 | #define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 | ||
| 699 | #define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 | ||
| 700 | #define regk_iop_sw_cfg_timer_grp1 0x00000000 | ||
| 701 | #define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 | ||
| 702 | #define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 | ||
| 703 | #define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 | ||
| 704 | #define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 | ||
| 705 | #define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 | ||
| 706 | #define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 | ||
| 707 | #define regk_iop_sw_cfg_trig0_0 0x00000000 | ||
| 708 | #define regk_iop_sw_cfg_trig0_1 0x00000000 | ||
| 709 | #define regk_iop_sw_cfg_trig0_2 0x00000000 | ||
| 710 | #define regk_iop_sw_cfg_trig0_3 0x00000000 | ||
| 711 | #define regk_iop_sw_cfg_trig1_0 0x00000000 | ||
| 712 | #define regk_iop_sw_cfg_trig1_1 0x00000000 | ||
| 713 | #define regk_iop_sw_cfg_trig1_2 0x00000000 | ||
| 714 | #define regk_iop_sw_cfg_trig1_3 0x00000000 | ||
| 715 | #define regk_iop_sw_cfg_trig2_0 0x00000001 | ||
| 716 | #define regk_iop_sw_cfg_trig2_1 0x00000001 | ||
| 717 | #define regk_iop_sw_cfg_trig2_2 0x00000001 | ||
| 718 | #define regk_iop_sw_cfg_trig2_3 0x00000001 | ||
| 719 | #define regk_iop_sw_cfg_trig3_0 0x00000001 | ||
| 720 | #define regk_iop_sw_cfg_trig3_1 0x00000001 | ||
| 721 | #define regk_iop_sw_cfg_trig3_2 0x00000001 | ||
| 722 | #define regk_iop_sw_cfg_trig3_3 0x00000001 | ||
| 723 | #define regk_iop_sw_cfg_trig4_0 0x00000002 | ||
| 724 | #define regk_iop_sw_cfg_trig4_1 0x00000002 | ||
| 725 | #define regk_iop_sw_cfg_trig4_2 0x00000002 | ||
| 726 | #define regk_iop_sw_cfg_trig4_3 0x00000002 | ||
| 727 | #define regk_iop_sw_cfg_trig5_0 0x00000002 | ||
| 728 | #define regk_iop_sw_cfg_trig5_1 0x00000002 | ||
| 729 | #define regk_iop_sw_cfg_trig5_2 0x00000002 | ||
| 730 | #define regk_iop_sw_cfg_trig5_3 0x00000002 | ||
| 731 | #define regk_iop_sw_cfg_trig6_0 0x00000003 | ||
| 732 | #define regk_iop_sw_cfg_trig6_1 0x00000003 | ||
| 733 | #define regk_iop_sw_cfg_trig6_2 0x00000003 | ||
| 734 | #define regk_iop_sw_cfg_trig6_3 0x00000003 | ||
| 735 | #define regk_iop_sw_cfg_trig7_0 0x00000003 | ||
| 736 | #define regk_iop_sw_cfg_trig7_1 0x00000003 | ||
| 737 | #define regk_iop_sw_cfg_trig7_2 0x00000003 | ||
| 738 | #define regk_iop_sw_cfg_trig7_3 0x00000003 | ||
| 739 | #endif /* __iop_sw_cfg_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index 3f4fe1b31815..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null | |||
| @@ -1,950 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_cpu_defs_asm_h | ||
| 2 | #define __iop_sw_cpu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_cpu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_mpu_trace, scope iop_sw_cpu, type r */ | ||
| 54 | #define reg_iop_sw_cpu_r_mpu_trace_offset 0 | ||
| 55 | |||
| 56 | /* Register r_spu_trace, scope iop_sw_cpu, type r */ | ||
| 57 | #define reg_iop_sw_cpu_r_spu_trace_offset 4 | ||
| 58 | |||
| 59 | /* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ | ||
| 60 | #define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 | ||
| 61 | |||
| 62 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | ||
| 63 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 64 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 | ||
| 65 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 66 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 | ||
| 67 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 | ||
| 68 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 | ||
| 69 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 | ||
| 70 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
| 71 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
| 72 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
| 73 | #define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 | ||
| 74 | |||
| 75 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | ||
| 76 | #define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 | ||
| 77 | #define reg_iop_sw_cpu_rw_mc_data___val___width 32 | ||
| 78 | #define reg_iop_sw_cpu_rw_mc_data_offset 16 | ||
| 79 | |||
| 80 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | ||
| 81 | #define reg_iop_sw_cpu_rw_mc_addr_offset 20 | ||
| 82 | |||
| 83 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | ||
| 84 | #define reg_iop_sw_cpu_rs_mc_data_offset 24 | ||
| 85 | |||
| 86 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | ||
| 87 | #define reg_iop_sw_cpu_r_mc_data_offset 28 | ||
| 88 | |||
| 89 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | ||
| 90 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 | ||
| 91 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 | ||
| 92 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 | ||
| 93 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 | ||
| 94 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 | ||
| 95 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 | ||
| 96 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 | ||
| 97 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 | ||
| 98 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 | ||
| 99 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 | ||
| 100 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 | ||
| 101 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 | ||
| 102 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 | ||
| 103 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 | ||
| 104 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 | ||
| 105 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 | ||
| 106 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 | ||
| 107 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 | ||
| 108 | #define reg_iop_sw_cpu_r_mc_stat_offset 32 | ||
| 109 | |||
| 110 | /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 111 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 | ||
| 112 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 | ||
| 113 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 | ||
| 114 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 | ||
| 115 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 | ||
| 116 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 | ||
| 117 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 | ||
| 118 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 | ||
| 119 | #define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 | ||
| 120 | |||
| 121 | /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ | ||
| 122 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 | ||
| 123 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 | ||
| 124 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 | ||
| 125 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 | ||
| 126 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 | ||
| 127 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 | ||
| 128 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 | ||
| 129 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 | ||
| 130 | #define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 | ||
| 131 | |||
| 132 | /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 133 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
| 134 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 | ||
| 135 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
| 136 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
| 137 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 | ||
| 138 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
| 139 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
| 140 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 | ||
| 141 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
| 142 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
| 143 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 | ||
| 144 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
| 145 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 | ||
| 146 | |||
| 147 | /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 148 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
| 149 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 | ||
| 150 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 | ||
| 151 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
| 152 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 | ||
| 153 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 | ||
| 154 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
| 155 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 | ||
| 156 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 | ||
| 157 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
| 158 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 | ||
| 159 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 | ||
| 160 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 | ||
| 161 | |||
| 162 | /* Register r_bus_in, scope iop_sw_cpu, type r */ | ||
| 163 | #define reg_iop_sw_cpu_r_bus_in_offset 52 | ||
| 164 | |||
| 165 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 166 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 | ||
| 167 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 | ||
| 168 | #define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 | ||
| 169 | |||
| 170 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | ||
| 171 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 | ||
| 172 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 | ||
| 173 | #define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 | ||
| 174 | |||
| 175 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 176 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 177 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 | ||
| 178 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 | ||
| 179 | |||
| 180 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 181 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 182 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 | ||
| 183 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 | ||
| 184 | |||
| 185 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | ||
| 186 | #define reg_iop_sw_cpu_r_gio_in_offset 72 | ||
| 187 | |||
| 188 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | ||
| 189 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 | ||
| 190 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 | ||
| 191 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 | ||
| 192 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 | ||
| 193 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 | ||
| 194 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 | ||
| 195 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 | ||
| 196 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 | ||
| 197 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 | ||
| 198 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 | ||
| 199 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 | ||
| 200 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 | ||
| 201 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 | ||
| 202 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 | ||
| 203 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 | ||
| 204 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 | ||
| 205 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 | ||
| 206 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 | ||
| 207 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 | ||
| 208 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 | ||
| 209 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 | ||
| 210 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 | ||
| 211 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 | ||
| 212 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 | ||
| 213 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 | ||
| 214 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 | ||
| 215 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 | ||
| 216 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 | ||
| 217 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 | ||
| 218 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 | ||
| 219 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 | ||
| 220 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 | ||
| 221 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 | ||
| 222 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 | ||
| 223 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 | ||
| 224 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 | ||
| 225 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 | ||
| 226 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 | ||
| 227 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 | ||
| 228 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 | ||
| 229 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 | ||
| 230 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 | ||
| 231 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 | ||
| 232 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 | ||
| 233 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 | ||
| 234 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 | ||
| 235 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 | ||
| 236 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 | ||
| 237 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 | ||
| 238 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 | ||
| 239 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 | ||
| 240 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 | ||
| 241 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 | ||
| 242 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 | ||
| 243 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 | ||
| 244 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 | ||
| 245 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 | ||
| 246 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 | ||
| 247 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 | ||
| 248 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 | ||
| 249 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 | ||
| 250 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 | ||
| 251 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 | ||
| 252 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 | ||
| 253 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 | ||
| 254 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 | ||
| 255 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 | ||
| 256 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 | ||
| 257 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 | ||
| 258 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 | ||
| 259 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 | ||
| 260 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 | ||
| 261 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 | ||
| 262 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 | ||
| 263 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 | ||
| 264 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 | ||
| 265 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 | ||
| 266 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 | ||
| 267 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 | ||
| 268 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 | ||
| 269 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 | ||
| 270 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 | ||
| 271 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 | ||
| 272 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 | ||
| 273 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 | ||
| 274 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 | ||
| 275 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 | ||
| 276 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 | ||
| 277 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 | ||
| 278 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 | ||
| 279 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 | ||
| 280 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 | ||
| 281 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 | ||
| 282 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 | ||
| 283 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 | ||
| 284 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 | ||
| 285 | #define reg_iop_sw_cpu_rw_intr0_mask_offset 76 | ||
| 286 | |||
| 287 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | ||
| 288 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 | ||
| 289 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 | ||
| 290 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 | ||
| 291 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 | ||
| 292 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 | ||
| 293 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 | ||
| 294 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 | ||
| 295 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 | ||
| 296 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 | ||
| 297 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 | ||
| 298 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 | ||
| 299 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 | ||
| 300 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 | ||
| 301 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 | ||
| 302 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 | ||
| 303 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 | ||
| 304 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 | ||
| 305 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 | ||
| 306 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 | ||
| 307 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 | ||
| 308 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 | ||
| 309 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 | ||
| 310 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 | ||
| 311 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 | ||
| 312 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 | ||
| 313 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 | ||
| 314 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 | ||
| 315 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 | ||
| 316 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 | ||
| 317 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 | ||
| 318 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 | ||
| 319 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 | ||
| 320 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 | ||
| 321 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 | ||
| 322 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 | ||
| 323 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 | ||
| 324 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 | ||
| 325 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 | ||
| 326 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 | ||
| 327 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 | ||
| 328 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 | ||
| 329 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 | ||
| 330 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 | ||
| 331 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 | ||
| 332 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 | ||
| 333 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 | ||
| 334 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 | ||
| 335 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 | ||
| 336 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 | ||
| 337 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 | ||
| 338 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 | ||
| 339 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 | ||
| 340 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 | ||
| 341 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 | ||
| 342 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 | ||
| 343 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 | ||
| 344 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 | ||
| 345 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 | ||
| 346 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 | ||
| 347 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 | ||
| 348 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 | ||
| 349 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 | ||
| 350 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 | ||
| 351 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 | ||
| 352 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 | ||
| 353 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 | ||
| 354 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 | ||
| 355 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 | ||
| 356 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 | ||
| 357 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 | ||
| 358 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 | ||
| 359 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 | ||
| 360 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 | ||
| 361 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 | ||
| 362 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 | ||
| 363 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 | ||
| 364 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 | ||
| 365 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 | ||
| 366 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 | ||
| 367 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 | ||
| 368 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 | ||
| 369 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 | ||
| 370 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 | ||
| 371 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 | ||
| 372 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 | ||
| 373 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 | ||
| 374 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 | ||
| 375 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 | ||
| 376 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 | ||
| 377 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 | ||
| 378 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 | ||
| 379 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 | ||
| 380 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 | ||
| 381 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 | ||
| 382 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 | ||
| 383 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 | ||
| 384 | #define reg_iop_sw_cpu_rw_ack_intr0_offset 80 | ||
| 385 | |||
| 386 | /* Register r_intr0, scope iop_sw_cpu, type r */ | ||
| 387 | #define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 | ||
| 388 | #define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 | ||
| 389 | #define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 | ||
| 390 | #define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 | ||
| 391 | #define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 | ||
| 392 | #define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 | ||
| 393 | #define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 | ||
| 394 | #define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 | ||
| 395 | #define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 | ||
| 396 | #define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 | ||
| 397 | #define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 | ||
| 398 | #define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 | ||
| 399 | #define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 | ||
| 400 | #define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 | ||
| 401 | #define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 | ||
| 402 | #define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 | ||
| 403 | #define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 | ||
| 404 | #define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 | ||
| 405 | #define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 | ||
| 406 | #define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 | ||
| 407 | #define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 | ||
| 408 | #define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 | ||
| 409 | #define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 | ||
| 410 | #define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 | ||
| 411 | #define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 | ||
| 412 | #define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 | ||
| 413 | #define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 | ||
| 414 | #define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 | ||
| 415 | #define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 | ||
| 416 | #define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 | ||
| 417 | #define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 | ||
| 418 | #define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 | ||
| 419 | #define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 | ||
| 420 | #define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 | ||
| 421 | #define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 | ||
| 422 | #define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 | ||
| 423 | #define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 | ||
| 424 | #define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 | ||
| 425 | #define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 | ||
| 426 | #define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 | ||
| 427 | #define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 | ||
| 428 | #define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 | ||
| 429 | #define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 | ||
| 430 | #define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 | ||
| 431 | #define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 | ||
| 432 | #define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 | ||
| 433 | #define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 | ||
| 434 | #define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 | ||
| 435 | #define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 | ||
| 436 | #define reg_iop_sw_cpu_r_intr0___spu_0___width 1 | ||
| 437 | #define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 | ||
| 438 | #define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 | ||
| 439 | #define reg_iop_sw_cpu_r_intr0___spu_1___width 1 | ||
| 440 | #define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 | ||
| 441 | #define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 | ||
| 442 | #define reg_iop_sw_cpu_r_intr0___spu_2___width 1 | ||
| 443 | #define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 | ||
| 444 | #define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 | ||
| 445 | #define reg_iop_sw_cpu_r_intr0___spu_3___width 1 | ||
| 446 | #define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 | ||
| 447 | #define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 | ||
| 448 | #define reg_iop_sw_cpu_r_intr0___spu_4___width 1 | ||
| 449 | #define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 | ||
| 450 | #define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 | ||
| 451 | #define reg_iop_sw_cpu_r_intr0___spu_5___width 1 | ||
| 452 | #define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 | ||
| 453 | #define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 | ||
| 454 | #define reg_iop_sw_cpu_r_intr0___spu_6___width 1 | ||
| 455 | #define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 | ||
| 456 | #define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 | ||
| 457 | #define reg_iop_sw_cpu_r_intr0___spu_7___width 1 | ||
| 458 | #define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 | ||
| 459 | #define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 | ||
| 460 | #define reg_iop_sw_cpu_r_intr0___spu_8___width 1 | ||
| 461 | #define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 | ||
| 462 | #define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 | ||
| 463 | #define reg_iop_sw_cpu_r_intr0___spu_9___width 1 | ||
| 464 | #define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 | ||
| 465 | #define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 | ||
| 466 | #define reg_iop_sw_cpu_r_intr0___spu_10___width 1 | ||
| 467 | #define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 | ||
| 468 | #define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 | ||
| 469 | #define reg_iop_sw_cpu_r_intr0___spu_11___width 1 | ||
| 470 | #define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 | ||
| 471 | #define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 | ||
| 472 | #define reg_iop_sw_cpu_r_intr0___spu_12___width 1 | ||
| 473 | #define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 | ||
| 474 | #define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 | ||
| 475 | #define reg_iop_sw_cpu_r_intr0___spu_13___width 1 | ||
| 476 | #define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 | ||
| 477 | #define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 | ||
| 478 | #define reg_iop_sw_cpu_r_intr0___spu_14___width 1 | ||
| 479 | #define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 | ||
| 480 | #define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 | ||
| 481 | #define reg_iop_sw_cpu_r_intr0___spu_15___width 1 | ||
| 482 | #define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 | ||
| 483 | #define reg_iop_sw_cpu_r_intr0_offset 84 | ||
| 484 | |||
| 485 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | ||
| 486 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 | ||
| 487 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 | ||
| 488 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 | ||
| 489 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 | ||
| 490 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 | ||
| 491 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 | ||
| 492 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 | ||
| 493 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 | ||
| 494 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 | ||
| 495 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 | ||
| 496 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 | ||
| 497 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 | ||
| 498 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 | ||
| 499 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 | ||
| 500 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 | ||
| 501 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 | ||
| 502 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 | ||
| 503 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 | ||
| 504 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 | ||
| 505 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 | ||
| 506 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 | ||
| 507 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 | ||
| 508 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 | ||
| 509 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 | ||
| 510 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 | ||
| 511 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 | ||
| 512 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 | ||
| 513 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 | ||
| 514 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 | ||
| 515 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 | ||
| 516 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 | ||
| 517 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 | ||
| 518 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 | ||
| 519 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 | ||
| 520 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 | ||
| 521 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 | ||
| 522 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 | ||
| 523 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 | ||
| 524 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 | ||
| 525 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 | ||
| 526 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 | ||
| 527 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 | ||
| 528 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 | ||
| 529 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 | ||
| 530 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 | ||
| 531 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 | ||
| 532 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 | ||
| 533 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 | ||
| 534 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 | ||
| 535 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 | ||
| 536 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 | ||
| 537 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 | ||
| 538 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 | ||
| 539 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 | ||
| 540 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 | ||
| 541 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 | ||
| 542 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 | ||
| 543 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 | ||
| 544 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 | ||
| 545 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 | ||
| 546 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 | ||
| 547 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 | ||
| 548 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 | ||
| 549 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 | ||
| 550 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 | ||
| 551 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 | ||
| 552 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 | ||
| 553 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 | ||
| 554 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 | ||
| 555 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 | ||
| 556 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 | ||
| 557 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 | ||
| 558 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 | ||
| 559 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 | ||
| 560 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 | ||
| 561 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 | ||
| 562 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 | ||
| 563 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 | ||
| 564 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 | ||
| 565 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 | ||
| 566 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 | ||
| 567 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 | ||
| 568 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 | ||
| 569 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 | ||
| 570 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 | ||
| 571 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 | ||
| 572 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 | ||
| 573 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 | ||
| 574 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 | ||
| 575 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 | ||
| 576 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 | ||
| 577 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 | ||
| 578 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 | ||
| 579 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 | ||
| 580 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 | ||
| 581 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 | ||
| 582 | #define reg_iop_sw_cpu_r_masked_intr0_offset 88 | ||
| 583 | |||
| 584 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | ||
| 585 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 | ||
| 586 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 | ||
| 587 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 | ||
| 588 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 | ||
| 589 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 | ||
| 590 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 | ||
| 591 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 | ||
| 592 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 | ||
| 593 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 | ||
| 594 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 | ||
| 595 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 | ||
| 596 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 | ||
| 597 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 | ||
| 598 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 | ||
| 599 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 | ||
| 600 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 | ||
| 601 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 | ||
| 602 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 | ||
| 603 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 | ||
| 604 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 | ||
| 605 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 | ||
| 606 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 | ||
| 607 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 | ||
| 608 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 | ||
| 609 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 | ||
| 610 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 | ||
| 611 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 | ||
| 612 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 | ||
| 613 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 | ||
| 614 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 | ||
| 615 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 | ||
| 616 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 | ||
| 617 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 | ||
| 618 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 | ||
| 619 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 | ||
| 620 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 | ||
| 621 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 | ||
| 622 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 | ||
| 623 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 | ||
| 624 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 | ||
| 625 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 | ||
| 626 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 | ||
| 627 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 | ||
| 628 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 | ||
| 629 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 | ||
| 630 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 | ||
| 631 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 | ||
| 632 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 | ||
| 633 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 | ||
| 634 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 | ||
| 635 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 | ||
| 636 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 | ||
| 637 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 | ||
| 638 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 | ||
| 639 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 | ||
| 640 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 | ||
| 641 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 | ||
| 642 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 | ||
| 643 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 | ||
| 644 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 | ||
| 645 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 | ||
| 646 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 | ||
| 647 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 | ||
| 648 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 | ||
| 649 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 | ||
| 650 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 | ||
| 651 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 | ||
| 652 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 | ||
| 653 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 | ||
| 654 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 | ||
| 655 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 | ||
| 656 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 | ||
| 657 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 | ||
| 658 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 | ||
| 659 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 | ||
| 660 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 | ||
| 661 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 | ||
| 662 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 | ||
| 663 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 | ||
| 664 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 | ||
| 665 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 | ||
| 666 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 | ||
| 667 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 | ||
| 668 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 | ||
| 669 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 | ||
| 670 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 | ||
| 671 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 | ||
| 672 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 | ||
| 673 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 | ||
| 674 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 | ||
| 675 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 | ||
| 676 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 | ||
| 677 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 | ||
| 678 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 | ||
| 679 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 | ||
| 680 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 | ||
| 681 | #define reg_iop_sw_cpu_rw_intr1_mask_offset 92 | ||
| 682 | |||
| 683 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | ||
| 684 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 | ||
| 685 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 | ||
| 686 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 | ||
| 687 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 | ||
| 688 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 | ||
| 689 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 | ||
| 690 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 | ||
| 691 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 | ||
| 692 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 | ||
| 693 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 | ||
| 694 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 | ||
| 695 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 | ||
| 696 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 | ||
| 697 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 | ||
| 698 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 | ||
| 699 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 | ||
| 700 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 | ||
| 701 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 | ||
| 702 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 | ||
| 703 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 | ||
| 704 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 | ||
| 705 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 | ||
| 706 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 | ||
| 707 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 | ||
| 708 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 | ||
| 709 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 | ||
| 710 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 | ||
| 711 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 | ||
| 712 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 | ||
| 713 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 | ||
| 714 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 | ||
| 715 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 | ||
| 716 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 | ||
| 717 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 | ||
| 718 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 | ||
| 719 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 | ||
| 720 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 | ||
| 721 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 | ||
| 722 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 | ||
| 723 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 | ||
| 724 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 | ||
| 725 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 | ||
| 726 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 | ||
| 727 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 | ||
| 728 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 | ||
| 729 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 | ||
| 730 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 | ||
| 731 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 | ||
| 732 | #define reg_iop_sw_cpu_rw_ack_intr1_offset 96 | ||
| 733 | |||
| 734 | /* Register r_intr1, scope iop_sw_cpu, type r */ | ||
| 735 | #define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 | ||
| 736 | #define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 | ||
| 737 | #define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 | ||
| 738 | #define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 | ||
| 739 | #define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 | ||
| 740 | #define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 | ||
| 741 | #define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 | ||
| 742 | #define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 | ||
| 743 | #define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 | ||
| 744 | #define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 | ||
| 745 | #define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 | ||
| 746 | #define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 | ||
| 747 | #define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 | ||
| 748 | #define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 | ||
| 749 | #define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 | ||
| 750 | #define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 | ||
| 751 | #define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 | ||
| 752 | #define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 | ||
| 753 | #define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 | ||
| 754 | #define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 | ||
| 755 | #define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 | ||
| 756 | #define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 | ||
| 757 | #define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 | ||
| 758 | #define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 | ||
| 759 | #define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 | ||
| 760 | #define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 | ||
| 761 | #define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 | ||
| 762 | #define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 | ||
| 763 | #define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 | ||
| 764 | #define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 | ||
| 765 | #define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 | ||
| 766 | #define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 | ||
| 767 | #define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 | ||
| 768 | #define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 | ||
| 769 | #define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 | ||
| 770 | #define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 | ||
| 771 | #define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 | ||
| 772 | #define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 | ||
| 773 | #define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 | ||
| 774 | #define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 | ||
| 775 | #define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 | ||
| 776 | #define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 | ||
| 777 | #define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 | ||
| 778 | #define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 | ||
| 779 | #define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 | ||
| 780 | #define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 | ||
| 781 | #define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 | ||
| 782 | #define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 | ||
| 783 | #define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 | ||
| 784 | #define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 | ||
| 785 | #define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 | ||
| 786 | #define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 | ||
| 787 | #define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 | ||
| 788 | #define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 | ||
| 789 | #define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 | ||
| 790 | #define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 | ||
| 791 | #define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 | ||
| 792 | #define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 | ||
| 793 | #define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 | ||
| 794 | #define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 | ||
| 795 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 | ||
| 796 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 | ||
| 797 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 | ||
| 798 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 | ||
| 799 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 | ||
| 800 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 | ||
| 801 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 | ||
| 802 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 | ||
| 803 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 | ||
| 804 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 | ||
| 805 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 | ||
| 806 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 | ||
| 807 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 | ||
| 808 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 | ||
| 809 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 | ||
| 810 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 | ||
| 811 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 | ||
| 812 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 | ||
| 813 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 | ||
| 814 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 | ||
| 815 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 | ||
| 816 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 | ||
| 817 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 | ||
| 818 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 | ||
| 819 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 | ||
| 820 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 | ||
| 821 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 | ||
| 822 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 | ||
| 823 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 | ||
| 824 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 | ||
| 825 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 | ||
| 826 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 | ||
| 827 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 | ||
| 828 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 | ||
| 829 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 | ||
| 830 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 | ||
| 831 | #define reg_iop_sw_cpu_r_intr1_offset 100 | ||
| 832 | |||
| 833 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | ||
| 834 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 | ||
| 835 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 | ||
| 836 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 | ||
| 837 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 | ||
| 838 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 | ||
| 839 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 | ||
| 840 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 | ||
| 841 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 | ||
| 842 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 | ||
| 843 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 | ||
| 844 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 | ||
| 845 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 | ||
| 846 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 | ||
| 847 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 | ||
| 848 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 | ||
| 849 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 | ||
| 850 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 | ||
| 851 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 | ||
| 852 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 | ||
| 853 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 | ||
| 854 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 | ||
| 855 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 | ||
| 856 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 | ||
| 857 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 | ||
| 858 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 | ||
| 859 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 | ||
| 860 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 | ||
| 861 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 | ||
| 862 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 | ||
| 863 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 | ||
| 864 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 | ||
| 865 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 | ||
| 866 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 | ||
| 867 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 | ||
| 868 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 | ||
| 869 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 | ||
| 870 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 | ||
| 871 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 | ||
| 872 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 | ||
| 873 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 | ||
| 874 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 | ||
| 875 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 | ||
| 876 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 | ||
| 877 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 | ||
| 878 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 | ||
| 879 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 | ||
| 880 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 | ||
| 881 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 | ||
| 882 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 | ||
| 883 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 | ||
| 884 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 | ||
| 885 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 | ||
| 886 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 | ||
| 887 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 | ||
| 888 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 | ||
| 889 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 | ||
| 890 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 | ||
| 891 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 | ||
| 892 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 | ||
| 893 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 | ||
| 894 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 | ||
| 895 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 | ||
| 896 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 | ||
| 897 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 | ||
| 898 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 | ||
| 899 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 | ||
| 900 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 | ||
| 901 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 | ||
| 902 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 | ||
| 903 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 | ||
| 904 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 | ||
| 905 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 | ||
| 906 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 | ||
| 907 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 | ||
| 908 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 | ||
| 909 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 | ||
| 910 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 | ||
| 911 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 | ||
| 912 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 | ||
| 913 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 | ||
| 914 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 | ||
| 915 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 | ||
| 916 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 | ||
| 917 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 | ||
| 918 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 | ||
| 919 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 | ||
| 920 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 | ||
| 921 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 | ||
| 922 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 | ||
| 923 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 | ||
| 924 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 | ||
| 925 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 | ||
| 926 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 | ||
| 927 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 | ||
| 928 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 | ||
| 929 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 | ||
| 930 | #define reg_iop_sw_cpu_r_masked_intr1_offset 104 | ||
| 931 | |||
| 932 | |||
| 933 | /* Constants */ | ||
| 934 | #define regk_iop_sw_cpu_copy 0x00000000 | ||
| 935 | #define regk_iop_sw_cpu_no 0x00000000 | ||
| 936 | #define regk_iop_sw_cpu_rd 0x00000002 | ||
| 937 | #define regk_iop_sw_cpu_reg_copy 0x00000001 | ||
| 938 | #define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 | ||
| 939 | #define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 | ||
| 940 | #define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 | ||
| 941 | #define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 | ||
| 942 | #define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 | ||
| 943 | #define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 944 | #define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 945 | #define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 | ||
| 946 | #define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 | ||
| 947 | #define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 | ||
| 948 | #define regk_iop_sw_cpu_wr 0x00000003 | ||
| 949 | #define regk_iop_sw_cpu_yes 0x00000001 | ||
| 950 | #endif /* __iop_sw_cpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index ffcc83b22d21..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null | |||
| @@ -1,1086 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_mpu_defs_asm_h | ||
| 2 | #define __iop_sw_mpu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_mpu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ | ||
| 54 | #define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 | ||
| 55 | #define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 | ||
| 56 | #define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 | ||
| 57 | |||
| 58 | /* Register r_spu_trace, scope iop_sw_mpu, type r */ | ||
| 59 | #define reg_iop_sw_mpu_r_spu_trace_offset 4 | ||
| 60 | |||
| 61 | /* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ | ||
| 62 | #define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 | ||
| 63 | |||
| 64 | /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ | ||
| 65 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 66 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 | ||
| 67 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 68 | #define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 | ||
| 69 | #define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 | ||
| 70 | #define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 | ||
| 71 | #define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 | ||
| 72 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
| 73 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
| 74 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
| 75 | #define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 | ||
| 76 | |||
| 77 | /* Register rw_mc_data, scope iop_sw_mpu, type rw */ | ||
| 78 | #define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 | ||
| 79 | #define reg_iop_sw_mpu_rw_mc_data___val___width 32 | ||
| 80 | #define reg_iop_sw_mpu_rw_mc_data_offset 16 | ||
| 81 | |||
| 82 | /* Register rw_mc_addr, scope iop_sw_mpu, type rw */ | ||
| 83 | #define reg_iop_sw_mpu_rw_mc_addr_offset 20 | ||
| 84 | |||
| 85 | /* Register rs_mc_data, scope iop_sw_mpu, type rs */ | ||
| 86 | #define reg_iop_sw_mpu_rs_mc_data_offset 24 | ||
| 87 | |||
| 88 | /* Register r_mc_data, scope iop_sw_mpu, type r */ | ||
| 89 | #define reg_iop_sw_mpu_r_mc_data_offset 28 | ||
| 90 | |||
| 91 | /* Register r_mc_stat, scope iop_sw_mpu, type r */ | ||
| 92 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 | ||
| 93 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 | ||
| 94 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 | ||
| 95 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 | ||
| 96 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 | ||
| 97 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 | ||
| 98 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 | ||
| 99 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 | ||
| 100 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 | ||
| 101 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 | ||
| 102 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 | ||
| 103 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 | ||
| 104 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 | ||
| 105 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 | ||
| 106 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 | ||
| 107 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 | ||
| 108 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 | ||
| 109 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 | ||
| 110 | #define reg_iop_sw_mpu_r_mc_stat_offset 32 | ||
| 111 | |||
| 112 | /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 113 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 | ||
| 114 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 | ||
| 115 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 | ||
| 116 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 | ||
| 117 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 | ||
| 118 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 | ||
| 119 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 | ||
| 120 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 | ||
| 121 | #define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 | ||
| 122 | |||
| 123 | /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ | ||
| 124 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 | ||
| 125 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 | ||
| 126 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 | ||
| 127 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 | ||
| 128 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 | ||
| 129 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 | ||
| 130 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 | ||
| 131 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 | ||
| 132 | #define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 | ||
| 133 | |||
| 134 | /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 135 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
| 136 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 | ||
| 137 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
| 138 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
| 139 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 | ||
| 140 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
| 141 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
| 142 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 | ||
| 143 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
| 144 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
| 145 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 | ||
| 146 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
| 147 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 | ||
| 148 | |||
| 149 | /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 150 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
| 151 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 | ||
| 152 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 | ||
| 153 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
| 154 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 | ||
| 155 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 | ||
| 156 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
| 157 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 | ||
| 158 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 | ||
| 159 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
| 160 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 | ||
| 161 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 | ||
| 162 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 | ||
| 163 | |||
| 164 | /* Register r_bus_in, scope iop_sw_mpu, type r */ | ||
| 165 | #define reg_iop_sw_mpu_r_bus_in_offset 52 | ||
| 166 | |||
| 167 | /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 168 | #define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 | ||
| 169 | #define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 | ||
| 170 | #define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 | ||
| 171 | |||
| 172 | /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ | ||
| 173 | #define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 | ||
| 174 | #define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 | ||
| 175 | #define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 | ||
| 176 | |||
| 177 | /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 178 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 179 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 | ||
| 180 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 | ||
| 181 | |||
| 182 | /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 183 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 184 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 | ||
| 185 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 | ||
| 186 | |||
| 187 | /* Register r_gio_in, scope iop_sw_mpu, type r */ | ||
| 188 | #define reg_iop_sw_mpu_r_gio_in_offset 72 | ||
| 189 | |||
| 190 | /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ | ||
| 191 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 | ||
| 192 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 | ||
| 193 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 | ||
| 194 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 | ||
| 195 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 | ||
| 196 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 | ||
| 197 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 | ||
| 198 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 | ||
| 199 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 | ||
| 200 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 | ||
| 201 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 | ||
| 202 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 | ||
| 203 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 | ||
| 204 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 | ||
| 205 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 | ||
| 206 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 | ||
| 207 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 | ||
| 208 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 | ||
| 209 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 | ||
| 210 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 | ||
| 211 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 | ||
| 212 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 | ||
| 213 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 | ||
| 214 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 | ||
| 215 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 | ||
| 216 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 | ||
| 217 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 | ||
| 218 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 | ||
| 219 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 | ||
| 220 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 | ||
| 221 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 | ||
| 222 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 | ||
| 223 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 | ||
| 224 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 | ||
| 225 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 | ||
| 226 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 | ||
| 227 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 | ||
| 228 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 | ||
| 229 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 | ||
| 230 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 | ||
| 231 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 | ||
| 232 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 | ||
| 233 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 | ||
| 234 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 | ||
| 235 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 | ||
| 236 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 | ||
| 237 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 | ||
| 238 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 | ||
| 239 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 | ||
| 240 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 | ||
| 241 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 | ||
| 242 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 | ||
| 243 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 | ||
| 244 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 | ||
| 245 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 | ||
| 246 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 | ||
| 247 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 | ||
| 248 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 | ||
| 249 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 | ||
| 250 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 | ||
| 251 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 | ||
| 252 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 | ||
| 253 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 | ||
| 254 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 | ||
| 255 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 | ||
| 256 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 | ||
| 257 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 | ||
| 258 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 | ||
| 259 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 | ||
| 260 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 | ||
| 261 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 | ||
| 262 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 | ||
| 263 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 | ||
| 264 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 | ||
| 265 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 | ||
| 266 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 | ||
| 267 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 | ||
| 268 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 | ||
| 269 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 | ||
| 270 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 | ||
| 271 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 | ||
| 272 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 | ||
| 273 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 | ||
| 274 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 | ||
| 275 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 | ||
| 276 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 | ||
| 277 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 | ||
| 278 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 | ||
| 279 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 | ||
| 280 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 | ||
| 281 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 | ||
| 282 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 | ||
| 283 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 | ||
| 284 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 | ||
| 285 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 | ||
| 286 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 | ||
| 287 | #define reg_iop_sw_mpu_rw_cpu_intr_offset 76 | ||
| 288 | |||
| 289 | /* Register r_cpu_intr, scope iop_sw_mpu, type r */ | ||
| 290 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 | ||
| 291 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 | ||
| 292 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 | ||
| 293 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 | ||
| 294 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 | ||
| 295 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 | ||
| 296 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 | ||
| 297 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 | ||
| 298 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 | ||
| 299 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 | ||
| 300 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 | ||
| 301 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 | ||
| 302 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 | ||
| 303 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 | ||
| 304 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 | ||
| 305 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 | ||
| 306 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 | ||
| 307 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 | ||
| 308 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 | ||
| 309 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 | ||
| 310 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 | ||
| 311 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 | ||
| 312 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 | ||
| 313 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 | ||
| 314 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 | ||
| 315 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 | ||
| 316 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 | ||
| 317 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 | ||
| 318 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 | ||
| 319 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 | ||
| 320 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 | ||
| 321 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 | ||
| 322 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 | ||
| 323 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 | ||
| 324 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 | ||
| 325 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 | ||
| 326 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 | ||
| 327 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 | ||
| 328 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 | ||
| 329 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 | ||
| 330 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 | ||
| 331 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 | ||
| 332 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 | ||
| 333 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 | ||
| 334 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 | ||
| 335 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 | ||
| 336 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 | ||
| 337 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 | ||
| 338 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 | ||
| 339 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 | ||
| 340 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 | ||
| 341 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 | ||
| 342 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 | ||
| 343 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 | ||
| 344 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 | ||
| 345 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 | ||
| 346 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 | ||
| 347 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 | ||
| 348 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 | ||
| 349 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 | ||
| 350 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 | ||
| 351 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 | ||
| 352 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 | ||
| 353 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 | ||
| 354 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 | ||
| 355 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 | ||
| 356 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 | ||
| 357 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 | ||
| 358 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 | ||
| 359 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 | ||
| 360 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 | ||
| 361 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 | ||
| 362 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 | ||
| 363 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 | ||
| 364 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 | ||
| 365 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 | ||
| 366 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 | ||
| 367 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 | ||
| 368 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 | ||
| 369 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 | ||
| 370 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 | ||
| 371 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 | ||
| 372 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 | ||
| 373 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 | ||
| 374 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 | ||
| 375 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 | ||
| 376 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 | ||
| 377 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 | ||
| 378 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 | ||
| 379 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 | ||
| 380 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 | ||
| 381 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 | ||
| 382 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 | ||
| 383 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 | ||
| 384 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 | ||
| 385 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 | ||
| 386 | #define reg_iop_sw_mpu_r_cpu_intr_offset 80 | ||
| 387 | |||
| 388 | /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ | ||
| 389 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 | ||
| 390 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 | ||
| 391 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 | ||
| 392 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 | ||
| 393 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 | ||
| 394 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 | ||
| 395 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 | ||
| 396 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 | ||
| 397 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 | ||
| 398 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 | ||
| 399 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 | ||
| 400 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 | ||
| 401 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 | ||
| 402 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 | ||
| 403 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 | ||
| 404 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 | ||
| 405 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 | ||
| 406 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 | ||
| 407 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 | ||
| 408 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 | ||
| 409 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 | ||
| 410 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 | ||
| 411 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 | ||
| 412 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 | ||
| 413 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 | ||
| 414 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 | ||
| 415 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 | ||
| 416 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 | ||
| 417 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 | ||
| 418 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 | ||
| 419 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 | ||
| 420 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 | ||
| 421 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 | ||
| 422 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 | ||
| 423 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 | ||
| 424 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 | ||
| 425 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 | ||
| 426 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 | ||
| 427 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 | ||
| 428 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 | ||
| 429 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 | ||
| 430 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 | ||
| 431 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 | ||
| 432 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 | ||
| 433 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 | ||
| 434 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 | ||
| 435 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 | ||
| 436 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 | ||
| 437 | #define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 | ||
| 438 | |||
| 439 | /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ | ||
| 440 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 | ||
| 441 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 | ||
| 442 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 | ||
| 443 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 | ||
| 444 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 | ||
| 445 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 | ||
| 446 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 | ||
| 447 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 | ||
| 448 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 | ||
| 449 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 | ||
| 450 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 | ||
| 451 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 | ||
| 452 | #define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 | ||
| 453 | |||
| 454 | /* Register r_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 455 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 | ||
| 456 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 | ||
| 457 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 | ||
| 458 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 | ||
| 459 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 | ||
| 460 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 | ||
| 461 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 | ||
| 462 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 | ||
| 463 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 | ||
| 464 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 | ||
| 465 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 | ||
| 466 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 | ||
| 467 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 | ||
| 468 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 | ||
| 469 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 | ||
| 470 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 | ||
| 471 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 | ||
| 472 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 | ||
| 473 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 | ||
| 474 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 | ||
| 475 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 | ||
| 476 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 | ||
| 477 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 | ||
| 478 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 | ||
| 479 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 | ||
| 480 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 | ||
| 481 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 | ||
| 482 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 | ||
| 483 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 | ||
| 484 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 | ||
| 485 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 | ||
| 486 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 | ||
| 487 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 | ||
| 488 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 | ||
| 489 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 | ||
| 490 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 | ||
| 491 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 | ||
| 492 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 | ||
| 493 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 | ||
| 494 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 | ||
| 495 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 | ||
| 496 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 | ||
| 497 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 | ||
| 498 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 | ||
| 499 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 | ||
| 500 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 | ||
| 501 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 | ||
| 502 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 | ||
| 503 | #define reg_iop_sw_mpu_r_intr_grp0_offset 92 | ||
| 504 | |||
| 505 | /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 506 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 | ||
| 507 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 | ||
| 508 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 | ||
| 509 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 | ||
| 510 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 | ||
| 511 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 | ||
| 512 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 | ||
| 513 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 | ||
| 514 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 | ||
| 515 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 | ||
| 516 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 | ||
| 517 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 | ||
| 518 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 | ||
| 519 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 | ||
| 520 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 | ||
| 521 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 | ||
| 522 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 | ||
| 523 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 | ||
| 524 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 | ||
| 525 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 | ||
| 526 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 | ||
| 527 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 | ||
| 528 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 | ||
| 529 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 | ||
| 530 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 | ||
| 531 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 | ||
| 532 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 | ||
| 533 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 | ||
| 534 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 | ||
| 535 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 | ||
| 536 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 | ||
| 537 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 | ||
| 538 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 | ||
| 539 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 | ||
| 540 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 | ||
| 541 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 | ||
| 542 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 | ||
| 543 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 | ||
| 544 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 | ||
| 545 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 | ||
| 546 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 | ||
| 547 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 | ||
| 548 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 | ||
| 549 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 | ||
| 550 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 | ||
| 551 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 | ||
| 552 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 | ||
| 553 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 | ||
| 554 | #define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 | ||
| 555 | |||
| 556 | /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ | ||
| 557 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 | ||
| 558 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 | ||
| 559 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 | ||
| 560 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 | ||
| 561 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 | ||
| 562 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 | ||
| 563 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 | ||
| 564 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 | ||
| 565 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 | ||
| 566 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 | ||
| 567 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 | ||
| 568 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 | ||
| 569 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 | ||
| 570 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 | ||
| 571 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 | ||
| 572 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 | ||
| 573 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 | ||
| 574 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 | ||
| 575 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 | ||
| 576 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 | ||
| 577 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 | ||
| 578 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 | ||
| 579 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 | ||
| 580 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 | ||
| 581 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 | ||
| 582 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 | ||
| 583 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 | ||
| 584 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 | ||
| 585 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 | ||
| 586 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 | ||
| 587 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 | ||
| 588 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 | ||
| 589 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 | ||
| 590 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 | ||
| 591 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 | ||
| 592 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 | ||
| 593 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 | ||
| 594 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 | ||
| 595 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 | ||
| 596 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 | ||
| 597 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 | ||
| 598 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 | ||
| 599 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 | ||
| 600 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 | ||
| 601 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 | ||
| 602 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 | ||
| 603 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 | ||
| 604 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 | ||
| 605 | #define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 | ||
| 606 | |||
| 607 | /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ | ||
| 608 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 | ||
| 609 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 | ||
| 610 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 | ||
| 611 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 | ||
| 612 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 | ||
| 613 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 | ||
| 614 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 | ||
| 615 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 | ||
| 616 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 | ||
| 617 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 | ||
| 618 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 | ||
| 619 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 | ||
| 620 | #define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 | ||
| 621 | |||
| 622 | /* Register r_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 623 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 | ||
| 624 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 | ||
| 625 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 | ||
| 626 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 | ||
| 627 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 | ||
| 628 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 | ||
| 629 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 | ||
| 630 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 | ||
| 631 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 | ||
| 632 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 | ||
| 633 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 | ||
| 634 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 | ||
| 635 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 | ||
| 636 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 | ||
| 637 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 | ||
| 638 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 | ||
| 639 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 | ||
| 640 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 | ||
| 641 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 | ||
| 642 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 | ||
| 643 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 | ||
| 644 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 | ||
| 645 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 | ||
| 646 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 | ||
| 647 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 | ||
| 648 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 | ||
| 649 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 | ||
| 650 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 | ||
| 651 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 | ||
| 652 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 | ||
| 653 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 | ||
| 654 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 | ||
| 655 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 | ||
| 656 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 | ||
| 657 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 | ||
| 658 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 | ||
| 659 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 | ||
| 660 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 | ||
| 661 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 | ||
| 662 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 | ||
| 663 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 | ||
| 664 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 | ||
| 665 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 | ||
| 666 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 | ||
| 667 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 | ||
| 668 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 | ||
| 669 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 | ||
| 670 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 | ||
| 671 | #define reg_iop_sw_mpu_r_intr_grp1_offset 108 | ||
| 672 | |||
| 673 | /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 674 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 | ||
| 675 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 | ||
| 676 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 | ||
| 677 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 | ||
| 678 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 | ||
| 679 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 | ||
| 680 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 | ||
| 681 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 | ||
| 682 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 | ||
| 683 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 | ||
| 684 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 | ||
| 685 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 | ||
| 686 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 | ||
| 687 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 | ||
| 688 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 | ||
| 689 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 | ||
| 690 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 | ||
| 691 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 | ||
| 692 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 | ||
| 693 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 | ||
| 694 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 | ||
| 695 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 | ||
| 696 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 | ||
| 697 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 | ||
| 698 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 | ||
| 699 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 | ||
| 700 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 | ||
| 701 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 | ||
| 702 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 | ||
| 703 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 | ||
| 704 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 | ||
| 705 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 | ||
| 706 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 | ||
| 707 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 | ||
| 708 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 | ||
| 709 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 | ||
| 710 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 | ||
| 711 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 | ||
| 712 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 | ||
| 713 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 | ||
| 714 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 | ||
| 715 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 | ||
| 716 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 | ||
| 717 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 | ||
| 718 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 | ||
| 719 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 | ||
| 720 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 | ||
| 721 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 | ||
| 722 | #define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 | ||
| 723 | |||
| 724 | /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ | ||
| 725 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 | ||
| 726 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 | ||
| 727 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 | ||
| 728 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 | ||
| 729 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 | ||
| 730 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 | ||
| 731 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 | ||
| 732 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 | ||
| 733 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 | ||
| 734 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 | ||
| 735 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 | ||
| 736 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 | ||
| 737 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 | ||
| 738 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 | ||
| 739 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 | ||
| 740 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 | ||
| 741 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 | ||
| 742 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 | ||
| 743 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 | ||
| 744 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 | ||
| 745 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 | ||
| 746 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 | ||
| 747 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 | ||
| 748 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 | ||
| 749 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 | ||
| 750 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 | ||
| 751 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 | ||
| 752 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 | ||
| 753 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 | ||
| 754 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 | ||
| 755 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 | ||
| 756 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 | ||
| 757 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 | ||
| 758 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 | ||
| 759 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 | ||
| 760 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 | ||
| 761 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 | ||
| 762 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 | ||
| 763 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 | ||
| 764 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 | ||
| 765 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 | ||
| 766 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 | ||
| 767 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 | ||
| 768 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 | ||
| 769 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 | ||
| 770 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 | ||
| 771 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 | ||
| 772 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 | ||
| 773 | #define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 | ||
| 774 | |||
| 775 | /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ | ||
| 776 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 | ||
| 777 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 | ||
| 778 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 | ||
| 779 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 | ||
| 780 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 | ||
| 781 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 | ||
| 782 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 | ||
| 783 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 | ||
| 784 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 | ||
| 785 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 | ||
| 786 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 | ||
| 787 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 | ||
| 788 | #define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 | ||
| 789 | |||
| 790 | /* Register r_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 791 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 | ||
| 792 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 | ||
| 793 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 | ||
| 794 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 | ||
| 795 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 | ||
| 796 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 | ||
| 797 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 | ||
| 798 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 | ||
| 799 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 | ||
| 800 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 | ||
| 801 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 | ||
| 802 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 | ||
| 803 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 | ||
| 804 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 | ||
| 805 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 | ||
| 806 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 | ||
| 807 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 | ||
| 808 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 | ||
| 809 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 | ||
| 810 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 | ||
| 811 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 | ||
| 812 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 | ||
| 813 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 | ||
| 814 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 | ||
| 815 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 | ||
| 816 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 | ||
| 817 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 | ||
| 818 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 | ||
| 819 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 | ||
| 820 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 | ||
| 821 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 | ||
| 822 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 | ||
| 823 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 | ||
| 824 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 | ||
| 825 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 | ||
| 826 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 | ||
| 827 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 | ||
| 828 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 | ||
| 829 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 | ||
| 830 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 | ||
| 831 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 | ||
| 832 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 | ||
| 833 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 | ||
| 834 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 | ||
| 835 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 | ||
| 836 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 | ||
| 837 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 | ||
| 838 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 | ||
| 839 | #define reg_iop_sw_mpu_r_intr_grp2_offset 124 | ||
| 840 | |||
| 841 | /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 842 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 | ||
| 843 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 | ||
| 844 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 | ||
| 845 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 | ||
| 846 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 | ||
| 847 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 | ||
| 848 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 | ||
| 849 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 | ||
| 850 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 | ||
| 851 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 | ||
| 852 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 | ||
| 853 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 | ||
| 854 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 | ||
| 855 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 | ||
| 856 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 | ||
| 857 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 | ||
| 858 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 | ||
| 859 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 | ||
| 860 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 | ||
| 861 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 | ||
| 862 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 | ||
| 863 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 | ||
| 864 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 | ||
| 865 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 | ||
| 866 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 | ||
| 867 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 | ||
| 868 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 | ||
| 869 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 | ||
| 870 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 | ||
| 871 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 | ||
| 872 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 | ||
| 873 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 | ||
| 874 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 | ||
| 875 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 | ||
| 876 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 | ||
| 877 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 | ||
| 878 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 | ||
| 879 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 | ||
| 880 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 | ||
| 881 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 | ||
| 882 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 | ||
| 883 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 | ||
| 884 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 | ||
| 885 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 | ||
| 886 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 | ||
| 887 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 | ||
| 888 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 | ||
| 889 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 | ||
| 890 | #define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 | ||
| 891 | |||
| 892 | /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ | ||
| 893 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 | ||
| 894 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 | ||
| 895 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 | ||
| 896 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 | ||
| 897 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 | ||
| 898 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 | ||
| 899 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 | ||
| 900 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 | ||
| 901 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 | ||
| 902 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 | ||
| 903 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 | ||
| 904 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 | ||
| 905 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 | ||
| 906 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 | ||
| 907 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 | ||
| 908 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 | ||
| 909 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 | ||
| 910 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 | ||
| 911 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 | ||
| 912 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 | ||
| 913 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 | ||
| 914 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 | ||
| 915 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 | ||
| 916 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 | ||
| 917 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 | ||
| 918 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 | ||
| 919 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 | ||
| 920 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 | ||
| 921 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 | ||
| 922 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 | ||
| 923 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 | ||
| 924 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 | ||
| 925 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 | ||
| 926 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 | ||
| 927 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 | ||
| 928 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 | ||
| 929 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 | ||
| 930 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 | ||
| 931 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 | ||
| 932 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 | ||
| 933 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 | ||
| 934 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 | ||
| 935 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 | ||
| 936 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 | ||
| 937 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 | ||
| 938 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 | ||
| 939 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 | ||
| 940 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 | ||
| 941 | #define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 | ||
| 942 | |||
| 943 | /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ | ||
| 944 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 | ||
| 945 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 | ||
| 946 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 | ||
| 947 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 | ||
| 948 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 | ||
| 949 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 | ||
| 950 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 | ||
| 951 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 | ||
| 952 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 | ||
| 953 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 | ||
| 954 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 | ||
| 955 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 | ||
| 956 | #define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 | ||
| 957 | |||
| 958 | /* Register r_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 959 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 | ||
| 960 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 | ||
| 961 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 | ||
| 962 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 | ||
| 963 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 | ||
| 964 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 | ||
| 965 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 | ||
| 966 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 | ||
| 967 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 | ||
| 968 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 | ||
| 969 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 | ||
| 970 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 | ||
| 971 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 | ||
| 972 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 | ||
| 973 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 | ||
| 974 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 | ||
| 975 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 | ||
| 976 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 | ||
| 977 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 | ||
| 978 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 | ||
| 979 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 | ||
| 980 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 | ||
| 981 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 | ||
| 982 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 | ||
| 983 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 | ||
| 984 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 | ||
| 985 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 | ||
| 986 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 | ||
| 987 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 | ||
| 988 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 | ||
| 989 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 | ||
| 990 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 | ||
| 991 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 | ||
| 992 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 | ||
| 993 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 | ||
| 994 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 | ||
| 995 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 | ||
| 996 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 | ||
| 997 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 | ||
| 998 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 | ||
| 999 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 | ||
| 1000 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 | ||
| 1001 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 | ||
| 1002 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 | ||
| 1003 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 | ||
| 1004 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 | ||
| 1005 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 | ||
| 1006 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 | ||
| 1007 | #define reg_iop_sw_mpu_r_intr_grp3_offset 140 | ||
| 1008 | |||
| 1009 | /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 1010 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 | ||
| 1011 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 | ||
| 1012 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 | ||
| 1013 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 | ||
| 1014 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 | ||
| 1015 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 | ||
| 1016 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 | ||
| 1017 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 | ||
| 1018 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 | ||
| 1019 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 | ||
| 1020 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 | ||
| 1021 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 | ||
| 1022 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 | ||
| 1023 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 | ||
| 1024 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 | ||
| 1025 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 | ||
| 1026 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 | ||
| 1027 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 | ||
| 1028 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 | ||
| 1029 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 | ||
| 1030 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 | ||
| 1031 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 | ||
| 1032 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 | ||
| 1033 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 | ||
| 1034 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 | ||
| 1035 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 | ||
| 1036 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 | ||
| 1037 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 | ||
| 1038 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 | ||
| 1039 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 | ||
| 1040 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 | ||
| 1041 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 | ||
| 1042 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 | ||
| 1043 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 | ||
| 1044 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 | ||
| 1045 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 | ||
| 1046 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 | ||
| 1047 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 | ||
| 1048 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 | ||
| 1049 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 | ||
| 1050 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 | ||
| 1051 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 | ||
| 1052 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 | ||
| 1053 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 | ||
| 1054 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 | ||
| 1055 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 | ||
| 1056 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 | ||
| 1057 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 | ||
| 1058 | #define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 | ||
| 1059 | |||
| 1060 | |||
| 1061 | /* Constants */ | ||
| 1062 | #define regk_iop_sw_mpu_copy 0x00000000 | ||
| 1063 | #define regk_iop_sw_mpu_cpu 0x00000000 | ||
| 1064 | #define regk_iop_sw_mpu_mpu 0x00000001 | ||
| 1065 | #define regk_iop_sw_mpu_no 0x00000000 | ||
| 1066 | #define regk_iop_sw_mpu_nop 0x00000000 | ||
| 1067 | #define regk_iop_sw_mpu_rd 0x00000002 | ||
| 1068 | #define regk_iop_sw_mpu_reg_copy 0x00000001 | ||
| 1069 | #define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 | ||
| 1070 | #define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 | ||
| 1071 | #define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 | ||
| 1072 | #define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 | ||
| 1073 | #define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 | ||
| 1074 | #define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 1075 | #define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 1076 | #define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 | ||
| 1077 | #define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 | ||
| 1078 | #define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 | ||
| 1079 | #define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 | ||
| 1080 | #define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 | ||
| 1081 | #define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 | ||
| 1082 | #define regk_iop_sw_mpu_set 0x00000001 | ||
| 1083 | #define regk_iop_sw_mpu_spu 0x00000002 | ||
| 1084 | #define regk_iop_sw_mpu_wr 0x00000003 | ||
| 1085 | #define regk_iop_sw_mpu_yes 0x00000001 | ||
| 1086 | #endif /* __iop_sw_mpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 67a745338087..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null | |||
| @@ -1,523 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_spu_defs_asm_h | ||
| 2 | #define __iop_sw_spu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_spu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_mpu_trace, scope iop_sw_spu, type r */ | ||
| 54 | #define reg_iop_sw_spu_r_mpu_trace_offset 0 | ||
| 55 | |||
| 56 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | ||
| 57 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 58 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 | ||
| 59 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 60 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 | ||
| 61 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 | ||
| 62 | #define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 | ||
| 63 | #define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 | ||
| 64 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
| 65 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
| 66 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
| 67 | #define reg_iop_sw_spu_rw_mc_ctrl_offset 4 | ||
| 68 | |||
| 69 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | ||
| 70 | #define reg_iop_sw_spu_rw_mc_data___val___lsb 0 | ||
| 71 | #define reg_iop_sw_spu_rw_mc_data___val___width 32 | ||
| 72 | #define reg_iop_sw_spu_rw_mc_data_offset 8 | ||
| 73 | |||
| 74 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | ||
| 75 | #define reg_iop_sw_spu_rw_mc_addr_offset 12 | ||
| 76 | |||
| 77 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | ||
| 78 | #define reg_iop_sw_spu_rs_mc_data_offset 16 | ||
| 79 | |||
| 80 | /* Register r_mc_data, scope iop_sw_spu, type r */ | ||
| 81 | #define reg_iop_sw_spu_r_mc_data_offset 20 | ||
| 82 | |||
| 83 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | ||
| 84 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 | ||
| 85 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 | ||
| 86 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 | ||
| 87 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 | ||
| 88 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 | ||
| 89 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 | ||
| 90 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 | ||
| 91 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 | ||
| 92 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 | ||
| 93 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 | ||
| 94 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 | ||
| 95 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 | ||
| 96 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 | ||
| 97 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 | ||
| 98 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 | ||
| 99 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 | ||
| 100 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 | ||
| 101 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 | ||
| 102 | #define reg_iop_sw_spu_r_mc_stat_offset 24 | ||
| 103 | |||
| 104 | /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ | ||
| 105 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 | ||
| 106 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 | ||
| 107 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 | ||
| 108 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 | ||
| 109 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 | ||
| 110 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 | ||
| 111 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 | ||
| 112 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 | ||
| 113 | #define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 | ||
| 114 | |||
| 115 | /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ | ||
| 116 | #define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 | ||
| 117 | #define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 | ||
| 118 | #define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 | ||
| 119 | #define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 | ||
| 120 | #define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 | ||
| 121 | #define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 | ||
| 122 | #define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 | ||
| 123 | #define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 | ||
| 124 | #define reg_iop_sw_spu_rw_bus_set_mask_offset 32 | ||
| 125 | |||
| 126 | /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 127 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
| 128 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 | ||
| 129 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
| 130 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
| 131 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 | ||
| 132 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
| 133 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
| 134 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 | ||
| 135 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
| 136 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
| 137 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 | ||
| 138 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
| 139 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 | ||
| 140 | |||
| 141 | /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 142 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
| 143 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 | ||
| 144 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 | ||
| 145 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
| 146 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 | ||
| 147 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 | ||
| 148 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
| 149 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 | ||
| 150 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 | ||
| 151 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
| 152 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 | ||
| 153 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 | ||
| 154 | #define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 | ||
| 155 | |||
| 156 | /* Register r_bus_in, scope iop_sw_spu, type r */ | ||
| 157 | #define reg_iop_sw_spu_r_bus_in_offset 44 | ||
| 158 | |||
| 159 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | ||
| 160 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 | ||
| 161 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 | ||
| 162 | #define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 | ||
| 163 | |||
| 164 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | ||
| 165 | #define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 | ||
| 166 | #define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 | ||
| 167 | #define reg_iop_sw_spu_rw_gio_set_mask_offset 52 | ||
| 168 | |||
| 169 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 170 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 171 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 | ||
| 172 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 | ||
| 173 | |||
| 174 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 175 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 176 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 | ||
| 177 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 | ||
| 178 | |||
| 179 | /* Register r_gio_in, scope iop_sw_spu, type r */ | ||
| 180 | #define reg_iop_sw_spu_r_gio_in_offset 64 | ||
| 181 | |||
| 182 | /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 183 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 | ||
| 184 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 | ||
| 185 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 | ||
| 186 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 | ||
| 187 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 | ||
| 188 | |||
| 189 | /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 190 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 | ||
| 191 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 | ||
| 192 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 | ||
| 193 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 | ||
| 194 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 | ||
| 195 | |||
| 196 | /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 197 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 | ||
| 198 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 | ||
| 199 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 | ||
| 200 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 | ||
| 201 | #define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 | ||
| 202 | |||
| 203 | /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 204 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 | ||
| 205 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 | ||
| 206 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 | ||
| 207 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 | ||
| 208 | #define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 | ||
| 209 | |||
| 210 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 211 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 | ||
| 212 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 | ||
| 213 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 | ||
| 214 | |||
| 215 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 216 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 | ||
| 217 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 | ||
| 218 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 | ||
| 219 | |||
| 220 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 221 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 | ||
| 222 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 | ||
| 223 | #define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 | ||
| 224 | |||
| 225 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 226 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 | ||
| 227 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 | ||
| 228 | #define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 | ||
| 229 | |||
| 230 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 231 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 | ||
| 232 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 | ||
| 233 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 | ||
| 234 | |||
| 235 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 236 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 | ||
| 237 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 | ||
| 238 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 | ||
| 239 | |||
| 240 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 241 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 | ||
| 242 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 | ||
| 243 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 | ||
| 244 | |||
| 245 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 246 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 | ||
| 247 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 | ||
| 248 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 | ||
| 249 | |||
| 250 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | ||
| 251 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 | ||
| 252 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 | ||
| 253 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 | ||
| 254 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 | ||
| 255 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 | ||
| 256 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 | ||
| 257 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 | ||
| 258 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 | ||
| 259 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 | ||
| 260 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 | ||
| 261 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 | ||
| 262 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 | ||
| 263 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 | ||
| 264 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 | ||
| 265 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 | ||
| 266 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 | ||
| 267 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 | ||
| 268 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 | ||
| 269 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 | ||
| 270 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 | ||
| 271 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 | ||
| 272 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 | ||
| 273 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 | ||
| 274 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 | ||
| 275 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 | ||
| 276 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 | ||
| 277 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 | ||
| 278 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 | ||
| 279 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 | ||
| 280 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 | ||
| 281 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 | ||
| 282 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 | ||
| 283 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 | ||
| 284 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 | ||
| 285 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 | ||
| 286 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 | ||
| 287 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 | ||
| 288 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 | ||
| 289 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 | ||
| 290 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 | ||
| 291 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 | ||
| 292 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 | ||
| 293 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 | ||
| 294 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 | ||
| 295 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 | ||
| 296 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 | ||
| 297 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 | ||
| 298 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 | ||
| 299 | #define reg_iop_sw_spu_rw_cpu_intr_offset 116 | ||
| 300 | |||
| 301 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | ||
| 302 | #define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 | ||
| 303 | #define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 | ||
| 304 | #define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 | ||
| 305 | #define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 | ||
| 306 | #define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 | ||
| 307 | #define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 | ||
| 308 | #define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 | ||
| 309 | #define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 | ||
| 310 | #define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 | ||
| 311 | #define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 | ||
| 312 | #define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 | ||
| 313 | #define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 | ||
| 314 | #define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 | ||
| 315 | #define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 | ||
| 316 | #define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 | ||
| 317 | #define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 | ||
| 318 | #define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 | ||
| 319 | #define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 | ||
| 320 | #define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 | ||
| 321 | #define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 | ||
| 322 | #define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 | ||
| 323 | #define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 | ||
| 324 | #define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 | ||
| 325 | #define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 | ||
| 326 | #define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 | ||
| 327 | #define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 | ||
| 328 | #define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 | ||
| 329 | #define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 | ||
| 330 | #define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 | ||
| 331 | #define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 | ||
| 332 | #define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 | ||
| 333 | #define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 | ||
| 334 | #define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 | ||
| 335 | #define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 | ||
| 336 | #define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 | ||
| 337 | #define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 | ||
| 338 | #define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 | ||
| 339 | #define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 | ||
| 340 | #define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 | ||
| 341 | #define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 | ||
| 342 | #define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 | ||
| 343 | #define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 | ||
| 344 | #define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 | ||
| 345 | #define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 | ||
| 346 | #define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 | ||
| 347 | #define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 | ||
| 348 | #define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 | ||
| 349 | #define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 | ||
| 350 | #define reg_iop_sw_spu_r_cpu_intr_offset 120 | ||
| 351 | |||
| 352 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | ||
| 353 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 | ||
| 354 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 | ||
| 355 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 | ||
| 356 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 | ||
| 357 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 | ||
| 358 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 | ||
| 359 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 | ||
| 360 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 | ||
| 361 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 | ||
| 362 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 | ||
| 363 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 | ||
| 364 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 | ||
| 365 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 | ||
| 366 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 | ||
| 367 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 | ||
| 368 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 | ||
| 369 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 | ||
| 370 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 | ||
| 371 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 | ||
| 372 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 | ||
| 373 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 | ||
| 374 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 | ||
| 375 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 | ||
| 376 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 | ||
| 377 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 | ||
| 378 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 | ||
| 379 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 | ||
| 380 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 | ||
| 381 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 | ||
| 382 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 | ||
| 383 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 | ||
| 384 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 | ||
| 385 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 | ||
| 386 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 | ||
| 387 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 | ||
| 388 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 | ||
| 389 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 | ||
| 390 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 | ||
| 391 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 | ||
| 392 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 | ||
| 393 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 | ||
| 394 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 | ||
| 395 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 | ||
| 396 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 | ||
| 397 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 | ||
| 398 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 | ||
| 399 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 | ||
| 400 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 | ||
| 401 | #define reg_iop_sw_spu_r_hw_intr_offset 124 | ||
| 402 | |||
| 403 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | ||
| 404 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 | ||
| 405 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 | ||
| 406 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 | ||
| 407 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 | ||
| 408 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 | ||
| 409 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 | ||
| 410 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 | ||
| 411 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 | ||
| 412 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 | ||
| 413 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 | ||
| 414 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 | ||
| 415 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 | ||
| 416 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 | ||
| 417 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 | ||
| 418 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 | ||
| 419 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 | ||
| 420 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 | ||
| 421 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 | ||
| 422 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 | ||
| 423 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 | ||
| 424 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 | ||
| 425 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 | ||
| 426 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 | ||
| 427 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 | ||
| 428 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 | ||
| 429 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 | ||
| 430 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 | ||
| 431 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 | ||
| 432 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 | ||
| 433 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 | ||
| 434 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 | ||
| 435 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 | ||
| 436 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 | ||
| 437 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 | ||
| 438 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 | ||
| 439 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 | ||
| 440 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 | ||
| 441 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 | ||
| 442 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 | ||
| 443 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 | ||
| 444 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 | ||
| 445 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 | ||
| 446 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 | ||
| 447 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 | ||
| 448 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 | ||
| 449 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 | ||
| 450 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 | ||
| 451 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 | ||
| 452 | #define reg_iop_sw_spu_rw_mpu_intr_offset 128 | ||
| 453 | |||
| 454 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | ||
| 455 | #define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 | ||
| 456 | #define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 | ||
| 457 | #define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 | ||
| 458 | #define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 | ||
| 459 | #define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 | ||
| 460 | #define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 | ||
| 461 | #define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 | ||
| 462 | #define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 | ||
| 463 | #define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 | ||
| 464 | #define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 | ||
| 465 | #define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 | ||
| 466 | #define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 | ||
| 467 | #define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 | ||
| 468 | #define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 | ||
| 469 | #define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 | ||
| 470 | #define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 | ||
| 471 | #define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 | ||
| 472 | #define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 | ||
| 473 | #define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 | ||
| 474 | #define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 | ||
| 475 | #define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 | ||
| 476 | #define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 | ||
| 477 | #define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 | ||
| 478 | #define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 | ||
| 479 | #define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 | ||
| 480 | #define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 | ||
| 481 | #define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 | ||
| 482 | #define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 | ||
| 483 | #define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 | ||
| 484 | #define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 | ||
| 485 | #define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 | ||
| 486 | #define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 | ||
| 487 | #define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 | ||
| 488 | #define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 | ||
| 489 | #define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 | ||
| 490 | #define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 | ||
| 491 | #define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 | ||
| 492 | #define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 | ||
| 493 | #define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 | ||
| 494 | #define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 | ||
| 495 | #define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 | ||
| 496 | #define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 | ||
| 497 | #define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 | ||
| 498 | #define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 | ||
| 499 | #define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 | ||
| 500 | #define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 | ||
| 501 | #define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 | ||
| 502 | #define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 | ||
| 503 | #define reg_iop_sw_spu_r_mpu_intr_offset 132 | ||
| 504 | |||
| 505 | |||
| 506 | /* Constants */ | ||
| 507 | #define regk_iop_sw_spu_copy 0x00000000 | ||
| 508 | #define regk_iop_sw_spu_no 0x00000000 | ||
| 509 | #define regk_iop_sw_spu_nop 0x00000000 | ||
| 510 | #define regk_iop_sw_spu_rd 0x00000002 | ||
| 511 | #define regk_iop_sw_spu_reg_copy 0x00000001 | ||
| 512 | #define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 | ||
| 513 | #define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 | ||
| 514 | #define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 | ||
| 515 | #define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 | ||
| 516 | #define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 | ||
| 517 | #define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 518 | #define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 519 | #define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 | ||
| 520 | #define regk_iop_sw_spu_set 0x00000001 | ||
| 521 | #define regk_iop_sw_spu_wr 0x00000003 | ||
| 522 | #define regk_iop_sw_spu_yes 0x00000001 | ||
| 523 | #endif /* __iop_sw_spu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index 4ad671202af0..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | #ifndef __iop_version_defs_asm_h | ||
| 2 | #define __iop_version_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_version.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_version, scope iop_version, type r */ | ||
| 54 | #define reg_iop_version_r_version___nr___lsb 0 | ||
| 55 | #define reg_iop_version_r_version___nr___width 8 | ||
| 56 | #define reg_iop_version_r_version_offset 0 | ||
| 57 | |||
| 58 | |||
| 59 | /* Constants */ | ||
| 60 | #define regk_iop_version_v2_0 0x00000002 | ||
| 61 | #endif /* __iop_version_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h deleted file mode 100644 index af3196c60a46..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* Autogenerated Changes here will be lost! | ||
| 2 | * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg | ||
| 3 | */ | ||
| 4 | #define regi_iop_version (regi_iop + 0) | ||
| 5 | #define regi_iop_fifo_in_extra (regi_iop + 64) | ||
| 6 | #define regi_iop_fifo_out_extra (regi_iop + 128) | ||
| 7 | #define regi_iop_trigger_grp0 (regi_iop + 192) | ||
| 8 | #define regi_iop_trigger_grp1 (regi_iop + 256) | ||
| 9 | #define regi_iop_trigger_grp2 (regi_iop + 320) | ||
| 10 | #define regi_iop_trigger_grp3 (regi_iop + 384) | ||
| 11 | #define regi_iop_trigger_grp4 (regi_iop + 448) | ||
| 12 | #define regi_iop_trigger_grp5 (regi_iop + 512) | ||
| 13 | #define regi_iop_trigger_grp6 (regi_iop + 576) | ||
| 14 | #define regi_iop_trigger_grp7 (regi_iop + 640) | ||
| 15 | #define regi_iop_crc_par (regi_iop + 768) | ||
| 16 | #define regi_iop_dmc_in (regi_iop + 896) | ||
| 17 | #define regi_iop_dmc_out (regi_iop + 1024) | ||
| 18 | #define regi_iop_fifo_in (regi_iop + 1152) | ||
| 19 | #define regi_iop_fifo_out (regi_iop + 1280) | ||
| 20 | #define regi_iop_scrc_in (regi_iop + 1408) | ||
| 21 | #define regi_iop_scrc_out (regi_iop + 1536) | ||
| 22 | #define regi_iop_timer_grp0 (regi_iop + 1664) | ||
| 23 | #define regi_iop_timer_grp1 (regi_iop + 1792) | ||
| 24 | #define regi_iop_sap_in (regi_iop + 2048) | ||
| 25 | #define regi_iop_sap_out (regi_iop + 2304) | ||
| 26 | #define regi_iop_spu (regi_iop + 2560) | ||
| 27 | #define regi_iop_sw_cfg (regi_iop + 2816) | ||
| 28 | #define regi_iop_sw_cpu (regi_iop + 3072) | ||
| 29 | #define regi_iop_sw_mpu (regi_iop + 3328) | ||
| 30 | #define regi_iop_sw_spu (regi_iop + 3584) | ||
| 31 | #define regi_iop_mpu (regi_iop + 4096) | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 51dde016c03a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h +++ /dev/null | |||
| @@ -1,141 +0,0 @@ | |||
| 1 | #ifndef __iop_sap_in_defs_h | ||
| 2 | #define __iop_sap_in_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sap_in.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sap_in */ | ||
| 83 | |||
| 84 | #define STRIDE_iop_sap_in_rw_bus_byte 4 | ||
| 85 | /* Register rw_bus_byte, scope iop_sap_in, type rw */ | ||
| 86 | typedef struct { | ||
| 87 | unsigned int sync_sel : 2; | ||
| 88 | unsigned int sync_ext_src : 3; | ||
| 89 | unsigned int sync_edge : 2; | ||
| 90 | unsigned int delay : 2; | ||
| 91 | unsigned int dummy1 : 23; | ||
| 92 | } reg_iop_sap_in_rw_bus_byte; | ||
| 93 | #define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 | ||
| 94 | #define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 | ||
| 95 | |||
| 96 | #define STRIDE_iop_sap_in_rw_gio 4 | ||
| 97 | /* Register rw_gio, scope iop_sap_in, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int sync_sel : 2; | ||
| 100 | unsigned int sync_ext_src : 3; | ||
| 101 | unsigned int sync_edge : 2; | ||
| 102 | unsigned int delay : 2; | ||
| 103 | unsigned int logic : 2; | ||
| 104 | unsigned int dummy1 : 21; | ||
| 105 | } reg_iop_sap_in_rw_gio; | ||
| 106 | #define REG_RD_ADDR_iop_sap_in_rw_gio 16 | ||
| 107 | #define REG_WR_ADDR_iop_sap_in_rw_gio 16 | ||
| 108 | |||
| 109 | |||
| 110 | /* Constants */ | ||
| 111 | enum { | ||
| 112 | regk_iop_sap_in_and = 0x00000002, | ||
| 113 | regk_iop_sap_in_ext_clk200 = 0x00000003, | ||
| 114 | regk_iop_sap_in_gio0 = 0x00000000, | ||
| 115 | regk_iop_sap_in_gio12 = 0x00000003, | ||
| 116 | regk_iop_sap_in_gio16 = 0x00000004, | ||
| 117 | regk_iop_sap_in_gio20 = 0x00000005, | ||
| 118 | regk_iop_sap_in_gio24 = 0x00000006, | ||
| 119 | regk_iop_sap_in_gio28 = 0x00000007, | ||
| 120 | regk_iop_sap_in_gio4 = 0x00000001, | ||
| 121 | regk_iop_sap_in_gio8 = 0x00000002, | ||
| 122 | regk_iop_sap_in_inv = 0x00000001, | ||
| 123 | regk_iop_sap_in_neg = 0x00000002, | ||
| 124 | regk_iop_sap_in_no = 0x00000000, | ||
| 125 | regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, | ||
| 126 | regk_iop_sap_in_none = 0x00000000, | ||
| 127 | regk_iop_sap_in_one = 0x00000001, | ||
| 128 | regk_iop_sap_in_or = 0x00000003, | ||
| 129 | regk_iop_sap_in_pos = 0x00000001, | ||
| 130 | regk_iop_sap_in_pos_neg = 0x00000003, | ||
| 131 | regk_iop_sap_in_rw_bus_byte_default = 0x00000000, | ||
| 132 | regk_iop_sap_in_rw_bus_byte_size = 0x00000004, | ||
| 133 | regk_iop_sap_in_rw_gio_default = 0x00000000, | ||
| 134 | regk_iop_sap_in_rw_gio_size = 0x00000020, | ||
| 135 | regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, | ||
| 136 | regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, | ||
| 137 | regk_iop_sap_in_tmr_clk200 = 0x00000001, | ||
| 138 | regk_iop_sap_in_two = 0x00000002, | ||
| 139 | regk_iop_sap_in_two_clk200 = 0x00000000 | ||
| 140 | }; | ||
| 141 | #endif /* __iop_sap_in_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 5af88baa2ac1..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h +++ /dev/null | |||
| @@ -1,231 +0,0 @@ | |||
| 1 | #ifndef __iop_sap_out_defs_h | ||
| 2 | #define __iop_sap_out_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sap_out.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sap_out */ | ||
| 83 | |||
| 84 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int clk0_src : 2; | ||
| 87 | unsigned int clk0_gate_src : 2; | ||
| 88 | unsigned int clk0_force_src : 3; | ||
| 89 | unsigned int clk1_src : 2; | ||
| 90 | unsigned int clk1_gate_src : 2; | ||
| 91 | unsigned int clk1_force_src : 3; | ||
| 92 | unsigned int dummy1 : 18; | ||
| 93 | } reg_iop_sap_out_rw_gen_gated; | ||
| 94 | #define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 | ||
| 95 | #define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 | ||
| 96 | |||
| 97 | /* Register rw_bus, scope iop_sap_out, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int byte0_clk_sel : 2; | ||
| 100 | unsigned int byte0_clk_ext : 2; | ||
| 101 | unsigned int byte0_gated_clk : 1; | ||
| 102 | unsigned int byte0_clk_inv : 1; | ||
| 103 | unsigned int byte0_delay : 1; | ||
| 104 | unsigned int byte1_clk_sel : 2; | ||
| 105 | unsigned int byte1_clk_ext : 2; | ||
| 106 | unsigned int byte1_gated_clk : 1; | ||
| 107 | unsigned int byte1_clk_inv : 1; | ||
| 108 | unsigned int byte1_delay : 1; | ||
| 109 | unsigned int byte2_clk_sel : 2; | ||
| 110 | unsigned int byte2_clk_ext : 2; | ||
| 111 | unsigned int byte2_gated_clk : 1; | ||
| 112 | unsigned int byte2_clk_inv : 1; | ||
| 113 | unsigned int byte2_delay : 1; | ||
| 114 | unsigned int byte3_clk_sel : 2; | ||
| 115 | unsigned int byte3_clk_ext : 2; | ||
| 116 | unsigned int byte3_gated_clk : 1; | ||
| 117 | unsigned int byte3_clk_inv : 1; | ||
| 118 | unsigned int byte3_delay : 1; | ||
| 119 | unsigned int dummy1 : 4; | ||
| 120 | } reg_iop_sap_out_rw_bus; | ||
| 121 | #define REG_RD_ADDR_iop_sap_out_rw_bus 4 | ||
| 122 | #define REG_WR_ADDR_iop_sap_out_rw_bus 4 | ||
| 123 | |||
| 124 | /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ | ||
| 125 | typedef struct { | ||
| 126 | unsigned int byte0_clk_sel : 2; | ||
| 127 | unsigned int byte0_clk_ext : 2; | ||
| 128 | unsigned int byte0_gated_clk : 1; | ||
| 129 | unsigned int byte0_clk_inv : 1; | ||
| 130 | unsigned int byte0_delay : 1; | ||
| 131 | unsigned int byte0_logic : 2; | ||
| 132 | unsigned int byte0_logic_src : 2; | ||
| 133 | unsigned int byte1_clk_sel : 2; | ||
| 134 | unsigned int byte1_clk_ext : 2; | ||
| 135 | unsigned int byte1_gated_clk : 1; | ||
| 136 | unsigned int byte1_clk_inv : 1; | ||
| 137 | unsigned int byte1_delay : 1; | ||
| 138 | unsigned int byte1_logic : 2; | ||
| 139 | unsigned int byte1_logic_src : 2; | ||
| 140 | unsigned int dummy1 : 10; | ||
| 141 | } reg_iop_sap_out_rw_bus_lo_oe; | ||
| 142 | #define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 | ||
| 143 | #define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 | ||
| 144 | |||
| 145 | /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ | ||
| 146 | typedef struct { | ||
| 147 | unsigned int byte2_clk_sel : 2; | ||
| 148 | unsigned int byte2_clk_ext : 2; | ||
| 149 | unsigned int byte2_gated_clk : 1; | ||
| 150 | unsigned int byte2_clk_inv : 1; | ||
| 151 | unsigned int byte2_delay : 1; | ||
| 152 | unsigned int byte2_logic : 2; | ||
| 153 | unsigned int byte2_logic_src : 2; | ||
| 154 | unsigned int byte3_clk_sel : 2; | ||
| 155 | unsigned int byte3_clk_ext : 2; | ||
| 156 | unsigned int byte3_gated_clk : 1; | ||
| 157 | unsigned int byte3_clk_inv : 1; | ||
| 158 | unsigned int byte3_delay : 1; | ||
| 159 | unsigned int byte3_logic : 2; | ||
| 160 | unsigned int byte3_logic_src : 2; | ||
| 161 | unsigned int dummy1 : 10; | ||
| 162 | } reg_iop_sap_out_rw_bus_hi_oe; | ||
| 163 | #define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 | ||
| 164 | #define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 | ||
| 165 | |||
| 166 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
| 167 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int out_clk_sel : 3; | ||
| 170 | unsigned int out_clk_ext : 2; | ||
| 171 | unsigned int out_gated_clk : 1; | ||
| 172 | unsigned int out_clk_inv : 1; | ||
| 173 | unsigned int out_delay : 1; | ||
| 174 | unsigned int out_logic : 2; | ||
| 175 | unsigned int out_logic_src : 2; | ||
| 176 | unsigned int oe_clk_sel : 3; | ||
| 177 | unsigned int oe_clk_ext : 2; | ||
| 178 | unsigned int oe_gated_clk : 1; | ||
| 179 | unsigned int oe_clk_inv : 1; | ||
| 180 | unsigned int oe_delay : 1; | ||
| 181 | unsigned int oe_logic : 2; | ||
| 182 | unsigned int oe_logic_src : 2; | ||
| 183 | unsigned int dummy1 : 8; | ||
| 184 | } reg_iop_sap_out_rw_gio; | ||
| 185 | #define REG_RD_ADDR_iop_sap_out_rw_gio 16 | ||
| 186 | #define REG_WR_ADDR_iop_sap_out_rw_gio 16 | ||
| 187 | |||
| 188 | |||
| 189 | /* Constants */ | ||
| 190 | enum { | ||
| 191 | regk_iop_sap_out_always = 0x00000001, | ||
| 192 | regk_iop_sap_out_and = 0x00000002, | ||
| 193 | regk_iop_sap_out_clk0 = 0x00000000, | ||
| 194 | regk_iop_sap_out_clk1 = 0x00000001, | ||
| 195 | regk_iop_sap_out_clk12 = 0x00000004, | ||
| 196 | regk_iop_sap_out_clk200 = 0x00000000, | ||
| 197 | regk_iop_sap_out_ext = 0x00000002, | ||
| 198 | regk_iop_sap_out_gated = 0x00000003, | ||
| 199 | regk_iop_sap_out_gio0 = 0x00000000, | ||
| 200 | regk_iop_sap_out_gio1 = 0x00000000, | ||
| 201 | regk_iop_sap_out_gio16 = 0x00000002, | ||
| 202 | regk_iop_sap_out_gio17 = 0x00000002, | ||
| 203 | regk_iop_sap_out_gio24 = 0x00000003, | ||
| 204 | regk_iop_sap_out_gio25 = 0x00000003, | ||
| 205 | regk_iop_sap_out_gio8 = 0x00000001, | ||
| 206 | regk_iop_sap_out_gio9 = 0x00000001, | ||
| 207 | regk_iop_sap_out_gio_out10 = 0x00000005, | ||
| 208 | regk_iop_sap_out_gio_out18 = 0x00000006, | ||
| 209 | regk_iop_sap_out_gio_out2 = 0x00000004, | ||
| 210 | regk_iop_sap_out_gio_out26 = 0x00000007, | ||
| 211 | regk_iop_sap_out_inv = 0x00000001, | ||
| 212 | regk_iop_sap_out_nand = 0x00000003, | ||
| 213 | regk_iop_sap_out_no = 0x00000000, | ||
| 214 | regk_iop_sap_out_none = 0x00000000, | ||
| 215 | regk_iop_sap_out_one = 0x00000001, | ||
| 216 | regk_iop_sap_out_rw_bus_default = 0x00000000, | ||
| 217 | regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, | ||
| 218 | regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, | ||
| 219 | regk_iop_sap_out_rw_gen_gated_default = 0x00000000, | ||
| 220 | regk_iop_sap_out_rw_gio_default = 0x00000000, | ||
| 221 | regk_iop_sap_out_rw_gio_size = 0x00000020, | ||
| 222 | regk_iop_sap_out_spu_gio6 = 0x00000002, | ||
| 223 | regk_iop_sap_out_spu_gio7 = 0x00000003, | ||
| 224 | regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, | ||
| 225 | regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, | ||
| 226 | regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, | ||
| 227 | regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, | ||
| 228 | regk_iop_sap_out_tmr200 = 0x00000001, | ||
| 229 | regk_iop_sap_out_yes = 0x00000001 | ||
| 230 | }; | ||
| 231 | #endif /* __iop_sap_out_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index 98ac95275a1c..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null | |||
| @@ -1,725 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_cfg_defs_h | ||
| 2 | #define __iop_sw_cfg_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_cfg.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sw_cfg */ | ||
| 83 | |||
| 84 | /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int cfg : 2; | ||
| 87 | unsigned int dummy1 : 30; | ||
| 88 | } reg_iop_sw_cfg_rw_crc_par_owner; | ||
| 89 | #define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 | ||
| 90 | #define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 | ||
| 91 | |||
| 92 | /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ | ||
| 93 | typedef struct { | ||
| 94 | unsigned int cfg : 2; | ||
| 95 | unsigned int dummy1 : 30; | ||
| 96 | } reg_iop_sw_cfg_rw_dmc_in_owner; | ||
| 97 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 | ||
| 98 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 | ||
| 99 | |||
| 100 | /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ | ||
| 101 | typedef struct { | ||
| 102 | unsigned int cfg : 2; | ||
| 103 | unsigned int dummy1 : 30; | ||
| 104 | } reg_iop_sw_cfg_rw_dmc_out_owner; | ||
| 105 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 | ||
| 106 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 | ||
| 107 | |||
| 108 | /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ | ||
| 109 | typedef struct { | ||
| 110 | unsigned int cfg : 2; | ||
| 111 | unsigned int dummy1 : 30; | ||
| 112 | } reg_iop_sw_cfg_rw_fifo_in_owner; | ||
| 113 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 | ||
| 114 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 | ||
| 115 | |||
| 116 | /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 117 | typedef struct { | ||
| 118 | unsigned int cfg : 2; | ||
| 119 | unsigned int dummy1 : 30; | ||
| 120 | } reg_iop_sw_cfg_rw_fifo_in_extra_owner; | ||
| 121 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 | ||
| 122 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 | ||
| 123 | |||
| 124 | /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ | ||
| 125 | typedef struct { | ||
| 126 | unsigned int cfg : 2; | ||
| 127 | unsigned int dummy1 : 30; | ||
| 128 | } reg_iop_sw_cfg_rw_fifo_out_owner; | ||
| 129 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 | ||
| 130 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 | ||
| 131 | |||
| 132 | /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 133 | typedef struct { | ||
| 134 | unsigned int cfg : 2; | ||
| 135 | unsigned int dummy1 : 30; | ||
| 136 | } reg_iop_sw_cfg_rw_fifo_out_extra_owner; | ||
| 137 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 | ||
| 138 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 | ||
| 139 | |||
| 140 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | ||
| 141 | typedef struct { | ||
| 142 | unsigned int cfg : 2; | ||
| 143 | unsigned int dummy1 : 30; | ||
| 144 | } reg_iop_sw_cfg_rw_sap_in_owner; | ||
| 145 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 | ||
| 146 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 | ||
| 147 | |||
| 148 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | ||
| 149 | typedef struct { | ||
| 150 | unsigned int cfg : 2; | ||
| 151 | unsigned int dummy1 : 30; | ||
| 152 | } reg_iop_sw_cfg_rw_sap_out_owner; | ||
| 153 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 | ||
| 154 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 | ||
| 155 | |||
| 156 | /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int cfg : 2; | ||
| 159 | unsigned int dummy1 : 30; | ||
| 160 | } reg_iop_sw_cfg_rw_scrc_in_owner; | ||
| 161 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 | ||
| 162 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 | ||
| 163 | |||
| 164 | /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ | ||
| 165 | typedef struct { | ||
| 166 | unsigned int cfg : 2; | ||
| 167 | unsigned int dummy1 : 30; | ||
| 168 | } reg_iop_sw_cfg_rw_scrc_out_owner; | ||
| 169 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 | ||
| 170 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 | ||
| 171 | |||
| 172 | /* Register rw_spu_owner, scope iop_sw_cfg, type rw */ | ||
| 173 | typedef struct { | ||
| 174 | unsigned int cfg : 1; | ||
| 175 | unsigned int dummy1 : 31; | ||
| 176 | } reg_iop_sw_cfg_rw_spu_owner; | ||
| 177 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 | ||
| 178 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 | ||
| 179 | |||
| 180 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 181 | typedef struct { | ||
| 182 | unsigned int cfg : 2; | ||
| 183 | unsigned int dummy1 : 30; | ||
| 184 | } reg_iop_sw_cfg_rw_timer_grp0_owner; | ||
| 185 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 | ||
| 186 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 | ||
| 187 | |||
| 188 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 189 | typedef struct { | ||
| 190 | unsigned int cfg : 2; | ||
| 191 | unsigned int dummy1 : 30; | ||
| 192 | } reg_iop_sw_cfg_rw_timer_grp1_owner; | ||
| 193 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 | ||
| 194 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 | ||
| 195 | |||
| 196 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int cfg : 2; | ||
| 199 | unsigned int dummy1 : 30; | ||
| 200 | } reg_iop_sw_cfg_rw_trigger_grp0_owner; | ||
| 201 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 | ||
| 202 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 | ||
| 203 | |||
| 204 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int cfg : 2; | ||
| 207 | unsigned int dummy1 : 30; | ||
| 208 | } reg_iop_sw_cfg_rw_trigger_grp1_owner; | ||
| 209 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 | ||
| 210 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 | ||
| 211 | |||
| 212 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | ||
| 213 | typedef struct { | ||
| 214 | unsigned int cfg : 2; | ||
| 215 | unsigned int dummy1 : 30; | ||
| 216 | } reg_iop_sw_cfg_rw_trigger_grp2_owner; | ||
| 217 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 | ||
| 218 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 | ||
| 219 | |||
| 220 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int cfg : 2; | ||
| 223 | unsigned int dummy1 : 30; | ||
| 224 | } reg_iop_sw_cfg_rw_trigger_grp3_owner; | ||
| 225 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 | ||
| 226 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 | ||
| 227 | |||
| 228 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int cfg : 2; | ||
| 231 | unsigned int dummy1 : 30; | ||
| 232 | } reg_iop_sw_cfg_rw_trigger_grp4_owner; | ||
| 233 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 | ||
| 234 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 | ||
| 235 | |||
| 236 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int cfg : 2; | ||
| 239 | unsigned int dummy1 : 30; | ||
| 240 | } reg_iop_sw_cfg_rw_trigger_grp5_owner; | ||
| 241 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 | ||
| 242 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 | ||
| 243 | |||
| 244 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | ||
| 245 | typedef struct { | ||
| 246 | unsigned int cfg : 2; | ||
| 247 | unsigned int dummy1 : 30; | ||
| 248 | } reg_iop_sw_cfg_rw_trigger_grp6_owner; | ||
| 249 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 | ||
| 250 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 | ||
| 251 | |||
| 252 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int cfg : 2; | ||
| 255 | unsigned int dummy1 : 30; | ||
| 256 | } reg_iop_sw_cfg_rw_trigger_grp7_owner; | ||
| 257 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 | ||
| 258 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 | ||
| 259 | |||
| 260 | /* Register rw_bus_mask, scope iop_sw_cfg, type rw */ | ||
| 261 | typedef struct { | ||
| 262 | unsigned int byte0 : 8; | ||
| 263 | unsigned int byte1 : 8; | ||
| 264 | unsigned int byte2 : 8; | ||
| 265 | unsigned int byte3 : 8; | ||
| 266 | } reg_iop_sw_cfg_rw_bus_mask; | ||
| 267 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 | ||
| 268 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 | ||
| 269 | |||
| 270 | /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 271 | typedef struct { | ||
| 272 | unsigned int byte0 : 1; | ||
| 273 | unsigned int byte1 : 1; | ||
| 274 | unsigned int byte2 : 1; | ||
| 275 | unsigned int byte3 : 1; | ||
| 276 | unsigned int dummy1 : 28; | ||
| 277 | } reg_iop_sw_cfg_rw_bus_oe_mask; | ||
| 278 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 | ||
| 279 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 | ||
| 280 | |||
| 281 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | ||
| 282 | typedef struct { | ||
| 283 | unsigned int val : 32; | ||
| 284 | } reg_iop_sw_cfg_rw_gio_mask; | ||
| 285 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 | ||
| 286 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 | ||
| 287 | |||
| 288 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 289 | typedef struct { | ||
| 290 | unsigned int val : 32; | ||
| 291 | } reg_iop_sw_cfg_rw_gio_oe_mask; | ||
| 292 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 | ||
| 293 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 | ||
| 294 | |||
| 295 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | ||
| 296 | typedef struct { | ||
| 297 | unsigned int bus_byte0 : 2; | ||
| 298 | unsigned int bus_byte1 : 2; | ||
| 299 | unsigned int bus_byte2 : 2; | ||
| 300 | unsigned int bus_byte3 : 2; | ||
| 301 | unsigned int gio3_0 : 2; | ||
| 302 | unsigned int gio7_4 : 2; | ||
| 303 | unsigned int gio11_8 : 2; | ||
| 304 | unsigned int gio15_12 : 2; | ||
| 305 | unsigned int gio19_16 : 2; | ||
| 306 | unsigned int gio23_20 : 2; | ||
| 307 | unsigned int gio27_24 : 2; | ||
| 308 | unsigned int gio31_28 : 2; | ||
| 309 | unsigned int dummy1 : 8; | ||
| 310 | } reg_iop_sw_cfg_rw_pinmapping; | ||
| 311 | #define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 | ||
| 312 | #define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 | ||
| 313 | |||
| 314 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | ||
| 315 | typedef struct { | ||
| 316 | unsigned int bus_lo : 2; | ||
| 317 | unsigned int bus_hi : 2; | ||
| 318 | unsigned int bus_lo_oe : 2; | ||
| 319 | unsigned int bus_hi_oe : 2; | ||
| 320 | unsigned int dummy1 : 24; | ||
| 321 | } reg_iop_sw_cfg_rw_bus_out_cfg; | ||
| 322 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 | ||
| 323 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 | ||
| 324 | |||
| 325 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 326 | typedef struct { | ||
| 327 | unsigned int gio0 : 3; | ||
| 328 | unsigned int gio0_oe : 1; | ||
| 329 | unsigned int gio1 : 3; | ||
| 330 | unsigned int gio1_oe : 1; | ||
| 331 | unsigned int gio2 : 3; | ||
| 332 | unsigned int gio2_oe : 1; | ||
| 333 | unsigned int gio3 : 3; | ||
| 334 | unsigned int gio3_oe : 1; | ||
| 335 | unsigned int dummy1 : 16; | ||
| 336 | } reg_iop_sw_cfg_rw_gio_out_grp0_cfg; | ||
| 337 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 | ||
| 338 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 | ||
| 339 | |||
| 340 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 341 | typedef struct { | ||
| 342 | unsigned int gio4 : 3; | ||
| 343 | unsigned int gio4_oe : 1; | ||
| 344 | unsigned int gio5 : 3; | ||
| 345 | unsigned int gio5_oe : 1; | ||
| 346 | unsigned int gio6 : 3; | ||
| 347 | unsigned int gio6_oe : 1; | ||
| 348 | unsigned int gio7 : 3; | ||
| 349 | unsigned int gio7_oe : 1; | ||
| 350 | unsigned int dummy1 : 16; | ||
| 351 | } reg_iop_sw_cfg_rw_gio_out_grp1_cfg; | ||
| 352 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 | ||
| 353 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 | ||
| 354 | |||
| 355 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
| 356 | typedef struct { | ||
| 357 | unsigned int gio8 : 3; | ||
| 358 | unsigned int gio8_oe : 1; | ||
| 359 | unsigned int gio9 : 3; | ||
| 360 | unsigned int gio9_oe : 1; | ||
| 361 | unsigned int gio10 : 3; | ||
| 362 | unsigned int gio10_oe : 1; | ||
| 363 | unsigned int gio11 : 3; | ||
| 364 | unsigned int gio11_oe : 1; | ||
| 365 | unsigned int dummy1 : 16; | ||
| 366 | } reg_iop_sw_cfg_rw_gio_out_grp2_cfg; | ||
| 367 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 | ||
| 368 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 | ||
| 369 | |||
| 370 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
| 371 | typedef struct { | ||
| 372 | unsigned int gio12 : 3; | ||
| 373 | unsigned int gio12_oe : 1; | ||
| 374 | unsigned int gio13 : 3; | ||
| 375 | unsigned int gio13_oe : 1; | ||
| 376 | unsigned int gio14 : 3; | ||
| 377 | unsigned int gio14_oe : 1; | ||
| 378 | unsigned int gio15 : 3; | ||
| 379 | unsigned int gio15_oe : 1; | ||
| 380 | unsigned int dummy1 : 16; | ||
| 381 | } reg_iop_sw_cfg_rw_gio_out_grp3_cfg; | ||
| 382 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 | ||
| 383 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 | ||
| 384 | |||
| 385 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | ||
| 386 | typedef struct { | ||
| 387 | unsigned int gio16 : 3; | ||
| 388 | unsigned int gio16_oe : 1; | ||
| 389 | unsigned int gio17 : 3; | ||
| 390 | unsigned int gio17_oe : 1; | ||
| 391 | unsigned int gio18 : 3; | ||
| 392 | unsigned int gio18_oe : 1; | ||
| 393 | unsigned int gio19 : 3; | ||
| 394 | unsigned int gio19_oe : 1; | ||
| 395 | unsigned int dummy1 : 16; | ||
| 396 | } reg_iop_sw_cfg_rw_gio_out_grp4_cfg; | ||
| 397 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 | ||
| 398 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 | ||
| 399 | |||
| 400 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | ||
| 401 | typedef struct { | ||
| 402 | unsigned int gio20 : 3; | ||
| 403 | unsigned int gio20_oe : 1; | ||
| 404 | unsigned int gio21 : 3; | ||
| 405 | unsigned int gio21_oe : 1; | ||
| 406 | unsigned int gio22 : 3; | ||
| 407 | unsigned int gio22_oe : 1; | ||
| 408 | unsigned int gio23 : 3; | ||
| 409 | unsigned int gio23_oe : 1; | ||
| 410 | unsigned int dummy1 : 16; | ||
| 411 | } reg_iop_sw_cfg_rw_gio_out_grp5_cfg; | ||
| 412 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 | ||
| 413 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 | ||
| 414 | |||
| 415 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | ||
| 416 | typedef struct { | ||
| 417 | unsigned int gio24 : 3; | ||
| 418 | unsigned int gio24_oe : 1; | ||
| 419 | unsigned int gio25 : 3; | ||
| 420 | unsigned int gio25_oe : 1; | ||
| 421 | unsigned int gio26 : 3; | ||
| 422 | unsigned int gio26_oe : 1; | ||
| 423 | unsigned int gio27 : 3; | ||
| 424 | unsigned int gio27_oe : 1; | ||
| 425 | unsigned int dummy1 : 16; | ||
| 426 | } reg_iop_sw_cfg_rw_gio_out_grp6_cfg; | ||
| 427 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 | ||
| 428 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 | ||
| 429 | |||
| 430 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | ||
| 431 | typedef struct { | ||
| 432 | unsigned int gio28 : 3; | ||
| 433 | unsigned int gio28_oe : 1; | ||
| 434 | unsigned int gio29 : 3; | ||
| 435 | unsigned int gio29_oe : 1; | ||
| 436 | unsigned int gio30 : 3; | ||
| 437 | unsigned int gio30_oe : 1; | ||
| 438 | unsigned int gio31 : 3; | ||
| 439 | unsigned int gio31_oe : 1; | ||
| 440 | unsigned int dummy1 : 16; | ||
| 441 | } reg_iop_sw_cfg_rw_gio_out_grp7_cfg; | ||
| 442 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 | ||
| 443 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 | ||
| 444 | |||
| 445 | /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ | ||
| 446 | typedef struct { | ||
| 447 | unsigned int bus0_in : 1; | ||
| 448 | unsigned int bus1_in : 1; | ||
| 449 | unsigned int dummy1 : 30; | ||
| 450 | } reg_iop_sw_cfg_rw_spu_cfg; | ||
| 451 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 | ||
| 452 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 | ||
| 453 | |||
| 454 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 455 | typedef struct { | ||
| 456 | unsigned int ext_clk : 3; | ||
| 457 | unsigned int tmr0_en : 2; | ||
| 458 | unsigned int tmr1_en : 2; | ||
| 459 | unsigned int tmr2_en : 2; | ||
| 460 | unsigned int tmr3_en : 2; | ||
| 461 | unsigned int tmr0_dis : 2; | ||
| 462 | unsigned int tmr1_dis : 2; | ||
| 463 | unsigned int tmr2_dis : 2; | ||
| 464 | unsigned int tmr3_dis : 2; | ||
| 465 | unsigned int dummy1 : 13; | ||
| 466 | } reg_iop_sw_cfg_rw_timer_grp0_cfg; | ||
| 467 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 | ||
| 468 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 | ||
| 469 | |||
| 470 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 471 | typedef struct { | ||
| 472 | unsigned int ext_clk : 3; | ||
| 473 | unsigned int tmr0_en : 2; | ||
| 474 | unsigned int tmr1_en : 2; | ||
| 475 | unsigned int tmr2_en : 2; | ||
| 476 | unsigned int tmr3_en : 2; | ||
| 477 | unsigned int tmr0_dis : 2; | ||
| 478 | unsigned int tmr1_dis : 2; | ||
| 479 | unsigned int tmr2_dis : 2; | ||
| 480 | unsigned int tmr3_dis : 2; | ||
| 481 | unsigned int dummy1 : 13; | ||
| 482 | } reg_iop_sw_cfg_rw_timer_grp1_cfg; | ||
| 483 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 | ||
| 484 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 | ||
| 485 | |||
| 486 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | ||
| 487 | typedef struct { | ||
| 488 | unsigned int grp0_dis : 1; | ||
| 489 | unsigned int grp0_en : 1; | ||
| 490 | unsigned int grp1_dis : 1; | ||
| 491 | unsigned int grp1_en : 1; | ||
| 492 | unsigned int grp2_dis : 1; | ||
| 493 | unsigned int grp2_en : 1; | ||
| 494 | unsigned int grp3_dis : 1; | ||
| 495 | unsigned int grp3_en : 1; | ||
| 496 | unsigned int grp4_dis : 1; | ||
| 497 | unsigned int grp4_en : 1; | ||
| 498 | unsigned int grp5_dis : 1; | ||
| 499 | unsigned int grp5_en : 1; | ||
| 500 | unsigned int grp6_dis : 1; | ||
| 501 | unsigned int grp6_en : 1; | ||
| 502 | unsigned int grp7_dis : 1; | ||
| 503 | unsigned int grp7_en : 1; | ||
| 504 | unsigned int dummy1 : 16; | ||
| 505 | } reg_iop_sw_cfg_rw_trigger_grps_cfg; | ||
| 506 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 | ||
| 507 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 | ||
| 508 | |||
| 509 | /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 510 | typedef struct { | ||
| 511 | unsigned int out_strb : 4; | ||
| 512 | unsigned int in_src : 2; | ||
| 513 | unsigned int in_size : 3; | ||
| 514 | unsigned int in_last : 2; | ||
| 515 | unsigned int in_strb : 4; | ||
| 516 | unsigned int dummy1 : 17; | ||
| 517 | } reg_iop_sw_cfg_rw_pdp_cfg; | ||
| 518 | #define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 | ||
| 519 | #define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 | ||
| 520 | |||
| 521 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 522 | typedef struct { | ||
| 523 | unsigned int sdp_out_strb : 3; | ||
| 524 | unsigned int sdp_in_data : 3; | ||
| 525 | unsigned int sdp_in_last : 2; | ||
| 526 | unsigned int sdp_in_strb : 3; | ||
| 527 | unsigned int dummy1 : 21; | ||
| 528 | } reg_iop_sw_cfg_rw_sdp_cfg; | ||
| 529 | #define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 | ||
| 530 | #define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 | ||
| 531 | |||
| 532 | |||
| 533 | /* Constants */ | ||
| 534 | enum { | ||
| 535 | regk_iop_sw_cfg_a = 0x00000001, | ||
| 536 | regk_iop_sw_cfg_b = 0x00000002, | ||
| 537 | regk_iop_sw_cfg_bus = 0x00000000, | ||
| 538 | regk_iop_sw_cfg_bus_rot16 = 0x00000002, | ||
| 539 | regk_iop_sw_cfg_bus_rot24 = 0x00000003, | ||
| 540 | regk_iop_sw_cfg_bus_rot8 = 0x00000001, | ||
| 541 | regk_iop_sw_cfg_clk12 = 0x00000000, | ||
| 542 | regk_iop_sw_cfg_cpu = 0x00000000, | ||
| 543 | regk_iop_sw_cfg_gated_clk0 = 0x0000000e, | ||
| 544 | regk_iop_sw_cfg_gated_clk1 = 0x0000000f, | ||
| 545 | regk_iop_sw_cfg_gio0 = 0x00000004, | ||
| 546 | regk_iop_sw_cfg_gio1 = 0x00000001, | ||
| 547 | regk_iop_sw_cfg_gio2 = 0x00000005, | ||
| 548 | regk_iop_sw_cfg_gio3 = 0x00000002, | ||
| 549 | regk_iop_sw_cfg_gio4 = 0x00000006, | ||
| 550 | regk_iop_sw_cfg_gio5 = 0x00000003, | ||
| 551 | regk_iop_sw_cfg_gio6 = 0x00000007, | ||
| 552 | regk_iop_sw_cfg_gio7 = 0x00000004, | ||
| 553 | regk_iop_sw_cfg_gio_in18 = 0x00000002, | ||
| 554 | regk_iop_sw_cfg_gio_in19 = 0x00000003, | ||
| 555 | regk_iop_sw_cfg_gio_in20 = 0x00000004, | ||
| 556 | regk_iop_sw_cfg_gio_in21 = 0x00000005, | ||
| 557 | regk_iop_sw_cfg_gio_in26 = 0x00000006, | ||
| 558 | regk_iop_sw_cfg_gio_in27 = 0x00000007, | ||
| 559 | regk_iop_sw_cfg_gio_in4 = 0x00000000, | ||
| 560 | regk_iop_sw_cfg_gio_in5 = 0x00000001, | ||
| 561 | regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, | ||
| 562 | regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, | ||
| 563 | regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, | ||
| 564 | regk_iop_sw_cfg_mpu = 0x00000001, | ||
| 565 | regk_iop_sw_cfg_none = 0x00000000, | ||
| 566 | regk_iop_sw_cfg_pdp_out = 0x00000001, | ||
| 567 | regk_iop_sw_cfg_pdp_out_hi = 0x00000001, | ||
| 568 | regk_iop_sw_cfg_pdp_out_lo = 0x00000000, | ||
| 569 | regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, | ||
| 570 | regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, | ||
| 571 | regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, | ||
| 572 | regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, | ||
| 573 | regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, | ||
| 574 | regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, | ||
| 575 | regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, | ||
| 576 | regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, | ||
| 577 | regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, | ||
| 578 | regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, | ||
| 579 | regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, | ||
| 580 | regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, | ||
| 581 | regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, | ||
| 582 | regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, | ||
| 583 | regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, | ||
| 584 | regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, | ||
| 585 | regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, | ||
| 586 | regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, | ||
| 587 | regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, | ||
| 588 | regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, | ||
| 589 | regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, | ||
| 590 | regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, | ||
| 591 | regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, | ||
| 592 | regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, | ||
| 593 | regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, | ||
| 594 | regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, | ||
| 595 | regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, | ||
| 596 | regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, | ||
| 597 | regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, | ||
| 598 | regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, | ||
| 599 | regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, | ||
| 600 | regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, | ||
| 601 | regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, | ||
| 602 | regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, | ||
| 603 | regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, | ||
| 604 | regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, | ||
| 605 | regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, | ||
| 606 | regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, | ||
| 607 | regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, | ||
| 608 | regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, | ||
| 609 | regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, | ||
| 610 | regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, | ||
| 611 | regk_iop_sw_cfg_sdp_out = 0x00000004, | ||
| 612 | regk_iop_sw_cfg_size16 = 0x00000002, | ||
| 613 | regk_iop_sw_cfg_size24 = 0x00000003, | ||
| 614 | regk_iop_sw_cfg_size32 = 0x00000004, | ||
| 615 | regk_iop_sw_cfg_size8 = 0x00000001, | ||
| 616 | regk_iop_sw_cfg_spu = 0x00000002, | ||
| 617 | regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, | ||
| 618 | regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, | ||
| 619 | regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, | ||
| 620 | regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, | ||
| 621 | regk_iop_sw_cfg_spu_g0 = 0x00000007, | ||
| 622 | regk_iop_sw_cfg_spu_g1 = 0x00000007, | ||
| 623 | regk_iop_sw_cfg_spu_g2 = 0x00000007, | ||
| 624 | regk_iop_sw_cfg_spu_g3 = 0x00000007, | ||
| 625 | regk_iop_sw_cfg_spu_g4 = 0x00000007, | ||
| 626 | regk_iop_sw_cfg_spu_g5 = 0x00000007, | ||
| 627 | regk_iop_sw_cfg_spu_g6 = 0x00000007, | ||
| 628 | regk_iop_sw_cfg_spu_g7 = 0x00000007, | ||
| 629 | regk_iop_sw_cfg_spu_gio0 = 0x00000000, | ||
| 630 | regk_iop_sw_cfg_spu_gio1 = 0x00000001, | ||
| 631 | regk_iop_sw_cfg_spu_gio5 = 0x00000005, | ||
| 632 | regk_iop_sw_cfg_spu_gio6 = 0x00000006, | ||
| 633 | regk_iop_sw_cfg_spu_gio7 = 0x00000007, | ||
| 634 | regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, | ||
| 635 | regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, | ||
| 636 | regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, | ||
| 637 | regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, | ||
| 638 | regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, | ||
| 639 | regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, | ||
| 640 | regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, | ||
| 641 | regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, | ||
| 642 | regk_iop_sw_cfg_spu_gioout0 = 0x00000000, | ||
| 643 | regk_iop_sw_cfg_spu_gioout1 = 0x00000000, | ||
| 644 | regk_iop_sw_cfg_spu_gioout10 = 0x00000007, | ||
| 645 | regk_iop_sw_cfg_spu_gioout11 = 0x00000007, | ||
| 646 | regk_iop_sw_cfg_spu_gioout12 = 0x00000007, | ||
| 647 | regk_iop_sw_cfg_spu_gioout13 = 0x00000007, | ||
| 648 | regk_iop_sw_cfg_spu_gioout14 = 0x00000007, | ||
| 649 | regk_iop_sw_cfg_spu_gioout15 = 0x00000007, | ||
| 650 | regk_iop_sw_cfg_spu_gioout16 = 0x00000007, | ||
| 651 | regk_iop_sw_cfg_spu_gioout17 = 0x00000007, | ||
| 652 | regk_iop_sw_cfg_spu_gioout18 = 0x00000007, | ||
| 653 | regk_iop_sw_cfg_spu_gioout19 = 0x00000007, | ||
| 654 | regk_iop_sw_cfg_spu_gioout2 = 0x00000001, | ||
| 655 | regk_iop_sw_cfg_spu_gioout20 = 0x00000007, | ||
| 656 | regk_iop_sw_cfg_spu_gioout21 = 0x00000007, | ||
| 657 | regk_iop_sw_cfg_spu_gioout22 = 0x00000007, | ||
| 658 | regk_iop_sw_cfg_spu_gioout23 = 0x00000007, | ||
| 659 | regk_iop_sw_cfg_spu_gioout24 = 0x00000007, | ||
| 660 | regk_iop_sw_cfg_spu_gioout25 = 0x00000007, | ||
| 661 | regk_iop_sw_cfg_spu_gioout26 = 0x00000007, | ||
| 662 | regk_iop_sw_cfg_spu_gioout27 = 0x00000007, | ||
| 663 | regk_iop_sw_cfg_spu_gioout28 = 0x00000007, | ||
| 664 | regk_iop_sw_cfg_spu_gioout29 = 0x00000007, | ||
| 665 | regk_iop_sw_cfg_spu_gioout3 = 0x00000001, | ||
| 666 | regk_iop_sw_cfg_spu_gioout30 = 0x00000007, | ||
| 667 | regk_iop_sw_cfg_spu_gioout31 = 0x00000007, | ||
| 668 | regk_iop_sw_cfg_spu_gioout4 = 0x00000002, | ||
| 669 | regk_iop_sw_cfg_spu_gioout5 = 0x00000002, | ||
| 670 | regk_iop_sw_cfg_spu_gioout6 = 0x00000003, | ||
| 671 | regk_iop_sw_cfg_spu_gioout7 = 0x00000003, | ||
| 672 | regk_iop_sw_cfg_spu_gioout8 = 0x00000007, | ||
| 673 | regk_iop_sw_cfg_spu_gioout9 = 0x00000007, | ||
| 674 | regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, | ||
| 675 | regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, | ||
| 676 | regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, | ||
| 677 | regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, | ||
| 678 | regk_iop_sw_cfg_timer_grp0 = 0x00000000, | ||
| 679 | regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, | ||
| 680 | regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, | ||
| 681 | regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, | ||
| 682 | regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, | ||
| 683 | regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, | ||
| 684 | regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, | ||
| 685 | regk_iop_sw_cfg_timer_grp1 = 0x00000000, | ||
| 686 | regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, | ||
| 687 | regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, | ||
| 688 | regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, | ||
| 689 | regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, | ||
| 690 | regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, | ||
| 691 | regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, | ||
| 692 | regk_iop_sw_cfg_trig0_0 = 0x00000000, | ||
| 693 | regk_iop_sw_cfg_trig0_1 = 0x00000000, | ||
| 694 | regk_iop_sw_cfg_trig0_2 = 0x00000000, | ||
| 695 | regk_iop_sw_cfg_trig0_3 = 0x00000000, | ||
| 696 | regk_iop_sw_cfg_trig1_0 = 0x00000000, | ||
| 697 | regk_iop_sw_cfg_trig1_1 = 0x00000000, | ||
| 698 | regk_iop_sw_cfg_trig1_2 = 0x00000000, | ||
| 699 | regk_iop_sw_cfg_trig1_3 = 0x00000000, | ||
| 700 | regk_iop_sw_cfg_trig2_0 = 0x00000001, | ||
| 701 | regk_iop_sw_cfg_trig2_1 = 0x00000001, | ||
| 702 | regk_iop_sw_cfg_trig2_2 = 0x00000001, | ||
| 703 | regk_iop_sw_cfg_trig2_3 = 0x00000001, | ||
| 704 | regk_iop_sw_cfg_trig3_0 = 0x00000001, | ||
| 705 | regk_iop_sw_cfg_trig3_1 = 0x00000001, | ||
| 706 | regk_iop_sw_cfg_trig3_2 = 0x00000001, | ||
| 707 | regk_iop_sw_cfg_trig3_3 = 0x00000001, | ||
| 708 | regk_iop_sw_cfg_trig4_0 = 0x00000002, | ||
| 709 | regk_iop_sw_cfg_trig4_1 = 0x00000002, | ||
| 710 | regk_iop_sw_cfg_trig4_2 = 0x00000002, | ||
| 711 | regk_iop_sw_cfg_trig4_3 = 0x00000002, | ||
| 712 | regk_iop_sw_cfg_trig5_0 = 0x00000002, | ||
| 713 | regk_iop_sw_cfg_trig5_1 = 0x00000002, | ||
| 714 | regk_iop_sw_cfg_trig5_2 = 0x00000002, | ||
| 715 | regk_iop_sw_cfg_trig5_3 = 0x00000002, | ||
| 716 | regk_iop_sw_cfg_trig6_0 = 0x00000003, | ||
| 717 | regk_iop_sw_cfg_trig6_1 = 0x00000003, | ||
| 718 | regk_iop_sw_cfg_trig6_2 = 0x00000003, | ||
| 719 | regk_iop_sw_cfg_trig6_3 = 0x00000003, | ||
| 720 | regk_iop_sw_cfg_trig7_0 = 0x00000003, | ||
| 721 | regk_iop_sw_cfg_trig7_1 = 0x00000003, | ||
| 722 | regk_iop_sw_cfg_trig7_2 = 0x00000003, | ||
| 723 | regk_iop_sw_cfg_trig7_3 = 0x00000003 | ||
| 724 | }; | ||
| 725 | #endif /* __iop_sw_cfg_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index a16f556370eb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null | |||
| @@ -1,522 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_cpu_defs_h | ||
| 2 | #define __iop_sw_cpu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_cpu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sw_cpu */ | ||
| 83 | |||
| 84 | /* Register r_mpu_trace, scope iop_sw_cpu, type r */ | ||
| 85 | typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; | ||
| 86 | #define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 | ||
| 87 | |||
| 88 | /* Register r_spu_trace, scope iop_sw_cpu, type r */ | ||
| 89 | typedef unsigned int reg_iop_sw_cpu_r_spu_trace; | ||
| 90 | #define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 | ||
| 91 | |||
| 92 | /* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ | ||
| 93 | typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; | ||
| 94 | #define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 | ||
| 95 | |||
| 96 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | ||
| 97 | typedef struct { | ||
| 98 | unsigned int keep_owner : 1; | ||
| 99 | unsigned int cmd : 2; | ||
| 100 | unsigned int size : 3; | ||
| 101 | unsigned int wr_spu_mem : 1; | ||
| 102 | unsigned int dummy1 : 25; | ||
| 103 | } reg_iop_sw_cpu_rw_mc_ctrl; | ||
| 104 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 | ||
| 105 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 | ||
| 106 | |||
| 107 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | ||
| 108 | typedef struct { | ||
| 109 | unsigned int val : 32; | ||
| 110 | } reg_iop_sw_cpu_rw_mc_data; | ||
| 111 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 | ||
| 112 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 | ||
| 113 | |||
| 114 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | ||
| 115 | typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; | ||
| 116 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 | ||
| 117 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 | ||
| 118 | |||
| 119 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | ||
| 120 | typedef unsigned int reg_iop_sw_cpu_rs_mc_data; | ||
| 121 | #define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 | ||
| 122 | |||
| 123 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | ||
| 124 | typedef unsigned int reg_iop_sw_cpu_r_mc_data; | ||
| 125 | #define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 | ||
| 126 | |||
| 127 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | ||
| 128 | typedef struct { | ||
| 129 | unsigned int busy_cpu : 1; | ||
| 130 | unsigned int busy_mpu : 1; | ||
| 131 | unsigned int busy_spu : 1; | ||
| 132 | unsigned int owned_by_cpu : 1; | ||
| 133 | unsigned int owned_by_mpu : 1; | ||
| 134 | unsigned int owned_by_spu : 1; | ||
| 135 | unsigned int dummy1 : 26; | ||
| 136 | } reg_iop_sw_cpu_r_mc_stat; | ||
| 137 | #define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 | ||
| 138 | |||
| 139 | /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 140 | typedef struct { | ||
| 141 | unsigned int byte0 : 8; | ||
| 142 | unsigned int byte1 : 8; | ||
| 143 | unsigned int byte2 : 8; | ||
| 144 | unsigned int byte3 : 8; | ||
| 145 | } reg_iop_sw_cpu_rw_bus_clr_mask; | ||
| 146 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 | ||
| 147 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 | ||
| 148 | |||
| 149 | /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ | ||
| 150 | typedef struct { | ||
| 151 | unsigned int byte0 : 8; | ||
| 152 | unsigned int byte1 : 8; | ||
| 153 | unsigned int byte2 : 8; | ||
| 154 | unsigned int byte3 : 8; | ||
| 155 | } reg_iop_sw_cpu_rw_bus_set_mask; | ||
| 156 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 | ||
| 157 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 | ||
| 158 | |||
| 159 | /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 160 | typedef struct { | ||
| 161 | unsigned int byte0 : 1; | ||
| 162 | unsigned int byte1 : 1; | ||
| 163 | unsigned int byte2 : 1; | ||
| 164 | unsigned int byte3 : 1; | ||
| 165 | unsigned int dummy1 : 28; | ||
| 166 | } reg_iop_sw_cpu_rw_bus_oe_clr_mask; | ||
| 167 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 | ||
| 168 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 | ||
| 169 | |||
| 170 | /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 171 | typedef struct { | ||
| 172 | unsigned int byte0 : 1; | ||
| 173 | unsigned int byte1 : 1; | ||
| 174 | unsigned int byte2 : 1; | ||
| 175 | unsigned int byte3 : 1; | ||
| 176 | unsigned int dummy1 : 28; | ||
| 177 | } reg_iop_sw_cpu_rw_bus_oe_set_mask; | ||
| 178 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 | ||
| 179 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 | ||
| 180 | |||
| 181 | /* Register r_bus_in, scope iop_sw_cpu, type r */ | ||
| 182 | typedef unsigned int reg_iop_sw_cpu_r_bus_in; | ||
| 183 | #define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 | ||
| 184 | |||
| 185 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 186 | typedef struct { | ||
| 187 | unsigned int val : 32; | ||
| 188 | } reg_iop_sw_cpu_rw_gio_clr_mask; | ||
| 189 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 | ||
| 190 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 | ||
| 191 | |||
| 192 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | ||
| 193 | typedef struct { | ||
| 194 | unsigned int val : 32; | ||
| 195 | } reg_iop_sw_cpu_rw_gio_set_mask; | ||
| 196 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 | ||
| 197 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 | ||
| 198 | |||
| 199 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 200 | typedef struct { | ||
| 201 | unsigned int val : 32; | ||
| 202 | } reg_iop_sw_cpu_rw_gio_oe_clr_mask; | ||
| 203 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 | ||
| 204 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 | ||
| 205 | |||
| 206 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 207 | typedef struct { | ||
| 208 | unsigned int val : 32; | ||
| 209 | } reg_iop_sw_cpu_rw_gio_oe_set_mask; | ||
| 210 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 | ||
| 211 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 | ||
| 212 | |||
| 213 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | ||
| 214 | typedef unsigned int reg_iop_sw_cpu_r_gio_in; | ||
| 215 | #define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 | ||
| 216 | |||
| 217 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int mpu_0 : 1; | ||
| 220 | unsigned int mpu_1 : 1; | ||
| 221 | unsigned int mpu_2 : 1; | ||
| 222 | unsigned int mpu_3 : 1; | ||
| 223 | unsigned int mpu_4 : 1; | ||
| 224 | unsigned int mpu_5 : 1; | ||
| 225 | unsigned int mpu_6 : 1; | ||
| 226 | unsigned int mpu_7 : 1; | ||
| 227 | unsigned int mpu_8 : 1; | ||
| 228 | unsigned int mpu_9 : 1; | ||
| 229 | unsigned int mpu_10 : 1; | ||
| 230 | unsigned int mpu_11 : 1; | ||
| 231 | unsigned int mpu_12 : 1; | ||
| 232 | unsigned int mpu_13 : 1; | ||
| 233 | unsigned int mpu_14 : 1; | ||
| 234 | unsigned int mpu_15 : 1; | ||
| 235 | unsigned int spu_0 : 1; | ||
| 236 | unsigned int spu_1 : 1; | ||
| 237 | unsigned int spu_2 : 1; | ||
| 238 | unsigned int spu_3 : 1; | ||
| 239 | unsigned int spu_4 : 1; | ||
| 240 | unsigned int spu_5 : 1; | ||
| 241 | unsigned int spu_6 : 1; | ||
| 242 | unsigned int spu_7 : 1; | ||
| 243 | unsigned int spu_8 : 1; | ||
| 244 | unsigned int spu_9 : 1; | ||
| 245 | unsigned int spu_10 : 1; | ||
| 246 | unsigned int spu_11 : 1; | ||
| 247 | unsigned int spu_12 : 1; | ||
| 248 | unsigned int spu_13 : 1; | ||
| 249 | unsigned int spu_14 : 1; | ||
| 250 | unsigned int spu_15 : 1; | ||
| 251 | } reg_iop_sw_cpu_rw_intr0_mask; | ||
| 252 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 | ||
| 253 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 | ||
| 254 | |||
| 255 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | ||
| 256 | typedef struct { | ||
| 257 | unsigned int mpu_0 : 1; | ||
| 258 | unsigned int mpu_1 : 1; | ||
| 259 | unsigned int mpu_2 : 1; | ||
| 260 | unsigned int mpu_3 : 1; | ||
| 261 | unsigned int mpu_4 : 1; | ||
| 262 | unsigned int mpu_5 : 1; | ||
| 263 | unsigned int mpu_6 : 1; | ||
| 264 | unsigned int mpu_7 : 1; | ||
| 265 | unsigned int mpu_8 : 1; | ||
| 266 | unsigned int mpu_9 : 1; | ||
| 267 | unsigned int mpu_10 : 1; | ||
| 268 | unsigned int mpu_11 : 1; | ||
| 269 | unsigned int mpu_12 : 1; | ||
| 270 | unsigned int mpu_13 : 1; | ||
| 271 | unsigned int mpu_14 : 1; | ||
| 272 | unsigned int mpu_15 : 1; | ||
| 273 | unsigned int spu_0 : 1; | ||
| 274 | unsigned int spu_1 : 1; | ||
| 275 | unsigned int spu_2 : 1; | ||
| 276 | unsigned int spu_3 : 1; | ||
| 277 | unsigned int spu_4 : 1; | ||
| 278 | unsigned int spu_5 : 1; | ||
| 279 | unsigned int spu_6 : 1; | ||
| 280 | unsigned int spu_7 : 1; | ||
| 281 | unsigned int spu_8 : 1; | ||
| 282 | unsigned int spu_9 : 1; | ||
| 283 | unsigned int spu_10 : 1; | ||
| 284 | unsigned int spu_11 : 1; | ||
| 285 | unsigned int spu_12 : 1; | ||
| 286 | unsigned int spu_13 : 1; | ||
| 287 | unsigned int spu_14 : 1; | ||
| 288 | unsigned int spu_15 : 1; | ||
| 289 | } reg_iop_sw_cpu_rw_ack_intr0; | ||
| 290 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 | ||
| 291 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 | ||
| 292 | |||
| 293 | /* Register r_intr0, scope iop_sw_cpu, type r */ | ||
| 294 | typedef struct { | ||
| 295 | unsigned int mpu_0 : 1; | ||
| 296 | unsigned int mpu_1 : 1; | ||
| 297 | unsigned int mpu_2 : 1; | ||
| 298 | unsigned int mpu_3 : 1; | ||
| 299 | unsigned int mpu_4 : 1; | ||
| 300 | unsigned int mpu_5 : 1; | ||
| 301 | unsigned int mpu_6 : 1; | ||
| 302 | unsigned int mpu_7 : 1; | ||
| 303 | unsigned int mpu_8 : 1; | ||
| 304 | unsigned int mpu_9 : 1; | ||
| 305 | unsigned int mpu_10 : 1; | ||
| 306 | unsigned int mpu_11 : 1; | ||
| 307 | unsigned int mpu_12 : 1; | ||
| 308 | unsigned int mpu_13 : 1; | ||
| 309 | unsigned int mpu_14 : 1; | ||
| 310 | unsigned int mpu_15 : 1; | ||
| 311 | unsigned int spu_0 : 1; | ||
| 312 | unsigned int spu_1 : 1; | ||
| 313 | unsigned int spu_2 : 1; | ||
| 314 | unsigned int spu_3 : 1; | ||
| 315 | unsigned int spu_4 : 1; | ||
| 316 | unsigned int spu_5 : 1; | ||
| 317 | unsigned int spu_6 : 1; | ||
| 318 | unsigned int spu_7 : 1; | ||
| 319 | unsigned int spu_8 : 1; | ||
| 320 | unsigned int spu_9 : 1; | ||
| 321 | unsigned int spu_10 : 1; | ||
| 322 | unsigned int spu_11 : 1; | ||
| 323 | unsigned int spu_12 : 1; | ||
| 324 | unsigned int spu_13 : 1; | ||
| 325 | unsigned int spu_14 : 1; | ||
| 326 | unsigned int spu_15 : 1; | ||
| 327 | } reg_iop_sw_cpu_r_intr0; | ||
| 328 | #define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 | ||
| 329 | |||
| 330 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | ||
| 331 | typedef struct { | ||
| 332 | unsigned int mpu_0 : 1; | ||
| 333 | unsigned int mpu_1 : 1; | ||
| 334 | unsigned int mpu_2 : 1; | ||
| 335 | unsigned int mpu_3 : 1; | ||
| 336 | unsigned int mpu_4 : 1; | ||
| 337 | unsigned int mpu_5 : 1; | ||
| 338 | unsigned int mpu_6 : 1; | ||
| 339 | unsigned int mpu_7 : 1; | ||
| 340 | unsigned int mpu_8 : 1; | ||
| 341 | unsigned int mpu_9 : 1; | ||
| 342 | unsigned int mpu_10 : 1; | ||
| 343 | unsigned int mpu_11 : 1; | ||
| 344 | unsigned int mpu_12 : 1; | ||
| 345 | unsigned int mpu_13 : 1; | ||
| 346 | unsigned int mpu_14 : 1; | ||
| 347 | unsigned int mpu_15 : 1; | ||
| 348 | unsigned int spu_0 : 1; | ||
| 349 | unsigned int spu_1 : 1; | ||
| 350 | unsigned int spu_2 : 1; | ||
| 351 | unsigned int spu_3 : 1; | ||
| 352 | unsigned int spu_4 : 1; | ||
| 353 | unsigned int spu_5 : 1; | ||
| 354 | unsigned int spu_6 : 1; | ||
| 355 | unsigned int spu_7 : 1; | ||
| 356 | unsigned int spu_8 : 1; | ||
| 357 | unsigned int spu_9 : 1; | ||
| 358 | unsigned int spu_10 : 1; | ||
| 359 | unsigned int spu_11 : 1; | ||
| 360 | unsigned int spu_12 : 1; | ||
| 361 | unsigned int spu_13 : 1; | ||
| 362 | unsigned int spu_14 : 1; | ||
| 363 | unsigned int spu_15 : 1; | ||
| 364 | } reg_iop_sw_cpu_r_masked_intr0; | ||
| 365 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 | ||
| 366 | |||
| 367 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | ||
| 368 | typedef struct { | ||
| 369 | unsigned int mpu_16 : 1; | ||
| 370 | unsigned int mpu_17 : 1; | ||
| 371 | unsigned int mpu_18 : 1; | ||
| 372 | unsigned int mpu_19 : 1; | ||
| 373 | unsigned int mpu_20 : 1; | ||
| 374 | unsigned int mpu_21 : 1; | ||
| 375 | unsigned int mpu_22 : 1; | ||
| 376 | unsigned int mpu_23 : 1; | ||
| 377 | unsigned int mpu_24 : 1; | ||
| 378 | unsigned int mpu_25 : 1; | ||
| 379 | unsigned int mpu_26 : 1; | ||
| 380 | unsigned int mpu_27 : 1; | ||
| 381 | unsigned int mpu_28 : 1; | ||
| 382 | unsigned int mpu_29 : 1; | ||
| 383 | unsigned int mpu_30 : 1; | ||
| 384 | unsigned int mpu_31 : 1; | ||
| 385 | unsigned int dmc_in : 1; | ||
| 386 | unsigned int dmc_out : 1; | ||
| 387 | unsigned int fifo_in : 1; | ||
| 388 | unsigned int fifo_out : 1; | ||
| 389 | unsigned int fifo_in_extra : 1; | ||
| 390 | unsigned int fifo_out_extra : 1; | ||
| 391 | unsigned int trigger_grp0 : 1; | ||
| 392 | unsigned int trigger_grp1 : 1; | ||
| 393 | unsigned int trigger_grp2 : 1; | ||
| 394 | unsigned int trigger_grp3 : 1; | ||
| 395 | unsigned int trigger_grp4 : 1; | ||
| 396 | unsigned int trigger_grp5 : 1; | ||
| 397 | unsigned int trigger_grp6 : 1; | ||
| 398 | unsigned int trigger_grp7 : 1; | ||
| 399 | unsigned int timer_grp0 : 1; | ||
| 400 | unsigned int timer_grp1 : 1; | ||
| 401 | } reg_iop_sw_cpu_rw_intr1_mask; | ||
| 402 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 | ||
| 403 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 | ||
| 404 | |||
| 405 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | ||
| 406 | typedef struct { | ||
| 407 | unsigned int mpu_16 : 1; | ||
| 408 | unsigned int mpu_17 : 1; | ||
| 409 | unsigned int mpu_18 : 1; | ||
| 410 | unsigned int mpu_19 : 1; | ||
| 411 | unsigned int mpu_20 : 1; | ||
| 412 | unsigned int mpu_21 : 1; | ||
| 413 | unsigned int mpu_22 : 1; | ||
| 414 | unsigned int mpu_23 : 1; | ||
| 415 | unsigned int mpu_24 : 1; | ||
| 416 | unsigned int mpu_25 : 1; | ||
| 417 | unsigned int mpu_26 : 1; | ||
| 418 | unsigned int mpu_27 : 1; | ||
| 419 | unsigned int mpu_28 : 1; | ||
| 420 | unsigned int mpu_29 : 1; | ||
| 421 | unsigned int mpu_30 : 1; | ||
| 422 | unsigned int mpu_31 : 1; | ||
| 423 | unsigned int dummy1 : 16; | ||
| 424 | } reg_iop_sw_cpu_rw_ack_intr1; | ||
| 425 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 | ||
| 426 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 | ||
| 427 | |||
| 428 | /* Register r_intr1, scope iop_sw_cpu, type r */ | ||
| 429 | typedef struct { | ||
| 430 | unsigned int mpu_16 : 1; | ||
| 431 | unsigned int mpu_17 : 1; | ||
| 432 | unsigned int mpu_18 : 1; | ||
| 433 | unsigned int mpu_19 : 1; | ||
| 434 | unsigned int mpu_20 : 1; | ||
| 435 | unsigned int mpu_21 : 1; | ||
| 436 | unsigned int mpu_22 : 1; | ||
| 437 | unsigned int mpu_23 : 1; | ||
| 438 | unsigned int mpu_24 : 1; | ||
| 439 | unsigned int mpu_25 : 1; | ||
| 440 | unsigned int mpu_26 : 1; | ||
| 441 | unsigned int mpu_27 : 1; | ||
| 442 | unsigned int mpu_28 : 1; | ||
| 443 | unsigned int mpu_29 : 1; | ||
| 444 | unsigned int mpu_30 : 1; | ||
| 445 | unsigned int mpu_31 : 1; | ||
| 446 | unsigned int dmc_in : 1; | ||
| 447 | unsigned int dmc_out : 1; | ||
| 448 | unsigned int fifo_in : 1; | ||
| 449 | unsigned int fifo_out : 1; | ||
| 450 | unsigned int fifo_in_extra : 1; | ||
| 451 | unsigned int fifo_out_extra : 1; | ||
| 452 | unsigned int trigger_grp0 : 1; | ||
| 453 | unsigned int trigger_grp1 : 1; | ||
| 454 | unsigned int trigger_grp2 : 1; | ||
| 455 | unsigned int trigger_grp3 : 1; | ||
| 456 | unsigned int trigger_grp4 : 1; | ||
| 457 | unsigned int trigger_grp5 : 1; | ||
| 458 | unsigned int trigger_grp6 : 1; | ||
| 459 | unsigned int trigger_grp7 : 1; | ||
| 460 | unsigned int timer_grp0 : 1; | ||
| 461 | unsigned int timer_grp1 : 1; | ||
| 462 | } reg_iop_sw_cpu_r_intr1; | ||
| 463 | #define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 | ||
| 464 | |||
| 465 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | ||
| 466 | typedef struct { | ||
| 467 | unsigned int mpu_16 : 1; | ||
| 468 | unsigned int mpu_17 : 1; | ||
| 469 | unsigned int mpu_18 : 1; | ||
| 470 | unsigned int mpu_19 : 1; | ||
| 471 | unsigned int mpu_20 : 1; | ||
| 472 | unsigned int mpu_21 : 1; | ||
| 473 | unsigned int mpu_22 : 1; | ||
| 474 | unsigned int mpu_23 : 1; | ||
| 475 | unsigned int mpu_24 : 1; | ||
| 476 | unsigned int mpu_25 : 1; | ||
| 477 | unsigned int mpu_26 : 1; | ||
| 478 | unsigned int mpu_27 : 1; | ||
| 479 | unsigned int mpu_28 : 1; | ||
| 480 | unsigned int mpu_29 : 1; | ||
| 481 | unsigned int mpu_30 : 1; | ||
| 482 | unsigned int mpu_31 : 1; | ||
| 483 | unsigned int dmc_in : 1; | ||
| 484 | unsigned int dmc_out : 1; | ||
| 485 | unsigned int fifo_in : 1; | ||
| 486 | unsigned int fifo_out : 1; | ||
| 487 | unsigned int fifo_in_extra : 1; | ||
| 488 | unsigned int fifo_out_extra : 1; | ||
| 489 | unsigned int trigger_grp0 : 1; | ||
| 490 | unsigned int trigger_grp1 : 1; | ||
| 491 | unsigned int trigger_grp2 : 1; | ||
| 492 | unsigned int trigger_grp3 : 1; | ||
| 493 | unsigned int trigger_grp4 : 1; | ||
| 494 | unsigned int trigger_grp5 : 1; | ||
| 495 | unsigned int trigger_grp6 : 1; | ||
| 496 | unsigned int trigger_grp7 : 1; | ||
| 497 | unsigned int timer_grp0 : 1; | ||
| 498 | unsigned int timer_grp1 : 1; | ||
| 499 | } reg_iop_sw_cpu_r_masked_intr1; | ||
| 500 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 | ||
| 501 | |||
| 502 | |||
| 503 | /* Constants */ | ||
| 504 | enum { | ||
| 505 | regk_iop_sw_cpu_copy = 0x00000000, | ||
| 506 | regk_iop_sw_cpu_no = 0x00000000, | ||
| 507 | regk_iop_sw_cpu_rd = 0x00000002, | ||
| 508 | regk_iop_sw_cpu_reg_copy = 0x00000001, | ||
| 509 | regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, | ||
| 510 | regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
| 511 | regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, | ||
| 512 | regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, | ||
| 513 | regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, | ||
| 514 | regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 515 | regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 516 | regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, | ||
| 517 | regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, | ||
| 518 | regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, | ||
| 519 | regk_iop_sw_cpu_wr = 0x00000003, | ||
| 520 | regk_iop_sw_cpu_yes = 0x00000001 | ||
| 521 | }; | ||
| 522 | #endif /* __iop_sw_cpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index a2e4e1a33e57..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null | |||
| @@ -1,648 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_mpu_defs_h | ||
| 2 | #define __iop_sw_mpu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_mpu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sw_mpu */ | ||
| 83 | |||
| 84 | /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int cfg : 2; | ||
| 87 | unsigned int dummy1 : 30; | ||
| 88 | } reg_iop_sw_mpu_rw_sw_cfg_owner; | ||
| 89 | #define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 | ||
| 90 | #define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 | ||
| 91 | |||
| 92 | /* Register r_spu_trace, scope iop_sw_mpu, type r */ | ||
| 93 | typedef unsigned int reg_iop_sw_mpu_r_spu_trace; | ||
| 94 | #define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 | ||
| 95 | |||
| 96 | /* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ | ||
| 97 | typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; | ||
| 98 | #define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 | ||
| 99 | |||
| 100 | /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ | ||
| 101 | typedef struct { | ||
| 102 | unsigned int keep_owner : 1; | ||
| 103 | unsigned int cmd : 2; | ||
| 104 | unsigned int size : 3; | ||
| 105 | unsigned int wr_spu_mem : 1; | ||
| 106 | unsigned int dummy1 : 25; | ||
| 107 | } reg_iop_sw_mpu_rw_mc_ctrl; | ||
| 108 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 | ||
| 109 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 | ||
| 110 | |||
| 111 | /* Register rw_mc_data, scope iop_sw_mpu, type rw */ | ||
| 112 | typedef struct { | ||
| 113 | unsigned int val : 32; | ||
| 114 | } reg_iop_sw_mpu_rw_mc_data; | ||
| 115 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 | ||
| 116 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 | ||
| 117 | |||
| 118 | /* Register rw_mc_addr, scope iop_sw_mpu, type rw */ | ||
| 119 | typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; | ||
| 120 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 | ||
| 121 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 | ||
| 122 | |||
| 123 | /* Register rs_mc_data, scope iop_sw_mpu, type rs */ | ||
| 124 | typedef unsigned int reg_iop_sw_mpu_rs_mc_data; | ||
| 125 | #define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 | ||
| 126 | |||
| 127 | /* Register r_mc_data, scope iop_sw_mpu, type r */ | ||
| 128 | typedef unsigned int reg_iop_sw_mpu_r_mc_data; | ||
| 129 | #define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 | ||
| 130 | |||
| 131 | /* Register r_mc_stat, scope iop_sw_mpu, type r */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int busy_cpu : 1; | ||
| 134 | unsigned int busy_mpu : 1; | ||
| 135 | unsigned int busy_spu : 1; | ||
| 136 | unsigned int owned_by_cpu : 1; | ||
| 137 | unsigned int owned_by_mpu : 1; | ||
| 138 | unsigned int owned_by_spu : 1; | ||
| 139 | unsigned int dummy1 : 26; | ||
| 140 | } reg_iop_sw_mpu_r_mc_stat; | ||
| 141 | #define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 | ||
| 142 | |||
| 143 | /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 144 | typedef struct { | ||
| 145 | unsigned int byte0 : 8; | ||
| 146 | unsigned int byte1 : 8; | ||
| 147 | unsigned int byte2 : 8; | ||
| 148 | unsigned int byte3 : 8; | ||
| 149 | } reg_iop_sw_mpu_rw_bus_clr_mask; | ||
| 150 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 | ||
| 151 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 | ||
| 152 | |||
| 153 | /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int byte0 : 8; | ||
| 156 | unsigned int byte1 : 8; | ||
| 157 | unsigned int byte2 : 8; | ||
| 158 | unsigned int byte3 : 8; | ||
| 159 | } reg_iop_sw_mpu_rw_bus_set_mask; | ||
| 160 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 | ||
| 161 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 | ||
| 162 | |||
| 163 | /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 164 | typedef struct { | ||
| 165 | unsigned int byte0 : 1; | ||
| 166 | unsigned int byte1 : 1; | ||
| 167 | unsigned int byte2 : 1; | ||
| 168 | unsigned int byte3 : 1; | ||
| 169 | unsigned int dummy1 : 28; | ||
| 170 | } reg_iop_sw_mpu_rw_bus_oe_clr_mask; | ||
| 171 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 | ||
| 172 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 | ||
| 173 | |||
| 174 | /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 175 | typedef struct { | ||
| 176 | unsigned int byte0 : 1; | ||
| 177 | unsigned int byte1 : 1; | ||
| 178 | unsigned int byte2 : 1; | ||
| 179 | unsigned int byte3 : 1; | ||
| 180 | unsigned int dummy1 : 28; | ||
| 181 | } reg_iop_sw_mpu_rw_bus_oe_set_mask; | ||
| 182 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 | ||
| 183 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 | ||
| 184 | |||
| 185 | /* Register r_bus_in, scope iop_sw_mpu, type r */ | ||
| 186 | typedef unsigned int reg_iop_sw_mpu_r_bus_in; | ||
| 187 | #define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 | ||
| 188 | |||
| 189 | /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 190 | typedef struct { | ||
| 191 | unsigned int val : 32; | ||
| 192 | } reg_iop_sw_mpu_rw_gio_clr_mask; | ||
| 193 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 | ||
| 194 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 | ||
| 195 | |||
| 196 | /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int val : 32; | ||
| 199 | } reg_iop_sw_mpu_rw_gio_set_mask; | ||
| 200 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 | ||
| 201 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 | ||
| 202 | |||
| 203 | /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 204 | typedef struct { | ||
| 205 | unsigned int val : 32; | ||
| 206 | } reg_iop_sw_mpu_rw_gio_oe_clr_mask; | ||
| 207 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 | ||
| 208 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 | ||
| 209 | |||
| 210 | /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 211 | typedef struct { | ||
| 212 | unsigned int val : 32; | ||
| 213 | } reg_iop_sw_mpu_rw_gio_oe_set_mask; | ||
| 214 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 | ||
| 215 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 | ||
| 216 | |||
| 217 | /* Register r_gio_in, scope iop_sw_mpu, type r */ | ||
| 218 | typedef unsigned int reg_iop_sw_mpu_r_gio_in; | ||
| 219 | #define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 | ||
| 220 | |||
| 221 | /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ | ||
| 222 | typedef struct { | ||
| 223 | unsigned int intr0 : 1; | ||
| 224 | unsigned int intr1 : 1; | ||
| 225 | unsigned int intr2 : 1; | ||
| 226 | unsigned int intr3 : 1; | ||
| 227 | unsigned int intr4 : 1; | ||
| 228 | unsigned int intr5 : 1; | ||
| 229 | unsigned int intr6 : 1; | ||
| 230 | unsigned int intr7 : 1; | ||
| 231 | unsigned int intr8 : 1; | ||
| 232 | unsigned int intr9 : 1; | ||
| 233 | unsigned int intr10 : 1; | ||
| 234 | unsigned int intr11 : 1; | ||
| 235 | unsigned int intr12 : 1; | ||
| 236 | unsigned int intr13 : 1; | ||
| 237 | unsigned int intr14 : 1; | ||
| 238 | unsigned int intr15 : 1; | ||
| 239 | unsigned int intr16 : 1; | ||
| 240 | unsigned int intr17 : 1; | ||
| 241 | unsigned int intr18 : 1; | ||
| 242 | unsigned int intr19 : 1; | ||
| 243 | unsigned int intr20 : 1; | ||
| 244 | unsigned int intr21 : 1; | ||
| 245 | unsigned int intr22 : 1; | ||
| 246 | unsigned int intr23 : 1; | ||
| 247 | unsigned int intr24 : 1; | ||
| 248 | unsigned int intr25 : 1; | ||
| 249 | unsigned int intr26 : 1; | ||
| 250 | unsigned int intr27 : 1; | ||
| 251 | unsigned int intr28 : 1; | ||
| 252 | unsigned int intr29 : 1; | ||
| 253 | unsigned int intr30 : 1; | ||
| 254 | unsigned int intr31 : 1; | ||
| 255 | } reg_iop_sw_mpu_rw_cpu_intr; | ||
| 256 | #define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 | ||
| 257 | #define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 | ||
| 258 | |||
| 259 | /* Register r_cpu_intr, scope iop_sw_mpu, type r */ | ||
| 260 | typedef struct { | ||
| 261 | unsigned int intr0 : 1; | ||
| 262 | unsigned int intr1 : 1; | ||
| 263 | unsigned int intr2 : 1; | ||
| 264 | unsigned int intr3 : 1; | ||
| 265 | unsigned int intr4 : 1; | ||
| 266 | unsigned int intr5 : 1; | ||
| 267 | unsigned int intr6 : 1; | ||
| 268 | unsigned int intr7 : 1; | ||
| 269 | unsigned int intr8 : 1; | ||
| 270 | unsigned int intr9 : 1; | ||
| 271 | unsigned int intr10 : 1; | ||
| 272 | unsigned int intr11 : 1; | ||
| 273 | unsigned int intr12 : 1; | ||
| 274 | unsigned int intr13 : 1; | ||
| 275 | unsigned int intr14 : 1; | ||
| 276 | unsigned int intr15 : 1; | ||
| 277 | unsigned int intr16 : 1; | ||
| 278 | unsigned int intr17 : 1; | ||
| 279 | unsigned int intr18 : 1; | ||
| 280 | unsigned int intr19 : 1; | ||
| 281 | unsigned int intr20 : 1; | ||
| 282 | unsigned int intr21 : 1; | ||
| 283 | unsigned int intr22 : 1; | ||
| 284 | unsigned int intr23 : 1; | ||
| 285 | unsigned int intr24 : 1; | ||
| 286 | unsigned int intr25 : 1; | ||
| 287 | unsigned int intr26 : 1; | ||
| 288 | unsigned int intr27 : 1; | ||
| 289 | unsigned int intr28 : 1; | ||
| 290 | unsigned int intr29 : 1; | ||
| 291 | unsigned int intr30 : 1; | ||
| 292 | unsigned int intr31 : 1; | ||
| 293 | } reg_iop_sw_mpu_r_cpu_intr; | ||
| 294 | #define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 | ||
| 295 | |||
| 296 | /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ | ||
| 297 | typedef struct { | ||
| 298 | unsigned int spu_intr0 : 1; | ||
| 299 | unsigned int trigger_grp0 : 1; | ||
| 300 | unsigned int timer_grp0 : 1; | ||
| 301 | unsigned int fifo_out : 1; | ||
| 302 | unsigned int spu_intr1 : 1; | ||
| 303 | unsigned int trigger_grp1 : 1; | ||
| 304 | unsigned int timer_grp1 : 1; | ||
| 305 | unsigned int fifo_in : 1; | ||
| 306 | unsigned int spu_intr2 : 1; | ||
| 307 | unsigned int trigger_grp2 : 1; | ||
| 308 | unsigned int fifo_out_extra : 1; | ||
| 309 | unsigned int dmc_out : 1; | ||
| 310 | unsigned int spu_intr3 : 1; | ||
| 311 | unsigned int trigger_grp3 : 1; | ||
| 312 | unsigned int fifo_in_extra : 1; | ||
| 313 | unsigned int dmc_in : 1; | ||
| 314 | unsigned int dummy1 : 16; | ||
| 315 | } reg_iop_sw_mpu_rw_intr_grp0_mask; | ||
| 316 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 | ||
| 317 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 | ||
| 318 | |||
| 319 | /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ | ||
| 320 | typedef struct { | ||
| 321 | unsigned int spu_intr0 : 1; | ||
| 322 | unsigned int dummy1 : 3; | ||
| 323 | unsigned int spu_intr1 : 1; | ||
| 324 | unsigned int dummy2 : 3; | ||
| 325 | unsigned int spu_intr2 : 1; | ||
| 326 | unsigned int dummy3 : 3; | ||
| 327 | unsigned int spu_intr3 : 1; | ||
| 328 | unsigned int dummy4 : 19; | ||
| 329 | } reg_iop_sw_mpu_rw_ack_intr_grp0; | ||
| 330 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 | ||
| 331 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 | ||
| 332 | |||
| 333 | /* Register r_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 334 | typedef struct { | ||
| 335 | unsigned int spu_intr0 : 1; | ||
| 336 | unsigned int trigger_grp0 : 1; | ||
| 337 | unsigned int timer_grp0 : 1; | ||
| 338 | unsigned int fifo_out : 1; | ||
| 339 | unsigned int spu_intr1 : 1; | ||
| 340 | unsigned int trigger_grp1 : 1; | ||
| 341 | unsigned int timer_grp1 : 1; | ||
| 342 | unsigned int fifo_in : 1; | ||
| 343 | unsigned int spu_intr2 : 1; | ||
| 344 | unsigned int trigger_grp2 : 1; | ||
| 345 | unsigned int fifo_out_extra : 1; | ||
| 346 | unsigned int dmc_out : 1; | ||
| 347 | unsigned int spu_intr3 : 1; | ||
| 348 | unsigned int trigger_grp3 : 1; | ||
| 349 | unsigned int fifo_in_extra : 1; | ||
| 350 | unsigned int dmc_in : 1; | ||
| 351 | unsigned int dummy1 : 16; | ||
| 352 | } reg_iop_sw_mpu_r_intr_grp0; | ||
| 353 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 | ||
| 354 | |||
| 355 | /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 356 | typedef struct { | ||
| 357 | unsigned int spu_intr0 : 1; | ||
| 358 | unsigned int trigger_grp0 : 1; | ||
| 359 | unsigned int timer_grp0 : 1; | ||
| 360 | unsigned int fifo_out : 1; | ||
| 361 | unsigned int spu_intr1 : 1; | ||
| 362 | unsigned int trigger_grp1 : 1; | ||
| 363 | unsigned int timer_grp1 : 1; | ||
| 364 | unsigned int fifo_in : 1; | ||
| 365 | unsigned int spu_intr2 : 1; | ||
| 366 | unsigned int trigger_grp2 : 1; | ||
| 367 | unsigned int fifo_out_extra : 1; | ||
| 368 | unsigned int dmc_out : 1; | ||
| 369 | unsigned int spu_intr3 : 1; | ||
| 370 | unsigned int trigger_grp3 : 1; | ||
| 371 | unsigned int fifo_in_extra : 1; | ||
| 372 | unsigned int dmc_in : 1; | ||
| 373 | unsigned int dummy1 : 16; | ||
| 374 | } reg_iop_sw_mpu_r_masked_intr_grp0; | ||
| 375 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 | ||
| 376 | |||
| 377 | /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ | ||
| 378 | typedef struct { | ||
| 379 | unsigned int spu_intr4 : 1; | ||
| 380 | unsigned int trigger_grp4 : 1; | ||
| 381 | unsigned int fifo_out_extra : 1; | ||
| 382 | unsigned int dmc_out : 1; | ||
| 383 | unsigned int spu_intr5 : 1; | ||
| 384 | unsigned int trigger_grp5 : 1; | ||
| 385 | unsigned int fifo_in_extra : 1; | ||
| 386 | unsigned int dmc_in : 1; | ||
| 387 | unsigned int spu_intr6 : 1; | ||
| 388 | unsigned int trigger_grp6 : 1; | ||
| 389 | unsigned int timer_grp0 : 1; | ||
| 390 | unsigned int fifo_out : 1; | ||
| 391 | unsigned int spu_intr7 : 1; | ||
| 392 | unsigned int trigger_grp7 : 1; | ||
| 393 | unsigned int timer_grp1 : 1; | ||
| 394 | unsigned int fifo_in : 1; | ||
| 395 | unsigned int dummy1 : 16; | ||
| 396 | } reg_iop_sw_mpu_rw_intr_grp1_mask; | ||
| 397 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 | ||
| 398 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 | ||
| 399 | |||
| 400 | /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ | ||
| 401 | typedef struct { | ||
| 402 | unsigned int spu_intr4 : 1; | ||
| 403 | unsigned int dummy1 : 3; | ||
| 404 | unsigned int spu_intr5 : 1; | ||
| 405 | unsigned int dummy2 : 3; | ||
| 406 | unsigned int spu_intr6 : 1; | ||
| 407 | unsigned int dummy3 : 3; | ||
| 408 | unsigned int spu_intr7 : 1; | ||
| 409 | unsigned int dummy4 : 19; | ||
| 410 | } reg_iop_sw_mpu_rw_ack_intr_grp1; | ||
| 411 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 | ||
| 412 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 | ||
| 413 | |||
| 414 | /* Register r_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 415 | typedef struct { | ||
| 416 | unsigned int spu_intr4 : 1; | ||
| 417 | unsigned int trigger_grp4 : 1; | ||
| 418 | unsigned int fifo_out_extra : 1; | ||
| 419 | unsigned int dmc_out : 1; | ||
| 420 | unsigned int spu_intr5 : 1; | ||
| 421 | unsigned int trigger_grp5 : 1; | ||
| 422 | unsigned int fifo_in_extra : 1; | ||
| 423 | unsigned int dmc_in : 1; | ||
| 424 | unsigned int spu_intr6 : 1; | ||
| 425 | unsigned int trigger_grp6 : 1; | ||
| 426 | unsigned int timer_grp0 : 1; | ||
| 427 | unsigned int fifo_out : 1; | ||
| 428 | unsigned int spu_intr7 : 1; | ||
| 429 | unsigned int trigger_grp7 : 1; | ||
| 430 | unsigned int timer_grp1 : 1; | ||
| 431 | unsigned int fifo_in : 1; | ||
| 432 | unsigned int dummy1 : 16; | ||
| 433 | } reg_iop_sw_mpu_r_intr_grp1; | ||
| 434 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 | ||
| 435 | |||
| 436 | /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 437 | typedef struct { | ||
| 438 | unsigned int spu_intr4 : 1; | ||
| 439 | unsigned int trigger_grp4 : 1; | ||
| 440 | unsigned int fifo_out_extra : 1; | ||
| 441 | unsigned int dmc_out : 1; | ||
| 442 | unsigned int spu_intr5 : 1; | ||
| 443 | unsigned int trigger_grp5 : 1; | ||
| 444 | unsigned int fifo_in_extra : 1; | ||
| 445 | unsigned int dmc_in : 1; | ||
| 446 | unsigned int spu_intr6 : 1; | ||
| 447 | unsigned int trigger_grp6 : 1; | ||
| 448 | unsigned int timer_grp0 : 1; | ||
| 449 | unsigned int fifo_out : 1; | ||
| 450 | unsigned int spu_intr7 : 1; | ||
| 451 | unsigned int trigger_grp7 : 1; | ||
| 452 | unsigned int timer_grp1 : 1; | ||
| 453 | unsigned int fifo_in : 1; | ||
| 454 | unsigned int dummy1 : 16; | ||
| 455 | } reg_iop_sw_mpu_r_masked_intr_grp1; | ||
| 456 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 | ||
| 457 | |||
| 458 | /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ | ||
| 459 | typedef struct { | ||
| 460 | unsigned int spu_intr8 : 1; | ||
| 461 | unsigned int trigger_grp0 : 1; | ||
| 462 | unsigned int timer_grp0 : 1; | ||
| 463 | unsigned int fifo_out : 1; | ||
| 464 | unsigned int spu_intr9 : 1; | ||
| 465 | unsigned int trigger_grp1 : 1; | ||
| 466 | unsigned int timer_grp1 : 1; | ||
| 467 | unsigned int fifo_in : 1; | ||
| 468 | unsigned int spu_intr10 : 1; | ||
| 469 | unsigned int trigger_grp2 : 1; | ||
| 470 | unsigned int fifo_out_extra : 1; | ||
| 471 | unsigned int dmc_out : 1; | ||
| 472 | unsigned int spu_intr11 : 1; | ||
| 473 | unsigned int trigger_grp3 : 1; | ||
| 474 | unsigned int fifo_in_extra : 1; | ||
| 475 | unsigned int dmc_in : 1; | ||
| 476 | unsigned int dummy1 : 16; | ||
| 477 | } reg_iop_sw_mpu_rw_intr_grp2_mask; | ||
| 478 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 | ||
| 479 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 | ||
| 480 | |||
| 481 | /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ | ||
| 482 | typedef struct { | ||
| 483 | unsigned int spu_intr8 : 1; | ||
| 484 | unsigned int dummy1 : 3; | ||
| 485 | unsigned int spu_intr9 : 1; | ||
| 486 | unsigned int dummy2 : 3; | ||
| 487 | unsigned int spu_intr10 : 1; | ||
| 488 | unsigned int dummy3 : 3; | ||
| 489 | unsigned int spu_intr11 : 1; | ||
| 490 | unsigned int dummy4 : 19; | ||
| 491 | } reg_iop_sw_mpu_rw_ack_intr_grp2; | ||
| 492 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 | ||
| 493 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 | ||
| 494 | |||
| 495 | /* Register r_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 496 | typedef struct { | ||
| 497 | unsigned int spu_intr8 : 1; | ||
| 498 | unsigned int trigger_grp0 : 1; | ||
| 499 | unsigned int timer_grp0 : 1; | ||
| 500 | unsigned int fifo_out : 1; | ||
| 501 | unsigned int spu_intr9 : 1; | ||
| 502 | unsigned int trigger_grp1 : 1; | ||
| 503 | unsigned int timer_grp1 : 1; | ||
| 504 | unsigned int fifo_in : 1; | ||
| 505 | unsigned int spu_intr10 : 1; | ||
| 506 | unsigned int trigger_grp2 : 1; | ||
| 507 | unsigned int fifo_out_extra : 1; | ||
| 508 | unsigned int dmc_out : 1; | ||
| 509 | unsigned int spu_intr11 : 1; | ||
| 510 | unsigned int trigger_grp3 : 1; | ||
| 511 | unsigned int fifo_in_extra : 1; | ||
| 512 | unsigned int dmc_in : 1; | ||
| 513 | unsigned int dummy1 : 16; | ||
| 514 | } reg_iop_sw_mpu_r_intr_grp2; | ||
| 515 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 | ||
| 516 | |||
| 517 | /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 518 | typedef struct { | ||
| 519 | unsigned int spu_intr8 : 1; | ||
| 520 | unsigned int trigger_grp0 : 1; | ||
| 521 | unsigned int timer_grp0 : 1; | ||
| 522 | unsigned int fifo_out : 1; | ||
| 523 | unsigned int spu_intr9 : 1; | ||
| 524 | unsigned int trigger_grp1 : 1; | ||
| 525 | unsigned int timer_grp1 : 1; | ||
| 526 | unsigned int fifo_in : 1; | ||
| 527 | unsigned int spu_intr10 : 1; | ||
| 528 | unsigned int trigger_grp2 : 1; | ||
| 529 | unsigned int fifo_out_extra : 1; | ||
| 530 | unsigned int dmc_out : 1; | ||
| 531 | unsigned int spu_intr11 : 1; | ||
| 532 | unsigned int trigger_grp3 : 1; | ||
| 533 | unsigned int fifo_in_extra : 1; | ||
| 534 | unsigned int dmc_in : 1; | ||
| 535 | unsigned int dummy1 : 16; | ||
| 536 | } reg_iop_sw_mpu_r_masked_intr_grp2; | ||
| 537 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 | ||
| 538 | |||
| 539 | /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ | ||
| 540 | typedef struct { | ||
| 541 | unsigned int spu_intr12 : 1; | ||
| 542 | unsigned int trigger_grp4 : 1; | ||
| 543 | unsigned int fifo_out_extra : 1; | ||
| 544 | unsigned int dmc_out : 1; | ||
| 545 | unsigned int spu_intr13 : 1; | ||
| 546 | unsigned int trigger_grp5 : 1; | ||
| 547 | unsigned int fifo_in_extra : 1; | ||
| 548 | unsigned int dmc_in : 1; | ||
| 549 | unsigned int spu_intr14 : 1; | ||
| 550 | unsigned int trigger_grp6 : 1; | ||
| 551 | unsigned int timer_grp0 : 1; | ||
| 552 | unsigned int fifo_out : 1; | ||
| 553 | unsigned int spu_intr15 : 1; | ||
| 554 | unsigned int trigger_grp7 : 1; | ||
| 555 | unsigned int timer_grp1 : 1; | ||
| 556 | unsigned int fifo_in : 1; | ||
| 557 | unsigned int dummy1 : 16; | ||
| 558 | } reg_iop_sw_mpu_rw_intr_grp3_mask; | ||
| 559 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 | ||
| 560 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 | ||
| 561 | |||
| 562 | /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ | ||
| 563 | typedef struct { | ||
| 564 | unsigned int spu_intr12 : 1; | ||
| 565 | unsigned int dummy1 : 3; | ||
| 566 | unsigned int spu_intr13 : 1; | ||
| 567 | unsigned int dummy2 : 3; | ||
| 568 | unsigned int spu_intr14 : 1; | ||
| 569 | unsigned int dummy3 : 3; | ||
| 570 | unsigned int spu_intr15 : 1; | ||
| 571 | unsigned int dummy4 : 19; | ||
| 572 | } reg_iop_sw_mpu_rw_ack_intr_grp3; | ||
| 573 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 | ||
| 574 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 | ||
| 575 | |||
| 576 | /* Register r_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 577 | typedef struct { | ||
| 578 | unsigned int spu_intr12 : 1; | ||
| 579 | unsigned int trigger_grp4 : 1; | ||
| 580 | unsigned int fifo_out_extra : 1; | ||
| 581 | unsigned int dmc_out : 1; | ||
| 582 | unsigned int spu_intr13 : 1; | ||
| 583 | unsigned int trigger_grp5 : 1; | ||
| 584 | unsigned int fifo_in_extra : 1; | ||
| 585 | unsigned int dmc_in : 1; | ||
| 586 | unsigned int spu_intr14 : 1; | ||
| 587 | unsigned int trigger_grp6 : 1; | ||
| 588 | unsigned int timer_grp0 : 1; | ||
| 589 | unsigned int fifo_out : 1; | ||
| 590 | unsigned int spu_intr15 : 1; | ||
| 591 | unsigned int trigger_grp7 : 1; | ||
| 592 | unsigned int timer_grp1 : 1; | ||
| 593 | unsigned int fifo_in : 1; | ||
| 594 | unsigned int dummy1 : 16; | ||
| 595 | } reg_iop_sw_mpu_r_intr_grp3; | ||
| 596 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 | ||
| 597 | |||
| 598 | /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 599 | typedef struct { | ||
| 600 | unsigned int spu_intr12 : 1; | ||
| 601 | unsigned int trigger_grp4 : 1; | ||
| 602 | unsigned int fifo_out_extra : 1; | ||
| 603 | unsigned int dmc_out : 1; | ||
| 604 | unsigned int spu_intr13 : 1; | ||
| 605 | unsigned int trigger_grp5 : 1; | ||
| 606 | unsigned int fifo_in_extra : 1; | ||
| 607 | unsigned int dmc_in : 1; | ||
| 608 | unsigned int spu_intr14 : 1; | ||
| 609 | unsigned int trigger_grp6 : 1; | ||
| 610 | unsigned int timer_grp0 : 1; | ||
| 611 | unsigned int fifo_out : 1; | ||
| 612 | unsigned int spu_intr15 : 1; | ||
| 613 | unsigned int trigger_grp7 : 1; | ||
| 614 | unsigned int timer_grp1 : 1; | ||
| 615 | unsigned int fifo_in : 1; | ||
| 616 | unsigned int dummy1 : 16; | ||
| 617 | } reg_iop_sw_mpu_r_masked_intr_grp3; | ||
| 618 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 | ||
| 619 | |||
| 620 | |||
| 621 | /* Constants */ | ||
| 622 | enum { | ||
| 623 | regk_iop_sw_mpu_copy = 0x00000000, | ||
| 624 | regk_iop_sw_mpu_cpu = 0x00000000, | ||
| 625 | regk_iop_sw_mpu_mpu = 0x00000001, | ||
| 626 | regk_iop_sw_mpu_no = 0x00000000, | ||
| 627 | regk_iop_sw_mpu_nop = 0x00000000, | ||
| 628 | regk_iop_sw_mpu_rd = 0x00000002, | ||
| 629 | regk_iop_sw_mpu_reg_copy = 0x00000001, | ||
| 630 | regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, | ||
| 631 | regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
| 632 | regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, | ||
| 633 | regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, | ||
| 634 | regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, | ||
| 635 | regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 636 | regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 637 | regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, | ||
| 638 | regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, | ||
| 639 | regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, | ||
| 640 | regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, | ||
| 641 | regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, | ||
| 642 | regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, | ||
| 643 | regk_iop_sw_mpu_set = 0x00000001, | ||
| 644 | regk_iop_sw_mpu_spu = 0x00000002, | ||
| 645 | regk_iop_sw_mpu_wr = 0x00000003, | ||
| 646 | regk_iop_sw_mpu_yes = 0x00000001 | ||
| 647 | }; | ||
| 648 | #endif /* __iop_sw_mpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index c8560b865a1a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null | |||
| @@ -1,441 +0,0 @@ | |||
| 1 | #ifndef __iop_sw_spu_defs_h | ||
| 2 | #define __iop_sw_spu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_spu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sw_spu */ | ||
| 83 | |||
| 84 | /* Register r_mpu_trace, scope iop_sw_spu, type r */ | ||
| 85 | typedef unsigned int reg_iop_sw_spu_r_mpu_trace; | ||
| 86 | #define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 | ||
| 87 | |||
| 88 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | ||
| 89 | typedef struct { | ||
| 90 | unsigned int keep_owner : 1; | ||
| 91 | unsigned int cmd : 2; | ||
| 92 | unsigned int size : 3; | ||
| 93 | unsigned int wr_spu_mem : 1; | ||
| 94 | unsigned int dummy1 : 25; | ||
| 95 | } reg_iop_sw_spu_rw_mc_ctrl; | ||
| 96 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 | ||
| 97 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 | ||
| 98 | |||
| 99 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | ||
| 100 | typedef struct { | ||
| 101 | unsigned int val : 32; | ||
| 102 | } reg_iop_sw_spu_rw_mc_data; | ||
| 103 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 | ||
| 104 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 | ||
| 105 | |||
| 106 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | ||
| 107 | typedef unsigned int reg_iop_sw_spu_rw_mc_addr; | ||
| 108 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 | ||
| 109 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 | ||
| 110 | |||
| 111 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | ||
| 112 | typedef unsigned int reg_iop_sw_spu_rs_mc_data; | ||
| 113 | #define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 | ||
| 114 | |||
| 115 | /* Register r_mc_data, scope iop_sw_spu, type r */ | ||
| 116 | typedef unsigned int reg_iop_sw_spu_r_mc_data; | ||
| 117 | #define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 | ||
| 118 | |||
| 119 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | ||
| 120 | typedef struct { | ||
| 121 | unsigned int busy_cpu : 1; | ||
| 122 | unsigned int busy_mpu : 1; | ||
| 123 | unsigned int busy_spu : 1; | ||
| 124 | unsigned int owned_by_cpu : 1; | ||
| 125 | unsigned int owned_by_mpu : 1; | ||
| 126 | unsigned int owned_by_spu : 1; | ||
| 127 | unsigned int dummy1 : 26; | ||
| 128 | } reg_iop_sw_spu_r_mc_stat; | ||
| 129 | #define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 | ||
| 130 | |||
| 131 | /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int byte0 : 8; | ||
| 134 | unsigned int byte1 : 8; | ||
| 135 | unsigned int byte2 : 8; | ||
| 136 | unsigned int byte3 : 8; | ||
| 137 | } reg_iop_sw_spu_rw_bus_clr_mask; | ||
| 138 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 | ||
| 139 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 | ||
| 140 | |||
| 141 | /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ | ||
| 142 | typedef struct { | ||
| 143 | unsigned int byte0 : 8; | ||
| 144 | unsigned int byte1 : 8; | ||
| 145 | unsigned int byte2 : 8; | ||
| 146 | unsigned int byte3 : 8; | ||
| 147 | } reg_iop_sw_spu_rw_bus_set_mask; | ||
| 148 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 | ||
| 149 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 | ||
| 150 | |||
| 151 | /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 152 | typedef struct { | ||
| 153 | unsigned int byte0 : 1; | ||
| 154 | unsigned int byte1 : 1; | ||
| 155 | unsigned int byte2 : 1; | ||
| 156 | unsigned int byte3 : 1; | ||
| 157 | unsigned int dummy1 : 28; | ||
| 158 | } reg_iop_sw_spu_rw_bus_oe_clr_mask; | ||
| 159 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 | ||
| 160 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 | ||
| 161 | |||
| 162 | /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int byte0 : 1; | ||
| 165 | unsigned int byte1 : 1; | ||
| 166 | unsigned int byte2 : 1; | ||
| 167 | unsigned int byte3 : 1; | ||
| 168 | unsigned int dummy1 : 28; | ||
| 169 | } reg_iop_sw_spu_rw_bus_oe_set_mask; | ||
| 170 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 | ||
| 171 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 | ||
| 172 | |||
| 173 | /* Register r_bus_in, scope iop_sw_spu, type r */ | ||
| 174 | typedef unsigned int reg_iop_sw_spu_r_bus_in; | ||
| 175 | #define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 | ||
| 176 | |||
| 177 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int val : 32; | ||
| 180 | } reg_iop_sw_spu_rw_gio_clr_mask; | ||
| 181 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 | ||
| 182 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 | ||
| 183 | |||
| 184 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | ||
| 185 | typedef struct { | ||
| 186 | unsigned int val : 32; | ||
| 187 | } reg_iop_sw_spu_rw_gio_set_mask; | ||
| 188 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 | ||
| 189 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 | ||
| 190 | |||
| 191 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int val : 32; | ||
| 194 | } reg_iop_sw_spu_rw_gio_oe_clr_mask; | ||
| 195 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 | ||
| 196 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 | ||
| 197 | |||
| 198 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 199 | typedef struct { | ||
| 200 | unsigned int val : 32; | ||
| 201 | } reg_iop_sw_spu_rw_gio_oe_set_mask; | ||
| 202 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 | ||
| 203 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 | ||
| 204 | |||
| 205 | /* Register r_gio_in, scope iop_sw_spu, type r */ | ||
| 206 | typedef unsigned int reg_iop_sw_spu_r_gio_in; | ||
| 207 | #define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 | ||
| 208 | |||
| 209 | /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 210 | typedef struct { | ||
| 211 | unsigned int byte0 : 8; | ||
| 212 | unsigned int byte1 : 8; | ||
| 213 | unsigned int dummy1 : 16; | ||
| 214 | } reg_iop_sw_spu_rw_bus_clr_mask_lo; | ||
| 215 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 | ||
| 216 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 | ||
| 217 | |||
| 218 | /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 219 | typedef struct { | ||
| 220 | unsigned int byte2 : 8; | ||
| 221 | unsigned int byte3 : 8; | ||
| 222 | unsigned int dummy1 : 16; | ||
| 223 | } reg_iop_sw_spu_rw_bus_clr_mask_hi; | ||
| 224 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 | ||
| 225 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 | ||
| 226 | |||
| 227 | /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 228 | typedef struct { | ||
| 229 | unsigned int byte0 : 8; | ||
| 230 | unsigned int byte1 : 8; | ||
| 231 | unsigned int dummy1 : 16; | ||
| 232 | } reg_iop_sw_spu_rw_bus_set_mask_lo; | ||
| 233 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 | ||
| 234 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 | ||
| 235 | |||
| 236 | /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int byte2 : 8; | ||
| 239 | unsigned int byte3 : 8; | ||
| 240 | unsigned int dummy1 : 16; | ||
| 241 | } reg_iop_sw_spu_rw_bus_set_mask_hi; | ||
| 242 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 | ||
| 243 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 | ||
| 244 | |||
| 245 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 246 | typedef struct { | ||
| 247 | unsigned int val : 16; | ||
| 248 | unsigned int dummy1 : 16; | ||
| 249 | } reg_iop_sw_spu_rw_gio_clr_mask_lo; | ||
| 250 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 | ||
| 251 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 | ||
| 252 | |||
| 253 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 254 | typedef struct { | ||
| 255 | unsigned int val : 16; | ||
| 256 | unsigned int dummy1 : 16; | ||
| 257 | } reg_iop_sw_spu_rw_gio_clr_mask_hi; | ||
| 258 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 | ||
| 259 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 | ||
| 260 | |||
| 261 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 262 | typedef struct { | ||
| 263 | unsigned int val : 16; | ||
| 264 | unsigned int dummy1 : 16; | ||
| 265 | } reg_iop_sw_spu_rw_gio_set_mask_lo; | ||
| 266 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 | ||
| 267 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 | ||
| 268 | |||
| 269 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 270 | typedef struct { | ||
| 271 | unsigned int val : 16; | ||
| 272 | unsigned int dummy1 : 16; | ||
| 273 | } reg_iop_sw_spu_rw_gio_set_mask_hi; | ||
| 274 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 | ||
| 275 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 | ||
| 276 | |||
| 277 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 278 | typedef struct { | ||
| 279 | unsigned int val : 16; | ||
| 280 | unsigned int dummy1 : 16; | ||
| 281 | } reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; | ||
| 282 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 | ||
| 283 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 | ||
| 284 | |||
| 285 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 286 | typedef struct { | ||
| 287 | unsigned int val : 16; | ||
| 288 | unsigned int dummy1 : 16; | ||
| 289 | } reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; | ||
| 290 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 | ||
| 291 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 | ||
| 292 | |||
| 293 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 294 | typedef struct { | ||
| 295 | unsigned int val : 16; | ||
| 296 | unsigned int dummy1 : 16; | ||
| 297 | } reg_iop_sw_spu_rw_gio_oe_set_mask_lo; | ||
| 298 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 | ||
| 299 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 | ||
| 300 | |||
| 301 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 302 | typedef struct { | ||
| 303 | unsigned int val : 16; | ||
| 304 | unsigned int dummy1 : 16; | ||
| 305 | } reg_iop_sw_spu_rw_gio_oe_set_mask_hi; | ||
| 306 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 | ||
| 307 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 | ||
| 308 | |||
| 309 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | ||
| 310 | typedef struct { | ||
| 311 | unsigned int intr0 : 1; | ||
| 312 | unsigned int intr1 : 1; | ||
| 313 | unsigned int intr2 : 1; | ||
| 314 | unsigned int intr3 : 1; | ||
| 315 | unsigned int intr4 : 1; | ||
| 316 | unsigned int intr5 : 1; | ||
| 317 | unsigned int intr6 : 1; | ||
| 318 | unsigned int intr7 : 1; | ||
| 319 | unsigned int intr8 : 1; | ||
| 320 | unsigned int intr9 : 1; | ||
| 321 | unsigned int intr10 : 1; | ||
| 322 | unsigned int intr11 : 1; | ||
| 323 | unsigned int intr12 : 1; | ||
| 324 | unsigned int intr13 : 1; | ||
| 325 | unsigned int intr14 : 1; | ||
| 326 | unsigned int intr15 : 1; | ||
| 327 | unsigned int dummy1 : 16; | ||
| 328 | } reg_iop_sw_spu_rw_cpu_intr; | ||
| 329 | #define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 | ||
| 330 | #define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 | ||
| 331 | |||
| 332 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | ||
| 333 | typedef struct { | ||
| 334 | unsigned int intr0 : 1; | ||
| 335 | unsigned int intr1 : 1; | ||
| 336 | unsigned int intr2 : 1; | ||
| 337 | unsigned int intr3 : 1; | ||
| 338 | unsigned int intr4 : 1; | ||
| 339 | unsigned int intr5 : 1; | ||
| 340 | unsigned int intr6 : 1; | ||
| 341 | unsigned int intr7 : 1; | ||
| 342 | unsigned int intr8 : 1; | ||
| 343 | unsigned int intr9 : 1; | ||
| 344 | unsigned int intr10 : 1; | ||
| 345 | unsigned int intr11 : 1; | ||
| 346 | unsigned int intr12 : 1; | ||
| 347 | unsigned int intr13 : 1; | ||
| 348 | unsigned int intr14 : 1; | ||
| 349 | unsigned int intr15 : 1; | ||
| 350 | unsigned int dummy1 : 16; | ||
| 351 | } reg_iop_sw_spu_r_cpu_intr; | ||
| 352 | #define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 | ||
| 353 | |||
| 354 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | ||
| 355 | typedef struct { | ||
| 356 | unsigned int trigger_grp0 : 1; | ||
| 357 | unsigned int trigger_grp1 : 1; | ||
| 358 | unsigned int trigger_grp2 : 1; | ||
| 359 | unsigned int trigger_grp3 : 1; | ||
| 360 | unsigned int trigger_grp4 : 1; | ||
| 361 | unsigned int trigger_grp5 : 1; | ||
| 362 | unsigned int trigger_grp6 : 1; | ||
| 363 | unsigned int trigger_grp7 : 1; | ||
| 364 | unsigned int timer_grp0 : 1; | ||
| 365 | unsigned int timer_grp1 : 1; | ||
| 366 | unsigned int fifo_out : 1; | ||
| 367 | unsigned int fifo_out_extra : 1; | ||
| 368 | unsigned int fifo_in : 1; | ||
| 369 | unsigned int fifo_in_extra : 1; | ||
| 370 | unsigned int dmc_out : 1; | ||
| 371 | unsigned int dmc_in : 1; | ||
| 372 | unsigned int dummy1 : 16; | ||
| 373 | } reg_iop_sw_spu_r_hw_intr; | ||
| 374 | #define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 | ||
| 375 | |||
| 376 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | ||
| 377 | typedef struct { | ||
| 378 | unsigned int intr0 : 1; | ||
| 379 | unsigned int intr1 : 1; | ||
| 380 | unsigned int intr2 : 1; | ||
| 381 | unsigned int intr3 : 1; | ||
| 382 | unsigned int intr4 : 1; | ||
| 383 | unsigned int intr5 : 1; | ||
| 384 | unsigned int intr6 : 1; | ||
| 385 | unsigned int intr7 : 1; | ||
| 386 | unsigned int intr8 : 1; | ||
| 387 | unsigned int intr9 : 1; | ||
| 388 | unsigned int intr10 : 1; | ||
| 389 | unsigned int intr11 : 1; | ||
| 390 | unsigned int intr12 : 1; | ||
| 391 | unsigned int intr13 : 1; | ||
| 392 | unsigned int intr14 : 1; | ||
| 393 | unsigned int intr15 : 1; | ||
| 394 | unsigned int dummy1 : 16; | ||
| 395 | } reg_iop_sw_spu_rw_mpu_intr; | ||
| 396 | #define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 | ||
| 397 | #define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 | ||
| 398 | |||
| 399 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | ||
| 400 | typedef struct { | ||
| 401 | unsigned int intr0 : 1; | ||
| 402 | unsigned int intr1 : 1; | ||
| 403 | unsigned int intr2 : 1; | ||
| 404 | unsigned int intr3 : 1; | ||
| 405 | unsigned int intr4 : 1; | ||
| 406 | unsigned int intr5 : 1; | ||
| 407 | unsigned int intr6 : 1; | ||
| 408 | unsigned int intr7 : 1; | ||
| 409 | unsigned int intr8 : 1; | ||
| 410 | unsigned int intr9 : 1; | ||
| 411 | unsigned int intr10 : 1; | ||
| 412 | unsigned int intr11 : 1; | ||
| 413 | unsigned int intr12 : 1; | ||
| 414 | unsigned int intr13 : 1; | ||
| 415 | unsigned int intr14 : 1; | ||
| 416 | unsigned int intr15 : 1; | ||
| 417 | unsigned int dummy1 : 16; | ||
| 418 | } reg_iop_sw_spu_r_mpu_intr; | ||
| 419 | #define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 | ||
| 420 | |||
| 421 | |||
| 422 | /* Constants */ | ||
| 423 | enum { | ||
| 424 | regk_iop_sw_spu_copy = 0x00000000, | ||
| 425 | regk_iop_sw_spu_no = 0x00000000, | ||
| 426 | regk_iop_sw_spu_nop = 0x00000000, | ||
| 427 | regk_iop_sw_spu_rd = 0x00000002, | ||
| 428 | regk_iop_sw_spu_reg_copy = 0x00000001, | ||
| 429 | regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, | ||
| 430 | regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
| 431 | regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, | ||
| 432 | regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, | ||
| 433 | regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, | ||
| 434 | regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 435 | regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 436 | regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, | ||
| 437 | regk_iop_sw_spu_set = 0x00000001, | ||
| 438 | regk_iop_sw_spu_wr = 0x00000003, | ||
| 439 | regk_iop_sw_spu_yes = 0x00000001 | ||
| 440 | }; | ||
| 441 | #endif /* __iop_sw_spu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h deleted file mode 100644 index 20de425e652b..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | #ifndef __iop_version_defs_h | ||
| 2 | #define __iop_version_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_version.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_version */ | ||
| 83 | |||
| 84 | /* Register r_version, scope iop_version, type r */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int nr : 8; | ||
| 87 | unsigned int dummy1 : 24; | ||
| 88 | } reg_iop_version_r_version; | ||
| 89 | #define REG_RD_ADDR_iop_version_r_version 0 | ||
| 90 | |||
| 91 | |||
| 92 | /* Constants */ | ||
| 93 | enum { | ||
| 94 | regk_iop_version_v2_0 = 0x00000002 | ||
| 95 | }; | ||
| 96 | #endif /* __iop_version_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h deleted file mode 100644 index 243ac3c882cb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h +++ /dev/null | |||
| @@ -1,142 +0,0 @@ | |||
| 1 | #ifndef __l2cache_defs_h | ||
| 2 | #define __l2cache_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: l2cache.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope l2cache */ | ||
| 83 | |||
| 84 | /* Register rw_cfg, scope l2cache, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int en : 1; | ||
| 87 | unsigned int dummy1 : 31; | ||
| 88 | } reg_l2cache_rw_cfg; | ||
| 89 | #define REG_RD_ADDR_l2cache_rw_cfg 0 | ||
| 90 | #define REG_WR_ADDR_l2cache_rw_cfg 0 | ||
| 91 | |||
| 92 | /* Register rw_ctrl, scope l2cache, type rw */ | ||
| 93 | typedef struct { | ||
| 94 | unsigned int dummy1 : 7; | ||
| 95 | unsigned int cbase : 9; | ||
| 96 | unsigned int dummy2 : 4; | ||
| 97 | unsigned int csize : 10; | ||
| 98 | unsigned int dummy3 : 2; | ||
| 99 | } reg_l2cache_rw_ctrl; | ||
| 100 | #define REG_RD_ADDR_l2cache_rw_ctrl 4 | ||
| 101 | #define REG_WR_ADDR_l2cache_rw_ctrl 4 | ||
| 102 | |||
| 103 | /* Register rw_idxop, scope l2cache, type rw */ | ||
| 104 | typedef struct { | ||
| 105 | unsigned int idx : 10; | ||
| 106 | unsigned int dummy1 : 14; | ||
| 107 | unsigned int way : 3; | ||
| 108 | unsigned int dummy2 : 2; | ||
| 109 | unsigned int cmd : 3; | ||
| 110 | } reg_l2cache_rw_idxop; | ||
| 111 | #define REG_RD_ADDR_l2cache_rw_idxop 8 | ||
| 112 | #define REG_WR_ADDR_l2cache_rw_idxop 8 | ||
| 113 | |||
| 114 | /* Register rw_addrop_addr, scope l2cache, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int addr : 32; | ||
| 117 | } reg_l2cache_rw_addrop_addr; | ||
| 118 | #define REG_RD_ADDR_l2cache_rw_addrop_addr 12 | ||
| 119 | #define REG_WR_ADDR_l2cache_rw_addrop_addr 12 | ||
| 120 | |||
| 121 | /* Register rw_addrop_ctrl, scope l2cache, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int size : 16; | ||
| 124 | unsigned int dummy1 : 13; | ||
| 125 | unsigned int cmd : 3; | ||
| 126 | } reg_l2cache_rw_addrop_ctrl; | ||
| 127 | #define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 | ||
| 128 | #define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 | ||
| 129 | |||
| 130 | |||
| 131 | /* Constants */ | ||
| 132 | enum { | ||
| 133 | regk_l2cache_flush = 0x00000001, | ||
| 134 | regk_l2cache_no = 0x00000000, | ||
| 135 | regk_l2cache_rw_addrop_addr_default = 0x00000000, | ||
| 136 | regk_l2cache_rw_addrop_ctrl_default = 0x00000000, | ||
| 137 | regk_l2cache_rw_cfg_default = 0x00000000, | ||
| 138 | regk_l2cache_rw_ctrl_default = 0x00000000, | ||
| 139 | regk_l2cache_rw_idxop_default = 0x00000000, | ||
| 140 | regk_l2cache_yes = 0x00000001 | ||
| 141 | }; | ||
| 142 | #endif /* __l2cache_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h deleted file mode 100644 index c0e7628cbf7d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h +++ /dev/null | |||
| @@ -1,482 +0,0 @@ | |||
| 1 | #ifndef __marb_bar_defs_h | ||
| 2 | #define __marb_bar_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: marb_bar.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope marb_bar */ | ||
| 83 | |||
| 84 | #define STRIDE_marb_bar_rw_ddr2_slots 4 | ||
| 85 | /* Register rw_ddr2_slots, scope marb_bar, type rw */ | ||
| 86 | typedef struct { | ||
| 87 | unsigned int owner : 4; | ||
| 88 | unsigned int dummy1 : 28; | ||
| 89 | } reg_marb_bar_rw_ddr2_slots; | ||
| 90 | #define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 | ||
| 91 | #define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 | ||
| 92 | |||
| 93 | /* Register rw_h264_rd_burst, scope marb_bar, type rw */ | ||
| 94 | typedef struct { | ||
| 95 | unsigned int ddr2_bsize : 2; | ||
| 96 | unsigned int dummy1 : 30; | ||
| 97 | } reg_marb_bar_rw_h264_rd_burst; | ||
| 98 | #define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 | ||
| 99 | #define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 | ||
| 100 | |||
| 101 | /* Register rw_h264_wr_burst, scope marb_bar, type rw */ | ||
| 102 | typedef struct { | ||
| 103 | unsigned int ddr2_bsize : 2; | ||
| 104 | unsigned int dummy1 : 30; | ||
| 105 | } reg_marb_bar_rw_h264_wr_burst; | ||
| 106 | #define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 | ||
| 107 | #define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 | ||
| 108 | |||
| 109 | /* Register rw_ccd_burst, scope marb_bar, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int ddr2_bsize : 2; | ||
| 112 | unsigned int dummy1 : 30; | ||
| 113 | } reg_marb_bar_rw_ccd_burst; | ||
| 114 | #define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 | ||
| 115 | #define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 | ||
| 116 | |||
| 117 | /* Register rw_vin_wr_burst, scope marb_bar, type rw */ | ||
| 118 | typedef struct { | ||
| 119 | unsigned int ddr2_bsize : 2; | ||
| 120 | unsigned int dummy1 : 30; | ||
| 121 | } reg_marb_bar_rw_vin_wr_burst; | ||
| 122 | #define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 | ||
| 123 | #define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 | ||
| 124 | |||
| 125 | /* Register rw_vin_rd_burst, scope marb_bar, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int ddr2_bsize : 2; | ||
| 128 | unsigned int dummy1 : 30; | ||
| 129 | } reg_marb_bar_rw_vin_rd_burst; | ||
| 130 | #define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 | ||
| 131 | #define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 | ||
| 132 | |||
| 133 | /* Register rw_sclr_rd_burst, scope marb_bar, type rw */ | ||
| 134 | typedef struct { | ||
| 135 | unsigned int ddr2_bsize : 2; | ||
| 136 | unsigned int dummy1 : 30; | ||
| 137 | } reg_marb_bar_rw_sclr_rd_burst; | ||
| 138 | #define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 | ||
| 139 | #define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 | ||
| 140 | |||
| 141 | /* Register rw_vout_burst, scope marb_bar, type rw */ | ||
| 142 | typedef struct { | ||
| 143 | unsigned int ddr2_bsize : 2; | ||
| 144 | unsigned int dummy1 : 30; | ||
| 145 | } reg_marb_bar_rw_vout_burst; | ||
| 146 | #define REG_RD_ADDR_marb_bar_rw_vout_burst 280 | ||
| 147 | #define REG_WR_ADDR_marb_bar_rw_vout_burst 280 | ||
| 148 | |||
| 149 | /* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ | ||
| 150 | typedef struct { | ||
| 151 | unsigned int ddr2_bsize : 2; | ||
| 152 | unsigned int dummy1 : 30; | ||
| 153 | } reg_marb_bar_rw_sclr_fifo_burst; | ||
| 154 | #define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 | ||
| 155 | #define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 | ||
| 156 | |||
| 157 | /* Register rw_l2cache_burst, scope marb_bar, type rw */ | ||
| 158 | typedef struct { | ||
| 159 | unsigned int ddr2_bsize : 2; | ||
| 160 | unsigned int dummy1 : 30; | ||
| 161 | } reg_marb_bar_rw_l2cache_burst; | ||
| 162 | #define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 | ||
| 163 | #define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 | ||
| 164 | |||
| 165 | /* Register rw_intr_mask, scope marb_bar, type rw */ | ||
| 166 | typedef struct { | ||
| 167 | unsigned int bp0 : 1; | ||
| 168 | unsigned int bp1 : 1; | ||
| 169 | unsigned int bp2 : 1; | ||
| 170 | unsigned int bp3 : 1; | ||
| 171 | unsigned int dummy1 : 28; | ||
| 172 | } reg_marb_bar_rw_intr_mask; | ||
| 173 | #define REG_RD_ADDR_marb_bar_rw_intr_mask 292 | ||
| 174 | #define REG_WR_ADDR_marb_bar_rw_intr_mask 292 | ||
| 175 | |||
| 176 | /* Register rw_ack_intr, scope marb_bar, type rw */ | ||
| 177 | typedef struct { | ||
| 178 | unsigned int bp0 : 1; | ||
| 179 | unsigned int bp1 : 1; | ||
| 180 | unsigned int bp2 : 1; | ||
| 181 | unsigned int bp3 : 1; | ||
| 182 | unsigned int dummy1 : 28; | ||
| 183 | } reg_marb_bar_rw_ack_intr; | ||
| 184 | #define REG_RD_ADDR_marb_bar_rw_ack_intr 296 | ||
| 185 | #define REG_WR_ADDR_marb_bar_rw_ack_intr 296 | ||
| 186 | |||
| 187 | /* Register r_intr, scope marb_bar, type r */ | ||
| 188 | typedef struct { | ||
| 189 | unsigned int bp0 : 1; | ||
| 190 | unsigned int bp1 : 1; | ||
| 191 | unsigned int bp2 : 1; | ||
| 192 | unsigned int bp3 : 1; | ||
| 193 | unsigned int dummy1 : 28; | ||
| 194 | } reg_marb_bar_r_intr; | ||
| 195 | #define REG_RD_ADDR_marb_bar_r_intr 300 | ||
| 196 | |||
| 197 | /* Register r_masked_intr, scope marb_bar, type r */ | ||
| 198 | typedef struct { | ||
| 199 | unsigned int bp0 : 1; | ||
| 200 | unsigned int bp1 : 1; | ||
| 201 | unsigned int bp2 : 1; | ||
| 202 | unsigned int bp3 : 1; | ||
| 203 | unsigned int dummy1 : 28; | ||
| 204 | } reg_marb_bar_r_masked_intr; | ||
| 205 | #define REG_RD_ADDR_marb_bar_r_masked_intr 304 | ||
| 206 | |||
| 207 | /* Register rw_stop_mask, scope marb_bar, type rw */ | ||
| 208 | typedef struct { | ||
| 209 | unsigned int h264_rd : 1; | ||
| 210 | unsigned int h264_wr : 1; | ||
| 211 | unsigned int ccd : 1; | ||
| 212 | unsigned int vin_wr : 1; | ||
| 213 | unsigned int vin_rd : 1; | ||
| 214 | unsigned int sclr_rd : 1; | ||
| 215 | unsigned int vout : 1; | ||
| 216 | unsigned int sclr_fifo : 1; | ||
| 217 | unsigned int l2cache : 1; | ||
| 218 | unsigned int dummy1 : 23; | ||
| 219 | } reg_marb_bar_rw_stop_mask; | ||
| 220 | #define REG_RD_ADDR_marb_bar_rw_stop_mask 308 | ||
| 221 | #define REG_WR_ADDR_marb_bar_rw_stop_mask 308 | ||
| 222 | |||
| 223 | /* Register r_stopped, scope marb_bar, type r */ | ||
| 224 | typedef struct { | ||
| 225 | unsigned int h264_rd : 1; | ||
| 226 | unsigned int h264_wr : 1; | ||
| 227 | unsigned int ccd : 1; | ||
| 228 | unsigned int vin_wr : 1; | ||
| 229 | unsigned int vin_rd : 1; | ||
| 230 | unsigned int sclr_rd : 1; | ||
| 231 | unsigned int vout : 1; | ||
| 232 | unsigned int sclr_fifo : 1; | ||
| 233 | unsigned int l2cache : 1; | ||
| 234 | unsigned int dummy1 : 23; | ||
| 235 | } reg_marb_bar_r_stopped; | ||
| 236 | #define REG_RD_ADDR_marb_bar_r_stopped 312 | ||
| 237 | |||
| 238 | /* Register rw_no_snoop, scope marb_bar, type rw */ | ||
| 239 | typedef struct { | ||
| 240 | unsigned int h264_rd : 1; | ||
| 241 | unsigned int h264_wr : 1; | ||
| 242 | unsigned int ccd : 1; | ||
| 243 | unsigned int vin_wr : 1; | ||
| 244 | unsigned int vin_rd : 1; | ||
| 245 | unsigned int sclr_rd : 1; | ||
| 246 | unsigned int vout : 1; | ||
| 247 | unsigned int sclr_fifo : 1; | ||
| 248 | unsigned int l2cache : 1; | ||
| 249 | unsigned int dummy1 : 23; | ||
| 250 | } reg_marb_bar_rw_no_snoop; | ||
| 251 | #define REG_RD_ADDR_marb_bar_rw_no_snoop 576 | ||
| 252 | #define REG_WR_ADDR_marb_bar_rw_no_snoop 576 | ||
| 253 | |||
| 254 | |||
| 255 | /* Constants */ | ||
| 256 | enum { | ||
| 257 | regk_marb_bar_ccd = 0x00000002, | ||
| 258 | regk_marb_bar_h264_rd = 0x00000000, | ||
| 259 | regk_marb_bar_h264_wr = 0x00000001, | ||
| 260 | regk_marb_bar_l2cache = 0x00000008, | ||
| 261 | regk_marb_bar_no = 0x00000000, | ||
| 262 | regk_marb_bar_r_stopped_default = 0x00000000, | ||
| 263 | regk_marb_bar_rw_ccd_burst_default = 0x00000000, | ||
| 264 | regk_marb_bar_rw_ddr2_slots_default = 0x00000000, | ||
| 265 | regk_marb_bar_rw_ddr2_slots_size = 0x00000040, | ||
| 266 | regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, | ||
| 267 | regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, | ||
| 268 | regk_marb_bar_rw_intr_mask_default = 0x00000000, | ||
| 269 | regk_marb_bar_rw_l2cache_burst_default = 0x00000000, | ||
| 270 | regk_marb_bar_rw_no_snoop_default = 0x00000000, | ||
| 271 | regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, | ||
| 272 | regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, | ||
| 273 | regk_marb_bar_rw_stop_mask_default = 0x00000000, | ||
| 274 | regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, | ||
| 275 | regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, | ||
| 276 | regk_marb_bar_rw_vout_burst_default = 0x00000000, | ||
| 277 | regk_marb_bar_sclr_fifo = 0x00000007, | ||
| 278 | regk_marb_bar_sclr_rd = 0x00000005, | ||
| 279 | regk_marb_bar_vin_rd = 0x00000004, | ||
| 280 | regk_marb_bar_vin_wr = 0x00000003, | ||
| 281 | regk_marb_bar_vout = 0x00000006, | ||
| 282 | regk_marb_bar_yes = 0x00000001 | ||
| 283 | }; | ||
| 284 | #endif /* __marb_bar_defs_h */ | ||
| 285 | #ifndef __marb_bar_bp_defs_h | ||
| 286 | #define __marb_bar_bp_defs_h | ||
| 287 | |||
| 288 | /* | ||
| 289 | * This file is autogenerated from | ||
| 290 | * file: marb_bar.r | ||
| 291 | * | ||
| 292 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r | ||
| 293 | * Any changes here will be lost. | ||
| 294 | * | ||
| 295 | * -*- buffer-read-only: t -*- | ||
| 296 | */ | ||
| 297 | /* Main access macros */ | ||
| 298 | #ifndef REG_RD | ||
| 299 | #define REG_RD( scope, inst, reg ) \ | ||
| 300 | REG_READ( reg_##scope##_##reg, \ | ||
| 301 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 302 | #endif | ||
| 303 | |||
| 304 | #ifndef REG_WR | ||
| 305 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 306 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 307 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 308 | #endif | ||
| 309 | |||
| 310 | #ifndef REG_RD_VECT | ||
| 311 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 312 | REG_READ( reg_##scope##_##reg, \ | ||
| 313 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 314 | (index) * STRIDE_##scope##_##reg ) | ||
| 315 | #endif | ||
| 316 | |||
| 317 | #ifndef REG_WR_VECT | ||
| 318 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 319 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 320 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 321 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 322 | #endif | ||
| 323 | |||
| 324 | #ifndef REG_RD_INT | ||
| 325 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 326 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #ifndef REG_WR_INT | ||
| 330 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 331 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 332 | #endif | ||
| 333 | |||
| 334 | #ifndef REG_RD_INT_VECT | ||
| 335 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 336 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 337 | (index) * STRIDE_##scope##_##reg ) | ||
| 338 | #endif | ||
| 339 | |||
| 340 | #ifndef REG_WR_INT_VECT | ||
| 341 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 342 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 343 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 344 | #endif | ||
| 345 | |||
| 346 | #ifndef REG_TYPE_CONV | ||
| 347 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 348 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 349 | #endif | ||
| 350 | |||
| 351 | #ifndef reg_page_size | ||
| 352 | #define reg_page_size 8192 | ||
| 353 | #endif | ||
| 354 | |||
| 355 | #ifndef REG_ADDR | ||
| 356 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 357 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 358 | #endif | ||
| 359 | |||
| 360 | #ifndef REG_ADDR_VECT | ||
| 361 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 362 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 363 | (index) * STRIDE_##scope##_##reg ) | ||
| 364 | #endif | ||
| 365 | |||
| 366 | /* C-code for register scope marb_bar_bp */ | ||
| 367 | |||
| 368 | /* Register rw_first_addr, scope marb_bar_bp, type rw */ | ||
| 369 | typedef unsigned int reg_marb_bar_bp_rw_first_addr; | ||
| 370 | #define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 | ||
| 371 | #define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 | ||
| 372 | |||
| 373 | /* Register rw_last_addr, scope marb_bar_bp, type rw */ | ||
| 374 | typedef unsigned int reg_marb_bar_bp_rw_last_addr; | ||
| 375 | #define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 | ||
| 376 | #define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 | ||
| 377 | |||
| 378 | /* Register rw_op, scope marb_bar_bp, type rw */ | ||
| 379 | typedef struct { | ||
| 380 | unsigned int rd : 1; | ||
| 381 | unsigned int wr : 1; | ||
| 382 | unsigned int rd_excl : 1; | ||
| 383 | unsigned int pri_wr : 1; | ||
| 384 | unsigned int us_rd : 1; | ||
| 385 | unsigned int us_wr : 1; | ||
| 386 | unsigned int us_rd_excl : 1; | ||
| 387 | unsigned int us_pri_wr : 1; | ||
| 388 | unsigned int dummy1 : 24; | ||
| 389 | } reg_marb_bar_bp_rw_op; | ||
| 390 | #define REG_RD_ADDR_marb_bar_bp_rw_op 8 | ||
| 391 | #define REG_WR_ADDR_marb_bar_bp_rw_op 8 | ||
| 392 | |||
| 393 | /* Register rw_clients, scope marb_bar_bp, type rw */ | ||
| 394 | typedef struct { | ||
| 395 | unsigned int h264_rd : 1; | ||
| 396 | unsigned int h264_wr : 1; | ||
| 397 | unsigned int ccd : 1; | ||
| 398 | unsigned int vin_wr : 1; | ||
| 399 | unsigned int vin_rd : 1; | ||
| 400 | unsigned int sclr_rd : 1; | ||
| 401 | unsigned int vout : 1; | ||
| 402 | unsigned int sclr_fifo : 1; | ||
| 403 | unsigned int l2cache : 1; | ||
| 404 | unsigned int dummy1 : 23; | ||
| 405 | } reg_marb_bar_bp_rw_clients; | ||
| 406 | #define REG_RD_ADDR_marb_bar_bp_rw_clients 12 | ||
| 407 | #define REG_WR_ADDR_marb_bar_bp_rw_clients 12 | ||
| 408 | |||
| 409 | /* Register rw_options, scope marb_bar_bp, type rw */ | ||
| 410 | typedef struct { | ||
| 411 | unsigned int wrap : 1; | ||
| 412 | unsigned int dummy1 : 31; | ||
| 413 | } reg_marb_bar_bp_rw_options; | ||
| 414 | #define REG_RD_ADDR_marb_bar_bp_rw_options 16 | ||
| 415 | #define REG_WR_ADDR_marb_bar_bp_rw_options 16 | ||
| 416 | |||
| 417 | /* Register r_brk_addr, scope marb_bar_bp, type r */ | ||
| 418 | typedef unsigned int reg_marb_bar_bp_r_brk_addr; | ||
| 419 | #define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 | ||
| 420 | |||
| 421 | /* Register r_brk_op, scope marb_bar_bp, type r */ | ||
| 422 | typedef struct { | ||
| 423 | unsigned int rd : 1; | ||
| 424 | unsigned int wr : 1; | ||
| 425 | unsigned int rd_excl : 1; | ||
| 426 | unsigned int pri_wr : 1; | ||
| 427 | unsigned int us_rd : 1; | ||
| 428 | unsigned int us_wr : 1; | ||
| 429 | unsigned int us_rd_excl : 1; | ||
| 430 | unsigned int us_pri_wr : 1; | ||
| 431 | unsigned int dummy1 : 24; | ||
| 432 | } reg_marb_bar_bp_r_brk_op; | ||
| 433 | #define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 | ||
| 434 | |||
| 435 | /* Register r_brk_clients, scope marb_bar_bp, type r */ | ||
| 436 | typedef struct { | ||
| 437 | unsigned int h264_rd : 1; | ||
| 438 | unsigned int h264_wr : 1; | ||
| 439 | unsigned int ccd : 1; | ||
| 440 | unsigned int vin_wr : 1; | ||
| 441 | unsigned int vin_rd : 1; | ||
| 442 | unsigned int sclr_rd : 1; | ||
| 443 | unsigned int vout : 1; | ||
| 444 | unsigned int sclr_fifo : 1; | ||
| 445 | unsigned int l2cache : 1; | ||
| 446 | unsigned int dummy1 : 23; | ||
| 447 | } reg_marb_bar_bp_r_brk_clients; | ||
| 448 | #define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 | ||
| 449 | |||
| 450 | /* Register r_brk_first_client, scope marb_bar_bp, type r */ | ||
| 451 | typedef struct { | ||
| 452 | unsigned int h264_rd : 1; | ||
| 453 | unsigned int h264_wr : 1; | ||
| 454 | unsigned int ccd : 1; | ||
| 455 | unsigned int vin_wr : 1; | ||
| 456 | unsigned int vin_rd : 1; | ||
| 457 | unsigned int sclr_rd : 1; | ||
| 458 | unsigned int vout : 1; | ||
| 459 | unsigned int sclr_fifo : 1; | ||
| 460 | unsigned int l2cache : 1; | ||
| 461 | unsigned int dummy1 : 23; | ||
| 462 | } reg_marb_bar_bp_r_brk_first_client; | ||
| 463 | #define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 | ||
| 464 | |||
| 465 | /* Register r_brk_size, scope marb_bar_bp, type r */ | ||
| 466 | typedef unsigned int reg_marb_bar_bp_r_brk_size; | ||
| 467 | #define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 | ||
| 468 | |||
| 469 | /* Register rw_ack, scope marb_bar_bp, type rw */ | ||
| 470 | typedef unsigned int reg_marb_bar_bp_rw_ack; | ||
| 471 | #define REG_RD_ADDR_marb_bar_bp_rw_ack 40 | ||
| 472 | #define REG_WR_ADDR_marb_bar_bp_rw_ack 40 | ||
| 473 | |||
| 474 | |||
| 475 | /* Constants */ | ||
| 476 | enum { | ||
| 477 | regk_marb_bar_bp_no = 0x00000000, | ||
| 478 | regk_marb_bar_bp_rw_op_default = 0x00000000, | ||
| 479 | regk_marb_bar_bp_rw_options_default = 0x00000000, | ||
| 480 | regk_marb_bar_bp_yes = 0x00000001 | ||
| 481 | }; | ||
| 482 | #endif /* __marb_bar_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h deleted file mode 100644 index 2baa833f109a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h +++ /dev/null | |||
| @@ -1,626 +0,0 @@ | |||
| 1 | #ifndef __marb_foo_defs_h | ||
| 2 | #define __marb_foo_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: marb_foo.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope marb_foo */ | ||
| 83 | |||
| 84 | #define STRIDE_marb_foo_rw_intm_slots 4 | ||
| 85 | /* Register rw_intm_slots, scope marb_foo, type rw */ | ||
| 86 | typedef struct { | ||
| 87 | unsigned int owner : 4; | ||
| 88 | unsigned int dummy1 : 28; | ||
| 89 | } reg_marb_foo_rw_intm_slots; | ||
| 90 | #define REG_RD_ADDR_marb_foo_rw_intm_slots 0 | ||
| 91 | #define REG_WR_ADDR_marb_foo_rw_intm_slots 0 | ||
| 92 | |||
| 93 | #define STRIDE_marb_foo_rw_l2_slots 4 | ||
| 94 | /* Register rw_l2_slots, scope marb_foo, type rw */ | ||
| 95 | typedef struct { | ||
| 96 | unsigned int owner : 4; | ||
| 97 | unsigned int dummy1 : 28; | ||
| 98 | } reg_marb_foo_rw_l2_slots; | ||
| 99 | #define REG_RD_ADDR_marb_foo_rw_l2_slots 256 | ||
| 100 | #define REG_WR_ADDR_marb_foo_rw_l2_slots 256 | ||
| 101 | |||
| 102 | #define STRIDE_marb_foo_rw_regs_slots 4 | ||
| 103 | /* Register rw_regs_slots, scope marb_foo, type rw */ | ||
| 104 | typedef struct { | ||
| 105 | unsigned int owner : 4; | ||
| 106 | unsigned int dummy1 : 28; | ||
| 107 | } reg_marb_foo_rw_regs_slots; | ||
| 108 | #define REG_RD_ADDR_marb_foo_rw_regs_slots 512 | ||
| 109 | #define REG_WR_ADDR_marb_foo_rw_regs_slots 512 | ||
| 110 | |||
| 111 | /* Register rw_sclr_burst, scope marb_foo, type rw */ | ||
| 112 | typedef struct { | ||
| 113 | unsigned int intm_bsize : 2; | ||
| 114 | unsigned int l2_bsize : 2; | ||
| 115 | unsigned int dummy1 : 28; | ||
| 116 | } reg_marb_foo_rw_sclr_burst; | ||
| 117 | #define REG_RD_ADDR_marb_foo_rw_sclr_burst 528 | ||
| 118 | #define REG_WR_ADDR_marb_foo_rw_sclr_burst 528 | ||
| 119 | |||
| 120 | /* Register rw_dma0_burst, scope marb_foo, type rw */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int intm_bsize : 2; | ||
| 123 | unsigned int l2_bsize : 2; | ||
| 124 | unsigned int dummy1 : 28; | ||
| 125 | } reg_marb_foo_rw_dma0_burst; | ||
| 126 | #define REG_RD_ADDR_marb_foo_rw_dma0_burst 532 | ||
| 127 | #define REG_WR_ADDR_marb_foo_rw_dma0_burst 532 | ||
| 128 | |||
| 129 | /* Register rw_dma1_burst, scope marb_foo, type rw */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int intm_bsize : 2; | ||
| 132 | unsigned int l2_bsize : 2; | ||
| 133 | unsigned int dummy1 : 28; | ||
| 134 | } reg_marb_foo_rw_dma1_burst; | ||
| 135 | #define REG_RD_ADDR_marb_foo_rw_dma1_burst 536 | ||
| 136 | #define REG_WR_ADDR_marb_foo_rw_dma1_burst 536 | ||
| 137 | |||
| 138 | /* Register rw_dma2_burst, scope marb_foo, type rw */ | ||
| 139 | typedef struct { | ||
| 140 | unsigned int intm_bsize : 2; | ||
| 141 | unsigned int l2_bsize : 2; | ||
| 142 | unsigned int dummy1 : 28; | ||
| 143 | } reg_marb_foo_rw_dma2_burst; | ||
| 144 | #define REG_RD_ADDR_marb_foo_rw_dma2_burst 540 | ||
| 145 | #define REG_WR_ADDR_marb_foo_rw_dma2_burst 540 | ||
| 146 | |||
| 147 | /* Register rw_dma3_burst, scope marb_foo, type rw */ | ||
| 148 | typedef struct { | ||
| 149 | unsigned int intm_bsize : 2; | ||
| 150 | unsigned int l2_bsize : 2; | ||
| 151 | unsigned int dummy1 : 28; | ||
| 152 | } reg_marb_foo_rw_dma3_burst; | ||
| 153 | #define REG_RD_ADDR_marb_foo_rw_dma3_burst 544 | ||
| 154 | #define REG_WR_ADDR_marb_foo_rw_dma3_burst 544 | ||
| 155 | |||
| 156 | /* Register rw_dma4_burst, scope marb_foo, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int intm_bsize : 2; | ||
| 159 | unsigned int l2_bsize : 2; | ||
| 160 | unsigned int dummy1 : 28; | ||
| 161 | } reg_marb_foo_rw_dma4_burst; | ||
| 162 | #define REG_RD_ADDR_marb_foo_rw_dma4_burst 548 | ||
| 163 | #define REG_WR_ADDR_marb_foo_rw_dma4_burst 548 | ||
| 164 | |||
| 165 | /* Register rw_dma5_burst, scope marb_foo, type rw */ | ||
| 166 | typedef struct { | ||
| 167 | unsigned int intm_bsize : 2; | ||
| 168 | unsigned int l2_bsize : 2; | ||
| 169 | unsigned int dummy1 : 28; | ||
| 170 | } reg_marb_foo_rw_dma5_burst; | ||
| 171 | #define REG_RD_ADDR_marb_foo_rw_dma5_burst 552 | ||
| 172 | #define REG_WR_ADDR_marb_foo_rw_dma5_burst 552 | ||
| 173 | |||
| 174 | /* Register rw_dma6_burst, scope marb_foo, type rw */ | ||
| 175 | typedef struct { | ||
| 176 | unsigned int intm_bsize : 2; | ||
| 177 | unsigned int l2_bsize : 2; | ||
| 178 | unsigned int dummy1 : 28; | ||
| 179 | } reg_marb_foo_rw_dma6_burst; | ||
| 180 | #define REG_RD_ADDR_marb_foo_rw_dma6_burst 556 | ||
| 181 | #define REG_WR_ADDR_marb_foo_rw_dma6_burst 556 | ||
| 182 | |||
| 183 | /* Register rw_dma7_burst, scope marb_foo, type rw */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int intm_bsize : 2; | ||
| 186 | unsigned int l2_bsize : 2; | ||
| 187 | unsigned int dummy1 : 28; | ||
| 188 | } reg_marb_foo_rw_dma7_burst; | ||
| 189 | #define REG_RD_ADDR_marb_foo_rw_dma7_burst 560 | ||
| 190 | #define REG_WR_ADDR_marb_foo_rw_dma7_burst 560 | ||
| 191 | |||
| 192 | /* Register rw_dma9_burst, scope marb_foo, type rw */ | ||
| 193 | typedef struct { | ||
| 194 | unsigned int intm_bsize : 2; | ||
| 195 | unsigned int l2_bsize : 2; | ||
| 196 | unsigned int dummy1 : 28; | ||
| 197 | } reg_marb_foo_rw_dma9_burst; | ||
| 198 | #define REG_RD_ADDR_marb_foo_rw_dma9_burst 564 | ||
| 199 | #define REG_WR_ADDR_marb_foo_rw_dma9_burst 564 | ||
| 200 | |||
| 201 | /* Register rw_dma11_burst, scope marb_foo, type rw */ | ||
| 202 | typedef struct { | ||
| 203 | unsigned int intm_bsize : 2; | ||
| 204 | unsigned int l2_bsize : 2; | ||
| 205 | unsigned int dummy1 : 28; | ||
| 206 | } reg_marb_foo_rw_dma11_burst; | ||
| 207 | #define REG_RD_ADDR_marb_foo_rw_dma11_burst 568 | ||
| 208 | #define REG_WR_ADDR_marb_foo_rw_dma11_burst 568 | ||
| 209 | |||
| 210 | /* Register rw_cpui_burst, scope marb_foo, type rw */ | ||
| 211 | typedef struct { | ||
| 212 | unsigned int intm_bsize : 2; | ||
| 213 | unsigned int l2_bsize : 2; | ||
| 214 | unsigned int dummy1 : 28; | ||
| 215 | } reg_marb_foo_rw_cpui_burst; | ||
| 216 | #define REG_RD_ADDR_marb_foo_rw_cpui_burst 572 | ||
| 217 | #define REG_WR_ADDR_marb_foo_rw_cpui_burst 572 | ||
| 218 | |||
| 219 | /* Register rw_cpud_burst, scope marb_foo, type rw */ | ||
| 220 | typedef struct { | ||
| 221 | unsigned int intm_bsize : 2; | ||
| 222 | unsigned int l2_bsize : 2; | ||
| 223 | unsigned int dummy1 : 28; | ||
| 224 | } reg_marb_foo_rw_cpud_burst; | ||
| 225 | #define REG_RD_ADDR_marb_foo_rw_cpud_burst 576 | ||
| 226 | #define REG_WR_ADDR_marb_foo_rw_cpud_burst 576 | ||
| 227 | |||
| 228 | /* Register rw_iop_burst, scope marb_foo, type rw */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int intm_bsize : 2; | ||
| 231 | unsigned int l2_bsize : 2; | ||
| 232 | unsigned int dummy1 : 28; | ||
| 233 | } reg_marb_foo_rw_iop_burst; | ||
| 234 | #define REG_RD_ADDR_marb_foo_rw_iop_burst 580 | ||
| 235 | #define REG_WR_ADDR_marb_foo_rw_iop_burst 580 | ||
| 236 | |||
| 237 | /* Register rw_ccdstat_burst, scope marb_foo, type rw */ | ||
| 238 | typedef struct { | ||
| 239 | unsigned int intm_bsize : 2; | ||
| 240 | unsigned int l2_bsize : 2; | ||
| 241 | unsigned int dummy1 : 28; | ||
| 242 | } reg_marb_foo_rw_ccdstat_burst; | ||
| 243 | #define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584 | ||
| 244 | #define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584 | ||
| 245 | |||
| 246 | /* Register rw_intr_mask, scope marb_foo, type rw */ | ||
| 247 | typedef struct { | ||
| 248 | unsigned int bp0 : 1; | ||
| 249 | unsigned int bp1 : 1; | ||
| 250 | unsigned int bp2 : 1; | ||
| 251 | unsigned int bp3 : 1; | ||
| 252 | unsigned int dummy1 : 28; | ||
| 253 | } reg_marb_foo_rw_intr_mask; | ||
| 254 | #define REG_RD_ADDR_marb_foo_rw_intr_mask 588 | ||
| 255 | #define REG_WR_ADDR_marb_foo_rw_intr_mask 588 | ||
| 256 | |||
| 257 | /* Register rw_ack_intr, scope marb_foo, type rw */ | ||
| 258 | typedef struct { | ||
| 259 | unsigned int bp0 : 1; | ||
| 260 | unsigned int bp1 : 1; | ||
| 261 | unsigned int bp2 : 1; | ||
| 262 | unsigned int bp3 : 1; | ||
| 263 | unsigned int dummy1 : 28; | ||
| 264 | } reg_marb_foo_rw_ack_intr; | ||
| 265 | #define REG_RD_ADDR_marb_foo_rw_ack_intr 592 | ||
| 266 | #define REG_WR_ADDR_marb_foo_rw_ack_intr 592 | ||
| 267 | |||
| 268 | /* Register r_intr, scope marb_foo, type r */ | ||
| 269 | typedef struct { | ||
| 270 | unsigned int bp0 : 1; | ||
| 271 | unsigned int bp1 : 1; | ||
| 272 | unsigned int bp2 : 1; | ||
| 273 | unsigned int bp3 : 1; | ||
| 274 | unsigned int dummy1 : 28; | ||
| 275 | } reg_marb_foo_r_intr; | ||
| 276 | #define REG_RD_ADDR_marb_foo_r_intr 596 | ||
| 277 | |||
| 278 | /* Register r_masked_intr, scope marb_foo, type r */ | ||
| 279 | typedef struct { | ||
| 280 | unsigned int bp0 : 1; | ||
| 281 | unsigned int bp1 : 1; | ||
| 282 | unsigned int bp2 : 1; | ||
| 283 | unsigned int bp3 : 1; | ||
| 284 | unsigned int dummy1 : 28; | ||
| 285 | } reg_marb_foo_r_masked_intr; | ||
| 286 | #define REG_RD_ADDR_marb_foo_r_masked_intr 600 | ||
| 287 | |||
| 288 | /* Register rw_stop_mask, scope marb_foo, type rw */ | ||
| 289 | typedef struct { | ||
| 290 | unsigned int sclr : 1; | ||
| 291 | unsigned int dma0 : 1; | ||
| 292 | unsigned int dma1 : 1; | ||
| 293 | unsigned int dma2 : 1; | ||
| 294 | unsigned int dma3 : 1; | ||
| 295 | unsigned int dma4 : 1; | ||
| 296 | unsigned int dma5 : 1; | ||
| 297 | unsigned int dma6 : 1; | ||
| 298 | unsigned int dma7 : 1; | ||
| 299 | unsigned int dma9 : 1; | ||
| 300 | unsigned int dma11 : 1; | ||
| 301 | unsigned int cpui : 1; | ||
| 302 | unsigned int cpud : 1; | ||
| 303 | unsigned int iop : 1; | ||
| 304 | unsigned int ccdstat : 1; | ||
| 305 | unsigned int dummy1 : 17; | ||
| 306 | } reg_marb_foo_rw_stop_mask; | ||
| 307 | #define REG_RD_ADDR_marb_foo_rw_stop_mask 604 | ||
| 308 | #define REG_WR_ADDR_marb_foo_rw_stop_mask 604 | ||
| 309 | |||
| 310 | /* Register r_stopped, scope marb_foo, type r */ | ||
| 311 | typedef struct { | ||
| 312 | unsigned int sclr : 1; | ||
| 313 | unsigned int dma0 : 1; | ||
| 314 | unsigned int dma1 : 1; | ||
| 315 | unsigned int dma2 : 1; | ||
| 316 | unsigned int dma3 : 1; | ||
| 317 | unsigned int dma4 : 1; | ||
| 318 | unsigned int dma5 : 1; | ||
| 319 | unsigned int dma6 : 1; | ||
| 320 | unsigned int dma7 : 1; | ||
| 321 | unsigned int dma9 : 1; | ||
| 322 | unsigned int dma11 : 1; | ||
| 323 | unsigned int cpui : 1; | ||
| 324 | unsigned int cpud : 1; | ||
| 325 | unsigned int iop : 1; | ||
| 326 | unsigned int ccdstat : 1; | ||
| 327 | unsigned int dummy1 : 17; | ||
| 328 | } reg_marb_foo_r_stopped; | ||
| 329 | #define REG_RD_ADDR_marb_foo_r_stopped 608 | ||
| 330 | |||
| 331 | /* Register rw_no_snoop, scope marb_foo, type rw */ | ||
| 332 | typedef struct { | ||
| 333 | unsigned int sclr : 1; | ||
| 334 | unsigned int dma0 : 1; | ||
| 335 | unsigned int dma1 : 1; | ||
| 336 | unsigned int dma2 : 1; | ||
| 337 | unsigned int dma3 : 1; | ||
| 338 | unsigned int dma4 : 1; | ||
| 339 | unsigned int dma5 : 1; | ||
| 340 | unsigned int dma6 : 1; | ||
| 341 | unsigned int dma7 : 1; | ||
| 342 | unsigned int dma9 : 1; | ||
| 343 | unsigned int dma11 : 1; | ||
| 344 | unsigned int cpui : 1; | ||
| 345 | unsigned int cpud : 1; | ||
| 346 | unsigned int iop : 1; | ||
| 347 | unsigned int ccdstat : 1; | ||
| 348 | unsigned int dummy1 : 17; | ||
| 349 | } reg_marb_foo_rw_no_snoop; | ||
| 350 | #define REG_RD_ADDR_marb_foo_rw_no_snoop 896 | ||
| 351 | #define REG_WR_ADDR_marb_foo_rw_no_snoop 896 | ||
| 352 | |||
| 353 | /* Register rw_no_snoop_rq, scope marb_foo, type rw */ | ||
| 354 | typedef struct { | ||
| 355 | unsigned int dummy1 : 11; | ||
| 356 | unsigned int cpui : 1; | ||
| 357 | unsigned int cpud : 1; | ||
| 358 | unsigned int dummy2 : 19; | ||
| 359 | } reg_marb_foo_rw_no_snoop_rq; | ||
| 360 | #define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900 | ||
| 361 | #define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900 | ||
| 362 | |||
| 363 | |||
| 364 | /* Constants */ | ||
| 365 | enum { | ||
| 366 | regk_marb_foo_ccdstat = 0x0000000e, | ||
| 367 | regk_marb_foo_cpud = 0x0000000c, | ||
| 368 | regk_marb_foo_cpui = 0x0000000b, | ||
| 369 | regk_marb_foo_dma0 = 0x00000001, | ||
| 370 | regk_marb_foo_dma1 = 0x00000002, | ||
| 371 | regk_marb_foo_dma11 = 0x0000000a, | ||
| 372 | regk_marb_foo_dma2 = 0x00000003, | ||
| 373 | regk_marb_foo_dma3 = 0x00000004, | ||
| 374 | regk_marb_foo_dma4 = 0x00000005, | ||
| 375 | regk_marb_foo_dma5 = 0x00000006, | ||
| 376 | regk_marb_foo_dma6 = 0x00000007, | ||
| 377 | regk_marb_foo_dma7 = 0x00000008, | ||
| 378 | regk_marb_foo_dma9 = 0x00000009, | ||
| 379 | regk_marb_foo_iop = 0x0000000d, | ||
| 380 | regk_marb_foo_no = 0x00000000, | ||
| 381 | regk_marb_foo_r_stopped_default = 0x00000000, | ||
| 382 | regk_marb_foo_rw_ccdstat_burst_default = 0x00000000, | ||
| 383 | regk_marb_foo_rw_cpud_burst_default = 0x00000000, | ||
| 384 | regk_marb_foo_rw_cpui_burst_default = 0x00000000, | ||
| 385 | regk_marb_foo_rw_dma0_burst_default = 0x00000000, | ||
| 386 | regk_marb_foo_rw_dma11_burst_default = 0x00000000, | ||
| 387 | regk_marb_foo_rw_dma1_burst_default = 0x00000000, | ||
| 388 | regk_marb_foo_rw_dma2_burst_default = 0x00000000, | ||
| 389 | regk_marb_foo_rw_dma3_burst_default = 0x00000000, | ||
| 390 | regk_marb_foo_rw_dma4_burst_default = 0x00000000, | ||
| 391 | regk_marb_foo_rw_dma5_burst_default = 0x00000000, | ||
| 392 | regk_marb_foo_rw_dma6_burst_default = 0x00000000, | ||
| 393 | regk_marb_foo_rw_dma7_burst_default = 0x00000000, | ||
| 394 | regk_marb_foo_rw_dma9_burst_default = 0x00000000, | ||
| 395 | regk_marb_foo_rw_intm_slots_default = 0x00000000, | ||
| 396 | regk_marb_foo_rw_intm_slots_size = 0x00000040, | ||
| 397 | regk_marb_foo_rw_intr_mask_default = 0x00000000, | ||
| 398 | regk_marb_foo_rw_iop_burst_default = 0x00000000, | ||
| 399 | regk_marb_foo_rw_l2_slots_default = 0x00000000, | ||
| 400 | regk_marb_foo_rw_l2_slots_size = 0x00000040, | ||
| 401 | regk_marb_foo_rw_no_snoop_default = 0x00000000, | ||
| 402 | regk_marb_foo_rw_no_snoop_rq_default = 0x00000000, | ||
| 403 | regk_marb_foo_rw_regs_slots_default = 0x00000000, | ||
| 404 | regk_marb_foo_rw_regs_slots_size = 0x00000004, | ||
| 405 | regk_marb_foo_rw_sclr_burst_default = 0x00000000, | ||
| 406 | regk_marb_foo_rw_stop_mask_default = 0x00000000, | ||
| 407 | regk_marb_foo_sclr = 0x00000000, | ||
| 408 | regk_marb_foo_yes = 0x00000001 | ||
| 409 | }; | ||
| 410 | #endif /* __marb_foo_defs_h */ | ||
| 411 | #ifndef __marb_foo_bp_defs_h | ||
| 412 | #define __marb_foo_bp_defs_h | ||
| 413 | |||
| 414 | /* | ||
| 415 | * This file is autogenerated from | ||
| 416 | * file: marb_foo.r | ||
| 417 | * | ||
| 418 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r | ||
| 419 | * Any changes here will be lost. | ||
| 420 | * | ||
| 421 | * -*- buffer-read-only: t -*- | ||
| 422 | */ | ||
| 423 | /* Main access macros */ | ||
| 424 | #ifndef REG_RD | ||
| 425 | #define REG_RD( scope, inst, reg ) \ | ||
| 426 | REG_READ( reg_##scope##_##reg, \ | ||
| 427 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 428 | #endif | ||
| 429 | |||
| 430 | #ifndef REG_WR | ||
| 431 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 432 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 433 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 434 | #endif | ||
| 435 | |||
| 436 | #ifndef REG_RD_VECT | ||
| 437 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 438 | REG_READ( reg_##scope##_##reg, \ | ||
| 439 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 440 | (index) * STRIDE_##scope##_##reg ) | ||
| 441 | #endif | ||
| 442 | |||
| 443 | #ifndef REG_WR_VECT | ||
| 444 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 445 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 446 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 447 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 448 | #endif | ||
| 449 | |||
| 450 | #ifndef REG_RD_INT | ||
| 451 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 452 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 453 | #endif | ||
| 454 | |||
| 455 | #ifndef REG_WR_INT | ||
| 456 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 457 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 458 | #endif | ||
| 459 | |||
| 460 | #ifndef REG_RD_INT_VECT | ||
| 461 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 462 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 463 | (index) * STRIDE_##scope##_##reg ) | ||
| 464 | #endif | ||
| 465 | |||
| 466 | #ifndef REG_WR_INT_VECT | ||
| 467 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 468 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 469 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 470 | #endif | ||
| 471 | |||
| 472 | #ifndef REG_TYPE_CONV | ||
| 473 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 474 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 475 | #endif | ||
| 476 | |||
| 477 | #ifndef reg_page_size | ||
| 478 | #define reg_page_size 8192 | ||
| 479 | #endif | ||
| 480 | |||
| 481 | #ifndef REG_ADDR | ||
| 482 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 483 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 484 | #endif | ||
| 485 | |||
| 486 | #ifndef REG_ADDR_VECT | ||
| 487 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 488 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 489 | (index) * STRIDE_##scope##_##reg ) | ||
| 490 | #endif | ||
| 491 | |||
| 492 | /* C-code for register scope marb_foo_bp */ | ||
| 493 | |||
| 494 | /* Register rw_first_addr, scope marb_foo_bp, type rw */ | ||
| 495 | typedef unsigned int reg_marb_foo_bp_rw_first_addr; | ||
| 496 | #define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0 | ||
| 497 | #define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0 | ||
| 498 | |||
| 499 | /* Register rw_last_addr, scope marb_foo_bp, type rw */ | ||
| 500 | typedef unsigned int reg_marb_foo_bp_rw_last_addr; | ||
| 501 | #define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4 | ||
| 502 | #define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4 | ||
| 503 | |||
| 504 | /* Register rw_op, scope marb_foo_bp, type rw */ | ||
| 505 | typedef struct { | ||
| 506 | unsigned int rd : 1; | ||
| 507 | unsigned int wr : 1; | ||
| 508 | unsigned int rd_excl : 1; | ||
| 509 | unsigned int pri_wr : 1; | ||
| 510 | unsigned int us_rd : 1; | ||
| 511 | unsigned int us_wr : 1; | ||
| 512 | unsigned int us_rd_excl : 1; | ||
| 513 | unsigned int us_pri_wr : 1; | ||
| 514 | unsigned int dummy1 : 24; | ||
| 515 | } reg_marb_foo_bp_rw_op; | ||
| 516 | #define REG_RD_ADDR_marb_foo_bp_rw_op 8 | ||
| 517 | #define REG_WR_ADDR_marb_foo_bp_rw_op 8 | ||
| 518 | |||
| 519 | /* Register rw_clients, scope marb_foo_bp, type rw */ | ||
| 520 | typedef struct { | ||
| 521 | unsigned int sclr : 1; | ||
| 522 | unsigned int dma0 : 1; | ||
| 523 | unsigned int dma1 : 1; | ||
| 524 | unsigned int dma2 : 1; | ||
| 525 | unsigned int dma3 : 1; | ||
| 526 | unsigned int dma4 : 1; | ||
| 527 | unsigned int dma5 : 1; | ||
| 528 | unsigned int dma6 : 1; | ||
| 529 | unsigned int dma7 : 1; | ||
| 530 | unsigned int dma9 : 1; | ||
| 531 | unsigned int dma11 : 1; | ||
| 532 | unsigned int cpui : 1; | ||
| 533 | unsigned int cpud : 1; | ||
| 534 | unsigned int iop : 1; | ||
| 535 | unsigned int ccdstat : 1; | ||
| 536 | unsigned int dummy1 : 17; | ||
| 537 | } reg_marb_foo_bp_rw_clients; | ||
| 538 | #define REG_RD_ADDR_marb_foo_bp_rw_clients 12 | ||
| 539 | #define REG_WR_ADDR_marb_foo_bp_rw_clients 12 | ||
| 540 | |||
| 541 | /* Register rw_options, scope marb_foo_bp, type rw */ | ||
| 542 | typedef struct { | ||
| 543 | unsigned int wrap : 1; | ||
| 544 | unsigned int dummy1 : 31; | ||
| 545 | } reg_marb_foo_bp_rw_options; | ||
| 546 | #define REG_RD_ADDR_marb_foo_bp_rw_options 16 | ||
| 547 | #define REG_WR_ADDR_marb_foo_bp_rw_options 16 | ||
| 548 | |||
| 549 | /* Register r_brk_addr, scope marb_foo_bp, type r */ | ||
| 550 | typedef unsigned int reg_marb_foo_bp_r_brk_addr; | ||
| 551 | #define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20 | ||
| 552 | |||
| 553 | /* Register r_brk_op, scope marb_foo_bp, type r */ | ||
| 554 | typedef struct { | ||
| 555 | unsigned int rd : 1; | ||
| 556 | unsigned int wr : 1; | ||
| 557 | unsigned int rd_excl : 1; | ||
| 558 | unsigned int pri_wr : 1; | ||
| 559 | unsigned int us_rd : 1; | ||
| 560 | unsigned int us_wr : 1; | ||
| 561 | unsigned int us_rd_excl : 1; | ||
| 562 | unsigned int us_pri_wr : 1; | ||
| 563 | unsigned int dummy1 : 24; | ||
| 564 | } reg_marb_foo_bp_r_brk_op; | ||
| 565 | #define REG_RD_ADDR_marb_foo_bp_r_brk_op 24 | ||
| 566 | |||
| 567 | /* Register r_brk_clients, scope marb_foo_bp, type r */ | ||
| 568 | typedef struct { | ||
| 569 | unsigned int sclr : 1; | ||
| 570 | unsigned int dma0 : 1; | ||
| 571 | unsigned int dma1 : 1; | ||
| 572 | unsigned int dma2 : 1; | ||
| 573 | unsigned int dma3 : 1; | ||
| 574 | unsigned int dma4 : 1; | ||
| 575 | unsigned int dma5 : 1; | ||
| 576 | unsigned int dma6 : 1; | ||
| 577 | unsigned int dma7 : 1; | ||
| 578 | unsigned int dma9 : 1; | ||
| 579 | unsigned int dma11 : 1; | ||
| 580 | unsigned int cpui : 1; | ||
| 581 | unsigned int cpud : 1; | ||
| 582 | unsigned int iop : 1; | ||
| 583 | unsigned int ccdstat : 1; | ||
| 584 | unsigned int dummy1 : 17; | ||
| 585 | } reg_marb_foo_bp_r_brk_clients; | ||
| 586 | #define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28 | ||
| 587 | |||
| 588 | /* Register r_brk_first_client, scope marb_foo_bp, type r */ | ||
| 589 | typedef struct { | ||
| 590 | unsigned int sclr : 1; | ||
| 591 | unsigned int dma0 : 1; | ||
| 592 | unsigned int dma1 : 1; | ||
| 593 | unsigned int dma2 : 1; | ||
| 594 | unsigned int dma3 : 1; | ||
| 595 | unsigned int dma4 : 1; | ||
| 596 | unsigned int dma5 : 1; | ||
| 597 | unsigned int dma6 : 1; | ||
| 598 | unsigned int dma7 : 1; | ||
| 599 | unsigned int dma9 : 1; | ||
| 600 | unsigned int dma11 : 1; | ||
| 601 | unsigned int cpui : 1; | ||
| 602 | unsigned int cpud : 1; | ||
| 603 | unsigned int iop : 1; | ||
| 604 | unsigned int ccdstat : 1; | ||
| 605 | unsigned int dummy1 : 17; | ||
| 606 | } reg_marb_foo_bp_r_brk_first_client; | ||
| 607 | #define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32 | ||
| 608 | |||
| 609 | /* Register r_brk_size, scope marb_foo_bp, type r */ | ||
| 610 | typedef unsigned int reg_marb_foo_bp_r_brk_size; | ||
| 611 | #define REG_RD_ADDR_marb_foo_bp_r_brk_size 36 | ||
| 612 | |||
| 613 | /* Register rw_ack, scope marb_foo_bp, type rw */ | ||
| 614 | typedef unsigned int reg_marb_foo_bp_rw_ack; | ||
| 615 | #define REG_RD_ADDR_marb_foo_bp_rw_ack 40 | ||
| 616 | #define REG_WR_ADDR_marb_foo_bp_rw_ack 40 | ||
| 617 | |||
| 618 | |||
| 619 | /* Constants */ | ||
| 620 | enum { | ||
| 621 | regk_marb_foo_bp_no = 0x00000000, | ||
| 622 | regk_marb_foo_bp_rw_op_default = 0x00000000, | ||
| 623 | regk_marb_foo_bp_rw_options_default = 0x00000000, | ||
| 624 | regk_marb_foo_bp_yes = 0x00000001 | ||
| 625 | }; | ||
| 626 | #endif /* __marb_foo_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h deleted file mode 100644 index 4b96cd2cba8a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h +++ /dev/null | |||
| @@ -1,312 +0,0 @@ | |||
| 1 | #ifndef __pinmux_defs_h | ||
| 2 | #define __pinmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: pinmux.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope pinmux */ | ||
| 83 | |||
| 84 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int eth : 1; | ||
| 87 | unsigned int eth_mdio : 1; | ||
| 88 | unsigned int geth : 1; | ||
| 89 | unsigned int tg : 1; | ||
| 90 | unsigned int tg_clk : 1; | ||
| 91 | unsigned int vout : 1; | ||
| 92 | unsigned int vout_sync : 1; | ||
| 93 | unsigned int ser1 : 1; | ||
| 94 | unsigned int ser2 : 1; | ||
| 95 | unsigned int ser3 : 1; | ||
| 96 | unsigned int ser4 : 1; | ||
| 97 | unsigned int sser : 1; | ||
| 98 | unsigned int pwm0 : 1; | ||
| 99 | unsigned int pwm1 : 1; | ||
| 100 | unsigned int pwm2 : 1; | ||
| 101 | unsigned int timer0 : 1; | ||
| 102 | unsigned int timer1 : 1; | ||
| 103 | unsigned int pio : 1; | ||
| 104 | unsigned int i2c0 : 1; | ||
| 105 | unsigned int i2c1 : 1; | ||
| 106 | unsigned int i2c1_sda1 : 1; | ||
| 107 | unsigned int i2c1_sda2 : 1; | ||
| 108 | unsigned int i2c1_sda3 : 1; | ||
| 109 | unsigned int i2c1_sen : 1; | ||
| 110 | unsigned int dummy1 : 8; | ||
| 111 | } reg_pinmux_rw_hwprot; | ||
| 112 | #define REG_RD_ADDR_pinmux_rw_hwprot 0 | ||
| 113 | #define REG_WR_ADDR_pinmux_rw_hwprot 0 | ||
| 114 | |||
| 115 | /* Register rw_gio_pa, scope pinmux, type rw */ | ||
| 116 | typedef struct { | ||
| 117 | unsigned int pa0 : 1; | ||
| 118 | unsigned int pa1 : 1; | ||
| 119 | unsigned int pa2 : 1; | ||
| 120 | unsigned int pa3 : 1; | ||
| 121 | unsigned int pa4 : 1; | ||
| 122 | unsigned int pa5 : 1; | ||
| 123 | unsigned int pa6 : 1; | ||
| 124 | unsigned int pa7 : 1; | ||
| 125 | unsigned int pa8 : 1; | ||
| 126 | unsigned int pa9 : 1; | ||
| 127 | unsigned int pa10 : 1; | ||
| 128 | unsigned int pa11 : 1; | ||
| 129 | unsigned int pa12 : 1; | ||
| 130 | unsigned int pa13 : 1; | ||
| 131 | unsigned int pa14 : 1; | ||
| 132 | unsigned int pa15 : 1; | ||
| 133 | unsigned int pa16 : 1; | ||
| 134 | unsigned int pa17 : 1; | ||
| 135 | unsigned int pa18 : 1; | ||
| 136 | unsigned int pa19 : 1; | ||
| 137 | unsigned int pa20 : 1; | ||
| 138 | unsigned int pa21 : 1; | ||
| 139 | unsigned int pa22 : 1; | ||
| 140 | unsigned int pa23 : 1; | ||
| 141 | unsigned int pa24 : 1; | ||
| 142 | unsigned int pa25 : 1; | ||
| 143 | unsigned int pa26 : 1; | ||
| 144 | unsigned int pa27 : 1; | ||
| 145 | unsigned int pa28 : 1; | ||
| 146 | unsigned int pa29 : 1; | ||
| 147 | unsigned int pa30 : 1; | ||
| 148 | unsigned int pa31 : 1; | ||
| 149 | } reg_pinmux_rw_gio_pa; | ||
| 150 | #define REG_RD_ADDR_pinmux_rw_gio_pa 4 | ||
| 151 | #define REG_WR_ADDR_pinmux_rw_gio_pa 4 | ||
| 152 | |||
| 153 | /* Register rw_gio_pb, scope pinmux, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int pb0 : 1; | ||
| 156 | unsigned int pb1 : 1; | ||
| 157 | unsigned int pb2 : 1; | ||
| 158 | unsigned int pb3 : 1; | ||
| 159 | unsigned int pb4 : 1; | ||
| 160 | unsigned int pb5 : 1; | ||
| 161 | unsigned int pb6 : 1; | ||
| 162 | unsigned int pb7 : 1; | ||
| 163 | unsigned int pb8 : 1; | ||
| 164 | unsigned int pb9 : 1; | ||
| 165 | unsigned int pb10 : 1; | ||
| 166 | unsigned int pb11 : 1; | ||
| 167 | unsigned int pb12 : 1; | ||
| 168 | unsigned int pb13 : 1; | ||
| 169 | unsigned int pb14 : 1; | ||
| 170 | unsigned int pb15 : 1; | ||
| 171 | unsigned int pb16 : 1; | ||
| 172 | unsigned int pb17 : 1; | ||
| 173 | unsigned int pb18 : 1; | ||
| 174 | unsigned int pb19 : 1; | ||
| 175 | unsigned int pb20 : 1; | ||
| 176 | unsigned int pb21 : 1; | ||
| 177 | unsigned int pb22 : 1; | ||
| 178 | unsigned int pb23 : 1; | ||
| 179 | unsigned int pb24 : 1; | ||
| 180 | unsigned int pb25 : 1; | ||
| 181 | unsigned int pb26 : 1; | ||
| 182 | unsigned int pb27 : 1; | ||
| 183 | unsigned int pb28 : 1; | ||
| 184 | unsigned int pb29 : 1; | ||
| 185 | unsigned int pb30 : 1; | ||
| 186 | unsigned int pb31 : 1; | ||
| 187 | } reg_pinmux_rw_gio_pb; | ||
| 188 | #define REG_RD_ADDR_pinmux_rw_gio_pb 8 | ||
| 189 | #define REG_WR_ADDR_pinmux_rw_gio_pb 8 | ||
| 190 | |||
| 191 | /* Register rw_gio_pc, scope pinmux, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int pc0 : 1; | ||
| 194 | unsigned int pc1 : 1; | ||
| 195 | unsigned int pc2 : 1; | ||
| 196 | unsigned int pc3 : 1; | ||
| 197 | unsigned int pc4 : 1; | ||
| 198 | unsigned int pc5 : 1; | ||
| 199 | unsigned int pc6 : 1; | ||
| 200 | unsigned int pc7 : 1; | ||
| 201 | unsigned int pc8 : 1; | ||
| 202 | unsigned int pc9 : 1; | ||
| 203 | unsigned int pc10 : 1; | ||
| 204 | unsigned int pc11 : 1; | ||
| 205 | unsigned int pc12 : 1; | ||
| 206 | unsigned int pc13 : 1; | ||
| 207 | unsigned int pc14 : 1; | ||
| 208 | unsigned int pc15 : 1; | ||
| 209 | unsigned int dummy1 : 16; | ||
| 210 | } reg_pinmux_rw_gio_pc; | ||
| 211 | #define REG_RD_ADDR_pinmux_rw_gio_pc 12 | ||
| 212 | #define REG_WR_ADDR_pinmux_rw_gio_pc 12 | ||
| 213 | |||
| 214 | /* Register rw_iop_pa, scope pinmux, type rw */ | ||
| 215 | typedef struct { | ||
| 216 | unsigned int pa0 : 1; | ||
| 217 | unsigned int pa1 : 1; | ||
| 218 | unsigned int pa2 : 1; | ||
| 219 | unsigned int pa3 : 1; | ||
| 220 | unsigned int pa4 : 1; | ||
| 221 | unsigned int pa5 : 1; | ||
| 222 | unsigned int pa6 : 1; | ||
| 223 | unsigned int pa7 : 1; | ||
| 224 | unsigned int pa8 : 1; | ||
| 225 | unsigned int pa9 : 1; | ||
| 226 | unsigned int pa10 : 1; | ||
| 227 | unsigned int pa11 : 1; | ||
| 228 | unsigned int pa12 : 1; | ||
| 229 | unsigned int pa13 : 1; | ||
| 230 | unsigned int pa14 : 1; | ||
| 231 | unsigned int pa15 : 1; | ||
| 232 | unsigned int pa16 : 1; | ||
| 233 | unsigned int pa17 : 1; | ||
| 234 | unsigned int pa18 : 1; | ||
| 235 | unsigned int pa19 : 1; | ||
| 236 | unsigned int pa20 : 1; | ||
| 237 | unsigned int pa21 : 1; | ||
| 238 | unsigned int pa22 : 1; | ||
| 239 | unsigned int pa23 : 1; | ||
| 240 | unsigned int pa24 : 1; | ||
| 241 | unsigned int pa25 : 1; | ||
| 242 | unsigned int pa26 : 1; | ||
| 243 | unsigned int pa27 : 1; | ||
| 244 | unsigned int pa28 : 1; | ||
| 245 | unsigned int pa29 : 1; | ||
| 246 | unsigned int pa30 : 1; | ||
| 247 | unsigned int pa31 : 1; | ||
| 248 | } reg_pinmux_rw_iop_pa; | ||
| 249 | #define REG_RD_ADDR_pinmux_rw_iop_pa 16 | ||
| 250 | #define REG_WR_ADDR_pinmux_rw_iop_pa 16 | ||
| 251 | |||
| 252 | /* Register rw_iop_pb, scope pinmux, type rw */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int pb0 : 1; | ||
| 255 | unsigned int pb1 : 1; | ||
| 256 | unsigned int pb2 : 1; | ||
| 257 | unsigned int pb3 : 1; | ||
| 258 | unsigned int pb4 : 1; | ||
| 259 | unsigned int pb5 : 1; | ||
| 260 | unsigned int pb6 : 1; | ||
| 261 | unsigned int pb7 : 1; | ||
| 262 | unsigned int dummy1 : 24; | ||
| 263 | } reg_pinmux_rw_iop_pb; | ||
| 264 | #define REG_RD_ADDR_pinmux_rw_iop_pb 20 | ||
| 265 | #define REG_WR_ADDR_pinmux_rw_iop_pb 20 | ||
| 266 | |||
| 267 | /* Register rw_iop_pio, scope pinmux, type rw */ | ||
| 268 | typedef struct { | ||
| 269 | unsigned int d0 : 1; | ||
| 270 | unsigned int d1 : 1; | ||
| 271 | unsigned int d2 : 1; | ||
| 272 | unsigned int d3 : 1; | ||
| 273 | unsigned int d4 : 1; | ||
| 274 | unsigned int d5 : 1; | ||
| 275 | unsigned int d6 : 1; | ||
| 276 | unsigned int d7 : 1; | ||
| 277 | unsigned int rd_n : 1; | ||
| 278 | unsigned int wr_n : 1; | ||
| 279 | unsigned int a0 : 1; | ||
| 280 | unsigned int a1 : 1; | ||
| 281 | unsigned int ce0_n : 1; | ||
| 282 | unsigned int ce1_n : 1; | ||
| 283 | unsigned int ce2_n : 1; | ||
| 284 | unsigned int rdy : 1; | ||
| 285 | unsigned int dummy1 : 16; | ||
| 286 | } reg_pinmux_rw_iop_pio; | ||
| 287 | #define REG_RD_ADDR_pinmux_rw_iop_pio 24 | ||
| 288 | #define REG_WR_ADDR_pinmux_rw_iop_pio 24 | ||
| 289 | |||
| 290 | /* Register rw_iop_usb, scope pinmux, type rw */ | ||
| 291 | typedef struct { | ||
| 292 | unsigned int usb0 : 1; | ||
| 293 | unsigned int dummy1 : 31; | ||
| 294 | } reg_pinmux_rw_iop_usb; | ||
| 295 | #define REG_RD_ADDR_pinmux_rw_iop_usb 28 | ||
| 296 | #define REG_WR_ADDR_pinmux_rw_iop_usb 28 | ||
| 297 | |||
| 298 | |||
| 299 | /* Constants */ | ||
| 300 | enum { | ||
| 301 | regk_pinmux_no = 0x00000000, | ||
| 302 | regk_pinmux_rw_gio_pa_default = 0x00000000, | ||
| 303 | regk_pinmux_rw_gio_pb_default = 0x00000000, | ||
| 304 | regk_pinmux_rw_gio_pc_default = 0x00000000, | ||
| 305 | regk_pinmux_rw_hwprot_default = 0x00000000, | ||
| 306 | regk_pinmux_rw_iop_pa_default = 0x00000000, | ||
| 307 | regk_pinmux_rw_iop_pb_default = 0x00000000, | ||
| 308 | regk_pinmux_rw_iop_pio_default = 0x00000000, | ||
| 309 | regk_pinmux_rw_iop_usb_default = 0x00000001, | ||
| 310 | regk_pinmux_yes = 0x00000001 | ||
| 311 | }; | ||
| 312 | #endif /* __pinmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h deleted file mode 100644 index 2d8e4b4cc602..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h +++ /dev/null | |||
| @@ -1,371 +0,0 @@ | |||
| 1 | #ifndef __pio_defs_h | ||
| 2 | #define __pio_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: pio.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope pio */ | ||
| 83 | |||
| 84 | /* Register rw_data, scope pio, type rw */ | ||
| 85 | typedef unsigned int reg_pio_rw_data; | ||
| 86 | #define REG_RD_ADDR_pio_rw_data 64 | ||
| 87 | #define REG_WR_ADDR_pio_rw_data 64 | ||
| 88 | |||
| 89 | /* Register rw_io_access0, scope pio, type rw */ | ||
| 90 | typedef struct { | ||
| 91 | unsigned int data : 8; | ||
| 92 | unsigned int dummy1 : 24; | ||
| 93 | } reg_pio_rw_io_access0; | ||
| 94 | #define REG_RD_ADDR_pio_rw_io_access0 0 | ||
| 95 | #define REG_WR_ADDR_pio_rw_io_access0 0 | ||
| 96 | |||
| 97 | /* Register rw_io_access1, scope pio, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int data : 8; | ||
| 100 | unsigned int dummy1 : 24; | ||
| 101 | } reg_pio_rw_io_access1; | ||
| 102 | #define REG_RD_ADDR_pio_rw_io_access1 4 | ||
| 103 | #define REG_WR_ADDR_pio_rw_io_access1 4 | ||
| 104 | |||
| 105 | /* Register rw_io_access2, scope pio, type rw */ | ||
| 106 | typedef struct { | ||
| 107 | unsigned int data : 8; | ||
| 108 | unsigned int dummy1 : 24; | ||
| 109 | } reg_pio_rw_io_access2; | ||
| 110 | #define REG_RD_ADDR_pio_rw_io_access2 8 | ||
| 111 | #define REG_WR_ADDR_pio_rw_io_access2 8 | ||
| 112 | |||
| 113 | /* Register rw_io_access3, scope pio, type rw */ | ||
| 114 | typedef struct { | ||
| 115 | unsigned int data : 8; | ||
| 116 | unsigned int dummy1 : 24; | ||
| 117 | } reg_pio_rw_io_access3; | ||
| 118 | #define REG_RD_ADDR_pio_rw_io_access3 12 | ||
| 119 | #define REG_WR_ADDR_pio_rw_io_access3 12 | ||
| 120 | |||
| 121 | /* Register rw_io_access4, scope pio, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int data : 8; | ||
| 124 | unsigned int dummy1 : 24; | ||
| 125 | } reg_pio_rw_io_access4; | ||
| 126 | #define REG_RD_ADDR_pio_rw_io_access4 16 | ||
| 127 | #define REG_WR_ADDR_pio_rw_io_access4 16 | ||
| 128 | |||
| 129 | /* Register rw_io_access5, scope pio, type rw */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int data : 8; | ||
| 132 | unsigned int dummy1 : 24; | ||
| 133 | } reg_pio_rw_io_access5; | ||
| 134 | #define REG_RD_ADDR_pio_rw_io_access5 20 | ||
| 135 | #define REG_WR_ADDR_pio_rw_io_access5 20 | ||
| 136 | |||
| 137 | /* Register rw_io_access6, scope pio, type rw */ | ||
| 138 | typedef struct { | ||
| 139 | unsigned int data : 8; | ||
| 140 | unsigned int dummy1 : 24; | ||
| 141 | } reg_pio_rw_io_access6; | ||
| 142 | #define REG_RD_ADDR_pio_rw_io_access6 24 | ||
| 143 | #define REG_WR_ADDR_pio_rw_io_access6 24 | ||
| 144 | |||
| 145 | /* Register rw_io_access7, scope pio, type rw */ | ||
| 146 | typedef struct { | ||
| 147 | unsigned int data : 8; | ||
| 148 | unsigned int dummy1 : 24; | ||
| 149 | } reg_pio_rw_io_access7; | ||
| 150 | #define REG_RD_ADDR_pio_rw_io_access7 28 | ||
| 151 | #define REG_WR_ADDR_pio_rw_io_access7 28 | ||
| 152 | |||
| 153 | /* Register rw_io_access8, scope pio, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int data : 8; | ||
| 156 | unsigned int dummy1 : 24; | ||
| 157 | } reg_pio_rw_io_access8; | ||
| 158 | #define REG_RD_ADDR_pio_rw_io_access8 32 | ||
| 159 | #define REG_WR_ADDR_pio_rw_io_access8 32 | ||
| 160 | |||
| 161 | /* Register rw_io_access9, scope pio, type rw */ | ||
| 162 | typedef struct { | ||
| 163 | unsigned int data : 8; | ||
| 164 | unsigned int dummy1 : 24; | ||
| 165 | } reg_pio_rw_io_access9; | ||
| 166 | #define REG_RD_ADDR_pio_rw_io_access9 36 | ||
| 167 | #define REG_WR_ADDR_pio_rw_io_access9 36 | ||
| 168 | |||
| 169 | /* Register rw_io_access10, scope pio, type rw */ | ||
| 170 | typedef struct { | ||
| 171 | unsigned int data : 8; | ||
| 172 | unsigned int dummy1 : 24; | ||
| 173 | } reg_pio_rw_io_access10; | ||
| 174 | #define REG_RD_ADDR_pio_rw_io_access10 40 | ||
| 175 | #define REG_WR_ADDR_pio_rw_io_access10 40 | ||
| 176 | |||
| 177 | /* Register rw_io_access11, scope pio, type rw */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int data : 8; | ||
| 180 | unsigned int dummy1 : 24; | ||
| 181 | } reg_pio_rw_io_access11; | ||
| 182 | #define REG_RD_ADDR_pio_rw_io_access11 44 | ||
| 183 | #define REG_WR_ADDR_pio_rw_io_access11 44 | ||
| 184 | |||
| 185 | /* Register rw_io_access12, scope pio, type rw */ | ||
| 186 | typedef struct { | ||
| 187 | unsigned int data : 8; | ||
| 188 | unsigned int dummy1 : 24; | ||
| 189 | } reg_pio_rw_io_access12; | ||
| 190 | #define REG_RD_ADDR_pio_rw_io_access12 48 | ||
| 191 | #define REG_WR_ADDR_pio_rw_io_access12 48 | ||
| 192 | |||
| 193 | /* Register rw_io_access13, scope pio, type rw */ | ||
| 194 | typedef struct { | ||
| 195 | unsigned int data : 8; | ||
| 196 | unsigned int dummy1 : 24; | ||
| 197 | } reg_pio_rw_io_access13; | ||
| 198 | #define REG_RD_ADDR_pio_rw_io_access13 52 | ||
| 199 | #define REG_WR_ADDR_pio_rw_io_access13 52 | ||
| 200 | |||
| 201 | /* Register rw_io_access14, scope pio, type rw */ | ||
| 202 | typedef struct { | ||
| 203 | unsigned int data : 8; | ||
| 204 | unsigned int dummy1 : 24; | ||
| 205 | } reg_pio_rw_io_access14; | ||
| 206 | #define REG_RD_ADDR_pio_rw_io_access14 56 | ||
| 207 | #define REG_WR_ADDR_pio_rw_io_access14 56 | ||
| 208 | |||
| 209 | /* Register rw_io_access15, scope pio, type rw */ | ||
| 210 | typedef struct { | ||
| 211 | unsigned int data : 8; | ||
| 212 | unsigned int dummy1 : 24; | ||
| 213 | } reg_pio_rw_io_access15; | ||
| 214 | #define REG_RD_ADDR_pio_rw_io_access15 60 | ||
| 215 | #define REG_WR_ADDR_pio_rw_io_access15 60 | ||
| 216 | |||
| 217 | /* Register rw_ce0_cfg, scope pio, type rw */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int lw : 6; | ||
| 220 | unsigned int ew : 3; | ||
| 221 | unsigned int zw : 3; | ||
| 222 | unsigned int aw : 2; | ||
| 223 | unsigned int mode : 2; | ||
| 224 | unsigned int dummy1 : 16; | ||
| 225 | } reg_pio_rw_ce0_cfg; | ||
| 226 | #define REG_RD_ADDR_pio_rw_ce0_cfg 68 | ||
| 227 | #define REG_WR_ADDR_pio_rw_ce0_cfg 68 | ||
| 228 | |||
| 229 | /* Register rw_ce1_cfg, scope pio, type rw */ | ||
| 230 | typedef struct { | ||
| 231 | unsigned int lw : 6; | ||
| 232 | unsigned int ew : 3; | ||
| 233 | unsigned int zw : 3; | ||
| 234 | unsigned int aw : 2; | ||
| 235 | unsigned int mode : 2; | ||
| 236 | unsigned int dummy1 : 16; | ||
| 237 | } reg_pio_rw_ce1_cfg; | ||
| 238 | #define REG_RD_ADDR_pio_rw_ce1_cfg 72 | ||
| 239 | #define REG_WR_ADDR_pio_rw_ce1_cfg 72 | ||
| 240 | |||
| 241 | /* Register rw_ce2_cfg, scope pio, type rw */ | ||
| 242 | typedef struct { | ||
| 243 | unsigned int lw : 6; | ||
| 244 | unsigned int ew : 3; | ||
| 245 | unsigned int zw : 3; | ||
| 246 | unsigned int aw : 2; | ||
| 247 | unsigned int mode : 2; | ||
| 248 | unsigned int dummy1 : 16; | ||
| 249 | } reg_pio_rw_ce2_cfg; | ||
| 250 | #define REG_RD_ADDR_pio_rw_ce2_cfg 76 | ||
| 251 | #define REG_WR_ADDR_pio_rw_ce2_cfg 76 | ||
| 252 | |||
| 253 | /* Register rw_dout, scope pio, type rw */ | ||
| 254 | typedef struct { | ||
| 255 | unsigned int data : 8; | ||
| 256 | unsigned int rd_n : 1; | ||
| 257 | unsigned int wr_n : 1; | ||
| 258 | unsigned int a0 : 1; | ||
| 259 | unsigned int a1 : 1; | ||
| 260 | unsigned int ce0_n : 1; | ||
| 261 | unsigned int ce1_n : 1; | ||
| 262 | unsigned int ce2_n : 1; | ||
| 263 | unsigned int rdy : 1; | ||
| 264 | unsigned int dummy1 : 16; | ||
| 265 | } reg_pio_rw_dout; | ||
| 266 | #define REG_RD_ADDR_pio_rw_dout 80 | ||
| 267 | #define REG_WR_ADDR_pio_rw_dout 80 | ||
| 268 | |||
| 269 | /* Register rw_oe, scope pio, type rw */ | ||
| 270 | typedef struct { | ||
| 271 | unsigned int data : 8; | ||
| 272 | unsigned int rd_n : 1; | ||
| 273 | unsigned int wr_n : 1; | ||
| 274 | unsigned int a0 : 1; | ||
| 275 | unsigned int a1 : 1; | ||
| 276 | unsigned int ce0_n : 1; | ||
| 277 | unsigned int ce1_n : 1; | ||
| 278 | unsigned int ce2_n : 1; | ||
| 279 | unsigned int rdy : 1; | ||
| 280 | unsigned int dummy1 : 16; | ||
| 281 | } reg_pio_rw_oe; | ||
| 282 | #define REG_RD_ADDR_pio_rw_oe 84 | ||
| 283 | #define REG_WR_ADDR_pio_rw_oe 84 | ||
| 284 | |||
| 285 | /* Register rw_man_ctrl, scope pio, type rw */ | ||
| 286 | typedef struct { | ||
| 287 | unsigned int data : 8; | ||
| 288 | unsigned int rd_n : 1; | ||
| 289 | unsigned int wr_n : 1; | ||
| 290 | unsigned int a0 : 1; | ||
| 291 | unsigned int a1 : 1; | ||
| 292 | unsigned int ce0_n : 1; | ||
| 293 | unsigned int ce1_n : 1; | ||
| 294 | unsigned int ce2_n : 1; | ||
| 295 | unsigned int rdy : 1; | ||
| 296 | unsigned int dummy1 : 16; | ||
| 297 | } reg_pio_rw_man_ctrl; | ||
| 298 | #define REG_RD_ADDR_pio_rw_man_ctrl 88 | ||
| 299 | #define REG_WR_ADDR_pio_rw_man_ctrl 88 | ||
| 300 | |||
| 301 | /* Register r_din, scope pio, type r */ | ||
| 302 | typedef struct { | ||
| 303 | unsigned int data : 8; | ||
| 304 | unsigned int rd_n : 1; | ||
| 305 | unsigned int wr_n : 1; | ||
| 306 | unsigned int a0 : 1; | ||
| 307 | unsigned int a1 : 1; | ||
| 308 | unsigned int ce0_n : 1; | ||
| 309 | unsigned int ce1_n : 1; | ||
| 310 | unsigned int ce2_n : 1; | ||
| 311 | unsigned int rdy : 1; | ||
| 312 | unsigned int dummy1 : 16; | ||
| 313 | } reg_pio_r_din; | ||
| 314 | #define REG_RD_ADDR_pio_r_din 92 | ||
| 315 | |||
| 316 | /* Register r_stat, scope pio, type r */ | ||
| 317 | typedef struct { | ||
| 318 | unsigned int busy : 1; | ||
| 319 | unsigned int dummy1 : 31; | ||
| 320 | } reg_pio_r_stat; | ||
| 321 | #define REG_RD_ADDR_pio_r_stat 96 | ||
| 322 | |||
| 323 | /* Register rw_intr_mask, scope pio, type rw */ | ||
| 324 | typedef struct { | ||
| 325 | unsigned int rdy : 1; | ||
| 326 | unsigned int dummy1 : 31; | ||
| 327 | } reg_pio_rw_intr_mask; | ||
| 328 | #define REG_RD_ADDR_pio_rw_intr_mask 100 | ||
| 329 | #define REG_WR_ADDR_pio_rw_intr_mask 100 | ||
| 330 | |||
| 331 | /* Register rw_ack_intr, scope pio, type rw */ | ||
| 332 | typedef struct { | ||
| 333 | unsigned int rdy : 1; | ||
| 334 | unsigned int dummy1 : 31; | ||
| 335 | } reg_pio_rw_ack_intr; | ||
| 336 | #define REG_RD_ADDR_pio_rw_ack_intr 104 | ||
| 337 | #define REG_WR_ADDR_pio_rw_ack_intr 104 | ||
| 338 | |||
| 339 | /* Register r_intr, scope pio, type r */ | ||
| 340 | typedef struct { | ||
| 341 | unsigned int rdy : 1; | ||
| 342 | unsigned int dummy1 : 31; | ||
| 343 | } reg_pio_r_intr; | ||
| 344 | #define REG_RD_ADDR_pio_r_intr 108 | ||
| 345 | |||
| 346 | /* Register r_masked_intr, scope pio, type r */ | ||
| 347 | typedef struct { | ||
| 348 | unsigned int rdy : 1; | ||
| 349 | unsigned int dummy1 : 31; | ||
| 350 | } reg_pio_r_masked_intr; | ||
| 351 | #define REG_RD_ADDR_pio_r_masked_intr 112 | ||
| 352 | |||
| 353 | |||
| 354 | /* Constants */ | ||
| 355 | enum { | ||
| 356 | regk_pio_a2 = 0x00000003, | ||
| 357 | regk_pio_no = 0x00000000, | ||
| 358 | regk_pio_normal = 0x00000000, | ||
| 359 | regk_pio_rd = 0x00000001, | ||
| 360 | regk_pio_rw_ce0_cfg_default = 0x00000000, | ||
| 361 | regk_pio_rw_ce1_cfg_default = 0x00000000, | ||
| 362 | regk_pio_rw_ce2_cfg_default = 0x00000000, | ||
| 363 | regk_pio_rw_intr_mask_default = 0x00000000, | ||
| 364 | regk_pio_rw_man_ctrl_default = 0x00000000, | ||
| 365 | regk_pio_rw_oe_default = 0x00000000, | ||
| 366 | regk_pio_wr = 0x00000002, | ||
| 367 | regk_pio_wr_ce2 = 0x00000003, | ||
| 368 | regk_pio_yes = 0x00000001, | ||
| 369 | regk_pio_yes_all = 0x000000ff | ||
| 370 | }; | ||
| 371 | #endif /* __pio_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h deleted file mode 100644 index 36e59d6e96b6..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h +++ /dev/null | |||
| @@ -1,103 +0,0 @@ | |||
| 1 | #ifndef __reg_map_h | ||
| 2 | #define __reg_map_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: reg.rmap | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | typedef enum { | ||
| 14 | regi_ccd = 0xb0000000, | ||
| 15 | regi_ccd_top = 0xb0000000, | ||
| 16 | regi_ccd_dp = 0xb0000400, | ||
| 17 | regi_ccd_stat = 0xb0000800, | ||
| 18 | regi_ccd_tg = 0xb0001000, | ||
| 19 | regi_cfg = 0xb0002000, | ||
| 20 | regi_clkgen = 0xb0004000, | ||
| 21 | regi_ddr2_ctrl = 0xb0006000, | ||
| 22 | regi_dma0 = 0xb0008000, | ||
| 23 | regi_dma1 = 0xb000a000, | ||
| 24 | regi_dma11 = 0xb000c000, | ||
| 25 | regi_dma2 = 0xb000e000, | ||
| 26 | regi_dma3 = 0xb0010000, | ||
| 27 | regi_dma4 = 0xb0012000, | ||
| 28 | regi_dma5 = 0xb0014000, | ||
| 29 | regi_dma6 = 0xb0016000, | ||
| 30 | regi_dma7 = 0xb0018000, | ||
| 31 | regi_dma9 = 0xb001a000, | ||
| 32 | regi_eth = 0xb001c000, | ||
| 33 | regi_gio = 0xb0020000, | ||
| 34 | regi_h264 = 0xb0022000, | ||
| 35 | regi_hist = 0xb0026000, | ||
| 36 | regi_iop = 0xb0028000, | ||
| 37 | regi_iop_version = 0xb0028000, | ||
| 38 | regi_iop_fifo_in_extra = 0xb0028040, | ||
| 39 | regi_iop_fifo_out_extra = 0xb0028080, | ||
| 40 | regi_iop_trigger_grp0 = 0xb00280c0, | ||
| 41 | regi_iop_trigger_grp1 = 0xb0028100, | ||
| 42 | regi_iop_trigger_grp2 = 0xb0028140, | ||
| 43 | regi_iop_trigger_grp3 = 0xb0028180, | ||
| 44 | regi_iop_trigger_grp4 = 0xb00281c0, | ||
| 45 | regi_iop_trigger_grp5 = 0xb0028200, | ||
| 46 | regi_iop_trigger_grp6 = 0xb0028240, | ||
| 47 | regi_iop_trigger_grp7 = 0xb0028280, | ||
| 48 | regi_iop_crc_par = 0xb0028300, | ||
| 49 | regi_iop_dmc_in = 0xb0028380, | ||
| 50 | regi_iop_dmc_out = 0xb0028400, | ||
| 51 | regi_iop_fifo_in = 0xb0028480, | ||
| 52 | regi_iop_fifo_out = 0xb0028500, | ||
| 53 | regi_iop_scrc_in = 0xb0028580, | ||
| 54 | regi_iop_scrc_out = 0xb0028600, | ||
| 55 | regi_iop_timer_grp0 = 0xb0028680, | ||
| 56 | regi_iop_timer_grp1 = 0xb0028700, | ||
| 57 | regi_iop_sap_in = 0xb0028800, | ||
| 58 | regi_iop_sap_out = 0xb0028900, | ||
| 59 | regi_iop_spu = 0xb0028a00, | ||
| 60 | regi_iop_sw_cfg = 0xb0028b00, | ||
| 61 | regi_iop_sw_cpu = 0xb0028c00, | ||
| 62 | regi_iop_sw_mpu = 0xb0028d00, | ||
| 63 | regi_iop_sw_spu = 0xb0028e00, | ||
| 64 | regi_iop_mpu = 0xb0029000, | ||
| 65 | regi_irq = 0xb002a000, | ||
| 66 | regi_irq2 = 0xb006a000, | ||
| 67 | regi_jpeg = 0xb002c000, | ||
| 68 | regi_l2cache = 0xb0030000, | ||
| 69 | regi_marb_bar = 0xb0032000, | ||
| 70 | regi_marb_bar_bp0 = 0xb0032140, | ||
| 71 | regi_marb_bar_bp1 = 0xb0032180, | ||
| 72 | regi_marb_bar_bp2 = 0xb00321c0, | ||
| 73 | regi_marb_bar_bp3 = 0xb0032200, | ||
| 74 | regi_marb_foo = 0xb0034000, | ||
| 75 | regi_marb_foo_bp0 = 0xb0034280, | ||
| 76 | regi_marb_foo_bp1 = 0xb00342c0, | ||
| 77 | regi_marb_foo_bp2 = 0xb0034300, | ||
| 78 | regi_marb_foo_bp3 = 0xb0034340, | ||
| 79 | regi_pinmux = 0xb0038000, | ||
| 80 | regi_pio = 0xb0036000, | ||
| 81 | regi_sclr = 0xb003a000, | ||
| 82 | regi_sclr_fifo = 0xb003c000, | ||
| 83 | regi_ser0 = 0xb003e000, | ||
| 84 | regi_ser1 = 0xb0040000, | ||
| 85 | regi_ser2 = 0xb0042000, | ||
| 86 | regi_ser3 = 0xb0044000, | ||
| 87 | regi_ser4 = 0xb0046000, | ||
| 88 | regi_sser = 0xb0048000, | ||
| 89 | regi_strcop = 0xb004a000, | ||
| 90 | regi_strdma0 = 0xb004e000, | ||
| 91 | regi_strdma1 = 0xb0050000, | ||
| 92 | regi_strdma2 = 0xb0052000, | ||
| 93 | regi_strdma3 = 0xb0054000, | ||
| 94 | regi_strdma5 = 0xb0056000, | ||
| 95 | regi_strmux = 0xb004c000, | ||
| 96 | regi_timer0 = 0xb0058000, | ||
| 97 | regi_timer1 = 0xb005a000, | ||
| 98 | regi_timer2 = 0xb006e000, | ||
| 99 | regi_trace = 0xb005c000, | ||
| 100 | regi_vin = 0xb005e000, | ||
| 101 | regi_vout = 0xb0060000 | ||
| 102 | } reg_scope_instances; | ||
| 103 | #endif /* __reg_map_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h deleted file mode 100644 index 14f718a4ecc3..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h +++ /dev/null | |||
| @@ -1,120 +0,0 @@ | |||
| 1 | #ifndef __strmux_defs_h | ||
| 2 | #define __strmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: strmux.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope strmux */ | ||
| 83 | |||
| 84 | /* Register rw_cfg, scope strmux, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int dma0 : 2; | ||
| 87 | unsigned int dma1 : 2; | ||
| 88 | unsigned int dma2 : 2; | ||
| 89 | unsigned int dma3 : 2; | ||
| 90 | unsigned int dma4 : 2; | ||
| 91 | unsigned int dma5 : 2; | ||
| 92 | unsigned int dma6 : 2; | ||
| 93 | unsigned int dma7 : 2; | ||
| 94 | unsigned int dummy1 : 2; | ||
| 95 | unsigned int dma9 : 2; | ||
| 96 | unsigned int dummy2 : 2; | ||
| 97 | unsigned int dma11 : 2; | ||
| 98 | unsigned int dummy3 : 8; | ||
| 99 | } reg_strmux_rw_cfg; | ||
| 100 | #define REG_RD_ADDR_strmux_rw_cfg 0 | ||
| 101 | #define REG_WR_ADDR_strmux_rw_cfg 0 | ||
| 102 | |||
| 103 | |||
| 104 | /* Constants */ | ||
| 105 | enum { | ||
| 106 | regk_strmux_eth = 0x00000001, | ||
| 107 | regk_strmux_h264 = 0x00000001, | ||
| 108 | regk_strmux_iop = 0x00000001, | ||
| 109 | regk_strmux_jpeg = 0x00000001, | ||
| 110 | regk_strmux_off = 0x00000000, | ||
| 111 | regk_strmux_rw_cfg_default = 0x00000000, | ||
| 112 | regk_strmux_ser0 = 0x00000002, | ||
| 113 | regk_strmux_ser1 = 0x00000002, | ||
| 114 | regk_strmux_ser2 = 0x00000002, | ||
| 115 | regk_strmux_ser3 = 0x00000002, | ||
| 116 | regk_strmux_ser4 = 0x00000002, | ||
| 117 | regk_strmux_sser = 0x00000001, | ||
| 118 | regk_strmux_strcop = 0x00000001 | ||
| 119 | }; | ||
| 120 | #endif /* __strmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h deleted file mode 100644 index 2c33e097d60a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h +++ /dev/null | |||
| @@ -1,265 +0,0 @@ | |||
| 1 | #ifndef __timer_defs_h | ||
| 2 | #define __timer_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: timer.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope timer */ | ||
| 83 | |||
| 84 | /* Register rw_tmr0_div, scope timer, type rw */ | ||
| 85 | typedef unsigned int reg_timer_rw_tmr0_div; | ||
| 86 | #define REG_RD_ADDR_timer_rw_tmr0_div 0 | ||
| 87 | #define REG_WR_ADDR_timer_rw_tmr0_div 0 | ||
| 88 | |||
| 89 | /* Register r_tmr0_data, scope timer, type r */ | ||
| 90 | typedef unsigned int reg_timer_r_tmr0_data; | ||
| 91 | #define REG_RD_ADDR_timer_r_tmr0_data 4 | ||
| 92 | |||
| 93 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | ||
| 94 | typedef struct { | ||
| 95 | unsigned int op : 2; | ||
| 96 | unsigned int freq : 3; | ||
| 97 | unsigned int dummy1 : 27; | ||
| 98 | } reg_timer_rw_tmr0_ctrl; | ||
| 99 | #define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 | ||
| 100 | #define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 | ||
| 101 | |||
| 102 | /* Register rw_tmr1_div, scope timer, type rw */ | ||
| 103 | typedef unsigned int reg_timer_rw_tmr1_div; | ||
| 104 | #define REG_RD_ADDR_timer_rw_tmr1_div 16 | ||
| 105 | #define REG_WR_ADDR_timer_rw_tmr1_div 16 | ||
| 106 | |||
| 107 | /* Register r_tmr1_data, scope timer, type r */ | ||
| 108 | typedef unsigned int reg_timer_r_tmr1_data; | ||
| 109 | #define REG_RD_ADDR_timer_r_tmr1_data 20 | ||
| 110 | |||
| 111 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | ||
| 112 | typedef struct { | ||
| 113 | unsigned int op : 2; | ||
| 114 | unsigned int freq : 3; | ||
| 115 | unsigned int dummy1 : 27; | ||
| 116 | } reg_timer_rw_tmr1_ctrl; | ||
| 117 | #define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 | ||
| 118 | #define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 | ||
| 119 | |||
| 120 | /* Register rs_cnt_data, scope timer, type rs */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int tmr : 24; | ||
| 123 | unsigned int cnt : 8; | ||
| 124 | } reg_timer_rs_cnt_data; | ||
| 125 | #define REG_RD_ADDR_timer_rs_cnt_data 32 | ||
| 126 | |||
| 127 | /* Register r_cnt_data, scope timer, type r */ | ||
| 128 | typedef struct { | ||
| 129 | unsigned int tmr : 24; | ||
| 130 | unsigned int cnt : 8; | ||
| 131 | } reg_timer_r_cnt_data; | ||
| 132 | #define REG_RD_ADDR_timer_r_cnt_data 36 | ||
| 133 | |||
| 134 | /* Register rw_cnt_cfg, scope timer, type rw */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int clk : 2; | ||
| 137 | unsigned int dummy1 : 30; | ||
| 138 | } reg_timer_rw_cnt_cfg; | ||
| 139 | #define REG_RD_ADDR_timer_rw_cnt_cfg 40 | ||
| 140 | #define REG_WR_ADDR_timer_rw_cnt_cfg 40 | ||
| 141 | |||
| 142 | /* Register rw_trig, scope timer, type rw */ | ||
| 143 | typedef unsigned int reg_timer_rw_trig; | ||
| 144 | #define REG_RD_ADDR_timer_rw_trig 48 | ||
| 145 | #define REG_WR_ADDR_timer_rw_trig 48 | ||
| 146 | |||
| 147 | /* Register rw_trig_cfg, scope timer, type rw */ | ||
| 148 | typedef struct { | ||
| 149 | unsigned int tmr : 2; | ||
| 150 | unsigned int dummy1 : 30; | ||
| 151 | } reg_timer_rw_trig_cfg; | ||
| 152 | #define REG_RD_ADDR_timer_rw_trig_cfg 52 | ||
| 153 | #define REG_WR_ADDR_timer_rw_trig_cfg 52 | ||
| 154 | |||
| 155 | /* Register r_time, scope timer, type r */ | ||
| 156 | typedef unsigned int reg_timer_r_time; | ||
| 157 | #define REG_RD_ADDR_timer_r_time 56 | ||
| 158 | |||
| 159 | /* Register rw_out, scope timer, type rw */ | ||
| 160 | typedef struct { | ||
| 161 | unsigned int tmr : 2; | ||
| 162 | unsigned int dummy1 : 30; | ||
| 163 | } reg_timer_rw_out; | ||
| 164 | #define REG_RD_ADDR_timer_rw_out 60 | ||
| 165 | #define REG_WR_ADDR_timer_rw_out 60 | ||
| 166 | |||
| 167 | /* Register rw_wd_ctrl, scope timer, type rw */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int cnt : 8; | ||
| 170 | unsigned int cmd : 1; | ||
| 171 | unsigned int key : 7; | ||
| 172 | unsigned int dummy1 : 16; | ||
| 173 | } reg_timer_rw_wd_ctrl; | ||
| 174 | #define REG_RD_ADDR_timer_rw_wd_ctrl 64 | ||
| 175 | #define REG_WR_ADDR_timer_rw_wd_ctrl 64 | ||
| 176 | |||
| 177 | /* Register r_wd_stat, scope timer, type r */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int cnt : 8; | ||
| 180 | unsigned int cmd : 1; | ||
| 181 | unsigned int dummy1 : 23; | ||
| 182 | } reg_timer_r_wd_stat; | ||
| 183 | #define REG_RD_ADDR_timer_r_wd_stat 68 | ||
| 184 | |||
| 185 | /* Register rw_intr_mask, scope timer, type rw */ | ||
| 186 | typedef struct { | ||
| 187 | unsigned int tmr0 : 1; | ||
| 188 | unsigned int tmr1 : 1; | ||
| 189 | unsigned int cnt : 1; | ||
| 190 | unsigned int trig : 1; | ||
| 191 | unsigned int dummy1 : 28; | ||
| 192 | } reg_timer_rw_intr_mask; | ||
| 193 | #define REG_RD_ADDR_timer_rw_intr_mask 72 | ||
| 194 | #define REG_WR_ADDR_timer_rw_intr_mask 72 | ||
| 195 | |||
| 196 | /* Register rw_ack_intr, scope timer, type rw */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int tmr0 : 1; | ||
| 199 | unsigned int tmr1 : 1; | ||
| 200 | unsigned int cnt : 1; | ||
| 201 | unsigned int trig : 1; | ||
| 202 | unsigned int dummy1 : 28; | ||
| 203 | } reg_timer_rw_ack_intr; | ||
| 204 | #define REG_RD_ADDR_timer_rw_ack_intr 76 | ||
| 205 | #define REG_WR_ADDR_timer_rw_ack_intr 76 | ||
| 206 | |||
| 207 | /* Register r_intr, scope timer, type r */ | ||
| 208 | typedef struct { | ||
| 209 | unsigned int tmr0 : 1; | ||
| 210 | unsigned int tmr1 : 1; | ||
| 211 | unsigned int cnt : 1; | ||
| 212 | unsigned int trig : 1; | ||
| 213 | unsigned int dummy1 : 28; | ||
| 214 | } reg_timer_r_intr; | ||
| 215 | #define REG_RD_ADDR_timer_r_intr 80 | ||
| 216 | |||
| 217 | /* Register r_masked_intr, scope timer, type r */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int tmr0 : 1; | ||
| 220 | unsigned int tmr1 : 1; | ||
| 221 | unsigned int cnt : 1; | ||
| 222 | unsigned int trig : 1; | ||
| 223 | unsigned int dummy1 : 28; | ||
| 224 | } reg_timer_r_masked_intr; | ||
| 225 | #define REG_RD_ADDR_timer_r_masked_intr 84 | ||
| 226 | |||
| 227 | /* Register rw_test, scope timer, type rw */ | ||
| 228 | typedef struct { | ||
| 229 | unsigned int dis : 1; | ||
| 230 | unsigned int en : 1; | ||
| 231 | unsigned int dummy1 : 30; | ||
| 232 | } reg_timer_rw_test; | ||
| 233 | #define REG_RD_ADDR_timer_rw_test 88 | ||
| 234 | #define REG_WR_ADDR_timer_rw_test 88 | ||
| 235 | |||
| 236 | |||
| 237 | /* Constants */ | ||
| 238 | enum { | ||
| 239 | regk_timer_ext = 0x00000001, | ||
| 240 | regk_timer_f100 = 0x00000007, | ||
| 241 | regk_timer_f29_493 = 0x00000004, | ||
| 242 | regk_timer_f32 = 0x00000005, | ||
| 243 | regk_timer_f32_768 = 0x00000006, | ||
| 244 | regk_timer_f90 = 0x00000003, | ||
| 245 | regk_timer_hold = 0x00000001, | ||
| 246 | regk_timer_ld = 0x00000000, | ||
| 247 | regk_timer_no = 0x00000000, | ||
| 248 | regk_timer_off = 0x00000000, | ||
| 249 | regk_timer_run = 0x00000002, | ||
| 250 | regk_timer_rw_cnt_cfg_default = 0x00000000, | ||
| 251 | regk_timer_rw_intr_mask_default = 0x00000000, | ||
| 252 | regk_timer_rw_out_default = 0x00000000, | ||
| 253 | regk_timer_rw_test_default = 0x00000000, | ||
| 254 | regk_timer_rw_tmr0_ctrl_default = 0x00000000, | ||
| 255 | regk_timer_rw_tmr1_ctrl_default = 0x00000000, | ||
| 256 | regk_timer_rw_trig_cfg_default = 0x00000000, | ||
| 257 | regk_timer_start = 0x00000001, | ||
| 258 | regk_timer_stop = 0x00000000, | ||
| 259 | regk_timer_time = 0x00000001, | ||
| 260 | regk_timer_tmr0 = 0x00000002, | ||
| 261 | regk_timer_tmr1 = 0x00000003, | ||
| 262 | regk_timer_vclk = 0x00000002, | ||
| 263 | regk_timer_yes = 0x00000001 | ||
| 264 | }; | ||
| 265 | #endif /* __timer_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/memmap.h b/include/asm-cris/arch-v32/mach-a3/memmap.h deleted file mode 100644 index 7e15c9eb4e49..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/memmap.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_MEMMAP_H | ||
| 2 | #define _ASM_ARCH_MEMMAP_H | ||
| 3 | |||
| 4 | #define MEM_INTMEM_START (0x38000000) | ||
| 5 | #define MEM_INTMEM_SIZE (0x00018000) | ||
| 6 | #define MEM_DRAM_START (0x40000000) | ||
| 7 | |||
| 8 | #define MEM_NON_CACHEABLE (0x80000000) | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/pinmux.h b/include/asm-cris/arch-v32/mach-a3/pinmux.h deleted file mode 100644 index db42a7254584..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/pinmux.h +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_PINMUX_H | ||
| 2 | #define _ASM_CRIS_ARCH_PINMUX_H | ||
| 3 | |||
| 4 | #define PORT_A 0 | ||
| 5 | #define PORT_B 1 | ||
| 6 | #define PORT_C 2 | ||
| 7 | |||
| 8 | enum pin_mode { | ||
| 9 | pinmux_none = 0, | ||
| 10 | pinmux_fixed, | ||
| 11 | pinmux_gpio, | ||
| 12 | pinmux_iop | ||
| 13 | }; | ||
| 14 | |||
| 15 | enum fixed_function { | ||
| 16 | pinmux_eth, | ||
| 17 | pinmux_geth, | ||
| 18 | pinmux_tg_ccd, | ||
| 19 | pinmux_tg_cmos, | ||
| 20 | pinmux_vout, | ||
| 21 | pinmux_ser1, | ||
| 22 | pinmux_ser2, | ||
| 23 | pinmux_ser3, | ||
| 24 | pinmux_ser4, | ||
| 25 | pinmux_sser, | ||
| 26 | pinmux_pio, | ||
| 27 | pinmux_pwm0, | ||
| 28 | pinmux_pwm1, | ||
| 29 | pinmux_pwm2, | ||
| 30 | pinmux_i2c0, | ||
| 31 | pinmux_i2c1, | ||
| 32 | pinmux_i2c1_3wire, | ||
| 33 | pinmux_i2c1_sda1, | ||
| 34 | pinmux_i2c1_sda2, | ||
| 35 | pinmux_i2c1_sda3, | ||
| 36 | }; | ||
| 37 | |||
| 38 | int crisv32_pinmux_init(void); | ||
| 39 | int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); | ||
| 40 | int crisv32_pinmux_alloc_fixed(enum fixed_function function); | ||
| 41 | int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); | ||
| 42 | int crisv32_pinmux_dealloc_fixed(enum fixed_function function); | ||
| 43 | void crisv32_pinmux_dump(void); | ||
| 44 | |||
| 45 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/startup.inc b/include/asm-cris/arch-v32/mach-a3/startup.inc deleted file mode 100644 index 2f23e5e16f4a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/startup.inc +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | #include <hwregs/asm/reg_map_asm.h> | ||
| 2 | #include <hwregs/asm/gio_defs_asm.h> | ||
| 3 | #include <hwregs/asm/pio_defs_asm.h> | ||
| 4 | #include <hwregs/asm/clkgen_defs_asm.h> | ||
| 5 | #include <hwregs/asm/pinmux_defs_asm.h> | ||
| 6 | |||
| 7 | .macro GIO_INIT | ||
| 8 | move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 | ||
| 9 | move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 | ||
| 10 | move.d $r0, [$r1] | ||
| 11 | |||
| 12 | move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 | ||
| 13 | move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 | ||
| 14 | move.d $r0, [$r1] | ||
| 15 | |||
| 16 | move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 | ||
| 17 | move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 | ||
| 18 | move.d $r0, [$r1] | ||
| 19 | |||
| 20 | move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 | ||
| 21 | move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 | ||
| 22 | move.d $r0, [$r1] | ||
| 23 | |||
| 24 | move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 | ||
| 25 | move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 | ||
| 26 | move.d $r0, [$r1] | ||
| 27 | |||
| 28 | move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 | ||
| 29 | move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 | ||
| 30 | move.d $r0, [$r1] | ||
| 31 | |||
| 32 | move.d 0xFFFFFFFF, $r0 | ||
| 33 | move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 | ||
| 34 | move.d $r0, [$r1] | ||
| 35 | move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 | ||
| 36 | move.d $r0, [$r1] | ||
| 37 | move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 | ||
| 38 | move.d $r0, [$r1] | ||
| 39 | .endm | ||
| 40 | |||
| 41 | .macro START_CLOCKS | ||
| 42 | move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 | ||
| 43 | move.d [$r1], $r0 | ||
| 44 | or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ | ||
| 45 | REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ | ||
| 46 | REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 | ||
| 47 | move.d $r0, [$r1] | ||
| 48 | .endm | ||
| 49 | |||
| 50 | .macro SETUP_WAIT_STATES | ||
| 51 | move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 | ||
| 52 | move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 | ||
| 53 | move.d $r1, [$r0] | ||
| 54 | move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 | ||
| 55 | move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 | ||
| 56 | move.d $r1, [$r0] | ||
| 57 | move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 | ||
| 58 | move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 | ||
| 59 | move.d $r1, [$r0] | ||
| 60 | .endm | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/arbiter.h b/include/asm-cris/arch-v32/mach-fs/arbiter.h deleted file mode 100644 index a2e0ec8faa7d..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/arbiter.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_ARBITER_H | ||
| 2 | #define _ASM_CRIS_ARCH_ARBITER_H | ||
| 3 | |||
| 4 | #define EXT_REGION 0 | ||
| 5 | #define INT_REGION 1 | ||
| 6 | |||
| 7 | typedef void (watch_callback)(void); | ||
| 8 | |||
| 9 | enum { | ||
| 10 | arbiter_all_dmas = 0x3ff, | ||
| 11 | arbiter_cpu = 0xc00, | ||
| 12 | arbiter_all_clients = 0x3fff | ||
| 13 | }; | ||
| 14 | |||
| 15 | enum { | ||
| 16 | arbiter_all_read = 0x55, | ||
| 17 | arbiter_all_write = 0xaa, | ||
| 18 | arbiter_all_accesses = 0xff | ||
| 19 | }; | ||
| 20 | |||
| 21 | int crisv32_arbiter_allocate_bandwidth(int client, int region, | ||
| 22 | unsigned long bandwidth); | ||
| 23 | int crisv32_arbiter_watch(unsigned long start, unsigned long size, | ||
| 24 | unsigned long clients, unsigned long accesses, | ||
| 25 | watch_callback * cb); | ||
| 26 | int crisv32_arbiter_unwatch(int id); | ||
| 27 | |||
| 28 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index 0a409c92837e..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h +++ /dev/null | |||
| @@ -1,319 +0,0 @@ | |||
| 1 | #ifndef __bif_core_defs_asm_h | ||
| 2 | #define __bif_core_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_core_regs.r | ||
| 7 | * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r | ||
| 11 | * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_grp1_cfg, scope bif_core, type rw */ | ||
| 57 | #define reg_bif_core_rw_grp1_cfg___lw___lsb 0 | ||
| 58 | #define reg_bif_core_rw_grp1_cfg___lw___width 6 | ||
| 59 | #define reg_bif_core_rw_grp1_cfg___ew___lsb 6 | ||
| 60 | #define reg_bif_core_rw_grp1_cfg___ew___width 3 | ||
| 61 | #define reg_bif_core_rw_grp1_cfg___zw___lsb 9 | ||
| 62 | #define reg_bif_core_rw_grp1_cfg___zw___width 3 | ||
| 63 | #define reg_bif_core_rw_grp1_cfg___aw___lsb 12 | ||
| 64 | #define reg_bif_core_rw_grp1_cfg___aw___width 2 | ||
| 65 | #define reg_bif_core_rw_grp1_cfg___dw___lsb 14 | ||
| 66 | #define reg_bif_core_rw_grp1_cfg___dw___width 2 | ||
| 67 | #define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 | ||
| 68 | #define reg_bif_core_rw_grp1_cfg___ewb___width 2 | ||
| 69 | #define reg_bif_core_rw_grp1_cfg___bw___lsb 18 | ||
| 70 | #define reg_bif_core_rw_grp1_cfg___bw___width 1 | ||
| 71 | #define reg_bif_core_rw_grp1_cfg___bw___bit 18 | ||
| 72 | #define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 | ||
| 73 | #define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 | ||
| 74 | #define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 | ||
| 75 | #define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 | ||
| 76 | #define reg_bif_core_rw_grp1_cfg___erc_en___width 1 | ||
| 77 | #define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 | ||
| 78 | #define reg_bif_core_rw_grp1_cfg___mode___lsb 21 | ||
| 79 | #define reg_bif_core_rw_grp1_cfg___mode___width 1 | ||
| 80 | #define reg_bif_core_rw_grp1_cfg___mode___bit 21 | ||
| 81 | #define reg_bif_core_rw_grp1_cfg_offset 0 | ||
| 82 | |||
| 83 | /* Register rw_grp2_cfg, scope bif_core, type rw */ | ||
| 84 | #define reg_bif_core_rw_grp2_cfg___lw___lsb 0 | ||
| 85 | #define reg_bif_core_rw_grp2_cfg___lw___width 6 | ||
| 86 | #define reg_bif_core_rw_grp2_cfg___ew___lsb 6 | ||
| 87 | #define reg_bif_core_rw_grp2_cfg___ew___width 3 | ||
| 88 | #define reg_bif_core_rw_grp2_cfg___zw___lsb 9 | ||
| 89 | #define reg_bif_core_rw_grp2_cfg___zw___width 3 | ||
| 90 | #define reg_bif_core_rw_grp2_cfg___aw___lsb 12 | ||
| 91 | #define reg_bif_core_rw_grp2_cfg___aw___width 2 | ||
| 92 | #define reg_bif_core_rw_grp2_cfg___dw___lsb 14 | ||
| 93 | #define reg_bif_core_rw_grp2_cfg___dw___width 2 | ||
| 94 | #define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 | ||
| 95 | #define reg_bif_core_rw_grp2_cfg___ewb___width 2 | ||
| 96 | #define reg_bif_core_rw_grp2_cfg___bw___lsb 18 | ||
| 97 | #define reg_bif_core_rw_grp2_cfg___bw___width 1 | ||
| 98 | #define reg_bif_core_rw_grp2_cfg___bw___bit 18 | ||
| 99 | #define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 | ||
| 100 | #define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 | ||
| 101 | #define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 | ||
| 102 | #define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 | ||
| 103 | #define reg_bif_core_rw_grp2_cfg___erc_en___width 1 | ||
| 104 | #define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 | ||
| 105 | #define reg_bif_core_rw_grp2_cfg___mode___lsb 21 | ||
| 106 | #define reg_bif_core_rw_grp2_cfg___mode___width 1 | ||
| 107 | #define reg_bif_core_rw_grp2_cfg___mode___bit 21 | ||
| 108 | #define reg_bif_core_rw_grp2_cfg_offset 4 | ||
| 109 | |||
| 110 | /* Register rw_grp3_cfg, scope bif_core, type rw */ | ||
| 111 | #define reg_bif_core_rw_grp3_cfg___lw___lsb 0 | ||
| 112 | #define reg_bif_core_rw_grp3_cfg___lw___width 6 | ||
| 113 | #define reg_bif_core_rw_grp3_cfg___ew___lsb 6 | ||
| 114 | #define reg_bif_core_rw_grp3_cfg___ew___width 3 | ||
| 115 | #define reg_bif_core_rw_grp3_cfg___zw___lsb 9 | ||
| 116 | #define reg_bif_core_rw_grp3_cfg___zw___width 3 | ||
| 117 | #define reg_bif_core_rw_grp3_cfg___aw___lsb 12 | ||
| 118 | #define reg_bif_core_rw_grp3_cfg___aw___width 2 | ||
| 119 | #define reg_bif_core_rw_grp3_cfg___dw___lsb 14 | ||
| 120 | #define reg_bif_core_rw_grp3_cfg___dw___width 2 | ||
| 121 | #define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 | ||
| 122 | #define reg_bif_core_rw_grp3_cfg___ewb___width 2 | ||
| 123 | #define reg_bif_core_rw_grp3_cfg___bw___lsb 18 | ||
| 124 | #define reg_bif_core_rw_grp3_cfg___bw___width 1 | ||
| 125 | #define reg_bif_core_rw_grp3_cfg___bw___bit 18 | ||
| 126 | #define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 | ||
| 127 | #define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 | ||
| 128 | #define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 | ||
| 129 | #define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 | ||
| 130 | #define reg_bif_core_rw_grp3_cfg___erc_en___width 1 | ||
| 131 | #define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 | ||
| 132 | #define reg_bif_core_rw_grp3_cfg___mode___lsb 21 | ||
| 133 | #define reg_bif_core_rw_grp3_cfg___mode___width 1 | ||
| 134 | #define reg_bif_core_rw_grp3_cfg___mode___bit 21 | ||
| 135 | #define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 | ||
| 136 | #define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 | ||
| 137 | #define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 | ||
| 138 | #define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 | ||
| 139 | #define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 | ||
| 140 | #define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 | ||
| 141 | #define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 | ||
| 142 | #define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 | ||
| 143 | #define reg_bif_core_rw_grp3_cfg_offset 8 | ||
| 144 | |||
| 145 | /* Register rw_grp4_cfg, scope bif_core, type rw */ | ||
| 146 | #define reg_bif_core_rw_grp4_cfg___lw___lsb 0 | ||
| 147 | #define reg_bif_core_rw_grp4_cfg___lw___width 6 | ||
| 148 | #define reg_bif_core_rw_grp4_cfg___ew___lsb 6 | ||
| 149 | #define reg_bif_core_rw_grp4_cfg___ew___width 3 | ||
| 150 | #define reg_bif_core_rw_grp4_cfg___zw___lsb 9 | ||
| 151 | #define reg_bif_core_rw_grp4_cfg___zw___width 3 | ||
| 152 | #define reg_bif_core_rw_grp4_cfg___aw___lsb 12 | ||
| 153 | #define reg_bif_core_rw_grp4_cfg___aw___width 2 | ||
| 154 | #define reg_bif_core_rw_grp4_cfg___dw___lsb 14 | ||
| 155 | #define reg_bif_core_rw_grp4_cfg___dw___width 2 | ||
| 156 | #define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 | ||
| 157 | #define reg_bif_core_rw_grp4_cfg___ewb___width 2 | ||
| 158 | #define reg_bif_core_rw_grp4_cfg___bw___lsb 18 | ||
| 159 | #define reg_bif_core_rw_grp4_cfg___bw___width 1 | ||
| 160 | #define reg_bif_core_rw_grp4_cfg___bw___bit 18 | ||
| 161 | #define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 | ||
| 162 | #define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 | ||
| 163 | #define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 | ||
| 164 | #define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 | ||
| 165 | #define reg_bif_core_rw_grp4_cfg___erc_en___width 1 | ||
| 166 | #define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 | ||
| 167 | #define reg_bif_core_rw_grp4_cfg___mode___lsb 21 | ||
| 168 | #define reg_bif_core_rw_grp4_cfg___mode___width 1 | ||
| 169 | #define reg_bif_core_rw_grp4_cfg___mode___bit 21 | ||
| 170 | #define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 | ||
| 171 | #define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 | ||
| 172 | #define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 | ||
| 173 | #define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 | ||
| 174 | #define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 | ||
| 175 | #define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 | ||
| 176 | #define reg_bif_core_rw_grp4_cfg_offset 12 | ||
| 177 | |||
| 178 | /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ | ||
| 179 | #define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 | ||
| 180 | #define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 | ||
| 181 | #define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 | ||
| 182 | #define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 | ||
| 183 | #define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 | ||
| 184 | #define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 | ||
| 185 | #define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 | ||
| 186 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 | ||
| 187 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 | ||
| 188 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 | ||
| 189 | #define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 | ||
| 190 | #define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 | ||
| 191 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 | ||
| 192 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 | ||
| 193 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 | ||
| 194 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 | ||
| 195 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 | ||
| 196 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 | ||
| 197 | #define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 | ||
| 198 | #define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 | ||
| 199 | #define reg_bif_core_rw_sdram_cfg_grp0_offset 16 | ||
| 200 | |||
| 201 | /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ | ||
| 202 | #define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 | ||
| 203 | #define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 | ||
| 204 | #define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 | ||
| 205 | #define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 | ||
| 206 | #define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 | ||
| 207 | #define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 | ||
| 208 | #define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 | ||
| 209 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 | ||
| 210 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 | ||
| 211 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 | ||
| 212 | #define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 | ||
| 213 | #define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 | ||
| 214 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 | ||
| 215 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 | ||
| 216 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 | ||
| 217 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 | ||
| 218 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 | ||
| 219 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 | ||
| 220 | #define reg_bif_core_rw_sdram_cfg_grp1_offset 20 | ||
| 221 | |||
| 222 | /* Register rw_sdram_timing, scope bif_core, type rw */ | ||
| 223 | #define reg_bif_core_rw_sdram_timing___cl___lsb 0 | ||
| 224 | #define reg_bif_core_rw_sdram_timing___cl___width 3 | ||
| 225 | #define reg_bif_core_rw_sdram_timing___rcd___lsb 3 | ||
| 226 | #define reg_bif_core_rw_sdram_timing___rcd___width 3 | ||
| 227 | #define reg_bif_core_rw_sdram_timing___rp___lsb 6 | ||
| 228 | #define reg_bif_core_rw_sdram_timing___rp___width 3 | ||
| 229 | #define reg_bif_core_rw_sdram_timing___rc___lsb 9 | ||
| 230 | #define reg_bif_core_rw_sdram_timing___rc___width 2 | ||
| 231 | #define reg_bif_core_rw_sdram_timing___dpl___lsb 11 | ||
| 232 | #define reg_bif_core_rw_sdram_timing___dpl___width 2 | ||
| 233 | #define reg_bif_core_rw_sdram_timing___pde___lsb 13 | ||
| 234 | #define reg_bif_core_rw_sdram_timing___pde___width 1 | ||
| 235 | #define reg_bif_core_rw_sdram_timing___pde___bit 13 | ||
| 236 | #define reg_bif_core_rw_sdram_timing___ref___lsb 14 | ||
| 237 | #define reg_bif_core_rw_sdram_timing___ref___width 2 | ||
| 238 | #define reg_bif_core_rw_sdram_timing___cpd___lsb 16 | ||
| 239 | #define reg_bif_core_rw_sdram_timing___cpd___width 1 | ||
| 240 | #define reg_bif_core_rw_sdram_timing___cpd___bit 16 | ||
| 241 | #define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 | ||
| 242 | #define reg_bif_core_rw_sdram_timing___sdcke___width 1 | ||
| 243 | #define reg_bif_core_rw_sdram_timing___sdcke___bit 17 | ||
| 244 | #define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 | ||
| 245 | #define reg_bif_core_rw_sdram_timing___sdclk___width 1 | ||
| 246 | #define reg_bif_core_rw_sdram_timing___sdclk___bit 18 | ||
| 247 | #define reg_bif_core_rw_sdram_timing_offset 24 | ||
| 248 | |||
| 249 | /* Register rw_sdram_cmd, scope bif_core, type rw */ | ||
| 250 | #define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 | ||
| 251 | #define reg_bif_core_rw_sdram_cmd___cmd___width 3 | ||
| 252 | #define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 | ||
| 253 | #define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 | ||
| 254 | #define reg_bif_core_rw_sdram_cmd_offset 28 | ||
| 255 | |||
| 256 | /* Register rs_sdram_ref_stat, scope bif_core, type rs */ | ||
| 257 | #define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 | ||
| 258 | #define reg_bif_core_rs_sdram_ref_stat___ok___width 1 | ||
| 259 | #define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 | ||
| 260 | #define reg_bif_core_rs_sdram_ref_stat_offset 32 | ||
| 261 | |||
| 262 | /* Register r_sdram_ref_stat, scope bif_core, type r */ | ||
| 263 | #define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 | ||
| 264 | #define reg_bif_core_r_sdram_ref_stat___ok___width 1 | ||
| 265 | #define reg_bif_core_r_sdram_ref_stat___ok___bit 0 | ||
| 266 | #define reg_bif_core_r_sdram_ref_stat_offset 36 | ||
| 267 | |||
| 268 | |||
| 269 | /* Constants */ | ||
| 270 | #define regk_bif_core_bank2 0x00000000 | ||
| 271 | #define regk_bif_core_bank4 0x00000001 | ||
| 272 | #define regk_bif_core_bit10 0x0000000a | ||
| 273 | #define regk_bif_core_bit11 0x0000000b | ||
| 274 | #define regk_bif_core_bit12 0x0000000c | ||
| 275 | #define regk_bif_core_bit13 0x0000000d | ||
| 276 | #define regk_bif_core_bit14 0x0000000e | ||
| 277 | #define regk_bif_core_bit15 0x0000000f | ||
| 278 | #define regk_bif_core_bit16 0x00000010 | ||
| 279 | #define regk_bif_core_bit17 0x00000011 | ||
| 280 | #define regk_bif_core_bit18 0x00000012 | ||
| 281 | #define regk_bif_core_bit19 0x00000013 | ||
| 282 | #define regk_bif_core_bit20 0x00000014 | ||
| 283 | #define regk_bif_core_bit21 0x00000015 | ||
| 284 | #define regk_bif_core_bit22 0x00000016 | ||
| 285 | #define regk_bif_core_bit23 0x00000017 | ||
| 286 | #define regk_bif_core_bit24 0x00000018 | ||
| 287 | #define regk_bif_core_bit25 0x00000019 | ||
| 288 | #define regk_bif_core_bit26 0x0000001a | ||
| 289 | #define regk_bif_core_bit27 0x0000001b | ||
| 290 | #define regk_bif_core_bit28 0x0000001c | ||
| 291 | #define regk_bif_core_bit29 0x0000001d | ||
| 292 | #define regk_bif_core_bit9 0x00000009 | ||
| 293 | #define regk_bif_core_bw16 0x00000001 | ||
| 294 | #define regk_bif_core_bw32 0x00000000 | ||
| 295 | #define regk_bif_core_bwe 0x00000000 | ||
| 296 | #define regk_bif_core_cwe 0x00000001 | ||
| 297 | #define regk_bif_core_e15us 0x00000001 | ||
| 298 | #define regk_bif_core_e7800ns 0x00000002 | ||
| 299 | #define regk_bif_core_grp0 0x00000000 | ||
| 300 | #define regk_bif_core_grp1 0x00000001 | ||
| 301 | #define regk_bif_core_mrs 0x00000003 | ||
| 302 | #define regk_bif_core_no 0x00000000 | ||
| 303 | #define regk_bif_core_none 0x00000000 | ||
| 304 | #define regk_bif_core_nop 0x00000000 | ||
| 305 | #define regk_bif_core_off 0x00000000 | ||
| 306 | #define regk_bif_core_pre 0x00000002 | ||
| 307 | #define regk_bif_core_r_sdram_ref_stat_default 0x00000001 | ||
| 308 | #define regk_bif_core_rd 0x00000002 | ||
| 309 | #define regk_bif_core_ref 0x00000001 | ||
| 310 | #define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 | ||
| 311 | #define regk_bif_core_rw_grp1_cfg_default 0x000006cf | ||
| 312 | #define regk_bif_core_rw_grp2_cfg_default 0x000006cf | ||
| 313 | #define regk_bif_core_rw_grp3_cfg_default 0x000006cf | ||
| 314 | #define regk_bif_core_rw_grp4_cfg_default 0x000006cf | ||
| 315 | #define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 | ||
| 316 | #define regk_bif_core_slf 0x00000004 | ||
| 317 | #define regk_bif_core_wr 0x00000001 | ||
| 318 | #define regk_bif_core_yes 0x00000001 | ||
| 319 | #endif /* __bif_core_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h deleted file mode 100644 index a9908dfc2937..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h +++ /dev/null | |||
| @@ -1,131 +0,0 @@ | |||
| 1 | #ifndef __config_defs_asm_h | ||
| 2 | #define __config_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../rtl/config_regs.r | ||
| 7 | * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp | ||
| 8 | * last modfied: Thu Mar 4 12:34:39 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r | ||
| 11 | * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register r_bootsel, scope config, type r */ | ||
| 57 | #define reg_config_r_bootsel___boot_mode___lsb 0 | ||
| 58 | #define reg_config_r_bootsel___boot_mode___width 3 | ||
| 59 | #define reg_config_r_bootsel___full_duplex___lsb 3 | ||
| 60 | #define reg_config_r_bootsel___full_duplex___width 1 | ||
| 61 | #define reg_config_r_bootsel___full_duplex___bit 3 | ||
| 62 | #define reg_config_r_bootsel___user___lsb 4 | ||
| 63 | #define reg_config_r_bootsel___user___width 1 | ||
| 64 | #define reg_config_r_bootsel___user___bit 4 | ||
| 65 | #define reg_config_r_bootsel___pll___lsb 5 | ||
| 66 | #define reg_config_r_bootsel___pll___width 1 | ||
| 67 | #define reg_config_r_bootsel___pll___bit 5 | ||
| 68 | #define reg_config_r_bootsel___flash_bw___lsb 6 | ||
| 69 | #define reg_config_r_bootsel___flash_bw___width 1 | ||
| 70 | #define reg_config_r_bootsel___flash_bw___bit 6 | ||
| 71 | #define reg_config_r_bootsel_offset 0 | ||
| 72 | |||
| 73 | /* Register rw_clk_ctrl, scope config, type rw */ | ||
| 74 | #define reg_config_rw_clk_ctrl___pll___lsb 0 | ||
| 75 | #define reg_config_rw_clk_ctrl___pll___width 1 | ||
| 76 | #define reg_config_rw_clk_ctrl___pll___bit 0 | ||
| 77 | #define reg_config_rw_clk_ctrl___cpu___lsb 1 | ||
| 78 | #define reg_config_rw_clk_ctrl___cpu___width 1 | ||
| 79 | #define reg_config_rw_clk_ctrl___cpu___bit 1 | ||
| 80 | #define reg_config_rw_clk_ctrl___iop___lsb 2 | ||
| 81 | #define reg_config_rw_clk_ctrl___iop___width 1 | ||
| 82 | #define reg_config_rw_clk_ctrl___iop___bit 2 | ||
| 83 | #define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 | ||
| 84 | #define reg_config_rw_clk_ctrl___dma01_eth0___width 1 | ||
| 85 | #define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 | ||
| 86 | #define reg_config_rw_clk_ctrl___dma23___lsb 4 | ||
| 87 | #define reg_config_rw_clk_ctrl___dma23___width 1 | ||
| 88 | #define reg_config_rw_clk_ctrl___dma23___bit 4 | ||
| 89 | #define reg_config_rw_clk_ctrl___dma45___lsb 5 | ||
| 90 | #define reg_config_rw_clk_ctrl___dma45___width 1 | ||
| 91 | #define reg_config_rw_clk_ctrl___dma45___bit 5 | ||
| 92 | #define reg_config_rw_clk_ctrl___dma67___lsb 6 | ||
| 93 | #define reg_config_rw_clk_ctrl___dma67___width 1 | ||
| 94 | #define reg_config_rw_clk_ctrl___dma67___bit 6 | ||
| 95 | #define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 | ||
| 96 | #define reg_config_rw_clk_ctrl___dma89_strcop___width 1 | ||
| 97 | #define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 | ||
| 98 | #define reg_config_rw_clk_ctrl___bif___lsb 8 | ||
| 99 | #define reg_config_rw_clk_ctrl___bif___width 1 | ||
| 100 | #define reg_config_rw_clk_ctrl___bif___bit 8 | ||
| 101 | #define reg_config_rw_clk_ctrl___fix_io___lsb 9 | ||
| 102 | #define reg_config_rw_clk_ctrl___fix_io___width 1 | ||
| 103 | #define reg_config_rw_clk_ctrl___fix_io___bit 9 | ||
| 104 | #define reg_config_rw_clk_ctrl_offset 4 | ||
| 105 | |||
| 106 | /* Register rw_pad_ctrl, scope config, type rw */ | ||
| 107 | #define reg_config_rw_pad_ctrl___usb_susp___lsb 0 | ||
| 108 | #define reg_config_rw_pad_ctrl___usb_susp___width 1 | ||
| 109 | #define reg_config_rw_pad_ctrl___usb_susp___bit 0 | ||
| 110 | #define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 | ||
| 111 | #define reg_config_rw_pad_ctrl___phyrst_n___width 1 | ||
| 112 | #define reg_config_rw_pad_ctrl___phyrst_n___bit 1 | ||
| 113 | #define reg_config_rw_pad_ctrl_offset 8 | ||
| 114 | |||
| 115 | |||
| 116 | /* Constants */ | ||
| 117 | #define regk_config_bw16 0x00000000 | ||
| 118 | #define regk_config_bw32 0x00000001 | ||
| 119 | #define regk_config_master 0x00000005 | ||
| 120 | #define regk_config_nand 0x00000003 | ||
| 121 | #define regk_config_net_rx 0x00000001 | ||
| 122 | #define regk_config_net_tx_rx 0x00000002 | ||
| 123 | #define regk_config_no 0x00000000 | ||
| 124 | #define regk_config_none 0x00000007 | ||
| 125 | #define regk_config_nor 0x00000000 | ||
| 126 | #define regk_config_rw_clk_ctrl_default 0x00000002 | ||
| 127 | #define regk_config_rw_pad_ctrl_default 0x00000000 | ||
| 128 | #define regk_config_ser 0x00000004 | ||
| 129 | #define regk_config_slave 0x00000006 | ||
| 130 | #define regk_config_yes 0x00000001 | ||
| 131 | #endif /* __config_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index be4c63936d90..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h +++ /dev/null | |||
| @@ -1,276 +0,0 @@ | |||
| 1 | #ifndef __gio_defs_asm_h | ||
| 2 | #define __gio_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/gio/rtl/gio_regs.r | ||
| 7 | * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:07:47 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r | ||
| 11 | * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 57 | #define reg_gio_rw_pa_dout___data___lsb 0 | ||
| 58 | #define reg_gio_rw_pa_dout___data___width 8 | ||
| 59 | #define reg_gio_rw_pa_dout_offset 0 | ||
| 60 | |||
| 61 | /* Register r_pa_din, scope gio, type r */ | ||
| 62 | #define reg_gio_r_pa_din___data___lsb 0 | ||
| 63 | #define reg_gio_r_pa_din___data___width 8 | ||
| 64 | #define reg_gio_r_pa_din_offset 4 | ||
| 65 | |||
| 66 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 67 | #define reg_gio_rw_pa_oe___oe___lsb 0 | ||
| 68 | #define reg_gio_rw_pa_oe___oe___width 8 | ||
| 69 | #define reg_gio_rw_pa_oe_offset 8 | ||
| 70 | |||
| 71 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 72 | #define reg_gio_rw_intr_cfg___pa0___lsb 0 | ||
| 73 | #define reg_gio_rw_intr_cfg___pa0___width 3 | ||
| 74 | #define reg_gio_rw_intr_cfg___pa1___lsb 3 | ||
| 75 | #define reg_gio_rw_intr_cfg___pa1___width 3 | ||
| 76 | #define reg_gio_rw_intr_cfg___pa2___lsb 6 | ||
| 77 | #define reg_gio_rw_intr_cfg___pa2___width 3 | ||
| 78 | #define reg_gio_rw_intr_cfg___pa3___lsb 9 | ||
| 79 | #define reg_gio_rw_intr_cfg___pa3___width 3 | ||
| 80 | #define reg_gio_rw_intr_cfg___pa4___lsb 12 | ||
| 81 | #define reg_gio_rw_intr_cfg___pa4___width 3 | ||
| 82 | #define reg_gio_rw_intr_cfg___pa5___lsb 15 | ||
| 83 | #define reg_gio_rw_intr_cfg___pa5___width 3 | ||
| 84 | #define reg_gio_rw_intr_cfg___pa6___lsb 18 | ||
| 85 | #define reg_gio_rw_intr_cfg___pa6___width 3 | ||
| 86 | #define reg_gio_rw_intr_cfg___pa7___lsb 21 | ||
| 87 | #define reg_gio_rw_intr_cfg___pa7___width 3 | ||
| 88 | #define reg_gio_rw_intr_cfg_offset 12 | ||
| 89 | |||
| 90 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 91 | #define reg_gio_rw_intr_mask___pa0___lsb 0 | ||
| 92 | #define reg_gio_rw_intr_mask___pa0___width 1 | ||
| 93 | #define reg_gio_rw_intr_mask___pa0___bit 0 | ||
| 94 | #define reg_gio_rw_intr_mask___pa1___lsb 1 | ||
| 95 | #define reg_gio_rw_intr_mask___pa1___width 1 | ||
| 96 | #define reg_gio_rw_intr_mask___pa1___bit 1 | ||
| 97 | #define reg_gio_rw_intr_mask___pa2___lsb 2 | ||
| 98 | #define reg_gio_rw_intr_mask___pa2___width 1 | ||
| 99 | #define reg_gio_rw_intr_mask___pa2___bit 2 | ||
| 100 | #define reg_gio_rw_intr_mask___pa3___lsb 3 | ||
| 101 | #define reg_gio_rw_intr_mask___pa3___width 1 | ||
| 102 | #define reg_gio_rw_intr_mask___pa3___bit 3 | ||
| 103 | #define reg_gio_rw_intr_mask___pa4___lsb 4 | ||
| 104 | #define reg_gio_rw_intr_mask___pa4___width 1 | ||
| 105 | #define reg_gio_rw_intr_mask___pa4___bit 4 | ||
| 106 | #define reg_gio_rw_intr_mask___pa5___lsb 5 | ||
| 107 | #define reg_gio_rw_intr_mask___pa5___width 1 | ||
| 108 | #define reg_gio_rw_intr_mask___pa5___bit 5 | ||
| 109 | #define reg_gio_rw_intr_mask___pa6___lsb 6 | ||
| 110 | #define reg_gio_rw_intr_mask___pa6___width 1 | ||
| 111 | #define reg_gio_rw_intr_mask___pa6___bit 6 | ||
| 112 | #define reg_gio_rw_intr_mask___pa7___lsb 7 | ||
| 113 | #define reg_gio_rw_intr_mask___pa7___width 1 | ||
| 114 | #define reg_gio_rw_intr_mask___pa7___bit 7 | ||
| 115 | #define reg_gio_rw_intr_mask_offset 16 | ||
| 116 | |||
| 117 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 118 | #define reg_gio_rw_ack_intr___pa0___lsb 0 | ||
| 119 | #define reg_gio_rw_ack_intr___pa0___width 1 | ||
| 120 | #define reg_gio_rw_ack_intr___pa0___bit 0 | ||
| 121 | #define reg_gio_rw_ack_intr___pa1___lsb 1 | ||
| 122 | #define reg_gio_rw_ack_intr___pa1___width 1 | ||
| 123 | #define reg_gio_rw_ack_intr___pa1___bit 1 | ||
| 124 | #define reg_gio_rw_ack_intr___pa2___lsb 2 | ||
| 125 | #define reg_gio_rw_ack_intr___pa2___width 1 | ||
| 126 | #define reg_gio_rw_ack_intr___pa2___bit 2 | ||
| 127 | #define reg_gio_rw_ack_intr___pa3___lsb 3 | ||
| 128 | #define reg_gio_rw_ack_intr___pa3___width 1 | ||
| 129 | #define reg_gio_rw_ack_intr___pa3___bit 3 | ||
| 130 | #define reg_gio_rw_ack_intr___pa4___lsb 4 | ||
| 131 | #define reg_gio_rw_ack_intr___pa4___width 1 | ||
| 132 | #define reg_gio_rw_ack_intr___pa4___bit 4 | ||
| 133 | #define reg_gio_rw_ack_intr___pa5___lsb 5 | ||
| 134 | #define reg_gio_rw_ack_intr___pa5___width 1 | ||
| 135 | #define reg_gio_rw_ack_intr___pa5___bit 5 | ||
| 136 | #define reg_gio_rw_ack_intr___pa6___lsb 6 | ||
| 137 | #define reg_gio_rw_ack_intr___pa6___width 1 | ||
| 138 | #define reg_gio_rw_ack_intr___pa6___bit 6 | ||
| 139 | #define reg_gio_rw_ack_intr___pa7___lsb 7 | ||
| 140 | #define reg_gio_rw_ack_intr___pa7___width 1 | ||
| 141 | #define reg_gio_rw_ack_intr___pa7___bit 7 | ||
| 142 | #define reg_gio_rw_ack_intr_offset 20 | ||
| 143 | |||
| 144 | /* Register r_intr, scope gio, type r */ | ||
| 145 | #define reg_gio_r_intr___pa0___lsb 0 | ||
| 146 | #define reg_gio_r_intr___pa0___width 1 | ||
| 147 | #define reg_gio_r_intr___pa0___bit 0 | ||
| 148 | #define reg_gio_r_intr___pa1___lsb 1 | ||
| 149 | #define reg_gio_r_intr___pa1___width 1 | ||
| 150 | #define reg_gio_r_intr___pa1___bit 1 | ||
| 151 | #define reg_gio_r_intr___pa2___lsb 2 | ||
| 152 | #define reg_gio_r_intr___pa2___width 1 | ||
| 153 | #define reg_gio_r_intr___pa2___bit 2 | ||
| 154 | #define reg_gio_r_intr___pa3___lsb 3 | ||
| 155 | #define reg_gio_r_intr___pa3___width 1 | ||
| 156 | #define reg_gio_r_intr___pa3___bit 3 | ||
| 157 | #define reg_gio_r_intr___pa4___lsb 4 | ||
| 158 | #define reg_gio_r_intr___pa4___width 1 | ||
| 159 | #define reg_gio_r_intr___pa4___bit 4 | ||
| 160 | #define reg_gio_r_intr___pa5___lsb 5 | ||
| 161 | #define reg_gio_r_intr___pa5___width 1 | ||
| 162 | #define reg_gio_r_intr___pa5___bit 5 | ||
| 163 | #define reg_gio_r_intr___pa6___lsb 6 | ||
| 164 | #define reg_gio_r_intr___pa6___width 1 | ||
| 165 | #define reg_gio_r_intr___pa6___bit 6 | ||
| 166 | #define reg_gio_r_intr___pa7___lsb 7 | ||
| 167 | #define reg_gio_r_intr___pa7___width 1 | ||
| 168 | #define reg_gio_r_intr___pa7___bit 7 | ||
| 169 | #define reg_gio_r_intr_offset 24 | ||
| 170 | |||
| 171 | /* Register r_masked_intr, scope gio, type r */ | ||
| 172 | #define reg_gio_r_masked_intr___pa0___lsb 0 | ||
| 173 | #define reg_gio_r_masked_intr___pa0___width 1 | ||
| 174 | #define reg_gio_r_masked_intr___pa0___bit 0 | ||
| 175 | #define reg_gio_r_masked_intr___pa1___lsb 1 | ||
| 176 | #define reg_gio_r_masked_intr___pa1___width 1 | ||
| 177 | #define reg_gio_r_masked_intr___pa1___bit 1 | ||
| 178 | #define reg_gio_r_masked_intr___pa2___lsb 2 | ||
| 179 | #define reg_gio_r_masked_intr___pa2___width 1 | ||
| 180 | #define reg_gio_r_masked_intr___pa2___bit 2 | ||
| 181 | #define reg_gio_r_masked_intr___pa3___lsb 3 | ||
| 182 | #define reg_gio_r_masked_intr___pa3___width 1 | ||
| 183 | #define reg_gio_r_masked_intr___pa3___bit 3 | ||
| 184 | #define reg_gio_r_masked_intr___pa4___lsb 4 | ||
| 185 | #define reg_gio_r_masked_intr___pa4___width 1 | ||
| 186 | #define reg_gio_r_masked_intr___pa4___bit 4 | ||
| 187 | #define reg_gio_r_masked_intr___pa5___lsb 5 | ||
| 188 | #define reg_gio_r_masked_intr___pa5___width 1 | ||
| 189 | #define reg_gio_r_masked_intr___pa5___bit 5 | ||
| 190 | #define reg_gio_r_masked_intr___pa6___lsb 6 | ||
| 191 | #define reg_gio_r_masked_intr___pa6___width 1 | ||
| 192 | #define reg_gio_r_masked_intr___pa6___bit 6 | ||
| 193 | #define reg_gio_r_masked_intr___pa7___lsb 7 | ||
| 194 | #define reg_gio_r_masked_intr___pa7___width 1 | ||
| 195 | #define reg_gio_r_masked_intr___pa7___bit 7 | ||
| 196 | #define reg_gio_r_masked_intr_offset 28 | ||
| 197 | |||
| 198 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 199 | #define reg_gio_rw_pb_dout___data___lsb 0 | ||
| 200 | #define reg_gio_rw_pb_dout___data___width 18 | ||
| 201 | #define reg_gio_rw_pb_dout_offset 32 | ||
| 202 | |||
| 203 | /* Register r_pb_din, scope gio, type r */ | ||
| 204 | #define reg_gio_r_pb_din___data___lsb 0 | ||
| 205 | #define reg_gio_r_pb_din___data___width 18 | ||
| 206 | #define reg_gio_r_pb_din_offset 36 | ||
| 207 | |||
| 208 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 209 | #define reg_gio_rw_pb_oe___oe___lsb 0 | ||
| 210 | #define reg_gio_rw_pb_oe___oe___width 18 | ||
| 211 | #define reg_gio_rw_pb_oe_offset 40 | ||
| 212 | |||
| 213 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 214 | #define reg_gio_rw_pc_dout___data___lsb 0 | ||
| 215 | #define reg_gio_rw_pc_dout___data___width 18 | ||
| 216 | #define reg_gio_rw_pc_dout_offset 48 | ||
| 217 | |||
| 218 | /* Register r_pc_din, scope gio, type r */ | ||
| 219 | #define reg_gio_r_pc_din___data___lsb 0 | ||
| 220 | #define reg_gio_r_pc_din___data___width 18 | ||
| 221 | #define reg_gio_r_pc_din_offset 52 | ||
| 222 | |||
| 223 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 224 | #define reg_gio_rw_pc_oe___oe___lsb 0 | ||
| 225 | #define reg_gio_rw_pc_oe___oe___width 18 | ||
| 226 | #define reg_gio_rw_pc_oe_offset 56 | ||
| 227 | |||
| 228 | /* Register rw_pd_dout, scope gio, type rw */ | ||
| 229 | #define reg_gio_rw_pd_dout___data___lsb 0 | ||
| 230 | #define reg_gio_rw_pd_dout___data___width 18 | ||
| 231 | #define reg_gio_rw_pd_dout_offset 64 | ||
| 232 | |||
| 233 | /* Register r_pd_din, scope gio, type r */ | ||
| 234 | #define reg_gio_r_pd_din___data___lsb 0 | ||
| 235 | #define reg_gio_r_pd_din___data___width 18 | ||
| 236 | #define reg_gio_r_pd_din_offset 68 | ||
| 237 | |||
| 238 | /* Register rw_pd_oe, scope gio, type rw */ | ||
| 239 | #define reg_gio_rw_pd_oe___oe___lsb 0 | ||
| 240 | #define reg_gio_rw_pd_oe___oe___width 18 | ||
| 241 | #define reg_gio_rw_pd_oe_offset 72 | ||
| 242 | |||
| 243 | /* Register rw_pe_dout, scope gio, type rw */ | ||
| 244 | #define reg_gio_rw_pe_dout___data___lsb 0 | ||
| 245 | #define reg_gio_rw_pe_dout___data___width 18 | ||
| 246 | #define reg_gio_rw_pe_dout_offset 80 | ||
| 247 | |||
| 248 | /* Register r_pe_din, scope gio, type r */ | ||
| 249 | #define reg_gio_r_pe_din___data___lsb 0 | ||
| 250 | #define reg_gio_r_pe_din___data___width 18 | ||
| 251 | #define reg_gio_r_pe_din_offset 84 | ||
| 252 | |||
| 253 | /* Register rw_pe_oe, scope gio, type rw */ | ||
| 254 | #define reg_gio_rw_pe_oe___oe___lsb 0 | ||
| 255 | #define reg_gio_rw_pe_oe___oe___width 18 | ||
| 256 | #define reg_gio_rw_pe_oe_offset 88 | ||
| 257 | |||
| 258 | |||
| 259 | /* Constants */ | ||
| 260 | #define regk_gio_anyedge 0x00000007 | ||
| 261 | #define regk_gio_hi 0x00000001 | ||
| 262 | #define regk_gio_lo 0x00000002 | ||
| 263 | #define regk_gio_negedge 0x00000006 | ||
| 264 | #define regk_gio_no 0x00000000 | ||
| 265 | #define regk_gio_off 0x00000000 | ||
| 266 | #define regk_gio_posedge 0x00000005 | ||
| 267 | #define regk_gio_rw_intr_cfg_default 0x00000000 | ||
| 268 | #define regk_gio_rw_intr_mask_default 0x00000000 | ||
| 269 | #define regk_gio_rw_pa_oe_default 0x00000000 | ||
| 270 | #define regk_gio_rw_pb_oe_default 0x00000000 | ||
| 271 | #define regk_gio_rw_pc_oe_default 0x00000000 | ||
| 272 | #define regk_gio_rw_pd_oe_default 0x00000000 | ||
| 273 | #define regk_gio_rw_pe_oe_default 0x00000000 | ||
| 274 | #define regk_gio_set 0x00000003 | ||
| 275 | #define regk_gio_yes 0x00000001 | ||
| 276 | #endif /* __gio_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 30cf5a936b64..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h +++ /dev/null | |||
| @@ -1,632 +0,0 @@ | |||
| 1 | #ifndef __pinmux_defs_asm_h | ||
| 2 | #define __pinmux_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 7 | * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:11 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 11 | * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_pa, scope pinmux, type rw */ | ||
| 57 | #define reg_pinmux_rw_pa___pa0___lsb 0 | ||
| 58 | #define reg_pinmux_rw_pa___pa0___width 1 | ||
| 59 | #define reg_pinmux_rw_pa___pa0___bit 0 | ||
| 60 | #define reg_pinmux_rw_pa___pa1___lsb 1 | ||
| 61 | #define reg_pinmux_rw_pa___pa1___width 1 | ||
| 62 | #define reg_pinmux_rw_pa___pa1___bit 1 | ||
| 63 | #define reg_pinmux_rw_pa___pa2___lsb 2 | ||
| 64 | #define reg_pinmux_rw_pa___pa2___width 1 | ||
| 65 | #define reg_pinmux_rw_pa___pa2___bit 2 | ||
| 66 | #define reg_pinmux_rw_pa___pa3___lsb 3 | ||
| 67 | #define reg_pinmux_rw_pa___pa3___width 1 | ||
| 68 | #define reg_pinmux_rw_pa___pa3___bit 3 | ||
| 69 | #define reg_pinmux_rw_pa___pa4___lsb 4 | ||
| 70 | #define reg_pinmux_rw_pa___pa4___width 1 | ||
| 71 | #define reg_pinmux_rw_pa___pa4___bit 4 | ||
| 72 | #define reg_pinmux_rw_pa___pa5___lsb 5 | ||
| 73 | #define reg_pinmux_rw_pa___pa5___width 1 | ||
| 74 | #define reg_pinmux_rw_pa___pa5___bit 5 | ||
| 75 | #define reg_pinmux_rw_pa___pa6___lsb 6 | ||
| 76 | #define reg_pinmux_rw_pa___pa6___width 1 | ||
| 77 | #define reg_pinmux_rw_pa___pa6___bit 6 | ||
| 78 | #define reg_pinmux_rw_pa___pa7___lsb 7 | ||
| 79 | #define reg_pinmux_rw_pa___pa7___width 1 | ||
| 80 | #define reg_pinmux_rw_pa___pa7___bit 7 | ||
| 81 | #define reg_pinmux_rw_pa___csp2_n___lsb 8 | ||
| 82 | #define reg_pinmux_rw_pa___csp2_n___width 1 | ||
| 83 | #define reg_pinmux_rw_pa___csp2_n___bit 8 | ||
| 84 | #define reg_pinmux_rw_pa___csp3_n___lsb 9 | ||
| 85 | #define reg_pinmux_rw_pa___csp3_n___width 1 | ||
| 86 | #define reg_pinmux_rw_pa___csp3_n___bit 9 | ||
| 87 | #define reg_pinmux_rw_pa___csp5_n___lsb 10 | ||
| 88 | #define reg_pinmux_rw_pa___csp5_n___width 1 | ||
| 89 | #define reg_pinmux_rw_pa___csp5_n___bit 10 | ||
| 90 | #define reg_pinmux_rw_pa___csp6_n___lsb 11 | ||
| 91 | #define reg_pinmux_rw_pa___csp6_n___width 1 | ||
| 92 | #define reg_pinmux_rw_pa___csp6_n___bit 11 | ||
| 93 | #define reg_pinmux_rw_pa___hsh4___lsb 12 | ||
| 94 | #define reg_pinmux_rw_pa___hsh4___width 1 | ||
| 95 | #define reg_pinmux_rw_pa___hsh4___bit 12 | ||
| 96 | #define reg_pinmux_rw_pa___hsh5___lsb 13 | ||
| 97 | #define reg_pinmux_rw_pa___hsh5___width 1 | ||
| 98 | #define reg_pinmux_rw_pa___hsh5___bit 13 | ||
| 99 | #define reg_pinmux_rw_pa___hsh6___lsb 14 | ||
| 100 | #define reg_pinmux_rw_pa___hsh6___width 1 | ||
| 101 | #define reg_pinmux_rw_pa___hsh6___bit 14 | ||
| 102 | #define reg_pinmux_rw_pa___hsh7___lsb 15 | ||
| 103 | #define reg_pinmux_rw_pa___hsh7___width 1 | ||
| 104 | #define reg_pinmux_rw_pa___hsh7___bit 15 | ||
| 105 | #define reg_pinmux_rw_pa_offset 0 | ||
| 106 | |||
| 107 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 108 | #define reg_pinmux_rw_hwprot___ser1___lsb 0 | ||
| 109 | #define reg_pinmux_rw_hwprot___ser1___width 1 | ||
| 110 | #define reg_pinmux_rw_hwprot___ser1___bit 0 | ||
| 111 | #define reg_pinmux_rw_hwprot___ser2___lsb 1 | ||
| 112 | #define reg_pinmux_rw_hwprot___ser2___width 1 | ||
| 113 | #define reg_pinmux_rw_hwprot___ser2___bit 1 | ||
| 114 | #define reg_pinmux_rw_hwprot___ser3___lsb 2 | ||
| 115 | #define reg_pinmux_rw_hwprot___ser3___width 1 | ||
| 116 | #define reg_pinmux_rw_hwprot___ser3___bit 2 | ||
| 117 | #define reg_pinmux_rw_hwprot___sser0___lsb 3 | ||
| 118 | #define reg_pinmux_rw_hwprot___sser0___width 1 | ||
| 119 | #define reg_pinmux_rw_hwprot___sser0___bit 3 | ||
| 120 | #define reg_pinmux_rw_hwprot___sser1___lsb 4 | ||
| 121 | #define reg_pinmux_rw_hwprot___sser1___width 1 | ||
| 122 | #define reg_pinmux_rw_hwprot___sser1___bit 4 | ||
| 123 | #define reg_pinmux_rw_hwprot___ata0___lsb 5 | ||
| 124 | #define reg_pinmux_rw_hwprot___ata0___width 1 | ||
| 125 | #define reg_pinmux_rw_hwprot___ata0___bit 5 | ||
| 126 | #define reg_pinmux_rw_hwprot___ata1___lsb 6 | ||
| 127 | #define reg_pinmux_rw_hwprot___ata1___width 1 | ||
| 128 | #define reg_pinmux_rw_hwprot___ata1___bit 6 | ||
| 129 | #define reg_pinmux_rw_hwprot___ata2___lsb 7 | ||
| 130 | #define reg_pinmux_rw_hwprot___ata2___width 1 | ||
| 131 | #define reg_pinmux_rw_hwprot___ata2___bit 7 | ||
| 132 | #define reg_pinmux_rw_hwprot___ata3___lsb 8 | ||
| 133 | #define reg_pinmux_rw_hwprot___ata3___width 1 | ||
| 134 | #define reg_pinmux_rw_hwprot___ata3___bit 8 | ||
| 135 | #define reg_pinmux_rw_hwprot___ata___lsb 9 | ||
| 136 | #define reg_pinmux_rw_hwprot___ata___width 1 | ||
| 137 | #define reg_pinmux_rw_hwprot___ata___bit 9 | ||
| 138 | #define reg_pinmux_rw_hwprot___eth1___lsb 10 | ||
| 139 | #define reg_pinmux_rw_hwprot___eth1___width 1 | ||
| 140 | #define reg_pinmux_rw_hwprot___eth1___bit 10 | ||
| 141 | #define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 | ||
| 142 | #define reg_pinmux_rw_hwprot___eth1_mgm___width 1 | ||
| 143 | #define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 | ||
| 144 | #define reg_pinmux_rw_hwprot___timer___lsb 12 | ||
| 145 | #define reg_pinmux_rw_hwprot___timer___width 1 | ||
| 146 | #define reg_pinmux_rw_hwprot___timer___bit 12 | ||
| 147 | #define reg_pinmux_rw_hwprot___p21___lsb 13 | ||
| 148 | #define reg_pinmux_rw_hwprot___p21___width 1 | ||
| 149 | #define reg_pinmux_rw_hwprot___p21___bit 13 | ||
| 150 | #define reg_pinmux_rw_hwprot_offset 4 | ||
| 151 | |||
| 152 | /* Register rw_pb_gio, scope pinmux, type rw */ | ||
| 153 | #define reg_pinmux_rw_pb_gio___pb0___lsb 0 | ||
| 154 | #define reg_pinmux_rw_pb_gio___pb0___width 1 | ||
| 155 | #define reg_pinmux_rw_pb_gio___pb0___bit 0 | ||
| 156 | #define reg_pinmux_rw_pb_gio___pb1___lsb 1 | ||
| 157 | #define reg_pinmux_rw_pb_gio___pb1___width 1 | ||
| 158 | #define reg_pinmux_rw_pb_gio___pb1___bit 1 | ||
| 159 | #define reg_pinmux_rw_pb_gio___pb2___lsb 2 | ||
| 160 | #define reg_pinmux_rw_pb_gio___pb2___width 1 | ||
| 161 | #define reg_pinmux_rw_pb_gio___pb2___bit 2 | ||
| 162 | #define reg_pinmux_rw_pb_gio___pb3___lsb 3 | ||
| 163 | #define reg_pinmux_rw_pb_gio___pb3___width 1 | ||
| 164 | #define reg_pinmux_rw_pb_gio___pb3___bit 3 | ||
| 165 | #define reg_pinmux_rw_pb_gio___pb4___lsb 4 | ||
| 166 | #define reg_pinmux_rw_pb_gio___pb4___width 1 | ||
| 167 | #define reg_pinmux_rw_pb_gio___pb4___bit 4 | ||
| 168 | #define reg_pinmux_rw_pb_gio___pb5___lsb 5 | ||
| 169 | #define reg_pinmux_rw_pb_gio___pb5___width 1 | ||
| 170 | #define reg_pinmux_rw_pb_gio___pb5___bit 5 | ||
| 171 | #define reg_pinmux_rw_pb_gio___pb6___lsb 6 | ||
| 172 | #define reg_pinmux_rw_pb_gio___pb6___width 1 | ||
| 173 | #define reg_pinmux_rw_pb_gio___pb6___bit 6 | ||
| 174 | #define reg_pinmux_rw_pb_gio___pb7___lsb 7 | ||
| 175 | #define reg_pinmux_rw_pb_gio___pb7___width 1 | ||
| 176 | #define reg_pinmux_rw_pb_gio___pb7___bit 7 | ||
| 177 | #define reg_pinmux_rw_pb_gio___pb8___lsb 8 | ||
| 178 | #define reg_pinmux_rw_pb_gio___pb8___width 1 | ||
| 179 | #define reg_pinmux_rw_pb_gio___pb8___bit 8 | ||
| 180 | #define reg_pinmux_rw_pb_gio___pb9___lsb 9 | ||
| 181 | #define reg_pinmux_rw_pb_gio___pb9___width 1 | ||
| 182 | #define reg_pinmux_rw_pb_gio___pb9___bit 9 | ||
| 183 | #define reg_pinmux_rw_pb_gio___pb10___lsb 10 | ||
| 184 | #define reg_pinmux_rw_pb_gio___pb10___width 1 | ||
| 185 | #define reg_pinmux_rw_pb_gio___pb10___bit 10 | ||
| 186 | #define reg_pinmux_rw_pb_gio___pb11___lsb 11 | ||
| 187 | #define reg_pinmux_rw_pb_gio___pb11___width 1 | ||
| 188 | #define reg_pinmux_rw_pb_gio___pb11___bit 11 | ||
| 189 | #define reg_pinmux_rw_pb_gio___pb12___lsb 12 | ||
| 190 | #define reg_pinmux_rw_pb_gio___pb12___width 1 | ||
| 191 | #define reg_pinmux_rw_pb_gio___pb12___bit 12 | ||
| 192 | #define reg_pinmux_rw_pb_gio___pb13___lsb 13 | ||
| 193 | #define reg_pinmux_rw_pb_gio___pb13___width 1 | ||
| 194 | #define reg_pinmux_rw_pb_gio___pb13___bit 13 | ||
| 195 | #define reg_pinmux_rw_pb_gio___pb14___lsb 14 | ||
| 196 | #define reg_pinmux_rw_pb_gio___pb14___width 1 | ||
| 197 | #define reg_pinmux_rw_pb_gio___pb14___bit 14 | ||
| 198 | #define reg_pinmux_rw_pb_gio___pb15___lsb 15 | ||
| 199 | #define reg_pinmux_rw_pb_gio___pb15___width 1 | ||
| 200 | #define reg_pinmux_rw_pb_gio___pb15___bit 15 | ||
| 201 | #define reg_pinmux_rw_pb_gio___pb16___lsb 16 | ||
| 202 | #define reg_pinmux_rw_pb_gio___pb16___width 1 | ||
| 203 | #define reg_pinmux_rw_pb_gio___pb16___bit 16 | ||
| 204 | #define reg_pinmux_rw_pb_gio___pb17___lsb 17 | ||
| 205 | #define reg_pinmux_rw_pb_gio___pb17___width 1 | ||
| 206 | #define reg_pinmux_rw_pb_gio___pb17___bit 17 | ||
| 207 | #define reg_pinmux_rw_pb_gio_offset 8 | ||
| 208 | |||
| 209 | /* Register rw_pb_iop, scope pinmux, type rw */ | ||
| 210 | #define reg_pinmux_rw_pb_iop___pb0___lsb 0 | ||
| 211 | #define reg_pinmux_rw_pb_iop___pb0___width 1 | ||
| 212 | #define reg_pinmux_rw_pb_iop___pb0___bit 0 | ||
| 213 | #define reg_pinmux_rw_pb_iop___pb1___lsb 1 | ||
| 214 | #define reg_pinmux_rw_pb_iop___pb1___width 1 | ||
| 215 | #define reg_pinmux_rw_pb_iop___pb1___bit 1 | ||
| 216 | #define reg_pinmux_rw_pb_iop___pb2___lsb 2 | ||
| 217 | #define reg_pinmux_rw_pb_iop___pb2___width 1 | ||
| 218 | #define reg_pinmux_rw_pb_iop___pb2___bit 2 | ||
| 219 | #define reg_pinmux_rw_pb_iop___pb3___lsb 3 | ||
| 220 | #define reg_pinmux_rw_pb_iop___pb3___width 1 | ||
| 221 | #define reg_pinmux_rw_pb_iop___pb3___bit 3 | ||
| 222 | #define reg_pinmux_rw_pb_iop___pb4___lsb 4 | ||
| 223 | #define reg_pinmux_rw_pb_iop___pb4___width 1 | ||
| 224 | #define reg_pinmux_rw_pb_iop___pb4___bit 4 | ||
| 225 | #define reg_pinmux_rw_pb_iop___pb5___lsb 5 | ||
| 226 | #define reg_pinmux_rw_pb_iop___pb5___width 1 | ||
| 227 | #define reg_pinmux_rw_pb_iop___pb5___bit 5 | ||
| 228 | #define reg_pinmux_rw_pb_iop___pb6___lsb 6 | ||
| 229 | #define reg_pinmux_rw_pb_iop___pb6___width 1 | ||
| 230 | #define reg_pinmux_rw_pb_iop___pb6___bit 6 | ||
| 231 | #define reg_pinmux_rw_pb_iop___pb7___lsb 7 | ||
| 232 | #define reg_pinmux_rw_pb_iop___pb7___width 1 | ||
| 233 | #define reg_pinmux_rw_pb_iop___pb7___bit 7 | ||
| 234 | #define reg_pinmux_rw_pb_iop___pb8___lsb 8 | ||
| 235 | #define reg_pinmux_rw_pb_iop___pb8___width 1 | ||
| 236 | #define reg_pinmux_rw_pb_iop___pb8___bit 8 | ||
| 237 | #define reg_pinmux_rw_pb_iop___pb9___lsb 9 | ||
| 238 | #define reg_pinmux_rw_pb_iop___pb9___width 1 | ||
| 239 | #define reg_pinmux_rw_pb_iop___pb9___bit 9 | ||
| 240 | #define reg_pinmux_rw_pb_iop___pb10___lsb 10 | ||
| 241 | #define reg_pinmux_rw_pb_iop___pb10___width 1 | ||
| 242 | #define reg_pinmux_rw_pb_iop___pb10___bit 10 | ||
| 243 | #define reg_pinmux_rw_pb_iop___pb11___lsb 11 | ||
| 244 | #define reg_pinmux_rw_pb_iop___pb11___width 1 | ||
| 245 | #define reg_pinmux_rw_pb_iop___pb11___bit 11 | ||
| 246 | #define reg_pinmux_rw_pb_iop___pb12___lsb 12 | ||
| 247 | #define reg_pinmux_rw_pb_iop___pb12___width 1 | ||
| 248 | #define reg_pinmux_rw_pb_iop___pb12___bit 12 | ||
| 249 | #define reg_pinmux_rw_pb_iop___pb13___lsb 13 | ||
| 250 | #define reg_pinmux_rw_pb_iop___pb13___width 1 | ||
| 251 | #define reg_pinmux_rw_pb_iop___pb13___bit 13 | ||
| 252 | #define reg_pinmux_rw_pb_iop___pb14___lsb 14 | ||
| 253 | #define reg_pinmux_rw_pb_iop___pb14___width 1 | ||
| 254 | #define reg_pinmux_rw_pb_iop___pb14___bit 14 | ||
| 255 | #define reg_pinmux_rw_pb_iop___pb15___lsb 15 | ||
| 256 | #define reg_pinmux_rw_pb_iop___pb15___width 1 | ||
| 257 | #define reg_pinmux_rw_pb_iop___pb15___bit 15 | ||
| 258 | #define reg_pinmux_rw_pb_iop___pb16___lsb 16 | ||
| 259 | #define reg_pinmux_rw_pb_iop___pb16___width 1 | ||
| 260 | #define reg_pinmux_rw_pb_iop___pb16___bit 16 | ||
| 261 | #define reg_pinmux_rw_pb_iop___pb17___lsb 17 | ||
| 262 | #define reg_pinmux_rw_pb_iop___pb17___width 1 | ||
| 263 | #define reg_pinmux_rw_pb_iop___pb17___bit 17 | ||
| 264 | #define reg_pinmux_rw_pb_iop_offset 12 | ||
| 265 | |||
| 266 | /* Register rw_pc_gio, scope pinmux, type rw */ | ||
| 267 | #define reg_pinmux_rw_pc_gio___pc0___lsb 0 | ||
| 268 | #define reg_pinmux_rw_pc_gio___pc0___width 1 | ||
| 269 | #define reg_pinmux_rw_pc_gio___pc0___bit 0 | ||
| 270 | #define reg_pinmux_rw_pc_gio___pc1___lsb 1 | ||
| 271 | #define reg_pinmux_rw_pc_gio___pc1___width 1 | ||
| 272 | #define reg_pinmux_rw_pc_gio___pc1___bit 1 | ||
| 273 | #define reg_pinmux_rw_pc_gio___pc2___lsb 2 | ||
| 274 | #define reg_pinmux_rw_pc_gio___pc2___width 1 | ||
| 275 | #define reg_pinmux_rw_pc_gio___pc2___bit 2 | ||
| 276 | #define reg_pinmux_rw_pc_gio___pc3___lsb 3 | ||
| 277 | #define reg_pinmux_rw_pc_gio___pc3___width 1 | ||
| 278 | #define reg_pinmux_rw_pc_gio___pc3___bit 3 | ||
| 279 | #define reg_pinmux_rw_pc_gio___pc4___lsb 4 | ||
| 280 | #define reg_pinmux_rw_pc_gio___pc4___width 1 | ||
| 281 | #define reg_pinmux_rw_pc_gio___pc4___bit 4 | ||
| 282 | #define reg_pinmux_rw_pc_gio___pc5___lsb 5 | ||
| 283 | #define reg_pinmux_rw_pc_gio___pc5___width 1 | ||
| 284 | #define reg_pinmux_rw_pc_gio___pc5___bit 5 | ||
| 285 | #define reg_pinmux_rw_pc_gio___pc6___lsb 6 | ||
| 286 | #define reg_pinmux_rw_pc_gio___pc6___width 1 | ||
| 287 | #define reg_pinmux_rw_pc_gio___pc6___bit 6 | ||
| 288 | #define reg_pinmux_rw_pc_gio___pc7___lsb 7 | ||
| 289 | #define reg_pinmux_rw_pc_gio___pc7___width 1 | ||
| 290 | #define reg_pinmux_rw_pc_gio___pc7___bit 7 | ||
| 291 | #define reg_pinmux_rw_pc_gio___pc8___lsb 8 | ||
| 292 | #define reg_pinmux_rw_pc_gio___pc8___width 1 | ||
| 293 | #define reg_pinmux_rw_pc_gio___pc8___bit 8 | ||
| 294 | #define reg_pinmux_rw_pc_gio___pc9___lsb 9 | ||
| 295 | #define reg_pinmux_rw_pc_gio___pc9___width 1 | ||
| 296 | #define reg_pinmux_rw_pc_gio___pc9___bit 9 | ||
| 297 | #define reg_pinmux_rw_pc_gio___pc10___lsb 10 | ||
| 298 | #define reg_pinmux_rw_pc_gio___pc10___width 1 | ||
| 299 | #define reg_pinmux_rw_pc_gio___pc10___bit 10 | ||
| 300 | #define reg_pinmux_rw_pc_gio___pc11___lsb 11 | ||
| 301 | #define reg_pinmux_rw_pc_gio___pc11___width 1 | ||
| 302 | #define reg_pinmux_rw_pc_gio___pc11___bit 11 | ||
| 303 | #define reg_pinmux_rw_pc_gio___pc12___lsb 12 | ||
| 304 | #define reg_pinmux_rw_pc_gio___pc12___width 1 | ||
| 305 | #define reg_pinmux_rw_pc_gio___pc12___bit 12 | ||
| 306 | #define reg_pinmux_rw_pc_gio___pc13___lsb 13 | ||
| 307 | #define reg_pinmux_rw_pc_gio___pc13___width 1 | ||
| 308 | #define reg_pinmux_rw_pc_gio___pc13___bit 13 | ||
| 309 | #define reg_pinmux_rw_pc_gio___pc14___lsb 14 | ||
| 310 | #define reg_pinmux_rw_pc_gio___pc14___width 1 | ||
| 311 | #define reg_pinmux_rw_pc_gio___pc14___bit 14 | ||
| 312 | #define reg_pinmux_rw_pc_gio___pc15___lsb 15 | ||
| 313 | #define reg_pinmux_rw_pc_gio___pc15___width 1 | ||
| 314 | #define reg_pinmux_rw_pc_gio___pc15___bit 15 | ||
| 315 | #define reg_pinmux_rw_pc_gio___pc16___lsb 16 | ||
| 316 | #define reg_pinmux_rw_pc_gio___pc16___width 1 | ||
| 317 | #define reg_pinmux_rw_pc_gio___pc16___bit 16 | ||
| 318 | #define reg_pinmux_rw_pc_gio___pc17___lsb 17 | ||
| 319 | #define reg_pinmux_rw_pc_gio___pc17___width 1 | ||
| 320 | #define reg_pinmux_rw_pc_gio___pc17___bit 17 | ||
| 321 | #define reg_pinmux_rw_pc_gio_offset 16 | ||
| 322 | |||
| 323 | /* Register rw_pc_iop, scope pinmux, type rw */ | ||
| 324 | #define reg_pinmux_rw_pc_iop___pc0___lsb 0 | ||
| 325 | #define reg_pinmux_rw_pc_iop___pc0___width 1 | ||
| 326 | #define reg_pinmux_rw_pc_iop___pc0___bit 0 | ||
| 327 | #define reg_pinmux_rw_pc_iop___pc1___lsb 1 | ||
| 328 | #define reg_pinmux_rw_pc_iop___pc1___width 1 | ||
| 329 | #define reg_pinmux_rw_pc_iop___pc1___bit 1 | ||
| 330 | #define reg_pinmux_rw_pc_iop___pc2___lsb 2 | ||
| 331 | #define reg_pinmux_rw_pc_iop___pc2___width 1 | ||
| 332 | #define reg_pinmux_rw_pc_iop___pc2___bit 2 | ||
| 333 | #define reg_pinmux_rw_pc_iop___pc3___lsb 3 | ||
| 334 | #define reg_pinmux_rw_pc_iop___pc3___width 1 | ||
| 335 | #define reg_pinmux_rw_pc_iop___pc3___bit 3 | ||
| 336 | #define reg_pinmux_rw_pc_iop___pc4___lsb 4 | ||
| 337 | #define reg_pinmux_rw_pc_iop___pc4___width 1 | ||
| 338 | #define reg_pinmux_rw_pc_iop___pc4___bit 4 | ||
| 339 | #define reg_pinmux_rw_pc_iop___pc5___lsb 5 | ||
| 340 | #define reg_pinmux_rw_pc_iop___pc5___width 1 | ||
| 341 | #define reg_pinmux_rw_pc_iop___pc5___bit 5 | ||
| 342 | #define reg_pinmux_rw_pc_iop___pc6___lsb 6 | ||
| 343 | #define reg_pinmux_rw_pc_iop___pc6___width 1 | ||
| 344 | #define reg_pinmux_rw_pc_iop___pc6___bit 6 | ||
| 345 | #define reg_pinmux_rw_pc_iop___pc7___lsb 7 | ||
| 346 | #define reg_pinmux_rw_pc_iop___pc7___width 1 | ||
| 347 | #define reg_pinmux_rw_pc_iop___pc7___bit 7 | ||
| 348 | #define reg_pinmux_rw_pc_iop___pc8___lsb 8 | ||
| 349 | #define reg_pinmux_rw_pc_iop___pc8___width 1 | ||
| 350 | #define reg_pinmux_rw_pc_iop___pc8___bit 8 | ||
| 351 | #define reg_pinmux_rw_pc_iop___pc9___lsb 9 | ||
| 352 | #define reg_pinmux_rw_pc_iop___pc9___width 1 | ||
| 353 | #define reg_pinmux_rw_pc_iop___pc9___bit 9 | ||
| 354 | #define reg_pinmux_rw_pc_iop___pc10___lsb 10 | ||
| 355 | #define reg_pinmux_rw_pc_iop___pc10___width 1 | ||
| 356 | #define reg_pinmux_rw_pc_iop___pc10___bit 10 | ||
| 357 | #define reg_pinmux_rw_pc_iop___pc11___lsb 11 | ||
| 358 | #define reg_pinmux_rw_pc_iop___pc11___width 1 | ||
| 359 | #define reg_pinmux_rw_pc_iop___pc11___bit 11 | ||
| 360 | #define reg_pinmux_rw_pc_iop___pc12___lsb 12 | ||
| 361 | #define reg_pinmux_rw_pc_iop___pc12___width 1 | ||
| 362 | #define reg_pinmux_rw_pc_iop___pc12___bit 12 | ||
| 363 | #define reg_pinmux_rw_pc_iop___pc13___lsb 13 | ||
| 364 | #define reg_pinmux_rw_pc_iop___pc13___width 1 | ||
| 365 | #define reg_pinmux_rw_pc_iop___pc13___bit 13 | ||
| 366 | #define reg_pinmux_rw_pc_iop___pc14___lsb 14 | ||
| 367 | #define reg_pinmux_rw_pc_iop___pc14___width 1 | ||
| 368 | #define reg_pinmux_rw_pc_iop___pc14___bit 14 | ||
| 369 | #define reg_pinmux_rw_pc_iop___pc15___lsb 15 | ||
| 370 | #define reg_pinmux_rw_pc_iop___pc15___width 1 | ||
| 371 | #define reg_pinmux_rw_pc_iop___pc15___bit 15 | ||
| 372 | #define reg_pinmux_rw_pc_iop___pc16___lsb 16 | ||
| 373 | #define reg_pinmux_rw_pc_iop___pc16___width 1 | ||
| 374 | #define reg_pinmux_rw_pc_iop___pc16___bit 16 | ||
| 375 | #define reg_pinmux_rw_pc_iop___pc17___lsb 17 | ||
| 376 | #define reg_pinmux_rw_pc_iop___pc17___width 1 | ||
| 377 | #define reg_pinmux_rw_pc_iop___pc17___bit 17 | ||
| 378 | #define reg_pinmux_rw_pc_iop_offset 20 | ||
| 379 | |||
| 380 | /* Register rw_pd_gio, scope pinmux, type rw */ | ||
| 381 | #define reg_pinmux_rw_pd_gio___pd0___lsb 0 | ||
| 382 | #define reg_pinmux_rw_pd_gio___pd0___width 1 | ||
| 383 | #define reg_pinmux_rw_pd_gio___pd0___bit 0 | ||
| 384 | #define reg_pinmux_rw_pd_gio___pd1___lsb 1 | ||
| 385 | #define reg_pinmux_rw_pd_gio___pd1___width 1 | ||
| 386 | #define reg_pinmux_rw_pd_gio___pd1___bit 1 | ||
| 387 | #define reg_pinmux_rw_pd_gio___pd2___lsb 2 | ||
| 388 | #define reg_pinmux_rw_pd_gio___pd2___width 1 | ||
| 389 | #define reg_pinmux_rw_pd_gio___pd2___bit 2 | ||
| 390 | #define reg_pinmux_rw_pd_gio___pd3___lsb 3 | ||
| 391 | #define reg_pinmux_rw_pd_gio___pd3___width 1 | ||
| 392 | #define reg_pinmux_rw_pd_gio___pd3___bit 3 | ||
| 393 | #define reg_pinmux_rw_pd_gio___pd4___lsb 4 | ||
| 394 | #define reg_pinmux_rw_pd_gio___pd4___width 1 | ||
| 395 | #define reg_pinmux_rw_pd_gio___pd4___bit 4 | ||
| 396 | #define reg_pinmux_rw_pd_gio___pd5___lsb 5 | ||
| 397 | #define reg_pinmux_rw_pd_gio___pd5___width 1 | ||
| 398 | #define reg_pinmux_rw_pd_gio___pd5___bit 5 | ||
| 399 | #define reg_pinmux_rw_pd_gio___pd6___lsb 6 | ||
| 400 | #define reg_pinmux_rw_pd_gio___pd6___width 1 | ||
| 401 | #define reg_pinmux_rw_pd_gio___pd6___bit 6 | ||
| 402 | #define reg_pinmux_rw_pd_gio___pd7___lsb 7 | ||
| 403 | #define reg_pinmux_rw_pd_gio___pd7___width 1 | ||
| 404 | #define reg_pinmux_rw_pd_gio___pd7___bit 7 | ||
| 405 | #define reg_pinmux_rw_pd_gio___pd8___lsb 8 | ||
| 406 | #define reg_pinmux_rw_pd_gio___pd8___width 1 | ||
| 407 | #define reg_pinmux_rw_pd_gio___pd8___bit 8 | ||
| 408 | #define reg_pinmux_rw_pd_gio___pd9___lsb 9 | ||
| 409 | #define reg_pinmux_rw_pd_gio___pd9___width 1 | ||
| 410 | #define reg_pinmux_rw_pd_gio___pd9___bit 9 | ||
| 411 | #define reg_pinmux_rw_pd_gio___pd10___lsb 10 | ||
| 412 | #define reg_pinmux_rw_pd_gio___pd10___width 1 | ||
| 413 | #define reg_pinmux_rw_pd_gio___pd10___bit 10 | ||
| 414 | #define reg_pinmux_rw_pd_gio___pd11___lsb 11 | ||
| 415 | #define reg_pinmux_rw_pd_gio___pd11___width 1 | ||
| 416 | #define reg_pinmux_rw_pd_gio___pd11___bit 11 | ||
| 417 | #define reg_pinmux_rw_pd_gio___pd12___lsb 12 | ||
| 418 | #define reg_pinmux_rw_pd_gio___pd12___width 1 | ||
| 419 | #define reg_pinmux_rw_pd_gio___pd12___bit 12 | ||
| 420 | #define reg_pinmux_rw_pd_gio___pd13___lsb 13 | ||
| 421 | #define reg_pinmux_rw_pd_gio___pd13___width 1 | ||
| 422 | #define reg_pinmux_rw_pd_gio___pd13___bit 13 | ||
| 423 | #define reg_pinmux_rw_pd_gio___pd14___lsb 14 | ||
| 424 | #define reg_pinmux_rw_pd_gio___pd14___width 1 | ||
| 425 | #define reg_pinmux_rw_pd_gio___pd14___bit 14 | ||
| 426 | #define reg_pinmux_rw_pd_gio___pd15___lsb 15 | ||
| 427 | #define reg_pinmux_rw_pd_gio___pd15___width 1 | ||
| 428 | #define reg_pinmux_rw_pd_gio___pd15___bit 15 | ||
| 429 | #define reg_pinmux_rw_pd_gio___pd16___lsb 16 | ||
| 430 | #define reg_pinmux_rw_pd_gio___pd16___width 1 | ||
| 431 | #define reg_pinmux_rw_pd_gio___pd16___bit 16 | ||
| 432 | #define reg_pinmux_rw_pd_gio___pd17___lsb 17 | ||
| 433 | #define reg_pinmux_rw_pd_gio___pd17___width 1 | ||
| 434 | #define reg_pinmux_rw_pd_gio___pd17___bit 17 | ||
| 435 | #define reg_pinmux_rw_pd_gio_offset 24 | ||
| 436 | |||
| 437 | /* Register rw_pd_iop, scope pinmux, type rw */ | ||
| 438 | #define reg_pinmux_rw_pd_iop___pd0___lsb 0 | ||
| 439 | #define reg_pinmux_rw_pd_iop___pd0___width 1 | ||
| 440 | #define reg_pinmux_rw_pd_iop___pd0___bit 0 | ||
| 441 | #define reg_pinmux_rw_pd_iop___pd1___lsb 1 | ||
| 442 | #define reg_pinmux_rw_pd_iop___pd1___width 1 | ||
| 443 | #define reg_pinmux_rw_pd_iop___pd1___bit 1 | ||
| 444 | #define reg_pinmux_rw_pd_iop___pd2___lsb 2 | ||
| 445 | #define reg_pinmux_rw_pd_iop___pd2___width 1 | ||
| 446 | #define reg_pinmux_rw_pd_iop___pd2___bit 2 | ||
| 447 | #define reg_pinmux_rw_pd_iop___pd3___lsb 3 | ||
| 448 | #define reg_pinmux_rw_pd_iop___pd3___width 1 | ||
| 449 | #define reg_pinmux_rw_pd_iop___pd3___bit 3 | ||
| 450 | #define reg_pinmux_rw_pd_iop___pd4___lsb 4 | ||
| 451 | #define reg_pinmux_rw_pd_iop___pd4___width 1 | ||
| 452 | #define reg_pinmux_rw_pd_iop___pd4___bit 4 | ||
| 453 | #define reg_pinmux_rw_pd_iop___pd5___lsb 5 | ||
| 454 | #define reg_pinmux_rw_pd_iop___pd5___width 1 | ||
| 455 | #define reg_pinmux_rw_pd_iop___pd5___bit 5 | ||
| 456 | #define reg_pinmux_rw_pd_iop___pd6___lsb 6 | ||
| 457 | #define reg_pinmux_rw_pd_iop___pd6___width 1 | ||
| 458 | #define reg_pinmux_rw_pd_iop___pd6___bit 6 | ||
| 459 | #define reg_pinmux_rw_pd_iop___pd7___lsb 7 | ||
| 460 | #define reg_pinmux_rw_pd_iop___pd7___width 1 | ||
| 461 | #define reg_pinmux_rw_pd_iop___pd7___bit 7 | ||
| 462 | #define reg_pinmux_rw_pd_iop___pd8___lsb 8 | ||
| 463 | #define reg_pinmux_rw_pd_iop___pd8___width 1 | ||
| 464 | #define reg_pinmux_rw_pd_iop___pd8___bit 8 | ||
| 465 | #define reg_pinmux_rw_pd_iop___pd9___lsb 9 | ||
| 466 | #define reg_pinmux_rw_pd_iop___pd9___width 1 | ||
| 467 | #define reg_pinmux_rw_pd_iop___pd9___bit 9 | ||
| 468 | #define reg_pinmux_rw_pd_iop___pd10___lsb 10 | ||
| 469 | #define reg_pinmux_rw_pd_iop___pd10___width 1 | ||
| 470 | #define reg_pinmux_rw_pd_iop___pd10___bit 10 | ||
| 471 | #define reg_pinmux_rw_pd_iop___pd11___lsb 11 | ||
| 472 | #define reg_pinmux_rw_pd_iop___pd11___width 1 | ||
| 473 | #define reg_pinmux_rw_pd_iop___pd11___bit 11 | ||
| 474 | #define reg_pinmux_rw_pd_iop___pd12___lsb 12 | ||
| 475 | #define reg_pinmux_rw_pd_iop___pd12___width 1 | ||
| 476 | #define reg_pinmux_rw_pd_iop___pd12___bit 12 | ||
| 477 | #define reg_pinmux_rw_pd_iop___pd13___lsb 13 | ||
| 478 | #define reg_pinmux_rw_pd_iop___pd13___width 1 | ||
| 479 | #define reg_pinmux_rw_pd_iop___pd13___bit 13 | ||
| 480 | #define reg_pinmux_rw_pd_iop___pd14___lsb 14 | ||
| 481 | #define reg_pinmux_rw_pd_iop___pd14___width 1 | ||
| 482 | #define reg_pinmux_rw_pd_iop___pd14___bit 14 | ||
| 483 | #define reg_pinmux_rw_pd_iop___pd15___lsb 15 | ||
| 484 | #define reg_pinmux_rw_pd_iop___pd15___width 1 | ||
| 485 | #define reg_pinmux_rw_pd_iop___pd15___bit 15 | ||
| 486 | #define reg_pinmux_rw_pd_iop___pd16___lsb 16 | ||
| 487 | #define reg_pinmux_rw_pd_iop___pd16___width 1 | ||
| 488 | #define reg_pinmux_rw_pd_iop___pd16___bit 16 | ||
| 489 | #define reg_pinmux_rw_pd_iop___pd17___lsb 17 | ||
| 490 | #define reg_pinmux_rw_pd_iop___pd17___width 1 | ||
| 491 | #define reg_pinmux_rw_pd_iop___pd17___bit 17 | ||
| 492 | #define reg_pinmux_rw_pd_iop_offset 28 | ||
| 493 | |||
| 494 | /* Register rw_pe_gio, scope pinmux, type rw */ | ||
| 495 | #define reg_pinmux_rw_pe_gio___pe0___lsb 0 | ||
| 496 | #define reg_pinmux_rw_pe_gio___pe0___width 1 | ||
| 497 | #define reg_pinmux_rw_pe_gio___pe0___bit 0 | ||
| 498 | #define reg_pinmux_rw_pe_gio___pe1___lsb 1 | ||
| 499 | #define reg_pinmux_rw_pe_gio___pe1___width 1 | ||
| 500 | #define reg_pinmux_rw_pe_gio___pe1___bit 1 | ||
| 501 | #define reg_pinmux_rw_pe_gio___pe2___lsb 2 | ||
| 502 | #define reg_pinmux_rw_pe_gio___pe2___width 1 | ||
| 503 | #define reg_pinmux_rw_pe_gio___pe2___bit 2 | ||
| 504 | #define reg_pinmux_rw_pe_gio___pe3___lsb 3 | ||
| 505 | #define reg_pinmux_rw_pe_gio___pe3___width 1 | ||
| 506 | #define reg_pinmux_rw_pe_gio___pe3___bit 3 | ||
| 507 | #define reg_pinmux_rw_pe_gio___pe4___lsb 4 | ||
| 508 | #define reg_pinmux_rw_pe_gio___pe4___width 1 | ||
| 509 | #define reg_pinmux_rw_pe_gio___pe4___bit 4 | ||
| 510 | #define reg_pinmux_rw_pe_gio___pe5___lsb 5 | ||
| 511 | #define reg_pinmux_rw_pe_gio___pe5___width 1 | ||
| 512 | #define reg_pinmux_rw_pe_gio___pe5___bit 5 | ||
| 513 | #define reg_pinmux_rw_pe_gio___pe6___lsb 6 | ||
| 514 | #define reg_pinmux_rw_pe_gio___pe6___width 1 | ||
| 515 | #define reg_pinmux_rw_pe_gio___pe6___bit 6 | ||
| 516 | #define reg_pinmux_rw_pe_gio___pe7___lsb 7 | ||
| 517 | #define reg_pinmux_rw_pe_gio___pe7___width 1 | ||
| 518 | #define reg_pinmux_rw_pe_gio___pe7___bit 7 | ||
| 519 | #define reg_pinmux_rw_pe_gio___pe8___lsb 8 | ||
| 520 | #define reg_pinmux_rw_pe_gio___pe8___width 1 | ||
| 521 | #define reg_pinmux_rw_pe_gio___pe8___bit 8 | ||
| 522 | #define reg_pinmux_rw_pe_gio___pe9___lsb 9 | ||
| 523 | #define reg_pinmux_rw_pe_gio___pe9___width 1 | ||
| 524 | #define reg_pinmux_rw_pe_gio___pe9___bit 9 | ||
| 525 | #define reg_pinmux_rw_pe_gio___pe10___lsb 10 | ||
| 526 | #define reg_pinmux_rw_pe_gio___pe10___width 1 | ||
| 527 | #define reg_pinmux_rw_pe_gio___pe10___bit 10 | ||
| 528 | #define reg_pinmux_rw_pe_gio___pe11___lsb 11 | ||
| 529 | #define reg_pinmux_rw_pe_gio___pe11___width 1 | ||
| 530 | #define reg_pinmux_rw_pe_gio___pe11___bit 11 | ||
| 531 | #define reg_pinmux_rw_pe_gio___pe12___lsb 12 | ||
| 532 | #define reg_pinmux_rw_pe_gio___pe12___width 1 | ||
| 533 | #define reg_pinmux_rw_pe_gio___pe12___bit 12 | ||
| 534 | #define reg_pinmux_rw_pe_gio___pe13___lsb 13 | ||
| 535 | #define reg_pinmux_rw_pe_gio___pe13___width 1 | ||
| 536 | #define reg_pinmux_rw_pe_gio___pe13___bit 13 | ||
| 537 | #define reg_pinmux_rw_pe_gio___pe14___lsb 14 | ||
| 538 | #define reg_pinmux_rw_pe_gio___pe14___width 1 | ||
| 539 | #define reg_pinmux_rw_pe_gio___pe14___bit 14 | ||
| 540 | #define reg_pinmux_rw_pe_gio___pe15___lsb 15 | ||
| 541 | #define reg_pinmux_rw_pe_gio___pe15___width 1 | ||
| 542 | #define reg_pinmux_rw_pe_gio___pe15___bit 15 | ||
| 543 | #define reg_pinmux_rw_pe_gio___pe16___lsb 16 | ||
| 544 | #define reg_pinmux_rw_pe_gio___pe16___width 1 | ||
| 545 | #define reg_pinmux_rw_pe_gio___pe16___bit 16 | ||
| 546 | #define reg_pinmux_rw_pe_gio___pe17___lsb 17 | ||
| 547 | #define reg_pinmux_rw_pe_gio___pe17___width 1 | ||
| 548 | #define reg_pinmux_rw_pe_gio___pe17___bit 17 | ||
| 549 | #define reg_pinmux_rw_pe_gio_offset 32 | ||
| 550 | |||
| 551 | /* Register rw_pe_iop, scope pinmux, type rw */ | ||
| 552 | #define reg_pinmux_rw_pe_iop___pe0___lsb 0 | ||
| 553 | #define reg_pinmux_rw_pe_iop___pe0___width 1 | ||
| 554 | #define reg_pinmux_rw_pe_iop___pe0___bit 0 | ||
| 555 | #define reg_pinmux_rw_pe_iop___pe1___lsb 1 | ||
| 556 | #define reg_pinmux_rw_pe_iop___pe1___width 1 | ||
| 557 | #define reg_pinmux_rw_pe_iop___pe1___bit 1 | ||
| 558 | #define reg_pinmux_rw_pe_iop___pe2___lsb 2 | ||
| 559 | #define reg_pinmux_rw_pe_iop___pe2___width 1 | ||
| 560 | #define reg_pinmux_rw_pe_iop___pe2___bit 2 | ||
| 561 | #define reg_pinmux_rw_pe_iop___pe3___lsb 3 | ||
| 562 | #define reg_pinmux_rw_pe_iop___pe3___width 1 | ||
| 563 | #define reg_pinmux_rw_pe_iop___pe3___bit 3 | ||
| 564 | #define reg_pinmux_rw_pe_iop___pe4___lsb 4 | ||
| 565 | #define reg_pinmux_rw_pe_iop___pe4___width 1 | ||
| 566 | #define reg_pinmux_rw_pe_iop___pe4___bit 4 | ||
| 567 | #define reg_pinmux_rw_pe_iop___pe5___lsb 5 | ||
| 568 | #define reg_pinmux_rw_pe_iop___pe5___width 1 | ||
| 569 | #define reg_pinmux_rw_pe_iop___pe5___bit 5 | ||
| 570 | #define reg_pinmux_rw_pe_iop___pe6___lsb 6 | ||
| 571 | #define reg_pinmux_rw_pe_iop___pe6___width 1 | ||
| 572 | #define reg_pinmux_rw_pe_iop___pe6___bit 6 | ||
| 573 | #define reg_pinmux_rw_pe_iop___pe7___lsb 7 | ||
| 574 | #define reg_pinmux_rw_pe_iop___pe7___width 1 | ||
| 575 | #define reg_pinmux_rw_pe_iop___pe7___bit 7 | ||
| 576 | #define reg_pinmux_rw_pe_iop___pe8___lsb 8 | ||
| 577 | #define reg_pinmux_rw_pe_iop___pe8___width 1 | ||
| 578 | #define reg_pinmux_rw_pe_iop___pe8___bit 8 | ||
| 579 | #define reg_pinmux_rw_pe_iop___pe9___lsb 9 | ||
| 580 | #define reg_pinmux_rw_pe_iop___pe9___width 1 | ||
| 581 | #define reg_pinmux_rw_pe_iop___pe9___bit 9 | ||
| 582 | #define reg_pinmux_rw_pe_iop___pe10___lsb 10 | ||
| 583 | #define reg_pinmux_rw_pe_iop___pe10___width 1 | ||
| 584 | #define reg_pinmux_rw_pe_iop___pe10___bit 10 | ||
| 585 | #define reg_pinmux_rw_pe_iop___pe11___lsb 11 | ||
| 586 | #define reg_pinmux_rw_pe_iop___pe11___width 1 | ||
| 587 | #define reg_pinmux_rw_pe_iop___pe11___bit 11 | ||
| 588 | #define reg_pinmux_rw_pe_iop___pe12___lsb 12 | ||
| 589 | #define reg_pinmux_rw_pe_iop___pe12___width 1 | ||
| 590 | #define reg_pinmux_rw_pe_iop___pe12___bit 12 | ||
| 591 | #define reg_pinmux_rw_pe_iop___pe13___lsb 13 | ||
| 592 | #define reg_pinmux_rw_pe_iop___pe13___width 1 | ||
| 593 | #define reg_pinmux_rw_pe_iop___pe13___bit 13 | ||
| 594 | #define reg_pinmux_rw_pe_iop___pe14___lsb 14 | ||
| 595 | #define reg_pinmux_rw_pe_iop___pe14___width 1 | ||
| 596 | #define reg_pinmux_rw_pe_iop___pe14___bit 14 | ||
| 597 | #define reg_pinmux_rw_pe_iop___pe15___lsb 15 | ||
| 598 | #define reg_pinmux_rw_pe_iop___pe15___width 1 | ||
| 599 | #define reg_pinmux_rw_pe_iop___pe15___bit 15 | ||
| 600 | #define reg_pinmux_rw_pe_iop___pe16___lsb 16 | ||
| 601 | #define reg_pinmux_rw_pe_iop___pe16___width 1 | ||
| 602 | #define reg_pinmux_rw_pe_iop___pe16___bit 16 | ||
| 603 | #define reg_pinmux_rw_pe_iop___pe17___lsb 17 | ||
| 604 | #define reg_pinmux_rw_pe_iop___pe17___width 1 | ||
| 605 | #define reg_pinmux_rw_pe_iop___pe17___bit 17 | ||
| 606 | #define reg_pinmux_rw_pe_iop_offset 36 | ||
| 607 | |||
| 608 | /* Register rw_usb_phy, scope pinmux, type rw */ | ||
| 609 | #define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 | ||
| 610 | #define reg_pinmux_rw_usb_phy___en_usb0___width 1 | ||
| 611 | #define reg_pinmux_rw_usb_phy___en_usb0___bit 0 | ||
| 612 | #define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 | ||
| 613 | #define reg_pinmux_rw_usb_phy___en_usb1___width 1 | ||
| 614 | #define reg_pinmux_rw_usb_phy___en_usb1___bit 1 | ||
| 615 | #define reg_pinmux_rw_usb_phy_offset 40 | ||
| 616 | |||
| 617 | |||
| 618 | /* Constants */ | ||
| 619 | #define regk_pinmux_no 0x00000000 | ||
| 620 | #define regk_pinmux_rw_hwprot_default 0x00000000 | ||
| 621 | #define regk_pinmux_rw_pa_default 0x00000000 | ||
| 622 | #define regk_pinmux_rw_pb_gio_default 0x00000000 | ||
| 623 | #define regk_pinmux_rw_pb_iop_default 0x00000000 | ||
| 624 | #define regk_pinmux_rw_pc_gio_default 0x00000000 | ||
| 625 | #define regk_pinmux_rw_pc_iop_default 0x00000000 | ||
| 626 | #define regk_pinmux_rw_pd_gio_default 0x00000000 | ||
| 627 | #define regk_pinmux_rw_pd_iop_default 0x00000000 | ||
| 628 | #define regk_pinmux_rw_pe_gio_default 0x00000000 | ||
| 629 | #define regk_pinmux_rw_pe_iop_default 0x00000000 | ||
| 630 | #define regk_pinmux_rw_usb_phy_default 0x00000000 | ||
| 631 | #define regk_pinmux_yes 0x00000001 | ||
| 632 | #endif /* __pinmux_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 87517aebd2cb..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | #ifndef __reg_map_h | ||
| 2 | #define __reg_map_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../mod/fakereg.rmap | ||
| 7 | * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp | ||
| 8 | * last modified: Wed Feb 11 20:53:25 2004 | ||
| 9 | * file: ../../rtl/global.rmap | ||
| 10 | * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp | ||
| 11 | * last modified: Mon Aug 18 17:08:23 2003 | ||
| 12 | * file: ../../mod/modreg.rmap | ||
| 13 | * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp | ||
| 14 | * last modified: Fri Feb 20 16:40:04 2004 | ||
| 15 | * | ||
| 16 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap | ||
| 17 | * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 18 | * Any changes here will be lost. | ||
| 19 | * | ||
| 20 | * -*- buffer-read-only: t -*- | ||
| 21 | */ | ||
| 22 | #define regi_artpec_mod 0xb7044000 | ||
| 23 | #define regi_ata 0xb0032000 | ||
| 24 | #define regi_ata_mod 0xb7006000 | ||
| 25 | #define regi_barber 0xb701a000 | ||
| 26 | #define regi_bif_core 0xb0014000 | ||
| 27 | #define regi_bif_dma 0xb0016000 | ||
| 28 | #define regi_bif_slave 0xb0018000 | ||
| 29 | #define regi_bif_slave_ext 0xac000000 | ||
| 30 | #define regi_bus_master 0xb703c000 | ||
| 31 | #define regi_config 0xb003c000 | ||
| 32 | #define regi_dma0 0xb0000000 | ||
| 33 | #define regi_dma1 0xb0002000 | ||
| 34 | #define regi_dma2 0xb0004000 | ||
| 35 | #define regi_dma3 0xb0006000 | ||
| 36 | #define regi_dma4 0xb0008000 | ||
| 37 | #define regi_dma5 0xb000a000 | ||
| 38 | #define regi_dma6 0xb000c000 | ||
| 39 | #define regi_dma7 0xb000e000 | ||
| 40 | #define regi_dma8 0xb0010000 | ||
| 41 | #define regi_dma9 0xb0012000 | ||
| 42 | #define regi_eth0 0xb0034000 | ||
| 43 | #define regi_eth1 0xb0036000 | ||
| 44 | #define regi_eth_mod 0xb7004000 | ||
| 45 | #define regi_eth_mod1 0xb701c000 | ||
| 46 | #define regi_eth_strmod 0xb7008000 | ||
| 47 | #define regi_eth_strmod1 0xb7032000 | ||
| 48 | #define regi_ext_dma 0xb703a000 | ||
| 49 | #define regi_ext_mem 0xb7046000 | ||
| 50 | #define regi_gen_io 0xb7016000 | ||
| 51 | #define regi_gio 0xb001a000 | ||
| 52 | #define regi_hook 0xb7000000 | ||
| 53 | #define regi_iop 0xb0020000 | ||
| 54 | #define regi_irq 0xb001c000 | ||
| 55 | #define regi_irq_nmi 0xb701e000 | ||
| 56 | #define regi_marb 0xb003e000 | ||
| 57 | #define regi_marb_bp0 0xb003e240 | ||
| 58 | #define regi_marb_bp1 0xb003e280 | ||
| 59 | #define regi_marb_bp2 0xb003e2c0 | ||
| 60 | #define regi_marb_bp3 0xb003e300 | ||
| 61 | #define regi_nand_mod 0xb7014000 | ||
| 62 | #define regi_p21 0xb002e000 | ||
| 63 | #define regi_p21_mod 0xb7042000 | ||
| 64 | #define regi_pci_mod 0xb7010000 | ||
| 65 | #define regi_pin_test 0xb7018000 | ||
| 66 | #define regi_pinmux 0xb0038000 | ||
| 67 | #define regi_sdram_chk 0xb703e000 | ||
| 68 | #define regi_sdram_mod 0xb7012000 | ||
| 69 | #define regi_ser0 0xb0026000 | ||
| 70 | #define regi_ser1 0xb0028000 | ||
| 71 | #define regi_ser2 0xb002a000 | ||
| 72 | #define regi_ser3 0xb002c000 | ||
| 73 | #define regi_ser_mod0 0xb7020000 | ||
| 74 | #define regi_ser_mod1 0xb7022000 | ||
| 75 | #define regi_ser_mod2 0xb7024000 | ||
| 76 | #define regi_ser_mod3 0xb7026000 | ||
| 77 | #define regi_smif_stat 0xb700e000 | ||
| 78 | #define regi_sser0 0xb0022000 | ||
| 79 | #define regi_sser1 0xb0024000 | ||
| 80 | #define regi_sser_mod0 0xb700a000 | ||
| 81 | #define regi_sser_mod1 0xb700c000 | ||
| 82 | #define regi_strcop 0xb0030000 | ||
| 83 | #define regi_strmux 0xb003a000 | ||
| 84 | #define regi_strmux_tst 0xb7040000 | ||
| 85 | #define regi_tap 0xb7002000 | ||
| 86 | #define regi_timer 0xb001e000 | ||
| 87 | #define regi_timer_mod 0xb7034000 | ||
| 88 | #define regi_trace 0xb0040000 | ||
| 89 | #define regi_usb0 0xb7028000 | ||
| 90 | #define regi_usb1 0xb702a000 | ||
| 91 | #define regi_usb2 0xb702c000 | ||
| 92 | #define regi_usb3 0xb702e000 | ||
| 93 | #define regi_usb_dev 0xb7030000 | ||
| 94 | #define regi_utmi_mod0 0xb7036000 | ||
| 95 | #define regi_utmi_mod1 0xb7038000 | ||
| 96 | #endif /* __reg_map_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index e1197194d5c1..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h +++ /dev/null | |||
| @@ -1,229 +0,0 @@ | |||
| 1 | #ifndef __timer_defs_asm_h | ||
| 2 | #define __timer_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/timer/rtl/timer_regs.r | ||
| 7 | * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:53 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r | ||
| 11 | * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_tmr0_div, scope timer, type rw */ | ||
| 57 | #define reg_timer_rw_tmr0_div_offset 0 | ||
| 58 | |||
| 59 | /* Register r_tmr0_data, scope timer, type r */ | ||
| 60 | #define reg_timer_r_tmr0_data_offset 4 | ||
| 61 | |||
| 62 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | ||
| 63 | #define reg_timer_rw_tmr0_ctrl___op___lsb 0 | ||
| 64 | #define reg_timer_rw_tmr0_ctrl___op___width 2 | ||
| 65 | #define reg_timer_rw_tmr0_ctrl___freq___lsb 2 | ||
| 66 | #define reg_timer_rw_tmr0_ctrl___freq___width 3 | ||
| 67 | #define reg_timer_rw_tmr0_ctrl_offset 8 | ||
| 68 | |||
| 69 | /* Register rw_tmr1_div, scope timer, type rw */ | ||
| 70 | #define reg_timer_rw_tmr1_div_offset 16 | ||
| 71 | |||
| 72 | /* Register r_tmr1_data, scope timer, type r */ | ||
| 73 | #define reg_timer_r_tmr1_data_offset 20 | ||
| 74 | |||
| 75 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | ||
| 76 | #define reg_timer_rw_tmr1_ctrl___op___lsb 0 | ||
| 77 | #define reg_timer_rw_tmr1_ctrl___op___width 2 | ||
| 78 | #define reg_timer_rw_tmr1_ctrl___freq___lsb 2 | ||
| 79 | #define reg_timer_rw_tmr1_ctrl___freq___width 3 | ||
| 80 | #define reg_timer_rw_tmr1_ctrl_offset 24 | ||
| 81 | |||
| 82 | /* Register rs_cnt_data, scope timer, type rs */ | ||
| 83 | #define reg_timer_rs_cnt_data___tmr___lsb 0 | ||
| 84 | #define reg_timer_rs_cnt_data___tmr___width 24 | ||
| 85 | #define reg_timer_rs_cnt_data___cnt___lsb 24 | ||
| 86 | #define reg_timer_rs_cnt_data___cnt___width 8 | ||
| 87 | #define reg_timer_rs_cnt_data_offset 32 | ||
| 88 | |||
| 89 | /* Register r_cnt_data, scope timer, type r */ | ||
| 90 | #define reg_timer_r_cnt_data___tmr___lsb 0 | ||
| 91 | #define reg_timer_r_cnt_data___tmr___width 24 | ||
| 92 | #define reg_timer_r_cnt_data___cnt___lsb 24 | ||
| 93 | #define reg_timer_r_cnt_data___cnt___width 8 | ||
| 94 | #define reg_timer_r_cnt_data_offset 36 | ||
| 95 | |||
| 96 | /* Register rw_cnt_cfg, scope timer, type rw */ | ||
| 97 | #define reg_timer_rw_cnt_cfg___clk___lsb 0 | ||
| 98 | #define reg_timer_rw_cnt_cfg___clk___width 2 | ||
| 99 | #define reg_timer_rw_cnt_cfg_offset 40 | ||
| 100 | |||
| 101 | /* Register rw_trig, scope timer, type rw */ | ||
| 102 | #define reg_timer_rw_trig_offset 48 | ||
| 103 | |||
| 104 | /* Register rw_trig_cfg, scope timer, type rw */ | ||
| 105 | #define reg_timer_rw_trig_cfg___tmr___lsb 0 | ||
| 106 | #define reg_timer_rw_trig_cfg___tmr___width 2 | ||
| 107 | #define reg_timer_rw_trig_cfg_offset 52 | ||
| 108 | |||
| 109 | /* Register r_time, scope timer, type r */ | ||
| 110 | #define reg_timer_r_time_offset 56 | ||
| 111 | |||
| 112 | /* Register rw_out, scope timer, type rw */ | ||
| 113 | #define reg_timer_rw_out___tmr___lsb 0 | ||
| 114 | #define reg_timer_rw_out___tmr___width 2 | ||
| 115 | #define reg_timer_rw_out_offset 60 | ||
| 116 | |||
| 117 | /* Register rw_wd_ctrl, scope timer, type rw */ | ||
| 118 | #define reg_timer_rw_wd_ctrl___cnt___lsb 0 | ||
| 119 | #define reg_timer_rw_wd_ctrl___cnt___width 8 | ||
| 120 | #define reg_timer_rw_wd_ctrl___cmd___lsb 8 | ||
| 121 | #define reg_timer_rw_wd_ctrl___cmd___width 1 | ||
| 122 | #define reg_timer_rw_wd_ctrl___cmd___bit 8 | ||
| 123 | #define reg_timer_rw_wd_ctrl___key___lsb 9 | ||
| 124 | #define reg_timer_rw_wd_ctrl___key___width 7 | ||
| 125 | #define reg_timer_rw_wd_ctrl_offset 64 | ||
| 126 | |||
| 127 | /* Register r_wd_stat, scope timer, type r */ | ||
| 128 | #define reg_timer_r_wd_stat___cnt___lsb 0 | ||
| 129 | #define reg_timer_r_wd_stat___cnt___width 8 | ||
| 130 | #define reg_timer_r_wd_stat___cmd___lsb 8 | ||
| 131 | #define reg_timer_r_wd_stat___cmd___width 1 | ||
| 132 | #define reg_timer_r_wd_stat___cmd___bit 8 | ||
| 133 | #define reg_timer_r_wd_stat_offset 68 | ||
| 134 | |||
| 135 | /* Register rw_intr_mask, scope timer, type rw */ | ||
| 136 | #define reg_timer_rw_intr_mask___tmr0___lsb 0 | ||
| 137 | #define reg_timer_rw_intr_mask___tmr0___width 1 | ||
| 138 | #define reg_timer_rw_intr_mask___tmr0___bit 0 | ||
| 139 | #define reg_timer_rw_intr_mask___tmr1___lsb 1 | ||
| 140 | #define reg_timer_rw_intr_mask___tmr1___width 1 | ||
| 141 | #define reg_timer_rw_intr_mask___tmr1___bit 1 | ||
| 142 | #define reg_timer_rw_intr_mask___cnt___lsb 2 | ||
| 143 | #define reg_timer_rw_intr_mask___cnt___width 1 | ||
| 144 | #define reg_timer_rw_intr_mask___cnt___bit 2 | ||
| 145 | #define reg_timer_rw_intr_mask___trig___lsb 3 | ||
| 146 | #define reg_timer_rw_intr_mask___trig___width 1 | ||
| 147 | #define reg_timer_rw_intr_mask___trig___bit 3 | ||
| 148 | #define reg_timer_rw_intr_mask_offset 72 | ||
| 149 | |||
| 150 | /* Register rw_ack_intr, scope timer, type rw */ | ||
| 151 | #define reg_timer_rw_ack_intr___tmr0___lsb 0 | ||
| 152 | #define reg_timer_rw_ack_intr___tmr0___width 1 | ||
| 153 | #define reg_timer_rw_ack_intr___tmr0___bit 0 | ||
| 154 | #define reg_timer_rw_ack_intr___tmr1___lsb 1 | ||
| 155 | #define reg_timer_rw_ack_intr___tmr1___width 1 | ||
| 156 | #define reg_timer_rw_ack_intr___tmr1___bit 1 | ||
| 157 | #define reg_timer_rw_ack_intr___cnt___lsb 2 | ||
| 158 | #define reg_timer_rw_ack_intr___cnt___width 1 | ||
| 159 | #define reg_timer_rw_ack_intr___cnt___bit 2 | ||
| 160 | #define reg_timer_rw_ack_intr___trig___lsb 3 | ||
| 161 | #define reg_timer_rw_ack_intr___trig___width 1 | ||
| 162 | #define reg_timer_rw_ack_intr___trig___bit 3 | ||
| 163 | #define reg_timer_rw_ack_intr_offset 76 | ||
| 164 | |||
| 165 | /* Register r_intr, scope timer, type r */ | ||
| 166 | #define reg_timer_r_intr___tmr0___lsb 0 | ||
| 167 | #define reg_timer_r_intr___tmr0___width 1 | ||
| 168 | #define reg_timer_r_intr___tmr0___bit 0 | ||
| 169 | #define reg_timer_r_intr___tmr1___lsb 1 | ||
| 170 | #define reg_timer_r_intr___tmr1___width 1 | ||
| 171 | #define reg_timer_r_intr___tmr1___bit 1 | ||
| 172 | #define reg_timer_r_intr___cnt___lsb 2 | ||
| 173 | #define reg_timer_r_intr___cnt___width 1 | ||
| 174 | #define reg_timer_r_intr___cnt___bit 2 | ||
| 175 | #define reg_timer_r_intr___trig___lsb 3 | ||
| 176 | #define reg_timer_r_intr___trig___width 1 | ||
| 177 | #define reg_timer_r_intr___trig___bit 3 | ||
| 178 | #define reg_timer_r_intr_offset 80 | ||
| 179 | |||
| 180 | /* Register r_masked_intr, scope timer, type r */ | ||
| 181 | #define reg_timer_r_masked_intr___tmr0___lsb 0 | ||
| 182 | #define reg_timer_r_masked_intr___tmr0___width 1 | ||
| 183 | #define reg_timer_r_masked_intr___tmr0___bit 0 | ||
| 184 | #define reg_timer_r_masked_intr___tmr1___lsb 1 | ||
| 185 | #define reg_timer_r_masked_intr___tmr1___width 1 | ||
| 186 | #define reg_timer_r_masked_intr___tmr1___bit 1 | ||
| 187 | #define reg_timer_r_masked_intr___cnt___lsb 2 | ||
| 188 | #define reg_timer_r_masked_intr___cnt___width 1 | ||
| 189 | #define reg_timer_r_masked_intr___cnt___bit 2 | ||
| 190 | #define reg_timer_r_masked_intr___trig___lsb 3 | ||
| 191 | #define reg_timer_r_masked_intr___trig___width 1 | ||
| 192 | #define reg_timer_r_masked_intr___trig___bit 3 | ||
| 193 | #define reg_timer_r_masked_intr_offset 84 | ||
| 194 | |||
| 195 | /* Register rw_test, scope timer, type rw */ | ||
| 196 | #define reg_timer_rw_test___dis___lsb 0 | ||
| 197 | #define reg_timer_rw_test___dis___width 1 | ||
| 198 | #define reg_timer_rw_test___dis___bit 0 | ||
| 199 | #define reg_timer_rw_test___en___lsb 1 | ||
| 200 | #define reg_timer_rw_test___en___width 1 | ||
| 201 | #define reg_timer_rw_test___en___bit 1 | ||
| 202 | #define reg_timer_rw_test_offset 88 | ||
| 203 | |||
| 204 | |||
| 205 | /* Constants */ | ||
| 206 | #define regk_timer_ext 0x00000001 | ||
| 207 | #define regk_timer_f100 0x00000007 | ||
| 208 | #define regk_timer_f29_493 0x00000004 | ||
| 209 | #define regk_timer_f32 0x00000005 | ||
| 210 | #define regk_timer_f32_768 0x00000006 | ||
| 211 | #define regk_timer_hold 0x00000001 | ||
| 212 | #define regk_timer_ld 0x00000000 | ||
| 213 | #define regk_timer_no 0x00000000 | ||
| 214 | #define regk_timer_off 0x00000000 | ||
| 215 | #define regk_timer_run 0x00000002 | ||
| 216 | #define regk_timer_rw_cnt_cfg_default 0x00000000 | ||
| 217 | #define regk_timer_rw_intr_mask_default 0x00000000 | ||
| 218 | #define regk_timer_rw_out_default 0x00000000 | ||
| 219 | #define regk_timer_rw_test_default 0x00000000 | ||
| 220 | #define regk_timer_rw_tmr0_ctrl_default 0x00000000 | ||
| 221 | #define regk_timer_rw_tmr1_ctrl_default 0x00000000 | ||
| 222 | #define regk_timer_rw_trig_cfg_default 0x00000000 | ||
| 223 | #define regk_timer_start 0x00000001 | ||
| 224 | #define regk_timer_stop 0x00000000 | ||
| 225 | #define regk_timer_time 0x00000001 | ||
| 226 | #define regk_timer_tmr0 0x00000002 | ||
| 227 | #define regk_timer_tmr1 0x00000003 | ||
| 228 | #define regk_timer_yes 0x00000001 | ||
| 229 | #endif /* __timer_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h deleted file mode 100644 index 44362a62b47c..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h +++ /dev/null | |||
| @@ -1,284 +0,0 @@ | |||
| 1 | #ifndef __bif_core_defs_h | ||
| 2 | #define __bif_core_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_core_regs.r | ||
| 7 | * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r | ||
| 11 | * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_core */ | ||
| 86 | |||
| 87 | /* Register rw_grp1_cfg, scope bif_core, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int lw : 6; | ||
| 90 | unsigned int ew : 3; | ||
| 91 | unsigned int zw : 3; | ||
| 92 | unsigned int aw : 2; | ||
| 93 | unsigned int dw : 2; | ||
| 94 | unsigned int ewb : 2; | ||
| 95 | unsigned int bw : 1; | ||
| 96 | unsigned int wr_extend : 1; | ||
| 97 | unsigned int erc_en : 1; | ||
| 98 | unsigned int mode : 1; | ||
| 99 | unsigned int dummy1 : 10; | ||
| 100 | } reg_bif_core_rw_grp1_cfg; | ||
| 101 | #define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 | ||
| 102 | #define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 | ||
| 103 | |||
| 104 | /* Register rw_grp2_cfg, scope bif_core, type rw */ | ||
| 105 | typedef struct { | ||
| 106 | unsigned int lw : 6; | ||
| 107 | unsigned int ew : 3; | ||
| 108 | unsigned int zw : 3; | ||
| 109 | unsigned int aw : 2; | ||
| 110 | unsigned int dw : 2; | ||
| 111 | unsigned int ewb : 2; | ||
| 112 | unsigned int bw : 1; | ||
| 113 | unsigned int wr_extend : 1; | ||
| 114 | unsigned int erc_en : 1; | ||
| 115 | unsigned int mode : 1; | ||
| 116 | unsigned int dummy1 : 10; | ||
| 117 | } reg_bif_core_rw_grp2_cfg; | ||
| 118 | #define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 | ||
| 119 | #define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 | ||
| 120 | |||
| 121 | /* Register rw_grp3_cfg, scope bif_core, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int lw : 6; | ||
| 124 | unsigned int ew : 3; | ||
| 125 | unsigned int zw : 3; | ||
| 126 | unsigned int aw : 2; | ||
| 127 | unsigned int dw : 2; | ||
| 128 | unsigned int ewb : 2; | ||
| 129 | unsigned int bw : 1; | ||
| 130 | unsigned int wr_extend : 1; | ||
| 131 | unsigned int erc_en : 1; | ||
| 132 | unsigned int mode : 1; | ||
| 133 | unsigned int dummy1 : 2; | ||
| 134 | unsigned int gated_csp0 : 2; | ||
| 135 | unsigned int gated_csp1 : 2; | ||
| 136 | unsigned int gated_csp2 : 2; | ||
| 137 | unsigned int gated_csp3 : 2; | ||
| 138 | } reg_bif_core_rw_grp3_cfg; | ||
| 139 | #define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 | ||
| 140 | #define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 | ||
| 141 | |||
| 142 | /* Register rw_grp4_cfg, scope bif_core, type rw */ | ||
| 143 | typedef struct { | ||
| 144 | unsigned int lw : 6; | ||
| 145 | unsigned int ew : 3; | ||
| 146 | unsigned int zw : 3; | ||
| 147 | unsigned int aw : 2; | ||
| 148 | unsigned int dw : 2; | ||
| 149 | unsigned int ewb : 2; | ||
| 150 | unsigned int bw : 1; | ||
| 151 | unsigned int wr_extend : 1; | ||
| 152 | unsigned int erc_en : 1; | ||
| 153 | unsigned int mode : 1; | ||
| 154 | unsigned int dummy1 : 4; | ||
| 155 | unsigned int gated_csp4 : 2; | ||
| 156 | unsigned int gated_csp5 : 2; | ||
| 157 | unsigned int gated_csp6 : 2; | ||
| 158 | } reg_bif_core_rw_grp4_cfg; | ||
| 159 | #define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 | ||
| 160 | #define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 | ||
| 161 | |||
| 162 | /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int bank_sel : 5; | ||
| 165 | unsigned int ca : 3; | ||
| 166 | unsigned int type : 1; | ||
| 167 | unsigned int bw : 1; | ||
| 168 | unsigned int sh : 3; | ||
| 169 | unsigned int wmm : 1; | ||
| 170 | unsigned int sh16 : 1; | ||
| 171 | unsigned int grp_sel : 5; | ||
| 172 | unsigned int dummy1 : 12; | ||
| 173 | } reg_bif_core_rw_sdram_cfg_grp0; | ||
| 174 | #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 | ||
| 175 | #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 | ||
| 176 | |||
| 177 | /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int bank_sel : 5; | ||
| 180 | unsigned int ca : 3; | ||
| 181 | unsigned int type : 1; | ||
| 182 | unsigned int bw : 1; | ||
| 183 | unsigned int sh : 3; | ||
| 184 | unsigned int wmm : 1; | ||
| 185 | unsigned int sh16 : 1; | ||
| 186 | unsigned int dummy1 : 17; | ||
| 187 | } reg_bif_core_rw_sdram_cfg_grp1; | ||
| 188 | #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 | ||
| 189 | #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 | ||
| 190 | |||
| 191 | /* Register rw_sdram_timing, scope bif_core, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int cl : 3; | ||
| 194 | unsigned int rcd : 3; | ||
| 195 | unsigned int rp : 3; | ||
| 196 | unsigned int rc : 2; | ||
| 197 | unsigned int dpl : 2; | ||
| 198 | unsigned int pde : 1; | ||
| 199 | unsigned int ref : 2; | ||
| 200 | unsigned int cpd : 1; | ||
| 201 | unsigned int sdcke : 1; | ||
| 202 | unsigned int sdclk : 1; | ||
| 203 | unsigned int dummy1 : 13; | ||
| 204 | } reg_bif_core_rw_sdram_timing; | ||
| 205 | #define REG_RD_ADDR_bif_core_rw_sdram_timing 24 | ||
| 206 | #define REG_WR_ADDR_bif_core_rw_sdram_timing 24 | ||
| 207 | |||
| 208 | /* Register rw_sdram_cmd, scope bif_core, type rw */ | ||
| 209 | typedef struct { | ||
| 210 | unsigned int cmd : 3; | ||
| 211 | unsigned int mrs_data : 15; | ||
| 212 | unsigned int dummy1 : 14; | ||
| 213 | } reg_bif_core_rw_sdram_cmd; | ||
| 214 | #define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 | ||
| 215 | #define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 | ||
| 216 | |||
| 217 | /* Register rs_sdram_ref_stat, scope bif_core, type rs */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int ok : 1; | ||
| 220 | unsigned int dummy1 : 31; | ||
| 221 | } reg_bif_core_rs_sdram_ref_stat; | ||
| 222 | #define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 | ||
| 223 | |||
| 224 | /* Register r_sdram_ref_stat, scope bif_core, type r */ | ||
| 225 | typedef struct { | ||
| 226 | unsigned int ok : 1; | ||
| 227 | unsigned int dummy1 : 31; | ||
| 228 | } reg_bif_core_r_sdram_ref_stat; | ||
| 229 | #define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 | ||
| 230 | |||
| 231 | |||
| 232 | /* Constants */ | ||
| 233 | enum { | ||
| 234 | regk_bif_core_bank2 = 0x00000000, | ||
| 235 | regk_bif_core_bank4 = 0x00000001, | ||
| 236 | regk_bif_core_bit10 = 0x0000000a, | ||
| 237 | regk_bif_core_bit11 = 0x0000000b, | ||
| 238 | regk_bif_core_bit12 = 0x0000000c, | ||
| 239 | regk_bif_core_bit13 = 0x0000000d, | ||
| 240 | regk_bif_core_bit14 = 0x0000000e, | ||
| 241 | regk_bif_core_bit15 = 0x0000000f, | ||
| 242 | regk_bif_core_bit16 = 0x00000010, | ||
| 243 | regk_bif_core_bit17 = 0x00000011, | ||
| 244 | regk_bif_core_bit18 = 0x00000012, | ||
| 245 | regk_bif_core_bit19 = 0x00000013, | ||
| 246 | regk_bif_core_bit20 = 0x00000014, | ||
| 247 | regk_bif_core_bit21 = 0x00000015, | ||
| 248 | regk_bif_core_bit22 = 0x00000016, | ||
| 249 | regk_bif_core_bit23 = 0x00000017, | ||
| 250 | regk_bif_core_bit24 = 0x00000018, | ||
| 251 | regk_bif_core_bit25 = 0x00000019, | ||
| 252 | regk_bif_core_bit26 = 0x0000001a, | ||
| 253 | regk_bif_core_bit27 = 0x0000001b, | ||
| 254 | regk_bif_core_bit28 = 0x0000001c, | ||
| 255 | regk_bif_core_bit29 = 0x0000001d, | ||
| 256 | regk_bif_core_bit9 = 0x00000009, | ||
| 257 | regk_bif_core_bw16 = 0x00000001, | ||
| 258 | regk_bif_core_bw32 = 0x00000000, | ||
| 259 | regk_bif_core_bwe = 0x00000000, | ||
| 260 | regk_bif_core_cwe = 0x00000001, | ||
| 261 | regk_bif_core_e15us = 0x00000001, | ||
| 262 | regk_bif_core_e7800ns = 0x00000002, | ||
| 263 | regk_bif_core_grp0 = 0x00000000, | ||
| 264 | regk_bif_core_grp1 = 0x00000001, | ||
| 265 | regk_bif_core_mrs = 0x00000003, | ||
| 266 | regk_bif_core_no = 0x00000000, | ||
| 267 | regk_bif_core_none = 0x00000000, | ||
| 268 | regk_bif_core_nop = 0x00000000, | ||
| 269 | regk_bif_core_off = 0x00000000, | ||
| 270 | regk_bif_core_pre = 0x00000002, | ||
| 271 | regk_bif_core_r_sdram_ref_stat_default = 0x00000001, | ||
| 272 | regk_bif_core_rd = 0x00000002, | ||
| 273 | regk_bif_core_ref = 0x00000001, | ||
| 274 | regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, | ||
| 275 | regk_bif_core_rw_grp1_cfg_default = 0x000006cf, | ||
| 276 | regk_bif_core_rw_grp2_cfg_default = 0x000006cf, | ||
| 277 | regk_bif_core_rw_grp3_cfg_default = 0x000006cf, | ||
| 278 | regk_bif_core_rw_grp4_cfg_default = 0x000006cf, | ||
| 279 | regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, | ||
| 280 | regk_bif_core_slf = 0x00000004, | ||
| 281 | regk_bif_core_wr = 0x00000001, | ||
| 282 | regk_bif_core_yes = 0x00000001 | ||
| 283 | }; | ||
| 284 | #endif /* __bif_core_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h deleted file mode 100644 index 3cb51a09dba7..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h +++ /dev/null | |||
| @@ -1,473 +0,0 @@ | |||
| 1 | #ifndef __bif_dma_defs_h | ||
| 2 | #define __bif_dma_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_dma_regs.r | ||
| 7 | * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r | ||
| 11 | * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_dma */ | ||
| 86 | |||
| 87 | /* Register rw_ch0_ctrl, scope bif_dma, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int bw : 2; | ||
| 90 | unsigned int burst_len : 1; | ||
| 91 | unsigned int cont : 1; | ||
| 92 | unsigned int end_pad : 1; | ||
| 93 | unsigned int cnt : 1; | ||
| 94 | unsigned int dreq_pin : 3; | ||
| 95 | unsigned int dreq_mode : 2; | ||
| 96 | unsigned int tc_in_pin : 3; | ||
| 97 | unsigned int tc_in_mode : 2; | ||
| 98 | unsigned int bus_mode : 2; | ||
| 99 | unsigned int rate_en : 1; | ||
| 100 | unsigned int wr_all : 1; | ||
| 101 | unsigned int dummy1 : 12; | ||
| 102 | } reg_bif_dma_rw_ch0_ctrl; | ||
| 103 | #define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 | ||
| 104 | #define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 | ||
| 105 | |||
| 106 | /* Register rw_ch0_addr, scope bif_dma, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int addr : 32; | ||
| 109 | } reg_bif_dma_rw_ch0_addr; | ||
| 110 | #define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 | ||
| 111 | #define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 | ||
| 112 | |||
| 113 | /* Register rw_ch0_start, scope bif_dma, type rw */ | ||
| 114 | typedef struct { | ||
| 115 | unsigned int run : 1; | ||
| 116 | unsigned int dummy1 : 31; | ||
| 117 | } reg_bif_dma_rw_ch0_start; | ||
| 118 | #define REG_RD_ADDR_bif_dma_rw_ch0_start 8 | ||
| 119 | #define REG_WR_ADDR_bif_dma_rw_ch0_start 8 | ||
| 120 | |||
| 121 | /* Register rw_ch0_cnt, scope bif_dma, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int start_cnt : 16; | ||
| 124 | unsigned int dummy1 : 16; | ||
| 125 | } reg_bif_dma_rw_ch0_cnt; | ||
| 126 | #define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 | ||
| 127 | #define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 | ||
| 128 | |||
| 129 | /* Register r_ch0_stat, scope bif_dma, type r */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int cnt : 16; | ||
| 132 | unsigned int dummy1 : 15; | ||
| 133 | unsigned int run : 1; | ||
| 134 | } reg_bif_dma_r_ch0_stat; | ||
| 135 | #define REG_RD_ADDR_bif_dma_r_ch0_stat 16 | ||
| 136 | |||
| 137 | /* Register rw_ch1_ctrl, scope bif_dma, type rw */ | ||
| 138 | typedef struct { | ||
| 139 | unsigned int bw : 2; | ||
| 140 | unsigned int burst_len : 1; | ||
| 141 | unsigned int cont : 1; | ||
| 142 | unsigned int end_discard : 1; | ||
| 143 | unsigned int cnt : 1; | ||
| 144 | unsigned int dreq_pin : 3; | ||
| 145 | unsigned int dreq_mode : 2; | ||
| 146 | unsigned int tc_in_pin : 3; | ||
| 147 | unsigned int tc_in_mode : 2; | ||
| 148 | unsigned int bus_mode : 2; | ||
| 149 | unsigned int rate_en : 1; | ||
| 150 | unsigned int dummy1 : 13; | ||
| 151 | } reg_bif_dma_rw_ch1_ctrl; | ||
| 152 | #define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 | ||
| 153 | #define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 | ||
| 154 | |||
| 155 | /* Register rw_ch1_addr, scope bif_dma, type rw */ | ||
| 156 | typedef struct { | ||
| 157 | unsigned int addr : 32; | ||
| 158 | } reg_bif_dma_rw_ch1_addr; | ||
| 159 | #define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 | ||
| 160 | #define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 | ||
| 161 | |||
| 162 | /* Register rw_ch1_start, scope bif_dma, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int run : 1; | ||
| 165 | unsigned int dummy1 : 31; | ||
| 166 | } reg_bif_dma_rw_ch1_start; | ||
| 167 | #define REG_RD_ADDR_bif_dma_rw_ch1_start 40 | ||
| 168 | #define REG_WR_ADDR_bif_dma_rw_ch1_start 40 | ||
| 169 | |||
| 170 | /* Register rw_ch1_cnt, scope bif_dma, type rw */ | ||
| 171 | typedef struct { | ||
| 172 | unsigned int start_cnt : 16; | ||
| 173 | unsigned int dummy1 : 16; | ||
| 174 | } reg_bif_dma_rw_ch1_cnt; | ||
| 175 | #define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 | ||
| 176 | #define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 | ||
| 177 | |||
| 178 | /* Register r_ch1_stat, scope bif_dma, type r */ | ||
| 179 | typedef struct { | ||
| 180 | unsigned int cnt : 16; | ||
| 181 | unsigned int dummy1 : 15; | ||
| 182 | unsigned int run : 1; | ||
| 183 | } reg_bif_dma_r_ch1_stat; | ||
| 184 | #define REG_RD_ADDR_bif_dma_r_ch1_stat 48 | ||
| 185 | |||
| 186 | /* Register rw_ch2_ctrl, scope bif_dma, type rw */ | ||
| 187 | typedef struct { | ||
| 188 | unsigned int bw : 2; | ||
| 189 | unsigned int burst_len : 1; | ||
| 190 | unsigned int cont : 1; | ||
| 191 | unsigned int end_pad : 1; | ||
| 192 | unsigned int cnt : 1; | ||
| 193 | unsigned int dreq_pin : 3; | ||
| 194 | unsigned int dreq_mode : 2; | ||
| 195 | unsigned int tc_in_pin : 3; | ||
| 196 | unsigned int tc_in_mode : 2; | ||
| 197 | unsigned int bus_mode : 2; | ||
| 198 | unsigned int rate_en : 1; | ||
| 199 | unsigned int wr_all : 1; | ||
| 200 | unsigned int dummy1 : 12; | ||
| 201 | } reg_bif_dma_rw_ch2_ctrl; | ||
| 202 | #define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 | ||
| 203 | #define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 | ||
| 204 | |||
| 205 | /* Register rw_ch2_addr, scope bif_dma, type rw */ | ||
| 206 | typedef struct { | ||
| 207 | unsigned int addr : 32; | ||
| 208 | } reg_bif_dma_rw_ch2_addr; | ||
| 209 | #define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 | ||
| 210 | #define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 | ||
| 211 | |||
| 212 | /* Register rw_ch2_start, scope bif_dma, type rw */ | ||
| 213 | typedef struct { | ||
| 214 | unsigned int run : 1; | ||
| 215 | unsigned int dummy1 : 31; | ||
| 216 | } reg_bif_dma_rw_ch2_start; | ||
| 217 | #define REG_RD_ADDR_bif_dma_rw_ch2_start 72 | ||
| 218 | #define REG_WR_ADDR_bif_dma_rw_ch2_start 72 | ||
| 219 | |||
| 220 | /* Register rw_ch2_cnt, scope bif_dma, type rw */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int start_cnt : 16; | ||
| 223 | unsigned int dummy1 : 16; | ||
| 224 | } reg_bif_dma_rw_ch2_cnt; | ||
| 225 | #define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 | ||
| 226 | #define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 | ||
| 227 | |||
| 228 | /* Register r_ch2_stat, scope bif_dma, type r */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int cnt : 16; | ||
| 231 | unsigned int dummy1 : 15; | ||
| 232 | unsigned int run : 1; | ||
| 233 | } reg_bif_dma_r_ch2_stat; | ||
| 234 | #define REG_RD_ADDR_bif_dma_r_ch2_stat 80 | ||
| 235 | |||
| 236 | /* Register rw_ch3_ctrl, scope bif_dma, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int bw : 2; | ||
| 239 | unsigned int burst_len : 1; | ||
| 240 | unsigned int cont : 1; | ||
| 241 | unsigned int end_discard : 1; | ||
| 242 | unsigned int cnt : 1; | ||
| 243 | unsigned int dreq_pin : 3; | ||
| 244 | unsigned int dreq_mode : 2; | ||
| 245 | unsigned int tc_in_pin : 3; | ||
| 246 | unsigned int tc_in_mode : 2; | ||
| 247 | unsigned int bus_mode : 2; | ||
| 248 | unsigned int rate_en : 1; | ||
| 249 | unsigned int dummy1 : 13; | ||
| 250 | } reg_bif_dma_rw_ch3_ctrl; | ||
| 251 | #define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 | ||
| 252 | #define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 | ||
| 253 | |||
| 254 | /* Register rw_ch3_addr, scope bif_dma, type rw */ | ||
| 255 | typedef struct { | ||
| 256 | unsigned int addr : 32; | ||
| 257 | } reg_bif_dma_rw_ch3_addr; | ||
| 258 | #define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 | ||
| 259 | #define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 | ||
| 260 | |||
| 261 | /* Register rw_ch3_start, scope bif_dma, type rw */ | ||
| 262 | typedef struct { | ||
| 263 | unsigned int run : 1; | ||
| 264 | unsigned int dummy1 : 31; | ||
| 265 | } reg_bif_dma_rw_ch3_start; | ||
| 266 | #define REG_RD_ADDR_bif_dma_rw_ch3_start 104 | ||
| 267 | #define REG_WR_ADDR_bif_dma_rw_ch3_start 104 | ||
| 268 | |||
| 269 | /* Register rw_ch3_cnt, scope bif_dma, type rw */ | ||
| 270 | typedef struct { | ||
| 271 | unsigned int start_cnt : 16; | ||
| 272 | unsigned int dummy1 : 16; | ||
| 273 | } reg_bif_dma_rw_ch3_cnt; | ||
| 274 | #define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 | ||
| 275 | #define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 | ||
| 276 | |||
| 277 | /* Register r_ch3_stat, scope bif_dma, type r */ | ||
| 278 | typedef struct { | ||
| 279 | unsigned int cnt : 16; | ||
| 280 | unsigned int dummy1 : 15; | ||
| 281 | unsigned int run : 1; | ||
| 282 | } reg_bif_dma_r_ch3_stat; | ||
| 283 | #define REG_RD_ADDR_bif_dma_r_ch3_stat 112 | ||
| 284 | |||
| 285 | /* Register rw_intr_mask, scope bif_dma, type rw */ | ||
| 286 | typedef struct { | ||
| 287 | unsigned int ext_dma0 : 1; | ||
| 288 | unsigned int ext_dma1 : 1; | ||
| 289 | unsigned int ext_dma2 : 1; | ||
| 290 | unsigned int ext_dma3 : 1; | ||
| 291 | unsigned int dummy1 : 28; | ||
| 292 | } reg_bif_dma_rw_intr_mask; | ||
| 293 | #define REG_RD_ADDR_bif_dma_rw_intr_mask 128 | ||
| 294 | #define REG_WR_ADDR_bif_dma_rw_intr_mask 128 | ||
| 295 | |||
| 296 | /* Register rw_ack_intr, scope bif_dma, type rw */ | ||
| 297 | typedef struct { | ||
| 298 | unsigned int ext_dma0 : 1; | ||
| 299 | unsigned int ext_dma1 : 1; | ||
| 300 | unsigned int ext_dma2 : 1; | ||
| 301 | unsigned int ext_dma3 : 1; | ||
| 302 | unsigned int dummy1 : 28; | ||
| 303 | } reg_bif_dma_rw_ack_intr; | ||
| 304 | #define REG_RD_ADDR_bif_dma_rw_ack_intr 132 | ||
| 305 | #define REG_WR_ADDR_bif_dma_rw_ack_intr 132 | ||
| 306 | |||
| 307 | /* Register r_intr, scope bif_dma, type r */ | ||
| 308 | typedef struct { | ||
| 309 | unsigned int ext_dma0 : 1; | ||
| 310 | unsigned int ext_dma1 : 1; | ||
| 311 | unsigned int ext_dma2 : 1; | ||
| 312 | unsigned int ext_dma3 : 1; | ||
| 313 | unsigned int dummy1 : 28; | ||
| 314 | } reg_bif_dma_r_intr; | ||
| 315 | #define REG_RD_ADDR_bif_dma_r_intr 136 | ||
| 316 | |||
| 317 | /* Register r_masked_intr, scope bif_dma, type r */ | ||
| 318 | typedef struct { | ||
| 319 | unsigned int ext_dma0 : 1; | ||
| 320 | unsigned int ext_dma1 : 1; | ||
| 321 | unsigned int ext_dma2 : 1; | ||
| 322 | unsigned int ext_dma3 : 1; | ||
| 323 | unsigned int dummy1 : 28; | ||
| 324 | } reg_bif_dma_r_masked_intr; | ||
| 325 | #define REG_RD_ADDR_bif_dma_r_masked_intr 140 | ||
| 326 | |||
| 327 | /* Register rw_pin0_cfg, scope bif_dma, type rw */ | ||
| 328 | typedef struct { | ||
| 329 | unsigned int master_ch : 2; | ||
| 330 | unsigned int master_mode : 3; | ||
| 331 | unsigned int slave_ch : 2; | ||
| 332 | unsigned int slave_mode : 3; | ||
| 333 | unsigned int dummy1 : 22; | ||
| 334 | } reg_bif_dma_rw_pin0_cfg; | ||
| 335 | #define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 | ||
| 336 | #define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 | ||
| 337 | |||
| 338 | /* Register rw_pin1_cfg, scope bif_dma, type rw */ | ||
| 339 | typedef struct { | ||
| 340 | unsigned int master_ch : 2; | ||
| 341 | unsigned int master_mode : 3; | ||
| 342 | unsigned int slave_ch : 2; | ||
| 343 | unsigned int slave_mode : 3; | ||
| 344 | unsigned int dummy1 : 22; | ||
| 345 | } reg_bif_dma_rw_pin1_cfg; | ||
| 346 | #define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 | ||
| 347 | #define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 | ||
| 348 | |||
| 349 | /* Register rw_pin2_cfg, scope bif_dma, type rw */ | ||
| 350 | typedef struct { | ||
| 351 | unsigned int master_ch : 2; | ||
| 352 | unsigned int master_mode : 3; | ||
| 353 | unsigned int slave_ch : 2; | ||
| 354 | unsigned int slave_mode : 3; | ||
| 355 | unsigned int dummy1 : 22; | ||
| 356 | } reg_bif_dma_rw_pin2_cfg; | ||
| 357 | #define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 | ||
| 358 | #define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 | ||
| 359 | |||
| 360 | /* Register rw_pin3_cfg, scope bif_dma, type rw */ | ||
| 361 | typedef struct { | ||
| 362 | unsigned int master_ch : 2; | ||
| 363 | unsigned int master_mode : 3; | ||
| 364 | unsigned int slave_ch : 2; | ||
| 365 | unsigned int slave_mode : 3; | ||
| 366 | unsigned int dummy1 : 22; | ||
| 367 | } reg_bif_dma_rw_pin3_cfg; | ||
| 368 | #define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 | ||
| 369 | #define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 | ||
| 370 | |||
| 371 | /* Register rw_pin4_cfg, scope bif_dma, type rw */ | ||
| 372 | typedef struct { | ||
| 373 | unsigned int master_ch : 2; | ||
| 374 | unsigned int master_mode : 3; | ||
| 375 | unsigned int slave_ch : 2; | ||
| 376 | unsigned int slave_mode : 3; | ||
| 377 | unsigned int dummy1 : 22; | ||
| 378 | } reg_bif_dma_rw_pin4_cfg; | ||
| 379 | #define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 | ||
| 380 | #define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 | ||
| 381 | |||
| 382 | /* Register rw_pin5_cfg, scope bif_dma, type rw */ | ||
| 383 | typedef struct { | ||
| 384 | unsigned int master_ch : 2; | ||
| 385 | unsigned int master_mode : 3; | ||
| 386 | unsigned int slave_ch : 2; | ||
| 387 | unsigned int slave_mode : 3; | ||
| 388 | unsigned int dummy1 : 22; | ||
| 389 | } reg_bif_dma_rw_pin5_cfg; | ||
| 390 | #define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 | ||
| 391 | #define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 | ||
| 392 | |||
| 393 | /* Register rw_pin6_cfg, scope bif_dma, type rw */ | ||
| 394 | typedef struct { | ||
| 395 | unsigned int master_ch : 2; | ||
| 396 | unsigned int master_mode : 3; | ||
| 397 | unsigned int slave_ch : 2; | ||
| 398 | unsigned int slave_mode : 3; | ||
| 399 | unsigned int dummy1 : 22; | ||
| 400 | } reg_bif_dma_rw_pin6_cfg; | ||
| 401 | #define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 | ||
| 402 | #define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 | ||
| 403 | |||
| 404 | /* Register rw_pin7_cfg, scope bif_dma, type rw */ | ||
| 405 | typedef struct { | ||
| 406 | unsigned int master_ch : 2; | ||
| 407 | unsigned int master_mode : 3; | ||
| 408 | unsigned int slave_ch : 2; | ||
| 409 | unsigned int slave_mode : 3; | ||
| 410 | unsigned int dummy1 : 22; | ||
| 411 | } reg_bif_dma_rw_pin7_cfg; | ||
| 412 | #define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 | ||
| 413 | #define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 | ||
| 414 | |||
| 415 | /* Register r_pin_stat, scope bif_dma, type r */ | ||
| 416 | typedef struct { | ||
| 417 | unsigned int pin0 : 1; | ||
| 418 | unsigned int pin1 : 1; | ||
| 419 | unsigned int pin2 : 1; | ||
| 420 | unsigned int pin3 : 1; | ||
| 421 | unsigned int pin4 : 1; | ||
| 422 | unsigned int pin5 : 1; | ||
| 423 | unsigned int pin6 : 1; | ||
| 424 | unsigned int pin7 : 1; | ||
| 425 | unsigned int dummy1 : 24; | ||
| 426 | } reg_bif_dma_r_pin_stat; | ||
| 427 | #define REG_RD_ADDR_bif_dma_r_pin_stat 192 | ||
| 428 | |||
| 429 | |||
| 430 | /* Constants */ | ||
| 431 | enum { | ||
| 432 | regk_bif_dma_as_master = 0x00000001, | ||
| 433 | regk_bif_dma_as_slave = 0x00000001, | ||
| 434 | regk_bif_dma_burst1 = 0x00000000, | ||
| 435 | regk_bif_dma_burst8 = 0x00000001, | ||
| 436 | regk_bif_dma_bw16 = 0x00000001, | ||
| 437 | regk_bif_dma_bw32 = 0x00000002, | ||
| 438 | regk_bif_dma_bw8 = 0x00000000, | ||
| 439 | regk_bif_dma_dack = 0x00000006, | ||
| 440 | regk_bif_dma_dack_inv = 0x00000007, | ||
| 441 | regk_bif_dma_force = 0x00000001, | ||
| 442 | regk_bif_dma_hi = 0x00000003, | ||
| 443 | regk_bif_dma_inv = 0x00000003, | ||
| 444 | regk_bif_dma_lo = 0x00000002, | ||
| 445 | regk_bif_dma_master = 0x00000001, | ||
| 446 | regk_bif_dma_no = 0x00000000, | ||
| 447 | regk_bif_dma_norm = 0x00000002, | ||
| 448 | regk_bif_dma_off = 0x00000000, | ||
| 449 | regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, | ||
| 450 | regk_bif_dma_rw_ch0_start_default = 0x00000000, | ||
| 451 | regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, | ||
| 452 | regk_bif_dma_rw_ch1_start_default = 0x00000000, | ||
| 453 | regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, | ||
| 454 | regk_bif_dma_rw_ch2_start_default = 0x00000000, | ||
| 455 | regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, | ||
| 456 | regk_bif_dma_rw_ch3_start_default = 0x00000000, | ||
| 457 | regk_bif_dma_rw_intr_mask_default = 0x00000000, | ||
| 458 | regk_bif_dma_rw_pin0_cfg_default = 0x00000000, | ||
| 459 | regk_bif_dma_rw_pin1_cfg_default = 0x00000000, | ||
| 460 | regk_bif_dma_rw_pin2_cfg_default = 0x00000000, | ||
| 461 | regk_bif_dma_rw_pin3_cfg_default = 0x00000000, | ||
| 462 | regk_bif_dma_rw_pin4_cfg_default = 0x00000000, | ||
| 463 | regk_bif_dma_rw_pin5_cfg_default = 0x00000000, | ||
| 464 | regk_bif_dma_rw_pin6_cfg_default = 0x00000000, | ||
| 465 | regk_bif_dma_rw_pin7_cfg_default = 0x00000000, | ||
| 466 | regk_bif_dma_slave = 0x00000002, | ||
| 467 | regk_bif_dma_sreq = 0x00000006, | ||
| 468 | regk_bif_dma_sreq_inv = 0x00000007, | ||
| 469 | regk_bif_dma_tc = 0x00000004, | ||
| 470 | regk_bif_dma_tc_inv = 0x00000005, | ||
| 471 | regk_bif_dma_yes = 0x00000001 | ||
| 472 | }; | ||
| 473 | #endif /* __bif_dma_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h deleted file mode 100644 index 0c434585a3f9..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h +++ /dev/null | |||
| @@ -1,249 +0,0 @@ | |||
| 1 | #ifndef __bif_slave_defs_h | ||
| 2 | #define __bif_slave_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_slave_regs.r | ||
| 7 | * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:34 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r | ||
| 11 | * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_slave */ | ||
| 86 | |||
| 87 | /* Register rw_slave_cfg, scope bif_slave, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int slave_id : 3; | ||
| 90 | unsigned int use_slave_id : 1; | ||
| 91 | unsigned int boot_rdy : 1; | ||
| 92 | unsigned int loopback : 1; | ||
| 93 | unsigned int dis : 1; | ||
| 94 | unsigned int dummy1 : 25; | ||
| 95 | } reg_bif_slave_rw_slave_cfg; | ||
| 96 | #define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 | ||
| 97 | #define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 | ||
| 98 | |||
| 99 | /* Register r_slave_mode, scope bif_slave, type r */ | ||
| 100 | typedef struct { | ||
| 101 | unsigned int ch0_mode : 1; | ||
| 102 | unsigned int ch1_mode : 1; | ||
| 103 | unsigned int ch2_mode : 1; | ||
| 104 | unsigned int ch3_mode : 1; | ||
| 105 | unsigned int dummy1 : 28; | ||
| 106 | } reg_bif_slave_r_slave_mode; | ||
| 107 | #define REG_RD_ADDR_bif_slave_r_slave_mode 4 | ||
| 108 | |||
| 109 | /* Register rw_ch0_cfg, scope bif_slave, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int rd_hold : 2; | ||
| 112 | unsigned int access_mode : 1; | ||
| 113 | unsigned int access_ctrl : 1; | ||
| 114 | unsigned int data_cs : 2; | ||
| 115 | unsigned int dummy1 : 26; | ||
| 116 | } reg_bif_slave_rw_ch0_cfg; | ||
| 117 | #define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 | ||
| 118 | #define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 | ||
| 119 | |||
| 120 | /* Register rw_ch1_cfg, scope bif_slave, type rw */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int rd_hold : 2; | ||
| 123 | unsigned int access_mode : 1; | ||
| 124 | unsigned int access_ctrl : 1; | ||
| 125 | unsigned int data_cs : 2; | ||
| 126 | unsigned int dummy1 : 26; | ||
| 127 | } reg_bif_slave_rw_ch1_cfg; | ||
| 128 | #define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 | ||
| 129 | #define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 | ||
| 130 | |||
| 131 | /* Register rw_ch2_cfg, scope bif_slave, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int rd_hold : 2; | ||
| 134 | unsigned int access_mode : 1; | ||
| 135 | unsigned int access_ctrl : 1; | ||
| 136 | unsigned int data_cs : 2; | ||
| 137 | unsigned int dummy1 : 26; | ||
| 138 | } reg_bif_slave_rw_ch2_cfg; | ||
| 139 | #define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 | ||
| 140 | #define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 | ||
| 141 | |||
| 142 | /* Register rw_ch3_cfg, scope bif_slave, type rw */ | ||
| 143 | typedef struct { | ||
| 144 | unsigned int rd_hold : 2; | ||
| 145 | unsigned int access_mode : 1; | ||
| 146 | unsigned int access_ctrl : 1; | ||
| 147 | unsigned int data_cs : 2; | ||
| 148 | unsigned int dummy1 : 26; | ||
| 149 | } reg_bif_slave_rw_ch3_cfg; | ||
| 150 | #define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 | ||
| 151 | #define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 | ||
| 152 | |||
| 153 | /* Register rw_arb_cfg, scope bif_slave, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int brin_mode : 1; | ||
| 156 | unsigned int brout_mode : 3; | ||
| 157 | unsigned int bg_mode : 3; | ||
| 158 | unsigned int release : 2; | ||
| 159 | unsigned int acquire : 1; | ||
| 160 | unsigned int settle_time : 2; | ||
| 161 | unsigned int dram_ctrl : 1; | ||
| 162 | unsigned int dummy1 : 19; | ||
| 163 | } reg_bif_slave_rw_arb_cfg; | ||
| 164 | #define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 | ||
| 165 | #define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 | ||
| 166 | |||
| 167 | /* Register r_arb_stat, scope bif_slave, type r */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int init_mode : 1; | ||
| 170 | unsigned int mode : 1; | ||
| 171 | unsigned int brin : 1; | ||
| 172 | unsigned int brout : 1; | ||
| 173 | unsigned int bg : 1; | ||
| 174 | unsigned int dummy1 : 27; | ||
| 175 | } reg_bif_slave_r_arb_stat; | ||
| 176 | #define REG_RD_ADDR_bif_slave_r_arb_stat 36 | ||
| 177 | |||
| 178 | /* Register rw_intr_mask, scope bif_slave, type rw */ | ||
| 179 | typedef struct { | ||
| 180 | unsigned int bus_release : 1; | ||
| 181 | unsigned int bus_acquire : 1; | ||
| 182 | unsigned int dummy1 : 30; | ||
| 183 | } reg_bif_slave_rw_intr_mask; | ||
| 184 | #define REG_RD_ADDR_bif_slave_rw_intr_mask 64 | ||
| 185 | #define REG_WR_ADDR_bif_slave_rw_intr_mask 64 | ||
| 186 | |||
| 187 | /* Register rw_ack_intr, scope bif_slave, type rw */ | ||
| 188 | typedef struct { | ||
| 189 | unsigned int bus_release : 1; | ||
| 190 | unsigned int bus_acquire : 1; | ||
| 191 | unsigned int dummy1 : 30; | ||
| 192 | } reg_bif_slave_rw_ack_intr; | ||
| 193 | #define REG_RD_ADDR_bif_slave_rw_ack_intr 68 | ||
| 194 | #define REG_WR_ADDR_bif_slave_rw_ack_intr 68 | ||
| 195 | |||
| 196 | /* Register r_intr, scope bif_slave, type r */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int bus_release : 1; | ||
| 199 | unsigned int bus_acquire : 1; | ||
| 200 | unsigned int dummy1 : 30; | ||
| 201 | } reg_bif_slave_r_intr; | ||
| 202 | #define REG_RD_ADDR_bif_slave_r_intr 72 | ||
| 203 | |||
| 204 | /* Register r_masked_intr, scope bif_slave, type r */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int bus_release : 1; | ||
| 207 | unsigned int bus_acquire : 1; | ||
| 208 | unsigned int dummy1 : 30; | ||
| 209 | } reg_bif_slave_r_masked_intr; | ||
| 210 | #define REG_RD_ADDR_bif_slave_r_masked_intr 76 | ||
| 211 | |||
| 212 | |||
| 213 | /* Constants */ | ||
| 214 | enum { | ||
| 215 | regk_bif_slave_active_hi = 0x00000003, | ||
| 216 | regk_bif_slave_active_lo = 0x00000002, | ||
| 217 | regk_bif_slave_addr = 0x00000000, | ||
| 218 | regk_bif_slave_always = 0x00000001, | ||
| 219 | regk_bif_slave_at_idle = 0x00000002, | ||
| 220 | regk_bif_slave_burst_end = 0x00000003, | ||
| 221 | regk_bif_slave_dma = 0x00000001, | ||
| 222 | regk_bif_slave_hi = 0x00000003, | ||
| 223 | regk_bif_slave_inv = 0x00000001, | ||
| 224 | regk_bif_slave_lo = 0x00000002, | ||
| 225 | regk_bif_slave_local = 0x00000001, | ||
| 226 | regk_bif_slave_master = 0x00000000, | ||
| 227 | regk_bif_slave_mode_reg = 0x00000001, | ||
| 228 | regk_bif_slave_no = 0x00000000, | ||
| 229 | regk_bif_slave_norm = 0x00000000, | ||
| 230 | regk_bif_slave_on_access = 0x00000000, | ||
| 231 | regk_bif_slave_rw_arb_cfg_default = 0x00000000, | ||
| 232 | regk_bif_slave_rw_ch0_cfg_default = 0x00000000, | ||
| 233 | regk_bif_slave_rw_ch1_cfg_default = 0x00000000, | ||
| 234 | regk_bif_slave_rw_ch2_cfg_default = 0x00000000, | ||
| 235 | regk_bif_slave_rw_ch3_cfg_default = 0x00000000, | ||
| 236 | regk_bif_slave_rw_intr_mask_default = 0x00000000, | ||
| 237 | regk_bif_slave_rw_slave_cfg_default = 0x00000000, | ||
| 238 | regk_bif_slave_shared = 0x00000000, | ||
| 239 | regk_bif_slave_slave = 0x00000001, | ||
| 240 | regk_bif_slave_t0ns = 0x00000003, | ||
| 241 | regk_bif_slave_t10ns = 0x00000002, | ||
| 242 | regk_bif_slave_t20ns = 0x00000003, | ||
| 243 | regk_bif_slave_t30ns = 0x00000002, | ||
| 244 | regk_bif_slave_t40ns = 0x00000001, | ||
| 245 | regk_bif_slave_t50ns = 0x00000000, | ||
| 246 | regk_bif_slave_yes = 0x00000001, | ||
| 247 | regk_bif_slave_z = 0x00000004 | ||
| 248 | }; | ||
| 249 | #endif /* __bif_slave_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h deleted file mode 100644 index abc5f20705f7..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h +++ /dev/null | |||
| @@ -1,142 +0,0 @@ | |||
| 1 | #ifndef __config_defs_h | ||
| 2 | #define __config_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../rtl/config_regs.r | ||
| 7 | * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp | ||
| 8 | * last modfied: Thu Mar 4 12:34:39 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r | ||
| 11 | * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope config */ | ||
| 86 | |||
| 87 | /* Register r_bootsel, scope config, type r */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int boot_mode : 3; | ||
| 90 | unsigned int full_duplex : 1; | ||
| 91 | unsigned int user : 1; | ||
| 92 | unsigned int pll : 1; | ||
| 93 | unsigned int flash_bw : 1; | ||
| 94 | unsigned int dummy1 : 25; | ||
| 95 | } reg_config_r_bootsel; | ||
| 96 | #define REG_RD_ADDR_config_r_bootsel 0 | ||
| 97 | |||
| 98 | /* Register rw_clk_ctrl, scope config, type rw */ | ||
| 99 | typedef struct { | ||
| 100 | unsigned int pll : 1; | ||
| 101 | unsigned int cpu : 1; | ||
| 102 | unsigned int iop : 1; | ||
| 103 | unsigned int dma01_eth0 : 1; | ||
| 104 | unsigned int dma23 : 1; | ||
| 105 | unsigned int dma45 : 1; | ||
| 106 | unsigned int dma67 : 1; | ||
| 107 | unsigned int dma89_strcop : 1; | ||
| 108 | unsigned int bif : 1; | ||
| 109 | unsigned int fix_io : 1; | ||
| 110 | unsigned int dummy1 : 22; | ||
| 111 | } reg_config_rw_clk_ctrl; | ||
| 112 | #define REG_RD_ADDR_config_rw_clk_ctrl 4 | ||
| 113 | #define REG_WR_ADDR_config_rw_clk_ctrl 4 | ||
| 114 | |||
| 115 | /* Register rw_pad_ctrl, scope config, type rw */ | ||
| 116 | typedef struct { | ||
| 117 | unsigned int usb_susp : 1; | ||
| 118 | unsigned int phyrst_n : 1; | ||
| 119 | unsigned int dummy1 : 30; | ||
| 120 | } reg_config_rw_pad_ctrl; | ||
| 121 | #define REG_RD_ADDR_config_rw_pad_ctrl 8 | ||
| 122 | #define REG_WR_ADDR_config_rw_pad_ctrl 8 | ||
| 123 | |||
| 124 | |||
| 125 | /* Constants */ | ||
| 126 | enum { | ||
| 127 | regk_config_bw16 = 0x00000000, | ||
| 128 | regk_config_bw32 = 0x00000001, | ||
| 129 | regk_config_master = 0x00000005, | ||
| 130 | regk_config_nand = 0x00000003, | ||
| 131 | regk_config_net_rx = 0x00000001, | ||
| 132 | regk_config_net_tx_rx = 0x00000002, | ||
| 133 | regk_config_no = 0x00000000, | ||
| 134 | regk_config_none = 0x00000007, | ||
| 135 | regk_config_nor = 0x00000000, | ||
| 136 | regk_config_rw_clk_ctrl_default = 0x00000002, | ||
| 137 | regk_config_rw_pad_ctrl_default = 0x00000000, | ||
| 138 | regk_config_ser = 0x00000004, | ||
| 139 | regk_config_slave = 0x00000006, | ||
| 140 | regk_config_yes = 0x00000001 | ||
| 141 | }; | ||
| 142 | #endif /* __config_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h deleted file mode 100644 index 26aa3efcf91b..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h +++ /dev/null | |||
| @@ -1,295 +0,0 @@ | |||
| 1 | #ifndef __gio_defs_h | ||
| 2 | #define __gio_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/gio/rtl/gio_regs.r | ||
| 7 | * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:07:47 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r | ||
| 11 | * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope gio */ | ||
| 86 | |||
| 87 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int data : 8; | ||
| 90 | unsigned int dummy1 : 24; | ||
| 91 | } reg_gio_rw_pa_dout; | ||
| 92 | #define REG_RD_ADDR_gio_rw_pa_dout 0 | ||
| 93 | #define REG_WR_ADDR_gio_rw_pa_dout 0 | ||
| 94 | |||
| 95 | /* Register r_pa_din, scope gio, type r */ | ||
| 96 | typedef struct { | ||
| 97 | unsigned int data : 8; | ||
| 98 | unsigned int dummy1 : 24; | ||
| 99 | } reg_gio_r_pa_din; | ||
| 100 | #define REG_RD_ADDR_gio_r_pa_din 4 | ||
| 101 | |||
| 102 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 103 | typedef struct { | ||
| 104 | unsigned int oe : 8; | ||
| 105 | unsigned int dummy1 : 24; | ||
| 106 | } reg_gio_rw_pa_oe; | ||
| 107 | #define REG_RD_ADDR_gio_rw_pa_oe 8 | ||
| 108 | #define REG_WR_ADDR_gio_rw_pa_oe 8 | ||
| 109 | |||
| 110 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int pa0 : 3; | ||
| 113 | unsigned int pa1 : 3; | ||
| 114 | unsigned int pa2 : 3; | ||
| 115 | unsigned int pa3 : 3; | ||
| 116 | unsigned int pa4 : 3; | ||
| 117 | unsigned int pa5 : 3; | ||
| 118 | unsigned int pa6 : 3; | ||
| 119 | unsigned int pa7 : 3; | ||
| 120 | unsigned int dummy1 : 8; | ||
| 121 | } reg_gio_rw_intr_cfg; | ||
| 122 | #define REG_RD_ADDR_gio_rw_intr_cfg 12 | ||
| 123 | #define REG_WR_ADDR_gio_rw_intr_cfg 12 | ||
| 124 | |||
| 125 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int pa0 : 1; | ||
| 128 | unsigned int pa1 : 1; | ||
| 129 | unsigned int pa2 : 1; | ||
| 130 | unsigned int pa3 : 1; | ||
| 131 | unsigned int pa4 : 1; | ||
| 132 | unsigned int pa5 : 1; | ||
| 133 | unsigned int pa6 : 1; | ||
| 134 | unsigned int pa7 : 1; | ||
| 135 | unsigned int dummy1 : 24; | ||
| 136 | } reg_gio_rw_intr_mask; | ||
| 137 | #define REG_RD_ADDR_gio_rw_intr_mask 16 | ||
| 138 | #define REG_WR_ADDR_gio_rw_intr_mask 16 | ||
| 139 | |||
| 140 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 141 | typedef struct { | ||
| 142 | unsigned int pa0 : 1; | ||
| 143 | unsigned int pa1 : 1; | ||
| 144 | unsigned int pa2 : 1; | ||
| 145 | unsigned int pa3 : 1; | ||
| 146 | unsigned int pa4 : 1; | ||
| 147 | unsigned int pa5 : 1; | ||
| 148 | unsigned int pa6 : 1; | ||
| 149 | unsigned int pa7 : 1; | ||
| 150 | unsigned int dummy1 : 24; | ||
| 151 | } reg_gio_rw_ack_intr; | ||
| 152 | #define REG_RD_ADDR_gio_rw_ack_intr 20 | ||
| 153 | #define REG_WR_ADDR_gio_rw_ack_intr 20 | ||
| 154 | |||
| 155 | /* Register r_intr, scope gio, type r */ | ||
| 156 | typedef struct { | ||
| 157 | unsigned int pa0 : 1; | ||
| 158 | unsigned int pa1 : 1; | ||
| 159 | unsigned int pa2 : 1; | ||
| 160 | unsigned int pa3 : 1; | ||
| 161 | unsigned int pa4 : 1; | ||
| 162 | unsigned int pa5 : 1; | ||
| 163 | unsigned int pa6 : 1; | ||
| 164 | unsigned int pa7 : 1; | ||
| 165 | unsigned int dummy1 : 24; | ||
| 166 | } reg_gio_r_intr; | ||
| 167 | #define REG_RD_ADDR_gio_r_intr 24 | ||
| 168 | |||
| 169 | /* Register r_masked_intr, scope gio, type r */ | ||
| 170 | typedef struct { | ||
| 171 | unsigned int pa0 : 1; | ||
| 172 | unsigned int pa1 : 1; | ||
| 173 | unsigned int pa2 : 1; | ||
| 174 | unsigned int pa3 : 1; | ||
| 175 | unsigned int pa4 : 1; | ||
| 176 | unsigned int pa5 : 1; | ||
| 177 | unsigned int pa6 : 1; | ||
| 178 | unsigned int pa7 : 1; | ||
| 179 | unsigned int dummy1 : 24; | ||
| 180 | } reg_gio_r_masked_intr; | ||
| 181 | #define REG_RD_ADDR_gio_r_masked_intr 28 | ||
| 182 | |||
| 183 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int data : 18; | ||
| 186 | unsigned int dummy1 : 14; | ||
| 187 | } reg_gio_rw_pb_dout; | ||
| 188 | #define REG_RD_ADDR_gio_rw_pb_dout 32 | ||
| 189 | #define REG_WR_ADDR_gio_rw_pb_dout 32 | ||
| 190 | |||
| 191 | /* Register r_pb_din, scope gio, type r */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int data : 18; | ||
| 194 | unsigned int dummy1 : 14; | ||
| 195 | } reg_gio_r_pb_din; | ||
| 196 | #define REG_RD_ADDR_gio_r_pb_din 36 | ||
| 197 | |||
| 198 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 199 | typedef struct { | ||
| 200 | unsigned int oe : 18; | ||
| 201 | unsigned int dummy1 : 14; | ||
| 202 | } reg_gio_rw_pb_oe; | ||
| 203 | #define REG_RD_ADDR_gio_rw_pb_oe 40 | ||
| 204 | #define REG_WR_ADDR_gio_rw_pb_oe 40 | ||
| 205 | |||
| 206 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 207 | typedef struct { | ||
| 208 | unsigned int data : 18; | ||
| 209 | unsigned int dummy1 : 14; | ||
| 210 | } reg_gio_rw_pc_dout; | ||
| 211 | #define REG_RD_ADDR_gio_rw_pc_dout 48 | ||
| 212 | #define REG_WR_ADDR_gio_rw_pc_dout 48 | ||
| 213 | |||
| 214 | /* Register r_pc_din, scope gio, type r */ | ||
| 215 | typedef struct { | ||
| 216 | unsigned int data : 18; | ||
| 217 | unsigned int dummy1 : 14; | ||
| 218 | } reg_gio_r_pc_din; | ||
| 219 | #define REG_RD_ADDR_gio_r_pc_din 52 | ||
| 220 | |||
| 221 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 222 | typedef struct { | ||
| 223 | unsigned int oe : 18; | ||
| 224 | unsigned int dummy1 : 14; | ||
| 225 | } reg_gio_rw_pc_oe; | ||
| 226 | #define REG_RD_ADDR_gio_rw_pc_oe 56 | ||
| 227 | #define REG_WR_ADDR_gio_rw_pc_oe 56 | ||
| 228 | |||
| 229 | /* Register rw_pd_dout, scope gio, type rw */ | ||
| 230 | typedef struct { | ||
| 231 | unsigned int data : 18; | ||
| 232 | unsigned int dummy1 : 14; | ||
| 233 | } reg_gio_rw_pd_dout; | ||
| 234 | #define REG_RD_ADDR_gio_rw_pd_dout 64 | ||
| 235 | #define REG_WR_ADDR_gio_rw_pd_dout 64 | ||
| 236 | |||
| 237 | /* Register r_pd_din, scope gio, type r */ | ||
| 238 | typedef struct { | ||
| 239 | unsigned int data : 18; | ||
| 240 | unsigned int dummy1 : 14; | ||
| 241 | } reg_gio_r_pd_din; | ||
| 242 | #define REG_RD_ADDR_gio_r_pd_din 68 | ||
| 243 | |||
| 244 | /* Register rw_pd_oe, scope gio, type rw */ | ||
| 245 | typedef struct { | ||
| 246 | unsigned int oe : 18; | ||
| 247 | unsigned int dummy1 : 14; | ||
| 248 | } reg_gio_rw_pd_oe; | ||
| 249 | #define REG_RD_ADDR_gio_rw_pd_oe 72 | ||
| 250 | #define REG_WR_ADDR_gio_rw_pd_oe 72 | ||
| 251 | |||
| 252 | /* Register rw_pe_dout, scope gio, type rw */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int data : 18; | ||
| 255 | unsigned int dummy1 : 14; | ||
| 256 | } reg_gio_rw_pe_dout; | ||
| 257 | #define REG_RD_ADDR_gio_rw_pe_dout 80 | ||
| 258 | #define REG_WR_ADDR_gio_rw_pe_dout 80 | ||
| 259 | |||
| 260 | /* Register r_pe_din, scope gio, type r */ | ||
| 261 | typedef struct { | ||
| 262 | unsigned int data : 18; | ||
| 263 | unsigned int dummy1 : 14; | ||
| 264 | } reg_gio_r_pe_din; | ||
| 265 | #define REG_RD_ADDR_gio_r_pe_din 84 | ||
| 266 | |||
| 267 | /* Register rw_pe_oe, scope gio, type rw */ | ||
| 268 | typedef struct { | ||
| 269 | unsigned int oe : 18; | ||
| 270 | unsigned int dummy1 : 14; | ||
| 271 | } reg_gio_rw_pe_oe; | ||
| 272 | #define REG_RD_ADDR_gio_rw_pe_oe 88 | ||
| 273 | #define REG_WR_ADDR_gio_rw_pe_oe 88 | ||
| 274 | |||
| 275 | |||
| 276 | /* Constants */ | ||
| 277 | enum { | ||
| 278 | regk_gio_anyedge = 0x00000007, | ||
| 279 | regk_gio_hi = 0x00000001, | ||
| 280 | regk_gio_lo = 0x00000002, | ||
| 281 | regk_gio_negedge = 0x00000006, | ||
| 282 | regk_gio_no = 0x00000000, | ||
| 283 | regk_gio_off = 0x00000000, | ||
| 284 | regk_gio_posedge = 0x00000005, | ||
| 285 | regk_gio_rw_intr_cfg_default = 0x00000000, | ||
| 286 | regk_gio_rw_intr_mask_default = 0x00000000, | ||
| 287 | regk_gio_rw_pa_oe_default = 0x00000000, | ||
| 288 | regk_gio_rw_pb_oe_default = 0x00000000, | ||
| 289 | regk_gio_rw_pc_oe_default = 0x00000000, | ||
| 290 | regk_gio_rw_pd_oe_default = 0x00000000, | ||
| 291 | regk_gio_rw_pe_oe_default = 0x00000000, | ||
| 292 | regk_gio_set = 0x00000003, | ||
| 293 | regk_gio_yes = 0x00000001 | ||
| 294 | }; | ||
| 295 | #endif /* __gio_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h deleted file mode 100644 index bacc2a895c21..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version | ||
| 2 | from ../../inst/intr_vect/rtl/guinness/ivmask.config.r | ||
| 3 | version . */ | ||
| 4 | |||
| 5 | #ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R | ||
| 6 | #define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R | ||
| 7 | #define MEMARB_INTR_VECT 0x31 | ||
| 8 | #define GEN_IO_INTR_VECT 0x32 | ||
| 9 | #define GIO_INTR_VECT GEN_IO_INTR_VECT | ||
| 10 | #define IOP0_INTR_VECT 0x33 | ||
| 11 | #define IOP1_INTR_VECT 0x34 | ||
| 12 | #define IOP2_INTR_VECT 0x35 | ||
| 13 | #define IOP3_INTR_VECT 0x36 | ||
| 14 | #define DMA0_INTR_VECT 0x37 | ||
| 15 | #define DMA1_INTR_VECT 0x38 | ||
| 16 | #define DMA2_INTR_VECT 0x39 | ||
| 17 | #define DMA3_INTR_VECT 0x3a | ||
| 18 | #define DMA4_INTR_VECT 0x3b | ||
| 19 | #define DMA5_INTR_VECT 0x3c | ||
| 20 | #define DMA6_INTR_VECT 0x3d | ||
| 21 | #define DMA7_INTR_VECT 0x3e | ||
| 22 | #define DMA8_INTR_VECT 0x3f | ||
| 23 | #define DMA9_INTR_VECT 0x40 | ||
| 24 | #define ATA_INTR_VECT 0x41 | ||
| 25 | #define SSER0_INTR_VECT 0x42 | ||
| 26 | #define SSER1_INTR_VECT 0x43 | ||
| 27 | #define SER0_INTR_VECT 0x44 | ||
| 28 | #define SER1_INTR_VECT 0x45 | ||
| 29 | #define SER2_INTR_VECT 0x46 | ||
| 30 | #define SER3_INTR_VECT 0x47 | ||
| 31 | #define P21_INTR_VECT 0x48 | ||
| 32 | #define ETH0_INTR_VECT 0x49 | ||
| 33 | #define ETH1_INTR_VECT 0x4a | ||
| 34 | #define TIMER_INTR_VECT 0x4b | ||
| 35 | #define TIMER0_INTR_VECT TIMER_INTR_VECT | ||
| 36 | #define BIF_ARB_INTR_VECT 0x4c | ||
| 37 | #define BIF_DMA_INTR_VECT 0x4d | ||
| 38 | #define EXT_INTR_VECT 0x4e | ||
| 39 | #define IPI_INTR_VECT 0x4f | ||
| 40 | #define NBR_INTR_VECT 0x50 | ||
| 41 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h deleted file mode 100644 index aa65128ae1aa..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h +++ /dev/null | |||
| @@ -1,228 +0,0 @@ | |||
| 1 | #ifndef __intr_vect_defs_h | ||
| 2 | #define __intr_vect_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r | ||
| 7 | * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp | ||
| 8 | * last modfied: Mon Apr 11 16:08:03 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r | ||
| 11 | * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope intr_vect */ | ||
| 86 | |||
| 87 | #define STRIDE_intr_vect_rw_mask 0 | ||
| 88 | /* Register rw_mask, scope intr_vect, type rw */ | ||
| 89 | typedef struct { | ||
| 90 | unsigned int memarb : 1; | ||
| 91 | unsigned int gen_io : 1; | ||
| 92 | unsigned int iop0 : 1; | ||
| 93 | unsigned int iop1 : 1; | ||
| 94 | unsigned int iop2 : 1; | ||
| 95 | unsigned int iop3 : 1; | ||
| 96 | unsigned int dma0 : 1; | ||
| 97 | unsigned int dma1 : 1; | ||
| 98 | unsigned int dma2 : 1; | ||
| 99 | unsigned int dma3 : 1; | ||
| 100 | unsigned int dma4 : 1; | ||
| 101 | unsigned int dma5 : 1; | ||
| 102 | unsigned int dma6 : 1; | ||
| 103 | unsigned int dma7 : 1; | ||
| 104 | unsigned int dma8 : 1; | ||
| 105 | unsigned int dma9 : 1; | ||
| 106 | unsigned int ata : 1; | ||
| 107 | unsigned int sser0 : 1; | ||
| 108 | unsigned int sser1 : 1; | ||
| 109 | unsigned int ser0 : 1; | ||
| 110 | unsigned int ser1 : 1; | ||
| 111 | unsigned int ser2 : 1; | ||
| 112 | unsigned int ser3 : 1; | ||
| 113 | unsigned int p21 : 1; | ||
| 114 | unsigned int eth0 : 1; | ||
| 115 | unsigned int eth1 : 1; | ||
| 116 | unsigned int timer0 : 1; | ||
| 117 | unsigned int bif_arb : 1; | ||
| 118 | unsigned int bif_dma : 1; | ||
| 119 | unsigned int ext : 1; | ||
| 120 | unsigned int dummy1 : 2; | ||
| 121 | } reg_intr_vect_rw_mask; | ||
| 122 | #define REG_RD_ADDR_intr_vect_rw_mask 0 | ||
| 123 | #define REG_WR_ADDR_intr_vect_rw_mask 0 | ||
| 124 | |||
| 125 | #define STRIDE_intr_vect_r_vect 0 | ||
| 126 | /* Register r_vect, scope intr_vect, type r */ | ||
| 127 | typedef struct { | ||
| 128 | unsigned int memarb : 1; | ||
| 129 | unsigned int gen_io : 1; | ||
| 130 | unsigned int iop0 : 1; | ||
| 131 | unsigned int iop1 : 1; | ||
| 132 | unsigned int iop2 : 1; | ||
| 133 | unsigned int iop3 : 1; | ||
| 134 | unsigned int dma0 : 1; | ||
| 135 | unsigned int dma1 : 1; | ||
| 136 | unsigned int dma2 : 1; | ||
| 137 | unsigned int dma3 : 1; | ||
| 138 | unsigned int dma4 : 1; | ||
| 139 | unsigned int dma5 : 1; | ||
| 140 | unsigned int dma6 : 1; | ||
| 141 | unsigned int dma7 : 1; | ||
| 142 | unsigned int dma8 : 1; | ||
| 143 | unsigned int dma9 : 1; | ||
| 144 | unsigned int ata : 1; | ||
| 145 | unsigned int sser0 : 1; | ||
| 146 | unsigned int sser1 : 1; | ||
| 147 | unsigned int ser0 : 1; | ||
| 148 | unsigned int ser1 : 1; | ||
| 149 | unsigned int ser2 : 1; | ||
| 150 | unsigned int ser3 : 1; | ||
| 151 | unsigned int p21 : 1; | ||
| 152 | unsigned int eth0 : 1; | ||
| 153 | unsigned int eth1 : 1; | ||
| 154 | unsigned int timer : 1; | ||
| 155 | unsigned int bif_arb : 1; | ||
| 156 | unsigned int bif_dma : 1; | ||
| 157 | unsigned int ext : 1; | ||
| 158 | unsigned int dummy1 : 2; | ||
| 159 | } reg_intr_vect_r_vect; | ||
| 160 | #define REG_RD_ADDR_intr_vect_r_vect 4 | ||
| 161 | |||
| 162 | #define STRIDE_intr_vect_r_masked_vect 0 | ||
| 163 | /* Register r_masked_vect, scope intr_vect, type r */ | ||
| 164 | typedef struct { | ||
| 165 | unsigned int memarb : 1; | ||
| 166 | unsigned int gen_io : 1; | ||
| 167 | unsigned int iop0 : 1; | ||
| 168 | unsigned int iop1 : 1; | ||
| 169 | unsigned int iop2 : 1; | ||
| 170 | unsigned int iop3 : 1; | ||
| 171 | unsigned int dma0 : 1; | ||
| 172 | unsigned int dma1 : 1; | ||
| 173 | unsigned int dma2 : 1; | ||
| 174 | unsigned int dma3 : 1; | ||
| 175 | unsigned int dma4 : 1; | ||
| 176 | unsigned int dma5 : 1; | ||
| 177 | unsigned int dma6 : 1; | ||
| 178 | unsigned int dma7 : 1; | ||
| 179 | unsigned int dma8 : 1; | ||
| 180 | unsigned int dma9 : 1; | ||
| 181 | unsigned int ata : 1; | ||
| 182 | unsigned int sser0 : 1; | ||
| 183 | unsigned int sser1 : 1; | ||
| 184 | unsigned int ser0 : 1; | ||
| 185 | unsigned int ser1 : 1; | ||
| 186 | unsigned int ser2 : 1; | ||
| 187 | unsigned int ser3 : 1; | ||
| 188 | unsigned int p21 : 1; | ||
| 189 | unsigned int eth0 : 1; | ||
| 190 | unsigned int eth1 : 1; | ||
| 191 | unsigned int timer : 1; | ||
| 192 | unsigned int bif_arb : 1; | ||
| 193 | unsigned int bif_dma : 1; | ||
| 194 | unsigned int ext : 1; | ||
| 195 | unsigned int dummy1 : 2; | ||
| 196 | } reg_intr_vect_r_masked_vect; | ||
| 197 | #define REG_RD_ADDR_intr_vect_r_masked_vect 8 | ||
| 198 | |||
| 199 | /* Register r_nmi, scope intr_vect, type r */ | ||
| 200 | typedef struct { | ||
| 201 | unsigned int ext : 1; | ||
| 202 | unsigned int watchdog : 1; | ||
| 203 | unsigned int dummy1 : 30; | ||
| 204 | } reg_intr_vect_r_nmi; | ||
| 205 | #define REG_RD_ADDR_intr_vect_r_nmi 12 | ||
| 206 | |||
| 207 | /* Register r_guru, scope intr_vect, type r */ | ||
| 208 | typedef struct { | ||
| 209 | unsigned int jtag : 1; | ||
| 210 | unsigned int dummy1 : 31; | ||
| 211 | } reg_intr_vect_r_guru; | ||
| 212 | #define REG_RD_ADDR_intr_vect_r_guru 16 | ||
| 213 | |||
| 214 | /* Register rw_ipi, scope intr_vect, type rw */ | ||
| 215 | typedef struct | ||
| 216 | { | ||
| 217 | unsigned int vector; | ||
| 218 | } reg_intr_vect_rw_ipi; | ||
| 219 | #define REG_RD_ADDR_intr_vect_rw_ipi 20 | ||
| 220 | #define REG_WR_ADDR_intr_vect_rw_ipi 20 | ||
| 221 | |||
| 222 | /* Constants */ | ||
| 223 | enum { | ||
| 224 | regk_intr_vect_off = 0x00000000, | ||
| 225 | regk_intr_vect_on = 0x00000001, | ||
| 226 | regk_intr_vect_rw_mask_default = 0x00000000 | ||
| 227 | }; | ||
| 228 | #endif /* __intr_vect_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h deleted file mode 100644 index dcaaec4620ba..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h +++ /dev/null | |||
| @@ -1,205 +0,0 @@ | |||
| 1 | #ifndef __marb_bp_defs_h | ||
| 2 | #define __marb_bp_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Fri Nov 7 15:36:04 2003 | ||
| 9 | * | ||
| 10 | * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 11 | * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | /* C-code for register scope marb_bp */ | ||
| 75 | |||
| 76 | /* Register rw_first_addr, scope marb_bp, type rw */ | ||
| 77 | typedef unsigned int reg_marb_bp_rw_first_addr; | ||
| 78 | #define REG_RD_ADDR_marb_bp_rw_first_addr 0 | ||
| 79 | #define REG_WR_ADDR_marb_bp_rw_first_addr 0 | ||
| 80 | |||
| 81 | /* Register rw_last_addr, scope marb_bp, type rw */ | ||
| 82 | typedef unsigned int reg_marb_bp_rw_last_addr; | ||
| 83 | #define REG_RD_ADDR_marb_bp_rw_last_addr 4 | ||
| 84 | #define REG_WR_ADDR_marb_bp_rw_last_addr 4 | ||
| 85 | |||
| 86 | /* Register rw_op, scope marb_bp, type rw */ | ||
| 87 | typedef struct { | ||
| 88 | unsigned int read : 1; | ||
| 89 | unsigned int write : 1; | ||
| 90 | unsigned int read_excl : 1; | ||
| 91 | unsigned int pri_write : 1; | ||
| 92 | unsigned int us_read : 1; | ||
| 93 | unsigned int us_write : 1; | ||
| 94 | unsigned int us_read_excl : 1; | ||
| 95 | unsigned int us_pri_write : 1; | ||
| 96 | unsigned int dummy1 : 24; | ||
| 97 | } reg_marb_bp_rw_op; | ||
| 98 | #define REG_RD_ADDR_marb_bp_rw_op 8 | ||
| 99 | #define REG_WR_ADDR_marb_bp_rw_op 8 | ||
| 100 | |||
| 101 | /* Register rw_clients, scope marb_bp, type rw */ | ||
| 102 | typedef struct { | ||
| 103 | unsigned int dma0 : 1; | ||
| 104 | unsigned int dma1 : 1; | ||
| 105 | unsigned int dma2 : 1; | ||
| 106 | unsigned int dma3 : 1; | ||
| 107 | unsigned int dma4 : 1; | ||
| 108 | unsigned int dma5 : 1; | ||
| 109 | unsigned int dma6 : 1; | ||
| 110 | unsigned int dma7 : 1; | ||
| 111 | unsigned int dma8 : 1; | ||
| 112 | unsigned int dma9 : 1; | ||
| 113 | unsigned int cpui : 1; | ||
| 114 | unsigned int cpud : 1; | ||
| 115 | unsigned int iop : 1; | ||
| 116 | unsigned int slave : 1; | ||
| 117 | unsigned int dummy1 : 18; | ||
| 118 | } reg_marb_bp_rw_clients; | ||
| 119 | #define REG_RD_ADDR_marb_bp_rw_clients 12 | ||
| 120 | #define REG_WR_ADDR_marb_bp_rw_clients 12 | ||
| 121 | |||
| 122 | /* Register rw_options, scope marb_bp, type rw */ | ||
| 123 | typedef struct { | ||
| 124 | unsigned int wrap : 1; | ||
| 125 | unsigned int dummy1 : 31; | ||
| 126 | } reg_marb_bp_rw_options; | ||
| 127 | #define REG_RD_ADDR_marb_bp_rw_options 16 | ||
| 128 | #define REG_WR_ADDR_marb_bp_rw_options 16 | ||
| 129 | |||
| 130 | /* Register r_break_addr, scope marb_bp, type r */ | ||
| 131 | typedef unsigned int reg_marb_bp_r_break_addr; | ||
| 132 | #define REG_RD_ADDR_marb_bp_r_break_addr 20 | ||
| 133 | |||
| 134 | /* Register r_break_op, scope marb_bp, type r */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int read : 1; | ||
| 137 | unsigned int write : 1; | ||
| 138 | unsigned int read_excl : 1; | ||
| 139 | unsigned int pri_write : 1; | ||
| 140 | unsigned int us_read : 1; | ||
| 141 | unsigned int us_write : 1; | ||
| 142 | unsigned int us_read_excl : 1; | ||
| 143 | unsigned int us_pri_write : 1; | ||
| 144 | unsigned int dummy1 : 24; | ||
| 145 | } reg_marb_bp_r_break_op; | ||
| 146 | #define REG_RD_ADDR_marb_bp_r_break_op 24 | ||
| 147 | |||
| 148 | /* Register r_break_clients, scope marb_bp, type r */ | ||
| 149 | typedef struct { | ||
| 150 | unsigned int dma0 : 1; | ||
| 151 | unsigned int dma1 : 1; | ||
| 152 | unsigned int dma2 : 1; | ||
| 153 | unsigned int dma3 : 1; | ||
| 154 | unsigned int dma4 : 1; | ||
| 155 | unsigned int dma5 : 1; | ||
| 156 | unsigned int dma6 : 1; | ||
| 157 | unsigned int dma7 : 1; | ||
| 158 | unsigned int dma8 : 1; | ||
| 159 | unsigned int dma9 : 1; | ||
| 160 | unsigned int cpui : 1; | ||
| 161 | unsigned int cpud : 1; | ||
| 162 | unsigned int iop : 1; | ||
| 163 | unsigned int slave : 1; | ||
| 164 | unsigned int dummy1 : 18; | ||
| 165 | } reg_marb_bp_r_break_clients; | ||
| 166 | #define REG_RD_ADDR_marb_bp_r_break_clients 28 | ||
| 167 | |||
| 168 | /* Register r_break_first_client, scope marb_bp, type r */ | ||
| 169 | typedef struct { | ||
| 170 | unsigned int dma0 : 1; | ||
| 171 | unsigned int dma1 : 1; | ||
| 172 | unsigned int dma2 : 1; | ||
| 173 | unsigned int dma3 : 1; | ||
| 174 | unsigned int dma4 : 1; | ||
| 175 | unsigned int dma5 : 1; | ||
| 176 | unsigned int dma6 : 1; | ||
| 177 | unsigned int dma7 : 1; | ||
| 178 | unsigned int dma8 : 1; | ||
| 179 | unsigned int dma9 : 1; | ||
| 180 | unsigned int cpui : 1; | ||
| 181 | unsigned int cpud : 1; | ||
| 182 | unsigned int iop : 1; | ||
| 183 | unsigned int slave : 1; | ||
| 184 | unsigned int dummy1 : 18; | ||
| 185 | } reg_marb_bp_r_break_first_client; | ||
| 186 | #define REG_RD_ADDR_marb_bp_r_break_first_client 32 | ||
| 187 | |||
| 188 | /* Register r_break_size, scope marb_bp, type r */ | ||
| 189 | typedef unsigned int reg_marb_bp_r_break_size; | ||
| 190 | #define REG_RD_ADDR_marb_bp_r_break_size 36 | ||
| 191 | |||
| 192 | /* Register rw_ack, scope marb_bp, type rw */ | ||
| 193 | typedef unsigned int reg_marb_bp_rw_ack; | ||
| 194 | #define REG_RD_ADDR_marb_bp_rw_ack 40 | ||
| 195 | #define REG_WR_ADDR_marb_bp_rw_ack 40 | ||
| 196 | |||
| 197 | |||
| 198 | /* Constants */ | ||
| 199 | enum { | ||
| 200 | regk_marb_bp_no = 0x00000000, | ||
| 201 | regk_marb_bp_rw_op_default = 0x00000000, | ||
| 202 | regk_marb_bp_rw_options_default = 0x00000000, | ||
| 203 | regk_marb_bp_yes = 0x00000001 | ||
| 204 | }; | ||
| 205 | #endif /* __marb_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h deleted file mode 100644 index 254da0854986..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h +++ /dev/null | |||
| @@ -1,475 +0,0 @@ | |||
| 1 | #ifndef __marb_defs_h | ||
| 2 | #define __marb_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:12:16 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 11 | * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope marb */ | ||
| 86 | |||
| 87 | #define STRIDE_marb_rw_int_slots 4 | ||
| 88 | /* Register rw_int_slots, scope marb, type rw */ | ||
| 89 | typedef struct { | ||
| 90 | unsigned int owner : 4; | ||
| 91 | unsigned int dummy1 : 28; | ||
| 92 | } reg_marb_rw_int_slots; | ||
| 93 | #define REG_RD_ADDR_marb_rw_int_slots 0 | ||
| 94 | #define REG_WR_ADDR_marb_rw_int_slots 0 | ||
| 95 | |||
| 96 | #define STRIDE_marb_rw_ext_slots 4 | ||
| 97 | /* Register rw_ext_slots, scope marb, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int owner : 4; | ||
| 100 | unsigned int dummy1 : 28; | ||
| 101 | } reg_marb_rw_ext_slots; | ||
| 102 | #define REG_RD_ADDR_marb_rw_ext_slots 256 | ||
| 103 | #define REG_WR_ADDR_marb_rw_ext_slots 256 | ||
| 104 | |||
| 105 | #define STRIDE_marb_rw_regs_slots 4 | ||
| 106 | /* Register rw_regs_slots, scope marb, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int owner : 4; | ||
| 109 | unsigned int dummy1 : 28; | ||
| 110 | } reg_marb_rw_regs_slots; | ||
| 111 | #define REG_RD_ADDR_marb_rw_regs_slots 512 | ||
| 112 | #define REG_WR_ADDR_marb_rw_regs_slots 512 | ||
| 113 | |||
| 114 | /* Register rw_intr_mask, scope marb, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int bp0 : 1; | ||
| 117 | unsigned int bp1 : 1; | ||
| 118 | unsigned int bp2 : 1; | ||
| 119 | unsigned int bp3 : 1; | ||
| 120 | unsigned int dummy1 : 28; | ||
| 121 | } reg_marb_rw_intr_mask; | ||
| 122 | #define REG_RD_ADDR_marb_rw_intr_mask 528 | ||
| 123 | #define REG_WR_ADDR_marb_rw_intr_mask 528 | ||
| 124 | |||
| 125 | /* Register rw_ack_intr, scope marb, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int bp0 : 1; | ||
| 128 | unsigned int bp1 : 1; | ||
| 129 | unsigned int bp2 : 1; | ||
| 130 | unsigned int bp3 : 1; | ||
| 131 | unsigned int dummy1 : 28; | ||
| 132 | } reg_marb_rw_ack_intr; | ||
| 133 | #define REG_RD_ADDR_marb_rw_ack_intr 532 | ||
| 134 | #define REG_WR_ADDR_marb_rw_ack_intr 532 | ||
| 135 | |||
| 136 | /* Register r_intr, scope marb, type r */ | ||
| 137 | typedef struct { | ||
| 138 | unsigned int bp0 : 1; | ||
| 139 | unsigned int bp1 : 1; | ||
| 140 | unsigned int bp2 : 1; | ||
| 141 | unsigned int bp3 : 1; | ||
| 142 | unsigned int dummy1 : 28; | ||
| 143 | } reg_marb_r_intr; | ||
| 144 | #define REG_RD_ADDR_marb_r_intr 536 | ||
| 145 | |||
| 146 | /* Register r_masked_intr, scope marb, type r */ | ||
| 147 | typedef struct { | ||
| 148 | unsigned int bp0 : 1; | ||
| 149 | unsigned int bp1 : 1; | ||
| 150 | unsigned int bp2 : 1; | ||
| 151 | unsigned int bp3 : 1; | ||
| 152 | unsigned int dummy1 : 28; | ||
| 153 | } reg_marb_r_masked_intr; | ||
| 154 | #define REG_RD_ADDR_marb_r_masked_intr 540 | ||
| 155 | |||
| 156 | /* Register rw_stop_mask, scope marb, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int dma0 : 1; | ||
| 159 | unsigned int dma1 : 1; | ||
| 160 | unsigned int dma2 : 1; | ||
| 161 | unsigned int dma3 : 1; | ||
| 162 | unsigned int dma4 : 1; | ||
| 163 | unsigned int dma5 : 1; | ||
| 164 | unsigned int dma6 : 1; | ||
| 165 | unsigned int dma7 : 1; | ||
| 166 | unsigned int dma8 : 1; | ||
| 167 | unsigned int dma9 : 1; | ||
| 168 | unsigned int cpui : 1; | ||
| 169 | unsigned int cpud : 1; | ||
| 170 | unsigned int iop : 1; | ||
| 171 | unsigned int slave : 1; | ||
| 172 | unsigned int dummy1 : 18; | ||
| 173 | } reg_marb_rw_stop_mask; | ||
| 174 | #define REG_RD_ADDR_marb_rw_stop_mask 544 | ||
| 175 | #define REG_WR_ADDR_marb_rw_stop_mask 544 | ||
| 176 | |||
| 177 | /* Register r_stopped, scope marb, type r */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int dma0 : 1; | ||
| 180 | unsigned int dma1 : 1; | ||
| 181 | unsigned int dma2 : 1; | ||
| 182 | unsigned int dma3 : 1; | ||
| 183 | unsigned int dma4 : 1; | ||
| 184 | unsigned int dma5 : 1; | ||
| 185 | unsigned int dma6 : 1; | ||
| 186 | unsigned int dma7 : 1; | ||
| 187 | unsigned int dma8 : 1; | ||
| 188 | unsigned int dma9 : 1; | ||
| 189 | unsigned int cpui : 1; | ||
| 190 | unsigned int cpud : 1; | ||
| 191 | unsigned int iop : 1; | ||
| 192 | unsigned int slave : 1; | ||
| 193 | unsigned int dummy1 : 18; | ||
| 194 | } reg_marb_r_stopped; | ||
| 195 | #define REG_RD_ADDR_marb_r_stopped 548 | ||
| 196 | |||
| 197 | /* Register rw_no_snoop, scope marb, type rw */ | ||
| 198 | typedef struct { | ||
| 199 | unsigned int dma0 : 1; | ||
| 200 | unsigned int dma1 : 1; | ||
| 201 | unsigned int dma2 : 1; | ||
| 202 | unsigned int dma3 : 1; | ||
| 203 | unsigned int dma4 : 1; | ||
| 204 | unsigned int dma5 : 1; | ||
| 205 | unsigned int dma6 : 1; | ||
| 206 | unsigned int dma7 : 1; | ||
| 207 | unsigned int dma8 : 1; | ||
| 208 | unsigned int dma9 : 1; | ||
| 209 | unsigned int cpui : 1; | ||
| 210 | unsigned int cpud : 1; | ||
| 211 | unsigned int iop : 1; | ||
| 212 | unsigned int slave : 1; | ||
| 213 | unsigned int dummy1 : 18; | ||
| 214 | } reg_marb_rw_no_snoop; | ||
| 215 | #define REG_RD_ADDR_marb_rw_no_snoop 832 | ||
| 216 | #define REG_WR_ADDR_marb_rw_no_snoop 832 | ||
| 217 | |||
| 218 | /* Register rw_no_snoop_rq, scope marb, type rw */ | ||
| 219 | typedef struct { | ||
| 220 | unsigned int dummy1 : 10; | ||
| 221 | unsigned int cpui : 1; | ||
| 222 | unsigned int cpud : 1; | ||
| 223 | unsigned int dummy2 : 20; | ||
| 224 | } reg_marb_rw_no_snoop_rq; | ||
| 225 | #define REG_RD_ADDR_marb_rw_no_snoop_rq 836 | ||
| 226 | #define REG_WR_ADDR_marb_rw_no_snoop_rq 836 | ||
| 227 | |||
| 228 | |||
| 229 | /* Constants */ | ||
| 230 | enum { | ||
| 231 | regk_marb_cpud = 0x0000000b, | ||
| 232 | regk_marb_cpui = 0x0000000a, | ||
| 233 | regk_marb_dma0 = 0x00000000, | ||
| 234 | regk_marb_dma1 = 0x00000001, | ||
| 235 | regk_marb_dma2 = 0x00000002, | ||
| 236 | regk_marb_dma3 = 0x00000003, | ||
| 237 | regk_marb_dma4 = 0x00000004, | ||
| 238 | regk_marb_dma5 = 0x00000005, | ||
| 239 | regk_marb_dma6 = 0x00000006, | ||
| 240 | regk_marb_dma7 = 0x00000007, | ||
| 241 | regk_marb_dma8 = 0x00000008, | ||
| 242 | regk_marb_dma9 = 0x00000009, | ||
| 243 | regk_marb_iop = 0x0000000c, | ||
| 244 | regk_marb_no = 0x00000000, | ||
| 245 | regk_marb_r_stopped_default = 0x00000000, | ||
| 246 | regk_marb_rw_ext_slots_default = 0x00000000, | ||
| 247 | regk_marb_rw_ext_slots_size = 0x00000040, | ||
| 248 | regk_marb_rw_int_slots_default = 0x00000000, | ||
| 249 | regk_marb_rw_int_slots_size = 0x00000040, | ||
| 250 | regk_marb_rw_intr_mask_default = 0x00000000, | ||
| 251 | regk_marb_rw_no_snoop_default = 0x00000000, | ||
| 252 | regk_marb_rw_no_snoop_rq_default = 0x00000000, | ||
| 253 | regk_marb_rw_regs_slots_default = 0x00000000, | ||
| 254 | regk_marb_rw_regs_slots_size = 0x00000004, | ||
| 255 | regk_marb_rw_stop_mask_default = 0x00000000, | ||
| 256 | regk_marb_slave = 0x0000000d, | ||
| 257 | regk_marb_yes = 0x00000001 | ||
| 258 | }; | ||
| 259 | #endif /* __marb_defs_h */ | ||
| 260 | #ifndef __marb_bp_defs_h | ||
| 261 | #define __marb_bp_defs_h | ||
| 262 | |||
| 263 | /* | ||
| 264 | * This file is autogenerated from | ||
| 265 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 266 | * id: <not found> | ||
| 267 | * last modfied: Mon Apr 11 16:12:16 2005 | ||
| 268 | * | ||
| 269 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 270 | * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 271 | * Any changes here will be lost. | ||
| 272 | * | ||
| 273 | * -*- buffer-read-only: t -*- | ||
| 274 | */ | ||
| 275 | /* Main access macros */ | ||
| 276 | #ifndef REG_RD | ||
| 277 | #define REG_RD( scope, inst, reg ) \ | ||
| 278 | REG_READ( reg_##scope##_##reg, \ | ||
| 279 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 280 | #endif | ||
| 281 | |||
| 282 | #ifndef REG_WR | ||
| 283 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 284 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 285 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 286 | #endif | ||
| 287 | |||
| 288 | #ifndef REG_RD_VECT | ||
| 289 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 290 | REG_READ( reg_##scope##_##reg, \ | ||
| 291 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 292 | (index) * STRIDE_##scope##_##reg ) | ||
| 293 | #endif | ||
| 294 | |||
| 295 | #ifndef REG_WR_VECT | ||
| 296 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 297 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 298 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 299 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 300 | #endif | ||
| 301 | |||
| 302 | #ifndef REG_RD_INT | ||
| 303 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 304 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 305 | #endif | ||
| 306 | |||
| 307 | #ifndef REG_WR_INT | ||
| 308 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 309 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 310 | #endif | ||
| 311 | |||
| 312 | #ifndef REG_RD_INT_VECT | ||
| 313 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 314 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 315 | (index) * STRIDE_##scope##_##reg ) | ||
| 316 | #endif | ||
| 317 | |||
| 318 | #ifndef REG_WR_INT_VECT | ||
| 319 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 320 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 321 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 322 | #endif | ||
| 323 | |||
| 324 | #ifndef REG_TYPE_CONV | ||
| 325 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 326 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #ifndef reg_page_size | ||
| 330 | #define reg_page_size 8192 | ||
| 331 | #endif | ||
| 332 | |||
| 333 | #ifndef REG_ADDR | ||
| 334 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 335 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 336 | #endif | ||
| 337 | |||
| 338 | #ifndef REG_ADDR_VECT | ||
| 339 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 340 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 341 | (index) * STRIDE_##scope##_##reg ) | ||
| 342 | #endif | ||
| 343 | |||
| 344 | /* C-code for register scope marb_bp */ | ||
| 345 | |||
| 346 | /* Register rw_first_addr, scope marb_bp, type rw */ | ||
| 347 | typedef unsigned int reg_marb_bp_rw_first_addr; | ||
| 348 | #define REG_RD_ADDR_marb_bp_rw_first_addr 0 | ||
| 349 | #define REG_WR_ADDR_marb_bp_rw_first_addr 0 | ||
| 350 | |||
| 351 | /* Register rw_last_addr, scope marb_bp, type rw */ | ||
| 352 | typedef unsigned int reg_marb_bp_rw_last_addr; | ||
| 353 | #define REG_RD_ADDR_marb_bp_rw_last_addr 4 | ||
| 354 | #define REG_WR_ADDR_marb_bp_rw_last_addr 4 | ||
| 355 | |||
| 356 | /* Register rw_op, scope marb_bp, type rw */ | ||
| 357 | typedef struct { | ||
| 358 | unsigned int rd : 1; | ||
| 359 | unsigned int wr : 1; | ||
| 360 | unsigned int rd_excl : 1; | ||
| 361 | unsigned int pri_wr : 1; | ||
| 362 | unsigned int us_rd : 1; | ||
| 363 | unsigned int us_wr : 1; | ||
| 364 | unsigned int us_rd_excl : 1; | ||
| 365 | unsigned int us_pri_wr : 1; | ||
| 366 | unsigned int dummy1 : 24; | ||
| 367 | } reg_marb_bp_rw_op; | ||
| 368 | #define REG_RD_ADDR_marb_bp_rw_op 8 | ||
| 369 | #define REG_WR_ADDR_marb_bp_rw_op 8 | ||
| 370 | |||
| 371 | /* Register rw_clients, scope marb_bp, type rw */ | ||
| 372 | typedef struct { | ||
| 373 | unsigned int dma0 : 1; | ||
| 374 | unsigned int dma1 : 1; | ||
| 375 | unsigned int dma2 : 1; | ||
| 376 | unsigned int dma3 : 1; | ||
| 377 | unsigned int dma4 : 1; | ||
| 378 | unsigned int dma5 : 1; | ||
| 379 | unsigned int dma6 : 1; | ||
| 380 | unsigned int dma7 : 1; | ||
| 381 | unsigned int dma8 : 1; | ||
| 382 | unsigned int dma9 : 1; | ||
| 383 | unsigned int cpui : 1; | ||
| 384 | unsigned int cpud : 1; | ||
| 385 | unsigned int iop : 1; | ||
| 386 | unsigned int slave : 1; | ||
| 387 | unsigned int dummy1 : 18; | ||
| 388 | } reg_marb_bp_rw_clients; | ||
| 389 | #define REG_RD_ADDR_marb_bp_rw_clients 12 | ||
| 390 | #define REG_WR_ADDR_marb_bp_rw_clients 12 | ||
| 391 | |||
| 392 | /* Register rw_options, scope marb_bp, type rw */ | ||
| 393 | typedef struct { | ||
| 394 | unsigned int wrap : 1; | ||
| 395 | unsigned int dummy1 : 31; | ||
| 396 | } reg_marb_bp_rw_options; | ||
| 397 | #define REG_RD_ADDR_marb_bp_rw_options 16 | ||
| 398 | #define REG_WR_ADDR_marb_bp_rw_options 16 | ||
| 399 | |||
| 400 | /* Register r_brk_addr, scope marb_bp, type r */ | ||
| 401 | typedef unsigned int reg_marb_bp_r_brk_addr; | ||
| 402 | #define REG_RD_ADDR_marb_bp_r_brk_addr 20 | ||
| 403 | |||
| 404 | /* Register r_brk_op, scope marb_bp, type r */ | ||
| 405 | typedef struct { | ||
| 406 | unsigned int rd : 1; | ||
| 407 | unsigned int wr : 1; | ||
| 408 | unsigned int rd_excl : 1; | ||
| 409 | unsigned int pri_wr : 1; | ||
| 410 | unsigned int us_rd : 1; | ||
| 411 | unsigned int us_wr : 1; | ||
| 412 | unsigned int us_rd_excl : 1; | ||
| 413 | unsigned int us_pri_wr : 1; | ||
| 414 | unsigned int dummy1 : 24; | ||
| 415 | } reg_marb_bp_r_brk_op; | ||
| 416 | #define REG_RD_ADDR_marb_bp_r_brk_op 24 | ||
| 417 | |||
| 418 | /* Register r_brk_clients, scope marb_bp, type r */ | ||
| 419 | typedef struct { | ||
| 420 | unsigned int dma0 : 1; | ||
| 421 | unsigned int dma1 : 1; | ||
| 422 | unsigned int dma2 : 1; | ||
| 423 | unsigned int dma3 : 1; | ||
| 424 | unsigned int dma4 : 1; | ||
| 425 | unsigned int dma5 : 1; | ||
| 426 | unsigned int dma6 : 1; | ||
| 427 | unsigned int dma7 : 1; | ||
| 428 | unsigned int dma8 : 1; | ||
| 429 | unsigned int dma9 : 1; | ||
| 430 | unsigned int cpui : 1; | ||
| 431 | unsigned int cpud : 1; | ||
| 432 | unsigned int iop : 1; | ||
| 433 | unsigned int slave : 1; | ||
| 434 | unsigned int dummy1 : 18; | ||
| 435 | } reg_marb_bp_r_brk_clients; | ||
| 436 | #define REG_RD_ADDR_marb_bp_r_brk_clients 28 | ||
| 437 | |||
| 438 | /* Register r_brk_first_client, scope marb_bp, type r */ | ||
| 439 | typedef struct { | ||
| 440 | unsigned int dma0 : 1; | ||
| 441 | unsigned int dma1 : 1; | ||
| 442 | unsigned int dma2 : 1; | ||
| 443 | unsigned int dma3 : 1; | ||
| 444 | unsigned int dma4 : 1; | ||
| 445 | unsigned int dma5 : 1; | ||
| 446 | unsigned int dma6 : 1; | ||
| 447 | unsigned int dma7 : 1; | ||
| 448 | unsigned int dma8 : 1; | ||
| 449 | unsigned int dma9 : 1; | ||
| 450 | unsigned int cpui : 1; | ||
| 451 | unsigned int cpud : 1; | ||
| 452 | unsigned int iop : 1; | ||
| 453 | unsigned int slave : 1; | ||
| 454 | unsigned int dummy1 : 18; | ||
| 455 | } reg_marb_bp_r_brk_first_client; | ||
| 456 | #define REG_RD_ADDR_marb_bp_r_brk_first_client 32 | ||
| 457 | |||
| 458 | /* Register r_brk_size, scope marb_bp, type r */ | ||
| 459 | typedef unsigned int reg_marb_bp_r_brk_size; | ||
| 460 | #define REG_RD_ADDR_marb_bp_r_brk_size 36 | ||
| 461 | |||
| 462 | /* Register rw_ack, scope marb_bp, type rw */ | ||
| 463 | typedef unsigned int reg_marb_bp_rw_ack; | ||
| 464 | #define REG_RD_ADDR_marb_bp_rw_ack 40 | ||
| 465 | #define REG_WR_ADDR_marb_bp_rw_ack 40 | ||
| 466 | |||
| 467 | |||
| 468 | /* Constants */ | ||
| 469 | enum { | ||
| 470 | regk_marb_bp_no = 0x00000000, | ||
| 471 | regk_marb_bp_rw_op_default = 0x00000000, | ||
| 472 | regk_marb_bp_rw_options_default = 0x00000000, | ||
| 473 | regk_marb_bp_yes = 0x00000001 | ||
| 474 | }; | ||
| 475 | #endif /* __marb_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h deleted file mode 100644 index 751eab5f191c..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h +++ /dev/null | |||
| @@ -1,357 +0,0 @@ | |||
| 1 | #ifndef __pinmux_defs_h | ||
| 2 | #define __pinmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 7 | * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:11 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 11 | * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope pinmux */ | ||
| 86 | |||
| 87 | /* Register rw_pa, scope pinmux, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int pa0 : 1; | ||
| 90 | unsigned int pa1 : 1; | ||
| 91 | unsigned int pa2 : 1; | ||
| 92 | unsigned int pa3 : 1; | ||
| 93 | unsigned int pa4 : 1; | ||
| 94 | unsigned int pa5 : 1; | ||
| 95 | unsigned int pa6 : 1; | ||
| 96 | unsigned int pa7 : 1; | ||
| 97 | unsigned int csp2_n : 1; | ||
| 98 | unsigned int csp3_n : 1; | ||
| 99 | unsigned int csp5_n : 1; | ||
| 100 | unsigned int csp6_n : 1; | ||
| 101 | unsigned int hsh4 : 1; | ||
| 102 | unsigned int hsh5 : 1; | ||
| 103 | unsigned int hsh6 : 1; | ||
| 104 | unsigned int hsh7 : 1; | ||
| 105 | unsigned int dummy1 : 16; | ||
| 106 | } reg_pinmux_rw_pa; | ||
| 107 | #define REG_RD_ADDR_pinmux_rw_pa 0 | ||
| 108 | #define REG_WR_ADDR_pinmux_rw_pa 0 | ||
| 109 | |||
| 110 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int ser1 : 1; | ||
| 113 | unsigned int ser2 : 1; | ||
| 114 | unsigned int ser3 : 1; | ||
| 115 | unsigned int sser0 : 1; | ||
| 116 | unsigned int sser1 : 1; | ||
| 117 | unsigned int ata0 : 1; | ||
| 118 | unsigned int ata1 : 1; | ||
| 119 | unsigned int ata2 : 1; | ||
| 120 | unsigned int ata3 : 1; | ||
| 121 | unsigned int ata : 1; | ||
| 122 | unsigned int eth1 : 1; | ||
| 123 | unsigned int eth1_mgm : 1; | ||
| 124 | unsigned int timer : 1; | ||
| 125 | unsigned int p21 : 1; | ||
| 126 | unsigned int dummy1 : 18; | ||
| 127 | } reg_pinmux_rw_hwprot; | ||
| 128 | #define REG_RD_ADDR_pinmux_rw_hwprot 4 | ||
| 129 | #define REG_WR_ADDR_pinmux_rw_hwprot 4 | ||
| 130 | |||
| 131 | /* Register rw_pb_gio, scope pinmux, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int pb0 : 1; | ||
| 134 | unsigned int pb1 : 1; | ||
| 135 | unsigned int pb2 : 1; | ||
| 136 | unsigned int pb3 : 1; | ||
| 137 | unsigned int pb4 : 1; | ||
| 138 | unsigned int pb5 : 1; | ||
| 139 | unsigned int pb6 : 1; | ||
| 140 | unsigned int pb7 : 1; | ||
| 141 | unsigned int pb8 : 1; | ||
| 142 | unsigned int pb9 : 1; | ||
| 143 | unsigned int pb10 : 1; | ||
| 144 | unsigned int pb11 : 1; | ||
| 145 | unsigned int pb12 : 1; | ||
| 146 | unsigned int pb13 : 1; | ||
| 147 | unsigned int pb14 : 1; | ||
| 148 | unsigned int pb15 : 1; | ||
| 149 | unsigned int pb16 : 1; | ||
| 150 | unsigned int pb17 : 1; | ||
| 151 | unsigned int dummy1 : 14; | ||
| 152 | } reg_pinmux_rw_pb_gio; | ||
| 153 | #define REG_RD_ADDR_pinmux_rw_pb_gio 8 | ||
| 154 | #define REG_WR_ADDR_pinmux_rw_pb_gio 8 | ||
| 155 | |||
| 156 | /* Register rw_pb_iop, scope pinmux, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int pb0 : 1; | ||
| 159 | unsigned int pb1 : 1; | ||
| 160 | unsigned int pb2 : 1; | ||
| 161 | unsigned int pb3 : 1; | ||
| 162 | unsigned int pb4 : 1; | ||
| 163 | unsigned int pb5 : 1; | ||
| 164 | unsigned int pb6 : 1; | ||
| 165 | unsigned int pb7 : 1; | ||
| 166 | unsigned int pb8 : 1; | ||
| 167 | unsigned int pb9 : 1; | ||
| 168 | unsigned int pb10 : 1; | ||
| 169 | unsigned int pb11 : 1; | ||
| 170 | unsigned int pb12 : 1; | ||
| 171 | unsigned int pb13 : 1; | ||
| 172 | unsigned int pb14 : 1; | ||
| 173 | unsigned int pb15 : 1; | ||
| 174 | unsigned int pb16 : 1; | ||
| 175 | unsigned int pb17 : 1; | ||
| 176 | unsigned int dummy1 : 14; | ||
| 177 | } reg_pinmux_rw_pb_iop; | ||
| 178 | #define REG_RD_ADDR_pinmux_rw_pb_iop 12 | ||
| 179 | #define REG_WR_ADDR_pinmux_rw_pb_iop 12 | ||
| 180 | |||
| 181 | /* Register rw_pc_gio, scope pinmux, type rw */ | ||
| 182 | typedef struct { | ||
| 183 | unsigned int pc0 : 1; | ||
| 184 | unsigned int pc1 : 1; | ||
| 185 | unsigned int pc2 : 1; | ||
| 186 | unsigned int pc3 : 1; | ||
| 187 | unsigned int pc4 : 1; | ||
| 188 | unsigned int pc5 : 1; | ||
| 189 | unsigned int pc6 : 1; | ||
| 190 | unsigned int pc7 : 1; | ||
| 191 | unsigned int pc8 : 1; | ||
| 192 | unsigned int pc9 : 1; | ||
| 193 | unsigned int pc10 : 1; | ||
| 194 | unsigned int pc11 : 1; | ||
| 195 | unsigned int pc12 : 1; | ||
| 196 | unsigned int pc13 : 1; | ||
| 197 | unsigned int pc14 : 1; | ||
| 198 | unsigned int pc15 : 1; | ||
| 199 | unsigned int pc16 : 1; | ||
| 200 | unsigned int pc17 : 1; | ||
| 201 | unsigned int dummy1 : 14; | ||
| 202 | } reg_pinmux_rw_pc_gio; | ||
| 203 | #define REG_RD_ADDR_pinmux_rw_pc_gio 16 | ||
| 204 | #define REG_WR_ADDR_pinmux_rw_pc_gio 16 | ||
| 205 | |||
| 206 | /* Register rw_pc_iop, scope pinmux, type rw */ | ||
| 207 | typedef struct { | ||
| 208 | unsigned int pc0 : 1; | ||
| 209 | unsigned int pc1 : 1; | ||
| 210 | unsigned int pc2 : 1; | ||
| 211 | unsigned int pc3 : 1; | ||
| 212 | unsigned int pc4 : 1; | ||
| 213 | unsigned int pc5 : 1; | ||
| 214 | unsigned int pc6 : 1; | ||
| 215 | unsigned int pc7 : 1; | ||
| 216 | unsigned int pc8 : 1; | ||
| 217 | unsigned int pc9 : 1; | ||
| 218 | unsigned int pc10 : 1; | ||
| 219 | unsigned int pc11 : 1; | ||
| 220 | unsigned int pc12 : 1; | ||
| 221 | unsigned int pc13 : 1; | ||
| 222 | unsigned int pc14 : 1; | ||
| 223 | unsigned int pc15 : 1; | ||
| 224 | unsigned int pc16 : 1; | ||
| 225 | unsigned int pc17 : 1; | ||
| 226 | unsigned int dummy1 : 14; | ||
| 227 | } reg_pinmux_rw_pc_iop; | ||
| 228 | #define REG_RD_ADDR_pinmux_rw_pc_iop 20 | ||
| 229 | #define REG_WR_ADDR_pinmux_rw_pc_iop 20 | ||
| 230 | |||
| 231 | /* Register rw_pd_gio, scope pinmux, type rw */ | ||
| 232 | typedef struct { | ||
| 233 | unsigned int pd0 : 1; | ||
| 234 | unsigned int pd1 : 1; | ||
| 235 | unsigned int pd2 : 1; | ||
| 236 | unsigned int pd3 : 1; | ||
| 237 | unsigned int pd4 : 1; | ||
| 238 | unsigned int pd5 : 1; | ||
| 239 | unsigned int pd6 : 1; | ||
| 240 | unsigned int pd7 : 1; | ||
| 241 | unsigned int pd8 : 1; | ||
| 242 | unsigned int pd9 : 1; | ||
| 243 | unsigned int pd10 : 1; | ||
| 244 | unsigned int pd11 : 1; | ||
| 245 | unsigned int pd12 : 1; | ||
| 246 | unsigned int pd13 : 1; | ||
| 247 | unsigned int pd14 : 1; | ||
| 248 | unsigned int pd15 : 1; | ||
| 249 | unsigned int pd16 : 1; | ||
| 250 | unsigned int pd17 : 1; | ||
| 251 | unsigned int dummy1 : 14; | ||
| 252 | } reg_pinmux_rw_pd_gio; | ||
| 253 | #define REG_RD_ADDR_pinmux_rw_pd_gio 24 | ||
| 254 | #define REG_WR_ADDR_pinmux_rw_pd_gio 24 | ||
| 255 | |||
| 256 | /* Register rw_pd_iop, scope pinmux, type rw */ | ||
| 257 | typedef struct { | ||
| 258 | unsigned int pd0 : 1; | ||
| 259 | unsigned int pd1 : 1; | ||
| 260 | unsigned int pd2 : 1; | ||
| 261 | unsigned int pd3 : 1; | ||
| 262 | unsigned int pd4 : 1; | ||
| 263 | unsigned int pd5 : 1; | ||
| 264 | unsigned int pd6 : 1; | ||
| 265 | unsigned int pd7 : 1; | ||
| 266 | unsigned int pd8 : 1; | ||
| 267 | unsigned int pd9 : 1; | ||
| 268 | unsigned int pd10 : 1; | ||
| 269 | unsigned int pd11 : 1; | ||
| 270 | unsigned int pd12 : 1; | ||
| 271 | unsigned int pd13 : 1; | ||
| 272 | unsigned int pd14 : 1; | ||
| 273 | unsigned int pd15 : 1; | ||
| 274 | unsigned int pd16 : 1; | ||
| 275 | unsigned int pd17 : 1; | ||
| 276 | unsigned int dummy1 : 14; | ||
| 277 | } reg_pinmux_rw_pd_iop; | ||
| 278 | #define REG_RD_ADDR_pinmux_rw_pd_iop 28 | ||
| 279 | #define REG_WR_ADDR_pinmux_rw_pd_iop 28 | ||
| 280 | |||
| 281 | /* Register rw_pe_gio, scope pinmux, type rw */ | ||
| 282 | typedef struct { | ||
| 283 | unsigned int pe0 : 1; | ||
| 284 | unsigned int pe1 : 1; | ||
| 285 | unsigned int pe2 : 1; | ||
| 286 | unsigned int pe3 : 1; | ||
| 287 | unsigned int pe4 : 1; | ||
| 288 | unsigned int pe5 : 1; | ||
| 289 | unsigned int pe6 : 1; | ||
| 290 | unsigned int pe7 : 1; | ||
| 291 | unsigned int pe8 : 1; | ||
| 292 | unsigned int pe9 : 1; | ||
| 293 | unsigned int pe10 : 1; | ||
| 294 | unsigned int pe11 : 1; | ||
| 295 | unsigned int pe12 : 1; | ||
| 296 | unsigned int pe13 : 1; | ||
| 297 | unsigned int pe14 : 1; | ||
| 298 | unsigned int pe15 : 1; | ||
| 299 | unsigned int pe16 : 1; | ||
| 300 | unsigned int pe17 : 1; | ||
| 301 | unsigned int dummy1 : 14; | ||
| 302 | } reg_pinmux_rw_pe_gio; | ||
| 303 | #define REG_RD_ADDR_pinmux_rw_pe_gio 32 | ||
| 304 | #define REG_WR_ADDR_pinmux_rw_pe_gio 32 | ||
| 305 | |||
| 306 | /* Register rw_pe_iop, scope pinmux, type rw */ | ||
| 307 | typedef struct { | ||
| 308 | unsigned int pe0 : 1; | ||
| 309 | unsigned int pe1 : 1; | ||
| 310 | unsigned int pe2 : 1; | ||
| 311 | unsigned int pe3 : 1; | ||
| 312 | unsigned int pe4 : 1; | ||
| 313 | unsigned int pe5 : 1; | ||
| 314 | unsigned int pe6 : 1; | ||
| 315 | unsigned int pe7 : 1; | ||
| 316 | unsigned int pe8 : 1; | ||
| 317 | unsigned int pe9 : 1; | ||
| 318 | unsigned int pe10 : 1; | ||
| 319 | unsigned int pe11 : 1; | ||
| 320 | unsigned int pe12 : 1; | ||
| 321 | unsigned int pe13 : 1; | ||
| 322 | unsigned int pe14 : 1; | ||
| 323 | unsigned int pe15 : 1; | ||
| 324 | unsigned int pe16 : 1; | ||
| 325 | unsigned int pe17 : 1; | ||
| 326 | unsigned int dummy1 : 14; | ||
| 327 | } reg_pinmux_rw_pe_iop; | ||
| 328 | #define REG_RD_ADDR_pinmux_rw_pe_iop 36 | ||
| 329 | #define REG_WR_ADDR_pinmux_rw_pe_iop 36 | ||
| 330 | |||
| 331 | /* Register rw_usb_phy, scope pinmux, type rw */ | ||
| 332 | typedef struct { | ||
| 333 | unsigned int en_usb0 : 1; | ||
| 334 | unsigned int en_usb1 : 1; | ||
| 335 | unsigned int dummy1 : 30; | ||
| 336 | } reg_pinmux_rw_usb_phy; | ||
| 337 | #define REG_RD_ADDR_pinmux_rw_usb_phy 40 | ||
| 338 | #define REG_WR_ADDR_pinmux_rw_usb_phy 40 | ||
| 339 | |||
| 340 | |||
| 341 | /* Constants */ | ||
| 342 | enum { | ||
| 343 | regk_pinmux_no = 0x00000000, | ||
| 344 | regk_pinmux_rw_hwprot_default = 0x00000000, | ||
| 345 | regk_pinmux_rw_pa_default = 0x00000000, | ||
| 346 | regk_pinmux_rw_pb_gio_default = 0x00000000, | ||
| 347 | regk_pinmux_rw_pb_iop_default = 0x00000000, | ||
| 348 | regk_pinmux_rw_pc_gio_default = 0x00000000, | ||
| 349 | regk_pinmux_rw_pc_iop_default = 0x00000000, | ||
| 350 | regk_pinmux_rw_pd_gio_default = 0x00000000, | ||
| 351 | regk_pinmux_rw_pd_iop_default = 0x00000000, | ||
| 352 | regk_pinmux_rw_pe_gio_default = 0x00000000, | ||
| 353 | regk_pinmux_rw_pe_iop_default = 0x00000000, | ||
| 354 | regk_pinmux_rw_usb_phy_default = 0x00000000, | ||
| 355 | regk_pinmux_yes = 0x00000001 | ||
| 356 | }; | ||
| 357 | #endif /* __pinmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h deleted file mode 100644 index 4146973a58b3..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h +++ /dev/null | |||
| @@ -1,104 +0,0 @@ | |||
| 1 | #ifndef __reg_map_h | ||
| 2 | #define __reg_map_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../mod/fakereg.rmap | ||
| 7 | * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp | ||
| 8 | * last modified: Wed Feb 11 20:53:25 2004 | ||
| 9 | * file: ../../rtl/global.rmap | ||
| 10 | * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp | ||
| 11 | * last modified: Mon Aug 18 17:08:23 2003 | ||
| 12 | * file: ../../mod/modreg.rmap | ||
| 13 | * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp | ||
| 14 | * last modified: Fri Feb 20 16:40:04 2004 | ||
| 15 | * | ||
| 16 | * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap | ||
| 17 | * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 18 | * Any changes here will be lost. | ||
| 19 | * | ||
| 20 | * -*- buffer-read-only: t -*- | ||
| 21 | */ | ||
| 22 | typedef enum { | ||
| 23 | regi_ata = 0xb0032000, | ||
| 24 | regi_bif_core = 0xb0014000, | ||
| 25 | regi_bif_dma = 0xb0016000, | ||
| 26 | regi_bif_slave = 0xb0018000, | ||
| 27 | regi_config = 0xb003c000, | ||
| 28 | regi_dma0 = 0xb0000000, | ||
| 29 | regi_dma1 = 0xb0002000, | ||
| 30 | regi_dma2 = 0xb0004000, | ||
| 31 | regi_dma3 = 0xb0006000, | ||
| 32 | regi_dma4 = 0xb0008000, | ||
| 33 | regi_dma5 = 0xb000a000, | ||
| 34 | regi_dma6 = 0xb000c000, | ||
| 35 | regi_dma7 = 0xb000e000, | ||
| 36 | regi_dma8 = 0xb0010000, | ||
| 37 | regi_dma9 = 0xb0012000, | ||
| 38 | regi_eth0 = 0xb0034000, | ||
| 39 | regi_eth1 = 0xb0036000, | ||
| 40 | regi_gio = 0xb001a000, | ||
| 41 | regi_iop = 0xb0020000, | ||
| 42 | regi_iop_version = 0xb0020000, | ||
| 43 | regi_iop_fifo_in0_extra = 0xb0020040, | ||
| 44 | regi_iop_fifo_in1_extra = 0xb0020080, | ||
| 45 | regi_iop_fifo_out0_extra = 0xb00200c0, | ||
| 46 | regi_iop_fifo_out1_extra = 0xb0020100, | ||
| 47 | regi_iop_trigger_grp0 = 0xb0020140, | ||
| 48 | regi_iop_trigger_grp1 = 0xb0020180, | ||
| 49 | regi_iop_trigger_grp2 = 0xb00201c0, | ||
| 50 | regi_iop_trigger_grp3 = 0xb0020200, | ||
| 51 | regi_iop_trigger_grp4 = 0xb0020240, | ||
| 52 | regi_iop_trigger_grp5 = 0xb0020280, | ||
| 53 | regi_iop_trigger_grp6 = 0xb00202c0, | ||
| 54 | regi_iop_trigger_grp7 = 0xb0020300, | ||
| 55 | regi_iop_crc_par0 = 0xb0020380, | ||
| 56 | regi_iop_crc_par1 = 0xb0020400, | ||
| 57 | regi_iop_dmc_in0 = 0xb0020480, | ||
| 58 | regi_iop_dmc_in1 = 0xb0020500, | ||
| 59 | regi_iop_dmc_out0 = 0xb0020580, | ||
| 60 | regi_iop_dmc_out1 = 0xb0020600, | ||
| 61 | regi_iop_fifo_in0 = 0xb0020680, | ||
| 62 | regi_iop_fifo_in1 = 0xb0020700, | ||
| 63 | regi_iop_fifo_out0 = 0xb0020780, | ||
| 64 | regi_iop_fifo_out1 = 0xb0020800, | ||
| 65 | regi_iop_scrc_in0 = 0xb0020880, | ||
| 66 | regi_iop_scrc_in1 = 0xb0020900, | ||
| 67 | regi_iop_scrc_out0 = 0xb0020980, | ||
| 68 | regi_iop_scrc_out1 = 0xb0020a00, | ||
| 69 | regi_iop_timer_grp0 = 0xb0020a80, | ||
| 70 | regi_iop_timer_grp1 = 0xb0020b00, | ||
| 71 | regi_iop_timer_grp2 = 0xb0020b80, | ||
| 72 | regi_iop_timer_grp3 = 0xb0020c00, | ||
| 73 | regi_iop_sap_in = 0xb0020d00, | ||
| 74 | regi_iop_sap_out = 0xb0020e00, | ||
| 75 | regi_iop_spu0 = 0xb0020f00, | ||
| 76 | regi_iop_spu1 = 0xb0021000, | ||
| 77 | regi_iop_sw_cfg = 0xb0021100, | ||
| 78 | regi_iop_sw_cpu = 0xb0021200, | ||
| 79 | regi_iop_sw_mpu = 0xb0021300, | ||
| 80 | regi_iop_sw_spu0 = 0xb0021400, | ||
| 81 | regi_iop_sw_spu1 = 0xb0021500, | ||
| 82 | regi_iop_mpu = 0xb0021600, | ||
| 83 | regi_irq = 0xb001c000, | ||
| 84 | regi_irq2 = 0xb005c000, | ||
| 85 | regi_marb = 0xb003e000, | ||
| 86 | regi_marb_bp0 = 0xb003e240, | ||
| 87 | regi_marb_bp1 = 0xb003e280, | ||
| 88 | regi_marb_bp2 = 0xb003e2c0, | ||
| 89 | regi_marb_bp3 = 0xb003e300, | ||
| 90 | regi_pinmux = 0xb0038000, | ||
| 91 | regi_ser0 = 0xb0026000, | ||
| 92 | regi_ser1 = 0xb0028000, | ||
| 93 | regi_ser2 = 0xb002a000, | ||
| 94 | regi_ser3 = 0xb002c000, | ||
| 95 | regi_sser0 = 0xb0022000, | ||
| 96 | regi_sser1 = 0xb0024000, | ||
| 97 | regi_strcop = 0xb0030000, | ||
| 98 | regi_strmux = 0xb003a000, | ||
| 99 | regi_timer = 0xb001e000, | ||
| 100 | regi_timer0 = 0xb001e000, | ||
| 101 | regi_timer2 = 0xb005e000, | ||
| 102 | regi_trace = 0xb0040000, | ||
| 103 | } reg_scope_instances; | ||
| 104 | #endif /* __reg_map_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h deleted file mode 100644 index cbfaa867829e..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h +++ /dev/null | |||
| @@ -1,127 +0,0 @@ | |||
| 1 | #ifndef __strmux_defs_h | ||
| 2 | #define __strmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/strmux/rtl/guinness/strmux_regs.r | ||
| 7 | * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:43 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r | ||
| 11 | * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope strmux */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope strmux, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int dma0 : 3; | ||
| 90 | unsigned int dma1 : 3; | ||
| 91 | unsigned int dma2 : 3; | ||
| 92 | unsigned int dma3 : 3; | ||
| 93 | unsigned int dma4 : 3; | ||
| 94 | unsigned int dma5 : 3; | ||
| 95 | unsigned int dma6 : 3; | ||
| 96 | unsigned int dma7 : 3; | ||
| 97 | unsigned int dma8 : 3; | ||
| 98 | unsigned int dma9 : 3; | ||
| 99 | unsigned int dummy1 : 2; | ||
| 100 | } reg_strmux_rw_cfg; | ||
| 101 | #define REG_RD_ADDR_strmux_rw_cfg 0 | ||
| 102 | #define REG_WR_ADDR_strmux_rw_cfg 0 | ||
| 103 | |||
| 104 | |||
| 105 | /* Constants */ | ||
| 106 | enum { | ||
| 107 | regk_strmux_ata = 0x00000003, | ||
| 108 | regk_strmux_eth0 = 0x00000001, | ||
| 109 | regk_strmux_eth1 = 0x00000004, | ||
| 110 | regk_strmux_ext0 = 0x00000001, | ||
| 111 | regk_strmux_ext1 = 0x00000001, | ||
| 112 | regk_strmux_ext2 = 0x00000001, | ||
| 113 | regk_strmux_ext3 = 0x00000001, | ||
| 114 | regk_strmux_iop0 = 0x00000002, | ||
| 115 | regk_strmux_iop1 = 0x00000001, | ||
| 116 | regk_strmux_off = 0x00000000, | ||
| 117 | regk_strmux_p21 = 0x00000004, | ||
| 118 | regk_strmux_rw_cfg_default = 0x00000000, | ||
| 119 | regk_strmux_ser0 = 0x00000002, | ||
| 120 | regk_strmux_ser1 = 0x00000002, | ||
| 121 | regk_strmux_ser2 = 0x00000004, | ||
| 122 | regk_strmux_ser3 = 0x00000003, | ||
| 123 | regk_strmux_sser0 = 0x00000003, | ||
| 124 | regk_strmux_sser1 = 0x00000003, | ||
| 125 | regk_strmux_strcop = 0x00000002 | ||
| 126 | }; | ||
| 127 | #endif /* __strmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h deleted file mode 100644 index 76bcc591921d..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h +++ /dev/null | |||
| @@ -1,266 +0,0 @@ | |||
| 1 | #ifndef __timer_defs_h | ||
| 2 | #define __timer_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/timer/rtl/timer_regs.r | ||
| 7 | * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:53 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r | ||
| 11 | * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope timer */ | ||
| 86 | |||
| 87 | /* Register rw_tmr0_div, scope timer, type rw */ | ||
| 88 | typedef unsigned int reg_timer_rw_tmr0_div; | ||
| 89 | #define REG_RD_ADDR_timer_rw_tmr0_div 0 | ||
| 90 | #define REG_WR_ADDR_timer_rw_tmr0_div 0 | ||
| 91 | |||
| 92 | /* Register r_tmr0_data, scope timer, type r */ | ||
| 93 | typedef unsigned int reg_timer_r_tmr0_data; | ||
| 94 | #define REG_RD_ADDR_timer_r_tmr0_data 4 | ||
| 95 | |||
| 96 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | ||
| 97 | typedef struct { | ||
| 98 | unsigned int op : 2; | ||
| 99 | unsigned int freq : 3; | ||
| 100 | unsigned int dummy1 : 27; | ||
| 101 | } reg_timer_rw_tmr0_ctrl; | ||
| 102 | #define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 | ||
| 103 | #define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 | ||
| 104 | |||
| 105 | /* Register rw_tmr1_div, scope timer, type rw */ | ||
| 106 | typedef unsigned int reg_timer_rw_tmr1_div; | ||
| 107 | #define REG_RD_ADDR_timer_rw_tmr1_div 16 | ||
| 108 | #define REG_WR_ADDR_timer_rw_tmr1_div 16 | ||
| 109 | |||
| 110 | /* Register r_tmr1_data, scope timer, type r */ | ||
| 111 | typedef unsigned int reg_timer_r_tmr1_data; | ||
| 112 | #define REG_RD_ADDR_timer_r_tmr1_data 20 | ||
| 113 | |||
| 114 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int op : 2; | ||
| 117 | unsigned int freq : 3; | ||
| 118 | unsigned int dummy1 : 27; | ||
| 119 | } reg_timer_rw_tmr1_ctrl; | ||
| 120 | #define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 | ||
| 121 | #define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 | ||
| 122 | |||
| 123 | /* Register rs_cnt_data, scope timer, type rs */ | ||
| 124 | typedef struct { | ||
| 125 | unsigned int tmr : 24; | ||
| 126 | unsigned int cnt : 8; | ||
| 127 | } reg_timer_rs_cnt_data; | ||
| 128 | #define REG_RD_ADDR_timer_rs_cnt_data 32 | ||
| 129 | |||
| 130 | /* Register r_cnt_data, scope timer, type r */ | ||
| 131 | typedef struct { | ||
| 132 | unsigned int tmr : 24; | ||
| 133 | unsigned int cnt : 8; | ||
| 134 | } reg_timer_r_cnt_data; | ||
| 135 | #define REG_RD_ADDR_timer_r_cnt_data 36 | ||
| 136 | |||
| 137 | /* Register rw_cnt_cfg, scope timer, type rw */ | ||
| 138 | typedef struct { | ||
| 139 | unsigned int clk : 2; | ||
| 140 | unsigned int dummy1 : 30; | ||
| 141 | } reg_timer_rw_cnt_cfg; | ||
| 142 | #define REG_RD_ADDR_timer_rw_cnt_cfg 40 | ||
| 143 | #define REG_WR_ADDR_timer_rw_cnt_cfg 40 | ||
| 144 | |||
| 145 | /* Register rw_trig, scope timer, type rw */ | ||
| 146 | typedef unsigned int reg_timer_rw_trig; | ||
| 147 | #define REG_RD_ADDR_timer_rw_trig 48 | ||
| 148 | #define REG_WR_ADDR_timer_rw_trig 48 | ||
| 149 | |||
| 150 | /* Register rw_trig_cfg, scope timer, type rw */ | ||
| 151 | typedef struct { | ||
| 152 | unsigned int tmr : 2; | ||
| 153 | unsigned int dummy1 : 30; | ||
| 154 | } reg_timer_rw_trig_cfg; | ||
| 155 | #define REG_RD_ADDR_timer_rw_trig_cfg 52 | ||
| 156 | #define REG_WR_ADDR_timer_rw_trig_cfg 52 | ||
| 157 | |||
| 158 | /* Register r_time, scope timer, type r */ | ||
| 159 | typedef unsigned int reg_timer_r_time; | ||
| 160 | #define REG_RD_ADDR_timer_r_time 56 | ||
| 161 | |||
| 162 | /* Register rw_out, scope timer, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int tmr : 2; | ||
| 165 | unsigned int dummy1 : 30; | ||
| 166 | } reg_timer_rw_out; | ||
| 167 | #define REG_RD_ADDR_timer_rw_out 60 | ||
| 168 | #define REG_WR_ADDR_timer_rw_out 60 | ||
| 169 | |||
| 170 | /* Register rw_wd_ctrl, scope timer, type rw */ | ||
| 171 | typedef struct { | ||
| 172 | unsigned int cnt : 8; | ||
| 173 | unsigned int cmd : 1; | ||
| 174 | unsigned int key : 7; | ||
| 175 | unsigned int dummy1 : 16; | ||
| 176 | } reg_timer_rw_wd_ctrl; | ||
| 177 | #define REG_RD_ADDR_timer_rw_wd_ctrl 64 | ||
| 178 | #define REG_WR_ADDR_timer_rw_wd_ctrl 64 | ||
| 179 | |||
| 180 | /* Register r_wd_stat, scope timer, type r */ | ||
| 181 | typedef struct { | ||
| 182 | unsigned int cnt : 8; | ||
| 183 | unsigned int cmd : 1; | ||
| 184 | unsigned int dummy1 : 23; | ||
| 185 | } reg_timer_r_wd_stat; | ||
| 186 | #define REG_RD_ADDR_timer_r_wd_stat 68 | ||
| 187 | |||
| 188 | /* Register rw_intr_mask, scope timer, type rw */ | ||
| 189 | typedef struct { | ||
| 190 | unsigned int tmr0 : 1; | ||
| 191 | unsigned int tmr1 : 1; | ||
| 192 | unsigned int cnt : 1; | ||
| 193 | unsigned int trig : 1; | ||
| 194 | unsigned int dummy1 : 28; | ||
| 195 | } reg_timer_rw_intr_mask; | ||
| 196 | #define REG_RD_ADDR_timer_rw_intr_mask 72 | ||
| 197 | #define REG_WR_ADDR_timer_rw_intr_mask 72 | ||
| 198 | |||
| 199 | /* Register rw_ack_intr, scope timer, type rw */ | ||
| 200 | typedef struct { | ||
| 201 | unsigned int tmr0 : 1; | ||
| 202 | unsigned int tmr1 : 1; | ||
| 203 | unsigned int cnt : 1; | ||
| 204 | unsigned int trig : 1; | ||
| 205 | unsigned int dummy1 : 28; | ||
| 206 | } reg_timer_rw_ack_intr; | ||
| 207 | #define REG_RD_ADDR_timer_rw_ack_intr 76 | ||
| 208 | #define REG_WR_ADDR_timer_rw_ack_intr 76 | ||
| 209 | |||
| 210 | /* Register r_intr, scope timer, type r */ | ||
| 211 | typedef struct { | ||
| 212 | unsigned int tmr0 : 1; | ||
| 213 | unsigned int tmr1 : 1; | ||
| 214 | unsigned int cnt : 1; | ||
| 215 | unsigned int trig : 1; | ||
| 216 | unsigned int dummy1 : 28; | ||
| 217 | } reg_timer_r_intr; | ||
| 218 | #define REG_RD_ADDR_timer_r_intr 80 | ||
| 219 | |||
| 220 | /* Register r_masked_intr, scope timer, type r */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int tmr0 : 1; | ||
| 223 | unsigned int tmr1 : 1; | ||
| 224 | unsigned int cnt : 1; | ||
| 225 | unsigned int trig : 1; | ||
| 226 | unsigned int dummy1 : 28; | ||
| 227 | } reg_timer_r_masked_intr; | ||
| 228 | #define REG_RD_ADDR_timer_r_masked_intr 84 | ||
| 229 | |||
| 230 | /* Register rw_test, scope timer, type rw */ | ||
| 231 | typedef struct { | ||
| 232 | unsigned int dis : 1; | ||
| 233 | unsigned int en : 1; | ||
| 234 | unsigned int dummy1 : 30; | ||
| 235 | } reg_timer_rw_test; | ||
| 236 | #define REG_RD_ADDR_timer_rw_test 88 | ||
| 237 | #define REG_WR_ADDR_timer_rw_test 88 | ||
| 238 | |||
| 239 | |||
| 240 | /* Constants */ | ||
| 241 | enum { | ||
| 242 | regk_timer_ext = 0x00000001, | ||
| 243 | regk_timer_f100 = 0x00000007, | ||
| 244 | regk_timer_f29_493 = 0x00000004, | ||
| 245 | regk_timer_f32 = 0x00000005, | ||
| 246 | regk_timer_f32_768 = 0x00000006, | ||
| 247 | regk_timer_hold = 0x00000001, | ||
| 248 | regk_timer_ld = 0x00000000, | ||
| 249 | regk_timer_no = 0x00000000, | ||
| 250 | regk_timer_off = 0x00000000, | ||
| 251 | regk_timer_run = 0x00000002, | ||
| 252 | regk_timer_rw_cnt_cfg_default = 0x00000000, | ||
| 253 | regk_timer_rw_intr_mask_default = 0x00000000, | ||
| 254 | regk_timer_rw_out_default = 0x00000000, | ||
| 255 | regk_timer_rw_test_default = 0x00000000, | ||
| 256 | regk_timer_rw_tmr0_ctrl_default = 0x00000000, | ||
| 257 | regk_timer_rw_tmr1_ctrl_default = 0x00000000, | ||
| 258 | regk_timer_rw_trig_cfg_default = 0x00000000, | ||
| 259 | regk_timer_start = 0x00000001, | ||
| 260 | regk_timer_stop = 0x00000000, | ||
| 261 | regk_timer_time = 0x00000001, | ||
| 262 | regk_timer_tmr0 = 0x00000002, | ||
| 263 | regk_timer_tmr1 = 0x00000003, | ||
| 264 | regk_timer_yes = 0x00000001 | ||
| 265 | }; | ||
| 266 | #endif /* __timer_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/pinmux.h b/include/asm-cris/arch-v32/mach-fs/pinmux.h deleted file mode 100644 index c2b3036779df..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/pinmux.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_PINMUX_H | ||
| 2 | #define _ASM_CRIS_ARCH_PINMUX_H | ||
| 3 | |||
| 4 | #define PORT_B 0 | ||
| 5 | #define PORT_C 1 | ||
| 6 | #define PORT_D 2 | ||
| 7 | #define PORT_E 3 | ||
| 8 | |||
| 9 | enum pin_mode { | ||
| 10 | pinmux_none = 0, | ||
| 11 | pinmux_fixed, | ||
| 12 | pinmux_gpio, | ||
| 13 | pinmux_iop | ||
| 14 | }; | ||
| 15 | |||
| 16 | enum fixed_function { | ||
| 17 | pinmux_ser1, | ||
| 18 | pinmux_ser2, | ||
| 19 | pinmux_ser3, | ||
| 20 | pinmux_sser0, | ||
| 21 | pinmux_sser1, | ||
| 22 | pinmux_ata0, | ||
| 23 | pinmux_ata1, | ||
| 24 | pinmux_ata2, | ||
| 25 | pinmux_ata3, | ||
| 26 | pinmux_ata, | ||
| 27 | pinmux_eth1, | ||
| 28 | pinmux_timer | ||
| 29 | }; | ||
| 30 | |||
| 31 | int crisv32_pinmux_init(void); | ||
| 32 | int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); | ||
| 33 | int crisv32_pinmux_alloc_fixed(enum fixed_function function); | ||
| 34 | int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); | ||
| 35 | int crisv32_pinmux_dealloc_fixed(enum fixed_function function); | ||
| 36 | void crisv32_pinmux_dump(void); | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/startup.inc b/include/asm-cris/arch-v32/mach-fs/startup.inc deleted file mode 100644 index 4a10ccbd6cc1..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/startup.inc +++ /dev/null | |||
| @@ -1,77 +0,0 @@ | |||
| 1 | #include <hwregs/asm/reg_map_asm.h> | ||
| 2 | #include <hwregs/asm/bif_core_defs_asm.h> | ||
| 3 | #include <hwregs/asm/gio_defs_asm.h> | ||
| 4 | #include <hwregs/asm/config_defs_asm.h> | ||
| 5 | |||
| 6 | .macro GIO_INIT | ||
| 7 | move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 | ||
| 8 | move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 | ||
| 9 | move.d $r0, [$r1] | ||
| 10 | |||
| 11 | move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 | ||
| 12 | move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 | ||
| 13 | move.d $r0, [$r1] | ||
| 14 | |||
| 15 | move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 | ||
| 16 | move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 | ||
| 17 | move.d $r0, [$r1] | ||
| 18 | |||
| 19 | move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 | ||
| 20 | move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 | ||
| 21 | move.d $r0, [$r1] | ||
| 22 | |||
| 23 | move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 | ||
| 24 | move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 | ||
| 25 | move.d $r0, [$r1] | ||
| 26 | |||
| 27 | move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 | ||
| 28 | move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 | ||
| 29 | move.d $r0, [$r1] | ||
| 30 | |||
| 31 | move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 | ||
| 32 | move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 | ||
| 33 | move.d $r0, [$r1] | ||
| 34 | |||
| 35 | move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 | ||
| 36 | move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 | ||
| 37 | move.d $r0, [$r1] | ||
| 38 | |||
| 39 | move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 | ||
| 40 | move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 | ||
| 41 | move.d $r0, [$r1] | ||
| 42 | |||
| 43 | move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 | ||
| 44 | move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 | ||
| 45 | move.d $r0, [$r1] | ||
| 46 | .endm | ||
| 47 | |||
| 48 | .macro START_CLOCKS | ||
| 49 | move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 | ||
| 50 | move.d [$r1], $r0 | ||
| 51 | or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ | ||
| 52 | REG_STATE(config, rw_clk_ctrl, bif, yes) | \ | ||
| 53 | REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 | ||
| 54 | move.d $r0, [$r1] | ||
| 55 | .endm | ||
| 56 | |||
| 57 | .macro SETUP_WAIT_STATES | ||
| 58 | ;; Set up waitstates etc | ||
| 59 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 | ||
| 60 | move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 | ||
| 61 | move.d $r1, [$r0] | ||
| 62 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 | ||
| 63 | move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 | ||
| 64 | move.d $r1, [$r0] | ||
| 65 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 | ||
| 66 | move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 | ||
| 67 | move.d $r1, [$r0] | ||
| 68 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 | ||
| 69 | move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 | ||
| 70 | move.d $r1, [$r0] | ||
| 71 | #ifdef CONFIG_ETRAX_VCS_SIM | ||
| 72 | ;; Set up minimal flash waitstates | ||
| 73 | move.d 0, $r10 | ||
| 74 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11 | ||
| 75 | move.d $r10, [$r11] | ||
| 76 | #endif | ||
| 77 | .endm | ||
diff --git a/include/asm-cris/arch-v32/memmap.h b/include/asm-cris/arch-v32/memmap.h deleted file mode 100644 index d29df5644d3e..000000000000 --- a/include/asm-cris/arch-v32/memmap.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_MEMMAP_H | ||
| 2 | #define _ASM_ARCH_MEMMAP_H | ||
| 3 | |||
| 4 | #define MEM_CSE0_START (0x00000000) | ||
| 5 | #define MEM_CSE0_SIZE (0x04000000) | ||
| 6 | #define MEM_CSE1_START (0x04000000) | ||
| 7 | #define MEM_CSE1_SIZE (0x04000000) | ||
| 8 | #define MEM_CSR0_START (0x08000000) | ||
| 9 | #define MEM_CSR1_START (0x0c000000) | ||
| 10 | #define MEM_CSP0_START (0x10000000) | ||
| 11 | #define MEM_CSP1_START (0x14000000) | ||
| 12 | #define MEM_CSP2_START (0x18000000) | ||
| 13 | #define MEM_CSP3_START (0x1c000000) | ||
| 14 | #define MEM_CSP4_START (0x20000000) | ||
| 15 | #define MEM_CSP5_START (0x24000000) | ||
| 16 | #define MEM_CSP6_START (0x28000000) | ||
| 17 | #define MEM_CSP7_START (0x2c000000) | ||
| 18 | #define MEM_INTMEM_START (0x38000000) | ||
| 19 | #define MEM_INTMEM_SIZE (0x00020000) | ||
| 20 | #define MEM_DRAM_START (0x40000000) | ||
| 21 | |||
| 22 | #define MEM_NON_CACHEABLE (0x80000000) | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mmu.h b/include/asm-cris/arch-v32/mmu.h deleted file mode 100644 index 6bcdc3fdf7dc..000000000000 --- a/include/asm-cris/arch-v32/mmu.h +++ /dev/null | |||
| @@ -1,111 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_MMU_H | ||
| 2 | #define _ASM_CRIS_ARCH_MMU_H | ||
| 3 | |||
| 4 | /* MMU context type. */ | ||
| 5 | typedef struct | ||
| 6 | { | ||
| 7 | unsigned int page_id; | ||
| 8 | } mm_context_t; | ||
| 9 | |||
| 10 | /* Kernel memory segments. */ | ||
| 11 | #define KSEG_F 0xf0000000UL | ||
| 12 | #define KSEG_E 0xe0000000UL | ||
| 13 | #define KSEG_D 0xd0000000UL | ||
| 14 | #define KSEG_C 0xc0000000UL | ||
| 15 | #define KSEG_B 0xb0000000UL | ||
| 16 | #define KSEG_A 0xa0000000UL | ||
| 17 | #define KSEG_9 0x90000000UL | ||
| 18 | #define KSEG_8 0x80000000UL | ||
| 19 | #define KSEG_7 0x70000000UL | ||
| 20 | #define KSEG_6 0x60000000UL | ||
| 21 | #define KSEG_5 0x50000000UL | ||
| 22 | #define KSEG_4 0x40000000UL | ||
| 23 | #define KSEG_3 0x30000000UL | ||
| 24 | #define KSEG_2 0x20000000UL | ||
| 25 | #define KSEG_1 0x10000000UL | ||
| 26 | #define KSEG_0 0x00000000UL | ||
| 27 | |||
| 28 | /* | ||
| 29 | * CRISv32 PTE bits: | ||
| 30 | * | ||
| 31 | * Bit: 31-13 12-5 4 3 2 1 0 | ||
| 32 | * +-----+------+--------+-------+--------+-------+---------+ | ||
| 33 | * | pfn | zero | global | valid | kernel | write | execute | | ||
| 34 | * +-----+------+--------+-------+--------+-------+---------+ | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Defines for accessing the bits. Also define some synonyms for use with | ||
| 39 | * the software-based defined bits below. | ||
| 40 | */ | ||
| 41 | #define _PAGE_EXECUTE (1 << 0) /* Execution bit. */ | ||
| 42 | #define _PAGE_WE (1 << 1) /* Write bit. */ | ||
| 43 | #define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */ | ||
| 44 | #define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */ | ||
| 45 | #define _PAGE_VALID (1 << 3) /* Page is valid. */ | ||
| 46 | #define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ | ||
| 47 | #define _PAGE_GLOBAL (1 << 4) /* Global page. */ | ||
| 48 | |||
| 49 | /* | ||
| 50 | * The hardware doesn't care about these bits, but the kernel uses them in | ||
| 51 | * software. | ||
| 52 | */ | ||
| 53 | #define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */ | ||
| 54 | #define _PAGE_FILE (1 << 6) /* 1=pagecache, 0=swap (when !present) */ | ||
| 55 | #define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */ | ||
| 56 | #define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */ | ||
| 57 | #define _PAGE_READ (1 << 8) /* Read enabled. */ | ||
| 58 | #define _PAGE_WRITE (1 << 9) /* Write enabled. */ | ||
| 59 | |||
| 60 | /* Define some higher level generic page attributes. */ | ||
| 61 | #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) | ||
| 62 | #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) | ||
| 63 | |||
| 64 | #define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) | ||
| 65 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) | ||
| 66 | |||
| 67 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) | ||
| 68 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ | ||
| 69 | _PAGE_ACCESSED) | ||
| 70 | #define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ | ||
| 71 | _PAGE_ACCESSED | _PAGE_EXECUTE) | ||
| 72 | |||
| 73 | #define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) | ||
| 74 | #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED) | ||
| 75 | |||
| 76 | #define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) | ||
| 77 | #define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE) | ||
| 78 | #define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ | ||
| 79 | _PAGE_PRESENT | __READABLE | __WRITEABLE) | ||
| 80 | #define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \ | ||
| 81 | _PAGE_PRESENT | __READABLE | __WRITEABLE) | ||
| 82 | #define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \ | ||
| 83 | _PAGE_PRESENT | __READABLE) | ||
| 84 | |||
| 85 | #define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) | ||
| 86 | |||
| 87 | /* CRISv32 can do page protection for execute. | ||
| 88 | * Write permissions imply read permissions. | ||
| 89 | * Note that the numbers are in Execute-Write-Read order! | ||
| 90 | */ | ||
| 91 | #define __P000 PAGE_NONE | ||
| 92 | #define __P001 PAGE_READONLY | ||
| 93 | #define __P010 PAGE_COPY | ||
| 94 | #define __P011 PAGE_COPY | ||
| 95 | #define __P100 PAGE_READONLY_EXEC | ||
| 96 | #define __P101 PAGE_READONLY_EXEC | ||
| 97 | #define __P110 PAGE_COPY_EXEC | ||
| 98 | #define __P111 PAGE_COPY_EXEC | ||
| 99 | |||
| 100 | #define __S000 PAGE_NONE | ||
| 101 | #define __S001 PAGE_READONLY | ||
| 102 | #define __S010 PAGE_SHARED | ||
| 103 | #define __S011 PAGE_SHARED | ||
| 104 | #define __S100 PAGE_READONLY_EXEC | ||
| 105 | #define __S101 PAGE_READONLY_EXEC | ||
| 106 | #define __S110 PAGE_SHARED_EXEC | ||
| 107 | #define __S111 PAGE_SHARED_EXEC | ||
| 108 | |||
| 109 | #define PTE_FILE_MAX_BITS 25 | ||
| 110 | |||
| 111 | #endif /* _ASM_CRIS_ARCH_MMU_H */ | ||
diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h deleted file mode 100644 index 4442c4bd52f4..000000000000 --- a/include/asm-cris/arch-v32/offset.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | #ifndef __ASM_OFFSETS_H__ | ||
| 2 | #define __ASM_OFFSETS_H__ | ||
| 3 | /* | ||
| 4 | * DO NOT MODIFY. | ||
| 5 | * | ||
| 6 | * This file was generated by arch/cris/Makefile | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */ | ||
| 11 | #define PT_r13 56 /* offsetof(struct pt_regs, r13) */ | ||
| 12 | #define PT_r12 52 /* offsetof(struct pt_regs, r12) */ | ||
| 13 | #define PT_r11 48 /* offsetof(struct pt_regs, r11) */ | ||
| 14 | #define PT_r10 44 /* offsetof(struct pt_regs, r10) */ | ||
| 15 | #define PT_r9 40 /* offsetof(struct pt_regs, r9) */ | ||
| 16 | #define PT_acr 60 /* offsetof(struct pt_regs, acr) */ | ||
| 17 | #define PT_srs 64 /* offsetof(struct pt_regs, srs) */ | ||
| 18 | #define PT_mof 68 /* offsetof(struct pt_regs, mof) */ | ||
| 19 | #define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */ | ||
| 20 | #define PT_srp 80 /* offsetof(struct pt_regs, srp) */ | ||
| 21 | |||
| 22 | #define TI_task 0 /* offsetof(struct thread_info, task) */ | ||
| 23 | #define TI_flags 8 /* offsetof(struct thread_info, flags) */ | ||
| 24 | #define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ | ||
| 25 | |||
| 26 | #define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ | ||
| 27 | #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ | ||
| 28 | #define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ | ||
| 29 | |||
| 30 | #define TASK_pid 151 /* offsetof(struct task_struct, pid) */ | ||
| 31 | |||
| 32 | #define LCLONE_VM 256 /* CLONE_VM */ | ||
| 33 | #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ | ||
| 34 | |||
| 35 | #endif | ||
diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h deleted file mode 100644 index 20f1b4806bfe..000000000000 --- a/include/asm-cris/arch-v32/page.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_PAGE_H | ||
| 2 | #define _ASM_CRIS_ARCH_PAGE_H | ||
| 3 | |||
| 4 | |||
| 5 | #ifdef __KERNEL__ | ||
| 6 | |||
| 7 | #define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Macros to convert between physical and virtual addresses. By stripping a | ||
| 11 | * selected bit it's possible to convert between KSEG_x and 0x40000000 where the | ||
| 12 | * DRAM really resides. DRAM is virtually at 0xc. | ||
| 13 | */ | ||
| 14 | #ifndef CONFIG_ETRAX_VCS_SIM | ||
| 15 | #define __pa(x) ((unsigned long)(x) & 0x7fffffff) | ||
| 16 | #define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) | ||
| 17 | #else | ||
| 18 | #define __pa(x) ((unsigned long)(x) & 0x3fffffff) | ||
| 19 | #define __va(x) ((void *)((unsigned long)(x) | 0xc0000000)) | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ | ||
| 23 | VM_MAYREAD | VM_MAYWRITE) | ||
| 24 | |||
| 25 | #endif /* __KERNEL__ */ | ||
| 26 | |||
| 27 | #endif /* _ASM_CRIS_ARCH_PAGE_H */ | ||
diff --git a/include/asm-cris/arch-v32/pgtable.h b/include/asm-cris/arch-v32/pgtable.h deleted file mode 100644 index 08cb7ff7e4e7..000000000000 --- a/include/asm-cris/arch-v32/pgtable.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_PGTABLE_H | ||
| 2 | #define _ASM_CRIS_ARCH_PGTABLE_H | ||
| 3 | |||
| 4 | /* Define the kernels virtual memory area. */ | ||
| 5 | #define VMALLOC_START KSEG_D | ||
| 6 | #define VMALLOC_END KSEG_E | ||
| 7 | #define VMALLOC_VMADDR(x) ((unsigned long)(x)) | ||
| 8 | |||
| 9 | #endif /* _ASM_CRIS_ARCH_PGTABLE_H */ | ||
diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h deleted file mode 100644 index bb09bce42e7a..000000000000 --- a/include/asm-cris/arch-v32/pinmux.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_PINMUX_H | ||
| 2 | #define _ASM_CRIS_ARCH_PINMUX_H | ||
| 3 | |||
| 4 | #define PORT_B 0 | ||
| 5 | #define PORT_C 1 | ||
| 6 | #define PORT_D 2 | ||
| 7 | #define PORT_E 3 | ||
| 8 | |||
| 9 | enum pin_mode | ||
| 10 | { | ||
| 11 | pinmux_none = 0, | ||
| 12 | pinmux_fixed, | ||
| 13 | pinmux_gpio, | ||
| 14 | pinmux_iop | ||
| 15 | }; | ||
| 16 | |||
| 17 | enum fixed_function | ||
| 18 | { | ||
| 19 | pinmux_ser1, | ||
| 20 | pinmux_ser2, | ||
| 21 | pinmux_ser3, | ||
| 22 | pinmux_sser0, | ||
| 23 | pinmux_sser1, | ||
| 24 | pinmux_ata0, | ||
| 25 | pinmux_ata1, | ||
| 26 | pinmux_ata2, | ||
| 27 | pinmux_ata3, | ||
| 28 | pinmux_ata, | ||
| 29 | pinmux_eth1, | ||
| 30 | pinmux_timer | ||
| 31 | }; | ||
| 32 | |||
| 33 | int crisv32_pinmux_init(void); | ||
| 34 | int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); | ||
| 35 | int crisv32_pinmux_alloc_fixed(enum fixed_function function); | ||
| 36 | int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); | ||
| 37 | int crisv32_pinmux_dealloc_fixed(enum fixed_function function); | ||
| 38 | void crisv32_pinmux_dump(void); | ||
| 39 | |||
| 40 | #endif | ||
diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h deleted file mode 100644 index f80b47790ca6..000000000000 --- a/include/asm-cris/arch-v32/processor.h +++ /dev/null | |||
| @@ -1,59 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_PROCESSOR_H | ||
| 2 | #define _ASM_CRIS_ARCH_PROCESSOR_H | ||
| 3 | |||
| 4 | |||
| 5 | /* Return current instruction pointer. */ | ||
| 6 | #define current_text_addr() \ | ||
| 7 | ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;}) | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Since CRIS doesn't do hardware task-switching this hasn't really anything to | ||
| 11 | * do with the proccessor itself, it's just here for legacy reasons. This is | ||
| 12 | * used when task-switching using _resume defined in entry.S. The offsets here | ||
| 13 | * are hardcoded into _resume, so if this struct is changed, entry.S needs to be | ||
| 14 | * changed as well. | ||
| 15 | */ | ||
| 16 | struct thread_struct { | ||
| 17 | unsigned long ksp; /* Kernel stack pointer. */ | ||
| 18 | unsigned long usp; /* User stack pointer. */ | ||
| 19 | unsigned long ccs; /* Saved flags register. */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | /* | ||
| 23 | * User-space process size. This is hardcoded into a few places, so don't | ||
| 24 | * changed it unless everything's clear! | ||
| 25 | */ | ||
| 26 | #ifndef CONFIG_ETRAX_VCS_SIM | ||
| 27 | #define TASK_SIZE (0xB0000000UL) | ||
| 28 | #else | ||
| 29 | #define TASK_SIZE (0xA0000000UL) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | /* CCS I=1, enable interrupts. */ | ||
| 33 | #define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) } | ||
| 34 | |||
| 35 | #define KSTK_EIP(tsk) \ | ||
| 36 | ({ \ | ||
| 37 | unsigned long eip = 0; \ | ||
| 38 | unsigned long regs = (unsigned long)task_pt_regs(tsk); \ | ||
| 39 | if (regs > PAGE_SIZE && virt_addr_valid(regs)) \ | ||
| 40 | eip = ((struct pt_regs *)regs)->erp; \ | ||
| 41 | eip; \ | ||
| 42 | }) | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Give the thread a program location, set user-mode and switch user | ||
| 46 | * stackpointer. | ||
| 47 | */ | ||
| 48 | #define start_thread(regs, ip, usp) \ | ||
| 49 | do { \ | ||
| 50 | set_fs(USER_DS); \ | ||
| 51 | regs->erp = ip; \ | ||
| 52 | regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \ | ||
| 53 | wrusp(usp); \ | ||
| 54 | } while(0) | ||
| 55 | |||
| 56 | /* Nothing special to do for v32 when handling a kernel bus fault fixup. */ | ||
| 57 | #define arch_fixup(regs) {}; | ||
| 58 | |||
| 59 | #endif /* _ASM_CRIS_ARCH_PROCESSOR_H */ | ||
diff --git a/include/asm-cris/arch-v32/ptrace.h b/include/asm-cris/arch-v32/ptrace.h deleted file mode 100644 index 41f4e8662bc2..000000000000 --- a/include/asm-cris/arch-v32/ptrace.h +++ /dev/null | |||
| @@ -1,118 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_PTRACE_H | ||
| 2 | #define _CRIS_ARCH_PTRACE_H | ||
| 3 | |||
| 4 | /* Register numbers in the ptrace system call interface */ | ||
| 5 | |||
| 6 | #define PT_ORIG_R10 0 | ||
| 7 | #define PT_R0 1 | ||
| 8 | #define PT_R1 2 | ||
| 9 | #define PT_R2 3 | ||
| 10 | #define PT_R3 4 | ||
| 11 | #define PT_R4 5 | ||
| 12 | #define PT_R5 6 | ||
| 13 | #define PT_R6 7 | ||
| 14 | #define PT_R7 8 | ||
| 15 | #define PT_R8 9 | ||
| 16 | #define PT_R9 10 | ||
| 17 | #define PT_R10 11 | ||
| 18 | #define PT_R11 12 | ||
| 19 | #define PT_R12 13 | ||
| 20 | #define PT_R13 14 | ||
| 21 | #define PT_ACR 15 | ||
| 22 | #define PT_SRS 16 | ||
| 23 | #define PT_MOF 17 | ||
| 24 | #define PT_SPC 18 | ||
| 25 | #define PT_CCS 19 | ||
| 26 | #define PT_SRP 20 | ||
| 27 | #define PT_ERP 21 /* This is actually the debugged process' PC */ | ||
| 28 | #define PT_EXS 22 | ||
| 29 | #define PT_EDA 23 | ||
| 30 | #define PT_USP 24 /* special case - USP is not in the pt_regs */ | ||
| 31 | #define PT_PPC 25 /* special case - pseudo PC */ | ||
| 32 | #define PT_BP 26 /* Base number for BP registers. */ | ||
| 33 | #define PT_BP_CTRL 26 /* BP control register. */ | ||
| 34 | #define PT_MAX 40 | ||
| 35 | |||
| 36 | /* Condition code bit numbers. */ | ||
| 37 | #define C_CCS_BITNR 0 | ||
| 38 | #define V_CCS_BITNR 1 | ||
| 39 | #define Z_CCS_BITNR 2 | ||
| 40 | #define N_CCS_BITNR 3 | ||
| 41 | #define X_CCS_BITNR 4 | ||
| 42 | #define I_CCS_BITNR 5 | ||
| 43 | #define U_CCS_BITNR 6 | ||
| 44 | #define P_CCS_BITNR 7 | ||
| 45 | #define R_CCS_BITNR 8 | ||
| 46 | #define S_CCS_BITNR 9 | ||
| 47 | #define M_CCS_BITNR 30 | ||
| 48 | #define Q_CCS_BITNR 31 | ||
| 49 | #define CCS_SHIFT 10 /* Shift count for each level in CCS */ | ||
| 50 | |||
| 51 | /* pt_regs not only specifices the format in the user-struct during | ||
| 52 | * ptrace but is also the frame format used in the kernel prologue/epilogues | ||
| 53 | * themselves | ||
| 54 | */ | ||
| 55 | |||
| 56 | struct pt_regs { | ||
| 57 | unsigned long orig_r10; | ||
| 58 | /* pushed by movem r13, [sp] in SAVE_ALL. */ | ||
| 59 | unsigned long r0; | ||
| 60 | unsigned long r1; | ||
| 61 | unsigned long r2; | ||
| 62 | unsigned long r3; | ||
| 63 | unsigned long r4; | ||
| 64 | unsigned long r5; | ||
| 65 | unsigned long r6; | ||
| 66 | unsigned long r7; | ||
| 67 | unsigned long r8; | ||
| 68 | unsigned long r9; | ||
| 69 | unsigned long r10; | ||
| 70 | unsigned long r11; | ||
| 71 | unsigned long r12; | ||
| 72 | unsigned long r13; | ||
| 73 | unsigned long acr; | ||
| 74 | unsigned long srs; | ||
| 75 | unsigned long mof; | ||
| 76 | unsigned long spc; | ||
| 77 | unsigned long ccs; | ||
| 78 | unsigned long srp; | ||
| 79 | unsigned long erp; /* This is actually the debugged process' PC */ | ||
| 80 | /* For debugging purposes; saved only when needed. */ | ||
| 81 | unsigned long exs; | ||
| 82 | unsigned long eda; | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) | ||
| 86 | * when doing a context-switch. it is used (apart from in resume) when a new | ||
| 87 | * thread is made and we need to make _resume (which is starting it for the | ||
| 88 | * first time) realise what is going on. | ||
| 89 | * | ||
| 90 | * Actually, the use is very close to the thread struct (TSS) in that both the | ||
| 91 | * switch_stack and the TSS are used to keep thread stuff when switching in | ||
| 92 | * _resume. | ||
| 93 | */ | ||
| 94 | |||
| 95 | struct switch_stack { | ||
| 96 | unsigned long r0; | ||
| 97 | unsigned long r1; | ||
| 98 | unsigned long r2; | ||
| 99 | unsigned long r3; | ||
| 100 | unsigned long r4; | ||
| 101 | unsigned long r5; | ||
| 102 | unsigned long r6; | ||
| 103 | unsigned long r7; | ||
| 104 | unsigned long r8; | ||
| 105 | unsigned long r9; | ||
| 106 | unsigned long return_ip; /* ip that _resume will return to */ | ||
| 107 | }; | ||
| 108 | |||
| 109 | #ifdef __KERNEL__ | ||
| 110 | |||
| 111 | #define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) | ||
| 112 | #define instruction_pointer(regs) ((regs)->erp) | ||
| 113 | extern void show_regs(struct pt_regs *); | ||
| 114 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 115 | |||
| 116 | #endif /* __KERNEL__ */ | ||
| 117 | |||
| 118 | #endif | ||
diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h deleted file mode 100644 index 0d5709b983a1..000000000000 --- a/include/asm-cris/arch-v32/spinlock.h +++ /dev/null | |||
| @@ -1,129 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_SPINLOCK_H | ||
| 2 | #define __ASM_ARCH_SPINLOCK_H | ||
| 3 | |||
| 4 | #include <linux/spinlock_types.h> | ||
| 5 | |||
| 6 | #define RW_LOCK_BIAS 0x01000000 | ||
| 7 | |||
| 8 | extern void cris_spin_unlock(void *l, int val); | ||
| 9 | extern void cris_spin_lock(void *l); | ||
| 10 | extern int cris_spin_trylock(void *l); | ||
| 11 | |||
| 12 | static inline int __raw_spin_is_locked(raw_spinlock_t *x) | ||
| 13 | { | ||
| 14 | return *(volatile signed char *)(&(x)->slock) <= 0; | ||
| 15 | } | ||
| 16 | |||
| 17 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) | ||
| 18 | { | ||
| 19 | __asm__ volatile ("move.d %1,%0" \ | ||
| 20 | : "=m" (lock->slock) \ | ||
| 21 | : "r" (1) \ | ||
| 22 | : "memory"); | ||
| 23 | } | ||
| 24 | |||
| 25 | static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) | ||
| 26 | { | ||
| 27 | while (__raw_spin_is_locked(lock)) | ||
| 28 | cpu_relax(); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline int __raw_spin_trylock(raw_spinlock_t *lock) | ||
| 32 | { | ||
| 33 | return cris_spin_trylock((void *)&lock->slock); | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline void __raw_spin_lock(raw_spinlock_t *lock) | ||
| 37 | { | ||
| 38 | cris_spin_lock((void *)&lock->slock); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void | ||
| 42 | __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) | ||
| 43 | { | ||
| 44 | __raw_spin_lock(lock); | ||
| 45 | } | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Read-write spinlocks, allowing multiple readers | ||
| 49 | * but only one writer. | ||
| 50 | * | ||
| 51 | * NOTE! it is quite common to have readers in interrupts | ||
| 52 | * but no interrupt writers. For those circumstances we | ||
| 53 | * can "mix" irq-safe locks - any writer needs to get a | ||
| 54 | * irq-safe write-lock, but readers can get non-irqsafe | ||
| 55 | * read-locks. | ||
| 56 | * | ||
| 57 | */ | ||
| 58 | |||
| 59 | static inline int __raw_read_can_lock(raw_rwlock_t *x) | ||
| 60 | { | ||
| 61 | return (int)(x)->lock > 0; | ||
| 62 | } | ||
| 63 | |||
| 64 | static inline int __raw_write_can_lock(raw_rwlock_t *x) | ||
| 65 | { | ||
| 66 | return (x)->lock == RW_LOCK_BIAS; | ||
| 67 | } | ||
| 68 | |||
| 69 | static inline void __raw_read_lock(raw_rwlock_t *rw) | ||
| 70 | { | ||
| 71 | __raw_spin_lock(&rw->slock); | ||
| 72 | while (rw->lock == 0); | ||
| 73 | rw->lock--; | ||
| 74 | __raw_spin_unlock(&rw->slock); | ||
| 75 | } | ||
| 76 | |||
| 77 | static inline void __raw_write_lock(raw_rwlock_t *rw) | ||
| 78 | { | ||
| 79 | __raw_spin_lock(&rw->slock); | ||
| 80 | while (rw->lock != RW_LOCK_BIAS); | ||
| 81 | rw->lock == 0; | ||
| 82 | __raw_spin_unlock(&rw->slock); | ||
| 83 | } | ||
| 84 | |||
| 85 | static inline void __raw_read_unlock(raw_rwlock_t *rw) | ||
| 86 | { | ||
| 87 | __raw_spin_lock(&rw->slock); | ||
| 88 | rw->lock++; | ||
| 89 | __raw_spin_unlock(&rw->slock); | ||
| 90 | } | ||
| 91 | |||
| 92 | static inline void __raw_write_unlock(raw_rwlock_t *rw) | ||
| 93 | { | ||
| 94 | __raw_spin_lock(&rw->slock); | ||
| 95 | while (rw->lock != RW_LOCK_BIAS); | ||
| 96 | rw->lock == RW_LOCK_BIAS; | ||
| 97 | __raw_spin_unlock(&rw->slock); | ||
| 98 | } | ||
| 99 | |||
| 100 | static inline int __raw_read_trylock(raw_rwlock_t *rw) | ||
| 101 | { | ||
| 102 | int ret = 0; | ||
| 103 | __raw_spin_lock(&rw->slock); | ||
| 104 | if (rw->lock != 0) { | ||
| 105 | rw->lock--; | ||
| 106 | ret = 1; | ||
| 107 | } | ||
| 108 | __raw_spin_unlock(&rw->slock); | ||
| 109 | return ret; | ||
| 110 | } | ||
| 111 | |||
| 112 | static inline int __raw_write_trylock(raw_rwlock_t *rw) | ||
| 113 | { | ||
| 114 | int ret = 0; | ||
| 115 | __raw_spin_lock(&rw->slock); | ||
| 116 | if (rw->lock == RW_LOCK_BIAS) { | ||
| 117 | rw->lock == 0; | ||
| 118 | ret = 1; | ||
| 119 | } | ||
| 120 | __raw_spin_unlock(&rw->slock); | ||
| 121 | return 1; | ||
| 122 | } | ||
| 123 | |||
| 124 | |||
| 125 | #define _raw_spin_relax(lock) cpu_relax() | ||
| 126 | #define _raw_read_relax(lock) cpu_relax() | ||
| 127 | #define _raw_write_relax(lock) cpu_relax() | ||
| 128 | |||
| 129 | #endif /* __ASM_ARCH_SPINLOCK_H */ | ||
diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h deleted file mode 100644 index 6ca90f1f110a..000000000000 --- a/include/asm-cris/arch-v32/system.h +++ /dev/null | |||
| @@ -1,69 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_SYSTEM_H | ||
| 2 | #define _ASM_CRIS_ARCH_SYSTEM_H | ||
| 3 | |||
| 4 | |||
| 5 | /* Read the CPU version register. */ | ||
| 6 | static inline unsigned long rdvr(void) | ||
| 7 | { | ||
| 8 | unsigned char vr; | ||
| 9 | |||
| 10 | __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr)); | ||
| 11 | return vr; | ||
| 12 | } | ||
| 13 | |||
| 14 | #define cris_machine_name "crisv32" | ||
| 15 | |||
| 16 | /* Read the user-mode stack pointer. */ | ||
| 17 | static inline unsigned long rdusp(void) | ||
| 18 | { | ||
| 19 | unsigned long usp; | ||
| 20 | |||
| 21 | __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp)); | ||
| 22 | return usp; | ||
| 23 | } | ||
| 24 | |||
| 25 | /* Read the current stack pointer. */ | ||
| 26 | static inline unsigned long rdsp(void) | ||
| 27 | { | ||
| 28 | unsigned long sp; | ||
| 29 | |||
| 30 | __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp)); | ||
| 31 | return sp; | ||
| 32 | } | ||
| 33 | |||
| 34 | /* Write the user-mode stack pointer. */ | ||
| 35 | #define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp)) | ||
| 36 | |||
| 37 | #define nop() __asm__ __volatile__ ("nop"); | ||
| 38 | |||
| 39 | #define xchg(ptr,x) \ | ||
| 40 | ((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr)))) | ||
| 41 | |||
| 42 | #define tas(ptr) (xchg((ptr),1)) | ||
| 43 | |||
| 44 | struct __xchg_dummy { unsigned long a[100]; }; | ||
| 45 | #define __xg(x) ((struct __xchg_dummy *)(x)) | ||
| 46 | |||
| 47 | /* Used for interrupt control. */ | ||
| 48 | #define local_save_flags(x) \ | ||
| 49 | __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory"); | ||
| 50 | |||
| 51 | #define local_irq_restore(x) \ | ||
| 52 | __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory"); | ||
| 53 | |||
| 54 | #define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory"); | ||
| 55 | #define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory"); | ||
| 56 | |||
| 57 | #define irqs_disabled() \ | ||
| 58 | ({ \ | ||
| 59 | unsigned long flags; \ | ||
| 60 | \ | ||
| 61 | local_save_flags(flags);\ | ||
| 62 | !(flags & (1 << I_CCS_BITNR)); \ | ||
| 63 | }) | ||
| 64 | |||
| 65 | /* Used for spinlocks, etc. */ | ||
| 66 | #define local_irq_save(x) \ | ||
| 67 | __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); | ||
| 68 | |||
| 69 | #endif /* _ASM_CRIS_ARCH_SYSTEM_H */ | ||
diff --git a/include/asm-cris/arch-v32/thread_info.h b/include/asm-cris/arch-v32/thread_info.h deleted file mode 100644 index d6936956a3c6..000000000000 --- a/include/asm-cris/arch-v32/thread_info.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_THREAD_INFO_H | ||
| 2 | #define _ASM_CRIS_ARCH_THREAD_INFO_H | ||
| 3 | |||
| 4 | /* Return a thread_info struct. */ | ||
| 5 | static inline struct thread_info *current_thread_info(void) | ||
| 6 | { | ||
| 7 | struct thread_info *ti; | ||
| 8 | |||
| 9 | __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL)); | ||
| 10 | return ti; | ||
| 11 | } | ||
| 12 | |||
| 13 | #endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */ | ||
diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h deleted file mode 100644 index 2591d3c5ed9d..000000000000 --- a/include/asm-cris/arch-v32/timex.h +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_TIMEX_H | ||
| 2 | #define _ASM_CRIS_ARCH_TIMEX_H | ||
| 3 | |||
| 4 | #include <hwregs/reg_map.h> | ||
| 5 | #include <hwregs/reg_rdwr.h> | ||
| 6 | #include <hwregs/timer_defs.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * The clock runs at 100MHz, we divide it by 1000000. If you change anything | ||
| 10 | * here you must check time.c as well. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */ | ||
| 14 | |||
| 15 | /* The timer0 values gives 10 ns resolution but interrupts at HZ. */ | ||
| 16 | #define TIMER0_FREQ (CLOCK_TICK_RATE) | ||
| 17 | #define TIMER0_DIV (TIMER0_FREQ/(HZ)) | ||
| 18 | |||
| 19 | /* Convert the value in step of 10 ns to 1us without overflow: */ | ||
| 20 | #define GET_JIFFIES_USEC() \ | ||
| 21 | ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100) | ||
| 22 | |||
| 23 | extern unsigned long get_ns_in_jiffie(void); | ||
| 24 | |||
| 25 | static inline unsigned long get_us_in_jiffie_highres(void) | ||
| 26 | { | ||
| 27 | return get_ns_in_jiffie() / 1000; | ||
| 28 | } | ||
| 29 | |||
| 30 | #endif | ||
| 31 | |||
diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h deleted file mode 100644 index 4effb1253660..000000000000 --- a/include/asm-cris/arch-v32/tlb.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ARCH_TLB_H | ||
| 2 | #define _CRIS_ARCH_TLB_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used | ||
| 6 | * to store the "process" it belongs to (=> fast mm context switch). The | ||
| 7 | * last page_id is never used so we can make TLB entries that never matches. | ||
| 8 | */ | ||
| 9 | #define NUM_TLB_ENTRIES 64 | ||
| 10 | #define NUM_PAGEID 256 | ||
| 11 | #define INVALID_PAGEID 255 | ||
| 12 | #define NO_CONTEXT -1 | ||
| 13 | |||
| 14 | #endif /* _CRIS_ARCH_TLB_H */ | ||
diff --git a/include/asm-cris/arch-v32/uaccess.h b/include/asm-cris/arch-v32/uaccess.h deleted file mode 100644 index 6b207f1b6622..000000000000 --- a/include/asm-cris/arch-v32/uaccess.h +++ /dev/null | |||
| @@ -1,748 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Authors: Hans-Peter Nilsson (hp@axis.com) | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | #ifndef _CRIS_ARCH_UACCESS_H | ||
| 6 | #define _CRIS_ARCH_UACCESS_H | ||
| 7 | |||
| 8 | /* | ||
| 9 | * We don't tell gcc that we are accessing memory, but this is OK | ||
| 10 | * because we do not write to any memory gcc knows about, so there | ||
| 11 | * are no aliasing issues. | ||
| 12 | * | ||
| 13 | * Note that PC at a fault is the address *at* the faulting | ||
| 14 | * instruction for CRISv32. | ||
| 15 | */ | ||
| 16 | #define __put_user_asm(x, addr, err, op) \ | ||
| 17 | __asm__ __volatile__( \ | ||
| 18 | "2: "op" %1,[%2]\n" \ | ||
| 19 | "4:\n" \ | ||
| 20 | " .section .fixup,\"ax\"\n" \ | ||
| 21 | "3: move.d %3,%0\n" \ | ||
| 22 | " jump 4b\n" \ | ||
| 23 | " nop\n" \ | ||
| 24 | " .previous\n" \ | ||
| 25 | " .section __ex_table,\"a\"\n" \ | ||
| 26 | " .dword 2b,3b\n" \ | ||
| 27 | " .previous\n" \ | ||
| 28 | : "=r" (err) \ | ||
| 29 | : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 30 | |||
| 31 | #define __put_user_asm_64(x, addr, err) do { \ | ||
| 32 | int dummy_for_put_user_asm_64_; \ | ||
| 33 | __asm__ __volatile__( \ | ||
| 34 | "2: move.d %M2,[%1+]\n" \ | ||
| 35 | "4: move.d %H2,[%1]\n" \ | ||
| 36 | "5:\n" \ | ||
| 37 | " .section .fixup,\"ax\"\n" \ | ||
| 38 | "3: move.d %4,%0\n" \ | ||
| 39 | " jump 5b\n" \ | ||
| 40 | " .previous\n" \ | ||
| 41 | " .section __ex_table,\"a\"\n" \ | ||
| 42 | " .dword 2b,3b\n" \ | ||
| 43 | " .dword 4b,3b\n" \ | ||
| 44 | " .previous\n" \ | ||
| 45 | : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \ | ||
| 46 | : "r" (x), "1" (addr), "g" (-EFAULT), \ | ||
| 47 | "0" (err)); \ | ||
| 48 | } while (0) | ||
| 49 | |||
| 50 | /* See comment before __put_user_asm. */ | ||
| 51 | |||
| 52 | #define __get_user_asm(x, addr, err, op) \ | ||
| 53 | __asm__ __volatile__( \ | ||
| 54 | "2: "op" [%2],%1\n" \ | ||
| 55 | "4:\n" \ | ||
| 56 | " .section .fixup,\"ax\"\n" \ | ||
| 57 | "3: move.d %3,%0\n" \ | ||
| 58 | " jump 4b\n" \ | ||
| 59 | " moveq 0,%1\n" \ | ||
| 60 | " .previous\n" \ | ||
| 61 | " .section __ex_table,\"a\"\n" \ | ||
| 62 | " .dword 2b,3b\n" \ | ||
| 63 | " .previous\n" \ | ||
| 64 | : "=r" (err), "=r" (x) \ | ||
| 65 | : "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 66 | |||
| 67 | #define __get_user_asm_64(x, addr, err) do { \ | ||
| 68 | int dummy_for_get_user_asm_64_; \ | ||
| 69 | __asm__ __volatile__( \ | ||
| 70 | "2: move.d [%2+],%M1\n" \ | ||
| 71 | "4: move.d [%2],%H1\n" \ | ||
| 72 | "5:\n" \ | ||
| 73 | " .section .fixup,\"ax\"\n" \ | ||
| 74 | "3: move.d %4,%0\n" \ | ||
| 75 | " jump 5b\n" \ | ||
| 76 | " moveq 0,%1\n" \ | ||
| 77 | " .previous\n" \ | ||
| 78 | " .section __ex_table,\"a\"\n" \ | ||
| 79 | " .dword 2b,3b\n" \ | ||
| 80 | " .dword 4b,3b\n" \ | ||
| 81 | " .previous\n" \ | ||
| 82 | : "=r" (err), "=r" (x), \ | ||
| 83 | "=b" (dummy_for_get_user_asm_64_) \ | ||
| 84 | : "2" (addr), "g" (-EFAULT), "0" (err));\ | ||
| 85 | } while (0) | ||
| 86 | |||
| 87 | /* | ||
| 88 | * Copy a null terminated string from userspace. | ||
| 89 | * | ||
| 90 | * Must return: | ||
| 91 | * -EFAULT for an exception | ||
| 92 | * count if we hit the buffer limit | ||
| 93 | * bytes copied if we hit a null byte | ||
| 94 | * (without the null byte) | ||
| 95 | */ | ||
| 96 | static inline long | ||
| 97 | __do_strncpy_from_user(char *dst, const char *src, long count) | ||
| 98 | { | ||
| 99 | long res; | ||
| 100 | |||
| 101 | if (count == 0) | ||
| 102 | return 0; | ||
| 103 | |||
| 104 | /* | ||
| 105 | * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. | ||
| 106 | * So do we. | ||
| 107 | * | ||
| 108 | * This code is deduced from: | ||
| 109 | * | ||
| 110 | * char tmp2; | ||
| 111 | * long tmp1, tmp3; | ||
| 112 | * tmp1 = count; | ||
| 113 | * while ((*dst++ = (tmp2 = *src++)) != 0 | ||
| 114 | * && --tmp1) | ||
| 115 | * ; | ||
| 116 | * | ||
| 117 | * res = count - tmp1; | ||
| 118 | * | ||
| 119 | * with tweaks. | ||
| 120 | */ | ||
| 121 | |||
| 122 | __asm__ __volatile__ ( | ||
| 123 | " move.d %3,%0\n" | ||
| 124 | "5: move.b [%2+],$acr\n" | ||
| 125 | "1: beq 2f\n" | ||
| 126 | " move.b $acr,[%1+]\n" | ||
| 127 | |||
| 128 | " subq 1,%0\n" | ||
| 129 | "2: bne 1b\n" | ||
| 130 | " move.b [%2+],$acr\n" | ||
| 131 | |||
| 132 | " sub.d %3,%0\n" | ||
| 133 | " neg.d %0,%0\n" | ||
| 134 | "3:\n" | ||
| 135 | " .section .fixup,\"ax\"\n" | ||
| 136 | "4: move.d %7,%0\n" | ||
| 137 | " jump 3b\n" | ||
| 138 | " nop\n" | ||
| 139 | |||
| 140 | /* The address for a fault at the first move is trivial. | ||
| 141 | The address for a fault at the second move is that of | ||
| 142 | the preceding branch insn, since the move insn is in | ||
| 143 | its delay-slot. That address is also a branch | ||
| 144 | target. Just so you don't get confused... */ | ||
| 145 | " .previous\n" | ||
| 146 | " .section __ex_table,\"a\"\n" | ||
| 147 | " .dword 5b,4b\n" | ||
| 148 | " .dword 2b,4b\n" | ||
| 149 | " .previous" | ||
| 150 | : "=r" (res), "=b" (dst), "=b" (src), "=r" (count) | ||
| 151 | : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) | ||
| 152 | : "acr"); | ||
| 153 | |||
| 154 | return res; | ||
| 155 | } | ||
| 156 | |||
| 157 | /* A few copy asms to build up the more complex ones from. | ||
| 158 | |||
| 159 | Note again, a post-increment is performed regardless of whether a bus | ||
| 160 | fault occurred in that instruction, and PC for a faulted insn is the | ||
| 161 | address for the insn, or for the preceding branch when in a delay-slot. */ | ||
| 162 | |||
| 163 | #define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 164 | __asm__ __volatile__ ( \ | ||
| 165 | COPY \ | ||
| 166 | "1:\n" \ | ||
| 167 | " .section .fixup,\"ax\"\n" \ | ||
| 168 | FIXUP \ | ||
| 169 | " .previous\n" \ | ||
| 170 | " .section __ex_table,\"a\"\n" \ | ||
| 171 | TENTRY \ | ||
| 172 | " .previous\n" \ | ||
| 173 | : "=b" (to), "=b" (from), "=r" (ret) \ | ||
| 174 | : "0" (to), "1" (from), "2" (ret) \ | ||
| 175 | : "acr", "memory") | ||
| 176 | |||
| 177 | #define __asm_copy_from_user_1(to, from, ret) \ | ||
| 178 | __asm_copy_user_cont(to, from, ret, \ | ||
| 179 | "2: move.b [%1+],$acr\n" \ | ||
| 180 | " move.b $acr,[%0+]\n", \ | ||
| 181 | "3: addq 1,%2\n" \ | ||
| 182 | " jump 1b\n" \ | ||
| 183 | " clear.b [%0+]\n", \ | ||
| 184 | " .dword 2b,3b\n") | ||
| 185 | |||
| 186 | #define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 187 | __asm_copy_user_cont(to, from, ret, \ | ||
| 188 | COPY \ | ||
| 189 | "2: move.w [%1+],$acr\n" \ | ||
| 190 | " move.w $acr,[%0+]\n", \ | ||
| 191 | FIXUP \ | ||
| 192 | "3: addq 2,%2\n" \ | ||
| 193 | " jump 1b\n" \ | ||
| 194 | " clear.w [%0+]\n", \ | ||
| 195 | TENTRY \ | ||
| 196 | " .dword 2b,3b\n") | ||
| 197 | |||
| 198 | #define __asm_copy_from_user_2(to, from, ret) \ | ||
| 199 | __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") | ||
| 200 | |||
| 201 | #define __asm_copy_from_user_3(to, from, ret) \ | ||
| 202 | __asm_copy_from_user_2x_cont(to, from, ret, \ | ||
| 203 | "4: move.b [%1+],$acr\n" \ | ||
| 204 | " move.b $acr,[%0+]\n", \ | ||
| 205 | "5: addq 1,%2\n" \ | ||
| 206 | " clear.b [%0+]\n", \ | ||
| 207 | " .dword 4b,5b\n") | ||
| 208 | |||
| 209 | #define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 210 | __asm_copy_user_cont(to, from, ret, \ | ||
| 211 | COPY \ | ||
| 212 | "2: move.d [%1+],$acr\n" \ | ||
| 213 | " move.d $acr,[%0+]\n", \ | ||
| 214 | FIXUP \ | ||
| 215 | "3: addq 4,%2\n" \ | ||
| 216 | " jump 1b\n" \ | ||
| 217 | " clear.d [%0+]\n", \ | ||
| 218 | TENTRY \ | ||
| 219 | " .dword 2b,3b\n") | ||
| 220 | |||
| 221 | #define __asm_copy_from_user_4(to, from, ret) \ | ||
| 222 | __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") | ||
| 223 | |||
| 224 | #define __asm_copy_from_user_5(to, from, ret) \ | ||
| 225 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 226 | "4: move.b [%1+],$acr\n" \ | ||
| 227 | " move.b $acr,[%0+]\n", \ | ||
| 228 | "5: addq 1,%2\n" \ | ||
| 229 | " clear.b [%0+]\n", \ | ||
| 230 | " .dword 4b,5b\n") | ||
| 231 | |||
| 232 | #define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 233 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 234 | COPY \ | ||
| 235 | "4: move.w [%1+],$acr\n" \ | ||
| 236 | " move.w $acr,[%0+]\n", \ | ||
| 237 | FIXUP \ | ||
| 238 | "5: addq 2,%2\n" \ | ||
| 239 | " clear.w [%0+]\n", \ | ||
| 240 | TENTRY \ | ||
| 241 | " .dword 4b,5b\n") | ||
| 242 | |||
| 243 | #define __asm_copy_from_user_6(to, from, ret) \ | ||
| 244 | __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") | ||
| 245 | |||
| 246 | #define __asm_copy_from_user_7(to, from, ret) \ | ||
| 247 | __asm_copy_from_user_6x_cont(to, from, ret, \ | ||
| 248 | "6: move.b [%1+],$acr\n" \ | ||
| 249 | " move.b $acr,[%0+]\n", \ | ||
| 250 | "7: addq 1,%2\n" \ | ||
| 251 | " clear.b [%0+]\n", \ | ||
| 252 | " .dword 6b,7b\n") | ||
| 253 | |||
| 254 | #define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 255 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 256 | COPY \ | ||
| 257 | "4: move.d [%1+],$acr\n" \ | ||
| 258 | " move.d $acr,[%0+]\n", \ | ||
| 259 | FIXUP \ | ||
| 260 | "5: addq 4,%2\n" \ | ||
| 261 | " clear.d [%0+]\n", \ | ||
| 262 | TENTRY \ | ||
| 263 | " .dword 4b,5b\n") | ||
| 264 | |||
| 265 | #define __asm_copy_from_user_8(to, from, ret) \ | ||
| 266 | __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") | ||
| 267 | |||
| 268 | #define __asm_copy_from_user_9(to, from, ret) \ | ||
| 269 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 270 | "6: move.b [%1+],$acr\n" \ | ||
| 271 | " move.b $acr,[%0+]\n", \ | ||
| 272 | "7: addq 1,%2\n" \ | ||
| 273 | " clear.b [%0+]\n", \ | ||
| 274 | " .dword 6b,7b\n") | ||
| 275 | |||
| 276 | #define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 277 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 278 | COPY \ | ||
| 279 | "6: move.w [%1+],$acr\n" \ | ||
| 280 | " move.w $acr,[%0+]\n", \ | ||
| 281 | FIXUP \ | ||
| 282 | "7: addq 2,%2\n" \ | ||
| 283 | " clear.w [%0+]\n", \ | ||
| 284 | TENTRY \ | ||
| 285 | " .dword 6b,7b\n") | ||
| 286 | |||
| 287 | #define __asm_copy_from_user_10(to, from, ret) \ | ||
| 288 | __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") | ||
| 289 | |||
| 290 | #define __asm_copy_from_user_11(to, from, ret) \ | ||
| 291 | __asm_copy_from_user_10x_cont(to, from, ret, \ | ||
| 292 | "8: move.b [%1+],$acr\n" \ | ||
| 293 | " move.b $acr,[%0+]\n", \ | ||
| 294 | "9: addq 1,%2\n" \ | ||
| 295 | " clear.b [%0+]\n", \ | ||
| 296 | " .dword 8b,9b\n") | ||
| 297 | |||
| 298 | #define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 299 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 300 | COPY \ | ||
| 301 | "6: move.d [%1+],$acr\n" \ | ||
| 302 | " move.d $acr,[%0+]\n", \ | ||
| 303 | FIXUP \ | ||
| 304 | "7: addq 4,%2\n" \ | ||
| 305 | " clear.d [%0+]\n", \ | ||
| 306 | TENTRY \ | ||
| 307 | " .dword 6b,7b\n") | ||
| 308 | |||
| 309 | #define __asm_copy_from_user_12(to, from, ret) \ | ||
| 310 | __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") | ||
| 311 | |||
| 312 | #define __asm_copy_from_user_13(to, from, ret) \ | ||
| 313 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 314 | "8: move.b [%1+],$acr\n" \ | ||
| 315 | " move.b $acr,[%0+]\n", \ | ||
| 316 | "9: addq 1,%2\n" \ | ||
| 317 | " clear.b [%0+]\n", \ | ||
| 318 | " .dword 8b,9b\n") | ||
| 319 | |||
| 320 | #define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 321 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 322 | COPY \ | ||
| 323 | "8: move.w [%1+],$acr\n" \ | ||
| 324 | " move.w $acr,[%0+]\n", \ | ||
| 325 | FIXUP \ | ||
| 326 | "9: addq 2,%2\n" \ | ||
| 327 | " clear.w [%0+]\n", \ | ||
| 328 | TENTRY \ | ||
| 329 | " .dword 8b,9b\n") | ||
| 330 | |||
| 331 | #define __asm_copy_from_user_14(to, from, ret) \ | ||
| 332 | __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") | ||
| 333 | |||
| 334 | #define __asm_copy_from_user_15(to, from, ret) \ | ||
| 335 | __asm_copy_from_user_14x_cont(to, from, ret, \ | ||
| 336 | "10: move.b [%1+],$acr\n" \ | ||
| 337 | " move.b $acr,[%0+]\n", \ | ||
| 338 | "11: addq 1,%2\n" \ | ||
| 339 | " clear.b [%0+]\n", \ | ||
| 340 | " .dword 10b,11b\n") | ||
| 341 | |||
| 342 | #define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 343 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 344 | COPY \ | ||
| 345 | "8: move.d [%1+],$acr\n" \ | ||
| 346 | " move.d $acr,[%0+]\n", \ | ||
| 347 | FIXUP \ | ||
| 348 | "9: addq 4,%2\n" \ | ||
| 349 | " clear.d [%0+]\n", \ | ||
| 350 | TENTRY \ | ||
| 351 | " .dword 8b,9b\n") | ||
| 352 | |||
| 353 | #define __asm_copy_from_user_16(to, from, ret) \ | ||
| 354 | __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") | ||
| 355 | |||
| 356 | #define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 357 | __asm_copy_from_user_16x_cont(to, from, ret, \ | ||
| 358 | COPY \ | ||
| 359 | "10: move.d [%1+],$acr\n" \ | ||
| 360 | " move.d $acr,[%0+]\n", \ | ||
| 361 | FIXUP \ | ||
| 362 | "11: addq 4,%2\n" \ | ||
| 363 | " clear.d [%0+]\n", \ | ||
| 364 | TENTRY \ | ||
| 365 | " .dword 10b,11b\n") | ||
| 366 | |||
| 367 | #define __asm_copy_from_user_20(to, from, ret) \ | ||
| 368 | __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") | ||
| 369 | |||
| 370 | #define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 371 | __asm_copy_from_user_20x_cont(to, from, ret, \ | ||
| 372 | COPY \ | ||
| 373 | "12: move.d [%1+],$acr\n" \ | ||
| 374 | " move.d $acr,[%0+]\n", \ | ||
| 375 | FIXUP \ | ||
| 376 | "13: addq 4,%2\n" \ | ||
| 377 | " clear.d [%0+]\n", \ | ||
| 378 | TENTRY \ | ||
| 379 | " .dword 12b,13b\n") | ||
| 380 | |||
| 381 | #define __asm_copy_from_user_24(to, from, ret) \ | ||
| 382 | __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") | ||
| 383 | |||
| 384 | /* And now, the to-user ones. */ | ||
| 385 | |||
| 386 | #define __asm_copy_to_user_1(to, from, ret) \ | ||
| 387 | __asm_copy_user_cont(to, from, ret, \ | ||
| 388 | " move.b [%1+],$acr\n" \ | ||
| 389 | "2: move.b $acr,[%0+]\n", \ | ||
| 390 | "3: jump 1b\n" \ | ||
| 391 | " addq 1,%2\n", \ | ||
| 392 | " .dword 2b,3b\n") | ||
| 393 | |||
| 394 | #define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 395 | __asm_copy_user_cont(to, from, ret, \ | ||
| 396 | COPY \ | ||
| 397 | " move.w [%1+],$acr\n" \ | ||
| 398 | "2: move.w $acr,[%0+]\n", \ | ||
| 399 | FIXUP \ | ||
| 400 | "3: jump 1b\n" \ | ||
| 401 | " addq 2,%2\n", \ | ||
| 402 | TENTRY \ | ||
| 403 | " .dword 2b,3b\n") | ||
| 404 | |||
| 405 | #define __asm_copy_to_user_2(to, from, ret) \ | ||
| 406 | __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") | ||
| 407 | |||
| 408 | #define __asm_copy_to_user_3(to, from, ret) \ | ||
| 409 | __asm_copy_to_user_2x_cont(to, from, ret, \ | ||
| 410 | " move.b [%1+],$acr\n" \ | ||
| 411 | "4: move.b $acr,[%0+]\n", \ | ||
| 412 | "5: addq 1,%2\n", \ | ||
| 413 | " .dword 4b,5b\n") | ||
| 414 | |||
| 415 | #define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 416 | __asm_copy_user_cont(to, from, ret, \ | ||
| 417 | COPY \ | ||
| 418 | " move.d [%1+],$acr\n" \ | ||
| 419 | "2: move.d $acr,[%0+]\n", \ | ||
| 420 | FIXUP \ | ||
| 421 | "3: jump 1b\n" \ | ||
| 422 | " addq 4,%2\n", \ | ||
| 423 | TENTRY \ | ||
| 424 | " .dword 2b,3b\n") | ||
| 425 | |||
| 426 | #define __asm_copy_to_user_4(to, from, ret) \ | ||
| 427 | __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") | ||
| 428 | |||
| 429 | #define __asm_copy_to_user_5(to, from, ret) \ | ||
| 430 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 431 | " move.b [%1+],$acr\n" \ | ||
| 432 | "4: move.b $acr,[%0+]\n", \ | ||
| 433 | "5: addq 1,%2\n", \ | ||
| 434 | " .dword 4b,5b\n") | ||
| 435 | |||
| 436 | #define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 437 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 438 | COPY \ | ||
| 439 | " move.w [%1+],$acr\n" \ | ||
| 440 | "4: move.w $acr,[%0+]\n", \ | ||
| 441 | FIXUP \ | ||
| 442 | "5: addq 2,%2\n", \ | ||
| 443 | TENTRY \ | ||
| 444 | " .dword 4b,5b\n") | ||
| 445 | |||
| 446 | #define __asm_copy_to_user_6(to, from, ret) \ | ||
| 447 | __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") | ||
| 448 | |||
| 449 | #define __asm_copy_to_user_7(to, from, ret) \ | ||
| 450 | __asm_copy_to_user_6x_cont(to, from, ret, \ | ||
| 451 | " move.b [%1+],$acr\n" \ | ||
| 452 | "6: move.b $acr,[%0+]\n", \ | ||
| 453 | "7: addq 1,%2\n", \ | ||
| 454 | " .dword 6b,7b\n") | ||
| 455 | |||
| 456 | #define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 457 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 458 | COPY \ | ||
| 459 | " move.d [%1+],$acr\n" \ | ||
| 460 | "4: move.d $acr,[%0+]\n", \ | ||
| 461 | FIXUP \ | ||
| 462 | "5: addq 4,%2\n", \ | ||
| 463 | TENTRY \ | ||
| 464 | " .dword 4b,5b\n") | ||
| 465 | |||
| 466 | #define __asm_copy_to_user_8(to, from, ret) \ | ||
| 467 | __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") | ||
| 468 | |||
| 469 | #define __asm_copy_to_user_9(to, from, ret) \ | ||
| 470 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 471 | " move.b [%1+],$acr\n" \ | ||
| 472 | "6: move.b $acr,[%0+]\n", \ | ||
| 473 | "7: addq 1,%2\n", \ | ||
| 474 | " .dword 6b,7b\n") | ||
| 475 | |||
| 476 | #define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 477 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 478 | COPY \ | ||
| 479 | " move.w [%1+],$acr\n" \ | ||
| 480 | "6: move.w $acr,[%0+]\n", \ | ||
| 481 | FIXUP \ | ||
| 482 | "7: addq 2,%2\n", \ | ||
| 483 | TENTRY \ | ||
| 484 | " .dword 6b,7b\n") | ||
| 485 | |||
| 486 | #define __asm_copy_to_user_10(to, from, ret) \ | ||
| 487 | __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") | ||
| 488 | |||
| 489 | #define __asm_copy_to_user_11(to, from, ret) \ | ||
| 490 | __asm_copy_to_user_10x_cont(to, from, ret, \ | ||
| 491 | " move.b [%1+],$acr\n" \ | ||
| 492 | "8: move.b $acr,[%0+]\n", \ | ||
| 493 | "9: addq 1,%2\n", \ | ||
| 494 | " .dword 8b,9b\n") | ||
| 495 | |||
| 496 | #define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 497 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 498 | COPY \ | ||
| 499 | " move.d [%1+],$acr\n" \ | ||
| 500 | "6: move.d $acr,[%0+]\n", \ | ||
| 501 | FIXUP \ | ||
| 502 | "7: addq 4,%2\n", \ | ||
| 503 | TENTRY \ | ||
| 504 | " .dword 6b,7b\n") | ||
| 505 | |||
| 506 | #define __asm_copy_to_user_12(to, from, ret) \ | ||
| 507 | __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") | ||
| 508 | |||
| 509 | #define __asm_copy_to_user_13(to, from, ret) \ | ||
| 510 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 511 | " move.b [%1+],$acr\n" \ | ||
| 512 | "8: move.b $acr,[%0+]\n", \ | ||
| 513 | "9: addq 1,%2\n", \ | ||
| 514 | " .dword 8b,9b\n") | ||
| 515 | |||
| 516 | #define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 517 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 518 | COPY \ | ||
| 519 | " move.w [%1+],$acr\n" \ | ||
| 520 | "8: move.w $acr,[%0+]\n", \ | ||
| 521 | FIXUP \ | ||
| 522 | "9: addq 2,%2\n", \ | ||
| 523 | TENTRY \ | ||
| 524 | " .dword 8b,9b\n") | ||
| 525 | |||
| 526 | #define __asm_copy_to_user_14(to, from, ret) \ | ||
| 527 | __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") | ||
| 528 | |||
| 529 | #define __asm_copy_to_user_15(to, from, ret) \ | ||
| 530 | __asm_copy_to_user_14x_cont(to, from, ret, \ | ||
| 531 | " move.b [%1+],$acr\n" \ | ||
| 532 | "10: move.b $acr,[%0+]\n", \ | ||
| 533 | "11: addq 1,%2\n", \ | ||
| 534 | " .dword 10b,11b\n") | ||
| 535 | |||
| 536 | #define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 537 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 538 | COPY \ | ||
| 539 | " move.d [%1+],$acr\n" \ | ||
| 540 | "8: move.d $acr,[%0+]\n", \ | ||
| 541 | FIXUP \ | ||
| 542 | "9: addq 4,%2\n", \ | ||
| 543 | TENTRY \ | ||
| 544 | " .dword 8b,9b\n") | ||
| 545 | |||
| 546 | #define __asm_copy_to_user_16(to, from, ret) \ | ||
| 547 | __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") | ||
| 548 | |||
| 549 | #define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 550 | __asm_copy_to_user_16x_cont(to, from, ret, \ | ||
| 551 | COPY \ | ||
| 552 | " move.d [%1+],$acr\n" \ | ||
| 553 | "10: move.d $acr,[%0+]\n", \ | ||
| 554 | FIXUP \ | ||
| 555 | "11: addq 4,%2\n", \ | ||
| 556 | TENTRY \ | ||
| 557 | " .dword 10b,11b\n") | ||
| 558 | |||
| 559 | #define __asm_copy_to_user_20(to, from, ret) \ | ||
| 560 | __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") | ||
| 561 | |||
| 562 | #define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 563 | __asm_copy_to_user_20x_cont(to, from, ret, \ | ||
| 564 | COPY \ | ||
| 565 | " move.d [%1+],$acr\n" \ | ||
| 566 | "12: move.d $acr,[%0+]\n", \ | ||
| 567 | FIXUP \ | ||
| 568 | "13: addq 4,%2\n", \ | ||
| 569 | TENTRY \ | ||
| 570 | " .dword 12b,13b\n") | ||
| 571 | |||
| 572 | #define __asm_copy_to_user_24(to, from, ret) \ | ||
| 573 | __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") | ||
| 574 | |||
| 575 | /* Define a few clearing asms with exception handlers. */ | ||
| 576 | |||
| 577 | /* This frame-asm is like the __asm_copy_user_cont one, but has one less | ||
| 578 | input. */ | ||
| 579 | |||
| 580 | #define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 581 | __asm__ __volatile__ ( \ | ||
| 582 | CLEAR \ | ||
| 583 | "1:\n" \ | ||
| 584 | " .section .fixup,\"ax\"\n" \ | ||
| 585 | FIXUP \ | ||
| 586 | " .previous\n" \ | ||
| 587 | " .section __ex_table,\"a\"\n" \ | ||
| 588 | TENTRY \ | ||
| 589 | " .previous" \ | ||
| 590 | : "=b" (to), "=r" (ret) \ | ||
| 591 | : "0" (to), "1" (ret) \ | ||
| 592 | : "memory") | ||
| 593 | |||
| 594 | #define __asm_clear_1(to, ret) \ | ||
| 595 | __asm_clear(to, ret, \ | ||
| 596 | "2: clear.b [%0+]\n", \ | ||
| 597 | "3: jump 1b\n" \ | ||
| 598 | " addq 1,%1\n", \ | ||
| 599 | " .dword 2b,3b\n") | ||
| 600 | |||
| 601 | #define __asm_clear_2(to, ret) \ | ||
| 602 | __asm_clear(to, ret, \ | ||
| 603 | "2: clear.w [%0+]\n", \ | ||
| 604 | "3: jump 1b\n" \ | ||
| 605 | " addq 2,%1\n", \ | ||
| 606 | " .dword 2b,3b\n") | ||
| 607 | |||
| 608 | #define __asm_clear_3(to, ret) \ | ||
| 609 | __asm_clear(to, ret, \ | ||
| 610 | "2: clear.w [%0+]\n" \ | ||
| 611 | "3: clear.b [%0+]\n", \ | ||
| 612 | "4: addq 2,%1\n" \ | ||
| 613 | "5: jump 1b\n" \ | ||
| 614 | " addq 1,%1\n", \ | ||
| 615 | " .dword 2b,4b\n" \ | ||
| 616 | " .dword 3b,5b\n") | ||
| 617 | |||
| 618 | #define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 619 | __asm_clear(to, ret, \ | ||
| 620 | CLEAR \ | ||
| 621 | "2: clear.d [%0+]\n", \ | ||
| 622 | FIXUP \ | ||
| 623 | "3: jump 1b\n" \ | ||
| 624 | " addq 4,%1\n", \ | ||
| 625 | TENTRY \ | ||
| 626 | " .dword 2b,3b\n") | ||
| 627 | |||
| 628 | #define __asm_clear_4(to, ret) \ | ||
| 629 | __asm_clear_4x_cont(to, ret, "", "", "") | ||
| 630 | |||
| 631 | #define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 632 | __asm_clear_4x_cont(to, ret, \ | ||
| 633 | CLEAR \ | ||
| 634 | "4: clear.d [%0+]\n", \ | ||
| 635 | FIXUP \ | ||
| 636 | "5: addq 4,%1\n", \ | ||
| 637 | TENTRY \ | ||
| 638 | " .dword 4b,5b\n") | ||
| 639 | |||
| 640 | #define __asm_clear_8(to, ret) \ | ||
| 641 | __asm_clear_8x_cont(to, ret, "", "", "") | ||
| 642 | |||
| 643 | #define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 644 | __asm_clear_8x_cont(to, ret, \ | ||
| 645 | CLEAR \ | ||
| 646 | "6: clear.d [%0+]\n", \ | ||
| 647 | FIXUP \ | ||
| 648 | "7: addq 4,%1\n", \ | ||
| 649 | TENTRY \ | ||
| 650 | " .dword 6b,7b\n") | ||
| 651 | |||
| 652 | #define __asm_clear_12(to, ret) \ | ||
| 653 | __asm_clear_12x_cont(to, ret, "", "", "") | ||
| 654 | |||
| 655 | #define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 656 | __asm_clear_12x_cont(to, ret, \ | ||
| 657 | CLEAR \ | ||
| 658 | "8: clear.d [%0+]\n", \ | ||
| 659 | FIXUP \ | ||
| 660 | "9: addq 4,%1\n", \ | ||
| 661 | TENTRY \ | ||
| 662 | " .dword 8b,9b\n") | ||
| 663 | |||
| 664 | #define __asm_clear_16(to, ret) \ | ||
| 665 | __asm_clear_16x_cont(to, ret, "", "", "") | ||
| 666 | |||
| 667 | #define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 668 | __asm_clear_16x_cont(to, ret, \ | ||
| 669 | CLEAR \ | ||
| 670 | "10: clear.d [%0+]\n", \ | ||
| 671 | FIXUP \ | ||
| 672 | "11: addq 4,%1\n", \ | ||
| 673 | TENTRY \ | ||
| 674 | " .dword 10b,11b\n") | ||
| 675 | |||
| 676 | #define __asm_clear_20(to, ret) \ | ||
| 677 | __asm_clear_20x_cont(to, ret, "", "", "") | ||
| 678 | |||
| 679 | #define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 680 | __asm_clear_20x_cont(to, ret, \ | ||
| 681 | CLEAR \ | ||
| 682 | "12: clear.d [%0+]\n", \ | ||
| 683 | FIXUP \ | ||
| 684 | "13: addq 4,%1\n", \ | ||
| 685 | TENTRY \ | ||
| 686 | " .dword 12b,13b\n") | ||
| 687 | |||
| 688 | #define __asm_clear_24(to, ret) \ | ||
| 689 | __asm_clear_24x_cont(to, ret, "", "", "") | ||
| 690 | |||
| 691 | /* | ||
| 692 | * Return the size of a string (including the ending 0) | ||
| 693 | * | ||
| 694 | * Return length of string in userspace including terminating 0 | ||
| 695 | * or 0 for error. Return a value greater than N if too long. | ||
| 696 | */ | ||
| 697 | |||
| 698 | static inline long | ||
| 699 | strnlen_user(const char *s, long n) | ||
| 700 | { | ||
| 701 | long res, tmp1; | ||
| 702 | |||
| 703 | if (!access_ok(VERIFY_READ, s, 0)) | ||
| 704 | return 0; | ||
| 705 | |||
| 706 | /* | ||
| 707 | * This code is deduced from: | ||
| 708 | * | ||
| 709 | * tmp1 = n; | ||
| 710 | * while (tmp1-- > 0 && *s++) | ||
| 711 | * ; | ||
| 712 | * | ||
| 713 | * res = n - tmp1; | ||
| 714 | * | ||
| 715 | * (with tweaks). | ||
| 716 | */ | ||
| 717 | |||
| 718 | __asm__ __volatile__ ( | ||
| 719 | " move.d %1,$acr\n" | ||
| 720 | " cmpq 0,$acr\n" | ||
| 721 | "0:\n" | ||
| 722 | " ble 1f\n" | ||
| 723 | " subq 1,$acr\n" | ||
| 724 | |||
| 725 | "4: test.b [%0+]\n" | ||
| 726 | " bne 0b\n" | ||
| 727 | " cmpq 0,$acr\n" | ||
| 728 | "1:\n" | ||
| 729 | " move.d %1,%0\n" | ||
| 730 | " sub.d $acr,%0\n" | ||
| 731 | "2:\n" | ||
| 732 | " .section .fixup,\"ax\"\n" | ||
| 733 | |||
| 734 | "3: jump 2b\n" | ||
| 735 | " clear.d %0\n" | ||
| 736 | |||
| 737 | " .previous\n" | ||
| 738 | " .section __ex_table,\"a\"\n" | ||
| 739 | " .dword 4b,3b\n" | ||
| 740 | " .previous\n" | ||
| 741 | : "=r" (res), "=r" (tmp1) | ||
| 742 | : "0" (s), "1" (n) | ||
| 743 | : "acr"); | ||
| 744 | |||
| 745 | return res; | ||
| 746 | } | ||
| 747 | |||
| 748 | #endif | ||
diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h deleted file mode 100644 index 0051114c63c7..000000000000 --- a/include/asm-cris/arch-v32/unistd.h +++ /dev/null | |||
| @@ -1,155 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_UNISTD_H_ | ||
| 2 | #define _ASM_CRIS_ARCH_UNISTD_H_ | ||
| 3 | |||
| 4 | /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ | ||
| 5 | /* | ||
| 6 | * Don't remove the .ifnc tests; they are an insurance against | ||
| 7 | * any hard-to-spot gcc register allocation bugs. | ||
| 8 | */ | ||
| 9 | #define _syscall0(type,name) \ | ||
| 10 | type name(void) \ | ||
| 11 | { \ | ||
| 12 | register long __a __asm__ ("r10"); \ | ||
| 13 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 14 | __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ | ||
| 15 | ".err\n\t" \ | ||
| 16 | ".endif\n\t" \ | ||
| 17 | "break 13" \ | ||
| 18 | : "=r" (__a) \ | ||
| 19 | : "r" (__n_) \ | ||
| 20 | : "memory"); \ | ||
| 21 | if (__a >= 0) \ | ||
| 22 | return (type) __a; \ | ||
| 23 | errno = -__a; \ | ||
| 24 | return (type) -1; \ | ||
| 25 | } | ||
| 26 | |||
| 27 | #define _syscall1(type,name,type1,arg1) \ | ||
| 28 | type name(type1 arg1) \ | ||
| 29 | { \ | ||
| 30 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 31 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 32 | __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ | ||
| 33 | ".err\n\t" \ | ||
| 34 | ".endif\n\t" \ | ||
| 35 | "break 13" \ | ||
| 36 | : "=r" (__a) \ | ||
| 37 | : "r" (__n_), "0" (__a) \ | ||
| 38 | : "memory"); \ | ||
| 39 | if (__a >= 0) \ | ||
| 40 | return (type) __a; \ | ||
| 41 | errno = -__a; \ | ||
| 42 | return (type) -1; \ | ||
| 43 | } | ||
| 44 | |||
| 45 | #define _syscall2(type,name,type1,arg1,type2,arg2) \ | ||
| 46 | type name(type1 arg1,type2 arg2) \ | ||
| 47 | { \ | ||
| 48 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 49 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 50 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 51 | __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ | ||
| 52 | ".err\n\t" \ | ||
| 53 | ".endif\n\t" \ | ||
| 54 | "break 13" \ | ||
| 55 | : "=r" (__a) \ | ||
| 56 | : "r" (__n_), "0" (__a), "r" (__b) \ | ||
| 57 | : "memory"); \ | ||
| 58 | if (__a >= 0) \ | ||
| 59 | return (type) __a; \ | ||
| 60 | errno = -__a; \ | ||
| 61 | return (type) -1; \ | ||
| 62 | } | ||
| 63 | |||
| 64 | #define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ | ||
| 65 | type name(type1 arg1,type2 arg2,type3 arg3) \ | ||
| 66 | { \ | ||
| 67 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 68 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 69 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 70 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 71 | __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ | ||
| 72 | ".err\n\t" \ | ||
| 73 | ".endif\n\t" \ | ||
| 74 | "break 13" \ | ||
| 75 | : "=r" (__a) \ | ||
| 76 | : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \ | ||
| 77 | : "memory"); \ | ||
| 78 | if (__a >= 0) \ | ||
| 79 | return (type) __a; \ | ||
| 80 | errno = -__a; \ | ||
| 81 | return (type) -1; \ | ||
| 82 | } | ||
| 83 | |||
| 84 | #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ | ||
| 85 | type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ | ||
| 86 | { \ | ||
| 87 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 88 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 89 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 90 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 91 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 92 | __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ | ||
| 93 | ".err\n\t" \ | ||
| 94 | ".endif\n\t" \ | ||
| 95 | "break 13" \ | ||
| 96 | : "=r" (__a) \ | ||
| 97 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 98 | "r" (__c), "r" (__d)\ | ||
| 99 | : "memory"); \ | ||
| 100 | if (__a >= 0) \ | ||
| 101 | return (type) __a; \ | ||
| 102 | errno = -__a; \ | ||
| 103 | return (type) -1; \ | ||
| 104 | } | ||
| 105 | |||
| 106 | #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ | ||
| 107 | type5,arg5) \ | ||
| 108 | type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ | ||
| 109 | { \ | ||
| 110 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 111 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 112 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 113 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 114 | register long __e __asm__ ("mof") = (long) arg5; \ | ||
| 115 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 116 | __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \ | ||
| 117 | ".err\n\t" \ | ||
| 118 | ".endif\n\t" \ | ||
| 119 | "break 13" \ | ||
| 120 | : "=r" (__a) \ | ||
| 121 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 122 | "r" (__c), "r" (__d), "h" (__e) \ | ||
| 123 | : "memory"); \ | ||
| 124 | if (__a >= 0) \ | ||
| 125 | return (type) __a; \ | ||
| 126 | errno = -__a; \ | ||
| 127 | return (type) -1; \ | ||
| 128 | } | ||
| 129 | |||
| 130 | #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ | ||
| 131 | type5,arg5,type6,arg6) \ | ||
| 132 | type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ | ||
| 133 | { \ | ||
| 134 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 135 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 136 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 137 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 138 | register long __e __asm__ ("mof") = (long) arg5; \ | ||
| 139 | register long __f __asm__ ("srp") = (long) arg6; \ | ||
| 140 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 141 | __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \ | ||
| 142 | ".err\n\t" \ | ||
| 143 | ".endif\n\t" \ | ||
| 144 | "break 13" \ | ||
| 145 | : "=r" (__a) \ | ||
| 146 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 147 | "r" (__c), "r" (__d), "h" (__e), "x" (__f) \ | ||
| 148 | : "memory"); \ | ||
| 149 | if (__a >= 0) \ | ||
| 150 | return (type) __a; \ | ||
| 151 | errno = -__a; \ | ||
| 152 | return (type) -1; \ | ||
| 153 | } | ||
| 154 | |||
| 155 | #endif | ||
diff --git a/include/asm-cris/arch-v32/user.h b/include/asm-cris/arch-v32/user.h deleted file mode 100644 index 03fa1f3c3c00..000000000000 --- a/include/asm-cris/arch-v32/user.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_USER_H | ||
| 2 | #define _ASM_CRIS_ARCH_USER_H | ||
| 3 | |||
| 4 | /* User-mode register used for core dumps. */ | ||
| 5 | |||
| 6 | struct user_regs_struct { | ||
| 7 | unsigned long r0; /* General registers. */ | ||
| 8 | unsigned long r1; | ||
| 9 | unsigned long r2; | ||
| 10 | unsigned long r3; | ||
| 11 | unsigned long r4; | ||
| 12 | unsigned long r5; | ||
| 13 | unsigned long r6; | ||
| 14 | unsigned long r7; | ||
| 15 | unsigned long r8; | ||
| 16 | unsigned long r9; | ||
| 17 | unsigned long r10; | ||
| 18 | unsigned long r11; | ||
| 19 | unsigned long r12; | ||
| 20 | unsigned long r13; | ||
| 21 | unsigned long sp; /* R14, Stack pointer. */ | ||
| 22 | unsigned long acr; /* R15, Address calculation register. */ | ||
| 23 | unsigned long bz; /* P0, Constant zero (8-bits). */ | ||
| 24 | unsigned long vr; /* P1, Version register (8-bits). */ | ||
| 25 | unsigned long pid; /* P2, Process ID (8-bits). */ | ||
| 26 | unsigned long srs; /* P3, Support register select (8-bits). */ | ||
| 27 | unsigned long wz; /* P4, Constant zero (16-bits). */ | ||
| 28 | unsigned long exs; /* P5, Exception status. */ | ||
| 29 | unsigned long eda; /* P6, Exception data address. */ | ||
| 30 | unsigned long mof; /* P7, Multiply overflow regiter. */ | ||
| 31 | unsigned long dz; /* P8, Constant zero (32-bits). */ | ||
| 32 | unsigned long ebp; /* P9, Exception base pointer. */ | ||
| 33 | unsigned long erp; /* P10, Exception return pointer. */ | ||
| 34 | unsigned long srp; /* P11, Subroutine return pointer. */ | ||
| 35 | unsigned long nrp; /* P12, NMI return pointer. */ | ||
| 36 | unsigned long ccs; /* P13, Condition code stack. */ | ||
| 37 | unsigned long usp; /* P14, User mode stack pointer. */ | ||
| 38 | unsigned long spc; /* P15, Single step PC. */ | ||
| 39 | }; | ||
| 40 | |||
| 41 | #endif /* _ASM_CRIS_ARCH_USER_H */ | ||
diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h deleted file mode 100644 index 5fc87768774a..000000000000 --- a/include/asm-cris/atomic.h +++ /dev/null | |||
| @@ -1,164 +0,0 @@ | |||
| 1 | /* $Id: atomic.h,v 1.3 2001/07/25 16:15:19 bjornw Exp $ */ | ||
| 2 | |||
| 3 | #ifndef __ASM_CRIS_ATOMIC__ | ||
| 4 | #define __ASM_CRIS_ATOMIC__ | ||
| 5 | |||
| 6 | #include <linux/compiler.h> | ||
| 7 | |||
| 8 | #include <asm/system.h> | ||
| 9 | #include <asm/arch/atomic.h> | ||
| 10 | |||
| 11 | /* | ||
| 12 | * Atomic operations that C can't guarantee us. Useful for | ||
| 13 | * resource counting etc.. | ||
| 14 | */ | ||
| 15 | |||
| 16 | typedef struct { volatile int counter; } atomic_t; | ||
| 17 | |||
| 18 | #define ATOMIC_INIT(i) { (i) } | ||
| 19 | |||
| 20 | #define atomic_read(v) ((v)->counter) | ||
| 21 | #define atomic_set(v,i) (((v)->counter) = (i)) | ||
| 22 | |||
| 23 | /* These should be written in asm but we do it in C for now. */ | ||
| 24 | |||
| 25 | static inline void atomic_add(int i, volatile atomic_t *v) | ||
| 26 | { | ||
| 27 | unsigned long flags; | ||
| 28 | cris_atomic_save(v, flags); | ||
| 29 | v->counter += i; | ||
| 30 | cris_atomic_restore(v, flags); | ||
| 31 | } | ||
| 32 | |||
| 33 | static inline void atomic_sub(int i, volatile atomic_t *v) | ||
| 34 | { | ||
| 35 | unsigned long flags; | ||
| 36 | cris_atomic_save(v, flags); | ||
| 37 | v->counter -= i; | ||
| 38 | cris_atomic_restore(v, flags); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline int atomic_add_return(int i, volatile atomic_t *v) | ||
| 42 | { | ||
| 43 | unsigned long flags; | ||
| 44 | int retval; | ||
| 45 | cris_atomic_save(v, flags); | ||
| 46 | retval = (v->counter += i); | ||
| 47 | cris_atomic_restore(v, flags); | ||
| 48 | return retval; | ||
| 49 | } | ||
| 50 | |||
| 51 | #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) | ||
| 52 | |||
| 53 | static inline int atomic_sub_return(int i, volatile atomic_t *v) | ||
| 54 | { | ||
| 55 | unsigned long flags; | ||
| 56 | int retval; | ||
| 57 | cris_atomic_save(v, flags); | ||
| 58 | retval = (v->counter -= i); | ||
| 59 | cris_atomic_restore(v, flags); | ||
| 60 | return retval; | ||
| 61 | } | ||
| 62 | |||
| 63 | static inline int atomic_sub_and_test(int i, volatile atomic_t *v) | ||
| 64 | { | ||
| 65 | int retval; | ||
| 66 | unsigned long flags; | ||
| 67 | cris_atomic_save(v, flags); | ||
| 68 | retval = (v->counter -= i) == 0; | ||
| 69 | cris_atomic_restore(v, flags); | ||
| 70 | return retval; | ||
| 71 | } | ||
| 72 | |||
| 73 | static inline void atomic_inc(volatile atomic_t *v) | ||
| 74 | { | ||
| 75 | unsigned long flags; | ||
| 76 | cris_atomic_save(v, flags); | ||
| 77 | (v->counter)++; | ||
| 78 | cris_atomic_restore(v, flags); | ||
| 79 | } | ||
| 80 | |||
| 81 | static inline void atomic_dec(volatile atomic_t *v) | ||
| 82 | { | ||
| 83 | unsigned long flags; | ||
| 84 | cris_atomic_save(v, flags); | ||
| 85 | (v->counter)--; | ||
| 86 | cris_atomic_restore(v, flags); | ||
| 87 | } | ||
| 88 | |||
| 89 | static inline int atomic_inc_return(volatile atomic_t *v) | ||
| 90 | { | ||
| 91 | unsigned long flags; | ||
| 92 | int retval; | ||
| 93 | cris_atomic_save(v, flags); | ||
| 94 | retval = ++(v->counter); | ||
| 95 | cris_atomic_restore(v, flags); | ||
| 96 | return retval; | ||
| 97 | } | ||
| 98 | |||
| 99 | static inline int atomic_dec_return(volatile atomic_t *v) | ||
| 100 | { | ||
| 101 | unsigned long flags; | ||
| 102 | int retval; | ||
| 103 | cris_atomic_save(v, flags); | ||
| 104 | retval = --(v->counter); | ||
| 105 | cris_atomic_restore(v, flags); | ||
| 106 | return retval; | ||
| 107 | } | ||
| 108 | static inline int atomic_dec_and_test(volatile atomic_t *v) | ||
| 109 | { | ||
| 110 | int retval; | ||
| 111 | unsigned long flags; | ||
| 112 | cris_atomic_save(v, flags); | ||
| 113 | retval = --(v->counter) == 0; | ||
| 114 | cris_atomic_restore(v, flags); | ||
| 115 | return retval; | ||
| 116 | } | ||
| 117 | |||
| 118 | static inline int atomic_inc_and_test(volatile atomic_t *v) | ||
| 119 | { | ||
| 120 | int retval; | ||
| 121 | unsigned long flags; | ||
| 122 | cris_atomic_save(v, flags); | ||
| 123 | retval = ++(v->counter) == 0; | ||
| 124 | cris_atomic_restore(v, flags); | ||
| 125 | return retval; | ||
| 126 | } | ||
| 127 | |||
| 128 | static inline int atomic_cmpxchg(atomic_t *v, int old, int new) | ||
| 129 | { | ||
| 130 | int ret; | ||
| 131 | unsigned long flags; | ||
| 132 | |||
| 133 | cris_atomic_save(v, flags); | ||
| 134 | ret = v->counter; | ||
| 135 | if (likely(ret == old)) | ||
| 136 | v->counter = new; | ||
| 137 | cris_atomic_restore(v, flags); | ||
| 138 | return ret; | ||
| 139 | } | ||
| 140 | |||
| 141 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | ||
| 142 | |||
| 143 | static inline int atomic_add_unless(atomic_t *v, int a, int u) | ||
| 144 | { | ||
| 145 | int ret; | ||
| 146 | unsigned long flags; | ||
| 147 | |||
| 148 | cris_atomic_save(v, flags); | ||
| 149 | ret = v->counter; | ||
| 150 | if (ret != u) | ||
| 151 | v->counter += a; | ||
| 152 | cris_atomic_restore(v, flags); | ||
| 153 | return ret != u; | ||
| 154 | } | ||
| 155 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) | ||
| 156 | |||
| 157 | /* Atomic operations are already serializing */ | ||
| 158 | #define smp_mb__before_atomic_dec() barrier() | ||
| 159 | #define smp_mb__after_atomic_dec() barrier() | ||
| 160 | #define smp_mb__before_atomic_inc() barrier() | ||
| 161 | #define smp_mb__after_atomic_inc() barrier() | ||
| 162 | |||
| 163 | #include <asm-generic/atomic.h> | ||
| 164 | #endif | ||
diff --git a/include/asm-cris/auxvec.h b/include/asm-cris/auxvec.h deleted file mode 100644 index cb30b01bf19f..000000000000 --- a/include/asm-cris/auxvec.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | #ifndef __ASMCRIS_AUXVEC_H | ||
| 2 | #define __ASMCRIS_AUXVEC_H | ||
| 3 | |||
| 4 | #endif | ||
diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h deleted file mode 100644 index 015ca5445ddd..000000000000 --- a/include/asm-cris/axisflashmap.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | #ifndef __ASM_AXISFLASHMAP_H | ||
| 2 | #define __ASM_AXISFLASHMAP_H | ||
| 3 | |||
| 4 | /* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC | ||
| 5 | * as start, it ends with 0xFFFFFFFF */ | ||
| 6 | #define FLASH_BOOT_MAGIC 0xbeefcace | ||
| 7 | #define BOOTPARAM_OFFSET 0xc000 | ||
| 8 | /* apps/bootblocktool is used to read and write the parameters, | ||
| 9 | * and it has nothing to do with the partition table. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define PARTITION_TABLE_OFFSET 10 | ||
| 13 | #define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ | ||
| 14 | |||
| 15 | /* The partitiontable_head is located at offset +10: */ | ||
| 16 | struct partitiontable_head { | ||
| 17 | __u16 magic; /* PARTITION_TABLE_MAGIC */ | ||
| 18 | __u16 size; /* Length of ptable block (entries + end marker) */ | ||
| 19 | __u32 checksum; /* simple longword sum, over entries + end marker */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | /* And followed by partition table entries */ | ||
| 23 | struct partitiontable_entry { | ||
| 24 | __u32 offset; /* relative to the sector the ptable is in */ | ||
| 25 | __u32 size; /* in bytes */ | ||
| 26 | __u32 checksum; /* simple longword sum */ | ||
| 27 | __u16 type; /* see type codes below */ | ||
| 28 | __u16 flags; /* bit 0: ro/rw = 1/0 */ | ||
| 29 | __u32 future0; /* 16 bytes reserved for future use */ | ||
| 30 | __u32 future1; | ||
| 31 | __u32 future2; | ||
| 32 | __u32 future3; | ||
| 33 | }; | ||
| 34 | /* ended by an end marker: */ | ||
| 35 | #define PARTITIONTABLE_END_MARKER 0xFFFFFFFF | ||
| 36 | #define PARTITIONTABLE_END_MARKER_SIZE 4 | ||
| 37 | |||
| 38 | #define PARTITIONTABLE_END_PAD 10 | ||
| 39 | |||
| 40 | /* Complete structure for whole partition table */ | ||
| 41 | /* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting | ||
| 42 | * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER. | ||
| 43 | */ | ||
| 44 | struct partitiontable { | ||
| 45 | __u8 skip[PARTITION_TABLE_OFFSET]; | ||
| 46 | struct partitiontable_head head; | ||
| 47 | struct partitiontable_entry entries[]; | ||
| 48 | }; | ||
| 49 | |||
| 50 | #define PARTITION_TYPE_PARAM 0x0001 | ||
| 51 | #define PARTITION_TYPE_KERNEL 0x0002 | ||
| 52 | #define PARTITION_TYPE_JFFS 0x0003 | ||
| 53 | #define PARTITION_TYPE_JFFS2 0x0000 | ||
| 54 | |||
| 55 | #define PARTITION_FLAGS_READONLY_MASK 0x0001 | ||
| 56 | #define PARTITION_FLAGS_READONLY 0x0001 | ||
| 57 | |||
| 58 | /* The master mtd for the entire flash. */ | ||
| 59 | extern struct mtd_info *axisflash_mtd; | ||
| 60 | |||
| 61 | #endif | ||
diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h deleted file mode 100644 index 75ea6e096483..000000000000 --- a/include/asm-cris/bitops.h +++ /dev/null | |||
| @@ -1,166 +0,0 @@ | |||
| 1 | /* asm/bitops.h for Linux/CRIS | ||
| 2 | * | ||
| 3 | * TODO: asm versions if speed is needed | ||
| 4 | * | ||
| 5 | * All bit operations return 0 if the bit was cleared before the | ||
| 6 | * operation and != 0 if it was not. | ||
| 7 | * | ||
| 8 | * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef _CRIS_BITOPS_H | ||
| 12 | #define _CRIS_BITOPS_H | ||
| 13 | |||
| 14 | /* Currently this is unsuitable for consumption outside the kernel. */ | ||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #ifndef _LINUX_BITOPS_H | ||
| 18 | #error only <linux/bitops.h> can be included directly | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #include <asm/arch/bitops.h> | ||
| 22 | #include <asm/system.h> | ||
| 23 | #include <asm/atomic.h> | ||
| 24 | #include <linux/compiler.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * set_bit - Atomically set a bit in memory | ||
| 28 | * @nr: the bit to set | ||
| 29 | * @addr: the address to start counting from | ||
| 30 | * | ||
| 31 | * This function is atomic and may not be reordered. See __set_bit() | ||
| 32 | * if you do not require the atomic guarantees. | ||
| 33 | * Note that @nr may be almost arbitrarily large; this function is not | ||
| 34 | * restricted to acting on a single-word quantity. | ||
| 35 | */ | ||
| 36 | |||
| 37 | #define set_bit(nr, addr) (void)test_and_set_bit(nr, addr) | ||
| 38 | |||
| 39 | /* | ||
| 40 | * clear_bit - Clears a bit in memory | ||
| 41 | * @nr: Bit to clear | ||
| 42 | * @addr: Address to start counting from | ||
| 43 | * | ||
| 44 | * clear_bit() is atomic and may not be reordered. However, it does | ||
| 45 | * not contain a memory barrier, so if it is used for locking purposes, | ||
| 46 | * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() | ||
| 47 | * in order to ensure changes are visible on other processors. | ||
| 48 | */ | ||
| 49 | |||
| 50 | #define clear_bit(nr, addr) (void)test_and_clear_bit(nr, addr) | ||
| 51 | |||
| 52 | /* | ||
| 53 | * change_bit - Toggle a bit in memory | ||
| 54 | * @nr: Bit to change | ||
| 55 | * @addr: Address to start counting from | ||
| 56 | * | ||
| 57 | * change_bit() is atomic and may not be reordered. | ||
| 58 | * Note that @nr may be almost arbitrarily large; this function is not | ||
| 59 | * restricted to acting on a single-word quantity. | ||
| 60 | */ | ||
| 61 | |||
| 62 | #define change_bit(nr, addr) (void)test_and_change_bit(nr, addr) | ||
| 63 | |||
| 64 | /** | ||
| 65 | * test_and_set_bit - Set a bit and return its old value | ||
| 66 | * @nr: Bit to set | ||
| 67 | * @addr: Address to count from | ||
| 68 | * | ||
| 69 | * This operation is atomic and cannot be reordered. | ||
| 70 | * It also implies a memory barrier. | ||
| 71 | */ | ||
| 72 | |||
| 73 | static inline int test_and_set_bit(int nr, volatile unsigned long *addr) | ||
| 74 | { | ||
| 75 | unsigned int mask, retval; | ||
| 76 | unsigned long flags; | ||
| 77 | unsigned int *adr = (unsigned int *)addr; | ||
| 78 | |||
| 79 | adr += nr >> 5; | ||
| 80 | mask = 1 << (nr & 0x1f); | ||
| 81 | cris_atomic_save(addr, flags); | ||
| 82 | retval = (mask & *adr) != 0; | ||
| 83 | *adr |= mask; | ||
| 84 | cris_atomic_restore(addr, flags); | ||
| 85 | return retval; | ||
| 86 | } | ||
| 87 | |||
| 88 | /* | ||
| 89 | * clear_bit() doesn't provide any barrier for the compiler. | ||
| 90 | */ | ||
| 91 | #define smp_mb__before_clear_bit() barrier() | ||
| 92 | #define smp_mb__after_clear_bit() barrier() | ||
| 93 | |||
| 94 | /** | ||
| 95 | * test_and_clear_bit - Clear a bit and return its old value | ||
| 96 | * @nr: Bit to clear | ||
| 97 | * @addr: Address to count from | ||
| 98 | * | ||
| 99 | * This operation is atomic and cannot be reordered. | ||
| 100 | * It also implies a memory barrier. | ||
| 101 | */ | ||
| 102 | |||
| 103 | static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) | ||
| 104 | { | ||
| 105 | unsigned int mask, retval; | ||
| 106 | unsigned long flags; | ||
| 107 | unsigned int *adr = (unsigned int *)addr; | ||
| 108 | |||
| 109 | adr += nr >> 5; | ||
| 110 | mask = 1 << (nr & 0x1f); | ||
| 111 | cris_atomic_save(addr, flags); | ||
| 112 | retval = (mask & *adr) != 0; | ||
| 113 | *adr &= ~mask; | ||
| 114 | cris_atomic_restore(addr, flags); | ||
| 115 | return retval; | ||
| 116 | } | ||
| 117 | |||
| 118 | /** | ||
| 119 | * test_and_change_bit - Change a bit and return its old value | ||
| 120 | * @nr: Bit to change | ||
| 121 | * @addr: Address to count from | ||
| 122 | * | ||
| 123 | * This operation is atomic and cannot be reordered. | ||
| 124 | * It also implies a memory barrier. | ||
| 125 | */ | ||
| 126 | |||
| 127 | static inline int test_and_change_bit(int nr, volatile unsigned long *addr) | ||
| 128 | { | ||
| 129 | unsigned int mask, retval; | ||
| 130 | unsigned long flags; | ||
| 131 | unsigned int *adr = (unsigned int *)addr; | ||
| 132 | adr += nr >> 5; | ||
| 133 | mask = 1 << (nr & 0x1f); | ||
| 134 | cris_atomic_save(addr, flags); | ||
| 135 | retval = (mask & *adr) != 0; | ||
| 136 | *adr ^= mask; | ||
| 137 | cris_atomic_restore(addr, flags); | ||
| 138 | return retval; | ||
| 139 | } | ||
| 140 | |||
| 141 | #include <asm-generic/bitops/non-atomic.h> | ||
| 142 | |||
| 143 | /* | ||
| 144 | * Since we define it "external", it collides with the built-in | ||
| 145 | * definition, which doesn't have the same semantics. We don't want to | ||
| 146 | * use -fno-builtin, so just hide the name ffs. | ||
| 147 | */ | ||
| 148 | #define ffs kernel_ffs | ||
| 149 | |||
| 150 | #include <asm-generic/bitops/fls.h> | ||
| 151 | #include <asm-generic/bitops/fls64.h> | ||
| 152 | #include <asm-generic/bitops/hweight.h> | ||
| 153 | #include <asm-generic/bitops/find.h> | ||
| 154 | #include <asm-generic/bitops/lock.h> | ||
| 155 | |||
| 156 | #include <asm-generic/bitops/ext2-non-atomic.h> | ||
| 157 | |||
| 158 | #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) | ||
| 159 | #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) | ||
| 160 | |||
| 161 | #include <asm-generic/bitops/minix.h> | ||
| 162 | #include <asm-generic/bitops/sched.h> | ||
| 163 | |||
| 164 | #endif /* __KERNEL__ */ | ||
| 165 | |||
| 166 | #endif /* _CRIS_BITOPS_H */ | ||
diff --git a/include/asm-cris/bug.h b/include/asm-cris/bug.h deleted file mode 100644 index fee12d4ae683..000000000000 --- a/include/asm-cris/bug.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | #ifndef _CRIS_BUG_H | ||
| 2 | #define _CRIS_BUG_H | ||
| 3 | #include <asm/arch/bug.h> | ||
| 4 | #endif | ||
diff --git a/include/asm-cris/bugs.h b/include/asm-cris/bugs.h deleted file mode 100644 index c5907aac1007..000000000000 --- a/include/asm-cris/bugs.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $ | ||
| 2 | * | ||
| 3 | * include/asm-cris/bugs.h | ||
| 4 | * | ||
| 5 | * Copyright (C) 2001 Axis Communications AB | ||
| 6 | */ | ||
| 7 | |||
| 8 | /* | ||
| 9 | * This is included by init/main.c to check for architecture-dependent bugs. | ||
| 10 | * | ||
| 11 | * Needs: | ||
| 12 | * void check_bugs(void); | ||
| 13 | */ | ||
| 14 | |||
| 15 | static void check_bugs(void) | ||
| 16 | { | ||
| 17 | } | ||
| 18 | |||
| 19 | |||
| 20 | |||
| 21 | |||
diff --git a/include/asm-cris/byteorder.h b/include/asm-cris/byteorder.h deleted file mode 100644 index 0cd9db1cc888..000000000000 --- a/include/asm-cris/byteorder.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | #ifndef _CRIS_BYTEORDER_H | ||
| 2 | #define _CRIS_BYTEORDER_H | ||
| 3 | |||
| 4 | #ifdef __GNUC__ | ||
| 5 | |||
| 6 | #ifdef __KERNEL__ | ||
| 7 | #include <asm/arch/byteorder.h> | ||
| 8 | |||
| 9 | /* defines are necessary because the other files detect the presence | ||
| 10 | * of a defined __arch_swab32, not an inline | ||
| 11 | */ | ||
| 12 | #define __arch__swab32(x) ___arch__swab32(x) | ||
| 13 | #define __arch__swab16(x) ___arch__swab16(x) | ||
| 14 | #endif /* __KERNEL__ */ | ||
| 15 | |||
| 16 | #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) | ||
| 17 | # define __BYTEORDER_HAS_U64__ | ||
| 18 | # define __SWAB_64_THRU_32__ | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #endif /* __GNUC__ */ | ||
| 22 | |||
| 23 | #include <linux/byteorder/little_endian.h> | ||
| 24 | |||
| 25 | #endif | ||
| 26 | |||
| 27 | |||
diff --git a/include/asm-cris/cache.h b/include/asm-cris/cache.h deleted file mode 100644 index 46a3b26e205a..000000000000 --- a/include/asm-cris/cache.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _ASM_CACHE_H | ||
| 2 | #define _ASM_CACHE_H | ||
| 3 | |||
| 4 | #include <asm/arch/cache.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_CACHE_H */ | ||
diff --git a/include/asm-cris/cacheflush.h b/include/asm-cris/cacheflush.h deleted file mode 100644 index cf60e3f69f8d..000000000000 --- a/include/asm-cris/cacheflush.h +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | #ifndef _CRIS_CACHEFLUSH_H | ||
| 2 | #define _CRIS_CACHEFLUSH_H | ||
| 3 | |||
| 4 | /* Keep includes the same across arches. */ | ||
| 5 | #include <linux/mm.h> | ||
| 6 | |||
| 7 | /* The cache doesn't need to be flushed when TLB entries change because | ||
| 8 | * the cache is mapped to physical memory, not virtual memory | ||
| 9 | */ | ||
| 10 | #define flush_cache_all() do { } while (0) | ||
| 11 | #define flush_cache_mm(mm) do { } while (0) | ||
| 12 | #define flush_cache_dup_mm(mm) do { } while (0) | ||
| 13 | #define flush_cache_range(vma, start, end) do { } while (0) | ||
| 14 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) | ||
| 15 | #define flush_dcache_page(page) do { } while (0) | ||
| 16 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | ||
| 17 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | ||
| 18 | #define flush_icache_range(start, end) do { } while (0) | ||
| 19 | #define flush_icache_page(vma,pg) do { } while (0) | ||
| 20 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) | ||
| 21 | #define flush_cache_vmap(start, end) do { } while (0) | ||
| 22 | #define flush_cache_vunmap(start, end) do { } while (0) | ||
| 23 | |||
| 24 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | ||
| 25 | memcpy(dst, src, len) | ||
| 26 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | ||
| 27 | memcpy(dst, src, len) | ||
| 28 | |||
| 29 | int change_page_attr(struct page *page, int numpages, pgprot_t prot); | ||
| 30 | |||
| 31 | #endif /* _CRIS_CACHEFLUSH_H */ | ||
diff --git a/include/asm-cris/checksum.h b/include/asm-cris/checksum.h deleted file mode 100644 index c6c5be62c698..000000000000 --- a/include/asm-cris/checksum.h +++ /dev/null | |||
| @@ -1,83 +0,0 @@ | |||
| 1 | /* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */ | ||
| 2 | |||
| 3 | #ifndef _CRIS_CHECKSUM_H | ||
| 4 | #define _CRIS_CHECKSUM_H | ||
| 5 | |||
| 6 | #include <asm/arch/checksum.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * computes the checksum of a memory block at buff, length len, | ||
| 10 | * and adds in "sum" (32-bit) | ||
| 11 | * | ||
| 12 | * returns a 32-bit number suitable for feeding into itself | ||
| 13 | * or csum_tcpudp_magic | ||
| 14 | * | ||
| 15 | * this function must be called with even lengths, except | ||
| 16 | * for the last fragment, which may be odd | ||
| 17 | * | ||
| 18 | * it's best to have buff aligned on a 32-bit boundary | ||
| 19 | */ | ||
| 20 | __wsum csum_partial(const void *buff, int len, __wsum sum); | ||
| 21 | |||
| 22 | /* | ||
| 23 | * the same as csum_partial, but copies from src while it | ||
| 24 | * checksums | ||
| 25 | * | ||
| 26 | * here even more important to align src and dst on a 32-bit (or even | ||
| 27 | * better 64-bit) boundary | ||
| 28 | */ | ||
| 29 | |||
| 30 | __wsum csum_partial_copy_nocheck(const void *src, void *dst, | ||
| 31 | int len, __wsum sum); | ||
| 32 | |||
| 33 | /* | ||
| 34 | * Fold a partial checksum into a word | ||
| 35 | */ | ||
| 36 | |||
| 37 | static inline __sum16 csum_fold(__wsum csum) | ||
| 38 | { | ||
| 39 | u32 sum = (__force u32)csum; | ||
| 40 | sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ | ||
| 41 | sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ | ||
| 42 | return (__force __sum16)~sum; | ||
| 43 | } | ||
| 44 | |||
| 45 | extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, | ||
| 46 | int len, __wsum sum, | ||
| 47 | int *errptr); | ||
| 48 | |||
| 49 | /* | ||
| 50 | * This is a version of ip_compute_csum() optimized for IP headers, | ||
| 51 | * which always checksum on 4 octet boundaries. | ||
| 52 | * | ||
| 53 | */ | ||
| 54 | |||
| 55 | static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) | ||
| 56 | { | ||
| 57 | return csum_fold(csum_partial(iph, ihl * 4, 0)); | ||
| 58 | } | ||
| 59 | |||
| 60 | /* | ||
| 61 | * computes the checksum of the TCP/UDP pseudo-header | ||
| 62 | * returns a 16-bit checksum, already complemented | ||
| 63 | */ | ||
| 64 | |||
| 65 | static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, | ||
| 66 | unsigned short len, | ||
| 67 | unsigned short proto, | ||
| 68 | __wsum sum) | ||
| 69 | { | ||
| 70 | return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); | ||
| 71 | } | ||
| 72 | |||
| 73 | /* | ||
| 74 | * this routine is used for miscellaneous IP-like checksums, mainly | ||
| 75 | * in icmp.c | ||
| 76 | */ | ||
| 77 | |||
| 78 | static inline __sum16 ip_compute_csum(const void *buff, int len) | ||
| 79 | { | ||
| 80 | return csum_fold (csum_partial(buff, len, 0)); | ||
| 81 | } | ||
| 82 | |||
| 83 | #endif | ||
diff --git a/include/asm-cris/cputime.h b/include/asm-cris/cputime.h deleted file mode 100644 index 4446a65656fa..000000000000 --- a/include/asm-cris/cputime.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef __CRIS_CPUTIME_H | ||
| 2 | #define __CRIS_CPUTIME_H | ||
| 3 | |||
| 4 | #include <asm-generic/cputime.h> | ||
| 5 | |||
| 6 | #endif /* __CRIS_CPUTIME_H */ | ||
diff --git a/include/asm-cris/current.h b/include/asm-cris/current.h deleted file mode 100644 index 5f5c0efd00be..000000000000 --- a/include/asm-cris/current.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | #ifndef _CRIS_CURRENT_H | ||
| 2 | #define _CRIS_CURRENT_H | ||
| 3 | |||
| 4 | #include <linux/thread_info.h> | ||
| 5 | |||
| 6 | struct task_struct; | ||
| 7 | |||
| 8 | static inline struct task_struct * get_current(void) | ||
| 9 | { | ||
| 10 | return current_thread_info()->task; | ||
| 11 | } | ||
| 12 | |||
| 13 | #define current get_current() | ||
| 14 | |||
| 15 | #endif /* !(_CRIS_CURRENT_H) */ | ||
diff --git a/include/asm-cris/delay.h b/include/asm-cris/delay.h deleted file mode 100644 index 123e19aef49d..000000000000 --- a/include/asm-cris/delay.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | #ifndef _CRIS_DELAY_H | ||
| 2 | #define _CRIS_DELAY_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Copyright (C) 1998-2002 Axis Communications AB | ||
| 6 | * | ||
| 7 | * Delay routines, using a pre-computed "loops_per_second" value. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <asm/arch/delay.h> | ||
| 11 | |||
| 12 | /* Use only for very small delays ( < 1 msec). */ | ||
| 13 | |||
| 14 | extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ | ||
| 15 | |||
| 16 | /* May be defined by arch/delay.h. */ | ||
| 17 | #ifndef udelay | ||
| 18 | static inline void udelay(unsigned long usecs) | ||
| 19 | { | ||
| 20 | __delay(usecs * loops_per_usec); | ||
| 21 | } | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #endif /* defined(_CRIS_DELAY_H) */ | ||
| 25 | |||
| 26 | |||
| 27 | |||
diff --git a/include/asm-cris/device.h b/include/asm-cris/device.h deleted file mode 100644 index d8f9872b0e2d..000000000000 --- a/include/asm-cris/device.h +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Arch specific extensions to struct device | ||
| 3 | * | ||
| 4 | * This file is released under the GPLv2 | ||
| 5 | */ | ||
| 6 | #include <asm-generic/device.h> | ||
| 7 | |||
diff --git a/include/asm-cris/div64.h b/include/asm-cris/div64.h deleted file mode 100644 index 6cd978cefb28..000000000000 --- a/include/asm-cris/div64.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/div64.h> | ||
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h deleted file mode 100644 index da8ef8e8f842..000000000000 --- a/include/asm-cris/dma-mapping.h +++ /dev/null | |||
| @@ -1,170 +0,0 @@ | |||
| 1 | /* DMA mapping. Nothing tricky here, just virt_to_phys */ | ||
| 2 | |||
| 3 | #ifndef _ASM_CRIS_DMA_MAPPING_H | ||
| 4 | #define _ASM_CRIS_DMA_MAPPING_H | ||
| 5 | |||
| 6 | #include <linux/mm.h> | ||
| 7 | #include <linux/kernel.h> | ||
| 8 | |||
| 9 | #include <asm/cache.h> | ||
| 10 | #include <asm/io.h> | ||
| 11 | #include <asm/scatterlist.h> | ||
| 12 | |||
| 13 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) | ||
| 14 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | ||
| 15 | |||
| 16 | #ifdef CONFIG_PCI | ||
| 17 | #include <asm-generic/dma-coherent.h> | ||
| 18 | |||
| 19 | void *dma_alloc_coherent(struct device *dev, size_t size, | ||
| 20 | dma_addr_t *dma_handle, gfp_t flag); | ||
| 21 | |||
| 22 | void dma_free_coherent(struct device *dev, size_t size, | ||
| 23 | void *vaddr, dma_addr_t dma_handle); | ||
| 24 | #else | ||
| 25 | static inline void * | ||
| 26 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, | ||
| 27 | gfp_t flag) | ||
| 28 | { | ||
| 29 | BUG(); | ||
| 30 | return NULL; | ||
| 31 | } | ||
| 32 | |||
| 33 | static inline void | ||
| 34 | dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, | ||
| 35 | dma_addr_t dma_handle) | ||
| 36 | { | ||
| 37 | BUG(); | ||
| 38 | } | ||
| 39 | #endif | ||
| 40 | static inline dma_addr_t | ||
| 41 | dma_map_single(struct device *dev, void *ptr, size_t size, | ||
| 42 | enum dma_data_direction direction) | ||
| 43 | { | ||
| 44 | BUG_ON(direction == DMA_NONE); | ||
| 45 | return virt_to_phys(ptr); | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline void | ||
| 49 | dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, | ||
| 50 | enum dma_data_direction direction) | ||
| 51 | { | ||
| 52 | BUG_ON(direction == DMA_NONE); | ||
| 53 | } | ||
| 54 | |||
| 55 | static inline int | ||
| 56 | dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | ||
| 57 | enum dma_data_direction direction) | ||
| 58 | { | ||
| 59 | printk("Map sg\n"); | ||
| 60 | return nents; | ||
| 61 | } | ||
| 62 | |||
| 63 | static inline dma_addr_t | ||
| 64 | dma_map_page(struct device *dev, struct page *page, unsigned long offset, | ||
| 65 | size_t size, enum dma_data_direction direction) | ||
| 66 | { | ||
| 67 | BUG_ON(direction == DMA_NONE); | ||
| 68 | return page_to_phys(page) + offset; | ||
| 69 | } | ||
| 70 | |||
| 71 | static inline void | ||
| 72 | dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, | ||
| 73 | enum dma_data_direction direction) | ||
| 74 | { | ||
| 75 | BUG_ON(direction == DMA_NONE); | ||
| 76 | } | ||
| 77 | |||
| 78 | |||
| 79 | static inline void | ||
| 80 | dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, | ||
| 81 | enum dma_data_direction direction) | ||
| 82 | { | ||
| 83 | BUG_ON(direction == DMA_NONE); | ||
| 84 | } | ||
| 85 | |||
| 86 | static inline void | ||
| 87 | dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, | ||
| 88 | enum dma_data_direction direction) | ||
| 89 | { | ||
| 90 | } | ||
| 91 | |||
| 92 | static inline void | ||
| 93 | dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, | ||
| 94 | enum dma_data_direction direction) | ||
| 95 | { | ||
| 96 | } | ||
| 97 | |||
| 98 | static inline void | ||
| 99 | dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, | ||
| 100 | unsigned long offset, size_t size, | ||
| 101 | enum dma_data_direction direction) | ||
| 102 | { | ||
| 103 | } | ||
| 104 | |||
| 105 | static inline void | ||
| 106 | dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, | ||
| 107 | unsigned long offset, size_t size, | ||
| 108 | enum dma_data_direction direction) | ||
| 109 | { | ||
| 110 | } | ||
| 111 | |||
| 112 | static inline void | ||
| 113 | dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, | ||
| 114 | enum dma_data_direction direction) | ||
| 115 | { | ||
| 116 | } | ||
| 117 | |||
| 118 | static inline void | ||
| 119 | dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, | ||
| 120 | enum dma_data_direction direction) | ||
| 121 | { | ||
| 122 | } | ||
| 123 | |||
| 124 | static inline int | ||
| 125 | dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | ||
| 126 | { | ||
| 127 | return 0; | ||
| 128 | } | ||
| 129 | |||
| 130 | static inline int | ||
| 131 | dma_supported(struct device *dev, u64 mask) | ||
| 132 | { | ||
| 133 | /* | ||
| 134 | * we fall back to GFP_DMA when the mask isn't all 1s, | ||
| 135 | * so we can't guarantee allocations that must be | ||
| 136 | * within a tighter range than GFP_DMA.. | ||
| 137 | */ | ||
| 138 | if(mask < 0x00ffffff) | ||
| 139 | return 0; | ||
| 140 | |||
| 141 | return 1; | ||
| 142 | } | ||
| 143 | |||
| 144 | static inline int | ||
| 145 | dma_set_mask(struct device *dev, u64 mask) | ||
| 146 | { | ||
| 147 | if(!dev->dma_mask || !dma_supported(dev, mask)) | ||
| 148 | return -EIO; | ||
| 149 | |||
| 150 | *dev->dma_mask = mask; | ||
| 151 | |||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | static inline int | ||
| 156 | dma_get_cache_alignment(void) | ||
| 157 | { | ||
| 158 | return (1 << INTERNODE_CACHE_SHIFT); | ||
| 159 | } | ||
| 160 | |||
| 161 | #define dma_is_consistent(d, h) (1) | ||
| 162 | |||
| 163 | static inline void | ||
| 164 | dma_cache_sync(struct device *dev, void *vaddr, size_t size, | ||
| 165 | enum dma_data_direction direction) | ||
| 166 | { | ||
| 167 | } | ||
| 168 | |||
| 169 | |||
| 170 | #endif | ||
diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h deleted file mode 100644 index 6f188dc56138..000000000000 --- a/include/asm-cris/dma.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */ | ||
| 2 | |||
| 3 | #ifndef _ASM_DMA_H | ||
| 4 | #define _ASM_DMA_H | ||
| 5 | |||
| 6 | #include <asm/arch/dma.h> | ||
| 7 | |||
| 8 | /* it's useless on the Etrax, but unfortunately needed by the new | ||
| 9 | bootmem allocator (but this should do it for this) */ | ||
| 10 | |||
| 11 | #define MAX_DMA_ADDRESS PAGE_OFFSET | ||
| 12 | |||
| 13 | /* From PCI */ | ||
| 14 | |||
| 15 | #ifdef CONFIG_PCI | ||
| 16 | extern int isa_dma_bridge_buggy; | ||
| 17 | #else | ||
| 18 | #define isa_dma_bridge_buggy (0) | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #endif /* _ASM_DMA_H */ | ||
diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h deleted file mode 100644 index f0d17fbc81ba..000000000000 --- a/include/asm-cris/elf.h +++ /dev/null | |||
| @@ -1,93 +0,0 @@ | |||
| 1 | #ifndef __ASMCRIS_ELF_H | ||
| 2 | #define __ASMCRIS_ELF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * ELF register definitions.. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <asm/user.h> | ||
| 9 | |||
| 10 | #define R_CRIS_NONE 0 | ||
| 11 | #define R_CRIS_8 1 | ||
| 12 | #define R_CRIS_16 2 | ||
| 13 | #define R_CRIS_32 3 | ||
| 14 | #define R_CRIS_8_PCREL 4 | ||
| 15 | #define R_CRIS_16_PCREL 5 | ||
| 16 | #define R_CRIS_32_PCREL 6 | ||
| 17 | #define R_CRIS_GNU_VTINHERIT 7 | ||
| 18 | #define R_CRIS_GNU_VTENTRY 8 | ||
| 19 | #define R_CRIS_COPY 9 | ||
| 20 | #define R_CRIS_GLOB_DAT 10 | ||
| 21 | #define R_CRIS_JUMP_SLOT 11 | ||
| 22 | #define R_CRIS_RELATIVE 12 | ||
| 23 | #define R_CRIS_16_GOT 13 | ||
| 24 | #define R_CRIS_32_GOT 14 | ||
| 25 | #define R_CRIS_16_GOTPLT 15 | ||
| 26 | #define R_CRIS_32_GOTPLT 16 | ||
| 27 | #define R_CRIS_32_GOTREL 17 | ||
| 28 | #define R_CRIS_32_PLT_GOTREL 18 | ||
| 29 | #define R_CRIS_32_PLT_PCREL 19 | ||
| 30 | |||
| 31 | typedef unsigned long elf_greg_t; | ||
| 32 | |||
| 33 | /* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is | ||
| 34 | thus exposed to user-space. */ | ||
| 35 | #define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) | ||
| 36 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | ||
| 37 | |||
| 38 | /* A placeholder; CRIS does not have any fp regs. */ | ||
| 39 | typedef unsigned long elf_fpregset_t; | ||
| 40 | |||
| 41 | /* | ||
| 42 | * These are used to set parameters in the core dumps. | ||
| 43 | */ | ||
| 44 | #define ELF_CLASS ELFCLASS32 | ||
| 45 | #define ELF_DATA ELFDATA2LSB | ||
| 46 | #define ELF_ARCH EM_CRIS | ||
| 47 | |||
| 48 | #include <asm/arch/elf.h> | ||
| 49 | |||
| 50 | /* The master for these definitions is {binutils}/include/elf/cris.h: */ | ||
| 51 | /* User symbols in this file have a leading underscore. */ | ||
| 52 | #define EF_CRIS_UNDERSCORE 0x00000001 | ||
| 53 | |||
| 54 | /* This is a mask for different incompatible machine variants. */ | ||
| 55 | #define EF_CRIS_VARIANT_MASK 0x0000000e | ||
| 56 | |||
| 57 | /* Variant 0; may contain v0..10 object. */ | ||
| 58 | #define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 | ||
| 59 | |||
| 60 | /* Variant 1; contains v32 object. */ | ||
| 61 | #define EF_CRIS_VARIANT_V32 0x00000002 | ||
| 62 | |||
| 63 | /* Variant 2; contains object compatible with v32 and v10. */ | ||
| 64 | #define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 | ||
| 65 | /* End of excerpt from {binutils}/include/elf/cris.h. */ | ||
| 66 | |||
| 67 | #define USE_ELF_CORE_DUMP | ||
| 68 | |||
| 69 | #define ELF_EXEC_PAGESIZE 8192 | ||
| 70 | |||
| 71 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | ||
| 72 | use of this is to invoke "./ld.so someprog" to test out a new version of | ||
| 73 | the loader. We need to make sure that it is out of the way of the program | ||
| 74 | that it will "exec", and that there is sufficient room for the brk. */ | ||
| 75 | |||
| 76 | #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) | ||
| 77 | |||
| 78 | /* This yields a mask that user programs can use to figure out what | ||
| 79 | instruction set this CPU supports. This could be done in user space, | ||
| 80 | but it's not easy, and we've already done it here. */ | ||
| 81 | |||
| 82 | #define ELF_HWCAP (0) | ||
| 83 | |||
| 84 | /* This yields a string that ld.so will use to load implementation | ||
| 85 | specific libraries for optimization. This is more specific in | ||
| 86 | intent than poking at uname or /proc/cpuinfo. | ||
| 87 | */ | ||
| 88 | |||
| 89 | #define ELF_PLATFORM (NULL) | ||
| 90 | |||
| 91 | #define SET_PERSONALITY(ex) set_personality(PER_LINUX) | ||
| 92 | |||
| 93 | #endif | ||
diff --git a/include/asm-cris/emergency-restart.h b/include/asm-cris/emergency-restart.h deleted file mode 100644 index 108d8c48e42e..000000000000 --- a/include/asm-cris/emergency-restart.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _ASM_EMERGENCY_RESTART_H | ||
| 2 | #define _ASM_EMERGENCY_RESTART_H | ||
| 3 | |||
| 4 | #include <asm-generic/emergency-restart.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_EMERGENCY_RESTART_H */ | ||
diff --git a/include/asm-cris/errno.h b/include/asm-cris/errno.h deleted file mode 100644 index 2bf5eb5fa773..000000000000 --- a/include/asm-cris/errno.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _CRIS_ERRNO_H | ||
| 2 | #define _CRIS_ERRNO_H | ||
| 3 | |||
| 4 | #include <asm-generic/errno.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/eshlibld.h b/include/asm-cris/eshlibld.h deleted file mode 100644 index 10ce36cf79a9..000000000000 --- a/include/asm-cris/eshlibld.h +++ /dev/null | |||
| @@ -1,113 +0,0 @@ | |||
| 1 | /*!************************************************************************** | ||
| 2 | *! | ||
| 3 | *! FILE NAME : eshlibld.h | ||
| 4 | *! | ||
| 5 | *! DESCRIPTION: Prototypes for exported shared library functions | ||
| 6 | *! | ||
| 7 | *! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit | ||
| 8 | *! (EXPORTED) | ||
| 9 | *! | ||
| 10 | *!--------------------------------------------------------------------------- | ||
| 11 | *! | ||
| 12 | *! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN | ||
| 13 | *! | ||
| 14 | *!**************************************************************************/ | ||
| 15 | /* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */ | ||
| 16 | |||
| 17 | #ifndef _cris_relocate_h | ||
| 18 | #define _cris_relocate_h | ||
| 19 | |||
| 20 | /* Please note that this file is also compiled into the xsim simulator. | ||
| 21 | Try to avoid breaking its double use (only works on a little-endian | ||
| 22 | 32-bit machine such as the i386 anyway). | ||
| 23 | |||
| 24 | Use __KERNEL__ when you're about to use kernel functions, | ||
| 25 | (which you should not do here anyway, since this file is | ||
| 26 | used by glibc). | ||
| 27 | Use defined(__KERNEL__) || defined(__elinux__) when doing | ||
| 28 | things that only makes sense on an elinux system. | ||
| 29 | Use __CRIS__ when you're about to do (really) CRIS-specific code. | ||
| 30 | */ | ||
| 31 | |||
| 32 | /* We have dependencies all over the place for the host system | ||
| 33 | for xsim being a linux system, so let's not pretend anything | ||
| 34 | else with #ifdef:s here until fixed. */ | ||
| 35 | #include <linux/limits.h> | ||
| 36 | |||
| 37 | /* Maybe do sanity checking if file input. */ | ||
| 38 | #undef SANITYCHECK_RELOC | ||
| 39 | |||
| 40 | /* Maybe output debug messages. */ | ||
| 41 | #undef RELOC_DEBUG | ||
| 42 | |||
| 43 | /* Maybe we want to share core as well as disk space. | ||
| 44 | Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is | ||
| 45 | assumed that we want to share code when debugging (exposes more | ||
| 46 | trouble). */ | ||
| 47 | #ifndef SHARE_LIB_CORE | ||
| 48 | # if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \ | ||
| 49 | && !defined(CONFIG_SHARE_SHLIB_CORE) | ||
| 50 | # define SHARE_LIB_CORE 0 | ||
| 51 | # else | ||
| 52 | # define SHARE_LIB_CORE 1 | ||
| 53 | # endif /* __KERNEL__ etc */ | ||
| 54 | #endif /* SHARE_LIB_CORE */ | ||
| 55 | |||
| 56 | |||
| 57 | /* Main exported function; supposed to be called when the program a.out | ||
| 58 | has been read in. */ | ||
| 59 | extern int | ||
| 60 | perform_cris_aout_relocations(unsigned long text, unsigned long tlength, | ||
| 61 | unsigned long data, unsigned long dlength, | ||
| 62 | unsigned long baddr, unsigned long blength, | ||
| 63 | |||
| 64 | /* These may be zero when there's "perfect" | ||
| 65 | position-independent code. */ | ||
| 66 | unsigned char *trel, unsigned long tsrel, | ||
| 67 | unsigned long dsrel, | ||
| 68 | |||
| 69 | /* These will be zero at a first try, to see | ||
| 70 | if code is statically linked. Else a | ||
| 71 | second try, with the symbol table and | ||
| 72 | string table nonzero should be done. */ | ||
| 73 | unsigned char *symbols, unsigned long symlength, | ||
| 74 | unsigned char *strings, unsigned long stringlength, | ||
| 75 | |||
| 76 | /* These will only be used when symbol table | ||
| 77 | information is present. */ | ||
| 78 | char **env, int envc, | ||
| 79 | int euid, int is_suid); | ||
| 80 | |||
| 81 | |||
| 82 | #ifdef RELOC_DEBUG | ||
| 83 | /* Task-specific debug stuff. */ | ||
| 84 | struct task_reloc_debug { | ||
| 85 | struct memdebug *alloclast; | ||
| 86 | unsigned long alloc_total; | ||
| 87 | unsigned long export_total; | ||
| 88 | }; | ||
| 89 | #endif /* RELOC_DEBUG */ | ||
| 90 | |||
| 91 | #if SHARE_LIB_CORE | ||
| 92 | |||
| 93 | /* When code (and some very specific data) is shared and not just | ||
| 94 | dynamically linked, we need to export hooks for exec beginning and | ||
| 95 | end. */ | ||
| 96 | |||
| 97 | struct shlibdep; | ||
| 98 | |||
| 99 | extern void | ||
| 100 | shlibmod_exit(struct shlibdep **deps); | ||
| 101 | |||
| 102 | /* Returns 0 if failure, nonzero for ok. */ | ||
| 103 | extern int | ||
| 104 | shlibmod_fork(struct shlibdep **deps); | ||
| 105 | |||
| 106 | #else /* ! SHARE_LIB_CORE */ | ||
| 107 | # define shlibmod_exit(x) | ||
| 108 | # define shlibmod_fork(x) 1 | ||
| 109 | #endif /* ! SHARE_LIB_CORE */ | ||
| 110 | |||
| 111 | #endif _cris_relocate_h | ||
| 112 | /********************** END OF FILE eshlibld.h *****************************/ | ||
| 113 | |||
diff --git a/include/asm-cris/ethernet.h b/include/asm-cris/ethernet.h deleted file mode 100644 index 4d58652c3a49..000000000000 --- a/include/asm-cris/ethernet.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * ioctl defines for ethernet driver | ||
| 3 | * | ||
| 4 | * Copyright (c) 2001 Axis Communications AB | ||
| 5 | * | ||
| 6 | * Author: Mikael Starvik | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _CRIS_ETHERNET_H | ||
| 11 | #define _CRIS_ETHERNET_H | ||
| 12 | #define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ | ||
| 13 | #define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ | ||
| 14 | #define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ | ||
| 15 | #define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ | ||
| 16 | #define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ | ||
| 17 | #define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ | ||
| 18 | #define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ | ||
| 19 | #define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ | ||
| 20 | #define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 | ||
| 21 | #endif /* _CRIS_ETHERNET_H */ | ||
diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h deleted file mode 100644 index 38f1c8e1770c..000000000000 --- a/include/asm-cris/etraxgpio.h +++ /dev/null | |||
| @@ -1,179 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * The following devices are accessable using this driver using | ||
| 3 | * GPIO_MAJOR (120) and a couple of minor numbers. | ||
| 4 | * | ||
| 5 | * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): | ||
| 6 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | ||
| 7 | * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction | ||
| 8 | * /dev/leds minor 2, Access to leds depending on kernelconfig | ||
| 9 | * /dev/gpiog minor 3 | ||
| 10 | * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG | ||
| 11 | * g1-g7 and g25-g31 is both input and outputs but on different pins | ||
| 12 | * Also note that some bits change pins depending on what interfaces | ||
| 13 | * are enabled. | ||
| 14 | * | ||
| 15 | * For ETRAX FS (CONFIG_ETRAXFS): | ||
| 16 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | ||
| 17 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction | ||
| 18 | * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction | ||
| 19 | * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction | ||
| 20 | * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction | ||
| 21 | * /dev/leds minor 2, Access to leds depending on kernelconfig | ||
| 22 | * | ||
| 23 | * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): | ||
| 24 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | ||
| 25 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction | ||
| 26 | * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction | ||
| 27 | * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction | ||
| 28 | * /dev/leds minor 2, Access to leds depending on kernelconfig | ||
| 29 | * /dev/pwm0 minor 16, PWM channel 0 on PA30 | ||
| 30 | * /dev/pwm1 minor 17, PWM channel 1 on PA31 | ||
| 31 | * /dev/pwm2 minor 18, PWM channel 2 on PB26 | ||
| 32 | * | ||
| 33 | */ | ||
| 34 | #ifndef _ASM_ETRAXGPIO_H | ||
| 35 | #define _ASM_ETRAXGPIO_H | ||
| 36 | |||
| 37 | /* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ | ||
| 38 | #ifdef CONFIG_ETRAX_ARCH_V10 | ||
| 39 | #define ETRAXGPIO_IOCTYPE 43 | ||
| 40 | #define GPIO_MINOR_A 0 | ||
| 41 | #define GPIO_MINOR_B 1 | ||
| 42 | #define GPIO_MINOR_LEDS 2 | ||
| 43 | #define GPIO_MINOR_G 3 | ||
| 44 | #define GPIO_MINOR_LAST 3 | ||
| 45 | #endif | ||
| 46 | |||
| 47 | #ifdef CONFIG_ETRAXFS | ||
| 48 | #define ETRAXGPIO_IOCTYPE 43 | ||
| 49 | #define GPIO_MINOR_A 0 | ||
| 50 | #define GPIO_MINOR_B 1 | ||
| 51 | #define GPIO_MINOR_LEDS 2 | ||
| 52 | #define GPIO_MINOR_C 3 | ||
| 53 | #define GPIO_MINOR_D 4 | ||
| 54 | #define GPIO_MINOR_E 5 | ||
| 55 | #ifdef CONFIG_ETRAX_VIRTUAL_GPIO | ||
| 56 | #define GPIO_MINOR_V 6 | ||
| 57 | #define GPIO_MINOR_LAST 6 | ||
| 58 | #else | ||
| 59 | #define GPIO_MINOR_LAST 5 | ||
| 60 | #endif | ||
| 61 | #endif | ||
| 62 | |||
| 63 | #ifdef CONFIG_CRIS_MACH_ARTPEC3 | ||
| 64 | #define ETRAXGPIO_IOCTYPE 43 | ||
| 65 | #define GPIO_MINOR_A 0 | ||
| 66 | #define GPIO_MINOR_B 1 | ||
| 67 | #define GPIO_MINOR_LEDS 2 | ||
| 68 | #define GPIO_MINOR_C 3 | ||
| 69 | #define GPIO_MINOR_D 4 | ||
| 70 | #ifdef CONFIG_ETRAX_VIRTUAL_GPIO | ||
| 71 | #define GPIO_MINOR_V 6 | ||
| 72 | #define GPIO_MINOR_LAST 6 | ||
| 73 | #else | ||
| 74 | #define GPIO_MINOR_LAST 4 | ||
| 75 | #endif | ||
| 76 | #define GPIO_MINOR_PWM0 16 | ||
| 77 | #define GPIO_MINOR_PWM1 17 | ||
| 78 | #define GPIO_MINOR_PWM2 18 | ||
| 79 | #define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2 | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* supported ioctl _IOC_NR's */ | ||
| 83 | |||
| 84 | #define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ | ||
| 85 | #define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ | ||
| 86 | #define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ | ||
| 87 | |||
| 88 | /* the alarm is waited for by select() */ | ||
| 89 | |||
| 90 | #define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ | ||
| 91 | #define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ | ||
| 92 | #define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ | ||
| 93 | |||
| 94 | /* LED ioctl */ | ||
| 95 | #define IO_LEDACTIVE_SET 0x7 /* set active led | ||
| 96 | * 0=off, 1=green, 2=red, 3=yellow */ | ||
| 97 | |||
| 98 | /* GPIO direction ioctl's */ | ||
| 99 | #define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ | ||
| 100 | #define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, | ||
| 101 | returns mask with current inputs (obsolete) */ | ||
| 102 | #define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, | ||
| 103 | returns mask with current outputs (obsolete)*/ | ||
| 104 | |||
| 105 | /* LED ioctl extended */ | ||
| 106 | #define IO_LED_SETBIT 0xB | ||
| 107 | #define IO_LED_CLRBIT 0xC | ||
| 108 | |||
| 109 | /* SHUTDOWN ioctl */ | ||
| 110 | #define IO_SHUTDOWN 0xD | ||
| 111 | #define IO_GET_PWR_BT 0xE | ||
| 112 | |||
| 113 | /* Bit toggling in driver settings */ | ||
| 114 | /* bit set in low byte0 is CLK mask (0x00FF), | ||
| 115 | bit set in byte1 is DATA mask (0xFF00) | ||
| 116 | msb, data_mask[7:0] , clk_mask[7:0] | ||
| 117 | */ | ||
| 118 | #define IO_CFG_WRITE_MODE 0xF | ||
| 119 | #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ | ||
| 120 | ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) | ||
| 121 | |||
| 122 | /* The following 4 ioctl's take a pointer as argument and handles | ||
| 123 | * 32 bit ports (port G) properly. | ||
| 124 | * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT | ||
| 125 | */ | ||
| 126 | #define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ | ||
| 127 | #define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ | ||
| 128 | #define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, | ||
| 129 | * *arg updated with current input pins. | ||
| 130 | */ | ||
| 131 | #define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, | ||
| 132 | * *arg updated with current output pins. | ||
| 133 | */ | ||
| 134 | |||
| 135 | /* The following ioctl's are applicable to the PWM channels only */ | ||
| 136 | |||
| 137 | #define IO_PWM_SET_MODE 0x20 | ||
| 138 | |||
| 139 | enum io_pwm_mode { | ||
| 140 | PWM_OFF = 0, /* disabled, deallocated */ | ||
| 141 | PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ | ||
| 142 | PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ | ||
| 143 | PWM_VARFREQ = 3 /* individually configurable high/low periods */ | ||
| 144 | }; | ||
| 145 | |||
| 146 | struct io_pwm_set_mode { | ||
| 147 | enum io_pwm_mode mode; | ||
| 148 | }; | ||
| 149 | |||
| 150 | /* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns | ||
| 151 | * from 10ns (value = 0) to 81920ns (value = 8191) | ||
| 152 | * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to | ||
| 153 | * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty | ||
| 154 | * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) | ||
| 155 | */ | ||
| 156 | #define IO_PWM_SET_PERIOD 0x21 | ||
| 157 | |||
| 158 | struct io_pwm_set_period { | ||
| 159 | unsigned int lo; /* 0..8191 */ | ||
| 160 | unsigned int hi; /* 0..8191 */ | ||
| 161 | }; | ||
| 162 | |||
| 163 | /* Only for modes PWM_STANDARD and PWM_FAST. | ||
| 164 | * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from | ||
| 165 | * 0 (value = 0) to 255/256 (value = 255). | ||
| 166 | * For PWM_FAST, set duty cycle of PWM output signal from | ||
| 167 | * 0% (value = 0) to 100% (value = 255). Output signal in this mode | ||
| 168 | * is a 10ns pulse surrounded by a high or low level depending on duty | ||
| 169 | * cycle (except for 0% and 100% which result in a constant output). | ||
| 170 | * Resulting output frequency varies from 50 MHz at 50% duty cycle, | ||
| 171 | * down to 390 kHz at min/max duty cycle. | ||
| 172 | */ | ||
| 173 | #define IO_PWM_SET_DUTY 0x22 | ||
| 174 | |||
| 175 | struct io_pwm_set_duty { | ||
| 176 | int duty; /* 0..255 */ | ||
| 177 | }; | ||
| 178 | |||
| 179 | #endif | ||
diff --git a/include/asm-cris/etraxi2c.h b/include/asm-cris/etraxi2c.h deleted file mode 100644 index e369a7620893..000000000000 --- a/include/asm-cris/etraxi2c.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */ | ||
| 2 | |||
| 3 | #ifndef _LINUX_ETRAXI2C_H | ||
| 4 | #define _LINUX_ETRAXI2C_H | ||
| 5 | |||
| 6 | /* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */ | ||
| 7 | |||
| 8 | #define ETRAXI2C_IOCTYPE 44 | ||
| 9 | |||
| 10 | /* supported ioctl _IOC_NR's */ | ||
| 11 | |||
| 12 | /* in write operations, the argument contains both i2c | ||
| 13 | * slave, register and value. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value)) | ||
| 17 | #define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8)) | ||
| 18 | |||
| 19 | #define I2C_ARGSLAVE(arg) ((arg) >> 16) | ||
| 20 | #define I2C_ARGREG(arg) (((arg) >> 8) & 0xff) | ||
| 21 | #define I2C_ARGVALUE(arg) ((arg) & 0xff) | ||
| 22 | |||
| 23 | #define I2C_WRITEREG 0x1 /* write to an i2c register */ | ||
| 24 | #define I2C_READREG 0x2 /* read from an i2c register */ | ||
| 25 | |||
| 26 | /* | ||
| 27 | EXAMPLE usage: | ||
| 28 | |||
| 29 | i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); | ||
| 30 | ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); | ||
| 31 | |||
| 32 | i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); | ||
| 33 | val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); | ||
| 34 | |||
| 35 | */ | ||
| 36 | #endif | ||
diff --git a/include/asm-cris/fasttimer.h b/include/asm-cris/fasttimer.h deleted file mode 100644 index 8f8a8d6c9653..000000000000 --- a/include/asm-cris/fasttimer.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-cris/fasttimer.h | ||
| 3 | * | ||
| 4 | * Fast timers for ETRAX100LX | ||
| 5 | * Copyright (C) 2000-2007 Axis Communications AB | ||
| 6 | */ | ||
| 7 | #include <linux/time.h> /* struct timeval */ | ||
| 8 | #include <linux/timex.h> | ||
| 9 | |||
| 10 | #ifdef CONFIG_ETRAX_FAST_TIMER | ||
| 11 | |||
| 12 | typedef void fast_timer_function_type(unsigned long); | ||
| 13 | |||
| 14 | struct fasttime_t { | ||
| 15 | unsigned long tv_jiff; /* jiffies */ | ||
| 16 | unsigned long tv_usec; /* microseconds */ | ||
| 17 | }; | ||
| 18 | |||
| 19 | struct fast_timer{ /* Close to timer_list */ | ||
| 20 | struct fast_timer *next; | ||
| 21 | struct fast_timer *prev; | ||
| 22 | struct fasttime_t tv_set; | ||
| 23 | struct fasttime_t tv_expires; | ||
| 24 | unsigned long delay_us; | ||
| 25 | fast_timer_function_type *function; | ||
| 26 | unsigned long data; | ||
| 27 | const char *name; | ||
| 28 | }; | ||
| 29 | |||
| 30 | extern struct fast_timer *fast_timer_list; | ||
| 31 | |||
| 32 | void start_one_shot_timer(struct fast_timer *t, | ||
| 33 | fast_timer_function_type *function, | ||
| 34 | unsigned long data, | ||
| 35 | unsigned long delay_us, | ||
| 36 | const char *name); | ||
| 37 | |||
| 38 | int del_fast_timer(struct fast_timer * t); | ||
| 39 | /* return 1 if deleted */ | ||
| 40 | |||
| 41 | |||
| 42 | void schedule_usleep(unsigned long us); | ||
| 43 | |||
| 44 | |||
| 45 | int fast_timer_init(void); | ||
| 46 | |||
| 47 | #endif | ||
diff --git a/include/asm-cris/fb.h b/include/asm-cris/fb.h deleted file mode 100644 index c7df38030992..000000000000 --- a/include/asm-cris/fb.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | #ifndef _ASM_FB_H_ | ||
| 2 | #define _ASM_FB_H_ | ||
| 3 | #include <linux/fb.h> | ||
| 4 | |||
| 5 | #define fb_pgprotect(...) do {} while (0) | ||
| 6 | |||
| 7 | static inline int fb_is_primary_device(struct fb_info *info) | ||
| 8 | { | ||
| 9 | return 0; | ||
| 10 | } | ||
| 11 | |||
| 12 | #endif /* _ASM_FB_H_ */ | ||
diff --git a/include/asm-cris/fcntl.h b/include/asm-cris/fcntl.h deleted file mode 100644 index 46ab12db5739..000000000000 --- a/include/asm-cris/fcntl.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/fcntl.h> | ||
diff --git a/include/asm-cris/futex.h b/include/asm-cris/futex.h deleted file mode 100644 index 6a332a9f099c..000000000000 --- a/include/asm-cris/futex.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _ASM_FUTEX_H | ||
| 2 | #define _ASM_FUTEX_H | ||
| 3 | |||
| 4 | #include <asm-generic/futex.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h deleted file mode 100644 index 74178adeb1cd..000000000000 --- a/include/asm-cris/hardirq.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | #ifndef __ASM_HARDIRQ_H | ||
| 2 | #define __ASM_HARDIRQ_H | ||
| 3 | |||
| 4 | #include <asm/irq.h> | ||
| 5 | #include <linux/threads.h> | ||
| 6 | #include <linux/cache.h> | ||
| 7 | |||
| 8 | typedef struct { | ||
| 9 | unsigned int __softirq_pending; | ||
| 10 | } ____cacheline_aligned irq_cpustat_t; | ||
| 11 | |||
| 12 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | ||
| 13 | |||
| 14 | void ack_bad_irq(unsigned int irq); | ||
| 15 | |||
| 16 | #define HARDIRQ_BITS 8 | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The hardirq mask has to be large enough to have | ||
| 20 | * space for potentially all IRQ sources in the system | ||
| 21 | * nesting on a single CPU: | ||
| 22 | */ | ||
| 23 | #if (1 << HARDIRQ_BITS) < NR_IRQS | ||
| 24 | # error HARDIRQ_BITS is too low! | ||
| 25 | #endif | ||
| 26 | |||
| 27 | #endif /* __ASM_HARDIRQ_H */ | ||
diff --git a/include/asm-cris/hw_irq.h b/include/asm-cris/hw_irq.h deleted file mode 100644 index 298066020af2..000000000000 --- a/include/asm-cris/hw_irq.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | #ifndef _ASM_HW_IRQ_H | ||
| 2 | #define _ASM_HW_IRQ_H | ||
| 3 | |||
| 4 | #endif | ||
| 5 | |||
diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h deleted file mode 100644 index b87ce63f531f..000000000000 --- a/include/asm-cris/io.h +++ /dev/null | |||
| @@ -1,154 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_IO_H | ||
| 2 | #define _ASM_CRIS_IO_H | ||
| 3 | |||
| 4 | #include <asm/page.h> /* for __va, __pa */ | ||
| 5 | #include <asm/arch/io.h> | ||
| 6 | #include <linux/kernel.h> | ||
| 7 | |||
| 8 | struct cris_io_operations | ||
| 9 | { | ||
| 10 | u32 (*read_mem)(void *addr, int size); | ||
| 11 | void (*write_mem)(u32 val, int size, void *addr); | ||
| 12 | u32 (*read_io)(u32 port, void *addr, int size, int count); | ||
| 13 | void (*write_io)(u32 port, void *addr, int size, int count); | ||
| 14 | }; | ||
| 15 | |||
| 16 | #ifdef CONFIG_PCI | ||
| 17 | extern struct cris_io_operations *cris_iops; | ||
| 18 | #else | ||
| 19 | #define cris_iops ((struct cris_io_operations*)NULL) | ||
| 20 | #endif | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Change virtual addresses to physical addresses and vv. | ||
| 24 | */ | ||
| 25 | |||
| 26 | static inline unsigned long virt_to_phys(volatile void * address) | ||
| 27 | { | ||
| 28 | return __pa(address); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline void * phys_to_virt(unsigned long address) | ||
| 32 | { | ||
| 33 | return __va(address); | ||
| 34 | } | ||
| 35 | |||
| 36 | extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); | ||
| 37 | extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot); | ||
| 38 | |||
| 39 | static inline void __iomem * ioremap (unsigned long offset, unsigned long size) | ||
| 40 | { | ||
| 41 | return __ioremap(offset, size, 0); | ||
| 42 | } | ||
| 43 | |||
| 44 | extern void iounmap(volatile void * __iomem addr); | ||
| 45 | |||
| 46 | extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); | ||
| 47 | |||
| 48 | /* | ||
| 49 | * IO bus memory addresses are also 1:1 with the physical address | ||
| 50 | */ | ||
| 51 | #define virt_to_bus virt_to_phys | ||
| 52 | #define bus_to_virt phys_to_virt | ||
| 53 | |||
| 54 | /* | ||
| 55 | * readX/writeX() are used to access memory mapped devices. On some | ||
| 56 | * architectures the memory mapped IO stuff needs to be accessed | ||
| 57 | * differently. On the CRIS architecture, we just read/write the | ||
| 58 | * memory location directly. | ||
| 59 | */ | ||
| 60 | #ifdef CONFIG_PCI | ||
| 61 | #define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000) | ||
| 62 | #else | ||
| 63 | #define PCI_SPACE(x) 0 | ||
| 64 | #endif | ||
| 65 | static inline unsigned char readb(const volatile void __iomem *addr) | ||
| 66 | { | ||
| 67 | if (PCI_SPACE(addr) && cris_iops) | ||
| 68 | return cris_iops->read_mem((void*)addr, 1); | ||
| 69 | else | ||
| 70 | return *(volatile unsigned char __force *) addr; | ||
| 71 | } | ||
| 72 | static inline unsigned short readw(const volatile void __iomem *addr) | ||
| 73 | { | ||
| 74 | if (PCI_SPACE(addr) && cris_iops) | ||
| 75 | return cris_iops->read_mem((void*)addr, 2); | ||
| 76 | else | ||
| 77 | return *(volatile unsigned short __force *) addr; | ||
| 78 | } | ||
| 79 | static inline unsigned int readl(const volatile void __iomem *addr) | ||
| 80 | { | ||
| 81 | if (PCI_SPACE(addr) && cris_iops) | ||
| 82 | return cris_iops->read_mem((void*)addr, 4); | ||
| 83 | else | ||
| 84 | return *(volatile unsigned int __force *) addr; | ||
| 85 | } | ||
| 86 | #define readb_relaxed(addr) readb(addr) | ||
| 87 | #define readw_relaxed(addr) readw(addr) | ||
| 88 | #define readl_relaxed(addr) readl(addr) | ||
| 89 | #define __raw_readb readb | ||
| 90 | #define __raw_readw readw | ||
| 91 | #define __raw_readl readl | ||
| 92 | |||
| 93 | static inline void writeb(unsigned char b, volatile void __iomem *addr) | ||
| 94 | { | ||
| 95 | if (PCI_SPACE(addr) && cris_iops) | ||
| 96 | cris_iops->write_mem(b, 1, (void*)addr); | ||
| 97 | else | ||
| 98 | *(volatile unsigned char __force *) addr = b; | ||
| 99 | } | ||
| 100 | static inline void writew(unsigned short b, volatile void __iomem *addr) | ||
| 101 | { | ||
| 102 | if (PCI_SPACE(addr) && cris_iops) | ||
| 103 | cris_iops->write_mem(b, 2, (void*)addr); | ||
| 104 | else | ||
| 105 | *(volatile unsigned short __force *) addr = b; | ||
| 106 | } | ||
| 107 | static inline void writel(unsigned int b, volatile void __iomem *addr) | ||
| 108 | { | ||
| 109 | if (PCI_SPACE(addr) && cris_iops) | ||
| 110 | cris_iops->write_mem(b, 4, (void*)addr); | ||
| 111 | else | ||
| 112 | *(volatile unsigned int __force *) addr = b; | ||
| 113 | } | ||
| 114 | #define __raw_writeb writeb | ||
| 115 | #define __raw_writew writew | ||
| 116 | #define __raw_writel writel | ||
| 117 | |||
| 118 | #define mmiowb() | ||
| 119 | |||
| 120 | #define memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
| 121 | #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
| 122 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
| 123 | |||
| 124 | |||
| 125 | /* I/O port access. Normally there is no I/O space on CRIS but when | ||
| 126 | * Cardbus/PCI is enabled the request is passed through the bridge. | ||
| 127 | */ | ||
| 128 | |||
| 129 | #define IO_SPACE_LIMIT 0xffff | ||
| 130 | #define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0) | ||
| 131 | #define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0) | ||
| 132 | #define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0) | ||
| 133 | #define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0) | ||
| 134 | #define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0) | ||
| 135 | #define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0) | ||
| 136 | #define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1) | ||
| 137 | #define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1) | ||
| 138 | #define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1) | ||
| 139 | #define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count) | ||
| 140 | #define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count) | ||
| 141 | #define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count) | ||
| 142 | |||
| 143 | /* | ||
| 144 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | ||
| 145 | * access | ||
| 146 | */ | ||
| 147 | #define xlate_dev_mem_ptr(p) __va(p) | ||
| 148 | |||
| 149 | /* | ||
| 150 | * Convert a virtual cached pointer to an uncached pointer | ||
| 151 | */ | ||
| 152 | #define xlate_dev_kmem_ptr(p) p | ||
| 153 | |||
| 154 | #endif | ||
diff --git a/include/asm-cris/ioctl.h b/include/asm-cris/ioctl.h deleted file mode 100644 index b279fe06dfe5..000000000000 --- a/include/asm-cris/ioctl.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/ioctl.h> | ||
diff --git a/include/asm-cris/ioctls.h b/include/asm-cris/ioctls.h deleted file mode 100644 index 4f4e52531fa0..000000000000 --- a/include/asm-cris/ioctls.h +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | #ifndef __ARCH_CRIS_IOCTLS_H__ | ||
| 2 | #define __ARCH_CRIS_IOCTLS_H__ | ||
| 3 | |||
| 4 | /* verbatim copy of asm-i386/ioctls.h */ | ||
| 5 | |||
| 6 | #include <asm/ioctl.h> | ||
| 7 | |||
| 8 | /* 0x54 is just a magic number to make these relatively unique ('T') */ | ||
| 9 | |||
| 10 | #define TCGETS 0x5401 | ||
| 11 | #define TCSETS 0x5402 | ||
| 12 | #define TCSETSW 0x5403 | ||
| 13 | #define TCSETSF 0x5404 | ||
| 14 | #define TCGETA 0x5405 | ||
| 15 | #define TCSETA 0x5406 | ||
| 16 | #define TCSETAW 0x5407 | ||
| 17 | #define TCSETAF 0x5408 | ||
| 18 | #define TCSBRK 0x5409 | ||
| 19 | #define TCXONC 0x540A | ||
| 20 | #define TCFLSH 0x540B | ||
| 21 | #define TIOCEXCL 0x540C | ||
| 22 | #define TIOCNXCL 0x540D | ||
| 23 | #define TIOCSCTTY 0x540E | ||
| 24 | #define TIOCGPGRP 0x540F | ||
| 25 | #define TIOCSPGRP 0x5410 | ||
| 26 | #define TIOCOUTQ 0x5411 | ||
| 27 | #define TIOCSTI 0x5412 | ||
| 28 | #define TIOCGWINSZ 0x5413 | ||
| 29 | #define TIOCSWINSZ 0x5414 | ||
| 30 | #define TIOCMGET 0x5415 | ||
| 31 | #define TIOCMBIS 0x5416 | ||
| 32 | #define TIOCMBIC 0x5417 | ||
| 33 | #define TIOCMSET 0x5418 | ||
| 34 | #define TIOCGSOFTCAR 0x5419 | ||
| 35 | #define TIOCSSOFTCAR 0x541A | ||
| 36 | #define FIONREAD 0x541B | ||
| 37 | #define TIOCINQ FIONREAD | ||
| 38 | #define TIOCLINUX 0x541C | ||
| 39 | #define TIOCCONS 0x541D | ||
| 40 | #define TIOCGSERIAL 0x541E | ||
| 41 | #define TIOCSSERIAL 0x541F | ||
| 42 | #define TIOCPKT 0x5420 | ||
| 43 | #define FIONBIO 0x5421 | ||
| 44 | #define TIOCNOTTY 0x5422 | ||
| 45 | #define TIOCSETD 0x5423 | ||
| 46 | #define TIOCGETD 0x5424 | ||
| 47 | #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ | ||
| 48 | #define TIOCSBRK 0x5427 /* BSD compatibility */ | ||
| 49 | #define TIOCCBRK 0x5428 /* BSD compatibility */ | ||
| 50 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ | ||
| 51 | #define TCGETS2 _IOR('T',0x2A, struct termios2) | ||
| 52 | #define TCSETS2 _IOW('T',0x2B, struct termios2) | ||
| 53 | #define TCSETSW2 _IOW('T',0x2C, struct termios2) | ||
| 54 | #define TCSETSF2 _IOW('T',0x2D, struct termios2) | ||
| 55 | #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ | ||
| 56 | #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ | ||
| 57 | |||
| 58 | #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ | ||
| 59 | #define FIOCLEX 0x5451 | ||
| 60 | #define FIOASYNC 0x5452 | ||
| 61 | #define TIOCSERCONFIG 0x5453 | ||
| 62 | #define TIOCSERGWILD 0x5454 | ||
| 63 | #define TIOCSERSWILD 0x5455 | ||
| 64 | #define TIOCGLCKTRMIOS 0x5456 | ||
| 65 | #define TIOCSLCKTRMIOS 0x5457 | ||
| 66 | #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ | ||
| 67 | #define TIOCSERGETLSR 0x5459 /* Get line status register */ | ||
| 68 | #define TIOCSERGETMULTI 0x545A /* Get multiport config */ | ||
| 69 | #define TIOCSERSETMULTI 0x545B /* Set multiport config */ | ||
| 70 | |||
| 71 | #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ | ||
| 72 | #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ | ||
| 73 | #define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */ | ||
| 74 | #define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */ | ||
| 75 | #define FIOQSIZE 0x5460 | ||
| 76 | |||
| 77 | #define TIOCSERSETRS485 0x5461 /* enable rs-485 */ | ||
| 78 | #define TIOCSERWRRS485 0x5462 /* write rs-485 */ | ||
| 79 | |||
| 80 | /* Used for packet mode */ | ||
| 81 | #define TIOCPKT_DATA 0 | ||
| 82 | #define TIOCPKT_FLUSHREAD 1 | ||
| 83 | #define TIOCPKT_FLUSHWRITE 2 | ||
| 84 | #define TIOCPKT_STOP 4 | ||
| 85 | #define TIOCPKT_START 8 | ||
| 86 | #define TIOCPKT_NOSTOP 16 | ||
| 87 | #define TIOCPKT_DOSTOP 32 | ||
| 88 | |||
| 89 | #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ | ||
| 90 | |||
| 91 | #endif | ||
diff --git a/include/asm-cris/ipcbuf.h b/include/asm-cris/ipcbuf.h deleted file mode 100644 index 8b0c18b02844..000000000000 --- a/include/asm-cris/ipcbuf.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | #ifndef __CRIS_IPCBUF_H__ | ||
| 2 | #define __CRIS_IPCBUF_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The user_ipc_perm structure for CRIS architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 32-bit mode_t and seq | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct ipc64_perm | ||
| 15 | { | ||
| 16 | __kernel_key_t key; | ||
| 17 | __kernel_uid32_t uid; | ||
| 18 | __kernel_gid32_t gid; | ||
| 19 | __kernel_uid32_t cuid; | ||
| 20 | __kernel_gid32_t cgid; | ||
| 21 | __kernel_mode_t mode; | ||
| 22 | unsigned short __pad1; | ||
| 23 | unsigned short seq; | ||
| 24 | unsigned short __pad2; | ||
| 25 | unsigned long __unused1; | ||
| 26 | unsigned long __unused2; | ||
| 27 | }; | ||
| 28 | |||
| 29 | #endif /* __CRIS_IPCBUF_H__ */ | ||
diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h deleted file mode 100644 index 998cce9f3200..000000000000 --- a/include/asm-cris/irq.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | #ifndef _ASM_IRQ_H | ||
| 2 | #define _ASM_IRQ_H | ||
| 3 | |||
| 4 | #include <asm/arch/irq.h> | ||
| 5 | |||
| 6 | static inline int irq_canonicalize(int irq) | ||
| 7 | { | ||
| 8 | return irq; | ||
| 9 | } | ||
| 10 | |||
| 11 | #endif /* _ASM_IRQ_H */ | ||
| 12 | |||
| 13 | |||
diff --git a/include/asm-cris/irq_regs.h b/include/asm-cris/irq_regs.h deleted file mode 100644 index 3dd9c0b70270..000000000000 --- a/include/asm-cris/irq_regs.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/irq_regs.h> | ||
diff --git a/include/asm-cris/kdebug.h b/include/asm-cris/kdebug.h deleted file mode 100644 index 6ece1b037665..000000000000 --- a/include/asm-cris/kdebug.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/kdebug.h> | ||
diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h deleted file mode 100644 index 492988cb9077..000000000000 --- a/include/asm-cris/kmap_types.h +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | #ifndef _ASM_KMAP_TYPES_H | ||
| 2 | #define _ASM_KMAP_TYPES_H | ||
| 3 | |||
| 4 | /* Dummy header just to define km_type. None of this | ||
| 5 | * is actually used on cris. | ||
| 6 | */ | ||
| 7 | |||
| 8 | enum km_type { | ||
| 9 | KM_BOUNCE_READ, | ||
| 10 | KM_SKB_SUNRPC_DATA, | ||
| 11 | KM_SKB_DATA_SOFTIRQ, | ||
| 12 | KM_USER0, | ||
| 13 | KM_USER1, | ||
| 14 | KM_BIO_SRC_IRQ, | ||
| 15 | KM_BIO_DST_IRQ, | ||
| 16 | KM_PTE0, | ||
| 17 | KM_PTE1, | ||
| 18 | KM_IRQ0, | ||
| 19 | KM_IRQ1, | ||
| 20 | KM_SOFTIRQ0, | ||
| 21 | KM_SOFTIRQ1, | ||
| 22 | KM_TYPE_NR | ||
| 23 | }; | ||
| 24 | |||
| 25 | #endif | ||
diff --git a/include/asm-cris/linkage.h b/include/asm-cris/linkage.h deleted file mode 100644 index 291c2d01c44f..000000000000 --- a/include/asm-cris/linkage.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef __ASM_LINKAGE_H | ||
| 2 | #define __ASM_LINKAGE_H | ||
| 3 | |||
| 4 | /* Nothing to see here... */ | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/local.h b/include/asm-cris/local.h deleted file mode 100644 index c11c530f74d0..000000000000 --- a/include/asm-cris/local.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/local.h> | ||
diff --git a/include/asm-cris/mman.h b/include/asm-cris/mman.h deleted file mode 100644 index 1c35e1b66b46..000000000000 --- a/include/asm-cris/mman.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | #ifndef __CRIS_MMAN_H__ | ||
| 2 | #define __CRIS_MMAN_H__ | ||
| 3 | |||
| 4 | /* verbatim copy of asm-i386/ version */ | ||
| 5 | |||
| 6 | #include <asm-generic/mman.h> | ||
| 7 | |||
| 8 | #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ | ||
| 9 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
| 10 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
| 11 | #define MAP_LOCKED 0x2000 /* pages are locked */ | ||
| 12 | #define MAP_NORESERVE 0x4000 /* don't check for reservations */ | ||
| 13 | #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
| 14 | #define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
| 15 | |||
| 16 | #define MCL_CURRENT 1 /* lock all current mappings */ | ||
| 17 | #define MCL_FUTURE 2 /* lock all future mappings */ | ||
| 18 | |||
| 19 | #endif /* __CRIS_MMAN_H__ */ | ||
diff --git a/include/asm-cris/mmu.h b/include/asm-cris/mmu.h deleted file mode 100644 index c40a1bcad06c..000000000000 --- a/include/asm-cris/mmu.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * CRIS MMU constants and PTE layout | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _CRIS_MMU_H | ||
| 6 | #define _CRIS_MMU_H | ||
| 7 | |||
| 8 | #include <asm/arch/mmu.h> | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h deleted file mode 100644 index 72ba08dcfd18..000000000000 --- a/include/asm-cris/mmu_context.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | #ifndef __CRIS_MMU_CONTEXT_H | ||
| 2 | #define __CRIS_MMU_CONTEXT_H | ||
| 3 | |||
| 4 | #include <asm-generic/mm_hooks.h> | ||
| 5 | |||
| 6 | extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); | ||
| 7 | extern void get_mmu_context(struct mm_struct *mm); | ||
| 8 | extern void destroy_context(struct mm_struct *mm); | ||
| 9 | extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, | ||
| 10 | struct task_struct *tsk); | ||
| 11 | |||
| 12 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
| 13 | |||
| 14 | #define activate_mm(prev,next) switch_mm((prev),(next),NULL) | ||
| 15 | |||
| 16 | /* current active pgd - this is similar to other processors pgd | ||
| 17 | * registers like cr3 on the i386 | ||
| 18 | */ | ||
| 19 | |||
| 20 | extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */ | ||
| 21 | |||
| 22 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | ||
| 23 | { | ||
| 24 | } | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-cris/module.h b/include/asm-cris/module.h deleted file mode 100644 index 7ee72311bd78..000000000000 --- a/include/asm-cris/module.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_MODULE_H | ||
| 2 | #define _ASM_CRIS_MODULE_H | ||
| 3 | /* cris is simple */ | ||
| 4 | struct mod_arch_specific { }; | ||
| 5 | |||
| 6 | #define Elf_Shdr Elf32_Shdr | ||
| 7 | #define Elf_Sym Elf32_Sym | ||
| 8 | #define Elf_Ehdr Elf32_Ehdr | ||
| 9 | #endif /* _ASM_CRIS_MODULE_H */ | ||
diff --git a/include/asm-cris/msgbuf.h b/include/asm-cris/msgbuf.h deleted file mode 100644 index ada63df1d574..000000000000 --- a/include/asm-cris/msgbuf.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | #ifndef _CRIS_MSGBUF_H | ||
| 2 | #define _CRIS_MSGBUF_H | ||
| 3 | |||
| 4 | /* verbatim copy of asm-i386 version */ | ||
| 5 | |||
| 6 | /* | ||
| 7 | * The msqid64_ds structure for CRIS architecture. | ||
| 8 | * Note extra padding because this structure is passed back and forth | ||
| 9 | * between kernel and user space. | ||
| 10 | * | ||
| 11 | * Pad space is left for: | ||
| 12 | * - 64-bit time_t to solve y2038 problem | ||
| 13 | * - 2 miscellaneous 32-bit values | ||
| 14 | */ | ||
| 15 | |||
| 16 | struct msqid64_ds { | ||
| 17 | struct ipc64_perm msg_perm; | ||
| 18 | __kernel_time_t msg_stime; /* last msgsnd time */ | ||
| 19 | unsigned long __unused1; | ||
| 20 | __kernel_time_t msg_rtime; /* last msgrcv time */ | ||
| 21 | unsigned long __unused2; | ||
| 22 | __kernel_time_t msg_ctime; /* last change time */ | ||
| 23 | unsigned long __unused3; | ||
| 24 | unsigned long msg_cbytes; /* current number of bytes on queue */ | ||
| 25 | unsigned long msg_qnum; /* number of messages in queue */ | ||
| 26 | unsigned long msg_qbytes; /* max number of bytes on queue */ | ||
| 27 | __kernel_pid_t msg_lspid; /* pid of last msgsnd */ | ||
| 28 | __kernel_pid_t msg_lrpid; /* last receive pid */ | ||
| 29 | unsigned long __unused4; | ||
| 30 | unsigned long __unused5; | ||
| 31 | }; | ||
| 32 | |||
| 33 | #endif /* _CRIS_MSGBUF_H */ | ||
diff --git a/include/asm-cris/mutex.h b/include/asm-cris/mutex.h deleted file mode 100644 index 458c1f7fbc18..000000000000 --- a/include/asm-cris/mutex.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Pull in the generic implementation for the mutex fastpath. | ||
| 3 | * | ||
| 4 | * TODO: implement optimized primitives instead, or leave the generic | ||
| 5 | * implementation in place, or pick the atomic_xchg() based generic | ||
| 6 | * implementation. (see asm-generic/mutex-xchg.h for details) | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm-generic/mutex-dec.h> | ||
diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h deleted file mode 100644 index d19272ba6b69..000000000000 --- a/include/asm-cris/page.h +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | #ifndef _CRIS_PAGE_H | ||
| 2 | #define _CRIS_PAGE_H | ||
| 3 | |||
| 4 | #include <asm/arch/page.h> | ||
| 5 | #include <linux/const.h> | ||
| 6 | |||
| 7 | /* PAGE_SHIFT determines the page size */ | ||
| 8 | #define PAGE_SHIFT 13 | ||
| 9 | #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) | ||
| 10 | #define PAGE_MASK (~(PAGE_SIZE-1)) | ||
| 11 | |||
| 12 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) | ||
| 13 | #define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) | ||
| 14 | |||
| 15 | #define clear_user_page(page, vaddr, pg) clear_page(page) | ||
| 16 | #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) | ||
| 17 | |||
| 18 | #define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ | ||
| 19 | alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) | ||
| 20 | #define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE | ||
| 21 | |||
| 22 | /* | ||
| 23 | * These are used to make use of C type-checking.. | ||
| 24 | */ | ||
| 25 | #ifndef __ASSEMBLY__ | ||
| 26 | typedef struct { unsigned long pte; } pte_t; | ||
| 27 | typedef struct { unsigned long pgd; } pgd_t; | ||
| 28 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
| 29 | typedef struct page *pgtable_t; | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #define pte_val(x) ((x).pte) | ||
| 33 | #define pgd_val(x) ((x).pgd) | ||
| 34 | #define pgprot_val(x) ((x).pgprot) | ||
| 35 | |||
| 36 | #define __pte(x) ((pte_t) { (x) } ) | ||
| 37 | #define __pgd(x) ((pgd_t) { (x) } ) | ||
| 38 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
| 39 | |||
| 40 | /* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */ | ||
| 41 | /* for that before indexing into the page table starting at mem_map */ | ||
| 42 | #define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) | ||
| 43 | #define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr) | ||
| 44 | |||
| 45 | /* to index into the page map. our pages all start at physical addr PAGE_OFFSET so | ||
| 46 | * we can let the map start there. notice that we subtract PAGE_OFFSET because | ||
| 47 | * we start our mem_map there - in other ports they map mem_map physically and | ||
| 48 | * use __pa instead. in our system both the physical and virtual address of DRAM | ||
| 49 | * is too high to let mem_map start at 0, so we do it this way instead (similar | ||
| 50 | * to arm and m68k I think) | ||
| 51 | */ | ||
| 52 | |||
| 53 | #define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT)) | ||
| 54 | #define VALID_PAGE(page) (((page) - mem_map) < max_mapnr) | ||
| 55 | #define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT) | ||
| 56 | |||
| 57 | /* convert a page (based on mem_map and forward) to a physical address | ||
| 58 | * do this by figuring out the virtual address and then use __pa | ||
| 59 | */ | ||
| 60 | |||
| 61 | #define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) | ||
| 62 | |||
| 63 | #ifndef __ASSEMBLY__ | ||
| 64 | |||
| 65 | #endif /* __ASSEMBLY__ */ | ||
| 66 | |||
| 67 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ | ||
| 68 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | ||
| 69 | |||
| 70 | #include <asm-generic/memory_model.h> | ||
| 71 | #include <asm-generic/page.h> | ||
| 72 | |||
| 73 | #endif /* _CRIS_PAGE_H */ | ||
| 74 | |||
diff --git a/include/asm-cris/param.h b/include/asm-cris/param.h deleted file mode 100644 index 0e47994e40be..000000000000 --- a/include/asm-cris/param.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | #ifndef _ASMCRIS_PARAM_H | ||
| 2 | #define _ASMCRIS_PARAM_H | ||
| 3 | |||
| 4 | /* Currently we assume that HZ=100 is good for CRIS. */ | ||
| 5 | #ifdef __KERNEL__ | ||
| 6 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ | ||
| 7 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | ||
| 8 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | ||
| 9 | #endif | ||
| 10 | |||
| 11 | #ifndef HZ | ||
| 12 | #define HZ 100 | ||
| 13 | #endif | ||
| 14 | |||
| 15 | #define EXEC_PAGESIZE 8192 | ||
| 16 | |||
| 17 | #ifndef NOGROUP | ||
| 18 | #define NOGROUP (-1) | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h deleted file mode 100644 index 730ce40fdd0f..000000000000 --- a/include/asm-cris/pci.h +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_PCI_H | ||
| 2 | #define __ASM_CRIS_PCI_H | ||
| 3 | |||
| 4 | |||
| 5 | #ifdef __KERNEL__ | ||
| 6 | #include <linux/mm.h> /* for struct page */ | ||
| 7 | |||
| 8 | /* Can be used to override the logic in pci_scan_bus for skipping | ||
| 9 | already-configured bus numbers - to be used for buggy BIOSes | ||
| 10 | or architectures with incomplete PCI setup by the loader */ | ||
| 11 | |||
| 12 | #define pcibios_assign_all_busses(void) 1 | ||
| 13 | |||
| 14 | extern unsigned long pci_mem_start; | ||
| 15 | #define PCIBIOS_MIN_IO 0x1000 | ||
| 16 | #define PCIBIOS_MIN_MEM 0x10000000 | ||
| 17 | |||
| 18 | #define PCIBIOS_MIN_CARDBUS_IO 0x4000 | ||
| 19 | |||
| 20 | void pcibios_config_init(void); | ||
| 21 | struct pci_bus * pcibios_scan_root(int bus); | ||
| 22 | int pcibios_assign_resources(void); | ||
| 23 | |||
| 24 | void pcibios_set_master(struct pci_dev *dev); | ||
| 25 | void pcibios_penalize_isa_irq(int irq); | ||
| 26 | struct irq_routing_table *pcibios_get_irq_routing_table(void); | ||
| 27 | int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); | ||
| 28 | |||
| 29 | /* Dynamic DMA mapping stuff. | ||
| 30 | * i386 has everything mapped statically. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #include <linux/types.h> | ||
| 34 | #include <linux/slab.h> | ||
| 35 | #include <asm/scatterlist.h> | ||
| 36 | #include <linux/string.h> | ||
| 37 | #include <asm/io.h> | ||
| 38 | |||
| 39 | struct pci_dev; | ||
| 40 | |||
| 41 | /* The PCI address space does equal the physical memory | ||
| 42 | * address space. The networking and block device layers use | ||
| 43 | * this boolean for bounce buffer decisions. | ||
| 44 | */ | ||
| 45 | #define PCI_DMA_BUS_IS_PHYS (1) | ||
| 46 | |||
| 47 | /* pci_unmap_{page,single} is a nop so... */ | ||
| 48 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) | ||
| 49 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) | ||
| 50 | #define pci_unmap_addr(PTR, ADDR_NAME) (0) | ||
| 51 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | ||
| 52 | #define pci_unmap_len(PTR, LEN_NAME) (0) | ||
| 53 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | ||
| 54 | |||
| 55 | #define HAVE_PCI_MMAP | ||
| 56 | extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | ||
| 57 | enum pci_mmap_state mmap_state, int write_combine); | ||
| 58 | |||
| 59 | |||
| 60 | #endif /* __KERNEL__ */ | ||
| 61 | |||
| 62 | /* implement the pci_ DMA API in terms of the generic device dma_ one */ | ||
| 63 | #include <asm-generic/pci-dma-compat.h> | ||
| 64 | |||
| 65 | /* generic pci stuff */ | ||
| 66 | #include <asm-generic/pci.h> | ||
| 67 | |||
| 68 | #endif /* __ASM_CRIS_PCI_H */ | ||
diff --git a/include/asm-cris/percpu.h b/include/asm-cris/percpu.h deleted file mode 100644 index 6db9b43cf80a..000000000000 --- a/include/asm-cris/percpu.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _CRIS_PERCPU_H | ||
| 2 | #define _CRIS_PERCPU_H | ||
| 3 | |||
| 4 | #include <asm-generic/percpu.h> | ||
| 5 | |||
| 6 | #endif /* _CRIS_PERCPU_H */ | ||
diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h deleted file mode 100644 index a1ba761d0573..000000000000 --- a/include/asm-cris/pgalloc.h +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | #ifndef _CRIS_PGALLOC_H | ||
| 2 | #define _CRIS_PGALLOC_H | ||
| 3 | |||
| 4 | #include <linux/threads.h> | ||
| 5 | #include <linux/mm.h> | ||
| 6 | |||
| 7 | #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) | ||
| 8 | #define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) | ||
| 9 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 10 | |||
| 11 | /* | ||
| 12 | * Allocate and free page tables. | ||
| 13 | */ | ||
| 14 | |||
| 15 | static inline pgd_t *pgd_alloc (struct mm_struct *mm) | ||
| 16 | { | ||
| 17 | return (pgd_t *)get_zeroed_page(GFP_KERNEL); | ||
| 18 | } | ||
| 19 | |||
| 20 | static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) | ||
| 21 | { | ||
| 22 | free_page((unsigned long)pgd); | ||
| 23 | } | ||
| 24 | |||
| 25 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) | ||
| 26 | { | ||
| 27 | pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); | ||
| 28 | return pte; | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) | ||
| 32 | { | ||
| 33 | struct page *pte; | ||
| 34 | pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); | ||
| 35 | pgtable_page_ctor(pte); | ||
| 36 | return pte; | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | ||
| 40 | { | ||
| 41 | free_page((unsigned long)pte); | ||
| 42 | } | ||
| 43 | |||
| 44 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) | ||
| 45 | { | ||
| 46 | pgtable_page_dtor(pte); | ||
| 47 | __free_page(pte); | ||
| 48 | } | ||
| 49 | |||
| 50 | #define __pte_free_tlb(tlb,pte) \ | ||
| 51 | do { \ | ||
| 52 | pgtable_page_dtor(pte); \ | ||
| 53 | tlb_remove_page((tlb), pte); \ | ||
| 54 | } while (0) | ||
| 55 | |||
| 56 | #define check_pgt_cache() do { } while (0) | ||
| 57 | |||
| 58 | #endif | ||
diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h deleted file mode 100644 index 829e7a7d9fb9..000000000000 --- a/include/asm-cris/pgtable.h +++ /dev/null | |||
| @@ -1,299 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * CRIS pgtable.h - macros and functions to manipulate page tables. | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _CRIS_PGTABLE_H | ||
| 6 | #define _CRIS_PGTABLE_H | ||
| 7 | |||
| 8 | #include <asm/page.h> | ||
| 9 | #include <asm-generic/pgtable-nopmd.h> | ||
| 10 | |||
| 11 | #ifndef __ASSEMBLY__ | ||
| 12 | #include <linux/sched.h> | ||
| 13 | #include <asm/mmu.h> | ||
| 14 | #endif | ||
| 15 | #include <asm/arch/pgtable.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * The Linux memory management assumes a three-level page table setup. On | ||
| 19 | * CRIS, we use that, but "fold" the mid level into the top-level page | ||
| 20 | * table. Since the MMU TLB is software loaded through an interrupt, it | ||
| 21 | * supports any page table structure, so we could have used a three-level | ||
| 22 | * setup, but for the amounts of memory we normally use, a two-level is | ||
| 23 | * probably more efficient. | ||
| 24 | * | ||
| 25 | * This file contains the functions and defines necessary to modify and use | ||
| 26 | * the CRIS page table tree. | ||
| 27 | */ | ||
| 28 | #ifndef __ASSEMBLY__ | ||
| 29 | extern void paging_init(void); | ||
| 30 | #endif | ||
| 31 | |||
| 32 | /* Certain architectures need to do special things when pte's | ||
| 33 | * within a page table are directly modified. Thus, the following | ||
| 34 | * hook is made available. | ||
| 35 | */ | ||
| 36 | #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) | ||
| 37 | #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) | ||
| 38 | |||
| 39 | /* | ||
| 40 | * (pmds are folded into pgds so this doesn't get actually called, | ||
| 41 | * but the define is needed for a generic inline function.) | ||
| 42 | */ | ||
| 43 | #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) | ||
| 44 | #define set_pgu(pudptr, pudval) (*(pudptr) = pudval) | ||
| 45 | |||
| 46 | /* PGDIR_SHIFT determines the size of the area a second-level page table can | ||
| 47 | * map. It is equal to the page size times the number of PTE's that fit in | ||
| 48 | * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. | ||
| 49 | */ | ||
| 50 | |||
| 51 | #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) | ||
| 52 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
| 53 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
| 54 | |||
| 55 | /* | ||
| 56 | * entries per page directory level: we use a two-level, so | ||
| 57 | * we don't really have any PMD directory physically. | ||
| 58 | * pointers are 4 bytes so we can use the page size and | ||
| 59 | * divide it by 4 (shift by 2). | ||
| 60 | */ | ||
| 61 | #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) | ||
| 62 | #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) | ||
| 63 | |||
| 64 | /* calculate how many PGD entries a user-level program can use | ||
| 65 | * the first mappable virtual address is 0 | ||
| 66 | * (TASK_SIZE is the maximum virtual address space) | ||
| 67 | */ | ||
| 68 | |||
| 69 | #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) | ||
| 70 | #define FIRST_USER_ADDRESS 0 | ||
| 71 | |||
| 72 | /* zero page used for uninitialized stuff */ | ||
| 73 | #ifndef __ASSEMBLY__ | ||
| 74 | extern unsigned long empty_zero_page; | ||
| 75 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | ||
| 76 | #endif | ||
| 77 | |||
| 78 | /* number of bits that fit into a memory pointer */ | ||
| 79 | #define BITS_PER_PTR (8*sizeof(unsigned long)) | ||
| 80 | |||
| 81 | /* to align the pointer to a pointer address */ | ||
| 82 | #define PTR_MASK (~(sizeof(void*)-1)) | ||
| 83 | |||
| 84 | /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */ | ||
| 85 | /* 64-bit machines, beware! SRB. */ | ||
| 86 | #define SIZEOF_PTR_LOG2 2 | ||
| 87 | |||
| 88 | /* to find an entry in a page-table */ | ||
| 89 | #define PAGE_PTR(address) \ | ||
| 90 | ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) | ||
| 91 | |||
| 92 | /* to set the page-dir */ | ||
| 93 | #define SET_PAGE_DIR(tsk,pgdir) | ||
| 94 | |||
| 95 | #define pte_none(x) (!pte_val(x)) | ||
| 96 | #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) | ||
| 97 | #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) | ||
| 98 | |||
| 99 | #define pmd_none(x) (!pmd_val(x)) | ||
| 100 | /* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad | ||
| 101 | * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. | ||
| 102 | */ | ||
| 103 | #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) | ||
| 104 | #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) | ||
| 105 | #define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) | ||
| 106 | |||
| 107 | #ifndef __ASSEMBLY__ | ||
| 108 | |||
| 109 | /* | ||
| 110 | * The following only work if pte_present() is true. | ||
| 111 | * Undefined behaviour if not.. | ||
| 112 | */ | ||
| 113 | |||
| 114 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } | ||
| 115 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } | ||
| 116 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } | ||
| 117 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } | ||
| 118 | static inline int pte_special(pte_t pte) { return 0; } | ||
| 119 | |||
| 120 | static inline pte_t pte_wrprotect(pte_t pte) | ||
| 121 | { | ||
| 122 | pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); | ||
| 123 | return pte; | ||
| 124 | } | ||
| 125 | |||
| 126 | static inline pte_t pte_mkclean(pte_t pte) | ||
| 127 | { | ||
| 128 | pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); | ||
| 129 | return pte; | ||
| 130 | } | ||
| 131 | |||
| 132 | static inline pte_t pte_mkold(pte_t pte) | ||
| 133 | { | ||
| 134 | pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); | ||
| 135 | return pte; | ||
| 136 | } | ||
| 137 | |||
| 138 | static inline pte_t pte_mkwrite(pte_t pte) | ||
| 139 | { | ||
| 140 | pte_val(pte) |= _PAGE_WRITE; | ||
| 141 | if (pte_val(pte) & _PAGE_MODIFIED) | ||
| 142 | pte_val(pte) |= _PAGE_SILENT_WRITE; | ||
| 143 | return pte; | ||
| 144 | } | ||
| 145 | |||
| 146 | static inline pte_t pte_mkdirty(pte_t pte) | ||
| 147 | { | ||
| 148 | pte_val(pte) |= _PAGE_MODIFIED; | ||
| 149 | if (pte_val(pte) & _PAGE_WRITE) | ||
| 150 | pte_val(pte) |= _PAGE_SILENT_WRITE; | ||
| 151 | return pte; | ||
| 152 | } | ||
| 153 | |||
| 154 | static inline pte_t pte_mkyoung(pte_t pte) | ||
| 155 | { | ||
| 156 | pte_val(pte) |= _PAGE_ACCESSED; | ||
| 157 | if (pte_val(pte) & _PAGE_READ) | ||
| 158 | { | ||
| 159 | pte_val(pte) |= _PAGE_SILENT_READ; | ||
| 160 | if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) == | ||
| 161 | (_PAGE_WRITE | _PAGE_MODIFIED)) | ||
| 162 | pte_val(pte) |= _PAGE_SILENT_WRITE; | ||
| 163 | } | ||
| 164 | return pte; | ||
| 165 | } | ||
| 166 | static inline pte_t pte_mkspecial(pte_t pte) { return pte; } | ||
| 167 | |||
| 168 | /* | ||
| 169 | * Conversion functions: convert a page and protection to a page entry, | ||
| 170 | * and a page entry and page directory to the page they refer to. | ||
| 171 | */ | ||
| 172 | |||
| 173 | /* What actually goes as arguments to the various functions is less than | ||
| 174 | * obvious, but a rule of thumb is that struct page's goes as struct page *, | ||
| 175 | * really physical DRAM addresses are unsigned long's, and DRAM "virtual" | ||
| 176 | * addresses (the 0xc0xxxxxx's) goes as void *'s. | ||
| 177 | */ | ||
| 178 | |||
| 179 | static inline pte_t __mk_pte(void * page, pgprot_t pgprot) | ||
| 180 | { | ||
| 181 | pte_t pte; | ||
| 182 | /* the PTE needs a physical address */ | ||
| 183 | pte_val(pte) = __pa(page) | pgprot_val(pgprot); | ||
| 184 | return pte; | ||
| 185 | } | ||
| 186 | |||
| 187 | #define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot)) | ||
| 188 | |||
| 189 | #define mk_pte_phys(physpage, pgprot) \ | ||
| 190 | ({ \ | ||
| 191 | pte_t __pte; \ | ||
| 192 | \ | ||
| 193 | pte_val(__pte) = (physpage) + pgprot_val(pgprot); \ | ||
| 194 | __pte; \ | ||
| 195 | }) | ||
| 196 | |||
| 197 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | ||
| 198 | { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } | ||
| 199 | |||
| 200 | |||
| 201 | /* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval | ||
| 202 | * __pte_page(pte_val) refers to the "virtual" DRAM interval | ||
| 203 | * pte_pagenr refers to the page-number counted starting from the virtual DRAM start | ||
| 204 | */ | ||
| 205 | |||
| 206 | static inline unsigned long __pte_page(pte_t pte) | ||
| 207 | { | ||
| 208 | /* the PTE contains a physical address */ | ||
| 209 | return (unsigned long)__va(pte_val(pte) & PAGE_MASK); | ||
| 210 | } | ||
| 211 | |||
| 212 | #define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) | ||
| 213 | |||
| 214 | /* permanent address of a page */ | ||
| 215 | |||
| 216 | #define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) | ||
| 217 | #define pte_page(pte) (mem_map+pte_pagenr(pte)) | ||
| 218 | |||
| 219 | /* only the pte's themselves need to point to physical DRAM (see above) | ||
| 220 | * the pagetable links are purely handled within the kernel SW and thus | ||
| 221 | * don't need the __pa and __va transformations. | ||
| 222 | */ | ||
| 223 | |||
| 224 | static inline void pmd_set(pmd_t * pmdp, pte_t * ptep) | ||
| 225 | { pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; } | ||
| 226 | |||
| 227 | #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) | ||
| 228 | #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) | ||
| 229 | |||
| 230 | /* to find an entry in a page-table-directory. */ | ||
| 231 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) | ||
| 232 | |||
| 233 | /* to find an entry in a page-table-directory */ | ||
| 234 | static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address) | ||
| 235 | { | ||
| 236 | return mm->pgd + pgd_index(address); | ||
| 237 | } | ||
| 238 | |||
| 239 | /* to find an entry in a kernel page-table-directory */ | ||
| 240 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | ||
| 241 | |||
| 242 | /* Find an entry in the third-level page table.. */ | ||
| 243 | #define __pte_offset(address) \ | ||
| 244 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
| 245 | #define pte_offset_kernel(dir, address) \ | ||
| 246 | ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) | ||
| 247 | #define pte_offset_map(dir, address) \ | ||
| 248 | ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) | ||
| 249 | #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address) | ||
| 250 | |||
| 251 | #define pte_unmap(pte) do { } while (0) | ||
| 252 | #define pte_unmap_nested(pte) do { } while (0) | ||
| 253 | #define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) | ||
| 254 | #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) | ||
| 255 | |||
| 256 | #define pte_ERROR(e) \ | ||
| 257 | printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) | ||
| 258 | #define pgd_ERROR(e) \ | ||
| 259 | printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) | ||
| 260 | |||
| 261 | |||
| 262 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ | ||
| 263 | |||
| 264 | /* | ||
| 265 | * CRIS doesn't have any external MMU info: the kernel page | ||
| 266 | * tables contain all the necessary information. | ||
| 267 | * | ||
| 268 | * Actually I am not sure on what this could be used for. | ||
| 269 | */ | ||
| 270 | static inline void update_mmu_cache(struct vm_area_struct * vma, | ||
| 271 | unsigned long address, pte_t pte) | ||
| 272 | { | ||
| 273 | } | ||
| 274 | |||
| 275 | /* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ | ||
| 276 | /* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */ | ||
| 277 | |||
| 278 | #define __swp_type(x) (((x).val >> 5) & 0x7f) | ||
| 279 | #define __swp_offset(x) ((x).val >> 12) | ||
| 280 | #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) }) | ||
| 281 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
| 282 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | ||
| 283 | |||
| 284 | #define kern_addr_valid(addr) (1) | ||
| 285 | |||
| 286 | #include <asm-generic/pgtable.h> | ||
| 287 | |||
| 288 | /* | ||
| 289 | * No page table caches to initialise | ||
| 290 | */ | ||
| 291 | #define pgtable_cache_init() do { } while (0) | ||
| 292 | |||
| 293 | #define pte_to_pgoff(x) (pte_val(x) >> 6) | ||
| 294 | #define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE) | ||
| 295 | |||
| 296 | typedef pte_t *pte_addr_t; | ||
| 297 | |||
| 298 | #endif /* __ASSEMBLY__ */ | ||
| 299 | #endif /* _CRIS_PGTABLE_H */ | ||
diff --git a/include/asm-cris/poll.h b/include/asm-cris/poll.h deleted file mode 100644 index c98509d3149e..000000000000 --- a/include/asm-cris/poll.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/poll.h> | ||
diff --git a/include/asm-cris/posix_types.h b/include/asm-cris/posix_types.h deleted file mode 100644 index ce3fb25a460b..000000000000 --- a/include/asm-cris/posix_types.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | /* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ | ||
| 2 | |||
| 3 | /* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ | ||
| 4 | /* I guess we should write these in assembler because they are used often. */ | ||
| 5 | |||
| 6 | #ifndef __ARCH_CRIS_POSIX_TYPES_H | ||
| 7 | #define __ARCH_CRIS_POSIX_TYPES_H | ||
| 8 | |||
| 9 | /* | ||
| 10 | * This file is generally used by user-level software, so you need to | ||
| 11 | * be a little careful about namespace pollution etc. Also, we cannot | ||
| 12 | * assume GCC is being used. | ||
| 13 | */ | ||
| 14 | |||
| 15 | typedef unsigned long __kernel_ino_t; | ||
| 16 | typedef unsigned short __kernel_mode_t; | ||
| 17 | typedef unsigned short __kernel_nlink_t; | ||
| 18 | typedef long __kernel_off_t; | ||
| 19 | typedef int __kernel_pid_t; | ||
| 20 | typedef unsigned short __kernel_ipc_pid_t; | ||
| 21 | typedef unsigned short __kernel_uid_t; | ||
| 22 | typedef unsigned short __kernel_gid_t; | ||
| 23 | typedef __SIZE_TYPE__ __kernel_size_t; | ||
| 24 | typedef long __kernel_ssize_t; | ||
| 25 | typedef int __kernel_ptrdiff_t; | ||
| 26 | typedef long __kernel_time_t; | ||
| 27 | typedef long __kernel_suseconds_t; | ||
| 28 | typedef long __kernel_clock_t; | ||
| 29 | typedef int __kernel_timer_t; | ||
| 30 | typedef int __kernel_clockid_t; | ||
| 31 | typedef int __kernel_daddr_t; | ||
| 32 | typedef char * __kernel_caddr_t; | ||
| 33 | typedef unsigned short __kernel_uid16_t; | ||
| 34 | typedef unsigned short __kernel_gid16_t; | ||
| 35 | typedef unsigned int __kernel_uid32_t; | ||
| 36 | typedef unsigned int __kernel_gid32_t; | ||
| 37 | |||
| 38 | typedef unsigned short __kernel_old_uid_t; | ||
| 39 | typedef unsigned short __kernel_old_gid_t; | ||
| 40 | typedef unsigned short __kernel_old_dev_t; | ||
| 41 | |||
| 42 | #ifdef __GNUC__ | ||
| 43 | typedef long long __kernel_loff_t; | ||
| 44 | #endif | ||
| 45 | |||
| 46 | typedef struct { | ||
| 47 | int val[2]; | ||
| 48 | } __kernel_fsid_t; | ||
| 49 | |||
| 50 | #ifdef __KERNEL__ | ||
| 51 | |||
| 52 | #undef __FD_SET | ||
| 53 | #define __FD_SET(fd,fdsetp) set_bit(fd, (void *)(fdsetp)) | ||
| 54 | |||
| 55 | #undef __FD_CLR | ||
| 56 | #define __FD_CLR(fd,fdsetp) clear_bit(fd, (void *)(fdsetp)) | ||
| 57 | |||
| 58 | #undef __FD_ISSET | ||
| 59 | #define __FD_ISSET(fd,fdsetp) test_bit(fd, (void *)(fdsetp)) | ||
| 60 | |||
| 61 | #undef __FD_ZERO | ||
| 62 | #define __FD_ZERO(fdsetp) memset((void *)(fdsetp), 0, __FDSET_LONGS << 2) | ||
| 63 | |||
| 64 | #endif /* __KERNEL__ */ | ||
| 65 | |||
| 66 | #endif /* __ARCH_CRIS_POSIX_TYPES_H */ | ||
diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h deleted file mode 100644 index cdc0c1dce6be..000000000000 --- a/include/asm-cris/processor.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-cris/processor.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000, 2001 Axis Communications AB | ||
| 5 | * | ||
| 6 | * Authors: Bjorn Wesen Initial version | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_CRIS_PROCESSOR_H | ||
| 11 | #define __ASM_CRIS_PROCESSOR_H | ||
| 12 | |||
| 13 | #include <asm/system.h> | ||
| 14 | #include <asm/page.h> | ||
| 15 | #include <asm/ptrace.h> | ||
| 16 | #include <asm/arch/processor.h> | ||
| 17 | |||
| 18 | struct task_struct; | ||
| 19 | |||
| 20 | #define STACK_TOP TASK_SIZE | ||
| 21 | #define STACK_TOP_MAX STACK_TOP | ||
| 22 | |||
| 23 | /* This decides where the kernel will search for a free chunk of vm | ||
| 24 | * space during mmap's. | ||
| 25 | */ | ||
| 26 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) | ||
| 27 | |||
| 28 | /* THREAD_SIZE is the size of the task_struct/kernel_stack combo. | ||
| 29 | * normally, the stack is found by doing something like p + THREAD_SIZE | ||
| 30 | * in CRIS, a page is 8192 bytes, which seems like a sane size | ||
| 31 | */ | ||
| 32 | |||
| 33 | #define THREAD_SIZE PAGE_SIZE | ||
| 34 | #define KERNEL_STACK_SIZE PAGE_SIZE | ||
| 35 | |||
| 36 | /* | ||
| 37 | * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack. | ||
| 38 | * This macro allows us to find those regs for a task. | ||
| 39 | * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while | ||
| 40 | * we're in the kernel, won't affect this - only the first user->kernel transition | ||
| 41 | * registers are reached by this. | ||
| 42 | */ | ||
| 43 | |||
| 44 | #define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1) | ||
| 45 | |||
| 46 | /* | ||
| 47 | * Dito but for the currently running task | ||
| 48 | */ | ||
| 49 | |||
| 50 | #define task_pt_regs(task) user_regs(task_thread_info(task)) | ||
| 51 | #define current_regs() task_pt_regs(current) | ||
| 52 | |||
| 53 | static inline void prepare_to_copy(struct task_struct *tsk) | ||
| 54 | { | ||
| 55 | } | ||
| 56 | |||
| 57 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); | ||
| 58 | |||
| 59 | unsigned long get_wchan(struct task_struct *p); | ||
| 60 | |||
| 61 | #define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) | ||
| 62 | |||
| 63 | extern unsigned long thread_saved_pc(struct task_struct *tsk); | ||
| 64 | |||
| 65 | /* Free all resources held by a thread. */ | ||
| 66 | static inline void release_thread(struct task_struct *dead_task) | ||
| 67 | { | ||
| 68 | /* Nothing needs to be done. */ | ||
| 69 | } | ||
| 70 | |||
| 71 | #define init_stack (init_thread_union.stack) | ||
| 72 | |||
| 73 | #define cpu_relax() barrier() | ||
| 74 | |||
| 75 | #endif /* __ASM_CRIS_PROCESSOR_H */ | ||
diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h deleted file mode 100644 index d910925e3174..000000000000 --- a/include/asm-cris/ptrace.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | #ifndef _CRIS_PTRACE_H | ||
| 2 | #define _CRIS_PTRACE_H | ||
| 3 | |||
| 4 | #include <asm/arch/ptrace.h> | ||
| 5 | |||
| 6 | #ifdef __KERNEL__ | ||
| 7 | |||
| 8 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | ||
| 9 | #define PTRACE_GETREGS 12 | ||
| 10 | #define PTRACE_SETREGS 13 | ||
| 11 | |||
| 12 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 13 | |||
| 14 | #endif /* __KERNEL__ */ | ||
| 15 | |||
| 16 | #endif /* _CRIS_PTRACE_H */ | ||
diff --git a/include/asm-cris/resource.h b/include/asm-cris/resource.h deleted file mode 100644 index b5d29448de4e..000000000000 --- a/include/asm-cris/resource.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _CRIS_RESOURCE_H | ||
| 2 | #define _CRIS_RESOURCE_H | ||
| 3 | |||
| 4 | #include <asm-generic/resource.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/rs485.h b/include/asm-cris/rs485.h deleted file mode 100644 index c331c51b0c2b..000000000000 --- a/include/asm-cris/rs485.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* RS-485 structures */ | ||
| 2 | |||
| 3 | /* RS-485 support */ | ||
| 4 | /* Used with ioctl() TIOCSERSETRS485 */ | ||
| 5 | struct rs485_control { | ||
| 6 | unsigned short rts_on_send; | ||
| 7 | unsigned short rts_after_sent; | ||
| 8 | unsigned long delay_rts_before_send; | ||
| 9 | unsigned short enabled; | ||
| 10 | #ifdef __KERNEL__ | ||
| 11 | int disable_serial_loopback; | ||
| 12 | #endif | ||
| 13 | }; | ||
| 14 | |||
| 15 | /* Used with ioctl() TIOCSERWRRS485 */ | ||
| 16 | struct rs485_write { | ||
| 17 | unsigned short outc_size; | ||
| 18 | unsigned char *outc; | ||
| 19 | }; | ||
| 20 | |||
diff --git a/include/asm-cris/rtc.h b/include/asm-cris/rtc.h deleted file mode 100644 index 17d3019529e1..000000000000 --- a/include/asm-cris/rtc.h +++ /dev/null | |||
| @@ -1,107 +0,0 @@ | |||
| 1 | |||
| 2 | #ifndef __RTC_H__ | ||
| 3 | #define __RTC_H__ | ||
| 4 | |||
| 5 | #ifdef CONFIG_ETRAX_DS1302 | ||
| 6 | /* Dallas DS1302 clock/calendar register numbers. */ | ||
| 7 | # define RTC_SECONDS 0 | ||
| 8 | # define RTC_MINUTES 1 | ||
| 9 | # define RTC_HOURS 2 | ||
| 10 | # define RTC_DAY_OF_MONTH 3 | ||
| 11 | # define RTC_MONTH 4 | ||
| 12 | # define RTC_WEEKDAY 5 | ||
| 13 | # define RTC_YEAR 6 | ||
| 14 | # define RTC_CONTROL 7 | ||
| 15 | |||
| 16 | /* Bits in CONTROL register. */ | ||
| 17 | # define RTC_CONTROL_WRITEPROTECT 0x80 | ||
| 18 | # define RTC_TRICKLECHARGER 8 | ||
| 19 | |||
| 20 | /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */ | ||
| 21 | # define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ | ||
| 22 | # define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ | ||
| 23 | # define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ | ||
| 24 | # define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ | ||
| 25 | # define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ | ||
| 26 | # define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ | ||
| 27 | # define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ | ||
| 28 | |||
| 29 | #elif defined(CONFIG_ETRAX_PCF8563) | ||
| 30 | /* I2C bus slave registers. */ | ||
| 31 | # define RTC_I2C_READ 0xa3 | ||
| 32 | # define RTC_I2C_WRITE 0xa2 | ||
| 33 | |||
| 34 | /* Phillips PCF8563 registers. */ | ||
| 35 | # define RTC_CONTROL1 0x00 /* Control/Status register 1. */ | ||
| 36 | # define RTC_CONTROL2 0x01 /* Control/Status register 2. */ | ||
| 37 | # define RTC_CLOCKOUT_FREQ 0x0d /* CLKOUT frequency. */ | ||
| 38 | # define RTC_TIMER_CONTROL 0x0e /* Timer control. */ | ||
| 39 | # define RTC_TIMER_CNTDOWN 0x0f /* Timer countdown. */ | ||
| 40 | |||
| 41 | /* BCD encoded clock registers. */ | ||
| 42 | # define RTC_SECONDS 0x02 | ||
| 43 | # define RTC_MINUTES 0x03 | ||
| 44 | # define RTC_HOURS 0x04 | ||
| 45 | # define RTC_DAY_OF_MONTH 0x05 | ||
| 46 | # define RTC_WEEKDAY 0x06 /* Not coded in BCD! */ | ||
| 47 | # define RTC_MONTH 0x07 | ||
| 48 | # define RTC_YEAR 0x08 | ||
| 49 | # define RTC_MINUTE_ALARM 0x09 | ||
| 50 | # define RTC_HOUR_ALARM 0x0a | ||
| 51 | # define RTC_DAY_ALARM 0x0b | ||
| 52 | # define RTC_WEEKDAY_ALARM 0x0c | ||
| 53 | |||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifdef CONFIG_ETRAX_DS1302 | ||
| 57 | extern unsigned char ds1302_readreg(int reg); | ||
| 58 | extern void ds1302_writereg(int reg, unsigned char val); | ||
| 59 | extern int ds1302_init(void); | ||
| 60 | # define CMOS_READ(x) ds1302_readreg(x) | ||
| 61 | # define CMOS_WRITE(val,reg) ds1302_writereg(reg,val) | ||
| 62 | # define RTC_INIT() ds1302_init() | ||
| 63 | #elif defined(CONFIG_ETRAX_PCF8563) | ||
| 64 | extern unsigned char pcf8563_readreg(int reg); | ||
| 65 | extern void pcf8563_writereg(int reg, unsigned char val); | ||
| 66 | extern int pcf8563_init(void); | ||
| 67 | # define CMOS_READ(x) pcf8563_readreg(x) | ||
| 68 | # define CMOS_WRITE(val,reg) pcf8563_writereg(reg,val) | ||
| 69 | # define RTC_INIT() pcf8563_init() | ||
| 70 | #else | ||
| 71 | /* No RTC configured so we shouldn't try to access any. */ | ||
| 72 | # define CMOS_READ(x) 42 | ||
| 73 | # define CMOS_WRITE(x,y) | ||
| 74 | # define RTC_INIT() (-1) | ||
| 75 | #endif | ||
| 76 | |||
| 77 | /* | ||
| 78 | * The struct used to pass data via the following ioctl. Similar to the | ||
| 79 | * struct tm in <time.h>, but it needs to be here so that the kernel | ||
| 80 | * source is self contained, allowing cross-compiles, etc. etc. | ||
| 81 | */ | ||
| 82 | struct rtc_time { | ||
| 83 | int tm_sec; | ||
| 84 | int tm_min; | ||
| 85 | int tm_hour; | ||
| 86 | int tm_mday; | ||
| 87 | int tm_mon; | ||
| 88 | int tm_year; | ||
| 89 | int tm_wday; | ||
| 90 | int tm_yday; | ||
| 91 | int tm_isdst; | ||
| 92 | }; | ||
| 93 | |||
| 94 | /* ioctl() calls that are permitted to the /dev/rtc interface. */ | ||
| 95 | #define RTC_MAGIC 'p' | ||
| 96 | /* Read RTC time. */ | ||
| 97 | #define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) | ||
| 98 | /* Set RTC time. */ | ||
| 99 | #define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) | ||
| 100 | #define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) | ||
| 101 | /* Voltage low detector */ | ||
| 102 | #define RTC_VL_READ _IOR(RTC_MAGIC, 0x13, int) | ||
| 103 | /* Clear voltage low information */ | ||
| 104 | #define RTC_VL_CLR _IO(RTC_MAGIC, 0x14) | ||
| 105 | #define RTC_MAX_IOCTL 0x14 | ||
| 106 | |||
| 107 | #endif /* __RTC_H__ */ | ||
diff --git a/include/asm-cris/scatterlist.h b/include/asm-cris/scatterlist.h deleted file mode 100644 index faff53ad1f96..000000000000 --- a/include/asm-cris/scatterlist.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_SCATTERLIST_H | ||
| 2 | #define __ASM_CRIS_SCATTERLIST_H | ||
| 3 | |||
| 4 | struct scatterlist { | ||
| 5 | #ifdef CONFIG_DEBUG_SG | ||
| 6 | unsigned long sg_magic; | ||
| 7 | #endif | ||
| 8 | char * address; /* Location data is to be transferred to */ | ||
| 9 | unsigned int length; | ||
| 10 | |||
| 11 | /* The following is i386 highmem junk - not used by us */ | ||
| 12 | unsigned long page_link; | ||
| 13 | unsigned int offset;/* for highmem, page offset */ | ||
| 14 | |||
| 15 | }; | ||
| 16 | |||
| 17 | #define sg_dma_address(sg) ((sg)->address) | ||
| 18 | #define sg_dma_len(sg) ((sg)->length) | ||
| 19 | /* i386 junk */ | ||
| 20 | |||
| 21 | #define ISA_DMA_THRESHOLD (0x1fffffff) | ||
| 22 | |||
| 23 | #endif /* !(__ASM_CRIS_SCATTERLIST_H) */ | ||
diff --git a/include/asm-cris/sections.h b/include/asm-cris/sections.h deleted file mode 100644 index 2c998ce8967b..000000000000 --- a/include/asm-cris/sections.h +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | #ifndef _CRIS_SECTIONS_H | ||
| 2 | #define _CRIS_SECTIONS_H | ||
| 3 | |||
| 4 | /* nothing to see, move along */ | ||
| 5 | #include <asm-generic/sections.h> | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/include/asm-cris/segment.h b/include/asm-cris/segment.h deleted file mode 100644 index c067513beaaf..000000000000 --- a/include/asm-cris/segment.h +++ /dev/null | |||
| @@ -1,8 +0,0 @@ | |||
| 1 | #ifndef _ASM_SEGMENT_H | ||
| 2 | #define _ASM_SEGMENT_H | ||
| 3 | |||
| 4 | typedef struct { | ||
| 5 | unsigned long seg; | ||
| 6 | } mm_segment_t; | ||
| 7 | |||
| 8 | #endif | ||
diff --git a/include/asm-cris/sembuf.h b/include/asm-cris/sembuf.h deleted file mode 100644 index 7fed9843796d..000000000000 --- a/include/asm-cris/sembuf.h +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | #ifndef _CRIS_SEMBUF_H | ||
| 2 | #define _CRIS_SEMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The semid64_ds structure for CRIS architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct semid64_ds { | ||
| 15 | struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ | ||
| 16 | __kernel_time_t sem_otime; /* last semop time */ | ||
| 17 | unsigned long __unused1; | ||
| 18 | __kernel_time_t sem_ctime; /* last change time */ | ||
| 19 | unsigned long __unused2; | ||
| 20 | unsigned long sem_nsems; /* no. of semaphores in array */ | ||
| 21 | unsigned long __unused3; | ||
| 22 | unsigned long __unused4; | ||
| 23 | }; | ||
| 24 | |||
| 25 | #endif /* _CRIS_SEMBUF_H */ | ||
diff --git a/include/asm-cris/setup.h b/include/asm-cris/setup.h deleted file mode 100644 index b90728652d1a..000000000000 --- a/include/asm-cris/setup.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _CRIS_SETUP_H | ||
| 2 | #define _CRIS_SETUP_H | ||
| 3 | |||
| 4 | #define COMMAND_LINE_SIZE 256 | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/shmbuf.h b/include/asm-cris/shmbuf.h deleted file mode 100644 index 3239e3f000e8..000000000000 --- a/include/asm-cris/shmbuf.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | #ifndef _CRIS_SHMBUF_H | ||
| 2 | #define _CRIS_SHMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The shmid64_ds structure for CRIS architecture (same as for i386) | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct shmid64_ds { | ||
| 15 | struct ipc64_perm shm_perm; /* operation perms */ | ||
| 16 | size_t shm_segsz; /* size of segment (bytes) */ | ||
| 17 | __kernel_time_t shm_atime; /* last attach time */ | ||
| 18 | unsigned long __unused1; | ||
| 19 | __kernel_time_t shm_dtime; /* last detach time */ | ||
| 20 | unsigned long __unused2; | ||
| 21 | __kernel_time_t shm_ctime; /* last change time */ | ||
| 22 | unsigned long __unused3; | ||
| 23 | __kernel_pid_t shm_cpid; /* pid of creator */ | ||
| 24 | __kernel_pid_t shm_lpid; /* pid of last operator */ | ||
| 25 | unsigned long shm_nattch; /* no. of current attaches */ | ||
| 26 | unsigned long __unused4; | ||
| 27 | unsigned long __unused5; | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct shminfo64 { | ||
| 31 | unsigned long shmmax; | ||
| 32 | unsigned long shmmin; | ||
| 33 | unsigned long shmmni; | ||
| 34 | unsigned long shmseg; | ||
| 35 | unsigned long shmall; | ||
| 36 | unsigned long __unused1; | ||
| 37 | unsigned long __unused2; | ||
| 38 | unsigned long __unused3; | ||
| 39 | unsigned long __unused4; | ||
| 40 | }; | ||
| 41 | |||
| 42 | #endif /* _CRIS_SHMBUF_H */ | ||
diff --git a/include/asm-cris/shmparam.h b/include/asm-cris/shmparam.h deleted file mode 100644 index d29d12270687..000000000000 --- a/include/asm-cris/shmparam.h +++ /dev/null | |||
| @@ -1,8 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_SHMPARAM_H | ||
| 2 | #define _ASM_CRIS_SHMPARAM_H | ||
| 3 | |||
| 4 | /* same as asm-i386/ version.. */ | ||
| 5 | |||
| 6 | #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ | ||
| 7 | |||
| 8 | #endif /* _ASM_CRIS_SHMPARAM_H */ | ||
diff --git a/include/asm-cris/sigcontext.h b/include/asm-cris/sigcontext.h deleted file mode 100644 index a1d634e120df..000000000000 --- a/include/asm-cris/sigcontext.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ | ||
| 2 | |||
| 3 | #ifndef _ASM_CRIS_SIGCONTEXT_H | ||
| 4 | #define _ASM_CRIS_SIGCONTEXT_H | ||
| 5 | |||
| 6 | #include <asm/ptrace.h> | ||
| 7 | |||
| 8 | /* This struct is saved by setup_frame in signal.c, to keep the current context while | ||
| 9 | a signal handler is executed. It's restored by sys_sigreturn. | ||
| 10 | |||
| 11 | To keep things simple, we use pt_regs here even though normally you just specify | ||
| 12 | the list of regs to save. Then we can use copy_from_user on the entire regs instead | ||
| 13 | of a bunch of get_user's as well... | ||
| 14 | |||
| 15 | */ | ||
| 16 | |||
| 17 | struct sigcontext { | ||
| 18 | struct pt_regs regs; /* needs to be first */ | ||
| 19 | unsigned long oldmask; | ||
| 20 | unsigned long usp; /* usp before stacking this gunk on it */ | ||
| 21 | }; | ||
| 22 | |||
| 23 | #endif | ||
| 24 | |||
diff --git a/include/asm-cris/siginfo.h b/include/asm-cris/siginfo.h deleted file mode 100644 index c1cd6d16928b..000000000000 --- a/include/asm-cris/siginfo.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _CRIS_SIGINFO_H | ||
| 2 | #define _CRIS_SIGINFO_H | ||
| 3 | |||
| 4 | #include <asm-generic/siginfo.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/signal.h b/include/asm-cris/signal.h deleted file mode 100644 index 349ae682b568..000000000000 --- a/include/asm-cris/signal.h +++ /dev/null | |||
| @@ -1,163 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_SIGNAL_H | ||
| 2 | #define _ASM_CRIS_SIGNAL_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* Avoid too many header ordering problems. */ | ||
| 7 | struct siginfo; | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | /* Most things should be clean enough to redefine this at will, if care | ||
| 11 | is taken to make libc match. */ | ||
| 12 | |||
| 13 | #define _NSIG 64 | ||
| 14 | #define _NSIG_BPW 32 | ||
| 15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 16 | |||
| 17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 18 | |||
| 19 | typedef struct { | ||
| 20 | unsigned long sig[_NSIG_WORDS]; | ||
| 21 | } sigset_t; | ||
| 22 | |||
| 23 | #else | ||
| 24 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 25 | |||
| 26 | #define NSIG 32 | ||
| 27 | typedef unsigned long sigset_t; | ||
| 28 | |||
| 29 | #endif /* __KERNEL__ */ | ||
| 30 | |||
| 31 | #define SIGHUP 1 | ||
| 32 | #define SIGINT 2 | ||
| 33 | #define SIGQUIT 3 | ||
| 34 | #define SIGILL 4 | ||
| 35 | #define SIGTRAP 5 | ||
| 36 | #define SIGABRT 6 | ||
| 37 | #define SIGIOT 6 | ||
| 38 | #define SIGBUS 7 | ||
| 39 | #define SIGFPE 8 | ||
| 40 | #define SIGKILL 9 | ||
| 41 | #define SIGUSR1 10 | ||
| 42 | #define SIGSEGV 11 | ||
| 43 | #define SIGUSR2 12 | ||
| 44 | #define SIGPIPE 13 | ||
| 45 | #define SIGALRM 14 | ||
| 46 | #define SIGTERM 15 | ||
| 47 | #define SIGSTKFLT 16 | ||
| 48 | #define SIGCHLD 17 | ||
| 49 | #define SIGCONT 18 | ||
| 50 | #define SIGSTOP 19 | ||
| 51 | #define SIGTSTP 20 | ||
| 52 | #define SIGTTIN 21 | ||
| 53 | #define SIGTTOU 22 | ||
| 54 | #define SIGURG 23 | ||
| 55 | #define SIGXCPU 24 | ||
| 56 | #define SIGXFSZ 25 | ||
| 57 | #define SIGVTALRM 26 | ||
| 58 | #define SIGPROF 27 | ||
| 59 | #define SIGWINCH 28 | ||
| 60 | #define SIGIO 29 | ||
| 61 | #define SIGPOLL SIGIO | ||
| 62 | /* | ||
| 63 | #define SIGLOST 29 | ||
| 64 | */ | ||
| 65 | #define SIGPWR 30 | ||
| 66 | #define SIGSYS 31 | ||
| 67 | #define SIGUNUSED 31 | ||
| 68 | |||
| 69 | /* These should not be considered constants from userland. */ | ||
| 70 | #define SIGRTMIN 32 | ||
| 71 | #define SIGRTMAX _NSIG | ||
| 72 | |||
| 73 | /* | ||
| 74 | * SA_FLAGS values: | ||
| 75 | * | ||
| 76 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 77 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 78 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 79 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 80 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 81 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 82 | * | ||
| 83 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 84 | * Unix names RESETHAND and NODEFER respectively. | ||
| 85 | */ | ||
| 86 | |||
| 87 | #define SA_NOCLDSTOP 0x00000001u | ||
| 88 | #define SA_NOCLDWAIT 0x00000002u | ||
| 89 | #define SA_SIGINFO 0x00000004u | ||
| 90 | #define SA_ONSTACK 0x08000000u | ||
| 91 | #define SA_RESTART 0x10000000u | ||
| 92 | #define SA_NODEFER 0x40000000u | ||
| 93 | #define SA_RESETHAND 0x80000000u | ||
| 94 | |||
| 95 | #define SA_NOMASK SA_NODEFER | ||
| 96 | #define SA_ONESHOT SA_RESETHAND | ||
| 97 | |||
| 98 | #define SA_RESTORER 0x04000000 | ||
| 99 | |||
| 100 | /* | ||
| 101 | * sigaltstack controls | ||
| 102 | */ | ||
| 103 | #define SS_ONSTACK 1 | ||
| 104 | #define SS_DISABLE 2 | ||
| 105 | |||
| 106 | #define MINSIGSTKSZ 2048 | ||
| 107 | #define SIGSTKSZ 8192 | ||
| 108 | |||
| 109 | #include <asm-generic/signal.h> | ||
| 110 | |||
| 111 | #ifdef __KERNEL__ | ||
| 112 | struct old_sigaction { | ||
| 113 | __sighandler_t sa_handler; | ||
| 114 | old_sigset_t sa_mask; | ||
| 115 | unsigned long sa_flags; | ||
| 116 | void (*sa_restorer)(void); | ||
| 117 | }; | ||
| 118 | |||
| 119 | struct sigaction { | ||
| 120 | __sighandler_t sa_handler; | ||
| 121 | unsigned long sa_flags; | ||
| 122 | void (*sa_restorer)(void); | ||
| 123 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 124 | }; | ||
| 125 | |||
| 126 | struct k_sigaction { | ||
| 127 | struct sigaction sa; | ||
| 128 | }; | ||
| 129 | #else | ||
| 130 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 131 | |||
| 132 | struct sigaction { | ||
| 133 | union { | ||
| 134 | __sighandler_t _sa_handler; | ||
| 135 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
| 136 | } _u; | ||
| 137 | sigset_t sa_mask; | ||
| 138 | unsigned long sa_flags; | ||
| 139 | void (*sa_restorer)(void); | ||
| 140 | }; | ||
| 141 | |||
| 142 | #define sa_handler _u._sa_handler | ||
| 143 | #define sa_sigaction _u._sa_sigaction | ||
| 144 | |||
| 145 | #endif /* __KERNEL__ */ | ||
| 146 | |||
| 147 | typedef struct sigaltstack { | ||
| 148 | void *ss_sp; | ||
| 149 | int ss_flags; | ||
| 150 | size_t ss_size; | ||
| 151 | } stack_t; | ||
| 152 | |||
| 153 | #ifdef __KERNEL__ | ||
| 154 | #include <asm/sigcontext.h> | ||
| 155 | |||
| 156 | /* here we could define asm-optimized sigaddset, sigdelset etc. operations. | ||
| 157 | * if we don't, generic ones are used from linux/signal.h | ||
| 158 | */ | ||
| 159 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
| 160 | |||
| 161 | #endif /* __KERNEL__ */ | ||
| 162 | |||
| 163 | #endif | ||
diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h deleted file mode 100644 index dba33aba3e95..000000000000 --- a/include/asm-cris/smp.h +++ /dev/null | |||
| @@ -1,11 +0,0 @@ | |||
| 1 | #ifndef __ASM_SMP_H | ||
| 2 | #define __ASM_SMP_H | ||
| 3 | |||
| 4 | #include <linux/cpumask.h> | ||
| 5 | |||
| 6 | extern cpumask_t phys_cpu_present_map; | ||
| 7 | extern cpumask_t cpu_possible_map; | ||
| 8 | |||
| 9 | #define raw_smp_processor_id() (current_thread_info()->cpu) | ||
| 10 | |||
| 11 | #endif | ||
diff --git a/include/asm-cris/socket.h b/include/asm-cris/socket.h deleted file mode 100644 index 9df0ca82f5de..000000000000 --- a/include/asm-cris/socket.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | #ifndef _ASM_SOCKET_H | ||
| 2 | #define _ASM_SOCKET_H | ||
| 3 | |||
| 4 | /* almost the same as asm-i386/socket.h */ | ||
| 5 | |||
| 6 | #include <asm/sockios.h> | ||
| 7 | |||
| 8 | /* For setsockoptions(2) */ | ||
| 9 | #define SOL_SOCKET 1 | ||
| 10 | |||
| 11 | #define SO_DEBUG 1 | ||
| 12 | #define SO_REUSEADDR 2 | ||
| 13 | #define SO_TYPE 3 | ||
| 14 | #define SO_ERROR 4 | ||
| 15 | #define SO_DONTROUTE 5 | ||
| 16 | #define SO_BROADCAST 6 | ||
| 17 | #define SO_SNDBUF 7 | ||
| 18 | #define SO_RCVBUF 8 | ||
| 19 | #define SO_SNDBUFFORCE 32 | ||
| 20 | #define SO_RCVBUFFORCE 33 | ||
| 21 | #define SO_KEEPALIVE 9 | ||
| 22 | #define SO_OOBINLINE 10 | ||
| 23 | #define SO_NO_CHECK 11 | ||
| 24 | #define SO_PRIORITY 12 | ||
| 25 | #define SO_LINGER 13 | ||
| 26 | #define SO_BSDCOMPAT 14 | ||
| 27 | /* To add :#define SO_REUSEPORT 15 */ | ||
| 28 | #define SO_PASSCRED 16 | ||
| 29 | #define SO_PEERCRED 17 | ||
| 30 | #define SO_RCVLOWAT 18 | ||
| 31 | #define SO_SNDLOWAT 19 | ||
| 32 | #define SO_RCVTIMEO 20 | ||
| 33 | #define SO_SNDTIMEO 21 | ||
| 34 | |||
| 35 | /* Security levels - as per NRL IPv6 - don't actually do anything */ | ||
| 36 | #define SO_SECURITY_AUTHENTICATION 22 | ||
| 37 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 23 | ||
| 38 | #define SO_SECURITY_ENCRYPTION_NETWORK 24 | ||
| 39 | |||
| 40 | #define SO_BINDTODEVICE 25 | ||
| 41 | |||
| 42 | /* Socket filtering */ | ||
| 43 | #define SO_ATTACH_FILTER 26 | ||
| 44 | #define SO_DETACH_FILTER 27 | ||
| 45 | |||
| 46 | #define SO_PEERNAME 28 | ||
| 47 | #define SO_TIMESTAMP 29 | ||
| 48 | #define SCM_TIMESTAMP SO_TIMESTAMP | ||
| 49 | |||
| 50 | #define SO_ACCEPTCONN 30 | ||
| 51 | |||
| 52 | #define SO_PEERSEC 31 | ||
| 53 | #define SO_PASSSEC 34 | ||
| 54 | #define SO_TIMESTAMPNS 35 | ||
| 55 | #define SCM_TIMESTAMPNS SO_TIMESTAMPNS | ||
| 56 | |||
| 57 | #define SO_MARK 36 | ||
| 58 | |||
| 59 | #endif /* _ASM_SOCKET_H */ | ||
| 60 | |||
| 61 | |||
diff --git a/include/asm-cris/sockios.h b/include/asm-cris/sockios.h deleted file mode 100644 index cfe7bfecf599..000000000000 --- a/include/asm-cris/sockios.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | #ifndef __ARCH_CRIS_SOCKIOS__ | ||
| 2 | #define __ARCH_CRIS_SOCKIOS__ | ||
| 3 | |||
| 4 | /* Socket-level I/O control calls. */ | ||
| 5 | #define FIOSETOWN 0x8901 | ||
| 6 | #define SIOCSPGRP 0x8902 | ||
| 7 | #define FIOGETOWN 0x8903 | ||
| 8 | #define SIOCGPGRP 0x8904 | ||
| 9 | #define SIOCATMARK 0x8905 | ||
| 10 | #define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ | ||
| 11 | #define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/include/asm-cris/spinlock.h b/include/asm-cris/spinlock.h deleted file mode 100644 index 2e8ba8afc7af..000000000000 --- a/include/asm-cris/spinlock.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm/arch/spinlock.h> | ||
diff --git a/include/asm-cris/stat.h b/include/asm-cris/stat.h deleted file mode 100644 index 9e558cc3c43b..000000000000 --- a/include/asm-cris/stat.h +++ /dev/null | |||
| @@ -1,81 +0,0 @@ | |||
| 1 | #ifndef _CRIS_STAT_H | ||
| 2 | #define _CRIS_STAT_H | ||
| 3 | |||
| 4 | /* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in | ||
| 5 | the kernel if necessary. */ | ||
| 6 | |||
| 7 | struct __old_kernel_stat { | ||
| 8 | unsigned short st_dev; | ||
| 9 | unsigned short st_ino; | ||
| 10 | unsigned short st_mode; | ||
| 11 | unsigned short st_nlink; | ||
| 12 | unsigned short st_uid; | ||
| 13 | unsigned short st_gid; | ||
| 14 | unsigned short st_rdev; | ||
| 15 | unsigned long st_size; | ||
| 16 | unsigned long st_atime; | ||
| 17 | unsigned long st_mtime; | ||
| 18 | unsigned long st_ctime; | ||
| 19 | }; | ||
| 20 | |||
| 21 | #define STAT_HAVE_NSEC 1 | ||
| 22 | |||
| 23 | struct stat { | ||
| 24 | unsigned long st_dev; | ||
| 25 | unsigned long st_ino; | ||
| 26 | unsigned short st_mode; | ||
| 27 | unsigned short st_nlink; | ||
| 28 | unsigned short st_uid; | ||
| 29 | unsigned short st_gid; | ||
| 30 | unsigned long st_rdev; | ||
| 31 | unsigned long st_size; | ||
| 32 | unsigned long st_blksize; | ||
| 33 | unsigned long st_blocks; | ||
| 34 | unsigned long st_atime; | ||
| 35 | unsigned long st_atime_nsec; | ||
| 36 | unsigned long st_mtime; | ||
| 37 | unsigned long st_mtime_nsec; | ||
| 38 | unsigned long st_ctime; | ||
| 39 | unsigned long st_ctime_nsec; | ||
| 40 | unsigned long __unused4; | ||
| 41 | unsigned long __unused5; | ||
| 42 | }; | ||
| 43 | |||
| 44 | /* This matches struct stat64 in glibc2.1, hence the absolutely | ||
| 45 | * insane amounts of padding around dev_t's. | ||
| 46 | */ | ||
| 47 | struct stat64 { | ||
| 48 | unsigned long long st_dev; | ||
| 49 | unsigned char __pad0[4]; | ||
| 50 | |||
| 51 | #define STAT64_HAS_BROKEN_ST_INO 1 | ||
| 52 | unsigned long __st_ino; | ||
| 53 | |||
| 54 | unsigned int st_mode; | ||
| 55 | unsigned int st_nlink; | ||
| 56 | |||
| 57 | unsigned long st_uid; | ||
| 58 | unsigned long st_gid; | ||
| 59 | |||
| 60 | unsigned long long st_rdev; | ||
| 61 | unsigned char __pad3[4]; | ||
| 62 | |||
| 63 | long long st_size; | ||
| 64 | unsigned long st_blksize; | ||
| 65 | |||
| 66 | unsigned long st_blocks; /* Number 512-byte blocks allocated. */ | ||
| 67 | unsigned long __pad4; /* future possible st_blocks high bits */ | ||
| 68 | |||
| 69 | unsigned long st_atime; | ||
| 70 | unsigned long st_atime_nsec; | ||
| 71 | |||
| 72 | unsigned long st_mtime; | ||
| 73 | unsigned long st_mtime_nsec; | ||
| 74 | |||
| 75 | unsigned long st_ctime; | ||
| 76 | unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ | ||
| 77 | |||
| 78 | unsigned long long st_ino; | ||
| 79 | }; | ||
| 80 | |||
| 81 | #endif | ||
diff --git a/include/asm-cris/statfs.h b/include/asm-cris/statfs.h deleted file mode 100644 index fdaf921844bc..000000000000 --- a/include/asm-cris/statfs.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _CRIS_STATFS_H | ||
| 2 | #define _CRIS_STATFS_H | ||
| 3 | |||
| 4 | #include <asm-generic/statfs.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/string.h b/include/asm-cris/string.h deleted file mode 100644 index 691190e99a27..000000000000 --- a/include/asm-cris/string.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_STRING_H | ||
| 2 | #define _ASM_CRIS_STRING_H | ||
| 3 | |||
| 4 | /* the optimized memcpy is in arch/cris/lib/string.c */ | ||
| 5 | |||
| 6 | #define __HAVE_ARCH_MEMCPY | ||
| 7 | extern void *memcpy(void *, const void *, size_t); | ||
| 8 | |||
| 9 | /* New and improved. In arch/cris/lib/memset.c */ | ||
| 10 | |||
| 11 | #define __HAVE_ARCH_MEMSET | ||
| 12 | extern void *memset(void *, int, size_t); | ||
| 13 | |||
| 14 | #endif | ||
diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h deleted file mode 100644 index d87c24df2b38..000000000000 --- a/include/asm-cris/sync_serial.h +++ /dev/null | |||
| @@ -1,107 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * ioctl defines for synchronous serial port driver | ||
| 3 | * | ||
| 4 | * Copyright (c) 2001-2003 Axis Communications AB | ||
| 5 | * | ||
| 6 | * Author: Mikael Starvik | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef SYNC_SERIAL_H | ||
| 11 | #define SYNC_SERIAL_H | ||
| 12 | |||
| 13 | #include <linux/ioctl.h> | ||
| 14 | |||
| 15 | #define SSP_SPEED _IOR('S', 0, unsigned int) | ||
| 16 | #define SSP_MODE _IOR('S', 1, unsigned int) | ||
| 17 | #define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) | ||
| 18 | #define SSP_IPOLARITY _IOR('S', 3, unsigned int) | ||
| 19 | #define SSP_OPOLARITY _IOR('S', 4, unsigned int) | ||
| 20 | #define SSP_SPI _IOR('S', 5, unsigned int) | ||
| 21 | #define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) | ||
| 22 | |||
| 23 | /* Values for SSP_SPEED */ | ||
| 24 | #define SSP150 0 | ||
| 25 | #define SSP300 1 | ||
| 26 | #define SSP600 2 | ||
| 27 | #define SSP1200 3 | ||
| 28 | #define SSP2400 4 | ||
| 29 | #define SSP4800 5 | ||
| 30 | #define SSP9600 6 | ||
| 31 | #define SSP19200 7 | ||
| 32 | #define SSP28800 8 | ||
| 33 | #define SSP57600 9 | ||
| 34 | #define SSP115200 10 | ||
| 35 | #define SSP230400 11 | ||
| 36 | #define SSP460800 12 | ||
| 37 | #define SSP921600 13 | ||
| 38 | #define SSP3125000 14 | ||
| 39 | #define CODEC 15 | ||
| 40 | |||
| 41 | #define FREQ_4MHz 0 | ||
| 42 | #define FREQ_2MHz 1 | ||
| 43 | #define FREQ_1MHz 2 | ||
| 44 | #define FREQ_512kHz 3 | ||
| 45 | #define FREQ_256kHz 4 | ||
| 46 | #define FREQ_128kHz 5 | ||
| 47 | #define FREQ_64kHz 6 | ||
| 48 | #define FREQ_32kHz 7 | ||
| 49 | |||
| 50 | /* Used by application to set CODEC divider, word rate and frame rate */ | ||
| 51 | #define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28)) | ||
| 52 | |||
| 53 | /* Used by driver to extract speed */ | ||
| 54 | #define GET_SPEED(x) (x & 0xff) | ||
| 55 | #define GET_FREQ(x) ((x & 0xff00) >> 8) | ||
| 56 | #define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) | ||
| 57 | #define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) | ||
| 58 | |||
| 59 | /* Values for SSP_MODE */ | ||
| 60 | #define MASTER_OUTPUT 0 | ||
| 61 | #define SLAVE_OUTPUT 1 | ||
| 62 | #define MASTER_INPUT 2 | ||
| 63 | #define SLAVE_INPUT 3 | ||
| 64 | #define MASTER_BIDIR 4 | ||
| 65 | #define SLAVE_BIDIR 5 | ||
| 66 | |||
| 67 | /* Values for SSP_FRAME_SYNC */ | ||
| 68 | #define NORMAL_SYNC 1 | ||
| 69 | #define EARLY_SYNC 2 | ||
| 70 | #define SECOND_WORD_SYNC 0x40000 | ||
| 71 | |||
| 72 | #define BIT_SYNC 4 | ||
| 73 | #define WORD_SYNC 8 | ||
| 74 | #define EXTENDED_SYNC 0x10 | ||
| 75 | |||
| 76 | #define SYNC_OFF 0x20 | ||
| 77 | #define SYNC_ON 0x40 | ||
| 78 | #define WORD_SIZE_8 0x80 | ||
| 79 | #define WORD_SIZE_12 0x100 | ||
| 80 | #define WORD_SIZE_16 0x200 | ||
| 81 | #define WORD_SIZE_24 0x400 | ||
| 82 | #define WORD_SIZE_32 0x800 | ||
| 83 | #define BIT_ORDER_LSB 0x1000 | ||
| 84 | #define BIT_ORDER_MSB 0x2000 | ||
| 85 | #define FLOW_CONTROL_ENABLE 0x4000 | ||
| 86 | #define FLOW_CONTROL_DISABLE 0x8000 | ||
| 87 | #define CLOCK_GATED 0x10000 | ||
| 88 | #define CLOCK_NOT_GATED 0x20000 | ||
| 89 | |||
| 90 | /* Values for SSP_IPOLARITY and SSP_OPOLARITY */ | ||
| 91 | #define CLOCK_NORMAL 1 | ||
| 92 | #define CLOCK_INVERT 2 | ||
| 93 | #define CLOCK_INEGEDGE CLOCK_NORMAL | ||
| 94 | #define CLOCK_IPOSEDGE CLOCK_INVERT | ||
| 95 | #define FRAME_NORMAL 4 | ||
| 96 | #define FRAME_INVERT 8 | ||
| 97 | #define STATUS_NORMAL 0x10 | ||
| 98 | #define STATUS_INVERT 0x20 | ||
| 99 | |||
| 100 | /* Values for SSP_SPI */ | ||
| 101 | #define SPI_MASTER 0 | ||
| 102 | #define SPI_SLAVE 1 | ||
| 103 | |||
| 104 | /* Values for SSP_INBUFCHUNK */ | ||
| 105 | /* plain integer with the size of DMA chunks */ | ||
| 106 | |||
| 107 | #endif | ||
diff --git a/include/asm-cris/system.h b/include/asm-cris/system.h deleted file mode 100644 index 5bcfe5a10907..000000000000 --- a/include/asm-cris/system.h +++ /dev/null | |||
| @@ -1,88 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_SYSTEM_H | ||
| 2 | #define __ASM_CRIS_SYSTEM_H | ||
| 3 | |||
| 4 | #include <asm/arch/system.h> | ||
| 5 | |||
| 6 | /* the switch_to macro calls resume, an asm function in entry.S which does the actual | ||
| 7 | * task switching. | ||
| 8 | */ | ||
| 9 | |||
| 10 | extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int); | ||
| 11 | #define switch_to(prev,next,last) last = resume(prev,next, \ | ||
| 12 | (int)&((struct task_struct *)0)->thread) | ||
| 13 | |||
| 14 | #define barrier() __asm__ __volatile__("": : :"memory") | ||
| 15 | #define mb() barrier() | ||
| 16 | #define rmb() mb() | ||
| 17 | #define wmb() mb() | ||
| 18 | #define read_barrier_depends() do { } while(0) | ||
| 19 | #define set_mb(var, value) do { var = value; mb(); } while (0) | ||
| 20 | |||
| 21 | #ifdef CONFIG_SMP | ||
| 22 | #define smp_mb() mb() | ||
| 23 | #define smp_rmb() rmb() | ||
| 24 | #define smp_wmb() wmb() | ||
| 25 | #define smp_read_barrier_depends() read_barrier_depends() | ||
| 26 | #else | ||
| 27 | #define smp_mb() barrier() | ||
| 28 | #define smp_rmb() barrier() | ||
| 29 | #define smp_wmb() barrier() | ||
| 30 | #define smp_read_barrier_depends() do { } while(0) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #define iret() | ||
| 34 | |||
| 35 | /* | ||
| 36 | * disable hlt during certain critical i/o operations | ||
| 37 | */ | ||
| 38 | #define HAVE_DISABLE_HLT | ||
| 39 | void disable_hlt(void); | ||
| 40 | void enable_hlt(void); | ||
| 41 | |||
| 42 | static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) | ||
| 43 | { | ||
| 44 | /* since Etrax doesn't have any atomic xchg instructions, we need to disable | ||
| 45 | irq's (if enabled) and do it with move.d's */ | ||
| 46 | unsigned long flags,temp; | ||
| 47 | local_irq_save(flags); /* save flags, including irq enable bit and shut off irqs */ | ||
| 48 | switch (size) { | ||
| 49 | case 1: | ||
| 50 | *((unsigned char *)&temp) = x; | ||
| 51 | x = *(unsigned char *)ptr; | ||
| 52 | *(unsigned char *)ptr = *((unsigned char *)&temp); | ||
| 53 | break; | ||
| 54 | case 2: | ||
| 55 | *((unsigned short *)&temp) = x; | ||
| 56 | x = *(unsigned short *)ptr; | ||
| 57 | *(unsigned short *)ptr = *((unsigned short *)&temp); | ||
| 58 | break; | ||
| 59 | case 4: | ||
| 60 | temp = x; | ||
| 61 | x = *(unsigned long *)ptr; | ||
| 62 | *(unsigned long *)ptr = temp; | ||
| 63 | break; | ||
| 64 | } | ||
| 65 | local_irq_restore(flags); /* restore irq enable bit */ | ||
| 66 | return x; | ||
| 67 | } | ||
| 68 | |||
| 69 | #include <asm-generic/cmpxchg-local.h> | ||
| 70 | |||
| 71 | /* | ||
| 72 | * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make | ||
| 73 | * them available. | ||
| 74 | */ | ||
| 75 | #define cmpxchg_local(ptr, o, n) \ | ||
| 76 | ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ | ||
| 77 | (unsigned long)(n), sizeof(*(ptr)))) | ||
| 78 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | ||
| 79 | |||
| 80 | #ifndef CONFIG_SMP | ||
| 81 | #include <asm-generic/cmpxchg.h> | ||
| 82 | #endif | ||
| 83 | |||
| 84 | #define arch_align_stack(x) (x) | ||
| 85 | |||
| 86 | void default_idle(void); | ||
| 87 | |||
| 88 | #endif | ||
diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h deleted file mode 100644 index 66e1a7492a0c..000000000000 --- a/include/asm-cris/termbits.h +++ /dev/null | |||
| @@ -1,234 +0,0 @@ | |||
| 1 | /* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ | ||
| 2 | |||
| 3 | #ifndef __ARCH_ETRAX100_TERMBITS_H__ | ||
| 4 | #define __ARCH_ETRAX100_TERMBITS_H__ | ||
| 5 | |||
| 6 | #include <linux/posix_types.h> | ||
| 7 | |||
| 8 | typedef unsigned char cc_t; | ||
| 9 | typedef unsigned int speed_t; | ||
| 10 | typedef unsigned int tcflag_t; | ||
| 11 | |||
| 12 | #define NCCS 19 | ||
| 13 | struct termios { | ||
| 14 | tcflag_t c_iflag; /* input mode flags */ | ||
| 15 | tcflag_t c_oflag; /* output mode flags */ | ||
| 16 | tcflag_t c_cflag; /* control mode flags */ | ||
| 17 | tcflag_t c_lflag; /* local mode flags */ | ||
| 18 | cc_t c_line; /* line discipline */ | ||
| 19 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | struct termios2 { | ||
| 23 | tcflag_t c_iflag; /* input mode flags */ | ||
| 24 | tcflag_t c_oflag; /* output mode flags */ | ||
| 25 | tcflag_t c_cflag; /* control mode flags */ | ||
| 26 | tcflag_t c_lflag; /* local mode flags */ | ||
| 27 | cc_t c_line; /* line discipline */ | ||
| 28 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 29 | speed_t c_ispeed; /* input speed */ | ||
| 30 | speed_t c_ospeed; /* output speed */ | ||
| 31 | }; | ||
| 32 | |||
| 33 | struct ktermios { | ||
| 34 | tcflag_t c_iflag; /* input mode flags */ | ||
| 35 | tcflag_t c_oflag; /* output mode flags */ | ||
| 36 | tcflag_t c_cflag; /* control mode flags */ | ||
| 37 | tcflag_t c_lflag; /* local mode flags */ | ||
| 38 | cc_t c_line; /* line discipline */ | ||
| 39 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 40 | speed_t c_ispeed; /* input speed */ | ||
| 41 | speed_t c_ospeed; /* output speed */ | ||
| 42 | }; | ||
| 43 | |||
| 44 | /* c_cc characters */ | ||
| 45 | #define VINTR 0 | ||
| 46 | #define VQUIT 1 | ||
| 47 | #define VERASE 2 | ||
| 48 | #define VKILL 3 | ||
| 49 | #define VEOF 4 | ||
| 50 | #define VTIME 5 | ||
| 51 | #define VMIN 6 | ||
| 52 | #define VSWTC 7 | ||
| 53 | #define VSTART 8 | ||
| 54 | #define VSTOP 9 | ||
| 55 | #define VSUSP 10 | ||
| 56 | #define VEOL 11 | ||
| 57 | #define VREPRINT 12 | ||
| 58 | #define VDISCARD 13 | ||
| 59 | #define VWERASE 14 | ||
| 60 | #define VLNEXT 15 | ||
| 61 | #define VEOL2 16 | ||
| 62 | |||
| 63 | /* c_iflag bits */ | ||
| 64 | #define IGNBRK 0000001 | ||
| 65 | #define BRKINT 0000002 | ||
| 66 | #define IGNPAR 0000004 | ||
| 67 | #define PARMRK 0000010 | ||
| 68 | #define INPCK 0000020 | ||
| 69 | #define ISTRIP 0000040 | ||
| 70 | #define INLCR 0000100 | ||
| 71 | #define IGNCR 0000200 | ||
| 72 | #define ICRNL 0000400 | ||
| 73 | #define IUCLC 0001000 | ||
| 74 | #define IXON 0002000 | ||
| 75 | #define IXANY 0004000 | ||
| 76 | #define IXOFF 0010000 | ||
| 77 | #define IMAXBEL 0020000 | ||
| 78 | #define IUTF8 0040000 | ||
| 79 | |||
| 80 | /* c_oflag bits */ | ||
| 81 | #define OPOST 0000001 | ||
| 82 | #define OLCUC 0000002 | ||
| 83 | #define ONLCR 0000004 | ||
| 84 | #define OCRNL 0000010 | ||
| 85 | #define ONOCR 0000020 | ||
| 86 | #define ONLRET 0000040 | ||
| 87 | #define OFILL 0000100 | ||
| 88 | #define OFDEL 0000200 | ||
| 89 | #define NLDLY 0000400 | ||
| 90 | #define NL0 0000000 | ||
| 91 | #define NL1 0000400 | ||
| 92 | #define CRDLY 0003000 | ||
| 93 | #define CR0 0000000 | ||
| 94 | #define CR1 0001000 | ||
| 95 | #define CR2 0002000 | ||
| 96 | #define CR3 0003000 | ||
| 97 | #define TABDLY 0014000 | ||
| 98 | #define TAB0 0000000 | ||
| 99 | #define TAB1 0004000 | ||
| 100 | #define TAB2 0010000 | ||
| 101 | #define TAB3 0014000 | ||
| 102 | #define XTABS 0014000 | ||
| 103 | #define BSDLY 0020000 | ||
| 104 | #define BS0 0000000 | ||
| 105 | #define BS1 0020000 | ||
| 106 | #define VTDLY 0040000 | ||
| 107 | #define VT0 0000000 | ||
| 108 | #define VT1 0040000 | ||
| 109 | #define FFDLY 0100000 | ||
| 110 | #define FF0 0000000 | ||
| 111 | #define FF1 0100000 | ||
| 112 | |||
| 113 | /* c_cflag bit meaning */ | ||
| 114 | /* | ||
| 115 | * 3 2 1 | ||
| 116 | * 10 987 654 321 098 765 432 109 876 543 210 | ||
| 117 | * | | ||| CBAUD | ||
| 118 | * obaud | ||
| 119 | * | ||
| 120 | * ||CSIZE | ||
| 121 | * | ||
| 122 | * |CSTOP | ||
| 123 | * |CREAD | ||
| 124 | * |CPARENB | ||
| 125 | * | ||
| 126 | * |CPARODD | ||
| 127 | * |HUPCL | ||
| 128 | * |CLOCAL | ||
| 129 | * |CBAUDEX | ||
| 130 | * 10 987 654 321 098 765 432 109 876 543 210 | ||
| 131 | * | || || CIBAUD, IBSHIFT=16 | ||
| 132 | * ibaud | ||
| 133 | * |CMSPAR | ||
| 134 | * | CRTSCTS | ||
| 135 | * x x xxx xxx x x xx Free bits | ||
| 136 | */ | ||
| 137 | |||
| 138 | #define CBAUD 0010017 | ||
| 139 | #define B0 0000000 /* hang up */ | ||
| 140 | #define B50 0000001 | ||
| 141 | #define B75 0000002 | ||
| 142 | #define B110 0000003 | ||
| 143 | #define B134 0000004 | ||
| 144 | #define B150 0000005 | ||
| 145 | #define B200 0000006 | ||
| 146 | #define B300 0000007 | ||
| 147 | #define B600 0000010 | ||
| 148 | #define B1200 0000011 | ||
| 149 | #define B1800 0000012 | ||
| 150 | #define B2400 0000013 | ||
| 151 | #define B4800 0000014 | ||
| 152 | #define B9600 0000015 | ||
| 153 | #define B19200 0000016 | ||
| 154 | #define B38400 0000017 | ||
| 155 | #define EXTA B19200 | ||
| 156 | #define EXTB B38400 | ||
| 157 | #define CSIZE 0000060 | ||
| 158 | #define CS5 0000000 | ||
| 159 | #define CS6 0000020 | ||
| 160 | #define CS7 0000040 | ||
| 161 | #define CS8 0000060 | ||
| 162 | #define CSTOPB 0000100 | ||
| 163 | #define CREAD 0000200 | ||
| 164 | #define PARENB 0000400 | ||
| 165 | #define PARODD 0001000 | ||
| 166 | #define HUPCL 0002000 | ||
| 167 | #define CLOCAL 0004000 | ||
| 168 | #define CBAUDEX 0010000 | ||
| 169 | #define BOTHER 0010000 | ||
| 170 | #define B57600 0010001 | ||
| 171 | #define B115200 0010002 | ||
| 172 | #define B230400 0010003 | ||
| 173 | #define B460800 0010004 | ||
| 174 | |||
| 175 | /* Unsupported rates, but needed to avoid compile error. */ | ||
| 176 | #define B500000 0010005 | ||
| 177 | #define B576000 0010006 | ||
| 178 | #define B1000000 0010010 | ||
| 179 | #define B1152000 0010011 | ||
| 180 | #define B1500000 0010012 | ||
| 181 | #define B2000000 0010013 | ||
| 182 | #define B2500000 0010014 | ||
| 183 | #define B3000000 0010015 | ||
| 184 | #define B3500000 0010016 | ||
| 185 | #define B4000000 0010017 | ||
| 186 | |||
| 187 | /* etrax supports these additional three baud rates */ | ||
| 188 | #define B921600 0010005 | ||
| 189 | #define B1843200 0010006 | ||
| 190 | #define B6250000 0010007 | ||
| 191 | /* ETRAX FS supports this as well */ | ||
| 192 | #define B12500000 0010010 | ||
| 193 | #define CIBAUD 002003600000 /* input baud rate (used in v32) */ | ||
| 194 | /* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX | ||
| 195 | * shifted left IBSHIFT bits. | ||
| 196 | */ | ||
| 197 | #define IBSHIFT 16 | ||
| 198 | #define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ | ||
| 199 | #define CRTSCTS 020000000000 /* flow control */ | ||
| 200 | |||
| 201 | /* c_lflag bits */ | ||
| 202 | #define ISIG 0000001 | ||
| 203 | #define ICANON 0000002 | ||
| 204 | #define XCASE 0000004 | ||
| 205 | #define ECHO 0000010 | ||
| 206 | #define ECHOE 0000020 | ||
| 207 | #define ECHOK 0000040 | ||
| 208 | #define ECHONL 0000100 | ||
| 209 | #define NOFLSH 0000200 | ||
| 210 | #define TOSTOP 0000400 | ||
| 211 | #define ECHOCTL 0001000 | ||
| 212 | #define ECHOPRT 0002000 | ||
| 213 | #define ECHOKE 0004000 | ||
| 214 | #define FLUSHO 0010000 | ||
| 215 | #define PENDIN 0040000 | ||
| 216 | #define IEXTEN 0100000 | ||
| 217 | |||
| 218 | /* tcflow() and TCXONC use these */ | ||
| 219 | #define TCOOFF 0 | ||
| 220 | #define TCOON 1 | ||
| 221 | #define TCIOFF 2 | ||
| 222 | #define TCION 3 | ||
| 223 | |||
| 224 | /* tcflush() and TCFLSH use these */ | ||
| 225 | #define TCIFLUSH 0 | ||
| 226 | #define TCOFLUSH 1 | ||
| 227 | #define TCIOFLUSH 2 | ||
| 228 | |||
| 229 | /* tcsetattr uses these */ | ||
| 230 | #define TCSANOW 0 | ||
| 231 | #define TCSADRAIN 1 | ||
| 232 | #define TCSAFLUSH 2 | ||
| 233 | |||
| 234 | #endif | ||
diff --git a/include/asm-cris/termios.h b/include/asm-cris/termios.h deleted file mode 100644 index b0124e6c2e41..000000000000 --- a/include/asm-cris/termios.h +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | #ifndef _CRIS_TERMIOS_H | ||
| 2 | #define _CRIS_TERMIOS_H | ||
| 3 | |||
| 4 | #include <asm/termbits.h> | ||
| 5 | #include <asm/ioctls.h> | ||
| 6 | #include <asm/rs485.h> | ||
| 7 | |||
| 8 | struct winsize { | ||
| 9 | unsigned short ws_row; | ||
| 10 | unsigned short ws_col; | ||
| 11 | unsigned short ws_xpixel; | ||
| 12 | unsigned short ws_ypixel; | ||
| 13 | }; | ||
| 14 | |||
| 15 | #define NCC 8 | ||
| 16 | struct termio { | ||
| 17 | unsigned short c_iflag; /* input mode flags */ | ||
| 18 | unsigned short c_oflag; /* output mode flags */ | ||
| 19 | unsigned short c_cflag; /* control mode flags */ | ||
| 20 | unsigned short c_lflag; /* local mode flags */ | ||
| 21 | unsigned char c_line; /* line discipline */ | ||
| 22 | unsigned char c_cc[NCC]; /* control characters */ | ||
| 23 | }; | ||
| 24 | |||
| 25 | /* modem lines */ | ||
| 26 | #define TIOCM_LE 0x001 | ||
| 27 | #define TIOCM_DTR 0x002 | ||
| 28 | #define TIOCM_RTS 0x004 | ||
| 29 | #define TIOCM_ST 0x008 | ||
| 30 | #define TIOCM_SR 0x010 | ||
| 31 | #define TIOCM_CTS 0x020 | ||
| 32 | #define TIOCM_CAR 0x040 | ||
| 33 | #define TIOCM_RNG 0x080 | ||
| 34 | #define TIOCM_DSR 0x100 | ||
| 35 | #define TIOCM_CD TIOCM_CAR | ||
| 36 | #define TIOCM_RI TIOCM_RNG | ||
| 37 | #define TIOCM_OUT1 0x2000 | ||
| 38 | #define TIOCM_OUT2 0x4000 | ||
| 39 | #define TIOCM_LOOP 0x8000 | ||
| 40 | |||
| 41 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ | ||
| 42 | |||
| 43 | #ifdef __KERNEL__ | ||
| 44 | |||
| 45 | /* intr=^C quit=^\ erase=del kill=^U | ||
| 46 | eof=^D vtime=\0 vmin=\1 sxtc=\0 | ||
| 47 | start=^Q stop=^S susp=^Z eol=\0 | ||
| 48 | reprint=^R discard=^U werase=^W lnext=^V | ||
| 49 | eol2=\0 | ||
| 50 | */ | ||
| 51 | #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Translate a "termio" structure into a "termios". Ugh. | ||
| 55 | */ | ||
| 56 | #define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ | ||
| 57 | unsigned short __tmp; \ | ||
| 58 | get_user(__tmp,&(termio)->x); \ | ||
| 59 | *(unsigned short *) &(termios)->x = __tmp; \ | ||
| 60 | } | ||
| 61 | |||
| 62 | #define user_termio_to_kernel_termios(termios, termio) \ | ||
| 63 | ({ \ | ||
| 64 | SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ | ||
| 65 | SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ | ||
| 66 | SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ | ||
| 67 | SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ | ||
| 68 | copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ | ||
| 69 | }) | ||
| 70 | |||
| 71 | /* | ||
| 72 | * Translate a "termios" structure into a "termio". Ugh. | ||
| 73 | */ | ||
| 74 | #define kernel_termios_to_user_termio(termio, termios) \ | ||
| 75 | ({ \ | ||
| 76 | put_user((termios)->c_iflag, &(termio)->c_iflag); \ | ||
| 77 | put_user((termios)->c_oflag, &(termio)->c_oflag); \ | ||
| 78 | put_user((termios)->c_cflag, &(termio)->c_cflag); \ | ||
| 79 | put_user((termios)->c_lflag, &(termio)->c_lflag); \ | ||
| 80 | put_user((termios)->c_line, &(termio)->c_line); \ | ||
| 81 | copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ | ||
| 82 | }) | ||
| 83 | |||
| 84 | #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) | ||
| 85 | #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) | ||
| 86 | #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) | ||
| 87 | #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) | ||
| 88 | |||
| 89 | #endif /* __KERNEL__ */ | ||
| 90 | |||
| 91 | #endif /* _CRIS_TERMIOS_H */ | ||
diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h deleted file mode 100644 index cee97f14af3b..000000000000 --- a/include/asm-cris/thread_info.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /* thread_info.h: CRIS low-level thread information | ||
| 2 | * | ||
| 3 | * Copyright (C) 2002 David Howells (dhowells@redhat.com) | ||
| 4 | * - Incorporating suggestions made by Linus Torvalds and Dave Miller | ||
| 5 | * | ||
| 6 | * CRIS port by Axis Communications | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _ASM_THREAD_INFO_H | ||
| 10 | #define _ASM_THREAD_INFO_H | ||
| 11 | |||
| 12 | #ifdef __KERNEL__ | ||
| 13 | |||
| 14 | #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR | ||
| 15 | |||
| 16 | #ifndef __ASSEMBLY__ | ||
| 17 | #include <asm/types.h> | ||
| 18 | #include <asm/processor.h> | ||
| 19 | #include <asm/arch/thread_info.h> | ||
| 20 | #include <asm/segment.h> | ||
| 21 | #endif | ||
| 22 | |||
| 23 | |||
| 24 | /* | ||
| 25 | * low level task data that entry.S needs immediate access to | ||
| 26 | * - this struct should fit entirely inside of one cache line | ||
| 27 | * - this struct shares the supervisor stack pages | ||
| 28 | * - if the contents of this structure are changed, the assembly constants must also be changed | ||
| 29 | */ | ||
| 30 | #ifndef __ASSEMBLY__ | ||
| 31 | struct thread_info { | ||
| 32 | struct task_struct *task; /* main task structure */ | ||
| 33 | struct exec_domain *exec_domain; /* execution domain */ | ||
| 34 | unsigned long flags; /* low level flags */ | ||
| 35 | __u32 cpu; /* current CPU */ | ||
| 36 | int preempt_count; /* 0 => preemptable, <0 => BUG */ | ||
| 37 | __u32 tls; /* TLS for this thread */ | ||
| 38 | |||
| 39 | mm_segment_t addr_limit; /* thread address space: | ||
| 40 | 0-0xBFFFFFFF for user-thead | ||
| 41 | 0-0xFFFFFFFF for kernel-thread | ||
| 42 | */ | ||
| 43 | struct restart_block restart_block; | ||
| 44 | __u8 supervisor_stack[0]; | ||
| 45 | }; | ||
| 46 | |||
| 47 | #endif | ||
| 48 | |||
| 49 | #define PREEMPT_ACTIVE 0x10000000 | ||
| 50 | |||
| 51 | /* | ||
| 52 | * macros/functions for gaining access to the thread information structure | ||
| 53 | * | ||
| 54 | * preempt_count needs to be 1 initially, until the scheduler is functional. | ||
| 55 | */ | ||
| 56 | #ifndef __ASSEMBLY__ | ||
| 57 | #define INIT_THREAD_INFO(tsk) \ | ||
| 58 | { \ | ||
| 59 | .task = &tsk, \ | ||
| 60 | .exec_domain = &default_exec_domain, \ | ||
| 61 | .flags = 0, \ | ||
| 62 | .cpu = 0, \ | ||
| 63 | .preempt_count = 1, \ | ||
| 64 | .addr_limit = KERNEL_DS, \ | ||
| 65 | .restart_block = { \ | ||
| 66 | .fn = do_no_restart_syscall, \ | ||
| 67 | }, \ | ||
| 68 | } | ||
| 69 | |||
| 70 | #define init_thread_info (init_thread_union.thread_info) | ||
| 71 | |||
| 72 | /* thread information allocation */ | ||
| 73 | #define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) | ||
| 74 | #define free_thread_info(ti) free_pages((unsigned long) (ti), 1) | ||
| 75 | |||
| 76 | #endif /* !__ASSEMBLY__ */ | ||
| 77 | |||
| 78 | /* | ||
| 79 | * thread information flags | ||
| 80 | * - these are process state flags that various assembly files may need to access | ||
| 81 | * - pending work-to-be-done flags are in LSW | ||
| 82 | * - other flags in MSW | ||
| 83 | */ | ||
| 84 | #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ | ||
| 85 | #define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ | ||
| 86 | #define TIF_SIGPENDING 2 /* signal pending */ | ||
| 87 | #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ | ||
| 88 | #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ | ||
| 89 | #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ | ||
| 90 | #define TIF_MEMDIE 17 | ||
| 91 | #define TIF_FREEZE 18 /* is freezing for suspend */ | ||
| 92 | |||
| 93 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | ||
| 94 | #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) | ||
| 95 | #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) | ||
| 96 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) | ||
| 97 | #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) | ||
| 98 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | ||
| 99 | #define _TIF_FREEZE (1<<TIF_FREEZE) | ||
| 100 | |||
| 101 | #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ | ||
| 102 | #define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */ | ||
| 103 | |||
| 104 | #endif /* __KERNEL__ */ | ||
| 105 | |||
| 106 | #endif /* _ASM_THREAD_INFO_H */ | ||
diff --git a/include/asm-cris/timex.h b/include/asm-cris/timex.h deleted file mode 100644 index b92e0e80fe86..000000000000 --- a/include/asm-cris/timex.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-cris/timex.h | ||
| 3 | * | ||
| 4 | * CRIS architecture timex specifications | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef _ASM_CRIS_TIMEX_H | ||
| 8 | #define _ASM_CRIS_TIMEX_H | ||
| 9 | |||
| 10 | #include <asm/arch/timex.h> | ||
| 11 | |||
| 12 | /* | ||
| 13 | * We don't have a cycle-counter.. but we do not support SMP anyway where this is | ||
| 14 | * used so it does not matter. | ||
| 15 | */ | ||
| 16 | |||
| 17 | typedef unsigned long long cycles_t; | ||
| 18 | |||
| 19 | static inline cycles_t get_cycles(void) | ||
| 20 | { | ||
| 21 | return 0; | ||
| 22 | } | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/include/asm-cris/tlb.h b/include/asm-cris/tlb.h deleted file mode 100644 index 7724246a2601..000000000000 --- a/include/asm-cris/tlb.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | #ifndef _CRIS_TLB_H | ||
| 2 | #define _CRIS_TLB_H | ||
| 3 | |||
| 4 | #include <linux/pagemap.h> | ||
| 5 | |||
| 6 | #include <asm/arch/tlb.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * cris doesn't need any special per-pte or | ||
| 10 | * per-vma handling.. | ||
| 11 | */ | ||
| 12 | #define tlb_start_vma(tlb, vma) do { } while (0) | ||
| 13 | #define tlb_end_vma(tlb, vma) do { } while (0) | ||
| 14 | #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) | ||
| 15 | |||
| 16 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) | ||
| 17 | #include <asm-generic/tlb.h> | ||
| 18 | |||
| 19 | #endif | ||
diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h deleted file mode 100644 index 20697e7ef4f2..000000000000 --- a/include/asm-cris/tlbflush.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | #ifndef _CRIS_TLBFLUSH_H | ||
| 2 | #define _CRIS_TLBFLUSH_H | ||
| 3 | |||
| 4 | #include <linux/mm.h> | ||
| 5 | #include <asm/processor.h> | ||
| 6 | #include <asm/pgtable.h> | ||
| 7 | #include <asm/pgalloc.h> | ||
| 8 | |||
| 9 | /* | ||
| 10 | * TLB flushing (implemented in arch/cris/mm/tlb.c): | ||
| 11 | * | ||
| 12 | * - flush_tlb() flushes the current mm struct TLBs | ||
| 13 | * - flush_tlb_all() flushes all processes TLBs | ||
| 14 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | ||
| 15 | * - flush_tlb_page(vma, vmaddr) flushes one page | ||
| 16 | * - flush_tlb_range(mm, start, end) flushes a range of pages | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | |||
| 20 | extern void __flush_tlb_all(void); | ||
| 21 | extern void __flush_tlb_mm(struct mm_struct *mm); | ||
| 22 | extern void __flush_tlb_page(struct vm_area_struct *vma, | ||
| 23 | unsigned long addr); | ||
| 24 | |||
| 25 | #ifdef CONFIG_SMP | ||
| 26 | extern void flush_tlb_all(void); | ||
| 27 | extern void flush_tlb_mm(struct mm_struct *mm); | ||
| 28 | extern void flush_tlb_page(struct vm_area_struct *vma, | ||
| 29 | unsigned long addr); | ||
| 30 | #else | ||
| 31 | #define flush_tlb_all __flush_tlb_all | ||
| 32 | #define flush_tlb_mm __flush_tlb_mm | ||
| 33 | #define flush_tlb_page __flush_tlb_page | ||
| 34 | #endif | ||
| 35 | |||
| 36 | static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) | ||
| 37 | { | ||
| 38 | flush_tlb_mm(vma->vm_mm); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void flush_tlb(void) | ||
| 42 | { | ||
| 43 | flush_tlb_mm(current->mm); | ||
| 44 | } | ||
| 45 | |||
| 46 | #define flush_tlb_kernel_range(start, end) flush_tlb_all() | ||
| 47 | |||
| 48 | #endif /* _CRIS_TLBFLUSH_H */ | ||
diff --git a/include/asm-cris/topology.h b/include/asm-cris/topology.h deleted file mode 100644 index 2ac613d32a89..000000000000 --- a/include/asm-cris/topology.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_TOPOLOGY_H | ||
| 2 | #define _ASM_CRIS_TOPOLOGY_H | ||
| 3 | |||
| 4 | #include <asm-generic/topology.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_CRIS_TOPOLOGY_H */ | ||
diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h deleted file mode 100644 index 5790262cbe8a..000000000000 --- a/include/asm-cris/types.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | #ifndef _ETRAX_TYPES_H | ||
| 2 | #define _ETRAX_TYPES_H | ||
| 3 | |||
| 4 | #include <asm-generic/int-ll64.h> | ||
| 5 | |||
| 6 | #ifndef __ASSEMBLY__ | ||
| 7 | |||
| 8 | typedef unsigned short umode_t; | ||
| 9 | |||
| 10 | #endif /* __ASSEMBLY__ */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * These aren't exported outside the kernel to avoid name space clashes | ||
| 14 | */ | ||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #define BITS_PER_LONG 32 | ||
| 18 | |||
| 19 | #ifndef __ASSEMBLY__ | ||
| 20 | |||
| 21 | /* Dma addresses are 32-bits wide, just like our other addresses. */ | ||
| 22 | |||
| 23 | typedef u32 dma_addr_t; | ||
| 24 | typedef u32 dma64_addr_t; | ||
| 25 | |||
| 26 | #endif /* __ASSEMBLY__ */ | ||
| 27 | |||
| 28 | #endif /* __KERNEL__ */ | ||
| 29 | |||
| 30 | #endif | ||
diff --git a/include/asm-cris/uaccess.h b/include/asm-cris/uaccess.h deleted file mode 100644 index ea11eaf0e922..000000000000 --- a/include/asm-cris/uaccess.h +++ /dev/null | |||
| @@ -1,404 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Authors: Bjorn Wesen (bjornw@axis.com) | ||
| 3 | * Hans-Peter Nilsson (hp@axis.com) | ||
| 4 | */ | ||
| 5 | |||
| 6 | /* Asm:s have been tweaked (within the domain of correctness) to give | ||
| 7 | satisfactory results for "gcc version 2.96 20000427 (experimental)". | ||
| 8 | |||
| 9 | Check regularly... | ||
| 10 | |||
| 11 | Register $r9 is chosen for temporaries, being a call-clobbered register | ||
| 12 | first in line to be used (notably for local blocks), not colliding with | ||
| 13 | parameter registers. */ | ||
| 14 | |||
| 15 | #ifndef _CRIS_UACCESS_H | ||
| 16 | #define _CRIS_UACCESS_H | ||
| 17 | |||
| 18 | #ifndef __ASSEMBLY__ | ||
| 19 | #include <linux/sched.h> | ||
| 20 | #include <linux/errno.h> | ||
| 21 | #include <asm/processor.h> | ||
| 22 | #include <asm/page.h> | ||
| 23 | |||
| 24 | #define VERIFY_READ 0 | ||
| 25 | #define VERIFY_WRITE 1 | ||
| 26 | |||
| 27 | /* | ||
| 28 | * The fs value determines whether argument validity checking should be | ||
| 29 | * performed or not. If get_fs() == USER_DS, checking is performed, with | ||
| 30 | * get_fs() == KERNEL_DS, checking is bypassed. | ||
| 31 | * | ||
| 32 | * For historical reasons, these macros are grossly misnamed. | ||
| 33 | */ | ||
| 34 | |||
| 35 | #define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) | ||
| 36 | |||
| 37 | /* addr_limit is the maximum accessible address for the task. we misuse | ||
| 38 | * the KERNEL_DS and USER_DS values to both assign and compare the | ||
| 39 | * addr_limit values through the equally misnamed get/set_fs macros. | ||
| 40 | * (see above) | ||
| 41 | */ | ||
| 42 | |||
| 43 | #define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) | ||
| 44 | #define USER_DS MAKE_MM_SEG(TASK_SIZE) | ||
| 45 | |||
| 46 | #define get_ds() (KERNEL_DS) | ||
| 47 | #define get_fs() (current_thread_info()->addr_limit) | ||
| 48 | #define set_fs(x) (current_thread_info()->addr_limit = (x)) | ||
| 49 | |||
| 50 | #define segment_eq(a,b) ((a).seg == (b).seg) | ||
| 51 | |||
| 52 | #define __kernel_ok (segment_eq(get_fs(), KERNEL_DS)) | ||
| 53 | #define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size))) | ||
| 54 | #define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size))) | ||
| 55 | #define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size)) | ||
| 56 | |||
| 57 | #include <asm/arch/uaccess.h> | ||
| 58 | |||
| 59 | /* | ||
| 60 | * The exception table consists of pairs of addresses: the first is the | ||
| 61 | * address of an instruction that is allowed to fault, and the second is | ||
| 62 | * the address at which the program should continue. No registers are | ||
| 63 | * modified, so it is entirely up to the continuation code to figure out | ||
| 64 | * what to do. | ||
| 65 | * | ||
| 66 | * All the routines below use bits of fixup code that are out of line | ||
| 67 | * with the main instruction path. This means when everything is well, | ||
| 68 | * we don't even have to jump over them. Further, they do not intrude | ||
| 69 | * on our cache or tlb entries. | ||
| 70 | */ | ||
| 71 | |||
| 72 | struct exception_table_entry | ||
| 73 | { | ||
| 74 | unsigned long insn, fixup; | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* | ||
| 78 | * These are the main single-value transfer routines. They automatically | ||
| 79 | * use the right size if we just have the right pointer type. | ||
| 80 | * | ||
| 81 | * This gets kind of ugly. We want to return _two_ values in "get_user()" | ||
| 82 | * and yet we don't want to do any pointers, because that is too much | ||
| 83 | * of a performance impact. Thus we have a few rather ugly macros here, | ||
| 84 | * and hide all the ugliness from the user. | ||
| 85 | * | ||
| 86 | * The "__xxx" versions of the user access functions are versions that | ||
| 87 | * do not verify the address space, that must have been done previously | ||
| 88 | * with a separate "access_ok()" call (this is used when we do multiple | ||
| 89 | * accesses to the same area of user memory). | ||
| 90 | * | ||
| 91 | * As we use the same address space for kernel and user data on | ||
| 92 | * CRIS, we can just do these as direct assignments. (Of course, the | ||
| 93 | * exception handling means that it's no longer "just"...) | ||
| 94 | */ | ||
| 95 | #define get_user(x,ptr) \ | ||
| 96 | __get_user_check((x),(ptr),sizeof(*(ptr))) | ||
| 97 | #define put_user(x,ptr) \ | ||
| 98 | __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) | ||
| 99 | |||
| 100 | #define __get_user(x,ptr) \ | ||
| 101 | __get_user_nocheck((x),(ptr),sizeof(*(ptr))) | ||
| 102 | #define __put_user(x,ptr) \ | ||
| 103 | __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) | ||
| 104 | |||
| 105 | extern long __put_user_bad(void); | ||
| 106 | |||
| 107 | #define __put_user_size(x,ptr,size,retval) \ | ||
| 108 | do { \ | ||
| 109 | retval = 0; \ | ||
| 110 | switch (size) { \ | ||
| 111 | case 1: __put_user_asm(x,ptr,retval,"move.b"); break; \ | ||
| 112 | case 2: __put_user_asm(x,ptr,retval,"move.w"); break; \ | ||
| 113 | case 4: __put_user_asm(x,ptr,retval,"move.d"); break; \ | ||
| 114 | case 8: __put_user_asm_64(x,ptr,retval); break; \ | ||
| 115 | default: __put_user_bad(); \ | ||
| 116 | } \ | ||
| 117 | } while (0) | ||
| 118 | |||
| 119 | #define __get_user_size(x,ptr,size,retval) \ | ||
| 120 | do { \ | ||
| 121 | retval = 0; \ | ||
| 122 | switch (size) { \ | ||
| 123 | case 1: __get_user_asm(x,ptr,retval,"move.b"); break; \ | ||
| 124 | case 2: __get_user_asm(x,ptr,retval,"move.w"); break; \ | ||
| 125 | case 4: __get_user_asm(x,ptr,retval,"move.d"); break; \ | ||
| 126 | case 8: __get_user_asm_64(x,ptr,retval); break; \ | ||
| 127 | default: (x) = __get_user_bad(); \ | ||
| 128 | } \ | ||
| 129 | } while (0) | ||
| 130 | |||
| 131 | #define __put_user_nocheck(x,ptr,size) \ | ||
| 132 | ({ \ | ||
| 133 | long __pu_err; \ | ||
| 134 | __put_user_size((x),(ptr),(size),__pu_err); \ | ||
| 135 | __pu_err; \ | ||
| 136 | }) | ||
| 137 | |||
| 138 | #define __put_user_check(x,ptr,size) \ | ||
| 139 | ({ \ | ||
| 140 | long __pu_err = -EFAULT; \ | ||
| 141 | __typeof__(*(ptr)) *__pu_addr = (ptr); \ | ||
| 142 | if (access_ok(VERIFY_WRITE,__pu_addr,size)) \ | ||
| 143 | __put_user_size((x),__pu_addr,(size),__pu_err); \ | ||
| 144 | __pu_err; \ | ||
| 145 | }) | ||
| 146 | |||
| 147 | struct __large_struct { unsigned long buf[100]; }; | ||
| 148 | #define __m(x) (*(struct __large_struct *)(x)) | ||
| 149 | |||
| 150 | |||
| 151 | |||
| 152 | #define __get_user_nocheck(x,ptr,size) \ | ||
| 153 | ({ \ | ||
| 154 | long __gu_err, __gu_val; \ | ||
| 155 | __get_user_size(__gu_val,(ptr),(size),__gu_err); \ | ||
| 156 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
| 157 | __gu_err; \ | ||
| 158 | }) | ||
| 159 | |||
| 160 | #define __get_user_check(x,ptr,size) \ | ||
| 161 | ({ \ | ||
| 162 | long __gu_err = -EFAULT, __gu_val = 0; \ | ||
| 163 | const __typeof__(*(ptr)) *__gu_addr = (ptr); \ | ||
| 164 | if (access_ok(VERIFY_READ,__gu_addr,size)) \ | ||
| 165 | __get_user_size(__gu_val,__gu_addr,(size),__gu_err); \ | ||
| 166 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
| 167 | __gu_err; \ | ||
| 168 | }) | ||
| 169 | |||
| 170 | extern long __get_user_bad(void); | ||
| 171 | |||
| 172 | /* More complex functions. Most are inline, but some call functions that | ||
| 173 | live in lib/usercopy.c */ | ||
| 174 | |||
| 175 | extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n); | ||
| 176 | extern unsigned long __copy_user_zeroing(void *to, const void __user *from, unsigned long n); | ||
| 177 | extern unsigned long __do_clear_user(void __user *to, unsigned long n); | ||
| 178 | |||
| 179 | static inline unsigned long | ||
| 180 | __generic_copy_to_user(void __user *to, const void *from, unsigned long n) | ||
| 181 | { | ||
| 182 | if (access_ok(VERIFY_WRITE, to, n)) | ||
| 183 | return __copy_user(to,from,n); | ||
| 184 | return n; | ||
| 185 | } | ||
| 186 | |||
| 187 | static inline unsigned long | ||
| 188 | __generic_copy_from_user(void *to, const void __user *from, unsigned long n) | ||
| 189 | { | ||
| 190 | if (access_ok(VERIFY_READ, from, n)) | ||
| 191 | return __copy_user_zeroing(to,from,n); | ||
| 192 | return n; | ||
| 193 | } | ||
| 194 | |||
| 195 | static inline unsigned long | ||
| 196 | __generic_clear_user(void __user *to, unsigned long n) | ||
| 197 | { | ||
| 198 | if (access_ok(VERIFY_WRITE, to, n)) | ||
| 199 | return __do_clear_user(to,n); | ||
| 200 | return n; | ||
| 201 | } | ||
| 202 | |||
| 203 | static inline long | ||
| 204 | __strncpy_from_user(char *dst, const char __user *src, long count) | ||
| 205 | { | ||
| 206 | return __do_strncpy_from_user(dst, src, count); | ||
| 207 | } | ||
| 208 | |||
| 209 | static inline long | ||
| 210 | strncpy_from_user(char *dst, const char __user *src, long count) | ||
| 211 | { | ||
| 212 | long res = -EFAULT; | ||
| 213 | if (access_ok(VERIFY_READ, src, 1)) | ||
| 214 | res = __do_strncpy_from_user(dst, src, count); | ||
| 215 | return res; | ||
| 216 | } | ||
| 217 | |||
| 218 | |||
| 219 | /* Note that these expand awfully if made into switch constructs, so | ||
| 220 | don't do that. */ | ||
| 221 | |||
| 222 | static inline unsigned long | ||
| 223 | __constant_copy_from_user(void *to, const void __user *from, unsigned long n) | ||
| 224 | { | ||
| 225 | unsigned long ret = 0; | ||
| 226 | if (n == 0) | ||
| 227 | ; | ||
| 228 | else if (n == 1) | ||
| 229 | __asm_copy_from_user_1(to, from, ret); | ||
| 230 | else if (n == 2) | ||
| 231 | __asm_copy_from_user_2(to, from, ret); | ||
| 232 | else if (n == 3) | ||
| 233 | __asm_copy_from_user_3(to, from, ret); | ||
| 234 | else if (n == 4) | ||
| 235 | __asm_copy_from_user_4(to, from, ret); | ||
| 236 | else if (n == 5) | ||
| 237 | __asm_copy_from_user_5(to, from, ret); | ||
| 238 | else if (n == 6) | ||
| 239 | __asm_copy_from_user_6(to, from, ret); | ||
| 240 | else if (n == 7) | ||
| 241 | __asm_copy_from_user_7(to, from, ret); | ||
| 242 | else if (n == 8) | ||
| 243 | __asm_copy_from_user_8(to, from, ret); | ||
| 244 | else if (n == 9) | ||
| 245 | __asm_copy_from_user_9(to, from, ret); | ||
| 246 | else if (n == 10) | ||
| 247 | __asm_copy_from_user_10(to, from, ret); | ||
| 248 | else if (n == 11) | ||
| 249 | __asm_copy_from_user_11(to, from, ret); | ||
| 250 | else if (n == 12) | ||
| 251 | __asm_copy_from_user_12(to, from, ret); | ||
| 252 | else if (n == 13) | ||
| 253 | __asm_copy_from_user_13(to, from, ret); | ||
| 254 | else if (n == 14) | ||
| 255 | __asm_copy_from_user_14(to, from, ret); | ||
| 256 | else if (n == 15) | ||
| 257 | __asm_copy_from_user_15(to, from, ret); | ||
| 258 | else if (n == 16) | ||
| 259 | __asm_copy_from_user_16(to, from, ret); | ||
| 260 | else if (n == 20) | ||
| 261 | __asm_copy_from_user_20(to, from, ret); | ||
| 262 | else if (n == 24) | ||
| 263 | __asm_copy_from_user_24(to, from, ret); | ||
| 264 | else | ||
| 265 | ret = __generic_copy_from_user(to, from, n); | ||
| 266 | |||
| 267 | return ret; | ||
| 268 | } | ||
| 269 | |||
| 270 | /* Ditto, don't make a switch out of this. */ | ||
| 271 | |||
| 272 | static inline unsigned long | ||
| 273 | __constant_copy_to_user(void __user *to, const void *from, unsigned long n) | ||
| 274 | { | ||
| 275 | unsigned long ret = 0; | ||
| 276 | if (n == 0) | ||
| 277 | ; | ||
| 278 | else if (n == 1) | ||
| 279 | __asm_copy_to_user_1(to, from, ret); | ||
| 280 | else if (n == 2) | ||
| 281 | __asm_copy_to_user_2(to, from, ret); | ||
| 282 | else if (n == 3) | ||
| 283 | __asm_copy_to_user_3(to, from, ret); | ||
| 284 | else if (n == 4) | ||
| 285 | __asm_copy_to_user_4(to, from, ret); | ||
| 286 | else if (n == 5) | ||
| 287 | __asm_copy_to_user_5(to, from, ret); | ||
| 288 | else if (n == 6) | ||
| 289 | __asm_copy_to_user_6(to, from, ret); | ||
| 290 | else if (n == 7) | ||
| 291 | __asm_copy_to_user_7(to, from, ret); | ||
| 292 | else if (n == 8) | ||
| 293 | __asm_copy_to_user_8(to, from, ret); | ||
| 294 | else if (n == 9) | ||
| 295 | __asm_copy_to_user_9(to, from, ret); | ||
| 296 | else if (n == 10) | ||
| 297 | __asm_copy_to_user_10(to, from, ret); | ||
| 298 | else if (n == 11) | ||
| 299 | __asm_copy_to_user_11(to, from, ret); | ||
| 300 | else if (n == 12) | ||
| 301 | __asm_copy_to_user_12(to, from, ret); | ||
| 302 | else if (n == 13) | ||
| 303 | __asm_copy_to_user_13(to, from, ret); | ||
| 304 | else if (n == 14) | ||
| 305 | __asm_copy_to_user_14(to, from, ret); | ||
| 306 | else if (n == 15) | ||
| 307 | __asm_copy_to_user_15(to, from, ret); | ||
| 308 | else if (n == 16) | ||
| 309 | __asm_copy_to_user_16(to, from, ret); | ||
| 310 | else if (n == 20) | ||
| 311 | __asm_copy_to_user_20(to, from, ret); | ||
| 312 | else if (n == 24) | ||
| 313 | __asm_copy_to_user_24(to, from, ret); | ||
| 314 | else | ||
| 315 | ret = __generic_copy_to_user(to, from, n); | ||
| 316 | |||
| 317 | return ret; | ||
| 318 | } | ||
| 319 | |||
| 320 | /* No switch, please. */ | ||
| 321 | |||
| 322 | static inline unsigned long | ||
| 323 | __constant_clear_user(void __user *to, unsigned long n) | ||
| 324 | { | ||
| 325 | unsigned long ret = 0; | ||
| 326 | if (n == 0) | ||
| 327 | ; | ||
| 328 | else if (n == 1) | ||
| 329 | __asm_clear_1(to, ret); | ||
| 330 | else if (n == 2) | ||
| 331 | __asm_clear_2(to, ret); | ||
| 332 | else if (n == 3) | ||
| 333 | __asm_clear_3(to, ret); | ||
| 334 | else if (n == 4) | ||
| 335 | __asm_clear_4(to, ret); | ||
| 336 | else if (n == 8) | ||
| 337 | __asm_clear_8(to, ret); | ||
| 338 | else if (n == 12) | ||
| 339 | __asm_clear_12(to, ret); | ||
| 340 | else if (n == 16) | ||
| 341 | __asm_clear_16(to, ret); | ||
| 342 | else if (n == 20) | ||
| 343 | __asm_clear_20(to, ret); | ||
| 344 | else if (n == 24) | ||
| 345 | __asm_clear_24(to, ret); | ||
| 346 | else | ||
| 347 | ret = __generic_clear_user(to, n); | ||
| 348 | |||
| 349 | return ret; | ||
| 350 | } | ||
| 351 | |||
| 352 | |||
| 353 | #define clear_user(to, n) \ | ||
| 354 | (__builtin_constant_p(n) ? \ | ||
| 355 | __constant_clear_user(to, n) : \ | ||
| 356 | __generic_clear_user(to, n)) | ||
| 357 | |||
| 358 | #define copy_from_user(to, from, n) \ | ||
| 359 | (__builtin_constant_p(n) ? \ | ||
| 360 | __constant_copy_from_user(to, from, n) : \ | ||
| 361 | __generic_copy_from_user(to, from, n)) | ||
| 362 | |||
| 363 | #define copy_to_user(to, from, n) \ | ||
| 364 | (__builtin_constant_p(n) ? \ | ||
| 365 | __constant_copy_to_user(to, from, n) : \ | ||
| 366 | __generic_copy_to_user(to, from, n)) | ||
| 367 | |||
| 368 | /* We let the __ versions of copy_from/to_user inline, because they're often | ||
| 369 | * used in fast paths and have only a small space overhead. | ||
| 370 | */ | ||
| 371 | |||
| 372 | static inline unsigned long | ||
| 373 | __generic_copy_from_user_nocheck(void *to, const void __user *from, | ||
| 374 | unsigned long n) | ||
| 375 | { | ||
| 376 | return __copy_user_zeroing(to,from,n); | ||
| 377 | } | ||
| 378 | |||
| 379 | static inline unsigned long | ||
| 380 | __generic_copy_to_user_nocheck(void __user *to, const void *from, | ||
| 381 | unsigned long n) | ||
| 382 | { | ||
| 383 | return __copy_user(to,from,n); | ||
| 384 | } | ||
| 385 | |||
| 386 | static inline unsigned long | ||
| 387 | __generic_clear_user_nocheck(void __user *to, unsigned long n) | ||
| 388 | { | ||
| 389 | return __do_clear_user(to,n); | ||
| 390 | } | ||
| 391 | |||
| 392 | /* without checking */ | ||
| 393 | |||
| 394 | #define __copy_to_user(to,from,n) __generic_copy_to_user_nocheck((to),(from),(n)) | ||
| 395 | #define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n)) | ||
| 396 | #define __copy_to_user_inatomic __copy_to_user | ||
| 397 | #define __copy_from_user_inatomic __copy_from_user | ||
| 398 | #define __clear_user(to,n) __generic_clear_user_nocheck((to),(n)) | ||
| 399 | |||
| 400 | #define strlen_user(str) strnlen_user((str), 0x7ffffffe) | ||
| 401 | |||
| 402 | #endif /* __ASSEMBLY__ */ | ||
| 403 | |||
| 404 | #endif /* _CRIS_UACCESS_H */ | ||
diff --git a/include/asm-cris/ucontext.h b/include/asm-cris/ucontext.h deleted file mode 100644 index eed6ad5eb3f2..000000000000 --- a/include/asm-cris/ucontext.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_UCONTEXT_H | ||
| 2 | #define _ASM_CRIS_UCONTEXT_H | ||
| 3 | |||
| 4 | struct ucontext { | ||
| 5 | unsigned long uc_flags; | ||
| 6 | struct ucontext *uc_link; | ||
| 7 | stack_t uc_stack; | ||
| 8 | struct sigcontext uc_mcontext; | ||
| 9 | sigset_t uc_sigmask; /* mask last for extensibility */ | ||
| 10 | }; | ||
| 11 | |||
| 12 | #endif /* !_ASM_CRIS_UCONTEXT_H */ | ||
diff --git a/include/asm-cris/unaligned.h b/include/asm-cris/unaligned.h deleted file mode 100644 index 7b3f3fec567c..000000000000 --- a/include/asm-cris/unaligned.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_UNALIGNED_H | ||
| 2 | #define _ASM_CRIS_UNALIGNED_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * CRIS can do unaligned accesses itself. | ||
| 6 | */ | ||
| 7 | #include <linux/unaligned/access_ok.h> | ||
| 8 | #include <linux/unaligned/generic.h> | ||
| 9 | |||
| 10 | #define get_unaligned __get_unaligned_le | ||
| 11 | #define put_unaligned __put_unaligned_le | ||
| 12 | |||
| 13 | #endif /* _ASM_CRIS_UNALIGNED_H */ | ||
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h deleted file mode 100644 index 76398ef87e9b..000000000000 --- a/include/asm-cris/unistd.h +++ /dev/null | |||
| @@ -1,374 +0,0 @@ | |||
| 1 | #ifndef _ASM_CRIS_UNISTD_H_ | ||
| 2 | #define _ASM_CRIS_UNISTD_H_ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file contains the system call numbers, and stub macros for libc. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #define __NR_restart_syscall 0 | ||
| 9 | #define __NR_exit 1 | ||
| 10 | #define __NR_fork 2 | ||
| 11 | #define __NR_read 3 | ||
| 12 | #define __NR_write 4 | ||
| 13 | #define __NR_open 5 | ||
| 14 | #define __NR_close 6 | ||
| 15 | #define __NR_waitpid 7 | ||
| 16 | #define __NR_creat 8 | ||
| 17 | #define __NR_link 9 | ||
| 18 | #define __NR_unlink 10 | ||
| 19 | #define __NR_execve 11 | ||
| 20 | #define __NR_chdir 12 | ||
| 21 | #define __NR_time 13 | ||
| 22 | #define __NR_mknod 14 | ||
| 23 | #define __NR_chmod 15 | ||
| 24 | #define __NR_lchown 16 | ||
| 25 | #define __NR_break 17 | ||
| 26 | #define __NR_oldstat 18 | ||
| 27 | #define __NR_lseek 19 | ||
| 28 | #define __NR_getpid 20 | ||
| 29 | #define __NR_mount 21 | ||
| 30 | #define __NR_umount 22 | ||
| 31 | #define __NR_setuid 23 | ||
| 32 | #define __NR_getuid 24 | ||
| 33 | #define __NR_stime 25 | ||
| 34 | #define __NR_ptrace 26 | ||
| 35 | #define __NR_alarm 27 | ||
| 36 | #define __NR_oldfstat 28 | ||
| 37 | #define __NR_pause 29 | ||
| 38 | #define __NR_utime 30 | ||
| 39 | #define __NR_stty 31 | ||
| 40 | #define __NR_gtty 32 | ||
| 41 | #define __NR_access 33 | ||
| 42 | #define __NR_nice 34 | ||
| 43 | #define __NR_ftime 35 | ||
| 44 | #define __NR_sync 36 | ||
| 45 | #define __NR_kill 37 | ||
| 46 | #define __NR_rename 38 | ||
| 47 | #define __NR_mkdir 39 | ||
| 48 | #define __NR_rmdir 40 | ||
| 49 | #define __NR_dup 41 | ||
| 50 | #define __NR_pipe 42 | ||
| 51 | #define __NR_times 43 | ||
| 52 | #define __NR_prof 44 | ||
| 53 | #define __NR_brk 45 | ||
| 54 | #define __NR_setgid 46 | ||
| 55 | #define __NR_getgid 47 | ||
| 56 | #define __NR_signal 48 | ||
| 57 | #define __NR_geteuid 49 | ||
| 58 | #define __NR_getegid 50 | ||
| 59 | #define __NR_acct 51 | ||
| 60 | #define __NR_umount2 52 | ||
| 61 | #define __NR_lock 53 | ||
| 62 | #define __NR_ioctl 54 | ||
| 63 | #define __NR_fcntl 55 | ||
| 64 | #define __NR_mpx 56 | ||
| 65 | #define __NR_setpgid 57 | ||
| 66 | #define __NR_ulimit 58 | ||
| 67 | #define __NR_oldolduname 59 | ||
| 68 | #define __NR_umask 60 | ||
| 69 | #define __NR_chroot 61 | ||
| 70 | #define __NR_ustat 62 | ||
| 71 | #define __NR_dup2 63 | ||
| 72 | #define __NR_getppid 64 | ||
| 73 | #define __NR_getpgrp 65 | ||
| 74 | #define __NR_setsid 66 | ||
| 75 | #define __NR_sigaction 67 | ||
| 76 | #define __NR_sgetmask 68 | ||
| 77 | #define __NR_ssetmask 69 | ||
| 78 | #define __NR_setreuid 70 | ||
| 79 | #define __NR_setregid 71 | ||
| 80 | #define __NR_sigsuspend 72 | ||
| 81 | #define __NR_sigpending 73 | ||
| 82 | #define __NR_sethostname 74 | ||
| 83 | #define __NR_setrlimit 75 | ||
| 84 | #define __NR_getrlimit 76 | ||
| 85 | #define __NR_getrusage 77 | ||
| 86 | #define __NR_gettimeofday 78 | ||
| 87 | #define __NR_settimeofday 79 | ||
| 88 | #define __NR_getgroups 80 | ||
| 89 | #define __NR_setgroups 81 | ||
| 90 | #define __NR_select 82 | ||
| 91 | #define __NR_symlink 83 | ||
| 92 | #define __NR_oldlstat 84 | ||
| 93 | #define __NR_readlink 85 | ||
| 94 | #define __NR_uselib 86 | ||
| 95 | #define __NR_swapon 87 | ||
| 96 | #define __NR_reboot 88 | ||
| 97 | #define __NR_readdir 89 | ||
| 98 | #define __NR_mmap 90 | ||
| 99 | #define __NR_munmap 91 | ||
| 100 | #define __NR_truncate 92 | ||
| 101 | #define __NR_ftruncate 93 | ||
| 102 | #define __NR_fchmod 94 | ||
| 103 | #define __NR_fchown 95 | ||
| 104 | #define __NR_getpriority 96 | ||
| 105 | #define __NR_setpriority 97 | ||
| 106 | #define __NR_profil 98 | ||
| 107 | #define __NR_statfs 99 | ||
| 108 | #define __NR_fstatfs 100 | ||
| 109 | #define __NR_ioperm 101 | ||
| 110 | #define __NR_socketcall 102 | ||
| 111 | #define __NR_syslog 103 | ||
| 112 | #define __NR_setitimer 104 | ||
| 113 | #define __NR_getitimer 105 | ||
| 114 | #define __NR_stat 106 | ||
| 115 | #define __NR_lstat 107 | ||
| 116 | #define __NR_fstat 108 | ||
| 117 | #define __NR_olduname 109 | ||
| 118 | #define __NR_iopl 110 | ||
| 119 | #define __NR_vhangup 111 | ||
| 120 | #define __NR_idle 112 | ||
| 121 | #define __NR_vm86 113 | ||
| 122 | #define __NR_wait4 114 | ||
| 123 | #define __NR_swapoff 115 | ||
| 124 | #define __NR_sysinfo 116 | ||
| 125 | #define __NR_ipc 117 | ||
| 126 | #define __NR_fsync 118 | ||
| 127 | #define __NR_sigreturn 119 | ||
| 128 | #define __NR_clone 120 | ||
| 129 | #define __NR_setdomainname 121 | ||
| 130 | #define __NR_uname 122 | ||
| 131 | #define __NR_modify_ldt 123 | ||
| 132 | #define __NR_adjtimex 124 | ||
| 133 | #define __NR_mprotect 125 | ||
| 134 | #define __NR_sigprocmask 126 | ||
| 135 | #define __NR_create_module 127 | ||
| 136 | #define __NR_init_module 128 | ||
| 137 | #define __NR_delete_module 129 | ||
| 138 | #define __NR_get_kernel_syms 130 | ||
| 139 | #define __NR_quotactl 131 | ||
| 140 | #define __NR_getpgid 132 | ||
| 141 | #define __NR_fchdir 133 | ||
| 142 | #define __NR_bdflush 134 | ||
| 143 | #define __NR_sysfs 135 | ||
| 144 | #define __NR_personality 136 | ||
| 145 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
| 146 | #define __NR_setfsuid 138 | ||
| 147 | #define __NR_setfsgid 139 | ||
| 148 | #define __NR__llseek 140 | ||
| 149 | #define __NR_getdents 141 | ||
| 150 | #define __NR__newselect 142 | ||
| 151 | #define __NR_flock 143 | ||
| 152 | #define __NR_msync 144 | ||
| 153 | #define __NR_readv 145 | ||
| 154 | #define __NR_writev 146 | ||
| 155 | #define __NR_getsid 147 | ||
| 156 | #define __NR_fdatasync 148 | ||
| 157 | #define __NR__sysctl 149 | ||
| 158 | #define __NR_mlock 150 | ||
| 159 | #define __NR_munlock 151 | ||
| 160 | #define __NR_mlockall 152 | ||
| 161 | #define __NR_munlockall 153 | ||
| 162 | #define __NR_sched_setparam 154 | ||
| 163 | #define __NR_sched_getparam 155 | ||
| 164 | #define __NR_sched_setscheduler 156 | ||
| 165 | #define __NR_sched_getscheduler 157 | ||
| 166 | #define __NR_sched_yield 158 | ||
| 167 | #define __NR_sched_get_priority_max 159 | ||
| 168 | #define __NR_sched_get_priority_min 160 | ||
| 169 | #define __NR_sched_rr_get_interval 161 | ||
| 170 | #define __NR_nanosleep 162 | ||
| 171 | #define __NR_mremap 163 | ||
| 172 | #define __NR_setresuid 164 | ||
| 173 | #define __NR_getresuid 165 | ||
| 174 | |||
| 175 | #define __NR_query_module 167 | ||
| 176 | #define __NR_poll 168 | ||
| 177 | #define __NR_nfsservctl 169 | ||
| 178 | #define __NR_setresgid 170 | ||
| 179 | #define __NR_getresgid 171 | ||
| 180 | #define __NR_prctl 172 | ||
| 181 | #define __NR_rt_sigreturn 173 | ||
| 182 | #define __NR_rt_sigaction 174 | ||
| 183 | #define __NR_rt_sigprocmask 175 | ||
| 184 | #define __NR_rt_sigpending 176 | ||
| 185 | #define __NR_rt_sigtimedwait 177 | ||
| 186 | #define __NR_rt_sigqueueinfo 178 | ||
| 187 | #define __NR_rt_sigsuspend 179 | ||
| 188 | #define __NR_pread64 180 | ||
| 189 | #define __NR_pwrite64 181 | ||
| 190 | #define __NR_chown 182 | ||
| 191 | #define __NR_getcwd 183 | ||
| 192 | #define __NR_capget 184 | ||
| 193 | #define __NR_capset 185 | ||
| 194 | #define __NR_sigaltstack 186 | ||
| 195 | #define __NR_sendfile 187 | ||
| 196 | #define __NR_getpmsg 188 /* some people actually want streams */ | ||
| 197 | #define __NR_putpmsg 189 /* some people actually want streams */ | ||
| 198 | #define __NR_vfork 190 | ||
| 199 | #define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ | ||
| 200 | #define __NR_mmap2 192 | ||
| 201 | #define __NR_truncate64 193 | ||
| 202 | #define __NR_ftruncate64 194 | ||
| 203 | #define __NR_stat64 195 | ||
| 204 | #define __NR_lstat64 196 | ||
| 205 | #define __NR_fstat64 197 | ||
| 206 | #define __NR_lchown32 198 | ||
| 207 | #define __NR_getuid32 199 | ||
| 208 | #define __NR_getgid32 200 | ||
| 209 | #define __NR_geteuid32 201 | ||
| 210 | #define __NR_getegid32 202 | ||
| 211 | #define __NR_setreuid32 203 | ||
| 212 | #define __NR_setregid32 204 | ||
| 213 | #define __NR_getgroups32 205 | ||
| 214 | #define __NR_setgroups32 206 | ||
| 215 | #define __NR_fchown32 207 | ||
| 216 | #define __NR_setresuid32 208 | ||
| 217 | #define __NR_getresuid32 209 | ||
| 218 | #define __NR_setresgid32 210 | ||
| 219 | #define __NR_getresgid32 211 | ||
| 220 | #define __NR_chown32 212 | ||
| 221 | #define __NR_setuid32 213 | ||
| 222 | #define __NR_setgid32 214 | ||
| 223 | #define __NR_setfsuid32 215 | ||
| 224 | #define __NR_setfsgid32 216 | ||
| 225 | #define __NR_pivot_root 217 | ||
| 226 | #define __NR_mincore 218 | ||
| 227 | #define __NR_madvise 219 | ||
| 228 | #define __NR_getdents64 220 | ||
| 229 | #define __NR_fcntl64 221 | ||
| 230 | /* 223 is unused */ | ||
| 231 | #define __NR_gettid 224 | ||
| 232 | #define __NR_readahead 225 | ||
| 233 | #define __NR_setxattr 226 | ||
| 234 | #define __NR_lsetxattr 227 | ||
| 235 | #define __NR_fsetxattr 228 | ||
| 236 | #define __NR_getxattr 229 | ||
| 237 | #define __NR_lgetxattr 230 | ||
| 238 | #define __NR_fgetxattr 231 | ||
| 239 | #define __NR_listxattr 232 | ||
| 240 | #define __NR_llistxattr 233 | ||
| 241 | #define __NR_flistxattr 234 | ||
| 242 | #define __NR_removexattr 235 | ||
| 243 | #define __NR_lremovexattr 236 | ||
| 244 | #define __NR_fremovexattr 237 | ||
| 245 | #define __NR_tkill 238 | ||
| 246 | #define __NR_sendfile64 239 | ||
| 247 | #define __NR_futex 240 | ||
| 248 | #define __NR_sched_setaffinity 241 | ||
| 249 | #define __NR_sched_getaffinity 242 | ||
| 250 | #define __NR_set_thread_area 243 | ||
| 251 | #define __NR_get_thread_area 244 | ||
| 252 | #define __NR_io_setup 245 | ||
| 253 | #define __NR_io_destroy 246 | ||
| 254 | #define __NR_io_getevents 247 | ||
| 255 | #define __NR_io_submit 248 | ||
| 256 | #define __NR_io_cancel 249 | ||
| 257 | #define __NR_fadvise64 250 | ||
| 258 | /* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ | ||
| 259 | #define __NR_exit_group 252 | ||
| 260 | #define __NR_lookup_dcookie 253 | ||
| 261 | #define __NR_epoll_create 254 | ||
| 262 | #define __NR_epoll_ctl 255 | ||
| 263 | #define __NR_epoll_wait 256 | ||
| 264 | #define __NR_remap_file_pages 257 | ||
| 265 | #define __NR_set_tid_address 258 | ||
| 266 | #define __NR_timer_create 259 | ||
| 267 | #define __NR_timer_settime (__NR_timer_create+1) | ||
| 268 | #define __NR_timer_gettime (__NR_timer_create+2) | ||
| 269 | #define __NR_timer_getoverrun (__NR_timer_create+3) | ||
| 270 | #define __NR_timer_delete (__NR_timer_create+4) | ||
| 271 | #define __NR_clock_settime (__NR_timer_create+5) | ||
| 272 | #define __NR_clock_gettime (__NR_timer_create+6) | ||
| 273 | #define __NR_clock_getres (__NR_timer_create+7) | ||
| 274 | #define __NR_clock_nanosleep (__NR_timer_create+8) | ||
| 275 | #define __NR_statfs64 268 | ||
| 276 | #define __NR_fstatfs64 269 | ||
| 277 | #define __NR_tgkill 270 | ||
| 278 | #define __NR_utimes 271 | ||
| 279 | #define __NR_fadvise64_64 272 | ||
| 280 | #define __NR_vserver 273 | ||
| 281 | #define __NR_mbind 274 | ||
| 282 | #define __NR_get_mempolicy 275 | ||
| 283 | #define __NR_set_mempolicy 276 | ||
| 284 | #define __NR_mq_open 277 | ||
| 285 | #define __NR_mq_unlink (__NR_mq_open+1) | ||
| 286 | #define __NR_mq_timedsend (__NR_mq_open+2) | ||
| 287 | #define __NR_mq_timedreceive (__NR_mq_open+3) | ||
| 288 | #define __NR_mq_notify (__NR_mq_open+4) | ||
| 289 | #define __NR_mq_getsetattr (__NR_mq_open+5) | ||
| 290 | #define __NR_kexec_load 283 | ||
| 291 | #define __NR_waitid 284 | ||
| 292 | /* #define __NR_sys_setaltroot 285 */ | ||
| 293 | #define __NR_add_key 286 | ||
| 294 | #define __NR_request_key 287 | ||
| 295 | #define __NR_keyctl 288 | ||
| 296 | #define __NR_ioprio_set 289 | ||
| 297 | #define __NR_ioprio_get 290 | ||
| 298 | #define __NR_inotify_init 291 | ||
| 299 | #define __NR_inotify_add_watch 292 | ||
| 300 | #define __NR_inotify_rm_watch 293 | ||
| 301 | #define __NR_migrate_pages 294 | ||
| 302 | #define __NR_openat 295 | ||
| 303 | #define __NR_mkdirat 296 | ||
| 304 | #define __NR_mknodat 297 | ||
| 305 | #define __NR_fchownat 298 | ||
| 306 | #define __NR_futimesat 299 | ||
| 307 | #define __NR_fstatat64 300 | ||
| 308 | #define __NR_unlinkat 301 | ||
| 309 | #define __NR_renameat 302 | ||
| 310 | #define __NR_linkat 303 | ||
| 311 | #define __NR_symlinkat 304 | ||
| 312 | #define __NR_readlinkat 305 | ||
| 313 | #define __NR_fchmodat 306 | ||
| 314 | #define __NR_faccessat 307 | ||
| 315 | #define __NR_pselect6 308 | ||
| 316 | #define __NR_ppoll 309 | ||
| 317 | #define __NR_unshare 310 | ||
| 318 | #define __NR_set_robust_list 311 | ||
| 319 | #define __NR_get_robust_list 312 | ||
| 320 | #define __NR_splice 313 | ||
| 321 | #define __NR_sync_file_range 314 | ||
| 322 | #define __NR_tee 315 | ||
| 323 | #define __NR_vmsplice 316 | ||
| 324 | #define __NR_move_pages 317 | ||
| 325 | #define __NR_getcpu 318 | ||
| 326 | #define __NR_epoll_pwait 319 | ||
| 327 | #define __NR_utimensat 320 | ||
| 328 | #define __NR_signalfd 321 | ||
| 329 | #define __NR_timerfd_create 322 | ||
| 330 | #define __NR_eventfd 323 | ||
| 331 | #define __NR_fallocate 324 | ||
| 332 | #define __NR_timerfd_settime 325 | ||
| 333 | #define __NR_timerfd_gettime 326 | ||
| 334 | |||
| 335 | #ifdef __KERNEL__ | ||
| 336 | |||
| 337 | #define NR_syscalls 327 | ||
| 338 | |||
| 339 | #include <asm/arch/unistd.h> | ||
| 340 | |||
| 341 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
| 342 | #define __ARCH_WANT_OLD_READDIR | ||
| 343 | #define __ARCH_WANT_OLD_STAT | ||
| 344 | #define __ARCH_WANT_STAT64 | ||
| 345 | #define __ARCH_WANT_SYS_ALARM | ||
| 346 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
| 347 | #define __ARCH_WANT_SYS_PAUSE | ||
| 348 | #define __ARCH_WANT_SYS_SGETMASK | ||
| 349 | #define __ARCH_WANT_SYS_SIGNAL | ||
| 350 | #define __ARCH_WANT_SYS_TIME | ||
| 351 | #define __ARCH_WANT_SYS_UTIME | ||
| 352 | #define __ARCH_WANT_SYS_WAITPID | ||
| 353 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
| 354 | #define __ARCH_WANT_SYS_FADVISE64 | ||
| 355 | #define __ARCH_WANT_SYS_GETPGRP | ||
| 356 | #define __ARCH_WANT_SYS_LLSEEK | ||
| 357 | #define __ARCH_WANT_SYS_NICE | ||
| 358 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
| 359 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
| 360 | #define __ARCH_WANT_SYS_SIGPENDING | ||
| 361 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
| 362 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
| 363 | #define __ARCH_WANT_SYS_RT_SIGSUSPEND | ||
| 364 | |||
| 365 | /* | ||
| 366 | * "Conditional" syscalls | ||
| 367 | * | ||
| 368 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
| 369 | * but it doesn't work on all toolchains, so we just do it by hand | ||
| 370 | */ | ||
| 371 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
| 372 | |||
| 373 | #endif /* __KERNEL__ */ | ||
| 374 | #endif /* _ASM_CRIS_UNISTD_H_ */ | ||
diff --git a/include/asm-cris/user.h b/include/asm-cris/user.h deleted file mode 100644 index 73e60fcbcf38..000000000000 --- a/include/asm-cris/user.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | #ifndef __ASM_CRIS_USER_H | ||
| 2 | #define __ASM_CRIS_USER_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | #include <asm/ptrace.h> | ||
| 6 | #include <asm/page.h> | ||
| 7 | #include <asm/arch/user.h> | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Core file format: The core file is written in such a way that gdb | ||
| 11 | * can understand it and provide useful information to the user (under | ||
| 12 | * linux we use the `trad-core' bfd). The file contents are as follows: | ||
| 13 | * | ||
| 14 | * upage: 1 page consisting of a user struct that tells gdb | ||
| 15 | * what is present in the file. Directly after this is a | ||
| 16 | * copy of the task_struct, which is currently not used by gdb, | ||
| 17 | * but it may come in handy at some point. All of the registers | ||
| 18 | * are stored as part of the upage. The upage should always be | ||
| 19 | * only one page long. | ||
| 20 | * data: The data segment follows next. We use current->end_text to | ||
| 21 | * current->brk to pick up all of the user variables, plus any memory | ||
| 22 | * that may have been sbrk'ed. No attempt is made to determine if a | ||
| 23 | * page is demand-zero or if a page is totally unused, we just cover | ||
| 24 | * the entire range. All of the addresses are rounded in such a way | ||
| 25 | * that an integral number of pages is written. | ||
| 26 | * stack: We need the stack information in order to get a meaningful | ||
| 27 | * backtrace. We need to write the data from usp to | ||
| 28 | * current->start_stack, so we round each of these in order to be able | ||
| 29 | * to write an integer number of pages. | ||
| 30 | */ | ||
| 31 | |||
| 32 | struct user { | ||
| 33 | struct user_regs_struct regs; /* entire machine state */ | ||
| 34 | size_t u_tsize; /* text size (pages) */ | ||
| 35 | size_t u_dsize; /* data size (pages) */ | ||
| 36 | size_t u_ssize; /* stack size (pages) */ | ||
| 37 | unsigned long start_code; /* text starting address */ | ||
| 38 | unsigned long start_data; /* data starting address */ | ||
| 39 | unsigned long start_stack; /* stack starting address */ | ||
| 40 | long int signal; /* signal causing core dump */ | ||
| 41 | unsigned long u_ar0; /* help gdb find registers */ | ||
| 42 | unsigned long magic; /* identifies a core file */ | ||
| 43 | char u_comm[32]; /* user command name */ | ||
| 44 | }; | ||
| 45 | |||
| 46 | #define NBPG PAGE_SIZE | ||
| 47 | #define UPAGES 1 | ||
| 48 | #define HOST_TEXT_START_ADDR (u.start_code) | ||
| 49 | #define HOST_DATA_START_ADDR (u.start_data) | ||
| 50 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) | ||
| 51 | |||
| 52 | #endif /* __ASM_CRIS_USER_H */ | ||