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-rw-r--r--include/acpi/acpi_bus.h17
-rw-r--r--include/acpi/acpi_drivers.h1
-rw-r--r--include/asm-alpha/pci.h19
-rw-r--r--include/asm-alpha/serial.h47
-rw-r--r--include/asm-arm/arch-pxa/debug-macro.S2
-rw-r--r--include/asm-arm/arch-s3c2410/audio.h49
-rw-r--r--include/asm-arm/hardware/arm_timer.h21
-rw-r--r--include/asm-arm/pci.h10
-rw-r--r--include/asm-arm/system.h12
-rw-r--r--include/asm-arm/tlbflush.h28
-rw-r--r--include/asm-arm26/serial.h22
-rw-r--r--include/asm-frv/pci.h10
-rw-r--r--include/asm-i386/pci.h10
-rw-r--r--include/asm-i386/serial.h102
-rw-r--r--include/asm-ia64/iosapic.h12
-rw-r--r--include/asm-ia64/mmu_context.h3
-rw-r--r--include/asm-ia64/pci.h19
-rw-r--r--include/asm-ia64/sn/addrs.h17
-rw-r--r--include/asm-ia64/sn/l1.h1
-rw-r--r--include/asm-ia64/sn/shub_mmr.h346
-rw-r--r--include/asm-ia64/sn/simulator.h13
-rw-r--r--include/asm-ia64/sn/sn2/sn_hwperf.h2
-rw-r--r--include/asm-ia64/sn/sn_sal.h10
-rw-r--r--include/asm-ia64/sn/tioca_provider.h1
-rw-r--r--include/asm-ia64/vga.h5
-rw-r--r--include/asm-m68k/serial.h47
-rw-r--r--include/asm-mips/pci.h10
-rw-r--r--include/asm-mips/serial.h84
-rw-r--r--include/asm-parisc/pci.h19
-rw-r--r--include/asm-parisc/serial.h16
-rw-r--r--include/asm-ppc/pc_serial.h86
-rw-r--r--include/asm-ppc/pci.h16
-rw-r--r--include/asm-ppc64/byteorder.h10
-rw-r--r--include/asm-ppc64/pci.h26
-rw-r--r--include/asm-sh/bigsur/serial.h5
-rw-r--r--include/asm-sh/ec3104/serial.h4
-rw-r--r--include/asm-sh/pci.h10
-rw-r--r--include/asm-sh/serial.h6
-rw-r--r--include/asm-sh64/pci.h10
-rw-r--r--include/asm-sh64/serial.h4
-rw-r--r--include/asm-sparc/pci.h10
-rw-r--r--include/asm-sparc64/pci.h19
-rw-r--r--include/asm-v850/pci.h10
-rw-r--r--include/asm-x86_64/pci.h10
-rw-r--r--include/asm-x86_64/serial.h102
-rw-r--r--include/linux/acpi.h19
-rw-r--r--include/linux/blkdev.h1
-rw-r--r--include/linux/byteorder/swabb.h17
-rw-r--r--include/linux/etherdevice.h1
-rw-r--r--include/linux/i2c-dev.h1
-rw-r--r--include/linux/in6.h2
-rw-r--r--include/linux/irq.h5
-rw-r--r--include/linux/netlink.h1
-rw-r--r--include/linux/pci.h33
-rw-r--r--include/linux/pci_ids.h2
-rw-r--r--include/linux/pkt_cls.h1
-rw-r--r--include/linux/pkt_sched.h9
-rw-r--r--include/linux/rtnetlink.h10
-rw-r--r--include/linux/sysctl.h1
-rw-r--r--include/linux/usb_ch9.h6
-rw-r--r--include/linux/videodev2.h2
-rw-r--r--include/linux/writeback.h2
-rw-r--r--include/linux/xattr_acl.h50
-rw-r--r--include/media/tuner.h20
-rw-r--r--include/net/ipv6.h1
-rw-r--r--include/net/sctp/constants.h18
-rw-r--r--include/net/sctp/structs.h4
67 files changed, 675 insertions, 814 deletions
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index c627bc408a6b..9ad142476f33 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -108,6 +108,21 @@ typedef int (*acpi_op_unbind) (struct acpi_device *device);
108typedef int (*acpi_op_match) (struct acpi_device *device, 108typedef int (*acpi_op_match) (struct acpi_device *device,
109 struct acpi_driver *driver); 109 struct acpi_driver *driver);
110 110
111struct acpi_bus_ops {
112 u32 acpi_op_add:1;
113 u32 acpi_op_remove:1;
114 u32 acpi_op_lock:1;
115 u32 acpi_op_start:1;
116 u32 acpi_op_stop:1;
117 u32 acpi_op_suspend:1;
118 u32 acpi_op_resume:1;
119 u32 acpi_op_scan:1;
120 u32 acpi_op_bind:1;
121 u32 acpi_op_unbind:1;
122 u32 acpi_op_match:1;
123 u32 reserved:21;
124};
125
111struct acpi_device_ops { 126struct acpi_device_ops {
112 acpi_op_add add; 127 acpi_op_add add;
113 acpi_op_remove remove; 128 acpi_op_remove remove;
@@ -327,9 +342,9 @@ int acpi_bus_generate_event (struct acpi_device *device, u8 type, int data);
327int acpi_bus_receive_event (struct acpi_bus_event *event); 342int acpi_bus_receive_event (struct acpi_bus_event *event);
328int acpi_bus_register_driver (struct acpi_driver *driver); 343int acpi_bus_register_driver (struct acpi_driver *driver);
329int acpi_bus_unregister_driver (struct acpi_driver *driver); 344int acpi_bus_unregister_driver (struct acpi_driver *driver);
330int acpi_bus_scan (struct acpi_device *start);
331int acpi_bus_add (struct acpi_device **child, struct acpi_device *parent, 345int acpi_bus_add (struct acpi_device **child, struct acpi_device *parent,
332 acpi_handle handle, int type); 346 acpi_handle handle, int type);
347int acpi_bus_start (struct acpi_device *device);
333 348
334 349
335int acpi_match_ids (struct acpi_device *device, char *ids); 350int acpi_match_ids (struct acpi_device *device, char *ids);
diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h
index c62e92ec43b2..4ec722d73381 100644
--- a/include/acpi/acpi_drivers.h
+++ b/include/acpi/acpi_drivers.h
@@ -68,6 +68,7 @@ void acpi_pci_irq_del_prt (int segment, int bus);
68 68
69struct pci_bus; 69struct pci_bus;
70 70
71acpi_status acpi_get_pci_id (acpi_handle handle, struct acpi_pci_id *id);
71int acpi_pci_bind (struct acpi_device *device); 72int acpi_pci_bind (struct acpi_device *device);
72int acpi_pci_unbind (struct acpi_device *device); 73int acpi_pci_unbind (struct acpi_device *device);
73int acpi_pci_bind_root (struct acpi_device *device, struct acpi_pci_id *id, struct pci_bus *bus); 74int acpi_pci_bind_root (struct acpi_device *device, struct acpi_pci_id *id, struct pci_bus *bus);
diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h
index 0c7b57bc043a..b7806aa3785c 100644
--- a/include/asm-alpha/pci.h
+++ b/include/asm-alpha/pci.h
@@ -223,6 +223,25 @@ pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr,
223 /* Nothing to do. */ 223 /* Nothing to do. */
224} 224}
225 225
226#ifdef CONFIG_PCI
227static inline void pci_dma_burst_advice(struct pci_dev *pdev,
228 enum pci_dma_burst_strategy *strat,
229 unsigned long *strategy_parameter)
230{
231 unsigned long cacheline_size;
232 u8 byte;
233
234 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
235 if (byte == 0)
236 cacheline_size = 1024;
237 else
238 cacheline_size = (int) byte * 4;
239
240 *strat = PCI_DMA_BURST_BOUNDARY;
241 *strategy_parameter = cacheline_size;
242}
243#endif
244
226/* TODO: integrate with include/asm-generic/pci.h ? */ 245/* TODO: integrate with include/asm-generic/pci.h ? */
227static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 246static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
228{ 247{
diff --git a/include/asm-alpha/serial.h b/include/asm-alpha/serial.h
index 7b2d9ee95a44..7e4b2987d453 100644
--- a/include/asm-alpha/serial.h
+++ b/include/asm-alpha/serial.h
@@ -22,54 +22,9 @@
22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
23#endif 23#endif
24 24
25#ifdef CONFIG_SERIAL_MANY_PORTS 25#define SERIAL_PORT_DFNS \
26#define FOURPORT_FLAGS ASYNC_FOURPORT
27#define ACCENT_FLAGS 0
28#define BOCA_FLAGS 0
29#endif
30
31#define STD_SERIAL_PORT_DEFNS \
32 /* UART CLK PORT IRQ FLAGS */ \ 26 /* UART CLK PORT IRQ FLAGS */ \
33 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 27 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
34 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 28 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
35 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 29 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
36 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 30 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
37
38
39#ifdef CONFIG_SERIAL_MANY_PORTS
40#define EXTRA_SERIAL_PORT_DEFNS \
41 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
42 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
43 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
44 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
45 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
46 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
47 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
48 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
49 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
50 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
51 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
52 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
53 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
54 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
55 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
56 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
57 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
58 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
59 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
60 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
61 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
62 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
63 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
64 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
65 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
66 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
67 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
68 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
69#else
70#define EXTRA_SERIAL_PORT_DEFNS
71#endif
72
73#define SERIAL_PORT_DFNS \
74 STD_SERIAL_PORT_DEFNS \
75 EXTRA_SERIAL_PORT_DEFNS
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S
index f288e74b67c2..b6ec68879176 100644
--- a/include/asm-arm/arch-pxa/debug-macro.S
+++ b/include/asm-arm/arch-pxa/debug-macro.S
@@ -11,6 +11,8 @@
11 * 11 *
12*/ 12*/
13 13
14#include "hardware.h"
15
14 .macro addruart,rx 16 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0 17 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled? 18 tst \rx, #1 @ MMU enabled?
diff --git a/include/asm-arm/arch-s3c2410/audio.h b/include/asm-arm/arch-s3c2410/audio.h
new file mode 100644
index 000000000000..0d276e67f2fb
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/audio.h
@@ -0,0 +1,49 @@
1/* linux/include/asm-arm/arch-s3c2410/audio.h
2 *
3 * (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX - Audio platfrom_device info
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Changelog:
14 * 20-Nov-2004 BJD Created file
15 * 07-Mar-2005 BJD Added suspend/resume calls
16*/
17
18#ifndef __ASM_ARCH_AUDIO_H
19#define __ASM_ARCH_AUDIO_H __FILE__
20
21/* struct s3c24xx_iis_ops
22 *
23 * called from the s3c24xx audio core to deal with the architecture
24 * or the codec's setup and control.
25 *
26 * the pointer to itself is passed through in case the caller wants to
27 * embed this in an larger structure for easy reference to it's context.
28*/
29
30struct s3c24xx_iis_ops {
31 struct module *owner;
32
33 int (*startup)(struct s3c24xx_iis_ops *me);
34 void (*shutdown)(struct s3c24xx_iis_ops *me);
35 int (*suspend)(struct s3c24xx_iis_ops *me);
36 int (*resume)(struct s3c24xx_iis_ops *me);
37
38 int (*open)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm);
39 int (*close)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm);
40 int (*prepare)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm, snd_pcm_runtime_t *rt);
41};
42
43struct s3c24xx_platdata_iis {
44 const char *codec_clk;
45 struct s3c24xx_iis_ops *ops;
46 int (*match_dev)(struct device *dev);
47};
48
49#endif /* __ASM_ARCH_AUDIO_H */
diff --git a/include/asm-arm/hardware/arm_timer.h b/include/asm-arm/hardware/arm_timer.h
new file mode 100644
index 000000000000..04be3bdf46b8
--- /dev/null
+++ b/include/asm-arm/hardware/arm_timer.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
2#define __ASM_ARM_HARDWARE_ARM_TIMER_H
3
4#define TIMER_LOAD 0x00
5#define TIMER_VALUE 0x04
6#define TIMER_CTRL 0x08
7#define TIMER_CTRL_ONESHOT (1 << 0)
8#define TIMER_CTRL_32BIT (1 << 1)
9#define TIMER_CTRL_DIV1 (0 << 2)
10#define TIMER_CTRL_DIV16 (1 << 2)
11#define TIMER_CTRL_DIV256 (2 << 2)
12#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
13#define TIMER_CTRL_PERIODIC (1 << 6)
14#define TIMER_CTRL_ENABLE (1 << 7)
15
16#define TIMER_INTCLR 0x0c
17#define TIMER_RIS 0x10
18#define TIMER_MIS 0x14
19#define TIMER_BGLOAD 0x18
20
21#endif
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index 40ffaefbeb1a..e300646fe650 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -42,6 +42,16 @@ static inline void pcibios_penalize_isa_irq(int irq)
42#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) 42#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
43#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) 43#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
44 44
45#ifdef CONFIG_PCI
46static inline void pci_dma_burst_advice(struct pci_dev *pdev,
47 enum pci_dma_burst_strategy *strat,
48 unsigned long *strategy_parameter)
49{
50 *strat = PCI_DMA_BURST_INFINITY;
51 *strategy_parameter = ~0UL;
52}
53#endif
54
45#define HAVE_PCI_MMAP 55#define HAVE_PCI_MMAP
46extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 56extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
47 enum pci_mmap_state mmap_state, int write_combine); 57 enum pci_mmap_state mmap_state, int write_combine);
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 3d0d2860b6db..cdf49f442fd2 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -290,7 +290,6 @@ do { \
290}) 290})
291 291
292#ifdef CONFIG_SMP 292#ifdef CONFIG_SMP
293#error SMP not supported
294 293
295#define smp_mb() mb() 294#define smp_mb() mb()
296#define smp_rmb() rmb() 295#define smp_rmb() rmb()
@@ -304,6 +303,8 @@ do { \
304#define smp_wmb() barrier() 303#define smp_wmb() barrier()
305#define smp_read_barrier_depends() do { } while(0) 304#define smp_read_barrier_depends() do { } while(0)
306 305
306#endif /* CONFIG_SMP */
307
307#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) 308#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
308/* 309/*
309 * On the StrongARM, "swp" is terminally broken since it bypasses the 310 * On the StrongARM, "swp" is terminally broken since it bypasses the
@@ -316,9 +317,16 @@ do { \
316 * 317 *
317 * We choose (1) since its the "easiest" to achieve here and is not 318 * We choose (1) since its the "easiest" to achieve here and is not
318 * dependent on the processor type. 319 * dependent on the processor type.
320 *
321 * NOTE that this solution won't work on an SMP system, so explcitly
322 * forbid it here.
319 */ 323 */
324#ifdef CONFIG_SMP
325#error SMP is not supported on SA1100/SA110
326#else
320#define swp_is_buggy 327#define swp_is_buggy
321#endif 328#endif
329#endif
322 330
323static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) 331static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
324{ 332{
@@ -361,8 +369,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
361 return ret; 369 return ret;
362} 370}
363 371
364#endif /* CONFIG_SMP */
365
366#endif /* __ASSEMBLY__ */ 372#endif /* __ASSEMBLY__ */
367 373
368#define arch_align_stack(x) (x) 374#define arch_align_stack(x) (x)
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8a864b118569..9387a5e1ffe0 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -235,7 +235,7 @@ extern struct cpu_tlb_fns cpu_tlb;
235 235
236#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) 236#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
237 237
238static inline void flush_tlb_all(void) 238static inline void local_flush_tlb_all(void)
239{ 239{
240 const int zero = 0; 240 const int zero = 0;
241 const unsigned int __tlb_flag = __cpu_tlb_flags; 241 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -253,7 +253,7 @@ static inline void flush_tlb_all(void)
253 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); 253 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
254} 254}
255 255
256static inline void flush_tlb_mm(struct mm_struct *mm) 256static inline void local_flush_tlb_mm(struct mm_struct *mm)
257{ 257{
258 const int zero = 0; 258 const int zero = 0;
259 const int asid = ASID(mm); 259 const int asid = ASID(mm);
@@ -282,7 +282,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
282} 282}
283 283
284static inline void 284static inline void
285flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 285local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
286{ 286{
287 const int zero = 0; 287 const int zero = 0;
288 const unsigned int __tlb_flag = __cpu_tlb_flags; 288 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -313,7 +313,7 @@ flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
313 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr)); 313 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
314} 314}
315 315
316static inline void flush_tlb_kernel_page(unsigned long kaddr) 316static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
317{ 317{
318 const int zero = 0; 318 const int zero = 0;
319 const unsigned int __tlb_flag = __cpu_tlb_flags; 319 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -384,8 +384,24 @@ static inline void clean_pmd_entry(pmd_t *pmd)
384/* 384/*
385 * Convert calls to our calling convention. 385 * Convert calls to our calling convention.
386 */ 386 */
387#define flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) 387#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
388#define flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) 388#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
389
390#ifndef CONFIG_SMP
391#define flush_tlb_all local_flush_tlb_all
392#define flush_tlb_mm local_flush_tlb_mm
393#define flush_tlb_page local_flush_tlb_page
394#define flush_tlb_kernel_page local_flush_tlb_kernel_page
395#define flush_tlb_range local_flush_tlb_range
396#define flush_tlb_kernel_range local_flush_tlb_kernel_range
397#else
398extern void flush_tlb_all(void);
399extern void flush_tlb_mm(struct mm_struct *mm);
400extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
401extern void flush_tlb_kernel_page(unsigned long kaddr);
402extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
403extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
404#endif
389 405
390/* 406/*
391 * if PG_dcache_dirty is set for the page, we need to ensure that any 407 * if PG_dcache_dirty is set for the page, we need to ensure that any
diff --git a/include/asm-arm26/serial.h b/include/asm-arm26/serial.h
index 21e1df31f086..5fc747d1b501 100644
--- a/include/asm-arm26/serial.h
+++ b/include/asm-arm26/serial.h
@@ -30,34 +30,16 @@
30#if defined(CONFIG_ARCH_A5K) 30#if defined(CONFIG_ARCH_A5K)
31 /* UART CLK PORT IRQ FLAGS */ 31 /* UART CLK PORT IRQ FLAGS */
32 32
33#define STD_SERIAL_PORT_DEFNS \ 33#define SERIAL_PORT_DFNS \
34 { 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \ 34 { 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \
35 { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */ 35 { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */
36 36
37#else 37#else
38 38
39#define STD_SERIAL_PORT_DEFNS \ 39#define SERIAL_PORT_DFNS \
40 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS0 */ \ 40 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS0 */ \
41 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS1 */ 41 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS1 */
42 42
43#endif 43#endif
44 44
45#define EXTRA_SERIAL_PORT_DEFNS \
46 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS2 */ \
47 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS3 */ \
48 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS4 */ \
49 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS5 */ \
50 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS6 */ \
51 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS7 */ \
52 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS8 */ \
53 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS9 */ \
54 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS10 */ \
55 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS11 */ \
56 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS12 */ \
57 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS13 */
58
59#define SERIAL_PORT_DFNS \
60 STD_SERIAL_PORT_DEFNS \
61 EXTRA_SERIAL_PORT_DEFNS
62
63#endif 45#endif
diff --git a/include/asm-frv/pci.h b/include/asm-frv/pci.h
index a6a469231f62..b4efe5e3591a 100644
--- a/include/asm-frv/pci.h
+++ b/include/asm-frv/pci.h
@@ -57,6 +57,16 @@ extern void pci_free_consistent(struct pci_dev *hwdev, size_t size,
57 */ 57 */
58#define PCI_DMA_BUS_IS_PHYS (1) 58#define PCI_DMA_BUS_IS_PHYS (1)
59 59
60#ifdef CONFIG_PCI
61static inline void pci_dma_burst_advice(struct pci_dev *pdev,
62 enum pci_dma_burst_strategy *strat,
63 unsigned long *strategy_parameter)
64{
65 *strat = PCI_DMA_BURST_INFINITY;
66 *strategy_parameter = ~0UL;
67}
68#endif
69
60/* 70/*
61 * These are pretty much arbitary with the CoMEM implementation. 71 * These are pretty much arbitary with the CoMEM implementation.
62 * We have the whole address space to ourselves. 72 * We have the whole address space to ourselves.
diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h
index fb749b85a739..3561899eb826 100644
--- a/include/asm-i386/pci.h
+++ b/include/asm-i386/pci.h
@@ -99,6 +99,16 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
99{ 99{
100} 100}
101 101
102#ifdef CONFIG_PCI
103static inline void pci_dma_burst_advice(struct pci_dev *pdev,
104 enum pci_dma_burst_strategy *strat,
105 unsigned long *strategy_parameter)
106{
107 *strat = PCI_DMA_BURST_INFINITY;
108 *strategy_parameter = ~0UL;
109}
110#endif
111
102#endif /* __KERNEL__ */ 112#endif /* __KERNEL__ */
103 113
104/* implement the pci_ DMA API in terms of the generic device dma_ one */ 114/* implement the pci_ DMA API in terms of the generic device dma_ one */
diff --git a/include/asm-i386/serial.h b/include/asm-i386/serial.h
index 21ddecc77c77..e1ecfccb743b 100644
--- a/include/asm-i386/serial.h
+++ b/include/asm-i386/serial.h
@@ -22,109 +22,9 @@
22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
23#endif 23#endif
24 24
25#ifdef CONFIG_SERIAL_MANY_PORTS 25#define SERIAL_PORT_DFNS \
26#define FOURPORT_FLAGS ASYNC_FOURPORT
27#define ACCENT_FLAGS 0
28#define BOCA_FLAGS 0
29#define HUB6_FLAGS 0
30#endif
31
32#define MCA_COM_FLAGS (STD_COM_FLAGS|ASYNC_BOOT_ONLYMCA)
33
34/*
35 * The following define the access methods for the HUB6 card. All
36 * access is through two ports for all 24 possible chips. The card is
37 * selected through the high 2 bits, the port on that card with the
38 * "middle" 3 bits, and the register on that port with the bottom
39 * 3 bits.
40 *
41 * While the access port and interrupt is configurable, the default
42 * port locations are 0x302 for the port control register, and 0x303
43 * for the data read/write register. Normally, the interrupt is at irq3
44 * but can be anything from 3 to 7 inclusive. Note that using 3 will
45 * require disabling com2.
46 */
47
48#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
49
50#define STD_SERIAL_PORT_DEFNS \
51 /* UART CLK PORT IRQ FLAGS */ \ 26 /* UART CLK PORT IRQ FLAGS */ \
52 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 27 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
53 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 28 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
54 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 29 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
55 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 30 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
56
57
58#ifdef CONFIG_SERIAL_MANY_PORTS
59#define EXTRA_SERIAL_PORT_DEFNS \
60 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
61 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
62 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
63 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
64 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
65 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
66 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
67 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
68 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
69 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
70 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
71 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
72 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
73 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
74 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
75 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
76 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
77 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
78 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
79 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
80 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
81 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
82 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
83 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
84 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
85 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
86 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
87 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
88#else
89#define EXTRA_SERIAL_PORT_DEFNS
90#endif
91
92/* You can have up to four HUB6's in the system, but I've only
93 * included two cards here for a total of twelve ports.
94 */
95#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
96#define HUB6_SERIAL_PORT_DFNS \
97 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
98 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
99 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
100 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
101 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
102 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
103 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
104 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
105 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
106 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
107 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
108 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
109#else
110#define HUB6_SERIAL_PORT_DFNS
111#endif
112
113#ifdef CONFIG_MCA
114#define MCA_SERIAL_PORT_DFNS \
115 { 0, BASE_BAUD, 0x3220, 3, MCA_COM_FLAGS }, \
116 { 0, BASE_BAUD, 0x3228, 3, MCA_COM_FLAGS }, \
117 { 0, BASE_BAUD, 0x4220, 3, MCA_COM_FLAGS }, \
118 { 0, BASE_BAUD, 0x4228, 3, MCA_COM_FLAGS }, \
119 { 0, BASE_BAUD, 0x5220, 3, MCA_COM_FLAGS }, \
120 { 0, BASE_BAUD, 0x5228, 3, MCA_COM_FLAGS },
121#else
122#define MCA_SERIAL_PORT_DFNS
123#endif
124
125#define SERIAL_PORT_DFNS \
126 STD_SERIAL_PORT_DEFNS \
127 EXTRA_SERIAL_PORT_DEFNS \
128 HUB6_SERIAL_PORT_DFNS \
129 MCA_SERIAL_PORT_DFNS
130
diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h
index 38a7a72791cc..1093f35b3b90 100644
--- a/include/asm-ia64/iosapic.h
+++ b/include/asm-ia64/iosapic.h
@@ -71,8 +71,11 @@ static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
71} 71}
72 72
73extern void __init iosapic_system_init (int pcat_compat); 73extern void __init iosapic_system_init (int pcat_compat);
74extern void __init iosapic_init (unsigned long address, 74extern int __devinit iosapic_init (unsigned long address,
75 unsigned int gsi_base); 75 unsigned int gsi_base);
76#ifdef CONFIG_HOTPLUG
77extern int iosapic_remove (unsigned int gsi_base);
78#endif /* CONFIG_HOTPLUG */
76extern int gsi_to_vector (unsigned int gsi); 79extern int gsi_to_vector (unsigned int gsi);
77extern int gsi_to_irq (unsigned int gsi); 80extern int gsi_to_irq (unsigned int gsi);
78extern void iosapic_enable_intr (unsigned int vector); 81extern void iosapic_enable_intr (unsigned int vector);
@@ -94,11 +97,14 @@ extern unsigned int iosapic_version (char __iomem *addr);
94 97
95extern void iosapic_pci_fixup (int); 98extern void iosapic_pci_fixup (int);
96#ifdef CONFIG_NUMA 99#ifdef CONFIG_NUMA
97extern void __init map_iosapic_to_node (unsigned int, int); 100extern void __devinit map_iosapic_to_node (unsigned int, int);
98#endif 101#endif
99#else 102#else
100#define iosapic_system_init(pcat_compat) do { } while (0) 103#define iosapic_system_init(pcat_compat) do { } while (0)
101#define iosapic_init(address,gsi_base) do { } while (0) 104#define iosapic_init(address,gsi_base) (-EINVAL)
105#ifdef CONFIG_HOTPLUG
106#define iosapic_remove(gsi_base) (-ENODEV)
107#endif /* CONFIG_HOTPLUG */
102#define iosapic_register_intr(gsi,polarity,trigger) (gsi) 108#define iosapic_register_intr(gsi,polarity,trigger) (gsi)
103#define iosapic_unregister_intr(irq) do { } while (0) 109#define iosapic_unregister_intr(irq) do { } while (0)
104#define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger) do { } while (0) 110#define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger) do { } while (0)
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h
index 0096e7e05012..e3e5fededb04 100644
--- a/include/asm-ia64/mmu_context.h
+++ b/include/asm-ia64/mmu_context.h
@@ -132,6 +132,9 @@ reload_context (mm_context_t context)
132 ia64_srlz_i(); /* srlz.i implies srlz.d */ 132 ia64_srlz_i(); /* srlz.i implies srlz.d */
133} 133}
134 134
135/*
136 * Must be called with preemption off
137 */
135static inline void 138static inline void
136activate_context (struct mm_struct *mm) 139activate_context (struct mm_struct *mm)
137{ 140{
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
index a8314ee4e7d2..0c4c5d801d3f 100644
--- a/include/asm-ia64/pci.h
+++ b/include/asm-ia64/pci.h
@@ -82,6 +82,25 @@ extern int pcibios_prep_mwi (struct pci_dev *);
82#define sg_dma_len(sg) ((sg)->dma_length) 82#define sg_dma_len(sg) ((sg)->dma_length)
83#define sg_dma_address(sg) ((sg)->dma_address) 83#define sg_dma_address(sg) ((sg)->dma_address)
84 84
85#ifdef CONFIG_PCI
86static inline void pci_dma_burst_advice(struct pci_dev *pdev,
87 enum pci_dma_burst_strategy *strat,
88 unsigned long *strategy_parameter)
89{
90 unsigned long cacheline_size;
91 u8 byte;
92
93 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
94 if (byte == 0)
95 cacheline_size = 1024;
96 else
97 cacheline_size = (int) byte * 4;
98
99 *strat = PCI_DMA_BURST_MULTIPLE;
100 *strategy_parameter = cacheline_size;
101}
102#endif
103
85#define HAVE_PCI_MMAP 104#define HAVE_PCI_MMAP
86extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, 105extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
87 enum pci_mmap_state mmap_state, int write_combine); 106 enum pci_mmap_state mmap_state, int write_combine);
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index 1bfdfb4d7b01..103d745dc5f2 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -216,6 +216,10 @@
216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK) 216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
217 217
218 218
219#define TIO_IOSPACE_ADDR(n,x) \
220 /* Move in the Chiplet ID for TIO Local Block MMR */ \
221 (REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
222
219/* 223/*
220 * The following macros produce the correct base virtual address for 224 * The following macros produce the correct base virtual address for
221 * the hub registers. The REMOTE_HUB_* macro produce 225 * the hub registers. The REMOTE_HUB_* macro produce
@@ -233,13 +237,16 @@
233#define REMOTE_HUB_ADDR(n,x) \ 237#define REMOTE_HUB_ADDR(n,x) \
234 ((n & 1) ? \ 238 ((n & 1) ? \
235 /* TIO: */ \ 239 /* TIO: */ \
236 ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \ 240 (is_shub2() ? \
237 : /* SHUB: */ \ 241 /* TIO on Shub2 */ \
238 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\ 242 (volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \
243 : /* TIO on shub1 */ \
244 (volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
245 \
246 : /* SHUB1 and SHUB2 MMRs: */ \
247 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
239 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x))))) 248 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
240 249
241
242
243#define HUB_L(x) (*((volatile typeof(*x) *)x)) 250#define HUB_L(x) (*((volatile typeof(*x) *)x))
244#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d)) 251#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
245 252
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 08050d37b662..2e5f0aa38889 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -33,5 +33,6 @@
33#define L1_BRICKTYPE_PA 0x6a /* j */ 33#define L1_BRICKTYPE_PA 0x6a /* j */
34#define L1_BRICKTYPE_IA 0x6b /* k */ 34#define L1_BRICKTYPE_IA 0x6b /* k */
35#define L1_BRICKTYPE_ATHENA 0x2b /* + */ 35#define L1_BRICKTYPE_ATHENA 0x2b /* + */
36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
36 37
37#endif /* _ASM_IA64_SN_L1_H */ 38#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 323fa0cd8d83..7de1d1d4b71a 100644
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -14,96 +14,98 @@
14/* Register "SH_IPI_INT" */ 14/* Register "SH_IPI_INT" */
15/* SHub Inter-Processor Interrupt Registers */ 15/* SHub Inter-Processor Interrupt Registers */
16/* ==================================================================== */ 16/* ==================================================================== */
17#define SH1_IPI_INT 0x0000000110000380 17#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
18#define SH2_IPI_INT 0x0000000010000380 18#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
19 19
20/* SH_IPI_INT_TYPE */ 20/* SH_IPI_INT_TYPE */
21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
22#define SH_IPI_INT_TYPE_SHFT 0 22#define SH_IPI_INT_TYPE_SHFT 0
23#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 23#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
24 24
25/* SH_IPI_INT_AGT */ 25/* SH_IPI_INT_AGT */
26/* Description: Agent, must be 0 for SHub */ 26/* Description: Agent, must be 0 for SHub */
27#define SH_IPI_INT_AGT_SHFT 3 27#define SH_IPI_INT_AGT_SHFT 3
28#define SH_IPI_INT_AGT_MASK 0x0000000000000008 28#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
29 29
30/* SH_IPI_INT_PID */ 30/* SH_IPI_INT_PID */
31/* Description: Processor ID, same setting as on targeted McKinley */ 31/* Description: Processor ID, same setting as on targeted McKinley */
32#define SH_IPI_INT_PID_SHFT 4 32#define SH_IPI_INT_PID_SHFT 4
33#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 33#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
34 34
35/* SH_IPI_INT_BASE */ 35/* SH_IPI_INT_BASE */
36/* Description: Optional interrupt vector area, 2MB aligned */ 36/* Description: Optional interrupt vector area, 2MB aligned */
37#define SH_IPI_INT_BASE_SHFT 21 37#define SH_IPI_INT_BASE_SHFT 21
38#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 38#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
39 39
40/* SH_IPI_INT_IDX */ 40/* SH_IPI_INT_IDX */
41/* Description: Targeted McKinley interrupt vector */ 41/* Description: Targeted McKinley interrupt vector */
42#define SH_IPI_INT_IDX_SHFT 52 42#define SH_IPI_INT_IDX_SHFT 52
43#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 43#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
44 44
45/* SH_IPI_INT_SEND */ 45/* SH_IPI_INT_SEND */
46/* Description: Send Interrupt Message to PI, This generates a puls */ 46/* Description: Send Interrupt Message to PI, This generates a puls */
47#define SH_IPI_INT_SEND_SHFT 63 47#define SH_IPI_INT_SEND_SHFT 63
48#define SH_IPI_INT_SEND_MASK 0x8000000000000000 48#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
49 49
50/* ==================================================================== */ 50/* ==================================================================== */
51/* Register "SH_EVENT_OCCURRED" */ 51/* Register "SH_EVENT_OCCURRED" */
52/* SHub Interrupt Event Occurred */ 52/* SHub Interrupt Event Occurred */
53/* ==================================================================== */ 53/* ==================================================================== */
54#define SH1_EVENT_OCCURRED 0x0000000110010000 54#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
55#define SH1_EVENT_OCCURRED_ALIAS 0x0000000110010008 55#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
56#define SH2_EVENT_OCCURRED 0x0000000010010000 56#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
57#define SH2_EVENT_OCCURRED_ALIAS 0x0000000010010008 57#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
58 58
59/* ==================================================================== */ 59/* ==================================================================== */
60/* Register "SH_PI_CAM_CONTROL" */ 60/* Register "SH_PI_CAM_CONTROL" */
61/* CRB CAM MMR Access Control */ 61/* CRB CAM MMR Access Control */
62/* ==================================================================== */ 62/* ==================================================================== */
63#define SH1_PI_CAM_CONTROL 0x0000000120050300 63#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
64 64
65/* ==================================================================== */ 65/* ==================================================================== */
66/* Register "SH_SHUB_ID" */ 66/* Register "SH_SHUB_ID" */
67/* SHub ID Number */ 67/* SHub ID Number */
68/* ==================================================================== */ 68/* ==================================================================== */
69#define SH1_SHUB_ID 0x0000000110060580 69#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
70#define SH1_SHUB_ID_REVISION_SHFT 28 70#define SH1_SHUB_ID_REVISION_SHFT 28
71#define SH1_SHUB_ID_REVISION_MASK 0x00000000f0000000 71#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
72 72
73/* ==================================================================== */ 73/* ==================================================================== */
74/* Register "SH_RTC" */ 74/* Register "SH_RTC" */
75/* Real-time Clock */ 75/* Real-time Clock */
76/* ==================================================================== */ 76/* ==================================================================== */
77#define SH1_RTC 0x00000001101c0000 77#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
78#define SH2_RTC 0x00000002101c0000 78#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
79#define SH_RTC_MASK 0x007fffffffffffff 79#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
80 80
81/* ==================================================================== */ 81/* ==================================================================== */
82/* Register "SH_PIO_WRITE_STATUS_0|1" */ 82/* Register "SH_PIO_WRITE_STATUS_0|1" */
83/* PIO Write Status for CPU 0 & 1 */ 83/* PIO Write Status for CPU 0 & 1 */
84/* ==================================================================== */ 84/* ==================================================================== */
85#define SH1_PIO_WRITE_STATUS_0 0x0000000120070200 85#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
86#define SH1_PIO_WRITE_STATUS_1 0x0000000120070280 86#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
87#define SH2_PIO_WRITE_STATUS_0 0x0000000020070200 87#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
88#define SH2_PIO_WRITE_STATUS_1 0x0000000020070280 88#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
89#define SH2_PIO_WRITE_STATUS_2 0x0000000020070300 89#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
90#define SH2_PIO_WRITE_STATUS_3 0x0000000020070380 90#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
91 91
92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ 92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
93/* Description: Deadlock response detected */ 93/* Description: Deadlock response detected */
94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1 94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002 95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
96 __IA64_UL_CONST(0x0000000000000002)
96 97
97/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ 98/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
98/* Description: Count of currently pending PIO writes */ 99/* Description: Count of currently pending PIO writes */
99#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56 100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 101#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
102 __IA64_UL_CONST(0x3f00000000000000)
101 103
102/* ==================================================================== */ 104/* ==================================================================== */
103/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ 105/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
104/* ==================================================================== */ 106/* ==================================================================== */
105#define SH1_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 107#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
106#define SH2_PIO_WRITE_STATUS_0_ALIAS 0x0000000020070208 108#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
107 109
108/* ==================================================================== */ 110/* ==================================================================== */
109/* Register "SH_EVENT_OCCURRED" */ 111/* Register "SH_EVENT_OCCURRED" */
@@ -111,33 +113,33 @@
111/* ==================================================================== */ 113/* ==================================================================== */
112/* SH_EVENT_OCCURRED_UART_INT */ 114/* SH_EVENT_OCCURRED_UART_INT */
113/* Description: Pending Junk Bus UART Interrupt */ 115/* Description: Pending Junk Bus UART Interrupt */
114#define SH_EVENT_OCCURRED_UART_INT_SHFT 20 116#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
115#define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 117#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
116 118
117/* SH_EVENT_OCCURRED_IPI_INT */ 119/* SH_EVENT_OCCURRED_IPI_INT */
118/* Description: Pending IPI Interrupt */ 120/* Description: Pending IPI Interrupt */
119#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 121#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
120#define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 122#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
121 123
122/* SH_EVENT_OCCURRED_II_INT0 */ 124/* SH_EVENT_OCCURRED_II_INT0 */
123/* Description: Pending II 0 Interrupt */ 125/* Description: Pending II 0 Interrupt */
124#define SH_EVENT_OCCURRED_II_INT0_SHFT 29 126#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
125#define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 127#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
126 128
127/* SH_EVENT_OCCURRED_II_INT1 */ 129/* SH_EVENT_OCCURRED_II_INT1 */
128/* Description: Pending II 1 Interrupt */ 130/* Description: Pending II 1 Interrupt */
129#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 131#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
130#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 132#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
131 133
132/* SH2_EVENT_OCCURRED_EXTIO_INT2 */ 134/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
133/* Description: Pending SHUB 2 EXT IO INT2 */ 135/* Description: Pending SHUB 2 EXT IO INT2 */
134#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33 136#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
135#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000 137#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
136 138
137/* SH2_EVENT_OCCURRED_EXTIO_INT3 */ 139/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
138/* Description: Pending SHUB 2 EXT IO INT3 */ 140/* Description: Pending SHUB 2 EXT IO INT3 */
139#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34 141#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
140#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000 142#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
141 143
142#define SH_ALL_INT_MASK \ 144#define SH_ALL_INT_MASK \
143 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \ 145 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
@@ -149,310 +151,310 @@
149/* ==================================================================== */ 151/* ==================================================================== */
150/* LEDS */ 152/* LEDS */
151/* ==================================================================== */ 153/* ==================================================================== */
152#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL 154#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
153#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL 155#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
154#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL 156#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
155#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL 157#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
156 158
157#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL 159#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
158#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL 160#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
159#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL 161#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
160#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL 162#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
161 163
162/* ==================================================================== */ 164/* ==================================================================== */
163/* Register "SH1_PTC_0" */ 165/* Register "SH1_PTC_0" */
164/* Puge Translation Cache Message Configuration Information */ 166/* Puge Translation Cache Message Configuration Information */
165/* ==================================================================== */ 167/* ==================================================================== */
166#define SH1_PTC_0 0x00000001101a0000 168#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
167 169
168/* SH1_PTC_0_A */ 170/* SH1_PTC_0_A */
169/* Description: Type */ 171/* Description: Type */
170#define SH1_PTC_0_A_SHFT 0 172#define SH1_PTC_0_A_SHFT 0
171 173
172/* SH1_PTC_0_PS */ 174/* SH1_PTC_0_PS */
173/* Description: Page Size */ 175/* Description: Page Size */
174#define SH1_PTC_0_PS_SHFT 2 176#define SH1_PTC_0_PS_SHFT 2
175 177
176/* SH1_PTC_0_RID */ 178/* SH1_PTC_0_RID */
177/* Description: Region ID */ 179/* Description: Region ID */
178#define SH1_PTC_0_RID_SHFT 8 180#define SH1_PTC_0_RID_SHFT 8
179 181
180/* SH1_PTC_0_START */ 182/* SH1_PTC_0_START */
181/* Description: Start */ 183/* Description: Start */
182#define SH1_PTC_0_START_SHFT 63 184#define SH1_PTC_0_START_SHFT 63
183 185
184/* ==================================================================== */ 186/* ==================================================================== */
185/* Register "SH1_PTC_1" */ 187/* Register "SH1_PTC_1" */
186/* Puge Translation Cache Message Configuration Information */ 188/* Puge Translation Cache Message Configuration Information */
187/* ==================================================================== */ 189/* ==================================================================== */
188#define SH1_PTC_1 0x00000001101a0080 190#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
189 191
190/* SH1_PTC_1_START */ 192/* SH1_PTC_1_START */
191/* Description: PTC_1 Start */ 193/* Description: PTC_1 Start */
192#define SH1_PTC_1_START_SHFT 63 194#define SH1_PTC_1_START_SHFT 63
193
194 195
195/* ==================================================================== */ 196/* ==================================================================== */
196/* Register "SH2_PTC" */ 197/* Register "SH2_PTC" */
197/* Puge Translation Cache Message Configuration Information */ 198/* Puge Translation Cache Message Configuration Information */
198/* ==================================================================== */ 199/* ==================================================================== */
199#define SH2_PTC 0x0000000170000000 200#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
200 201
201/* SH2_PTC_A */ 202/* SH2_PTC_A */
202/* Description: Type */ 203/* Description: Type */
203#define SH2_PTC_A_SHFT 0 204#define SH2_PTC_A_SHFT 0
204 205
205/* SH2_PTC_PS */ 206/* SH2_PTC_PS */
206/* Description: Page Size */ 207/* Description: Page Size */
207#define SH2_PTC_PS_SHFT 2 208#define SH2_PTC_PS_SHFT 2
208 209
209/* SH2_PTC_RID */ 210/* SH2_PTC_RID */
210/* Description: Region ID */ 211/* Description: Region ID */
211#define SH2_PTC_RID_SHFT 4 212#define SH2_PTC_RID_SHFT 4
212 213
213/* SH2_PTC_START */ 214/* SH2_PTC_START */
214/* Description: Start */ 215/* Description: Start */
215#define SH2_PTC_START_SHFT 63 216#define SH2_PTC_START_SHFT 63
216 217
217/* SH2_PTC_ADDR_RID */ 218/* SH2_PTC_ADDR_RID */
218/* Description: Region ID */ 219/* Description: Region ID */
219#define SH2_PTC_ADDR_SHFT 4 220#define SH2_PTC_ADDR_SHFT 4
220#define SH2_PTC_ADDR_MASK 0x1ffffffffffff000 221#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
221 222
222/* ==================================================================== */ 223/* ==================================================================== */
223/* Register "SH_RTC1_INT_CONFIG" */ 224/* Register "SH_RTC1_INT_CONFIG" */
224/* SHub RTC 1 Interrupt Config Registers */ 225/* SHub RTC 1 Interrupt Config Registers */
225/* ==================================================================== */ 226/* ==================================================================== */
226 227
227#define SH1_RTC1_INT_CONFIG 0x0000000110001480 228#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
228#define SH2_RTC1_INT_CONFIG 0x0000000010001480 229#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
229#define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff 230#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
230#define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 231#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
231 232
232/* SH_RTC1_INT_CONFIG_TYPE */ 233/* SH_RTC1_INT_CONFIG_TYPE */
233/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 234/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
234#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 235#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
235#define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 236#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
236 237
237/* SH_RTC1_INT_CONFIG_AGT */ 238/* SH_RTC1_INT_CONFIG_AGT */
238/* Description: Agent, must be 0 for SHub */ 239/* Description: Agent, must be 0 for SHub */
239#define SH_RTC1_INT_CONFIG_AGT_SHFT 3 240#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
240#define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 241#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
241 242
242/* SH_RTC1_INT_CONFIG_PID */ 243/* SH_RTC1_INT_CONFIG_PID */
243/* Description: Processor ID, same setting as on targeted McKinley */ 244/* Description: Processor ID, same setting as on targeted McKinley */
244#define SH_RTC1_INT_CONFIG_PID_SHFT 4 245#define SH_RTC1_INT_CONFIG_PID_SHFT 4
245#define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 246#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
246 247
247/* SH_RTC1_INT_CONFIG_BASE */ 248/* SH_RTC1_INT_CONFIG_BASE */
248/* Description: Optional interrupt vector area, 2MB aligned */ 249/* Description: Optional interrupt vector area, 2MB aligned */
249#define SH_RTC1_INT_CONFIG_BASE_SHFT 21 250#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
250#define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 251#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
251 252
252/* SH_RTC1_INT_CONFIG_IDX */ 253/* SH_RTC1_INT_CONFIG_IDX */
253/* Description: Targeted McKinley interrupt vector */ 254/* Description: Targeted McKinley interrupt vector */
254#define SH_RTC1_INT_CONFIG_IDX_SHFT 52 255#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
255#define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 256#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
256 257
257/* ==================================================================== */ 258/* ==================================================================== */
258/* Register "SH_RTC1_INT_ENABLE" */ 259/* Register "SH_RTC1_INT_ENABLE" */
259/* SHub RTC 1 Interrupt Enable Registers */ 260/* SHub RTC 1 Interrupt Enable Registers */
260/* ==================================================================== */ 261/* ==================================================================== */
261 262
262#define SH1_RTC1_INT_ENABLE 0x0000000110001500 263#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
263#define SH2_RTC1_INT_ENABLE 0x0000000010001500 264#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
264#define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 265#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
265#define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 266#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
266 267
267/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ 268/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
268/* Description: Enable RTC 1 Interrupt */ 269/* Description: Enable RTC 1 Interrupt */
269#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 271#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
272 __IA64_UL_CONST(0x0000000000000001)
271 273
272/* ==================================================================== */ 274/* ==================================================================== */
273/* Register "SH_RTC2_INT_CONFIG" */ 275/* Register "SH_RTC2_INT_CONFIG" */
274/* SHub RTC 2 Interrupt Config Registers */ 276/* SHub RTC 2 Interrupt Config Registers */
275/* ==================================================================== */ 277/* ==================================================================== */
276 278
277#define SH1_RTC2_INT_CONFIG 0x0000000110001580 279#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
278#define SH2_RTC2_INT_CONFIG 0x0000000010001580 280#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
279#define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff 281#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
280#define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 282#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
281 283
282/* SH_RTC2_INT_CONFIG_TYPE */ 284/* SH_RTC2_INT_CONFIG_TYPE */
283/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 285/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
284#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 286#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
285#define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 287#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
286 288
287/* SH_RTC2_INT_CONFIG_AGT */ 289/* SH_RTC2_INT_CONFIG_AGT */
288/* Description: Agent, must be 0 for SHub */ 290/* Description: Agent, must be 0 for SHub */
289#define SH_RTC2_INT_CONFIG_AGT_SHFT 3 291#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
290#define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 292#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
291 293
292/* SH_RTC2_INT_CONFIG_PID */ 294/* SH_RTC2_INT_CONFIG_PID */
293/* Description: Processor ID, same setting as on targeted McKinley */ 295/* Description: Processor ID, same setting as on targeted McKinley */
294#define SH_RTC2_INT_CONFIG_PID_SHFT 4 296#define SH_RTC2_INT_CONFIG_PID_SHFT 4
295#define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 297#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
296 298
297/* SH_RTC2_INT_CONFIG_BASE */ 299/* SH_RTC2_INT_CONFIG_BASE */
298/* Description: Optional interrupt vector area, 2MB aligned */ 300/* Description: Optional interrupt vector area, 2MB aligned */
299#define SH_RTC2_INT_CONFIG_BASE_SHFT 21 301#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
300#define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 302#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
301 303
302/* SH_RTC2_INT_CONFIG_IDX */ 304/* SH_RTC2_INT_CONFIG_IDX */
303/* Description: Targeted McKinley interrupt vector */ 305/* Description: Targeted McKinley interrupt vector */
304#define SH_RTC2_INT_CONFIG_IDX_SHFT 52 306#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
305#define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 307#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
306 308
307/* ==================================================================== */ 309/* ==================================================================== */
308/* Register "SH_RTC2_INT_ENABLE" */ 310/* Register "SH_RTC2_INT_ENABLE" */
309/* SHub RTC 2 Interrupt Enable Registers */ 311/* SHub RTC 2 Interrupt Enable Registers */
310/* ==================================================================== */ 312/* ==================================================================== */
311 313
312#define SH1_RTC2_INT_ENABLE 0x0000000110001600 314#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
313#define SH2_RTC2_INT_ENABLE 0x0000000010001600 315#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
314#define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 316#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
315#define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 317#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
316 318
317/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ 319/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
318/* Description: Enable RTC 2 Interrupt */ 320/* Description: Enable RTC 2 Interrupt */
319#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 321#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
320#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 322#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
323 __IA64_UL_CONST(0x0000000000000001)
321 324
322/* ==================================================================== */ 325/* ==================================================================== */
323/* Register "SH_RTC3_INT_CONFIG" */ 326/* Register "SH_RTC3_INT_CONFIG" */
324/* SHub RTC 3 Interrupt Config Registers */ 327/* SHub RTC 3 Interrupt Config Registers */
325/* ==================================================================== */ 328/* ==================================================================== */
326 329
327#define SH1_RTC3_INT_CONFIG 0x0000000110001680 330#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
328#define SH2_RTC3_INT_CONFIG 0x0000000010001680 331#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
329#define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff 332#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
330#define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 333#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
331 334
332/* SH_RTC3_INT_CONFIG_TYPE */ 335/* SH_RTC3_INT_CONFIG_TYPE */
333/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 336/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
334#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 337#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
335#define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 338#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
336 339
337/* SH_RTC3_INT_CONFIG_AGT */ 340/* SH_RTC3_INT_CONFIG_AGT */
338/* Description: Agent, must be 0 for SHub */ 341/* Description: Agent, must be 0 for SHub */
339#define SH_RTC3_INT_CONFIG_AGT_SHFT 3 342#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
340#define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 343#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
341 344
342/* SH_RTC3_INT_CONFIG_PID */ 345/* SH_RTC3_INT_CONFIG_PID */
343/* Description: Processor ID, same setting as on targeted McKinley */ 346/* Description: Processor ID, same setting as on targeted McKinley */
344#define SH_RTC3_INT_CONFIG_PID_SHFT 4 347#define SH_RTC3_INT_CONFIG_PID_SHFT 4
345#define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 348#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
346 349
347/* SH_RTC3_INT_CONFIG_BASE */ 350/* SH_RTC3_INT_CONFIG_BASE */
348/* Description: Optional interrupt vector area, 2MB aligned */ 351/* Description: Optional interrupt vector area, 2MB aligned */
349#define SH_RTC3_INT_CONFIG_BASE_SHFT 21 352#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
350#define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 353#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
351 354
352/* SH_RTC3_INT_CONFIG_IDX */ 355/* SH_RTC3_INT_CONFIG_IDX */
353/* Description: Targeted McKinley interrupt vector */ 356/* Description: Targeted McKinley interrupt vector */
354#define SH_RTC3_INT_CONFIG_IDX_SHFT 52 357#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
355#define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 358#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
356 359
357/* ==================================================================== */ 360/* ==================================================================== */
358/* Register "SH_RTC3_INT_ENABLE" */ 361/* Register "SH_RTC3_INT_ENABLE" */
359/* SHub RTC 3 Interrupt Enable Registers */ 362/* SHub RTC 3 Interrupt Enable Registers */
360/* ==================================================================== */ 363/* ==================================================================== */
361 364
362#define SH1_RTC3_INT_ENABLE 0x0000000110001700 365#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
363#define SH2_RTC3_INT_ENABLE 0x0000000010001700 366#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
364#define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 367#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
365#define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 368#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
366 369
367/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ 370/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
368/* Description: Enable RTC 3 Interrupt */ 371/* Description: Enable RTC 3 Interrupt */
369#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 372#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
370#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 373#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
374 __IA64_UL_CONST(0x0000000000000001)
371 375
372/* SH_EVENT_OCCURRED_RTC1_INT */ 376/* SH_EVENT_OCCURRED_RTC1_INT */
373/* Description: Pending RTC 1 Interrupt */ 377/* Description: Pending RTC 1 Interrupt */
374#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 378#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
375#define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 379#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
376 380
377/* SH_EVENT_OCCURRED_RTC2_INT */ 381/* SH_EVENT_OCCURRED_RTC2_INT */
378/* Description: Pending RTC 2 Interrupt */ 382/* Description: Pending RTC 2 Interrupt */
379#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 383#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
380#define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 384#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
381 385
382/* SH_EVENT_OCCURRED_RTC3_INT */ 386/* SH_EVENT_OCCURRED_RTC3_INT */
383/* Description: Pending RTC 3 Interrupt */ 387/* Description: Pending RTC 3 Interrupt */
384#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 388#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
385#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 389#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
386 390
387/* ==================================================================== */ 391/* ==================================================================== */
388/* Register "SH_IPI_ACCESS" */ 392/* Register "SH_IPI_ACCESS" */
389/* CPU interrupt Access Permission Bits */ 393/* CPU interrupt Access Permission Bits */
390/* ==================================================================== */ 394/* ==================================================================== */
391 395
392#define SH1_IPI_ACCESS 0x0000000110060480 396#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
393#define SH2_IPI_ACCESS0 0x0000000010060c00 397#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
394#define SH2_IPI_ACCESS1 0x0000000010060c80 398#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
395#define SH2_IPI_ACCESS2 0x0000000010060d00 399#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
396#define SH2_IPI_ACCESS3 0x0000000010060d80 400#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
397 401
398/* ==================================================================== */ 402/* ==================================================================== */
399/* Register "SH_INT_CMPB" */ 403/* Register "SH_INT_CMPB" */
400/* RTC Compare Value for Processor B */ 404/* RTC Compare Value for Processor B */
401/* ==================================================================== */ 405/* ==================================================================== */
402 406
403#define SH1_INT_CMPB 0x00000001101b0080 407#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
404#define SH2_INT_CMPB 0x00000000101b0080 408#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
405#define SH_INT_CMPB_MASK 0x007fffffffffffff 409#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
406#define SH_INT_CMPB_INIT 0x0000000000000000 410#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
407 411
408/* SH_INT_CMPB_REAL_TIME_CMPB */ 412/* SH_INT_CMPB_REAL_TIME_CMPB */
409/* Description: Real Time Clock Compare */ 413/* Description: Real Time Clock Compare */
410#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 414#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
411#define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff 415#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
412 416
413/* ==================================================================== */ 417/* ==================================================================== */
414/* Register "SH_INT_CMPC" */ 418/* Register "SH_INT_CMPC" */
415/* RTC Compare Value for Processor C */ 419/* RTC Compare Value for Processor C */
416/* ==================================================================== */ 420/* ==================================================================== */
417 421
418#define SH1_INT_CMPC 0x00000001101b0100 422#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
419#define SH2_INT_CMPC 0x00000000101b0100 423#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
420#define SH_INT_CMPC_MASK 0x007fffffffffffff 424#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
421#define SH_INT_CMPC_INIT 0x0000000000000000 425#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
422 426
423/* SH_INT_CMPC_REAL_TIME_CMPC */ 427/* SH_INT_CMPC_REAL_TIME_CMPC */
424/* Description: Real Time Clock Compare */ 428/* Description: Real Time Clock Compare */
425#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 429#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
426#define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff 430#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
427 431
428/* ==================================================================== */ 432/* ==================================================================== */
429/* Register "SH_INT_CMPD" */ 433/* Register "SH_INT_CMPD" */
430/* RTC Compare Value for Processor D */ 434/* RTC Compare Value for Processor D */
431/* ==================================================================== */ 435/* ==================================================================== */
432 436
433#define SH1_INT_CMPD 0x00000001101b0180 437#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
434#define SH2_INT_CMPD 0x00000000101b0180 438#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
435#define SH_INT_CMPD_MASK 0x007fffffffffffff 439#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
436#define SH_INT_CMPD_INIT 0x0000000000000000 440#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
437 441
438/* SH_INT_CMPD_REAL_TIME_CMPD */ 442/* SH_INT_CMPD_REAL_TIME_CMPD */
439/* Description: Real Time Clock Compare */ 443/* Description: Real Time Clock Compare */
440#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 444#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
441#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff 445#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
442 446
443/* ==================================================================== */ 447/* ==================================================================== */
444/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ 448/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
445/* privilege vector for acc=0 */ 449/* privilege vector for acc=0 */
446/* ==================================================================== */ 450/* ==================================================================== */
447 451#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
448#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300
449 452
450/* ==================================================================== */ 453/* ==================================================================== */
451/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ 454/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
452/* privilege vector for acc=0 */ 455/* privilege vector for acc=0 */
453/* ==================================================================== */ 456/* ==================================================================== */
454 457#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
455#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300
456 458
457/* ==================================================================== */ 459/* ==================================================================== */
458/* Some MMRs are functionally identical (or close enough) on both SHUB1 */ 460/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
@@ -484,17 +486,17 @@
484/* Engine 0 Control and Status Register */ 486/* Engine 0 Control and Status Register */
485/* ========================================================================== */ 487/* ========================================================================== */
486 488
487#define SH2_BT_ENG_CSR_0 0x0000000030040000 489#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
488#define SH2_BT_ENG_SRC_ADDR_0 0x0000000030040080 490#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
489#define SH2_BT_ENG_DEST_ADDR_0 0x0000000030040100 491#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
490#define SH2_BT_ENG_NOTIF_ADDR_0 0x0000000030040180 492#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
491 493
492/* ========================================================================== */ 494/* ========================================================================== */
493/* BTE interfaces 1-3 */ 495/* BTE interfaces 1-3 */
494/* ========================================================================== */ 496/* ========================================================================== */
495 497
496#define SH2_BT_ENG_CSR_1 0x0000000030050000 498#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
497#define SH2_BT_ENG_CSR_2 0x0000000030060000 499#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
498#define SH2_BT_ENG_CSR_3 0x0000000030070000 500#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
499 501
500#endif /* _ASM_IA64_SN_SHUB_MMR_H */ 502#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
index 78eb4f869c8b..cf770e246af5 100644
--- a/include/asm-ia64/sn/simulator.h
+++ b/include/asm-ia64/sn/simulator.h
@@ -10,16 +10,17 @@
10 10
11#include <linux/config.h> 11#include <linux/config.h>
12 12
13#ifdef CONFIG_IA64_SGI_SN_SIM
14
15#define SNMAGIC 0xaeeeeeee8badbeefL 13#define SNMAGIC 0xaeeeeeee8badbeefL
16#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;}) 14#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
17
18#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
19 15
16#ifdef CONFIG_IA64_SGI_SN_SIM
17#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
18#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
19#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
20extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
20#else 21#else
21
22#define IS_RUNNING_ON_SIMULATOR() (0) 22#define IS_RUNNING_ON_SIMULATOR() (0)
23#define IS_RUNNING_ON_FAKE_PROM() (0)
23#define SIMULATOR_SLEEP() 24#define SIMULATOR_SLEEP()
24 25
25#endif 26#endif
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
index b0c4d6dd77ba..df75f4c4aec3 100644
--- a/include/asm-ia64/sn/sn2/sn_hwperf.h
+++ b/include/asm-ia64/sn/sn2/sn_hwperf.h
@@ -223,4 +223,6 @@ struct sn_hwperf_ioctl_args {
223#define SN_HWPERF_OP_RECONFIGURE 253 223#define SN_HWPERF_OP_RECONFIGURE 253
224#define SN_HWPERF_OP_INVAL 254 224#define SN_HWPERF_OP_INVAL 254
225 225
226int sn_topology_open(struct inode *inode, struct file *file);
227int sn_topology_release(struct inode *inode, struct file *file);
226#endif /* SN_HWPERF_H */ 228#endif /* SN_HWPERF_H */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index eb0395ad0d6a..1455375d2ce4 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -132,6 +132,8 @@
132#define SALRET_INVALID_ARG (-2) 132#define SALRET_INVALID_ARG (-2)
133#define SALRET_ERROR (-3) 133#define SALRET_ERROR (-3)
134 134
135#define SN_SAL_FAKE_PROM 0x02009999
136
135 137
136/** 138/**
137 * sn_sal_rev_major - get the major SGI SAL revision number 139 * sn_sal_rev_major - get the major SGI SAL revision number
@@ -1105,4 +1107,12 @@ ia64_sn_bte_recovery(nasid_t nasid)
1105 return (int) rv.status; 1107 return (int) rv.status;
1106} 1108}
1107 1109
1110static inline int
1111ia64_sn_is_fake_prom(void)
1112{
1113 struct ia64_sal_retval rv;
1114 SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
1115 return (rv.status == 0);
1116}
1117
1108#endif /* _ASM_IA64_SN_SN_SAL_H */ 1118#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index b6acc22ab239..5ccec608d325 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -201,6 +201,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
201} 201}
202 202
203extern uint32_t tioca_gart_found; 203extern uint32_t tioca_gart_found;
204extern struct list_head tioca_list;
204extern int tioca_init_provider(void); 205extern int tioca_init_provider(void);
205extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern); 206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
206#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */ 207#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/include/asm-ia64/vga.h b/include/asm-ia64/vga.h
index 1f446d6841f6..bc3349ffc505 100644
--- a/include/asm-ia64/vga.h
+++ b/include/asm-ia64/vga.h
@@ -14,7 +14,10 @@
14 * videoram directly without any black magic. 14 * videoram directly without any black magic.
15 */ 15 */
16 16
17#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0)) 17extern unsigned long vga_console_iobase;
18extern unsigned long vga_console_membase;
19
20#define VGA_MAP_MEM(x) ((unsigned long) ioremap(vga_console_membase + (x), 0))
18 21
19#define vga_readb(x) (*(x)) 22#define vga_readb(x) (*(x))
20#define vga_writeb(x,y) (*(y) = (x)) 23#define vga_writeb(x,y) (*(y) = (x))
diff --git a/include/asm-m68k/serial.h b/include/asm-m68k/serial.h
index 9f5bcdc105fc..3fe29f8b0194 100644
--- a/include/asm-m68k/serial.h
+++ b/include/asm-m68k/serial.h
@@ -26,54 +26,9 @@
26#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 26#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
27#endif 27#endif
28 28
29#ifdef CONFIG_SERIAL_MANY_PORTS 29#define SERIAL_PORT_DFNS \
30#define FOURPORT_FLAGS ASYNC_FOURPORT
31#define ACCENT_FLAGS 0
32#define BOCA_FLAGS 0
33#endif
34
35#define STD_SERIAL_PORT_DEFNS \
36 /* UART CLK PORT IRQ FLAGS */ \ 30 /* UART CLK PORT IRQ FLAGS */ \
37 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 31 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
38 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 32 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
39 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 33 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
40 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 34 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
41
42
43#ifdef CONFIG_SERIAL_MANY_PORTS
44#define EXTRA_SERIAL_PORT_DEFNS \
45 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
46 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
47 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
48 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
49 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
50 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
51 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
52 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
53 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
54 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
55 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
56 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
57 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
58 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
59 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
60 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
61 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
62 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
63 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
64 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
65 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
66 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
67 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
68 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
69 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
70 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
71 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
72 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
73#else
74#define EXTRA_SERIAL_PORT_DEFNS
75#endif
76
77#define SERIAL_PORT_DFNS \
78 STD_SERIAL_PORT_DEFNS \
79 EXTRA_SERIAL_PORT_DEFNS
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c9c576b48556..2d323b6e147d 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -130,6 +130,16 @@ extern void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev,
130extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, 130extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev,
131 dma64_addr_t dma_addr, size_t len, int direction); 131 dma64_addr_t dma_addr, size_t len, int direction);
132 132
133#ifdef CONFIG_PCI
134static inline void pci_dma_burst_advice(struct pci_dev *pdev,
135 enum pci_dma_burst_strategy *strat,
136 unsigned long *strategy_parameter)
137{
138 *strat = PCI_DMA_BURST_INFINITY;
139 *strategy_parameter = ~0UL;
140}
141#endif
142
133extern void pcibios_resource_to_bus(struct pci_dev *dev, 143extern void pcibios_resource_to_bus(struct pci_dev *dev,
134 struct pci_bus_region *region, struct resource *res); 144 struct pci_bus_region *region, struct resource *res);
135 145
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 8a70ff58f760..4eed8e2acdc3 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -29,32 +29,6 @@
29#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 29#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
30#endif 30#endif
31 31
32#ifdef CONFIG_SERIAL_MANY_PORTS
33#define FOURPORT_FLAGS ASYNC_FOURPORT
34#define ACCENT_FLAGS 0
35#define BOCA_FLAGS 0
36#define HUB6_FLAGS 0
37#define RS_TABLE_SIZE 64
38#else
39#define RS_TABLE_SIZE
40#endif
41
42/*
43 * The following define the access methods for the HUB6 card. All
44 * access is through two ports for all 24 possible chips. The card is
45 * selected through the high 2 bits, the port on that card with the
46 * "middle" 3 bits, and the register on that port with the bottom
47 * 3 bits.
48 *
49 * While the access port and interrupt is configurable, the default
50 * port locations are 0x302 for the port control register, and 0x303
51 * for the data read/write register. Normally, the interrupt is at irq3
52 * but can be anything from 3 to 7 inclusive. Note that using 3 will
53 * require disabling com2.
54 */
55
56#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
57
58#ifdef CONFIG_MACH_JAZZ 32#ifdef CONFIG_MACH_JAZZ
59#include <asm/jazz.h> 33#include <asm/jazz.h>
60 34
@@ -240,66 +214,10 @@
240 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 214 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
241 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 215 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
242 216
243#ifdef CONFIG_SERIAL_MANY_PORTS
244#define EXTRA_SERIAL_PORT_DEFNS \
245 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
246 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
247 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
248 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
249 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
250 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
251 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
252 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
253 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
254 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
255 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
256 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
257 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
258 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
259 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
260 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
261 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
262 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
263 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
264 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
265 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
266 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
267 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
268 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
269 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
270 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
271 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
272 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
273#else /* CONFIG_SERIAL_MANY_PORTS */
274#define EXTRA_SERIAL_PORT_DEFNS
275#endif /* CONFIG_SERIAL_MANY_PORTS */
276
277#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ 217#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
278#define STD_SERIAL_PORT_DEFNS 218#define STD_SERIAL_PORT_DEFNS
279#define EXTRA_SERIAL_PORT_DEFNS
280#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ 219#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
281 220
282/* You can have up to four HUB6's in the system, but I've only
283 * included two cards here for a total of twelve ports.
284 */
285#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
286#define HUB6_SERIAL_PORT_DFNS \
287 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
288 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
289 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
290 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
291 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
292 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
293 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
294 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
295 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
296 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
297 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
298 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
299#else
300#define HUB6_SERIAL_PORT_DFNS
301#endif
302
303#ifdef CONFIG_MOMENCO_JAGUAR_ATX 221#ifdef CONFIG_MOMENCO_JAGUAR_ATX
304/* Ordinary NS16552 duart with a 20MHz crystal. */ 222/* Ordinary NS16552 duart with a 20MHz crystal. */
305#define JAGUAR_ATX_UART_CLK 20000000 223#define JAGUAR_ATX_UART_CLK 20000000
@@ -427,8 +345,6 @@
427 COBALT_SERIAL_PORT_DEFNS \ 345 COBALT_SERIAL_PORT_DEFNS \
428 DDB5477_SERIAL_PORT_DEFNS \ 346 DDB5477_SERIAL_PORT_DEFNS \
429 EV96100_SERIAL_PORT_DEFNS \ 347 EV96100_SERIAL_PORT_DEFNS \
430 EXTRA_SERIAL_PORT_DEFNS \
431 HUB6_SERIAL_PORT_DFNS \
432 IP32_SERIAL_PORT_DEFNS \ 348 IP32_SERIAL_PORT_DEFNS \
433 ITE_SERIAL_PORT_DEFNS \ 349 ITE_SERIAL_PORT_DEFNS \
434 IVR_SERIAL_PORT_DEFNS \ 350 IVR_SERIAL_PORT_DEFNS \
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index 0763c2982fb0..ee741c150176 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -230,6 +230,25 @@ extern inline void pcibios_register_hba(struct pci_hba_data *x)
230/* export the pci_ DMA API in terms of the dma_ one */ 230/* export the pci_ DMA API in terms of the dma_ one */
231#include <asm-generic/pci-dma-compat.h> 231#include <asm-generic/pci-dma-compat.h>
232 232
233#ifdef CONFIG_PCI
234static inline void pci_dma_burst_advice(struct pci_dev *pdev,
235 enum pci_dma_burst_strategy *strat,
236 unsigned long *strategy_parameter)
237{
238 unsigned long cacheline_size;
239 u8 byte;
240
241 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
242 if (byte == 0)
243 cacheline_size = 1024;
244 else
245 cacheline_size = (int) byte * 4;
246
247 *strat = PCI_DMA_BURST_MULTIPLE;
248 *strategy_parameter = cacheline_size;
249}
250#endif
251
233extern void 252extern void
234pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 253pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
235 struct resource *res); 254 struct resource *res);
diff --git a/include/asm-parisc/serial.h b/include/asm-parisc/serial.h
index 239c5dcab7e6..82fd820d684f 100644
--- a/include/asm-parisc/serial.h
+++ b/include/asm-parisc/serial.h
@@ -19,18 +19,4 @@
19 * A500 w/ PCI serial cards: 5 + 4 * card ~= 17 19 * A500 w/ PCI serial cards: 5 + 4 * card ~= 17
20 */ 20 */
21 21
22#define STD_SERIAL_PORT_DEFNS \ 22#define SERIAL_PORT_DFNS
23 { 0, }, /* ttyS0 */ \
24 { 0, }, /* ttyS1 */ \
25 { 0, }, /* ttyS2 */ \
26 { 0, }, /* ttyS3 */ \
27 { 0, }, /* ttyS4 */ \
28 { 0, }, /* ttyS5 */ \
29 { 0, }, /* ttyS6 */ \
30 { 0, }, /* ttyS7 */ \
31 { 0, }, /* ttyS8 */
32
33
34#define SERIAL_PORT_DFNS \
35 STD_SERIAL_PORT_DEFNS
36
diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h
index fa9cbb67ce3e..8f994f9f8857 100644
--- a/include/asm-ppc/pc_serial.h
+++ b/include/asm-ppc/pc_serial.h
@@ -35,93 +35,9 @@
35#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 35#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
36#endif 36#endif
37 37
38#ifdef CONFIG_SERIAL_MANY_PORTS 38#define SERIAL_PORT_DFNS \
39#define FOURPORT_FLAGS ASYNC_FOURPORT
40#define ACCENT_FLAGS 0
41#define BOCA_FLAGS 0
42#define HUB6_FLAGS 0
43#endif
44
45/*
46 * The following define the access methods for the HUB6 card. All
47 * access is through two ports for all 24 possible chips. The card is
48 * selected through the high 2 bits, the port on that card with the
49 * "middle" 3 bits, and the register on that port with the bottom
50 * 3 bits.
51 *
52 * While the access port and interrupt is configurable, the default
53 * port locations are 0x302 for the port control register, and 0x303
54 * for the data read/write register. Normally, the interrupt is at irq3
55 * but can be anything from 3 to 7 inclusive. Note that using 3 will
56 * require disabling com2.
57 */
58
59#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
60
61#define STD_SERIAL_PORT_DEFNS \
62 /* UART CLK PORT IRQ FLAGS */ \ 39 /* UART CLK PORT IRQ FLAGS */ \
63 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 40 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
64 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 41 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
65 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 42 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
66 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 43 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
67
68
69#ifdef CONFIG_SERIAL_MANY_PORTS
70#define EXTRA_SERIAL_PORT_DEFNS \
71 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
72 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
73 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
74 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
75 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
76 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
77 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
78 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
79 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
80 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
81 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
82 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
83 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
84 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
85 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
86 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
87 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
88 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
89 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
90 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
91 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
92 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
93 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
94 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
95 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
96 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
97 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
98 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
99#else
100#define EXTRA_SERIAL_PORT_DEFNS
101#endif
102
103/* You can have up to four HUB6's in the system, but I've only
104 * included two cards here for a total of twelve ports.
105 */
106#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
107#define HUB6_SERIAL_PORT_DFNS \
108 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
109 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
110 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
111 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
112 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
113 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
114 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
115 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
116 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
117 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
118 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
119 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
120#else
121#define HUB6_SERIAL_PORT_DFNS
122#endif
123
124#define SERIAL_PORT_DFNS \
125 STD_SERIAL_PORT_DEFNS \
126 EXTRA_SERIAL_PORT_DEFNS \
127 HUB6_SERIAL_PORT_DFNS
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index ce5ae6d048f5..db0a2a0ec74d 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -69,6 +69,16 @@ extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
69#define pci_unmap_len(PTR, LEN_NAME) (0) 69#define pci_unmap_len(PTR, LEN_NAME) (0)
70#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) 70#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
71 71
72#ifdef CONFIG_PCI
73static inline void pci_dma_burst_advice(struct pci_dev *pdev,
74 enum pci_dma_burst_strategy *strat,
75 unsigned long *strategy_parameter)
76{
77 *strat = PCI_DMA_BURST_INFINITY;
78 *strategy_parameter = ~0UL;
79}
80#endif
81
72/* 82/*
73 * At present there are very few 32-bit PPC machines that can have 83 * At present there are very few 32-bit PPC machines that can have
74 * memory above the 4GB point, and we don't support that. 84 * memory above the 4GB point, and we don't support that.
@@ -103,6 +113,12 @@ extern pgprot_t pci_phys_mem_access_prot(struct file *file,
103 unsigned long size, 113 unsigned long size,
104 pgprot_t prot); 114 pgprot_t prot);
105 115
116#define HAVE_ARCH_PCI_RESOURCE_TO_USER
117extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
118 const struct resource *rsrc,
119 u64 *start, u64 *end);
120
121
106#endif /* __KERNEL__ */ 122#endif /* __KERNEL__ */
107 123
108#endif /* __PPC_PCI_H */ 124#endif /* __PPC_PCI_H */
diff --git a/include/asm-ppc64/byteorder.h b/include/asm-ppc64/byteorder.h
index 80327532de64..8b57da62b674 100644
--- a/include/asm-ppc64/byteorder.h
+++ b/include/asm-ppc64/byteorder.h
@@ -40,7 +40,6 @@ static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
40 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); 40 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
41} 41}
42 42
43#if 0
44static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value) 43static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
45{ 44{
46 __u16 result; 45 __u16 result;
@@ -63,17 +62,8 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
63 return result; 62 return result;
64} 63}
65 64
66static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 value)
67{
68 __u64 result;
69#error implement me
70}
71
72#define __arch__swab16(x) ___arch__swab16(x) 65#define __arch__swab16(x) ___arch__swab16(x)
73#define __arch__swab32(x) ___arch__swab32(x) 66#define __arch__swab32(x) ___arch__swab32(x)
74#define __arch__swab64(x) ___arch__swab64(x)
75
76#endif
77 67
78/* The same, but returns converted value from the location pointer by addr. */ 68/* The same, but returns converted value from the location pointer by addr. */
79#define __arch__swab16p(addr) ld_le16(addr) 69#define __arch__swab16p(addr) ld_le16(addr)
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index 6cd593f660a0..d12dfce21e20 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -78,6 +78,25 @@ static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
78 return 0; 78 return 0;
79} 79}
80 80
81#ifdef CONFIG_PCI
82static inline void pci_dma_burst_advice(struct pci_dev *pdev,
83 enum pci_dma_burst_strategy *strat,
84 unsigned long *strategy_parameter)
85{
86 unsigned long cacheline_size;
87 u8 byte;
88
89 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
90 if (byte == 0)
91 cacheline_size = 1024;
92 else
93 cacheline_size = (int) byte * 4;
94
95 *strat = PCI_DMA_BURST_MULTIPLE;
96 *strategy_parameter = cacheline_size;
97}
98#endif
99
81extern int pci_domain_nr(struct pci_bus *bus); 100extern int pci_domain_nr(struct pci_bus *bus);
82 101
83/* Decide whether to display the domain number in /proc */ 102/* Decide whether to display the domain number in /proc */
@@ -136,6 +155,13 @@ extern pgprot_t pci_phys_mem_access_prot(struct file *file,
136 unsigned long size, 155 unsigned long size,
137 pgprot_t prot); 156 pgprot_t prot);
138 157
158#ifdef CONFIG_PPC_MULTIPLATFORM
159#define HAVE_ARCH_PCI_RESOURCE_TO_USER
160extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
161 const struct resource *rsrc,
162 u64 *start, u64 *end);
163#endif /* CONFIG_PPC_MULTIPLATFORM */
164
139 165
140#endif /* __KERNEL__ */ 166#endif /* __KERNEL__ */
141 167
diff --git a/include/asm-sh/bigsur/serial.h b/include/asm-sh/bigsur/serial.h
index 540f12205923..7233af42f755 100644
--- a/include/asm-sh/bigsur/serial.h
+++ b/include/asm-sh/bigsur/serial.h
@@ -14,13 +14,10 @@
14#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) 14#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
15 15
16 16
17#define STD_SERIAL_PORT_DEFNS \ 17#define SERIAL_PORT_DFNS \
18 /* UART CLK PORT IRQ FLAGS */ \ 18 /* UART CLK PORT IRQ FLAGS */ \
19 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ 19 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
20 20
21
22#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
23
24/* XXX: This should be moved ino irq.h */ 21/* XXX: This should be moved ino irq.h */
25#define irq_cannonicalize(x) (x) 22#define irq_cannonicalize(x) (x)
26 23
diff --git a/include/asm-sh/ec3104/serial.h b/include/asm-sh/ec3104/serial.h
index f8eb16312ed9..cfe4d78ec1ee 100644
--- a/include/asm-sh/ec3104/serial.h
+++ b/include/asm-sh/ec3104/serial.h
@@ -10,13 +10,11 @@
10 * it's got the keyboard controller behind it so we can't really use it 10 * it's got the keyboard controller behind it so we can't really use it
11 * (without moving the keyboard driver to userspace, which doesn't sound 11 * (without moving the keyboard driver to userspace, which doesn't sound
12 * like a very good idea) */ 12 * like a very good idea) */
13#define STD_SERIAL_PORT_DEFNS \ 13#define SERIAL_PORT_DFNS \
14 /* UART CLK PORT IRQ FLAGS */ \ 14 /* UART CLK PORT IRQ FLAGS */ \
15 { 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \ 15 { 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \
16 { 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \ 16 { 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \
17 { 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */ 17 { 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */
18 18
19#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
20
21/* XXX: This should be moved ino irq.h */ 19/* XXX: This should be moved ino irq.h */
22#define irq_cannonicalize(x) (x) 20#define irq_cannonicalize(x) (x)
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
index 9c3b63d0105e..26044889c770 100644
--- a/include/asm-sh/pci.h
+++ b/include/asm-sh/pci.h
@@ -96,6 +96,16 @@ static inline void pcibios_penalize_isa_irq(int irq)
96#define sg_dma_address(sg) (virt_to_bus((sg)->dma_address)) 96#define sg_dma_address(sg) (virt_to_bus((sg)->dma_address))
97#define sg_dma_len(sg) ((sg)->length) 97#define sg_dma_len(sg) ((sg)->length)
98 98
99#ifdef CONFIG_PCI
100static inline void pci_dma_burst_advice(struct pci_dev *pdev,
101 enum pci_dma_burst_strategy *strat,
102 unsigned long *strategy_parameter)
103{
104 *strat = PCI_DMA_BURST_INFINITY;
105 *strategy_parameter = ~0UL;
106}
107#endif
108
99/* Board-specific fixup routines. */ 109/* Board-specific fixup routines. */
100extern void pcibios_fixup(void); 110extern void pcibios_fixup(void);
101extern void pcibios_fixup_irqs(void); 111extern void pcibios_fixup_irqs(void);
diff --git a/include/asm-sh/serial.h b/include/asm-sh/serial.h
index 5474dbdbaa86..f51e232d5cd9 100644
--- a/include/asm-sh/serial.h
+++ b/include/asm-sh/serial.h
@@ -29,20 +29,18 @@
29#ifdef CONFIG_HD64465 29#ifdef CONFIG_HD64465
30#include <asm/hd64465.h> 30#include <asm/hd64465.h>
31 31
32#define STD_SERIAL_PORT_DEFNS \ 32#define SERIAL_PORT_DFNS \
33 /* UART CLK PORT IRQ FLAGS */ \ 33 /* UART CLK PORT IRQ FLAGS */ \
34 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ 34 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
35 35
36#else 36#else
37 37
38#define STD_SERIAL_PORT_DEFNS \ 38#define SERIAL_PORT_DFNS \
39 /* UART CLK PORT IRQ FLAGS */ \ 39 /* UART CLK PORT IRQ FLAGS */ \
40 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 40 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
41 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */ 41 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */
42 42
43#endif 43#endif
44 44
45#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
46
47#endif 45#endif
48#endif /* _ASM_SERIAL_H */ 46#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-sh64/pci.h b/include/asm-sh64/pci.h
index 8cc14e139750..c68870e02d91 100644
--- a/include/asm-sh64/pci.h
+++ b/include/asm-sh64/pci.h
@@ -86,6 +86,16 @@ static inline void pcibios_penalize_isa_irq(int irq)
86#define sg_dma_address(sg) ((sg)->dma_address) 86#define sg_dma_address(sg) ((sg)->dma_address)
87#define sg_dma_len(sg) ((sg)->length) 87#define sg_dma_len(sg) ((sg)->length)
88 88
89#ifdef CONFIG_PCI
90static inline void pci_dma_burst_advice(struct pci_dev *pdev,
91 enum pci_dma_burst_strategy *strat,
92 unsigned long *strategy_parameter)
93{
94 *strat = PCI_DMA_BURST_INFINITY;
95 *strategy_parameter = ~0UL;
96}
97#endif
98
89/* Board-specific fixup routines. */ 99/* Board-specific fixup routines. */
90extern void pcibios_fixup(void); 100extern void pcibios_fixup(void);
91extern void pcibios_fixup_irqs(void); 101extern void pcibios_fixup_irqs(void);
diff --git a/include/asm-sh64/serial.h b/include/asm-sh64/serial.h
index 8e39b4e90c76..29c9be15112b 100644
--- a/include/asm-sh64/serial.h
+++ b/include/asm-sh64/serial.h
@@ -20,13 +20,11 @@
20 20
21#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) 21#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
22 22
23#define STD_SERIAL_PORT_DEFNS \ 23#define SERIAL_PORT_DFNS \
24 /* UART CLK PORT IRQ FLAGS */ \ 24 /* UART CLK PORT IRQ FLAGS */ \
25 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 25 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
26 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */ 26 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */
27 27
28#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
29
30/* XXX: This should be moved ino irq.h */ 28/* XXX: This should be moved ino irq.h */
31#define irq_cannonicalize(x) (x) 29#define irq_cannonicalize(x) (x)
32 30
diff --git a/include/asm-sparc/pci.h b/include/asm-sparc/pci.h
index d200a25a7373..44bb38758c96 100644
--- a/include/asm-sparc/pci.h
+++ b/include/asm-sparc/pci.h
@@ -144,6 +144,16 @@ extern inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
144 144
145#define pci_dac_dma_supported(dev, mask) (0) 145#define pci_dac_dma_supported(dev, mask) (0)
146 146
147#ifdef CONFIG_PCI
148static inline void pci_dma_burst_advice(struct pci_dev *pdev,
149 enum pci_dma_burst_strategy *strat,
150 unsigned long *strategy_parameter)
151{
152 *strat = PCI_DMA_BURST_INFINITY;
153 *strategy_parameter = ~0UL;
154}
155#endif
156
147static inline void pcibios_add_platform_entries(struct pci_dev *dev) 157static inline void pcibios_add_platform_entries(struct pci_dev *dev)
148{ 158{
149} 159}
diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h
index 2a0c85cd1c11..84e41c1ef3f8 100644
--- a/include/asm-sparc64/pci.h
+++ b/include/asm-sparc64/pci.h
@@ -220,6 +220,25 @@ static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
220 return (dma_addr == PCI_DMA_ERROR_CODE); 220 return (dma_addr == PCI_DMA_ERROR_CODE);
221} 221}
222 222
223#ifdef CONFIG_PCI
224static inline void pci_dma_burst_advice(struct pci_dev *pdev,
225 enum pci_dma_burst_strategy *strat,
226 unsigned long *strategy_parameter)
227{
228 unsigned long cacheline_size;
229 u8 byte;
230
231 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
232 if (byte == 0)
233 cacheline_size = 1024;
234 else
235 cacheline_size = (int) byte * 4;
236
237 *strat = PCI_DMA_BURST_BOUNDARY;
238 *strategy_parameter = cacheline_size;
239}
240#endif
241
223/* Return the index of the PCI controller for device PDEV. */ 242/* Return the index of the PCI controller for device PDEV. */
224 243
225extern int pci_domain_nr(struct pci_bus *bus); 244extern int pci_domain_nr(struct pci_bus *bus);
diff --git a/include/asm-v850/pci.h b/include/asm-v850/pci.h
index e41941447b49..8e79be0fe99d 100644
--- a/include/asm-v850/pci.h
+++ b/include/asm-v850/pci.h
@@ -81,6 +81,16 @@ extern void
81pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr, 81pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr,
82 dma_addr_t dma_addr); 82 dma_addr_t dma_addr);
83 83
84#ifdef CONFIG_PCI
85static inline void pci_dma_burst_advice(struct pci_dev *pdev,
86 enum pci_dma_burst_strategy *strat,
87 unsigned long *strategy_parameter)
88{
89 *strat = PCI_DMA_BURST_INFINITY;
90 *strategy_parameter = ~0UL;
91}
92#endif
93
84static inline void pcibios_add_platform_entries(struct pci_dev *dev) 94static inline void pcibios_add_platform_entries(struct pci_dev *dev)
85{ 95{
86} 96}
diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h
index 8712520ca47f..c1961db88fac 100644
--- a/include/asm-x86_64/pci.h
+++ b/include/asm-x86_64/pci.h
@@ -123,6 +123,16 @@ pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr,
123 flush_write_buffers(); 123 flush_write_buffers();
124} 124}
125 125
126#ifdef CONFIG_PCI
127static inline void pci_dma_burst_advice(struct pci_dev *pdev,
128 enum pci_dma_burst_strategy *strat,
129 unsigned long *strategy_parameter)
130{
131 *strat = PCI_DMA_BURST_INFINITY;
132 *strategy_parameter = ~0UL;
133}
134#endif
135
126#define HAVE_PCI_MMAP 136#define HAVE_PCI_MMAP
127extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 137extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
128 enum pci_mmap_state mmap_state, int write_combine); 138 enum pci_mmap_state mmap_state, int write_combine);
diff --git a/include/asm-x86_64/serial.h b/include/asm-x86_64/serial.h
index dbab232044cd..dc752eafa681 100644
--- a/include/asm-x86_64/serial.h
+++ b/include/asm-x86_64/serial.h
@@ -22,109 +22,9 @@
22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
23#endif 23#endif
24 24
25#ifdef CONFIG_SERIAL_MANY_PORTS 25#define SERIAL_PORT_DFNS \
26#define FOURPORT_FLAGS ASYNC_FOURPORT
27#define ACCENT_FLAGS 0
28#define BOCA_FLAGS 0
29#define HUB6_FLAGS 0
30#endif
31
32#define MCA_COM_FLAGS (STD_COM_FLAGS|ASYNC_BOOT_ONLYMCA)
33
34/*
35 * The following define the access methods for the HUB6 card. All
36 * access is through two ports for all 24 possible chips. The card is
37 * selected through the high 2 bits, the port on that card with the
38 * "middle" 3 bits, and the register on that port with the bottom
39 * 3 bits.
40 *
41 * While the access port and interrupt is configurable, the default
42 * port locations are 0x302 for the port control register, and 0x303
43 * for the data read/write register. Normally, the interrupt is at irq3
44 * but can be anything from 3 to 7 inclusive. Note that using 3 will
45 * require disabling com2.
46 */
47
48#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
49
50#define STD_SERIAL_PORT_DEFNS \
51 /* UART CLK PORT IRQ FLAGS */ \ 26 /* UART CLK PORT IRQ FLAGS */ \
52 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 27 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
53 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 28 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
54 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 29 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
55 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 30 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
56
57
58#ifdef CONFIG_SERIAL_MANY_PORTS
59#define EXTRA_SERIAL_PORT_DEFNS \
60 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
61 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
62 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
63 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
64 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
65 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
66 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
67 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
68 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
69 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
70 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
71 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
72 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
73 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
74 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
75 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
76 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
77 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
78 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
79 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
80 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
81 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
82 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
83 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
84 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
85 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
86 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
87 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
88#else
89#define EXTRA_SERIAL_PORT_DEFNS
90#endif
91
92/* You can have up to four HUB6's in the system, but I've only
93 * included two cards here for a total of twelve ports.
94 */
95#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
96#define HUB6_SERIAL_PORT_DFNS \
97 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
98 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
99 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
100 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
101 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
102 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
103 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
104 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
105 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
106 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
107 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
108 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
109#else
110#define HUB6_SERIAL_PORT_DFNS
111#endif
112
113#ifdef CONFIG_MCA
114#define MCA_SERIAL_PORT_DFNS \
115 { 0, BASE_BAUD, 0x3220, 3, MCA_COM_FLAGS }, \
116 { 0, BASE_BAUD, 0x3228, 3, MCA_COM_FLAGS }, \
117 { 0, BASE_BAUD, 0x4220, 3, MCA_COM_FLAGS }, \
118 { 0, BASE_BAUD, 0x4228, 3, MCA_COM_FLAGS }, \
119 { 0, BASE_BAUD, 0x5220, 3, MCA_COM_FLAGS }, \
120 { 0, BASE_BAUD, 0x5228, 3, MCA_COM_FLAGS },
121#else
122#define MCA_SERIAL_PORT_DFNS
123#endif
124
125#define SERIAL_PORT_DFNS \
126 STD_SERIAL_PORT_DEFNS \
127 EXTRA_SERIAL_PORT_DEFNS \
128 HUB6_SERIAL_PORT_DFNS \
129 MCA_SERIAL_PORT_DFNS
130
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index b123cc08773d..ef8483673aa3 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -342,11 +342,19 @@ struct acpi_table_ecdt {
342 342
343/* PCI MMCONFIG */ 343/* PCI MMCONFIG */
344 344
345/* Defined in PCI Firmware Specification 3.0 */
346struct acpi_table_mcfg_config {
347 u32 base_address;
348 u32 base_reserved;
349 u16 pci_segment_group_number;
350 u8 start_bus_number;
351 u8 end_bus_number;
352 u8 reserved[4];
353} __attribute__ ((packed));
345struct acpi_table_mcfg { 354struct acpi_table_mcfg {
346 struct acpi_table_header header; 355 struct acpi_table_header header;
347 u8 reserved[8]; 356 u8 reserved[8];
348 u32 base_address; 357 struct acpi_table_mcfg_config config[0];
349 u32 base_reserved;
350} __attribute__ ((packed)); 358} __attribute__ ((packed));
351 359
352/* Table Handlers */ 360/* Table Handlers */
@@ -391,6 +399,7 @@ int acpi_table_parse (enum acpi_table_id id, acpi_table_handler handler);
391int acpi_get_table_header_early (enum acpi_table_id id, struct acpi_table_header **header); 399int acpi_get_table_header_early (enum acpi_table_id id, struct acpi_table_header **header);
392int acpi_table_parse_madt (enum acpi_madt_entry_id id, acpi_madt_entry_handler handler, unsigned int max_entries); 400int acpi_table_parse_madt (enum acpi_madt_entry_id id, acpi_madt_entry_handler handler, unsigned int max_entries);
393int acpi_table_parse_srat (enum acpi_srat_entry_id id, acpi_madt_entry_handler handler, unsigned int max_entries); 401int acpi_table_parse_srat (enum acpi_srat_entry_id id, acpi_madt_entry_handler handler, unsigned int max_entries);
402int acpi_parse_mcfg (unsigned long phys_addr, unsigned long size);
394void acpi_table_print (struct acpi_table_header *header, unsigned long phys_addr); 403void acpi_table_print (struct acpi_table_header *header, unsigned long phys_addr);
395void acpi_table_print_madt_entry (acpi_table_entry_header *madt); 404void acpi_table_print_madt_entry (acpi_table_entry_header *madt);
396void acpi_table_print_srat_entry (acpi_table_entry_header *srat); 405void acpi_table_print_srat_entry (acpi_table_entry_header *srat);
@@ -407,9 +416,13 @@ int acpi_map_lsapic(acpi_handle handle, int *pcpu);
407int acpi_unmap_lsapic(int cpu); 416int acpi_unmap_lsapic(int cpu);
408#endif /* CONFIG_ACPI_HOTPLUG_CPU */ 417#endif /* CONFIG_ACPI_HOTPLUG_CPU */
409 418
419int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base);
420int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base);
421
410extern int acpi_mp_config; 422extern int acpi_mp_config;
411 423
412extern u32 pci_mmcfg_base_addr; 424extern struct acpi_table_mcfg_config *pci_mmcfg_config;
425extern int pci_mmcfg_config_num;
413 426
414extern int sbf_port ; 427extern int sbf_port ;
415 428
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 21a8674cd149..0881b5cdee3d 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -96,6 +96,7 @@ struct io_context {
96 96
97void put_io_context(struct io_context *ioc); 97void put_io_context(struct io_context *ioc);
98void exit_io_context(void); 98void exit_io_context(void);
99struct io_context *current_io_context(int gfp_flags);
99struct io_context *get_io_context(int gfp_flags); 100struct io_context *get_io_context(int gfp_flags);
100void copy_io_context(struct io_context **pdst, struct io_context **psrc); 101void copy_io_context(struct io_context **pdst, struct io_context **psrc);
101void swap_io_context(struct io_context **ioc1, struct io_context **ioc2); 102void swap_io_context(struct io_context **ioc1, struct io_context **ioc2);
diff --git a/include/linux/byteorder/swabb.h b/include/linux/byteorder/swabb.h
index d28d9a804d3b..d5f2a3205109 100644
--- a/include/linux/byteorder/swabb.h
+++ b/include/linux/byteorder/swabb.h
@@ -92,29 +92,32 @@
92#endif /* OPTIMIZE */ 92#endif /* OPTIMIZE */
93 93
94 94
95static __inline__ __const__ __u32 __fswahw32(__u32 x) 95static inline __u32 __fswahw32(__u32 x)
96{ 96{
97 return __arch__swahw32(x); 97 return __arch__swahw32(x);
98} 98}
99static __inline__ __u32 __swahw32p(__u32 *x) 99
100static inline __u32 __swahw32p(__u32 *x)
100{ 101{
101 return __arch__swahw32p(x); 102 return __arch__swahw32p(x);
102} 103}
103static __inline__ void __swahw32s(__u32 *addr) 104
105static inline void __swahw32s(__u32 *addr)
104{ 106{
105 __arch__swahw32s(addr); 107 __arch__swahw32s(addr);
106} 108}
107 109
108 110static inline __u32 __fswahb32(__u32 x)
109static __inline__ __const__ __u32 __fswahb32(__u32 x)
110{ 111{
111 return __arch__swahb32(x); 112 return __arch__swahb32(x);
112} 113}
113static __inline__ __u32 __swahb32p(__u32 *x) 114
115static inline __u32 __swahb32p(__u32 *x)
114{ 116{
115 return __arch__swahb32p(x); 117 return __arch__swahb32p(x);
116} 118}
117static __inline__ void __swahb32s(__u32 *addr) 119
120static inline void __swahb32s(__u32 *addr)
118{ 121{
119 __arch__swahb32s(addr); 122 __arch__swahb32s(addr);
120} 123}
diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h
index ae588aab21b6..a6626dac6e3f 100644
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -25,6 +25,7 @@
25#define _LINUX_ETHERDEVICE_H 25#define _LINUX_ETHERDEVICE_H
26 26
27#include <linux/if_ether.h> 27#include <linux/if_ether.h>
28#include <linux/netdevice.h>
28#include <linux/random.h> 29#include <linux/random.h>
29 30
30#ifdef __KERNEL__ 31#ifdef __KERNEL__
diff --git a/include/linux/i2c-dev.h b/include/linux/i2c-dev.h
index d228230ffe5d..541695679762 100644
--- a/include/linux/i2c-dev.h
+++ b/include/linux/i2c-dev.h
@@ -25,6 +25,7 @@
25#define _LINUX_I2C_DEV_H 25#define _LINUX_I2C_DEV_H
26 26
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/compiler.h>
28 29
29/* Some IOCTL commands are defined in <linux/i2c.h> */ 30/* Some IOCTL commands are defined in <linux/i2c.h> */
30/* Note: 10-bit addresses are NOT supported! */ 31/* Note: 10-bit addresses are NOT supported! */
diff --git a/include/linux/in6.h b/include/linux/in6.h
index f8256c582845..dcf5720ffcbb 100644
--- a/include/linux/in6.h
+++ b/include/linux/in6.h
@@ -156,7 +156,7 @@ struct in6_flowlabel_req
156#define IPV6_CHECKSUM 7 156#define IPV6_CHECKSUM 7
157#define IPV6_HOPLIMIT 8 157#define IPV6_HOPLIMIT 8
158#define IPV6_NEXTHOP 9 158#define IPV6_NEXTHOP 9
159#define IPV6_AUTHHDR 10 159#define IPV6_AUTHHDR 10 /* obsolete */
160#define IPV6_FLOWINFO 11 160#define IPV6_FLOWINFO 11
161 161
162#define IPV6_UNICAST_HOPS 16 162#define IPV6_UNICAST_HOPS 16
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 12277799c007..069d3b84d311 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -85,9 +85,10 @@ extern int no_irq_affinity;
85extern int noirqdebug_setup(char *str); 85extern int noirqdebug_setup(char *str);
86 86
87extern fastcall int handle_IRQ_event(unsigned int irq, struct pt_regs *regs, 87extern fastcall int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
88 struct irqaction *action); 88 struct irqaction *action);
89extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs); 89extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);
90extern void note_interrupt(unsigned int irq, irq_desc_t *desc, int action_ret); 90extern void note_interrupt(unsigned int irq, irq_desc_t *desc,
91 int action_ret, struct pt_regs *regs);
91extern int can_request_irq(unsigned int irq, unsigned long irqflags); 92extern int can_request_irq(unsigned int irq, unsigned long irqflags);
92 93
93extern void init_irq_proc(void); 94extern void init_irq_proc(void);
diff --git a/include/linux/netlink.h b/include/linux/netlink.h
index 3029cad63a01..27e4d164a108 100644
--- a/include/linux/netlink.h
+++ b/include/linux/netlink.h
@@ -168,6 +168,7 @@ __nlmsg_put(struct sk_buff *skb, u32 pid, u32 seq, int type, int len, int flags)
168 nlh->nlmsg_flags = flags; 168 nlh->nlmsg_flags = flags;
169 nlh->nlmsg_pid = pid; 169 nlh->nlmsg_pid = pid;
170 nlh->nlmsg_seq = seq; 170 nlh->nlmsg_seq = seq;
171 memset(NLMSG_DATA(nlh) + len, 0, NLMSG_ALIGN(size) - size);
171 return nlh; 172 return nlh;
172} 173}
173 174
diff --git a/include/linux/pci.h b/include/linux/pci.h
index b5238bd18830..66798b46f308 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -734,16 +734,20 @@ void pcibios_update_irq(struct pci_dev *, int irq);
734/* Generic PCI functions used internally */ 734/* Generic PCI functions used internally */
735 735
736extern struct pci_bus *pci_find_bus(int domain, int busnr); 736extern struct pci_bus *pci_find_bus(int domain, int busnr);
737void pci_bus_add_devices(struct pci_bus *bus);
737struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata); 738struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
738static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata) 739static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
739{ 740{
740 return pci_scan_bus_parented(NULL, bus, ops, sysdata); 741 struct pci_bus *root_bus;
742 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
743 if (root_bus)
744 pci_bus_add_devices(root_bus);
745 return root_bus;
741} 746}
742int pci_scan_slot(struct pci_bus *bus, int devfn); 747int pci_scan_slot(struct pci_bus *bus, int devfn);
743struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn); 748struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
744unsigned int pci_scan_child_bus(struct pci_bus *bus); 749unsigned int pci_scan_child_bus(struct pci_bus *bus);
745void pci_bus_add_device(struct pci_dev *dev); 750void pci_bus_add_device(struct pci_dev *dev);
746void pci_bus_add_devices(struct pci_bus *bus);
747void pci_name_device(struct pci_dev *dev); 751void pci_name_device(struct pci_dev *dev);
748char *pci_class_name(u32 class); 752char *pci_class_name(u32 class);
749void pci_read_bridge_bases(struct pci_bus *child); 753void pci_read_bridge_bases(struct pci_bus *child);
@@ -870,6 +874,15 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass
870#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 874#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
871#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 875#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
872 876
877enum pci_dma_burst_strategy {
878 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
879 strategy_parameter is N/A */
880 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
881 byte boundaries */
882 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
883 strategy_parameter byte boundaries */
884};
885
873#if defined(CONFIG_ISA) || defined(CONFIG_EISA) 886#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
874extern struct pci_dev *isa_bridge; 887extern struct pci_dev *isa_bridge;
875#endif 888#endif
@@ -972,6 +985,8 @@ static inline int pci_proc_domain(struct pci_bus *bus)
972} 985}
973#endif 986#endif
974 987
988#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
989
975#endif /* !CONFIG_PCI */ 990#endif /* !CONFIG_PCI */
976 991
977/* these helpers provide future and backwards compatibility 992/* these helpers provide future and backwards compatibility
@@ -1016,6 +1031,20 @@ static inline char *pci_name(struct pci_dev *pdev)
1016#define pci_pretty_name(dev) "" 1031#define pci_pretty_name(dev) ""
1017#endif 1032#endif
1018 1033
1034
1035/* Some archs don't want to expose struct resource to userland as-is
1036 * in sysfs and /proc
1037 */
1038#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1039static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1040 const struct resource *rsrc, u64 *start, u64 *end)
1041{
1042 *start = rsrc->start;
1043 *end = rsrc->end;
1044}
1045#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1046
1047
1019/* 1048/*
1020 * The world is not perfect and supplies us with broken PCI devices. 1049 * The world is not perfect and supplies us with broken PCI devices.
1021 * For at least a part of these bugs we need a work-around, so both 1050 * For at least a part of these bugs we need a work-around, so both
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1e0bc6a8d653..c3ee1ae4545a 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -62,6 +62,8 @@
62 62
63#define PCI_BASE_CLASS_SYSTEM 0x08 63#define PCI_BASE_CLASS_SYSTEM 0x08
64#define PCI_CLASS_SYSTEM_PIC 0x0800 64#define PCI_CLASS_SYSTEM_PIC 0x0800
65#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010
66#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020
65#define PCI_CLASS_SYSTEM_DMA 0x0801 67#define PCI_CLASS_SYSTEM_DMA 0x0801
66#define PCI_CLASS_SYSTEM_TIMER 0x0802 68#define PCI_CLASS_SYSTEM_TIMER 0x0802
67#define PCI_CLASS_SYSTEM_RTC 0x0803 69#define PCI_CLASS_SYSTEM_RTC 0x0803
diff --git a/include/linux/pkt_cls.h b/include/linux/pkt_cls.h
index 25d2d67c1faf..bd2c5a2bbbf5 100644
--- a/include/linux/pkt_cls.h
+++ b/include/linux/pkt_cls.h
@@ -276,6 +276,7 @@ struct tc_rsvp_pinfo
276 __u8 protocol; 276 __u8 protocol;
277 __u8 tunnelid; 277 __u8 tunnelid;
278 __u8 tunnelhdr; 278 __u8 tunnelhdr;
279 __u8 pad;
279}; 280};
280 281
281/* ROUTE filter */ 282/* ROUTE filter */
diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h
index 1d9da36eb9db..60ffcb9c5791 100644
--- a/include/linux/pkt_sched.h
+++ b/include/linux/pkt_sched.h
@@ -221,9 +221,11 @@ struct tc_gred_qopt
221/* gred setup */ 221/* gred setup */
222struct tc_gred_sopt 222struct tc_gred_sopt
223{ 223{
224 __u32 DPs; 224 __u32 DPs;
225 __u32 def_DP; 225 __u32 def_DP;
226 __u8 grio; 226 __u8 grio;
227 __u8 pad1;
228 __u16 pad2;
227}; 229};
228 230
229/* HTB section */ 231/* HTB section */
@@ -351,6 +353,7 @@ struct tc_cbq_ovl
351#define TC_CBQ_OVL_DROP 3 353#define TC_CBQ_OVL_DROP 3
352#define TC_CBQ_OVL_RCLASSIC 4 354#define TC_CBQ_OVL_RCLASSIC 4
353 unsigned char priority2; 355 unsigned char priority2;
356 __u16 pad;
354 __u32 penalty; 357 __u32 penalty;
355}; 358};
356 359
diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h
index d021888b58f1..657c05ab8f9e 100644
--- a/include/linux/rtnetlink.h
+++ b/include/linux/rtnetlink.h
@@ -363,6 +363,8 @@ enum
363struct rta_session 363struct rta_session
364{ 364{
365 __u8 proto; 365 __u8 proto;
366 __u8 pad1;
367 __u16 pad2;
366 368
367 union { 369 union {
368 struct { 370 struct {
@@ -635,10 +637,13 @@ struct ifinfomsg
635struct prefixmsg 637struct prefixmsg
636{ 638{
637 unsigned char prefix_family; 639 unsigned char prefix_family;
640 unsigned char prefix_pad1;
641 unsigned short prefix_pad2;
638 int prefix_ifindex; 642 int prefix_ifindex;
639 unsigned char prefix_type; 643 unsigned char prefix_type;
640 unsigned char prefix_len; 644 unsigned char prefix_len;
641 unsigned char prefix_flags; 645 unsigned char prefix_flags;
646 unsigned char prefix_pad3;
642}; 647};
643 648
644enum 649enum
@@ -898,7 +903,9 @@ extern void __rta_fill(struct sk_buff *skb, int attrtype, int attrlen, const voi
898 memcpy(skb_put(skb, attrlen), data, attrlen); }) 903 memcpy(skb_put(skb, attrlen), data, attrlen); })
899 904
900#define RTA_PUT_NOHDR(skb, attrlen, data) \ 905#define RTA_PUT_NOHDR(skb, attrlen, data) \
901 RTA_APPEND(skb, RTA_ALIGN(attrlen), data) 906({ RTA_APPEND(skb, RTA_ALIGN(attrlen), data); \
907 memset(skb->tail - (RTA_ALIGN(attrlen) - attrlen), 0, \
908 RTA_ALIGN(attrlen) - attrlen); })
902 909
903#define RTA_PUT_U8(skb, attrtype, value) \ 910#define RTA_PUT_U8(skb, attrtype, value) \
904({ u8 _tmp = (value); \ 911({ u8 _tmp = (value); \
@@ -978,6 +985,7 @@ __rta_reserve(struct sk_buff *skb, int attrtype, int attrlen)
978 rta = (struct rtattr*)skb_put(skb, RTA_ALIGN(size)); 985 rta = (struct rtattr*)skb_put(skb, RTA_ALIGN(size));
979 rta->rta_type = attrtype; 986 rta->rta_type = attrtype;
980 rta->rta_len = size; 987 rta->rta_len = size;
988 memset(RTA_DATA(rta) + attrlen, 0, RTA_ALIGN(size) - size);
981 return rta; 989 return rta;
982} 990}
983 991
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index ebfe1250f0a4..5b5f434ac9a0 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -641,6 +641,7 @@ enum {
641 NET_SCTP_ADDIP_ENABLE = 13, 641 NET_SCTP_ADDIP_ENABLE = 13,
642 NET_SCTP_PRSCTP_ENABLE = 14, 642 NET_SCTP_PRSCTP_ENABLE = 14,
643 NET_SCTP_SNDBUF_POLICY = 15, 643 NET_SCTP_SNDBUF_POLICY = 15,
644 NET_SCTP_SACK_TIMEOUT = 16,
644}; 645};
645 646
646/* /proc/sys/net/bridge */ 647/* /proc/sys/net/bridge */
diff --git a/include/linux/usb_ch9.h b/include/linux/usb_ch9.h
index 39e7ff4ffd28..ee21e6bf3867 100644
--- a/include/linux/usb_ch9.h
+++ b/include/linux/usb_ch9.h
@@ -19,7 +19,7 @@
19#ifndef __LINUX_USB_CH9_H 19#ifndef __LINUX_USB_CH9_H
20#define __LINUX_USB_CH9_H 20#define __LINUX_USB_CH9_H
21 21
22#include <asm/types.h> /* __u8 etc */ 22#include <linux/types.h> /* __u8 etc */
23 23
24/*-------------------------------------------------------------------------*/ 24/*-------------------------------------------------------------------------*/
25 25
@@ -294,8 +294,8 @@ struct usb_endpoint_descriptor {
294 __le16 wMaxPacketSize; 294 __le16 wMaxPacketSize;
295 __u8 bInterval; 295 __u8 bInterval;
296 296
297 // NOTE: these two are _only_ in audio endpoints. 297 /* NOTE: these two are _only_ in audio endpoints. */
298 // use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. 298 /* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */
299 __u8 bRefresh; 299 __u8 bRefresh;
300 __u8 bSynchAddress; 300 __u8 bSynchAddress;
301} __attribute__ ((packed)); 301} __attribute__ ((packed));
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 4e0edce53760..acbfc525576d 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -221,6 +221,8 @@ struct v4l2_pix_format
221/* Vendor-specific formats */ 221/* Vendor-specific formats */
222#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W','N','V','A') /* Winnov hw compress */ 222#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W','N','V','A') /* Winnov hw compress */
223#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S','9','1','0') /* SN9C10x compression */ 223#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S','9','1','0') /* SN9C10x compression */
224#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P','W','C','1') /* pwc older webcam */
225#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P','W','C','2') /* pwc newer webcam */
224 226
225/* 227/*
226 * F O R M A T E N U M E R A T I O N 228 * F O R M A T E N U M E R A T I O N
diff --git a/include/linux/writeback.h b/include/linux/writeback.h
index d5c3fe1bf33d..542dbaee6512 100644
--- a/include/linux/writeback.h
+++ b/include/linux/writeback.h
@@ -85,7 +85,7 @@ static inline void wait_on_inode(struct inode *inode)
85/* 85/*
86 * mm/page-writeback.c 86 * mm/page-writeback.c
87 */ 87 */
88int wakeup_bdflush(long nr_pages); 88int wakeup_pdflush(long nr_pages);
89void laptop_io_completion(void); 89void laptop_io_completion(void);
90void laptop_sync_completion(void); 90void laptop_sync_completion(void);
91void throttle_vm_writeout(void); 91void throttle_vm_writeout(void);
diff --git a/include/linux/xattr_acl.h b/include/linux/xattr_acl.h
deleted file mode 100644
index 7a1f9b93a45f..000000000000
--- a/include/linux/xattr_acl.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 File: linux/xattr_acl.h
3
4 (extended attribute representation of access control lists)
5
6 (C) 2000 Andreas Gruenbacher, <a.gruenbacher@computer.org>
7*/
8
9#ifndef _LINUX_XATTR_ACL_H
10#define _LINUX_XATTR_ACL_H
11
12#include <linux/posix_acl.h>
13
14#define XATTR_NAME_ACL_ACCESS "system.posix_acl_access"
15#define XATTR_NAME_ACL_DEFAULT "system.posix_acl_default"
16
17#define XATTR_ACL_VERSION 0x0002
18
19typedef struct {
20 __u16 e_tag;
21 __u16 e_perm;
22 __u32 e_id;
23} xattr_acl_entry;
24
25typedef struct {
26 __u32 a_version;
27 xattr_acl_entry a_entries[0];
28} xattr_acl_header;
29
30static inline size_t xattr_acl_size(int count)
31{
32 return sizeof(xattr_acl_header) + count * sizeof(xattr_acl_entry);
33}
34
35static inline int xattr_acl_count(size_t size)
36{
37 if (size < sizeof(xattr_acl_header))
38 return -1;
39 size -= sizeof(xattr_acl_header);
40 if (size % sizeof(xattr_acl_entry))
41 return -1;
42 return size / sizeof(xattr_acl_entry);
43}
44
45struct posix_acl * posix_acl_from_xattr(const void *value, size_t size);
46int posix_acl_to_xattr(const struct posix_acl *acl, void *buffer, size_t size);
47
48
49
50#endif /* _LINUX_XATTR_ACL_H */
diff --git a/include/media/tuner.h b/include/media/tuner.h
index 2dd8310901e8..4794c5632360 100644
--- a/include/media/tuner.h
+++ b/include/media/tuner.h
@@ -1,5 +1,6 @@
1 1
2/* 2/* $Id: tuner.h,v 1.33 2005/06/21 14:58:08 mkrufky Exp $
3 *
3 tuner.h - definition for different tuners 4 tuner.h - definition for different tuners
4 5
5 Copyright (C) 1997 Markus Schroeder (schroedm@uni-duesseldorf.de) 6 Copyright (C) 1997 Markus Schroeder (schroedm@uni-duesseldorf.de)
@@ -23,6 +24,8 @@
23#ifndef _TUNER_H 24#ifndef _TUNER_H
24#define _TUNER_H 25#define _TUNER_H
25 26
27#include <linux/videodev2.h>
28
26#include "id.h" 29#include "id.h"
27 30
28#define ADDR_UNSET (255) 31#define ADDR_UNSET (255)
@@ -88,7 +91,7 @@
88#define TUNER_LG_NTSC_TAPE 47 91#define TUNER_LG_NTSC_TAPE 47
89 92
90#define TUNER_TNF_8831BGFF 48 93#define TUNER_TNF_8831BGFF 48
91#define TUNER_MICROTUNE_4042FI5 49 /* FusionHDTV 3 Gold - 4042 FI5 (3X 8147) */ 94#define TUNER_MICROTUNE_4042FI5 49 /* DViCO FusionHDTV 3 Gold-Q - 4042 FI5 (3X 8147) */
92#define TUNER_TCL_2002N 50 95#define TUNER_TCL_2002N 50
93#define TUNER_PHILIPS_FM1256_IH3 51 96#define TUNER_PHILIPS_FM1256_IH3 51
94 97
@@ -98,18 +101,18 @@
98#define TUNER_LG_PAL_TAPE 55 /* Hauppauge PVR-150 PAL */ 101#define TUNER_LG_PAL_TAPE 55 /* Hauppauge PVR-150 PAL */
99 102
100#define TUNER_PHILIPS_FQ1216AME_MK4 56 /* Hauppauge PVR-150 PAL */ 103#define TUNER_PHILIPS_FQ1216AME_MK4 56 /* Hauppauge PVR-150 PAL */
101#define TUNER_PHILIPS_FQ1236A_MK4 57 /* Hauppauge PVR-500MCE NTSC */ 104#define TUNER_PHILIPS_FQ1236A_MK4 57 /* Hauppauge PVR-500MCE NTSC */
102 105
103#define TUNER_YMEC_TVF_8531MF 58 106#define TUNER_YMEC_TVF_8531MF 58
104#define TUNER_YMEC_TVF_5533MF 59 /* Pixelview Pro Ultra NTSC */ 107#define TUNER_YMEC_TVF_5533MF 59 /* Pixelview Pro Ultra NTSC */
105#define TUNER_THOMSON_DTT7611 60 108#define TUNER_THOMSON_DTT7611 60 /* DViCO FusionHDTV 3 Gold-T */
106#define TUNER_TENA_9533_DI 61 109#define TUNER_TENA_9533_DI 61
110
107#define TUNER_TEA5767 62 /* Only FM Radio Tuner */ 111#define TUNER_TEA5767 62 /* Only FM Radio Tuner */
112#define TUNER_PHILIPS_FMD1216ME_MK3 63
108 113
109#define TEA5767_TUNER_NAME "Philips TEA5767HN FM Radio" 114#define TEA5767_TUNER_NAME "Philips TEA5767HN FM Radio"
110 115
111#define TUNER_THOMSON_DTT7611 60
112
113#define NOTUNER 0 116#define NOTUNER 0
114#define PAL 1 /* PAL_BG */ 117#define PAL 1 /* PAL_BG */
115#define PAL_I 2 118#define PAL_I 2
@@ -194,11 +197,15 @@ struct tuner {
194 unsigned char i2c_easy_mode[2]; 197 unsigned char i2c_easy_mode[2];
195 unsigned char i2c_set_freq[8]; 198 unsigned char i2c_set_freq[8];
196 199
200 /* used to keep track of audmode */
201 unsigned int audmode;
202
197 /* function ptrs */ 203 /* function ptrs */
198 void (*tv_freq)(struct i2c_client *c, unsigned int freq); 204 void (*tv_freq)(struct i2c_client *c, unsigned int freq);
199 void (*radio_freq)(struct i2c_client *c, unsigned int freq); 205 void (*radio_freq)(struct i2c_client *c, unsigned int freq);
200 int (*has_signal)(struct i2c_client *c); 206 int (*has_signal)(struct i2c_client *c);
201 int (*is_stereo)(struct i2c_client *c); 207 int (*is_stereo)(struct i2c_client *c);
208 int (*set_tuner)(struct i2c_client *c, struct v4l2_tuner *v);
202}; 209};
203 210
204extern unsigned int tuner_debug; 211extern unsigned int tuner_debug;
@@ -206,6 +213,7 @@ extern unsigned const int tuner_count;
206 213
207extern int microtune_init(struct i2c_client *c); 214extern int microtune_init(struct i2c_client *c);
208extern int tda8290_init(struct i2c_client *c); 215extern int tda8290_init(struct i2c_client *c);
216extern int tea5767_tuner_init(struct i2c_client *c);
209extern int default_tuner_init(struct i2c_client *c); 217extern int default_tuner_init(struct i2c_client *c);
210 218
211#define tuner_warn(fmt, arg...) \ 219#define tuner_warn(fmt, arg...) \
diff --git a/include/net/ipv6.h b/include/net/ipv6.h
index 771b47e30f86..69324465e8b3 100644
--- a/include/net/ipv6.h
+++ b/include/net/ipv6.h
@@ -183,7 +183,6 @@ struct ipv6_txoptions
183 struct ipv6_opt_hdr *hopopt; 183 struct ipv6_opt_hdr *hopopt;
184 struct ipv6_opt_hdr *dst0opt; 184 struct ipv6_opt_hdr *dst0opt;
185 struct ipv6_rt_hdr *srcrt; /* Routing Header */ 185 struct ipv6_rt_hdr *srcrt; /* Routing Header */
186 struct ipv6_opt_hdr *auth;
187 struct ipv6_opt_hdr *dst1opt; 186 struct ipv6_opt_hdr *dst1opt;
188 187
189 /* Option buffer, as read by IPV6_PKTOPTIONS, starts here. */ 188 /* Option buffer, as read by IPV6_PKTOPTIONS, starts here. */
diff --git a/include/net/sctp/constants.h b/include/net/sctp/constants.h
index 4868c7f7749d..5999e5684bbf 100644
--- a/include/net/sctp/constants.h
+++ b/include/net/sctp/constants.h
@@ -263,23 +263,11 @@ enum { SCTP_MIN_PMTU = 576 };
263enum { SCTP_MAX_DUP_TSNS = 16 }; 263enum { SCTP_MAX_DUP_TSNS = 16 };
264enum { SCTP_MAX_GABS = 16 }; 264enum { SCTP_MAX_GABS = 16 };
265 265
266/* Here we define the default timers. */ 266/* Heartbeat interval - 30 secs */
267#define SCTP_DEFAULT_TIMEOUT_HEARTBEAT (30 * HZ)
267 268
268/* cookie timer def = ? seconds */ 269/* Delayed sack timer - 200ms */
269#define SCTP_DEFAULT_TIMEOUT_T1_COOKIE (3 * HZ)
270
271/* init timer def = 3 seconds */
272#define SCTP_DEFAULT_TIMEOUT_T1_INIT (3 * HZ)
273
274/* shutdown timer def = 300 ms */
275#define SCTP_DEFAULT_TIMEOUT_T2_SHUTDOWN ((300 * HZ) / 1000)
276
277/* 0 seconds + RTO */
278#define SCTP_DEFAULT_TIMEOUT_HEARTBEAT (10 * HZ)
279
280/* recv timer def = 200ms (in usec) */
281#define SCTP_DEFAULT_TIMEOUT_SACK ((200 * HZ) / 1000) 270#define SCTP_DEFAULT_TIMEOUT_SACK ((200 * HZ) / 1000)
282#define SCTP_DEFAULT_TIMEOUT_SACK_MAX ((500 * HZ) / 1000) /* 500 ms */
283 271
284/* RTO.Initial - 3 seconds 272/* RTO.Initial - 3 seconds
285 * RTO.Min - 1 second 273 * RTO.Min - 1 second
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index dfad4d3c581c..47727c7cc628 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -161,6 +161,9 @@ extern struct sctp_globals {
161 */ 161 */
162 int sndbuf_policy; 162 int sndbuf_policy;
163 163
164 /* Delayed SACK timeout 200ms default*/
165 int sack_timeout;
166
164 /* HB.interval - 30 seconds */ 167 /* HB.interval - 30 seconds */
165 int hb_interval; 168 int hb_interval;
166 169
@@ -217,6 +220,7 @@ extern struct sctp_globals {
217#define sctp_sndbuf_policy (sctp_globals.sndbuf_policy) 220#define sctp_sndbuf_policy (sctp_globals.sndbuf_policy)
218#define sctp_max_retrans_path (sctp_globals.max_retrans_path) 221#define sctp_max_retrans_path (sctp_globals.max_retrans_path)
219#define sctp_max_retrans_init (sctp_globals.max_retrans_init) 222#define sctp_max_retrans_init (sctp_globals.max_retrans_init)
223#define sctp_sack_timeout (sctp_globals.sack_timeout)
220#define sctp_hb_interval (sctp_globals.hb_interval) 224#define sctp_hb_interval (sctp_globals.hb_interval)
221#define sctp_max_instreams (sctp_globals.max_instreams) 225#define sctp_max_instreams (sctp_globals.max_instreams)
222#define sctp_max_outstreams (sctp_globals.max_outstreams) 226#define sctp_max_outstreams (sctp_globals.max_outstreams)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 16:22:58 -0500