diff options
Diffstat (limited to 'include')
74 files changed, 0 insertions, 16825 deletions
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h deleted file mode 100644 index 4b0e15206006..000000000000 --- a/include/asm-ppc/8xx_immap.h +++ /dev/null | |||
| @@ -1,564 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * MPC8xx Internal Memory Map | ||
| 3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | ||
| 4 | * | ||
| 5 | * The I/O on the MPC860 is comprised of blocks of special registers | ||
| 6 | * and the dual port ram for the Communication Processor Module. | ||
| 7 | * Within this space are functional units such as the SIU, memory | ||
| 8 | * controller, system timers, and other control functions. It is | ||
| 9 | * a combination that I found difficult to separate into logical | ||
| 10 | * functional files.....but anyone else is welcome to try. -- Dan | ||
| 11 | */ | ||
| 12 | #ifdef __KERNEL__ | ||
| 13 | #ifndef __IMMAP_8XX__ | ||
| 14 | #define __IMMAP_8XX__ | ||
| 15 | |||
| 16 | /* System configuration registers. | ||
| 17 | */ | ||
| 18 | typedef struct sys_conf { | ||
| 19 | uint sc_siumcr; | ||
| 20 | uint sc_sypcr; | ||
| 21 | uint sc_swt; | ||
| 22 | char res1[2]; | ||
| 23 | ushort sc_swsr; | ||
| 24 | uint sc_sipend; | ||
| 25 | uint sc_simask; | ||
| 26 | uint sc_siel; | ||
| 27 | uint sc_sivec; | ||
| 28 | uint sc_tesr; | ||
| 29 | char res2[0xc]; | ||
| 30 | uint sc_sdcr; | ||
| 31 | char res3[0x4c]; | ||
| 32 | } sysconf8xx_t; | ||
| 33 | |||
| 34 | /* PCMCIA configuration registers. | ||
| 35 | */ | ||
| 36 | typedef struct pcmcia_conf { | ||
| 37 | uint pcmc_pbr0; | ||
| 38 | uint pcmc_por0; | ||
| 39 | uint pcmc_pbr1; | ||
| 40 | uint pcmc_por1; | ||
| 41 | uint pcmc_pbr2; | ||
| 42 | uint pcmc_por2; | ||
| 43 | uint pcmc_pbr3; | ||
| 44 | uint pcmc_por3; | ||
| 45 | uint pcmc_pbr4; | ||
| 46 | uint pcmc_por4; | ||
| 47 | uint pcmc_pbr5; | ||
| 48 | uint pcmc_por5; | ||
| 49 | uint pcmc_pbr6; | ||
| 50 | uint pcmc_por6; | ||
| 51 | uint pcmc_pbr7; | ||
| 52 | uint pcmc_por7; | ||
| 53 | char res1[0x20]; | ||
| 54 | uint pcmc_pgcra; | ||
| 55 | uint pcmc_pgcrb; | ||
| 56 | uint pcmc_pscr; | ||
| 57 | char res2[4]; | ||
| 58 | uint pcmc_pipr; | ||
| 59 | char res3[4]; | ||
| 60 | uint pcmc_per; | ||
| 61 | char res4[4]; | ||
| 62 | } pcmconf8xx_t; | ||
| 63 | |||
| 64 | /* Memory controller registers. | ||
| 65 | */ | ||
| 66 | typedef struct mem_ctlr { | ||
| 67 | uint memc_br0; | ||
| 68 | uint memc_or0; | ||
| 69 | uint memc_br1; | ||
| 70 | uint memc_or1; | ||
| 71 | uint memc_br2; | ||
| 72 | uint memc_or2; | ||
| 73 | uint memc_br3; | ||
| 74 | uint memc_or3; | ||
| 75 | uint memc_br4; | ||
| 76 | uint memc_or4; | ||
| 77 | uint memc_br5; | ||
| 78 | uint memc_or5; | ||
| 79 | uint memc_br6; | ||
| 80 | uint memc_or6; | ||
| 81 | uint memc_br7; | ||
| 82 | uint memc_or7; | ||
| 83 | char res1[0x24]; | ||
| 84 | uint memc_mar; | ||
| 85 | uint memc_mcr; | ||
| 86 | char res2[4]; | ||
| 87 | uint memc_mamr; | ||
| 88 | uint memc_mbmr; | ||
| 89 | ushort memc_mstat; | ||
| 90 | ushort memc_mptpr; | ||
| 91 | uint memc_mdr; | ||
| 92 | char res3[0x80]; | ||
| 93 | } memctl8xx_t; | ||
| 94 | |||
| 95 | /*----------------------------------------------------------------------- | ||
| 96 | * BR - Memory Controler: Base Register 16-9 | ||
| 97 | */ | ||
| 98 | #define BR_BA_MSK 0xffff8000 /* Base Address Mask */ | ||
| 99 | #define BR_AT_MSK 0x00007000 /* Address Type Mask */ | ||
| 100 | #define BR_PS_MSK 0x00000c00 /* Port Size Mask */ | ||
| 101 | #define BR_PS_32 0x00000000 /* 32 bit port size */ | ||
| 102 | #define BR_PS_16 0x00000800 /* 16 bit port size */ | ||
| 103 | #define BR_PS_8 0x00000400 /* 8 bit port size */ | ||
| 104 | #define BR_PARE 0x00000200 /* Parity Enable */ | ||
| 105 | #define BR_WP 0x00000100 /* Write Protect */ | ||
| 106 | #define BR_MS_MSK 0x000000c0 /* Machine Select Mask */ | ||
| 107 | #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ | ||
| 108 | #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ | ||
| 109 | #define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */ | ||
| 110 | #define BR_V 0x00000001 /* Bank Valid */ | ||
| 111 | |||
| 112 | /*----------------------------------------------------------------------- | ||
| 113 | * OR - Memory Controler: Option Register 16-11 | ||
| 114 | */ | ||
| 115 | #define OR_AM_MSK 0xffff8000 /* Address Mask Mask */ | ||
| 116 | #define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ | ||
| 117 | #define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ | ||
| 118 | /* Address Multiplex */ | ||
| 119 | #define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ | ||
| 120 | #define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ | ||
| 121 | #define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ | ||
| 122 | #define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ | ||
| 123 | #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ | ||
| 124 | #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ | ||
| 125 | #define OR_BI 0x00000100 /* Burst inhibit */ | ||
| 126 | #define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */ | ||
| 127 | #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ | ||
| 128 | #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ | ||
| 129 | #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ | ||
| 130 | #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ | ||
| 131 | #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ | ||
| 132 | #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ | ||
| 133 | #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ | ||
| 134 | #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ | ||
| 135 | #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ | ||
| 136 | #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ | ||
| 137 | #define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ | ||
| 138 | #define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ | ||
| 139 | #define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ | ||
| 140 | #define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ | ||
| 141 | #define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ | ||
| 142 | #define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ | ||
| 143 | #define OR_SETA 0x00000008 /* External Transfer Acknowledge */ | ||
| 144 | #define OR_TRLX 0x00000004 /* Timing Relaxed */ | ||
| 145 | #define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ | ||
| 146 | |||
| 147 | /* System Integration Timers. | ||
| 148 | */ | ||
| 149 | typedef struct sys_int_timers { | ||
| 150 | ushort sit_tbscr; | ||
| 151 | char res0[0x02]; | ||
| 152 | uint sit_tbreff0; | ||
| 153 | uint sit_tbreff1; | ||
| 154 | char res1[0x14]; | ||
| 155 | ushort sit_rtcsc; | ||
| 156 | char res2[0x02]; | ||
| 157 | uint sit_rtc; | ||
| 158 | uint sit_rtsec; | ||
| 159 | uint sit_rtcal; | ||
| 160 | char res3[0x10]; | ||
| 161 | ushort sit_piscr; | ||
| 162 | char res4[2]; | ||
| 163 | uint sit_pitc; | ||
| 164 | uint sit_pitr; | ||
| 165 | char res5[0x34]; | ||
| 166 | } sit8xx_t; | ||
| 167 | |||
| 168 | #define TBSCR_TBIRQ_MASK ((ushort)0xff00) | ||
| 169 | #define TBSCR_REFA ((ushort)0x0080) | ||
| 170 | #define TBSCR_REFB ((ushort)0x0040) | ||
| 171 | #define TBSCR_REFAE ((ushort)0x0008) | ||
| 172 | #define TBSCR_REFBE ((ushort)0x0004) | ||
| 173 | #define TBSCR_TBF ((ushort)0x0002) | ||
| 174 | #define TBSCR_TBE ((ushort)0x0001) | ||
| 175 | |||
| 176 | #define RTCSC_RTCIRQ_MASK ((ushort)0xff00) | ||
| 177 | #define RTCSC_SEC ((ushort)0x0080) | ||
| 178 | #define RTCSC_ALR ((ushort)0x0040) | ||
| 179 | #define RTCSC_38K ((ushort)0x0010) | ||
| 180 | #define RTCSC_SIE ((ushort)0x0008) | ||
| 181 | #define RTCSC_ALE ((ushort)0x0004) | ||
| 182 | #define RTCSC_RTF ((ushort)0x0002) | ||
| 183 | #define RTCSC_RTE ((ushort)0x0001) | ||
| 184 | |||
| 185 | #define PISCR_PIRQ_MASK ((ushort)0xff00) | ||
| 186 | #define PISCR_PS ((ushort)0x0080) | ||
| 187 | #define PISCR_PIE ((ushort)0x0004) | ||
| 188 | #define PISCR_PTF ((ushort)0x0002) | ||
| 189 | #define PISCR_PTE ((ushort)0x0001) | ||
| 190 | |||
| 191 | /* Clocks and Reset. | ||
| 192 | */ | ||
| 193 | typedef struct clk_and_reset { | ||
| 194 | uint car_sccr; | ||
| 195 | uint car_plprcr; | ||
| 196 | uint car_rsr; | ||
| 197 | char res[0x74]; /* Reserved area */ | ||
| 198 | } car8xx_t; | ||
| 199 | |||
| 200 | /* System Integration Timers keys. | ||
| 201 | */ | ||
| 202 | typedef struct sitk { | ||
| 203 | uint sitk_tbscrk; | ||
| 204 | uint sitk_tbreff0k; | ||
| 205 | uint sitk_tbreff1k; | ||
| 206 | uint sitk_tbk; | ||
| 207 | char res1[0x10]; | ||
| 208 | uint sitk_rtcsck; | ||
| 209 | uint sitk_rtck; | ||
| 210 | uint sitk_rtseck; | ||
| 211 | uint sitk_rtcalk; | ||
| 212 | char res2[0x10]; | ||
| 213 | uint sitk_piscrk; | ||
| 214 | uint sitk_pitck; | ||
| 215 | char res3[0x38]; | ||
| 216 | } sitk8xx_t; | ||
| 217 | |||
| 218 | /* Clocks and reset keys. | ||
| 219 | */ | ||
| 220 | typedef struct cark { | ||
| 221 | uint cark_sccrk; | ||
| 222 | uint cark_plprcrk; | ||
| 223 | uint cark_rsrk; | ||
| 224 | char res[0x474]; | ||
| 225 | } cark8xx_t; | ||
| 226 | |||
| 227 | /* The key to unlock registers maintained by keep-alive power. | ||
| 228 | */ | ||
| 229 | #define KAPWR_KEY ((unsigned int)0x55ccaa33) | ||
| 230 | |||
| 231 | /* Video interface. MPC823 Only. | ||
| 232 | */ | ||
| 233 | typedef struct vid823 { | ||
| 234 | ushort vid_vccr; | ||
| 235 | ushort res1; | ||
| 236 | u_char vid_vsr; | ||
| 237 | u_char res2; | ||
| 238 | u_char vid_vcmr; | ||
| 239 | u_char res3; | ||
| 240 | uint vid_vbcb; | ||
| 241 | uint res4; | ||
| 242 | uint vid_vfcr0; | ||
| 243 | uint vid_vfaa0; | ||
| 244 | uint vid_vfba0; | ||
| 245 | uint vid_vfcr1; | ||
| 246 | uint vid_vfaa1; | ||
| 247 | uint vid_vfba1; | ||
| 248 | u_char res5[0x18]; | ||
| 249 | } vid823_t; | ||
| 250 | |||
| 251 | /* LCD interface. 823 Only. | ||
| 252 | */ | ||
| 253 | typedef struct lcd { | ||
| 254 | uint lcd_lccr; | ||
| 255 | uint lcd_lchcr; | ||
| 256 | uint lcd_lcvcr; | ||
| 257 | char res1[4]; | ||
| 258 | uint lcd_lcfaa; | ||
| 259 | uint lcd_lcfba; | ||
| 260 | char lcd_lcsr; | ||
| 261 | char res2[0x7]; | ||
| 262 | } lcd823_t; | ||
| 263 | |||
| 264 | /* I2C | ||
| 265 | */ | ||
| 266 | typedef struct i2c { | ||
| 267 | u_char i2c_i2mod; | ||
| 268 | char res1[3]; | ||
| 269 | u_char i2c_i2add; | ||
| 270 | char res2[3]; | ||
| 271 | u_char i2c_i2brg; | ||
| 272 | char res3[3]; | ||
| 273 | u_char i2c_i2com; | ||
| 274 | char res4[3]; | ||
| 275 | u_char i2c_i2cer; | ||
| 276 | char res5[3]; | ||
| 277 | u_char i2c_i2cmr; | ||
| 278 | char res6[0x8b]; | ||
| 279 | } i2c8xx_t; | ||
| 280 | |||
| 281 | /* DMA control/status registers. | ||
| 282 | */ | ||
| 283 | typedef struct sdma_csr { | ||
| 284 | char res1[4]; | ||
| 285 | uint sdma_sdar; | ||
| 286 | u_char sdma_sdsr; | ||
| 287 | char res3[3]; | ||
| 288 | u_char sdma_sdmr; | ||
| 289 | char res4[3]; | ||
| 290 | u_char sdma_idsr1; | ||
| 291 | char res5[3]; | ||
| 292 | u_char sdma_idmr1; | ||
| 293 | char res6[3]; | ||
| 294 | u_char sdma_idsr2; | ||
| 295 | char res7[3]; | ||
| 296 | u_char sdma_idmr2; | ||
| 297 | char res8[0x13]; | ||
| 298 | } sdma8xx_t; | ||
| 299 | |||
| 300 | /* Communication Processor Module Interrupt Controller. | ||
| 301 | */ | ||
| 302 | typedef struct cpm_ic { | ||
| 303 | ushort cpic_civr; | ||
| 304 | char res[0xe]; | ||
| 305 | uint cpic_cicr; | ||
| 306 | uint cpic_cipr; | ||
| 307 | uint cpic_cimr; | ||
| 308 | uint cpic_cisr; | ||
| 309 | } cpic8xx_t; | ||
| 310 | |||
| 311 | /* Input/Output Port control/status registers. | ||
| 312 | */ | ||
| 313 | typedef struct io_port { | ||
| 314 | ushort iop_padir; | ||
| 315 | ushort iop_papar; | ||
| 316 | ushort iop_paodr; | ||
| 317 | ushort iop_padat; | ||
| 318 | char res1[8]; | ||
| 319 | ushort iop_pcdir; | ||
| 320 | ushort iop_pcpar; | ||
| 321 | ushort iop_pcso; | ||
| 322 | ushort iop_pcdat; | ||
| 323 | ushort iop_pcint; | ||
| 324 | char res2[6]; | ||
| 325 | ushort iop_pddir; | ||
| 326 | ushort iop_pdpar; | ||
| 327 | char res3[2]; | ||
| 328 | ushort iop_pddat; | ||
| 329 | uint utmode; | ||
| 330 | char res4[4]; | ||
| 331 | } iop8xx_t; | ||
| 332 | |||
| 333 | /* Communication Processor Module Timers | ||
| 334 | */ | ||
| 335 | typedef struct cpm_timers { | ||
| 336 | ushort cpmt_tgcr; | ||
| 337 | char res1[0xe]; | ||
| 338 | ushort cpmt_tmr1; | ||
| 339 | ushort cpmt_tmr2; | ||
| 340 | ushort cpmt_trr1; | ||
| 341 | ushort cpmt_trr2; | ||
| 342 | ushort cpmt_tcr1; | ||
| 343 | ushort cpmt_tcr2; | ||
| 344 | ushort cpmt_tcn1; | ||
| 345 | ushort cpmt_tcn2; | ||
| 346 | ushort cpmt_tmr3; | ||
| 347 | ushort cpmt_tmr4; | ||
| 348 | ushort cpmt_trr3; | ||
| 349 | ushort cpmt_trr4; | ||
| 350 | ushort cpmt_tcr3; | ||
| 351 | ushort cpmt_tcr4; | ||
| 352 | ushort cpmt_tcn3; | ||
| 353 | ushort cpmt_tcn4; | ||
| 354 | ushort cpmt_ter1; | ||
| 355 | ushort cpmt_ter2; | ||
| 356 | ushort cpmt_ter3; | ||
| 357 | ushort cpmt_ter4; | ||
| 358 | char res2[8]; | ||
| 359 | } cpmtimer8xx_t; | ||
| 360 | |||
| 361 | /* Finally, the Communication Processor stuff..... | ||
| 362 | */ | ||
| 363 | typedef struct scc { /* Serial communication channels */ | ||
| 364 | uint scc_gsmrl; | ||
| 365 | uint scc_gsmrh; | ||
| 366 | ushort scc_psmr; | ||
| 367 | char res1[2]; | ||
| 368 | ushort scc_todr; | ||
| 369 | ushort scc_dsr; | ||
| 370 | ushort scc_scce; | ||
| 371 | char res2[2]; | ||
| 372 | ushort scc_sccm; | ||
| 373 | char res3; | ||
| 374 | u_char scc_sccs; | ||
| 375 | char res4[8]; | ||
| 376 | } scc_t; | ||
| 377 | |||
| 378 | typedef struct smc { /* Serial management channels */ | ||
| 379 | char res1[2]; | ||
| 380 | ushort smc_smcmr; | ||
| 381 | char res2[2]; | ||
| 382 | u_char smc_smce; | ||
| 383 | char res3[3]; | ||
| 384 | u_char smc_smcm; | ||
| 385 | char res4[5]; | ||
| 386 | } smc_t; | ||
| 387 | |||
| 388 | /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but | ||
| 389 | * it fits within the address space. | ||
| 390 | */ | ||
| 391 | |||
| 392 | typedef struct fec { | ||
| 393 | uint fec_addr_low; /* lower 32 bits of station address */ | ||
| 394 | ushort fec_addr_high; /* upper 16 bits of station address */ | ||
| 395 | ushort res1; /* reserved */ | ||
| 396 | uint fec_hash_table_high; /* upper 32-bits of hash table */ | ||
| 397 | uint fec_hash_table_low; /* lower 32-bits of hash table */ | ||
| 398 | uint fec_r_des_start; /* beginning of Rx descriptor ring */ | ||
| 399 | uint fec_x_des_start; /* beginning of Tx descriptor ring */ | ||
| 400 | uint fec_r_buff_size; /* Rx buffer size */ | ||
| 401 | uint res2[9]; /* reserved */ | ||
| 402 | uint fec_ecntrl; /* ethernet control register */ | ||
| 403 | uint fec_ievent; /* interrupt event register */ | ||
| 404 | uint fec_imask; /* interrupt mask register */ | ||
| 405 | uint fec_ivec; /* interrupt level and vector status */ | ||
| 406 | uint fec_r_des_active; /* Rx ring updated flag */ | ||
| 407 | uint fec_x_des_active; /* Tx ring updated flag */ | ||
| 408 | uint res3[10]; /* reserved */ | ||
| 409 | uint fec_mii_data; /* MII data register */ | ||
| 410 | uint fec_mii_speed; /* MII speed control register */ | ||
| 411 | uint res4[17]; /* reserved */ | ||
| 412 | uint fec_r_bound; /* end of RAM (read-only) */ | ||
| 413 | uint fec_r_fstart; /* Rx FIFO start address */ | ||
| 414 | uint res5[6]; /* reserved */ | ||
| 415 | uint fec_x_fstart; /* Tx FIFO start address */ | ||
| 416 | uint res6[17]; /* reserved */ | ||
| 417 | uint fec_fun_code; /* fec SDMA function code */ | ||
| 418 | uint res7[3]; /* reserved */ | ||
| 419 | uint fec_r_cntrl; /* Rx control register */ | ||
| 420 | uint fec_r_hash; /* Rx hash register */ | ||
| 421 | uint res8[14]; /* reserved */ | ||
| 422 | uint fec_x_cntrl; /* Tx control register */ | ||
| 423 | uint res9[0x1e]; /* reserved */ | ||
| 424 | } fec_t; | ||
| 425 | |||
| 426 | /* The FEC and LCD color map share the same address space.... | ||
| 427 | * I guess we will never see an 823T :-). | ||
| 428 | */ | ||
| 429 | union fec_lcd { | ||
| 430 | fec_t fl_un_fec; | ||
| 431 | u_char fl_un_cmap[0x200]; | ||
| 432 | }; | ||
| 433 | |||
| 434 | typedef struct comm_proc { | ||
| 435 | /* General control and status registers. | ||
| 436 | */ | ||
| 437 | ushort cp_cpcr; | ||
| 438 | u_char res1[2]; | ||
| 439 | ushort cp_rccr; | ||
| 440 | u_char res2; | ||
| 441 | u_char cp_rmds; | ||
| 442 | u_char res3[4]; | ||
| 443 | ushort cp_cpmcr1; | ||
| 444 | ushort cp_cpmcr2; | ||
| 445 | ushort cp_cpmcr3; | ||
| 446 | ushort cp_cpmcr4; | ||
| 447 | u_char res4[2]; | ||
| 448 | ushort cp_rter; | ||
| 449 | u_char res5[2]; | ||
| 450 | ushort cp_rtmr; | ||
| 451 | u_char res6[0x14]; | ||
| 452 | |||
| 453 | /* Baud rate generators. | ||
| 454 | */ | ||
| 455 | uint cp_brgc1; | ||
| 456 | uint cp_brgc2; | ||
| 457 | uint cp_brgc3; | ||
| 458 | uint cp_brgc4; | ||
| 459 | |||
| 460 | /* Serial Communication Channels. | ||
| 461 | */ | ||
| 462 | scc_t cp_scc[4]; | ||
| 463 | |||
| 464 | /* Serial Management Channels. | ||
| 465 | */ | ||
| 466 | smc_t cp_smc[2]; | ||
| 467 | |||
| 468 | /* Serial Peripheral Interface. | ||
| 469 | */ | ||
| 470 | ushort cp_spmode; | ||
| 471 | u_char res7[4]; | ||
| 472 | u_char cp_spie; | ||
| 473 | u_char res8[3]; | ||
| 474 | u_char cp_spim; | ||
| 475 | u_char res9[2]; | ||
| 476 | u_char cp_spcom; | ||
| 477 | u_char res10[2]; | ||
| 478 | |||
| 479 | /* Parallel Interface Port. | ||
| 480 | */ | ||
| 481 | u_char res11[2]; | ||
| 482 | ushort cp_pipc; | ||
| 483 | u_char res12[2]; | ||
| 484 | ushort cp_ptpr; | ||
| 485 | uint cp_pbdir; | ||
| 486 | uint cp_pbpar; | ||
| 487 | u_char res13[2]; | ||
| 488 | ushort cp_pbodr; | ||
| 489 | uint cp_pbdat; | ||
| 490 | |||
| 491 | /* Port E - MPC87x/88x only. | ||
| 492 | */ | ||
| 493 | uint cp_pedir; | ||
| 494 | uint cp_pepar; | ||
| 495 | uint cp_peso; | ||
| 496 | uint cp_peodr; | ||
| 497 | uint cp_pedat; | ||
| 498 | |||
| 499 | /* Communications Processor Timing Register - | ||
| 500 | Contains RMII Timing for the FECs on MPC87x/88x only. | ||
| 501 | */ | ||
| 502 | uint cp_cptr; | ||
| 503 | |||
| 504 | /* Serial Interface and Time Slot Assignment. | ||
| 505 | */ | ||
| 506 | uint cp_simode; | ||
| 507 | u_char cp_sigmr; | ||
| 508 | u_char res15; | ||
| 509 | u_char cp_sistr; | ||
| 510 | u_char cp_sicmr; | ||
| 511 | u_char res16[4]; | ||
| 512 | uint cp_sicr; | ||
| 513 | uint cp_sirp; | ||
| 514 | u_char res17[0xc]; | ||
| 515 | |||
| 516 | /* 256 bytes of MPC823 video controller RAM array. | ||
| 517 | */ | ||
| 518 | u_char cp_vcram[0x100]; | ||
| 519 | u_char cp_siram[0x200]; | ||
| 520 | |||
| 521 | /* The fast ethernet controller is not really part of the CPM, | ||
| 522 | * but it resides in the address space. | ||
| 523 | * The LCD color map is also here. | ||
| 524 | */ | ||
| 525 | union fec_lcd fl_un; | ||
| 526 | #define cp_fec fl_un.fl_un_fec | ||
| 527 | #define lcd_cmap fl_un.fl_un_cmap | ||
| 528 | char res18[0xE00]; | ||
| 529 | |||
| 530 | /* The DUET family has a second FEC here */ | ||
| 531 | fec_t cp_fec2; | ||
| 532 | #define cp_fec1 cp_fec /* consistency macro */ | ||
| 533 | |||
| 534 | /* Dual Ported RAM follows. | ||
| 535 | * There are many different formats for this memory area | ||
| 536 | * depending upon the devices used and options chosen. | ||
| 537 | * Some processors don't have all of it populated. | ||
| 538 | */ | ||
| 539 | u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ | ||
| 540 | u_char cp_dparam[0x400]; /* Parameter RAM */ | ||
| 541 | } cpm8xx_t; | ||
| 542 | |||
| 543 | /* Internal memory map. | ||
| 544 | */ | ||
| 545 | typedef struct immap { | ||
| 546 | sysconf8xx_t im_siu_conf; /* SIU Configuration */ | ||
| 547 | pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ | ||
| 548 | memctl8xx_t im_memctl; /* Memory Controller */ | ||
| 549 | sit8xx_t im_sit; /* System integration timers */ | ||
| 550 | car8xx_t im_clkrst; /* Clocks and reset */ | ||
| 551 | sitk8xx_t im_sitk; /* Sys int timer keys */ | ||
| 552 | cark8xx_t im_clkrstk; /* Clocks and reset keys */ | ||
| 553 | vid823_t im_vid; /* Video (823 only) */ | ||
| 554 | lcd823_t im_lcd; /* LCD (823 only) */ | ||
| 555 | i2c8xx_t im_i2c; /* I2C control/status */ | ||
| 556 | sdma8xx_t im_sdma; /* SDMA control/status */ | ||
| 557 | cpic8xx_t im_cpic; /* CPM Interrupt Controller */ | ||
| 558 | iop8xx_t im_ioport; /* IO Port control/status */ | ||
| 559 | cpmtimer8xx_t im_cpmtimer; /* CPM timers */ | ||
| 560 | cpm8xx_t im_cpm; /* Communication processor */ | ||
| 561 | } immap_t; | ||
| 562 | |||
| 563 | #endif /* __IMMAP_8XX__ */ | ||
| 564 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/amigayle.h b/include/asm-ppc/amigayle.h deleted file mode 100644 index 1fe0b87859b0..000000000000 --- a/include/asm-ppc/amigayle.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-m68k/amigayle.h> | ||
diff --git a/include/asm-ppc/amipcmcia.h b/include/asm-ppc/amipcmcia.h deleted file mode 100644 index 3f65f63f508f..000000000000 --- a/include/asm-ppc/amipcmcia.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-m68k/amipcmcia.h> | ||
diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h deleted file mode 100644 index f6ed77aee328..000000000000 --- a/include/asm-ppc/bootinfo.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Non-machine dependent bootinfo structure. Basic idea | ||
| 3 | * borrowed from the m68k. | ||
| 4 | * | ||
| 5 | * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org> | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifdef __KERNEL__ | ||
| 9 | #ifndef _PPC_BOOTINFO_H | ||
| 10 | #define _PPC_BOOTINFO_H | ||
| 11 | |||
| 12 | #include <asm/page.h> | ||
| 13 | |||
| 14 | struct bi_record { | ||
| 15 | unsigned long tag; /* tag ID */ | ||
| 16 | unsigned long size; /* size of record (in bytes) */ | ||
| 17 | unsigned long data[0]; /* data */ | ||
| 18 | }; | ||
| 19 | |||
| 20 | #define BI_FIRST 0x1010 /* first record - marker */ | ||
| 21 | #define BI_LAST 0x1011 /* last record - marker */ | ||
| 22 | #define BI_CMD_LINE 0x1012 | ||
| 23 | #define BI_BOOTLOADER_ID 0x1013 | ||
| 24 | #define BI_INITRD 0x1014 | ||
| 25 | #define BI_SYSMAP 0x1015 | ||
| 26 | #define BI_MACHTYPE 0x1016 | ||
| 27 | #define BI_MEMSIZE 0x1017 | ||
| 28 | #define BI_BOARD_INFO 0x1018 | ||
| 29 | |||
| 30 | extern struct bi_record *find_bootinfo(void); | ||
| 31 | extern void bootinfo_init(struct bi_record *rec); | ||
| 32 | extern void bootinfo_append(unsigned long tag, unsigned long size, void * data); | ||
| 33 | extern void parse_bootinfo(struct bi_record *rec); | ||
| 34 | extern unsigned long boot_mem_size; | ||
| 35 | |||
| 36 | static inline struct bi_record * | ||
| 37 | bootinfo_addr(unsigned long offset) | ||
| 38 | { | ||
| 39 | |||
| 40 | return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1, | ||
| 41 | (1 << 20)); | ||
| 42 | } | ||
| 43 | |||
| 44 | |||
| 45 | #endif /* _PPC_BOOTINFO_H */ | ||
| 46 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h deleted file mode 100644 index b0c51b45d7a2..000000000000 --- a/include/asm-ppc/bootx.h +++ /dev/null | |||
| @@ -1,135 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file describes the structure passed from the BootX application | ||
| 3 | * (for MacOS) when it is used to boot Linux. | ||
| 4 | * | ||
| 5 | * Written by Benjamin Herrenschmidt. | ||
| 6 | */ | ||
| 7 | |||
| 8 | |||
| 9 | #ifndef __ASM_BOOTX_H__ | ||
| 10 | #define __ASM_BOOTX_H__ | ||
| 11 | |||
| 12 | #ifdef macintosh | ||
| 13 | #include <Types.h> | ||
| 14 | #include "linux_type_defs.h" | ||
| 15 | #endif | ||
| 16 | |||
| 17 | #ifdef macintosh | ||
| 18 | /* All this requires PowerPC alignment */ | ||
| 19 | #pragma options align=power | ||
| 20 | #endif | ||
| 21 | |||
| 22 | /* On kernel entry: | ||
| 23 | * | ||
| 24 | * r3 = 0x426f6f58 ('BooX') | ||
| 25 | * r4 = pointer to boot_infos | ||
| 26 | * r5 = NULL | ||
| 27 | * | ||
| 28 | * Data and instruction translation disabled, interrupts | ||
| 29 | * disabled, kernel loaded at physical 0x00000000 on PCI | ||
| 30 | * machines (will be different on NuBus). | ||
| 31 | */ | ||
| 32 | |||
| 33 | #define BOOT_INFO_VERSION 5 | ||
| 34 | #define BOOT_INFO_COMPATIBLE_VERSION 1 | ||
| 35 | |||
| 36 | /* Bit in the architecture flag mask. More to be defined in | ||
| 37 | future versions. Note that either BOOT_ARCH_PCI or | ||
| 38 | BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are | ||
| 39 | set additionally when BOOT_ARCH_NUBUS is set. | ||
| 40 | */ | ||
| 41 | #define BOOT_ARCH_PCI 0x00000001UL | ||
| 42 | #define BOOT_ARCH_NUBUS 0x00000002UL | ||
| 43 | #define BOOT_ARCH_NUBUS_PDM 0x00000010UL | ||
| 44 | #define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL | ||
| 45 | #define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL | ||
| 46 | |||
| 47 | /* Maximum number of ranges in phys memory map */ | ||
| 48 | #define MAX_MEM_MAP_SIZE 26 | ||
| 49 | |||
| 50 | /* This is the format of an element in the physical memory map. Note that | ||
| 51 | the map is optional and current BootX will only build it for pre-PCI | ||
| 52 | machines */ | ||
| 53 | typedef struct boot_info_map_entry | ||
| 54 | { | ||
| 55 | __u32 physAddr; /* Physical starting address */ | ||
| 56 | __u32 size; /* Size in bytes */ | ||
| 57 | } boot_info_map_entry_t; | ||
| 58 | |||
| 59 | |||
| 60 | /* Here are the boot informations that are passed to the bootstrap | ||
| 61 | * Note that the kernel arguments and the device tree are appended | ||
| 62 | * at the end of this structure. */ | ||
| 63 | typedef struct boot_infos | ||
| 64 | { | ||
| 65 | /* Version of this structure */ | ||
| 66 | __u32 version; | ||
| 67 | /* backward compatible down to version: */ | ||
| 68 | __u32 compatible_version; | ||
| 69 | |||
| 70 | /* NEW (vers. 2) this holds the current _logical_ base addr of | ||
| 71 | the frame buffer (for use by early boot message) */ | ||
| 72 | __u8* logicalDisplayBase; | ||
| 73 | |||
| 74 | /* NEW (vers. 4) Apple's machine identification */ | ||
| 75 | __u32 machineID; | ||
| 76 | |||
| 77 | /* NEW (vers. 4) Detected hw architecture */ | ||
| 78 | __u32 architecture; | ||
| 79 | |||
| 80 | /* The device tree (internal addresses relative to the beginning of the tree, | ||
| 81 | * device tree offset relative to the beginning of this structure). | ||
| 82 | * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this | ||
| 83 | * field is 0. | ||
| 84 | */ | ||
| 85 | __u32 deviceTreeOffset; /* Device tree offset */ | ||
| 86 | __u32 deviceTreeSize; /* Size of the device tree */ | ||
| 87 | |||
| 88 | /* Some infos about the current MacOS display */ | ||
| 89 | __u32 dispDeviceRect[4]; /* left,top,right,bottom */ | ||
| 90 | __u32 dispDeviceDepth; /* (8, 16 or 32) */ | ||
| 91 | __u8* dispDeviceBase; /* base address (physical) */ | ||
| 92 | __u32 dispDeviceRowBytes; /* rowbytes (in bytes) */ | ||
| 93 | __u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */ | ||
| 94 | /* Optional offset in the registry to the current | ||
| 95 | * MacOS display. (Can be 0 when not detected) */ | ||
| 96 | __u32 dispDeviceRegEntryOffset; | ||
| 97 | |||
| 98 | /* Optional pointer to boot ramdisk (offset from this structure) */ | ||
| 99 | __u32 ramDisk; | ||
| 100 | __u32 ramDiskSize; /* size of ramdisk image */ | ||
| 101 | |||
| 102 | /* Kernel command line arguments (offset from this structure) */ | ||
| 103 | __u32 kernelParamsOffset; | ||
| 104 | |||
| 105 | /* ALL BELOW NEW (vers. 4) */ | ||
| 106 | |||
| 107 | /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag | ||
| 108 | (non-PCI) only. On PCI, memory is contiguous and it's size is in the | ||
| 109 | device-tree. */ | ||
| 110 | boot_info_map_entry_t | ||
| 111 | physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */ | ||
| 112 | __u32 physMemoryMapSize; /* How many entries in map */ | ||
| 113 | |||
| 114 | |||
| 115 | /* The framebuffer size (optional, currently 0) */ | ||
| 116 | __u32 frameBufferSize; /* Represents a max size, can be 0. */ | ||
| 117 | |||
| 118 | /* NEW (vers. 5) */ | ||
| 119 | |||
| 120 | /* Total params size (args + colormap + device tree + ramdisk) */ | ||
| 121 | __u32 totalParamsSize; | ||
| 122 | |||
| 123 | } boot_infos_t; | ||
| 124 | |||
| 125 | /* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented | ||
| 126 | * by 3 short words containing a 16 bits (unsigned) color component. | ||
| 127 | * Later versions may contain the gamma table for direct-color devices here. | ||
| 128 | */ | ||
| 129 | #define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL) | ||
| 130 | |||
| 131 | #ifdef macintosh | ||
| 132 | #pragma options align=reset | ||
| 133 | #endif | ||
| 134 | |||
| 135 | #endif | ||
diff --git a/include/asm-ppc/btext.h b/include/asm-ppc/btext.h deleted file mode 100644 index ed3630251b3b..000000000000 --- a/include/asm-ppc/btext.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Definitions for using the procedures in btext.c. | ||
| 3 | * | ||
| 4 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> | ||
| 5 | */ | ||
| 6 | #ifndef __PPC_BTEXT_H | ||
| 7 | #define __PPC_BTEXT_H | ||
| 8 | #ifdef __KERNEL__ | ||
| 9 | |||
| 10 | #include <asm/bootx.h> | ||
| 11 | |||
| 12 | extern void btext_clearscreen(void); | ||
| 13 | extern void btext_flushscreen(void); | ||
| 14 | |||
| 15 | extern unsigned long disp_BAT[2]; | ||
| 16 | |||
| 17 | extern boot_infos_t disp_bi; | ||
| 18 | extern int boot_text_mapped; | ||
| 19 | |||
| 20 | extern void btext_init(boot_infos_t *bi); | ||
| 21 | extern void btext_welcome(void); | ||
| 22 | extern void btext_prepare_BAT(void); | ||
| 23 | extern void btext_setup_display(int width, int height, int depth, int pitch, | ||
| 24 | unsigned long address); | ||
| 25 | extern void map_boot_text(void); | ||
| 26 | extern void btext_update_display(unsigned long phys, int width, int height, | ||
| 27 | int depth, int pitch); | ||
| 28 | |||
| 29 | extern void btext_drawchar(char c); | ||
| 30 | extern void btext_drawstring(const char *str); | ||
| 31 | extern void btext_drawhex(unsigned long v); | ||
| 32 | |||
| 33 | #endif /* __KERNEL__ */ | ||
| 34 | #endif /* __PPC_BTEXT_H */ | ||
diff --git a/include/asm-ppc/cpm1.h b/include/asm-ppc/cpm1.h deleted file mode 100644 index 03035acd85c6..000000000000 --- a/include/asm-ppc/cpm1.h +++ /dev/null | |||
| @@ -1,688 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * MPC8xx Communication Processor Module. | ||
| 3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | ||
| 4 | * | ||
| 5 | * This file contains structures and information for the communication | ||
| 6 | * processor channels. Some CPM control and status is available | ||
| 7 | * throught the MPC8xx internal memory map. See immap.h for details. | ||
| 8 | * This file only contains what I need for the moment, not the total | ||
| 9 | * CPM capabilities. I (or someone else) will add definitions as they | ||
| 10 | * are needed. -- Dan | ||
| 11 | * | ||
| 12 | * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 | ||
| 13 | * bytes of the DP RAM and relocates the I2C parameter area to the | ||
| 14 | * IDMA1 space. The remaining DP RAM is available for buffer descriptors | ||
| 15 | * or other use. | ||
| 16 | */ | ||
| 17 | #ifndef __CPM1__ | ||
| 18 | #define __CPM1__ | ||
| 19 | |||
| 20 | #include <asm/8xx_immap.h> | ||
| 21 | #include <asm/ptrace.h> | ||
| 22 | |||
| 23 | /* CPM Command register. | ||
| 24 | */ | ||
| 25 | #define CPM_CR_RST ((ushort)0x8000) | ||
| 26 | #define CPM_CR_OPCODE ((ushort)0x0f00) | ||
| 27 | #define CPM_CR_CHAN ((ushort)0x00f0) | ||
| 28 | #define CPM_CR_FLG ((ushort)0x0001) | ||
| 29 | |||
| 30 | /* Some commands (there are more...later) | ||
| 31 | */ | ||
| 32 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | ||
| 33 | #define CPM_CR_INIT_RX ((ushort)0x0001) | ||
| 34 | #define CPM_CR_INIT_TX ((ushort)0x0002) | ||
| 35 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | ||
| 36 | #define CPM_CR_STOP_TX ((ushort)0x0004) | ||
| 37 | #define CPM_CR_GRA_STOP_TX ((ushort)0x0005) | ||
| 38 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | ||
| 39 | #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) | ||
| 40 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | ||
| 41 | #define CPM_CR_SET_TIMER CPM_CR_SET_GADDR | ||
| 42 | |||
| 43 | /* Channel numbers. | ||
| 44 | */ | ||
| 45 | #define CPM_CR_CH_SCC1 ((ushort)0x0000) | ||
| 46 | #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ | ||
| 47 | #define CPM_CR_CH_SCC2 ((ushort)0x0004) | ||
| 48 | #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ | ||
| 49 | #define CPM_CR_CH_TIMER CPM_CR_CH_SPI | ||
| 50 | #define CPM_CR_CH_SCC3 ((ushort)0x0008) | ||
| 51 | #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ | ||
| 52 | #define CPM_CR_CH_SCC4 ((ushort)0x000c) | ||
| 53 | #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ | ||
| 54 | |||
| 55 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) | ||
| 56 | |||
| 57 | /* The dual ported RAM is multi-functional. Some areas can be (and are | ||
| 58 | * being) used for microcode. There is an area that can only be used | ||
| 59 | * as data ram for buffer descriptors, which is all we use right now. | ||
| 60 | * Currently the first 512 and last 256 bytes are used for microcode. | ||
| 61 | */ | ||
| 62 | #define CPM_DATAONLY_BASE ((uint)0x0800) | ||
| 63 | #define CPM_DATAONLY_SIZE ((uint)0x0700) | ||
| 64 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) | ||
| 65 | |||
| 66 | /* Export the base address of the communication processor registers | ||
| 67 | * and dual port ram. | ||
| 68 | */ | ||
| 69 | extern cpm8xx_t *cpmp; /* Pointer to comm processor */ | ||
| 70 | extern unsigned long cpm_dpalloc(uint size, uint align); | ||
| 71 | extern int cpm_dpfree(unsigned long offset); | ||
| 72 | extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); | ||
| 73 | extern void cpm_dpdump(void); | ||
| 74 | extern void *cpm_dpram_addr(unsigned long offset); | ||
| 75 | extern uint cpm_dpram_phys(u8 *addr); | ||
| 76 | extern void cpm_setbrg(uint brg, uint rate); | ||
| 77 | |||
| 78 | extern void cpm_load_patch(volatile immap_t *immr); | ||
| 79 | |||
| 80 | /* Buffer descriptors used by many of the CPM protocols. | ||
| 81 | */ | ||
| 82 | typedef struct cpm_buf_desc { | ||
| 83 | ushort cbd_sc; /* Status and Control */ | ||
| 84 | ushort cbd_datlen; /* Data length in buffer */ | ||
| 85 | uint cbd_bufaddr; /* Buffer address in host memory */ | ||
| 86 | } cbd_t; | ||
| 87 | |||
| 88 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ | ||
| 89 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ | ||
| 90 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | ||
| 91 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | ||
| 92 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ | ||
| 93 | #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ | ||
| 94 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | ||
| 95 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | ||
| 96 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | ||
| 97 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | ||
| 98 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | ||
| 99 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | ||
| 100 | #define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ | ||
| 101 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | ||
| 102 | #define BD_SC_UN ((ushort)0x0002) /* Underrun */ | ||
| 103 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ | ||
| 104 | #define BD_SC_CL ((ushort)0x0001) /* Collision */ | ||
| 105 | |||
| 106 | /* Parameter RAM offsets. | ||
| 107 | */ | ||
| 108 | #define PROFF_SCC1 ((uint)0x0000) | ||
| 109 | #define PROFF_IIC ((uint)0x0080) | ||
| 110 | #define PROFF_SCC2 ((uint)0x0100) | ||
| 111 | #define PROFF_SPI ((uint)0x0180) | ||
| 112 | #define PROFF_SCC3 ((uint)0x0200) | ||
| 113 | #define PROFF_SMC1 ((uint)0x0280) | ||
| 114 | #define PROFF_SCC4 ((uint)0x0300) | ||
| 115 | #define PROFF_SMC2 ((uint)0x0380) | ||
| 116 | |||
| 117 | /* Define enough so I can at least use the serial port as a UART. | ||
| 118 | * The MBX uses SMC1 as the host serial port. | ||
| 119 | */ | ||
| 120 | typedef struct smc_uart { | ||
| 121 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | ||
| 122 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | ||
| 123 | u_char smc_rfcr; /* Rx function code */ | ||
| 124 | u_char smc_tfcr; /* Tx function code */ | ||
| 125 | ushort smc_mrblr; /* Max receive buffer length */ | ||
| 126 | uint smc_rstate; /* Internal */ | ||
| 127 | uint smc_idp; /* Internal */ | ||
| 128 | ushort smc_rbptr; /* Internal */ | ||
| 129 | ushort smc_ibc; /* Internal */ | ||
| 130 | uint smc_rxtmp; /* Internal */ | ||
| 131 | uint smc_tstate; /* Internal */ | ||
| 132 | uint smc_tdp; /* Internal */ | ||
| 133 | ushort smc_tbptr; /* Internal */ | ||
| 134 | ushort smc_tbc; /* Internal */ | ||
| 135 | uint smc_txtmp; /* Internal */ | ||
| 136 | ushort smc_maxidl; /* Maximum idle characters */ | ||
| 137 | ushort smc_tmpidl; /* Temporary idle counter */ | ||
| 138 | ushort smc_brklen; /* Last received break length */ | ||
| 139 | ushort smc_brkec; /* rcv'd break condition counter */ | ||
| 140 | ushort smc_brkcr; /* xmt break count register */ | ||
| 141 | ushort smc_rmask; /* Temporary bit mask */ | ||
| 142 | char res1[8]; /* Reserved */ | ||
| 143 | ushort smc_rpbase; /* Relocation pointer */ | ||
| 144 | } smc_uart_t; | ||
| 145 | |||
| 146 | /* Function code bits. | ||
| 147 | */ | ||
| 148 | #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ | ||
| 149 | |||
| 150 | /* SMC uart mode register. | ||
| 151 | */ | ||
| 152 | #define SMCMR_REN ((ushort)0x0001) | ||
| 153 | #define SMCMR_TEN ((ushort)0x0002) | ||
| 154 | #define SMCMR_DM ((ushort)0x000c) | ||
| 155 | #define SMCMR_SM_GCI ((ushort)0x0000) | ||
| 156 | #define SMCMR_SM_UART ((ushort)0x0020) | ||
| 157 | #define SMCMR_SM_TRANS ((ushort)0x0030) | ||
| 158 | #define SMCMR_SM_MASK ((ushort)0x0030) | ||
| 159 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | ||
| 160 | #define SMCMR_REVD SMCMR_PM_EVEN | ||
| 161 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | ||
| 162 | #define SMCMR_BS SMCMR_PEN | ||
| 163 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | ||
| 164 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | ||
| 165 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | ||
| 166 | |||
| 167 | /* SMC2 as Centronics parallel printer. It is half duplex, in that | ||
| 168 | * it can only receive or transmit. The parameter ram values for | ||
| 169 | * each direction are either unique or properly overlap, so we can | ||
| 170 | * include them in one structure. | ||
| 171 | */ | ||
| 172 | typedef struct smc_centronics { | ||
| 173 | ushort scent_rbase; | ||
| 174 | ushort scent_tbase; | ||
| 175 | u_char scent_cfcr; | ||
| 176 | u_char scent_smask; | ||
| 177 | ushort scent_mrblr; | ||
| 178 | uint scent_rstate; | ||
| 179 | uint scent_r_ptr; | ||
| 180 | ushort scent_rbptr; | ||
| 181 | ushort scent_r_cnt; | ||
| 182 | uint scent_rtemp; | ||
| 183 | uint scent_tstate; | ||
| 184 | uint scent_t_ptr; | ||
| 185 | ushort scent_tbptr; | ||
| 186 | ushort scent_t_cnt; | ||
| 187 | uint scent_ttemp; | ||
| 188 | ushort scent_max_sl; | ||
| 189 | ushort scent_sl_cnt; | ||
| 190 | ushort scent_character1; | ||
| 191 | ushort scent_character2; | ||
| 192 | ushort scent_character3; | ||
| 193 | ushort scent_character4; | ||
| 194 | ushort scent_character5; | ||
| 195 | ushort scent_character6; | ||
| 196 | ushort scent_character7; | ||
| 197 | ushort scent_character8; | ||
| 198 | ushort scent_rccm; | ||
| 199 | ushort scent_rccr; | ||
| 200 | } smc_cent_t; | ||
| 201 | |||
| 202 | /* Centronics Status Mask Register. | ||
| 203 | */ | ||
| 204 | #define SMC_CENT_F ((u_char)0x08) | ||
| 205 | #define SMC_CENT_PE ((u_char)0x04) | ||
| 206 | #define SMC_CENT_S ((u_char)0x02) | ||
| 207 | |||
| 208 | /* SMC Event and Mask register. | ||
| 209 | */ | ||
| 210 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | ||
| 211 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | ||
| 212 | #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ | ||
| 213 | #define SMCM_BSY ((unsigned char)0x04) | ||
| 214 | #define SMCM_TX ((unsigned char)0x02) | ||
| 215 | #define SMCM_RX ((unsigned char)0x01) | ||
| 216 | |||
| 217 | /* Baud rate generators. | ||
| 218 | */ | ||
| 219 | #define CPM_BRG_RST ((uint)0x00020000) | ||
| 220 | #define CPM_BRG_EN ((uint)0x00010000) | ||
| 221 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | ||
| 222 | #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) | ||
| 223 | #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) | ||
| 224 | #define CPM_BRG_ATB ((uint)0x00002000) | ||
| 225 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | ||
| 226 | #define CPM_BRG_DIV16 ((uint)0x00000001) | ||
| 227 | |||
| 228 | /* SI Clock Route Register | ||
| 229 | */ | ||
| 230 | #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) | ||
| 231 | #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) | ||
| 232 | #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) | ||
| 233 | #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) | ||
| 234 | #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) | ||
| 235 | #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) | ||
| 236 | #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) | ||
| 237 | #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) | ||
| 238 | |||
| 239 | /* SCCs. | ||
| 240 | */ | ||
| 241 | #define SCC_GSMRH_IRP ((uint)0x00040000) | ||
| 242 | #define SCC_GSMRH_GDE ((uint)0x00010000) | ||
| 243 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | ||
| 244 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | ||
| 245 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | ||
| 246 | #define SCC_GSMRH_REVD ((uint)0x00002000) | ||
| 247 | #define SCC_GSMRH_TRX ((uint)0x00001000) | ||
| 248 | #define SCC_GSMRH_TTX ((uint)0x00000800) | ||
| 249 | #define SCC_GSMRH_CDP ((uint)0x00000400) | ||
| 250 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | ||
| 251 | #define SCC_GSMRH_CDS ((uint)0x00000100) | ||
| 252 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | ||
| 253 | #define SCC_GSMRH_TFL ((uint)0x00000040) | ||
| 254 | #define SCC_GSMRH_RFW ((uint)0x00000020) | ||
| 255 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | ||
| 256 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | ||
| 257 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | ||
| 258 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | ||
| 259 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | ||
| 260 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | ||
| 261 | |||
| 262 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | ||
| 263 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | ||
| 264 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | ||
| 265 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | ||
| 266 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | ||
| 267 | #define SCC_GSMRL_TCI ((uint)0x10000000) | ||
| 268 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | ||
| 269 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | ||
| 270 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | ||
| 271 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | ||
| 272 | #define SCC_GSMRL_RINV ((uint)0x02000000) | ||
| 273 | #define SCC_GSMRL_TINV ((uint)0x01000000) | ||
| 274 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | ||
| 275 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | ||
| 276 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | ||
| 277 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | ||
| 278 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | ||
| 279 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | ||
| 280 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | ||
| 281 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | ||
| 282 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | ||
| 283 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | ||
| 284 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | ||
| 285 | #define SCC_GSMRL_TEND ((uint)0x00040000) | ||
| 286 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | ||
| 287 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | ||
| 288 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | ||
| 289 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | ||
| 290 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | ||
| 291 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | ||
| 292 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | ||
| 293 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | ||
| 294 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | ||
| 295 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | ||
| 296 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | ||
| 297 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | ||
| 298 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | ||
| 299 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | ||
| 300 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | ||
| 301 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | ||
| 302 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | ||
| 303 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | ||
| 304 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | ||
| 305 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | ||
| 306 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | ||
| 307 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | ||
| 308 | #define SCC_GSMRL_ENR ((uint)0x00000020) | ||
| 309 | #define SCC_GSMRL_ENT ((uint)0x00000010) | ||
| 310 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | ||
| 311 | #define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) | ||
| 312 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | ||
| 313 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | ||
| 314 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | ||
| 315 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | ||
| 316 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | ||
| 317 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | ||
| 318 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | ||
| 319 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | ||
| 320 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | ||
| 321 | |||
| 322 | #define SCC_TODR_TOD ((ushort)0x8000) | ||
| 323 | |||
| 324 | /* SCC Event and Mask register. | ||
| 325 | */ | ||
| 326 | #define SCCM_TXE ((unsigned char)0x10) | ||
| 327 | #define SCCM_BSY ((unsigned char)0x04) | ||
| 328 | #define SCCM_TX ((unsigned char)0x02) | ||
| 329 | #define SCCM_RX ((unsigned char)0x01) | ||
| 330 | |||
| 331 | typedef struct scc_param { | ||
| 332 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | ||
| 333 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | ||
| 334 | u_char scc_rfcr; /* Rx function code */ | ||
| 335 | u_char scc_tfcr; /* Tx function code */ | ||
| 336 | ushort scc_mrblr; /* Max receive buffer length */ | ||
| 337 | uint scc_rstate; /* Internal */ | ||
| 338 | uint scc_idp; /* Internal */ | ||
| 339 | ushort scc_rbptr; /* Internal */ | ||
| 340 | ushort scc_ibc; /* Internal */ | ||
| 341 | uint scc_rxtmp; /* Internal */ | ||
| 342 | uint scc_tstate; /* Internal */ | ||
| 343 | uint scc_tdp; /* Internal */ | ||
| 344 | ushort scc_tbptr; /* Internal */ | ||
| 345 | ushort scc_tbc; /* Internal */ | ||
| 346 | uint scc_txtmp; /* Internal */ | ||
| 347 | uint scc_rcrc; /* Internal */ | ||
| 348 | uint scc_tcrc; /* Internal */ | ||
| 349 | } sccp_t; | ||
| 350 | |||
| 351 | /* Function code bits. | ||
| 352 | */ | ||
| 353 | #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ | ||
| 354 | |||
| 355 | /* CPM Ethernet through SCCx. | ||
| 356 | */ | ||
| 357 | typedef struct scc_enet { | ||
| 358 | sccp_t sen_genscc; | ||
| 359 | uint sen_cpres; /* Preset CRC */ | ||
| 360 | uint sen_cmask; /* Constant mask for CRC */ | ||
| 361 | uint sen_crcec; /* CRC Error counter */ | ||
| 362 | uint sen_alec; /* alignment error counter */ | ||
| 363 | uint sen_disfc; /* discard frame counter */ | ||
| 364 | ushort sen_pads; /* Tx short frame pad character */ | ||
| 365 | ushort sen_retlim; /* Retry limit threshold */ | ||
| 366 | ushort sen_retcnt; /* Retry limit counter */ | ||
| 367 | ushort sen_maxflr; /* maximum frame length register */ | ||
| 368 | ushort sen_minflr; /* minimum frame length register */ | ||
| 369 | ushort sen_maxd1; /* maximum DMA1 length */ | ||
| 370 | ushort sen_maxd2; /* maximum DMA2 length */ | ||
| 371 | ushort sen_maxd; /* Rx max DMA */ | ||
| 372 | ushort sen_dmacnt; /* Rx DMA counter */ | ||
| 373 | ushort sen_maxb; /* Max BD byte count */ | ||
| 374 | ushort sen_gaddr1; /* Group address filter */ | ||
| 375 | ushort sen_gaddr2; | ||
| 376 | ushort sen_gaddr3; | ||
| 377 | ushort sen_gaddr4; | ||
| 378 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | ||
| 379 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | ||
| 380 | uint sen_tbuf0rba; /* Internal */ | ||
| 381 | uint sen_tbuf0crc; /* Internal */ | ||
| 382 | ushort sen_tbuf0bcnt; /* Internal */ | ||
| 383 | ushort sen_paddrh; /* physical address (MSB) */ | ||
| 384 | ushort sen_paddrm; | ||
| 385 | ushort sen_paddrl; /* physical address (LSB) */ | ||
| 386 | ushort sen_pper; /* persistence */ | ||
| 387 | ushort sen_rfbdptr; /* Rx first BD pointer */ | ||
| 388 | ushort sen_tfbdptr; /* Tx first BD pointer */ | ||
| 389 | ushort sen_tlbdptr; /* Tx last BD pointer */ | ||
| 390 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | ||
| 391 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | ||
| 392 | uint sen_tbuf1rba; /* Internal */ | ||
| 393 | uint sen_tbuf1crc; /* Internal */ | ||
| 394 | ushort sen_tbuf1bcnt; /* Internal */ | ||
| 395 | ushort sen_txlen; /* Tx Frame length counter */ | ||
| 396 | ushort sen_iaddr1; /* Individual address filter */ | ||
| 397 | ushort sen_iaddr2; | ||
| 398 | ushort sen_iaddr3; | ||
| 399 | ushort sen_iaddr4; | ||
| 400 | ushort sen_boffcnt; /* Backoff counter */ | ||
| 401 | |||
| 402 | /* NOTE: Some versions of the manual have the following items | ||
| 403 | * incorrectly documented. Below is the proper order. | ||
| 404 | */ | ||
| 405 | ushort sen_taddrh; /* temp address (MSB) */ | ||
| 406 | ushort sen_taddrm; | ||
| 407 | ushort sen_taddrl; /* temp address (LSB) */ | ||
| 408 | } scc_enet_t; | ||
| 409 | |||
| 410 | /* SCC Event register as used by Ethernet. | ||
| 411 | */ | ||
| 412 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | ||
| 413 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | ||
| 414 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | ||
| 415 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | ||
| 416 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | ||
| 417 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | ||
| 418 | |||
| 419 | /* SCC Mode Register (PMSR) as used by Ethernet. | ||
| 420 | */ | ||
| 421 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | ||
| 422 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | ||
| 423 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | ||
| 424 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | ||
| 425 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | ||
| 426 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | ||
| 427 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | ||
| 428 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | ||
| 429 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | ||
| 430 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | ||
| 431 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | ||
| 432 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | ||
| 433 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | ||
| 434 | |||
| 435 | /* Buffer descriptor control/status used by Ethernet receive. | ||
| 436 | */ | ||
| 437 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | ||
| 438 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | ||
| 439 | #define BD_ENET_RX_INTR ((ushort)0x1000) | ||
| 440 | #define BD_ENET_RX_LAST ((ushort)0x0800) | ||
| 441 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | ||
| 442 | #define BD_ENET_RX_MISS ((ushort)0x0100) | ||
| 443 | #define BD_ENET_RX_LG ((ushort)0x0020) | ||
| 444 | #define BD_ENET_RX_NO ((ushort)0x0010) | ||
| 445 | #define BD_ENET_RX_SH ((ushort)0x0008) | ||
| 446 | #define BD_ENET_RX_CR ((ushort)0x0004) | ||
| 447 | #define BD_ENET_RX_OV ((ushort)0x0002) | ||
| 448 | #define BD_ENET_RX_CL ((ushort)0x0001) | ||
| 449 | #define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ | ||
| 450 | #define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ | ||
| 451 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ | ||
| 452 | |||
| 453 | /* Buffer descriptor control/status used by Ethernet transmit. | ||
| 454 | */ | ||
| 455 | #define BD_ENET_TX_READY ((ushort)0x8000) | ||
| 456 | #define BD_ENET_TX_PAD ((ushort)0x4000) | ||
| 457 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | ||
| 458 | #define BD_ENET_TX_INTR ((ushort)0x1000) | ||
| 459 | #define BD_ENET_TX_LAST ((ushort)0x0800) | ||
| 460 | #define BD_ENET_TX_TC ((ushort)0x0400) | ||
| 461 | #define BD_ENET_TX_DEF ((ushort)0x0200) | ||
| 462 | #define BD_ENET_TX_HB ((ushort)0x0100) | ||
| 463 | #define BD_ENET_TX_LC ((ushort)0x0080) | ||
| 464 | #define BD_ENET_TX_RL ((ushort)0x0040) | ||
| 465 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | ||
| 466 | #define BD_ENET_TX_UN ((ushort)0x0002) | ||
| 467 | #define BD_ENET_TX_CSL ((ushort)0x0001) | ||
| 468 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | ||
| 469 | |||
| 470 | /* SCC as UART | ||
| 471 | */ | ||
| 472 | typedef struct scc_uart { | ||
| 473 | sccp_t scc_genscc; | ||
| 474 | char res1[8]; /* Reserved */ | ||
| 475 | ushort scc_maxidl; /* Maximum idle chars */ | ||
| 476 | ushort scc_idlc; /* temp idle counter */ | ||
| 477 | ushort scc_brkcr; /* Break count register */ | ||
| 478 | ushort scc_parec; /* receive parity error counter */ | ||
| 479 | ushort scc_frmec; /* receive framing error counter */ | ||
| 480 | ushort scc_nosec; /* receive noise counter */ | ||
| 481 | ushort scc_brkec; /* receive break condition counter */ | ||
| 482 | ushort scc_brkln; /* last received break length */ | ||
| 483 | ushort scc_uaddr1; /* UART address character 1 */ | ||
| 484 | ushort scc_uaddr2; /* UART address character 2 */ | ||
| 485 | ushort scc_rtemp; /* Temp storage */ | ||
| 486 | ushort scc_toseq; /* Transmit out of sequence char */ | ||
| 487 | ushort scc_char1; /* control character 1 */ | ||
| 488 | ushort scc_char2; /* control character 2 */ | ||
| 489 | ushort scc_char3; /* control character 3 */ | ||
| 490 | ushort scc_char4; /* control character 4 */ | ||
| 491 | ushort scc_char5; /* control character 5 */ | ||
| 492 | ushort scc_char6; /* control character 6 */ | ||
| 493 | ushort scc_char7; /* control character 7 */ | ||
| 494 | ushort scc_char8; /* control character 8 */ | ||
| 495 | ushort scc_rccm; /* receive control character mask */ | ||
| 496 | ushort scc_rccr; /* receive control character register */ | ||
| 497 | ushort scc_rlbc; /* receive last break character */ | ||
| 498 | } scc_uart_t; | ||
| 499 | |||
| 500 | /* SCC Event and Mask registers when it is used as a UART. | ||
| 501 | */ | ||
| 502 | #define UART_SCCM_GLR ((ushort)0x1000) | ||
| 503 | #define UART_SCCM_GLT ((ushort)0x0800) | ||
| 504 | #define UART_SCCM_AB ((ushort)0x0200) | ||
| 505 | #define UART_SCCM_IDL ((ushort)0x0100) | ||
| 506 | #define UART_SCCM_GRA ((ushort)0x0080) | ||
| 507 | #define UART_SCCM_BRKE ((ushort)0x0040) | ||
| 508 | #define UART_SCCM_BRKS ((ushort)0x0020) | ||
| 509 | #define UART_SCCM_CCR ((ushort)0x0008) | ||
| 510 | #define UART_SCCM_BSY ((ushort)0x0004) | ||
| 511 | #define UART_SCCM_TX ((ushort)0x0002) | ||
| 512 | #define UART_SCCM_RX ((ushort)0x0001) | ||
| 513 | |||
| 514 | /* The SCC PMSR when used as a UART. | ||
| 515 | */ | ||
| 516 | #define SCU_PSMR_FLC ((ushort)0x8000) | ||
| 517 | #define SCU_PSMR_SL ((ushort)0x4000) | ||
| 518 | #define SCU_PSMR_CL ((ushort)0x3000) | ||
| 519 | #define SCU_PSMR_UM ((ushort)0x0c00) | ||
| 520 | #define SCU_PSMR_FRZ ((ushort)0x0200) | ||
| 521 | #define SCU_PSMR_RZS ((ushort)0x0100) | ||
| 522 | #define SCU_PSMR_SYN ((ushort)0x0080) | ||
| 523 | #define SCU_PSMR_DRT ((ushort)0x0040) | ||
| 524 | #define SCU_PSMR_PEN ((ushort)0x0010) | ||
| 525 | #define SCU_PSMR_RPM ((ushort)0x000c) | ||
| 526 | #define SCU_PSMR_REVP ((ushort)0x0008) | ||
| 527 | #define SCU_PSMR_TPM ((ushort)0x0003) | ||
| 528 | #define SCU_PSMR_TEVP ((ushort)0x0002) | ||
| 529 | |||
| 530 | /* CPM Transparent mode SCC. | ||
| 531 | */ | ||
| 532 | typedef struct scc_trans { | ||
| 533 | sccp_t st_genscc; | ||
| 534 | uint st_cpres; /* Preset CRC */ | ||
| 535 | uint st_cmask; /* Constant mask for CRC */ | ||
| 536 | } scc_trans_t; | ||
| 537 | |||
| 538 | #define BD_SCC_TX_LAST ((ushort)0x0800) | ||
| 539 | |||
| 540 | /* IIC parameter RAM. | ||
| 541 | */ | ||
| 542 | typedef struct iic { | ||
| 543 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | ||
| 544 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | ||
| 545 | u_char iic_rfcr; /* Rx function code */ | ||
| 546 | u_char iic_tfcr; /* Tx function code */ | ||
| 547 | ushort iic_mrblr; /* Max receive buffer length */ | ||
| 548 | uint iic_rstate; /* Internal */ | ||
| 549 | uint iic_rdp; /* Internal */ | ||
| 550 | ushort iic_rbptr; /* Internal */ | ||
| 551 | ushort iic_rbc; /* Internal */ | ||
| 552 | uint iic_rxtmp; /* Internal */ | ||
| 553 | uint iic_tstate; /* Internal */ | ||
| 554 | uint iic_tdp; /* Internal */ | ||
| 555 | ushort iic_tbptr; /* Internal */ | ||
| 556 | ushort iic_tbc; /* Internal */ | ||
| 557 | uint iic_txtmp; /* Internal */ | ||
| 558 | char res1[4]; /* Reserved */ | ||
| 559 | ushort iic_rpbase; /* Relocation pointer */ | ||
| 560 | char res2[2]; /* Reserved */ | ||
| 561 | } iic_t; | ||
| 562 | |||
| 563 | #define BD_IIC_START ((ushort)0x0400) | ||
| 564 | |||
| 565 | /* SPI parameter RAM. | ||
| 566 | */ | ||
| 567 | typedef struct spi { | ||
| 568 | ushort spi_rbase; /* Rx Buffer descriptor base address */ | ||
| 569 | ushort spi_tbase; /* Tx Buffer descriptor base address */ | ||
| 570 | u_char spi_rfcr; /* Rx function code */ | ||
| 571 | u_char spi_tfcr; /* Tx function code */ | ||
| 572 | ushort spi_mrblr; /* Max receive buffer length */ | ||
| 573 | uint spi_rstate; /* Internal */ | ||
| 574 | uint spi_rdp; /* Internal */ | ||
| 575 | ushort spi_rbptr; /* Internal */ | ||
| 576 | ushort spi_rbc; /* Internal */ | ||
| 577 | uint spi_rxtmp; /* Internal */ | ||
| 578 | uint spi_tstate; /* Internal */ | ||
| 579 | uint spi_tdp; /* Internal */ | ||
| 580 | ushort spi_tbptr; /* Internal */ | ||
| 581 | ushort spi_tbc; /* Internal */ | ||
| 582 | uint spi_txtmp; /* Internal */ | ||
| 583 | uint spi_res; | ||
| 584 | ushort spi_rpbase; /* Relocation pointer */ | ||
| 585 | ushort spi_res2; | ||
| 586 | } spi_t; | ||
| 587 | |||
| 588 | /* SPI Mode register. | ||
| 589 | */ | ||
| 590 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ | ||
| 591 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ | ||
| 592 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ | ||
| 593 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ | ||
| 594 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ | ||
| 595 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ | ||
| 596 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ | ||
| 597 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ | ||
| 598 | #define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ | ||
| 599 | #define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ | ||
| 600 | #define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ | ||
| 601 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ | ||
| 602 | |||
| 603 | /* SPIE fields */ | ||
| 604 | #define SPIE_MME 0x20 | ||
| 605 | #define SPIE_TXE 0x10 | ||
| 606 | #define SPIE_BSY 0x04 | ||
| 607 | #define SPIE_TXB 0x02 | ||
| 608 | #define SPIE_RXB 0x01 | ||
| 609 | |||
| 610 | /* | ||
| 611 | * RISC Controller Configuration Register definitons | ||
| 612 | */ | ||
| 613 | #define RCCR_TIME 0x8000 /* RISC Timer Enable */ | ||
| 614 | #define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ | ||
| 615 | #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ | ||
| 616 | |||
| 617 | /* RISC Timer Parameter RAM offset */ | ||
| 618 | #define PROFF_RTMR ((uint)0x01B0) | ||
| 619 | |||
| 620 | typedef struct risc_timer_pram { | ||
| 621 | unsigned short tm_base; /* RISC Timer Table Base Address */ | ||
| 622 | unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ | ||
| 623 | unsigned short r_tmr; /* RISC Timer Mode Register */ | ||
| 624 | unsigned short r_tmv; /* RISC Timer Valid Register */ | ||
| 625 | unsigned long tm_cmd; /* RISC Timer Command Register */ | ||
| 626 | unsigned long tm_cnt; /* RISC Timer Internal Count */ | ||
| 627 | } rt_pram_t; | ||
| 628 | |||
| 629 | /* Bits in RISC Timer Command Register */ | ||
| 630 | #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ | ||
| 631 | #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ | ||
| 632 | #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ | ||
| 633 | #define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ | ||
| 634 | #define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ | ||
| 635 | |||
| 636 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM | ||
| 637 | * channels or devices. All of these are presented to the PPC core | ||
| 638 | * as a single interrupt. The CPM interrupt handler dispatches its | ||
| 639 | * own handlers, in a similar fashion to the PPC core handler. We | ||
| 640 | * use the table as defined in the manuals (i.e. no special high | ||
| 641 | * priority and SCC1 == SCCa, etc...). | ||
| 642 | */ | ||
| 643 | #define CPMVEC_NR 32 | ||
| 644 | #define CPMVEC_PIO_PC15 ((ushort)0x1f) | ||
| 645 | #define CPMVEC_SCC1 ((ushort)0x1e) | ||
| 646 | #define CPMVEC_SCC2 ((ushort)0x1d) | ||
| 647 | #define CPMVEC_SCC3 ((ushort)0x1c) | ||
| 648 | #define CPMVEC_SCC4 ((ushort)0x1b) | ||
| 649 | #define CPMVEC_PIO_PC14 ((ushort)0x1a) | ||
| 650 | #define CPMVEC_TIMER1 ((ushort)0x19) | ||
| 651 | #define CPMVEC_PIO_PC13 ((ushort)0x18) | ||
| 652 | #define CPMVEC_PIO_PC12 ((ushort)0x17) | ||
| 653 | #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) | ||
| 654 | #define CPMVEC_IDMA1 ((ushort)0x15) | ||
| 655 | #define CPMVEC_IDMA2 ((ushort)0x14) | ||
| 656 | #define CPMVEC_TIMER2 ((ushort)0x12) | ||
| 657 | #define CPMVEC_RISCTIMER ((ushort)0x11) | ||
| 658 | #define CPMVEC_I2C ((ushort)0x10) | ||
| 659 | #define CPMVEC_PIO_PC11 ((ushort)0x0f) | ||
| 660 | #define CPMVEC_PIO_PC10 ((ushort)0x0e) | ||
| 661 | #define CPMVEC_TIMER3 ((ushort)0x0c) | ||
| 662 | #define CPMVEC_PIO_PC9 ((ushort)0x0b) | ||
| 663 | #define CPMVEC_PIO_PC8 ((ushort)0x0a) | ||
| 664 | #define CPMVEC_PIO_PC7 ((ushort)0x09) | ||
| 665 | #define CPMVEC_TIMER4 ((ushort)0x07) | ||
| 666 | #define CPMVEC_PIO_PC6 ((ushort)0x06) | ||
| 667 | #define CPMVEC_SPI ((ushort)0x05) | ||
| 668 | #define CPMVEC_SMC1 ((ushort)0x04) | ||
| 669 | #define CPMVEC_SMC2 ((ushort)0x03) | ||
| 670 | #define CPMVEC_PIO_PC5 ((ushort)0x02) | ||
| 671 | #define CPMVEC_PIO_PC4 ((ushort)0x01) | ||
| 672 | #define CPMVEC_ERROR ((ushort)0x00) | ||
| 673 | |||
| 674 | /* CPM interrupt configuration vector. | ||
| 675 | */ | ||
| 676 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ | ||
| 677 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ | ||
| 678 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ | ||
| 679 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ | ||
| 680 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ | ||
| 681 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ | ||
| 682 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ | ||
| 683 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | ||
| 684 | |||
| 685 | extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); | ||
| 686 | extern void cpm_free_handler(int vec); | ||
| 687 | |||
| 688 | #endif /* __CPM1__ */ | ||
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h deleted file mode 100644 index 4c538228e42f..000000000000 --- a/include/asm-ppc/cpm2.h +++ /dev/null | |||
| @@ -1,1248 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Communication Processor Module v2. | ||
| 3 | * | ||
| 4 | * This file contains structures and information for the communication | ||
| 5 | * processor channels found in the dual port RAM or parameter RAM. | ||
| 6 | * All CPM control and status is available through the CPM2 internal | ||
| 7 | * memory map. See immap_cpm2.h for details. | ||
| 8 | */ | ||
| 9 | #ifdef __KERNEL__ | ||
| 10 | #ifndef __CPM2__ | ||
| 11 | #define __CPM2__ | ||
| 12 | |||
| 13 | #include <asm/immap_cpm2.h> | ||
| 14 | |||
| 15 | /* CPM Command register. | ||
| 16 | */ | ||
| 17 | #define CPM_CR_RST ((uint)0x80000000) | ||
| 18 | #define CPM_CR_PAGE ((uint)0x7c000000) | ||
| 19 | #define CPM_CR_SBLOCK ((uint)0x03e00000) | ||
| 20 | #define CPM_CR_FLG ((uint)0x00010000) | ||
| 21 | #define CPM_CR_MCN ((uint)0x00003fc0) | ||
| 22 | #define CPM_CR_OPCODE ((uint)0x0000000f) | ||
| 23 | |||
| 24 | /* Device sub-block and page codes. | ||
| 25 | */ | ||
| 26 | #define CPM_CR_SCC1_SBLOCK (0x04) | ||
| 27 | #define CPM_CR_SCC2_SBLOCK (0x05) | ||
| 28 | #define CPM_CR_SCC3_SBLOCK (0x06) | ||
| 29 | #define CPM_CR_SCC4_SBLOCK (0x07) | ||
| 30 | #define CPM_CR_SMC1_SBLOCK (0x08) | ||
| 31 | #define CPM_CR_SMC2_SBLOCK (0x09) | ||
| 32 | #define CPM_CR_SPI_SBLOCK (0x0a) | ||
| 33 | #define CPM_CR_I2C_SBLOCK (0x0b) | ||
| 34 | #define CPM_CR_TIMER_SBLOCK (0x0f) | ||
| 35 | #define CPM_CR_RAND_SBLOCK (0x0e) | ||
| 36 | #define CPM_CR_FCC1_SBLOCK (0x10) | ||
| 37 | #define CPM_CR_FCC2_SBLOCK (0x11) | ||
| 38 | #define CPM_CR_FCC3_SBLOCK (0x12) | ||
| 39 | #define CPM_CR_IDMA1_SBLOCK (0x14) | ||
| 40 | #define CPM_CR_IDMA2_SBLOCK (0x15) | ||
| 41 | #define CPM_CR_IDMA3_SBLOCK (0x16) | ||
| 42 | #define CPM_CR_IDMA4_SBLOCK (0x17) | ||
| 43 | #define CPM_CR_MCC1_SBLOCK (0x1c) | ||
| 44 | |||
| 45 | #define CPM_CR_FCC_SBLOCK(x) (x + 0x10) | ||
| 46 | |||
| 47 | #define CPM_CR_SCC1_PAGE (0x00) | ||
| 48 | #define CPM_CR_SCC2_PAGE (0x01) | ||
| 49 | #define CPM_CR_SCC3_PAGE (0x02) | ||
| 50 | #define CPM_CR_SCC4_PAGE (0x03) | ||
| 51 | #define CPM_CR_SMC1_PAGE (0x07) | ||
| 52 | #define CPM_CR_SMC2_PAGE (0x08) | ||
| 53 | #define CPM_CR_SPI_PAGE (0x09) | ||
| 54 | #define CPM_CR_I2C_PAGE (0x0a) | ||
| 55 | #define CPM_CR_TIMER_PAGE (0x0a) | ||
| 56 | #define CPM_CR_RAND_PAGE (0x0a) | ||
| 57 | #define CPM_CR_FCC1_PAGE (0x04) | ||
| 58 | #define CPM_CR_FCC2_PAGE (0x05) | ||
| 59 | #define CPM_CR_FCC3_PAGE (0x06) | ||
| 60 | #define CPM_CR_IDMA1_PAGE (0x07) | ||
| 61 | #define CPM_CR_IDMA2_PAGE (0x08) | ||
| 62 | #define CPM_CR_IDMA3_PAGE (0x09) | ||
| 63 | #define CPM_CR_IDMA4_PAGE (0x0a) | ||
| 64 | #define CPM_CR_MCC1_PAGE (0x07) | ||
| 65 | #define CPM_CR_MCC2_PAGE (0x08) | ||
| 66 | |||
| 67 | #define CPM_CR_FCC_PAGE(x) (x + 0x04) | ||
| 68 | |||
| 69 | /* Some opcodes (there are more...later) | ||
| 70 | */ | ||
| 71 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | ||
| 72 | #define CPM_CR_INIT_RX ((ushort)0x0001) | ||
| 73 | #define CPM_CR_INIT_TX ((ushort)0x0002) | ||
| 74 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | ||
| 75 | #define CPM_CR_STOP_TX ((ushort)0x0004) | ||
| 76 | #define CPM_CR_GRA_STOP_TX ((ushort)0x0005) | ||
| 77 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | ||
| 78 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | ||
| 79 | #define CPM_CR_START_IDMA ((ushort)0x0009) | ||
| 80 | #define CPM_CR_STOP_IDMA ((ushort)0x000b) | ||
| 81 | |||
| 82 | #define mk_cr_cmd(PG, SBC, MCN, OP) \ | ||
| 83 | ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) | ||
| 84 | |||
| 85 | /* Dual Port RAM addresses. The first 16K is available for almost | ||
| 86 | * any CPM use, so we put the BDs there. The first 128 bytes are | ||
| 87 | * used for SMC1 and SMC2 parameter RAM, so we start allocating | ||
| 88 | * BDs above that. All of this must change when we start | ||
| 89 | * downloading RAM microcode. | ||
| 90 | */ | ||
| 91 | #define CPM_DATAONLY_BASE ((uint)128) | ||
| 92 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) | ||
| 93 | #if defined(CONFIG_8272) | ||
| 94 | #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) | ||
| 95 | #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) | ||
| 96 | #else | ||
| 97 | #define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) | ||
| 98 | #define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) | ||
| 99 | #endif | ||
| 100 | |||
| 101 | /* The number of pages of host memory we allocate for CPM. This is | ||
| 102 | * done early in kernel initialization to get physically contiguous | ||
| 103 | * pages. | ||
| 104 | */ | ||
| 105 | #define NUM_CPM_HOST_PAGES 2 | ||
| 106 | |||
| 107 | /* Export the base address of the communication processor registers | ||
| 108 | * and dual port ram. | ||
| 109 | */ | ||
| 110 | extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ | ||
| 111 | |||
| 112 | extern unsigned long cpm_dpalloc(uint size, uint align); | ||
| 113 | extern int cpm_dpfree(unsigned long offset); | ||
| 114 | extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); | ||
| 115 | extern void cpm_dpdump(void); | ||
| 116 | extern void *cpm_dpram_addr(unsigned long offset); | ||
| 117 | extern void cpm_setbrg(uint brg, uint rate); | ||
| 118 | extern void cpm2_fastbrg(uint brg, uint rate, int div16); | ||
| 119 | extern void cpm2_reset(void); | ||
| 120 | |||
| 121 | |||
| 122 | /* Buffer descriptors used by many of the CPM protocols. | ||
| 123 | */ | ||
| 124 | typedef struct cpm_buf_desc { | ||
| 125 | ushort cbd_sc; /* Status and Control */ | ||
| 126 | ushort cbd_datlen; /* Data length in buffer */ | ||
| 127 | uint cbd_bufaddr; /* Buffer address in host memory */ | ||
| 128 | } cbd_t; | ||
| 129 | |||
| 130 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ | ||
| 131 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ | ||
| 132 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | ||
| 133 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | ||
| 134 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ | ||
| 135 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | ||
| 136 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | ||
| 137 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | ||
| 138 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | ||
| 139 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | ||
| 140 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | ||
| 141 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | ||
| 142 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ | ||
| 143 | |||
| 144 | /* Function code bits, usually generic to devices. | ||
| 145 | */ | ||
| 146 | #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ | ||
| 147 | #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ | ||
| 148 | #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ | ||
| 149 | #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ | ||
| 150 | #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ | ||
| 151 | |||
| 152 | /* Parameter RAM offsets from the base. | ||
| 153 | */ | ||
| 154 | #define PROFF_SCC1 ((uint)0x8000) | ||
| 155 | #define PROFF_SCC2 ((uint)0x8100) | ||
| 156 | #define PROFF_SCC3 ((uint)0x8200) | ||
| 157 | #define PROFF_SCC4 ((uint)0x8300) | ||
| 158 | #define PROFF_FCC1 ((uint)0x8400) | ||
| 159 | #define PROFF_FCC2 ((uint)0x8500) | ||
| 160 | #define PROFF_FCC3 ((uint)0x8600) | ||
| 161 | #define PROFF_MCC1 ((uint)0x8700) | ||
| 162 | #define PROFF_SMC1_BASE ((uint)0x87fc) | ||
| 163 | #define PROFF_IDMA1_BASE ((uint)0x87fe) | ||
| 164 | #define PROFF_MCC2 ((uint)0x8800) | ||
| 165 | #define PROFF_SMC2_BASE ((uint)0x88fc) | ||
| 166 | #define PROFF_IDMA2_BASE ((uint)0x88fe) | ||
| 167 | #define PROFF_SPI_BASE ((uint)0x89fc) | ||
| 168 | #define PROFF_IDMA3_BASE ((uint)0x89fe) | ||
| 169 | #define PROFF_TIMERS ((uint)0x8ae0) | ||
| 170 | #define PROFF_REVNUM ((uint)0x8af0) | ||
| 171 | #define PROFF_RAND ((uint)0x8af8) | ||
| 172 | #define PROFF_I2C_BASE ((uint)0x8afc) | ||
| 173 | #define PROFF_IDMA4_BASE ((uint)0x8afe) | ||
| 174 | |||
| 175 | #define PROFF_SCC_SIZE ((uint)0x100) | ||
| 176 | #define PROFF_FCC_SIZE ((uint)0x100) | ||
| 177 | #define PROFF_SMC_SIZE ((uint)64) | ||
| 178 | |||
| 179 | /* The SMCs are relocated to any of the first eight DPRAM pages. | ||
| 180 | * We will fix these at the first locations of DPRAM, until we | ||
| 181 | * get some microcode patches :-). | ||
| 182 | * The parameter ram space for the SMCs is fifty-some bytes, and | ||
| 183 | * they are required to start on a 64 byte boundary. | ||
| 184 | */ | ||
| 185 | #define PROFF_SMC1 (0) | ||
| 186 | #define PROFF_SMC2 (64) | ||
| 187 | |||
| 188 | |||
| 189 | /* Define enough so I can at least use the serial port as a UART. | ||
| 190 | */ | ||
| 191 | typedef struct smc_uart { | ||
| 192 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | ||
| 193 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | ||
| 194 | u_char smc_rfcr; /* Rx function code */ | ||
| 195 | u_char smc_tfcr; /* Tx function code */ | ||
| 196 | ushort smc_mrblr; /* Max receive buffer length */ | ||
| 197 | uint smc_rstate; /* Internal */ | ||
| 198 | uint smc_idp; /* Internal */ | ||
| 199 | ushort smc_rbptr; /* Internal */ | ||
| 200 | ushort smc_ibc; /* Internal */ | ||
| 201 | uint smc_rxtmp; /* Internal */ | ||
| 202 | uint smc_tstate; /* Internal */ | ||
| 203 | uint smc_tdp; /* Internal */ | ||
| 204 | ushort smc_tbptr; /* Internal */ | ||
| 205 | ushort smc_tbc; /* Internal */ | ||
| 206 | uint smc_txtmp; /* Internal */ | ||
| 207 | ushort smc_maxidl; /* Maximum idle characters */ | ||
| 208 | ushort smc_tmpidl; /* Temporary idle counter */ | ||
| 209 | ushort smc_brklen; /* Last received break length */ | ||
| 210 | ushort smc_brkec; /* rcv'd break condition counter */ | ||
| 211 | ushort smc_brkcr; /* xmt break count register */ | ||
| 212 | ushort smc_rmask; /* Temporary bit mask */ | ||
| 213 | uint smc_stmp; /* SDMA Temp */ | ||
| 214 | } smc_uart_t; | ||
| 215 | |||
| 216 | /* SMC uart mode register (Internal memory map). | ||
| 217 | */ | ||
| 218 | #define SMCMR_REN ((ushort)0x0001) | ||
| 219 | #define SMCMR_TEN ((ushort)0x0002) | ||
| 220 | #define SMCMR_DM ((ushort)0x000c) | ||
| 221 | #define SMCMR_SM_GCI ((ushort)0x0000) | ||
| 222 | #define SMCMR_SM_UART ((ushort)0x0020) | ||
| 223 | #define SMCMR_SM_TRANS ((ushort)0x0030) | ||
| 224 | #define SMCMR_SM_MASK ((ushort)0x0030) | ||
| 225 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | ||
| 226 | #define SMCMR_REVD SMCMR_PM_EVEN | ||
| 227 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | ||
| 228 | #define SMCMR_BS SMCMR_PEN | ||
| 229 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | ||
| 230 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | ||
| 231 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | ||
| 232 | |||
| 233 | /* SMC Event and Mask register. | ||
| 234 | */ | ||
| 235 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | ||
| 236 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | ||
| 237 | #define SMCM_TXE ((unsigned char)0x10) | ||
| 238 | #define SMCM_BSY ((unsigned char)0x04) | ||
| 239 | #define SMCM_TX ((unsigned char)0x02) | ||
| 240 | #define SMCM_RX ((unsigned char)0x01) | ||
| 241 | |||
| 242 | /* Baud rate generators. | ||
| 243 | */ | ||
| 244 | #define CPM_BRG_RST ((uint)0x00020000) | ||
| 245 | #define CPM_BRG_EN ((uint)0x00010000) | ||
| 246 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | ||
| 247 | #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) | ||
| 248 | #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) | ||
| 249 | #define CPM_BRG_ATB ((uint)0x00002000) | ||
| 250 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | ||
| 251 | #define CPM_BRG_DIV16 ((uint)0x00000001) | ||
| 252 | |||
| 253 | /* SCCs. | ||
| 254 | */ | ||
| 255 | #define SCC_GSMRH_IRP ((uint)0x00040000) | ||
| 256 | #define SCC_GSMRH_GDE ((uint)0x00010000) | ||
| 257 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | ||
| 258 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | ||
| 259 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | ||
| 260 | #define SCC_GSMRH_REVD ((uint)0x00002000) | ||
| 261 | #define SCC_GSMRH_TRX ((uint)0x00001000) | ||
| 262 | #define SCC_GSMRH_TTX ((uint)0x00000800) | ||
| 263 | #define SCC_GSMRH_CDP ((uint)0x00000400) | ||
| 264 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | ||
| 265 | #define SCC_GSMRH_CDS ((uint)0x00000100) | ||
| 266 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | ||
| 267 | #define SCC_GSMRH_TFL ((uint)0x00000040) | ||
| 268 | #define SCC_GSMRH_RFW ((uint)0x00000020) | ||
| 269 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | ||
| 270 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | ||
| 271 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | ||
| 272 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | ||
| 273 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | ||
| 274 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | ||
| 275 | |||
| 276 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | ||
| 277 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | ||
| 278 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | ||
| 279 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | ||
| 280 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | ||
| 281 | #define SCC_GSMRL_TCI ((uint)0x10000000) | ||
| 282 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | ||
| 283 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | ||
| 284 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | ||
| 285 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | ||
| 286 | #define SCC_GSMRL_RINV ((uint)0x02000000) | ||
| 287 | #define SCC_GSMRL_TINV ((uint)0x01000000) | ||
| 288 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | ||
| 289 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | ||
| 290 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | ||
| 291 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | ||
| 292 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | ||
| 293 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | ||
| 294 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | ||
| 295 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | ||
| 296 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | ||
| 297 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | ||
| 298 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | ||
| 299 | #define SCC_GSMRL_TEND ((uint)0x00040000) | ||
| 300 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | ||
| 301 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | ||
| 302 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | ||
| 303 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | ||
| 304 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | ||
| 305 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | ||
| 306 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | ||
| 307 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | ||
| 308 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | ||
| 309 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | ||
| 310 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | ||
| 311 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | ||
| 312 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | ||
| 313 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | ||
| 314 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | ||
| 315 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | ||
| 316 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | ||
| 317 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | ||
| 318 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | ||
| 319 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | ||
| 320 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | ||
| 321 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | ||
| 322 | #define SCC_GSMRL_ENR ((uint)0x00000020) | ||
| 323 | #define SCC_GSMRL_ENT ((uint)0x00000010) | ||
| 324 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | ||
| 325 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | ||
| 326 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | ||
| 327 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | ||
| 328 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | ||
| 329 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | ||
| 330 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | ||
| 331 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | ||
| 332 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | ||
| 333 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | ||
| 334 | |||
| 335 | #define SCC_TODR_TOD ((ushort)0x8000) | ||
| 336 | |||
| 337 | /* SCC Event and Mask register. | ||
| 338 | */ | ||
| 339 | #define SCCM_TXE ((unsigned char)0x10) | ||
| 340 | #define SCCM_BSY ((unsigned char)0x04) | ||
| 341 | #define SCCM_TX ((unsigned char)0x02) | ||
| 342 | #define SCCM_RX ((unsigned char)0x01) | ||
| 343 | |||
| 344 | typedef struct scc_param { | ||
| 345 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | ||
| 346 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | ||
| 347 | u_char scc_rfcr; /* Rx function code */ | ||
| 348 | u_char scc_tfcr; /* Tx function code */ | ||
| 349 | ushort scc_mrblr; /* Max receive buffer length */ | ||
| 350 | uint scc_rstate; /* Internal */ | ||
| 351 | uint scc_idp; /* Internal */ | ||
| 352 | ushort scc_rbptr; /* Internal */ | ||
| 353 | ushort scc_ibc; /* Internal */ | ||
| 354 | uint scc_rxtmp; /* Internal */ | ||
| 355 | uint scc_tstate; /* Internal */ | ||
| 356 | uint scc_tdp; /* Internal */ | ||
| 357 | ushort scc_tbptr; /* Internal */ | ||
| 358 | ushort scc_tbc; /* Internal */ | ||
| 359 | uint scc_txtmp; /* Internal */ | ||
| 360 | uint scc_rcrc; /* Internal */ | ||
| 361 | uint scc_tcrc; /* Internal */ | ||
| 362 | } sccp_t; | ||
| 363 | |||
| 364 | /* CPM Ethernet through SCC1. | ||
| 365 | */ | ||
| 366 | typedef struct scc_enet { | ||
| 367 | sccp_t sen_genscc; | ||
| 368 | uint sen_cpres; /* Preset CRC */ | ||
| 369 | uint sen_cmask; /* Constant mask for CRC */ | ||
| 370 | uint sen_crcec; /* CRC Error counter */ | ||
| 371 | uint sen_alec; /* alignment error counter */ | ||
| 372 | uint sen_disfc; /* discard frame counter */ | ||
| 373 | ushort sen_pads; /* Tx short frame pad character */ | ||
| 374 | ushort sen_retlim; /* Retry limit threshold */ | ||
| 375 | ushort sen_retcnt; /* Retry limit counter */ | ||
| 376 | ushort sen_maxflr; /* maximum frame length register */ | ||
| 377 | ushort sen_minflr; /* minimum frame length register */ | ||
| 378 | ushort sen_maxd1; /* maximum DMA1 length */ | ||
| 379 | ushort sen_maxd2; /* maximum DMA2 length */ | ||
| 380 | ushort sen_maxd; /* Rx max DMA */ | ||
| 381 | ushort sen_dmacnt; /* Rx DMA counter */ | ||
| 382 | ushort sen_maxb; /* Max BD byte count */ | ||
| 383 | ushort sen_gaddr1; /* Group address filter */ | ||
| 384 | ushort sen_gaddr2; | ||
| 385 | ushort sen_gaddr3; | ||
| 386 | ushort sen_gaddr4; | ||
| 387 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | ||
| 388 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | ||
| 389 | uint sen_tbuf0rba; /* Internal */ | ||
| 390 | uint sen_tbuf0crc; /* Internal */ | ||
| 391 | ushort sen_tbuf0bcnt; /* Internal */ | ||
| 392 | ushort sen_paddrh; /* physical address (MSB) */ | ||
| 393 | ushort sen_paddrm; | ||
| 394 | ushort sen_paddrl; /* physical address (LSB) */ | ||
| 395 | ushort sen_pper; /* persistence */ | ||
| 396 | ushort sen_rfbdptr; /* Rx first BD pointer */ | ||
| 397 | ushort sen_tfbdptr; /* Tx first BD pointer */ | ||
| 398 | ushort sen_tlbdptr; /* Tx last BD pointer */ | ||
| 399 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | ||
| 400 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | ||
| 401 | uint sen_tbuf1rba; /* Internal */ | ||
| 402 | uint sen_tbuf1crc; /* Internal */ | ||
| 403 | ushort sen_tbuf1bcnt; /* Internal */ | ||
| 404 | ushort sen_txlen; /* Tx Frame length counter */ | ||
| 405 | ushort sen_iaddr1; /* Individual address filter */ | ||
| 406 | ushort sen_iaddr2; | ||
| 407 | ushort sen_iaddr3; | ||
| 408 | ushort sen_iaddr4; | ||
| 409 | ushort sen_boffcnt; /* Backoff counter */ | ||
| 410 | |||
| 411 | /* NOTE: Some versions of the manual have the following items | ||
| 412 | * incorrectly documented. Below is the proper order. | ||
| 413 | */ | ||
| 414 | ushort sen_taddrh; /* temp address (MSB) */ | ||
| 415 | ushort sen_taddrm; | ||
| 416 | ushort sen_taddrl; /* temp address (LSB) */ | ||
| 417 | } scc_enet_t; | ||
| 418 | |||
| 419 | |||
| 420 | /* SCC Event register as used by Ethernet. | ||
| 421 | */ | ||
| 422 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | ||
| 423 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | ||
| 424 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | ||
| 425 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | ||
| 426 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | ||
| 427 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | ||
| 428 | |||
| 429 | /* SCC Mode Register (PSMR) as used by Ethernet. | ||
| 430 | */ | ||
| 431 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | ||
| 432 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | ||
| 433 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | ||
| 434 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | ||
| 435 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | ||
| 436 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | ||
| 437 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | ||
| 438 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | ||
| 439 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | ||
| 440 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | ||
| 441 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | ||
| 442 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | ||
| 443 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | ||
| 444 | |||
| 445 | /* Buffer descriptor control/status used by Ethernet receive. | ||
| 446 | * Common to SCC and FCC. | ||
| 447 | */ | ||
| 448 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | ||
| 449 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | ||
| 450 | #define BD_ENET_RX_INTR ((ushort)0x1000) | ||
| 451 | #define BD_ENET_RX_LAST ((ushort)0x0800) | ||
| 452 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | ||
| 453 | #define BD_ENET_RX_MISS ((ushort)0x0100) | ||
| 454 | #define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ | ||
| 455 | #define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ | ||
| 456 | #define BD_ENET_RX_LG ((ushort)0x0020) | ||
| 457 | #define BD_ENET_RX_NO ((ushort)0x0010) | ||
| 458 | #define BD_ENET_RX_SH ((ushort)0x0008) | ||
| 459 | #define BD_ENET_RX_CR ((ushort)0x0004) | ||
| 460 | #define BD_ENET_RX_OV ((ushort)0x0002) | ||
| 461 | #define BD_ENET_RX_CL ((ushort)0x0001) | ||
| 462 | #define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ | ||
| 463 | |||
| 464 | /* Buffer descriptor control/status used by Ethernet transmit. | ||
| 465 | * Common to SCC and FCC. | ||
| 466 | */ | ||
| 467 | #define BD_ENET_TX_READY ((ushort)0x8000) | ||
| 468 | #define BD_ENET_TX_PAD ((ushort)0x4000) | ||
| 469 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | ||
| 470 | #define BD_ENET_TX_INTR ((ushort)0x1000) | ||
| 471 | #define BD_ENET_TX_LAST ((ushort)0x0800) | ||
| 472 | #define BD_ENET_TX_TC ((ushort)0x0400) | ||
| 473 | #define BD_ENET_TX_DEF ((ushort)0x0200) | ||
| 474 | #define BD_ENET_TX_HB ((ushort)0x0100) | ||
| 475 | #define BD_ENET_TX_LC ((ushort)0x0080) | ||
| 476 | #define BD_ENET_TX_RL ((ushort)0x0040) | ||
| 477 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | ||
| 478 | #define BD_ENET_TX_UN ((ushort)0x0002) | ||
| 479 | #define BD_ENET_TX_CSL ((ushort)0x0001) | ||
| 480 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | ||
| 481 | |||
| 482 | /* SCC as UART | ||
| 483 | */ | ||
| 484 | typedef struct scc_uart { | ||
| 485 | sccp_t scc_genscc; | ||
| 486 | uint scc_res1; /* Reserved */ | ||
| 487 | uint scc_res2; /* Reserved */ | ||
| 488 | ushort scc_maxidl; /* Maximum idle chars */ | ||
| 489 | ushort scc_idlc; /* temp idle counter */ | ||
| 490 | ushort scc_brkcr; /* Break count register */ | ||
| 491 | ushort scc_parec; /* receive parity error counter */ | ||
| 492 | ushort scc_frmec; /* receive framing error counter */ | ||
| 493 | ushort scc_nosec; /* receive noise counter */ | ||
| 494 | ushort scc_brkec; /* receive break condition counter */ | ||
| 495 | ushort scc_brkln; /* last received break length */ | ||
| 496 | ushort scc_uaddr1; /* UART address character 1 */ | ||
| 497 | ushort scc_uaddr2; /* UART address character 2 */ | ||
| 498 | ushort scc_rtemp; /* Temp storage */ | ||
| 499 | ushort scc_toseq; /* Transmit out of sequence char */ | ||
| 500 | ushort scc_char1; /* control character 1 */ | ||
| 501 | ushort scc_char2; /* control character 2 */ | ||
| 502 | ushort scc_char3; /* control character 3 */ | ||
| 503 | ushort scc_char4; /* control character 4 */ | ||
| 504 | ushort scc_char5; /* control character 5 */ | ||
| 505 | ushort scc_char6; /* control character 6 */ | ||
| 506 | ushort scc_char7; /* control character 7 */ | ||
| 507 | ushort scc_char8; /* control character 8 */ | ||
| 508 | ushort scc_rccm; /* receive control character mask */ | ||
| 509 | ushort scc_rccr; /* receive control character register */ | ||
| 510 | ushort scc_rlbc; /* receive last break character */ | ||
| 511 | } scc_uart_t; | ||
| 512 | |||
| 513 | /* SCC Event and Mask registers when it is used as a UART. | ||
| 514 | */ | ||
| 515 | #define UART_SCCM_GLR ((ushort)0x1000) | ||
| 516 | #define UART_SCCM_GLT ((ushort)0x0800) | ||
| 517 | #define UART_SCCM_AB ((ushort)0x0200) | ||
| 518 | #define UART_SCCM_IDL ((ushort)0x0100) | ||
| 519 | #define UART_SCCM_GRA ((ushort)0x0080) | ||
| 520 | #define UART_SCCM_BRKE ((ushort)0x0040) | ||
| 521 | #define UART_SCCM_BRKS ((ushort)0x0020) | ||
| 522 | #define UART_SCCM_CCR ((ushort)0x0008) | ||
| 523 | #define UART_SCCM_BSY ((ushort)0x0004) | ||
| 524 | #define UART_SCCM_TX ((ushort)0x0002) | ||
| 525 | #define UART_SCCM_RX ((ushort)0x0001) | ||
| 526 | |||
| 527 | /* The SCC PSMR when used as a UART. | ||
| 528 | */ | ||
| 529 | #define SCU_PSMR_FLC ((ushort)0x8000) | ||
| 530 | #define SCU_PSMR_SL ((ushort)0x4000) | ||
| 531 | #define SCU_PSMR_CL ((ushort)0x3000) | ||
| 532 | #define SCU_PSMR_UM ((ushort)0x0c00) | ||
| 533 | #define SCU_PSMR_FRZ ((ushort)0x0200) | ||
| 534 | #define SCU_PSMR_RZS ((ushort)0x0100) | ||
| 535 | #define SCU_PSMR_SYN ((ushort)0x0080) | ||
| 536 | #define SCU_PSMR_DRT ((ushort)0x0040) | ||
| 537 | #define SCU_PSMR_PEN ((ushort)0x0010) | ||
| 538 | #define SCU_PSMR_RPM ((ushort)0x000c) | ||
| 539 | #define SCU_PSMR_REVP ((ushort)0x0008) | ||
| 540 | #define SCU_PSMR_TPM ((ushort)0x0003) | ||
| 541 | #define SCU_PSMR_TEVP ((ushort)0x0002) | ||
| 542 | |||
| 543 | /* CPM Transparent mode SCC. | ||
| 544 | */ | ||
| 545 | typedef struct scc_trans { | ||
| 546 | sccp_t st_genscc; | ||
| 547 | uint st_cpres; /* Preset CRC */ | ||
| 548 | uint st_cmask; /* Constant mask for CRC */ | ||
| 549 | } scc_trans_t; | ||
| 550 | |||
| 551 | #define BD_SCC_TX_LAST ((ushort)0x0800) | ||
| 552 | |||
| 553 | /* How about some FCCs..... | ||
| 554 | */ | ||
| 555 | #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) | ||
| 556 | #define FCC_GFMR_DIAG_LE ((uint)0x40000000) | ||
| 557 | #define FCC_GFMR_DIAG_AE ((uint)0x80000000) | ||
| 558 | #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) | ||
| 559 | #define FCC_GFMR_TCI ((uint)0x20000000) | ||
| 560 | #define FCC_GFMR_TRX ((uint)0x10000000) | ||
| 561 | #define FCC_GFMR_TTX ((uint)0x08000000) | ||
| 562 | #define FCC_GFMR_TTX ((uint)0x08000000) | ||
| 563 | #define FCC_GFMR_CDP ((uint)0x04000000) | ||
| 564 | #define FCC_GFMR_CTSP ((uint)0x02000000) | ||
| 565 | #define FCC_GFMR_CDS ((uint)0x01000000) | ||
| 566 | #define FCC_GFMR_CTSS ((uint)0x00800000) | ||
| 567 | #define FCC_GFMR_SYNL_NONE ((uint)0x00000000) | ||
| 568 | #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) | ||
| 569 | #define FCC_GFMR_SYNL_8 ((uint)0x00008000) | ||
| 570 | #define FCC_GFMR_SYNL_16 ((uint)0x0000c000) | ||
| 571 | #define FCC_GFMR_RTSM ((uint)0x00002000) | ||
| 572 | #define FCC_GFMR_RENC_NRZ ((uint)0x00000000) | ||
| 573 | #define FCC_GFMR_RENC_NRZI ((uint)0x00000800) | ||
| 574 | #define FCC_GFMR_REVD ((uint)0x00000400) | ||
| 575 | #define FCC_GFMR_TENC_NRZ ((uint)0x00000000) | ||
| 576 | #define FCC_GFMR_TENC_NRZI ((uint)0x00000100) | ||
| 577 | #define FCC_GFMR_TCRC_16 ((uint)0x00000000) | ||
| 578 | #define FCC_GFMR_TCRC_32 ((uint)0x00000080) | ||
| 579 | #define FCC_GFMR_ENR ((uint)0x00000020) | ||
| 580 | #define FCC_GFMR_ENT ((uint)0x00000010) | ||
| 581 | #define FCC_GFMR_MODE_ENET ((uint)0x0000000c) | ||
| 582 | #define FCC_GFMR_MODE_ATM ((uint)0x0000000a) | ||
| 583 | #define FCC_GFMR_MODE_HDLC ((uint)0x00000000) | ||
| 584 | |||
| 585 | /* Generic FCC parameter ram. | ||
| 586 | */ | ||
| 587 | typedef struct fcc_param { | ||
| 588 | ushort fcc_riptr; /* Rx Internal temp pointer */ | ||
| 589 | ushort fcc_tiptr; /* Tx Internal temp pointer */ | ||
| 590 | ushort fcc_res1; | ||
| 591 | ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ | ||
| 592 | uint fcc_rstate; /* Upper byte is Func code, must be set */ | ||
| 593 | uint fcc_rbase; /* Receive BD base */ | ||
| 594 | ushort fcc_rbdstat; /* RxBD status */ | ||
| 595 | ushort fcc_rbdlen; /* RxBD down counter */ | ||
| 596 | uint fcc_rdptr; /* RxBD internal data pointer */ | ||
| 597 | uint fcc_tstate; /* Upper byte is Func code, must be set */ | ||
| 598 | uint fcc_tbase; /* Transmit BD base */ | ||
| 599 | ushort fcc_tbdstat; /* TxBD status */ | ||
| 600 | ushort fcc_tbdlen; /* TxBD down counter */ | ||
| 601 | uint fcc_tdptr; /* TxBD internal data pointer */ | ||
| 602 | uint fcc_rbptr; /* Rx BD Internal buf pointer */ | ||
| 603 | uint fcc_tbptr; /* Tx BD Internal buf pointer */ | ||
| 604 | uint fcc_rcrc; /* Rx temp CRC */ | ||
| 605 | uint fcc_res2; | ||
| 606 | uint fcc_tcrc; /* Tx temp CRC */ | ||
| 607 | } fccp_t; | ||
| 608 | |||
| 609 | |||
| 610 | /* Ethernet controller through FCC. | ||
| 611 | */ | ||
| 612 | typedef struct fcc_enet { | ||
| 613 | fccp_t fen_genfcc; | ||
| 614 | uint fen_statbuf; /* Internal status buffer */ | ||
| 615 | uint fen_camptr; /* CAM address */ | ||
| 616 | uint fen_cmask; /* Constant mask for CRC */ | ||
| 617 | uint fen_cpres; /* Preset CRC */ | ||
| 618 | uint fen_crcec; /* CRC Error counter */ | ||
| 619 | uint fen_alec; /* alignment error counter */ | ||
| 620 | uint fen_disfc; /* discard frame counter */ | ||
| 621 | ushort fen_retlim; /* Retry limit */ | ||
| 622 | ushort fen_retcnt; /* Retry counter */ | ||
| 623 | ushort fen_pper; /* Persistence */ | ||
| 624 | ushort fen_boffcnt; /* backoff counter */ | ||
| 625 | uint fen_gaddrh; /* Group address filter, high 32-bits */ | ||
| 626 | uint fen_gaddrl; /* Group address filter, low 32-bits */ | ||
| 627 | ushort fen_tfcstat; /* out of sequence TxBD */ | ||
| 628 | ushort fen_tfclen; | ||
| 629 | uint fen_tfcptr; | ||
| 630 | ushort fen_mflr; /* Maximum frame length (1518) */ | ||
| 631 | ushort fen_paddrh; /* MAC address */ | ||
| 632 | ushort fen_paddrm; | ||
| 633 | ushort fen_paddrl; | ||
| 634 | ushort fen_ibdcount; /* Internal BD counter */ | ||
| 635 | ushort fen_ibdstart; /* Internal BD start pointer */ | ||
| 636 | ushort fen_ibdend; /* Internal BD end pointer */ | ||
| 637 | ushort fen_txlen; /* Internal Tx frame length counter */ | ||
| 638 | uint fen_ibdbase[8]; /* Internal use */ | ||
| 639 | uint fen_iaddrh; /* Individual address filter */ | ||
| 640 | uint fen_iaddrl; | ||
| 641 | ushort fen_minflr; /* Minimum frame length (64) */ | ||
| 642 | ushort fen_taddrh; /* Filter transfer MAC address */ | ||
| 643 | ushort fen_taddrm; | ||
| 644 | ushort fen_taddrl; | ||
| 645 | ushort fen_padptr; /* Pointer to pad byte buffer */ | ||
| 646 | ushort fen_cftype; /* control frame type */ | ||
| 647 | ushort fen_cfrange; /* control frame range */ | ||
| 648 | ushort fen_maxb; /* maximum BD count */ | ||
| 649 | ushort fen_maxd1; /* Max DMA1 length (1520) */ | ||
| 650 | ushort fen_maxd2; /* Max DMA2 length (1520) */ | ||
| 651 | ushort fen_maxd; /* internal max DMA count */ | ||
| 652 | ushort fen_dmacnt; /* internal DMA counter */ | ||
| 653 | uint fen_octc; /* Total octect counter */ | ||
| 654 | uint fen_colc; /* Total collision counter */ | ||
| 655 | uint fen_broc; /* Total broadcast packet counter */ | ||
| 656 | uint fen_mulc; /* Total multicast packet count */ | ||
| 657 | uint fen_uspc; /* Total packets < 64 bytes */ | ||
| 658 | uint fen_frgc; /* Total packets < 64 bytes with errors */ | ||
| 659 | uint fen_ospc; /* Total packets > 1518 */ | ||
| 660 | uint fen_jbrc; /* Total packets > 1518 with errors */ | ||
| 661 | uint fen_p64c; /* Total packets == 64 bytes */ | ||
| 662 | uint fen_p65c; /* Total packets 64 < bytes <= 127 */ | ||
| 663 | uint fen_p128c; /* Total packets 127 < bytes <= 255 */ | ||
| 664 | uint fen_p256c; /* Total packets 256 < bytes <= 511 */ | ||
| 665 | uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ | ||
| 666 | uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ | ||
| 667 | uint fen_cambuf; /* Internal CAM buffer poiner */ | ||
| 668 | ushort fen_rfthr; /* Received frames threshold */ | ||
| 669 | ushort fen_rfcnt; /* Received frames count */ | ||
| 670 | } fcc_enet_t; | ||
| 671 | |||
| 672 | /* FCC Event/Mask register as used by Ethernet. | ||
| 673 | */ | ||
| 674 | #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | ||
| 675 | #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ | ||
| 676 | #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ | ||
| 677 | #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | ||
| 678 | #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ | ||
| 679 | #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ | ||
| 680 | #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | ||
| 681 | #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | ||
| 682 | |||
| 683 | /* FCC Mode Register (FPSMR) as used by Ethernet. | ||
| 684 | */ | ||
| 685 | #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ | ||
| 686 | #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ | ||
| 687 | #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ | ||
| 688 | #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ | ||
| 689 | #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ | ||
| 690 | #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ | ||
| 691 | #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ | ||
| 692 | #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ | ||
| 693 | #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ | ||
| 694 | #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ | ||
| 695 | #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ | ||
| 696 | #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ | ||
| 697 | #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ | ||
| 698 | |||
| 699 | /* IIC parameter RAM. | ||
| 700 | */ | ||
| 701 | typedef struct iic { | ||
| 702 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | ||
| 703 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | ||
| 704 | u_char iic_rfcr; /* Rx function code */ | ||
| 705 | u_char iic_tfcr; /* Tx function code */ | ||
| 706 | ushort iic_mrblr; /* Max receive buffer length */ | ||
| 707 | uint iic_rstate; /* Internal */ | ||
| 708 | uint iic_rdp; /* Internal */ | ||
| 709 | ushort iic_rbptr; /* Internal */ | ||
| 710 | ushort iic_rbc; /* Internal */ | ||
| 711 | uint iic_rxtmp; /* Internal */ | ||
| 712 | uint iic_tstate; /* Internal */ | ||
| 713 | uint iic_tdp; /* Internal */ | ||
| 714 | ushort iic_tbptr; /* Internal */ | ||
| 715 | ushort iic_tbc; /* Internal */ | ||
| 716 | uint iic_txtmp; /* Internal */ | ||
| 717 | } iic_t; | ||
| 718 | |||
| 719 | /* SPI parameter RAM. | ||
| 720 | */ | ||
| 721 | typedef struct spi { | ||
| 722 | ushort spi_rbase; /* Rx Buffer descriptor base address */ | ||
| 723 | ushort spi_tbase; /* Tx Buffer descriptor base address */ | ||
| 724 | u_char spi_rfcr; /* Rx function code */ | ||
| 725 | u_char spi_tfcr; /* Tx function code */ | ||
| 726 | ushort spi_mrblr; /* Max receive buffer length */ | ||
| 727 | uint spi_rstate; /* Internal */ | ||
| 728 | uint spi_rdp; /* Internal */ | ||
| 729 | ushort spi_rbptr; /* Internal */ | ||
| 730 | ushort spi_rbc; /* Internal */ | ||
| 731 | uint spi_rxtmp; /* Internal */ | ||
| 732 | uint spi_tstate; /* Internal */ | ||
| 733 | uint spi_tdp; /* Internal */ | ||
| 734 | ushort spi_tbptr; /* Internal */ | ||
| 735 | ushort spi_tbc; /* Internal */ | ||
| 736 | uint spi_txtmp; /* Internal */ | ||
| 737 | uint spi_res; /* Tx temp. */ | ||
| 738 | uint spi_res1[4]; /* SDMA temp. */ | ||
| 739 | } spi_t; | ||
| 740 | |||
| 741 | /* SPI Mode register. | ||
| 742 | */ | ||
| 743 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ | ||
| 744 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ | ||
| 745 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ | ||
| 746 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ | ||
| 747 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ | ||
| 748 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ | ||
| 749 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ | ||
| 750 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ | ||
| 751 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ | ||
| 752 | |||
| 753 | #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) | ||
| 754 | #define SPMODE_PM(x) ((x) &0xF) | ||
| 755 | |||
| 756 | #define SPI_EB ((u_char)0x10) /* big endian byte order */ | ||
| 757 | |||
| 758 | #define BD_IIC_START ((ushort)0x0400) | ||
| 759 | |||
| 760 | /* IDMA parameter RAM | ||
| 761 | */ | ||
| 762 | typedef struct idma { | ||
| 763 | ushort ibase; /* IDMA buffer descriptor table base address */ | ||
| 764 | ushort dcm; /* DMA channel mode */ | ||
| 765 | ushort ibdptr; /* IDMA current buffer descriptor pointer */ | ||
| 766 | ushort dpr_buf; /* IDMA transfer buffer base address */ | ||
| 767 | ushort buf_inv; /* internal buffer inventory */ | ||
| 768 | ushort ss_max; /* steady-state maximum transfer size */ | ||
| 769 | ushort dpr_in_ptr; /* write pointer inside the internal buffer */ | ||
| 770 | ushort sts; /* source transfer size */ | ||
| 771 | ushort dpr_out_ptr; /* read pointer inside the internal buffer */ | ||
| 772 | ushort seob; /* source end of burst */ | ||
| 773 | ushort deob; /* destination end of burst */ | ||
| 774 | ushort dts; /* destination transfer size */ | ||
| 775 | ushort ret_add; /* return address when working in ERM=1 mode */ | ||
| 776 | ushort res0; /* reserved */ | ||
| 777 | uint bd_cnt; /* internal byte count */ | ||
| 778 | uint s_ptr; /* source internal data pointer */ | ||
| 779 | uint d_ptr; /* destination internal data pointer */ | ||
| 780 | uint istate; /* internal state */ | ||
| 781 | u_char res1[20]; /* pad to 64-byte length */ | ||
| 782 | } idma_t; | ||
| 783 | |||
| 784 | /* DMA channel mode bit fields | ||
| 785 | */ | ||
| 786 | #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ | ||
| 787 | #define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ | ||
| 788 | #define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ | ||
| 789 | #define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ | ||
| 790 | #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ | ||
| 791 | #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ | ||
| 792 | #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ | ||
| 793 | #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ | ||
| 794 | #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ | ||
| 795 | #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ | ||
| 796 | #define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ | ||
| 797 | #define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ | ||
| 798 | #define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ | ||
| 799 | #define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ | ||
| 800 | #define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ | ||
| 801 | #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ | ||
| 802 | #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ | ||
| 803 | #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ | ||
| 804 | |||
| 805 | /* IDMA Buffer Descriptors | ||
| 806 | */ | ||
| 807 | typedef struct idma_bd { | ||
| 808 | uint flags; | ||
| 809 | uint len; /* data length */ | ||
| 810 | uint src; /* source data buffer pointer */ | ||
| 811 | uint dst; /* destination data buffer pointer */ | ||
| 812 | } idma_bd_t; | ||
| 813 | |||
| 814 | /* IDMA buffer descriptor flag bit fields | ||
| 815 | */ | ||
| 816 | #define IDMA_BD_V ((uint)0x80000000) /* valid */ | ||
| 817 | #define IDMA_BD_W ((uint)0x20000000) /* wrap */ | ||
| 818 | #define IDMA_BD_I ((uint)0x10000000) /* interrupt */ | ||
| 819 | #define IDMA_BD_L ((uint)0x08000000) /* last */ | ||
| 820 | #define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ | ||
| 821 | #define IDMA_BD_SDN ((uint)0x00400000) /* source done */ | ||
| 822 | #define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ | ||
| 823 | #define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ | ||
| 824 | #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ | ||
| 825 | #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ | ||
| 826 | #define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ | ||
| 827 | #define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ | ||
| 828 | #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ | ||
| 829 | #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ | ||
| 830 | #define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ | ||
| 831 | |||
| 832 | /* per-channel IDMA registers | ||
| 833 | */ | ||
| 834 | typedef struct im_idma { | ||
| 835 | u_char idsr; /* IDMAn event status register */ | ||
| 836 | u_char res0[3]; | ||
| 837 | u_char idmr; /* IDMAn event mask register */ | ||
| 838 | u_char res1[3]; | ||
| 839 | } im_idma_t; | ||
| 840 | |||
| 841 | /* IDMA event register bit fields | ||
| 842 | */ | ||
| 843 | #define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ | ||
| 844 | #define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ | ||
| 845 | #define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ | ||
| 846 | #define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ | ||
| 847 | |||
| 848 | /* RISC Controller Configuration Register (RCCR) bit fields | ||
| 849 | */ | ||
| 850 | #define RCCR_TIME ((uint)0x80000000) /* timer enable */ | ||
| 851 | #define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ | ||
| 852 | #define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ | ||
| 853 | #define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ | ||
| 854 | #define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ | ||
| 855 | #define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ | ||
| 856 | #define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ | ||
| 857 | #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ | ||
| 858 | #define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ | ||
| 859 | #define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ | ||
| 860 | #define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ | ||
| 861 | #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ | ||
| 862 | #define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ | ||
| 863 | #define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ | ||
| 864 | #define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ | ||
| 865 | #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ | ||
| 866 | #define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ | ||
| 867 | #define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ | ||
| 868 | #define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ | ||
| 869 | #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ | ||
| 870 | #define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ | ||
| 871 | #define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ | ||
| 872 | #define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ | ||
| 873 | #define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ | ||
| 874 | #define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ | ||
| 875 | #define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ | ||
| 876 | #define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ | ||
| 877 | #define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ | ||
| 878 | #define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ | ||
| 879 | #define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ | ||
| 880 | #define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ | ||
| 881 | #define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ | ||
| 882 | #define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ | ||
| 883 | #define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ | ||
| 884 | #define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ | ||
| 885 | #define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ | ||
| 886 | #define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ | ||
| 887 | #define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ | ||
| 888 | |||
| 889 | /*----------------------------------------------------------------------- | ||
| 890 | * CMXFCR - CMX FCC Clock Route Register | ||
| 891 | */ | ||
| 892 | #define CMXFCR_FC1 0x40000000 /* FCC1 connection */ | ||
| 893 | #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ | ||
| 894 | #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ | ||
| 895 | #define CMXFCR_FC2 0x00400000 /* FCC2 connection */ | ||
| 896 | #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ | ||
| 897 | #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ | ||
| 898 | #define CMXFCR_FC3 0x00004000 /* FCC3 connection */ | ||
| 899 | #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ | ||
| 900 | #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ | ||
| 901 | |||
| 902 | #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ | ||
| 903 | #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ | ||
| 904 | #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ | ||
| 905 | #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ | ||
| 906 | #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ | ||
| 907 | #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ | ||
| 908 | #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ | ||
| 909 | #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ | ||
| 910 | |||
| 911 | #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ | ||
| 912 | #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ | ||
| 913 | #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ | ||
| 914 | #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ | ||
| 915 | #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ | ||
| 916 | #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ | ||
| 917 | #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ | ||
| 918 | #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ | ||
| 919 | |||
| 920 | #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ | ||
| 921 | #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ | ||
| 922 | #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ | ||
| 923 | #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ | ||
| 924 | #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ | ||
| 925 | #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ | ||
| 926 | #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ | ||
| 927 | #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ | ||
| 928 | |||
| 929 | #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ | ||
| 930 | #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ | ||
| 931 | #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ | ||
| 932 | #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ | ||
| 933 | #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ | ||
| 934 | #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ | ||
| 935 | #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ | ||
| 936 | #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ | ||
| 937 | |||
| 938 | #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ | ||
| 939 | #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ | ||
| 940 | #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ | ||
| 941 | #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ | ||
| 942 | #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ | ||
| 943 | #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ | ||
| 944 | #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ | ||
| 945 | #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ | ||
| 946 | |||
| 947 | #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ | ||
| 948 | #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ | ||
| 949 | #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ | ||
| 950 | #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ | ||
| 951 | #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ | ||
| 952 | #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ | ||
| 953 | #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ | ||
| 954 | #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ | ||
| 955 | |||
| 956 | /*----------------------------------------------------------------------- | ||
| 957 | * CMXSCR - CMX SCC Clock Route Register | ||
| 958 | */ | ||
| 959 | #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ | ||
| 960 | #define CMXSCR_SC1 0x40000000 /* SCC1 connection */ | ||
| 961 | #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ | ||
| 962 | #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ | ||
| 963 | #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ | ||
| 964 | #define CMXSCR_SC2 0x00400000 /* SCC2 connection */ | ||
| 965 | #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ | ||
| 966 | #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ | ||
| 967 | #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ | ||
| 968 | #define CMXSCR_SC3 0x00004000 /* SCC3 connection */ | ||
| 969 | #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ | ||
| 970 | #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ | ||
| 971 | #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ | ||
| 972 | #define CMXSCR_SC4 0x00000040 /* SCC4 connection */ | ||
| 973 | #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ | ||
| 974 | #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ | ||
| 975 | |||
| 976 | #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ | ||
| 977 | #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ | ||
| 978 | #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ | ||
| 979 | #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ | ||
| 980 | #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ | ||
| 981 | #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ | ||
| 982 | #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ | ||
| 983 | #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ | ||
| 984 | |||
| 985 | #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ | ||
| 986 | #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ | ||
| 987 | #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ | ||
| 988 | #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ | ||
| 989 | #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ | ||
| 990 | #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ | ||
| 991 | #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ | ||
| 992 | #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ | ||
| 993 | |||
| 994 | #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ | ||
| 995 | #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ | ||
| 996 | #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ | ||
| 997 | #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ | ||
| 998 | #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ | ||
| 999 | #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ | ||
| 1000 | #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ | ||
| 1001 | #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ | ||
| 1002 | |||
| 1003 | #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ | ||
| 1004 | #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ | ||
| 1005 | #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ | ||
| 1006 | #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ | ||
| 1007 | #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ | ||
| 1008 | #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ | ||
| 1009 | #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ | ||
| 1010 | #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ | ||
| 1011 | |||
| 1012 | #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ | ||
| 1013 | #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ | ||
| 1014 | #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ | ||
| 1015 | #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ | ||
| 1016 | #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ | ||
| 1017 | #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ | ||
| 1018 | #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ | ||
| 1019 | #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ | ||
| 1020 | |||
| 1021 | #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ | ||
| 1022 | #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ | ||
| 1023 | #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ | ||
| 1024 | #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ | ||
| 1025 | #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ | ||
| 1026 | #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ | ||
| 1027 | #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ | ||
| 1028 | #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ | ||
| 1029 | |||
| 1030 | #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ | ||
| 1031 | #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ | ||
| 1032 | #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ | ||
| 1033 | #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ | ||
| 1034 | #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ | ||
| 1035 | #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ | ||
| 1036 | #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ | ||
| 1037 | #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ | ||
| 1038 | |||
| 1039 | #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ | ||
| 1040 | #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ | ||
| 1041 | #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ | ||
| 1042 | #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ | ||
| 1043 | #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ | ||
| 1044 | #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ | ||
| 1045 | #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ | ||
| 1046 | #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ | ||
| 1047 | |||
| 1048 | /*----------------------------------------------------------------------- | ||
| 1049 | * SIUMCR - SIU Module Configuration Register 4-31 | ||
| 1050 | */ | ||
| 1051 | #define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ | ||
| 1052 | #define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ | ||
| 1053 | #define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ | ||
| 1054 | #define SIUMCR_CDIS 0x10000000 /* Core Disable */ | ||
| 1055 | #define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ | ||
| 1056 | #define SIUMCR_DPPC01 0x04000000 /* - " - */ | ||
| 1057 | #define SIUMCR_DPPC10 0x08000000 /* - " - */ | ||
| 1058 | #define SIUMCR_DPPC11 0x0c000000 /* - " - */ | ||
| 1059 | #define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ | ||
| 1060 | #define SIUMCR_L2CPC01 0x01000000 /* - " - */ | ||
| 1061 | #define SIUMCR_L2CPC10 0x02000000 /* - " - */ | ||
| 1062 | #define SIUMCR_L2CPC11 0x03000000 /* - " - */ | ||
| 1063 | #define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ | ||
| 1064 | #define SIUMCR_LBPC01 0x00400000 /* - " - */ | ||
| 1065 | #define SIUMCR_LBPC10 0x00800000 /* - " - */ | ||
| 1066 | #define SIUMCR_LBPC11 0x00c00000 /* - " - */ | ||
| 1067 | #define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ | ||
| 1068 | #define SIUMCR_APPC01 0x00100000 /* - " - */ | ||
| 1069 | #define SIUMCR_APPC10 0x00200000 /* - " - */ | ||
| 1070 | #define SIUMCR_APPC11 0x00300000 /* - " - */ | ||
| 1071 | #define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ | ||
| 1072 | #define SIUMCR_CS10PC01 0x00040000 /* - " - */ | ||
| 1073 | #define SIUMCR_CS10PC10 0x00080000 /* - " - */ | ||
| 1074 | #define SIUMCR_CS10PC11 0x000c0000 /* - " - */ | ||
| 1075 | #define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ | ||
| 1076 | #define SIUMCR_BCTLC01 0x00010000 /* - " - */ | ||
| 1077 | #define SIUMCR_BCTLC10 0x00020000 /* - " - */ | ||
| 1078 | #define SIUMCR_BCTLC11 0x00030000 /* - " - */ | ||
| 1079 | #define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ | ||
| 1080 | #define SIUMCR_MMR01 0x00004000 /* - " - */ | ||
| 1081 | #define SIUMCR_MMR10 0x00008000 /* - " - */ | ||
| 1082 | #define SIUMCR_MMR11 0x0000c000 /* - " - */ | ||
| 1083 | #define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ | ||
| 1084 | |||
| 1085 | /*----------------------------------------------------------------------- | ||
| 1086 | * SCCR - System Clock Control Register 9-8 | ||
| 1087 | */ | ||
| 1088 | #define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ | ||
| 1089 | #define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ | ||
| 1090 | #define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ | ||
| 1091 | #define SCCR_PCIDF_SHIFT 3 | ||
| 1092 | |||
| 1093 | #ifndef CPM_IMMR_OFFSET | ||
| 1094 | #define CPM_IMMR_OFFSET 0x101a8 | ||
| 1095 | #endif | ||
| 1096 | |||
| 1097 | #define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ | ||
| 1098 | |||
| 1099 | /* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK | ||
| 1100 | * in order to use clock-computing stuff below for the FCC x | ||
| 1101 | */ | ||
| 1102 | |||
| 1103 | /* Automatically generates register configurations */ | ||
| 1104 | #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ | ||
| 1105 | |||
| 1106 | #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ | ||
| 1107 | #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ | ||
| 1108 | #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ | ||
| 1109 | #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ | ||
| 1110 | #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ | ||
| 1111 | #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ | ||
| 1112 | |||
| 1113 | #define PC_F1RXCLK PC_CLK(F1_RXCLK) | ||
| 1114 | #define PC_F1TXCLK PC_CLK(F1_TXCLK) | ||
| 1115 | #define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) | ||
| 1116 | #define CMX1_CLK_MASK ((uint)0xff000000) | ||
| 1117 | |||
| 1118 | #define PC_F2RXCLK PC_CLK(F2_RXCLK) | ||
| 1119 | #define PC_F2TXCLK PC_CLK(F2_TXCLK) | ||
| 1120 | #define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) | ||
| 1121 | #define CMX2_CLK_MASK ((uint)0x00ff0000) | ||
| 1122 | |||
| 1123 | #define PC_F3RXCLK PC_CLK(F3_RXCLK) | ||
| 1124 | #define PC_F3TXCLK PC_CLK(F3_TXCLK) | ||
| 1125 | #define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) | ||
| 1126 | #define CMX3_CLK_MASK ((uint)0x0000ff00) | ||
| 1127 | |||
| 1128 | #define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK) | ||
| 1129 | #define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE) | ||
| 1130 | |||
| 1131 | #define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK) | ||
| 1132 | |||
| 1133 | /* I/O Pin assignment for FCC1. I don't yet know the best way to do this, | ||
| 1134 | * but there is little variation among the choices. | ||
| 1135 | */ | ||
| 1136 | #define PA1_COL 0x00000001U | ||
| 1137 | #define PA1_CRS 0x00000002U | ||
| 1138 | #define PA1_TXER 0x00000004U | ||
| 1139 | #define PA1_TXEN 0x00000008U | ||
| 1140 | #define PA1_RXDV 0x00000010U | ||
| 1141 | #define PA1_RXER 0x00000020U | ||
| 1142 | #define PA1_TXDAT 0x00003c00U | ||
| 1143 | #define PA1_RXDAT 0x0003c000U | ||
| 1144 | #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) | ||
| 1145 | #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ | ||
| 1146 | PA1_RXDV | PA1_RXER) | ||
| 1147 | #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) | ||
| 1148 | #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) | ||
| 1149 | |||
| 1150 | |||
| 1151 | /* I/O Pin assignment for FCC2. I don't yet know the best way to do this, | ||
| 1152 | * but there is little variation among the choices. | ||
| 1153 | */ | ||
| 1154 | #define PB2_TXER 0x00000001U | ||
| 1155 | #define PB2_RXDV 0x00000002U | ||
| 1156 | #define PB2_TXEN 0x00000004U | ||
| 1157 | #define PB2_RXER 0x00000008U | ||
| 1158 | #define PB2_COL 0x00000010U | ||
| 1159 | #define PB2_CRS 0x00000020U | ||
| 1160 | #define PB2_TXDAT 0x000003c0U | ||
| 1161 | #define PB2_RXDAT 0x00003c00U | ||
| 1162 | #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ | ||
| 1163 | PB2_RXER | PB2_RXDV | PB2_TXER) | ||
| 1164 | #define PB2_PSORB1 (PB2_TXEN) | ||
| 1165 | #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) | ||
| 1166 | #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) | ||
| 1167 | |||
| 1168 | |||
| 1169 | /* I/O Pin assignment for FCC3. I don't yet know the best way to do this, | ||
| 1170 | * but there is little variation among the choices. | ||
| 1171 | */ | ||
| 1172 | #define PB3_RXDV 0x00004000U | ||
| 1173 | #define PB3_RXER 0x00008000U | ||
| 1174 | #define PB3_TXER 0x00010000U | ||
| 1175 | #define PB3_TXEN 0x00020000U | ||
| 1176 | #define PB3_COL 0x00040000U | ||
| 1177 | #define PB3_CRS 0x00080000U | ||
| 1178 | #define PB3_TXDAT 0x0f000000U | ||
| 1179 | #define PC3_TXDAT 0x00000010U | ||
| 1180 | #define PB3_RXDAT 0x00f00000U | ||
| 1181 | #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ | ||
| 1182 | PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) | ||
| 1183 | #define PB3_PSORB1 0 | ||
| 1184 | #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) | ||
| 1185 | #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) | ||
| 1186 | #define PC3_DIRC1 (PC3_TXDAT) | ||
| 1187 | |||
| 1188 | /* Handy macro to specify mem for FCCs*/ | ||
| 1189 | #define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) | ||
| 1190 | #define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) | ||
| 1191 | #define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) | ||
| 1192 | #define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2) | ||
| 1193 | |||
| 1194 | /* Clocks and GRG's */ | ||
| 1195 | |||
| 1196 | enum cpm_clk_dir { | ||
| 1197 | CPM_CLK_RX, | ||
| 1198 | CPM_CLK_TX, | ||
| 1199 | CPM_CLK_RTX | ||
| 1200 | }; | ||
| 1201 | |||
| 1202 | enum cpm_clk_target { | ||
| 1203 | CPM_CLK_SCC1, | ||
| 1204 | CPM_CLK_SCC2, | ||
| 1205 | CPM_CLK_SCC3, | ||
| 1206 | CPM_CLK_SCC4, | ||
| 1207 | CPM_CLK_FCC1, | ||
| 1208 | CPM_CLK_FCC2, | ||
| 1209 | CPM_CLK_FCC3 | ||
| 1210 | }; | ||
| 1211 | |||
| 1212 | enum cpm_clk { | ||
| 1213 | CPM_CLK_NONE = 0, | ||
| 1214 | CPM_BRG1, /* Baud Rate Generator 1 */ | ||
| 1215 | CPM_BRG2, /* Baud Rate Generator 2 */ | ||
| 1216 | CPM_BRG3, /* Baud Rate Generator 3 */ | ||
| 1217 | CPM_BRG4, /* Baud Rate Generator 4 */ | ||
| 1218 | CPM_BRG5, /* Baud Rate Generator 5 */ | ||
| 1219 | CPM_BRG6, /* Baud Rate Generator 6 */ | ||
| 1220 | CPM_BRG7, /* Baud Rate Generator 7 */ | ||
| 1221 | CPM_BRG8, /* Baud Rate Generator 8 */ | ||
| 1222 | CPM_CLK1, /* Clock 1 */ | ||
| 1223 | CPM_CLK2, /* Clock 2 */ | ||
| 1224 | CPM_CLK3, /* Clock 3 */ | ||
| 1225 | CPM_CLK4, /* Clock 4 */ | ||
| 1226 | CPM_CLK5, /* Clock 5 */ | ||
| 1227 | CPM_CLK6, /* Clock 6 */ | ||
| 1228 | CPM_CLK7, /* Clock 7 */ | ||
| 1229 | CPM_CLK8, /* Clock 8 */ | ||
| 1230 | CPM_CLK9, /* Clock 9 */ | ||
| 1231 | CPM_CLK10, /* Clock 10 */ | ||
| 1232 | CPM_CLK11, /* Clock 11 */ | ||
| 1233 | CPM_CLK12, /* Clock 12 */ | ||
| 1234 | CPM_CLK13, /* Clock 13 */ | ||
| 1235 | CPM_CLK14, /* Clock 14 */ | ||
| 1236 | CPM_CLK15, /* Clock 15 */ | ||
| 1237 | CPM_CLK16, /* Clock 16 */ | ||
| 1238 | CPM_CLK17, /* Clock 17 */ | ||
| 1239 | CPM_CLK18, /* Clock 18 */ | ||
| 1240 | CPM_CLK19, /* Clock 19 */ | ||
| 1241 | CPM_CLK20, /* Clock 20 */ | ||
| 1242 | CPM_CLK_DUMMY | ||
| 1243 | }; | ||
| 1244 | |||
| 1245 | extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode); | ||
| 1246 | |||
| 1247 | #endif /* __CPM2__ */ | ||
| 1248 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/delay.h b/include/asm-ppc/delay.h deleted file mode 100644 index badde6845af2..000000000000 --- a/include/asm-ppc/delay.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | #ifndef _PPC_DELAY_H | ||
| 3 | #define _PPC_DELAY_H | ||
| 4 | |||
| 5 | #include <asm/param.h> | ||
| 6 | |||
| 7 | /* | ||
| 8 | * Copyright 1996, Paul Mackerras. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | ||
| 11 | * modify it under the terms of the GNU General Public License | ||
| 12 | * as published by the Free Software Foundation; either version | ||
| 13 | * 2 of the License, or (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | extern unsigned long loops_per_jiffy; | ||
| 17 | |||
| 18 | extern void __delay(unsigned int loops); | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so | ||
| 22 | * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32. | ||
| 23 | * | ||
| 24 | * The mulhwu instruction gives us loops = (a * b) / 2^32. | ||
| 25 | * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226 | ||
| 26 | * because this lets us support a wide range of HZ and | ||
| 27 | * loops_per_jiffy values without either a or b overflowing 2^32. | ||
| 28 | * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and | ||
| 29 | * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280 | ||
| 30 | * (which corresponds to ~3800 bogomips at HZ = 100). | ||
| 31 | * -- paulus | ||
| 32 | */ | ||
| 33 | #define __MAX_UDELAY (226050910UL/HZ) /* maximum udelay argument */ | ||
| 34 | #define __MAX_NDELAY (4294967295UL/HZ) /* maximum ndelay argument */ | ||
| 35 | |||
| 36 | extern __inline__ void __udelay(unsigned int x) | ||
| 37 | { | ||
| 38 | unsigned int loops; | ||
| 39 | |||
| 40 | __asm__("mulhwu %0,%1,%2" : "=r" (loops) : | ||
| 41 | "r" (x), "r" (loops_per_jiffy * 226)); | ||
| 42 | __delay(loops); | ||
| 43 | } | ||
| 44 | |||
| 45 | extern __inline__ void __ndelay(unsigned int x) | ||
| 46 | { | ||
| 47 | unsigned int loops; | ||
| 48 | |||
| 49 | __asm__("mulhwu %0,%1,%2" : "=r" (loops) : | ||
| 50 | "r" (x), "r" (loops_per_jiffy * 5)); | ||
| 51 | __delay(loops); | ||
| 52 | } | ||
| 53 | |||
| 54 | extern void __bad_udelay(void); /* deliberately undefined */ | ||
| 55 | extern void __bad_ndelay(void); /* deliberately undefined */ | ||
| 56 | |||
| 57 | #define udelay(n) (__builtin_constant_p(n)? \ | ||
| 58 | ((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n) * (19 * HZ))) : \ | ||
| 59 | __udelay((n) * (19 * HZ))) | ||
| 60 | |||
| 61 | #define ndelay(n) (__builtin_constant_p(n)? \ | ||
| 62 | ((n) > __MAX_NDELAY? __bad_ndelay(): __ndelay((n) * HZ)) : \ | ||
| 63 | __ndelay((n) * HZ)) | ||
| 64 | |||
| 65 | #endif /* defined(_PPC_DELAY_H) */ | ||
| 66 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/device.h b/include/asm-ppc/device.h deleted file mode 100644 index d8f9872b0e2d..000000000000 --- a/include/asm-ppc/device.h +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Arch specific extensions to struct device | ||
| 3 | * | ||
| 4 | * This file is released under the GPLv2 | ||
| 5 | */ | ||
| 6 | #include <asm-generic/device.h> | ||
| 7 | |||
diff --git a/include/asm-ppc/floppy.h b/include/asm-ppc/floppy.h deleted file mode 100644 index 7d9b3f430d92..000000000000 --- a/include/asm-ppc/floppy.h +++ /dev/null | |||
| @@ -1,178 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Architecture specific parts of the Floppy driver | ||
| 3 | * | ||
| 4 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 5 | * License. See the file "COPYING" in the main directory of this archive | ||
| 6 | * for more details. | ||
| 7 | * | ||
| 8 | * Copyright (C) 1995 | ||
| 9 | */ | ||
| 10 | #ifdef __KERNEL__ | ||
| 11 | #ifndef __ASM_PPC_FLOPPY_H | ||
| 12 | #define __ASM_PPC_FLOPPY_H | ||
| 13 | |||
| 14 | #define fd_inb(port) inb_p(port) | ||
| 15 | #define fd_outb(value,port) outb_p(value,port) | ||
| 16 | |||
| 17 | #define fd_disable_dma() fd_ops->_disable_dma(FLOPPY_DMA) | ||
| 18 | #define fd_free_dma() fd_ops->_free_dma(FLOPPY_DMA) | ||
| 19 | #define fd_get_dma_residue() fd_ops->_get_dma_residue(FLOPPY_DMA) | ||
| 20 | #define fd_dma_setup(addr, size, mode, io) fd_ops->_dma_setup(addr, size, mode, io) | ||
| 21 | #define fd_enable_irq() enable_irq(FLOPPY_IRQ) | ||
| 22 | #define fd_disable_irq() disable_irq(FLOPPY_IRQ) | ||
| 23 | #define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); | ||
| 24 | |||
| 25 | static int fd_request_dma(void); | ||
| 26 | |||
| 27 | struct fd_dma_ops { | ||
| 28 | void (*_disable_dma)(unsigned int dmanr); | ||
| 29 | void (*_free_dma)(unsigned int dmanr); | ||
| 30 | int (*_get_dma_residue)(unsigned int dummy); | ||
| 31 | int (*_dma_setup)(char *addr, unsigned long size, int mode, int io); | ||
| 32 | }; | ||
| 33 | |||
| 34 | static int virtual_dma_count; | ||
| 35 | static int virtual_dma_residue; | ||
| 36 | static char *virtual_dma_addr; | ||
| 37 | static int virtual_dma_mode; | ||
| 38 | static int doing_vdma; | ||
| 39 | static struct fd_dma_ops *fd_ops; | ||
| 40 | |||
| 41 | static irqreturn_t floppy_hardint(int irq, void *dev_id) | ||
| 42 | { | ||
| 43 | unsigned char st; | ||
| 44 | int lcount; | ||
| 45 | char *lptr; | ||
| 46 | |||
| 47 | if (!doing_vdma) | ||
| 48 | return floppy_interrupt(irq, dev_id); | ||
| 49 | |||
| 50 | |||
| 51 | st = 1; | ||
| 52 | for (lcount=virtual_dma_count, lptr=virtual_dma_addr; | ||
| 53 | lcount; lcount--, lptr++) { | ||
| 54 | st=inb(virtual_dma_port+4) & 0xa0 ; | ||
| 55 | if (st != 0xa0) | ||
| 56 | break; | ||
| 57 | if (virtual_dma_mode) | ||
| 58 | outb_p(*lptr, virtual_dma_port+5); | ||
| 59 | else | ||
| 60 | *lptr = inb_p(virtual_dma_port+5); | ||
| 61 | } | ||
| 62 | virtual_dma_count = lcount; | ||
| 63 | virtual_dma_addr = lptr; | ||
| 64 | st = inb(virtual_dma_port+4); | ||
| 65 | |||
| 66 | if (st == 0x20) | ||
| 67 | return IRQ_HANDLED; | ||
| 68 | if (!(st & 0x20)) { | ||
| 69 | virtual_dma_residue += virtual_dma_count; | ||
| 70 | virtual_dma_count=0; | ||
| 71 | doing_vdma = 0; | ||
| 72 | floppy_interrupt(irq, dev_id); | ||
| 73 | return IRQ_HANDLED; | ||
| 74 | } | ||
| 75 | return IRQ_HANDLED; | ||
| 76 | } | ||
| 77 | |||
| 78 | static void vdma_disable_dma(unsigned int dummy) | ||
| 79 | { | ||
| 80 | doing_vdma = 0; | ||
| 81 | virtual_dma_residue += virtual_dma_count; | ||
| 82 | virtual_dma_count=0; | ||
| 83 | } | ||
| 84 | |||
| 85 | static void vdma_nop(unsigned int dummy) | ||
| 86 | { | ||
| 87 | } | ||
| 88 | |||
| 89 | |||
| 90 | static int vdma_get_dma_residue(unsigned int dummy) | ||
| 91 | { | ||
| 92 | return virtual_dma_count + virtual_dma_residue; | ||
| 93 | } | ||
| 94 | |||
| 95 | |||
| 96 | static int fd_request_irq(void) | ||
| 97 | { | ||
| 98 | if (can_use_virtual_dma) | ||
| 99 | return request_irq(FLOPPY_IRQ, floppy_hardint, | ||
| 100 | IRQF_DISABLED, "floppy", NULL); | ||
| 101 | else | ||
| 102 | return request_irq(FLOPPY_IRQ, floppy_interrupt, | ||
| 103 | IRQF_DISABLED, "floppy", NULL); | ||
| 104 | } | ||
| 105 | |||
| 106 | static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io) | ||
| 107 | { | ||
| 108 | doing_vdma = 1; | ||
| 109 | virtual_dma_port = io; | ||
| 110 | virtual_dma_mode = (mode == DMA_MODE_WRITE); | ||
| 111 | virtual_dma_addr = addr; | ||
| 112 | virtual_dma_count = size; | ||
| 113 | virtual_dma_residue = 0; | ||
| 114 | return 0; | ||
| 115 | } | ||
| 116 | |||
| 117 | static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) | ||
| 118 | { | ||
| 119 | /* actual, physical DMA */ | ||
| 120 | doing_vdma = 0; | ||
| 121 | clear_dma_ff(FLOPPY_DMA); | ||
| 122 | set_dma_mode(FLOPPY_DMA,mode); | ||
| 123 | set_dma_addr(FLOPPY_DMA,(unsigned int)virt_to_bus(addr)); | ||
| 124 | set_dma_count(FLOPPY_DMA,size); | ||
| 125 | enable_dma(FLOPPY_DMA); | ||
| 126 | return 0; | ||
| 127 | } | ||
| 128 | |||
| 129 | static struct fd_dma_ops real_dma_ops = | ||
| 130 | { | ||
| 131 | ._disable_dma = disable_dma, | ||
| 132 | ._free_dma = free_dma, | ||
| 133 | ._get_dma_residue = get_dma_residue, | ||
| 134 | ._dma_setup = hard_dma_setup | ||
| 135 | }; | ||
| 136 | |||
| 137 | static struct fd_dma_ops virt_dma_ops = | ||
| 138 | { | ||
| 139 | ._disable_dma = vdma_disable_dma, | ||
| 140 | ._free_dma = vdma_nop, | ||
| 141 | ._get_dma_residue = vdma_get_dma_residue, | ||
| 142 | ._dma_setup = vdma_dma_setup | ||
| 143 | }; | ||
| 144 | |||
| 145 | static int fd_request_dma() | ||
| 146 | { | ||
| 147 | if (can_use_virtual_dma & 1) { | ||
| 148 | fd_ops = &virt_dma_ops; | ||
| 149 | return 0; | ||
| 150 | } | ||
| 151 | else { | ||
| 152 | fd_ops = &real_dma_ops; | ||
| 153 | return request_dma(FLOPPY_DMA, "floppy"); | ||
| 154 | } | ||
| 155 | } | ||
| 156 | |||
| 157 | static int FDC1 = 0x3f0; | ||
| 158 | static int FDC2 = -1; | ||
| 159 | |||
| 160 | /* | ||
| 161 | * Again, the CMOS information not available | ||
| 162 | */ | ||
| 163 | #define FLOPPY0_TYPE 6 | ||
| 164 | #define FLOPPY1_TYPE 0 | ||
| 165 | |||
| 166 | #define N_FDC 2 /* Don't change this! */ | ||
| 167 | #define N_DRIVE 8 | ||
| 168 | |||
| 169 | /* | ||
| 170 | * The PowerPC has no problems with floppy DMA crossing 64k borders. | ||
| 171 | */ | ||
| 172 | #define CROSS_64KB(a,s) (0) | ||
| 173 | |||
| 174 | #endif /* __ASM_PPC_FLOPPY_H */ | ||
| 175 | |||
| 176 | #define EXTRA_FLOPPY_PARAMS | ||
| 177 | |||
| 178 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/fs_pd.h b/include/asm-ppc/fs_pd.h deleted file mode 100644 index 8691327653af..000000000000 --- a/include/asm-ppc/fs_pd.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Platform information definitions. | ||
| 3 | * | ||
| 4 | * 2006 (c) MontaVista Software, Inc. | ||
| 5 | * Vitaly Bordug <vbordug@ru.mvista.com> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public License | ||
| 8 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 9 | * kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef FS_PD_H | ||
| 13 | #define FS_PD_H | ||
| 14 | |||
| 15 | static inline int uart_baudrate(void) | ||
| 16 | { | ||
| 17 | int baud; | ||
| 18 | bd_t *bd = (bd_t *) __res; | ||
| 19 | |||
| 20 | if (bd->bi_baudrate) | ||
| 21 | baud = bd->bi_baudrate; | ||
| 22 | else | ||
| 23 | baud = -1; | ||
| 24 | return baud; | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline int uart_clock(void) | ||
| 28 | { | ||
| 29 | return (((bd_t *) __res)->bi_intfreq); | ||
| 30 | } | ||
| 31 | |||
| 32 | #define cpm2_map(member) (&cpm2_immr->member) | ||
| 33 | #define cpm2_map_size(member, size) (&cpm2_immr->member) | ||
| 34 | #define cpm2_unmap(addr) do {} while(0) | ||
| 35 | |||
| 36 | #endif | ||
diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h deleted file mode 100644 index 341ae55b99fb..000000000000 --- a/include/asm-ppc/gg2.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997 Geert Uytterhoeven | ||
| 5 | * | ||
| 6 | * This file is based on the following documentation: | ||
| 7 | * | ||
| 8 | * The VAS96011/12 Chipset, Data Book, Edition 1.0 | ||
| 9 | * VLSI Technology, Inc. | ||
| 10 | * | ||
| 11 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 12 | * License. See the file COPYING in the main directory of this archive | ||
| 13 | * for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef _ASMPPC_GG2_H | ||
| 17 | #define _ASMPPC_GG2_H | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Memory Map (CHRP mode) | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ | ||
| 24 | #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ | ||
| 25 | #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ | ||
| 26 | #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ | ||
| 27 | #define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ | ||
| 28 | /* special PCI cycles */ | ||
| 29 | #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ | ||
| 30 | #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ | ||
| 31 | |||
| 32 | |||
| 33 | /* | ||
| 34 | * GG2 specific PCI Registers | ||
| 35 | */ | ||
| 36 | |||
| 37 | extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ | ||
| 38 | |||
| 39 | #define GG2_PCI_BUSNO 0x40 /* Bus number */ | ||
| 40 | #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ | ||
| 41 | #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ | ||
| 42 | #define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ | ||
| 43 | #define GG2_PCI_ADDR_MAP 0x5c /* Address map */ | ||
| 44 | #define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ | ||
| 45 | #define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ | ||
| 46 | #define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ | ||
| 47 | #define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ | ||
| 48 | #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ | ||
| 49 | #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ | ||
| 50 | #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ | ||
| 51 | #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ | ||
| 52 | #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ | ||
| 53 | #define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ | ||
| 54 | #define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ | ||
| 55 | #define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ | ||
| 56 | #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ | ||
| 57 | #define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ | ||
| 58 | #define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ | ||
| 59 | /* Cleared when read */ | ||
| 60 | |||
| 61 | #endif /* _ASMPPC_GG2_H */ | ||
diff --git a/include/asm-ppc/gt64260.h b/include/asm-ppc/gt64260.h deleted file mode 100644 index 9e63b3cfffca..000000000000 --- a/include/asm-ppc/gt64260.h +++ /dev/null | |||
| @@ -1,322 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/gt64260.h | ||
| 3 | * | ||
| 4 | * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines. | ||
| 5 | * | ||
| 6 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
| 7 | * | ||
| 8 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | #ifndef __ASMPPC_GT64260_H | ||
| 14 | #define __ASMPPC_GT64260_H | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/pci.h> | ||
| 19 | #include <linux/slab.h> | ||
| 20 | |||
| 21 | #include <asm/byteorder.h> | ||
| 22 | #include <asm/io.h> | ||
| 23 | #include <asm/irq.h> | ||
| 24 | #include <asm/uaccess.h> | ||
| 25 | #include <asm/machdep.h> | ||
| 26 | #include <asm/pci-bridge.h> | ||
| 27 | #include <asm/gt64260_defs.h> | ||
| 28 | |||
| 29 | |||
| 30 | extern u32 gt64260_base; | ||
| 31 | extern u32 gt64260_irq_base; /* We handle the next 96 IRQs from here */ | ||
| 32 | extern u32 gt64260_revision; | ||
| 33 | extern u8 gt64260_pci_exclude_bridge; | ||
| 34 | |||
| 35 | #ifndef TRUE | ||
| 36 | #define TRUE 1 | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef FALSE | ||
| 40 | #define FALSE 0 | ||
| 41 | #endif | ||
| 42 | |||
| 43 | /* IRQs defined by the 64260 */ | ||
| 44 | #define GT64260_IRQ_MPSC0 40 | ||
| 45 | #define GT64260_IRQ_MPSC1 42 | ||
| 46 | #define GT64260_IRQ_SDMA 36 | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Define a default physical memory map to be set up on the bridge. | ||
| 50 | * Also define a struct to pass that info from board-specific routines to | ||
| 51 | * GT64260 generic set up routines. By passing this info in, the board | ||
| 52 | * support developer can modify it at will. | ||
| 53 | */ | ||
| 54 | |||
| 55 | /* | ||
| 56 | * This is the default memory map: | ||
| 57 | * CPU PCI | ||
| 58 | * --- --- | ||
| 59 | * PCI 0 I/O: 0xfa000000-0xfaffffff 0x00000000-0x00ffffff | ||
| 60 | * PCI 1 I/O: 0xfb000000-0xfbffffff 0x01000000-0x01ffffff | ||
| 61 | * PCI 0 MEM: 0x80000000-0x8fffffff 0x80000000-0x8fffffff | ||
| 62 | * PCI 1 MEM: 0x90000000-0x9fffffff 0x90000000-0x9fffffff | ||
| 63 | */ | ||
| 64 | |||
| 65 | /* Default physical memory map for the GT64260 bridge */ | ||
| 66 | |||
| 67 | /* | ||
| 68 | * PCI Bus 0 Definitions | ||
| 69 | */ | ||
| 70 | #define GT64260_PCI_0_IO_SIZE 0x01000000U | ||
| 71 | #define GT64260_PCI_0_MEM_SIZE 0x10000000U | ||
| 72 | |||
| 73 | /* Processor Physical addresses */ | ||
| 74 | #define GT64260_PCI_0_IO_START_PROC 0xfa000000U | ||
| 75 | #define GT64260_PCI_0_IO_END_PROC (GT64260_PCI_0_IO_START_PROC + \ | ||
| 76 | GT64260_PCI_0_IO_SIZE - 1) | ||
| 77 | |||
| 78 | /* PCI 0 addresses */ | ||
| 79 | #define GT64260_PCI_0_IO_START 0x00000000U | ||
| 80 | #define GT64260_PCI_0_IO_END (GT64260_PCI_0_IO_START + \ | ||
| 81 | GT64260_PCI_0_IO_SIZE - 1) | ||
| 82 | |||
| 83 | /* Processor Physical addresses */ | ||
| 84 | #define GT64260_PCI_0_MEM_START_PROC 0x80000000U | ||
| 85 | #define GT64260_PCI_0_MEM_END_PROC (GT64260_PCI_0_MEM_START_PROC + \ | ||
| 86 | GT64260_PCI_0_MEM_SIZE - 1) | ||
| 87 | |||
| 88 | /* PCI 0 addresses */ | ||
| 89 | #define GT64260_PCI_0_MEM_START 0x80000000U | ||
| 90 | #define GT64260_PCI_0_MEM_END (GT64260_PCI_0_MEM_START + \ | ||
| 91 | GT64260_PCI_0_MEM_SIZE - 1) | ||
| 92 | |||
| 93 | /* | ||
| 94 | * PCI Bus 1 Definitions | ||
| 95 | */ | ||
| 96 | #define GT64260_PCI_1_IO_SIZE 0x01000000U | ||
| 97 | #define GT64260_PCI_1_MEM_SIZE 0x10000000U | ||
| 98 | |||
| 99 | /* PCI 1 addresses */ | ||
| 100 | #define GT64260_PCI_1_IO_START 0x01000000U | ||
| 101 | #define GT64260_PCI_1_IO_END (GT64260_PCI_1_IO_START + \ | ||
| 102 | GT64260_PCI_1_IO_SIZE - 1) | ||
| 103 | |||
| 104 | /* Processor Physical addresses */ | ||
| 105 | #define GT64260_PCI_1_IO_START_PROC 0xfb000000U | ||
| 106 | #define GT64260_PCI_1_IO_END_PROC (GT64260_PCI_1_IO_START_PROC + \ | ||
| 107 | GT64260_PCI_1_IO_SIZE - 1) | ||
| 108 | |||
| 109 | /* PCI 1 addresses */ | ||
| 110 | #define GT64260_PCI_1_MEM_START 0x90000000U | ||
| 111 | #define GT64260_PCI_1_MEM_END (GT64260_PCI_1_MEM_START + \ | ||
| 112 | GT64260_PCI_1_MEM_SIZE - 1) | ||
| 113 | |||
| 114 | /* Processor Physical addresses */ | ||
| 115 | #define GT64260_PCI_1_MEM_START_PROC 0x90000000U | ||
| 116 | #define GT64260_PCI_1_MEM_END_PROC (GT64260_PCI_1_MEM_START_PROC + \ | ||
| 117 | GT64260_PCI_1_MEM_SIZE - 1) | ||
| 118 | |||
| 119 | /* Define struct to pass mem-map info into gt64260_common.c code */ | ||
| 120 | typedef struct { | ||
| 121 | struct pci_controller *hose_a; | ||
| 122 | struct pci_controller *hose_b; | ||
| 123 | |||
| 124 | u32 mem_size; | ||
| 125 | |||
| 126 | u32 pci_0_io_start_proc; | ||
| 127 | u32 pci_0_io_start_pci; | ||
| 128 | u32 pci_0_io_size; | ||
| 129 | u32 pci_0_io_swap; | ||
| 130 | |||
| 131 | u32 pci_0_mem_start_proc; | ||
| 132 | u32 pci_0_mem_start_pci_hi; | ||
| 133 | u32 pci_0_mem_start_pci_lo; | ||
| 134 | u32 pci_0_mem_size; | ||
| 135 | u32 pci_0_mem_swap; | ||
| 136 | |||
| 137 | u32 pci_1_io_start_proc; | ||
| 138 | u32 pci_1_io_start_pci; | ||
| 139 | u32 pci_1_io_size; | ||
| 140 | u32 pci_1_io_swap; | ||
| 141 | |||
| 142 | u32 pci_1_mem_start_proc; | ||
| 143 | u32 pci_1_mem_start_pci_hi; | ||
| 144 | u32 pci_1_mem_start_pci_lo; | ||
| 145 | u32 pci_1_mem_size; | ||
| 146 | u32 pci_1_mem_swap; | ||
| 147 | } gt64260_bridge_info_t; | ||
| 148 | |||
| 149 | #define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) { \ | ||
| 150 | (ip)->mem_size = (ms); \ | ||
| 151 | \ | ||
| 152 | (ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC; \ | ||
| 153 | (ip)->pci_0_io_start_pci = GT64260_PCI_0_IO_START; \ | ||
| 154 | (ip)->pci_0_io_size = GT64260_PCI_0_IO_SIZE; \ | ||
| 155 | (ip)->pci_0_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ | ||
| 156 | \ | ||
| 157 | (ip)->pci_0_mem_start_proc = GT64260_PCI_0_MEM_START_PROC; \ | ||
| 158 | (ip)->pci_0_mem_start_pci_hi = 0x00000000; \ | ||
| 159 | (ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START; \ | ||
| 160 | (ip)->pci_0_mem_size = GT64260_PCI_0_MEM_SIZE; \ | ||
| 161 | (ip)->pci_0_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ | ||
| 162 | \ | ||
| 163 | (ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC; \ | ||
| 164 | (ip)->pci_1_io_start_pci = GT64260_PCI_1_IO_START; \ | ||
| 165 | (ip)->pci_1_io_size = GT64260_PCI_1_IO_SIZE; \ | ||
| 166 | (ip)->pci_1_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ | ||
| 167 | \ | ||
| 168 | (ip)->pci_1_mem_start_proc = GT64260_PCI_1_MEM_START_PROC; \ | ||
| 169 | (ip)->pci_1_mem_start_pci_hi = 0x00000000; \ | ||
| 170 | (ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START; \ | ||
| 171 | (ip)->pci_1_mem_size = GT64260_PCI_1_MEM_SIZE; \ | ||
| 172 | (ip)->pci_1_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ | ||
| 173 | } | ||
| 174 | |||
| 175 | /* | ||
| 176 | ***************************************************************************** | ||
| 177 | * | ||
| 178 | * I/O macros to access the 64260's registers | ||
| 179 | * | ||
| 180 | ***************************************************************************** | ||
| 181 | */ | ||
| 182 | |||
| 183 | extern inline uint32_t gt_read(uint32_t offs){ | ||
| 184 | return (in_le32((volatile uint *)(gt64260_base + offs))); | ||
| 185 | } | ||
| 186 | extern inline void gt_write(uint32_t offs, uint32_t d){ | ||
| 187 | out_le32((volatile uint *)(gt64260_base + offs), d); | ||
| 188 | } | ||
| 189 | |||
| 190 | #if 0 /* paranoid SMP version */ | ||
| 191 | extern inline void gt_modify(u32 offs, u32 data, u32 mask) \ | ||
| 192 | { | ||
| 193 | uint32_t reg; | ||
| 194 | spin_lock(>64260_lock); | ||
| 195 | reg = gt_read(offs) & (~mask); /* zero any bits we care about*/ | ||
| 196 | reg |= data & mask; /* set bits from the data */ | ||
| 197 | gt_write(offs, reg); | ||
| 198 | spin_unlock(>64260_lock); | ||
| 199 | } | ||
| 200 | #else | ||
| 201 | extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask) | ||
| 202 | { | ||
| 203 | uint32_t reg; | ||
| 204 | reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/ | ||
| 205 | reg |= (data) & (mask); /* set bits from the data */ | ||
| 206 | gt_write(offs, reg); | ||
| 207 | } | ||
| 208 | #endif | ||
| 209 | #define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits) | ||
| 210 | |||
| 211 | #define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits) | ||
| 212 | |||
| 213 | |||
| 214 | /* | ||
| 215 | ***************************************************************************** | ||
| 216 | * | ||
| 217 | * Function Prototypes | ||
| 218 | * | ||
| 219 | ***************************************************************************** | ||
| 220 | */ | ||
| 221 | |||
| 222 | int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info, | ||
| 223 | int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char))); | ||
| 224 | int gt64260_bridge_init(gt64260_bridge_info_t *info); | ||
| 225 | int gt64260_cpu_scs_set_window(u32 window, | ||
| 226 | u32 base_addr, | ||
| 227 | u32 size); | ||
| 228 | int gt64260_cpu_cs_set_window(u32 window, | ||
| 229 | u32 base_addr, | ||
| 230 | u32 size); | ||
| 231 | int gt64260_cpu_boot_set_window(u32 base_addr, | ||
| 232 | u32 size); | ||
| 233 | int gt64260_cpu_set_pci_io_window(u32 pci_bus, | ||
| 234 | u32 cpu_base_addr, | ||
| 235 | u32 pci_base_addr, | ||
| 236 | u32 size, | ||
| 237 | u32 swap); | ||
| 238 | int gt64260_cpu_set_pci_mem_window(u32 pci_bus, | ||
| 239 | u32 window, | ||
| 240 | u32 cpu_base_addr, | ||
| 241 | u32 pci_base_addr_hi, | ||
| 242 | u32 pci_base_addr_lo, | ||
| 243 | u32 size, | ||
| 244 | u32 swap_64bit); | ||
| 245 | int gt64260_cpu_prot_set_window(u32 window, | ||
| 246 | u32 base_addr, | ||
| 247 | u32 size, | ||
| 248 | u32 access_bits); | ||
| 249 | int gt64260_cpu_snoop_set_window(u32 window, | ||
| 250 | u32 base_addr, | ||
| 251 | u32 size, | ||
| 252 | u32 snoop_type); | ||
| 253 | void gt64260_cpu_disable_all_windows(void); | ||
| 254 | int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits); | ||
| 255 | int gt64260_pci_slave_scs_set_window(struct pci_controller *hose, | ||
| 256 | u32 window, | ||
| 257 | u32 pci_base_addr, | ||
| 258 | u32 cpu_base_addr, | ||
| 259 | u32 size); | ||
| 260 | int gt64260_pci_slave_cs_set_window(struct pci_controller *hose, | ||
| 261 | u32 window, | ||
| 262 | u32 pci_base_addr, | ||
| 263 | u32 cpu_base_addr, | ||
| 264 | u32 size); | ||
| 265 | int gt64260_pci_slave_boot_set_window(struct pci_controller *hose, | ||
| 266 | u32 pci_base_addr, | ||
| 267 | u32 cpu_base_addr, | ||
| 268 | u32 size); | ||
| 269 | int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose, | ||
| 270 | u32 window, | ||
| 271 | u32 pci_base_addr, | ||
| 272 | u32 other_bus_base_addr, | ||
| 273 | u32 size); | ||
| 274 | int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose, | ||
| 275 | u32 pci_base_addr, | ||
| 276 | u32 other_bus_base_addr, | ||
| 277 | u32 size); | ||
| 278 | int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose, | ||
| 279 | u32 window, | ||
| 280 | u32 pci_base_addr_hi, | ||
| 281 | u32 pci_base_addr_lo, | ||
| 282 | u32 cpu_base_addr, | ||
| 283 | u32 size); | ||
| 284 | int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose, | ||
| 285 | u32 window, | ||
| 286 | u32 pci_base_addr_hi, | ||
| 287 | u32 pci_base_addr_lo, | ||
| 288 | u32 cpu_base_addr, | ||
| 289 | u32 size); | ||
| 290 | int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose, | ||
| 291 | u32 pci_base_addr_hi, | ||
| 292 | u32 pci_base_addr_lo, | ||
| 293 | u32 cpu_base_addr, | ||
| 294 | u32 size); | ||
| 295 | int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose, | ||
| 296 | u32 window, | ||
| 297 | u32 pci_base_addr_hi, | ||
| 298 | u32 pci_base_addr_lo, | ||
| 299 | u32 other_bus_base_addr, | ||
| 300 | u32 size); | ||
| 301 | int gt64260_pci_acc_cntl_set_window(u32 pci_bus, | ||
| 302 | u32 window, | ||
| 303 | u32 base_addr_hi, | ||
| 304 | u32 base_addr_lo, | ||
| 305 | u32 size, | ||
| 306 | u32 features); | ||
| 307 | int gt64260_pci_snoop_set_window(u32 pci_bus, | ||
| 308 | u32 window, | ||
| 309 | u32 base_addr_hi, | ||
| 310 | u32 base_addr_lo, | ||
| 311 | u32 size, | ||
| 312 | u32 snoop_type); | ||
| 313 | int gt64260_set_base(u32 new_base); | ||
| 314 | int gt64260_get_base(u32 *base); | ||
| 315 | int gt64260_pci_exclude_device(u8 bus, u8 devfn); | ||
| 316 | |||
| 317 | void gt64260_init_irq(void); | ||
| 318 | int gt64260_get_irq(void); | ||
| 319 | |||
| 320 | void gt64260_mpsc_progress(char *s, unsigned short hex); | ||
| 321 | |||
| 322 | #endif /* __ASMPPC_GT64260_H */ | ||
diff --git a/include/asm-ppc/gt64260_defs.h b/include/asm-ppc/gt64260_defs.h deleted file mode 100644 index 6ffd01a5373e..000000000000 --- a/include/asm-ppc/gt64260_defs.h +++ /dev/null | |||
| @@ -1,1010 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/gt64260_defs.h | ||
| 3 | * | ||
| 4 | * Register definitions for the Marvell/Galileo GT64260 host bridge. | ||
| 5 | * | ||
| 6 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
| 7 | * | ||
| 8 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | #ifndef __ASMPPC_GT64260_DEFS_H | ||
| 14 | #define __ASMPPC_GT64260_DEFS_H | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Define a macro to represent the supported version of the 64260. | ||
| 18 | */ | ||
| 19 | #define GT64260 0x01 | ||
| 20 | #define GT64260A 0x10 | ||
| 21 | |||
| 22 | /* | ||
| 23 | ***************************************************************************** | ||
| 24 | * | ||
| 25 | * CPU Interface Registers | ||
| 26 | * | ||
| 27 | ***************************************************************************** | ||
| 28 | */ | ||
| 29 | |||
| 30 | /* CPU physical address of 64260's registers */ | ||
| 31 | #define GT64260_INTERNAL_SPACE_DECODE 0x0068 | ||
| 32 | #define GT64260_INTERNAL_SPACE_SIZE 0x10000 | ||
| 33 | #define GT64260_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 | ||
| 34 | |||
| 35 | /* CPU Memory Controller Window Registers (4 windows) */ | ||
| 36 | #define GT64260_CPU_SCS_DECODE_WINDOWS 4 | ||
| 37 | |||
| 38 | #define GT64260_CPU_SCS_DECODE_0_BOT 0x0008 | ||
| 39 | #define GT64260_CPU_SCS_DECODE_0_TOP 0x0010 | ||
| 40 | #define GT64260_CPU_SCS_DECODE_1_BOT 0x0208 | ||
| 41 | #define GT64260_CPU_SCS_DECODE_1_TOP 0x0210 | ||
| 42 | #define GT64260_CPU_SCS_DECODE_2_BOT 0x0018 | ||
| 43 | #define GT64260_CPU_SCS_DECODE_2_TOP 0x0020 | ||
| 44 | #define GT64260_CPU_SCS_DECODE_3_BOT 0x0218 | ||
| 45 | #define GT64260_CPU_SCS_DECODE_3_TOP 0x0220 | ||
| 46 | |||
| 47 | /* CPU Device Controller Window Registers (4 windows) */ | ||
| 48 | #define GT64260_CPU_CS_DECODE_WINDOWS 4 | ||
| 49 | |||
| 50 | #define GT64260_CPU_CS_DECODE_0_BOT 0x0028 | ||
| 51 | #define GT64260_CPU_CS_DECODE_0_TOP 0x0030 | ||
| 52 | #define GT64260_CPU_CS_DECODE_1_BOT 0x0228 | ||
| 53 | #define GT64260_CPU_CS_DECODE_1_TOP 0x0230 | ||
| 54 | #define GT64260_CPU_CS_DECODE_2_BOT 0x0248 | ||
| 55 | #define GT64260_CPU_CS_DECODE_2_TOP 0x0250 | ||
| 56 | #define GT64260_CPU_CS_DECODE_3_BOT 0x0038 | ||
| 57 | #define GT64260_CPU_CS_DECODE_3_TOP 0x0040 | ||
| 58 | |||
| 59 | #define GT64260_CPU_BOOT_CS_DECODE_0_BOT 0x0238 | ||
| 60 | #define GT64260_CPU_BOOT_CS_DECODE_0_TOP 0x0240 | ||
| 61 | |||
| 62 | /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ | ||
| 63 | #define GT64260_PCI_BUSES 2 | ||
| 64 | #define GT64260_PCI_IO_WINDOWS_PER_BUS 1 | ||
| 65 | #define GT64260_PCI_MEM_WINDOWS_PER_BUS 4 | ||
| 66 | |||
| 67 | #define GT64260_CPU_PCI_SWAP_BYTE 0x00000000 | ||
| 68 | #define GT64260_CPU_PCI_SWAP_NONE 0x01000000 | ||
| 69 | #define GT64260_CPU_PCI_SWAP_BYTE_WORD 0x02000000 | ||
| 70 | #define GT64260_CPU_PCI_SWAP_WORD 0x03000000 | ||
| 71 | #define GT64260_CPU_PCI_SWAP_MASK 0x07000000 | ||
| 72 | |||
| 73 | #define GT64260_CPU_PCI_MEM_REQ64 (1<<27) | ||
| 74 | |||
| 75 | #define GT64260_CPU_PCI_0_IO_DECODE_BOT 0x0048 | ||
| 76 | #define GT64260_CPU_PCI_0_IO_DECODE_TOP 0x0050 | ||
| 77 | #define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT 0x0058 | ||
| 78 | #define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP 0x0060 | ||
| 79 | #define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT 0x0080 | ||
| 80 | #define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP 0x0088 | ||
| 81 | #define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT 0x0258 | ||
| 82 | #define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP 0x0260 | ||
| 83 | #define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT 0x0280 | ||
| 84 | #define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP 0x0288 | ||
| 85 | |||
| 86 | #define GT64260_CPU_PCI_0_IO_REMAP 0x00f0 | ||
| 87 | #define GT64260_CPU_PCI_0_MEM_0_REMAP_LO 0x00f8 | ||
| 88 | #define GT64260_CPU_PCI_0_MEM_0_REMAP_HI 0x0320 | ||
| 89 | #define GT64260_CPU_PCI_0_MEM_1_REMAP_LO 0x0100 | ||
| 90 | #define GT64260_CPU_PCI_0_MEM_1_REMAP_HI 0x0328 | ||
| 91 | #define GT64260_CPU_PCI_0_MEM_2_REMAP_LO 0x02f8 | ||
| 92 | #define GT64260_CPU_PCI_0_MEM_2_REMAP_HI 0x0330 | ||
| 93 | #define GT64260_CPU_PCI_0_MEM_3_REMAP_LO 0x0300 | ||
| 94 | #define GT64260_CPU_PCI_0_MEM_3_REMAP_HI 0x0338 | ||
| 95 | |||
| 96 | #define GT64260_CPU_PCI_1_IO_DECODE_BOT 0x0090 | ||
| 97 | #define GT64260_CPU_PCI_1_IO_DECODE_TOP 0x0098 | ||
| 98 | #define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT 0x00a0 | ||
| 99 | #define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP 0x00a8 | ||
| 100 | #define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT 0x00b0 | ||
| 101 | #define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP 0x00b8 | ||
| 102 | #define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT 0x02a0 | ||
| 103 | #define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP 0x02a8 | ||
| 104 | #define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT 0x02b0 | ||
| 105 | #define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP 0x02b8 | ||
| 106 | |||
| 107 | #define GT64260_CPU_PCI_1_IO_REMAP 0x0108 | ||
| 108 | #define GT64260_CPU_PCI_1_MEM_0_REMAP_LO 0x0110 | ||
| 109 | #define GT64260_CPU_PCI_1_MEM_0_REMAP_HI 0x0340 | ||
| 110 | #define GT64260_CPU_PCI_1_MEM_1_REMAP_LO 0x0118 | ||
| 111 | #define GT64260_CPU_PCI_1_MEM_1_REMAP_HI 0x0348 | ||
| 112 | #define GT64260_CPU_PCI_1_MEM_2_REMAP_LO 0x0310 | ||
| 113 | #define GT64260_CPU_PCI_1_MEM_2_REMAP_HI 0x0350 | ||
| 114 | #define GT64260_CPU_PCI_1_MEM_3_REMAP_LO 0x0318 | ||
| 115 | #define GT64260_CPU_PCI_1_MEM_3_REMAP_HI 0x0358 | ||
| 116 | |||
| 117 | /* CPU Control Registers */ | ||
| 118 | #define GT64260_CPU_CONFIG 0x0000 | ||
| 119 | #define GT64260_CPU_MODE 0x0120 | ||
| 120 | #define GT64260_CPU_MASTER_CNTL 0x0160 | ||
| 121 | #define GT64260_CPU_XBAR_CNTL_LO 0x0150 | ||
| 122 | #define GT64260_CPU_XBAR_CNTL_HI 0x0158 | ||
| 123 | #define GT64260_CPU_XBAR_TO 0x0168 | ||
| 124 | #define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 | ||
| 125 | #define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 | ||
| 126 | |||
| 127 | /* CPU Sync Barrier Registers */ | ||
| 128 | #define GT64260_CPU_SYNC_BARRIER_PCI_0 0x00c0 | ||
| 129 | #define GT64260_CPU_SYNC_BARRIER_PCI_1 0x00c8 | ||
| 130 | |||
| 131 | /* CPU Access Protection Registers */ | ||
| 132 | #define GT64260_CPU_PROT_WINDOWS 8 | ||
| 133 | |||
| 134 | #define GT64260_CPU_PROT_ACCPROTECT (1<<16) | ||
| 135 | #define GT64260_CPU_PROT_WRPROTECT (1<<17) | ||
| 136 | #define GT64260_CPU_PROT_CACHEPROTECT (1<<18) | ||
| 137 | |||
| 138 | #define GT64260_CPU_PROT_BASE_0 0x0180 | ||
| 139 | #define GT64260_CPU_PROT_TOP_0 0x0188 | ||
| 140 | #define GT64260_CPU_PROT_BASE_1 0x0190 | ||
| 141 | #define GT64260_CPU_PROT_TOP_1 0x0198 | ||
| 142 | #define GT64260_CPU_PROT_BASE_2 0x01a0 | ||
| 143 | #define GT64260_CPU_PROT_TOP_2 0x01a8 | ||
| 144 | #define GT64260_CPU_PROT_BASE_3 0x01b0 | ||
| 145 | #define GT64260_CPU_PROT_TOP_3 0x01b8 | ||
| 146 | #define GT64260_CPU_PROT_BASE_4 0x01c0 | ||
| 147 | #define GT64260_CPU_PROT_TOP_4 0x01c8 | ||
| 148 | #define GT64260_CPU_PROT_BASE_5 0x01d0 | ||
| 149 | #define GT64260_CPU_PROT_TOP_5 0x01d8 | ||
| 150 | #define GT64260_CPU_PROT_BASE_6 0x01e0 | ||
| 151 | #define GT64260_CPU_PROT_TOP_6 0x01e8 | ||
| 152 | #define GT64260_CPU_PROT_BASE_7 0x01f0 | ||
| 153 | #define GT64260_CPU_PROT_TOP_7 0x01f8 | ||
| 154 | |||
| 155 | /* CPU Snoop Control Registers */ | ||
| 156 | #define GT64260_CPU_SNOOP_WINDOWS 4 | ||
| 157 | |||
| 158 | #define GT64260_CPU_SNOOP_NONE 0x00000000 | ||
| 159 | #define GT64260_CPU_SNOOP_WT 0x00010000 | ||
| 160 | #define GT64260_CPU_SNOOP_WB 0x00020000 | ||
| 161 | #define GT64260_CPU_SNOOP_MASK 0x00030000 | ||
| 162 | #define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK | ||
| 163 | |||
| 164 | #define GT64260_CPU_SNOOP_BASE_0 0x0380 | ||
| 165 | #define GT64260_CPU_SNOOP_TOP_0 0x0388 | ||
| 166 | #define GT64260_CPU_SNOOP_BASE_1 0x0390 | ||
| 167 | #define GT64260_CPU_SNOOP_TOP_1 0x0398 | ||
| 168 | #define GT64260_CPU_SNOOP_BASE_2 0x03a0 | ||
| 169 | #define GT64260_CPU_SNOOP_TOP_2 0x03a8 | ||
| 170 | #define GT64260_CPU_SNOOP_BASE_3 0x03b0 | ||
| 171 | #define GT64260_CPU_SNOOP_TOP_3 0x03b8 | ||
| 172 | |||
| 173 | /* CPU Error Report Registers */ | ||
| 174 | #define GT64260_CPU_ERR_ADDR_LO 0x0070 | ||
| 175 | #define GT64260_CPU_ERR_ADDR_HI 0x0078 | ||
| 176 | #define GT64260_CPU_ERR_DATA_LO 0x0128 | ||
| 177 | #define GT64260_CPU_ERR_DATA_HI 0x0130 | ||
| 178 | #define GT64260_CPU_ERR_PARITY 0x0138 | ||
| 179 | #define GT64260_CPU_ERR_CAUSE 0x0140 | ||
| 180 | #define GT64260_CPU_ERR_MASK 0x0148 | ||
| 181 | |||
| 182 | |||
| 183 | /* | ||
| 184 | ***************************************************************************** | ||
| 185 | * | ||
| 186 | * SDRAM Cotnroller Registers | ||
| 187 | * | ||
| 188 | ***************************************************************************** | ||
| 189 | */ | ||
| 190 | |||
| 191 | /* SDRAM Config Registers */ | ||
| 192 | #define GT64260_SDRAM_CONFIG 0x0448 | ||
| 193 | #define GT64260_SDRAM_OPERATION_MODE 0x0474 | ||
| 194 | #define GT64260_SDRAM_ADDR_CNTL 0x047c | ||
| 195 | #define GT64260_SDRAM_TIMING_PARAMS 0x04b4 | ||
| 196 | #define GT64260_SDRAM_UMA_CNTL 0x04a4 | ||
| 197 | #define GT64260_SDRAM_XBAR_CNTL_LO 0x04a8 | ||
| 198 | #define GT64260_SDRAM_XBAR_CNTL_HI 0x04ac | ||
| 199 | #define GT64260_SDRAM_XBAR_CNTL_TO 0x04b0 | ||
| 200 | |||
| 201 | /* SDRAM Banks Parameters Registers */ | ||
| 202 | #define GT64260_SDRAM_BANK_PARAMS_0 0x044c | ||
| 203 | #define GT64260_SDRAM_BANK_PARAMS_1 0x0450 | ||
| 204 | #define GT64260_SDRAM_BANK_PARAMS_2 0x0454 | ||
| 205 | #define GT64260_SDRAM_BANK_PARAMS_3 0x0458 | ||
| 206 | |||
| 207 | /* SDRAM Error Report Registers */ | ||
| 208 | #define GT64260_SDRAM_ERR_DATA_LO 0x0484 | ||
| 209 | #define GT64260_SDRAM_ERR_DATA_HI 0x0480 | ||
| 210 | #define GT64260_SDRAM_ERR_ADDR 0x0490 | ||
| 211 | #define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 | ||
| 212 | #define GT64260_SDRAM_ERR_ECC_CALC 0x048c | ||
| 213 | #define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 | ||
| 214 | #define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 | ||
| 215 | |||
| 216 | |||
| 217 | /* | ||
| 218 | ***************************************************************************** | ||
| 219 | * | ||
| 220 | * Device/BOOT Cotnroller Registers | ||
| 221 | * | ||
| 222 | ***************************************************************************** | ||
| 223 | */ | ||
| 224 | |||
| 225 | /* Device Control Registers */ | ||
| 226 | #define GT64260_DEV_BANK_PARAMS_0 0x045c | ||
| 227 | #define GT64260_DEV_BANK_PARAMS_1 0x0460 | ||
| 228 | #define GT64260_DEV_BANK_PARAMS_2 0x0464 | ||
| 229 | #define GT64260_DEV_BANK_PARAMS_3 0x0468 | ||
| 230 | #define GT64260_DEV_BOOT_PARAMS 0x046c | ||
| 231 | #define GT64260_DEV_IF_CNTL 0x04c0 | ||
| 232 | #define GT64260_DEV_IF_XBAR_CNTL_LO 0x04c8 | ||
| 233 | #define GT64260_DEV_IF_XBAR_CNTL_HI 0x04cc | ||
| 234 | #define GT64260_DEV_IF_XBAR_CNTL_TO 0x04c4 | ||
| 235 | |||
| 236 | /* Device Interrupt Registers */ | ||
| 237 | #define GT64260_DEV_INTR_CAUSE 0x04d0 | ||
| 238 | #define GT64260_DEV_INTR_MASK 0x04d4 | ||
| 239 | #define GT64260_DEV_INTR_ERR_ADDR 0x04d8 | ||
| 240 | |||
| 241 | |||
| 242 | /* | ||
| 243 | ***************************************************************************** | ||
| 244 | * | ||
| 245 | * PCI Bridge Interface Registers | ||
| 246 | * | ||
| 247 | ***************************************************************************** | ||
| 248 | */ | ||
| 249 | |||
| 250 | /* PCI Configuration Access Registers */ | ||
| 251 | #define GT64260_PCI_0_CONFIG_ADDR 0x0cf8 | ||
| 252 | #define GT64260_PCI_0_CONFIG_DATA 0x0cfc | ||
| 253 | #define GT64260_PCI_0_IACK 0x0c34 | ||
| 254 | |||
| 255 | #define GT64260_PCI_1_CONFIG_ADDR 0x0c78 | ||
| 256 | #define GT64260_PCI_1_CONFIG_DATA 0x0c7c | ||
| 257 | #define GT64260_PCI_1_IACK 0x0cb4 | ||
| 258 | |||
| 259 | /* PCI Control Registers */ | ||
| 260 | #define GT64260_PCI_0_CMD 0x0c00 | ||
| 261 | #define GT64260_PCI_0_MODE 0x0d00 | ||
| 262 | #define GT64260_PCI_0_TO_RETRY 0x0c04 | ||
| 263 | #define GT64260_PCI_0_RD_BUF_DISCARD_TIMER 0x0d04 | ||
| 264 | #define GT64260_PCI_0_MSI_TRIGGER_TIMER 0x0c38 | ||
| 265 | #define GT64260_PCI_0_ARBITER_CNTL 0x1d00 | ||
| 266 | #define GT64260_PCI_0_XBAR_CNTL_LO 0x1d08 | ||
| 267 | #define GT64260_PCI_0_XBAR_CNTL_HI 0x1d0c | ||
| 268 | #define GT64260_PCI_0_XBAR_CNTL_TO 0x1d04 | ||
| 269 | #define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO 0x1d18 | ||
| 270 | #define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI 0x1d1c | ||
| 271 | #define GT64260_PCI_0_SYNC_BARRIER 0x1d10 | ||
| 272 | #define GT64260_PCI_0_P2P_CONFIG 0x1d14 | ||
| 273 | #define GT64260_PCI_0_P2P_SWAP_CNTL 0x1d54 | ||
| 274 | |||
| 275 | #define GT64260_PCI_1_CMD 0x0c80 | ||
| 276 | #define GT64260_PCI_1_MODE 0x0d80 | ||
| 277 | #define GT64260_PCI_1_TO_RETRY 0x0c84 | ||
| 278 | #define GT64260_PCI_1_RD_BUF_DISCARD_TIMER 0x0d84 | ||
| 279 | #define GT64260_PCI_1_MSI_TRIGGER_TIMER 0x0cb8 | ||
| 280 | #define GT64260_PCI_1_ARBITER_CNTL 0x1d80 | ||
| 281 | #define GT64260_PCI_1_XBAR_CNTL_LO 0x1d88 | ||
| 282 | #define GT64260_PCI_1_XBAR_CNTL_HI 0x1d8c | ||
| 283 | #define GT64260_PCI_1_XBAR_CNTL_TO 0x1d84 | ||
| 284 | #define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO 0x1d98 | ||
| 285 | #define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI 0x1d9c | ||
| 286 | #define GT64260_PCI_1_SYNC_BARRIER 0x1d90 | ||
| 287 | #define GT64260_PCI_1_P2P_CONFIG 0x1d94 | ||
| 288 | #define GT64260_PCI_1_P2P_SWAP_CNTL 0x1dd4 | ||
| 289 | |||
| 290 | /* PCI Access Control Regions Registers */ | ||
| 291 | #define GT64260_PCI_ACC_CNTL_WINDOWS 8 | ||
| 292 | |||
| 293 | #define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) | ||
| 294 | #define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) | ||
| 295 | #define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) | ||
| 296 | #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) | ||
| 297 | #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) | ||
| 298 | #define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS 0x00000000 | ||
| 299 | #define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS 0x00100000 | ||
| 300 | #define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS 0x00200000 | ||
| 301 | #define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 | ||
| 302 | #define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 | ||
| 303 | #define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 | ||
| 304 | #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 | ||
| 305 | #define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 | ||
| 306 | #define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 | ||
| 307 | #define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) | ||
| 308 | #define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) | ||
| 309 | |||
| 310 | #define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ | ||
| 311 | GT64260_PCI_ACC_CNTL_DREADEN | \ | ||
| 312 | GT64260_PCI_ACC_CNTL_RDPREFETCH | \ | ||
| 313 | GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ | ||
| 314 | GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ | ||
| 315 | GT64260_PCI_ACC_CNTL_MBURST_MASK | \ | ||
| 316 | GT64260_PCI_ACC_CNTL_SWAP_MASK | \ | ||
| 317 | GT64260_PCI_ACC_CNTL_ACCPROT| \ | ||
| 318 | GT64260_PCI_ACC_CNTL_WRPROT) | ||
| 319 | |||
| 320 | #define GT64260_PCI_0_ACC_CNTL_0_BASE_LO 0x1e00 | ||
| 321 | #define GT64260_PCI_0_ACC_CNTL_0_BASE_HI 0x1e04 | ||
| 322 | #define GT64260_PCI_0_ACC_CNTL_0_TOP 0x1e08 | ||
| 323 | #define GT64260_PCI_0_ACC_CNTL_1_BASE_LO 0x1e10 | ||
| 324 | #define GT64260_PCI_0_ACC_CNTL_1_BASE_HI 0x1e14 | ||
| 325 | #define GT64260_PCI_0_ACC_CNTL_1_TOP 0x1e18 | ||
| 326 | #define GT64260_PCI_0_ACC_CNTL_2_BASE_LO 0x1e20 | ||
| 327 | #define GT64260_PCI_0_ACC_CNTL_2_BASE_HI 0x1e24 | ||
| 328 | #define GT64260_PCI_0_ACC_CNTL_2_TOP 0x1e28 | ||
| 329 | #define GT64260_PCI_0_ACC_CNTL_3_BASE_LO 0x1e30 | ||
| 330 | #define GT64260_PCI_0_ACC_CNTL_3_BASE_HI 0x1e34 | ||
| 331 | #define GT64260_PCI_0_ACC_CNTL_3_TOP 0x1e38 | ||
| 332 | #define GT64260_PCI_0_ACC_CNTL_4_BASE_LO 0x1e40 | ||
| 333 | #define GT64260_PCI_0_ACC_CNTL_4_BASE_HI 0x1e44 | ||
| 334 | #define GT64260_PCI_0_ACC_CNTL_4_TOP 0x1e48 | ||
| 335 | #define GT64260_PCI_0_ACC_CNTL_5_BASE_LO 0x1e50 | ||
| 336 | #define GT64260_PCI_0_ACC_CNTL_5_BASE_HI 0x1e54 | ||
| 337 | #define GT64260_PCI_0_ACC_CNTL_5_TOP 0x1e58 | ||
| 338 | #define GT64260_PCI_0_ACC_CNTL_6_BASE_LO 0x1e60 | ||
| 339 | #define GT64260_PCI_0_ACC_CNTL_6_BASE_HI 0x1e64 | ||
| 340 | #define GT64260_PCI_0_ACC_CNTL_6_TOP 0x1e68 | ||
| 341 | #define GT64260_PCI_0_ACC_CNTL_7_BASE_LO 0x1e70 | ||
| 342 | #define GT64260_PCI_0_ACC_CNTL_7_BASE_HI 0x1e74 | ||
| 343 | #define GT64260_PCI_0_ACC_CNTL_7_TOP 0x1e78 | ||
| 344 | |||
| 345 | #define GT64260_PCI_1_ACC_CNTL_0_BASE_LO 0x1e80 | ||
| 346 | #define GT64260_PCI_1_ACC_CNTL_0_BASE_HI 0x1e84 | ||
| 347 | #define GT64260_PCI_1_ACC_CNTL_0_TOP 0x1e88 | ||
| 348 | #define GT64260_PCI_1_ACC_CNTL_1_BASE_LO 0x1e90 | ||
| 349 | #define GT64260_PCI_1_ACC_CNTL_1_BASE_HI 0x1e94 | ||
| 350 | #define GT64260_PCI_1_ACC_CNTL_1_TOP 0x1e98 | ||
| 351 | #define GT64260_PCI_1_ACC_CNTL_2_BASE_LO 0x1ea0 | ||
| 352 | #define GT64260_PCI_1_ACC_CNTL_2_BASE_HI 0x1ea4 | ||
| 353 | #define GT64260_PCI_1_ACC_CNTL_2_TOP 0x1ea8 | ||
| 354 | #define GT64260_PCI_1_ACC_CNTL_3_BASE_LO 0x1eb0 | ||
| 355 | #define GT64260_PCI_1_ACC_CNTL_3_BASE_HI 0x1eb4 | ||
| 356 | #define GT64260_PCI_1_ACC_CNTL_3_TOP 0x1eb8 | ||
| 357 | #define GT64260_PCI_1_ACC_CNTL_4_BASE_LO 0x1ec0 | ||
| 358 | #define GT64260_PCI_1_ACC_CNTL_4_BASE_HI 0x1ec4 | ||
| 359 | #define GT64260_PCI_1_ACC_CNTL_4_TOP 0x1ec8 | ||
| 360 | #define GT64260_PCI_1_ACC_CNTL_5_BASE_LO 0x1ed0 | ||
| 361 | #define GT64260_PCI_1_ACC_CNTL_5_BASE_HI 0x1ed4 | ||
| 362 | #define GT64260_PCI_1_ACC_CNTL_5_TOP 0x1ed8 | ||
| 363 | #define GT64260_PCI_1_ACC_CNTL_6_BASE_LO 0x1ee0 | ||
| 364 | #define GT64260_PCI_1_ACC_CNTL_6_BASE_HI 0x1ee4 | ||
| 365 | #define GT64260_PCI_1_ACC_CNTL_6_TOP 0x1ee8 | ||
| 366 | #define GT64260_PCI_1_ACC_CNTL_7_BASE_LO 0x1ef0 | ||
| 367 | #define GT64260_PCI_1_ACC_CNTL_7_BASE_HI 0x1ef4 | ||
| 368 | #define GT64260_PCI_1_ACC_CNTL_7_TOP 0x1ef8 | ||
| 369 | |||
| 370 | /* PCI Snoop Control Registers */ | ||
| 371 | #define GT64260_PCI_SNOOP_WINDOWS 4 | ||
| 372 | |||
| 373 | #define GT64260_PCI_SNOOP_NONE 0x00000000 | ||
| 374 | #define GT64260_PCI_SNOOP_WT 0x00001000 | ||
| 375 | #define GT64260_PCI_SNOOP_WB 0x00002000 | ||
| 376 | |||
| 377 | #define GT64260_PCI_0_SNOOP_0_BASE_LO 0x1f00 | ||
| 378 | #define GT64260_PCI_0_SNOOP_0_BASE_HI 0x1f04 | ||
| 379 | #define GT64260_PCI_0_SNOOP_0_TOP 0x1f08 | ||
| 380 | #define GT64260_PCI_0_SNOOP_1_BASE_LO 0x1f10 | ||
| 381 | #define GT64260_PCI_0_SNOOP_1_BASE_HI 0x1f14 | ||
| 382 | #define GT64260_PCI_0_SNOOP_1_TOP 0x1f18 | ||
| 383 | #define GT64260_PCI_0_SNOOP_2_BASE_LO 0x1f20 | ||
| 384 | #define GT64260_PCI_0_SNOOP_2_BASE_HI 0x1f24 | ||
| 385 | #define GT64260_PCI_0_SNOOP_2_TOP 0x1f28 | ||
| 386 | #define GT64260_PCI_0_SNOOP_3_BASE_LO 0x1f30 | ||
| 387 | #define GT64260_PCI_0_SNOOP_3_BASE_HI 0x1f34 | ||
| 388 | #define GT64260_PCI_0_SNOOP_3_TOP 0x1f38 | ||
| 389 | |||
| 390 | #define GT64260_PCI_1_SNOOP_0_BASE_LO 0x1f80 | ||
| 391 | #define GT64260_PCI_1_SNOOP_0_BASE_HI 0x1f84 | ||
| 392 | #define GT64260_PCI_1_SNOOP_0_TOP 0x1f88 | ||
| 393 | #define GT64260_PCI_1_SNOOP_1_BASE_LO 0x1f90 | ||
| 394 | #define GT64260_PCI_1_SNOOP_1_BASE_HI 0x1f94 | ||
| 395 | #define GT64260_PCI_1_SNOOP_1_TOP 0x1f98 | ||
| 396 | #define GT64260_PCI_1_SNOOP_2_BASE_LO 0x1fa0 | ||
| 397 | #define GT64260_PCI_1_SNOOP_2_BASE_HI 0x1fa4 | ||
| 398 | #define GT64260_PCI_1_SNOOP_2_TOP 0x1fa8 | ||
| 399 | #define GT64260_PCI_1_SNOOP_3_BASE_LO 0x1fb0 | ||
| 400 | #define GT64260_PCI_1_SNOOP_3_BASE_HI 0x1fb4 | ||
| 401 | #define GT64260_PCI_1_SNOOP_3_TOP 0x1fb8 | ||
| 402 | |||
| 403 | /* PCI Error Report Registers */ | ||
| 404 | #define GT64260_PCI_0_ERR_SERR_MASK 0x0c28 | ||
| 405 | #define GT64260_PCI_0_ERR_ADDR_LO 0x1d40 | ||
| 406 | #define GT64260_PCI_0_ERR_ADDR_HI 0x1d44 | ||
| 407 | #define GT64260_PCI_0_ERR_DATA_LO 0x1d48 | ||
| 408 | #define GT64260_PCI_0_ERR_DATA_HI 0x1d4c | ||
| 409 | #define GT64260_PCI_0_ERR_CMD 0x1d50 | ||
| 410 | #define GT64260_PCI_0_ERR_CAUSE 0x1d58 | ||
| 411 | #define GT64260_PCI_0_ERR_MASK 0x1d5c | ||
| 412 | |||
| 413 | #define GT64260_PCI_1_ERR_SERR_MASK 0x0ca8 | ||
| 414 | #define GT64260_PCI_1_ERR_ADDR_LO 0x1dc0 | ||
| 415 | #define GT64260_PCI_1_ERR_ADDR_HI 0x1dc4 | ||
| 416 | #define GT64260_PCI_1_ERR_DATA_LO 0x1dc8 | ||
| 417 | #define GT64260_PCI_1_ERR_DATA_HI 0x1dcc | ||
| 418 | #define GT64260_PCI_1_ERR_CMD 0x1dd0 | ||
| 419 | #define GT64260_PCI_1_ERR_CAUSE 0x1dd8 | ||
| 420 | #define GT64260_PCI_1_ERR_MASK 0x1ddc | ||
| 421 | |||
| 422 | /* PCI Slave Address Decoding Registers */ | ||
| 423 | #define GT64260_PCI_SCS_WINDOWS 4 | ||
| 424 | #define GT64260_PCI_CS_WINDOWS 4 | ||
| 425 | #define GT64260_PCI_BOOT_WINDOWS 1 | ||
| 426 | #define GT64260_PCI_P2P_MEM_WINDOWS 2 | ||
| 427 | #define GT64260_PCI_P2P_IO_WINDOWS 1 | ||
| 428 | #define GT64260_PCI_DAC_SCS_WINDOWS 4 | ||
| 429 | #define GT64260_PCI_DAC_CS_WINDOWS 4 | ||
| 430 | #define GT64260_PCI_DAC_BOOT_WINDOWS 1 | ||
| 431 | #define GT64260_PCI_DAC_P2P_MEM_WINDOWS 2 | ||
| 432 | |||
| 433 | #define GT64260_PCI_0_SLAVE_SCS_0_SIZE 0x0c08 | ||
| 434 | #define GT64260_PCI_0_SLAVE_SCS_1_SIZE 0x0d08 | ||
| 435 | #define GT64260_PCI_0_SLAVE_SCS_2_SIZE 0x0c0c | ||
| 436 | #define GT64260_PCI_0_SLAVE_SCS_3_SIZE 0x0d0c | ||
| 437 | #define GT64260_PCI_0_SLAVE_CS_0_SIZE 0x0c10 | ||
| 438 | #define GT64260_PCI_0_SLAVE_CS_1_SIZE 0x0d10 | ||
| 439 | #define GT64260_PCI_0_SLAVE_CS_2_SIZE 0x0d18 | ||
| 440 | #define GT64260_PCI_0_SLAVE_CS_3_SIZE 0x0c14 | ||
| 441 | #define GT64260_PCI_0_SLAVE_BOOT_SIZE 0x0d14 | ||
| 442 | #define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE 0x0d1c | ||
| 443 | #define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE 0x0d20 | ||
| 444 | #define GT64260_PCI_0_SLAVE_P2P_IO_SIZE 0x0d24 | ||
| 445 | #define GT64260_PCI_0_SLAVE_CPU_SIZE 0x0d28 | ||
| 446 | |||
| 447 | #define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE 0x0e00 | ||
| 448 | #define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE 0x0e04 | ||
| 449 | #define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE 0x0e08 | ||
| 450 | #define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE 0x0e0c | ||
| 451 | #define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE 0x0e10 | ||
| 452 | #define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE 0x0e14 | ||
| 453 | #define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE 0x0e18 | ||
| 454 | #define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE 0x0e1c | ||
| 455 | #define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE 0x0e20 | ||
| 456 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE 0x0e24 | ||
| 457 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE 0x0e28 | ||
| 458 | #define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE 0x0e2c | ||
| 459 | |||
| 460 | #define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE 0x0d2c | ||
| 461 | |||
| 462 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0 (1<<0) | ||
| 463 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1 (1<<1) | ||
| 464 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2 (1<<2) | ||
| 465 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3 (1<<3) | ||
| 466 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0 (1<<4) | ||
| 467 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1 (1<<5) | ||
| 468 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2 (1<<6) | ||
| 469 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3 (1<<7) | ||
| 470 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT (1<<8) | ||
| 471 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM (1<<9) | ||
| 472 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO (1<<10) | ||
| 473 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0 (1<<11) | ||
| 474 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1 (1<<12) | ||
| 475 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO (1<<13) | ||
| 476 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU (1<<14) | ||
| 477 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0 (1<<15) | ||
| 478 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1 (1<<16) | ||
| 479 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2 (1<<17) | ||
| 480 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3 (1<<18) | ||
| 481 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0 (1<<19) | ||
| 482 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1 (1<<20) | ||
| 483 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2 (1<<21) | ||
| 484 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3 (1<<22) | ||
| 485 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT (1<<23) | ||
| 486 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24) | ||
| 487 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25) | ||
| 488 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU (1<<26) | ||
| 489 | |||
| 490 | #define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES 0x0c3c | ||
| 491 | #define GT64260_PCI_0_SLAVE_SCS_0_REMAP 0x0c48 | ||
| 492 | #define GT64260_PCI_0_SLAVE_SCS_1_REMAP 0x0d48 | ||
| 493 | #define GT64260_PCI_0_SLAVE_SCS_2_REMAP 0x0c4c | ||
| 494 | #define GT64260_PCI_0_SLAVE_SCS_3_REMAP 0x0d4c | ||
| 495 | #define GT64260_PCI_0_SLAVE_CS_0_REMAP 0x0c50 | ||
| 496 | #define GT64260_PCI_0_SLAVE_CS_1_REMAP 0x0d50 | ||
| 497 | #define GT64260_PCI_0_SLAVE_CS_2_REMAP 0x0d58 | ||
| 498 | #define GT64260_PCI_0_SLAVE_CS_3_REMAP 0x0c54 | ||
| 499 | #define GT64260_PCI_0_SLAVE_BOOT_REMAP 0x0d54 | ||
| 500 | #define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c | ||
| 501 | #define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 | ||
| 502 | #define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 | ||
| 503 | #define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 | ||
| 504 | #define GT64260_PCI_0_SLAVE_P2P_IO_REMAP 0x0d6c | ||
| 505 | #define GT64260_PCI_0_SLAVE_CPU_REMAP 0x0d70 | ||
| 506 | |||
| 507 | #define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP 0x0f00 | ||
| 508 | #define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP 0x0f04 | ||
| 509 | #define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP 0x0f08 | ||
| 510 | #define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP 0x0f0c | ||
| 511 | #define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP 0x0f10 | ||
| 512 | #define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP 0x0f14 | ||
| 513 | #define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP 0x0f18 | ||
| 514 | #define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP 0x0f1c | ||
| 515 | #define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP 0x0f20 | ||
| 516 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0f24 | ||
| 517 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0f28 | ||
| 518 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0f2c | ||
| 519 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0f30 | ||
| 520 | #define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP 0x0f34 | ||
| 521 | |||
| 522 | #define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP 0x0f38 | ||
| 523 | #define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL 0x0d3c | ||
| 524 | |||
| 525 | #define GT64260_PCI_1_SLAVE_SCS_0_SIZE 0x0c88 | ||
| 526 | #define GT64260_PCI_1_SLAVE_SCS_1_SIZE 0x0d88 | ||
| 527 | #define GT64260_PCI_1_SLAVE_SCS_2_SIZE 0x0c8c | ||
| 528 | #define GT64260_PCI_1_SLAVE_SCS_3_SIZE 0x0d8c | ||
| 529 | #define GT64260_PCI_1_SLAVE_CS_0_SIZE 0x0c90 | ||
| 530 | #define GT64260_PCI_1_SLAVE_CS_1_SIZE 0x0d90 | ||
| 531 | #define GT64260_PCI_1_SLAVE_CS_2_SIZE 0x0d98 | ||
| 532 | #define GT64260_PCI_1_SLAVE_CS_3_SIZE 0x0c94 | ||
| 533 | #define GT64260_PCI_1_SLAVE_BOOT_SIZE 0x0d94 | ||
| 534 | #define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE 0x0d9c | ||
| 535 | #define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE 0x0da0 | ||
| 536 | #define GT64260_PCI_1_SLAVE_P2P_IO_SIZE 0x0da4 | ||
| 537 | #define GT64260_PCI_1_SLAVE_CPU_SIZE 0x0da8 | ||
| 538 | |||
| 539 | #define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE 0x0e80 | ||
| 540 | #define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE 0x0e84 | ||
| 541 | #define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE 0x0e88 | ||
| 542 | #define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE 0x0e8c | ||
| 543 | #define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE 0x0e90 | ||
| 544 | #define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE 0x0e94 | ||
| 545 | #define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE 0x0e98 | ||
| 546 | #define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE 0x0e9c | ||
| 547 | #define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE 0x0ea0 | ||
| 548 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE 0x0ea4 | ||
| 549 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE 0x0ea8 | ||
| 550 | #define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE 0x0eac | ||
| 551 | |||
| 552 | #define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE 0x0dac | ||
| 553 | |||
| 554 | #define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES 0x0cbc | ||
| 555 | #define GT64260_PCI_1_SLAVE_SCS_0_REMAP 0x0cc8 | ||
| 556 | #define GT64260_PCI_1_SLAVE_SCS_1_REMAP 0x0dc8 | ||
| 557 | #define GT64260_PCI_1_SLAVE_SCS_2_REMAP 0x0ccc | ||
| 558 | #define GT64260_PCI_1_SLAVE_SCS_3_REMAP 0x0dcc | ||
| 559 | #define GT64260_PCI_1_SLAVE_CS_0_REMAP 0x0cd0 | ||
| 560 | #define GT64260_PCI_1_SLAVE_CS_1_REMAP 0x0dd0 | ||
| 561 | #define GT64260_PCI_1_SLAVE_CS_2_REMAP 0x0dd8 | ||
| 562 | #define GT64260_PCI_1_SLAVE_CS_3_REMAP 0x0cd4 | ||
| 563 | #define GT64260_PCI_1_SLAVE_BOOT_REMAP 0x0dd4 | ||
| 564 | #define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc | ||
| 565 | #define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 | ||
| 566 | #define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 | ||
| 567 | #define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 | ||
| 568 | #define GT64260_PCI_1_SLAVE_P2P_IO_REMAP 0x0dec | ||
| 569 | #define GT64260_PCI_1_SLAVE_CPU_REMAP 0x0df0 | ||
| 570 | |||
| 571 | #define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP 0x0f80 | ||
| 572 | #define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP 0x0f84 | ||
| 573 | #define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP 0x0f88 | ||
| 574 | #define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP 0x0f8c | ||
| 575 | #define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP 0x0f90 | ||
| 576 | #define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP 0x0f94 | ||
| 577 | #define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP 0x0f98 | ||
| 578 | #define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP 0x0f9c | ||
| 579 | #define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP 0x0fa0 | ||
| 580 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0fa4 | ||
| 581 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0fa8 | ||
| 582 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0fac | ||
| 583 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0fb0 | ||
| 584 | #define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP 0x0fb4 | ||
| 585 | |||
| 586 | #define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP 0x0fb8 | ||
| 587 | #define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL 0x0dbc | ||
| 588 | |||
| 589 | |||
| 590 | /* | ||
| 591 | ***************************************************************************** | ||
| 592 | * | ||
| 593 | * I2O Controller Interface Registers | ||
| 594 | * | ||
| 595 | ***************************************************************************** | ||
| 596 | */ | ||
| 597 | |||
| 598 | /* FIXME: fill in */ | ||
| 599 | |||
| 600 | |||
| 601 | |||
| 602 | /* | ||
| 603 | ***************************************************************************** | ||
| 604 | * | ||
| 605 | * DMA Controller Interface Registers | ||
| 606 | * | ||
| 607 | ***************************************************************************** | ||
| 608 | */ | ||
| 609 | |||
| 610 | /* FIXME: fill in */ | ||
| 611 | |||
| 612 | |||
| 613 | /* | ||
| 614 | ***************************************************************************** | ||
| 615 | * | ||
| 616 | * Timer/Counter Interface Registers | ||
| 617 | * | ||
| 618 | ***************************************************************************** | ||
| 619 | */ | ||
| 620 | |||
| 621 | /* FIXME: fill in */ | ||
| 622 | |||
| 623 | |||
| 624 | /* | ||
| 625 | ***************************************************************************** | ||
| 626 | * | ||
| 627 | * Communications Controller (Enet, Serial, etc.) Interface Registers | ||
| 628 | * | ||
| 629 | ***************************************************************************** | ||
| 630 | */ | ||
| 631 | |||
| 632 | #define GT64260_ENET_0_CNTL_LO 0xf200 | ||
| 633 | #define GT64260_ENET_0_CNTL_HI 0xf204 | ||
| 634 | #define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI 0xf208 | ||
| 635 | #define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI 0xf20c | ||
| 636 | #define GT64260_ENET_0_RX_DESC_ADDR_HI 0xf210 | ||
| 637 | #define GT64260_ENET_0_TX_DESC_ADDR_HI 0xf214 | ||
| 638 | #define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI 0xf218 | ||
| 639 | #define GT64260_ENET_1_CNTL_LO 0xf220 | ||
| 640 | #define GT64260_ENET_1_CNTL_HI 0xf224 | ||
| 641 | #define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI 0xf228 | ||
| 642 | #define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI 0xf22c | ||
| 643 | #define GT64260_ENET_1_RX_DESC_ADDR_HI 0xf230 | ||
| 644 | #define GT64260_ENET_1_TX_DESC_ADDR_HI 0xf234 | ||
| 645 | #define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI 0xf238 | ||
| 646 | #define GT64260_ENET_2_CNTL_LO 0xf240 | ||
| 647 | #define GT64260_ENET_2_CNTL_HI 0xf244 | ||
| 648 | #define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI 0xf248 | ||
| 649 | #define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI 0xf24c | ||
| 650 | #define GT64260_ENET_2_RX_DESC_ADDR_HI 0xf250 | ||
| 651 | #define GT64260_ENET_2_TX_DESC_ADDR_HI 0xf254 | ||
| 652 | #define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI 0xf258 | ||
| 653 | |||
| 654 | #define GT64260_MPSC_0_CNTL_LO 0xf280 | ||
| 655 | #define GT64260_MPSC_0_CNTL_HI 0xf284 | ||
| 656 | #define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI 0xf288 | ||
| 657 | #define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI 0xf28c | ||
| 658 | #define GT64260_MPSC_0_RX_DESC_ADDR_HI 0xf290 | ||
| 659 | #define GT64260_MPSC_0_TX_DESC_ADDR_HI 0xf294 | ||
| 660 | #define GT64260_MPSC_1_CNTL_LO 0xf2c0 | ||
| 661 | #define GT64260_MPSC_1_CNTL_HI 0xf2c4 | ||
| 662 | #define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI 0xf2c8 | ||
| 663 | #define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI 0xf2cc | ||
| 664 | #define GT64260_MPSC_1_RX_DESC_ADDR_HI 0xf2d0 | ||
| 665 | #define GT64260_MPSC_1_TX_DESC_ADDR_HI 0xf2d4 | ||
| 666 | |||
| 667 | #define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 | ||
| 668 | #define GT64260_SER_INIT_LAST_DATA 0xf324 | ||
| 669 | #define GT64260_SER_INIT_CONTROL 0xf328 | ||
| 670 | #define GT64260_SER_INIT_STATUS 0xf32c | ||
| 671 | |||
| 672 | #define GT64260_COMM_ARBITER_CNTL 0xf300 | ||
| 673 | #define GT64260_COMM_CONFIG 0xb40c | ||
| 674 | #define GT64260_COMM_XBAR_TO 0xf304 | ||
| 675 | #define GT64260_COMM_INTR_CAUSE 0xf310 | ||
| 676 | #define GT64260_COMM_INTR_MASK 0xf314 | ||
| 677 | #define GT64260_COMM_ERR_ADDR 0xf318 | ||
| 678 | |||
| 679 | |||
| 680 | /* | ||
| 681 | ***************************************************************************** | ||
| 682 | * | ||
| 683 | * Fast Ethernet Controller Interface Registers | ||
| 684 | * | ||
| 685 | ***************************************************************************** | ||
| 686 | */ | ||
| 687 | |||
| 688 | #define GT64260_ENET_PHY_ADDR 0x2000 | ||
| 689 | #define GT64260_ENET_ESMIR 0x2010 | ||
| 690 | |||
| 691 | #define GT64260_ENET_E0PCR 0x2400 | ||
| 692 | #define GT64260_ENET_E0PCXR 0x2408 | ||
| 693 | #define GT64260_ENET_E0PCMR 0x2410 | ||
| 694 | #define GT64260_ENET_E0PSR 0x2418 | ||
| 695 | #define GT64260_ENET_E0SPR 0x2420 | ||
| 696 | #define GT64260_ENET_E0HTPR 0x2428 | ||
| 697 | #define GT64260_ENET_E0FCSAL 0x2430 | ||
| 698 | #define GT64260_ENET_E0FCSAH 0x2438 | ||
| 699 | #define GT64260_ENET_E0SDCR 0x2440 | ||
| 700 | #define GT64260_ENET_E0SDCMR 0x2448 | ||
| 701 | #define GT64260_ENET_E0ICR 0x2450 | ||
| 702 | #define GT64260_ENET_E0IMR 0x2458 | ||
| 703 | #define GT64260_ENET_E0FRDP0 0x2480 | ||
| 704 | #define GT64260_ENET_E0FRDP1 0x2484 | ||
| 705 | #define GT64260_ENET_E0FRDP2 0x2488 | ||
| 706 | #define GT64260_ENET_E0FRDP3 0x248c | ||
| 707 | #define GT64260_ENET_E0CRDP0 0x24a0 | ||
| 708 | #define GT64260_ENET_E0CRDP1 0x24a4 | ||
| 709 | #define GT64260_ENET_E0CRDP2 0x24a8 | ||
| 710 | #define GT64260_ENET_E0CRDP3 0x24ac | ||
| 711 | #define GT64260_ENET_E0CTDP0 0x24e0 | ||
| 712 | #define GT64260_ENET_E0CTDP1 0x24e4 | ||
| 713 | #define GT64260_ENET_0_DSCP2P0L 0x2460 | ||
| 714 | #define GT64260_ENET_0_DSCP2P0H 0x2464 | ||
| 715 | #define GT64260_ENET_0_DSCP2P1L 0x2468 | ||
| 716 | #define GT64260_ENET_0_DSCP2P1H 0x246c | ||
| 717 | #define GT64260_ENET_0_VPT2P 0x2470 | ||
| 718 | #define GT64260_ENET_0_MIB_CTRS 0x2500 | ||
| 719 | |||
| 720 | #define GT64260_ENET_E1PCR 0x2800 | ||
| 721 | #define GT64260_ENET_E1PCXR 0x2808 | ||
| 722 | #define GT64260_ENET_E1PCMR 0x2810 | ||
| 723 | #define GT64260_ENET_E1PSR 0x2818 | ||
| 724 | #define GT64260_ENET_E1SPR 0x2820 | ||
| 725 | #define GT64260_ENET_E1HTPR 0x2828 | ||
| 726 | #define GT64260_ENET_E1FCSAL 0x2830 | ||
| 727 | #define GT64260_ENET_E1FCSAH 0x2838 | ||
| 728 | #define GT64260_ENET_E1SDCR 0x2840 | ||
| 729 | #define GT64260_ENET_E1SDCMR 0x2848 | ||
| 730 | #define GT64260_ENET_E1ICR 0x2850 | ||
| 731 | #define GT64260_ENET_E1IMR 0x2858 | ||
| 732 | #define GT64260_ENET_E1FRDP0 0x2880 | ||
| 733 | #define GT64260_ENET_E1FRDP1 0x2884 | ||
| 734 | #define GT64260_ENET_E1FRDP2 0x2888 | ||
| 735 | #define GT64260_ENET_E1FRDP3 0x288c | ||
| 736 | #define GT64260_ENET_E1CRDP0 0x28a0 | ||
| 737 | #define GT64260_ENET_E1CRDP1 0x28a4 | ||
| 738 | #define GT64260_ENET_E1CRDP2 0x28a8 | ||
| 739 | #define GT64260_ENET_E1CRDP3 0x28ac | ||
| 740 | #define GT64260_ENET_E1CTDP0 0x28e0 | ||
| 741 | #define GT64260_ENET_E1CTDP1 0x28e4 | ||
| 742 | #define GT64260_ENET_1_DSCP2P0L 0x2860 | ||
| 743 | #define GT64260_ENET_1_DSCP2P0H 0x2864 | ||
| 744 | #define GT64260_ENET_1_DSCP2P1L 0x2868 | ||
| 745 | #define GT64260_ENET_1_DSCP2P1H 0x286c | ||
| 746 | #define GT64260_ENET_1_VPT2P 0x2870 | ||
| 747 | #define GT64260_ENET_1_MIB_CTRS 0x2900 | ||
| 748 | |||
| 749 | #define GT64260_ENET_E2PCR 0x2c00 | ||
| 750 | #define GT64260_ENET_E2PCXR 0x2c08 | ||
| 751 | #define GT64260_ENET_E2PCMR 0x2c10 | ||
| 752 | #define GT64260_ENET_E2PSR 0x2c18 | ||
| 753 | #define GT64260_ENET_E2SPR 0x2c20 | ||
| 754 | #define GT64260_ENET_E2HTPR 0x2c28 | ||
| 755 | #define GT64260_ENET_E2FCSAL 0x2c30 | ||
| 756 | #define GT64260_ENET_E2FCSAH 0x2c38 | ||
| 757 | #define GT64260_ENET_E2SDCR 0x2c40 | ||
| 758 | #define GT64260_ENET_E2SDCMR 0x2c48 | ||
| 759 | #define GT64260_ENET_E2ICR 0x2c50 | ||
| 760 | #define GT64260_ENET_E2IMR 0x2c58 | ||
| 761 | #define GT64260_ENET_E2FRDP0 0x2c80 | ||
| 762 | #define GT64260_ENET_E2FRDP1 0x2c84 | ||
| 763 | #define GT64260_ENET_E2FRDP2 0x2c88 | ||
| 764 | #define GT64260_ENET_E2FRDP3 0x2c8c | ||
| 765 | #define GT64260_ENET_E2CRDP0 0x2ca0 | ||
| 766 | #define GT64260_ENET_E2CRDP1 0x2ca4 | ||
| 767 | #define GT64260_ENET_E2CRDP2 0x2ca8 | ||
| 768 | #define GT64260_ENET_E2CRDP3 0x2cac | ||
| 769 | #define GT64260_ENET_E2CTDP0 0x2ce0 | ||
| 770 | #define GT64260_ENET_E2CTDP1 0x2ce4 | ||
| 771 | #define GT64260_ENET_2_DSCP2P0L 0x2c60 | ||
| 772 | #define GT64260_ENET_2_DSCP2P0H 0x2c64 | ||
| 773 | #define GT64260_ENET_2_DSCP2P1L 0x2c68 | ||
| 774 | #define GT64260_ENET_2_DSCP2P1H 0x2c6c | ||
| 775 | #define GT64260_ENET_2_VPT2P 0x2c70 | ||
| 776 | #define GT64260_ENET_2_MIB_CTRS 0x2d00 | ||
| 777 | |||
| 778 | |||
| 779 | /* | ||
| 780 | ***************************************************************************** | ||
| 781 | * | ||
| 782 | * Multi-Protocol Serial Controller Interface Registers | ||
| 783 | * | ||
| 784 | ***************************************************************************** | ||
| 785 | */ | ||
| 786 | |||
| 787 | /* Signal Routing */ | ||
| 788 | #define GT64260_MPSC_MRR 0xb400 | ||
| 789 | #define GT64260_MPSC_RCRR 0xb404 | ||
| 790 | #define GT64260_MPSC_TCRR 0xb408 | ||
| 791 | |||
| 792 | /* Main Configuratino Registers */ | ||
| 793 | #define GT64260_MPSC_0_MMCRL 0x8000 | ||
| 794 | #define GT64260_MPSC_0_MMCRH 0x8004 | ||
| 795 | #define GT64260_MPSC_0_MPCR 0x8008 | ||
| 796 | #define GT64260_MPSC_0_CHR_1 0x800c | ||
| 797 | #define GT64260_MPSC_0_CHR_2 0x8010 | ||
| 798 | #define GT64260_MPSC_0_CHR_3 0x8014 | ||
| 799 | #define GT64260_MPSC_0_CHR_4 0x8018 | ||
| 800 | #define GT64260_MPSC_0_CHR_5 0x801c | ||
| 801 | #define GT64260_MPSC_0_CHR_6 0x8020 | ||
| 802 | #define GT64260_MPSC_0_CHR_7 0x8024 | ||
| 803 | #define GT64260_MPSC_0_CHR_8 0x8028 | ||
| 804 | #define GT64260_MPSC_0_CHR_9 0x802c | ||
| 805 | #define GT64260_MPSC_0_CHR_10 0x8030 | ||
| 806 | #define GT64260_MPSC_0_CHR_11 0x8034 | ||
| 807 | |||
| 808 | #define GT64260_MPSC_1_MMCRL 0x9000 | ||
| 809 | #define GT64260_MPSC_1_MMCRH 0x9004 | ||
| 810 | #define GT64260_MPSC_1_MPCR 0x9008 | ||
| 811 | #define GT64260_MPSC_1_CHR_1 0x900c | ||
| 812 | #define GT64260_MPSC_1_CHR_2 0x9010 | ||
| 813 | #define GT64260_MPSC_1_CHR_3 0x9014 | ||
| 814 | #define GT64260_MPSC_1_CHR_4 0x9018 | ||
| 815 | #define GT64260_MPSC_1_CHR_5 0x901c | ||
| 816 | #define GT64260_MPSC_1_CHR_6 0x9020 | ||
| 817 | #define GT64260_MPSC_1_CHR_7 0x9024 | ||
| 818 | #define GT64260_MPSC_1_CHR_8 0x9028 | ||
| 819 | #define GT64260_MPSC_1_CHR_9 0x902c | ||
| 820 | #define GT64260_MPSC_1_CHR_10 0x9030 | ||
| 821 | #define GT64260_MPSC_1_CHR_11 0x9034 | ||
| 822 | |||
| 823 | #define GT64260_MPSC_0_INTR_CAUSE 0xb804 | ||
| 824 | #define GT64260_MPSC_0_INTR_MASK 0xb884 | ||
| 825 | #define GT64260_MPSC_1_INTR_CAUSE 0xb80c | ||
| 826 | #define GT64260_MPSC_1_INTR_MASK 0xb88c | ||
| 827 | |||
| 828 | #define GT64260_MPSC_UART_CR_TEV (1<<1) | ||
| 829 | #define GT64260_MPSC_UART_CR_TA (1<<7) | ||
| 830 | #define GT64260_MPSC_UART_CR_TTCS (1<<9) | ||
| 831 | #define GT64260_MPSC_UART_CR_REV (1<<17) | ||
| 832 | #define GT64260_MPSC_UART_CR_RA (1<<23) | ||
| 833 | #define GT64260_MPSC_UART_CR_CRD (1<<25) | ||
| 834 | #define GT64260_MPSC_UART_CR_EH (1<<31) | ||
| 835 | |||
| 836 | #define GT64260_MPSC_UART_ESR_CTS (1<<0) | ||
| 837 | #define GT64260_MPSC_UART_ESR_CD (1<<1) | ||
| 838 | #define GT64260_MPSC_UART_ESR_TIDLE (1<<3) | ||
| 839 | #define GT64260_MPSC_UART_ESR_RHS (1<<5) | ||
| 840 | #define GT64260_MPSC_UART_ESR_RLS (1<<7) | ||
| 841 | #define GT64260_MPSC_UART_ESR_RLIDL (1<<11) | ||
| 842 | |||
| 843 | |||
| 844 | /* | ||
| 845 | ***************************************************************************** | ||
| 846 | * | ||
| 847 | * Serial DMA Controller Interface Registers | ||
| 848 | * | ||
| 849 | ***************************************************************************** | ||
| 850 | */ | ||
| 851 | |||
| 852 | #define GT64260_SDMA_0_SDC 0x4000 | ||
| 853 | #define GT64260_SDMA_0_SDCM 0x4008 | ||
| 854 | #define GT64260_SDMA_0_RX_DESC 0x4800 | ||
| 855 | #define GT64260_SDMA_0_RX_BUF_PTR 0x4808 | ||
| 856 | #define GT64260_SDMA_0_SCRDP 0x4810 | ||
| 857 | #define GT64260_SDMA_0_TX_DESC 0x4c00 | ||
| 858 | #define GT64260_SDMA_0_SCTDP 0x4c10 | ||
| 859 | #define GT64260_SDMA_0_SFTDP 0x4c14 | ||
| 860 | |||
| 861 | #define GT64260_SDMA_1_SDC 0x6000 | ||
| 862 | #define GT64260_SDMA_1_SDCM 0x6008 | ||
| 863 | #define GT64260_SDMA_1_RX_DESC 0x6800 | ||
| 864 | #define GT64260_SDMA_1_RX_BUF_PTR 0x6808 | ||
| 865 | #define GT64260_SDMA_1_SCRDP 0x6810 | ||
| 866 | #define GT64260_SDMA_1_TX_DESC 0x6c00 | ||
| 867 | #define GT64260_SDMA_1_SCTDP 0x6c10 | ||
| 868 | #define GT64260_SDMA_1_SFTDP 0x6c14 | ||
| 869 | |||
| 870 | #define GT64260_SDMA_INTR_CAUSE 0xb800 | ||
| 871 | #define GT64260_SDMA_INTR_MASK 0xb880 | ||
| 872 | |||
| 873 | #define GT64260_SDMA_DESC_CMDSTAT_PE (1<<0) | ||
| 874 | #define GT64260_SDMA_DESC_CMDSTAT_CDL (1<<1) | ||
| 875 | #define GT64260_SDMA_DESC_CMDSTAT_FR (1<<3) | ||
| 876 | #define GT64260_SDMA_DESC_CMDSTAT_OR (1<<6) | ||
| 877 | #define GT64260_SDMA_DESC_CMDSTAT_BR (1<<9) | ||
| 878 | #define GT64260_SDMA_DESC_CMDSTAT_MI (1<<10) | ||
| 879 | #define GT64260_SDMA_DESC_CMDSTAT_A (1<<11) | ||
| 880 | #define GT64260_SDMA_DESC_CMDSTAT_AM (1<<12) | ||
| 881 | #define GT64260_SDMA_DESC_CMDSTAT_CT (1<<13) | ||
| 882 | #define GT64260_SDMA_DESC_CMDSTAT_C (1<<14) | ||
| 883 | #define GT64260_SDMA_DESC_CMDSTAT_ES (1<<15) | ||
| 884 | #define GT64260_SDMA_DESC_CMDSTAT_L (1<<16) | ||
| 885 | #define GT64260_SDMA_DESC_CMDSTAT_F (1<<17) | ||
| 886 | #define GT64260_SDMA_DESC_CMDSTAT_P (1<<18) | ||
| 887 | #define GT64260_SDMA_DESC_CMDSTAT_EI (1<<23) | ||
| 888 | #define GT64260_SDMA_DESC_CMDSTAT_O (1<<31) | ||
| 889 | |||
| 890 | #define GT64260_SDMA_SDC_RFT (1<<0) | ||
| 891 | #define GT64260_SDMA_SDC_SFM (1<<1) | ||
| 892 | #define GT64260_SDMA_SDC_BLMR (1<<6) | ||
| 893 | #define GT64260_SDMA_SDC_BLMT (1<<7) | ||
| 894 | #define GT64260_SDMA_SDC_POVR (1<<8) | ||
| 895 | #define GT64260_SDMA_SDC_RIFB (1<<9) | ||
| 896 | |||
| 897 | #define GT64260_SDMA_SDCM_ERD (1<<7) | ||
| 898 | #define GT64260_SDMA_SDCM_AR (1<<15) | ||
| 899 | #define GT64260_SDMA_SDCM_STD (1<<16) | ||
| 900 | #define GT64260_SDMA_SDCM_TXD (1<<23) | ||
| 901 | #define GT64260_SDMA_SDCM_AT (1<<31) | ||
| 902 | |||
| 903 | #define GT64260_SDMA_0_CAUSE_RXBUF (1<<0) | ||
| 904 | #define GT64260_SDMA_0_CAUSE_RXERR (1<<1) | ||
| 905 | #define GT64260_SDMA_0_CAUSE_TXBUF (1<<2) | ||
| 906 | #define GT64260_SDMA_0_CAUSE_TXEND (1<<3) | ||
| 907 | #define GT64260_SDMA_1_CAUSE_RXBUF (1<<8) | ||
| 908 | #define GT64260_SDMA_1_CAUSE_RXERR (1<<9) | ||
| 909 | #define GT64260_SDMA_1_CAUSE_TXBUF (1<<10) | ||
| 910 | #define GT64260_SDMA_1_CAUSE_TXEND (1<<11) | ||
| 911 | |||
| 912 | |||
| 913 | /* | ||
| 914 | ***************************************************************************** | ||
| 915 | * | ||
| 916 | * Baud Rate Generator Interface Registers | ||
| 917 | * | ||
| 918 | ***************************************************************************** | ||
| 919 | */ | ||
| 920 | |||
| 921 | #define GT64260_BRG_0_BCR 0xb200 | ||
| 922 | #define GT64260_BRG_0_BTR 0xb204 | ||
| 923 | #define GT64260_BRG_1_BCR 0xb208 | ||
| 924 | #define GT64260_BRG_1_BTR 0xb20c | ||
| 925 | #define GT64260_BRG_2_BCR 0xb210 | ||
| 926 | #define GT64260_BRG_2_BTR 0xb214 | ||
| 927 | |||
| 928 | #define GT64260_BRG_INTR_CAUSE 0xb834 | ||
| 929 | #define GT64260_BRG_INTR_MASK 0xb8b4 | ||
| 930 | |||
| 931 | |||
| 932 | /* | ||
| 933 | ***************************************************************************** | ||
| 934 | * | ||
| 935 | * Watchdog Timer Interface Registers | ||
| 936 | * | ||
| 937 | ***************************************************************************** | ||
| 938 | */ | ||
| 939 | |||
| 940 | #define GT64260_WDT_WDC 0xb410 | ||
| 941 | #define GT64260_WDT_WDV 0xb414 | ||
| 942 | |||
| 943 | |||
| 944 | /* | ||
| 945 | ***************************************************************************** | ||
| 946 | * | ||
| 947 | * General Purpose Pins Controller Interface Registers | ||
| 948 | * | ||
| 949 | ***************************************************************************** | ||
| 950 | */ | ||
| 951 | |||
| 952 | #define GT64260_GPP_IO_CNTL 0xf100 | ||
| 953 | #define GT64260_GPP_LEVEL_CNTL 0xf110 | ||
| 954 | #define GT64260_GPP_VALUE 0xf104 | ||
| 955 | #define GT64260_GPP_INTR_CAUSE 0xf108 | ||
| 956 | #define GT64260_GPP_INTR_MASK 0xf10c | ||
| 957 | |||
| 958 | |||
| 959 | /* | ||
| 960 | ***************************************************************************** | ||
| 961 | * | ||
| 962 | * Multi-Purpose Pins Controller Interface Registers | ||
| 963 | * | ||
| 964 | ***************************************************************************** | ||
| 965 | */ | ||
| 966 | |||
| 967 | #define GT64260_MPP_CNTL_0 0xf000 | ||
| 968 | #define GT64260_MPP_CNTL_1 0xf004 | ||
| 969 | #define GT64260_MPP_CNTL_2 0xf008 | ||
| 970 | #define GT64260_MPP_CNTL_3 0xf00c | ||
| 971 | #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 | ||
| 972 | |||
| 973 | |||
| 974 | /* | ||
| 975 | ***************************************************************************** | ||
| 976 | * | ||
| 977 | * I2C Controller Interface Registers | ||
| 978 | * | ||
| 979 | ***************************************************************************** | ||
| 980 | */ | ||
| 981 | |||
| 982 | /* FIXME: fill in */ | ||
| 983 | |||
| 984 | |||
| 985 | /* | ||
| 986 | ***************************************************************************** | ||
| 987 | * | ||
| 988 | * Interrupt Controller Interface Registers | ||
| 989 | * | ||
| 990 | ***************************************************************************** | ||
| 991 | */ | ||
| 992 | |||
| 993 | #define GT64260_IC_MAIN_CAUSE_LO 0x0c18 | ||
| 994 | #define GT64260_IC_MAIN_CAUSE_HI 0x0c68 | ||
| 995 | #define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c | ||
| 996 | #define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c | ||
| 997 | #define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 | ||
| 998 | #define GT64260_IC_PCI_0_INTR_MASK_LO 0x0c24 | ||
| 999 | #define GT64260_IC_PCI_0_INTR_MASK_HI 0x0c64 | ||
| 1000 | #define GT64260_IC_PCI_0_SELECT_CAUSE 0x0c74 | ||
| 1001 | #define GT64260_IC_PCI_1_INTR_MASK_LO 0x0ca4 | ||
| 1002 | #define GT64260_IC_PCI_1_INTR_MASK_HI 0x0ce4 | ||
| 1003 | #define GT64260_IC_PCI_1_SELECT_CAUSE 0x0cf4 | ||
| 1004 | #define GT64260_IC_CPU_INT_0_MASK 0x0e60 | ||
| 1005 | #define GT64260_IC_CPU_INT_1_MASK 0x0e64 | ||
| 1006 | #define GT64260_IC_CPU_INT_2_MASK 0x0e68 | ||
| 1007 | #define GT64260_IC_CPU_INT_3_MASK 0x0e6c | ||
| 1008 | |||
| 1009 | |||
| 1010 | #endif /* __ASMPPC_GT64260_DEFS_H */ | ||
diff --git a/include/asm-ppc/harrier.h b/include/asm-ppc/harrier.h deleted file mode 100644 index 7acd7fc126ec..000000000000 --- a/include/asm-ppc/harrier.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Definitions for Motorola MCG Harrier North Bridge & Memory controller | ||
| 3 | * | ||
| 4 | * Author: Dale Farnsworth | ||
| 5 | * dale.farnsworth@mvista.com | ||
| 6 | * | ||
| 7 | * Modified by: Randy Vinson | ||
| 8 | * rvinson@mvista.com | ||
| 9 | * | ||
| 10 | * Copyright 2001-2002 MontaVista Software Inc. | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify it | ||
| 13 | * under the terms of the GNU General Public License as published by the | ||
| 14 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 15 | * option) any later version. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ASMPPC_HARRIER_H | ||
| 19 | #define __ASMPPC_HARRIER_H | ||
| 20 | |||
| 21 | #include <linux/types.h> | ||
| 22 | #include <asm/pci-bridge.h> | ||
| 23 | |||
| 24 | struct pci_controller; | ||
| 25 | int harrier_init(struct pci_controller *hose, | ||
| 26 | uint ppc_reg_base, | ||
| 27 | ulong processor_pci_mem_start, | ||
| 28 | ulong processor_pci_mem_end, | ||
| 29 | ulong processor_pci_io_start, | ||
| 30 | ulong processor_pci_io_end, | ||
| 31 | ulong processor_mpic_base); | ||
| 32 | |||
| 33 | unsigned long harrier_get_mem_size(uint smc_base); | ||
| 34 | |||
| 35 | int harrier_mpic_init(unsigned int pci_mem_offset); | ||
| 36 | |||
| 37 | void harrier_setup_nonmonarch(uint ppc_reg_base, | ||
| 38 | uint in0_size); | ||
| 39 | void harrier_release_eready(uint ppc_reg_base); | ||
| 40 | |||
| 41 | void harrier_wait_eready(uint ppc_reg_base); | ||
| 42 | |||
| 43 | #endif /* __ASMPPC_HARRIER_H */ | ||
diff --git a/include/asm-ppc/hawk.h b/include/asm-ppc/hawk.h deleted file mode 100644 index f347007d22af..000000000000 --- a/include/asm-ppc/hawk.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/hawk.h | ||
| 3 | * | ||
| 4 | * Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. | ||
| 5 | * | ||
| 6 | * Author: Mark A. Greer | ||
| 7 | * mgreer@mvista.com | ||
| 8 | * | ||
| 9 | * Modified by Randy Vinson (rvinson@mvista.com) | ||
| 10 | * | ||
| 11 | * 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 12 | * the terms of the GNU General Public License version 2. This program | ||
| 13 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 14 | * or implied. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ASMPPC_HAWK_H | ||
| 18 | #define __ASMPPC_HAWK_H | ||
| 19 | |||
| 20 | #include <asm/pci-bridge.h> | ||
| 21 | #include <asm/hawk_defs.h> | ||
| 22 | |||
| 23 | extern int hawk_init(struct pci_controller *hose, | ||
| 24 | unsigned int ppc_reg_base, unsigned long processor_pci_mem_start, | ||
| 25 | unsigned long processor_pci_mem_end, | ||
| 26 | unsigned long processor_pci_io_start, | ||
| 27 | unsigned long processor_pci_io_end, | ||
| 28 | unsigned long processor_mpic_base); | ||
| 29 | extern unsigned long hawk_get_mem_size(unsigned int smc_base); | ||
| 30 | extern int hawk_mpic_init(unsigned int pci_mem_offset); | ||
| 31 | |||
| 32 | #endif /* __ASMPPC_HAWK_H */ | ||
diff --git a/include/asm-ppc/hawk_defs.h b/include/asm-ppc/hawk_defs.h deleted file mode 100644 index 6d1d2baf648c..000000000000 --- a/include/asm-ppc/hawk_defs.h +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/hawk_defs.h | ||
| 3 | * | ||
| 4 | * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. | ||
| 5 | * | ||
| 6 | * Author: Mark A. Greer | ||
| 7 | * mgreer@mvista.com | ||
| 8 | * | ||
| 9 | * Modified by Randy Vinson (rvinson@mvista.com) | ||
| 10 | * | ||
| 11 | * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 12 | * the terms of the GNU General Public License version 2. This program | ||
| 13 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 14 | * or implied. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ASMPPC_HAWK_DEFS_H | ||
| 18 | #define __ASMPPC_HAWK_DEFS_H | ||
| 19 | |||
| 20 | #include <asm/pci-bridge.h> | ||
| 21 | |||
| 22 | /* | ||
| 23 | * The Falcon/Raven and HAWK have 4 sets of registers: | ||
| 24 | * 1) PPC Registers which define the mappings from PPC bus to PCI bus, | ||
| 25 | * etc. | ||
| 26 | * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the | ||
| 27 | * MPIC base address. | ||
| 28 | * 3) MPIC registers | ||
| 29 | * 4) System Memory Controller (SMC) registers. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8 | ||
| 33 | #define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc | ||
| 34 | |||
| 35 | #define HAWK_MPIC_SIZE 0x00040000U | ||
| 36 | #define HAWK_SMC_SIZE 0x00001000U | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Define PPC register offsets. | ||
| 40 | */ | ||
| 41 | #define HAWK_PPC_XSADD0_OFF 0x40 | ||
| 42 | #define HAWK_PPC_XSOFF0_OFF 0x44 | ||
| 43 | #define HAWK_PPC_XSADD1_OFF 0x48 | ||
| 44 | #define HAWK_PPC_XSOFF1_OFF 0x4c | ||
| 45 | #define HAWK_PPC_XSADD2_OFF 0x50 | ||
| 46 | #define HAWK_PPC_XSOFF2_OFF 0x54 | ||
| 47 | #define HAWK_PPC_XSADD3_OFF 0x58 | ||
| 48 | #define HAWK_PPC_XSOFF3_OFF 0x5c | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Define PCI register offsets. | ||
| 52 | */ | ||
| 53 | #define HAWK_PCI_PSADD0_OFF 0x80 | ||
| 54 | #define HAWK_PCI_PSOFF0_OFF 0x84 | ||
| 55 | #define HAWK_PCI_PSADD1_OFF 0x88 | ||
| 56 | #define HAWK_PCI_PSOFF1_OFF 0x8c | ||
| 57 | #define HAWK_PCI_PSADD2_OFF 0x90 | ||
| 58 | #define HAWK_PCI_PSOFF2_OFF 0x94 | ||
| 59 | #define HAWK_PCI_PSADD3_OFF 0x98 | ||
| 60 | #define HAWK_PCI_PSOFF3_OFF 0x9c | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Define the System Memory Controller (SMC) register offsets. | ||
| 64 | */ | ||
| 65 | #define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10 | ||
| 66 | #define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11 | ||
| 67 | #define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12 | ||
| 68 | #define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13 | ||
| 69 | #define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */ | ||
| 70 | #define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */ | ||
| 71 | #define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */ | ||
| 72 | #define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */ | ||
| 73 | |||
| 74 | #define FALCON_SMC_REG_COUNT 4 | ||
| 75 | #define HAWK_SMC_REG_COUNT 8 | ||
| 76 | #endif /* __ASMPPC_HAWK_DEFS_H */ | ||
diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h deleted file mode 100644 index f7b21ee302b4..000000000000 --- a/include/asm-ppc/highmem.h +++ /dev/null | |||
| @@ -1,135 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * highmem.h: virtual kernel memory mappings for high memory | ||
| 3 | * | ||
| 4 | * PowerPC version, stolen from the i386 version. | ||
| 5 | * | ||
| 6 | * Used in CONFIG_HIGHMEM systems for memory pages which | ||
| 7 | * are not addressable by direct kernel virtual addresses. | ||
| 8 | * | ||
| 9 | * Copyright (C) 1999 Gerhard Wichert, Siemens AG | ||
| 10 | * Gerhard.Wichert@pdb.siemens.de | ||
| 11 | * | ||
| 12 | * | ||
| 13 | * Redesigned the x86 32-bit VM architecture to deal with | ||
| 14 | * up to 16 Terrabyte physical memory. With current x86 CPUs | ||
| 15 | * we now support up to 64 Gigabytes physical RAM. | ||
| 16 | * | ||
| 17 | * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _ASM_HIGHMEM_H | ||
| 21 | #define _ASM_HIGHMEM_H | ||
| 22 | |||
| 23 | #ifdef __KERNEL__ | ||
| 24 | |||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/interrupt.h> | ||
| 27 | #include <asm/kmap_types.h> | ||
| 28 | #include <asm/tlbflush.h> | ||
| 29 | #include <asm/page.h> | ||
| 30 | |||
| 31 | /* undef for production */ | ||
| 32 | #define HIGHMEM_DEBUG 1 | ||
| 33 | |||
| 34 | extern pte_t *kmap_pte; | ||
| 35 | extern pgprot_t kmap_prot; | ||
| 36 | extern pte_t *pkmap_page_table; | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Right now we initialize only a single pte table. It can be extended | ||
| 40 | * easily, subsequent pte tables have to be allocated in one physical | ||
| 41 | * chunk of RAM. | ||
| 42 | */ | ||
| 43 | #define PKMAP_BASE CONFIG_HIGHMEM_START | ||
| 44 | #define LAST_PKMAP (1 << PTE_SHIFT) | ||
| 45 | #define LAST_PKMAP_MASK (LAST_PKMAP-1) | ||
| 46 | #define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) | ||
| 47 | #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) | ||
| 48 | |||
| 49 | #define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL) | ||
| 50 | |||
| 51 | extern void *kmap_high(struct page *page); | ||
| 52 | extern void kunmap_high(struct page *page); | ||
| 53 | |||
| 54 | static inline void *kmap(struct page *page) | ||
| 55 | { | ||
| 56 | might_sleep(); | ||
| 57 | if (!PageHighMem(page)) | ||
| 58 | return page_address(page); | ||
| 59 | return kmap_high(page); | ||
| 60 | } | ||
| 61 | |||
| 62 | static inline void kunmap(struct page *page) | ||
| 63 | { | ||
| 64 | BUG_ON(in_interrupt()); | ||
| 65 | if (!PageHighMem(page)) | ||
| 66 | return; | ||
| 67 | kunmap_high(page); | ||
| 68 | } | ||
| 69 | |||
| 70 | /* | ||
| 71 | * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap | ||
| 72 | * gives a more generic (and caching) interface. But kmap_atomic can | ||
| 73 | * be used in IRQ contexts, so in some (very limited) cases we need | ||
| 74 | * it. | ||
| 75 | */ | ||
| 76 | static inline void *kmap_atomic(struct page *page, enum km_type type) | ||
| 77 | { | ||
| 78 | unsigned int idx; | ||
| 79 | unsigned long vaddr; | ||
| 80 | |||
| 81 | /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ | ||
| 82 | pagefault_disable(); | ||
| 83 | if (!PageHighMem(page)) | ||
| 84 | return page_address(page); | ||
| 85 | |||
| 86 | idx = type + KM_TYPE_NR*smp_processor_id(); | ||
| 87 | vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE; | ||
| 88 | #ifdef HIGHMEM_DEBUG | ||
| 89 | BUG_ON(!pte_none(*(kmap_pte+idx))); | ||
| 90 | #endif | ||
| 91 | set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot)); | ||
| 92 | flush_tlb_page(NULL, vaddr); | ||
| 93 | |||
| 94 | return (void*) vaddr; | ||
| 95 | } | ||
| 96 | |||
| 97 | static inline void kunmap_atomic(void *kvaddr, enum km_type type) | ||
| 98 | { | ||
| 99 | #ifdef HIGHMEM_DEBUG | ||
| 100 | unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; | ||
| 101 | unsigned int idx = type + KM_TYPE_NR*smp_processor_id(); | ||
| 102 | |||
| 103 | if (vaddr < KMAP_FIX_BEGIN) { // FIXME | ||
| 104 | pagefault_enable(); | ||
| 105 | return; | ||
| 106 | } | ||
| 107 | |||
| 108 | BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE); | ||
| 109 | |||
| 110 | /* | ||
| 111 | * force other mappings to Oops if they'll try to access | ||
| 112 | * this pte without first remap it | ||
| 113 | */ | ||
| 114 | pte_clear(&init_mm, vaddr, kmap_pte+idx); | ||
| 115 | flush_tlb_page(NULL, vaddr); | ||
| 116 | #endif | ||
| 117 | pagefault_enable(); | ||
| 118 | } | ||
| 119 | |||
| 120 | static inline struct page *kmap_atomic_to_page(void *ptr) | ||
| 121 | { | ||
| 122 | unsigned long idx, vaddr = (unsigned long) ptr; | ||
| 123 | |||
| 124 | if (vaddr < KMAP_FIX_BEGIN) | ||
| 125 | return virt_to_page(ptr); | ||
| 126 | |||
| 127 | idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT; | ||
| 128 | return pte_page(kmap_pte[idx]); | ||
| 129 | } | ||
| 130 | |||
| 131 | #define flush_cache_kmaps() flush_cache_all() | ||
| 132 | |||
| 133 | #endif /* __KERNEL__ */ | ||
| 134 | |||
| 135 | #endif /* _ASM_HIGHMEM_H */ | ||
diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h deleted file mode 100644 index 1ad4eed07fbe..000000000000 --- a/include/asm-ppc/hydra.h +++ /dev/null | |||
| @@ -1,102 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997 Geert Uytterhoeven | ||
| 5 | * | ||
| 6 | * This file is based on the following documentation: | ||
| 7 | * | ||
| 8 | * Macintosh Technology in the Common Hardware Reference Platform | ||
| 9 | * Apple Computer, Inc. | ||
| 10 | * | ||
| 11 | * © Copyright 1995 Apple Computer, Inc. All rights reserved. | ||
| 12 | * | ||
| 13 | * It's available online from http://chrp.apple.com/MacTech.pdf. | ||
| 14 | * You can obtain paper copies of this book from computer bookstores or by | ||
| 15 | * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San | ||
| 16 | * Francisco, CA 94104. Reference ISBN 1-55860-393-X. | ||
| 17 | * | ||
| 18 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 19 | * License. See the file COPYING in the main directory of this archive | ||
| 20 | * for more details. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _ASMPPC_HYDRA_H | ||
| 24 | #define _ASMPPC_HYDRA_H | ||
| 25 | |||
| 26 | #ifdef __KERNEL__ | ||
| 27 | |||
| 28 | struct Hydra { | ||
| 29 | /* DBDMA Controller Register Space */ | ||
| 30 | char Pad1[0x30]; | ||
| 31 | u_int CachePD; | ||
| 32 | u_int IDs; | ||
| 33 | u_int Feature_Control; | ||
| 34 | char Pad2[0x7fc4]; | ||
| 35 | /* DBDMA Channel Register Space */ | ||
| 36 | char SCSI_DMA[0x100]; | ||
| 37 | char Pad3[0x300]; | ||
| 38 | char SCCA_Tx_DMA[0x100]; | ||
| 39 | char SCCA_Rx_DMA[0x100]; | ||
| 40 | char SCCB_Tx_DMA[0x100]; | ||
| 41 | char SCCB_Rx_DMA[0x100]; | ||
| 42 | char Pad4[0x7800]; | ||
| 43 | /* Device Register Space */ | ||
| 44 | char SCSI[0x1000]; | ||
| 45 | char ADB[0x1000]; | ||
| 46 | char SCC_Legacy[0x1000]; | ||
| 47 | char SCC[0x1000]; | ||
| 48 | char Pad9[0x2000]; | ||
| 49 | char VIA[0x2000]; | ||
| 50 | char Pad10[0x28000]; | ||
| 51 | char OpenPIC[0x40000]; | ||
| 52 | }; | ||
| 53 | |||
| 54 | extern volatile struct Hydra __iomem *Hydra; | ||
| 55 | |||
| 56 | |||
| 57 | /* | ||
| 58 | * Feature Control Register | ||
| 59 | */ | ||
| 60 | |||
| 61 | #define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */ | ||
| 62 | #define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */ | ||
| 63 | #define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */ | ||
| 64 | #define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */ | ||
| 65 | #define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */ | ||
| 66 | #define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */ | ||
| 67 | #define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */ | ||
| 68 | #define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */ | ||
| 69 | #define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */ | ||
| 70 | |||
| 71 | |||
| 72 | /* | ||
| 73 | * OpenPIC Interrupt Sources | ||
| 74 | */ | ||
| 75 | |||
| 76 | #define HYDRA_INT_SIO 0 | ||
| 77 | #define HYDRA_INT_SCSI_DMA 1 | ||
| 78 | #define HYDRA_INT_SCCA_TX_DMA 2 | ||
| 79 | #define HYDRA_INT_SCCA_RX_DMA 3 | ||
| 80 | #define HYDRA_INT_SCCB_TX_DMA 4 | ||
| 81 | #define HYDRA_INT_SCCB_RX_DMA 5 | ||
| 82 | #define HYDRA_INT_SCSI 6 | ||
| 83 | #define HYDRA_INT_SCCA 7 | ||
| 84 | #define HYDRA_INT_SCCB 8 | ||
| 85 | #define HYDRA_INT_VIA 9 | ||
| 86 | #define HYDRA_INT_ADB 10 | ||
| 87 | #define HYDRA_INT_ADB_NMI 11 | ||
| 88 | #define HYDRA_INT_EXT1 12 /* PCI IRQW */ | ||
| 89 | #define HYDRA_INT_EXT2 13 /* PCI IRQX */ | ||
| 90 | #define HYDRA_INT_EXT3 14 /* PCI IRQY */ | ||
| 91 | #define HYDRA_INT_EXT4 15 /* PCI IRQZ */ | ||
| 92 | #define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */ | ||
| 93 | #define HYDRA_INT_EXT6 17 /* IDE Secondary */ | ||
| 94 | #define HYDRA_INT_EXT7 18 /* Power Off Request */ | ||
| 95 | #define HYDRA_INT_SPARE 19 | ||
| 96 | |||
| 97 | extern int hydra_init(void); | ||
| 98 | extern void macio_adb_init(void); | ||
| 99 | |||
| 100 | #endif /* __KERNEL__ */ | ||
| 101 | |||
| 102 | #endif /* _ASMPPC_HYDRA_H */ | ||
diff --git a/include/asm-ppc/ibm403.h b/include/asm-ppc/ibm403.h deleted file mode 100644 index c9c5d539cfdb..000000000000 --- a/include/asm-ppc/ibm403.h +++ /dev/null | |||
| @@ -1,478 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com> | ||
| 3 | * | ||
| 4 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 5 | * the terms of the GNU General Public License version 2. This program | ||
| 6 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 7 | * or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | |||
| 11 | #ifdef __KERNEL__ | ||
| 12 | #ifndef __ASM_IBM403_H__ | ||
| 13 | #define __ASM_IBM403_H__ | ||
| 14 | |||
| 15 | |||
| 16 | #if defined(CONFIG_403GCX) | ||
| 17 | |||
| 18 | #define DCRN_BE_BASE 0x090 | ||
| 19 | #define DCRN_DMA0_BASE 0x0C0 | ||
| 20 | #define DCRN_DMA1_BASE 0x0C8 | ||
| 21 | #define DCRN_DMA2_BASE 0x0D0 | ||
| 22 | #define DCRN_DMA3_BASE 0x0D8 | ||
| 23 | #define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ | ||
| 24 | #define DCRN_DMASR_BASE 0x0E0 | ||
| 25 | |||
| 26 | #define DCRN_EXIER_BASE 0x042 | ||
| 27 | #define DCRN_EXISR_BASE 0x040 | ||
| 28 | #define DCRN_IOCR_BASE 0x0A0 | ||
| 29 | |||
| 30 | |||
| 31 | /* ------------------------------------------------------------------------- */ | ||
| 32 | #endif | ||
| 33 | |||
| 34 | |||
| 35 | |||
| 36 | #ifdef DCRN_BE_BASE | ||
| 37 | #define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ | ||
| 38 | #define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register*/ | ||
| 39 | #endif | ||
| 40 | /* DCRN_BESR */ | ||
| 41 | #define BESR_DSES 0x80000000 /* Data-Side Error Status */ | ||
| 42 | #define BESR_DMES 0x40000000 /* DMA Error Status */ | ||
| 43 | #define BESR_RWS 0x20000000 /* Read/Write Status */ | ||
| 44 | #define BESR_ETMASK 0x1C000000 /* Error Type */ | ||
| 45 | #define ET_PROT 0 | ||
| 46 | #define ET_PARITY 1 | ||
| 47 | #define ET_NCFG 2 | ||
| 48 | #define ET_BUSERR 4 | ||
| 49 | #define ET_BUSTO 6 | ||
| 50 | |||
| 51 | #ifdef DCRN_CHCR_BASE | ||
| 52 | #define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ | ||
| 53 | #define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ | ||
| 54 | #endif | ||
| 55 | #define CHR1_CETE 0x00800000 /* CPU external timer enable */ | ||
| 56 | #define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ | ||
| 57 | |||
| 58 | #ifdef DCRN_CHPSR_BASE | ||
| 59 | #define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifdef DCRN_CIC_BASE | ||
| 63 | #define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ | ||
| 64 | #define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ | ||
| 65 | #define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ | ||
| 66 | #define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ | ||
| 67 | #define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ | ||
| 68 | #define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ | ||
| 69 | #define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ | ||
| 70 | #define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ | ||
| 71 | #define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifdef DCRN_CPMFR_BASE | ||
| 75 | #define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ | ||
| 76 | #endif | ||
| 77 | |||
| 78 | #ifndef CPM_AUD | ||
| 79 | #define CPM_AUD 0x00000000 | ||
| 80 | #endif | ||
| 81 | #ifndef CPM_BRG | ||
| 82 | #define CPM_BRG 0x00000000 | ||
| 83 | #endif | ||
| 84 | #ifndef CPM_CBS | ||
| 85 | #define CPM_CBS 0x00000000 | ||
| 86 | #endif | ||
| 87 | #ifndef CPM_CPU | ||
| 88 | #define CPM_CPU 0x00000000 | ||
| 89 | #endif | ||
| 90 | #ifndef CPM_DCP | ||
| 91 | #define CPM_DCP 0x00000000 | ||
| 92 | #endif | ||
| 93 | #ifndef CPM_DCRX | ||
| 94 | #define CPM_DCRX 0x00000000 | ||
| 95 | #endif | ||
| 96 | #ifndef CPM_DENC | ||
| 97 | #define CPM_DENC 0x00000000 | ||
| 98 | #endif | ||
| 99 | #ifndef CPM_DMA | ||
| 100 | #define CPM_DMA 0x00000000 | ||
| 101 | #endif | ||
| 102 | #ifndef CPM_DSCR | ||
| 103 | #define CPM_DSCR 0x00000000 | ||
| 104 | #endif | ||
| 105 | #ifndef CPM_EBC | ||
| 106 | #define CPM_EBC 0x00000000 | ||
| 107 | #endif | ||
| 108 | #ifndef CPM_EBIU | ||
| 109 | #define CPM_EBIU 0x00000000 | ||
| 110 | #endif | ||
| 111 | #ifndef CPM_EMAC_MM | ||
| 112 | #define CPM_EMAC_MM 0x00000000 | ||
| 113 | #endif | ||
| 114 | #ifndef CPM_EMAC_RM | ||
| 115 | #define CPM_EMAC_RM 0x00000000 | ||
| 116 | #endif | ||
| 117 | #ifndef CPM_EMAC_TM | ||
| 118 | #define CPM_EMAC_TM 0x00000000 | ||
| 119 | #endif | ||
| 120 | #ifndef CPM_GPIO0 | ||
| 121 | #define CPM_GPIO0 0x00000000 | ||
| 122 | #endif | ||
| 123 | #ifndef CPM_GPT | ||
| 124 | #define CPM_GPT 0x00000000 | ||
| 125 | #endif | ||
| 126 | #ifndef CPM_I1284 | ||
| 127 | #define CPM_I1284 0x00000000 | ||
| 128 | #endif | ||
| 129 | #ifndef CPM_IIC0 | ||
| 130 | #define CPM_IIC0 0x00000000 | ||
| 131 | #endif | ||
| 132 | #ifndef CPM_IIC1 | ||
| 133 | #define CPM_IIC1 0x00000000 | ||
| 134 | #endif | ||
| 135 | #ifndef CPM_MSI | ||
| 136 | #define CPM_MSI 0x00000000 | ||
| 137 | #endif | ||
| 138 | #ifndef CPM_PCI | ||
| 139 | #define CPM_PCI 0x00000000 | ||
| 140 | #endif | ||
| 141 | #ifndef CPM_PLB | ||
| 142 | #define CPM_PLB 0x00000000 | ||
| 143 | #endif | ||
| 144 | #ifndef CPM_SC0 | ||
| 145 | #define CPM_SC0 0x00000000 | ||
| 146 | #endif | ||
| 147 | #ifndef CPM_SC1 | ||
| 148 | #define CPM_SC1 0x00000000 | ||
| 149 | #endif | ||
| 150 | #ifndef CPM_SDRAM0 | ||
| 151 | #define CPM_SDRAM0 0x00000000 | ||
| 152 | #endif | ||
| 153 | #ifndef CPM_SDRAM1 | ||
| 154 | #define CPM_SDRAM1 0x00000000 | ||
| 155 | #endif | ||
| 156 | #ifndef CPM_TMRCLK | ||
| 157 | #define CPM_TMRCLK 0x00000000 | ||
| 158 | #endif | ||
| 159 | #ifndef CPM_UART0 | ||
| 160 | #define CPM_UART0 0x00000000 | ||
| 161 | #endif | ||
| 162 | #ifndef CPM_UART1 | ||
| 163 | #define CPM_UART1 0x00000000 | ||
| 164 | #endif | ||
| 165 | #ifndef CPM_UART2 | ||
| 166 | #define CPM_UART2 0x00000000 | ||
| 167 | #endif | ||
| 168 | #ifndef CPM_UIC | ||
| 169 | #define CPM_UIC 0x00000000 | ||
| 170 | #endif | ||
| 171 | #ifndef CPM_VID2 | ||
| 172 | #define CPM_VID2 0x00000000 | ||
| 173 | #endif | ||
| 174 | #ifndef CPM_XPT27 | ||
| 175 | #define CPM_XPT27 0x00000000 | ||
| 176 | #endif | ||
| 177 | #ifndef CPM_XPT54 | ||
| 178 | #define CPM_XPT54 0x00000000 | ||
| 179 | #endif | ||
| 180 | |||
| 181 | #ifdef DCRN_CPMSR_BASE | ||
| 182 | #define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ | ||
| 183 | #define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ | ||
| 184 | #endif | ||
| 185 | |||
| 186 | #ifdef DCRN_DCP0_BASE | ||
| 187 | #define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) /* Decompression Controller Address */ | ||
| 188 | #define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) /* Decompression Controller Data */ | ||
| 189 | #endif | ||
| 190 | |||
| 191 | #ifdef DCRN_DCRX_BASE | ||
| 192 | #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ | ||
| 193 | #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ | ||
| 194 | #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ | ||
| 195 | #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ | ||
| 196 | #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ | ||
| 197 | #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ | ||
| 198 | #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ | ||
| 199 | #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ | ||
| 200 | #endif | ||
| 201 | |||
| 202 | #ifdef DCRN_DMA0_BASE | ||
| 203 | #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */ | ||
| 204 | #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ | ||
| 205 | #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */ | ||
| 206 | #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */ | ||
| 207 | #ifdef DCRNCAP_DMA_CC | ||
| 208 | #define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */ | ||
| 209 | #endif | ||
| 210 | |||
| 211 | #ifdef DCRNCAP_DMA_SG | ||
| 212 | #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */ | ||
| 213 | #endif | ||
| 214 | #endif | ||
| 215 | |||
| 216 | #ifdef DCRN_DMA1_BASE | ||
| 217 | #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control Register 1 */ | ||
| 218 | #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ | ||
| 219 | #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) /* DMA Destination Address Register 1 */ | ||
| 220 | #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ | ||
| 221 | |||
| 222 | #ifdef DCRNCAP_DMA_CC | ||
| 223 | #define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) /* DMA Chained Count Register 1 */ | ||
| 224 | #endif | ||
| 225 | #ifdef DCRNCAP_DMA_SG | ||
| 226 | #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 1 */ | ||
| 227 | #endif | ||
| 228 | #endif | ||
| 229 | |||
| 230 | #ifdef DCRN_DMA2_BASE | ||
| 231 | #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ | ||
| 232 | #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ | ||
| 233 | #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ | ||
| 234 | #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ | ||
| 235 | #ifdef DCRNCAP_DMA_CC | ||
| 236 | #define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ | ||
| 237 | #endif | ||
| 238 | #ifdef DCRNCAP_DMA_SG | ||
| 239 | #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ | ||
| 240 | #endif | ||
| 241 | #endif | ||
| 242 | |||
| 243 | #ifdef DCRN_DMA3_BASE | ||
| 244 | #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ | ||
| 245 | #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ | ||
| 246 | #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ | ||
| 247 | #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ | ||
| 248 | #ifdef DCRNCAP_DMA_CC | ||
| 249 | #define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ | ||
| 250 | #endif | ||
| 251 | #ifdef DCRNCAP_DMA_SG | ||
| 252 | #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ | ||
| 253 | #endif | ||
| 254 | #endif | ||
| 255 | |||
| 256 | #ifdef DCRN_DMASR_BASE | ||
| 257 | #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ | ||
| 258 | #ifdef DCRNCAP_DMA_SG | ||
| 259 | #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ | ||
| 260 | /* don't know if these two registers always exist if scatter/gather exists */ | ||
| 261 | #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ | ||
| 262 | #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ | ||
| 263 | #endif | ||
| 264 | #endif | ||
| 265 | |||
| 266 | #ifdef DCRN_EBC_BASE | ||
| 267 | #define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ | ||
| 268 | #define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ | ||
| 269 | #endif | ||
| 270 | |||
| 271 | #ifdef DCRN_EXIER_BASE | ||
| 272 | #define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ | ||
| 273 | #endif | ||
| 274 | |||
| 275 | #ifdef DCRN_EBIMC_BASE | ||
| 276 | #define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ | ||
| 277 | #define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ | ||
| 278 | #define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ | ||
| 279 | #define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ | ||
| 280 | #define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ | ||
| 281 | #define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ | ||
| 282 | #define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ | ||
| 283 | #define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ | ||
| 284 | #define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */ | ||
| 285 | #define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */ | ||
| 286 | #define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */ | ||
| 287 | #define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */ | ||
| 288 | #define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */ | ||
| 289 | #define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */ | ||
| 290 | #define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */ | ||
| 291 | #define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */ | ||
| 292 | #define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */ | ||
| 293 | #define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */ | ||
| 294 | #define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */ | ||
| 295 | #endif | ||
| 296 | |||
| 297 | #ifdef DCRN_EXISR_BASE | ||
| 298 | #define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ | ||
| 299 | #endif | ||
| 300 | #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ | ||
| 301 | #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ | ||
| 302 | #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ | ||
| 303 | #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ | ||
| 304 | #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ | ||
| 305 | #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ | ||
| 306 | #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ | ||
| 307 | #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ | ||
| 308 | #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ | ||
| 309 | #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ | ||
| 310 | #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ | ||
| 311 | #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ | ||
| 312 | #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ | ||
| 313 | #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ | ||
| 314 | |||
| 315 | #ifdef DCRN_IOCR_BASE | ||
| 316 | #define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ | ||
| 317 | #endif | ||
| 318 | #define IOCR_E0TE 0x80000000 | ||
| 319 | #define IOCR_E0LP 0x40000000 | ||
| 320 | #define IOCR_E1TE 0x20000000 | ||
| 321 | #define IOCR_E1LP 0x10000000 | ||
| 322 | #define IOCR_E2TE 0x08000000 | ||
| 323 | #define IOCR_E2LP 0x04000000 | ||
| 324 | #define IOCR_E3TE 0x02000000 | ||
| 325 | #define IOCR_E3LP 0x01000000 | ||
| 326 | #define IOCR_E4TE 0x00800000 | ||
| 327 | #define IOCR_E4LP 0x00400000 | ||
| 328 | #define IOCR_EDT 0x00080000 | ||
| 329 | #define IOCR_SOR 0x00040000 | ||
| 330 | #define IOCR_EDO 0x00008000 | ||
| 331 | #define IOCR_2XC 0x00004000 | ||
| 332 | #define IOCR_ATC 0x00002000 | ||
| 333 | #define IOCR_SPD 0x00001000 | ||
| 334 | #define IOCR_BEM 0x00000800 | ||
| 335 | #define IOCR_PTD 0x00000400 | ||
| 336 | #define IOCR_ARE 0x00000080 | ||
| 337 | #define IOCR_DRC 0x00000020 | ||
| 338 | #define IOCR_RDM(x) (((x) & 0x3) << 3) | ||
| 339 | #define IOCR_TCS 0x00000004 | ||
| 340 | #define IOCR_SCS 0x00000002 | ||
| 341 | #define IOCR_SPC 0x00000001 | ||
| 342 | |||
| 343 | #ifdef DCRN_MAL_BASE | ||
| 344 | #define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */ | ||
| 345 | #define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */ | ||
| 346 | #define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */ | ||
| 347 | #define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */ | ||
| 348 | #define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */ | ||
| 349 | #define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */ | ||
| 350 | #define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */ | ||
| 351 | #define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */ | ||
| 352 | #define DCRN_MALRXCARR (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */ | ||
| 353 | #define DCRN_MALRXCASR (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */ | ||
| 354 | #define DCRN_MALRXDEIR (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */ | ||
| 355 | #define DCRN_MALRXEOBISR (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status */ | ||
| 356 | #define DCRN_MALRXCTP0R (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */ | ||
| 357 | #define DCRN_MALTXCTP0R (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */ | ||
| 358 | #define DCRN_MALTXCTP1R (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */ | ||
| 359 | #define DCRN_MALRCBS0 (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */ | ||
| 360 | #endif | ||
| 361 | /* DCRN_MALCR */ | ||
| 362 | #define MALCR_MMSR 0x80000000/* MAL Software reset */ | ||
| 363 | #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ | ||
| 364 | #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ | ||
| 365 | #define MALCR_PLBP_3 0x00C00000 /* highest */ | ||
| 366 | #define MALCR_GA 0x00200000 /* Guarded Active Bit */ | ||
| 367 | #define MALCR_OA 0x00100000 /* Ordered Active Bit */ | ||
| 368 | #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ | ||
| 369 | #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ | ||
| 370 | #define MALCR_PLBLT_2 0x00020000 | ||
| 371 | #define MALCR_PLBLT_3 0x00010000 | ||
| 372 | #define MALCR_PLBLT_4 0x00008000 | ||
| 373 | #define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ | ||
| 374 | #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ | ||
| 375 | #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ | ||
| 376 | #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ | ||
| 377 | #define MALCR_LEA 0x00000002 /* Locked Error Active */ | ||
| 378 | #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ | ||
| 379 | /* DCRN_MALESR */ | ||
| 380 | #define MALESR_EVB 0x80000000 /* Error Valid Bit */ | ||
| 381 | #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ | ||
| 382 | #define MALESR_DE 0x00100000 /* Descriptor Error */ | ||
| 383 | #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ | ||
| 384 | #define MALESR_OTE 0x00040000 /* OPB Timeout Error */ | ||
| 385 | #define MALESR_OSE 0x00020000 /* OPB Slave Error */ | ||
| 386 | #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ | ||
| 387 | #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ | ||
| 388 | #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ | ||
| 389 | #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ | ||
| 390 | #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ | ||
| 391 | #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ | ||
| 392 | /* DCRN_MALIER */ | ||
| 393 | #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ | ||
| 394 | #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ | ||
| 395 | #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ | ||
| 396 | #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ | ||
| 397 | #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ | ||
| 398 | /* DCRN_MALTXEOBISR */ | ||
| 399 | #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ | ||
| 400 | #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ | ||
| 401 | |||
| 402 | #ifdef DCRN_OCM0_BASE | ||
| 403 | #define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ | ||
| 404 | #define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ | ||
| 405 | #define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ | ||
| 406 | #define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ | ||
| 407 | #endif | ||
| 408 | |||
| 409 | #ifdef DCRN_PLB0_BASE | ||
| 410 | #define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) | ||
| 411 | #define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) | ||
| 412 | /* doesn't exist on stb03xxx? */ | ||
| 413 | #define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) | ||
| 414 | #endif | ||
| 415 | |||
| 416 | #ifdef DCRN_PLB1_BASE | ||
| 417 | #define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) | ||
| 418 | #define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) | ||
| 419 | /* doesn't exist on stb03xxx? */ | ||
| 420 | #define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) | ||
| 421 | #endif | ||
| 422 | |||
| 423 | #ifdef DCRN_PLLMR_BASE | ||
| 424 | #define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ | ||
| 425 | #endif | ||
| 426 | |||
| 427 | #ifdef DCRN_POB0_BASE | ||
| 428 | #define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) | ||
| 429 | #define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) | ||
| 430 | #define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) | ||
| 431 | #endif | ||
| 432 | |||
| 433 | #ifdef DCRN_SCCR_BASE | ||
| 434 | #define DCRN_SCCR (DCRN_SCCR_BASE + 0x0) | ||
| 435 | #endif | ||
| 436 | |||
| 437 | #ifdef DCRN_SDRAM0_BASE | ||
| 438 | #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */ | ||
| 439 | #define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */ | ||
| 440 | #endif | ||
| 441 | |||
| 442 | #ifdef DCRN_UIC0_BASE | ||
| 443 | #define DCRN_UIC0_SR (DCRN_UIC0_BASE + 0x0) | ||
| 444 | #define DCRN_UIC0_ER (DCRN_UIC0_BASE + 0x2) | ||
| 445 | #define DCRN_UIC0_CR (DCRN_UIC0_BASE + 0x3) | ||
| 446 | #define DCRN_UIC0_PR (DCRN_UIC0_BASE + 0x4) | ||
| 447 | #define DCRN_UIC0_TR (DCRN_UIC0_BASE + 0x5) | ||
| 448 | #define DCRN_UIC0_MSR (DCRN_UIC0_BASE + 0x6) | ||
| 449 | #define DCRN_UIC0_VR (DCRN_UIC0_BASE + 0x7) | ||
| 450 | #define DCRN_UIC0_VCR (DCRN_UIC0_BASE + 0x8) | ||
| 451 | #endif | ||
| 452 | |||
| 453 | #ifdef DCRN_UIC1_BASE | ||
| 454 | #define DCRN_UIC1_SR (DCRN_UIC1_BASE + 0x0) | ||
| 455 | #define DCRN_UIC1_SRS (DCRN_UIC1_BASE + 0x1) | ||
| 456 | #define DCRN_UIC1_ER (DCRN_UIC1_BASE + 0x2) | ||
| 457 | #define DCRN_UIC1_CR (DCRN_UIC1_BASE + 0x3) | ||
| 458 | #define DCRN_UIC1_PR (DCRN_UIC1_BASE + 0x4) | ||
| 459 | #define DCRN_UIC1_TR (DCRN_UIC1_BASE + 0x5) | ||
| 460 | #define DCRN_UIC1_MSR (DCRN_UIC1_BASE + 0x6) | ||
| 461 | #define DCRN_UIC1_VR (DCRN_UIC1_BASE + 0x7) | ||
| 462 | #define DCRN_UIC1_VCR (DCRN_UIC1_BASE + 0x8) | ||
| 463 | #endif | ||
| 464 | |||
| 465 | #ifdef DCRN_SDRAM0_BASE | ||
| 466 | #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ | ||
| 467 | #define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ | ||
| 468 | #endif | ||
| 469 | |||
| 470 | #ifdef DCRN_OCM0_BASE | ||
| 471 | #define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ | ||
| 472 | #define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ | ||
| 473 | #define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ | ||
| 474 | #define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ | ||
| 475 | #endif | ||
| 476 | |||
| 477 | #endif /* __ASM_IBM403_H__ */ | ||
| 478 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm405.h b/include/asm-ppc/ibm405.h deleted file mode 100644 index 4e5be9e2c153..000000000000 --- a/include/asm-ppc/ibm405.h +++ /dev/null | |||
| @@ -1,299 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Author: Armin Kuster <akuster@mvista.com> | ||
| 3 | * | ||
| 4 | * 2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 5 | * the terms of the GNU General Public License version 2. This program | ||
| 6 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 7 | * or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifdef __KERNEL__ | ||
| 11 | #ifndef __ASM_IBM405_H__ | ||
| 12 | #define __ASM_IBM405_H__ | ||
| 13 | |||
| 14 | #ifdef DCRN_BE_BASE | ||
| 15 | #define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ | ||
| 16 | #define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ | ||
| 17 | #endif | ||
| 18 | /* DCRN_BESR */ | ||
| 19 | #define BESR_DSES 0x80000000 /* Data-Side Error Status */ | ||
| 20 | #define BESR_DMES 0x40000000 /* DMA Error Status */ | ||
| 21 | #define BESR_RWS 0x20000000 /* Read/Write Status */ | ||
| 22 | #define BESR_ETMASK 0x1C000000 /* Error Type */ | ||
| 23 | #define ET_PROT 0 | ||
| 24 | #define ET_PARITY 1 | ||
| 25 | #define ET_NCFG 2 | ||
| 26 | #define ET_BUSERR 4 | ||
| 27 | #define ET_BUSTO 6 | ||
| 28 | |||
| 29 | /* Clock and power management shifts for emacs */ | ||
| 30 | #define IBM_CPM_EMMII 0 /* Shift value for MII */ | ||
| 31 | #define IBM_CPM_EMRX 1 /* Shift value for recv */ | ||
| 32 | #define IBM_CPM_EMTX 2 /* Shift value for MAC */ | ||
| 33 | |||
| 34 | #ifdef DCRN_CHCR_BASE | ||
| 35 | #define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ | ||
| 36 | #define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ | ||
| 37 | #endif | ||
| 38 | #define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ | ||
| 39 | |||
| 40 | #ifdef DCRN_CHPSR_BASE | ||
| 41 | #define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ | ||
| 42 | #endif | ||
| 43 | |||
| 44 | #ifdef DCRN_CPMFR_BASE | ||
| 45 | #define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifdef DCRN_CPMSR_BASE | ||
| 49 | #define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ | ||
| 50 | #define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifdef DCRN_DCP0_BASE | ||
| 54 | /* Decompression Controller Address */ | ||
| 55 | #define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) | ||
| 56 | /* Decompression Controller Data */ | ||
| 57 | #define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) | ||
| 58 | #else | ||
| 59 | #define DCRN_DCP0_CFGADDR 0x0 | ||
| 60 | #define DCRN_DCP0_CFGDATA 0x0 | ||
| 61 | #endif | ||
| 62 | |||
| 63 | #ifdef DCRN_DMA0_BASE | ||
| 64 | /* DMA Channel Control Register 0 */ | ||
| 65 | #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) | ||
| 66 | #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ | ||
| 67 | /* DMA Destination Address Register 0 */ | ||
| 68 | #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) | ||
| 69 | /* DMA Source Address Register 0 */ | ||
| 70 | #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) | ||
| 71 | #ifdef DCRNCAP_DMA_CC | ||
| 72 | /* DMA Chained Count Register 0 */ | ||
| 73 | #define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) | ||
| 74 | #endif | ||
| 75 | #ifdef DCRNCAP_DMA_SG | ||
| 76 | /* DMA Scatter/Gather Descriptor Addr 0 */ | ||
| 77 | #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) | ||
| 78 | #endif | ||
| 79 | #endif | ||
| 80 | |||
| 81 | #ifdef DCRN_DMA1_BASE | ||
| 82 | /* DMA Channel Control Register 1 */ | ||
| 83 | #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) | ||
| 84 | #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ | ||
| 85 | /* DMA Destination Address Register 1 */ | ||
| 86 | #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) | ||
| 87 | /* DMA Source Address Register 1 */ | ||
| 88 | #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ | ||
| 89 | #ifdef DCRNCAP_DMA_CC | ||
| 90 | /* DMA Chained Count Register 1 */ | ||
| 91 | #define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) | ||
| 92 | #endif | ||
| 93 | #ifdef DCRNCAP_DMA_SG | ||
| 94 | /* DMA Scatter/Gather Descriptor Addr 1 */ | ||
| 95 | #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) | ||
| 96 | #endif | ||
| 97 | #endif | ||
| 98 | |||
| 99 | #ifdef DCRN_DMA2_BASE | ||
| 100 | #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ | ||
| 101 | #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ | ||
| 102 | #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ | ||
| 103 | #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ | ||
| 104 | #ifdef DCRNCAP_DMA_CC | ||
| 105 | #define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ | ||
| 106 | #endif | ||
| 107 | #ifdef DCRNCAP_DMA_SG | ||
| 108 | #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ | ||
| 109 | #endif | ||
| 110 | #endif | ||
| 111 | |||
| 112 | #ifdef DCRN_DMA3_BASE | ||
| 113 | #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ | ||
| 114 | #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ | ||
| 115 | #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ | ||
| 116 | #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ | ||
| 117 | #ifdef DCRNCAP_DMA_CC | ||
| 118 | #define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ | ||
| 119 | #endif | ||
| 120 | #ifdef DCRNCAP_DMA_SG | ||
| 121 | #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ | ||
| 122 | #endif | ||
| 123 | #endif | ||
| 124 | |||
| 125 | #ifdef DCRN_DMASR_BASE | ||
| 126 | #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ | ||
| 127 | #ifdef DCRNCAP_DMA_SG | ||
| 128 | #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ | ||
| 129 | /* don't know if these two registers always exist if scatter/gather exists */ | ||
| 130 | #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ | ||
| 131 | #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ | ||
| 132 | #endif | ||
| 133 | #endif | ||
| 134 | |||
| 135 | #ifdef DCRN_EBC_BASE | ||
| 136 | #define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ | ||
| 137 | #define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ | ||
| 138 | #endif | ||
| 139 | |||
| 140 | #ifdef DCRN_EXIER_BASE | ||
| 141 | #define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ | ||
| 142 | #endif | ||
| 143 | |||
| 144 | #ifdef DCRN_EXISR_BASE | ||
| 145 | #define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ | ||
| 146 | #endif | ||
| 147 | |||
| 148 | #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ | ||
| 149 | #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ | ||
| 150 | #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ | ||
| 151 | #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ | ||
| 152 | #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ | ||
| 153 | #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ | ||
| 154 | #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ | ||
| 155 | #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ | ||
| 156 | #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ | ||
| 157 | #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ | ||
| 158 | #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ | ||
| 159 | #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ | ||
| 160 | #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ | ||
| 161 | #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ | ||
| 162 | |||
| 163 | #ifdef DCRN_IOCR_BASE | ||
| 164 | #define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ | ||
| 165 | #endif | ||
| 166 | #define IOCR_E0TE 0x80000000 | ||
| 167 | #define IOCR_E0LP 0x40000000 | ||
| 168 | #define IOCR_E1TE 0x20000000 | ||
| 169 | #define IOCR_E1LP 0x10000000 | ||
| 170 | #define IOCR_E2TE 0x08000000 | ||
| 171 | #define IOCR_E2LP 0x04000000 | ||
| 172 | #define IOCR_E3TE 0x02000000 | ||
| 173 | #define IOCR_E3LP 0x01000000 | ||
| 174 | #define IOCR_E4TE 0x00800000 | ||
| 175 | #define IOCR_E4LP 0x00400000 | ||
| 176 | #define IOCR_EDT 0x00080000 | ||
| 177 | #define IOCR_SOR 0x00040000 | ||
| 178 | #define IOCR_EDO 0x00008000 | ||
| 179 | #define IOCR_2XC 0x00004000 | ||
| 180 | #define IOCR_ATC 0x00002000 | ||
| 181 | #define IOCR_SPD 0x00001000 | ||
| 182 | #define IOCR_BEM 0x00000800 | ||
| 183 | #define IOCR_PTD 0x00000400 | ||
| 184 | #define IOCR_ARE 0x00000080 | ||
| 185 | #define IOCR_DRC 0x00000020 | ||
| 186 | #define IOCR_RDM(x) (((x) & 0x3) << 3) | ||
| 187 | #define IOCR_TCS 0x00000004 | ||
| 188 | #define IOCR_SCS 0x00000002 | ||
| 189 | #define IOCR_SPC 0x00000001 | ||
| 190 | |||
| 191 | #define DCRN_MALCR(base) (base + 0x0) /* MAL Configuration */ | ||
| 192 | #define DCRN_MALDBR(base) ((base) + 0x3) /* Debug Register */ | ||
| 193 | #define DCRN_MALESR(base) ((base) + 0x1) /* Error Status */ | ||
| 194 | #define DCRN_MALIER(base) ((base) + 0x2) /* Interrupt Enable */ | ||
| 195 | #define DCRN_MALTXCARR(base) ((base) + 0x5) /* TX Channed Active Reset Register */ | ||
| 196 | #define DCRN_MALTXCASR(base) ((base) + 0x4) /* TX Channel Active Set Register */ | ||
| 197 | #define DCRN_MALTXDEIR(base) ((base) + 0x7) /* Tx Descriptor Error Interrupt */ | ||
| 198 | #define DCRN_MALTXEOBISR(base) ((base) + 0x6) /* Tx End of Buffer Interrupt Status */ | ||
| 199 | #define DCRN_MALRXCARR(base) ((base) + 0x11) /* RX Channed Active Reset Register */ | ||
| 200 | #define DCRN_MALRXCASR(base) ((base) + 0x10) /* RX Channel Active Set Register */ | ||
| 201 | #define DCRN_MALRXDEIR(base) ((base) + 0x13) /* Rx Descriptor Error Interrupt */ | ||
| 202 | #define DCRN_MALRXEOBISR(base) ((base) + 0x12) /* Rx End of Buffer Interrupt Status */ | ||
| 203 | #define DCRN_MALRXCTP0R(base) ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */ | ||
| 204 | #define DCRN_MALRXCTP1R(base) ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */ | ||
| 205 | #define DCRN_MALTXCTP0R(base) ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */ | ||
| 206 | #define DCRN_MALTXCTP1R(base) ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */ | ||
| 207 | #define DCRN_MALTXCTP2R(base) ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */ | ||
| 208 | #define DCRN_MALTXCTP3R(base) ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */ | ||
| 209 | #define DCRN_MALRCBS0(base) ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */ | ||
| 210 | #define DCRN_MALRCBS1(base) ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */ | ||
| 211 | |||
| 212 | /* DCRN_MALCR */ | ||
| 213 | #define MALCR_MMSR 0x80000000 /* MAL Software reset */ | ||
| 214 | #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ | ||
| 215 | #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ | ||
| 216 | #define MALCR_PLBP_3 0x00C00000 /* highest */ | ||
| 217 | #define MALCR_GA 0x00200000 /* Guarded Active Bit */ | ||
| 218 | #define MALCR_OA 0x00100000 /* Ordered Active Bit */ | ||
| 219 | #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ | ||
| 220 | #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ | ||
| 221 | #define MALCR_PLBLT_2 0x00020000 | ||
| 222 | #define MALCR_PLBLT_3 0x00010000 | ||
| 223 | #define MALCR_PLBLT_4 0x00008000 | ||
| 224 | #define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ | ||
| 225 | #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ | ||
| 226 | #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ | ||
| 227 | #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ | ||
| 228 | #define MALCR_LEA 0x00000002 /* Locked Error Active */ | ||
| 229 | #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ | ||
| 230 | /* DCRN_MALESR */ | ||
| 231 | #define MALESR_EVB 0x80000000 /* Error Valid Bit */ | ||
| 232 | #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ | ||
| 233 | #define MALESR_DE 0x00100000 /* Descriptor Error */ | ||
| 234 | #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ | ||
| 235 | #define MALESR_OTE 0x00040000 /* OPB Timeout Error */ | ||
| 236 | #define MALESR_OSE 0x00020000 /* OPB Slave Error */ | ||
| 237 | #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ | ||
| 238 | #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ | ||
| 239 | #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ | ||
| 240 | #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ | ||
| 241 | #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ | ||
| 242 | #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ | ||
| 243 | /* DCRN_MALIER */ | ||
| 244 | #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ | ||
| 245 | #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ | ||
| 246 | #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ | ||
| 247 | #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ | ||
| 248 | #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ | ||
| 249 | /* DCRN_MALTXEOBISR */ | ||
| 250 | #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ | ||
| 251 | #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ | ||
| 252 | |||
| 253 | #ifdef DCRN_PLB0_BASE | ||
| 254 | #define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) | ||
| 255 | #define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) | ||
| 256 | /* doesn't exist on stb03xxx? */ | ||
| 257 | #define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) | ||
| 258 | #endif | ||
| 259 | |||
| 260 | #ifdef DCRN_PLB1_BASE | ||
| 261 | #define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) | ||
| 262 | #define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) | ||
| 263 | /* doesn't exist on stb03xxx? */ | ||
| 264 | #define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) | ||
| 265 | #endif | ||
| 266 | |||
| 267 | #ifdef DCRN_PLLMR_BASE | ||
| 268 | #define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ | ||
| 269 | #endif | ||
| 270 | |||
| 271 | #ifdef DCRN_POB0_BASE | ||
| 272 | #define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) | ||
| 273 | #define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) | ||
| 274 | #define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) | ||
| 275 | #endif | ||
| 276 | |||
| 277 | #define DCRN_UIC_SR(base) (base + 0x0) | ||
| 278 | #define DCRN_UIC_ER(base) (base + 0x2) | ||
| 279 | #define DCRN_UIC_CR(base) (base + 0x3) | ||
| 280 | #define DCRN_UIC_PR(base) (base + 0x4) | ||
| 281 | #define DCRN_UIC_TR(base) (base + 0x5) | ||
| 282 | #define DCRN_UIC_MSR(base) (base + 0x6) | ||
| 283 | #define DCRN_UIC_VR(base) (base + 0x7) | ||
| 284 | #define DCRN_UIC_VCR(base) (base + 0x8) | ||
| 285 | |||
| 286 | #ifdef DCRN_SDRAM0_BASE | ||
| 287 | #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ | ||
| 288 | #define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ | ||
| 289 | #endif | ||
| 290 | |||
| 291 | #ifdef DCRN_OCM0_BASE | ||
| 292 | #define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ | ||
| 293 | #define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ | ||
| 294 | #define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ | ||
| 295 | #define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ | ||
| 296 | #endif | ||
| 297 | |||
| 298 | #endif /* __ASM_IBM405_H__ */ | ||
| 299 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h deleted file mode 100644 index 7818b54b6e37..000000000000 --- a/include/asm-ppc/ibm44x.h +++ /dev/null | |||
| @@ -1,674 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/ibm44x.h | ||
| 3 | * | ||
| 4 | * PPC44x definitions | ||
| 5 | * | ||
| 6 | * Matt Porter <mporter@kernel.crashing.org> | ||
| 7 | * | ||
| 8 | * Copyright 2002-2005 MontaVista Software Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | #ifndef __ASM_IBM44x_H__ | ||
| 18 | #define __ASM_IBM44x_H__ | ||
| 19 | |||
| 20 | |||
| 21 | #ifndef NR_BOARD_IRQS | ||
| 22 | #define NR_BOARD_IRQS 0 | ||
| 23 | #endif | ||
| 24 | |||
| 25 | #define _IO_BASE isa_io_base | ||
| 26 | #define _ISA_MEM_BASE isa_mem_base | ||
| 27 | #define PCI_DRAM_OFFSET pci_dram_offset | ||
| 28 | |||
| 29 | /* TLB entry offset/size used for pinning kernel lowmem */ | ||
| 30 | #define PPC44x_PIN_SHIFT 28 | ||
| 31 | #define PPC_PIN_SIZE (1 << PPC44x_PIN_SHIFT) | ||
| 32 | |||
| 33 | /* Lowest TLB slot consumed by the default pinned TLBs */ | ||
| 34 | #define PPC44x_LOW_SLOT 63 | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Least significant 32-bits and extended real page number (ERPN) of | ||
| 38 | * UART0 physical address location for early serial text debug | ||
| 39 | */ | ||
| 40 | #if defined(CONFIG_440SP) | ||
| 41 | #define UART0_PHYS_ERPN 1 | ||
| 42 | #define UART0_PHYS_IO_BASE 0xf0000200 | ||
| 43 | #elif defined(CONFIG_440SPE) | ||
| 44 | #define UART0_PHYS_ERPN 4 | ||
| 45 | #define UART0_PHYS_IO_BASE 0xf0000200 | ||
| 46 | #elif defined(CONFIG_440EP) | ||
| 47 | #define UART0_PHYS_IO_BASE 0xe0000000 | ||
| 48 | #else | ||
| 49 | #define UART0_PHYS_ERPN 1 | ||
| 50 | #define UART0_PHYS_IO_BASE 0x40000200 | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* | ||
| 54 | * XXX This 36-bit trap stuff will move somewhere in syslib/ | ||
| 55 | * when we rework/abstract the PPC44x PCI-X handling -mdp | ||
| 56 | */ | ||
| 57 | |||
| 58 | /* | ||
| 59 | * Standard 4GB "page" definitions | ||
| 60 | */ | ||
| 61 | #if defined(CONFIG_440SP) | ||
| 62 | #define PPC44x_IO_PAGE 0x0000000100000000ULL | ||
| 63 | #define PPC44x_PCICFG_PAGE 0x0000000900000000ULL | ||
| 64 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE | ||
| 65 | #define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL | ||
| 66 | #elif defined(CONFIG_440SPE) | ||
| 67 | #define PPC44x_IO_PAGE 0x0000000400000000ULL | ||
| 68 | #define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL | ||
| 69 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE | ||
| 70 | #define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL | ||
| 71 | #elif defined(CONFIG_440EP) | ||
| 72 | #define PPC44x_IO_PAGE 0x0000000000000000ULL | ||
| 73 | #define PPC44x_PCICFG_PAGE 0x0000000000000000ULL | ||
| 74 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE | ||
| 75 | #define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL | ||
| 76 | #else | ||
| 77 | #define PPC44x_IO_PAGE 0x0000000100000000ULL | ||
| 78 | #define PPC44x_PCICFG_PAGE 0x0000000200000000ULL | ||
| 79 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE | ||
| 80 | #define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL | ||
| 81 | #endif | ||
| 82 | |||
| 83 | /* | ||
| 84 | * 36-bit trap ranges | ||
| 85 | */ | ||
| 86 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) | ||
| 87 | #define PPC44x_IO_LO 0xf0000000UL | ||
| 88 | #define PPC44x_IO_HI 0xf0000fffUL | ||
| 89 | #define PPC44x_PCI0CFG_LO 0x0ec00000UL | ||
| 90 | #define PPC44x_PCI0CFG_HI 0x0ec00007UL | ||
| 91 | #define PPC44x_PCI1CFG_LO 0x1ec00000UL | ||
| 92 | #define PPC44x_PCI1CFG_HI 0x1ec00007UL | ||
| 93 | #define PPC44x_PCI2CFG_LO 0x2ec00000UL | ||
| 94 | #define PPC44x_PCI2CFG_HI 0x2ec00007UL | ||
| 95 | #define PPC44x_PCIMEM_LO 0x80000000UL | ||
| 96 | #define PPC44x_PCIMEM_HI 0xdfffffffUL | ||
| 97 | #elif defined(CONFIG_440EP) | ||
| 98 | #define PPC44x_IO_LO 0xef500000UL | ||
| 99 | #define PPC44x_IO_HI 0xefffffffUL | ||
| 100 | #define PPC44x_PCI0CFG_LO 0xeec00000UL | ||
| 101 | #define PPC44x_PCI0CFG_HI 0xeecfffffUL | ||
| 102 | #define PPC44x_PCIMEM_LO 0xa0000000UL | ||
| 103 | #define PPC44x_PCIMEM_HI 0xdfffffffUL | ||
| 104 | #else | ||
| 105 | #define PPC44x_IO_LO 0x40000000UL | ||
| 106 | #define PPC44x_IO_HI 0x40000fffUL | ||
| 107 | #define PPC44x_PCI0CFG_LO 0x0ec00000UL | ||
| 108 | #define PPC44x_PCI0CFG_HI 0x0ec00007UL | ||
| 109 | #define PPC44x_PCIMEM_LO 0x80002000UL | ||
| 110 | #define PPC44x_PCIMEM_HI 0xffffffffUL | ||
| 111 | #endif | ||
| 112 | |||
| 113 | /* | ||
| 114 | * The "residual" board information structure the boot loader passes | ||
| 115 | * into the kernel. | ||
| 116 | */ | ||
| 117 | #ifndef __ASSEMBLY__ | ||
| 118 | |||
| 119 | /* | ||
| 120 | * DCRN definitions | ||
| 121 | */ | ||
| 122 | |||
| 123 | |||
| 124 | /* CPRs (440GX and 440SP/440SPe) */ | ||
| 125 | #define DCRN_CPR_CONFIG_ADDR 0xc | ||
| 126 | #define DCRN_CPR_CONFIG_DATA 0xd | ||
| 127 | |||
| 128 | #define DCRN_CPR_CLKUPD 0x0020 | ||
| 129 | #define DCRN_CPR_PLLC 0x0040 | ||
| 130 | #define DCRN_CPR_PLLD 0x0060 | ||
| 131 | #define DCRN_CPR_PRIMAD 0x0080 | ||
| 132 | #define DCRN_CPR_PRIMBD 0x00a0 | ||
| 133 | #define DCRN_CPR_OPBD 0x00c0 | ||
| 134 | #define DCRN_CPR_PERD 0x00e0 | ||
| 135 | #define DCRN_CPR_MALD 0x0100 | ||
| 136 | |||
| 137 | /* CPRs read/write helper macros */ | ||
| 138 | #define CPR_READ(offset) ({\ | ||
| 139 | mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ | ||
| 140 | mfdcr(DCRN_CPR_CONFIG_DATA);}) | ||
| 141 | #define CPR_WRITE(offset, data) ({\ | ||
| 142 | mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ | ||
| 143 | mtdcr(DCRN_CPR_CONFIG_DATA, data);}) | ||
| 144 | |||
| 145 | /* SDRs (440GX and 440SP/440SPe) */ | ||
| 146 | #define DCRN_SDR_CONFIG_ADDR 0xe | ||
| 147 | #define DCRN_SDR_CONFIG_DATA 0xf | ||
| 148 | #define DCRN_SDR_PFC0 0x4100 | ||
| 149 | #define DCRN_SDR_PFC1 0x4101 | ||
| 150 | #define DCRN_SDR_PFC1_EPS 0x1c00000 | ||
| 151 | #define DCRN_SDR_PFC1_EPS_SHIFT 22 | ||
| 152 | #define DCRN_SDR_PFC1_RMII 0x02000000 | ||
| 153 | #define DCRN_SDR_MFR 0x4300 | ||
| 154 | #define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ | ||
| 155 | #define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ | ||
| 156 | #define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ | ||
| 157 | #define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */ | ||
| 158 | #define DCRN_SDR_MFR_T0TXFL 0x00080000 | ||
| 159 | #define DCRN_SDR_MFR_T0TXFH 0x00040000 | ||
| 160 | #define DCRN_SDR_MFR_T1TXFL 0x00020000 | ||
| 161 | #define DCRN_SDR_MFR_T1TXFH 0x00010000 | ||
| 162 | #define DCRN_SDR_MFR_E0TXFL 0x00008000 | ||
| 163 | #define DCRN_SDR_MFR_E0TXFH 0x00004000 | ||
| 164 | #define DCRN_SDR_MFR_E0RXFL 0x00002000 | ||
| 165 | #define DCRN_SDR_MFR_E0RXFH 0x00001000 | ||
| 166 | #define DCRN_SDR_MFR_E1TXFL 0x00000800 | ||
| 167 | #define DCRN_SDR_MFR_E1TXFH 0x00000400 | ||
| 168 | #define DCRN_SDR_MFR_E1RXFL 0x00000200 | ||
| 169 | #define DCRN_SDR_MFR_E1RXFH 0x00000100 | ||
| 170 | #define DCRN_SDR_MFR_E2TXFL 0x00000080 | ||
| 171 | #define DCRN_SDR_MFR_E2TXFH 0x00000040 | ||
| 172 | #define DCRN_SDR_MFR_E2RXFL 0x00000020 | ||
| 173 | #define DCRN_SDR_MFR_E2RXFH 0x00000010 | ||
| 174 | #define DCRN_SDR_MFR_E3TXFL 0x00000008 | ||
| 175 | #define DCRN_SDR_MFR_E3TXFH 0x00000004 | ||
| 176 | #define DCRN_SDR_MFR_E3RXFL 0x00000002 | ||
| 177 | #define DCRN_SDR_MFR_E3RXFH 0x00000001 | ||
| 178 | #define DCRN_SDR_UART0 0x0120 | ||
| 179 | #define DCRN_SDR_UART1 0x0121 | ||
| 180 | |||
| 181 | #ifdef CONFIG_440EP | ||
| 182 | #define DCRN_SDR_UART2 0x0122 | ||
| 183 | #define DCRN_SDR_UART3 0x0123 | ||
| 184 | #define DCRN_SDR_CUST0 0x4000 | ||
| 185 | #endif | ||
| 186 | |||
| 187 | /* SDR read/write helper macros */ | ||
| 188 | #define SDR_READ(offset) ({\ | ||
| 189 | mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ | ||
| 190 | mfdcr(DCRN_SDR_CONFIG_DATA);}) | ||
| 191 | #define SDR_WRITE(offset, data) ({\ | ||
| 192 | mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ | ||
| 193 | mtdcr(DCRN_SDR_CONFIG_DATA,data);}) | ||
| 194 | |||
| 195 | /* DMA (excluding 440SP/440SPe) */ | ||
| 196 | #define DCRN_DMA0_BASE 0x100 | ||
| 197 | #define DCRN_DMA1_BASE 0x108 | ||
| 198 | #define DCRN_DMA2_BASE 0x110 | ||
| 199 | #define DCRN_DMA3_BASE 0x118 | ||
| 200 | #define DCRN_DMASR_BASE 0x120 | ||
| 201 | #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ | ||
| 202 | #define DCRN_MAL_BASE 0x180 | ||
| 203 | |||
| 204 | #ifdef CONFIG_440EP | ||
| 205 | #define DCRN_DMA2P40_BASE 0x300 | ||
| 206 | #define DCRN_DMA2P41_BASE 0x308 | ||
| 207 | #define DCRN_DMA2P42_BASE 0x310 | ||
| 208 | #define DCRN_DMA2P43_BASE 0x318 | ||
| 209 | #define DCRN_DMA2P4SR_BASE 0x320 | ||
| 210 | #endif | ||
| 211 | |||
| 212 | /* UIC */ | ||
| 213 | #define DCRN_UIC0_BASE 0xc0 | ||
| 214 | #define DCRN_UIC1_BASE 0xd0 | ||
| 215 | #define UIC0 DCRN_UIC0_BASE | ||
| 216 | #define UIC1 DCRN_UIC1_BASE | ||
| 217 | |||
| 218 | #ifdef CONFIG_440SPE | ||
| 219 | #define DCRN_UIC2_BASE 0xe0 | ||
| 220 | #define DCRN_UIC3_BASE 0xf0 | ||
| 221 | #define UIC2 DCRN_UIC2_BASE | ||
| 222 | #define UIC3 DCRN_UIC3_BASE | ||
| 223 | #else | ||
| 224 | #define DCRN_UIC2_BASE 0x210 | ||
| 225 | #define DCRN_UICB_BASE 0x200 | ||
| 226 | #define UIC2 DCRN_UIC2_BASE | ||
| 227 | #define UICB DCRN_UICB_BASE | ||
| 228 | #endif | ||
| 229 | |||
| 230 | #define DCRN_UIC_SR(base) (base + 0x0) | ||
| 231 | #define DCRN_UIC_ER(base) (base + 0x2) | ||
| 232 | #define DCRN_UIC_CR(base) (base + 0x3) | ||
| 233 | #define DCRN_UIC_PR(base) (base + 0x4) | ||
| 234 | #define DCRN_UIC_TR(base) (base + 0x5) | ||
| 235 | #define DCRN_UIC_MSR(base) (base + 0x6) | ||
| 236 | #define DCRN_UIC_VR(base) (base + 0x7) | ||
| 237 | #define DCRN_UIC_VCR(base) (base + 0x8) | ||
| 238 | |||
| 239 | #define UIC0_UIC1NC 0x00000002 | ||
| 240 | |||
| 241 | #ifdef CONFIG_440SPE | ||
| 242 | #define UIC0_UIC1NC 0x00000002 | ||
| 243 | #define UIC0_UIC2NC 0x00200000 | ||
| 244 | #define UIC0_UIC3NC 0x00008000 | ||
| 245 | #endif | ||
| 246 | |||
| 247 | #define UICB_UIC0NC 0x40000000 | ||
| 248 | #define UICB_UIC1NC 0x10000000 | ||
| 249 | #define UICB_UIC2NC 0x04000000 | ||
| 250 | |||
| 251 | /* 440 MAL DCRs */ | ||
| 252 | #define DCRN_MALCR(base) (base + 0x0) /* Configuration */ | ||
| 253 | #define DCRN_MALESR(base) (base + 0x1) /* Error Status */ | ||
| 254 | #define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */ | ||
| 255 | #define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */ | ||
| 256 | #define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */ | ||
| 257 | #define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */ | ||
| 258 | #define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */ | ||
| 259 | #define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */ | ||
| 260 | #define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */ | ||
| 261 | #define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */ | ||
| 262 | #define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */ | ||
| 263 | #define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */ | ||
| 264 | #define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */ | ||
| 265 | #define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */ | ||
| 266 | #define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */ | ||
| 267 | #define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */ | ||
| 268 | #define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */ | ||
| 269 | #define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */ | ||
| 270 | #define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */ | ||
| 271 | |||
| 272 | /* Compatibility DCRN's */ | ||
| 273 | #define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */ | ||
| 274 | #define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */ | ||
| 275 | #define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */ | ||
| 276 | #define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */ | ||
| 277 | #define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */ | ||
| 278 | #define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */ | ||
| 279 | #define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */ | ||
| 280 | #define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */ | ||
| 281 | |||
| 282 | #define MALCR_MMSR 0x80000000 /* MAL Software reset */ | ||
| 283 | #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ | ||
| 284 | #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ | ||
| 285 | #define MALCR_PLBP_3 0x00C00000 /* highest */ | ||
| 286 | #define MALCR_GA 0x00200000 /* Guarded Active Bit */ | ||
| 287 | #define MALCR_OA 0x00100000 /* Ordered Active Bit */ | ||
| 288 | #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ | ||
| 289 | #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ | ||
| 290 | #define MALCR_PLBLT_2 0x00020000 | ||
| 291 | #define MALCR_PLBLT_3 0x00010000 | ||
| 292 | #define MALCR_PLBLT_4 0x00008000 | ||
| 293 | #ifdef CONFIG_440GP | ||
| 294 | #define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */ | ||
| 295 | #else | ||
| 296 | #define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */ | ||
| 297 | #endif | ||
| 298 | #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ | ||
| 299 | #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ | ||
| 300 | #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ | ||
| 301 | #define MALCR_LEA 0x00000002 /* Locked Error Active */ | ||
| 302 | #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ | ||
| 303 | /* DCRN_MALESR */ | ||
| 304 | #define MALESR_EVB 0x80000000 /* Error Valid Bit */ | ||
| 305 | #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ | ||
| 306 | #define MALESR_DE 0x00100000 /* Descriptor Error */ | ||
| 307 | #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ | ||
| 308 | #define MALESR_OTE 0x00040000 /* OPB Timeout Error */ | ||
| 309 | #define MALESR_OSE 0x00020000 /* OPB Slave Error */ | ||
| 310 | #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ | ||
| 311 | #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ | ||
| 312 | #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ | ||
| 313 | #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ | ||
| 314 | #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ | ||
| 315 | #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ | ||
| 316 | /* DCRN_MALIER */ | ||
| 317 | #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ | ||
| 318 | #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ | ||
| 319 | #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ | ||
| 320 | #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ | ||
| 321 | #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ | ||
| 322 | /* DCRN_MALTXEOBISR */ | ||
| 323 | #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ | ||
| 324 | #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ | ||
| 325 | |||
| 326 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) | ||
| 327 | /* 440SP/440SPe PLB Arbiter DCRs */ | ||
| 328 | #define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ | ||
| 329 | #define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ | ||
| 330 | |||
| 331 | #define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */ | ||
| 332 | #define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */ | ||
| 333 | #define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */ | ||
| 334 | #define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */ | ||
| 335 | #define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */ | ||
| 336 | |||
| 337 | #define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */ | ||
| 338 | #define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */ | ||
| 339 | #define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */ | ||
| 340 | #define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */ | ||
| 341 | #define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */ | ||
| 342 | #else | ||
| 343 | /* 440GP/GX PLB Arbiter DCRs */ | ||
| 344 | #define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ | ||
| 345 | #define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ | ||
| 346 | #define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ | ||
| 347 | #define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ | ||
| 348 | #define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ | ||
| 349 | #define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ | ||
| 350 | #endif | ||
| 351 | |||
| 352 | /* 440GP/GX PLB to OPB bridge DCRs */ | ||
| 353 | #define DCRN_POB0_BESR0 0x090 | ||
| 354 | #define DCRN_POB0_BESR1 0x094 | ||
| 355 | #define DCRN_POB0_BEARL 0x092 | ||
| 356 | #define DCRN_POB0_BEARH 0x093 | ||
| 357 | |||
| 358 | /* 440GP/GX OPB to PLB bridge DCRs */ | ||
| 359 | #define DCRN_OPB0_BSTAT 0x0a9 | ||
| 360 | #define DCRN_OPB0_BEARL 0x0aa | ||
| 361 | #define DCRN_OPB0_BEARH 0x0ab | ||
| 362 | |||
| 363 | /* 440GP Clock, PM, chip control */ | ||
| 364 | #define DCRN_CPC0_SR 0x0b0 | ||
| 365 | #define DCRN_CPC0_ER 0x0b1 | ||
| 366 | #define DCRN_CPC0_FR 0x0b2 | ||
| 367 | #define DCRN_CPC0_SYS0 0x0e0 | ||
| 368 | #define DCRN_CPC0_SYS1 0x0e1 | ||
| 369 | #define DCRN_CPC0_CUST0 0x0e2 | ||
| 370 | #define DCRN_CPC0_CUST1 0x0e3 | ||
| 371 | #define DCRN_CPC0_STRP0 0x0e4 | ||
| 372 | #define DCRN_CPC0_STRP1 0x0e5 | ||
| 373 | #define DCRN_CPC0_STRP2 0x0e6 | ||
| 374 | #define DCRN_CPC0_STRP3 0x0e7 | ||
| 375 | #define DCRN_CPC0_GPIO 0x0e8 | ||
| 376 | #define DCRN_CPC0_PLB 0x0e9 | ||
| 377 | #define DCRN_CPC0_CR1 0x0ea | ||
| 378 | #define DCRN_CPC0_CR0 0x0eb | ||
| 379 | #define DCRN_CPC0_MIRQ0 0x0ec | ||
| 380 | #define DCRN_CPC0_MIRQ1 0x0ed | ||
| 381 | #define DCRN_CPC0_JTAGID 0x0ef | ||
| 382 | |||
| 383 | /* 440GP DMA controller DCRs */ | ||
| 384 | #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */ | ||
| 385 | #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */ | ||
| 386 | #define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */ | ||
| 387 | #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */ | ||
| 388 | #define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */ | ||
| 389 | #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */ | ||
| 390 | #define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */ | ||
| 391 | #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */ | ||
| 392 | |||
| 393 | #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */ | ||
| 394 | #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */ | ||
| 395 | #define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */ | ||
| 396 | #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */ | ||
| 397 | #define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */ | ||
| 398 | #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */ | ||
| 399 | #define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */ | ||
| 400 | #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */ | ||
| 401 | |||
| 402 | #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */ | ||
| 403 | #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */ | ||
| 404 | #define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */ | ||
| 405 | #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */ | ||
| 406 | #define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */ | ||
| 407 | #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */ | ||
| 408 | #define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */ | ||
| 409 | #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */ | ||
| 410 | |||
| 411 | #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */ | ||
| 412 | #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */ | ||
| 413 | #define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */ | ||
| 414 | #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */ | ||
| 415 | #define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */ | ||
| 416 | #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */ | ||
| 417 | #define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */ | ||
| 418 | #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */ | ||
| 419 | |||
| 420 | #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ | ||
| 421 | #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ | ||
| 422 | #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ | ||
| 423 | #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ | ||
| 424 | |||
| 425 | /* 440GP/440GX SDRAM controller DCRs */ | ||
| 426 | #define DCRN_SDRAM0_CFGADDR 0x010 | ||
| 427 | #define DCRN_SDRAM0_CFGDATA 0x011 | ||
| 428 | |||
| 429 | #define SDRAM0_B0CR 0x40 | ||
| 430 | #define SDRAM0_B1CR 0x44 | ||
| 431 | #define SDRAM0_B2CR 0x48 | ||
| 432 | #define SDRAM0_B3CR 0x4c | ||
| 433 | |||
| 434 | #define SDRAM_CONFIG_BANK_ENABLE 0x00000001 | ||
| 435 | #define SDRAM_CONFIG_SIZE_MASK 0x000e0000 | ||
| 436 | #define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17) | ||
| 437 | #define SDRAM_CONFIG_SIZE_8M 0x00000001 | ||
| 438 | #define SDRAM_CONFIG_SIZE_16M 0x00000002 | ||
| 439 | #define SDRAM_CONFIG_SIZE_32M 0x00000003 | ||
| 440 | #define SDRAM_CONFIG_SIZE_64M 0x00000004 | ||
| 441 | #define SDRAM_CONFIG_SIZE_128M 0x00000005 | ||
| 442 | #define SDRAM_CONFIG_SIZE_256M 0x00000006 | ||
| 443 | #define SDRAM_CONFIG_SIZE_512M 0x00000007 | ||
| 444 | #define PPC44x_MEM_SIZE_8M 0x00800000 | ||
| 445 | #define PPC44x_MEM_SIZE_16M 0x01000000 | ||
| 446 | #define PPC44x_MEM_SIZE_32M 0x02000000 | ||
| 447 | #define PPC44x_MEM_SIZE_64M 0x04000000 | ||
| 448 | #define PPC44x_MEM_SIZE_128M 0x08000000 | ||
| 449 | #define PPC44x_MEM_SIZE_256M 0x10000000 | ||
| 450 | #define PPC44x_MEM_SIZE_512M 0x20000000 | ||
| 451 | #define PPC44x_MEM_SIZE_1G 0x40000000 | ||
| 452 | #define PPC44x_MEM_SIZE_2G 0x80000000 | ||
| 453 | |||
| 454 | /* 440SP/440SPe memory controller DCRs */ | ||
| 455 | #define DCRN_MQ0_BS0BAS 0x40 | ||
| 456 | #if defined(CONFIG_440SP) | ||
| 457 | #define MQ0_NUM_BANKS 2 | ||
| 458 | #elif defined(CONFIG_440SPE) | ||
| 459 | #define MQ0_NUM_BANKS 4 | ||
| 460 | #endif | ||
| 461 | |||
| 462 | #define MQ0_CONFIG_SIZE_MASK 0x0000fff0 | ||
| 463 | #define MQ0_CONFIG_SIZE_8M 0x0000ffc0 | ||
| 464 | #define MQ0_CONFIG_SIZE_16M 0x0000ff80 | ||
| 465 | #define MQ0_CONFIG_SIZE_32M 0x0000ff00 | ||
| 466 | #define MQ0_CONFIG_SIZE_64M 0x0000fe00 | ||
| 467 | #define MQ0_CONFIG_SIZE_128M 0x0000fc00 | ||
| 468 | #define MQ0_CONFIG_SIZE_256M 0x0000f800 | ||
| 469 | #define MQ0_CONFIG_SIZE_512M 0x0000f000 | ||
| 470 | #define MQ0_CONFIG_SIZE_1G 0x0000e000 | ||
| 471 | #define MQ0_CONFIG_SIZE_2G 0x0000c000 | ||
| 472 | #define MQ0_CONFIG_SIZE_4G 0x00008000 | ||
| 473 | |||
| 474 | /* Internal SRAM Controller 440GX/440SP/440SPe */ | ||
| 475 | #define DCRN_SRAM0_BASE 0x000 | ||
| 476 | |||
| 477 | #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) | ||
| 478 | #define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021) | ||
| 479 | #define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022) | ||
| 480 | #define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023) | ||
| 481 | #define SRAM_SBCR_BAS0 0x80000000 | ||
| 482 | #define SRAM_SBCR_BAS1 0x80010000 | ||
| 483 | #define SRAM_SBCR_BAS2 0x80020000 | ||
| 484 | #define SRAM_SBCR_BAS3 0x80030000 | ||
| 485 | #define SRAM_SBCR_BU_MASK 0x00000180 | ||
| 486 | #define SRAM_SBCR_BS_64KB 0x00000800 | ||
| 487 | #define SRAM_SBCR_BU_RO 0x00000080 | ||
| 488 | #define SRAM_SBCR_BU_RW 0x00000180 | ||
| 489 | #define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024) | ||
| 490 | #define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025) | ||
| 491 | #define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026) | ||
| 492 | #define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027) | ||
| 493 | #define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028) | ||
| 494 | #define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029) | ||
| 495 | #define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) | ||
| 496 | #define SRAM_DPC_ENABLE 0x80000000 | ||
| 497 | |||
| 498 | /* L2 Cache Controller 440GX/440SP/440SPe */ | ||
| 499 | #define DCRN_L2C0_CFG 0x030 | ||
| 500 | #define L2C_CFG_L2M 0x80000000 | ||
| 501 | #define L2C_CFG_ICU 0x40000000 | ||
| 502 | #define L2C_CFG_DCU 0x20000000 | ||
| 503 | #define L2C_CFG_DCW_MASK 0x1e000000 | ||
| 504 | #define L2C_CFG_TPC 0x01000000 | ||
| 505 | #define L2C_CFG_CPC 0x00800000 | ||
| 506 | #define L2C_CFG_FRAN 0x00200000 | ||
| 507 | #define L2C_CFG_SS_MASK 0x00180000 | ||
| 508 | #define L2C_CFG_SS_256 0x00000000 | ||
| 509 | #define L2C_CFG_CPIM 0x00040000 | ||
| 510 | #define L2C_CFG_TPIM 0x00020000 | ||
| 511 | #define L2C_CFG_LIM 0x00010000 | ||
| 512 | #define L2C_CFG_PMUX_MASK 0x00007000 | ||
| 513 | #define L2C_CFG_PMUX_SNP 0x00000000 | ||
| 514 | #define L2C_CFG_PMUX_IF 0x00001000 | ||
| 515 | #define L2C_CFG_PMUX_DF 0x00002000 | ||
| 516 | #define L2C_CFG_PMUX_DS 0x00003000 | ||
| 517 | #define L2C_CFG_PMIM 0x00000800 | ||
| 518 | #define L2C_CFG_TPEI 0x00000400 | ||
| 519 | #define L2C_CFG_CPEI 0x00000200 | ||
| 520 | #define L2C_CFG_NAM 0x00000100 | ||
| 521 | #define L2C_CFG_SMCM 0x00000080 | ||
| 522 | #define L2C_CFG_NBRM 0x00000040 | ||
| 523 | #define DCRN_L2C0_CMD 0x031 | ||
| 524 | #define L2C_CMD_CLR 0x80000000 | ||
| 525 | #define L2C_CMD_DIAG 0x40000000 | ||
| 526 | #define L2C_CMD_INV 0x20000000 | ||
| 527 | #define L2C_CMD_CCP 0x10000000 | ||
| 528 | #define L2C_CMD_CTE 0x08000000 | ||
| 529 | #define L2C_CMD_STRC 0x04000000 | ||
| 530 | #define L2C_CMD_STPC 0x02000000 | ||
| 531 | #define L2C_CMD_RPMC 0x01000000 | ||
| 532 | #define L2C_CMD_HCC 0x00800000 | ||
| 533 | #define DCRN_L2C0_ADDR 0x032 | ||
| 534 | #define DCRN_L2C0_DATA 0x033 | ||
| 535 | #define DCRN_L2C0_SR 0x034 | ||
| 536 | #define L2C_SR_CC 0x80000000 | ||
| 537 | #define L2C_SR_CPE 0x40000000 | ||
| 538 | #define L2C_SR_TPE 0x20000000 | ||
| 539 | #define L2C_SR_LRU 0x10000000 | ||
| 540 | #define L2C_SR_PCS 0x08000000 | ||
| 541 | #define DCRN_L2C0_REVID 0x035 | ||
| 542 | #define DCRN_L2C0_SNP0 0x036 | ||
| 543 | #define DCRN_L2C0_SNP1 0x037 | ||
| 544 | #define L2C_SNP_BA_MASK 0xffff0000 | ||
| 545 | #define L2C_SNP_SSR_MASK 0x0000f000 | ||
| 546 | #define L2C_SNP_SSR_32G 0x0000f000 | ||
| 547 | #define L2C_SNP_ESR 0x00000800 | ||
| 548 | |||
| 549 | /* | ||
| 550 | * PCI-X definitions | ||
| 551 | */ | ||
| 552 | #define PCIX0_CFGA 0x0ec00000UL | ||
| 553 | #define PCIX1_CFGA 0x1ec00000UL | ||
| 554 | #define PCIX2_CFGA 0x2ec00000UL | ||
| 555 | #define PCIX0_CFGD 0x0ec00004UL | ||
| 556 | #define PCIX1_CFGD 0x1ec00004UL | ||
| 557 | #define PCIX2_CFGD 0x2ec00004UL | ||
| 558 | |||
| 559 | #define PCIX0_IO_BASE 0x0000000908000000ULL | ||
| 560 | #define PCIX1_IO_BASE 0x0000000908000000ULL | ||
| 561 | #define PCIX2_IO_BASE 0x0000000908000000ULL | ||
| 562 | #define PCIX_IO_SIZE 0x00010000 | ||
| 563 | |||
| 564 | #ifdef CONFIG_440SP | ||
| 565 | #define PCIX0_REG_BASE 0x000000090ec80000ULL | ||
| 566 | #else | ||
| 567 | #define PCIX0_REG_BASE 0x000000020ec80000ULL | ||
| 568 | #endif | ||
| 569 | #define PCIX_REG_OFFSET 0x10000000 | ||
| 570 | #define PCIX_REG_SIZE 0x200 | ||
| 571 | |||
| 572 | #define PCIX0_VENDID 0x000 | ||
| 573 | #define PCIX0_DEVID 0x002 | ||
| 574 | #define PCIX0_COMMAND 0x004 | ||
| 575 | #define PCIX0_STATUS 0x006 | ||
| 576 | #define PCIX0_REVID 0x008 | ||
| 577 | #define PCIX0_CLS 0x009 | ||
| 578 | #define PCIX0_CACHELS 0x00c | ||
| 579 | #define PCIX0_LATTIM 0x00d | ||
| 580 | #define PCIX0_HDTYPE 0x00e | ||
| 581 | #define PCIX0_BIST 0x00f | ||
| 582 | #define PCIX0_BAR0L 0x010 | ||
| 583 | #define PCIX0_BAR0H 0x014 | ||
| 584 | #define PCIX0_BAR1 0x018 | ||
| 585 | #define PCIX0_BAR2L 0x01c | ||
| 586 | #define PCIX0_BAR2H 0x020 | ||
| 587 | #define PCIX0_BAR3 0x024 | ||
| 588 | #define PCIX0_CISPTR 0x028 | ||
| 589 | #define PCIX0_SBSYSVID 0x02c | ||
| 590 | #define PCIX0_SBSYSID 0x02e | ||
| 591 | #define PCIX0_EROMBA 0x030 | ||
| 592 | #define PCIX0_CAP 0x034 | ||
| 593 | #define PCIX0_RES0 0x035 | ||
| 594 | #define PCIX0_RES1 0x036 | ||
| 595 | #define PCIX0_RES2 0x038 | ||
| 596 | #define PCIX0_INTLN 0x03c | ||
| 597 | #define PCIX0_INTPN 0x03d | ||
| 598 | #define PCIX0_MINGNT 0x03e | ||
| 599 | #define PCIX0_MAXLTNCY 0x03f | ||
| 600 | #define PCIX0_BRDGOPT1 0x040 | ||
| 601 | #define PCIX0_BRDGOPT2 0x044 | ||
| 602 | #define PCIX0_ERREN 0x050 | ||
| 603 | #define PCIX0_ERRSTS 0x054 | ||
| 604 | #define PCIX0_PLBBESR 0x058 | ||
| 605 | #define PCIX0_PLBBEARL 0x05c | ||
| 606 | #define PCIX0_PLBBEARH 0x060 | ||
| 607 | #define PCIX0_POM0LAL 0x068 | ||
| 608 | #define PCIX0_POM0LAH 0x06c | ||
| 609 | #define PCIX0_POM0SA 0x070 | ||
| 610 | #define PCIX0_POM0PCIAL 0x074 | ||
| 611 | #define PCIX0_POM0PCIAH 0x078 | ||
| 612 | #define PCIX0_POM1LAL 0x07c | ||
| 613 | #define PCIX0_POM1LAH 0x080 | ||
| 614 | #define PCIX0_POM1SA 0x084 | ||
| 615 | #define PCIX0_POM1PCIAL 0x088 | ||
| 616 | #define PCIX0_POM1PCIAH 0x08c | ||
| 617 | #define PCIX0_POM2SA 0x090 | ||
| 618 | #define PCIX0_PIM0SAL 0x098 | ||
| 619 | #define PCIX0_PIM0SA PCIX0_PIM0SAL | ||
| 620 | #define PCIX0_PIM0LAL 0x09c | ||
| 621 | #define PCIX0_PIM0LAH 0x0a0 | ||
| 622 | #define PCIX0_PIM1SA 0x0a4 | ||
| 623 | #define PCIX0_PIM1LAL 0x0a8 | ||
| 624 | #define PCIX0_PIM1LAH 0x0ac | ||
| 625 | #define PCIX0_PIM2SAL 0x0b0 | ||
| 626 | #define PCIX0_PIM2SA PCIX0_PIM2SAL | ||
| 627 | #define PCIX0_PIM2LAL 0x0b4 | ||
| 628 | #define PCIX0_PIM2LAH 0x0b8 | ||
| 629 | #define PCIX0_OMCAPID 0x0c0 | ||
| 630 | #define PCIX0_OMNIPTR 0x0c1 | ||
| 631 | #define PCIX0_OMMC 0x0c2 | ||
| 632 | #define PCIX0_OMMA 0x0c4 | ||
| 633 | #define PCIX0_OMMUA 0x0c8 | ||
| 634 | #define PCIX0_OMMDATA 0x0cc | ||
| 635 | #define PCIX0_OMMEOI 0x0ce | ||
| 636 | #define PCIX0_PMCAPID 0x0d0 | ||
| 637 | #define PCIX0_PMNIPTR 0x0d1 | ||
| 638 | #define PCIX0_PMC 0x0d2 | ||
| 639 | #define PCIX0_PMCSR 0x0d4 | ||
| 640 | #define PCIX0_PMCSRBSE 0x0d6 | ||
| 641 | #define PCIX0_PMDATA 0x0d7 | ||
| 642 | #define PCIX0_PMSCRR 0x0d8 | ||
| 643 | #define PCIX0_CAPID 0x0dc | ||
| 644 | #define PCIX0_NIPTR 0x0dd | ||
| 645 | #define PCIX0_CMD 0x0de | ||
| 646 | #define PCIX0_STS 0x0e0 | ||
| 647 | #define PCIX0_IDR 0x0e4 | ||
| 648 | #define PCIX0_CID 0x0e8 | ||
| 649 | #define PCIX0_RID 0x0ec | ||
| 650 | #define PCIX0_PIM0SAH 0x0f8 | ||
| 651 | #define PCIX0_PIM2SAH 0x0fc | ||
| 652 | #define PCIX0_MSGIL 0x100 | ||
| 653 | #define PCIX0_MSGIH 0x104 | ||
| 654 | #define PCIX0_MSGOL 0x108 | ||
| 655 | #define PCIX0_MSGOH 0x10c | ||
| 656 | #define PCIX0_IM 0x1f8 | ||
| 657 | |||
| 658 | #define IIC_OWN 0x55 | ||
| 659 | #define IIC_CLOCK 50 | ||
| 660 | |||
| 661 | #undef NR_UICS | ||
| 662 | #if defined(CONFIG_440GX) | ||
| 663 | #define NR_UICS 3 | ||
| 664 | #elif defined(CONFIG_440SPE) | ||
| 665 | #define NR_UICS 4 | ||
| 666 | #else | ||
| 667 | #define NR_UICS 2 | ||
| 668 | #endif | ||
| 669 | |||
| 670 | #include <asm/ibm4xx.h> | ||
| 671 | |||
| 672 | #endif /* __ASSEMBLY__ */ | ||
| 673 | #endif /* __ASM_IBM44x_H__ */ | ||
| 674 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h deleted file mode 100644 index ed6891af05d3..000000000000 --- a/include/asm-ppc/ibm4xx.h +++ /dev/null | |||
| @@ -1,124 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | ||
| 4 | * | ||
| 5 | * Module name: ibm4xx.h | ||
| 6 | * | ||
| 7 | * Description: | ||
| 8 | * A generic include file which pulls in appropriate include files | ||
| 9 | * for specific board types based on configuration settings. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifdef __KERNEL__ | ||
| 14 | #ifndef __ASM_IBM4XX_H__ | ||
| 15 | #define __ASM_IBM4XX_H__ | ||
| 16 | |||
| 17 | #include <asm/types.h> | ||
| 18 | #include <asm/dcr.h> | ||
| 19 | |||
| 20 | #ifdef CONFIG_40x | ||
| 21 | |||
| 22 | #if defined(CONFIG_BUBINGA) | ||
| 23 | #include <platforms/4xx/bubinga.h> | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #if defined(CONFIG_CPCI405) | ||
| 27 | #include <platforms/4xx/cpci405.h> | ||
| 28 | #endif | ||
| 29 | |||
| 30 | #if defined(CONFIG_EP405) | ||
| 31 | #include <platforms/4xx/ep405.h> | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #if defined(CONFIG_REDWOOD_5) | ||
| 35 | #include <platforms/4xx/redwood5.h> | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #if defined(CONFIG_REDWOOD_6) | ||
| 39 | #include <platforms/4xx/redwood6.h> | ||
| 40 | #endif | ||
| 41 | |||
| 42 | #if defined(CONFIG_SYCAMORE) | ||
| 43 | #include <platforms/4xx/sycamore.h> | ||
| 44 | #endif | ||
| 45 | |||
| 46 | #if defined(CONFIG_WALNUT) | ||
| 47 | #include <platforms/4xx/walnut.h> | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #if defined(CONFIG_XILINX_VIRTEX) | ||
| 51 | #include <platforms/4xx/virtex.h> | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #ifndef __ASSEMBLY__ | ||
| 55 | |||
| 56 | #ifdef CONFIG_40x | ||
| 57 | /* | ||
| 58 | * The "residual" board information structure the boot loader passes | ||
| 59 | * into the kernel. | ||
| 60 | */ | ||
| 61 | extern bd_t __res; | ||
| 62 | #endif | ||
| 63 | |||
| 64 | void ppc4xx_setup_arch(void); | ||
| 65 | void ppc4xx_map_io(void); | ||
| 66 | void ppc4xx_init_IRQ(void); | ||
| 67 | void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, | ||
| 68 | unsigned long r6, unsigned long r7); | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef PPC4xx_MACHINE_NAME | ||
| 72 | #define PPC4xx_MACHINE_NAME "Unidentified 4xx class" | ||
| 73 | #endif | ||
| 74 | |||
| 75 | |||
| 76 | /* IO_BASE is for PCI I/O. | ||
| 77 | * ISA not supported, just here to resolve copilation. | ||
| 78 | */ | ||
| 79 | |||
| 80 | #ifndef _IO_BASE | ||
| 81 | #define _IO_BASE 0xe8000000 /* The PCI address window */ | ||
| 82 | #define _ISA_MEM_BASE 0 | ||
| 83 | #define PCI_DRAM_OFFSET 0 | ||
| 84 | #endif | ||
| 85 | |||
| 86 | #elif defined(CONFIG_44x) | ||
| 87 | |||
| 88 | #if defined(CONFIG_BAMBOO) | ||
| 89 | #include <platforms/4xx/bamboo.h> | ||
| 90 | #endif | ||
| 91 | |||
| 92 | #if defined(CONFIG_EBONY) | ||
| 93 | #include <platforms/4xx/ebony.h> | ||
| 94 | #endif | ||
| 95 | |||
| 96 | #if defined(CONFIG_LUAN) | ||
| 97 | #include <platforms/4xx/luan.h> | ||
| 98 | #endif | ||
| 99 | |||
| 100 | #if defined(CONFIG_YUCCA) | ||
| 101 | #include <platforms/4xx/yucca.h> | ||
| 102 | #endif | ||
| 103 | |||
| 104 | #if defined(CONFIG_OCOTEA) | ||
| 105 | #include <platforms/4xx/ocotea.h> | ||
| 106 | #endif | ||
| 107 | |||
| 108 | #if defined(CONFIG_TAISHAN) | ||
| 109 | #include <platforms/4xx/taishan.h> | ||
| 110 | #endif | ||
| 111 | |||
| 112 | #ifndef __ASSEMBLY__ | ||
| 113 | #ifdef CONFIG_40x | ||
| 114 | /* | ||
| 115 | * The "residual" board information structure the boot loader passes | ||
| 116 | * into the kernel. | ||
| 117 | */ | ||
| 118 | extern bd_t __res; | ||
| 119 | #endif | ||
| 120 | #endif | ||
| 121 | #endif /* CONFIG_40x */ | ||
| 122 | |||
| 123 | #endif /* __ASM_IBM4XX_H__ */ | ||
| 124 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h deleted file mode 100644 index ddce616f765a..000000000000 --- a/include/asm-ppc/ibm_ocp.h +++ /dev/null | |||
| @@ -1,204 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * ibm_ocp.h | ||
| 3 | * | ||
| 4 | * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) | ||
| 5 | * Mipsys - France | ||
| 6 | * | ||
| 7 | * Derived from work (c) Armin Kuster akuster@pacbell.net | ||
| 8 | * | ||
| 9 | * Additional support and port to 2.6 LDM/sysfs by | ||
| 10 | * Matt Porter <mporter@kernel.crashing.org> | ||
| 11 | * Copyright 2003-2004 MontaVista Software, Inc. | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify it | ||
| 14 | * under the terms of the GNU General Public License as published by the | ||
| 15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 16 | * option) any later version. | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | #ifdef __KERNEL__ | ||
| 20 | #ifndef __IBM_OCP_H__ | ||
| 21 | #define __IBM_OCP_H__ | ||
| 22 | |||
| 23 | #include <asm/types.h> | ||
| 24 | |||
| 25 | /* | ||
| 26 | * IBM 4xx OCP system information | ||
| 27 | */ | ||
| 28 | struct ocp_sys_info_data { | ||
| 29 | int opb_bus_freq; /* OPB Bus Frequency (Hz) */ | ||
| 30 | int ebc_bus_freq; /* EBC Bus Frequency (Hz) */ | ||
| 31 | }; | ||
| 32 | |||
| 33 | extern struct ocp_sys_info_data ocp_sys_info; | ||
| 34 | |||
| 35 | /* | ||
| 36 | * EMAC additional data and sysfs support | ||
| 37 | * | ||
| 38 | * Note about mdio_idx: When you have a zmii, it's usually | ||
| 39 | * not necessary, it covers the case of the 405EP which has | ||
| 40 | * the MDIO lines on EMAC0 only | ||
| 41 | * | ||
| 42 | * Note about phy_map: Per EMAC map of PHY ids which should | ||
| 43 | * be probed by emac_probe. Different EMACs can have | ||
| 44 | * overlapping maps. | ||
| 45 | * | ||
| 46 | * Note, this map uses inverse logic for bits: | ||
| 47 | * 0 - id should be probed | ||
| 48 | * 1 - id should be ignored | ||
| 49 | * | ||
| 50 | * Default value of 0x00000000 - will result in usual | ||
| 51 | * auto-detection logic. | ||
| 52 | * | ||
| 53 | */ | ||
| 54 | |||
| 55 | struct ocp_func_emac_data { | ||
| 56 | int rgmii_idx; /* RGMII device index or -1 */ | ||
| 57 | int rgmii_mux; /* RGMII input of this EMAC */ | ||
| 58 | int zmii_idx; /* ZMII device index or -1 */ | ||
| 59 | int zmii_mux; /* ZMII input of this EMAC */ | ||
| 60 | int mal_idx; /* MAL device index */ | ||
| 61 | int mal_rx_chan; /* MAL rx channel number */ | ||
| 62 | int mal_tx_chan; /* MAL tx channel number */ | ||
| 63 | int wol_irq; /* WOL interrupt */ | ||
| 64 | int mdio_idx; /* EMAC idx of MDIO master or -1 */ | ||
| 65 | int tah_idx; /* TAH device index or -1 */ | ||
| 66 | int phy_mode; /* PHY type or configurable mode */ | ||
| 67 | u8 mac_addr[6]; /* EMAC mac address */ | ||
| 68 | u32 phy_map; /* EMAC phy map */ | ||
| 69 | u32 phy_feat_exc; /* Excluded PHY features */ | ||
| 70 | }; | ||
| 71 | |||
| 72 | /* Sysfs support */ | ||
| 73 | #define OCP_SYSFS_EMAC_DATA() \ | ||
| 74 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \ | ||
| 75 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \ | ||
| 76 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \ | ||
| 77 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \ | ||
| 78 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \ | ||
| 79 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \ | ||
| 80 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \ | ||
| 81 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \ | ||
| 82 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \ | ||
| 83 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \ | ||
| 84 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \ | ||
| 85 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \ | ||
| 86 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\ | ||
| 87 | \ | ||
| 88 | void ocp_show_emac_data(struct device *dev) \ | ||
| 89 | { \ | ||
| 90 | device_create_file(dev, &dev_attr_emac_rgmii_idx); \ | ||
| 91 | device_create_file(dev, &dev_attr_emac_rgmii_mux); \ | ||
| 92 | device_create_file(dev, &dev_attr_emac_zmii_idx); \ | ||
| 93 | device_create_file(dev, &dev_attr_emac_zmii_mux); \ | ||
| 94 | device_create_file(dev, &dev_attr_emac_mal_idx); \ | ||
| 95 | device_create_file(dev, &dev_attr_emac_mal_rx_chan); \ | ||
| 96 | device_create_file(dev, &dev_attr_emac_mal_tx_chan); \ | ||
| 97 | device_create_file(dev, &dev_attr_emac_wol_irq); \ | ||
| 98 | device_create_file(dev, &dev_attr_emac_mdio_idx); \ | ||
| 99 | device_create_file(dev, &dev_attr_emac_tah_idx); \ | ||
| 100 | device_create_file(dev, &dev_attr_emac_phy_mode); \ | ||
| 101 | device_create_file(dev, &dev_attr_emac_phy_map); \ | ||
| 102 | device_create_file(dev, &dev_attr_emac_phy_feat_exc); \ | ||
| 103 | } | ||
| 104 | |||
| 105 | /* | ||
| 106 | * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY) | ||
| 107 | */ | ||
| 108 | #define PHY_MODE_NA 0 | ||
| 109 | #define PHY_MODE_MII 1 | ||
| 110 | #define PHY_MODE_RMII 2 | ||
| 111 | #define PHY_MODE_SMII 3 | ||
| 112 | #define PHY_MODE_RGMII 4 | ||
| 113 | #define PHY_MODE_TBI 5 | ||
| 114 | #define PHY_MODE_GMII 6 | ||
| 115 | #define PHY_MODE_RTBI 7 | ||
| 116 | #define PHY_MODE_SGMII 8 | ||
| 117 | |||
| 118 | #ifdef CONFIG_40x | ||
| 119 | /* | ||
| 120 | * Helper function to copy MAC addresses from the bd_t to OCP EMAC | ||
| 121 | * additions. | ||
| 122 | * | ||
| 123 | * The range of EMAC indices (inclusive) to be copied are the arguments. | ||
| 124 | */ | ||
| 125 | static inline void ibm_ocp_set_emac(int start, int end) | ||
| 126 | { | ||
| 127 | int i; | ||
| 128 | struct ocp_def *def; | ||
| 129 | |||
| 130 | /* Copy MAC addresses to EMAC additions */ | ||
| 131 | for (i=start; i<=end; i++) { | ||
| 132 | def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); | ||
| 133 | if (i == 0) | ||
| 134 | memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, | ||
| 135 | __res.bi_enetaddr, 6); | ||
| 136 | #if defined(CONFIG_405EP) || defined(CONFIG_44x) | ||
| 137 | else if (i == 1) | ||
| 138 | memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, | ||
| 139 | __res.bi_enet1addr, 6); | ||
| 140 | #endif | ||
| 141 | #if defined(CONFIG_440GX) | ||
| 142 | else if (i == 2) | ||
| 143 | memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, | ||
| 144 | __res.bi_enet2addr, 6); | ||
| 145 | else if (i == 3) | ||
| 146 | memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, | ||
| 147 | __res.bi_enet3addr, 6); | ||
| 148 | #endif | ||
| 149 | } | ||
| 150 | } | ||
| 151 | #endif | ||
| 152 | |||
| 153 | /* | ||
| 154 | * MAL additional data and sysfs support | ||
| 155 | */ | ||
| 156 | struct ocp_func_mal_data { | ||
| 157 | int num_tx_chans; /* Number of TX channels */ | ||
| 158 | int num_rx_chans; /* Number of RX channels */ | ||
| 159 | int txeob_irq; /* TX End Of Buffer IRQ */ | ||
| 160 | int rxeob_irq; /* RX End Of Buffer IRQ */ | ||
| 161 | int txde_irq; /* TX Descriptor Error IRQ */ | ||
| 162 | int rxde_irq; /* RX Descriptor Error IRQ */ | ||
| 163 | int serr_irq; /* MAL System Error IRQ */ | ||
| 164 | int dcr_base; /* MALx_CFG DCR number */ | ||
| 165 | }; | ||
| 166 | |||
| 167 | #define OCP_SYSFS_MAL_DATA() \ | ||
| 168 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans) \ | ||
| 169 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans) \ | ||
| 170 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq) \ | ||
| 171 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \ | ||
| 172 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \ | ||
| 173 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \ | ||
| 174 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \ | ||
| 175 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \ | ||
| 176 | \ | ||
| 177 | void ocp_show_mal_data(struct device *dev) \ | ||
| 178 | { \ | ||
| 179 | device_create_file(dev, &dev_attr_mal_num_tx_chans); \ | ||
| 180 | device_create_file(dev, &dev_attr_mal_num_rx_chans); \ | ||
| 181 | device_create_file(dev, &dev_attr_mal_txeob_irq); \ | ||
| 182 | device_create_file(dev, &dev_attr_mal_rxeob_irq); \ | ||
| 183 | device_create_file(dev, &dev_attr_mal_txde_irq); \ | ||
| 184 | device_create_file(dev, &dev_attr_mal_rxde_irq); \ | ||
| 185 | device_create_file(dev, &dev_attr_mal_serr_irq); \ | ||
| 186 | device_create_file(dev, &dev_attr_mal_dcr_base); \ | ||
| 187 | } | ||
| 188 | |||
| 189 | /* | ||
| 190 | * IIC additional data and sysfs support | ||
| 191 | */ | ||
| 192 | struct ocp_func_iic_data { | ||
| 193 | int fast_mode; /* IIC fast mode enabled */ | ||
| 194 | }; | ||
| 195 | |||
| 196 | #define OCP_SYSFS_IIC_DATA() \ | ||
| 197 | OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \ | ||
| 198 | \ | ||
| 199 | void ocp_show_iic_data(struct device *dev) \ | ||
| 200 | { \ | ||
| 201 | device_create_file(dev, &dev_attr_iic_fast_mode); \ | ||
| 202 | } | ||
| 203 | #endif /* __IBM_OCP_H__ */ | ||
| 204 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm_ocp_pci.h b/include/asm-ppc/ibm_ocp_pci.h deleted file mode 100644 index a81ab6144358..000000000000 --- a/include/asm-ppc/ibm_ocp_pci.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Author: Armin Kuster <akuster@mvista.com> | ||
| 3 | * | ||
| 4 | * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 5 | * the terms of the GNU General Public License version 2. This program | ||
| 6 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 7 | * or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifdef __KERNEL__ | ||
| 11 | #ifndef __ASM_IBM_OCP_PCI_H__ | ||
| 12 | #define __ASM_IBM_OCP_PCI_H__ | ||
| 13 | |||
| 14 | /* PCI 32 */ | ||
| 15 | |||
| 16 | struct pmm_regs { | ||
| 17 | u32 la; | ||
| 18 | u32 ma; | ||
| 19 | u32 pcila; | ||
| 20 | u32 pciha; | ||
| 21 | }; | ||
| 22 | |||
| 23 | typedef struct pcil0_regs { | ||
| 24 | struct pmm_regs pmm[3]; | ||
| 25 | u32 ptm1ms; | ||
| 26 | u32 ptm1la; | ||
| 27 | u32 ptm2ms; | ||
| 28 | u32 ptm2la; | ||
| 29 | } pci0_t; | ||
| 30 | |||
| 31 | #endif /* __ASM_IBM_OCP_PCI_H__ */ | ||
| 32 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/immap_cpm2.h b/include/asm-ppc/immap_cpm2.h deleted file mode 100644 index 3c23d9cb47a6..000000000000 --- a/include/asm-ppc/immap_cpm2.h +++ /dev/null | |||
| @@ -1,648 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * CPM2 Internal Memory Map | ||
| 3 | * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) | ||
| 4 | * | ||
| 5 | * The Internal Memory Map for devices with CPM2 on them. This | ||
| 6 | * is the superset of all CPM2 devices (8260, 8266, 8280, 8272, | ||
| 7 | * 8560). | ||
| 8 | */ | ||
| 9 | #ifdef __KERNEL__ | ||
| 10 | #ifndef __IMMAP_CPM2__ | ||
| 11 | #define __IMMAP_CPM2__ | ||
| 12 | |||
| 13 | /* System configuration registers. | ||
| 14 | */ | ||
| 15 | typedef struct sys_82xx_conf { | ||
| 16 | u32 sc_siumcr; | ||
| 17 | u32 sc_sypcr; | ||
| 18 | u8 res1[6]; | ||
| 19 | u16 sc_swsr; | ||
| 20 | u8 res2[20]; | ||
| 21 | u32 sc_bcr; | ||
| 22 | u8 sc_ppc_acr; | ||
| 23 | u8 res3[3]; | ||
| 24 | u32 sc_ppc_alrh; | ||
| 25 | u32 sc_ppc_alrl; | ||
| 26 | u8 sc_lcl_acr; | ||
| 27 | u8 res4[3]; | ||
| 28 | u32 sc_lcl_alrh; | ||
| 29 | u32 sc_lcl_alrl; | ||
| 30 | u32 sc_tescr1; | ||
| 31 | u32 sc_tescr2; | ||
| 32 | u32 sc_ltescr1; | ||
| 33 | u32 sc_ltescr2; | ||
| 34 | u32 sc_pdtea; | ||
| 35 | u8 sc_pdtem; | ||
| 36 | u8 res5[3]; | ||
| 37 | u32 sc_ldtea; | ||
| 38 | u8 sc_ldtem; | ||
| 39 | u8 res6[163]; | ||
| 40 | } sysconf_82xx_cpm2_t; | ||
| 41 | |||
| 42 | typedef struct sys_85xx_conf { | ||
| 43 | u32 sc_cear; | ||
| 44 | u16 sc_ceer; | ||
| 45 | u16 sc_cemr; | ||
| 46 | u8 res1[70]; | ||
| 47 | u32 sc_smaer; | ||
| 48 | u8 res2[4]; | ||
| 49 | u32 sc_smevr; | ||
| 50 | u32 sc_smctr; | ||
| 51 | u32 sc_lmaer; | ||
| 52 | u8 res3[4]; | ||
| 53 | u32 sc_lmevr; | ||
| 54 | u32 sc_lmctr; | ||
| 55 | u8 res4[144]; | ||
| 56 | } sysconf_85xx_cpm2_t; | ||
| 57 | |||
| 58 | typedef union sys_conf { | ||
| 59 | sysconf_82xx_cpm2_t siu_82xx; | ||
| 60 | sysconf_85xx_cpm2_t siu_85xx; | ||
| 61 | } sysconf_cpm2_t; | ||
| 62 | |||
| 63 | |||
| 64 | |||
| 65 | /* Memory controller registers. | ||
| 66 | */ | ||
| 67 | typedef struct mem_ctlr { | ||
| 68 | u32 memc_br0; | ||
| 69 | u32 memc_or0; | ||
| 70 | u32 memc_br1; | ||
| 71 | u32 memc_or1; | ||
| 72 | u32 memc_br2; | ||
| 73 | u32 memc_or2; | ||
| 74 | u32 memc_br3; | ||
| 75 | u32 memc_or3; | ||
| 76 | u32 memc_br4; | ||
| 77 | u32 memc_or4; | ||
| 78 | u32 memc_br5; | ||
| 79 | u32 memc_or5; | ||
| 80 | u32 memc_br6; | ||
| 81 | u32 memc_or6; | ||
| 82 | u32 memc_br7; | ||
| 83 | u32 memc_or7; | ||
| 84 | u32 memc_br8; | ||
| 85 | u32 memc_or8; | ||
| 86 | u32 memc_br9; | ||
| 87 | u32 memc_or9; | ||
| 88 | u32 memc_br10; | ||
| 89 | u32 memc_or10; | ||
| 90 | u32 memc_br11; | ||
| 91 | u32 memc_or11; | ||
| 92 | u8 res1[8]; | ||
| 93 | u32 memc_mar; | ||
| 94 | u8 res2[4]; | ||
| 95 | u32 memc_mamr; | ||
| 96 | u32 memc_mbmr; | ||
| 97 | u32 memc_mcmr; | ||
| 98 | u8 res3[8]; | ||
| 99 | u16 memc_mptpr; | ||
| 100 | u8 res4[2]; | ||
| 101 | u32 memc_mdr; | ||
| 102 | u8 res5[4]; | ||
| 103 | u32 memc_psdmr; | ||
| 104 | u32 memc_lsdmr; | ||
| 105 | u8 memc_purt; | ||
| 106 | u8 res6[3]; | ||
| 107 | u8 memc_psrt; | ||
| 108 | u8 res7[3]; | ||
| 109 | u8 memc_lurt; | ||
| 110 | u8 res8[3]; | ||
| 111 | u8 memc_lsrt; | ||
| 112 | u8 res9[3]; | ||
| 113 | u32 memc_immr; | ||
| 114 | u32 memc_pcibr0; | ||
| 115 | u32 memc_pcibr1; | ||
| 116 | u8 res10[16]; | ||
| 117 | u32 memc_pcimsk0; | ||
| 118 | u32 memc_pcimsk1; | ||
| 119 | u8 res11[52]; | ||
| 120 | } memctl_cpm2_t; | ||
| 121 | |||
| 122 | /* System Integration Timers. | ||
| 123 | */ | ||
| 124 | typedef struct sys_int_timers { | ||
| 125 | u8 res1[32]; | ||
| 126 | u16 sit_tmcntsc; | ||
| 127 | u8 res2[2]; | ||
| 128 | u32 sit_tmcnt; | ||
| 129 | u8 res3[4]; | ||
| 130 | u32 sit_tmcntal; | ||
| 131 | u8 res4[16]; | ||
| 132 | u16 sit_piscr; | ||
| 133 | u8 res5[2]; | ||
| 134 | u32 sit_pitc; | ||
| 135 | u32 sit_pitr; | ||
| 136 | u8 res6[94]; | ||
| 137 | u8 res7[390]; | ||
| 138 | } sit_cpm2_t; | ||
| 139 | |||
| 140 | #define PISCR_PIRQ_MASK ((u16)0xff00) | ||
| 141 | #define PISCR_PS ((u16)0x0080) | ||
| 142 | #define PISCR_PIE ((u16)0x0004) | ||
| 143 | #define PISCR_PTF ((u16)0x0002) | ||
| 144 | #define PISCR_PTE ((u16)0x0001) | ||
| 145 | |||
| 146 | /* PCI Controller. | ||
| 147 | */ | ||
| 148 | typedef struct pci_ctlr { | ||
| 149 | u32 pci_omisr; | ||
| 150 | u32 pci_omimr; | ||
| 151 | u8 res1[8]; | ||
| 152 | u32 pci_ifqpr; | ||
| 153 | u32 pci_ofqpr; | ||
| 154 | u8 res2[8]; | ||
| 155 | u32 pci_imr0; | ||
| 156 | u32 pci_imr1; | ||
| 157 | u32 pci_omr0; | ||
| 158 | u32 pci_omr1; | ||
| 159 | u32 pci_odr; | ||
| 160 | u8 res3[4]; | ||
| 161 | u32 pci_idr; | ||
| 162 | u8 res4[20]; | ||
| 163 | u32 pci_imisr; | ||
| 164 | u32 pci_imimr; | ||
| 165 | u8 res5[24]; | ||
| 166 | u32 pci_ifhpr; | ||
| 167 | u8 res6[4]; | ||
| 168 | u32 pci_iftpr; | ||
| 169 | u8 res7[4]; | ||
| 170 | u32 pci_iphpr; | ||
| 171 | u8 res8[4]; | ||
| 172 | u32 pci_iptpr; | ||
| 173 | u8 res9[4]; | ||
| 174 | u32 pci_ofhpr; | ||
| 175 | u8 res10[4]; | ||
| 176 | u32 pci_oftpr; | ||
| 177 | u8 res11[4]; | ||
| 178 | u32 pci_ophpr; | ||
| 179 | u8 res12[4]; | ||
| 180 | u32 pci_optpr; | ||
| 181 | u8 res13[8]; | ||
| 182 | u32 pci_mucr; | ||
| 183 | u8 res14[8]; | ||
| 184 | u32 pci_qbar; | ||
| 185 | u8 res15[12]; | ||
| 186 | u32 pci_dmamr0; | ||
| 187 | u32 pci_dmasr0; | ||
| 188 | u32 pci_dmacdar0; | ||
| 189 | u8 res16[4]; | ||
| 190 | u32 pci_dmasar0; | ||
| 191 | u8 res17[4]; | ||
| 192 | u32 pci_dmadar0; | ||
| 193 | u8 res18[4]; | ||
| 194 | u32 pci_dmabcr0; | ||
| 195 | u32 pci_dmandar0; | ||
| 196 | u8 res19[86]; | ||
| 197 | u32 pci_dmamr1; | ||
| 198 | u32 pci_dmasr1; | ||
| 199 | u32 pci_dmacdar1; | ||
| 200 | u8 res20[4]; | ||
| 201 | u32 pci_dmasar1; | ||
| 202 | u8 res21[4]; | ||
| 203 | u32 pci_dmadar1; | ||
| 204 | u8 res22[4]; | ||
| 205 | u32 pci_dmabcr1; | ||
| 206 | u32 pci_dmandar1; | ||
| 207 | u8 res23[88]; | ||
| 208 | u32 pci_dmamr2; | ||
| 209 | u32 pci_dmasr2; | ||
| 210 | u32 pci_dmacdar2; | ||
| 211 | u8 res24[4]; | ||
| 212 | u32 pci_dmasar2; | ||
| 213 | u8 res25[4]; | ||
| 214 | u32 pci_dmadar2; | ||
| 215 | u8 res26[4]; | ||
| 216 | u32 pci_dmabcr2; | ||
| 217 | u32 pci_dmandar2; | ||
| 218 | u8 res27[88]; | ||
| 219 | u32 pci_dmamr3; | ||
| 220 | u32 pci_dmasr3; | ||
| 221 | u32 pci_dmacdar3; | ||
| 222 | u8 res28[4]; | ||
| 223 | u32 pci_dmasar3; | ||
| 224 | u8 res29[4]; | ||
| 225 | u32 pci_dmadar3; | ||
| 226 | u8 res30[4]; | ||
| 227 | u32 pci_dmabcr3; | ||
| 228 | u32 pci_dmandar3; | ||
| 229 | u8 res31[344]; | ||
| 230 | u32 pci_potar0; | ||
| 231 | u8 res32[4]; | ||
| 232 | u32 pci_pobar0; | ||
| 233 | u8 res33[4]; | ||
| 234 | u32 pci_pocmr0; | ||
| 235 | u8 res34[4]; | ||
| 236 | u32 pci_potar1; | ||
| 237 | u8 res35[4]; | ||
| 238 | u32 pci_pobar1; | ||
| 239 | u8 res36[4]; | ||
| 240 | u32 pci_pocmr1; | ||
| 241 | u8 res37[4]; | ||
| 242 | u32 pci_potar2; | ||
| 243 | u8 res38[4]; | ||
| 244 | u32 pci_pobar2; | ||
| 245 | u8 res39[4]; | ||
| 246 | u32 pci_pocmr2; | ||
| 247 | u8 res40[50]; | ||
| 248 | u32 pci_ptcr; | ||
| 249 | u32 pci_gpcr; | ||
| 250 | u32 pci_gcr; | ||
| 251 | u32 pci_esr; | ||
| 252 | u32 pci_emr; | ||
| 253 | u32 pci_ecr; | ||
| 254 | u32 pci_eacr; | ||
| 255 | u8 res41[4]; | ||
| 256 | u32 pci_edcr; | ||
| 257 | u8 res42[4]; | ||
| 258 | u32 pci_eccr; | ||
| 259 | u8 res43[44]; | ||
| 260 | u32 pci_pitar1; | ||
| 261 | u8 res44[4]; | ||
| 262 | u32 pci_pibar1; | ||
| 263 | u8 res45[4]; | ||
| 264 | u32 pci_picmr1; | ||
| 265 | u8 res46[4]; | ||
| 266 | u32 pci_pitar0; | ||
| 267 | u8 res47[4]; | ||
| 268 | u32 pci_pibar0; | ||
| 269 | u8 res48[4]; | ||
| 270 | u32 pci_picmr0; | ||
| 271 | u8 res49[4]; | ||
| 272 | u32 pci_cfg_addr; | ||
| 273 | u32 pci_cfg_data; | ||
| 274 | u32 pci_int_ack; | ||
| 275 | u8 res50[756]; | ||
| 276 | } pci_cpm2_t; | ||
| 277 | |||
| 278 | /* Interrupt Controller. | ||
| 279 | */ | ||
| 280 | typedef struct interrupt_controller { | ||
| 281 | u16 ic_sicr; | ||
| 282 | u8 res1[2]; | ||
| 283 | u32 ic_sivec; | ||
| 284 | u32 ic_sipnrh; | ||
| 285 | u32 ic_sipnrl; | ||
| 286 | u32 ic_siprr; | ||
| 287 | u32 ic_scprrh; | ||
| 288 | u32 ic_scprrl; | ||
| 289 | u32 ic_simrh; | ||
| 290 | u32 ic_simrl; | ||
| 291 | u32 ic_siexr; | ||
| 292 | u8 res2[88]; | ||
| 293 | } intctl_cpm2_t; | ||
| 294 | |||
| 295 | /* Clocks and Reset. | ||
| 296 | */ | ||
| 297 | typedef struct clk_and_reset { | ||
| 298 | u32 car_sccr; | ||
| 299 | u8 res1[4]; | ||
| 300 | u32 car_scmr; | ||
| 301 | u8 res2[4]; | ||
| 302 | u32 car_rsr; | ||
| 303 | u32 car_rmr; | ||
| 304 | u8 res[104]; | ||
| 305 | } car_cpm2_t; | ||
| 306 | |||
| 307 | /* Input/Output Port control/status registers. | ||
| 308 | * Names consistent with processor manual, although they are different | ||
| 309 | * from the original 8xx names....... | ||
| 310 | */ | ||
| 311 | typedef struct io_port { | ||
| 312 | u32 iop_pdira; | ||
| 313 | u32 iop_ppara; | ||
| 314 | u32 iop_psora; | ||
| 315 | u32 iop_podra; | ||
| 316 | u32 iop_pdata; | ||
| 317 | u8 res1[12]; | ||
| 318 | u32 iop_pdirb; | ||
| 319 | u32 iop_pparb; | ||
| 320 | u32 iop_psorb; | ||
| 321 | u32 iop_podrb; | ||
| 322 | u32 iop_pdatb; | ||
| 323 | u8 res2[12]; | ||
| 324 | u32 iop_pdirc; | ||
| 325 | u32 iop_pparc; | ||
| 326 | u32 iop_psorc; | ||
| 327 | u32 iop_podrc; | ||
| 328 | u32 iop_pdatc; | ||
| 329 | u8 res3[12]; | ||
| 330 | u32 iop_pdird; | ||
| 331 | u32 iop_ppard; | ||
| 332 | u32 iop_psord; | ||
| 333 | u32 iop_podrd; | ||
| 334 | u32 iop_pdatd; | ||
| 335 | u8 res4[12]; | ||
| 336 | } iop_cpm2_t; | ||
| 337 | |||
| 338 | /* Communication Processor Module Timers | ||
| 339 | */ | ||
| 340 | typedef struct cpm_timers { | ||
| 341 | u8 cpmt_tgcr1; | ||
| 342 | u8 res1[3]; | ||
| 343 | u8 cpmt_tgcr2; | ||
| 344 | u8 res2[11]; | ||
| 345 | u16 cpmt_tmr1; | ||
| 346 | u16 cpmt_tmr2; | ||
| 347 | u16 cpmt_trr1; | ||
| 348 | u16 cpmt_trr2; | ||
| 349 | u16 cpmt_tcr1; | ||
| 350 | u16 cpmt_tcr2; | ||
| 351 | u16 cpmt_tcn1; | ||
| 352 | u16 cpmt_tcn2; | ||
| 353 | u16 cpmt_tmr3; | ||
| 354 | u16 cpmt_tmr4; | ||
| 355 | u16 cpmt_trr3; | ||
| 356 | u16 cpmt_trr4; | ||
| 357 | u16 cpmt_tcr3; | ||
| 358 | u16 cpmt_tcr4; | ||
| 359 | u16 cpmt_tcn3; | ||
| 360 | u16 cpmt_tcn4; | ||
| 361 | u16 cpmt_ter1; | ||
| 362 | u16 cpmt_ter2; | ||
| 363 | u16 cpmt_ter3; | ||
| 364 | u16 cpmt_ter4; | ||
| 365 | u8 res3[584]; | ||
| 366 | } cpmtimer_cpm2_t; | ||
| 367 | |||
| 368 | /* DMA control/status registers. | ||
| 369 | */ | ||
| 370 | typedef struct sdma_csr { | ||
| 371 | u8 res0[24]; | ||
| 372 | u8 sdma_sdsr; | ||
| 373 | u8 res1[3]; | ||
| 374 | u8 sdma_sdmr; | ||
| 375 | u8 res2[3]; | ||
| 376 | u8 sdma_idsr1; | ||
| 377 | u8 res3[3]; | ||
| 378 | u8 sdma_idmr1; | ||
| 379 | u8 res4[3]; | ||
| 380 | u8 sdma_idsr2; | ||
| 381 | u8 res5[3]; | ||
| 382 | u8 sdma_idmr2; | ||
| 383 | u8 res6[3]; | ||
| 384 | u8 sdma_idsr3; | ||
| 385 | u8 res7[3]; | ||
| 386 | u8 sdma_idmr3; | ||
| 387 | u8 res8[3]; | ||
| 388 | u8 sdma_idsr4; | ||
| 389 | u8 res9[3]; | ||
| 390 | u8 sdma_idmr4; | ||
| 391 | u8 res10[707]; | ||
| 392 | } sdma_cpm2_t; | ||
| 393 | |||
| 394 | /* Fast controllers | ||
| 395 | */ | ||
| 396 | typedef struct fcc { | ||
| 397 | u32 fcc_gfmr; | ||
| 398 | u32 fcc_fpsmr; | ||
| 399 | u16 fcc_ftodr; | ||
| 400 | u8 res1[2]; | ||
| 401 | u16 fcc_fdsr; | ||
| 402 | u8 res2[2]; | ||
| 403 | u16 fcc_fcce; | ||
| 404 | u8 res3[2]; | ||
| 405 | u16 fcc_fccm; | ||
| 406 | u8 res4[2]; | ||
| 407 | u8 fcc_fccs; | ||
| 408 | u8 res5[3]; | ||
| 409 | u8 fcc_ftirr_phy[4]; | ||
| 410 | } fcc_t; | ||
| 411 | |||
| 412 | /* Fast controllers continued | ||
| 413 | */ | ||
| 414 | typedef struct fcc_c { | ||
| 415 | u32 fcc_firper; | ||
| 416 | u32 fcc_firer; | ||
| 417 | u32 fcc_firsr_hi; | ||
| 418 | u32 fcc_firsr_lo; | ||
| 419 | u8 fcc_gfemr; | ||
| 420 | u8 res1[15]; | ||
| 421 | } fcc_c_t; | ||
| 422 | |||
| 423 | /* TC Layer | ||
| 424 | */ | ||
| 425 | typedef struct tclayer { | ||
| 426 | u16 tc_tcmode; | ||
| 427 | u16 tc_cdsmr; | ||
| 428 | u16 tc_tcer; | ||
| 429 | u16 tc_rcc; | ||
| 430 | u16 tc_tcmr; | ||
| 431 | u16 tc_fcc; | ||
| 432 | u16 tc_ccc; | ||
| 433 | u16 tc_icc; | ||
| 434 | u16 tc_tcc; | ||
| 435 | u16 tc_ecc; | ||
| 436 | u8 res1[12]; | ||
| 437 | } tclayer_t; | ||
| 438 | |||
| 439 | |||
| 440 | /* I2C | ||
| 441 | */ | ||
| 442 | typedef struct i2c { | ||
| 443 | u8 i2c_i2mod; | ||
| 444 | u8 res1[3]; | ||
| 445 | u8 i2c_i2add; | ||
| 446 | u8 res2[3]; | ||
| 447 | u8 i2c_i2brg; | ||
| 448 | u8 res3[3]; | ||
| 449 | u8 i2c_i2com; | ||
| 450 | u8 res4[3]; | ||
| 451 | u8 i2c_i2cer; | ||
| 452 | u8 res5[3]; | ||
| 453 | u8 i2c_i2cmr; | ||
| 454 | u8 res6[331]; | ||
| 455 | } i2c_cpm2_t; | ||
| 456 | |||
| 457 | typedef struct scc { /* Serial communication channels */ | ||
| 458 | u32 scc_gsmrl; | ||
| 459 | u32 scc_gsmrh; | ||
| 460 | u16 scc_psmr; | ||
| 461 | u8 res1[2]; | ||
| 462 | u16 scc_todr; | ||
| 463 | u16 scc_dsr; | ||
| 464 | u16 scc_scce; | ||
| 465 | u8 res2[2]; | ||
| 466 | u16 scc_sccm; | ||
| 467 | u8 res3; | ||
| 468 | u8 scc_sccs; | ||
| 469 | u8 res4[8]; | ||
| 470 | } scc_t; | ||
| 471 | |||
| 472 | typedef struct smc { /* Serial management channels */ | ||
| 473 | u8 res1[2]; | ||
| 474 | u16 smc_smcmr; | ||
| 475 | u8 res2[2]; | ||
| 476 | u8 smc_smce; | ||
| 477 | u8 res3[3]; | ||
| 478 | u8 smc_smcm; | ||
| 479 | u8 res4[5]; | ||
| 480 | } smc_t; | ||
| 481 | |||
| 482 | /* Serial Peripheral Interface. | ||
| 483 | */ | ||
| 484 | typedef struct spi_ctrl { | ||
| 485 | u16 spi_spmode; | ||
| 486 | u8 res1[4]; | ||
| 487 | u8 spi_spie; | ||
| 488 | u8 res2[3]; | ||
| 489 | u8 spi_spim; | ||
| 490 | u8 res3[2]; | ||
| 491 | u8 spi_spcom; | ||
| 492 | u8 res4[82]; | ||
| 493 | } spictl_cpm2_t; | ||
| 494 | |||
| 495 | /* CPM Mux. | ||
| 496 | */ | ||
| 497 | typedef struct cpmux { | ||
| 498 | u8 cmx_si1cr; | ||
| 499 | u8 res1; | ||
| 500 | u8 cmx_si2cr; | ||
| 501 | u8 res2; | ||
| 502 | u32 cmx_fcr; | ||
| 503 | u32 cmx_scr; | ||
| 504 | u8 cmx_smr; | ||
| 505 | u8 res3; | ||
| 506 | u16 cmx_uar; | ||
| 507 | u8 res4[16]; | ||
| 508 | } cpmux_t; | ||
| 509 | |||
| 510 | /* SIRAM control | ||
| 511 | */ | ||
| 512 | typedef struct siram { | ||
| 513 | u16 si_amr; | ||
| 514 | u16 si_bmr; | ||
| 515 | u16 si_cmr; | ||
| 516 | u16 si_dmr; | ||
| 517 | u8 si_gmr; | ||
| 518 | u8 res1; | ||
| 519 | u8 si_cmdr; | ||
| 520 | u8 res2; | ||
| 521 | u8 si_str; | ||
| 522 | u8 res3; | ||
| 523 | u16 si_rsr; | ||
| 524 | } siramctl_t; | ||
| 525 | |||
| 526 | typedef struct mcc { | ||
| 527 | u16 mcc_mcce; | ||
| 528 | u8 res1[2]; | ||
| 529 | u16 mcc_mccm; | ||
| 530 | u8 res2[2]; | ||
| 531 | u8 mcc_mccf; | ||
| 532 | u8 res3[7]; | ||
| 533 | } mcc_t; | ||
| 534 | |||
| 535 | typedef struct comm_proc { | ||
| 536 | u32 cp_cpcr; | ||
| 537 | u32 cp_rccr; | ||
| 538 | u8 res1[14]; | ||
| 539 | u16 cp_rter; | ||
| 540 | u8 res2[2]; | ||
| 541 | u16 cp_rtmr; | ||
| 542 | u16 cp_rtscr; | ||
| 543 | u8 res3[2]; | ||
| 544 | u32 cp_rtsr; | ||
| 545 | u8 res4[12]; | ||
| 546 | } cpm_cpm2_t; | ||
| 547 | |||
| 548 | /* USB Controller. | ||
| 549 | */ | ||
| 550 | typedef struct usb_ctlr { | ||
| 551 | u8 usb_usmod; | ||
| 552 | u8 usb_usadr; | ||
| 553 | u8 usb_uscom; | ||
| 554 | u8 res1[1]; | ||
| 555 | u16 usb_usep1; | ||
| 556 | u16 usb_usep2; | ||
| 557 | u16 usb_usep3; | ||
| 558 | u16 usb_usep4; | ||
| 559 | u8 res2[4]; | ||
| 560 | u16 usb_usber; | ||
| 561 | u8 res3[2]; | ||
| 562 | u16 usb_usbmr; | ||
| 563 | u8 usb_usbs; | ||
| 564 | u8 res4[7]; | ||
| 565 | } usb_cpm2_t; | ||
| 566 | |||
| 567 | /* ...and the whole thing wrapped up.... | ||
| 568 | */ | ||
| 569 | |||
| 570 | typedef struct immap { | ||
| 571 | /* Some references are into the unique and known dpram spaces, | ||
| 572 | * others are from the generic base. | ||
| 573 | */ | ||
| 574 | #define im_dprambase im_dpram1 | ||
| 575 | u8 im_dpram1[16*1024]; | ||
| 576 | u8 res1[16*1024]; | ||
| 577 | u8 im_dpram2[4*1024]; | ||
| 578 | u8 res2[8*1024]; | ||
| 579 | u8 im_dpram3[4*1024]; | ||
| 580 | u8 res3[16*1024]; | ||
| 581 | |||
| 582 | sysconf_cpm2_t im_siu_conf; /* SIU Configuration */ | ||
| 583 | memctl_cpm2_t im_memctl; /* Memory Controller */ | ||
| 584 | sit_cpm2_t im_sit; /* System Integration Timers */ | ||
| 585 | pci_cpm2_t im_pci; /* PCI Controller */ | ||
| 586 | intctl_cpm2_t im_intctl; /* Interrupt Controller */ | ||
| 587 | car_cpm2_t im_clkrst; /* Clocks and reset */ | ||
| 588 | iop_cpm2_t im_ioport; /* IO Port control/status */ | ||
| 589 | cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */ | ||
| 590 | sdma_cpm2_t im_sdma; /* SDMA control/status */ | ||
| 591 | |||
| 592 | fcc_t im_fcc[3]; /* Three FCCs */ | ||
| 593 | u8 res4z[32]; | ||
| 594 | fcc_c_t im_fcc_c[3]; /* Continued FCCs */ | ||
| 595 | |||
| 596 | u8 res4[32]; | ||
| 597 | |||
| 598 | tclayer_t im_tclayer[8]; /* Eight TCLayers */ | ||
| 599 | u16 tc_tcgsr; | ||
| 600 | u16 tc_tcger; | ||
| 601 | |||
| 602 | /* First set of baud rate generators. | ||
| 603 | */ | ||
| 604 | u8 res[236]; | ||
| 605 | u32 im_brgc5; | ||
| 606 | u32 im_brgc6; | ||
| 607 | u32 im_brgc7; | ||
| 608 | u32 im_brgc8; | ||
| 609 | |||
| 610 | u8 res5[608]; | ||
| 611 | |||
| 612 | i2c_cpm2_t im_i2c; /* I2C control/status */ | ||
| 613 | cpm_cpm2_t im_cpm; /* Communication processor */ | ||
| 614 | |||
| 615 | /* Second set of baud rate generators. | ||
| 616 | */ | ||
| 617 | u32 im_brgc1; | ||
| 618 | u32 im_brgc2; | ||
| 619 | u32 im_brgc3; | ||
| 620 | u32 im_brgc4; | ||
| 621 | |||
| 622 | scc_t im_scc[4]; /* Four SCCs */ | ||
| 623 | smc_t im_smc[2]; /* Couple of SMCs */ | ||
| 624 | spictl_cpm2_t im_spi; /* A SPI */ | ||
| 625 | cpmux_t im_cpmux; /* CPM clock route mux */ | ||
| 626 | siramctl_t im_siramctl1; /* First SI RAM Control */ | ||
| 627 | mcc_t im_mcc1; /* First MCC */ | ||
| 628 | siramctl_t im_siramctl2; /* Second SI RAM Control */ | ||
| 629 | mcc_t im_mcc2; /* Second MCC */ | ||
| 630 | usb_cpm2_t im_usb; /* USB Controller */ | ||
| 631 | |||
| 632 | u8 res6[1153]; | ||
| 633 | |||
| 634 | u16 im_si1txram[256]; | ||
| 635 | u8 res7[512]; | ||
| 636 | u16 im_si1rxram[256]; | ||
| 637 | u8 res8[512]; | ||
| 638 | u16 im_si2txram[256]; | ||
| 639 | u8 res9[512]; | ||
| 640 | u16 im_si2rxram[256]; | ||
| 641 | u8 res10[512]; | ||
| 642 | u8 res11[4096]; | ||
| 643 | } cpm2_map_t; | ||
| 644 | |||
| 645 | extern cpm2_map_t *cpm2_immr; | ||
| 646 | |||
| 647 | #endif /* __IMMAP_CPM2__ */ | ||
| 648 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h deleted file mode 100644 index a0d409a5d80f..000000000000 --- a/include/asm-ppc/io.h +++ /dev/null | |||
| @@ -1,502 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | #ifndef _PPC_IO_H | ||
| 3 | #define _PPC_IO_H | ||
| 4 | |||
| 5 | #include <linux/string.h> | ||
| 6 | #include <linux/types.h> | ||
| 7 | |||
| 8 | #include <asm/page.h> | ||
| 9 | #include <asm/byteorder.h> | ||
| 10 | #include <asm/synch.h> | ||
| 11 | #include <asm/mmu.h> | ||
| 12 | |||
| 13 | #define SIO_CONFIG_RA 0x398 | ||
| 14 | #define SIO_CONFIG_RD 0x399 | ||
| 15 | |||
| 16 | #define SLOW_DOWN_IO | ||
| 17 | |||
| 18 | #define PMAC_ISA_MEM_BASE 0 | ||
| 19 | #define PMAC_PCI_DRAM_OFFSET 0 | ||
| 20 | #define CHRP_ISA_IO_BASE 0xf8000000 | ||
| 21 | #define CHRP_ISA_MEM_BASE 0xf7000000 | ||
| 22 | #define CHRP_PCI_DRAM_OFFSET 0 | ||
| 23 | #define PREP_ISA_IO_BASE 0x80000000 | ||
| 24 | #define PREP_ISA_MEM_BASE 0xc0000000 | ||
| 25 | #define PREP_PCI_DRAM_OFFSET 0x80000000 | ||
| 26 | |||
| 27 | #if defined(CONFIG_4xx) | ||
| 28 | #include <asm/ibm4xx.h> | ||
| 29 | #elif defined(CONFIG_8xx) | ||
| 30 | #include <asm/mpc8xx.h> | ||
| 31 | #elif defined(CONFIG_8260) | ||
| 32 | #include <asm/mpc8260.h> | ||
| 33 | #elif !defined(CONFIG_PCI) | ||
| 34 | #define _IO_BASE 0 | ||
| 35 | #define _ISA_MEM_BASE 0 | ||
| 36 | #define PCI_DRAM_OFFSET 0 | ||
| 37 | #else /* Everyone else */ | ||
| 38 | #define _IO_BASE isa_io_base | ||
| 39 | #define _ISA_MEM_BASE isa_mem_base | ||
| 40 | #define PCI_DRAM_OFFSET pci_dram_offset | ||
| 41 | #endif /* Platform-dependent I/O */ | ||
| 42 | |||
| 43 | #define ___IO_BASE ((void __iomem *)_IO_BASE) | ||
| 44 | extern unsigned long isa_io_base; | ||
| 45 | extern unsigned long isa_mem_base; | ||
| 46 | extern unsigned long pci_dram_offset; | ||
| 47 | |||
| 48 | /* | ||
| 49 | * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. | ||
| 50 | * | ||
| 51 | * Read operations have additional twi & isync to make sure the read | ||
| 52 | * is actually performed (i.e. the data has come back) before we start | ||
| 53 | * executing any following instructions. | ||
| 54 | */ | ||
| 55 | extern inline int in_8(const volatile unsigned char __iomem *addr) | ||
| 56 | { | ||
| 57 | int ret; | ||
| 58 | |||
| 59 | __asm__ __volatile__( | ||
| 60 | "sync; lbz%U1%X1 %0,%1;\n" | ||
| 61 | "twi 0,%0,0;\n" | ||
| 62 | "isync" : "=r" (ret) : "m" (*addr)); | ||
| 63 | return ret; | ||
| 64 | } | ||
| 65 | |||
| 66 | extern inline void out_8(volatile unsigned char __iomem *addr, int val) | ||
| 67 | { | ||
| 68 | __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); | ||
| 69 | } | ||
| 70 | |||
| 71 | extern inline int in_le16(const volatile unsigned short __iomem *addr) | ||
| 72 | { | ||
| 73 | int ret; | ||
| 74 | |||
| 75 | __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" | ||
| 76 | "twi 0,%0,0;\n" | ||
| 77 | "isync" : "=r" (ret) : | ||
| 78 | "r" (addr), "m" (*addr)); | ||
| 79 | return ret; | ||
| 80 | } | ||
| 81 | |||
| 82 | extern inline int in_be16(const volatile unsigned short __iomem *addr) | ||
| 83 | { | ||
| 84 | int ret; | ||
| 85 | |||
| 86 | __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" | ||
| 87 | "twi 0,%0,0;\n" | ||
| 88 | "isync" : "=r" (ret) : "m" (*addr)); | ||
| 89 | return ret; | ||
| 90 | } | ||
| 91 | |||
| 92 | extern inline void out_le16(volatile unsigned short __iomem *addr, int val) | ||
| 93 | { | ||
| 94 | __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : | ||
| 95 | "r" (val), "r" (addr)); | ||
| 96 | } | ||
| 97 | |||
| 98 | extern inline void out_be16(volatile unsigned short __iomem *addr, int val) | ||
| 99 | { | ||
| 100 | __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); | ||
| 101 | } | ||
| 102 | |||
| 103 | extern inline unsigned in_le32(const volatile unsigned __iomem *addr) | ||
| 104 | { | ||
| 105 | unsigned ret; | ||
| 106 | |||
| 107 | __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" | ||
| 108 | "twi 0,%0,0;\n" | ||
| 109 | "isync" : "=r" (ret) : | ||
| 110 | "r" (addr), "m" (*addr)); | ||
| 111 | return ret; | ||
| 112 | } | ||
| 113 | |||
| 114 | extern inline unsigned in_be32(const volatile unsigned __iomem *addr) | ||
| 115 | { | ||
| 116 | unsigned ret; | ||
| 117 | |||
| 118 | __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" | ||
| 119 | "twi 0,%0,0;\n" | ||
| 120 | "isync" : "=r" (ret) : "m" (*addr)); | ||
| 121 | return ret; | ||
| 122 | } | ||
| 123 | |||
| 124 | extern inline void out_le32(volatile unsigned __iomem *addr, int val) | ||
| 125 | { | ||
| 126 | __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : | ||
| 127 | "r" (val), "r" (addr)); | ||
| 128 | } | ||
| 129 | |||
| 130 | extern inline void out_be32(volatile unsigned __iomem *addr, int val) | ||
| 131 | { | ||
| 132 | __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); | ||
| 133 | } | ||
| 134 | #if defined (CONFIG_8260_PCI9) | ||
| 135 | #define readb(addr) in_8((volatile u8 *)(addr)) | ||
| 136 | #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) | ||
| 137 | #else | ||
| 138 | static inline __u8 readb(const volatile void __iomem *addr) | ||
| 139 | { | ||
| 140 | return in_8(addr); | ||
| 141 | } | ||
| 142 | static inline void writeb(__u8 b, volatile void __iomem *addr) | ||
| 143 | { | ||
| 144 | out_8(addr, b); | ||
| 145 | } | ||
| 146 | #endif | ||
| 147 | |||
| 148 | #if defined (CONFIG_8260_PCI9) | ||
| 149 | /* Use macros if PCI9 workaround enabled */ | ||
| 150 | #define readw(addr) in_le16((volatile u16 *)(addr)) | ||
| 151 | #define readl(addr) in_le32((volatile u32 *)(addr)) | ||
| 152 | #define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) | ||
| 153 | #define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) | ||
| 154 | #else | ||
| 155 | static inline __u16 readw(const volatile void __iomem *addr) | ||
| 156 | { | ||
| 157 | return in_le16(addr); | ||
| 158 | } | ||
| 159 | static inline __u32 readl(const volatile void __iomem *addr) | ||
| 160 | { | ||
| 161 | return in_le32(addr); | ||
| 162 | } | ||
| 163 | static inline void writew(__u16 b, volatile void __iomem *addr) | ||
| 164 | { | ||
| 165 | out_le16(addr, b); | ||
| 166 | } | ||
| 167 | static inline void writel(__u32 b, volatile void __iomem *addr) | ||
| 168 | { | ||
| 169 | out_le32(addr, b); | ||
| 170 | } | ||
| 171 | #endif /* CONFIG_8260_PCI9 */ | ||
| 172 | |||
| 173 | #define readb_relaxed(addr) readb(addr) | ||
| 174 | #define readw_relaxed(addr) readw(addr) | ||
| 175 | #define readl_relaxed(addr) readl(addr) | ||
| 176 | |||
| 177 | static inline __u8 __raw_readb(const volatile void __iomem *addr) | ||
| 178 | { | ||
| 179 | return *(__force volatile __u8 *)(addr); | ||
| 180 | } | ||
| 181 | static inline __u16 __raw_readw(const volatile void __iomem *addr) | ||
| 182 | { | ||
| 183 | return *(__force volatile __u16 *)(addr); | ||
| 184 | } | ||
| 185 | static inline __u32 __raw_readl(const volatile void __iomem *addr) | ||
| 186 | { | ||
| 187 | return *(__force volatile __u32 *)(addr); | ||
| 188 | } | ||
| 189 | static inline void __raw_writeb(__u8 b, volatile void __iomem *addr) | ||
| 190 | { | ||
| 191 | *(__force volatile __u8 *)(addr) = b; | ||
| 192 | } | ||
| 193 | static inline void __raw_writew(__u16 b, volatile void __iomem *addr) | ||
| 194 | { | ||
| 195 | *(__force volatile __u16 *)(addr) = b; | ||
| 196 | } | ||
| 197 | static inline void __raw_writel(__u32 b, volatile void __iomem *addr) | ||
| 198 | { | ||
| 199 | *(__force volatile __u32 *)(addr) = b; | ||
| 200 | } | ||
| 201 | |||
| 202 | #define mmiowb() | ||
| 203 | |||
| 204 | /* | ||
| 205 | * The insw/outsw/insl/outsl macros don't do byte-swapping. | ||
| 206 | * They are only used in practice for transferring buffers which | ||
| 207 | * are arrays of bytes, and byte-swapping is not appropriate in | ||
| 208 | * that case. - paulus | ||
| 209 | */ | ||
| 210 | #define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns)) | ||
| 211 | #define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns)) | ||
| 212 | #define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns)) | ||
| 213 | #define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns)) | ||
| 214 | #define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl)) | ||
| 215 | #define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl)) | ||
| 216 | |||
| 217 | #define readsb(a, b, n) _insb((a), (b), (n)) | ||
| 218 | #define readsw(a, b, n) _insw_ns((a), (b), (n)) | ||
| 219 | #define readsl(a, b, n) _insl_ns((a), (b), (n)) | ||
| 220 | #define writesb(a, b, n) _outsb((a),(b),(n)) | ||
| 221 | #define writesw(a, b, n) _outsw_ns((a),(b),(n)) | ||
| 222 | #define writesl(a, b, n) _outsl_ns((a),(b),(n)) | ||
| 223 | |||
| 224 | |||
| 225 | /* | ||
| 226 | * On powermacs and 8xx we will get a machine check exception | ||
| 227 | * if we try to read data from a non-existent I/O port. Because | ||
| 228 | * the machine check is an asynchronous exception, it isn't | ||
| 229 | * well-defined which instruction SRR0 will point to when the | ||
| 230 | * exception occurs. | ||
| 231 | * With the sequence below (twi; isync; nop), we have found that | ||
| 232 | * the machine check occurs on one of the three instructions on | ||
| 233 | * all PPC implementations tested so far. The twi and isync are | ||
| 234 | * needed on the 601 (in fact twi; sync works too), the isync and | ||
| 235 | * nop are needed on 604[e|r], and any of twi, sync or isync will | ||
| 236 | * work on 603[e], 750, 74xx. | ||
| 237 | * The twi creates an explicit data dependency on the returned | ||
| 238 | * value which seems to be needed to make the 601 wait for the | ||
| 239 | * load to finish. | ||
| 240 | */ | ||
| 241 | |||
| 242 | #define __do_in_asm(name, op) \ | ||
| 243 | extern __inline__ unsigned int name(unsigned int port) \ | ||
| 244 | { \ | ||
| 245 | unsigned int x; \ | ||
| 246 | __asm__ __volatile__( \ | ||
| 247 | "sync\n" \ | ||
| 248 | "0:" op " %0,0,%1\n" \ | ||
| 249 | "1: twi 0,%0,0\n" \ | ||
| 250 | "2: isync\n" \ | ||
| 251 | "3: nop\n" \ | ||
| 252 | "4:\n" \ | ||
| 253 | ".section .fixup,\"ax\"\n" \ | ||
| 254 | "5: li %0,-1\n" \ | ||
| 255 | " b 4b\n" \ | ||
| 256 | ".previous\n" \ | ||
| 257 | ".section __ex_table,\"a\"\n" \ | ||
| 258 | " .align 2\n" \ | ||
| 259 | " .long 0b,5b\n" \ | ||
| 260 | " .long 1b,5b\n" \ | ||
| 261 | " .long 2b,5b\n" \ | ||
| 262 | " .long 3b,5b\n" \ | ||
| 263 | ".previous" \ | ||
| 264 | : "=&r" (x) \ | ||
| 265 | : "r" (port + ___IO_BASE)); \ | ||
| 266 | return x; \ | ||
| 267 | } | ||
| 268 | |||
| 269 | #define __do_out_asm(name, op) \ | ||
| 270 | extern __inline__ void name(unsigned int val, unsigned int port) \ | ||
| 271 | { \ | ||
| 272 | __asm__ __volatile__( \ | ||
| 273 | "sync\n" \ | ||
| 274 | "0:" op " %0,0,%1\n" \ | ||
| 275 | "1: sync\n" \ | ||
| 276 | "2:\n" \ | ||
| 277 | ".section __ex_table,\"a\"\n" \ | ||
| 278 | " .align 2\n" \ | ||
| 279 | " .long 0b,2b\n" \ | ||
| 280 | " .long 1b,2b\n" \ | ||
| 281 | ".previous" \ | ||
| 282 | : : "r" (val), "r" (port + ___IO_BASE)); \ | ||
| 283 | } | ||
| 284 | |||
| 285 | __do_out_asm(outb, "stbx") | ||
| 286 | #if defined (CONFIG_8260_PCI9) | ||
| 287 | /* in asm cannot be defined if PCI9 workaround is used */ | ||
| 288 | #define inb(port) in_8((port)+___IO_BASE) | ||
| 289 | #define inw(port) in_le16((port)+___IO_BASE) | ||
| 290 | #define inl(port) in_le32((port)+___IO_BASE) | ||
| 291 | __do_out_asm(outw, "sthbrx") | ||
| 292 | __do_out_asm(outl, "stwbrx") | ||
| 293 | #else | ||
| 294 | __do_in_asm(inb, "lbzx") | ||
| 295 | __do_in_asm(inw, "lhbrx") | ||
| 296 | __do_in_asm(inl, "lwbrx") | ||
| 297 | __do_out_asm(outw, "sthbrx") | ||
| 298 | __do_out_asm(outl, "stwbrx") | ||
| 299 | |||
| 300 | #endif | ||
| 301 | |||
| 302 | #define inb_p(port) inb((port)) | ||
| 303 | #define outb_p(val, port) outb((val), (port)) | ||
| 304 | #define inw_p(port) inw((port)) | ||
| 305 | #define outw_p(val, port) outw((val), (port)) | ||
| 306 | #define inl_p(port) inl((port)) | ||
| 307 | #define outl_p(val, port) outl((val), (port)) | ||
| 308 | |||
| 309 | extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); | ||
| 310 | extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); | ||
| 311 | extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); | ||
| 312 | extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); | ||
| 313 | extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); | ||
| 314 | extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); | ||
| 315 | |||
| 316 | |||
| 317 | #define IO_SPACE_LIMIT ~0 | ||
| 318 | |||
| 319 | #if defined (CONFIG_8260_PCI9) | ||
| 320 | #define memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
| 321 | #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
| 322 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
| 323 | #else | ||
| 324 | static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) | ||
| 325 | { | ||
| 326 | memset((void __force *)addr, val, count); | ||
| 327 | } | ||
| 328 | static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count) | ||
| 329 | { | ||
| 330 | memcpy(dst, (void __force *) src, count); | ||
| 331 | } | ||
| 332 | static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) | ||
| 333 | { | ||
| 334 | memcpy((void __force *) dst, src, count); | ||
| 335 | } | ||
| 336 | #endif | ||
| 337 | |||
| 338 | /* | ||
| 339 | * Map in an area of physical address space, for accessing | ||
| 340 | * I/O devices etc. | ||
| 341 | */ | ||
| 342 | extern void __iomem *__ioremap(phys_addr_t address, unsigned long size, | ||
| 343 | unsigned long flags); | ||
| 344 | extern void __iomem *ioremap(phys_addr_t address, unsigned long size); | ||
| 345 | #ifdef CONFIG_44x | ||
| 346 | extern void __iomem *ioremap64(unsigned long long address, unsigned long size); | ||
| 347 | #endif | ||
| 348 | #define ioremap_nocache(addr, size) ioremap((addr), (size)) | ||
| 349 | extern void iounmap(volatile void __iomem *addr); | ||
| 350 | extern unsigned long iopa(unsigned long addr); | ||
| 351 | extern void io_block_mapping(unsigned long virt, phys_addr_t phys, | ||
| 352 | unsigned int size, int flags); | ||
| 353 | |||
| 354 | /* | ||
| 355 | * The PCI bus is inherently Little-Endian. The PowerPC is being | ||
| 356 | * run Big-Endian. Thus all values which cross the [PCI] barrier | ||
| 357 | * must be endian-adjusted. Also, the local DRAM has a different | ||
| 358 | * address from the PCI point of view, thus buffer addresses also | ||
| 359 | * have to be modified [mapped] appropriately. | ||
| 360 | */ | ||
| 361 | extern inline unsigned long virt_to_bus(volatile void * address) | ||
| 362 | { | ||
| 363 | if (address == (void *)0) | ||
| 364 | return 0; | ||
| 365 | return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET; | ||
| 366 | } | ||
| 367 | |||
| 368 | extern inline void * bus_to_virt(unsigned long address) | ||
| 369 | { | ||
| 370 | if (address == 0) | ||
| 371 | return NULL; | ||
| 372 | return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE); | ||
| 373 | } | ||
| 374 | |||
| 375 | /* | ||
| 376 | * Change virtual addresses to physical addresses and vv, for | ||
| 377 | * addresses in the area where the kernel has the RAM mapped. | ||
| 378 | */ | ||
| 379 | extern inline unsigned long virt_to_phys(volatile void * address) | ||
| 380 | { | ||
| 381 | return (unsigned long) address - KERNELBASE; | ||
| 382 | } | ||
| 383 | |||
| 384 | extern inline void * phys_to_virt(unsigned long address) | ||
| 385 | { | ||
| 386 | return (void *) (address + KERNELBASE); | ||
| 387 | } | ||
| 388 | |||
| 389 | /* | ||
| 390 | * Change "struct page" to physical address. | ||
| 391 | */ | ||
| 392 | #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) | ||
| 393 | #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) | ||
| 394 | |||
| 395 | /* Enforce in-order execution of data I/O. | ||
| 396 | * No distinction between read/write on PPC; use eieio for all three. | ||
| 397 | */ | ||
| 398 | #define iobarrier_rw() eieio() | ||
| 399 | #define iobarrier_r() eieio() | ||
| 400 | #define iobarrier_w() eieio() | ||
| 401 | |||
| 402 | /* | ||
| 403 | * Here comes the ppc implementation of the IOMAP | ||
| 404 | * interfaces. | ||
| 405 | */ | ||
| 406 | static inline unsigned int ioread8(void __iomem *addr) | ||
| 407 | { | ||
| 408 | return readb(addr); | ||
| 409 | } | ||
| 410 | |||
| 411 | static inline unsigned int ioread16(void __iomem *addr) | ||
| 412 | { | ||
| 413 | return readw(addr); | ||
| 414 | } | ||
| 415 | |||
| 416 | static inline unsigned int ioread32(void __iomem *addr) | ||
| 417 | { | ||
| 418 | return readl(addr); | ||
| 419 | } | ||
| 420 | |||
| 421 | static inline void iowrite8(u8 val, void __iomem *addr) | ||
| 422 | { | ||
| 423 | writeb(val, addr); | ||
| 424 | } | ||
| 425 | |||
| 426 | static inline void iowrite16(u16 val, void __iomem *addr) | ||
| 427 | { | ||
| 428 | writew(val, addr); | ||
| 429 | } | ||
| 430 | |||
| 431 | static inline void iowrite32(u32 val, void __iomem *addr) | ||
| 432 | { | ||
| 433 | writel(val, addr); | ||
| 434 | } | ||
| 435 | |||
| 436 | static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count) | ||
| 437 | { | ||
| 438 | _insb(addr, dst, count); | ||
| 439 | } | ||
| 440 | |||
| 441 | static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count) | ||
| 442 | { | ||
| 443 | _insw_ns(addr, dst, count); | ||
| 444 | } | ||
| 445 | |||
| 446 | static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count) | ||
| 447 | { | ||
| 448 | _insl_ns(addr, dst, count); | ||
| 449 | } | ||
| 450 | |||
| 451 | static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count) | ||
| 452 | { | ||
| 453 | _outsb(addr, src, count); | ||
| 454 | } | ||
| 455 | |||
| 456 | static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count) | ||
| 457 | { | ||
| 458 | _outsw_ns(addr, src, count); | ||
| 459 | } | ||
| 460 | |||
| 461 | static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count) | ||
| 462 | { | ||
| 463 | _outsl_ns(addr, src, count); | ||
| 464 | } | ||
| 465 | |||
| 466 | /* Create a virtual mapping cookie for an IO port range */ | ||
| 467 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | ||
| 468 | extern void ioport_unmap(void __iomem *); | ||
| 469 | |||
| 470 | /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ | ||
| 471 | struct pci_dev; | ||
| 472 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); | ||
| 473 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *); | ||
| 474 | |||
| 475 | #endif /* _PPC_IO_H */ | ||
| 476 | |||
| 477 | #ifdef CONFIG_8260_PCI9 | ||
| 478 | #include <asm/mpc8260_pci9.h> | ||
| 479 | #endif | ||
| 480 | |||
| 481 | /* | ||
| 482 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | ||
| 483 | * access | ||
| 484 | */ | ||
| 485 | #define xlate_dev_mem_ptr(p) __va(p) | ||
| 486 | |||
| 487 | /* | ||
| 488 | * Convert a virtual cached pointer to an uncached pointer | ||
| 489 | */ | ||
| 490 | #define xlate_dev_kmem_ptr(p) p | ||
| 491 | |||
| 492 | /* access ports */ | ||
| 493 | #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) | ||
| 494 | #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) | ||
| 495 | |||
| 496 | #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) | ||
| 497 | #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) | ||
| 498 | |||
| 499 | #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) | ||
| 500 | #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) | ||
| 501 | |||
| 502 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/irq_regs.h b/include/asm-ppc/irq_regs.h deleted file mode 100644 index 3dd9c0b70270..000000000000 --- a/include/asm-ppc/irq_regs.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/irq_regs.h> | ||
diff --git a/include/asm-ppc/kdebug.h b/include/asm-ppc/kdebug.h deleted file mode 100644 index 6ece1b037665..000000000000 --- a/include/asm-ppc/kdebug.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-generic/kdebug.h> | ||
diff --git a/include/asm-ppc/kgdb.h b/include/asm-ppc/kgdb.h deleted file mode 100644 index b617dac82969..000000000000 --- a/include/asm-ppc/kgdb.h +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * kgdb.h: Defines and declarations for serial line source level | ||
| 3 | * remote debugging of the Linux kernel using gdb. | ||
| 4 | * | ||
| 5 | * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu) | ||
| 6 | * | ||
| 7 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
| 8 | */ | ||
| 9 | #ifdef __KERNEL__ | ||
| 10 | #ifndef _PPC_KGDB_H | ||
| 11 | #define _PPC_KGDB_H | ||
| 12 | |||
| 13 | #ifndef __ASSEMBLY__ | ||
| 14 | |||
| 15 | /* Things specific to the gen550 backend. */ | ||
| 16 | struct uart_port; | ||
| 17 | |||
| 18 | extern void gen550_progress(char *, unsigned short); | ||
| 19 | extern void gen550_kgdb_map_scc(void); | ||
| 20 | extern void gen550_init(int, struct uart_port *); | ||
| 21 | |||
| 22 | /* Things specific to the pmac backend. */ | ||
| 23 | extern void zs_kgdb_hook(int tty_num); | ||
| 24 | |||
| 25 | /* To init the kgdb engine. (called by serial hook)*/ | ||
| 26 | extern void set_debug_traps(void); | ||
| 27 | |||
| 28 | /* To enter the debugger explicitly. */ | ||
| 29 | extern void breakpoint(void); | ||
| 30 | |||
| 31 | /* For taking exceptions | ||
| 32 | * these are defined in traps.c | ||
| 33 | */ | ||
| 34 | extern int (*debugger)(struct pt_regs *regs); | ||
| 35 | extern int (*debugger_bpt)(struct pt_regs *regs); | ||
| 36 | extern int (*debugger_sstep)(struct pt_regs *regs); | ||
| 37 | extern int (*debugger_iabr_match)(struct pt_regs *regs); | ||
| 38 | extern int (*debugger_dabr_match)(struct pt_regs *regs); | ||
| 39 | extern void (*debugger_fault_handler)(struct pt_regs *regs); | ||
| 40 | |||
| 41 | /* What we bring to the party */ | ||
| 42 | int kgdb_bpt(struct pt_regs *regs); | ||
| 43 | int kgdb_sstep(struct pt_regs *regs); | ||
| 44 | void kgdb(struct pt_regs *regs); | ||
| 45 | int kgdb_iabr_match(struct pt_regs *regs); | ||
| 46 | int kgdb_dabr_match(struct pt_regs *regs); | ||
| 47 | |||
| 48 | /* | ||
| 49 | * external low-level support routines (ie macserial.c) | ||
| 50 | */ | ||
| 51 | extern void kgdb_interruptible(int); /* control interrupts from serial */ | ||
| 52 | extern void putDebugChar(char); /* write a single character */ | ||
| 53 | extern char getDebugChar(void); /* read and return a single char */ | ||
| 54 | |||
| 55 | #endif /* !(__ASSEMBLY__) */ | ||
| 56 | #endif /* !(_PPC_KGDB_H) */ | ||
| 57 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h deleted file mode 100644 index bf9e05dd54b5..000000000000 --- a/include/asm-ppc/m8260_pci.h +++ /dev/null | |||
| @@ -1,187 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/m8260_pci.h | ||
| 3 | * | ||
| 4 | * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifdef __KERNEL__ | ||
| 13 | #ifndef __M8260_PCI_H | ||
| 14 | #define __M8260_PCI_H | ||
| 15 | |||
| 16 | #include <linux/pci_ids.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Define the vendor/device ID for the MPC8265. | ||
| 20 | */ | ||
| 21 | #define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
| 22 | #define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
| 23 | |||
| 24 | #define M8265_PCIBR0 0x101ac | ||
| 25 | #define M8265_PCIBR1 0x101b0 | ||
| 26 | #define M8265_PCIMSK0 0x101c4 | ||
| 27 | #define M8265_PCIMSK1 0x101c8 | ||
| 28 | |||
| 29 | /* Bit definitions for PCIBR registers */ | ||
| 30 | |||
| 31 | #define PCIBR_ENABLE 0x00000001 | ||
| 32 | |||
| 33 | /* Bit definitions for PCIMSK registers */ | ||
| 34 | |||
| 35 | #define PCIMSK_32KiB 0xFFFF8000 /* Size of window, smallest */ | ||
| 36 | #define PCIMSK_64KiB 0xFFFF0000 | ||
| 37 | #define PCIMSK_128KiB 0xFFFE0000 | ||
| 38 | #define PCIMSK_256KiB 0xFFFC0000 | ||
| 39 | #define PCIMSK_512KiB 0xFFF80000 | ||
| 40 | #define PCIMSK_1MiB 0xFFF00000 | ||
| 41 | #define PCIMSK_2MiB 0xFFE00000 | ||
| 42 | #define PCIMSK_4MiB 0xFFC00000 | ||
| 43 | #define PCIMSK_8MiB 0xFF800000 | ||
| 44 | #define PCIMSK_16MiB 0xFF000000 | ||
| 45 | #define PCIMSK_32MiB 0xFE000000 | ||
| 46 | #define PCIMSK_64MiB 0xFC000000 | ||
| 47 | #define PCIMSK_128MiB 0xF8000000 | ||
| 48 | #define PCIMSK_256MiB 0xF0000000 | ||
| 49 | #define PCIMSK_512MiB 0xE0000000 | ||
| 50 | #define PCIMSK_1GiB 0xC0000000 /* Size of window, largest */ | ||
| 51 | |||
| 52 | |||
| 53 | #define M826X_SCCR_PCI_MODE_EN 0x100 | ||
| 54 | |||
| 55 | |||
| 56 | /* | ||
| 57 | * Outbound ATU registers (3 sets). These registers control how 60x bus (local) | ||
| 58 | * addresses are translated to PCI addresses when the MPC826x is a PCI bus | ||
| 59 | * master (initiator). | ||
| 60 | */ | ||
| 61 | |||
| 62 | #define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ | ||
| 63 | #define POTAR_REG1 0x10818 | ||
| 64 | #define POTAR_REG2 0x10830 | ||
| 65 | |||
| 66 | #define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ | ||
| 67 | #define POBAR_REG1 0x10820 | ||
| 68 | #define POBAR_REG2 0x10838 | ||
| 69 | |||
| 70 | #define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ | ||
| 71 | #define POCMR_REG1 0x10828 | ||
| 72 | #define POCMR_REG2 0x10840 | ||
| 73 | |||
| 74 | /* Bit definitions for POMCR registers */ | ||
| 75 | |||
| 76 | #define POCMR_MASK_4KiB 0x000FFFFF | ||
| 77 | #define POCMR_MASK_8KiB 0x000FFFFE | ||
| 78 | #define POCMR_MASK_16KiB 0x000FFFFC | ||
| 79 | #define POCMR_MASK_32KiB 0x000FFFF8 | ||
| 80 | #define POCMR_MASK_64KiB 0x000FFFF0 | ||
| 81 | #define POCMR_MASK_128KiB 0x000FFFE0 | ||
| 82 | #define POCMR_MASK_256KiB 0x000FFFC0 | ||
| 83 | #define POCMR_MASK_512KiB 0x000FFF80 | ||
| 84 | #define POCMR_MASK_1MiB 0x000FFF00 | ||
| 85 | #define POCMR_MASK_2MiB 0x000FFE00 | ||
| 86 | #define POCMR_MASK_4MiB 0x000FFC00 | ||
| 87 | #define POCMR_MASK_8MiB 0x000FF800 | ||
| 88 | #define POCMR_MASK_16MiB 0x000FF000 | ||
| 89 | #define POCMR_MASK_32MiB 0x000FE000 | ||
| 90 | #define POCMR_MASK_64MiB 0x000FC000 | ||
| 91 | #define POCMR_MASK_128MiB 0x000F8000 | ||
| 92 | #define POCMR_MASK_256MiB 0x000F0000 | ||
| 93 | #define POCMR_MASK_512MiB 0x000E0000 | ||
| 94 | #define POCMR_MASK_1GiB 0x000C0000 | ||
| 95 | |||
| 96 | #define POCMR_ENABLE 0x80000000 | ||
| 97 | #define POCMR_PCI_IO 0x40000000 | ||
| 98 | #define POCMR_PREFETCH_EN 0x20000000 | ||
| 99 | |||
| 100 | /* Soft PCI reset */ | ||
| 101 | |||
| 102 | #define PCI_GCR_REG 0x10880 | ||
| 103 | |||
| 104 | /* Bit definitions for PCI_GCR registers */ | ||
| 105 | |||
| 106 | #define PCIGCR_PCI_BUS_EN 0x1 | ||
| 107 | |||
| 108 | #define PCI_EMR_REG 0x10888 | ||
| 109 | /* | ||
| 110 | * Inbound ATU registers (2 sets). These registers control how PCI addresses | ||
| 111 | * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. | ||
| 112 | */ | ||
| 113 | |||
| 114 | #define PITAR_REG1 0x108D0 | ||
| 115 | #define PIBAR_REG1 0x108D8 | ||
| 116 | #define PICMR_REG1 0x108E0 | ||
| 117 | #define PITAR_REG0 0x108E8 | ||
| 118 | #define PIBAR_REG0 0x108F0 | ||
| 119 | #define PICMR_REG0 0x108F8 | ||
| 120 | |||
| 121 | /* Bit definitions for PCI Inbound Comparison Mask registers */ | ||
| 122 | |||
| 123 | #define PICMR_MASK_4KiB 0x000FFFFF | ||
| 124 | #define PICMR_MASK_8KiB 0x000FFFFE | ||
| 125 | #define PICMR_MASK_16KiB 0x000FFFFC | ||
| 126 | #define PICMR_MASK_32KiB 0x000FFFF8 | ||
| 127 | #define PICMR_MASK_64KiB 0x000FFFF0 | ||
| 128 | #define PICMR_MASK_128KiB 0x000FFFE0 | ||
| 129 | #define PICMR_MASK_256KiB 0x000FFFC0 | ||
| 130 | #define PICMR_MASK_512KiB 0x000FFF80 | ||
| 131 | #define PICMR_MASK_1MiB 0x000FFF00 | ||
| 132 | #define PICMR_MASK_2MiB 0x000FFE00 | ||
| 133 | #define PICMR_MASK_4MiB 0x000FFC00 | ||
| 134 | #define PICMR_MASK_8MiB 0x000FF800 | ||
| 135 | #define PICMR_MASK_16MiB 0x000FF000 | ||
| 136 | #define PICMR_MASK_32MiB 0x000FE000 | ||
| 137 | #define PICMR_MASK_64MiB 0x000FC000 | ||
| 138 | #define PICMR_MASK_128MiB 0x000F8000 | ||
| 139 | #define PICMR_MASK_256MiB 0x000F0000 | ||
| 140 | #define PICMR_MASK_512MiB 0x000E0000 | ||
| 141 | #define PICMR_MASK_1GiB 0x000C0000 | ||
| 142 | |||
| 143 | #define PICMR_ENABLE 0x80000000 | ||
| 144 | #define PICMR_NO_SNOOP_EN 0x40000000 | ||
| 145 | #define PICMR_PREFETCH_EN 0x20000000 | ||
| 146 | |||
| 147 | /* PCI error Registers */ | ||
| 148 | |||
| 149 | #define PCI_ERROR_STATUS_REG 0x10884 | ||
| 150 | #define PCI_ERROR_MASK_REG 0x10888 | ||
| 151 | #define PCI_ERROR_CONTROL_REG 0x1088C | ||
| 152 | #define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 | ||
| 153 | #define PCI_ERROR_DATA_CAPTURE_REG 0x10898 | ||
| 154 | #define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 | ||
| 155 | |||
| 156 | /* PCI error Register bit defines */ | ||
| 157 | |||
| 158 | #define PCI_ERROR_PCI_ADDR_PAR 0x00000001 | ||
| 159 | #define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 | ||
| 160 | #define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 | ||
| 161 | #define PCI_ERROR_PCI_NO_RSP 0x00000008 | ||
| 162 | #define PCI_ERROR_PCI_TAR_ABT 0x00000010 | ||
| 163 | #define PCI_ERROR_PCI_SERR 0x00000020 | ||
| 164 | #define PCI_ERROR_PCI_PERR_RD 0x00000040 | ||
| 165 | #define PCI_ERROR_PCI_PERR_WR 0x00000080 | ||
| 166 | #define PCI_ERROR_I2O_OFQO 0x00000100 | ||
| 167 | #define PCI_ERROR_I2O_IPQO 0x00000200 | ||
| 168 | #define PCI_ERROR_IRA 0x00000400 | ||
| 169 | #define PCI_ERROR_NMI 0x00000800 | ||
| 170 | #define PCI_ERROR_I2O_DBMC 0x00001000 | ||
| 171 | |||
| 172 | /* | ||
| 173 | * Register pair used to generate configuration cycles on the PCI bus | ||
| 174 | * and access the MPC826x's own PCI configuration registers. | ||
| 175 | */ | ||
| 176 | |||
| 177 | #define PCI_CFG_ADDR_REG 0x10900 | ||
| 178 | #define PCI_CFG_DATA_REG 0x10904 | ||
| 179 | |||
| 180 | /* Bus parking decides where the bus control sits when idle */ | ||
| 181 | /* If modifying memory controllers for PCI park on the core */ | ||
| 182 | |||
| 183 | #define PPC_ACR_BUS_PARK_CORE 0x6 | ||
| 184 | #define PPC_ACR_BUS_PARK_PCI 0x3 | ||
| 185 | |||
| 186 | #endif /* __M8260_PCI_H */ | ||
| 187 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h deleted file mode 100644 index a20b499b0186..000000000000 --- a/include/asm-ppc/machdep.h +++ /dev/null | |||
| @@ -1,178 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | #ifndef _PPC_MACHDEP_H | ||
| 3 | #define _PPC_MACHDEP_H | ||
| 4 | |||
| 5 | #include <linux/init.h> | ||
| 6 | #include <linux/kexec.h> | ||
| 7 | |||
| 8 | #include <asm/setup.h> | ||
| 9 | #include <asm/page.h> | ||
| 10 | |||
| 11 | struct pt_regs; | ||
| 12 | struct pci_bus; | ||
| 13 | struct pci_dev; | ||
| 14 | struct seq_file; | ||
| 15 | struct file; | ||
| 16 | |||
| 17 | /* | ||
| 18 | * This is for compatibility with ARCH=powerpc. | ||
| 19 | */ | ||
| 20 | #define machine_is(x) __MACHINE_IS_##x | ||
| 21 | #define __MACHINE_IS_powermac 0 | ||
| 22 | #define __MACHINE_IS_chrp 0 | ||
| 23 | #ifdef CONFIG_PPC_PREP | ||
| 24 | #define __MACHINE_IS_prep 1 | ||
| 25 | #else | ||
| 26 | #define __MACHINE_IS_prep 0 | ||
| 27 | #endif | ||
| 28 | |||
| 29 | /* We export this macro for external modules like Alsa to know if | ||
| 30 | * ppc_md.feature_call is implemented or not | ||
| 31 | */ | ||
| 32 | #define CONFIG_PPC_HAS_FEATURE_CALLS | ||
| 33 | |||
| 34 | struct machdep_calls { | ||
| 35 | void (*setup_arch)(void); | ||
| 36 | /* Optional, may be NULL. */ | ||
| 37 | int (*show_cpuinfo)(struct seq_file *m); | ||
| 38 | int (*show_percpuinfo)(struct seq_file *m, int i); | ||
| 39 | /* Optional, may be NULL. */ | ||
| 40 | unsigned int (*irq_canonicalize)(unsigned int irq); | ||
| 41 | void (*init_IRQ)(void); | ||
| 42 | int (*get_irq)(void); | ||
| 43 | |||
| 44 | /* A general init function, called by ppc_init in init/main.c. | ||
| 45 | May be NULL. DEPRECATED ! */ | ||
| 46 | void (*init)(void); | ||
| 47 | /* For compatibility with merged platforms */ | ||
| 48 | void (*init_early)(void); | ||
| 49 | |||
| 50 | void (*restart)(char *cmd); | ||
| 51 | void (*power_off)(void); | ||
| 52 | void (*halt)(void); | ||
| 53 | |||
| 54 | void (*idle_loop)(void); | ||
| 55 | void (*power_save)(void); | ||
| 56 | |||
| 57 | long (*time_init)(void); /* Optional, may be NULL */ | ||
| 58 | int (*set_rtc_time)(unsigned long nowtime); | ||
| 59 | unsigned long (*get_rtc_time)(void); | ||
| 60 | unsigned char (*rtc_read_val)(int addr); | ||
| 61 | void (*rtc_write_val)(int addr, unsigned char val); | ||
| 62 | void (*calibrate_decr)(void); | ||
| 63 | |||
| 64 | void (*heartbeat)(void); | ||
| 65 | unsigned long heartbeat_reset; | ||
| 66 | unsigned long heartbeat_count; | ||
| 67 | |||
| 68 | unsigned long (*find_end_of_memory)(void); | ||
| 69 | void (*setup_io_mappings)(void); | ||
| 70 | |||
| 71 | void (*early_serial_map)(void); | ||
| 72 | void (*progress)(char *, unsigned short); | ||
| 73 | void (*kgdb_map_scc)(void); | ||
| 74 | |||
| 75 | unsigned char (*nvram_read_val)(int addr); | ||
| 76 | void (*nvram_write_val)(int addr, unsigned char val); | ||
| 77 | void (*nvram_sync)(void); | ||
| 78 | |||
| 79 | /* | ||
| 80 | * optional PCI "hooks" | ||
| 81 | */ | ||
| 82 | |||
| 83 | /* Called after scanning the bus, before allocating resources */ | ||
| 84 | void (*pcibios_fixup)(void); | ||
| 85 | |||
| 86 | /* Called after PPC generic resource fixup to perform | ||
| 87 | machine specific fixups */ | ||
| 88 | void (*pcibios_fixup_resources)(struct pci_dev *); | ||
| 89 | |||
| 90 | /* Called for each PCI bus in the system when it's probed */ | ||
| 91 | void (*pcibios_fixup_bus)(struct pci_bus *); | ||
| 92 | |||
| 93 | /* Called when pci_enable_device() is called (initial=0) or | ||
| 94 | * when a device with no assigned resource is found (initial=1). | ||
| 95 | * Returns 0 to allow assignment/enabling of the device. */ | ||
| 96 | int (*pcibios_enable_device_hook)(struct pci_dev *, int initial); | ||
| 97 | |||
| 98 | /* For interrupt routing */ | ||
| 99 | unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *); | ||
| 100 | int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char); | ||
| 101 | |||
| 102 | /* Called in indirect_* to avoid touching devices */ | ||
| 103 | int (*pci_exclude_device)(unsigned char, unsigned char); | ||
| 104 | |||
| 105 | /* Called at then very end of pcibios_init() */ | ||
| 106 | void (*pcibios_after_init)(void); | ||
| 107 | |||
| 108 | /* Get access protection for /dev/mem */ | ||
| 109 | pgprot_t (*phys_mem_access_prot)(struct file *file, | ||
| 110 | unsigned long pfn, | ||
| 111 | unsigned long size, | ||
| 112 | pgprot_t vma_prot); | ||
| 113 | |||
| 114 | /* Motherboard/chipset features. This is a kind of general purpose | ||
| 115 | * hook used to control some machine specific features (like reset | ||
| 116 | * lines, chip power control, etc...). | ||
| 117 | */ | ||
| 118 | long (*feature_call)(unsigned int feature, ...); | ||
| 119 | |||
| 120 | #ifdef CONFIG_SMP | ||
| 121 | /* functions for dealing with other cpus */ | ||
| 122 | struct smp_ops_t *smp_ops; | ||
| 123 | #endif /* CONFIG_SMP */ | ||
| 124 | |||
| 125 | #ifdef CONFIG_KEXEC | ||
| 126 | /* Called to shutdown machine specific hardware not already controlled | ||
| 127 | * by other drivers. | ||
| 128 | * XXX Should we move this one out of kexec scope? | ||
| 129 | */ | ||
| 130 | void (*machine_shutdown)(void); | ||
| 131 | |||
| 132 | /* Called to do the minimal shutdown needed to run a kexec'd kernel | ||
| 133 | * to run successfully. | ||
| 134 | * XXX Should we move this one out of kexec scope? | ||
| 135 | */ | ||
| 136 | void (*machine_crash_shutdown)(void); | ||
| 137 | |||
| 138 | /* Called to do what every setup is needed on image and the | ||
| 139 | * reboot code buffer. Returns 0 on success. | ||
| 140 | * Provide your own (maybe dummy) implementation if your platform | ||
| 141 | * claims to support kexec. | ||
| 142 | */ | ||
| 143 | int (*machine_kexec_prepare)(struct kimage *image); | ||
| 144 | |||
| 145 | /* Called to handle any machine specific cleanup on image */ | ||
| 146 | void (*machine_kexec_cleanup)(struct kimage *image); | ||
| 147 | |||
| 148 | /* Called to perform the _real_ kexec. | ||
| 149 | * Do NOT allocate memory or fail here. We are past the point of | ||
| 150 | * no return. | ||
| 151 | */ | ||
| 152 | void (*machine_kexec)(struct kimage *image); | ||
| 153 | #endif /* CONFIG_KEXEC */ | ||
| 154 | }; | ||
| 155 | |||
| 156 | extern struct machdep_calls ppc_md; | ||
| 157 | extern char cmd_line[COMMAND_LINE_SIZE]; | ||
| 158 | |||
| 159 | extern void setup_pci_ptrs(void); | ||
| 160 | |||
| 161 | #ifdef CONFIG_SMP | ||
| 162 | struct smp_ops_t { | ||
| 163 | void (*message_pass)(int target, int msg); | ||
| 164 | int (*probe)(void); | ||
| 165 | void (*kick_cpu)(int nr); | ||
| 166 | void (*setup_cpu)(int nr); | ||
| 167 | void (*space_timers)(int nr); | ||
| 168 | void (*take_timebase)(void); | ||
| 169 | void (*give_timebase)(void); | ||
| 170 | }; | ||
| 171 | |||
| 172 | /* Poor default implementations */ | ||
| 173 | extern void __devinit smp_generic_give_timebase(void); | ||
| 174 | extern void __devinit smp_generic_take_timebase(void); | ||
| 175 | #endif /* CONFIG_SMP */ | ||
| 176 | |||
| 177 | #endif /* _PPC_MACHDEP_H */ | ||
| 178 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/md.h b/include/asm-ppc/md.h deleted file mode 100644 index 9a9b6b42b4b4..000000000000 --- a/include/asm-ppc/md.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * md.h: High speed xor_block operation for RAID4/5 | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifdef __KERNEL__ | ||
| 7 | #ifndef __ASM_MD_H | ||
| 8 | #define __ASM_MD_H | ||
| 9 | |||
| 10 | /* #define HAVE_ARCH_XORBLOCK */ | ||
| 11 | |||
| 12 | #define MD_XORBLOCK_ALIGNMENT sizeof(long) | ||
| 13 | |||
| 14 | #endif /* __ASM_MD_H */ | ||
| 15 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mk48t59.h b/include/asm-ppc/mk48t59.h deleted file mode 100644 index 6a0ed6fc2d56..000000000000 --- a/include/asm-ppc/mk48t59.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Registers for the mk48t59 real-time-clock | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _PPC_MK48T59_H | ||
| 6 | #define _PPC_MK48T59_H | ||
| 7 | |||
| 8 | /* RTC Offsets */ | ||
| 9 | |||
| 10 | #define MK48T59_RTC_SECONDS 0x1FF9 | ||
| 11 | #define MK48T59_RTC_MINUTES 0x1FFA | ||
| 12 | #define MK48T59_RTC_HOURS 0x1FFB | ||
| 13 | #define MK48T59_RTC_DAY_OF_WEEK 0x1FFC | ||
| 14 | #define MK48T59_RTC_DAY_OF_MONTH 0x1FFD | ||
| 15 | #define MK48T59_RTC_MONTH 0x1FFE | ||
| 16 | #define MK48T59_RTC_YEAR 0x1FFF | ||
| 17 | |||
| 18 | #define MK48T59_RTC_CONTROLA 0x1FF8 | ||
| 19 | #define MK48T59_RTC_CA_WRITE 0x80 | ||
| 20 | #define MK48T59_RTC_CA_READ 0x40 | ||
| 21 | #define MK48T59_RTC_CA_CALIB_SIGN 0x20 | ||
| 22 | #define MK48T59_RTC_CA_CALIB_MASK 0x1f | ||
| 23 | |||
| 24 | #define MK48T59_RTC_CONTROLB 0x1FF9 | ||
| 25 | #define MK48T59_RTC_CB_STOP 0x80 | ||
| 26 | |||
| 27 | #endif /* _PPC_MK48T59_H */ | ||
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h deleted file mode 100644 index d76ef098ed37..000000000000 --- a/include/asm-ppc/mmu.h +++ /dev/null | |||
| @@ -1,444 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * PowerPC memory management structures | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifdef __KERNEL__ | ||
| 6 | #ifndef _PPC_MMU_H_ | ||
| 7 | #define _PPC_MMU_H_ | ||
| 8 | |||
| 9 | |||
| 10 | #ifndef __ASSEMBLY__ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Define physical address type. Machines using split size | ||
| 14 | * virtual/physical addressing like 32-bit virtual / 36-bit | ||
| 15 | * physical need a larger than native word size type. -Matt | ||
| 16 | */ | ||
| 17 | #ifndef CONFIG_PHYS_64BIT | ||
| 18 | #define PHYS_FMT "%.8lx" | ||
| 19 | #else | ||
| 20 | extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t); | ||
| 21 | #define PHYS_FMT "%16Lx" | ||
| 22 | #endif | ||
| 23 | |||
| 24 | typedef struct { | ||
| 25 | unsigned long id; | ||
| 26 | unsigned long vdso_base; | ||
| 27 | } mm_context_t; | ||
| 28 | |||
| 29 | /* Hardware Page Table Entry */ | ||
| 30 | typedef struct _PTE { | ||
| 31 | unsigned long v:1; /* Entry is valid */ | ||
| 32 | unsigned long vsid:24; /* Virtual segment identifier */ | ||
| 33 | unsigned long h:1; /* Hash algorithm indicator */ | ||
| 34 | unsigned long api:6; /* Abbreviated page index */ | ||
| 35 | unsigned long rpn:20; /* Real (physical) page number */ | ||
| 36 | unsigned long :3; /* Unused */ | ||
| 37 | unsigned long r:1; /* Referenced */ | ||
| 38 | unsigned long c:1; /* Changed */ | ||
| 39 | unsigned long w:1; /* Write-thru cache mode */ | ||
| 40 | unsigned long i:1; /* Cache inhibited */ | ||
| 41 | unsigned long m:1; /* Memory coherence */ | ||
| 42 | unsigned long g:1; /* Guarded */ | ||
| 43 | unsigned long :1; /* Unused */ | ||
| 44 | unsigned long pp:2; /* Page protection */ | ||
| 45 | } PTE; | ||
| 46 | |||
| 47 | /* Values for PP (assumes Ks=0, Kp=1) */ | ||
| 48 | #define PP_RWXX 0 /* Supervisor read/write, User none */ | ||
| 49 | #define PP_RWRX 1 /* Supervisor read/write, User read */ | ||
| 50 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ | ||
| 51 | #define PP_RXRX 3 /* Supervisor read, User read */ | ||
| 52 | |||
| 53 | /* Segment Register */ | ||
| 54 | typedef struct _SEGREG { | ||
| 55 | unsigned long t:1; /* Normal or I/O type */ | ||
| 56 | unsigned long ks:1; /* Supervisor 'key' (normally 0) */ | ||
| 57 | unsigned long kp:1; /* User 'key' (normally 1) */ | ||
| 58 | unsigned long n:1; /* No-execute */ | ||
| 59 | unsigned long :4; /* Unused */ | ||
| 60 | unsigned long vsid:24; /* Virtual Segment Identifier */ | ||
| 61 | } SEGREG; | ||
| 62 | |||
| 63 | /* Block Address Translation (BAT) Registers */ | ||
| 64 | typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ | ||
| 65 | unsigned long bepi:15; /* Effective page index (virtual address) */ | ||
| 66 | unsigned long :8; /* unused */ | ||
| 67 | unsigned long w:1; | ||
| 68 | unsigned long i:1; /* Cache inhibit */ | ||
| 69 | unsigned long m:1; /* Memory coherence */ | ||
| 70 | unsigned long ks:1; /* Supervisor key (normally 0) */ | ||
| 71 | unsigned long kp:1; /* User key (normally 1) */ | ||
| 72 | unsigned long pp:2; /* Page access protections */ | ||
| 73 | } P601_BATU; | ||
| 74 | |||
| 75 | typedef struct _BATU { /* Upper part of BAT (all except 601) */ | ||
| 76 | unsigned long bepi:15; /* Effective page index (virtual address) */ | ||
| 77 | unsigned long :4; /* Unused */ | ||
| 78 | unsigned long bl:11; /* Block size mask */ | ||
| 79 | unsigned long vs:1; /* Supervisor valid */ | ||
| 80 | unsigned long vp:1; /* User valid */ | ||
| 81 | } BATU; | ||
| 82 | |||
| 83 | typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ | ||
| 84 | unsigned long brpn:15; /* Real page index (physical address) */ | ||
| 85 | unsigned long :10; /* Unused */ | ||
| 86 | unsigned long v:1; /* Valid bit */ | ||
| 87 | unsigned long bl:6; /* Block size mask */ | ||
| 88 | } P601_BATL; | ||
| 89 | |||
| 90 | typedef struct _BATL { /* Lower part of BAT (all except 601) */ | ||
| 91 | unsigned long brpn:15; /* Real page index (physical address) */ | ||
| 92 | unsigned long :10; /* Unused */ | ||
| 93 | unsigned long w:1; /* Write-thru cache */ | ||
| 94 | unsigned long i:1; /* Cache inhibit */ | ||
| 95 | unsigned long m:1; /* Memory coherence */ | ||
| 96 | unsigned long g:1; /* Guarded (MBZ in IBAT) */ | ||
| 97 | unsigned long :1; /* Unused */ | ||
| 98 | unsigned long pp:2; /* Page access protections */ | ||
| 99 | } BATL; | ||
| 100 | |||
| 101 | typedef struct _BAT { | ||
| 102 | BATU batu; /* Upper register */ | ||
| 103 | BATL batl; /* Lower register */ | ||
| 104 | } BAT; | ||
| 105 | |||
| 106 | typedef struct _P601_BAT { | ||
| 107 | P601_BATU batu; /* Upper register */ | ||
| 108 | P601_BATL batl; /* Lower register */ | ||
| 109 | } P601_BAT; | ||
| 110 | |||
| 111 | #endif /* __ASSEMBLY__ */ | ||
| 112 | |||
| 113 | /* Block size masks */ | ||
| 114 | #define BL_128K 0x000 | ||
| 115 | #define BL_256K 0x001 | ||
| 116 | #define BL_512K 0x003 | ||
| 117 | #define BL_1M 0x007 | ||
| 118 | #define BL_2M 0x00F | ||
| 119 | #define BL_4M 0x01F | ||
| 120 | #define BL_8M 0x03F | ||
| 121 | #define BL_16M 0x07F | ||
| 122 | #define BL_32M 0x0FF | ||
| 123 | #define BL_64M 0x1FF | ||
| 124 | #define BL_128M 0x3FF | ||
| 125 | #define BL_256M 0x7FF | ||
| 126 | |||
| 127 | /* BAT Access Protection */ | ||
| 128 | #define BPP_XX 0x00 /* No access */ | ||
| 129 | #define BPP_RX 0x01 /* Read only */ | ||
| 130 | #define BPP_RW 0x02 /* Read/write */ | ||
| 131 | |||
| 132 | /* Control/status registers for the MPC8xx. | ||
| 133 | * A write operation to these registers causes serialized access. | ||
| 134 | * During software tablewalk, the registers used perform mask/shift-add | ||
| 135 | * operations when written/read. A TLB entry is created when the Mx_RPN | ||
| 136 | * is written, and the contents of several registers are used to | ||
| 137 | * create the entry. | ||
| 138 | */ | ||
| 139 | #define SPRN_MI_CTR 784 /* Instruction TLB control register */ | ||
| 140 | #define MI_GPM 0x80000000 /* Set domain manager mode */ | ||
| 141 | #define MI_PPM 0x40000000 /* Set subpage protection */ | ||
| 142 | #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ | ||
| 143 | #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ | ||
| 144 | #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ | ||
| 145 | #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ | ||
| 146 | #define MI_RESETVAL 0x00000000 /* Value of register at reset */ | ||
| 147 | |||
| 148 | /* These are the Ks and Kp from the PowerPC books. For proper operation, | ||
| 149 | * Ks = 0, Kp = 1. | ||
| 150 | */ | ||
| 151 | #define SPRN_MI_AP 786 | ||
| 152 | #define MI_Ks 0x80000000 /* Should not be set */ | ||
| 153 | #define MI_Kp 0x40000000 /* Should always be set */ | ||
| 154 | |||
| 155 | /* The effective page number register. When read, contains the information | ||
| 156 | * about the last instruction TLB miss. When MI_RPN is written, bits in | ||
| 157 | * this register are used to create the TLB entry. | ||
| 158 | */ | ||
| 159 | #define SPRN_MI_EPN 787 | ||
| 160 | #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ | ||
| 161 | #define MI_EVALID 0x00000200 /* Entry is valid */ | ||
| 162 | #define MI_ASIDMASK 0x0000000f /* ASID match value */ | ||
| 163 | /* Reset value is undefined */ | ||
| 164 | |||
| 165 | /* A "level 1" or "segment" or whatever you want to call it register. | ||
| 166 | * For the instruction TLB, it contains bits that get loaded into the | ||
| 167 | * TLB entry when the MI_RPN is written. | ||
| 168 | */ | ||
| 169 | #define SPRN_MI_TWC 789 | ||
| 170 | #define MI_APG 0x000001e0 /* Access protection group (0) */ | ||
| 171 | #define MI_GUARDED 0x00000010 /* Guarded storage */ | ||
| 172 | #define MI_PSMASK 0x0000000c /* Mask of page size bits */ | ||
| 173 | #define MI_PS8MEG 0x0000000c /* 8M page size */ | ||
| 174 | #define MI_PS512K 0x00000004 /* 512K page size */ | ||
| 175 | #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ | ||
| 176 | #define MI_SVALID 0x00000001 /* Segment entry is valid */ | ||
| 177 | /* Reset value is undefined */ | ||
| 178 | |||
| 179 | /* Real page number. Defined by the pte. Writing this register | ||
| 180 | * causes a TLB entry to be created for the instruction TLB, using | ||
| 181 | * additional information from the MI_EPN, and MI_TWC registers. | ||
| 182 | */ | ||
| 183 | #define SPRN_MI_RPN 790 | ||
| 184 | |||
| 185 | /* Define an RPN value for mapping kernel memory to large virtual | ||
| 186 | * pages for boot initialization. This has real page number of 0, | ||
| 187 | * large page size, shared page, cache enabled, and valid. | ||
| 188 | * Also mark all subpages valid and write access. | ||
| 189 | */ | ||
| 190 | #define MI_BOOTINIT 0x000001fd | ||
| 191 | |||
| 192 | #define SPRN_MD_CTR 792 /* Data TLB control register */ | ||
| 193 | #define MD_GPM 0x80000000 /* Set domain manager mode */ | ||
| 194 | #define MD_PPM 0x40000000 /* Set subpage protection */ | ||
| 195 | #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ | ||
| 196 | #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ | ||
| 197 | #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ | ||
| 198 | #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ | ||
| 199 | #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ | ||
| 200 | #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ | ||
| 201 | #define MD_RESETVAL 0x04000000 /* Value of register at reset */ | ||
| 202 | |||
| 203 | #define SPRN_M_CASID 793 /* Address space ID (context) to match */ | ||
| 204 | #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ | ||
| 205 | |||
| 206 | |||
| 207 | /* These are the Ks and Kp from the PowerPC books. For proper operation, | ||
| 208 | * Ks = 0, Kp = 1. | ||
| 209 | */ | ||
| 210 | #define SPRN_MD_AP 794 | ||
| 211 | #define MD_Ks 0x80000000 /* Should not be set */ | ||
| 212 | #define MD_Kp 0x40000000 /* Should always be set */ | ||
| 213 | |||
| 214 | /* The effective page number register. When read, contains the information | ||
| 215 | * about the last instruction TLB miss. When MD_RPN is written, bits in | ||
| 216 | * this register are used to create the TLB entry. | ||
| 217 | */ | ||
| 218 | #define SPRN_MD_EPN 795 | ||
| 219 | #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ | ||
| 220 | #define MD_EVALID 0x00000200 /* Entry is valid */ | ||
| 221 | #define MD_ASIDMASK 0x0000000f /* ASID match value */ | ||
| 222 | /* Reset value is undefined */ | ||
| 223 | |||
| 224 | /* The pointer to the base address of the first level page table. | ||
| 225 | * During a software tablewalk, reading this register provides the address | ||
| 226 | * of the entry associated with MD_EPN. | ||
| 227 | */ | ||
| 228 | #define SPRN_M_TWB 796 | ||
| 229 | #define M_L1TB 0xfffff000 /* Level 1 table base address */ | ||
| 230 | #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ | ||
| 231 | /* Reset value is undefined */ | ||
| 232 | |||
| 233 | /* A "level 1" or "segment" or whatever you want to call it register. | ||
| 234 | * For the data TLB, it contains bits that get loaded into the TLB entry | ||
| 235 | * when the MD_RPN is written. It is also provides the hardware assist | ||
| 236 | * for finding the PTE address during software tablewalk. | ||
| 237 | */ | ||
| 238 | #define SPRN_MD_TWC 797 | ||
| 239 | #define MD_L2TB 0xfffff000 /* Level 2 table base address */ | ||
| 240 | #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ | ||
| 241 | #define MD_APG 0x000001e0 /* Access protection group (0) */ | ||
| 242 | #define MD_GUARDED 0x00000010 /* Guarded storage */ | ||
| 243 | #define MD_PSMASK 0x0000000c /* Mask of page size bits */ | ||
| 244 | #define MD_PS8MEG 0x0000000c /* 8M page size */ | ||
| 245 | #define MD_PS512K 0x00000004 /* 512K page size */ | ||
| 246 | #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ | ||
| 247 | #define MD_WT 0x00000002 /* Use writethrough page attribute */ | ||
| 248 | #define MD_SVALID 0x00000001 /* Segment entry is valid */ | ||
| 249 | /* Reset value is undefined */ | ||
| 250 | |||
| 251 | |||
| 252 | /* Real page number. Defined by the pte. Writing this register | ||
| 253 | * causes a TLB entry to be created for the data TLB, using | ||
| 254 | * additional information from the MD_EPN, and MD_TWC registers. | ||
| 255 | */ | ||
| 256 | #define SPRN_MD_RPN 798 | ||
| 257 | |||
| 258 | /* This is a temporary storage register that could be used to save | ||
| 259 | * a processor working register during a tablewalk. | ||
| 260 | */ | ||
| 261 | #define SPRN_M_TW 799 | ||
| 262 | |||
| 263 | /* | ||
| 264 | * At present, all PowerPC 400-class processors share a similar TLB | ||
| 265 | * architecture. The instruction and data sides share a unified, | ||
| 266 | * 64-entry, fully-associative TLB which is maintained totally under | ||
| 267 | * software control. In addition, the instruction side has a | ||
| 268 | * hardware-managed, 4-entry, fully- associative TLB which serves as a | ||
| 269 | * first level to the shared TLB. These two TLBs are known as the UTLB | ||
| 270 | * and ITLB, respectively. | ||
| 271 | */ | ||
| 272 | |||
| 273 | #define PPC4XX_TLB_SIZE 64 | ||
| 274 | |||
| 275 | /* | ||
| 276 | * TLB entries are defined by a "high" tag portion and a "low" data | ||
| 277 | * portion. On all architectures, the data portion is 32-bits. | ||
| 278 | * | ||
| 279 | * TLB entries are managed entirely under software control by reading, | ||
| 280 | * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx | ||
| 281 | * instructions. | ||
| 282 | */ | ||
| 283 | |||
| 284 | #define TLB_LO 1 | ||
| 285 | #define TLB_HI 0 | ||
| 286 | |||
| 287 | #define TLB_DATA TLB_LO | ||
| 288 | #define TLB_TAG TLB_HI | ||
| 289 | |||
| 290 | /* Tag portion */ | ||
| 291 | |||
| 292 | #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ | ||
| 293 | #define TLB_PAGESZ_MASK 0x00000380 | ||
| 294 | #define TLB_PAGESZ(x) (((x) & 0x7) << 7) | ||
| 295 | #define PAGESZ_1K 0 | ||
| 296 | #define PAGESZ_4K 1 | ||
| 297 | #define PAGESZ_16K 2 | ||
| 298 | #define PAGESZ_64K 3 | ||
| 299 | #define PAGESZ_256K 4 | ||
| 300 | #define PAGESZ_1M 5 | ||
| 301 | #define PAGESZ_4M 6 | ||
| 302 | #define PAGESZ_16M 7 | ||
| 303 | #define TLB_VALID 0x00000040 /* Entry is valid */ | ||
| 304 | |||
| 305 | /* Data portion */ | ||
| 306 | |||
| 307 | #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ | ||
| 308 | #define TLB_PERM_MASK 0x00000300 | ||
| 309 | #define TLB_EX 0x00000200 /* Instruction execution allowed */ | ||
| 310 | #define TLB_WR 0x00000100 /* Writes permitted */ | ||
| 311 | #define TLB_ZSEL_MASK 0x000000F0 | ||
| 312 | #define TLB_ZSEL(x) (((x) & 0xF) << 4) | ||
| 313 | #define TLB_ATTR_MASK 0x0000000F | ||
| 314 | #define TLB_W 0x00000008 /* Caching is write-through */ | ||
| 315 | #define TLB_I 0x00000004 /* Caching is inhibited */ | ||
| 316 | #define TLB_M 0x00000002 /* Memory is coherent */ | ||
| 317 | #define TLB_G 0x00000001 /* Memory is guarded from prefetch */ | ||
| 318 | |||
| 319 | /* | ||
| 320 | * PPC440 support | ||
| 321 | */ | ||
| 322 | #define PPC44x_MMUCR_TID 0x000000ff | ||
| 323 | #define PPC44x_MMUCR_STS 0x00010000 | ||
| 324 | |||
| 325 | #define PPC44x_TLB_PAGEID 0 | ||
| 326 | #define PPC44x_TLB_XLAT 1 | ||
| 327 | #define PPC44x_TLB_ATTRIB 2 | ||
| 328 | |||
| 329 | /* Page identification fields */ | ||
| 330 | #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ | ||
| 331 | #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ | ||
| 332 | #define PPC44x_TLB_TS 0x00000100 /* Translation address space */ | ||
| 333 | #define PPC44x_TLB_1K 0x00000000 /* Page sizes */ | ||
| 334 | #define PPC44x_TLB_4K 0x00000010 | ||
| 335 | #define PPC44x_TLB_16K 0x00000020 | ||
| 336 | #define PPC44x_TLB_64K 0x00000030 | ||
| 337 | #define PPC44x_TLB_256K 0x00000040 | ||
| 338 | #define PPC44x_TLB_1M 0x00000050 | ||
| 339 | #define PPC44x_TLB_16M 0x00000070 | ||
| 340 | #define PPC44x_TLB_256M 0x00000090 | ||
| 341 | |||
| 342 | /* Translation fields */ | ||
| 343 | #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ | ||
| 344 | #define PPC44x_TLB_ERPN_MASK 0x0000000f | ||
| 345 | |||
| 346 | /* Storage attribute and access control fields */ | ||
| 347 | #define PPC44x_TLB_ATTR_MASK 0x0000ff80 | ||
| 348 | #define PPC44x_TLB_U0 0x00008000 /* User 0 */ | ||
| 349 | #define PPC44x_TLB_U1 0x00004000 /* User 1 */ | ||
| 350 | #define PPC44x_TLB_U2 0x00002000 /* User 2 */ | ||
| 351 | #define PPC44x_TLB_U3 0x00001000 /* User 3 */ | ||
| 352 | #define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ | ||
| 353 | #define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ | ||
| 354 | #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ | ||
| 355 | #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ | ||
| 356 | #define PPC44x_TLB_E 0x00000080 /* Memory is guarded */ | ||
| 357 | |||
| 358 | #define PPC44x_TLB_PERM_MASK 0x0000003f | ||
| 359 | #define PPC44x_TLB_UX 0x00000020 /* User execution */ | ||
| 360 | #define PPC44x_TLB_UW 0x00000010 /* User write */ | ||
| 361 | #define PPC44x_TLB_UR 0x00000008 /* User read */ | ||
| 362 | #define PPC44x_TLB_SX 0x00000004 /* Super execution */ | ||
| 363 | #define PPC44x_TLB_SW 0x00000002 /* Super write */ | ||
| 364 | #define PPC44x_TLB_SR 0x00000001 /* Super read */ | ||
| 365 | |||
| 366 | /* Book-E defined page sizes */ | ||
| 367 | #define BOOKE_PAGESZ_1K 0 | ||
| 368 | #define BOOKE_PAGESZ_4K 1 | ||
| 369 | #define BOOKE_PAGESZ_16K 2 | ||
| 370 | #define BOOKE_PAGESZ_64K 3 | ||
| 371 | #define BOOKE_PAGESZ_256K 4 | ||
| 372 | #define BOOKE_PAGESZ_1M 5 | ||
| 373 | #define BOOKE_PAGESZ_4M 6 | ||
| 374 | #define BOOKE_PAGESZ_16M 7 | ||
| 375 | #define BOOKE_PAGESZ_64M 8 | ||
| 376 | #define BOOKE_PAGESZ_256M 9 | ||
| 377 | #define BOOKE_PAGESZ_1GB 10 | ||
| 378 | #define BOOKE_PAGESZ_4GB 11 | ||
| 379 | #define BOOKE_PAGESZ_16GB 12 | ||
| 380 | #define BOOKE_PAGESZ_64GB 13 | ||
| 381 | #define BOOKE_PAGESZ_256GB 14 | ||
| 382 | #define BOOKE_PAGESZ_1TB 15 | ||
| 383 | |||
| 384 | #ifndef CONFIG_SERIAL_TEXT_DEBUG | ||
| 385 | #define PPC44x_EARLY_TLBS 1 | ||
| 386 | #else | ||
| 387 | #define PPC44x_EARLY_TLBS 2 | ||
| 388 | #endif | ||
| 389 | |||
| 390 | /* | ||
| 391 | * Freescale Book-E MMU support | ||
| 392 | */ | ||
| 393 | |||
| 394 | #define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) | ||
| 395 | #define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) | ||
| 396 | #define MAS0_NV(x) ((x) & 0x00000FFF) | ||
| 397 | |||
| 398 | #define MAS1_VALID 0x80000000 | ||
| 399 | #define MAS1_IPROT 0x40000000 | ||
| 400 | #define MAS1_TID(x) ((x << 16) & 0x3FFF0000) | ||
| 401 | #define MAS1_TS 0x00001000 | ||
| 402 | #define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) | ||
| 403 | |||
| 404 | #define MAS2_EPN 0xFFFFF000 | ||
| 405 | #define MAS2_X0 0x00000040 | ||
| 406 | #define MAS2_X1 0x00000020 | ||
| 407 | #define MAS2_W 0x00000010 | ||
| 408 | #define MAS2_I 0x00000008 | ||
| 409 | #define MAS2_M 0x00000004 | ||
| 410 | #define MAS2_G 0x00000002 | ||
| 411 | #define MAS2_E 0x00000001 | ||
| 412 | |||
| 413 | #define MAS3_RPN 0xFFFFF000 | ||
| 414 | #define MAS3_U0 0x00000200 | ||
| 415 | #define MAS3_U1 0x00000100 | ||
| 416 | #define MAS3_U2 0x00000080 | ||
| 417 | #define MAS3_U3 0x00000040 | ||
| 418 | #define MAS3_UX 0x00000020 | ||
| 419 | #define MAS3_SX 0x00000010 | ||
| 420 | #define MAS3_UW 0x00000008 | ||
| 421 | #define MAS3_SW 0x00000004 | ||
| 422 | #define MAS3_UR 0x00000002 | ||
| 423 | #define MAS3_SR 0x00000001 | ||
| 424 | |||
| 425 | #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) | ||
| 426 | #define MAS4_TIDDSEL 0x000F0000 | ||
| 427 | #define MAS4_TSIZED(x) MAS1_TSIZE(x) | ||
| 428 | #define MAS4_X0D 0x00000040 | ||
| 429 | #define MAS4_X1D 0x00000020 | ||
| 430 | #define MAS4_WD 0x00000010 | ||
| 431 | #define MAS4_ID 0x00000008 | ||
| 432 | #define MAS4_MD 0x00000004 | ||
| 433 | #define MAS4_GD 0x00000002 | ||
| 434 | #define MAS4_ED 0x00000001 | ||
| 435 | |||
| 436 | #define MAS6_SPID0 0x3FFF0000 | ||
| 437 | #define MAS6_SPID1 0x00007FFE | ||
| 438 | #define MAS6_SAS 0x00000001 | ||
| 439 | #define MAS6_SPID MAS6_SPID0 | ||
| 440 | |||
| 441 | #define MAS7_RPN 0xFFFFFFFF | ||
| 442 | |||
| 443 | #endif /* _PPC_MMU_H_ */ | ||
| 444 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h deleted file mode 100644 index 9f097e25b169..000000000000 --- a/include/asm-ppc/mmu_context.h +++ /dev/null | |||
| @@ -1,198 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | #ifndef __PPC_MMU_CONTEXT_H | ||
| 3 | #define __PPC_MMU_CONTEXT_H | ||
| 4 | |||
| 5 | #include <linux/bitops.h> | ||
| 6 | |||
| 7 | #include <asm/atomic.h> | ||
| 8 | #include <asm/mmu.h> | ||
| 9 | #include <asm/cputable.h> | ||
| 10 | #include <asm-generic/mm_hooks.h> | ||
| 11 | |||
| 12 | /* | ||
| 13 | * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs | ||
| 14 | * (virtual segment identifiers) for each context. Although the | ||
| 15 | * hardware supports 24-bit VSIDs, and thus >1 million contexts, | ||
| 16 | * we only use 32,768 of them. That is ample, since there can be | ||
| 17 | * at most around 30,000 tasks in the system anyway, and it means | ||
| 18 | * that we can use a bitmap to indicate which contexts are in use. | ||
| 19 | * Using a bitmap means that we entirely avoid all of the problems | ||
| 20 | * that we used to have when the context number overflowed, | ||
| 21 | * particularly on SMP systems. | ||
| 22 | * -- paulus. | ||
| 23 | */ | ||
| 24 | |||
| 25 | /* | ||
| 26 | * This function defines the mapping from contexts to VSIDs (virtual | ||
| 27 | * segment IDs). We use a skew on both the context and the high 4 bits | ||
| 28 | * of the 32-bit virtual address (the "effective segment ID") in order | ||
| 29 | * to spread out the entries in the MMU hash table. Note, if this | ||
| 30 | * function is changed then arch/ppc/mm/hashtable.S will have to be | ||
| 31 | * changed to correspond. | ||
| 32 | */ | ||
| 33 | #define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \ | ||
| 34 | & 0xffffff) | ||
| 35 | |||
| 36 | /* | ||
| 37 | The MPC8xx has only 16 contexts. We rotate through them on each | ||
| 38 | task switch. A better way would be to keep track of tasks that | ||
| 39 | own contexts, and implement an LRU usage. That way very active | ||
| 40 | tasks don't always have to pay the TLB reload overhead. The | ||
| 41 | kernel pages are mapped shared, so the kernel can run on behalf | ||
| 42 | of any task that makes a kernel entry. Shared does not mean they | ||
| 43 | are not protected, just that the ASID comparison is not performed. | ||
| 44 | -- Dan | ||
| 45 | |||
| 46 | The IBM4xx has 256 contexts, so we can just rotate through these | ||
| 47 | as a way of "switching" contexts. If the TID of the TLB is zero, | ||
| 48 | the PID/TID comparison is disabled, so we can use a TID of zero | ||
| 49 | to represent all kernel pages as shared among all contexts. | ||
| 50 | -- Dan | ||
| 51 | */ | ||
| 52 | |||
| 53 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | ||
| 54 | { | ||
| 55 | } | ||
| 56 | |||
| 57 | #ifdef CONFIG_8xx | ||
| 58 | #define NO_CONTEXT 16 | ||
| 59 | #define LAST_CONTEXT 15 | ||
| 60 | #define FIRST_CONTEXT 0 | ||
| 61 | |||
| 62 | #elif defined(CONFIG_4xx) | ||
| 63 | #define NO_CONTEXT 256 | ||
| 64 | #define LAST_CONTEXT 255 | ||
| 65 | #define FIRST_CONTEXT 1 | ||
| 66 | |||
| 67 | #else | ||
| 68 | |||
| 69 | /* PPC 6xx, 7xx CPUs */ | ||
| 70 | #define NO_CONTEXT ((unsigned long) -1) | ||
| 71 | #define LAST_CONTEXT 32767 | ||
| 72 | #define FIRST_CONTEXT 1 | ||
| 73 | #endif | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Set the current MMU context. | ||
| 77 | * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by | ||
| 78 | * loading up the segment registers for the user part of the address space. | ||
| 79 | * | ||
| 80 | * Since the PGD is immediately available, it is much faster to simply | ||
| 81 | * pass this along as a second parameter, which is required for 8xx and | ||
| 82 | * can be used for debugging on all processors (if you happen to have | ||
| 83 | * an Abatron). | ||
| 84 | */ | ||
| 85 | extern void set_context(unsigned long contextid, pgd_t *pgd); | ||
| 86 | |||
| 87 | /* | ||
| 88 | * Bitmap of contexts in use. | ||
| 89 | * The size of this bitmap is LAST_CONTEXT + 1 bits. | ||
| 90 | */ | ||
| 91 | extern unsigned long context_map[]; | ||
| 92 | |||
| 93 | /* | ||
| 94 | * This caches the next context number that we expect to be free. | ||
| 95 | * Its use is an optimization only, we can't rely on this context | ||
| 96 | * number to be free, but it usually will be. | ||
| 97 | */ | ||
| 98 | extern unsigned long next_mmu_context; | ||
| 99 | |||
| 100 | /* | ||
| 101 | * If we don't have sufficient contexts to give one to every task | ||
| 102 | * that could be in the system, we need to be able to steal contexts. | ||
| 103 | * These variables support that. | ||
| 104 | */ | ||
| 105 | #if LAST_CONTEXT < 30000 | ||
| 106 | #define FEW_CONTEXTS 1 | ||
| 107 | extern atomic_t nr_free_contexts; | ||
| 108 | extern struct mm_struct *context_mm[LAST_CONTEXT+1]; | ||
| 109 | extern void steal_context(void); | ||
| 110 | #endif | ||
| 111 | |||
| 112 | /* | ||
| 113 | * Get a new mmu context for the address space described by `mm'. | ||
| 114 | */ | ||
| 115 | static inline void get_mmu_context(struct mm_struct *mm) | ||
| 116 | { | ||
| 117 | unsigned long ctx; | ||
| 118 | |||
| 119 | if (mm->context.id != NO_CONTEXT) | ||
| 120 | return; | ||
| 121 | #ifdef FEW_CONTEXTS | ||
| 122 | while (atomic_dec_if_positive(&nr_free_contexts) < 0) | ||
| 123 | steal_context(); | ||
| 124 | #endif | ||
| 125 | ctx = next_mmu_context; | ||
| 126 | while (test_and_set_bit(ctx, context_map)) { | ||
| 127 | ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); | ||
| 128 | if (ctx > LAST_CONTEXT) | ||
| 129 | ctx = 0; | ||
| 130 | } | ||
| 131 | next_mmu_context = (ctx + 1) & LAST_CONTEXT; | ||
| 132 | mm->context.id = ctx; | ||
| 133 | #ifdef FEW_CONTEXTS | ||
| 134 | context_mm[ctx] = mm; | ||
| 135 | #endif | ||
| 136 | } | ||
| 137 | |||
| 138 | /* | ||
| 139 | * Set up the context for a new address space. | ||
| 140 | */ | ||
| 141 | static inline int init_new_context(struct task_struct *t, struct mm_struct *mm) | ||
| 142 | { | ||
| 143 | mm->context.id = NO_CONTEXT; | ||
| 144 | mm->context.vdso_base = 0; | ||
| 145 | return 0; | ||
| 146 | } | ||
| 147 | |||
| 148 | /* | ||
| 149 | * We're finished using the context for an address space. | ||
| 150 | */ | ||
| 151 | static inline void destroy_context(struct mm_struct *mm) | ||
| 152 | { | ||
| 153 | preempt_disable(); | ||
| 154 | if (mm->context.id != NO_CONTEXT) { | ||
| 155 | clear_bit(mm->context.id, context_map); | ||
| 156 | mm->context.id = NO_CONTEXT; | ||
| 157 | #ifdef FEW_CONTEXTS | ||
| 158 | atomic_inc(&nr_free_contexts); | ||
| 159 | #endif | ||
| 160 | } | ||
| 161 | preempt_enable(); | ||
| 162 | } | ||
| 163 | |||
| 164 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | ||
| 165 | struct task_struct *tsk) | ||
| 166 | { | ||
| 167 | #ifdef CONFIG_ALTIVEC | ||
| 168 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | ||
| 169 | asm volatile ("dssall;\n" | ||
| 170 | #ifndef CONFIG_POWER4 | ||
| 171 | "sync;\n" /* G4 needs a sync here, G5 apparently not */ | ||
| 172 | #endif | ||
| 173 | : : ); | ||
| 174 | #endif /* CONFIG_ALTIVEC */ | ||
| 175 | |||
| 176 | tsk->thread.pgdir = next->pgd; | ||
| 177 | |||
| 178 | /* No need to flush userspace segments if the mm doesnt change */ | ||
| 179 | if (prev == next) | ||
| 180 | return; | ||
| 181 | |||
| 182 | /* Setup new userspace context */ | ||
| 183 | get_mmu_context(next); | ||
| 184 | set_context(next->context.id, next->pgd); | ||
| 185 | } | ||
| 186 | |||
| 187 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
| 188 | |||
| 189 | /* | ||
| 190 | * After we have set current->mm to a new value, this activates | ||
| 191 | * the context for the new mm so we see the new mappings. | ||
| 192 | */ | ||
| 193 | #define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current) | ||
| 194 | |||
| 195 | extern void mmu_context_init(void); | ||
| 196 | |||
| 197 | #endif /* __PPC_MMU_CONTEXT_H */ | ||
| 198 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h deleted file mode 100644 index b30a6a3b5bd2..000000000000 --- a/include/asm-ppc/mpc10x.h +++ /dev/null | |||
| @@ -1,180 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem | ||
| 3 | * ctlr/EPIC/etc. | ||
| 4 | * | ||
| 5 | * Author: Mark A. Greer | ||
| 6 | * mgreer@mvista.com | ||
| 7 | * | ||
| 8 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | #ifndef __PPC_KERNEL_MPC10X_H | ||
| 14 | #define __PPC_KERNEL_MPC10X_H | ||
| 15 | |||
| 16 | #include <linux/pci_ids.h> | ||
| 17 | #include <asm/pci-bridge.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * The values here don't completely map everything but should work in most | ||
| 21 | * cases. | ||
| 22 | * | ||
| 23 | * MAP A (PReP Map) | ||
| 24 | * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff | ||
| 25 | * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff | ||
| 26 | * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 | ||
| 27 | * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) | ||
| 28 | * | ||
| 29 | * MAP B (CHRP Map) | ||
| 30 | * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff | ||
| 31 | * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff | ||
| 32 | * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 | ||
| 33 | * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) | ||
| 34 | */ | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Define the vendor/device IDs for the various bridges--should be added to | ||
| 38 | * <linux/pci_ids.h> | ||
| 39 | */ | ||
| 40 | #define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ | ||
| 41 | PCI_VENDOR_ID_MOTOROLA) | ||
| 42 | #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
| 43 | #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
| 44 | #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
| 45 | |||
| 46 | /* Define the type of map to use */ | ||
| 47 | #define MPC10X_MEM_MAP_A 1 | ||
| 48 | #define MPC10X_MEM_MAP_B 2 | ||
| 49 | |||
| 50 | /* Map A (PReP Map) Defines */ | ||
| 51 | #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 | ||
| 52 | #define MPC10X_MAPA_CNFG_DATA 0x80000cfc | ||
| 53 | |||
| 54 | #define MPC10X_MAPA_ISA_IO_BASE 0x80000000 | ||
| 55 | #define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 | ||
| 56 | #define MPC10X_MAPA_DRAM_OFFSET 0x80000000 | ||
| 57 | |||
| 58 | #define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0 | ||
| 59 | #define MPC10X_MAPA_PCI_IO_START 0x00000000 | ||
| 60 | #define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) | ||
| 61 | #define MPC10X_MAPA_PCI_MEM_START 0x00000000 | ||
| 62 | #define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) | ||
| 63 | |||
| 64 | #define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ | ||
| 65 | MPC10X_MAPA_PCI_MEM_START) | ||
| 66 | |||
| 67 | /* Map B (CHRP Map) Defines */ | ||
| 68 | #define MPC10X_MAPB_CNFG_ADDR 0xfec00000 | ||
| 69 | #define MPC10X_MAPB_CNFG_DATA 0xfee00000 | ||
| 70 | |||
| 71 | #define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 | ||
| 72 | #define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 | ||
| 73 | #define MPC10X_MAPB_DRAM_OFFSET 0x00000000 | ||
| 74 | |||
| 75 | #define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000 | ||
| 76 | #define MPC10X_MAPB_PCI_IO_START 0x00000000 | ||
| 77 | #define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) | ||
| 78 | #define MPC10X_MAPB_PCI_MEM_START 0x80000000 | ||
| 79 | #define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) | ||
| 80 | |||
| 81 | #define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ | ||
| 82 | MPC10X_MAPB_PCI_MEM_START) | ||
| 83 | |||
| 84 | /* Set hose members to values appropriate for the mem map used */ | ||
| 85 | #define MPC10X_SETUP_HOSE(hose, map) { \ | ||
| 86 | (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET; \ | ||
| 87 | (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START; \ | ||
| 88 | (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END; \ | ||
| 89 | (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START; \ | ||
| 90 | (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END; \ | ||
| 91 | (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE; \ | ||
| 92 | } | ||
| 93 | |||
| 94 | |||
| 95 | /* Miscellaneous Configuration register offsets */ | ||
| 96 | #define MPC10X_CFG_PIR_REG 0x09 | ||
| 97 | #define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 | ||
| 98 | #define MPC10X_CFG_PIR_AGENT 0x01 | ||
| 99 | |||
| 100 | #define MPC10X_CFG_EUMBBAR 0x78 | ||
| 101 | |||
| 102 | #define MPC10X_CFG_PICR1_REG 0xa8 | ||
| 103 | #define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 | ||
| 104 | #define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 | ||
| 105 | #define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 | ||
| 106 | #define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 | ||
| 107 | #define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 | ||
| 108 | |||
| 109 | #define MPC10X_CFG_PICR2_REG 0xac | ||
| 110 | #define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 | ||
| 111 | |||
| 112 | #define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 | ||
| 113 | #define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ | ||
| 114 | #define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ | ||
| 115 | #define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ | ||
| 116 | #define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ | ||
| 117 | #define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ | ||
| 118 | |||
| 119 | /* Define offsets for the memory controller registers in the config space */ | ||
| 120 | #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ | ||
| 121 | #define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ | ||
| 122 | #define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ | ||
| 123 | #define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ | ||
| 124 | |||
| 125 | #define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ | ||
| 126 | #define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ | ||
| 127 | #define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ | ||
| 128 | #define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ | ||
| 129 | |||
| 130 | #define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 | ||
| 131 | |||
| 132 | /* Define some offset in the EUMB */ | ||
| 133 | #define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ | ||
| 134 | |||
| 135 | #define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ | ||
| 136 | #define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ | ||
| 137 | #define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ | ||
| 138 | #define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ | ||
| 139 | #define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ | ||
| 140 | #define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ | ||
| 141 | #define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ | ||
| 142 | #define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ | ||
| 143 | #define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ | ||
| 144 | #define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ | ||
| 145 | #define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ | ||
| 146 | #define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ | ||
| 147 | #define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ | ||
| 148 | #define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ | ||
| 149 | #define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ | ||
| 150 | #define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ | ||
| 151 | |||
| 152 | /* | ||
| 153 | * Define some recommended places to put the EUMB regs. | ||
| 154 | * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff. | ||
| 155 | */ | ||
| 156 | extern unsigned long ioremap_base; | ||
| 157 | #define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE) | ||
| 158 | #define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE | ||
| 159 | |||
| 160 | enum ppc_sys_devices { | ||
| 161 | MPC10X_IIC1, | ||
| 162 | MPC10X_DMA0, | ||
| 163 | MPC10X_DMA1, | ||
| 164 | MPC10X_UART0, | ||
| 165 | MPC10X_UART1, | ||
| 166 | NUM_PPC_SYS_DEVS, | ||
| 167 | }; | ||
| 168 | |||
| 169 | int mpc10x_bridge_init(struct pci_controller *hose, | ||
| 170 | uint current_map, | ||
| 171 | uint new_map, | ||
| 172 | uint phys_eumb_base); | ||
| 173 | unsigned long mpc10x_get_mem_size(uint mem_map); | ||
| 174 | int mpc10x_enable_store_gathering(struct pci_controller *hose); | ||
| 175 | int mpc10x_disable_store_gathering(struct pci_controller *hose); | ||
| 176 | |||
| 177 | /* For MPC107 boards that use the built-in openpic */ | ||
| 178 | void mpc10x_set_openpic(void); | ||
| 179 | |||
| 180 | #endif /* __PPC_KERNEL_MPC10X_H */ | ||
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h deleted file mode 100644 index d9d21aa68ba3..000000000000 --- a/include/asm-ppc/mpc52xx.h +++ /dev/null | |||
| @@ -1,450 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/mpc52xx.h | ||
| 3 | * | ||
| 4 | * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips | ||
| 5 | * May need to be cleaned as the port goes on ... | ||
| 6 | * | ||
| 7 | * | ||
| 8 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | ||
| 9 | * | ||
| 10 | * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> | ||
| 11 | * for the 2.4 kernel. | ||
| 12 | * | ||
| 13 | * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com> | ||
| 14 | * Copyright (C) 2003 MontaVista, Software, Inc. | ||
| 15 | * | ||
| 16 | * This file is licensed under the terms of the GNU General Public License | ||
| 17 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 18 | * kind, whether express or implied. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_MPC52xx_H__ | ||
| 22 | #define __ASM_MPC52xx_H__ | ||
| 23 | |||
| 24 | #ifndef __ASSEMBLY__ | ||
| 25 | #include <asm/ppcboot.h> | ||
| 26 | #include <asm/types.h> | ||
| 27 | |||
| 28 | struct pt_regs; | ||
| 29 | #endif /* __ASSEMBLY__ */ | ||
| 30 | |||
| 31 | |||
| 32 | /* ======================================================================== */ | ||
| 33 | /* PPC Sys devices definition */ | ||
| 34 | /* ======================================================================== */ | ||
| 35 | |||
| 36 | enum ppc_sys_devices { | ||
| 37 | MPC52xx_MSCAN1, | ||
| 38 | MPC52xx_MSCAN2, | ||
| 39 | MPC52xx_SPI, | ||
| 40 | MPC52xx_USB, | ||
| 41 | MPC52xx_BDLC, | ||
| 42 | MPC52xx_PSC1, | ||
| 43 | MPC52xx_PSC2, | ||
| 44 | MPC52xx_PSC3, | ||
| 45 | MPC52xx_PSC4, | ||
| 46 | MPC52xx_PSC5, | ||
| 47 | MPC52xx_PSC6, | ||
| 48 | MPC52xx_FEC, | ||
| 49 | MPC52xx_ATA, | ||
| 50 | MPC52xx_I2C1, | ||
| 51 | MPC52xx_I2C2, | ||
| 52 | NUM_PPC_SYS_DEVS, | ||
| 53 | }; | ||
| 54 | |||
| 55 | |||
| 56 | /* ======================================================================== */ | ||
| 57 | /* Main registers/struct addresses */ | ||
| 58 | /* ======================================================================== */ | ||
| 59 | |||
| 60 | /* MBAR position */ | ||
| 61 | #define MPC52xx_MBAR 0xf0000000 /* Phys address */ | ||
| 62 | #define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */ | ||
| 63 | #define MPC52xx_MBAR_SIZE 0x00010000 | ||
| 64 | |||
| 65 | #define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x))) | ||
| 66 | #define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x))) | ||
| 67 | |||
| 68 | /* Registers zone offset/size */ | ||
| 69 | #define MPC52xx_MMAP_CTL_OFFSET 0x0000 | ||
| 70 | #define MPC52xx_MMAP_CTL_SIZE 0x068 | ||
| 71 | #define MPC52xx_SDRAM_OFFSET 0x0100 | ||
| 72 | #define MPC52xx_SDRAM_SIZE 0x010 | ||
| 73 | #define MPC52xx_CDM_OFFSET 0x0200 | ||
| 74 | #define MPC52xx_CDM_SIZE 0x038 | ||
| 75 | #define MPC52xx_INTR_OFFSET 0x0500 | ||
| 76 | #define MPC52xx_INTR_SIZE 0x04c | ||
| 77 | #define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4)) | ||
| 78 | #define MPC52xx_GPT_SIZE 0x010 | ||
| 79 | #define MPC52xx_RTC_OFFSET 0x0800 | ||
| 80 | #define MPC52xx_RTC_SIZE 0x024 | ||
| 81 | #define MPC52xx_GPIO_OFFSET 0x0b00 | ||
| 82 | #define MPC52xx_GPIO_SIZE 0x040 | ||
| 83 | #define MPC52xx_GPIO_WKUP_OFFSET 0x0c00 | ||
| 84 | #define MPC52xx_GPIO_WKUP_SIZE 0x028 | ||
| 85 | #define MPC52xx_PCI_OFFSET 0x0d00 | ||
| 86 | #define MPC52xx_PCI_SIZE 0x100 | ||
| 87 | #define MPC52xx_SDMA_OFFSET 0x1200 | ||
| 88 | #define MPC52xx_SDMA_SIZE 0x100 | ||
| 89 | #define MPC52xx_XLB_OFFSET 0x1f00 | ||
| 90 | #define MPC52xx_XLB_SIZE 0x100 | ||
| 91 | #define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00) | ||
| 92 | #define MPC52xx_PSC_SIZE 0x0a0 | ||
| 93 | |||
| 94 | /* SRAM used for SDMA */ | ||
| 95 | #define MPC52xx_SRAM_OFFSET 0x8000 | ||
| 96 | #define MPC52xx_SRAM_SIZE 0x4000 | ||
| 97 | |||
| 98 | |||
| 99 | /* ======================================================================== */ | ||
| 100 | /* IRQ mapping */ | ||
| 101 | /* ======================================================================== */ | ||
| 102 | /* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change | ||
| 103 | * this | ||
| 104 | */ | ||
| 105 | |||
| 106 | #define MPC52xx_CRIT_IRQ_NUM 4 | ||
| 107 | #define MPC52xx_MAIN_IRQ_NUM 17 | ||
| 108 | #define MPC52xx_SDMA_IRQ_NUM 17 | ||
| 109 | #define MPC52xx_PERP_IRQ_NUM 23 | ||
| 110 | |||
| 111 | #define MPC52xx_CRIT_IRQ_BASE 1 | ||
| 112 | #define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM) | ||
| 113 | #define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM) | ||
| 114 | #define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM) | ||
| 115 | |||
| 116 | #define MPC52xx_IRQ0 (MPC52xx_CRIT_IRQ_BASE + 0) | ||
| 117 | #define MPC52xx_SLICE_TIMER_0_IRQ (MPC52xx_CRIT_IRQ_BASE + 1) | ||
| 118 | #define MPC52xx_HI_INT_IRQ (MPC52xx_CRIT_IRQ_BASE + 2) | ||
| 119 | #define MPC52xx_CCS_IRQ (MPC52xx_CRIT_IRQ_BASE + 3) | ||
| 120 | |||
| 121 | #define MPC52xx_IRQ1 (MPC52xx_MAIN_IRQ_BASE + 1) | ||
| 122 | #define MPC52xx_IRQ2 (MPC52xx_MAIN_IRQ_BASE + 2) | ||
| 123 | #define MPC52xx_IRQ3 (MPC52xx_MAIN_IRQ_BASE + 3) | ||
| 124 | |||
| 125 | #define MPC52xx_SDMA_IRQ (MPC52xx_PERP_IRQ_BASE + 0) | ||
| 126 | #define MPC52xx_PSC1_IRQ (MPC52xx_PERP_IRQ_BASE + 1) | ||
| 127 | #define MPC52xx_PSC2_IRQ (MPC52xx_PERP_IRQ_BASE + 2) | ||
| 128 | #define MPC52xx_PSC3_IRQ (MPC52xx_PERP_IRQ_BASE + 3) | ||
| 129 | #define MPC52xx_PSC6_IRQ (MPC52xx_PERP_IRQ_BASE + 4) | ||
| 130 | #define MPC52xx_IRDA_IRQ (MPC52xx_PERP_IRQ_BASE + 4) | ||
| 131 | #define MPC52xx_FEC_IRQ (MPC52xx_PERP_IRQ_BASE + 5) | ||
| 132 | #define MPC52xx_USB_IRQ (MPC52xx_PERP_IRQ_BASE + 6) | ||
| 133 | #define MPC52xx_ATA_IRQ (MPC52xx_PERP_IRQ_BASE + 7) | ||
| 134 | #define MPC52xx_PCI_CNTRL_IRQ (MPC52xx_PERP_IRQ_BASE + 8) | ||
| 135 | #define MPC52xx_PCI_SCIRX_IRQ (MPC52xx_PERP_IRQ_BASE + 9) | ||
| 136 | #define MPC52xx_PCI_SCITX_IRQ (MPC52xx_PERP_IRQ_BASE + 10) | ||
| 137 | #define MPC52xx_PSC4_IRQ (MPC52xx_PERP_IRQ_BASE + 11) | ||
| 138 | #define MPC52xx_PSC5_IRQ (MPC52xx_PERP_IRQ_BASE + 12) | ||
| 139 | #define MPC52xx_SPI_MODF_IRQ (MPC52xx_PERP_IRQ_BASE + 13) | ||
| 140 | #define MPC52xx_SPI_SPIF_IRQ (MPC52xx_PERP_IRQ_BASE + 14) | ||
| 141 | #define MPC52xx_I2C1_IRQ (MPC52xx_PERP_IRQ_BASE + 15) | ||
| 142 | #define MPC52xx_I2C2_IRQ (MPC52xx_PERP_IRQ_BASE + 16) | ||
| 143 | #define MPC52xx_MSCAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17) | ||
| 144 | #define MPC52xx_MSCAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18) | ||
| 145 | #define MPC52xx_IR_RX_IRQ (MPC52xx_PERP_IRQ_BASE + 19) | ||
| 146 | #define MPC52xx_IR_TX_IRQ (MPC52xx_PERP_IRQ_BASE + 20) | ||
| 147 | #define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21) | ||
| 148 | #define MPC52xx_BDLC_IRQ (MPC52xx_PERP_IRQ_BASE + 22) | ||
| 149 | |||
| 150 | |||
| 151 | |||
| 152 | /* ======================================================================== */ | ||
| 153 | /* Structures mapping of some unit register set */ | ||
| 154 | /* ======================================================================== */ | ||
| 155 | |||
| 156 | #ifndef __ASSEMBLY__ | ||
| 157 | |||
| 158 | /* Memory Mapping Control */ | ||
| 159 | struct mpc52xx_mmap_ctl { | ||
| 160 | u32 mbar; /* MMAP_CTRL + 0x00 */ | ||
| 161 | |||
| 162 | u32 cs0_start; /* MMAP_CTRL + 0x04 */ | ||
| 163 | u32 cs0_stop; /* MMAP_CTRL + 0x08 */ | ||
| 164 | u32 cs1_start; /* MMAP_CTRL + 0x0c */ | ||
| 165 | u32 cs1_stop; /* MMAP_CTRL + 0x10 */ | ||
| 166 | u32 cs2_start; /* MMAP_CTRL + 0x14 */ | ||
| 167 | u32 cs2_stop; /* MMAP_CTRL + 0x18 */ | ||
| 168 | u32 cs3_start; /* MMAP_CTRL + 0x1c */ | ||
| 169 | u32 cs3_stop; /* MMAP_CTRL + 0x20 */ | ||
| 170 | u32 cs4_start; /* MMAP_CTRL + 0x24 */ | ||
| 171 | u32 cs4_stop; /* MMAP_CTRL + 0x28 */ | ||
| 172 | u32 cs5_start; /* MMAP_CTRL + 0x2c */ | ||
| 173 | u32 cs5_stop; /* MMAP_CTRL + 0x30 */ | ||
| 174 | |||
| 175 | u32 sdram0; /* MMAP_CTRL + 0x34 */ | ||
| 176 | u32 sdram1; /* MMAP_CTRL + 0X38 */ | ||
| 177 | |||
| 178 | u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */ | ||
| 179 | |||
| 180 | u32 boot_start; /* MMAP_CTRL + 0x4c */ | ||
| 181 | u32 boot_stop; /* MMAP_CTRL + 0x50 */ | ||
| 182 | |||
| 183 | u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */ | ||
| 184 | |||
| 185 | u32 cs6_start; /* MMAP_CTRL + 0x58 */ | ||
| 186 | u32 cs6_stop; /* MMAP_CTRL + 0x5c */ | ||
| 187 | u32 cs7_start; /* MMAP_CTRL + 0x60 */ | ||
| 188 | u32 cs7_stop; /* MMAP_CTRL + 0x64 */ | ||
| 189 | }; | ||
| 190 | |||
| 191 | /* SDRAM control */ | ||
| 192 | struct mpc52xx_sdram { | ||
| 193 | u32 mode; /* SDRAM + 0x00 */ | ||
| 194 | u32 ctrl; /* SDRAM + 0x04 */ | ||
| 195 | u32 config1; /* SDRAM + 0x08 */ | ||
| 196 | u32 config2; /* SDRAM + 0x0c */ | ||
| 197 | }; | ||
| 198 | |||
| 199 | /* Interrupt controller */ | ||
| 200 | struct mpc52xx_intr { | ||
| 201 | u32 per_mask; /* INTR + 0x00 */ | ||
| 202 | u32 per_pri1; /* INTR + 0x04 */ | ||
| 203 | u32 per_pri2; /* INTR + 0x08 */ | ||
| 204 | u32 per_pri3; /* INTR + 0x0c */ | ||
| 205 | u32 ctrl; /* INTR + 0x10 */ | ||
| 206 | u32 main_mask; /* INTR + 0x14 */ | ||
| 207 | u32 main_pri1; /* INTR + 0x18 */ | ||
| 208 | u32 main_pri2; /* INTR + 0x1c */ | ||
| 209 | u32 reserved1; /* INTR + 0x20 */ | ||
| 210 | u32 enc_status; /* INTR + 0x24 */ | ||
| 211 | u32 crit_status; /* INTR + 0x28 */ | ||
| 212 | u32 main_status; /* INTR + 0x2c */ | ||
| 213 | u32 per_status; /* INTR + 0x30 */ | ||
| 214 | u32 reserved2; /* INTR + 0x34 */ | ||
| 215 | u32 per_error; /* INTR + 0x38 */ | ||
| 216 | }; | ||
| 217 | |||
| 218 | /* SDMA */ | ||
| 219 | struct mpc52xx_sdma { | ||
| 220 | u32 taskBar; /* SDMA + 0x00 */ | ||
| 221 | u32 currentPointer; /* SDMA + 0x04 */ | ||
| 222 | u32 endPointer; /* SDMA + 0x08 */ | ||
| 223 | u32 variablePointer;/* SDMA + 0x0c */ | ||
| 224 | |||
| 225 | u8 IntVect1; /* SDMA + 0x10 */ | ||
| 226 | u8 IntVect2; /* SDMA + 0x11 */ | ||
| 227 | u16 PtdCntrl; /* SDMA + 0x12 */ | ||
| 228 | |||
| 229 | u32 IntPend; /* SDMA + 0x14 */ | ||
| 230 | u32 IntMask; /* SDMA + 0x18 */ | ||
| 231 | |||
| 232 | u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ | ||
| 233 | |||
| 234 | u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */ | ||
| 235 | |||
| 236 | u32 cReqSelect; /* SDMA + 0x5c */ | ||
| 237 | u32 task_size0; /* SDMA + 0x60 */ | ||
| 238 | u32 task_size1; /* SDMA + 0x64 */ | ||
| 239 | u32 MDEDebug; /* SDMA + 0x68 */ | ||
| 240 | u32 ADSDebug; /* SDMA + 0x6c */ | ||
| 241 | u32 Value1; /* SDMA + 0x70 */ | ||
| 242 | u32 Value2; /* SDMA + 0x74 */ | ||
| 243 | u32 Control; /* SDMA + 0x78 */ | ||
| 244 | u32 Status; /* SDMA + 0x7c */ | ||
| 245 | u32 PTDDebug; /* SDMA + 0x80 */ | ||
| 246 | }; | ||
| 247 | |||
| 248 | /* GPT */ | ||
| 249 | struct mpc52xx_gpt { | ||
| 250 | u32 mode; /* GPTx + 0x00 */ | ||
| 251 | u32 count; /* GPTx + 0x04 */ | ||
| 252 | u32 pwm; /* GPTx + 0x08 */ | ||
| 253 | u32 status; /* GPTx + 0X0c */ | ||
| 254 | }; | ||
| 255 | |||
| 256 | /* RTC */ | ||
| 257 | struct mpc52xx_rtc { | ||
| 258 | u32 time_set; /* RTC + 0x00 */ | ||
| 259 | u32 date_set; /* RTC + 0x04 */ | ||
| 260 | u32 stopwatch; /* RTC + 0x08 */ | ||
| 261 | u32 int_enable; /* RTC + 0x0c */ | ||
| 262 | u32 time; /* RTC + 0x10 */ | ||
| 263 | u32 date; /* RTC + 0x14 */ | ||
| 264 | u32 stopwatch_intr; /* RTC + 0x18 */ | ||
| 265 | u32 bus_error; /* RTC + 0x1c */ | ||
| 266 | u32 dividers; /* RTC + 0x20 */ | ||
| 267 | }; | ||
| 268 | |||
| 269 | /* GPIO */ | ||
| 270 | struct mpc52xx_gpio { | ||
| 271 | u32 port_config; /* GPIO + 0x00 */ | ||
| 272 | u32 simple_gpioe; /* GPIO + 0x04 */ | ||
| 273 | u32 simple_ode; /* GPIO + 0x08 */ | ||
| 274 | u32 simple_ddr; /* GPIO + 0x0c */ | ||
| 275 | u32 simple_dvo; /* GPIO + 0x10 */ | ||
| 276 | u32 simple_ival; /* GPIO + 0x14 */ | ||
| 277 | u8 outo_gpioe; /* GPIO + 0x18 */ | ||
| 278 | u8 reserved1[3]; /* GPIO + 0x19 */ | ||
| 279 | u8 outo_dvo; /* GPIO + 0x1c */ | ||
| 280 | u8 reserved2[3]; /* GPIO + 0x1d */ | ||
| 281 | u8 sint_gpioe; /* GPIO + 0x20 */ | ||
| 282 | u8 reserved3[3]; /* GPIO + 0x21 */ | ||
| 283 | u8 sint_ode; /* GPIO + 0x24 */ | ||
| 284 | u8 reserved4[3]; /* GPIO + 0x25 */ | ||
| 285 | u8 sint_ddr; /* GPIO + 0x28 */ | ||
| 286 | u8 reserved5[3]; /* GPIO + 0x29 */ | ||
| 287 | u8 sint_dvo; /* GPIO + 0x2c */ | ||
| 288 | u8 reserved6[3]; /* GPIO + 0x2d */ | ||
| 289 | u8 sint_inten; /* GPIO + 0x30 */ | ||
| 290 | u8 reserved7[3]; /* GPIO + 0x31 */ | ||
| 291 | u16 sint_itype; /* GPIO + 0x34 */ | ||
| 292 | u16 reserved8; /* GPIO + 0x36 */ | ||
| 293 | u8 gpio_control; /* GPIO + 0x38 */ | ||
| 294 | u8 reserved9[3]; /* GPIO + 0x39 */ | ||
| 295 | u8 sint_istat; /* GPIO + 0x3c */ | ||
| 296 | u8 sint_ival; /* GPIO + 0x3d */ | ||
| 297 | u8 bus_errs; /* GPIO + 0x3e */ | ||
| 298 | u8 reserved10; /* GPIO + 0x3f */ | ||
| 299 | }; | ||
| 300 | |||
| 301 | #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4 | ||
| 302 | #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5 | ||
| 303 | #define MPC52xx_GPIO_PCI_DIS (1<<15) | ||
| 304 | |||
| 305 | /* GPIO with WakeUp*/ | ||
| 306 | struct mpc52xx_gpio_wkup { | ||
| 307 | u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */ | ||
| 308 | u8 reserved1[3]; /* GPIO_WKUP + 0x03 */ | ||
| 309 | u8 wkup_ode; /* GPIO_WKUP + 0x04 */ | ||
| 310 | u8 reserved2[3]; /* GPIO_WKUP + 0x05 */ | ||
| 311 | u8 wkup_ddr; /* GPIO_WKUP + 0x08 */ | ||
| 312 | u8 reserved3[3]; /* GPIO_WKUP + 0x09 */ | ||
| 313 | u8 wkup_dvo; /* GPIO_WKUP + 0x0C */ | ||
| 314 | u8 reserved4[3]; /* GPIO_WKUP + 0x0D */ | ||
| 315 | u8 wkup_inten; /* GPIO_WKUP + 0x10 */ | ||
| 316 | u8 reserved5[3]; /* GPIO_WKUP + 0x11 */ | ||
| 317 | u8 wkup_iinten; /* GPIO_WKUP + 0x14 */ | ||
| 318 | u8 reserved6[3]; /* GPIO_WKUP + 0x15 */ | ||
| 319 | u16 wkup_itype; /* GPIO_WKUP + 0x18 */ | ||
| 320 | u8 reserved7[2]; /* GPIO_WKUP + 0x1A */ | ||
| 321 | u8 wkup_maste; /* GPIO_WKUP + 0x1C */ | ||
| 322 | u8 reserved8[3]; /* GPIO_WKUP + 0x1D */ | ||
| 323 | u8 wkup_ival; /* GPIO_WKUP + 0x20 */ | ||
| 324 | u8 reserved9[3]; /* GPIO_WKUP + 0x21 */ | ||
| 325 | u8 wkup_istat; /* GPIO_WKUP + 0x24 */ | ||
| 326 | u8 reserved10[3]; /* GPIO_WKUP + 0x25 */ | ||
| 327 | }; | ||
| 328 | |||
| 329 | /* XLB Bus control */ | ||
| 330 | struct mpc52xx_xlb { | ||
| 331 | u8 reserved[0x40]; | ||
| 332 | u32 config; /* XLB + 0x40 */ | ||
| 333 | u32 version; /* XLB + 0x44 */ | ||
| 334 | u32 status; /* XLB + 0x48 */ | ||
| 335 | u32 int_enable; /* XLB + 0x4c */ | ||
| 336 | u32 addr_capture; /* XLB + 0x50 */ | ||
| 337 | u32 bus_sig_capture; /* XLB + 0x54 */ | ||
| 338 | u32 addr_timeout; /* XLB + 0x58 */ | ||
| 339 | u32 data_timeout; /* XLB + 0x5c */ | ||
| 340 | u32 bus_act_timeout; /* XLB + 0x60 */ | ||
| 341 | u32 master_pri_enable; /* XLB + 0x64 */ | ||
| 342 | u32 master_priority; /* XLB + 0x68 */ | ||
| 343 | u32 base_address; /* XLB + 0x6c */ | ||
| 344 | u32 snoop_window; /* XLB + 0x70 */ | ||
| 345 | }; | ||
| 346 | |||
| 347 | #define MPC52xx_XLB_CFG_PLDIS (1 << 31) | ||
| 348 | #define MPC52xx_XLB_CFG_SNOOP (1 << 15) | ||
| 349 | |||
| 350 | /* Clock Distribution control */ | ||
| 351 | struct mpc52xx_cdm { | ||
| 352 | u32 jtag_id; /* CDM + 0x00 reg0 read only */ | ||
| 353 | u32 rstcfg; /* CDM + 0x04 reg1 read only */ | ||
| 354 | u32 breadcrumb; /* CDM + 0x08 reg2 */ | ||
| 355 | |||
| 356 | u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */ | ||
| 357 | u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */ | ||
| 358 | u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */ | ||
| 359 | u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */ | ||
| 360 | |||
| 361 | u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */ | ||
| 362 | u8 fd_enable; /* CDM + 0x11 reg4 byte1 */ | ||
| 363 | u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */ | ||
| 364 | |||
| 365 | u32 clk_enables; /* CDM + 0x14 reg5 */ | ||
| 366 | |||
| 367 | u8 osc_disable; /* CDM + 0x18 reg6 byte0 */ | ||
| 368 | u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */ | ||
| 369 | |||
| 370 | u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */ | ||
| 371 | u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */ | ||
| 372 | u8 reserved1; /* CDM + 0x1e reg7 byte2 */ | ||
| 373 | u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */ | ||
| 374 | |||
| 375 | u8 soft_reset; /* CDM + 0x20 u8 byte0 */ | ||
| 376 | u8 no_ckstp; /* CDM + 0x21 u8 byte0 */ | ||
| 377 | u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */ | ||
| 378 | |||
| 379 | u8 pll_lock; /* CDM + 0x24 reg9 byte0 */ | ||
| 380 | u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */ | ||
| 381 | u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */ | ||
| 382 | u8 reserved3; /* CDM + 0x27 reg9 byte3 */ | ||
| 383 | |||
| 384 | u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */ | ||
| 385 | u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */ | ||
| 386 | |||
| 387 | u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */ | ||
| 388 | u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */ | ||
| 389 | |||
| 390 | u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */ | ||
| 391 | u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */ | ||
| 392 | |||
| 393 | u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */ | ||
| 394 | u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */ | ||
| 395 | }; | ||
| 396 | |||
| 397 | #endif /* __ASSEMBLY__ */ | ||
| 398 | |||
| 399 | |||
| 400 | /* ========================================================================= */ | ||
| 401 | /* Prototypes for MPC52xx syslib */ | ||
| 402 | /* ========================================================================= */ | ||
| 403 | |||
| 404 | #ifndef __ASSEMBLY__ | ||
| 405 | |||
| 406 | extern void mpc52xx_init_irq(void); | ||
| 407 | extern int mpc52xx_get_irq(void); | ||
| 408 | |||
| 409 | extern unsigned long mpc52xx_find_end_of_memory(void); | ||
| 410 | extern void mpc52xx_set_bat(void); | ||
| 411 | extern void mpc52xx_map_io(void); | ||
| 412 | extern void mpc52xx_restart(char *cmd); | ||
| 413 | extern void mpc52xx_halt(void); | ||
| 414 | extern void mpc52xx_power_off(void); | ||
| 415 | extern void mpc52xx_progress(char *s, unsigned short hex); | ||
| 416 | extern void mpc52xx_calibrate_decr(void); | ||
| 417 | |||
| 418 | extern void mpc52xx_find_bridges(void); | ||
| 419 | |||
| 420 | extern void mpc52xx_setup_cpu(void); | ||
| 421 | |||
| 422 | |||
| 423 | |||
| 424 | /* Matching of PSC function */ | ||
| 425 | struct mpc52xx_psc_func { | ||
| 426 | int id; | ||
| 427 | char *func; | ||
| 428 | }; | ||
| 429 | |||
| 430 | extern int mpc52xx_match_psc_function(int psc_idx, const char *func); | ||
| 431 | extern struct mpc52xx_psc_func mpc52xx_psc_functions[]; | ||
| 432 | /* This array is to be defined in platform file */ | ||
| 433 | |||
| 434 | #endif /* __ASSEMBLY__ */ | ||
| 435 | |||
| 436 | |||
| 437 | /* ========================================================================= */ | ||
| 438 | /* Platform configuration */ | ||
| 439 | /* ========================================================================= */ | ||
| 440 | |||
| 441 | /* The U-Boot platform information struct */ | ||
| 442 | extern bd_t __res; | ||
| 443 | |||
| 444 | /* Platform options */ | ||
| 445 | #if defined(CONFIG_LITE5200) | ||
| 446 | #include <platforms/lite5200.h> | ||
| 447 | #endif | ||
| 448 | |||
| 449 | |||
| 450 | #endif /* __ASM_MPC52xx_H__ */ | ||
diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h deleted file mode 100644 index 39fcd02cd4e8..000000000000 --- a/include/asm-ppc/mpc52xx_psc.h +++ /dev/null | |||
| @@ -1,200 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/mpc52xx_psc.h | ||
| 3 | * | ||
| 4 | * Definitions of consts/structs to drive the Freescale MPC52xx OnChip | ||
| 5 | * PSCs. Theses are shared between multiple drivers since a PSC can be | ||
| 6 | * UART, AC97, IR, I2S, ... So this header is in asm-ppc. | ||
| 7 | * | ||
| 8 | * | ||
| 9 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | ||
| 10 | * | ||
| 11 | * Based/Extracted from some header of the 2.4 originally written by | ||
| 12 | * Dale Farnsworth <dfarnsworth@mvista.com> | ||
| 13 | * | ||
| 14 | * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> | ||
| 15 | * Copyright (C) 2003 MontaVista, Software, Inc. | ||
| 16 | * | ||
| 17 | * This file is licensed under the terms of the GNU General Public License | ||
| 18 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 19 | * kind, whether express or implied. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ASM_MPC52xx_PSC_H__ | ||
| 23 | #define __ASM_MPC52xx_PSC_H__ | ||
| 24 | |||
| 25 | #include <asm/types.h> | ||
| 26 | |||
| 27 | /* Max number of PSCs */ | ||
| 28 | #define MPC52xx_PSC_MAXNUM 6 | ||
| 29 | |||
| 30 | /* Programmable Serial Controller (PSC) status register bits */ | ||
| 31 | #define MPC52xx_PSC_SR_UNEX_RX 0x0001 | ||
| 32 | #define MPC52xx_PSC_SR_DATA_VAL 0x0002 | ||
| 33 | #define MPC52xx_PSC_SR_DATA_OVR 0x0004 | ||
| 34 | #define MPC52xx_PSC_SR_CMDSEND 0x0008 | ||
| 35 | #define MPC52xx_PSC_SR_CDE 0x0080 | ||
| 36 | #define MPC52xx_PSC_SR_RXRDY 0x0100 | ||
| 37 | #define MPC52xx_PSC_SR_RXFULL 0x0200 | ||
| 38 | #define MPC52xx_PSC_SR_TXRDY 0x0400 | ||
| 39 | #define MPC52xx_PSC_SR_TXEMP 0x0800 | ||
| 40 | #define MPC52xx_PSC_SR_OE 0x1000 | ||
| 41 | #define MPC52xx_PSC_SR_PE 0x2000 | ||
| 42 | #define MPC52xx_PSC_SR_FE 0x4000 | ||
| 43 | #define MPC52xx_PSC_SR_RB 0x8000 | ||
| 44 | |||
| 45 | /* PSC Command values */ | ||
| 46 | #define MPC52xx_PSC_RX_ENABLE 0x0001 | ||
| 47 | #define MPC52xx_PSC_RX_DISABLE 0x0002 | ||
| 48 | #define MPC52xx_PSC_TX_ENABLE 0x0004 | ||
| 49 | #define MPC52xx_PSC_TX_DISABLE 0x0008 | ||
| 50 | #define MPC52xx_PSC_SEL_MODE_REG_1 0x0010 | ||
| 51 | #define MPC52xx_PSC_RST_RX 0x0020 | ||
| 52 | #define MPC52xx_PSC_RST_TX 0x0030 | ||
| 53 | #define MPC52xx_PSC_RST_ERR_STAT 0x0040 | ||
| 54 | #define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050 | ||
| 55 | #define MPC52xx_PSC_START_BRK 0x0060 | ||
| 56 | #define MPC52xx_PSC_STOP_BRK 0x0070 | ||
| 57 | |||
| 58 | /* PSC TxRx FIFO status bits */ | ||
| 59 | #define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040 | ||
| 60 | #define MPC52xx_PSC_RXTX_FIFO_UF 0x0020 | ||
| 61 | #define MPC52xx_PSC_RXTX_FIFO_OF 0x0010 | ||
| 62 | #define MPC52xx_PSC_RXTX_FIFO_FR 0x0008 | ||
| 63 | #define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004 | ||
| 64 | #define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002 | ||
| 65 | #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 | ||
| 66 | |||
| 67 | /* PSC interrupt mask bits */ | ||
| 68 | #define MPC52xx_PSC_IMR_TXRDY 0x0100 | ||
| 69 | #define MPC52xx_PSC_IMR_RXRDY 0x0200 | ||
| 70 | #define MPC52xx_PSC_IMR_DB 0x0400 | ||
| 71 | #define MPC52xx_PSC_IMR_IPC 0x8000 | ||
| 72 | |||
| 73 | /* PSC input port change bit */ | ||
| 74 | #define MPC52xx_PSC_CTS 0x01 | ||
| 75 | #define MPC52xx_PSC_DCD 0x02 | ||
| 76 | #define MPC52xx_PSC_D_CTS 0x10 | ||
| 77 | #define MPC52xx_PSC_D_DCD 0x20 | ||
| 78 | |||
| 79 | /* PSC mode fields */ | ||
| 80 | #define MPC52xx_PSC_MODE_5_BITS 0x00 | ||
| 81 | #define MPC52xx_PSC_MODE_6_BITS 0x01 | ||
| 82 | #define MPC52xx_PSC_MODE_7_BITS 0x02 | ||
| 83 | #define MPC52xx_PSC_MODE_8_BITS 0x03 | ||
| 84 | #define MPC52xx_PSC_MODE_BITS_MASK 0x03 | ||
| 85 | #define MPC52xx_PSC_MODE_PAREVEN 0x00 | ||
| 86 | #define MPC52xx_PSC_MODE_PARODD 0x04 | ||
| 87 | #define MPC52xx_PSC_MODE_PARFORCE 0x08 | ||
| 88 | #define MPC52xx_PSC_MODE_PARNONE 0x10 | ||
| 89 | #define MPC52xx_PSC_MODE_ERR 0x20 | ||
| 90 | #define MPC52xx_PSC_MODE_FFULL 0x40 | ||
| 91 | #define MPC52xx_PSC_MODE_RXRTS 0x80 | ||
| 92 | |||
| 93 | #define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 | ||
| 94 | #define MPC52xx_PSC_MODE_ONE_STOP 0x07 | ||
| 95 | #define MPC52xx_PSC_MODE_TWO_STOP 0x0f | ||
| 96 | |||
| 97 | #define MPC52xx_PSC_RFNUM_MASK 0x01ff | ||
| 98 | |||
| 99 | |||
| 100 | /* Structure of the hardware registers */ | ||
| 101 | struct mpc52xx_psc { | ||
| 102 | u8 mode; /* PSC + 0x00 */ | ||
| 103 | u8 reserved0[3]; | ||
| 104 | union { /* PSC + 0x04 */ | ||
| 105 | u16 status; | ||
| 106 | u16 clock_select; | ||
| 107 | } sr_csr; | ||
| 108 | #define mpc52xx_psc_status sr_csr.status | ||
| 109 | #define mpc52xx_psc_clock_select sr_csr.clock_select | ||
| 110 | u16 reserved1; | ||
| 111 | u8 command; /* PSC + 0x08 */ | ||
| 112 | u8 reserved2[3]; | ||
| 113 | union { /* PSC + 0x0c */ | ||
| 114 | u8 buffer_8; | ||
| 115 | u16 buffer_16; | ||
| 116 | u32 buffer_32; | ||
| 117 | } buffer; | ||
| 118 | #define mpc52xx_psc_buffer_8 buffer.buffer_8 | ||
| 119 | #define mpc52xx_psc_buffer_16 buffer.buffer_16 | ||
| 120 | #define mpc52xx_psc_buffer_32 buffer.buffer_32 | ||
| 121 | union { /* PSC + 0x10 */ | ||
| 122 | u8 ipcr; | ||
| 123 | u8 acr; | ||
| 124 | } ipcr_acr; | ||
| 125 | #define mpc52xx_psc_ipcr ipcr_acr.ipcr | ||
| 126 | #define mpc52xx_psc_acr ipcr_acr.acr | ||
| 127 | u8 reserved3[3]; | ||
| 128 | union { /* PSC + 0x14 */ | ||
| 129 | u16 isr; | ||
| 130 | u16 imr; | ||
| 131 | } isr_imr; | ||
| 132 | #define mpc52xx_psc_isr isr_imr.isr | ||
| 133 | #define mpc52xx_psc_imr isr_imr.imr | ||
| 134 | u16 reserved4; | ||
| 135 | u8 ctur; /* PSC + 0x18 */ | ||
| 136 | u8 reserved5[3]; | ||
| 137 | u8 ctlr; /* PSC + 0x1c */ | ||
| 138 | u8 reserved6[3]; | ||
| 139 | u32 ccr; /* PSC + 0x20 */ | ||
| 140 | u32 ac97_slots; /* PSC + 0x24 */ | ||
| 141 | u32 ac97_cmd; /* PSC + 0x28 */ | ||
| 142 | u32 ac97_data; /* PSC + 0x2c */ | ||
| 143 | u8 ivr; /* PSC + 0x30 */ | ||
| 144 | u8 reserved8[3]; | ||
| 145 | u8 ip; /* PSC + 0x34 */ | ||
| 146 | u8 reserved9[3]; | ||
| 147 | u8 op1; /* PSC + 0x38 */ | ||
| 148 | u8 reserved10[3]; | ||
| 149 | u8 op0; /* PSC + 0x3c */ | ||
| 150 | u8 reserved11[3]; | ||
| 151 | u32 sicr; /* PSC + 0x40 */ | ||
| 152 | u8 ircr1; /* PSC + 0x44 */ | ||
| 153 | u8 reserved13[3]; | ||
| 154 | u8 ircr2; /* PSC + 0x44 */ | ||
| 155 | u8 reserved14[3]; | ||
| 156 | u8 irsdr; /* PSC + 0x4c */ | ||
| 157 | u8 reserved15[3]; | ||
| 158 | u8 irmdr; /* PSC + 0x50 */ | ||
| 159 | u8 reserved16[3]; | ||
| 160 | u8 irfdr; /* PSC + 0x54 */ | ||
| 161 | u8 reserved17[3]; | ||
| 162 | }; | ||
| 163 | |||
| 164 | struct mpc52xx_psc_fifo { | ||
| 165 | u16 rfnum; /* PSC + 0x58 */ | ||
| 166 | u16 reserved18; | ||
| 167 | u16 tfnum; /* PSC + 0x5c */ | ||
| 168 | u16 reserved19; | ||
| 169 | u32 rfdata; /* PSC + 0x60 */ | ||
| 170 | u16 rfstat; /* PSC + 0x64 */ | ||
| 171 | u16 reserved20; | ||
| 172 | u8 rfcntl; /* PSC + 0x68 */ | ||
| 173 | u8 reserved21[5]; | ||
| 174 | u16 rfalarm; /* PSC + 0x6e */ | ||
| 175 | u16 reserved22; | ||
| 176 | u16 rfrptr; /* PSC + 0x72 */ | ||
| 177 | u16 reserved23; | ||
| 178 | u16 rfwptr; /* PSC + 0x76 */ | ||
| 179 | u16 reserved24; | ||
| 180 | u16 rflrfptr; /* PSC + 0x7a */ | ||
| 181 | u16 reserved25; | ||
| 182 | u16 rflwfptr; /* PSC + 0x7e */ | ||
| 183 | u32 tfdata; /* PSC + 0x80 */ | ||
| 184 | u16 tfstat; /* PSC + 0x84 */ | ||
| 185 | u16 reserved26; | ||
| 186 | u8 tfcntl; /* PSC + 0x88 */ | ||
| 187 | u8 reserved27[5]; | ||
| 188 | u16 tfalarm; /* PSC + 0x8e */ | ||
| 189 | u16 reserved28; | ||
| 190 | u16 tfrptr; /* PSC + 0x92 */ | ||
| 191 | u16 reserved29; | ||
| 192 | u16 tfwptr; /* PSC + 0x96 */ | ||
| 193 | u16 reserved30; | ||
| 194 | u16 tflrfptr; /* PSC + 0x9a */ | ||
| 195 | u16 reserved31; | ||
| 196 | u16 tflwfptr; /* PSC + 0x9e */ | ||
| 197 | }; | ||
| 198 | |||
| 199 | |||
| 200 | #endif /* __ASM_MPC52xx_PSC_H__ */ | ||
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h deleted file mode 100644 index 402ba15c2e80..000000000000 --- a/include/asm-ppc/mpc8260.h +++ /dev/null | |||
| @@ -1,98 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Since there are many different boards and no standard configuration, | ||
| 3 | * we have a unique include file for each. Rather than change every | ||
| 4 | * file that has to include MPC8260 configuration, they all include | ||
| 5 | * this one and the configuration switching is done here. | ||
| 6 | */ | ||
| 7 | #ifdef __KERNEL__ | ||
| 8 | #ifndef __ASM_PPC_MPC8260_H__ | ||
| 9 | #define __ASM_PPC_MPC8260_H__ | ||
| 10 | |||
| 11 | |||
| 12 | #ifdef CONFIG_8260 | ||
| 13 | |||
| 14 | #ifdef CONFIG_EST8260 | ||
| 15 | #include <platforms/est8260.h> | ||
| 16 | #endif | ||
| 17 | |||
| 18 | #ifdef CONFIG_SBC82xx | ||
| 19 | #include <platforms/sbc82xx.h> | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #ifdef CONFIG_SBS8260 | ||
| 23 | #include <platforms/sbs8260.h> | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifdef CONFIG_RPX8260 | ||
| 27 | #include <platforms/rpx8260.h> | ||
| 28 | #endif | ||
| 29 | |||
| 30 | #ifdef CONFIG_WILLOW | ||
| 31 | #include <platforms/willow.h> | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #ifdef CONFIG_TQM8260 | ||
| 35 | #include <platforms/tqm8260.h> | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #ifdef CONFIG_PCI_8260 | ||
| 39 | #include <syslib/m82xx_pci.h> | ||
| 40 | #endif | ||
| 41 | |||
| 42 | /* Make sure the memory translation stuff is there if PCI not used. | ||
| 43 | */ | ||
| 44 | #ifndef _IO_BASE | ||
| 45 | #define _IO_BASE 0 | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef _ISA_MEM_BASE | ||
| 49 | #define _ISA_MEM_BASE 0 | ||
| 50 | #endif | ||
| 51 | |||
| 52 | #ifndef PCI_DRAM_OFFSET | ||
| 53 | #define PCI_DRAM_OFFSET 0 | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Map 256MB I/O region | ||
| 57 | */ | ||
| 58 | #ifndef IO_PHYS_ADDR | ||
| 59 | #define IO_PHYS_ADDR 0xe0000000 | ||
| 60 | #endif | ||
| 61 | #ifndef IO_VIRT_ADDR | ||
| 62 | #define IO_VIRT_ADDR IO_PHYS_ADDR | ||
| 63 | #endif | ||
| 64 | |||
| 65 | enum ppc_sys_devices { | ||
| 66 | MPC82xx_CPM_FCC1, | ||
| 67 | MPC82xx_CPM_FCC2, | ||
| 68 | MPC82xx_CPM_FCC3, | ||
| 69 | MPC82xx_CPM_I2C, | ||
| 70 | MPC82xx_CPM_SCC1, | ||
| 71 | MPC82xx_CPM_SCC2, | ||
| 72 | MPC82xx_CPM_SCC3, | ||
| 73 | MPC82xx_CPM_SCC4, | ||
| 74 | MPC82xx_CPM_SPI, | ||
| 75 | MPC82xx_CPM_MCC1, | ||
| 76 | MPC82xx_CPM_MCC2, | ||
| 77 | MPC82xx_CPM_SMC1, | ||
| 78 | MPC82xx_CPM_SMC2, | ||
| 79 | MPC82xx_CPM_USB, | ||
| 80 | MPC82xx_SEC1, | ||
| 81 | MPC82xx_MDIO_BB, | ||
| 82 | NUM_PPC_SYS_DEVS, | ||
| 83 | }; | ||
| 84 | |||
| 85 | #ifndef __ASSEMBLY__ | ||
| 86 | /* The "residual" data board information structure the boot loader | ||
| 87 | * hands to us. | ||
| 88 | */ | ||
| 89 | extern unsigned char __res[]; | ||
| 90 | #endif | ||
| 91 | |||
| 92 | #ifndef BOARD_CHIP_NAME | ||
| 93 | #define BOARD_CHIP_NAME "" | ||
| 94 | #endif | ||
| 95 | |||
| 96 | #endif /* CONFIG_8260 */ | ||
| 97 | #endif /* !__ASM_PPC_MPC8260_H__ */ | ||
| 98 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mpc8260_pci9.h b/include/asm-ppc/mpc8260_pci9.h deleted file mode 100644 index 9f7176881c56..000000000000 --- a/include/asm-ppc/mpc8260_pci9.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* include/asm-ppc/mpc8260_pci9.h | ||
| 2 | * | ||
| 3 | * Undefine the PCI read* and in* macros so we can define them as functions | ||
| 4 | * that implement the workaround for the MPC8260 device erratum PCI 9. | ||
| 5 | * | ||
| 6 | * This header file should only be included at the end of include/asm-ppc/io.h | ||
| 7 | * and never included directly anywhere else. | ||
| 8 | * | ||
| 9 | * Author: andy_lowe@mvista.com | ||
| 10 | * | ||
| 11 | * 2003 (c) MontaVista Software, Inc. This file is licensed under | ||
| 12 | * the terms of the GNU General Public License version 2. This program | ||
| 13 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 14 | * or implied. | ||
| 15 | */ | ||
| 16 | #ifndef _PPC_IO_H | ||
| 17 | #error "Do not include mpc8260_pci9.h directly." | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifdef __KERNEL__ | ||
| 21 | #ifndef __CONFIG_8260_PCI9_DEFS | ||
| 22 | #define __CONFIG_8260_PCI9_DEFS | ||
| 23 | |||
| 24 | #undef readb | ||
| 25 | #undef readw | ||
| 26 | #undef readl | ||
| 27 | #undef insb | ||
| 28 | #undef insw | ||
| 29 | #undef insl | ||
| 30 | #undef inb | ||
| 31 | #undef inw | ||
| 32 | #undef inl | ||
| 33 | #undef memcpy_fromio | ||
| 34 | |||
| 35 | extern int readb(volatile unsigned char *addr); | ||
| 36 | extern int readw(volatile unsigned short *addr); | ||
| 37 | extern unsigned readl(volatile unsigned *addr); | ||
| 38 | extern void insb(unsigned port, void *buf, int ns); | ||
| 39 | extern void insw(unsigned port, void *buf, int ns); | ||
| 40 | extern void insl(unsigned port, void *buf, int nl); | ||
| 41 | extern int inb(unsigned port); | ||
| 42 | extern int inw(unsigned port); | ||
| 43 | extern unsigned inl(unsigned port); | ||
| 44 | extern void *memcpy_fromio(void *dest, unsigned long src, size_t count); | ||
| 45 | |||
| 46 | #endif /* !__CONFIG_8260_PCI9_DEFS */ | ||
| 47 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h deleted file mode 100644 index b9e3060b0278..000000000000 --- a/include/asm-ppc/mpc8xx.h +++ /dev/null | |||
| @@ -1,122 +0,0 @@ | |||
| 1 | /* This is the single file included by all MPC8xx build options. | ||
| 2 | * Since there are many different boards and no standard configuration, | ||
| 3 | * we have a unique include file for each. Rather than change every | ||
| 4 | * file that has to include MPC8xx configuration, they all include | ||
| 5 | * this one and the configuration switching is done here. | ||
| 6 | */ | ||
| 7 | #ifdef __KERNEL__ | ||
| 8 | #ifndef __CONFIG_8xx_DEFS | ||
| 9 | #define __CONFIG_8xx_DEFS | ||
| 10 | |||
| 11 | |||
| 12 | #ifdef CONFIG_8xx | ||
| 13 | |||
| 14 | #ifdef CONFIG_MBX | ||
| 15 | #include <platforms/mbx.h> | ||
| 16 | #endif | ||
| 17 | |||
| 18 | #ifdef CONFIG_FADS | ||
| 19 | #include <platforms/fads.h> | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #ifdef CONFIG_RPXLITE | ||
| 23 | #include <platforms/rpxlite.h> | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifdef CONFIG_BSEIP | ||
| 27 | #include <platforms/bseip.h> | ||
| 28 | #endif | ||
| 29 | |||
| 30 | #ifdef CONFIG_RPXCLASSIC | ||
| 31 | #include <platforms/rpxclassic.h> | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #if defined(CONFIG_TQM8xxL) | ||
| 35 | #include <platforms/tqm8xx.h> | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) | ||
| 39 | #include <platforms/ivms8.h> | ||
| 40 | #endif | ||
| 41 | |||
| 42 | #if defined(CONFIG_HERMES_PRO) | ||
| 43 | #include <platforms/hermes.h> | ||
| 44 | #endif | ||
| 45 | |||
| 46 | #if defined(CONFIG_IP860) | ||
| 47 | #include <platforms/ip860.h> | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #if defined(CONFIG_LWMON) | ||
| 51 | #include <platforms/lwmon.h> | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #if defined(CONFIG_PCU_E) | ||
| 55 | #include <platforms/pcu_e.h> | ||
| 56 | #endif | ||
| 57 | |||
| 58 | #if defined(CONFIG_CCM) | ||
| 59 | #include <platforms/ccm.h> | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #if defined(CONFIG_LANTEC) | ||
| 63 | #include <platforms/lantec.h> | ||
| 64 | #endif | ||
| 65 | |||
| 66 | /* Currently, all 8xx boards that support a processor to PCI/ISA bridge | ||
| 67 | * use the same memory map. | ||
| 68 | */ | ||
| 69 | #if 0 | ||
| 70 | #if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR) | ||
| 71 | #define _IO_BASE PCI_ISA_IO_ADDR | ||
| 72 | #define _ISA_MEM_BASE PCI_ISA_MEM_ADDR | ||
| 73 | #define PCI_DRAM_OFFSET 0x80000000 | ||
| 74 | #else | ||
| 75 | #define _IO_BASE 0 | ||
| 76 | #define _ISA_MEM_BASE 0 | ||
| 77 | #define PCI_DRAM_OFFSET 0 | ||
| 78 | #endif | ||
| 79 | #else | ||
| 80 | #if !defined(_IO_BASE) /* defined in board specific header */ | ||
| 81 | #define _IO_BASE 0 | ||
| 82 | #endif | ||
| 83 | #define _ISA_MEM_BASE 0 | ||
| 84 | #define PCI_DRAM_OFFSET 0 | ||
| 85 | #endif | ||
| 86 | |||
| 87 | #ifndef __ASSEMBLY__ | ||
| 88 | /* The "residual" data board information structure the boot loader | ||
| 89 | * hands to us. | ||
| 90 | */ | ||
| 91 | extern unsigned char __res[]; | ||
| 92 | |||
| 93 | struct pt_regs; | ||
| 94 | |||
| 95 | enum ppc_sys_devices { | ||
| 96 | MPC8xx_CPM_FEC1, | ||
| 97 | MPC8xx_CPM_FEC2, | ||
| 98 | MPC8xx_CPM_I2C, | ||
| 99 | MPC8xx_CPM_SCC1, | ||
| 100 | MPC8xx_CPM_SCC2, | ||
| 101 | MPC8xx_CPM_SCC3, | ||
| 102 | MPC8xx_CPM_SCC4, | ||
| 103 | MPC8xx_CPM_SPI, | ||
| 104 | MPC8xx_CPM_MCC1, | ||
| 105 | MPC8xx_CPM_MCC2, | ||
| 106 | MPC8xx_CPM_SMC1, | ||
| 107 | MPC8xx_CPM_SMC2, | ||
| 108 | MPC8xx_CPM_USB, | ||
| 109 | MPC8xx_MDIO_FEC, | ||
| 110 | NUM_PPC_SYS_DEVS, | ||
| 111 | }; | ||
| 112 | |||
| 113 | #define PPC_PIN_SIZE (24 * 1024 * 1024) /* 24Mbytes of data pinned */ | ||
| 114 | |||
| 115 | #ifndef BOARD_CHIP_NAME | ||
| 116 | #define BOARD_CHIP_NAME "" | ||
| 117 | #endif | ||
| 118 | |||
| 119 | #endif /* !__ASSEMBLY__ */ | ||
| 120 | #endif /* CONFIG_8xx */ | ||
| 121 | #endif /* __CONFIG_8xx_DEFS */ | ||
| 122 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h deleted file mode 100644 index 2963d6aa3ea5..000000000000 --- a/include/asm-ppc/mv64x60.h +++ /dev/null | |||
| @@ -1,353 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/mv64x60.h | ||
| 3 | * | ||
| 4 | * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines. | ||
| 5 | * | ||
| 6 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
| 7 | * | ||
| 8 | * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | #ifndef __ASMPPC_MV64x60_H | ||
| 14 | #define __ASMPPC_MV64x60_H | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/pci.h> | ||
| 19 | #include <linux/slab.h> | ||
| 20 | |||
| 21 | #include <asm/byteorder.h> | ||
| 22 | #include <asm/io.h> | ||
| 23 | #include <asm/irq.h> | ||
| 24 | #include <asm/uaccess.h> | ||
| 25 | #include <asm/machdep.h> | ||
| 26 | #include <asm/pci-bridge.h> | ||
| 27 | #include <asm/mv64x60_defs.h> | ||
| 28 | |||
| 29 | struct platform_device; | ||
| 30 | |||
| 31 | extern u8 mv64x60_pci_exclude_bridge; | ||
| 32 | |||
| 33 | extern spinlock_t mv64x60_lock; | ||
| 34 | |||
| 35 | /* 32-bit Window table entry defines */ | ||
| 36 | #define MV64x60_CPU2MEM_0_WIN 0 | ||
| 37 | #define MV64x60_CPU2MEM_1_WIN 1 | ||
| 38 | #define MV64x60_CPU2MEM_2_WIN 2 | ||
| 39 | #define MV64x60_CPU2MEM_3_WIN 3 | ||
| 40 | #define MV64x60_CPU2DEV_0_WIN 4 | ||
| 41 | #define MV64x60_CPU2DEV_1_WIN 5 | ||
| 42 | #define MV64x60_CPU2DEV_2_WIN 6 | ||
| 43 | #define MV64x60_CPU2DEV_3_WIN 7 | ||
| 44 | #define MV64x60_CPU2BOOT_WIN 8 | ||
| 45 | #define MV64x60_CPU2PCI0_IO_WIN 9 | ||
| 46 | #define MV64x60_CPU2PCI0_MEM_0_WIN 10 | ||
| 47 | #define MV64x60_CPU2PCI0_MEM_1_WIN 11 | ||
| 48 | #define MV64x60_CPU2PCI0_MEM_2_WIN 12 | ||
| 49 | #define MV64x60_CPU2PCI0_MEM_3_WIN 13 | ||
| 50 | #define MV64x60_CPU2PCI1_IO_WIN 14 | ||
| 51 | #define MV64x60_CPU2PCI1_MEM_0_WIN 15 | ||
| 52 | #define MV64x60_CPU2PCI1_MEM_1_WIN 16 | ||
| 53 | #define MV64x60_CPU2PCI1_MEM_2_WIN 17 | ||
| 54 | #define MV64x60_CPU2PCI1_MEM_3_WIN 18 | ||
| 55 | #define MV64x60_CPU2SRAM_WIN 19 | ||
| 56 | #define MV64x60_CPU2PCI0_IO_REMAP_WIN 20 | ||
| 57 | #define MV64x60_CPU2PCI1_IO_REMAP_WIN 21 | ||
| 58 | #define MV64x60_CPU_PROT_0_WIN 22 | ||
| 59 | #define MV64x60_CPU_PROT_1_WIN 23 | ||
| 60 | #define MV64x60_CPU_PROT_2_WIN 24 | ||
| 61 | #define MV64x60_CPU_PROT_3_WIN 25 | ||
| 62 | #define MV64x60_CPU_SNOOP_0_WIN 26 | ||
| 63 | #define MV64x60_CPU_SNOOP_1_WIN 27 | ||
| 64 | #define MV64x60_CPU_SNOOP_2_WIN 28 | ||
| 65 | #define MV64x60_CPU_SNOOP_3_WIN 29 | ||
| 66 | #define MV64x60_PCI02MEM_REMAP_0_WIN 30 | ||
| 67 | #define MV64x60_PCI02MEM_REMAP_1_WIN 31 | ||
| 68 | #define MV64x60_PCI02MEM_REMAP_2_WIN 32 | ||
| 69 | #define MV64x60_PCI02MEM_REMAP_3_WIN 33 | ||
| 70 | #define MV64x60_PCI12MEM_REMAP_0_WIN 34 | ||
| 71 | #define MV64x60_PCI12MEM_REMAP_1_WIN 35 | ||
| 72 | #define MV64x60_PCI12MEM_REMAP_2_WIN 36 | ||
| 73 | #define MV64x60_PCI12MEM_REMAP_3_WIN 37 | ||
| 74 | #define MV64x60_ENET2MEM_0_WIN 38 | ||
| 75 | #define MV64x60_ENET2MEM_1_WIN 39 | ||
| 76 | #define MV64x60_ENET2MEM_2_WIN 40 | ||
| 77 | #define MV64x60_ENET2MEM_3_WIN 41 | ||
| 78 | #define MV64x60_ENET2MEM_4_WIN 42 | ||
| 79 | #define MV64x60_ENET2MEM_5_WIN 43 | ||
| 80 | #define MV64x60_MPSC2MEM_0_WIN 44 | ||
| 81 | #define MV64x60_MPSC2MEM_1_WIN 45 | ||
| 82 | #define MV64x60_MPSC2MEM_2_WIN 46 | ||
| 83 | #define MV64x60_MPSC2MEM_3_WIN 47 | ||
| 84 | #define MV64x60_IDMA2MEM_0_WIN 48 | ||
| 85 | #define MV64x60_IDMA2MEM_1_WIN 49 | ||
| 86 | #define MV64x60_IDMA2MEM_2_WIN 50 | ||
| 87 | #define MV64x60_IDMA2MEM_3_WIN 51 | ||
| 88 | #define MV64x60_IDMA2MEM_4_WIN 52 | ||
| 89 | #define MV64x60_IDMA2MEM_5_WIN 53 | ||
| 90 | #define MV64x60_IDMA2MEM_6_WIN 54 | ||
| 91 | #define MV64x60_IDMA2MEM_7_WIN 55 | ||
| 92 | |||
| 93 | #define MV64x60_32BIT_WIN_COUNT 56 | ||
| 94 | |||
| 95 | /* 64-bit Window table entry defines */ | ||
| 96 | #define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0 | ||
| 97 | #define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN 1 | ||
| 98 | #define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN 2 | ||
| 99 | #define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN 3 | ||
| 100 | #define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN 4 | ||
| 101 | #define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN 5 | ||
| 102 | #define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN 6 | ||
| 103 | #define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN 7 | ||
| 104 | #define MV64x60_PCI02MEM_ACC_CNTL_0_WIN 8 | ||
| 105 | #define MV64x60_PCI02MEM_ACC_CNTL_1_WIN 9 | ||
| 106 | #define MV64x60_PCI02MEM_ACC_CNTL_2_WIN 10 | ||
| 107 | #define MV64x60_PCI02MEM_ACC_CNTL_3_WIN 11 | ||
| 108 | #define MV64x60_PCI12MEM_ACC_CNTL_0_WIN 12 | ||
| 109 | #define MV64x60_PCI12MEM_ACC_CNTL_1_WIN 13 | ||
| 110 | #define MV64x60_PCI12MEM_ACC_CNTL_2_WIN 14 | ||
| 111 | #define MV64x60_PCI12MEM_ACC_CNTL_3_WIN 15 | ||
| 112 | #define MV64x60_PCI02MEM_SNOOP_0_WIN 16 | ||
| 113 | #define MV64x60_PCI02MEM_SNOOP_1_WIN 17 | ||
| 114 | #define MV64x60_PCI02MEM_SNOOP_2_WIN 18 | ||
| 115 | #define MV64x60_PCI02MEM_SNOOP_3_WIN 19 | ||
| 116 | #define MV64x60_PCI12MEM_SNOOP_0_WIN 20 | ||
| 117 | #define MV64x60_PCI12MEM_SNOOP_1_WIN 21 | ||
| 118 | #define MV64x60_PCI12MEM_SNOOP_2_WIN 22 | ||
| 119 | #define MV64x60_PCI12MEM_SNOOP_3_WIN 23 | ||
| 120 | |||
| 121 | #define MV64x60_64BIT_WIN_COUNT 24 | ||
| 122 | |||
| 123 | /* | ||
| 124 | * Define a structure that's used to pass in config information to the | ||
| 125 | * core routines. | ||
| 126 | */ | ||
| 127 | struct mv64x60_pci_window { | ||
| 128 | u32 cpu_base; | ||
| 129 | u32 pci_base_hi; | ||
| 130 | u32 pci_base_lo; | ||
| 131 | u32 size; | ||
| 132 | u32 swap; | ||
| 133 | }; | ||
| 134 | |||
| 135 | struct mv64x60_pci_info { | ||
| 136 | u8 enable_bus; /* allow access to this PCI bus? */ | ||
| 137 | |||
| 138 | struct mv64x60_pci_window pci_io; | ||
| 139 | struct mv64x60_pci_window pci_mem[3]; | ||
| 140 | |||
| 141 | u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS]; | ||
| 142 | u32 snoop_options[MV64x60_CPU2MEM_WINDOWS]; | ||
| 143 | u16 pci_cmd_bits; | ||
| 144 | u16 latency_timer; | ||
| 145 | }; | ||
| 146 | |||
| 147 | struct mv64x60_setup_info { | ||
| 148 | u32 phys_reg_base; | ||
| 149 | u32 window_preserve_mask_32_hi; | ||
| 150 | u32 window_preserve_mask_32_lo; | ||
| 151 | u32 window_preserve_mask_64; | ||
| 152 | |||
| 153 | u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS]; | ||
| 154 | u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS]; | ||
| 155 | u32 enet_options[MV64x60_CPU2MEM_WINDOWS]; | ||
| 156 | u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS]; | ||
| 157 | u32 idma_options[MV64x60_CPU2MEM_WINDOWS]; | ||
| 158 | |||
| 159 | struct mv64x60_pci_info pci_0; | ||
| 160 | struct mv64x60_pci_info pci_1; | ||
| 161 | }; | ||
| 162 | |||
| 163 | /* Define what the top bits in the extra member of a window entry means. */ | ||
| 164 | #define MV64x60_EXTRA_INVALID 0x00000000 | ||
| 165 | #define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000 | ||
| 166 | #define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000 | ||
| 167 | #define MV64x60_EXTRA_ENET_ENAB 0x30000000 | ||
| 168 | #define MV64x60_EXTRA_MPSC_ENAB 0x40000000 | ||
| 169 | #define MV64x60_EXTRA_IDMA_ENAB 0x50000000 | ||
| 170 | #define MV64x60_EXTRA_PCIACC_ENAB 0x60000000 | ||
| 171 | |||
| 172 | #define MV64x60_EXTRA_MASK 0xf0000000 | ||
| 173 | |||
| 174 | /* | ||
| 175 | * Define the 'handle' struct that will be passed between the 64x60 core | ||
| 176 | * code and the platform-specific code that will use it. The handle | ||
| 177 | * will contain pointers to chip-specific routines & information. | ||
| 178 | */ | ||
| 179 | struct mv64x60_32bit_window { | ||
| 180 | u32 base_reg; | ||
| 181 | u32 size_reg; | ||
| 182 | u8 base_bits; | ||
| 183 | u8 size_bits; | ||
| 184 | u32 (*get_from_field)(u32 val, u32 num_bits); | ||
| 185 | u32 (*map_to_field)(u32 val, u32 num_bits); | ||
| 186 | u32 extra; | ||
| 187 | }; | ||
| 188 | |||
| 189 | struct mv64x60_64bit_window { | ||
| 190 | u32 base_hi_reg; | ||
| 191 | u32 base_lo_reg; | ||
| 192 | u32 size_reg; | ||
| 193 | u8 base_lo_bits; | ||
| 194 | u8 size_bits; | ||
| 195 | u32 (*get_from_field)(u32 val, u32 num_bits); | ||
| 196 | u32 (*map_to_field)(u32 val, u32 num_bits); | ||
| 197 | u32 extra; | ||
| 198 | }; | ||
| 199 | |||
| 200 | typedef struct mv64x60_handle mv64x60_handle_t; | ||
| 201 | struct mv64x60_chip_info { | ||
| 202 | u32 (*translate_size)(u32 base, u32 size, u32 num_bits); | ||
| 203 | u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits); | ||
| 204 | void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus, | ||
| 205 | u32 window, u32 base); | ||
| 206 | void (*set_pci2regs_window)(struct mv64x60_handle *bh, | ||
| 207 | struct pci_controller *hose, u32 bus, u32 base); | ||
| 208 | u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window); | ||
| 209 | void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window); | ||
| 210 | void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window); | ||
| 211 | void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window); | ||
| 212 | void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window); | ||
| 213 | void (*disable_all_windows)(mv64x60_handle_t *bh, | ||
| 214 | struct mv64x60_setup_info *si); | ||
| 215 | void (*config_io2mem_windows)(mv64x60_handle_t *bh, | ||
| 216 | struct mv64x60_setup_info *si, | ||
| 217 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
| 218 | void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base); | ||
| 219 | void (*chip_specific_init)(mv64x60_handle_t *bh, | ||
| 220 | struct mv64x60_setup_info *si); | ||
| 221 | |||
| 222 | struct mv64x60_32bit_window *window_tab_32bit; | ||
| 223 | struct mv64x60_64bit_window *window_tab_64bit; | ||
| 224 | }; | ||
| 225 | |||
| 226 | struct mv64x60_handle { | ||
| 227 | u32 type; /* type of bridge */ | ||
| 228 | u32 rev; /* revision of bridge */ | ||
| 229 | void __iomem *v_base;/* virtual base addr of bridge regs */ | ||
| 230 | phys_addr_t p_base; /* physical base addr of bridge regs */ | ||
| 231 | |||
| 232 | u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/ | ||
| 233 | u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/ | ||
| 234 | |||
| 235 | u32 io_base_a; /* vaddr of pci 0's I/O space */ | ||
| 236 | u32 io_base_b; /* vaddr of pci 1's I/O space */ | ||
| 237 | |||
| 238 | struct pci_controller *hose_a; | ||
| 239 | struct pci_controller *hose_b; | ||
| 240 | |||
| 241 | struct mv64x60_chip_info *ci; /* chip/bridge-specific info */ | ||
| 242 | }; | ||
| 243 | |||
| 244 | |||
| 245 | /* Define I/O routines for accessing registers on the 64x60 bridge. */ | ||
| 246 | extern inline void | ||
| 247 | mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) { | ||
| 248 | ulong flags; | ||
| 249 | |||
| 250 | spin_lock_irqsave(&mv64x60_lock, flags); | ||
| 251 | out_le32(bh->v_base + offset, val); | ||
| 252 | spin_unlock_irqrestore(&mv64x60_lock, flags); | ||
| 253 | } | ||
| 254 | |||
| 255 | extern inline u32 | ||
| 256 | mv64x60_read(struct mv64x60_handle *bh, u32 offset) { | ||
| 257 | ulong flags; | ||
| 258 | u32 reg; | ||
| 259 | |||
| 260 | spin_lock_irqsave(&mv64x60_lock, flags); | ||
| 261 | reg = in_le32(bh->v_base + offset); | ||
| 262 | spin_unlock_irqrestore(&mv64x60_lock, flags); | ||
| 263 | return reg; | ||
| 264 | } | ||
| 265 | |||
| 266 | extern inline void | ||
| 267 | mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask) | ||
| 268 | { | ||
| 269 | u32 reg; | ||
| 270 | ulong flags; | ||
| 271 | |||
| 272 | spin_lock_irqsave(&mv64x60_lock, flags); | ||
| 273 | reg = in_le32(bh->v_base + offs) & (~mask); | ||
| 274 | reg |= data & mask; | ||
| 275 | out_le32(bh->v_base + offs, reg); | ||
| 276 | spin_unlock_irqrestore(&mv64x60_lock, flags); | ||
| 277 | } | ||
| 278 | |||
| 279 | #define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits) | ||
| 280 | #define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits) | ||
| 281 | |||
| 282 | #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) | ||
| 283 | #define MV64XXX_DEV_NAME "mv64xxx" | ||
| 284 | |||
| 285 | struct mv64xxx_pdata { | ||
| 286 | u32 hs_reg_valid; | ||
| 287 | }; | ||
| 288 | #endif | ||
| 289 | |||
| 290 | /* Externally visible function prototypes */ | ||
| 291 | int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si); | ||
| 292 | u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type); | ||
| 293 | void mv64x60_early_init(struct mv64x60_handle *bh, | ||
| 294 | struct mv64x60_setup_info *si); | ||
| 295 | void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, | ||
| 296 | u32 cfg_data, struct pci_controller **hose); | ||
| 297 | int mv64x60_get_type(struct mv64x60_handle *bh); | ||
| 298 | int mv64x60_setup_for_chip(struct mv64x60_handle *bh); | ||
| 299 | void __iomem *mv64x60_get_bridge_vbase(void); | ||
| 300 | u32 mv64x60_get_bridge_type(void); | ||
| 301 | u32 mv64x60_get_bridge_rev(void); | ||
| 302 | void mv64x60_get_mem_windows(struct mv64x60_handle *bh, | ||
| 303 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
| 304 | void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, | ||
| 305 | struct mv64x60_setup_info *si, | ||
| 306 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
| 307 | void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, | ||
| 308 | struct mv64x60_pci_info *pi, u32 bus); | ||
| 309 | void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, | ||
| 310 | struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus, | ||
| 311 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
| 312 | void mv64x60_config_resources(struct pci_controller *hose, | ||
| 313 | struct mv64x60_pci_info *pi, u32 io_base); | ||
| 314 | void mv64x60_config_pci_params(struct pci_controller *hose, | ||
| 315 | struct mv64x60_pci_info *pi); | ||
| 316 | void mv64x60_pd_fixup(struct mv64x60_handle *bh, | ||
| 317 | struct platform_device *pd_devs[], u32 entries); | ||
| 318 | void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, | ||
| 319 | u32 *base, u32 *size); | ||
| 320 | void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base, | ||
| 321 | u32 size, u32 other_bits); | ||
| 322 | void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, | ||
| 323 | u32 *base_hi, u32 *base_lo, u32 *size); | ||
| 324 | void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, | ||
| 325 | u32 base_hi, u32 base_lo, u32 size, u32 other_bits); | ||
| 326 | void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus); | ||
| 327 | int mv64x60_pci_exclude_device(u8 bus, u8 devfn); | ||
| 328 | |||
| 329 | |||
| 330 | void gt64260_init_irq(void); | ||
| 331 | int gt64260_get_irq(void); | ||
| 332 | void mv64360_init_irq(void); | ||
| 333 | int mv64360_get_irq(void); | ||
| 334 | |||
| 335 | u32 mv64x60_mask(u32 val, u32 num_bits); | ||
| 336 | u32 mv64x60_shift_left(u32 val, u32 num_bits); | ||
| 337 | u32 mv64x60_shift_right(u32 val, u32 num_bits); | ||
| 338 | u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh, | ||
| 339 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
| 340 | |||
| 341 | void mv64x60_progress_init(u32 base); | ||
| 342 | void mv64x60_mpsc_progress(char *s, unsigned short hex); | ||
| 343 | |||
| 344 | extern struct mv64x60_32bit_window | ||
| 345 | gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT]; | ||
| 346 | extern struct mv64x60_64bit_window | ||
| 347 | gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT]; | ||
| 348 | extern struct mv64x60_32bit_window | ||
| 349 | mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT]; | ||
| 350 | extern struct mv64x60_64bit_window | ||
| 351 | mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT]; | ||
| 352 | |||
| 353 | #endif /* __ASMPPC_MV64x60_H */ | ||
diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h deleted file mode 100644 index 5b0704a3e6ea..000000000000 --- a/include/asm-ppc/mv64x60_defs.h +++ /dev/null | |||
| @@ -1,976 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/mv64x60_defs.h | ||
| 3 | * | ||
| 4 | * Register definitions for the Marvell/Galileo GT64260, MV64360, etc. | ||
| 5 | * host bridges. | ||
| 6 | * | ||
| 7 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
| 8 | * | ||
| 9 | * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 10 | * the terms of the GNU General Public License version 2. This program | ||
| 11 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 12 | * or implied. | ||
| 13 | */ | ||
| 14 | #ifndef __ASMPPC_MV64x60_DEFS_H | ||
| 15 | #define __ASMPPC_MV64x60_DEFS_H | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Define the Marvell bridges that are supported | ||
| 19 | */ | ||
| 20 | #define MV64x60_TYPE_INVALID 0 | ||
| 21 | #define MV64x60_TYPE_GT64260A 1 | ||
| 22 | #define MV64x60_TYPE_GT64260B 2 | ||
| 23 | #define MV64x60_TYPE_MV64360 3 | ||
| 24 | #define MV64x60_TYPE_MV64361 4 | ||
| 25 | #define MV64x60_TYPE_MV64362 5 | ||
| 26 | #define MV64x60_TYPE_MV64460 6 | ||
| 27 | |||
| 28 | |||
| 29 | /* Revisions of each supported chip */ | ||
| 30 | #define GT64260_REV_A 0x10 | ||
| 31 | #define GT64260_REV_B 0x20 | ||
| 32 | #define MV64360 0x01 | ||
| 33 | #define MV64460 0x01 | ||
| 34 | |||
| 35 | /* Minimum window size supported by 64260 is 1MB */ | ||
| 36 | #define GT64260_WINDOW_SIZE_MIN 0x00100000 | ||
| 37 | #define MV64360_WINDOW_SIZE_MIN 0x00010000 | ||
| 38 | |||
| 39 | #define MV64x60_TCLK_FREQ_MAX 133333333U | ||
| 40 | |||
| 41 | /* IRQ's for embedded controllers */ | ||
| 42 | #define MV64x60_IRQ_DEV 1 | ||
| 43 | #define MV64x60_IRQ_CPU_ERR 3 | ||
| 44 | #define MV64x60_IRQ_TIMER_0_1 8 | ||
| 45 | #define MV64x60_IRQ_TIMER_2_3 9 | ||
| 46 | #define MV64x60_IRQ_TIMER_4_5 10 | ||
| 47 | #define MV64x60_IRQ_TIMER_6_7 11 | ||
| 48 | #define MV64x60_IRQ_P1_GPP_0_7 24 | ||
| 49 | #define MV64x60_IRQ_P1_GPP_8_15 25 | ||
| 50 | #define MV64x60_IRQ_P1_GPP_16_23 26 | ||
| 51 | #define MV64x60_IRQ_P1_GPP_24_31 27 | ||
| 52 | #define MV64x60_IRQ_DOORBELL 28 | ||
| 53 | #define MV64x60_IRQ_ETH_0 32 | ||
| 54 | #define MV64x60_IRQ_ETH_1 33 | ||
| 55 | #define MV64x60_IRQ_ETH_2 34 | ||
| 56 | #define MV64x60_IRQ_SDMA_0 36 | ||
| 57 | #define MV64x60_IRQ_I2C 37 | ||
| 58 | #define MV64x60_IRQ_BRG 39 | ||
| 59 | #define MV64x60_IRQ_MPSC_0 40 | ||
| 60 | #define MV64x60_IRQ_MPSC_1 42 | ||
| 61 | #define MV64x60_IRQ_COMM 43 | ||
| 62 | #define MV64x60_IRQ_P0_GPP_0_7 56 | ||
| 63 | #define MV64x60_IRQ_P0_GPP_8_15 57 | ||
| 64 | #define MV64x60_IRQ_P0_GPP_16_23 58 | ||
| 65 | #define MV64x60_IRQ_P0_GPP_24_31 59 | ||
| 66 | |||
| 67 | #define MV64360_IRQ_PCI0 12 | ||
| 68 | #define MV64360_IRQ_SRAM_PAR_ERR 13 | ||
| 69 | #define MV64360_IRQ_PCI1 16 | ||
| 70 | #define MV64360_IRQ_SDMA_1 38 | ||
| 71 | |||
| 72 | #define MV64x60_IRQ_GPP0 64 | ||
| 73 | #define MV64x60_IRQ_GPP1 65 | ||
| 74 | #define MV64x60_IRQ_GPP2 66 | ||
| 75 | #define MV64x60_IRQ_GPP3 67 | ||
| 76 | #define MV64x60_IRQ_GPP4 68 | ||
| 77 | #define MV64x60_IRQ_GPP5 69 | ||
| 78 | #define MV64x60_IRQ_GPP6 70 | ||
| 79 | #define MV64x60_IRQ_GPP7 71 | ||
| 80 | #define MV64x60_IRQ_GPP8 72 | ||
| 81 | #define MV64x60_IRQ_GPP9 73 | ||
| 82 | #define MV64x60_IRQ_GPP10 74 | ||
| 83 | #define MV64x60_IRQ_GPP11 75 | ||
| 84 | #define MV64x60_IRQ_GPP12 76 | ||
| 85 | #define MV64x60_IRQ_GPP13 77 | ||
| 86 | #define MV64x60_IRQ_GPP14 78 | ||
| 87 | #define MV64x60_IRQ_GPP15 79 | ||
| 88 | #define MV64x60_IRQ_GPP16 80 | ||
| 89 | #define MV64x60_IRQ_GPP17 81 | ||
| 90 | #define MV64x60_IRQ_GPP18 82 | ||
| 91 | #define MV64x60_IRQ_GPP19 83 | ||
| 92 | #define MV64x60_IRQ_GPP20 84 | ||
| 93 | #define MV64x60_IRQ_GPP21 85 | ||
| 94 | #define MV64x60_IRQ_GPP22 86 | ||
| 95 | #define MV64x60_IRQ_GPP23 87 | ||
| 96 | #define MV64x60_IRQ_GPP24 88 | ||
| 97 | #define MV64x60_IRQ_GPP25 89 | ||
| 98 | #define MV64x60_IRQ_GPP26 90 | ||
| 99 | #define MV64x60_IRQ_GPP27 91 | ||
| 100 | #define MV64x60_IRQ_GPP28 92 | ||
| 101 | #define MV64x60_IRQ_GPP29 93 | ||
| 102 | #define MV64x60_IRQ_GPP30 94 | ||
| 103 | #define MV64x60_IRQ_GPP31 95 | ||
| 104 | |||
| 105 | /* Offsets for register blocks */ | ||
| 106 | #define GT64260_ENET_PHY_ADDR 0x2000 | ||
| 107 | #define GT64260_ENET_ESMIR 0x2010 | ||
| 108 | #define GT64260_ENET_0_OFFSET 0x2400 | ||
| 109 | #define GT64260_ENET_1_OFFSET 0x2800 | ||
| 110 | #define GT64260_ENET_2_OFFSET 0x2c00 | ||
| 111 | #define MV64x60_SDMA_0_OFFSET 0x4000 | ||
| 112 | #define MV64x60_SDMA_1_OFFSET 0x6000 | ||
| 113 | #define MV64x60_MPSC_0_OFFSET 0x8000 | ||
| 114 | #define MV64x60_MPSC_1_OFFSET 0x9000 | ||
| 115 | #define MV64x60_MPSC_ROUTING_OFFSET 0xb400 | ||
| 116 | #define MV64x60_SDMA_INTR_OFFSET 0xb800 | ||
| 117 | #define MV64x60_BRG_0_OFFSET 0xb200 | ||
| 118 | #define MV64x60_BRG_1_OFFSET 0xb208 | ||
| 119 | |||
| 120 | /* | ||
| 121 | ***************************************************************************** | ||
| 122 | * | ||
| 123 | * CPU Interface Registers | ||
| 124 | * | ||
| 125 | ***************************************************************************** | ||
| 126 | */ | ||
| 127 | |||
| 128 | /* CPU physical address of bridge's registers */ | ||
| 129 | #define MV64x60_INTERNAL_SPACE_DECODE 0x0068 | ||
| 130 | #define MV64x60_INTERNAL_SPACE_SIZE 0x10000 | ||
| 131 | #define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 | ||
| 132 | |||
| 133 | #define MV64360_CPU_BAR_ENABLE 0x0278 | ||
| 134 | |||
| 135 | /* CPU Memory Controller Window Registers (4 windows) */ | ||
| 136 | #define MV64x60_CPU2MEM_WINDOWS 4 | ||
| 137 | |||
| 138 | #define MV64x60_CPU2MEM_0_BASE 0x0008 | ||
| 139 | #define MV64x60_CPU2MEM_0_SIZE 0x0010 | ||
| 140 | #define MV64x60_CPU2MEM_1_BASE 0x0208 | ||
| 141 | #define MV64x60_CPU2MEM_1_SIZE 0x0210 | ||
| 142 | #define MV64x60_CPU2MEM_2_BASE 0x0018 | ||
| 143 | #define MV64x60_CPU2MEM_2_SIZE 0x0020 | ||
| 144 | #define MV64x60_CPU2MEM_3_BASE 0x0218 | ||
| 145 | #define MV64x60_CPU2MEM_3_SIZE 0x0220 | ||
| 146 | |||
| 147 | /* CPU Device Controller Window Registers (4 windows) */ | ||
| 148 | #define MV64x60_CPU2DEV_WINDOWS 4 | ||
| 149 | |||
| 150 | #define MV64x60_CPU2DEV_0_BASE 0x0028 | ||
| 151 | #define MV64x60_CPU2DEV_0_SIZE 0x0030 | ||
| 152 | #define MV64x60_CPU2DEV_1_BASE 0x0228 | ||
| 153 | #define MV64x60_CPU2DEV_1_SIZE 0x0230 | ||
| 154 | #define MV64x60_CPU2DEV_2_BASE 0x0248 | ||
| 155 | #define MV64x60_CPU2DEV_2_SIZE 0x0250 | ||
| 156 | #define MV64x60_CPU2DEV_3_BASE 0x0038 | ||
| 157 | #define MV64x60_CPU2DEV_3_SIZE 0x0040 | ||
| 158 | |||
| 159 | #define MV64x60_CPU2BOOT_0_BASE 0x0238 | ||
| 160 | #define MV64x60_CPU2BOOT_0_SIZE 0x0240 | ||
| 161 | |||
| 162 | #define MV64360_CPU2SRAM_BASE 0x0268 | ||
| 163 | |||
| 164 | /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ | ||
| 165 | #define MV64x60_PCI_BUSES 2 | ||
| 166 | #define MV64x60_PCI_IO_WINDOWS_PER_BUS 1 | ||
| 167 | #define MV64x60_PCI_MEM_WINDOWS_PER_BUS 4 | ||
| 168 | |||
| 169 | #define MV64x60_CPU2PCI_SWAP_BYTE 0x00000000 | ||
| 170 | #define MV64x60_CPU2PCI_SWAP_NONE 0x01000000 | ||
| 171 | #define MV64x60_CPU2PCI_SWAP_BYTE_WORD 0x02000000 | ||
| 172 | #define MV64x60_CPU2PCI_SWAP_WORD 0x03000000 | ||
| 173 | |||
| 174 | #define MV64x60_CPU2PCI_MEM_REQ64 (1<<27) | ||
| 175 | |||
| 176 | #define MV64x60_CPU2PCI0_IO_BASE 0x0048 | ||
| 177 | #define MV64x60_CPU2PCI0_IO_SIZE 0x0050 | ||
| 178 | #define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058 | ||
| 179 | #define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060 | ||
| 180 | #define MV64x60_CPU2PCI0_MEM_1_BASE 0x0080 | ||
| 181 | #define MV64x60_CPU2PCI0_MEM_1_SIZE 0x0088 | ||
| 182 | #define MV64x60_CPU2PCI0_MEM_2_BASE 0x0258 | ||
| 183 | #define MV64x60_CPU2PCI0_MEM_2_SIZE 0x0260 | ||
| 184 | #define MV64x60_CPU2PCI0_MEM_3_BASE 0x0280 | ||
| 185 | #define MV64x60_CPU2PCI0_MEM_3_SIZE 0x0288 | ||
| 186 | |||
| 187 | #define MV64x60_CPU2PCI0_IO_REMAP 0x00f0 | ||
| 188 | #define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8 | ||
| 189 | #define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320 | ||
| 190 | #define MV64x60_CPU2PCI0_MEM_1_REMAP_LO 0x0100 | ||
| 191 | #define MV64x60_CPU2PCI0_MEM_1_REMAP_HI 0x0328 | ||
| 192 | #define MV64x60_CPU2PCI0_MEM_2_REMAP_LO 0x02f8 | ||
| 193 | #define MV64x60_CPU2PCI0_MEM_2_REMAP_HI 0x0330 | ||
| 194 | #define MV64x60_CPU2PCI0_MEM_3_REMAP_LO 0x0300 | ||
| 195 | #define MV64x60_CPU2PCI0_MEM_3_REMAP_HI 0x0338 | ||
| 196 | |||
| 197 | #define MV64x60_CPU2PCI1_IO_BASE 0x0090 | ||
| 198 | #define MV64x60_CPU2PCI1_IO_SIZE 0x0098 | ||
| 199 | #define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0 | ||
| 200 | #define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8 | ||
| 201 | #define MV64x60_CPU2PCI1_MEM_1_BASE 0x00b0 | ||
| 202 | #define MV64x60_CPU2PCI1_MEM_1_SIZE 0x00b8 | ||
| 203 | #define MV64x60_CPU2PCI1_MEM_2_BASE 0x02a0 | ||
| 204 | #define MV64x60_CPU2PCI1_MEM_2_SIZE 0x02a8 | ||
| 205 | #define MV64x60_CPU2PCI1_MEM_3_BASE 0x02b0 | ||
| 206 | #define MV64x60_CPU2PCI1_MEM_3_SIZE 0x02b8 | ||
| 207 | |||
| 208 | #define MV64x60_CPU2PCI1_IO_REMAP 0x0108 | ||
| 209 | #define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110 | ||
| 210 | #define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340 | ||
| 211 | #define MV64x60_CPU2PCI1_MEM_1_REMAP_LO 0x0118 | ||
| 212 | #define MV64x60_CPU2PCI1_MEM_1_REMAP_HI 0x0348 | ||
| 213 | #define MV64x60_CPU2PCI1_MEM_2_REMAP_LO 0x0310 | ||
| 214 | #define MV64x60_CPU2PCI1_MEM_2_REMAP_HI 0x0350 | ||
| 215 | #define MV64x60_CPU2PCI1_MEM_3_REMAP_LO 0x0318 | ||
| 216 | #define MV64x60_CPU2PCI1_MEM_3_REMAP_HI 0x0358 | ||
| 217 | |||
| 218 | /* CPU Control Registers */ | ||
| 219 | #define MV64x60_CPU_CONFIG 0x0000 | ||
| 220 | #define MV64x60_CPU_MODE 0x0120 | ||
| 221 | #define MV64x60_CPU_MASTER_CNTL 0x0160 | ||
| 222 | #define MV64x60_CPU_XBAR_CNTL_LO 0x0150 | ||
| 223 | #define MV64x60_CPU_XBAR_CNTL_HI 0x0158 | ||
| 224 | #define MV64x60_CPU_XBAR_TO 0x0168 | ||
| 225 | |||
| 226 | #define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 | ||
| 227 | #define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 | ||
| 228 | |||
| 229 | #define MV64360_CPU_PADS_CALIBRATION 0x03b4 | ||
| 230 | #define MV64360_CPU_RESET_SAMPLE_LO 0x03c4 | ||
| 231 | #define MV64360_CPU_RESET_SAMPLE_HI 0x03d4 | ||
| 232 | |||
| 233 | /* SMP Register Map */ | ||
| 234 | #define MV64360_WHO_AM_I 0x0200 | ||
| 235 | #define MV64360_CPU0_DOORBELL 0x0214 | ||
| 236 | #define MV64360_CPU0_DOORBELL_CLR 0x021c | ||
| 237 | #define MV64360_CPU0_DOORBELL_MASK 0x0234 | ||
| 238 | #define MV64360_CPU1_DOORBELL 0x0224 | ||
| 239 | #define MV64360_CPU1_DOORBELL_CLR 0x022c | ||
| 240 | #define MV64360_CPU1_DOORBELL_MASK 0x023c | ||
| 241 | #define MV64360_CPUx_DOORBELL(x) (0x0214 + ((x)*0x10)) | ||
| 242 | #define MV64360_CPUx_DOORBELL_CLR(x) (0x021c + ((x)*0x10)) | ||
| 243 | #define MV64360_CPUx_DOORBELL_MASK(x) (0x0234 + ((x)*0x08)) | ||
| 244 | #define MV64360_SEMAPHORE_0 0x0244 | ||
| 245 | #define MV64360_SEMAPHORE_1 0x024c | ||
| 246 | #define MV64360_SEMAPHORE_2 0x0254 | ||
| 247 | #define MV64360_SEMAPHORE_3 0x025c | ||
| 248 | #define MV64360_SEMAPHORE_4 0x0264 | ||
| 249 | #define MV64360_SEMAPHORE_5 0x026c | ||
| 250 | #define MV64360_SEMAPHORE_6 0x0274 | ||
| 251 | #define MV64360_SEMAPHORE_7 0x027c | ||
| 252 | |||
| 253 | /* CPU Sync Barrier Registers */ | ||
| 254 | #define GT64260_CPU_SYNC_BARRIER_PCI0 0x00c0 | ||
| 255 | #define GT64260_CPU_SYNC_BARRIER_PCI1 0x00c8 | ||
| 256 | |||
| 257 | #define MV64360_CPU0_SYNC_BARRIER_TRIG 0x00c0 | ||
| 258 | #define MV64360_CPU0_SYNC_BARRIER_VIRT 0x00c8 | ||
| 259 | #define MV64360_CPU1_SYNC_BARRIER_TRIG 0x00d0 | ||
| 260 | #define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8 | ||
| 261 | |||
| 262 | /* CPU Deadlock and Ordering registers (Rev B part only) */ | ||
| 263 | #define GT64260_CPU_DEADLOCK_ORDERING 0x02d0 | ||
| 264 | #define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8 | ||
| 265 | #define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0 | ||
| 266 | |||
| 267 | /* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */ | ||
| 268 | #define MV64x260_CPU_PROT_WINDOWS 4 | ||
| 269 | |||
| 270 | #define GT64260_CPU_PROT_ACCPROTECT (1<<16) | ||
| 271 | #define GT64260_CPU_PROT_WRPROTECT (1<<17) | ||
| 272 | #define GT64260_CPU_PROT_CACHEPROTECT (1<<18) | ||
| 273 | |||
| 274 | #define MV64360_CPU_PROT_ACCPROTECT (1<<20) | ||
| 275 | #define MV64360_CPU_PROT_WRPROTECT (1<<21) | ||
| 276 | #define MV64360_CPU_PROT_CACHEPROTECT (1<<22) | ||
| 277 | #define MV64360_CPU_PROT_WIN_ENABLE (1<<31) | ||
| 278 | |||
| 279 | #define MV64x60_CPU_PROT_BASE_0 0x0180 | ||
| 280 | #define MV64x60_CPU_PROT_SIZE_0 0x0188 | ||
| 281 | #define MV64x60_CPU_PROT_BASE_1 0x0190 | ||
| 282 | #define MV64x60_CPU_PROT_SIZE_1 0x0198 | ||
| 283 | #define MV64x60_CPU_PROT_BASE_2 0x01a0 | ||
| 284 | #define MV64x60_CPU_PROT_SIZE_2 0x01a8 | ||
| 285 | #define MV64x60_CPU_PROT_BASE_3 0x01b0 | ||
| 286 | #define MV64x60_CPU_PROT_SIZE_3 0x01b8 | ||
| 287 | |||
| 288 | #define GT64260_CPU_PROT_BASE_4 0x01c0 | ||
| 289 | #define GT64260_CPU_PROT_SIZE_4 0x01c8 | ||
| 290 | #define GT64260_CPU_PROT_BASE_5 0x01d0 | ||
| 291 | #define GT64260_CPU_PROT_SIZE_5 0x01d8 | ||
| 292 | #define GT64260_CPU_PROT_BASE_6 0x01e0 | ||
| 293 | #define GT64260_CPU_PROT_SIZE_6 0x01e8 | ||
| 294 | #define GT64260_CPU_PROT_BASE_7 0x01f0 | ||
| 295 | #define GT64260_CPU_PROT_SIZE_7 0x01f8 | ||
| 296 | |||
| 297 | /* CPU Snoop Control Registers (64260 only) */ | ||
| 298 | #define GT64260_CPU_SNOOP_WINDOWS 4 | ||
| 299 | |||
| 300 | #define GT64260_CPU_SNOOP_NONE 0x00000000 | ||
| 301 | #define GT64260_CPU_SNOOP_WT 0x00010000 | ||
| 302 | #define GT64260_CPU_SNOOP_WB 0x00020000 | ||
| 303 | #define GT64260_CPU_SNOOP_MASK 0x00030000 | ||
| 304 | #define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK | ||
| 305 | |||
| 306 | #define GT64260_CPU_SNOOP_BASE_0 0x0380 | ||
| 307 | #define GT64260_CPU_SNOOP_SIZE_0 0x0388 | ||
| 308 | #define GT64260_CPU_SNOOP_BASE_1 0x0390 | ||
| 309 | #define GT64260_CPU_SNOOP_SIZE_1 0x0398 | ||
| 310 | #define GT64260_CPU_SNOOP_BASE_2 0x03a0 | ||
| 311 | #define GT64260_CPU_SNOOP_SIZE_2 0x03a8 | ||
| 312 | #define GT64260_CPU_SNOOP_BASE_3 0x03b0 | ||
| 313 | #define GT64260_CPU_SNOOP_SIZE_3 0x03b8 | ||
| 314 | |||
| 315 | /* CPU Snoop Control Registers (64360 only) */ | ||
| 316 | #define MV64360_CPU_SNOOP_WINDOWS 4 | ||
| 317 | #define MV64360_CPU_SNOOP_NONE 0x00000000 | ||
| 318 | #define MV64360_CPU_SNOOP_WT 0x00010000 | ||
| 319 | #define MV64360_CPU_SNOOP_WB 0x00020000 | ||
| 320 | #define MV64360_CPU_SNOOP_MASK 0x00030000 | ||
| 321 | #define MV64360_CPU_SNOOP_ALL_BITS MV64360_CPU_SNOOP_MASK | ||
| 322 | |||
| 323 | |||
| 324 | /* CPU Error Report Registers */ | ||
| 325 | #define MV64x60_CPU_ERR_ADDR_LO 0x0070 | ||
| 326 | #define MV64x60_CPU_ERR_ADDR_HI 0x0078 | ||
| 327 | #define MV64x60_CPU_ERR_DATA_LO 0x0128 | ||
| 328 | #define MV64x60_CPU_ERR_DATA_HI 0x0130 | ||
| 329 | #define MV64x60_CPU_ERR_PARITY 0x0138 | ||
| 330 | #define MV64x60_CPU_ERR_CAUSE 0x0140 | ||
| 331 | #define MV64x60_CPU_ERR_MASK 0x0148 | ||
| 332 | |||
| 333 | /* | ||
| 334 | ***************************************************************************** | ||
| 335 | * | ||
| 336 | * SRAM Controller Registers | ||
| 337 | * | ||
| 338 | ***************************************************************************** | ||
| 339 | */ | ||
| 340 | |||
| 341 | #define MV64360_SRAM_CONFIG 0x0380 | ||
| 342 | #define MV64360_SRAM_TEST_MODE 0x03f4 | ||
| 343 | #define MV64360_SRAM_ERR_CAUSE 0x0388 | ||
| 344 | #define MV64360_SRAM_ERR_ADDR_LO 0x0390 | ||
| 345 | #define MV64360_SRAM_ERR_ADDR_HI 0x03f8 | ||
| 346 | #define MV64360_SRAM_ERR_DATA_LO 0x0398 | ||
| 347 | #define MV64360_SRAM_ERR_DATA_HI 0x03a0 | ||
| 348 | #define MV64360_SRAM_ERR_PARITY 0x03a8 | ||
| 349 | |||
| 350 | #define MV64360_SRAM_SIZE 0x00040000 /* 2Mb/256KB SRAM */ | ||
| 351 | |||
| 352 | /* | ||
| 353 | ***************************************************************************** | ||
| 354 | * | ||
| 355 | * SDRAM/MEM Controller Registers | ||
| 356 | * | ||
| 357 | ***************************************************************************** | ||
| 358 | */ | ||
| 359 | |||
| 360 | /* SDRAM Config Registers (64260) */ | ||
| 361 | #define GT64260_SDRAM_CONFIG 0x0448 | ||
| 362 | |||
| 363 | /* SDRAM Error Report Registers (64260) */ | ||
| 364 | #define GT64260_SDRAM_ERR_DATA_LO 0x0484 | ||
| 365 | #define GT64260_SDRAM_ERR_DATA_HI 0x0480 | ||
| 366 | #define GT64260_SDRAM_ERR_ADDR 0x0490 | ||
| 367 | #define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 | ||
| 368 | #define GT64260_SDRAM_ERR_ECC_CALC 0x048c | ||
| 369 | #define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 | ||
| 370 | #define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 | ||
| 371 | |||
| 372 | /* SDRAM Config Registers (64360) */ | ||
| 373 | #define MV64360_SDRAM_CONFIG 0x1400 | ||
| 374 | |||
| 375 | /* SDRAM Control Registers */ | ||
| 376 | #define MV64360_D_UNIT_CONTROL_LOW 0x1404 | ||
| 377 | #define MV64360_D_UNIT_CONTROL_HIGH 0x1424 | ||
| 378 | #define MV64460_D_UNIT_MMASK 0x14b0 | ||
| 379 | |||
| 380 | /* SDRAM Error Report Registers (64360) */ | ||
| 381 | #define MV64360_SDRAM_ERR_DATA_LO 0x1444 | ||
| 382 | #define MV64360_SDRAM_ERR_DATA_HI 0x1440 | ||
| 383 | #define MV64360_SDRAM_ERR_ADDR 0x1450 | ||
| 384 | #define MV64360_SDRAM_ERR_ECC_RCVD 0x1448 | ||
| 385 | #define MV64360_SDRAM_ERR_ECC_CALC 0x144c | ||
| 386 | #define MV64360_SDRAM_ERR_ECC_CNTL 0x1454 | ||
| 387 | #define MV64360_SDRAM_ERR_ECC_ERR_CNT 0x1458 | ||
| 388 | |||
| 389 | /* | ||
| 390 | ***************************************************************************** | ||
| 391 | * | ||
| 392 | * Device/BOOT Controller Registers | ||
| 393 | * | ||
| 394 | ***************************************************************************** | ||
| 395 | */ | ||
| 396 | |||
| 397 | /* Device Control Registers */ | ||
| 398 | #define MV64x60_DEV_BANK_PARAMS_0 0x045c | ||
| 399 | #define MV64x60_DEV_BANK_PARAMS_1 0x0460 | ||
| 400 | #define MV64x60_DEV_BANK_PARAMS_2 0x0464 | ||
| 401 | #define MV64x60_DEV_BANK_PARAMS_3 0x0468 | ||
| 402 | #define MV64x60_DEV_BOOT_PARAMS 0x046c | ||
| 403 | #define MV64x60_DEV_IF_CNTL 0x04c0 | ||
| 404 | #define MV64x60_DEV_IF_XBAR_CNTL_LO 0x04c8 | ||
| 405 | #define MV64x60_DEV_IF_XBAR_CNTL_HI 0x04cc | ||
| 406 | #define MV64x60_DEV_IF_XBAR_CNTL_TO 0x04c4 | ||
| 407 | |||
| 408 | /* Device Interrupt Registers */ | ||
| 409 | #define MV64x60_DEV_INTR_CAUSE 0x04d0 | ||
| 410 | #define MV64x60_DEV_INTR_MASK 0x04d4 | ||
| 411 | #define MV64x60_DEV_INTR_ERR_ADDR 0x04d8 | ||
| 412 | |||
| 413 | #define MV64360_DEV_INTR_ERR_DATA 0x04dc | ||
| 414 | #define MV64360_DEV_INTR_ERR_PAR 0x04e0 | ||
| 415 | |||
| 416 | /* | ||
| 417 | ***************************************************************************** | ||
| 418 | * | ||
| 419 | * PCI Bridge Interface Registers | ||
| 420 | * | ||
| 421 | ***************************************************************************** | ||
| 422 | */ | ||
| 423 | |||
| 424 | /* PCI Configuration Access Registers */ | ||
| 425 | #define MV64x60_PCI0_CONFIG_ADDR 0x0cf8 | ||
| 426 | #define MV64x60_PCI0_CONFIG_DATA 0x0cfc | ||
| 427 | #define MV64x60_PCI0_IACK 0x0c34 | ||
| 428 | |||
| 429 | #define MV64x60_PCI1_CONFIG_ADDR 0x0c78 | ||
| 430 | #define MV64x60_PCI1_CONFIG_DATA 0x0c7c | ||
| 431 | #define MV64x60_PCI1_IACK 0x0cb4 | ||
| 432 | |||
| 433 | /* PCI Control Registers */ | ||
| 434 | #define MV64x60_PCI0_CMD 0x0c00 | ||
| 435 | #define MV64x60_PCI0_MODE 0x0d00 | ||
| 436 | #define MV64x60_PCI0_TO_RETRY 0x0c04 | ||
| 437 | #define MV64x60_PCI0_RD_BUF_DISCARD_TIMER 0x0d04 | ||
| 438 | #define MV64x60_PCI0_MSI_TRIGGER_TIMER 0x0c38 | ||
| 439 | #define MV64x60_PCI0_ARBITER_CNTL 0x1d00 | ||
| 440 | #define MV64x60_PCI0_XBAR_CNTL_LO 0x1d08 | ||
| 441 | #define MV64x60_PCI0_XBAR_CNTL_HI 0x1d0c | ||
| 442 | #define MV64x60_PCI0_XBAR_CNTL_TO 0x1d04 | ||
| 443 | #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO 0x1d18 | ||
| 444 | #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI 0x1d1c | ||
| 445 | #define MV64x60_PCI0_SYNC_BARRIER 0x1d10 | ||
| 446 | #define MV64x60_PCI0_P2P_CONFIG 0x1d14 | ||
| 447 | #define MV64x60_PCI0_INTR_MASK | ||
| 448 | |||
| 449 | #define GT64260_PCI0_P2P_SWAP_CNTL 0x1d54 | ||
| 450 | |||
| 451 | #define MV64x60_PCI1_CMD 0x0c80 | ||
| 452 | #define MV64x60_PCI1_MODE 0x0d80 | ||
| 453 | #define MV64x60_PCI1_TO_RETRY 0x0c84 | ||
| 454 | #define MV64x60_PCI1_RD_BUF_DISCARD_TIMER 0x0d84 | ||
| 455 | #define MV64x60_PCI1_MSI_TRIGGER_TIMER 0x0cb8 | ||
| 456 | #define MV64x60_PCI1_ARBITER_CNTL 0x1d80 | ||
| 457 | #define MV64x60_PCI1_XBAR_CNTL_LO 0x1d88 | ||
| 458 | #define MV64x60_PCI1_XBAR_CNTL_HI 0x1d8c | ||
| 459 | #define MV64x60_PCI1_XBAR_CNTL_TO 0x1d84 | ||
| 460 | #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO 0x1d98 | ||
| 461 | #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI 0x1d9c | ||
| 462 | #define MV64x60_PCI1_SYNC_BARRIER 0x1d90 | ||
| 463 | #define MV64x60_PCI1_P2P_CONFIG 0x1d94 | ||
| 464 | |||
| 465 | #define GT64260_PCI1_P2P_SWAP_CNTL 0x1dd4 | ||
| 466 | |||
| 467 | /* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */ | ||
| 468 | #define MV64x60_PCIMODE_CONVENTIONAL 0 | ||
| 469 | #define MV64x60_PCIMODE_PCIX_66 (1 << 4) | ||
| 470 | #define MV64x60_PCIMODE_PCIX_100 (2 << 4) | ||
| 471 | #define MV64x60_PCIMODE_PCIX_133 (3 << 4) | ||
| 472 | #define MV64x60_PCIMODE_MASK (0x3 << 4) | ||
| 473 | |||
| 474 | /* PCI Access Control Regions Registers */ | ||
| 475 | #define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) | ||
| 476 | #define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) | ||
| 477 | #define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) | ||
| 478 | #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) | ||
| 479 | #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) | ||
| 480 | #define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES 0x00000000 | ||
| 481 | #define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES 0x00100000 | ||
| 482 | #define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES 0x00200000 | ||
| 483 | #define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 | ||
| 484 | #define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 | ||
| 485 | #define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 | ||
| 486 | #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 | ||
| 487 | #define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 | ||
| 488 | #define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 | ||
| 489 | #define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) | ||
| 490 | #define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) | ||
| 491 | |||
| 492 | #define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ | ||
| 493 | GT64260_PCI_ACC_CNTL_DREADEN | \ | ||
| 494 | GT64260_PCI_ACC_CNTL_RDPREFETCH | \ | ||
| 495 | GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ | ||
| 496 | GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ | ||
| 497 | GT64260_PCI_ACC_CNTL_MBURST_MASK | \ | ||
| 498 | GT64260_PCI_ACC_CNTL_SWAP_MASK | \ | ||
| 499 | GT64260_PCI_ACC_CNTL_ACCPROT| \ | ||
| 500 | GT64260_PCI_ACC_CNTL_WRPROT) | ||
| 501 | |||
| 502 | #define MV64360_PCI_ACC_CNTL_ENABLE (1<<0) | ||
| 503 | #define MV64360_PCI_ACC_CNTL_REQ64 (1<<1) | ||
| 504 | #define MV64360_PCI_ACC_CNTL_SNOOP_NONE 0x00000000 | ||
| 505 | #define MV64360_PCI_ACC_CNTL_SNOOP_WT 0x00000004 | ||
| 506 | #define MV64360_PCI_ACC_CNTL_SNOOP_WB 0x00000008 | ||
| 507 | #define MV64360_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c | ||
| 508 | #define MV64360_PCI_ACC_CNTL_ACCPROT (1<<4) | ||
| 509 | #define MV64360_PCI_ACC_CNTL_WRPROT (1<<5) | ||
| 510 | #define MV64360_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 | ||
| 511 | #define MV64360_PCI_ACC_CNTL_SWAP_NONE 0x00000040 | ||
| 512 | #define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080 | ||
| 513 | #define MV64360_PCI_ACC_CNTL_SWAP_WORD 0x000000c0 | ||
| 514 | #define MV64360_PCI_ACC_CNTL_SWAP_MASK 0x000000c0 | ||
| 515 | #define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000 | ||
| 516 | #define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100 | ||
| 517 | #define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200 | ||
| 518 | #define MV64360_PCI_ACC_CNTL_MBURST_MASK 0x00000300 | ||
| 519 | #define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000 | ||
| 520 | #define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400 | ||
| 521 | #define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800 | ||
| 522 | #define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00 | ||
| 523 | #define MV64360_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00 | ||
| 524 | |||
| 525 | #define MV64360_PCI_ACC_CNTL_ALL_BITS (MV64360_PCI_ACC_CNTL_ENABLE | \ | ||
| 526 | MV64360_PCI_ACC_CNTL_REQ64 | \ | ||
| 527 | MV64360_PCI_ACC_CNTL_SNOOP_MASK | \ | ||
| 528 | MV64360_PCI_ACC_CNTL_ACCPROT | \ | ||
| 529 | MV64360_PCI_ACC_CNTL_WRPROT | \ | ||
| 530 | MV64360_PCI_ACC_CNTL_SWAP_MASK | \ | ||
| 531 | MV64360_PCI_ACC_CNTL_MBURST_MASK | \ | ||
| 532 | MV64360_PCI_ACC_CNTL_RDSIZE_MASK) | ||
| 533 | |||
| 534 | #define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00 | ||
| 535 | #define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04 | ||
| 536 | #define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08 | ||
| 537 | #define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10 | ||
| 538 | #define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14 | ||
| 539 | #define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18 | ||
| 540 | #define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20 | ||
| 541 | #define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24 | ||
| 542 | #define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28 | ||
| 543 | #define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30 | ||
| 544 | #define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34 | ||
| 545 | #define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38 | ||
| 546 | #define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40 | ||
| 547 | #define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44 | ||
| 548 | #define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48 | ||
| 549 | #define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50 | ||
| 550 | #define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54 | ||
| 551 | #define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58 | ||
| 552 | |||
| 553 | #define GT64260_PCI0_ACC_CNTL_6_BASE_LO 0x1e60 | ||
| 554 | #define GT64260_PCI0_ACC_CNTL_6_BASE_HI 0x1e64 | ||
| 555 | #define GT64260_PCI0_ACC_CNTL_6_SIZE 0x1e68 | ||
| 556 | #define GT64260_PCI0_ACC_CNTL_7_BASE_LO 0x1e70 | ||
| 557 | #define GT64260_PCI0_ACC_CNTL_7_BASE_HI 0x1e74 | ||
| 558 | #define GT64260_PCI0_ACC_CNTL_7_SIZE 0x1e78 | ||
| 559 | |||
| 560 | #define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80 | ||
| 561 | #define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84 | ||
| 562 | #define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88 | ||
| 563 | #define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90 | ||
| 564 | #define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94 | ||
| 565 | #define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98 | ||
| 566 | #define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0 | ||
| 567 | #define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4 | ||
| 568 | #define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8 | ||
| 569 | #define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0 | ||
| 570 | #define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4 | ||
| 571 | #define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8 | ||
| 572 | #define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0 | ||
| 573 | #define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4 | ||
| 574 | #define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8 | ||
| 575 | #define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0 | ||
| 576 | #define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4 | ||
| 577 | #define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8 | ||
| 578 | |||
| 579 | #define GT64260_PCI1_ACC_CNTL_6_BASE_LO 0x1ee0 | ||
| 580 | #define GT64260_PCI1_ACC_CNTL_6_BASE_HI 0x1ee4 | ||
| 581 | #define GT64260_PCI1_ACC_CNTL_6_SIZE 0x1ee8 | ||
| 582 | #define GT64260_PCI1_ACC_CNTL_7_BASE_LO 0x1ef0 | ||
| 583 | #define GT64260_PCI1_ACC_CNTL_7_BASE_HI 0x1ef4 | ||
| 584 | #define GT64260_PCI1_ACC_CNTL_7_SIZE 0x1ef8 | ||
| 585 | |||
| 586 | /* PCI Snoop Control Registers (64260 only) */ | ||
| 587 | #define GT64260_PCI_SNOOP_NONE 0x00000000 | ||
| 588 | #define GT64260_PCI_SNOOP_WT 0x00001000 | ||
| 589 | #define GT64260_PCI_SNOOP_WB 0x00002000 | ||
| 590 | |||
| 591 | #define GT64260_PCI0_SNOOP_0_BASE_LO 0x1f00 | ||
| 592 | #define GT64260_PCI0_SNOOP_0_BASE_HI 0x1f04 | ||
| 593 | #define GT64260_PCI0_SNOOP_0_SIZE 0x1f08 | ||
| 594 | #define GT64260_PCI0_SNOOP_1_BASE_LO 0x1f10 | ||
| 595 | #define GT64260_PCI0_SNOOP_1_BASE_HI 0x1f14 | ||
| 596 | #define GT64260_PCI0_SNOOP_1_SIZE 0x1f18 | ||
| 597 | #define GT64260_PCI0_SNOOP_2_BASE_LO 0x1f20 | ||
| 598 | #define GT64260_PCI0_SNOOP_2_BASE_HI 0x1f24 | ||
| 599 | #define GT64260_PCI0_SNOOP_2_SIZE 0x1f28 | ||
| 600 | #define GT64260_PCI0_SNOOP_3_BASE_LO 0x1f30 | ||
| 601 | #define GT64260_PCI0_SNOOP_3_BASE_HI 0x1f34 | ||
| 602 | #define GT64260_PCI0_SNOOP_3_SIZE 0x1f38 | ||
| 603 | |||
| 604 | #define GT64260_PCI1_SNOOP_0_BASE_LO 0x1f80 | ||
| 605 | #define GT64260_PCI1_SNOOP_0_BASE_HI 0x1f84 | ||
| 606 | #define GT64260_PCI1_SNOOP_0_SIZE 0x1f88 | ||
| 607 | #define GT64260_PCI1_SNOOP_1_BASE_LO 0x1f90 | ||
| 608 | #define GT64260_PCI1_SNOOP_1_BASE_HI 0x1f94 | ||
| 609 | #define GT64260_PCI1_SNOOP_1_SIZE 0x1f98 | ||
| 610 | #define GT64260_PCI1_SNOOP_2_BASE_LO 0x1fa0 | ||
| 611 | #define GT64260_PCI1_SNOOP_2_BASE_HI 0x1fa4 | ||
| 612 | #define GT64260_PCI1_SNOOP_2_SIZE 0x1fa8 | ||
| 613 | #define GT64260_PCI1_SNOOP_3_BASE_LO 0x1fb0 | ||
| 614 | #define GT64260_PCI1_SNOOP_3_BASE_HI 0x1fb4 | ||
| 615 | #define GT64260_PCI1_SNOOP_3_SIZE 0x1fb8 | ||
| 616 | |||
| 617 | /* PCI Error Report Registers */ | ||
| 618 | #define MV64x60_PCI0_ERR_SERR_MASK 0x0c28 | ||
| 619 | #define MV64x60_PCI0_ERR_ADDR_LO 0x1d40 | ||
| 620 | #define MV64x60_PCI0_ERR_ADDR_HI 0x1d44 | ||
| 621 | #define MV64x60_PCI0_ERR_DATA_LO 0x1d48 | ||
| 622 | #define MV64x60_PCI0_ERR_DATA_HI 0x1d4c | ||
| 623 | #define MV64x60_PCI0_ERR_CMD 0x1d50 | ||
| 624 | #define MV64x60_PCI0_ERR_CAUSE 0x1d58 | ||
| 625 | #define MV64x60_PCI0_ERR_MASK 0x1d5c | ||
| 626 | |||
| 627 | #define MV64x60_PCI1_ERR_SERR_MASK 0x0ca8 | ||
| 628 | #define MV64x60_PCI1_ERR_ADDR_LO 0x1dc0 | ||
| 629 | #define MV64x60_PCI1_ERR_ADDR_HI 0x1dc4 | ||
| 630 | #define MV64x60_PCI1_ERR_DATA_LO 0x1dc8 | ||
| 631 | #define MV64x60_PCI1_ERR_DATA_HI 0x1dcc | ||
| 632 | #define MV64x60_PCI1_ERR_CMD 0x1dd0 | ||
| 633 | #define MV64x60_PCI1_ERR_CAUSE 0x1dd8 | ||
| 634 | #define MV64x60_PCI1_ERR_MASK 0x1ddc | ||
| 635 | |||
| 636 | /* PCI Slave Address Decoding Registers */ | ||
| 637 | #define MV64x60_PCI0_MEM_0_SIZE 0x0c08 | ||
| 638 | #define MV64x60_PCI0_MEM_1_SIZE 0x0d08 | ||
| 639 | #define MV64x60_PCI0_MEM_2_SIZE 0x0c0c | ||
| 640 | #define MV64x60_PCI0_MEM_3_SIZE 0x0d0c | ||
| 641 | #define MV64x60_PCI1_MEM_0_SIZE 0x0c88 | ||
| 642 | #define MV64x60_PCI1_MEM_1_SIZE 0x0d88 | ||
| 643 | #define MV64x60_PCI1_MEM_2_SIZE 0x0c8c | ||
| 644 | #define MV64x60_PCI1_MEM_3_SIZE 0x0d8c | ||
| 645 | |||
| 646 | #define MV64x60_PCI0_BAR_ENABLE 0x0c3c | ||
| 647 | #define MV64x60_PCI1_BAR_ENABLE 0x0cbc | ||
| 648 | |||
| 649 | #define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c | ||
| 650 | #define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc | ||
| 651 | |||
| 652 | #define MV64x60_PCI0_SLAVE_MEM_0_REMAP 0x0c48 | ||
| 653 | #define MV64x60_PCI0_SLAVE_MEM_1_REMAP 0x0d48 | ||
| 654 | #define MV64x60_PCI0_SLAVE_MEM_2_REMAP 0x0c4c | ||
| 655 | #define MV64x60_PCI0_SLAVE_MEM_3_REMAP 0x0d4c | ||
| 656 | #define MV64x60_PCI0_SLAVE_DEV_0_REMAP 0x0c50 | ||
| 657 | #define MV64x60_PCI0_SLAVE_DEV_1_REMAP 0x0d50 | ||
| 658 | #define MV64x60_PCI0_SLAVE_DEV_2_REMAP 0x0d58 | ||
| 659 | #define MV64x60_PCI0_SLAVE_DEV_3_REMAP 0x0c54 | ||
| 660 | #define MV64x60_PCI0_SLAVE_BOOT_REMAP 0x0d54 | ||
| 661 | #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c | ||
| 662 | #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 | ||
| 663 | #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 | ||
| 664 | #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 | ||
| 665 | #define MV64x60_PCI0_SLAVE_P2P_IO_REMAP 0x0d6c | ||
| 666 | #define MV64x60_PCI0_SLAVE_CPU_REMAP 0x0d70 | ||
| 667 | |||
| 668 | #define MV64x60_PCI1_SLAVE_MEM_0_REMAP 0x0cc8 | ||
| 669 | #define MV64x60_PCI1_SLAVE_MEM_1_REMAP 0x0dc8 | ||
| 670 | #define MV64x60_PCI1_SLAVE_MEM_2_REMAP 0x0ccc | ||
| 671 | #define MV64x60_PCI1_SLAVE_MEM_3_REMAP 0x0dcc | ||
| 672 | #define MV64x60_PCI1_SLAVE_DEV_0_REMAP 0x0cd0 | ||
| 673 | #define MV64x60_PCI1_SLAVE_DEV_1_REMAP 0x0dd0 | ||
| 674 | #define MV64x60_PCI1_SLAVE_DEV_2_REMAP 0x0dd8 | ||
| 675 | #define MV64x60_PCI1_SLAVE_DEV_3_REMAP 0x0cd4 | ||
| 676 | #define MV64x60_PCI1_SLAVE_BOOT_REMAP 0x0dd4 | ||
| 677 | #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc | ||
| 678 | #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 | ||
| 679 | #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 | ||
| 680 | #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 | ||
| 681 | #define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec | ||
| 682 | #define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0 | ||
| 683 | |||
| 684 | #define MV64360_PCICFG_CPCI_HOTSWAP 0x68 | ||
| 685 | |||
| 686 | /* | ||
| 687 | ***************************************************************************** | ||
| 688 | * | ||
| 689 | * ENET Controller Interface Registers | ||
| 690 | * | ||
| 691 | ***************************************************************************** | ||
| 692 | */ | ||
| 693 | |||
| 694 | /* ENET Controller Window Registers (6 windows) */ | ||
| 695 | #define MV64360_ENET2MEM_WINDOWS 6 | ||
| 696 | |||
| 697 | #define MV64360_ENET2MEM_0_BASE 0x2200 | ||
| 698 | #define MV64360_ENET2MEM_0_SIZE 0x2204 | ||
| 699 | #define MV64360_ENET2MEM_1_BASE 0x2208 | ||
| 700 | #define MV64360_ENET2MEM_1_SIZE 0x220c | ||
| 701 | #define MV64360_ENET2MEM_2_BASE 0x2210 | ||
| 702 | #define MV64360_ENET2MEM_2_SIZE 0x2214 | ||
| 703 | #define MV64360_ENET2MEM_3_BASE 0x2218 | ||
| 704 | #define MV64360_ENET2MEM_3_SIZE 0x221c | ||
| 705 | #define MV64360_ENET2MEM_4_BASE 0x2220 | ||
| 706 | #define MV64360_ENET2MEM_4_SIZE 0x2224 | ||
| 707 | #define MV64360_ENET2MEM_5_BASE 0x2228 | ||
| 708 | #define MV64360_ENET2MEM_5_SIZE 0x222c | ||
| 709 | |||
| 710 | #define MV64360_ENET2MEM_SNOOP_NONE 0x00000000 | ||
| 711 | #define MV64360_ENET2MEM_SNOOP_WT 0x00001000 | ||
| 712 | #define MV64360_ENET2MEM_SNOOP_WB 0x00002000 | ||
| 713 | |||
| 714 | #define MV64360_ENET2MEM_BAR_ENABLE 0x2290 | ||
| 715 | |||
| 716 | #define MV64360_ENET2MEM_ACC_PROT_0 0x2294 | ||
| 717 | #define MV64360_ENET2MEM_ACC_PROT_1 0x2298 | ||
| 718 | #define MV64360_ENET2MEM_ACC_PROT_2 0x229c | ||
| 719 | |||
| 720 | /* | ||
| 721 | ***************************************************************************** | ||
| 722 | * | ||
| 723 | * MPSC Controller Interface Registers | ||
| 724 | * | ||
| 725 | ***************************************************************************** | ||
| 726 | */ | ||
| 727 | |||
| 728 | /* MPSC Controller Window Registers (4 windows) */ | ||
| 729 | #define MV64360_MPSC2MEM_WINDOWS 4 | ||
| 730 | |||
| 731 | #define MV64360_MPSC2MEM_0_BASE 0xf200 | ||
| 732 | #define MV64360_MPSC2MEM_0_SIZE 0xf204 | ||
| 733 | #define MV64360_MPSC2MEM_1_BASE 0xf208 | ||
| 734 | #define MV64360_MPSC2MEM_1_SIZE 0xf20c | ||
| 735 | #define MV64360_MPSC2MEM_2_BASE 0xf210 | ||
| 736 | #define MV64360_MPSC2MEM_2_SIZE 0xf214 | ||
| 737 | #define MV64360_MPSC2MEM_3_BASE 0xf218 | ||
| 738 | #define MV64360_MPSC2MEM_3_SIZE 0xf21c | ||
| 739 | |||
| 740 | #define MV64360_MPSC_0_REMAP 0xf240 | ||
| 741 | #define MV64360_MPSC_1_REMAP 0xf244 | ||
| 742 | |||
| 743 | #define MV64360_MPSC2MEM_SNOOP_NONE 0x00000000 | ||
| 744 | #define MV64360_MPSC2MEM_SNOOP_WT 0x00001000 | ||
| 745 | #define MV64360_MPSC2MEM_SNOOP_WB 0x00002000 | ||
| 746 | |||
| 747 | #define MV64360_MPSC2MEM_BAR_ENABLE 0xf250 | ||
| 748 | |||
| 749 | #define MV64360_MPSC2MEM_ACC_PROT_0 0xf254 | ||
| 750 | #define MV64360_MPSC2MEM_ACC_PROT_1 0xf258 | ||
| 751 | |||
| 752 | #define MV64360_MPSC2REGS_BASE 0xf25c | ||
| 753 | |||
| 754 | /* | ||
| 755 | ***************************************************************************** | ||
| 756 | * | ||
| 757 | * Timer/Counter Interface Registers | ||
| 758 | * | ||
| 759 | ***************************************************************************** | ||
| 760 | */ | ||
| 761 | |||
| 762 | #define MV64x60_TIMR_CNTR_0 0x0850 | ||
| 763 | #define MV64x60_TIMR_CNTR_1 0x0854 | ||
| 764 | #define MV64x60_TIMR_CNTR_2 0x0858 | ||
| 765 | #define MV64x60_TIMR_CNTR_3 0x085c | ||
| 766 | #define MV64x60_TIMR_CNTR_0_3_CNTL 0x0864 | ||
| 767 | #define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE 0x0868 | ||
| 768 | #define MV64x60_TIMR_CNTR_0_3_INTR_MASK 0x086c | ||
| 769 | |||
| 770 | #define GT64260_TIMR_CNTR_4 0x0950 | ||
| 771 | #define GT64260_TIMR_CNTR_5 0x0954 | ||
| 772 | #define GT64260_TIMR_CNTR_6 0x0958 | ||
| 773 | #define GT64260_TIMR_CNTR_7 0x095c | ||
| 774 | #define GT64260_TIMR_CNTR_4_7_CNTL 0x0964 | ||
| 775 | #define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968 | ||
| 776 | #define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c | ||
| 777 | |||
| 778 | /* | ||
| 779 | ***************************************************************************** | ||
| 780 | * | ||
| 781 | * Communications Controller | ||
| 782 | * | ||
| 783 | ***************************************************************************** | ||
| 784 | */ | ||
| 785 | |||
| 786 | #define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 | ||
| 787 | #define GT64260_SER_INIT_LAST_DATA 0xf324 | ||
| 788 | #define GT64260_SER_INIT_CONTROL 0xf328 | ||
| 789 | #define GT64260_SER_INIT_STATUS 0xf32c | ||
| 790 | |||
| 791 | #define MV64x60_COMM_ARBITER_CNTL 0xf300 | ||
| 792 | #define MV64x60_COMM_CONFIG 0xb40c | ||
| 793 | #define MV64x60_COMM_XBAR_TO 0xf304 | ||
| 794 | #define MV64x60_COMM_INTR_CAUSE 0xf310 | ||
| 795 | #define MV64x60_COMM_INTR_MASK 0xf314 | ||
| 796 | #define MV64x60_COMM_ERR_ADDR 0xf318 | ||
| 797 | |||
| 798 | #define MV64360_COMM_ARBITER_CNTL 0xf300 | ||
| 799 | |||
| 800 | /* | ||
| 801 | ***************************************************************************** | ||
| 802 | * | ||
| 803 | * IDMA Controller Interface Registers | ||
| 804 | * | ||
| 805 | ***************************************************************************** | ||
| 806 | */ | ||
| 807 | |||
| 808 | /* IDMA Controller Window Registers (8 windows) */ | ||
| 809 | #define MV64360_IDMA2MEM_WINDOWS 8 | ||
| 810 | |||
| 811 | #define MV64360_IDMA2MEM_0_BASE 0x0a00 | ||
| 812 | #define MV64360_IDMA2MEM_0_SIZE 0x0a04 | ||
| 813 | #define MV64360_IDMA2MEM_1_BASE 0x0a08 | ||
| 814 | #define MV64360_IDMA2MEM_1_SIZE 0x0a0c | ||
| 815 | #define MV64360_IDMA2MEM_2_BASE 0x0a10 | ||
| 816 | #define MV64360_IDMA2MEM_2_SIZE 0x0a14 | ||
| 817 | #define MV64360_IDMA2MEM_3_BASE 0x0a18 | ||
| 818 | #define MV64360_IDMA2MEM_3_SIZE 0x0a1c | ||
| 819 | #define MV64360_IDMA2MEM_4_BASE 0x0a20 | ||
| 820 | #define MV64360_IDMA2MEM_4_SIZE 0x0a24 | ||
| 821 | #define MV64360_IDMA2MEM_5_BASE 0x0a28 | ||
| 822 | #define MV64360_IDMA2MEM_5_SIZE 0x0a2c | ||
| 823 | #define MV64360_IDMA2MEM_6_BASE 0x0a30 | ||
| 824 | #define MV64360_IDMA2MEM_6_SIZE 0x0a34 | ||
| 825 | #define MV64360_IDMA2MEM_7_BASE 0x0a38 | ||
| 826 | #define MV64360_IDMA2MEM_7_SIZE 0x0a3c | ||
| 827 | |||
| 828 | #define MV64360_IDMA2MEM_SNOOP_NONE 0x00000000 | ||
| 829 | #define MV64360_IDMA2MEM_SNOOP_WT 0x00001000 | ||
| 830 | #define MV64360_IDMA2MEM_SNOOP_WB 0x00002000 | ||
| 831 | |||
| 832 | #define MV64360_IDMA2MEM_BAR_ENABLE 0x0a80 | ||
| 833 | |||
| 834 | #define MV64360_IDMA2MEM_ACC_PROT_0 0x0a70 | ||
| 835 | #define MV64360_IDMA2MEM_ACC_PROT_1 0x0a74 | ||
| 836 | #define MV64360_IDMA2MEM_ACC_PROT_2 0x0a78 | ||
| 837 | #define MV64360_IDMA2MEM_ACC_PROT_3 0x0a7c | ||
| 838 | |||
| 839 | #define MV64x60_IDMA_0_OFFSET 0x0800 | ||
| 840 | #define MV64x60_IDMA_1_OFFSET 0x0804 | ||
| 841 | #define MV64x60_IDMA_2_OFFSET 0x0808 | ||
| 842 | #define MV64x60_IDMA_3_OFFSET 0x080c | ||
| 843 | #define MV64x60_IDMA_4_OFFSET 0x0900 | ||
| 844 | #define MV64x60_IDMA_5_OFFSET 0x0904 | ||
| 845 | #define MV64x60_IDMA_6_OFFSET 0x0908 | ||
| 846 | #define MV64x60_IDMA_7_OFFSET 0x090c | ||
| 847 | |||
| 848 | #define MV64x60_IDMA_BYTE_COUNT (0x0800 - MV64x60_IDMA_0_OFFSET) | ||
| 849 | #define MV64x60_IDMA_SRC_ADDR (0x0810 - MV64x60_IDMA_0_OFFSET) | ||
| 850 | #define MV64x60_IDMA_DST_ADDR (0x0820 - MV64x60_IDMA_0_OFFSET) | ||
| 851 | #define MV64x60_IDMA_NEXT_DESC (0x0830 - MV64x60_IDMA_0_OFFSET) | ||
| 852 | #define MV64x60_IDMA_CUR_DESC (0x0870 - MV64x60_IDMA_0_OFFSET) | ||
| 853 | #define MV64x60_IDMA_SRC_PCI_ADDR_HI (0x0890 - MV64x60_IDMA_0_OFFSET) | ||
| 854 | #define MV64x60_IDMA_DST_PCI_ADDR_HI (0x08a0 - MV64x60_IDMA_0_OFFSET) | ||
| 855 | #define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI (0x08b0 - MV64x60_IDMA_0_OFFSET) | ||
| 856 | #define MV64x60_IDMA_CONTROL_LO (0x0840 - MV64x60_IDMA_0_OFFSET) | ||
| 857 | #define MV64x60_IDMA_CONTROL_HI (0x0880 - MV64x60_IDMA_0_OFFSET) | ||
| 858 | |||
| 859 | #define MV64x60_IDMA_0_3_ARBITER_CNTL 0x0860 | ||
| 860 | #define MV64x60_IDMA_4_7_ARBITER_CNTL 0x0960 | ||
| 861 | |||
| 862 | #define MV64x60_IDMA_0_3_XBAR_TO 0x08d0 | ||
| 863 | #define MV64x60_IDMA_4_7_XBAR_TO 0x09d0 | ||
| 864 | |||
| 865 | #define MV64x60_IDMA_0_3_INTR_CAUSE 0x08c0 | ||
| 866 | #define MV64x60_IDMA_0_3_INTR_MASK 0x08c4 | ||
| 867 | #define MV64x60_IDMA_0_3_ERROR_ADDR 0x08c8 | ||
| 868 | #define MV64x60_IDMA_0_3_ERROR_SELECT 0x08cc | ||
| 869 | #define MV64x60_IDMA_4_7_INTR_CAUSE 0x09c0 | ||
| 870 | #define MV64x60_IDMA_4_7_INTR_MASK 0x09c4 | ||
| 871 | #define MV64x60_IDMA_4_7_ERROR_ADDR 0x09c8 | ||
| 872 | #define MV64x60_IDMA_4_7_ERROR_SELECT 0x09cc | ||
| 873 | |||
| 874 | /* | ||
| 875 | ***************************************************************************** | ||
| 876 | * | ||
| 877 | * Watchdog Timer Interface Registers | ||
| 878 | * | ||
| 879 | ***************************************************************************** | ||
| 880 | */ | ||
| 881 | |||
| 882 | #define MV64x60_WDT_WDC 0xb410 | ||
| 883 | #define MV64x60_WDT_WDV 0xb414 | ||
| 884 | |||
| 885 | |||
| 886 | /* | ||
| 887 | ***************************************************************************** | ||
| 888 | * | ||
| 889 | * General Purpose Pins Controller Interface Registers | ||
| 890 | * | ||
| 891 | ***************************************************************************** | ||
| 892 | */ | ||
| 893 | |||
| 894 | #define MV64x60_GPP_IO_CNTL 0xf100 | ||
| 895 | #define MV64x60_GPP_LEVEL_CNTL 0xf110 | ||
| 896 | #define MV64x60_GPP_VALUE 0xf104 | ||
| 897 | #define MV64x60_GPP_INTR_CAUSE 0xf108 | ||
| 898 | #define MV64x60_GPP_INTR_MASK 0xf10c | ||
| 899 | #define MV64x60_GPP_VALUE_SET 0xf118 | ||
| 900 | #define MV64x60_GPP_VALUE_CLR 0xf11c | ||
| 901 | |||
| 902 | |||
| 903 | /* | ||
| 904 | ***************************************************************************** | ||
| 905 | * | ||
| 906 | * Multi-Purpose Pins Controller Interface Registers | ||
| 907 | * | ||
| 908 | ***************************************************************************** | ||
| 909 | */ | ||
| 910 | |||
| 911 | #define MV64x60_MPP_CNTL_0 0xf000 | ||
| 912 | #define MV64x60_MPP_CNTL_1 0xf004 | ||
| 913 | #define MV64x60_MPP_CNTL_2 0xf008 | ||
| 914 | #define MV64x60_MPP_CNTL_3 0xf00c | ||
| 915 | #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 | ||
| 916 | |||
| 917 | #define MV64x60_ETH_BAR_GAP 0x8 | ||
| 918 | #define MV64x60_ETH_SIZE_REG_GAP 0x8 | ||
| 919 | #define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 | ||
| 920 | #define MV64x60_ETH_PORT_ACCESS_CTRL_GAP 0x4 | ||
| 921 | |||
| 922 | #define MV64x60_EBAR_ATTR_DRAM_CS0 0x00000E00 | ||
| 923 | #define MV64x60_EBAR_ATTR_DRAM_CS1 0x00000D00 | ||
| 924 | #define MV64x60_EBAR_ATTR_DRAM_CS2 0x00000B00 | ||
| 925 | #define MV64x60_EBAR_ATTR_DRAM_CS3 0x00000700 | ||
| 926 | |||
| 927 | #define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 | ||
| 928 | #define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 | ||
| 929 | #define MV64x60_EBAR_ATTR_CBS_SRAM 0x00000000 | ||
| 930 | #define MV64x60_EBAR_ATTR_CBS_CPU_BUS 0x00000800 | ||
| 931 | |||
| 932 | |||
| 933 | /* | ||
| 934 | ***************************************************************************** | ||
| 935 | * | ||
| 936 | * Interrupt Controller Interface Registers | ||
| 937 | * | ||
| 938 | ***************************************************************************** | ||
| 939 | */ | ||
| 940 | |||
| 941 | #define GT64260_IC_OFFSET 0x0c18 | ||
| 942 | |||
| 943 | #define GT64260_IC_MAIN_CAUSE_LO 0x0c18 | ||
| 944 | #define GT64260_IC_MAIN_CAUSE_HI 0x0c68 | ||
| 945 | #define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c | ||
| 946 | #define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c | ||
| 947 | #define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 | ||
| 948 | #define GT64260_IC_PCI0_INTR_MASK_LO 0x0c24 | ||
| 949 | #define GT64260_IC_PCI0_INTR_MASK_HI 0x0c64 | ||
| 950 | #define GT64260_IC_PCI0_SELECT_CAUSE 0x0c74 | ||
| 951 | #define GT64260_IC_PCI1_INTR_MASK_LO 0x0ca4 | ||
| 952 | #define GT64260_IC_PCI1_INTR_MASK_HI 0x0ce4 | ||
| 953 | #define GT64260_IC_PCI1_SELECT_CAUSE 0x0cf4 | ||
| 954 | #define GT64260_IC_CPU_INT_0_MASK 0x0e60 | ||
| 955 | #define GT64260_IC_CPU_INT_1_MASK 0x0e64 | ||
| 956 | #define GT64260_IC_CPU_INT_2_MASK 0x0e68 | ||
| 957 | #define GT64260_IC_CPU_INT_3_MASK 0x0e6c | ||
| 958 | |||
| 959 | #define MV64360_IC_OFFSET 0x0000 | ||
| 960 | |||
| 961 | #define MV64360_IC_MAIN_CAUSE_LO 0x0004 | ||
| 962 | #define MV64360_IC_MAIN_CAUSE_HI 0x000c | ||
| 963 | #define MV64360_IC_CPU0_INTR_MASK_LO 0x0014 | ||
| 964 | #define MV64360_IC_CPU0_INTR_MASK_HI 0x001c | ||
| 965 | #define MV64360_IC_CPU0_SELECT_CAUSE 0x0024 | ||
| 966 | #define MV64360_IC_CPU1_INTR_MASK_LO 0x0034 | ||
| 967 | #define MV64360_IC_CPU1_INTR_MASK_HI 0x003c | ||
| 968 | #define MV64360_IC_CPU1_SELECT_CAUSE 0x0044 | ||
| 969 | #define MV64360_IC_INT0_MASK_LO 0x0054 | ||
| 970 | #define MV64360_IC_INT0_MASK_HI 0x005c | ||
| 971 | #define MV64360_IC_INT0_SELECT_CAUSE 0x0064 | ||
| 972 | #define MV64360_IC_INT1_MASK_LO 0x0074 | ||
| 973 | #define MV64360_IC_INT1_MASK_HI 0x007c | ||
| 974 | #define MV64360_IC_INT1_SELECT_CAUSE 0x0084 | ||
| 975 | |||
| 976 | #endif /* __ASMPPC_MV64x60_DEFS_H */ | ||
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h deleted file mode 100644 index 3909a2eec286..000000000000 --- a/include/asm-ppc/ocp.h +++ /dev/null | |||
| @@ -1,204 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * ocp.h | ||
| 3 | * | ||
| 4 | * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) | ||
| 5 | * Mipsys - France | ||
| 6 | * | ||
| 7 | * Derived from work (c) Armin Kuster akuster@pacbell.net | ||
| 8 | * | ||
| 9 | * Additional support and port to 2.6 LDM/sysfs by | ||
| 10 | * Matt Porter <mporter@kernel.crashing.org> | ||
| 11 | * Copyright 2003-2004 MontaVista Software, Inc. | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify it | ||
| 14 | * under the terms of the GNU General Public License as published by the | ||
| 15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 16 | * option) any later version. | ||
| 17 | * | ||
| 18 | * TODO: - Add get/put interface & fixup locking to provide same API for | ||
| 19 | * 2.4 and 2.5 | ||
| 20 | * - Rework PM callbacks | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifdef __KERNEL__ | ||
| 24 | #ifndef __OCP_H__ | ||
| 25 | #define __OCP_H__ | ||
| 26 | |||
| 27 | #include <linux/init.h> | ||
| 28 | #include <linux/list.h> | ||
| 29 | #include <linux/device.h> | ||
| 30 | #include <linux/rwsem.h> | ||
| 31 | |||
| 32 | #include <asm/mmu.h> | ||
| 33 | #include <asm/ocp_ids.h> | ||
| 34 | |||
| 35 | #ifdef CONFIG_PPC_OCP | ||
| 36 | |||
| 37 | #define OCP_MAX_IRQS 7 | ||
| 38 | #define MAX_EMACS 4 | ||
| 39 | #define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */ | ||
| 40 | #define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */ | ||
| 41 | #define OCP_NULL_TYPE -1 /* used to mark end of list */ | ||
| 42 | #define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */ | ||
| 43 | #define OCP_PADDR_NA 0 /* No MMIO registers */ | ||
| 44 | |||
| 45 | #define OCP_ANY_ID (~0) | ||
| 46 | #define OCP_ANY_INDEX -1 | ||
| 47 | |||
| 48 | extern struct list_head ocp_devices; | ||
| 49 | extern struct rw_semaphore ocp_devices_sem; | ||
| 50 | |||
| 51 | struct ocp_device_id { | ||
| 52 | unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */ | ||
| 53 | unsigned long driver_data; /* Data private to the driver */ | ||
| 54 | }; | ||
| 55 | |||
| 56 | |||
| 57 | /* | ||
| 58 | * Static definition of an OCP device. | ||
| 59 | * | ||
| 60 | * @vendor: Vendor code. It is _STRONGLY_ discouraged to use | ||
| 61 | * the vendor code as a way to match a unique device, | ||
| 62 | * though I kept that possibility open, you should | ||
| 63 | * really define different function codes for different | ||
| 64 | * device types | ||
| 65 | * @function: This is the function code for this device. | ||
| 66 | * @index: This index is used for mapping the Nth function of a | ||
| 67 | * given core. This is typically used for cross-driver | ||
| 68 | * matching, like looking for a given MAL or ZMII from | ||
| 69 | * an EMAC or for getting to the proper set of DCRs. | ||
| 70 | * Indices are no longer magically calculated based on | ||
| 71 | * structure ordering, they have to be actually coded | ||
| 72 | * into the ocp_def to avoid any possible confusion | ||
| 73 | * I _STRONGLY_ (again ? wow !) encourage anybody relying | ||
| 74 | * on index mapping to encode the "target" index in an | ||
| 75 | * associated structure pointed to by "additions", see | ||
| 76 | * how it's done for the EMAC driver. | ||
| 77 | * @paddr: Device physical address (may not mean anything...) | ||
| 78 | * @irq: Interrupt line for this device (TODO: think about making | ||
| 79 | * an array with this) | ||
| 80 | * @pm: Currently, contains the bitmask in CPMFR DCR for the device | ||
| 81 | * @additions: Optionally points to a function specific structure | ||
| 82 | * providing additional informations for a given device | ||
| 83 | * instance. It's currently used by the EMAC driver for MAL | ||
| 84 | * channel & ZMII port mapping among others. | ||
| 85 | * @show: Optionally points to a function specific structure | ||
| 86 | * providing a sysfs show routine for additions fields. | ||
| 87 | */ | ||
| 88 | struct ocp_def { | ||
| 89 | unsigned int vendor; | ||
| 90 | unsigned int function; | ||
| 91 | int index; | ||
| 92 | phys_addr_t paddr; | ||
| 93 | int irq; | ||
| 94 | unsigned long pm; | ||
| 95 | void *additions; | ||
| 96 | void (*show)(struct device *); | ||
| 97 | }; | ||
| 98 | |||
| 99 | |||
| 100 | /* Struct for a given device instance */ | ||
| 101 | struct ocp_device { | ||
| 102 | struct list_head link; | ||
| 103 | char name[80]; /* device name */ | ||
| 104 | struct ocp_def *def; /* device definition */ | ||
| 105 | void *drvdata; /* driver data for this device */ | ||
| 106 | struct ocp_driver *driver; | ||
| 107 | u32 current_state; /* Current operating state. In ACPI-speak, | ||
| 108 | this is D0-D3, D0 being fully functional, | ||
| 109 | and D3 being off. */ | ||
| 110 | struct device dev; | ||
| 111 | }; | ||
| 112 | |||
| 113 | struct ocp_driver { | ||
| 114 | struct list_head node; | ||
| 115 | char *name; | ||
| 116 | const struct ocp_device_id *id_table; /* NULL if wants all devices */ | ||
| 117 | int (*probe) (struct ocp_device *dev); /* New device inserted */ | ||
| 118 | void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | ||
| 119 | int (*suspend) (struct ocp_device *dev, pm_message_t state); /* Device suspended */ | ||
| 120 | int (*resume) (struct ocp_device *dev); /* Device woken up */ | ||
| 121 | struct device_driver driver; | ||
| 122 | }; | ||
| 123 | |||
| 124 | #define to_ocp_dev(n) container_of(n, struct ocp_device, dev) | ||
| 125 | #define to_ocp_drv(n) container_of(n, struct ocp_driver, driver) | ||
| 126 | |||
| 127 | /* Similar to the helpers above, these manipulate per-ocp_dev | ||
| 128 | * driver-specific data. Currently stored as ocp_dev::ocpdev, | ||
| 129 | * a void pointer, but it is not present on older kernels. | ||
| 130 | */ | ||
| 131 | static inline void * | ||
| 132 | ocp_get_drvdata(struct ocp_device *pdev) | ||
| 133 | { | ||
| 134 | return pdev->drvdata; | ||
| 135 | } | ||
| 136 | |||
| 137 | static inline void | ||
| 138 | ocp_set_drvdata(struct ocp_device *pdev, void *data) | ||
| 139 | { | ||
| 140 | pdev->drvdata = data; | ||
| 141 | } | ||
| 142 | |||
| 143 | #if defined (CONFIG_PM) | ||
| 144 | /* | ||
| 145 | * This is right for the IBM 405 and 440 but will need to be | ||
| 146 | * generalized if the OCP stuff gets used on other processors. | ||
| 147 | */ | ||
| 148 | static inline void | ||
| 149 | ocp_force_power_off(struct ocp_device *odev) | ||
| 150 | { | ||
| 151 | mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm); | ||
| 152 | } | ||
| 153 | |||
| 154 | static inline void | ||
| 155 | ocp_force_power_on(struct ocp_device *odev) | ||
| 156 | { | ||
| 157 | mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm); | ||
| 158 | } | ||
| 159 | #else | ||
| 160 | #define ocp_force_power_off(x) (void)(x) | ||
| 161 | #define ocp_force_power_on(x) (void)(x) | ||
| 162 | #endif | ||
| 163 | |||
| 164 | /* Register/Unregister an OCP driver */ | ||
| 165 | extern int ocp_register_driver(struct ocp_driver *drv); | ||
| 166 | extern void ocp_unregister_driver(struct ocp_driver *drv); | ||
| 167 | |||
| 168 | /* Build list of devices */ | ||
| 169 | extern int ocp_early_init(void) __init; | ||
| 170 | |||
| 171 | /* Find a device by index */ | ||
| 172 | extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index); | ||
| 173 | |||
| 174 | /* Get a def by index */ | ||
| 175 | extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index); | ||
| 176 | |||
| 177 | /* Add a device by index */ | ||
| 178 | extern int ocp_add_one_device(struct ocp_def *def); | ||
| 179 | |||
| 180 | /* Remove a device by index */ | ||
| 181 | extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index); | ||
| 182 | |||
| 183 | /* Iterate over devices and execute a routine */ | ||
| 184 | extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg); | ||
| 185 | |||
| 186 | /* Sysfs support */ | ||
| 187 | #define OCP_SYSFS_ADDTL(type, format, name, field) \ | ||
| 188 | static ssize_t \ | ||
| 189 | show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf) \ | ||
| 190 | { \ | ||
| 191 | struct ocp_device *odev = to_ocp_dev(dev); \ | ||
| 192 | type *add = odev->def->additions; \ | ||
| 193 | \ | ||
| 194 | return sprintf(buf, format, add->field); \ | ||
| 195 | } \ | ||
| 196 | static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL); | ||
| 197 | |||
| 198 | #ifdef CONFIG_IBM_OCP | ||
| 199 | #include <asm/ibm_ocp.h> | ||
| 200 | #endif | ||
| 201 | |||
| 202 | #endif /* CONFIG_PPC_OCP */ | ||
| 203 | #endif /* __OCP_H__ */ | ||
| 204 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h deleted file mode 100644 index 8ae4b311a37c..000000000000 --- a/include/asm-ppc/ocp_ids.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * ocp_ids.h | ||
| 3 | * | ||
| 4 | * OCP device ids based on the ideas from PCI | ||
| 5 | * | ||
| 6 | * The numbers below are almost completely arbitrary, and in fact | ||
| 7 | * strings might work better. -- paulus | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Vender device | ||
| 17 | * [xxxx] [xxxx] | ||
| 18 | * | ||
| 19 | * Keep in order, please | ||
| 20 | */ | ||
| 21 | |||
| 22 | /* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */ | ||
| 23 | |||
| 24 | #define OCP_VENDOR_INVALID 0x0000 | ||
| 25 | #define OCP_VENDOR_ARM 0x0004 | ||
| 26 | #define OCP_VENDOR_FREESCALE 0x1057 | ||
| 27 | #define OCP_VENDOR_IBM 0x1014 | ||
| 28 | #define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE | ||
| 29 | #define OCP_VENDOR_XILINX 0x10ee | ||
| 30 | #define OCP_VENDOR_UNKNOWN 0xFFFF | ||
| 31 | |||
| 32 | /* device identification */ | ||
| 33 | |||
| 34 | /* define type */ | ||
| 35 | #define OCP_FUNC_INVALID 0x0000 | ||
| 36 | |||
| 37 | /* system 0x0001 - 0x001F */ | ||
| 38 | |||
| 39 | /* Timers 0x0020 - 0x002F */ | ||
| 40 | |||
| 41 | /* Serial 0x0030 - 0x006F*/ | ||
| 42 | #define OCP_FUNC_16550 0x0031 | ||
| 43 | #define OCP_FUNC_IIC 0x0032 | ||
| 44 | #define OCP_FUNC_USB 0x0033 | ||
| 45 | #define OCP_FUNC_PSC_UART 0x0034 | ||
| 46 | |||
| 47 | /* Memory devices 0x0090 - 0x009F */ | ||
| 48 | #define OCP_FUNC_MAL 0x0090 | ||
| 49 | #define OCP_FUNC_DMA 0x0091 | ||
| 50 | |||
| 51 | /* Display 0x00A0 - 0x00AF */ | ||
| 52 | |||
| 53 | /* Sound 0x00B0 - 0x00BF */ | ||
| 54 | |||
| 55 | /* Mass Storage 0x00C0 - 0xxCF */ | ||
| 56 | #define OCP_FUNC_IDE 0x00C0 | ||
| 57 | |||
| 58 | /* Misc 0x00D0 - 0x00DF*/ | ||
| 59 | #define OCP_FUNC_GPIO 0x00D0 | ||
| 60 | #define OCP_FUNC_ZMII 0x00D1 | ||
| 61 | #define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */ | ||
| 62 | #define OCP_FUNC_RGMII 0x00D3 | ||
| 63 | #define OCP_FUNC_TAH 0x00D4 | ||
| 64 | #define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */ | ||
| 65 | |||
| 66 | /* Network 0x0200 - 0x02FF */ | ||
| 67 | #define OCP_FUNC_EMAC 0x0200 | ||
| 68 | #define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */ | ||
| 69 | |||
| 70 | /* Bridge devices 0xE00 - 0xEFF */ | ||
| 71 | #define OCP_FUNC_OPB 0x0E00 | ||
| 72 | |||
| 73 | #define OCP_FUNC_UNKNOWN 0xFFFF | ||
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h deleted file mode 100644 index 778d5726212c..000000000000 --- a/include/asm-ppc/open_pic.h +++ /dev/null | |||
| @@ -1,98 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997 Geert Uytterhoeven | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _PPC_KERNEL_OPEN_PIC_H | ||
| 13 | #define _PPC_KERNEL_OPEN_PIC_H | ||
| 14 | |||
| 15 | #include <linux/irq.h> | ||
| 16 | |||
| 17 | #define OPENPIC_SIZE 0x40000 | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Non-offset'ed vector numbers | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define OPENPIC_VEC_TIMER 110 /* and up */ | ||
| 24 | #define OPENPIC_VEC_IPI 118 /* and up */ | ||
| 25 | #define OPENPIC_VEC_SPURIOUS 255 | ||
| 26 | |||
| 27 | /* Priorities */ | ||
| 28 | #define OPENPIC_PRIORITY_IPI_BASE 10 | ||
| 29 | #define OPENPIC_PRIORITY_DEFAULT 4 | ||
| 30 | #define OPENPIC_PRIORITY_NMI 9 | ||
| 31 | |||
| 32 | /* OpenPIC IRQ controller structure */ | ||
| 33 | extern struct hw_interrupt_type open_pic; | ||
| 34 | |||
| 35 | /* OpenPIC IPI controller structure */ | ||
| 36 | #ifdef CONFIG_SMP | ||
| 37 | extern struct hw_interrupt_type open_pic_ipi; | ||
| 38 | #endif /* CONFIG_SMP */ | ||
| 39 | |||
| 40 | extern u_int OpenPIC_NumInitSenses; | ||
| 41 | extern u_char *OpenPIC_InitSenses; | ||
| 42 | extern void __iomem * OpenPIC_Addr; | ||
| 43 | extern int epic_serial_mode; | ||
| 44 | |||
| 45 | /* Exported functions */ | ||
| 46 | extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr); | ||
| 47 | extern void openpic_init(int linux_irq_offset); | ||
| 48 | extern void openpic_init_nmi_irq(u_int irq); | ||
| 49 | extern void openpic_set_irq_priority(u_int irq, u_int pri); | ||
| 50 | extern void openpic_hookup_cascade(u_int irq, char *name, | ||
| 51 | int (*cascade_fn)(void)); | ||
| 52 | extern u_int openpic_irq(void); | ||
| 53 | extern void openpic_eoi(void); | ||
| 54 | extern void openpic_request_IPIs(void); | ||
| 55 | extern void do_openpic_setup_cpu(void); | ||
| 56 | extern int openpic_get_irq(void); | ||
| 57 | extern void openpic_reset_processor_phys(u_int cpumask); | ||
| 58 | extern void openpic_setup_ISU(int isu_num, unsigned long addr); | ||
| 59 | extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask); | ||
| 60 | extern void smp_openpic_message_pass(int target, int msg); | ||
| 61 | extern void openpic_set_k2_cascade(int irq); | ||
| 62 | extern void openpic_set_priority(u_int pri); | ||
| 63 | extern u_int openpic_get_priority(void); | ||
| 64 | |||
| 65 | extern inline int openpic_to_irq(int irq) | ||
| 66 | { | ||
| 67 | /* IRQ 0 usually means 'disabled'.. don't mess with it | ||
| 68 | * exceptions to this (sandpoint maybe?) | ||
| 69 | * shouldn't use openpic_to_irq | ||
| 70 | */ | ||
| 71 | if (irq != 0){ | ||
| 72 | return irq += NUM_8259_INTERRUPTS; | ||
| 73 | } else { | ||
| 74 | return 0; | ||
| 75 | } | ||
| 76 | } | ||
| 77 | /* Support for second openpic on G5 macs */ | ||
| 78 | |||
| 79 | // FIXME: To be replaced by sane cascaded controller management */ | ||
| 80 | |||
| 81 | #define PMAC_OPENPIC2_OFFSET 128 | ||
| 82 | |||
| 83 | #define OPENPIC2_VEC_TIMER 110 /* and up */ | ||
| 84 | #define OPENPIC2_VEC_IPI 118 /* and up */ | ||
| 85 | #define OPENPIC2_VEC_SPURIOUS 127 | ||
| 86 | |||
| 87 | |||
| 88 | extern void* OpenPIC2_Addr; | ||
| 89 | |||
| 90 | /* Exported functions */ | ||
| 91 | extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr); | ||
| 92 | extern void openpic2_init(int linux_irq_offset); | ||
| 93 | extern void openpic2_init_nmi_irq(u_int irq); | ||
| 94 | extern u_int openpic2_irq(void); | ||
| 95 | extern void openpic2_eoi(void); | ||
| 96 | extern int openpic2_get_irq(void); | ||
| 97 | extern void openpic2_setup_ISU(int isu_num, unsigned long addr); | ||
| 98 | #endif /* _PPC_KERNEL_OPEN_PIC_H */ | ||
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h deleted file mode 100644 index 37e4756b6b2d..000000000000 --- a/include/asm-ppc/page.h +++ /dev/null | |||
| @@ -1,140 +0,0 @@ | |||
| 1 | #ifndef _PPC_PAGE_H | ||
| 2 | #define _PPC_PAGE_H | ||
| 3 | |||
| 4 | #include <asm/asm-compat.h> | ||
| 5 | |||
| 6 | /* PAGE_SHIFT determines the page size */ | ||
| 7 | #define PAGE_SHIFT 12 | ||
| 8 | #define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT) | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Subtle: this is an int (not an unsigned long) and so it | ||
| 12 | * gets extended to 64 bits the way want (i.e. with 1s). -- paulus | ||
| 13 | */ | ||
| 14 | #define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | |||
| 18 | /* This must match what is in arch/ppc/Makefile */ | ||
| 19 | #define PAGE_OFFSET CONFIG_KERNEL_START | ||
| 20 | #define KERNELBASE PAGE_OFFSET | ||
| 21 | #define is_kernel_addr(x) ((x) >= PAGE_OFFSET) | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | |||
| 25 | /* | ||
| 26 | * The basic type of a PTE - 64 bits for those CPUs with > 32 bit | ||
| 27 | * physical addressing. For now this just the IBM PPC440. | ||
| 28 | */ | ||
| 29 | #ifdef CONFIG_PTE_64BIT | ||
| 30 | typedef unsigned long long pte_basic_t; | ||
| 31 | #define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */ | ||
| 32 | #define PTE_FMT "%16Lx" | ||
| 33 | #else | ||
| 34 | typedef unsigned long pte_basic_t; | ||
| 35 | #define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */ | ||
| 36 | #define PTE_FMT "%.8lx" | ||
| 37 | #endif | ||
| 38 | |||
| 39 | /* align addr on a size boundary - adjust address up/down if needed */ | ||
| 40 | #define _ALIGN_UP(addr,size) (((addr)+((size)-1))&(~((size)-1))) | ||
| 41 | #define _ALIGN_DOWN(addr,size) ((addr)&(~((size)-1))) | ||
| 42 | |||
| 43 | /* align addr on a size boundary - adjust address up if needed */ | ||
| 44 | #define _ALIGN(addr,size) _ALIGN_UP(addr,size) | ||
| 45 | |||
| 46 | /* to align the pointer to the (next) page boundary */ | ||
| 47 | #define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE) | ||
| 48 | |||
| 49 | |||
| 50 | #undef STRICT_MM_TYPECHECKS | ||
| 51 | |||
| 52 | #ifdef STRICT_MM_TYPECHECKS | ||
| 53 | /* | ||
| 54 | * These are used to make use of C type-checking.. | ||
| 55 | */ | ||
| 56 | typedef struct { pte_basic_t pte; } pte_t; | ||
| 57 | typedef struct { unsigned long pmd; } pmd_t; | ||
| 58 | typedef struct { unsigned long pgd; } pgd_t; | ||
| 59 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
| 60 | |||
| 61 | #define pte_val(x) ((x).pte) | ||
| 62 | #define pmd_val(x) ((x).pmd) | ||
| 63 | #define pgd_val(x) ((x).pgd) | ||
| 64 | #define pgprot_val(x) ((x).pgprot) | ||
| 65 | |||
| 66 | #define __pte(x) ((pte_t) { (x) } ) | ||
| 67 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
| 68 | #define __pgd(x) ((pgd_t) { (x) } ) | ||
| 69 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
| 70 | |||
| 71 | #else | ||
| 72 | /* | ||
| 73 | * .. while these make it easier on the compiler | ||
| 74 | */ | ||
| 75 | typedef pte_basic_t pte_t; | ||
| 76 | typedef unsigned long pmd_t; | ||
| 77 | typedef unsigned long pgd_t; | ||
| 78 | typedef unsigned long pgprot_t; | ||
| 79 | |||
| 80 | #define pte_val(x) (x) | ||
| 81 | #define pmd_val(x) (x) | ||
| 82 | #define pgd_val(x) (x) | ||
| 83 | #define pgprot_val(x) (x) | ||
| 84 | |||
| 85 | #define __pte(x) (x) | ||
| 86 | #define __pmd(x) (x) | ||
| 87 | #define __pgd(x) (x) | ||
| 88 | #define __pgprot(x) (x) | ||
| 89 | |||
| 90 | #endif | ||
| 91 | |||
| 92 | struct page; | ||
| 93 | extern void clear_pages(void *page, int order); | ||
| 94 | static inline void clear_page(void *page) { clear_pages(page, 0); } | ||
| 95 | extern void copy_page(void *to, void *from); | ||
| 96 | extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg); | ||
| 97 | extern void copy_user_page(void *to, void *from, unsigned long vaddr, | ||
| 98 | struct page *pg); | ||
| 99 | |||
| 100 | #define PPC_MEMSTART 0 | ||
| 101 | #define PPC_MEMOFFSET PAGE_OFFSET | ||
| 102 | |||
| 103 | #define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET) | ||
| 104 | #define ___va(paddr) ((paddr)+PPC_MEMOFFSET) | ||
| 105 | |||
| 106 | extern int page_is_ram(unsigned long pfn); | ||
| 107 | |||
| 108 | #define __pa(x) ___pa((unsigned long)(x)) | ||
| 109 | #define __va(x) ((void *)(___va((unsigned long)(x)))) | ||
| 110 | |||
| 111 | #define ARCH_PFN_OFFSET 0 | ||
| 112 | #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) | ||
| 113 | #define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT) | ||
| 114 | |||
| 115 | #define pfn_valid(pfn) ((pfn) < max_mapnr) | ||
| 116 | #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) | ||
| 117 | |||
| 118 | /* Pure 2^n version of get_order */ | ||
| 119 | extern __inline__ int get_order(unsigned long size) | ||
| 120 | { | ||
| 121 | int lz; | ||
| 122 | |||
| 123 | size = (size-1) >> PAGE_SHIFT; | ||
| 124 | asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size)); | ||
| 125 | return 32 - lz; | ||
| 126 | } | ||
| 127 | |||
| 128 | typedef struct page *pgtable_t; | ||
| 129 | |||
| 130 | #endif /* __ASSEMBLY__ */ | ||
| 131 | |||
| 132 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ | ||
| 133 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | ||
| 134 | |||
| 135 | /* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */ | ||
| 136 | #define __HAVE_ARCH_GATE_AREA 1 | ||
| 137 | |||
| 138 | #include <asm-generic/memory_model.h> | ||
| 139 | #endif /* __KERNEL__ */ | ||
| 140 | #endif /* _PPC_PAGE_H */ | ||
diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h deleted file mode 100644 index 81a2d0fdaf00..000000000000 --- a/include/asm-ppc/pc_serial.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/pc_serial.h | ||
| 3 | * | ||
| 4 | * This is basically a copy of include/asm-i386/serial.h. | ||
| 5 | * It is used on platforms which have an ISA bus and thus are likely | ||
| 6 | * to have PC-style serial ports at the legacy I/O port addresses. | ||
| 7 | * It also includes the definitions for the fourport, accent, boca | ||
| 8 | * and hub6 multiport serial cards, although I have never heard of | ||
| 9 | * anyone using any of those on a PPC platform. -- paulus | ||
| 10 | */ | ||
| 11 | |||
| 12 | |||
| 13 | /* | ||
| 14 | * This assumes you have a 1.8432 MHz clock for your UART. | ||
| 15 | * | ||
| 16 | * It'd be nice if someone built a serial card with a 24.576 MHz | ||
| 17 | * clock, since the 16550A is capable of handling a top speed of 1.5 | ||
| 18 | * megabits/second; but this requires the faster clock. | ||
| 19 | */ | ||
| 20 | #define BASE_BAUD ( 1843200 / 16 ) | ||
| 21 | |||
| 22 | #ifdef CONFIG_SERIAL_MANY_PORTS | ||
| 23 | #define RS_TABLE_SIZE 64 | ||
| 24 | #else | ||
| 25 | #define RS_TABLE_SIZE 4 | ||
| 26 | #endif | ||
| 27 | |||
| 28 | /* Standard COM flags (except for COM4, because of the 8514 problem) */ | ||
| 29 | #ifdef CONFIG_SERIAL_DETECT_IRQ | ||
| 30 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) | ||
| 31 | #define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) | ||
| 32 | #else | ||
| 33 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) | ||
| 34 | #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #define SERIAL_PORT_DFNS \ | ||
| 38 | /* UART CLK PORT IRQ FLAGS */ \ | ||
| 39 | { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ | ||
| 40 | { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ | ||
| 41 | { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ | ||
| 42 | { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ | ||
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h deleted file mode 100644 index 4d35b844bc58..000000000000 --- a/include/asm-ppc/pci-bridge.h +++ /dev/null | |||
| @@ -1,151 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | #ifndef _ASM_PCI_BRIDGE_H | ||
| 3 | #define _ASM_PCI_BRIDGE_H | ||
| 4 | |||
| 5 | #include <linux/ioport.h> | ||
| 6 | #include <linux/pci.h> | ||
| 7 | |||
| 8 | struct device_node; | ||
| 9 | struct pci_controller; | ||
| 10 | |||
| 11 | /* | ||
| 12 | * pci_io_base returns the memory address at which you can access | ||
| 13 | * the I/O space for PCI bus number `bus' (or NULL on error). | ||
| 14 | */ | ||
| 15 | extern void __iomem *pci_bus_io_base(unsigned int bus); | ||
| 16 | extern unsigned long pci_bus_io_base_phys(unsigned int bus); | ||
| 17 | extern unsigned long pci_bus_mem_base_phys(unsigned int bus); | ||
| 18 | |||
| 19 | /* Allocate a new PCI host bridge structure */ | ||
| 20 | extern struct pci_controller* pcibios_alloc_controller(void); | ||
| 21 | |||
| 22 | /* Helper function for setting up resources */ | ||
| 23 | extern void pci_init_resource(struct resource *res, resource_size_t start, | ||
| 24 | resource_size_t end, int flags, char *name); | ||
| 25 | |||
| 26 | /* Get the PCI host controller for a bus */ | ||
| 27 | extern struct pci_controller* pci_bus_to_hose(int bus); | ||
| 28 | |||
| 29 | /* Get the PCI host controller for an OF device */ | ||
| 30 | extern struct pci_controller* | ||
| 31 | pci_find_hose_for_OF_device(struct device_node* node); | ||
| 32 | |||
| 33 | /* Fill up host controller resources from the OF node */ | ||
| 34 | extern void | ||
| 35 | pci_process_bridge_OF_ranges(struct pci_controller *hose, | ||
| 36 | struct device_node *dev, int primary); | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Structure of a PCI controller (host bridge) | ||
| 40 | */ | ||
| 41 | struct pci_controller { | ||
| 42 | int index; /* PCI domain number */ | ||
| 43 | struct pci_controller *next; | ||
| 44 | struct pci_bus *bus; | ||
| 45 | void *arch_data; | ||
| 46 | struct device *parent; | ||
| 47 | |||
| 48 | int first_busno; | ||
| 49 | int last_busno; | ||
| 50 | int bus_offset; | ||
| 51 | |||
| 52 | void __iomem *io_base_virt; | ||
| 53 | resource_size_t io_base_phys; | ||
| 54 | |||
| 55 | /* Some machines (PReP) have a non 1:1 mapping of | ||
| 56 | * the PCI memory space in the CPU bus space | ||
| 57 | */ | ||
| 58 | resource_size_t pci_mem_offset; | ||
| 59 | |||
| 60 | struct pci_ops *ops; | ||
| 61 | volatile unsigned int __iomem *cfg_addr; | ||
| 62 | volatile void __iomem *cfg_data; | ||
| 63 | /* | ||
| 64 | * If set, indirect method will set the cfg_type bit as | ||
| 65 | * needed to generate type 1 configuration transactions. | ||
| 66 | */ | ||
| 67 | int set_cfg_type; | ||
| 68 | |||
| 69 | /* Currently, we limit ourselves to 1 IO range and 3 mem | ||
| 70 | * ranges since the common pci_bus structure can't handle more | ||
| 71 | */ | ||
| 72 | struct resource io_resource; | ||
| 73 | struct resource mem_resources[3]; | ||
| 74 | int mem_resource_count; | ||
| 75 | |||
| 76 | /* Host bridge I/O and Memory space | ||
| 77 | * Used for BAR placement algorithms | ||
| 78 | */ | ||
| 79 | struct resource io_space; | ||
| 80 | struct resource mem_space; | ||
| 81 | }; | ||
| 82 | |||
| 83 | static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) | ||
| 84 | { | ||
| 85 | return bus->sysdata; | ||
| 86 | } | ||
| 87 | |||
| 88 | /* These are used for config access before all the PCI probing | ||
| 89 | has been done. */ | ||
| 90 | int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, | ||
| 91 | int where, u8 *val); | ||
| 92 | int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, | ||
| 93 | int where, u16 *val); | ||
| 94 | int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, | ||
| 95 | int where, u32 *val); | ||
| 96 | int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, | ||
| 97 | int where, u8 val); | ||
| 98 | int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, | ||
| 99 | int where, u16 val); | ||
| 100 | int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, | ||
| 101 | int where, u32 val); | ||
| 102 | |||
| 103 | extern void setup_indirect_pci_nomap(struct pci_controller* hose, | ||
| 104 | void __iomem *cfg_addr, void __iomem *cfg_data); | ||
| 105 | extern void setup_indirect_pci(struct pci_controller* hose, | ||
| 106 | u32 cfg_addr, u32 cfg_data); | ||
| 107 | extern void setup_grackle(struct pci_controller *hose); | ||
| 108 | |||
| 109 | extern unsigned char common_swizzle(struct pci_dev *, unsigned char *); | ||
| 110 | |||
| 111 | /* | ||
| 112 | * The following code swizzles for exactly one bridge. The routine | ||
| 113 | * common_swizzle below handles multiple bridges. But there are a | ||
| 114 | * some boards that don't follow the PCI spec's suggestion so we | ||
| 115 | * break this piece out separately. | ||
| 116 | */ | ||
| 117 | static inline unsigned char bridge_swizzle(unsigned char pin, | ||
| 118 | unsigned char idsel) | ||
| 119 | { | ||
| 120 | return (((pin-1) + idsel) % 4) + 1; | ||
| 121 | } | ||
| 122 | |||
| 123 | /* | ||
| 124 | * The following macro is used to lookup irqs in a standard table | ||
| 125 | * format for those PPC systems that do not already have PCI | ||
| 126 | * interrupts properly routed. | ||
| 127 | */ | ||
| 128 | /* FIXME - double check this */ | ||
| 129 | #define PCI_IRQ_TABLE_LOOKUP \ | ||
| 130 | ({ long _ctl_ = -1; \ | ||
| 131 | if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ | ||
| 132 | _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ | ||
| 133 | _ctl_; }) | ||
| 134 | |||
| 135 | /* | ||
| 136 | * Scan the buses below a given PCI host bridge and assign suitable | ||
| 137 | * resources to all devices found. | ||
| 138 | */ | ||
| 139 | extern int pciauto_bus_scan(struct pci_controller *, int); | ||
| 140 | |||
| 141 | #ifdef CONFIG_PCI | ||
| 142 | extern unsigned long pci_address_to_pio(phys_addr_t address); | ||
| 143 | #else | ||
| 144 | static inline unsigned long pci_address_to_pio(phys_addr_t address) | ||
| 145 | { | ||
| 146 | return (unsigned long)-1; | ||
| 147 | } | ||
| 148 | #endif | ||
| 149 | |||
| 150 | #endif | ||
| 151 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h deleted file mode 100644 index d2442cd72a59..000000000000 --- a/include/asm-ppc/pci.h +++ /dev/null | |||
| @@ -1,156 +0,0 @@ | |||
| 1 | #ifndef __PPC_PCI_H | ||
| 2 | #define __PPC_PCI_H | ||
| 3 | #ifdef __KERNEL__ | ||
| 4 | |||
| 5 | #include <linux/types.h> | ||
| 6 | #include <linux/slab.h> | ||
| 7 | #include <linux/string.h> | ||
| 8 | #include <linux/mm.h> | ||
| 9 | #include <asm/scatterlist.h> | ||
| 10 | #include <asm/io.h> | ||
| 11 | #include <asm/pci-bridge.h> | ||
| 12 | #include <asm-generic/pci-dma-compat.h> | ||
| 13 | |||
| 14 | struct pci_dev; | ||
| 15 | |||
| 16 | /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ | ||
| 17 | #define IOBASE_BRIDGE_NUMBER 0 | ||
| 18 | #define IOBASE_MEMORY 1 | ||
| 19 | #define IOBASE_IO 2 | ||
| 20 | #define IOBASE_ISA_IO 3 | ||
| 21 | #define IOBASE_ISA_MEM 4 | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Set this to 1 if you want the kernel to re-assign all PCI | ||
| 25 | * bus numbers | ||
| 26 | */ | ||
| 27 | extern int pci_assign_all_buses; | ||
| 28 | |||
| 29 | #define pcibios_assign_all_busses() (pci_assign_all_buses) | ||
| 30 | #define pcibios_scan_all_fns(a, b) 0 | ||
| 31 | |||
| 32 | #define PCIBIOS_MIN_IO 0x1000 | ||
| 33 | #define PCIBIOS_MIN_MEM 0x10000000 | ||
| 34 | |||
| 35 | extern inline void pcibios_set_master(struct pci_dev *dev) | ||
| 36 | { | ||
| 37 | /* No special bus mastering setup handling */ | ||
| 38 | } | ||
| 39 | |||
| 40 | extern inline void pcibios_penalize_isa_irq(int irq, int active) | ||
| 41 | { | ||
| 42 | /* We don't do dynamic PCI IRQ allocation */ | ||
| 43 | } | ||
| 44 | |||
| 45 | extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res); | ||
| 46 | |||
| 47 | /* | ||
| 48 | * The PCI bus bridge can translate addresses issued by the processor(s) | ||
| 49 | * into a different address on the PCI bus. On 32-bit cpus, we assume | ||
| 50 | * this mapping is 1-1, but on 64-bit systems it often isn't. | ||
| 51 | * | ||
| 52 | * Obsolete ! Drivers should now use pci_resource_to_bus | ||
| 53 | */ | ||
| 54 | extern unsigned long phys_to_bus(unsigned long pa); | ||
| 55 | extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr); | ||
| 56 | extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr); | ||
| 57 | |||
| 58 | /* The PCI address space does equal the physical memory | ||
| 59 | * address space. The networking and block device layers use | ||
| 60 | * this boolean for bounce buffer decisions. | ||
| 61 | */ | ||
| 62 | #define PCI_DMA_BUS_IS_PHYS (1) | ||
| 63 | |||
| 64 | #ifdef CONFIG_NOT_COHERENT_CACHE | ||
| 65 | /* | ||
| 66 | * pci_unmap_{page,single} are NOPs but pci_dma_sync_single_for_cpu() | ||
| 67 | * and so on are not, so... | ||
| 68 | */ | ||
| 69 | |||
| 70 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ | ||
| 71 | dma_addr_t ADDR_NAME; | ||
| 72 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ | ||
| 73 | __u32 LEN_NAME; | ||
| 74 | #define pci_unmap_addr(PTR, ADDR_NAME) \ | ||
| 75 | ((PTR)->ADDR_NAME) | ||
| 76 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ | ||
| 77 | (((PTR)->ADDR_NAME) = (VAL)) | ||
| 78 | #define pci_unmap_len(PTR, LEN_NAME) \ | ||
| 79 | ((PTR)->LEN_NAME) | ||
| 80 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ | ||
| 81 | (((PTR)->LEN_NAME) = (VAL)) | ||
| 82 | |||
| 83 | #else /* coherent */ | ||
| 84 | |||
| 85 | /* pci_unmap_{page,single} is a nop so... */ | ||
| 86 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) | ||
| 87 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) | ||
| 88 | #define pci_unmap_addr(PTR, ADDR_NAME) (0) | ||
| 89 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | ||
| 90 | #define pci_unmap_len(PTR, LEN_NAME) (0) | ||
| 91 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | ||
| 92 | |||
| 93 | #endif /* CONFIG_NOT_COHERENT_CACHE */ | ||
| 94 | |||
| 95 | #ifdef CONFIG_PCI | ||
| 96 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, | ||
| 97 | enum pci_dma_burst_strategy *strat, | ||
| 98 | unsigned long *strategy_parameter) | ||
| 99 | { | ||
| 100 | *strat = PCI_DMA_BURST_INFINITY; | ||
| 101 | *strategy_parameter = ~0UL; | ||
| 102 | } | ||
| 103 | #endif | ||
| 104 | |||
| 105 | /* Return the index of the PCI controller for device PDEV. */ | ||
| 106 | #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index | ||
| 107 | |||
| 108 | /* Set the name of the bus as it appears in /proc/bus/pci */ | ||
| 109 | static inline int pci_proc_domain(struct pci_bus *bus) | ||
| 110 | { | ||
| 111 | return 0; | ||
| 112 | } | ||
| 113 | |||
| 114 | /* Map a range of PCI memory or I/O space for a device into user space */ | ||
| 115 | int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, | ||
| 116 | enum pci_mmap_state mmap_state, int write_combine); | ||
| 117 | |||
| 118 | /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ | ||
| 119 | #define HAVE_PCI_MMAP 1 | ||
| 120 | |||
| 121 | extern void | ||
| 122 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | ||
| 123 | struct resource *res); | ||
| 124 | |||
| 125 | extern void | ||
| 126 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | ||
| 127 | struct pci_bus_region *region); | ||
| 128 | |||
| 129 | static inline struct resource * | ||
| 130 | pcibios_select_root(struct pci_dev *pdev, struct resource *res) | ||
| 131 | { | ||
| 132 | struct resource *root = NULL; | ||
| 133 | |||
| 134 | if (res->flags & IORESOURCE_IO) | ||
| 135 | root = &ioport_resource; | ||
| 136 | if (res->flags & IORESOURCE_MEM) | ||
| 137 | root = &iomem_resource; | ||
| 138 | |||
| 139 | return root; | ||
| 140 | } | ||
| 141 | |||
| 142 | struct file; | ||
| 143 | extern pgprot_t pci_phys_mem_access_prot(struct file *file, | ||
| 144 | unsigned long pfn, | ||
| 145 | unsigned long size, | ||
| 146 | pgprot_t prot); | ||
| 147 | |||
| 148 | #define HAVE_ARCH_PCI_RESOURCE_TO_USER | ||
| 149 | extern void pci_resource_to_user(const struct pci_dev *dev, int bar, | ||
| 150 | const struct resource *rsrc, | ||
| 151 | resource_size_t *start, resource_size_t *end); | ||
| 152 | |||
| 153 | |||
| 154 | #endif /* __KERNEL__ */ | ||
| 155 | |||
| 156 | #endif /* __PPC_PCI_H */ | ||
diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h deleted file mode 100644 index fd4d1d74cfb1..000000000000 --- a/include/asm-ppc/pgalloc.h +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | #ifndef _PPC_PGALLOC_H | ||
| 3 | #define _PPC_PGALLOC_H | ||
| 4 | |||
| 5 | #include <linux/threads.h> | ||
| 6 | |||
| 7 | extern void __bad_pte(pmd_t *pmd); | ||
| 8 | |||
| 9 | extern pgd_t *pgd_alloc(struct mm_struct *mm); | ||
| 10 | extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); | ||
| 11 | |||
| 12 | /* | ||
| 13 | * We don't have any real pmd's, and this code never triggers because | ||
| 14 | * the pgd will always be present.. | ||
| 15 | */ | ||
| 16 | #define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); }) | ||
| 17 | #define pmd_free(mm, x) do { } while (0) | ||
| 18 | #define __pmd_free_tlb(tlb,x) do { } while (0) | ||
| 19 | #define pgd_populate(mm, pmd, pte) BUG() | ||
| 20 | |||
| 21 | #ifndef CONFIG_BOOKE | ||
| 22 | #define pmd_populate_kernel(mm, pmd, pte) \ | ||
| 23 | (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) | ||
| 24 | #define pmd_populate(mm, pmd, pte) \ | ||
| 25 | (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) | ||
| 26 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 27 | #else | ||
| 28 | #define pmd_populate_kernel(mm, pmd, pte) \ | ||
| 29 | (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) | ||
| 30 | #define pmd_populate(mm, pmd, pte) \ | ||
| 31 | (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) | ||
| 32 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); | ||
| 36 | extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr); | ||
| 37 | extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); | ||
| 38 | extern void pte_free(struct mm_struct *mm, pgtable_t pte); | ||
| 39 | |||
| 40 | #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) | ||
| 41 | |||
| 42 | #define check_pgt_cache() do { } while (0) | ||
| 43 | |||
| 44 | #endif /* _PPC_PGALLOC_H */ | ||
| 45 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h deleted file mode 100644 index 55f9d38e3bf8..000000000000 --- a/include/asm-ppc/pgtable.h +++ /dev/null | |||
| @@ -1,771 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | #ifndef _PPC_PGTABLE_H | ||
| 3 | #define _PPC_PGTABLE_H | ||
| 4 | |||
| 5 | #include <asm-generic/4level-fixup.h> | ||
| 6 | |||
| 7 | |||
| 8 | #ifndef __ASSEMBLY__ | ||
| 9 | #include <linux/sched.h> | ||
| 10 | #include <linux/threads.h> | ||
| 11 | #include <asm/processor.h> /* For TASK_SIZE */ | ||
| 12 | #include <asm/mmu.h> | ||
| 13 | #include <asm/page.h> | ||
| 14 | #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */ | ||
| 15 | struct mm_struct; | ||
| 16 | |||
| 17 | extern unsigned long va_to_phys(unsigned long address); | ||
| 18 | extern pte_t *va_to_pte(unsigned long address); | ||
| 19 | extern unsigned long ioremap_bot, ioremap_base; | ||
| 20 | #endif /* __ASSEMBLY__ */ | ||
| 21 | |||
| 22 | /* | ||
| 23 | * The PowerPC MMU uses a hash table containing PTEs, together with | ||
| 24 | * a set of 16 segment registers (on 32-bit implementations), to define | ||
| 25 | * the virtual to physical address mapping. | ||
| 26 | * | ||
| 27 | * We use the hash table as an extended TLB, i.e. a cache of currently | ||
| 28 | * active mappings. We maintain a two-level page table tree, much | ||
| 29 | * like that used by the i386, for the sake of the Linux memory | ||
| 30 | * management code. Low-level assembler code in hashtable.S | ||
| 31 | * (procedure hash_page) is responsible for extracting ptes from the | ||
| 32 | * tree and putting them into the hash table when necessary, and | ||
| 33 | * updating the accessed and modified bits in the page table tree. | ||
| 34 | */ | ||
| 35 | |||
| 36 | /* | ||
| 37 | * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. | ||
| 38 | * We also use the two level tables, but we can put the real bits in them | ||
| 39 | * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, | ||
| 40 | * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has | ||
| 41 | * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit | ||
| 42 | * based upon user/super access. The TLB does not have accessed nor write | ||
| 43 | * protect. We assume that if the TLB get loaded with an entry it is | ||
| 44 | * accessed, and overload the changed bit for write protect. We use | ||
| 45 | * two bits in the software pte that are supposed to be set to zero in | ||
| 46 | * the TLB entry (24 and 25) for these indicators. Although the level 1 | ||
| 47 | * descriptor contains the guarded and writethrough/copyback bits, we can | ||
| 48 | * set these at the page level since they get copied from the Mx_TWC | ||
| 49 | * register when the TLB entry is loaded. We will use bit 27 for guard, since | ||
| 50 | * that is where it exists in the MD_TWC, and bit 26 for writethrough. | ||
| 51 | * These will get masked from the level 2 descriptor at TLB load time, and | ||
| 52 | * copied to the MD_TWC before it gets loaded. | ||
| 53 | * Large page sizes added. We currently support two sizes, 4K and 8M. | ||
| 54 | * This also allows a TLB hander optimization because we can directly | ||
| 55 | * load the PMD into MD_TWC. The 8M pages are only used for kernel | ||
| 56 | * mapping of well known areas. The PMD (PGD) entries contain control | ||
| 57 | * flags in addition to the address, so care must be taken that the | ||
| 58 | * software no longer assumes these are only pointers. | ||
| 59 | */ | ||
| 60 | |||
| 61 | /* | ||
| 62 | * At present, all PowerPC 400-class processors share a similar TLB | ||
| 63 | * architecture. The instruction and data sides share a unified, | ||
| 64 | * 64-entry, fully-associative TLB which is maintained totally under | ||
| 65 | * software control. In addition, the instruction side has a | ||
| 66 | * hardware-managed, 4-entry, fully-associative TLB which serves as a | ||
| 67 | * first level to the shared TLB. These two TLBs are known as the UTLB | ||
| 68 | * and ITLB, respectively (see "mmu.h" for definitions). | ||
| 69 | */ | ||
| 70 | |||
| 71 | /* | ||
| 72 | * The normal case is that PTEs are 32-bits and we have a 1-page | ||
| 73 | * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus | ||
| 74 | * | ||
| 75 | * For any >32-bit physical address platform, we can use the following | ||
| 76 | * two level page table layout where the pgdir is 8KB and the MS 13 bits | ||
| 77 | * are an index to the second level table. The combined pgdir/pmd first | ||
| 78 | * level has 2048 entries and the second level has 512 64-bit PTE entries. | ||
| 79 | * -Matt | ||
| 80 | */ | ||
| 81 | /* PMD_SHIFT determines the size of the area mapped by the PTE pages */ | ||
| 82 | #define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT) | ||
| 83 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
| 84 | #define PMD_MASK (~(PMD_SIZE-1)) | ||
| 85 | |||
| 86 | /* PGDIR_SHIFT determines what a top-level page table entry can map */ | ||
| 87 | #define PGDIR_SHIFT PMD_SHIFT | ||
| 88 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
| 89 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
| 90 | |||
| 91 | /* | ||
| 92 | * entries per page directory level: our page-table tree is two-level, so | ||
| 93 | * we don't really have any PMD directory. | ||
| 94 | */ | ||
| 95 | #define PTRS_PER_PTE (1 << PTE_SHIFT) | ||
| 96 | #define PTRS_PER_PMD 1 | ||
| 97 | #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) | ||
| 98 | |||
| 99 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) | ||
| 100 | #define FIRST_USER_ADDRESS 0 | ||
| 101 | |||
| 102 | #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) | ||
| 103 | #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) | ||
| 104 | |||
| 105 | #define pte_ERROR(e) \ | ||
| 106 | printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e)) | ||
| 107 | #define pmd_ERROR(e) \ | ||
| 108 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | ||
| 109 | #define pgd_ERROR(e) \ | ||
| 110 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | ||
| 111 | |||
| 112 | /* | ||
| 113 | * Just any arbitrary offset to the start of the vmalloc VM area: the | ||
| 114 | * current 64MB value just means that there will be a 64MB "hole" after the | ||
| 115 | * physical memory until the kernel virtual memory starts. That means that | ||
| 116 | * any out-of-bounds memory accesses will hopefully be caught. | ||
| 117 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | ||
| 118 | * area for the same reason. ;) | ||
| 119 | * | ||
| 120 | * We no longer map larger than phys RAM with the BATs so we don't have | ||
| 121 | * to worry about the VMALLOC_OFFSET causing problems. We do have to worry | ||
| 122 | * about clashes between our early calls to ioremap() that start growing down | ||
| 123 | * from ioremap_base being run into the VM area allocations (growing upwards | ||
| 124 | * from VMALLOC_START). For this reason we have ioremap_bot to check when | ||
| 125 | * we actually run into our mappings setup in the early boot with the VM | ||
| 126 | * system. This really does become a problem for machines with good amounts | ||
| 127 | * of RAM. -- Cort | ||
| 128 | */ | ||
| 129 | #define VMALLOC_OFFSET (0x1000000) /* 16M */ | ||
| 130 | #ifdef PPC_PIN_SIZE | ||
| 131 | #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) | ||
| 132 | #else | ||
| 133 | #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) | ||
| 134 | #endif | ||
| 135 | #define VMALLOC_END ioremap_bot | ||
| 136 | |||
| 137 | /* | ||
| 138 | * Bits in a linux-style PTE. These match the bits in the | ||
| 139 | * (hardware-defined) PowerPC PTE as closely as possible. | ||
| 140 | */ | ||
| 141 | |||
| 142 | #if defined(CONFIG_40x) | ||
| 143 | |||
| 144 | /* There are several potential gotchas here. The 40x hardware TLBLO | ||
| 145 | field looks like this: | ||
| 146 | |||
| 147 | 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 | ||
| 148 | RPN..................... 0 0 EX WR ZSEL....... W I M G | ||
| 149 | |||
| 150 | Where possible we make the Linux PTE bits match up with this | ||
| 151 | |||
| 152 | - bits 20 and 21 must be cleared, because we use 4k pages (40x can | ||
| 153 | support down to 1k pages), this is done in the TLBMiss exception | ||
| 154 | handler. | ||
| 155 | - We use only zones 0 (for kernel pages) and 1 (for user pages) | ||
| 156 | of the 16 available. Bit 24-26 of the TLB are cleared in the TLB | ||
| 157 | miss handler. Bit 27 is PAGE_USER, thus selecting the correct | ||
| 158 | zone. | ||
| 159 | - PRESENT *must* be in the bottom two bits because swap cache | ||
| 160 | entries use the top 30 bits. Because 40x doesn't support SMP | ||
| 161 | anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 | ||
| 162 | is cleared in the TLB miss handler before the TLB entry is loaded. | ||
| 163 | - All other bits of the PTE are loaded into TLBLO without | ||
| 164 | modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for | ||
| 165 | software PTE bits. We actually use use bits 21, 24, 25, and | ||
| 166 | 30 respectively for the software bits: ACCESSED, DIRTY, RW, and | ||
| 167 | PRESENT. | ||
| 168 | */ | ||
| 169 | |||
| 170 | /* Definitions for 40x embedded chips. */ | ||
| 171 | #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ | ||
| 172 | #define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */ | ||
| 173 | #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ | ||
| 174 | #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ | ||
| 175 | #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ | ||
| 176 | #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ | ||
| 177 | #define _PAGE_RW 0x040 /* software: Writes permitted */ | ||
| 178 | #define _PAGE_DIRTY 0x080 /* software: dirty page */ | ||
| 179 | #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ | ||
| 180 | #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ | ||
| 181 | #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ | ||
| 182 | |||
| 183 | #define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */ | ||
| 184 | #define _PMD_BAD 0x802 | ||
| 185 | #define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */ | ||
| 186 | #define _PMD_SIZE_4M 0x0c0 | ||
| 187 | #define _PMD_SIZE_16M 0x0e0 | ||
| 188 | #define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4)) | ||
| 189 | |||
| 190 | #elif defined(CONFIG_44x) | ||
| 191 | /* | ||
| 192 | * Definitions for PPC440 | ||
| 193 | * | ||
| 194 | * Because of the 3 word TLB entries to support 36-bit addressing, | ||
| 195 | * the attribute are difficult to map in such a fashion that they | ||
| 196 | * are easily loaded during exception processing. I decided to | ||
| 197 | * organize the entry so the ERPN is the only portion in the | ||
| 198 | * upper word of the PTE and the attribute bits below are packed | ||
| 199 | * in as sensibly as they can be in the area below a 4KB page size | ||
| 200 | * oriented RPN. This at least makes it easy to load the RPN and | ||
| 201 | * ERPN fields in the TLB. -Matt | ||
| 202 | * | ||
| 203 | * Note that these bits preclude future use of a page size | ||
| 204 | * less than 4KB. | ||
| 205 | * | ||
| 206 | * | ||
| 207 | * PPC 440 core has following TLB attribute fields; | ||
| 208 | * | ||
| 209 | * TLB1: | ||
| 210 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 | ||
| 211 | * RPN................................. - - - - - - ERPN....... | ||
| 212 | * | ||
| 213 | * TLB2: | ||
| 214 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 | ||
| 215 | * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR | ||
| 216 | * | ||
| 217 | * There are some constrains and options, to decide mapping software bits | ||
| 218 | * into TLB entry. | ||
| 219 | * | ||
| 220 | * - PRESENT *must* be in the bottom three bits because swap cache | ||
| 221 | * entries use the top 29 bits for TLB2. | ||
| 222 | * | ||
| 223 | * - FILE *must* be in the bottom three bits because swap cache | ||
| 224 | * entries use the top 29 bits for TLB2. | ||
| 225 | * | ||
| 226 | * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it | ||
| 227 | * doesn't support SMP. So we can use this as software bit, like | ||
| 228 | * DIRTY. | ||
| 229 | * | ||
| 230 | * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used | ||
| 231 | * for memory protection related functions (see PTE structure in | ||
| 232 | * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the | ||
| 233 | * above bits. Note that the bit values are CPU specific, not architecture | ||
| 234 | * specific. | ||
| 235 | * | ||
| 236 | * The kernel PTE entry holds an arch-dependent swp_entry structure under | ||
| 237 | * certain situations. In other words, in such situations some portion of | ||
| 238 | * the PTE bits are used as a swp_entry. In the PPC implementation, the | ||
| 239 | * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still | ||
| 240 | * hold protection values. That means the three protection bits are | ||
| 241 | * reserved for both PTE and SWAP entry at the most significant three | ||
| 242 | * LSBs. | ||
| 243 | * | ||
| 244 | * There are three protection bits available for SWAP entry: | ||
| 245 | * _PAGE_PRESENT | ||
| 246 | * _PAGE_FILE | ||
| 247 | * _PAGE_HASHPTE (if HW has) | ||
| 248 | * | ||
| 249 | * So those three bits have to be inside of 0-2nd LSB of PTE. | ||
| 250 | * | ||
| 251 | */ | ||
| 252 | |||
| 253 | #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ | ||
| 254 | #define _PAGE_RW 0x00000002 /* S: Write permission */ | ||
| 255 | #define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ | ||
| 256 | #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ | ||
| 257 | #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ | ||
| 258 | #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ | ||
| 259 | #define _PAGE_USER 0x00000040 /* S: User page */ | ||
| 260 | #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ | ||
| 261 | #define _PAGE_GUARDED 0x00000100 /* H: G bit */ | ||
| 262 | #define _PAGE_DIRTY 0x00000200 /* S: Page dirty */ | ||
| 263 | #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ | ||
| 264 | #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ | ||
| 265 | |||
| 266 | /* TODO: Add large page lowmem mapping support */ | ||
| 267 | #define _PMD_PRESENT 0 | ||
| 268 | #define _PMD_PRESENT_MASK (PAGE_MASK) | ||
| 269 | #define _PMD_BAD (~PAGE_MASK) | ||
| 270 | |||
| 271 | /* ERPN in a PTE never gets cleared, ignore it */ | ||
| 272 | #define _PTE_NONE_MASK 0xffffffff00000000ULL | ||
| 273 | |||
| 274 | #elif defined(CONFIG_8xx) | ||
| 275 | /* Definitions for 8xx embedded chips. */ | ||
| 276 | #define _PAGE_PRESENT 0x0001 /* Page is valid */ | ||
| 277 | #define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */ | ||
| 278 | #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ | ||
| 279 | #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ | ||
| 280 | |||
| 281 | /* These five software bits must be masked out when the entry is loaded | ||
| 282 | * into the TLB. | ||
| 283 | */ | ||
| 284 | #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ | ||
| 285 | #define _PAGE_GUARDED 0x0010 /* software: guarded access */ | ||
| 286 | #define _PAGE_DIRTY 0x0020 /* software: page changed */ | ||
| 287 | #define _PAGE_RW 0x0040 /* software: user write access allowed */ | ||
| 288 | #define _PAGE_ACCESSED 0x0080 /* software: page referenced */ | ||
| 289 | |||
| 290 | /* Setting any bits in the nibble with the follow two controls will | ||
| 291 | * require a TLB exception handler change. It is assumed unused bits | ||
| 292 | * are always zero. | ||
| 293 | */ | ||
| 294 | #define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ | ||
| 295 | #define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ | ||
| 296 | |||
| 297 | #define _PMD_PRESENT 0x0001 | ||
| 298 | #define _PMD_BAD 0x0ff0 | ||
| 299 | #define _PMD_PAGE_MASK 0x000c | ||
| 300 | #define _PMD_PAGE_8M 0x000c | ||
| 301 | |||
| 302 | #define _PTE_NONE_MASK _PAGE_ACCESSED | ||
| 303 | |||
| 304 | #else /* CONFIG_6xx */ | ||
| 305 | /* Definitions for 60x, 740/750, etc. */ | ||
| 306 | #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ | ||
| 307 | #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ | ||
| 308 | #define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */ | ||
| 309 | #define _PAGE_USER 0x004 /* usermode access allowed */ | ||
| 310 | #define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ | ||
| 311 | #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ | ||
| 312 | #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ | ||
| 313 | #define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ | ||
| 314 | #define _PAGE_DIRTY 0x080 /* C: page changed */ | ||
| 315 | #define _PAGE_ACCESSED 0x100 /* R: page referenced */ | ||
| 316 | #define _PAGE_EXEC 0x200 /* software: i-cache coherency required */ | ||
| 317 | #define _PAGE_RW 0x400 /* software: user write access allowed */ | ||
| 318 | |||
| 319 | #define _PTE_NONE_MASK _PAGE_HASHPTE | ||
| 320 | |||
| 321 | #define _PMD_PRESENT 0 | ||
| 322 | #define _PMD_PRESENT_MASK (PAGE_MASK) | ||
| 323 | #define _PMD_BAD (~PAGE_MASK) | ||
| 324 | #endif | ||
| 325 | |||
| 326 | /* | ||
| 327 | * Some bits are only used on some cpu families... | ||
| 328 | */ | ||
| 329 | #ifndef _PAGE_HASHPTE | ||
| 330 | #define _PAGE_HASHPTE 0 | ||
| 331 | #endif | ||
| 332 | #ifndef _PTE_NONE_MASK | ||
| 333 | #define _PTE_NONE_MASK 0 | ||
| 334 | #endif | ||
| 335 | #ifndef _PAGE_SHARED | ||
| 336 | #define _PAGE_SHARED 0 | ||
| 337 | #endif | ||
| 338 | #ifndef _PAGE_HWWRITE | ||
| 339 | #define _PAGE_HWWRITE 0 | ||
| 340 | #endif | ||
| 341 | #ifndef _PAGE_HWEXEC | ||
| 342 | #define _PAGE_HWEXEC 0 | ||
| 343 | #endif | ||
| 344 | #ifndef _PAGE_EXEC | ||
| 345 | #define _PAGE_EXEC 0 | ||
| 346 | #endif | ||
| 347 | #ifndef _PMD_PRESENT_MASK | ||
| 348 | #define _PMD_PRESENT_MASK _PMD_PRESENT | ||
| 349 | #endif | ||
| 350 | #ifndef _PMD_SIZE | ||
| 351 | #define _PMD_SIZE 0 | ||
| 352 | #define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE() | ||
| 353 | #endif | ||
| 354 | |||
| 355 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) | ||
| 356 | |||
| 357 | /* | ||
| 358 | * Note: the _PAGE_COHERENT bit automatically gets set in the hardware | ||
| 359 | * PTE if CONFIG_SMP is defined (hash_page does this); there is no need | ||
| 360 | * to have it in the Linux PTE, and in fact the bit could be reused for | ||
| 361 | * another purpose. -- paulus. | ||
| 362 | */ | ||
| 363 | |||
| 364 | #ifdef CONFIG_44x | ||
| 365 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED) | ||
| 366 | #else | ||
| 367 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) | ||
| 368 | #endif | ||
| 369 | #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) | ||
| 370 | #define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE) | ||
| 371 | |||
| 372 | #ifdef CONFIG_PPC_STD_MMU | ||
| 373 | /* On standard PPC MMU, no user access implies kernel read/write access, | ||
| 374 | * so to write-protect kernel memory we must turn on user access */ | ||
| 375 | #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER) | ||
| 376 | #else | ||
| 377 | #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED) | ||
| 378 | #endif | ||
| 379 | |||
| 380 | #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) | ||
| 381 | #define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC) | ||
| 382 | |||
| 383 | #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) | ||
| 384 | /* We want the debuggers to be able to set breakpoints anywhere, so | ||
| 385 | * don't write protect the kernel text */ | ||
| 386 | #define _PAGE_RAM_TEXT _PAGE_RAM | ||
| 387 | #else | ||
| 388 | #define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC) | ||
| 389 | #endif | ||
| 390 | |||
| 391 | #define PAGE_NONE __pgprot(_PAGE_BASE) | ||
| 392 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) | ||
| 393 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) | ||
| 394 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) | ||
| 395 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) | ||
| 396 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) | ||
| 397 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) | ||
| 398 | |||
| 399 | #define PAGE_KERNEL __pgprot(_PAGE_RAM) | ||
| 400 | #define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO) | ||
| 401 | |||
| 402 | /* | ||
| 403 | * The PowerPC can only do execute protection on a segment (256MB) basis, | ||
| 404 | * not on a page basis. So we consider execute permission the same as read. | ||
| 405 | * Also, write permissions imply read permissions. | ||
| 406 | * This is the closest we can get.. | ||
| 407 | */ | ||
| 408 | #define __P000 PAGE_NONE | ||
| 409 | #define __P001 PAGE_READONLY_X | ||
| 410 | #define __P010 PAGE_COPY | ||
| 411 | #define __P011 PAGE_COPY_X | ||
| 412 | #define __P100 PAGE_READONLY | ||
| 413 | #define __P101 PAGE_READONLY_X | ||
| 414 | #define __P110 PAGE_COPY | ||
| 415 | #define __P111 PAGE_COPY_X | ||
| 416 | |||
| 417 | #define __S000 PAGE_NONE | ||
| 418 | #define __S001 PAGE_READONLY_X | ||
| 419 | #define __S010 PAGE_SHARED | ||
| 420 | #define __S011 PAGE_SHARED_X | ||
| 421 | #define __S100 PAGE_READONLY | ||
| 422 | #define __S101 PAGE_READONLY_X | ||
| 423 | #define __S110 PAGE_SHARED | ||
| 424 | #define __S111 PAGE_SHARED_X | ||
| 425 | |||
| 426 | #ifndef __ASSEMBLY__ | ||
| 427 | /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a | ||
| 428 | * kernel without large page PMD support */ | ||
| 429 | extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); | ||
| 430 | |||
| 431 | /* | ||
| 432 | * Conversions between PTE values and page frame numbers. | ||
| 433 | */ | ||
| 434 | |||
| 435 | /* in some case we want to additionaly adjust where the pfn is in the pte to | ||
| 436 | * allow room for more flags */ | ||
| 437 | #define PFN_SHIFT_OFFSET (PAGE_SHIFT) | ||
| 438 | |||
| 439 | #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) | ||
| 440 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | ||
| 441 | |||
| 442 | #define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\ | ||
| 443 | pgprot_val(prot)) | ||
| 444 | #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) | ||
| 445 | |||
| 446 | /* | ||
| 447 | * ZERO_PAGE is a global shared page that is always zero: used | ||
| 448 | * for zero-mapped memory areas etc.. | ||
| 449 | */ | ||
| 450 | extern unsigned long empty_zero_page[1024]; | ||
| 451 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | ||
| 452 | |||
| 453 | #endif /* __ASSEMBLY__ */ | ||
| 454 | |||
| 455 | #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) | ||
| 456 | #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) | ||
| 457 | #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) | ||
| 458 | |||
| 459 | #define pmd_none(pmd) (!pmd_val(pmd)) | ||
| 460 | #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) | ||
| 461 | #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) | ||
| 462 | #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) | ||
| 463 | |||
| 464 | #ifndef __ASSEMBLY__ | ||
| 465 | /* | ||
| 466 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
| 467 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
| 468 | * into the pgd entry) | ||
| 469 | */ | ||
| 470 | static inline int pgd_none(pgd_t pgd) { return 0; } | ||
| 471 | static inline int pgd_bad(pgd_t pgd) { return 0; } | ||
| 472 | static inline int pgd_present(pgd_t pgd) { return 1; } | ||
| 473 | #define pgd_clear(xp) do { } while (0) | ||
| 474 | |||
| 475 | #define pgd_page_vaddr(pgd) \ | ||
| 476 | ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) | ||
| 477 | |||
| 478 | /* | ||
| 479 | * The following only work if pte_present() is true. | ||
| 480 | * Undefined behaviour if not.. | ||
| 481 | */ | ||
| 482 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } | ||
| 483 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } | ||
| 484 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } | ||
| 485 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } | ||
| 486 | static inline int pte_special(pte_t pte) { return 0; } | ||
| 487 | |||
| 488 | static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } | ||
| 489 | static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } | ||
| 490 | |||
| 491 | static inline pte_t pte_wrprotect(pte_t pte) { | ||
| 492 | pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } | ||
| 493 | static inline pte_t pte_mkclean(pte_t pte) { | ||
| 494 | pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } | ||
| 495 | static inline pte_t pte_mkold(pte_t pte) { | ||
| 496 | pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } | ||
| 497 | |||
| 498 | static inline pte_t pte_mkwrite(pte_t pte) { | ||
| 499 | pte_val(pte) |= _PAGE_RW; return pte; } | ||
| 500 | static inline pte_t pte_mkdirty(pte_t pte) { | ||
| 501 | pte_val(pte) |= _PAGE_DIRTY; return pte; } | ||
| 502 | static inline pte_t pte_mkyoung(pte_t pte) { | ||
| 503 | pte_val(pte) |= _PAGE_ACCESSED; return pte; } | ||
| 504 | static inline pte_t pte_mkspecial(pte_t pte) { | ||
| 505 | return pte; } | ||
| 506 | |||
| 507 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | ||
| 508 | { | ||
| 509 | pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); | ||
| 510 | return pte; | ||
| 511 | } | ||
| 512 | |||
| 513 | /* | ||
| 514 | * When flushing the tlb entry for a page, we also need to flush the hash | ||
| 515 | * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. | ||
| 516 | */ | ||
| 517 | extern int flush_hash_pages(unsigned context, unsigned long va, | ||
| 518 | unsigned long pmdval, int count); | ||
| 519 | |||
| 520 | /* Add an HPTE to the hash table */ | ||
| 521 | extern void add_hash_page(unsigned context, unsigned long va, | ||
| 522 | unsigned long pmdval); | ||
| 523 | |||
| 524 | /* | ||
| 525 | * Atomic PTE updates. | ||
| 526 | * | ||
| 527 | * pte_update clears and sets bit atomically, and returns | ||
| 528 | * the old pte value. In the 64-bit PTE case we lock around the | ||
| 529 | * low PTE word since we expect ALL flag bits to be there | ||
| 530 | */ | ||
| 531 | #ifndef CONFIG_PTE_64BIT | ||
| 532 | static inline unsigned long pte_update(pte_t *p, unsigned long clr, | ||
| 533 | unsigned long set) | ||
| 534 | { | ||
| 535 | unsigned long old, tmp; | ||
| 536 | |||
| 537 | __asm__ __volatile__("\ | ||
| 538 | 1: lwarx %0,0,%3\n\ | ||
| 539 | andc %1,%0,%4\n\ | ||
| 540 | or %1,%1,%5\n" | ||
| 541 | PPC405_ERR77(0,%3) | ||
| 542 | " stwcx. %1,0,%3\n\ | ||
| 543 | bne- 1b" | ||
| 544 | : "=&r" (old), "=&r" (tmp), "=m" (*p) | ||
| 545 | : "r" (p), "r" (clr), "r" (set), "m" (*p) | ||
| 546 | : "cc" ); | ||
| 547 | return old; | ||
| 548 | } | ||
| 549 | #else | ||
| 550 | static inline unsigned long long pte_update(pte_t *p, unsigned long clr, | ||
| 551 | unsigned long set) | ||
| 552 | { | ||
| 553 | unsigned long long old; | ||
| 554 | unsigned long tmp; | ||
| 555 | |||
| 556 | __asm__ __volatile__("\ | ||
| 557 | 1: lwarx %L0,0,%4\n\ | ||
| 558 | lwzx %0,0,%3\n\ | ||
| 559 | andc %1,%L0,%5\n\ | ||
| 560 | or %1,%1,%6\n" | ||
| 561 | PPC405_ERR77(0,%3) | ||
| 562 | " stwcx. %1,0,%4\n\ | ||
| 563 | bne- 1b" | ||
| 564 | : "=&r" (old), "=&r" (tmp), "=m" (*p) | ||
| 565 | : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) | ||
| 566 | : "cc" ); | ||
| 567 | return old; | ||
| 568 | } | ||
| 569 | #endif | ||
| 570 | |||
| 571 | /* | ||
| 572 | * set_pte stores a linux PTE into the linux page table. | ||
| 573 | * On machines which use an MMU hash table we avoid changing the | ||
| 574 | * _PAGE_HASHPTE bit. | ||
| 575 | */ | ||
| 576 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | ||
| 577 | pte_t *ptep, pte_t pte) | ||
| 578 | { | ||
| 579 | #if _PAGE_HASHPTE != 0 | ||
| 580 | pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE); | ||
| 581 | #else | ||
| 582 | *ptep = pte; | ||
| 583 | #endif | ||
| 584 | } | ||
| 585 | |||
| 586 | /* | ||
| 587 | * 2.6 calles this without flushing the TLB entry, this is wrong | ||
| 588 | * for our hash-based implementation, we fix that up here | ||
| 589 | */ | ||
| 590 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | ||
| 591 | static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) | ||
| 592 | { | ||
| 593 | unsigned long old; | ||
| 594 | old = pte_update(ptep, _PAGE_ACCESSED, 0); | ||
| 595 | #if _PAGE_HASHPTE != 0 | ||
| 596 | if (old & _PAGE_HASHPTE) { | ||
| 597 | unsigned long ptephys = __pa(ptep) & PAGE_MASK; | ||
| 598 | flush_hash_pages(context, addr, ptephys, 1); | ||
| 599 | } | ||
| 600 | #endif | ||
| 601 | return (old & _PAGE_ACCESSED) != 0; | ||
| 602 | } | ||
| 603 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | ||
| 604 | __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep) | ||
| 605 | |||
| 606 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | ||
| 607 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, | ||
| 608 | pte_t *ptep) | ||
| 609 | { | ||
| 610 | return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); | ||
| 611 | } | ||
| 612 | |||
| 613 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | ||
| 614 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | ||
| 615 | pte_t *ptep) | ||
| 616 | { | ||
| 617 | pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); | ||
| 618 | } | ||
| 619 | |||
| 620 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | ||
| 621 | static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) | ||
| 622 | { | ||
| 623 | unsigned long bits = pte_val(entry) & | ||
| 624 | (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW); | ||
| 625 | pte_update(ptep, 0, bits); | ||
| 626 | } | ||
| 627 | |||
| 628 | #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ | ||
| 629 | ({ \ | ||
| 630 | int __changed = !pte_same(*(__ptep), __entry); \ | ||
| 631 | if (__changed) { \ | ||
| 632 | __ptep_set_access_flags(__ptep, __entry, __dirty); \ | ||
| 633 | flush_tlb_page_nohash(__vma, __address); \ | ||
| 634 | } \ | ||
| 635 | __changed; \ | ||
| 636 | }) | ||
| 637 | |||
| 638 | /* | ||
| 639 | * Macro to mark a page protection value as "uncacheable". | ||
| 640 | */ | ||
| 641 | #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) | ||
| 642 | |||
| 643 | struct file; | ||
| 644 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | ||
| 645 | unsigned long size, pgprot_t vma_prot); | ||
| 646 | #define __HAVE_PHYS_MEM_ACCESS_PROT | ||
| 647 | |||
| 648 | #define __HAVE_ARCH_PTE_SAME | ||
| 649 | #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) | ||
| 650 | |||
| 651 | /* | ||
| 652 | * Note that on Book E processors, the pmd contains the kernel virtual | ||
| 653 | * (lowmem) address of the pte page. The physical address is less useful | ||
| 654 | * because everything runs with translation enabled (even the TLB miss | ||
| 655 | * handler). On everything else the pmd contains the physical address | ||
| 656 | * of the pte page. -- paulus | ||
| 657 | */ | ||
| 658 | #ifndef CONFIG_BOOKE | ||
| 659 | #define pmd_page_vaddr(pmd) \ | ||
| 660 | ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) | ||
| 661 | #define pmd_page(pmd) \ | ||
| 662 | (mem_map + (pmd_val(pmd) >> PAGE_SHIFT)) | ||
| 663 | #else | ||
| 664 | #define pmd_page_vaddr(pmd) \ | ||
| 665 | ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) | ||
| 666 | #define pmd_page(pmd) \ | ||
| 667 | (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT)) | ||
| 668 | #endif | ||
| 669 | |||
| 670 | /* to find an entry in a kernel page-table-directory */ | ||
| 671 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | ||
| 672 | |||
| 673 | /* to find an entry in a page-table-directory */ | ||
| 674 | #define pgd_index(address) ((address) >> PGDIR_SHIFT) | ||
| 675 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | ||
| 676 | |||
| 677 | /* Find an entry in the second-level page table.. */ | ||
| 678 | static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) | ||
| 679 | { | ||
| 680 | return (pmd_t *) dir; | ||
| 681 | } | ||
| 682 | |||
| 683 | /* Find an entry in the third-level page table.. */ | ||
| 684 | #define pte_index(address) \ | ||
| 685 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
| 686 | #define pte_offset_kernel(dir, addr) \ | ||
| 687 | ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr)) | ||
| 688 | #define pte_offset_map(dir, addr) \ | ||
| 689 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr)) | ||
| 690 | #define pte_offset_map_nested(dir, addr) \ | ||
| 691 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr)) | ||
| 692 | |||
| 693 | #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) | ||
| 694 | #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) | ||
| 695 | |||
| 696 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | ||
| 697 | |||
| 698 | extern void paging_init(void); | ||
| 699 | |||
| 700 | /* | ||
| 701 | * Encode and decode a swap entry. | ||
| 702 | * Note that the bits we use in a PTE for representing a swap entry | ||
| 703 | * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the | ||
| 704 | *_PAGE_HASHPTE bit (if used). -- paulus | ||
| 705 | */ | ||
| 706 | #define __swp_type(entry) ((entry).val & 0x1f) | ||
| 707 | #define __swp_offset(entry) ((entry).val >> 5) | ||
| 708 | #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) | ||
| 709 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) | ||
| 710 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) | ||
| 711 | |||
| 712 | /* Encode and decode a nonlinear file mapping entry */ | ||
| 713 | #define PTE_FILE_MAX_BITS 29 | ||
| 714 | #define pte_to_pgoff(pte) (pte_val(pte) >> 3) | ||
| 715 | #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) | ||
| 716 | |||
| 717 | /* Values for nocacheflag and cmode */ | ||
| 718 | /* These are not used by the APUS kernel_map, but prevents | ||
| 719 | compilation errors. */ | ||
| 720 | #define KERNELMAP_FULL_CACHING 0 | ||
| 721 | #define KERNELMAP_NOCACHE_SER 1 | ||
| 722 | #define KERNELMAP_NOCACHE_NONSER 2 | ||
| 723 | #define KERNELMAP_NO_COPYBACK 3 | ||
| 724 | |||
| 725 | /* | ||
| 726 | * Map some physical address range into the kernel address space. | ||
| 727 | */ | ||
| 728 | extern unsigned long kernel_map(unsigned long paddr, unsigned long size, | ||
| 729 | int nocacheflag, unsigned long *memavailp ); | ||
| 730 | |||
| 731 | /* | ||
| 732 | * Set cache mode of (kernel space) address range. | ||
| 733 | */ | ||
| 734 | extern void kernel_set_cachemode (unsigned long address, unsigned long size, | ||
| 735 | unsigned int cmode); | ||
| 736 | |||
| 737 | /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ | ||
| 738 | #define kern_addr_valid(addr) (1) | ||
| 739 | |||
| 740 | #ifdef CONFIG_PHYS_64BIT | ||
| 741 | extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, | ||
| 742 | unsigned long paddr, unsigned long size, pgprot_t prot); | ||
| 743 | |||
| 744 | static inline int io_remap_pfn_range(struct vm_area_struct *vma, | ||
| 745 | unsigned long vaddr, | ||
| 746 | unsigned long pfn, | ||
| 747 | unsigned long size, | ||
| 748 | pgprot_t prot) | ||
| 749 | { | ||
| 750 | phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); | ||
| 751 | return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot); | ||
| 752 | } | ||
| 753 | #else | ||
| 754 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ | ||
| 755 | remap_pfn_range(vma, vaddr, pfn, size, prot) | ||
| 756 | #endif | ||
| 757 | |||
| 758 | /* | ||
| 759 | * No page table caches to initialise | ||
| 760 | */ | ||
| 761 | #define pgtable_cache_init() do { } while (0) | ||
| 762 | |||
| 763 | extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep, | ||
| 764 | pmd_t **pmdp); | ||
| 765 | |||
| 766 | #include <asm-generic/pgtable.h> | ||
| 767 | |||
| 768 | #endif /* !__ASSEMBLY__ */ | ||
| 769 | |||
| 770 | #endif /* _PPC_PGTABLE_H */ | ||
| 771 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h deleted file mode 100644 index 6f6760b30dd8..000000000000 --- a/include/asm-ppc/pnp.h +++ /dev/null | |||
| @@ -1,645 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | /* 11/02/95 */ | ||
| 3 | /*----------------------------------------------------------------------------*/ | ||
| 4 | /* Plug and Play header definitions */ | ||
| 5 | /*----------------------------------------------------------------------------*/ | ||
| 6 | |||
| 7 | /* Structure map for PnP on PowerPC Reference Platform */ | ||
| 8 | /* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ | ||
| 9 | /* (or later versions) is available on Compuserve in the PLUGPLAY area. */ | ||
| 10 | /* This code has extensions to that specification, namely new short and */ | ||
| 11 | /* long tag types for platform dependent information */ | ||
| 12 | |||
| 13 | /* Warning: LE notation used throughout this file */ | ||
| 14 | |||
| 15 | /* For enum's: if given in hex then they are bit significant, i.e. */ | ||
| 16 | /* only one bit is on for each enum */ | ||
| 17 | |||
| 18 | #ifndef _PNP_ | ||
| 19 | #define _PNP_ | ||
| 20 | |||
| 21 | #ifndef __ASSEMBLY__ | ||
| 22 | #define MAX_MEM_REGISTERS 9 | ||
| 23 | #define MAX_IO_PORTS 20 | ||
| 24 | #define MAX_IRQS 7 | ||
| 25 | /*#define MAX_DMA_CHANNELS 7*/ | ||
| 26 | |||
| 27 | /* Interrupt controllers */ | ||
| 28 | |||
| 29 | #define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ | ||
| 30 | #define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ | ||
| 31 | #define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ | ||
| 32 | #define PNPinterrupt3 "PNP0003" /* APIC */ | ||
| 33 | #define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ | ||
| 34 | |||
| 35 | /* Timers */ | ||
| 36 | |||
| 37 | #define PNPtimer0 "PNP0100" /* AT Timer */ | ||
| 38 | #define PNPtimer1 "PNP0101" /* EISA Timer */ | ||
| 39 | #define PNPtimer2 "PNP0102" /* MCA Timer */ | ||
| 40 | |||
| 41 | /* DMA controllers */ | ||
| 42 | |||
| 43 | #define PNPdma0 "PNP0200" /* AT DMA Controller */ | ||
| 44 | #define PNPdma1 "PNP0201" /* EISA DMA Controller */ | ||
| 45 | #define PNPdma2 "PNP0202" /* MCA DMA Controller */ | ||
| 46 | |||
| 47 | /* start of August 15, 1994 additions */ | ||
| 48 | /* CMOS */ | ||
| 49 | #define PNPCMOS "IBM0009" /* CMOS */ | ||
| 50 | |||
| 51 | /* L2 Cache */ | ||
| 52 | #define PNPL2 "IBM0007" /* L2 Cache */ | ||
| 53 | |||
| 54 | /* NVRAM */ | ||
| 55 | #define PNPNVRAM "IBM0008" /* NVRAM */ | ||
| 56 | |||
| 57 | /* Power Management */ | ||
| 58 | #define PNPPM "IBM0005" /* Power Management */ | ||
| 59 | /* end of August 15, 1994 additions */ | ||
| 60 | |||
| 61 | /* Keyboards */ | ||
| 62 | |||
| 63 | #define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ | ||
| 64 | #define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ | ||
| 65 | #define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ | ||
| 66 | #define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ | ||
| 67 | #define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ | ||
| 68 | #define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ | ||
| 69 | #define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ | ||
| 70 | #define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ | ||
| 71 | |||
| 72 | /* Parallel port controllers */ | ||
| 73 | |||
| 74 | #define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ | ||
| 75 | #define PNPparallel1 "PNP0401" /* ECP Parallel Port */ | ||
| 76 | #define PNPepp "IBM001C" /* EPP Parallel Port */ | ||
| 77 | |||
| 78 | /* Serial port controllers */ | ||
| 79 | |||
| 80 | #define PNPserial0 "PNP0500" /* Standard PC Serial port */ | ||
| 81 | #define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ | ||
| 82 | |||
| 83 | /* Disk controllers */ | ||
| 84 | |||
| 85 | #define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ | ||
| 86 | #define PNPdisk1 "PNP0601" /* Plus Hardcard II */ | ||
| 87 | #define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ | ||
| 88 | |||
| 89 | /* Diskette controllers */ | ||
| 90 | |||
| 91 | #define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ | ||
| 92 | |||
| 93 | /* Display controllers */ | ||
| 94 | |||
| 95 | #define PNPdisplay0 "PNP0900" /* VGA Compatible */ | ||
| 96 | #define PNPdisplay1 "PNP0901" /* Video Seven VGA */ | ||
| 97 | #define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ | ||
| 98 | #define PNPdisplay3 "PNP0903" /* Trident VGA */ | ||
| 99 | #define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ | ||
| 100 | #define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ | ||
| 101 | #define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ | ||
| 102 | #define PNPdisplay7 "PNP0907" /* Western Digital VGA */ | ||
| 103 | #define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ | ||
| 104 | #define PNPdisplay9 "PNP0909" /* S3 */ | ||
| 105 | #define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ | ||
| 106 | #define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ | ||
| 107 | #define PNPdisplayC "PNP090C" /* XGA Compatible */ | ||
| 108 | #define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ | ||
| 109 | #define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ | ||
| 110 | #define PNPdisplayF "PNP090F" /* Oak Technology VGA */ | ||
| 111 | |||
| 112 | /* Peripheral busses */ | ||
| 113 | |||
| 114 | #define PNPbuses0 "PNP0A00" /* ISA Bus */ | ||
| 115 | #define PNPbuses1 "PNP0A01" /* EISA Bus */ | ||
| 116 | #define PNPbuses2 "PNP0A02" /* MCA Bus */ | ||
| 117 | #define PNPbuses3 "PNP0A03" /* PCI Bus */ | ||
| 118 | #define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ | ||
| 119 | |||
| 120 | /* RTC, BIOS, planar devices */ | ||
| 121 | |||
| 122 | #define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ | ||
| 123 | #define PNPrtc0 "PNP0B00" /* AT RTC */ | ||
| 124 | #define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ | ||
| 125 | #define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ | ||
| 126 | #define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ | ||
| 127 | #define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ | ||
| 128 | |||
| 129 | /* PCMCIA controller */ | ||
| 130 | |||
| 131 | #define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ | ||
| 132 | |||
| 133 | /* Mice */ | ||
| 134 | |||
| 135 | #define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ | ||
| 136 | #define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ | ||
| 137 | #define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ | ||
| 138 | #define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ | ||
| 139 | #define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ | ||
| 140 | #define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ | ||
| 141 | #define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ | ||
| 142 | #define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ | ||
| 143 | #define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ | ||
| 144 | #define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ | ||
| 145 | #define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ | ||
| 146 | #define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ | ||
| 147 | |||
| 148 | /* Modems */ | ||
| 149 | |||
| 150 | #define PNPmodem0 "PNP9000" /* Specific IDs TBD */ | ||
| 151 | |||
| 152 | /* Network controllers */ | ||
| 153 | |||
| 154 | #define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ | ||
| 155 | #define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ | ||
| 156 | #define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ | ||
| 157 | #define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ | ||
| 158 | #define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ | ||
| 159 | #define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ | ||
| 160 | #define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ | ||
| 161 | #define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ | ||
| 162 | |||
| 163 | /* SCSI controllers */ | ||
| 164 | |||
| 165 | #define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ | ||
| 166 | #define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ | ||
| 167 | #define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ | ||
| 168 | #define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ | ||
| 169 | #define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ | ||
| 170 | #define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ | ||
| 171 | #define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ | ||
| 172 | |||
| 173 | /* Sound/Video, Multimedia */ | ||
| 174 | |||
| 175 | #define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ | ||
| 176 | #define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ | ||
| 177 | #define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ | ||
| 178 | #define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ | ||
| 179 | #define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ | ||
| 180 | #define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ | ||
| 181 | #define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ | ||
| 182 | #define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ | ||
| 183 | |||
| 184 | /* Operator Panel */ | ||
| 185 | #define PNPopctl "IBM000B" /* Operator's panel */ | ||
| 186 | |||
| 187 | /* Service Processor */ | ||
| 188 | #define PNPsp "IBM0011" /* IBM Service Processor */ | ||
| 189 | #define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ | ||
| 190 | #define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ | ||
| 191 | |||
| 192 | /* Memory Controller */ | ||
| 193 | #define PNPmemctl "IBM000A" /* Memory controller */ | ||
| 194 | |||
| 195 | /* Graphics Assist */ | ||
| 196 | #define PNPg_assist "IBM0014" /* Graphics Assist */ | ||
| 197 | |||
| 198 | /* Miscellaneous Device Controllers */ | ||
| 199 | #define PNPtablet "IBM0019" /* IBM Tablet Controller */ | ||
| 200 | |||
| 201 | /* PNP Packet Handles */ | ||
| 202 | |||
| 203 | #define S1_Packet 0x0A /* Version resource */ | ||
| 204 | #define S2_Packet 0x15 /* Logical DEVID (without flags) */ | ||
| 205 | #define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ | ||
| 206 | #define S3_Packet 0x1C /* Compatible device ID */ | ||
| 207 | #define S4_Packet 0x22 /* IRQ resource (without flags) */ | ||
| 208 | #define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ | ||
| 209 | #define S5_Packet 0x2A /* DMA resource */ | ||
| 210 | #define S6_Packet 0x30 /* Depend funct start (w/o priority) */ | ||
| 211 | #define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ | ||
| 212 | #define S7_Packet 0x38 /* Depend funct end */ | ||
| 213 | #define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ | ||
| 214 | #define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ | ||
| 215 | #define S14_Packet 0x71 /* Vendor defined */ | ||
| 216 | #define S15_Packet 0x78 /* End of resource (w/o checksum) */ | ||
| 217 | #define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ | ||
| 218 | #define L1_Packet 0x81 /* Memory range */ | ||
| 219 | #define L1_Shadow 0x20 /* Memory is shadowable */ | ||
| 220 | #define L1_32bit_mem 0x18 /* 32-bit memory only */ | ||
| 221 | #define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ | ||
| 222 | #define L1_Decode_Hi 0x04 /* decode supports high address */ | ||
| 223 | #define L1_Cache 0x02 /* read cacheable, write-through */ | ||
| 224 | #define L1_Writeable 0x01 /* Memory is writeable */ | ||
| 225 | #define L2_Packet 0x82 /* ANSI ID string */ | ||
| 226 | #define L3_Packet 0x83 /* Unicode ID string */ | ||
| 227 | #define L4_Packet 0x84 /* Vendor defined */ | ||
| 228 | #define L5_Packet 0x85 /* Large I/O */ | ||
| 229 | #define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ | ||
| 230 | #define END_TAG 0x78 /* End of resource */ | ||
| 231 | #define DF_START_TAG 0x30 /* Dependent function start */ | ||
| 232 | #define DF_START_TAG_priority 0x31 /* Dependent function start */ | ||
| 233 | #define DF_END_TAG 0x38 /* Dependent function end */ | ||
| 234 | #define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ | ||
| 235 | |||
| 236 | /* Device Base Type Codes */ | ||
| 237 | |||
| 238 | typedef enum _PnP_BASE_TYPE { | ||
| 239 | Reserved = 0, | ||
| 240 | MassStorageDevice = 1, | ||
| 241 | NetworkInterfaceController = 2, | ||
| 242 | DisplayController = 3, | ||
| 243 | MultimediaController = 4, | ||
| 244 | MemoryController = 5, | ||
| 245 | BridgeController = 6, | ||
| 246 | CommunicationsDevice = 7, | ||
| 247 | SystemPeripheral = 8, | ||
| 248 | InputDevice = 9, | ||
| 249 | ServiceProcessor = 0x0A, /* 11/2/95 */ | ||
| 250 | } PnP_BASE_TYPE; | ||
| 251 | |||
| 252 | /* Device Sub Type Codes */ | ||
| 253 | |||
| 254 | typedef enum _PnP_SUB_TYPE { | ||
| 255 | SCSIController = 0, | ||
| 256 | IDEController = 1, | ||
| 257 | FloppyController = 2, | ||
| 258 | IPIController = 3, | ||
| 259 | OtherMassStorageController = 0x80, | ||
| 260 | |||
| 261 | EthernetController = 0, | ||
| 262 | TokenRingController = 1, | ||
| 263 | FDDIController = 2, | ||
| 264 | OtherNetworkController = 0x80, | ||
| 265 | |||
| 266 | VGAController= 0, | ||
| 267 | SVGAController= 1, | ||
| 268 | XGAController= 2, | ||
| 269 | OtherDisplayController = 0x80, | ||
| 270 | |||
| 271 | VideoController = 0, | ||
| 272 | AudioController = 1, | ||
| 273 | OtherMultimediaController = 0x80, | ||
| 274 | |||
| 275 | RAM = 0, | ||
| 276 | FLASH = 1, | ||
| 277 | OtherMemoryDevice = 0x80, | ||
| 278 | |||
| 279 | HostProcessorBridge = 0, | ||
| 280 | ISABridge = 1, | ||
| 281 | EISABridge = 2, | ||
| 282 | MicroChannelBridge = 3, | ||
| 283 | PCIBridge = 4, | ||
| 284 | PCMCIABridge = 5, | ||
| 285 | VMEBridge = 6, | ||
| 286 | OtherBridgeDevice = 0x80, | ||
| 287 | |||
| 288 | RS232Device = 0, | ||
| 289 | ATCompatibleParallelPort = 1, | ||
| 290 | OtherCommunicationsDevice = 0x80, | ||
| 291 | |||
| 292 | ProgrammableInterruptController = 0, | ||
| 293 | DMAController = 1, | ||
| 294 | SystemTimer = 2, | ||
| 295 | RealTimeClock = 3, | ||
| 296 | L2Cache = 4, | ||
| 297 | NVRAM = 5, | ||
| 298 | PowerManagement = 6, | ||
| 299 | CMOS = 7, | ||
| 300 | OperatorPanel = 8, | ||
| 301 | ServiceProcessorClass1 = 9, | ||
| 302 | ServiceProcessorClass2 = 0xA, | ||
| 303 | ServiceProcessorClass3 = 0xB, | ||
| 304 | GraphicAssist = 0xC, | ||
| 305 | SystemPlanar = 0xF, /* 10/5/95 */ | ||
| 306 | OtherSystemPeripheral = 0x80, | ||
| 307 | |||
| 308 | KeyboardController = 0, | ||
| 309 | Digitizer = 1, | ||
| 310 | MouseController = 2, | ||
| 311 | TabletController = 3, /* 10/27/95 */ | ||
| 312 | OtherInputController = 0x80, | ||
| 313 | |||
| 314 | GeneralMemoryController = 0, | ||
| 315 | } PnP_SUB_TYPE; | ||
| 316 | |||
| 317 | /* Device Interface Type Codes */ | ||
| 318 | |||
| 319 | typedef enum _PnP_INTERFACE { | ||
| 320 | General = 0, | ||
| 321 | GeneralSCSI = 0, | ||
| 322 | GeneralIDE = 0, | ||
| 323 | ATACompatible = 1, | ||
| 324 | |||
| 325 | GeneralFloppy = 0, | ||
| 326 | Compatible765 = 1, | ||
| 327 | NS398_Floppy = 2, /* NS Super I/O wired to use index | ||
| 328 | register at port 398 and data | ||
| 329 | register at port 399 */ | ||
| 330 | NS26E_Floppy = 3, /* Ports 26E and 26F */ | ||
| 331 | NS15C_Floppy = 4, /* Ports 15C and 15D */ | ||
| 332 | NS2E_Floppy = 5, /* Ports 2E and 2F */ | ||
| 333 | CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ | ||
| 334 | |||
| 335 | GeneralIPI = 0, | ||
| 336 | |||
| 337 | GeneralEther = 0, | ||
| 338 | GeneralToken = 0, | ||
| 339 | GeneralFDDI = 0, | ||
| 340 | |||
| 341 | GeneralVGA = 0, | ||
| 342 | GeneralSVGA = 0, | ||
| 343 | GeneralXGA = 0, | ||
| 344 | |||
| 345 | GeneralVideo = 0, | ||
| 346 | GeneralAudio = 0, | ||
| 347 | CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ | ||
| 348 | |||
| 349 | GeneralRAM = 0, | ||
| 350 | GeneralFLASH = 0, | ||
| 351 | PCIMemoryController = 0, /* PCI Config Method */ | ||
| 352 | RS6KMemoryController = 1, /* RS6K Config Method */ | ||
| 353 | |||
| 354 | GeneralHostBridge = 0, | ||
| 355 | GeneralISABridge = 0, | ||
| 356 | GeneralEISABridge = 0, | ||
| 357 | GeneralMCABridge = 0, | ||
| 358 | GeneralPCIBridge = 0, | ||
| 359 | PCIBridgeDirect = 0, | ||
| 360 | PCIBridgeIndirect = 1, | ||
| 361 | PCIBridgeRS6K = 2, | ||
| 362 | GeneralPCMCIABridge = 0, | ||
| 363 | GeneralVMEBridge = 0, | ||
| 364 | |||
| 365 | GeneralRS232 = 0, | ||
| 366 | COMx = 1, | ||
| 367 | Compatible16450 = 2, | ||
| 368 | Compatible16550 = 3, | ||
| 369 | NS398SerPort = 4, /* NS Super I/O wired to use index | ||
| 370 | register at port 398 and data | ||
| 371 | register at port 399 */ | ||
| 372 | NS26ESerPort = 5, /* Ports 26E and 26F */ | ||
| 373 | NS15CSerPort = 6, /* Ports 15C and 15D */ | ||
| 374 | NS2ESerPort = 7, /* Ports 2E and 2F */ | ||
| 375 | |||
| 376 | GeneralParPort = 0, | ||
| 377 | LPTx = 1, | ||
| 378 | NS398ParPort = 2, /* NS Super I/O wired to use index | ||
| 379 | register at port 398 and data | ||
| 380 | register at port 399 */ | ||
| 381 | NS26EParPort = 3, /* Ports 26E and 26F */ | ||
| 382 | NS15CParPort = 4, /* Ports 15C and 15D */ | ||
| 383 | NS2EParPort = 5, /* Ports 2E and 2F */ | ||
| 384 | |||
| 385 | GeneralPIC = 0, | ||
| 386 | ISA_PIC = 1, | ||
| 387 | EISA_PIC = 2, | ||
| 388 | MPIC = 3, | ||
| 389 | RS6K_PIC = 4, | ||
| 390 | |||
| 391 | GeneralDMA = 0, | ||
| 392 | ISA_DMA = 1, | ||
| 393 | EISA_DMA = 2, | ||
| 394 | |||
| 395 | GeneralTimer = 0, | ||
| 396 | ISA_Timer = 1, | ||
| 397 | EISA_Timer = 2, | ||
| 398 | GeneralRTC = 0, | ||
| 399 | ISA_RTC = 1, | ||
| 400 | |||
| 401 | StoreThruOnly = 1, | ||
| 402 | StoreInEnabled = 2, | ||
| 403 | RS6KL2Cache = 3, | ||
| 404 | |||
| 405 | IndirectNVRAM = 0, /* Indirectly addressed */ | ||
| 406 | DirectNVRAM = 1, /* Memory Mapped */ | ||
| 407 | IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ | ||
| 408 | |||
| 409 | GeneralPowerManagement = 0, | ||
| 410 | EPOWPowerManagement = 1, | ||
| 411 | PowerControl = 2, // d1378 | ||
| 412 | |||
| 413 | GeneralCMOS = 0, | ||
| 414 | |||
| 415 | GeneralOPPanel = 0, | ||
| 416 | HarddiskLight = 1, | ||
| 417 | CDROMLight = 2, | ||
| 418 | PowerLight = 3, | ||
| 419 | KeyLock = 4, | ||
| 420 | ANDisplay = 5, /* AlphaNumeric Display */ | ||
| 421 | SystemStatusLED = 6, /* 3 digit 7 segment LED */ | ||
| 422 | CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ | ||
| 423 | |||
| 424 | GeneralServiceProcessor = 0, | ||
| 425 | |||
| 426 | TransferData = 1, | ||
| 427 | IGMC32 = 2, | ||
| 428 | IGMC64 = 3, | ||
| 429 | |||
| 430 | GeneralSystemPlanar = 0, /* 10/5/95 */ | ||
| 431 | |||
| 432 | } PnP_INTERFACE; | ||
| 433 | |||
| 434 | /* PnP resources */ | ||
| 435 | |||
| 436 | /* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ | ||
| 437 | |||
| 438 | typedef struct _SERIAL_ID { | ||
| 439 | unsigned char VendorID0; /* Bit(7)=0 */ | ||
| 440 | /* Bits(6:2)=1st character in */ | ||
| 441 | /* compressed ASCII */ | ||
| 442 | /* Bits(1:0)=2nd character in */ | ||
| 443 | /* compressed ASCII bits(4:3) */ | ||
| 444 | unsigned char VendorID1; /* Bits(7:5)=2nd character in */ | ||
| 445 | /* compressed ASCII bits(2:0) */ | ||
| 446 | /* Bits(4:0)=3rd character in */ | ||
| 447 | /* compressed ASCII */ | ||
| 448 | unsigned char VendorID2; /* Product number - vendor assigned */ | ||
| 449 | unsigned char VendorID3; /* Product number - vendor assigned */ | ||
| 450 | |||
| 451 | /* Serial number is to provide uniqueness if more than one board of same */ | ||
| 452 | /* type is in system. Must be "FFFFFFFF" if feature not supported. */ | ||
| 453 | |||
| 454 | unsigned char Serial0; /* Unique serial number bits (7:0) */ | ||
| 455 | unsigned char Serial1; /* Unique serial number bits (15:8) */ | ||
| 456 | unsigned char Serial2; /* Unique serial number bits (23:16) */ | ||
| 457 | unsigned char Serial3; /* Unique serial number bits (31:24) */ | ||
| 458 | unsigned char Checksum; | ||
| 459 | } SERIAL_ID; | ||
| 460 | |||
| 461 | typedef enum _PnPItemName { | ||
| 462 | Unused = 0, | ||
| 463 | PnPVersion = 1, | ||
| 464 | LogicalDevice = 2, | ||
| 465 | CompatibleDevice = 3, | ||
| 466 | IRQFormat = 4, | ||
| 467 | DMAFormat = 5, | ||
| 468 | StartDepFunc = 6, | ||
| 469 | EndDepFunc = 7, | ||
| 470 | IOPort = 8, | ||
| 471 | FixedIOPort = 9, | ||
| 472 | Res1 = 10, | ||
| 473 | Res2 = 11, | ||
| 474 | Res3 = 12, | ||
| 475 | SmallVendorItem = 14, | ||
| 476 | EndTag = 15, | ||
| 477 | MemoryRange = 1, | ||
| 478 | ANSIIdentifier = 2, | ||
| 479 | UnicodeIdentifier = 3, | ||
| 480 | LargeVendorItem = 4, | ||
| 481 | MemoryRange32 = 5, | ||
| 482 | MemoryRangeFixed32 = 6, | ||
| 483 | } PnPItemName; | ||
| 484 | |||
| 485 | /* Define a bunch of access functions for the bits in the tag field */ | ||
| 486 | |||
| 487 | /* Tag type - 0 = small; 1 = large */ | ||
| 488 | #define tag_type(t) (((t) & 0x80)>>7) | ||
| 489 | #define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) | ||
| 490 | |||
| 491 | /* Small item name is 4 bits - one of PnPItemName enum above */ | ||
| 492 | #define tag_small_item_name(t) (((t) & 0x78)>>3) | ||
| 493 | #define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) | ||
| 494 | |||
| 495 | /* Small item count is 3 bits - count of further bytes in packet */ | ||
| 496 | #define tag_small_count(t) ((t) & 0x07) | ||
| 497 | #define set_tag_count(t,v) (t = (t & 0x78) | (v)) | ||
| 498 | |||
| 499 | /* Large item name is 7 bits - one of PnPItemName enum above */ | ||
| 500 | #define tag_large_item_name(t) ((t) & 0x7f) | ||
| 501 | #define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) | ||
| 502 | |||
| 503 | /* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ | ||
| 504 | |||
| 505 | typedef union _PnP_TAG_PACKET { | ||
| 506 | struct _S1_Pack{ /* VERSION PACKET */ | ||
| 507 | unsigned char Tag; /* small tag = 0x0a */ | ||
| 508 | unsigned char Version[2]; /* PnP version, Vendor version */ | ||
| 509 | } S1_Pack; | ||
| 510 | |||
| 511 | struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ | ||
| 512 | unsigned char Tag; /* small tag = 0x15 or 0x16 */ | ||
| 513 | unsigned char DevId[4]; /* Logical device id */ | ||
| 514 | unsigned char Flags[2]; /* bit(0) boot device; */ | ||
| 515 | /* bit(7:1) cmd in range x31-x37 */ | ||
| 516 | /* bit(7:0) cmd in range x28-x3f (opt)*/ | ||
| 517 | } S2_Pack; | ||
| 518 | |||
| 519 | struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ | ||
| 520 | unsigned char Tag; /* small tag = 0x1c */ | ||
| 521 | unsigned char CompatId[4]; /* Compatible device id */ | ||
| 522 | } S3_Pack; | ||
| 523 | |||
| 524 | struct _S4_Pack{ /* IRQ PACKET */ | ||
| 525 | unsigned char Tag; /* small tag = 0x22 or 0x23 */ | ||
| 526 | unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ | ||
| 527 | /* bit(0) is IRQ8 ... */ | ||
| 528 | unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ | ||
| 529 | /* bit(0) - high true edge sensitive */ | ||
| 530 | /* bit(1) - low true edge sensitive */ | ||
| 531 | /* bit(2) - high true level sensitive*/ | ||
| 532 | /* bit(3) - low true level sensitive */ | ||
| 533 | /* bit(7:4) - must be 0 */ | ||
| 534 | } S4_Pack; | ||
| 535 | |||
| 536 | struct _S5_Pack{ /* DMA PACKET */ | ||
| 537 | unsigned char Tag; /* small tag = 0x2a */ | ||
| 538 | unsigned char DMAMask; /* bit(0) is channel 0 ... */ | ||
| 539 | unsigned char DMAInfo; | ||
| 540 | } S5_Pack; | ||
| 541 | |||
| 542 | struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ | ||
| 543 | unsigned char Tag; /* small tag = 0x30 or 0x31 */ | ||
| 544 | unsigned char Priority; /* Optional; if missing then x01; else*/ | ||
| 545 | /* x00 = best possible */ | ||
| 546 | /* x01 = acceptible */ | ||
| 547 | /* x02 = sub-optimal but functional */ | ||
| 548 | } S6_Pack; | ||
| 549 | |||
| 550 | struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ | ||
| 551 | unsigned char Tag; /* small tag = 0x38 */ | ||
| 552 | } S7_Pack; | ||
| 553 | |||
| 554 | struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ | ||
| 555 | unsigned char Tag; /* small tag x47 */ | ||
| 556 | unsigned char IOInfo; /* x0 = decode only bits(9:0); */ | ||
| 557 | #define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ | ||
| 558 | unsigned char RangeMin[2]; /* Min base address */ | ||
| 559 | unsigned char RangeMax[2]; /* Max base address */ | ||
| 560 | unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ | ||
| 561 | unsigned char IONum; /* number of contiguous I/O ports */ | ||
| 562 | } S8_Pack; | ||
| 563 | |||
| 564 | struct _S9_Pack{ /* FIXED I/O PORT PACKET */ | ||
| 565 | unsigned char Tag; /* small tag = 0x4b */ | ||
| 566 | unsigned char Range[2]; /* base address 10 bits */ | ||
| 567 | unsigned char IONum; /* number of contiguous I/O ports */ | ||
| 568 | } S9_Pack; | ||
| 569 | |||
| 570 | struct _S14_Pack{ /* VENDOR DEFINED PACKET */ | ||
| 571 | unsigned char Tag; /* small tag = 0x7m m = 1-7 */ | ||
| 572 | union _S14_Data{ | ||
| 573 | unsigned char Data[7]; /* Vendor defined */ | ||
| 574 | struct _S14_PPCPack{ /* Pr*p s14 pack */ | ||
| 575 | unsigned char Type; /* 00=non-IBM */ | ||
| 576 | unsigned char PPCData[6]; /* Vendor defined */ | ||
| 577 | } S14_PPCPack; | ||
| 578 | } S14_Data; | ||
| 579 | } S14_Pack; | ||
| 580 | |||
| 581 | struct _S15_Pack{ /* END PACKET */ | ||
| 582 | unsigned char Tag; /* small tag = 0x78 or 0x79 */ | ||
| 583 | unsigned char Check; /* optional - checksum */ | ||
| 584 | } S15_Pack; | ||
| 585 | |||
| 586 | struct _L1_Pack{ /* MEMORY RANGE PACKET */ | ||
| 587 | unsigned char Tag; /* large tag = 0x81 */ | ||
| 588 | unsigned char Count0; /* x09 */ | ||
| 589 | unsigned char Count1; /* x00 */ | ||
| 590 | unsigned char Data[9]; /* a variable array of bytes, */ | ||
| 591 | /* count in tag */ | ||
| 592 | } L1_Pack; | ||
| 593 | |||
| 594 | struct _L2_Pack{ /* ANSI ID STRING PACKET */ | ||
| 595 | unsigned char Tag; /* large tag = 0x82 */ | ||
| 596 | unsigned char Count0; /* Length of string */ | ||
| 597 | unsigned char Count1; | ||
| 598 | unsigned char Identifier[1]; /* a variable array of bytes, */ | ||
| 599 | /* count in tag */ | ||
| 600 | } L2_Pack; | ||
| 601 | |||
| 602 | struct _L3_Pack{ /* UNICODE ID STRING PACKET */ | ||
| 603 | unsigned char Tag; /* large tag = 0x83 */ | ||
| 604 | unsigned char Count0; /* Length + 2 of string */ | ||
| 605 | unsigned char Count1; | ||
| 606 | unsigned char Country0; /* TBD */ | ||
| 607 | unsigned char Country1; /* TBD */ | ||
| 608 | unsigned char Identifier[1]; /* a variable array of bytes, */ | ||
| 609 | /* count in tag */ | ||
| 610 | } L3_Pack; | ||
| 611 | |||
| 612 | struct _L4_Pack{ /* VENDOR DEFINED PACKET */ | ||
| 613 | unsigned char Tag; /* large tag = 0x84 */ | ||
| 614 | unsigned char Count0; | ||
| 615 | unsigned char Count1; | ||
| 616 | union _L4_Data{ | ||
| 617 | unsigned char Data[1]; /* a variable array of bytes, */ | ||
| 618 | /* count in tag */ | ||
| 619 | struct _L4_PPCPack{ /* Pr*p L4 packet */ | ||
| 620 | unsigned char Type; /* 00=non-IBM */ | ||
| 621 | unsigned char PPCData[1]; /* a variable array of bytes, */ | ||
| 622 | /* count in tag */ | ||
| 623 | } L4_PPCPack; | ||
| 624 | } L4_Data; | ||
| 625 | } L4_Pack; | ||
| 626 | |||
| 627 | struct _L5_Pack{ | ||
| 628 | unsigned char Tag; /* large tag = 0x85 */ | ||
| 629 | unsigned char Count0; /* Count = 17 */ | ||
| 630 | unsigned char Count1; | ||
| 631 | unsigned char Data[17]; | ||
| 632 | } L5_Pack; | ||
| 633 | |||
| 634 | struct _L6_Pack{ | ||
| 635 | unsigned char Tag; /* large tag = 0x86 */ | ||
| 636 | unsigned char Count0; /* Count = 9 */ | ||
| 637 | unsigned char Count1; | ||
| 638 | unsigned char Data[9]; | ||
| 639 | } L6_Pack; | ||
| 640 | |||
| 641 | } PnP_TAG_PACKET; | ||
| 642 | |||
| 643 | #endif /* __ASSEMBLY__ */ | ||
| 644 | #endif /* ndef _PNP_ */ | ||
| 645 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h deleted file mode 100644 index 935d1e05366b..000000000000 --- a/include/asm-ppc/ppc4xx_dma.h +++ /dev/null | |||
| @@ -1,579 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/ppc4xx_dma.h | ||
| 3 | * | ||
| 4 | * IBM PPC4xx DMA engine library | ||
| 5 | * | ||
| 6 | * Copyright 2000-2004 MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * Cleaned up a bit more, Matt Porter <mporter@kernel.crashing.org> | ||
| 9 | * | ||
| 10 | * Original code by Armin Kuster <akuster@mvista.com> | ||
| 11 | * and Pete Popov <ppopov@mvista.com> | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify it | ||
| 14 | * under the terms of the GNU General Public License as published by the | ||
| 15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 16 | * option) any later version. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License along | ||
| 19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 20 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifdef __KERNEL__ | ||
| 24 | #ifndef __ASMPPC_PPC4xx_DMA_H | ||
| 25 | #define __ASMPPC_PPC4xx_DMA_H | ||
| 26 | |||
| 27 | #include <linux/types.h> | ||
| 28 | #include <asm/mmu.h> | ||
| 29 | #include <asm/ibm4xx.h> | ||
| 30 | |||
| 31 | #undef DEBUG_4xxDMA | ||
| 32 | |||
| 33 | #define MAX_PPC4xx_DMA_CHANNELS 4 | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Function return status codes | ||
| 37 | * These values are used to indicate whether or not the function | ||
| 38 | * call was successful, or a bad/invalid parameter was passed. | ||
| 39 | */ | ||
| 40 | #define DMA_STATUS_GOOD 0 | ||
| 41 | #define DMA_STATUS_BAD_CHANNEL 1 | ||
| 42 | #define DMA_STATUS_BAD_HANDLE 2 | ||
| 43 | #define DMA_STATUS_BAD_MODE 3 | ||
| 44 | #define DMA_STATUS_NULL_POINTER 4 | ||
| 45 | #define DMA_STATUS_OUT_OF_MEMORY 5 | ||
| 46 | #define DMA_STATUS_SGL_LIST_EMPTY 6 | ||
| 47 | #define DMA_STATUS_GENERAL_ERROR 7 | ||
| 48 | #define DMA_STATUS_CHANNEL_NOTFREE 8 | ||
| 49 | |||
| 50 | #define DMA_CHANNEL_BUSY 0x80000000 | ||
| 51 | |||
| 52 | /* | ||
| 53 | * These indicate status as returned from the DMA Status Register. | ||
| 54 | */ | ||
| 55 | #define DMA_STATUS_NO_ERROR 0 | ||
| 56 | #define DMA_STATUS_CS 1 /* Count Status */ | ||
| 57 | #define DMA_STATUS_TS 2 /* Transfer Status */ | ||
| 58 | #define DMA_STATUS_DMA_ERROR 3 /* DMA Error Occurred */ | ||
| 59 | #define DMA_STATUS_DMA_BUSY 4 /* The channel is busy */ | ||
| 60 | |||
| 61 | |||
| 62 | /* | ||
| 63 | * DMA Channel Control Registers | ||
| 64 | */ | ||
| 65 | |||
| 66 | #ifdef CONFIG_44x | ||
| 67 | #define PPC4xx_DMA_64BIT | ||
| 68 | #define DMA_CR_OFFSET 1 | ||
| 69 | #else | ||
| 70 | #define DMA_CR_OFFSET 0 | ||
| 71 | #endif | ||
| 72 | |||
| 73 | #define DMA_CE_ENABLE (1<<31) /* DMA Channel Enable */ | ||
| 74 | #define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31) | ||
| 75 | #define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31) | ||
| 76 | |||
| 77 | #define DMA_CIE_ENABLE (1<<30) /* DMA Channel Interrupt Enable */ | ||
| 78 | #define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30) | ||
| 79 | #define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30) | ||
| 80 | |||
| 81 | #define DMA_TD (1<<29) | ||
| 82 | #define SET_DMA_TD(x) (((x)&0x1)<<29) | ||
| 83 | #define GET_DMA_TD(x) (((x)&DMA_TD)>>29) | ||
| 84 | |||
| 85 | #define DMA_PL (1<<28) /* Peripheral Location */ | ||
| 86 | #define SET_DMA_PL(x) (((x)&0x1)<<28) | ||
| 87 | #define GET_DMA_PL(x) (((x)&DMA_PL)>>28) | ||
| 88 | |||
| 89 | #define EXTERNAL_PERIPHERAL 0 | ||
| 90 | #define INTERNAL_PERIPHERAL 1 | ||
| 91 | |||
| 92 | #define SET_DMA_PW(x) (((x)&0x3)<<(26-DMA_CR_OFFSET)) /* Peripheral Width */ | ||
| 93 | #define DMA_PW_MASK SET_DMA_PW(3) | ||
| 94 | #define PW_8 0 | ||
| 95 | #define PW_16 1 | ||
| 96 | #define PW_32 2 | ||
| 97 | #define PW_64 3 | ||
| 98 | /* FIXME: Add PW_128 support for 440GP DMA block */ | ||
| 99 | #define GET_DMA_PW(x) (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET)) | ||
| 100 | |||
| 101 | #define DMA_DAI (1<<(25-DMA_CR_OFFSET)) /* Destination Address Increment */ | ||
| 102 | #define SET_DMA_DAI(x) (((x)&0x1)<<(25-DMA_CR_OFFSET)) | ||
| 103 | |||
| 104 | #define DMA_SAI (1<<(24-DMA_CR_OFFSET)) /* Source Address Increment */ | ||
| 105 | #define SET_DMA_SAI(x) (((x)&0x1)<<(24-DMA_CR_OFFSET)) | ||
| 106 | |||
| 107 | #define DMA_BEN (1<<(23-DMA_CR_OFFSET)) /* Buffer Enable */ | ||
| 108 | #define SET_DMA_BEN(x) (((x)&0x1)<<(23-DMA_CR_OFFSET)) | ||
| 109 | |||
| 110 | #define SET_DMA_TM(x) (((x)&0x3)<<(21-DMA_CR_OFFSET)) /* Transfer Mode */ | ||
| 111 | #define DMA_TM_MASK SET_DMA_TM(3) | ||
| 112 | #define TM_PERIPHERAL 0 /* Peripheral */ | ||
| 113 | #define TM_RESERVED 1 /* Reserved */ | ||
| 114 | #define TM_S_MM 2 /* Memory to Memory */ | ||
| 115 | #define TM_D_MM 3 /* Device Paced Memory to Memory */ | ||
| 116 | #define GET_DMA_TM(x) (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET)) | ||
| 117 | |||
| 118 | #define SET_DMA_PSC(x) (((x)&0x3)<<(19-DMA_CR_OFFSET)) /* Peripheral Setup Cycles */ | ||
| 119 | #define DMA_PSC_MASK SET_DMA_PSC(3) | ||
| 120 | #define GET_DMA_PSC(x) (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET)) | ||
| 121 | |||
| 122 | #define SET_DMA_PWC(x) (((x)&0x3F)<<(13-DMA_CR_OFFSET)) /* Peripheral Wait Cycles */ | ||
| 123 | #define DMA_PWC_MASK SET_DMA_PWC(0x3F) | ||
| 124 | #define GET_DMA_PWC(x) (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET)) | ||
| 125 | |||
| 126 | #define SET_DMA_PHC(x) (((x)&0x7)<<(10-DMA_CR_OFFSET)) /* Peripheral Hold Cycles */ | ||
| 127 | #define DMA_PHC_MASK SET_DMA_PHC(0x7) | ||
| 128 | #define GET_DMA_PHC(x) (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET)) | ||
| 129 | |||
| 130 | #define DMA_ETD_OUTPUT (1<<(9-DMA_CR_OFFSET)) /* EOT pin is a TC output */ | ||
| 131 | #define SET_DMA_ETD(x) (((x)&0x1)<<(9-DMA_CR_OFFSET)) | ||
| 132 | |||
| 133 | #define DMA_TCE_ENABLE (1<<(8-DMA_CR_OFFSET)) | ||
| 134 | #define SET_DMA_TCE(x) (((x)&0x1)<<(8-DMA_CR_OFFSET)) | ||
| 135 | |||
| 136 | #define DMA_DEC (1<<(2)) /* Address Decrement */ | ||
| 137 | #define SET_DMA_DEC(x) (((x)&0x1)<<2) | ||
| 138 | #define GET_DMA_DEC(x) (((x)&DMA_DEC)>>2) | ||
| 139 | |||
| 140 | |||
| 141 | /* | ||
| 142 | * Transfer Modes | ||
| 143 | * These modes are defined in a way that makes it possible to | ||
| 144 | * simply "or" in the value in the control register. | ||
| 145 | */ | ||
| 146 | |||
| 147 | #define DMA_MODE_MM (SET_DMA_TM(TM_S_MM)) /* memory to memory */ | ||
| 148 | |||
| 149 | /* Device-paced memory to memory, */ | ||
| 150 | /* device is at source address */ | ||
| 151 | #define DMA_MODE_MM_DEVATSRC (DMA_TD | SET_DMA_TM(TM_D_MM)) | ||
| 152 | |||
| 153 | /* Device-paced memory to memory, */ | ||
| 154 | /* device is at destination address */ | ||
| 155 | #define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM)) | ||
| 156 | |||
| 157 | /* 405gp/440gp */ | ||
| 158 | #define SET_DMA_PREFETCH(x) (((x)&0x3)<<(4-DMA_CR_OFFSET)) /* Memory Read Prefetch */ | ||
| 159 | #define DMA_PREFETCH_MASK SET_DMA_PREFETCH(3) | ||
| 160 | #define PREFETCH_1 0 /* Prefetch 1 Double Word */ | ||
| 161 | #define PREFETCH_2 1 | ||
| 162 | #define PREFETCH_4 2 | ||
| 163 | #define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET)) | ||
| 164 | |||
| 165 | #define DMA_PCE (1<<(3-DMA_CR_OFFSET)) /* Parity Check Enable */ | ||
| 166 | #define SET_DMA_PCE(x) (((x)&0x1)<<(3-DMA_CR_OFFSET)) | ||
| 167 | #define GET_DMA_PCE(x) (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET)) | ||
| 168 | |||
| 169 | /* stb3x */ | ||
| 170 | |||
| 171 | #define DMA_ECE_ENABLE (1<<5) | ||
| 172 | #define SET_DMA_ECE(x) (((x)&0x1)<<5) | ||
| 173 | #define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5) | ||
| 174 | |||
| 175 | #define DMA_TCD_DISABLE (1<<4) | ||
| 176 | #define SET_DMA_TCD(x) (((x)&0x1)<<4) | ||
| 177 | #define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4) | ||
| 178 | |||
| 179 | typedef uint32_t sgl_handle_t; | ||
| 180 | |||
| 181 | #ifdef CONFIG_PPC4xx_EDMA | ||
| 182 | |||
| 183 | #define SGL_LIST_SIZE 4096 | ||
| 184 | #define DMA_PPC4xx_SIZE SGL_LIST_SIZE | ||
| 185 | |||
| 186 | #define SET_DMA_PRIORITY(x) (((x)&0x3)<<(6-DMA_CR_OFFSET)) /* DMA Channel Priority */ | ||
| 187 | #define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3) | ||
| 188 | #define PRIORITY_LOW 0 | ||
| 189 | #define PRIORITY_MID_LOW 1 | ||
| 190 | #define PRIORITY_MID_HIGH 2 | ||
| 191 | #define PRIORITY_HIGH 3 | ||
| 192 | #define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET)) | ||
| 193 | |||
| 194 | /* | ||
| 195 | * DMA Polarity Configuration Register | ||
| 196 | */ | ||
| 197 | #define DMAReq_ActiveLow(chan) (1<<(31-(chan*3))) | ||
| 198 | #define DMAAck_ActiveLow(chan) (1<<(30-(chan*3))) | ||
| 199 | #define EOT_ActiveLow(chan) (1<<(29-(chan*3))) /* End of Transfer */ | ||
| 200 | |||
| 201 | /* | ||
| 202 | * DMA Sleep Mode Register | ||
| 203 | */ | ||
| 204 | #define SLEEP_MODE_ENABLE (1<<21) | ||
| 205 | |||
| 206 | /* | ||
| 207 | * DMA Status Register | ||
| 208 | */ | ||
| 209 | #define DMA_CS0 (1<<31) /* Terminal Count has been reached */ | ||
| 210 | #define DMA_CS1 (1<<30) | ||
| 211 | #define DMA_CS2 (1<<29) | ||
| 212 | #define DMA_CS3 (1<<28) | ||
| 213 | |||
| 214 | #define DMA_TS0 (1<<27) /* End of Transfer has been requested */ | ||
| 215 | #define DMA_TS1 (1<<26) | ||
| 216 | #define DMA_TS2 (1<<25) | ||
| 217 | #define DMA_TS3 (1<<24) | ||
| 218 | |||
| 219 | #define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ | ||
| 220 | #define DMA_CH1_ERR (1<<22) | ||
| 221 | #define DMA_CH2_ERR (1<<21) | ||
| 222 | #define DMA_CH3_ERR (1<<20) | ||
| 223 | |||
| 224 | #define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */ | ||
| 225 | #define DMA_IN_DMA_REQ1 (1<<18) | ||
| 226 | #define DMA_IN_DMA_REQ2 (1<<17) | ||
| 227 | #define DMA_IN_DMA_REQ3 (1<<16) | ||
| 228 | |||
| 229 | #define DMA_EXT_DMA_REQ0 (1<<15) /* External DMA Request is pending */ | ||
| 230 | #define DMA_EXT_DMA_REQ1 (1<<14) | ||
| 231 | #define DMA_EXT_DMA_REQ2 (1<<13) | ||
| 232 | #define DMA_EXT_DMA_REQ3 (1<<12) | ||
| 233 | |||
| 234 | #define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */ | ||
| 235 | #define DMA_CH1_BUSY (1<<10) | ||
| 236 | #define DMA_CH2_BUSY (1<<9) | ||
| 237 | #define DMA_CH3_BUSY (1<<8) | ||
| 238 | |||
| 239 | #define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */ | ||
| 240 | #define DMA_SG1 (1<<6) | ||
| 241 | #define DMA_SG2 (1<<5) | ||
| 242 | #define DMA_SG3 (1<<4) | ||
| 243 | |||
| 244 | /* DMA Channel Count Register */ | ||
| 245 | #define DMA_CTC_BTEN (1<<23) /* Burst Enable/Disable bit */ | ||
| 246 | #define DMA_CTC_BSIZ_MSK (3<<21) /* Mask of the Burst size bits */ | ||
| 247 | #define DMA_CTC_BSIZ_2 (0) | ||
| 248 | #define DMA_CTC_BSIZ_4 (1<<21) | ||
| 249 | #define DMA_CTC_BSIZ_8 (2<<21) | ||
| 250 | #define DMA_CTC_BSIZ_16 (3<<21) | ||
| 251 | |||
| 252 | /* | ||
| 253 | * DMA SG Command Register | ||
| 254 | */ | ||
| 255 | #define SSG_ENABLE(chan) (1<<(31-chan)) /* Start Scatter Gather */ | ||
| 256 | #define SSG_MASK_ENABLE(chan) (1<<(15-chan)) /* Enable writing to SSG0 bit */ | ||
| 257 | |||
| 258 | /* | ||
| 259 | * DMA Scatter/Gather Descriptor Bit fields | ||
| 260 | */ | ||
| 261 | #define SG_LINK (1<<31) /* Link */ | ||
| 262 | #define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */ | ||
| 263 | #define SG_ETI_ENABLE (1<<28) /* Enable End of Transfer Interrupt */ | ||
| 264 | #define SG_ERI_ENABLE (1<<27) /* Enable Error Interrupt */ | ||
| 265 | #define SG_COUNT_MASK 0xFFFF /* Count Field */ | ||
| 266 | |||
| 267 | #define SET_DMA_CONTROL \ | ||
| 268 | (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ | ||
| 269 | SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */\ | ||
| 270 | SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ | ||
| 271 | SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ | ||
| 272 | SET_DMA_PL(p_init->pl) | /* peripheral location */ \ | ||
| 273 | SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ | ||
| 274 | SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ | ||
| 275 | SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ | ||
| 276 | SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ | ||
| 277 | SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ | ||
| 278 | SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ | ||
| 279 | SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ | ||
| 280 | SET_DMA_PREFETCH(p_init->pf) /* read prefetch */) | ||
| 281 | |||
| 282 | #define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan)) | ||
| 283 | |||
| 284 | #elif defined(CONFIG_STB03xxx) /* stb03xxx */ | ||
| 285 | |||
| 286 | #define DMA_PPC4xx_SIZE 4096 | ||
| 287 | |||
| 288 | /* | ||
| 289 | * DMA Status Register | ||
| 290 | */ | ||
| 291 | |||
| 292 | #define SET_DMA_PRIORITY(x) (((x)&0x00800001)) /* DMA Channel Priority */ | ||
| 293 | #define DMA_PRIORITY_MASK 0x00800001 | ||
| 294 | #define PRIORITY_LOW 0x00000000 | ||
| 295 | #define PRIORITY_MID_LOW 0x00000001 | ||
| 296 | #define PRIORITY_MID_HIGH 0x00800000 | ||
| 297 | #define PRIORITY_HIGH 0x00800001 | ||
| 298 | #define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001)) | ||
| 299 | |||
| 300 | #define DMA_CS0 (1<<31) /* Terminal Count has been reached */ | ||
| 301 | #define DMA_CS1 (1<<30) | ||
| 302 | #define DMA_CS2 (1<<29) | ||
| 303 | #define DMA_CS3 (1<<28) | ||
| 304 | |||
| 305 | #define DMA_TS0 (1<<27) /* End of Transfer has been requested */ | ||
| 306 | #define DMA_TS1 (1<<26) | ||
| 307 | #define DMA_TS2 (1<<25) | ||
| 308 | #define DMA_TS3 (1<<24) | ||
| 309 | |||
| 310 | #define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ | ||
| 311 | #define DMA_CH1_ERR (1<<22) | ||
| 312 | #define DMA_CH2_ERR (1<<21) | ||
| 313 | #define DMA_CH3_ERR (1<<20) | ||
| 314 | |||
| 315 | #define DMA_CT0 (1<<19) /* Chained transfere */ | ||
| 316 | |||
| 317 | #define DMA_IN_DMA_REQ0 (1<<18) /* Internal DMA Request is pending */ | ||
| 318 | #define DMA_IN_DMA_REQ1 (1<<17) | ||
| 319 | #define DMA_IN_DMA_REQ2 (1<<16) | ||
| 320 | #define DMA_IN_DMA_REQ3 (1<<15) | ||
| 321 | |||
| 322 | #define DMA_EXT_DMA_REQ0 (1<<14) /* External DMA Request is pending */ | ||
| 323 | #define DMA_EXT_DMA_REQ1 (1<<13) | ||
| 324 | #define DMA_EXT_DMA_REQ2 (1<<12) | ||
| 325 | #define DMA_EXT_DMA_REQ3 (1<<11) | ||
| 326 | |||
| 327 | #define DMA_CH0_BUSY (1<<10) /* DMA Channel 0 Busy */ | ||
| 328 | #define DMA_CH1_BUSY (1<<9) | ||
| 329 | #define DMA_CH2_BUSY (1<<8) | ||
| 330 | #define DMA_CH3_BUSY (1<<7) | ||
| 331 | |||
| 332 | #define DMA_CT1 (1<<6) /* Chained transfere */ | ||
| 333 | #define DMA_CT2 (1<<5) | ||
| 334 | #define DMA_CT3 (1<<4) | ||
| 335 | |||
| 336 | #define DMA_CH_ENABLE (1<<7) | ||
| 337 | #define SET_DMA_CH(x) (((x)&0x1)<<7) | ||
| 338 | #define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7) | ||
| 339 | |||
| 340 | /* STBx25xxx dma unique */ | ||
| 341 | /* enable device port on a dma channel | ||
| 342 | * example ext 0 on dma 1 | ||
| 343 | */ | ||
| 344 | |||
| 345 | #define SSP0_RECV 15 | ||
| 346 | #define SSP0_XMIT 14 | ||
| 347 | #define EXT_DMA_0 12 | ||
| 348 | #define SC1_XMIT 11 | ||
| 349 | #define SC1_RECV 10 | ||
| 350 | #define EXT_DMA_2 9 | ||
| 351 | #define EXT_DMA_3 8 | ||
| 352 | #define SERIAL2_XMIT 7 | ||
| 353 | #define SERIAL2_RECV 6 | ||
| 354 | #define SC0_XMIT 5 | ||
| 355 | #define SC0_RECV 4 | ||
| 356 | #define SERIAL1_XMIT 3 | ||
| 357 | #define SERIAL1_RECV 2 | ||
| 358 | #define SERIAL0_XMIT 1 | ||
| 359 | #define SERIAL0_RECV 0 | ||
| 360 | |||
| 361 | #define DMA_CHAN_0 1 | ||
| 362 | #define DMA_CHAN_1 2 | ||
| 363 | #define DMA_CHAN_2 3 | ||
| 364 | #define DMA_CHAN_3 4 | ||
| 365 | |||
| 366 | /* end STBx25xx */ | ||
| 367 | |||
| 368 | /* | ||
| 369 | * Bit 30 must be one for Redwoods, otherwise transfers may receive errors. | ||
| 370 | */ | ||
| 371 | #define DMA_CR_MB0 0x2 | ||
| 372 | |||
| 373 | #define SET_DMA_CONTROL \ | ||
| 374 | (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ | ||
| 375 | SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ | ||
| 376 | SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ | ||
| 377 | SET_DMA_PL(p_init->pl) | /* peripheral location */ \ | ||
| 378 | SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ | ||
| 379 | SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ | ||
| 380 | SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ | ||
| 381 | SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ | ||
| 382 | SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ | ||
| 383 | SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ | ||
| 384 | SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ | ||
| 385 | SET_DMA_TCD(p_init->tcd_disable) | /* TC chain mode disable */ \ | ||
| 386 | SET_DMA_ECE(p_init->ece_enable) | /* ECE chanin mode enable */ \ | ||
| 387 | SET_DMA_CH(p_init->ch_enable) | /* Chain enable */ \ | ||
| 388 | DMA_CR_MB0 /* must be one */) | ||
| 389 | |||
| 390 | #define GET_DMA_POLARITY(chan) chan | ||
| 391 | |||
| 392 | #endif | ||
| 393 | |||
| 394 | typedef struct { | ||
| 395 | unsigned short in_use; /* set when channel is being used, clr when | ||
| 396 | * available. | ||
| 397 | */ | ||
| 398 | /* | ||
| 399 | * Valid polarity settings: | ||
| 400 | * DMAReq_ActiveLow(n) | ||
| 401 | * DMAAck_ActiveLow(n) | ||
| 402 | * EOT_ActiveLow(n) | ||
| 403 | * | ||
| 404 | * n is 0 to max dma chans | ||
| 405 | */ | ||
| 406 | unsigned int polarity; | ||
| 407 | |||
| 408 | char buffer_enable; /* Boolean: buffer enable */ | ||
| 409 | char tce_enable; /* Boolean: terminal count enable */ | ||
| 410 | char etd_output; /* Boolean: eot pin is a tc output */ | ||
| 411 | char pce; /* Boolean: parity check enable */ | ||
| 412 | |||
| 413 | /* | ||
| 414 | * Peripheral location: | ||
| 415 | * INTERNAL_PERIPHERAL (UART0 on the 405GP) | ||
| 416 | * EXTERNAL_PERIPHERAL | ||
| 417 | */ | ||
| 418 | char pl; /* internal/external peripheral */ | ||
| 419 | |||
| 420 | /* | ||
| 421 | * Valid pwidth settings: | ||
| 422 | * PW_8 | ||
| 423 | * PW_16 | ||
| 424 | * PW_32 | ||
| 425 | * PW_64 | ||
| 426 | */ | ||
| 427 | unsigned int pwidth; | ||
| 428 | |||
| 429 | char dai; /* Boolean: dst address increment */ | ||
| 430 | char sai; /* Boolean: src address increment */ | ||
| 431 | |||
| 432 | /* | ||
| 433 | * Valid psc settings: 0-3 | ||
| 434 | */ | ||
| 435 | unsigned int psc; /* Peripheral Setup Cycles */ | ||
| 436 | |||
| 437 | /* | ||
| 438 | * Valid pwc settings: | ||
| 439 | * 0-63 | ||
| 440 | */ | ||
| 441 | unsigned int pwc; /* Peripheral Wait Cycles */ | ||
| 442 | |||
| 443 | /* | ||
| 444 | * Valid phc settings: | ||
| 445 | * 0-7 | ||
| 446 | */ | ||
| 447 | unsigned int phc; /* Peripheral Hold Cycles */ | ||
| 448 | |||
| 449 | /* | ||
| 450 | * Valid cp (channel priority) settings: | ||
| 451 | * PRIORITY_LOW | ||
| 452 | * PRIORITY_MID_LOW | ||
| 453 | * PRIORITY_MID_HIGH | ||
| 454 | * PRIORITY_HIGH | ||
| 455 | */ | ||
| 456 | unsigned int cp; /* channel priority */ | ||
| 457 | |||
| 458 | /* | ||
| 459 | * Valid pf (memory read prefetch) settings: | ||
| 460 | * | ||
| 461 | * PREFETCH_1 | ||
| 462 | * PREFETCH_2 | ||
| 463 | * PREFETCH_4 | ||
| 464 | */ | ||
| 465 | unsigned int pf; /* memory read prefetch */ | ||
| 466 | |||
| 467 | /* | ||
| 468 | * Boolean: channel interrupt enable | ||
| 469 | * NOTE: for sgl transfers, only the last descriptor will be setup to | ||
| 470 | * interrupt. | ||
| 471 | */ | ||
| 472 | char int_enable; | ||
| 473 | |||
| 474 | char shift; /* easy access to byte_count shift, based on */ | ||
| 475 | /* the width of the channel */ | ||
| 476 | |||
| 477 | uint32_t control; /* channel control word */ | ||
| 478 | |||
| 479 | /* These variabled are used ONLY in single dma transfers */ | ||
| 480 | unsigned int mode; /* transfer mode */ | ||
| 481 | phys_addr_t addr; | ||
| 482 | char ce; /* channel enable */ | ||
| 483 | #ifdef CONFIG_STB03xxx | ||
| 484 | char ch_enable; | ||
| 485 | char tcd_disable; | ||
| 486 | char ece_enable; | ||
| 487 | char td; /* transfer direction */ | ||
| 488 | #endif | ||
| 489 | |||
| 490 | char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */ | ||
| 491 | } ppc_dma_ch_t; | ||
| 492 | |||
| 493 | /* | ||
| 494 | * PPC44x DMA implementations have a slightly different | ||
| 495 | * descriptor layout. Probably moved about due to the | ||
| 496 | * change to 64-bit addresses and link pointer. I don't | ||
| 497 | * know why they didn't just leave control_count after | ||
| 498 | * the dst_addr. | ||
| 499 | */ | ||
| 500 | #ifdef PPC4xx_DMA_64BIT | ||
| 501 | typedef struct { | ||
| 502 | uint32_t control; | ||
| 503 | uint32_t control_count; | ||
| 504 | phys_addr_t src_addr; | ||
| 505 | phys_addr_t dst_addr; | ||
| 506 | phys_addr_t next; | ||
| 507 | } ppc_sgl_t; | ||
| 508 | #else | ||
| 509 | typedef struct { | ||
| 510 | uint32_t control; | ||
| 511 | phys_addr_t src_addr; | ||
| 512 | phys_addr_t dst_addr; | ||
| 513 | uint32_t control_count; | ||
| 514 | uint32_t next; | ||
| 515 | } ppc_sgl_t; | ||
| 516 | #endif | ||
| 517 | |||
| 518 | typedef struct { | ||
| 519 | unsigned int dmanr; | ||
| 520 | uint32_t control; /* channel ctrl word; loaded from each descrptr */ | ||
| 521 | uint32_t sgl_control; /* LK, TCI, ETI, and ERI bits in sgl descriptor */ | ||
| 522 | dma_addr_t dma_addr; /* dma (physical) address of this list */ | ||
| 523 | ppc_sgl_t *phead; | ||
| 524 | dma_addr_t phead_dma; | ||
| 525 | ppc_sgl_t *ptail; | ||
| 526 | dma_addr_t ptail_dma; | ||
| 527 | } sgl_list_info_t; | ||
| 528 | |||
| 529 | typedef struct { | ||
| 530 | phys_addr_t *src_addr; | ||
| 531 | phys_addr_t *dst_addr; | ||
| 532 | phys_addr_t dma_src_addr; | ||
| 533 | phys_addr_t dma_dst_addr; | ||
| 534 | } pci_alloc_desc_t; | ||
| 535 | |||
| 536 | extern ppc_dma_ch_t dma_channels[]; | ||
| 537 | |||
| 538 | /* | ||
| 539 | * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c | ||
| 540 | */ | ||
| 541 | extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *); | ||
| 542 | extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *); | ||
| 543 | extern int ppc4xx_set_channel_priority(unsigned int, unsigned int); | ||
| 544 | extern unsigned int ppc4xx_get_peripheral_width(unsigned int); | ||
| 545 | extern void ppc4xx_set_sg_addr(int, phys_addr_t); | ||
| 546 | extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int); | ||
| 547 | extern void ppc4xx_enable_dma_sgl(sgl_handle_t); | ||
| 548 | extern void ppc4xx_disable_dma_sgl(sgl_handle_t); | ||
| 549 | extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *); | ||
| 550 | extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *); | ||
| 551 | extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int); | ||
| 552 | extern void ppc4xx_free_dma_handle(sgl_handle_t); | ||
| 553 | extern int ppc4xx_get_dma_status(void); | ||
| 554 | extern int ppc4xx_enable_burst(unsigned int); | ||
| 555 | extern int ppc4xx_disable_burst(unsigned int); | ||
| 556 | extern int ppc4xx_set_burst_size(unsigned int, unsigned int); | ||
| 557 | extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr); | ||
| 558 | extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr); | ||
| 559 | extern void ppc4xx_enable_dma(unsigned int dmanr); | ||
| 560 | extern void ppc4xx_disable_dma(unsigned int dmanr); | ||
| 561 | extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count); | ||
| 562 | extern int ppc4xx_get_dma_residue(unsigned int dmanr); | ||
| 563 | extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr, | ||
| 564 | phys_addr_t dst_dma_addr); | ||
| 565 | extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr); | ||
| 566 | extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr); | ||
| 567 | extern int ppc4xx_clr_dma_status(unsigned int dmanr); | ||
| 568 | extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); | ||
| 569 | extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); | ||
| 570 | extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode); | ||
| 571 | |||
| 572 | /* These are in kernel/dma.c: */ | ||
| 573 | |||
| 574 | /* reserve a DMA channel */ | ||
| 575 | extern int request_dma(unsigned int dmanr, const char *device_id); | ||
| 576 | /* release it again */ | ||
| 577 | extern void free_dma(unsigned int dmanr); | ||
| 578 | #endif | ||
| 579 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h deleted file mode 100644 index e44261206f8b..000000000000 --- a/include/asm-ppc/ppc4xx_pic.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/ppc4xx_pic.h | ||
| 3 | * | ||
| 4 | * Interrupt controller driver for PowerPC 4xx-based processors. | ||
| 5 | * | ||
| 6 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | ||
| 7 | * | ||
| 8 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> | ||
| 9 | * Copyright (c) 2004 Zultys Technologies | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify it | ||
| 12 | * under the terms of the GNU General Public License as published by the | ||
| 13 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 14 | * option) any later version. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __PPC4XX_PIC_H__ | ||
| 18 | #define __PPC4XX_PIC_H__ | ||
| 19 | |||
| 20 | #include <linux/types.h> | ||
| 21 | #include <linux/irq.h> | ||
| 22 | |||
| 23 | /* "Fixed" UIC settings (they are chip, not board specific), | ||
| 24 | * e.g. polarity/triggerring for internal interrupt sources. | ||
| 25 | * | ||
| 26 | * Platform port should provide NR_UICS-sized array named ppc4xx_core_uic_cfg | ||
| 27 | * with these "fixed" settings: .polarity contains exact value which will | ||
| 28 | * be written (masked with "ext_irq_mask") into UICx_PR register, | ||
| 29 | * .triggering - to UICx_TR. | ||
| 30 | * | ||
| 31 | * Settings for external IRQs can be specified separately by the | ||
| 32 | * board support code. In this case properly sized array of unsigned | ||
| 33 | * char named ppc4xx_uic_ext_irq_cfg should be filled with correct | ||
| 34 | * values using IRQ_SENSE_XXXXX and IRQ_POLARITY_XXXXXXX defines. | ||
| 35 | * | ||
| 36 | * If these arrays aren't provided, UIC initialization code keeps firmware | ||
| 37 | * configuration. Also, ppc4xx_uic_ext_irq_cfg implies ppc4xx_core_uic_cfg | ||
| 38 | * is defined. | ||
| 39 | * | ||
| 40 | * Both ppc4xx_core_uic_cfg and ppc4xx_uic_ext_irq_cfg are declared as | ||
| 41 | * "weak" symbols in ppc4xx_pic.c | ||
| 42 | * | ||
| 43 | */ | ||
| 44 | struct ppc4xx_uic_settings { | ||
| 45 | u32 polarity; | ||
| 46 | u32 triggering; | ||
| 47 | u32 ext_irq_mask; | ||
| 48 | }; | ||
| 49 | |||
| 50 | extern void ppc4xx_pic_init(void); | ||
| 51 | |||
| 52 | #endif /* __PPC4XX_PIC_H__ */ | ||
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h deleted file mode 100644 index d2fee41d600b..000000000000 --- a/include/asm-ppc/ppc_sys.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/ppc_sys.h | ||
| 3 | * | ||
| 4 | * PPC system definitions and library functions | ||
| 5 | * | ||
| 6 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
| 7 | * | ||
| 8 | * Copyright 2005 Freescale Semiconductor, Inc | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | #ifndef __ASM_PPC_SYS_H | ||
| 18 | #define __ASM_PPC_SYS_H | ||
| 19 | |||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/types.h> | ||
| 23 | |||
| 24 | #if defined(CONFIG_8260) | ||
| 25 | #include <asm/mpc8260.h> | ||
| 26 | #elif defined(CONFIG_8xx) | ||
| 27 | #include <asm/mpc8xx.h> | ||
| 28 | #elif defined(CONFIG_PPC_MPC52xx) | ||
| 29 | #include <asm/mpc52xx.h> | ||
| 30 | #elif defined(CONFIG_MPC10X_BRIDGE) | ||
| 31 | #include <asm/mpc10x.h> | ||
| 32 | #else | ||
| 33 | #error "need definition of ppc_sys_devices" | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #define PPC_SYS_IORESOURCE_FIXUPPED 0x00000001 | ||
| 37 | |||
| 38 | struct ppc_sys_spec { | ||
| 39 | /* PPC sys is matched via (ID & mask) == value, id could be | ||
| 40 | * PVR, SVR, IMMR, * etc. */ | ||
| 41 | u32 mask; | ||
| 42 | u32 value; | ||
| 43 | u32 num_devices; | ||
| 44 | char *ppc_sys_name; | ||
| 45 | u8 config[NUM_PPC_SYS_DEVS]; | ||
| 46 | enum ppc_sys_devices *device_list; | ||
| 47 | }; | ||
| 48 | |||
| 49 | struct platform_notify_dev_map { | ||
| 50 | const char *bus_id; | ||
| 51 | void (*rtn)(struct platform_device * pdev, int idx); | ||
| 52 | }; | ||
| 53 | |||
| 54 | enum platform_device_func { | ||
| 55 | PPC_SYS_FUNC_DUMMY = 0, | ||
| 56 | PPC_SYS_FUNC_ETH = 1, | ||
| 57 | PPC_SYS_FUNC_UART = 2, | ||
| 58 | PPC_SYS_FUNC_HLDC = 3, | ||
| 59 | PPC_SYS_FUNC_USB = 4, | ||
| 60 | PPC_SYS_FUNC_IRDA = 5, | ||
| 61 | }; | ||
| 62 | |||
| 63 | #define PPC_SYS_CONFIG_DISABLED 1 | ||
| 64 | |||
| 65 | /* describes all specific chips and which devices they have on them */ | ||
| 66 | extern struct ppc_sys_spec ppc_sys_specs[]; | ||
| 67 | extern struct ppc_sys_spec *cur_ppc_sys_spec; | ||
| 68 | |||
| 69 | /* determine which specific SOC we are */ | ||
| 70 | extern void identify_ppc_sys_by_id(u32 id) __init; | ||
| 71 | extern void identify_ppc_sys_by_name(char *name) __init; | ||
| 72 | extern void identify_ppc_sys_by_name_and_id(char *name, u32 id) __init; | ||
| 73 | |||
| 74 | /* describes all devices that may exist in a given family of processors */ | ||
| 75 | extern struct platform_device ppc_sys_platform_devices[]; | ||
| 76 | |||
| 77 | /* allow any platform_device fixup to occur before device is registered */ | ||
| 78 | extern int (*ppc_sys_device_fixup) (struct platform_device * pdev); | ||
| 79 | |||
| 80 | /* Update all memory resources by paddr, call before platform_device_register */ | ||
| 81 | extern void ppc_sys_fixup_mem_resource(struct platform_device *pdev, | ||
| 82 | phys_addr_t paddr) __init; | ||
| 83 | |||
| 84 | /* Get platform_data pointer out of platform device, call before platform_device_register */ | ||
| 85 | extern void *ppc_sys_get_pdata(enum ppc_sys_devices dev) __init; | ||
| 86 | |||
| 87 | /* remove a device from the system */ | ||
| 88 | extern void ppc_sys_device_remove(enum ppc_sys_devices dev); | ||
| 89 | |||
| 90 | /* Function assignment stuff */ | ||
| 91 | void ppc_sys_device_initfunc(void); | ||
| 92 | void ppc_sys_device_setfunc(enum ppc_sys_devices dev, | ||
| 93 | enum platform_device_func func); | ||
| 94 | void ppc_sys_device_set_func_all(enum platform_device_func func); | ||
| 95 | |||
| 96 | void platform_notify_map(const struct platform_notify_dev_map *map, | ||
| 97 | struct device *dev); | ||
| 98 | |||
| 99 | /* Enable / disable stuff */ | ||
| 100 | void ppc_sys_device_disable(enum ppc_sys_devices dev); | ||
| 101 | void ppc_sys_device_enable(enum ppc_sys_devices dev); | ||
| 102 | void ppc_sys_device_enable_all(void); | ||
| 103 | void ppc_sys_device_disable_all(void); | ||
| 104 | |||
| 105 | #endif /* __ASM_PPC_SYS_H */ | ||
| 106 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h deleted file mode 100644 index 3819e17cd7b0..000000000000 --- a/include/asm-ppc/ppcboot.h +++ /dev/null | |||
| @@ -1,100 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * (C) Copyright 2000, 2001 | ||
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation; either version 2 of | ||
| 8 | * the License, or (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 18 | * MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_PPCBOOT_H__ | ||
| 22 | #define __ASM_PPCBOOT_H__ | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Board information passed to kernel from PPCBoot | ||
| 26 | * | ||
| 27 | * include/asm-ppc/ppcboot.h | ||
| 28 | */ | ||
| 29 | |||
| 30 | #ifndef __ASSEMBLY__ | ||
| 31 | #include <linux/types.h> | ||
| 32 | |||
| 33 | typedef struct bd_info { | ||
| 34 | unsigned long bi_memstart; /* start of DRAM memory */ | ||
| 35 | unsigned long bi_memsize; /* size of DRAM memory in bytes */ | ||
| 36 | unsigned long bi_flashstart; /* start of FLASH memory */ | ||
| 37 | unsigned long bi_flashsize; /* size of FLASH memory */ | ||
| 38 | unsigned long bi_flashoffset; /* reserved area for startup monitor */ | ||
| 39 | unsigned long bi_sramstart; /* start of SRAM memory */ | ||
| 40 | unsigned long bi_sramsize; /* size of SRAM memory */ | ||
| 41 | #if defined(CONFIG_8xx) || defined(CONFIG_CPM2) | ||
| 42 | unsigned long bi_immr_base; /* base of IMMR register */ | ||
| 43 | #endif | ||
| 44 | #if defined(CONFIG_PPC_MPC52xx) | ||
| 45 | unsigned long bi_mbar_base; /* base of internal registers */ | ||
| 46 | #endif | ||
| 47 | unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ | ||
| 48 | unsigned long bi_ip_addr; /* IP Address */ | ||
| 49 | unsigned char bi_enetaddr[6]; /* Ethernet address */ | ||
| 50 | unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ | ||
| 51 | unsigned long bi_intfreq; /* Internal Freq, in MHz */ | ||
| 52 | unsigned long bi_busfreq; /* Bus Freq, in MHz */ | ||
| 53 | #if defined(CONFIG_CPM2) | ||
| 54 | unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ | ||
| 55 | unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ | ||
| 56 | unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ | ||
| 57 | unsigned long bi_vco; /* VCO Out from PLL, in MHz */ | ||
| 58 | #endif | ||
| 59 | #if defined(CONFIG_PPC_MPC52xx) | ||
| 60 | unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ | ||
| 61 | unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ | ||
| 62 | #endif | ||
| 63 | unsigned long bi_baudrate; /* Console Baudrate */ | ||
| 64 | #if defined(CONFIG_4xx) | ||
| 65 | unsigned char bi_s_version[4]; /* Version of this structure */ | ||
| 66 | unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */ | ||
| 67 | unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ | ||
| 68 | unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ | ||
| 69 | unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ | ||
| 70 | unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ | ||
| 71 | #endif | ||
| 72 | #if defined(CONFIG_HYMOD) | ||
| 73 | hymod_conf_t bi_hymod_conf; /* hymod configuration information */ | ||
| 74 | #endif | ||
| 75 | #if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) | ||
| 76 | /* second onboard ethernet port */ | ||
| 77 | unsigned char bi_enet1addr[6]; | ||
| 78 | #endif | ||
| 79 | #if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) | ||
| 80 | /* third onboard ethernet ports */ | ||
| 81 | unsigned char bi_enet2addr[6]; | ||
| 82 | #endif | ||
| 83 | #if defined(CONFIG_440GX) | ||
| 84 | /* fourth onboard ethernet ports */ | ||
| 85 | unsigned char bi_enet3addr[6]; | ||
| 86 | #endif | ||
| 87 | #if defined(CONFIG_4xx) | ||
| 88 | unsigned int bi_opbfreq; /* OB clock in Hz */ | ||
| 89 | int bi_iic_fast[2]; /* Use fast i2c mode */ | ||
| 90 | #endif | ||
| 91 | #if defined(CONFIG_440GX) | ||
| 92 | int bi_phynum[4]; /* phy mapping */ | ||
| 93 | int bi_phymode[4]; /* phy mode */ | ||
| 94 | #endif | ||
| 95 | } bd_t; | ||
| 96 | |||
| 97 | #define bi_tbfreq bi_intfreq | ||
| 98 | |||
| 99 | #endif /* __ASSEMBLY__ */ | ||
| 100 | #endif /* __ASM_PPCBOOT_H__ */ | ||
diff --git a/include/asm-ppc/prep_nvram.h b/include/asm-ppc/prep_nvram.h deleted file mode 100644 index 6dbc36a84df2..000000000000 --- a/include/asm-ppc/prep_nvram.h +++ /dev/null | |||
| @@ -1,153 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * PreP compliant NVRAM access | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* Corey Minyard (minyard@acm.org) - Stolen from PReP book. Per the | ||
| 6 | license I must say: | ||
| 7 | (C) Copyright (Corey Minyard), (1998). All rights reserved | ||
| 8 | */ | ||
| 9 | |||
| 10 | /* Structure map for NVRAM on PowerPC Reference Platform */ | ||
| 11 | /* All fields are either character/byte strings which are valid either | ||
| 12 | endian or they are big-endian numbers. | ||
| 13 | |||
| 14 | There are a number of Date and Time fields which are in RTC format, | ||
| 15 | big-endian. These are stored in UT (GMT). | ||
| 16 | |||
| 17 | For enum's: if given in hex then they are bit significant, i.e. only | ||
| 18 | one bit is on for each enum. | ||
| 19 | */ | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | #ifndef _PPC_PREP_NVRAM_H | ||
| 22 | #define _PPC_PREP_NVRAM_H | ||
| 23 | |||
| 24 | #define MAX_PREP_NVRAM 0x8000 | ||
| 25 | #define PREP_NVRAM_AS0 0x74 | ||
| 26 | #define PREP_NVRAM_AS1 0x75 | ||
| 27 | #define PREP_NVRAM_DATA 0x77 | ||
| 28 | |||
| 29 | #define NVSIZE 4096 /* size of NVRAM */ | ||
| 30 | #define OSAREASIZE 512 /* size of OSArea space */ | ||
| 31 | #define CONFSIZE 1024 /* guess at size of Configuration space */ | ||
| 32 | |||
| 33 | typedef struct _SECURITY { | ||
| 34 | unsigned long BootErrCnt; /* Count of boot password errors */ | ||
| 35 | unsigned long ConfigErrCnt; /* Count of config password errors */ | ||
| 36 | unsigned long BootErrorDT[2]; /* Date&Time from RTC of last error in pw */ | ||
| 37 | unsigned long ConfigErrorDT[2]; /* Date&Time from RTC of last error in pw */ | ||
| 38 | unsigned long BootCorrectDT[2]; /* Date&Time from RTC of last correct pw */ | ||
| 39 | unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */ | ||
| 40 | unsigned long BootSetDT[2]; /* Date&Time from RTC of last set of pw */ | ||
| 41 | unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */ | ||
| 42 | unsigned char Serial[16]; /* Box serial number */ | ||
| 43 | } SECURITY; | ||
| 44 | |||
| 45 | typedef enum _OS_ID { | ||
| 46 | Unknown = 0, | ||
| 47 | Firmware = 1, | ||
| 48 | AIX = 2, | ||
| 49 | NT = 3, | ||
| 50 | MKOS2 = 4, | ||
| 51 | MKAIX = 5, | ||
| 52 | Taligent = 6, | ||
| 53 | Solaris = 7, | ||
| 54 | MK = 12 | ||
| 55 | } OS_ID; | ||
| 56 | |||
| 57 | typedef struct _ERROR_LOG { | ||
| 58 | unsigned char ErrorLogEntry[40]; /* To be architected */ | ||
| 59 | } ERROR_LOG; | ||
| 60 | |||
| 61 | typedef enum _BOOT_STATUS { | ||
| 62 | BootStarted = 0x01, | ||
| 63 | BootFinished = 0x02, | ||
| 64 | RestartStarted = 0x04, | ||
| 65 | RestartFinished = 0x08, | ||
| 66 | PowerFailStarted = 0x10, | ||
| 67 | PowerFailFinished = 0x20, | ||
| 68 | ProcessorReady = 0x40, | ||
| 69 | ProcessorRunning = 0x80, | ||
| 70 | ProcessorStart = 0x0100 | ||
| 71 | } BOOT_STATUS; | ||
| 72 | |||
| 73 | typedef struct _RESTART_BLOCK { | ||
| 74 | unsigned short Version; | ||
| 75 | unsigned short Revision; | ||
| 76 | unsigned long ResumeReserve1[2]; | ||
| 77 | volatile unsigned long BootStatus; | ||
| 78 | unsigned long CheckSum; /* Checksum of RESTART_BLOCK */ | ||
| 79 | void * RestartAddress; | ||
| 80 | void * SaveAreaAddr; | ||
| 81 | unsigned long SaveAreaLength; | ||
| 82 | } RESTART_BLOCK; | ||
| 83 | |||
| 84 | typedef enum _OSAREA_USAGE { | ||
| 85 | Empty = 0, | ||
| 86 | Used = 1 | ||
| 87 | } OSAREA_USAGE; | ||
| 88 | |||
| 89 | typedef enum _PM_MODE { | ||
| 90 | Suspend = 0x80, /* Part of state is in memory */ | ||
| 91 | Normal = 0x00 /* No power management in effect */ | ||
| 92 | } PMMODE; | ||
| 93 | |||
| 94 | typedef struct _HEADER { | ||
| 95 | unsigned short Size; /* NVRAM size in K(1024) */ | ||
| 96 | unsigned char Version; /* Structure map different */ | ||
| 97 | unsigned char Revision; /* Structure map the same -may | ||
| 98 | be new values in old fields | ||
| 99 | in other words old code still works */ | ||
| 100 | unsigned short Crc1; /* check sum from beginning of nvram to OSArea */ | ||
| 101 | unsigned short Crc2; /* check sum of config */ | ||
| 102 | unsigned char LastOS; /* OS_ID */ | ||
| 103 | unsigned char Endian; /* B if big endian, L if little endian */ | ||
| 104 | unsigned char OSAreaUsage; /* OSAREA_USAGE */ | ||
| 105 | unsigned char PMMode; /* Shutdown mode */ | ||
| 106 | RESTART_BLOCK RestartBlock; | ||
| 107 | SECURITY Security; | ||
| 108 | ERROR_LOG ErrorLog[2]; | ||
| 109 | |||
| 110 | /* Global Environment information */ | ||
| 111 | void * GEAddress; | ||
| 112 | unsigned long GELength; | ||
| 113 | |||
| 114 | /* Date&Time from RTC of last change to Global Environment */ | ||
| 115 | unsigned long GELastWriteDT[2]; | ||
| 116 | |||
| 117 | /* Configuration information */ | ||
| 118 | void * ConfigAddress; | ||
| 119 | unsigned long ConfigLength; | ||
| 120 | |||
| 121 | /* Date&Time from RTC of last change to Configuration */ | ||
| 122 | unsigned long ConfigLastWriteDT[2]; | ||
| 123 | unsigned long ConfigCount; /* Count of entries in Configuration */ | ||
| 124 | |||
| 125 | /* OS dependent temp area */ | ||
| 126 | void * OSAreaAddress; | ||
| 127 | unsigned long OSAreaLength; | ||
| 128 | |||
| 129 | /* Date&Time from RTC of last change to OSAreaArea */ | ||
| 130 | unsigned long OSAreaLastWriteDT[2]; | ||
| 131 | } HEADER; | ||
| 132 | |||
| 133 | /* Here is the whole map of the NVRAM */ | ||
| 134 | typedef struct _NVRAM_MAP { | ||
| 135 | HEADER Header; | ||
| 136 | unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)]; | ||
| 137 | unsigned char OSArea[OSAREASIZE]; | ||
| 138 | unsigned char ConfigArea[CONFSIZE]; | ||
| 139 | } NVRAM_MAP; | ||
| 140 | |||
| 141 | /* Routines to manipulate the NVRAM */ | ||
| 142 | void init_prep_nvram(void); | ||
| 143 | char *prep_nvram_get_var(const char *name); | ||
| 144 | char *prep_nvram_first_var(void); | ||
| 145 | char *prep_nvram_next_var(char *name); | ||
| 146 | |||
| 147 | /* Routines to read and write directly to the NVRAM */ | ||
| 148 | unsigned char prep_nvram_read_val(int addr); | ||
| 149 | void prep_nvram_write_val(int addr, | ||
| 150 | unsigned char val); | ||
| 151 | |||
| 152 | #endif /* _PPC_PREP_NVRAM_H */ | ||
| 153 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h deleted file mode 100644 index 71f4c996fe75..000000000000 --- a/include/asm-ppc/prom.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Definitions for talking to the Open Firmware PROM on | ||
| 3 | * Power Macintosh computers. | ||
| 4 | * | ||
| 5 | * Copyright (C) 1996 Paul Mackerras. | ||
| 6 | */ | ||
| 7 | #ifdef __KERNEL__ | ||
| 8 | #ifndef _PPC_PROM_H | ||
| 9 | #define _PPC_PROM_H | ||
| 10 | |||
| 11 | /* This is used in arch/ppc/mm/mem_pieces.h */ | ||
| 12 | struct reg_property { | ||
| 13 | unsigned int address; | ||
| 14 | unsigned int size; | ||
| 15 | }; | ||
| 16 | |||
| 17 | /* | ||
| 18 | * These macros assist in performing the address calculations that we | ||
| 19 | * need to do to access data when the kernel is running at an address | ||
| 20 | * that is different from the address that the kernel is linked at. | ||
| 21 | * The reloc_offset() function returns the difference between these | ||
| 22 | * two addresses and the macros simplify the process of adding or | ||
| 23 | * subtracting this offset to/from pointer values. | ||
| 24 | */ | ||
| 25 | extern unsigned long reloc_offset(void); | ||
| 26 | extern unsigned long add_reloc_offset(unsigned long); | ||
| 27 | extern unsigned long sub_reloc_offset(unsigned long); | ||
| 28 | |||
| 29 | #define PTRRELOC(x) ((typeof(x))add_reloc_offset((unsigned long)(x))) | ||
| 30 | #define PTRUNRELOC(x) ((typeof(x))sub_reloc_offset((unsigned long)(x))) | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Fallback definitions since we don't support OF in arch/ppc any more. | ||
| 34 | */ | ||
| 35 | #define machine_is_compatible(x) 0 | ||
| 36 | #define of_find_compatible_node(f, t, c) NULL | ||
| 37 | #define of_get_property(p, n, l) NULL | ||
| 38 | |||
| 39 | #endif /* _PPC_PROM_H */ | ||
| 40 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/raven.h b/include/asm-ppc/raven.h deleted file mode 100644 index 66f52cc0a03c..000000000000 --- a/include/asm-ppc/raven.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/raven.h -- Raven MPIC chip. | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998 Johnnie Peters | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifdef __KERNEL__ | ||
| 12 | #ifndef _ASMPPC_RAVEN_H | ||
| 13 | #define _ASMPPC_RAVEN_H | ||
| 14 | |||
| 15 | #define MVME2600_INT_SIO 0 | ||
| 16 | #define MVME2600_INT_FALCN_ECC_ERR 1 | ||
| 17 | #define MVME2600_INT_PCI_ETHERNET 2 | ||
| 18 | #define MVME2600_INT_PCI_SCSI 3 | ||
| 19 | #define MVME2600_INT_PCI_GRAPHICS 4 | ||
| 20 | #define MVME2600_INT_PCI_VME0 5 | ||
| 21 | #define MVME2600_INT_PCI_VME1 6 | ||
| 22 | #define MVME2600_INT_PCI_VME2 7 | ||
| 23 | #define MVME2600_INT_PCI_VME3 8 | ||
| 24 | #define MVME2600_INT_PCI_INTA 9 | ||
| 25 | #define MVME2600_INT_PCI_INTB 10 | ||
| 26 | #define MVME2600_INT_PCI_INTC 11 | ||
| 27 | #define MVME2600_INT_PCI_INTD 12 | ||
| 28 | #define MVME2600_INT_LM_SIG0 13 | ||
| 29 | #define MVME2600_INT_LM_SIG1 14 | ||
| 30 | |||
| 31 | extern struct hw_interrupt_type raven_pic; | ||
| 32 | |||
| 33 | extern int raven_init(void); | ||
| 34 | #endif /* _ASMPPC_RAVEN_H */ | ||
| 35 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h deleted file mode 100644 index 91e96af88bd8..000000000000 --- a/include/asm-ppc/reg_booke.h +++ /dev/null | |||
| @@ -1,443 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Contains register definitions common to the Book E PowerPC | ||
| 3 | * specification. Notice that while the IBM-40x series of CPUs | ||
| 4 | * are not true Book E PowerPCs, they borrowed a number of features | ||
| 5 | * before Book E was finalized, and are included here as well. Unfortunatly, | ||
| 6 | * they sometimes used different locations than true Book E CPUs did. | ||
| 7 | */ | ||
| 8 | #ifdef __KERNEL__ | ||
| 9 | #ifndef __ASM_PPC_REG_BOOKE_H__ | ||
| 10 | #define __ASM_PPC_REG_BOOKE_H__ | ||
| 11 | |||
| 12 | #ifndef __ASSEMBLY__ | ||
| 13 | /* Performance Monitor Registers */ | ||
| 14 | #define mfpmr(rn) ({unsigned int rval; \ | ||
| 15 | asm volatile("mfpmr %0," __stringify(rn) \ | ||
| 16 | : "=r" (rval)); rval;}) | ||
| 17 | #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) | ||
| 18 | #endif /* __ASSEMBLY__ */ | ||
| 19 | |||
| 20 | /* Freescale Book E Performance Monitor APU Registers */ | ||
| 21 | #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ | ||
| 22 | #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ | ||
| 23 | #define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ | ||
| 24 | #define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ | ||
| 25 | #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ | ||
| 26 | #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ | ||
| 27 | #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ | ||
| 28 | #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ | ||
| 29 | |||
| 30 | #define PMLCA_FC 0x80000000 /* Freeze Counter */ | ||
| 31 | #define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ | ||
| 32 | #define PMLCA_FCU 0x20000000 /* Freeze in User */ | ||
| 33 | #define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ | ||
| 34 | #define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ | ||
| 35 | #define PMLCA_CE 0x04000000 /* Condition Enable */ | ||
| 36 | |||
| 37 | #define PMLCA_EVENT_MASK 0x007f0000 /* Event field */ | ||
| 38 | #define PMLCA_EVENT_SHIFT 16 | ||
| 39 | |||
| 40 | #define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ | ||
| 41 | #define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ | ||
| 42 | #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ | ||
| 43 | #define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ | ||
| 44 | |||
| 45 | #define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */ | ||
| 46 | #define PMLCB_THRESHMUL_SHIFT 8 | ||
| 47 | |||
| 48 | #define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ | ||
| 49 | #define PMLCB_THRESHOLD_SHIFT 0 | ||
| 50 | |||
| 51 | #define PMRN_PMGC0 0x190 /* PM Global Control 0 */ | ||
| 52 | |||
| 53 | #define PMGC0_FAC 0x80000000 /* Freeze all Counters */ | ||
| 54 | #define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ | ||
| 55 | #define PMGC0_FCECE 0x20000000 /* Freeze countes on | ||
| 56 | Enabled Condition or | ||
| 57 | Event */ | ||
| 58 | |||
| 59 | #define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ | ||
| 60 | #define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ | ||
| 61 | #define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ | ||
| 62 | #define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ | ||
| 63 | #define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ | ||
| 64 | #define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ | ||
| 65 | #define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ | ||
| 66 | #define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ | ||
| 67 | #define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ | ||
| 68 | #define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ | ||
| 69 | #define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ | ||
| 70 | #define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ | ||
| 71 | #define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ | ||
| 72 | |||
| 73 | |||
| 74 | /* Machine State Register (MSR) Fields */ | ||
| 75 | #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ | ||
| 76 | #define MSR_SPE (1<<25) /* Enable SPE */ | ||
| 77 | #define MSR_DWE (1<<10) /* Debug Wait Enable */ | ||
| 78 | #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ | ||
| 79 | #define MSR_IS MSR_IR /* Instruction Space */ | ||
| 80 | #define MSR_DS MSR_DR /* Data Space */ | ||
| 81 | #define MSR_PMM (1<<2) /* Performance monitor mark bit */ | ||
| 82 | |||
| 83 | /* Default MSR for kernel mode. */ | ||
| 84 | #if defined (CONFIG_40x) | ||
| 85 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) | ||
| 86 | #elif defined(CONFIG_BOOKE) | ||
| 87 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) | ||
| 88 | #endif | ||
| 89 | |||
| 90 | /* Special Purpose Registers (SPRNs)*/ | ||
| 91 | #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ | ||
| 92 | #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ | ||
| 93 | #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ | ||
| 94 | #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ | ||
| 95 | #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ | ||
| 96 | #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ | ||
| 97 | #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ | ||
| 98 | #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ | ||
| 99 | #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ | ||
| 100 | #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ | ||
| 101 | #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ | ||
| 102 | #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ | ||
| 103 | #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ | ||
| 104 | #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ | ||
| 105 | #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ | ||
| 106 | #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ | ||
| 107 | #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ | ||
| 108 | #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ | ||
| 109 | #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ | ||
| 110 | #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ | ||
| 111 | #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ | ||
| 112 | #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ | ||
| 113 | #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ | ||
| 114 | #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ | ||
| 115 | #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ | ||
| 116 | #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ | ||
| 117 | #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ | ||
| 118 | #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ | ||
| 119 | #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ | ||
| 120 | #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ | ||
| 121 | #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ | ||
| 122 | #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ | ||
| 123 | #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ | ||
| 124 | #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ | ||
| 125 | #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ | ||
| 126 | #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ | ||
| 127 | #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ | ||
| 128 | #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ | ||
| 129 | #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ | ||
| 130 | #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ | ||
| 131 | #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ | ||
| 132 | #define SPRN_MCSR 0x23C /* Machine Check Status Register */ | ||
| 133 | #define SPRN_MCAR 0x23D /* Machine Check Address Register */ | ||
| 134 | #define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ | ||
| 135 | #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ | ||
| 136 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ | ||
| 137 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ | ||
| 138 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | ||
| 139 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ | ||
| 140 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ | ||
| 141 | #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ | ||
| 142 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ | ||
| 143 | #define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */ | ||
| 144 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ | ||
| 145 | #define SPRN_PID2 0x27A /* Process ID Register 2 */ | ||
| 146 | #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ | ||
| 147 | #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ | ||
| 148 | #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ | ||
| 149 | #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ | ||
| 150 | #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ | ||
| 151 | #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ | ||
| 152 | #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ | ||
| 153 | #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ | ||
| 154 | #define SPRN_SLER 0x3BB /* Little-endian real mode */ | ||
| 155 | #define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ | ||
| 156 | #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ | ||
| 157 | #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ | ||
| 158 | #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ | ||
| 159 | #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ | ||
| 160 | #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ | ||
| 161 | #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ | ||
| 162 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ | ||
| 163 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ | ||
| 164 | #define SPRN_SVR 0x3FF /* System Version Register */ | ||
| 165 | |||
| 166 | /* | ||
| 167 | * SPRs which have conflicting definitions on true Book E versus classic, | ||
| 168 | * or IBM 40x. | ||
| 169 | */ | ||
| 170 | #ifdef CONFIG_BOOKE | ||
| 171 | #define SPRN_PID 0x030 /* Process ID */ | ||
| 172 | #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ | ||
| 173 | #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ | ||
| 174 | #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ | ||
| 175 | #define SPRN_DEAR 0x03D /* Data Error Address Register */ | ||
| 176 | #define SPRN_ESR 0x03E /* Exception Syndrome Register */ | ||
| 177 | #define SPRN_PIR 0x11E /* Processor Identification Register */ | ||
| 178 | #define SPRN_DBSR 0x130 /* Debug Status Register */ | ||
| 179 | #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ | ||
| 180 | #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ | ||
| 181 | #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ | ||
| 182 | #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ | ||
| 183 | #define SPRN_DAC1 0x13C /* Data Address Compare 1 */ | ||
| 184 | #define SPRN_DAC2 0x13D /* Data Address Compare 2 */ | ||
| 185 | #define SPRN_TSR 0x150 /* Timer Status Register */ | ||
| 186 | #define SPRN_TCR 0x154 /* Timer Control Register */ | ||
| 187 | #endif /* Book E */ | ||
| 188 | #ifdef CONFIG_40x | ||
| 189 | #define SPRN_PID 0x3B1 /* Process ID */ | ||
| 190 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ | ||
| 191 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ | ||
| 192 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ | ||
| 193 | #define SPRN_TSR 0x3D8 /* Timer Status Register */ | ||
| 194 | #define SPRN_TCR 0x3DA /* Timer Control Register */ | ||
| 195 | #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ | ||
| 196 | #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ | ||
| 197 | #define SPRN_DBSR 0x3F0 /* Debug Status Register */ | ||
| 198 | #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ | ||
| 199 | #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ | ||
| 200 | #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ | ||
| 201 | #define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ | ||
| 202 | #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ | ||
| 203 | #endif | ||
| 204 | |||
| 205 | /* Bit definitions for CCR1. */ | ||
| 206 | #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ | ||
| 207 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ | ||
| 208 | |||
| 209 | /* Bit definitions for the MCSR. */ | ||
| 210 | #ifdef CONFIG_4xx | ||
| 211 | #define MCSR_MCS 0x80000000 /* Machine Check Summary */ | ||
| 212 | #define MCSR_IB 0x40000000 /* Instruction PLB Error */ | ||
| 213 | #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ | ||
| 214 | #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ | ||
| 215 | #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ | ||
| 216 | #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ | ||
| 217 | #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ | ||
| 218 | #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ | ||
| 219 | #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ | ||
| 220 | #endif | ||
| 221 | |||
| 222 | /* Bit definitions for the DBSR. */ | ||
| 223 | /* | ||
| 224 | * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. | ||
| 225 | */ | ||
| 226 | #ifdef CONFIG_BOOKE | ||
| 227 | #define DBSR_IC 0x08000000 /* Instruction Completion */ | ||
| 228 | #define DBSR_BT 0x04000000 /* Branch Taken */ | ||
| 229 | #define DBSR_TIE 0x01000000 /* Trap Instruction Event */ | ||
| 230 | #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ | ||
| 231 | #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ | ||
| 232 | #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ | ||
| 233 | #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ | ||
| 234 | #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ | ||
| 235 | #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ | ||
| 236 | #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ | ||
| 237 | #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ | ||
| 238 | #endif | ||
| 239 | #ifdef CONFIG_40x | ||
| 240 | #define DBSR_IC 0x80000000 /* Instruction Completion */ | ||
| 241 | #define DBSR_BT 0x40000000 /* Branch taken */ | ||
| 242 | #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ | ||
| 243 | #define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ | ||
| 244 | #define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ | ||
| 245 | #define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ | ||
| 246 | #define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ | ||
| 247 | #define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ | ||
| 248 | #define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ | ||
| 249 | #define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ | ||
| 250 | #define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ | ||
| 251 | #endif | ||
| 252 | |||
| 253 | /* Bit definitions related to the ESR. */ | ||
| 254 | #define ESR_MCI 0x80000000 /* Machine Check - Instruction */ | ||
| 255 | #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ | ||
| 256 | #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ | ||
| 257 | #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ | ||
| 258 | #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ | ||
| 259 | #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ | ||
| 260 | #define ESR_PPR 0x04000000 /* Program Exception - Privileged */ | ||
| 261 | #define ESR_PTR 0x02000000 /* Program Exception - Trap */ | ||
| 262 | #define ESR_FP 0x01000000 /* Floating Point Operation */ | ||
| 263 | #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ | ||
| 264 | #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ | ||
| 265 | #define ESR_ST 0x00800000 /* Store Operation */ | ||
| 266 | #define ESR_DLK 0x00200000 /* Data Cache Locking */ | ||
| 267 | #define ESR_ILK 0x00100000 /* Instr. Cache Locking */ | ||
| 268 | #define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ | ||
| 269 | #define ESR_BO 0x00020000 /* Byte Ordering */ | ||
| 270 | |||
| 271 | /* Bit definitions related to the DBCR0. */ | ||
| 272 | #define DBCR0_EDM 0x80000000 /* External Debug Mode */ | ||
| 273 | #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ | ||
| 274 | #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ | ||
| 275 | #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ | ||
| 276 | #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ | ||
| 277 | #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ | ||
| 278 | #define DBCR0_RST_NONE 0x00000000 /* No Reset */ | ||
| 279 | #define DBCR0_IC 0x08000000 /* Instruction Completion */ | ||
| 280 | #define DBCR0_BT 0x04000000 /* Branch Taken */ | ||
| 281 | #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ | ||
| 282 | #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ | ||
| 283 | #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ | ||
| 284 | #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ | ||
| 285 | #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ | ||
| 286 | #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ | ||
| 287 | #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ | ||
| 288 | #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ | ||
| 289 | #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ | ||
| 290 | #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ | ||
| 291 | #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ | ||
| 292 | #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ | ||
| 293 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ | ||
| 294 | |||
| 295 | /* Bit definitions related to the TCR. */ | ||
| 296 | #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ | ||
| 297 | #define TCR_WP_MASK TCR_WP(3) | ||
| 298 | #define WP_2_17 0 /* 2^17 clocks */ | ||
| 299 | #define WP_2_21 1 /* 2^21 clocks */ | ||
| 300 | #define WP_2_25 2 /* 2^25 clocks */ | ||
| 301 | #define WP_2_29 3 /* 2^29 clocks */ | ||
| 302 | #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ | ||
| 303 | #define TCR_WRC_MASK TCR_WRC(3) | ||
| 304 | #define WRC_NONE 0 /* No reset will occur */ | ||
| 305 | #define WRC_CORE 1 /* Core reset will occur */ | ||
| 306 | #define WRC_CHIP 2 /* Chip reset will occur */ | ||
| 307 | #define WRC_SYSTEM 3 /* System reset will occur */ | ||
| 308 | #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ | ||
| 309 | #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ | ||
| 310 | #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ | ||
| 311 | #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ | ||
| 312 | #define TCR_FP_MASK TCR_FP(3) | ||
| 313 | #define FP_2_9 0 /* 2^9 clocks */ | ||
| 314 | #define FP_2_13 1 /* 2^13 clocks */ | ||
| 315 | #define FP_2_17 2 /* 2^17 clocks */ | ||
| 316 | #define FP_2_21 3 /* 2^21 clocks */ | ||
| 317 | #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ | ||
| 318 | #define TCR_ARE 0x00400000 /* Auto Reload Enable */ | ||
| 319 | |||
| 320 | /* Bit definitions for the TSR. */ | ||
| 321 | #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ | ||
| 322 | #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ | ||
| 323 | #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ | ||
| 324 | #define WRS_NONE 0 /* No WDT reset occurred */ | ||
| 325 | #define WRS_CORE 1 /* WDT forced core reset */ | ||
| 326 | #define WRS_CHIP 2 /* WDT forced chip reset */ | ||
| 327 | #define WRS_SYSTEM 3 /* WDT forced system reset */ | ||
| 328 | #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ | ||
| 329 | #define TSR_DIS TSR_PIS /* DEC Interrupt Status */ | ||
| 330 | #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ | ||
| 331 | |||
| 332 | /* Bit definitions for the DCCR. */ | ||
| 333 | #define DCCR_NOCACHE 0 /* Noncacheable */ | ||
| 334 | #define DCCR_CACHE 1 /* Cacheable */ | ||
| 335 | |||
| 336 | /* Bit definitions for DCWR. */ | ||
| 337 | #define DCWR_COPY 0 /* Copy-back */ | ||
| 338 | #define DCWR_WRITE 1 /* Write-through */ | ||
| 339 | |||
| 340 | /* Bit definitions for ICCR. */ | ||
| 341 | #define ICCR_NOCACHE 0 /* Noncacheable */ | ||
| 342 | #define ICCR_CACHE 1 /* Cacheable */ | ||
| 343 | |||
| 344 | /* Bit definitions for L1CSR0. */ | ||
| 345 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ | ||
| 346 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | ||
| 347 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ | ||
| 348 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | ||
| 349 | |||
| 350 | /* Bit definitions for L1CSR1. */ | ||
| 351 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ | ||
| 352 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ | ||
| 353 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ | ||
| 354 | |||
| 355 | /* Bit definitions for SGR. */ | ||
| 356 | #define SGR_NORMAL 0 /* Speculative fetching allowed. */ | ||
| 357 | #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ | ||
| 358 | |||
| 359 | /* Bit definitions for SPEFSCR. */ | ||
| 360 | #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ | ||
| 361 | #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ | ||
| 362 | #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ | ||
| 363 | #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ | ||
| 364 | #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ | ||
| 365 | #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ | ||
| 366 | #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ | ||
| 367 | #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ | ||
| 368 | #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ | ||
| 369 | #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ | ||
| 370 | #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ | ||
| 371 | #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ | ||
| 372 | #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ | ||
| 373 | #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ | ||
| 374 | #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ | ||
| 375 | #define SPEFSCR_OV 0x00004000 /* Integer overflow */ | ||
| 376 | #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ | ||
| 377 | #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ | ||
| 378 | #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ | ||
| 379 | #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ | ||
| 380 | #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ | ||
| 381 | #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ | ||
| 382 | #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ | ||
| 383 | #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ | ||
| 384 | #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ | ||
| 385 | #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ | ||
| 386 | #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ | ||
| 387 | #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ | ||
| 388 | |||
| 389 | /* | ||
| 390 | * The IBM-403 is an even more odd special case, as it is much | ||
| 391 | * older than the IBM-405 series. We put these down here incase someone | ||
| 392 | * wishes to support these machines again. | ||
| 393 | */ | ||
| 394 | #ifdef CONFIG_403GCX | ||
| 395 | /* Special Purpose Registers (SPRNs)*/ | ||
| 396 | #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ | ||
| 397 | #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ | ||
| 398 | #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ | ||
| 399 | #define SPRN_TBHI 0x3DC /* Time Base High */ | ||
| 400 | #define SPRN_TBLO 0x3DD /* Time Base Low */ | ||
| 401 | #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ | ||
| 402 | #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ | ||
| 403 | #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ | ||
| 404 | #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ | ||
| 405 | #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ | ||
| 406 | |||
| 407 | |||
| 408 | /* Bit definitions for the DBCR. */ | ||
| 409 | #define DBCR_EDM DBCR0_EDM | ||
| 410 | #define DBCR_IDM DBCR0_IDM | ||
| 411 | #define DBCR_RST(x) (((x) & 0x3) << 28) | ||
| 412 | #define DBCR_RST_NONE 0 | ||
| 413 | #define DBCR_RST_CORE 1 | ||
| 414 | #define DBCR_RST_CHIP 2 | ||
| 415 | #define DBCR_RST_SYSTEM 3 | ||
| 416 | #define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ | ||
| 417 | #define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ | ||
| 418 | #define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ | ||
| 419 | #define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ | ||
| 420 | #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ | ||
| 421 | #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ | ||
| 422 | #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ | ||
| 423 | #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ | ||
| 424 | #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ | ||
| 425 | #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ | ||
| 426 | #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ | ||
| 427 | #define DAC_BYTE 0 | ||
| 428 | #define DAC_HALF 1 | ||
| 429 | #define DAC_WORD 2 | ||
| 430 | #define DAC_QUAD 3 | ||
| 431 | #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ | ||
| 432 | #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ | ||
| 433 | #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ | ||
| 434 | #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ | ||
| 435 | #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ | ||
| 436 | #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ | ||
| 437 | #define DBCR_SIA 0x00000008 /* Second IAC Enable */ | ||
| 438 | #define DBCR_SDA 0x00000004 /* Second DAC Enable */ | ||
| 439 | #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ | ||
| 440 | #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ | ||
| 441 | #endif /* 403GCX */ | ||
| 442 | #endif /* __ASM_PPC_REG_BOOKE_H__ */ | ||
| 443 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h deleted file mode 100644 index 934810d25667..000000000000 --- a/include/asm-ppc/residual.h +++ /dev/null | |||
| @@ -1,350 +0,0 @@ | |||
| 1 | /* 7/18/95 */ | ||
| 2 | /*----------------------------------------------------------------------------*/ | ||
| 3 | /* Residual Data header definitions and prototypes */ | ||
| 4 | /*----------------------------------------------------------------------------*/ | ||
| 5 | |||
| 6 | /* Structure map for RESIDUAL on PowerPC Reference Platform */ | ||
| 7 | /* residual.h - Residual data structure passed in r3. */ | ||
| 8 | /* Load point passed in r4 to boot image. */ | ||
| 9 | /* For enum's: if given in hex then they are bit significant, */ | ||
| 10 | /* i.e. only one bit is on for each enum */ | ||
| 11 | /* Reserved fields must be filled with zeros. */ | ||
| 12 | |||
| 13 | #ifdef __KERNEL__ | ||
| 14 | #ifndef _RESIDUAL_ | ||
| 15 | #define _RESIDUAL_ | ||
| 16 | |||
| 17 | #ifndef __ASSEMBLY__ | ||
| 18 | |||
| 19 | #define MAX_CPUS 32 /* These should be set to the maximum */ | ||
| 20 | #define MAX_MEMS 64 /* number possible for this system. */ | ||
| 21 | #define MAX_DEVICES 256 /* Changing these will change the */ | ||
| 22 | #define AVE_PNP_SIZE 32 /* structure, hence the version of */ | ||
| 23 | #define MAX_MEM_SEGS 64 /* this header file. */ | ||
| 24 | |||
| 25 | /*----------------------------------------------------------------------------*/ | ||
| 26 | /* Public structures... */ | ||
| 27 | /*----------------------------------------------------------------------------*/ | ||
| 28 | |||
| 29 | #include <asm/pnp.h> | ||
| 30 | |||
| 31 | typedef enum _L1CACHE_TYPE { | ||
| 32 | NoneCAC = 0, | ||
| 33 | SplitCAC = 1, | ||
| 34 | CombinedCAC = 2 | ||
| 35 | } L1CACHE_TYPE; | ||
| 36 | |||
| 37 | typedef enum _TLB_TYPE { | ||
| 38 | NoneTLB = 0, | ||
| 39 | SplitTLB = 1, | ||
| 40 | CombinedTLB = 2 | ||
| 41 | } TLB_TYPE; | ||
| 42 | |||
| 43 | typedef enum _FIRMWARE_SUPPORT { | ||
| 44 | Conventional = 0x01, | ||
| 45 | OpenFirmware = 0x02, | ||
| 46 | Diagnostics = 0x04, | ||
| 47 | LowDebug = 0x08, | ||
| 48 | Multiboot = 0x10, | ||
| 49 | LowClient = 0x20, | ||
| 50 | Hex41 = 0x40, | ||
| 51 | FAT = 0x80, | ||
| 52 | ISO9660 = 0x0100, | ||
| 53 | SCSI_InitiatorID_Override = 0x0200, | ||
| 54 | Tape_Boot = 0x0400, | ||
| 55 | FW_Boot_Path = 0x0800 | ||
| 56 | } FIRMWARE_SUPPORT; | ||
| 57 | |||
| 58 | typedef enum _FIRMWARE_SUPPLIERS { | ||
| 59 | IBMFirmware = 0x00, | ||
| 60 | MotoFirmware = 0x01, /* 7/18/95 */ | ||
| 61 | FirmWorks = 0x02, /* 10/5/95 */ | ||
| 62 | Bull = 0x03, /* 04/03/96 */ | ||
| 63 | } FIRMWARE_SUPPLIERS; | ||
| 64 | |||
| 65 | typedef enum _ENDIAN_SWITCH_METHODS { | ||
| 66 | UsePort92 = 0x01, | ||
| 67 | UsePCIConfigA8 = 0x02, | ||
| 68 | UseFF001030 = 0x03, | ||
| 69 | } ENDIAN_SWITCH_METHODS; | ||
| 70 | |||
| 71 | typedef enum _SPREAD_IO_METHODS { | ||
| 72 | UsePort850 = 0x00, | ||
| 73 | /*UsePCIConfigA8 = 0x02,*/ | ||
| 74 | } SPREAD_IO_METHODS; | ||
| 75 | |||
| 76 | typedef struct _VPD { | ||
| 77 | |||
| 78 | /* Box dependent stuff */ | ||
| 79 | unsigned char PrintableModel[32]; /* Null terminated string. | ||
| 80 | Must be of the form: | ||
| 81 | vvv,<20h>,<model designation>,<0x0> | ||
| 82 | where vvv is the vendor ID | ||
| 83 | e.g. IBM PPS MODEL 6015<0x0> */ | ||
| 84 | unsigned char Serial[16]; /* 12/94: | ||
| 85 | Serial Number; must be of the form: | ||
| 86 | vvv<serial number> where vvv is the | ||
| 87 | vendor ID. | ||
| 88 | e.g. IBM60151234567<20h><20h> */ | ||
| 89 | unsigned char Reserved[48]; | ||
| 90 | unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ | ||
| 91 | unsigned long FirmwareSupports; /* See FirmwareSupport enum */ | ||
| 92 | unsigned long NvramSize; /* Size of nvram in bytes */ | ||
| 93 | unsigned long NumSIMMSlots; | ||
| 94 | unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ | ||
| 95 | unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ | ||
| 96 | unsigned long SmpIar; | ||
| 97 | unsigned long RAMErrLogOffset; /* Heap offset to error log */ | ||
| 98 | unsigned long Reserved5; | ||
| 99 | unsigned long Reserved6; | ||
| 100 | unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ | ||
| 101 | unsigned long ProcessorBusHz; /* Processor bus clock frequency */ | ||
| 102 | unsigned long Reserved7; | ||
| 103 | unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ | ||
| 104 | unsigned long WordWidth; /* Word width in bits */ | ||
| 105 | unsigned long PageSize; /* Page size in bytes */ | ||
| 106 | unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache | ||
| 107 | for which coherency is maintained; | ||
| 108 | normally <= CacheLineSize. */ | ||
| 109 | unsigned long GranuleSize; /* Unit of lock allocation to avoid */ | ||
| 110 | /* false sharing of locks. */ | ||
| 111 | |||
| 112 | /* L1 Cache variables */ | ||
| 113 | unsigned long CacheSize; /* L1 Cache size in KB. This is the */ | ||
| 114 | /* total size of the L1, whether */ | ||
| 115 | /* combined or split */ | ||
| 116 | unsigned long CacheAttrib; /* L1CACHE_TYPE */ | ||
| 117 | unsigned long CacheAssoc; /* L1 Cache associativity. Use this | ||
| 118 | for combined cache. If split, put | ||
| 119 | zeros here. */ | ||
| 120 | unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use | ||
| 121 | for combined cache. If split, put | ||
| 122 | zeros here. */ | ||
| 123 | /* For split L1 Cache: (= combined if combined cache) */ | ||
| 124 | unsigned long I_CacheSize; | ||
| 125 | unsigned long I_CacheAssoc; | ||
| 126 | unsigned long I_CacheLineSize; | ||
| 127 | unsigned long D_CacheSize; | ||
| 128 | unsigned long D_CacheAssoc; | ||
| 129 | unsigned long D_CacheLineSize; | ||
| 130 | |||
| 131 | /* Translation Lookaside Buffer variables */ | ||
| 132 | unsigned long TLBSize; /* Total number of TLBs on the system */ | ||
| 133 | unsigned long TLBAttrib; /* Combined I+D or split TLB */ | ||
| 134 | unsigned long TLBAssoc; /* TLB Associativity. Use this for | ||
| 135 | combined TLB. If split, put zeros | ||
| 136 | here. */ | ||
| 137 | /* For split TLB: (= combined if combined TLB) */ | ||
| 138 | unsigned long I_TLBSize; | ||
| 139 | unsigned long I_TLBAssoc; | ||
| 140 | unsigned long D_TLBSize; | ||
| 141 | unsigned long D_TLBAssoc; | ||
| 142 | |||
| 143 | unsigned long ExtendedVPD; /* Offset to extended VPD area; | ||
| 144 | null if unused */ | ||
| 145 | } VPD; | ||
| 146 | |||
| 147 | typedef enum _DEVICE_FLAGS { | ||
| 148 | Enabled = 0x4000, /* 1 - PCI device is enabled */ | ||
| 149 | Integrated = 0x2000, | ||
| 150 | Failed = 0x1000, /* 1 - device failed POST code tests */ | ||
| 151 | Static = 0x0800, /* 0 - dynamically configurable | ||
| 152 | 1 - static */ | ||
| 153 | Dock = 0x0400, /* 0 - not a docking station device | ||
| 154 | 1 - is a docking station device */ | ||
| 155 | Boot = 0x0200, /* 0 - device cannot be used for BOOT | ||
| 156 | 1 - can be a BOOT device */ | ||
| 157 | Configurable = 0x0100, /* 1 - device is configurable */ | ||
| 158 | Disableable = 0x80, /* 1 - device can be disabled */ | ||
| 159 | PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ | ||
| 160 | ReadOnly = 0x20, /* 1 - device is read only */ | ||
| 161 | Removable = 0x10, /* 1 - device is removable */ | ||
| 162 | ConsoleIn = 0x08, | ||
| 163 | ConsoleOut = 0x04, | ||
| 164 | Input = 0x02, | ||
| 165 | Output = 0x01 | ||
| 166 | } DEVICE_FLAGS; | ||
| 167 | |||
| 168 | typedef enum _BUS_ID { | ||
| 169 | ISADEVICE = 0x01, | ||
| 170 | EISADEVICE = 0x02, | ||
| 171 | PCIDEVICE = 0x04, | ||
| 172 | PCMCIADEVICE = 0x08, | ||
| 173 | PNPISADEVICE = 0x10, | ||
| 174 | MCADEVICE = 0x20, | ||
| 175 | MXDEVICE = 0x40, /* Devices on mezzanine bus */ | ||
| 176 | PROCESSORDEVICE = 0x80, /* Devices on processor bus */ | ||
| 177 | VMEDEVICE = 0x100, | ||
| 178 | } BUS_ID; | ||
| 179 | |||
| 180 | typedef struct _DEVICE_ID { | ||
| 181 | unsigned long BusId; /* See BUS_ID enum above */ | ||
| 182 | unsigned long DevId; /* Big Endian format */ | ||
| 183 | unsigned long SerialNum; /* For multiple usage of a single | ||
| 184 | DevId */ | ||
| 185 | unsigned long Flags; /* See DEVICE_FLAGS enum above */ | ||
| 186 | unsigned char BaseType; /* See pnp.h for bit definitions */ | ||
| 187 | unsigned char SubType; /* See pnp.h for bit definitions */ | ||
| 188 | unsigned char Interface; /* See pnp.h for bit definitions */ | ||
| 189 | unsigned char Spare; | ||
| 190 | } DEVICE_ID; | ||
| 191 | |||
| 192 | typedef union _BUS_ACCESS { | ||
| 193 | struct _PnPAccess{ | ||
| 194 | unsigned char CSN; | ||
| 195 | unsigned char LogicalDevNumber; | ||
| 196 | unsigned short ReadDataPort; | ||
| 197 | } PnPAccess; | ||
| 198 | struct _ISAAccess{ | ||
| 199 | unsigned char SlotNumber; /* ISA Slot Number generally not | ||
| 200 | available; 0 if unknown */ | ||
| 201 | unsigned char LogicalDevNumber; | ||
| 202 | unsigned short ISAReserved; | ||
| 203 | } ISAAccess; | ||
| 204 | struct _MCAAccess{ | ||
| 205 | unsigned char SlotNumber; | ||
| 206 | unsigned char LogicalDevNumber; | ||
| 207 | unsigned short MCAReserved; | ||
| 208 | } MCAAccess; | ||
| 209 | struct _PCMCIAAccess{ | ||
| 210 | unsigned char SlotNumber; | ||
| 211 | unsigned char LogicalDevNumber; | ||
| 212 | unsigned short PCMCIAReserved; | ||
| 213 | } PCMCIAAccess; | ||
| 214 | struct _EISAAccess{ | ||
| 215 | unsigned char SlotNumber; | ||
| 216 | unsigned char FunctionNumber; | ||
| 217 | unsigned short EISAReserved; | ||
| 218 | } EISAAccess; | ||
| 219 | struct _PCIAccess{ | ||
| 220 | unsigned char BusNumber; | ||
| 221 | unsigned char DevFuncNumber; | ||
| 222 | unsigned short PCIReserved; | ||
| 223 | } PCIAccess; | ||
| 224 | struct _ProcBusAccess{ | ||
| 225 | unsigned char BusNumber; | ||
| 226 | unsigned char BUID; | ||
| 227 | unsigned short ProcBusReserved; | ||
| 228 | } ProcBusAccess; | ||
| 229 | } BUS_ACCESS; | ||
| 230 | |||
| 231 | /* Per logical device information */ | ||
| 232 | typedef struct _PPC_DEVICE { | ||
| 233 | DEVICE_ID DeviceId; | ||
| 234 | BUS_ACCESS BusAccess; | ||
| 235 | |||
| 236 | /* The following three are offsets into the DevicePnPHeap */ | ||
| 237 | /* All are in PnP compressed format */ | ||
| 238 | unsigned long AllocatedOffset; /* Allocated resource description */ | ||
| 239 | unsigned long PossibleOffset; /* Possible resource description */ | ||
| 240 | unsigned long CompatibleOffset; /* Compatible device identifiers */ | ||
| 241 | } PPC_DEVICE; | ||
| 242 | |||
| 243 | typedef enum _CPU_STATE { | ||
| 244 | CPU_GOOD = 0, /* CPU is present, and active */ | ||
| 245 | CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ | ||
| 246 | CPU_OFF = 2, /* CPU is present, but inactive */ | ||
| 247 | CPU_FAILED = 3, /* CPU is present, but failed POST */ | ||
| 248 | CPU_NOT_PRESENT = 255 /* CPU not present */ | ||
| 249 | } CPU_STATE; | ||
| 250 | |||
| 251 | typedef struct _PPC_CPU { | ||
| 252 | unsigned long CpuType; /* Result of mfspr from Processor | ||
| 253 | Version Register (PVR). | ||
| 254 | PVR(0-15) = Version (e.g. 601) | ||
| 255 | PVR(16-31 = EC Level */ | ||
| 256 | unsigned char CpuNumber; /* CPU Number for this processor */ | ||
| 257 | unsigned char CpuState; /* CPU State, see CPU_STATE enum */ | ||
| 258 | unsigned short Reserved; | ||
| 259 | } PPC_CPU; | ||
| 260 | |||
| 261 | typedef struct _PPC_MEM { | ||
| 262 | unsigned long SIMMSize; /* 0 - absent or bad | ||
| 263 | 8M, 32M (in MB) */ | ||
| 264 | } PPC_MEM; | ||
| 265 | |||
| 266 | typedef enum _MEM_USAGE { | ||
| 267 | Other = 0x8000, | ||
| 268 | ResumeBlock = 0x4000, /* for use by power management */ | ||
| 269 | SystemROM = 0x2000, /* Flash memory (populated) */ | ||
| 270 | UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ | ||
| 271 | IOMemory = 0x0800, | ||
| 272 | SystemIO = 0x0400, | ||
| 273 | SystemRegs = 0x0200, | ||
| 274 | PCIAddr = 0x0100, | ||
| 275 | PCIConfig = 0x80, | ||
| 276 | ISAAddr = 0x40, | ||
| 277 | Unpopulated = 0x20, /* Unpopulated part of System Memory */ | ||
| 278 | Free = 0x10, /* Free part of System Memory */ | ||
| 279 | BootImage = 0x08, /* BootImage part of System Memory */ | ||
| 280 | FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ | ||
| 281 | FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ | ||
| 282 | FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ | ||
| 283 | } MEM_USAGE; | ||
| 284 | |||
| 285 | typedef struct _MEM_MAP { | ||
| 286 | unsigned long Usage; /* See MEM_USAGE above */ | ||
| 287 | unsigned long BasePage; /* Page number measured in 4KB pages */ | ||
| 288 | unsigned long PageCount; /* Page count measured in 4KB pages */ | ||
| 289 | } MEM_MAP; | ||
| 290 | |||
| 291 | typedef struct _RESIDUAL { | ||
| 292 | unsigned long ResidualLength; /* Length of Residual */ | ||
| 293 | unsigned char Version; /* of this data structure */ | ||
| 294 | unsigned char Revision; /* of this data structure */ | ||
| 295 | unsigned short EC; /* of this data structure */ | ||
| 296 | /* VPD */ | ||
| 297 | VPD VitalProductData; | ||
| 298 | /* CPU */ | ||
| 299 | unsigned short MaxNumCpus; /* Max CPUs in this system */ | ||
| 300 | unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ | ||
| 301 | /* that there are unpopulated or */ | ||
| 302 | /* otherwise unusable cpu locations */ | ||
| 303 | PPC_CPU Cpus[MAX_CPUS]; | ||
| 304 | /* Memory */ | ||
| 305 | unsigned long TotalMemory; /* Total amount of memory installed */ | ||
| 306 | unsigned long GoodMemory; /* Total amount of good memory */ | ||
| 307 | unsigned long ActualNumMemSegs; | ||
| 308 | MEM_MAP Segs[MAX_MEM_SEGS]; | ||
| 309 | unsigned long ActualNumMemories; | ||
| 310 | PPC_MEM Memories[MAX_MEMS]; | ||
| 311 | /* Devices */ | ||
| 312 | unsigned long ActualNumDevices; | ||
| 313 | PPC_DEVICE Devices[MAX_DEVICES]; | ||
| 314 | unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; | ||
| 315 | } RESIDUAL; | ||
| 316 | |||
| 317 | |||
| 318 | /* | ||
| 319 | * Forward declaration - we can't include <linux/pci.h> because it | ||
| 320 | * breaks the boot loader | ||
| 321 | */ | ||
| 322 | struct pci_dev; | ||
| 323 | |||
| 324 | extern RESIDUAL *res; | ||
| 325 | extern void print_residual_device_info(void); | ||
| 326 | extern PPC_DEVICE *residual_find_device(unsigned long BusMask, | ||
| 327 | unsigned char * DevID, int BaseType, | ||
| 328 | int SubType, int Interface, int n); | ||
| 329 | extern int residual_pcidev_irq(struct pci_dev *dev); | ||
| 330 | extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi); | ||
| 331 | extern unsigned int residual_isapic_addr(void); | ||
| 332 | extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, | ||
| 333 | int n); | ||
| 334 | extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, | ||
| 335 | unsigned packet_type, | ||
| 336 | int n); | ||
| 337 | extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, | ||
| 338 | unsigned packet_type, | ||
| 339 | int n); | ||
| 340 | |||
| 341 | #ifdef CONFIG_PREP_RESIDUAL | ||
| 342 | #define have_residual_data (res && res->ResidualLength) | ||
| 343 | #else | ||
| 344 | #define have_residual_data 0 | ||
| 345 | #endif | ||
| 346 | |||
| 347 | #endif /* __ASSEMBLY__ */ | ||
| 348 | #endif /* ndef _RESIDUAL_ */ | ||
| 349 | |||
| 350 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/rtc.h b/include/asm-ppc/rtc.h deleted file mode 100644 index 6025b46d0a2a..000000000000 --- a/include/asm-ppc/rtc.h +++ /dev/null | |||
| @@ -1,95 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/rtc.h | ||
| 3 | * | ||
| 4 | * Author: Tom Rini <trini@mvista.com> | ||
| 5 | * | ||
| 6 | * 2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | * | ||
| 11 | * Based on: | ||
| 12 | * include/asm-m68k/rtc.h | ||
| 13 | * | ||
| 14 | * Copyright Richard Zidlicky | ||
| 15 | * implementation details for genrtc/q40rtc driver | ||
| 16 | * | ||
| 17 | * And the old drivers/macintosh/rtc.c which was heavily based on: | ||
| 18 | * Linux/SPARC Real Time Clock Driver | ||
| 19 | * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) | ||
| 20 | * | ||
| 21 | * With additional work by Paul Mackerras and Franz Sirl. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef __ASM_RTC_H__ | ||
| 25 | #define __ASM_RTC_H__ | ||
| 26 | |||
| 27 | #ifdef __KERNEL__ | ||
| 28 | |||
| 29 | #include <linux/rtc.h> | ||
| 30 | |||
| 31 | #include <asm/machdep.h> | ||
| 32 | #include <asm/time.h> | ||
| 33 | |||
| 34 | #define RTC_PIE 0x40 /* periodic interrupt enable */ | ||
| 35 | #define RTC_AIE 0x20 /* alarm interrupt enable */ | ||
| 36 | #define RTC_UIE 0x10 /* update-finished interrupt enable */ | ||
| 37 | |||
| 38 | /* some dummy definitions */ | ||
| 39 | #define RTC_BATT_BAD 0x100 /* battery bad */ | ||
| 40 | #define RTC_SQWE 0x08 /* enable square-wave output */ | ||
| 41 | #define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ | ||
| 42 | #define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ | ||
| 43 | #define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ | ||
| 44 | |||
| 45 | static inline unsigned int get_rtc_time(struct rtc_time *time) | ||
| 46 | { | ||
| 47 | if (ppc_md.get_rtc_time) { | ||
| 48 | unsigned long nowtime; | ||
| 49 | |||
| 50 | nowtime = (ppc_md.get_rtc_time)(); | ||
| 51 | |||
| 52 | to_tm(nowtime, time); | ||
| 53 | |||
| 54 | time->tm_year -= 1900; | ||
| 55 | time->tm_mon -= 1; /* Make sure userland has a 0-based month */ | ||
| 56 | } | ||
| 57 | return RTC_24H; | ||
| 58 | } | ||
| 59 | |||
| 60 | /* Set the current date and time in the real time clock. */ | ||
| 61 | static inline int set_rtc_time(struct rtc_time *time) | ||
| 62 | { | ||
| 63 | if (ppc_md.get_rtc_time) { | ||
| 64 | unsigned long nowtime; | ||
| 65 | |||
| 66 | nowtime = mktime(time->tm_year+1900, time->tm_mon+1, | ||
| 67 | time->tm_mday, time->tm_hour, time->tm_min, | ||
| 68 | time->tm_sec); | ||
| 69 | |||
| 70 | (ppc_md.set_rtc_time)(nowtime); | ||
| 71 | |||
| 72 | return 0; | ||
| 73 | } else | ||
| 74 | return -EINVAL; | ||
| 75 | } | ||
| 76 | |||
| 77 | static inline unsigned int get_rtc_ss(void) | ||
| 78 | { | ||
| 79 | struct rtc_time h; | ||
| 80 | |||
| 81 | get_rtc_time(&h); | ||
| 82 | return h.tm_sec; | ||
| 83 | } | ||
| 84 | |||
| 85 | static inline int get_rtc_pll(struct rtc_pll_info *pll) | ||
| 86 | { | ||
| 87 | return -EINVAL; | ||
| 88 | } | ||
| 89 | static inline int set_rtc_pll(struct rtc_pll_info *pll) | ||
| 90 | { | ||
| 91 | return -EINVAL; | ||
| 92 | } | ||
| 93 | |||
| 94 | #endif /* __KERNEL__ */ | ||
| 95 | #endif /* __ASM_RTC_H__ */ | ||
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h deleted file mode 100644 index d35ed10315b1..000000000000 --- a/include/asm-ppc/serial.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-ppc/serial.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifdef __KERNEL__ | ||
| 6 | #ifndef __ASM_SERIAL_H__ | ||
| 7 | #define __ASM_SERIAL_H__ | ||
| 8 | |||
| 9 | |||
| 10 | #if defined(CONFIG_EV64260) | ||
| 11 | #include <platforms/ev64260.h> | ||
| 12 | #elif defined(CONFIG_CHESTNUT) | ||
| 13 | #include <platforms/chestnut.h> | ||
| 14 | #elif defined(CONFIG_POWERPMC250) | ||
| 15 | #include <platforms/powerpmc250.h> | ||
| 16 | #elif defined(CONFIG_LOPEC) | ||
| 17 | #include <platforms/lopec.h> | ||
| 18 | #elif defined(CONFIG_MVME5100) | ||
| 19 | #include <platforms/mvme5100.h> | ||
| 20 | #elif defined(CONFIG_PAL4) | ||
| 21 | #include <platforms/pal4_serial.h> | ||
| 22 | #elif defined(CONFIG_PRPMC750) | ||
| 23 | #include <platforms/prpmc750.h> | ||
| 24 | #elif defined(CONFIG_PRPMC800) | ||
| 25 | #include <platforms/prpmc800.h> | ||
| 26 | #elif defined(CONFIG_SANDPOINT) | ||
| 27 | #include <platforms/sandpoint.h> | ||
| 28 | #elif defined(CONFIG_SPRUCE) | ||
| 29 | #include <platforms/spruce.h> | ||
| 30 | #elif defined(CONFIG_4xx) | ||
| 31 | #include <asm/ibm4xx.h> | ||
| 32 | #elif defined(CONFIG_RADSTONE_PPC7D) | ||
| 33 | #include <platforms/radstone_ppc7d.h> | ||
| 34 | #else | ||
| 35 | |||
| 36 | /* | ||
| 37 | * XXX Assume it has PC-style ISA serial ports - true for PReP at least. | ||
| 38 | */ | ||
| 39 | #include <asm/pc_serial.h> | ||
| 40 | |||
| 41 | #endif /* !CONFIG_GEMINI and others */ | ||
| 42 | #endif /* __ASM_SERIAL_H__ */ | ||
| 43 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h deleted file mode 100644 index e75791ea33a6..000000000000 --- a/include/asm-ppc/smp.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* smp.h: PPC specific SMP stuff. | ||
| 2 | * | ||
| 3 | * Original was a copy of sparc smp.h. Now heavily modified | ||
| 4 | * for PPC. | ||
| 5 | * | ||
| 6 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | ||
| 7 | * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com> | ||
| 8 | */ | ||
| 9 | #ifdef __KERNEL__ | ||
| 10 | #ifndef _PPC_SMP_H | ||
| 11 | #define _PPC_SMP_H | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/bitops.h> | ||
| 15 | #include <linux/errno.h> | ||
| 16 | #include <linux/cpumask.h> | ||
| 17 | #include <linux/threads.h> | ||
| 18 | |||
| 19 | #ifdef CONFIG_SMP | ||
| 20 | |||
| 21 | #ifndef __ASSEMBLY__ | ||
| 22 | |||
| 23 | struct cpuinfo_PPC { | ||
| 24 | unsigned long loops_per_jiffy; | ||
| 25 | unsigned long pvr; | ||
| 26 | unsigned long *pgd_cache; | ||
| 27 | unsigned long *pte_cache; | ||
| 28 | unsigned long pgtable_cache_sz; | ||
| 29 | }; | ||
| 30 | |||
| 31 | extern struct cpuinfo_PPC cpu_data[]; | ||
| 32 | extern cpumask_t cpu_online_map; | ||
| 33 | extern cpumask_t cpu_possible_map; | ||
| 34 | extern unsigned long smp_proc_in_lock[]; | ||
| 35 | extern volatile unsigned long cpu_callin_map[]; | ||
| 36 | extern int smp_tb_synchronized; | ||
| 37 | extern struct smp_ops_t *smp_ops; | ||
| 38 | |||
| 39 | extern void smp_send_tlb_invalidate(int); | ||
| 40 | extern void smp_send_xmon_break(int cpu); | ||
| 41 | struct pt_regs; | ||
| 42 | extern void smp_message_recv(int); | ||
| 43 | |||
| 44 | extern int __cpu_disable(void); | ||
| 45 | extern void __cpu_die(unsigned int cpu); | ||
| 46 | extern void cpu_die(void) __attribute__((noreturn)); | ||
| 47 | |||
| 48 | #define raw_smp_processor_id() (current_thread_info()->cpu) | ||
| 49 | |||
| 50 | extern int __cpu_up(unsigned int cpu); | ||
| 51 | |||
| 52 | extern int smp_hw_index[]; | ||
| 53 | #define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) | ||
| 54 | #define get_hard_smp_processor_id(cpu) (smp_hw_index[(cpu)]) | ||
| 55 | #define set_hard_smp_processor_id(cpu, phys)\ | ||
| 56 | (smp_hw_index[(cpu)] = (phys)) | ||
| 57 | |||
| 58 | #endif /* __ASSEMBLY__ */ | ||
| 59 | |||
| 60 | #else /* !(CONFIG_SMP) */ | ||
| 61 | |||
| 62 | static inline void cpu_die(void) { } | ||
| 63 | #define get_hard_smp_processor_id(cpu) 0 | ||
| 64 | #define set_hard_smp_processor_id(cpu, phys) | ||
| 65 | #define hard_smp_processor_id() 0 | ||
| 66 | |||
| 67 | #endif /* !(CONFIG_SMP) */ | ||
| 68 | |||
| 69 | #ifndef __ASSEMBLY__ | ||
| 70 | extern int boot_cpuid; | ||
| 71 | extern int boot_cpuid_phys; | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #endif /* !(_PPC_SMP_H) */ | ||
| 75 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h deleted file mode 100644 index fccaf5531e57..000000000000 --- a/include/asm-ppc/spinlock.h +++ /dev/null | |||
| @@ -1,168 +0,0 @@ | |||
| 1 | #ifndef __ASM_SPINLOCK_H | ||
| 2 | #define __ASM_SPINLOCK_H | ||
| 3 | |||
| 4 | #include <asm/system.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Simple spin lock operations. | ||
| 8 | * | ||
| 9 | * (the type definitions are in asm/raw_spinlock_types.h) | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define __raw_spin_is_locked(x) ((x)->slock != 0) | ||
| 13 | #define __raw_spin_unlock_wait(lock) \ | ||
| 14 | do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0) | ||
| 15 | #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) | ||
| 16 | |||
| 17 | static inline void __raw_spin_lock(raw_spinlock_t *lock) | ||
| 18 | { | ||
| 19 | unsigned long tmp; | ||
| 20 | |||
| 21 | __asm__ __volatile__( | ||
| 22 | "b 1f # __raw_spin_lock\n\ | ||
| 23 | 2: lwzx %0,0,%1\n\ | ||
| 24 | cmpwi 0,%0,0\n\ | ||
| 25 | bne+ 2b\n\ | ||
| 26 | 1: lwarx %0,0,%1\n\ | ||
| 27 | cmpwi 0,%0,0\n\ | ||
| 28 | bne- 2b\n" | ||
| 29 | PPC405_ERR77(0,%1) | ||
| 30 | " stwcx. %2,0,%1\n\ | ||
| 31 | bne- 2b\n\ | ||
| 32 | isync" | ||
| 33 | : "=&r"(tmp) | ||
| 34 | : "r"(&lock->slock), "r"(1) | ||
| 35 | : "cr0", "memory"); | ||
| 36 | } | ||
| 37 | |||
| 38 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) | ||
| 39 | { | ||
| 40 | __asm__ __volatile__("eieio # __raw_spin_unlock": : :"memory"); | ||
| 41 | lock->slock = 0; | ||
| 42 | } | ||
| 43 | |||
| 44 | #define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock))) | ||
| 45 | |||
| 46 | /* | ||
| 47 | * Read-write spinlocks, allowing multiple readers | ||
| 48 | * but only one writer. | ||
| 49 | * | ||
| 50 | * NOTE! it is quite common to have readers in interrupts | ||
| 51 | * but no interrupt writers. For those circumstances we | ||
| 52 | * can "mix" irq-safe locks - any writer needs to get a | ||
| 53 | * irq-safe write-lock, but readers can get non-irqsafe | ||
| 54 | * read-locks. | ||
| 55 | */ | ||
| 56 | |||
| 57 | #define __raw_read_can_lock(rw) ((rw)->lock >= 0) | ||
| 58 | #define __raw_write_can_lock(rw) (!(rw)->lock) | ||
| 59 | |||
| 60 | static __inline__ int __raw_read_trylock(raw_rwlock_t *rw) | ||
| 61 | { | ||
| 62 | signed int tmp; | ||
| 63 | |||
| 64 | __asm__ __volatile__( | ||
| 65 | "2: lwarx %0,0,%1 # read_trylock\n\ | ||
| 66 | addic. %0,%0,1\n\ | ||
| 67 | ble- 1f\n" | ||
| 68 | PPC405_ERR77(0,%1) | ||
| 69 | " stwcx. %0,0,%1\n\ | ||
| 70 | bne- 2b\n\ | ||
| 71 | isync\n\ | ||
| 72 | 1:" | ||
| 73 | : "=&r"(tmp) | ||
| 74 | : "r"(&rw->lock) | ||
| 75 | : "cr0", "memory"); | ||
| 76 | |||
| 77 | return tmp > 0; | ||
| 78 | } | ||
| 79 | |||
| 80 | static __inline__ void __raw_read_lock(raw_rwlock_t *rw) | ||
| 81 | { | ||
| 82 | signed int tmp; | ||
| 83 | |||
| 84 | __asm__ __volatile__( | ||
| 85 | "b 2f # read_lock\n\ | ||
| 86 | 1: lwzx %0,0,%1\n\ | ||
| 87 | cmpwi 0,%0,0\n\ | ||
| 88 | blt+ 1b\n\ | ||
| 89 | 2: lwarx %0,0,%1\n\ | ||
| 90 | addic. %0,%0,1\n\ | ||
| 91 | ble- 1b\n" | ||
| 92 | PPC405_ERR77(0,%1) | ||
| 93 | " stwcx. %0,0,%1\n\ | ||
| 94 | bne- 2b\n\ | ||
| 95 | isync" | ||
| 96 | : "=&r"(tmp) | ||
| 97 | : "r"(&rw->lock) | ||
| 98 | : "cr0", "memory"); | ||
| 99 | } | ||
| 100 | |||
| 101 | static __inline__ void __raw_read_unlock(raw_rwlock_t *rw) | ||
| 102 | { | ||
| 103 | signed int tmp; | ||
| 104 | |||
| 105 | __asm__ __volatile__( | ||
| 106 | "eieio # read_unlock\n\ | ||
| 107 | 1: lwarx %0,0,%1\n\ | ||
| 108 | addic %0,%0,-1\n" | ||
| 109 | PPC405_ERR77(0,%1) | ||
| 110 | " stwcx. %0,0,%1\n\ | ||
| 111 | bne- 1b" | ||
| 112 | : "=&r"(tmp) | ||
| 113 | : "r"(&rw->lock) | ||
| 114 | : "cr0", "memory"); | ||
| 115 | } | ||
| 116 | |||
| 117 | static __inline__ int __raw_write_trylock(raw_rwlock_t *rw) | ||
| 118 | { | ||
| 119 | signed int tmp; | ||
| 120 | |||
| 121 | __asm__ __volatile__( | ||
| 122 | "2: lwarx %0,0,%1 # write_trylock\n\ | ||
| 123 | cmpwi 0,%0,0\n\ | ||
| 124 | bne- 1f\n" | ||
| 125 | PPC405_ERR77(0,%1) | ||
| 126 | " stwcx. %2,0,%1\n\ | ||
| 127 | bne- 2b\n\ | ||
| 128 | isync\n\ | ||
| 129 | 1:" | ||
| 130 | : "=&r"(tmp) | ||
| 131 | : "r"(&rw->lock), "r"(-1) | ||
| 132 | : "cr0", "memory"); | ||
| 133 | |||
| 134 | return tmp == 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | static __inline__ void __raw_write_lock(raw_rwlock_t *rw) | ||
| 138 | { | ||
| 139 | signed int tmp; | ||
| 140 | |||
| 141 | __asm__ __volatile__( | ||
| 142 | "b 2f # write_lock\n\ | ||
| 143 | 1: lwzx %0,0,%1\n\ | ||
| 144 | cmpwi 0,%0,0\n\ | ||
| 145 | bne+ 1b\n\ | ||
| 146 | 2: lwarx %0,0,%1\n\ | ||
| 147 | cmpwi 0,%0,0\n\ | ||
| 148 | bne- 1b\n" | ||
| 149 | PPC405_ERR77(0,%1) | ||
| 150 | " stwcx. %2,0,%1\n\ | ||
| 151 | bne- 2b\n\ | ||
| 152 | isync" | ||
| 153 | : "=&r"(tmp) | ||
| 154 | : "r"(&rw->lock), "r"(-1) | ||
| 155 | : "cr0", "memory"); | ||
| 156 | } | ||
| 157 | |||
| 158 | static __inline__ void __raw_write_unlock(raw_rwlock_t *rw) | ||
| 159 | { | ||
| 160 | __asm__ __volatile__("eieio # write_unlock": : :"memory"); | ||
| 161 | rw->lock = 0; | ||
| 162 | } | ||
| 163 | |||
| 164 | #define _raw_spin_relax(lock) cpu_relax() | ||
| 165 | #define _raw_read_relax(lock) cpu_relax() | ||
| 166 | #define _raw_write_relax(lock) cpu_relax() | ||
| 167 | |||
| 168 | #endif /* __ASM_SPINLOCK_H */ | ||
diff --git a/include/asm-ppc/suspend.h b/include/asm-ppc/suspend.h deleted file mode 100644 index 3df9f32bd834..000000000000 --- a/include/asm-ppc/suspend.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | static inline int arch_prepare_suspend(void) | ||
| 2 | { | ||
| 3 | return 0; | ||
| 4 | } | ||
| 5 | |||
| 6 | static inline void save_processor_state(void) | ||
| 7 | { | ||
| 8 | } | ||
| 9 | |||
| 10 | static inline void restore_processor_state(void) | ||
| 11 | { | ||
| 12 | } | ||
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h deleted file mode 100644 index 70ebd333c55b..000000000000 --- a/include/asm-ppc/system.h +++ /dev/null | |||
| @@ -1,289 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | ||
| 3 | */ | ||
| 4 | #ifndef __PPC_SYSTEM_H | ||
| 5 | #define __PPC_SYSTEM_H | ||
| 6 | |||
| 7 | #include <linux/kernel.h> | ||
| 8 | |||
| 9 | #include <asm/hw_irq.h> | ||
| 10 | |||
| 11 | /* | ||
| 12 | * Memory barrier. | ||
| 13 | * The sync instruction guarantees that all memory accesses initiated | ||
| 14 | * by this processor have been performed (with respect to all other | ||
| 15 | * mechanisms that access memory). The eieio instruction is a barrier | ||
| 16 | * providing an ordering (separately) for (a) cacheable stores and (b) | ||
| 17 | * loads and stores to non-cacheable memory (e.g. I/O devices). | ||
| 18 | * | ||
| 19 | * mb() prevents loads and stores being reordered across this point. | ||
| 20 | * rmb() prevents loads being reordered across this point. | ||
| 21 | * wmb() prevents stores being reordered across this point. | ||
| 22 | * read_barrier_depends() prevents data-dependent loads being reordered | ||
| 23 | * across this point (nop on PPC). | ||
| 24 | * | ||
| 25 | * We can use the eieio instruction for wmb, but since it doesn't | ||
| 26 | * give any ordering guarantees about loads, we have to use the | ||
| 27 | * stronger but slower sync instruction for mb and rmb. | ||
| 28 | */ | ||
| 29 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | ||
| 30 | #define rmb() __asm__ __volatile__ ("sync" : : : "memory") | ||
| 31 | #define wmb() __asm__ __volatile__ ("eieio" : : : "memory") | ||
| 32 | #define read_barrier_depends() do { } while(0) | ||
| 33 | |||
| 34 | #define set_mb(var, value) do { var = value; mb(); } while (0) | ||
| 35 | |||
| 36 | #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */ | ||
| 37 | #ifdef CONFIG_SMP | ||
| 38 | #define smp_mb() mb() | ||
| 39 | #define smp_rmb() rmb() | ||
| 40 | #define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") | ||
| 41 | #define smp_read_barrier_depends() read_barrier_depends() | ||
| 42 | #else | ||
| 43 | #define smp_mb() barrier() | ||
| 44 | #define smp_rmb() barrier() | ||
| 45 | #define smp_wmb() barrier() | ||
| 46 | #define smp_read_barrier_depends() do { } while(0) | ||
| 47 | #endif /* CONFIG_SMP */ | ||
| 48 | |||
| 49 | #ifdef __KERNEL__ | ||
| 50 | struct task_struct; | ||
| 51 | struct pt_regs; | ||
| 52 | |||
| 53 | extern void print_backtrace(unsigned long *); | ||
| 54 | extern void show_regs(struct pt_regs * regs); | ||
| 55 | extern void flush_instruction_cache(void); | ||
| 56 | extern void hard_reset_now(void); | ||
| 57 | extern void poweroff_now(void); | ||
| 58 | extern int set_dabr(unsigned long dabr); | ||
| 59 | #ifdef CONFIG_6xx | ||
| 60 | extern long _get_L2CR(void); | ||
| 61 | extern long _get_L3CR(void); | ||
| 62 | extern void _set_L2CR(unsigned long); | ||
| 63 | extern void _set_L3CR(unsigned long); | ||
| 64 | #else | ||
| 65 | #define _get_L2CR() 0L | ||
| 66 | #define _get_L3CR() 0L | ||
| 67 | #define _set_L2CR(val) do { } while(0) | ||
| 68 | #define _set_L3CR(val) do { } while(0) | ||
| 69 | #endif | ||
| 70 | extern void via_cuda_init(void); | ||
| 71 | extern void pmac_nvram_init(void); | ||
| 72 | extern void chrp_nvram_init(void); | ||
| 73 | extern void read_rtc_time(void); | ||
| 74 | extern void pmac_find_display(void); | ||
| 75 | extern void giveup_fpu(struct task_struct *); | ||
| 76 | extern void disable_kernel_fp(void); | ||
| 77 | extern void enable_kernel_fp(void); | ||
| 78 | extern void flush_fp_to_thread(struct task_struct *); | ||
| 79 | extern void enable_kernel_altivec(void); | ||
| 80 | extern void giveup_altivec(struct task_struct *); | ||
| 81 | extern void load_up_altivec(struct task_struct *); | ||
| 82 | extern int emulate_altivec(struct pt_regs *); | ||
| 83 | extern void giveup_spe(struct task_struct *); | ||
| 84 | extern void load_up_spe(struct task_struct *); | ||
| 85 | extern int fix_alignment(struct pt_regs *); | ||
| 86 | extern void cvt_fd(float *from, double *to, struct thread_struct *thread); | ||
| 87 | extern void cvt_df(double *from, float *to, struct thread_struct *thread); | ||
| 88 | |||
| 89 | #ifndef CONFIG_SMP | ||
| 90 | extern void discard_lazy_cpu_state(void); | ||
| 91 | #else | ||
| 92 | static inline void discard_lazy_cpu_state(void) | ||
| 93 | { | ||
| 94 | } | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #ifdef CONFIG_ALTIVEC | ||
| 98 | extern void flush_altivec_to_thread(struct task_struct *); | ||
| 99 | #else | ||
| 100 | static inline void flush_altivec_to_thread(struct task_struct *t) | ||
| 101 | { | ||
| 102 | } | ||
| 103 | #endif | ||
| 104 | |||
| 105 | #ifdef CONFIG_SPE | ||
| 106 | extern void flush_spe_to_thread(struct task_struct *); | ||
| 107 | #else | ||
| 108 | static inline void flush_spe_to_thread(struct task_struct *t) | ||
| 109 | { | ||
| 110 | } | ||
| 111 | #endif | ||
| 112 | |||
| 113 | extern int call_rtas(const char *, int, int, unsigned long *, ...); | ||
| 114 | extern void cacheable_memzero(void *p, unsigned int nb); | ||
| 115 | extern void *cacheable_memcpy(void *, const void *, unsigned int); | ||
| 116 | extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); | ||
| 117 | extern void bad_page_fault(struct pt_regs *, unsigned long, int); | ||
| 118 | extern int die(const char *, struct pt_regs *, long); | ||
| 119 | extern void _exception(int, struct pt_regs *, int, unsigned long); | ||
| 120 | void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); | ||
| 121 | |||
| 122 | #ifdef CONFIG_BOOKE_WDT | ||
| 123 | extern u32 booke_wdt_enabled; | ||
| 124 | extern u32 booke_wdt_period; | ||
| 125 | #endif /* CONFIG_BOOKE_WDT */ | ||
| 126 | |||
| 127 | struct device_node; | ||
| 128 | extern void note_scsi_host(struct device_node *, void *); | ||
| 129 | |||
| 130 | extern struct task_struct *__switch_to(struct task_struct *, | ||
| 131 | struct task_struct *); | ||
| 132 | #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) | ||
| 133 | |||
| 134 | struct thread_struct; | ||
| 135 | extern struct task_struct *_switch(struct thread_struct *prev, | ||
| 136 | struct thread_struct *next); | ||
| 137 | |||
| 138 | extern unsigned int rtas_data; | ||
| 139 | |||
| 140 | static __inline__ unsigned long | ||
| 141 | xchg_u32(volatile void *p, unsigned long val) | ||
| 142 | { | ||
| 143 | unsigned long prev; | ||
| 144 | |||
| 145 | __asm__ __volatile__ ("\n\ | ||
| 146 | 1: lwarx %0,0,%2 \n" | ||
| 147 | PPC405_ERR77(0,%2) | ||
| 148 | " stwcx. %3,0,%2 \n\ | ||
| 149 | bne- 1b" | ||
| 150 | : "=&r" (prev), "=m" (*(volatile unsigned long *)p) | ||
| 151 | : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) | ||
| 152 | : "cc", "memory"); | ||
| 153 | |||
| 154 | return prev; | ||
| 155 | } | ||
| 156 | |||
| 157 | /* | ||
| 158 | * This function doesn't exist, so you'll get a linker error | ||
| 159 | * if something tries to do an invalid xchg(). | ||
| 160 | */ | ||
| 161 | extern void __xchg_called_with_bad_pointer(void); | ||
| 162 | |||
| 163 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | ||
| 164 | |||
| 165 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) | ||
| 166 | { | ||
| 167 | switch (size) { | ||
| 168 | case 4: | ||
| 169 | return (unsigned long) xchg_u32(ptr, x); | ||
| 170 | #if 0 /* xchg_u64 doesn't exist on 32-bit PPC */ | ||
| 171 | case 8: | ||
| 172 | return (unsigned long) xchg_u64(ptr, x); | ||
| 173 | #endif /* 0 */ | ||
| 174 | } | ||
| 175 | __xchg_called_with_bad_pointer(); | ||
| 176 | return x; | ||
| 177 | |||
| 178 | |||
| 179 | } | ||
| 180 | |||
| 181 | static inline void * xchg_ptr(void * m, void * val) | ||
| 182 | { | ||
| 183 | return (void *) xchg_u32(m, (unsigned long) val); | ||
| 184 | } | ||
| 185 | |||
| 186 | |||
| 187 | #define __HAVE_ARCH_CMPXCHG 1 | ||
| 188 | |||
| 189 | static __inline__ unsigned long | ||
| 190 | __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) | ||
| 191 | { | ||
| 192 | unsigned int prev; | ||
| 193 | |||
| 194 | __asm__ __volatile__ ("\n\ | ||
| 195 | 1: lwarx %0,0,%2 \n\ | ||
| 196 | cmpw 0,%0,%3 \n\ | ||
| 197 | bne 2f \n" | ||
| 198 | PPC405_ERR77(0,%2) | ||
| 199 | " stwcx. %4,0,%2 \n\ | ||
| 200 | bne- 1b\n" | ||
| 201 | #ifdef CONFIG_SMP | ||
| 202 | " sync\n" | ||
| 203 | #endif /* CONFIG_SMP */ | ||
| 204 | "2:" | ||
| 205 | : "=&r" (prev), "=m" (*p) | ||
| 206 | : "r" (p), "r" (old), "r" (new), "m" (*p) | ||
| 207 | : "cc", "memory"); | ||
| 208 | |||
| 209 | return prev; | ||
| 210 | } | ||
| 211 | |||
| 212 | static inline unsigned long | ||
| 213 | __cmpxchg_u32_local(volatile unsigned int *p, unsigned int old, | ||
| 214 | unsigned int new) | ||
| 215 | { | ||
| 216 | unsigned int prev; | ||
| 217 | |||
| 218 | __asm__ __volatile__ ("\n\ | ||
| 219 | 1: lwarx %0,0,%2 \n\ | ||
| 220 | cmpw 0,%0,%3 \n\ | ||
| 221 | bne 2f \n" | ||
| 222 | PPC405_ERR77(0,%2) | ||
| 223 | " stwcx. %4,0,%2 \n\ | ||
| 224 | bne- 1b\n" | ||
| 225 | "2:" | ||
| 226 | : "=&r" (prev), "=m" (*p) | ||
| 227 | : "r" (p), "r" (old), "r" (new), "m" (*p) | ||
| 228 | : "cc", "memory"); | ||
| 229 | |||
| 230 | return prev; | ||
| 231 | } | ||
| 232 | |||
| 233 | /* This function doesn't exist, so you'll get a linker error | ||
| 234 | if something tries to do an invalid cmpxchg(). */ | ||
| 235 | extern void __cmpxchg_called_with_bad_pointer(void); | ||
| 236 | |||
| 237 | static __inline__ unsigned long | ||
| 238 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, | ||
| 239 | unsigned int size) | ||
| 240 | { | ||
| 241 | switch (size) { | ||
| 242 | case 4: | ||
| 243 | return __cmpxchg_u32(ptr, old, new); | ||
| 244 | #if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */ | ||
| 245 | case 8: | ||
| 246 | return __cmpxchg_u64(ptr, old, new); | ||
| 247 | #endif /* 0 */ | ||
| 248 | } | ||
| 249 | __cmpxchg_called_with_bad_pointer(); | ||
| 250 | return old; | ||
| 251 | } | ||
| 252 | |||
| 253 | #define cmpxchg(ptr, o, n) \ | ||
| 254 | ({ \ | ||
| 255 | __typeof__(*(ptr)) _o_ = (o); \ | ||
| 256 | __typeof__(*(ptr)) _n_ = (n); \ | ||
| 257 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | ||
| 258 | (unsigned long)_n_, sizeof(*(ptr))); \ | ||
| 259 | }) | ||
| 260 | |||
| 261 | #include <asm-generic/cmpxchg-local.h> | ||
| 262 | |||
| 263 | static inline unsigned long __cmpxchg_local(volatile void *ptr, | ||
| 264 | unsigned long old, | ||
| 265 | unsigned long new, int size) | ||
| 266 | { | ||
| 267 | switch (size) { | ||
| 268 | case 4: | ||
| 269 | return __cmpxchg_u32_local(ptr, old, new); | ||
| 270 | default: | ||
| 271 | return __cmpxchg_local_generic(ptr, old, new, size); | ||
| 272 | } | ||
| 273 | |||
| 274 | return old; | ||
| 275 | } | ||
| 276 | |||
| 277 | /* | ||
| 278 | * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make | ||
| 279 | * them available. | ||
| 280 | */ | ||
| 281 | #define cmpxchg_local(ptr, o, n) \ | ||
| 282 | ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \ | ||
| 283 | (unsigned long)(n), sizeof(*(ptr)))) | ||
| 284 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | ||
| 285 | |||
| 286 | #define arch_align_stack(x) (x) | ||
| 287 | |||
| 288 | #endif /* __KERNEL__ */ | ||
| 289 | #endif /* __PPC_SYSTEM_H */ | ||
diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h deleted file mode 100644 index 81dbcd43a501..000000000000 --- a/include/asm-ppc/time.h +++ /dev/null | |||
| @@ -1,161 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Common time prototypes and such for all ppc machines. | ||
| 3 | * | ||
| 4 | * Written by Cort Dougan (cort@fsmlabs.com) to merge | ||
| 5 | * Paul Mackerras' version and mine for PReP and Pmac. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifdef __KERNEL__ | ||
| 9 | #ifndef __ASM_TIME_H__ | ||
| 10 | #define __ASM_TIME_H__ | ||
| 11 | |||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/rtc.h> | ||
| 14 | #include <linux/threads.h> | ||
| 15 | |||
| 16 | #include <asm/reg.h> | ||
| 17 | |||
| 18 | /* time.c */ | ||
| 19 | extern unsigned tb_ticks_per_jiffy; | ||
| 20 | extern unsigned tb_to_us; | ||
| 21 | extern unsigned tb_last_stamp; | ||
| 22 | extern unsigned long disarm_decr[NR_CPUS]; | ||
| 23 | |||
| 24 | extern void to_tm(int tim, struct rtc_time * tm); | ||
| 25 | extern time_t last_rtc_update; | ||
| 26 | |||
| 27 | extern void set_dec_cpu6(unsigned int val); | ||
| 28 | |||
| 29 | int via_calibrate_decr(void); | ||
| 30 | |||
| 31 | /* Accessor functions for the decrementer register. | ||
| 32 | * The 4xx doesn't even have a decrementer. I tried to use the | ||
| 33 | * generic timer interrupt code, which seems OK, with the 4xx PIT | ||
| 34 | * in auto-reload mode. The problem is PIT stops counting when it | ||
| 35 | * hits zero. If it would wrap, we could use it just like a decrementer. | ||
| 36 | */ | ||
| 37 | static __inline__ unsigned int get_dec(void) | ||
| 38 | { | ||
| 39 | #if defined(CONFIG_40x) | ||
| 40 | return (mfspr(SPRN_PIT)); | ||
| 41 | #else | ||
| 42 | return (mfspr(SPRN_DEC)); | ||
| 43 | #endif | ||
| 44 | } | ||
| 45 | |||
| 46 | static __inline__ void set_dec(unsigned int val) | ||
| 47 | { | ||
| 48 | #if defined(CONFIG_40x) | ||
| 49 | return; /* Have to let it auto-reload */ | ||
| 50 | #elif defined(CONFIG_8xx_CPU6) | ||
| 51 | set_dec_cpu6(val); | ||
| 52 | #else | ||
| 53 | mtspr(SPRN_DEC, val); | ||
| 54 | #endif | ||
| 55 | } | ||
| 56 | |||
| 57 | /* Accessor functions for the timebase (RTC on 601) registers. */ | ||
| 58 | /* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ | ||
| 59 | #ifdef CONFIG_6xx | ||
| 60 | extern __inline__ int __pure __USE_RTC(void) { | ||
| 61 | return (mfspr(SPRN_PVR)>>16) == 1; | ||
| 62 | } | ||
| 63 | #else | ||
| 64 | #define __USE_RTC() 0 | ||
| 65 | #endif | ||
| 66 | |||
| 67 | extern __inline__ unsigned long get_tbl(void) { | ||
| 68 | unsigned long tbl; | ||
| 69 | #if defined(CONFIG_403GCX) | ||
| 70 | asm volatile("mfspr %0, 0x3dd" : "=r" (tbl)); | ||
| 71 | #else | ||
| 72 | asm volatile("mftb %0" : "=r" (tbl)); | ||
| 73 | #endif | ||
| 74 | return tbl; | ||
| 75 | } | ||
| 76 | |||
| 77 | extern __inline__ unsigned long get_tbu(void) { | ||
| 78 | unsigned long tbl; | ||
| 79 | #if defined(CONFIG_403GCX) | ||
| 80 | asm volatile("mfspr %0, 0x3dc" : "=r" (tbl)); | ||
| 81 | #else | ||
| 82 | asm volatile("mftbu %0" : "=r" (tbl)); | ||
| 83 | #endif | ||
| 84 | return tbl; | ||
| 85 | } | ||
| 86 | |||
| 87 | extern __inline__ void set_tb(unsigned int upper, unsigned int lower) | ||
| 88 | { | ||
| 89 | mtspr(SPRN_TBWL, 0); | ||
| 90 | mtspr(SPRN_TBWU, upper); | ||
| 91 | mtspr(SPRN_TBWL, lower); | ||
| 92 | } | ||
| 93 | |||
| 94 | extern __inline__ unsigned long get_rtcl(void) { | ||
| 95 | unsigned long rtcl; | ||
| 96 | asm volatile("mfrtcl %0" : "=r" (rtcl)); | ||
| 97 | return rtcl; | ||
| 98 | } | ||
| 99 | |||
| 100 | extern __inline__ unsigned long get_rtcu(void) | ||
| 101 | { | ||
| 102 | unsigned long rtcu; | ||
| 103 | asm volatile("mfrtcu %0" : "=r" (rtcu)); | ||
| 104 | return rtcu; | ||
| 105 | } | ||
| 106 | |||
| 107 | extern __inline__ unsigned get_native_tbl(void) { | ||
| 108 | if (__USE_RTC()) | ||
| 109 | return get_rtcl(); | ||
| 110 | else | ||
| 111 | return get_tbl(); | ||
| 112 | } | ||
| 113 | |||
| 114 | /* On machines with RTC, this function can only be used safely | ||
| 115 | * after the timestamp and for 1 second. It is only used by gettimeofday | ||
| 116 | * however so it should not matter. | ||
| 117 | */ | ||
| 118 | extern __inline__ unsigned tb_ticks_since(unsigned tstamp) { | ||
| 119 | if (__USE_RTC()) { | ||
| 120 | int delta = get_rtcl() - tstamp; | ||
| 121 | return delta<0 ? delta + 1000000000 : delta; | ||
| 122 | } else { | ||
| 123 | return get_tbl() - tstamp; | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | #if 0 | ||
| 128 | extern __inline__ unsigned long get_bin_rtcl(void) { | ||
| 129 | unsigned long rtcl, rtcu1, rtcu2; | ||
| 130 | asm volatile("\ | ||
| 131 | 1: mfrtcu %0\n\ | ||
| 132 | mfrtcl %1\n\ | ||
| 133 | mfrtcu %2\n\ | ||
| 134 | cmpw %0,%2\n\ | ||
| 135 | bne- 1b\n" | ||
| 136 | : "=r" (rtcu1), "=r" (rtcl), "=r" (rtcu2) | ||
| 137 | : : "cr0"); | ||
| 138 | return rtcu2*1000000000+rtcl; | ||
| 139 | } | ||
| 140 | |||
| 141 | extern __inline__ unsigned binary_tbl(void) { | ||
| 142 | if (__USE_RTC()) | ||
| 143 | return get_bin_rtcl(); | ||
| 144 | else | ||
| 145 | return get_tbl(); | ||
| 146 | } | ||
| 147 | #endif | ||
| 148 | |||
| 149 | /* Use mulhwu to scale processor timebase to timeval */ | ||
| 150 | /* Specifically, this computes (x * y) / 2^32. -- paulus */ | ||
| 151 | #define mulhwu(x,y) \ | ||
| 152 | ({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) | ||
| 153 | |||
| 154 | unsigned mulhwu_scale_factor(unsigned, unsigned); | ||
| 155 | |||
| 156 | #define account_process_vtime(tsk) do { } while (0) | ||
| 157 | #define calculate_steal_time() do { } while (0) | ||
| 158 | #define snapshot_timebases() do { } while (0) | ||
| 159 | |||
| 160 | #endif /* __ASM_TIME_H__ */ | ||
| 161 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h deleted file mode 100644 index 937c7dbe6e5c..000000000000 --- a/include/asm-ppc/todc.h +++ /dev/null | |||
| @@ -1,488 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Definitions for the M48Txx and mc146818 series of Time of day/Real Time | ||
| 3 | * Clock chips. | ||
| 4 | * | ||
| 5 | * Author: Mark A. Greer | ||
| 6 | * mgreer@mvista.com | ||
| 7 | * | ||
| 8 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips. | ||
| 16 | * Purpose is to make one generic file that handles all of these chips instead | ||
| 17 | * of every platform implementing the same code over & over again. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __PPC_KERNEL_TODC_H | ||
| 21 | #define __PPC_KERNEL_TODC_H | ||
| 22 | |||
| 23 | typedef struct { | ||
| 24 | uint rtc_type; /* your particular chip */ | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Following are the addresses of the AS0, AS1, and DATA registers | ||
| 28 | * of these chips. Note that these are board-specific. | ||
| 29 | */ | ||
| 30 | unsigned int nvram_as0; | ||
| 31 | unsigned int nvram_as1; | ||
| 32 | unsigned int nvram_data; | ||
| 33 | |||
| 34 | /* | ||
| 35 | * Define bits to stop external set of regs from changing so | ||
| 36 | * the chip can be read/written reliably. | ||
| 37 | */ | ||
| 38 | unsigned char enable_read; | ||
| 39 | unsigned char enable_write; | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Following is the number of AS0 address bits. This is normally | ||
| 43 | * 8 but some bad hardware routes address lines incorrectly. | ||
| 44 | */ | ||
| 45 | int as0_bits; | ||
| 46 | |||
| 47 | int nvram_size; /* Size of NVRAM on chip */ | ||
| 48 | int sw_flags; /* Software control flags */ | ||
| 49 | |||
| 50 | /* Following are the register offsets for the particular chip */ | ||
| 51 | int year; | ||
| 52 | int month; | ||
| 53 | int day_of_month; | ||
| 54 | int day_of_week; | ||
| 55 | int hours; | ||
| 56 | int minutes; | ||
| 57 | int seconds; | ||
| 58 | int control_b; | ||
| 59 | int control_a; | ||
| 60 | int watchdog; | ||
| 61 | int interrupts; | ||
| 62 | int alarm_date; | ||
| 63 | int alarm_hour; | ||
| 64 | int alarm_minutes; | ||
| 65 | int alarm_seconds; | ||
| 66 | int century; | ||
| 67 | int flags; | ||
| 68 | |||
| 69 | /* | ||
| 70 | * Some RTC chips have their NVRAM buried behind a addr/data pair of | ||
| 71 | * regs on the first level/clock registers. The following fields | ||
| 72 | * are the addresses for those addr/data regs. | ||
| 73 | */ | ||
| 74 | int nvram_addr_reg; | ||
| 75 | int nvram_data_reg; | ||
| 76 | } todc_info_t; | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Define the types of TODC/RTC variants that are supported in | ||
| 80 | * arch/ppc/kernel/todc_time.c | ||
| 81 | * Make a new one of these for any chip somehow differs from what's already | ||
| 82 | * defined. That way, if you ever need to put in code to touch those | ||
| 83 | * bits/registers in todc_time.c, you can put it inside an | ||
| 84 | * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break | ||
| 85 | * anyone else. | ||
| 86 | */ | ||
| 87 | #define TODC_TYPE_MK48T35 1 | ||
| 88 | #define TODC_TYPE_MK48T37 2 | ||
| 89 | #define TODC_TYPE_MK48T59 3 | ||
| 90 | #define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */ | ||
| 91 | #define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */ | ||
| 92 | #define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */ | ||
| 93 | #define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */ | ||
| 94 | #define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */ | ||
| 95 | #define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */ | ||
| 96 | #define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */ | ||
| 97 | #define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */ | ||
| 98 | #define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */ | ||
| 99 | #define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */ | ||
| 100 | #define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */ | ||
| 101 | |||
| 102 | /* | ||
| 103 | * Bit to clear/set to enable reads/writes to the chip | ||
| 104 | */ | ||
| 105 | #define TODC_MK48TXX_CNTL_A_R 0x40 | ||
| 106 | #define TODC_MK48TXX_CNTL_A_W 0x80 | ||
| 107 | #define TODC_MK48TXX_DAY_CB 0x80 | ||
| 108 | |||
| 109 | #define TODC_DS1501_CNTL_B_TE 0x80 | ||
| 110 | |||
| 111 | /* | ||
| 112 | * Define flag bits used by todc routines. | ||
| 113 | */ | ||
| 114 | #define TODC_FLAG_2_LEVEL_NVRAM 0x00000001 | ||
| 115 | |||
| 116 | /* | ||
| 117 | * Define the values for the various RTC's that should to into the todc_info | ||
| 118 | * table. | ||
| 119 | * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only | ||
| 120 | * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set. | ||
| 121 | */ | ||
| 122 | #define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8 | ||
| 123 | #define TODC_TYPE_MK48T35_SW_FLAGS 0 | ||
| 124 | #define TODC_TYPE_MK48T35_YEAR 0x7fff | ||
| 125 | #define TODC_TYPE_MK48T35_MONTH 0x7ffe | ||
| 126 | #define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */ | ||
| 127 | #define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */ | ||
| 128 | #define TODC_TYPE_MK48T35_HOURS 0x7ffb | ||
| 129 | #define TODC_TYPE_MK48T35_MINUTES 0x7ffa | ||
| 130 | #define TODC_TYPE_MK48T35_SECONDS 0x7ff9 | ||
| 131 | #define TODC_TYPE_MK48T35_CNTL_B 0x7ff9 | ||
| 132 | #define TODC_TYPE_MK48T35_CNTL_A 0x7ff8 | ||
| 133 | #define TODC_TYPE_MK48T35_WATCHDOG 0x0000 | ||
| 134 | #define TODC_TYPE_MK48T35_INTERRUPTS 0x0000 | ||
| 135 | #define TODC_TYPE_MK48T35_ALARM_DATE 0x0000 | ||
| 136 | #define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000 | ||
| 137 | #define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000 | ||
| 138 | #define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000 | ||
| 139 | #define TODC_TYPE_MK48T35_CENTURY 0x0000 | ||
| 140 | #define TODC_TYPE_MK48T35_FLAGS 0x0000 | ||
| 141 | #define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0 | ||
| 142 | #define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0 | ||
| 143 | |||
| 144 | #define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0 | ||
| 145 | #define TODC_TYPE_MK48T37_SW_FLAGS 0 | ||
| 146 | #define TODC_TYPE_MK48T37_YEAR 0x7fff | ||
| 147 | #define TODC_TYPE_MK48T37_MONTH 0x7ffe | ||
| 148 | #define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */ | ||
| 149 | #define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */ | ||
| 150 | #define TODC_TYPE_MK48T37_HOURS 0x7ffb | ||
| 151 | #define TODC_TYPE_MK48T37_MINUTES 0x7ffa | ||
| 152 | #define TODC_TYPE_MK48T37_SECONDS 0x7ff9 | ||
| 153 | #define TODC_TYPE_MK48T37_CNTL_B 0x7ff9 | ||
| 154 | #define TODC_TYPE_MK48T37_CNTL_A 0x7ff8 | ||
| 155 | #define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7 | ||
| 156 | #define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6 | ||
| 157 | #define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5 | ||
| 158 | #define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4 | ||
| 159 | #define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3 | ||
| 160 | #define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2 | ||
| 161 | #define TODC_TYPE_MK48T37_CENTURY 0x7ff1 | ||
| 162 | #define TODC_TYPE_MK48T37_FLAGS 0x7ff0 | ||
| 163 | #define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0 | ||
| 164 | #define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0 | ||
| 165 | |||
| 166 | #define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0 | ||
| 167 | #define TODC_TYPE_MK48T59_SW_FLAGS 0 | ||
| 168 | #define TODC_TYPE_MK48T59_YEAR 0x1fff | ||
| 169 | #define TODC_TYPE_MK48T59_MONTH 0x1ffe | ||
| 170 | #define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */ | ||
| 171 | #define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */ | ||
| 172 | #define TODC_TYPE_MK48T59_HOURS 0x1ffb | ||
| 173 | #define TODC_TYPE_MK48T59_MINUTES 0x1ffa | ||
| 174 | #define TODC_TYPE_MK48T59_SECONDS 0x1ff9 | ||
| 175 | #define TODC_TYPE_MK48T59_CNTL_B 0x1ff9 | ||
| 176 | #define TODC_TYPE_MK48T59_CNTL_A 0x1ff8 | ||
| 177 | #define TODC_TYPE_MK48T59_WATCHDOG 0x1fff | ||
| 178 | #define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff | ||
| 179 | #define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff | ||
| 180 | #define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff | ||
| 181 | #define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff | ||
| 182 | #define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff | ||
| 183 | #define TODC_TYPE_MK48T59_CENTURY 0x1fff | ||
| 184 | #define TODC_TYPE_MK48T59_FLAGS 0x1fff | ||
| 185 | #define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0 | ||
| 186 | #define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0 | ||
| 187 | |||
| 188 | #define TODC_TYPE_DS1501_NVRAM_SIZE 0x100 | ||
| 189 | #define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM | ||
| 190 | #define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06) | ||
| 191 | #define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05) | ||
| 192 | #define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04) | ||
| 193 | #define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03) | ||
| 194 | #define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02) | ||
| 195 | #define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01) | ||
| 196 | #define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00) | ||
| 197 | #define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f) | ||
| 198 | #define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f) | ||
| 199 | #define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) | ||
| 200 | #define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) | ||
| 201 | #define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b) | ||
| 202 | #define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a) | ||
| 203 | #define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09) | ||
| 204 | #define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08) | ||
| 205 | #define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07) | ||
| 206 | #define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) | ||
| 207 | #define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10 | ||
| 208 | #define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13 | ||
| 209 | |||
| 210 | #define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0 | ||
| 211 | #define TODC_TYPE_DS1553_SW_FLAGS 0 | ||
| 212 | #define TODC_TYPE_DS1553_YEAR 0x1fff | ||
| 213 | #define TODC_TYPE_DS1553_MONTH 0x1ffe | ||
| 214 | #define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */ | ||
| 215 | #define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */ | ||
| 216 | #define TODC_TYPE_DS1553_HOURS 0x1ffb | ||
| 217 | #define TODC_TYPE_DS1553_MINUTES 0x1ffa | ||
| 218 | #define TODC_TYPE_DS1553_SECONDS 0x1ff9 | ||
| 219 | #define TODC_TYPE_DS1553_CNTL_B 0x1ff9 | ||
| 220 | #define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */ | ||
| 221 | #define TODC_TYPE_DS1553_WATCHDOG 0x1ff7 | ||
| 222 | #define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6 | ||
| 223 | #define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5 | ||
| 224 | #define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4 | ||
| 225 | #define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3 | ||
| 226 | #define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2 | ||
| 227 | #define TODC_TYPE_DS1553_CENTURY 0x1ff8 | ||
| 228 | #define TODC_TYPE_DS1553_FLAGS 0x1ff0 | ||
| 229 | #define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0 | ||
| 230 | #define TODC_TYPE_DS1553_NVRAM_DATA_REG 0 | ||
| 231 | |||
| 232 | #define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0 | ||
| 233 | #define TODC_TYPE_DS1557_SW_FLAGS 0 | ||
| 234 | #define TODC_TYPE_DS1557_YEAR 0x7ffff | ||
| 235 | #define TODC_TYPE_DS1557_MONTH 0x7fffe | ||
| 236 | #define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */ | ||
| 237 | #define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */ | ||
| 238 | #define TODC_TYPE_DS1557_HOURS 0x7fffb | ||
| 239 | #define TODC_TYPE_DS1557_MINUTES 0x7fffa | ||
| 240 | #define TODC_TYPE_DS1557_SECONDS 0x7fff9 | ||
| 241 | #define TODC_TYPE_DS1557_CNTL_B 0x7fff9 | ||
| 242 | #define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */ | ||
| 243 | #define TODC_TYPE_DS1557_WATCHDOG 0x7fff7 | ||
| 244 | #define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6 | ||
| 245 | #define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5 | ||
| 246 | #define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4 | ||
| 247 | #define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3 | ||
| 248 | #define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2 | ||
| 249 | #define TODC_TYPE_DS1557_CENTURY 0x7fff8 | ||
| 250 | #define TODC_TYPE_DS1557_FLAGS 0x7fff0 | ||
| 251 | #define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0 | ||
| 252 | #define TODC_TYPE_DS1557_NVRAM_DATA_REG 0 | ||
| 253 | |||
| 254 | #define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8 | ||
| 255 | #define TODC_TYPE_DS1643_SW_FLAGS 0 | ||
| 256 | #define TODC_TYPE_DS1643_YEAR 0x1fff | ||
| 257 | #define TODC_TYPE_DS1643_MONTH 0x1ffe | ||
| 258 | #define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */ | ||
| 259 | #define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */ | ||
| 260 | #define TODC_TYPE_DS1643_HOURS 0x1ffb | ||
| 261 | #define TODC_TYPE_DS1643_MINUTES 0x1ffa | ||
| 262 | #define TODC_TYPE_DS1643_SECONDS 0x1ff9 | ||
| 263 | #define TODC_TYPE_DS1643_CNTL_B 0x1ff9 | ||
| 264 | #define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */ | ||
| 265 | #define TODC_TYPE_DS1643_WATCHDOG 0x1fff | ||
| 266 | #define TODC_TYPE_DS1643_INTERRUPTS 0x1fff | ||
| 267 | #define TODC_TYPE_DS1643_ALARM_DATE 0x1fff | ||
| 268 | #define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff | ||
| 269 | #define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff | ||
| 270 | #define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff | ||
| 271 | #define TODC_TYPE_DS1643_CENTURY 0x1ff8 | ||
| 272 | #define TODC_TYPE_DS1643_FLAGS 0x1fff | ||
| 273 | #define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0 | ||
| 274 | #define TODC_TYPE_DS1643_NVRAM_DATA_REG 0 | ||
| 275 | |||
| 276 | #define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */ | ||
| 277 | #define TODC_TYPE_DS1693_SW_FLAGS 0 | ||
| 278 | #define TODC_TYPE_DS1693_YEAR 0x09 | ||
| 279 | #define TODC_TYPE_DS1693_MONTH 0x08 | ||
| 280 | #define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */ | ||
| 281 | #define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */ | ||
| 282 | #define TODC_TYPE_DS1693_HOURS 0x04 | ||
| 283 | #define TODC_TYPE_DS1693_MINUTES 0x02 | ||
| 284 | #define TODC_TYPE_DS1693_SECONDS 0x00 | ||
| 285 | #define TODC_TYPE_DS1693_CNTL_B 0x0b | ||
| 286 | #define TODC_TYPE_DS1693_CNTL_A 0x0a | ||
| 287 | #define TODC_TYPE_DS1693_WATCHDOG 0xff | ||
| 288 | #define TODC_TYPE_DS1693_INTERRUPTS 0xff | ||
| 289 | #define TODC_TYPE_DS1693_ALARM_DATE 0x49 | ||
| 290 | #define TODC_TYPE_DS1693_ALARM_HOUR 0x05 | ||
| 291 | #define TODC_TYPE_DS1693_ALARM_MINUTES 0x03 | ||
| 292 | #define TODC_TYPE_DS1693_ALARM_SECONDS 0x01 | ||
| 293 | #define TODC_TYPE_DS1693_CENTURY 0x48 | ||
| 294 | #define TODC_TYPE_DS1693_FLAGS 0xff | ||
| 295 | #define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0 | ||
| 296 | #define TODC_TYPE_DS1693_NVRAM_DATA_REG 0 | ||
| 297 | |||
| 298 | #define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8 | ||
| 299 | #define TODC_TYPE_DS1743_SW_FLAGS 0 | ||
| 300 | #define TODC_TYPE_DS1743_YEAR 0x1fff | ||
| 301 | #define TODC_TYPE_DS1743_MONTH 0x1ffe | ||
| 302 | #define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */ | ||
| 303 | #define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */ | ||
| 304 | #define TODC_TYPE_DS1743_HOURS 0x1ffb | ||
| 305 | #define TODC_TYPE_DS1743_MINUTES 0x1ffa | ||
| 306 | #define TODC_TYPE_DS1743_SECONDS 0x1ff9 | ||
| 307 | #define TODC_TYPE_DS1743_CNTL_B 0x1ff9 | ||
| 308 | #define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */ | ||
| 309 | #define TODC_TYPE_DS1743_WATCHDOG 0x1fff | ||
| 310 | #define TODC_TYPE_DS1743_INTERRUPTS 0x1fff | ||
| 311 | #define TODC_TYPE_DS1743_ALARM_DATE 0x1fff | ||
| 312 | #define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff | ||
| 313 | #define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff | ||
| 314 | #define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff | ||
| 315 | #define TODC_TYPE_DS1743_CENTURY 0x1ff8 | ||
| 316 | #define TODC_TYPE_DS1743_FLAGS 0x1fff | ||
| 317 | #define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0 | ||
| 318 | #define TODC_TYPE_DS1743_NVRAM_DATA_REG 0 | ||
| 319 | |||
| 320 | #define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8 | ||
| 321 | #define TODC_TYPE_DS1746_SW_FLAGS 0 | ||
| 322 | #define TODC_TYPE_DS1746_YEAR 0x1ffff | ||
| 323 | #define TODC_TYPE_DS1746_MONTH 0x1fffe | ||
| 324 | #define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */ | ||
| 325 | #define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */ | ||
| 326 | #define TODC_TYPE_DS1746_HOURS 0x1fffb | ||
| 327 | #define TODC_TYPE_DS1746_MINUTES 0x1fffa | ||
| 328 | #define TODC_TYPE_DS1746_SECONDS 0x1fff9 | ||
| 329 | #define TODC_TYPE_DS1746_CNTL_B 0x1fff9 | ||
| 330 | #define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */ | ||
| 331 | #define TODC_TYPE_DS1746_WATCHDOG 0x00000 | ||
| 332 | #define TODC_TYPE_DS1746_INTERRUPTS 0x00000 | ||
| 333 | #define TODC_TYPE_DS1746_ALARM_DATE 0x00000 | ||
| 334 | #define TODC_TYPE_DS1746_ALARM_HOUR 0x00000 | ||
| 335 | #define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000 | ||
| 336 | #define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000 | ||
| 337 | #define TODC_TYPE_DS1746_CENTURY 0x00000 | ||
| 338 | #define TODC_TYPE_DS1746_FLAGS 0x00000 | ||
| 339 | #define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0 | ||
| 340 | #define TODC_TYPE_DS1746_NVRAM_DATA_REG 0 | ||
| 341 | |||
| 342 | #define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8 | ||
| 343 | #define TODC_TYPE_DS1747_SW_FLAGS 0 | ||
| 344 | #define TODC_TYPE_DS1747_YEAR 0x7ffff | ||
| 345 | #define TODC_TYPE_DS1747_MONTH 0x7fffe | ||
| 346 | #define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */ | ||
| 347 | #define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */ | ||
| 348 | #define TODC_TYPE_DS1747_HOURS 0x7fffb | ||
| 349 | #define TODC_TYPE_DS1747_MINUTES 0x7fffa | ||
| 350 | #define TODC_TYPE_DS1747_SECONDS 0x7fff9 | ||
| 351 | #define TODC_TYPE_DS1747_CNTL_B 0x7fff9 | ||
| 352 | #define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */ | ||
| 353 | #define TODC_TYPE_DS1747_WATCHDOG 0x00000 | ||
| 354 | #define TODC_TYPE_DS1747_INTERRUPTS 0x00000 | ||
| 355 | #define TODC_TYPE_DS1747_ALARM_DATE 0x00000 | ||
| 356 | #define TODC_TYPE_DS1747_ALARM_HOUR 0x00000 | ||
| 357 | #define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000 | ||
| 358 | #define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000 | ||
| 359 | #define TODC_TYPE_DS1747_CENTURY 0x00000 | ||
| 360 | #define TODC_TYPE_DS1747_FLAGS 0x00000 | ||
| 361 | #define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0 | ||
| 362 | #define TODC_TYPE_DS1747_NVRAM_DATA_REG 0 | ||
| 363 | |||
| 364 | #define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */ | ||
| 365 | #define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM | ||
| 366 | #define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00) | ||
| 367 | #define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01) | ||
| 368 | #define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02) | ||
| 369 | #define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03) | ||
| 370 | #define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04) | ||
| 371 | #define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05) | ||
| 372 | #define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06) | ||
| 373 | #define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07) | ||
| 374 | #define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08) | ||
| 375 | #define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09) | ||
| 376 | #define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A) | ||
| 377 | #define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B) | ||
| 378 | #define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C) | ||
| 379 | #define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D) | ||
| 380 | #define TODC_TYPE_DS17285_WATCHDOG 0 | ||
| 381 | #define TODC_TYPE_DS17285_INTERRUPTS 0 | ||
| 382 | #define TODC_TYPE_DS17285_ALARM_DATE 0 | ||
| 383 | #define TODC_TYPE_DS17285_CENTURY 0 | ||
| 384 | #define TODC_TYPE_DS17285_FLAGS 0 | ||
| 385 | #define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50 | ||
| 386 | #define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53 | ||
| 387 | |||
| 388 | #define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */ | ||
| 389 | #define TODC_TYPE_MC146818_SW_FLAGS 0 | ||
| 390 | #define TODC_TYPE_MC146818_YEAR 0x09 | ||
| 391 | #define TODC_TYPE_MC146818_MONTH 0x08 | ||
| 392 | #define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */ | ||
| 393 | #define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */ | ||
| 394 | #define TODC_TYPE_MC146818_HOURS 0x04 | ||
| 395 | #define TODC_TYPE_MC146818_MINUTES 0x02 | ||
| 396 | #define TODC_TYPE_MC146818_SECONDS 0x00 | ||
| 397 | #define TODC_TYPE_MC146818_CNTL_B 0x0a | ||
| 398 | #define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */ | ||
| 399 | #define TODC_TYPE_MC146818_WATCHDOG 0 | ||
| 400 | #define TODC_TYPE_MC146818_INTERRUPTS 0x0c | ||
| 401 | #define TODC_TYPE_MC146818_ALARM_DATE 0xff | ||
| 402 | #define TODC_TYPE_MC146818_ALARM_HOUR 0x05 | ||
| 403 | #define TODC_TYPE_MC146818_ALARM_MINUTES 0x03 | ||
| 404 | #define TODC_TYPE_MC146818_ALARM_SECONDS 0x01 | ||
| 405 | #define TODC_TYPE_MC146818_CENTURY 0xff | ||
| 406 | #define TODC_TYPE_MC146818_FLAGS 0xff | ||
| 407 | #define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0 | ||
| 408 | #define TODC_TYPE_MC146818_NVRAM_DATA_REG 0 | ||
| 409 | |||
| 410 | #define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */ | ||
| 411 | #define TODC_TYPE_PC97307_SW_FLAGS 0 | ||
| 412 | #define TODC_TYPE_PC97307_YEAR 0x09 | ||
| 413 | #define TODC_TYPE_PC97307_MONTH 0x08 | ||
| 414 | #define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */ | ||
| 415 | #define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */ | ||
| 416 | #define TODC_TYPE_PC97307_HOURS 0x04 | ||
| 417 | #define TODC_TYPE_PC97307_MINUTES 0x02 | ||
| 418 | #define TODC_TYPE_PC97307_SECONDS 0x00 | ||
| 419 | #define TODC_TYPE_PC97307_CNTL_B 0x0a | ||
| 420 | #define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */ | ||
| 421 | #define TODC_TYPE_PC97307_WATCHDOG 0x0c | ||
| 422 | #define TODC_TYPE_PC97307_INTERRUPTS 0x0d | ||
| 423 | #define TODC_TYPE_PC97307_ALARM_DATE 0xff | ||
| 424 | #define TODC_TYPE_PC97307_ALARM_HOUR 0x05 | ||
| 425 | #define TODC_TYPE_PC97307_ALARM_MINUTES 0x03 | ||
| 426 | #define TODC_TYPE_PC97307_ALARM_SECONDS 0x01 | ||
| 427 | #define TODC_TYPE_PC97307_CENTURY 0xff | ||
| 428 | #define TODC_TYPE_PC97307_FLAGS 0xff | ||
| 429 | #define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0 | ||
| 430 | #define TODC_TYPE_PC97307_NVRAM_DATA_REG 0 | ||
| 431 | |||
| 432 | /* | ||
| 433 | * Define macros to allocate and init the todc_info_t table that will | ||
| 434 | * be used by the todc_time.c routines. | ||
| 435 | */ | ||
| 436 | #define TODC_ALLOC() \ | ||
| 437 | static todc_info_t todc_info_alloc; \ | ||
| 438 | todc_info_t *todc_info = &todc_info_alloc; | ||
| 439 | |||
| 440 | #define TODC_INIT(clock_type, as0, as1, data, bits) { \ | ||
| 441 | todc_info->rtc_type = clock_type; \ | ||
| 442 | \ | ||
| 443 | todc_info->nvram_as0 = (unsigned int)(as0); \ | ||
| 444 | todc_info->nvram_as1 = (unsigned int)(as1); \ | ||
| 445 | todc_info->nvram_data = (unsigned int)(data); \ | ||
| 446 | \ | ||
| 447 | todc_info->as0_bits = (bits); \ | ||
| 448 | \ | ||
| 449 | todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \ | ||
| 450 | todc_info->sw_flags = clock_type ##_SW_FLAGS; \ | ||
| 451 | \ | ||
| 452 | todc_info->year = clock_type ##_YEAR; \ | ||
| 453 | todc_info->month = clock_type ##_MONTH; \ | ||
| 454 | todc_info->day_of_month = clock_type ##_DOM; \ | ||
| 455 | todc_info->day_of_week = clock_type ##_DOW; \ | ||
| 456 | todc_info->hours = clock_type ##_HOURS; \ | ||
| 457 | todc_info->minutes = clock_type ##_MINUTES; \ | ||
| 458 | todc_info->seconds = clock_type ##_SECONDS; \ | ||
| 459 | todc_info->control_b = clock_type ##_CNTL_B; \ | ||
| 460 | todc_info->control_a = clock_type ##_CNTL_A; \ | ||
| 461 | todc_info->watchdog = clock_type ##_WATCHDOG; \ | ||
| 462 | todc_info->interrupts = clock_type ##_INTERRUPTS; \ | ||
| 463 | todc_info->alarm_date = clock_type ##_ALARM_DATE; \ | ||
| 464 | todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \ | ||
| 465 | todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \ | ||
| 466 | todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \ | ||
| 467 | todc_info->century = clock_type ##_CENTURY; \ | ||
| 468 | todc_info->flags = clock_type ##_FLAGS; \ | ||
| 469 | \ | ||
| 470 | todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \ | ||
| 471 | todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \ | ||
| 472 | } | ||
| 473 | |||
| 474 | extern todc_info_t *todc_info; | ||
| 475 | |||
| 476 | unsigned char todc_direct_read_val(int addr); | ||
| 477 | void todc_direct_write_val(int addr, unsigned char val); | ||
| 478 | unsigned char todc_m48txx_read_val(int addr); | ||
| 479 | void todc_m48txx_write_val(int addr, unsigned char val); | ||
| 480 | unsigned char todc_mc146818_read_val(int addr); | ||
| 481 | void todc_mc146818_write_val(int addr, unsigned char val); | ||
| 482 | |||
| 483 | long todc_time_init(void); | ||
| 484 | unsigned long todc_get_rtc_time(void); | ||
| 485 | int todc_set_rtc_time(unsigned long nowtime); | ||
| 486 | void todc_calibrate_decr(void); | ||
| 487 | |||
| 488 | #endif /* __PPC_KERNEL_TODC_H */ | ||
diff --git a/include/asm-ppc/traps.h b/include/asm-ppc/traps.h deleted file mode 100644 index 68e7326b56f1..000000000000 --- a/include/asm-ppc/traps.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | #include <asm-m68k/traps.h> | ||
diff --git a/include/asm-ppc/zorro.h b/include/asm-ppc/zorro.h deleted file mode 100644 index 1e5fbc65e77b..000000000000 --- a/include/asm-ppc/zorro.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | #ifndef _ASM_PPC_ZORRO_H | ||
| 2 | #define _ASM_PPC_ZORRO_H | ||
| 3 | |||
| 4 | #include <asm/io.h> | ||
| 5 | |||
| 6 | #define z_readb in_8 | ||
| 7 | #define z_readw in_be16 | ||
| 8 | #define z_readl in_be32 | ||
| 9 | |||
| 10 | #define z_writeb(val, port) out_8((port), (val)) | ||
| 11 | #define z_writew(val, port) out_be16((port), (val)) | ||
| 12 | #define z_writel(val, port) out_be32((port), (val)) | ||
| 13 | |||
| 14 | #define z_memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
| 15 | #define z_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
| 16 | #define z_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
| 17 | |||
| 18 | extern void *__ioremap(unsigned long address, unsigned long size, | ||
| 19 | unsigned long flags); | ||
| 20 | |||
| 21 | extern void *ioremap(unsigned long address, unsigned long size); | ||
| 22 | extern void iounmap(void *addr); | ||
| 23 | |||
| 24 | extern void *__ioremap(unsigned long address, unsigned long size, | ||
| 25 | unsigned long flags); | ||
| 26 | |||
| 27 | #define z_ioremap ioremap | ||
| 28 | #define z_iounmap iounmap | ||
| 29 | |||
| 30 | #endif /* _ASM_PPC_ZORRO_H */ | ||