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-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200.h118
-rw-r--r--include/asm-arm/arch-at91rm9200/gpio.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/hardware.h37
-rw-r--r--include/asm-arm/arch-at91rm9200/irqs.h2
4 files changed, 83 insertions, 76 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index 58f40931a5c1..a5a86b1ff886 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -19,67 +19,80 @@
19/* 19/*
20 * Peripheral identifiers/interrupts. 20 * Peripheral identifiers/interrupts.
21 */ 21 */
22#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 22#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23#define AT91_ID_SYS 1 /* System Peripheral */ 23#define AT91_ID_SYS 1 /* System Peripheral */
24#define AT91_ID_PIOA 2 /* Parallel IO Controller A */ 24#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
25#define AT91_ID_PIOB 3 /* Parallel IO Controller B */ 25#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
26#define AT91_ID_PIOC 4 /* Parallel IO Controller C */ 26#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
27#define AT91_ID_PIOD 5 /* Parallel IO Controller D */ 27#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
28#define AT91_ID_US0 6 /* USART 0 */ 28#define AT91RM9200_ID_US0 6 /* USART 0 */
29#define AT91_ID_US1 7 /* USART 1 */ 29#define AT91RM9200_ID_US1 7 /* USART 1 */
30#define AT91_ID_US2 8 /* USART 2 */ 30#define AT91RM9200_ID_US2 8 /* USART 2 */
31#define AT91_ID_US3 9 /* USART 3 */ 31#define AT91RM9200_ID_US3 9 /* USART 3 */
32#define AT91_ID_MCI 10 /* Multimedia Card Interface */ 32#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
33#define AT91_ID_UDP 11 /* USB Device Port */ 33#define AT91RM9200_ID_UDP 11 /* USB Device Port */
34#define AT91_ID_TWI 12 /* Two-Wire Interface */ 34#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
35#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ 35#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
36#define AT91_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 36#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
37#define AT91_ID_SSC1 15 /* Serial Synchronous Controller 1 */ 37#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
38#define AT91_ID_SSC2 16 /* Serial Synchronous Controller 2 */ 38#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
39#define AT91_ID_TC0 17 /* Timer Counter 0 */ 39#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
40#define AT91_ID_TC1 18 /* Timer Counter 1 */ 40#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
41#define AT91_ID_TC2 19 /* Timer Counter 2 */ 41#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
42#define AT91_ID_TC3 20 /* Timer Counter 3 */ 42#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
43#define AT91_ID_TC4 21 /* Timer Counter 4 */ 43#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
44#define AT91_ID_TC5 22 /* Timer Counter 5 */ 44#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
45#define AT91_ID_UHP 23 /* USB Host port */ 45#define AT91RM9200_ID_UHP 23 /* USB Host port */
46#define AT91_ID_EMAC 24 /* Ethernet MAC */ 46#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
47#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ 47#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
48#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ 48#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
49#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ 49#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
50#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ 50#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
51#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ 51#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
52#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ 52#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
53#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ 53#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
54 54
55 55
56/* 56/*
57 * Peripheral physical base addresses. 57 * Peripheral physical base addresses.
58 */ 58 */
59#define AT91_BASE_TCB0 0xfffa0000 59#define AT91RM9200_BASE_TCB0 0xfffa0000
60#define AT91_BASE_TC0 0xfffa0000 60#define AT91RM9200_BASE_TC0 0xfffa0000
61#define AT91_BASE_TC1 0xfffa0040 61#define AT91RM9200_BASE_TC1 0xfffa0040
62#define AT91_BASE_TC2 0xfffa0080 62#define AT91RM9200_BASE_TC2 0xfffa0080
63#define AT91_BASE_TCB1 0xfffa4000 63#define AT91RM9200_BASE_TCB1 0xfffa4000
64#define AT91_BASE_TC3 0xfffa4000 64#define AT91RM9200_BASE_TC3 0xfffa4000
65#define AT91_BASE_TC4 0xfffa4040 65#define AT91RM9200_BASE_TC4 0xfffa4040
66#define AT91_BASE_TC5 0xfffa4080 66#define AT91RM9200_BASE_TC5 0xfffa4080
67#define AT91_BASE_UDP 0xfffb0000 67#define AT91RM9200_BASE_UDP 0xfffb0000
68#define AT91_BASE_MCI 0xfffb4000 68#define AT91RM9200_BASE_MCI 0xfffb4000
69#define AT91_BASE_TWI 0xfffb8000 69#define AT91RM9200_BASE_TWI 0xfffb8000
70#define AT91_BASE_EMAC 0xfffbc000 70#define AT91RM9200_BASE_EMAC 0xfffbc000
71#define AT91_BASE_US0 0xfffc0000 71#define AT91RM9200_BASE_US0 0xfffc0000
72#define AT91_BASE_US1 0xfffc4000 72#define AT91RM9200_BASE_US1 0xfffc4000
73#define AT91_BASE_US2 0xfffc8000 73#define AT91RM9200_BASE_US2 0xfffc8000
74#define AT91_BASE_US3 0xfffcc000 74#define AT91RM9200_BASE_US3 0xfffcc000
75#define AT91_BASE_SSC0 0xfffd0000 75#define AT91RM9200_BASE_SSC0 0xfffd0000
76#define AT91_BASE_SSC1 0xfffd4000 76#define AT91RM9200_BASE_SSC1 0xfffd4000
77#define AT91_BASE_SSC2 0xfffd8000 77#define AT91RM9200_BASE_SSC2 0xfffd8000
78#define AT91_BASE_SPI 0xfffe0000 78#define AT91RM9200_BASE_SPI 0xfffe0000
79#define AT91_BASE_SYS 0xfffff000 79#define AT91_BASE_SYS 0xfffff000
80 80
81 81
82/* 82/*
83 * Internal Memory.
84 */
85#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
86#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
87
88#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
89#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
90
91#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
92
93
94#if 0
95/*
83 * PIO pin definitions (peripheral A/B multiplexing). 96 * PIO pin definitions (peripheral A/B multiplexing).
84 */ 97 */
85#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */ 98#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */
@@ -257,5 +270,6 @@
257#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ 270#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
258#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ 271#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
259#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ 272#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
273#endif
260 274
261#endif 275#endif
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
index dbde1baaf251..6243f28a0b81 100644
--- a/include/asm-arm/arch-at91rm9200/gpio.h
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -20,7 +20,7 @@
20#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */ 20#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */
21#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */ 21#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */
22 22
23/* these pin numbers double as IRQ numbers, like AT91_ID_* values */ 23/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
24 24
25#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) 25#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
26#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) 26#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 235d39d91107..878e65f369bf 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -34,27 +34,23 @@
34 * Virtual to Physical Address mapping for IO devices. 34 * Virtual to Physical Address mapping for IO devices.
35 */ 35 */
36#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) 36#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
37#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91_BASE_SPI) 37#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
38#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91_BASE_SSC2) 38#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91RM9200_BASE_SSC2)
39#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91_BASE_SSC1) 39#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91RM9200_BASE_SSC1)
40#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91_BASE_SSC0) 40#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91RM9200_BASE_SSC0)
41#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91_BASE_US3) 41#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91RM9200_BASE_US3)
42#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91_BASE_US2) 42#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91RM9200_BASE_US2)
43#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91_BASE_US1) 43#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91RM9200_BASE_US1)
44#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91_BASE_US0) 44#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91RM9200_BASE_US0)
45#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91_BASE_EMAC) 45#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
46#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91_BASE_TWI) 46#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
47#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91_BASE_MCI) 47#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
48#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91_BASE_UDP) 48#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
49#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91_BASE_TCB1) 49#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91RM9200_BASE_TCB1)
50#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0) 50#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91RM9200_BASE_TCB0)
51
52/* Internal SRAM */
53#define AT91_SRAM_BASE 0x00200000 /* Internal SRAM base address */
54#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */
55 51
56 /* Internal SRAM is mapped below the IO devices */ 52 /* Internal SRAM is mapped below the IO devices */
57#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE) 53#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
58 54
59/* Serial ports */ 55/* Serial ports */
60#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */ 56#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */
@@ -71,9 +67,6 @@
71/* Compact Flash */ 67/* Compact Flash */
72#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */ 68#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
73 69
74/* Multi-Master Memory controller */
75#define AT91_UHP_BASE 0x00300000 /* USB Host controller */
76
77/* Clocks */ 70/* Clocks */
78#define AT91_SLOW_CLOCK 32768 /* slow clock */ 71#define AT91_SLOW_CLOCK 32768 /* slow clock */
79 72
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index f63842c2c093..763cb96c418b 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -32,7 +32,7 @@
32 32
33 33
34/* 34/*
35 * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h 35 * IRQ interrupt symbols are the AT91xxx_ID_* symbols
36 * for IRQs handled directly through the AIC, or else the AT91_PIN_* 36 * for IRQs handled directly through the AIC, or else the AT91_PIN_*
37 * symbols in gpio.h for ones handled indirectly as GPIOs. 37 * symbols in gpio.h for ones handled indirectly as GPIOs.
38 * We make provision for 4 banks of GPIO. 38 * We make provision for 4 banks of GPIO.
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 20:41:15 -0500