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-rw-r--r--include/asm-arm/arch-at91/at91_mci.h2
-rw-r--r--include/asm-arm/arch-at91/at91rm9200.h5
-rw-r--r--include/asm-arm/arch-at91/at91sam9260.h7
-rw-r--r--include/asm-arm/arch-at91/at91sam9261.h4
-rw-r--r--include/asm-arm/arch-at91/at91sam9263.h4
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl.h5
-rw-r--r--include/asm-arm/arch-at91/uncompress.h32
-rw-r--r--include/asm-arm/arch-ixp4xx/cpu.h15
-rw-r--r--include/asm-arm/arch-ixp4xx/dsmg600.h7
-rw-r--r--include/asm-arm/arch-ixp4xx/hardware.h6
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h2
-rw-r--r--include/asm-arm/arch-ixp4xx/ixp4xx-regs.h36
-rw-r--r--include/asm-arm/arch-ixp4xx/nas100d.h18
-rw-r--r--include/asm-arm/arch-ixp4xx/npe.h39
-rw-r--r--include/asm-arm/arch-ixp4xx/nslu2.h21
-rw-r--r--include/asm-arm/arch-ixp4xx/platform.h21
-rw-r--r--include/asm-arm/arch-ixp4xx/qmgr.h126
-rw-r--r--include/asm-arm/arch-ixp4xx/uncompress.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h13
-rw-r--r--include/asm-arm/arch-realview/board-eb.h171
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S3
-rw-r--r--include/asm-arm/arch-realview/hardware.h1
-rw-r--r--include/asm-arm/arch-realview/irqs.h105
-rw-r--r--include/asm-arm/arch-realview/platform.h170
-rw-r--r--include/asm-arm/arch-realview/scu.h4
-rw-r--r--include/asm-arm/arch-realview/uncompress.h2
-rw-r--r--include/asm-arm/hardware/arm_twd.h7
-rw-r--r--include/asm-arm/smp.h21
-rw-r--r--include/linux/atmel_serial.h127
29 files changed, 658 insertions, 318 deletions
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index c2e11cc374ba..1551fc24eb43 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -89,7 +89,7 @@
89#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ 89#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
90#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ 90#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
91#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ 91#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
92#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ 92#define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */
93#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ 93#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
94#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ 94#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
95#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ 95#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
index 802891a9cd81..e8fc0b1c33f4 100644
--- a/include/asm-arm/arch-at91/at91rm9200.h
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -93,6 +93,11 @@
93#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ 93#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
94#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ 94#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
95 95
96#define AT91_USART0 AT91RM9200_BASE_US0
97#define AT91_USART1 AT91RM9200_BASE_US1
98#define AT91_USART2 AT91RM9200_BASE_US2
99#define AT91_USART3 AT91RM9200_BASE_US3
100
96#define AT91_MATRIX 0 /* not supported */ 101#define AT91_MATRIX 0 /* not supported */
97 102
98/* 103/*
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index 0427f8698c07..c8934fe34dc5 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -99,6 +99,13 @@
99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
100#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 100#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
101 101
102#define AT91_USART0 AT91SAM9260_BASE_US0
103#define AT91_USART1 AT91SAM9260_BASE_US1
104#define AT91_USART2 AT91SAM9260_BASE_US2
105#define AT91_USART3 AT91SAM9260_BASE_US3
106#define AT91_USART4 AT91SAM9260_BASE_US4
107#define AT91_USART5 AT91SAM9260_BASE_US5
108
102 109
103/* 110/*
104 * Internal Memory. 111 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
index 9eb459570330..c7c4778dac49 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -84,6 +84,10 @@
84#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 84#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
86 86
87#define AT91_USART0 AT91SAM9261_BASE_US0
88#define AT91_USART1 AT91SAM9261_BASE_US1
89#define AT91_USART2 AT91SAM9261_BASE_US2
90
87 91
88/* 92/*
89 * Internal Memory. 93 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index 115c47ac7ebb..018a647311da 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -101,6 +101,10 @@
101#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) 101#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
102#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 102#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
103 103
104#define AT91_USART0 AT91SAM9263_BASE_US0
105#define AT91_USART1 AT91SAM9263_BASE_US1
106#define AT91_USART2 AT91SAM9263_BASE_US2
107
104#define AT91_SMC AT91_SMC0 108#define AT91_SMC AT91_SMC0
105 109
106/* 110/*
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 8a9708a370c6..16d2832f6c0a 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -94,6 +94,11 @@
94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
95#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) 95#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
96 96
97#define AT91_USART0 AT91SAM9RL_BASE_US0
98#define AT91_USART1 AT91SAM9RL_BASE_US1
99#define AT91_USART2 AT91SAM9RL_BASE_US2
100#define AT91_USART3 AT91SAM9RL_BASE_US3
101
97 102
98/* 103/*
99 * Internal Memory. 104 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h
index 272a7e0dc6cf..f5636a8f6132 100644
--- a/include/asm-arm/arch-at91/uncompress.h
+++ b/include/asm-arm/arch-at91/uncompress.h
@@ -22,7 +22,23 @@
22#define __ASM_ARCH_UNCOMPRESS_H 22#define __ASM_ARCH_UNCOMPRESS_H
23 23
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/arch/at91_dbgu.h> 25#include <linux/atmel_serial.h>
26
27#if defined(CONFIG_AT91_EARLY_DBGU)
28#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
29#elif defined(CONFIG_AT91_EARLY_USART0)
30#define UART_OFFSET AT91_USART0
31#elif defined(CONFIG_AT91_EARLY_USART1)
32#define UART_OFFSET AT91_USART1
33#elif defined(CONFIG_AT91_EARLY_USART2)
34#define UART_OFFSET AT91_USART2
35#elif defined(CONFIG_AT91_EARLY_USART3)
36#define UART_OFFSET AT91_USART3
37#elif defined(CONFIG_AT91_EARLY_USART4)
38#define UART_OFFSET AT91_USART4
39#elif defined(CONFIG_AT91_EARLY_USART5)
40#define UART_OFFSET AT91_USART5
41#endif
26 42
27/* 43/*
28 * The following code assumes the serial port has already been 44 * The following code assumes the serial port has already been
@@ -33,22 +49,22 @@
33 */ 49 */
34static void putc(int c) 50static void putc(int c)
35{ 51{
36#ifdef AT91_DBGU 52#ifdef UART_OFFSET
37 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 53 void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */
38 54
39 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) 55 while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY))
40 barrier(); 56 barrier();
41 __raw_writel(c, sys + AT91_DBGU_THR); 57 __raw_writel(c, sys + ATMEL_US_THR);
42#endif 58#endif
43} 59}
44 60
45static inline void flush(void) 61static inline void flush(void)
46{ 62{
47#ifdef AT91_DBGU 63#ifdef UART_OFFSET
48 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 64 void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */
49 65
50 /* wait for transmission to complete */ 66 /* wait for transmission to complete */
51 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) 67 while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
52 barrier(); 68 barrier();
53#endif 69#endif
54} 70}
diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h
index d2523b326c6c..2fa3d6b8dbb8 100644
--- a/include/asm-arm/arch-ixp4xx/cpu.h
+++ b/include/asm-arm/arch-ixp4xx/cpu.h
@@ -28,4 +28,19 @@ extern unsigned int processor_id;
28#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ 28#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
29 IXP465_PROCESSOR_ID_VALUE) 29 IXP465_PROCESSOR_ID_VALUE)
30 30
31static inline u32 ixp4xx_read_feature_bits(void)
32{
33 unsigned int val = ~*IXP4XX_EXP_CFG2;
34 val &= ~IXP4XX_FEATURE_RESERVED;
35 if (!cpu_is_ixp46x())
36 val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
37
38 return val;
39}
40
41static inline void ixp4xx_write_feature_bits(u32 value)
42{
43 *IXP4XX_EXP_CFG2 = ~value;
44}
45
31#endif /* _ASM_ARCH_CPU_H */ 46#endif /* _ASM_ARCH_CPU_H */
diff --git a/include/asm-arm/arch-ixp4xx/dsmg600.h b/include/asm-arm/arch-ixp4xx/dsmg600.h
index a19605ad240d..b7673e171abe 100644
--- a/include/asm-arm/arch-ixp4xx/dsmg600.h
+++ b/include/asm-arm/arch-ixp4xx/dsmg600.h
@@ -40,18 +40,13 @@
40/* Buttons */ 40/* Buttons */
41 41
42#define DSMG600_PB_GPIO 15 /* power button */ 42#define DSMG600_PB_GPIO 15 /* power button */
43#define DSMG600_PB_BM (1L << DSMG600_PB_GPIO)
44
45#define DSMG600_RB_GPIO 3 /* reset button */ 43#define DSMG600_RB_GPIO 3 /* reset button */
46 44
47#define DSMG600_RB_IRQ IRQ_IXP4XX_GPIO3 45/* Power control */
48 46
49#define DSMG600_PO_GPIO 2 /* power off */ 47#define DSMG600_PO_GPIO 2 /* power off */
50 48
51/* LEDs */ 49/* LEDs */
52 50
53#define DSMG600_LED_PWR_GPIO 0 51#define DSMG600_LED_PWR_GPIO 0
54#define DSMG600_LED_PWR_BM (1L << DSMG600_LED_PWR_GPIO)
55
56#define DSMG600_LED_WLAN_GPIO 14 52#define DSMG600_LED_WLAN_GPIO 14
57#define DSMG600_LED_WLAN_BM (1L << DSMG600_LED_WLAN_GPIO)
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 297ceda08b61..73e8dc36f6a4 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -27,13 +27,13 @@
27 27
28#define pcibios_assign_all_busses() 1 28#define pcibios_assign_all_busses() 1
29 29
30/* Register locations and bits */
31#include "ixp4xx-regs.h"
32
30#ifndef __ASSEMBLER__ 33#ifndef __ASSEMBLER__
31#include <asm/arch/cpu.h> 34#include <asm/arch/cpu.h>
32#endif 35#endif
33 36
34/* Register locations and bits */
35#include "ixp4xx-regs.h"
36
37/* Platform helper functions and definitions */ 37/* Platform helper functions and definitions */
38#include "platform.h" 38#include "platform.h"
39 39
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index 9c5d2357aff3..de181ce958db 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARM_ARCH_IO_H 13#ifndef __ASM_ARM_ARCH_IO_H
14#define __ASM_ARM_ARCH_IO_H 14#define __ASM_ARM_ARCH_IO_H
15 15
16#include <linux/bitops.h>
17
16#include <asm/hardware.h> 18#include <asm/hardware.h>
17 19
18#define IO_SPACE_LIMIT 0xffff0000 20#define IO_SPACE_LIMIT 0xffff0000
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 5d949d763a91..c704fe8cf42f 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -15,10 +15,6 @@
15 * 15 *
16 */ 16 */
17 17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <asm/hardware.h>"
20#endif
21
22#ifndef _ASM_ARM_IXP4XX_H_ 18#ifndef _ASM_ARM_IXP4XX_H_
23#define _ASM_ARM_IXP4XX_H_ 19#define _ASM_ARM_IXP4XX_H_
24 20
@@ -607,4 +603,36 @@
607 603
608#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 604#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
609 605
606/* "fuse" bits of IXP_EXP_CFG2 */
607#define IXP4XX_FEATURE_RCOMP (1 << 0)
608#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
609#define IXP4XX_FEATURE_HASH (1 << 2)
610#define IXP4XX_FEATURE_AES (1 << 3)
611#define IXP4XX_FEATURE_DES (1 << 4)
612#define IXP4XX_FEATURE_HDLC (1 << 5)
613#define IXP4XX_FEATURE_AAL (1 << 6)
614#define IXP4XX_FEATURE_HSS (1 << 7)
615#define IXP4XX_FEATURE_UTOPIA (1 << 8)
616#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
617#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
618#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
619#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
620#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
621#define IXP4XX_FEATURE_PCI (1 << 14)
622#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
623#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
624#define IXP4XX_FEATURE_USB_HOST (1 << 18)
625#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
626#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
627#define IXP4XX_FEATURE_RSA (1 << 21)
628#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
629#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
630
631#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
632 IXP4XX_FEATURE_USB_HOST | \
633 IXP4XX_FEATURE_NPEA_ETH | \
634 IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
635 IXP4XX_FEATURE_RSA | \
636 IXP4XX_FEATURE_XSCALE_MAX_FREQ)
637
610#endif 638#endif
diff --git a/include/asm-arm/arch-ixp4xx/nas100d.h b/include/asm-arm/arch-ixp4xx/nas100d.h
index 131e0a1d0df3..98d937897bce 100644
--- a/include/asm-arm/arch-ixp4xx/nas100d.h
+++ b/include/asm-arm/arch-ixp4xx/nas100d.h
@@ -38,15 +38,15 @@
38 38
39/* Buttons */ 39/* Buttons */
40 40
41#define NAS100D_PB_GPIO 14 41#define NAS100D_PB_GPIO 14 /* power button */
42#define NAS100D_RB_GPIO 4 42#define NAS100D_RB_GPIO 4 /* reset button */
43
44/* Power control */
45
43#define NAS100D_PO_GPIO 12 /* power off */ 46#define NAS100D_PO_GPIO 12 /* power off */
44 47
45#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14 48/* LEDs */
46#define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4
47 49
48/* 50#define NAS100D_LED_WLAN_GPIO 0
49#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO) 51#define NAS100D_LED_DISK_GPIO 3
50#define NAS100D_PO_BM (1L << NAS100D_PO_GPIO) 52#define NAS100D_LED_PWR_GPIO 15
51#define NAS100D_RB_BM (1L << NAS100D_RB_GPIO)
52*/
diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h
new file mode 100644
index 000000000000..37d0511689dc
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/npe.h
@@ -0,0 +1,39 @@
1#ifndef __IXP4XX_NPE_H
2#define __IXP4XX_NPE_H
3
4#include <linux/kernel.h>
5
6extern const char *npe_names[];
7
8struct npe_regs {
9 u32 exec_addr, exec_data, exec_status_cmd, exec_count;
10 u32 action_points[4];
11 u32 watchpoint_fifo, watch_count;
12 u32 profile_count;
13 u32 messaging_status, messaging_control;
14 u32 mailbox_status, /*messaging_*/ in_out_fifo;
15};
16
17struct npe {
18 struct resource *mem_res;
19 struct npe_regs __iomem *regs;
20 u32 regs_phys;
21 int id;
22 int valid;
23};
24
25
26static inline const char *npe_name(struct npe *npe)
27{
28 return npe_names[npe->id];
29}
30
31int npe_running(struct npe *npe);
32int npe_send_message(struct npe *npe, const void *msg, const char *what);
33int npe_recv_message(struct npe *npe, void *msg, const char *what);
34int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
35int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
36struct npe *npe_request(int id);
37void npe_release(struct npe *npe);
38
39#endif /* __IXP4XX_NPE_H */
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
index 850fdc5b45da..714bbc65126a 100644
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -39,34 +39,17 @@
39 39
40/* Buttons */ 40/* Buttons */
41 41
42#define NSLU2_PB_GPIO 5 42#define NSLU2_PB_GPIO 5 /* power button */
43#define NSLU2_PO_GPIO 8 /* power off */ 43#define NSLU2_PO_GPIO 8 /* power off */
44#define NSLU2_RB_GPIO 12 44#define NSLU2_RB_GPIO 12 /* reset button */
45
46#define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5
47#define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12
48
49#define NSLU2_PB_BM (1L << NSLU2_PB_GPIO)
50#define NSLU2_PO_BM (1L << NSLU2_PO_GPIO)
51#define NSLU2_RB_BM (1L << NSLU2_RB_GPIO)
52 45
53/* Buzzer */ 46/* Buzzer */
54 47
55#define NSLU2_GPIO_BUZZ 4 48#define NSLU2_GPIO_BUZZ 4
56#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ)
57 49
58/* LEDs */ 50/* LEDs */
59 51
60#define NSLU2_LED_RED_GPIO 0 52#define NSLU2_LED_RED_GPIO 0
61#define NSLU2_LED_GRN_GPIO 1 53#define NSLU2_LED_GRN_GPIO 1
62
63#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED_GPIO)
64#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN_GPIO)
65
66#define NSLU2_LED_DISK1_GPIO 3 54#define NSLU2_LED_DISK1_GPIO 3
67#define NSLU2_LED_DISK2_GPIO 2 55#define NSLU2_LED_DISK2_GPIO 2
68
69#define NSLU2_LED_DISK1_BM (1L << NSLU2_LED_DISK1_GPIO)
70#define NSLU2_LED_DISK2_BM (1L << NSLU2_LED_DISK2_GPIO)
71
72
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 2ce28e3fd325..a1f2b5404db1 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -91,6 +91,27 @@ struct ixp4xx_pata_data {
91 91
92struct sys_timer; 92struct sys_timer;
93 93
94#define IXP4XX_ETH_NPEA 0x00
95#define IXP4XX_ETH_NPEB 0x10
96#define IXP4XX_ETH_NPEC 0x20
97
98/* Information about built-in Ethernet MAC interfaces */
99struct eth_plat_info {
100 u8 phy; /* MII PHY ID, 0 - 31 */
101 u8 rxq; /* configurable, currently 0 - 31 only */
102 u8 txreadyq;
103 u8 hwaddr[6];
104};
105
106/* Information about built-in HSS (synchronous serial) interfaces */
107struct hss_plat_info {
108 int (*set_clock)(int port, unsigned int clock_type);
109 int (*open)(int port, void *pdev,
110 void (*set_carrier_cb)(void *pdev, int carrier));
111 void (*close)(int port, void *pdev);
112 u8 txreadyq;
113};
114
94/* 115/*
95 * Frequency of clock used for primary clocksource 116 * Frequency of clock used for primary clocksource
96 */ 117 */
diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h
new file mode 100644
index 000000000000..1e52b95cede5
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/qmgr.h
@@ -0,0 +1,126 @@
1/*
2 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#ifndef IXP4XX_QMGR_H
10#define IXP4XX_QMGR_H
11
12#include <linux/io.h>
13#include <linux/kernel.h>
14
15#define HALF_QUEUES 32
16#define QUEUES 64 /* only 32 lower queues currently supported */
17#define MAX_QUEUE_LENGTH 4 /* in dwords */
18
19#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
20#define QUEUE_STAT1_NEARLY_EMPTY 2
21#define QUEUE_STAT1_NEARLY_FULL 4
22#define QUEUE_STAT1_FULL 8
23#define QUEUE_STAT2_UNDERFLOW 1
24#define QUEUE_STAT2_OVERFLOW 2
25
26#define QUEUE_WATERMARK_0_ENTRIES 0
27#define QUEUE_WATERMARK_1_ENTRY 1
28#define QUEUE_WATERMARK_2_ENTRIES 2
29#define QUEUE_WATERMARK_4_ENTRIES 3
30#define QUEUE_WATERMARK_8_ENTRIES 4
31#define QUEUE_WATERMARK_16_ENTRIES 5
32#define QUEUE_WATERMARK_32_ENTRIES 6
33#define QUEUE_WATERMARK_64_ENTRIES 7
34
35/* queue interrupt request conditions */
36#define QUEUE_IRQ_SRC_EMPTY 0
37#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
38#define QUEUE_IRQ_SRC_NEARLY_FULL 2
39#define QUEUE_IRQ_SRC_FULL 3
40#define QUEUE_IRQ_SRC_NOT_EMPTY 4
41#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
42#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
43#define QUEUE_IRQ_SRC_NOT_FULL 7
44
45struct qmgr_regs {
46 u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
47 u32 stat1[4]; /* 0x400 - 0x40F */
48 u32 stat2[2]; /* 0x410 - 0x417 */
49 u32 statne_h; /* 0x418 - queue nearly empty */
50 u32 statf_h; /* 0x41C - queue full */
51 u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
52 u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
53 u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
54 u32 reserved[1776];
55 u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
56};
57
58void qmgr_set_irq(unsigned int queue, int src,
59 void (*handler)(void *pdev), void *pdev);
60void qmgr_enable_irq(unsigned int queue);
61void qmgr_disable_irq(unsigned int queue);
62
63/* request_ and release_queue() must be called from non-IRQ context */
64int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
65 unsigned int nearly_empty_watermark,
66 unsigned int nearly_full_watermark);
67void qmgr_release_queue(unsigned int queue);
68
69
70static inline void qmgr_put_entry(unsigned int queue, u32 val)
71{
72 extern struct qmgr_regs __iomem *qmgr_regs;
73 __raw_writel(val, &qmgr_regs->acc[queue][0]);
74}
75
76static inline u32 qmgr_get_entry(unsigned int queue)
77{
78 extern struct qmgr_regs __iomem *qmgr_regs;
79 return __raw_readl(&qmgr_regs->acc[queue][0]);
80}
81
82static inline int qmgr_get_stat1(unsigned int queue)
83{
84 extern struct qmgr_regs __iomem *qmgr_regs;
85 return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
86 >> ((queue & 7) << 2)) & 0xF;
87}
88
89static inline int qmgr_get_stat2(unsigned int queue)
90{
91 extern struct qmgr_regs __iomem *qmgr_regs;
92 return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
93 >> ((queue & 0xF) << 1)) & 0x3;
94}
95
96static inline int qmgr_stat_empty(unsigned int queue)
97{
98 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
99}
100
101static inline int qmgr_stat_nearly_empty(unsigned int queue)
102{
103 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
104}
105
106static inline int qmgr_stat_nearly_full(unsigned int queue)
107{
108 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
109}
110
111static inline int qmgr_stat_full(unsigned int queue)
112{
113 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
114}
115
116static inline int qmgr_stat_underflow(unsigned int queue)
117{
118 return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
119}
120
121static inline int qmgr_stat_overflow(unsigned int queue)
122{
123 return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
124}
125
126#endif
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
index f7a35b78823f..34ef48fe327e 100644
--- a/include/asm-arm/arch-ixp4xx/uncompress.h
+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
@@ -13,7 +13,7 @@
13#ifndef _ARCH_UNCOMPRESS_H_ 13#ifndef _ARCH_UNCOMPRESS_H_
14#define _ARCH_UNCOMPRESS_H_ 14#define _ARCH_UNCOMPRESS_H_
15 15
16#include <asm/hardware.h> 16#include "ixp4xx-regs.h"
17#include <asm/mach-types.h> 17#include <asm/mach-types.h>
18#include <linux/serial_reg.h> 18#include <linux/serial_reg.h>
19 19
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 66d54119757c..8e1b3ead827f 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -12,6 +12,19 @@
12 12
13#ifndef __ASM_ARCH_PXA3XX_REGS_H 13#ifndef __ASM_ARCH_PXA3XX_REGS_H
14#define __ASM_ARCH_PXA3XX_REGS_H 14#define __ASM_ARCH_PXA3XX_REGS_H
15/*
16 * Service Power Management Unit (MPMU)
17 */
18#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
19#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
20#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
21#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
22#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
23#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
24#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
25#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
26#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
27#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
15 28
16/* 29/*
17 * Slave Power Managment Unit 30 * Slave Power Managment Unit
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h
new file mode 100644
index 000000000000..3e437b7f425a
--- /dev/null
+++ b/include/asm-arm/arch-realview/board-eb.h
@@ -0,0 +1,171 @@
1/*
2 * include/asm-arm/arch-realview/board-eb.h
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __ASM_ARCH_BOARD_EB_H
22#define __ASM_ARCH_BOARD_EB_H
23
24#include <asm/arch/platform.h>
25
26/*
27 * RealView EB + ARM11MPCore peripheral addresses
28 */
29#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
30#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
31#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
32#define REALVIEW_EB11MP_TWD_BASE 0x10100700
33#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
34#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
35#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
36#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
37#else
38#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
39#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
40#define REALVIEW_EB11MP_TWD_BASE 0x1F000700
41#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
42#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
43#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
44#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
45#endif
46
47#define IRQ_EB_GIC_START 32
48
49/*
50 * RealView EB interrupt sources
51 */
52#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
53#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
54#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
55#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
56#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
57#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
58#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
59#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
60#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
61 /* 9 reserved */
62#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
63#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
64#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
65#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
66#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
67#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
68#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
69#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
70#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
71#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
72#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
73#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
74#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
75#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
76#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
77#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
78#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
79#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
80#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
81#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
82#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
83#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
84
85/*
86 * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
87 */
88#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
89#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
90#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
91#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
92#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
93#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
94#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
95#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
96#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
97#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
98#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
99#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
100#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
101#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
102#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
103#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
104
105#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
106#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
107#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
108#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
109#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
110#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
111#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
112#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
113#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
114#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
115#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
116#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
117
118#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
119#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
120#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
121
122#define IRQ_EB11MP_UART2 -1
123#define IRQ_EB11MP_UART3 -1
124#define IRQ_EB11MP_CLCD -1
125#define IRQ_EB11MP_DMA -1
126#define IRQ_EB11MP_WDOG -1
127#define IRQ_EB11MP_GPIO0 -1
128#define IRQ_EB11MP_GPIO1 -1
129#define IRQ_EB11MP_GPIO2 -1
130#define IRQ_EB11MP_SCI -1
131#define IRQ_EB11MP_SSP -1
132
133#define NR_GIC_EB11MP 2
134
135/*
136 * Only define NR_IRQS if less than NR_IRQS_EB
137 */
138#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
139
140#if defined(CONFIG_MACH_REALVIEW_EB) \
141 && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
142#undef NR_IRQS
143#define NR_IRQS NR_IRQS_EB
144#endif
145
146#if defined(CONFIG_REALVIEW_EB_ARM11MP) \
147 && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
148#undef MAX_GIC_NR
149#define MAX_GIC_NR NR_GIC_EB11MP
150#endif
151
152/*
153 * Core tile identification (REALVIEW_SYS_PROCID)
154 */
155#define REALVIEW_EB_PROC_MASK 0xFF000000
156#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000
157#define REALVIEW_EB_PROC_ARM9 0x02000000
158#define REALVIEW_EB_PROC_ARM11 0x04000000
159#define REALVIEW_EB_PROC_ARM11MP 0x06000000
160
161#define check_eb_proc(proc_type) \
162 ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \
163 == proc_type)
164
165#ifdef CONFIG_REALVIEW_EB_ARM11MP
166#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
167#else
168#define core_tile_eb11mp() 0
169#endif
170
171#endif /* __ASM_ARCH_BOARD_EB_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 3b4e2076603a..cd26306d8e57 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -14,7 +14,8 @@
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp 16 .macro get_irqnr_preamble, base, tmp
17 ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) 17 ldr \base, =gic_cpu_base_addr
18 ldr \base, [\base]
18 .endm 19 .endm
19 20
20 .macro arch_ret_to_user, tmp1, tmp2 21 .macro arch_ret_to_user, tmp1, tmp2
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
index aa78fe087ab2..bad8d7ce9bfe 100644
--- a/include/asm-arm/arch-realview/hardware.h
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -23,7 +23,6 @@
23#define __ASM_ARCH_HARDWARE_H 23#define __ASM_ARCH_HARDWARE_H
24 24
25#include <asm/sizes.h> 25#include <asm/sizes.h>
26#include <asm/arch/platform.h>
27 26
28/* macro to get at IO space when running virtually */ 27/* macro to get at IO space when running virtually */
29#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) 28#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index 5a5db56f86b8..ad0c911002fc 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -19,103 +19,18 @@
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21 21
22#include <asm/arch/platform.h> 22#ifndef __ASM_ARCH_IRQS_H
23#define __ASM_ARCH_IRQS_H
23 24
24#define IRQ_LOCALTIMER 29 25#include <asm/arch/board-eb.h>
25#define IRQ_LOCALWDOG 30
26 26
27/* 27#define IRQ_LOCALTIMER 29
28 * IRQ interrupts definitions are the same the INT definitions 28#define IRQ_LOCALWDOG 30
29 * held within platform.h
30 */
31#define IRQ_GIC_START 32
32#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT)
33#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT)
34#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx)
35#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx)
36#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1)
37#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3)
38#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0)
39#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1)
40#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2)
41#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3)
42#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT)
43#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT)
44#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0)
45#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1)
46#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2)
47#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3)
48#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT)
49#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT)
50#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT)
51#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT)
52#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT)
53#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT)
54#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B)
55#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B)
56#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0)
57#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1)
58#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3)
59#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD)
60#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH)
61#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD)
62#define IRQ_DoC (IRQ_GIC_START + INT_DoC)
63#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A)
64#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A)
65#define IRQ_AACI (IRQ_GIC_START + INT_AACI)
66#define IRQ_ETH (IRQ_GIC_START + INT_ETH)
67#define IRQ_USB (IRQ_GIC_START + INT_USB)
68#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0)
69#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1)
70#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2)
71#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3)
72#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0)
73#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1)
74#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2)
75#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3)
76#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4)
77#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5)
78#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6)
79#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7)
80 29
81#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1) 30#define IRQ_GIC_START 32
82#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2)
83 31
84#define IRQMASK_WDOGINT INTMASK_WDOGINT 32#ifndef NR_IRQS
85#define IRQMASK_SOFTINT INTMASK_SOFTINT 33#error "NR_IRQS not defined by the board-specific files"
86#define IRQMASK_COMMRx INTMASK_COMMRx 34#endif
87#define IRQMASK_COMMTx INTMASK_COMMTx
88#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
89#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
90#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
91#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
92#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
93#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
94#define IRQMASK_RTCINT INTMASK_RTCINT
95#define IRQMASK_SSPINT INTMASK_SSPINT
96#define IRQMASK_UARTINT0 INTMASK_UARTINT0
97#define IRQMASK_UARTINT1 INTMASK_UARTINT1
98#define IRQMASK_UARTINT2 INTMASK_UARTINT2
99#define IRQMASK_SCIINT INTMASK_SCIINT
100#define IRQMASK_CLCDINT INTMASK_CLCDINT
101#define IRQMASK_DMAINT INTMASK_DMAINT
102#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
103#define IRQMASK_MBXINT INTMASK_MBXINT
104#define IRQMASK_GNDINT INTMASK_GNDINT
105#define IRQMASK_MMCI0B INTMASK_MMCI0B
106#define IRQMASK_MMCI1B INTMASK_MMCI1B
107#define IRQMASK_KMI0 INTMASK_KMI0
108#define IRQMASK_KMI1 INTMASK_KMI1
109#define IRQMASK_SCI3 INTMASK_SCI3
110#define IRQMASK_UART3 INTMASK_UART3
111#define IRQMASK_CLCD INTMASK_CLCD
112#define IRQMASK_TOUCH INTMASK_TOUCH
113#define IRQMASK_KEYPAD INTMASK_KEYPAD
114#define IRQMASK_DoC INTMASK_DoC
115#define IRQMASK_MMCI0A INTMASK_MMCI0A
116#define IRQMASK_MMCI1A INTMASK_MMCI1A
117#define IRQMASK_AACI INTMASK_AACI
118#define IRQMASK_ETH INTMASK_ETH
119#define IRQMASK_USB INTMASK_USB
120 35
121#define NR_IRQS (IRQ_GIC_START + 96) 36#endif
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 6e0eab95a3a2..4fd351b5e4a2 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -18,8 +18,8 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20 20
21#ifndef __address_h 21#ifndef __ASM_ARCH_PLATFORM_H
22#define __address_h 1 22#define __ASM_ARCH_PLATFORM_H
23 23
24/* 24/*
25 * Memory definitions 25 * Memory definitions
@@ -81,11 +81,12 @@
81#define REALVIEW_SYS_24MHz_OFFSET 0x5C 81#define REALVIEW_SYS_24MHz_OFFSET 0x5C
82#define REALVIEW_SYS_MISC_OFFSET 0x60 82#define REALVIEW_SYS_MISC_OFFSET 0x60
83#define REALVIEW_SYS_IOSEL_OFFSET 0x70 83#define REALVIEW_SYS_IOSEL_OFFSET 0x70
84#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 84#define REALVIEW_SYS_PROCID_OFFSET 0x84
85#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 85#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
86#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 86#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
87#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C 87#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
88#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 88#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
89#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
89 90
90#define REALVIEW_SYS_BASE 0x10000000 91#define REALVIEW_SYS_BASE 0x10000000
91#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) 92#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
@@ -114,6 +115,7 @@
114#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) 115#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
115#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) 116#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
116#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) 117#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
118#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
117#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) 119#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
118#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) 120#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
119#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) 121#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
@@ -203,30 +205,8 @@
203 /* Reserved 0x1001A000 - 0x1001FFFF */ 205 /* Reserved 0x1001A000 - 0x1001FFFF */
204#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ 206#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
205#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ 207#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
206#ifndef CONFIG_REALVIEW_MPCORE
207#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ 208#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
208#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ 209#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
209#else
210#ifdef CONFIG_REALVIEW_MPCORE_REVB
211#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
212#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
213#define REALVIEW_TWD_BASE 0x10100700
214#define REALVIEW_TWD_SIZE 0x00000100
215#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
216#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
217#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
218#else
219#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
220#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
221#define REALVIEW_TWD_BASE 0x1F000700
222#define REALVIEW_TWD_SIZE 0x00000100
223#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
224#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
225#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
226#endif
227#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
228#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
229#endif
230#define REALVIEW_SMC_BASE 0x10080000 /* SMC */ 210#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
231 /* Reserved 0x10090000 - 0x100EFFFF */ 211 /* Reserved 0x10090000 - 0x100EFFFF */
232 212
@@ -283,134 +263,6 @@
283#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ 263#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
284#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ 264#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
285 265
286/* ------------------------------------------------------------------------
287 * Interrupts - bit assignment (primary)
288 * ------------------------------------------------------------------------
289 */
290#ifndef CONFIG_REALVIEW_MPCORE
291#define INT_WDOGINT 0 /* Watchdog timer */
292#define INT_SOFTINT 1 /* Software interrupt */
293#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
294#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
295#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
296#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
297#define INT_GPIOINT0 6 /* GPIO 0 */
298#define INT_GPIOINT1 7 /* GPIO 1 */
299#define INT_GPIOINT2 8 /* GPIO 2 */
300/* 9 reserved */
301#define INT_RTCINT 10 /* Real Time Clock */
302#define INT_SSPINT 11 /* Synchronous Serial Port */
303#define INT_UARTINT0 12 /* UART 0 on development chip */
304#define INT_UARTINT1 13 /* UART 1 on development chip */
305#define INT_UARTINT2 14 /* UART 2 on development chip */
306#define INT_UARTINT3 15 /* UART 3 on development chip */
307#define INT_SCIINT 16 /* Smart Card Interface */
308#define INT_MMCI0A 17 /* Multimedia Card 0A */
309#define INT_MMCI0B 18 /* Multimedia Card 0B */
310#define INT_AACI 19 /* Audio Codec */
311#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
312#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
313#define INT_CHARLCD 22 /* Character LCD */
314#define INT_CLCDINT 23 /* CLCD controller */
315#define INT_DMAINT 24 /* DMA controller */
316#define INT_PWRFAILINT 25 /* Power failure */
317#define INT_PISMO 26
318#define INT_DoC 27 /* Disk on Chip memory controller */
319#define INT_ETH 28 /* Ethernet controller */
320#define INT_USB 29 /* USB controller */
321#define INT_TSPENINT 30 /* Touchscreen pen */
322#define INT_TSKPADINT 31 /* Touchscreen keypad */
323
324#else
325
326#define MAX_GIC_NR 2
327
328#define INT_AACI 0
329#define INT_TIMERINT0_1 1
330#define INT_TIMERINT2_3 2
331#define INT_USB 3
332#define INT_UARTINT0 4
333#define INT_UARTINT1 5
334#define INT_RTCINT 6
335#define INT_KMI0 7
336#define INT_KMI1 8
337#define INT_ETH 9
338#define INT_EB_IRQ1 10 /* main GIC */
339#define INT_EB_IRQ2 11 /* tile GIC */
340#define INT_EB_FIQ1 12 /* main GIC */
341#define INT_EB_FIQ2 13 /* tile GIC */
342#define INT_MMCI0A 14
343#define INT_MMCI0B 15
344
345#define INT_PMU_CPU0 17
346#define INT_PMU_CPU1 18
347#define INT_PMU_CPU2 19
348#define INT_PMU_CPU3 20
349#define INT_PMU_SCU0 21
350#define INT_PMU_SCU1 22
351#define INT_PMU_SCU2 23
352#define INT_PMU_SCU3 24
353#define INT_PMU_SCU4 25
354#define INT_PMU_SCU5 26
355#define INT_PMU_SCU6 27
356#define INT_PMU_SCU7 28
357
358#define INT_L220_EVENT 29
359#define INT_L220_SLAVE 30
360#define INT_L220_DECODE 31
361
362#define INT_UARTINT2 -1
363#define INT_UARTINT3 -1
364#define INT_CLCDINT -1
365#define INT_DMAINT -1
366#define INT_WDOGINT -1
367#define INT_GPIOINT0 -1
368#define INT_GPIOINT1 -1
369#define INT_GPIOINT2 -1
370#define INT_SCIINT -1
371#define INT_SSPINT -1
372#endif
373
374/*
375 * Interrupt bit positions
376 *
377 */
378#define INTMASK_WDOGINT (1 << INT_WDOGINT)
379#define INTMASK_SOFTINT (1 << INT_SOFTINT)
380#define INTMASK_COMMRx (1 << INT_COMMRx)
381#define INTMASK_COMMTx (1 << INT_COMMTx)
382#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
383#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
384#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
385#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
386#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
387#define INTMASK_RTCINT (1 << INT_RTCINT)
388#define INTMASK_SSPINT (1 << INT_SSPINT)
389#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
390#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
391#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
392#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
393#define INTMASK_SCIINT (1 << INT_SCIINT)
394#define INTMASK_MMCI0A (1 << INT_MMCI0A)
395#define INTMASK_MMCI0B (1 << INT_MMCI0B)
396#define INTMASK_AACI (1 << INT_AACI)
397#define INTMASK_KMI0 (1 << INT_KMI0)
398#define INTMASK_KMI1 (1 << INT_KMI1)
399#define INTMASK_CHARLCD (1 << INT_CHARLCD)
400#define INTMASK_CLCDINT (1 << INT_CLCDINT)
401#define INTMASK_DMAINT (1 << INT_DMAINT)
402#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
403#define INTMASK_PISMO (1 << INT_PISMO)
404#define INTMASK_DoC (1 << INT_DoC)
405#define INTMASK_ETH (1 << INT_ETH)
406#define INTMASK_USB (1 << INT_USB)
407#define INTMASK_TSPENINT (1 << INT_TSPENINT)
408#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
409
410#define MAXIRQNUM 31
411#define MAXFIQNUM 31
412#define MAXSWINUM 31
413
414/* 266/*
415 * Application Flash 267 * Application Flash
416 * 268 *
@@ -463,6 +315,4 @@
463#define REALVIEW_CSR_BASE 0x10000000 315#define REALVIEW_CSR_BASE 0x10000000
464#define REALVIEW_CSR_SIZE 0x10000000 316#define REALVIEW_CSR_SIZE 0x10000000
465 317
466#endif 318#endif /* __ASM_ARCH_PLATFORM_H */
467
468/* END */
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h
index cc293640178e..08b3db883c36 100644
--- a/include/asm-arm/arch-realview/scu.h
+++ b/include/asm-arm/arch-realview/scu.h
@@ -1,8 +1,8 @@
1#ifndef __ASMARM_ARCH_SCU_H 1#ifndef __ASMARM_ARCH_SCU_H
2#define __ASMARM_ARCH_SCU_H 2#define __ASMARM_ARCH_SCU_H
3 3
4#include <asm/arch/platform.h> 4#include <asm/arch/board-eb.h>
5 5
6#define SCU_BASE REALVIEW_MPCORE_SCU_BASE 6#define SCU_BASE REALVIEW_EB11MP_SCU_BASE
7 7
8#endif 8#endif
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
index f05631d76743..3d5c2db07a26 100644
--- a/include/asm-arm/arch-realview/uncompress.h
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -19,6 +19,8 @@
19 */ 19 */
20#include <asm/hardware.h> 20#include <asm/hardware.h>
21 21
22#include <asm/arch/platform.h>
23
22#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) 24#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
23#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) 25#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
24#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) 26#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
diff --git a/include/asm-arm/hardware/arm_twd.h b/include/asm-arm/hardware/arm_twd.h
index 131d5b40e072..e521b70713c8 100644
--- a/include/asm-arm/hardware/arm_twd.h
+++ b/include/asm-arm/hardware/arm_twd.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_HARDWARE_TWD_H 1#ifndef __ASM_HARDWARE_TWD_H
2#define __ASM_HARDWARE_TWD_H 2#define __ASM_HARDWARE_TWD_H
3 3
4#define TWD_TIMER_LOAD 0x00 4#define TWD_TIMER_LOAD 0x00
5#define TWD_TIMER_COUNTER 0x04 5#define TWD_TIMER_COUNTER 0x04
6#define TWD_TIMER_CONTROL 0x08 6#define TWD_TIMER_CONTROL 0x08
7#define TWD_TIMER_INTSTAT 0x0C 7#define TWD_TIMER_INTSTAT 0x0C
@@ -13,4 +13,9 @@
13#define TWD_WDOG_RESETSTAT 0x30 13#define TWD_WDOG_RESETSTAT 0x30
14#define TWD_WDOG_DISABLE 0x34 14#define TWD_WDOG_DISABLE 0x34
15 15
16#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
17#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20
16#endif 21#endif
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index f67acce387e7..af99636db400 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -61,6 +61,11 @@ extern void smp_cross_call(cpumask_t callmap);
61extern void smp_send_timer(void); 61extern void smp_send_timer(void);
62 62
63/* 63/*
64 * Broadcast a clock event to other CPUs.
65 */
66extern void smp_timer_broadcast(cpumask_t mask);
67
68/*
64 * Boot a secondary CPU, and assign it the specified idle task. 69 * Boot a secondary CPU, and assign it the specified idle task.
65 * This also gives us the initial stack to use for this CPU. 70 * This also gives us the initial stack to use for this CPU.
66 */ 71 */
@@ -96,11 +101,12 @@ extern void platform_cpu_die(unsigned int cpu);
96extern int platform_cpu_kill(unsigned int cpu); 101extern int platform_cpu_kill(unsigned int cpu);
97extern void platform_cpu_enable(unsigned int cpu); 102extern void platform_cpu_enable(unsigned int cpu);
98 103
99#ifdef CONFIG_LOCAL_TIMERS
100/* 104/*
101 * Setup a local timer interrupt for a CPU. 105 * Local timer interrupt handling function (can be IPI'ed).
102 */ 106 */
103extern void local_timer_setup(unsigned int cpu); 107extern void local_timer_interrupt(void);
108
109#ifdef CONFIG_LOCAL_TIMERS
104 110
105/* 111/*
106 * Stop a local timer interrupt. 112 * Stop a local timer interrupt.
@@ -114,10 +120,6 @@ extern int local_timer_ack(void);
114 120
115#else 121#else
116 122
117static inline void local_timer_setup(unsigned int cpu)
118{
119}
120
121static inline void local_timer_stop(unsigned int cpu) 123static inline void local_timer_stop(unsigned int cpu)
122{ 124{
123} 125}
@@ -125,6 +127,11 @@ static inline void local_timer_stop(unsigned int cpu)
125#endif 127#endif
126 128
127/* 129/*
130 * Setup a local timer interrupt for a CPU.
131 */
132extern void local_timer_setup(unsigned int cpu);
133
134/*
128 * show local interrupt info 135 * show local interrupt info
129 */ 136 */
130extern void show_local_irqs(struct seq_file *); 137extern void show_local_irqs(struct seq_file *);
diff --git a/include/linux/atmel_serial.h b/include/linux/atmel_serial.h
new file mode 100644
index 000000000000..fd6833764d72
--- /dev/null
+++ b/include/linux/atmel_serial.h
@@ -0,0 +1,127 @@
1/*
2 * include/linux/atmel_serial.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * USART registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef ATMEL_SERIAL_H
17#define ATMEL_SERIAL_H
18
19#define ATMEL_US_CR 0x00 /* Control Register */
20#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */
21#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */
22#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */
23#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */
24#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */
25#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */
26#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */
27#define ATMEL_US_STTBRK (1 << 9) /* Start Break */
28#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */
29#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */
30#define ATMEL_US_SENDA (1 << 12) /* Send Address */
31#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
32#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
33#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
34#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
35#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
36#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
37#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
38
39#define ATMEL_US_MR 0x04 /* Mode Register */
40#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */
41#define ATMEL_US_USMODE_NORMAL 0
42#define ATMEL_US_USMODE_RS485 1
43#define ATMEL_US_USMODE_HWHS 2
44#define ATMEL_US_USMODE_MODEM 3
45#define ATMEL_US_USMODE_ISO7816_T0 4
46#define ATMEL_US_USMODE_ISO7816_T1 6
47#define ATMEL_US_USMODE_IRDA 8
48#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
49#define ATMEL_US_USCLKS_MCK (0 << 4)
50#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
51#define ATMEL_US_USCLKS_SCK (3 << 4)
52#define ATMEL_US_CHRL (3 << 6) /* Character Length */
53#define ATMEL_US_CHRL_5 (0 << 6)
54#define ATMEL_US_CHRL_6 (1 << 6)
55#define ATMEL_US_CHRL_7 (2 << 6)
56#define ATMEL_US_CHRL_8 (3 << 6)
57#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */
58#define ATMEL_US_PAR (7 << 9) /* Parity Type */
59#define ATMEL_US_PAR_EVEN (0 << 9)
60#define ATMEL_US_PAR_ODD (1 << 9)
61#define ATMEL_US_PAR_SPACE (2 << 9)
62#define ATMEL_US_PAR_MARK (3 << 9)
63#define ATMEL_US_PAR_NONE (4 << 9)
64#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
65#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */
66#define ATMEL_US_NBSTOP_1 (0 << 12)
67#define ATMEL_US_NBSTOP_1_5 (1 << 12)
68#define ATMEL_US_NBSTOP_2 (2 << 12)
69#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */
70#define ATMEL_US_CHMODE_NORMAL (0 << 14)
71#define ATMEL_US_CHMODE_ECHO (1 << 14)
72#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
73#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
74#define ATMEL_US_MSBF (1 << 16) /* Bit Order */
75#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */
76#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */
77#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */
78#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
79#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */
80#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */
81#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
82
83#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
84#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */
85#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */
86#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */
87#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */
88#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
89#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */
90#define ATMEL_US_FRAME (1 << 6) /* Framing Error */
91#define ATMEL_US_PARE (1 << 7) /* Parity Error */
92#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */
93#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */
94#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
95#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
96#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
97#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
98#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
99#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
100#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
101#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
102#define ATMEL_US_RI (1 << 20) /* RI */
103#define ATMEL_US_DSR (1 << 21) /* DSR */
104#define ATMEL_US_DCD (1 << 22) /* DCD */
105#define ATMEL_US_CTS (1 << 23) /* CTS */
106
107#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
108#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
109#define ATMEL_US_CSR 0x14 /* Channel Status Register */
110#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
111#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
112#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
113
114#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
115#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
116
117#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */
118#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */
119
120#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
121#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */
122
123#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
124#define ATMEL_US_NER 0x44 /* Number of Errors Register */
125#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
126
127#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 02:29:56 -0500