102 files changed, 1096 insertions, 386 deletions

diff --git a/include/acpi/processor.h b/include/acpi/processor.h
index 26d79f6db8a0..76411b1fc4fd 100644
--- a/include/acpi/processor.h
+++ b/include/acpi/processor.h
@@ -78,7 +78,6 @@ struct acpi_processor_cx {
 struct acpi_processor_power {
         struct cpuidle_device dev;
         struct acpi_processor_cx *state;
-        struct acpi_processor_cx *bm_state;
         unsigned long bm_check_timestamp;
         u32 default_state;
         u32 bm_activity;
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index c0d7075982c1..79054965baa6 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -33,6 +33,7 @@
 
 #include <linux/mtd/partitions.h>
 #include <linux/device.h>
+#include <linux/i2c.h>
 #include <linux/spi/spi.h>
 
  /* USB Device */
@@ -94,7 +95,7 @@ struct at91_nand_data {
 extern void __init at91_add_device_nand(struct at91_nand_data *data);
 
  /* I2C*/
-extern void __init at91_add_device_i2c(void);
+extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
 
  /* SPI */
 extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h
index e69639585721..27c580898958 100644
--- a/include/asm-arm/arch-ixp23xx/irqs.h
+++ b/include/asm-arm/arch-ixp23xx/irqs.h
@@ -153,7 +153,7 @@
  */
 #define NR_IXP23XX_MACH_IRQS            32
 
-#define NR_IRQS                         NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS
+#define NR_IRQS                         (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS)
 
 #define IXP23XX_MACH_IRQ(irq)           (NR_IXP23XX_IRQ + (irq))
 
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index b3cf33441f6e..56d2c98e143c 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -37,7 +37,7 @@
 #define OMAP1510P1_EMIFF_PRI_VALUE              0x00
 
 #define NR_FPGA_IRQS            24
-#define NR_IRQS                 IH_BOARD_BASE + NR_FPGA_IRQS
+#define NR_IRQS                 (IH_BOARD_BASE + NR_FPGA_IRQS)
 
 #ifndef __ASSEMBLY__
 void fpga_write(unsigned char val, int reg);
diff --git a/include/asm-arm/arch-s3c2410/spi-gpio.h b/include/asm-arm/arch-s3c2410/spi-gpio.h
index c1e4db7c9710..ba1dca88d480 100644
--- a/include/asm-arm/arch-s3c2410/spi-gpio.h
+++ b/include/asm-arm/arch-s3c2410/spi-gpio.h
@@ -21,6 +21,8 @@ struct s3c2410_spigpio_info {
         unsigned long            pin_mosi;
         unsigned long            pin_miso;
 
+        int                      bus_num;
+
         unsigned long            board_size;
         struct spi_board_info   *board_info;
 
diff --git a/include/asm-avr32/cacheflush.h b/include/asm-avr32/cacheflush.h
index dfaaa88cd412..670674749b20 100644
--- a/include/asm-avr32/cacheflush.h
+++ b/include/asm-avr32/cacheflush.h
@@ -116,15 +116,16 @@ extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
  * flush with all configurations.
  */
 extern void flush_icache_range(unsigned long start, unsigned long end);
-extern void flush_icache_user_range(struct vm_area_struct *vma,
-                                    struct page *page,
-                                    unsigned long addr, int len);
 
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) do { \
-        memcpy(dst, src, len);                                  \
-        flush_icache_user_range(vma, page, vaddr, len);         \
-} while(0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len)    \
-        memcpy(dst, src, len)
+extern void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+                unsigned long vaddr, void *dst, const void *src,
+                unsigned long len);
+
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+                struct page *page, unsigned long vaddr, void *dst,
+                const void *src, unsigned long len)
+{
+        memcpy(dst, src, len);
+}
 
 #endif /* __ASM_AVR32_CACHEFLUSH_H */
diff --git a/include/asm-avr32/ocd.h b/include/asm-avr32/ocd.h
index 46f73180a127..996405e0393f 100644
--- a/include/asm-avr32/ocd.h
+++ b/include/asm-avr32/ocd.h
@@ -1,7 +1,7 @@
 /*
- * AVR32 OCD Registers
+ * AVR32 OCD Interface and register definitions
  *
- * Copyright (C) 2004-2006 Atmel Corporation
+ * Copyright (C) 2004-2007 Atmel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -10,69 +10,529 @@
 #ifndef __ASM_AVR32_OCD_H
 #define __ASM_AVR32_OCD_H
 
-/* Debug Registers */
-#define DBGREG_DID                0
-#define DBGREG_DC                 8
-#define DBGREG_DS                16
-#define DBGREG_RWCS              28
-#define DBGREG_RWA               36
-#define DBGREG_RWD               40
-#define DBGREG_WT                44
-#define DBGREG_DTC               52
-#define DBGREG_DTSA0             56
-#define DBGREG_DTSA1             60
-#define DBGREG_DTEA0             72
-#define DBGREG_DTEA1             76
-#define DBGREG_BWC0A             88
-#define DBGREG_BWC0B             92
-#define DBGREG_BWC1A             96
-#define DBGREG_BWC1B            100
-#define DBGREG_BWC2A            104
-#define DBGREG_BWC2B            108
-#define DBGREG_BWC3A            112
-#define DBGREG_BWC3B            116
-#define DBGREG_BWA0A            120
-#define DBGREG_BWA0B            124
-#define DBGREG_BWA1A            128
-#define DBGREG_BWA1B            132
-#define DBGREG_BWA2A            136
-#define DBGREG_BWA2B            140
-#define DBGREG_BWA3A            144
-#define DBGREG_BWA3B            148
-#define DBGREG_BWD3A            153
-#define DBGREG_BWD3B            156
-
-#define DBGREG_PID              284
-
-#define SABAH_OCD               0x01
-#define SABAH_ICACHE            0x02
-#define SABAH_MEM_CACHED        0x04
-#define SABAH_MEM_UNCACHED      0x05
-
-/* Fields in the Development Control register */
-#define DC_SS_BIT               8
-
-#define DC_SS                   (1 <<  DC_SS_BIT)
-#define DC_DBE                  (1 << 13)
-#define DC_RID                  (1 << 27)
-#define DC_ORP                  (1 << 28)
-#define DC_MM                   (1 << 29)
-#define DC_RES                  (1 << 30)
-
-/* Fields in the Development Status register */
-#define DS_SSS                  (1 <<  0)
-#define DS_SWB                  (1 <<  1)
-#define DS_HWB                  (1 <<  2)
-#define DS_BP_SHIFT             8
-#define DS_BP_MASK              (0xff << DS_BP_SHIFT)
-
-#define __mfdr(addr)                                                    \
-({                                                                      \
-        register unsigned long value;                                   \
-        asm volatile("mfdr      %0, %1" : "=r"(value) : "i"(addr));     \
-        value;                                                          \
-})
-#define __mtdr(addr, value)                                             \
-        asm volatile("mtdr      %0, %1" : : "i"(addr), "r"(value))
+/* OCD Register offsets. Abbreviations used below:
+ *
+ *      BP      Breakpoint
+ *      Comm    Communication
+ *      DT      Data Trace
+ *      PC      Program Counter
+ *      PID     Process ID
+ *      R/W     Read/Write
+ *      WP      Watchpoint
+ */
+#define OCD_DID                         0x0000  /* Device ID */
+#define OCD_DC                          0x0008  /* Development Control */
+#define OCD_DS                          0x0010  /* Development Status */
+#define OCD_RWCS                        0x001c  /* R/W Access Control */
+#define OCD_RWA                         0x0024  /* R/W Access Address */
+#define OCD_RWD                         0x0028  /* R/W Access Data */
+#define OCD_WT                          0x002c  /* Watchpoint Trigger */
+#define OCD_DTC                         0x0034  /* Data Trace Control */
+#define OCD_DTSA0                       0x0038  /* DT Start Addr Channel 0 */
+#define OCD_DTSA1                       0x003c  /* DT Start Addr Channel 1 */
+#define OCD_DTEA0                       0x0048  /* DT End Addr Channel 0 */
+#define OCD_DTEA1                       0x004c  /* DT End Addr Channel 1 */
+#define OCD_BWC0A                       0x0058  /* PC BP/WP Control 0A */
+#define OCD_BWC0B                       0x005c  /* PC BP/WP Control 0B */
+#define OCD_BWC1A                       0x0060  /* PC BP/WP Control 1A */
+#define OCD_BWC1B                       0x0064  /* PC BP/WP Control 1B */
+#define OCD_BWC2A                       0x0068  /* PC BP/WP Control 2A */
+#define OCD_BWC2B                       0x006c  /* PC BP/WP Control 2B */
+#define OCD_BWC3A                       0x0070  /* Data BP/WP Control 3A */
+#define OCD_BWC3B                       0x0074  /* Data BP/WP Control 3B */
+#define OCD_BWA0A                       0x0078  /* PC BP/WP Address 0A */
+#define OCD_BWA0B                       0x007c  /* PC BP/WP Address 0B */
+#define OCD_BWA1A                       0x0080  /* PC BP/WP Address 1A */
+#define OCD_BWA1B                       0x0084  /* PC BP/WP Address 1B */
+#define OCD_BWA2A                       0x0088  /* PC BP/WP Address 2A */
+#define OCD_BWA2B                       0x008c  /* PC BP/WP Address 2B */
+#define OCD_BWA3A                       0x0090  /* Data BP/WP Address 3A */
+#define OCD_BWA3B                       0x0094  /* Data BP/WP Address 3B */
+#define OCD_NXCFG                       0x0100  /* Nexus Configuration */
+#define OCD_DINST                       0x0104  /* Debug Instruction */
+#define OCD_DPC                         0x0108  /* Debug Program Counter */
+#define OCD_CPUCM                       0x010c  /* CPU Control Mask */
+#define OCD_DCCPU                       0x0110  /* Debug Comm CPU */
+#define OCD_DCEMU                       0x0114  /* Debug Comm Emulator */
+#define OCD_DCSR                        0x0118  /* Debug Comm Status */
+#define OCD_PID                         0x011c  /* Ownership Trace PID */
+#define OCD_EPC0                        0x0120  /* Event Pair Control 0 */
+#define OCD_EPC1                        0x0124  /* Event Pair Control 1 */
+#define OCD_EPC2                        0x0128  /* Event Pair Control 2 */
+#define OCD_EPC3                        0x012c  /* Event Pair Control 3 */
+#define OCD_AXC                         0x0130  /* AUX port Control */
+
+/* Bits in DID */
+#define OCD_DID_MID_START               1
+#define OCD_DID_MID_SIZE                11
+#define OCD_DID_PN_START                12
+#define OCD_DID_PN_SIZE                 16
+#define OCD_DID_RN_START                28
+#define OCD_DID_RN_SIZE                 4
+
+/* Bits in DC */
+#define OCD_DC_TM_START                 0
+#define OCD_DC_TM_SIZE                  2
+#define OCD_DC_EIC_START                3
+#define OCD_DC_EIC_SIZE                 2
+#define OCD_DC_OVC_START                5
+#define OCD_DC_OVC_SIZE                 3
+#define OCD_DC_SS_BIT                   8
+#define OCD_DC_DBR_BIT                  12
+#define OCD_DC_DBE_BIT                  13
+#define OCD_DC_EOS_START                20
+#define OCD_DC_EOS_SIZE                 2
+#define OCD_DC_SQA_BIT                  22
+#define OCD_DC_IRP_BIT                  23
+#define OCD_DC_IFM_BIT                  24
+#define OCD_DC_TOZ_BIT                  25
+#define OCD_DC_TSR_BIT                  26
+#define OCD_DC_RID_BIT                  27
+#define OCD_DC_ORP_BIT                  28
+#define OCD_DC_MM_BIT                   29
+#define OCD_DC_RES_BIT                  30
+#define OCD_DC_ABORT_BIT                31
+
+/* Bits in DS */
+#define OCD_DS_SSS_BIT                  0
+#define OCD_DS_SWB_BIT                  1
+#define OCD_DS_HWB_BIT                  2
+#define OCD_DS_HWE_BIT                  3
+#define OCD_DS_STP_BIT                  4
+#define OCD_DS_DBS_BIT                  5
+#define OCD_DS_BP_START                 8
+#define OCD_DS_BP_SIZE                  8
+#define OCD_DS_INC_BIT                  24
+#define OCD_DS_BOZ_BIT                  25
+#define OCD_DS_DBA_BIT                  26
+#define OCD_DS_EXB_BIT                  27
+#define OCD_DS_NTBF_BIT                 28
+
+/* Bits in RWCS */
+#define OCD_RWCS_DV_BIT                 0
+#define OCD_RWCS_ERR_BIT                1
+#define OCD_RWCS_CNT_START              2
+#define OCD_RWCS_CNT_SIZE               14
+#define OCD_RWCS_CRC_BIT                19
+#define OCD_RWCS_NTBC_START             20
+#define OCD_RWCS_NTBC_SIZE              2
+#define OCD_RWCS_NTE_BIT                22
+#define OCD_RWCS_NTAP_BIT               23
+#define OCD_RWCS_WRAPPED_BIT            24
+#define OCD_RWCS_CCTRL_START            25
+#define OCD_RWCS_CCTRL_SIZE             2
+#define OCD_RWCS_SZ_START               27
+#define OCD_RWCS_SZ_SIZE                3
+#define OCD_RWCS_RW_BIT                 30
+#define OCD_RWCS_AC_BIT                 31
+
+/* Bits in RWA */
+#define OCD_RWA_RWA_START               0
+#define OCD_RWA_RWA_SIZE                32
+
+/* Bits in RWD */
+#define OCD_RWD_RWD_START               0
+#define OCD_RWD_RWD_SIZE                32
+
+/* Bits in WT */
+#define OCD_WT_DTE_START                20
+#define OCD_WT_DTE_SIZE                 3
+#define OCD_WT_DTS_START                23
+#define OCD_WT_DTS_SIZE                 3
+#define OCD_WT_PTE_START                26
+#define OCD_WT_PTE_SIZE                 3
+#define OCD_WT_PTS_START                29
+#define OCD_WT_PTS_SIZE                 3
+
+/* Bits in DTC */
+#define OCD_DTC_T0WP_BIT                0
+#define OCD_DTC_T1WP_BIT                1
+#define OCD_DTC_ASID0EN_BIT             2
+#define OCD_DTC_ASID0_START             3
+#define OCD_DTC_ASID0_SIZE              8
+#define OCD_DTC_ASID1EN_BIT             11
+#define OCD_DTC_ASID1_START             12
+#define OCD_DTC_ASID1_SIZE              8
+#define OCD_DTC_RWT1_START              28
+#define OCD_DTC_RWT1_SIZE               2
+#define OCD_DTC_RWT0_START              30
+#define OCD_DTC_RWT0_SIZE               2
+
+/* Bits in DTSA0 */
+#define OCD_DTSA0_DTSA_START            0
+#define OCD_DTSA0_DTSA_SIZE             32
+
+/* Bits in DTSA1 */
+#define OCD_DTSA1_DTSA_START            0
+#define OCD_DTSA1_DTSA_SIZE             32
+
+/* Bits in DTEA0 */
+#define OCD_DTEA0_DTEA_START            0
+#define OCD_DTEA0_DTEA_SIZE             32
+
+/* Bits in DTEA1 */
+#define OCD_DTEA1_DTEA_START            0
+#define OCD_DTEA1_DTEA_SIZE             32
+
+/* Bits in BWC0A */
+#define OCD_BWC0A_ASIDEN_BIT            0
+#define OCD_BWC0A_ASID_START            1
+#define OCD_BWC0A_ASID_SIZE             8
+#define OCD_BWC0A_EOC_BIT               14
+#define OCD_BWC0A_AME_BIT               25
+#define OCD_BWC0A_BWE_START             30
+#define OCD_BWC0A_BWE_SIZE              2
+
+/* Bits in BWC0B */
+#define OCD_BWC0B_ASIDEN_BIT            0
+#define OCD_BWC0B_ASID_START            1
+#define OCD_BWC0B_ASID_SIZE             8
+#define OCD_BWC0B_EOC_BIT               14
+#define OCD_BWC0B_AME_BIT               25
+#define OCD_BWC0B_BWE_START             30
+#define OCD_BWC0B_BWE_SIZE              2
+
+/* Bits in BWC1A */
+#define OCD_BWC1A_ASIDEN_BIT            0
+#define OCD_BWC1A_ASID_START            1
+#define OCD_BWC1A_ASID_SIZE             8
+#define OCD_BWC1A_EOC_BIT               14
+#define OCD_BWC1A_AME_BIT               25
+#define OCD_BWC1A_BWE_START             30
+#define OCD_BWC1A_BWE_SIZE              2
+
+/* Bits in BWC1B */
+#define OCD_BWC1B_ASIDEN_BIT            0
+#define OCD_BWC1B_ASID_START            1
+#define OCD_BWC1B_ASID_SIZE             8
+#define OCD_BWC1B_EOC_BIT               14
+#define OCD_BWC1B_AME_BIT               25
+#define OCD_BWC1B_BWE_START             30
+#define OCD_BWC1B_BWE_SIZE              2
+
+/* Bits in BWC2A */
+#define OCD_BWC2A_ASIDEN_BIT            0
+#define OCD_BWC2A_ASID_START            1
+#define OCD_BWC2A_ASID_SIZE             8
+#define OCD_BWC2A_EOC_BIT               14
+#define OCD_BWC2A_AMB_START             20
+#define OCD_BWC2A_AMB_SIZE              5
+#define OCD_BWC2A_AME_BIT               25
+#define OCD_BWC2A_BWE_START             30
+#define OCD_BWC2A_BWE_SIZE              2
+
+/* Bits in BWC2B */
+#define OCD_BWC2B_ASIDEN_BIT            0
+#define OCD_BWC2B_ASID_START            1
+#define OCD_BWC2B_ASID_SIZE             8
+#define OCD_BWC2B_EOC_BIT               14
+#define OCD_BWC2B_AME_BIT               25
+#define OCD_BWC2B_BWE_START             30
+#define OCD_BWC2B_BWE_SIZE              2
+
+/* Bits in BWC3A */
+#define OCD_BWC3A_ASIDEN_BIT            0
+#define OCD_BWC3A_ASID_START            1
+#define OCD_BWC3A_ASID_SIZE             8
+#define OCD_BWC3A_SIZE_START            9
+#define OCD_BWC3A_SIZE_SIZE             3
+#define OCD_BWC3A_EOC_BIT               14
+#define OCD_BWC3A_BWO_START             16
+#define OCD_BWC3A_BWO_SIZE              2
+#define OCD_BWC3A_BME_START             20
+#define OCD_BWC3A_BME_SIZE              4
+#define OCD_BWC3A_BRW_START             28
+#define OCD_BWC3A_BRW_SIZE              2
+#define OCD_BWC3A_BWE_START             30
+#define OCD_BWC3A_BWE_SIZE              2
+
+/* Bits in BWC3B */
+#define OCD_BWC3B_ASIDEN_BIT            0
+#define OCD_BWC3B_ASID_START            1
+#define OCD_BWC3B_ASID_SIZE             8
+#define OCD_BWC3B_SIZE_START            9
+#define OCD_BWC3B_SIZE_SIZE             3
+#define OCD_BWC3B_EOC_BIT               14
+#define OCD_BWC3B_BWO_START             16
+#define OCD_BWC3B_BWO_SIZE              2
+#define OCD_BWC3B_BME_START             20
+#define OCD_BWC3B_BME_SIZE              4
+#define OCD_BWC3B_BRW_START             28
+#define OCD_BWC3B_BRW_SIZE              2
+#define OCD_BWC3B_BWE_START             30
+#define OCD_BWC3B_BWE_SIZE              2
+
+/* Bits in BWA0A */
+#define OCD_BWA0A_BWA_START             0
+#define OCD_BWA0A_BWA_SIZE              32
+
+/* Bits in BWA0B */
+#define OCD_BWA0B_BWA_START             0
+#define OCD_BWA0B_BWA_SIZE              32
+
+/* Bits in BWA1A */
+#define OCD_BWA1A_BWA_START             0
+#define OCD_BWA1A_BWA_SIZE              32
+
+/* Bits in BWA1B */
+#define OCD_BWA1B_BWA_START             0
+#define OCD_BWA1B_BWA_SIZE              32
+
+/* Bits in BWA2A */
+#define OCD_BWA2A_BWA_START             0
+#define OCD_BWA2A_BWA_SIZE              32
+
+/* Bits in BWA2B */
+#define OCD_BWA2B_BWA_START             0
+#define OCD_BWA2B_BWA_SIZE              32
+
+/* Bits in BWA3A */
+#define OCD_BWA3A_BWA_START             0
+#define OCD_BWA3A_BWA_SIZE              32
+
+/* Bits in BWA3B */
+#define OCD_BWA3B_BWA_START             0
+#define OCD_BWA3B_BWA_SIZE              32
+
+/* Bits in NXCFG */
+#define OCD_NXCFG_NXARCH_START          0
+#define OCD_NXCFG_NXARCH_SIZE           4
+#define OCD_NXCFG_NXOCD_START           4
+#define OCD_NXCFG_NXOCD_SIZE            4
+#define OCD_NXCFG_NXPCB_START           8
+#define OCD_NXCFG_NXPCB_SIZE            4
+#define OCD_NXCFG_NXDB_START            12
+#define OCD_NXCFG_NXDB_SIZE             4
+#define OCD_NXCFG_MXMSEO_BIT            16
+#define OCD_NXCFG_NXMDO_START           17
+#define OCD_NXCFG_NXMDO_SIZE            4
+#define OCD_NXCFG_NXPT_BIT              21
+#define OCD_NXCFG_NXOT_BIT              22
+#define OCD_NXCFG_NXDWT_BIT             23
+#define OCD_NXCFG_NXDRT_BIT             24
+#define OCD_NXCFG_NXDTC_START           25
+#define OCD_NXCFG_NXDTC_SIZE            3
+#define OCD_NXCFG_NXDMA_BIT             28
+
+/* Bits in DINST */
+#define OCD_DINST_DINST_START           0
+#define OCD_DINST_DINST_SIZE            32
+
+/* Bits in CPUCM */
+#define OCD_CPUCM_BEM_BIT               1
+#define OCD_CPUCM_FEM_BIT               2
+#define OCD_CPUCM_REM_BIT               3
+#define OCD_CPUCM_IBEM_BIT              4
+#define OCD_CPUCM_IEEM_BIT              5
+
+/* Bits in DCCPU */
+#define OCD_DCCPU_DATA_START            0
+#define OCD_DCCPU_DATA_SIZE             32
+
+/* Bits in DCEMU */
+#define OCD_DCEMU_DATA_START            0
+#define OCD_DCEMU_DATA_SIZE             32
+
+/* Bits in DCSR */
+#define OCD_DCSR_CPUD_BIT               0
+#define OCD_DCSR_EMUD_BIT               1
+
+/* Bits in PID */
+#define OCD_PID_PROCESS_START           0
+#define OCD_PID_PROCESS_SIZE            32
+
+/* Bits in EPC0 */
+#define OCD_EPC0_RNG_START              0
+#define OCD_EPC0_RNG_SIZE               2
+#define OCD_EPC0_CE_BIT                 4
+#define OCD_EPC0_ECNT_START             16
+#define OCD_EPC0_ECNT_SIZE              16
+
+/* Bits in EPC1 */
+#define OCD_EPC1_RNG_START              0
+#define OCD_EPC1_RNG_SIZE               2
+#define OCD_EPC1_ATB_BIT                5
+#define OCD_EPC1_AM_BIT                 6
+
+/* Bits in EPC2 */
+#define OCD_EPC2_RNG_START              0
+#define OCD_EPC2_RNG_SIZE               2
+#define OCD_EPC2_DB_START               2
+#define OCD_EPC2_DB_SIZE                2
+
+/* Bits in EPC3 */
+#define OCD_EPC3_RNG_START              0
+#define OCD_EPC3_RNG_SIZE               2
+#define OCD_EPC3_DWE_BIT                2
+
+/* Bits in AXC */
+#define OCD_AXC_DIV_START               0
+#define OCD_AXC_DIV_SIZE                4
+#define OCD_AXC_AXE_BIT                 8
+#define OCD_AXC_AXS_BIT                 9
+#define OCD_AXC_DDR_BIT                 10
+#define OCD_AXC_LS_BIT                  11
+#define OCD_AXC_REX_BIT                 12
+#define OCD_AXC_REXTEN_BIT              13
+
+/* Constants for DC:EIC */
+#define OCD_EIC_PROGRAM_AND_DATA_TRACE  0
+#define OCD_EIC_BREAKPOINT              1
+#define OCD_EIC_NOP                     2
+
+/* Constants for DC:OVC */
+#define OCD_OVC_OVERRUN                 0
+#define OCD_OVC_DELAY_CPU_BTM           1
+#define OCD_OVC_DELAY_CPU_DTM           2
+#define OCD_OVC_DELAY_CPU_BTM_DTM       3
+
+/* Constants for DC:EOS */
+#define OCD_EOS_NOP                     0
+#define OCD_EOS_DEBUG_MODE              1
+#define OCD_EOS_BREAKPOINT_WATCHPOINT   2
+#define OCD_EOS_THQ                     3
+
+/* Constants for RWCS:NTBC */
+#define OCD_NTBC_OVERWRITE              0
+#define OCD_NTBC_DISABLE                1
+#define OCD_NTBC_BREAKPOINT             2
+
+/* Constants for RWCS:CCTRL */
+#define OCD_CCTRL_AUTO                  0
+#define OCD_CCTRL_CACHED                1
+#define OCD_CCTRL_UNCACHED              2
+
+/* Constants for RWCS:SZ */
+#define OCD_SZ_BYTE                     0
+#define OCD_SZ_HALFWORD                 1
+#define OCD_SZ_WORD                     2
+
+/* Constants for WT:PTS */
+#define OCD_PTS_DISABLED                0
+#define OCD_PTS_PROGRAM_0B              1
+#define OCD_PTS_PROGRAM_1A              2
+#define OCD_PTS_PROGRAM_1B              3
+#define OCD_PTS_PROGRAM_2A              4
+#define OCD_PTS_PROGRAM_2B              5
+#define OCD_PTS_DATA_3A                 6
+#define OCD_PTS_DATA_3B                 7
+
+/* Constants for DTC:RWT1 */
+#define OCD_RWT1_NO_TRACE               0
+#define OCD_RWT1_DATA_READ              1
+#define OCD_RWT1_DATA_WRITE             2
+#define OCD_RWT1_DATA_READ_WRITE        3
+
+/* Constants for DTC:RWT0 */
+#define OCD_RWT0_NO_TRACE               0
+#define OCD_RWT0_DATA_READ              1
+#define OCD_RWT0_DATA_WRITE             2
+#define OCD_RWT0_DATA_READ_WRITE        3
+
+/* Constants for BWC0A:BWE */
+#define OCD_BWE_DISABLED                0
+#define OCD_BWE_BREAKPOINT_ENABLED      1
+#define OCD_BWE_WATCHPOINT_ENABLED      3
+
+/* Constants for BWC0B:BWE */
+#define OCD_BWE_DISABLED                0
+#define OCD_BWE_BREAKPOINT_ENABLED      1
+#define OCD_BWE_WATCHPOINT_ENABLED      3
+
+/* Constants for BWC1A:BWE */
+#define OCD_BWE_DISABLED                0
+#define OCD_BWE_BREAKPOINT_ENABLED      1
+#define OCD_BWE_WATCHPOINT_ENABLED      3
+
+/* Constants for BWC1B:BWE */
+#define OCD_BWE_DISABLED                0
+#define OCD_BWE_BREAKPOINT_ENABLED      1
+#define OCD_BWE_WATCHPOINT_ENABLED      3
+
+/* Constants for BWC2A:BWE */
+#define OCD_BWE_DISABLED                0
+#define OCD_BWE_BREAKPOINT_ENABLED      1
+#define OCD_BWE_WATCHPOINT_ENABLED      3
+
+/* Constants for BWC2B:BWE */
+#define OCD_BWE_DISABLED                0
+#define OCD_BWE_BREAKPOINT_ENABLED      1
+#define OCD_BWE_WATCHPOINT_ENABLED      3
+
+/* Constants for BWC3A:SIZE */
+#define OCD_SIZE_BYTE_ACCESS            4
+#define OCD_SIZE_HALFWORD_ACCESS        5
+#define OCD_SIZE_WORD_ACCESS            6
+#define OCD_SIZE_DOUBLE_WORD_ACCESS     7
+
+/* Constants for BWC3A:BRW */
+#define OCD_BRW_READ_BREAK              0
+#define OCD_BRW_WRITE_BREAK             1
+#define OCD_BRW_ANY_ACCES_BREAK         2
+
+/* Constants for BWC3A:BWE */
+#define OCD_BWE_DISABLED                0
+#define OCD_BWE_BREAKPOINT_ENABLED      1
+#define OCD_BWE_WATCHPOINT_ENABLED      3
+
+/* Constants for BWC3B:SIZE */
+#define OCD_SIZE_BYTE_ACCESS            4
+#define OCD_SIZE_HALFWORD_ACCESS        5
+#define OCD_SIZE_WORD_ACCESS            6
+#define OCD_SIZE_DOUBLE_WORD_ACCESS     7
+
+/* Constants for BWC3B:BRW */
+#define OCD_BRW_READ_BREAK              0
+#define OCD_BRW_WRITE_BREAK             1
+#define OCD_BRW_ANY_ACCES_BREAK         2
+
+/* Constants for BWC3B:BWE */
+#define OCD_BWE_DISABLED                0
+#define OCD_BWE_BREAKPOINT_ENABLED      1
+#define OCD_BWE_WATCHPOINT_ENABLED      3
+
+/* Constants for EPC0:RNG */
+#define OCD_RNG_DISABLED                0
+#define OCD_RNG_EXCLUSIVE               1
+#define OCD_RNG_INCLUSIVE               2
+
+/* Constants for EPC1:RNG */
+#define OCD_RNG_DISABLED                0
+#define OCD_RNG_EXCLUSIVE               1
+#define OCD_RNG_INCLUSIVE               2
+
+/* Constants for EPC2:RNG */
+#define OCD_RNG_DISABLED                0
+#define OCD_RNG_EXCLUSIVE               1
+#define OCD_RNG_INCLUSIVE               2
+
+/* Constants for EPC2:DB */
+#define OCD_DB_DISABLED                 0
+#define OCD_DB_CHAINED_B                1
+#define OCD_DB_CHAINED_A                2
+#define OCD_DB_AHAINED_A_AND_B          3
+
+/* Constants for EPC3:RNG */
+#define OCD_RNG_DISABLED                0
+#define OCD_RNG_EXCLUSIVE               1
+#define OCD_RNG_INCLUSIVE               2
+
+#ifndef __ASSEMBLER__
+
+/* Register access macros */
+static inline unsigned long __ocd_read(unsigned int reg)
+{
+        return __builtin_mfdr(reg);
+}
+
+static inline void __ocd_write(unsigned int reg, unsigned long value)
+{
+        __builtin_mtdr(reg, value);
+}
+
+#define ocd_read(reg)                   __ocd_read(OCD_##reg)
+#define ocd_write(reg, value)           __ocd_write(OCD_##reg, value)
+
+#endif /* !__ASSEMBLER__ */
 
 #endif /* __ASM_AVR32_OCD_H */
diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h
index 6a64833756a6..a52576b25afe 100644
--- a/include/asm-avr32/processor.h
+++ b/include/asm-avr32/processor.h
@@ -139,6 +139,9 @@ extern void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl);
 extern void show_stack_log_lvl(struct task_struct *tsk, unsigned long sp,
                                struct pt_regs *regs, const char *log_lvl);
 
+#define task_pt_regs(p) \
+        ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
+
 #define KSTK_EIP(tsk)   ((tsk)->thread.cpu_context.pc)
 #define KSTK_ESP(tsk)   ((tsk)->thread.cpu_context.ksp)
 
diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h
index 60f0f19a81f1..8c5dba5e33df 100644
--- a/include/asm-avr32/ptrace.h
+++ b/include/asm-avr32/ptrace.h
@@ -14,8 +14,7 @@
 /*
  * Status Register bits
  */
-#define SR_H            0x40000000
-#define SR_R            0x20000000
+#define SR_H            0x20000000
 #define SR_J            0x10000000
 #define SR_DM           0x08000000
 #define SR_D            0x04000000
@@ -35,8 +34,7 @@
 #define SR_I0M          0x00020000
 #define SR_GM           0x00010000
 
-#define SR_H_BIT        30
-#define SR_R_BIT        29
+#define SR_H_BIT        29
 #define SR_J_BIT        28
 #define SR_DM_BIT       27
 #define SR_D_BIT        26
diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h
index dd21182b60e0..d4e0950170ca 100644
--- a/include/asm-avr32/sysreg.h
+++ b/include/asm-avr32/sysreg.h
@@ -93,6 +93,8 @@
 #define SYSREG_I3M_SIZE                         1
 #define SYSREG_EM_OFFSET                        21
 #define SYSREG_EM_SIZE                          1
+#define SYSREG_MODE_OFFSET                      22
+#define SYSREG_MODE_SIZE                        3
 #define SYSREG_M0_OFFSET                        22
 #define SYSREG_M0_SIZE                          1
 #define SYSREG_M1_OFFSET                        23
diff --git a/include/asm-avr32/system.h b/include/asm-avr32/system.h
index dc2d527cef41..c600cc15cbcb 100644
--- a/include/asm-avr32/system.h
+++ b/include/asm-avr32/system.h
@@ -35,8 +35,8 @@
 #include <asm/ocd.h>
 #define finish_arch_switch(prev)                        \
         do {                                            \
-                __mtdr(DBGREG_PID, prev->pid);          \
-                __mtdr(DBGREG_PID, current->pid);       \
+                ocd_write(PID, prev->pid);              \
+                ocd_write(PID, current->pid);           \
         } while(0)
 #endif
 
diff --git a/include/asm-avr32/thread_info.h b/include/asm-avr32/thread_info.h
index 17dacf3f36d3..184b574289b4 100644
--- a/include/asm-avr32/thread_info.h
+++ b/include/asm-avr32/thread_info.h
@@ -25,6 +25,11 @@ struct thread_info {
         unsigned long           flags;          /* low level flags */
         __u32                   cpu;
         __s32                   preempt_count;  /* 0 => preemptable, <0 => BUG */
+        __u32                   rar_saved;      /* return address... */
+        __u32                   rsr_saved;      /* ...and status register
+                                                   saved by debug handler
+                                                   when setting up
+                                                   trampoline */
         struct restart_block    restart_block;
         __u8                    supervisor_stack[0];
 };
@@ -78,8 +83,8 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NEED_RESCHED        2       /* rescheduling necessary */
 #define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
                                            TIF_NEED_RESCHED */
-#define TIF_BREAKPOINT          4       /* true if we should break after return */
-#define TIF_SINGLE_STEP         5       /* single step after next break */
+#define TIF_BREAKPOINT          4       /* enter monitor mode on return */
+#define TIF_SINGLE_STEP         5       /* single step in progress */
 #define TIF_MEMDIE              6
 #define TIF_RESTORE_SIGMASK     7       /* restore signal mask in do_signal */
 #define TIF_CPU_GOING_TO_SLEEP  8       /* CPU is entering sleep 0 mode */
@@ -89,18 +94,24 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
-#define _TIF_BREAKPOINT         (1 << TIF_BREAKPOINT)
 #define _TIF_SINGLE_STEP        (1 << TIF_SINGLE_STEP)
 #define _TIF_MEMDIE             (1 << TIF_MEMDIE)
 #define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
 #define _TIF_CPU_GOING_TO_SLEEP (1 << TIF_CPU_GOING_TO_SLEEP)
 
-/* XXX: These two masks must never span more than 16 bits! */
+/* Note: The masks below must never span more than 16 bits! */
+
 /* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK          0x0000013e
+#define _TIF_WORK_MASK                          \
+        ((1 << TIF_SIGPENDING)                  \
+         | (1 << TIF_NEED_RESCHED)              \
+         | (1 << TIF_POLLING_NRFLAG)            \
+         | (1 << TIF_BREAKPOINT)                \
+         | (1 << TIF_RESTORE_SIGMASK))
+
 /* work to do on any return to userspace */
-#define _TIF_ALLWORK_MASK       0x0000013f
+#define _TIF_ALLWORK_MASK       (_TIF_WORK_MASK | (1 << TIF_SYSCALL_TRACE))
 /* work to do on return from debug mode */
-#define _TIF_DBGWORK_MASK       0x0000017e
+#define _TIF_DBGWORK_MASK       (_TIF_WORK_MASK & ~(1 << TIF_BREAKPOINT))
 
 #endif /* __ASM_AVR32_THREAD_INFO_H */
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 0212e180b90e..39bdd86871cf 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -50,8 +50,8 @@ extern unsigned long get_sclk(void);
 extern unsigned long sclk_to_usecs(unsigned long sclk);
 extern unsigned long usecs_to_sclk(unsigned long usecs);
 
-extern void dump_thread(struct pt_regs *regs, struct user *dump);
-extern void dump_bfin_regs(struct pt_regs *fp, void *retaddr);
+extern void dump_bfin_process(struct pt_regs *regs);
+extern void dump_bfin_mem(void *retaddr);
 extern void dump_bfin_trace_buffer(void);
 
 extern int init_arch_irq(void);
@@ -63,6 +63,7 @@ extern void bfin_dcache_init(void);
 extern int read_iloc(void);
 extern int bfin_console_init(void);
 extern asmlinkage void lower_to_irq14(void);
+extern asmlinkage void bfin_return_from_exception(void);
 extern void init_exception_vectors(void);
 extern void init_dma(void);
 extern void program_IAR(void);
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h
index f617d8765451..1a0b57f6a3d4 100644
--- a/include/asm-blackfin/bfin5xx_spi.h
+++ b/include/asm-blackfin/bfin5xx_spi.h
@@ -152,6 +152,7 @@
 struct bfin5xx_spi_master {
         u16 num_chipselect;
         u8 enable_dma;
+        u16 pin_req[4];
 };
 
 /* spi_board_info.controller_data for SPI slave devices,
@@ -162,7 +163,7 @@ struct bfin5xx_spi_chip {
         u8 enable_dma;
         u8 bits_per_word;
         u8 cs_change_per_word;
-        u8 cs_chg_udelay;
+        u16 cs_chg_udelay; /* Some devices require 16-bit delays */
 };
 
 #endif /* _SPI_CHANNEL_H_ */
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index bec6ecdf1bdb..c4d0596e8e9f 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -27,6 +27,9 @@
  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#ifndef __ASM_CPLBINIT_H__
+#define __ASM_CPLBINIT_H__
+
 #include <asm/blackfin.h>
 #include <asm/cplb.h>
 
@@ -57,8 +60,8 @@ struct cplb_tab {
         u16 size;
 };
 
-extern u_long icplb_table[MAX_CPLBS+1];
-extern u_long dcplb_table[MAX_CPLBS+1];
+extern u_long icplb_table[];
+extern u_long dcplb_table[];
 
 /* Till here we are discussing about the static memory management model.
  * However, the operating envoronments commonly define more CPLB
@@ -69,28 +72,16 @@ extern u_long dcplb_table[MAX_CPLBS+1];
  * This is how Page descriptor Table is implemented in uClinux/Blackfin.
  */
 
-#ifdef CONFIG_CPLB_SWITCH_TAB_L1
-extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
-extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
-
-#ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
-extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
-#endif /* CONFIG_CPLB_INFO */
-
-#else
-
-extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
-extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
-
+extern u_long ipdt_table[];
+extern u_long dpdt_table[];
 #ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
-extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
-#endif /* CONFIG_CPLB_INFO */
-
-#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
+extern u_long ipdt_swapcount_table[];
+extern u_long dpdt_swapcount_table[];
+#endif
 
 extern unsigned long reserved_mem_dcache_on;
 extern unsigned long reserved_mem_icache_on;
 
 extern void generate_cpl_tables(void);
+
+#endif
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index 52e7a10d7ff8..473a8113277f 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -1,29 +1,47 @@
-#ifndef _BLACKFIN_DELAY_H
-#define _BLACKFIN_DELAY_H
-
-static inline void __delay(unsigned long loops)
-{
-
-/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers,
-   uncomment this as soon those are implemented */
 /*
-      __asm__ __volatile__ (  "\t LSETUP (1f,1f) LC0= %0\n\t"
-                              "1:\t NOP;\n\t"
-                              : :"a" (loops)
-                              : "LT0","LB0","LC0");
+ * delay.h - delay functions
+ *
+ * Copyright (c) 2004-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_DELAY_H__
+#define __ASM_DELAY_H__
 
-*/
+#include <asm/mach/anomaly.h>
 
-        __asm__ __volatile__("[--SP] = LC0;\n\t"
-                             "[--SP] = LT0;\n\t"
-                             "[--SP] = LB0;\n\t"
-                             "LSETUP (1f,1f) LC0 = %0;\n\t"
-                             "1:\t NOP;\n\t"
-                             "LB0 = [SP++];\n\t"
-                                "LT0 = [SP++];\n\t"
-                                "LC0 = [SP++];\n"
-                                :
-                                :"a" (loops));
+static inline void __delay(unsigned long loops)
+{
+        if (ANOMALY_05000312) {
+                /* Interrupted loads to loop registers -> bad */
+                unsigned long tmp;
+                __asm__ __volatile__(
+                        "[--SP] = LC0;"
+                        "[--SP] = LT0;"
+                        "[--SP] = LB0;"
+                        "LSETUP (1f,1f) LC0 = %1;"
+                        "1: NOP;"
+                        /* We take advantage of the fact that LC0 is 0 at
+                         * the end of the loop.  Otherwise we'd need some
+                         * NOPs after the CLI here.
+                         */
+                        "CLI %0;"
+                        "LB0 = [SP++];"
+                        "LT0 = [SP++];"
+                        "LC0 = [SP++];"
+                        "STI %0;"
+                        : "=d" (tmp)
+                        : "a" (loops)
+                );
+        } else
+                __asm__ __volatile__ (
+                        "LSETUP(1f, 1f) LC0 = %0;"
+                        "1: NOP;"
+                        :
+                        : "a" (loops)
+                        : "LT0", "LB0", "LC0"
+                );
 }
 
 #include <linux/param.h>        /* needed for HZ */
@@ -41,4 +59,4 @@ static inline void udelay(unsigned long usecs)
         __delay(usecs * loops_per_jiffy / (1000000 / HZ));
 }
 
-#endif                          /* defined(_BLACKFIN_DELAY_H) */
+#endif
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index d1d2e6be3b59..1601d62f39a5 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -122,6 +122,7 @@ extern void outsl(unsigned long port, const void *addr, unsigned long count);
 extern void insb(unsigned long port, void *addr, unsigned long count);
 extern void insw(unsigned long port, void *addr, unsigned long count);
 extern void insl(unsigned long port, void *addr, unsigned long count);
+extern void insl_16(unsigned long port, void *addr, unsigned long count);
 
 extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
 extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
index 304f5bcfebe4..4e2b3f2020e5 100644
--- a/include/asm-blackfin/mach-bf527/irq.h
+++ b/include/asm-blackfin/mach-bf527/irq.h
@@ -176,11 +176,7 @@
 
 #define GPIO_IRQ_BASE   IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PH15+1)
-#else
-#define NR_IRQS     (SYS_IRQS+1)
-#endif
 
 #define IVG7            7
 #define IVG8            8
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
index c5aa20102b24..193082deaa4e 100644
--- a/include/asm-blackfin/mach-bf527/mem_map.h
+++ b/include/asm-blackfin/mach-bf527/mem_map.h
@@ -47,6 +47,7 @@
 /* Boot ROM Memory */
 
 #define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x8000
 
 /* Level 1 Memory */
 
@@ -90,9 +91,7 @@
 
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif                          /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 452fb825d891..832e6f6122da 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -130,11 +130,7 @@ Core        Emulation               **
 
 #define GPIO_IRQ_BASE           IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS         (IRQ_PF15+1)
-#else
-#define NR_IRQS         SYS_IRQS
-#endif
 
 #define IVG7                    7
 #define IVG8                    8
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index 94d8c4062eb7..bd30b6f3be00 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -1,4 +1,3 @@
-
 /*
  * File:         include/asm-blackfin/mach-bf533/mem_map.h
  * Based on:
@@ -48,6 +47,7 @@
 /* Boot ROM Memory */
 
 #define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x400
 
 /* Level 1 Memory */
 
@@ -160,9 +160,7 @@
 
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
index b88d7a03ee3e..137f4884acfe 100644
--- a/include/asm-blackfin/mach-bf533/portmux.h
+++ b/include/asm-blackfin/mach-bf533/portmux.h
@@ -42,7 +42,7 @@
 #define P_SPORT0_DRPRI  (P_DONTCARE)
 
 #define P_SPI0_MOSI     (P_DONTCARE)
-#define P_SPI0_MIS0     (P_DONTCARE)
+#define P_SPI0_MISO     (P_DONTCARE)
 #define P_SPI0_SCK      (P_DONTCARE)
 #define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
 #define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index 36c44bc1a917..be6f2ff77f31 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -162,11 +162,7 @@ Core        Emulation               **
 
 #define GPIO_IRQ_BASE   IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PH15+1)
-#else
-#define NR_IRQS     (IRQ_UART1_ERROR+1)
-#endif
 
 #define IVG7            7
 #define IVG8            8
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 18759e38eaae..5c6726d6f3b1 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -47,6 +47,7 @@
 /* Boot ROM Memory */
 
 #define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x800
 
 /* Level 1 Memory */
 
@@ -167,9 +168,7 @@
 
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif                          /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 7e6d349beb08..e748588e8930 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -106,24 +106,22 @@
 
 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
 
-#ifdef CONFIG_BF542
-#define CPU "BF542"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF544
-#define CPU "BF544"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF548
-#define CPU "BF548"
-#define CPUID 0x027c6000
-#endif
-#ifdef CONFIG_BF549
-#define CPU "BF549"
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
+#if defined(CONFIG_BF542)
+# define CPU   "BF542"
+# define CPUID 0x027c8000
+#elif defined(CONFIG_BF544)
+# define CPU "BF544"
+# define CPUID 0x027c8000
+#elif defined(CONFIG_BF547)
+# define CPU "BF547"
+#elif defined(CONFIG_BF548)
+# define CPU "BF548"
+# define CPUID 0x027c6000
+#elif defined(CONFIG_BF549)
+# define CPU "BF549"
+#else
+# define CPU "UNKNOWN"
+# define CPUID 0x0
 #endif
 
 #endif  /* __MACH_BF48_H__  */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index 760307e34b9e..b8b9870e2697 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -645,7 +645,7 @@
 
 /* Bit masks for HOST_STATUS */
 
-#define                     READY  0x1        /* DMA Ready */
+#define                 DMA_READY  0x1        /* DMA Ready */
 #define                  FIFOFULL  0x2        /* FIFO Full */
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
 #define                  COMPLETE  0x8        /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index 70af33c963b0..ecbca952985c 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1007,7 +1007,7 @@
 
 /* Bit masks for HOST_STATUS */
 
-#define                     READY  0x1        /* DMA Ready */
+#define                 DMA_READY  0x1        /* DMA Ready */
 #define                  FIFOFULL  0x2        /* FIFO Full */
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
 #define                  COMPLETE  0x8        /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index da979cb62f7d..319a48590c9c 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -1644,8 +1644,25 @@
 #define                   RESTART  0x20       /* Work Unit Transitions */
 #define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
 #define                     DI_EN  0x80       /* Data Interrupt Enable */
+
 #define                    NDSIZE  0xf00      /* Flex Descriptor Size */
+#define                  NDSIZE_0 0x0000      /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define                  NDSIZE_1 0x0100      /* Next Descriptor Size = 1 */
+#define                  NDSIZE_2 0x0200      /* Next Descriptor Size = 2 */
+#define                  NDSIZE_3 0x0300      /* Next Descriptor Size = 3 */
+#define                  NDSIZE_4 0x0400      /* Next Descriptor Size = 4 */
+#define                  NDSIZE_5 0x0500      /* Next Descriptor Size = 5 */
+#define                  NDSIZE_6 0x0600      /* Next Descriptor Size = 6 */
+#define                  NDSIZE_7 0x0700      /* Next Descriptor Size = 7 */
+#define                  NDSIZE_8 0x0800      /* Next Descriptor Size = 8 */
+#define                  NDSIZE_9 0x0900      /* Next Descriptor Size = 9 */
+
 #define                   DMAFLOW  0xf000     /* Next Operation */
+#define              DMAFLOW_STOP  0x0000     /* Stop Mode */
+#define              DMAFLOW_AUTO  0x1000     /* Autobuffer Mode */
+#define             DMAFLOW_ARRAY  0x4000     /* Descriptor Array Mode */
+#define             DMAFLOW_SMALL  0x6000     /* Small Model Descriptor List Mode */
+#define             DMAFLOW_LARGE  0x7000     /* Large Model Descriptor List Mode */
 
 /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
 
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 3b08cf9bd6f3..9fb7bc5399a8 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -338,11 +338,7 @@ Events         (highest priority)  EMU         0
 
 #define GPIO_IRQ_BASE   IRQ_PA0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PJ15+1)
-#else
-#define NR_IRQS     (SYS_IRQS+1)
-#endif
 
 /* For compatibility reasons with existing code */
 
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index ec1597e31831..f99f47bc3a07 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -47,6 +47,12 @@
 /* Boot ROM Memory */
 
 #define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x1000
+
+/* L1 Instruction ROM */
+
+#define L1_ROM_START            0xFFA14000
+#define L1_ROM_LENGTH           0x10000
 
 /* Level 1 Memory */
 
@@ -87,11 +93,19 @@
 #define BFIN_DSUPBANKS  0
 #endif /*CONFIG_BFIN_DCACHE*/
 
+/* Level 2 Memory */
+#if !defined(CONFIG_BF542)
+# define L2_START          0xFEB00000
+# if defined(CONFIG_BF544)
+#  define L2_LENGTH        0x10000
+# else
+#  define L2_LENGTH        0x20000
+# endif
+#endif
+
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF54x)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 17e1d5dcef02..3ef9e5f36136 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -33,25 +33,6 @@
 #define SUPPORTED_REVID         0x3
 
 #define OFFSET_(x) ((x) & 0x0000FFFF)
-#define L1_ISRAM                0xFFA00000
-#define L1_ISRAM_END            0xFFA04000
-#define DATA_BANKA_SRAM         0xFF800000
-#define DATA_BANKA_SRAM_END     0xFF804000
-#define DATA_BANKB_SRAM         0xFF900000
-#define DATA_BANKB_SRAM_END     0xFF904000
-#define L1_DSRAMA               0xFF800000
-#define L1_DSRAMA_END           0xFF804000
-#define L1_DSRAMB               0xFF900000
-#define L1_DSRAMB_END           0xFF904000
-#define L2_SRAM                 0xFEB00000
-#define L2_SRAM_END             0xFEB20000
-#define AMB_FLASH               0x20000000
-#define AMB_FLASH_END           0x21000000
-#define AMB_FLASH_LENGTH        0x01000000
-#define L1_ISRAM_LENGTH         0x4000
-#define L1_DSRAMA_LENGTH        0x4000
-#define L1_DSRAMB_LENGTH        0x4000
-#define L2_SRAM_LENGTH          0x20000
 
 /*some misc defines*/
 #define IMASK_IVG15             0x8000
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 7945e8a3a841..c3c0eb13c819 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,7 @@
 /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
 #define SWRST                   SICA_SWRST
 #define SYSCR                   SICA_SYSCR
+#define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
 #define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
 #define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
 #define RESET_SOFTWARE          (SWRST_OCCURRED)
@@ -877,12 +878,14 @@
 #define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
 /* SWRST Mask */
-#define SYSTEM_RESET           0x00000007       /* Initiates a system software reset */
-#define SWRST_DBL_FAULT_B      0x00000800       /* SWRST Core B Double Fault */
-#define SWRST_DBL_FAULT_A      0x00001000       /* SWRST Core A Double Fault */
-#define SWRST_WDT_B                    0x00002000       /* SWRST Watchdog B */
-#define SWRST_WDT_A                    0x00004000       /* SWRST Watchdog A */
-#define SWRST_OCCURRED         0x00008000       /* SWRST Status */
+#define SYSTEM_RESET           0x0007   /* Initiates a system software reset */
+#define DOUBLE_FAULT_A         0x0008   /* Core A Double Fault Causes Reset */
+#define DOUBLE_FAULT_B         0x0010   /* Core B Double Fault Causes Reset */
+#define SWRST_DBL_FAULT_A      0x0800   /* SWRST Core A Double Fault */
+#define SWRST_DBL_FAULT_B      0x1000   /* SWRST Core B Double Fault */
+#define SWRST_WDT_B                    0x2000   /* SWRST Watchdog B */
+#define SWRST_WDT_A                    0x4000   /* SWRST Watchdog A */
+#define SWRST_OCCURRED         0x8000   /* SWRST Status */
 
 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
 
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 12789927db3d..83f0383957d2 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -291,11 +291,7 @@
 
 #define GPIO_IRQ_BASE           IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS                 (IRQ_PF47 + 1)
-#else
-#define NR_IRQS                 SYS_IRQS
-#endif
 
 #define IVG7                    7
 #define IVG8                    8
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index f7ac09cf2c3d..c26d8486cc4b 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -19,6 +19,11 @@
 #define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
 #define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
 
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x800
+
 /* Level 1 Memory */
 
 #ifdef CONFIG_BFIN_ICACHE
@@ -67,9 +72,7 @@
 
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF561)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index c1d8c4a78fcf..e8967f6124f7 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -46,7 +46,7 @@
 #endif
 
 #define bfin_read8(addr) ({ \
-        uint8_t __v; \
+        uint32_t __v; \
         __asm__ __volatile__( \
                 NOP_PAD_ANOMALY_05000198 \
                 "%0 = b[%1] (z);" \
@@ -56,7 +56,7 @@
         __v; })
 
 #define bfin_read16(addr) ({ \
-        uint16_t __v; \
+        uint32_t __v; \
         __asm__ __volatile__( \
                 NOP_PAD_ANOMALY_05000198 \
                 "%0 = w[%1] (z);" \
@@ -80,7 +80,7 @@
                 NOP_PAD_ANOMALY_05000198 \
                 "b[%0] = %1;" \
                 : \
-                : "a" (addr), "d" (val) \
+                : "a" (addr), "d" ((uint8_t)(val)) \
                 : "memory" \
         )
 
@@ -89,7 +89,7 @@
                 NOP_PAD_ANOMALY_05000198 \
                 "w[%0] = %1;" \
                 : \
-                : "a" (addr), "d" (val) \
+                : "a" (addr), "d" ((uint16_t)(val)) \
                 : "memory" \
         )
 
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
index 3b671d5fd70d..cbaff24b4b25 100644
--- a/include/asm-blackfin/page_offset.h
+++ b/include/asm-blackfin/page_offset.h
@@ -1,6 +1,6 @@
 
 /* This handles the memory map.. */
 
-#ifdef CONFIG_BFIN
+#ifdef CONFIG_BLACKFIN
 #define PAGE_OFFSET_RAW         0x00000000
 #endif
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index e8ada91ab002..321f4d96e4ae 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -1,6 +1,8 @@
 #ifndef _BLACKFIN_STRING_H_
 #define _BLACKFIN_STRING_H_
 
+#include <linux/types.h>
+
 #ifdef __KERNEL__               /* only set these up for kernel code */
 
 #define __HAVE_ARCH_STRCPY
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index fe365b1b7ca8..ee1cbf73a9ab 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -48,28 +48,80 @@
 
 #ifndef __ASSEMBLY__
 
-#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3 "External Memory Addressing Error\n"
-#define HWC_x12 "Performance Monitor Overflow\n"
-#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default "Reserved\n"
-
-#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n"
-#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n"
-#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n"
-#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n"
-#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n"
-#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n"
+#define HWC_x2(level) \
+        "System MMR Error\n" \
+        level " - An error occurred due to an invalid access to an System MMR location\n" \
+        level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
+        level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
+#define HWC_x3(level) \
+        "External Memory Addressing Error\n"
+#define HWC_x12(level) \
+        "Performance Monitor Overflow\n"
+#define HWC_x18(level) \
+        "RAISE 5 instruction\n" \
+        level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
+#define HWC_default(level) \
+         "Reserved\n"
+#define EXC_0x03(level) \
+        "Application stack overflow\n" \
+        level " - Please increase the stack size of the application using elf2flt -s option,\n" \
+        level "   and/or reduce the stack use of the application.\n"
+#define EXC_0x10(level) \
+        "Single step\n" \
+        level " - When the processor is in single step mode, every instruction\n" \
+        level "   generates an exception. Primarily used for debugging.\n"
+#define EXC_0x11(level) \
+        "Exception caused by a trace buffer full condition\n" \
+        level " - The processor takes this exception when the trace\n" \
+        level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
+#define EXC_0x21(level) \
+        "Undefined instruction\n" \
+        level " - May be used to emulate instructions that are not defined for\n" \
+        level "   a particular processor implementation.\n"
+#define EXC_0x22(level) \
+        "Illegal instruction combination\n" \
+        level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
+        level "   Processor Instruction Set Reference.\n"
+#define EXC_0x23(level) \
+        "Data access CPLB protection violation\n" \
+        level " - Attempted read or write to Supervisor resource,\n" \
+        level "   or illegal data memory access. \n"
+#define EXC_0x24(level) \
+        "Data access misaligned address violation\n" \
+        level " - Attempted misaligned data memory or data cache access.\n"
+#define EXC_0x25(level) \
+        "Unrecoverable event\n" \
+        level " - For example, an exception generated while processing a previous exception.\n"
+#define EXC_0x26(level) \
+        "Data access CPLB miss\n" \
+        level " - Used by the MMU to signal a CPLB miss on a data access.\n"
+#define EXC_0x27(level) \
+        "Data access multiple CPLB hits\n" \
+        level " - More than one CPLB entry matches data fetch address.\n"
+#define EXC_0x28(level) \
+        "Program Sequencer Exception caused by an emulation watchpoint match\n" \
+        level " - There is a watchpoint match, and one of the EMUSW\n" \
+        level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
+#define EXC_0x2A(level) \
+        "Instruction fetch misaligned address violation\n" \
+        level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
+        level "   exception, the return address provided in RETX is the destination address which is\n" \
+        level "   misaligned, rather than the address of the offending instruction.\n"
+#define EXC_0x2B(level) \
+        "CPLB protection violation\n" \
+        level " - Illegal instruction fetch access (memory protection violation).\n"
+#define EXC_0x2C(level) \
+        "Instruction fetch CPLB miss\n" \
+        level " - CPLB miss on an instruction fetch.\n"
+#define EXC_0x2D(level) \
+        "Instruction fetch multiple CPLB hits\n" \
+        level " - More than one CPLB entry matches instruction fetch address.\n"
+#define EXC_0x2E(level) \
+        "Illegal use of supervisor resource\n" \
+        level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
+        level "   Supervisor resources are registers and instructions that are reserved\n" \
+        level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
+        level "   only instructions.\n"
 
 #endif                          /* __ASSEMBLY__ */
 #endif                          /* _BFIN_TRAPS_H */
diff --git a/include/asm-generic/resource.h b/include/asm-generic/resource.h
index cfe3692b23e5..a4a22cc35898 100644
--- a/include/asm-generic/resource.h
+++ b/include/asm-generic/resource.h
@@ -12,7 +12,7 @@
  *   then it defines them prior including asm-generic/resource.h. )
  */
 
-#define RLIMIT_CPU              0       /* CPU time in ms */
+#define RLIMIT_CPU              0       /* CPU time in sec */
 #define RLIMIT_FSIZE            1       /* Maximum filesize */
 #define RLIMIT_DATA             2       /* max data size */
 #define RLIMIT_STACK            3       /* max stack size */
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h
index 49730ffbbae4..81bcd5e51789 100644
--- a/include/asm-ia64/acpi.h
+++ b/include/asm-ia64/acpi.h
@@ -94,6 +94,7 @@ ia64_acpi_release_global_lock (unsigned int *lock)
 #define acpi_noirq 0    /* ACPI always enabled on IA64 */
 #define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */
 #define acpi_strict 1   /* no ACPI spec workarounds on IA64 */
+#define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */
 static inline void disable_acpi(void) { }
 
 const char *acpi_get_sysname (void);
diff --git a/include/asm-m32r/thread_info.h b/include/asm-m32r/thread_info.h
index c039820dba7c..1effcd0f5e63 100644
--- a/include/asm-m32r/thread_info.h
+++ b/include/asm-m32r/thread_info.h
@@ -149,16 +149,21 @@ static inline unsigned int get_thread_fault_code(void)
 #define TIF_NEED_RESCHED        2       /* rescheduling necessary */
 #define TIF_SINGLESTEP          3       /* restore singlestep on return to user mode */
 #define TIF_IRET                4       /* return with iret */
-#define TIF_POLLING_NRFLAG      16      /* true if poll_idle() is polling TIF_NEED_RESCHED */
-                                        /* 31..28 fault code */
-#define TIF_MEMDIE              17
+#define TIF_RESTORE_SIGMASK     8       /* restore signal mask in do_signal() */
+#define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
+#define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
+#define TIF_MEMDIE              18      /* OOM killer killed process */
+#define TIF_FREEZE              19      /* is freezing for suspend */
 
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
 #define _TIF_IRET               (1<<TIF_IRET)
+#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE             (1<<TIF_FREEZE)
 
 #define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
 #define _TIF_ALLWORK_MASK       0x0000FFFF      /* work to do on any return to u-space */
diff --git a/include/asm-m32r/unistd.h b/include/asm-m32r/unistd.h
index cbbd53762ea6..f467eac9ba70 100644
--- a/include/asm-m32r/unistd.h
+++ b/include/asm-m32r/unistd.h
@@ -290,10 +290,50 @@
 #define __NR_mq_getsetattr      (__NR_mq_open+5)
 #define __NR_kexec_load         283
 #define __NR_waitid             284
+/* 285 is unused */
+#define __NR_add_key            286
+#define __NR_request_key        287
+#define __NR_keyctl             288
+#define __NR_ioprio_set         289
+#define __NR_ioprio_get         290
+#define __NR_inotify_init       291
+#define __NR_inotify_add_watch  292
+#define __NR_inotify_rm_watch   293
+#define __NR_migrate_pages      294
+#define __NR_openat             295
+#define __NR_mkdirat            296
+#define __NR_mknodat            297
+#define __NR_fchownat           298
+#define __NR_futimesat          299
+#define __NR_fstatat64          300
+#define __NR_unlinkat           301
+#define __NR_renameat           302
+#define __NR_linkat             303
+#define __NR_symlinkat          304
+#define __NR_readlinkat         305
+#define __NR_fchmodat           306
+#define __NR_faccessat          307
+#define __NR_pselect6           308
+#define __NR_ppoll              309
+#define __NR_unshare            310
+#define __NR_set_robust_list    311
+#define __NR_get_robust_list    312
+#define __NR_splice             313
+#define __NR_sync_file_range    314
+#define __NR_tee                315
+#define __NR_vmsplice           316
+#define __NR_move_pages         317
+#define __NR_getcpu             318
+#define __NR_epoll_pwait        319
+#define __NR_utimensat          320
+#define __NR_signalfd           321
+#define __NR_timerfd            322
+#define __NR_eventfd            323
+#define __NR_fallocate          324
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 285
+#define NR_syscalls 325
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_STAT64
@@ -311,6 +351,30 @@
 #define __ARCH_WANT_SYS_OLDUMOUNT
 #define __ARCH_WANT_SYS_RT_SIGACTION
 
+#define __IGNORE_lchown
+#define __IGNORE_setuid
+#define __IGNORE_getuid
+#define __IGNORE_setgid
+#define __IGNORE_getgid
+#define __IGNORE_geteuid
+#define __IGNORE_getegid
+#define __IGNORE_fcntl
+#define __IGNORE_setreuid
+#define __IGNORE_setregid
+#define __IGNORE_getrlimit
+#define __IGNORE_getgroups
+#define __IGNORE_setgroups
+#define __IGNORE_select
+#define __IGNORE_mmap
+#define __IGNORE_fchown
+#define __IGNORE_setfsuid
+#define __IGNORE_setfsgid
+#define __IGNORE_setresuid
+#define __IGNORE_getresuid
+#define __IGNORE_setresgid
+#define __IGNORE_getresgid
+#define __IGNORE_chown
+
 /*
  * "Conditional" syscalls
  *
diff --git a/include/asm-mips/8253pit.h b/include/asm-mips/8253pit.h
deleted file mode 100644
index 285f78488ccb..000000000000
--- a/include/asm-mips/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * 8253/8254 Programmable Interval Timer
- */
-
-#ifndef _8253PIT_H
-#define _8253PIT_H
-
-#define PIT_TICK_RATE   1193182UL
-
-#endif
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index f6bd308f047f..5ea701fc3425 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -207,13 +207,13 @@
 #endif
 
 #ifndef cpu_dcache_line_size
-#define cpu_dcache_line_size()  current_cpu_data.dcache.linesz
+#define cpu_dcache_line_size()  cpu_data[0].dcache.linesz
 #endif
 #ifndef cpu_icache_line_size
-#define cpu_icache_line_size()  current_cpu_data.icache.linesz
+#define cpu_icache_line_size()  cpu_data[0].icache.linesz
 #endif
 #ifndef cpu_scache_line_size
-#define cpu_scache_line_size()  current_cpu_data.scache.linesz
+#define cpu_scache_line_size()  cpu_data[0].scache.linesz
 #endif
 
 #endif /* __ASM_CPU_FEATURES_H */
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index 833437d31ef1..d6a6c21f16db 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -92,6 +92,7 @@
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
 #endif
 #define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+#define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
 
 /* 8237 DMA controllers */
 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 3e7e30d4f418..17f082cfea85 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -35,7 +35,7 @@
                 "       .set    mips0                           \n"     \
                 "       .section .fixup,\"ax\"                  \n"     \
                 "4:     li      %0, %6                          \n"     \
-                "       j       2b                              \n"     \
+                "       j       3b                              \n"     \
                 "       .previous                               \n"     \
                 "       .section __ex_table,\"a\"               \n"     \
                 "       "__UA_ADDR "\t1b, 4b                    \n"     \
@@ -61,7 +61,7 @@
                 "       .set    mips0                           \n"     \
                 "       .section .fixup,\"ax\"                  \n"     \
                 "4:     li      %0, %6                          \n"     \
-                "       j       2b                              \n"     \
+                "       j       3b                              \n"     \
                 "       .previous                               \n"     \
                 "       .section __ex_table,\"a\"               \n"     \
                 "       "__UA_ADDR "\t1b, 4b                    \n"     \
@@ -200,4 +200,4 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
 }
 
 #endif
-#endif
+#endif /* _ASM_FUTEX_H */
diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h
index 032ca73f181b..5dabc870b322 100644
--- a/include/asm-mips/i8253.h
+++ b/include/asm-mips/i8253.h
@@ -12,6 +12,8 @@
 #define PIT_CH0                 0x40
 #define PIT_CH2                 0x42
 
+#define PIT_TICK_RATE           1193182UL
+
 extern spinlock_t i8253_lock;
 
 extern void setup_pit_timer(void);
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index ab5612f90f6f..85bc5302bce0 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -22,7 +22,7 @@ enum ip32_irq_no {
          * CPU interrupts are 0 ... 7
          */
 
-        CRIME_IRQ_BASE                  = MIPS_CPU_IRQ_BASE,
+        CRIME_IRQ_BASE                  = MIPS_CPU_IRQ_BASE + 8,
 
         /*
          * MACE
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 3bdce9126f16..bf7701243d71 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -526,7 +526,7 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
 /* Au1000 */
 #ifdef CONFIG_SOC_AU1000
 enum soc_au1000_ints {
-        AU1000_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+        AU1000_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
         AU1000_UART0_INT        = AU1000_FIRST_INT,
         AU1000_UART1_INT,                               /* au1000 */
         AU1000_UART2_INT,                               /* au1000 */
@@ -605,7 +605,7 @@ enum soc_au1000_ints {
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
 enum soc_au1500_ints {
-        AU1500_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+        AU1500_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
         AU1500_UART0_INT        = AU1500_FIRST_INT,
         AU1000_PCI_INTA,                                /* au1500 */
         AU1000_PCI_INTB,                                /* au1500 */
@@ -686,7 +686,7 @@ enum soc_au1500_ints {
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
 enum soc_au1100_ints {
-        AU1100_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+        AU1100_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
         AU1100_UART0_INT,
         AU1100_UART1_INT,
         AU1100_SD_INT,
@@ -761,7 +761,7 @@ enum soc_au1100_ints {
 
 #ifdef CONFIG_SOC_AU1550
 enum soc_au1550_ints {
-        AU1550_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+        AU1550_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
         AU1550_UART0_INT        = AU1550_FIRST_INT,
         AU1550_PCI_INTA,
         AU1550_PCI_INTB,
@@ -851,7 +851,7 @@ enum soc_au1550_ints {
 
 #ifdef CONFIG_SOC_AU1200
 enum soc_au1200_ints {
-        AU1200_FIRST_INT        = MIPS_CPU_IRQ_BASE,
+        AU1200_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
         AU1200_UART0_INT        = AU1200_FIRST_INT,
         AU1200_SWT_INT,
         AU1200_SD_INT,
@@ -948,11 +948,12 @@ enum soc_au1200_ints {
 
 #endif /* CONFIG_SOC_AU1200 */
 
-#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 0)
-#define AU1000_INTC0_INT_LAST   (MIPS_CPU_IRQ_BASE + 31)
-#define AU1000_INTC1_INT_BASE   (MIPS_CPU_IRQ_BASE + 32)
-#define AU1000_INTC1_INT_LAST   (MIPS_CPU_IRQ_BASE + 63)
-#define AU1000_MAX_INTR         (MIPS_CPU_IRQ_BASE + 63)
+#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
+#define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_BASE + 32)
+#define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
+
+#define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
 #define INTX                    0xFF                    /* not valid */
 
 /* Programmable Counters 0 and 1 */
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 90e4b403f531..a944eda4faf5 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -68,11 +68,15 @@ do {									\
         if (cpu_has_dsp)                                                \
                 __save_dsp(prev);                                       \
         (last) = resume(prev, next, task_thread_info(next));            \
+} while (0)
+
+#define finish_arch_switch(prev)                                        \
+do {                                                                    \
         if (cpu_has_dsp)                                                \
                 __restore_dsp(current);                                 \
         if (cpu_has_userlocal)                                          \
-                write_c0_userlocal(task_thread_info(current)->tp_value);\
-} while(0)
+                write_c0_userlocal(current_thread_info()->tp_value);    \
+} while (0)
 
 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 {
@@ -205,8 +209,6 @@ extern void *set_except_vector(int n, void *addr);
 extern unsigned long ebase;
 extern void per_cpu_trap_init(void);
 
-extern int stop_a_enabled;
-
 /*
  * See include/asm-ia64/system.h; prevents deadlock on SMP
  * systems.
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index ee1663e64da1..7717934f94c3 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -58,10 +58,22 @@ extern int (*perf_irq)(void);
  * Initialize the calling CPU's compare interrupt as clockevent device
  */
 #ifdef CONFIG_CEVT_R4K
-extern void mips_clockevent_init(void);
+extern int mips_clockevent_init(void);
 extern unsigned int __weak get_c0_compare_int(void);
 #else
-static inline void mips_clockevent_init(void)
+static inline int mips_clockevent_init(void)
+{
+        return -ENXIO;
+}
+#endif
+
+/*
+ * Initialize the count register as a clocksource
+ */
+#ifdef CONFIG_CEVT_R4K
+extern void init_mips_clocksource(void);
+#else
+static inline void init_mips_clocksource(void)
 {
 }
 #endif
diff --git a/include/asm-parisc/pdc.h b/include/asm-parisc/pdc.h
index 5e0c3ca5450b..deda8c311373 100644
--- a/include/asm-parisc/pdc.h
+++ b/include/asm-parisc/pdc.h
@@ -645,8 +645,7 @@ int pdc_soft_power_button(int sw_control);
 void pdc_io_reset(void);
 void pdc_io_reset_devices(void);
 int pdc_iodc_getc(void);
-void pdc_iodc_putc(unsigned char c);
-void pdc_iodc_outc(unsigned char c);
+int pdc_iodc_print(unsigned char *str, unsigned count);
 void pdc_printf(const char *fmt, ...);
 
 void pdc_emergency_unlock(void);
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
index 374d0db37e1c..17110aff26e7 100644
--- a/include/asm-powerpc/page_32.h
+++ b/include/asm-powerpc/page_32.h
@@ -6,6 +6,10 @@
 
 #define PPC_MEMSTART    0
 
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
+#endif
+
 #ifndef __ASSEMBLY__
 /*
  * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index dc318458b5fe..d8bdc79db12e 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -246,7 +246,6 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
         return PCI_DN(busdn)->phb;
 }
 
-extern void pcibios_free_controller(struct pci_controller *phb);
 
 extern void isa_bridge_find_early(struct pci_controller *hose);
 
@@ -282,9 +281,11 @@ extern void
 pci_process_bridge_OF_ranges(struct pci_controller *hose,
                            struct device_node *dev, int primary);
 
-/* Allocate a new PCI host bridge structure */
+/* Allocate & free a PCI host bridge structure */
 extern struct pci_controller *
 pcibios_alloc_controller(struct device_node *dev);
+extern void pcibios_free_controller(struct pci_controller *phb);
+
 #ifdef CONFIG_PCI
 extern unsigned long pci_address_to_pio(phys_addr_t address);
 extern int pcibios_vaddr_is_ioport(void __iomem *address);
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index fea2d8ff1e73..d1332bbcbd9b 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -86,6 +86,11 @@ extern int icache_44x_need_flush;
  * entries per page directory level: our page-table tree is two-level, so
  * we don't really have any PMD directory.
  */
+#ifndef __ASSEMBLY__
+#define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_SHIFT)
+#define PGD_TABLE_SIZE  (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
+#endif  /* __ASSEMBLY__ */
+
 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
 #define PTRS_PER_PMD    1
 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
index 780f82642756..ce5de6e0e690 100644
--- a/include/asm-powerpc/time.h
+++ b/include/asm-powerpc/time.h
@@ -237,18 +237,14 @@ struct cpu_usage {
 
 DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
 
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
-extern void account_process_vtime(struct task_struct *tsk);
-#else
-#define account_process_vtime(tsk)              do { } while (0)
-#endif
-
 #if defined(CONFIG_VIRT_CPU_ACCOUNTING)
 extern void calculate_steal_time(void);
 extern void snapshot_timebases(void);
+#define account_process_vtime(tsk)              account_process_tick(tsk, 0)
 #else
 #define calculate_steal_time()                  do { } while (0)
 #define snapshot_timebases()                    do { } while (0)
+#define account_process_vtime(tsk)              do { } while (0)
 #endif
 
 extern void secondary_cpu_time_init(void);
diff --git a/include/asm-powerpc/vdso_datapage.h b/include/asm-powerpc/vdso_datapage.h
index 8a94f0eba5e9..f01393224b52 100644
--- a/include/asm-powerpc/vdso_datapage.h
+++ b/include/asm-powerpc/vdso_datapage.h
@@ -77,6 +77,10 @@ struct vdso_data {
         /* those additional ones don't have to be located anywhere
          * special as they were not part of the original systemcfg
          */
+        __u32 dcache_block_size;                /* L1 d-cache block size     */
+        __u32 icache_block_size;                /* L1 i-cache block size     */
+        __u32 dcache_log_block_size;            /* L1 d-cache log block size */
+        __u32 icache_log_block_size;            /* L1 i-cache log block size */
         __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
         __s32 wtom_clock_nsec;
         __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls  */
@@ -99,6 +103,10 @@ struct vdso_data {
         __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
         __s32 wtom_clock_nsec;
         __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
+        __u32 dcache_block_size;        /* L1 d-cache block size     */
+        __u32 icache_block_size;        /* L1 i-cache block size     */
+        __u32 dcache_log_block_size;    /* L1 d-cache log block size */
+        __u32 icache_log_block_size;    /* L1 i-cache log block size */
 };
 
 #endif /* CONFIG_PPC64 */
diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h
index d866d3385556..44bda786eef7 100644
--- a/include/asm-s390/system.h
+++ b/include/asm-s390/system.h
@@ -388,6 +388,11 @@ extern void (*_machine_power_off)(void);
 
 #define arch_align_stack(x) (x)
 
+#ifdef CONFIG_TRACE_IRQFLAGS
+extern psw_t sysc_restore_trace_psw;
+extern psw_t io_restore_trace_psw;
+#endif
+
 #endif /* __KERNEL__ */
 
 #endif
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h
index b91246153b7e..9d528ada3c14 100644
--- a/include/asm-sh/cacheflush.h
+++ b/include/asm-sh/cacheflush.h
@@ -43,7 +43,7 @@ extern void __flush_purge_region(void *start, int size);
 extern void __flush_invalidate_region(void *start, int size);
 #endif
 
-#ifdef CONFIG_CPU_SH4
+#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF)
 extern void copy_to_user_page(struct vm_area_struct *vma,
         struct page *page, unsigned long vaddr, void *dst, const void *src,
         unsigned long len);
diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h
index 0693689d4146..f8a89793ac8c 100644
--- a/include/asm-x86/acpi.h
+++ b/include/asm-x86/acpi.h
@@ -1,5 +1,32 @@
+#ifndef _ASM_X86_ACPI_H
+#define _ASM_X86_ACPI_H
+
 #ifdef CONFIG_X86_32
 # include "acpi_32.h"
 #else
 # include "acpi_64.h"
 #endif
+
+#include <asm/processor.h>
+
+/*
+ * Check if the CPU can handle C2 and deeper
+ */
+static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
+{
+        /*
+         * Early models (<=5) of AMD Opterons are not supposed to go into
+         * C2 state.
+         *
+         * Steppings 0x0A and later are good
+         */
+        if (boot_cpu_data.x86 == 0x0F &&
+            boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+            boot_cpu_data.x86_model <= 0x05 &&
+            boot_cpu_data.x86_mask < 0x0A)
+                return 1;
+        else
+                return max_cstate;
+}
+
+#endif
diff --git a/include/asm-x86/apic_32.h b/include/asm-x86/apic_32.h
index 4091b33dcb10..be158b27d54b 100644
--- a/include/asm-x86/apic_32.h
+++ b/include/asm-x86/apic_32.h
@@ -120,6 +120,7 @@ extern int local_apic_timer_disabled;
 
 #else /* !CONFIG_X86_LOCAL_APIC */
 static inline void lapic_shutdown(void) { }
+#define local_apic_timer_c2_ok          1
 
 #endif /* !CONFIG_X86_LOCAL_APIC */
 
diff --git a/include/asm-x86/hpet.h b/include/asm-x86/hpet.h
index b1f3c1ea55d9..ad8d6e758785 100644
--- a/include/asm-x86/hpet.h
+++ b/include/asm-x86/hpet.h
@@ -61,6 +61,7 @@ extern unsigned long force_hpet_address;
 extern int hpet_force_user;
 extern int is_hpet_enabled(void);
 extern int hpet_enable(void);
+extern void hpet_disable(void);
 extern unsigned long hpet_readl(unsigned long a);
 extern void force_hpet_resume(void);
 
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 8ccedf7a0a5a..e3c16c981e46 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -132,6 +132,11 @@ extern unsigned long acpi_realmode_flags;
 int acpi_register_gsi (u32 gsi, int triggering, int polarity);
 int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
 
+#ifdef CONFIG_X86_IO_APIC
+extern int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity);
+#else
+#define acpi_get_override_irq(bus, trigger, polarity) (-1)
+#endif
 /*
  * This function undoes the effect of one call to acpi_register_gsi().
  * If this matches the last registration, any IRQ resources for gsi
diff --git a/include/linux/cgroup_subsys.h b/include/linux/cgroup_subsys.h
index d62fcee9a08a..9ec43186ba80 100644
--- a/include/linux/cgroup_subsys.h
+++ b/include/linux/cgroup_subsys.h
@@ -30,3 +30,10 @@ SUBSYS(cpu_cgroup)
 #endif
 
 /* */
+
+#ifdef CONFIG_CGROUP_CPUACCT
+SUBSYS(cpuacct)
+#endif
+
+/* */
+
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 16a51546db44..c4e00161a247 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -92,6 +92,7 @@ struct cpuidle_device {
         struct kobject          kobj;
         struct completion       kobj_unregister;
         void                    *governor_data;
+        struct cpuidle_state    *safe_state;
 };
 
 DECLARE_PER_CPU(struct cpuidle_device *, cpuidle_devices);
diff --git a/include/linux/ext2_fs.h b/include/linux/ext2_fs.h
index 0f6c86c634fd..84cec2aa9f1e 100644
--- a/include/linux/ext2_fs.h
+++ b/include/linux/ext2_fs.h
@@ -563,11 +563,4 @@ enum {
                                          ~EXT2_DIR_ROUND)
 #define EXT2_MAX_REC_LEN                ((1<<16)-1)
 
-static inline ext2_fsblk_t
-ext2_group_first_block_no(struct super_block *sb, unsigned long group_no)
-{
-        return group_no * (ext2_fsblk_t)EXT2_BLOCKS_PER_GROUP(sb) +
-                le32_to_cpu(EXT2_SB(sb)->s_es->s_first_data_block);
-}
-
 #endif  /* _LINUX_EXT2_FS_H */
diff --git a/include/linux/fuse.h b/include/linux/fuse.h
index d0c437028c80..5c86f1196c3a 100644
--- a/include/linux/fuse.h
+++ b/include/linux/fuse.h
@@ -16,6 +16,7 @@
  *  - add lk_flags in fuse_lk_in
  *  - add lock_owner field to fuse_setattr_in, fuse_read_in and fuse_write_in
  *  - add blksize field to fuse_attr
+ *  - add file flags field to fuse_read_in and fuse_write_in
  */
 
 #include <asm/types.h>
@@ -280,6 +281,8 @@ struct fuse_read_in {
         __u32   size;
         __u32   read_flags;
         __u64   lock_owner;
+        __u32   flags;
+        __u32   padding;
 };
 
 #define FUSE_COMPAT_WRITE_IN_SIZE 24
@@ -290,6 +293,8 @@ struct fuse_write_in {
         __u32   size;
         __u32   write_flags;
         __u64   lock_owner;
+        __u32   flags;
+        __u32   padding;
 };
 
 struct fuse_write_out {
diff --git a/include/linux/if_bonding.h b/include/linux/if_bonding.h
index 84598fa2e9de..65c2d247068b 100644
--- a/include/linux/if_bonding.h
+++ b/include/linux/if_bonding.h
@@ -85,7 +85,8 @@
 
 /* hashing types */
 #define BOND_XMIT_POLICY_LAYER2         0 /* layer 2 (MAC only), default */
-#define BOND_XMIT_POLICY_LAYER34        1 /* layer 3+4 (IP ^ MAC) */
+#define BOND_XMIT_POLICY_LAYER34        1 /* layer 3+4 (IP ^ (TCP || UDP)) */
+#define BOND_XMIT_POLICY_LAYER23        2 /* layer 2+3 (IP ^ MAC) */
 
 typedef struct ifbond {
         __s32 bond_mode;
diff --git a/include/linux/inet_lro.h b/include/linux/inet_lro.h
index 1246d46abbc0..80335b7d77c5 100644
--- a/include/linux/inet_lro.h
+++ b/include/linux/inet_lro.h
@@ -91,6 +91,9 @@ struct net_lro_mgr {
         int max_desc; /* Max number of LRO descriptors  */
         int max_aggr; /* Max number of LRO packets to be aggregated */
 
+        int frag_align_pad; /* Padding required to properly align layer 3
+                             * headers in generated skb when using frags */
+
         struct net_lro_desc *lro_arr; /* Array of LRO descriptors */
 
         /*
diff --git a/include/linux/input.h b/include/linux/input.h
index b45f240a8c45..2075d6da2a31 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -530,6 +530,11 @@ struct input_absinfo {
 #define KEY_DOLLAR              0x1b2
 #define KEY_EURO                0x1b3
 
+#define KEY_FRAMEBACK           0x1b4   /* Consumer - transport controls */
+#define KEY_FRAMEFORWARD        0x1b5
+
+#define KEY_CONTEXT_MENU        0x1b6   /* GenDesc - system context menu */
+
 #define KEY_DEL_EOL             0x1c0
 #define KEY_DEL_EOS             0x1c1
 #define KEY_INS_LINE            0x1c2
diff --git a/include/linux/jbd.h b/include/linux/jbd.h
index 16e7ed855a18..d9ecd13393b0 100644
--- a/include/linux/jbd.h
+++ b/include/linux/jbd.h
@@ -439,6 +439,8 @@ struct transaction_s
         /*
          * Transaction's current state
          * [no locking - only kjournald alters this]
+         * [j_list_lock] guards transition of a transaction into T_FINISHED
+         * state and subsequent call of __journal_drop_transaction()
          * FIXME: needs barriers
          * KLUDGE: [use j_state_lock]
          */
diff --git a/include/linux/kd.h b/include/linux/kd.h
index c91fc0c9c495..15f2853ea58f 100644
--- a/include/linux/kd.h
+++ b/include/linux/kd.h
@@ -126,7 +126,7 @@ struct kbdiacrs {
 #define KDSKBDIACR      0x4B4B  /* write kernel accent table */
 
 struct kbdiacruc {
-        __u32 diacr, base, result;
+        unsigned int diacr, base, result;
 };
 struct kbdiacrsuc {
         unsigned int kb_cnt;    /* number of entries in following array */
diff --git a/include/linux/leds.h b/include/linux/leds.h
index dc1178f6184b..b4130ff58d0c 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -14,6 +14,7 @@
 
 #include <linux/list.h>
 #include <linux/spinlock.h>
+#include <linux/rwsem.h>
 
 struct device;
 /*
@@ -43,7 +44,7 @@ struct led_classdev {
 
 #ifdef CONFIG_LEDS_TRIGGERS
         /* Protects the trigger data below */
-        rwlock_t                 trigger_lock;
+        struct rw_semaphore      trigger_lock;
 
         struct led_trigger      *trigger;
         struct list_head         trig_list;
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 56a5673aebad..ef52a07c43d8 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -340,6 +340,7 @@ enum {
         ATA_HORKAGE_HPA_SIZE    = (1 << 6),     /* native size off by one */
         ATA_HORKAGE_IPM         = (1 << 7),     /* Link PM problems */
         ATA_HORKAGE_IVB         = (1 << 8),     /* cbl det validity bit bugs */
+        ATA_HORKAGE_STUCK_ERR   = (1 << 9),     /* stuck ERR on next PACKET */
 
          /* DMA mask for user DMA control: User visible values; DO NOT
             renumber */
@@ -771,8 +772,6 @@ static inline int ata_port_is_dummy(struct ata_port *ap)
 
 extern void sata_print_link_status(struct ata_link *link);
 extern void ata_port_probe(struct ata_port *);
-extern void __sata_phy_reset(struct ata_port *ap);
-extern void sata_phy_reset(struct ata_port *ap);
 extern void ata_bus_reset(struct ata_port *ap);
 extern int sata_set_spd(struct ata_link *link);
 extern int sata_link_debounce(struct ata_link *link,
@@ -994,8 +993,6 @@ extern void sata_pmp_do_eh(struct ata_port *ap,
 /*
  * EH
  */
-extern void ata_eng_timeout(struct ata_port *ap);
-
 extern void ata_port_schedule_eh(struct ata_port *ap);
 extern int ata_link_abort(struct ata_link *link);
 extern int ata_port_abort(struct ata_port *ap);
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 520238cbae5d..1b7b95c67aca 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -12,6 +12,7 @@
 #include <linux/prio_tree.h>
 #include <linux/debug_locks.h>
 #include <linux/mm_types.h>
+#include <linux/security.h>
 
 struct mempolicy;
 struct anon_vma;
@@ -513,6 +514,21 @@ static inline void set_page_links(struct page *page, enum zone_type zone,
 }
 
 /*
+ * If a hint addr is less than mmap_min_addr change hint to be as
+ * low as possible but still greater than mmap_min_addr
+ */
+static inline unsigned long round_hint_to_min(unsigned long hint)
+{
+#ifdef CONFIG_SECURITY
+        hint &= PAGE_MASK;
+        if (((void *)hint != NULL) &&
+            (hint < mmap_min_addr))
+                return PAGE_ALIGN(mmap_min_addr);
+#endif
+        return hint;
+}
+
+/*
  * Some inline functions in vmstat.h depend on page_zone()
  */
 #include <linux/vmstat.h>
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index e82a6ebc725d..2d15d4aac094 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -422,7 +422,6 @@ extern long nfs_sync_mapping_wait(struct address_space *, struct writeback_contr
 extern int nfs_wb_all(struct inode *inode);
 extern int nfs_wb_nocommit(struct inode *inode);
 extern int nfs_wb_page(struct inode *inode, struct page* page);
-extern int nfs_wb_page_priority(struct inode *inode, struct page* page, int how);
 extern int nfs_wb_page_cancel(struct inode *inode, struct page* page);
 #if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4)
 extern int  nfs_commit_inode(struct inode *, int);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1ee009e8fec8..111aa10f1136 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1237,6 +1237,10 @@
 #define PCI_DEVICE_ID_NVIDIA_NVENET_33              0x0761
 #define PCI_DEVICE_ID_NVIDIA_NVENET_34              0x0762
 #define PCI_DEVICE_ID_NVIDIA_NVENET_35              0x0763
+#define PCI_DEVICE_ID_NVIDIA_NVENET_36              0x0AB0
+#define PCI_DEVICE_ID_NVIDIA_NVENET_37              0x0AB1
+#define PCI_DEVICE_ID_NVIDIA_NVENET_38              0x0AB2
+#define PCI_DEVICE_ID_NVIDIA_NVENET_39              0x0AB3
 
 #define PCI_VENDOR_ID_IMS               0x10e0
 #define PCI_DEVICE_ID_IMS_TT128         0x9128
diff --git a/include/linux/phy.h b/include/linux/phy.h
index f0742b6aaa64..554836edd915 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -58,6 +58,8 @@ typedef enum {
         PHY_INTERFACE_MODE_RMII,
         PHY_INTERFACE_MODE_RGMII,
         PHY_INTERFACE_MODE_RGMII_ID,
+        PHY_INTERFACE_MODE_RGMII_RXID,
+        PHY_INTERFACE_MODE_RGMII_TXID,
         PHY_INTERFACE_MODE_RTBI
 } phy_interface_t;
 
@@ -401,6 +403,7 @@ int phy_mii_ioctl(struct phy_device *phydev,
 int phy_start_interrupts(struct phy_device *phydev);
 void phy_print_status(struct phy_device *phydev);
 struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id);
+void phy_device_free(struct phy_device *phydev);
 
 extern struct bus_type mdio_bus_type;
 #endif /* __PHY_H */
diff --git a/include/linux/pnp.h b/include/linux/pnp.h
index 664d68cb1fbd..0a0426c2867d 100644
--- a/include/linux/pnp.h
+++ b/include/linux/pnp.h
@@ -13,8 +13,8 @@
 #include <linux/errno.h>
 #include <linux/mod_devicetable.h>
 
-#define PNP_MAX_PORT            8
-#define PNP_MAX_MEM             4
+#define PNP_MAX_PORT            24
+#define PNP_MAX_MEM             12
 #define PNP_MAX_IRQ             2
 #define PNP_MAX_DMA             2
 #define PNP_NAME_LEN            50
diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h
index 1273c6ec535c..a5316829215b 100644
--- a/include/linux/proc_fs.h
+++ b/include/linux/proc_fs.h
@@ -48,6 +48,8 @@ typedef	int (read_proc_t)(char *page, char **start, off_t off,
 typedef int (write_proc_t)(struct file *file, const char __user *buffer,
                            unsigned long count, void *data);
 typedef int (get_info_t)(char *, char **, off_t, int);
+typedef struct proc_dir_entry *(shadow_proc_t)(struct task_struct *task,
+                                                struct proc_dir_entry *pde);
 
 struct proc_dir_entry {
         unsigned int low_ino;
@@ -75,10 +77,10 @@ struct proc_dir_entry {
         read_proc_t *read_proc;
         write_proc_t *write_proc;
         atomic_t count;         /* use count */
-        int deleted;            /* delete flag */
         int pde_users;  /* number of callers into module in progress */
         spinlock_t pde_unload_lock; /* proc_fops checks and pde_users bumps */
         struct completion *pde_unload_completion;
+        shadow_proc_t *shadow_proc;
 };
 
 struct kcore_list {
diff --git a/include/linux/rtc.h b/include/linux/rtc.h
index 6d5e4a46781e..f2d0d1527721 100644
--- a/include/linux/rtc.h
+++ b/include/linux/rtc.h
@@ -133,6 +133,9 @@ struct rtc_class_ops {
 #define RTC_DEVICE_NAME_SIZE 20
 struct rtc_task;
 
+/* flags */
+#define RTC_DEV_BUSY 0
+
 struct rtc_device
 {
         struct device dev;
@@ -145,7 +148,7 @@ struct rtc_device
         struct mutex ops_lock;
 
         struct cdev char_dev;
-        struct mutex char_lock;
+        unsigned long flags;
 
         unsigned long irq_data;
         spinlock_t irq_lock;
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 259735044148..416e000dfe81 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -26,6 +26,16 @@
 
 #define SG_MAGIC        0x87654321
 
+/*
+ * We overload the LSB of the page pointer to indicate whether it's
+ * a valid sg entry, or whether it points to the start of a new scatterlist.
+ * Those low bits are there for everyone! (thanks mason :-)
+ */
+#define sg_is_chain(sg)         ((sg)->page_link & 0x01)
+#define sg_is_last(sg)          ((sg)->page_link & 0x02)
+#define sg_chain_ptr(sg)        \
+        ((struct scatterlist *) ((sg)->page_link & ~0x03))
+
 /**
  * sg_assign_page - Assign a given page to an SG entry
  * @sg:             SG entry
@@ -47,6 +57,7 @@ static inline void sg_assign_page(struct scatterlist *sg, struct page *page)
         BUG_ON((unsigned long) page & 0x03);
 #ifdef CONFIG_DEBUG_SG
         BUG_ON(sg->sg_magic != SG_MAGIC);
+        BUG_ON(sg_is_chain(sg));
 #endif
         sg->page_link = page_link | (unsigned long) page;
 }
@@ -73,7 +84,14 @@ static inline void sg_set_page(struct scatterlist *sg, struct page *page,
         sg->length = len;
 }
 
-#define sg_page(sg)     ((struct page *) ((sg)->page_link & ~0x3))
+static inline struct page *sg_page(struct scatterlist *sg)
+{
+#ifdef CONFIG_DEBUG_SG
+        BUG_ON(sg->sg_magic != SG_MAGIC);
+        BUG_ON(sg_is_chain(sg));
+#endif
+        return (struct page *)((sg)->page_link & ~0x3);
+}
 
 /**
  * sg_set_buf - Set sg entry to point at given data
@@ -88,16 +106,6 @@ static inline void sg_set_buf(struct scatterlist *sg, const void *buf,
         sg_set_page(sg, virt_to_page(buf), buflen, offset_in_page(buf));
 }
 
-/*
- * We overload the LSB of the page pointer to indicate whether it's
- * a valid sg entry, or whether it points to the start of a new scatterlist.
- * Those low bits are there for everyone! (thanks mason :-)
- */
-#define sg_is_chain(sg)         ((sg)->page_link & 0x01)
-#define sg_is_last(sg)          ((sg)->page_link & 0x02)
-#define sg_chain_ptr(sg)        \
-        ((struct scatterlist *) ((sg)->page_link & ~0x03))
-
 /**
  * sg_next - return the next scatterlist entry in a list
  * @sg:         The current sg entry
@@ -179,6 +187,13 @@ static inline void sg_chain(struct scatterlist *prv, unsigned int prv_nents,
 #ifndef ARCH_HAS_SG_CHAIN
         BUG();
 #endif
+
+        /*
+         * offset and length are unused for chain entry.  Clear them.
+         */
+        prv->offset = 0;
+        prv->length = 0;
+
         /*
          * Set lowest bit to indicate a link pointer, and make sure to clear
          * the termination bit if it happens to be set.
diff --git a/include/linux/sched.h b/include/linux/sched.h
index ee800e7a70de..ac3d496fbd20 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -282,6 +282,10 @@ static inline void touch_all_softlockup_watchdogs(void)
 
 /* Attach to any functions which should be ignored in wchan output. */
 #define __sched         __attribute__((__section__(".sched.text")))
+
+/* Linker adds these: start and end of __sched functions */
+extern char __sched_text_start[], __sched_text_end[];
+
 /* Is this address in the __sched functions? */
 extern int in_sched_functions(unsigned long addr);
 
diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h
index 827b85bbf388..1ee2c05142f6 100644
--- a/include/linux/screen_info.h
+++ b/include/linux/screen_info.h
@@ -63,6 +63,8 @@ struct screen_info {
 
 #define VIDEO_TYPE_PMAC         0x60    /* PowerMacintosh frame buffer. */
 
+#define VIDEO_TYPE_EFI          0x70    /* EFI graphic mode             */
+
 #ifdef __KERNEL__
 extern struct screen_info screen_info;
 
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 6a5203fb9cf1..9963f81fea9a 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -437,7 +437,7 @@ uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
 #ifdef SUPPORT_SYSRQ
         if (port->sysrq) {
                 if (ch && time_before(jiffies, port->sysrq)) {
-                        handle_sysrq(ch, port->info->tty);
+                        handle_sysrq(ch, port->info ? port->info->tty : NULL);
                         port->sysrq = 0;
                         return 1;
                 }
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 91140fe8c119..bddd50bd6878 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -356,7 +356,6 @@ static inline struct sk_buff *alloc_skb_fclone(unsigned int size,
         return __alloc_skb(size, priority, 1, -1);
 }
 
-extern void            kfree_skbmem(struct sk_buff *skb);
 extern struct sk_buff *skb_morph(struct sk_buff *dst, struct sk_buff *src);
 extern struct sk_buff *skb_clone(struct sk_buff *skb,
                                  gfp_t priority);
diff --git a/include/linux/sunrpc/debug.h b/include/linux/sunrpc/debug.h
index 3347c72b848a..3912cf16361e 100644
--- a/include/linux/sunrpc/debug.h
+++ b/include/linux/sunrpc/debug.h
@@ -88,11 +88,6 @@ enum {
         CTL_SLOTTABLE_TCP,
         CTL_MIN_RESVPORT,
         CTL_MAX_RESVPORT,
-        CTL_SLOTTABLE_RDMA,
-        CTL_RDMA_MAXINLINEREAD,
-        CTL_RDMA_MAXINLINEWRITE,
-        CTL_RDMA_WRITEPADDING,
-        CTL_RDMA_MEMREG,
 };
 
 #endif /* _LINUX_SUNRPC_DEBUG_H_ */
diff --git a/include/linux/sunrpc/xprtsock.h b/include/linux/sunrpc/xprtsock.h
index 2c6c2c2783d8..c2a46c45c8f7 100644
--- a/include/linux/sunrpc/xprtsock.h
+++ b/include/linux/sunrpc/xprtsock.h
@@ -9,12 +9,6 @@
 
 #ifdef __KERNEL__
 
-/*
- * Socket transport setup operations
- */
-struct rpc_xprt *xs_setup_udp(struct xprt_create *args);
-struct rpc_xprt *xs_setup_tcp(struct xprt_create *args);
-
 int             init_socket_xprt(void);
 void            cleanup_socket_xprt(void);
 
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index e99171f01b4c..4f5047df8a9e 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -70,7 +70,6 @@ enum
         CTL_ABI=9,              /* Binary emulation */
         CTL_CPU=10,             /* CPU stuff (speed scaling, etc) */
         CTL_ARLAN=254,          /* arlan wireless driver */
-        CTL_APPLDATA=2120,      /* s390 appldata */
         CTL_S390DBF=5677,       /* s390 debug */
         CTL_SUNRPC=7249,        /* sunrpc debug */
         CTL_PM=9899,            /* frv power management */
@@ -207,11 +206,6 @@ enum
         VM_PANIC_ON_OOM=33,     /* panic at out-of-memory */
         VM_VDSO_ENABLED=34,     /* map VDSO into new processes? */
         VM_MIN_SLAB=35,          /* Percent pages ignored by zone reclaim */
-
-        /* s390 vm cmm sysctls */
-        VM_CMM_PAGES=1111,
-        VM_CMM_TIMED_PAGES=1112,
-        VM_CMM_TIMEOUT=1113,
 };
 
 
diff --git a/include/linux/thread_info.h b/include/linux/thread_info.h
index 1c4eb41dbd89..9c4ad755d7e5 100644
--- a/include/linux/thread_info.h
+++ b/include/linux/thread_info.h
@@ -7,12 +7,25 @@
 #ifndef _LINUX_THREAD_INFO_H
 #define _LINUX_THREAD_INFO_H
 
+#include <linux/types.h>
+
 /*
- * System call restart block. 
+ * System call restart block.
  */
 struct restart_block {
         long (*fn)(struct restart_block *);
-        unsigned long arg0, arg1, arg2, arg3;
+        union {
+                struct {
+                        unsigned long arg0, arg1, arg2, arg3;
+                };
+                /* For futex_wait */
+                struct {
+                        u32 *uaddr;
+                        u32 val;
+                        u32 flags;
+                        u64 time;
+                } futex;
+        };
 };
 
 extern long do_no_restart_syscall(struct restart_block *parm);
diff --git a/include/linux/timex.h b/include/linux/timex.h
index 37ac3ff90faf..24c6a2b59511 100644
--- a/include/linux/timex.h
+++ b/include/linux/timex.h
@@ -137,6 +137,7 @@ struct timex {
 #define ADJ_TIMECONST           0x0020  /* pll time constant */
 #define ADJ_TICK                0x4000  /* tick value */
 #define ADJ_OFFSET_SINGLESHOT   0x8001  /* old-fashioned adjtime */
+#define ADJ_OFFSET_SS_READ      0xa001  /* read-only adjtime */
 
 /* xntp 3.4 compatibility names */
 #define MOD_OFFSET      ADJ_OFFSET
diff --git a/include/linux/usb.h b/include/linux/usb.h
index c5c8f169d3cf..416ee7617d9e 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -157,6 +157,7 @@ struct usb_interface {
                                          * bound to */
         enum usb_interface_condition condition;         /* state of binding */
         unsigned is_active:1;           /* the interface is not suspended */
+        unsigned sysfs_files_created:1; /* the sysfs attributes exist */
         unsigned needs_remote_wakeup:1; /* driver requires remote wakeup */
 
         struct device dev;              /* interface specific device info */
diff --git a/include/linux/usbdevice_fs.h b/include/linux/usbdevice_fs.h
index 342dd5a7e8bb..8ca5a7fbc9ec 100644
--- a/include/linux/usbdevice_fs.h
+++ b/include/linux/usbdevice_fs.h
@@ -102,7 +102,8 @@ struct usbdevfs_urb {
         int start_frame;
         int number_of_packets;
         int error_count;
-        unsigned int signr;  /* signal to be sent on error, -1 if none should be sent */
+        unsigned int signr;     /* signal to be sent on completion,
+                                  or 0 if none should be sent. */
         void *usercontext;
         struct usbdevfs_iso_packet_desc iso_frame_desc[0];
 };
diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h
index 164d13211165..d8ae48439f12 100644
--- a/include/net/ieee80211.h
+++ b/include/net/ieee80211.h
@@ -115,8 +115,16 @@ extern u32 ieee80211_debug_level;
 do { if (ieee80211_debug_level & (level)) \
   printk(KERN_DEBUG "ieee80211: %c %s " fmt, \
          in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
+static inline bool ieee80211_ratelimit_debug(u32 level)
+{
+        return (ieee80211_debug_level & level) && net_ratelimit();
+}
 #else
 #define IEEE80211_DEBUG(level, fmt, args...) do {} while (0)
+static inline bool ieee80211_ratelimit_debug(u32 level)
+{
+        return false;
+}
 #endif                          /* CONFIG_IEEE80211_DEBUG */
 
 /* escape_essid() is intended to be used in debug (and possibly error)
diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h
index 469216d93663..37f6cb112127 100644
--- a/include/net/inet_hashtables.h
+++ b/include/net/inet_hashtables.h
@@ -186,9 +186,8 @@ static inline void inet_ehash_locks_free(struct inet_hashinfo *hashinfo)
                 if (size > PAGE_SIZE)
                         vfree(hashinfo->ehash_locks);
                 else
-#else
-                kfree(hashinfo->ehash_locks);
 #endif
+                kfree(hashinfo->ehash_locks);
                 hashinfo->ehash_locks = NULL;
         }
 }
diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index 67ea2c0c0ab7..8a7d59be8a0d 100644
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -328,40 +328,6 @@ extern int ip_vs_get_debug_level(void);
 #define FTPDATA  __constant_htons(20)
 
 /*
- *      IPVS sysctl variables under the /proc/sys/net/ipv4/vs/
- */
-#define NET_IPV4_VS              21
-
-enum {
-        NET_IPV4_VS_DEBUG_LEVEL=1,
-        NET_IPV4_VS_AMEMTHRESH=2,
-        NET_IPV4_VS_AMDROPRATE=3,
-        NET_IPV4_VS_DROP_ENTRY=4,
-        NET_IPV4_VS_DROP_PACKET=5,
-        NET_IPV4_VS_SECURE_TCP=6,
-        NET_IPV4_VS_TO_ES=7,
-        NET_IPV4_VS_TO_SS=8,
-        NET_IPV4_VS_TO_SR=9,
-        NET_IPV4_VS_TO_FW=10,
-        NET_IPV4_VS_TO_TW=11,
-        NET_IPV4_VS_TO_CL=12,
-        NET_IPV4_VS_TO_CW=13,
-        NET_IPV4_VS_TO_LA=14,
-        NET_IPV4_VS_TO_LI=15,
-        NET_IPV4_VS_TO_SA=16,
-        NET_IPV4_VS_TO_UDP=17,
-        NET_IPV4_VS_TO_ICMP=18,
-        NET_IPV4_VS_LBLC_EXPIRE=19,
-        NET_IPV4_VS_LBLCR_EXPIRE=20,
-        NET_IPV4_VS_CACHE_BYPASS=22,
-        NET_IPV4_VS_EXPIRE_NODEST_CONN=23,
-        NET_IPV4_VS_SYNC_THRESHOLD=24,
-        NET_IPV4_VS_NAT_ICMP_SEND=25,
-        NET_IPV4_VS_EXPIRE_QUIESCENT_TEMPLATE=26,
-        NET_IPV4_VS_LAST
-};
-
-/*
  *      TCP State Values
  */
 enum {
diff --git a/include/net/route.h b/include/net/route.h
index f7ce6259f86f..59b0b19205a2 100644
--- a/include/net/route.h
+++ b/include/net/route.h
@@ -109,7 +109,6 @@ struct in_device;
 extern int              ip_rt_init(void);
 extern void             ip_rt_redirect(__be32 old_gw, __be32 dst, __be32 new_gw,
                                        __be32 src, struct net_device *dev);
-extern void             ip_rt_advice(struct rtable **rp, int advice);
 extern void             rt_cache_flush(int how);
 extern int              __ip_route_output_key(struct rtable **, const struct flowi *flp);
 extern int              ip_route_output_key(struct rtable **, struct flowi *flp);
diff --git a/include/net/sctp/constants.h b/include/net/sctp/constants.h
index f30b537d6952..05f22a6afbcd 100644
--- a/include/net/sctp/constants.h
+++ b/include/net/sctp/constants.h
@@ -441,11 +441,14 @@ enum {
         SCTP_AUTH_HMAC_ID_RESERVED_0,
         SCTP_AUTH_HMAC_ID_SHA1,
         SCTP_AUTH_HMAC_ID_RESERVED_2,
-        SCTP_AUTH_HMAC_ID_SHA256
+#if defined (CONFIG_CRYPTO_SHA256) || defined (CONFIG_CRYPTO_SHA256_MODULE)
+        SCTP_AUTH_HMAC_ID_SHA256,
+#endif
+        __SCTP_AUTH_HMAC_MAX
 };
 
-#define SCTP_AUTH_HMAC_ID_MAX   SCTP_AUTH_HMAC_ID_SHA256
-#define SCTP_AUTH_NUM_HMACS (SCTP_AUTH_HMAC_ID_SHA256 + 1)
+#define SCTP_AUTH_HMAC_ID_MAX   __SCTP_AUTH_HMAC_MAX - 1
+#define SCTP_AUTH_NUM_HMACS     __SCTP_AUTH_HMAC_MAX
 #define SCTP_SHA1_SIG_SIZE 20
 #define SCTP_SHA256_SIG_SIZE 32
 
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index eb3113c38a94..002a00a4e6be 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -1184,6 +1184,9 @@ int sctp_bind_addr_copy(struct sctp_bind_addr *dest,
                         const struct sctp_bind_addr *src,
                         sctp_scope_t scope, gfp_t gfp,
                         int flags);
+int sctp_bind_addr_dup(struct sctp_bind_addr *dest,
+                        const struct sctp_bind_addr *src,
+                        gfp_t gfp);
 int sctp_add_bind_addr(struct sctp_bind_addr *, union sctp_addr *,
                        __u8 use_as_src, gfp_t gfp);
 int sctp_del_bind_addr(struct sctp_bind_addr *, union sctp_addr *);
diff --git a/include/net/sock.h b/include/net/sock.h
index 567e468d7492..67e35c7e230c 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -1236,6 +1236,9 @@ static inline struct sk_buff *sk_stream_alloc_pskb(struct sock *sk,
 {
         struct sk_buff *skb;
 
+        /* The TCP header must be at least 32-bit aligned.  */
+        size = ALIGN(size, 4);
+
         skb = alloc_skb_fclone(size + sk->sk_prot->max_header, gfp);
         if (skb) {
                 skb->truesize += mem;
diff --git a/include/net/tcp.h b/include/net/tcp.h
index d695cea7730d..cb5b033e0e59 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -1288,6 +1288,9 @@ static inline void tcp_insert_write_queue_before(struct sk_buff *new,
                                                   struct sock *sk)
 {
         __skb_insert(new, skb->prev, skb, &sk->sk_write_queue);
+
+        if (sk->sk_send_head == skb)
+                sk->sk_send_head = new;
 }
 
 static inline void tcp_unlink_write_queue(struct sk_buff *skb, struct sock *sk)
diff --git a/include/sound/version.h b/include/sound/version.h
index a2be8ad8894b..a9781eb0da09 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
 /* include/version.h.  Generated by alsa/ksync script.  */
 #define CONFIG_SND_VERSION "1.0.15"
-#define CONFIG_SND_DATE " (Tue Oct 23 06:09:18 2007 UTC)"
+#define CONFIG_SND_DATE " (Tue Nov 20 19:16:42 2007 UTC)"