34 files changed, 531 insertions, 797 deletions
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
index a12ac8ab2ad0..802891a9cd81 100644
--- a/include/asm-arm/arch-at91/at91rm9200.h
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -107,185 +107,4 @@
 #define AT91RM9200_UHP_BASE     0x00300000      /* USB Host controller */
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-#define AT91_PA0_MISO           (1 <<  0)       /* A: SPI Master-In Slave-Out */
-#define AT91_PA0_PCK3           (1 <<  0)       /* B: PMC Programmable Clock Output 3 */
-#define AT91_PA1_MOSI           (1 <<  1)       /* A: SPI Master-Out Slave-In */
-#define AT91_PA1_PCK0           (1 <<  1)       /* B: PMC Programmable Clock Output 0 */
-#define AT91_PA2_SPCK           (1 <<  2)       /* A: SPI Serial Clock */
-#define AT91_PA2_IRQ4           (1 <<  2)       /* B: External Interrupt 4 */
-#define AT91_PA3_NPCS0          (1 <<  3)       /* A: SPI Peripheral Chip Select 0 */
-#define AT91_PA3_IRQ5           (1 <<  3)       /* B: External Interrupt 5 */
-#define AT91_PA4_NPCS1          (1 <<  4)       /* A: SPI Peripheral Chip Select 1 */
-#define AT91_PA4_PCK1           (1 <<  4)       /* B: PMC Programmable Clock Output 1 */
-#define AT91_PA5_NPCS2          (1 <<  5)       /* A: SPI Peripheral Chip Select 2 */
-#define AT91_PA5_TXD3           (1 <<  5)       /* B: USART Transmit Data 3 */
-#define AT91_PA6_NPCS3          (1 <<  6)       /* A: SPI Peripheral Chip Select 3 */
-#define AT91_PA6_RXD3           (1 <<  6)       /* B: USART Receive Data 3 */
-#define AT91_PA7_ETXCK_EREFCK   (1 <<  7)       /* A: Ethernet Reference Clock / Transmit Clock */
-#define AT91_PA7_PCK2           (1 <<  7)       /* B: PMC Programmable Clock Output 2 */
-#define AT91_PA8_ETXEN          (1 <<  8)       /* A: Ethernet Transmit Enable */
-#define AT91_PA8_MCCDB          (1 <<  8)       /* B: MMC Multimedia Card B Command */
-#define AT91_PA9_ETX0           (1 <<  9)       /* A: Ethernet Transmit Data 0 */
-#define AT91_PA9_MCDB0          (1 <<  9)       /* B: MMC Multimedia Card B Data 0 */
-#define AT91_PA10_ETX1          (1 << 10)       /* A: Ethernet Transmit Data 1 */
-#define AT91_PA10_MCDB1         (1 << 10)       /* B: MMC Multimedia Card B Data 1 */
-#define AT91_PA11_ECRS_ECRSDV   (1 << 11)       /* A: Ethernet Carrier Sense / Data Valid */
-#define AT91_PA11_MCDB2         (1 << 11)       /* B: MMC Multimedia Card B Data 2 */
-#define AT91_PA12_ERX0          (1 << 12)       /* A: Ethernet Receive Data 0 */
-#define AT91_PA12_MCDB3         (1 << 12)       /* B: MMC Multimedia Card B Data 3 */
-#define AT91_PA13_ERX1          (1 << 13)       /* A: Ethernet Receive Data 1 */
-#define AT91_PA13_TCLK0         (1 << 13)       /* B: TC External Clock Input 0 */
-#define AT91_PA14_ERXER         (1 << 14)       /* A: Ethernet Receive Error */
-#define AT91_PA14_TCLK1         (1 << 14)       /* B: TC External Clock Input 1 */
-#define AT91_PA15_EMDC          (1 << 15)       /* A: Ethernet Management Data Clock */
-#define AT91_PA15_TCLK2         (1 << 15)       /* B: TC External Clock Input 2 */
-#define AT91_PA16_EMDIO         (1 << 16)       /* A: Ethernet Management Data I/O */
-#define AT91_PA16_IRQ6          (1 << 16)       /* B: External Interrupt 6 */
-#define AT91_PA17_TXD0          (1 << 17)       /* A: USART Transmit Data 0 */
-#define AT91_PA17_TIOA0         (1 << 17)       /* B: TC I/O Line A 0 */
-#define AT91_PA18_RXD0          (1 << 18)       /* A: USART Receive Data 0 */
-#define AT91_PA18_TIOB0         (1 << 18)       /* B: TC I/O Line B 0 */
-#define AT91_PA19_SCK0          (1 << 19)       /* A: USART Serial Clock 0 */
-#define AT91_PA19_TIOA1         (1 << 19)       /* B: TC I/O Line A 1 */
-#define AT91_PA20_CTS0          (1 << 20)       /* A: USART Clear To Send 0 */
-#define AT91_PA20_TIOB1         (1 << 20)       /* B: TC I/O Line B 1 */
-#define AT91_PA21_RTS0          (1 << 21)       /* A: USART Ready To Send 0 */
-#define AT91_PA21_TIOA2         (1 << 21)       /* B: TC I/O Line A 2 */
-#define AT91_PA22_RXD2          (1 << 22)       /* A: USART Receive Data 2 */
-#define AT91_PA22_TIOB2         (1 << 22)       /* B: TC I/O Line B 2 */
-#define AT91_PA23_TXD2          (1 << 23)       /* A: USART Transmit Data 2 */
-#define AT91_PA23_IRQ3          (1 << 23)       /* B: External Interrupt 3 */
-#define AT91_PA24_SCK2          (1 << 24)       /* A: USART Serial Clock 2 */
-#define AT91_PA24_PCK1          (1 << 24)       /* B: PMC Programmable Clock Output 1 */
-#define AT91_PA25_TWD           (1 << 25)       /* A: TWI Two-wire Serial Data */
-#define AT91_PA25_IRQ2          (1 << 25)       /* B: External Interrupt 2 */
-#define AT91_PA26_TWCK          (1 << 26)       /* A: TWI Two-wire Serial Clock */
-#define AT91_PA26_IRQ1          (1 << 26)       /* B: External Interrupt 1 */
-#define AT91_PA27_MCCK          (1 << 27)       /* A: MMC Multimedia Card Clock */
-#define AT91_PA27_TCLK3         (1 << 27)       /* B: TC External Clock Input 3 */
-#define AT91_PA28_MCCDA         (1 << 28)       /* A: MMC Multimedia Card A Command */
-#define AT91_PA28_TCLK4         (1 << 28)       /* B: TC External Clock Input 4 */
-#define AT91_PA29_MCDA0         (1 << 29)       /* A: MMC Multimedia Card A Data 0 */
-#define AT91_PA29_TCLK5         (1 << 29)       /* B: TC External Clock Input 5 */
-#define AT91_PA30_DRXD          (1 << 30)       /* A: DBGU Receive Data */
-#define AT91_PA30_CTS2          (1 << 30)       /* B: USART Clear To Send 2 */
-#define AT91_PA31_DTXD          (1 << 31)       /* A: DBGU Transmit Data */
-#define AT91_PA31_RTS2          (1 << 31)       /* B: USART Ready To Send 2 */
-#define AT91_PB0_TF0            (1 <<  0)       /* A: SSC Transmit Frame Sync 0 */
-#define AT91_PB0_RTS3           (1 <<  0)       /* B: USART Ready To Send 3 */
-#define AT91_PB1_TK0            (1 <<  1)       /* A: SSC Transmit Clock 0 */
-#define AT91_PB1_CTS3           (1 <<  1)       /* B: USART Clear To Send 3 */
-#define AT91_PB2_TD0            (1 <<  2)       /* A: SSC Transmit Data 0 */
-#define AT91_PB2_SCK3           (1 <<  2)       /* B: USART Serial Clock 3 */
-#define AT91_PB3_RD0            (1 <<  3)       /* A: SSC Receive Data 0 */
-#define AT91_PB3_MCDA1          (1 <<  3)       /* B: MMC Multimedia Card A Data 1 */
-#define AT91_PB4_RK0            (1 <<  4)       /* A: SSC Receive Clock 0 */
-#define AT91_PB4_MCDA2          (1 <<  4)       /* B: MMC Multimedia Card A Data 2 */
-#define AT91_PB5_RF0            (1 <<  5)       /* A: SSC Receive Frame Sync 0 */
-#define AT91_PB5_MCDA3          (1 <<  5)       /* B: MMC Multimedia Card A Data 3 */
-#define AT91_PB6_TF1            (1 <<  6)       /* A: SSC Transmit Frame Sync 1 */
-#define AT91_PB6_TIOA3          (1 <<  6)       /* B: TC I/O Line A 3 */
-#define AT91_PB7_TK1            (1 <<  7)       /* A: SSC Transmit Clock 1 */
-#define AT91_PB7_TIOB3          (1 <<  7)       /* B: TC I/O Line B 3 */
-#define AT91_PB8_TD1            (1 <<  8)       /* A: SSC Transmit Data 1 */
-#define AT91_PB8_TIOA4          (1 <<  8)       /* B: TC I/O Line A 4 */
-#define AT91_PB9_RD1            (1 <<  9)       /* A: SSC Receive Data 1 */
-#define AT91_PB9_TIOB4          (1 <<  9)       /* B: TC I/O Line B 4 */
-#define AT91_PB10_RK1           (1 << 10)       /* A: SSC Receive Clock 1 */
-#define AT91_PB10_TIOA5         (1 << 10)       /* B: TC I/O Line A 5 */
-#define AT91_PB11_RF1           (1 << 11)       /* A: SSC Receive Frame Sync 1 */
-#define AT91_PB11_TIOB5         (1 << 11)       /* B: TC I/O Line B 5 */
-#define AT91_PB12_TF2           (1 << 12)       /* A: SSC Transmit Frame Sync 2 */
-#define AT91_PB12_ETX2          (1 << 12)       /* B: Ethernet Transmit Data 2 */
-#define AT91_PB13_TK2           (1 << 13)       /* A: SSC Transmit Clock 3 */
-#define AT91_PB13_ETX3          (1 << 13)       /* B: Ethernet Transmit Data 3 */
-#define AT91_PB14_TD2           (1 << 14)       /* A: SSC Transmit Data 2 */
-#define AT91_PB14_ETXER         (1 << 14)       /* B: Ethernet Transmit Coding Error */
-#define AT91_PB15_RD2           (1 << 15)       /* A: SSC Receive Data 2 */
-#define AT91_PB15_ERX2          (1 << 15)       /* B: Ethernet Receive Data 2 */
-#define AT91_PB16_RK2           (1 << 16)       /* A: SSC Receive Clock 2 */
-#define AT91_PB16_ERX3          (1 << 16)       /* B: Ethernet Receive Data 3 */
-#define AT91_PB17_RF2           (1 << 17)       /* A: SSC Receive Frame Sync 2 */
-#define AT91_PB17_ERXDV         (1 << 17)       /* B: Ethernet Receive Data Valid */
-#define AT91_PB18_RI1           (1 << 18)       /* A: USART Ring Indicator 1 */
-#define AT91_PB18_ECOL          (1 << 18)       /* B: Ethernet Collision Detected */
-#define AT91_PB19_DTR1          (1 << 19)       /* A: USART Data Terminal Ready 1 */
-#define AT91_PB19_ERXCK         (1 << 19)       /* B: Ethernet Receive Clock */
-#define AT91_PB20_TXD1          (1 << 20)       /* A: USART Transmit Data 1 */
-#define AT91_PB21_RXD1          (1 << 21)       /* A: USART Receive Data 1 */
-#define AT91_PB22_SCK1          (1 << 22)       /* A: USART Serial Clock 1 */
-#define AT91_PB23_DCD1          (1 << 23)       /* A: USART Data Carrier Detect 1 */
-#define AT91_PB24_CTS1          (1 << 24)       /* A: USART Clear To Send 1 */
-#define AT91_PB25_DSR1          (1 << 25)       /* A: USART Data Set Ready 1 */
-#define AT91_PB25_EF100         (1 << 25)       /* B: Ethernet Force 100 Mbit */
-#define AT91_PB26_RTS1          (1 << 26)       /* A: USART Ready To Send 1 */
-#define AT91_PB27_PCK0          (1 << 27)       /* B: PMC Programmable Clock Output 0 */
-#define AT91_PB28_FIQ           (1 << 28)       /* A: Fast Interrupt */
-#define AT91_PB29_IRQ0          (1 << 29)       /* A: External Interrupt 0 */
-#define AT91_PC0_BFCK           (1 <<  0)       /* A: Burst Flash Clock */
-#define AT91_PC1_BFRDY_SMOE     (1 <<  1)       /* A: Burst Flash Ready / SmartMedia Output Enable */
-#define AT91_PC2_BFAVD          (1 <<  2)       /* A: Burst Flash Address Valid */
-#define AT91_PC3_BFBAA_SMWE     (1 <<  3)       /* A: Burst Flash Address Advance / SmartMedia Write Enable */
-#define AT91_PC4_BFOE           (1 <<  4)       /* A: Burst Flash Output Enable */
-#define AT91_PC5_BFWE           (1 <<  5)       /* A: Burst Flash Write Enable */
-#define AT91_PC6_NWAIT          (1 <<  6)       /* A: SMC Wait Signal */
-#define AT91_PC7_A23            (1 <<  7)       /* A: Address Bus 23 */
-#define AT91_PC8_A24            (1 <<  8)       /* A: Address Bus 24 */
-#define AT91_PC9_A25_CFRNW      (1 <<  9)       /* A: Address Bus 25 / Compact Flash Read Not Write */
-#define AT91_PC10_NCS4_CFCS     (1 << 10)       /* A: SMC Chip Select 4 / Compact Flash Chip Select */
-#define AT91_PC11_NCS5_CFCE1    (1 << 11)       /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
-#define AT91_PC12_NCS6_CFCE2    (1 << 12)       /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
-#define AT91_PC13_NCS7          (1 << 13)       /* A: Chip Select 7 */
-#define AT91_PD0_ETX0           (1 <<  0)       /* A: Ethernet Transmit Data 0 */
-#define AT91_PD1_ETX1           (1 <<  1)       /* A: Ethernet Transmit Data 1 */
-#define AT91_PD2_ETX2           (1 <<  2)       /* A: Ethernet Transmit Data 2 */
-#define AT91_PD3_ETX3           (1 <<  3)       /* A: Ethernet Transmit Data 3 */
-#define AT91_PD4_ETXEN          (1 <<  4)       /* A: Ethernet Transmit Enable */
-#define AT91_PD5_ETXER          (1 <<  5)       /* A: Ethernet Transmit Coding Error */
-#define AT91_PD6_DTXD           (1 <<  6)       /* A: DBGU Transmit Data */
-#define AT91_PD7_PCK0           (1 <<  7)       /* A: PMC Programmable Clock Output 0 */
-#define AT91_PD7_TSYNC          (1 <<  7)       /* B: ETM Trace Synchronization Signal */
-#define AT91_PD8_PCK1           (1 <<  8)       /* A: PMC Programmable Clock Output 1 */
-#define AT91_PD8_TCLK           (1 <<  8)       /* B: ETM Trace Clock */
-#define AT91_PD9_PCK2           (1 <<  9)       /* A: PMC Programmable Clock Output 2 */
-#define AT91_PD9_TPS0           (1 <<  9)       /* B: ETM Trace ARM Pipeline Status 0 */
-#define AT91_PD10_PCK3          (1 << 10)       /* A: PMC Programmable Clock Output 3 */
-#define AT91_PD10_TPS1          (1 << 10)       /* B: ETM Trace ARM Pipeline Status 1 */
-#define AT91_PD11_TPS2          (1 << 11)       /* B: ETM Trace ARM Pipeline Status 2 */
-#define AT91_PD12_TPK0          (1 << 12)       /* B: ETM Trace Packet Port 0 */
-#define AT91_PD13_TPK1          (1 << 13)       /* B: ETM Trace Packet Port 1 */
-#define AT91_PD14_TPK2          (1 << 14)       /* B: ETM Trace Packet Port 2 */
-#define AT91_PD15_TD0           (1 << 15)       /* A: SSC Transmit Data 0 */
-#define AT91_PD15_TPK3          (1 << 15)       /* B: ETM Trace Packet Port 3 */
-#define AT91_PD16_TD1           (1 << 16)       /* A: SSC Transmit Data 1 */
-#define AT91_PD16_TPK4          (1 << 16)       /* B: ETM Trace Packet Port 4 */
-#define AT91_PD17_TD2           (1 << 17)       /* A: SSC Transmit Data 2 */
-#define AT91_PD17_TPK5          (1 << 17)       /* B: ETM Trace Packet Port 5 */
-#define AT91_PD18_NPCS1         (1 << 18)       /* A: SPI Peripheral Chip Select 1 */
-#define AT91_PD18_TPK6          (1 << 18)       /* B: ETM Trace Packet Port 6 */
-#define AT91_PD19_NPCS2         (1 << 19)       /* A: SPI Peripheral Chip Select 2 */
-#define AT91_PD19_TPK7          (1 << 19)       /* B: ETM Trace Packet Port 7 */
-#define AT91_PD20_NPCS3         (1 << 20)       /* A: SPI Peripheral Chip Select 3 */
-#define AT91_PD20_TPK8          (1 << 20)       /* B: ETM Trace Packet Port 8 */
-#define AT91_PD21_RTS0          (1 << 21)       /* A: USART Ready To Send 0 */
-#define AT91_PD21_TPK9          (1 << 21)       /* B: ETM Trace Packet Port 9 */
-#define AT91_PD22_RTS1          (1 << 22)       /* A: USART Ready To Send 1 */
-#define AT91_PD22_TPK10         (1 << 22)       /* B: ETM Trace Packet Port 10 */
-#define AT91_PD23_RTS2          (1 << 23)       /* A: USART Ready To Send 2 */
-#define AT91_PD23_TPK11         (1 << 23)       /* B: ETM Trace Packet Port 11 */
-#define AT91_PD24_RTS3          (1 << 24)       /* A: USART Ready To Send 3 */
-#define AT91_PD24_TPK12         (1 << 24)       /* B: ETM Trace Packet Port 12 */
-#define AT91_PD25_DTR1          (1 << 25)       /* A: USART Data Terminal Ready 1 */
-#define AT91_PD25_TPK13         (1 << 25)       /* B: ETM Trace Packet Port 13 */
-#define AT91_PD26_TPK14         (1 << 26)       /* B: ETM Trace Packet Port 14 */
-#define AT91_PD27_TPK15         (1 << 27)       /* B: ETM Trace Packet Port 15 */
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index 2cadebc36af7..0427f8698c07 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -117,13 +117,4 @@
 #define AT91SAM9XE_SRAM_BASE    0x00300000      /* Internal SRAM base address */
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-// TODO: Add
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
index 01b58ffe2e27..9eb459570330 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -98,195 +98,4 @@
 #define AT91SAM9261_LCDC_BASE   0x00600000      /* LDC controller */
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-#define AT91_PA0_SPI0_MISO      (1 <<  0)       /* A: SPI0 Master In Slave */
-#define AT91_PA0_MCDA0          (1 <<  0)       /* B: Multimedia Card A Data 0 */
-#define AT91_PA1_SPI0_MOSI      (1 <<  1)       /* A: SPI0 Master Out Slave */
-#define AT91_PA1_MCCDA          (1 <<  1)       /* B: Multimedia Card A Command */
-#define AT91_PA2_SPI0_SPCK      (1 <<  2)       /* A: SPI0 Serial Clock */
-#define AT91_PA2_MCCK           (1 <<  2)       /* B: Multimedia Card Clock */
-#define AT91_PA3_SPI0_NPCS0     (1 <<  3)       /* A: SPI0 Peripheral Chip Select 0 */
-#define AT91_PA4_SPI0_NPCS1     (1 <<  4)       /* A: SPI0 Peripheral Chip Select 1 */
-#define AT91_PA4_MCDA1          (1 <<  4)       /* B: Multimedia Card A Data 1 */
-#define AT91_PA5_SPI0_NPCS2     (1 <<  5)       /* A: SPI0 Peripheral Chip Select 2 */
-#define AT91_PA5_MCDA2          (1 <<  5)       /* B: Multimedia Card A Data 2 */
-#define AT91_PA6_SPI0_NPCS3     (1 <<  6)       /* A: SPI0 Peripheral Chip Select 3 */
-#define AT91_PA6_MCDA3          (1 <<  6)       /* B: Multimedia Card A Data 3 */
-#define AT91_PA7_TWD            (1 <<  7)       /* A: TWI Two-wire Serial Data */
-#define AT91_PA7_PCK0           (1 <<  7)       /* B: PMC Programmable clock Output 0 */
-#define AT91_PA8_TWCK           (1 <<  8)       /* A: TWI Two-wire Serial Clock */
-#define AT91_PA8_PCK1           (1 <<  8)       /* B: PMC Programmable clock Output 1 */
-#define AT91_PA9_DRXD           (1 <<  9)       /* A: DBGU Debug Receive Data */
-#define AT91_PA9_PCK2           (1 <<  9)       /* B: PMC Programmable clock Output 2 */
-#define AT91_PA10_DTXD          (1 << 10)       /* A: DBGU Debug Transmit Data */
-#define AT91_PA10_PCK3          (1 << 10)       /* B: PMC Programmable clock Output 3 */
-#define AT91_PA11_TSYNC         (1 << 11)       /* A: Trace Synchronization Signal */
-#define AT91_PA11_SCK1          (1 << 11)       /* B: USART1 Serial Clock */
-#define AT91_PA12_TCLK          (1 << 12)       /* A: Trace Clock */
-#define AT91_PA12_RTS1          (1 << 12)       /* B: USART1 Ready To Send */
-#define AT91_PA13_TPS0          (1 << 13)       /* A: Trace ARM Pipeline Status 0 */
-#define AT91_PA13_CTS1          (1 << 13)       /* B: USART1 Clear To Send */
-#define AT91_PA14_TPS1          (1 << 14)       /* A: Trace ARM Pipeline Status 1 */
-#define AT91_PA14_SCK2          (1 << 14)       /* B: USART2 Serial Clock */
-#define AT91_PA15_TPS2          (1 << 15)       /* A: Trace ARM Pipeline Status 2 */
-#define AT91_PA15_RTS2          (1 << 15)       /* B: USART2 Ready To Send */
-#define AT91_PA16_TPK0          (1 << 16)       /* A: Trace Packet Port 0 */
-#define AT91_PA16_CTS2          (1 << 16)       /* B: USART2 Clear To Send */
-#define AT91_PA17_TPK1          (1 << 17)       /* A: Trace Packet Port 1 */
-#define AT91_PA17_TF1           (1 << 17)       /* B: SSC1 Transmit Frame Sync */
-#define AT91_PA18_TPK2          (1 << 18)       /* A: Trace Packet Port 2 */
-#define AT91_PA18_TK1           (1 << 18)       /* B: SSC1 Transmit Clock */
-#define AT91_PA19_TPK3          (1 << 19)       /* A: Trace Packet Port 3 */
-#define AT91_PA19_TD1           (1 << 19)       /* B: SSC1 Transmit Data */
-#define AT91_PA20_TPK4          (1 << 20)       /* A: Trace Packet Port 4 */
-#define AT91_PA20_RD1           (1 << 20)       /* B: SSC1 Receive Data */
-#define AT91_PA21_TPK5          (1 << 21)       /* A: Trace Packet Port 5 */
-#define AT91_PA21_RK1           (1 << 21)       /* B: SSC1 Receive Clock */
-#define AT91_PA22_TPK6          (1 << 22)       /* A: Trace Packet Port 6 */
-#define AT91_PA22_RF1           (1 << 22)       /* B: SSC1 Receive Frame Sync */
-#define AT91_PA23_TPK7          (1 << 23)       /* A: Trace Packet Port 7 */
-#define AT91_PA23_RTS0          (1 << 23)       /* B: USART0 Ready To Send */
-#define AT91_PA24_TPK8          (1 << 24)       /* A: Trace Packet Port 8 */
-#define AT91_PA24_SPI1_NPCS1    (1 << 24)       /* B: SPI1 Peripheral Chip Select 1 */
-#define AT91_PA25_TPK9          (1 << 25)       /* A: Trace Packet Port 9 */
-#define AT91_PA25_SPI1_NPCS2    (1 << 25)       /* B: SPI1 Peripheral Chip Select 2 */
-#define AT91_PA26_TPK10         (1 << 26)       /* A: Trace Packet Port 10 */
-#define AT91_PA26_SPI1_NPCS3    (1 << 26)       /* B: SPI1 Peripheral Chip Select 3 */
-#define AT91_PA27_TPK11         (1 << 27)       /* A: Trace Packet Port 11 */
-#define AT91_PA27_SPI0_NPCS1    (1 << 27)       /* B: SPI0 Peripheral Chip Select 1 */
-#define AT91_PA28_TPK12         (1 << 28)       /* A: Trace Packet Port 12 */
-#define AT91_PA28_SPI0_NPCS2    (1 << 28)       /* B: SPI0 Peripheral Chip Select 2 */
-#define AT91_PA29_TPK13         (1 << 29)       /* A: Trace Packet Port 13 */
-#define AT91_PA29_SPI0_NPCS3    (1 << 29)       /* B: SPI0 Peripheral Chip Select 3 */
-#define AT91_PA30_TPK14         (1 << 30)       /* A: Trace Packet Port 14 */
-#define AT91_PA30_A23           (1 << 30)       /* B: Address Bus bit 23 */
-#define AT91_PA31_TPK15         (1 << 31)       /* A: Trace Packet Port 15 */
-#define AT91_PA31_A24           (1 << 31)       /* B: Address Bus bit 24 */
-#define AT91_PB0_LCDVSYNC       (1 <<  0)       /* A: LCD Vertical Synchronization */
-#define AT91_PB1_LCDHSYNC       (1 <<  1)       /* A: LCD Horizontal Synchronization */
-#define AT91_PB2_LCDDOTCK       (1 <<  2)       /* A: LCD Dot Clock */
-#define AT91_PB2_PCK0           (1 <<  2)       /* B: PMC Programmable clock Output 0 */
-#define AT91_PB3_LCDDEN         (1 <<  3)       /* A: LCD Data Enable */
-#define AT91_PB4_LCDCC          (1 <<  4)       /* A: LCD Contrast Control */
-#define AT91_PB4_LCDD2          (1 <<  4)       /* B: LCD Data Bus Bit 2 */
-#define AT91_PB5_LCDD0          (1 <<  5)       /* A: LCD Data Bus Bit 0 */
-#define AT91_PB5_LCDD3          (1 <<  5)       /* B: LCD Data Bus Bit 3 */
-#define AT91_PB6_LCDD1          (1 <<  6)       /* A: LCD Data Bus Bit 1 */
-#define AT91_PB6_LCDD4          (1 <<  6)       /* B: LCD Data Bus Bit 4 */
-#define AT91_PB7_LCDD2          (1 <<  7)       /* A: LCD Data Bus Bit 2 */
-#define AT91_PB7_LCDD5          (1 <<  7)       /* B: LCD Data Bus Bit 5 */
-#define AT91_PB8_LCDD3          (1 <<  8)       /* A: LCD Data Bus Bit 3 */
-#define AT91_PB8_LCDD6          (1 <<  8)       /* B: LCD Data Bus Bit 6 */
-#define AT91_PB9_LCDD4          (1 <<  9)       /* A: LCD Data Bus Bit 4 */
-#define AT91_PB9_LCDD7          (1 <<  9)       /* B: LCD Data Bus Bit 7 */
-#define AT91_PB10_LCDD5         (1 << 10)       /* A: LCD Data Bus Bit 5 */
-#define AT91_PB10_LCDD10        (1 << 10)       /* B: LCD Data Bus Bit 10 */
-#define AT91_PB11_LCDD6         (1 << 11)       /* A: LCD Data Bus Bit 6 */
-#define AT91_PB11_LCDD11        (1 << 11)       /* B: LCD Data Bus Bit 11 */
-#define AT91_PB12_LCDD7         (1 << 12)       /* A: LCD Data Bus Bit 7 */
-#define AT91_PB12_LCDD12        (1 << 12)       /* B: LCD Data Bus Bit 12 */
-#define AT91_PB13_LCDD8         (1 << 13)       /* A: LCD Data Bus Bit 8 */
-#define AT91_PB13_LCDD13        (1 << 13)       /* B: LCD Data Bus Bit 13 */
-#define AT91_PB14_LCDD9         (1 << 14)       /* A: LCD Data Bus Bit 9 */
-#define AT91_PB14_LCDD14        (1 << 14)       /* B: LCD Data Bus Bit 14 */
-#define AT91_PB15_LCDD10        (1 << 15)       /* A: LCD Data Bus Bit 10 */
-#define AT91_PB15_LCDD15        (1 << 15)       /* B: LCD Data Bus Bit 15 */
-#define AT91_PB16_LCDD11        (1 << 16)       /* A: LCD Data Bus Bit 11 */
-#define AT91_PB16_LCDD19        (1 << 16)       /* B: LCD Data Bus Bit 19 */
-#define AT91_PB17_LCDD12        (1 << 17)       /* A: LCD Data Bus Bit 12 */
-#define AT91_PB17_LCDD20        (1 << 17)       /* B: LCD Data Bus Bit 20 */
-#define AT91_PB18_LCDD13        (1 << 18)       /* A: LCD Data Bus Bit 13 */
-#define AT91_PB18_LCDD21        (1 << 18)       /* B: LCD Data Bus Bit 21 */
-#define AT91_PB19_LCDD14        (1 << 19)       /* A: LCD Data Bus Bit 14 */
-#define AT91_PB19_LCDD22        (1 << 19)       /* B: LCD Data Bus Bit 22 */
-#define AT91_PB20_LCDD15        (1 << 20)       /* A: LCD Data Bus Bit 15 */
-#define AT91_PB20_LCDD23        (1 << 20)       /* B: LCD Data Bus Bit 23 */
-#define AT91_PB21_TF0           (1 << 21)       /* A: SSC0 Transmit Frame Sync */
-#define AT91_PB21_LCDD16        (1 << 21)       /* B: LCD Data Bus Bit 16 */
-#define AT91_PB22_TK0           (1 << 22)       /* A: SSC0 Transmit Clock */
-#define AT91_PB22_LCDD17        (1 << 22)       /* B: LCD Data Bus Bit 17 */
-#define AT91_PB23_TD0           (1 << 23)       /* A: SSC0 Transmit Data */
-#define AT91_PB23_LCDD18        (1 << 23)       /* B: LCD Data Bus Bit 18 */
-#define AT91_PB24_RD0           (1 << 24)       /* A: SSC0 Receive Data */
-#define AT91_PB24_LCDD19        (1 << 24)       /* B: LCD Data Bus Bit 19 */
-#define AT91_PB25_RK0           (1 << 25)       /* A: SSC0 Receive Clock */
-#define AT91_PB25_LCDD20        (1 << 25)       /* B: LCD Data Bus Bit 20 */
-#define AT91_PB26_RF0           (1 << 26)       /* A: SSC0 Receive Frame Sync */
-#define AT91_PB26_LCDD21        (1 << 26)       /* B: LCD Data Bus Bit 21 */
-#define AT91_PB27_SPI1_NPCS1    (1 << 27)       /* A: SPI1 Peripheral Chip Select 1 */
-#define AT91_PB27_LCDD22        (1 << 27)       /* B: LCD Data Bus Bit 22 */
-#define AT91_PB28_SPI1_NPCS0    (1 << 28)       /* A: SPI1 Peripheral Chip Select 0 */
-#define AT91_PB28_LCDD23        (1 << 28)       /* B: LCD Data Bus Bit 23 */
-#define AT91_PB29_SPI1_SPCK     (1 << 29)       /* A: SPI1 Serial Clock */
-#define AT91_PB29_IRQ2          (1 << 29)       /* B: Interrupt input 2 */
-#define AT91_PB30_SPI1_MISO     (1 << 30)       /* A: SPI1 Master In Slave */
-#define AT91_PB30_IRQ1          (1 << 30)       /* B: Interrupt input 1 */
-#define AT91_PB31_SPI1_MOSI     (1 << 31)       /* A: SPI1 Master Out Slave */
-#define AT91_PB31_PCK2          (1 << 31)       /* B: PMC Programmable clock Output 2 */
-#define AT91_PC0_SMOE           (1 << 0)        /* A: SmartMedia Output Enable */
-#define AT91_PC0_NCS6           (1 << 0)        /* B: Chip Select 6 */
-#define AT91_PC1_SMWE           (1 << 1)        /* A: SmartMedia Write Enable */
-#define AT91_PC1_NCS7           (1 << 1)        /* B: Chip Select 7 */
-#define AT91_PC2_NWAIT          (1 << 2)        /* A: NWAIT */
-#define AT91_PC2_IRQ0           (1 << 2)        /* B: Interrupt input 0 */
-#define AT91_PC3_A25_CFRNW      (1 << 3)        /* A: Address Bus[25] / Compact Flash Read Not Write */
-#define AT91_PC4_NCS4_CFCS0     (1 << 4)        /* A: Chip Select 4 / CompactFlash Chip Select 0 */
-#define AT91_PC5_NCS5_CFCS1     (1 << 5)        /* A: Chip Select 5 / CompactFlash Chip Select 1 */
-#define AT91_PC6_CFCE1          (1 << 6)        /* A: CompactFlash Chip Enable 1 */
-#define AT91_PC7_CFCE2          (1 << 7)        /* A: CompactFlash Chip Enable 2 */
-#define AT91_PC8_TXD0           (1 << 8)        /* A: USART0 Transmit Data */
-#define AT91_PC8_PCK2           (1 << 8)        /* B: PMC Programmable clock Output 2 */
-#define AT91_PC9_RXD0           (1 << 9)        /* A: USART0 Receive Data */
-#define AT91_PC9_PCK3           (1 << 9)        /* B: PMC Programmable clock Output 3 */
-#define AT91_PC10_RTS0          (1 << 10)       /* A: USART0 Ready To Send */
-#define AT91_PC10_SCK0          (1 << 10)       /* B: USART0 Serial Clock */
-#define AT91_PC11_CTS0          (1 << 11)       /* A: USART0 Clear To Send */
-#define AT91_PC11_FIQ           (1 << 11)       /* B: AIC Fast Interrupt Input */
-#define AT91_PC12_TXD1          (1 << 12)       /* A: USART1 Transmit Data */
-#define AT91_PC12_NCS6          (1 << 12)       /* B: Chip Select 6 */
-#define AT91_PC13_RXD1          (1 << 13)       /* A: USART1 Receive Data */
-#define AT91_PC13_NCS7          (1 << 13)       /* B: Chip Select 7 */
-#define AT91_PC14_TXD2          (1 << 14)       /* A: USART2 Transmit Data */
-#define AT91_PC14_SPI1_NPCS2    (1 << 14)       /* B: SPI1 Peripheral Chip Select 2 */
-#define AT91_PC15_RXD2          (1 << 15)       /* A: USART2 Receive Data */
-#define AT91_PC15_SPI1_NPCS3    (1 << 15)       /* B: SPI1 Peripheral Chip Select 3 */
-#define AT91_PC16_D16           (1 << 16)       /* A: Data Bus [16] */
-#define AT91_PC16_TCLK0         (1 << 16)       /* B: Timer Counter 0 external clock input */
-#define AT91_PC17_D17           (1 << 17)       /* A: Data Bus [17] */
-#define AT91_PC17_TCLK1         (1 << 17)       /* B: Timer Counter 1 external clock input */
-#define AT91_PC18_D18           (1 << 18)       /* A: Data Bus [18] */
-#define AT91_PC18_TCLK2         (1 << 18)       /* B: Timer Counter 2 external clock input */
-#define AT91_PC19_D19           (1 << 19)       /* A: Data Bus [19] */
-#define AT91_PC19_TIOA0         (1 << 19)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91_PC20_D20           (1 << 20)       /* A: Data Bus [20] */
-#define AT91_PC20_TIOB0         (1 << 20)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91_PC21_D21           (1 << 21)       /* A: Data Bus [21] */
-#define AT91_PC21_TIOA1         (1 << 21)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91_PC22_D22           (1 << 22)       /* A: Data Bus [22] */
-#define AT91_PC22_TIOB1         (1 << 22)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91_PC23_D23           (1 << 23)       /* A: Data Bus [23] */
-#define AT91_PC23_TIOA2         (1 << 23)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91_PC24_D24           (1 << 24)       /* A: Data Bus [24] */
-#define AT91_PC24_TIOB2         (1 << 24)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91_PC25_D25           (1 << 25)       /* A: Data Bus [25] */
-#define AT91_PC25_TF2           (1 << 25)       /* B: SSC2 Transmit Frame Sync */
-#define AT91_PC26_D26           (1 << 26)       /* A: Data Bus [26] */
-#define AT91_PC26_TK2           (1 << 26)       /* B: SSC2 Transmit Clock */
-#define AT91_PC27_D27           (1 << 27)       /* A: Data Bus [27] */
-#define AT91_PC27_TD2           (1 << 27)       /* B: SSC2 Transmit Data */
-#define AT91_PC28_D28           (1 << 28)       /* A: Data Bus [28] */
-#define AT91_PC28_RD2           (1 << 28)       /* B: SSC2 Receive Data */
-#define AT91_PC29_D29           (1 << 29)       /* A: Data Bus [29] */
-#define AT91_PC29_RK2           (1 << 29)       /* B: SSC2 Receive Clock */
-#define AT91_PC30_D30           (1 << 30)       /* A: Data Bus [30] */
-#define AT91_PC30_RF2           (1 << 30)       /* B: SSC2 Receive Frame Sync */
-#define AT91_PC31_D31           (1 << 31)       /* A: Data Bus [31] */
-#define AT91_PC31_PCK1          (1 << 31)       /* B: PMC Programmable clock Output 1 */
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index f4af68ae0ea9..115c47ac7ebb 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -119,13 +119,5 @@
 #define AT91SAM9263_DMAC_BASE   0x00800000      /* DMA Controller */
 #define AT91SAM9263_UHP_BASE    0x00a00000      /* USB Host controller */
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-// TODO: Add
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 7a34a5b1fed0..0ce6ee98ed0b 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -121,7 +121,7 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 /* AC97 */
 struct atmel_ac97_data {
        u8              reset_pin;      /* reset */
-}
+};
 extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
 /* LEDs */
diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h
index 6513065941d0..aec2d6563622 100644
--- a/include/asm-arm/arch-omap/aic23.h
+++ b/include/asm-arm/arch-omap/aic23.h
@@ -110,7 +110,7 @@
 #define TLV320AIC23ID1                  (0x1a)  // cs low
 #define TLV320AIC23ID2                  (0x1b)  // cs high
-void tlv320aic23_power_up(void);
+void aic23_power_up(void);
-void tlv320aic23_power_down(void);
+void aic23_power_down(void);
 #endif /* __ASM_ARCH_AIC23_H */
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h
index de0c5b792c58..dcb587b311f1 100644
--- a/include/asm-arm/arch-omap/board-apollon.h
+++ b/include/asm-arm/arch-omap/board-apollon.h
@@ -30,16 +30,7 @@
 #define __ASM_ARCH_OMAP_APOLLON_H
 /* Placeholder for APOLLON specific defines */
-/* GPMC CS0 */
-#define APOLLON_CS0_BASE                0x00000000
-/* GPMC CS1 */
-#define APOLLON_CS1_BASE                0x08000000
-#define APOLLON_ETHR_START              (APOLLON_CS1_BASE + 0x300)
 #define APOLLON_ETHR_GPIO_IRQ           74
-/* GPMC CS2 - reserved for OneNAND */
-#define APOLLON_CS2_BASE                0x10000000
-/* GPMC CS3 - reserved for NOR or NAND */
-#define APOLLON_CS3_BASE                0x18000000
 #endif /*  __ASM_ARCH_OMAP_APOLLON_H */
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
index 7ef664bc9e33..7e0efef4bb65 100644
--- a/include/asm-arm/arch-omap/board-h4.h
+++ b/include/asm-arm/arch-omap/board-h4.h
@@ -30,9 +30,6 @@
 #define __ASM_ARCH_OMAP_H4_H
 /* Placeholder for H4 specific defines */
-/* GPMC CS1 */
-#define OMAP24XX_ETHR_START             0x08000300
 #define OMAP24XX_ETHR_GPIO_IRQ          92
-#define H4_CS0_BASE                     0x04000000
 #endif /*  __ASM_ARCH_OMAP_H4_H */
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index 4fd717e626a2..031672c56377 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -12,6 +12,8 @@
 #include <linux/types.h>
+#include <asm/arch/gpio-switch.h>
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
 #define OMAP_TAG_MMC            0x4f02
@@ -99,26 +101,31 @@ struct omap_usb_config {
 struct omap_lcd_config {
        char panel_name[16];
        char ctrl_name[16];
+        s16  nreset_gpio;
+        u8   data_lines;
+};
+struct device;
+struct fb_info;
+struct omap_backlight_config {
+        int default_intensity;
+        int (*set_power)(struct device *dev, int state);
+        int (*check_fb)(struct fb_info *fb);
 };
 struct omap_fbmem_config {
-        u32 fb_sram_start;
+        u32 start;
-        u32 fb_sram_size;
+        u32 size;
-        u32 fb_sdram_start;
+};
-        u32 fb_sdram_size;
-};
+struct omap_pwm_led_platform_data {
+        const char *name;
-/* Cover:
+        int intensity_timer;
- *      high -> closed
+        int blink_timer;
- *      low  -> open
+        void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
- * Connection:
+};
- *      high -> connected
- *      low  -> disconnected
+/* See include/asm-arm/arch-omap/gpio-switch.h for definitions */
- */
-#define OMAP_GPIO_SWITCH_TYPE_COVER             0x0000
-#define OMAP_GPIO_SWITCH_TYPE_CONNECTION        0x0001
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
-#define OMAP_GPIO_SWITCH_FLAG_OUTPUT            0x0002
 struct omap_gpio_switch_config {
        char name[12];
        u16 gpio;
diff --git a/include/asm-arm/arch-omap/dsp.h b/include/asm-arm/arch-omap/dsp.h
deleted file mode 100644
index 06dad83dd41f..000000000000
--- a/include/asm-arm/arch-omap/dsp.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/dsp.h
- *
- * Header for OMAP DSP driver
- *
- * Copyright (C) 2002-2005 Nokia Corporation
- *
- * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * 2005/06/01:  DSP Gateway version 3.3
- */
-#ifndef ASM_ARCH_DSP_H
-#define ASM_ARCH_DSP_H
-/*
- * for /dev/dspctl/ctl
- */
-#define OMAP_DSP_IOCTL_RESET                    1
-#define OMAP_DSP_IOCTL_RUN                      2
-#define OMAP_DSP_IOCTL_SETRSTVECT               3
-#define OMAP_DSP_IOCTL_CPU_IDLE                 4
-#define OMAP_DSP_IOCTL_MPUI_WORDSWAP_ON         5
-#define OMAP_DSP_IOCTL_MPUI_WORDSWAP_OFF        6
-#define OMAP_DSP_IOCTL_MPUI_BYTESWAP_ON         7
-#define OMAP_DSP_IOCTL_MPUI_BYTESWAP_OFF        8
-#define OMAP_DSP_IOCTL_GBL_IDLE                 9
-#define OMAP_DSP_IOCTL_DSPCFG                   10
-#define OMAP_DSP_IOCTL_DSPUNCFG                 11
-#define OMAP_DSP_IOCTL_TASKCNT                  12
-#define OMAP_DSP_IOCTL_POLL                     13
-#define OMAP_DSP_IOCTL_REGMEMR                  40
-#define OMAP_DSP_IOCTL_REGMEMW                  41
-#define OMAP_DSP_IOCTL_REGIOR                   42
-#define OMAP_DSP_IOCTL_REGIOW                   43
-#define OMAP_DSP_IOCTL_GETVAR                   44
-#define OMAP_DSP_IOCTL_SETVAR                   45
-#define OMAP_DSP_IOCTL_RUNLEVEL                 50
-#define OMAP_DSP_IOCTL_SUSPEND                  51
-#define OMAP_DSP_IOCTL_RESUME                   52
-#define OMAP_DSP_IOCTL_FBEN                     53
-#define OMAP_DSP_IOCTL_FBDIS                    54
-#define OMAP_DSP_IOCTL_MBSEND                   99
-/*
- * for taskdev
- * (ioctls below should be >= 0x10000)
- */
-#define OMAP_DSP_TASK_IOCTL_BFLSH       0x10000
-#define OMAP_DSP_TASK_IOCTL_SETBSZ      0x10001
-#define OMAP_DSP_TASK_IOCTL_LOCK        0x10002
-#define OMAP_DSP_TASK_IOCTL_UNLOCK      0x10003
-#define OMAP_DSP_TASK_IOCTL_GETNAME     0x10004
-/*
- * for /dev/dspctl/mem
- */
-#define OMAP_DSP_MEM_IOCTL_EXMAP        1
-#define OMAP_DSP_MEM_IOCTL_EXUNMAP      2
-#define OMAP_DSP_MEM_IOCTL_EXMAP_FLUSH  3
-#define OMAP_DSP_MEM_IOCTL_FBEXPORT     5
-#define OMAP_DSP_MEM_IOCTL_MMUITACK     7
-#define OMAP_DSP_MEM_IOCTL_MMUINIT      9
-#define OMAP_DSP_MEM_IOCTL_KMEM_RESERVE 11
-#define OMAP_DSP_MEM_IOCTL_KMEM_RELEASE 12
-struct omap_dsp_mapinfo {
-        unsigned long dspadr;
-        unsigned long size;
-};
-/*
- * for /dev/dspctl/twch
- */
-#define OMAP_DSP_TWCH_IOCTL_MKDEV       1
-#define OMAP_DSP_TWCH_IOCTL_RMDEV       2
-#define OMAP_DSP_TWCH_IOCTL_TADD        11
-#define OMAP_DSP_TWCH_IOCTL_TDEL        12
-#define OMAP_DSP_TWCH_IOCTL_TKILL       13
-#define OMAP_DSP_DEVSTATE_NOTASK        0x00000001
-#define OMAP_DSP_DEVSTATE_ATTACHED      0x00000002
-#define OMAP_DSP_DEVSTATE_GARBAGE       0x00000004
-#define OMAP_DSP_DEVSTATE_INVALID       0x00000008
-#define OMAP_DSP_DEVSTATE_ADDREQ        0x00000100
-#define OMAP_DSP_DEVSTATE_DELREQ        0x00000200
-#define OMAP_DSP_DEVSTATE_ADDFAIL       0x00001000
-#define OMAP_DSP_DEVSTATE_ADDING        0x00010000
-#define OMAP_DSP_DEVSTATE_DELING        0x00020000
-#define OMAP_DSP_DEVSTATE_KILLING       0x00040000
-#define OMAP_DSP_DEVSTATE_STATE_MASK    0x7fffffff
-#define OMAP_DSP_DEVSTATE_STALE         0x80000000
-struct omap_dsp_taddinfo {
-        unsigned char minor;
-        unsigned long taskadr;
-};
-#define OMAP_DSP_TADD_ABORTADR  0xffffffff
-/*
- * error cause definition (for error detection device)
- */
-#define OMAP_DSP_ERRDT_WDT      0x00000001
-#define OMAP_DSP_ERRDT_MMU      0x00000002
-/*
- * mailbox protocol definitions
- */
-struct omap_dsp_mailbox_cmd {
-        unsigned short cmd;
-        unsigned short data;
-};
-struct omap_dsp_reginfo {
-        unsigned short adr;
-        unsigned short val;
-};
-struct omap_dsp_varinfo {
-        unsigned char varid;
-        unsigned short val[0];
-};
-#define OMAP_DSP_MBPROT_REVISION        0x0019
-#define OMAP_DSP_MBCMD_WDSND    0x10
-#define OMAP_DSP_MBCMD_WDREQ    0x11
-#define OMAP_DSP_MBCMD_BKSND    0x20
-#define OMAP_DSP_MBCMD_BKREQ    0x21
-#define OMAP_DSP_MBCMD_BKYLD    0x23
-#define OMAP_DSP_MBCMD_BKSNDP   0x24
-#define OMAP_DSP_MBCMD_BKREQP   0x25
-#define OMAP_DSP_MBCMD_TCTL     0x30
-#define OMAP_DSP_MBCMD_TCTLDATA 0x31
-#define OMAP_DSP_MBCMD_POLL     0x32
-#define OMAP_DSP_MBCMD_WDT      0x50    /* v3.3: obsolete */
-#define OMAP_DSP_MBCMD_RUNLEVEL 0x51
-#define OMAP_DSP_MBCMD_PM       0x52
-#define OMAP_DSP_MBCMD_SUSPEND  0x53
-#define OMAP_DSP_MBCMD_KFUNC    0x54
-#define OMAP_DSP_MBCMD_TCFG     0x60
-#define OMAP_DSP_MBCMD_TADD     0x62
-#define OMAP_DSP_MBCMD_TDEL     0x63
-#define OMAP_DSP_MBCMD_TSTOP    0x65
-#define OMAP_DSP_MBCMD_DSPCFG   0x70
-#define OMAP_DSP_MBCMD_REGRW    0x72
-#define OMAP_DSP_MBCMD_GETVAR   0x74
-#define OMAP_DSP_MBCMD_SETVAR   0x75
-#define OMAP_DSP_MBCMD_ERR      0x78
-#define OMAP_DSP_MBCMD_DBG      0x79
-#define OMAP_DSP_MBCMD_TCTL_TINIT       0x0000
-#define OMAP_DSP_MBCMD_TCTL_TEN         0x0001
-#define OMAP_DSP_MBCMD_TCTL_TDIS        0x0002
-#define OMAP_DSP_MBCMD_TCTL_TCLR        0x0003
-#define OMAP_DSP_MBCMD_TCTL_TCLR_FORCE  0x0004
-#define OMAP_DSP_MBCMD_RUNLEVEL_USER            0x01
-#define OMAP_DSP_MBCMD_RUNLEVEL_SUPER           0x0e
-#define OMAP_DSP_MBCMD_RUNLEVEL_RECOVERY        0x10
-#define OMAP_DSP_MBCMD_PM_DISABLE       0x00
-#define OMAP_DSP_MBCMD_PM_ENABLE        0x01
-#define OMAP_DSP_MBCMD_KFUNC_FBCTL      0x00
-#define OMAP_DSP_MBCMD_KFUNC_AUDIO_PWR  0x01
-#define OMAP_DSP_MBCMD_FBCTL_UPD        0x0000
-#define OMAP_DSP_MBCMD_FBCTL_ENABLE     0x0002
-#define OMAP_DSP_MBCMD_FBCTL_DISABLE    0x0003
-#define OMAP_DSP_MBCMD_AUDIO_PWR_UP     0x0000
-#define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN1  0x0001
-#define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN2  0x0002
-#define OMAP_DSP_MBCMD_TDEL_SAFE        0x0000
-#define OMAP_DSP_MBCMD_TDEL_KILL        0x0001
-#define OMAP_DSP_MBCMD_DSPCFG_REQ       0x00
-#define OMAP_DSP_MBCMD_DSPCFG_SYSADRH   0x28
-#define OMAP_DSP_MBCMD_DSPCFG_SYSADRL   0x29
-#define OMAP_DSP_MBCMD_DSPCFG_PROTREV   0x70
-#define OMAP_DSP_MBCMD_DSPCFG_ABORT     0x78
-#define OMAP_DSP_MBCMD_DSPCFG_LAST      0x80
-#define OMAP_DSP_MBCMD_REGRW_MEMR       0x00
-#define OMAP_DSP_MBCMD_REGRW_MEMW       0x01
-#define OMAP_DSP_MBCMD_REGRW_IOR        0x02
-#define OMAP_DSP_MBCMD_REGRW_IOW        0x03
-#define OMAP_DSP_MBCMD_REGRW_DATA       0x04
-#define OMAP_DSP_MBCMD_VARID_ICRMASK    0x00
-#define OMAP_DSP_MBCMD_VARID_LOADINFO   0x01
-#define OMAP_DSP_TTYP_ARCV      0x0001
-#define OMAP_DSP_TTYP_ASND      0x0002
-#define OMAP_DSP_TTYP_BKMD      0x0004
-#define OMAP_DSP_TTYP_BKDM      0x0008
-#define OMAP_DSP_TTYP_PVMD      0x0010
-#define OMAP_DSP_TTYP_PVDM      0x0020
-#define OMAP_DSP_EID_BADTID     0x10
-#define OMAP_DSP_EID_BADTCN     0x11
-#define OMAP_DSP_EID_BADBID     0x20
-#define OMAP_DSP_EID_BADCNT     0x21
-#define OMAP_DSP_EID_NOTLOCKED  0x22
-#define OMAP_DSP_EID_STVBUF     0x23
-#define OMAP_DSP_EID_BADADR     0x24
-#define OMAP_DSP_EID_BADTCTL    0x30
-#define OMAP_DSP_EID_BADPARAM   0x50
-#define OMAP_DSP_EID_FATAL      0x58
-#define OMAP_DSP_EID_NOMEM      0xc0
-#define OMAP_DSP_EID_NORES      0xc1
-#define OMAP_DSP_EID_IPBFULL    0xc2
-#define OMAP_DSP_EID_WDT        0xd0
-#define OMAP_DSP_EID_TASKNOTRDY 0xe0
-#define OMAP_DSP_EID_TASKBSY    0xe1
-#define OMAP_DSP_EID_TASKERR    0xef
-#define OMAP_DSP_EID_BADCFGTYP  0xf0
-#define OMAP_DSP_EID_DEBUG      0xf8
-#define OMAP_DSP_EID_BADSEQ     0xfe
-#define OMAP_DSP_EID_BADCMD     0xff
-#define OMAP_DSP_TNM_LEN        16
-#define OMAP_DSP_TID_FREE       0xff
-#define OMAP_DSP_TID_ANON       0xfe
-#define OMAP_DSP_BID_NULL       0xffff
-#define OMAP_DSP_BID_PVT        0xfffe
-#endif /* ASM_ARCH_DSP_H */
diff --git a/include/asm-arm/arch-omap/dsp_common.h b/include/asm-arm/arch-omap/dsp_common.h
index 16a459dfa714..c61f868f24ee 100644
--- a/include/asm-arm/arch-omap/dsp_common.h
+++ b/include/asm-arm/arch-omap/dsp_common.h
@@ -1,38 +1,34 @@
 /*
- * linux/include/asm-arm/arch-omap/dsp_common.h
+ * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
 *
- * Header for OMAP DSP subsystem control
+ * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
 *
- * Copyright (C) 2004,2005 Nokia Corporation
+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
 *
- * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
 *
- * This program is free software; you can redistribute it and/or modify
+ * This program is distributed in the hope that it will be useful, but
- * it under the terms of the GNU General Public License as published by
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
- * the Free Software Foundation; either version 2 of the License, or
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * (at your option) any later version.
+ * General Public License for more details.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
 *
- * 2005/06/03:  DSP Gateway version 3.3
 */
 #ifndef ASM_ARCH_DSP_COMMON_H
 #define ASM_ARCH_DSP_COMMON_H
+#ifdef CONFIG_ARCH_OMAP1
 extern void omap_dsp_request_mpui(void);
 extern void omap_dsp_release_mpui(void);
 extern int omap_dsp_request_mem(void);
 extern int omap_dsp_release_mem(void);
+#endif
-extern void (*omap_dsp_audio_pwr_up_request)(int stage);
-extern void (*omap_dsp_audio_pwr_down_request)(int stage);
 #endif /* ASM_ARCH_DSP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/gpio-switch.h b/include/asm-arm/arch-omap/gpio-switch.h
new file mode 100644
index 000000000000..10da0e07c0cf
--- /dev/null
+++ b/include/asm-arm/arch-omap/gpio-switch.h
@@ -0,0 +1,54 @@
+/*
+ * GPIO switch definitions
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
+#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
+#include <linux/types.h>
+/* Cover:
+ *      high -> closed
+ *      low  -> open
+ * Connection:
+ *      high -> connected
+ *      low  -> disconnected
+ * Activity:
+ *      high -> active
+ *      low  -> inactive
+ *
+ */
+#define OMAP_GPIO_SWITCH_TYPE_COVER             0x0000
+#define OMAP_GPIO_SWITCH_TYPE_CONNECTION        0x0001
+#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY          0x0002
+#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT            0x0002
+struct omap_gpio_switch {
+        const char *name;
+        s16 gpio;
+        unsigned flags:4;
+        unsigned type:4;
+        /* Time in ms to debounce when transitioning from
+         * inactive state to active state. */
+        u16 debounce_rising;
+        /* Same for transition from active to inactive state. */
+        u16 debounce_falling;
+        /* notify board-specific code about state changes */
+        void (* notify)(void *data, int state);
+        void *notify_data;
+};
+/* Call at init time only */
+extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
+                                        int count);
+#endif
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
index 7c03ef6c14c4..995cc83482eb 100644
--- a/include/asm-arm/arch-omap/gpmc.h
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -87,5 +87,7 @@ extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
+extern int gpmc_cs_set_reserved(int cs, int reserved);
+extern int gpmc_cs_reserved(int cs);
 #endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 481048d65214..e225f4f39b34 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -267,6 +267,15 @@
 #define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
 /*
+ * ----------------------------------------------------------------------------
+ * Pulse-Width Light
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_PWL_BASE                   0xfffb5800
+#define OMAP_PWL_ENABLE                 (OMAP_PWL_BASE + 0x00)
+#define OMAP_PWL_CLK_ENABLE             (OMAP_PWL_BASE + 0x04)
+/*
 * ---------------------------------------------------------------------------
 * Processor specific defines
 * ---------------------------------------------------------------------------
diff --git a/include/asm-arm/arch-omap/hwa742.h b/include/asm-arm/arch-omap/hwa742.h
new file mode 100644
index 000000000000..577f492f2d3c
--- /dev/null
+++ b/include/asm-arm/arch-omap/hwa742.h
@@ -0,0 +1,12 @@
+#ifndef _HWA742_H
+#define _HWA742_H
+struct hwa742_platform_data {
+        void            (*power_up)(struct device *dev);
+        void            (*power_down)(struct device *dev);
+        unsigned long   (*get_clock_rate)(struct device *dev);
+        unsigned        te_connected:1;
+};
+#endif
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 78f68e6a4f0c..4aca7e3d7566 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -77,6 +77,17 @@
 #define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
 #define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
+/* DSP */
+#define DSP_MEM_24XX_PHYS       OMAP24XX_DSP_MEM_BASE   /* 0x58000000 */
+#define DSP_MEM_24XX_VIRT       0xe0000000
+#define DSP_MEM_24XX_SIZE       0x28000
+#define DSP_IPI_24XX_PHYS       OMAP24XX_DSP_IPI_BASE   /* 0x59000000 */
+#define DSP_IPI_24XX_VIRT       0xe1000000
+#define DSP_IPI_24XX_SIZE       SZ_4K
+#define DSP_MMU_24XX_PHYS       OMAP24XX_DSP_MMU_BASE   /* 0x5a000000 */
+#define DSP_MMU_24XX_VIRT       0xe2000000
+#define DSP_MMU_24XX_SIZE       SZ_4K
 #endif
 #ifndef __ASSEMBLER__
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index c5bb05a69b81..3ede58b51db2 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -37,8 +37,6 @@
 #define INT_DSP_MMU_ABORT       7
 #define INT_HOST                8
 #define INT_ABORT               9
-#define INT_DSP_MAILBOX1        10
-#define INT_DSP_MAILBOX2        11
 #define INT_BRIDGE_PRIV         13
 #define INT_GPIO_BANK1          14
 #define INT_UART3               15
@@ -63,6 +61,8 @@
 #define INT_1510_RES2           2
 #define INT_1510_SPI_TX         4
 #define INT_1510_SPI_RX         5
+#define INT_1510_DSP_MAILBOX1   10
+#define INT_1510_DSP_MAILBOX2   11
 #define INT_1510_RES12          12
 #define INT_1510_LB_MMU         17
 #define INT_1510_RES18          18
@@ -75,6 +75,8 @@
 #define INT_1610_IH2_FIQ        2
 #define INT_1610_McBSP2_TX      4
 #define INT_1610_McBSP2_RX      5
+#define INT_1610_DSP_MAILBOX1   10
+#define INT_1610_DSP_MAILBOX2   11
 #define INT_1610_LCD_LINE       12
 #define INT_1610_GPTIMER1       17
 #define INT_1610_GPTIMER2       18
@@ -131,11 +133,11 @@
 #define INT_RTC_TIMER           (25 + IH2_BASE)
 #define INT_RTC_ALARM           (26 + IH2_BASE)
 #define INT_MEM_STICK           (27 + IH2_BASE)
-#define INT_DSP_MMU             (28 + IH2_BASE)
 /*
 * OMAP-1510 specific IRQ numbers for interrupt handler 2
 */
+#define INT_1510_DSP_MMU        (28 + IH2_BASE)
 #define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
 /*
@@ -146,6 +148,7 @@
 #define INT_1610_USB_OTG        (8 + IH2_BASE)
 #define INT_1610_SoSSI          (9 + IH2_BASE)
 #define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
+#define INT_1610_DSP_MMU        (28 + IH2_BASE)
 #define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
 #define INT_1610_STI            (32 + IH2_BASE)
 #define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
@@ -239,10 +242,15 @@
 #define INT_24XX_SDMA_IRQ3      15
 #define INT_24XX_CAM_IRQ        24
 #define INT_24XX_DSS_IRQ        25
+#define INT_24XX_MAIL_U0_MPU    26
+#define INT_24XX_DSP_UMA        27
+#define INT_24XX_DSP_MMU        28
 #define INT_24XX_GPIO_BANK1     29
 #define INT_24XX_GPIO_BANK2     30
 #define INT_24XX_GPIO_BANK3     31
 #define INT_24XX_GPIO_BANK4     32
+#define INT_24XX_GPIO_BANK5     33
+#define INT_24XX_MAIL_U3_MPU    34
 #define INT_24XX_GPTIMER1       37
 #define INT_24XX_GPTIMER2       38
 #define INT_24XX_GPTIMER3       39
@@ -262,6 +270,12 @@
 #define INT_24XX_UART1_IRQ      72
 #define INT_24XX_UART2_IRQ      73
 #define INT_24XX_UART3_IRQ      74
+#define INT_24XX_USB_IRQ_GEN    75
+#define INT_24XX_USB_IRQ_NISO   76
+#define INT_24XX_USB_IRQ_ISO    77
+#define INT_24XX_USB_IRQ_HGEN   78
+#define INT_24XX_USB_IRQ_HSOF   79
+#define INT_24XX_USB_IRQ_OTG    80
 #define INT_24XX_MMC_IRQ        83
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
diff --git a/include/asm-arm/arch-omap/lcd_lph8923.h b/include/asm-arm/arch-omap/lcd_lph8923.h
deleted file mode 100644
index 004e67e22ca7..000000000000
--- a/include/asm-arm/arch-omap/lcd_lph8923.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __LCD_LPH8923_H
-#define __LCD_LPH8923_H
-enum lcd_lph8923_test_num {
-        LCD_LPH8923_TEST_RGB_LINES,
-};
-enum lcd_lph8923_test_result {
-        LCD_LPH8923_TEST_SUCCESS,
-        LCD_LPH8923_TEST_INVALID,
-        LCD_LPH8923_TEST_FAILED,
-};
-#endif
diff --git a/include/asm-arm/arch-omap/lcd_mipid.h b/include/asm-arm/arch-omap/lcd_mipid.h
new file mode 100644
index 000000000000..f8fbc4801e52
--- /dev/null
+++ b/include/asm-arm/arch-omap/lcd_mipid.h
@@ -0,0 +1,24 @@
+#ifndef __LCD_MIPID_H
+#define __LCD_MIPID_H
+enum mipid_test_num {
+        MIPID_TEST_RGB_LINES,
+};
+enum mipid_test_result {
+        MIPID_TEST_SUCCESS,
+        MIPID_TEST_INVALID,
+        MIPID_TEST_FAILED,
+};
+#ifdef __KERNEL__
+struct mipid_platform_data {
+        int     nreset_gpio;
+        int     data_lines;
+        void    (*shutdown)(struct mipid_platform_data *pdata);
+};
+#endif
+#endif
diff --git a/include/asm-arm/arch-omap/led.h b/include/asm-arm/arch-omap/led.h
new file mode 100644
index 000000000000..f3acae28e2da
--- /dev/null
+++ b/include/asm-arm/arch-omap/led.h
@@ -0,0 +1,24 @@
+/*
+ *  linux/include/asm-arm/arch-omap/led.h
+ *
+ *  Copyright (C) 2006 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_ARCH_LED_H
+#define ASMARM_ARCH_LED_H
+struct omap_led_config {
+        struct led_classdev     cdev;
+        s16                     gpio;
+};
+struct omap_led_platform_data {
+        s16                     nr_leds;
+        struct omap_led_config  *leds;
+};
+#endif
diff --git a/include/asm-arm/arch-omap/mailbox.h b/include/asm-arm/arch-omap/mailbox.h
new file mode 100644
index 000000000000..4bf0909461f2
--- /dev/null
+++ b/include/asm-arm/arch-omap/mailbox.h
@@ -0,0 +1,73 @@
+/* mailbox.h */
+#ifndef MAILBOX_H
+#define MAILBOX_H
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <linux/blkdev.h>
+typedef u32 mbox_msg_t;
+typedef void (mbox_receiver_t)(mbox_msg_t msg);
+struct omap_mbox;
+typedef int __bitwise omap_mbox_irq_t;
+#define IRQ_TX ((__force omap_mbox_irq_t) 1)
+#define IRQ_RX ((__force omap_mbox_irq_t) 2)
+typedef int __bitwise omap_mbox_type_t;
+#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
+#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
+struct omap_mbox_ops {
+        omap_mbox_type_t        type;
+        int             (*startup)(struct omap_mbox *mbox);
+        void            (*shutdown)(struct omap_mbox *mbox);
+        /* fifo */
+        mbox_msg_t      (*fifo_read)(struct omap_mbox *mbox);
+        void            (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
+        int             (*fifo_empty)(struct omap_mbox *mbox);
+        int             (*fifo_full)(struct omap_mbox *mbox);
+        /* irq */
+        void            (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        void            (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        void            (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        int             (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+};
+struct omap_mbox_queue {
+        spinlock_t              lock;
+        request_queue_t         *queue;
+        struct work_struct      work;
+        int     (*callback)(void *);
+        struct omap_mbox        *mbox;
+};
+struct omap_mbox {
+        char                    *name;
+        unsigned int            irq;
+        struct omap_mbox_queue  *txq, *rxq;
+        struct omap_mbox_ops    *ops;
+        mbox_msg_t              seq_snd, seq_rcv;
+        struct device           dev;
+        struct omap_mbox        *next;
+        void                    *priv;
+        void                    (*err_notify)(void);
+};
+int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
+void omap_mbox_init_seq(struct omap_mbox *);
+struct omap_mbox *omap_mbox_get(const char *);
+void omap_mbox_put(struct omap_mbox *);
+int omap_mbox_register(struct omap_mbox *);
+int omap_mbox_unregister(struct omap_mbox *);
+#endif /* MAILBOX_H */
diff --git a/include/asm-arm/arch-omap/mcspi.h b/include/asm-arm/arch-omap/mcspi.h
index 9e7f40a88e1b..1254e4945b6f 100644
--- a/include/asm-arm/arch-omap/mcspi.h
+++ b/include/asm-arm/arch-omap/mcspi.h
@@ -2,7 +2,6 @@
 #define _OMAP2_MCSPI_H
 struct omap2_mcspi_platform_config {
-        unsigned long   base;
        unsigned short  num_cs;
 };
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index 48fabc493163..14cba97c18ad 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -86,5 +86,18 @@
 #endif  /* CONFIG_ARCH_OMAP15XX */
+/* Override the ARM default */
+#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
+#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
+#endif
+#define CONSISTENT_DMA_SIZE \
+        (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
+#endif
 #endif
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h
index 88cd4c87f0de..82d276a6bd95 100644
--- a/include/asm-arm/arch-omap/menelaus.h
+++ b/include/asm-arm/arch-omap/menelaus.h
@@ -7,10 +7,19 @@
 #ifndef __ASM_ARCH_MENELAUS_H
 #define __ASM_ARCH_MENELAUS_H
-extern void menelaus_mmc_register(void (*callback)(unsigned long data, u8 card_mask),
+extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
-                                  unsigned long data);
+                                          void *data);
-extern void menelaus_mmc_remove(void);
+extern void menelaus_unregister_mmc_callback(void);
-extern void menelaus_mmc_opendrain(int enable);
+extern int menelaus_set_mmc_opendrain(int slot, int enable);
+extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
+extern int menelaus_set_vmem(unsigned int mV);
+extern int menelaus_set_vio(unsigned int mV);
+extern int menelaus_set_vmmc(unsigned int mV);
+extern int menelaus_set_vaux(unsigned int mV);
+extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
+extern int menelaus_set_slot_sel(int enable);
+extern int menelaus_get_slot_pin_states(void);
 #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
 #define omap_has_menelaus()     1
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
index f0c7f0fb4dc0..f7f5cdfdccce 100644
--- a/include/asm-arm/arch-omap/omap16xx.h
+++ b/include/asm-arm/arch-omap/omap16xx.h
@@ -159,15 +159,6 @@
 #define UART3_MVR               (OMAP_UART3_BASE + 0x50)
 /*
- * ----------------------------------------------------------------------------
- * Pulse-Width Light
- * ----------------------------------------------------------------------------
- */
-#define OMAP16XX_PWL_BASE       (0xfffb5800)
-#define OMAP16XX_PWL_ENABLE     (OMAP16XX_PWL_BASE + 0x00)
-#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
-/*
 * ---------------------------------------------------------------------------
 * Watchdog timer
 * ---------------------------------------------------------------------------
@@ -199,5 +190,8 @@
 #define WSPR_DISABLE_0         (0x0000aaaa)
 #define WSPR_DISABLE_1         (0x00005555)
+/* Mailbox */
+#define OMAP16XX_MAILBOX_BASE   (0xfffcf000)
 #endif /*  __ASM_ARCH_OMAP16XX_H */
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 6e59805fa654..708b2fac77f2 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -20,5 +20,14 @@
 #define OMAP24XX_PRCM_BASE      (L4_24XX_BASE + 0x8000)
 #define OMAP24XX_SDRC_BASE      (L3_24XX_BASE + 0x9000)
+/* DSP SS */
+#define OMAP24XX_DSP_BASE       0x58000000
+#define OMAP24XX_DSP_MEM_BASE   (OMAP24XX_DSP_BASE + 0x0)
+#define OMAP24XX_DSP_IPI_BASE   (OMAP24XX_DSP_BASE + 0x1000000)
+#define OMAP24XX_DSP_MMU_BASE   (OMAP24XX_DSP_BASE + 0x2000000)
+/* Mailbox */
+#define OMAP24XX_MAILBOX_BASE   (L4_24XX_BASE + 0x94000)
 #endif /* __ASM_ARCH_OMAP24XX_H */
diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h
index fccdb3db025f..46d7a4f60854 100644
--- a/include/asm-arm/arch-omap/omapfb.h
+++ b/include/asm-arm/arch-omap/omapfb.h
@@ -24,6 +24,9 @@
 #ifndef __OMAPFB_H
 #define __OMAPFB_H
+#include <asm/ioctl.h>
+#include <asm/types.h>
 /* IOCTL commands. */
 #define OMAP_IOW(num, dtype)    _IOW('O', num, dtype)
@@ -35,26 +38,46 @@
 #define OMAPFB_SYNC_GFX         OMAP_IO(37)
 #define OMAPFB_VSYNC            OMAP_IO(38)
 #define OMAPFB_SET_UPDATE_MODE  OMAP_IOW(40, int)
-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(41, struct omapfb_update_window_old)
+#define OMAPFB_GET_CAPS         OMAP_IOR(42, struct omapfb_caps)
-#define OMAPFB_GET_CAPS         OMAP_IOR(42, unsigned long)
 #define OMAPFB_GET_UPDATE_MODE  OMAP_IOW(43, int)
 #define OMAPFB_LCD_TEST         OMAP_IOW(45, int)
 #define OMAPFB_CTRL_TEST        OMAP_IOW(46, int)
-#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(47, struct omapfb_update_window)
+#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
-#define OMAPFB_SETUP_PLANE      OMAP_IOW(48, struct omapfb_setup_plane)
-#define OMAPFB_ENABLE_PLANE     OMAP_IOW(49, struct omapfb_enable_plane)
 #define OMAPFB_SET_COLOR_KEY    OMAP_IOW(50, struct omapfb_color_key)
+#define OMAPFB_GET_COLOR_KEY    OMAP_IOW(51, struct omapfb_color_key)
+#define OMAPFB_SETUP_PLANE      OMAP_IOW(52, struct omapfb_plane_info)
+#define OMAPFB_QUERY_PLANE      OMAP_IOW(53, struct omapfb_plane_info)
+#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(54, struct omapfb_update_window)
+#define OMAPFB_SETUP_MEM        OMAP_IOW(55, struct omapfb_mem_info)
+#define OMAPFB_QUERY_MEM        OMAP_IOW(56, struct omapfb_mem_info)
 #define OMAPFB_CAPS_GENERIC_MASK        0x00000fff
 #define OMAPFB_CAPS_LCDC_MASK           0x00fff000
 #define OMAPFB_CAPS_PANEL_MASK          0xff000000
 #define OMAPFB_CAPS_MANUAL_UPDATE       0x00001000
+#define OMAPFB_CAPS_TEARSYNC            0x00002000
+#define OMAPFB_CAPS_PLANE_RELOCATE_MEM  0x00004000
+#define OMAPFB_CAPS_PLANE_SCALE         0x00008000
+#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
+#define OMAPFB_CAPS_WINDOW_SCALE        0x00020000
+#define OMAPFB_CAPS_WINDOW_OVERLAY      0x00040000
 #define OMAPFB_CAPS_SET_BACKLIGHT       0x01000000
 /* Values from DSP must map to lower 16-bits */
-#define OMAPFB_FORMAT_MASK         0x00ff
+#define OMAPFB_FORMAT_MASK              0x00ff
-#define OMAPFB_FORMAT_FLAG_DOUBLE  0x0100
+#define OMAPFB_FORMAT_FLAG_DOUBLE       0x0100
+#define OMAPFB_FORMAT_FLAG_TEARSYNC     0x0200
+#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC  0x0400
+#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY       0x0800
+#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY      0x1000
+#define OMAPFB_EVENT_READY      1
+#define OMAPFB_EVENT_DISABLED   2
+#define OMAPFB_MEMTYPE_SDRAM            0
+#define OMAPFB_MEMTYPE_SRAM             1
+#define OMAPFB_MEMTYPE_MAX              1
 enum omapfb_color_format {
        OMAPFB_COLOR_RGB565 = 0,
@@ -64,17 +87,23 @@ enum omapfb_color_format {
        OMAPFB_COLOR_CLUT_4BPP,
        OMAPFB_COLOR_CLUT_2BPP,
        OMAPFB_COLOR_CLUT_1BPP,
+        OMAPFB_COLOR_RGB444,
+        OMAPFB_COLOR_YUY422,
 };
 struct omapfb_update_window {
        __u32 x, y;
        __u32 width, height;
        __u32 format;
+        __u32 out_x, out_y;
+        __u32 out_width, out_height;
+        __u32 reserved[8];
 };
 struct omapfb_update_window_old {
        __u32 x, y;
        __u32 width, height;
+        __u32 format;
 };
 enum omapfb_plane {
@@ -88,18 +117,28 @@ enum omapfb_channel_out {
        OMAPFB_CHANNEL_OUT_DIGIT,
 };
-struct omapfb_setup_plane {
+struct omapfb_plane_info {
-        __u8  plane;
+        __u32 pos_x;
+        __u32 pos_y;
+        __u8  enabled;
        __u8  channel_out;
-        __u32 offset;
+        __u8  mirror;
-        __u32 pos_x, pos_y;
+        __u8  reserved1;
-        __u32 width, height;
+        __u32 out_width;
-        __u32 color_mode;
+        __u32 out_height;
+        __u32 reserved2[12];
 };
-struct omapfb_enable_plane {
+struct omapfb_mem_info {
-        __u8  plane;
+        __u32 size;
-        __u8  enable;
+        __u8  type;
+        __u8  reserved[3];
+};
+struct omapfb_caps {
+        __u32 ctrl;
+        __u32 plane_color;
+        __u32 wnd_color;
 };
 enum omapfb_color_key_type {
@@ -141,6 +180,9 @@ enum omapfb_update_mode {
 #define OMAP_LCDC_PANEL_TFT             0x0100
+#define OMAPFB_PLANE_XRES_MIN           8
+#define OMAPFB_PLANE_YRES_MIN           8
 #ifdef CONFIG_ARCH_OMAP1
 #define OMAPFB_PLANE_NUM                1
 #else
@@ -169,19 +211,19 @@ struct lcd_panel {
        int             pcd;            /* pixel clock divider.
                                           Obsolete use pixel_clock instead */
-        int             (*init)         (struct omapfb_device *fbdev);
+        int             (*init)         (struct lcd_panel *panel,
-        void            (*cleanup)      (void);
+                                         struct omapfb_device *fbdev);
-        int             (*enable)       (void);
+        void            (*cleanup)      (struct lcd_panel *panel);
-        void            (*disable)      (void);
+        int             (*enable)       (struct lcd_panel *panel);
-        unsigned long   (*get_caps)     (void);
+        void            (*disable)      (struct lcd_panel *panel);
-        int             (*set_bklight_level)(unsigned int level);
+        unsigned long   (*get_caps)     (struct lcd_panel *panel);
-        unsigned int    (*get_bklight_level)(void);
+        int             (*set_bklight_level)(struct lcd_panel *panel,
-        unsigned int    (*get_bklight_max)  (void);
+                                             unsigned int level);
-        int             (*run_test)     (int test_num);
+        unsigned int    (*get_bklight_level)(struct lcd_panel *panel);
+        unsigned int    (*get_bklight_max)  (struct lcd_panel *panel);
+        int             (*run_test)     (struct lcd_panel *panel, int test_num);
 };
-struct omapfb_device;
 struct extif_timings {
        int cs_on_time;
        int cs_off_time;
@@ -202,9 +244,10 @@ struct extif_timings {
 };
 struct lcd_ctrl_extif {
-        int  (*init)            (void);
+        int  (*init)            (struct omapfb_device *fbdev);
        void (*cleanup)         (void);
        void (*get_clk_info)    (u32 *clk_period, u32 *max_clk_div);
+        unsigned long (*get_max_tx_rate)(void);
        int  (*convert_timings) (struct extif_timings *timings);
        void (*set_timings)     (const struct extif_timings *timings);
        void (*set_bits_per_cycle)(int bpc);
@@ -213,31 +256,48 @@ struct lcd_ctrl_extif {
        void (*write_data)      (const void *buf, unsigned int len);
        void (*transfer_area)   (int width, int height,
                                 void (callback)(void * data), void *data);
+        int  (*setup_tearsync)  (unsigned pin_cnt,
+                                 unsigned hs_pulse_time, unsigned vs_pulse_time,
+                                 int hs_pol_inv, int vs_pol_inv, int div);
+        int  (*enable_tearsync) (int enable, unsigned line);
        unsigned long           max_transmit_size;
 };
 struct omapfb_notifier_block {
        struct notifier_block   nb;
        void                    *data;
+        int                     plane_idx;
 };
-typedef int (*omapfb_notifier_callback_t)(struct omapfb_notifier_block *,
+typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
-                                           unsigned long event,
+                                          unsigned long event,
-                                           struct omapfb_device *fbdev);
+                                          void *fbi);
+struct omapfb_mem_region {
+        dma_addr_t      paddr;
+        void            *vaddr;
+        unsigned long   size;
+        u8              type;           /* OMAPFB_PLANE_MEM_* */
+        unsigned        alloc:1;        /* allocated by the driver */
+        unsigned        map:1;          /* kernel mapped by the driver */
+};
+struct omapfb_mem_desc {
+        int                             region_cnt;
+        struct omapfb_mem_region        region[OMAPFB_PLANE_NUM];
+};
 struct lcd_ctrl {
        const char      *name;
        void            *data;
        int             (*init)           (struct omapfb_device *fbdev,
-                                           int ext_mode, int req_vram_size);
+                                           int ext_mode,
+                                           struct omapfb_mem_desc *req_md);
        void            (*cleanup)        (void);
        void            (*bind_client)    (struct omapfb_notifier_block *nb);
-        void            (*get_vram_layout)(unsigned long *size,
+        void            (*get_caps)       (int plane, struct omapfb_caps *caps);
-                                           void **virt_base,
-                                           dma_addr_t *phys_base);
-        int             (*mmap)           (struct vm_area_struct *vma);
-        unsigned long   (*get_caps)       (void);
        int             (*set_update_mode)(enum omapfb_update_mode mode);
        enum omapfb_update_mode (*get_update_mode)(void);
        int             (*setup_plane)    (int plane, int channel_out,
@@ -245,8 +305,16 @@ struct lcd_ctrl {
                                           int screen_width,
                                           int pos_x, int pos_y, int width,
                                           int height, int color_mode);
+        int             (*setup_mem)      (int plane, size_t size,
+                                           int mem_type, unsigned long *paddr);
+        int             (*mmap)           (struct fb_info *info,
+                                           struct vm_area_struct *vma);
+        int             (*set_scale)      (int plane,
+                                           int orig_width, int orig_height,
+                                           int out_width, int out_height);
        int             (*enable_plane)   (int plane, int enable);
-        int             (*update_window)  (struct omapfb_update_window *win,
+        int             (*update_window)  (struct fb_info *fbi,
+                                           struct omapfb_update_window *win,
                                           void (*callback)(void *),
                                           void *callback_data);
        void            (*sync)           (void);
@@ -257,7 +325,7 @@ struct lcd_ctrl {
                                           u16 blue, u16 transp,
                                           int update_hw_mem);
        int             (*set_color_key)  (struct omapfb_color_key *ck);
+        int             (*get_color_key)  (struct omapfb_color_key *ck);
 };
 enum omapfb_state {
@@ -266,19 +334,20 @@ enum omapfb_state {
        OMAPFB_ACTIVE   = 100
 };
+struct omapfb_plane_struct {
+        int                             idx;
+        struct omapfb_plane_info        info;
+        enum omapfb_color_format        color_mode;
+        struct omapfb_device            *fbdev;
+};
 struct omapfb_device {
        int                     state;
        int                     ext_lcdc;               /* Using external
                                                           LCD controller */
        struct mutex            rqueue_mutex;
-        void                    *vram_virt_base;
-        dma_addr_t              vram_phys_base;
-        unsigned long           vram_size;
-        int                     color_mode;
        int                     palette_size;
-        int                     mirror;
        u32                     pseudo_palette[17];
        struct lcd_panel        *panel;                 /* LCD panel */
@@ -286,19 +355,19 @@ struct omapfb_device {
        struct lcd_ctrl         *int_ctrl;              /* internal LCD ctrl */
        struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
                                                           interface */
-        struct fb_info          *fb_info;
        struct device           *dev;
+        struct fb_var_screeninfo        new_var;        /* for mode changes */
+        struct omapfb_mem_desc          mem_desc;
+        struct fb_info                  *fb_info[OMAPFB_PLANE_NUM];
 };
 struct omapfb_platform_data {
-        struct omap_lcd_config   lcd;
+        struct omap_lcd_config          lcd;
-        struct omap_fbmem_config fbmem;
+        struct omapfb_mem_desc          mem_desc;
+        void                            *ctrl_platform_data;
 };
-#define OMAPFB_EVENT_READY      1
-#define OMAPFB_EVENT_DISABLED   2
 #ifdef CONFIG_ARCH_OMAP1
 extern struct lcd_ctrl omap1_lcd_ctrl;
 #else
@@ -310,15 +379,16 @@ extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
 extern void omapfb_notify_clients(struct omapfb_device *fbdev,
                                  unsigned long event);
 extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
-                                    omapfb_notifier_callback_t callback,
+                                   omapfb_notifier_callback_t callback,
-                                    void *callback_data);
+                                   void *callback_data);
 extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
-extern int  omapfb_update_window_async(struct omapfb_update_window *win,
+extern int  omapfb_update_window_async(struct fb_info *fbi,
-                                        void (*callback)(void *),
+                                       struct omapfb_update_window *win,
-                                        void *callback_data);
+                                       void (*callback)(void *),
+                                       void *callback_data);
-/* in arch/arm/plat-omap/devices.c */
+/* in arch/arm/plat-omap/fb.c */
-extern void omapfb_reserve_mem(void);
+extern void omapfb_set_ctrl_platform_data(void *pdata);
 #endif /* __KERNEL__ */
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index 6fc0dd57b7c3..bb9bb3fd532f 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -20,9 +20,6 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
                                      u32 mem_type);
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-extern unsigned long omap_fb_sram_start;
-extern unsigned long omap_fb_sram_size;
 /* Do not use these */
 extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
 extern unsigned long sram_reprogram_clock_sz;
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 054fb9a8e0c6..99ae9eabaf71 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -7,9 +7,27 @@
 /*-------------------------------------------------------------------------*/
-#define OTG_BASE                        0xfffb0400
+#define OMAP1_OTG_BASE                  0xfffb0400
-#define UDC_BASE                        0xfffb4000
+#define OMAP1_UDC_BASE                  0xfffb4000
-#define OMAP_OHCI_BASE                  0xfffba000
+#define OMAP1_OHCI_BASE                 0xfffba000
+#define OMAP2_OHCI_BASE                 0x4805e000
+#define OMAP2_UDC_BASE                  0x4805e200
+#define OMAP2_OTG_BASE                  0x4805e300
+#ifdef CONFIG_ARCH_OMAP1
+#define OTG_BASE                        OMAP1_OTG_BASE
+#define UDC_BASE                        OMAP1_UDC_BASE
+#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
+#else
+#define OTG_BASE                        OMAP2_OTG_BASE
+#define UDC_BASE                        OMAP2_UDC_BASE
+#define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
+#endif
 /*-------------------------------------------------------------------------*/
@@ -28,6 +46,7 @@
 #       define   HST_IDLE_EN            (1 << 14)
 #       define   DEV_IDLE_EN            (1 << 13)
 #       define   OTG_RESET_DONE         (1 << 2)
+#       define   OTG_SOFT_RESET         (1 << 1)
 #define OTG_SYSCON_2_REG                OTG_REG32(0x08)
 #       define   OTG_EN                 (1 << 31)
 #       define   USBX_SYNCHRO           (1 << 30)
@@ -103,6 +122,7 @@
 /*-------------------------------------------------------------------------*/
+/* OMAP1 */
 #define USB_TRANSCEIVER_CTRL_REG        __REG32(0xfffe1000 + 0x0064)
 #       define  CONF_USB2_UNI_R         (1 << 8)
 #       define  CONF_USB1_UNI_R         (1 << 7)
@@ -111,7 +131,17 @@
 #       define  CONF_USB_PWRDN_DM_R     (1 << 2)
 #       define  CONF_USB_PWRDN_DP_R     (1 << 1)
+/* OMAP2 */
+#define CONTROL_DEVCONF_REG             __REG32(L4_24XX_BASE + 0x0274)
+#       define  USB_UNIDIR                      0x0
+#       define  USB_UNIDIR_TLL                  0x1
+#       define  USB_BIDIR                       0x2
+#       define  USB_BIDIR_TLL                   0x3
+#       define  USBT0WRMODEI(x)         ((x) << 22)
+#       define  USBT1WRMODEI(x)         ((x) << 20)
+#       define  USBT2WRMODEI(x)         ((x) << 18)
+#       define  USBT2TLL5PI             (1 << 17)
+#       define  USB0PUENACTLOI          (1 << 16)
+#       define  USBSTANDBYCTRL          (1 << 15)
 #endif  /* __ASM_ARCH_OMAP_USB_H */
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index afad32c76e6c..d1294a46c70c 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -102,6 +102,14 @@
 //# endif
 #endif
+#if defined(CONFIG_CPU_V7)
+//# ifdef _CACHE
+#  define MULTI_CACHE 1
+//# else
+//#  define _CACHE v7
+//# endif
+#endif
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintainence model
 #endif
@@ -418,11 +426,19 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 */
 #define flush_icache_page(vma,page)     do { } while (0)
-#define __cacheid_present(val)          (val != read_cpuid(CPUID_ID))
+#define __cacheid_present(val)                  (val != read_cpuid(CPUID_ID))
-#define __cacheid_vivt(val)             ((val & (15 << 25)) != (14 << 25))
+#define __cacheid_type_v7(val)                  ((val & (7 << 29)) == (4 << 29))
-#define __cacheid_vipt(val)             ((val & (15 << 25)) == (14 << 25))
-#define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vivt_prev7(val)               ((val & (15 << 25)) != (14 << 25))
-#define __cacheid_vipt_aliasing(val)    ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+#define __cacheid_vipt_prev7(val)               ((val & (15 << 25)) == (14 << 25))
+#define __cacheid_vipt_nonaliasing_prev7(val)   ((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vipt_aliasing_prev7(val)      ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+#define __cacheid_vivt(val)                     (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
+#define __cacheid_vipt(val)                     (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
+#define __cacheid_vipt_nonaliasing(val)         (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
+#define __cacheid_vipt_aliasing(val)            (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
+#define __cacheid_vivt_asid_tagged_instr(val)   (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
@@ -430,6 +446,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 #define cache_is_vipt()                 0
 #define cache_is_vipt_nonaliasing()     0
 #define cache_is_vipt_aliasing()        0
+#define icache_is_vivt_asid_tagged()    0
 #elif defined(CONFIG_CPU_CACHE_VIPT)
@@ -447,6 +464,12 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
                __cacheid_vipt_aliasing(__val);                         \
        })
+#define icache_is_vivt_asid_tagged()                                    \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_vivt_asid_tagged_instr(__val);                \
+        })
 #else
 #define cache_is_vivt()                                                 \
@@ -475,6 +498,13 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
                 __cacheid_vipt_aliasing(__val);                        \
        })
+#define icache_is_vivt_asid_tagged()                                    \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_present(__val) &&                             \
+                 __cacheid_vivt_asid_tagged_instr(__val);               \
+        })
 #endif
 #endif
diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h
index 0cc5d3b10ce2..22274ce81375 100644
--- a/include/asm-arm/glue.h
+++ b/include/asm-arm/glue.h
@@ -38,6 +38,7 @@
 *        v5tej_early   - ARMv5 with Thumb and Java early abort handler
 *        xscale        - ARMv5 with Thumb with Xscale extensions
 *        v6_early      - ARMv6 generic early abort handler
+ *        v7_early      - ARMv7 generic early abort handler
 */
 #undef CPU_ABORT_HANDLER
 #undef MULTI_ABORT
@@ -106,6 +107,14 @@
 # endif
 #endif
+#ifdef CONFIG_CPU_ABRT_EV7
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v7_early_abort
+# endif
+#endif
 #ifndef CPU_ABORT_HANDLER
 #error Unknown data abort handler type
 #endif
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index f8755c818b54..4981ad419198 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -36,8 +36,9 @@ void __check_kvm_seq(struct mm_struct *mm);
 * The context ID is used by debuggers and trace logic, and
 * should be unique within all running processes.
 */
-#define ASID_BITS       8
+#define ASID_BITS               8
-#define ASID_MASK       ((~0) << ASID_BITS)
+#define ASID_MASK               ((~0) << ASID_BITS)
+#define ASID_FIRST_VERSION      (1 << ASID_BITS)
 extern unsigned int cpu_last_asid;
@@ -96,8 +97,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #ifdef CONFIG_MMU
        unsigned int cpu = smp_processor_id();
-        if (prev != next) {
+        if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
-                cpu_set(cpu, next->cpu_vm_mask);
                check_context(next);
                cpu_switch_mm(next->pgd, next);
                if (cache_is_vivt())
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index ea7e54c319be..5599d4e5e708 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -193,6 +193,14 @@
 #   define CPU_NAME cpu_v6
 #  endif
 # endif
+# ifdef CONFIG_CPU_V7
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_v7
+#  endif
+# endif
 #endif
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index f2da3b6e3a83..6f8e6a69dc5f 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -14,6 +14,7 @@
 #define CPU_ARCH_ARMv5TE        6
 #define CPU_ARCH_ARMv5TEJ       7
 #define CPU_ARCH_ARMv6          8
+#define CPU_ARCH_ARMv7          9
 /*
 * CR1 bits (CP#15 CR1)
@@ -155,7 +156,11 @@ extern unsigned int user_debug;
 #define vectors_high()  (0)
 #endif
-#if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6
+#if __LINUX_ARM_ARCH__ >= 7
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
                                    : : "r" (0) : "memory")
 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \