42 files changed, 248 insertions, 184 deletions

diff --git a/include/acpi/processor.h b/include/acpi/processor.h
index 26d79f6db8a0..76411b1fc4fd 100644
--- a/include/acpi/processor.h
+++ b/include/acpi/processor.h
@@ -78,7 +78,6 @@ struct acpi_processor_cx {
 struct acpi_processor_power {
         struct cpuidle_device dev;
         struct acpi_processor_cx *state;
-        struct acpi_processor_cx *bm_state;
         unsigned long bm_check_timestamp;
         u32 default_state;
         u32 bm_activity;
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 0212e180b90e..39bdd86871cf 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -50,8 +50,8 @@ extern unsigned long get_sclk(void);
 extern unsigned long sclk_to_usecs(unsigned long sclk);
 extern unsigned long usecs_to_sclk(unsigned long usecs);
 
-extern void dump_thread(struct pt_regs *regs, struct user *dump);
-extern void dump_bfin_regs(struct pt_regs *fp, void *retaddr);
+extern void dump_bfin_process(struct pt_regs *regs);
+extern void dump_bfin_mem(void *retaddr);
 extern void dump_bfin_trace_buffer(void);
 
 extern int init_arch_irq(void);
@@ -63,6 +63,7 @@ extern void bfin_dcache_init(void);
 extern int read_iloc(void);
 extern int bfin_console_init(void);
 extern asmlinkage void lower_to_irq14(void);
+extern asmlinkage void bfin_return_from_exception(void);
 extern void init_exception_vectors(void);
 extern void init_dma(void);
 extern void program_IAR(void);
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index bec6ecdf1bdb..c4d0596e8e9f 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -27,6 +27,9 @@
  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#ifndef __ASM_CPLBINIT_H__
+#define __ASM_CPLBINIT_H__
+
 #include <asm/blackfin.h>
 #include <asm/cplb.h>
 
@@ -57,8 +60,8 @@ struct cplb_tab {
         u16 size;
 };
 
-extern u_long icplb_table[MAX_CPLBS+1];
-extern u_long dcplb_table[MAX_CPLBS+1];
+extern u_long icplb_table[];
+extern u_long dcplb_table[];
 
 /* Till here we are discussing about the static memory management model.
  * However, the operating envoronments commonly define more CPLB
@@ -69,28 +72,16 @@ extern u_long dcplb_table[MAX_CPLBS+1];
  * This is how Page descriptor Table is implemented in uClinux/Blackfin.
  */
 
-#ifdef CONFIG_CPLB_SWITCH_TAB_L1
-extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
-extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
-
-#ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
-extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
-#endif /* CONFIG_CPLB_INFO */
-
-#else
-
-extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
-extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
-
+extern u_long ipdt_table[];
+extern u_long dpdt_table[];
 #ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
-extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
-#endif /* CONFIG_CPLB_INFO */
-
-#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
+extern u_long ipdt_swapcount_table[];
+extern u_long dpdt_swapcount_table[];
+#endif
 
 extern unsigned long reserved_mem_dcache_on;
 extern unsigned long reserved_mem_icache_on;
 
 extern void generate_cpl_tables(void);
+
+#endif
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index 52e7a10d7ff8..473a8113277f 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -1,29 +1,47 @@
-#ifndef _BLACKFIN_DELAY_H
-#define _BLACKFIN_DELAY_H
-
-static inline void __delay(unsigned long loops)
-{
-
-/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers,
-   uncomment this as soon those are implemented */
 /*
-      __asm__ __volatile__ (  "\t LSETUP (1f,1f) LC0= %0\n\t"
-                              "1:\t NOP;\n\t"
-                              : :"a" (loops)
-                              : "LT0","LB0","LC0");
+ * delay.h - delay functions
+ *
+ * Copyright (c) 2004-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_DELAY_H__
+#define __ASM_DELAY_H__
 
-*/
+#include <asm/mach/anomaly.h>
 
-        __asm__ __volatile__("[--SP] = LC0;\n\t"
-                             "[--SP] = LT0;\n\t"
-                             "[--SP] = LB0;\n\t"
-                             "LSETUP (1f,1f) LC0 = %0;\n\t"
-                             "1:\t NOP;\n\t"
-                             "LB0 = [SP++];\n\t"
-                                "LT0 = [SP++];\n\t"
-                                "LC0 = [SP++];\n"
-                                :
-                                :"a" (loops));
+static inline void __delay(unsigned long loops)
+{
+        if (ANOMALY_05000312) {
+                /* Interrupted loads to loop registers -> bad */
+                unsigned long tmp;
+                __asm__ __volatile__(
+                        "[--SP] = LC0;"
+                        "[--SP] = LT0;"
+                        "[--SP] = LB0;"
+                        "LSETUP (1f,1f) LC0 = %1;"
+                        "1: NOP;"
+                        /* We take advantage of the fact that LC0 is 0 at
+                         * the end of the loop.  Otherwise we'd need some
+                         * NOPs after the CLI here.
+                         */
+                        "CLI %0;"
+                        "LB0 = [SP++];"
+                        "LT0 = [SP++];"
+                        "LC0 = [SP++];"
+                        "STI %0;"
+                        : "=d" (tmp)
+                        : "a" (loops)
+                );
+        } else
+                __asm__ __volatile__ (
+                        "LSETUP(1f, 1f) LC0 = %0;"
+                        "1: NOP;"
+                        :
+                        : "a" (loops)
+                        : "LT0", "LB0", "LC0"
+                );
 }
 
 #include <linux/param.h>        /* needed for HZ */
@@ -41,4 +59,4 @@ static inline void udelay(unsigned long usecs)
         __delay(usecs * loops_per_jiffy / (1000000 / HZ));
 }
 
-#endif                          /* defined(_BLACKFIN_DELAY_H) */
+#endif
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index d1d2e6be3b59..1601d62f39a5 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -122,6 +122,7 @@ extern void outsl(unsigned long port, const void *addr, unsigned long count);
 extern void insb(unsigned long port, void *addr, unsigned long count);
 extern void insw(unsigned long port, void *addr, unsigned long count);
 extern void insl(unsigned long port, void *addr, unsigned long count);
+extern void insl_16(unsigned long port, void *addr, unsigned long count);
 
 extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
 extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
index 304f5bcfebe4..4e2b3f2020e5 100644
--- a/include/asm-blackfin/mach-bf527/irq.h
+++ b/include/asm-blackfin/mach-bf527/irq.h
@@ -176,11 +176,7 @@
 
 #define GPIO_IRQ_BASE   IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PH15+1)
-#else
-#define NR_IRQS     (SYS_IRQS+1)
-#endif
 
 #define IVG7            7
 #define IVG8            8
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
index c5aa20102b24..193082deaa4e 100644
--- a/include/asm-blackfin/mach-bf527/mem_map.h
+++ b/include/asm-blackfin/mach-bf527/mem_map.h
@@ -47,6 +47,7 @@
 /* Boot ROM Memory */
 
 #define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x8000
 
 /* Level 1 Memory */
 
@@ -90,9 +91,7 @@
 
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif                          /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 452fb825d891..832e6f6122da 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -130,11 +130,7 @@ Core        Emulation               **
 
 #define GPIO_IRQ_BASE           IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS         (IRQ_PF15+1)
-#else
-#define NR_IRQS         SYS_IRQS
-#endif
 
 #define IVG7                    7
 #define IVG8                    8
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index 94d8c4062eb7..bd30b6f3be00 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -1,4 +1,3 @@
-
 /*
  * File:         include/asm-blackfin/mach-bf533/mem_map.h
  * Based on:
@@ -48,6 +47,7 @@
 /* Boot ROM Memory */
 
 #define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x400
 
 /* Level 1 Memory */
 
@@ -160,9 +160,7 @@
 
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index 36c44bc1a917..be6f2ff77f31 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -162,11 +162,7 @@ Core        Emulation               **
 
 #define GPIO_IRQ_BASE   IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PH15+1)
-#else
-#define NR_IRQS     (IRQ_UART1_ERROR+1)
-#endif
 
 #define IVG7            7
 #define IVG8            8
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 18759e38eaae..5c6726d6f3b1 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -47,6 +47,7 @@
 /* Boot ROM Memory */
 
 #define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x800
 
 /* Level 1 Memory */
 
@@ -167,9 +168,7 @@
 
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif                          /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 7e6d349beb08..e748588e8930 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -106,24 +106,22 @@
 
 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
 
-#ifdef CONFIG_BF542
-#define CPU "BF542"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF544
-#define CPU "BF544"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF548
-#define CPU "BF548"
-#define CPUID 0x027c6000
-#endif
-#ifdef CONFIG_BF549
-#define CPU "BF549"
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
+#if defined(CONFIG_BF542)
+# define CPU   "BF542"
+# define CPUID 0x027c8000
+#elif defined(CONFIG_BF544)
+# define CPU "BF544"
+# define CPUID 0x027c8000
+#elif defined(CONFIG_BF547)
+# define CPU "BF547"
+#elif defined(CONFIG_BF548)
+# define CPU "BF548"
+# define CPUID 0x027c6000
+#elif defined(CONFIG_BF549)
+# define CPU "BF549"
+#else
+# define CPU "UNKNOWN"
+# define CPUID 0x0
 #endif
 
 #endif  /* __MACH_BF48_H__  */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index 760307e34b9e..b8b9870e2697 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -645,7 +645,7 @@
 
 /* Bit masks for HOST_STATUS */
 
-#define                     READY  0x1        /* DMA Ready */
+#define                 DMA_READY  0x1        /* DMA Ready */
 #define                  FIFOFULL  0x2        /* FIFO Full */
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
 #define                  COMPLETE  0x8        /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index 70af33c963b0..ecbca952985c 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1007,7 +1007,7 @@
 
 /* Bit masks for HOST_STATUS */
 
-#define                     READY  0x1        /* DMA Ready */
+#define                 DMA_READY  0x1        /* DMA Ready */
 #define                  FIFOFULL  0x2        /* FIFO Full */
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
 #define                  COMPLETE  0x8        /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 3b08cf9bd6f3..9fb7bc5399a8 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -338,11 +338,7 @@ Events         (highest priority)  EMU         0
 
 #define GPIO_IRQ_BASE   IRQ_PA0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PJ15+1)
-#else
-#define NR_IRQS     (SYS_IRQS+1)
-#endif
 
 /* For compatibility reasons with existing code */
 
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index ec1597e31831..f99f47bc3a07 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -47,6 +47,12 @@
 /* Boot ROM Memory */
 
 #define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x1000
+
+/* L1 Instruction ROM */
+
+#define L1_ROM_START            0xFFA14000
+#define L1_ROM_LENGTH           0x10000
 
 /* Level 1 Memory */
 
@@ -87,11 +93,19 @@
 #define BFIN_DSUPBANKS  0
 #endif /*CONFIG_BFIN_DCACHE*/
 
+/* Level 2 Memory */
+#if !defined(CONFIG_BF542)
+# define L2_START          0xFEB00000
+# if defined(CONFIG_BF544)
+#  define L2_LENGTH        0x10000
+# else
+#  define L2_LENGTH        0x20000
+# endif
+#endif
+
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF54x)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 17e1d5dcef02..3ef9e5f36136 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -33,25 +33,6 @@
 #define SUPPORTED_REVID         0x3
 
 #define OFFSET_(x) ((x) & 0x0000FFFF)
-#define L1_ISRAM                0xFFA00000
-#define L1_ISRAM_END            0xFFA04000
-#define DATA_BANKA_SRAM         0xFF800000
-#define DATA_BANKA_SRAM_END     0xFF804000
-#define DATA_BANKB_SRAM         0xFF900000
-#define DATA_BANKB_SRAM_END     0xFF904000
-#define L1_DSRAMA               0xFF800000
-#define L1_DSRAMA_END           0xFF804000
-#define L1_DSRAMB               0xFF900000
-#define L1_DSRAMB_END           0xFF904000
-#define L2_SRAM                 0xFEB00000
-#define L2_SRAM_END             0xFEB20000
-#define AMB_FLASH               0x20000000
-#define AMB_FLASH_END           0x21000000
-#define AMB_FLASH_LENGTH        0x01000000
-#define L1_ISRAM_LENGTH         0x4000
-#define L1_DSRAMA_LENGTH        0x4000
-#define L1_DSRAMB_LENGTH        0x4000
-#define L2_SRAM_LENGTH          0x20000
 
 /*some misc defines*/
 #define IMASK_IVG15             0x8000
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 7945e8a3a841..c3c0eb13c819 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,7 @@
 /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
 #define SWRST                   SICA_SWRST
 #define SYSCR                   SICA_SYSCR
+#define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
 #define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
 #define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
 #define RESET_SOFTWARE          (SWRST_OCCURRED)
@@ -877,12 +878,14 @@
 #define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
 /* SWRST Mask */
-#define SYSTEM_RESET           0x00000007       /* Initiates a system software reset */
-#define SWRST_DBL_FAULT_B      0x00000800       /* SWRST Core B Double Fault */
-#define SWRST_DBL_FAULT_A      0x00001000       /* SWRST Core A Double Fault */
-#define SWRST_WDT_B                    0x00002000       /* SWRST Watchdog B */
-#define SWRST_WDT_A                    0x00004000       /* SWRST Watchdog A */
-#define SWRST_OCCURRED         0x00008000       /* SWRST Status */
+#define SYSTEM_RESET           0x0007   /* Initiates a system software reset */
+#define DOUBLE_FAULT_A         0x0008   /* Core A Double Fault Causes Reset */
+#define DOUBLE_FAULT_B         0x0010   /* Core B Double Fault Causes Reset */
+#define SWRST_DBL_FAULT_A      0x0800   /* SWRST Core A Double Fault */
+#define SWRST_DBL_FAULT_B      0x1000   /* SWRST Core B Double Fault */
+#define SWRST_WDT_B                    0x2000   /* SWRST Watchdog B */
+#define SWRST_WDT_A                    0x4000   /* SWRST Watchdog A */
+#define SWRST_OCCURRED         0x8000   /* SWRST Status */
 
 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
 
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 12789927db3d..83f0383957d2 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -291,11 +291,7 @@
 
 #define GPIO_IRQ_BASE           IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS                 (IRQ_PF47 + 1)
-#else
-#define NR_IRQS                 SYS_IRQS
-#endif
 
 #define IVG7                    7
 #define IVG8                    8
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index f7ac09cf2c3d..c26d8486cc4b 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -19,6 +19,11 @@
 #define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
 #define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
 
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x800
+
 /* Level 1 Memory */
 
 #ifdef CONFIG_BFIN_ICACHE
@@ -67,9 +72,7 @@
 
 /* Scratch Pad Memory */
 
-#if defined(CONFIG_BF561)
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
-#endif
 
 #endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index c1d8c4a78fcf..e8967f6124f7 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -46,7 +46,7 @@
 #endif
 
 #define bfin_read8(addr) ({ \
-        uint8_t __v; \
+        uint32_t __v; \
         __asm__ __volatile__( \
                 NOP_PAD_ANOMALY_05000198 \
                 "%0 = b[%1] (z);" \
@@ -56,7 +56,7 @@
         __v; })
 
 #define bfin_read16(addr) ({ \
-        uint16_t __v; \
+        uint32_t __v; \
         __asm__ __volatile__( \
                 NOP_PAD_ANOMALY_05000198 \
                 "%0 = w[%1] (z);" \
@@ -80,7 +80,7 @@
                 NOP_PAD_ANOMALY_05000198 \
                 "b[%0] = %1;" \
                 : \
-                : "a" (addr), "d" (val) \
+                : "a" (addr), "d" ((uint8_t)(val)) \
                 : "memory" \
         )
 
@@ -89,7 +89,7 @@
                 NOP_PAD_ANOMALY_05000198 \
                 "w[%0] = %1;" \
                 : \
-                : "a" (addr), "d" (val) \
+                : "a" (addr), "d" ((uint16_t)(val)) \
                 : "memory" \
         )
 
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
index 3b671d5fd70d..cbaff24b4b25 100644
--- a/include/asm-blackfin/page_offset.h
+++ b/include/asm-blackfin/page_offset.h
@@ -1,6 +1,6 @@
 
 /* This handles the memory map.. */
 
-#ifdef CONFIG_BFIN
+#ifdef CONFIG_BLACKFIN
 #define PAGE_OFFSET_RAW         0x00000000
 #endif
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index e8ada91ab002..321f4d96e4ae 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -1,6 +1,8 @@
 #ifndef _BLACKFIN_STRING_H_
 #define _BLACKFIN_STRING_H_
 
+#include <linux/types.h>
+
 #ifdef __KERNEL__               /* only set these up for kernel code */
 
 #define __HAVE_ARCH_STRCPY
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index fe365b1b7ca8..ee1cbf73a9ab 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -48,28 +48,80 @@
 
 #ifndef __ASSEMBLY__
 
-#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3 "External Memory Addressing Error\n"
-#define HWC_x12 "Performance Monitor Overflow\n"
-#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default "Reserved\n"
-
-#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n"
-#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n"
-#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n"
-#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n"
-#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n"
-#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n"
+#define HWC_x2(level) \
+        "System MMR Error\n" \
+        level " - An error occurred due to an invalid access to an System MMR location\n" \
+        level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
+        level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
+#define HWC_x3(level) \
+        "External Memory Addressing Error\n"
+#define HWC_x12(level) \
+        "Performance Monitor Overflow\n"
+#define HWC_x18(level) \
+        "RAISE 5 instruction\n" \
+        level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
+#define HWC_default(level) \
+         "Reserved\n"
+#define EXC_0x03(level) \
+        "Application stack overflow\n" \
+        level " - Please increase the stack size of the application using elf2flt -s option,\n" \
+        level "   and/or reduce the stack use of the application.\n"
+#define EXC_0x10(level) \
+        "Single step\n" \
+        level " - When the processor is in single step mode, every instruction\n" \
+        level "   generates an exception. Primarily used for debugging.\n"
+#define EXC_0x11(level) \
+        "Exception caused by a trace buffer full condition\n" \
+        level " - The processor takes this exception when the trace\n" \
+        level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
+#define EXC_0x21(level) \
+        "Undefined instruction\n" \
+        level " - May be used to emulate instructions that are not defined for\n" \
+        level "   a particular processor implementation.\n"
+#define EXC_0x22(level) \
+        "Illegal instruction combination\n" \
+        level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
+        level "   Processor Instruction Set Reference.\n"
+#define EXC_0x23(level) \
+        "Data access CPLB protection violation\n" \
+        level " - Attempted read or write to Supervisor resource,\n" \
+        level "   or illegal data memory access. \n"
+#define EXC_0x24(level) \
+        "Data access misaligned address violation\n" \
+        level " - Attempted misaligned data memory or data cache access.\n"
+#define EXC_0x25(level) \
+        "Unrecoverable event\n" \
+        level " - For example, an exception generated while processing a previous exception.\n"
+#define EXC_0x26(level) \
+        "Data access CPLB miss\n" \
+        level " - Used by the MMU to signal a CPLB miss on a data access.\n"
+#define EXC_0x27(level) \
+        "Data access multiple CPLB hits\n" \
+        level " - More than one CPLB entry matches data fetch address.\n"
+#define EXC_0x28(level) \
+        "Program Sequencer Exception caused by an emulation watchpoint match\n" \
+        level " - There is a watchpoint match, and one of the EMUSW\n" \
+        level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
+#define EXC_0x2A(level) \
+        "Instruction fetch misaligned address violation\n" \
+        level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
+        level "   exception, the return address provided in RETX is the destination address which is\n" \
+        level "   misaligned, rather than the address of the offending instruction.\n"
+#define EXC_0x2B(level) \
+        "CPLB protection violation\n" \
+        level " - Illegal instruction fetch access (memory protection violation).\n"
+#define EXC_0x2C(level) \
+        "Instruction fetch CPLB miss\n" \
+        level " - CPLB miss on an instruction fetch.\n"
+#define EXC_0x2D(level) \
+        "Instruction fetch multiple CPLB hits\n" \
+        level " - More than one CPLB entry matches instruction fetch address.\n"
+#define EXC_0x2E(level) \
+        "Illegal use of supervisor resource\n" \
+        level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
+        level "   Supervisor resources are registers and instructions that are reserved\n" \
+        level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
+        level "   only instructions.\n"
 
 #endif                          /* __ASSEMBLY__ */
 #endif                          /* _BFIN_TRAPS_H */
diff --git a/include/asm-mips/8253pit.h b/include/asm-mips/8253pit.h
deleted file mode 100644
index 285f78488ccb..000000000000
--- a/include/asm-mips/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * 8253/8254 Programmable Interval Timer
- */
-
-#ifndef _8253PIT_H
-#define _8253PIT_H
-
-#define PIT_TICK_RATE   1193182UL
-
-#endif
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index 833437d31ef1..d6a6c21f16db 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -92,6 +92,7 @@
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
 #endif
 #define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+#define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
 
 /* 8237 DMA controllers */
 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 3e7e30d4f418..17f082cfea85 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -35,7 +35,7 @@
                 "       .set    mips0                           \n"     \
                 "       .section .fixup,\"ax\"                  \n"     \
                 "4:     li      %0, %6                          \n"     \
-                "       j       2b                              \n"     \
+                "       j       3b                              \n"     \
                 "       .previous                               \n"     \
                 "       .section __ex_table,\"a\"               \n"     \
                 "       "__UA_ADDR "\t1b, 4b                    \n"     \
@@ -61,7 +61,7 @@
                 "       .set    mips0                           \n"     \
                 "       .section .fixup,\"ax\"                  \n"     \
                 "4:     li      %0, %6                          \n"     \
-                "       j       2b                              \n"     \
+                "       j       3b                              \n"     \
                 "       .previous                               \n"     \
                 "       .section __ex_table,\"a\"               \n"     \
                 "       "__UA_ADDR "\t1b, 4b                    \n"     \
@@ -200,4 +200,4 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
 }
 
 #endif
-#endif
+#endif /* _ASM_FUTEX_H */
diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h
index 032ca73f181b..5dabc870b322 100644
--- a/include/asm-mips/i8253.h
+++ b/include/asm-mips/i8253.h
@@ -12,6 +12,8 @@
 #define PIT_CH0                 0x40
 #define PIT_CH2                 0x42
 
+#define PIT_TICK_RATE           1193182UL
+
 extern spinlock_t i8253_lock;
 
 extern void setup_pit_timer(void);
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index ab5612f90f6f..85bc5302bce0 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -22,7 +22,7 @@ enum ip32_irq_no {
          * CPU interrupts are 0 ... 7
          */
 
-        CRIME_IRQ_BASE                  = MIPS_CPU_IRQ_BASE,
+        CRIME_IRQ_BASE                  = MIPS_CPU_IRQ_BASE + 8,
 
         /*
          * MACE
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 90e4b403f531..1030562d6ea6 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -68,11 +68,15 @@ do {									\
         if (cpu_has_dsp)                                                \
                 __save_dsp(prev);                                       \
         (last) = resume(prev, next, task_thread_info(next));            \
+} while (0)
+
+#define finish_arch_switch(prev)                                        \
+do {                                                                    \
         if (cpu_has_dsp)                                                \
                 __restore_dsp(current);                                 \
         if (cpu_has_userlocal)                                          \
-                write_c0_userlocal(task_thread_info(current)->tp_value);\
-} while(0)
+                write_c0_userlocal(current_thread_info()->tp_value);    \
+} while (0)
 
 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 {
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index ee1663e64da1..7717934f94c3 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -58,10 +58,22 @@ extern int (*perf_irq)(void);
  * Initialize the calling CPU's compare interrupt as clockevent device
  */
 #ifdef CONFIG_CEVT_R4K
-extern void mips_clockevent_init(void);
+extern int mips_clockevent_init(void);
 extern unsigned int __weak get_c0_compare_int(void);
 #else
-static inline void mips_clockevent_init(void)
+static inline int mips_clockevent_init(void)
+{
+        return -ENXIO;
+}
+#endif
+
+/*
+ * Initialize the count register as a clocksource
+ */
+#ifdef CONFIG_CEVT_R4K
+extern void init_mips_clocksource(void);
+#else
+static inline void init_mips_clocksource(void)
 {
 }
 #endif
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
index 374d0db37e1c..17110aff26e7 100644
--- a/include/asm-powerpc/page_32.h
+++ b/include/asm-powerpc/page_32.h
@@ -6,6 +6,10 @@
 
 #define PPC_MEMSTART    0
 
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
+#endif
+
 #ifndef __ASSEMBLY__
 /*
  * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index dc318458b5fe..d8bdc79db12e 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -246,7 +246,6 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
         return PCI_DN(busdn)->phb;
 }
 
-extern void pcibios_free_controller(struct pci_controller *phb);
 
 extern void isa_bridge_find_early(struct pci_controller *hose);
 
@@ -282,9 +281,11 @@ extern void
 pci_process_bridge_OF_ranges(struct pci_controller *hose,
                            struct device_node *dev, int primary);
 
-/* Allocate a new PCI host bridge structure */
+/* Allocate & free a PCI host bridge structure */
 extern struct pci_controller *
 pcibios_alloc_controller(struct device_node *dev);
+extern void pcibios_free_controller(struct pci_controller *phb);
+
 #ifdef CONFIG_PCI
 extern unsigned long pci_address_to_pio(phys_addr_t address);
 extern int pcibios_vaddr_is_ioport(void __iomem *address);
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
index 8eaa7b28d9d0..87db8728e82d 100644
--- a/include/asm-powerpc/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -164,7 +164,8 @@ extern int rtas_call(int token, int, int, int *, ...);
 extern void rtas_restart(char *cmd);
 extern void rtas_power_off(void);
 extern void rtas_halt(void);
-extern void rtas_os_term(char *str);
+extern void rtas_panic_msg(char *str);
+extern void rtas_os_term(void);
 extern int rtas_get_sensor(int sensor, int index, int *state);
 extern int rtas_get_power_level(int powerdomain, int *level);
 extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
diff --git a/include/asm-powerpc/vdso_datapage.h b/include/asm-powerpc/vdso_datapage.h
index 8a94f0eba5e9..f01393224b52 100644
--- a/include/asm-powerpc/vdso_datapage.h
+++ b/include/asm-powerpc/vdso_datapage.h
@@ -77,6 +77,10 @@ struct vdso_data {
         /* those additional ones don't have to be located anywhere
          * special as they were not part of the original systemcfg
          */
+        __u32 dcache_block_size;                /* L1 d-cache block size     */
+        __u32 icache_block_size;                /* L1 i-cache block size     */
+        __u32 dcache_log_block_size;            /* L1 d-cache log block size */
+        __u32 icache_log_block_size;            /* L1 i-cache log block size */
         __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
         __s32 wtom_clock_nsec;
         __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls  */
@@ -99,6 +103,10 @@ struct vdso_data {
         __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
         __s32 wtom_clock_nsec;
         __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
+        __u32 dcache_block_size;        /* L1 d-cache block size     */
+        __u32 icache_block_size;        /* L1 i-cache block size     */
+        __u32 dcache_log_block_size;    /* L1 d-cache log block size */
+        __u32 icache_log_block_size;    /* L1 i-cache log block size */
 };
 
 #endif /* CONFIG_PPC64 */
diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h
index d866d3385556..44bda786eef7 100644
--- a/include/asm-s390/system.h
+++ b/include/asm-s390/system.h
@@ -388,6 +388,11 @@ extern void (*_machine_power_off)(void);
 
 #define arch_align_stack(x) (x)
 
+#ifdef CONFIG_TRACE_IRQFLAGS
+extern psw_t sysc_restore_trace_psw;
+extern psw_t io_restore_trace_psw;
+#endif
+
 #endif /* __KERNEL__ */
 
 #endif
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h
index b91246153b7e..9d528ada3c14 100644
--- a/include/asm-sh/cacheflush.h
+++ b/include/asm-sh/cacheflush.h
@@ -43,7 +43,7 @@ extern void __flush_purge_region(void *start, int size);
 extern void __flush_invalidate_region(void *start, int size);
 #endif
 
-#ifdef CONFIG_CPU_SH4
+#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF)
 extern void copy_to_user_page(struct vm_area_struct *vma,
         struct page *page, unsigned long vaddr, void *dst, const void *src,
         unsigned long len);
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 8ccedf7a0a5a..e3c16c981e46 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -132,6 +132,11 @@ extern unsigned long acpi_realmode_flags;
 int acpi_register_gsi (u32 gsi, int triggering, int polarity);
 int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
 
+#ifdef CONFIG_X86_IO_APIC
+extern int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity);
+#else
+#define acpi_get_override_irq(bus, trigger, polarity) (-1)
+#endif
 /*
  * This function undoes the effect of one call to acpi_register_gsi().
  * If this matches the last registration, any IRQ resources for gsi
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 16a51546db44..c4e00161a247 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -92,6 +92,7 @@ struct cpuidle_device {
         struct kobject          kobj;
         struct completion       kobj_unregister;
         void                    *governor_data;
+        struct cpuidle_state    *safe_state;
 };
 
 DECLARE_PER_CPU(struct cpuidle_device *, cpuidle_devices);
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 56a5673aebad..ef52a07c43d8 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -340,6 +340,7 @@ enum {
         ATA_HORKAGE_HPA_SIZE    = (1 << 6),     /* native size off by one */
         ATA_HORKAGE_IPM         = (1 << 7),     /* Link PM problems */
         ATA_HORKAGE_IVB         = (1 << 8),     /* cbl det validity bit bugs */
+        ATA_HORKAGE_STUCK_ERR   = (1 << 9),     /* stuck ERR on next PACKET */
 
          /* DMA mask for user DMA control: User visible values; DO NOT
             renumber */
@@ -771,8 +772,6 @@ static inline int ata_port_is_dummy(struct ata_port *ap)
 
 extern void sata_print_link_status(struct ata_link *link);
 extern void ata_port_probe(struct ata_port *);
-extern void __sata_phy_reset(struct ata_port *ap);
-extern void sata_phy_reset(struct ata_port *ap);
 extern void ata_bus_reset(struct ata_port *ap);
 extern int sata_set_spd(struct ata_link *link);
 extern int sata_link_debounce(struct ata_link *link,
@@ -994,8 +993,6 @@ extern void sata_pmp_do_eh(struct ata_port *ap,
 /*
  * EH
  */
-extern void ata_eng_timeout(struct ata_port *ap);
-
 extern void ata_port_schedule_eh(struct ata_port *ap);
 extern int ata_link_abort(struct ata_link *link);
 extern int ata_port_abort(struct ata_port *ap);
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index e99171f01b4c..4f5047df8a9e 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -70,7 +70,6 @@ enum
         CTL_ABI=9,              /* Binary emulation */
         CTL_CPU=10,             /* CPU stuff (speed scaling, etc) */
         CTL_ARLAN=254,          /* arlan wireless driver */
-        CTL_APPLDATA=2120,      /* s390 appldata */
         CTL_S390DBF=5677,       /* s390 debug */
         CTL_SUNRPC=7249,        /* sunrpc debug */
         CTL_PM=9899,            /* frv power management */
@@ -207,11 +206,6 @@ enum
         VM_PANIC_ON_OOM=33,     /* panic at out-of-memory */
         VM_VDSO_ENABLED=34,     /* map VDSO into new processes? */
         VM_MIN_SLAB=35,          /* Percent pages ignored by zone reclaim */
-
-        /* s390 vm cmm sysctls */
-        VM_CMM_PAGES=1111,
-        VM_CMM_TIMED_PAGES=1112,
-        VM_CMM_TIMEOUT=1113,
 };
 
 
diff --git a/include/sound/version.h b/include/sound/version.h
index a2be8ad8894b..a9781eb0da09 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
 /* include/version.h.  Generated by alsa/ksync script.  */
 #define CONFIG_SND_VERSION "1.0.15"
-#define CONFIG_SND_DATE " (Tue Oct 23 06:09:18 2007 UTC)"
+#define CONFIG_SND_DATE " (Tue Nov 20 19:16:42 2007 UTC)"