diff options
Diffstat (limited to 'include')
33 files changed, 442 insertions, 83 deletions
diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h index d4187fe9a85a..472badb451c4 100644 --- a/include/asm-arm/arch-iop3xx/timex.h +++ b/include/asm-arm/arch-iop3xx/timex.h | |||
@@ -4,7 +4,7 @@ | |||
4 | * IOP3xx architecture timex specifications | 4 | * IOP3xx architecture timex specifications |
5 | */ | 5 | */ |
6 | #include <linux/config.h> | 6 | #include <linux/config.h> |
7 | 7 | #include <asm/hardware.h> | |
8 | 8 | ||
9 | #if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244) | 9 | #if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244) |
10 | 10 | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index cb33d57c146c..7f1be48ad67e 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h | |||
@@ -21,6 +21,7 @@ | |||
21 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA | 21 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA |
22 | * 28-Mar-2005 LCVR Fixed definition of GPB10 | 22 | * 28-Mar-2005 LCVR Fixed definition of GPB10 |
23 | * 26-Oct-2005 BJD Added generic configuration types | 23 | * 26-Oct-2005 BJD Added generic configuration types |
24 | * 27-Nov-2005 LCVR Added definitions to S3C2400 registers | ||
24 | */ | 25 | */ |
25 | 26 | ||
26 | 27 | ||
@@ -54,12 +55,16 @@ | |||
54 | 55 | ||
55 | #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) | 56 | #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) |
56 | 57 | ||
57 | /* port A - 22bits, zero in bit X makes pin X output | 58 | /* port A - S3C2410: 22bits, zero in bit X makes pin X output |
59 | * S3C2400: 18bits, zero in bit X makes pin X output | ||
58 | * 1 makes port special function, this is default | 60 | * 1 makes port special function, this is default |
59 | */ | 61 | */ |
60 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) | 62 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) |
61 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) | 63 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) |
62 | 64 | ||
65 | #define S3C2400_GPACON S3C2410_GPIOREG(0x00) | ||
66 | #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) | ||
67 | |||
63 | #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) | 68 | #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) |
64 | #define S3C2410_GPA0_OUT (0<<0) | 69 | #define S3C2410_GPA0_OUT (0<<0) |
65 | #define S3C2410_GPA0_ADDR0 (1<<0) | 70 | #define S3C2410_GPA0_ADDR0 (1<<0) |
@@ -103,34 +108,42 @@ | |||
103 | #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) | 108 | #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) |
104 | #define S3C2410_GPA10_OUT (0<<10) | 109 | #define S3C2410_GPA10_OUT (0<<10) |
105 | #define S3C2410_GPA10_ADDR25 (1<<10) | 110 | #define S3C2410_GPA10_ADDR25 (1<<10) |
111 | #define S3C2400_GPA10_SCKE (1<<10) | ||
106 | 112 | ||
107 | #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) | 113 | #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) |
108 | #define S3C2410_GPA11_OUT (0<<11) | 114 | #define S3C2410_GPA11_OUT (0<<11) |
109 | #define S3C2410_GPA11_ADDR26 (1<<11) | 115 | #define S3C2410_GPA11_ADDR26 (1<<11) |
116 | #define S3C2400_GPA11_nCAS0 (1<<11) | ||
110 | 117 | ||
111 | #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) | 118 | #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) |
112 | #define S3C2410_GPA12_OUT (0<<12) | 119 | #define S3C2410_GPA12_OUT (0<<12) |
113 | #define S3C2410_GPA12_nGCS1 (1<<12) | 120 | #define S3C2410_GPA12_nGCS1 (1<<12) |
121 | #define S3C2400_GPA12_nCAS1 (1<<12) | ||
114 | 122 | ||
115 | #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) | 123 | #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) |
116 | #define S3C2410_GPA13_OUT (0<<13) | 124 | #define S3C2410_GPA13_OUT (0<<13) |
117 | #define S3C2410_GPA13_nGCS2 (1<<13) | 125 | #define S3C2410_GPA13_nGCS2 (1<<13) |
126 | #define S3C2400_GPA13_nGCS1 (1<<13) | ||
118 | 127 | ||
119 | #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) | 128 | #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) |
120 | #define S3C2410_GPA14_OUT (0<<14) | 129 | #define S3C2410_GPA14_OUT (0<<14) |
121 | #define S3C2410_GPA14_nGCS3 (1<<14) | 130 | #define S3C2410_GPA14_nGCS3 (1<<14) |
131 | #define S3C2400_GPA14_nGCS2 (1<<14) | ||
122 | 132 | ||
123 | #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) | 133 | #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) |
124 | #define S3C2410_GPA15_OUT (0<<15) | 134 | #define S3C2410_GPA15_OUT (0<<15) |
125 | #define S3C2410_GPA15_nGCS4 (1<<15) | 135 | #define S3C2410_GPA15_nGCS4 (1<<15) |
136 | #define S3C2400_GPA15_nGCS3 (1<<15) | ||
126 | 137 | ||
127 | #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) | 138 | #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) |
128 | #define S3C2410_GPA16_OUT (0<<16) | 139 | #define S3C2410_GPA16_OUT (0<<16) |
129 | #define S3C2410_GPA16_nGCS5 (1<<16) | 140 | #define S3C2410_GPA16_nGCS5 (1<<16) |
141 | #define S3C2400_GPA16_nGCS4 (1<<16) | ||
130 | 142 | ||
131 | #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) | 143 | #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) |
132 | #define S3C2410_GPA17_OUT (0<<17) | 144 | #define S3C2410_GPA17_OUT (0<<17) |
133 | #define S3C2410_GPA17_CLE (1<<17) | 145 | #define S3C2410_GPA17_CLE (1<<17) |
146 | #define S3C2400_GPA17_nGCS5 (1<<17) | ||
134 | 147 | ||
135 | #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) | 148 | #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) |
136 | #define S3C2410_GPA18_OUT (0<<18) | 149 | #define S3C2410_GPA18_OUT (0<<18) |
@@ -152,10 +165,16 @@ | |||
152 | #define S3C2410_GPA22_OUT (0<<22) | 165 | #define S3C2410_GPA22_OUT (0<<22) |
153 | #define S3C2410_GPA22_nFCE (1<<22) | 166 | #define S3C2410_GPA22_nFCE (1<<22) |
154 | 167 | ||
155 | /* 0x08 and 0x0c are reserved */ | 168 | /* 0x08 and 0x0c are reserved on S3C2410 */ |
156 | 169 | ||
157 | /* GPB is 10 IO pins, each configured by 2 bits each in GPBCON. | 170 | /* S3C2410: |
171 | * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. | ||
158 | * 00 = input, 01 = output, 10=special function, 11=reserved | 172 | * 00 = input, 01 = output, 10=special function, 11=reserved |
173 | |||
174 | * S3C2400: | ||
175 | * GPB is 16 IO pins, each configured by 2 bits each in GPBCON. | ||
176 | * 00 = input, 01 = output, 10=data, 11=special function | ||
177 | |||
159 | * bit 0,1 = pin 0, 2,3= pin 1... | 178 | * bit 0,1 = pin 0, 2,3= pin 1... |
160 | * | 179 | * |
161 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled | 180 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled |
@@ -165,63 +184,113 @@ | |||
165 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) | 184 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) |
166 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) | 185 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) |
167 | 186 | ||
187 | #define S3C2400_GPBCON S3C2410_GPIOREG(0x08) | ||
188 | #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) | ||
189 | #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) | ||
190 | |||
168 | /* no i/o pin in port b can have value 3! */ | 191 | /* no i/o pin in port b can have value 3! */ |
169 | 192 | ||
170 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) | 193 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) |
171 | #define S3C2410_GPB0_INP (0x00 << 0) | 194 | #define S3C2410_GPB0_INP (0x00 << 0) |
172 | #define S3C2410_GPB0_OUTP (0x01 << 0) | 195 | #define S3C2410_GPB0_OUTP (0x01 << 0) |
173 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) | 196 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) |
197 | #define S3C2400_GPB0_DATA16 (0x02 << 0) | ||
174 | 198 | ||
175 | #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) | 199 | #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) |
176 | #define S3C2410_GPB1_INP (0x00 << 2) | 200 | #define S3C2410_GPB1_INP (0x00 << 2) |
177 | #define S3C2410_GPB1_OUTP (0x01 << 2) | 201 | #define S3C2410_GPB1_OUTP (0x01 << 2) |
178 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) | 202 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) |
203 | #define S3C2400_GPB1_DATA17 (0x02 << 2) | ||
179 | 204 | ||
180 | #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) | 205 | #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) |
181 | #define S3C2410_GPB2_INP (0x00 << 4) | 206 | #define S3C2410_GPB2_INP (0x00 << 4) |
182 | #define S3C2410_GPB2_OUTP (0x01 << 4) | 207 | #define S3C2410_GPB2_OUTP (0x01 << 4) |
183 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) | 208 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) |
209 | #define S3C2400_GPB2_DATA18 (0x02 << 4) | ||
210 | #define S3C2400_GPB2_TCLK1 (0x03 << 4) | ||
184 | 211 | ||
185 | #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) | 212 | #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) |
186 | #define S3C2410_GPB3_INP (0x00 << 6) | 213 | #define S3C2410_GPB3_INP (0x00 << 6) |
187 | #define S3C2410_GPB3_OUTP (0x01 << 6) | 214 | #define S3C2410_GPB3_OUTP (0x01 << 6) |
188 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) | 215 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) |
216 | #define S3C2400_GPB3_DATA19 (0x02 << 6) | ||
217 | #define S3C2400_GPB3_TXD1 (0x03 << 6) | ||
189 | 218 | ||
190 | #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) | 219 | #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) |
191 | #define S3C2410_GPB4_INP (0x00 << 8) | 220 | #define S3C2410_GPB4_INP (0x00 << 8) |
192 | #define S3C2410_GPB4_OUTP (0x01 << 8) | 221 | #define S3C2410_GPB4_OUTP (0x01 << 8) |
193 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) | 222 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) |
223 | #define S3C2400_GPB4_DATA20 (0x02 << 8) | ||
194 | #define S3C2410_GPB4_MASK (0x03 << 8) | 224 | #define S3C2410_GPB4_MASK (0x03 << 8) |
225 | #define S3C2400_GPB4_RXD1 (0x03 << 8) | ||
226 | #define S3C2400_GPB4_MASK (0x03 << 8) | ||
195 | 227 | ||
196 | #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) | 228 | #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) |
197 | #define S3C2410_GPB5_INP (0x00 << 10) | 229 | #define S3C2410_GPB5_INP (0x00 << 10) |
198 | #define S3C2410_GPB5_OUTP (0x01 << 10) | 230 | #define S3C2410_GPB5_OUTP (0x01 << 10) |
199 | #define S3C2410_GPB5_nXBACK (0x02 << 10) | 231 | #define S3C2410_GPB5_nXBACK (0x02 << 10) |
232 | #define S3C2400_GPB5_DATA21 (0x02 << 10) | ||
233 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) | ||
200 | 234 | ||
201 | #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) | 235 | #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) |
202 | #define S3C2410_GPB6_INP (0x00 << 12) | 236 | #define S3C2410_GPB6_INP (0x00 << 12) |
203 | #define S3C2410_GPB6_OUTP (0x01 << 12) | 237 | #define S3C2410_GPB6_OUTP (0x01 << 12) |
204 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) | 238 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) |
239 | #define S3C2400_GPB6_DATA22 (0x02 << 12) | ||
240 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) | ||
205 | 241 | ||
206 | #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) | 242 | #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) |
207 | #define S3C2410_GPB7_INP (0x00 << 14) | 243 | #define S3C2410_GPB7_INP (0x00 << 14) |
208 | #define S3C2410_GPB7_OUTP (0x01 << 14) | 244 | #define S3C2410_GPB7_OUTP (0x01 << 14) |
209 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) | 245 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) |
246 | #define S3C2400_GPB7_DATA23 (0x02 << 14) | ||
210 | 247 | ||
211 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) | 248 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) |
212 | #define S3C2410_GPB8_INP (0x00 << 16) | 249 | #define S3C2410_GPB8_INP (0x00 << 16) |
213 | #define S3C2410_GPB8_OUTP (0x01 << 16) | 250 | #define S3C2410_GPB8_OUTP (0x01 << 16) |
214 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) | 251 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) |
252 | #define S3C2400_GPB8_DATA24 (0x02 << 16) | ||
215 | 253 | ||
216 | #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) | 254 | #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) |
217 | #define S3C2410_GPB9_INP (0x00 << 18) | 255 | #define S3C2410_GPB9_INP (0x00 << 18) |
218 | #define S3C2410_GPB9_OUTP (0x01 << 18) | 256 | #define S3C2410_GPB9_OUTP (0x01 << 18) |
219 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) | 257 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) |
258 | #define S3C2400_GPB9_DATA25 (0x02 << 18) | ||
259 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) | ||
220 | 260 | ||
221 | #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) | 261 | #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) |
222 | #define S3C2410_GPB10_INP (0x00 << 20) | 262 | #define S3C2410_GPB10_INP (0x00 << 20) |
223 | #define S3C2410_GPB10_OUTP (0x01 << 20) | 263 | #define S3C2410_GPB10_OUTP (0x01 << 20) |
224 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) | 264 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) |
265 | #define S3C2400_GPB10_DATA26 (0x02 << 20) | ||
266 | #define S3C2400_GPB10_nSS (0x03 << 20) | ||
267 | |||
268 | #define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11) | ||
269 | #define S3C2400_GPB11_INP (0x00 << 22) | ||
270 | #define S3C2400_GPB11_OUTP (0x01 << 22) | ||
271 | #define S3C2400_GPB11_DATA27 (0x02 << 22) | ||
272 | |||
273 | #define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12) | ||
274 | #define S3C2400_GPB12_INP (0x00 << 24) | ||
275 | #define S3C2400_GPB12_OUTP (0x01 << 24) | ||
276 | #define S3C2400_GPB12_DATA28 (0x02 << 24) | ||
277 | |||
278 | #define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13) | ||
279 | #define S3C2400_GPB13_INP (0x00 << 26) | ||
280 | #define S3C2400_GPB13_OUTP (0x01 << 26) | ||
281 | #define S3C2400_GPB13_DATA29 (0x02 << 26) | ||
282 | |||
283 | #define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14) | ||
284 | #define S3C2400_GPB14_INP (0x00 << 28) | ||
285 | #define S3C2400_GPB14_OUTP (0x01 << 28) | ||
286 | #define S3C2400_GPB14_DATA30 (0x02 << 28) | ||
287 | |||
288 | #define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15) | ||
289 | #define S3C2400_GPB15_INP (0x00 << 30) | ||
290 | #define S3C2400_GPB15_OUTP (0x01 << 30) | ||
291 | #define S3C2400_GPB15_DATA31 (0x02 << 30) | ||
292 | |||
293 | #define S3C2410_GPB_PUPDIS(x) (1<<(x)) | ||
225 | 294 | ||
226 | /* Port C consits of 16 GPIO/Special function | 295 | /* Port C consits of 16 GPIO/Special function |
227 | * | 296 | * |
@@ -233,150 +302,193 @@ | |||
233 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) | 302 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) |
234 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) | 303 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) |
235 | 304 | ||
305 | #define S3C2400_GPCCON S3C2410_GPIOREG(0x14) | ||
306 | #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) | ||
307 | #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) | ||
308 | |||
236 | #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) | 309 | #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) |
237 | #define S3C2410_GPC0_INP (0x00 << 0) | 310 | #define S3C2410_GPC0_INP (0x00 << 0) |
238 | #define S3C2410_GPC0_OUTP (0x01 << 0) | 311 | #define S3C2410_GPC0_OUTP (0x01 << 0) |
239 | #define S3C2410_GPC0_LEND (0x02 << 0) | 312 | #define S3C2410_GPC0_LEND (0x02 << 0) |
313 | #define S3C2400_GPC0_VD0 (0x02 << 0) | ||
240 | 314 | ||
241 | #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) | 315 | #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) |
242 | #define S3C2410_GPC1_INP (0x00 << 2) | 316 | #define S3C2410_GPC1_INP (0x00 << 2) |
243 | #define S3C2410_GPC1_OUTP (0x01 << 2) | 317 | #define S3C2410_GPC1_OUTP (0x01 << 2) |
244 | #define S3C2410_GPC1_VCLK (0x02 << 2) | 318 | #define S3C2410_GPC1_VCLK (0x02 << 2) |
319 | #define S3C2400_GPC1_VD1 (0x02 << 2) | ||
245 | 320 | ||
246 | #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) | 321 | #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) |
247 | #define S3C2410_GPC2_INP (0x00 << 4) | 322 | #define S3C2410_GPC2_INP (0x00 << 4) |
248 | #define S3C2410_GPC2_OUTP (0x01 << 4) | 323 | #define S3C2410_GPC2_OUTP (0x01 << 4) |
249 | #define S3C2410_GPC2_VLINE (0x02 << 4) | 324 | #define S3C2410_GPC2_VLINE (0x02 << 4) |
325 | #define S3C2400_GPC2_VD2 (0x02 << 4) | ||
250 | 326 | ||
251 | #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) | 327 | #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) |
252 | #define S3C2410_GPC3_INP (0x00 << 6) | 328 | #define S3C2410_GPC3_INP (0x00 << 6) |
253 | #define S3C2410_GPC3_OUTP (0x01 << 6) | 329 | #define S3C2410_GPC3_OUTP (0x01 << 6) |
254 | #define S3C2410_GPC3_VFRAME (0x02 << 6) | 330 | #define S3C2410_GPC3_VFRAME (0x02 << 6) |
331 | #define S3C2400_GPC3_VD3 (0x02 << 6) | ||
255 | 332 | ||
256 | #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) | 333 | #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) |
257 | #define S3C2410_GPC4_INP (0x00 << 8) | 334 | #define S3C2410_GPC4_INP (0x00 << 8) |
258 | #define S3C2410_GPC4_OUTP (0x01 << 8) | 335 | #define S3C2410_GPC4_OUTP (0x01 << 8) |
259 | #define S3C2410_GPC4_VM (0x02 << 8) | 336 | #define S3C2410_GPC4_VM (0x02 << 8) |
337 | #define S3C2400_GPC4_VD4 (0x02 << 8) | ||
260 | 338 | ||
261 | #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) | 339 | #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) |
262 | #define S3C2410_GPC5_INP (0x00 << 10) | 340 | #define S3C2410_GPC5_INP (0x00 << 10) |
263 | #define S3C2410_GPC5_OUTP (0x01 << 10) | 341 | #define S3C2410_GPC5_OUTP (0x01 << 10) |
264 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) | 342 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) |
343 | #define S3C2400_GPC5_VD5 (0x02 << 10) | ||
265 | 344 | ||
266 | #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) | 345 | #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) |
267 | #define S3C2410_GPC6_INP (0x00 << 12) | 346 | #define S3C2410_GPC6_INP (0x00 << 12) |
268 | #define S3C2410_GPC6_OUTP (0x01 << 12) | 347 | #define S3C2410_GPC6_OUTP (0x01 << 12) |
269 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) | 348 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) |
349 | #define S3C2400_GPC6_VD6 (0x02 << 12) | ||
270 | 350 | ||
271 | #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) | 351 | #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) |
272 | #define S3C2410_GPC7_INP (0x00 << 14) | 352 | #define S3C2410_GPC7_INP (0x00 << 14) |
273 | #define S3C2410_GPC7_OUTP (0x01 << 14) | 353 | #define S3C2410_GPC7_OUTP (0x01 << 14) |
274 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) | 354 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) |
355 | #define S3C2400_GPC7_VD7 (0x02 << 14) | ||
275 | 356 | ||
276 | #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) | 357 | #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) |
277 | #define S3C2410_GPC8_INP (0x00 << 16) | 358 | #define S3C2410_GPC8_INP (0x00 << 16) |
278 | #define S3C2410_GPC8_OUTP (0x01 << 16) | 359 | #define S3C2410_GPC8_OUTP (0x01 << 16) |
279 | #define S3C2410_GPC8_VD0 (0x02 << 16) | 360 | #define S3C2410_GPC8_VD0 (0x02 << 16) |
361 | #define S3C2400_GPC8_VD8 (0x02 << 16) | ||
280 | 362 | ||
281 | #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) | 363 | #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) |
282 | #define S3C2410_GPC9_INP (0x00 << 18) | 364 | #define S3C2410_GPC9_INP (0x00 << 18) |
283 | #define S3C2410_GPC9_OUTP (0x01 << 18) | 365 | #define S3C2410_GPC9_OUTP (0x01 << 18) |
284 | #define S3C2410_GPC9_VD1 (0x02 << 18) | 366 | #define S3C2410_GPC9_VD1 (0x02 << 18) |
367 | #define S3C2400_GPC9_VD9 (0x02 << 18) | ||
285 | 368 | ||
286 | #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) | 369 | #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) |
287 | #define S3C2410_GPC10_INP (0x00 << 20) | 370 | #define S3C2410_GPC10_INP (0x00 << 20) |
288 | #define S3C2410_GPC10_OUTP (0x01 << 20) | 371 | #define S3C2410_GPC10_OUTP (0x01 << 20) |
289 | #define S3C2410_GPC10_VD2 (0x02 << 20) | 372 | #define S3C2410_GPC10_VD2 (0x02 << 20) |
373 | #define S3C2400_GPC10_VD10 (0x02 << 20) | ||
290 | 374 | ||
291 | #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) | 375 | #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) |
292 | #define S3C2410_GPC11_INP (0x00 << 22) | 376 | #define S3C2410_GPC11_INP (0x00 << 22) |
293 | #define S3C2410_GPC11_OUTP (0x01 << 22) | 377 | #define S3C2410_GPC11_OUTP (0x01 << 22) |
294 | #define S3C2410_GPC11_VD3 (0x02 << 22) | 378 | #define S3C2410_GPC11_VD3 (0x02 << 22) |
379 | #define S3C2400_GPC11_VD11 (0x02 << 22) | ||
295 | 380 | ||
296 | #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) | 381 | #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) |
297 | #define S3C2410_GPC12_INP (0x00 << 24) | 382 | #define S3C2410_GPC12_INP (0x00 << 24) |
298 | #define S3C2410_GPC12_OUTP (0x01 << 24) | 383 | #define S3C2410_GPC12_OUTP (0x01 << 24) |
299 | #define S3C2410_GPC12_VD4 (0x02 << 24) | 384 | #define S3C2410_GPC12_VD4 (0x02 << 24) |
385 | #define S3C2400_GPC12_VD12 (0x02 << 24) | ||
300 | 386 | ||
301 | #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) | 387 | #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) |
302 | #define S3C2410_GPC13_INP (0x00 << 26) | 388 | #define S3C2410_GPC13_INP (0x00 << 26) |
303 | #define S3C2410_GPC13_OUTP (0x01 << 26) | 389 | #define S3C2410_GPC13_OUTP (0x01 << 26) |
304 | #define S3C2410_GPC13_VD5 (0x02 << 26) | 390 | #define S3C2410_GPC13_VD5 (0x02 << 26) |
391 | #define S3C2400_GPC13_VD13 (0x02 << 26) | ||
305 | 392 | ||
306 | #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) | 393 | #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) |
307 | #define S3C2410_GPC14_INP (0x00 << 28) | 394 | #define S3C2410_GPC14_INP (0x00 << 28) |
308 | #define S3C2410_GPC14_OUTP (0x01 << 28) | 395 | #define S3C2410_GPC14_OUTP (0x01 << 28) |
309 | #define S3C2410_GPC14_VD6 (0x02 << 28) | 396 | #define S3C2410_GPC14_VD6 (0x02 << 28) |
397 | #define S3C2400_GPC14_VD14 (0x02 << 28) | ||
310 | 398 | ||
311 | #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) | 399 | #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) |
312 | #define S3C2410_GPC15_INP (0x00 << 30) | 400 | #define S3C2410_GPC15_INP (0x00 << 30) |
313 | #define S3C2410_GPC15_OUTP (0x01 << 30) | 401 | #define S3C2410_GPC15_OUTP (0x01 << 30) |
314 | #define S3C2410_GPC15_VD7 (0x02 << 30) | 402 | #define S3C2410_GPC15_VD7 (0x02 << 30) |
403 | #define S3C2400_GPC15_VD15 (0x02 << 30) | ||
404 | |||
405 | #define S3C2410_GPC_PUPDIS(x) (1<<(x)) | ||
315 | 406 | ||
316 | /* Port D consists of 16 GPIO/Special function | 407 | /* |
408 | * S3C2410: Port D consists of 16 GPIO/Special function | ||
317 | * | 409 | * |
318 | * almost identical setup to port b, but the special functions are mostly | 410 | * almost identical setup to port b, but the special functions are mostly |
319 | * to do with the video system's data. | 411 | * to do with the video system's data. |
412 | * | ||
413 | * S3C2400: Port D consists of 11 GPIO/Special function | ||
414 | * | ||
415 | * almost identical setup to port c | ||
320 | */ | 416 | */ |
321 | 417 | ||
322 | #define S3C2410_GPDCON S3C2410_GPIOREG(0x30) | 418 | #define S3C2410_GPDCON S3C2410_GPIOREG(0x30) |
323 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) | 419 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) |
324 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) | 420 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) |
325 | 421 | ||
422 | #define S3C2400_GPDCON S3C2410_GPIOREG(0x20) | ||
423 | #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) | ||
424 | #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) | ||
425 | |||
326 | #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) | 426 | #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) |
327 | #define S3C2410_GPD0_INP (0x00 << 0) | 427 | #define S3C2410_GPD0_INP (0x00 << 0) |
328 | #define S3C2410_GPD0_OUTP (0x01 << 0) | 428 | #define S3C2410_GPD0_OUTP (0x01 << 0) |
329 | #define S3C2410_GPD0_VD8 (0x02 << 0) | 429 | #define S3C2410_GPD0_VD8 (0x02 << 0) |
430 | #define S3C2400_GPD0_VFRAME (0x02 << 0) | ||
330 | 431 | ||
331 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) | 432 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) |
332 | #define S3C2410_GPD1_INP (0x00 << 2) | 433 | #define S3C2410_GPD1_INP (0x00 << 2) |
333 | #define S3C2410_GPD1_OUTP (0x01 << 2) | 434 | #define S3C2410_GPD1_OUTP (0x01 << 2) |
334 | #define S3C2410_GPD1_VD9 (0x02 << 2) | 435 | #define S3C2410_GPD1_VD9 (0x02 << 2) |
436 | #define S3C2400_GPD1_VM (0x02 << 2) | ||
335 | 437 | ||
336 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) | 438 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) |
337 | #define S3C2410_GPD2_INP (0x00 << 4) | 439 | #define S3C2410_GPD2_INP (0x00 << 4) |
338 | #define S3C2410_GPD2_OUTP (0x01 << 4) | 440 | #define S3C2410_GPD2_OUTP (0x01 << 4) |
339 | #define S3C2410_GPD2_VD10 (0x02 << 4) | 441 | #define S3C2410_GPD2_VD10 (0x02 << 4) |
442 | #define S3C2400_GPD2_VLINE (0x02 << 4) | ||
340 | 443 | ||
341 | #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) | 444 | #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) |
342 | #define S3C2410_GPD3_INP (0x00 << 6) | 445 | #define S3C2410_GPD3_INP (0x00 << 6) |
343 | #define S3C2410_GPD3_OUTP (0x01 << 6) | 446 | #define S3C2410_GPD3_OUTP (0x01 << 6) |
344 | #define S3C2410_GPD3_VD11 (0x02 << 6) | 447 | #define S3C2410_GPD3_VD11 (0x02 << 6) |
448 | #define S3C2400_GPD3_VCLK (0x02 << 6) | ||
345 | 449 | ||
346 | #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) | 450 | #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) |
347 | #define S3C2410_GPD4_INP (0x00 << 8) | 451 | #define S3C2410_GPD4_INP (0x00 << 8) |
348 | #define S3C2410_GPD4_OUTP (0x01 << 8) | 452 | #define S3C2410_GPD4_OUTP (0x01 << 8) |
349 | #define S3C2410_GPD4_VD12 (0x02 << 8) | 453 | #define S3C2410_GPD4_VD12 (0x02 << 8) |
454 | #define S3C2400_GPD4_LEND (0x02 << 8) | ||
350 | 455 | ||
351 | #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) | 456 | #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) |
352 | #define S3C2410_GPD5_INP (0x00 << 10) | 457 | #define S3C2410_GPD5_INP (0x00 << 10) |
353 | #define S3C2410_GPD5_OUTP (0x01 << 10) | 458 | #define S3C2410_GPD5_OUTP (0x01 << 10) |
354 | #define S3C2410_GPD5_VD13 (0x02 << 10) | 459 | #define S3C2410_GPD5_VD13 (0x02 << 10) |
460 | #define S3C2400_GPD5_TOUT0 (0x02 << 10) | ||
355 | 461 | ||
356 | #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) | 462 | #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) |
357 | #define S3C2410_GPD6_INP (0x00 << 12) | 463 | #define S3C2410_GPD6_INP (0x00 << 12) |
358 | #define S3C2410_GPD6_OUTP (0x01 << 12) | 464 | #define S3C2410_GPD6_OUTP (0x01 << 12) |
359 | #define S3C2410_GPD6_VD14 (0x02 << 12) | 465 | #define S3C2410_GPD6_VD14 (0x02 << 12) |
466 | #define S3C2400_GPD6_TOUT1 (0x02 << 12) | ||
360 | 467 | ||
361 | #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) | 468 | #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) |
362 | #define S3C2410_GPD7_INP (0x00 << 14) | 469 | #define S3C2410_GPD7_INP (0x00 << 14) |
363 | #define S3C2410_GPD7_OUTP (0x01 << 14) | 470 | #define S3C2410_GPD7_OUTP (0x01 << 14) |
364 | #define S3C2410_GPD7_VD15 (0x02 << 14) | 471 | #define S3C2410_GPD7_VD15 (0x02 << 14) |
472 | #define S3C2400_GPD7_TOUT2 (0x02 << 14) | ||
365 | 473 | ||
366 | #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) | 474 | #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) |
367 | #define S3C2410_GPD8_INP (0x00 << 16) | 475 | #define S3C2410_GPD8_INP (0x00 << 16) |
368 | #define S3C2410_GPD8_OUTP (0x01 << 16) | 476 | #define S3C2410_GPD8_OUTP (0x01 << 16) |
369 | #define S3C2410_GPD8_VD16 (0x02 << 16) | 477 | #define S3C2410_GPD8_VD16 (0x02 << 16) |
478 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) | ||
370 | 479 | ||
371 | #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) | 480 | #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) |
372 | #define S3C2410_GPD9_INP (0x00 << 18) | 481 | #define S3C2410_GPD9_INP (0x00 << 18) |
373 | #define S3C2410_GPD9_OUTP (0x01 << 18) | 482 | #define S3C2410_GPD9_OUTP (0x01 << 18) |
374 | #define S3C2410_GPD9_VD17 (0x02 << 18) | 483 | #define S3C2410_GPD9_VD17 (0x02 << 18) |
484 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) | ||
485 | #define S3C2410_GPD9_MASK (0x03 << 18) | ||
375 | 486 | ||
376 | #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) | 487 | #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) |
377 | #define S3C2410_GPD10_INP (0x00 << 20) | 488 | #define S3C2410_GPD10_INP (0x00 << 20) |
378 | #define S3C2410_GPD10_OUTP (0x01 << 20) | 489 | #define S3C2410_GPD10_OUTP (0x01 << 20) |
379 | #define S3C2410_GPD10_VD18 (0x02 << 20) | 490 | #define S3C2410_GPD10_VD18 (0x02 << 20) |
491 | #define S3C2400_GPD10_nWAIT (0x02 << 20) | ||
380 | 492 | ||
381 | #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) | 493 | #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) |
382 | #define S3C2410_GPD11_INP (0x00 << 22) | 494 | #define S3C2410_GPD11_INP (0x00 << 22) |
@@ -403,37 +515,56 @@ | |||
403 | #define S3C2410_GPD15_OUTP (0x01 << 30) | 515 | #define S3C2410_GPD15_OUTP (0x01 << 30) |
404 | #define S3C2410_GPD15_VD23 (0x02 << 30) | 516 | #define S3C2410_GPD15_VD23 (0x02 << 30) |
405 | 517 | ||
406 | /* Port E consists of 16 GPIO/Special function | 518 | #define S3C2410_GPD_PUPDIS(x) (1<<(x)) |
519 | |||
520 | /* S3C2410: | ||
521 | * Port E consists of 16 GPIO/Special function | ||
407 | * | 522 | * |
408 | * again, the same as port B, but dealing with I2S, SDI, and | 523 | * again, the same as port B, but dealing with I2S, SDI, and |
409 | * more miscellaneous functions | 524 | * more miscellaneous functions |
525 | * | ||
526 | * S3C2400: | ||
527 | * Port E consists of 12 GPIO/Special function | ||
528 | * | ||
529 | * GPIO / interrupt inputs | ||
410 | */ | 530 | */ |
411 | 531 | ||
412 | #define S3C2410_GPECON S3C2410_GPIOREG(0x40) | 532 | #define S3C2410_GPECON S3C2410_GPIOREG(0x40) |
413 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) | 533 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) |
414 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) | 534 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) |
415 | 535 | ||
536 | #define S3C2400_GPECON S3C2410_GPIOREG(0x2C) | ||
537 | #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) | ||
538 | #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) | ||
539 | |||
416 | #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) | 540 | #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) |
417 | #define S3C2410_GPE0_INP (0x00 << 0) | 541 | #define S3C2410_GPE0_INP (0x00 << 0) |
418 | #define S3C2410_GPE0_OUTP (0x01 << 0) | 542 | #define S3C2410_GPE0_OUTP (0x01 << 0) |
419 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) | 543 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) |
544 | #define S3C2400_GPE0_EINT0 (0x02 << 0) | ||
420 | #define S3C2410_GPE0_MASK (0x03 << 0) | 545 | #define S3C2410_GPE0_MASK (0x03 << 0) |
421 | 546 | ||
422 | #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) | 547 | #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) |
423 | #define S3C2410_GPE1_INP (0x00 << 2) | 548 | #define S3C2410_GPE1_INP (0x00 << 2) |
424 | #define S3C2410_GPE1_OUTP (0x01 << 2) | 549 | #define S3C2410_GPE1_OUTP (0x01 << 2) |
425 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) | 550 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) |
551 | #define S3C2400_GPE1_EINT1 (0x02 << 2) | ||
552 | #define S3C2400_GPE1_nSS (0x03 << 2) | ||
426 | #define S3C2410_GPE1_MASK (0x03 << 2) | 553 | #define S3C2410_GPE1_MASK (0x03 << 2) |
427 | 554 | ||
428 | #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) | 555 | #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) |
429 | #define S3C2410_GPE2_INP (0x00 << 4) | 556 | #define S3C2410_GPE2_INP (0x00 << 4) |
430 | #define S3C2410_GPE2_OUTP (0x01 << 4) | 557 | #define S3C2410_GPE2_OUTP (0x01 << 4) |
431 | #define S3C2410_GPE2_CDCLK (0x02 << 4) | 558 | #define S3C2410_GPE2_CDCLK (0x02 << 4) |
559 | #define S3C2400_GPE2_EINT2 (0x02 << 4) | ||
560 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) | ||
432 | 561 | ||
433 | #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) | 562 | #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) |
434 | #define S3C2410_GPE3_INP (0x00 << 6) | 563 | #define S3C2410_GPE3_INP (0x00 << 6) |
435 | #define S3C2410_GPE3_OUTP (0x01 << 6) | 564 | #define S3C2410_GPE3_OUTP (0x01 << 6) |
436 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) | 565 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) |
566 | #define S3C2400_GPE3_EINT3 (0x02 << 6) | ||
567 | #define S3C2400_GPE3_nCTS1 (0x03 << 6) | ||
437 | #define S3C2410_GPE3_nSS0 (0x03 << 6) | 568 | #define S3C2410_GPE3_nSS0 (0x03 << 6) |
438 | #define S3C2410_GPE3_MASK (0x03 << 6) | 569 | #define S3C2410_GPE3_MASK (0x03 << 6) |
439 | 570 | ||
@@ -441,6 +572,8 @@ | |||
441 | #define S3C2410_GPE4_INP (0x00 << 8) | 572 | #define S3C2410_GPE4_INP (0x00 << 8) |
442 | #define S3C2410_GPE4_OUTP (0x01 << 8) | 573 | #define S3C2410_GPE4_OUTP (0x01 << 8) |
443 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) | 574 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) |
575 | #define S3C2400_GPE4_EINT4 (0x02 << 8) | ||
576 | #define S3C2400_GPE4_nRTS1 (0x03 << 8) | ||
444 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) | 577 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) |
445 | #define S3C2410_GPE4_MASK (0x03 << 8) | 578 | #define S3C2410_GPE4_MASK (0x03 << 8) |
446 | 579 | ||
@@ -448,36 +581,46 @@ | |||
448 | #define S3C2410_GPE5_INP (0x00 << 10) | 581 | #define S3C2410_GPE5_INP (0x00 << 10) |
449 | #define S3C2410_GPE5_OUTP (0x01 << 10) | 582 | #define S3C2410_GPE5_OUTP (0x01 << 10) |
450 | #define S3C2410_GPE5_SDCLK (0x02 << 10) | 583 | #define S3C2410_GPE5_SDCLK (0x02 << 10) |
584 | #define S3C2400_GPE5_EINT5 (0x02 << 10) | ||
585 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) | ||
451 | 586 | ||
452 | #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) | 587 | #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) |
453 | #define S3C2410_GPE6_INP (0x00 << 12) | 588 | #define S3C2410_GPE6_INP (0x00 << 12) |
454 | #define S3C2410_GPE6_OUTP (0x01 << 12) | 589 | #define S3C2410_GPE6_OUTP (0x01 << 12) |
455 | #define S3C2410_GPE6_SDCMD (0x02 << 12) | 590 | #define S3C2410_GPE6_SDCMD (0x02 << 12) |
591 | #define S3C2400_GPE6_EINT6 (0x02 << 12) | ||
456 | 592 | ||
457 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) | 593 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) |
458 | #define S3C2410_GPE7_INP (0x00 << 14) | 594 | #define S3C2410_GPE7_INP (0x00 << 14) |
459 | #define S3C2410_GPE7_OUTP (0x01 << 14) | 595 | #define S3C2410_GPE7_OUTP (0x01 << 14) |
460 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) | 596 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) |
597 | #define S3C2400_GPE7_EINT7 (0x02 << 14) | ||
461 | 598 | ||
462 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) | 599 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) |
463 | #define S3C2410_GPE8_INP (0x00 << 16) | 600 | #define S3C2410_GPE8_INP (0x00 << 16) |
464 | #define S3C2410_GPE8_OUTP (0x01 << 16) | 601 | #define S3C2410_GPE8_OUTP (0x01 << 16) |
465 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) | 602 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) |
603 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) | ||
466 | 604 | ||
467 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) | 605 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) |
468 | #define S3C2410_GPE9_INP (0x00 << 18) | 606 | #define S3C2410_GPE9_INP (0x00 << 18) |
469 | #define S3C2410_GPE9_OUTP (0x01 << 18) | 607 | #define S3C2410_GPE9_OUTP (0x01 << 18) |
470 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) | 608 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) |
609 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) | ||
610 | #define S3C2400_GPE9_nXBACK (0x03 << 18) | ||
471 | 611 | ||
472 | #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) | 612 | #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) |
473 | #define S3C2410_GPE10_INP (0x00 << 20) | 613 | #define S3C2410_GPE10_INP (0x00 << 20) |
474 | #define S3C2410_GPE10_OUTP (0x01 << 20) | 614 | #define S3C2410_GPE10_OUTP (0x01 << 20) |
475 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) | 615 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) |
616 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) | ||
476 | 617 | ||
477 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) | 618 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) |
478 | #define S3C2410_GPE11_INP (0x00 << 22) | 619 | #define S3C2410_GPE11_INP (0x00 << 22) |
479 | #define S3C2410_GPE11_OUTP (0x01 << 22) | 620 | #define S3C2410_GPE11_OUTP (0x01 << 22) |
480 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) | 621 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) |
622 | #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) | ||
623 | #define S3C2400_GPE11_nXBREQ (0x03 << 22) | ||
481 | 624 | ||
482 | #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) | 625 | #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) |
483 | #define S3C2410_GPE12_INP (0x00 << 24) | 626 | #define S3C2410_GPE12_INP (0x00 << 24) |
@@ -509,7 +652,8 @@ | |||
509 | 652 | ||
510 | #define S3C2410_GPE_PUPDIS(x) (1<<(x)) | 653 | #define S3C2410_GPE_PUPDIS(x) (1<<(x)) |
511 | 654 | ||
512 | /* Port F consists of 8 GPIO/Special function | 655 | /* S3C2410: |
656 | * Port F consists of 8 GPIO/Special function | ||
513 | * | 657 | * |
514 | * GPIO / interrupt inputs | 658 | * GPIO / interrupt inputs |
515 | * | 659 | * |
@@ -517,100 +661,141 @@ | |||
517 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined | 661 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined |
518 | * | 662 | * |
519 | * pull up works like all other ports. | 663 | * pull up works like all other ports. |
664 | * | ||
665 | * S3C2400: | ||
666 | * Port F consists of 7 GPIO/Special function | ||
667 | * | ||
668 | * GPIO/serial/misc pins | ||
520 | */ | 669 | */ |
521 | 670 | ||
522 | #define S3C2410_GPFCON S3C2410_GPIOREG(0x50) | 671 | #define S3C2410_GPFCON S3C2410_GPIOREG(0x50) |
523 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) | 672 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) |
524 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) | 673 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) |
525 | 674 | ||
675 | #define S3C2400_GPFCON S3C2410_GPIOREG(0x38) | ||
676 | #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) | ||
677 | #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) | ||
678 | |||
526 | #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) | 679 | #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) |
527 | #define S3C2410_GPF0_INP (0x00 << 0) | 680 | #define S3C2410_GPF0_INP (0x00 << 0) |
528 | #define S3C2410_GPF0_OUTP (0x01 << 0) | 681 | #define S3C2410_GPF0_OUTP (0x01 << 0) |
529 | #define S3C2410_GPF0_EINT0 (0x02 << 0) | 682 | #define S3C2410_GPF0_EINT0 (0x02 << 0) |
683 | #define S3C2400_GPF0_RXD0 (0x02 << 0) | ||
530 | 684 | ||
531 | #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) | 685 | #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) |
532 | #define S3C2410_GPF1_INP (0x00 << 2) | 686 | #define S3C2410_GPF1_INP (0x00 << 2) |
533 | #define S3C2410_GPF1_OUTP (0x01 << 2) | 687 | #define S3C2410_GPF1_OUTP (0x01 << 2) |
534 | #define S3C2410_GPF1_EINT1 (0x02 << 2) | 688 | #define S3C2410_GPF1_EINT1 (0x02 << 2) |
689 | #define S3C2400_GPF1_RXD1 (0x02 << 2) | ||
690 | #define S3C2400_GPF1_IICSDA (0x03 << 2) | ||
535 | 691 | ||
536 | #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) | 692 | #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) |
537 | #define S3C2410_GPF2_INP (0x00 << 4) | 693 | #define S3C2410_GPF2_INP (0x00 << 4) |
538 | #define S3C2410_GPF2_OUTP (0x01 << 4) | 694 | #define S3C2410_GPF2_OUTP (0x01 << 4) |
539 | #define S3C2410_GPF2_EINT2 (0x02 << 4) | 695 | #define S3C2410_GPF2_EINT2 (0x02 << 4) |
696 | #define S3C2400_GPF2_TXD0 (0x02 << 4) | ||
540 | 697 | ||
541 | #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) | 698 | #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) |
542 | #define S3C2410_GPF3_INP (0x00 << 6) | 699 | #define S3C2410_GPF3_INP (0x00 << 6) |
543 | #define S3C2410_GPF3_OUTP (0x01 << 6) | 700 | #define S3C2410_GPF3_OUTP (0x01 << 6) |
544 | #define S3C2410_GPF3_EINT3 (0x02 << 6) | 701 | #define S3C2410_GPF3_EINT3 (0x02 << 6) |
702 | #define S3C2400_GPF3_TXD1 (0x02 << 6) | ||
703 | #define S3C2400_GPF3_IICSCL (0x03 << 6) | ||
545 | 704 | ||
546 | #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) | 705 | #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) |
547 | #define S3C2410_GPF4_INP (0x00 << 8) | 706 | #define S3C2410_GPF4_INP (0x00 << 8) |
548 | #define S3C2410_GPF4_OUTP (0x01 << 8) | 707 | #define S3C2410_GPF4_OUTP (0x01 << 8) |
549 | #define S3C2410_GPF4_EINT4 (0x02 << 8) | 708 | #define S3C2410_GPF4_EINT4 (0x02 << 8) |
709 | #define S3C2400_GPF4_nRTS0 (0x02 << 8) | ||
710 | #define S3C2400_GPF4_nXBACK (0x03 << 8) | ||
550 | 711 | ||
551 | #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) | 712 | #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) |
552 | #define S3C2410_GPF5_INP (0x00 << 10) | 713 | #define S3C2410_GPF5_INP (0x00 << 10) |
553 | #define S3C2410_GPF5_OUTP (0x01 << 10) | 714 | #define S3C2410_GPF5_OUTP (0x01 << 10) |
554 | #define S3C2410_GPF5_EINT5 (0x02 << 10) | 715 | #define S3C2410_GPF5_EINT5 (0x02 << 10) |
716 | #define S3C2400_GPF5_nCTS0 (0x02 << 10) | ||
717 | #define S3C2400_GPF5_nXBREQ (0x03 << 10) | ||
555 | 718 | ||
556 | #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) | 719 | #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) |
557 | #define S3C2410_GPF6_INP (0x00 << 12) | 720 | #define S3C2410_GPF6_INP (0x00 << 12) |
558 | #define S3C2410_GPF6_OUTP (0x01 << 12) | 721 | #define S3C2410_GPF6_OUTP (0x01 << 12) |
559 | #define S3C2410_GPF6_EINT6 (0x02 << 12) | 722 | #define S3C2410_GPF6_EINT6 (0x02 << 12) |
723 | #define S3C2400_GPF6_CLKOUT (0x02 << 12) | ||
560 | 724 | ||
561 | #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) | 725 | #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) |
562 | #define S3C2410_GPF7_INP (0x00 << 14) | 726 | #define S3C2410_GPF7_INP (0x00 << 14) |
563 | #define S3C2410_GPF7_OUTP (0x01 << 14) | 727 | #define S3C2410_GPF7_OUTP (0x01 << 14) |
564 | #define S3C2410_GPF7_EINT7 (0x02 << 14) | 728 | #define S3C2410_GPF7_EINT7 (0x02 << 14) |
565 | 729 | ||
566 | /* Port G consists of 8 GPIO/IRQ/Special function | 730 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) |
731 | |||
732 | /* S3C2410: | ||
733 | * Port G consists of 8 GPIO/IRQ/Special function | ||
567 | * | 734 | * |
568 | * GPGCON has 2 bits for each of the input pins on port F | 735 | * GPGCON has 2 bits for each of the input pins on port F |
569 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | 736 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
570 | * | 737 | * |
571 | * pull up works like all other ports. | 738 | * pull up works like all other ports. |
739 | * | ||
740 | * S3C2400: | ||
741 | * Port G consists of 10 GPIO/Special function | ||
572 | */ | 742 | */ |
573 | 743 | ||
574 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) | 744 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) |
575 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) | 745 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) |
576 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) | 746 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) |
577 | 747 | ||
748 | #define S3C2400_GPGCON S3C2410_GPIOREG(0x44) | ||
749 | #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) | ||
750 | #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) | ||
751 | |||
578 | #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) | 752 | #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) |
579 | #define S3C2410_GPG0_INP (0x00 << 0) | 753 | #define S3C2410_GPG0_INP (0x00 << 0) |
580 | #define S3C2410_GPG0_OUTP (0x01 << 0) | 754 | #define S3C2410_GPG0_OUTP (0x01 << 0) |
581 | #define S3C2410_GPG0_EINT8 (0x02 << 0) | 755 | #define S3C2410_GPG0_EINT8 (0x02 << 0) |
756 | #define S3C2400_GPG0_I2SLRCK (0x02 << 0) | ||
582 | 757 | ||
583 | #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) | 758 | #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) |
584 | #define S3C2410_GPG1_INP (0x00 << 2) | 759 | #define S3C2410_GPG1_INP (0x00 << 2) |
585 | #define S3C2410_GPG1_OUTP (0x01 << 2) | 760 | #define S3C2410_GPG1_OUTP (0x01 << 2) |
586 | #define S3C2410_GPG1_EINT9 (0x02 << 2) | 761 | #define S3C2410_GPG1_EINT9 (0x02 << 2) |
762 | #define S3C2400_GPG1_I2SSCLK (0x02 << 2) | ||
587 | 763 | ||
588 | #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) | 764 | #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) |
589 | #define S3C2410_GPG2_INP (0x00 << 4) | 765 | #define S3C2410_GPG2_INP (0x00 << 4) |
590 | #define S3C2410_GPG2_OUTP (0x01 << 4) | 766 | #define S3C2410_GPG2_OUTP (0x01 << 4) |
591 | #define S3C2410_GPG2_EINT10 (0x02 << 4) | 767 | #define S3C2410_GPG2_EINT10 (0x02 << 4) |
768 | #define S3C2400_GPG2_CDCLK (0x02 << 4) | ||
592 | 769 | ||
593 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) | 770 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) |
594 | #define S3C2410_GPG3_INP (0x00 << 6) | 771 | #define S3C2410_GPG3_INP (0x00 << 6) |
595 | #define S3C2410_GPG3_OUTP (0x01 << 6) | 772 | #define S3C2410_GPG3_OUTP (0x01 << 6) |
596 | #define S3C2410_GPG3_EINT11 (0x02 << 6) | 773 | #define S3C2410_GPG3_EINT11 (0x02 << 6) |
774 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) | ||
775 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) | ||
597 | 776 | ||
598 | #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) | 777 | #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) |
599 | #define S3C2410_GPG4_INP (0x00 << 8) | 778 | #define S3C2410_GPG4_INP (0x00 << 8) |
600 | #define S3C2410_GPG4_OUTP (0x01 << 8) | 779 | #define S3C2410_GPG4_OUTP (0x01 << 8) |
601 | #define S3C2410_GPG4_EINT12 (0x02 << 8) | 780 | #define S3C2410_GPG4_EINT12 (0x02 << 8) |
781 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) | ||
782 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) | ||
602 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) | 783 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) |
603 | 784 | ||
604 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) | 785 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) |
605 | #define S3C2410_GPG5_INP (0x00 << 10) | 786 | #define S3C2410_GPG5_INP (0x00 << 10) |
606 | #define S3C2410_GPG5_OUTP (0x01 << 10) | 787 | #define S3C2410_GPG5_OUTP (0x01 << 10) |
607 | #define S3C2410_GPG5_EINT13 (0x02 << 10) | 788 | #define S3C2410_GPG5_EINT13 (0x02 << 10) |
789 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) | ||
790 | #define S3C2400_GPG5_IICSDA (0x03 << 10) | ||
608 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) | 791 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) |
609 | 792 | ||
610 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) | 793 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) |
611 | #define S3C2410_GPG6_INP (0x00 << 12) | 794 | #define S3C2410_GPG6_INP (0x00 << 12) |
612 | #define S3C2410_GPG6_OUTP (0x01 << 12) | 795 | #define S3C2410_GPG6_OUTP (0x01 << 12) |
613 | #define S3C2410_GPG6_EINT14 (0x02 << 12) | 796 | #define S3C2410_GPG6_EINT14 (0x02 << 12) |
797 | #define S3C2400_GPG6_MMCDAT (0x02 << 12) | ||
798 | #define S3C2400_GPG6_IICSCL (0x03 << 12) | ||
614 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) | 799 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) |
615 | 800 | ||
616 | #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) | 801 | #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) |
@@ -618,16 +803,22 @@ | |||
618 | #define S3C2410_GPG7_OUTP (0x01 << 14) | 803 | #define S3C2410_GPG7_OUTP (0x01 << 14) |
619 | #define S3C2410_GPG7_EINT15 (0x02 << 14) | 804 | #define S3C2410_GPG7_EINT15 (0x02 << 14) |
620 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) | 805 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) |
806 | #define S3C2400_GPG7_SPIMISO (0x02 << 14) | ||
807 | #define S3C2400_GPG7_IICSDA (0x03 << 14) | ||
621 | 808 | ||
622 | #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) | 809 | #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) |
623 | #define S3C2410_GPG8_INP (0x00 << 16) | 810 | #define S3C2410_GPG8_INP (0x00 << 16) |
624 | #define S3C2410_GPG8_OUTP (0x01 << 16) | 811 | #define S3C2410_GPG8_OUTP (0x01 << 16) |
625 | #define S3C2410_GPG8_EINT16 (0x02 << 16) | 812 | #define S3C2410_GPG8_EINT16 (0x02 << 16) |
813 | #define S3C2400_GPG8_SPIMOSI (0x02 << 16) | ||
814 | #define S3C2400_GPG8_IICSCL (0x03 << 16) | ||
626 | 815 | ||
627 | #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) | 816 | #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) |
628 | #define S3C2410_GPG9_INP (0x00 << 18) | 817 | #define S3C2410_GPG9_INP (0x00 << 18) |
629 | #define S3C2410_GPG9_OUTP (0x01 << 18) | 818 | #define S3C2410_GPG9_OUTP (0x01 << 18) |
630 | #define S3C2410_GPG9_EINT17 (0x02 << 18) | 819 | #define S3C2410_GPG9_EINT17 (0x02 << 18) |
820 | #define S3C2400_GPG9_SPICLK (0x02 << 18) | ||
821 | #define S3C2400_GPG9_MMCCLK (0x03 << 18) | ||
631 | 822 | ||
632 | #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) | 823 | #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) |
633 | #define S3C2410_GPG10_INP (0x00 << 20) | 824 | #define S3C2410_GPG10_INP (0x00 << 20) |
@@ -737,19 +928,27 @@ | |||
737 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) | 928 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) |
738 | 929 | ||
739 | /* miscellaneous control */ | 930 | /* miscellaneous control */ |
740 | 931 | #define S3C2400_MISCCR S3C2410_GPIOREG(0x54) | |
741 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) | 932 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) |
742 | #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) | 933 | #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) |
743 | 934 | ||
744 | /* see clock.h for dclk definitions */ | 935 | /* see clock.h for dclk definitions */ |
745 | 936 | ||
746 | /* pullup control on databus */ | 937 | /* pullup control on databus */ |
747 | #define S3C2410_MISCCR_SPUCR_HEN (0) | 938 | #define S3C2410_MISCCR_SPUCR_HEN (0<<0) |
748 | #define S3C2410_MISCCR_SPUCR_HDIS (1<<0) | 939 | #define S3C2410_MISCCR_SPUCR_HDIS (1<<0) |
749 | #define S3C2410_MISCCR_SPUCR_LEN (0) | 940 | #define S3C2410_MISCCR_SPUCR_LEN (0<<1) |
750 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) | 941 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) |
751 | 942 | ||
752 | #define S3C2410_MISCCR_USBDEV (0) | 943 | #define S3C2400_MISCCR_SPUCR_LEN (0<<0) |
944 | #define S3C2400_MISCCR_SPUCR_LDIS (1<<0) | ||
945 | #define S3C2400_MISCCR_SPUCR_HEN (0<<1) | ||
946 | #define S3C2400_MISCCR_SPUCR_HDIS (1<<1) | ||
947 | |||
948 | #define S3C2400_MISCCR_HZ_STOPEN (0<<2) | ||
949 | #define S3C2400_MISCCR_HZ_STOPPREV (1<<2) | ||
950 | |||
951 | #define S3C2410_MISCCR_USBDEV (0<<3) | ||
753 | #define S3C2410_MISCCR_USBHOST (1<<3) | 952 | #define S3C2410_MISCCR_USBHOST (1<<3) |
754 | 953 | ||
755 | #define S3C2410_MISCCR_CLK0_MPLL (0<<4) | 954 | #define S3C2410_MISCCR_CLK0_MPLL (0<<4) |
@@ -785,7 +984,7 @@ | |||
785 | * | 984 | * |
786 | * Samsung datasheet p9-25 | 985 | * Samsung datasheet p9-25 |
787 | */ | 986 | */ |
788 | 987 | #define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58) | |
789 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) | 988 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) |
790 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) | 989 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) |
791 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) | 990 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) |
@@ -833,5 +1032,21 @@ | |||
833 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) | 1032 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) |
834 | #define S3C2410_GSTATUS2_PONRESET (1<<0) | 1033 | #define S3C2410_GSTATUS2_PONRESET (1<<0) |
835 | 1034 | ||
1035 | /* open drain control register */ | ||
1036 | #define S3C2400_OPENCR S3C2410_GPIOREG(0x50) | ||
1037 | |||
1038 | #define S3C2400_OPENCR_OPC_RXD1DIS (0<<0) | ||
1039 | #define S3C2400_OPENCR_OPC_RXD1EN (1<<0) | ||
1040 | #define S3C2400_OPENCR_OPC_TXD1DIS (0<<1) | ||
1041 | #define S3C2400_OPENCR_OPC_TXD1EN (1<<1) | ||
1042 | #define S3C2400_OPENCR_OPC_CMDDIS (0<<2) | ||
1043 | #define S3C2400_OPENCR_OPC_CMDEN (1<<2) | ||
1044 | #define S3C2400_OPENCR_OPC_DATDIS (0<<3) | ||
1045 | #define S3C2400_OPENCR_OPC_DATEN (1<<3) | ||
1046 | #define S3C2400_OPENCR_OPC_MISODIS (0<<4) | ||
1047 | #define S3C2400_OPENCR_OPC_MISOEN (1<<4) | ||
1048 | #define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) | ||
1049 | #define S3C2400_OPENCR_OPC_MOSIEN (1<<5) | ||
1050 | |||
836 | #endif /* __ASM_ARCH_REGS_GPIO_H */ | 1051 | #endif /* __ASM_ARCH_REGS_GPIO_H */ |
837 | 1052 | ||
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h index 9d4fe6cf205b..040ccde7a11e 100644 --- a/include/asm-arm/arch-sa1100/io.h +++ b/include/asm-arm/arch-sa1100/io.h | |||
@@ -10,8 +10,6 @@ | |||
10 | #ifndef __ASM_ARM_ARCH_IO_H | 10 | #ifndef __ASM_ARM_ARCH_IO_H |
11 | #define __ASM_ARM_ARCH_IO_H | 11 | #define __ASM_ARM_ARCH_IO_H |
12 | 12 | ||
13 | #include <asm/hardware.h> | ||
14 | |||
15 | #define IO_SPACE_LIMIT 0xffffffff | 13 | #define IO_SPACE_LIMIT 0xffffffff |
16 | 14 | ||
17 | /* | 15 | /* |
diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h index 71ca7d412687..d5dc624f452a 100644 --- a/include/asm-arm/semaphore.h +++ b/include/asm-arm/semaphore.h | |||
@@ -47,11 +47,6 @@ static inline void init_MUTEX_LOCKED(struct semaphore *sem) | |||
47 | sema_init(sem, 0); | 47 | sema_init(sem, 0); |
48 | } | 48 | } |
49 | 49 | ||
50 | static inline int sema_count(struct semaphore *sem) | ||
51 | { | ||
52 | return atomic_read(&sem->count); | ||
53 | } | ||
54 | |||
55 | /* | 50 | /* |
56 | * special register calling convention | 51 | * special register calling convention |
57 | */ | 52 | */ |
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h index 6ed4f916b166..43ad4e55878c 100644 --- a/include/asm-arm/spinlock.h +++ b/include/asm-arm/spinlock.h | |||
@@ -30,6 +30,9 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) | |||
30 | __asm__ __volatile__( | 30 | __asm__ __volatile__( |
31 | "1: ldrex %0, [%1]\n" | 31 | "1: ldrex %0, [%1]\n" |
32 | " teq %0, #0\n" | 32 | " teq %0, #0\n" |
33 | #ifdef CONFIG_CPU_32v6K | ||
34 | " wfene\n" | ||
35 | #endif | ||
33 | " strexeq %0, %2, [%1]\n" | 36 | " strexeq %0, %2, [%1]\n" |
34 | " teqeq %0, #0\n" | 37 | " teqeq %0, #0\n" |
35 | " bne 1b" | 38 | " bne 1b" |
@@ -65,7 +68,11 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) | |||
65 | smp_mb(); | 68 | smp_mb(); |
66 | 69 | ||
67 | __asm__ __volatile__( | 70 | __asm__ __volatile__( |
68 | " str %1, [%0]" | 71 | " str %1, [%0]\n" |
72 | #ifdef CONFIG_CPU_32v6K | ||
73 | " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ | ||
74 | " sev" | ||
75 | #endif | ||
69 | : | 76 | : |
70 | : "r" (&lock->lock), "r" (0) | 77 | : "r" (&lock->lock), "r" (0) |
71 | : "cc"); | 78 | : "cc"); |
@@ -87,6 +94,9 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) | |||
87 | __asm__ __volatile__( | 94 | __asm__ __volatile__( |
88 | "1: ldrex %0, [%1]\n" | 95 | "1: ldrex %0, [%1]\n" |
89 | " teq %0, #0\n" | 96 | " teq %0, #0\n" |
97 | #ifdef CONFIG_CPU_32v6K | ||
98 | " wfene\n" | ||
99 | #endif | ||
90 | " strexeq %0, %2, [%1]\n" | 100 | " strexeq %0, %2, [%1]\n" |
91 | " teq %0, #0\n" | 101 | " teq %0, #0\n" |
92 | " bne 1b" | 102 | " bne 1b" |
@@ -122,7 +132,11 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) | |||
122 | smp_mb(); | 132 | smp_mb(); |
123 | 133 | ||
124 | __asm__ __volatile__( | 134 | __asm__ __volatile__( |
125 | "str %1, [%0]" | 135 | "str %1, [%0]\n" |
136 | #ifdef CONFIG_CPU_32v6K | ||
137 | " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ | ||
138 | " sev\n" | ||
139 | #endif | ||
126 | : | 140 | : |
127 | : "r" (&rw->lock), "r" (0) | 141 | : "r" (&rw->lock), "r" (0) |
128 | : "cc"); | 142 | : "cc"); |
@@ -148,6 +162,9 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) | |||
148 | "1: ldrex %0, [%2]\n" | 162 | "1: ldrex %0, [%2]\n" |
149 | " adds %0, %0, #1\n" | 163 | " adds %0, %0, #1\n" |
150 | " strexpl %1, %0, [%2]\n" | 164 | " strexpl %1, %0, [%2]\n" |
165 | #ifdef CONFIG_CPU_32v6K | ||
166 | " wfemi\n" | ||
167 | #endif | ||
151 | " rsbpls %0, %1, #0\n" | 168 | " rsbpls %0, %1, #0\n" |
152 | " bmi 1b" | 169 | " bmi 1b" |
153 | : "=&r" (tmp), "=&r" (tmp2) | 170 | : "=&r" (tmp), "=&r" (tmp2) |
@@ -169,6 +186,11 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) | |||
169 | " strex %1, %0, [%2]\n" | 186 | " strex %1, %0, [%2]\n" |
170 | " teq %1, #0\n" | 187 | " teq %1, #0\n" |
171 | " bne 1b" | 188 | " bne 1b" |
189 | #ifdef CONFIG_CPU_32v6K | ||
190 | "\n cmp %0, #0\n" | ||
191 | " mcreq p15, 0, %0, c7, c10, 4\n" | ||
192 | " seveq" | ||
193 | #endif | ||
172 | : "=&r" (tmp), "=&r" (tmp2) | 194 | : "=&r" (tmp), "=&r" (tmp2) |
173 | : "r" (&rw->lock) | 195 | : "r" (&rw->lock) |
174 | : "cc"); | 196 | : "cc"); |
diff --git a/include/asm-frv/hardirq.h b/include/asm-frv/hardirq.h index 5248ca054909..685123981e8b 100644 --- a/include/asm-frv/hardirq.h +++ b/include/asm-frv/hardirq.h | |||
@@ -14,6 +14,7 @@ | |||
14 | 14 | ||
15 | #include <linux/config.h> | 15 | #include <linux/config.h> |
16 | #include <linux/threads.h> | 16 | #include <linux/threads.h> |
17 | #include <linux/irq.h> | ||
17 | 18 | ||
18 | typedef struct { | 19 | typedef struct { |
19 | unsigned int __softirq_pending; | 20 | unsigned int __softirq_pending; |
diff --git a/include/asm-frv/ide.h b/include/asm-frv/ide.h index f9caecf7e3c0..ae031eaa3dd2 100644 --- a/include/asm-frv/ide.h +++ b/include/asm-frv/ide.h | |||
@@ -33,10 +33,10 @@ | |||
33 | /* | 33 | /* |
34 | * some bits needed for parts of the IDE subsystem to compile | 34 | * some bits needed for parts of the IDE subsystem to compile |
35 | */ | 35 | */ |
36 | #define __ide_mm_insw(port, addr, n) insw(port, addr, n) | 36 | #define __ide_mm_insw(port, addr, n) insw((unsigned long) (port), addr, n) |
37 | #define __ide_mm_insl(port, addr, n) insl(port, addr, n) | 37 | #define __ide_mm_insl(port, addr, n) insl((unsigned long) (port), addr, n) |
38 | #define __ide_mm_outsw(port, addr, n) outsw(port, addr, n) | 38 | #define __ide_mm_outsw(port, addr, n) outsw((unsigned long) (port), addr, n) |
39 | #define __ide_mm_outsl(port, addr, n) outsl(port, addr, n) | 39 | #define __ide_mm_outsl(port, addr, n) outsl((unsigned long) (port), addr, n) |
40 | 40 | ||
41 | 41 | ||
42 | #endif /* __KERNEL__ */ | 42 | #endif /* __KERNEL__ */ |
diff --git a/include/asm-frv/page.h b/include/asm-frv/page.h index 4feba567e7fd..b8221b611b5c 100644 --- a/include/asm-frv/page.h +++ b/include/asm-frv/page.h | |||
@@ -47,8 +47,8 @@ typedef struct { unsigned long pgprot; } pgprot_t; | |||
47 | 47 | ||
48 | #define devmem_is_allowed(pfn) 1 | 48 | #define devmem_is_allowed(pfn) 1 |
49 | 49 | ||
50 | #define __pa(vaddr) virt_to_phys((void *) vaddr) | 50 | #define __pa(vaddr) virt_to_phys((void *) (unsigned long) (vaddr)) |
51 | #define __va(paddr) phys_to_virt((unsigned long) paddr) | 51 | #define __va(paddr) phys_to_virt((unsigned long) (paddr)) |
52 | 52 | ||
53 | #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) | 53 | #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) |
54 | 54 | ||
diff --git a/include/asm-frv/semaphore.h b/include/asm-frv/semaphore.h index b18396288df1..907c5c3643cc 100644 --- a/include/asm-frv/semaphore.h +++ b/include/asm-frv/semaphore.h | |||
@@ -20,7 +20,7 @@ | |||
20 | #include <linux/spinlock.h> | 20 | #include <linux/spinlock.h> |
21 | #include <linux/rwsem.h> | 21 | #include <linux/rwsem.h> |
22 | 22 | ||
23 | #define SEMAPHORE_DEBUG WAITQUEUE_DEBUG | 23 | #define SEMAPHORE_DEBUG 0 |
24 | 24 | ||
25 | /* | 25 | /* |
26 | * the semaphore definition | 26 | * the semaphore definition |
diff --git a/include/asm-frv/thread_info.h b/include/asm-frv/thread_info.h index c8cba7836f0d..60f6b2aee76d 100644 --- a/include/asm-frv/thread_info.h +++ b/include/asm-frv/thread_info.h | |||
@@ -58,7 +58,7 @@ struct thread_info { | |||
58 | 58 | ||
59 | #endif | 59 | #endif |
60 | 60 | ||
61 | #define PREEMPT_ACTIVE 0x4000000 | 61 | #define PREEMPT_ACTIVE 0x10000000 |
62 | 62 | ||
63 | /* | 63 | /* |
64 | * macros/functions for gaining access to the thread information structure | 64 | * macros/functions for gaining access to the thread information structure |
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h index 9dd9da105278..5e6362a786b7 100644 --- a/include/asm-ia64/page.h +++ b/include/asm-ia64/page.h | |||
@@ -110,8 +110,9 @@ extern int ia64_pfn_valid (unsigned long pfn); | |||
110 | # define pfn_to_page(pfn) (mem_map + (pfn)) | 110 | # define pfn_to_page(pfn) (mem_map + (pfn)) |
111 | #elif defined(CONFIG_DISCONTIGMEM) | 111 | #elif defined(CONFIG_DISCONTIGMEM) |
112 | extern struct page *vmem_map; | 112 | extern struct page *vmem_map; |
113 | extern unsigned long min_low_pfn; | ||
113 | extern unsigned long max_low_pfn; | 114 | extern unsigned long max_low_pfn; |
114 | # define pfn_valid(pfn) (((pfn) < max_low_pfn) && ia64_pfn_valid(pfn)) | 115 | # define pfn_valid(pfn) (((pfn) >= min_low_pfn) && ((pfn) < max_low_pfn) && ia64_pfn_valid(pfn)) |
115 | # define page_to_pfn(page) ((unsigned long) (page - vmem_map)) | 116 | # define page_to_pfn(page) ((unsigned long) (page - vmem_map)) |
116 | # define pfn_to_page(pfn) (vmem_map + (pfn)) | 117 | # define pfn_to_page(pfn) (vmem_map + (pfn)) |
117 | #endif | 118 | #endif |
diff --git a/include/asm-m32r/atomic.h b/include/asm-m32r/atomic.h index bfff69a49936..ef1fb8ea4726 100644 --- a/include/asm-m32r/atomic.h +++ b/include/asm-m32r/atomic.h | |||
@@ -242,6 +242,27 @@ static __inline__ int atomic_dec_return(atomic_t *v) | |||
242 | */ | 242 | */ |
243 | #define atomic_add_negative(i,v) (atomic_add_return((i), (v)) < 0) | 243 | #define atomic_add_negative(i,v) (atomic_add_return((i), (v)) < 0) |
244 | 244 | ||
245 | #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) | ||
246 | |||
247 | /** | ||
248 | * atomic_add_unless - add unless the number is a given value | ||
249 | * @v: pointer of type atomic_t | ||
250 | * @a: the amount to add to v... | ||
251 | * @u: ...unless v is equal to u. | ||
252 | * | ||
253 | * Atomically adds @a to @v, so long as it was not @u. | ||
254 | * Returns non-zero if @v was not @u, and zero otherwise. | ||
255 | */ | ||
256 | #define atomic_add_unless(v, a, u) \ | ||
257 | ({ \ | ||
258 | int c, old; \ | ||
259 | c = atomic_read(v); \ | ||
260 | while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \ | ||
261 | c = old; \ | ||
262 | c != (u); \ | ||
263 | }) | ||
264 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) | ||
265 | |||
245 | static __inline__ void atomic_clear_mask(unsigned long mask, atomic_t *addr) | 266 | static __inline__ void atomic_clear_mask(unsigned long mask, atomic_t *addr) |
246 | { | 267 | { |
247 | unsigned long flags; | 268 | unsigned long flags; |
diff --git a/include/asm-m32r/ide.h b/include/asm-m32r/ide.h index 194393bd8beb..f7aa96970d18 100644 --- a/include/asm-m32r/ide.h +++ b/include/asm-m32r/ide.h | |||
@@ -25,18 +25,21 @@ | |||
25 | # endif | 25 | # endif |
26 | #endif | 26 | #endif |
27 | 27 | ||
28 | #if defined(CONFIG_PLAT_M32700UT) | 28 | #include <asm/m32r.h> |
29 | #include <asm/irq.h> | 29 | |
30 | #include <asm/m32700ut/m32700ut_pld.h> | ||
31 | #endif | ||
32 | 30 | ||
33 | #define IDE_ARCH_OBSOLETE_DEFAULTS | 31 | #define IDE_ARCH_OBSOLETE_DEFAULTS |
34 | 32 | ||
35 | static __inline__ int ide_default_irq(unsigned long base) | 33 | static __inline__ int ide_default_irq(unsigned long base) |
36 | { | 34 | { |
37 | switch (base) { | 35 | switch (base) { |
38 | #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) | 36 | #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) |
37 | case 0x1f0: return PLD_IRQ_CFIREQ; | ||
38 | default: | ||
39 | return 0; | ||
40 | #elif defined(CONFIG_PLAT_MAPPI3) | ||
39 | case 0x1f0: return PLD_IRQ_CFIREQ; | 41 | case 0x1f0: return PLD_IRQ_CFIREQ; |
42 | case 0x170: return PLD_IRQ_IDEIREQ; | ||
40 | default: | 43 | default: |
41 | return 0; | 44 | return 0; |
42 | #else | 45 | #else |
diff --git a/include/asm-m32r/mappi3/mappi3_pld.h b/include/asm-m32r/mappi3/mappi3_pld.h index 3f1551f7f01f..1d3c25d61bcb 100644 --- a/include/asm-m32r/mappi3/mappi3_pld.h +++ b/include/asm-m32r/mappi3/mappi3_pld.h | |||
@@ -59,7 +59,7 @@ | |||
59 | #define M32R_IRQ_I2C (28) /* I2C-BUS */ | 59 | #define M32R_IRQ_I2C (28) /* I2C-BUS */ |
60 | #define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */ | 60 | #define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */ |
61 | #define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert */ | 61 | #define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert */ |
62 | #define PLD_IRQ_CFC_EJECT (8) /* INT7 CFC Card Eject */ | 62 | #define PLD_IRQ_IDEIREQ (8) /* INT7 IDE Interrupt */ |
63 | #define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */ | 63 | #define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */ |
64 | #define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */ | 64 | #define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */ |
65 | 65 | ||
diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h index 73348c3f858b..5eee832b73a0 100644 --- a/include/asm-m32r/system.h +++ b/include/asm-m32r/system.h | |||
@@ -11,6 +11,7 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/config.h> | 13 | #include <linux/config.h> |
14 | #include <asm/assembler.h> | ||
14 | 15 | ||
15 | #ifdef __KERNEL__ | 16 | #ifdef __KERNEL__ |
16 | 17 | ||
@@ -132,8 +133,6 @@ static inline void local_irq_disable(void) | |||
132 | !(flags & 0x40); \ | 133 | !(flags & 0x40); \ |
133 | }) | 134 | }) |
134 | 135 | ||
135 | #endif /* __KERNEL__ */ | ||
136 | |||
137 | #define nop() __asm__ __volatile__ ("nop" : : ) | 136 | #define nop() __asm__ __volatile__ ("nop" : : ) |
138 | 137 | ||
139 | #define xchg(ptr,x) \ | 138 | #define xchg(ptr,x) \ |
@@ -213,6 +212,67 @@ static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, | |||
213 | return (tmp); | 212 | return (tmp); |
214 | } | 213 | } |
215 | 214 | ||
215 | #define __HAVE_ARCH_CMPXCHG 1 | ||
216 | |||
217 | static __inline__ unsigned long | ||
218 | __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) | ||
219 | { | ||
220 | unsigned long flags; | ||
221 | unsigned int retval; | ||
222 | |||
223 | local_irq_save(flags); | ||
224 | __asm__ __volatile__ ( | ||
225 | DCACHE_CLEAR("%0", "r4", "%1") | ||
226 | M32R_LOCK" %0, @%1; \n" | ||
227 | " bne %0, %2, 1f; \n" | ||
228 | M32R_UNLOCK" %3, @%1; \n" | ||
229 | " bra 2f; \n" | ||
230 | " .fillinsn \n" | ||
231 | "1:" | ||
232 | M32R_UNLOCK" %2, @%1; \n" | ||
233 | " .fillinsn \n" | ||
234 | "2:" | ||
235 | : "=&r" (retval) | ||
236 | : "r" (p), "r" (old), "r" (new) | ||
237 | : "cbit", "memory" | ||
238 | #ifdef CONFIG_CHIP_M32700_TS1 | ||
239 | , "r4" | ||
240 | #endif /* CONFIG_CHIP_M32700_TS1 */ | ||
241 | ); | ||
242 | local_irq_restore(flags); | ||
243 | |||
244 | return retval; | ||
245 | } | ||
246 | |||
247 | /* This function doesn't exist, so you'll get a linker error | ||
248 | if something tries to do an invalid cmpxchg(). */ | ||
249 | extern void __cmpxchg_called_with_bad_pointer(void); | ||
250 | |||
251 | static __inline__ unsigned long | ||
252 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) | ||
253 | { | ||
254 | switch (size) { | ||
255 | case 4: | ||
256 | return __cmpxchg_u32(ptr, old, new); | ||
257 | #if 0 /* we don't have __cmpxchg_u64 */ | ||
258 | case 8: | ||
259 | return __cmpxchg_u64(ptr, old, new); | ||
260 | #endif /* 0 */ | ||
261 | } | ||
262 | __cmpxchg_called_with_bad_pointer(); | ||
263 | return old; | ||
264 | } | ||
265 | |||
266 | #define cmpxchg(ptr,o,n) \ | ||
267 | ({ \ | ||
268 | __typeof__(*(ptr)) _o_ = (o); \ | ||
269 | __typeof__(*(ptr)) _n_ = (n); \ | ||
270 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | ||
271 | (unsigned long)_n_, sizeof(*(ptr))); \ | ||
272 | }) | ||
273 | |||
274 | #endif /* __KERNEL__ */ | ||
275 | |||
216 | /* | 276 | /* |
217 | * Memory barrier. | 277 | * Memory barrier. |
218 | * | 278 | * |
diff --git a/include/asm-mips/mach-qemu/timex.h b/include/asm-mips/mach-qemu/timex.h new file mode 100644 index 000000000000..cd543693fb0a --- /dev/null +++ b/include/asm-mips/mach-qemu/timex.h | |||
@@ -0,0 +1,16 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2005 Daniel Jacobowitz | ||
7 | */ | ||
8 | #ifndef __ASM_MACH_QEMU_TIMEX_H | ||
9 | #define __ASM_MACH_QEMU_TIMEX_H | ||
10 | |||
11 | /* | ||
12 | * We use a simulated i8254 PIC... | ||
13 | */ | ||
14 | #define CLOCK_TICK_RATE 1193182 | ||
15 | |||
16 | #endif /* __ASM_MACH_QEMU_TIMEX_H */ | ||
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h index 6a35e6570ccd..f89f06050893 100644 --- a/include/asm-powerpc/iommu.h +++ b/include/asm-powerpc/iommu.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | 2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * Rewrite, cleanup: | 3 | * Rewrite, cleanup: |
4 | * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation | 4 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by | 7 | * it under the terms of the GNU General Public License as published by |
diff --git a/include/asm-powerpc/page_64.h b/include/asm-powerpc/page_64.h index 58a3dd9a79ec..6642c0125001 100644 --- a/include/asm-powerpc/page_64.h +++ b/include/asm-powerpc/page_64.h | |||
@@ -103,8 +103,9 @@ extern unsigned int HPAGE_SHIFT; | |||
103 | #define HTLB_AREA_SIZE (1UL << HTLB_AREA_SHIFT) | 103 | #define HTLB_AREA_SIZE (1UL << HTLB_AREA_SHIFT) |
104 | #define GET_HTLB_AREA(x) ((x) >> HTLB_AREA_SHIFT) | 104 | #define GET_HTLB_AREA(x) ((x) >> HTLB_AREA_SHIFT) |
105 | 105 | ||
106 | #define LOW_ESID_MASK(addr, len) (((1U << (GET_ESID(addr+len-1)+1)) \ | 106 | #define LOW_ESID_MASK(addr, len) \ |
107 | - (1U << GET_ESID(addr))) & 0xffff) | 107 | (((1U << (GET_ESID(min((addr)+(len)-1, 0x100000000UL))+1)) \ |
108 | - (1U << GET_ESID(min((addr), 0x100000000UL)))) & 0xffff) | ||
108 | #define HTLB_AREA_MASK(addr, len) (((1U << (GET_HTLB_AREA(addr+len-1)+1)) \ | 109 | #define HTLB_AREA_MASK(addr, len) (((1U << (GET_HTLB_AREA(addr+len-1)+1)) \ |
109 | - (1U << GET_HTLB_AREA(addr))) & 0xffff) | 110 | - (1U << GET_HTLB_AREA(addr))) & 0xffff) |
110 | 111 | ||
@@ -113,17 +114,21 @@ extern unsigned int HPAGE_SHIFT; | |||
113 | #define ARCH_HAS_SETCLEAR_HUGE_PTE | 114 | #define ARCH_HAS_SETCLEAR_HUGE_PTE |
114 | 115 | ||
115 | #define touches_hugepage_low_range(mm, addr, len) \ | 116 | #define touches_hugepage_low_range(mm, addr, len) \ |
116 | (LOW_ESID_MASK((addr), (len)) & (mm)->context.low_htlb_areas) | 117 | (((addr) < 0x100000000UL) \ |
118 | && (LOW_ESID_MASK((addr), (len)) & (mm)->context.low_htlb_areas)) | ||
117 | #define touches_hugepage_high_range(mm, addr, len) \ | 119 | #define touches_hugepage_high_range(mm, addr, len) \ |
118 | (HTLB_AREA_MASK((addr), (len)) & (mm)->context.high_htlb_areas) | 120 | ((((addr) + (len)) > 0x100000000UL) \ |
121 | && (HTLB_AREA_MASK((addr), (len)) & (mm)->context.high_htlb_areas)) | ||
119 | 122 | ||
120 | #define __within_hugepage_low_range(addr, len, segmask) \ | 123 | #define __within_hugepage_low_range(addr, len, segmask) \ |
121 | ((LOW_ESID_MASK((addr), (len)) | (segmask)) == (segmask)) | 124 | ( (((addr)+(len)) <= 0x100000000UL) \ |
125 | && ((LOW_ESID_MASK((addr), (len)) | (segmask)) == (segmask))) | ||
122 | #define within_hugepage_low_range(addr, len) \ | 126 | #define within_hugepage_low_range(addr, len) \ |
123 | __within_hugepage_low_range((addr), (len), \ | 127 | __within_hugepage_low_range((addr), (len), \ |
124 | current->mm->context.low_htlb_areas) | 128 | current->mm->context.low_htlb_areas) |
125 | #define __within_hugepage_high_range(addr, len, zonemask) \ | 129 | #define __within_hugepage_high_range(addr, len, zonemask) \ |
126 | ((HTLB_AREA_MASK((addr), (len)) | (zonemask)) == (zonemask)) | 130 | ( ((addr) >= 0x100000000UL) \ |
131 | && ((HTLB_AREA_MASK((addr), (len)) | (zonemask)) == (zonemask))) | ||
127 | #define within_hugepage_high_range(addr, len) \ | 132 | #define within_hugepage_high_range(addr, len) \ |
128 | __within_hugepage_high_range((addr), (len), \ | 133 | __within_hugepage_high_range((addr), (len), \ |
129 | current->mm->context.high_htlb_areas) | 134 | current->mm->context.high_htlb_areas) |
diff --git a/include/asm-powerpc/tce.h b/include/asm-powerpc/tce.h index d099d5200f9b..980a094fd5a7 100644 --- a/include/asm-powerpc/tce.h +++ b/include/asm-powerpc/tce.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | 2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * Rewrite, cleanup: | 3 | * Rewrite, cleanup: |
4 | * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation | 4 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by | 7 | * it under the terms of the GNU General Public License as published by |
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index 9a02879b235d..f0a9b44d3eb5 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h | |||
@@ -348,16 +348,6 @@ extern unsigned long find_ecache_flush_span(unsigned long size); | |||
348 | struct vm_area_struct; | 348 | struct vm_area_struct; |
349 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); | 349 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); |
350 | 350 | ||
351 | /* Make a non-present pseudo-TTE. */ | ||
352 | static inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space) | ||
353 | { | ||
354 | pte_t pte; | ||
355 | pte_val(pte) = (((page) | pgprot_val(prot) | _PAGE_E) & | ||
356 | ~(unsigned long)_PAGE_CACHE); | ||
357 | pte_val(pte) |= (((unsigned long)space) << 32); | ||
358 | return pte; | ||
359 | } | ||
360 | |||
361 | /* Encode and de-code a swap entry */ | 351 | /* Encode and de-code a swap entry */ |
362 | #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) | 352 | #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) |
363 | #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) | 353 | #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) |
diff --git a/include/linux/atmdev.h b/include/linux/atmdev.h index e7d0593bb576..b203ea82a0a8 100644 --- a/include/linux/atmdev.h +++ b/include/linux/atmdev.h | |||
@@ -7,7 +7,6 @@ | |||
7 | #define LINUX_ATMDEV_H | 7 | #define LINUX_ATMDEV_H |
8 | 8 | ||
9 | 9 | ||
10 | #include <linux/config.h> | ||
11 | #include <linux/atmapi.h> | 10 | #include <linux/atmapi.h> |
12 | #include <linux/atm.h> | 11 | #include <linux/atm.h> |
13 | #include <linux/atmioc.h> | 12 | #include <linux/atmioc.h> |
@@ -210,6 +209,7 @@ struct atm_cirange { | |||
210 | 209 | ||
211 | #ifdef __KERNEL__ | 210 | #ifdef __KERNEL__ |
212 | 211 | ||
212 | #include <linux/config.h> | ||
213 | #include <linux/wait.h> /* wait_queue_head_t */ | 213 | #include <linux/wait.h> /* wait_queue_head_t */ |
214 | #include <linux/time.h> /* struct timeval */ | 214 | #include <linux/time.h> /* struct timeval */ |
215 | #include <linux/net.h> | 215 | #include <linux/net.h> |
@@ -274,7 +274,7 @@ enum { | |||
274 | 274 | ||
275 | 275 | ||
276 | enum { | 276 | enum { |
277 | ATM_DF_CLOSE, /* close device when last VCC is closed */ | 277 | ATM_DF_REMOVED, /* device was removed from atm_devs list */ |
278 | }; | 278 | }; |
279 | 279 | ||
280 | 280 | ||
@@ -415,7 +415,6 @@ struct atm_dev *atm_dev_register(const char *type,const struct atmdev_ops *ops, | |||
415 | int number,unsigned long *flags); /* number == -1: pick first available */ | 415 | int number,unsigned long *flags); /* number == -1: pick first available */ |
416 | struct atm_dev *atm_dev_lookup(int number); | 416 | struct atm_dev *atm_dev_lookup(int number); |
417 | void atm_dev_deregister(struct atm_dev *dev); | 417 | void atm_dev_deregister(struct atm_dev *dev); |
418 | void shutdown_atm_dev(struct atm_dev *dev); | ||
419 | void vcc_insert_socket(struct sock *sk); | 418 | void vcc_insert_socket(struct sock *sk); |
420 | 419 | ||
421 | 420 | ||
@@ -457,18 +456,19 @@ static inline void atm_dev_hold(struct atm_dev *dev) | |||
457 | 456 | ||
458 | static inline void atm_dev_put(struct atm_dev *dev) | 457 | static inline void atm_dev_put(struct atm_dev *dev) |
459 | { | 458 | { |
460 | atomic_dec(&dev->refcnt); | 459 | if (atomic_dec_and_test(&dev->refcnt)) { |
461 | 460 | BUG_ON(!test_bit(ATM_DF_REMOVED, &dev->flags)); | |
462 | if ((atomic_read(&dev->refcnt) == 1) && | 461 | if (dev->ops->dev_close) |
463 | test_bit(ATM_DF_CLOSE,&dev->flags)) | 462 | dev->ops->dev_close(dev); |
464 | shutdown_atm_dev(dev); | 463 | kfree(dev); |
464 | } | ||
465 | } | 465 | } |
466 | 466 | ||
467 | 467 | ||
468 | int atm_charge(struct atm_vcc *vcc,int truesize); | 468 | int atm_charge(struct atm_vcc *vcc,int truesize); |
469 | struct sk_buff *atm_alloc_charge(struct atm_vcc *vcc,int pdu_size, | 469 | struct sk_buff *atm_alloc_charge(struct atm_vcc *vcc,int pdu_size, |
470 | gfp_t gfp_flags); | 470 | gfp_t gfp_flags); |
471 | int atm_pcr_goal(struct atm_trafprm *tp); | 471 | int atm_pcr_goal(const struct atm_trafprm *tp); |
472 | 472 | ||
473 | void vcc_release_async(struct atm_vcc *vcc, int reply); | 473 | void vcc_release_async(struct atm_vcc *vcc, int reply); |
474 | 474 | ||
diff --git a/include/linux/cn_proc.h b/include/linux/cn_proc.h index 70ab56317380..c948f678e04e 100644 --- a/include/linux/cn_proc.h +++ b/include/linux/cn_proc.h | |||
@@ -86,12 +86,12 @@ struct proc_event { | |||
86 | pid_t process_pid; | 86 | pid_t process_pid; |
87 | pid_t process_tgid; | 87 | pid_t process_tgid; |
88 | union { | 88 | union { |
89 | uid_t ruid; /* current->uid */ | 89 | __u32 ruid; /* task uid */ |
90 | gid_t rgid; /* current->gid */ | 90 | __u32 rgid; /* task gid */ |
91 | } r; | 91 | } r; |
92 | union { | 92 | union { |
93 | uid_t euid; | 93 | __u32 euid; |
94 | gid_t egid; | 94 | __u32 egid; |
95 | } e; | 95 | } e; |
96 | } id; | 96 | } id; |
97 | 97 | ||
diff --git a/include/linux/cpu.h b/include/linux/cpu.h index 43c44530ef9d..0ed1d4853c69 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h | |||
@@ -65,10 +65,9 @@ extern struct sysdev_class cpu_sysdev_class; | |||
65 | 65 | ||
66 | #ifdef CONFIG_HOTPLUG_CPU | 66 | #ifdef CONFIG_HOTPLUG_CPU |
67 | /* Stop CPUs going up and down. */ | 67 | /* Stop CPUs going up and down. */ |
68 | extern struct semaphore cpucontrol; | 68 | extern void lock_cpu_hotplug(void); |
69 | #define lock_cpu_hotplug() down(&cpucontrol) | 69 | extern void unlock_cpu_hotplug(void); |
70 | #define unlock_cpu_hotplug() up(&cpucontrol) | 70 | extern int lock_cpu_hotplug_interruptible(void); |
71 | #define lock_cpu_hotplug_interruptible() down_interruptible(&cpucontrol) | ||
72 | #define hotcpu_notifier(fn, pri) { \ | 71 | #define hotcpu_notifier(fn, pri) { \ |
73 | static struct notifier_block fn##_nb = \ | 72 | static struct notifier_block fn##_nb = \ |
74 | { .notifier_call = fn, .priority = pri }; \ | 73 | { .notifier_call = fn, .priority = pri }; \ |
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h index 1543daaa9c5e..ef3b5632e63a 100644 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h | |||
@@ -108,6 +108,7 @@ | |||
108 | #define I2C_DRIVERID_SAA7127 72 /* saa7124 video encoder */ | 108 | #define I2C_DRIVERID_SAA7127 72 /* saa7124 video encoder */ |
109 | #define I2C_DRIVERID_SAA711X 73 /* saa711x video encoders */ | 109 | #define I2C_DRIVERID_SAA711X 73 /* saa711x video encoders */ |
110 | #define I2C_DRIVERID_AKITAIOEXP 74 /* IO Expander on Sharp SL-C1000 */ | 110 | #define I2C_DRIVERID_AKITAIOEXP 74 /* IO Expander on Sharp SL-C1000 */ |
111 | #define I2C_DRIVERID_I2C_IR 75 /* I2C InfraRed on Video boards */ | ||
111 | 112 | ||
112 | #define I2C_DRIVERID_EXP0 0xF0 /* experimental use id's */ | 113 | #define I2C_DRIVERID_EXP0 0xF0 /* experimental use id's */ |
113 | #define I2C_DRIVERID_EXP1 0xF1 | 114 | #define I2C_DRIVERID_EXP1 0xF1 |
diff --git a/include/linux/memory.h b/include/linux/memory.h index 9a424383e6c6..dc4081b6f161 100644 --- a/include/linux/memory.h +++ b/include/linux/memory.h | |||
@@ -85,7 +85,6 @@ struct notifier_block; | |||
85 | extern int register_memory_notifier(struct notifier_block *nb); | 85 | extern int register_memory_notifier(struct notifier_block *nb); |
86 | extern void unregister_memory_notifier(struct notifier_block *nb); | 86 | extern void unregister_memory_notifier(struct notifier_block *nb); |
87 | 87 | ||
88 | extern struct sysdev_class memory_sysdev_class; | ||
89 | #endif /* CONFIG_MEMORY_HOTPLUG */ | 88 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
90 | 89 | ||
91 | #define hotplug_memory_notifier(fn, pri) { \ | 90 | #define hotplug_memory_notifier(fn, pri) { \ |
diff --git a/include/linux/mm.h b/include/linux/mm.h index f0cdfd18db55..29f02d8513f6 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h | |||
@@ -145,7 +145,7 @@ extern unsigned int kobjsize(const void *objp); | |||
145 | #define VM_GROWSDOWN 0x00000100 /* general info on the segment */ | 145 | #define VM_GROWSDOWN 0x00000100 /* general info on the segment */ |
146 | #define VM_GROWSUP 0x00000200 | 146 | #define VM_GROWSUP 0x00000200 |
147 | #define VM_SHM 0x00000000 /* Means nothing: delete it later */ | 147 | #define VM_SHM 0x00000000 /* Means nothing: delete it later */ |
148 | #define VM_UNPAGED 0x00000400 /* Pages managed without map count */ | 148 | #define VM_PFNMAP 0x00000400 /* Page-ranges managed without "struct page", just pure PFN */ |
149 | #define VM_DENYWRITE 0x00000800 /* ETXTBSY on write attempts.. */ | 149 | #define VM_DENYWRITE 0x00000800 /* ETXTBSY on write attempts.. */ |
150 | 150 | ||
151 | #define VM_EXECUTABLE 0x00001000 | 151 | #define VM_EXECUTABLE 0x00001000 |
@@ -163,6 +163,7 @@ extern unsigned int kobjsize(const void *objp); | |||
163 | #define VM_HUGETLB 0x00400000 /* Huge TLB Page VM */ | 163 | #define VM_HUGETLB 0x00400000 /* Huge TLB Page VM */ |
164 | #define VM_NONLINEAR 0x00800000 /* Is non-linear (remap_file_pages) */ | 164 | #define VM_NONLINEAR 0x00800000 /* Is non-linear (remap_file_pages) */ |
165 | #define VM_MAPPED_COPY 0x01000000 /* T if mapped copy of data (nommu mmap) */ | 165 | #define VM_MAPPED_COPY 0x01000000 /* T if mapped copy of data (nommu mmap) */ |
166 | #define VM_INCOMPLETE 0x02000000 /* Strange partial PFN mapping marker */ | ||
166 | 167 | ||
167 | #ifndef VM_STACK_DEFAULT_FLAGS /* arch can override this */ | 168 | #ifndef VM_STACK_DEFAULT_FLAGS /* arch can override this */ |
168 | #define VM_STACK_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS | 169 | #define VM_STACK_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS |
@@ -664,6 +665,7 @@ struct zap_details { | |||
664 | unsigned long truncate_count; /* Compare vm_truncate_count */ | 665 | unsigned long truncate_count; /* Compare vm_truncate_count */ |
665 | }; | 666 | }; |
666 | 667 | ||
668 | struct page *vm_normal_page(struct vm_area_struct *, unsigned long, pte_t); | ||
667 | unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address, | 669 | unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address, |
668 | unsigned long size, struct zap_details *); | 670 | unsigned long size, struct zap_details *); |
669 | unsigned long unmap_vmas(struct mmu_gather **tlb, | 671 | unsigned long unmap_vmas(struct mmu_gather **tlb, |
@@ -740,6 +742,8 @@ struct shrinker; | |||
740 | extern struct shrinker *set_shrinker(int, shrinker_t); | 742 | extern struct shrinker *set_shrinker(int, shrinker_t); |
741 | extern void remove_shrinker(struct shrinker *shrinker); | 743 | extern void remove_shrinker(struct shrinker *shrinker); |
742 | 744 | ||
745 | extern pte_t *FASTCALL(get_locked_pte(struct mm_struct *mm, unsigned long addr, spinlock_t **ptl)); | ||
746 | |||
743 | int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address); | 747 | int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address); |
744 | int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address); | 748 | int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address); |
745 | int __pte_alloc(struct mm_struct *mm, pmd_t *pmd, unsigned long address); | 749 | int __pte_alloc(struct mm_struct *mm, pmd_t *pmd, unsigned long address); |
@@ -952,8 +956,9 @@ struct page *vmalloc_to_page(void *addr); | |||
952 | unsigned long vmalloc_to_pfn(void *addr); | 956 | unsigned long vmalloc_to_pfn(void *addr); |
953 | int remap_pfn_range(struct vm_area_struct *, unsigned long addr, | 957 | int remap_pfn_range(struct vm_area_struct *, unsigned long addr, |
954 | unsigned long pfn, unsigned long size, pgprot_t); | 958 | unsigned long pfn, unsigned long size, pgprot_t); |
959 | int vm_insert_page(struct vm_area_struct *, unsigned long addr, struct page *); | ||
955 | 960 | ||
956 | struct page *follow_page(struct mm_struct *, unsigned long address, | 961 | struct page *follow_page(struct vm_area_struct *, unsigned long address, |
957 | unsigned int foll_flags); | 962 | unsigned int foll_flags); |
958 | #define FOLL_WRITE 0x01 /* check pte is writable */ | 963 | #define FOLL_WRITE 0x01 /* check pte is writable */ |
959 | #define FOLL_TOUCH 0x02 /* mark page accessed */ | 964 | #define FOLL_TOUCH 0x02 /* mark page accessed */ |
diff --git a/include/linux/mmc/protocol.h b/include/linux/mmc/protocol.h index f819cae92266..a14dc306545b 100644 --- a/include/linux/mmc/protocol.h +++ b/include/linux/mmc/protocol.h | |||
@@ -63,7 +63,7 @@ | |||
63 | /* class 5 */ | 63 | /* class 5 */ |
64 | #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ | 64 | #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ |
65 | #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ | 65 | #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ |
66 | #define MMC_ERASE 37 /* ac R1b */ | 66 | #define MMC_ERASE 38 /* ac R1b */ |
67 | 67 | ||
68 | /* class 9 */ | 68 | /* class 9 */ |
69 | #define MMC_FAST_IO 39 /* ac <Complex> R4 */ | 69 | #define MMC_FAST_IO 39 /* ac <Complex> R4 */ |
@@ -74,7 +74,7 @@ | |||
74 | 74 | ||
75 | /* class 8 */ | 75 | /* class 8 */ |
76 | #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ | 76 | #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ |
77 | #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */ | 77 | #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ |
78 | 78 | ||
79 | /* SD commands type argument response */ | 79 | /* SD commands type argument response */ |
80 | /* class 8 */ | 80 | /* class 8 */ |
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index 3c9ea4b7adda..23a568910341 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h | |||
@@ -1,7 +1,7 @@ | |||
1 | 1 | ||
2 | /* Common Flash Interface structures | 2 | /* Common Flash Interface structures |
3 | * See http://support.intel.com/design/flash/technote/index.htm | 3 | * See http://support.intel.com/design/flash/technote/index.htm |
4 | * $Id: cfi.h,v 1.56 2005/11/07 11:14:54 gleixner Exp $ | 4 | * $Id: cfi.h,v 1.57 2005/11/15 23:28:17 tpoynor Exp $ |
5 | */ | 5 | */ |
6 | 6 | ||
7 | #ifndef __MTD_CFI_H__ | 7 | #ifndef __MTD_CFI_H__ |
@@ -426,6 +426,22 @@ static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr) | |||
426 | } | 426 | } |
427 | } | 427 | } |
428 | 428 | ||
429 | static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr) | ||
430 | { | ||
431 | map_word val = map_read(map, addr); | ||
432 | |||
433 | if (map_bankwidth_is_1(map)) { | ||
434 | return val.x[0] & 0xff; | ||
435 | } else if (map_bankwidth_is_2(map)) { | ||
436 | return cfi16_to_cpu(val.x[0]); | ||
437 | } else { | ||
438 | /* No point in a 64-bit byteswap since that would just be | ||
439 | swapping the responses from different chips, and we are | ||
440 | only interested in one chip (a representative sample) */ | ||
441 | return cfi32_to_cpu(val.x[0]); | ||
442 | } | ||
443 | } | ||
444 | |||
429 | static inline void cfi_udelay(int us) | 445 | static inline void cfi_udelay(int us) |
430 | { | 446 | { |
431 | if (us >= 1000) { | 447 | if (us >= 1000) { |
diff --git a/include/linux/rmap.h b/include/linux/rmap.h index 35b30e6c8cf8..33261f1d2239 100644 --- a/include/linux/rmap.h +++ b/include/linux/rmap.h | |||
@@ -89,7 +89,7 @@ static inline void page_dup_rmap(struct page *page) | |||
89 | /* | 89 | /* |
90 | * Called from mm/vmscan.c to handle paging out | 90 | * Called from mm/vmscan.c to handle paging out |
91 | */ | 91 | */ |
92 | int page_referenced(struct page *, int is_locked, int ignore_token); | 92 | int page_referenced(struct page *, int is_locked); |
93 | int try_to_unmap(struct page *); | 93 | int try_to_unmap(struct page *); |
94 | 94 | ||
95 | /* | 95 | /* |
@@ -109,7 +109,7 @@ unsigned long page_address_in_vma(struct page *, struct vm_area_struct *); | |||
109 | #define anon_vma_prepare(vma) (0) | 109 | #define anon_vma_prepare(vma) (0) |
110 | #define anon_vma_link(vma) do {} while (0) | 110 | #define anon_vma_link(vma) do {} while (0) |
111 | 111 | ||
112 | #define page_referenced(page,l,i) TestClearPageReferenced(page) | 112 | #define page_referenced(page,l) TestClearPageReferenced(page) |
113 | #define try_to_unmap(page) SWAP_FAIL | 113 | #define try_to_unmap(page) SWAP_FAIL |
114 | 114 | ||
115 | #endif /* CONFIG_MMU */ | 115 | #endif /* CONFIG_MMU */ |
diff --git a/include/linux/sched.h b/include/linux/sched.h index 2038bd27b041..b0ad6f30679e 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h | |||
@@ -908,7 +908,6 @@ do { if (atomic_dec_and_test(&(tsk)->usage)) __put_task_struct(tsk); } while(0) | |||
908 | #define PF_SYNCWRITE 0x00200000 /* I am doing a sync write */ | 908 | #define PF_SYNCWRITE 0x00200000 /* I am doing a sync write */ |
909 | #define PF_BORROWED_MM 0x00400000 /* I am a kthread doing use_mm */ | 909 | #define PF_BORROWED_MM 0x00400000 /* I am a kthread doing use_mm */ |
910 | #define PF_RANDOMIZE 0x00800000 /* randomize virtual address space */ | 910 | #define PF_RANDOMIZE 0x00800000 /* randomize virtual address space */ |
911 | #define PF_HOTPLUG_CPU 0x01000000 /* Currently performing CPU hotplug */ | ||
912 | 911 | ||
913 | /* | 912 | /* |
914 | * Only the _current_ task can read/write to tsk->flags, but other | 913 | * Only the _current_ task can read/write to tsk->flags, but other |
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index a3ac92b19aca..e3710d7e260a 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h | |||
@@ -121,6 +121,9 @@ | |||
121 | 121 | ||
122 | #define PORT_IP3106 70 | 122 | #define PORT_IP3106 70 |
123 | 123 | ||
124 | /* Hilscher netx */ | ||
125 | #define PORT_NETX 71 | ||
126 | |||
124 | #ifdef __KERNEL__ | 127 | #ifdef __KERNEL__ |
125 | 128 | ||
126 | #include <linux/config.h> | 129 | #include <linux/config.h> |
diff --git a/include/linux/swap.h b/include/linux/swap.h index 20c975642cab..508668f840b6 100644 --- a/include/linux/swap.h +++ b/include/linux/swap.h | |||
@@ -239,6 +239,11 @@ static inline void put_swap_token(struct mm_struct *mm) | |||
239 | __put_swap_token(mm); | 239 | __put_swap_token(mm); |
240 | } | 240 | } |
241 | 241 | ||
242 | static inline void disable_swap_token(void) | ||
243 | { | ||
244 | put_swap_token(swap_token_mm); | ||
245 | } | ||
246 | |||
242 | #else /* CONFIG_SWAP */ | 247 | #else /* CONFIG_SWAP */ |
243 | 248 | ||
244 | #define total_swap_pages 0 | 249 | #define total_swap_pages 0 |
@@ -283,6 +288,7 @@ static inline swp_entry_t get_swap_page(void) | |||
283 | #define put_swap_token(x) do { } while(0) | 288 | #define put_swap_token(x) do { } while(0) |
284 | #define grab_swap_token() do { } while(0) | 289 | #define grab_swap_token() do { } while(0) |
285 | #define has_swap_token(x) 0 | 290 | #define has_swap_token(x) 0 |
291 | #define disable_swap_token() do { } while(0) | ||
286 | 292 | ||
287 | #endif /* CONFIG_SWAP */ | 293 | #endif /* CONFIG_SWAP */ |
288 | #endif /* __KERNEL__*/ | 294 | #endif /* __KERNEL__*/ |
diff --git a/include/media/tveeprom.h b/include/media/tveeprom.h index e2035c7da094..e9fc1a785497 100644 --- a/include/media/tveeprom.h +++ b/include/media/tveeprom.h | |||
@@ -4,12 +4,15 @@ | |||
4 | struct tveeprom { | 4 | struct tveeprom { |
5 | u32 has_radio; | 5 | u32 has_radio; |
6 | u32 has_ir; /* 0: no IR, 1: IR present, 2: unknown */ | 6 | u32 has_ir; /* 0: no IR, 1: IR present, 2: unknown */ |
7 | u32 has_MAC_address; /* 0: no MAC, 1: MAC present, 2: unknown */ | ||
7 | 8 | ||
8 | u32 tuner_type; | 9 | u32 tuner_type; |
9 | u32 tuner_formats; | 10 | u32 tuner_formats; |
11 | u32 tuner_hauppauge_model; | ||
10 | 12 | ||
11 | u32 tuner2_type; | 13 | u32 tuner2_type; |
12 | u32 tuner2_formats; | 14 | u32 tuner2_formats; |
15 | u32 tuner2_hauppauge_model; | ||
13 | 16 | ||
14 | u32 digitizer; | 17 | u32 digitizer; |
15 | u32 digitizer_formats; | 18 | u32 digitizer_formats; |
@@ -21,6 +24,7 @@ struct tveeprom { | |||
21 | u32 revision; | 24 | u32 revision; |
22 | u32 serial_number; | 25 | u32 serial_number; |
23 | char rev_str[5]; | 26 | char rev_str[5]; |
27 | u8 MAC_address[6]; | ||
24 | }; | 28 | }; |
25 | 29 | ||
26 | void tveeprom_hauppauge_analog(struct i2c_client *c, struct tveeprom *tvee, | 30 | void tveeprom_hauppauge_analog(struct i2c_client *c, struct tveeprom *tvee, |