4 files changed, 58 insertions, 0 deletions

diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 12f9d7139ebf..94fc9be1aab6 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -213,6 +213,18 @@
 #define MACH_GROUP_LEMOTE          27
 #define  MACH_LEMOTE_FULONG        0
 
+/*
+ * Valid machtype for group PMC-MSP
+ */
+#define MACH_GROUP_MSP         26       /* PMC-Sierra MSP boards/CPUs    */
+#define MACH_MSP4200_EVAL       0       /* PMC-Sierra MSP4200 Evaluation */
+#define MACH_MSP4200_GW         1       /* PMC-Sierra MSP4200 Gateway demo */
+#define MACH_MSP4200_FPGA       2       /* PMC-Sierra MSP4200 Emulation */
+#define MACH_MSP7120_EVAL       3       /* PMC-Sierra MSP7120 Evaluation */
+#define MACH_MSP7120_GW         4       /* PMC-Sierra MSP7120 Residential GW */
+#define MACH_MSP7120_FPGA       5       /* PMC-Sierra MSP7120 Emulation */
+#define MACH_MSP_OTHER        255       /* PMC-Sierra unknown board type */
+
 #define CL_SIZE                 COMMAND_LINE_SIZE
 
 const char *get_system_type(void);
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index a3623954dad1..3857358fb6de 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -109,6 +109,7 @@
  * Definitions for 7:0 on legacy processors
  */
 
+#define PRID_REV_MASK           0x00ff
 
 #define PRID_REV_TX4927         0x0022
 #define PRID_REV_TX4937         0x0030
@@ -125,6 +126,7 @@
 #define PRID_REV_VR4122         0x0070
 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 #define PRID_REV_VR4130         0x0080
+#define PRID_REV_34K_V1_0_2     0x0022
 
 /*
  * Older processors used to encode processor version and revision in two
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 668db02c2804..706b3691f57e 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -15,6 +15,7 @@
 
 #include <linux/linkage.h>
 #include <asm/hazards.h>
+#include <asm/war.h>
 
 /*
  * The following macros are especially useful for __asm__
@@ -537,6 +538,9 @@
 
 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 
+#define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
+
+
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  */
@@ -1298,10 +1302,39 @@ static inline void tlb_probe(void)
 
 static inline void tlb_read(void)
 {
+#if MIPS34K_MISSED_ITLB_WAR
+        int res = 0;
+
+        __asm__ __volatile__(
+        "       .set    push                                    \n"
+        "       .set    noreorder                               \n"
+        "       .set    noat                                    \n"
+        "       .set    mips32r2                                \n"
+        "       .word   0x41610001              # dvpe $1       \n"
+        "       move    %0, $1                                  \n"
+        "       ehb                                             \n"
+        "       .set    pop                                     \n"
+        : "=r" (res));
+
+        instruction_hazard();
+#endif
+
         __asm__ __volatile__(
                 ".set noreorder\n\t"
                 "tlbr\n\t"
                 ".set reorder");
+
+#if MIPS34K_MISSED_ITLB_WAR
+        if ((res & _ULCAST_(1)))
+                __asm__ __volatile__(
+                "       .set    push                            \n"
+                "       .set    noreorder                       \n"
+                "       .set    noat                            \n"
+                "       .set    mips32r2                        \n"
+                "       .word   0x41600021      # evpe          \n"
+                "       ehb                                     \n"
+                "       .set    pop                             \n");
+#endif
 }
 
 static inline void tlb_write_indexed(void)
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index c507f1b8014e..45cb82724830 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -198,6 +198,14 @@
 #endif
 
 /*
+ * 34K core erratum: "Problems Executing the TLBR Instruction"
+ */
+#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
+        defined(CONFIG_PMC_MSP7120_FPGA)
+#define MIPS34K_MISSED_ITLB_WAR         1
+#endif
+
+/*
  * Workarounds default to off
  */
 #ifndef ICACHE_REFILLS_WORKAROUND_WAR
@@ -236,5 +244,8 @@
 #ifndef R10000_LLSC_WAR
 #define R10000_LLSC_WAR                 0
 #endif
+#ifndef MIPS34K_MISSED_ITLB_WAR
+#define MIPS34K_MISSED_ITLB_WAR         0
+#endif
 
 #endif /* _ASM_WAR_H */