aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/8xx_immap.h2
-rw-r--r--include/asm-powerpc/commproc.h2
-rw-r--r--include/asm-powerpc/cpm.h1
-rw-r--r--include/asm-powerpc/cputhreads.h71
-rw-r--r--include/asm-powerpc/dma-mapping.h3
-rw-r--r--include/asm-powerpc/firmware.h2
-rw-r--r--include/asm-powerpc/immap_86xx.h25
-rw-r--r--include/asm-powerpc/io.h5
-rw-r--r--include/asm-powerpc/iommu.h3
-rw-r--r--include/asm-powerpc/ipic.h12
-rw-r--r--include/asm-powerpc/iseries/hv_lp_event.h2
-rw-r--r--include/asm-powerpc/machdep.h58
-rw-r--r--include/asm-powerpc/mmu-hash64.h1
-rw-r--r--include/asm-powerpc/nvram.h11
-rw-r--r--include/asm-powerpc/of_platform.h12
-rw-r--r--include/asm-powerpc/pci-bridge.h191
-rw-r--r--include/asm-powerpc/pci.h29
-rw-r--r--include/asm-powerpc/ppc-pci.h4
-rw-r--r--include/asm-powerpc/prom.h4
-rw-r--r--include/asm-powerpc/qe.h95
-rw-r--r--include/asm-powerpc/reg.h6
-rw-r--r--include/asm-powerpc/reg_booke.h15
-rw-r--r--include/asm-powerpc/smu.h142
-rw-r--r--include/asm-powerpc/spu.h28
-rw-r--r--include/asm-powerpc/spu_csa.h13
-rw-r--r--include/asm-powerpc/spu_priv1.h15
-rw-r--r--include/asm-ppc/8xx_immap.h2
-rw-r--r--include/asm-ppc/commproc.h2
-rw-r--r--include/asm-ppc/reg_booke.h2
-rw-r--r--include/linux/of.h4
-rw-r--r--include/linux/pmu.h36
31 files changed, 533 insertions, 265 deletions
diff --git a/include/asm-powerpc/8xx_immap.h b/include/asm-powerpc/8xx_immap.h
index 1311cefdfd30..4b0e15206006 100644
--- a/include/asm-powerpc/8xx_immap.h
+++ b/include/asm-powerpc/8xx_immap.h
@@ -123,7 +123,7 @@ typedef struct mem_ctlr {
123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ 123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ 124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125#define OR_BI 0x00000100 /* Burst inhibit */ 125#define OR_BI 0x00000100 /* Burst inhibit */
126#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ 126#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ 127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ 128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ 129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
diff --git a/include/asm-powerpc/commproc.h b/include/asm-powerpc/commproc.h
index 2ee59d7b335c..9e3b8648648c 100644
--- a/include/asm-powerpc/commproc.h
+++ b/include/asm-powerpc/commproc.h
@@ -693,7 +693,7 @@ typedef struct risc_timer_pram {
693#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 693#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
694#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 694#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
695#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 695#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
696#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 696#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
697#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 697#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
698#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 698#define CICR_IEN ((uint)0x00000080) /* Int. enable */
699#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 699#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h
index 48df9f330e76..fae83b137337 100644
--- a/include/asm-powerpc/cpm.h
+++ b/include/asm-powerpc/cpm.h
@@ -10,5 +10,6 @@ int cpm_muram_free(unsigned long offset);
10unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); 10unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
11void __iomem *cpm_muram_addr(unsigned long offset); 11void __iomem *cpm_muram_addr(unsigned long offset);
12dma_addr_t cpm_muram_dma(void __iomem *addr); 12dma_addr_t cpm_muram_dma(void __iomem *addr);
13int cpm_command(u32 command, u8 opcode);
13 14
14#endif 15#endif
diff --git a/include/asm-powerpc/cputhreads.h b/include/asm-powerpc/cputhreads.h
new file mode 100644
index 000000000000..8485c28b5f47
--- /dev/null
+++ b/include/asm-powerpc/cputhreads.h
@@ -0,0 +1,71 @@
1#ifndef _ASM_POWERPC_CPUTHREADS_H
2#define _ASM_POWERPC_CPUTHREADS_H
3
4#include <linux/cpumask.h>
5
6/*
7 * Mapping of threads to cores
8 */
9
10#ifdef CONFIG_SMP
11extern int threads_per_core;
12extern int threads_shift;
13extern cpumask_t threads_core_mask;
14#else
15#define threads_per_core 1
16#define threads_shift 0
17#define threads_core_mask (CPU_MASK_CPU0)
18#endif
19
20/* cpu_thread_mask_to_cores - Return a cpumask of one per cores
21 * hit by the argument
22 *
23 * @threads: a cpumask of threads
24 *
25 * This function returns a cpumask which will have one "cpu" (or thread)
26 * bit set for each core that has at least one thread set in the argument.
27 *
28 * This can typically be used for things like IPI for tlb invalidations
29 * since those need to be done only once per core/TLB
30 */
31static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
32{
33 cpumask_t tmp, res;
34 int i;
35
36 res = CPU_MASK_NONE;
37 for (i = 0; i < NR_CPUS; i += threads_per_core) {
38 cpus_shift_right(tmp, threads_core_mask, i);
39 if (cpus_intersects(threads, tmp))
40 cpu_set(i, res);
41 }
42 return res;
43}
44
45static inline int cpu_nr_cores(void)
46{
47 return NR_CPUS >> threads_shift;
48}
49
50static inline cpumask_t cpu_online_cores_map(void)
51{
52 return cpu_thread_mask_to_cores(cpu_online_map);
53}
54
55static inline int cpu_thread_to_core(int cpu)
56{
57 return cpu >> threads_shift;
58}
59
60static inline int cpu_thread_in_core(int cpu)
61{
62 return cpu & (threads_per_core - 1);
63}
64
65static inline int cpu_first_thread_in_core(int cpu)
66{
67 return cpu & ~(threads_per_core - 1);
68}
69
70#endif /* _ASM_POWERPC_CPUTHREADS_H */
71
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index ff52013c0e2d..e974876e18d2 100644
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -87,6 +87,9 @@ static inline int dma_supported(struct device *dev, u64 mask)
87 return dma_ops->dma_supported(dev, mask); 87 return dma_ops->dma_supported(dev, mask);
88} 88}
89 89
90/* We have our own implementation of pci_set_dma_mask() */
91#define HAVE_ARCH_PCI_SET_DMA_MASK
92
90static inline int dma_set_mask(struct device *dev, u64 dma_mask) 93static inline int dma_set_mask(struct device *dev, u64 dma_mask)
91{ 94{
92 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 95 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h
index 3671c128f271..1e41bd1c8502 100644
--- a/include/asm-powerpc/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -64,7 +64,7 @@ enum {
64 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 64 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
65 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 65 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
66 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT, 66 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
67 FW_FEATURE_CELLEB_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_BEAT, 67 FW_FEATURE_CELLEB_ALWAYS = 0,
68 FW_FEATURE_NATIVE_POSSIBLE = 0, 68 FW_FEATURE_NATIVE_POSSIBLE = 0,
69 FW_FEATURE_NATIVE_ALWAYS = 0, 69 FW_FEATURE_NATIVE_ALWAYS = 0,
70 FW_FEATURE_POSSIBLE = 70 FW_FEATURE_POSSIBLE =
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
index 0ad4e653d464..0f165e59c326 100644
--- a/include/asm-powerpc/immap_86xx.h
+++ b/include/asm-powerpc/immap_86xx.h
@@ -89,14 +89,14 @@ struct ccsr_guts {
89 * them. 89 * them.
90 * 90 *
91 * guts: Pointer to GUTS structure 91 * guts: Pointer to GUTS structure
92 * co: The DMA controller (1 or 2) 92 * co: The DMA controller (0 or 1)
93 * ch: The channel on the DMA controller (0, 1, 2, or 3) 93 * ch: The channel on the DMA controller (0, 1, 2, or 3)
94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) 94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
95 */ 95 */
96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, 96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
97 unsigned int co, unsigned int ch, unsigned int device) 97 unsigned int co, unsigned int ch, unsigned int device)
98{ 98{
99 unsigned int shift = 16 + (8 * (2 - co) + 2 * (3 - ch)); 99 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
100 100
101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); 101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
102} 102}
@@ -118,6 +118,27 @@ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
120 120
121/*
122 * Set the DMA external control bits in the GUTS
123 *
124 * The DMA external control bits in the PMUXCR are only meaningful for
125 * channels 0 and 3. Any other channels are ignored.
126 *
127 * guts: Pointer to GUTS structure
128 * co: The DMA controller (0 or 1)
129 * ch: The channel on the DMA controller (0, 1, 2, or 3)
130 * value: the new value for the bit (0 or 1)
131 */
132static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
133 unsigned int co, unsigned int ch, unsigned int value)
134{
135 if ((ch == 0) || (ch == 3)) {
136 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
137
138 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
139 }
140}
141
121#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 142#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
122#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 143#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
123#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 144#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index e44cdfc8493a..7be26f615755 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -50,15 +50,16 @@ extern int check_legacy_ioport(unsigned long base_port);
50#define PCI_DRAM_OFFSET pci_dram_offset 50#define PCI_DRAM_OFFSET pci_dram_offset
51#else 51#else
52#define _IO_BASE pci_io_base 52#define _IO_BASE pci_io_base
53#define _ISA_MEM_BASE 0 53#define _ISA_MEM_BASE isa_mem_base
54#define PCI_DRAM_OFFSET 0 54#define PCI_DRAM_OFFSET 0
55#endif 55#endif
56 56
57extern unsigned long isa_io_base; 57extern unsigned long isa_io_base;
58extern unsigned long isa_mem_base;
59extern unsigned long pci_io_base; 58extern unsigned long pci_io_base;
60extern unsigned long pci_dram_offset; 59extern unsigned long pci_dram_offset;
61 60
61extern resource_size_t isa_mem_base;
62
62#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO) 63#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
63#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits 64#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
64#endif 65#endif
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
index 4a82fdccee92..7a3cef785abd 100644
--- a/include/asm-powerpc/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -69,10 +69,9 @@ struct iommu_table {
69}; 69};
70 70
71struct scatterlist; 71struct scatterlist;
72struct device_node;
73 72
74/* Frees table for an individual device node */ 73/* Frees table for an individual device node */
75extern void iommu_free_table(struct device_node *dn); 74extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
76 75
77/* Initializes an iommu_table based in values set in the passed-in 76/* Initializes an iommu_table based in values set in the passed-in
78 * structure 77 * structure
diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h
index edec79dcb7c1..8ff08be00146 100644
--- a/include/asm-powerpc/ipic.h
+++ b/include/asm-powerpc/ipic.h
@@ -20,11 +20,13 @@
20 20
21/* Flags when we init the IPIC */ 21/* Flags when we init the IPIC */
22#define IPIC_SPREADMODE_GRP_A 0x00000001 22#define IPIC_SPREADMODE_GRP_A 0x00000001
23#define IPIC_SPREADMODE_GRP_D 0x00000002 23#define IPIC_SPREADMODE_GRP_B 0x00000002
24#define IPIC_SPREADMODE_MIX_A 0x00000004 24#define IPIC_SPREADMODE_GRP_C 0x00000004
25#define IPIC_SPREADMODE_MIX_B 0x00000008 25#define IPIC_SPREADMODE_GRP_D 0x00000008
26#define IPIC_DISABLE_MCP_OUT 0x00000010 26#define IPIC_SPREADMODE_MIX_A 0x00000010
27#define IPIC_IRQ0_MCP 0x00000020 27#define IPIC_SPREADMODE_MIX_B 0x00000020
28#define IPIC_DISABLE_MCP_OUT 0x00000040
29#define IPIC_IRQ0_MCP 0x00000080
28 30
29/* IPIC registers offsets */ 31/* IPIC registers offsets */
30#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */ 32#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
diff --git a/include/asm-powerpc/iseries/hv_lp_event.h b/include/asm-powerpc/iseries/hv_lp_event.h
index 6ce2ce1e2690..8f5da7d77202 100644
--- a/include/asm-powerpc/iseries/hv_lp_event.h
+++ b/include/asm-powerpc/iseries/hv_lp_event.h
@@ -78,7 +78,7 @@ extern int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
78 78
79/* 79/*
80 * Close an Lp Event Path for a type and partition 80 * Close an Lp Event Path for a type and partition
81 * returns 0 on sucess 81 * returns 0 on success
82 */ 82 */
83extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex); 83extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
84 84
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 6968f4300dca..0872ec228c1e 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -204,6 +204,13 @@ struct machdep_calls {
204 /* 204 /*
205 * optional PCI "hooks" 205 * optional PCI "hooks"
206 */ 206 */
207 /* Called in indirect_* to avoid touching devices */
208 int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
209
210 /* Called at then very end of pcibios_init() */
211 void (*pcibios_after_init)(void);
212
213#endif /* CONFIG_PPC32 */
207 214
208 /* Called after PPC generic resource fixup to perform 215 /* Called after PPC generic resource fixup to perform
209 machine specific fixups */ 216 machine specific fixups */
@@ -212,18 +219,9 @@ struct machdep_calls {
212 /* Called for each PCI bus in the system when it's probed */ 219 /* Called for each PCI bus in the system when it's probed */
213 void (*pcibios_fixup_bus)(struct pci_bus *); 220 void (*pcibios_fixup_bus)(struct pci_bus *);
214 221
215 /* Called when pci_enable_device() is called (initial=0) or 222 /* Called when pci_enable_device() is called. Returns 0 to
216 * when a device with no assigned resource is found (initial=1). 223 * allow assignment/enabling of the device. */
217 * Returns 0 to allow assignment/enabling of the device. */ 224 int (*pcibios_enable_device_hook)(struct pci_dev *);
218 int (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
219
220 /* Called in indirect_* to avoid touching devices */
221 int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
222
223 /* Called at then very end of pcibios_init() */
224 void (*pcibios_after_init)(void);
225
226#endif /* CONFIG_PPC32 */
227 225
228 /* Called to shutdown machine specific hardware not already controlled 226 /* Called to shutdown machine specific hardware not already controlled
229 * by other drivers. 227 * by other drivers.
@@ -253,6 +251,16 @@ struct machdep_calls {
253 */ 251 */
254 void (*machine_kexec)(struct kimage *image); 252 void (*machine_kexec)(struct kimage *image);
255#endif /* CONFIG_KEXEC */ 253#endif /* CONFIG_KEXEC */
254
255#ifdef CONFIG_SUSPEND
256 /* These are called to disable and enable, respectively, IRQs when
257 * entering a suspend state. If NULL, then the generic versions
258 * will be called. The generic versions disable/enable the
259 * decrementer along with interrupts.
260 */
261 void (*suspend_disable_irqs)(void);
262 void (*suspend_enable_irqs)(void);
263#endif
256}; 264};
257 265
258extern void power4_idle(void); 266extern void power4_idle(void);
@@ -326,5 +334,31 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal)
326 ppc_md.log_error(buf, err_type, fatal); 334 ppc_md.log_error(buf, err_type, fatal);
327} 335}
328 336
337#define __define_machine_initcall(mach,level,fn,id) \
338 static int __init __machine_initcall_##mach##_##fn(void) { \
339 if (machine_is(mach)) return fn(); \
340 return 0; \
341 } \
342 __define_initcall(level,__machine_initcall_##mach##_##fn,id);
343
344#define machine_core_initcall(mach,fn) __define_machine_initcall(mach,"1",fn,1)
345#define machine_core_initcall_sync(mach,fn) __define_machine_initcall(mach,"1s",fn,1s)
346#define machine_postcore_initcall(mach,fn) __define_machine_initcall(mach,"2",fn,2)
347#define machine_postcore_initcall_sync(mach,fn) __define_machine_initcall(mach,"2s",fn,2s)
348#define machine_arch_initcall(mach,fn) __define_machine_initcall(mach,"3",fn,3)
349#define machine_arch_initcall_sync(mach,fn) __define_machine_initcall(mach,"3s",fn,3s)
350#define machine_subsys_initcall(mach,fn) __define_machine_initcall(mach,"4",fn,4)
351#define machine_subsys_initcall_sync(mach,fn) __define_machine_initcall(mach,"4s",fn,4s)
352#define machine_fs_initcall(mach,fn) __define_machine_initcall(mach,"5",fn,5)
353#define machine_fs_initcall_sync(mach,fn) __define_machine_initcall(mach,"5s",fn,5s)
354#define machine_rootfs_initcall(mach,fn) __define_machine_initcall(mach,"rootfs",fn,rootfs)
355#define machine_device_initcall(mach,fn) __define_machine_initcall(mach,"6",fn,6)
356#define machine_device_initcall_sync(mach,fn) __define_machine_initcall(mach,"6s",fn,6s)
357#define machine_late_initcall(mach,fn) __define_machine_initcall(mach,"7",fn,7)
358#define machine_late_initcall_sync(mach,fn) __define_machine_initcall(mach,"7s",fn,7s)
359
360void generic_suspend_disable_irqs(void);
361void generic_suspend_enable_irqs(void);
362
329#endif /* __KERNEL__ */ 363#endif /* __KERNEL__ */
330#endif /* _ASM_POWERPC_MACHDEP_H */ 364#endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
index 82328dec2b52..12e5e773c67e 100644
--- a/include/asm-powerpc/mmu-hash64.h
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -180,6 +180,7 @@ extern int mmu_vmalloc_psize;
180extern int mmu_io_psize; 180extern int mmu_io_psize;
181extern int mmu_kernel_ssize; 181extern int mmu_kernel_ssize;
182extern int mmu_highuser_ssize; 182extern int mmu_highuser_ssize;
183extern u16 mmu_slb_size;
183 184
184/* 185/*
185 * If the processor supports 64k normal pages but not 64k cache 186 * If the processor supports 64k normal pages but not 64k cache
diff --git a/include/asm-powerpc/nvram.h b/include/asm-powerpc/nvram.h
index 9877982508bf..4e7059cc6113 100644
--- a/include/asm-powerpc/nvram.h
+++ b/include/asm-powerpc/nvram.h
@@ -10,6 +10,8 @@
10#ifndef _ASM_POWERPC_NVRAM_H 10#ifndef _ASM_POWERPC_NVRAM_H
11#define _ASM_POWERPC_NVRAM_H 11#define _ASM_POWERPC_NVRAM_H
12 12
13#include <linux/errno.h>
14
13#define NVRW_CNT 0x20 15#define NVRW_CNT 0x20
14#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */ 16#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */
15#define NVRAM_BLOCK_LEN 16 17#define NVRAM_BLOCK_LEN 16
@@ -71,7 +73,16 @@ extern int nvram_clear_error_log(void);
71extern struct nvram_partition *nvram_find_partition(int sig, const char *name); 73extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
72 74
73extern int pSeries_nvram_init(void); 75extern int pSeries_nvram_init(void);
76
77#ifdef CONFIG_MMIO_NVRAM
74extern int mmio_nvram_init(void); 78extern int mmio_nvram_init(void);
79#else
80static inline int mmio_nvram_init(void)
81{
82 return -ENODEV;
83}
84#endif
85
75#endif /* __KERNEL__ */ 86#endif /* __KERNEL__ */
76 87
77/* PowerMac specific nvram stuffs */ 88/* PowerMac specific nvram stuffs */
diff --git a/include/asm-powerpc/of_platform.h b/include/asm-powerpc/of_platform.h
index 80e6fad28b4f..1bce5efe1de0 100644
--- a/include/asm-powerpc/of_platform.h
+++ b/include/asm-powerpc/of_platform.h
@@ -15,8 +15,14 @@
15#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16 16
17/* Platform drivers register/unregister */ 17/* Platform drivers register/unregister */
18extern int of_register_platform_driver(struct of_platform_driver *drv); 18static inline int of_register_platform_driver(struct of_platform_driver *drv)
19extern void of_unregister_platform_driver(struct of_platform_driver *drv); 19{
20 return of_register_driver(drv, &of_platform_bus_type);
21}
22static inline void of_unregister_platform_driver(struct of_platform_driver *drv)
23{
24 of_unregister_driver(drv);
25}
20 26
21/* Platform devices and busses creation */ 27/* Platform devices and busses creation */
22extern struct of_device *of_platform_device_create(struct device_node *np, 28extern struct of_device *of_platform_device_create(struct device_node *np,
@@ -26,7 +32,7 @@ extern struct of_device *of_platform_device_create(struct device_node *np,
26#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1) 32#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
27 33
28extern int of_platform_bus_probe(struct device_node *root, 34extern int of_platform_bus_probe(struct device_node *root,
29 struct of_device_id *matches, 35 const struct of_device_id *matches,
30 struct device *parent); 36 struct device *parent);
31 37
32extern struct of_device *of_find_device_by_phandle(phandle ph); 38extern struct of_device *of_find_device_by_phandle(phandle ph);
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index d8bdc79db12e..9b16d3b17169 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -1,15 +1,42 @@
1#ifndef _ASM_POWERPC_PCI_BRIDGE_H 1#ifndef _ASM_POWERPC_PCI_BRIDGE_H
2#define _ASM_POWERPC_PCI_BRIDGE_H 2#define _ASM_POWERPC_PCI_BRIDGE_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
5#include <linux/pci.h> 10#include <linux/pci.h>
6#include <linux/list.h> 11#include <linux/list.h>
7#include <linux/ioport.h> 12#include <linux/ioport.h>
8 13
9#ifndef CONFIG_PPC64
10
11struct device_node; 14struct device_node;
12struct pci_controller; 15
16extern unsigned int ppc_pci_flags;
17enum {
18 /* Force re-assigning all resources (ignore firmware
19 * setup completely)
20 */
21 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
22
23 /* Re-assign all bus numbers */
24 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
25
26 /* Do not try to assign, just use existing setup */
27 PPC_PCI_PROBE_ONLY = 0x00000004,
28
29 /* Don't bother with ISA alignment unless the bridge has
30 * ISA forwarding enabled
31 */
32 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
33
34 /* Enable domain numbers in /proc */
35 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
36 /* ... except for domain 0 */
37 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
38};
39
13 40
14/* 41/*
15 * Structure of a PCI controller (host bridge) 42 * Structure of a PCI controller (host bridge)
@@ -17,26 +44,41 @@ struct pci_controller;
17struct pci_controller { 44struct pci_controller {
18 struct pci_bus *bus; 45 struct pci_bus *bus;
19 char is_dynamic; 46 char is_dynamic;
20 void *arch_data; 47#ifdef CONFIG_PPC64
48 int node;
49#endif
50 struct device_node *dn;
21 struct list_head list_node; 51 struct list_head list_node;
22 struct device *parent; 52 struct device *parent;
23 53
24 int first_busno; 54 int first_busno;
25 int last_busno; 55 int last_busno;
56#ifndef CONFIG_PPC64
26 int self_busno; 57 int self_busno;
58#endif
27 59
28 void __iomem *io_base_virt; 60 void __iomem *io_base_virt;
61#ifdef CONFIG_PPC64
62 void *io_base_alloc;
63#endif
29 resource_size_t io_base_phys; 64 resource_size_t io_base_phys;
65#ifndef CONFIG_PPC64
66 resource_size_t pci_io_size;
67#endif
30 68
31 /* Some machines (PReP) have a non 1:1 mapping of 69 /* Some machines (PReP) have a non 1:1 mapping of
32 * the PCI memory space in the CPU bus space 70 * the PCI memory space in the CPU bus space
33 */ 71 */
34 resource_size_t pci_mem_offset; 72 resource_size_t pci_mem_offset;
73#ifdef CONFIG_PPC64
74 unsigned long pci_io_size;
75#endif
35 76
36 struct pci_ops *ops; 77 struct pci_ops *ops;
37 volatile unsigned int __iomem *cfg_addr; 78 unsigned int __iomem *cfg_addr;
38 volatile void __iomem *cfg_data; 79 void __iomem *cfg_data;
39 80
81#ifndef CONFIG_PPC64
40 /* 82 /*
41 * Used for variants of PCI indirect handling and possible quirks: 83 * Used for variants of PCI indirect handling and possible quirks:
42 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 84 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
@@ -51,21 +93,30 @@ struct pci_controller {
51 * set. 93 * set.
52 * BIG_ENDIAN - cfg_addr is a big endian register 94 * BIG_ENDIAN - cfg_addr is a big endian register
53 */ 95 */
54#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) 96#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
55#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) 97#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
56#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) 98#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
57#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) 99#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
58#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010) 100#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
59 u32 indirect_type; 101 u32 indirect_type;
60 102#endif /* !CONFIG_PPC64 */
61 /* Currently, we limit ourselves to 1 IO range and 3 mem 103 /* Currently, we limit ourselves to 1 IO range and 3 mem
62 * ranges since the common pci_bus structure can't handle more 104 * ranges since the common pci_bus structure can't handle more
63 */ 105 */
64 struct resource io_resource; 106 struct resource io_resource;
65 struct resource mem_resources[3]; 107 struct resource mem_resources[3];
66 int global_number; /* PCI domain number */ 108 int global_number; /* PCI domain number */
109#ifdef CONFIG_PPC64
110 unsigned long buid;
111 unsigned long dma_window_base_cur;
112 unsigned long dma_window_size;
113
114 void *private_data;
115#endif /* CONFIG_PPC64 */
67}; 116};
68 117
118#ifndef CONFIG_PPC64
119
69static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) 120static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
70{ 121{
71 return bus->sysdata; 122 return bus->sysdata;
@@ -81,18 +132,18 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
81 132
82/* These are used for config access before all the PCI probing 133/* These are used for config access before all the PCI probing
83 has been done. */ 134 has been done. */
84int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, 135extern int early_read_config_byte(struct pci_controller *hose, int bus,
85 int where, u8 *val); 136 int dev_fn, int where, u8 *val);
86int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, 137extern int early_read_config_word(struct pci_controller *hose, int bus,
87 int where, u16 *val); 138 int dev_fn, int where, u16 *val);
88int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, 139extern int early_read_config_dword(struct pci_controller *hose, int bus,
89 int where, u32 *val); 140 int dev_fn, int where, u32 *val);
90int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, 141extern int early_write_config_byte(struct pci_controller *hose, int bus,
91 int where, u8 val); 142 int dev_fn, int where, u8 val);
92int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, 143extern int early_write_config_word(struct pci_controller *hose, int bus,
93 int where, u16 val); 144 int dev_fn, int where, u16 val);
94int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, 145extern int early_write_config_dword(struct pci_controller *hose, int bus,
95 int where, u32 val); 146 int dev_fn, int where, u32 val);
96 147
97extern int early_find_capability(struct pci_controller *hose, int bus, 148extern int early_find_capability(struct pci_controller *hose, int bus,
98 int dev_fn, int cap); 149 int dev_fn, int cap);
@@ -104,62 +155,12 @@ extern void setup_grackle(struct pci_controller *hose);
104extern void __init update_bridge_resource(struct pci_dev *dev, 155extern void __init update_bridge_resource(struct pci_dev *dev,
105 struct resource *res); 156 struct resource *res);
106 157
107#else 158#else /* CONFIG_PPC64 */
108
109
110/*
111 * This program is free software; you can redistribute it and/or
112 * modify it under the terms of the GNU General Public License
113 * as published by the Free Software Foundation; either version
114 * 2 of the License, or (at your option) any later version.
115 */
116
117/*
118 * Structure of a PCI controller (host bridge)
119 */
120struct pci_controller {
121 struct pci_bus *bus;
122 char is_dynamic;
123 int node;
124 void *arch_data;
125 struct list_head list_node;
126 struct device *parent;
127
128 int first_busno;
129 int last_busno;
130
131 void __iomem *io_base_virt;
132 void *io_base_alloc;
133 resource_size_t io_base_phys;
134
135 /* Some machines have a non 1:1 mapping of
136 * the PCI memory space in the CPU bus space
137 */
138 resource_size_t pci_mem_offset;
139 unsigned long pci_io_size;
140
141 struct pci_ops *ops;
142 volatile unsigned int __iomem *cfg_addr;
143 volatile void __iomem *cfg_data;
144
145 /* Currently, we limit ourselves to 1 IO range and 3 mem
146 * ranges since the common pci_bus structure can't handle more
147 */
148 struct resource io_resource;
149 struct resource mem_resources[3];
150 int global_number;
151 unsigned long buid;
152 unsigned long dma_window_base_cur;
153 unsigned long dma_window_size;
154
155 void *private_data;
156};
157 159
158/* 160/*
159 * PCI stuff, for nodes representing PCI devices, pointed to 161 * PCI stuff, for nodes representing PCI devices, pointed to
160 * by device_node->data. 162 * by device_node->data.
161 */ 163 */
162struct pci_controller;
163struct iommu_table; 164struct iommu_table;
164 165
165struct pci_dn { 166struct pci_dn {
@@ -179,9 +180,9 @@ struct pci_dn {
179 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 180 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
180 int eeh_config_addr; 181 int eeh_config_addr;
181 int eeh_pe_config_addr; /* new-style partition endpoint address */ 182 int eeh_pe_config_addr; /* new-style partition endpoint address */
182 int eeh_check_count; /* # times driver ignored error */ 183 int eeh_check_count; /* # times driver ignored error */
183 int eeh_freeze_count; /* # times this device froze up. */ 184 int eeh_freeze_count; /* # times this device froze up. */
184 int eeh_false_positives; /* # times this device reported #ff's */ 185 int eeh_false_positives; /* # times this device reported #ff's */
185 u32 config_space[16]; /* saved PCI config space */ 186 u32 config_space[16]; /* saved PCI config space */
186#endif 187#endif
187}; 188};
@@ -189,7 +190,7 @@ struct pci_dn {
189/* Get the pointer to a device_node's pci_dn */ 190/* Get the pointer to a device_node's pci_dn */
190#define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 191#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
191 192
192struct device_node *fetch_dev_dn(struct pci_dev *dev); 193extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
193 194
194/* Get a device_node from a pci_dev. This code must be fast except 195/* Get a device_node from a pci_dev. This code must be fast except
195 * in the case where the sysdata is incorrect and needs to be fixed 196 * in the case where the sysdata is incorrect and needs to be fixed
@@ -227,14 +228,14 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
227} 228}
228 229
229/** Find the bus corresponding to the indicated device node */ 230/** Find the bus corresponding to the indicated device node */
230struct pci_bus * pcibios_find_pci_bus(struct device_node *dn); 231extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
231 232
232/** Remove all of the PCI devices under this bus */ 233/** Remove all of the PCI devices under this bus */
233void pcibios_remove_pci_devices(struct pci_bus *bus); 234extern void pcibios_remove_pci_devices(struct pci_bus *bus);
234 235
235/** Discover new pci devices under this bus, and add them */ 236/** Discover new pci devices under this bus, and add them */
236void pcibios_add_pci_devices(struct pci_bus * bus); 237extern void pcibios_add_pci_devices(struct pci_bus *bus);
237void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus); 238extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
238 239
239extern int pcibios_remove_root_bus(struct pci_controller *phb); 240extern int pcibios_remove_root_bus(struct pci_controller *phb);
240 241
@@ -270,20 +271,18 @@ extern int pcibios_map_io_space(struct pci_bus *bus);
270#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 271#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
271#endif 272#endif
272 273
273#endif /* CONFIG_PPC64 */ 274#endif /* CONFIG_PPC64 */
274 275
275/* Get the PCI host controller for an OF device */ 276/* Get the PCI host controller for an OF device */
276extern struct pci_controller* 277extern struct pci_controller *pci_find_hose_for_OF_device(
277pci_find_hose_for_OF_device(struct device_node* node); 278 struct device_node* node);
278 279
279/* Fill up host controller resources from the OF node */ 280/* Fill up host controller resources from the OF node */
280extern void 281extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
281pci_process_bridge_OF_ranges(struct pci_controller *hose, 282 struct device_node *dev, int primary);
282 struct device_node *dev, int primary);
283 283
284/* Allocate & free a PCI host bridge structure */ 284/* Allocate & free a PCI host bridge structure */
285extern struct pci_controller * 285extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
286pcibios_alloc_controller(struct device_node *dev);
287extern void pcibios_free_controller(struct pci_controller *phb); 286extern void pcibios_free_controller(struct pci_controller *phb);
288 287
289#ifdef CONFIG_PCI 288#ifdef CONFIG_PCI
@@ -298,9 +297,7 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address)
298{ 297{
299 return 0; 298 return 0;
300} 299}
301#endif 300#endif /* CONFIG_PCI */
302
303 301
304 302#endif /* __KERNEL__ */
305#endif /* __KERNEL__ */ 303#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
306#endif
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index 7b11765c6865..a05a942b1c25 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -36,11 +36,10 @@ struct pci_dev;
36 36
37/* 37/*
38 * Set this to 1 if you want the kernel to re-assign all PCI 38 * Set this to 1 if you want the kernel to re-assign all PCI
39 * bus numbers 39 * bus numbers (don't do that on ppc64 yet !)
40 */ 40 */
41extern int pci_assign_all_buses; 41#define pcibios_assign_all_busses() (ppc_pci_flags & \
42#define pcibios_assign_all_busses() (pci_assign_all_buses) 42 PPC_PCI_REASSIGN_ALL_BUS)
43
44#define pcibios_scan_all_fns(a, b) 0 43#define pcibios_scan_all_fns(a, b) 0
45 44
46static inline void pcibios_set_master(struct pci_dev *dev) 45static inline void pcibios_set_master(struct pci_dev *dev)
@@ -95,9 +94,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
95#define get_pci_dma_ops() NULL 94#define get_pci_dma_ops() NULL
96#endif 95#endif
97 96
98/* Decide whether to display the domain number in /proc */
99extern int pci_proc_domain(struct pci_bus *bus);
100
101#else /* 32-bit */ 97#else /* 32-bit */
102 98
103#ifdef CONFIG_PCI 99#ifdef CONFIG_PCI
@@ -109,17 +105,14 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
109 *strategy_parameter = ~0UL; 105 *strategy_parameter = ~0UL;
110} 106}
111#endif 107#endif
112
113/* Set the name of the bus as it appears in /proc/bus/pci */
114static inline int pci_proc_domain(struct pci_bus *bus)
115{
116 return 0;
117}
118
119#endif /* CONFIG_PPC64 */ 108#endif /* CONFIG_PPC64 */
120 109
121extern int pci_domain_nr(struct pci_bus *bus); 110extern int pci_domain_nr(struct pci_bus *bus);
122 111
112/* Decide whether to display the domain number in /proc */
113extern int pci_proc_domain(struct pci_bus *bus);
114
115
123struct vm_area_struct; 116struct vm_area_struct;
124/* Map a range of PCI memory or I/O space for a device into user space */ 117/* Map a range of PCI memory or I/O space for a device into user space */
125int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, 118int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
@@ -199,13 +192,12 @@ static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
199 return root; 192 return root;
200} 193}
201 194
202extern void pcibios_fixup_device_resources(struct pci_dev *dev,
203 struct pci_bus *bus);
204
205extern void pcibios_setup_new_device(struct pci_dev *dev); 195extern void pcibios_setup_new_device(struct pci_dev *dev);
206 196
207extern void pcibios_claim_one_bus(struct pci_bus *b); 197extern void pcibios_claim_one_bus(struct pci_bus *b);
208 198
199extern void pcibios_resource_survey(void);
200
209extern struct pci_controller *init_phb_dynamic(struct device_node *dn); 201extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
210 202
211extern struct pci_dev *of_create_pci_dev(struct device_node *node, 203extern struct pci_dev *of_create_pci_dev(struct device_node *node,
@@ -229,5 +221,8 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
229 const struct resource *rsrc, 221 const struct resource *rsrc,
230 resource_size_t *start, resource_size_t *end); 222 resource_size_t *start, resource_size_t *end);
231 223
224extern void pcibios_do_bus_setup(struct pci_bus *bus);
225extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);
226
232#endif /* __KERNEL__ */ 227#endif /* __KERNEL__ */
233#endif /* __ASM_POWERPC_PCI_H */ 228#endif /* __ASM_POWERPC_PCI_H */
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
index b847aa10074b..854ab713f56c 100644
--- a/include/asm-powerpc/ppc-pci.h
+++ b/include/asm-powerpc/ppc-pci.h
@@ -22,7 +22,6 @@ extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
22 22
23 23
24extern struct list_head hose_list; 24extern struct list_head hose_list;
25extern int global_phb_number;
26 25
27extern void find_and_init_phbs(void); 26extern void find_and_init_phbs(void);
28 27
@@ -47,9 +46,6 @@ extern void init_pci_config_tokens (void);
47extern unsigned long get_phb_buid (struct device_node *); 46extern unsigned long get_phb_buid (struct device_node *);
48extern int rtas_setup_phb(struct pci_controller *phb); 47extern int rtas_setup_phb(struct pci_controller *phb);
49 48
50/* From iSeries PCI */
51extern void iSeries_pcibios_init(void);
52
53extern unsigned long pci_probe_only; 49extern unsigned long pci_probe_only;
54 50
55/* ---- EEH internal-use-only related routines ---- */ 51/* ---- EEH internal-use-only related routines ---- */
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index 925e2d384bb3..78b7b0d494c0 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -202,6 +202,10 @@ static inline unsigned long of_read_ulong(const u32 *cell, int size)
202 */ 202 */
203extern u64 of_translate_address(struct device_node *np, const u32 *addr); 203extern u64 of_translate_address(struct device_node *np, const u32 *addr);
204 204
205/* Translate a DMA address from device space to CPU space */
206extern u64 of_translate_dma_address(struct device_node *dev,
207 const u32 *in_addr);
208
205/* Extract an address from a device, returns the region size and 209/* Extract an address from a device, returns the region size and
206 * the address space flags too. The PCI version uses a BAR number 210 * the address space flags too. The PCI version uses a BAR number
207 * instead of an absolute index 211 * instead of an absolute index
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 0dabe46a29d2..a24b7b14958f 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -28,6 +28,52 @@
28#define MEM_PART_SECONDARY 1 28#define MEM_PART_SECONDARY 1
29#define MEM_PART_MURAM 2 29#define MEM_PART_MURAM 2
30 30
31/* Clocks and BRGs */
32enum qe_clock {
33 QE_CLK_NONE = 0,
34 QE_BRG1, /* Baud Rate Generator 1 */
35 QE_BRG2, /* Baud Rate Generator 2 */
36 QE_BRG3, /* Baud Rate Generator 3 */
37 QE_BRG4, /* Baud Rate Generator 4 */
38 QE_BRG5, /* Baud Rate Generator 5 */
39 QE_BRG6, /* Baud Rate Generator 6 */
40 QE_BRG7, /* Baud Rate Generator 7 */
41 QE_BRG8, /* Baud Rate Generator 8 */
42 QE_BRG9, /* Baud Rate Generator 9 */
43 QE_BRG10, /* Baud Rate Generator 10 */
44 QE_BRG11, /* Baud Rate Generator 11 */
45 QE_BRG12, /* Baud Rate Generator 12 */
46 QE_BRG13, /* Baud Rate Generator 13 */
47 QE_BRG14, /* Baud Rate Generator 14 */
48 QE_BRG15, /* Baud Rate Generator 15 */
49 QE_BRG16, /* Baud Rate Generator 16 */
50 QE_CLK1, /* Clock 1 */
51 QE_CLK2, /* Clock 2 */
52 QE_CLK3, /* Clock 3 */
53 QE_CLK4, /* Clock 4 */
54 QE_CLK5, /* Clock 5 */
55 QE_CLK6, /* Clock 6 */
56 QE_CLK7, /* Clock 7 */
57 QE_CLK8, /* Clock 8 */
58 QE_CLK9, /* Clock 9 */
59 QE_CLK10, /* Clock 10 */
60 QE_CLK11, /* Clock 11 */
61 QE_CLK12, /* Clock 12 */
62 QE_CLK13, /* Clock 13 */
63 QE_CLK14, /* Clock 14 */
64 QE_CLK15, /* Clock 15 */
65 QE_CLK16, /* Clock 16 */
66 QE_CLK17, /* Clock 17 */
67 QE_CLK18, /* Clock 18 */
68 QE_CLK19, /* Clock 19 */
69 QE_CLK20, /* Clock 20 */
70 QE_CLK21, /* Clock 21 */
71 QE_CLK22, /* Clock 22 */
72 QE_CLK23, /* Clock 23 */
73 QE_CLK24, /* Clock 24 */
74 QE_CLK_DUMMY
75};
76
31/* Export QE common operations */ 77/* Export QE common operations */
32extern void qe_reset(void); 78extern void qe_reset(void);
33extern int par_io_init(struct device_node *np); 79extern int par_io_init(struct device_node *np);
@@ -38,7 +84,8 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
38 84
39/* QE internal API */ 85/* QE internal API */
40int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 86int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
41void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier); 87enum qe_clock qe_clock_source(const char *source);
88int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
42int qe_get_snum(void); 89int qe_get_snum(void);
43void qe_put_snum(u8 snum); 90void qe_put_snum(u8 snum);
44unsigned long qe_muram_alloc(int size, int align); 91unsigned long qe_muram_alloc(int size, int align);
@@ -129,52 +176,6 @@ enum comm_dir {
129 COMM_DIR_RX_AND_TX = 3 176 COMM_DIR_RX_AND_TX = 3
130}; 177};
131 178
132/* Clocks and BRGs */
133enum qe_clock {
134 QE_CLK_NONE = 0,
135 QE_BRG1, /* Baud Rate Generator 1 */
136 QE_BRG2, /* Baud Rate Generator 2 */
137 QE_BRG3, /* Baud Rate Generator 3 */
138 QE_BRG4, /* Baud Rate Generator 4 */
139 QE_BRG5, /* Baud Rate Generator 5 */
140 QE_BRG6, /* Baud Rate Generator 6 */
141 QE_BRG7, /* Baud Rate Generator 7 */
142 QE_BRG8, /* Baud Rate Generator 8 */
143 QE_BRG9, /* Baud Rate Generator 9 */
144 QE_BRG10, /* Baud Rate Generator 10 */
145 QE_BRG11, /* Baud Rate Generator 11 */
146 QE_BRG12, /* Baud Rate Generator 12 */
147 QE_BRG13, /* Baud Rate Generator 13 */
148 QE_BRG14, /* Baud Rate Generator 14 */
149 QE_BRG15, /* Baud Rate Generator 15 */
150 QE_BRG16, /* Baud Rate Generator 16 */
151 QE_CLK1, /* Clock 1 */
152 QE_CLK2, /* Clock 2 */
153 QE_CLK3, /* Clock 3 */
154 QE_CLK4, /* Clock 4 */
155 QE_CLK5, /* Clock 5 */
156 QE_CLK6, /* Clock 6 */
157 QE_CLK7, /* Clock 7 */
158 QE_CLK8, /* Clock 8 */
159 QE_CLK9, /* Clock 9 */
160 QE_CLK10, /* Clock 10 */
161 QE_CLK11, /* Clock 11 */
162 QE_CLK12, /* Clock 12 */
163 QE_CLK13, /* Clock 13 */
164 QE_CLK14, /* Clock 14 */
165 QE_CLK15, /* Clock 15 */
166 QE_CLK16, /* Clock 16 */
167 QE_CLK17, /* Clock 17 */
168 QE_CLK18, /* Clock 18 */
169 QE_CLK19, /* Clock 19 */
170 QE_CLK20, /* Clock 20 */
171 QE_CLK21, /* Clock 21 */
172 QE_CLK22, /* Clock 22 */
173 QE_CLK23, /* Clock 23 */
174 QE_CLK24, /* Clock 24 */
175 QE_CLK_DUMMY,
176};
177
178/* QE CMXUCR Registers. 179/* QE CMXUCR Registers.
179 * There are two UCCs represented in each of the four CMXUCR registers. 180 * There are two UCCs represented in each of the four CMXUCR registers.
180 * These values are for the UCC in the LSBs 181 * These values are for the UCC in the LSBs
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index e775ff1ca413..1f685047c6ff 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -691,12 +691,6 @@
691#define PV_BE 0x0070 691#define PV_BE 0x0070
692#define PV_PA6T 0x0090 692#define PV_PA6T 0x0090
693 693
694/*
695 * Number of entries in the SLB. If this ever changes we should handle
696 * it with a use a cpu feature fixup.
697 */
698#define SLB_NUM_ENTRIES 64
699
700/* Macros for setting and retrieving special purpose registers */ 694/* Macros for setting and retrieving special purpose registers */
701#ifndef __ASSEMBLY__ 695#ifndef __ASSEMBLY__
702#define mfmsr() ({unsigned long rval; \ 696#define mfmsr() ({unsigned long rval; \
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 8fdc2b47afb9..d3e8dd0fc738 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -123,16 +123,23 @@
123#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 123#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
124#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 124#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
125#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 125#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
126#define SPRN_ATB 0x20E /* Alternate Time Base */
127#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
128#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
126#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ 129#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
127#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ 130#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
128#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ 131#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
129#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ 132#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
133#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
134#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
130#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ 135#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
131#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 136#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
132#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 137#define SPRN_MCSR 0x23C /* Machine Check Status Register */
133#define SPRN_MCAR 0x23D /* Machine Check Address Register */ 138#define SPRN_MCAR 0x23D /* Machine Check Address Register */
134#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ 139#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
135#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ 140#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
141#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
142#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
136#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 143#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
137#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 144#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
138#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 145#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
@@ -140,15 +147,18 @@
140#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ 147#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
141#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ 148#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
142#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ 149#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
143#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
144#define SPRN_PID1 0x279 /* Process ID Register 1 */ 150#define SPRN_PID1 0x279 /* Process ID Register 1 */
145#define SPRN_PID2 0x27A /* Process ID Register 2 */ 151#define SPRN_PID2 0x27A /* Process ID Register 2 */
146#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ 152#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
147#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ 153#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
154#define SPRN_EPR 0x2BE /* External Proxy Register */
148#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ 155#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
149#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ 156#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
157#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
150#define SPRN_MMUCR 0x3B2 /* MMU Control Register */ 158#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
151#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ 159#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
160#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
161#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
152#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ 162#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
153#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ 163#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
154#define SPRN_SLER 0x3BB /* Little-endian real mode */ 164#define SPRN_SLER 0x3BB /* Little-endian real mode */
@@ -159,6 +169,7 @@
159#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ 169#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
160#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ 170#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
161#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 171#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
172#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
162#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 173#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
163#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 174#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
164#define SPRN_SVR 0x3FF /* System Version Register */ 175#define SPRN_SVR 0x3FF /* System Version Register */
@@ -293,7 +304,7 @@
293#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 304#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
294#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 305#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
295#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 306#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
296#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ 307#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
297#define ESR_PTR 0x02000000 /* Program Exception - Trap */ 308#define ESR_PTR 0x02000000 /* Program Exception - Trap */
298#define ESR_FP 0x01000000 /* Floating Point Operation */ 309#define ESR_FP 0x01000000 /* Floating Point Operation */
299#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 310#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
diff --git a/include/asm-powerpc/smu.h b/include/asm-powerpc/smu.h
index e49f644ca63a..7ae2753da565 100644
--- a/include/asm-powerpc/smu.h
+++ b/include/asm-powerpc/smu.h
@@ -22,7 +22,7 @@
22 * Partition info commands 22 * Partition info commands
23 * 23 *
24 * These commands are used to retrieve the sdb-partition-XX datas from 24 * These commands are used to retrieve the sdb-partition-XX datas from
25 * the SMU. The lenght is always 2. First byte is the subcommand code 25 * the SMU. The length is always 2. First byte is the subcommand code
26 * and second byte is the partition ID. 26 * and second byte is the partition ID.
27 * 27 *
28 * The reply is 6 bytes: 28 * The reply is 6 bytes:
@@ -173,12 +173,12 @@
173 * Power supply control 173 * Power supply control
174 * 174 *
175 * The "sub" command is an ASCII string in the data, the 175 * The "sub" command is an ASCII string in the data, the
176 * data lenght is that of the string. 176 * data length is that of the string.
177 * 177 *
178 * The VSLEW command can be used to get or set the voltage slewing. 178 * The VSLEW command can be used to get or set the voltage slewing.
179 * - lenght 5 (only "VSLEW") : it returns "DONE" and 3 bytes of 179 * - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
180 * reply at data offset 6, 7 and 8. 180 * reply at data offset 6, 7 and 8.
181 * - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is 181 * - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is
182 * used to set the voltage slewing point. The SMU replies with "DONE" 182 * used to set the voltage slewing point. The SMU replies with "DONE"
183 * I yet have to figure out their exact meaning of those 3 bytes in 183 * I yet have to figure out their exact meaning of those 3 bytes in
184 * both cases. They seem to be: 184 * both cases. They seem to be:
@@ -201,20 +201,90 @@
201 */ 201 */
202#define SMU_CMD_READ_ADC 0xd8 202#define SMU_CMD_READ_ADC 0xd8
203 203
204
204/* Misc commands 205/* Misc commands
205 * 206 *
206 * This command seem to be a grab bag of various things 207 * This command seem to be a grab bag of various things
208 *
209 * Parameters:
210 * 1: subcommand
207 */ 211 */
208#define SMU_CMD_MISC_df_COMMAND 0xdf 212#define SMU_CMD_MISC_df_COMMAND 0xdf
209#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 /* i: 1 byte */ 213
214/*
215 * Sets "system ready" status
216 *
217 * I did not yet understand how it exactly works or what it does.
218 *
219 * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used
220 * the same codebase for all OF versions. On PowerBooks, this command would
221 * enable the backlight. For the G5s, it only activates the front LED. However,
222 * don't take this for granted.
223 *
224 * Parameters:
225 * 2: status [0x00, 0x01 or 0x02]
226 */
227#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02
228
229/*
230 * Sets mode of power switch.
231 *
232 * What this actually does is not yet known. Maybe it enables some interrupt.
233 *
234 * Parameters:
235 * 2: enable power switch? [0x00 or 0x01]
236 * 3 (optional): enable nmi? [0x00 or 0x01]
237 *
238 * Returns:
239 * If parameter 2 is 0x00 and parameter 3 is not specified, returns wether
240 * NMI is enabled. Otherwise unknown.
241 */
210#define SMU_CMD_MISC_df_NMI_OPTION 0x04 242#define SMU_CMD_MISC_df_NMI_OPTION 0x04
211 243
244/* Sets LED dimm offset.
245 *
246 * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
247 * frequency) depends on current time. Therefore, the SMU needs to know the
248 * timezone.
249 *
250 * Parameters:
251 * 2-8: unknown (BCD coding)
252 */
253#define SMU_CMD_MISC_df_DIMM_OFFSET 0x99
254
255
212/* 256/*
213 * Version info commands 257 * Version info commands
214 * 258 *
215 * I haven't quite tried to figure out how these work 259 * Parameters:
260 * 1 (optional): Specifies version part to retrieve
261 *
262 * Returns:
263 * Version value
216 */ 264 */
217#define SMU_CMD_VERSION_COMMAND 0xea 265#define SMU_CMD_VERSION_COMMAND 0xea
266#define SMU_VERSION_RUNNING 0x00
267#define SMU_VERSION_BASE 0x01
268#define SMU_VERSION_UPDATE 0x02
269
270
271/*
272 * Switches
273 *
274 * These are switches whose status seems to be known to the SMU.
275 *
276 * Parameters:
277 * none
278 *
279 * Result:
280 * Switch bits (ORed, see below)
281 */
282#define SMU_CMD_SWITCHES 0xdc
283
284/* Switches bits */
285#define SMU_SWITCH_CASE_CLOSED 0x01
286#define SMU_SWITCH_AC_POWER 0x04
287#define SMU_SWITCH_POWER_SWITCH 0x08
218 288
219 289
220/* 290/*
@@ -243,10 +313,64 @@
243 */ 313 */
244#define SMU_CMD_MISC_ee_COMMAND 0xee 314#define SMU_CMD_MISC_ee_COMMAND 0xee
245#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02 315#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
246#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */ 316
317/* Retrieves currently used watts.
318 *
319 * Parameters:
320 * 1: 0x03 (Meaning unknown)
321 */
322#define SMU_CMD_MISC_ee_GET_WATTS 0x03
323
324#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
247#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */ 325#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
248 326
249 327
328/*
329 * Power related commands
330 *
331 * Parameters:
332 * 1: subcommand
333 */
334#define SMU_CMD_POWER_EVENTS_COMMAND 0x8f
335
336/* SMU_POWER_EVENTS subcommands */
337enum {
338 SMU_PWR_GET_POWERUP_EVENTS = 0x00,
339 SMU_PWR_SET_POWERUP_EVENTS = 0x01,
340 SMU_PWR_CLR_POWERUP_EVENTS = 0x02,
341 SMU_PWR_GET_WAKEUP_EVENTS = 0x03,
342 SMU_PWR_SET_WAKEUP_EVENTS = 0x04,
343 SMU_PWR_CLR_WAKEUP_EVENTS = 0x05,
344
345 /*
346 * Get last shutdown cause
347 *
348 * Returns:
349 * 1 byte (signed char): Last shutdown cause. Exact meaning unknown.
350 */
351 SMU_PWR_LAST_SHUTDOWN_CAUSE = 0x07,
352
353 /*
354 * Sets or gets server ID. Meaning or use is unknown.
355 *
356 * Parameters:
357 * 2 (optional): Set server ID (1 byte)
358 *
359 * Returns:
360 * 1 byte (server ID?)
361 */
362 SMU_PWR_SERVER_ID = 0x08,
363};
364
365/* Power events wakeup bits */
366enum {
367 SMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */
368 SMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */
369 SMU_PWR_WAKEUP_AC_CHANGE = 0x04,
370 SMU_PWR_WAKEUP_LID_OPEN = 0x08,
371 SMU_PWR_WAKEUP_RING = 0x10,
372};
373
250 374
251/* 375/*
252 * - Kernel side interface - 376 * - Kernel side interface -
@@ -564,13 +688,13 @@ struct smu_user_cmd_hdr
564 688
565 __u8 cmd; /* SMU command byte */ 689 __u8 cmd; /* SMU command byte */
566 __u8 pad[3]; /* padding */ 690 __u8 pad[3]; /* padding */
567 __u32 data_len; /* Lenght of data following */ 691 __u32 data_len; /* Length of data following */
568}; 692};
569 693
570struct smu_user_reply_hdr 694struct smu_user_reply_hdr
571{ 695{
572 __u32 status; /* Command status */ 696 __u32 status; /* Command status */
573 __u32 reply_len; /* Lenght of data follwing */ 697 __u32 reply_len; /* Length of data follwing */
574}; 698};
575 699
576#endif /* _SMU_H */ 700#endif /* _SMU_H */
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index b1accce77bb5..5ca30e2e2639 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -104,6 +104,7 @@
104 104
105struct spu_context; 105struct spu_context;
106struct spu_runqueue; 106struct spu_runqueue;
107struct spu_lscsa;
107struct device_node; 108struct device_node;
108 109
109enum spu_utilization_state { 110enum spu_utilization_state {
@@ -145,7 +146,6 @@ struct spu {
145 void (* ibox_callback)(struct spu *spu); 146 void (* ibox_callback)(struct spu *spu);
146 void (* stop_callback)(struct spu *spu); 147 void (* stop_callback)(struct spu *spu);
147 void (* mfc_callback)(struct spu *spu); 148 void (* mfc_callback)(struct spu *spu);
148 void (* dma_callback)(struct spu *spu, int type);
149 149
150 char irq_c0[8]; 150 char irq_c0[8];
151 char irq_c1[8]; 151 char irq_c1[8];
@@ -196,10 +196,11 @@ struct cbe_spu_info {
196extern struct cbe_spu_info cbe_spu_info[]; 196extern struct cbe_spu_info cbe_spu_info[];
197 197
198void spu_init_channels(struct spu *spu); 198void spu_init_channels(struct spu *spu);
199int spu_irq_class_0_bottom(struct spu *spu);
200int spu_irq_class_1_bottom(struct spu *spu);
201void spu_irq_setaffinity(struct spu *spu, int cpu); 199void spu_irq_setaffinity(struct spu *spu, int cpu);
202 200
201void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
202 void *code, int code_size);
203
203#ifdef CONFIG_KEXEC 204#ifdef CONFIG_KEXEC
204void crash_register_spus(struct list_head *list); 205void crash_register_spus(struct list_head *list);
205#else 206#else
@@ -210,6 +211,7 @@ static inline void crash_register_spus(struct list_head *list)
210 211
211extern void spu_invalidate_slbs(struct spu *spu); 212extern void spu_invalidate_slbs(struct spu *spu);
212extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm); 213extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
214int spu_64k_pages_available(void);
213 215
214/* Calls from the memory management to the SPU */ 216/* Calls from the memory management to the SPU */
215struct mm_struct; 217struct mm_struct;
@@ -278,6 +280,8 @@ void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
278int spu_add_sysdev_attr_group(struct attribute_group *attrs); 280int spu_add_sysdev_attr_group(struct attribute_group *attrs);
279void spu_remove_sysdev_attr_group(struct attribute_group *attrs); 281void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
280 282
283int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
284 unsigned long dsisr, unsigned *flt);
281 285
282/* 286/*
283 * Notifier blocks: 287 * Notifier blocks:
@@ -299,7 +303,7 @@ int spu_switch_event_register(struct notifier_block * n);
299int spu_switch_event_unregister(struct notifier_block * n); 303int spu_switch_event_unregister(struct notifier_block * n);
300 304
301/* 305/*
302 * This defines the Local Store, Problem Area and Privlege Area of an SPU. 306 * This defines the Local Store, Problem Area and Privilege Area of an SPU.
303 */ 307 */
304 308
305union mfc_tag_size_class_cmd { 309union mfc_tag_size_class_cmd {
@@ -520,8 +524,24 @@ struct spu_priv1 {
520#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L 524#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
521#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L 525#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
522#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L 526#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
527#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L
523 u8 pad_0x118_0x140[0x28]; /* 0x118 */ 528 u8 pad_0x118_0x140[0x28]; /* 0x118 */
524 u64 int_stat_RW[3]; /* 0x140 */ 529 u64 int_stat_RW[3]; /* 0x140 */
530#define CLASS0_DMA_ALIGNMENT_INTR 0x1L
531#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L
532#define CLASS0_SPU_ERROR_INTR 0x4L
533#define CLASS0_INTR_MASK 0x7L
534#define CLASS1_SEGMENT_FAULT_INTR 0x1L
535#define CLASS1_STORAGE_FAULT_INTR 0x2L
536#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
537#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
538#define CLASS1_INTR_MASK 0xfL
539#define CLASS2_MAILBOX_INTR 0x1L
540#define CLASS2_SPU_STOP_INTR 0x2L
541#define CLASS2_SPU_HALT_INTR 0x4L
542#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
543#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
544#define CLASS2_INTR_MASK 0x1fL
525 u8 pad_0x158_0x180[0x28]; /* 0x158 */ 545 u8 pad_0x158_0x180[0x28]; /* 0x158 */
526 u64 int_route_RW; /* 0x180 */ 546 u64 int_route_RW; /* 0x180 */
527 547
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
index e87794d5d4ea..0ab6bff86078 100644
--- a/include/asm-powerpc/spu_csa.h
+++ b/include/asm-powerpc/spu_csa.h
@@ -194,7 +194,7 @@ struct spu_priv1_collapsed {
194}; 194};
195 195
196/* 196/*
197 * struct spu_priv2_collapsed - condensed priviliged 2 area, w/o pads. 197 * struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads.
198 */ 198 */
199struct spu_priv2_collapsed { 199struct spu_priv2_collapsed {
200 u64 slb_index_W; 200 u64 slb_index_W;
@@ -254,20 +254,11 @@ struct spu_state {
254 u64 spu_chnldata_RW[32]; 254 u64 spu_chnldata_RW[32];
255 u32 spu_mailbox_data[4]; 255 u32 spu_mailbox_data[4];
256 u32 pu_mailbox_data[1]; 256 u32 pu_mailbox_data[1];
257 u64 dar, dsisr; 257 u64 dar, dsisr, class_0_pending;
258 unsigned long suspend_time; 258 unsigned long suspend_time;
259 spinlock_t register_lock; 259 spinlock_t register_lock;
260}; 260};
261 261
262extern int spu_init_csa(struct spu_state *csa);
263extern void spu_fini_csa(struct spu_state *csa);
264extern int spu_save(struct spu_state *prev, struct spu *spu);
265extern int spu_restore(struct spu_state *new, struct spu *spu);
266extern int spu_switch(struct spu_state *prev, struct spu_state *new,
267 struct spu *spu);
268extern int spu_alloc_lscsa(struct spu_state *csa);
269extern void spu_free_lscsa(struct spu_state *csa);
270
271#endif /* !__SPU__ */ 262#endif /* !__SPU__ */
272#endif /* __KERNEL__ */ 263#endif /* __KERNEL__ */
273#endif /* !__ASSEMBLY__ */ 264#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
index 0f37c7c90820..25020a34ce7f 100644
--- a/include/asm-powerpc/spu_priv1.h
+++ b/include/asm-powerpc/spu_priv1.h
@@ -24,6 +24,7 @@
24#include <linux/types.h> 24#include <linux/types.h>
25 25
26struct spu; 26struct spu;
27struct spu_context;
27 28
28/* access to priv1 registers */ 29/* access to priv1 registers */
29 30
@@ -178,6 +179,8 @@ struct spu_management_ops {
178 int (*enumerate_spus)(int (*fn)(void *data)); 179 int (*enumerate_spus)(int (*fn)(void *data));
179 int (*create_spu)(struct spu *spu, void *data); 180 int (*create_spu)(struct spu *spu, void *data);
180 int (*destroy_spu)(struct spu *spu); 181 int (*destroy_spu)(struct spu *spu);
182 void (*enable_spu)(struct spu_context *ctx);
183 void (*disable_spu)(struct spu_context *ctx);
181 int (*init_affinity)(void); 184 int (*init_affinity)(void);
182}; 185};
183 186
@@ -207,6 +210,18 @@ spu_init_affinity (void)
207 return spu_management_ops->init_affinity(); 210 return spu_management_ops->init_affinity();
208} 211}
209 212
213static inline void
214spu_enable_spu (struct spu_context *ctx)
215{
216 spu_management_ops->enable_spu(ctx);
217}
218
219static inline void
220spu_disable_spu (struct spu_context *ctx)
221{
222 spu_management_ops->disable_spu(ctx);
223}
224
210/* 225/*
211 * The declarations folowing are put here for convenience 226 * The declarations folowing are put here for convenience
212 * and only intended to be used by the platform setup code. 227 * and only intended to be used by the platform setup code.
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h
index 1311cefdfd30..4b0e15206006 100644
--- a/include/asm-ppc/8xx_immap.h
+++ b/include/asm-ppc/8xx_immap.h
@@ -123,7 +123,7 @@ typedef struct mem_ctlr {
123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ 123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ 124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125#define OR_BI 0x00000100 /* Burst inhibit */ 125#define OR_BI 0x00000100 /* Burst inhibit */
126#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ 126#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ 127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ 128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ 129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/commproc.h
index 397248705e0e..462abb185f07 100644
--- a/include/asm-ppc/commproc.h
+++ b/include/asm-ppc/commproc.h
@@ -681,7 +681,7 @@ typedef struct risc_timer_pram {
681#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 681#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
682#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 682#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
683#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 683#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
684#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 684#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
685#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 685#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
686#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 686#define CICR_IEN ((uint)0x00000080) /* Int. enable */
687#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 687#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 82948ed2744a..4cad45a055dd 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -283,7 +283,7 @@
283#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 283#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
284#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 284#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
285#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 285#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
286#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ 286#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
287#define ESR_PTR 0x02000000 /* Program Exception - Trap */ 287#define ESR_PTR 0x02000000 /* Program Exception - Trap */
288#define ESR_FP 0x01000000 /* Floating Point Operation */ 288#define ESR_FP 0x01000000 /* Floating Point Operation */
289#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 289#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
diff --git a/include/linux/of.h b/include/linux/of.h
index 5c39b9270ff7..c65af7bd1e9c 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -46,6 +46,10 @@ extern struct device_node *of_find_node_by_phandle(phandle handle);
46extern struct device_node *of_get_parent(const struct device_node *node); 46extern struct device_node *of_get_parent(const struct device_node *node);
47extern struct device_node *of_get_next_child(const struct device_node *node, 47extern struct device_node *of_get_next_child(const struct device_node *node,
48 struct device_node *prev); 48 struct device_node *prev);
49#define for_each_child_of_node(parent, child) \
50 for (child = of_get_next_child(parent, NULL); child != NULL; \
51 child = of_get_next_child(parent, child))
52
49extern struct property *of_find_property(const struct device_node *np, 53extern struct property *of_find_property(const struct device_node *np,
50 const char *name, 54 const char *name,
51 int *lenp); 55 int *lenp);
diff --git a/include/linux/pmu.h b/include/linux/pmu.h
index b7824c215354..4c5f65392d36 100644
--- a/include/linux/pmu.h
+++ b/include/linux/pmu.h
@@ -159,41 +159,7 @@ extern void pmu_unlock(void);
159extern int pmu_present(void); 159extern int pmu_present(void);
160extern int pmu_get_model(void); 160extern int pmu_get_model(void);
161 161
162#ifdef CONFIG_PM 162extern void pmu_backlight_set_sleep(int sleep);
163/*
164 * Stuff for putting the powerbook to sleep and waking it again.
165 *
166 */
167#include <linux/list.h>
168
169struct pmu_sleep_notifier
170{
171 void (*notifier_call)(struct pmu_sleep_notifier *self, int when);
172 int priority;
173 struct list_head list;
174};
175
176/* Code values for calling sleep/wakeup handlers
177 */
178#define PBOOK_SLEEP_REQUEST 1
179#define PBOOK_SLEEP_NOW 2
180#define PBOOK_WAKE 3
181
182/* priority levels in notifiers */
183#define SLEEP_LEVEL_VIDEO 100 /* Video driver (first wake) */
184#define SLEEP_LEVEL_MEDIABAY 90 /* Media bay driver */
185#define SLEEP_LEVEL_BLOCK 80 /* IDE, SCSI */
186#define SLEEP_LEVEL_NET 70 /* bmac, gmac */
187#define SLEEP_LEVEL_MISC 60 /* Anything else */
188#define SLEEP_LEVEL_USERLAND 55 /* Reserved for apm_emu */
189#define SLEEP_LEVEL_ADB 50 /* ADB (async) */
190#define SLEEP_LEVEL_SOUND 40 /* Sound driver (blocking) */
191
192/* special register notifier functions */
193int pmu_register_sleep_notifier(struct pmu_sleep_notifier* notifier);
194int pmu_unregister_sleep_notifier(struct pmu_sleep_notifier* notifier);
195
196#endif /* CONFIG_PM */
197 163
198#define PMU_MAX_BATTERIES 2 164#define PMU_MAX_BATTERIES 2
199 165
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 19:53:11 -0500