1 files changed, 2 insertions, 14 deletions
diff --git a/include/asm-parisc/serial.h b/include/asm-parisc/serial.h
index 82fd820d684f..d7e3cc60dbc3 100644
--- a/include/asm-parisc/serial.h
+++ b/include/asm-parisc/serial.h
@@ -3,20 +3,8 @@
 */
 /*
- * This assumes you have a 7.272727 MHz clock for your UART.
+ * This is used for 16550-compatible UARTs
- * The documentation implies a 40Mhz clock, and elsewhere a 7Mhz clock
- * Clarified: 7.2727MHz on LASI. Not yet clarified for DINO
 */
+#define BASE_BAUD ( 1843200 / 16 )
-#define LASI_BASE_BAUD ( 7272727 / 16 )
-#define BASE_BAUD  LASI_BASE_BAUD
-/*
- * We don't use the ISA probing code, so these entries are just to reserve
- * space.  Some example (maximal) configurations:
- * - 712 w/ additional Lasi & RJ16 ports: 4
- * - J5k w/ PCI serial cards: 2 + 4 * card ~= 34
- * A500 w/ PCI serial cards: 5 + 4 * card ~= 17
- */
- 
 #define SERIAL_PORT_DFNS

diff --git a/include/asm-parisc/serial.h b/include/asm-parisc/serial.h index 82fd820d684f..d7e3cc60dbc3 100644 --- a/include/asm-parisc/serial.h +++ b/include/asm-parisc/serial.h
@@ -3,20 +3,8 @@
3	*/	3	*/
4		4
5	/*	5	/*
6	* This assumes you have a 7.272727 MHz clock for your UART.	6	* This is used for 16550-compatible UARTs
7	* The documentation implies a 40Mhz clock, and elsewhere a 7Mhz clock
8	* Clarified: 7.2727MHz on LASI. Not yet clarified for DINO
9	*/	7	*/
		8	#define BASE_BAUD ( 1843200 / 16 )
10		9
11	#define LASI_BASE_BAUD ( 7272727 / 16 )
12	#define BASE_BAUD LASI_BASE_BAUD
13
14	/*
15	* We don't use the ISA probing code, so these entries are just to reserve
16	* space. Some example (maximal) configurations:
17	* - 712 w/ additional Lasi & RJ16 ports: 4
18	* - J5k w/ PCI serial cards: 2 + 4 * card ~= 34
19	* A500 w/ PCI serial cards: 5 + 4 * card ~= 17
20	*/
21
22	#define SERIAL_PORT_DFNS	10	#define SERIAL_PORT_DFNS