70 files changed, 1106 insertions, 909 deletions
diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h
index f681e675b823..4e115f368d5f 100644
--- a/include/asm-alpha/pci.h
+++ b/include/asm-alpha/pci.h
@@ -254,6 +254,19 @@ extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
                                    struct pci_bus_region *region);
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        return root;
+}
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 72b04d846a23..cf35721cfa45 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -44,24 +44,12 @@
 #ifndef __ASSEMBLY__
-#if 0
+# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
-# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
-#else
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-#include <asm/types.h>
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)       __REGP(io_p2v(x))
-#endif
 /* With indexed regs we don't want to feed the index through io_p2v()
   especially if it is a variable, otherwise horrible code will result. */
-# define __REG2(x,y)     (*(volatile u32 *)((u32)&__REG(x) + (y)))
+# define __REG2(x,y)    \
+        (*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
 # define __PREG(x)      (io_v2p((u32)&(x)))
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h
new file mode 100644
index 000000000000..46ec2243974a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/i2c.h
@@ -0,0 +1,70 @@
+/*
+ *  i2c_pxa.h
+ *
+ *  Copyright (C) 2002 Intrinsyc Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#ifndef _I2C_PXA_H_
+#define _I2C_PXA_H_
+#if 0
+#define DEF_TIMEOUT             3
+#else
+/* need a longer timeout if we're dealing with the fact we may well be
+ * looking at a multi-master environment
+*/
+#define DEF_TIMEOUT             32
+#endif
+#define BUS_ERROR               (-EREMOTEIO)
+#define XFER_NAKED              (-ECONNREFUSED)
+#define I2C_RETRY               (-2000) /* an error has occurred retry transmit */
+/* ICR initialize bit values
+*
+*  15. FM       0 (100 Khz operation)
+*  14. UR       0 (No unit reset)
+*  13. SADIE    0 (Disables the unit from interrupting on slave addresses
+*                                       matching its slave address)
+*  12. ALDIE    0 (Disables the unit from interrupt when it loses arbitration
+*                                       in master mode)
+*  11. SSDIE    0 (Disables interrupts from a slave stop detected, in slave mode)
+*  10. BEIE     1 (Enable interrupts from detected bus errors, no ACK sent)
+*  9.  IRFIE    1 (Enable interrupts from full buffer received)
+*  8.  ITEIE    1 (Enables the I2C unit to interrupt when transmit buffer empty)
+*  7.  GCD      1 (Disables i2c unit response to general call messages as a slave)
+*  6.  IUE      0 (Disable unit until we change settings)
+*  5.  SCLE     1 (Enables the i2c clock output for master mode (drives SCL)
+*  4.  MA       0 (Only send stop with the ICR stop bit)
+*  3.  TB       0 (We are not transmitting a byte initially)
+*  2.  ACKNAK   0 (Send an ACK after the unit receives a byte)
+*  1.  STOP     0 (Do not send a STOP)
+*  0.  START    0 (Do not send a START)
+*
+*/
+#define I2C_ICR_INIT    (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+/* I2C status register init values
+ *
+ * 10. BED      1 (Clear bus error detected)
+ * 9.  SAD      1 (Clear slave address detected)
+ * 7.  IRF      1 (Clear IDBR Receive Full)
+ * 6.  ITE      1 (Clear IDBR Transmit Empty)
+ * 5.  ALD      1 (Clear Arbitration Loss Detected)
+ * 4.  SSD      1 (Clear Slave Stop Detected)
+ */
+#define I2C_ISR_INIT    0x7FF  /* status register init */
+struct i2c_slave_client;
+struct i2c_pxa_platform_data {
+        unsigned int            slave_addr;
+        struct i2c_slave_client *slave;
+};
+extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
+#endif
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index 9718063a2119..88c17dd02ed2 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -9,6 +9,7 @@ struct mmc_host;
 struct pxamci_platform_data {
        unsigned int ocr_mask;                  /* available voltages */
+        unsigned long detect_delay;             /* delay in jiffies before detecting cards after interrupt */
        int (*init)(struct device *, irqreturn_t (*)(int, void *, struct pt_regs *), void *);
        int (*get_ro)(struct device *);
        void (*setpower)(struct device *, unsigned int);
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index 10c62db34362..19c3b1e186bb 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -49,23 +49,9 @@
   ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 #ifndef __ASSEMBLY__
-#include <asm/types.h>
-#if 0
+# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
-# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
+# define __PREG(x)      (io_v2p((unsigned long)&(x)))
-#else
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)       __REGP(io_p2v(x))
-#endif
-# define __PREG(x)      (io_v2p((u32)&(x)))
 #else
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 035cdcff43d2..e81baff4f54b 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -256,7 +256,7 @@ extern void dmac_flush_range(unsigned long, unsigned long);
 * Convert calls to our calling convention.
 */
 #define flush_cache_all()               __cpuc_flush_kern_all()
+#ifndef CONFIG_CPU_CACHE_VIPT
 static inline void flush_cache_mm(struct mm_struct *mm)
 {
        if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
@@ -279,6 +279,11 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned l
                __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
        }
 }
+#else
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
+#endif
 /*
 * flush_cache_user_range is used when we want to ensure that the
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index 38ea5899a580..ead3ced38cb8 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -64,6 +64,19 @@ extern void
 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
                        struct pci_bus_region *region);
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        return root;
+}
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h
index ee1d8b5d8168..c36a77d3bf44 100644
--- a/include/asm-generic/pci.h
+++ b/include/asm-generic/pci.h
@@ -30,6 +30,19 @@ pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
        res->end = region->end;
 }
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        return root;
+}
 #define pcibios_scan_all_fns(a, b)      0
 #ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h
index a429fe225b07..20f98f1751a1 100644
--- a/include/asm-ia64/iosapic.h
+++ b/include/asm-ia64/iosapic.h
@@ -80,12 +80,9 @@ extern int iosapic_remove (unsigned int gsi_base);
 #endif /* CONFIG_HOTPLUG */
 extern int gsi_to_vector (unsigned int gsi);
 extern int gsi_to_irq (unsigned int gsi);
-extern void iosapic_enable_intr (unsigned int vector);
 extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
                                  unsigned long trigger);
-#ifdef CONFIG_ACPI_DEALLOCATE_IRQ
 extern void iosapic_unregister_intr (unsigned int irq);
-#endif
 extern void __init iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
                                      unsigned long polarity,
                                      unsigned long trigger);
@@ -97,7 +94,6 @@ extern int __init iosapic_register_platform_intr (u32 int_type,
                                           unsigned long trigger);
 extern unsigned int iosapic_version (char __iomem *addr);
-extern void iosapic_pci_fixup (int);
 #ifdef CONFIG_NUMA
 extern void __devinit map_iosapic_to_node (unsigned int, int);
 #endif
diff --git a/include/asm-ia64/irq.h b/include/asm-ia64/irq.h
index cd984d08fd15..dbe86c0bbce5 100644
--- a/include/asm-ia64/irq.h
+++ b/include/asm-ia64/irq.h
@@ -35,8 +35,4 @@ extern void disable_irq_nosync (unsigned int);
 extern void enable_irq (unsigned int);
 extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
-struct irqaction;
-struct pt_regs;
-int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
 #endif /* _ASM_IA64_IRQ_H */
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
index dba9f220be71..ef616fd4cb1b 100644
--- a/include/asm-ia64/pci.h
+++ b/include/asm-ia64/pci.h
@@ -156,6 +156,19 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev,
 extern void pcibios_bus_to_resource(struct pci_dev *dev,
                struct resource *res, struct pci_bus_region *region);
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        return root;
+}
 #define pcibios_scan_all_fns(a, b)      0
 #endif /* _ASM_IA64_PCI_H */
diff --git a/include/asm-m68knommu/coldfire.h b/include/asm-m68knommu/coldfire.h
index 16f32cc80c40..1df3f666a28e 100644
--- a/include/asm-m68knommu/coldfire.h
+++ b/include/asm-m68knommu/coldfire.h
@@ -22,7 +22,7 @@
 #define MCF_MBAR2       0x80000000
 #define MCF_IPSBAR      0x40000000
-#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
+#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
 #undef MCF_MBAR
 #define MCF_MBAR        MCF_IPSBAR
 #endif
@@ -54,6 +54,8 @@
 #define MCF_CLK         54000000
 #elif defined(CONFIG_CLOCK_60MHz)
 #define MCF_CLK         60000000
+#elif defined(CONFIG_CLOCK_62_5MHz)
+#define MCF_CLK         62500000
 #elif defined(CONFIG_CLOCK_64MHz)
 #define MCF_CLK         64000000
 #elif defined(CONFIG_CLOCK_66MHz)
@@ -76,7 +78,7 @@
 *      One some ColdFire family members the bus clock (used by internal
 *      peripherals) is not the same as the CPU clock.
 */
-#if defined(CONFIG_M5249) || defined(CONFIG_M527x)
+#if defined(CONFIG_M523x) || defined(CONFIG_M5249) || defined(CONFIG_M527x)
 #define MCF_BUSCLK      (MCF_CLK / 2)
 #else
 #define MCF_BUSCLK      MCF_CLK
diff --git a/include/asm-m68knommu/m523xsim.h b/include/asm-m68knommu/m523xsim.h
new file mode 100644
index 000000000000..926cfb805df7
--- /dev/null
+++ b/include/asm-m68knommu/m523xsim.h
@@ -0,0 +1,46 @@
+/****************************************************************************/
+/*
+ *      m523xsim.h -- ColdFire 523x System Integration Module support.
+ *
+ *      (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
+ */
+/****************************************************************************/
+#ifndef m523xsim_h
+#define m523xsim_h
+/****************************************************************************/
+#include <linux/config.h>
+/*
+ *      Define the 523x SIM register set addresses.
+ */
+#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 0 */
+#define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL            0x0c            /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH         0x10            /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL         0x14            /* Interrupt force 1-31 */
+#define MCFINTC_IRLR            0x18            /* */
+#define MCFINTC_IACKL           0x19            /* */
+#define MCFINTC_ICR0            0x40            /* Base ICR register */
+#define MCFINT_VECBASE          64              /* Vector base number */
+#define MCFINT_UART0            13              /* Interrupt number for UART0 */
+#define MCFINT_PIT1             36              /* Interrupt number for PIT1 */
+#define MCFINT_QSPI             18              /* Interrupt number for QSPI */
+/*
+ *      SDRAM configuration registers.
+ */
+#define MCFSIM_DCR              0x44            /* SDRAM control */
+#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
+#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
+#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
+#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
+/****************************************************************************/
+#endif  /* m523xsim_h */
diff --git a/include/asm-m68knommu/mcfsim.h b/include/asm-m68knommu/mcfsim.h
index 522e513c2bc6..b0c7736f7a99 100644
--- a/include/asm-m68knommu/mcfsim.h
+++ b/include/asm-m68knommu/mcfsim.h
@@ -15,13 +15,15 @@
 #include <linux/config.h>
 /*
- *      Include 5204, 5206/e, 5249, 5270/5271, 5272, 5280/5282, 5307 or
+ *      Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282,
- *      5407 specific addresses.
+ *      5307 or 5407 specific addresses.
 */
 #if defined(CONFIG_M5204)
 #include <asm/m5204sim.h>
 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
 #include <asm/m5206sim.h>
+#elif defined(CONFIG_M523x)
+#include <asm/m523xsim.h>
 #elif defined(CONFIG_M5249)
 #include <asm/m5249sim.h>
 #elif defined(CONFIG_M527x)
diff --git a/include/asm-m68knommu/mcfuart.h b/include/asm-m68knommu/mcfuart.h
index 54d4a85f4fdf..9c1210613bc7 100644
--- a/include/asm-m68knommu/mcfuart.h
+++ b/include/asm-m68knommu/mcfuart.h
@@ -29,7 +29,7 @@
 #define MCFUART_BASE1           0x140           /* Base address of UART1 */
 #define MCFUART_BASE2           0x180           /* Base address of UART2 */
 #endif
-#elif defined(CONFIG_M527x) || defined(CONFIG_M528x)
+#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
 #define MCFUART_BASE1           0x200           /* Base address of UART1 */
 #define MCFUART_BASE2           0x240           /* Base address of UART2 */
 #define MCFUART_BASE3           0x280           /* Base address of UART3 */
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index 98d79a3d54fa..d0b761f690b5 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -257,6 +257,19 @@ extern void
 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
                        struct pci_bus_region *region);
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        return root;
+}
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-powerpc/8253pit.h b/include/asm-powerpc/8253pit.h
index 862708a749b0..b70d6e53b303 100644
--- a/include/asm-powerpc/8253pit.h
+++ b/include/asm-powerpc/8253pit.h
@@ -1,10 +1,10 @@
+#ifndef _ASM_POWERPC_8253PIT_H
+#define _ASM_POWERPC_8253PIT_H
 /*
 * 8253/8254 Programmable Interval Timer
 */
-#ifndef _8253PIT_H
-#define _8253PIT_H
 #define PIT_TICK_RATE   1193182UL
-#endif
+#endif  /* _ASM_POWERPC_8253PIT_H */
diff --git a/include/asm-powerpc/agp.h b/include/asm-powerpc/agp.h
index ca9e423307f4..885b4631a6cf 100644
--- a/include/asm-powerpc/agp.h
+++ b/include/asm-powerpc/agp.h
@@ -1,10 +1,8 @@
-#ifndef AGP_H
+#ifndef _ASM_POWERPC_AGP_H
-#define AGP_H 1
+#define _ASM_POWERPC_AGP_H
 #include <asm/io.h>
-/* nothing much needed here */
 #define map_page_into_agp(page)
 #define unmap_page_from_agp(page)
 #define flush_agp_mappings()
@@ -20,4 +18,4 @@
 #define free_gatt_pages(table, order)   \
        free_pages((unsigned long)(table), (order))
-#endif
+#endif  /* _ASM_POWERPC_AGP_H */
diff --git a/include/asm-powerpc/bugs.h b/include/asm-powerpc/bugs.h
index 310187d0e33a..42fdb73e3068 100644
--- a/include/asm-powerpc/bugs.h
+++ b/include/asm-powerpc/bugs.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_BUGS_H
+#ifndef _ASM_POWERPC_BUGS_H
-#define _POWERPC_BUGS_H
+#define _ASM_POWERPC_BUGS_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -13,6 +13,6 @@
 * architecture-dependent bugs.
 */
-extern void check_bugs(void);
+static inline void check_bugs(void) { }
-#endif /* _POWERPC_BUGS_H */
+#endif  /* _ASM_POWERPC_BUGS_H */
diff --git a/include/asm-powerpc/errno.h b/include/asm-powerpc/errno.h
index 19f20bd41ae6..8c145fd17d86 100644
--- a/include/asm-powerpc/errno.h
+++ b/include/asm-powerpc/errno.h
@@ -1,5 +1,5 @@
-#ifndef _PPC_ERRNO_H
+#ifndef _ASM_POWERPC_ERRNO_H
-#define _PPC_ERRNO_H
+#define _ASM_POWERPC_ERRNO_H
 #include <asm-generic/errno.h>
@@ -8,4 +8,4 @@
 #define _LAST_ERRNO     516
-#endif
+#endif  /* _ASM_POWERPC_ERRNO_H */
diff --git a/include/asm-powerpc/ioctl.h b/include/asm-powerpc/ioctl.h
index 93c6acfdd0fd..8eb99848c402 100644
--- a/include/asm-powerpc/ioctl.h
+++ b/include/asm-powerpc/ioctl.h
@@ -1,5 +1,5 @@
-#ifndef _PPC_IOCTL_H
+#ifndef _ASM_POWERPC_IOCTL_H
-#define _PPC_IOCTL_H
+#define _ASM_POWERPC_IOCTL_H
 /*
@@ -66,4 +66,4 @@ extern unsigned int __invalid_size_argument_for_IOC;
 #define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
 #define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
-#endif
+#endif  /* _ASM_POWERPC_IOCTL_H */
diff --git a/include/asm-powerpc/ioctls.h b/include/asm-powerpc/ioctls.h
index f5b7f2b055e7..5b94ff489b8b 100644
--- a/include/asm-powerpc/ioctls.h
+++ b/include/asm-powerpc/ioctls.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_PPC_IOCTLS_H
+#ifndef _ASM_POWERPC_IOCTLS_H
-#define _ASM_PPC_IOCTLS_H
+#define _ASM_POWERPC_IOCTLS_H
 #include <asm/ioctl.h>
@@ -104,4 +104,4 @@
 #define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
 #define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-#endif /* _ASM_PPC_IOCTLS_H */
+#endif  /* _ASM_POWERPC_IOCTLS_H */
diff --git a/include/asm-powerpc/linkage.h b/include/asm-powerpc/linkage.h
index 291c2d01c44f..e1c4ac1cc4ba 100644
--- a/include/asm-powerpc/linkage.h
+++ b/include/asm-powerpc/linkage.h
@@ -1,6 +1,6 @@
-#ifndef __ASM_LINKAGE_H
+#ifndef _ASM_POWERPC_LINKAGE_H
-#define __ASM_LINKAGE_H
+#define _ASM_POWERPC_LINKAGE_H
 /* Nothing to see here... */
-#endif
+#endif  /* _ASM_POWERPC_LINKAGE_H */
diff --git a/include/asm-powerpc/mc146818rtc.h b/include/asm-powerpc/mc146818rtc.h
index a5619a2a1393..f2741c8b59a1 100644
--- a/include/asm-powerpc/mc146818rtc.h
+++ b/include/asm-powerpc/mc146818rtc.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_MC146818RTC_H
+#ifndef _ASM_POWERPC_MC146818RTC_H
-#define _POWERPC_MC146818RTC_H
+#define _ASM_POWERPC_MC146818RTC_H
 /*
 * Machine dependent access functions for RTC registers.
@@ -33,4 +33,4 @@ outb_p((val),RTC_PORT(1)); \
 })
 #endif  /* __KERNEL__ */
-#endif  /* _POWERPC_MC146818RTC_H */
+#endif  /* _ASM_POWERPC_MC146818RTC_H */
diff --git a/include/asm-powerpc/mman.h b/include/asm-powerpc/mman.h
index f2d55988d749..f5e5342fcac5 100644
--- a/include/asm-powerpc/mman.h
+++ b/include/asm-powerpc/mman.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_MMAN_H
+#ifndef _ASM_POWERPC_MMAN_H
-#define _POWERPC_MMAN_H
+#define _ASM_POWERPC_MMAN_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -49,4 +49,4 @@
 #define MAP_ANON        MAP_ANONYMOUS
 #define MAP_FILE        0
-#endif /* _POWERPC_MMAN_H */
+#endif  /* _ASM_POWERPC_MMAN_H */
diff --git a/include/asm-powerpc/module.h b/include/asm-powerpc/module.h
index 4438f4fd6524..7ecd05e03051 100644
--- a/include/asm-powerpc/module.h
+++ b/include/asm-powerpc/module.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_MODULE_H
+#ifndef _ASM_POWERPC_MODULE_H
-#define _POWERPC_MODULE_H
+#define _ASM_POWERPC_MODULE_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -74,4 +74,4 @@ struct exception_table_entry;
 void sort_ex_table(struct exception_table_entry *start,
                   struct exception_table_entry *finish);
-#endif /* _POWERPC_MODULE_H */
+#endif  /* _ASM_POWERPC_MODULE_H */
diff --git a/include/asm-ppc/msgbuf.h b/include/asm-powerpc/msgbuf.h
index 1053452a9376..dd76743c7537 100644
--- a/include/asm-ppc/msgbuf.h
+++ b/include/asm-powerpc/msgbuf.h
@@ -1,17 +1,25 @@
-#ifndef _PPC_MSGBUF_H
+#ifndef _ASM_POWERPC_MSGBUF_H
-#define _PPC_MSGBUF_H
+#define _ASM_POWERPC_MSGBUF_H
 /*
- * The msqid64_ds structure for the PPC architecture.
+ * The msqid64_ds structure for the PowerPC architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
 */
 struct msqid64_ds {
        struct ipc64_perm msg_perm;
+#ifndef __powerpc64__
        unsigned int    __unused1;
+#endif
        __kernel_time_t msg_stime;      /* last msgsnd time */
+#ifndef __powerpc64__
        unsigned int    __unused2;
+#endif
        __kernel_time_t msg_rtime;      /* last msgrcv time */
+#ifndef __powerpc64__
        unsigned int    __unused3;
+#endif
        __kernel_time_t msg_ctime;      /* last change time */
        unsigned long  msg_cbytes;      /* current number of bytes on queue */
        unsigned long  msg_qnum;        /* number of messages in queue */
@@ -22,4 +30,4 @@ struct msqid64_ds {
        unsigned long  __unused5;
 };
-#endif /* _PPC_MSGBUF_H */
+#endif  /* _ASM_POWERPC_MSGBUF_H */
diff --git a/include/asm-powerpc/namei.h b/include/asm-powerpc/namei.h
index 29c9ec832133..657443474a6a 100644
--- a/include/asm-powerpc/namei.h
+++ b/include/asm-powerpc/namei.h
@@ -1,14 +1,14 @@
+#ifndef _ASM_POWERPC_NAMEI_H
+#define _ASM_POWERPC_NAMEI_H
+#ifdef __KERNEL__
 /*
- * include/asm-ppc/namei.h
 * Adapted from include/asm-alpha/namei.h
 *
 * Included from fs/namei.c
 */
-#ifdef __KERNEL__
-#ifndef __PPC_NAMEI_H
-#define __PPC_NAMEI_H
 /* This dummy routine maybe changed to something useful
 * for /usr/gnemul/ emulation stuff.
 * Look at asm-sparc/namei.h for details.
@@ -16,5 +16,5 @@
 #define __emul_prefix() NULL
-#endif /* __PPC_NAMEI_H */
+#endif  /* __KERNEL__ */
-#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_NAMEI_H */
diff --git a/include/asm-ppc/param.h b/include/asm-powerpc/param.h
index 6198b1657a45..bdc724f70884 100644
--- a/include/asm-ppc/param.h
+++ b/include/asm-powerpc/param.h
@@ -1,10 +1,10 @@
-#ifndef _ASM_PPC_PARAM_H
+#ifndef _ASM_POWERPC_PARAM_H
-#define _ASM_PPC_PARAM_H
+#define _ASM_POWERPC_PARAM_H
 #include <linux/config.h>
 #ifdef __KERNEL__
-#define HZ              CONFIG_HZ       /* internal timer frequency */
+#define HZ              CONFIG_HZ       /* internal kernel timer frequency */
 #define USER_HZ         100             /* for user interfaces in "ticks" */
 #define CLOCKS_PER_SEC  (USER_HZ)       /* frequency at which times() counts */
 #endif /* __KERNEL__ */
@@ -21,4 +21,4 @@
 #define MAXHOSTNAMELEN  64      /* max length of hostname */
-#endif
+#endif  /* _ASM_POWERPC_PARAM_H */
diff --git a/include/asm-powerpc/poll.h b/include/asm-powerpc/poll.h
index be5024913c62..edd2054da86b 100644
--- a/include/asm-powerpc/poll.h
+++ b/include/asm-powerpc/poll.h
@@ -1,5 +1,5 @@
-#ifndef __PPC_POLL_H
+#ifndef _ASM_POWERPC_POLL_H
-#define __PPC_POLL_H
+#define _ASM_POWERPC_POLL_H
 #define POLLIN          0x0001
 #define POLLPRI         0x0002
@@ -20,4 +20,4 @@ struct pollfd {
        short revents;
 };
-#endif
+#endif  /* _ASM_POWERPC_POLL_H */
diff --git a/include/asm-powerpc/sembuf.h b/include/asm-powerpc/sembuf.h
index c98fc18fe805..99a41938ae3d 100644
--- a/include/asm-powerpc/sembuf.h
+++ b/include/asm-powerpc/sembuf.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_SEMBUF_H
+#ifndef _ASM_POWERPC_SEMBUF_H
-#define _POWERPC_SEMBUF_H
+#define _ASM_POWERPC_SEMBUF_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -33,4 +33,4 @@ struct semid64_ds {
        unsigned long   __unused4;
 };
-#endif /* _POWERPC_SEMBUF_H */
+#endif  /* _ASM_POWERPC_SEMBUF_H */
diff --git a/include/asm-powerpc/setup.h b/include/asm-powerpc/setup.h
new file mode 100644
index 000000000000..3d9740aae018
--- /dev/null
+++ b/include/asm-powerpc/setup.h
@@ -0,0 +1,9 @@
+#ifndef _ASM_POWERPC_SETUP_H
+#define _ASM_POWERPC_SETUP_H
+#ifdef __KERNEL__
+#define COMMAND_LINE_SIZE       512
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_SETUP_H */
diff --git a/include/asm-powerpc/shmbuf.h b/include/asm-powerpc/shmbuf.h
index 29632db3b178..8efa39698b6c 100644
--- a/include/asm-powerpc/shmbuf.h
+++ b/include/asm-powerpc/shmbuf.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_SHMBUF_H
+#ifndef _ASM_POWERPC_SHMBUF_H
-#define _POWERPC_SHMBUF_H
+#define _ASM_POWERPC_SHMBUF_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -21,19 +21,19 @@
 struct shmid64_ds {
        struct ipc64_perm       shm_perm;       /* operation perms */
-#ifndef __power64__
+#ifndef __powerpc64__
        unsigned long           __unused1;
 #endif
        __kernel_time_t         shm_atime;      /* last attach time */
-#ifndef __power64__
+#ifndef __powerpc64__
        unsigned long           __unused2;
 #endif
        __kernel_time_t         shm_dtime;      /* last detach time */
-#ifndef __power64__
+#ifndef __powerpc64__
        unsigned long           __unused3;
 #endif
        __kernel_time_t         shm_ctime;      /* last change time */
-#ifndef __power64__
+#ifndef __powerpc64__
        unsigned long           __unused4;
 #endif
        size_t                  shm_segsz;      /* size of segment (bytes) */
@@ -56,4 +56,4 @@ struct shminfo64 {
        unsigned long   __unused4;
 };
-#endif /* _POWERPC_SHMBUF_H */
+#endif  /* _ASM_POWERPC_SHMBUF_H */
diff --git a/include/asm-powerpc/shmparam.h b/include/asm-powerpc/shmparam.h
index d6250602ae64..5cda42a6d39e 100644
--- a/include/asm-powerpc/shmparam.h
+++ b/include/asm-powerpc/shmparam.h
@@ -1,6 +1,6 @@
-#ifndef _PPC_SHMPARAM_H
+#ifndef _ASM_POWERPC_SHMPARAM_H
-#define _PPC_SHMPARAM_H
+#define _ASM_POWERPC_SHMPARAM_H
 #define SHMLBA PAGE_SIZE                 /* attach addr a multiple of this */
-#endif /* _PPC_SHMPARAM_H */
+#endif  /* _ASM_POWERPC_SHMPARAM_H */
diff --git a/include/asm-powerpc/siginfo.h b/include/asm-powerpc/siginfo.h
index ae70b8010b19..538ea8ef509b 100644
--- a/include/asm-powerpc/siginfo.h
+++ b/include/asm-powerpc/siginfo.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_SIGINFO_H
+#ifndef _ASM_POWERPC_SIGINFO_H
-#define _POWERPC_SIGINFO_H
+#define _ASM_POWERPC_SIGINFO_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -15,4 +15,4 @@
 #include <asm-generic/siginfo.h>
-#endif /* _POWERPC_SIGINFO_H */
+#endif  /* _ASM_POWERPC_SIGINFO_H */
diff --git a/include/asm-powerpc/socket.h b/include/asm-powerpc/socket.h
index 51a0cf5ee9f0..e4b8177d4acc 100644
--- a/include/asm-powerpc/socket.h
+++ b/include/asm-powerpc/socket.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_SOCKET_H
+#ifndef _ASM_POWERPC_SOCKET_H
-#define _POWERPC_SOCKET_H
+#define _ASM_POWERPC_SOCKET_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -56,4 +56,4 @@
 #define SO_PEERSEC              31
-#endif /* _POWERPC_SOCKET_H */
+#endif  /* _ASM_POWERPC_SOCKET_H */
diff --git a/include/asm-powerpc/sockios.h b/include/asm-powerpc/sockios.h
index ef7ff664167e..590078d8ed28 100644
--- a/include/asm-powerpc/sockios.h
+++ b/include/asm-powerpc/sockios.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_SOCKIOS_H
+#ifndef _ASM_POWERPC_SOCKIOS_H
-#define _POWERPC_SOCKIOS_H
+#define _ASM_POWERPC_SOCKIOS_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -16,4 +16,4 @@
 #define SIOCATMARK      0x8905
 #define SIOCGSTAMP      0x8906          /* Get stamp */
-#endif /* _POWERPC_SOCKIOS_H */
+#endif  /* _ASM_POWERPC_SOCKIOS_H */
diff --git a/include/asm-powerpc/string.h b/include/asm-powerpc/string.h
index 225575997392..8606a696c088 100644
--- a/include/asm-powerpc/string.h
+++ b/include/asm-powerpc/string.h
@@ -1,5 +1,5 @@
-#ifndef _PPC_STRING_H_
+#ifndef _ASM_POWERPC_STRING_H
-#define _PPC_STRING_H_
+#define _ASM_POWERPC_STRING_H
 #ifdef __KERNEL__
@@ -29,4 +29,4 @@ extern void * memchr(const void *,int,__kernel_size_t);
 #endif /* __KERNEL__ */
-#endif
+#endif  /* _ASM_POWERPC_STRING_H */
diff --git a/include/asm-powerpc/termbits.h b/include/asm-powerpc/termbits.h
index 2c5bf85a8c3c..ebf6055481dc 100644
--- a/include/asm-powerpc/termbits.h
+++ b/include/asm-powerpc/termbits.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_TERMBITS_H
+#ifndef _ASM_POWERPC_TERMBITS_H
-#define _POWERPC_TERMBITS_H
+#define _ASM_POWERPC_TERMBITS_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -188,4 +188,4 @@ struct termios {
 #define TCSADRAIN       1
 #define TCSAFLUSH       2
-#endif /* _POWERPC_TERMBITS_H */
+#endif  /* _ASM_POWERPC_TERMBITS_H */
diff --git a/include/asm-powerpc/termios.h b/include/asm-powerpc/termios.h
index 237533bb0e9f..c5b8e5358f83 100644
--- a/include/asm-powerpc/termios.h
+++ b/include/asm-powerpc/termios.h
@@ -1,5 +1,5 @@
-#ifndef _POWERPC_TERMIOS_H
+#ifndef _ASM_POWERPC_TERMIOS_H
-#define _POWERPC_TERMIOS_H
+#define _ASM_POWERPC_TERMIOS_H
 /*
 * Liberally adapted from alpha/termios.h.  In particular, the c_cc[]
@@ -233,4 +233,4 @@ struct termio {
 #endif  /* __KERNEL__ */
-#endif  /* _POWERPC_TERMIOS_H */
+#endif  /* _ASM_POWERPC_TERMIOS_H */
diff --git a/include/asm-ppc/timex.h b/include/asm-powerpc/timex.h
index cffc8712077c..51c5b316be55 100644
--- a/include/asm-ppc/timex.h
+++ b/include/asm-powerpc/timex.h
@@ -1,11 +1,11 @@
+#ifndef _ASM_POWERPC_TIMEX_H
+#define _ASM_POWERPC_TIMEX_H
+#ifdef __KERNEL__
 /*
- * include/asm-ppc/timex.h
+ * PowerPC architecture timex specifications
- *
- * ppc architecture timex specifications
 */
-#ifdef __KERNEL__
-#ifndef _ASMppc_TIMEX_H
-#define _ASMppc_TIMEX_H
 #include <linux/config.h>
 #include <asm/cputable.h>
@@ -14,14 +14,21 @@
 typedef unsigned long cycles_t;
-/*
- * For the "cycle" counter we use the timebase lower half.
- * Currently only used on SMP.
- */
 static inline cycles_t get_cycles(void)
 {
-        cycles_t ret = 0;
+        cycles_t ret;
+#ifdef __powerpc64__
+        __asm__ __volatile__("mftb %0" : "=r" (ret) : );
+#else
+        /*
+         * For the "cycle" counter we use the timebase lower half.
+         * Currently only used on SMP.
+         */
+        ret = 0;
        __asm__ __volatile__(
                "98:    mftb %0\n"
@@ -33,8 +40,10 @@ static inline cycles_t get_cycles(void)
                "       .long 99b\n"
                ".previous"
                : "=r" (ret) : "i" (CPU_FTR_601));
+#endif
        return ret;
 }
-#endif
+#endif  /* __KERNEL__ */
-#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_TIMEX_H */
diff --git a/include/asm-ppc64/topology.h b/include/asm-powerpc/topology.h
index 1e9b19073230..2512e3836bf4 100644
--- a/include/asm-ppc64/topology.h
+++ b/include/asm-powerpc/topology.h
@@ -1,11 +1,12 @@
-#ifndef _ASM_PPC64_TOPOLOGY_H
+#ifndef _ASM_POWERPC_TOPOLOGY_H
-#define _ASM_PPC64_TOPOLOGY_H
+#define _ASM_POWERPC_TOPOLOGY_H
 #include <linux/config.h>
-#include <asm/mmzone.h>
 #ifdef CONFIG_NUMA
+#include <asm/mmzone.h>
 static inline int cpu_to_node(int cpu)
 {
        int node;
@@ -66,4 +67,4 @@ static inline int node_to_first_cpu(int node)
 #endif /* CONFIG_NUMA */
-#endif /* _ASM_PPC64_TOPOLOGY_H */
+#endif  /* _ASM_POWERPC_TOPOLOGY_H */
diff --git a/include/asm-powerpc/unaligned.h b/include/asm-powerpc/unaligned.h
index 45520d9b85d1..6c95dfa2652f 100644
--- a/include/asm-powerpc/unaligned.h
+++ b/include/asm-powerpc/unaligned.h
@@ -1,6 +1,7 @@
+#ifndef _ASM_POWERPC_UNALIGNED_H
+#define _ASM_POWERPC_UNALIGNED_H
 #ifdef __KERNEL__
-#ifndef __PPC_UNALIGNED_H
-#define __PPC_UNALIGNED_H
 /*
 * The PowerPC can do unaligned accesses itself in big endian mode.
@@ -14,5 +15,5 @@
 #define put_unaligned(val, ptr) ((void)( *(ptr) = (val) ))
-#endif
+#endif  /* __KERNEL__ */
-#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_UNALIGNED_H */
diff --git a/include/asm-ppc/user.h b/include/asm-powerpc/user.h
index d662b2151370..e59ade4b3dfb 100644
--- a/include/asm-ppc/user.h
+++ b/include/asm-powerpc/user.h
@@ -1,13 +1,14 @@
-#ifdef __KERNEL__
+#ifndef _ASM_POWERPC_USER_H
-#ifndef _PPC_USER_H
+#define _ASM_POWERPC_USER_H
-#define _PPC_USER_H
-/* Adapted from <asm-alpha/user.h> */
+#ifdef __KERNEL__
-#include <linux/ptrace.h>
+#include <asm/ptrace.h>
 #include <asm/page.h>
 /*
+ * Adapted from <asm-alpha/user.h>
+ *
 * Core file format: The core file is written in such a way that gdb
 * can understand it and provide useful information to the user (under
 * linux we use the `trad-core' bfd, NOT the osf-core).  The file contents
@@ -50,5 +51,5 @@ struct user {
 #define HOST_DATA_START_ADDR    (u.start_data)
 #define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
-#endif /* _PPC_USER_H */
+#endif  /* __KERNEL__ */
-#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_USER_H */
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index a811e440c978..9dd06cd40096 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -109,6 +109,19 @@ extern void
 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
                        struct pci_bus_region *region);
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        return root;
+}
 extern void pcibios_add_platform_entries(struct pci_dev *dev);
 struct file;
diff --git a/include/asm-ppc/setup.h b/include/asm-ppc/setup.h
deleted file mode 100644
index d2d19ee103df..000000000000
--- a/include/asm-ppc/setup.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_SETUP_H
-#define _PPC_SETUP_H
-#define m68k_num_memory num_memory
-#define m68k_memory memory
-#include <asm-m68k/setup.h>
-/* We have a bigger command line buffer. */
-#undef COMMAND_LINE_SIZE
-#define COMMAND_LINE_SIZE       512
-#endif /* _PPC_SETUP_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/topology.h b/include/asm-ppc/topology.h
deleted file mode 100644
index 6a029bbba6e1..000000000000
--- a/include/asm-ppc/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_PPC_TOPOLOGY_H
-#define _ASM_PPC_TOPOLOGY_H
-#include <asm-generic/topology.h>
-#endif /* _ASM_PPC_TOPOLOGY_H */
diff --git a/include/asm-ppc64/eeh.h b/include/asm-ppc64/eeh.h
index 94298b106a4b..40c8eb57493e 100644
--- a/include/asm-ppc64/eeh.h
+++ b/include/asm-ppc64/eeh.h
@@ -219,23 +219,24 @@ static inline void eeh_raw_writeq(u64 val, volatile void __iomem *addr)
 static inline void eeh_memset_io(volatile void __iomem *addr, int c,
                                 unsigned long n)
 {
+        void *p = (void __force *)addr;
        u32 lc = c;
        lc |= lc << 8;
        lc |= lc << 16;
-        while(n && !EEH_CHECK_ALIGN(addr, 4)) {
+        while(n && !EEH_CHECK_ALIGN(p, 4)) {
-                *((volatile u8 *)addr) = c;
+                *((volatile u8 *)p) = c;
-                addr = (void *)((unsigned long)addr + 1);
+                p++;
                n--;
        }
        while(n >= 4) {
-                *((volatile u32 *)addr) = lc;
+                *((volatile u32 *)p) = lc;
-                addr = (void *)((unsigned long)addr + 4);
+                p += 4;
                n -= 4;
        }
        while(n) {
-                *((volatile u8 *)addr) = c;
+                *((volatile u8 *)p) = c;
-                addr = (void *)((unsigned long)addr + 1);
+                p++;
                n--;
        }
        __asm__ __volatile__ ("sync" : : : "memory");
@@ -250,22 +251,22 @@ static inline void eeh_memcpy_fromio(void *dest, const volatile void __iomem *sr
        while(n && (!EEH_CHECK_ALIGN(vsrc, 4) || !EEH_CHECK_ALIGN(dest, 4))) {
                *((u8 *)dest) = *((volatile u8 *)vsrc);
                __asm__ __volatile__ ("eieio" : : : "memory");
-                vsrc = (void *)((unsigned long)vsrc + 1);
+                vsrc++;
-                dest = (void *)((unsigned long)dest + 1);                       
+                dest++;
                n--;
        }
        while(n > 4) {
                *((u32 *)dest) = *((volatile u32 *)vsrc);
                __asm__ __volatile__ ("eieio" : : : "memory");
-                vsrc = (void *)((unsigned long)vsrc + 4);
+                vsrc += 4;
-                dest = (void *)((unsigned long)dest + 4);                       
+                dest += 4;
                n -= 4;
        }
        while(n) {
                *((u8 *)dest) = *((volatile u8 *)vsrc);
                __asm__ __volatile__ ("eieio" : : : "memory");
-                vsrc = (void *)((unsigned long)vsrc + 1);
+                vsrc++;
-                dest = (void *)((unsigned long)dest + 1);                       
+                dest++;
                n--;
        }
        __asm__ __volatile__ ("sync" : : : "memory");
@@ -286,20 +287,20 @@ static inline void eeh_memcpy_toio(volatile void __iomem *dest, const void *src,
        while(n && (!EEH_CHECK_ALIGN(vdest, 4) || !EEH_CHECK_ALIGN(src, 4))) {
                *((volatile u8 *)vdest) = *((u8 *)src);
-                src = (void *)((unsigned long)src + 1);
+                src++;
-                vdest = (void *)((unsigned long)vdest + 1);                     
+                vdest++;
                n--;
        }
        while(n > 4) {
                *((volatile u32 *)vdest) = *((volatile u32 *)src);
-                src = (void *)((unsigned long)src + 4);
+                src += 4;
-                vdest = (void *)((unsigned long)vdest + 4);                     
+                vdest += 4;
                n-=4;
        }
        while(n) {
                *((volatile u8 *)vdest) = *((u8 *)src);
-                src = (void *)((unsigned long)src + 1);
+                src++;
-                vdest = (void *)((unsigned long)vdest + 1);                     
+                vdest++;
                n--;
        }
        __asm__ __volatile__ ("sync" : : : "memory");
diff --git a/include/asm-ppc64/io.h b/include/asm-ppc64/io.h
index aba1dfa388ba..59c958aea4db 100644
--- a/include/asm-ppc64/io.h
+++ b/include/asm-ppc64/io.h
@@ -20,10 +20,10 @@
 #include <asm-generic/iomap.h>
-#define __ide_mm_insw(p, a, c) _insw_ns((volatile u16 *)(p), (a), (c))
+#define __ide_mm_insw(p, a, c) _insw_ns((volatile u16 __iomem *)(p), (a), (c))
-#define __ide_mm_insl(p, a, c) _insl_ns((volatile u32 *)(p), (a), (c))
+#define __ide_mm_insl(p, a, c) _insl_ns((volatile u32 __iomem *)(p), (a), (c))
-#define __ide_mm_outsw(p, a, c) _outsw_ns((volatile u16 *)(p), (a), (c))
+#define __ide_mm_outsw(p, a, c) _outsw_ns((volatile u16 __iomem *)(p), (a), (c))
-#define __ide_mm_outsl(p, a, c) _outsl_ns((volatile u32 *)(p), (a), (c))
+#define __ide_mm_outsl(p, a, c) _outsl_ns((volatile u32 __iomem *)(p), (a), (c))
 #define SIO_CONFIG_RA   0x398
@@ -71,8 +71,8 @@ extern unsigned long io_page_mask;
 * Neither do the standard versions now, these are just here
 * for older code.
 */
-#define insw_ns(port, buf, ns)  _insw_ns((u16 *)((port)+pci_io_base), (buf), (ns))
+#define insw_ns(port, buf, ns)  _insw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
-#define insl_ns(port, buf, nl)  _insl_ns((u32 *)((port)+pci_io_base), (buf), (nl))
+#define insl_ns(port, buf, nl)  _insl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
 #else
 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
@@ -136,9 +136,9 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 #define insw_ns(port, buf, ns)  eeh_insw_ns((port), (buf), (ns))
 #define insl_ns(port, buf, nl)  eeh_insl_ns((port), (buf), (nl))
-#define outsb(port, buf, ns)  _outsb((u8 *)((port)+pci_io_base), (buf), (ns))
+#define outsb(port, buf, ns)  _outsb((u8 __iomem *)((port)+pci_io_base), (buf), (ns))
-#define outsw(port, buf, ns)  _outsw_ns((u16 *)((port)+pci_io_base), (buf), (ns))
+#define outsw(port, buf, ns)  _outsw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
-#define outsl(port, buf, nl)  _outsl_ns((u32 *)((port)+pci_io_base), (buf), (nl))
+#define outsl(port, buf, nl)  _outsl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
 #endif
@@ -147,16 +147,16 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 #define readl_relaxed(addr) readl(addr)
 #define readq_relaxed(addr) readq(addr)
-extern void _insb(volatile u8 *port, void *buf, int ns);
+extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
-extern void _outsb(volatile u8 *port, const void *buf, int ns);
+extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
-extern void _insw(volatile u16 *port, void *buf, int ns);
+extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
-extern void _outsw(volatile u16 *port, const void *buf, int ns);
+extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
-extern void _insl(volatile u32 *port, void *buf, int nl);
+extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
-extern void _outsl(volatile u32 *port, const void *buf, int nl);
+extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
-extern void _insw_ns(volatile u16 *port, void *buf, int ns);
+extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
-extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
+extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
-extern void _insl_ns(volatile u32 *port, void *buf, int nl);
+extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
-extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
+extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
 #define mmiowb()
@@ -176,8 +176,8 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
 * Neither do the standard versions now, these are just here
 * for older code.
 */
-#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+pci_io_base), (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
-#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+pci_io_base), (buf), (nl))
+#define outsl_ns(port, buf, nl) _outsl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
 #define IO_SPACE_LIMIT ~(0UL)
diff --git a/include/asm-ppc64/msgbuf.h b/include/asm-ppc64/msgbuf.h
deleted file mode 100644
index 31c1cbf133cc..000000000000
--- a/include/asm-ppc64/msgbuf.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _PPC64_MSGBUF_H
-#define _PPC64_MSGBUF_H
-/* 
- * The msqid64_ds structure for the PPC architecture.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-        __kernel_time_t msg_ctime;      /* last change time */
-        unsigned long  msg_cbytes;      /* current number of bytes on queue */
-        unsigned long  msg_qnum;        /* number of messages in queue */
-        unsigned long  msg_qbytes;      /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long  __unused1;
-        unsigned long  __unused2;
-};
-#endif /* _PPC64_MSGBUF_H */
diff --git a/include/asm-ppc64/param.h b/include/asm-ppc64/param.h
deleted file mode 100644
index 76c212d475b3..000000000000
--- a/include/asm-ppc64/param.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _ASM_PPC64_PARAM_H
-#define _ASM_PPC64_PARAM_H
-#include <linux/config.h>
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifdef __KERNEL__
-# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ        100             /* .. some user interfaces are in "ticks" */
-# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
-#endif
-#ifndef HZ
-#define HZ 100
-#endif
-#define EXEC_PAGESIZE   4096
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-#endif /* _ASM_PPC64_PARAM_H */
diff --git a/include/asm-ppc64/pci-bridge.h b/include/asm-ppc64/pci-bridge.h
index c4f9023ea5ed..6b4a5b1f695e 100644
--- a/include/asm-ppc64/pci-bridge.h
+++ b/include/asm-ppc64/pci-bridge.h
@@ -48,19 +48,52 @@ struct pci_controller {
        unsigned long dma_window_size;
 };
+/*
+ * PCI stuff, for nodes representing PCI devices, pointed to
+ * by device_node->data.
+ */
+struct pci_controller;
+struct iommu_table;
+struct pci_dn {
+        int     busno;                  /* for pci devices */
+        int     bussubno;               /* for pci devices */
+        int     devfn;                  /* for pci devices */
+        int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
+        int     eeh_config_addr;
+        int     eeh_capable;            /* from firmware */
+        int     eeh_check_count;        /* # times driver ignored error */
+        int     eeh_freeze_count;       /* # times this device froze up. */
+        int     eeh_is_bridge;          /* device is pci-to-pci bridge */
+        int     pci_ext_config_space;   /* for pci devices */
+        struct  pci_controller *phb;    /* for pci devices */
+        struct  iommu_table *iommu_table;       /* for phb's or bridges */
+        struct  pci_dev *pcidev;        /* back-pointer to the pci device */
+        struct  device_node *node;      /* back-pointer to the device_node */
+        u32     config_space[16];       /* saved PCI config space */
+};
+/* Get the pointer to a device_node's pci_dn */
+#define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 struct device_node *fetch_dev_dn(struct pci_dev *dev);
-/* Get a device_node from a pci_dev.  This code must be fast except in the case
+/* Get a device_node from a pci_dev.  This code must be fast except
- * where the sysdata is incorrect and needs to be fixed up (hopefully just once)
+ * in the case where the sysdata is incorrect and needs to be fixed
+ * up (this will only happen once).
+ * In this case the sysdata will have been inherited from a PCI host
+ * bridge or a PCI-PCI bridge further up the tree, so it will point
+ * to a valid struct pci_dn, just not the one we want.
 */
 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
 {
        struct device_node *dn = dev->sysdata;
+        struct pci_dn *pdn = dn->data;
-        if (dn->devfn == dev->devfn && dn->busno == dev->bus->number)
+        if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
                return dn;      /* fast path.  sysdata is good */
-        else
+        return fetch_dev_dn(dev);
-                return fetch_dev_dn(dev);
 }
 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
@@ -83,7 +116,7 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
        struct device_node *busdn = bus->sysdata;
        BUG_ON(busdn == NULL);
-        return busdn->phb;
+        return PCI_DN(busdn)->phb;
 }
 #endif
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index 4d057452f59b..a88bbfc26967 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -138,6 +138,19 @@ extern void
 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
                        struct pci_bus_region *region);
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        return root;
+}
 extern int
 unmap_bus_range(struct pci_bus *bus);
diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h
index dc5330b39509..c02ec1d6b909 100644
--- a/include/asm-ppc64/prom.h
+++ b/include/asm-ppc64/prom.h
@@ -116,14 +116,6 @@ struct property {
        struct property *next;
 };
-/* NOTE: the device_node contains PCI specific info for pci devices.
- * This perhaps could be hung off the device_node with another struct,
- * but for now it is directly in the node.  The phb ptr is a good
- * indication of a real PCI node.  Other nodes leave these fields zeroed.
- */
-struct pci_controller;
-struct iommu_table;
 struct device_node {
        char    *name;
        char    *type;
@@ -135,16 +127,6 @@ struct device_node {
        struct  interrupt_info *intrs;
        char    *full_name;
-        /* PCI stuff probably doesn't belong here */
-        int     busno;                  /* for pci devices */
-        int     bussubno;               /* for pci devices */
-        int     devfn;                  /* for pci devices */
-        int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
-        int     eeh_config_addr;
-        int     pci_ext_config_space;   /* for pci devices */
-        struct  pci_controller *phb;    /* for pci devices */
-        struct  iommu_table *iommu_table;       /* for phb's or bridges */
        struct  property *properties;
        struct  device_node *parent;
        struct  device_node *child;
@@ -154,6 +136,7 @@ struct device_node {
        struct  proc_dir_entry *pde;    /* this node's proc directory */
        struct  kref kref;
        unsigned long _flags;
+        void    *data;
 };
 extern struct device_node *of_chosen;
diff --git a/include/asm-ppc64/segment.h b/include/asm-ppc64/segment.h
deleted file mode 100644
index d80fb68cc79e..000000000000
--- a/include/asm-ppc64/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PPC64_SEGMENT_H
-#define __PPC64_SEGMENT_H
-/* Only here because we have some old header files that expect it.. */
-#endif /* __PPC64_SEGMENT_H */
diff --git a/include/asm-ppc64/setup.h b/include/asm-ppc64/setup.h
deleted file mode 100644
index b257b8348c73..000000000000
--- a/include/asm-ppc64/setup.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _PPC_SETUP_H
-#define _PPC_SETUP_H
-#define COMMAND_LINE_SIZE 512
-#endif /* _PPC_SETUP_H */
diff --git a/include/asm-ppc64/timex.h b/include/asm-ppc64/timex.h
deleted file mode 100644
index 8db4da4064cd..000000000000
--- a/include/asm-ppc64/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/include/asm-ppc/timex.h
- *
- * PPC64 architecture timex specifications
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASMPPC64_TIMEX_H
-#define _ASMPPC64_TIMEX_H
-#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
-typedef unsigned long cycles_t;
-static inline cycles_t get_cycles(void)
-{
-        cycles_t ret;
-        __asm__ __volatile__("mftb %0" : "=r" (ret) : );
-        return ret;
-}
-#endif
diff --git a/include/asm-ppc64/user.h b/include/asm-ppc64/user.h
deleted file mode 100644
index d7d6554a421f..000000000000
--- a/include/asm-ppc64/user.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PPC_USER_H
-#define _PPC_USER_H
-/* Adapted from <asm-alpha/user.h> 
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <asm/ptrace.h>
-#include <asm/page.h>
-/*
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd, NOT the osf-core).  The file contents
- * are as follows:
- *
- *  upage: 1 page consisting of a user struct that tells gdb
- *      what is present in the file.  Directly after this is a
- *      copy of the task_struct, which is currently not used by gdb,
- *      but it may come in handy at some point.  All of the registers
- *      are stored as part of the upage.  The upage should always be
- *      only one page long.
- *  data: The data segment follows next.  We use current->end_text to
- *      current->brk to pick up all of the user variables, plus any memory
- *      that may have been sbrk'ed.  No attempt is made to determine if a
- *      page is demand-zero or if a page is totally unused, we just cover
- *      the entire range.  All of the addresses are rounded in such a way
- *      that an integral number of pages is written.
- *  stack: We need the stack information in order to get a meaningful
- *      backtrace.  We need to write the data from usp to
- *      current->start_stack, so we round each of these in order to be able
- *      to write an integer number of pages.
- */
-struct user {
-        struct pt_regs  regs;                   /* entire machine state */
-        size_t          u_tsize;                /* text size (pages) */
-        size_t          u_dsize;                /* data size (pages) */
-        size_t          u_ssize;                /* stack size (pages) */
-        unsigned long   start_code;             /* text starting address */
-        unsigned long   start_data;             /* data starting address */
-        unsigned long   start_stack;            /* stack starting address */
-        long int        signal;                 /* signal causing core dump */
-        struct regs *   u_ar0;                  /* help gdb find registers */
-        unsigned long   magic;                  /* identifies a core file */
-        char            u_comm[32];             /* user command name */
-};
-#define NBPG                    PAGE_SIZE
-#define UPAGES                  1
-#define HOST_TEXT_START_ADDR    (u.start_code)
-#define HOST_DATA_START_ADDR    (u.start_data)
-#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
-#endif /* _PPC_USER_H */
diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h
index a4ab0ec7143a..89bd71b1c0d8 100644
--- a/include/asm-sparc64/pci.h
+++ b/include/asm-sparc64/pci.h
@@ -269,6 +269,8 @@ extern void
 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
                        struct pci_bus_region *region);
+extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index 5e94c05dc2fc..b5417529f6f1 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -28,13 +28,48 @@ enum sparc_cpu {
 #define ARCH_SUN4C_SUN4 0
 #define ARCH_SUN4 0
-extern void mb(void);
+/* These are here in an effort to more fully work around Spitfire Errata
-extern void rmb(void);
+ * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
-extern void wmb(void);
+ * branch, the chip can stop executing instructions until a trap occurs.
-extern void membar_storeload(void);
+ * Therefore, if interrupts are disabled, the chip can hang forever.
-extern void membar_storeload_storestore(void);
+ *
-extern void membar_storeload_loadload(void);
+ * It used to be believed that the memory barrier had to be right in the
-extern void membar_storestore_loadstore(void);
+ * delay slot, but a case has been traced recently wherein the memory barrier
+ * was one instruction after the branch delay slot and the chip still hung.
+ * The offending sequence was the following in sym_wakeup_done() of the
+ * sym53c8xx_2 driver:
+ *
+ *      call    sym_ccb_from_dsa, 0
+ *       movge  %icc, 0, %l0
+ *      brz,pn  %o0, .LL1303
+ *       mov    %o0, %l2
+ *      membar  #LoadLoad
+ *
+ * The branch has to be mispredicted for the bug to occur.  Therefore, we put
+ * the memory barrier explicitly into a "branch always, predicted taken"
+ * delay slot to avoid the problem case.
+ */
+#define membar_safe(type) \
+do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
+                             " membar   " type "\n" \
+                             "1:\n" \
+                             : : : "memory"); \
+} while (0)
+#define mb()    \
+        membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
+#define rmb()   \
+        membar_safe("#LoadLoad")
+#define wmb()   \
+        membar_safe("#StoreStore")
+#define membar_storeload() \
+        membar_safe("#StoreLoad")
+#define membar_storeload_storestore() \
+        membar_safe("#StoreLoad | #StoreStore")
+#define membar_storeload_loadload() \
+        membar_safe("#StoreLoad | #LoadLoad")
+#define membar_storestore_loadstore() \
+        membar_safe("#StoreStore | #LoadStore")
 #endif
diff --git a/include/linux/crc16.h b/include/linux/crc16.h
new file mode 100644
index 000000000000..bdedf825b04a
--- /dev/null
+++ b/include/linux/crc16.h
@@ -0,0 +1,44 @@
+/*
+ *      crc16.h - CRC-16 routine
+ *
+ * Implements the standard CRC-16, as used with 1-wire devices:
+ *   Width 16
+ *   Poly  0x8005 (x^16 + x^15 + x^2 + 1)
+ *   Init  0
+ *
+ * For 1-wire devices, the CRC is stored inverted, LSB-first
+ *
+ * Example buffer with the CRC attached:
+ *   31 32 33 34 35 36 37 38 39 C2 44
+ *
+ * The CRC over a buffer with the CRC attached is 0xB001.
+ * So, if (crc16(0, buf, size) == 0xB001) then the buffer is valid.
+ *
+ * Refer to "Application Note 937: Book of iButton Standards" for details.
+ * http://www.maxim-ic.com/appnotes.cfm/appnote_number/937
+ *
+ * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+#ifndef __CRC16_H
+#define __CRC16_H
+#include <linux/types.h>
+#define CRC16_INIT              0
+#define CRC16_VALID             0xb001
+extern u16 const crc16_table[256];
+extern u16 crc16(u16 crc, const u8 *buffer, size_t len);
+static inline u16 crc16_byte(u16 crc, const u8 data)
+{
+        return (crc >> 8) ^ crc16_table[(crc ^ data) & 0xff];
+}
+#endif /* __CRC16_H */
diff --git a/include/linux/i2c-pxa.h b/include/linux/i2c-pxa.h
new file mode 100644
index 000000000000..5f3eaf802223
--- /dev/null
+++ b/include/linux/i2c-pxa.h
@@ -0,0 +1,48 @@
+#ifndef _LINUX_I2C_ALGO_PXA_H
+#define _LINUX_I2C_ALGO_PXA_H
+struct i2c_eeprom_emu_watcher {
+        void (*write)(void *, unsigned int addr, unsigned char newval);
+};
+struct i2c_eeprom_emu_watch {
+        struct list_head node;
+        unsigned int start;
+        unsigned int end;
+        struct i2c_eeprom_emu_watcher *ops;
+        void *data;
+};
+#define I2C_EEPROM_EMU_SIZE (256)
+struct i2c_eeprom_emu {
+        unsigned int size;
+        unsigned int ptr;
+        unsigned int seen_start;
+        struct list_head watch;
+        unsigned char bytes[I2C_EEPROM_EMU_SIZE];
+};
+typedef enum i2c_slave_event_e {
+        I2C_SLAVE_EVENT_START_READ,
+        I2C_SLAVE_EVENT_START_WRITE,
+        I2C_SLAVE_EVENT_STOP
+} i2c_slave_event_t;
+struct i2c_slave_client {
+        void *data;
+        void (*event)(void *ptr, i2c_slave_event_t event);
+        int  (*read) (void *ptr);
+        void (*write)(void *ptr, unsigned int val);
+};
+extern int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *, void *data,
+                                     unsigned int addr, unsigned int size,
+                                     struct i2c_eeprom_emu_watcher *);
+extern void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *, void *data, struct i2c_eeprom_emu_watcher *watcher);
+extern struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void);
+#endif /* _LINUX_I2C_ALGO_PXA_H */
diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h
index 94a46f38c532..58385ee1c0ac 100644
--- a/include/linux/mempolicy.h
+++ b/include/linux/mempolicy.h
@@ -155,6 +155,7 @@ struct mempolicy *get_vma_policy(struct task_struct *task,
 extern void numa_default_policy(void);
 extern void numa_policy_init(void);
+extern struct mempolicy default_policy;
 #else
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 6014160d9c06..c1f021eddffa 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -109,6 +109,8 @@ struct mmc_host {
        struct mmc_card         *card_selected; /* the selected MMC card */
        struct work_struct      detect;
+        unsigned long           private[0] ____cacheline_aligned;
 };
 extern struct mmc_host *mmc_alloc_host(int extra, struct device *);
@@ -116,14 +118,18 @@ extern int mmc_add_host(struct mmc_host *);
 extern void mmc_remove_host(struct mmc_host *);
 extern void mmc_free_host(struct mmc_host *);
-#define mmc_priv(x)     ((void *)((x) + 1))
+static inline void *mmc_priv(struct mmc_host *host)
+{
+        return (void *)host->private;
+}
 #define mmc_dev(x)      ((x)->dev)
 #define mmc_hostname(x) ((x)->class_dev.class_id)
 extern int mmc_suspend_host(struct mmc_host *, pm_message_t);
 extern int mmc_resume_host(struct mmc_host *);
-extern void mmc_detect_change(struct mmc_host *);
+extern void mmc_detect_change(struct mmc_host *, unsigned long delay);
 extern void mmc_request_done(struct mmc_host *, struct mmc_request *);
 #endif
diff --git a/include/linux/pci.h b/include/linux/pci.h
index bc4c40000c0d..6caaba0af469 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -19,436 +19,10 @@
 #include <linux/mod_devicetable.h>
-/*
+/* Include the pci register defines */
- * Under PCI, each device has 256 bytes of configuration address space,
+#include <linux/pci_regs.h>
- * of which the first 64 bytes are standardized as follows:
- */
-#define PCI_VENDOR_ID           0x00    /* 16 bits */
-#define PCI_DEVICE_ID           0x02    /* 16 bits */
-#define PCI_COMMAND             0x04    /* 16 bits */
-#define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
-#define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
-#define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
-#define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
-#define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
-#define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
-#define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
-#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
-#define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
-#define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
-#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
-#define PCI_STATUS              0x06    /* 16 bits */
-#define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
-#define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
-#define  PCI_STATUS_UDF         0x40    /* Support User Definable Features [obsolete] */
-#define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
-#define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
-#define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST 0x000   
-#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
-#define  PCI_STATUS_DEVSEL_SLOW 0x400
-#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
-#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
-#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
-#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
-#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
-#define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
-                                           revision */
-#define PCI_REVISION_ID         0x08    /* Revision ID */
-#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
-#define PCI_CLASS_DEVICE        0x0a    /* Device class */
-#define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
-#define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
-#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
-#define  PCI_HEADER_TYPE_NORMAL 0
-#define  PCI_HEADER_TYPE_BRIDGE 1
-#define  PCI_HEADER_TYPE_CARDBUS 2
-#define PCI_BIST                0x0f    /* 8 bits */
-#define  PCI_BIST_CODE_MASK     0x0f    /* Return result */
-#define  PCI_BIST_START         0x40    /* 1 to start BIST, 2 secs or less */
-#define  PCI_BIST_CAPABLE       0x80    /* 1 if BIST capable */
-/*
- * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of 
- * 0xffffffff to the register, and reading it back.  Only 
- * 1 bits are decoded.
- */
-#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
-#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
-#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
-#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
-#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
-#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
-#define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
-#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
-#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
-#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
-#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
-#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
-#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
-#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
-/* bit 1 is reserved if address_space = 1 */
-/* Header type 0 (normal devices) */
-#define PCI_CARDBUS_CIS         0x28
-#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
-#define PCI_SUBSYSTEM_ID        0x2e  
-#define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
-#define  PCI_ROM_ADDRESS_ENABLE 0x01
-#define PCI_ROM_ADDRESS_MASK    (~0x7ffUL)
-#define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
-/* 0x35-0x3b are reserved */
-#define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
-#define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
-#define PCI_MIN_GNT             0x3e    /* 8 bits */
-#define PCI_MAX_LAT             0x3f    /* 8 bits */
-/* Header type 1 (PCI-to-PCI bridges) */
-#define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
-#define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
-#define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
-#define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary interface */
-#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
-#define PCI_IO_LIMIT            0x1d
-#define  PCI_IO_RANGE_TYPE_MASK 0x0fUL  /* I/O bridging type */
-#define  PCI_IO_RANGE_TYPE_16   0x00
-#define  PCI_IO_RANGE_TYPE_32   0x01
-#define  PCI_IO_RANGE_MASK      (~0x0fUL)
-#define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
-#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
-#define PCI_MEMORY_LIMIT        0x22
-#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
-#define  PCI_MEMORY_RANGE_MASK  (~0x0fUL)
-#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
-#define PCI_PREF_MEMORY_LIMIT   0x26
-#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
-#define  PCI_PREF_RANGE_TYPE_32 0x00
-#define  PCI_PREF_RANGE_TYPE_64 0x01
-#define  PCI_PREF_RANGE_MASK    (~0x0fUL)
-#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
-#define PCI_PREF_LIMIT_UPPER32  0x2c
-#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
-#define PCI_IO_LIMIT_UPPER16    0x32
-/* 0x34 same as for htype 0 */
-/* 0x35-0x3b is reserved */
-#define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
-/* 0x3c-0x3d are same as for htype 0 */
-#define PCI_BRIDGE_CONTROL      0x3e
-#define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
-#define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
-#define  PCI_BRIDGE_CTL_NO_ISA  0x04    /* Disable bridging of ISA ports */
-#define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
-#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
-#define  PCI_BRIDGE_CTL_BUS_RESET 0x40  /* Secondary bus reset */
-#define  PCI_BRIDGE_CTL_FAST_BACK 0x80  /* Fast Back2Back enabled on secondary interface */
-/* Header type 2 (CardBus bridges) */
-#define PCI_CB_CAPABILITY_LIST  0x14
-/* 0x15 reserved */
-#define PCI_CB_SEC_STATUS       0x16    /* Secondary status */
-#define PCI_CB_PRIMARY_BUS      0x18    /* PCI bus number */
-#define PCI_CB_CARD_BUS         0x19    /* CardBus bus number */
-#define PCI_CB_SUBORDINATE_BUS  0x1a    /* Subordinate bus number */
-#define PCI_CB_LATENCY_TIMER    0x1b    /* CardBus latency timer */
-#define PCI_CB_MEMORY_BASE_0    0x1c
-#define PCI_CB_MEMORY_LIMIT_0   0x20
-#define PCI_CB_MEMORY_BASE_1    0x24
-#define PCI_CB_MEMORY_LIMIT_1   0x28
-#define PCI_CB_IO_BASE_0        0x2c
-#define PCI_CB_IO_BASE_0_HI     0x2e
-#define PCI_CB_IO_LIMIT_0       0x30
-#define PCI_CB_IO_LIMIT_0_HI    0x32
-#define PCI_CB_IO_BASE_1        0x34
-#define PCI_CB_IO_BASE_1_HI     0x36
-#define PCI_CB_IO_LIMIT_1       0x38
-#define PCI_CB_IO_LIMIT_1_HI    0x3a
-#define  PCI_CB_IO_RANGE_MASK   (~0x03UL)
-/* 0x3c-0x3d are same as for htype 0 */
-#define PCI_CB_BRIDGE_CONTROL   0x3e
-#define  PCI_CB_BRIDGE_CTL_PARITY       0x01    /* Similar to standard bridge control register */
-#define  PCI_CB_BRIDGE_CTL_SERR         0x02
-#define  PCI_CB_BRIDGE_CTL_ISA          0x04
-#define  PCI_CB_BRIDGE_CTL_VGA          0x08
-#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
-#define  PCI_CB_BRIDGE_CTL_CB_RESET     0x40    /* CardBus reset */
-#define  PCI_CB_BRIDGE_CTL_16BIT_INT    0x80    /* Enable interrupt for 16-bit cards */
-#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100  /* Prefetch enable for both memory regions */
-#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
-#define  PCI_CB_BRIDGE_CTL_POST_WRITES  0x400
-#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
-#define PCI_CB_SUBSYSTEM_ID     0x42
-#define PCI_CB_LEGACY_MODE_BASE 0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
-/* 0x48-0x7f reserved */
-/* Capability lists */
-#define PCI_CAP_LIST_ID         0       /* Capability ID */
-#define  PCI_CAP_ID_PM          0x01    /* Power Management */
-#define  PCI_CAP_ID_AGP         0x02    /* Accelerated Graphics Port */
-#define  PCI_CAP_ID_VPD         0x03    /* Vital Product Data */
-#define  PCI_CAP_ID_SLOTID      0x04    /* Slot Identification */
-#define  PCI_CAP_ID_MSI         0x05    /* Message Signalled Interrupts */
-#define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
-#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
-#define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
-#define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
-#define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
-#define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
-#define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
-#define PCI_CAP_SIZEOF          4
-/* Power Management Registers */
-#define PCI_PM_PMC              2       /* PM Capabilities Register */
-#define  PCI_PM_CAP_VER_MASK    0x0007  /* Version */
-#define  PCI_PM_CAP_PME_CLOCK   0x0008  /* PME clock required */
-#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
-#define  PCI_PM_CAP_DSI         0x0020  /* Device specific initialization */
-#define  PCI_PM_CAP_AUX_POWER   0x01C0  /* Auxilliary power support mask */
-#define  PCI_PM_CAP_D1          0x0200  /* D1 power state support */
-#define  PCI_PM_CAP_D2          0x0400  /* D2 power state support */
-#define  PCI_PM_CAP_PME         0x0800  /* PME pin supported */
-#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
-#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
-#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
-#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
-#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
-#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
-#define PCI_PM_CTRL             4       /* PM control and status register */
-#define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
-#define  PCI_PM_CTRL_PME_ENABLE 0x0100  /* PME pin enable */
-#define  PCI_PM_CTRL_DATA_SEL_MASK      0x1e00  /* Data select (??) */
-#define  PCI_PM_CTRL_DATA_SCALE_MASK    0x6000  /* Data scale (??) */
-#define  PCI_PM_CTRL_PME_STATUS 0x8000  /* PME pin status */
-#define PCI_PM_PPB_EXTENSIONS   6       /* PPB support extensions (??) */
-#define  PCI_PM_PPB_B2_B3       0x40    /* Stop clock when in D3hot (??) */
-#define  PCI_PM_BPCC_ENABLE     0x80    /* Bus power/clock control enable (??) */
-#define PCI_PM_DATA_REGISTER    7       /* (??) */
-#define PCI_PM_SIZEOF           8
-/* AGP registers */
-#define PCI_AGP_VERSION         2       /* BCD version number */
-#define PCI_AGP_RFU             3       /* Rest of capability flags */
-#define PCI_AGP_STATUS          4       /* Status register */
-#define  PCI_AGP_STATUS_RQ_MASK 0xff000000      /* Maximum number of requests - 1 */
-#define  PCI_AGP_STATUS_SBA     0x0200  /* Sideband addressing supported */
-#define  PCI_AGP_STATUS_64BIT   0x0020  /* 64-bit addressing supported */
-#define  PCI_AGP_STATUS_FW      0x0010  /* FW transfers supported */
-#define  PCI_AGP_STATUS_RATE4   0x0004  /* 4x transfer rate supported */
-#define  PCI_AGP_STATUS_RATE2   0x0002  /* 2x transfer rate supported */
-#define  PCI_AGP_STATUS_RATE1   0x0001  /* 1x transfer rate supported */
-#define PCI_AGP_COMMAND         8       /* Control register */
-#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
-#define  PCI_AGP_COMMAND_SBA    0x0200  /* Sideband addressing enabled */
-#define  PCI_AGP_COMMAND_AGP    0x0100  /* Allow processing of AGP transactions */
-#define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
-#define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
-#define  PCI_AGP_COMMAND_RATE4  0x0004  /* Use 4x rate */
-#define  PCI_AGP_COMMAND_RATE2  0x0002  /* Use 2x rate */
-#define  PCI_AGP_COMMAND_RATE1  0x0001  /* Use 1x rate */
-#define PCI_AGP_SIZEOF          12
-/* Vital Product Data */
-#define PCI_VPD_ADDR            2       /* Address to access (15 bits!) */
-#define  PCI_VPD_ADDR_MASK      0x7fff  /* Address mask */
-#define  PCI_VPD_ADDR_F         0x8000  /* Write 0, 1 indicates completion */
-#define PCI_VPD_DATA            4       /* 32-bits of data returned here */
-/* Slot Identification */
-#define PCI_SID_ESR             2       /* Expansion Slot Register */
-#define  PCI_SID_ESR_NSLOTS     0x1f    /* Number of expansion slots available */
-#define  PCI_SID_ESR_FIC        0x20    /* First In Chassis Flag */
-#define PCI_SID_CHASSIS_NR      3       /* Chassis Number */
-/* Message Signalled Interrupts registers */
-#define PCI_MSI_FLAGS           2       /* Various flags */
-#define  PCI_MSI_FLAGS_64BIT    0x80    /* 64-bit addresses allowed */
-#define  PCI_MSI_FLAGS_QSIZE    0x70    /* Message queue size configured */
-#define  PCI_MSI_FLAGS_QMASK    0x0e    /* Maximum queue size available */
-#define  PCI_MSI_FLAGS_ENABLE   0x01    /* MSI feature enabled */
-#define  PCI_MSI_FLAGS_MASKBIT  0x100   /* 64-bit mask bits allowed */
-#define PCI_MSI_RFU             3       /* Rest of capability flags */
-#define PCI_MSI_ADDRESS_LO      4       /* Lower 32 bits */
-#define PCI_MSI_ADDRESS_HI      8       /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
-#define PCI_MSI_DATA_32         8       /* 16 bits of data for 32-bit devices */
-#define PCI_MSI_DATA_64         12      /* 16 bits of data for 64-bit devices */
-#define PCI_MSI_MASK_BIT        16      /* Mask bits register */
-/* CompactPCI Hotswap Register */
-#define PCI_CHSWP_CSR           2       /* Control and Status Register */
-#define  PCI_CHSWP_DHA          0x01    /* Device Hiding Arm */
-#define  PCI_CHSWP_EIM          0x02    /* ENUM# Signal Mask */
-#define  PCI_CHSWP_PIE          0x04    /* Pending Insert or Extract */
-#define  PCI_CHSWP_LOO          0x08    /* LED On / Off */
-#define  PCI_CHSWP_PI           0x30    /* Programming Interface */
-#define  PCI_CHSWP_EXT          0x40    /* ENUM# status - extraction */
-#define  PCI_CHSWP_INS          0x80    /* ENUM# status - insertion */
-/* PCI-X registers */
-#define PCI_X_CMD               2       /* Modes & Features */
-#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
-#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
-#define  PCI_X_CMD_MAX_READ     0x000c  /* Max Memory Read Byte Count */
-#define  PCI_X_CMD_MAX_SPLIT    0x0070  /* Max Outstanding Split Transactions */
-#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
-#define PCI_X_STATUS            4       /* PCI-X capabilities */
-#define  PCI_X_STATUS_DEVFN     0x000000ff      /* A copy of devfn */
-#define  PCI_X_STATUS_BUS       0x0000ff00      /* A copy of bus nr */
-#define  PCI_X_STATUS_64BIT     0x00010000      /* 64-bit device */
-#define  PCI_X_STATUS_133MHZ    0x00020000      /* 133 MHz capable */
-#define  PCI_X_STATUS_SPL_DISC  0x00040000      /* Split Completion Discarded */
-#define  PCI_X_STATUS_UNX_SPL   0x00080000      /* Unexpected Split Completion */
-#define  PCI_X_STATUS_COMPLEX   0x00100000      /* Device Complexity */
-#define  PCI_X_STATUS_MAX_READ  0x00600000      /* Designed Max Memory Read Count */
-#define  PCI_X_STATUS_MAX_SPLIT 0x03800000      /* Designed Max Outstanding Split Transactions */
-#define  PCI_X_STATUS_MAX_CUM   0x1c000000      /* Designed Max Cumulative Read Size */
-#define  PCI_X_STATUS_SPL_ERR   0x20000000      /* Rcvd Split Completion Error Msg */
-#define  PCI_X_STATUS_266MHZ    0x40000000      /* 266 MHz capable */
-#define  PCI_X_STATUS_533MHZ    0x80000000      /* 533 MHz capable */
-/* PCI Express capability registers */
-#define PCI_EXP_FLAGS           2       /* Capabilities register */
-#define PCI_EXP_FLAGS_VERS      0x000f  /* Capability version */
-#define PCI_EXP_FLAGS_TYPE      0x00f0  /* Device/Port type */
-#define  PCI_EXP_TYPE_ENDPOINT  0x0     /* Express Endpoint */
-#define  PCI_EXP_TYPE_LEG_END   0x1     /* Legacy Endpoint */
-#define  PCI_EXP_TYPE_ROOT_PORT 0x4     /* Root Port */
-#define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
-#define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
-#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
-#define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
-#define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
-#define PCI_EXP_DEVCAP          4       /* Device capabilities */
-#define  PCI_EXP_DEVCAP_PAYLOAD 0x07    /* Max_Payload_Size */
-#define  PCI_EXP_DEVCAP_PHANTOM 0x18    /* Phantom functions */
-#define  PCI_EXP_DEVCAP_EXT_TAG 0x20    /* Extended tags */
-#define  PCI_EXP_DEVCAP_L0S     0x1c0   /* L0s Acceptable Latency */
-#define  PCI_EXP_DEVCAP_L1      0xe00   /* L1 Acceptable Latency */
-#define  PCI_EXP_DEVCAP_ATN_BUT 0x1000  /* Attention Button Present */
-#define  PCI_EXP_DEVCAP_ATN_IND 0x2000  /* Attention Indicator Present */
-#define  PCI_EXP_DEVCAP_PWR_IND 0x4000  /* Power Indicator Present */
-#define  PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
-#define  PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
-#define PCI_EXP_DEVCTL          8       /* Device Control */
-#define  PCI_EXP_DEVCTL_CERE    0x0001  /* Correctable Error Reporting En. */
-#define  PCI_EXP_DEVCTL_NFERE   0x0002  /* Non-Fatal Error Reporting Enable */
-#define  PCI_EXP_DEVCTL_FERE    0x0004  /* Fatal Error Reporting Enable */
-#define  PCI_EXP_DEVCTL_URRE    0x0008  /* Unsupported Request Reporting En. */
-#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
-#define  PCI_EXP_DEVCTL_PAYLOAD 0x00e0  /* Max_Payload_Size */
-#define  PCI_EXP_DEVCTL_EXT_TAG 0x0100  /* Extended Tag Field Enable */
-#define  PCI_EXP_DEVCTL_PHANTOM 0x0200  /* Phantom Functions Enable */
-#define  PCI_EXP_DEVCTL_AUX_PME 0x0400  /* Auxiliary Power PM Enable */
-#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
-#define  PCI_EXP_DEVCTL_READRQ  0x7000  /* Max_Read_Request_Size */
-#define PCI_EXP_DEVSTA          10      /* Device Status */
-#define  PCI_EXP_DEVSTA_CED     0x01    /* Correctable Error Detected */
-#define  PCI_EXP_DEVSTA_NFED    0x02    /* Non-Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_FED     0x04    /* Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_URD     0x08    /* Unsupported Request Detected */
-#define  PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
-#define  PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
-#define PCI_EXP_LNKCAP          12      /* Link Capabilities */
-#define PCI_EXP_LNKCTL          16      /* Link Control */
-#define PCI_EXP_LNKSTA          18      /* Link Status */
-#define PCI_EXP_SLTCAP          20      /* Slot Capabilities */
-#define PCI_EXP_SLTCTL          24      /* Slot Control */
-#define PCI_EXP_SLTSTA          26      /* Slot Status */
-#define PCI_EXP_RTCTL           28      /* Root Control */
-#define  PCI_EXP_RTCTL_SECEE    0x01    /* System Error on Correctable Error */
-#define  PCI_EXP_RTCTL_SENFEE   0x02    /* System Error on Non-Fatal Error */
-#define  PCI_EXP_RTCTL_SEFEE    0x04    /* System Error on Fatal Error */
-#define  PCI_EXP_RTCTL_PMEIE    0x08    /* PME Interrupt Enable */
-#define  PCI_EXP_RTCTL_CRSSVE   0x10    /* CRS Software Visibility Enable */
-#define PCI_EXP_RTCAP           30      /* Root Capabilities */
-#define PCI_EXP_RTSTA           32      /* Root Status */
-/* Extended Capabilities (PCI-X 2.0 and Express) */
-#define PCI_EXT_CAP_ID(header)          (header & 0x0000ffff)
-#define PCI_EXT_CAP_VER(header)         ((header >> 16) & 0xf)
-#define PCI_EXT_CAP_NEXT(header)        ((header >> 20) & 0xffc)
-#define PCI_EXT_CAP_ID_ERR      1
-#define PCI_EXT_CAP_ID_VC       2
-#define PCI_EXT_CAP_ID_DSN      3
-#define PCI_EXT_CAP_ID_PWR      4
-/* Advanced Error Reporting */
-#define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
-#define  PCI_ERR_UNC_TRAIN      0x00000001      /* Training */
-#define  PCI_ERR_UNC_DLP        0x00000010      /* Data Link Protocol */
-#define  PCI_ERR_UNC_POISON_TLP 0x00001000      /* Poisoned TLP */
-#define  PCI_ERR_UNC_FCP        0x00002000      /* Flow Control Protocol */
-#define  PCI_ERR_UNC_COMP_TIME  0x00004000      /* Completion Timeout */
-#define  PCI_ERR_UNC_COMP_ABORT 0x00008000      /* Completer Abort */
-#define  PCI_ERR_UNC_UNX_COMP   0x00010000      /* Unexpected Completion */
-#define  PCI_ERR_UNC_RX_OVER    0x00020000      /* Receiver Overflow */
-#define  PCI_ERR_UNC_MALF_TLP   0x00040000      /* Malformed TLP */
-#define  PCI_ERR_UNC_ECRC       0x00080000      /* ECRC Error Status */
-#define  PCI_ERR_UNC_UNSUP      0x00100000      /* Unsupported Request */
-#define PCI_ERR_UNCOR_MASK      8       /* Uncorrectable Error Mask */
-        /* Same bits as above */
-#define PCI_ERR_UNCOR_SEVER     12      /* Uncorrectable Error Severity */
-        /* Same bits as above */
-#define PCI_ERR_COR_STATUS      16      /* Correctable Error Status */
-#define  PCI_ERR_COR_RCVR       0x00000001      /* Receiver Error Status */
-#define  PCI_ERR_COR_BAD_TLP    0x00000040      /* Bad TLP Status */
-#define  PCI_ERR_COR_BAD_DLLP   0x00000080      /* Bad DLLP Status */
-#define  PCI_ERR_COR_REP_ROLL   0x00000100      /* REPLAY_NUM Rollover */
-#define  PCI_ERR_COR_REP_TIMER  0x00001000      /* Replay Timer Timeout */
-#define PCI_ERR_COR_MASK        20      /* Correctable Error Mask */
-        /* Same bits as above */
-#define PCI_ERR_CAP             24      /* Advanced Error Capabilities */
-#define  PCI_ERR_CAP_FEP(x)     ((x) & 31)      /* First Error Pointer */
-#define  PCI_ERR_CAP_ECRC_GENC  0x00000020      /* ECRC Generation Capable */
-#define  PCI_ERR_CAP_ECRC_GENE  0x00000040      /* ECRC Generation Enable */
-#define  PCI_ERR_CAP_ECRC_CHKC  0x00000080      /* ECRC Check Capable */
-#define  PCI_ERR_CAP_ECRC_CHKE  0x00000100      /* ECRC Check Enable */
-#define PCI_ERR_HEADER_LOG      28      /* Header Log Register (16 bytes) */
-#define PCI_ERR_ROOT_COMMAND    44      /* Root Error Command */
-#define PCI_ERR_ROOT_STATUS     48
-#define PCI_ERR_ROOT_COR_SRC    52
-#define PCI_ERR_ROOT_SRC        54
-/* Virtual Channel */
-#define PCI_VC_PORT_REG1        4
-#define PCI_VC_PORT_REG2        8
-#define PCI_VC_PORT_CTRL        12
-#define PCI_VC_PORT_STATUS      14
-#define PCI_VC_RES_CAP          16
-#define PCI_VC_RES_CTRL         20
-#define PCI_VC_RES_STATUS       26
-/* Power Budgeting */
-#define PCI_PWR_DSR             4       /* Data Select Register */
-#define PCI_PWR_DATA            8       /* Data Register */
-#define  PCI_PWR_DATA_BASE(x)   ((x) & 0xff)        /* Base Power */
-#define  PCI_PWR_DATA_SCALE(x)  (((x) >> 8) & 3)    /* Data Scale */
-#define  PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)   /* PM Sub State */
-#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
-#define  PCI_PWR_DATA_TYPE(x)   (((x) >> 15) & 7)   /* Type */
-#define  PCI_PWR_DATA_RAIL(x)   (((x) >> 18) & 7)   /* Power Rail */
-#define PCI_PWR_CAP             12      /* Capability */
-#define  PCI_PWR_CAP_BUDGET(x)  ((x) & 1)       /* Included in system budget */
 /* Include the ID list */
 #include <linux/pci_ids.h>
 /*
@@ -496,11 +70,12 @@ enum pci_mmap_state {
 typedef int __bitwise pci_power_t;
-#define PCI_D0  ((pci_power_t __force) 0)
+#define PCI_D0          ((pci_power_t __force) 0)
-#define PCI_D1  ((pci_power_t __force) 1)
+#define PCI_D1          ((pci_power_t __force) 1)
-#define PCI_D2  ((pci_power_t __force) 2)
+#define PCI_D2          ((pci_power_t __force) 2)
 #define PCI_D3hot       ((pci_power_t __force) 3)
 #define PCI_D3cold      ((pci_power_t __force) 4)
+#define PCI_UNKNOWN     ((pci_power_t __force) 5)
 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
 /*
@@ -562,11 +137,6 @@ struct pci_dev {
        struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
        int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
        struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
-#ifdef CONFIG_PCI_NAMES
-#define PCI_NAME_SIZE   255
-#define PCI_NAME_HALF   __stringify(43) /* less than half to handle slop */
-        char            pretty_name[PCI_NAME_SIZE];     /* pretty name for users to see */
-#endif
 };
 #define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
@@ -582,15 +152,15 @@ struct pci_dev {
 *      7-10    bridges: address space assigned to buses behind the bridge
 */
-#define PCI_ROM_RESOURCE 6
+#define PCI_ROM_RESOURCE        6
-#define PCI_BRIDGE_RESOURCES 7
+#define PCI_BRIDGE_RESOURCES    7
-#define PCI_NUM_RESOURCES 11
+#define PCI_NUM_RESOURCES       11
 #ifndef PCI_BUS_NUM_RESOURCES
-#define PCI_BUS_NUM_RESOURCES 8
+#define PCI_BUS_NUM_RESOURCES   8
 #endif
-  
-#define PCI_REGION_FLAG_MASK 0x0fU      /* These bits of resource flags tell us the PCI region flags */
+#define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
 struct pci_bus {
        struct list_head node;          /* node in list of buses */
@@ -699,7 +269,7 @@ struct pci_driver {
 * @dev_class_mask: the class mask for this device
 *
 * This macro is used to create a struct pci_device_id that matches a
- * specific PCI class.  The vendor, device, subvendor, and subdevice 
+ * specific PCI class.  The vendor, device, subvendor, and subdevice
 * fields will be set to PCI_ANY_ID.
 */
 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
@@ -707,7 +277,7 @@ struct pci_driver {
        .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
        .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
-/* 
+/*
 * pci_module_init is obsolete, this stays here till we fix up all usages of it
 * in the tree.
 */
@@ -749,8 +319,6 @@ int pci_scan_slot(struct pci_bus *bus, int devfn);
 struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
 unsigned int pci_scan_child_bus(struct pci_bus *bus);
 void pci_bus_add_device(struct pci_dev *dev);
-void pci_name_device(struct pci_dev *dev);
-char *pci_class_name(u32 class);
 void pci_read_bridge_bases(struct pci_bus *child);
 struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
@@ -815,9 +383,12 @@ void pci_set_master(struct pci_dev *dev);
 #define HAVE_PCI_SET_MWI
 int pci_set_mwi(struct pci_dev *dev);
 void pci_clear_mwi(struct pci_dev *dev);
+void pci_intx(struct pci_dev *dev, int enable);
 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
+void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
 int pci_assign_resource(struct pci_dev *dev, int i);
+void pci_restore_bars(struct pci_dev *dev);
 /* ROM control related routines */
 void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size);
@@ -865,6 +436,9 @@ const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_
 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
+void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
+                  void *userdata);
 /* kmem_cache style wrapper around pci_alloc_consistent() */
 #include <linux/dmapool.h>
@@ -912,18 +486,26 @@ extern void pci_disable_msix(struct pci_dev *dev);
 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
 #endif
-#endif /* CONFIG_PCI */
+/*
+ * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
-/* Include architecture-dependent settings and functions */
+ * a PCI domain is defined to be a set of PCI busses which share
+ * configuration space.
+ */
+#ifndef CONFIG_PCI_DOMAINS
+static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        return 0;
+}
+#endif
-#include <asm/pci.h>
+#else /* CONFIG_PCI is not enabled */
 /*
 *  If the system does not have PCI, clearly these return errors.  Define
 *  these as simple inline functions to avoid hair in drivers.
 */
-#ifndef CONFIG_PCI
 #define _PCI_NOP(o,s,t) \
        static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
                { return PCIBIOS_FUNC_NOT_SUPPORTED; }
@@ -974,21 +556,11 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
-#else
+#endif /* CONFIG_PCI */
-/*
+/* Include architecture-dependent settings and functions */
- * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
- * a PCI domain is defined to be a set of PCI busses which share
+#include <asm/pci.h>
- * configuration space.
- */
-#ifndef CONFIG_PCI_DOMAINS
-static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
-static inline int pci_proc_domain(struct pci_bus *bus)
-{
-        return 0;
-}
-#endif
-#endif /* !CONFIG_PCI */
 /* these helpers provide future and backwards compatibility
 * for accessing popular PCI BAR info */
@@ -1025,13 +597,6 @@ static inline char *pci_name(struct pci_dev *pdev)
        return pdev->dev.bus_id;
 }
-/* Some archs want to see the pretty pci name, so use this macro */
-#ifdef CONFIG_PCI_NAMES
-#define pci_pretty_name(dev) ((dev)->pretty_name)
-#else
-#define pci_pretty_name(dev) ""
-#endif
 /* Some archs don't want to expose struct resource to userland as-is
 * in sysfs and /proc
@@ -1067,7 +632,7 @@ enum pci_fixup_pass {
 /* Anonymous variables would be nice... */
 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook)  \
-        static struct pci_fixup __pci_fixup_##name __attribute_used__   \
+        static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
        __attribute__((__section__(#section))) = { vendor, device, hook };
 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
new file mode 100644
index 000000000000..e2a089b051ed
--- /dev/null
+++ b/include/linux/pci_regs.h
@@ -0,0 +1,448 @@
+/*
+ *      pci_regs.h
+ *
+ *      PCI standard defines
+ *      Copyright 1994, Drew Eckhardt
+ *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
+ *
+ *      For more information, please consult the following manuals (look at
+ *      http://www.pcisig.com/ for how to get them):
+ *
+ *      PCI BIOS Specification
+ *      PCI Local Bus Specification
+ *      PCI to PCI Bridge Specification
+ *      PCI System Design Guide
+ */
+#ifndef LINUX_PCI_REGS_H
+#define LINUX_PCI_REGS_H
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+#define PCI_VENDOR_ID           0x00    /* 16 bits */
+#define PCI_DEVICE_ID           0x02    /* 16 bits */
+#define PCI_COMMAND             0x04    /* 16 bits */
+#define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
+#define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
+#define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
+#define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
+#define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
+#define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
+#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
+#define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
+#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
+#define PCI_STATUS              0x06    /* 16 bits */
+#define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
+#define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_UDF         0x40    /* Support User Definable Features [obsolete] */
+#define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
+#define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
+#define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
+#define  PCI_STATUS_DEVSEL_FAST         0x000
+#define  PCI_STATUS_DEVSEL_MEDIUM       0x200
+#define  PCI_STATUS_DEVSEL_SLOW         0x400
+#define  PCI_STATUS_SIG_TARGET_ABORT    0x800 /* Set on target abort */
+#define  PCI_STATUS_REC_TARGET_ABORT    0x1000 /* Master ack of " */
+#define  PCI_STATUS_REC_MASTER_ABORT    0x2000 /* Set on master abort */
+#define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000 /* Set when we drive SERR */
+#define  PCI_STATUS_DETECTED_PARITY     0x8000 /* Set on parity error */
+#define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8 revision */
+#define PCI_REVISION_ID         0x08    /* Revision ID */
+#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE        0x0a    /* Device class */
+#define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
+#define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
+#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
+#define  PCI_HEADER_TYPE_NORMAL         0
+#define  PCI_HEADER_TYPE_BRIDGE         1
+#define  PCI_HEADER_TYPE_CARDBUS        2
+#define PCI_BIST                0x0f    /* 8 bits */
+#define  PCI_BIST_CODE_MASK     0x0f    /* Return result */
+#define  PCI_BIST_START         0x40    /* 1 to start BIST, 2 secs or less */
+#define  PCI_BIST_CAPABLE       0x80    /* 1 if BIST capable */
+/*
+ * Base addresses specify locations in memory or I/O space.
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
+ * 1 bits are decoded.
+ */
+#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
+#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
+#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
+#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
+#define  PCI_BASE_ADDRESS_SPACE         0x01    /* 0 = memory, 1 = I/O */
+#define  PCI_BASE_ADDRESS_SPACE_IO      0x01
+#define  PCI_BASE_ADDRESS_SPACE_MEMORY  0x00
+#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
+#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
+#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
+#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
+/* bit 1 is reserved if address_space = 1 */
+/* Header type 0 (normal devices) */
+#define PCI_CARDBUS_CIS         0x28
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+#define PCI_SUBSYSTEM_ID        0x2e
+#define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
+#define  PCI_ROM_ADDRESS_ENABLE 0x01
+#define PCI_ROM_ADDRESS_MASK    (~0x7ffUL)
+#define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
+/* 0x35-0x3b are reserved */
+#define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
+#define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
+#define PCI_MIN_GNT             0x3e    /* 8 bits */
+#define PCI_MAX_LAT             0x3f    /* 8 bits */
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
+#define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
+#define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
+#define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary interface */
+#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
+#define PCI_IO_LIMIT            0x1d
+#define  PCI_IO_RANGE_TYPE_MASK 0x0fUL  /* I/O bridging type */
+#define  PCI_IO_RANGE_TYPE_16   0x00
+#define  PCI_IO_RANGE_TYPE_32   0x01
+#define  PCI_IO_RANGE_MASK      (~0x0fUL)
+#define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
+#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
+#define PCI_MEMORY_LIMIT        0x22
+#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
+#define  PCI_MEMORY_RANGE_MASK  (~0x0fUL)
+#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT   0x26
+#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
+#define  PCI_PREF_RANGE_TYPE_32 0x00
+#define  PCI_PREF_RANGE_TYPE_64 0x01
+#define  PCI_PREF_RANGE_MASK    (~0x0fUL)
+#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
+#define PCI_PREF_LIMIT_UPPER32  0x2c
+#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
+#define PCI_IO_LIMIT_UPPER16    0x32
+/* 0x34 same as for htype 0 */
+/* 0x35-0x3b is reserved */
+#define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_BRIDGE_CONTROL      0x3e
+#define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
+#define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
+#define  PCI_BRIDGE_CTL_NO_ISA  0x04    /* Disable bridging of ISA ports */
+#define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
+#define  PCI_BRIDGE_CTL_MASTER_ABORT    0x20  /* Report master aborts */
+#define  PCI_BRIDGE_CTL_BUS_RESET       0x40    /* Secondary bus reset */
+#define  PCI_BRIDGE_CTL_FAST_BACK       0x80    /* Fast Back2Back enabled on secondary interface */
+/* Header type 2 (CardBus bridges) */
+#define PCI_CB_CAPABILITY_LIST  0x14
+/* 0x15 reserved */
+#define PCI_CB_SEC_STATUS       0x16    /* Secondary status */
+#define PCI_CB_PRIMARY_BUS      0x18    /* PCI bus number */
+#define PCI_CB_CARD_BUS         0x19    /* CardBus bus number */
+#define PCI_CB_SUBORDINATE_BUS  0x1a    /* Subordinate bus number */
+#define PCI_CB_LATENCY_TIMER    0x1b    /* CardBus latency timer */
+#define PCI_CB_MEMORY_BASE_0    0x1c
+#define PCI_CB_MEMORY_LIMIT_0   0x20
+#define PCI_CB_MEMORY_BASE_1    0x24
+#define PCI_CB_MEMORY_LIMIT_1   0x28
+#define PCI_CB_IO_BASE_0        0x2c
+#define PCI_CB_IO_BASE_0_HI     0x2e
+#define PCI_CB_IO_LIMIT_0       0x30
+#define PCI_CB_IO_LIMIT_0_HI    0x32
+#define PCI_CB_IO_BASE_1        0x34
+#define PCI_CB_IO_BASE_1_HI     0x36
+#define PCI_CB_IO_LIMIT_1       0x38
+#define PCI_CB_IO_LIMIT_1_HI    0x3a
+#define  PCI_CB_IO_RANGE_MASK   (~0x03UL)
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_CB_BRIDGE_CONTROL   0x3e
+#define  PCI_CB_BRIDGE_CTL_PARITY       0x01    /* Similar to standard bridge control register */
+#define  PCI_CB_BRIDGE_CTL_SERR         0x02
+#define  PCI_CB_BRIDGE_CTL_ISA          0x04
+#define  PCI_CB_BRIDGE_CTL_VGA          0x08
+#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
+#define  PCI_CB_BRIDGE_CTL_CB_RESET     0x40    /* CardBus reset */
+#define  PCI_CB_BRIDGE_CTL_16BIT_INT    0x80    /* Enable interrupt for 16-bit cards */
+#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100  /* Prefetch enable for both memory regions */
+#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
+#define  PCI_CB_BRIDGE_CTL_POST_WRITES  0x400
+#define PCI_CB_SUBSYSTEM_VENDOR_ID      0x40
+#define PCI_CB_SUBSYSTEM_ID             0x42
+#define PCI_CB_LEGACY_MODE_BASE         0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
+/* 0x48-0x7f reserved */
+/* Capability lists */
+#define PCI_CAP_LIST_ID         0       /* Capability ID */
+#define  PCI_CAP_ID_PM          0x01    /* Power Management */
+#define  PCI_CAP_ID_AGP         0x02    /* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD         0x03    /* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID      0x04    /* Slot Identification */
+#define  PCI_CAP_ID_MSI         0x05    /* Message Signalled Interrupts */
+#define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
+#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
+#define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
+#define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
+#define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
+#define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
+#define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF          4
+/* Power Management Registers */
+#define PCI_PM_PMC              2       /* PM Capabilities Register */
+#define  PCI_PM_CAP_VER_MASK    0x0007  /* Version */
+#define  PCI_PM_CAP_PME_CLOCK   0x0008  /* PME clock required */
+#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
+#define  PCI_PM_CAP_DSI         0x0020  /* Device specific initialization */
+#define  PCI_PM_CAP_AUX_POWER   0x01C0  /* Auxilliary power support mask */
+#define  PCI_PM_CAP_D1          0x0200  /* D1 power state support */
+#define  PCI_PM_CAP_D2          0x0400  /* D2 power state support */
+#define  PCI_PM_CAP_PME         0x0800  /* PME pin supported */
+#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
+#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
+#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
+#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
+#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
+#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
+#define PCI_PM_CTRL             4       /* PM control and status register */
+#define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
+#define  PCI_PM_CTRL_NO_SOFT_RESET      0x0004  /* No reset for D3hot->D0 */
+#define  PCI_PM_CTRL_PME_ENABLE 0x0100  /* PME pin enable */
+#define  PCI_PM_CTRL_DATA_SEL_MASK      0x1e00  /* Data select (??) */
+#define  PCI_PM_CTRL_DATA_SCALE_MASK    0x6000  /* Data scale (??) */
+#define  PCI_PM_CTRL_PME_STATUS 0x8000  /* PME pin status */
+#define PCI_PM_PPB_EXTENSIONS   6       /* PPB support extensions (??) */
+#define  PCI_PM_PPB_B2_B3       0x40    /* Stop clock when in D3hot (??) */
+#define  PCI_PM_BPCC_ENABLE     0x80    /* Bus power/clock control enable (??) */
+#define PCI_PM_DATA_REGISTER    7       /* (??) */
+#define PCI_PM_SIZEOF           8
+/* AGP registers */
+#define PCI_AGP_VERSION         2       /* BCD version number */
+#define PCI_AGP_RFU             3       /* Rest of capability flags */
+#define PCI_AGP_STATUS          4       /* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK 0xff000000      /* Maximum number of requests - 1 */
+#define  PCI_AGP_STATUS_SBA     0x0200  /* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT   0x0020  /* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW      0x0010  /* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4   0x0004  /* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2   0x0002  /* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1   0x0001  /* 1x transfer rate supported */
+#define PCI_AGP_COMMAND         8       /* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
+#define  PCI_AGP_COMMAND_SBA    0x0200  /* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP    0x0100  /* Allow processing of AGP transactions */
+#define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4  0x0004  /* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2  0x0002  /* Use 2x rate */
+#define  PCI_AGP_COMMAND_RATE1  0x0001  /* Use 1x rate */
+#define PCI_AGP_SIZEOF          12
+/* Vital Product Data */
+#define PCI_VPD_ADDR            2       /* Address to access (15 bits!) */
+#define  PCI_VPD_ADDR_MASK      0x7fff  /* Address mask */
+#define  PCI_VPD_ADDR_F         0x8000  /* Write 0, 1 indicates completion */
+#define PCI_VPD_DATA            4       /* 32-bits of data returned here */
+/* Slot Identification */
+#define PCI_SID_ESR             2       /* Expansion Slot Register */
+#define  PCI_SID_ESR_NSLOTS     0x1f    /* Number of expansion slots available */
+#define  PCI_SID_ESR_FIC        0x20    /* First In Chassis Flag */
+#define PCI_SID_CHASSIS_NR      3       /* Chassis Number */
+/* Message Signalled Interrupts registers */
+#define PCI_MSI_FLAGS           2       /* Various flags */
+#define  PCI_MSI_FLAGS_64BIT    0x80    /* 64-bit addresses allowed */
+#define  PCI_MSI_FLAGS_QSIZE    0x70    /* Message queue size configured */
+#define  PCI_MSI_FLAGS_QMASK    0x0e    /* Maximum queue size available */
+#define  PCI_MSI_FLAGS_ENABLE   0x01    /* MSI feature enabled */
+#define  PCI_MSI_FLAGS_MASKBIT  0x100   /* 64-bit mask bits allowed */
+#define PCI_MSI_RFU             3       /* Rest of capability flags */
+#define PCI_MSI_ADDRESS_LO      4       /* Lower 32 bits */
+#define PCI_MSI_ADDRESS_HI      8       /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
+#define PCI_MSI_DATA_32         8       /* 16 bits of data for 32-bit devices */
+#define PCI_MSI_DATA_64         12      /* 16 bits of data for 64-bit devices */
+#define PCI_MSI_MASK_BIT        16      /* Mask bits register */
+/* CompactPCI Hotswap Register */
+#define PCI_CHSWP_CSR           2       /* Control and Status Register */
+#define  PCI_CHSWP_DHA          0x01    /* Device Hiding Arm */
+#define  PCI_CHSWP_EIM          0x02    /* ENUM# Signal Mask */
+#define  PCI_CHSWP_PIE          0x04    /* Pending Insert or Extract */
+#define  PCI_CHSWP_LOO          0x08    /* LED On / Off */
+#define  PCI_CHSWP_PI           0x30    /* Programming Interface */
+#define  PCI_CHSWP_EXT          0x40    /* ENUM# status - extraction */
+#define  PCI_CHSWP_INS          0x80    /* ENUM# status - insertion */
+/* PCI-X registers */
+#define PCI_X_CMD               2       /* Modes & Features */
+#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
+#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
+#define  PCI_X_CMD_MAX_READ     0x000c  /* Max Memory Read Byte Count */
+#define  PCI_X_CMD_MAX_SPLIT    0x0070  /* Max Outstanding Split Transactions */
+#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
+#define PCI_X_STATUS            4       /* PCI-X capabilities */
+#define  PCI_X_STATUS_DEVFN     0x000000ff      /* A copy of devfn */
+#define  PCI_X_STATUS_BUS       0x0000ff00      /* A copy of bus nr */
+#define  PCI_X_STATUS_64BIT     0x00010000      /* 64-bit device */
+#define  PCI_X_STATUS_133MHZ    0x00020000      /* 133 MHz capable */
+#define  PCI_X_STATUS_SPL_DISC  0x00040000      /* Split Completion Discarded */
+#define  PCI_X_STATUS_UNX_SPL   0x00080000      /* Unexpected Split Completion */
+#define  PCI_X_STATUS_COMPLEX   0x00100000      /* Device Complexity */
+#define  PCI_X_STATUS_MAX_READ  0x00600000      /* Designed Max Memory Read Count */
+#define  PCI_X_STATUS_MAX_SPLIT 0x03800000      /* Designed Max Outstanding Split Transactions */
+#define  PCI_X_STATUS_MAX_CUM   0x1c000000      /* Designed Max Cumulative Read Size */
+#define  PCI_X_STATUS_SPL_ERR   0x20000000      /* Rcvd Split Completion Error Msg */
+#define  PCI_X_STATUS_266MHZ    0x40000000      /* 266 MHz capable */
+#define  PCI_X_STATUS_533MHZ    0x80000000      /* 533 MHz capable */
+/* PCI Express capability registers */
+#define PCI_EXP_FLAGS           2       /* Capabilities register */
+#define PCI_EXP_FLAGS_VERS      0x000f  /* Capability version */
+#define PCI_EXP_FLAGS_TYPE      0x00f0  /* Device/Port type */
+#define  PCI_EXP_TYPE_ENDPOINT  0x0     /* Express Endpoint */
+#define  PCI_EXP_TYPE_LEG_END   0x1     /* Legacy Endpoint */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4     /* Root Port */
+#define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
+#define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
+#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
+#define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
+#define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
+#define PCI_EXP_DEVCAP          4       /* Device capabilities */
+#define  PCI_EXP_DEVCAP_PAYLOAD 0x07    /* Max_Payload_Size */
+#define  PCI_EXP_DEVCAP_PHANTOM 0x18    /* Phantom functions */
+#define  PCI_EXP_DEVCAP_EXT_TAG 0x20    /* Extended tags */
+#define  PCI_EXP_DEVCAP_L0S     0x1c0   /* L0s Acceptable Latency */
+#define  PCI_EXP_DEVCAP_L1      0xe00   /* L1 Acceptable Latency */
+#define  PCI_EXP_DEVCAP_ATN_BUT 0x1000  /* Attention Button Present */
+#define  PCI_EXP_DEVCAP_ATN_IND 0x2000  /* Attention Indicator Present */
+#define  PCI_EXP_DEVCAP_PWR_IND 0x4000  /* Power Indicator Present */
+#define  PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
+#define  PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
+#define PCI_EXP_DEVCTL          8       /* Device Control */
+#define  PCI_EXP_DEVCTL_CERE    0x0001  /* Correctable Error Reporting En. */
+#define  PCI_EXP_DEVCTL_NFERE   0x0002  /* Non-Fatal Error Reporting Enable */
+#define  PCI_EXP_DEVCTL_FERE    0x0004  /* Fatal Error Reporting Enable */
+#define  PCI_EXP_DEVCTL_URRE    0x0008  /* Unsupported Request Reporting En. */
+#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
+#define  PCI_EXP_DEVCTL_PAYLOAD 0x00e0  /* Max_Payload_Size */
+#define  PCI_EXP_DEVCTL_EXT_TAG 0x0100  /* Extended Tag Field Enable */
+#define  PCI_EXP_DEVCTL_PHANTOM 0x0200  /* Phantom Functions Enable */
+#define  PCI_EXP_DEVCTL_AUX_PME 0x0400  /* Auxiliary Power PM Enable */
+#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
+#define  PCI_EXP_DEVCTL_READRQ  0x7000  /* Max_Read_Request_Size */
+#define PCI_EXP_DEVSTA          10      /* Device Status */
+#define  PCI_EXP_DEVSTA_CED     0x01    /* Correctable Error Detected */
+#define  PCI_EXP_DEVSTA_NFED    0x02    /* Non-Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_FED     0x04    /* Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_URD     0x08    /* Unsupported Request Detected */
+#define  PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
+#define  PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
+#define PCI_EXP_LNKCAP          12      /* Link Capabilities */
+#define PCI_EXP_LNKCTL          16      /* Link Control */
+#define PCI_EXP_LNKSTA          18      /* Link Status */
+#define PCI_EXP_SLTCAP          20      /* Slot Capabilities */
+#define PCI_EXP_SLTCTL          24      /* Slot Control */
+#define PCI_EXP_SLTSTA          26      /* Slot Status */
+#define PCI_EXP_RTCTL           28      /* Root Control */
+#define  PCI_EXP_RTCTL_SECEE    0x01    /* System Error on Correctable Error */
+#define  PCI_EXP_RTCTL_SENFEE   0x02    /* System Error on Non-Fatal Error */
+#define  PCI_EXP_RTCTL_SEFEE    0x04    /* System Error on Fatal Error */
+#define  PCI_EXP_RTCTL_PMEIE    0x08    /* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_CRSSVE   0x10    /* CRS Software Visibility Enable */
+#define PCI_EXP_RTCAP           30      /* Root Capabilities */
+#define PCI_EXP_RTSTA           32      /* Root Status */
+/* Extended Capabilities (PCI-X 2.0 and Express) */
+#define PCI_EXT_CAP_ID(header)          (header & 0x0000ffff)
+#define PCI_EXT_CAP_VER(header)         ((header >> 16) & 0xf)
+#define PCI_EXT_CAP_NEXT(header)        ((header >> 20) & 0xffc)
+#define PCI_EXT_CAP_ID_ERR      1
+#define PCI_EXT_CAP_ID_VC       2
+#define PCI_EXT_CAP_ID_DSN      3
+#define PCI_EXT_CAP_ID_PWR      4
+/* Advanced Error Reporting */
+#define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
+#define  PCI_ERR_UNC_TRAIN      0x00000001      /* Training */
+#define  PCI_ERR_UNC_DLP        0x00000010      /* Data Link Protocol */
+#define  PCI_ERR_UNC_POISON_TLP 0x00001000      /* Poisoned TLP */
+#define  PCI_ERR_UNC_FCP        0x00002000      /* Flow Control Protocol */
+#define  PCI_ERR_UNC_COMP_TIME  0x00004000      /* Completion Timeout */
+#define  PCI_ERR_UNC_COMP_ABORT 0x00008000      /* Completer Abort */
+#define  PCI_ERR_UNC_UNX_COMP   0x00010000      /* Unexpected Completion */
+#define  PCI_ERR_UNC_RX_OVER    0x00020000      /* Receiver Overflow */
+#define  PCI_ERR_UNC_MALF_TLP   0x00040000      /* Malformed TLP */
+#define  PCI_ERR_UNC_ECRC       0x00080000      /* ECRC Error Status */
+#define  PCI_ERR_UNC_UNSUP      0x00100000      /* Unsupported Request */
+#define PCI_ERR_UNCOR_MASK      8       /* Uncorrectable Error Mask */
+        /* Same bits as above */
+#define PCI_ERR_UNCOR_SEVER     12      /* Uncorrectable Error Severity */
+        /* Same bits as above */
+#define PCI_ERR_COR_STATUS      16      /* Correctable Error Status */
+#define  PCI_ERR_COR_RCVR       0x00000001      /* Receiver Error Status */
+#define  PCI_ERR_COR_BAD_TLP    0x00000040      /* Bad TLP Status */
+#define  PCI_ERR_COR_BAD_DLLP   0x00000080      /* Bad DLLP Status */
+#define  PCI_ERR_COR_REP_ROLL   0x00000100      /* REPLAY_NUM Rollover */
+#define  PCI_ERR_COR_REP_TIMER  0x00001000      /* Replay Timer Timeout */
+#define PCI_ERR_COR_MASK        20      /* Correctable Error Mask */
+        /* Same bits as above */
+#define PCI_ERR_CAP             24      /* Advanced Error Capabilities */
+#define  PCI_ERR_CAP_FEP(x)     ((x) & 31)      /* First Error Pointer */
+#define  PCI_ERR_CAP_ECRC_GENC  0x00000020      /* ECRC Generation Capable */
+#define  PCI_ERR_CAP_ECRC_GENE  0x00000040      /* ECRC Generation Enable */
+#define  PCI_ERR_CAP_ECRC_CHKC  0x00000080      /* ECRC Check Capable */
+#define  PCI_ERR_CAP_ECRC_CHKE  0x00000100      /* ECRC Check Enable */
+#define PCI_ERR_HEADER_LOG      28      /* Header Log Register (16 bytes) */
+#define PCI_ERR_ROOT_COMMAND    44      /* Root Error Command */
+#define PCI_ERR_ROOT_STATUS     48
+#define PCI_ERR_ROOT_COR_SRC    52
+#define PCI_ERR_ROOT_SRC        54
+/* Virtual Channel */
+#define PCI_VC_PORT_REG1        4
+#define PCI_VC_PORT_REG2        8
+#define PCI_VC_PORT_CTRL        12
+#define PCI_VC_PORT_STATUS      14
+#define PCI_VC_RES_CAP          16
+#define PCI_VC_RES_CTRL         20
+#define PCI_VC_RES_STATUS       26
+/* Power Budgeting */
+#define PCI_PWR_DSR             4       /* Data Select Register */
+#define PCI_PWR_DATA            8       /* Data Register */
+#define  PCI_PWR_DATA_BASE(x)   ((x) & 0xff)        /* Base Power */
+#define  PCI_PWR_DATA_SCALE(x)  (((x) >> 8) & 3)    /* Data Scale */
+#define  PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)   /* PM Sub State */
+#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
+#define  PCI_PWR_DATA_TYPE(x)   (((x) >> 15) & 7)   /* Type */
+#define  PCI_PWR_DATA_RAIL(x)   (((x) >> 18) & 7)   /* Power Rail */
+#define PCI_PWR_CAP             12      /* Capability */
+#define  PCI_PWR_CAP_BUDGET(x)  ((x) & 1)       /* Included in system budget */
+#endif /* LINUX_PCI_REGS_H */
diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
index d8a023d804d4..317a979b24de 100644
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -30,6 +30,21 @@ struct plat_serial8250_port {
 };
 /*
+ * Allocate 8250 platform device IDs.  Nothing is implied by
+ * the numbering here, except for the legacy entry being -1.
+ */
+enum {
+        PLAT8250_DEV_LEGACY = -1,
+        PLAT8250_DEV_PLATFORM,
+        PLAT8250_DEV_PLATFORM1,
+        PLAT8250_DEV_FOURPORT,
+        PLAT8250_DEV_ACCENT,
+        PLAT8250_DEV_BOCA,
+        PLAT8250_DEV_HUB6,
+        PLAT8250_DEV_MCA,
+};
+/*
 * This should be used by drivers which want to register
 * their own 8250 ports without registering their own
 * platform device.  Using these will make your driver
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 9b12fe731612..27db8da43aa4 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -401,6 +401,9 @@ uart_handle_sysrq_char(struct uart_port *port, unsigned int ch,
 #endif
        return 0;
 }
+#ifndef SUPPORT_SYSRQ
+#define uart_handle_sysrq_char(port,ch,regs) uart_handle_sysrq_char(port, 0, NULL)
+#endif
 /*
 * We do the SysRQ and SAK checking like this...
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 724637792996..4dbe580f9335 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -5,6 +5,7 @@
 #include <linux/usb_ch9.h>
 #define USB_MAJOR                       180
+#define USB_DEVICE_MAJOR                189
 #ifdef __KERNEL__
@@ -349,6 +350,7 @@ struct usb_device {
        char *manufacturer;
        char *serial;                   /* static strings from the device */
        struct list_head filelist;
+        struct class_device *class_dev;
        struct dentry *usbfs_dentry;    /* usbfs dentry entry for the device */
        /*
@@ -614,7 +616,6 @@ extern int usb_disabled(void);
 #define URB_ISO_ASAP            0x0002  /* iso-only, urb->start_frame ignored */
 #define URB_NO_TRANSFER_DMA_MAP 0x0004  /* urb->transfer_dma valid on submit */
 #define URB_NO_SETUP_DMA_MAP    0x0008  /* urb->setup_dma valid on submit */
-#define URB_ASYNC_UNLINK        0x0010  /* usb_unlink_urb() returns asap */
 #define URB_NO_FSBR             0x0020  /* UHCI-specific */
 #define URB_ZERO_PACKET         0x0040  /* Finish bulk OUTs with short packet */
 #define URB_NO_INTERRUPT        0x0080  /* HINT: no non-error interrupt needed */
@@ -722,13 +723,7 @@ typedef void (*usb_complete_t)(struct urb *, struct pt_regs *);
 * Initialization:
 *
 * All URBs submitted must initialize the dev, pipe, transfer_flags (may be
- * zero), and complete fields.
+ * zero), and complete fields.  All URBs must also initialize
- * The URB_ASYNC_UNLINK transfer flag affects later invocations of
- * the usb_unlink_urb() routine.  Note: Failure to set URB_ASYNC_UNLINK
- * with usb_unlink_urb() is deprecated.  For synchronous unlinks use
- * usb_kill_urb() instead.
- *
- * All URBs must also initialize 
 * transfer_buffer and transfer_buffer_length.  They may provide the
 * URB_SHORT_NOT_OK transfer flag, indicating that short reads are
 * to be treated as errors; that flag is invalid for write requests.
diff --git a/include/linux/usb_isp116x.h b/include/linux/usb_isp116x.h
index 5f5a9d9bd6c2..436dd8a2b64a 100644
--- a/include/linux/usb_isp116x.h
+++ b/include/linux/usb_isp116x.h
@@ -7,36 +7,18 @@
 struct isp116x_platform_data {
        /* Enable internal resistors on downstream ports */
        unsigned sel15Kres:1;
-        /* Chip's internal clock won't be stopped in suspended state.
+        /* On-chip overcurrent detection */
-           Setting/unsetting this bit takes effect only if
-           'remote_wakeup_enable' below is not set. */
-        unsigned clknotstop:1;
-        /* On-chip overcurrent protection */
        unsigned oc_enable:1;
        /* INT output polarity */
        unsigned int_act_high:1;
        /* INT edge or level triggered */
        unsigned int_edge_triggered:1;
-        /* WAKEUP pin connected - NOT SUPPORTED  */
+        /* Enable wakeup by devices on usb bus (e.g. wakeup
-        /* unsigned remote_wakeup_connected:1; */
+           by attachment/detachment or by device activity
-        /* Wakeup by devices on usb bus enabled */
+           such as moving a mouse). When chosen, this option
+           prevents stopping internal clock, increasing
+           thereby power consumption in suspended state. */
        unsigned remote_wakeup_enable:1;
-        /* Switch or not to switch (keep always powered) */
-        unsigned no_power_switching:1;
-        /* Ganged port power switching (0) or individual port
-           power switching (1) */
-        unsigned power_switching_mode:1;
-        /* Given port_power, msec/2 after power on till power good */
-        u8 potpg;
-        /* Hardware reset set/clear. If implemented, this function must:
-           if set == 0,   deassert chip's HW reset pin
-           otherwise,     assert chip's HW reset pin       */
-        void (*reset) (struct device * dev, int set);
-        /* Hardware clock start/stop. If implemented, this function must:
-           if start == 0,    stop the external clock
-           otherwise,        start the external clock
-         */
-        void (*clock) (struct device * dev, int start);
        /* Inter-io delay (ns). The chip is picky about access timings; it
           expects at least:
           150ns delay between consecutive accesses to DATA_REG,