156 files changed, 4225 insertions, 3509 deletions
diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h
index 805ae3575e44..345a649ec838 100644
--- a/include/asm-arm/arch-omap/irda.h
+++ b/include/asm-arm/arch-omap/irda.h
@@ -24,7 +24,7 @@ struct omap_irda_config {
        /* Very specific to the needs of some platforms (h3,h4)
         * having calls which can sleep in irda_set_speed.
         */
-        struct work_struct gpio_expa;
+        struct delayed_work gpio_expa;
        int rx_channel;
        int tx_channel;
        unsigned long dest_start;
diff --git a/include/asm-avr32/types.h b/include/asm-avr32/types.h
index 3f47db9675af..2bff153a32ed 100644
--- a/include/asm-avr32/types.h
+++ b/include/asm-avr32/types.h
@@ -57,11 +57,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-h8300/types.h b/include/asm-h8300/types.h
index da2402b86540..2a8b1b2be782 100644
--- a/include/asm-h8300/types.h
+++ b/include/asm-h8300/types.h
@@ -55,12 +55,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
-#define HAVE_SECTOR_T
-typedef u64 sector_t;
-#define HAVE_BLKCNT_T
-typedef u64 blkcnt_t;
 #endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h
index 51a166242522..a6c024e2506f 100644
--- a/include/asm-i386/atomic.h
+++ b/include/asm-i386/atomic.h
@@ -14,7 +14,7 @@
 * on us. We need to use _exactly_ the address the user gave us,
 * not some alias that contains the same information.
 */
-typedef struct { volatile int counter; } atomic_t;
+typedef struct { int counter; } atomic_t;
 #define ATOMIC_INIT(i)  { (i) }
diff --git a/include/asm-i386/spinlock_types.h b/include/asm-i386/spinlock_types.h
index 59efe849f351..4da9345c1500 100644
--- a/include/asm-i386/spinlock_types.h
+++ b/include/asm-i386/spinlock_types.h
@@ -6,13 +6,13 @@
 #endif
 typedef struct {
-        volatile unsigned int slock;
+        unsigned int slock;
 } raw_spinlock_t;
 #define __RAW_SPIN_LOCK_UNLOCKED        { 1 }
 typedef struct {
-        volatile unsigned int lock;
+        unsigned int lock;
 } raw_rwlock_t;
 #define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h
index 4b4b295ccdb9..ad0a55bd782f 100644
--- a/include/asm-i386/types.h
+++ b/include/asm-i386/types.h
@@ -57,16 +57,6 @@ typedef u32 dma_addr_t;
 #endif
 typedef u64 dma64_addr_t;
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
-#ifdef CONFIG_LSF
-typedef u64 blkcnt_t;
-#define HAVE_BLKCNT_T
-#endif
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-m68knommu/irq.h b/include/asm-m68knommu/irq.h
index 45e7a2fd1689..7b8f874f8429 100644
--- a/include/asm-m68knommu/irq.h
+++ b/include/asm-m68knommu/irq.h
@@ -86,5 +86,6 @@ extern void (*mach_disable_irq)(unsigned int);
 #define enable_irq(x)   do { } while (0)
 #define disable_irq(x)  do { } while (0)
 #define disable_irq_nosync(x)   disable_irq(x)
+#define irq_canonicalize(irq)   (irq)
 #endif /* _M68K_IRQ_H_ */
diff --git a/include/asm-m68knommu/rtc.h b/include/asm-m68knommu/rtc.h
new file mode 100644
index 000000000000..eaf18ec83c8e
--- /dev/null
+++ b/include/asm-m68knommu/rtc.h
@@ -0,0 +1 @@
+#include <asm-m68k/rtc.h>
diff --git a/include/asm-m68knommu/ucontext.h b/include/asm-m68knommu/ucontext.h
index 5d570cedbb02..713a27f901cd 100644
--- a/include/asm-m68knommu/ucontext.h
+++ b/include/asm-m68knommu/ucontext.h
@@ -5,21 +5,17 @@ typedef int greg_t;
 #define NGREG 18
 typedef greg_t gregset_t[NGREG];
-#ifdef CONFIG_FPU
 typedef struct fpregset {
        int f_pcr;
        int f_psr;
        int f_fpiaddr;
        int f_fpregs[8][3];
 } fpregset_t;
-#endif
 struct mcontext {
        int version;
        gregset_t gregs;
-#ifdef CONFIG_FPU
        fpregset_t fpregs;
-#endif
 };
 #define MCONTEXT_VERSION 2
@@ -29,9 +25,7 @@ struct ucontext {
        struct ucontext  *uc_link;
        stack_t           uc_stack;
        struct mcontext   uc_mcontext;
-#ifdef CONFIG_FPU
        unsigned long     uc_filler[80];
-#endif
        sigset_t          uc_sigmask;   /* mask last for extensibility */
 };
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 7978d8e11647..c1a2409bb52a 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -15,6 +15,7 @@
 #define _ASM_ATOMIC_H
 #include <linux/irqflags.h>
+#include <asm/barrier.h>
 #include <asm/cpu-features.h>
 #include <asm/war.h>
@@ -130,6 +131,8 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
 {
        unsigned long result;
+        smp_mb();
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                unsigned long temp;
@@ -140,7 +143,6 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                "       sc      %0, %2                                  \n"
                "       beqzl   %0, 1b                                  \n"
                "       addu    %0, %1, %3                              \n"
-                "       sync                                            \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
@@ -155,7 +157,6 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                "       sc      %0, %2                                  \n"
                "       beqz    %0, 1b                                  \n"
                "       addu    %0, %1, %3                              \n"
-                "       sync                                            \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
@@ -170,6 +171,8 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                local_irq_restore(flags);
        }
+        smp_mb();
        return result;
 }
@@ -177,6 +180,8 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
 {
        unsigned long result;
+        smp_mb();
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                unsigned long temp;
@@ -187,7 +192,6 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                "       sc      %0, %2                                  \n"
                "       beqzl   %0, 1b                                  \n"
                "       subu    %0, %1, %3                              \n"
-                "       sync                                            \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
@@ -202,7 +206,6 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                "       sc      %0, %2                                  \n"
                "       beqz    %0, 1b                                  \n"
                "       subu    %0, %1, %3                              \n"
-                "       sync                                            \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
@@ -217,6 +220,8 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                local_irq_restore(flags);
        }
+        smp_mb();
        return result;
 }
@@ -232,6 +237,8 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
 {
        unsigned long result;
+        smp_mb();
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                unsigned long temp;
@@ -245,7 +252,6 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                "       beqzl   %0, 1b                                  \n"
                "        subu   %0, %1, %3                              \n"
                "       .set    reorder                                 \n"
-                "       sync                                            \n"
                "1:                                                     \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
@@ -264,7 +270,6 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                "       beqz    %0, 1b                                  \n"
                "        subu   %0, %1, %3                              \n"
                "       .set    reorder                                 \n"
-                "       sync                                            \n"
                "1:                                                     \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
@@ -281,6 +286,8 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                local_irq_restore(flags);
        }
+        smp_mb();
        return result;
 }
@@ -375,7 +382,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
 #ifdef CONFIG_64BIT
-typedef struct { volatile __s64 counter; } atomic64_t;
+typedef struct { volatile long counter; } atomic64_t;
 #define ATOMIC64_INIT(i)    { (i) }
@@ -484,6 +491,8 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 {
        unsigned long result;
+        smp_mb();
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                unsigned long temp;
@@ -494,7 +503,6 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                "       scd     %0, %2                                  \n"
                "       beqzl   %0, 1b                                  \n"
                "       addu    %0, %1, %3                              \n"
-                "       sync                                            \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
@@ -509,7 +517,6 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                "       scd     %0, %2                                  \n"
                "       beqz    %0, 1b                                  \n"
                "       addu    %0, %1, %3                              \n"
-                "       sync                                            \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
@@ -524,6 +531,8 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                local_irq_restore(flags);
        }
+        smp_mb();
        return result;
 }
@@ -531,6 +540,8 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
 {
        unsigned long result;
+        smp_mb();
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                unsigned long temp;
@@ -541,7 +552,6 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                "       scd     %0, %2                                  \n"
                "       beqzl   %0, 1b                                  \n"
                "       subu    %0, %1, %3                              \n"
-                "       sync                                            \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
@@ -556,7 +566,6 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                "       scd     %0, %2                                  \n"
                "       beqz    %0, 1b                                  \n"
                "       subu    %0, %1, %3                              \n"
-                "       sync                                            \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
@@ -571,6 +580,8 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                local_irq_restore(flags);
        }
+        smp_mb();
        return result;
 }
@@ -586,6 +597,8 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
 {
        unsigned long result;
+        smp_mb();
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                unsigned long temp;
@@ -599,7 +612,6 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                "       beqzl   %0, 1b                                  \n"
                "        dsubu  %0, %1, %3                              \n"
                "       .set    reorder                                 \n"
-                "       sync                                            \n"
                "1:                                                     \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
@@ -618,7 +630,6 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                "       beqz    %0, 1b                                  \n"
                "        dsubu  %0, %1, %3                              \n"
                "       .set    reorder                                 \n"
-                "       sync                                            \n"
                "1:                                                     \n"
                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
@@ -635,6 +646,8 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                local_irq_restore(flags);
        }
+        smp_mb();
        return result;
 }
diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h
new file mode 100644
index 000000000000..ed82631b0017
--- /dev/null
+++ b/include/asm-mips/barrier.h
@@ -0,0 +1,132 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+/*
+ * read_barrier_depends - Flush all pending reads that subsequents reads
+ * depend on.
+ *
+ * No data-dependent reads from memory-like regions are ever reordered
+ * over this barrier.  All reads preceding this primitive are guaranteed
+ * to access memory (but not necessarily other CPUs' caches) before any
+ * reads following this primitive that depend on the data return by
+ * any of the preceding reads.  This primitive is much lighter weight than
+ * rmb() on most CPUs, and is never heavier weight than is
+ * rmb().
+ *
+ * These ordering constraints are respected by both the local CPU
+ * and the compiler.
+ *
+ * Ordering is not guaranteed by anything other than these primitives,
+ * not even by data dependencies.  See the documentation for
+ * memory_barrier() for examples and URLs to more information.
+ *
+ * For example, the following code would force ordering (the initial
+ * value of "a" is zero, "b" is one, and "p" is "&a"):
+ *
+ * <programlisting>
+ *      CPU 0                           CPU 1
+ *
+ *      b = 2;
+ *      memory_barrier();
+ *      p = &b;                         q = p;
+ *                                      read_barrier_depends();
+ *                                      d = *q;
+ * </programlisting>
+ *
+ * because the read of "*q" depends on the read of "p" and these
+ * two reads are separated by a read_barrier_depends().  However,
+ * the following code, with the same initial values for "a" and "b":
+ *
+ * <programlisting>
+ *      CPU 0                           CPU 1
+ *
+ *      a = 2;
+ *      memory_barrier();
+ *      b = 3;                          y = b;
+ *                                      read_barrier_depends();
+ *                                      x = a;
+ * </programlisting>
+ *
+ * does not enforce ordering, since there is no data dependency between
+ * the read of "a" and the read of "b".  Therefore, on some CPUs, such
+ * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
+ * in cases like this where there are no data dependencies.
+ */
+#define read_barrier_depends()          do { } while(0)
+#define smp_read_barrier_depends()      do { } while(0)
+#ifdef CONFIG_CPU_HAS_SYNC
+#define __sync()                                \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                ".set   mips2\n\t"              \
+                "sync\n\t"                      \
+                ".set   pop"                    \
+                : /* no output */               \
+                : /* no input */                \
+                : "memory")
+#else
+#define __sync()        do { } while(0)
+#endif
+#define __fast_iob()                            \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                "lw     $0,%0\n\t"              \
+                "nop\n\t"                       \
+                ".set   pop"                    \
+                : /* no output */               \
+                : "m" (*(int *)CKSEG1)          \
+                : "memory")
+#define fast_wmb()      __sync()
+#define fast_rmb()      __sync()
+#define fast_mb()       __sync()
+#define fast_iob()                              \
+        do {                                    \
+                __sync();                       \
+                __fast_iob();                   \
+        } while (0)
+#ifdef CONFIG_CPU_HAS_WB
+#include <asm/wbflush.h>
+#define wmb()           fast_wmb()
+#define rmb()           fast_rmb()
+#define mb()            wbflush()
+#define iob()           wbflush()
+#else /* !CONFIG_CPU_HAS_WB */
+#define wmb()           fast_wmb()
+#define rmb()           fast_rmb()
+#define mb()            fast_mb()
+#define iob()           fast_iob()
+#endif /* !CONFIG_CPU_HAS_WB */
+#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
+#define __WEAK_ORDERING_MB      "       sync    \n"
+#else
+#define __WEAK_ORDERING_MB      "               \n"
+#endif
+#define smp_mb()        __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
+#define smp_rmb()       __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
+#define smp_wmb()       __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
+#define set_mb(var, value) \
+        do { var = value; smp_mb(); } while (0)
+#endif /* __ASM_BARRIER_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index b9007411b60f..06445de1324b 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -3,7 +3,7 @@
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
- * Copyright (c) 1994 - 1997, 1999, 2000  Ralf Baechle (ralf@gnu.org)
+ * Copyright (c) 1994 - 1997, 1999, 2000, 06  Ralf Baechle (ralf@linux-mips.org)
 * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
 */
 #ifndef _ASM_BITOPS_H
@@ -12,6 +12,7 @@
 #include <linux/compiler.h>
 #include <linux/irqflags.h>
 #include <linux/types.h>
+#include <asm/barrier.h>
 #include <asm/bug.h>
 #include <asm/byteorder.h>              /* sigh ... */
 #include <asm/cpu-features.h>
@@ -204,9 +205,6 @@ static inline int test_and_set_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -226,9 +224,6 @@ static inline int test_and_set_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -250,6 +245,8 @@ static inline int test_and_set_bit(unsigned long nr,
                return retval;
        }
+        smp_mb();
 }
 /*
@@ -275,9 +272,6 @@ static inline int test_and_clear_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -298,9 +292,6 @@ static inline int test_and_clear_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -322,6 +313,8 @@ static inline int test_and_clear_bit(unsigned long nr,
                return retval;
        }
+        smp_mb();
 }
 /*
@@ -346,9 +339,6 @@ static inline int test_and_change_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -368,9 +358,6 @@ static inline int test_and_change_bit(unsigned long nr,
                "       " __SC  "\t%2, %1                               \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -391,6 +378,8 @@ static inline int test_and_change_bit(unsigned long nr,
                return retval;
        }
+        smp_mb();
 }
 #include <asm-generic/bitops/non-atomic.h>
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
index 900f472fdd2b..55a0152feb08 100644
--- a/include/asm-mips/compat.h
+++ b/include/asm-mips/compat.h
@@ -32,6 +32,7 @@ typedef struct {
        s32     val[2];
 } compat_fsid_t;
 typedef s32             compat_timer_t;
+typedef s32             compat_key_t;
 typedef s32             compat_int_t;
 typedef s32             compat_long_t;
@@ -146,4 +147,71 @@ static inline void __user *compat_alloc_user_space(long len)
        return (void __user *) (regs->regs[29] - len);
 }
+struct compat_ipc64_perm {
+        compat_key_t key;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
+        compat_mode_t mode;
+        unsigned short seq;
+        unsigned short __pad2;
+        compat_ulong_t __unused1;
+        compat_ulong_t __unused2;
+};
+struct compat_semid64_ds {
+        struct compat_ipc64_perm sem_perm;
+        compat_time_t   sem_otime;
+        compat_time_t   sem_ctime;
+        compat_ulong_t  sem_nsems;
+        compat_ulong_t  __unused1;
+        compat_ulong_t  __unused2;
+};
+struct compat_msqid64_ds {
+        struct compat_ipc64_perm msg_perm;
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused1;
+#endif
+        compat_time_t   msg_stime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused1;
+#endif
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused2;
+#endif
+        compat_time_t   msg_rtime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused2;
+#endif
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused3;
+#endif
+        compat_time_t   msg_ctime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused3;
+#endif
+        compat_ulong_t  msg_cbytes;
+        compat_ulong_t  msg_qnum;
+        compat_ulong_t  msg_qbytes;
+        compat_pid_t    msg_lspid;
+        compat_pid_t    msg_lrpid;
+        compat_ulong_t  __unused4;
+        compat_ulong_t  __unused5;
+};
+struct compat_shmid64_ds {
+        struct compat_ipc64_perm shm_perm;
+        compat_size_t   shm_segsz;
+        compat_time_t   shm_atime;
+        compat_time_t   shm_dtime;
+        compat_time_t   shm_ctime;
+        compat_pid_t    shm_cpid;
+        compat_pid_t    shm_lpid;
+        compat_ulong_t  shm_nattch;
+        compat_ulong_t  __unused1;
+        compat_ulong_t  __unused2;
+};
 #endif /* _ASM_COMPAT_H */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index ed023eae0674..927a216bd530 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -1,19 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2006  Ralf Baechle (ralf@linux-mips.org)
+ */
 #ifndef _ASM_FUTEX_H
 #define _ASM_FUTEX_H
 #ifdef __KERNEL__
 #include <linux/futex.h>
+#include <asm/barrier.h>
 #include <asm/errno.h>
 #include <asm/uaccess.h>
 #include <asm/war.h>
-#ifdef CONFIG_SMP
-#define __FUTEX_SMP_SYNC "      sync                                    \n"
-#else
-#define __FUTEX_SMP_SYNC
-#endif
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)              \
 {                                                                       \
        if (cpu_has_llsc && R10000_LLSC_WAR) {                          \
@@ -27,7 +29,7 @@
                "       .set    mips3                           \n"     \
                "2:     sc      $1, %2                          \n"     \
                "       beqzl   $1, 1b                          \n"     \
-                __FUTEX_SMP_SYNC                                        \
+                __WEAK_ORDERING_MB                                      \
                "3:                                             \n"     \
                "       .set    pop                             \n"     \
                "       .set    mips0                           \n"     \
@@ -53,7 +55,7 @@
                "       .set    mips3                           \n"     \
                "2:     sc      $1, %2                          \n"     \
                "       beqz    $1, 1b                          \n"     \
-                __FUTEX_SMP_SYNC                                        \
+                __WEAK_ORDERING_MB                                      \
                "3:                                             \n"     \
                "       .set    pop                             \n"     \
                "       .set    mips0                           \n"     \
@@ -150,7 +152,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
                "       .set    mips3                                   \n"
                "2:     sc      $1, %1                                  \n"
                "       beqzl   $1, 1b                                  \n"
-                __FUTEX_SMP_SYNC
+                __WEAK_ORDERING_MB
                "3:                                                     \n"
                "       .set    pop                                     \n"
                "       .section .fixup,\"ax\"                          \n"
@@ -177,7 +179,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
                "       .set    mips3                                   \n"
                "2:     sc      $1, %1                                  \n"
                "       beqz    $1, 1b                                  \n"
-                __FUTEX_SMP_SYNC
+                __WEAK_ORDERING_MB
                "3:                                                     \n"
                "       .set    pop                                     \n"
                "       .section .fixup,\"ax\"                          \n"
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h
index 0214abe3f0af..4df8d8b118c0 100644
--- a/include/asm-mips/i8259.h
+++ b/include/asm-mips/i8259.h
@@ -19,10 +19,31 @@
 #include <asm/io.h>
+/* i8259A PIC registers */
+#define PIC_MASTER_CMD          0x20
+#define PIC_MASTER_IMR          0x21
+#define PIC_MASTER_ISR          PIC_MASTER_CMD
+#define PIC_MASTER_POLL         PIC_MASTER_ISR
+#define PIC_MASTER_OCW3         PIC_MASTER_ISR
+#define PIC_SLAVE_CMD           0xa0
+#define PIC_SLAVE_IMR           0xa1
+/* i8259A PIC related value */
+#define PIC_CASCADE_IR          2
+#define MASTER_ICW4_DEFAULT     0x01
+#define SLAVE_ICW4_DEFAULT      0x01
+#define PIC_ICW4_AEOI           2
 extern spinlock_t i8259A_lock;
+extern void init_8259A(int auto_eoi);
+extern void enable_8259A_irq(unsigned int irq);
+extern void disable_8259A_irq(unsigned int irq);
 extern void init_i8259_irqs(void);
+#define I8259A_IRQ_BASE 0
 /*
 * Do the traditional i8259 interrupt polling thing.  This is for the few
 * cases where no better interrupt acknowledge method is available and we
@@ -35,15 +56,15 @@ static inline int i8259_irq(void)
        spin_lock(&i8259A_lock);
        /* Perform an interrupt acknowledge cycle on controller 1. */
-        outb(0x0C, 0x20);               /* prepare for poll */
+        outb(0x0C, PIC_MASTER_CMD);             /* prepare for poll */
-        irq = inb(0x20) & 7;
+        irq = inb(PIC_MASTER_CMD) & 7;
-        if (irq == 2) {
+        if (irq == PIC_CASCADE_IR) {
                /*
                 * Interrupt is cascaded so perform interrupt
                 * acknowledge on controller 2.
                 */
-                outb(0x0C, 0xA0);               /* prepare for poll */
+                outb(0x0C, PIC_SLAVE_CMD);              /* prepare for poll */
-                irq = (inb(0xA0) & 7) + 8;
+                irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
        }
        if (unlikely(irq == 7)) {
@@ -54,14 +75,14 @@ static inline int i8259_irq(void)
                 * significant bit is not set then there is no valid
                 * interrupt.
                 */
-                outb(0x0B, 0x20);               /* ISR register */
+                outb(0x0B, PIC_MASTER_ISR);             /* ISR register */
-                if(~inb(0x20) & 0x80)
+                if(~inb(PIC_MASTER_ISR) & 0x80)
                        irq = -1;
        }
        spin_unlock(&i8259A_lock);
-        return irq;
+        return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
 }
 #endif /* _ASM_I8259_H */
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index d20f2e9b28be..2fbd47eba32d 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -156,9 +156,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define __pte_offset(address)                                           \
        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 #define pte_offset(dir, address)                                        \
-        ((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-#define pte_offset_kernel(dir, address) \
+#define pte_offset_kernel(dir, address)                                 \
-        ((pte_t *) pmd_page_vaddr(*(dir)) +  __pte_offset(address))
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 #define pte_offset_map(dir, address)                                    \
        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index b9b1e86493ee..a5b18710b6a4 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -212,9 +212,9 @@ static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
 #define __pte_offset(address)                                           \
        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 #define pte_offset(dir, address)                                        \
-        ((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 #define pte_offset_kernel(dir, address)                                 \
-        ((pte_t *) pmd_page_vaddr(*(dir)) +  __pte_offset(address))
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 #define pte_offset_map(dir, address)                                    \
        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
 #define pte_offset_map_nested(dir, address)                             \
diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h
index b63cd0655b3d..15d70ca56187 100644
--- a/include/asm-mips/sn/klconfig.h
+++ b/include/asm-mips/sn/klconfig.h
@@ -176,7 +176,7 @@ typedef struct kl_config_hdr {
 /* --- New Macros for the changed kl_config_hdr_t structure --- */
 #define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
-                        (unsigned long)_k + (_k->ch_malloc_hdr_off)))
+                        ((unsigned long)_k + (_k->ch_malloc_hdr_off)))
 #define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index c8d5587467bb..fc3217fc1118 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -3,12 +3,13 @@
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
- * Copyright (C) 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 06 by Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 */
 #ifndef _ASM_SPINLOCK_H
 #define _ASM_SPINLOCK_H
+#include <asm/barrier.h>
 #include <asm/war.h>
 /*
@@ -40,7 +41,6 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
                "       sc      %1, %0                                  \n"
                "       beqzl   %1, 1b                                  \n"
                "        nop                                            \n"
-                "       sync                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (lock->lock), "=&r" (tmp)
                : "m" (lock->lock)
@@ -53,19 +53,22 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
                "        li     %1, 1                                   \n"
                "       sc      %1, %0                                  \n"
                "       beqz    %1, 1b                                  \n"
-                "        sync                                           \n"
+                "        nop                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (lock->lock), "=&r" (tmp)
                : "m" (lock->lock)
                : "memory");
        }
+        smp_mb();
 }
 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 {
+        smp_mb();
        __asm__ __volatile__(
        "       .set    noreorder       # __raw_spin_unlock     \n"
-        "       sync                                            \n"
        "       sw      $0, %0                                  \n"
        "       .set\treorder                                   \n"
        : "=m" (lock->lock)
@@ -86,7 +89,6 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
                "       beqzl   %2, 1b                                  \n"
                "        nop                                            \n"
                "       andi    %2, %0, 1                               \n"
-                "       sync                                            \n"
                "       .set    reorder"
                : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
                : "m" (lock->lock)
@@ -99,13 +101,14 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
                "       sc      %2, %1                                  \n"
                "       beqz    %2, 1b                                  \n"
                "        andi   %2, %0, 1                               \n"
-                "       sync                                            \n"
                "       .set    reorder"
                : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
                : "m" (lock->lock)
                : "memory");
        }
+        smp_mb();
        return res == 0;
 }
@@ -143,7 +146,6 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
                "       sc      %1, %0                                  \n"
                "       beqzl   %1, 1b                                  \n"
                "        nop                                            \n"
-                "       sync                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (rw->lock), "=&r" (tmp)
                : "m" (rw->lock)
@@ -156,12 +158,14 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
                "        addu   %1, 1                                   \n"
                "       sc      %1, %0                                  \n"
                "       beqz    %1, 1b                                  \n"
-                "        sync                                           \n"
+                "        nop                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (rw->lock), "=&r" (tmp)
                : "m" (rw->lock)
                : "memory");
        }
+        smp_mb();
 }
 /* Note the use of sub, not subu which will make the kernel die with an
@@ -171,13 +175,14 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
 {
        unsigned int tmp;
+        smp_mb();
        if (R10000_LLSC_WAR) {
                __asm__ __volatile__(
                "1:     ll      %1, %2          # __raw_read_unlock     \n"
                "       sub     %1, 1                                   \n"
                "       sc      %1, %0                                  \n"
                "       beqzl   %1, 1b                                  \n"
-                "       sync                                            \n"
                : "=m" (rw->lock), "=&r" (tmp)
                : "m" (rw->lock)
                : "memory");
@@ -188,7 +193,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
                "       sub     %1, 1                                   \n"
                "       sc      %1, %0                                  \n"
                "       beqz    %1, 1b                                  \n"
-                "        sync                                           \n"
+                "        nop                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (rw->lock), "=&r" (tmp)
                : "m" (rw->lock)
@@ -208,7 +213,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
                "        lui    %1, 0x8000                              \n"
                "       sc      %1, %0                                  \n"
                "       beqzl   %1, 1b                                  \n"
-                "        sync                                           \n"
+                "        nop                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (rw->lock), "=&r" (tmp)
                : "m" (rw->lock)
@@ -221,18 +226,22 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
                "        lui    %1, 0x8000                              \n"
                "       sc      %1, %0                                  \n"
                "       beqz    %1, 1b                                  \n"
-                "        sync                                           \n"
+                "        nop                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (rw->lock), "=&r" (tmp)
                : "m" (rw->lock)
                : "memory");
        }
+        smp_mb();
 }
 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 {
+        smp_mb();
        __asm__ __volatile__(
-        "       sync                    # __raw_write_unlock    \n"
+        "                               # __raw_write_unlock    \n"
        "       sw      $0, %0                                  \n"
        : "=m" (rw->lock)
        : "m" (rw->lock)
@@ -252,11 +261,10 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
                "       bnez    %1, 2f                                  \n"
                "        addu   %1, 1                                   \n"
                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
                "       .set    reorder                                 \n"
-#ifdef CONFIG_SMP
+                "       beqzl   %1, 1b                                  \n"
-                "        sync                                           \n"
+                "        nop                                            \n"
-#endif
+                __WEAK_ORDERING_MB
                "       li      %2, 1                                   \n"
                "2:                                                     \n"
                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
@@ -271,10 +279,9 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
                "        addu   %1, 1                                   \n"
                "       sc      %1, %0                                  \n"
                "       beqz    %1, 1b                                  \n"
+                "        nop                                            \n"
                "       .set    reorder                                 \n"
-#ifdef CONFIG_SMP
+                __WEAK_ORDERING_MB
-                "        sync                                           \n"
-#endif
                "       li      %2, 1                                   \n"
                "2:                                                     \n"
                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
@@ -299,7 +306,8 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
                "        lui    %1, 0x8000                              \n"
                "       sc      %1, %0                                  \n"
                "       beqzl   %1, 1b                                  \n"
-                "        sync                                           \n"
+                "        nop                                            \n"
+                __WEAK_ORDERING_MB
                "       li      %2, 1                                   \n"
                "       .set    reorder                                 \n"
                "2:                                                     \n"
@@ -315,7 +323,8 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
                "       lui     %1, 0x8000                              \n"
                "       sc      %1, %0                                  \n"
                "       beqz    %1, 1b                                  \n"
-                "        sync                                           \n"
+                "        nop                                            \n"
+                __WEAK_ORDERING_MB
                "       li      %2, 1                                   \n"
                "       .set    reorder                                 \n"
                "2:                                                     \n"
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 3056feed5a36..9428057a50cf 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -3,7 +3,7 @@
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
 * Copyright (C) 1996 by Paul M. Antoine
 * Copyright (C) 1999 Silicon Graphics
 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
@@ -16,132 +16,12 @@
 #include <linux/irqflags.h>
 #include <asm/addrspace.h>
+#include <asm/barrier.h>
 #include <asm/cpu-features.h>
 #include <asm/dsp.h>
 #include <asm/ptrace.h>
 #include <asm/war.h>
-/*
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier.  All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads.  This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies.  See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      b = 2;
- *      memory_barrier();
- *      p = &b;                         q = p;
- *                                      read_barrier_depends();
- *                                      d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends().  However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      a = 2;
- *      memory_barrier();
- *      b = 3;                          y = b;
- *                                      read_barrier_depends();
- *                                      x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b".  Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
- * in cases like this where there are no data dependencies.
- */
-#define read_barrier_depends()  do { } while(0)
-#ifdef CONFIG_CPU_HAS_SYNC
-#define __sync()                                \
-        __asm__ __volatile__(                   \
-                ".set   push\n\t"               \
-                ".set   noreorder\n\t"          \
-                ".set   mips2\n\t"              \
-                "sync\n\t"                      \
-                ".set   pop"                    \
-                : /* no output */               \
-                : /* no input */                \
-                : "memory")
-#else
-#define __sync()        do { } while(0)
-#endif
-#define __fast_iob()                            \
-        __asm__ __volatile__(                   \
-                ".set   push\n\t"               \
-                ".set   noreorder\n\t"          \
-                "lw     $0,%0\n\t"              \
-                "nop\n\t"                       \
-                ".set   pop"                    \
-                : /* no output */               \
-                : "m" (*(int *)CKSEG1)          \
-                : "memory")
-#define fast_wmb()      __sync()
-#define fast_rmb()      __sync()
-#define fast_mb()       __sync()
-#define fast_iob()                              \
-        do {                                    \
-                __sync();                       \
-                __fast_iob();                   \
-        } while (0)
-#ifdef CONFIG_CPU_HAS_WB
-#include <asm/wbflush.h>
-#define wmb()           fast_wmb()
-#define rmb()           fast_rmb()
-#define mb()            wbflush()
-#define iob()           wbflush()
-#else /* !CONFIG_CPU_HAS_WB */
-#define wmb()           fast_wmb()
-#define rmb()           fast_rmb()
-#define mb()            fast_mb()
-#define iob()           fast_iob()
-#endif /* !CONFIG_CPU_HAS_WB */
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while(0)
-#endif
-#define set_mb(var, value) \
-do { var = value; mb(); } while (0)
 /*
 * switch_to(n) should switch tasks to task nr n, first
@@ -217,9 +97,6 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                "       .set    mips3                                   \n"
                "       sc      %2, %1                                  \n"
                "       beqzl   %2, 1b                                  \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                : "R" (*m), "Jr" (val)
@@ -235,9 +112,6 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                "       .set    mips3                                   \n"
                "       sc      %2, %1                                  \n"
                "       beqz    %2, 1b                                  \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                : "R" (*m), "Jr" (val)
@@ -251,6 +125,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                local_irq_restore(flags);       /* implies memory barrier  */
        }
+        smp_mb();
        return retval;
 }
@@ -268,9 +144,6 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                "       move    %2, %z4                                 \n"
                "       scd     %2, %1                                  \n"
                "       beqzl   %2, 1b                                  \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                : "R" (*m), "Jr" (val)
@@ -284,9 +157,6 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                "       move    %2, %z4                                 \n"
                "       scd     %2, %1                                  \n"
                "       beqz    %2, 1b                                  \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                : "R" (*m), "Jr" (val)
@@ -300,6 +170,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                local_irq_restore(flags);       /* implies memory barrier  */
        }
+        smp_mb();
        return retval;
 }
 #else
@@ -345,9 +217,6 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
                "       .set    mips3                                   \n"
                "       sc      $1, %1                                  \n"
                "       beqzl   $1, 1b                                  \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "2:                                                     \n"
                "       .set    pop                                     \n"
                : "=&r" (retval), "=R" (*m)
@@ -365,9 +234,6 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
                "       .set    mips3                                   \n"
                "       sc      $1, %1                                  \n"
                "       beqz    $1, 1b                                  \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "2:                                                     \n"
                "       .set    pop                                     \n"
                : "=&r" (retval), "=R" (*m)
@@ -383,6 +249,8 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
                local_irq_restore(flags);       /* implies memory barrier  */
        }
+        smp_mb();
        return retval;
 }
@@ -402,9 +270,6 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
                "       move    $1, %z4                                 \n"
                "       scd     $1, %1                                  \n"
                "       beqzl   $1, 1b                                  \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "2:                                                     \n"
                "       .set    pop                                     \n"
                : "=&r" (retval), "=R" (*m)
@@ -420,9 +285,6 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
                "       move    $1, %z4                                 \n"
                "       scd     $1, %1                                  \n"
                "       beqz    $1, 1b                                  \n"
-#ifdef CONFIG_SMP
-                "       sync                                            \n"
-#endif
                "2:                                                     \n"
                "       .set    pop                                     \n"
                : "=&r" (retval), "=R" (*m)
@@ -438,6 +300,8 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
                local_irq_restore(flags);       /* implies memory barrier  */
        }
+        smp_mb();
        return retval;
 }
 #else
diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h
index 2b52e180c6f2..63a13c5bd832 100644
--- a/include/asm-mips/types.h
+++ b/include/asm-mips/types.h
@@ -93,16 +93,6 @@ typedef unsigned long long phys_t;
 typedef unsigned long phys_t;
 #endif
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
-#ifdef CONFIG_LSF
-typedef u64 blkcnt_t;
-#define HAVE_BLKCNT_T
-#endif
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild
index 9827849953a3..1e637381c118 100644
--- a/include/asm-powerpc/Kbuild
+++ b/include/asm-powerpc/Kbuild
@@ -17,6 +17,7 @@ header-y += ipc.h
 header-y += poll.h
 header-y += shmparam.h
 header-y += sockios.h
+header-y += spu_info.h
 header-y += ucontext.h
 header-y += ioctl.h
 header-y += linkage.h
diff --git a/include/asm-powerpc/cell-pmu.h b/include/asm-powerpc/cell-pmu.h
new file mode 100644
index 000000000000..e8c2ebd3ddda
--- /dev/null
+++ b/include/asm-powerpc/cell-pmu.h
@@ -0,0 +1,113 @@
+/*
+ * Cell Broadband Engine Performance Monitor
+ *
+ * (C) Copyright IBM Corporation 2006
+ *
+ * Author:
+ *   David Erb (djerb@us.ibm.com)
+ *   Kevin Corry (kevcorry@us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_CELL_PMU_H__
+#define __ASM_CELL_PMU_H__
+/* The Cell PMU has four hardware performance counters, which can be
+ * configured as four 32-bit counters or eight 16-bit counters.
+ */
+#define NR_PHYS_CTRS 4
+#define NR_CTRS      (NR_PHYS_CTRS * 2)
+/* Macros for the pm_control register. */
+#define CBE_PM_16BIT_CTR(ctr)              (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
+#define CBE_PM_ENABLE_PERF_MON             0x80000000
+#define CBE_PM_STOP_AT_MAX                 0x40000000
+#define CBE_PM_TRACE_MODE_GET(pm_control)  (((pm_control) >> 28) & 0x3)
+#define CBE_PM_TRACE_MODE_SET(mode)        (((mode)  & 0x3) << 28)
+#define CBE_PM_COUNT_MODE_SET(count)       (((count) & 0x3) << 18)
+#define CBE_PM_FREEZE_ALL_CTRS             0x00100000
+#define CBE_PM_ENABLE_EXT_TRACE            0x00008000
+/* Macros for the trace_address register. */
+#define CBE_PM_TRACE_BUF_FULL              0x00000800
+#define CBE_PM_TRACE_BUF_EMPTY             0x00000400
+#define CBE_PM_TRACE_BUF_DATA_COUNT(ta)    ((ta) & 0x3ff)
+#define CBE_PM_TRACE_BUF_MAX_COUNT         0x400
+/* Macros for the pm07_control registers. */
+#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
+#define CBE_PM_CTR_INPUT_CONTROL           0x02000000
+#define CBE_PM_CTR_POLARITY                0x01000000
+#define CBE_PM_CTR_COUNT_CYCLES            0x00800000
+#define CBE_PM_CTR_ENABLE                  0x00400000
+/* Macros for the pm_status register. */
+#define CBE_PM_CTR_OVERFLOW_INTR(ctr)      (1 << (31 - ((ctr) & 7)))
+enum pm_reg_name {
+        group_control,
+        debug_bus_control,
+        trace_address,
+        ext_tr_timer,
+        pm_status,
+        pm_control,
+        pm_interval,
+        pm_start_stop,
+};
+/* Routines for reading/writing the PMU registers. */
+extern u32  cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
+extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
+extern u32  cbe_read_ctr(u32 cpu, u32 ctr);
+extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
+extern u32  cbe_read_pm07_control(u32 cpu, u32 ctr);
+extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
+extern u32  cbe_read_pm(u32 cpu, enum pm_reg_name reg);
+extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
+extern u32  cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
+extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
+extern void cbe_enable_pm(u32 cpu);
+extern void cbe_disable_pm(u32 cpu);
+extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
+extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
+extern void cbe_disable_pm_interrupts(u32 cpu);
+extern u32  cbe_query_pm_interrupts(u32 cpu);
+extern u32  cbe_clear_pm_interrupts(u32 cpu);
+extern void cbe_sync_irq(int node);
+/* Utility functions, macros */
+extern u32 cbe_get_hw_thread_id(int cpu);
+#define cbe_cpu_to_node(cpu) ((cpu) >> 1)
+#define CBE_COUNT_SUPERVISOR_MODE       0
+#define CBE_COUNT_HYPERVISOR_MODE       1
+#define CBE_COUNT_PROBLEM_MODE          2
+#define CBE_COUNT_ALL_MODES             3
+/* Macros for the pm07_control registers. */
+#define PM07_CTR_INPUT_MUX(x)                    (((x) & 0x3F) << 26)
+#define PM07_CTR_INPUT_CONTROL(x)                (((x) & 1) << 25)
+#define PM07_CTR_POLARITY(x)                     (((x) & 1) << 24)
+#define PM07_CTR_COUNT_CYCLES(x)                 (((x) & 1) << 23)
+#define PM07_CTR_ENABLE(x)                       (((x) & 1) << 22)
+#endif /* __ASM_CELL_PMU_H__ */
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index a9a40149a7c0..6fe5c9d4ca3b 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -24,6 +24,8 @@
 #define PPC_FEATURE_ICACHE_SNOOP        0x00002000
 #define PPC_FEATURE_ARCH_2_05           0x00001000
 #define PPC_FEATURE_PA6T                0x00000800
+#define PPC_FEATURE_HAS_DFP             0x00000400
+#define PPC_FEATURE_POWER6_EXT          0x00000200
 #define PPC_FEATURE_TRUE_LE             0x00000002
 #define PPC_FEATURE_PPC_LE              0x00000001
@@ -45,6 +47,7 @@ enum powerpc_oprofile_type {
        PPC_OPROFILE_POWER4 = 2,
        PPC_OPROFILE_G4 = 3,
        PPC_OPROFILE_BOOKE = 4,
+        PPC_OPROFILE_CELL = 5,
 };
 struct cpu_spec {
@@ -91,7 +94,7 @@ extern struct cpu_spec		*cur_cpu_spec;
 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
-extern struct cpu_spec *identify_cpu(unsigned long offset);
+extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
 extern void do_feature_fixups(unsigned long value, void *fixup_start,
                              void *fixup_end);
@@ -148,19 +151,13 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
+#define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
 #ifndef __ASSEMBLY__
-#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
+#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_SLB | \
-                                        CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
+                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
-                                        CPU_FTR_NODSISRALIGN)
+                                 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
-/* iSeries doesn't support large pages */
-#ifdef CONFIG_PPC_ISERIES
-#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
-#else
-#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
-#endif /* CONFIG_PPC_ISERIES */
 /* We only set the altivec features if the kernel was compiled with altivec
 * support
@@ -311,7 +308,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
            CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
-#ifdef __powerpc64__
+/* 64-bit CPUs */
 #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
 #define CPU_FTRS_RS64   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
@@ -332,7 +330,13 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
            CPU_FTR_MMCRA | CPU_FTR_SMT | \
            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-            CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
+            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE)
+#define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_MMCRA | CPU_FTR_SMT | \
+            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+            CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
+            CPU_FTR_SPURR | CPU_FTR_REAL_LE)
 #define CPU_FTRS_CELL   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -343,7 +347,6 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
            CPU_FTR_PURR | CPU_FTR_REAL_LE)
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
-#endif
 #ifdef __powerpc64__
 #define CPU_FTRS_POSSIBLE       \
diff --git a/include/asm-powerpc/dbdma.h b/include/asm-powerpc/dbdma.h
index 8973565f95d3..e23f07e73cb3 100644
--- a/include/asm-powerpc/dbdma.h
+++ b/include/asm-powerpc/dbdma.h
@@ -95,7 +95,13 @@ struct dbdma_cmd {
 #define DBDMA_DO_STOP(regs) do {                                \
        out_le32(&((regs)->control), (RUN|FLUSH)<<16);          \
        while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH))      \
-                ;                                               \
+                ; \
+} while(0)
+#define DBDMA_DO_RESET(regs) do {                               \
+        out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
+        while(in_le32(&((regs)->status)) & (RUN)) \
+                ; \
 } while(0)
 #endif /* _ASM_DBDMA_H_ */
diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h
new file mode 100644
index 000000000000..5dbfca8dde36
--- /dev/null
+++ b/include/asm-powerpc/dcr-mmio.h
@@ -0,0 +1,51 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                    <benh@kernel.crashing.org>
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_DCR_MMIO_H
+#define _ASM_POWERPC_DCR_MMIO_H
+#ifdef __KERNEL__
+#include <asm/io.h>
+typedef struct { void __iomem *token; unsigned int stride; } dcr_host_t;
+#define DCR_MAP_OK(host)        ((host).token != NULL)
+extern dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
+                          unsigned int dcr_c);
+extern void dcr_unmap(dcr_host_t host, unsigned int dcr_n, unsigned int dcr_c);
+static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n)
+{
+        return in_be32(host.token + dcr_n * host.stride);
+}
+static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value)
+{
+        out_be32(host.token + dcr_n * host.stride, value);
+}
+extern u64 of_translate_dcr_address(struct device_node *dev,
+                                    unsigned int dcr_n,
+                                    unsigned int *stride);
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_MMIO_H */
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
new file mode 100644
index 000000000000..fd4a5f5e33d1
--- /dev/null
+++ b/include/asm-powerpc/dcr-native.h
@@ -0,0 +1,39 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                    <benh@kernel.crashing.org>
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_DCR_NATIVE_H
+#define _ASM_POWERPC_DCR_NATIVE_H
+#ifdef __KERNEL__
+#include <asm/reg.h>
+typedef struct {} dcr_host_t;
+#define DCR_MAP_OK(host)        (1)
+#define dcr_map(dev, dcr_n, dcr_c)      {}
+#define dcr_unmap(host, dcr_n, dcr_c)   {}
+#define dcr_read(host, dcr_n)           mfdcr(dcr_n)
+#define dcr_write(host, dcr_n, value)   mtdcr(dcr_n, value)
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_NATIVE_H */
diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
new file mode 100644
index 000000000000..473f2c7fd892
--- /dev/null
+++ b/include/asm-powerpc/dcr.h
@@ -0,0 +1,42 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                    <benh@kernel.crashing.org>
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_DCR_H
+#define _ASM_POWERPC_DCR_H
+#ifdef __KERNEL__
+#ifdef CONFIG_PPC_DCR_NATIVE
+#include <asm/dcr-native.h>
+#else
+#include <asm/dcr-mmio.h>
+#endif
+/*
+ * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
+ * base from the device-tree
+ */
+#ifdef CONFIG_PPC_MERGE
+extern unsigned int dcr_resource_start(struct device_node *np,
+                                       unsigned int index);
+extern unsigned int dcr_resource_len(struct device_node *np,
+                                     unsigned int index);
+#endif /* CONFIG_PPC_MERGE */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_H */
diff --git a/include/asm-powerpc/device.h b/include/asm-powerpc/device.h
index d8f9872b0e2d..228ab2a315b9 100644
--- a/include/asm-powerpc/device.h
+++ b/include/asm-powerpc/device.h
@@ -3,5 +3,22 @@
 *
 * This file is released under the GPLv2
 */
-#include <asm-generic/device.h>
+#ifndef _ASM_POWERPC_DEVICE_H
+#define _ASM_POWERPC_DEVICE_H
+struct dma_mapping_ops;
+struct device_node;
+struct dev_archdata {
+        /* Optional pointer to an OF device node */
+        struct device_node      *of_node;
+        /* DMA operations on that device */
+        struct dma_mapping_ops  *dma_ops;
+        void                    *dma_data;
+        /* NUMA node if applicable */
+        int                     numa_node;
+};
+#endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index 2ab9baf78bb4..7e38b5fddada 100644
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -44,26 +44,150 @@ extern void __dma_sync_page(struct page *page, unsigned long offset,
 #endif /* ! CONFIG_NOT_COHERENT_CACHE */
 #ifdef CONFIG_PPC64
+/*
+ * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
+ */
+struct dma_mapping_ops {
+        void *          (*alloc_coherent)(struct device *dev, size_t size,
+                                dma_addr_t *dma_handle, gfp_t flag);
+        void            (*free_coherent)(struct device *dev, size_t size,
+                                void *vaddr, dma_addr_t dma_handle);
+        dma_addr_t      (*map_single)(struct device *dev, void *ptr,
+                                size_t size, enum dma_data_direction direction);
+        void            (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
+                                size_t size, enum dma_data_direction direction);
+        int             (*map_sg)(struct device *dev, struct scatterlist *sg,
+                                int nents, enum dma_data_direction direction);
+        void            (*unmap_sg)(struct device *dev, struct scatterlist *sg,
+                                int nents, enum dma_data_direction direction);
+        int             (*dma_supported)(struct device *dev, u64 mask);
+        int             (*dac_dma_supported)(struct device *dev, u64 mask);
+        int             (*set_dma_mask)(struct device *dev, u64 dma_mask);
+};
+static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
+{
+        /* We don't handle the NULL dev case for ISA for now. We could
+         * do it via an out of line call but it is not needed for now. The
+         * only ISA DMA device we support is the floppy and we have a hack
+         * in the floppy driver directly to get a device for us.
+         */
+        if (unlikely(dev == NULL || dev->archdata.dma_ops == NULL))
+                return NULL;
+        return dev->archdata.dma_ops;
+}
-extern int dma_supported(struct device *dev, u64 mask);
+static inline int dma_supported(struct device *dev, u64 mask)
-extern int dma_set_mask(struct device *dev, u64 dma_mask);
+{
-extern void *dma_alloc_coherent(struct device *dev, size_t size,
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-                dma_addr_t *dma_handle, gfp_t flag);
-extern void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
+        if (unlikely(dma_ops == NULL))
-                dma_addr_t dma_handle);
+                return 0;
-extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+        if (dma_ops->dma_supported == NULL)
-                size_t size, enum dma_data_direction direction);
+                return 1;
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+        return dma_ops->dma_supported(dev, mask);
-                size_t size, enum dma_data_direction direction);
+}
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                unsigned long offset, size_t size,
+static inline int dma_set_mask(struct device *dev, u64 dma_mask)
-                enum dma_data_direction direction);
+{
-extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-                size_t size, enum dma_data_direction direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+        if (unlikely(dma_ops == NULL))
-                enum dma_data_direction direction);
+                return -EIO;
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+        if (dma_ops->set_dma_mask != NULL)
-                int nhwentries, enum dma_data_direction direction);
+                return dma_ops->set_dma_mask(dev, dma_mask);
+        if (!dev->dma_mask || !dma_supported(dev, *dev->dma_mask))
+                return -EIO;
+        *dev->dma_mask = dma_mask;
+        return 0;
+}
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t *dma_handle, gfp_t flag)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        BUG_ON(!dma_ops);
+        return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
+}
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *cpu_addr, dma_addr_t dma_handle)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        BUG_ON(!dma_ops);
+        dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
+}
+static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+                                        size_t size,
+                                        enum dma_data_direction direction)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        BUG_ON(!dma_ops);
+        return dma_ops->map_single(dev, cpu_addr, size, direction);
+}
+static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+                                    size_t size,
+                                    enum dma_data_direction direction)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_single(dev, dma_addr, size, direction);
+}
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                                      unsigned long offset, size_t size,
+                                      enum dma_data_direction direction)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        BUG_ON(!dma_ops);
+        return dma_ops->map_single(dev, page_address(page) + offset, size,
+                        direction);
+}
+static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                  size_t size,
+                                  enum dma_data_direction direction)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_single(dev, dma_address, size, direction);
+}
+static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
+                             int nents, enum dma_data_direction direction)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        BUG_ON(!dma_ops);
+        return dma_ops->map_sg(dev, sg, nents, direction);
+}
+static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+                                int nhwentries,
+                                enum dma_data_direction direction)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_sg(dev, sg, nhwentries, direction);
+}
+/*
+ * Available generic sets of operations
+ */
+extern struct dma_mapping_ops dma_iommu_ops;
+extern struct dma_mapping_ops dma_direct_ops;
+extern unsigned long dma_direct_offset;
 #else /* CONFIG_PPC64 */
@@ -261,25 +385,5 @@ static inline void dma_cache_sync(void *vaddr, size_t size,
        __dma_sync(vaddr, size, (int)direction);
 }
-/*
- * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
- */
-struct dma_mapping_ops {
-        void *          (*alloc_coherent)(struct device *dev, size_t size,
-                                dma_addr_t *dma_handle, gfp_t flag);
-        void            (*free_coherent)(struct device *dev, size_t size,
-                                void *vaddr, dma_addr_t dma_handle);
-        dma_addr_t      (*map_single)(struct device *dev, void *ptr,
-                                size_t size, enum dma_data_direction direction);
-        void            (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
-                                size_t size, enum dma_data_direction direction);
-        int             (*map_sg)(struct device *dev, struct scatterlist *sg,
-                                int nents, enum dma_data_direction direction);
-        void            (*unmap_sg)(struct device *dev, struct scatterlist *sg,
-                                int nents, enum dma_data_direction direction);
-        int             (*dma_supported)(struct device *dev, u64 mask);
-        int             (*dac_dma_supported)(struct device *dev, u64 mask);
-};
 #endif /* __KERNEL__ */
 #endif  /* _ASM_DMA_MAPPING_H */
diff --git a/include/asm-powerpc/eeh.h b/include/asm-powerpc/eeh.h
index 6a784396660b..b886bec67016 100644
--- a/include/asm-powerpc/eeh.h
+++ b/include/asm-powerpc/eeh.h
@@ -120,10 +120,6 @@ static inline u8 eeh_readb(const volatile void __iomem *addr)
                return eeh_check_failure(addr, val);
        return val;
 }
-static inline void eeh_writeb(u8 val, volatile void __iomem *addr)
-{
-        out_8(addr, val);
-}
 static inline u16 eeh_readw(const volatile void __iomem *addr)
 {
@@ -132,21 +128,6 @@ static inline u16 eeh_readw(const volatile void __iomem *addr)
                return eeh_check_failure(addr, val);
        return val;
 }
-static inline void eeh_writew(u16 val, volatile void __iomem *addr)
-{
-        out_le16(addr, val);
-}
-static inline u16 eeh_raw_readw(const volatile void __iomem *addr)
-{
-        u16 val = in_be16(addr);
-        if (EEH_POSSIBLE_ERROR(val, u16))
-                return eeh_check_failure(addr, val);
-        return val;
-}
-static inline void eeh_raw_writew(u16 val, volatile void __iomem *addr) {
-        volatile u16 __iomem *vaddr = (volatile u16 __iomem *) addr;
-        out_be16(vaddr, val);
-}
 static inline u32 eeh_readl(const volatile void __iomem *addr)
 {
@@ -155,205 +136,75 @@ static inline u32 eeh_readl(const volatile void __iomem *addr)
                return eeh_check_failure(addr, val);
        return val;
 }
-static inline void eeh_writel(u32 val, volatile void __iomem *addr)
-{
+static inline u64 eeh_readq(const volatile void __iomem *addr)
-        out_le32(addr, val);
-}
-static inline u32 eeh_raw_readl(const volatile void __iomem *addr)
 {
-        u32 val = in_be32(addr);
+        u64 val = in_le64(addr);
-        if (EEH_POSSIBLE_ERROR(val, u32))
+        if (EEH_POSSIBLE_ERROR(val, u64))
                return eeh_check_failure(addr, val);
        return val;
 }
-static inline void eeh_raw_writel(u32 val, volatile void __iomem *addr)
-{
-        out_be32(addr, val);
-}
-static inline u64 eeh_readq(const volatile void __iomem *addr)
+static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 {
-        u64 val = in_le64(addr);
+        u16 val = in_be16(addr);
-        if (EEH_POSSIBLE_ERROR(val, u64))
+        if (EEH_POSSIBLE_ERROR(val, u16))
                return eeh_check_failure(addr, val);
        return val;
 }
-static inline void eeh_writeq(u64 val, volatile void __iomem *addr)
+static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 {
-        out_le64(addr, val);
+        u32 val = in_be32(addr);
+        if (EEH_POSSIBLE_ERROR(val, u32))
+                return eeh_check_failure(addr, val);
+        return val;
 }
-static inline u64 eeh_raw_readq(const volatile void __iomem *addr)
+static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 {
        u64 val = in_be64(addr);
        if (EEH_POSSIBLE_ERROR(val, u64))
                return eeh_check_failure(addr, val);
        return val;
 }
-static inline void eeh_raw_writeq(u64 val, volatile void __iomem *addr)
-{
-        out_be64(addr, val);
-}
-#define EEH_CHECK_ALIGN(v,a) \
-        ((((unsigned long)(v)) & ((a) - 1)) == 0)
-static inline void eeh_memset_io(volatile void __iomem *addr, int c,
+static inline void eeh_memcpy_fromio(void *dest, const
-                                 unsigned long n)
+                                     volatile void __iomem *src,
-{
-        void *p = (void __force *)addr;
-        u32 lc = c;
-        lc |= lc << 8;
-        lc |= lc << 16;
-        __asm__ __volatile__ ("sync" : : : "memory");
-        while(n && !EEH_CHECK_ALIGN(p, 4)) {
-                *((volatile u8 *)p) = c;
-                p++;
-                n--;
-        }
-        while(n >= 4) {
-                *((volatile u32 *)p) = lc;
-                p += 4;
-                n -= 4;
-        }
-        while(n) {
-                *((volatile u8 *)p) = c;
-                p++;
-                n--;
-        }
-        __asm__ __volatile__ ("sync" : : : "memory");
-}
-static inline void eeh_memcpy_fromio(void *dest, const volatile void __iomem *src,
                                     unsigned long n)
 {
-        void *vsrc = (void __force *) src;
+        _memcpy_fromio(dest, src, n);
-        void *destsave = dest;
-        unsigned long nsave = n;
-        __asm__ __volatile__ ("sync" : : : "memory");
-        while(n && (!EEH_CHECK_ALIGN(vsrc, 4) || !EEH_CHECK_ALIGN(dest, 4))) {
-                *((u8 *)dest) = *((volatile u8 *)vsrc);
-                __asm__ __volatile__ ("eieio" : : : "memory");
-                vsrc++;
-                dest++;
-                n--;
-        }
-        while(n > 4) {
-                *((u32 *)dest) = *((volatile u32 *)vsrc);
-                __asm__ __volatile__ ("eieio" : : : "memory");
-                vsrc += 4;
-                dest += 4;
-                n -= 4;
-        }
-        while(n) {
-                *((u8 *)dest) = *((volatile u8 *)vsrc);
-                __asm__ __volatile__ ("eieio" : : : "memory");
-                vsrc++;
-                dest++;
-                n--;
-        }
-        __asm__ __volatile__ ("sync" : : : "memory");
        /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
         * were copied. Check all four bytes.
         */
-        if ((nsave >= 4) &&
+        if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
-                (EEH_POSSIBLE_ERROR((*((u32 *) destsave+nsave-4)), u32))) {
+                eeh_check_failure(src, *((u32 *)(dest + n - 4)));
-                eeh_check_failure(src, (*((u32 *) destsave+nsave-4)));
-        }
-}
-static inline void eeh_memcpy_toio(volatile void __iomem *dest, const void *src,
-                                   unsigned long n)
-{
-        void *vdest = (void __force *) dest;
-        __asm__ __volatile__ ("sync" : : : "memory");
-        while(n && (!EEH_CHECK_ALIGN(vdest, 4) || !EEH_CHECK_ALIGN(src, 4))) {
-                *((volatile u8 *)vdest) = *((u8 *)src);
-                src++;
-                vdest++;
-                n--;
-        }
-        while(n > 4) {
-                *((volatile u32 *)vdest) = *((volatile u32 *)src);
-                src += 4;
-                vdest += 4;
-                n-=4;
-        }
-        while(n) {
-                *((volatile u8 *)vdest) = *((u8 *)src);
-                src++;
-                vdest++;
-                n--;
-        }
-        __asm__ __volatile__ ("sync" : : : "memory");
-}
-#undef EEH_CHECK_ALIGN
-static inline u8 eeh_inb(unsigned long port)
-{
-        u8 val;
-        val = in_8((u8 __iomem *)(port+pci_io_base));
-        if (EEH_POSSIBLE_ERROR(val, u8))
-                return eeh_check_failure((void __iomem *)(port), val);
-        return val;
-}
-static inline void eeh_outb(u8 val, unsigned long port)
-{
-        out_8((u8 __iomem *)(port+pci_io_base), val);
-}
-static inline u16 eeh_inw(unsigned long port)
-{
-        u16 val;
-        val = in_le16((u16 __iomem *)(port+pci_io_base));
-        if (EEH_POSSIBLE_ERROR(val, u16))
-                return eeh_check_failure((void __iomem *)(port), val);
-        return val;
-}
-static inline void eeh_outw(u16 val, unsigned long port)
-{
-        out_le16((u16 __iomem *)(port+pci_io_base), val);
-}
-static inline u32 eeh_inl(unsigned long port)
-{
-        u32 val;
-        val = in_le32((u32 __iomem *)(port+pci_io_base));
-        if (EEH_POSSIBLE_ERROR(val, u32))
-                return eeh_check_failure((void __iomem *)(port), val);
-        return val;
-}
-static inline void eeh_outl(u32 val, unsigned long port)
-{
-        out_le32((u32 __iomem *)(port+pci_io_base), val);
 }
 /* in-string eeh macros */
-static inline void eeh_insb(unsigned long port, void * buf, int ns)
+static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
+                              int ns)
 {
-        _insb((u8 __iomem *)(port+pci_io_base), buf, ns);
+        _insb(addr, buf, ns);
        if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
-                eeh_check_failure((void __iomem *)(port), *(u8*)buf);
+                eeh_check_failure(addr, *(u8*)buf);
 }
-static inline void eeh_insw_ns(unsigned long port, void * buf, int ns)
+static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
+                              int ns)
 {
-        _insw_ns((u16 __iomem *)(port+pci_io_base), buf, ns);
+        _insw(addr, buf, ns);
        if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
-                eeh_check_failure((void __iomem *)(port), *(u16*)buf);
+                eeh_check_failure(addr, *(u16*)buf);
 }
-static inline void eeh_insl_ns(unsigned long port, void * buf, int nl)
+static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
+                              int nl)
 {
-        _insl_ns((u32 __iomem *)(port+pci_io_base), buf, nl);
+        _insl(addr, buf, nl);
        if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
-                eeh_check_failure((void __iomem *)(port), *(u32*)buf);
+                eeh_check_failure(addr, *(u32*)buf);
 }
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h
index 9a83a987d396..b5436642a109 100644
--- a/include/asm-powerpc/elf.h
+++ b/include/asm-powerpc/elf.h
@@ -411,4 +411,17 @@ do {									\
 /* Keep this the last entry.  */
 #define R_PPC64_NUM             107
+#ifdef CONFIG_SPU_BASE
+/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
+#define NT_SPU          1
+extern int arch_notes_size(void);
+extern void arch_write_notes(struct file *file);
+#define ELF_CORE_EXTRA_NOTES_SIZE arch_notes_size()
+#define ELF_CORE_WRITE_EXTRA_NOTES arch_write_notes(file)
+#define ARCH_HAVE_EXTRA_ELF_NOTES
+#endif /* CONFIG_PPC_CELL */
 #endif /* _ASM_POWERPC_ELF_H */
diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h
index fdf9aff71150..98f7b62422c9 100644
--- a/include/asm-powerpc/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -42,6 +42,7 @@
 #define FW_FEATURE_SPLPAR       ASM_CONST(0x0000000000100000)
 #define FW_FEATURE_ISERIES      ASM_CONST(0x0000000000200000)
 #define FW_FEATURE_LPAR         ASM_CONST(0x0000000000400000)
+#define FW_FEATURE_PS3_LV1      ASM_CONST(0x0000000000800000)
 #ifndef __ASSEMBLY__
@@ -58,6 +59,10 @@ enum {
        FW_FEATURE_PSERIES_ALWAYS = 0,
        FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
        FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
+        FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
+        FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
+        FW_FEATURE_NATIVE_POSSIBLE = 0,
+        FW_FEATURE_NATIVE_ALWAYS = 0,
        FW_FEATURE_POSSIBLE =
 #ifdef CONFIG_PPC_PSERIES
                FW_FEATURE_PSERIES_POSSIBLE |
@@ -65,6 +70,12 @@ enum {
 #ifdef CONFIG_PPC_ISERIES
                FW_FEATURE_ISERIES_POSSIBLE |
 #endif
+#ifdef CONFIG_PPC_PS3
+                FW_FEATURE_PS3_POSSIBLE |
+#endif
+#ifdef CONFIG_PPC_NATIVE
+                FW_FEATURE_NATIVE_ALWAYS |
+#endif
                0,
        FW_FEATURE_ALWAYS =
 #ifdef CONFIG_PPC_PSERIES
@@ -73,6 +84,12 @@ enum {
 #ifdef CONFIG_PPC_ISERIES
                FW_FEATURE_ISERIES_ALWAYS &
 #endif
+#ifdef CONFIG_PPC_PS3
+                FW_FEATURE_PS3_ALWAYS &
+#endif
+#ifdef CONFIG_PPC_NATIVE
+                FW_FEATURE_NATIVE_ALWAYS &
+#endif
                FW_FEATURE_POSSIBLE,
 #else /* CONFIG_PPC64 */
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index d40359204aba..d604863d72fb 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -7,16 +7,40 @@
 #ifdef __KERNEL__
 #include <linux/errno.h>
+#include <linux/compiler.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 extern void timer_interrupt(struct pt_regs *);
-#ifdef CONFIG_PPC_ISERIES
+#ifdef CONFIG_PPC64
+#include <asm/paca.h>
+static inline unsigned long local_get_flags(void)
+{
+        unsigned long flags;
+        __asm__ __volatile__("lbz %0,%1(13)"
+        : "=r" (flags)
+        : "i" (offsetof(struct paca_struct, soft_enabled)));
+        return flags;
+}
+static inline unsigned long local_irq_disable(void)
+{
+        unsigned long flags, zero;
+        __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
+        : "=r" (flags), "=&r" (zero)
+        : "i" (offsetof(struct paca_struct, soft_enabled))
+        : "memory");
+        return flags;
+}
-extern unsigned long local_get_flags(void);
-extern unsigned long local_irq_disable(void);
 extern void local_irq_restore(unsigned long);
+extern void iseries_handle_interrupts(void);
 #define local_irq_enable()      local_irq_restore(1)
 #define local_save_flags(flags) ((flags) = local_get_flags())
@@ -24,17 +48,14 @@ extern void local_irq_restore(unsigned long);
 #define irqs_disabled()         (local_get_flags() == 0)
+#define hard_irq_enable()       __mtmsrd(mfmsr() | MSR_EE, 1)
+#define hard_irq_disable()      __mtmsrd(mfmsr() & ~MSR_EE, 1)
 #else
 #if defined(CONFIG_BOOKE)
 #define SET_MSR_EE(x)   mtmsr(x)
 #define local_irq_restore(flags)        __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
-#elif defined(__powerpc64__)
-#define SET_MSR_EE(x)   __mtmsrd(x, 1)
-#define local_irq_restore(flags) do { \
-        __asm__ __volatile__("": : :"memory"); \
-        __mtmsrd((flags), 1); \
-} while(0)
 #else
 #define SET_MSR_EE(x)   mtmsr(x)
 #define local_irq_restore(flags)        mtmsr(flags)
@@ -81,7 +102,10 @@ static inline void local_irq_save_ptr(unsigned long *flags)
 #define local_irq_save(flags)   local_irq_save_ptr(&flags)
 #define irqs_disabled()         ((mfmsr() & MSR_EE) == 0)
-#endif /* CONFIG_PPC_ISERIES */
+#define hard_irq_enable()       local_irq_enable()
+#define hard_irq_disable()      local_irq_disable()
+#endif /* CONFIG_PPC64 */
 #define mask_irq(irq)                                           \
        ({                                                      \
diff --git a/include/asm-powerpc/ibmebus.h b/include/asm-powerpc/ibmebus.h
index 3493429b70f5..66112114b8c5 100644
--- a/include/asm-powerpc/ibmebus.h
+++ b/include/asm-powerpc/ibmebus.h
@@ -44,7 +44,6 @@
 #include <linux/mod_devicetable.h>
 #include <asm/of_device.h>
-extern struct dma_mapping_ops ibmebus_dma_ops;
 extern struct bus_type ibmebus_bus_type;
 struct ibmebus_dev {    
diff --git a/include/asm-powerpc/ide.h b/include/asm-powerpc/ide.h
index c8390f9485de..0f66f0f82c32 100644
--- a/include/asm-powerpc/ide.h
+++ b/include/asm-powerpc/ide.h
@@ -22,10 +22,10 @@
 #endif
 #endif
-#define __ide_mm_insw(p, a, c)  _insw_ns((volatile u16 __iomem *)(p), (a), (c))
+#define __ide_mm_insw(p, a, c)  readsw((void __iomem *)(p), (a), (c))
-#define __ide_mm_insl(p, a, c)  _insl_ns((volatile u32 __iomem *)(p), (a), (c))
+#define __ide_mm_insl(p, a, c)  readsl((void __iomem *)(p), (a), (c))
-#define __ide_mm_outsw(p, a, c) _outsw_ns((volatile u16 __iomem *)(p), (a), (c))
+#define __ide_mm_outsw(p, a, c) writesw((void __iomem *)(p), (a), (c))
-#define __ide_mm_outsl(p, a, c) _outsl_ns((volatile u32 __iomem *)(p), (a), (c))
+#define __ide_mm_outsl(p, a, c) writesl((void __iomem *)(p), (a), (c))
 #ifndef  __powerpc64__
 #include <linux/hdreg.h>
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index ce12f85fff9b..9fdd0491f6a3 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -136,22 +136,7 @@ struct qe_timers {
 /* BRG */
 struct qe_brg {
-        __be32  brgc1;          /* BRG1 configuration register */
+        __be32  brgc[16];       /* BRG configuration registers */
-        __be32  brgc2;          /* BRG2 configuration register */
-        __be32  brgc3;          /* BRG3 configuration register */
-        __be32  brgc4;          /* BRG4 configuration register */
-        __be32  brgc5;          /* BRG5 configuration register */
-        __be32  brgc6;          /* BRG6 configuration register */
-        __be32  brgc7;          /* BRG7 configuration register */
-        __be32  brgc8;          /* BRG8 configuration register */
-        __be32  brgc9;          /* BRG9 configuration register */
-        __be32  brgc10;         /* BRG10 configuration register */
-        __be32  brgc11;         /* BRG11 configuration register */
-        __be32  brgc12;         /* BRG12 configuration register */
-        __be32  brgc13;         /* BRG13 configuration register */
-        __be32  brgc14;         /* BRG14 configuration register */
-        __be32  brgc15;         /* BRG15 configuration register */
-        __be32  brgc16;         /* BRG16 configuration register */
        u8      res0[0x40];
 } __attribute__ ((packed));
diff --git a/include/asm-powerpc/io-defs.h b/include/asm-powerpc/io-defs.h
new file mode 100644
index 000000000000..03691ab69217
--- /dev/null
+++ b/include/asm-powerpc/io-defs.h
@@ -0,0 +1,59 @@
+/* This file is meant to be include multiple times by other headers */
+DEF_PCI_AC_RET(readb, u8, (const PCI_IO_ADDR addr), (addr))
+DEF_PCI_AC_RET(readw, u16, (const PCI_IO_ADDR addr), (addr))
+DEF_PCI_AC_RET(readl, u32, (const PCI_IO_ADDR addr), (addr))
+DEF_PCI_AC_RET(readw_be, u16, (const PCI_IO_ADDR addr), (addr))
+DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr))
+DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr))
+DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr))
+DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr))
+DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr))
+DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr))
+#ifdef __powerpc64__
+DEF_PCI_AC_RET(readq, u64, (const PCI_IO_ADDR addr), (addr))
+DEF_PCI_AC_RET(readq_be, u64, (const PCI_IO_ADDR addr), (addr))
+DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr))
+DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr))
+#endif /* __powerpc64__ */
+DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port))
+DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port))
+DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port))
+DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port))
+DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port))
+DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port))
+DEF_PCI_AC_NORET(readsb, (const PCI_IO_ADDR a, void *b, unsigned long c), \
+                 (a, b, c))
+DEF_PCI_AC_NORET(readsw, (const PCI_IO_ADDR a, void *b, unsigned long c), \
+                 (a, b, c))
+DEF_PCI_AC_NORET(readsl, (const PCI_IO_ADDR a, void *b, unsigned long c), \
+                 (a, b, c))
+DEF_PCI_AC_NORET(writesb, (PCI_IO_ADDR a, const void *b, unsigned long c), \
+                 (a, b, c))
+DEF_PCI_AC_NORET(writesw, (PCI_IO_ADDR a, const void *b, unsigned long c), \
+                 (a, b, c))
+DEF_PCI_AC_NORET(writesl, (PCI_IO_ADDR a, const void *b, unsigned long c), \
+                 (a, b, c))
+DEF_PCI_AC_NORET(insb, (unsigned long p, void *b, unsigned long c), \
+                 (p, b, c))
+DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c), \
+                 (p, b, c))
+DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c), \
+                 (p, b, c))
+DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c), \
+                 (p, b, c))
+DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c), \
+                 (p, b, c))
+DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c), \
+                 (p, b, c))
+DEF_PCI_AC_NORET(memset_io, (PCI_IO_ADDR a, int c, unsigned long n),       \
+                 (a, c, n))
+DEF_PCI_AC_NORET(memcpy_fromio,(void *d,const PCI_IO_ADDR s,unsigned long n), \
+                 (d, s, n))
+DEF_PCI_AC_NORET(memcpy_toio,(PCI_IO_ADDR d,const void *s,unsigned long n),   \
+                 (d, s, n))
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index c2c5f14b5f5f..1cd532379c30 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -13,154 +13,530 @@
 extern int check_legacy_ioport(unsigned long base_port);
 #define PNPBIOS_BASE    0xf000  /* only relevant for PReP */
-#ifndef CONFIG_PPC64
-#include <asm-ppc/io.h>
-#else
 #include <linux/compiler.h>
 #include <asm/page.h>
 #include <asm/byteorder.h>
-#include <asm/paca.h>
 #include <asm/synch.h>
 #include <asm/delay.h>
+#include <asm/mmu.h>
 #include <asm-generic/iomap.h>
+#ifdef CONFIG_PPC64
+#include <asm/paca.h>
+#endif
 #define SIO_CONFIG_RA   0x398
 #define SIO_CONFIG_RD   0x399
 #define SLOW_DOWN_IO
+/* 32 bits uses slightly different variables for the various IO
+ * bases. Most of this file only uses _IO_BASE though which we
+ * define properly based on the platform
+ */
+#ifndef CONFIG_PCI
+#define _IO_BASE        0
+#define _ISA_MEM_BASE   0
+#define PCI_DRAM_OFFSET 0
+#elif defined(CONFIG_PPC32)
+#define _IO_BASE        isa_io_base
+#define _ISA_MEM_BASE   isa_mem_base
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define _IO_BASE        pci_io_base
+#define _ISA_MEM_BASE   0
+#define PCI_DRAM_OFFSET 0
+#endif
 extern unsigned long isa_io_base;
+extern unsigned long isa_mem_base;
 extern unsigned long pci_io_base;
+extern unsigned long pci_dram_offset;
+#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
+#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
+#endif
+/*
+ *
+ * Low level MMIO accessors
+ *
+ * This provides the non-bus specific accessors to MMIO. Those are PowerPC
+ * specific and thus shouldn't be used in generic code. The accessors
+ * provided here are:
+ *
+ *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
+ *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
+ *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
+ *
+ * Those operate directly on a kernel virtual address. Note that the prototype
+ * for the out_* accessors has the arguments in opposite order from the usual
+ * linux PCI accessors. Unlike those, they take the address first and the value
+ * next.
+ *
+ * Note: I might drop the _ns suffix on the stream operations soon as it is
+ * simply normal for stream operations to not swap in the first place.
+ *
+ */
+#ifdef CONFIG_PPC64
+#define IO_SET_SYNC_FLAG()      do { get_paca()->io_sync = 1; } while(0)
+#else
+#define IO_SET_SYNC_FLAG()
+#endif
+#define DEF_MMIO_IN(name, type, insn)                                   \
+static inline type name(const volatile type __iomem *addr)              \
+{                                                                       \
+        type ret;                                                       \
+        __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync"           \
+                : "=r" (ret) : "r" (addr), "m" (*addr));                \
+        return ret;                                                     \
+}
+#define DEF_MMIO_OUT(name, type, insn)                                  \
+static inline void name(volatile type __iomem *addr, type val)          \
+{                                                                       \
+        __asm__ __volatile__("sync;" insn                               \
+                : "=m" (*addr) : "r" (val), "r" (addr));                \
+        IO_SET_SYNC_FLAG();                                     \
+}
+#define DEF_MMIO_IN_BE(name, size, insn) \
+        DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2")
+#define DEF_MMIO_IN_LE(name, size, insn) \
+        DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1")
+#define DEF_MMIO_OUT_BE(name, size, insn) \
+        DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0")
+#define DEF_MMIO_OUT_LE(name, size, insn) \
+        DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2")
+DEF_MMIO_IN_BE(in_8,     8, lbz);
+DEF_MMIO_IN_BE(in_be16, 16, lhz);
+DEF_MMIO_IN_BE(in_be32, 32, lwz);
+DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
+DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
+DEF_MMIO_OUT_BE(out_8,     8, stb);
+DEF_MMIO_OUT_BE(out_be16, 16, sth);
+DEF_MMIO_OUT_BE(out_be32, 32, stw);
+DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
+DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
+#ifdef __powerpc64__
+DEF_MMIO_OUT_BE(out_be64, 64, std);
+DEF_MMIO_IN_BE(in_be64, 64, ld);
+/* There is no asm instructions for 64 bits reverse loads and stores */
+static inline u64 in_le64(const volatile u64 __iomem *addr)
+{
+        return le64_to_cpu(in_be64(addr));
+}
+static inline void out_le64(volatile u64 __iomem *addr, u64 val)
+{
+        out_be64(addr, cpu_to_le64(val));
+}
+#endif /* __powerpc64__ */
+/*
+ * Low level IO stream instructions are defined out of line for now
+ */
+extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
+extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
+extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
+extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
+extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
+extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
+/* The _ns naming is historical and will be removed. For now, just #define
+ * the non _ns equivalent names
+ */
+#define _insw   _insw_ns
+#define _insl   _insl_ns
+#define _outsw  _outsw_ns
+#define _outsl  _outsl_ns
+/*
+ * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
+ */
+extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
+extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
+                           unsigned long n);
+extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
+                         unsigned long n);
+/*
+ *
+ * PCI and standard ISA accessors
+ *
+ * Those are globally defined linux accessors for devices on PCI or ISA
+ * busses. They follow the Linux defined semantics. The current implementation
+ * for PowerPC is as close as possible to the x86 version of these, and thus
+ * provides fairly heavy weight barriers for the non-raw versions
+ *
+ * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
+ * allowing the platform to provide its own implementation of some or all
+ * of the accessors.
+ */
+/*
+ * Include the EEH definitions when EEH is enabled only so they don't get
+ * in the way when building for 32 bits
+ */
+#ifdef CONFIG_EEH
+#include <asm/eeh.h>
+#endif
+/* Shortcut to the MMIO argument pointer */
+#define PCI_IO_ADDR     volatile void __iomem *
+/* Indirect IO address tokens:
+ *
+ * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
+ * on all IOs. (Note that this is all 64 bits only for now)
+ *
+ * To help platforms who may need to differenciate MMIO addresses in
+ * their hooks, a bitfield is reserved for use by the platform near the
+ * top of MMIO addresses (not PIO, those have to cope the hard way).
+ *
+ * This bit field is 12 bits and is at the top of the IO virtual
+ * addresses PCI_IO_INDIRECT_TOKEN_MASK.
+ *
+ * The kernel virtual space is thus:
+ *
+ *  0xD000000000000000          : vmalloc
+ *  0xD000080000000000          : PCI PHB IO space
+ *  0xD000080080000000          : ioremap
+ *  0xD0000fffffffffff          : end of ioremap region
+ *
+ * Since the top 4 bits are reserved as the region ID, we use thus
+ * the next 12 bits and keep 4 bits available for the future if the
+ * virtual address space is ever to be extended.
+ *
+ * The direct IO mapping operations will then mask off those bits
+ * before doing the actual access, though that only happen when
+ * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
+ * mechanism
+ */
+#ifdef CONFIG_PPC_INDIRECT_IO
+#define PCI_IO_IND_TOKEN_MASK   0x0fff000000000000ul
+#define PCI_IO_IND_TOKEN_SHIFT  48
+#define PCI_FIX_ADDR(addr)                                              \
+        ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
+#define PCI_GET_ADDR_TOKEN(addr)                                        \
+        (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
+                PCI_IO_IND_TOKEN_SHIFT)
+#define PCI_SET_ADDR_TOKEN(addr, token)                                 \
+do {                                                                    \
+        unsigned long __a = (unsigned long)(addr);                      \
+        __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
+        __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
+        (addr) = (void __iomem *)__a;                                   \
+} while(0)
+#else
+#define PCI_FIX_ADDR(addr) (addr)
+#endif
-#ifdef CONFIG_PPC_ISERIES
+/*
-extern int in_8(const volatile unsigned char __iomem *addr);
+ * Non ordered and non-swapping "raw" accessors
-extern void out_8(volatile unsigned char __iomem *addr, int val);
+ */
-extern int in_le16(const volatile unsigned short __iomem *addr);
-extern int in_be16(const volatile unsigned short __iomem *addr);
-extern void out_le16(volatile unsigned short __iomem *addr, int val);
-extern void out_be16(volatile unsigned short __iomem *addr, int val);
-extern unsigned in_le32(const volatile unsigned __iomem *addr);
-extern unsigned in_be32(const volatile unsigned __iomem *addr);
-extern void out_le32(volatile unsigned __iomem *addr, int val);
-extern void out_be32(volatile unsigned __iomem *addr, int val);
-extern unsigned long in_le64(const volatile unsigned long __iomem *addr);
-extern unsigned long in_be64(const volatile unsigned long __iomem *addr);
-extern void out_le64(volatile unsigned long __iomem *addr, unsigned long val);
-extern void out_be64(volatile unsigned long __iomem *addr, unsigned long val);
-extern unsigned char __raw_readb(const volatile void __iomem *addr);
-extern unsigned short __raw_readw(const volatile void __iomem *addr);
-extern unsigned int __raw_readl(const volatile void __iomem *addr);
-extern unsigned long __raw_readq(const volatile void __iomem *addr);
-extern void __raw_writeb(unsigned char v, volatile void __iomem *addr);
-extern void __raw_writew(unsigned short v, volatile void __iomem *addr);
-extern void __raw_writel(unsigned int v, volatile void __iomem *addr);
-extern void __raw_writeq(unsigned long v, volatile void __iomem *addr);
-extern void memset_io(volatile void __iomem *addr, int c, unsigned long n);
-extern void memcpy_fromio(void *dest, const volatile void __iomem *src,
-                                 unsigned long n);
-extern void memcpy_toio(volatile void __iomem *dest, const void *src,
-                                 unsigned long n);
-#else /* CONFIG_PPC_ISERIES */
-#define in_8(addr)              __in_8((addr))
-#define out_8(addr, val)        __out_8((addr), (val))
-#define in_le16(addr)           __in_le16((addr))
-#define in_be16(addr)           __in_be16((addr))
-#define out_le16(addr, val)     __out_le16((addr), (val))
-#define out_be16(addr, val)     __out_be16((addr), (val))
-#define in_le32(addr)           __in_le32((addr))
-#define in_be32(addr)           __in_be32((addr))
-#define out_le32(addr, val)     __out_le32((addr), (val))
-#define out_be32(addr, val)     __out_be32((addr), (val))
-#define in_le64(addr)           __in_le64((addr))
-#define in_be64(addr)           __in_be64((addr))
-#define out_le64(addr, val)     __out_le64((addr), (val))
-#define out_be64(addr, val)     __out_be64((addr), (val))
 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 {
-        return *(volatile unsigned char __force *)addr;
+        return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
 }
 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 {
-        return *(volatile unsigned short __force *)addr;
+        return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
 }
 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 {
-        return *(volatile unsigned int __force *)addr;
+        return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
-}
-static inline unsigned long __raw_readq(const volatile void __iomem *addr)
-{
-        return *(volatile unsigned long __force *)addr;
 }
 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 {
-        *(volatile unsigned char __force *)addr = v;
+        *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
 }
 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 {
-        *(volatile unsigned short __force *)addr = v;
+        *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
 }
 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 {
-        *(volatile unsigned int __force *)addr = v;
+        *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
+}
+#ifdef __powerpc64__
+static inline unsigned long __raw_readq(const volatile void __iomem *addr)
+{
+        return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
 }
 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 {
-        *(volatile unsigned long __force *)addr = v;
+        *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
+}
+#endif /* __powerpc64__ */
+/*
+ *
+ * PCI PIO and MMIO accessors.
+ *
+ *
+ * On 32 bits, PIO operations have a recovery mechanism in case they trigger
+ * machine checks (which they occasionally do when probing non existing
+ * IO ports on some platforms, like PowerMac and 8xx).
+ * I always found it to be of dubious reliability and I am tempted to get
+ * rid of it one of these days. So if you think it's important to keep it,
+ * please voice up asap. We never had it for 64 bits and I do not intend
+ * to port it over
+ */
+#ifdef CONFIG_PPC32
+#define __do_in_asm(name, op)                           \
+static inline unsigned int name(unsigned int port)      \
+{                                                       \
+        unsigned int x;                                 \
+        __asm__ __volatile__(                           \
+                "sync\n"                                \
+                "0:"    op "    %0,0,%1\n"              \
+                "1:     twi     0,%0,0\n"               \
+                "2:     isync\n"                        \
+                "3:     nop\n"                          \
+                "4:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "5:     li      %0,-1\n"                \
+                "       b       4b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align  2\n"                    \
+                "       .long   0b,5b\n"                \
+                "       .long   1b,5b\n"                \
+                "       .long   2b,5b\n"                \
+                "       .long   3b,5b\n"                \
+                ".previous"                             \
+                : "=&r" (x)                             \
+                : "r" (port + _IO_BASE));               \
+        return x;                                       \
+}
+#define __do_out_asm(name, op)                          \
+static inline void name(unsigned int val, unsigned int port) \
+{                                                       \
+        __asm__ __volatile__(                           \
+                "sync\n"                                \
+                "0:" op " %0,0,%1\n"                    \
+                "1:     sync\n"                         \
+                "2:\n"                                  \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align  2\n"                    \
+                "       .long   0b,2b\n"                \
+                "       .long   1b,2b\n"                \
+                ".previous"                             \
+                : : "r" (val), "r" (port + _IO_BASE));  \
+}
+__do_in_asm(_rec_inb, "lbzx")
+__do_in_asm(_rec_inw, "lhbrx")
+__do_in_asm(_rec_inl, "lwbrx")
+__do_out_asm(_rec_outb, "stbx")
+__do_out_asm(_rec_outw, "sthbrx")
+__do_out_asm(_rec_outl, "stwbrx")
+#endif /* CONFIG_PPC32 */
+/* The "__do_*" operations below provide the actual "base" implementation
+ * for each of the defined acccessor. Some of them use the out_* functions
+ * directly, some of them still use EEH, though we might change that in the
+ * future. Those macros below provide the necessary argument swapping and
+ * handling of the IO base for PIO.
+ *
+ * They are themselves used by the macros that define the actual accessors
+ * and can be used by the hooks if any.
+ *
+ * Note that PIO operations are always defined in terms of their corresonding
+ * MMIO operations. That allows platforms like iSeries who want to modify the
+ * behaviour of both to only hook on the MMIO version and get both. It's also
+ * possible to hook directly at the toplevel PIO operation if they have to
+ * be handled differently
+ */
+#define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
+#define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
+#define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
+#define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
+#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
+#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
+#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
+#ifdef CONFIG_EEH
+#define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
+#define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
+#define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
+#define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
+#define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
+#define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
+#define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
+#else /* CONFIG_EEH */
+#define __do_readb(addr)        in_8(PCI_FIX_ADDR(addr))
+#define __do_readw(addr)        in_le16(PCI_FIX_ADDR(addr))
+#define __do_readl(addr)        in_le32(PCI_FIX_ADDR(addr))
+#define __do_readq(addr)        in_le64(PCI_FIX_ADDR(addr))
+#define __do_readw_be(addr)     in_be16(PCI_FIX_ADDR(addr))
+#define __do_readl_be(addr)     in_be32(PCI_FIX_ADDR(addr))
+#define __do_readq_be(addr)     in_be64(PCI_FIX_ADDR(addr))
+#endif /* !defined(CONFIG_EEH) */
+#ifdef CONFIG_PPC32
+#define __do_outb(val, port)    _rec_outb(val, port)
+#define __do_outw(val, port)    _rec_outw(val, port)
+#define __do_outl(val, port)    _rec_outl(val, port)
+#define __do_inb(port)          _rec_inb(port)
+#define __do_inw(port)          _rec_inw(port)
+#define __do_inl(port)          _rec_inl(port)
+#else /* CONFIG_PPC32 */
+#define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
+#define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
+#define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
+#define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
+#define __do_inw(port)          readw((PCI_IO_ADDR)_IO_BASE + port);
+#define __do_inl(port)          readl((PCI_IO_ADDR)_IO_BASE + port);
+#endif /* !CONFIG_PPC32 */
+#ifdef CONFIG_EEH
+#define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
+#define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
+#define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
+#else /* CONFIG_EEH */
+#define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
+#define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
+#define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
+#endif /* !CONFIG_EEH */
+#define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
+#define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
+#define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
+#define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
+#define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
+#define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
+#define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
+#define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
+#define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
+#define __do_memset_io(addr, c, n)      \
+                                _memset_io(PCI_FIX_ADDR(addr), c, n)
+#define __do_memcpy_toio(dst, src, n)   \
+                                _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
+#ifdef CONFIG_EEH
+#define __do_memcpy_fromio(dst, src, n) \
+                                eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
+#else /* CONFIG_EEH */
+#define __do_memcpy_fromio(dst, src, n) \
+                                _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
+#endif /* !CONFIG_EEH */
+#ifdef CONFIG_PPC_INDIRECT_IO
+#define DEF_PCI_HOOK(x)         x
+#else
+#define DEF_PCI_HOOK(x)         NULL
+#endif
+/* Structure containing all the hooks */
+extern struct ppc_pci_io {
+#define DEF_PCI_AC_RET(name, ret, at, al)       ret (*name) at;
+#define DEF_PCI_AC_NORET(name, at, al)          void (*name) at;
+#include <asm/io-defs.h>
+#undef DEF_PCI_AC_RET
+#undef DEF_PCI_AC_NORET
+} ppc_pci_io;
+/* The inline wrappers */
+#define DEF_PCI_AC_RET(name, ret, at, al)                       \
+static inline ret name at                                       \
+{                                                               \
+        if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
+                return ppc_pci_io.name al;                      \
+        return __do_##name al;                                  \
+}
+#define DEF_PCI_AC_NORET(name, at, al)                          \
+static inline void name at                                      \
+{                                                               \
+        if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
+                ppc_pci_io.name al;                             \
+        else                                                    \
+                __do_##name al;                                 \
 }
-#define memset_io(a,b,c)        eeh_memset_io((a),(b),(c))
-#define memcpy_fromio(a,b,c)    eeh_memcpy_fromio((a),(b),(c))
-#define memcpy_toio(a,b,c)      eeh_memcpy_toio((a),(b),(c))
-#endif /* CONFIG_PPC_ISERIES */
+#include <asm/io-defs.h>
+#undef DEF_PCI_AC_RET
+#undef DEF_PCI_AC_NORET
+/* Some drivers check for the presence of readq & writeq with
+ * a #ifdef, so we make them happy here.
+ */
+#ifdef __powerpc64__
+#define readq   readq
+#define writeq  writeq
+#endif
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define dma_cache_inv(_start,_size) \
+        invalidate_dcache_range(_start, (_start + _size))
+#define dma_cache_wback(_start,_size) \
+        clean_dcache_range(_start, (_start + _size))
+#define dma_cache_wback_inv(_start,_size) \
+        flush_dcache_range(_start, (_start + _size))
+#else /* CONFIG_NOT_COHERENT_CACHE */
+#define dma_cache_inv(_start,_size)             do { } while (0)
+#define dma_cache_wback(_start,_size)           do { } while (0)
+#define dma_cache_wback_inv(_start,_size)       do { } while (0)
+#endif /* !CONFIG_NOT_COHERENT_CACHE */
 /*
- * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * They are only used in practice for transferring buffers which
+ * access
- * are arrays of bytes, and byte-swapping is not appropriate in
+ */
- * that case.  - paulus */
+#define xlate_dev_mem_ptr(p)    __va(p)
-#define insb(port, buf, ns)     eeh_insb((port), (buf), (ns))
-#define insw(port, buf, ns)     eeh_insw_ns((port), (buf), (ns))
+/*
-#define insl(port, buf, nl)     eeh_insl_ns((port), (buf), (nl))
+ * Convert a virtual cached pointer to an uncached pointer
+ */
-#define outsb(port, buf, ns)  _outsb((u8 __iomem *)((port)+pci_io_base), (buf), (ns))
+#define xlate_dev_kmem_ptr(p)   p
-#define outsw(port, buf, ns)  _outsw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
-#define outsl(port, buf, nl)  _outsl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
-#define readb(addr)             eeh_readb(addr)
-#define readw(addr)             eeh_readw(addr)
-#define readl(addr)             eeh_readl(addr)
-#define readq(addr)             eeh_readq(addr)
-#define writeb(data, addr)      eeh_writeb((data), (addr))
-#define writew(data, addr)      eeh_writew((data), (addr))
-#define writel(data, addr)      eeh_writel((data), (addr))
-#define writeq(data, addr)      eeh_writeq((data), (addr))
-#define inb(port)               eeh_inb((unsigned long)port)
-#define outb(val, port)         eeh_outb(val, (unsigned long)port)
-#define inw(port)               eeh_inw((unsigned long)port)
-#define outw(val, port)         eeh_outw(val, (unsigned long)port)
-#define inl(port)               eeh_inl((unsigned long)port)
-#define outl(val, port)         eeh_outl(val, (unsigned long)port)
+/*
+ * We don't do relaxed operations yet, at least not with this semantic
+ */
 #define readb_relaxed(addr) readb(addr)
 #define readw_relaxed(addr) readw(addr)
 #define readl_relaxed(addr) readl(addr)
 #define readq_relaxed(addr) readq(addr)
-extern void _insb(volatile u8 __iomem *port, void *buf, long count);
+#ifdef CONFIG_PPC32
-extern void _outsb(volatile u8 __iomem *port, const void *buf, long count);
+#define mmiowb()
-extern void _insw_ns(volatile u16 __iomem *port, void *buf, long count);
+#else
-extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, long count);
+/*
-extern void _insl_ns(volatile u32 __iomem *port, void *buf, long count);
+ * Enforce synchronisation of stores vs. spin_unlock
-extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, long count);
+ * (this does it explicitely, though our implementation of spin_unlock
+ * does it implicitely too)
+ */
 static inline void mmiowb(void)
 {
        unsigned long tmp;
@@ -169,6 +545,24 @@ static inline void mmiowb(void)
        : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
        : "memory");
 }
+#endif /* !CONFIG_PPC32 */
+static inline void iosync(void)
+{
+        __asm__ __volatile__ ("sync" : : : "memory");
+}
+/* Enforce in-order execution of data I/O.
+ * No distinction between read/write on PPC; use eieio for all three.
+ * Those are fairly week though. They don't provide a barrier between
+ * MMIO and cacheable storage nor do they provide a barrier vs. locks,
+ * they only provide barriers between 2 __raw MMIO operations and
+ * possibly break write combining.
+ */
+#define iobarrier_rw() eieio()
+#define iobarrier_r()  eieio()
+#define iobarrier_w()  eieio()
 /*
 * output pause versions need a delay at least for the
@@ -185,11 +579,6 @@ static inline void mmiowb(void)
 #define IO_SPACE_LIMIT ~(0UL)
-extern int __ioremap_explicit(unsigned long p_addr, unsigned long v_addr,
-                              unsigned long size, unsigned long flags);
-extern void __iomem *__ioremap(unsigned long address, unsigned long size,
-                       unsigned long flags);
 /**
 * ioremap     -   map bus memory into CPU space
 * @address:   bus address of the memory
@@ -200,14 +589,77 @@ extern void __iomem *__ioremap(unsigned long address, unsigned long size,
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
+ *
+ * We provide a few variations of it:
+ *
+ * * ioremap is the standard one and provides non-cacheable guarded mappings
+ *   and can be hooked by the platform via ppc_md
+ *
+ * * ioremap_flags allows to specify the page flags as an argument and can
+ *   also be hooked by the platform via ppc_md
+ *
+ * * ioremap_nocache is identical to ioremap
+ *
+ * * iounmap undoes such a mapping and can be hooked
+ *
+ * * __ioremap_explicit (and the pending __iounmap_explicit) are low level
+ *   functions to create hand-made mappings for use only by the PCI code
+ *   and cannot currently be hooked.
+ *
+ * * __ioremap is the low level implementation used by ioremap and
+ *   ioremap_flags and cannot be hooked (but can be used by a hook on one
+ *   of the previous ones)
+ *
+ * * __iounmap, is the low level implementation used by iounmap and cannot
+ *   be hooked (but can be used by a hook on iounmap)
+ *
 */
-extern void __iomem *ioremap(unsigned long address, unsigned long size);
+extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
+extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
+                                   unsigned long flags);
 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
-extern int iounmap_explicit(volatile void __iomem *addr, unsigned long size);
 extern void iounmap(volatile void __iomem *addr);
+extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
+                               unsigned long flags);
+extern void __iounmap(volatile void __iomem *addr);
+extern int __ioremap_explicit(phys_addr_t p_addr, unsigned long v_addr,
+                              unsigned long size, unsigned long flags);
+extern int __iounmap_explicit(volatile void __iomem *start,
+                              unsigned long size);
 extern void __iomem * reserve_phb_iospace(unsigned long size);
+/* Those are more 32 bits only functions */
+extern unsigned long iopa(unsigned long addr);
+extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
+extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
+                             unsigned int size, int flags);
+/*
+ * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
+ * which needs some additional definitions here. They basically allow PIO
+ * space overall to be 1GB. This will work as long as we never try to use
+ * iomap to map MMIO below 1GB which should be fine on ppc64
+ */
+#define HAVE_ARCH_PIO_SIZE              1
+#define PIO_OFFSET                      0x00000000UL
+#define PIO_MASK                        0x3fffffffUL
+#define PIO_RESERVED                    0x40000000UL
+#define mmio_read16be(addr)             readw_be(addr)
+#define mmio_read32be(addr)             readl_be(addr)
+#define mmio_write16be(val, addr)       writew_be(val, addr)
+#define mmio_write32be(val, addr)       writel_be(val, addr)
+#define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
+#define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
+#define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
+#define mmio_outsb(addr, src, count)    writesb(addr, src, count)
+#define mmio_outsw(addr, src, count)    writesw(addr, src, count)
+#define mmio_outsl(addr, src, count)    writesl(addr, src, count)
 /**
 *      virt_to_phys    -       map virtual addresses to physical
 *      @address: address to remap
@@ -254,178 +706,33 @@ static inline void * phys_to_virt(unsigned long address)
 */
 #define BIO_VMERGE_BOUNDARY     0
-static inline void iosync(void)
-{
-        __asm__ __volatile__ ("sync" : : : "memory");
-}
-/* Enforce in-order execution of data I/O. 
- * No distinction between read/write on PPC; use eieio for all three.
- */
-#define iobarrier_rw() eieio()
-#define iobarrier_r()  eieio()
-#define iobarrier_w()  eieio()
 /*
- * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ * 32 bits still uses virt_to_bus() for it's implementation of DMA
- * These routines do not perform EEH-related I/O address translation,
+ * mappings se we have to keep it defined here. We also have some old
- * and should not be used directly by device drivers.  Use inb/readb
+ * drivers (shame shame shame) that use bus_to_virt() and haven't been
- * instead.
+ * fixed yet so I need to define it here.
 */
-static inline int __in_8(const volatile unsigned char __iomem *addr)
+#ifdef CONFIG_PPC32
-{
-        int ret;
-        __asm__ __volatile__("sync; lbz%U1%X1 %0,%1; twi 0,%0,0; isync"
+static inline unsigned long virt_to_bus(volatile void * address)
-                             : "=r" (ret) : "m" (*addr));
-        return ret;
-}
-static inline void __out_8(volatile unsigned char __iomem *addr, int val)
-{
-        __asm__ __volatile__("sync; stb%U0%X0 %1,%0"
-                             : "=m" (*addr) : "r" (val));
-        get_paca()->io_sync = 1;
-}
-static inline int __in_le16(const volatile unsigned short __iomem *addr)
 {
-        int ret;
+        if (address == NULL)
+                return 0;
-        __asm__ __volatile__("sync; lhbrx %0,0,%1; twi 0,%0,0; isync"
+        return __pa(address) + PCI_DRAM_OFFSET;
-                             : "=r" (ret) : "r" (addr), "m" (*addr));
-        return ret;
 }
-static inline int __in_be16(const volatile unsigned short __iomem *addr)
+static inline void * bus_to_virt(unsigned long address)
 {
-        int ret;
+        if (address == 0)
+                return NULL;
-        __asm__ __volatile__("sync; lhz%U1%X1 %0,%1; twi 0,%0,0; isync"
+        return __va(address - PCI_DRAM_OFFSET);
-                             : "=r" (ret) : "m" (*addr));
-        return ret;
 }
-static inline void __out_le16(volatile unsigned short __iomem *addr, int val)
+#define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
-{
-        __asm__ __volatile__("sync; sthbrx %1,0,%2"
-                             : "=m" (*addr) : "r" (val), "r" (addr));
-        get_paca()->io_sync = 1;
-}
-static inline void __out_be16(volatile unsigned short __iomem *addr, int val)
-{
-        __asm__ __volatile__("sync; sth%U0%X0 %1,%0"
-                             : "=m" (*addr) : "r" (val));
-        get_paca()->io_sync = 1;
-}
-static inline unsigned __in_le32(const volatile unsigned __iomem *addr)
-{
-        unsigned ret;
-        __asm__ __volatile__("sync; lwbrx %0,0,%1; twi 0,%0,0; isync"
-                             : "=r" (ret) : "r" (addr), "m" (*addr));
-        return ret;
-}
-static inline unsigned __in_be32(const volatile unsigned __iomem *addr)
+#endif /* CONFIG_PPC32 */
-{
-        unsigned ret;
-        __asm__ __volatile__("sync; lwz%U1%X1 %0,%1; twi 0,%0,0; isync"
-                             : "=r" (ret) : "m" (*addr));
-        return ret;
-}
-static inline void __out_le32(volatile unsigned __iomem *addr, int val)
-{
-        __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr)
-                             : "r" (val), "r" (addr));
-        get_paca()->io_sync = 1;
-}
-static inline void __out_be32(volatile unsigned __iomem *addr, int val)
-{
-        __asm__ __volatile__("sync; stw%U0%X0 %1,%0"
-                             : "=m" (*addr) : "r" (val));
-        get_paca()->io_sync = 1;
-}
-static inline unsigned long __in_le64(const volatile unsigned long __iomem *addr)
-{
-        unsigned long tmp, ret;
-        __asm__ __volatile__(
-                             "sync\n"
-                             "ld %1,0(%2)\n"
-                             "twi 0,%1,0\n"
-                             "isync\n"
-                             "rldimi %0,%1,5*8,1*8\n"
-                             "rldimi %0,%1,3*8,2*8\n"
-                             "rldimi %0,%1,1*8,3*8\n"
-                             "rldimi %0,%1,7*8,4*8\n"
-                             "rldicl %1,%1,32,0\n"
-                             "rlwimi %0,%1,8,8,31\n"
-                             "rlwimi %0,%1,24,16,23\n"
-                             : "=r" (ret) , "=r" (tmp) : "b" (addr) , "m" (*addr));
-        return ret;
-}
-static inline unsigned long __in_be64(const volatile unsigned long __iomem *addr)
-{
-        unsigned long ret;
-        __asm__ __volatile__("sync; ld%U1%X1 %0,%1; twi 0,%0,0; isync"
-                             : "=r" (ret) : "m" (*addr));
-        return ret;
-}
-static inline void __out_le64(volatile unsigned long __iomem *addr, unsigned long val)
-{
-        unsigned long tmp;
-        __asm__ __volatile__(
-                             "rldimi %0,%1,5*8,1*8\n"
-                             "rldimi %0,%1,3*8,2*8\n"
-                             "rldimi %0,%1,1*8,3*8\n"
-                             "rldimi %0,%1,7*8,4*8\n"
-                             "rldicl %1,%1,32,0\n"
-                             "rlwimi %0,%1,8,8,31\n"
-                             "rlwimi %0,%1,24,16,23\n"
-                             "sync\n"
-                             "std %0,0(%3)"
-                             : "=&r" (tmp) , "=&r" (val) : "1" (val) , "b" (addr) , "m" (*addr));
-        get_paca()->io_sync = 1;
-}
-static inline void __out_be64(volatile unsigned long __iomem *addr, unsigned long val)
-{
-        __asm__ __volatile__("sync; std%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-        get_paca()->io_sync = 1;
-}
-#include <asm/eeh.h>
-/* Nothing to do */
-#define dma_cache_inv(_start,_size)             do { } while (0)
-#define dma_cache_wback(_start,_size)           do { } while (0)
-#define dma_cache_wback_inv(_start,_size)       do { } while (0)
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
 #endif /* __KERNEL__ */
-#endif /* CONFIG_PPC64 */
 #endif /* _ASM_POWERPC_IO_H */
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
index 39fad685ffab..f85dbd305558 100644
--- a/include/asm-powerpc/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -34,7 +34,9 @@
 #define IOMMU_PAGE_MASK       (~((1 << IOMMU_PAGE_SHIFT) - 1))
 #define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
-#ifndef __ASSEMBLY__
+/* Boot time flags */
+extern int iommu_is_off;
+extern int iommu_force_on;
 /* Pure 2^n version of get_order */
 static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
@@ -42,8 +44,6 @@ static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
        return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
 }
-#endif   /* __ASSEMBLY__ */
 /*
 * IOMAP_MAX_ORDER defines the largest contiguous block
@@ -70,39 +70,31 @@ struct iommu_table {
 struct scatterlist;
 struct device_node;
-#ifdef CONFIG_PPC_MULTIPLATFORM
-/* Walks all buses and creates iommu tables */
-extern void iommu_setup_pSeries(void);
-extern void iommu_setup_dart(void);
 /* Frees table for an individual device node */
 extern void iommu_free_table(struct device_node *dn);
-#endif /* CONFIG_PPC_MULTIPLATFORM */
 /* Initializes an iommu_table based in values set in the passed-in
 * structure
 */
 extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
                                            int nid);
-extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
+extern int iommu_map_sg(struct iommu_table *tbl, struct scatterlist *sglist,
-                struct scatterlist *sglist, int nelems, unsigned long mask,
+                        int nelems, unsigned long mask,
-                enum dma_data_direction direction);
+                        enum dma_data_direction direction);
 extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
-                int nelems, enum dma_data_direction direction);
+                           int nelems, enum dma_data_direction direction);
 extern void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
-                dma_addr_t *dma_handle, unsigned long mask,
+                                  dma_addr_t *dma_handle, unsigned long mask,
-                gfp_t flag, int node);
+                                  gfp_t flag, int node);
 extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
-                void *vaddr, dma_addr_t dma_handle);
+                                void *vaddr, dma_addr_t dma_handle);
 extern dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
-                size_t size, unsigned long mask,
+                                   size_t size, unsigned long mask,
-                enum dma_data_direction direction);
+                                   enum dma_data_direction direction);
 extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
-                size_t size, enum dma_data_direction direction);
+                               size_t size, enum dma_data_direction direction);
 extern void iommu_init_early_pSeries(void);
 extern void iommu_init_early_iSeries(void);
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index f960f5346f40..46476e9a494a 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -135,6 +135,10 @@ struct irq_map_entry {
 extern struct irq_map_entry irq_map[NR_IRQS];
+static inline irq_hw_number_t virq_to_hw(unsigned int virq)
+{
+        return irq_map[virq].hwirq;
+}
 /**
 * irq_alloc_host - Allocate a new irq_host data structure
diff --git a/include/asm-powerpc/iseries/iommu.h b/include/asm-powerpc/iseries/iommu.h
index 0edbfe10cb37..6e323a13ac30 100644
--- a/include/asm-powerpc/iseries/iommu.h
+++ b/include/asm-powerpc/iseries/iommu.h
@@ -21,11 +21,13 @@
 * Boston, MA  02111-1307  USA
 */
+struct pci_dev;
 struct device_node;
 struct iommu_table;
 /* Creates table for an individual device node */
-extern void iommu_devnode_init_iSeries(struct device_node *dn);
+extern void iommu_devnode_init_iSeries(struct pci_dev *pdev,
+                                       struct device_node *dn);
 /* Get table parameters from HV */
 extern void iommu_table_getparms_iSeries(unsigned long busno,
diff --git a/include/asm-powerpc/lv1call.h b/include/asm-powerpc/lv1call.h
new file mode 100644
index 000000000000..f733beeea63a
--- /dev/null
+++ b/include/asm-powerpc/lv1call.h
@@ -0,0 +1,345 @@
+/*
+ *  PS3 hvcall interface.
+ *
+ *  Copyright (C) 2006 Sony Computer Entertainment Inc.
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2003, 2004 (c) MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#if !defined(_ASM_POWERPC_LV1CALL_H)
+#define _ASM_POWERPC_LV1CALL_H
+#if !defined(__ASSEMBLY__)
+#include <linux/types.h>
+/* lv1 call declaration macros */
+#define LV1_1_IN_ARG_DECL u64 in_1
+#define LV1_2_IN_ARG_DECL LV1_1_IN_ARG_DECL, u64 in_2
+#define LV1_3_IN_ARG_DECL LV1_2_IN_ARG_DECL, u64 in_3
+#define LV1_4_IN_ARG_DECL LV1_3_IN_ARG_DECL, u64 in_4
+#define LV1_5_IN_ARG_DECL LV1_4_IN_ARG_DECL, u64 in_5
+#define LV1_6_IN_ARG_DECL LV1_5_IN_ARG_DECL, u64 in_6
+#define LV1_7_IN_ARG_DECL LV1_6_IN_ARG_DECL, u64 in_7
+#define LV1_8_IN_ARG_DECL LV1_7_IN_ARG_DECL, u64 in_8
+#define LV1_1_OUT_ARG_DECL u64 *out_1
+#define LV1_2_OUT_ARG_DECL LV1_1_OUT_ARG_DECL, u64 *out_2
+#define LV1_3_OUT_ARG_DECL LV1_2_OUT_ARG_DECL, u64 *out_3
+#define LV1_4_OUT_ARG_DECL LV1_3_OUT_ARG_DECL, u64 *out_4
+#define LV1_5_OUT_ARG_DECL LV1_4_OUT_ARG_DECL, u64 *out_5
+#define LV1_6_OUT_ARG_DECL LV1_5_OUT_ARG_DECL, u64 *out_6
+#define LV1_7_OUT_ARG_DECL LV1_6_OUT_ARG_DECL, u64 *out_7
+#define LV1_0_IN_0_OUT_ARG_DECL void
+#define LV1_1_IN_0_OUT_ARG_DECL LV1_1_IN_ARG_DECL
+#define LV1_2_IN_0_OUT_ARG_DECL LV1_2_IN_ARG_DECL
+#define LV1_3_IN_0_OUT_ARG_DECL LV1_3_IN_ARG_DECL
+#define LV1_4_IN_0_OUT_ARG_DECL LV1_4_IN_ARG_DECL
+#define LV1_5_IN_0_OUT_ARG_DECL LV1_5_IN_ARG_DECL
+#define LV1_6_IN_0_OUT_ARG_DECL LV1_6_IN_ARG_DECL
+#define LV1_7_IN_0_OUT_ARG_DECL LV1_7_IN_ARG_DECL
+#define LV1_0_IN_1_OUT_ARG_DECL                    LV1_1_OUT_ARG_DECL
+#define LV1_1_IN_1_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_2_IN_1_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_3_IN_1_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_4_IN_1_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_5_IN_1_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_6_IN_1_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_7_IN_1_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_8_IN_1_OUT_ARG_DECL LV1_8_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_0_IN_2_OUT_ARG_DECL                    LV1_2_OUT_ARG_DECL
+#define LV1_1_IN_2_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_2_IN_2_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_3_IN_2_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_4_IN_2_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_5_IN_2_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_6_IN_2_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_7_IN_2_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_0_IN_3_OUT_ARG_DECL                    LV1_3_OUT_ARG_DECL
+#define LV1_1_IN_3_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_2_IN_3_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_3_IN_3_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_4_IN_3_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_5_IN_3_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_6_IN_3_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_7_IN_3_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_0_IN_4_OUT_ARG_DECL                    LV1_4_OUT_ARG_DECL
+#define LV1_1_IN_4_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_2_IN_4_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_3_IN_4_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_4_IN_4_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_5_IN_4_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_6_IN_4_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_7_IN_4_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_0_IN_5_OUT_ARG_DECL                    LV1_5_OUT_ARG_DECL
+#define LV1_1_IN_5_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_2_IN_5_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_3_IN_5_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_4_IN_5_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_5_IN_5_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_6_IN_5_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_7_IN_5_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_0_IN_6_OUT_ARG_DECL                    LV1_6_OUT_ARG_DECL
+#define LV1_1_IN_6_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_2_IN_6_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_3_IN_6_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_4_IN_6_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_5_IN_6_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_6_IN_6_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_7_IN_6_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_0_IN_7_OUT_ARG_DECL                    LV1_7_OUT_ARG_DECL
+#define LV1_1_IN_7_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_2_IN_7_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_3_IN_7_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_4_IN_7_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_5_IN_7_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_6_IN_7_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_7_IN_7_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_1_IN_ARGS in_1
+#define LV1_2_IN_ARGS LV1_1_IN_ARGS, in_2
+#define LV1_3_IN_ARGS LV1_2_IN_ARGS, in_3
+#define LV1_4_IN_ARGS LV1_3_IN_ARGS, in_4
+#define LV1_5_IN_ARGS LV1_4_IN_ARGS, in_5
+#define LV1_6_IN_ARGS LV1_5_IN_ARGS, in_6
+#define LV1_7_IN_ARGS LV1_6_IN_ARGS, in_7
+#define LV1_8_IN_ARGS LV1_7_IN_ARGS, in_8
+#define LV1_1_OUT_ARGS out_1
+#define LV1_2_OUT_ARGS LV1_1_OUT_ARGS, out_2
+#define LV1_3_OUT_ARGS LV1_2_OUT_ARGS, out_3
+#define LV1_4_OUT_ARGS LV1_3_OUT_ARGS, out_4
+#define LV1_5_OUT_ARGS LV1_4_OUT_ARGS, out_5
+#define LV1_6_OUT_ARGS LV1_5_OUT_ARGS, out_6
+#define LV1_7_OUT_ARGS LV1_6_OUT_ARGS, out_7
+#define LV1_0_IN_0_OUT_ARGS
+#define LV1_1_IN_0_OUT_ARGS LV1_1_IN_ARGS
+#define LV1_2_IN_0_OUT_ARGS LV1_2_IN_ARGS
+#define LV1_3_IN_0_OUT_ARGS LV1_3_IN_ARGS
+#define LV1_4_IN_0_OUT_ARGS LV1_4_IN_ARGS
+#define LV1_5_IN_0_OUT_ARGS LV1_5_IN_ARGS
+#define LV1_6_IN_0_OUT_ARGS LV1_6_IN_ARGS
+#define LV1_7_IN_0_OUT_ARGS LV1_7_IN_ARGS
+#define LV1_0_IN_1_OUT_ARGS                LV1_1_OUT_ARGS
+#define LV1_1_IN_1_OUT_ARGS LV1_1_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_2_IN_1_OUT_ARGS LV1_2_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_3_IN_1_OUT_ARGS LV1_3_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_4_IN_1_OUT_ARGS LV1_4_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_5_IN_1_OUT_ARGS LV1_5_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_6_IN_1_OUT_ARGS LV1_6_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_7_IN_1_OUT_ARGS LV1_7_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_8_IN_1_OUT_ARGS LV1_8_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_0_IN_2_OUT_ARGS                LV1_2_OUT_ARGS
+#define LV1_1_IN_2_OUT_ARGS LV1_1_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_2_IN_2_OUT_ARGS LV1_2_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_3_IN_2_OUT_ARGS LV1_3_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_4_IN_2_OUT_ARGS LV1_4_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_5_IN_2_OUT_ARGS LV1_5_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_6_IN_2_OUT_ARGS LV1_6_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_7_IN_2_OUT_ARGS LV1_7_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_0_IN_3_OUT_ARGS                LV1_3_OUT_ARGS
+#define LV1_1_IN_3_OUT_ARGS LV1_1_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_2_IN_3_OUT_ARGS LV1_2_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_3_IN_3_OUT_ARGS LV1_3_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_4_IN_3_OUT_ARGS LV1_4_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_5_IN_3_OUT_ARGS LV1_5_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_6_IN_3_OUT_ARGS LV1_6_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_7_IN_3_OUT_ARGS LV1_7_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_0_IN_4_OUT_ARGS                LV1_4_OUT_ARGS
+#define LV1_1_IN_4_OUT_ARGS LV1_1_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_2_IN_4_OUT_ARGS LV1_2_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_3_IN_4_OUT_ARGS LV1_3_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_4_IN_4_OUT_ARGS LV1_4_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_5_IN_4_OUT_ARGS LV1_5_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_6_IN_4_OUT_ARGS LV1_6_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_7_IN_4_OUT_ARGS LV1_7_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_0_IN_5_OUT_ARGS                LV1_5_OUT_ARGS
+#define LV1_1_IN_5_OUT_ARGS LV1_1_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_2_IN_5_OUT_ARGS LV1_2_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_3_IN_5_OUT_ARGS LV1_3_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_4_IN_5_OUT_ARGS LV1_4_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_5_IN_5_OUT_ARGS LV1_5_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_6_IN_5_OUT_ARGS LV1_6_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_7_IN_5_OUT_ARGS LV1_7_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_0_IN_6_OUT_ARGS                LV1_6_OUT_ARGS
+#define LV1_1_IN_6_OUT_ARGS LV1_1_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_2_IN_6_OUT_ARGS LV1_2_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_3_IN_6_OUT_ARGS LV1_3_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_4_IN_6_OUT_ARGS LV1_4_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_5_IN_6_OUT_ARGS LV1_5_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_6_IN_6_OUT_ARGS LV1_6_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_7_IN_6_OUT_ARGS LV1_7_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_0_IN_7_OUT_ARGS                LV1_7_OUT_ARGS
+#define LV1_1_IN_7_OUT_ARGS LV1_1_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_2_IN_7_OUT_ARGS LV1_2_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_3_IN_7_OUT_ARGS LV1_3_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_4_IN_7_OUT_ARGS LV1_4_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_5_IN_7_OUT_ARGS LV1_5_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_6_IN_7_OUT_ARGS LV1_6_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_7_IN_7_OUT_ARGS LV1_7_IN_ARGS, LV1_7_OUT_ARGS
+/*
+ * This LV1_CALL() macro is for use by callers.  It expands into an
+ * inline call wrapper and an underscored HV call declaration.  The
+ * wrapper can be used to instrument the lv1 call interface.  The
+ * file lv1call.S defines its own LV1_CALL() macro to expand into
+ * the actual underscored call definition.
+ */
+#if !defined(LV1_CALL)
+#define LV1_CALL(name, in, out, num)                               \
+  extern s64 _lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL);      \
+  static inline int lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL) \
+    {return _lv1_##name(LV1_##in##_IN_##out##_OUT_ARGS);}
+#endif
+#endif /* !defined(__ASSEMBLY__) */
+/* lv1 call table */
+LV1_CALL(allocate_memory,                               4, 2,   0 )
+LV1_CALL(write_htab_entry,                              4, 0,   1 )
+LV1_CALL(construct_virtual_address_space,               3, 2,   2 )
+LV1_CALL(invalidate_htab_entries,                       5, 0,   3 )
+LV1_CALL(get_virtual_address_space_id_of_ppe,           1, 1,   4 )
+LV1_CALL(query_logical_partition_address_region_info,   1, 5,   6 )
+LV1_CALL(select_virtual_address_space,                  1, 0,   7 )
+LV1_CALL(pause,                                         1, 0,   9 )
+LV1_CALL(destruct_virtual_address_space,                1, 0,  10 )
+LV1_CALL(configure_irq_state_bitmap,                    3, 0,  11 )
+LV1_CALL(connect_irq_plug_ext,                          5, 0,  12 )
+LV1_CALL(release_memory,                                1, 0,  13 )
+LV1_CALL(disconnect_irq_plug_ext,                       3, 0,  17 )
+LV1_CALL(construct_event_receive_port,                  0, 1,  18 )
+LV1_CALL(destruct_event_receive_port,                   1, 0,  19 )
+LV1_CALL(send_event_locally,                            1, 0,  24 )
+LV1_CALL(end_of_interrupt,                              1, 0,  27 )
+LV1_CALL(connect_irq_plug,                              2, 0,  28 )
+LV1_CALL(disconnect_irq_plug,                           1, 0,  29 )
+LV1_CALL(end_of_interrupt_ext,                          3, 0,  30 )
+LV1_CALL(did_update_interrupt_mask,                     2, 0,  31 )
+LV1_CALL(shutdown_logical_partition,                    1, 0,  44 )
+LV1_CALL(destruct_logical_spe,                          1, 0,  54 )
+LV1_CALL(construct_logical_spe,                         7, 6,  57 )
+LV1_CALL(set_spe_interrupt_mask,                        3, 0,  61 )
+LV1_CALL(set_spe_transition_notifier,                   3, 0,  64 )
+LV1_CALL(disable_logical_spe,                           2, 0,  65 )
+LV1_CALL(clear_spe_interrupt_status,                    4, 0,  66 )
+LV1_CALL(get_spe_interrupt_status,                      2, 1,  67 )
+LV1_CALL(get_logical_ppe_id,                            0, 1,  69 )
+LV1_CALL(set_interrupt_mask,                            5, 0,  73 )
+LV1_CALL(get_logical_partition_id,                      0, 1,  74 )
+LV1_CALL(configure_execution_time_variable,             1, 0,  77 )
+LV1_CALL(get_spe_irq_outlet,                            2, 1,  78 )
+LV1_CALL(set_spe_privilege_state_area_1_register,       3, 0,  79 )
+LV1_CALL(create_repository_node,                        6, 0,  90 )
+LV1_CALL(get_repository_node_value,                     5, 2,  91 )
+LV1_CALL(modify_repository_node_value,                  6, 0,  92 )
+LV1_CALL(remove_repository_node,                        4, 0,  93 )
+LV1_CALL(read_htab_entries,                             2, 5,  95 )
+LV1_CALL(set_dabr,                                      2, 0,  96 )
+LV1_CALL(get_total_execution_time,                      2, 1, 103 )
+LV1_CALL(construct_io_irq_outlet,                       1, 1, 120 )
+LV1_CALL(destruct_io_irq_outlet,                        1, 0, 121 )
+LV1_CALL(map_htab,                                      1, 1, 122 )
+LV1_CALL(unmap_htab,                                    1, 0, 123 )
+LV1_CALL(get_version_info,                              0, 1, 127 )
+LV1_CALL(insert_htab_entry,                             6, 3, 158 )
+LV1_CALL(read_virtual_uart,                             3, 1, 162 )
+LV1_CALL(write_virtual_uart,                            3, 1, 163 )
+LV1_CALL(set_virtual_uart_param,                        3, 0, 164 )
+LV1_CALL(get_virtual_uart_param,                        2, 1, 165 )
+LV1_CALL(configure_virtual_uart_irq,                    1, 1, 166 )
+LV1_CALL(open_device,                                   3, 0, 170 )
+LV1_CALL(close_device,                                  2, 0, 171 )
+LV1_CALL(map_device_mmio_region,                        5, 1, 172 )
+LV1_CALL(unmap_device_mmio_region,                      3, 0, 173 )
+LV1_CALL(allocate_device_dma_region,                    5, 1, 174 )
+LV1_CALL(free_device_dma_region,                        3, 0, 175 )
+LV1_CALL(map_device_dma_region,                         6, 0, 176 )
+LV1_CALL(unmap_device_dma_region,                       4, 0, 177 )
+LV1_CALL(net_add_multicast_address,                     4, 0, 185 )
+LV1_CALL(net_remove_multicast_address,                  4, 0, 186 )
+LV1_CALL(net_start_tx_dma,                              4, 0, 187 )
+LV1_CALL(net_stop_tx_dma,                               3, 0, 188 )
+LV1_CALL(net_start_rx_dma,                              4, 0, 189 )
+LV1_CALL(net_stop_rx_dma,                               3, 0, 190 )
+LV1_CALL(net_set_interrupt_status_indicator,            4, 0, 191 )
+LV1_CALL(net_set_interrupt_mask,                        4, 0, 193 )
+LV1_CALL(net_control,                                   6, 2, 194 )
+LV1_CALL(connect_interrupt_event_receive_port,          4, 0, 197 )
+LV1_CALL(disconnect_interrupt_event_receive_port,       4, 0, 198 )
+LV1_CALL(get_spe_all_interrupt_statuses,                1, 1, 199 )
+LV1_CALL(deconfigure_virtual_uart_irq,                  0, 0, 202 )
+LV1_CALL(enable_logical_spe,                            2, 0, 207 )
+LV1_CALL(gpu_open,                                      1, 0, 210 )
+LV1_CALL(gpu_close,                                     0, 0, 211 )
+LV1_CALL(gpu_device_map,                                1, 2, 212 )
+LV1_CALL(gpu_device_unmap,                              1, 0, 213 )
+LV1_CALL(gpu_memory_allocate,                           5, 2, 214 )
+LV1_CALL(gpu_memory_free,                               1, 0, 216 )
+LV1_CALL(gpu_context_allocate,                          2, 5, 217 )
+LV1_CALL(gpu_context_free,                              1, 0, 218 )
+LV1_CALL(gpu_context_iomap,                             5, 0, 221 )
+LV1_CALL(gpu_context_attribute,                         6, 0, 225 )
+LV1_CALL(gpu_context_intr,                              1, 1, 227 )
+LV1_CALL(gpu_attribute,                                 5, 0, 228 )
+LV1_CALL(get_rtc,                                       0, 2, 232 )
+LV1_CALL(set_ppe_periodic_tracer_frequency,             1, 0, 240 )
+LV1_CALL(start_ppe_periodic_tracer,                     5, 0, 241 )
+LV1_CALL(stop_ppe_periodic_tracer,                      1, 1, 242 )
+LV1_CALL(storage_read,                                  6, 1, 245 )
+LV1_CALL(storage_write,                                 6, 1, 246 )
+LV1_CALL(storage_send_device_command,                   6, 1, 248 )
+LV1_CALL(storage_get_async_status,                      1, 2, 249 )
+LV1_CALL(storage_check_async_status,                    2, 1, 254 )
+LV1_CALL(panic,                                         1, 0, 255 )
+LV1_CALL(construct_lpm,                                 6, 3, 140 )
+LV1_CALL(destruct_lpm,                                  1, 0, 141 )
+LV1_CALL(start_lpm,                                     1, 0, 142 )
+LV1_CALL(stop_lpm,                                      1, 1, 143 )
+LV1_CALL(copy_lpm_trace_buffer,                         3, 1, 144 )
+LV1_CALL(add_lpm_event_bookmark,                        5, 0, 145 )
+LV1_CALL(delete_lpm_event_bookmark,                     3, 0, 146 )
+LV1_CALL(set_lpm_interrupt_mask,                        3, 1, 147 )
+LV1_CALL(get_lpm_interrupt_status,                      1, 1, 148 )
+LV1_CALL(set_lpm_general_control,                       5, 2, 149 )
+LV1_CALL(set_lpm_interval,                              3, 1, 150 )
+LV1_CALL(set_lpm_trigger_control,                       3, 1, 151 )
+LV1_CALL(set_lpm_counter_control,                       4, 1, 152 )
+LV1_CALL(set_lpm_group_control,                         3, 1, 153 )
+LV1_CALL(set_lpm_debug_bus_control,                     3, 1, 154 )
+LV1_CALL(set_lpm_counter,                               5, 2, 155 )
+LV1_CALL(set_lpm_signal,                                7, 0, 156 )
+LV1_CALL(set_lpm_spr_trigger,                           2, 0, 157 )
+#endif
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index dac90dc341cb..1b04e5723548 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -26,6 +26,7 @@ struct device_node;
 struct iommu_table;
 struct rtc_time;
 struct file;
+struct pci_controller;
 #ifdef CONFIG_KEXEC
 struct kimage;
 #endif
@@ -84,9 +85,12 @@ struct machdep_calls {
        unsigned long   (*tce_get)(struct iommu_table *tbl,
                                    long index);
        void            (*tce_flush)(struct iommu_table *tbl);
-        void            (*iommu_dev_setup)(struct pci_dev *dev);
+        void            (*pci_dma_dev_setup)(struct pci_dev *dev);
-        void            (*iommu_bus_setup)(struct pci_bus *bus);
+        void            (*pci_dma_bus_setup)(struct pci_bus *bus);
-        void            (*irq_bus_setup)(struct pci_bus *bus);
+        void __iomem *  (*ioremap)(phys_addr_t addr, unsigned long size,
+                                   unsigned long flags);
+        void            (*iounmap)(volatile void __iomem *token);
 #endif /* CONFIG_PPC64 */
        int             (*probe)(void);
@@ -106,6 +110,10 @@ struct machdep_calls {
        /* Called after scanning the bus, before allocating resources */
        void            (*pcibios_fixup)(void);
        int             (*pci_probe_mode)(struct pci_bus *);
+        void            (*pci_irq_fixup)(struct pci_dev *dev);
+        /* To setup PHBs when using automatic OF platform driver for PCI */
+        int             (*pci_setup_phb)(struct pci_controller *host);
        void            (*restart)(char *cmd);
        void            (*power_off)(void);
@@ -199,10 +207,6 @@ struct machdep_calls {
         * Returns 0 to allow assignment/enabling of the device. */
        int  (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
-        /* For interrupt routing */
-        unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
-        int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
        /* Called in indirect_* to avoid touching devices */
        int (*pci_exclude_device)(unsigned char, unsigned char);
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index c3fc7a28e3cd..41c8c9c5a254 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -248,21 +248,6 @@ extern void hpte_init_native(void);
 extern void hpte_init_lpar(void);
 extern void hpte_init_iSeries(void);
-extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
-                                     unsigned long va, unsigned long prpn,
-                                     unsigned long rflags,
-                                     unsigned long vflags, int psize);
-extern long native_hpte_insert(unsigned long hpte_group,
-                               unsigned long va, unsigned long prpn,
-                               unsigned long rflags,
-                               unsigned long vflags, int psize);
-extern long iSeries_hpte_insert(unsigned long hpte_group,
-                                unsigned long va, unsigned long prpn,
-                                unsigned long rflags,
-                                unsigned long vflags, int psize);
 extern void stabs_alloc(void);
 extern void slb_initialize(void);
 extern void slb_flush_and_rebolt(void);
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
new file mode 100644
index 000000000000..4a28a850998c
--- /dev/null
+++ b/include/asm-powerpc/mpc52xx.h
@@ -0,0 +1,254 @@
+/*
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+#endif /* __ASSEMBLY__ */
+/* ======================================================================== */
+/* Structures mapping of some unit register set                             */
+/* ======================================================================== */
+#ifndef __ASSEMBLY__
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+        u32 mbar;               /* MMAP_CTRL + 0x00 */
+        u32 cs0_start;          /* MMAP_CTRL + 0x04 */
+        u32 cs0_stop;           /* MMAP_CTRL + 0x08 */
+        u32 cs1_start;          /* MMAP_CTRL + 0x0c */
+        u32 cs1_stop;           /* MMAP_CTRL + 0x10 */
+        u32 cs2_start;          /* MMAP_CTRL + 0x14 */
+        u32 cs2_stop;           /* MMAP_CTRL + 0x18 */
+        u32 cs3_start;          /* MMAP_CTRL + 0x1c */
+        u32 cs3_stop;           /* MMAP_CTRL + 0x20 */
+        u32 cs4_start;          /* MMAP_CTRL + 0x24 */
+        u32 cs4_stop;           /* MMAP_CTRL + 0x28 */
+        u32 cs5_start;          /* MMAP_CTRL + 0x2c */
+        u32 cs5_stop;           /* MMAP_CTRL + 0x30 */
+        u32 sdram0;             /* MMAP_CTRL + 0x34 */
+        u32 sdram1;             /* MMAP_CTRL + 0X38 */
+        u32 reserved[4];        /* MMAP_CTRL + 0x3c .. 0x48 */
+        u32 boot_start;         /* MMAP_CTRL + 0x4c */
+        u32 boot_stop;          /* MMAP_CTRL + 0x50 */
+        u32 ipbi_ws_ctrl;       /* MMAP_CTRL + 0x54 */
+        u32 cs6_start;          /* MMAP_CTRL + 0x58 */
+        u32 cs6_stop;           /* MMAP_CTRL + 0x5c */
+        u32 cs7_start;          /* MMAP_CTRL + 0x60 */
+        u32 cs7_stop;           /* MMAP_CTRL + 0x64 */
+};
+/* SDRAM control */
+struct mpc52xx_sdram {
+        u32 mode;               /* SDRAM + 0x00 */
+        u32 ctrl;               /* SDRAM + 0x04 */
+        u32 config1;            /* SDRAM + 0x08 */
+        u32 config2;            /* SDRAM + 0x0c */
+};
+/* SDMA */
+struct mpc52xx_sdma {
+        u32 taskBar;            /* SDMA + 0x00 */
+        u32 currentPointer;     /* SDMA + 0x04 */
+        u32 endPointer;         /* SDMA + 0x08 */
+        u32 variablePointer;    /* SDMA + 0x0c */
+        u8 IntVect1;            /* SDMA + 0x10 */
+        u8 IntVect2;            /* SDMA + 0x11 */
+        u16 PtdCntrl;           /* SDMA + 0x12 */
+        u32 IntPend;            /* SDMA + 0x14 */
+        u32 IntMask;            /* SDMA + 0x18 */
+        u16 tcr[16];            /* SDMA + 0x1c .. 0x3a */
+        u8 ipr[32];             /* SDMA + 0x3c .. 0x5b */
+        u32 cReqSelect;         /* SDMA + 0x5c */
+        u32 task_size0;         /* SDMA + 0x60 */
+        u32 task_size1;         /* SDMA + 0x64 */
+        u32 MDEDebug;           /* SDMA + 0x68 */
+        u32 ADSDebug;           /* SDMA + 0x6c */
+        u32 Value1;             /* SDMA + 0x70 */
+        u32 Value2;             /* SDMA + 0x74 */
+        u32 Control;            /* SDMA + 0x78 */
+        u32 Status;             /* SDMA + 0x7c */
+        u32 PTDDebug;           /* SDMA + 0x80 */
+};
+/* GPT */
+struct mpc52xx_gpt {
+        u32 mode;               /* GPTx + 0x00 */
+        u32 count;              /* GPTx + 0x04 */
+        u32 pwm;                /* GPTx + 0x08 */
+        u32 status;             /* GPTx + 0X0c */
+};
+/* GPIO */
+struct mpc52xx_gpio {
+        u32 port_config;        /* GPIO + 0x00 */
+        u32 simple_gpioe;       /* GPIO + 0x04 */
+        u32 simple_ode;         /* GPIO + 0x08 */
+        u32 simple_ddr;         /* GPIO + 0x0c */
+        u32 simple_dvo;         /* GPIO + 0x10 */
+        u32 simple_ival;        /* GPIO + 0x14 */
+        u8 outo_gpioe;          /* GPIO + 0x18 */
+        u8 reserved1[3];        /* GPIO + 0x19 */
+        u8 outo_dvo;            /* GPIO + 0x1c */
+        u8 reserved2[3];        /* GPIO + 0x1d */
+        u8 sint_gpioe;          /* GPIO + 0x20 */
+        u8 reserved3[3];        /* GPIO + 0x21 */
+        u8 sint_ode;            /* GPIO + 0x24 */
+        u8 reserved4[3];        /* GPIO + 0x25 */
+        u8 sint_ddr;            /* GPIO + 0x28 */
+        u8 reserved5[3];        /* GPIO + 0x29 */
+        u8 sint_dvo;            /* GPIO + 0x2c */
+        u8 reserved6[3];        /* GPIO + 0x2d */
+        u8 sint_inten;          /* GPIO + 0x30 */
+        u8 reserved7[3];        /* GPIO + 0x31 */
+        u16 sint_itype;         /* GPIO + 0x34 */
+        u16 reserved8;          /* GPIO + 0x36 */
+        u8 gpio_control;        /* GPIO + 0x38 */
+        u8 reserved9[3];        /* GPIO + 0x39 */
+        u8 sint_istat;          /* GPIO + 0x3c */
+        u8 sint_ival;           /* GPIO + 0x3d */
+        u8 bus_errs;            /* GPIO + 0x3e */
+        u8 reserved10;          /* GPIO + 0x3f */
+};
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD    5
+#define MPC52xx_GPIO_PCI_DIS                    (1<<15)
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+        u8 wkup_gpioe;          /* GPIO_WKUP + 0x00 */
+        u8 reserved1[3];        /* GPIO_WKUP + 0x03 */
+        u8 wkup_ode;            /* GPIO_WKUP + 0x04 */
+        u8 reserved2[3];        /* GPIO_WKUP + 0x05 */
+        u8 wkup_ddr;            /* GPIO_WKUP + 0x08 */
+        u8 reserved3[3];        /* GPIO_WKUP + 0x09 */
+        u8 wkup_dvo;            /* GPIO_WKUP + 0x0C */
+        u8 reserved4[3];        /* GPIO_WKUP + 0x0D */
+        u8 wkup_inten;          /* GPIO_WKUP + 0x10 */
+        u8 reserved5[3];        /* GPIO_WKUP + 0x11 */
+        u8 wkup_iinten;         /* GPIO_WKUP + 0x14 */
+        u8 reserved6[3];        /* GPIO_WKUP + 0x15 */
+        u16 wkup_itype;         /* GPIO_WKUP + 0x18 */
+        u8 reserved7[2];        /* GPIO_WKUP + 0x1A */
+        u8 wkup_maste;          /* GPIO_WKUP + 0x1C */
+        u8 reserved8[3];        /* GPIO_WKUP + 0x1D */
+        u8 wkup_ival;           /* GPIO_WKUP + 0x20 */
+        u8 reserved9[3];        /* GPIO_WKUP + 0x21 */
+        u8 wkup_istat;          /* GPIO_WKUP + 0x24 */
+        u8 reserved10[3];       /* GPIO_WKUP + 0x25 */
+};
+/* XLB Bus control */
+struct mpc52xx_xlb {
+        u8 reserved[0x40];
+        u32 config;             /* XLB + 0x40 */
+        u32 version;            /* XLB + 0x44 */
+        u32 status;             /* XLB + 0x48 */
+        u32 int_enable;         /* XLB + 0x4c */
+        u32 addr_capture;       /* XLB + 0x50 */
+        u32 bus_sig_capture;    /* XLB + 0x54 */
+        u32 addr_timeout;       /* XLB + 0x58 */
+        u32 data_timeout;       /* XLB + 0x5c */
+        u32 bus_act_timeout;    /* XLB + 0x60 */
+        u32 master_pri_enable;  /* XLB + 0x64 */
+        u32 master_priority;    /* XLB + 0x68 */
+        u32 base_address;       /* XLB + 0x6c */
+        u32 snoop_window;       /* XLB + 0x70 */
+};
+#define MPC52xx_XLB_CFG_PLDIS           (1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP           (1 << 15)
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+        u32 jtag_id;            /* CDM + 0x00  reg0 read only */
+        u32 rstcfg;             /* CDM + 0x04  reg1 read only */
+        u32 breadcrumb;         /* CDM + 0x08  reg2 */
+        u8 mem_clk_sel;         /* CDM + 0x0c  reg3 byte0 */
+        u8 xlb_clk_sel;         /* CDM + 0x0d  reg3 byte1 read only */
+        u8 ipb_clk_sel;         /* CDM + 0x0e  reg3 byte2 */
+        u8 pci_clk_sel;         /* CDM + 0x0f  reg3 byte3 */
+        u8 ext_48mhz_en;        /* CDM + 0x10  reg4 byte0 */
+        u8 fd_enable;           /* CDM + 0x11  reg4 byte1 */
+        u16 fd_counters;        /* CDM + 0x12  reg4 byte2,3 */
+        u32 clk_enables;        /* CDM + 0x14  reg5 */
+        u8 osc_disable;         /* CDM + 0x18  reg6 byte0 */
+        u8 reserved0[3];        /* CDM + 0x19  reg6 byte1,2,3 */
+        u8 ccs_sleep_enable;    /* CDM + 0x1c  reg7 byte0 */
+        u8 osc_sleep_enable;    /* CDM + 0x1d  reg7 byte1 */
+        u8 reserved1;           /* CDM + 0x1e  reg7 byte2 */
+        u8 ccs_qreq_test;       /* CDM + 0x1f  reg7 byte3 */
+        u8 soft_reset;          /* CDM + 0x20  u8 byte0 */
+        u8 no_ckstp;            /* CDM + 0x21  u8 byte0 */
+        u8 reserved2[2];        /* CDM + 0x22  u8 byte1,2,3 */
+        u8 pll_lock;            /* CDM + 0x24  reg9 byte0 */
+        u8 pll_looselock;       /* CDM + 0x25  reg9 byte1 */
+        u8 pll_sm_lockwin;      /* CDM + 0x26  reg9 byte2 */
+        u8 reserved3;           /* CDM + 0x27  reg9 byte3 */
+        u16 reserved4;          /* CDM + 0x28  reg10 byte0,1 */
+        u16 mclken_div_psc1;    /* CDM + 0x2a  reg10 byte2,3 */
+        u16 reserved5;          /* CDM + 0x2c  reg11 byte0,1 */
+        u16 mclken_div_psc2;    /* CDM + 0x2e  reg11 byte2,3 */
+        u16 reserved6;          /* CDM + 0x30  reg12 byte0,1 */
+        u16 mclken_div_psc3;    /* CDM + 0x32  reg12 byte2,3 */
+        u16 reserved7;          /* CDM + 0x34  reg13 byte0,1 */
+        u16 mclken_div_psc6;    /* CDM + 0x36  reg13 byte2,3 */
+};
+#endif /* __ASSEMBLY__ */
+/* ========================================================================= */
+/* Prototypes for MPC52xx sysdev                                             */
+/* ========================================================================= */
+#ifndef __ASSEMBLY__
+extern void __iomem * mpc52xx_find_and_map(const char *);
+extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
+extern void mpc52xx_setup_cpu(void);
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_POWERPC_MPC52xx_H__ */
diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/mpc85xx.h
index ccdb8a21138f..54142997a584 100644
--- a/include/asm-powerpc/mpc85xx.h
+++ b/include/asm-powerpc/mpc85xx.h
@@ -31,14 +31,6 @@
 #include <platforms/85xx/mpc85xx_cds.h>
 #endif
-#define _IO_BASE        isa_io_base
-#define _ISA_MEM_BASE   isa_mem_base
-#ifdef CONFIG_PCI
-#define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define PCI_DRAM_OFFSET 0
-#endif
 /* Let modules/drivers get at CCSRBAR */
 extern phys_addr_t get_ccsrbar(void);
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index ef0a5458d2b2..b71e7b32a555 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -3,6 +3,7 @@
 #ifdef __KERNEL__
 #include <linux/irq.h>
+#include <asm/dcr.h>
 /*
 * Global registers
@@ -225,6 +226,23 @@ struct mpic_irq_fixup
 #endif /* CONFIG_MPIC_BROKEN_U3 */
+enum mpic_reg_type {
+        mpic_access_mmio_le,
+        mpic_access_mmio_be,
+#ifdef CONFIG_PPC_DCR
+        mpic_access_dcr
+#endif
+};
+struct mpic_reg_bank {
+        u32 __iomem     *base;
+#ifdef CONFIG_PPC_DCR
+        dcr_host_t      dhost;
+        unsigned int    dbase;
+        unsigned int    doff;
+#endif /* CONFIG_PPC_DCR */
+};
 /* The instance data of a given MPIC */
 struct mpic
 {
@@ -264,11 +282,18 @@ struct mpic
        spinlock_t              fixup_lock;
 #endif
+        /* Register access method */
+        enum mpic_reg_type      reg_type;
        /* The various ioremap'ed bases */
-        volatile u32 __iomem    *gregs;
+        struct mpic_reg_bank    gregs;
-        volatile u32 __iomem    *tmregs;
+        struct mpic_reg_bank    tmregs;
-        volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
+        struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
-        volatile u32 __iomem    *isus[MPIC_MAX_ISU];
+        struct mpic_reg_bank    isus[MPIC_MAX_ISU];
+#ifdef CONFIG_PPC_DCR
+        unsigned int            dcr_base;
+#endif
 #ifdef CONFIG_MPIC_WEIRD
        /* Pointer to HW info array */
@@ -305,6 +330,8 @@ struct mpic
 #define MPIC_SPV_EOI                    0x00000020
 /* No passthrough disable */
 #define MPIC_NO_PTHROU_DIS              0x00000040
+/* DCR based MPIC */
+#define MPIC_USES_DCR                   0x00000080
 /* MPIC HW modification ID */
 #define MPIC_REGSET_MASK                0xf0000000
@@ -337,7 +364,7 @@ struct mpic
 * that is senses[0] correspond to linux irq "irq_offset".
 */
 extern struct mpic *mpic_alloc(struct device_node *node,
-                               unsigned long phys_addr,
+                               phys_addr_t phys_addr,
                               unsigned int flags,
                               unsigned int isu_size,
                               unsigned int irq_count,
@@ -350,7 +377,7 @@ extern struct mpic *mpic_alloc(struct device_node *node,
 * @phys_addr:  physical address of the ISU
 */
 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
-                            unsigned long phys_addr);
+                            phys_addr_t phys_addr);
 /* Set default sense codes
 *
diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h
index c5c0b0b3cd52..a889b2005bf5 100644
--- a/include/asm-powerpc/of_device.h
+++ b/include/asm-powerpc/of_device.h
@@ -6,12 +6,6 @@
 #include <linux/mod_devicetable.h>
 #include <asm/prom.h>
-/*
- * The of_platform_bus_type is a bus type used by drivers that do not
- * attach to a macio or similar bus but still use OF probing
- * mechanism
- */
-extern struct bus_type of_platform_bus_type;
 /*
 * The of_device is a kind of "base class" that is a superset of
@@ -20,46 +14,22 @@ extern struct bus_type of_platform_bus_type;
 */
 struct of_device
 {
-        struct device_node      *node;          /* OF device node */
+        struct device_node      *node;          /* to be obsoleted */
        u64                     dma_mask;       /* DMA mask */
        struct device           dev;            /* Generic device interface */
 };
 #define to_of_device(d) container_of(d, struct of_device, dev)
+extern const struct of_device_id *of_match_node(
+        const struct of_device_id *matches, const struct device_node *node);
 extern const struct of_device_id *of_match_device(
        const struct of_device_id *matches, const struct of_device *dev);
 extern struct of_device *of_dev_get(struct of_device *dev);
 extern void of_dev_put(struct of_device *dev);
-/*
- * An of_platform_driver driver is attached to a basic of_device on
- * the "platform bus" (of_platform_bus_type)
- */
-struct of_platform_driver
-{
-        char                    *name;
-        struct of_device_id     *match_table;
-        struct module           *owner;
-        int     (*probe)(struct of_device* dev, const struct of_device_id *match);
-        int     (*remove)(struct of_device* dev);
-        int     (*suspend)(struct of_device* dev, pm_message_t state);
-        int     (*resume)(struct of_device* dev);
-        int     (*shutdown)(struct of_device* dev);
-        struct device_driver    driver;
-};
-#define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver)
-extern int of_register_driver(struct of_platform_driver *drv);
-extern void of_unregister_driver(struct of_platform_driver *drv);
 extern int of_device_register(struct of_device *ofdev);
 extern void of_device_unregister(struct of_device *ofdev);
-extern struct of_device *of_platform_device_create(struct device_node *np,
-                                                   const char *bus_id,
-                                                   struct device *parent);
 extern void of_release_dev(struct device *dev);
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/of_platform.h b/include/asm-powerpc/of_platform.h
new file mode 100644
index 000000000000..217eafb167e9
--- /dev/null
+++ b/include/asm-powerpc/of_platform.h
@@ -0,0 +1,60 @@
+/*
+ *    Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                       <benh@kernel.crashing.org>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *
+ */
+#include <asm/of_device.h>
+/*
+ * The of_platform_bus_type is a bus type used by drivers that do not
+ * attach to a macio or similar bus but still use OF probing
+ * mechanism
+ */
+extern struct bus_type of_platform_bus_type;
+/*
+ * An of_platform_driver driver is attached to a basic of_device on
+ * the "platform bus" (of_platform_bus_type)
+ */
+struct of_platform_driver
+{
+        char                    *name;
+        struct of_device_id     *match_table;
+        struct module           *owner;
+        int     (*probe)(struct of_device* dev,
+                         const struct of_device_id *match);
+        int     (*remove)(struct of_device* dev);
+        int     (*suspend)(struct of_device* dev, pm_message_t state);
+        int     (*resume)(struct of_device* dev);
+        int     (*shutdown)(struct of_device* dev);
+        struct device_driver    driver;
+};
+#define to_of_platform_driver(drv) \
+        container_of(drv,struct of_platform_driver, driver)
+/* Platform drivers register/unregister */
+extern int of_register_platform_driver(struct of_platform_driver *drv);
+extern void of_unregister_platform_driver(struct of_platform_driver *drv);
+/* Platform devices and busses creation */
+extern struct of_device *of_platform_device_create(struct device_node *np,
+                                                   const char *bus_id,
+                                                   struct device *parent);
+/* pseudo "matches" value to not do deep probe */
+#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
+extern int of_platform_bus_probe(struct device_node *root,
+                                 struct of_device_id *matches,
+                                 struct device *parent);
+extern struct of_device *of_find_device_by_node(struct device_node *np);
+extern struct of_device *of_find_device_by_phandle(phandle ph);
diff --git a/include/asm-powerpc/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h
index 07a10e590c1d..71043bf3641f 100644
--- a/include/asm-powerpc/oprofile_impl.h
+++ b/include/asm-powerpc/oprofile_impl.h
@@ -44,7 +44,9 @@ struct op_powerpc_model {
                           int num_counters);
        void (*cpu_setup) (struct op_counter_config *);
        void (*start) (struct op_counter_config *);
+        void (*global_start) (struct op_counter_config *);
        void (*stop) (void);
+        void (*global_stop) (void);
        void (*handle_interrupt) (struct pt_regs *,
                                  struct op_counter_config *);
        int num_counters;
@@ -54,6 +56,7 @@ extern struct op_powerpc_model op_model_fsl_booke;
 extern struct op_powerpc_model op_model_rs64;
 extern struct op_powerpc_model op_model_power4;
 extern struct op_powerpc_model op_model_7450;
+extern struct op_powerpc_model op_model_cell;
 #ifndef CONFIG_FSL_BOOKE
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
index 0a4e5c93e8e6..0d3adc09c847 100644
--- a/include/asm-powerpc/paca.h
+++ b/include/asm-powerpc/paca.h
@@ -93,7 +93,8 @@ struct paca_struct {
        u64 stab_rr;                    /* stab/slb round-robin counter */
        u64 saved_r1;                   /* r1 save for RTAS calls */
        u64 saved_msr;                  /* MSR saved here by enter_rtas */
-        u8 proc_enabled;                /* irq soft-enable flag */
+        u8 soft_enabled;                /* irq soft-enable flag */
+        u8 hard_enabled;                /* set if irqs are enabled in MSR */
        u8 io_sync;                     /* writel() needs spin_unlock sync */
        /* Stuff for accurate time accounting */
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index 86ee46b09b8a..7bb7f9009806 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -25,6 +25,7 @@ struct pci_controller {
        int node;
        void *arch_data;
        struct list_head list_node;
+        struct device *parent;
        int first_busno;
        int last_busno;
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index 721c97f09b20..16f13319c769 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -70,15 +70,15 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 */
 #define PCI_DISABLE_MWI
-extern struct dma_mapping_ops pci_dma_ops;
+extern struct dma_mapping_ops *pci_dma_ops;
 /* For DAC DMA, we currently don't support it by default, but
 * we let 64-bit platforms override this.
 */
 static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
 {
-        if (pci_dma_ops.dac_dma_supported)
+        if (pci_dma_ops && pci_dma_ops->dac_dma_supported)
-                return pci_dma_ops.dac_dma_supported(&hwdev->dev, mask);
+                return pci_dma_ops->dac_dma_supported(&hwdev->dev, mask);
        return 0;
 }
@@ -210,6 +210,8 @@ extern int remap_bus_range(struct pci_bus *bus);
 extern void pcibios_fixup_device_resources(struct pci_dev *dev,
                        struct pci_bus *bus);
+extern void pcibios_setup_new_device(struct pci_dev *dev);
 extern void pcibios_claim_one_bus(struct pci_bus *b);
 extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
@@ -232,12 +234,10 @@ extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
                                         unsigned long size,
                                         pgprot_t prot);
-#if defined(CONFIG_PPC_MULTIPLATFORM) || defined(CONFIG_PPC32)
 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
 extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
                                 const struct resource *rsrc,
                                 resource_size_t *start, resource_size_t *end);
-#endif /* CONFIG_PPC_MULTIPLATFORM || CONFIG_PPC32 */
 #endif  /* __KERNEL__ */
 #endif /* __ASM_POWERPC_PCI_H */
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
index 1115756c79f9..ab6eddb518c7 100644
--- a/include/asm-powerpc/ppc-pci.h
+++ b/include/asm-powerpc/ppc-pci.h
@@ -36,18 +36,17 @@ typedef void *(*traverse_func)(struct device_node *me, void *data);
 void *traverse_pci_devices(struct device_node *start, traverse_func pre,
                void *data);
-void pci_devs_phb_init(void);
+extern void pci_devs_phb_init(void);
-void pci_devs_phb_init_dynamic(struct pci_controller *phb);
+extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
-int setup_phb(struct device_node *dev, struct pci_controller *phb);
+extern void scan_phb(struct pci_controller *hose);
-void __devinit scan_phb(struct pci_controller *hose);
 /* From rtas_pci.h */
-void init_pci_config_tokens (void);
+extern void init_pci_config_tokens (void);
-unsigned long get_phb_buid (struct device_node *);
+extern unsigned long get_phb_buid (struct device_node *);
+extern int rtas_setup_phb(struct pci_controller *phb);
 /* From pSeries_pci.h */
 extern void pSeries_final_fixup(void);
-extern void pSeries_irq_bus_setup(struct pci_bus *bus);
 extern unsigned long pci_probe_only;
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
index 6cb6fb19e57f..a26c32ee5527 100644
--- a/include/asm-powerpc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -53,10 +53,6 @@ extern unsigned char ucBoardRevMaj, ucBoardRevMin;
 #endif /* CONFIG_PPC_PREP */
-#ifndef CONFIG_PPC_MULTIPLATFORM
-#define _machine 0
-#endif /* CONFIG_PPC_MULTIPLATFORM */
 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
 /*
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index ec11d44eaeb5..0afee17f33b4 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -17,6 +17,7 @@
 */
 #include <linux/types.h>
 #include <linux/proc_fs.h>
+#include <linux/platform_device.h>
 #include <asm/atomic.h>
 /* Definitions used by the flattened device tree */
@@ -333,6 +334,20 @@ extern int of_irq_map_one(struct device_node *device, int index,
 struct pci_dev;
 extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
+static inline int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
+{
+        int irq = irq_of_parse_and_map(dev, index);
+        /* Only dereference the resource if both the
+         * resource and the irq are valid. */
+        if (r && irq != NO_IRQ) {
+                r->start = r->end = irq;
+                r->flags = IORESOURCE_IRQ;
+        }
+        return irq;
+}
 #endif /* __KERNEL__ */
 #endif /* _POWERPC_PROM_H */
diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h
new file mode 100644
index 000000000000..52a69ed0d90a
--- /dev/null
+++ b/include/asm-powerpc/ps3.h
@@ -0,0 +1,462 @@
+/*
+ *  PS3 platform declarations.
+ *
+ *  Copyright (C) 2006 Sony Computer Entertainment Inc.
+ *  Copyright 2006 Sony Corp.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#if !defined(_ASM_POWERPC_PS3_H)
+#define _ASM_POWERPC_PS3_H
+#include <linux/compiler.h> /* for __deprecated */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/device.h>
+/**
+ * struct ps3_device_id - HV bus device identifier from the system repository
+ * @bus_id: HV bus id, {1..} (zero invalid)
+ * @dev_id: HV device id, {0..}
+ */
+struct ps3_device_id {
+        unsigned int bus_id;
+        unsigned int dev_id;
+};
+/* dma routines */
+enum ps3_dma_page_size {
+        PS3_DMA_4K = 12U,
+        PS3_DMA_64K = 16U,
+        PS3_DMA_1M = 20U,
+        PS3_DMA_16M = 24U,
+};
+enum ps3_dma_region_type {
+        PS3_DMA_OTHER = 0,
+        PS3_DMA_INTERNAL = 2,
+};
+/**
+ * struct ps3_dma_region - A per device dma state variables structure
+ * @did: The HV device id.
+ * @page_size: The ioc pagesize.
+ * @region_type: The HV region type.
+ * @bus_addr: The 'translated' bus address of the region.
+ * @len: The length in bytes of the region.
+ * @chunk_list: Opaque variable used by the ioc page manager.
+ */
+struct ps3_dma_region {
+        struct ps3_device_id did;
+        enum ps3_dma_page_size page_size;
+        enum ps3_dma_region_type region_type;
+        unsigned long bus_addr;
+        unsigned long len;
+        struct {
+                spinlock_t lock;
+                struct list_head head;
+        } chunk_list;
+};
+/**
+ * struct ps3_dma_region_init - Helper to initialize structure variables
+ *
+ * Helper to properly initialize variables prior to calling
+ * ps3_system_bus_device_register.
+ */
+static inline void ps3_dma_region_init(struct ps3_dma_region *r,
+        const struct ps3_device_id* did, enum ps3_dma_page_size page_size,
+        enum ps3_dma_region_type region_type)
+{
+        r->did = *did;
+        r->page_size = page_size;
+        r->region_type = region_type;
+}
+int ps3_dma_region_create(struct ps3_dma_region *r);
+int ps3_dma_region_free(struct ps3_dma_region *r);
+int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr,
+        unsigned long len, unsigned long *bus_addr);
+int ps3_dma_unmap(struct ps3_dma_region *r, unsigned long bus_addr,
+        unsigned long len);
+/* mmio routines */
+enum ps3_mmio_page_size {
+        PS3_MMIO_4K = 12U,
+        PS3_MMIO_64K = 16U
+};
+/**
+ * struct ps3_mmio_region - a per device mmio state variables structure
+ *
+ * Current systems can be supported with a single region per device.
+ */
+struct ps3_mmio_region {
+        struct ps3_device_id did;
+        unsigned long bus_addr;
+        unsigned long len;
+        enum ps3_mmio_page_size page_size;
+        unsigned long lpar_addr;
+};
+/**
+ * struct ps3_mmio_region_init - Helper to initialize structure variables
+ *
+ * Helper to properly initialize variables prior to calling
+ * ps3_system_bus_device_register.
+ */
+static inline void ps3_mmio_region_init(struct ps3_mmio_region *r,
+        const struct ps3_device_id* did, unsigned long bus_addr,
+        unsigned long len, enum ps3_mmio_page_size page_size)
+{
+        r->did = *did;
+        r->bus_addr = bus_addr;
+        r->len = len;
+        r->page_size = page_size;
+}
+int ps3_mmio_region_create(struct ps3_mmio_region *r);
+int ps3_free_mmio_region(struct ps3_mmio_region *r);
+unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr);
+/* inrerrupt routines */
+int ps3_alloc_io_irq(unsigned int interrupt_id, unsigned int *virq);
+int ps3_free_io_irq(unsigned int virq);
+int ps3_alloc_event_irq(unsigned int *virq);
+int ps3_free_event_irq(unsigned int virq);
+int ps3_send_event_locally(unsigned int virq);
+int ps3_connect_event_irq(const struct ps3_device_id *did,
+        unsigned int interrupt_id, unsigned int *virq);
+int ps3_disconnect_event_irq(const struct ps3_device_id *did,
+        unsigned int interrupt_id, unsigned int virq);
+int ps3_alloc_vuart_irq(void* virt_addr_bmp, unsigned int *virq);
+int ps3_free_vuart_irq(unsigned int virq);
+int ps3_alloc_spe_irq(unsigned long spe_id, unsigned int class,
+        unsigned int *virq);
+int ps3_free_spe_irq(unsigned int virq);
+/* lv1 result codes */
+enum lv1_result {
+        LV1_SUCCESS                     = 0,
+        /* not used                       -1 */
+        LV1_RESOURCE_SHORTAGE           = -2,
+        LV1_NO_PRIVILEGE                = -3,
+        LV1_DENIED_BY_POLICY            = -4,
+        LV1_ACCESS_VIOLATION            = -5,
+        LV1_NO_ENTRY                    = -6,
+        LV1_DUPLICATE_ENTRY             = -7,
+        LV1_TYPE_MISMATCH               = -8,
+        LV1_BUSY                        = -9,
+        LV1_EMPTY                       = -10,
+        LV1_WRONG_STATE                 = -11,
+        /* not used                       -12 */
+        LV1_NO_MATCH                    = -13,
+        LV1_ALREADY_CONNECTED           = -14,
+        LV1_UNSUPPORTED_PARAMETER_VALUE = -15,
+        LV1_CONDITION_NOT_SATISFIED     = -16,
+        LV1_ILLEGAL_PARAMETER_VALUE     = -17,
+        LV1_BAD_OPTION                  = -18,
+        LV1_IMPLEMENTATION_LIMITATION   = -19,
+        LV1_NOT_IMPLEMENTED             = -20,
+        LV1_INVALID_CLASS_ID            = -21,
+        LV1_CONSTRAINT_NOT_SATISFIED    = -22,
+        LV1_ALIGNMENT_ERROR             = -23,
+        LV1_INTERNAL_ERROR              = -32768,
+};
+static inline const char* ps3_result(int result)
+{
+#if defined(DEBUG)
+        switch (result) {
+        case LV1_SUCCESS:
+                return "LV1_SUCCESS (0)";
+        case -1:
+                return "** unknown result ** (-1)";
+        case LV1_RESOURCE_SHORTAGE:
+                return "LV1_RESOURCE_SHORTAGE (-2)";
+        case LV1_NO_PRIVILEGE:
+                return "LV1_NO_PRIVILEGE (-3)";
+        case LV1_DENIED_BY_POLICY:
+                return "LV1_DENIED_BY_POLICY (-4)";
+        case LV1_ACCESS_VIOLATION:
+                return "LV1_ACCESS_VIOLATION (-5)";
+        case LV1_NO_ENTRY:
+                return "LV1_NO_ENTRY (-6)";
+        case LV1_DUPLICATE_ENTRY:
+                return "LV1_DUPLICATE_ENTRY (-7)";
+        case LV1_TYPE_MISMATCH:
+                return "LV1_TYPE_MISMATCH (-8)";
+        case LV1_BUSY:
+                return "LV1_BUSY (-9)";
+        case LV1_EMPTY:
+                return "LV1_EMPTY (-10)";
+        case LV1_WRONG_STATE:
+                return "LV1_WRONG_STATE (-11)";
+        case -12:
+                return "** unknown result ** (-12)";
+        case LV1_NO_MATCH:
+                return "LV1_NO_MATCH (-13)";
+        case LV1_ALREADY_CONNECTED:
+                return "LV1_ALREADY_CONNECTED (-14)";
+        case LV1_UNSUPPORTED_PARAMETER_VALUE:
+                return "LV1_UNSUPPORTED_PARAMETER_VALUE (-15)";
+        case LV1_CONDITION_NOT_SATISFIED:
+                return "LV1_CONDITION_NOT_SATISFIED (-16)";
+        case LV1_ILLEGAL_PARAMETER_VALUE:
+                return "LV1_ILLEGAL_PARAMETER_VALUE (-17)";
+        case LV1_BAD_OPTION:
+                return "LV1_BAD_OPTION (-18)";
+        case LV1_IMPLEMENTATION_LIMITATION:
+                return "LV1_IMPLEMENTATION_LIMITATION (-19)";
+        case LV1_NOT_IMPLEMENTED:
+                return "LV1_NOT_IMPLEMENTED (-20)";
+        case LV1_INVALID_CLASS_ID:
+                return "LV1_INVALID_CLASS_ID (-21)";
+        case LV1_CONSTRAINT_NOT_SATISFIED:
+                return "LV1_CONSTRAINT_NOT_SATISFIED (-22)";
+        case LV1_ALIGNMENT_ERROR:
+                return "LV1_ALIGNMENT_ERROR (-23)";
+        case LV1_INTERNAL_ERROR:
+                return "LV1_INTERNAL_ERROR (-32768)";
+        default:
+                BUG();
+                return "** unknown result **";
+        };
+#else
+        return "";
+#endif
+}
+/* repository bus info */
+enum ps3_bus_type {
+        PS3_BUS_TYPE_SB = 4,
+        PS3_BUS_TYPE_STORAGE = 5,
+};
+enum ps3_dev_type {
+        PS3_DEV_TYPE_SB_GELIC = 3,
+        PS3_DEV_TYPE_SB_USB = 4,
+        PS3_DEV_TYPE_SB_GPIO = 6,
+};
+int ps3_repository_read_bus_str(unsigned int bus_index, const char *bus_str,
+        u64 *value);
+int ps3_repository_read_bus_id(unsigned int bus_index, unsigned int *bus_id);
+int ps3_repository_read_bus_type(unsigned int bus_index,
+        enum ps3_bus_type *bus_type);
+int ps3_repository_read_bus_num_dev(unsigned int bus_index,
+        unsigned int *num_dev);
+/* repository bus device info */
+enum ps3_interrupt_type {
+        PS3_INTERRUPT_TYPE_EVENT_PORT = 2,
+        PS3_INTERRUPT_TYPE_SB_OHCI = 3,
+        PS3_INTERRUPT_TYPE_SB_EHCI = 4,
+        PS3_INTERRUPT_TYPE_OTHER = 5,
+};
+enum ps3_region_type {
+        PS3_REGION_TYPE_SB_OHCI = 3,
+        PS3_REGION_TYPE_SB_EHCI = 4,
+        PS3_REGION_TYPE_SB_GPIO = 5,
+};
+int ps3_repository_read_dev_str(unsigned int bus_index,
+        unsigned int dev_index, const char *dev_str, u64 *value);
+int ps3_repository_read_dev_id(unsigned int bus_index, unsigned int dev_index,
+        unsigned int *dev_id);
+int ps3_repository_read_dev_type(unsigned int bus_index,
+        unsigned int dev_index, enum ps3_dev_type *dev_type);
+int ps3_repository_read_dev_intr(unsigned int bus_index,
+        unsigned int dev_index, unsigned int intr_index,
+        enum ps3_interrupt_type *intr_type, unsigned int *interrupt_id);
+int ps3_repository_read_dev_reg_type(unsigned int bus_index,
+        unsigned int dev_index, unsigned int reg_index,
+        enum ps3_region_type *reg_type);
+int ps3_repository_read_dev_reg_addr(unsigned int bus_index,
+        unsigned int dev_index, unsigned int reg_index, u64 *bus_addr,
+        u64 *len);
+int ps3_repository_read_dev_reg(unsigned int bus_index,
+        unsigned int dev_index, unsigned int reg_index,
+        enum ps3_region_type *reg_type, u64 *bus_addr, u64 *len);
+/* repository bus enumerators */
+struct ps3_repository_device {
+        unsigned int bus_index;
+        unsigned int dev_index;
+        struct ps3_device_id did;
+};
+int ps3_repository_find_device(enum ps3_bus_type bus_type,
+        enum ps3_dev_type dev_type,
+        const struct ps3_repository_device *start_dev,
+        struct ps3_repository_device *dev);
+static inline int ps3_repository_find_first_device(
+        enum ps3_bus_type bus_type, enum ps3_dev_type dev_type,
+        struct ps3_repository_device *dev)
+{
+        return ps3_repository_find_device(bus_type, dev_type, NULL, dev);
+}
+int ps3_repository_find_interrupt(const struct ps3_repository_device *dev,
+        enum ps3_interrupt_type intr_type, unsigned int *interrupt_id);
+int ps3_repository_find_region(const struct ps3_repository_device *dev,
+        enum ps3_region_type reg_type, u64 *bus_addr, u64 *len);
+/* repository block device info */
+int ps3_repository_read_dev_port(unsigned int bus_index,
+        unsigned int dev_index, u64 *port);
+int ps3_repository_read_dev_blk_size(unsigned int bus_index,
+        unsigned int dev_index, u64 *blk_size);
+int ps3_repository_read_dev_num_blocks(unsigned int bus_index,
+        unsigned int dev_index, u64 *num_blocks);
+int ps3_repository_read_dev_num_regions(unsigned int bus_index,
+        unsigned int dev_index, unsigned int *num_regions);
+int ps3_repository_read_dev_region_id(unsigned int bus_index,
+        unsigned int dev_index, unsigned int region_index,
+        unsigned int *region_id);
+int ps3_repository_read_dev_region_size(unsigned int bus_index,
+        unsigned int dev_index, unsigned int region_index, u64 *region_size);
+int ps3_repository_read_dev_region_start(unsigned int bus_index,
+        unsigned int dev_index, unsigned int region_index, u64 *region_start);
+/* repository pu and memory info */
+int ps3_repository_read_num_pu(unsigned int *num_pu);
+int ps3_repository_read_ppe_id(unsigned int *pu_index, unsigned int *ppe_id);
+int ps3_repository_read_rm_base(unsigned int ppe_id, u64 *rm_base);
+int ps3_repository_read_rm_size(unsigned int ppe_id, u64 *rm_size);
+int ps3_repository_read_region_total(u64 *region_total);
+int ps3_repository_read_mm_info(u64 *rm_base, u64 *rm_size,
+        u64 *region_total);
+/* repository pme info */
+int ps3_repository_read_num_be(unsigned int *num_be);
+int ps3_repository_read_be_node_id(unsigned int be_index, u64 *node_id);
+int ps3_repository_read_tb_freq(u64 node_id, u64 *tb_freq);
+int ps3_repository_read_be_tb_freq(unsigned int be_index, u64 *tb_freq);
+/* repository 'Other OS' area */
+int ps3_repository_read_boot_dat_addr(u64 *lpar_addr);
+int ps3_repository_read_boot_dat_size(unsigned int *size);
+int ps3_repository_read_boot_dat_info(u64 *lpar_addr, unsigned int *size);
+/* repository spu info */
+/**
+ * enum spu_resource_type - Type of spu resource.
+ * @spu_resource_type_shared: Logical spu is shared with other partions.
+ * @spu_resource_type_exclusive: Logical spu is not shared with other partions.
+ *
+ * Returned by ps3_repository_read_spu_resource_id().
+ */
+enum ps3_spu_resource_type {
+        PS3_SPU_RESOURCE_TYPE_SHARED = 0,
+        PS3_SPU_RESOURCE_TYPE_EXCLUSIVE = 0x8000000000000000UL,
+};
+int ps3_repository_read_num_spu_reserved(unsigned int *num_spu_reserved);
+int ps3_repository_read_num_spu_resource_id(unsigned int *num_resource_id);
+int ps3_repository_read_spu_resource_id(unsigned int res_index,
+        enum ps3_spu_resource_type* resource_type, unsigned int *resource_id);
+/* system bus routines */
+enum ps3_match_id {
+        PS3_MATCH_ID_EHCI = 1,
+        PS3_MATCH_ID_OHCI,
+        PS3_MATCH_ID_GELIC,
+        PS3_MATCH_ID_AV_SETTINGS,
+        PS3_MATCH_ID_SYSTEM_MANAGER,
+};
+/**
+ * struct ps3_system_bus_device - a device on the system bus
+ */
+struct ps3_system_bus_device {
+        enum ps3_match_id match_id;
+        struct ps3_device_id did;
+        unsigned int interrupt_id;
+/*      struct iommu_table *iommu_table; -- waiting for Ben's cleanups */
+        struct ps3_dma_region *d_region;
+        struct ps3_mmio_region *m_region;
+        struct device core;
+};
+/**
+ * struct ps3_system_bus_driver - a driver for a device on the system bus
+ */
+struct ps3_system_bus_driver {
+        enum ps3_match_id match_id;
+        struct device_driver core;
+        int (*probe)(struct ps3_system_bus_device *);
+        int (*remove)(struct ps3_system_bus_device *);
+/*      int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */
+/*      int (*resume)(struct ps3_system_bus_device *); */
+};
+int ps3_system_bus_device_register(struct ps3_system_bus_device *dev);
+int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv);
+void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv);
+static inline struct ps3_system_bus_driver *to_ps3_system_bus_driver(
+        struct device_driver *_drv)
+{
+        return container_of(_drv, struct ps3_system_bus_driver, core);
+}
+static inline struct ps3_system_bus_device *to_ps3_system_bus_device(
+        struct device *_dev)
+{
+        return container_of(_dev, struct ps3_system_bus_device, core);
+}
+/**
+ * ps3_system_bus_set_drvdata -
+ * @dev: device structure
+ * @data: Data to set
+ */
+static inline void ps3_system_bus_set_driver_data(
+        struct ps3_system_bus_device *dev, void *data)
+{
+        dev->core.driver_data = data;
+}
+static inline void *ps3_system_bus_get_driver_data(
+        struct ps3_system_bus_device *dev)
+{
+        return dev->core.driver_data;
+}
+/* These two need global scope for get_dma_ops(). */
+extern struct bus_type ps3_system_bus_type;
+#endif
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
index d34f9e1f242c..5a0c136c0416 100644
--- a/include/asm-powerpc/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -54,8 +54,6 @@ struct rtas_args {
        rtas_arg_t *rets;     /* Pointer to return values in args[]. */
 };  
-extern struct rtas_args rtas_stop_self_args;
 struct rtas_t {
        unsigned long entry;            /* physical address pointer */
        unsigned long base;             /* physical address pointer */
diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h
index 38b1ea3b58fd..48ad807a0b8a 100644
--- a/include/asm-powerpc/sparsemem.h
+++ b/include/asm-powerpc/sparsemem.h
@@ -9,8 +9,14 @@
 * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
 */
 #define SECTION_SIZE_BITS       24
+#if defined(CONFIG_PS3_USE_LPAR_ADDR)
+#define MAX_PHYSADDR_BITS       47
+#define MAX_PHYSMEM_BITS        47
+#else
 #define MAX_PHYSADDR_BITS       44
 #define MAX_PHYSMEM_BITS        44
+#endif
 #ifdef CONFIG_MEMORY_HOTPLUG
 extern void create_section_mapping(unsigned long start, unsigned long end);
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index e73ea00efd8b..fdad4267b447 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -111,14 +111,12 @@ struct spu {
        u8 *local_store;
        unsigned long problem_phys;
        struct spu_problem __iomem *problem;
-        struct spu_priv1 __iomem *priv1;
        struct spu_priv2 __iomem *priv2;
        struct list_head list;
        struct list_head sched_list;
+        struct list_head full_list;
        int number;
-        int nid;
        unsigned int irqs[3];
-        u32 isrc;
        u32 node;
        u64 flags;
        u64 dar;
@@ -144,6 +142,7 @@ struct spu {
        char irq_c1[8];
        char irq_c2[8];
+        void* pdata; /* platform private data */
        struct sys_device sysdev;
 };
@@ -170,6 +169,13 @@ extern struct spufs_calls {
        struct module *owner;
 } spufs_calls;
+/* coredump calls implemented in spufs */
+struct spu_coredump_calls {
+        asmlinkage int (*arch_notes_size)(void);
+        asmlinkage void (*arch_write_notes)(struct file *file);
+        struct module *owner;
+};
 /* return status from spu_run, same as in libspe */
 #define SPE_EVENT_DMA_ALIGNMENT         0x0008  /*A DMA alignment error */
 #define SPE_EVENT_SPE_ERROR             0x0010  /*An illegal instruction error*/
@@ -182,8 +188,10 @@ extern struct spufs_calls {
 */
 #define SPU_CREATE_EVENTS_ENABLED       0x0001
 #define SPU_CREATE_GANG                 0x0002
+#define SPU_CREATE_NOSCHED              0x0004
+#define SPU_CREATE_ISOLATE              0x0008
-#define SPU_CREATE_FLAG_ALL             0x0003 /* mask of all valid flags */
+#define SPU_CREATE_FLAG_ALL             0x000f /* mask of all valid flags */
 #ifdef CONFIG_SPU_FS_MODULE
@@ -199,6 +207,15 @@ static inline void unregister_spu_syscalls(struct spufs_calls *calls)
 }
 #endif /* MODULE */
+int register_arch_coredump_calls(struct spu_coredump_calls *calls);
+void unregister_arch_coredump_calls(struct spu_coredump_calls *calls);
+int spu_add_sysdev_attr(struct sysdev_attribute *attr);
+void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
+int spu_add_sysdev_attr_group(struct attribute_group *attrs);
+void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
 /*
 * Notifier blocks:
@@ -277,6 +294,7 @@ struct spu_problem {
        u32 spu_runcntl_RW;                                     /* 0x401c */
 #define SPU_RUNCNTL_STOP        0L
 #define SPU_RUNCNTL_RUNNABLE    1L
+#define SPU_RUNCNTL_ISOLATE     2L
        u8  pad_0x4020_0x4024[0x4];                             /* 0x4020 */
        u32 spu_status_R;                                       /* 0x4024 */
 #define SPU_STOP_STATUS_SHIFT           16
@@ -289,8 +307,8 @@ struct spu_problem {
 #define SPU_STATUS_INVALID_INSTR        0x20
 #define SPU_STATUS_INVALID_CH           0x40
 #define SPU_STATUS_ISOLATED_STATE       0x80
-#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
+#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
-#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
+#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
        u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
        u32 spu_spe_R;                                          /* 0x402c */
        u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
index 964c2d38ccb7..bdbf906a767f 100644
--- a/include/asm-powerpc/spu_csa.h
+++ b/include/asm-powerpc/spu_csa.h
@@ -151,7 +151,6 @@ struct spu_priv1_collapsed {
        u64 mfc_fir_chkstp_enable_RW;
        u64 smf_sbi_signal_sel;
        u64 smf_ato_signal_sel;
-        u64 mfc_sdr_RW;
        u64 tlb_index_hint_RO;
        u64 tlb_index_W;
        u64 tlb_vpn_RW;
diff --git a/include/asm-powerpc/spu_info.h b/include/asm-powerpc/spu_info.h
new file mode 100644
index 000000000000..3545efbf9891
--- /dev/null
+++ b/include/asm-powerpc/spu_info.h
@@ -0,0 +1,54 @@
+/*
+ * SPU info structures
+ *
+ * (C) Copyright 2006 IBM Corp.
+ *
+ * Author: Dwayne Grant McConnell <decimal@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _SPU_INFO_H
+#define _SPU_INFO_H
+#ifdef __KERNEL__
+#include <asm/spu.h>
+#include <linux/types.h>
+#else
+struct mfc_cq_sr {
+        __u64 mfc_cq_data0_RW;
+        __u64 mfc_cq_data1_RW;
+        __u64 mfc_cq_data2_RW;
+        __u64 mfc_cq_data3_RW;
+};
+#endif /* __KERNEL__ */
+struct spu_dma_info {
+        __u64 dma_info_type;
+        __u64 dma_info_mask;
+        __u64 dma_info_status;
+        __u64 dma_info_stall_and_notify;
+        __u64 dma_info_atomic_command_status;
+        struct mfc_cq_sr dma_info_command_data[16];
+};
+struct spu_proxydma_info {
+        __u64 proxydma_info_type;
+        __u64 proxydma_info_mask;
+        __u64 proxydma_info_status;
+        struct mfc_cq_sr proxydma_info_command_data[8];
+};
+#endif
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
index 300c458b6d06..69dcb0c53884 100644
--- a/include/asm-powerpc/spu_priv1.h
+++ b/include/asm-powerpc/spu_priv1.h
@@ -21,12 +21,13 @@
 #define _SPU_PRIV1_H
 #if defined(__KERNEL__)
+#include <linux/types.h>
 struct spu;
 /* access to priv1 registers */
-struct spu_priv1_ops
+struct spu_priv1_ops {
-{
        void (*int_mask_and) (struct spu *spu, int class, u64 mask);
        void (*int_mask_or) (struct spu *spu, int class, u64 mask);
        void (*int_mask_set) (struct spu *spu, int class, u64 mask);
@@ -37,7 +38,7 @@ struct spu_priv1_ops
        u64 (*mfc_dar_get) (struct spu *spu);
        u64 (*mfc_dsisr_get) (struct spu *spu);
        void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
-        void (*mfc_sdr_set) (struct spu *spu, u64 sdr);
+        void (*mfc_sdr_setup) (struct spu *spu);
        void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
        u64 (*mfc_sr1_get) (struct spu *spu);
        void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
@@ -112,9 +113,9 @@ spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
 }
 static inline void
-spu_mfc_sdr_set (struct spu *spu, u64 sdr)
+spu_mfc_sdr_setup (struct spu *spu)
 {
-        spu_priv1_ops->mfc_sdr_set(spu, sdr);
+        spu_priv1_ops->mfc_sdr_setup(spu);
 }
 static inline void
@@ -171,12 +172,41 @@ spu_resource_allocation_enable_get (struct spu *spu)
        return spu_priv1_ops->resource_allocation_enable_get(spu);
 }
-/* The declarations folowing are put here for convenience
+/* spu management abstraction */
- * and only intended to be used by the platform setup code
- * for initializing spu_priv1_ops.
+struct spu_management_ops {
+        int (*enumerate_spus)(int (*fn)(void *data));
+        int (*create_spu)(struct spu *spu, void *data);
+        int (*destroy_spu)(struct spu *spu);
+};
+extern const struct spu_management_ops* spu_management_ops;
+static inline int
+spu_enumerate_spus (int (*fn)(void *data))
+{
+        return spu_management_ops->enumerate_spus(fn);
+}
+static inline int
+spu_create_spu (struct spu *spu, void *data)
+{
+        return spu_management_ops->create_spu(spu, data);
+}
+static inline int
+spu_destroy_spu (struct spu *spu)
+{
+        return spu_management_ops->destroy_spu(spu);
+}
+/*
+ * The declarations folowing are put here for convenience
+ * and only intended to be used by the platform setup code.
 */
 extern const struct spu_priv1_ops spu_priv1_mmio_ops;
+extern const struct spu_management_ops spu_management_of_ops;
 #endif /* __KERNEL__ */
 #endif
diff --git a/include/asm-powerpc/todc.h b/include/asm-powerpc/todc.h
deleted file mode 100644
index 60a8c39b8c11..000000000000
--- a/include/asm-powerpc/todc.h
+++ /dev/null
@@ -1,487 +0,0 @@
-/*
- * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
- * Clock chips.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-/*
- * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
- * Purpose is to make one generic file that handles all of these chips instead
- * of every platform implementing the same code over & over again.
- */
-#ifndef __PPC_KERNEL_TODC_H
-#define __PPC_KERNEL_TODC_H
-typedef struct {
-        uint rtc_type;          /* your particular chip */
-        /*
-         * Following are the addresses of the AS0, AS1, and DATA registers
-         * of these chips.  Note that these are board-specific.
-         */
-        unsigned int nvram_as0;
-        unsigned int nvram_as1;
-        unsigned int nvram_data;
-        /*
-         * Define bits to stop external set of regs from changing so
-         * the chip can be read/written reliably.
-         */
-        unsigned char enable_read;
-        unsigned char enable_write;
-        /*
-         * Following is the number of AS0 address bits.  This is normally
-         * 8 but some bad hardware routes address lines incorrectly.
-         */
-        int as0_bits;
-        int nvram_size; /* Size of NVRAM on chip */
-        int sw_flags;   /* Software control flags */
-        /* Following are the register offsets for the particular chip */
-        int year;
-        int month;
-        int day_of_month;
-        int day_of_week;
-        int hours;
-        int minutes;
-        int seconds;
-        int control_b;
-        int control_a;
-        int watchdog;
-        int interrupts;
-        int alarm_date;
-        int alarm_hour;
-        int alarm_minutes;
-        int alarm_seconds;
-        int century;
-        int flags;
-        /*
-         * Some RTC chips have their NVRAM buried behind a addr/data pair of
-         * regs on the first level/clock registers.  The following fields
-         * are the addresses for those addr/data regs.
-         */
-        int nvram_addr_reg;
-        int nvram_data_reg;
-} todc_info_t;
-/*
- * Define the types of TODC/RTC variants that are supported in
- * arch/ppc/kernel/todc_time.c
- * Make a new one of these for any chip somehow differs from what's already
- * defined.  That way, if you ever need to put in code to touch those
- * bits/registers in todc_time.c, you can put it inside an
- * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break
- * anyone else.
- */
-#define TODC_TYPE_MK48T35               1
-#define TODC_TYPE_MK48T37               2
-#define TODC_TYPE_MK48T59               3
-#define TODC_TYPE_DS1693                4       /* Dallas DS1693 RTC */
-#define TODC_TYPE_DS1743                5       /* Dallas DS1743 RTC */
-#define TODC_TYPE_DS1746                6       /* Dallas DS1746 RTC */
-#define TODC_TYPE_DS1747                7       /* Dallas DS1747 RTC */
-#define TODC_TYPE_DS1501                8       /* Dallas DS1501 RTC */
-#define TODC_TYPE_DS1643                9       /* Dallas DS1643 RTC */
-#define TODC_TYPE_PC97307               10      /* PC97307 internal RTC */
-#define TODC_TYPE_DS1557                11      /* Dallas DS1557 RTC */
-#define TODC_TYPE_DS17285               12      /* Dallas DS17285 RTC */
-#define TODC_TYPE_DS1553                13      /* Dallas DS1553 RTC */
-#define TODC_TYPE_MC146818              100     /* Leave room for m48txx's */
-/*
- * Bit to clear/set to enable reads/writes to the chip
- */
-#define TODC_MK48TXX_CNTL_A_R           0x40
-#define TODC_MK48TXX_CNTL_A_W           0x80
-#define TODC_MK48TXX_DAY_CB             0x80
-#define TODC_DS1501_CNTL_B_TE           0x80
-/*
- * Define flag bits used by todc routines.
- */
-#define TODC_FLAG_2_LEVEL_NVRAM         0x00000001
-/*
- * Define the values for the various RTC's that should to into the todc_info
- * table.
- * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
- * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
- */
-#define TODC_TYPE_MK48T35_NVRAM_SIZE            0x7ff8
-#define TODC_TYPE_MK48T35_SW_FLAGS              0
-#define TODC_TYPE_MK48T35_YEAR                  0x7fff
-#define TODC_TYPE_MK48T35_MONTH                 0x7ffe
-#define TODC_TYPE_MK48T35_DOM                   0x7ffd  /* Day of Month */
-#define TODC_TYPE_MK48T35_DOW                   0x7ffc  /* Day of Week */
-#define TODC_TYPE_MK48T35_HOURS                 0x7ffb
-#define TODC_TYPE_MK48T35_MINUTES               0x7ffa
-#define TODC_TYPE_MK48T35_SECONDS               0x7ff9
-#define TODC_TYPE_MK48T35_CNTL_B                0x7ff9
-#define TODC_TYPE_MK48T35_CNTL_A                0x7ff8
-#define TODC_TYPE_MK48T35_WATCHDOG              0x0000
-#define TODC_TYPE_MK48T35_INTERRUPTS            0x0000
-#define TODC_TYPE_MK48T35_ALARM_DATE            0x0000
-#define TODC_TYPE_MK48T35_ALARM_HOUR            0x0000
-#define TODC_TYPE_MK48T35_ALARM_MINUTES         0x0000
-#define TODC_TYPE_MK48T35_ALARM_SECONDS         0x0000
-#define TODC_TYPE_MK48T35_CENTURY               0x0000
-#define TODC_TYPE_MK48T35_FLAGS                 0x0000
-#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG        0
-#define TODC_TYPE_MK48T35_NVRAM_DATA_REG        0
-#define TODC_TYPE_MK48T37_NVRAM_SIZE            0x7ff0
-#define TODC_TYPE_MK48T37_SW_FLAGS              0
-#define TODC_TYPE_MK48T37_YEAR                  0x7fff
-#define TODC_TYPE_MK48T37_MONTH                 0x7ffe
-#define TODC_TYPE_MK48T37_DOM                   0x7ffd  /* Day of Month */
-#define TODC_TYPE_MK48T37_DOW                   0x7ffc  /* Day of Week */
-#define TODC_TYPE_MK48T37_HOURS                 0x7ffb
-#define TODC_TYPE_MK48T37_MINUTES               0x7ffa
-#define TODC_TYPE_MK48T37_SECONDS               0x7ff9
-#define TODC_TYPE_MK48T37_CNTL_B                0x7ff9
-#define TODC_TYPE_MK48T37_CNTL_A                0x7ff8
-#define TODC_TYPE_MK48T37_WATCHDOG              0x7ff7
-#define TODC_TYPE_MK48T37_INTERRUPTS            0x7ff6
-#define TODC_TYPE_MK48T37_ALARM_DATE            0x7ff5
-#define TODC_TYPE_MK48T37_ALARM_HOUR            0x7ff4
-#define TODC_TYPE_MK48T37_ALARM_MINUTES         0x7ff3
-#define TODC_TYPE_MK48T37_ALARM_SECONDS         0x7ff2
-#define TODC_TYPE_MK48T37_CENTURY               0x7ff1
-#define TODC_TYPE_MK48T37_FLAGS                 0x7ff0
-#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG        0
-#define TODC_TYPE_MK48T37_NVRAM_DATA_REG        0
-#define TODC_TYPE_MK48T59_NVRAM_SIZE            0x1ff0
-#define TODC_TYPE_MK48T59_SW_FLAGS              0
-#define TODC_TYPE_MK48T59_YEAR                  0x1fff
-#define TODC_TYPE_MK48T59_MONTH                 0x1ffe
-#define TODC_TYPE_MK48T59_DOM                   0x1ffd  /* Day of Month */
-#define TODC_TYPE_MK48T59_DOW                   0x1ffc  /* Day of Week */
-#define TODC_TYPE_MK48T59_HOURS                 0x1ffb
-#define TODC_TYPE_MK48T59_MINUTES               0x1ffa
-#define TODC_TYPE_MK48T59_SECONDS               0x1ff9
-#define TODC_TYPE_MK48T59_CNTL_B                0x1ff9
-#define TODC_TYPE_MK48T59_CNTL_A                0x1ff8
-#define TODC_TYPE_MK48T59_WATCHDOG              0x1fff
-#define TODC_TYPE_MK48T59_INTERRUPTS            0x1fff
-#define TODC_TYPE_MK48T59_ALARM_DATE            0x1fff
-#define TODC_TYPE_MK48T59_ALARM_HOUR            0x1fff
-#define TODC_TYPE_MK48T59_ALARM_MINUTES         0x1fff
-#define TODC_TYPE_MK48T59_ALARM_SECONDS         0x1fff
-#define TODC_TYPE_MK48T59_CENTURY               0x1fff
-#define TODC_TYPE_MK48T59_FLAGS                 0x1fff
-#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG        0
-#define TODC_TYPE_MK48T59_NVRAM_DATA_REG        0
-#define TODC_TYPE_DS1501_NVRAM_SIZE     0x100
-#define TODC_TYPE_DS1501_SW_FLAGS       TODC_FLAG_2_LEVEL_NVRAM
-#define TODC_TYPE_DS1501_YEAR           (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
-#define TODC_TYPE_DS1501_MONTH          (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
-#define TODC_TYPE_DS1501_DOM            (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
-#define TODC_TYPE_DS1501_DOW            (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
-#define TODC_TYPE_DS1501_HOURS          (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
-#define TODC_TYPE_DS1501_MINUTES        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
-#define TODC_TYPE_DS1501_SECONDS        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
-#define TODC_TYPE_DS1501_CNTL_B         (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
-#define TODC_TYPE_DS1501_CNTL_A         (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
-#define TODC_TYPE_DS1501_WATCHDOG       (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define TODC_TYPE_DS1501_INTERRUPTS     (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define TODC_TYPE_DS1501_ALARM_DATE     (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
-#define TODC_TYPE_DS1501_ALARM_HOUR     (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
-#define TODC_TYPE_DS1501_ALARM_MINUTES  (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
-#define TODC_TYPE_DS1501_ALARM_SECONDS  (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
-#define TODC_TYPE_DS1501_CENTURY        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
-#define TODC_TYPE_DS1501_FLAGS          (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
-#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
-#define TODC_TYPE_DS1553_NVRAM_SIZE             0x1ff0
-#define TODC_TYPE_DS1553_SW_FLAGS               0
-#define TODC_TYPE_DS1553_YEAR                   0x1fff
-#define TODC_TYPE_DS1553_MONTH                  0x1ffe
-#define TODC_TYPE_DS1553_DOM                    0x1ffd  /* Day of Month */
-#define TODC_TYPE_DS1553_DOW                    0x1ffc  /* Day of Week */
-#define TODC_TYPE_DS1553_HOURS                  0x1ffb
-#define TODC_TYPE_DS1553_MINUTES                0x1ffa
-#define TODC_TYPE_DS1553_SECONDS                0x1ff9
-#define TODC_TYPE_DS1553_CNTL_B                 0x1ff9
-#define TODC_TYPE_DS1553_CNTL_A                 0x1ff8  /* control_a R/W regs */
-#define TODC_TYPE_DS1553_WATCHDOG               0x1ff7
-#define TODC_TYPE_DS1553_INTERRUPTS             0x1ff6
-#define TODC_TYPE_DS1553_ALARM_DATE             0x1ff5
-#define TODC_TYPE_DS1553_ALARM_HOUR             0x1ff4
-#define TODC_TYPE_DS1553_ALARM_MINUTES          0x1ff3
-#define TODC_TYPE_DS1553_ALARM_SECONDS          0x1ff2
-#define TODC_TYPE_DS1553_CENTURY                0x1ff8
-#define TODC_TYPE_DS1553_FLAGS                  0x1ff0
-#define TODC_TYPE_DS1553_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1553_NVRAM_DATA_REG         0
-#define TODC_TYPE_DS1557_NVRAM_SIZE             0x7fff0
-#define TODC_TYPE_DS1557_SW_FLAGS               0
-#define TODC_TYPE_DS1557_YEAR                   0x7ffff
-#define TODC_TYPE_DS1557_MONTH                  0x7fffe
-#define TODC_TYPE_DS1557_DOM                    0x7fffd /* Day of Month */
-#define TODC_TYPE_DS1557_DOW                    0x7fffc /* Day of Week */
-#define TODC_TYPE_DS1557_HOURS                  0x7fffb
-#define TODC_TYPE_DS1557_MINUTES                0x7fffa
-#define TODC_TYPE_DS1557_SECONDS                0x7fff9
-#define TODC_TYPE_DS1557_CNTL_B                 0x7fff9
-#define TODC_TYPE_DS1557_CNTL_A                 0x7fff8 /* control_a R/W regs */
-#define TODC_TYPE_DS1557_WATCHDOG               0x7fff7
-#define TODC_TYPE_DS1557_INTERRUPTS             0x7fff6
-#define TODC_TYPE_DS1557_ALARM_DATE             0x7fff5
-#define TODC_TYPE_DS1557_ALARM_HOUR             0x7fff4
-#define TODC_TYPE_DS1557_ALARM_MINUTES          0x7fff3
-#define TODC_TYPE_DS1557_ALARM_SECONDS          0x7fff2
-#define TODC_TYPE_DS1557_CENTURY                0x7fff8
-#define TODC_TYPE_DS1557_FLAGS                  0x7fff0
-#define TODC_TYPE_DS1557_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1557_NVRAM_DATA_REG         0
-#define TODC_TYPE_DS1643_NVRAM_SIZE             0x1ff8
-#define TODC_TYPE_DS1643_SW_FLAGS               0
-#define TODC_TYPE_DS1643_YEAR                   0x1fff
-#define TODC_TYPE_DS1643_MONTH                  0x1ffe
-#define TODC_TYPE_DS1643_DOM                    0x1ffd  /* Day of Month */
-#define TODC_TYPE_DS1643_DOW                    0x1ffc  /* Day of Week */
-#define TODC_TYPE_DS1643_HOURS                  0x1ffb
-#define TODC_TYPE_DS1643_MINUTES                0x1ffa
-#define TODC_TYPE_DS1643_SECONDS                0x1ff9
-#define TODC_TYPE_DS1643_CNTL_B                 0x1ff9
-#define TODC_TYPE_DS1643_CNTL_A                 0x1ff8  /* control_a R/W regs */
-#define TODC_TYPE_DS1643_WATCHDOG               0x1fff
-#define TODC_TYPE_DS1643_INTERRUPTS             0x1fff
-#define TODC_TYPE_DS1643_ALARM_DATE             0x1fff
-#define TODC_TYPE_DS1643_ALARM_HOUR             0x1fff
-#define TODC_TYPE_DS1643_ALARM_MINUTES          0x1fff
-#define TODC_TYPE_DS1643_ALARM_SECONDS          0x1fff
-#define TODC_TYPE_DS1643_CENTURY                0x1ff8
-#define TODC_TYPE_DS1643_FLAGS                  0x1fff
-#define TODC_TYPE_DS1643_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1643_NVRAM_DATA_REG         0
-#define TODC_TYPE_DS1693_NVRAM_SIZE             0 /* Not handled yet */
-#define TODC_TYPE_DS1693_SW_FLAGS               0
-#define TODC_TYPE_DS1693_YEAR                   0x09
-#define TODC_TYPE_DS1693_MONTH                  0x08
-#define TODC_TYPE_DS1693_DOM                    0x07    /* Day of Month */
-#define TODC_TYPE_DS1693_DOW                    0x06    /* Day of Week */
-#define TODC_TYPE_DS1693_HOURS                  0x04
-#define TODC_TYPE_DS1693_MINUTES                0x02
-#define TODC_TYPE_DS1693_SECONDS                0x00
-#define TODC_TYPE_DS1693_CNTL_B                 0x0b
-#define TODC_TYPE_DS1693_CNTL_A                 0x0a
-#define TODC_TYPE_DS1693_WATCHDOG               0xff
-#define TODC_TYPE_DS1693_INTERRUPTS             0xff
-#define TODC_TYPE_DS1693_ALARM_DATE             0x49
-#define TODC_TYPE_DS1693_ALARM_HOUR             0x05
-#define TODC_TYPE_DS1693_ALARM_MINUTES          0x03
-#define TODC_TYPE_DS1693_ALARM_SECONDS          0x01
-#define TODC_TYPE_DS1693_CENTURY                0x48
-#define TODC_TYPE_DS1693_FLAGS                  0xff
-#define TODC_TYPE_DS1693_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1693_NVRAM_DATA_REG         0
-#define TODC_TYPE_DS1743_NVRAM_SIZE             0x1ff8
-#define TODC_TYPE_DS1743_SW_FLAGS               0
-#define TODC_TYPE_DS1743_YEAR                   0x1fff
-#define TODC_TYPE_DS1743_MONTH                  0x1ffe
-#define TODC_TYPE_DS1743_DOM                    0x1ffd  /* Day of Month */
-#define TODC_TYPE_DS1743_DOW                    0x1ffc  /* Day of Week */
-#define TODC_TYPE_DS1743_HOURS                  0x1ffb
-#define TODC_TYPE_DS1743_MINUTES                0x1ffa
-#define TODC_TYPE_DS1743_SECONDS                0x1ff9
-#define TODC_TYPE_DS1743_CNTL_B                 0x1ff9
-#define TODC_TYPE_DS1743_CNTL_A                 0x1ff8  /* control_a R/W regs */
-#define TODC_TYPE_DS1743_WATCHDOG               0x1fff
-#define TODC_TYPE_DS1743_INTERRUPTS             0x1fff
-#define TODC_TYPE_DS1743_ALARM_DATE             0x1fff
-#define TODC_TYPE_DS1743_ALARM_HOUR             0x1fff
-#define TODC_TYPE_DS1743_ALARM_MINUTES          0x1fff
-#define TODC_TYPE_DS1743_ALARM_SECONDS          0x1fff
-#define TODC_TYPE_DS1743_CENTURY                0x1ff8
-#define TODC_TYPE_DS1743_FLAGS                  0x1fff
-#define TODC_TYPE_DS1743_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1743_NVRAM_DATA_REG         0
-#define TODC_TYPE_DS1746_NVRAM_SIZE             0x1fff8
-#define TODC_TYPE_DS1746_SW_FLAGS               0
-#define TODC_TYPE_DS1746_YEAR                   0x1ffff
-#define TODC_TYPE_DS1746_MONTH                  0x1fffe
-#define TODC_TYPE_DS1746_DOM                    0x1fffd /* Day of Month */
-#define TODC_TYPE_DS1746_DOW                    0x1fffc /* Day of Week */
-#define TODC_TYPE_DS1746_HOURS                  0x1fffb
-#define TODC_TYPE_DS1746_MINUTES                0x1fffa
-#define TODC_TYPE_DS1746_SECONDS                0x1fff9
-#define TODC_TYPE_DS1746_CNTL_B                 0x1fff9
-#define TODC_TYPE_DS1746_CNTL_A                 0x1fff8 /* control_a R/W regs */
-#define TODC_TYPE_DS1746_WATCHDOG               0x00000
-#define TODC_TYPE_DS1746_INTERRUPTS             0x00000
-#define TODC_TYPE_DS1746_ALARM_DATE             0x00000
-#define TODC_TYPE_DS1746_ALARM_HOUR             0x00000
-#define TODC_TYPE_DS1746_ALARM_MINUTES          0x00000
-#define TODC_TYPE_DS1746_ALARM_SECONDS          0x00000
-#define TODC_TYPE_DS1746_CENTURY                0x00000
-#define TODC_TYPE_DS1746_FLAGS                  0x00000
-#define TODC_TYPE_DS1746_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1746_NVRAM_DATA_REG         0
-#define TODC_TYPE_DS1747_NVRAM_SIZE             0x7fff8
-#define TODC_TYPE_DS1747_SW_FLAGS               0
-#define TODC_TYPE_DS1747_YEAR                   0x7ffff
-#define TODC_TYPE_DS1747_MONTH                  0x7fffe
-#define TODC_TYPE_DS1747_DOM                    0x7fffd /* Day of Month */
-#define TODC_TYPE_DS1747_DOW                    0x7fffc /* Day of Week */
-#define TODC_TYPE_DS1747_HOURS                  0x7fffb
-#define TODC_TYPE_DS1747_MINUTES                0x7fffa
-#define TODC_TYPE_DS1747_SECONDS                0x7fff9
-#define TODC_TYPE_DS1747_CNTL_B                 0x7fff9
-#define TODC_TYPE_DS1747_CNTL_A                 0x7fff8 /* control_a R/W regs */
-#define TODC_TYPE_DS1747_WATCHDOG               0x00000
-#define TODC_TYPE_DS1747_INTERRUPTS             0x00000
-#define TODC_TYPE_DS1747_ALARM_DATE             0x00000
-#define TODC_TYPE_DS1747_ALARM_HOUR             0x00000
-#define TODC_TYPE_DS1747_ALARM_MINUTES          0x00000
-#define TODC_TYPE_DS1747_ALARM_SECONDS          0x00000
-#define TODC_TYPE_DS1747_CENTURY                0x00000
-#define TODC_TYPE_DS1747_FLAGS                  0x00000
-#define TODC_TYPE_DS1747_NVRAM_ADDR_REG         0
-#define TODC_TYPE_DS1747_NVRAM_DATA_REG         0
-#define TODC_TYPE_DS17285_NVRAM_SIZE            (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
-#define TODC_TYPE_DS17285_SW_FLAGS              TODC_FLAG_2_LEVEL_NVRAM
-#define TODC_TYPE_DS17285_SECONDS               (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
-#define TODC_TYPE_DS17285_ALARM_SECONDS         (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
-#define TODC_TYPE_DS17285_MINUTES               (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
-#define TODC_TYPE_DS17285_ALARM_MINUTES         (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
-#define TODC_TYPE_DS17285_HOURS                 (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
-#define TODC_TYPE_DS17285_ALARM_HOUR            (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
-#define TODC_TYPE_DS17285_DOW                   (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
-#define TODC_TYPE_DS17285_DOM                   (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
-#define TODC_TYPE_DS17285_MONTH                 (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
-#define TODC_TYPE_DS17285_YEAR                  (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
-#define TODC_TYPE_DS17285_CNTL_A                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
-#define TODC_TYPE_DS17285_CNTL_B                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
-#define TODC_TYPE_DS17285_CNTL_C                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
-#define TODC_TYPE_DS17285_CNTL_D                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
-#define TODC_TYPE_DS17285_WATCHDOG              0
-#define TODC_TYPE_DS17285_INTERRUPTS            0
-#define TODC_TYPE_DS17285_ALARM_DATE            0
-#define TODC_TYPE_DS17285_CENTURY               0
-#define TODC_TYPE_DS17285_FLAGS                 0
-#define TODC_TYPE_DS17285_NVRAM_ADDR_REG        0x50
-#define TODC_TYPE_DS17285_NVRAM_DATA_REG        0x53
-#define TODC_TYPE_MC146818_NVRAM_SIZE           0       /* XXXX */
-#define TODC_TYPE_MC146818_SW_FLAGS             0
-#define TODC_TYPE_MC146818_YEAR                 0x09
-#define TODC_TYPE_MC146818_MONTH                0x08
-#define TODC_TYPE_MC146818_DOM                  0x07    /* Day of Month */
-#define TODC_TYPE_MC146818_DOW                  0x06    /* Day of Week */
-#define TODC_TYPE_MC146818_HOURS                0x04
-#define TODC_TYPE_MC146818_MINUTES              0x02
-#define TODC_TYPE_MC146818_SECONDS              0x00
-#define TODC_TYPE_MC146818_CNTL_B               0x0a
-#define TODC_TYPE_MC146818_CNTL_A               0x0b    /* control_a R/W regs */
-#define TODC_TYPE_MC146818_WATCHDOG             0
-#define TODC_TYPE_MC146818_INTERRUPTS           0x0c
-#define TODC_TYPE_MC146818_ALARM_DATE           0xff
-#define TODC_TYPE_MC146818_ALARM_HOUR           0x05
-#define TODC_TYPE_MC146818_ALARM_MINUTES        0x03
-#define TODC_TYPE_MC146818_ALARM_SECONDS        0x01
-#define TODC_TYPE_MC146818_CENTURY              0xff
-#define TODC_TYPE_MC146818_FLAGS                0xff
-#define TODC_TYPE_MC146818_NVRAM_ADDR_REG       0
-#define TODC_TYPE_MC146818_NVRAM_DATA_REG       0
-#define TODC_TYPE_PC97307_NVRAM_SIZE            0       /* No NVRAM? */
-#define TODC_TYPE_PC97307_SW_FLAGS              0
-#define TODC_TYPE_PC97307_YEAR                  0x09
-#define TODC_TYPE_PC97307_MONTH                 0x08
-#define TODC_TYPE_PC97307_DOM                   0x07    /* Day of Month */
-#define TODC_TYPE_PC97307_DOW                   0x06    /* Day of Week */
-#define TODC_TYPE_PC97307_HOURS                 0x04
-#define TODC_TYPE_PC97307_MINUTES               0x02
-#define TODC_TYPE_PC97307_SECONDS               0x00
-#define TODC_TYPE_PC97307_CNTL_B                0x0a
-#define TODC_TYPE_PC97307_CNTL_A                0x0b    /* control_a R/W regs */
-#define TODC_TYPE_PC97307_WATCHDOG              0x0c
-#define TODC_TYPE_PC97307_INTERRUPTS            0x0d
-#define TODC_TYPE_PC97307_ALARM_DATE            0xff
-#define TODC_TYPE_PC97307_ALARM_HOUR            0x05
-#define TODC_TYPE_PC97307_ALARM_MINUTES         0x03
-#define TODC_TYPE_PC97307_ALARM_SECONDS         0x01
-#define TODC_TYPE_PC97307_CENTURY               0xff
-#define TODC_TYPE_PC97307_FLAGS                 0xff
-#define TODC_TYPE_PC97307_NVRAM_ADDR_REG        0
-#define TODC_TYPE_PC97307_NVRAM_DATA_REG        0
-/*
- * Define macros to allocate and init the todc_info_t table that will
- * be used by the todc_time.c routines.
- */
-#define TODC_ALLOC()                                                    \
-        static todc_info_t todc_info_alloc;                             \
-        todc_info_t *todc_info = &todc_info_alloc;
-#define TODC_INIT(clock_type, as0, as1, data, bits) {                   \
-        todc_info->rtc_type = clock_type;                               \
-                                                                        \
-        todc_info->nvram_as0 = (unsigned int)(as0);                     \
-        todc_info->nvram_as1 = (unsigned int)(as1);                     \
-        todc_info->nvram_data = (unsigned int)(data);                   \
-                                                                        \
-        todc_info->as0_bits = (bits);                                   \
-                                                                        \
-        todc_info->nvram_size = clock_type ##_NVRAM_SIZE;               \
-        todc_info->sw_flags = clock_type ##_SW_FLAGS;                   \
-                                                                        \
-        todc_info->year = clock_type ##_YEAR;                           \
-        todc_info->month = clock_type ##_MONTH;                         \
-        todc_info->day_of_month = clock_type ##_DOM;                    \
-        todc_info->day_of_week = clock_type ##_DOW;                     \
-        todc_info->hours = clock_type ##_HOURS;                         \
-        todc_info->minutes = clock_type ##_MINUTES;                     \
-        todc_info->seconds = clock_type ##_SECONDS;                     \
-        todc_info->control_b = clock_type ##_CNTL_B;                    \
-        todc_info->control_a = clock_type ##_CNTL_A;                    \
-        todc_info->watchdog = clock_type ##_WATCHDOG;                   \
-        todc_info->interrupts = clock_type ##_INTERRUPTS;               \
-        todc_info->alarm_date = clock_type ##_ALARM_DATE;               \
-        todc_info->alarm_hour = clock_type ##_ALARM_HOUR;               \
-        todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES;         \
-        todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS;         \
-        todc_info->century = clock_type ##_CENTURY;                     \
-        todc_info->flags = clock_type ##_FLAGS;                         \
-                                                                        \
-        todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG;       \
-        todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG;       \
-}
-extern todc_info_t *todc_info;
-unsigned char todc_direct_read_val(int addr);
-void todc_direct_write_val(int addr, unsigned char val);
-unsigned char todc_m48txx_read_val(int addr);
-void todc_m48txx_write_val(int addr, unsigned char val);
-unsigned char todc_mc146818_read_val(int addr);
-void todc_mc146818_write_val(int addr, unsigned char val);
-long todc_time_init(void);
-void todc_get_rtc_time(struct rtc_time *);
-int todc_set_rtc_time(struct rtc_time *);
-void todc_calibrate_decr(void);
-#endif                          /* __PPC_KERNEL_TODC_H */
diff --git a/include/asm-powerpc/topology.h b/include/asm-powerpc/topology.h
index 9fe7894ee035..50c014007de7 100644
--- a/include/asm-powerpc/topology.h
+++ b/include/asm-powerpc/topology.h
@@ -32,7 +32,14 @@ static inline int node_to_first_cpu(int node)
 int of_node_to_nid(struct device_node *device);
 struct pci_bus;
+#ifdef CONFIG_PCI
 extern int pcibus_to_node(struct pci_bus *bus);
+#else
+static inline int pcibus_to_node(struct pci_bus *bus)
+{
+        return -1;
+}
+#endif
 #define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
                                        CPU_MASK_ALL : \
diff --git a/include/asm-powerpc/tsi108.h b/include/asm-powerpc/tsi108.h
index 2c702d35a7cf..4e95d153be84 100644
--- a/include/asm-powerpc/tsi108.h
+++ b/include/asm-powerpc/tsi108.h
@@ -98,12 +98,12 @@ typedef struct {
 extern u32 get_vir_csrbase(void);
 extern u32 tsi108_csr_vir_base;
-extern inline u32 tsi108_read_reg(u32 reg_offset)
+static inline u32 tsi108_read_reg(u32 reg_offset)
 {
        return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
 }
-extern inline void tsi108_write_reg(u32 reg_offset, u32 val)
+static inline void tsi108_write_reg(u32 reg_offset, u32 val)
 {
        out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
 }
diff --git a/include/asm-powerpc/types.h b/include/asm-powerpc/types.h
index d6fb56b80453..3b363757a2bb 100644
--- a/include/asm-powerpc/types.h
+++ b/include/asm-powerpc/types.h
@@ -97,16 +97,6 @@ typedef struct {
        unsigned long env;
 } func_descr_t;
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
-#ifdef CONFIG_LSF
-typedef u64 blkcnt_t;
-#define HAVE_BLKCNT_T
-#endif
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/uaccess.h b/include/asm-powerpc/uaccess.h
index d83fc29c2bbf..adbf16b8cfbb 100644
--- a/include/asm-powerpc/uaccess.h
+++ b/include/asm-powerpc/uaccess.h
@@ -304,7 +304,7 @@ extern unsigned long __copy_tofrom_user(void __user *to,
 #ifndef __powerpc64__
-extern inline unsigned long copy_from_user(void *to,
+static inline unsigned long copy_from_user(void *to,
                const void __user *from, unsigned long n)
 {
        unsigned long over;
@@ -319,7 +319,7 @@ extern inline unsigned long copy_from_user(void *to,
        return n;
 }
-extern inline unsigned long copy_to_user(void __user *to,
+static inline unsigned long copy_to_user(void __user *to,
                const void *from, unsigned long n)
 {
        unsigned long over;
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h
index 0e4ea37f6466..04b6c17cc59b 100644
--- a/include/asm-powerpc/unistd.h
+++ b/include/asm-powerpc/unistd.h
@@ -446,7 +446,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 #include <linux/types.h>
 #include <linux/compiler.h>
 #include <linux/linkage.h>
-#include <asm/syscalls.h>
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
@@ -481,16 +480,9 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 /*
 * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
 */
-#ifdef CONFIG_PPC32
+#define cond_syscall(x) \
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+        asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
-#else
-#define cond_syscall(x) asm(".weak\t." #x "\n\t.set\t." #x ",.sys_ni_syscall")
-#endif
 #endif          /* __ASSEMBLY__ */
 #endif          /* __KERNEL__ */
diff --git a/include/asm-powerpc/vio.h b/include/asm-powerpc/vio.h
index 4b51d42e1419..0117b544ecbc 100644
--- a/include/asm-powerpc/vio.h
+++ b/include/asm-powerpc/vio.h
@@ -45,7 +45,6 @@ struct iommu_table;
 * The vio_dev structure is used to describe virtual I/O devices.
 */
 struct vio_dev {
-        struct iommu_table *iommu_table;     /* vio_map_* uses this */
        const char *name;
        const char *type;
        uint32_t unit_address;
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
index f1d337ed68d5..88320a05f0a8 100644
--- a/include/asm-powerpc/xmon.h
+++ b/include/asm-powerpc/xmon.h
@@ -14,8 +14,10 @@
 #ifdef CONFIG_XMON
 extern void xmon_setup(void);
+extern void xmon_register_spus(struct list_head *list);
 #else
 static inline void xmon_setup(void) { };
+static inline void xmon_register_spus(struct list_head *list) { };
 #endif
 #endif /* __KERNEL __ */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index a4c411b753ef..ccf1a9bb2e43 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -26,17 +26,11 @@
 #if defined(CONFIG_4xx)
 #include <asm/ibm4xx.h>
-#elif defined(CONFIG_PPC_MPC52xx)
-#include <asm/mpc52xx.h>
 #elif defined(CONFIG_8xx)
 #include <asm/mpc8xx.h>
 #elif defined(CONFIG_8260)
 #include <asm/mpc8260.h>
-#elif defined(CONFIG_83xx)
+#elif defined(CONFIG_APUS) || !defined(CONFIG_PCI)
-#include <asm/mpc83xx.h>
-#elif defined(CONFIG_85xx)
-#include <asm/mpc85xx.h>
-#elif defined(CONFIG_APUS)
 #define _IO_BASE        0
 #define _ISA_MEM_BASE   0
 #define PCI_DRAM_OFFSET 0
@@ -237,6 +231,14 @@ static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
 #define insl(port, buf, nl)     _insl_ns((port)+___IO_BASE, (buf), (nl))
 #define outsl(port, buf, nl)    _outsl_ns((port)+___IO_BASE, (buf), (nl))
+#define readsb(a, b, n)         _insb((a), (b), (n))
+#define readsw(a, b, n)         _insw_ns((a), (b), (n))
+#define readsl(a, b, n)         _insl_ns((a), (b), (n))
+#define writesb(a, b, n)        _outsb((a),(b),(n))
+#define writesw(a, b, n)        _outsw_ns((a),(b),(n))
+#define writesl(a, b, n)        _outsl_ns((a),(b),(n))
 /*
 * On powermacs and 8xx we will get a machine check exception 
 * if we try to read data from a non-existent I/O port. Because
@@ -327,12 +329,12 @@ __do_out_asm(outl, "stwbrx")
 #define inl_p(port)             inl((port))
 #define outl_p(val, port)       outl((val), (port))
-extern void _insb(volatile u8 __iomem *port, void *buf, long count);
+extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
-extern void _outsb(volatile u8 __iomem *port, const void *buf, long count);
+extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
-extern void _insw_ns(volatile u16 __iomem *port, void *buf, long count);
+extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
-extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, long count);
+extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
-extern void _insl_ns(volatile u32 __iomem *port, void *buf, long count);
+extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
-extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, long count);
+extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
 #define IO_SPACE_LIMIT ~0
diff --git a/include/asm-ppc/m48t35.h b/include/asm-ppc/m48t35.h
index f3c5e5dfa986..a5277ea4b194 100644
--- a/include/asm-ppc/m48t35.h
+++ b/include/asm-ppc/m48t35.h
@@ -39,7 +39,7 @@
 #define M48T35_RTC_WATCHDOG_RB         0x03
 #define M48T35_RTC_WATCHDOG_BMB        0x7c
 #define M48T35_RTC_WATCHDOG_WDS        0x80
-#define M48T35_RTC_WATCHDOG_ALL        (M48T35_RTC_WATCHDOG_RB|M48T35_RTC_WATCHDOG_BMB|M48T35_RTC_W
+#define M48T35_RTC_WATCHDOG_ALL        (M48T35_RTC_WATCHDOG_RB|M48T35_RTC_WATCHDOG_BMB|M48T35_RTC_W)
 #define M48T35_RTC_CONTROL_WRITE       0x80
 #define M48T35_RTC_CONTROL_READ        0x40
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
index 64c8874618dc..d9d21aa68ba3 100644
--- a/include/asm-ppc/mpc52xx.h
+++ b/include/asm-ppc/mpc52xx.h
@@ -29,17 +29,6 @@ struct pt_regs;
 #endif /* __ASSEMBLY__ */
-#ifdef CONFIG_PCI
-#define _IO_BASE        isa_io_base
-#define _ISA_MEM_BASE   isa_mem_base
-#define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define _IO_BASE        0
-#define _ISA_MEM_BASE   0
-#define PCI_DRAM_OFFSET 0
-#endif
 /* ======================================================================== */
 /* PPC Sys devices definition                                               */
 /* ======================================================================== */
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
index 02ed2c325714..c3061972309b 100644
--- a/include/asm-ppc/mpc83xx.h
+++ b/include/asm-ppc/mpc83xx.h
@@ -25,14 +25,6 @@
 #include <platforms/83xx/mpc834x_sys.h>
 #endif
-#define _IO_BASE        isa_io_base
-#define _ISA_MEM_BASE   isa_mem_base
-#ifdef CONFIG_PCI
-#define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define PCI_DRAM_OFFSET 0
-#endif
 /*
 * The "residual" board information structure the boot loader passes
 * into the kernel.
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 9b4851199c76..d7e4a79d77fb 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -44,14 +44,6 @@
 #include <platforms/85xx/tqm85xx.h>
 #endif
-#define _IO_BASE        isa_io_base
-#define _ISA_MEM_BASE   isa_mem_base
-#ifdef CONFIG_PCI
-#define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define PCI_DRAM_OFFSET 0
-#endif
 /*
 * The "residual" board information structure the boot loader passes
 * into the kernel.
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
index 9d5230689b31..6c955d0c1ef0 100644
--- a/include/asm-ppc/pci-bridge.h
+++ b/include/asm-ppc/pci-bridge.h
@@ -43,6 +43,7 @@ struct pci_controller {
        struct pci_controller *next;
        struct pci_bus *bus;
        void *arch_data;
+        struct device *parent;
        int first_busno;
        int last_busno;
diff --git a/include/asm-s390/types.h b/include/asm-s390/types.h
index ae2951cc83ac..fc5d7cf19324 100644
--- a/include/asm-s390/types.h
+++ b/include/asm-s390/types.h
@@ -87,16 +87,6 @@ typedef union {
        } subreg;
 } register_pair;
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
-#ifdef CONFIG_LSF
-typedef u64 blkcnt_t;
-#define HAVE_BLKCNT_T
-#endif
 #endif /* ! __s390x__   */
 #endif /* __ASSEMBLY__  */
 #endif /* __KERNEL__    */
diff --git a/include/asm-sh/atomic.h b/include/asm-sh/atomic.h
index 8bdc1ba56f73..28305c3cbddf 100644
--- a/include/asm-sh/atomic.h
+++ b/include/asm-sh/atomic.h
@@ -28,11 +28,11 @@ static inline void atomic_add(int i, atomic_t *v)
        unsigned long tmp;
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_add    \n"
+"1:     movli.l @%2, %0         ! atomic_add    \n"
-"       add     %2, %0                          \n"
+"       add     %1, %0                          \n"
-"       movco.l %0, @%3                         \n"
+"       movco.l %0, @%2                         \n"
 "       bf      1b                              \n"
-        : "=&z" (tmp), "=r" (&v->counter)
+        : "=&z" (tmp)
        : "r" (i), "r" (&v->counter)
        : "t");
 #else
@@ -50,11 +50,11 @@ static inline void atomic_sub(int i, atomic_t *v)
        unsigned long tmp;
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_sub    \n"
+"1:     movli.l @%2, %0         ! atomic_sub    \n"
-"       sub     %2, %0                          \n"
+"       sub     %1, %0                          \n"
-"       movco.l %0, @%3                         \n"
+"       movco.l %0, @%2                         \n"
 "       bf      1b                              \n"
-        : "=&z" (tmp), "=r" (&v->counter)
+        : "=&z" (tmp)
        : "r" (i), "r" (&v->counter)
        : "t");
 #else
@@ -80,12 +80,12 @@ static inline int atomic_add_return(int i, atomic_t *v)
 #ifdef CONFIG_CPU_SH4A
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_add_return     \n"
+"1:     movli.l @%2, %0         ! atomic_add_return     \n"
-"       add     %2, %0                                  \n"
+"       add     %1, %0                                  \n"
-"       movco.l %0, @%3                                 \n"
+"       movco.l %0, @%2                                 \n"
 "       bf      1b                                      \n"
 "       synco                                           \n"
-        : "=&z" (temp), "=r" (&v->counter)
+        : "=&z" (temp)
        : "r" (i), "r" (&v->counter)
        : "t");
 #else
@@ -109,12 +109,12 @@ static inline int atomic_sub_return(int i, atomic_t *v)
 #ifdef CONFIG_CPU_SH4A
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_sub_return     \n"
+"1:     movli.l @%2, %0         ! atomic_sub_return     \n"
-"       sub     %2, %0                                  \n"
+"       sub     %1, %0                                  \n"
-"       movco.l %0, @%3                                 \n"
+"       movco.l %0, @%2                                 \n"
 "       bf      1b                                      \n"
 "       synco                                           \n"
-        : "=&z" (temp), "=r" (&v->counter)
+        : "=&z" (temp)
        : "r" (i), "r" (&v->counter)
        : "t");
 #else
@@ -186,11 +186,11 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
        unsigned long tmp;
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_clear_mask     \n"
+"1:     movli.l @%2, %0         ! atomic_clear_mask     \n"
-"       and     %2, %0                                  \n"
+"       and     %1, %0                                  \n"
-"       movco.l %0, @%3                                 \n"
+"       movco.l %0, @%2                                 \n"
 "       bf      1b                                      \n"
-        : "=&z" (tmp), "=r" (&v->counter)
+        : "=&z" (tmp)
        : "r" (~mask), "r" (&v->counter)
        : "t");
 #else
@@ -208,11 +208,11 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
        unsigned long tmp;
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_set_mask       \n"
+"1:     movli.l @%2, %0         ! atomic_set_mask       \n"
-"       or      %2, %0                                  \n"
+"       or      %1, %0                                  \n"
-"       movco.l %0, @%3                                 \n"
+"       movco.l %0, @%2                                 \n"
 "       bf      1b                                      \n"
-        : "=&z" (tmp), "=r" (&v->counter)
+        : "=&z" (tmp)
        : "r" (mask), "r" (&v->counter)
        : "t");
 #else
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index beeea40f549e..795047da5e17 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -23,16 +23,20 @@ static void __init check_bugs(void)
        cpu_data->loops_per_jiffy = loops_per_jiffy;
        switch (cpu_data->type) {
-        case CPU_SH7604:
+        case CPU_SH7604 ... CPU_SH7619:
                *p++ = '2';
                break;
+        case CPU_SH7206:
+                *p++ = '2';
+                *p++ = 'a';
+                break;
        case CPU_SH7705 ... CPU_SH7300:
                *p++ = '3';
                break;
        case CPU_SH7750 ... CPU_SH4_501:
                *p++ = '4';
                break;
-        case CPU_SH7770 ... CPU_SH7781:
+        case CPU_SH7770 ... CPU_SH7785:
                *p++ = '4';
                *p++ = 'a';
                break;
diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h
index fdfb75b30f0d..1df92807f8c5 100644
--- a/include/asm-sh/clock.h
+++ b/include/asm-sh/clock.h
@@ -4,6 +4,7 @@
 #include <linux/kref.h>
 #include <linux/list.h>
 #include <linux/seq_file.h>
+#include <linux/clk.h>
 struct clk;
@@ -18,7 +19,7 @@ struct clk_ops {
 struct clk {
        struct list_head        node;
        const char              *name;
+        int                     id;
        struct module           *owner;
        struct clk              *parent;
@@ -40,22 +41,13 @@ void arch_init_clk_ops(struct clk_ops **, int type);
 int clk_init(void);
 int __clk_enable(struct clk *);
-int clk_enable(struct clk *);
 void __clk_disable(struct clk *);
-void clk_disable(struct clk *);
-int clk_set_rate(struct clk *, unsigned long rate);
-unsigned long clk_get_rate(struct clk *);
 void clk_recalc_rate(struct clk *);
-struct clk *clk_get(const char *id);
-void clk_put(struct clk *);
 int clk_register(struct clk *);
 void clk_unregister(struct clk *);
 int show_clocks(struct seq_file *m);
 #endif /* __ASM_SH_CLOCK_H */
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index cd96402e8562..20b9796842dc 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,6 +12,7 @@
 #define L1_CACHE_SHIFT  4
+#if defined(CONFIG_CPU_SUBTYPE_SH7604)
 #define CCR             0xfffffe92      /* Address of Cache Control Register */
 #define CCR_CACHE_CE    0x01    /* Cache enable */
@@ -27,5 +28,26 @@
 #define CCR_CACHE_ORA           CCR_CACHE_TW
 #define CCR_CACHE_WT            0x00    /* SH-2 is _always_ write-through */
+#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define CCR1            0xffffffec
+#define CCR             CCR1
+#define CCR_CACHE_CE    0x01    /* Cache enable */
+#define CCR_CACHE_WT    0x06    /* CCR[bit1=1,bit2=1] */
+                                /* 0x00000000-0x7fffffff: Write-through  */
+                                /* 0x80000000-0x9fffffff: Write-back     */
+                                /* 0xc0000000-0xdfffffff: Write-through  */
+#define CCR_CACHE_CB    0x00    /* CCR[bit1=0,bit2=0] */
+                                /* 0x00000000-0x7fffffff: Write-back     */
+                                /* 0x80000000-0x9fffffff: Write-through  */
+                                /* 0xc0000000-0xdfffffff: Write-back     */
+#define CCR_CACHE_CF    0x08    /* Cache invalidate */
+#define CACHE_OC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_DATA_ARRAY     0xf1000000
+#define CCR_CACHE_ENABLE        CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE    CCR_CACHE_CF
+#endif
 #endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/include/asm-sh/cpu-sh2/freq.h b/include/asm-sh/cpu-sh2/freq.h
new file mode 100644
index 000000000000..31de475da70b
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_FREQ_H
+#define __ASM_CPU_SH2_FREQ_H
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define FREQCR  0xf815ff80
+#endif
+#endif /* __ASM_CPU_SH2_FREQ_H */
diff --git a/include/asm-sh/cpu-sh2/mmu_context.h b/include/asm-sh/cpu-sh2/mmu_context.h
new file mode 100644
index 000000000000..beeb299e01ec
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/mmu_context.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-sh/cpu-sh2/mmu_context.h
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
+#define __ASM_CPU_SH2_MMU_CONTEXT_H
+/* No MMU */
+#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
diff --git a/include/asm-sh/cpu-sh2/timer.h b/include/asm-sh/cpu-sh2/timer.h
new file mode 100644
index 000000000000..a39c241e8195
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/timer.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_CPU_SH2_TIMER_H
+#define __ASM_CPU_SH2_TIMER_H
+/* Nothing needed yet */
+#endif /* __ASM_CPU_SH2_TIMER_H */
diff --git a/include/asm-sh/cpu-sh2a/addrspace.h b/include/asm-sh/cpu-sh2a/addrspace.h
new file mode 100644
index 000000000000..3d2e9aa21522
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/addrspace.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/addrspace.h>
diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
new file mode 100644
index 000000000000..3e4b9e480982
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cache.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-sh/cpu-sh2a/cache.h
+ *
+ * Copyright (C) 2004 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_CACHE_H
+#define __ASM_CPU_SH2A_CACHE_H
+#define L1_CACHE_SHIFT  4
+#define CCR1            0xfffc1000
+#define CCR2            0xfffc1004
+/* CCR1 behaves more like the traditional CCR */
+#define CCR             CCR1
+/*
+ * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
+ * listed here are reserved.
+ */
+#define CCR_CACHE_CB    0x0000  /* Hack */
+#define CCR_CACHE_OCE   0x0001
+#define CCR_CACHE_WT    0x0002
+#define CCR_CACHE_OCI   0x0008  /* OCF */
+#define CCR_CACHE_ICE   0x0100
+#define CCR_CACHE_ICI   0x0800  /* ICF */
+#define CACHE_IC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY  0xf0800000
+#define CCR_CACHE_ENABLE        (CCR_CACHE_OCE | CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI | CCR_CACHE_ICI)
+#endif /* __ASM_CPU_SH2A_CACHE_H */
diff --git a/include/asm-sh/cpu-sh2a/cacheflush.h b/include/asm-sh/cpu-sh2a/cacheflush.h
new file mode 100644
index 000000000000..fa3186c73350
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cacheflush.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/cacheflush.h>
diff --git a/include/asm-sh/cpu-sh2a/dma.h b/include/asm-sh/cpu-sh2a/dma.h
new file mode 100644
index 000000000000..0d5ad85c1de8
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/dma.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/dma.h>
diff --git a/include/asm-sh/cpu-sh2a/freq.h b/include/asm-sh/cpu-sh2a/freq.h
new file mode 100644
index 000000000000..e518fff6d10f
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2a/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_FREQ_H
+#define __ASM_CPU_SH2A_FREQ_H
+#if defined(CONFIG_CPU_SUBTYPE_SH7206)
+#define FREQCR  0xfffe0010
+#endif
+#endif /* __ASM_CPU_SH2A_FREQ_H */
diff --git a/include/asm-sh/cpu-sh2a/mmu_context.h b/include/asm-sh/cpu-sh2a/mmu_context.h
new file mode 100644
index 000000000000..cd2387f7db9e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/mmu_context.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/mmu_context.h>
diff --git a/include/asm-sh/cpu-sh2a/timer.h b/include/asm-sh/cpu-sh2a/timer.h
new file mode 100644
index 000000000000..fee504adf11e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/timer.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/timer.h>
diff --git a/include/asm-sh/cpu-sh2a/ubc.h b/include/asm-sh/cpu-sh2a/ubc.h
new file mode 100644
index 000000000000..cf28062b96a2
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/ubc.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/ubc.h>
diff --git a/include/asm-sh/cpu-sh2a/watchdog.h b/include/asm-sh/cpu-sh2a/watchdog.h
new file mode 100644
index 000000000000..c1b3e2488478
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/watchdog.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/watchdog.h>
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index d9daa028689f..faf3051cd429 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -14,9 +14,7 @@
 #include <linux/spinlock.h>
 #include <linux/wait.h>
 #include <linux/sysdev.h>
-#include <linux/device.h>
 #include <asm/cpu/dma.h>
-#include <asm/semaphore.h>
 /* The maximum address that we can perform a DMA transfer to on this platform */
 /* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
@@ -46,16 +44,21 @@
 * DMAC (dma_info) flags
 */
 enum {
-        DMAC_CHANNELS_CONFIGURED        = 0x00,
+        DMAC_CHANNELS_CONFIGURED        = 0x01,
-        DMAC_CHANNELS_TEI_CAPABLE       = 0x01,
+        DMAC_CHANNELS_TEI_CAPABLE       = 0x02, /* Transfer end interrupt */
 };
 /*
 * DMA channel capabilities / flags
 */
 enum {
-        DMA_TEI_CAPABLE                 = 0x01,
+        DMA_CONFIGURED                  = 0x01,
-        DMA_CONFIGURED                  = 0x02,
+        /*
+         * Transfer end interrupt, inherited from DMAC.
+         * wait_queue used in dma_wait_for_completion.
+         */
+        DMA_TEI_CAPABLE                 = 0x02,
 };
 extern spinlock_t dma_spin_lock;
@@ -68,28 +71,31 @@ struct dma_ops {
        int (*get_residue)(struct dma_channel *chan);
        int (*xfer)(struct dma_channel *chan);
-        void (*configure)(struct dma_channel *chan, unsigned long flags);
+        int (*configure)(struct dma_channel *chan, unsigned long flags);
+        int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
 };
 struct dma_channel {
-        char dev_id[16];
+        char dev_id[16];                /* unique name per DMAC of channel */
-        unsigned int chan;              /* Physical channel number */
+        unsigned int chan;              /* DMAC channel number */
        unsigned int vchan;             /* Virtual channel number */
        unsigned int mode;
        unsigned int count;
        unsigned long sar;
        unsigned long dar;
+        const char **caps;
        unsigned long flags;
        atomic_t busy;
-        struct semaphore sem;
        wait_queue_head_t wait_queue;
        struct sys_device dev;
-        char *name;
+        void *priv_data;
 };
 struct dma_info {
@@ -103,6 +109,12 @@ struct dma_info {
        struct dma_channel *channels;
        struct list_head list;
+        int first_channel_nr;
+};
+struct dma_chan_caps {
+        int ch_num;
+        const char **caplist;
 };
 #define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
@@ -121,6 +133,8 @@ extern int dma_xfer(unsigned int chan, unsigned long from,
 #define dma_read_page(chan, from, to)   \
        dma_read(chan, from, to, PAGE_SIZE)
+extern int request_dma_bycap(const char **dmac, const char **caps,
+                             const char *dev_id);
 extern int request_dma(unsigned int chan, const char *dev_id);
 extern void free_dma(unsigned int chan);
 extern int get_dma_residue(unsigned int chan);
@@ -131,6 +145,10 @@ extern void dma_configure_channel(unsigned int chan, unsigned long flags);
 extern int register_dmac(struct dma_info *info);
 extern void unregister_dmac(struct dma_info *info);
+extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
+extern int dma_extend(unsigned int chan, unsigned long op, void *param);
+extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
 #ifdef CONFIG_SYSFS
 /* arch/sh/drivers/dma/dma-sysfs.c */
diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h
index fc050fd7645e..43ca244564b1 100644
--- a/include/asm-sh/elf.h
+++ b/include/asm-sh/elf.h
@@ -74,7 +74,7 @@ typedef struct user_fpu_struct elf_fpregset_t;
 #define ELF_ARCH        EM_SH
 #define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
   use of this is to invoke "./ld.so someprog" to test out a new version of
diff --git a/include/asm-sh/entry-macros.S b/include/asm-sh/entry-macros.S
new file mode 100644
index 000000000000..500030eae7aa
--- /dev/null
+++ b/include/asm-sh/entry-macros.S
@@ -0,0 +1,33 @@
+! entry.S macro define
+        
+        .macro  cli
+        stc     sr, r0
+        or      #0xf0, r0
+        ldc     r0, sr
+        .endm
+        .macro  sti
+        mov     #0xf0, r11
+        extu.b  r11, r11
+        not     r11, r11
+        stc     sr, r10
+        and     r11, r10
+#ifdef CONFIG_HAS_SR_RB
+        stc     k_g_imask, r11
+        or      r11, r10
+#endif
+        ldc     r10, sr
+        .endm
+        .macro  get_current_thread_info, ti, tmp
+#ifdef CONFIG_HAS_SR_RB
+        stc     r7_bank, \ti
+#else
+        mov     #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
+        shll8   \tmp
+        shll2   \tmp
+        mov     r15, \ti
+        and     \tmp, \ti
+#endif  
+        .endm
diff --git a/include/asm-sh/irq-sh73180.h b/include/asm-sh/irq-sh73180.h
deleted file mode 100644
index b28af9a69d72..000000000000
--- a/include/asm-sh/irq-sh73180.h
+++ /dev/null
@@ -1,314 +0,0 @@
-#ifndef __ASM_SH_IRQ_SH73180_H
-#define __ASM_SH_IRQ_SH73180_H
-/*
- * linux/include/asm-sh/irq-sh73180.h
- *
- * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
- */
-#undef INTC_IPRA
-#undef INTC_IPRB
-#undef INTC_IPRC
-#undef INTC_IPRD
-#undef DMTE0_IRQ
-#undef DMTE1_IRQ
-#undef DMTE2_IRQ
-#undef DMTE3_IRQ
-#undef DMTE4_IRQ
-#undef DMTE5_IRQ
-#undef DMTE6_IRQ
-#undef DMTE7_IRQ
-#undef DMAE_IRQ
-#undef DMA_IPR_ADDR
-#undef DMA_IPR_POS
-#undef DMA_PRIORITY
-#undef INTC_IMCR0
-#undef INTC_IMCR1
-#undef INTC_IMCR2
-#undef INTC_IMCR3
-#undef INTC_IMCR4
-#undef INTC_IMCR5
-#undef INTC_IMCR6
-#undef INTC_IMCR7
-#undef INTC_IMCR8
-#undef INTC_IMCR9
-#undef INTC_IMCR10
-#define INTC_IPRA       0xA4080000UL
-#define INTC_IPRB       0xA4080004UL
-#define INTC_IPRC       0xA4080008UL
-#define INTC_IPRD       0xA408000CUL
-#define INTC_IPRE       0xA4080010UL
-#define INTC_IPRF       0xA4080014UL
-#define INTC_IPRG       0xA4080018UL
-#define INTC_IPRH       0xA408001CUL
-#define INTC_IPRI       0xA4080020UL
-#define INTC_IPRJ       0xA4080024UL
-#define INTC_IPRK       0xA4080028UL
-#define INTC_IMR0       0xA4080080UL
-#define INTC_IMR1       0xA4080084UL
-#define INTC_IMR2       0xA4080088UL
-#define INTC_IMR3       0xA408008CUL
-#define INTC_IMR4       0xA4080090UL
-#define INTC_IMR5       0xA4080094UL
-#define INTC_IMR6       0xA4080098UL
-#define INTC_IMR7       0xA408009CUL
-#define INTC_IMR8       0xA40800A0UL
-#define INTC_IMR9       0xA40800A4UL
-#define INTC_IMR10      0xA40800A8UL
-#define INTC_IMR11      0xA40800ACUL
-#define INTC_IMCR0      0xA40800C0UL
-#define INTC_IMCR1      0xA40800C4UL
-#define INTC_IMCR2      0xA40800C8UL
-#define INTC_IMCR3      0xA40800CCUL
-#define INTC_IMCR4      0xA40800D0UL
-#define INTC_IMCR5      0xA40800D4UL
-#define INTC_IMCR6      0xA40800D8UL
-#define INTC_IMCR7      0xA40800DCUL
-#define INTC_IMCR8      0xA40800E0UL
-#define INTC_IMCR9      0xA40800E4UL
-#define INTC_IMCR10     0xA40800E8UL
-#define INTC_IMCR11     0xA40800ECUL
-#define INTC_ICR0       0xA4140000UL
-#define INTC_ICR1       0xA414001CUL
-#define INTMSK0         0xa4140044
-#define INTMSKCLR0      0xa4140064
-#define INTC_INTPRI0    0xa4140010
-/*
-  NOTE:
-  *_IRQ = (INTEVT2 - 0x200)/0x20
-*/
-/* TMU0 */
-#define TMU0_IRQ        16
-#define TMU0_IPR_ADDR   INTC_IPRA
-#define TMU0_IPR_POS     3
-#define TMU0_PRIORITY    2
-#define TIMER_IRQ       16
-#define TIMER_IPR_ADDR  INTC_IPRA
-#define TIMER_IPR_POS    3
-#define TIMER_PRIORITY   2
-/* TMU1 */
-#define TMU1_IRQ        17
-#define TMU1_IPR_ADDR   INTC_IPRA
-#define TMU1_IPR_POS     2
-#define TMU1_PRIORITY    2
-/* TMU2 */
-#define TMU2_IRQ        18
-#define TMU2_IPR_ADDR   INTC_IPRA
-#define TMU2_IPR_POS     1
-#define TMU2_PRIORITY    2
-/* LCDC */
-#define LCDC_IRQ        28
-#define LCDC_IPR_ADDR   INTC_IPRB
-#define LCDC_IPR_POS     2
-#define LCDC_PRIORITY    2
-/* VIO (Video I/O) */
-#define CEU_IRQ         52
-#define BEU_IRQ         53
-#define VEU_IRQ         54
-#define VOU_IRQ         55
-#define VIO_IPR_ADDR    INTC_IPRE
-#define VIO_IPR_POS      2
-#define VIO_PRIORITY     2
-/* MFI (Multi Functional Interface) */
-#define MFI_IRQ         56
-#define MFI_IPR_ADDR    INTC_IPRE
-#define MFI_IPR_POS      1
-#define MFI_PRIORITY     2
-/* VPU (Video Processing Unit) */
-#define VPU_IRQ         60
-#define VPU_IPR_ADDR    INTC_IPRE
-#define VPU_IPR_POS      0
-#define VPU_PRIORITY     2
-/* 3DG */
-#define TDG_IRQ         63
-#define TDG_IPR_ADDR    INTC_IPRJ
-#define TDG_IPR_POS      2
-#define TDG_PRIORITY     2
-/* DMAC(1) */
-#define DMTE0_IRQ       48
-#define DMTE1_IRQ       49
-#define DMTE2_IRQ       50
-#define DMTE3_IRQ       51
-#define DMA1_IPR_ADDR   INTC_IPRE
-#define DMA1_IPR_POS    3
-#define DMA1_PRIORITY   7
-/* DMAC(2) */
-#define DMTE4_IRQ       76
-#define DMTE5_IRQ       77
-#define DMA2_IPR_ADDR   INTC_IPRF
-#define DMA2_IPR_POS    2
-#define DMA2_PRIORITY   7
-/* SCIF0 */
-#define SCIF_ERI_IRQ    80
-#define SCIF_RXI_IRQ    81
-#define SCIF_BRI_IRQ    82
-#define SCIF_TXI_IRQ    83
-#define SCIF_IPR_ADDR   INTC_IPRG
-#define SCIF_IPR_POS    3
-#define SCIF_PRIORITY   3
-/* SIOF0 */
-#define SIOF0_IRQ       84
-#define SIOF0_IPR_ADDR  INTC_IPRH
-#define SIOF0_IPR_POS   3
-#define SIOF0_PRIORITY  3
-/* FLCTL (Flash Memory Controller) */
-#define FLSTE_IRQ       92
-#define FLTEND_IRQ      93
-#define FLTRQ0_IRQ      94
-#define FLTRQ1_IRQ      95
-#define FLCTL_IPR_ADDR  INTC_IPRH
-#define FLCTL_IPR_POS   1
-#define FLCTL_PRIORITY  3
-/* IIC(0) (IIC Bus Interface) */
-#define IIC0_ALI_IRQ    96
-#define IIC0_TACKI_IRQ  97
-#define IIC0_WAITI_IRQ  98
-#define IIC0_DTEI_IRQ   99
-#define IIC0_IPR_ADDR   INTC_IPRH
-#define IIC0_IPR_POS    0
-#define IIC0_PRIORITY   3
-/* IIC(1) (IIC Bus Interface) */
-#define IIC1_ALI_IRQ    44
-#define IIC1_TACKI_IRQ  45
-#define IIC1_WAITI_IRQ  46
-#define IIC1_DTEI_IRQ   47
-#define IIC1_IPR_ADDR   INTC_IPRG
-#define IIC1_IPR_POS    0
-#define IIC1_PRIORITY   3
-/* SIO0 */
-#define SIO0_IRQ        88
-#define SIO0_IPR_ADDR   INTC_IPRI
-#define SIO0_IPR_POS    3
-#define SIO0_PRIORITY   3
-/* SDHI */
-#define SDHI_SDHII0_IRQ 100
-#define SDHI_SDHII1_IRQ 101
-#define SDHI_SDHII2_IRQ 102
-#define SDHI_SDHII3_IRQ 103
-#define SDHI_IPR_ADDR   INTC_IPRK
-#define SDHI_IPR_POS    0
-#define SDHI_PRIORITY   3
-/* SIU (Sound Interface Unit) */
-#define SIU_IRQ         108
-#define SIU_IPR_ADDR    INTC_IPRJ
-#define SIU_IPR_POS     1
-#define SIU_PRIORITY    3
-#define PORT_PACR       0xA4050100UL
-#define PORT_PBCR       0xA4050102UL
-#define PORT_PCCR       0xA4050104UL
-#define PORT_PDCR       0xA4050106UL
-#define PORT_PECR       0xA4050108UL
-#define PORT_PFCR       0xA405010AUL
-#define PORT_PGCR       0xA405010CUL
-#define PORT_PHCR       0xA405010EUL
-#define PORT_PJCR       0xA4050110UL
-#define PORT_PKCR       0xA4050112UL
-#define PORT_PLCR       0xA4050114UL
-#define PORT_SCPCR      0xA4050116UL
-#define PORT_PMCR       0xA4050118UL
-#define PORT_PNCR       0xA405011AUL
-#define PORT_PQCR       0xA405011CUL
-#define PORT_PRCR       0xA405011EUL
-#define PORT_PTCR       0xA405014CUL
-#define PORT_PUCR       0xA405014EUL
-#define PORT_PVCR       0xA4050150UL
-#define PORT_PSELA      0xA4050140UL
-#define PORT_PSELB      0xA4050142UL
-#define PORT_PSELC      0xA4050144UL
-#define PORT_PSELE      0xA4050158UL
-#define PORT_HIZCRA     0xA4050146UL
-#define PORT_HIZCRB     0xA4050148UL
-#define PORT_DRVCR      0xA405014AUL
-#define PORT_PADR       0xA4050120UL
-#define PORT_PBDR       0xA4050122UL
-#define PORT_PCDR       0xA4050124UL
-#define PORT_PDDR       0xA4050126UL
-#define PORT_PEDR       0xA4050128UL
-#define PORT_PFDR       0xA405012AUL
-#define PORT_PGDR       0xA405012CUL
-#define PORT_PHDR       0xA405012EUL
-#define PORT_PJDR       0xA4050130UL
-#define PORT_PKDR       0xA4050132UL
-#define PORT_PLDR       0xA4050134UL
-#define PORT_SCPDR      0xA4050136UL
-#define PORT_PMDR       0xA4050138UL
-#define PORT_PNDR       0xA405013AUL
-#define PORT_PQDR       0xA405013CUL
-#define PORT_PRDR       0xA405013EUL
-#define PORT_PTDR       0xA405016CUL
-#define PORT_PUDR       0xA405016EUL
-#define PORT_PVDR       0xA4050170UL
-#define IRQ0_IRQ        32
-#define IRQ1_IRQ        33
-#define IRQ2_IRQ        34
-#define IRQ3_IRQ        35
-#define IRQ4_IRQ        36
-#define IRQ5_IRQ        37
-#define IRQ6_IRQ        38
-#define IRQ7_IRQ        39
-#define INTPRI00        0xA4140010UL
-#define IRQ0_IPR_ADDR   INTPRI00
-#define IRQ1_IPR_ADDR   INTPRI00
-#define IRQ2_IPR_ADDR   INTPRI00
-#define IRQ3_IPR_ADDR   INTPRI00
-#define IRQ4_IPR_ADDR   INTPRI00
-#define IRQ5_IPR_ADDR   INTPRI00
-#define IRQ6_IPR_ADDR   INTPRI00
-#define IRQ7_IPR_ADDR   INTPRI00
-#define IRQ0_IPR_POS    7
-#define IRQ1_IPR_POS    6
-#define IRQ2_IPR_POS    5
-#define IRQ3_IPR_POS    4
-#define IRQ4_IPR_POS    3
-#define IRQ5_IPR_POS    2
-#define IRQ6_IPR_POS    1
-#define IRQ7_IPR_POS    0
-#define IRQ0_PRIORITY   1
-#define IRQ1_PRIORITY   1
-#define IRQ2_PRIORITY   1
-#define IRQ3_PRIORITY   1
-#define IRQ4_PRIORITY   1
-#define IRQ5_PRIORITY   1
-#define IRQ6_PRIORITY   1
-#define IRQ7_PRIORITY   1
-#endif /* __ASM_SH_IRQ_SH73180_H */
diff --git a/include/asm-sh/irq-sh7343.h b/include/asm-sh/irq-sh7343.h
deleted file mode 100644
index 5d15419b53b0..000000000000
--- a/include/asm-sh/irq-sh7343.h
+++ /dev/null
@@ -1,317 +0,0 @@
-#ifndef __ASM_SH_IRQ_SH7343_H
-#define __ASM_SH_IRQ_SH7343_H
-/*
- * linux/include/asm-sh/irq-sh7343.h
- *
- * Copyright (C) 2006 Kenati Technologies Inc.
- * Andre Mccurdy <andre@kenati.com>
- * Ranjit Deshpande <ranjit@kenati.com>
- */
-#undef INTC_IPRA
-#undef INTC_IPRB
-#undef INTC_IPRC
-#undef INTC_IPRD
-#undef DMTE0_IRQ
-#undef DMTE1_IRQ
-#undef DMTE2_IRQ
-#undef DMTE3_IRQ
-#undef DMTE4_IRQ
-#undef DMTE5_IRQ
-#undef DMTE6_IRQ
-#undef DMTE7_IRQ
-#undef DMAE_IRQ
-#undef DMA_IPR_ADDR
-#undef DMA_IPR_POS
-#undef DMA_PRIORITY
-#undef INTC_IMCR0
-#undef INTC_IMCR1
-#undef INTC_IMCR2
-#undef INTC_IMCR3
-#undef INTC_IMCR4
-#undef INTC_IMCR5
-#undef INTC_IMCR6
-#undef INTC_IMCR7
-#undef INTC_IMCR8
-#undef INTC_IMCR9
-#undef INTC_IMCR10
-#define INTC_IPRA       0xA4080000UL
-#define INTC_IPRB       0xA4080004UL
-#define INTC_IPRC       0xA4080008UL
-#define INTC_IPRD       0xA408000CUL
-#define INTC_IPRE       0xA4080010UL
-#define INTC_IPRF       0xA4080014UL
-#define INTC_IPRG       0xA4080018UL
-#define INTC_IPRH       0xA408001CUL
-#define INTC_IPRI       0xA4080020UL
-#define INTC_IPRJ       0xA4080024UL
-#define INTC_IPRK       0xA4080028UL
-#define INTC_IPRL       0xA408002CUL
-#define INTC_IMR0       0xA4080080UL
-#define INTC_IMR1       0xA4080084UL
-#define INTC_IMR2       0xA4080088UL
-#define INTC_IMR3       0xA408008CUL
-#define INTC_IMR4       0xA4080090UL
-#define INTC_IMR5       0xA4080094UL
-#define INTC_IMR6       0xA4080098UL
-#define INTC_IMR7       0xA408009CUL
-#define INTC_IMR8       0xA40800A0UL
-#define INTC_IMR9       0xA40800A4UL
-#define INTC_IMR10      0xA40800A8UL
-#define INTC_IMR11      0xA40800ACUL
-#define INTC_IMCR0      0xA40800C0UL
-#define INTC_IMCR1      0xA40800C4UL
-#define INTC_IMCR2      0xA40800C8UL
-#define INTC_IMCR3      0xA40800CCUL
-#define INTC_IMCR4      0xA40800D0UL
-#define INTC_IMCR5      0xA40800D4UL
-#define INTC_IMCR6      0xA40800D8UL
-#define INTC_IMCR7      0xA40800DCUL
-#define INTC_IMCR8      0xA40800E0UL
-#define INTC_IMCR9      0xA40800E4UL
-#define INTC_IMCR10     0xA40800E8UL
-#define INTC_IMCR11     0xA40800ECUL
-#define INTC_ICR0       0xA4140000UL
-#define INTC_ICR1       0xA414001CUL
-#define INTMSK0         0xa4140044
-#define INTMSKCLR0      0xa4140064
-#define INTC_INTPRI0    0xa4140010
-/*
-  NOTE:
-  *_IRQ = (INTEVT2 - 0x200)/0x20
-*/
-/* TMU0 */
-#define TMU0_IRQ        16
-#define TMU0_IPR_ADDR   INTC_IPRA
-#define TMU0_IPR_POS     3
-#define TMU0_PRIORITY    2
-#define TIMER_IRQ       16
-#define TIMER_IPR_ADDR  INTC_IPRA
-#define TIMER_IPR_POS    3
-#define TIMER_PRIORITY   2
-/* TMU1 */
-#define TMU1_IRQ        17
-#define TMU1_IPR_ADDR   INTC_IPRA
-#define TMU1_IPR_POS     2
-#define TMU1_PRIORITY    2
-/* TMU2 */
-#define TMU2_IRQ        18
-#define TMU2_IPR_ADDR   INTC_IPRA
-#define TMU2_IPR_POS     1
-#define TMU2_PRIORITY    2
-/* LCDC */
-#define LCDC_IRQ        28
-#define LCDC_IPR_ADDR   INTC_IPRB
-#define LCDC_IPR_POS     2
-#define LCDC_PRIORITY    2
-/* VIO (Video I/O) */
-#define CEU_IRQ         52
-#define BEU_IRQ         53
-#define VEU_IRQ         54
-#define VOU_IRQ         55
-#define VIO_IPR_ADDR    INTC_IPRE
-#define VIO_IPR_POS      2
-#define VIO_PRIORITY     2
-/* MFI (Multi Functional Interface) */
-#define MFI_IRQ         56
-#define MFI_IPR_ADDR    INTC_IPRE
-#define MFI_IPR_POS      1
-#define MFI_PRIORITY     2
-/* VPU (Video Processing Unit) */
-#define VPU_IRQ         60
-#define VPU_IPR_ADDR    INTC_IPRE
-#define VPU_IPR_POS      0
-#define VPU_PRIORITY     2
-/* 3DG */
-#define TDG_IRQ         63
-#define TDG_IPR_ADDR    INTC_IPRJ
-#define TDG_IPR_POS      2
-#define TDG_PRIORITY     2
-/* DMAC(1) */
-#define DMTE0_IRQ       48
-#define DMTE1_IRQ       49
-#define DMTE2_IRQ       50
-#define DMTE3_IRQ       51
-#define DMA1_IPR_ADDR   INTC_IPRE
-#define DMA1_IPR_POS    3
-#define DMA1_PRIORITY   7
-/* DMAC(2) */
-#define DMTE4_IRQ       76
-#define DMTE5_IRQ       77
-#define DMA2_IPR_ADDR   INTC_IPRF
-#define DMA2_IPR_POS    2
-#define DMA2_PRIORITY   7
-/* SCIF0 */
-#define SCIF_ERI_IRQ    80
-#define SCIF_RXI_IRQ    81
-#define SCIF_BRI_IRQ    82
-#define SCIF_TXI_IRQ    83
-#define SCIF_IPR_ADDR   INTC_IPRG
-#define SCIF_IPR_POS    3
-#define SCIF_PRIORITY   3
-/* SIOF0 */
-#define SIOF0_IRQ       84
-#define SIOF0_IPR_ADDR  INTC_IPRH
-#define SIOF0_IPR_POS   3
-#define SIOF0_PRIORITY  3
-/* FLCTL (Flash Memory Controller) */
-#define FLSTE_IRQ       92
-#define FLTEND_IRQ      93
-#define FLTRQ0_IRQ      94
-#define FLTRQ1_IRQ      95
-#define FLCTL_IPR_ADDR  INTC_IPRH
-#define FLCTL_IPR_POS   1
-#define FLCTL_PRIORITY  3
-/* IIC(0) (IIC Bus Interface) */
-#define IIC0_ALI_IRQ    96
-#define IIC0_TACKI_IRQ  97
-#define IIC0_WAITI_IRQ  98
-#define IIC0_DTEI_IRQ   99
-#define IIC0_IPR_ADDR   INTC_IPRH
-#define IIC0_IPR_POS    0
-#define IIC0_PRIORITY   3
-/* IIC(1) (IIC Bus Interface) */
-#define IIC1_ALI_IRQ    44
-#define IIC1_TACKI_IRQ  45
-#define IIC1_WAITI_IRQ  46
-#define IIC1_DTEI_IRQ   47
-#define IIC1_IPR_ADDR   INTC_IPRI
-#define IIC1_IPR_POS    0
-#define IIC1_PRIORITY   3
-/* SIO0 */
-#define SIO0_IRQ        88
-#define SIO0_IPR_ADDR   INTC_IPRI
-#define SIO0_IPR_POS    3
-#define SIO0_PRIORITY   3
-/* SDHI */
-#define SDHI_SDHII0_IRQ 100
-#define SDHI_SDHII1_IRQ 101
-#define SDHI_SDHII2_IRQ 102
-#define SDHI_SDHII3_IRQ 103
-#define SDHI_IPR_ADDR   INTC_IPRK
-#define SDHI_IPR_POS    0
-#define SDHI_PRIORITY   3
-/* SIU (Sound Interface Unit) */
-#define SIU_IRQ         108
-#define SIU_IPR_ADDR    INTC_IPRJ
-#define SIU_IPR_POS     1
-#define SIU_PRIORITY    3
-#define PORT_PACR       0xA4050100UL
-#define PORT_PBCR       0xA4050102UL
-#define PORT_PCCR       0xA4050104UL
-#define PORT_PDCR       0xA4050106UL
-#define PORT_PECR       0xA4050108UL
-#define PORT_PFCR       0xA405010AUL
-#define PORT_PGCR       0xA405010CUL
-#define PORT_PHCR       0xA405010EUL
-#define PORT_PJCR       0xA4050110UL
-#define PORT_PKCR       0xA4050112UL
-#define PORT_PLCR       0xA4050114UL
-#define PORT_SCPCR      0xA4050116UL
-#define PORT_PMCR       0xA4050118UL
-#define PORT_PNCR       0xA405011AUL
-#define PORT_PQCR       0xA405011CUL
-#define PORT_PRCR       0xA405011EUL
-#define PORT_PTCR       0xA405014CUL
-#define PORT_PUCR       0xA405014EUL
-#define PORT_PVCR       0xA4050150UL
-#define PORT_PSELA      0xA4050140UL
-#define PORT_PSELB      0xA4050142UL
-#define PORT_PSELC      0xA4050144UL
-#define PORT_PSELE      0xA4050158UL
-#define PORT_HIZCRA     0xA4050146UL
-#define PORT_HIZCRB     0xA4050148UL
-#define PORT_DRVCR      0xA405014AUL
-#define PORT_PADR       0xA4050120UL
-#define PORT_PBDR       0xA4050122UL
-#define PORT_PCDR       0xA4050124UL
-#define PORT_PDDR       0xA4050126UL
-#define PORT_PEDR       0xA4050128UL
-#define PORT_PFDR       0xA405012AUL
-#define PORT_PGDR       0xA405012CUL
-#define PORT_PHDR       0xA405012EUL
-#define PORT_PJDR       0xA4050130UL
-#define PORT_PKDR       0xA4050132UL
-#define PORT_PLDR       0xA4050134UL
-#define PORT_SCPDR      0xA4050136UL
-#define PORT_PMDR       0xA4050138UL
-#define PORT_PNDR       0xA405013AUL
-#define PORT_PQDR       0xA405013CUL
-#define PORT_PRDR       0xA405013EUL
-#define PORT_PTDR       0xA405016CUL
-#define PORT_PUDR       0xA405016EUL
-#define PORT_PVDR       0xA4050170UL
-#define IRQ0_IRQ        32
-#define IRQ1_IRQ        33
-#define IRQ2_IRQ        34
-#define IRQ3_IRQ        35
-#define IRQ4_IRQ        36
-#define IRQ5_IRQ        37
-#define IRQ6_IRQ        38
-#define IRQ7_IRQ        39
-#define INTPRI00        0xA4140010UL
-#define IRQ0_IPR_ADDR   INTPRI00
-#define IRQ1_IPR_ADDR   INTPRI00
-#define IRQ2_IPR_ADDR   INTPRI00
-#define IRQ3_IPR_ADDR   INTPRI00
-#define IRQ4_IPR_ADDR   INTPRI00
-#define IRQ5_IPR_ADDR   INTPRI00
-#define IRQ6_IPR_ADDR   INTPRI00
-#define IRQ7_IPR_ADDR   INTPRI00
-#define IRQ0_IPR_POS    7
-#define IRQ1_IPR_POS    6
-#define IRQ2_IPR_POS    5
-#define IRQ3_IPR_POS    4
-#define IRQ4_IPR_POS    3
-#define IRQ5_IPR_POS    2
-#define IRQ6_IPR_POS    1
-#define IRQ7_IPR_POS    0
-#define IRQ0_PRIORITY   1
-#define IRQ1_PRIORITY   1
-#define IRQ2_PRIORITY   1
-#define IRQ3_PRIORITY   1
-#define IRQ4_PRIORITY   1
-#define IRQ5_PRIORITY   1
-#define IRQ6_PRIORITY   1
-#define IRQ7_PRIORITY   1
-#endif /* __ASM_SH_IRQ_SH7343_H */
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
deleted file mode 100644
index 19912ae6a7f7..000000000000
--- a/include/asm-sh/irq-sh7780.h
+++ /dev/null
@@ -1,311 +0,0 @@
-#ifndef __ASM_SH_IRQ_SH7780_H
-#define __ASM_SH_IRQ_SH7780_H
-/*
- * linux/include/asm-sh/irq-sh7780.h
- *
- * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
- */
-#define INTC_BASE       0xffd00000
-#define INTC_ICR0       (INTC_BASE+0x0)
-#define INTC_ICR1       (INTC_BASE+0x1c)
-#define INTC_INTPRI     (INTC_BASE+0x10)
-#define INTC_INTREQ     (INTC_BASE+0x24)
-#define INTC_INTMSK0    (INTC_BASE+0x44)
-#define INTC_INTMSK1    (INTC_BASE+0x48)
-#define INTC_INTMSK2    (INTC_BASE+0x40080)
-#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
-#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
-#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
-#define INTC_NMIFCR     (INTC_BASE+0xc0)
-#define INTC_USERIMASK  (INTC_BASE+0x30000)
-#define INTC_INT2PRI0   (INTC_BASE+0x40000)
-#define INTC_INT2PRI1   (INTC_BASE+0x40004)
-#define INTC_INT2PRI2   (INTC_BASE+0x40008)
-#define INTC_INT2PRI3   (INTC_BASE+0x4000c)
-#define INTC_INT2PRI4   (INTC_BASE+0x40010)
-#define INTC_INT2PRI5   (INTC_BASE+0x40014)
-#define INTC_INT2PRI6   (INTC_BASE+0x40018)
-#define INTC_INT2PRI7   (INTC_BASE+0x4001c)
-#define INTC_INT2A0     (INTC_BASE+0x40030)
-#define INTC_INT2A1     (INTC_BASE+0x40034)
-#define INTC_INT2MSKR   (INTC_BASE+0x40038)
-#define INTC_INT2MSKCR  (INTC_BASE+0x4003c)
-#define INTC_INT2B0     (INTC_BASE+0x40040)
-#define INTC_INT2B1     (INTC_BASE+0x40044)
-#define INTC_INT2B2     (INTC_BASE+0x40048)
-#define INTC_INT2B3     (INTC_BASE+0x4004c)
-#define INTC_INT2B4     (INTC_BASE+0x40050)
-#define INTC_INT2B5     (INTC_BASE+0x40054)
-#define INTC_INT2B6     (INTC_BASE+0x40058)
-#define INTC_INT2B7     (INTC_BASE+0x4005c)
-#define INTC_INT2GPIC   (INTC_BASE+0x40090)
-/*
-  NOTE:
-  *_IRQ = (INTEVT2 - 0x200)/0x20
-*/
-/* IRQ 0-7 line external int*/
-#define IRQ0_IRQ        2
-#define IRQ0_IPR_ADDR   INTC_INTPRI
-#define IRQ0_IPR_POS    7
-#define IRQ0_PRIORITY   2
-#define IRQ1_IRQ        4
-#define IRQ1_IPR_ADDR   INTC_INTPRI
-#define IRQ1_IPR_POS    6
-#define IRQ1_PRIORITY   2
-#define IRQ2_IRQ        6
-#define IRQ2_IPR_ADDR   INTC_INTPRI
-#define IRQ2_IPR_POS    5
-#define IRQ2_PRIORITY   2
-#define IRQ3_IRQ        8
-#define IRQ3_IPR_ADDR   INTC_INTPRI
-#define IRQ3_IPR_POS    4
-#define IRQ3_PRIORITY   2
-#define IRQ4_IRQ        10
-#define IRQ4_IPR_ADDR   INTC_INTPRI
-#define IRQ4_IPR_POS    3
-#define IRQ4_PRIORITY   2
-#define IRQ5_IRQ        12
-#define IRQ5_IPR_ADDR   INTC_INTPRI
-#define IRQ5_IPR_POS    2
-#define IRQ5_PRIORITY   2
-#define IRQ6_IRQ        14
-#define IRQ6_IPR_ADDR   INTC_INTPRI
-#define IRQ6_IPR_POS    1
-#define IRQ6_PRIORITY   2
-#define IRQ7_IRQ        0
-#define IRQ7_IPR_ADDR   INTC_INTPRI
-#define IRQ7_IPR_POS    0
-#define IRQ7_PRIORITY   2
-/* TMU */
-/* ch0 */
-#define TMU_IRQ         28
-#define TMU_IPR_ADDR    INTC_INT2PRI0
-#define TMU_IPR_POS     3
-#define TMU_PRIORITY    2
-#define TIMER_IRQ       28
-#define TIMER_IPR_ADDR  INTC_INT2PRI0
-#define TIMER_IPR_POS   3
-#define TIMER_PRIORITY  2
-/* ch 1*/
-#define TMU_CH1_IRQ             29
-#define TMU_CH1_IPR_ADDR        INTC_INT2PRI0
-#define TMU_CH1_IPR_POS         2
-#define TMU_CH1_PRIORITY        2
-#define TIMER1_IRQ      29
-#define TIMER1_IPR_ADDR INTC_INT2PRI0
-#define TIMER1_IPR_POS  2
-#define TIMER1_PRIORITY 2
-/* ch 2*/
-#define TMU_CH2_IRQ             30
-#define TMU_CH2_IPR_ADDR        INTC_INT2PRI0
-#define TMU_CH2_IPR_POS         1
-#define TMU_CH2_PRIORITY        2
-/* ch 2 Input capture */
-#define TMU_CH2IC_IRQ           31
-#define TMU_CH2IC_IPR_ADDR      INTC_INT2PRI0
-#define TMU_CH2IC_IPR_POS       0
-#define TMU_CH2IC_PRIORITY      2
-/* ch 3 */
-#define TMU_CH3_IRQ             96
-#define TMU_CH3_IPR_ADDR        INTC_INT2PRI1
-#define TMU_CH3_IPR_POS         3
-#define TMU_CH3_PRIORITY        2
-/* ch 4 */
-#define TMU_CH4_IRQ             97
-#define TMU_CH4_IPR_ADDR        INTC_INT2PRI1
-#define TMU_CH4_IPR_POS         2
-#define TMU_CH4_PRIORITY        2
-/* ch 5*/
-#define TMU_CH5_IRQ             98
-#define TMU_CH5_IPR_ADDR        INTC_INT2PRI1
-#define TMU_CH5_IPR_POS         1
-#define TMU_CH5_PRIORITY        2
-/* SCIF0 */
-#define SCIF0_ERI_IRQ   40
-#define SCIF0_RXI_IRQ   41
-#define SCIF0_BRI_IRQ   42
-#define SCIF0_TXI_IRQ   43
-#define SCIF0_IPR_ADDR  INTC_INT2PRI2
-#define SCIF0_IPR_POS   3
-#define SCIF0_PRIORITY  3
-/* SCIF1 */
-#define SCIF1_ERI_IRQ   76
-#define SCIF1_RXI_IRQ   77
-#define SCIF1_BRI_IRQ   78
-#define SCIF1_TXI_IRQ   79
-#define SCIF1_IPR_ADDR  INTC_INT2PRI2
-#define SCIF1_IPR_POS   2
-#define SCIF1_PRIORITY  3
-#define WDT_IRQ         27
-#define WDT_IPR_ADDR    INTC_INT2PRI2
-#define WDT_IPR_POS     1
-#define WDT_PRIORITY    2
-/* DMAC(0) */
-#define DMINT0_IRQ      34
-#define DMINT1_IRQ      35
-#define DMINT2_IRQ      36
-#define DMINT3_IRQ      37
-#define DMINT4_IRQ      44
-#define DMINT5_IRQ      45
-#define DMINT6_IRQ      46
-#define DMINT7_IRQ      47
-#define DMAE_IRQ        38
-#define DMA0_IPR_ADDR   INTC_INT2PRI3
-#define DMA0_IPR_POS    2
-#define DMA0_PRIORITY   7
-/* DMAC(1) */
-#define DMINT8_IRQ      92
-#define DMINT9_IRQ      93
-#define DMINT10_IRQ     94
-#define DMINT11_IRQ     95
-#define DMA1_IPR_ADDR   INTC_INT2PRI3
-#define DMA1_IPR_POS    1
-#define DMA1_PRIORITY   7
-#define DMTE0_IRQ       DMINT0_IRQ
-#define DMTE4_IRQ       DMINT4_IRQ
-#define DMA_IPR_ADDR    DMA0_IPR_ADDR
-#define DMA_IPR_POS     DMA0_IPR_POS
-#define DMA_PRIORITY    DMA0_PRIORITY
-/* CMT */
-#define CMT_IRQ         56
-#define CMT_IPR_ADDR    INTC_INT2PRI4
-#define CMT_IPR_POS     3
-#define CMT_PRIORITY    0
-/* HAC */
-#define HAC_IRQ         60
-#define HAC_IPR_ADDR    INTC_INT2PRI4
-#define HAC_IPR_POS     2
-#define CMT_PRIORITY    0
-/* PCIC(0) */
-#define PCIC0_IRQ       64
-#define PCIC0_IPR_ADDR  INTC_INT2PRI4
-#define PCIC0_IPR_POS   1
-#define PCIC0_PRIORITY  2
-/* PCIC(1) */
-#define PCIC1_IRQ       65
-#define PCIC1_IPR_ADDR  INTC_INT2PRI4
-#define PCIC1_IPR_POS   0
-#define PCIC1_PRIORITY  2
-/* PCIC(2) */
-#define PCIC2_IRQ       66
-#define PCIC2_IPR_ADDR  INTC_INT2PRI5
-#define PCIC2_IPR_POS   3
-#define PCIC2_PRIORITY  2
-/* PCIC(3) */
-#define PCIC3_IRQ       67
-#define PCIC3_IPR_ADDR  INTC_INT2PRI5
-#define PCIC3_IPR_POS   2
-#define PCIC3_PRIORITY  2
-/* PCIC(4) */
-#define PCIC4_IRQ       68
-#define PCIC4_IPR_ADDR  INTC_INT2PRI5
-#define PCIC4_IPR_POS   1
-#define PCIC4_PRIORITY  2
-/* PCIC(5) */
-#define PCICERR_IRQ     69
-#define PCICPWD3_IRQ    70
-#define PCICPWD2_IRQ    71
-#define PCICPWD1_IRQ    72
-#define PCICPWD0_IRQ    73
-#define PCIC5_IPR_ADDR  INTC_INT2PRI5
-#define PCIC5_IPR_POS   0
-#define PCIC5_PRIORITY  2
-/* SIOF */
-#define SIOF_IRQ        80
-#define SIOF_IPR_ADDR   INTC_INT2PRI6
-#define SIOF_IPR_POS    3
-#define SIOF_PRIORITY   3
-/* HSPI */
-#define HSPI_IRQ        84
-#define HSPI_IPR_ADDR   INTC_INT2PRI6
-#define HSPI_IPR_POS    2
-#define HSPI_PRIORITY   3
-/* MMCIF */
-#define MMCIF_FSTAT_IRQ 88
-#define MMCIF_TRAN_IRQ  89
-#define MMCIF_ERR_IRQ   90
-#define MMCIF_FRDY_IRQ  91
-#define MMCIF_IPR_ADDR  INTC_INT2PRI6
-#define MMCIF_IPR_POS   1
-#define HSPI_PRIORITY   3
-/* SSI */
-#define SSI_IRQ         100
-#define SSI_IPR_ADDR    INTC_INT2PRI6
-#define SSI_IPR_POS     0
-#define SSI_PRIORITY    3
-/* FLCTL */
-#define FLCTL_FLSTE_IRQ         104
-#define FLCTL_FLTEND_IRQ        105
-#define FLCTL_FLTRQ0_IRQ        106
-#define FLCTL_FLTRQ1_IRQ        107
-#define FLCTL_IPR_ADDR          INTC_INT2PRI7
-#define FLCTL_IPR_POS           3
-#define FLCTL_PRIORITY          3
-/* GPIO */
-#define GPIO0_IRQ       108
-#define GPIO1_IRQ       109
-#define GPIO2_IRQ       110
-#define GPIO3_IRQ       111
-#define GPIO_IPR_ADDR   INTC_INT2PRI7
-#define GPIO_IPR_POS    2
-#define GPIO_PRIORITY   3
-#define INTC_TMU0_MSK   0
-#define INTC_TMU3_MSK   1
-#define INTC_RTC_MSK    2
-#define INTC_SCIF0_MSK  3
-#define INTC_SCIF1_MSK  4
-#define INTC_WDT_MSK    5
-#define INTC_HUID_MSK   7
-#define INTC_DMAC0_MSK  8
-#define INTC_DMAC1_MSK  9
-#define INTC_CMT_MSK    12
-#define INTC_HAC_MSK    13
-#define INTC_PCIC0_MSK  14
-#define INTC_PCIC1_MSK  15
-#define INTC_PCIC2_MSK  16
-#define INTC_PCIC3_MSK  17
-#define INTC_PCIC4_MSK  18
-#define INTC_PCIC5_MSK  19
-#define INTC_SIOF_MSK   20
-#define INTC_HSPI_MSK   21
-#define INTC_MMCIF_MSK  22
-#define INTC_SSI_MSK    23
-#define INTC_FLCTL_MSK  24
-#define INTC_GPIO_MSK   25
-#endif /* __ASM_SH_IRQ_SH7780_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 6cd3e9e2a76a..fd576088e47e 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -1,233 +1,9 @@
 #ifndef __ASM_SH_IRQ_H
 #define __ASM_SH_IRQ_H
-/*
- *
- * linux/include/asm-sh/irq.h
- *
- * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
- * Copyright (C) 2000  Kazumoto Kojima
- * Copyright (C) 2003  Paul Mundt
- *
- */
 #include <asm/machvec.h>
 #include <asm/ptrace.h>         /* for pt_regs */
-#ifndef CONFIG_CPU_SUBTYPE_SH7780
-#define INTC_DMAC0_MSK  0
-#if defined(CONFIG_CPU_SH3)
-#define INTC_IPRA       0xfffffee2UL
-#define INTC_IPRB       0xfffffee4UL
-#elif defined(CONFIG_CPU_SH4)
-#define INTC_IPRA       0xffd00004UL
-#define INTC_IPRB       0xffd00008UL
-#define INTC_IPRC       0xffd0000cUL
-#define INTC_IPRD       0xffd00010UL
-#endif
-#define TIMER_IRQ       16
-#define TIMER_IPR_ADDR  INTC_IPRA
-#define TIMER_IPR_POS    3
-#define TIMER_PRIORITY   2
-#define TIMER1_IRQ      17
-#define TIMER1_IPR_ADDR INTC_IPRA
-#define TIMER1_IPR_POS   2
-#define TIMER1_PRIORITY  4
-#define RTC_IRQ         22
-#define RTC_IPR_ADDR    INTC_IPRA
-#define RTC_IPR_POS      0
-#define RTC_PRIORITY    TIMER_PRIORITY
-#if defined(CONFIG_CPU_SH3)
-#define DMTE0_IRQ       48
-#define DMTE1_IRQ       49
-#define DMTE2_IRQ       50
-#define DMTE3_IRQ       51
-#define DMA_IPR_ADDR    INTC_IPRE
-#define DMA_IPR_POS     3
-#define DMA_PRIORITY    7
-#if defined(CONFIG_CPU_SUBTYPE_SH7300)
-/* TMU2 */
-#define TIMER2_IRQ      18
-#define TIMER2_IPR_ADDR INTC_IPRA
-#define TIMER2_IPR_POS   1
-#define TIMER2_PRIORITY  2
-/* WDT */
-#define WDT_IRQ         27
-#define WDT_IPR_ADDR    INTC_IPRB
-#define WDT_IPR_POS      3
-#define WDT_PRIORITY     2
-/* SIM (SIM Card Module) */
-#define SIM_ERI_IRQ     23
-#define SIM_RXI_IRQ     24
-#define SIM_TXI_IRQ     25
-#define SIM_TEND_IRQ    26
-#define SIM_IPR_ADDR    INTC_IPRB
-#define SIM_IPR_POS      1
-#define SIM_PRIORITY     2
-/* VIO (Video I/O) */
-#define VIO_IRQ         52
-#define VIO_IPR_ADDR    INTC_IPRE
-#define VIO_IPR_POS      2
-#define VIO_PRIORITY     2
-/* MFI (Multi Functional Interface) */
-#define MFI_IRQ         56
-#define MFI_IPR_ADDR    INTC_IPRE
-#define MFI_IPR_POS      1
-#define MFI_PRIORITY     2
-/* VPU (Video Processing Unit) */
-#define VPU_IRQ         60
-#define VPU_IPR_ADDR    INTC_IPRE
-#define VPU_IPR_POS      0
-#define VPU_PRIORITY     2
-/* KEY (Key Scan Interface) */
-#define KEY_IRQ         79
-#define KEY_IPR_ADDR    INTC_IPRF
-#define KEY_IPR_POS      3
-#define KEY_PRIORITY     2
-/* CMT (Compare Match Timer) */
-#define CMT_IRQ         104
-#define CMT_IPR_ADDR    INTC_IPRF
-#define CMT_IPR_POS      0
-#define CMT_PRIORITY     2
-/* DMAC(1) */
-#define DMTE0_IRQ       48
-#define DMTE1_IRQ       49
-#define DMTE2_IRQ       50
-#define DMTE3_IRQ       51
-#define DMA1_IPR_ADDR   INTC_IPRE
-#define DMA1_IPR_POS    3
-#define DMA1_PRIORITY   7
-/* DMAC(2) */
-#define DMTE4_IRQ       76
-#define DMTE5_IRQ       77
-#define DMA2_IPR_ADDR   INTC_IPRF
-#define DMA2_IPR_POS    2
-#define DMA2_PRIORITY   7
-/* SIOF0 */
-#define SIOF0_IRQ       84
-#define SIOF0_IPR_ADDR  INTC_IPRH
-#define SIOF0_IPR_POS   3
-#define SIOF0_PRIORITY  3
-/* FLCTL (Flash Memory Controller) */
-#define FLSTE_IRQ       92
-#define FLTEND_IRQ      93
-#define FLTRQ0_IRQ      94
-#define FLTRQ1_IRQ      95
-#define FLCTL_IPR_ADDR  INTC_IPRH
-#define FLCTL_IPR_POS   1
-#define FLCTL_PRIORITY  3
-/* IIC (IIC Bus Interface) */
-#define IIC_ALI_IRQ     96
-#define IIC_TACKI_IRQ   97
-#define IIC_WAITI_IRQ   98
-#define IIC_DTEI_IRQ    99
-#define IIC_IPR_ADDR    INTC_IPRH
-#define IIC_IPR_POS     0
-#define IIC_PRIORITY    3
-/* SIO0 */
-#define SIO0_IRQ        88
-#define SIO0_IPR_ADDR   INTC_IPRI
-#define SIO0_IPR_POS    3
-#define SIO0_PRIORITY   3
-/* SIU (Sound Interface Unit) */
-#define SIU_IRQ         108
-#define SIU_IPR_ADDR    INTC_IPRJ
-#define SIU_IPR_POS     1
-#define SIU_PRIORITY    3
-#endif
-#elif defined(CONFIG_CPU_SH4)
-#define DMTE0_IRQ       34
-#define DMTE1_IRQ       35
-#define DMTE2_IRQ       36
-#define DMTE3_IRQ       37
-#define DMTE4_IRQ       44      /* 7751R only */
-#define DMTE5_IRQ       45      /* 7751R only */
-#define DMTE6_IRQ       46      /* 7751R only */
-#define DMTE7_IRQ       47      /* 7751R only */
-#define DMAE_IRQ        38
-#define DMA_IPR_ADDR    INTC_IPRC
-#define DMA_IPR_POS     2
-#define DMA_PRIORITY    7
-#endif
-#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
-    defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
-    defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
-#define SCI_ERI_IRQ     23
-#define SCI_RXI_IRQ     24
-#define SCI_TXI_IRQ     25
-#define SCI_IPR_ADDR    INTC_IPRB
-#define SCI_IPR_POS     1
-#define SCI_PRIORITY    3
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7300)
-#define SCIF0_IRQ       80
-#define SCIF0_IPR_ADDR  INTC_IPRG
-#define SCIF0_IPR_POS   3
-#define SCIF0_PRIORITY  3
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7706) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7707) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7709)
-#define SCIF_ERI_IRQ    56
-#define SCIF_RXI_IRQ    57
-#define SCIF_BRI_IRQ    58
-#define SCIF_TXI_IRQ    59
-#define SCIF_IPR_ADDR   INTC_IPRE
-#define SCIF_IPR_POS    1
-#define SCIF_PRIORITY   3
-#define IRDA_ERI_IRQ    52
-#define IRDA_RXI_IRQ    53
-#define IRDA_BRI_IRQ    54
-#define IRDA_TXI_IRQ    55
-#define IRDA_IPR_ADDR   INTC_IPRE
-#define IRDA_IPR_POS    2
-#define IRDA_PRIORITY   3
-#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
-      defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
-#define SCIF_ERI_IRQ    40
-#define SCIF_RXI_IRQ    41
-#define SCIF_BRI_IRQ    42
-#define SCIF_TXI_IRQ    43
-#define SCIF_IPR_ADDR   INTC_IPRC
-#define SCIF_IPR_POS    1
-#define SCIF_PRIORITY   3
-#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
-#define SCIF1_ERI_IRQ   23
-#define SCIF1_RXI_IRQ   24
-#define SCIF1_BRI_IRQ   25
-#define SCIF1_TXI_IRQ   26
-#define SCIF1_IPR_ADDR  INTC_IPRB
-#define SCIF1_IPR_POS   1
-#define SCIF1_PRIORITY  3
-#endif /* ST40STB1 */
-#endif /* 775x / SH4-202 / ST40STB1 */
-#endif /* 7780 */
 /* NR_IRQS is made from three components:
 *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
 *   2. PINT_NR_IRQS   - number of PINT interrupts
@@ -265,6 +41,10 @@
 # define ONCHIP_NR_IRQS 109
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 # define ONCHIP_NR_IRQS 111
+#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
+# define ONCHIP_NR_IRQS 256
+#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+# define ONCHIP_NR_IRQS 128
 #elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
 # define ONCHIP_NR_IRQS 144
 #endif
@@ -312,9 +92,11 @@
 /* NR_IRQS. 1+2+3 */
 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
-extern void disable_irq(unsigned int);
+/*
-extern void disable_irq_nosync(unsigned int);
+ * Convert back and forth between INTEVT and IRQ values.
-extern void enable_irq(unsigned int);
+ */
+#define evt2irq(evt)            (((evt) >> 5) - 16)
+#define irq2evt(irq)            (((irq) + 16) << 5)
 /*
 * Simple Mask Register Support
@@ -327,362 +109,36 @@ extern unsigned short *irq_mask_register;
 */
 void init_IRQ_pint(void);
+/*
+ * The shift value is now the number of bits to shift, not the number of
+ * bits/4. This is to make it easier to read the value directly from the
+ * datasheets. The IPR address, addr, will be set from ipr_idx via the
+ * map_ipridx_to_addr function.
+ */
 struct ipr_data {
        unsigned int irq;
-        unsigned int addr;      /* Address of Interrupt Priority Register */
+        int ipr_idx;            /* Index for the IPR registered */
-        int shift;              /* Shifts of the 16-bit data */
+        int shift;              /* Number of bits to shift the data */
        int priority;           /* The priority */
+        unsigned int addr;      /* Address of Interrupt Priority Register */
 };
 /*
- * Function for "on chip support modules".
+ * Given an IPR IDX, map the value to an IPR register address.
 */
-extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
+unsigned int map_ipridx_to_addr(int idx);
-extern void make_imask_irq(unsigned int irq);
-#if defined(CONFIG_CPU_SUBTYPE_SH7300)
-#undef INTC_IPRA
-#undef INTC_IPRB
-#define INTC_IPRA       0xA414FEE2UL
-#define INTC_IPRB       0xA414FEE4UL
-#define INTC_IPRC       0xA4140016UL
-#define INTC_IPRD       0xA4140018UL
-#define INTC_IPRE       0xA414001AUL
-#define INTC_IPRF       0xA4080000UL
-#define INTC_IPRG       0xA4080002UL
-#define INTC_IPRH       0xA4080004UL
-#define INTC_IPRI       0xA4080006UL
-#define INTC_IPRJ       0xA4080008UL
-#define INTC_IMR0       0xA4080040UL
-#define INTC_IMR1       0xA4080042UL
-#define INTC_IMR2       0xA4080044UL
-#define INTC_IMR3       0xA4080046UL
-#define INTC_IMR4       0xA4080048UL
-#define INTC_IMR5       0xA408004AUL
-#define INTC_IMR6       0xA408004CUL
-#define INTC_IMR7       0xA408004EUL
-#define INTC_IMR8       0xA4080050UL
-#define INTC_IMR9       0xA4080052UL
-#define INTC_IMR10      0xA4080054UL
-#define INTC_IMCR0      0xA4080060UL
-#define INTC_IMCR1      0xA4080062UL
-#define INTC_IMCR2      0xA4080064UL
-#define INTC_IMCR3      0xA4080066UL
-#define INTC_IMCR4      0xA4080068UL
-#define INTC_IMCR5      0xA408006AUL
-#define INTC_IMCR6      0xA408006CUL
-#define INTC_IMCR7      0xA408006EUL
-#define INTC_IMCR8      0xA4080070UL
-#define INTC_IMCR9      0xA4080072UL
-#define INTC_IMCR10     0xA4080074UL
-#define INTC_ICR0       0xA414FEE0UL
-#define INTC_ICR1       0xA4140010UL
-#define INTC_IRR0       0xA4140004UL
-#define PORT_PACR       0xA4050100UL
-#define PORT_PBCR       0xA4050102UL
-#define PORT_PCCR       0xA4050104UL
-#define PORT_PDCR       0xA4050106UL
-#define PORT_PECR       0xA4050108UL
-#define PORT_PFCR       0xA405010AUL
-#define PORT_PGCR       0xA405010CUL
-#define PORT_PHCR       0xA405010EUL
-#define PORT_PJCR       0xA4050110UL
-#define PORT_PKCR       0xA4050112UL
-#define PORT_PLCR       0xA4050114UL
-#define PORT_SCPCR      0xA4050116UL
-#define PORT_PMCR       0xA4050118UL
-#define PORT_PNCR       0xA405011AUL
-#define PORT_PQCR       0xA405011CUL
-#define PORT_PSELA      0xA4050140UL
-#define PORT_PSELB      0xA4050142UL
-#define PORT_PSELC      0xA4050144UL
-#define PORT_HIZCRA     0xA4050146UL
-#define PORT_HIZCRB     0xA4050148UL
-#define PORT_DRVCR      0xA4050150UL
-#define PORT_PADR       0xA4050120UL
-#define PORT_PBDR       0xA4050122UL
-#define PORT_PCDR       0xA4050124UL
-#define PORT_PDDR       0xA4050126UL
-#define PORT_PEDR       0xA4050128UL
-#define PORT_PFDR       0xA405012AUL
-#define PORT_PGDR       0xA405012CUL
-#define PORT_PHDR       0xA405012EUL
-#define PORT_PJDR       0xA4050130UL
-#define PORT_PKDR       0xA4050132UL
-#define PORT_PLDR       0xA4050134UL
-#define PORT_SCPDR      0xA4050136UL
-#define PORT_PMDR       0xA4050138UL
-#define PORT_PNDR       0xA405013AUL
-#define PORT_PQDR       0xA405013CUL
-#define IRQ0_IRQ        32
-#define IRQ1_IRQ        33
-#define IRQ2_IRQ        34
-#define IRQ3_IRQ        35
-#define IRQ4_IRQ        36
-#define IRQ5_IRQ        37
-#define IRQ0_IPR_ADDR   INTC_IPRC
-#define IRQ1_IPR_ADDR   INTC_IPRC
-#define IRQ2_IPR_ADDR   INTC_IPRC
-#define IRQ3_IPR_ADDR   INTC_IPRC
-#define IRQ4_IPR_ADDR   INTC_IPRD
-#define IRQ5_IPR_ADDR   INTC_IPRD
-#define IRQ0_IPR_POS    0
-#define IRQ1_IPR_POS    1
-#define IRQ2_IPR_POS    2
-#define IRQ3_IPR_POS    3
-#define IRQ4_IPR_POS    0
-#define IRQ5_IPR_POS    1
-#define IRQ0_PRIORITY   1
+/*
-#define IRQ1_PRIORITY   1
+ * Enable individual interrupt mode for external IPR IRQs.
-#define IRQ2_PRIORITY   1
+ */
-#define IRQ3_PRIORITY   1
+void ipr_irq_enable_irlm(void);
-#define IRQ4_PRIORITY   1
-#define IRQ5_PRIORITY   1
-extern int ipr_irq_demux(int irq);
-#define __irq_demux(irq) ipr_irq_demux(irq)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
-#define INTC_IPRA       0xfffffee2UL
-#define INTC_IPRB       0xfffffe60UL
-#define INTC_VCRA       0xfffffe62UL
-#define INTC_VCRB       0xfffffe64UL
-#define INTC_VCRC       0xfffffe66UL
-#define INTC_VCRD       0xfffffe68UL
-#define INTC_VCRWDT     0xfffffee4UL
-#define INTC_VCRDIV     0xffffff0cUL
-#define INTC_VCRDMA0    0xffffffa0UL
-#define INTC_VCRDMA1    0xffffffa8UL
-#define INTC_ICR        0xfffffee0UL
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7706) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7707) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7709) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7710)
-#define INTC_IRR0       0xa4000004UL
-#define INTC_IRR1       0xa4000006UL
-#define INTC_IRR2       0xa4000008UL
-#define INTC_ICR0       0xfffffee0UL
-#define INTC_ICR1       0xa4000010UL
-#define INTC_ICR2       0xa4000012UL
-#define INTC_INTER      0xa4000014UL
-#define INTC_IPRC       0xa4000016UL
-#define INTC_IPRD       0xa4000018UL
-#define INTC_IPRE       0xa400001aUL
-#if defined(CONFIG_CPU_SUBTYPE_SH7707)
-#define INTC_IPRF       0xa400001cUL
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
-#define INTC_IPRF       0xa4080000UL
-#define INTC_IPRG       0xa4080002UL
-#define INTC_IPRH       0xa4080004UL
-#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
-/* Interrupt Controller Registers */
-#undef INTC_IPRA
-#undef INTC_IPRB
-#define INTC_IPRA       0xA414FEE2UL
-#define INTC_IPRB       0xA414FEE4UL
-#define INTC_IPRF       0xA4080000UL
-#define INTC_IPRG       0xA4080002UL
-#define INTC_IPRH       0xA4080004UL
-#define INTC_IPRI       0xA4080006UL
-#undef INTC_ICR0
-#undef INTC_ICR1
-#define INTC_ICR0       0xA414FEE0UL
-#define INTC_ICR1       0xA4140010UL
-#define INTC_IRR0       0xa4000004UL
-#define INTC_IRR1       0xa4000006UL
-#define INTC_IRR2       0xa4000008UL
-#define INTC_IRR3       0xa400000AUL
-#define INTC_IRR4       0xa400000CUL
-#define INTC_IRR5       0xa4080020UL
-#define INTC_IRR7       0xa4080024UL
-#define INTC_IRR8       0xa4080026UL
-/* Interrupt numbers */
-#define TIMER2_IRQ      18
-#define TIMER2_IPR_ADDR INTC_IPRA
-#define TIMER2_IPR_POS   1
-#define TIMER2_PRIORITY  2
-/* WDT */
-#define WDT_IRQ         27
-#define WDT_IPR_ADDR    INTC_IPRB
-#define WDT_IPR_POS      3
-#define WDT_PRIORITY     2
-#define SCIF0_ERI_IRQ   52
-#define SCIF0_RXI_IRQ   53
-#define SCIF0_BRI_IRQ   54
-#define SCIF0_TXI_IRQ   55
-#define SCIF0_IPR_ADDR  INTC_IPRE
-#define SCIF0_IPR_POS   2
-#define SCIF0_PRIORITY  3
-#define DMTE4_IRQ       76
-#define DMTE5_IRQ       77
-#define DMA2_IPR_ADDR   INTC_IPRF
-#define DMA2_IPR_POS    2
-#define DMA2_PRIORITY   7
-#define IPSEC_IRQ       79
-#define IPSEC_IPR_ADDR  INTC_IPRF
-#define IPSEC_IPR_POS   3
-#define IPSEC_PRIORITY  3
-/* EDMAC */
-#define EDMAC0_IRQ      80
-#define EDMAC0_IPR_ADDR INTC_IPRG
-#define EDMAC0_IPR_POS  3
-#define EDMAC0_PRIORITY 3
-#define EDMAC1_IRQ      81
-#define EDMAC1_IPR_ADDR INTC_IPRG
-#define EDMAC1_IPR_POS  2
-#define EDMAC1_PRIORITY 3
-#define EDMAC2_IRQ      82
-#define EDMAC2_IPR_ADDR INTC_IPRG
-#define EDMAC2_IPR_POS  1
-#define EDMAC2_PRIORITY 3
-/* SIOF */
-#define SIOF0_ERI_IRQ   96
-#define SIOF0_TXI_IRQ   97
-#define SIOF0_RXI_IRQ   98
-#define SIOF0_CCI_IRQ   99
-#define SIOF0_IPR_ADDR  INTC_IPRH
-#define SIOF0_IPR_POS   0
-#define SIOF0_PRIORITY  7
-#define SIOF1_ERI_IRQ   100
-#define SIOF1_TXI_IRQ   101
-#define SIOF1_RXI_IRQ   102
-#define SIOF1_CCI_IRQ   103
-#define SIOF1_IPR_ADDR  INTC_IPRI
-#define SIOF1_IPR_POS   1
-#define SIOF1_PRIORITY  7
-#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
-#if defined(CONFIG_CPU_SUBTYPE_SH7710)
-#define PORT_PACR       0xa4050100UL
-#define PORT_PBCR       0xa4050102UL
-#define PORT_PCCR       0xa4050104UL
-#define PORT_PETCR      0xa4050106UL
-#define PORT_PADR       0xa4050120UL
-#define PORT_PBDR       0xa4050122UL
-#define PORT_PCDR       0xa4050124UL
-#else
-#define PORT_PACR       0xa4000100UL
-#define PORT_PBCR       0xa4000102UL
-#define PORT_PCCR       0xa4000104UL
-#define PORT_PFCR       0xa400010aUL
-#define PORT_PADR       0xa4000120UL
-#define PORT_PBDR       0xa4000122UL
-#define PORT_PCDR       0xa4000124UL
-#define PORT_PFDR       0xa400012aUL
-#endif
-#define IRQ0_IRQ        32
-#define IRQ1_IRQ        33
-#define IRQ2_IRQ        34
-#define IRQ3_IRQ        35
-#define IRQ4_IRQ        36
-#define IRQ5_IRQ        37
-#define IRQ0_IPR_ADDR   INTC_IPRC
-#define IRQ1_IPR_ADDR   INTC_IPRC
-#define IRQ2_IPR_ADDR   INTC_IPRC
-#define IRQ3_IPR_ADDR   INTC_IPRC
-#define IRQ4_IPR_ADDR   INTC_IPRD
-#define IRQ5_IPR_ADDR   INTC_IPRD
-#define IRQ0_IPR_POS    0
-#define IRQ1_IPR_POS    1
-#define IRQ2_IPR_POS    2
-#define IRQ3_IPR_POS    3
-#define IRQ4_IPR_POS    0
-#define IRQ5_IPR_POS    1
-#define IRQ0_PRIORITY   1
-#define IRQ1_PRIORITY   1
-#define IRQ2_PRIORITY   1
-#define IRQ3_PRIORITY   1
-#define IRQ4_PRIORITY   1
-#define IRQ5_PRIORITY   1
-#define PINT0_IRQ       40
-#define PINT8_IRQ       41
-#define PINT0_IPR_ADDR  INTC_IPRD
-#define PINT8_IPR_ADDR  INTC_IPRD
-#define PINT0_IPR_POS   3
-#define PINT8_IPR_POS   2
-#define PINT0_PRIORITY  2
-#define PINT8_PRIORITY  2
-extern int ipr_irq_demux(int irq);
-#define __irq_demux(irq) ipr_irq_demux(irq)
-#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
-#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
-    defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
-#define INTC_ICR        0xffd00000
-#define INTC_ICR_NMIL   (1<<15)
-#define INTC_ICR_MAI    (1<<14)
-#define INTC_ICR_NMIB   (1<<9)
-#define INTC_ICR_NMIE   (1<<8)
-#define INTC_ICR_IRLM   (1<<7)
-#endif
-#ifdef CONFIG_CPU_SUBTYPE_SH7780
-#include <asm/irq-sh7780.h>
-#endif
-/* SH with INTC2-style interrupts */
-#ifdef CONFIG_CPU_HAS_INTC2_IRQ
-#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
-#define INTC2_BASE      0xfe080000
-#define INTC2_FIRST_IRQ 64
-#define INTC2_INTREQ_OFFSET     0x20
-#define INTC2_INTMSK_OFFSET     0x40
-#define INTC2_INTMSKCLR_OFFSET  0x60
-#define NR_INTC2_IRQS   25
-#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
-#define INTC2_BASE      0xfe080000
-#define INTC2_FIRST_IRQ 48      /* INTEVT 0x800 */
-#define INTC2_INTREQ_OFFSET     0x20
-#define INTC2_INTMSK_OFFSET     0x40
-#define INTC2_INTMSKCLR_OFFSET  0x60
-#define NR_INTC2_IRQS   64
-#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
-#define INTC2_BASE      0xffd40000
-#define INTC2_FIRST_IRQ 21
-#define INTC2_INTMSK_OFFSET     (0x38)
-#define INTC2_INTMSKCLR_OFFSET  (0x3c)
-#define NR_INTC2_IRQS   60
-#endif
-#define INTC2_INTPRI_OFFSET     0x00
+/*
+ * Function for "on chip support modules".
+ */
+void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
+void make_imask_irq(unsigned int irq);
+void init_IRQ_ipr(void);
 struct intc2_data {
        unsigned short irq;
@@ -693,20 +149,14 @@ struct intc2_data {
 void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
 void init_IRQ_intc2(void);
-#endif
-extern int shmse_irq_demux(int irq);
 static inline int generic_irq_demux(int irq)
 {
        return irq;
 }
-#ifndef __irq_demux
-#define __irq_demux(irq)        (irq)
-#endif
 #define irq_canonicalize(irq)   (irq)
-#define irq_demux(irq)          __irq_demux(sh_mv.mv_irq_demux(irq))
+#define irq_demux(irq)          sh_mv.mv_irq_demux(irq)
 #ifdef CONFIG_4KSTACKS
 extern void irq_ctx_init(int cpu);
@@ -717,12 +167,4 @@ extern void irq_ctx_exit(int cpu);
 # define irq_ctx_exit(cpu) do { } while (0)
 #endif
-#if defined(CONFIG_CPU_SUBTYPE_SH73180)
-#include <asm/irq-sh73180.h>
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7343)
-#include <asm/irq-sh7343.h>
-#endif
 #endif /* __ASM_SH_IRQ_H */
diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h
new file mode 100644
index 000000000000..9dedc1b693e3
--- /dev/null
+++ b/include/asm-sh/irqflags.h
@@ -0,0 +1,123 @@
+#ifndef __ASM_SH_IRQFLAGS_H
+#define __ASM_SH_IRQFLAGS_H
+static inline void raw_local_irq_enable(void)
+{
+        unsigned long __dummy0, __dummy1;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    %1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+                "stc    r6_bank, %1\n\t"
+                "or     %1, %0\n\t"
+#endif
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "1" (~0x000000f0)
+                : "memory"
+        );
+}
+static inline void raw_local_irq_disable(void)
+{
+        unsigned long flags;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "or     #0xf0, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&z" (flags)
+                : /* no inputs */
+                : "memory"
+        );
+}
+static inline void set_bl_bit(void)
+{
+        unsigned long __dummy0, __dummy1;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "or     %2, %0\n\t"
+                "and    %3, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "r" (0x10000000), "r" (0xffffff0f)
+                : "memory"
+        );
+}
+static inline void clear_bl_bit(void)
+{
+        unsigned long __dummy0, __dummy1;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    %2, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "1" (~0x10000000)
+                : "memory"
+        );
+}
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long flags;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    #0xf0, %0\n\t"
+                : "=&z" (flags)
+                : /* no inputs */
+                : "memory"
+        );
+        return flags;
+}
+#define raw_local_save_flags(flags) \
+                do { (flags) = __raw_local_save_flags(); } while (0)
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags != 0);
+}
+static inline int raw_irqs_disabled(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+        return raw_irqs_disabled_flags(flags);
+}
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long flags, __dummy;
+        __asm__ __volatile__ (
+                "stc    sr, %1\n\t"
+                "mov    %1, %0\n\t"
+                "or     #0xf0, %0\n\t"
+                "ldc    %0, sr\n\t"
+                "mov    %1, %0\n\t"
+                "and    #0xf0, %0\n\t"
+                : "=&z" (flags), "=&r" (__dummy)
+                : /* no inputs */
+                : "memory"
+        );
+        return flags;
+}
+#define raw_local_irq_save(flags) \
+                do { (flags) = __raw_local_irq_save(); } while (0)
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        if ((flags & 0xf0) != 0xf0)
+                raw_local_irq_enable();
+}
+#endif /* __ASM_SH_IRQFLAGS_H */
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index c7088efe579a..46f04e23bd45 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -10,7 +10,6 @@
 #include <asm/cpu/mmu_context.h>
 #include <asm/tlbflush.h>
-#include <asm/pgalloc.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
@@ -42,10 +41,8 @@ extern unsigned long mmu_context_cache;
 /*
 * Get MMU context if needed.
 */
-static __inline__ void
+static inline void get_mmu_context(struct mm_struct *mm)
-get_mmu_context(struct mm_struct *mm)
 {
-        extern void flush_tlb_all(void);
        unsigned long mc = mmu_context_cache;
        /* Check if we have old version of context. */
@@ -61,6 +58,7 @@ get_mmu_context(struct mm_struct *mm)
                 * Flush all TLB and start new cycle.
                 */
                flush_tlb_all();
                /*
                 * Fix version; Note that we avoid version #0
                 * to distingush NO_CONTEXT.
@@ -75,11 +73,10 @@ get_mmu_context(struct mm_struct *mm)
 * Initialize the context related info for a new mm_struct
 * instance.
 */
-static __inline__ int init_new_context(struct task_struct *tsk,
+static inline int init_new_context(struct task_struct *tsk,
                                       struct mm_struct *mm)
 {
        mm->context.id = NO_CONTEXT;
        return 0;
 }
@@ -87,12 +84,12 @@ static __inline__ int init_new_context(struct task_struct *tsk,
 * Destroy context related info for an mm_struct that is about
 * to be put to rest.
 */
-static __inline__ void destroy_context(struct mm_struct *mm)
+static inline void destroy_context(struct mm_struct *mm)
 {
        /* Do nothing */
 }
-static __inline__ void set_asid(unsigned long asid)
+static inline void set_asid(unsigned long asid)
 {
        unsigned long __dummy;
@@ -105,7 +102,7 @@ static __inline__ void set_asid(unsigned long asid)
                                "r" (0xffffff00));
 }
-static __inline__ unsigned long get_asid(void)
+static inline unsigned long get_asid(void)
 {
        unsigned long asid;
@@ -120,24 +117,29 @@ static __inline__ unsigned long get_asid(void)
 * After we have set current->mm to a new value, this activates
 * the context for the new mm so we see the new mappings.
 */
-static __inline__ void activate_context(struct mm_struct *mm)
+static inline void activate_context(struct mm_struct *mm)
 {
        get_mmu_context(mm);
        set_asid(mm->context.id & MMU_CONTEXT_ASID_MASK);
 }
-/* MMU_TTB can be used for optimizing the fault handling.
+/* MMU_TTB is used for optimizing the fault handling. */
-   (Currently not used) */
+static inline void set_TTB(pgd_t *pgd)
-static __inline__ void switch_mm(struct mm_struct *prev,
-                                 struct mm_struct *next,
-                                 struct task_struct *tsk)
 {
-        if (likely(prev != next)) {
+        ctrl_outl((unsigned long)pgd, MMU_TTB);
-                unsigned long __pgdir = (unsigned long)next->pgd;
+}
-                __asm__ __volatile__("mov.l     %0, %1"
+static inline pgd_t *get_TTB(void)
-                                     : /* no output */
+{
-                                     : "r" (__pgdir), "m" (__m(MMU_TTB)));
+        return (pgd_t *)ctrl_inl(MMU_TTB);
+}
+static inline void switch_mm(struct mm_struct *prev,
+                             struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        if (likely(prev != next)) {
+                set_TTB(next->pgd);
                activate_context(next);
        }
 }
@@ -147,7 +149,7 @@ static __inline__ void switch_mm(struct mm_struct *prev,
 #define activate_mm(prev, next) \
        switch_mm((prev),(next),NULL)
-static __inline__ void
+static inline void
 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 }
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index ca8b26d90475..380fd62dd05a 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -13,9 +13,16 @@
   [ P4 control   ]             0xE0000000
 */
 /* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT      12
+#if defined(CONFIG_PAGE_SIZE_4KB)
+# define PAGE_SHIFT     12
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+# define PAGE_SHIFT     13
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+# define PAGE_SHIFT     16
+#else
+# error "Bogus kernel page size?"
+#endif
 #ifdef __ASSEMBLY__
 #define PAGE_SIZE       (1 << PAGE_SHIFT)
@@ -28,8 +35,14 @@
 #if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
 #define HPAGE_SHIFT     16
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
+#define HPAGE_SHIFT     18
 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
 #define HPAGE_SHIFT     20
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define HPAGE_SHIFT     22
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
+#define HPAGE_SHIFT     26
 #endif
 #ifdef CONFIG_HUGETLB_PAGE
@@ -69,15 +82,25 @@ extern void __copy_user_page(void *to, void *from, void *orig_to);
 /*
 * These are used to make use of C type-checking..
 */
-typedef struct { unsigned long pte; } pte_t;
+#ifdef CONFIG_X2TLB
-typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long pte_low, pte_high; } pte_t;
+typedef struct { unsigned long long pgprot; } pgprot_t;
+#define pte_val(x) \
+        ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+#define __pte(x) \
+        ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
+#else
+typedef struct { unsigned long pte_low; } pte_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
+#define pte_val(x)      ((x).pte_low)
+#define __pte(x) ((pte_t) { (x) } )
+#endif
+typedef struct { unsigned long pgd; } pgd_t;
-#define pte_val(x)      ((x).pte)
 #define pgd_val(x)      ((x).pgd)
 #define pgprot_val(x)   ((x).pgprot)
-#define __pte(x) ((pte_t) { (x) } )
 #define __pgd(x) ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
diff --git a/include/asm-sh/pgalloc.h b/include/asm-sh/pgalloc.h
index e841465ab4d2..888e4529e6fe 100644
--- a/include/asm-sh/pgalloc.h
+++ b/include/asm-sh/pgalloc.h
@@ -1,13 +1,16 @@
 #ifndef __ASM_SH_PGALLOC_H
 #define __ASM_SH_PGALLOC_H
-#define pmd_populate_kernel(mm, pmd, pte) \
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
-                set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
+                                       pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
 static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
                                struct page *pte)
 {
-        set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
 }
 /*
@@ -15,7 +18,16 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 */
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-        return (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
+        pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT);
+        if (pgd) {
+                memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
+                memcpy(pgd + USER_PTRS_PER_PGD,
+                       swapper_pg_dir + USER_PTRS_PER_PGD,
+                       (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+        }
+        return pgd;
 }
 static inline void pgd_free(pgd_t *pgd)
diff --git a/include/asm-sh/pgtable-2level.h b/include/asm-sh/pgtable-2level.h
deleted file mode 100644
index b525db6f61c6..000000000000
--- a/include/asm-sh/pgtable-2level.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef __ASM_SH_PGTABLE_2LEVEL_H
-#define __ASM_SH_PGTABLE_2LEVEL_H
-/*
- * traditional two-level paging structure:
- */
-#define PGDIR_SHIFT     22
-#define PTRS_PER_PGD    1024
-/*
- * this is two-level, so we don't really have any
- * PMD directory physically.
- */
-#define PMD_SHIFT       22
-#define PTRS_PER_PMD    1
-#define PTRS_PER_PTE    1024
-#ifndef __ASSEMBLY__
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd)           { return 0; }
-static inline int pgd_bad(pgd_t pgd)            { return 0; }
-static inline int pgd_present(pgd_t pgd)        { return 1; }
-static inline void pgd_clear (pgd_t * pgdp)     { }
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
-#define pgd_page_vaddr(pgd) \
-((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
-#define pgd_page(pgd) \
-        (phys_to_page(pgd_val(pgd)))
-static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
-        return (pmd_t *) dir;
-}
-#define pte_pfn(x)              ((unsigned long)(((x).pte >> PAGE_SHIFT)))
-#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#endif /* !__ASSEMBLY__ */
-#endif /* __ASM_SH_PGTABLE_2LEVEL_H */
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 2c8682ad1012..c84901dbd8e5 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -15,15 +15,10 @@
 #include <asm-generic/pgtable-nopmd.h>
 #include <asm/page.h>
-#define PTRS_PER_PGD            1024
 #ifndef __ASSEMBLY__
 #include <asm/addrspace.h>
 #include <asm/fixmap.h>
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-extern void paging_init(void);
 /*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
@@ -33,15 +28,28 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #endif /* !__ASSEMBLY__ */
-/* traditional two-level paging structure */
+/*
-#define PGDIR_SHIFT     22
+ * traditional two-level paging structure
-#define PTRS_PER_PMD    1
+ */
-#define PTRS_PER_PTE    1024
+/* PTE bits */
-#define PMD_SIZE        (1UL << PMD_SHIFT)
+#ifdef CONFIG_X2TLB
-#define PMD_MASK        (~(PMD_SIZE-1))
+# define PTE_MAGNITUDE  3       /* 64-bit PTEs on extended mode SH-X2 TLB */
-#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#else
+# define PTE_MAGNITUDE  2       /* 32-bit PTEs */
+#endif
+#define PTE_SHIFT       PAGE_SHIFT
+#define PTE_BITS        (PTE_SHIFT - PTE_MAGNITUDE)
+/* PGD bits */
+#define PGDIR_SHIFT     (PTE_SHIFT + PTE_BITS)
+#define PGDIR_BITS      (32 - PGDIR_SHIFT)
+#define PGDIR_SIZE      (1 << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
+/* Entries per level */
+#define PTRS_PER_PTE    (PAGE_SIZE / 4)
+#define PTRS_PER_PGD    (PAGE_SIZE / 4)
 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS      0
@@ -49,7 +57,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 /*
 * First 1MB map is used by fixed purpose.
- * Currently only 4-enty (16kB) is used (see arch/sh/mm/cache.c)
+ * Currently only 4-entry (16kB) is used (see arch/sh/mm/cache.c)
 */
 #define VMALLOC_START   (P3SEG+0x00100000)
 #define VMALLOC_END     (FIXADDR_START-2*PAGE_SIZE)
@@ -57,7 +65,8 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 /*
 * Linux PTEL encoding.
 *
- * Hardware and software bit definitions for the PTEL value:
+ * Hardware and software bit definitions for the PTEL value (see below for
+ * notes on SH-X2 MMUs and 64-bit PTEs):
 *
 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
 *
@@ -76,20 +85,57 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 *
 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future
 *   software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
+ *
+ * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
+ *
+ * SH-X2 MMUs and extended PTEs
+ *
+ * SH-X2 supports an extended mode TLB with split data arrays due to the
+ * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
+ * SZ bit placeholders still exist in data array 1, but are implemented as
+ * reserved bits, with the real logic existing in data array 2.
+ *
+ * The downside to this is that we can no longer fit everything in to a 32-bit
+ * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
+ * side, this gives us quite a few spare bits to play with for future usage.
 */
+/* Legacy and compat mode bits */
 #define _PAGE_WT        0x001           /* WT-bit on SH-4, 0 on SH-3 */
 #define _PAGE_HW_SHARED 0x002           /* SH-bit  : shared among processes */
 #define _PAGE_DIRTY     0x004           /* D-bit   : page changed */
 #define _PAGE_CACHABLE  0x008           /* C-bit   : cachable */
-#define _PAGE_SZ0       0x010           /* SZ0-bit : Size of page */
+#ifndef CONFIG_X2TLB
-#define _PAGE_RW        0x020           /* PR0-bit : write access allowed */
+# define _PAGE_SZ0      0x010           /* SZ0-bit : Size of page */
-#define _PAGE_USER      0x040           /* PR1-bit : user space access allowed */
+# define _PAGE_RW       0x020           /* PR0-bit : write access allowed */
-#define _PAGE_SZ1       0x080           /* SZ1-bit : Size of page (on SH-4) */
+# define _PAGE_USER     0x040           /* PR1-bit : user space access allowed*/
+# define _PAGE_SZ1      0x080           /* SZ1-bit : Size of page (on SH-4) */
+#endif
 #define _PAGE_PRESENT   0x100           /* V-bit   : page is valid */
 #define _PAGE_PROTNONE  0x200           /* software: if not present  */
 #define _PAGE_ACCESSED  0x400           /* software: page referenced */
 #define _PAGE_FILE      _PAGE_WT        /* software: pagecache or swap? */
+/* Extended mode bits */
+#define _PAGE_EXT_ESZ0          0x0010  /* ESZ0-bit: Size of page */
+#define _PAGE_EXT_ESZ1          0x0020  /* ESZ1-bit: Size of page */
+#define _PAGE_EXT_ESZ2          0x0040  /* ESZ2-bit: Size of page */
+#define _PAGE_EXT_ESZ3          0x0080  /* ESZ3-bit: Size of page */
+#define _PAGE_EXT_USER_EXEC     0x0100  /* EPR0-bit: User space executable */
+#define _PAGE_EXT_USER_WRITE    0x0200  /* EPR1-bit: User space writable */
+#define _PAGE_EXT_USER_READ     0x0400  /* EPR2-bit: User space readable */
+#define _PAGE_EXT_KERN_EXEC     0x0800  /* EPR3-bit: Kernel space executable */
+#define _PAGE_EXT_KERN_WRITE    0x1000  /* EPR4-bit: Kernel space writable */
+#define _PAGE_EXT_KERN_READ     0x2000  /* EPR5-bit: Kernel space readable */
+/* Wrapper for extended mode pgprot twiddling */
+#ifdef CONFIG_X2TLB
+# define _PAGE_EXT(x)           ((unsigned long long)(x) << 32)
+#else
+# define _PAGE_EXT(x)           (0)
+#endif
 /* software: moves to PTEA.TC (Timing Control) */
 #define _PAGE_PCC_AREA5 0x00000000      /* use BSC registers for area5 */
 #define _PAGE_PCC_AREA6 0x80000000      /* use BSC registers for area6 */
@@ -114,37 +160,160 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #define _PAGE_FLAGS_HARDWARE_MASK       (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
-/* Hardware flags: SZ0=1 (4k-byte) */
+/* Hardware flags, page size encoding */
-#define _PAGE_FLAGS_HARD        _PAGE_SZ0
+#if defined(CONFIG_X2TLB)
+# if defined(CONFIG_PAGE_SIZE_4KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ0)
+# elif defined(CONFIG_PAGE_SIZE_8KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ1)
+# elif defined(CONFIG_PAGE_SIZE_64KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ2)
+# endif
+#else
+# if defined(CONFIG_PAGE_SIZE_4KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_SZ0
+# elif defined(CONFIG_PAGE_SIZE_64KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_SZ1
+# endif
+#endif
-#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#if defined(CONFIG_X2TLB)
-#define _PAGE_SZHUGE    (_PAGE_SZ1)
+# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2)
-#define _PAGE_SZHUGE    (_PAGE_SZ0 | _PAGE_SZ1)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ3)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
+# endif
+#else
+# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#  define _PAGE_SZHUGE  (_PAGE_SZ1)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_SZ0 | _PAGE_SZ1)
+# endif
+#endif
+/*
+ * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
+ * to make pte_mkhuge() happy.
+ */
+#ifndef _PAGE_SZHUGE
+# define _PAGE_SZHUGE   (_PAGE_FLAGS_HARD)
 #endif
-#define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
+#define _PAGE_CHG_MASK \
-#define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
+        (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
-#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
 #ifndef __ASSEMBLY__
-#ifdef CONFIG_MMU
+#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
-#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
-#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
-#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
-#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
-#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_READ | \
+                                           _PAGE_EXT_USER_WRITE))
+#define PAGE_EXECREAD   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_EXEC | \
+                                           _PAGE_EXT_USER_READ))
+#define PAGE_COPY       PAGE_EXECREAD
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_READ))
+#define PAGE_WRITEONLY  __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_WRITE))
+#define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_WRITE | \
+                                           _PAGE_EXT_USER_READ  | \
+                                           _PAGE_EXT_USER_EXEC))
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC))
 #define PAGE_KERNEL_NOCACHE \
-                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
-#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+                                 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
+                                 _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC))
+#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_EXEC))
+#define PAGE_KERNEL_PCC(slot, type) \
+                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC) \
+                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
+                                 (type))
+#elif defined(CONFIG_MMU) /* SH-X TLB */
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
+                                 _PAGE_CACHABLE | _PAGE_ACCESSED | \
+                                 _PAGE_FLAGS_HARD)
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_EXECREAD   PAGE_READONLY
+#define PAGE_RWX        PAGE_SHARED
+#define PAGE_WRITEONLY  PAGE_SHARED
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+#define PAGE_KERNEL_NOCACHE \
+                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
+                                 _PAGE_FLAGS_HARD)
+#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
 #define PAGE_KERNEL_PCC(slot, type) \
-                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_FLAGS_HARD | (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | (type))
+                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
+                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
+                                 (type))
 #else /* no mmu */
 #define PAGE_NONE               __pgprot(0)
 #define PAGE_SHARED             __pgprot(0)
 #define PAGE_COPY               __pgprot(0)
+#define PAGE_EXECREAD           __pgprot(0)
+#define PAGE_RWX                __pgprot(0)
 #define PAGE_READONLY           __pgprot(0)
+#define PAGE_WRITEONLY          __pgprot(0)
 #define PAGE_KERNEL             __pgprot(0)
 #define PAGE_KERNEL_NOCACHE     __pgprot(0)
 #define PAGE_KERNEL_RO          __pgprot(0)
@@ -154,27 +323,32 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #endif /* __ASSEMBLY__ */
 /*
- * As i386 and MIPS, SuperH can't do page protection for execute, and
+ * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
- * considers that the same as a read.  Also, write permissions imply
+ * protection for execute, and considers it the same as a read. Also, write
- * read permissions. This is the closest we can get..
+ * permission implies read permission. This is the closest we can get..
+ *
+ * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
+ * not only supporting separate execute, read, and write bits, but having
+ * completely separate permission bits for user and kernel space.
 */
+         /*xwr*/
 #define __P000  PAGE_NONE
 #define __P001  PAGE_READONLY
 #define __P010  PAGE_COPY
 #define __P011  PAGE_COPY
-#define __P100  PAGE_READONLY
+#define __P100  PAGE_EXECREAD
-#define __P101  PAGE_READONLY
+#define __P101  PAGE_EXECREAD
 #define __P110  PAGE_COPY
 #define __P111  PAGE_COPY
 #define __S000  PAGE_NONE
 #define __S001  PAGE_READONLY
-#define __S010  PAGE_SHARED
+#define __S010  PAGE_WRITEONLY
 #define __S011  PAGE_SHARED
-#define __S100  PAGE_READONLY
+#define __S100  PAGE_EXECREAD
-#define __S101  PAGE_READONLY
+#define __S101  PAGE_EXECREAD
-#define __S110  PAGE_SHARED
+#define __S110  PAGE_RWX
-#define __S111  PAGE_SHARED
+#define __S111  PAGE_RWX
 #ifndef __ASSEMBLY__
@@ -183,7 +357,17 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
+#ifdef CONFIG_X2TLB
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+        ptep->pte_high = pte.pte_high;
+        smp_wmb();
+        ptep->pte_low = pte.pte_low;
+}
+#else
 #define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#endif
 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
 /*
@@ -192,18 +376,18 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 */
 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define pte_pfn(x)              ((unsigned long)(((x).pte >> PAGE_SHIFT)))
+#define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #define pte_none(x)     (!pte_val(x))
 #define pte_present(x)  (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
-#define pte_clear(mm,addr,xp)   do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
+#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
 #define pmd_none(x)     (!pmd_val(x))
-#define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
+#define pmd_present(x)  (pmd_val(x))
 #define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
+#define pmd_bad(x)      (pmd_val(x) & ~PAGE_MASK)
 #define pages_to_mb(x)  ((x) >> (20-PAGE_SHIFT))
 #define pte_page(x)     phys_to_page(pte_val(x)&PTE_PHYS_MASK)
@@ -212,28 +396,52 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
-static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
+#define pte_not_present(pte)    (!(pte_val(pte) & _PAGE_PRESENT))
-static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
+#define pte_dirty(pte)          (pte_val(pte) & _PAGE_DIRTY)
-static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; }
+#define pte_young(pte)          (pte_val(pte) & _PAGE_ACCESSED)
-static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; }
+#define pte_file(pte)           (pte_val(pte) & _PAGE_FILE)
-static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
-static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_RW; }
+#ifdef CONFIG_X2TLB
-static inline int pte_not_present(pte_t pte){ return !(pte_val(pte) & _PAGE_PRESENT); }
+#define pte_read(pte)           ((pte).pte_high & _PAGE_EXT_USER_READ)
+#define pte_exec(pte)           ((pte).pte_high & _PAGE_EXT_USER_EXEC)
-static inline pte_t pte_rdprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
+#define pte_write(pte)          ((pte).pte_high & _PAGE_EXT_USER_WRITE)
-static inline pte_t pte_exprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
+#else
-static inline pte_t pte_mkclean(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
+#define pte_read(pte)           (pte_val(pte) & _PAGE_USER)
-static inline pte_t pte_mkold(pte_t pte)        { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
+#define pte_exec(pte)           (pte_val(pte) & _PAGE_USER)
-static inline pte_t pte_wrprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; }
+#define pte_write(pte)          (pte_val(pte) & _PAGE_RW)
-static inline pte_t pte_mkread(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
-static inline pte_t pte_mkexec(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
-static inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
-static inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
-static inline pte_t pte_mkwrite(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
-#ifdef CONFIG_HUGETLB_PAGE
-static inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
 #endif
+#define PTE_BIT_FUNC(h,fn,op) \
+static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
+#ifdef CONFIG_X2TLB
+/*
+ * We cheat a bit in the SH-X2 TLB case. As the permission bits are
+ * individually toggled (and user permissions are entirely decoupled from
+ * kernel permissions), we attempt to couple them a bit more sanely here.
+ */
+PTE_BIT_FUNC(high, rdprotect, &= ~_PAGE_EXT_USER_READ);
+PTE_BIT_FUNC(high, mkread, |= _PAGE_EXT_USER_READ | _PAGE_EXT_KERN_READ);
+PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
+PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
+PTE_BIT_FUNC(high, exprotect, &= ~_PAGE_EXT_USER_EXEC);
+PTE_BIT_FUNC(high, mkexec, |= _PAGE_EXT_USER_EXEC | _PAGE_EXT_KERN_EXEC);
+PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
+#else
+PTE_BIT_FUNC(low, rdprotect, &= ~_PAGE_USER);
+PTE_BIT_FUNC(low, mkread, |= _PAGE_USER);
+PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
+PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
+PTE_BIT_FUNC(low, exprotect, &= ~_PAGE_USER);
+PTE_BIT_FUNC(low, mkexec, |= _PAGE_USER);
+PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
+#endif
+PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
+PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
+PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
+PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
 /*
 * Macro and implementation to make a page protection as uncachable.
 */
@@ -258,13 +466,14 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
+{
+        set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) |
-#define pmd_page_vaddr(pmd) \
+                            pgprot_val(newprot)));
-((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+        return pte;
+}
-#define pmd_page(pmd) \
+#define pmd_page_vaddr(pmd)     pmd_val(pmd)
-        (phys_to_page(pmd_val(pmd)))
+#define pmd_page(pmd)           (virt_to_page(pmd_val(pmd)))
 /* to find an entry in a page-table-directory. */
 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
@@ -283,8 +492,15 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pte_unmap(pte)          do { } while (0)
 #define pte_unmap_nested(pte)   do { } while (0)
+#ifdef CONFIG_X2TLB
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
+               &(e), (e).pte_high, (e).pte_low)
+#else
 #define pte_ERROR(e) \
        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#endif
 #define pgd_ERROR(e) \
        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
@@ -337,6 +553,9 @@ extern unsigned int kobjsize(const void *objp);
 extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
 #endif
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern void paging_init(void);
 #include <asm-generic/pgtable.h>
 #endif /* !__ASSEMBLY__ */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 45bb74e35d32..6f1dd7ca1b1d 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -36,7 +36,10 @@
 */
 enum cpu_type {
        /* SH-2 types */
-        CPU_SH7604,
+        CPU_SH7604, CPU_SH7619,
+        /* SH-2A types */
+        CPU_SH7206,
        /* SH-3 types */
        CPU_SH7705, CPU_SH7706, CPU_SH7707,
@@ -47,7 +50,10 @@ enum cpu_type {
        /* SH-4 types */
        CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
        CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
+        /* SH-4A types */
        CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781,
+        CPU_SH7785,
        /* Unknown subtype */
        CPU_SH_NONE
@@ -130,12 +136,11 @@ union sh_fpu_union {
 };
 struct thread_struct {
+        /* Saved registers when thread is descheduled */
        unsigned long sp;
        unsigned long pc;
-        unsigned long trap_no, error_code;
+        /* Hardware debugging registers */
-        unsigned long address;
-        /* Hardware debugging registers may come here */
        unsigned long ubc_pc;
        /* floating point info */
@@ -150,12 +155,7 @@ typedef struct {
 extern int ubc_usercnt;
 #define INIT_THREAD  {                                          \
-        sizeof(init_stack) + (long) &init_stack, /* sp */       \
+        .sp = sizeof(init_stack) + (long) &init_stack,          \
-        0,                                       /* pc */       \
-        0, 0,                                                   \
-        0,                                                      \
-        0,                                                      \
-        {{{0,}},}                               /* fpu state */ \
 }
 /*
@@ -259,8 +259,8 @@ void show_trace(struct task_struct *tsk, unsigned long *sp,
                struct pt_regs *regs);
 extern unsigned long get_wchan(struct task_struct *p);
-#define KSTK_EIP(tsk)  ((tsk)->thread.pc)
+#define KSTK_EIP(tsk)  (task_pt_regs(tsk)->pc)
-#define KSTK_ESP(tsk)  ((tsk)->thread.sp)
+#define KSTK_ESP(tsk)  (task_pt_regs(tsk)->regs[15])
 #define cpu_sleep()     __asm__ __volatile__ ("sleep" : : : "memory")
 #define cpu_relax()     barrier()
diff --git a/include/asm-sh/push-switch.h b/include/asm-sh/push-switch.h
new file mode 100644
index 000000000000..dfc6bad567f0
--- /dev/null
+++ b/include/asm-sh/push-switch.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_SH_PUSH_SWITCH_H
+#define __ASM_SH_PUSH_SWITCH_H
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+struct push_switch {
+        /* switch state */
+        unsigned int            state:1;
+        /* debounce timer */
+        struct timer_list       debounce;
+        /* workqueue */
+        struct work_struct      work;
+};
+struct push_switch_platform_info {
+        /* IRQ handler */
+        irqreturn_t             (*irq_handler)(int irq, void *data);
+        /* Special IRQ flags */
+        unsigned int            irq_flags;
+        /* Bit location of switch */
+        unsigned int            bit;
+        /* Symbolic switch name */
+        const char              *name;
+};
+#endif /* __ASM_SH_PUSH_SWITCH_H */
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
index 9d2aea5e8488..4931ba817d73 100644
--- a/include/asm-sh/rwsem.h
+++ b/include/asm-sh/rwsem.h
@@ -25,11 +25,21 @@ struct rw_semaphore {
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
        spinlock_t              wait_lock;
        struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
 };
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
 #define __RWSEM_INITIALIZER(name) \
        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
-          LIST_HEAD_INIT((name).wait_list) }
+          LIST_HEAD_INIT((name).wait_list) \
+          __RWSEM_DEP_MAP_INIT(name) }
 #define DECLARE_RWSEM(name)             \
        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
@@ -39,6 +49,16 @@ extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
 extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
 extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+#define init_rwsem(sem)                         \
+do {                                            \
+        static struct lock_class_key __key;     \
+                                                \
+        __init_rwsem((sem), #sem, &__key);      \
+} while (0)
 static inline void init_rwsem(struct rw_semaphore *sem)
 {
        sem->count = RWSEM_UNLOCKED_VALUE;
@@ -141,6 +161,11 @@ static inline void __downgrade_write(struct rw_semaphore *sem)
                rwsem_downgrade_wake(sem);
 }
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        __down_write(sem);
+}
 /*
 * implement exchange and add functionality
 */
diff --git a/include/asm-sh/se7206.h b/include/asm-sh/se7206.h
new file mode 100644
index 000000000000..698eb80389ab
--- /dev/null
+++ b/include/asm-sh/se7206.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SH_SE7206_H
+#define __ASM_SH_SE7206_H
+#define PA_SMSC         0x30000000
+#define PA_MRSHPC       0x34000000
+#define PA_LED          0x31400000
+void init_se7206_IRQ(void);
+#define __IO_PREFIX     se7206
+#include <asm/io_generic.h>
+#endif /* __ASM_SH_SE7206_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 3340126f4e0f..b1e42e7f998b 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -6,6 +6,7 @@
 * Copyright (C) 2002 Paul Mundt
 */
+#include <linux/irqflags.h>
 #include <asm/types.h>
 /*
@@ -131,103 +132,6 @@ static inline unsigned long tas(volatile int *m)
 #define set_mb(var, value) do { xchg(&var, value); } while (0)
-/* Interrupt Control */
-#ifdef CONFIG_CPU_HAS_SR_RB
-static inline void local_irq_enable(void)
-{
-        unsigned long __dummy0, __dummy1;
-        __asm__ __volatile__("stc       sr, %0\n\t"
-                             "and       %1, %0\n\t"
-                             "stc       r6_bank, %1\n\t"
-                             "or        %1, %0\n\t"
-                             "ldc       %0, sr"
-                             : "=&r" (__dummy0), "=r" (__dummy1)
-                             : "1" (~0x000000f0)
-                             : "memory");
-}
-#else
-static inline void local_irq_enable(void)
-{
-        unsigned long __dummy0, __dummy1;
-        __asm__ __volatile__ (
-                "stc    sr, %0\n\t"
-                "and    %1, %0\n\t"
-                "ldc    %0, sr\n\t"
-                : "=&r" (__dummy0), "=r" (__dummy1)
-                : "1" (~0x000000f0)
-                : "memory");
-}
-#endif
-static inline void local_irq_disable(void)
-{
-        unsigned long __dummy;
-        __asm__ __volatile__("stc       sr, %0\n\t"
-                             "or        #0xf0, %0\n\t"
-                             "ldc       %0, sr"
-                             : "=&z" (__dummy)
-                             : /* no inputs */
-                             : "memory");
-}
-static inline void set_bl_bit(void)
-{
-        unsigned long __dummy0, __dummy1;
-        __asm__ __volatile__ ("stc      sr, %0\n\t"
-                             "or        %2, %0\n\t"
-                             "and       %3, %0\n\t"
-                             "ldc       %0, sr"
-                             : "=&r" (__dummy0), "=r" (__dummy1)
-                             : "r" (0x10000000), "r" (0xffffff0f)
-                             : "memory");
-}
-static inline void clear_bl_bit(void)
-{
-        unsigned long __dummy0, __dummy1;
-        __asm__ __volatile__ ("stc      sr, %0\n\t"
-                             "and       %2, %0\n\t"
-                             "ldc       %0, sr"
-                             : "=&r" (__dummy0), "=r" (__dummy1)
-                             : "1" (~0x10000000)
-                             : "memory");
-}
-#define local_save_flags(x) \
-        __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
-#define irqs_disabled()                 \
-({                                      \
-        unsigned long flags;            \
-        local_save_flags(flags);        \
-        (flags != 0);                   \
-})
-static inline unsigned long local_irq_save(void)
-{
-        unsigned long flags, __dummy;
-        __asm__ __volatile__("stc       sr, %1\n\t"
-                             "mov       %1, %0\n\t"
-                             "or        #0xf0, %0\n\t"
-                             "ldc       %0, sr\n\t"
-                             "mov       %1, %0\n\t"
-                             "and       #0xf0, %0"
-                             : "=&z" (flags), "=&r" (__dummy)
-                             :/**/
-                             : "memory" );
-        return flags;
-}
-#define local_irq_restore(x) do {                       \
-        if ((x & 0x000000f0) != 0x000000f0)             \
-                local_irq_enable();                     \
-} while (0)
 /*
 * Jump to P2 area.
 * When handling TLB or caches, we need to do it from P2 area.
@@ -264,9 +168,6 @@ do {							\
                : "=&r" (__dummy));                     \
 } while (0)
-/* For spinlocks etc */
-#define local_irq_save(x)       x = local_irq_save()
 static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
 {
        unsigned long flags, retval;
diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h
index 3ebc3f9039eb..0c01dc550819 100644
--- a/include/asm-sh/thread_info.h
+++ b/include/asm-sh/thread_info.h
@@ -90,13 +90,7 @@ static inline struct thread_info *current_thread_info(void)
 #endif
 #define free_thread_info(ti)    kfree(ti)
-#else /* !__ASSEMBLY__ */
+#endif /* __ASSEMBLY__ */
-/* how to get the thread information struct from ASM */
-#define GET_THREAD_INFO(reg) \
-        stc     r7_bank, reg
-#endif
 /*
 * thread information flags
diff --git a/include/asm-sh/timer.h b/include/asm-sh/timer.h
index 5df842bcf7b6..17b5e76a4c31 100644
--- a/include/asm-sh/timer.h
+++ b/include/asm-sh/timer.h
@@ -18,11 +18,32 @@ struct sys_timer {
        struct sys_device       dev;
        struct sys_timer_ops    *ops;
+#ifdef CONFIG_NO_IDLE_HZ
+        struct dyn_tick_timer   *dyn_tick;
+#endif
 };
+#ifdef CONFIG_NO_IDLE_HZ
+#define DYN_TICK_ENABLED        (1 << 1)
+struct dyn_tick_timer {
+        spinlock_t      lock;
+        unsigned int    state;                  /* Current state */
+        int             (*enable)(void);        /* Enables dynamic tick */
+        int             (*disable)(void);       /* Disables dynamic tick */
+        void            (*reprogram)(unsigned long); /* Reprograms the timer */
+        int             (*handler)(int, void *);
+};
+void timer_dyn_reprogram(void);
+#else
+#define timer_dyn_reprogram()   do { } while (0)
+#endif
 #define TICK_SIZE (tick_nsec / 1000)
-extern struct sys_timer tmu_timer;
+extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
 extern struct sys_timer *sys_timer;
 #ifndef CONFIG_GENERIC_TIME
diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h
index 270a4f4bc8a9..03f3583c8918 100644
--- a/include/asm-sh/titan.h
+++ b/include/asm-sh/titan.h
@@ -1,9 +1,8 @@
 /*
 * Platform defintions for Titan
 */
+#ifndef _ASM_SH_TITAN_H
-#ifndef _ASM_SH_TITAN_TITAN_H
+#define _ASM_SH_TITAN_H
-#define _ASM_SH_TITAN_TITAN_H
 #define __IO_PREFIX titan
 #include <asm/io_generic.h>
@@ -15,29 +14,4 @@
 #define TITAN_IRQ_MPCIB         11      /* mPCI B */
 #define TITAN_IRQ_USB           11      /* USB */
-/*
+#endif /* __ASM_SH_TITAN_H */
- * The external interrupt lines, these take up ints 0 - 15 inclusive
- * depending on the priority for the interrupt.  In fact the priority
- * is the interrupt :-)
- */
-#define IRL0_IRQ        0
-#define IRL0_IPR_ADDR   INTC_IPRD
-#define IRL0_IPR_POS    3
-#define IRL0_PRIORITY   8
-#define IRL1_IRQ        1
-#define IRL1_IPR_ADDR   INTC_IPRD
-#define IRL1_IPR_POS    2
-#define IRL1_PRIORITY   8
-#define IRL2_IRQ        2
-#define IRL2_IPR_ADDR   INTC_IPRD
-#define IRL2_IPR_POS    1
-#define IRL2_PRIORITY   8
-#define IRL3_IRQ        3
-#define IRL3_IPR_ADDR   INTC_IPRD
-#define IRL3_IPR_POS    0
-#define IRL3_PRIORITY   8
-#endif
diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h
index 3c09dd4ca31c..fd00dbb82f84 100644
--- a/include/asm-sh/types.h
+++ b/include/asm-sh/types.h
@@ -52,16 +52,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
-#ifdef CONFIG_LSF
-typedef u64 blkcnt_t;
-#define HAVE_BLKCNT_T
-#endif
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index 1c2abde122cd..0cae1d248761 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -349,12 +349,30 @@ do { \
        return (type) (res); \
 } while (0)
+#if defined(__sh2__) || defined(__SH2E__) || defined(__SH2A__)
+#define SYSCALL_ARG0    "trapa #0x20"
+#define SYSCALL_ARG1    "trapa #0x21"
+#define SYSCALL_ARG2    "trapa #0x22"
+#define SYSCALL_ARG3    "trapa #0x23"
+#define SYSCALL_ARG4    "trapa #0x24"
+#define SYSCALL_ARG5    "trapa #0x25"
+#define SYSCALL_ARG6    "trapa #0x26"
+#else
+#define SYSCALL_ARG0    "trapa #0x10"
+#define SYSCALL_ARG1    "trapa #0x11"
+#define SYSCALL_ARG2    "trapa #0x12"
+#define SYSCALL_ARG3    "trapa #0x13"
+#define SYSCALL_ARG4    "trapa #0x14"
+#define SYSCALL_ARG5    "trapa #0x15"
+#define SYSCALL_ARG6    "trapa #0x16"
+#endif
 /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
 #define _syscall0(type,name) \
 type name(void) \
 { \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
-__asm__ __volatile__ ("trapa    #0x10" \
+__asm__ __volatile__ (SYSCALL_ARG0 \
        : "=z" (__sc0) \
        : "0" (__sc0) \
        : "memory" ); \
@@ -366,7 +384,7 @@ type name(type1 arg1) \
 { \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
-__asm__ __volatile__ ("trapa    #0x11" \
+__asm__ __volatile__ (SYSCALL_ARG1 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4) \
        : "memory"); \
@@ -379,7 +397,7 @@ type name(type1 arg1,type2 arg2) \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
-__asm__ __volatile__ ("trapa    #0x12" \
+__asm__ __volatile__ (SYSCALL_ARG2 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5) \
        : "memory"); \
@@ -393,7 +411,7 @@ register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
-__asm__ __volatile__ ("trapa    #0x13" \
+__asm__ __volatile__ (SYSCALL_ARG3 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
        : "memory"); \
@@ -408,7 +426,7 @@ register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
-__asm__ __volatile__ ("trapa    #0x14" \
+__asm__ __volatile__ (SYSCALL_ARG4 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6),  \
          "r" (__sc7) \
@@ -425,7 +443,7 @@ register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
 register long __sc0 __asm__ ("r0") = (long) arg5; \
-__asm__ __volatile__ ("trapa    #0x15" \
+__asm__ __volatile__ (SYSCALL_ARG5 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7),  \
          "r" (__sc3) \
@@ -443,7 +461,7 @@ register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
 register long __sc0 __asm__ ("r0") = (long) arg5; \
 register long __sc1 __asm__ ("r1") = (long) arg6; \
-__asm__ __volatile__ ("trapa    #0x16" \
+__asm__ __volatile__ (SYSCALL_ARG6 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7),  \
          "r" (__sc3), "r" (__sc1) \
diff --git a/include/asm-x86_64/atomic.h b/include/asm-x86_64/atomic.h
index 007e88d6d43f..93849f7abc24 100644
--- a/include/asm-x86_64/atomic.h
+++ b/include/asm-x86_64/atomic.h
@@ -21,7 +21,7 @@
 * on us. We need to use _exactly_ the address the user gave us,
 * not some alias that contains the same information.
 */
-typedef struct { volatile int counter; } atomic_t;
+typedef struct { int counter; } atomic_t;
 #define ATOMIC_INIT(i)  { (i) }
diff --git a/include/asm-x86_64/spinlock_types.h b/include/asm-x86_64/spinlock_types.h
index 59efe849f351..4da9345c1500 100644
--- a/include/asm-x86_64/spinlock_types.h
+++ b/include/asm-x86_64/spinlock_types.h
@@ -6,13 +6,13 @@
 #endif
 typedef struct {
-        volatile unsigned int slock;
+        unsigned int slock;
 } raw_spinlock_t;
 #define __RAW_SPIN_LOCK_UNLOCKED        { 1 }
 typedef struct {
-        volatile unsigned int lock;
+        unsigned int lock;
 } raw_rwlock_t;
 #define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
diff --git a/include/asm-x86_64/types.h b/include/asm-x86_64/types.h
index c86c2e6793e2..2d4491aae281 100644
--- a/include/asm-x86_64/types.h
+++ b/include/asm-x86_64/types.h
@@ -48,9 +48,6 @@ typedef unsigned long long u64;
 typedef u64 dma64_addr_t;
 typedef u64 dma_addr_t;
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/linux/aio.h b/include/linux/aio.h
index 0d71c0041f13..9e350fd44d77 100644
--- a/include/linux/aio.h
+++ b/include/linux/aio.h
@@ -194,7 +194,7 @@ struct kioctx {
        struct aio_ring_info    ring_info;
-        struct work_struct      wq;
+        struct delayed_work     wq;
 };
 /* prototypes */
diff --git a/include/linux/connector.h b/include/linux/connector.h
index 4c02119c6ab9..3ea1cd58de97 100644
--- a/include/linux/connector.h
+++ b/include/linux/connector.h
@@ -133,7 +133,7 @@ struct cn_callback_data {
 struct cn_callback_entry {
        struct list_head callback_entry;
        struct cn_callback *cb;
-        struct work_struct work;
+        struct delayed_work work;
        struct cn_queue_dev *pdev;
        struct cn_callback_id id;
@@ -170,7 +170,7 @@ void cn_queue_free_dev(struct cn_queue_dev *dev);
 int cn_cb_equal(struct cb_id *, struct cb_id *);
-void cn_queue_wrapper(void *data);
+void cn_queue_wrapper(struct work_struct *work);
 extern int cn_already_initialized;
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 3fef7d67aedc..f02d71bf6894 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -33,6 +33,14 @@ struct cpu {
 extern int register_cpu(struct cpu *cpu, int num);
 extern struct sys_device *get_cpu_sysdev(unsigned cpu);
+extern int cpu_add_sysdev_attr(struct sysdev_attribute *attr);
+extern void cpu_remove_sysdev_attr(struct sysdev_attribute *attr);
+extern int cpu_add_sysdev_attr_group(struct attribute_group *attrs);
+extern void cpu_remove_sysdev_attr_group(struct attribute_group *attrs);
 #ifdef CONFIG_HOTPLUG_CPU
 extern void unregister_cpu(struct cpu *cpu);
 #endif
diff --git a/include/linux/elf.h b/include/linux/elf.h
index b70d1d2c8d28..743d5c8e6d36 100644
--- a/include/linux/elf.h
+++ b/include/linux/elf.h
@@ -368,5 +368,12 @@ extern Elf64_Dyn _DYNAMIC [];
 #endif
+#ifndef ARCH_HAVE_EXTRA_ELF_NOTES
+static inline int arch_notes_size(void) { return 0; }
+static inline void arch_write_notes(struct file *file) { }
+#define ELF_CORE_EXTRA_NOTES_SIZE arch_notes_size()
+#define ELF_CORE_WRITE_EXTRA_NOTES arch_write_notes(file)
+#endif /* ARCH_HAVE_EXTRA_ELF_NOTES */
 #endif /* _LINUX_ELF_H */
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index c115e9e840b4..1fb02e17f6f6 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -461,7 +461,7 @@ struct i2o_driver {
        int (*reply) (struct i2o_controller *, u32, struct i2o_message *);
        /* Event handler */
-        void (*event) (struct i2o_event *);
+        work_func_t event;
        struct workqueue_struct *event_queue;   /* Event queue */
diff --git a/include/linux/kbd_kern.h b/include/linux/kbd_kern.h
index efe0ee4cc80b..06c58c423fe1 100644
--- a/include/linux/kbd_kern.h
+++ b/include/linux/kbd_kern.h
@@ -158,7 +158,7 @@ static inline void con_schedule_flip(struct tty_struct *t)
        if (t->buf.tail != NULL)
                t->buf.tail->commit = t->buf.tail->used;
        spin_unlock_irqrestore(&t->buf.lock, flags);
-        schedule_work(&t->buf.work);
+        schedule_delayed_work(&t->buf.work, 0);
 }
 #endif
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 202283b5df96..ab2754830322 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -575,8 +575,9 @@ struct ata_port {
        struct ata_host         *host;
        struct device           *dev;
-        struct work_struct      port_task;
+        void                    *port_task_data;
-        struct work_struct      hotplug_task;
+        struct delayed_work     port_task;
+        struct delayed_work     hotplug_task;
        struct work_struct      scsi_rescan_task;
        unsigned int            hsm_task_state;
@@ -755,7 +756,7 @@ extern void ata_host_resume(struct ata_host *host);
 extern int ata_ratelimit(void);
 extern int ata_busy_sleep(struct ata_port *ap,
                          unsigned long timeout_pat, unsigned long timeout);
-extern void ata_port_queue_task(struct ata_port *ap, void (*fn)(void *),
+extern void ata_port_queue_task(struct ata_port *ap, work_func_t fn,
                                void *data, unsigned long delay);
 extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
                             unsigned long interval_msec,
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 528e7d3fecb1..c15ae1986b98 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -110,7 +110,7 @@ struct mmc_host {
        struct mmc_card         *card_busy;     /* the MMC card claiming host */
        struct mmc_card         *card_selected; /* the selected MMC card */
-        struct work_struct      detect;
+        struct delayed_work     detect;
        unsigned long           private[0] ____cacheline_aligned;
 };
diff --git a/include/linux/ncp_fs_sb.h b/include/linux/ncp_fs_sb.h
index b089d9506283..a503052138bd 100644
--- a/include/linux/ncp_fs_sb.h
+++ b/include/linux/ncp_fs_sb.h
@@ -127,10 +127,10 @@ struct ncp_server {
        } unexpected_packet;
 };
-extern void ncp_tcp_rcv_proc(void *server);
+extern void ncp_tcp_rcv_proc(struct work_struct *work);
-extern void ncp_tcp_tx_proc(void *server);
+extern void ncp_tcp_tx_proc(struct work_struct *work);
-extern void ncpdgram_rcv_proc(void *server);
+extern void ncpdgram_rcv_proc(struct work_struct *work);
-extern void ncpdgram_timeout_proc(void *server);
+extern void ncpdgram_timeout_proc(struct work_struct *work);
 extern void ncpdgram_timeout_call(unsigned long server);
 extern void ncp_tcp_data_ready(struct sock* sk, int len);
 extern void ncp_tcp_write_space(struct sock* sk);
diff --git a/include/linux/netpoll.h b/include/linux/netpoll.h
index 2cc9867b1626..29930b71a9aa 100644
--- a/include/linux/netpoll.h
+++ b/include/linux/netpoll.h
@@ -32,7 +32,7 @@ struct netpoll_info {
        struct netpoll *rx_np; /* netpoll that registered an rx_hook */
        struct sk_buff_head arp_tx; /* list of arp requests to reply to */
        struct sk_buff_head txq;
-        struct work_struct tx_work;
+        struct delayed_work tx_work;
 };
 void netpoll_poll(struct netpoll *np);
diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h
index 7ccfc7ef0a83..95796e6924f1 100644
--- a/include/linux/nfs_fs_sb.h
+++ b/include/linux/nfs_fs_sb.h
@@ -51,7 +51,7 @@ struct nfs_client {
        unsigned long           cl_lease_time;
        unsigned long           cl_last_renewal;
-        struct work_struct      cl_renewd;
+        struct delayed_work     cl_renewd;
        struct rpc_wait_queue   cl_rpcwaitq;
diff --git a/include/linux/reiserfs_fs_sb.h b/include/linux/reiserfs_fs_sb.h
index 62a7169aed8b..3a28742d86f9 100644
--- a/include/linux/reiserfs_fs_sb.h
+++ b/include/linux/reiserfs_fs_sb.h
@@ -249,7 +249,8 @@ struct reiserfs_journal {
        int j_errno;
        /* when flushing ordered buffers, throttle new ordered writers */
-        struct work_struct j_work;
+        struct delayed_work j_work;
+        struct super_block *j_work_sb;
        atomic_t j_async_throttle;
 };
diff --git a/include/linux/relay.h b/include/linux/relay.h
index 24accb483849..0e3d91b76996 100644
--- a/include/linux/relay.h
+++ b/include/linux/relay.h
@@ -38,7 +38,7 @@ struct rchan_buf
        size_t subbufs_consumed;        /* count of sub-buffers consumed */
        struct rchan *chan;             /* associated channel */
        wait_queue_head_t read_wait;    /* reader wait queue */
-        struct work_struct wake_readers; /* reader wake-up work struct */
+        struct delayed_work wake_readers; /* reader wake-up work struct */
        struct dentry *dentry;          /* channel file dentry */
        struct kref kref;               /* channel buffer refcount */
        struct page **page_array;       /* array of current buffer pages */
diff --git a/include/linux/sunrpc/rpc_pipe_fs.h b/include/linux/sunrpc/rpc_pipe_fs.h
index a2eb9b4a9de3..4a68125b6de6 100644
--- a/include/linux/sunrpc/rpc_pipe_fs.h
+++ b/include/linux/sunrpc/rpc_pipe_fs.h
@@ -30,7 +30,7 @@ struct rpc_inode {
 #define RPC_PIPE_WAIT_FOR_OPEN  1
        int flags;
        struct rpc_pipe_ops *ops;
-        struct work_struct queue_timeout;
+        struct delayed_work queue_timeout;
 };
 static inline struct rpc_inode *
diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h
index 60394fbc4c70..3e04c1512fc4 100644
--- a/include/linux/sunrpc/xprt.h
+++ b/include/linux/sunrpc/xprt.h
@@ -177,7 +177,7 @@ struct rpc_xprt {
        unsigned long           connect_timeout,
                                bind_timeout,
                                reestablish_timeout;
-        struct work_struct      connect_worker;
+        struct delayed_work     connect_worker;
        unsigned short          port;
        /*
diff --git a/include/linux/tty.h b/include/linux/tty.h
index 65321f911c1e..f717f0898238 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -53,7 +53,7 @@ struct tty_buffer {
 };
 struct tty_bufhead {
-        struct work_struct              work;
+        struct delayed_work work;
        struct semaphore pty_sem;
        spinlock_t lock;
        struct tty_buffer *head;        /* Queue head */
diff --git a/include/linux/types.h b/include/linux/types.h
index 745c409ebbb5..0351bf2fac85 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -136,15 +136,19 @@ typedef		__s64		int64_t;
 *
 * Linux always considers sectors to be 512 bytes long independently
 * of the devices real block size.
- *
- * If required, asm/types.h can override it and define
- * HAVE_SECTOR_T
 */
-#ifndef HAVE_SECTOR_T
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#else
 typedef unsigned long sector_t;
 #endif
-#ifndef HAVE_BLKCNT_T
+/*
+ * The type of the inode's block count.
+ */
+#ifdef CONFIG_LSF
+typedef u64 blkcnt_t;
+#else
 typedef unsigned long blkcnt_t;
 #endif
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 0cd73edeef13..aab5b1b72021 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -388,7 +388,7 @@ struct usb_device {
        int pm_usage_cnt;               /* usage counter for autosuspend */
 #ifdef CONFIG_PM
-        struct work_struct autosuspend; /* for delayed autosuspends */
+        struct delayed_work autosuspend; /* for delayed autosuspends */
        struct mutex pm_mutex;          /* protects PM operations */
        unsigned auto_pm:1;             /* autosuspend/resume in progress */
diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index 9bca3539a1e5..4a3ea83c6d16 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -11,12 +11,23 @@
 struct workqueue_struct;
+struct work_struct;
+typedef void (*work_func_t)(struct work_struct *work);
 struct work_struct {
-        unsigned long pending;
+        /* the first word is the work queue pointer and the flags rolled into
+         * one */
+        unsigned long management;
+#define WORK_STRUCT_PENDING 0           /* T if work item pending execution */
+#define WORK_STRUCT_NOAUTOREL 1         /* F if work item automatically released on exec */
+#define WORK_STRUCT_FLAG_MASK (3UL)
+#define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK)
        struct list_head entry;
-        void (*func)(void *);
+        work_func_t func;
-        void *data;
+};
-        void *wq_data;
+struct delayed_work {
+        struct work_struct work;
        struct timer_list timer;
 };
@@ -24,36 +35,117 @@ struct execute_work {
        struct work_struct work;
 };
-#define __WORK_INITIALIZER(n, f, d) {                           \
+#define __WORK_INITIALIZER(n, f) {                              \
+        .management = 0,                                        \
+        .entry  = { &(n).entry, &(n).entry },                   \
+        .func = (f),                                            \
+        }
+#define __WORK_INITIALIZER_NAR(n, f) {                          \
+        .management = (1 << WORK_STRUCT_NOAUTOREL),             \
        .entry  = { &(n).entry, &(n).entry },                   \
        .func = (f),                                            \
-        .data = (d),                                            \
+        }
+#define __DELAYED_WORK_INITIALIZER(n, f) {                      \
+        .work = __WORK_INITIALIZER((n).work, (f)),              \
+        .timer = TIMER_INITIALIZER(NULL, 0, 0),                 \
+        }
+#define __DELAYED_WORK_INITIALIZER_NAR(n, f) {                  \
+        .work = __WORK_INITIALIZER_NAR((n).work, (f)),          \
        .timer = TIMER_INITIALIZER(NULL, 0, 0),                 \
        }
-#define DECLARE_WORK(n, f, d)                                   \
+#define DECLARE_WORK(n, f)                                      \
-        struct work_struct n = __WORK_INITIALIZER(n, f, d)
+        struct work_struct n = __WORK_INITIALIZER(n, f)
+#define DECLARE_WORK_NAR(n, f)                                  \
+        struct work_struct n = __WORK_INITIALIZER_NAR(n, f)
+#define DECLARE_DELAYED_WORK(n, f)                              \
+        struct delayed_work n = __DELAYED_WORK_INITIALIZER(n, f)
+#define DECLARE_DELAYED_WORK_NAR(n, f)                  \
+        struct dwork_struct n = __DELAYED_WORK_INITIALIZER_NAR(n, f)
 /*
- * initialize a work-struct's func and data pointers:
+ * initialize a work item's function pointer
 */
-#define PREPARE_WORK(_work, _func, _data)                       \
+#define PREPARE_WORK(_work, _func)                              \
        do {                                                    \
-                (_work)->func = _func;                          \
+                (_work)->func = (_func);                        \
-                (_work)->data = _data;                          \
        } while (0)
+#define PREPARE_DELAYED_WORK(_work, _func)                      \
+        PREPARE_WORK(&(_work)->work, (_func))
 /*
- * initialize all of a work-struct:
+ * initialize all of a work item in one go
 */
-#define INIT_WORK(_work, _func, _data)                          \
+#define INIT_WORK(_work, _func)                                 \
        do {                                                    \
+                (_work)->management = 0;                        \
                INIT_LIST_HEAD(&(_work)->entry);                \
-                (_work)->pending = 0;                           \
+                PREPARE_WORK((_work), (_func));                 \
-                PREPARE_WORK((_work), (_func), (_data));        \
+        } while (0)
+#define INIT_WORK_NAR(_work, _func)                                     \
+        do {                                                            \
+                (_work)->management = (1 << WORK_STRUCT_NOAUTOREL);     \
+                INIT_LIST_HEAD(&(_work)->entry);                        \
+                PREPARE_WORK((_work), (_func));                         \
+        } while (0)
+#define INIT_DELAYED_WORK(_work, _func)                         \
+        do {                                                    \
+                INIT_WORK(&(_work)->work, (_func));             \
+                init_timer(&(_work)->timer);                    \
+        } while (0)
+#define INIT_DELAYED_WORK_NAR(_work, _func)                     \
+        do {                                                    \
+                INIT_WORK_NAR(&(_work)->work, (_func));         \
                init_timer(&(_work)->timer);                    \
        } while (0)
+/**
+ * work_pending - Find out whether a work item is currently pending
+ * @work: The work item in question
+ */
+#define work_pending(work) \
+        test_bit(WORK_STRUCT_PENDING, &(work)->management)
+/**
+ * delayed_work_pending - Find out whether a delayable work item is currently
+ * pending
+ * @work: The work item in question
+ */
+#define delayed_work_pending(work) \
+        test_bit(WORK_STRUCT_PENDING, &(work)->work.management)
+/**
+ * work_release - Release a work item under execution
+ * @work: The work item to release
+ *
+ * This is used to release a work item that has been initialised with automatic
+ * release mode disabled (WORK_STRUCT_NOAUTOREL is set).  This gives the work
+ * function the opportunity to grab auxiliary data from the container of the
+ * work_struct before clearing the pending bit as the work_struct may be
+ * subject to deallocation the moment the pending bit is cleared.
+ *
+ * In such a case, this should be called in the work function after it has
+ * fetched any data it may require from the containter of the work_struct.
+ * After this function has been called, the work_struct may be scheduled for
+ * further execution or it may be deallocated unless other precautions are
+ * taken.
+ *
+ * This should also be used to release a delayed work item.
+ */
+#define work_release(work) \
+        clear_bit(WORK_STRUCT_PENDING, &(work)->management)
 extern struct workqueue_struct *__create_workqueue(const char *name,
                                                    int singlethread);
 #define create_workqueue(name) __create_workqueue((name), 0)
@@ -62,39 +154,38 @@ extern struct workqueue_struct *__create_workqueue(const char *name,
 extern void destroy_workqueue(struct workqueue_struct *wq);
 extern int FASTCALL(queue_work(struct workqueue_struct *wq, struct work_struct *work));
-extern int FASTCALL(queue_delayed_work(struct workqueue_struct *wq, struct work_struct *work, unsigned long delay));
+extern int FASTCALL(queue_delayed_work(struct workqueue_struct *wq, struct delayed_work *work, unsigned long delay));
 extern int queue_delayed_work_on(int cpu, struct workqueue_struct *wq,
-        struct work_struct *work, unsigned long delay);
+        struct delayed_work *work, unsigned long delay);
 extern void FASTCALL(flush_workqueue(struct workqueue_struct *wq));
 extern int FASTCALL(schedule_work(struct work_struct *work));
-extern int FASTCALL(schedule_delayed_work(struct work_struct *work, unsigned long delay));
+extern int FASTCALL(schedule_delayed_work(struct delayed_work *work, unsigned long delay));
-extern int schedule_delayed_work_on(int cpu, struct work_struct *work, unsigned long delay);
+extern int schedule_delayed_work_on(int cpu, struct delayed_work *work, unsigned long delay);
-extern int schedule_on_each_cpu(void (*func)(void *info), void *info);
+extern int schedule_on_each_cpu(work_func_t func);
 extern void flush_scheduled_work(void);
 extern int current_is_keventd(void);
 extern int keventd_up(void);
 extern void init_workqueues(void);
-void cancel_rearming_delayed_work(struct work_struct *work);
+void cancel_rearming_delayed_work(struct delayed_work *work);
 void cancel_rearming_delayed_workqueue(struct workqueue_struct *,
-                                       struct work_struct *);
+                                       struct delayed_work *);
-int execute_in_process_context(void (*fn)(void *), void *,
+int execute_in_process_context(work_func_t fn, struct execute_work *);
-                               struct execute_work *);
 /*
 * Kill off a pending schedule_delayed_work().  Note that the work callback
 * function may still be running on return from cancel_delayed_work().  Run
 * flush_scheduled_work() to wait on it.
 */
-static inline int cancel_delayed_work(struct work_struct *work)
+static inline int cancel_delayed_work(struct delayed_work *work)
 {
        int ret;
        ret = del_timer_sync(&work->timer);
        if (ret)
-                clear_bit(0, &work->pending);
+                clear_bit(WORK_STRUCT_PENDING, &work->work.management);
        return ret;
 }
diff --git a/include/net/ieee80211softmac.h b/include/net/ieee80211softmac.h
index 617b672b1132..89119277553d 100644
--- a/include/net/ieee80211softmac.h
+++ b/include/net/ieee80211softmac.h
@@ -108,8 +108,8 @@ struct ieee80211softmac_assoc_info {
        /* Scan retries remaining */
        int scan_retry;
-        struct work_struct work;
+        struct delayed_work work;
-        struct work_struct timeout;
+        struct delayed_work timeout;
 };
 struct ieee80211softmac_bss_info {
diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h
index 5f48748fe017..f7be1ac73601 100644
--- a/include/net/inet_timewait_sock.h
+++ b/include/net/inet_timewait_sock.h
@@ -84,7 +84,7 @@ struct inet_timewait_death_row {
 };
 extern void inet_twdr_hangman(unsigned long data);
-extern void inet_twdr_twkill_work(void *data);
+extern void inet_twdr_twkill_work(struct work_struct *work);
 extern void inet_twdr_twcal_tick(unsigned long data);
 #if (BITS_PER_LONG == 64)
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index f8cbe40f52c0..c089f93ba591 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -1030,7 +1030,7 @@ void sctp_inq_init(struct sctp_inq *);
 void sctp_inq_free(struct sctp_inq *);
 void sctp_inq_push(struct sctp_inq *, struct sctp_chunk *packet);
 struct sctp_chunk *sctp_inq_pop(struct sctp_inq *);
-void sctp_inq_set_th_handler(struct sctp_inq *, void (*)(void *), void *);
+void sctp_inq_set_th_handler(struct sctp_inq *, work_func_t);
 /* This is the structure we use to hold outbound chunks.  You push
 * chunks in and they automatically pop out the other end as bundled
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
index ede639812f8a..623a0fc0dae1 100644
--- a/include/pcmcia/ss.h
+++ b/include/pcmcia/ss.h
@@ -262,9 +262,10 @@ struct pcmcia_socket {
                u8                      present:1,      /* PCMCIA card is present in socket */
                                        busy:1,         /* "master" ioctl is used */
                                        dead:1,         /* pcmcia module is being unloaded */
-                                        device_add_pending:1, /* a pseudo-multifunction-device
+                                        device_add_pending:1, /* a multifunction-device
                                                               * add event is pending */
-                                        reserved:4;
+                                        mfc_pfc:1,      /* the pending event adds a mfc (1) or pfc (0) */
+                                        reserved:3;
        }                               pcmcia_state;
        struct work_struct              device_add;     /* for adding further pseudo-multifunction
diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h
index 1d77b63c5ea4..9233ed5de664 100644
--- a/include/scsi/libsas.h
+++ b/include/scsi/libsas.h
@@ -201,9 +201,14 @@ struct domain_device {
        void *lldd_dev;
 };
+struct sas_discovery_event {
+        struct work_struct work;
+        struct asd_sas_port *port;
+};
 struct sas_discovery {
        spinlock_t disc_event_lock;
-        struct work_struct disc_work[DISC_NUM_EVENTS];
+        struct sas_discovery_event disc_work[DISC_NUM_EVENTS];
        unsigned long    pending;
        u8     fanout_sas_addr[8];
        u8     eeds_a[8];
@@ -249,14 +254,19 @@ struct asd_sas_port {
        void *lldd_port;          /* not touched by the sas class code */
 };
+struct asd_sas_event {
+        struct work_struct work;
+        struct asd_sas_phy *phy;
+};
 /* The phy pretty much is controlled by the LLDD.
 * The class only reads those fields.
 */
 struct asd_sas_phy {
 /* private: */
        /* protected by ha->event_lock */
-        struct work_struct   port_events[PORT_NUM_EVENTS];
+        struct asd_sas_event   port_events[PORT_NUM_EVENTS];
-        struct work_struct   phy_events[PHY_NUM_EVENTS];
+        struct asd_sas_event   phy_events[PHY_NUM_EVENTS];
        unsigned long port_events_pending;
        unsigned long phy_events_pending;
@@ -308,10 +318,15 @@ struct scsi_core {
        int               queue_thread_kill;
 };
+struct sas_ha_event {
+        struct work_struct work;
+        struct sas_ha_struct *ha;
+};
 struct sas_ha_struct {
 /* private: */
        spinlock_t       event_lock;
-        struct work_struct ha_events[HA_NUM_EVENTS];
+        struct sas_ha_event ha_events[HA_NUM_EVENTS];
        unsigned long    pending;
        struct scsi_core core;
@@ -339,6 +354,8 @@ struct sas_ha_struct {
        void (*notify_phy_event)(struct asd_sas_phy *, enum phy_event);
        void *lldd_ha;            /* not touched by sas class code */
+        struct list_head eh_done_q;
 };
 #define SHOST_TO_SAS_HA(_shost) (*(struct sas_ha_struct **)(_shost)->hostdata)
@@ -527,13 +544,16 @@ struct sas_task {
        void   *lldd_task;        /* for use by LLDDs */
        void   *uldd_task;
+        struct work_struct abort_work;
 };
-#define SAS_TASK_STATE_PENDING  1
+#define SAS_TASK_STATE_PENDING      1
-#define SAS_TASK_STATE_DONE     2
+#define SAS_TASK_STATE_DONE         2
-#define SAS_TASK_STATE_ABORTED  4
+#define SAS_TASK_STATE_ABORTED      4
+#define SAS_TASK_INITIATOR_ABORTED  8
 static inline struct sas_task *sas_alloc_task(gfp_t flags)
 {
@@ -593,6 +613,7 @@ struct sas_domain_function_template {
 extern int sas_register_ha(struct sas_ha_struct *);
 extern int sas_unregister_ha(struct sas_ha_struct *);
+int sas_phy_reset(struct sas_phy *phy, int hard_reset);
 extern int sas_queuecommand(struct scsi_cmnd *,
                     void (*scsi_done)(struct scsi_cmnd *));
 extern int sas_target_alloc(struct scsi_target *);
@@ -625,4 +646,6 @@ void sas_unregister_dev(struct domain_device *);
 void sas_init_dev(struct domain_device *);
+void sas_task_abort(struct work_struct *);
 #endif /* _SASLIB_H_ */
diff --git a/include/scsi/libsrp.h b/include/scsi/libsrp.h
new file mode 100644
index 000000000000..d143171896ae
--- /dev/null
+++ b/include/scsi/libsrp.h
@@ -0,0 +1,77 @@
+#ifndef __LIBSRP_H__
+#define __LIBSRP_H__
+#include <linux/list.h>
+#include <scsi/scsi_cmnd.h>
+#include <scsi/scsi_host.h>
+#include <scsi/srp.h>
+enum iue_flags {
+        V_DIOVER,
+        V_WRITE,
+        V_LINKED,
+        V_FLYING,
+};
+struct srp_buf {
+        dma_addr_t dma;
+        void *buf;
+};
+struct srp_queue {
+        void *pool;
+        void *items;
+        struct kfifo *queue;
+        spinlock_t lock;
+};
+struct srp_target {
+        struct Scsi_Host *shost;
+        struct device *dev;
+        spinlock_t lock;
+        struct list_head cmd_queue;
+        size_t srp_iu_size;
+        struct srp_queue iu_queue;
+        size_t rx_ring_size;
+        struct srp_buf **rx_ring;
+        void *ldata;
+};
+struct iu_entry {
+        struct srp_target *target;
+        struct list_head ilist;
+        dma_addr_t remote_token;
+        unsigned long flags;
+        struct srp_buf *sbuf;
+};
+typedef int (srp_rdma_t)(struct scsi_cmnd *, struct scatterlist *, int,
+                         struct srp_direct_buf *, int,
+                         enum dma_data_direction, unsigned int);
+extern int srp_target_alloc(struct srp_target *, struct device *, size_t, size_t);
+extern void srp_target_free(struct srp_target *);
+extern struct iu_entry *srp_iu_get(struct srp_target *);
+extern void srp_iu_put(struct iu_entry *);
+extern int srp_cmd_queue(struct Scsi_Host *, struct srp_cmd *, void *, u64);
+extern int srp_transfer_data(struct scsi_cmnd *, struct srp_cmd *,
+                             srp_rdma_t, int, int);
+static inline struct srp_target *host_to_srp_target(struct Scsi_Host *host)
+{
+        return (struct srp_target *) host->hostdata;
+}
+static inline int srp_cmd_direction(struct srp_cmd *cmd)
+{
+        return (cmd->buf_fmt >> 4) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+}
+#endif
diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h
index be117f812deb..d6948d0e8cdb 100644
--- a/include/scsi/scsi_cmnd.h
+++ b/include/scsi/scsi_cmnd.h
@@ -8,6 +8,7 @@
 struct request;
 struct scatterlist;
+struct Scsi_Host;
 struct scsi_device;
@@ -72,6 +73,9 @@ struct scsi_cmnd {
        unsigned short use_sg;  /* Number of pieces of scatter-gather */
        unsigned short sglist_len;      /* size of malloc'd scatter-gather list */
+        /* offset in cmd we are at (for multi-transfer tgt cmds) */
+        unsigned offset;
        unsigned underflow;     /* Return error if less than
                                   this amount is transferred */
@@ -119,7 +123,10 @@ struct scsi_cmnd {
 };
 extern struct scsi_cmnd *scsi_get_command(struct scsi_device *, gfp_t);
+extern struct scsi_cmnd *__scsi_get_command(struct Scsi_Host *, gfp_t);
 extern void scsi_put_command(struct scsi_cmnd *);
+extern void __scsi_put_command(struct Scsi_Host *, struct scsi_cmnd *,
+                               struct device *);
 extern void scsi_io_completion(struct scsi_cmnd *, unsigned int);
 extern void scsi_finish_command(struct scsi_cmnd *cmd);
 extern void scsi_req_abort_cmd(struct scsi_cmnd *cmd);
@@ -128,4 +135,7 @@ extern void *scsi_kmap_atomic_sg(struct scatterlist *sg, int sg_count,
                                 size_t *offset, size_t *len);
 extern void scsi_kunmap_atomic_sg(void *virt);
+extern struct scatterlist *scsi_alloc_sgtable(struct scsi_cmnd *, gfp_t);
+extern void scsi_free_sgtable(struct scatterlist *, int);
 #endif /* _SCSI_SCSI_CMND_H */
diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h
index b401c82036be..ebf31b16dc49 100644
--- a/include/scsi/scsi_device.h
+++ b/include/scsi/scsi_device.h
@@ -223,13 +223,13 @@ extern struct scsi_device *__scsi_iterate_devices(struct Scsi_Host *,
                                                  struct scsi_device *);
 /**
- * shost_for_each_device  -  iterate over all devices of a host
+ * shost_for_each_device - iterate over all devices of a host
- * @sdev:       iterator
+ * @sdev: the &struct scsi_device to use as a cursor
- * @host:       host whiches devices we want to iterate over
+ * @shost: the &struct scsi_host to iterate over
 *
- * This traverses over each devices of @shost.  The devices have
+ * Iterator that returns each device attached to @shost.  This loop
- * a reference that must be released by scsi_host_put when breaking
+ * takes a reference on each device and releases it at the end.  If
- * out of the loop.
+ * you break out of the loop, you must call scsi_device_put(sdev).
 */
 #define shost_for_each_device(sdev, shost) \
        for ((sdev) = __scsi_iterate_devices((shost), NULL); \
@@ -237,17 +237,17 @@ extern struct scsi_device *__scsi_iterate_devices(struct Scsi_Host *,
             (sdev) = __scsi_iterate_devices((shost), (sdev)))
 /**
- * __shost_for_each_device  -  iterate over all devices of a host (UNLOCKED)
+ * __shost_for_each_device - iterate over all devices of a host (UNLOCKED)
- * @sdev:       iterator
+ * @sdev: the &struct scsi_device to use as a cursor
- * @host:       host whiches devices we want to iterate over
+ * @shost: the &struct scsi_host to iterate over
 *
- * This traverses over each devices of @shost.  It does _not_ take a
+ * Iterator that returns each device attached to @shost.  It does _not_
- * reference on the scsi_device, thus it the whole loop must be protected
+ * take a reference on the scsi_device, so the whole loop must be
- * by shost->host_lock.
+ * protected by shost->host_lock.
 *
- * Note:  The only reason why drivers would want to use this is because
+ * Note: The only reason to use this is because you need to access the
- * they're need to access the device list in irq context.  Otherwise you
+ * device list in interrupt context.  Otherwise you really want to use
- * really want to use shost_for_each_device instead.
+ * shost_for_each_device instead.
 */
 #define __shost_for_each_device(sdev, shost) \
        list_for_each_entry((sdev), &((shost)->__devices), siblings)
diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h
index 39c6f8cc20c3..7f1f411d07af 100644
--- a/include/scsi/scsi_host.h
+++ b/include/scsi/scsi_host.h
@@ -7,6 +7,7 @@
 #include <linux/workqueue.h>
 #include <linux/mutex.h>
+struct request_queue;
 struct block_device;
 struct completion;
 struct module;
@@ -124,6 +125,39 @@ struct scsi_host_template {
                             void (*done)(struct scsi_cmnd *));
        /*
+         * The transfer functions are used to queue a scsi command to
+         * the LLD. When the driver is finished processing the command
+         * the done callback is invoked.
+         *
+         * return values: see queuecommand
+         *
+         * If the LLD accepts the cmd, it should set the result to an
+         * appropriate value when completed before calling the done function.
+         *
+         * STATUS: REQUIRED FOR TARGET DRIVERS
+         */
+        /* TODO: rename */
+        int (* transfer_response)(struct scsi_cmnd *,
+                                  void (*done)(struct scsi_cmnd *));
+        /*
+         * This is called to inform the LLD to transfer cmd->request_bufflen
+         * bytes of the cmd at cmd->offset in the cmd. The cmd->use_sg
+         * speciefies the number of scatterlist entried in the command
+         * and cmd->request_buffer contains the scatterlist.
+         *
+         * If the command cannot be processed in one transfer_data call
+         * becuase a scatterlist within the LLD's limits cannot be
+         * created then transfer_data will be called multiple times.
+         * It is initially called from process context, and later
+         * calls are from the interrup context.
+         */
+        int (* transfer_data)(struct scsi_cmnd *,
+                              void (*done)(struct scsi_cmnd *));
+        /* Used as callback for the completion of task management request. */
+        int (* tsk_mgmt_response)(u64 mid, int result);
+        /*
         * This is an error handling strategy routine.  You don't need to
         * define one of these if you don't want to - there is a default
         * routine that is present that should work in most cases.  For those
@@ -241,6 +275,24 @@ struct scsi_host_template {
        void (* target_destroy)(struct scsi_target *);
        /*
+         * If a host has the ability to discover targets on its own instead
+         * of scanning the entire bus, it can fill in this function and
+         * call scsi_scan_host().  This function will be called periodically
+         * until it returns 1 with the scsi_host and the elapsed time of
+         * the scan in jiffies.
+         *
+         * Status: OPTIONAL
+         */
+        int (* scan_finished)(struct Scsi_Host *, unsigned long);
+        /*
+         * If the host wants to be called before the scan starts, but
+         * after the midlayer has set up ready for the scan, it can fill
+         * in this function.
+         */
+        void (* scan_start)(struct Scsi_Host *);
+        /*
         * fill in this function to allow the queue depth of this host
         * to be changeable (on a per device basis).  returns either
         * the current queue depth setting (may be different from what
@@ -552,6 +604,9 @@ struct Scsi_Host {
        /* task mgmt function in progress */
        unsigned tmf_in_progress:1;
+        /* Asynchronous scan in progress */
+        unsigned async_scan:1;
        /*
         * Optional work queue to be utilized by the transport
         */
@@ -568,6 +623,12 @@ struct Scsi_Host {
         */
        unsigned int max_host_blocked;
+        /*
+         * q used for scsi_tgt msgs, async events or any other requests that
+         * need to be processed in userspace
+         */
+        struct request_queue *uspace_req_q;
        /* legacy crap */
        unsigned long base;
        unsigned long io_port;
@@ -648,11 +709,6 @@ extern const char *scsi_host_state_name(enum scsi_host_state);
 extern u64 scsi_calculate_bounce_limit(struct Scsi_Host *);
-static inline void scsi_assign_lock(struct Scsi_Host *shost, spinlock_t *lock)
-{
-        shost->host_lock = lock;
-}
 static inline struct device *scsi_get_device(struct Scsi_Host *shost)
 {
        return shost->shost_gendev.parent;
@@ -671,6 +727,9 @@ extern void scsi_unblock_requests(struct Scsi_Host *);
 extern void scsi_block_requests(struct Scsi_Host *);
 struct class_container;
+extern struct request_queue *__scsi_alloc_queue(struct Scsi_Host *shost,
+                                                void (*) (struct request_queue *));
 /*
 * These two functions are used to allocate and free a pseudo device
 * which will connect to the host adapter itself rather than any
diff --git a/include/scsi/scsi_tgt.h b/include/scsi/scsi_tgt.h
new file mode 100644
index 000000000000..4f4427937af2
--- /dev/null
+++ b/include/scsi/scsi_tgt.h
@@ -0,0 +1,19 @@
+/*
+ * SCSI target definitions
+ */
+#include <linux/dma-mapping.h>
+struct Scsi_Host;
+struct scsi_cmnd;
+struct scsi_lun;
+extern struct Scsi_Host *scsi_tgt_cmd_to_host(struct scsi_cmnd *);
+extern int scsi_tgt_alloc_queue(struct Scsi_Host *);
+extern void scsi_tgt_free_queue(struct Scsi_Host *);
+extern int scsi_tgt_queue_command(struct scsi_cmnd *, struct scsi_lun *, u64);
+extern int scsi_tgt_tsk_mgmt_request(struct Scsi_Host *, int, u64, struct scsi_lun *,
+                                     void *);
+extern struct scsi_cmnd *scsi_host_get_command(struct Scsi_Host *,
+                                               enum dma_data_direction, gfp_t);
+extern void scsi_host_put_command(struct Scsi_Host *, struct scsi_cmnd *);
diff --git a/include/scsi/scsi_tgt_if.h b/include/scsi/scsi_tgt_if.h
new file mode 100644
index 000000000000..46d5e70d7215
--- /dev/null
+++ b/include/scsi/scsi_tgt_if.h
@@ -0,0 +1,90 @@
+/*
+ * SCSI target kernel/user interface
+ *
+ * Copyright (C) 2005 FUJITA Tomonori <tomof@acm.org>
+ * Copyright (C) 2005 Mike Christie <michaelc@cs.wisc.edu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+#ifndef __SCSI_TARGET_IF_H
+#define __SCSI_TARGET_IF_H
+/* user -> kernel */
+#define TGT_UEVENT_CMD_RSP      0x0001
+#define TGT_UEVENT_TSK_MGMT_RSP 0x0002
+/* kernel -> user */
+#define TGT_KEVENT_CMD_REQ      0x1001
+#define TGT_KEVENT_CMD_DONE     0x1002
+#define TGT_KEVENT_TSK_MGMT_REQ 0x1003
+struct tgt_event_hdr {
+        uint16_t version;
+        uint16_t status;
+        uint16_t type;
+        uint16_t len;
+} __attribute__ ((aligned (sizeof(uint64_t))));
+struct tgt_event {
+        struct tgt_event_hdr hdr;
+        union {
+                /* user-> kernel */
+                struct {
+                        int host_no;
+                        uint32_t len;
+                        int result;
+                        aligned_u64 uaddr;
+                        uint8_t rw;
+                        aligned_u64 tag;
+                } cmd_rsp;
+                struct {
+                        int host_no;
+                        aligned_u64 mid;
+                        int result;
+                } tsk_mgmt_rsp;
+                /* kernel -> user */
+                struct {
+                        int host_no;
+                        uint32_t data_len;
+                        uint8_t scb[16];
+                        uint8_t lun[8];
+                        int attribute;
+                        aligned_u64 tag;
+                } cmd_req;
+                struct {
+                        int host_no;
+                        aligned_u64 tag;
+                        int result;
+                } cmd_done;
+                struct {
+                        int host_no;
+                        int function;
+                        aligned_u64 tag;
+                        uint8_t lun[8];
+                        aligned_u64 mid;
+                } tsk_mgmt_req;
+        } p;
+} __attribute__ ((aligned (sizeof(uint64_t))));
+#define TGT_RING_SIZE (1UL << 16)
+#define TGT_RING_PAGES (TGT_RING_SIZE >> PAGE_SHIFT)
+#define TGT_EVENT_PER_PAGE (PAGE_SIZE / sizeof(struct tgt_event))
+#define TGT_MAX_EVENTS (TGT_EVENT_PER_PAGE * TGT_RING_PAGES)
+#endif
diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h
index fd352323378b..798f7c7ee426 100644
--- a/include/scsi/scsi_transport_fc.h
+++ b/include/scsi/scsi_transport_fc.h
@@ -206,9 +206,9 @@ struct fc_rport {	/* aka fc_starget_attrs */
        u8 flags;
        struct list_head peers;
        struct device dev;
-        struct work_struct dev_loss_work;
+        struct delayed_work dev_loss_work;
        struct work_struct scan_work;
-        struct work_struct fail_io_work;
+        struct delayed_work fail_io_work;
        struct work_struct stgt_delete_work;
        struct work_struct rport_delete_work;
 } __attribute__((aligned(sizeof(unsigned long))));
diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h
index 4b95c89c95c9..d5c218ddc527 100644
--- a/include/scsi/scsi_transport_iscsi.h
+++ b/include/scsi/scsi_transport_iscsi.h
@@ -176,7 +176,7 @@ struct iscsi_cls_session {
        /* recovery fields */
        int recovery_tmo;
-        struct work_struct recovery_work;
+        struct delayed_work recovery_work;
        int target_id;
diff --git a/include/scsi/scsi_transport_sas.h b/include/scsi/scsi_transport_sas.h
index 53024377f3b8..59633a82de47 100644
--- a/include/scsi/scsi_transport_sas.h
+++ b/include/scsi/scsi_transport_sas.h
@@ -73,6 +73,8 @@ struct sas_phy {
        /* for the list of phys belonging to a port */
        struct list_head        port_siblings;
+        struct work_struct      reset_work;
 };
 #define dev_to_phy(d) \
diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h
index 4c43521cc493..33720397a904 100644
--- a/include/sound/ac97_codec.h
+++ b/include/sound/ac97_codec.h
@@ -511,7 +511,7 @@ struct snd_ac97 {
 #ifdef CONFIG_SND_AC97_POWER_SAVE
        unsigned int power_up;  /* power states */
        struct workqueue_struct *power_workq;
-        struct work_struct power_work;
+        struct delayed_work power_work;
 #endif
        struct device dev;
 };
diff --git a/include/sound/ak4114.h b/include/sound/ak4114.h
index 11702aa0bea9..2ee061625fd0 100644
--- a/include/sound/ak4114.h
+++ b/include/sound/ak4114.h
@@ -182,7 +182,7 @@ struct ak4114 {
        unsigned char rcs0;
        unsigned char rcs1;
        struct workqueue_struct *workqueue;
-        struct work_struct work;
+        struct delayed_work work;
        void *change_callback_private;
        void (*change_callback)(struct ak4114 *ak4114, unsigned char c0, unsigned char c1);
 };