35 files changed, 326 insertions, 67 deletions
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index db3b615ffbab..25b934b7f829 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -39,7 +39,9 @@ static inline void SSYNC (void)
 #elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
 static inline void SSYNC (void)
 {
-        __builtin_bfin_ssync();
+        __asm__ __volatile__ ("nop; nop; nop;\n\t"
+                        "ssync;\n\t"
+                        ::);
 }
 #elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
 static inline void SSYNC (void)
@@ -71,7 +73,9 @@ static inline void CSYNC (void)
 #elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
 static inline void CSYNC (void)
 {
-        __builtin_bfin_csync();
+        __asm__ __volatile__ ("nop; nop; nop;\n\t"
+                        "ssync;\n\t"
+                        ::);
 }
 #elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
 static inline void CSYNC (void)
@@ -80,6 +84,31 @@ static inline void CSYNC (void)
 }
 #endif
+#else  /* __ASSEMBLY__ */
+/* SSYNC & CSYNC implementations for assembly files */
+#define ssync(x) SSYNC(x)
+#define csync(x) CSYNC(x)
+#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
+#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
+#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
+#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
+#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+#define SSYNC(scratch) nop; nop; nop; SSYNC;
+#define CSYNC(scratch) nop; nop; nop; CSYNC;
+#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+#define SSYNC(scratch) SSYNC;
+#define CSYNC(scratch) CSYNC;
+#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
 #endif /* __ASSEMBLY__ */
 #endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h
index 7a77d7fe3a33..282fabccf6a6 100644
--- a/include/asm-blackfin/dma-mapping.h
+++ b/include/asm-blackfin/dma-mapping.h
@@ -15,6 +15,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_mapping_error
 /*
 * Map a single buffer of the indicated size for DMA in streaming mode.
 * The 32-bit bus address to use is returned.
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index eac8bcaf64c2..142cb333db29 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -20,7 +20,7 @@
 */
 #ifndef __ASSEMBLY__
-static inline unsigned char readb(void __iomem *addr)
+static inline unsigned char readb(const volatile void __iomem *addr)
 {
        unsigned int val;
        int tmp;
@@ -35,7 +35,7 @@ static inline unsigned char readb(void __iomem *addr)
        return (unsigned char) val;
 }
-static inline unsigned short readw(void __iomem *addr)
+static inline unsigned short readw(const volatile void __iomem *addr)
 {
        unsigned int val;
        int tmp;
@@ -50,7 +50,7 @@ static inline unsigned short readw(void __iomem *addr)
        return (unsigned short) val;
 }
-static inline unsigned int readl(void __iomem *addr)
+static inline unsigned int readl(const volatile void __iomem *addr)
 {
        unsigned int val;
        int tmp;
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index a84d3909345e..7302f290b93d 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -43,7 +43,8 @@
 #endif
 /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
-#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
+                || defined(CONFIG_BF_REV_0_3))
 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
                            slot1 and store of a P register in slot 2 is not
                            supported */
@@ -76,11 +77,16 @@
                            control */
 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
                            killed in a particular stage*/
+#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
+                            sequences */
 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
                            registers are interrupted */
-#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
+#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer  */
+#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
-#endif
+                          *  Next System MMR Access */
+#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
+                          *  and 1.15V Not Allowed for LQFP Packages */
+#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
 /* These issues only occur on 0.3 or 0.4 BF533 */
 #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
@@ -134,14 +140,14 @@
                            internal voltage regulator (VDDint) to increase. */
 #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
                            internal voltage regulator (VDDint) to decrease */
-#endif
+#endif /* issues only occur on 0.3 or 0.4 BF533 */
 /* These issues are only on 0.4 silicon */
 #if (defined(CONFIG_BF_REV_0_4))
 #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
                            (TDM) */
-#endif
+#endif /* issues are only on 0.4 silicon */
 /* These issues are only on 0.3 silicon */
 #if defined(CONFIG_BF_REV_0_3)
@@ -170,6 +176,72 @@
 #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
                            Sync Transmit Mode */
 #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
+#endif /* only on 0.3 silicon */
+#if defined(CONFIG_BF_REV_0_2)
+#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not
+                          *  supported */
+#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
+                          *  power on */
+#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
+                          *  emulation mode and/or exception, NMI, reset
+                          *  handlers */
+#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
+                          *  incorrect if data cache or DMA is active */
+#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
+                          *  or 1:1 */
+#define ANOMALY_05000125 /* Erroneous exception when enabling cache */
+#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
+                          *  during booting */
+#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
+#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
+                          * block in the loader file */
+#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
+                          *  overflow */
+#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
+                          *  of consecutive dual dag events */
+#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
+                          *  flag is configured to be edge sensitive */
+#define ANOMALY_05000143 /* A read from external memory may return a wrong
+                          *  value with data cache enabled */
+#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
+                          *  external memory */
+#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
+                          *  generate a waveform from PPI_CLK */
+#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
+                          *  chain */
+#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
+                          *  Error */
+#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
+                          *  device, the upper 8-bits of each word must be
+                          *  0x00 */
+#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
+                          *  outside of valid channels */
+#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
+                          *  certain PPI mode is in use */
+#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
+                          *  the next system MMR access thinking it should be
+                          *  32-bit. */
+#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
+                          *  sync in certain conditions */
+#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
+                          *  write-through cache data writes */
+#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
+#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
+#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
+                          *  accumulator saturation */
+#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
+                          *  registers */
+#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
+                          *  Transmit Modes */
+#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
+                          *  POLC */
+#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
 #endif
 #endif /*  _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index 23bf76aa3451..e043cafa3c42 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -78,6 +78,7 @@ struct bfin_serial_res {
 };
 struct bfin_serial_res bfin_serial_resource[] = {
+        {
        0xFFC00400,
        IRQ_UART_RX,
 #ifdef CONFIG_SERIAL_BFIN_DMA
@@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
        CONFIG_UART0_CTS_PIN,
        CONFIG_UART0_RTS_PIN,
 #endif
+        }
 };
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 7f040f5ba018..4453e614c3b1 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -73,8 +73,13 @@
                            control */
 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
                            killed in a particular stage*/
+#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
+                          *  boundary of reserved memory */
 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
                            registers are interrupted */
+#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
+#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
+                          *  received properly */
 #endif
 #if defined(CONFIG_BF_REV_0_2)
@@ -114,7 +119,21 @@
                            DMA system instability */
 #define ANOMALY_05000280 /* SPI Master boot mode does not work well with
                            Atmel Dataflash devices */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
+                          *  is not restored */
+#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
+                          *  control */
+#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
+                          *  Killed in a Particular Stage */
+#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
+                          *  (Not Available On Older Silicon) */
+#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
+#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
+                          *  On Next System MMR Access */
+#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
+                          *  mode */
+#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
+                          *  status No Carrier */
 #endif  /* CONFIG_BF_REV_0_2 */
 #endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 23bf76aa3451..e043cafa3c42 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -78,6 +78,7 @@ struct bfin_serial_res {
 };
 struct bfin_serial_res bfin_serial_resource[] = {
+        {
        0xFFC00400,
        IRQ_UART_RX,
 #ifdef CONFIG_SERIAL_BFIN_DMA
@@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
        CONFIG_UART0_CTS_PIN,
        CONFIG_UART0_RTS_PIN,
 #endif
+        }
 };
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index d39c396f850d..58f878947cbc 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -39,7 +39,20 @@
 #define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
 #define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
 #define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
+#ifdef ANOMALY_05000125
+static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
+{
+        unsigned long flags, iwr;
+        local_irq_save(flags);
+        __asm__(".align 8\n");
+        bfin_write32(IMEM_CONTROL, val);
+        __builtin_bfin_ssync();
+        local_irq_restore(flags);
+}
+#else
 #define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
+#endif
 #define bfin_read_DCPLB_STATUS()             bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)         bfin_write32(DCPLB_STATUS,val)
 #define bfin_read_DCPLB_FAULT_ADDR()         bfin_read32(DCPLB_FAULT_ADDR)
@@ -125,7 +138,21 @@
 #define DTEST_DATA3            0xFFE0040C
 */
 #define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
+#ifdef ANOMALY_05000125
+static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val)
+{
+        unsigned long flags, iwr;
+        local_irq_save(flags);
+        __asm__(".align 8\n");
+        bfin_write32(IMEM_CONTROL, val);
+        __builtin_bfin_ssync();
+        local_irq_restore(flags);
+}
+#else
 #define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
+#endif
 #define bfin_read_ICPLB_STATUS()             bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)         bfin_write32(ICPLB_STATUS,val)
 #define bfin_read_ICPLB_FAULT_ADDR()         bfin_read32(ICPLB_FAULT_ADDR)
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
index 4df8790a67d5..0df9f2d322a3 100644
--- a/include/asm-blackfin/unistd.h
+++ b/include/asm-blackfin/unistd.h
@@ -369,7 +369,6 @@
 #define __ARCH_WANT_SYS_NICE
 #define __ARCH_WANT_SYS_RT_SIGACTION
 #define __ARCH_WANT_SYS_RT_SIGSUSPEND
-#endif
 /*
 * "Conditional" syscalls
@@ -379,4 +378,6 @@
 */
 #define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
+#endif  /* __KERNEL__ */
 #endif                          /* __ASM_BFIN_UNISTD_H */
diff --git a/include/asm-i386/dma-mapping.h b/include/asm-i386/dma-mapping.h
index 183eebeebbdc..f1d72d177f68 100644
--- a/include/asm-i386/dma-mapping.h
+++ b/include/asm-i386/dma-mapping.h
@@ -123,6 +123,8 @@ dma_mapping_error(dma_addr_t dma_addr)
        return 0;
 }
+extern int forbid_dac;
 static inline int
 dma_supported(struct device *dev, u64 mask)
 {
@@ -134,6 +136,10 @@ dma_supported(struct device *dev, u64 mask)
        if(mask < 0x00ffffff)
                return 0;
+        /* Work around chipset bugs */
+        if (forbid_dac > 0 && mask > 0xffffffffULL)
+                return 0;
        return 1;
 }
diff --git a/include/asm-i386/paravirt.h b/include/asm-i386/paravirt.h
index d7a0512f88e0..7f846a7d6bcc 100644
--- a/include/asm-i386/paravirt.h
+++ b/include/asm-i386/paravirt.h
@@ -539,7 +539,7 @@ static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
        val = paravirt_read_msr(msr, &_err);    \
 } while(0)
-#define wrmsrl(msr,val)         ((void)paravirt_write_msr(msr, val, 0))
+#define wrmsrl(msr,val)         wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
 #define wrmsr_safe(msr,a,b)     paravirt_write_msr(msr, a, b)
 /* rdmsr with exception handling */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index ffe245b4258f..d9e81af53f78 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -310,7 +310,7 @@ static inline int test_and_clear_bit(unsigned long nr,
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp, res;
+                unsigned long temp;
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h
index 6599a901b63e..368a99e5c3e1 100644
--- a/include/asm-mips/compat-signal.h
+++ b/include/asm-mips/compat-signal.h
@@ -10,6 +10,68 @@
 #include <asm/uaccess.h>
+#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_code;
+        int si_errno;
+        union {
+                int _pad[SI_PAD_SIZE32];
+                /* kill() */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        compat_uid_t _uid;      /* sender's uid */
+                } _kill;
+                /* SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_uid_t _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+                /* IRIX SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_clock_t _utime;
+                        int _status;            /* exit code */
+                        compat_clock_t _stime;
+                } _irix_sigchld;
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        s32 _addr; /* faulting insn/memory ref. */
+                } _sigfault;
+                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;/* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        compat_uid_t _uid;      /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+        } _sifields;
+} compat_siginfo_t;
 static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
        const sigset_t *s)
 {
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 91803ba30ff2..3ca6a076124d 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -72,4 +72,13 @@ extern int allocate_irqno(void);
 extern void alloc_legacy_irqno(void);
 extern void free_irqno(unsigned int irq);
+/*
+ * Before R2 the timer and performance counter interrupts were both fixed to
+ * IE7.  Since R2 their number has to be read from the c0_intctl register.
+ */
+#define CP0_LEGACY_COMPARE_IRQ 7
+extern int cp0_compare_irq;
+extern int cp0_perfcount_irq;
 #endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
index 76add42e486e..93ba1c1b2a4f 100644
--- a/include/asm-mips/mips-boards/atlasint.h
+++ b/include/asm-mips/mips-boards/atlasint.h
@@ -28,11 +28,6 @@
 #include <irq.h>
-/*
- * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 /* CPU interrupt offsets */
 #define MIPSCPU_INT_SW0         0
 #define MIPSCPU_INT_SW1         1
@@ -42,7 +37,6 @@
 #define MIPSCPU_INT_MB2         4
 #define MIPSCPU_INT_MB3         5
 #define MIPSCPU_INT_MB4         6
-#define MIPSCPU_INT_CPUCTR      7
 /*
 * Interrupts 8..39 are used for Atlas interrupt controller interrupts
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 9180d6466113..7461318f1cd1 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -32,11 +32,6 @@
 */
 #define MALTA_INT_BASE          0
-/*
- * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 /* CPU interrupt offsets */
 #define MIPSCPU_INT_SW0         0
 #define MIPSCPU_INT_SW1         1
@@ -49,7 +44,6 @@
 #define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
 #define MIPSCPU_INT_MB4         6
 #define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
-#define MIPSCPU_INT_CPUCTR      7
 /*
 * Interrupts 64..127 are used for Soc-it Classic interrupts
diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h
index 4f6a3933699d..e710bae07340 100644
--- a/include/asm-mips/mips-boards/seadint.h
+++ b/include/asm-mips/mips-boards/seadint.h
@@ -22,14 +22,7 @@
 #include <irq.h>
-/*
- * Interrupts 0..7 are used for SEAD CPU interrupts
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 #define MIPSCPU_INT_UART0       2
 #define MIPSCPU_INT_UART1       3
-#define MIPSCPU_INT_CPUCTR      7
 #endif /* !(_MIPS_SEADINT_H) */
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
index 54f2fe621d69..8ef6db76d5c1 100644
--- a/include/asm-mips/mips-boards/simint.h
+++ b/include/asm-mips/mips-boards/simint.h
@@ -21,15 +21,11 @@
 #define SIM_INT_BASE            0
 #define MIPSCPU_INT_MB0         2
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 #define MIPS_CPU_TIMER_IRQ      7
-#define MIPSCPU_INT_CPUCTR      7
 #define MSC01E_INT_BASE         64
-#define MIPSCPU_INT_CPUCTR      7
 #define MSC01E_INT_CPUCTR       11
 #endif
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index 399d03f1c4fc..c5ef324fd69f 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -122,6 +122,13 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_KERNEL_TYPE "64BIT "
 #endif
-#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE
+#ifdef CONFIG_MIPS_MT_SMTC
+#define MODULE_KERNEL_SMTC "MT_SMTC "
+#else
+#define MODULE_KERNEL_SMTC ""
+#endif
+#define MODULE_ARCH_VERMAGIC \
+        MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC
 #endif /* _ASM_MODULE_H */
diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h
index 7e9afa720d43..21fbfc5afd02 100644
--- a/include/asm-parisc/system.h
+++ b/include/asm-parisc/system.h
@@ -188,7 +188,6 @@ static inline void set_eiem(unsigned long val)
 # define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
 #endif
-#define KERNEL_START (0x10100000 - 0x1000)
 #define arch_align_stack(x) (x)
 #endif
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index e0fcea8c64c3..5cb480af65d5 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -216,6 +216,11 @@ static inline void cpu_relax(void)
        barrier();
 }
+static inline void psw_set_key(unsigned int key)
+{
+        asm volatile("spka 0(%0)" : : "d" (key));
+}
 /*
 * Set PSW to specified value.
 */
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index fa6ca87080e8..332ee73688fc 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -470,14 +470,7 @@ struct user_regs_struct
 #define regs_return_value(regs)((regs)->gprs[2])
 #define profile_pc(regs) instruction_pointer(regs)
 extern void show_regs(struct pt_regs * regs);
-#endif
+#endif /* __KERNEL__ */
-static inline void
-psw_set_key(unsigned int key)
-{
-        asm volatile("spka 0(%0)" : : "d" (key));
-}
 #endif /* __ASSEMBLY__ */
 #endif /* _S390_PTRACE_H */
diff --git a/include/asm-um/bug.h b/include/asm-um/bug.h
index 3357c5e2468e..9e33b864c359 100644
--- a/include/asm-um/bug.h
+++ b/include/asm-um/bug.h
@@ -1,6 +1,6 @@
 #ifndef __UM_BUG_H
 #define __UM_BUG_H
-#include <asm/arch/bug.h>
+#include <asm-generic/bug.h>
 #endif
diff --git a/include/asm-um/common.lds.S b/include/asm-um/common.lds.S
index f5de80c31e88..e3f010bd12b3 100644
--- a/include/asm-um/common.lds.S
+++ b/include/asm-um/common.lds.S
@@ -20,6 +20,8 @@
  __ex_table : { *(__ex_table) }
  __stop___ex_table = .;
+  BUG_TABLE
  __uml_setup_start = .;
  .uml.setup.init : { *(.uml.setup.init) }
  __uml_setup_end = .;
diff --git a/include/asm-um/paravirt.h b/include/asm-um/paravirt.h
new file mode 100644
index 000000000000..9d6aaad80b5f
--- /dev/null
+++ b/include/asm-um/paravirt.h
@@ -0,0 +1,6 @@
+#ifndef __UM_PARAVIRT_H
+#define __UM_PARAVIRT_H
+#include "asm/arch/paravirt.h"
+#endif
diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h
index ae1ed05f2814..8696f8ad401e 100644
--- a/include/asm-x86_64/unistd.h
+++ b/include/asm-x86_64/unistd.h
@@ -626,9 +626,9 @@ __SYSCALL(__NR_utimensat, sys_utimensat)
 __SYSCALL(__NR_epoll_pwait, sys_epoll_pwait)
 #define __NR_signalfd           282
 __SYSCALL(__NR_signalfd, sys_signalfd)
-#define __NR_timerfd            282
+#define __NR_timerfd            283
 __SYSCALL(__NR_timerfd, sys_timerfd)
-#define __NR_eventfd            283
+#define __NR_eventfd            284
 __SYSCALL(__NR_eventfd, sys_eventfd)
 #ifndef __NO_STUBS
diff --git a/include/linux/fs.h b/include/linux/fs.h
index b3ae77cccbb6..6a41f4cab14c 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1211,6 +1211,14 @@ static inline void mark_inode_dirty_sync(struct inode *inode)
        __mark_inode_dirty(inode, I_DIRTY_SYNC);
 }
+/**
+ * inc_nlink - directly increment an inode's link count
+ * @inode: inode
+ *
+ * This is a low-level filesystem helper to replace any
+ * direct filesystem manipulation of i_nlink.  Currently,
+ * it is only here for parity with dec_nlink().
+ */
 static inline void inc_nlink(struct inode *inode)
 {
        inode->i_nlink++;
@@ -1222,11 +1230,30 @@ static inline void inode_inc_link_count(struct inode *inode)
        mark_inode_dirty(inode);
 }
+/**
+ * drop_nlink - directly drop an inode's link count
+ * @inode: inode
+ *
+ * This is a low-level filesystem helper to replace any
+ * direct filesystem manipulation of i_nlink.  In cases
+ * where we are attempting to track writes to the
+ * filesystem, a decrement to zero means an imminent
+ * write when the file is truncated and actually unlinked
+ * on the filesystem.
+ */
 static inline void drop_nlink(struct inode *inode)
 {
        inode->i_nlink--;
 }
+/**
+ * clear_nlink - directly zero an inode's link count
+ * @inode: inode
+ *
+ * This is a low-level filesystem helper to replace any
+ * direct filesystem manipulation of i_nlink.  See
+ * drop_nlink() for why we care about i_nlink hitting zero.
+ */
 static inline void clear_nlink(struct inode *inode)
 {
        inode->i_nlink = 0;
diff --git a/include/linux/futex.h b/include/linux/futex.h
index 899fc7f20edd..99650353adfa 100644
--- a/include/linux/futex.h
+++ b/include/linux/futex.h
@@ -17,7 +17,6 @@ union ktime;
 #define FUTEX_LOCK_PI           6
 #define FUTEX_UNLOCK_PI         7
 #define FUTEX_TRYLOCK_PI        8
-#define FUTEX_CMP_REQUEUE_PI    9
 #define FUTEX_PRIVATE_FLAG      128
 #define FUTEX_CMD_MASK          ~FUTEX_PRIVATE_FLAG
@@ -98,14 +97,9 @@ struct robust_list_head {
 #define FUTEX_OWNER_DIED        0x40000000
 /*
- * Some processes have been requeued on this PI-futex
- */
-#define FUTEX_WAITER_REQUEUED   0x20000000
-/*
 * The rest of the robust-futex field is for the TID:
 */
-#define FUTEX_TID_MASK          0x0fffffff
+#define FUTEX_TID_MASK          0x3fffffff
 /*
 * This limit protects against a deliberately circular list.
@@ -139,7 +133,6 @@ handle_futex_death(u32 __user *uaddr, struct task_struct *curr, int pi);
 #define FUT_OFF_MMSHARED 2 /* We set bit 1 if key has a reference on mm */
 union futex_key {
-        u32 __user *uaddr;
        struct {
                unsigned long pgoff;
                struct inode *inode;
diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h
index ae04901aa09a..d83fee2dc643 100644
--- a/include/linux/inetdevice.h
+++ b/include/linux/inetdevice.h
@@ -8,6 +8,7 @@
 #include <linux/netdevice.h>
 #include <linux/rcupdate.h>
 #include <linux/timer.h>
+#include <linux/sysctl.h>
 struct ipv4_devconf
 {
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
index 4fb552d12f7a..7d1eaa97de13 100644
--- a/include/linux/mlx4/cmd.h
+++ b/include/linux/mlx4/cmd.h
@@ -54,6 +54,7 @@ enum {
        MLX4_CMD_INIT_PORT       = 0x9,
        MLX4_CMD_CLOSE_PORT      = 0xa,
        MLX4_CMD_QUERY_HCA       = 0xb,
+        MLX4_CMD_QUERY_PORT      = 0x43,
        MLX4_CMD_SET_PORT        = 0xc,
        MLX4_CMD_ACCESS_DDR      = 0x2e,
        MLX4_CMD_MAP_ICM         = 0xffa,
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 8c5f8fd86841..b372f5910fc1 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -41,6 +41,7 @@
 enum {
        MLX4_FLAG_MSI_X         = 1 << 0,
+        MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
 };
 enum {
@@ -131,10 +132,10 @@ enum {
 struct mlx4_caps {
        u64                     fw_ver;
        int                     num_ports;
-        int                     vl_cap;
+        int                     vl_cap[MLX4_MAX_PORTS + 1];
-        int                     mtu_cap;
+        int                     mtu_cap[MLX4_MAX_PORTS + 1];
-        int                     gid_table_len;
+        int                     gid_table_len[MLX4_MAX_PORTS + 1];
-        int                     pkey_table_len;
+        int                     pkey_table_len[MLX4_MAX_PORTS + 1];
        int                     local_ca_ack_delay;
        int                     num_uars;
        int                     bf_reg_size;
@@ -174,7 +175,7 @@ struct mlx4_caps {
        u32                     page_size_cap;
        u32                     flags;
        u16                     stat_rate_support;
-        u8                      port_width_cap;
+        u8                      port_width_cap[MLX4_MAX_PORTS + 1];
 };
 struct mlx4_buf_list {
@@ -322,7 +323,7 @@ int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
-int mlx4_INIT_PORT(struct mlx4_dev *dev, struct mlx4_init_port_param *param, int port);
+int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 9eeb61adf6a3..10c57d279144 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -269,6 +269,10 @@ struct mlx4_wqe_data_seg {
        __be64                  addr;
 };
+enum {
+        MLX4_INLINE_ALIGN       = 64,
+};
 struct mlx4_wqe_inline_seg {
        __be32                  byte_count;
 };
diff --git a/include/linux/mm.h b/include/linux/mm.h
index e4183c6c7de3..1c1207472bb4 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -603,6 +603,10 @@ static inline struct address_space *page_mapping(struct page *page)
        if (unlikely(PageSwapCache(page)))
                mapping = &swapper_space;
+#ifdef CONFIG_SLUB
+        else if (unlikely(PageSlab(page)))
+                mapping = NULL;
+#endif
        else if (unlikely((unsigned long)mapping & PAGE_MAPPING_ANON))
                mapping = NULL;
        return mapping;
diff --git a/include/linux/slab.h b/include/linux/slab.h
index a015236cc572..cebcd3833c76 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -82,8 +82,8 @@ static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep,
 * to do various tricks to work around compiler limitations in order to
 * ensure proper constant folding.
 */
-#define KMALLOC_SHIFT_HIGH      ((MAX_ORDER + PAGE_SHIFT) <= 25 ? \
+#define KMALLOC_SHIFT_HIGH      ((MAX_ORDER + PAGE_SHIFT - 1) <= 25 ? \
-                                (MAX_ORDER + PAGE_SHIFT) : 25)
+                                (MAX_ORDER + PAGE_SHIFT - 1) : 25)
 #define KMALLOC_MAX_SIZE        (1UL << KMALLOC_SHIFT_HIGH)
 #define KMALLOC_MAX_ORDER       (KMALLOC_SHIFT_HIGH - PAGE_SHIFT)
diff --git a/include/linux/sm501-regs.h b/include/linux/sm501-regs.h
index cc9be4a11861..014e73b31fc0 100644
--- a/include/linux/sm501-regs.h
+++ b/include/linux/sm501-regs.h
@@ -64,6 +64,11 @@
 #define SM501_DEBUG_CONTROL             (0x000034)
 /* power management */
+#define SM501_POWERMODE_P2X_SRC         (1<<29)
+#define SM501_POWERMODE_V2X_SRC         (1<<20)
+#define SM501_POWERMODE_M_SRC           (1<<12)
+#define SM501_POWERMODE_M1_SRC          (1<<4)
 #define SM501_CURRENT_GATE              (0x000038)
 #define SM501_CURRENT_CLOCK             (0x00003C)
 #define SM501_POWER_MODE_0_GATE         (0x000040)
@@ -104,6 +109,9 @@
 #define SM501_DEVICEID                  (0x000060)
 /* 0x050100A0 */
+#define SM501_DEVICEID_SM501            (0x05010000)
+#define SM501_DEVICEID_IDMASK           (0xffff0000)
 #define SM501_PLLCLOCK_COUNT            (0x000064)
 #define SM501_MISC_TIMING               (0x000068)
 #define SM501_CURRENT_SDRAM_CLOCK       (0x00006C)