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-rw-r--r--include/asm-avr32/arch-at32ap/io.h39
-rw-r--r--include/asm-avr32/arch-at32ap/smc.h22
-rw-r--r--include/asm-avr32/arch-at32ap/time.h112
-rw-r--r--include/asm-avr32/atomic.h2
-rw-r--r--include/asm-avr32/bug.h50
-rw-r--r--include/asm-avr32/io.h326
-rw-r--r--include/asm-avr32/processor.h15
-rw-r--r--include/asm-avr32/setup.h13
-rw-r--r--include/asm-avr32/sysreg.h543
-rw-r--r--include/asm-avr32/system.h13
-rw-r--r--include/asm-avr32/thread_info.h2
-rw-r--r--include/asm-avr32/uaccess.h13
-rw-r--r--include/asm-generic/pgtable.h11
-rw-r--r--include/asm-mips/cacheflush.h2
-rw-r--r--include/asm-mips/jmr3927/irq.h57
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h130
-rw-r--r--include/asm-mips/jmr3927/tx3927.h8
-rw-r--r--include/asm-mips/jmr3927/txx927.h5
-rw-r--r--include/asm-mips/paccess.h2
-rw-r--r--include/asm-mips/sgi/hpc3.h2
-rw-r--r--include/asm-mips/sgi/ip22.h2
-rw-r--r--include/asm-mips/sgi/mc.h2
-rw-r--r--include/asm-mips/sibyte/bcm1480_int.h2
-rw-r--r--include/asm-mips/sibyte/bcm1480_mc.h32
-rw-r--r--include/asm-mips/sibyte/bcm1480_regs.h20
-rw-r--r--include/asm-mips/sibyte/bcm1480_scd.h94
-rw-r--r--include/asm-mips/sibyte/board.h14
-rw-r--r--include/asm-mips/sibyte/carmel.h1
-rw-r--r--include/asm-mips/sibyte/sb1250_int.h5
-rw-r--r--include/asm-mips/sibyte/sb1250_mac.h24
-rw-r--r--include/asm-mips/sibyte/sb1250_mc.h2
-rw-r--r--include/asm-mips/sibyte/sb1250_regs.h46
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h30
-rw-r--r--include/asm-mips/sibyte/swarm.h12
-rw-r--r--include/asm-s390/bug.h69
-rw-r--r--include/asm-s390/ccwgroup.h1
-rw-r--r--include/asm-s390/chpid.h53
-rw-r--r--include/asm-s390/cio.h8
-rw-r--r--include/asm-s390/ipl.h35
-rw-r--r--include/asm-s390/lowcore.h46
-rw-r--r--include/asm-s390/pgtable.h15
-rw-r--r--include/asm-s390/processor.h2
-rw-r--r--include/asm-s390/sclp.h14
-rw-r--r--include/asm-s390/setup.h2
-rw-r--r--include/asm-s390/smp.h6
-rw-r--r--include/linux/page-flags.h2
46 files changed, 1077 insertions, 829 deletions
diff --git a/include/asm-avr32/arch-at32ap/io.h b/include/asm-avr32/arch-at32ap/io.h
new file mode 100644
index 000000000000..ee59e401f041
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/io.h
@@ -0,0 +1,39 @@
1#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
2#define __ASM_AVR32_ARCH_AT32AP_IO_H
3
4/* For "bizarre" halfword swapping */
5#include <linux/byteorder/swabb.h>
6
7#if defined(CONFIG_AP7000_32_BIT_SMC)
8# define __swizzle_addr_b(addr) (addr ^ 3UL)
9# define __swizzle_addr_w(addr) (addr ^ 2UL)
10# define __swizzle_addr_l(addr) (addr)
11# define ioswabb(a, x) (x)
12# define ioswabw(a, x) (x)
13# define ioswabl(a, x) (x)
14# define __mem_ioswabb(a, x) (x)
15# define __mem_ioswabw(a, x) swab16(x)
16# define __mem_ioswabl(a, x) swab32(x)
17#elif defined(CONFIG_AP7000_16_BIT_SMC)
18# define __swizzle_addr_b(addr) (addr ^ 1UL)
19# define __swizzle_addr_w(addr) (addr)
20# define __swizzle_addr_l(addr) (addr)
21# define ioswabb(a, x) (x)
22# define ioswabw(a, x) (x)
23# define ioswabl(a, x) swahw32(x)
24# define __mem_ioswabb(a, x) (x)
25# define __mem_ioswabw(a, x) swab16(x)
26# define __mem_ioswabl(a, x) swahb32(x)
27#else
28# define __swizzle_addr_b(addr) (addr)
29# define __swizzle_addr_w(addr) (addr)
30# define __swizzle_addr_l(addr) (addr)
31# define ioswabb(a, x) (x)
32# define ioswabw(a, x) swab16(x)
33# define ioswabl(a, x) swab32(x)
34# define __mem_ioswabb(a, x) (x)
35# define __mem_ioswabw(a, x) (x)
36# define __mem_ioswabl(a, x) (x)
37#endif
38
39#endif /* __ASM_AVR32_ARCH_AT32AP_IO_H */
diff --git a/include/asm-avr32/arch-at32ap/smc.h b/include/asm-avr32/arch-at32ap/smc.h
index 3732b328303d..07152b7fd9c9 100644
--- a/include/asm-avr32/arch-at32ap/smc.h
+++ b/include/asm-avr32/arch-at32ap/smc.h
@@ -48,10 +48,32 @@ struct smc_config {
48 unsigned int nwe_controlled:1; 48 unsigned int nwe_controlled:1;
49 49
50 /* 50 /*
51 * 0: NWAIT is disabled
52 * 1: Reserved
53 * 2: NWAIT is frozen mode
54 * 3: NWAIT in ready mode
55 */
56 unsigned int nwait_mode:2;
57
58 /*
51 * 0: Byte select access type 59 * 0: Byte select access type
52 * 1: Byte write access type 60 * 1: Byte write access type
53 */ 61 */
54 unsigned int byte_write:1; 62 unsigned int byte_write:1;
63
64 /*
65 * Number of clock cycles before data is released after
66 * the rising edge of the read controlling signal
67 *
68 * Total cycles from SMC is tdf_cycles + 1
69 */
70 unsigned int tdf_cycles:4;
71
72 /*
73 * 0: TDF optimization disabled
74 * 1: TDF optimization enabled
75 */
76 unsigned int tdf_mode:1;
55}; 77};
56 78
57extern int smc_set_configuration(int cs, const struct smc_config *config); 79extern int smc_set_configuration(int cs, const struct smc_config *config);
diff --git a/include/asm-avr32/arch-at32ap/time.h b/include/asm-avr32/arch-at32ap/time.h
new file mode 100644
index 000000000000..cc8a43418a4d
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/time.h
@@ -0,0 +1,112 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
10#define _ASM_AVR32_ARCH_AT32AP_TIME_H
11
12#include <linux/platform_device.h>
13
14extern struct irqaction timer_irqaction;
15extern struct platform_device at32_systc0_device;
16extern void local_timer_interrupt(int irq, void *dev_id);
17
18#define TIMER_BCR 0x000000c0
19#define TIMER_BCR_SYNC 0
20#define TIMER_BMR 0x000000c4
21#define TIMER_BMR_TC0XC0S 0
22#define TIMER_BMR_TC1XC1S 2
23#define TIMER_BMR_TC2XC2S 4
24#define TIMER_CCR 0x00000000
25#define TIMER_CCR_CLKDIS 1
26#define TIMER_CCR_CLKEN 0
27#define TIMER_CCR_SWTRG 2
28#define TIMER_CMR 0x00000004
29#define TIMER_CMR_ABETRG 10
30#define TIMER_CMR_ACPA 16
31#define TIMER_CMR_ACPC 18
32#define TIMER_CMR_AEEVT 20
33#define TIMER_CMR_ASWTRG 22
34#define TIMER_CMR_BCPB 24
35#define TIMER_CMR_BCPC 26
36#define TIMER_CMR_BEEVT 28
37#define TIMER_CMR_BSWTRG 30
38#define TIMER_CMR_BURST 4
39#define TIMER_CMR_CLKI 3
40#define TIMER_CMR_CPCDIS 7
41#define TIMER_CMR_CPCSTOP 6
42#define TIMER_CMR_CPCTRG 14
43#define TIMER_CMR_EEVT 10
44#define TIMER_CMR_EEVTEDG 8
45#define TIMER_CMR_ENETRG 12
46#define TIMER_CMR_ETRGEDG 8
47#define TIMER_CMR_LDBDIS 7
48#define TIMER_CMR_LDBSTOP 6
49#define TIMER_CMR_LDRA 16
50#define TIMER_CMR_LDRB 18
51#define TIMER_CMR_TCCLKS 0
52#define TIMER_CMR_WAVE 15
53#define TIMER_CMR_WAVSEL 13
54#define TIMER_CV 0x00000010
55#define TIMER_CV_CV 0
56#define TIMER_IDR 0x00000028
57#define TIMER_IDR_COVFS 0
58#define TIMER_IDR_CPAS 2
59#define TIMER_IDR_CPBS 3
60#define TIMER_IDR_CPCS 4
61#define TIMER_IDR_ETRGS 7
62#define TIMER_IDR_LDRAS 5
63#define TIMER_IDR_LDRBS 6
64#define TIMER_IDR_LOVRS 1
65#define TIMER_IER 0x00000024
66#define TIMER_IER_COVFS 0
67#define TIMER_IER_CPAS 2
68#define TIMER_IER_CPBS 3
69#define TIMER_IER_CPCS 4
70#define TIMER_IER_ETRGS 7
71#define TIMER_IER_LDRAS 5
72#define TIMER_IER_LDRBS 6
73#define TIMER_IER_LOVRS 1
74#define TIMER_IMR 0x0000002c
75#define TIMER_IMR_COVFS 0
76#define TIMER_IMR_CPAS 2
77#define TIMER_IMR_CPBS 3
78#define TIMER_IMR_CPCS 4
79#define TIMER_IMR_ETRGS 7
80#define TIMER_IMR_LDRAS 5
81#define TIMER_IMR_LDRBS 6
82#define TIMER_IMR_LOVRS 1
83#define TIMER_RA 0x00000014
84#define TIMER_RA_RA 0
85#define TIMER_RB 0x00000018
86#define TIMER_RB_RB 0
87#define TIMER_RC 0x0000001c
88#define TIMER_RC_RC 0
89#define TIMER_SR 0x00000020
90#define TIMER_SR_CLKSTA 16
91#define TIMER_SR_COVFS 0
92#define TIMER_SR_CPAS 2
93#define TIMER_SR_CPBS 3
94#define TIMER_SR_CPCS 4
95#define TIMER_SR_ETRGS 7
96#define TIMER_SR_LDRAS 5
97#define TIMER_SR_LDRBS 6
98#define TIMER_SR_LOVRS 1
99#define TIMER_SR_MTIOA 17
100#define TIMER_SR_MTIOB 18
101
102/* Bit manipulation macros */
103#define TIMER_BIT(name) (1 << TIMER_##name)
104#define TIMER_BF(name,value) ((value) << TIMER_##name)
105
106/* Register access macros */
107#define timer_read(port,instance,reg) \
108 __raw_readl(port + (0x40 * instance) + TIMER_##reg)
109#define timer_write(port,instance,reg,value) \
110 __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
111
112#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
diff --git a/include/asm-avr32/atomic.h b/include/asm-avr32/atomic.h
index c40b6032c480..b9c2548a52f3 100644
--- a/include/asm-avr32/atomic.h
+++ b/include/asm-avr32/atomic.h
@@ -173,7 +173,7 @@ static inline int atomic_sub_if_positive(int i, atomic_t *v)
173} 173}
174 174
175#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) 175#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
176#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) 176#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
177 177
178#define atomic_sub(i, v) (void)atomic_sub_return(i, v) 178#define atomic_sub(i, v) (void)atomic_sub_return(i, v)
179#define atomic_add(i, v) (void)atomic_add_return(i, v) 179#define atomic_add(i, v) (void)atomic_add_return(i, v)
diff --git a/include/asm-avr32/bug.h b/include/asm-avr32/bug.h
index 521766bc9366..afdcd79a2966 100644
--- a/include/asm-avr32/bug.h
+++ b/include/asm-avr32/bug.h
@@ -18,27 +18,53 @@
18 18
19#ifdef CONFIG_DEBUG_BUGVERBOSE 19#ifdef CONFIG_DEBUG_BUGVERBOSE
20 20
21#define BUG() \ 21#define _BUG_OR_WARN(flags) \
22 do { \ 22 asm volatile( \
23 asm volatile(".hword %0\n\t" \ 23 "1: .hword %0\n" \
24 ".hword %1\n\t" \ 24 " .section __bug_table,\"a\",@progbits\n" \
25 ".long %2" \ 25 "2: .long 1b\n" \
26 : \ 26 " .long %1\n" \
27 : "n"(AVR32_BUG_OPCODE), \ 27 " .short %2\n" \
28 "i"(__LINE__), "X"(__FILE__)); \ 28 " .short %3\n" \
29 } while (0) 29 " .org 2b + %4\n" \
30 " .previous" \
31 : \
32 : "i"(AVR32_BUG_OPCODE), "i"(__FILE__), \
33 "i"(__LINE__), "i"(flags), \
34 "i"(sizeof(struct bug_entry)))
30 35
31#else 36#else
32 37
38#define _BUG_OR_WARN(flags) \
39 asm volatile( \
40 "1: .hword %0\n" \
41 " .section __bug_table,\"a\",@progbits\n" \
42 "2: .long 1b\n" \
43 " .short %1\n" \
44 " .org 2b + %2\n" \
45 " .previous" \
46 : \
47 : "i"(AVR32_BUG_OPCODE), "i"(flags), \
48 "i"(sizeof(struct bug_entry)))
49
50#endif /* CONFIG_DEBUG_BUGVERBOSE */
51
33#define BUG() \ 52#define BUG() \
34 do { \ 53 do { \
35 asm volatile(".hword %0\n\t" \ 54 _BUG_OR_WARN(0); \
36 : : "n"(AVR32_BUG_OPCODE)); \ 55 for (;;); \
37 } while (0) 56 } while (0)
38 57
39#endif /* CONFIG_DEBUG_BUGVERBOSE */ 58#define WARN_ON(condition) \
59 ({ \
60 typeof(condition) __ret_warn_on = (condition); \
61 if (unlikely(__ret_warn_on)) \
62 _BUG_OR_WARN(BUGFLAG_WARNING); \
63 unlikely(__ret_warn_on); \
64 })
40 65
41#define HAVE_ARCH_BUG 66#define HAVE_ARCH_BUG
67#define HAVE_ARCH_WARN_ON
42 68
43#endif /* CONFIG_BUG */ 69#endif /* CONFIG_BUG */
44 70
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
index c08e81048393..e30d4b3bd836 100644
--- a/include/asm-avr32/io.h
+++ b/include/asm-avr32/io.h
@@ -1,13 +1,15 @@
1#ifndef __ASM_AVR32_IO_H 1#ifndef __ASM_AVR32_IO_H
2#define __ASM_AVR32_IO_H 2#define __ASM_AVR32_IO_H
3 3
4#include <linux/kernel.h>
4#include <linux/string.h> 5#include <linux/string.h>
5 6#include <linux/types.h>
6#ifdef __KERNEL__
7 7
8#include <asm/addrspace.h> 8#include <asm/addrspace.h>
9#include <asm/byteorder.h> 9#include <asm/byteorder.h>
10 10
11#include <asm/arch/io.h>
12
11/* virt_to_phys will only work when address is in P1 or P2 */ 13/* virt_to_phys will only work when address is in P1 or P2 */
12static __inline__ unsigned long virt_to_phys(volatile void *address) 14static __inline__ unsigned long virt_to_phys(volatile void *address)
13{ 15{
@@ -36,104 +38,215 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
36extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); 38extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
37extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); 39extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
38 40
39static inline void writeb(unsigned char b, volatile void __iomem *addr) 41static inline void __raw_writeb(u8 v, volatile void __iomem *addr)
40{ 42{
41 *(volatile unsigned char __force *)addr = b; 43 *(volatile u8 __force *)addr = v;
42} 44}
43static inline void writew(unsigned short b, volatile void __iomem *addr) 45static inline void __raw_writew(u16 v, volatile void __iomem *addr)
44{ 46{
45 *(volatile unsigned short __force *)addr = b; 47 *(volatile u16 __force *)addr = v;
46} 48}
47static inline void writel(unsigned int b, volatile void __iomem *addr) 49static inline void __raw_writel(u32 v, volatile void __iomem *addr)
48{ 50{
49 *(volatile unsigned int __force *)addr = b; 51 *(volatile u32 __force *)addr = v;
50} 52}
51#define __raw_writeb writeb
52#define __raw_writew writew
53#define __raw_writel writel
54 53
55static inline unsigned char readb(const volatile void __iomem *addr) 54static inline u8 __raw_readb(const volatile void __iomem *addr)
56{ 55{
57 return *(const volatile unsigned char __force *)addr; 56 return *(const volatile u8 __force *)addr;
58} 57}
59static inline unsigned short readw(const volatile void __iomem *addr) 58static inline u16 __raw_readw(const volatile void __iomem *addr)
60{ 59{
61 return *(const volatile unsigned short __force *)addr; 60 return *(const volatile u16 __force *)addr;
62} 61}
63static inline unsigned int readl(const volatile void __iomem *addr) 62static inline u32 __raw_readl(const volatile void __iomem *addr)
64{ 63{
65 return *(const volatile unsigned int __force *)addr; 64 return *(const volatile u32 __force *)addr;
65}
66
67/* Convert I/O port address to virtual address */
68#ifndef __io
69# define __io(p) ((void *)phys_to_uncached(p))
70#endif
71
72/*
73 * Not really sure about the best way to slow down I/O on
74 * AVR32. Defining it as a no-op until we have an actual test case.
75 */
76#define SLOW_DOWN_IO do { } while (0)
77
78#define __BUILD_MEMORY_SINGLE(pfx, bwl, type) \
79static inline void \
80pfx##write##bwl(type val, volatile void __iomem *addr) \
81{ \
82 volatile type *__addr; \
83 type __val; \
84 \
85 __addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
86 __val = pfx##ioswab##bwl(__addr, val); \
87 \
88 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
89 \
90 *__addr = __val; \
91} \
92 \
93static inline type pfx##read##bwl(const volatile void __iomem *addr) \
94{ \
95 volatile type *__addr; \
96 type __val; \
97 \
98 __addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
99 \
100 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
101 \
102 __val = *__addr; \
103 return pfx##ioswab##bwl(__addr, __val); \
104}
105
106#define __BUILD_IOPORT_SINGLE(pfx, bwl, type, p, slow) \
107static inline void pfx##out##bwl##p(type val, unsigned long port) \
108{ \
109 volatile type *__addr; \
110 type __val; \
111 \
112 __addr = __io(__swizzle_addr_##bwl(port)); \
113 __val = pfx##ioswab##bwl(__addr, val); \
114 \
115 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
116 \
117 *__addr = __val; \
118 slow; \
119} \
120 \
121static inline type pfx##in##bwl##p(unsigned long port) \
122{ \
123 volatile type *__addr; \
124 type __val; \
125 \
126 __addr = __io(__swizzle_addr_##bwl(port)); \
127 \
128 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
129 \
130 __val = *__addr; \
131 slow; \
132 \
133 return pfx##ioswab##bwl(__addr, __val); \
134}
135
136#define __BUILD_MEMORY_PFX(bus, bwl, type) \
137 __BUILD_MEMORY_SINGLE(bus, bwl, type)
138
139#define BUILDIO_MEM(bwl, type) \
140 __BUILD_MEMORY_PFX(, bwl, type) \
141 __BUILD_MEMORY_PFX(__mem_, bwl, type)
142
143#define __BUILD_IOPORT_PFX(bus, bwl, type) \
144 __BUILD_IOPORT_SINGLE(bus, bwl, type, ,) \
145 __BUILD_IOPORT_SINGLE(bus, bwl, type, _p, SLOW_DOWN_IO)
146
147#define BUILDIO_IOPORT(bwl, type) \
148 __BUILD_IOPORT_PFX(, bwl, type) \
149 __BUILD_IOPORT_PFX(__mem_, bwl, type)
150
151BUILDIO_MEM(b, u8)
152BUILDIO_MEM(w, u16)
153BUILDIO_MEM(l, u32)
154
155BUILDIO_IOPORT(b, u8)
156BUILDIO_IOPORT(w, u16)
157BUILDIO_IOPORT(l, u32)
158
159#define readb_relaxed readb
160#define readw_relaxed readw
161#define readl_relaxed readl
162
163#define __BUILD_MEMORY_STRING(bwl, type) \
164static inline void writes##bwl(volatile void __iomem *addr, \
165 const void *data, unsigned int count) \
166{ \
167 const type *__data = data; \
168 \
169 while (count--) \
170 __mem_write##bwl(*__data++, addr); \
171} \
172 \
173static inline void reads##bwl(const volatile void __iomem *addr, \
174 void *data, unsigned int count) \
175{ \
176 type *__data = data; \
177 \
178 while (count--) \
179 *__data++ = __mem_read##bwl(addr); \
66} 180}
67#define __raw_readb readb
68#define __raw_readw readw
69#define __raw_readl readl
70 181
71#define writesb(p, d, l) __raw_writesb((unsigned int)p, d, l) 182#define __BUILD_IOPORT_STRING(bwl, type) \
72#define writesw(p, d, l) __raw_writesw((unsigned int)p, d, l) 183static inline void outs##bwl(unsigned long port, const void *data, \
73#define writesl(p, d, l) __raw_writesl((unsigned int)p, d, l) 184 unsigned int count) \
185{ \
186 const type *__data = data; \
187 \
188 while (count--) \
189 __mem_out##bwl(*__data++, port); \
190} \
191 \
192static inline void ins##bwl(unsigned long port, void *data, \
193 unsigned int count) \
194{ \
195 type *__data = data; \
196 \
197 while (count--) \
198 *__data++ = __mem_in##bwl(port); \
199}
74 200
75#define readsb(p, d, l) __raw_readsb((unsigned int)p, d, l) 201#define BUILDSTRING(bwl, type) \
76#define readsw(p, d, l) __raw_readsw((unsigned int)p, d, l) 202 __BUILD_MEMORY_STRING(bwl, type) \
77#define readsl(p, d, l) __raw_readsl((unsigned int)p, d, l) 203 __BUILD_IOPORT_STRING(bwl, type)
78 204
205BUILDSTRING(b, u8)
206BUILDSTRING(w, u16)
207BUILDSTRING(l, u32)
79 208
80/* 209/*
81 * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be 210 * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
82 */ 211 */
83#ifndef ioread8 212#ifndef ioread8
84 213
85#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) 214#define ioread8(p) ((unsigned int)readb(p))
86 215
87#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; }) 216#define ioread16(p) ((unsigned int)readw(p))
88#define ioread16be(p) ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; }) 217#define ioread16be(p) ((unsigned int)__raw_readw(p))
89 218
90#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; }) 219#define ioread32(p) ((unsigned int)readl(p))
91#define ioread32be(p) ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; }) 220#define ioread32be(p) ((unsigned int)__raw_readl(p))
92 221
93#define iowrite8(v,p) __raw_writeb(v, p) 222#define iowrite8(v,p) writeb(v, p)
94 223
95#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p) 224#define iowrite16(v,p) writew(v, p)
96#define iowrite16be(v,p) __raw_writew(cpu_to_be16(v), p) 225#define iowrite16be(v,p) __raw_writew(v, p)
97 226
98#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p) 227#define iowrite32(v,p) writel(v, p)
99#define iowrite32be(v,p) __raw_writel(cpu_to_be32(v), p) 228#define iowrite32be(v,p) __raw_writel(v, p)
100 229
101#define ioread8_rep(p,d,c) __raw_readsb(p,d,c) 230#define ioread8_rep(p,d,c) readsb(p,d,c)
102#define ioread16_rep(p,d,c) __raw_readsw(p,d,c) 231#define ioread16_rep(p,d,c) readsw(p,d,c)
103#define ioread32_rep(p,d,c) __raw_readsl(p,d,c) 232#define ioread32_rep(p,d,c) readsl(p,d,c)
104 233
105#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c) 234#define iowrite8_rep(p,s,c) writesb(p,s,c)
106#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c) 235#define iowrite16_rep(p,s,c) writesw(p,s,c)
107#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c) 236#define iowrite32_rep(p,s,c) writesl(p,s,c)
108 237
109#endif 238#endif
110 239
111
112/*
113 * These two are only here because ALSA _thinks_ it needs them...
114 */
115static inline void memcpy_fromio(void * to, const volatile void __iomem *from, 240static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
116 unsigned long count) 241 unsigned long count)
117{ 242{
118 char *p = to; 243 memcpy(to, (const void __force *)from, count);
119 while (count) {
120 count--;
121 *p = readb(from);
122 p++;
123 from++;
124 }
125} 244}
126 245
127static inline void memcpy_toio(volatile void __iomem *to, const void * from, 246static inline void memcpy_toio(volatile void __iomem *to, const void * from,
128 unsigned long count) 247 unsigned long count)
129{ 248{
130 const char *p = from; 249 memcpy((void __force *)to, from, count);
131 while (count) {
132 count--;
133 writeb(*p, to);
134 p++;
135 to++;
136 }
137} 250}
138 251
139static inline void memset_io(volatile void __iomem *addr, unsigned char val, 252static inline void memset_io(volatile void __iomem *addr, unsigned char val,
@@ -142,99 +255,8 @@ static inline void memset_io(volatile void __iomem *addr, unsigned char val,
142 memset((void __force *)addr, val, count); 255 memset((void __force *)addr, val, count);
143} 256}
144 257
145/*
146 * Bad read/write accesses...
147 */
148extern void __readwrite_bug(const char *fn);
149
150#define IO_SPACE_LIMIT 0xffffffff 258#define IO_SPACE_LIMIT 0xffffffff
151 259
152/* Convert I/O port address to virtual address */
153#define __io(p) ((void __iomem *)phys_to_uncached(p))
154
155/*
156 * IO port access primitives
157 * -------------------------
158 *
159 * The AVR32 doesn't have special IO access instructions; all IO is memory
160 * mapped. Note that these are defined to perform little endian accesses
161 * only. Their primary purpose is to access PCI and ISA peripherals.
162 *
163 * Note that for a big endian machine, this implies that the following
164 * big endian mode connectivity is in place.
165 *
166 * The machine specific io.h include defines __io to translate an "IO"
167 * address to a memory address.
168 *
169 * Note that we prevent GCC re-ordering or caching values in expressions
170 * by introducing sequence points into the in*() definitions. Note that
171 * __raw_* do not guarantee this behaviour.
172 *
173 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
174 */
175#define outb(v, p) __raw_writeb(v, __io(p))
176#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
177#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
178
179#define inb(p) __raw_readb(__io(p))
180#define inw(p) le16_to_cpu(__raw_readw(__io(p)))
181#define inl(p) le32_to_cpu(__raw_readl(__io(p)))
182
183static inline void __outsb(unsigned long port, void *addr, unsigned int count)
184{
185 while (count--) {
186 outb(*(u8 *)addr, port);
187 addr++;
188 }
189}
190
191static inline void __insb(unsigned long port, void *addr, unsigned int count)
192{
193 while (count--) {
194 *(u8 *)addr = inb(port);
195 addr++;
196 }
197}
198
199static inline void __outsw(unsigned long port, void *addr, unsigned int count)
200{
201 while (count--) {
202 outw(*(u16 *)addr, port);
203 addr += 2;
204 }
205}
206
207static inline void __insw(unsigned long port, void *addr, unsigned int count)
208{
209 while (count--) {
210 *(u16 *)addr = inw(port);
211 addr += 2;
212 }
213}
214
215static inline void __outsl(unsigned long port, void *addr, unsigned int count)
216{
217 while (count--) {
218 outl(*(u32 *)addr, port);
219 addr += 4;
220 }
221}
222
223static inline void __insl(unsigned long port, void *addr, unsigned int count)
224{
225 while (count--) {
226 *(u32 *)addr = inl(port);
227 addr += 4;
228 }
229}
230
231#define outsb(port, addr, count) __outsb(port, addr, count)
232#define insb(port, addr, count) __insb(port, addr, count)
233#define outsw(port, addr, count) __outsw(port, addr, count)
234#define insw(port, addr, count) __insw(port, addr, count)
235#define outsl(port, addr, count) __outsl(port, addr, count)
236#define insl(port, addr, count) __insl(port, addr, count)
237
238extern void __iomem *__ioremap(unsigned long offset, size_t size, 260extern void __iomem *__ioremap(unsigned long offset, size_t size,
239 unsigned long flags); 261 unsigned long flags);
240extern void __iounmap(void __iomem *addr); 262extern void __iounmap(void __iomem *addr);
@@ -292,6 +314,4 @@ extern void __iounmap(void __iomem *addr);
292 */ 314 */
293#define xlate_dev_kmem_ptr(p) p 315#define xlate_dev_kmem_ptr(p) p
294 316
295#endif /* __KERNEL__ */
296
297#endif /* __ASM_AVR32_IO_H */ 317#endif /* __ASM_AVR32_IO_H */
diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h
index f6913778a45f..6a64833756a6 100644
--- a/include/asm-avr32/processor.h
+++ b/include/asm-avr32/processor.h
@@ -40,6 +40,14 @@ enum tlb_config {
40 TLB_INVALID 40 TLB_INVALID
41}; 41};
42 42
43#define AVR32_FEATURE_RMW (1 << 0)
44#define AVR32_FEATURE_DSP (1 << 1)
45#define AVR32_FEATURE_SIMD (1 << 2)
46#define AVR32_FEATURE_OCD (1 << 3)
47#define AVR32_FEATURE_PCTR (1 << 4)
48#define AVR32_FEATURE_JAVA (1 << 5)
49#define AVR32_FEATURE_FPU (1 << 6)
50
43struct avr32_cpuinfo { 51struct avr32_cpuinfo {
44 struct clk *clk; 52 struct clk *clk;
45 unsigned long loops_per_jiffy; 53 unsigned long loops_per_jiffy;
@@ -48,6 +56,7 @@ struct avr32_cpuinfo {
48 unsigned short arch_revision; 56 unsigned short arch_revision;
49 unsigned short cpu_revision; 57 unsigned short cpu_revision;
50 enum tlb_config tlb_config; 58 enum tlb_config tlb_config;
59 unsigned long features;
51 60
52 struct cache_info icache; 61 struct cache_info icache;
53 struct cache_info dcache; 62 struct cache_info dcache;
@@ -125,10 +134,10 @@ extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
125#define thread_saved_pc(tsk) ((tsk)->thread.cpu_context.pc) 134#define thread_saved_pc(tsk) ((tsk)->thread.cpu_context.pc)
126 135
127struct pt_regs; 136struct pt_regs;
128void show_trace(struct task_struct *task, unsigned long *stack,
129 struct pt_regs *regs);
130
131extern unsigned long get_wchan(struct task_struct *p); 137extern unsigned long get_wchan(struct task_struct *p);
138extern void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl);
139extern void show_stack_log_lvl(struct task_struct *tsk, unsigned long sp,
140 struct pt_regs *regs, const char *log_lvl);
132 141
133#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc) 142#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc)
134#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp) 143#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp)
diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h
index 0a5224245e44..1ff1a217015d 100644
--- a/include/asm-avr32/setup.h
+++ b/include/asm-avr32/setup.h
@@ -124,19 +124,12 @@ struct tagtable {
124#define for_each_tag(t,base) \ 124#define for_each_tag(t,base) \
125 for (t = base; t->hdr.size; t = tag_next(t)) 125 for (t = base; t->hdr.size; t = tag_next(t))
126 126
127extern struct tag_mem_range *mem_phys;
128extern struct tag_mem_range *mem_reserved;
129extern struct tag_mem_range *mem_ramdisk;
130
131extern struct tag *bootloader_tags; 127extern struct tag *bootloader_tags;
132 128
133extern void setup_bootmem(void); 129extern resource_size_t fbmem_start;
134extern void setup_processor(void); 130extern resource_size_t fbmem_size;
135extern void board_setup_fbmem(unsigned long fbmem_start,
136 unsigned long fbmem_size);
137 131
138/* Chip-specific hook to enable the use of SDRAM */ 132void setup_processor(void);
139void chip_enable_sdram(void);
140 133
141#endif /* !__ASSEMBLY__ */ 134#endif /* !__ASSEMBLY__ */
142 135
diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h
index f91975f330f6..c02bc8304b13 100644
--- a/include/asm-avr32/sysreg.h
+++ b/include/asm-avr32/sysreg.h
@@ -7,326 +7,281 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#ifndef __ASM_AVR32_SYSREG_H__ 10#ifndef __ASM_AVR32_SYSREG_H
11#define __ASM_AVR32_SYSREG_H__ 11#define __ASM_AVR32_SYSREG_H
12 12
13/* sysreg register offsets */ 13/* sysreg register offsets */
14#define SYSREG_SR 0x0000 14#define SYSREG_SR 0x0000
15#define SYSREG_EVBA 0x0004 15#define SYSREG_EVBA 0x0004
16#define SYSREG_ACBA 0x0008 16#define SYSREG_ACBA 0x0008
17#define SYSREG_CPUCR 0x000c 17#define SYSREG_CPUCR 0x000c
18#define SYSREG_ECR 0x0010 18#define SYSREG_ECR 0x0010
19#define SYSREG_RSR_SUP 0x0014 19#define SYSREG_RSR_SUP 0x0014
20#define SYSREG_RSR_INT0 0x0018 20#define SYSREG_RSR_INT0 0x0018
21#define SYSREG_RSR_INT1 0x001c 21#define SYSREG_RSR_INT1 0x001c
22#define SYSREG_RSR_INT2 0x0020 22#define SYSREG_RSR_INT2 0x0020
23#define SYSREG_RSR_INT3 0x0024 23#define SYSREG_RSR_INT3 0x0024
24#define SYSREG_RSR_EX 0x0028 24#define SYSREG_RSR_EX 0x0028
25#define SYSREG_RSR_NMI 0x002c 25#define SYSREG_RSR_NMI 0x002c
26#define SYSREG_RSR_DBG 0x0030 26#define SYSREG_RSR_DBG 0x0030
27#define SYSREG_RAR_SUP 0x0034 27#define SYSREG_RAR_SUP 0x0034
28#define SYSREG_RAR_INT0 0x0038 28#define SYSREG_RAR_INT0 0x0038
29#define SYSREG_RAR_INT1 0x003c 29#define SYSREG_RAR_INT1 0x003c
30#define SYSREG_RAR_INT2 0x0040 30#define SYSREG_RAR_INT2 0x0040
31#define SYSREG_RAR_INT3 0x0044 31#define SYSREG_RAR_INT3 0x0044
32#define SYSREG_RAR_EX 0x0048 32#define SYSREG_RAR_EX 0x0048
33#define SYSREG_RAR_NMI 0x004c 33#define SYSREG_RAR_NMI 0x004c
34#define SYSREG_RAR_DBG 0x0050 34#define SYSREG_RAR_DBG 0x0050
35#define SYSREG_JECR 0x0054 35#define SYSREG_JECR 0x0054
36#define SYSREG_JOSP 0x0058 36#define SYSREG_JOSP 0x0058
37#define SYSREG_JAVA_LV0 0x005c 37#define SYSREG_JAVA_LV0 0x005c
38#define SYSREG_JAVA_LV1 0x0060 38#define SYSREG_JAVA_LV1 0x0060
39#define SYSREG_JAVA_LV2 0x0064 39#define SYSREG_JAVA_LV2 0x0064
40#define SYSREG_JAVA_LV3 0x0068 40#define SYSREG_JAVA_LV3 0x0068
41#define SYSREG_JAVA_LV4 0x006c 41#define SYSREG_JAVA_LV4 0x006c
42#define SYSREG_JAVA_LV5 0x0070 42#define SYSREG_JAVA_LV5 0x0070
43#define SYSREG_JAVA_LV6 0x0074 43#define SYSREG_JAVA_LV6 0x0074
44#define SYSREG_JAVA_LV7 0x0078 44#define SYSREG_JAVA_LV7 0x0078
45#define SYSREG_JTBA 0x007c 45#define SYSREG_JTBA 0x007c
46#define SYSREG_JBCR 0x0080 46#define SYSREG_JBCR 0x0080
47#define SYSREG_CONFIG0 0x0100 47#define SYSREG_CONFIG0 0x0100
48#define SYSREG_CONFIG1 0x0104 48#define SYSREG_CONFIG1 0x0104
49#define SYSREG_COUNT 0x0108 49#define SYSREG_COUNT 0x0108
50#define SYSREG_COMPARE 0x010c 50#define SYSREG_COMPARE 0x010c
51#define SYSREG_TLBEHI 0x0110 51#define SYSREG_TLBEHI 0x0110
52#define SYSREG_TLBELO 0x0114 52#define SYSREG_TLBELO 0x0114
53#define SYSREG_PTBR 0x0118 53#define SYSREG_PTBR 0x0118
54#define SYSREG_TLBEAR 0x011c 54#define SYSREG_TLBEAR 0x011c
55#define SYSREG_MMUCR 0x0120 55#define SYSREG_MMUCR 0x0120
56#define SYSREG_TLBARLO 0x0124 56#define SYSREG_TLBARLO 0x0124
57#define SYSREG_TLBARHI 0x0128 57#define SYSREG_TLBARHI 0x0128
58#define SYSREG_PCCNT 0x012c 58#define SYSREG_PCCNT 0x012c
59#define SYSREG_PCNT0 0x0130 59#define SYSREG_PCNT0 0x0130
60#define SYSREG_PCNT1 0x0134 60#define SYSREG_PCNT1 0x0134
61#define SYSREG_PCCR 0x0138 61#define SYSREG_PCCR 0x0138
62#define SYSREG_BEAR 0x013c 62#define SYSREG_BEAR 0x013c
63#define SYSREG_SABAL 0x0300
64#define SYSREG_SABAH 0x0304
65#define SYSREG_SABD 0x0308
63 66
64/* Bitfields in SR */ 67/* Bitfields in SR */
65#define SYSREG_SR_C_OFFSET 0 68#define SYSREG_SR_C_OFFSET 0
66#define SYSREG_SR_C_SIZE 1 69#define SYSREG_SR_C_SIZE 1
67#define SYSREG_Z_OFFSET 1 70#define SYSREG_Z_OFFSET 1
68#define SYSREG_Z_SIZE 1 71#define SYSREG_Z_SIZE 1
69#define SYSREG_SR_N_OFFSET 2 72#define SYSREG_SR_N_OFFSET 2
70#define SYSREG_SR_N_SIZE 1 73#define SYSREG_SR_N_SIZE 1
71#define SYSREG_SR_V_OFFSET 3 74#define SYSREG_SR_V_OFFSET 3
72#define SYSREG_SR_V_SIZE 1 75#define SYSREG_SR_V_SIZE 1
73#define SYSREG_Q_OFFSET 4 76#define SYSREG_Q_OFFSET 4
74#define SYSREG_Q_SIZE 1 77#define SYSREG_Q_SIZE 1
75#define SYSREG_GM_OFFSET 16 78#define SYSREG_L_OFFSET 5
76#define SYSREG_GM_SIZE 1 79#define SYSREG_L_SIZE 1
77#define SYSREG_I0M_OFFSET 17 80#define SYSREG_T_OFFSET 14
78#define SYSREG_I0M_SIZE 1 81#define SYSREG_T_SIZE 1
79#define SYSREG_I1M_OFFSET 18 82#define SYSREG_SR_R_OFFSET 15
80#define SYSREG_I1M_SIZE 1 83#define SYSREG_SR_R_SIZE 1
81#define SYSREG_I2M_OFFSET 19 84#define SYSREG_GM_OFFSET 16
82#define SYSREG_I2M_SIZE 1 85#define SYSREG_GM_SIZE 1
83#define SYSREG_I3M_OFFSET 20 86#define SYSREG_I0M_OFFSET 17
84#define SYSREG_I3M_SIZE 1 87#define SYSREG_I0M_SIZE 1
85#define SYSREG_EM_OFFSET 21 88#define SYSREG_I1M_OFFSET 18
86#define SYSREG_EM_SIZE 1 89#define SYSREG_I1M_SIZE 1
87#define SYSREG_M0_OFFSET 22 90#define SYSREG_I2M_OFFSET 19
88#define SYSREG_M0_SIZE 1 91#define SYSREG_I2M_SIZE 1
89#define SYSREG_M1_OFFSET 23 92#define SYSREG_I3M_OFFSET 20
90#define SYSREG_M1_SIZE 1 93#define SYSREG_I3M_SIZE 1
91#define SYSREG_M2_OFFSET 24 94#define SYSREG_EM_OFFSET 21
92#define SYSREG_M2_SIZE 1 95#define SYSREG_EM_SIZE 1
93#define SYSREG_SR_D_OFFSET 26 96#define SYSREG_M0_OFFSET 22
94#define SYSREG_SR_D_SIZE 1 97#define SYSREG_M0_SIZE 1
95#define SYSREG_DM_OFFSET 27 98#define SYSREG_M1_OFFSET 23
96#define SYSREG_DM_SIZE 1 99#define SYSREG_M1_SIZE 1
97#define SYSREG_SR_J_OFFSET 28 100#define SYSREG_M2_OFFSET 24
98#define SYSREG_SR_J_SIZE 1 101#define SYSREG_M2_SIZE 1
99#define SYSREG_R_OFFSET 29 102#define SYSREG_SR_D_OFFSET 26
100#define SYSREG_R_SIZE 1 103#define SYSREG_SR_D_SIZE 1
101#define SYSREG_H_OFFSET 30 104#define SYSREG_DM_OFFSET 27
102#define SYSREG_H_SIZE 1 105#define SYSREG_DM_SIZE 1
103 106#define SYSREG_SR_J_OFFSET 28
104/* Bitfields in EVBA */ 107#define SYSREG_SR_J_SIZE 1
105 108#define SYSREG_H_OFFSET 29
106/* Bitfields in ACBA */ 109#define SYSREG_H_SIZE 1
107 110
108/* Bitfields in CPUCR */ 111/* Bitfields in CPUCR */
109#define SYSREG_BI_OFFSET 0 112#define SYSREG_BI_OFFSET 0
110#define SYSREG_BI_SIZE 1 113#define SYSREG_BI_SIZE 1
111#define SYSREG_BE_OFFSET 1 114#define SYSREG_BE_OFFSET 1
112#define SYSREG_BE_SIZE 1 115#define SYSREG_BE_SIZE 1
113#define SYSREG_FE_OFFSET 2 116#define SYSREG_FE_OFFSET 2
114#define SYSREG_FE_SIZE 1 117#define SYSREG_FE_SIZE 1
115#define SYSREG_RE_OFFSET 3 118#define SYSREG_RE_OFFSET 3
116#define SYSREG_RE_SIZE 1 119#define SYSREG_RE_SIZE 1
117#define SYSREG_IBE_OFFSET 4 120#define SYSREG_IBE_OFFSET 4
118#define SYSREG_IBE_SIZE 1 121#define SYSREG_IBE_SIZE 1
119#define SYSREG_IEE_OFFSET 5 122#define SYSREG_IEE_OFFSET 5
120#define SYSREG_IEE_SIZE 1 123#define SYSREG_IEE_SIZE 1
121
122/* Bitfields in ECR */
123#define SYSREG_ECR_OFFSET 0
124#define SYSREG_ECR_SIZE 32
125
126/* Bitfields in RSR_SUP */
127
128/* Bitfields in RSR_INT0 */
129
130/* Bitfields in RSR_INT1 */
131
132/* Bitfields in RSR_INT2 */
133
134/* Bitfields in RSR_INT3 */
135
136/* Bitfields in RSR_EX */
137
138/* Bitfields in RSR_NMI */
139
140/* Bitfields in RSR_DBG */
141
142/* Bitfields in RAR_SUP */
143
144/* Bitfields in RAR_INT0 */
145
146/* Bitfields in RAR_INT1 */
147
148/* Bitfields in RAR_INT2 */
149
150/* Bitfields in RAR_INT3 */
151
152/* Bitfields in RAR_EX */
153
154/* Bitfields in RAR_NMI */
155
156/* Bitfields in RAR_DBG */
157
158/* Bitfields in JECR */
159
160/* Bitfields in JOSP */
161
162/* Bitfields in JAVA_LV0 */
163
164/* Bitfields in JAVA_LV1 */
165
166/* Bitfields in JAVA_LV2 */
167
168/* Bitfields in JAVA_LV3 */
169
170/* Bitfields in JAVA_LV4 */
171
172/* Bitfields in JAVA_LV5 */
173
174/* Bitfields in JAVA_LV6 */
175
176/* Bitfields in JAVA_LV7 */
177
178/* Bitfields in JTBA */
179
180/* Bitfields in JBCR */
181 124
182/* Bitfields in CONFIG0 */ 125/* Bitfields in CONFIG0 */
183#define SYSREG_CONFIG0_D_OFFSET 1 126#define SYSREG_CONFIG0_R_OFFSET 0
184#define SYSREG_CONFIG0_D_SIZE 1 127#define SYSREG_CONFIG0_R_SIZE 1
185#define SYSREG_CONFIG0_S_OFFSET 2 128#define SYSREG_CONFIG0_D_OFFSET 1
186#define SYSREG_CONFIG0_S_SIZE 1 129#define SYSREG_CONFIG0_D_SIZE 1
187#define SYSREG_O_OFFSET 3 130#define SYSREG_CONFIG0_S_OFFSET 2
188#define SYSREG_O_SIZE 1 131#define SYSREG_CONFIG0_S_SIZE 1
189#define SYSREG_P_OFFSET 4 132#define SYSREG_CONFIG0_O_OFFSET 3
190#define SYSREG_P_SIZE 1 133#define SYSREG_CONFIG0_O_SIZE 1
191#define SYSREG_CONFIG0_J_OFFSET 5 134#define SYSREG_CONFIG0_P_OFFSET 4
192#define SYSREG_CONFIG0_J_SIZE 1 135#define SYSREG_CONFIG0_P_SIZE 1
193#define SYSREG_F_OFFSET 6 136#define SYSREG_CONFIG0_J_OFFSET 5
194#define SYSREG_F_SIZE 1 137#define SYSREG_CONFIG0_J_SIZE 1
195#define SYSREG_MMUT_OFFSET 7 138#define SYSREG_CONFIG0_F_OFFSET 6
196#define SYSREG_MMUT_SIZE 3 139#define SYSREG_CONFIG0_F_SIZE 1
197#define SYSREG_AR_OFFSET 10 140#define SYSREG_MMUT_OFFSET 7
198#define SYSREG_AR_SIZE 3 141#define SYSREG_MMUT_SIZE 3
199#define SYSREG_AT_OFFSET 13 142#define SYSREG_AR_OFFSET 10
200#define SYSREG_AT_SIZE 3 143#define SYSREG_AR_SIZE 3
201#define SYSREG_PROCESSORREVISION_OFFSET 16 144#define SYSREG_AT_OFFSET 13
202#define SYSREG_PROCESSORREVISION_SIZE 8 145#define SYSREG_AT_SIZE 3
203#define SYSREG_PROCESSORID_OFFSET 24 146#define SYSREG_PROCESSORREVISION_OFFSET 16
204#define SYSREG_PROCESSORID_SIZE 8 147#define SYSREG_PROCESSORREVISION_SIZE 8
148#define SYSREG_PROCESSORID_OFFSET 24
149#define SYSREG_PROCESSORID_SIZE 8
205 150
206/* Bitfields in CONFIG1 */ 151/* Bitfields in CONFIG1 */
207#define SYSREG_DASS_OFFSET 0 152#define SYSREG_DASS_OFFSET 0
208#define SYSREG_DASS_SIZE 3 153#define SYSREG_DASS_SIZE 3
209#define SYSREG_DLSZ_OFFSET 3 154#define SYSREG_DLSZ_OFFSET 3
210#define SYSREG_DLSZ_SIZE 3 155#define SYSREG_DLSZ_SIZE 3
211#define SYSREG_DSET_OFFSET 6 156#define SYSREG_DSET_OFFSET 6
212#define SYSREG_DSET_SIZE 4 157#define SYSREG_DSET_SIZE 4
213#define SYSREG_IASS_OFFSET 10 158#define SYSREG_IASS_OFFSET 10
214#define SYSREG_IASS_SIZE 2 159#define SYSREG_IASS_SIZE 3
215#define SYSREG_ILSZ_OFFSET 13 160#define SYSREG_ILSZ_OFFSET 13
216#define SYSREG_ILSZ_SIZE 3 161#define SYSREG_ILSZ_SIZE 3
217#define SYSREG_ISET_OFFSET 16 162#define SYSREG_ISET_OFFSET 16
218#define SYSREG_ISET_SIZE 4 163#define SYSREG_ISET_SIZE 4
219#define SYSREG_DMMUSZ_OFFSET 20 164#define SYSREG_DMMUSZ_OFFSET 20
220#define SYSREG_DMMUSZ_SIZE 6 165#define SYSREG_DMMUSZ_SIZE 6
221#define SYSREG_IMMUSZ_OFFSET 26 166#define SYSREG_IMMUSZ_OFFSET 26
222#define SYSREG_IMMUSZ_SIZE 6 167#define SYSREG_IMMUSZ_SIZE 6
223
224/* Bitfields in COUNT */
225
226/* Bitfields in COMPARE */
227 168
228/* Bitfields in TLBEHI */ 169/* Bitfields in TLBEHI */
229#define SYSREG_ASID_OFFSET 0 170#define SYSREG_ASID_OFFSET 0
230#define SYSREG_ASID_SIZE 8 171#define SYSREG_ASID_SIZE 8
231#define SYSREG_TLBEHI_I_OFFSET 8 172#define SYSREG_TLBEHI_I_OFFSET 8
232#define SYSREG_TLBEHI_I_SIZE 1 173#define SYSREG_TLBEHI_I_SIZE 1
233#define SYSREG_TLBEHI_V_OFFSET 9 174#define SYSREG_TLBEHI_V_OFFSET 9
234#define SYSREG_TLBEHI_V_SIZE 1 175#define SYSREG_TLBEHI_V_SIZE 1
235#define SYSREG_VPN_OFFSET 10 176#define SYSREG_VPN_OFFSET 10
236#define SYSREG_VPN_SIZE 22 177#define SYSREG_VPN_SIZE 22
237 178
238/* Bitfields in TLBELO */ 179/* Bitfields in TLBELO */
239#define SYSREG_W_OFFSET 0 180#define SYSREG_W_OFFSET 0
240#define SYSREG_W_SIZE 1 181#define SYSREG_W_SIZE 1
241#define SYSREG_TLBELO_D_OFFSET 1 182#define SYSREG_TLBELO_D_OFFSET 1
242#define SYSREG_TLBELO_D_SIZE 1 183#define SYSREG_TLBELO_D_SIZE 1
243#define SYSREG_SZ_OFFSET 2 184#define SYSREG_SZ_OFFSET 2
244#define SYSREG_SZ_SIZE 2 185#define SYSREG_SZ_SIZE 2
245#define SYSREG_AP_OFFSET 4 186#define SYSREG_AP_OFFSET 4
246#define SYSREG_AP_SIZE 3 187#define SYSREG_AP_SIZE 3
247#define SYSREG_B_OFFSET 7 188#define SYSREG_B_OFFSET 7
248#define SYSREG_B_SIZE 1 189#define SYSREG_B_SIZE 1
249#define SYSREG_G_OFFSET 8 190#define SYSREG_G_OFFSET 8
250#define SYSREG_G_SIZE 1 191#define SYSREG_G_SIZE 1
251#define SYSREG_TLBELO_C_OFFSET 9 192#define SYSREG_TLBELO_C_OFFSET 9
252#define SYSREG_TLBELO_C_SIZE 1 193#define SYSREG_TLBELO_C_SIZE 1
253#define SYSREG_PFN_OFFSET 10 194#define SYSREG_PFN_OFFSET 10
254#define SYSREG_PFN_SIZE 22 195#define SYSREG_PFN_SIZE 22
255
256/* Bitfields in PTBR */
257
258/* Bitfields in TLBEAR */
259 196
260/* Bitfields in MMUCR */ 197/* Bitfields in MMUCR */
261#define SYSREG_E_OFFSET 0 198#define SYSREG_E_OFFSET 0
262#define SYSREG_E_SIZE 1 199#define SYSREG_E_SIZE 1
263#define SYSREG_M_OFFSET 1 200#define SYSREG_M_OFFSET 1
264#define SYSREG_M_SIZE 1 201#define SYSREG_M_SIZE 1
265#define SYSREG_MMUCR_I_OFFSET 2 202#define SYSREG_MMUCR_I_OFFSET 2
266#define SYSREG_MMUCR_I_SIZE 1 203#define SYSREG_MMUCR_I_SIZE 1
267#define SYSREG_MMUCR_N_OFFSET 3 204#define SYSREG_MMUCR_N_OFFSET 3
268#define SYSREG_MMUCR_N_SIZE 1 205#define SYSREG_MMUCR_N_SIZE 1
269#define SYSREG_MMUCR_S_OFFSET 4 206#define SYSREG_MMUCR_S_OFFSET 4
270#define SYSREG_MMUCR_S_SIZE 1 207#define SYSREG_MMUCR_S_SIZE 1
271#define SYSREG_DLA_OFFSET 8 208#define SYSREG_DLA_OFFSET 8
272#define SYSREG_DLA_SIZE 6 209#define SYSREG_DLA_SIZE 6
273#define SYSREG_DRP_OFFSET 14 210#define SYSREG_DRP_OFFSET 14
274#define SYSREG_DRP_SIZE 6 211#define SYSREG_DRP_SIZE 6
275#define SYSREG_ILA_OFFSET 20 212#define SYSREG_ILA_OFFSET 20
276#define SYSREG_ILA_SIZE 6 213#define SYSREG_ILA_SIZE 6
277#define SYSREG_IRP_OFFSET 26 214#define SYSREG_IRP_OFFSET 26
278#define SYSREG_IRP_SIZE 6 215#define SYSREG_IRP_SIZE 6
279
280/* Bitfields in TLBARLO */
281
282/* Bitfields in TLBARHI */
283
284/* Bitfields in PCCNT */
285
286/* Bitfields in PCNT0 */
287
288/* Bitfields in PCNT1 */
289 216
290/* Bitfields in PCCR */ 217/* Bitfields in PCCR */
291 218#define SYSREG_PCCR_R_OFFSET 1
292/* Bitfields in BEAR */ 219#define SYSREG_PCCR_R_SIZE 1
220#define SYSREG_PCCR_C_OFFSET 2
221#define SYSREG_PCCR_C_SIZE 1
222#define SYSREG_PCCR_S_OFFSET 3
223#define SYSREG_PCCR_S_SIZE 1
224#define SYSREG_IEC_OFFSET 4
225#define SYSREG_IEC_SIZE 1
226#define SYSREG_IE0_OFFSET 5
227#define SYSREG_IE0_SIZE 1
228#define SYSREG_IE1_OFFSET 6
229#define SYSREG_IE1_SIZE 1
230#define SYSREG_FC_OFFSET 8
231#define SYSREG_FC_SIZE 1
232#define SYSREG_F0_OFFSET 9
233#define SYSREG_F0_SIZE 1
234#define SYSREG_F1_OFFSET 10
235#define SYSREG_F1_SIZE 1
236#define SYSREG_CONF0_OFFSET 12
237#define SYSREG_CONF0_SIZE 6
238#define SYSREG_CONF1_OFFSET 18
239#define SYSREG_CONF1_SIZE 6
293 240
294/* Constants for ECR */ 241/* Constants for ECR */
295#define ECR_UNRECOVERABLE 0 242#define ECR_UNRECOVERABLE 0
296#define ECR_TLB_MULTIPLE 1 243#define ECR_TLB_MULTIPLE 1
297#define ECR_BUS_ERROR_WRITE 2 244#define ECR_BUS_ERROR_WRITE 2
298#define ECR_BUS_ERROR_READ 3 245#define ECR_BUS_ERROR_READ 3
299#define ECR_NMI 4 246#define ECR_NMI 4
300#define ECR_ADDR_ALIGN_X 5 247#define ECR_ADDR_ALIGN_X 5
301#define ECR_PROTECTION_X 6 248#define ECR_PROTECTION_X 6
302#define ECR_DEBUG 7 249#define ECR_DEBUG 7
303#define ECR_ILLEGAL_OPCODE 8 250#define ECR_ILLEGAL_OPCODE 8
304#define ECR_UNIMPL_INSTRUCTION 9 251#define ECR_UNIMPL_INSTRUCTION 9
305#define ECR_PRIVILEGE_VIOLATION 10 252#define ECR_PRIVILEGE_VIOLATION 10
306#define ECR_FPE 11 253#define ECR_FPE 11
307#define ECR_COPROC_ABSENT 12 254#define ECR_COPROC_ABSENT 12
308#define ECR_ADDR_ALIGN_R 13 255#define ECR_ADDR_ALIGN_R 13
309#define ECR_ADDR_ALIGN_W 14 256#define ECR_ADDR_ALIGN_W 14
310#define ECR_PROTECTION_R 15 257#define ECR_PROTECTION_R 15
311#define ECR_PROTECTION_W 16 258#define ECR_PROTECTION_W 16
312#define ECR_DTLB_MODIFIED 17 259#define ECR_DTLB_MODIFIED 17
313#define ECR_TLB_MISS_X 20 260#define ECR_TLB_MISS_X 20
314#define ECR_TLB_MISS_R 24 261#define ECR_TLB_MISS_R 24
315#define ECR_TLB_MISS_W 28 262#define ECR_TLB_MISS_W 28
316 263
317/* Bit manipulation macros */ 264/* Bit manipulation macros */
318#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) 265#define SYSREG_BIT(name) \
319#define SYSREG_BF(name,value) (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) << SYSREG_##name##_OFFSET) 266 (1 << SYSREG_##name##_OFFSET)
320#define SYSREG_BFEXT(name,value) (((value) >> SYSREG_##name##_OFFSET) & ((1 << SYSREG_##name##_SIZE) - 1)) 267#define SYSREG_BF(name,value) \
321#define SYSREG_BFINS(name,value,old) (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) << SYSREG_##name##_OFFSET)) | SYSREG_BF(name,value)) 268 (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \
269 << SYSREG_##name##_OFFSET)
270#define SYSREG_BFEXT(name,value)\
271 (((value) >> SYSREG_##name##_OFFSET) \
272 & ((1 << SYSREG_##name##_SIZE) - 1))
273#define SYSREG_BFINS(name,value,old) \
274 (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \
275 << SYSREG_##name##_OFFSET)) \
276 | SYSREG_BF(name,value))
322 277
278/* Register access macros */
323#ifdef __CHECKER__ 279#ifdef __CHECKER__
324extern unsigned long __builtin_mfsr(unsigned long reg); 280extern unsigned long __builtin_mfsr(unsigned long reg);
325extern void __builtin_mtsr(unsigned long reg, unsigned long value); 281extern void __builtin_mtsr(unsigned long reg, unsigned long value);
326#endif 282#endif
327 283
328/* Register access macros */ 284#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg)
329#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg) 285#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value)
330#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value)
331 286
332#endif /* __ASM_AVR32_SYSREG_H__ */ 287#endif /* __ASM_AVR32_SYSREG_H */
diff --git a/include/asm-avr32/system.h b/include/asm-avr32/system.h
index ac596058697d..a8236bacc878 100644
--- a/include/asm-avr32/system.h
+++ b/include/asm-avr32/system.h
@@ -9,6 +9,7 @@
9#define __ASM_AVR32_SYSTEM_H 9#define __ASM_AVR32_SYSTEM_H
10 10
11#include <linux/compiler.h> 11#include <linux/compiler.h>
12#include <linux/linkage.h>
12#include <linux/types.h> 13#include <linux/types.h>
13 14
14#include <asm/ptrace.h> 15#include <asm/ptrace.h>
@@ -140,15 +141,9 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
140 sizeof(*(ptr)))) 141 sizeof(*(ptr))))
141 142
142struct pt_regs; 143struct pt_regs;
143extern void __die(const char *, struct pt_regs *, unsigned long, 144void NORET_TYPE die(const char *str, struct pt_regs *regs, long err);
144 const char *, const char *, unsigned long); 145void _exception(long signr, struct pt_regs *regs, int code,
145extern void __die_if_kernel(const char *, struct pt_regs *, unsigned long, 146 unsigned long addr);
146 const char *, const char *, unsigned long);
147
148#define die(msg, regs, err) \
149 __die(msg, regs, err, __FILE__ ":", __FUNCTION__, __LINE__)
150#define die_if_kernel(msg, regs, err) \
151 __die_if_kernel(msg, regs, err, __FILE__ ":", __FUNCTION__, __LINE__)
152 147
153#define arch_align_stack(x) (x) 148#define arch_align_stack(x) (x)
154 149
diff --git a/include/asm-avr32/thread_info.h b/include/asm-avr32/thread_info.h
index d1f5b35ebd54..a2e606dd4f4a 100644
--- a/include/asm-avr32/thread_info.h
+++ b/include/asm-avr32/thread_info.h
@@ -83,6 +83,7 @@ static inline struct thread_info *current_thread_info(void)
83#define TIF_SINGLE_STEP 6 /* single step after next break */ 83#define TIF_SINGLE_STEP 6 /* single step after next break */
84#define TIF_MEMDIE 7 84#define TIF_MEMDIE 7
85#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal */ 85#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal */
86#define TIF_CPU_GOING_TO_SLEEP 9 /* CPU is entering sleep 0 mode */
86#define TIF_USERSPACE 31 /* true if FS sets userspace */ 87#define TIF_USERSPACE 31 /* true if FS sets userspace */
87 88
88#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) 89#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
@@ -94,6 +95,7 @@ static inline struct thread_info *current_thread_info(void)
94#define _TIF_SINGLE_STEP (1 << TIF_SINGLE_STEP) 95#define _TIF_SINGLE_STEP (1 << TIF_SINGLE_STEP)
95#define _TIF_MEMDIE (1 << TIF_MEMDIE) 96#define _TIF_MEMDIE (1 << TIF_MEMDIE)
96#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) 97#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
98#define _TIF_CPU_GOING_TO_SLEEP (1 << TIF_CPU_GOING_TO_SLEEP)
97 99
98/* XXX: These two masks must never span more than 16 bits! */ 100/* XXX: These two masks must never span more than 16 bits! */
99/* work to do on interrupt/exception return */ 101/* work to do on interrupt/exception return */
diff --git a/include/asm-avr32/uaccess.h b/include/asm-avr32/uaccess.h
index 74a679e9098c..ed092395215e 100644
--- a/include/asm-avr32/uaccess.h
+++ b/include/asm-avr32/uaccess.h
@@ -181,24 +181,23 @@ extern int __put_user_bad(void);
181 181
182#define __get_user_nocheck(x, ptr, size) \ 182#define __get_user_nocheck(x, ptr, size) \
183({ \ 183({ \
184 typeof(*(ptr)) __gu_val = (typeof(*(ptr)) __force)0; \ 184 unsigned long __gu_val = 0; \
185 int __gu_err = 0; \ 185 int __gu_err = 0; \
186 \ 186 \
187 switch (size) { \ 187 switch (size) { \
188 case 1: __get_user_asm("ub", __gu_val, ptr, __gu_err); break; \ 188 case 1: __get_user_asm("ub", __gu_val, ptr, __gu_err); break; \
189 case 2: __get_user_asm("uh", __gu_val, ptr, __gu_err); break; \ 189 case 2: __get_user_asm("uh", __gu_val, ptr, __gu_err); break; \
190 case 4: __get_user_asm("w", __gu_val, ptr, __gu_err); break; \ 190 case 4: __get_user_asm("w", __gu_val, ptr, __gu_err); break; \
191 case 8: __get_user_asm("d", __gu_val, ptr, __gu_err); break; \
192 default: __gu_err = __get_user_bad(); break; \ 191 default: __gu_err = __get_user_bad(); break; \
193 } \ 192 } \
194 \ 193 \
195 x = __gu_val; \ 194 x = (typeof(*(ptr)))__gu_val; \
196 __gu_err; \ 195 __gu_err; \
197}) 196})
198 197
199#define __get_user_check(x, ptr, size) \ 198#define __get_user_check(x, ptr, size) \
200({ \ 199({ \
201 typeof(*(ptr)) __gu_val = (typeof(*(ptr)) __force)0; \ 200 unsigned long __gu_val = 0; \
202 const typeof(*(ptr)) __user * __gu_addr = (ptr); \ 201 const typeof(*(ptr)) __user * __gu_addr = (ptr); \
203 int __gu_err = 0; \ 202 int __gu_err = 0; \
204 \ 203 \
@@ -216,10 +215,6 @@ extern int __put_user_bad(void);
216 __get_user_asm("w", __gu_val, __gu_addr, \ 215 __get_user_asm("w", __gu_val, __gu_addr, \
217 __gu_err); \ 216 __gu_err); \
218 break; \ 217 break; \
219 case 8: \
220 __get_user_asm("d", __gu_val, __gu_addr, \
221 __gu_err); \
222 break; \
223 default: \ 218 default: \
224 __gu_err = __get_user_bad(); \ 219 __gu_err = __get_user_bad(); \
225 break; \ 220 break; \
@@ -227,7 +222,7 @@ extern int __put_user_bad(void);
227 } else { \ 222 } else { \
228 __gu_err = -EFAULT; \ 223 __gu_err = -EFAULT; \
229 } \ 224 } \
230 x = __gu_val; \ 225 x = (typeof(*(ptr)))__gu_val; \
231 __gu_err; \ 226 __gu_err; \
232}) 227})
233 228
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index 6d7e279b1490..dc8f99ee305f 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -139,8 +139,15 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres
139#define pte_same(A,B) (pte_val(A) == pte_val(B)) 139#define pte_same(A,B) (pte_val(A) == pte_val(B))
140#endif 140#endif
141 141
142#ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY 142#ifndef __HAVE_ARCH_PAGE_TEST_DIRTY
143#define page_test_and_clear_dirty(page) (0) 143#define page_test_dirty(page) (0)
144#endif
145
146#ifndef __HAVE_ARCH_PAGE_CLEAR_DIRTY
147#define page_clear_dirty(page) do { } while (0)
148#endif
149
150#ifndef __HAVE_ARCH_PAGE_TEST_DIRTY
144#define pte_maybe_dirty(pte) pte_dirty(pte) 151#define pte_maybe_dirty(pte) pte_dirty(pte)
145#else 152#else
146#define pte_maybe_dirty(pte) (1) 153#define pte_maybe_dirty(pte) (1)
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 28d907d4347a..4933b4947ed0 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -96,6 +96,6 @@ extern void (*flush_data_cache_page)(unsigned long addr);
96unsigned long __init run_uncached(void *func); 96unsigned long __init run_uncached(void *func);
97 97
98extern void *kmap_coherent(struct page *page, unsigned long addr); 98extern void *kmap_coherent(struct page *page, unsigned long addr);
99extern void kunmap_coherent(struct page *page); 99extern void kunmap_coherent(void);
100 100
101#endif /* _ASM_CACHEFLUSH_H */ 101#endif /* _ASM_CACHEFLUSH_H */
diff --git a/include/asm-mips/jmr3927/irq.h b/include/asm-mips/jmr3927/irq.h
deleted file mode 100644
index e3e7ed38da6c..000000000000
--- a/include/asm-mips/jmr3927/irq.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * linux/include/asm-mips/tx3927/irq.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 Toshiba Corporation
9 */
10#ifndef __ASM_TX3927_IRQ_H
11#define __ASM_TX3927_IRQ_H
12
13#ifndef __ASSEMBLY__
14
15#include <asm/irq.h>
16
17struct tb_irq_space {
18 struct tb_irq_space* next;
19 int start_irqno;
20 int nr_irqs;
21 void (*mask_func)(int irq_nr, int space_id);
22 void (*unmask_func)(int irq_no, int space_id);
23 const char *name;
24 int space_id;
25 int can_share;
26};
27extern struct tb_irq_space* tb_irq_spaces;
28
29static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
30{
31 sp->next = tb_irq_spaces;
32 tb_irq_spaces = sp;
33}
34
35
36struct pt_regs;
37extern void
38toshibaboards_spurious(struct pt_regs *regs, int irq);
39extern void
40toshibaboards_irqdispatch(struct pt_regs *regs, int irq);
41
42extern struct irqaction *
43toshibaboards_get_irq_action(int irq);
44extern int
45toshibaboards_setup_irq(int irq, struct irqaction * new);
46
47
48extern int (*toshibaboards_gen_iack)(void);
49
50#endif /* !__ASSEMBLY__ */
51
52#define NR_ISA_IRQS 16
53#define TB_IRQ_IS_ISA(irq) \
54 (0 <= (irq) && (irq) < NR_ISA_IRQS)
55#define TB_IRQ_TO_ISA_IRQ(irq) (irq)
56
57#endif /* __ASM_TX3927_IRQ_H */
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index c50e68ffa3af..958e29706e2d 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF. 2 * Defines for the TJSYS JMR-TX3927
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General Public 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
@@ -12,10 +12,7 @@
12 12
13#include <asm/jmr3927/tx3927.h> 13#include <asm/jmr3927/tx3927.h>
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/jmr3927/irq.h>
16#ifndef __ASSEMBLY__
17#include <asm/system.h> 15#include <asm/system.h>
18#endif
19 16
20/* CS */ 17/* CS */
21#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ 18#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
@@ -35,28 +32,10 @@
35#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ 32#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
36#define JMR3927_PORT_BASE KSEG1 33#define JMR3927_PORT_BASE KSEG1
37 34
38/* select indirect initiator access per errata */
39#define JMR3927_INIT_INDIRECT_PCI
40#define PCI_ISTAT_IDICC 0x1000
41#define PCI_IPCIBE_IBE_LONG 0
42#define PCI_IPCIBE_ICMD_IOREAD 2
43#define PCI_IPCIBE_ICMD_IOWRITE 3
44#define PCI_IPCIBE_ICMD_MEMREAD 6
45#define PCI_IPCIBE_ICMD_MEMWRITE 7
46#define PCI_IPCIBE_ICMD_SHIFT 4
47
48/* Address map (virtual address) */ 35/* Address map (virtual address) */
49#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) 36#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
50#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) 37#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
51#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) 38#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
52#define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3)
53#define JMR3927_ISAMEM_BASE (JMR3927_IOB_BASE)
54#define JMR3927_ISAIO_BASE (JMR3927_IOB_BASE + 0x01000000)
55#define JMR3927_ISAC_BASE (JMR3927_IOB_BASE + 0x02000000)
56#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000)
57#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000)
58#define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5)
59#define JMR3927_PREMIER3_BASE (JMR3927_JMY1394_BASE + 0x00100000)
60#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) 39#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
61#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) 40#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
62 41
@@ -72,25 +51,14 @@
72#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) 51#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
73#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) 52#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
74 53
75#define JMR3927_ISAC_REV_ADDR (JMR3927_ISAC_BASE + 0x00000000)
76#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000)
77#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000)
78#define JMR3927_ISAC_NMI_ADDR (JMR3927_ISAC_BASE + 0x00400000)
79#define JMR3927_ISAC_LED_ADDR (JMR3927_ISAC_BASE + 0x00500000)
80#define JMR3927_ISAC_INTP_ADDR (JMR3927_ISAC_BASE + 0x00800000)
81#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000)
82#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000)
83#define JMR3927_ISAC_INTM_ADDR (JMR3927_ISAC_BASE + 0x00b00000)
84
85/* Flash ROM */ 54/* Flash ROM */
86#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) 55#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
87#define JMR3927_FLASH_SIZE 0x00400000 56#define JMR3927_FLASH_SIZE 0x00400000
88 57
89/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */ 58/* bits for IOC_REV/IOC_BREV (high byte) */
90#define JMR3927_IDT_MASK 0xfc 59#define JMR3927_IDT_MASK 0xfc
91#define JMR3927_REV_MASK 0x03 60#define JMR3927_REV_MASK 0x03
92#define JMR3927_IOC_IDT 0xe0 61#define JMR3927_IOC_IDT 0xe0
93#define JMR3927_ISAC_IDT 0x20
94 62
95/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ 63/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
96#define JMR3927_IOC_INTB_PCIA 0 64#define JMR3927_IOC_INTB_PCIA 0
@@ -114,40 +82,6 @@
114#define JMR3927_IOC_RESET_CPU 1 82#define JMR3927_IOC_RESET_CPU 1
115#define JMR3927_IOC_RESET_PCI 2 83#define JMR3927_IOC_RESET_PCI 2
116 84
117/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
118#define JMR3927_ISAC_EINTB_IOCHK 2
119#define JMR3927_ISAC_EINTB_BWTH 4
120#define JMR3927_ISAC_EINTF_IOCHK (1 << JMR3927_ISAC_EINTB_IOCHK)
121#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH)
122
123/* bits for ISAC_LED (high byte) */
124#define JMR3927_ISAC_LED_ISALED 0x01
125#define JMR3927_ISAC_LED_USRLED 0x02
126
127/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
128#define JMR3927_ISAC_INTB_IRQ5 0
129#define JMR3927_ISAC_INTB_IRQKB 1
130#define JMR3927_ISAC_INTB_IRQMOUSE 2
131#define JMR3927_ISAC_INTB_IRQ4 3
132#define JMR3927_ISAC_INTB_IRQ12 4
133#define JMR3927_ISAC_INTB_IRQ3 5
134#define JMR3927_ISAC_INTB_IRQ10 6
135#define JMR3927_ISAC_INTB_ISAER 7
136#define JMR3927_ISAC_INTF_IRQ5 (1 << JMR3927_ISAC_INTB_IRQ5)
137#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB)
138#define JMR3927_ISAC_INTF_IRQMOUSE (1 << JMR3927_ISAC_INTB_IRQMOUSE)
139#define JMR3927_ISAC_INTF_IRQ4 (1 << JMR3927_ISAC_INTB_IRQ4)
140#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12)
141#define JMR3927_ISAC_INTF_IRQ3 (1 << JMR3927_ISAC_INTB_IRQ3)
142#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10)
143#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER)
144
145#ifndef __ASSEMBLY__
146
147#if 0
148#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned short *)(a)) = (d) << 8)
149#define jmr3927_ioc_reg_in(a) (((*(volatile unsigned short *)(a)) >> 8) & 0xff)
150#else
151#if defined(__BIG_ENDIAN) 85#if defined(__BIG_ENDIAN)
152#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) 86#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
153#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) 87#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
@@ -157,31 +91,9 @@
157#else 91#else
158#error "No Endian" 92#error "No Endian"
159#endif 93#endif
160#endif
161#define jmr3927_isac_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
162#define jmr3927_isac_reg_in(a) (*(volatile unsigned char *)(a))
163
164static inline int jmr3927_have_isac(void)
165{
166 unsigned char idt;
167 unsigned long flags;
168 unsigned long romcr3;
169
170 local_irq_save(flags);
171 romcr3 = tx3927_romcptr->cr[3];
172 tx3927_romcptr->cr[3] &= 0xffffefff; /* do not wait infinitely */
173 idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
174 tx3927_romcptr->cr[3] = romcr3;
175 local_irq_restore(flags);
176
177 return idt == JMR3927_ISAC_IDT;
178}
179#define jmr3927_have_nvram() \
180 ((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)
181 94
182/* LED macro */ 95/* LED macro */
183#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) 96#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
184#define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
185 97
186#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) 98#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
187 99
@@ -190,10 +102,6 @@ static inline int jmr3927_have_isac(void)
190#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0) 102#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0)
191#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) 103#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
192#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) 104#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
193#define jmr3927_io_dipsw() (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)
194
195
196#endif /* !__ASSEMBLY__ */
197 105
198/* 106/*
199 * IRQ mappings 107 * IRQ mappings
@@ -206,16 +114,10 @@ static inline int jmr3927_have_isac(void)
206 */ 114 */
207#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ 115#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
208#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ 116#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
209#define JMR3927_NR_IRQ_ISAC 8 /* ISA */
210 117
211 118#define JMR3927_IRQ_IRC 16
212#define JMR3927_IRQ_IRC NR_ISA_IRQS
213#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) 119#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
214#define JMR3927_IRQ_ISAC (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) 120#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
215#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
216#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
217#define JMR3927_IRQ_IS_IOC(irq) (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
218#define JMR3927_IRQ_IS_ISAC(irq) (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)
219 121
220#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) 122#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
221#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) 123#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
@@ -240,37 +142,13 @@ static inline int jmr3927_have_isac(void)
240#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) 142#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
241#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) 143#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
242#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) 144#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
243#define JMR3927_IRQ_ISAC_IRQ5 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
244#define JMR3927_IRQ_ISAC_IRQKB (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
245#define JMR3927_IRQ_ISAC_IRQMOUSE (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
246#define JMR3927_IRQ_ISAC_IRQ4 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
247#define JMR3927_IRQ_ISAC_IRQ12 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
248#define JMR3927_IRQ_ISAC_IRQ3 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
249#define JMR3927_IRQ_ISAC_IRQ10 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
250#define JMR3927_IRQ_ISAC_ISAER (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)
251 145
252#if 0 /* auto detect */
253/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
254#define JMR3927_IRQ_ETHER1 JMR3927_IRQ_IRC_INT0
255#endif
256/* IOC (PCI, MODEM) */ 146/* IOC (PCI, MODEM) */
257#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 147#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
258/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
259#define JMR3927_IRQ_ISACINT JMR3927_IRQ_IRC_INT2
260/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ 148/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
261#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 149#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
262/* Clock Tick (10ms) */ 150/* Clock Tick (10ms) */
263#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0 151#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
264#define JMR3927_IRQ_IDE JMR3927_IRQ_ISAC_IRQ12
265
266/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
267#define JMR3927_IRQ_PREMIER3 JMR3927_IRQ_IRC_INT0
268
269/* I/O Ports */
270/* RTL8019AS 10M Ether */
271#define JMR3927_ETHER1_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
272#define JMR3927_KBD_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
273#define JMR3927_IDE_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)
274 152
275/* Clocks */ 153/* Clocks */
276#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 154#define JMR3927_CORECLK 132710400 /* 132.7MHz */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index b3d67c75d9ac..0b9073bfb759 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -22,8 +22,6 @@
22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) 22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
23#define TX3927_PIO_REG 0xfffef500 23#define TX3927_PIO_REG 0xfffef500
24 24
25#ifndef __ASSEMBLY__
26
27struct tx3927_sdramc_reg { 25struct tx3927_sdramc_reg {
28 volatile unsigned long cr[8]; 26 volatile unsigned long cr[8];
29 volatile unsigned long tr[3]; 27 volatile unsigned long tr[3];
@@ -164,8 +162,6 @@ struct tx3927_ccfg_reg {
164 volatile unsigned long pdcr; 162 volatile unsigned long pdcr;
165}; 163};
166 164
167#endif /* !__ASSEMBLY__ */
168
169/* 165/*
170 * SDRAMC 166 * SDRAMC
171 */ 167 */
@@ -348,8 +344,6 @@ struct tx3927_ccfg_reg {
348#define TX3927_PCFG_SELDMA_ALL 0x0000000f 344#define TX3927_PCFG_SELDMA_ALL 0x0000000f
349#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) 345#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
350 346
351#ifndef __ASSEMBLY__
352
353#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) 347#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
354#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) 348#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
355#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 349#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
@@ -360,6 +354,4 @@ struct tx3927_ccfg_reg {
360#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 354#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
361#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG) 355#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG)
362 356
363#endif /* !__ASSEMBLY__ */
364
365#endif /* __ASM_TX3927_H */ 357#endif /* __ASM_TX3927_H */
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
index 9d5792eab452..58a8ff6be815 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/jmr3927/txx927.h
@@ -10,8 +10,6 @@
10#ifndef __ASM_TXX927_H 10#ifndef __ASM_TXX927_H
11#define __ASM_TXX927_H 11#define __ASM_TXX927_H
12 12
13#ifndef __ASSEMBLY__
14
15struct txx927_tmr_reg { 13struct txx927_tmr_reg {
16 volatile unsigned long tcr; 14 volatile unsigned long tcr;
17 volatile unsigned long tisr; 15 volatile unsigned long tisr;
@@ -52,9 +50,6 @@ struct txx927_pio_reg {
52 volatile unsigned long maskext; 50 volatile unsigned long maskext;
53}; 51};
54 52
55#endif /* !__ASSEMBLY__ */
56
57
58/* 53/*
59 * TMR 54 * TMR
60 */ 55 */
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
index 147844ef103b..8c08fa904b2c 100644
--- a/include/asm-mips/paccess.h
+++ b/include/asm-mips/paccess.h
@@ -34,7 +34,7 @@ struct __large_pstruct { unsigned long buf[100]; };
34#define __get_dbe(x,ptr,size) \ 34#define __get_dbe(x,ptr,size) \
35({ \ 35({ \
36 long __gu_err; \ 36 long __gu_err; \
37 __typeof(*(ptr)) __gu_val; \ 37 __typeof__(*(ptr)) __gu_val; \
38 unsigned long __gu_addr; \ 38 unsigned long __gu_addr; \
39 __asm__("":"=r" (__gu_val)); \ 39 __asm__("":"=r" (__gu_val)); \
40 __gu_addr = (unsigned long) (ptr); \ 40 __gu_addr = (unsigned long) (ptr); \
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
index fcec52bafb25..c4729f531919 100644
--- a/include/asm-mips/sgi/hpc3.h
+++ b/include/asm-mips/sgi/hpc3.h
@@ -206,7 +206,7 @@ struct hpc3_regs {
206#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */ 206#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
207#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */ 207#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
208 208
209 volatile u32 eeprom; /* EEPROM data reg. */ 209 u32 eeprom; /* EEPROM data reg. */
210#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */ 210#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
211#define HPC3_EEPROM_CSEL 0x02 /* Chip select */ 211#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
212#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */ 212#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
index 6592f3bd1999..f4981c4f16bb 100644
--- a/include/asm-mips/sgi/ip22.h
+++ b/include/asm-mips/sgi/ip22.h
@@ -72,7 +72,7 @@
72 72
73#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE) 73#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
74 74
75extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg); 75extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
76extern unsigned short ip22_nvram_read(int reg); 76extern unsigned short ip22_nvram_read(int reg);
77 77
78#endif 78#endif
diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h
index c52f7834c7c8..1576c2394de8 100644
--- a/include/asm-mips/sgi/mc.h
+++ b/include/asm-mips/sgi/mc.h
@@ -57,7 +57,7 @@ struct sgimc_regs {
57 volatile u32 divider; /* Divider reg for RPSS */ 57 volatile u32 divider; /* Divider reg for RPSS */
58 58
59 u32 _unused5; 59 u32 _unused5;
60 volatile u32 eeprom; /* EEPROM byte reg for r4k */ 60 u32 eeprom; /* EEPROM byte reg for r4k */
61#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ 61#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
62#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ 62#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
63#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */ 63#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
index 42d4cf00efd3..c0d5206020fd 100644
--- a/include/asm-mips/sibyte/bcm1480_int.h
+++ b/include/asm-mips/sibyte/bcm1480_int.h
@@ -157,6 +157,7 @@
157 * Mask values for each interrupt 157 * Mask values for each interrupt
158 */ 158 */
159 159
160#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F))
160#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) 161#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
161#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) 162#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
162 163
@@ -195,6 +196,7 @@
195#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) 196#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
196#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) 197#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
197#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) 198#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
199#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0)
198#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) 200#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
199#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) 201#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
200#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) 202#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h
index 6bdc941afc91..a6a437451da4 100644
--- a/include/asm-mips/sibyte/bcm1480_mc.h
+++ b/include/asm-mips/sibyte/bcm1480_mc.h
@@ -382,6 +382,10 @@
382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) 382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)
383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) 383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)
384 384
385#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0)
386#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0)
387#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0)
388
385#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) 389#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)
386 390
387/* 391/*
@@ -412,6 +416,8 @@
412#define K_BCM1480_MC_DRAM_TYPE_DDR2 2 416#define K_BCM1480_MC_DRAM_TYPE_DDR2 2
413#endif 417#endif
414 418
419#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0
420
415#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) 421#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
416#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) 422#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
417 423
@@ -511,6 +517,22 @@
511#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) 517#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31)
512 518
513#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) 519#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32)
520
521#define S_BCM1480_MC_ODT0 0
522#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0)
523#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0)
524
525#define S_BCM1480_MC_ODT2 8
526#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2)
527#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2)
528
529#define S_BCM1480_MC_ODT4 16
530#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4)
531#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4)
532
533#define S_BCM1480_MC_ODT6 24
534#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6)
535#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6)
514#endif 536#endif
515 537
516/* 538/*
@@ -588,11 +610,11 @@
588#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) 610#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47)
589#endif 611#endif
590 612
591#define S_BCM1480_MC_DLL_DEFAULT 48 613#define S_BCM1480_MC_DLL_DEFAULT 48
592#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) 614#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT)
593#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) 615#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT)
594#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) 616#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT)
595#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) 617#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10)
596 618
597#if SIBYTE_HDR_FEATURE(1480, PASS2) 619#if SIBYTE_HDR_FEATURE(1480, PASS2)
598#define S_BCM1480_MC_DLL_REGCTRL 54 620#define S_BCM1480_MC_DLL_REGCTRL 54
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
index c2dd2fe3047c..bda391d3af85 100644
--- a/include/asm-mips/sibyte/bcm1480_regs.h
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -230,6 +230,7 @@
230 230
231#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) 231#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))
232#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) 232#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))
233#define A_BCM1480_DUART_IN_PORT(chan) (A_BCM1480_DUART(chan) + R_DUART_INP_ORT)
233 234
234/* 235/*
235 * These constants are the absolute addresses. 236 * These constants are the absolute addresses.
@@ -404,6 +405,21 @@
404#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ 405#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */
405#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ 406#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */
406 407
408/*
409 * these macros work together to build the address of a mailbox
410 * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
411 * for mbox_0_set_cpu2 returns 0x00100240C8
412 */
413#define R_BCM1480_IMR_MAILBOX_CPU 0x00
414#define R_BCM1480_IMR_MAILBOX_SET 0x08
415#define R_BCM1480_IMR_MAILBOX_CLR 0x10
416#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
417#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \
418 (A_BCM1480_IMR_CPU0_BASE + \
419 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
420 (cpu * BCM1480_IMR_REGISTER_SPACING) + \
421 (R_BCM1480_IMR_MAILBOX_0_CPU + reg))
422
407/* ********************************************************************* 423/* *********************************************************************
408 * System Performance Counter Registers (Section 4.7) 424 * System Performance Counter Registers (Section 4.7)
409 ********************************************************************* */ 425 ********************************************************************* */
@@ -428,6 +444,10 @@
428#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 444#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500
429#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 445#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508
430 446
447#define BCM1480_SCD_NUM_PERF_CNT 8
448#define BCM1480_SCD_PERF_CNT_SPACING 8
449#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))
450
431/* ********************************************************************* 451/* *********************************************************************
432 * System Bus Watcher Registers (Section 4.8) 452 * System Bus Watcher Registers (Section 4.8)
433 ********************************************************************* */ 453 ********************************************************************* */
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h
index 648bed96780f..6111d6dcf117 100644
--- a/include/asm-mips/sibyte/bcm1480_scd.h
+++ b/include/asm-mips/sibyte/bcm1480_scd.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003,2004,2005
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -78,6 +78,7 @@
78#define K_SYS_PART_BCM1280 0x1206 78#define K_SYS_PART_BCM1280 0x1206
79#define K_SYS_PART_BCM1455 0x1407 79#define K_SYS_PART_BCM1455 0x1407
80#define K_SYS_PART_BCM1255 0x1257 80#define K_SYS_PART_BCM1255 0x1257
81#define K_SYS_PART_BCM1158 0x1156
81 82
82/* 83/*
83 * Manufacturing Information Register (Table 14) 84 * Manufacturing Information Register (Table 14)
@@ -237,58 +238,42 @@
237 * System Performance Counter Configuration Register (Table 31) 238 * System Performance Counter Configuration Register (Table 31)
238 * Register: PERF_CNT_CFG_0 239 * Register: PERF_CNT_CFG_0
239 * 240 *
240 * Since the clear/enable bits are moved compared to the 241 * SPC_CFG_SRC[0-3] is the same as the 1250.
241 * 1250 and there are more fields, this register will be BCM1480 specific. 242 * SPC_CFG_SRC[4-7] only exist on the 1480
243 * The clear/enable bits are in different locations on the 1250 and 1480.
242 */ 244 */
243 245
244#define S_BCM1480_SPC_CFG_SRC0 0 246#define S_SPC_CFG_SRC4 32
245#define M_BCM1480_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0) 247#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4)
246#define V_BCM1480_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0) 248#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4)
247#define G_BCM1480_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0) 249#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4)
248 250
249#define S_BCM1480_SPC_CFG_SRC1 8 251#define S_SPC_CFG_SRC5 40
250#define M_BCM1480_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1) 252#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5)
251#define V_BCM1480_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1) 253#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5)
252#define G_BCM1480_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1) 254#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5)
253 255
254#define S_BCM1480_SPC_CFG_SRC2 16 256#define S_SPC_CFG_SRC6 48
255#define M_BCM1480_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2) 257#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6)
256#define V_BCM1480_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2) 258#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6)
257#define G_BCM1480_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2) 259#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6)
258 260
259#define S_BCM1480_SPC_CFG_SRC3 24 261#define S_SPC_CFG_SRC7 56
260#define M_BCM1480_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3) 262#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7)
261#define V_BCM1480_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3) 263#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7)
262#define G_BCM1480_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3) 264#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7)
263
264#define S_BCM1480_SPC_CFG_SRC4 32
265#define M_BCM1480_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4)
266#define V_BCM1480_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4)
267#define G_BCM1480_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4)
268
269#define S_BCM1480_SPC_CFG_SRC5 40
270#define M_BCM1480_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5)
271#define V_BCM1480_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5)
272#define G_BCM1480_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5)
273
274#define S_BCM1480_SPC_CFG_SRC6 48
275#define M_BCM1480_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6)
276#define V_BCM1480_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6)
277#define G_BCM1480_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6)
278
279#define S_BCM1480_SPC_CFG_SRC7 56
280#define M_BCM1480_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7)
281#define V_BCM1480_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7)
282#define G_BCM1480_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7)
283 265
284/* 266/*
285 * System Performance Counter Control Register (Table 32) 267 * System Performance Counter Control Register (Table 32)
286 * Register: PERF_CNT_CFG_1 268 * Register: PERF_CNT_CFG_1
287 * BCM1480 specific 269 * BCM1480 specific
288 */ 270 */
289 271#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0)
290#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) 272#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1)
291#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) 273#if SIBYTE_HDR_FEATURE_CHIP(1480)
274#define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR
275#define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE
276#endif
292 277
293/* 278/*
294 * System Performance Counters (Table 33) 279 * System Performance Counters (Table 33)
@@ -405,20 +390,10 @@
405 * Trace Control Register (Table 49) 390 * Trace Control Register (Table 49)
406 * Register: TRACE_CFG 391 * Register: TRACE_CFG
407 * 392 *
408 * Bits 0..8 are the same as the BCM1250, rest are different. 393 * BCM1480 changes to this register (other than location of the CUR_ADDR field)
409 * Entire register is redefined below. 394 * are defined below.
410 */ 395 */
411 396
412#define M_BCM1480_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
413#define M_BCM1480_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
414#define M_BCM1480_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
415#define M_BCM1480_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
416#define M_BCM1480_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
417#define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
418#define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
419#define M_BCM1480_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
420#define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT _SB_MAKEMASK1(8)
421
422#define S_BCM1480_SCD_TRACE_CFG_MODE 16 397#define S_BCM1480_SCD_TRACE_CFG_MODE 16
423#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) 398#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)
424#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) 399#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)
@@ -428,9 +403,4 @@
428#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 403#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
429#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 404#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2
430 405
431#define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR 24
432#define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
433#define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
434#define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
435
436#endif /* _BCM1480_SCD_H */ 406#endif /* _BCM1480_SCD_H */
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index 3dfe29ed42a8..73bce901a378 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation 2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -19,8 +19,8 @@
19#ifndef _SIBYTE_BOARD_H 19#ifndef _SIBYTE_BOARD_H
20#define _SIBYTE_BOARD_H 20#define _SIBYTE_BOARD_H
21 21
22
23#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \ 22#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
23 defined(CONFIG_SIBYTE_PT1120) || defined(CONFIG_SIBYTE_PT1125) || \
24 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \ 24 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
25 defined(CONFIG_SIBYTE_LITTLESUR) 25 defined(CONFIG_SIBYTE_LITTLESUR)
26#include <asm/sibyte/swarm.h> 26#include <asm/sibyte/swarm.h>
@@ -55,6 +55,16 @@
55#define setleds(t0,t1,c0,c1,c2,c3) 55#define setleds(t0,t1,c0,c1,c2,c3)
56#endif /* LEDS_PHYS */ 56#endif /* LEDS_PHYS */
57 57
58#else
59
60void swarm_setup(void);
61
62#ifdef LEDS_PHYS
63extern void setleds(char *str);
64#else
65#define setleds(s) do { } while (0)
66#endif /* LEDS_PHYS */
67
58#endif /* __ASSEMBLY__ */ 68#endif /* __ASSEMBLY__ */
59 69
60#endif /* _SIBYTE_BOARD_H */ 70#endif /* _SIBYTE_BOARD_H */
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
index 57c53e62a37a..11cad71323e8 100644
--- a/include/asm-mips/sibyte/carmel.h
+++ b/include/asm-mips/sibyte/carmel.h
@@ -18,7 +18,6 @@
18#ifndef __ASM_SIBYTE_CARMEL_H 18#ifndef __ASM_SIBYTE_CARMEL_H
19#define __ASM_SIBYTE_CARMEL_H 19#define __ASM_SIBYTE_CARMEL_H
20 20
21
22#include <asm/sibyte/sb1250.h> 21#include <asm/sibyte/sb1250.h>
23#include <asm/sibyte/sb1250_int.h> 22#include <asm/sibyte/sb1250_int.h>
24 23
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index 05c7b39f1b02..94e8299b0a2a 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -45,8 +45,6 @@
45 * First, the interrupt numbers. 45 * First, the interrupt numbers.
46 */ 46 */
47 47
48#if SIBYTE_HDR_FEATURE_1250_112x
49
50#define K_INT_SOURCES 64 48#define K_INT_SOURCES 64
51 49
52#define K_INT_WATCHDOG_TIMER_0 0 50#define K_INT_WATCHDOG_TIMER_0 0
@@ -152,6 +150,7 @@
152#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) 150#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
153#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) 151#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
154#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) 152#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
153#define M_INT_MBOX_ALL _SB_MAKEMASK(4,K_INT_MBOX_0)
155#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
156#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) 155#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
157#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) 156#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
@@ -247,5 +246,3 @@
247 246
248 247
249#endif /* 1250/112x */ 248#endif /* 1250/112x */
250
251#endif
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index adfc688fa559..833c8b59d687 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -129,9 +129,9 @@
129#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 129#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42)
130#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 130#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43)
131 131
132#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 132#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
133#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 133#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
134#endif /* 1250 PASS2 || 112x PASS1 */ 134#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
135 135
136#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 136#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
137#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 137#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
@@ -223,9 +223,9 @@
223/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 223/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
224/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ 224/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */
225#endif /* up to 1250 PASS1 */ 225#endif /* up to 1250 PASS1 */
226#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 226#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
227#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) 227#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH)
228#endif /* 1250 PASS2 || 112x PASS1 */ 228#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
229#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 229#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH)
230#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 230#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH)
231 231
@@ -234,9 +234,9 @@
234/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 234/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
235/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ 235/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */
236#endif /* up to 1250 PASS1 */ 236#endif /* up to 1250 PASS1 */
237#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 237#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
238#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) 238#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH)
239#endif /* 1250 PASS2 || 112x PASS1 */ 239#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
240#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 240#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH)
241#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 241#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH)
242 242
@@ -260,12 +260,12 @@
260#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 260#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH)
261#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 261#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH)
262 262
263#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 263#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
264#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 264#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
265#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) 265#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH)
266#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) 266#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH)
267#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) 267#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH)
268#endif /* 1250 PASS2 || 112x PASS1 */ 268#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
269 269
270/* 270/*
271 * MAC Frame Configuration Registers (Table 9-15) 271 * MAC Frame Configuration Registers (Table 9-15)
@@ -462,9 +462,9 @@
462#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 462#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44)
463#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 463#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45)
464#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 464#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46)
465#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 465#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
466#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ 466#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */
467#endif /* 1250 PASS2 || 112x PASS1 */ 467#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
468 468
469#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 469#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
470#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 470#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR)
@@ -598,9 +598,9 @@
598#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 598#define M_MAC_MCAST_INV _SB_MAKEMASK1(4)
599#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 599#define M_MAC_BCAST_EN _SB_MAKEMASK1(5)
600#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 600#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6)
601#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 601#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
602#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) 602#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7)
603#endif /* 1250 PASS2 || 112x PASS1 */ 603#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
604 604
605#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 605#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
606#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 606#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET)
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 26e421498c97..4fe848ffbc31 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -295,7 +295,7 @@
295 295
296#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 296#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
297#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) 297#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
298#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38) 298#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37)
299#endif /* 1250 PASS3 || 112x PASS1 */ 299#endif /* 1250 PASS3 || 112x PASS1 */
300 300
301 301
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index bab3a4580a36..da7c188993c9 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -131,6 +131,7 @@
131 131
132#endif 132#endif
133 133
134
134/* ********************************************************************* 135/* *********************************************************************
135 * PCI Interface Registers 136 * PCI Interface Registers
136 ********************************************************************* */ 137 ********************************************************************* */
@@ -239,14 +240,14 @@
239#define R_MAC_VLANTAG 0x00000110 240#define R_MAC_VLANTAG 0x00000110
240#define R_MAC_FRAMECFG 0x00000118 241#define R_MAC_FRAMECFG 0x00000118
241#define R_MAC_EOPCNT 0x00000120 242#define R_MAC_EOPCNT 0x00000120
242#define R_MAC_FIFO_PTRS 0x00000130 243#define R_MAC_FIFO_PTRS 0x00000128
243#define R_MAC_ADFILTER_CFG 0x00000200 244#define R_MAC_ADFILTER_CFG 0x00000200
244#define R_MAC_ETHERNET_ADDR 0x00000208 245#define R_MAC_ETHERNET_ADDR 0x00000208
245#define R_MAC_PKT_TYPE 0x00000210 246#define R_MAC_PKT_TYPE 0x00000210
246#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 247#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
247#define R_MAC_ADMASK0 0x00000218 248#define R_MAC_ADMASK0 0x00000218
248#define R_MAC_ADMASK1 0x00000220 249#define R_MAC_ADMASK1 0x00000220
249#endif /* 1250 PASS3 || 112x PASS1 */ 250#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
250#define R_MAC_HASH_BASE 0x00000240 251#define R_MAC_HASH_BASE 0x00000240
251#define R_MAC_ADDR_BASE 0x00000280 252#define R_MAC_ADDR_BASE 0x00000280
252#define R_MAC_CHLO0_BASE 0x00000300 253#define R_MAC_CHLO0_BASE 0x00000300
@@ -256,9 +257,9 @@
256#define R_MAC_INT_MASK 0x00000410 257#define R_MAC_INT_MASK 0x00000410
257#define R_MAC_TXD_CTL 0x00000420 258#define R_MAC_TXD_CTL 0x00000420
258#define R_MAC_MDIO 0x00000428 259#define R_MAC_MDIO 0x00000428
259#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 260#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
260#define R_MAC_STATUS1 0x00000430 261#define R_MAC_STATUS1 0x00000430
261#endif /* 1250 PASS2 || 112x PASS1 */ 262#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
262#define R_MAC_DEBUG_STATUS 0x00000448 263#define R_MAC_DEBUG_STATUS 0x00000448
263 264
264#define MAC_HASH_COUNT 8 265#define MAC_HASH_COUNT 8
@@ -289,11 +290,11 @@
289#define R_DUART_RX_HOLD 0x160 290#define R_DUART_RX_HOLD 0x160
290#define R_DUART_TX_HOLD 0x170 291#define R_DUART_TX_HOLD 0x170
291 292
292#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 293#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
293#define R_DUART_FULL_CTL 0x140 294#define R_DUART_FULL_CTL 0x140
294#define R_DUART_OPCR_X 0x180 295#define R_DUART_OPCR_X 0x180
295#define R_DUART_AUXCTL_X 0x190 296#define R_DUART_AUXCTL_X 0x190
296#endif /* 1250 PASS2 || 112x PASS1 */ 297#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
297 298
298 299
299/* 300/*
@@ -308,6 +309,7 @@
308#define R_DUART_IMR_B 0x350 309#define R_DUART_IMR_B 0x350
309#define R_DUART_OUT_PORT 0x360 310#define R_DUART_OUT_PORT 0x360
310#define R_DUART_OPCR 0x370 311#define R_DUART_OPCR 0x370
312#define R_DUART_IN_PORT 0x380
311 313
312#define R_DUART_SET_OPR 0x3B0 314#define R_DUART_SET_OPR 0x3B0
313#define R_DUART_CLEAR_OPR 0x3C0 315#define R_DUART_CLEAR_OPR 0x3C0
@@ -685,12 +687,17 @@
685#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 687#define A_ADDR_TRAP_REG_DEBUG 0x0010020460
686#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 688#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
687 689
690#define ADDR_TRAP_SPACING 8
691#define NUM_ADDR_TRAP 4
692#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
693#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
694#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
695
688 696
689/* ********************************************************************* 697/* *********************************************************************
690 * System Interrupt Mapper Registers 698 * System Interrupt Mapper Registers
691 ********************************************************************* */ 699 ********************************************************************* */
692 700
693#if SIBYTE_HDR_FEATURE_1250_112x
694#define A_IMR_CPU0_BASE 0x0010020000 701#define A_IMR_CPU0_BASE 0x0010020000
695#define A_IMR_CPU1_BASE 0x0010022000 702#define A_IMR_CPU1_BASE 0x0010022000
696#define IMR_REGISTER_SPACING 0x2000 703#define IMR_REGISTER_SPACING 0x2000
@@ -700,6 +707,7 @@
700#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 707#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))
701 708
702#define R_IMR_INTERRUPT_DIAG 0x0010 709#define R_IMR_INTERRUPT_DIAG 0x0010
710#define R_IMR_INTERRUPT_LDT 0x0018
703#define R_IMR_INTERRUPT_MASK 0x0028 711#define R_IMR_INTERRUPT_MASK 0x0028
704#define R_IMR_INTERRUPT_TRACE 0x0038 712#define R_IMR_INTERRUPT_TRACE 0x0038
705#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 713#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040
@@ -715,7 +723,14 @@
715#define R_IMR_INTERRUPT_STATUS_COUNT 7 723#define R_IMR_INTERRUPT_STATUS_COUNT 7
716#define R_IMR_INTERRUPT_MAP_BASE 0x0200 724#define R_IMR_INTERRUPT_MAP_BASE 0x0200
717#define R_IMR_INTERRUPT_MAP_COUNT 64 725#define R_IMR_INTERRUPT_MAP_COUNT 64
718#endif /* 1250/112x */ 726
727/*
728 * these macros work together to build the address of a mailbox
729 * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
730 * for mbox_0_set_cpu2 returns 0x00100240C8
731 */
732#define A_MAILBOX_REGISTER(reg,cpu) \
733 (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
719 734
720/* ********************************************************************* 735/* *********************************************************************
721 * System Performance Counter Registers 736 * System Performance Counter Registers
@@ -727,6 +742,10 @@
727#define A_SCD_PERF_CNT_2 0x00100204E0 742#define A_SCD_PERF_CNT_2 0x00100204E0
728#define A_SCD_PERF_CNT_3 0x00100204E8 743#define A_SCD_PERF_CNT_3 0x00100204E8
729 744
745#define SCD_NUM_PERF_CNT 4
746#define SCD_PERF_CNT_SPACING 8
747#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
748
730/* ********************************************************************* 749/* *********************************************************************
731 * System Bus Watcher Registers 750 * System Bus Watcher Registers
732 ********************************************************************* */ 751 ********************************************************************* */
@@ -772,6 +791,15 @@
772#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 791#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
773#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 792#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
774 793
794#define TRACE_REGISTER_SPACING 8
795#define TRACE_NUM_REGISTERS 8
796#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
797 (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
798 (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
799#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
800 (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
801 (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
802
775/* ********************************************************************* 803/* *********************************************************************
776 * System Generic DMA Registers 804 * System Generic DMA Registers
777 ********************************************************************* */ 805 ********************************************************************* */
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index b6a7d8f6ced5..9ea3da367ab6 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003,2004,2005
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -150,7 +150,7 @@
150 * (For the assembler version, sysrev and dest may be the same register. 150 * (For the assembler version, sysrev and dest may be the same register.
151 * Also, it clobbers AT.) 151 * Also, it clobbers AT.)
152 */ 152 */
153#ifdef __ASSEMBLY__ 153#ifdef __ASSEMBLER__
154#define SYS_SOC_TYPE(dest, sysrev) \ 154#define SYS_SOC_TYPE(dest, sysrev) \
155 .set push ; \ 155 .set push ; \
156 .set reorder ; \ 156 .set reorder ; \
@@ -214,6 +214,7 @@
214#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 214#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
215#endif 215#endif
216 216
217
217/* 218/*
218 * System Config Register (Table 4-2) 219 * System Config Register (Table 4-2)
219 * Register: SCD_SYSTEM_CFG 220 * Register: SCD_SYSTEM_CFG
@@ -360,13 +361,13 @@
360 */ 361 */
361 362
362#define V_SCD_TIMER_FREQ 1000000 363#define V_SCD_TIMER_FREQ 1000000
363#define V_SCD_TIMER_WIDTH 23
364 364
365#define S_SCD_TIMER_INIT 0 365#define S_SCD_TIMER_INIT 0
366#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT) 366#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT)
367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
369 369
370#define V_SCD_TIMER_WIDTH 23
370#define S_SCD_TIMER_CNT 0 371#define S_SCD_TIMER_CNT 0
371#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) 372#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
372#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 373#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
@@ -380,7 +381,6 @@
380 * System Performance Counters 381 * System Performance Counters
381 */ 382 */
382 383
383#if SIBYTE_HDR_FEATURE_1250_112x
384#define S_SPC_CFG_SRC0 0 384#define S_SPC_CFG_SRC0 0
385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
@@ -401,6 +401,7 @@
401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
403 403
404#if SIBYTE_HDR_FEATURE_1250_112x
404#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 405#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
405#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 406#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
406#endif 407#endif
@@ -516,8 +517,6 @@
516 * Trace Buffer Config register 517 * Trace Buffer Config register
517 */ 518 */
518 519
519#if SIBYTE_HDR_FEATURE_1250_112x
520
521#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 520#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
522#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 521#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
523#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 522#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
@@ -526,17 +525,26 @@
526#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 525#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
527#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 526#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
528#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 527#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
529#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 528#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
530#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 529#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
531#endif /* 1250 PASS2 || 112x PASS1 */ 530#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
532 531
532/*
533 * This field is the same on the 1250/112x and 1480, just located in
534 * a slightly different place in the register.
535 */
536#if SIBYTE_HDR_FEATURE_1250_112x
533#define S_SCD_TRACE_CFG_CUR_ADDR 10 537#define S_SCD_TRACE_CFG_CUR_ADDR 10
538#else
539#if SIBYTE_HDR_FEATURE_CHIP(1480)
540#define S_SCD_TRACE_CFG_CUR_ADDR 24
541#endif /* 1480 */
542#endif /* 1250/112x */
543
534#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 544#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
535#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 545#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
536#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 546#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
537 547
538#endif /* 1250/112x */
539
540/* 548/*
541 * Trace Event registers 549 * Trace Event registers
542 */ 550 */
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
index 86db37e5ad85..540865fa7ec3 100644
--- a/include/asm-mips/sibyte/swarm.h
+++ b/include/asm-mips/sibyte/swarm.h
@@ -32,6 +32,18 @@
32#define SIBYTE_HAVE_IDE 1 32#define SIBYTE_HAVE_IDE 1
33#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200" 33#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
34#endif 34#endif
35#ifdef CONFIG_SIBYTE_PT1120
36#define SIBYTE_BOARD_NAME "PT1120"
37#define SIBYTE_HAVE_PCMCIA 1
38#define SIBYTE_HAVE_IDE 1
39#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
40#endif
41#ifdef CONFIG_SIBYTE_PT1125
42#define SIBYTE_BOARD_NAME "PT1125"
43#define SIBYTE_HAVE_PCMCIA 1
44#define SIBYTE_HAVE_IDE 1
45#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
46#endif
35#ifdef CONFIG_SIBYTE_LITTLESUR 47#ifdef CONFIG_SIBYTE_LITTLESUR
36#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" 48#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
37#define SIBYTE_HAVE_PCMCIA 0 49#define SIBYTE_HAVE_PCMCIA 0
diff --git a/include/asm-s390/bug.h b/include/asm-s390/bug.h
index 876898363944..838684dc6d35 100644
--- a/include/asm-s390/bug.h
+++ b/include/asm-s390/bug.h
@@ -1,27 +1,70 @@
1#ifndef _S390_BUG_H 1#ifndef _ASM_S390_BUG_H
2#define _S390_BUG_H 2#define _ASM_S390_BUG_H
3 3
4#include <linux/kernel.h> 4#include <linux/kernel.h>
5 5
6#ifdef CONFIG_BUG 6#ifdef CONFIG_BUG
7 7
8static inline __attribute__((noreturn)) void __do_illegal_op(void) 8#ifdef CONFIG_64BIT
9{ 9#define S390_LONG ".quad"
10#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 3)
11 __builtin_trap();
12#else 10#else
13 asm volatile(".long 0"); 11#define S390_LONG ".long"
14#endif 12#endif
15}
16 13
17#define BUG() do { \ 14#ifdef CONFIG_DEBUG_BUGVERBOSE
18 printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ 15
19 __do_illegal_op(); \ 16#define __EMIT_BUG(x) do { \
17 asm volatile( \
18 "0: j 0b+2\n" \
19 "1:\n" \
20 ".section .rodata.str,\"aMS\",@progbits,1\n" \
21 "2: .asciz \""__FILE__"\"\n" \
22 ".previous\n" \
23 ".section __bug_table,\"a\"\n" \
24 "3:\t" S390_LONG "\t1b,2b\n" \
25 " .short %0,%1\n" \
26 " .org 3b+%2\n" \
27 ".previous\n" \
28 : : "i" (__LINE__), \
29 "i" (x), \
30 "i" (sizeof(struct bug_entry))); \
20} while (0) 31} while (0)
21 32
33#else /* CONFIG_DEBUG_BUGVERBOSE */
34
35#define __EMIT_BUG(x) do { \
36 asm volatile( \
37 "0: j 0b+2\n" \
38 "1:\n" \
39 ".section __bug_table,\"a\"\n" \
40 "2:\t" S390_LONG "\t1b\n" \
41 " .short %0\n" \
42 " .org 2b+%1\n" \
43 ".previous\n" \
44 : : "i" (x), \
45 "i" (sizeof(struct bug_entry))); \
46} while (0)
47
48#endif /* CONFIG_DEBUG_BUGVERBOSE */
49
50#define BUG() __EMIT_BUG(0)
51
52#define WARN_ON(x) ({ \
53 typeof(x) __ret_warn_on = (x); \
54 if (__builtin_constant_p(__ret_warn_on)) { \
55 if (__ret_warn_on) \
56 __EMIT_BUG(BUGFLAG_WARNING); \
57 } else { \
58 if (unlikely(__ret_warn_on)) \
59 __EMIT_BUG(BUGFLAG_WARNING); \
60 } \
61 unlikely(__ret_warn_on); \
62})
63
22#define HAVE_ARCH_BUG 64#define HAVE_ARCH_BUG
23#endif 65#define HAVE_ARCH_WARN_ON
66#endif /* CONFIG_BUG */
24 67
25#include <asm-generic/bug.h> 68#include <asm-generic/bug.h>
26 69
27#endif 70#endif /* _ASM_S390_BUG_H */
diff --git a/include/asm-s390/ccwgroup.h b/include/asm-s390/ccwgroup.h
index d2f9c0d53a97..925b3ddfa141 100644
--- a/include/asm-s390/ccwgroup.h
+++ b/include/asm-s390/ccwgroup.h
@@ -11,6 +11,7 @@ struct ccwgroup_device {
11 CCWGROUP_ONLINE, 11 CCWGROUP_ONLINE,
12 } state; 12 } state;
13 atomic_t onoff; 13 atomic_t onoff;
14 struct mutex reg_mutex;
14 unsigned int count; /* number of attached slave devices */ 15 unsigned int count; /* number of attached slave devices */
15 struct device dev; /* master device */ 16 struct device dev; /* master device */
16 struct ccw_device *cdev[0]; /* variable number, allocate as needed */ 17 struct ccw_device *cdev[0]; /* variable number, allocate as needed */
diff --git a/include/asm-s390/chpid.h b/include/asm-s390/chpid.h
new file mode 100644
index 000000000000..b203336fd892
--- /dev/null
+++ b/include/asm-s390/chpid.h
@@ -0,0 +1,53 @@
1/*
2 * drivers/s390/cio/chpid.h
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_CHPID_H
9#define _ASM_S390_CHPID_H _ASM_S390_CHPID_H
10
11#include <linux/string.h>
12#include <asm/types.h>
13#include <asm/cio.h>
14
15#define __MAX_CHPID 255
16
17struct chp_id {
18 u8 reserved1;
19 u8 cssid;
20 u8 reserved2;
21 u8 id;
22} __attribute__((packed));
23
24static inline void chp_id_init(struct chp_id *chpid)
25{
26 memset(chpid, 0, sizeof(struct chp_id));
27}
28
29static inline int chp_id_is_equal(struct chp_id *a, struct chp_id *b)
30{
31 return (a->id == b->id) && (a->cssid == b->cssid);
32}
33
34static inline void chp_id_next(struct chp_id *chpid)
35{
36 if (chpid->id < __MAX_CHPID)
37 chpid->id++;
38 else {
39 chpid->id = 0;
40 chpid->cssid++;
41 }
42}
43
44static inline int chp_id_is_valid(struct chp_id *chpid)
45{
46 return (chpid->cssid <= __MAX_CSSID);
47}
48
49
50#define chp_id_for_each(c) \
51 for (chp_id_init(c); chp_id_is_valid(c); chp_id_next(c))
52
53#endif /* _ASM_S390_CHPID_H */
diff --git a/include/asm-s390/cio.h b/include/asm-s390/cio.h
index d92785030980..f738d2827582 100644
--- a/include/asm-s390/cio.h
+++ b/include/asm-s390/cio.h
@@ -13,6 +13,7 @@
13#ifdef __KERNEL__ 13#ifdef __KERNEL__
14 14
15#define LPM_ANYPATH 0xff 15#define LPM_ANYPATH 0xff
16#define __MAX_CSSID 0
16 17
17/* 18/*
18 * subchannel status word 19 * subchannel status word
@@ -292,6 +293,13 @@ extern void css_schedule_reprobe(void);
292 293
293extern void reipl_ccw_dev(struct ccw_dev_id *id); 294extern void reipl_ccw_dev(struct ccw_dev_id *id);
294 295
296struct cio_iplinfo {
297 u16 devno;
298 int is_qdio;
299};
300
301extern int cio_get_iplinfo(struct cio_iplinfo *iplinfo);
302
295#endif 303#endif
296 304
297#endif 305#endif
diff --git a/include/asm-s390/ipl.h b/include/asm-s390/ipl.h
index 0eb64083480a..bdcd448d43fb 100644
--- a/include/asm-s390/ipl.h
+++ b/include/asm-s390/ipl.h
@@ -8,6 +8,8 @@
8#define _ASM_S390_IPL_H 8#define _ASM_S390_IPL_H
9 9
10#include <asm/types.h> 10#include <asm/types.h>
11#include <asm/cio.h>
12#include <asm/setup.h>
11 13
12#define IPL_PARMBLOCK_ORIGIN 0x2000 14#define IPL_PARMBLOCK_ORIGIN 0x2000
13 15
@@ -74,12 +76,12 @@ struct ipl_parameter_block {
74} __attribute__((packed)); 76} __attribute__((packed));
75 77
76/* 78/*
77 * IPL validity flags and parameters as detected in head.S 79 * IPL validity flags
78 */ 80 */
79extern u32 ipl_flags; 81extern u32 ipl_flags;
80extern u16 ipl_devno;
81 82
82extern u32 dump_prefix_page; 83extern u32 dump_prefix_page;
84
83extern void do_reipl(void); 85extern void do_reipl(void);
84extern void ipl_save_parameters(void); 86extern void ipl_save_parameters(void);
85 87
@@ -89,6 +91,35 @@ enum {
89 IPL_NSS_VALID = 4, 91 IPL_NSS_VALID = 4,
90}; 92};
91 93
94enum ipl_type {
95 IPL_TYPE_UNKNOWN = 1,
96 IPL_TYPE_CCW = 2,
97 IPL_TYPE_FCP = 4,
98 IPL_TYPE_FCP_DUMP = 8,
99 IPL_TYPE_NSS = 16,
100};
101
102struct ipl_info
103{
104 enum ipl_type type;
105 union {
106 struct {
107 struct ccw_dev_id dev_id;
108 } ccw;
109 struct {
110 struct ccw_dev_id dev_id;
111 u64 wwpn;
112 u64 lun;
113 } fcp;
114 struct {
115 char name[NSS_NAME_SIZE + 1];
116 } nss;
117 } data;
118};
119
120extern struct ipl_info ipl_info;
121extern void setup_ipl_info(void);
122
92/* 123/*
93 * DIAG 308 support 124 * DIAG 308 support
94 */ 125 */
diff --git a/include/asm-s390/lowcore.h b/include/asm-s390/lowcore.h
index 4a31d0a7ee83..ffc9788a21a7 100644
--- a/include/asm-s390/lowcore.h
+++ b/include/asm-s390/lowcore.h
@@ -147,6 +147,52 @@ void pgm_check_handler(void);
147void mcck_int_handler(void); 147void mcck_int_handler(void);
148void io_int_handler(void); 148void io_int_handler(void);
149 149
150struct save_area_s390 {
151 u32 ext_save;
152 u64 timer;
153 u64 clk_cmp;
154 u8 pad1[24];
155 u8 psw[8];
156 u32 pref_reg;
157 u8 pad2[20];
158 u32 acc_regs[16];
159 u64 fp_regs[4];
160 u32 gp_regs[16];
161 u32 ctrl_regs[16];
162} __attribute__((packed));
163
164struct save_area_s390x {
165 u64 fp_regs[16];
166 u64 gp_regs[16];
167 u8 psw[16];
168 u8 pad1[8];
169 u32 pref_reg;
170 u32 fp_ctrl_reg;
171 u8 pad2[4];
172 u32 tod_reg;
173 u64 timer;
174 u64 clk_cmp;
175 u8 pad3[8];
176 u32 acc_regs[16];
177 u64 ctrl_regs[16];
178} __attribute__((packed));
179
180union save_area {
181 struct save_area_s390 s390;
182 struct save_area_s390x s390x;
183};
184
185#define SAVE_AREA_BASE_S390 0xd4
186#define SAVE_AREA_BASE_S390X 0x1200
187
188#ifndef __s390x__
189#define SAVE_AREA_SIZE sizeof(struct save_area_s390)
190#define SAVE_AREA_BASE SAVE_AREA_BASE_S390
191#else
192#define SAVE_AREA_SIZE sizeof(struct save_area_s390x)
193#define SAVE_AREA_BASE SAVE_AREA_BASE_S390X
194#endif
195
150struct _lowcore 196struct _lowcore
151{ 197{
152#ifndef __s390x__ 198#ifndef __s390x__
diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h
index 13c16546eff5..8fe8d42e64c3 100644
--- a/include/asm-s390/pgtable.h
+++ b/include/asm-s390/pgtable.h
@@ -753,14 +753,14 @@ ptep_establish(struct vm_area_struct *vma,
753 * should therefore only be called if it is not mapped in any 753 * should therefore only be called if it is not mapped in any
754 * address space. 754 * address space.
755 */ 755 */
756static inline int page_test_and_clear_dirty(struct page *page) 756static inline int page_test_dirty(struct page *page)
757{ 757{
758 unsigned long physpage = page_to_phys(page); 758 return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0;
759 int skey = page_get_storage_key(physpage); 759}
760 760
761 if (skey & _PAGE_CHANGED) 761static inline void page_clear_dirty(struct page *page)
762 page_set_storage_key(physpage, skey & ~_PAGE_CHANGED); 762{
763 return skey & _PAGE_CHANGED; 763 page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY);
764} 764}
765 765
766/* 766/*
@@ -953,7 +953,8 @@ extern void memmap_init(unsigned long, int, unsigned long, unsigned long);
953#define __HAVE_ARCH_PTEP_CLEAR_FLUSH 953#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
954#define __HAVE_ARCH_PTEP_SET_WRPROTECT 954#define __HAVE_ARCH_PTEP_SET_WRPROTECT
955#define __HAVE_ARCH_PTE_SAME 955#define __HAVE_ARCH_PTE_SAME
956#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY 956#define __HAVE_ARCH_PAGE_TEST_DIRTY
957#define __HAVE_ARCH_PAGE_CLEAR_DIRTY
957#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG 958#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
958#include <asm-generic/pgtable.h> 959#include <asm-generic/pgtable.h>
959 960
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index 33b80ced4bc1..e0fcea8c64c3 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -57,6 +57,7 @@ struct cpuinfo_S390
57 57
58extern void s390_adjust_jiffies(void); 58extern void s390_adjust_jiffies(void);
59extern void print_cpu_info(struct cpuinfo_S390 *); 59extern void print_cpu_info(struct cpuinfo_S390 *);
60extern int get_cpu_capability(unsigned int *);
60 61
61/* Lazy FPU handling on uni-processor */ 62/* Lazy FPU handling on uni-processor */
62extern struct task_struct *last_task_used_math; 63extern struct task_struct *last_task_used_math;
@@ -196,6 +197,7 @@ extern unsigned long thread_saved_pc(struct task_struct *t);
196extern char *task_show_regs(struct task_struct *task, char *buffer); 197extern char *task_show_regs(struct task_struct *task, char *buffer);
197 198
198extern void show_registers(struct pt_regs *regs); 199extern void show_registers(struct pt_regs *regs);
200extern void show_code(struct pt_regs *regs);
199extern void show_trace(struct task_struct *task, unsigned long *sp); 201extern void show_trace(struct task_struct *task, unsigned long *sp);
200 202
201unsigned long get_wchan(struct task_struct *p); 203unsigned long get_wchan(struct task_struct *p);
diff --git a/include/asm-s390/sclp.h b/include/asm-s390/sclp.h
index 468b97018405..21ed64773210 100644
--- a/include/asm-s390/sclp.h
+++ b/include/asm-s390/sclp.h
@@ -9,6 +9,7 @@
9#define _ASM_S390_SCLP_H 9#define _ASM_S390_SCLP_H
10 10
11#include <linux/types.h> 11#include <linux/types.h>
12#include <asm/chpid.h>
12 13
13struct sccb_header { 14struct sccb_header {
14 u16 length; 15 u16 length;
@@ -33,7 +34,20 @@ struct sclp_readinfo_sccb {
33 u8 _reserved3[4096 - 112]; /* 112-4095 */ 34 u8 _reserved3[4096 - 112]; /* 112-4095 */
34} __attribute__((packed, aligned(4096))); 35} __attribute__((packed, aligned(4096)));
35 36
37#define SCLP_CHP_INFO_MASK_SIZE 32
38
39struct sclp_chp_info {
40 u8 recognized[SCLP_CHP_INFO_MASK_SIZE];
41 u8 standby[SCLP_CHP_INFO_MASK_SIZE];
42 u8 configured[SCLP_CHP_INFO_MASK_SIZE];
43};
44
36extern struct sclp_readinfo_sccb s390_readinfo_sccb; 45extern struct sclp_readinfo_sccb s390_readinfo_sccb;
37extern void sclp_readinfo_early(void); 46extern void sclp_readinfo_early(void);
47extern int sclp_sdias_blk_count(void);
48extern int sclp_sdias_copy(void *dest, int blk_num, int nr_blks);
49extern int sclp_chp_configure(struct chp_id chpid);
50extern int sclp_chp_deconfigure(struct chp_id chpid);
51extern int sclp_chp_read_info(struct sclp_chp_info *info);
38 52
39#endif /* _ASM_S390_SCLP_H */ 53#endif /* _ASM_S390_SCLP_H */
diff --git a/include/asm-s390/setup.h b/include/asm-s390/setup.h
index 44c7aee2bd34..a76a6b8fd887 100644
--- a/include/asm-s390/setup.h
+++ b/include/asm-s390/setup.h
@@ -40,6 +40,7 @@ struct mem_chunk {
40}; 40};
41 41
42extern struct mem_chunk memory_chunk[]; 42extern struct mem_chunk memory_chunk[];
43extern unsigned long real_memory_size;
43 44
44#ifdef CONFIG_S390_SWITCH_AMODE 45#ifdef CONFIG_S390_SWITCH_AMODE
45extern unsigned int switch_amode; 46extern unsigned int switch_amode;
@@ -77,6 +78,7 @@ extern unsigned long machine_flags;
77#endif /* __s390x__ */ 78#endif /* __s390x__ */
78 79
79#define MACHINE_HAS_SCLP (!MACHINE_IS_P390) 80#define MACHINE_HAS_SCLP (!MACHINE_IS_P390)
81#define ZFCPDUMP_HSA_SIZE (32UL<<20)
80 82
81/* 83/*
82 * Console mode. Override with conmode= 84 * Console mode. Override with conmode=
diff --git a/include/asm-s390/smp.h b/include/asm-s390/smp.h
index b957e4cda464..0a28e6d6ef40 100644
--- a/include/asm-s390/smp.h
+++ b/include/asm-s390/smp.h
@@ -54,9 +54,6 @@ extern int smp_call_function_on(void (*func) (void *info), void *info,
54 54
55#define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr) 55#define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr)
56 56
57extern int smp_get_cpu(cpumask_t cpu_map);
58extern void smp_put_cpu(int cpu);
59
60static inline __u16 hard_smp_processor_id(void) 57static inline __u16 hard_smp_processor_id(void)
61{ 58{
62 __u16 cpu_address; 59 __u16 cpu_address;
@@ -114,9 +111,8 @@ static inline void smp_send_stop(void)
114} 111}
115 112
116#define smp_cpu_not_running(cpu) 1 113#define smp_cpu_not_running(cpu) 1
117#define smp_get_cpu(cpu) ({ 0; })
118#define smp_put_cpu(cpu) ({ 0; })
119#define smp_setup_cpu_possible_map() do { } while (0) 114#define smp_setup_cpu_possible_map() do { } while (0)
120#endif 115#endif
121 116
117extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
122#endif 118#endif
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index 9cd0d0eaf523..96326594e55d 100644
--- a/include/linux/page-flags.h
+++ b/include/linux/page-flags.h
@@ -133,7 +133,7 @@
133static inline void SetPageUptodate(struct page *page) 133static inline void SetPageUptodate(struct page *page)
134{ 134{
135 if (!test_and_set_bit(PG_uptodate, &page->flags)) 135 if (!test_and_set_bit(PG_uptodate, &page->flags))
136 page_test_and_clear_dirty(page); 136 page_clear_dirty(page);
137} 137}
138#else 138#else
139#define SetPageUptodate(page) set_bit(PG_uptodate, &(page)->flags) 139#define SetPageUptodate(page) set_bit(PG_uptodate, &(page)->flags)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 02:19:23 -0500