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-rw-r--r--include/asm-arm26/cache.h3
-rw-r--r--include/asm-arm26/thread_info.h3
-rw-r--r--include/asm-ia64/pal.h2
-rw-r--r--include/asm-ia64/processor.h4
-rw-r--r--include/asm-ia64/sn/intr.h2
-rw-r--r--include/asm-ia64/sn/pcibr_provider.h48
-rw-r--r--include/asm-ia64/sn/pcibus_provider_defs.h14
-rw-r--r--include/asm-ia64/sn/pcidev.h4
-rw-r--r--include/asm-ia64/sn/pic.h204
-rw-r--r--include/asm-ia64/sn/shubio.h1620
-rw-r--r--include/asm-ia64/sn/sn_sal.h12
-rw-r--r--include/asm-ia64/sn/tioca.h82
-rw-r--r--include/asm-ia64/sn/tioca_provider.h56
-rw-r--r--include/asm-ia64/sn/tioce.h662
-rw-r--r--include/asm-ia64/sn/tioce_provider.h30
-rw-r--r--include/asm-ia64/sn/tiocp.h254
-rw-r--r--include/asm-ia64/sn/tiocx.h14
-rw-r--r--include/asm-sh/bus-sh.h1
-rw-r--r--include/asm-sh/clock.h61
-rw-r--r--include/asm-sh/cpu-sh3/dma.h31
-rw-r--r--include/asm-sh/cpu-sh4/dma.h52
-rw-r--r--include/asm-sh/cpu-sh4/freq.h2
-rw-r--r--include/asm-sh/dma-mapping.h25
-rw-r--r--include/asm-sh/dma.h14
-rw-r--r--include/asm-sh/freq.h11
-rw-r--r--include/asm-sh/io.h283
-rw-r--r--include/asm-sh/io_generic.h96
-rw-r--r--include/asm-sh/irq-sh7780.h349
-rw-r--r--include/asm-sh/irq.h143
-rw-r--r--include/asm-sh/kexec.h33
-rw-r--r--include/asm-sh/machvec.h66
-rw-r--r--include/asm-sh/timer.h42
-rw-r--r--include/asm-x86_64/ia32.h2
-rw-r--r--include/asm-x86_64/irq.h2
-rw-r--r--include/asm-x86_64/page.h7
-rw-r--r--include/asm-x86_64/processor.h9
-rw-r--r--include/asm-x86_64/system.h10
-rw-r--r--include/linux/fs.h3
-rw-r--r--include/linux/init.h12
-rw-r--r--include/linux/kexec.h1
40 files changed, 2446 insertions, 1823 deletions
diff --git a/include/asm-arm26/cache.h b/include/asm-arm26/cache.h
index f52ca1b808cd..8c3abcf728fe 100644
--- a/include/asm-arm26/cache.h
+++ b/include/asm-arm26/cache.h
@@ -4,7 +4,8 @@
4#ifndef __ASMARM_CACHE_H 4#ifndef __ASMARM_CACHE_H
5#define __ASMARM_CACHE_H 5#define __ASMARM_CACHE_H
6 6
7#define L1_CACHE_BYTES 32 7#define L1_CACHE_SHIFT 5
8#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
8#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 9#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
9#define SMP_CACHE_BYTES L1_CACHE_BYTES 10#define SMP_CACHE_BYTES L1_CACHE_BYTES
10 11
diff --git a/include/asm-arm26/thread_info.h b/include/asm-arm26/thread_info.h
index a65e58a0a767..9b367ebe515d 100644
--- a/include/asm-arm26/thread_info.h
+++ b/include/asm-arm26/thread_info.h
@@ -80,8 +80,7 @@ static inline struct thread_info *current_thread_info(void)
80 return (struct thread_info *)(sp & ~0x1fff); 80 return (struct thread_info *)(sp & ~0x1fff);
81} 81}
82 82
83/* FIXME - PAGE_SIZE < 32K */ 83#define THREAD_SIZE PAGE_SIZE
84#define THREAD_SIZE (8*32768) // FIXME - this needs attention (see kernel/fork.c which gets a nice div by zero if this is lower than 8*32768
85#define task_pt_regs(task) ((struct pt_regs *)(task_stack_page(task) + THREAD_SIZE - 8) - 1) 84#define task_pt_regs(task) ((struct pt_regs *)(task_stack_page(task) + THREAD_SIZE - 8) - 1)
86 85
87extern struct thread_info *alloc_thread_info(struct task_struct *task); 86extern struct thread_info *alloc_thread_info(struct task_struct *task);
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index e828377ad295..7708ec669a33 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -927,7 +927,7 @@ static inline s64
927ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) 927ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
928{ 928{
929 struct ia64_pal_retval iprv; 929 struct ia64_pal_retval iprv;
930 PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); 930 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
931 if (vector) 931 if (vector)
932 *vector = iprv.v0; 932 *vector = iprv.v0;
933 *progress = iprv.v1; 933 *progress = iprv.v1;
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 8c648bf72bbd..09b99029ac1a 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -25,8 +25,8 @@
25 * Limits for PMC and PMD are set to less than maximum architected values 25 * Limits for PMC and PMD are set to less than maximum architected values
26 * but should be sufficient for a while 26 * but should be sufficient for a while
27 */ 27 */
28#define IA64_NUM_PMC_REGS 32 28#define IA64_NUM_PMC_REGS 64
29#define IA64_NUM_PMD_REGS 32 29#define IA64_NUM_PMD_REGS 64
30 30
31#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000) 31#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
32#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000) 32#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
index e35074f526d9..a3431372c6e7 100644
--- a/include/asm-ia64/sn/intr.h
+++ b/include/asm-ia64/sn/intr.h
@@ -40,7 +40,7 @@ struct sn_irq_info {
40 int irq_cpuid; /* kernel logical cpuid */ 40 int irq_cpuid; /* kernel logical cpuid */
41 int irq_irq; /* the IRQ number */ 41 int irq_irq; /* the IRQ number */
42 int irq_int_bit; /* Bridge interrupt pin */ 42 int irq_int_bit; /* Bridge interrupt pin */
43 uint64_t irq_xtalkaddr; /* xtalkaddr IRQ is sent to */ 43 u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
44 int irq_bridge_type;/* pciio asic type (pciio.h) */ 44 int irq_bridge_type;/* pciio asic type (pciio.h) */
45 void *irq_bridge; /* bridge generating irq */ 45 void *irq_bridge; /* bridge generating irq */
46 void *irq_pciioinfo; /* associated pciio_info_t */ 46 void *irq_pciioinfo; /* associated pciio_info_t */
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
index 2b42d9ece26b..9334078b089a 100644
--- a/include/asm-ia64/sn/pcibr_provider.h
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -44,9 +44,9 @@
44#define PCI32_MAPPED_BASE 0x40000000 44#define PCI32_MAPPED_BASE 0x40000000
45#define PCI32_DIRECT_BASE 0x80000000 45#define PCI32_DIRECT_BASE 0x80000000
46 46
47#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ 47#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
48 (uint64_t)(x) >= PCI32_MAPPED_BASE) 48 (u64)(x) >= PCI32_MAPPED_BASE)
49#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) 49#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
50 50
51 51
52/* 52/*
@@ -63,7 +63,7 @@
63 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1)) 63 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
64 64
65#define MINIMAL_ATE_FLAG(addr, size) \ 65#define MINIMAL_ATE_FLAG(addr, size) \
66 (MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0) 66 (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
67 67
68/* bit 29 of the pci address is the SWAP bit */ 68/* bit 29 of the pci address is the SWAP bit */
69#define ATE_SWAPSHIFT 29 69#define ATE_SWAPSHIFT 29
@@ -90,27 +90,27 @@
90 * PMU resources. 90 * PMU resources.
91 */ 91 */
92struct ate_resource{ 92struct ate_resource{
93 uint64_t *ate; 93 u64 *ate;
94 uint64_t num_ate; 94 u64 num_ate;
95 uint64_t lowest_free_index; 95 u64 lowest_free_index;
96}; 96};
97 97
98struct pcibus_info { 98struct pcibus_info {
99 struct pcibus_bussoft pbi_buscommon; /* common header */ 99 struct pcibus_bussoft pbi_buscommon; /* common header */
100 uint32_t pbi_moduleid; 100 u32 pbi_moduleid;
101 short pbi_bridge_type; 101 short pbi_bridge_type;
102 short pbi_bridge_mode; 102 short pbi_bridge_mode;
103 103
104 struct ate_resource pbi_int_ate_resource; 104 struct ate_resource pbi_int_ate_resource;
105 uint64_t pbi_int_ate_size; 105 u64 pbi_int_ate_size;
106 106
107 uint64_t pbi_dir_xbase; 107 u64 pbi_dir_xbase;
108 char pbi_hub_xid; 108 char pbi_hub_xid;
109 109
110 uint64_t pbi_devreg[8]; 110 u64 pbi_devreg[8];
111 111
112 uint32_t pbi_valid_devices; 112 u32 pbi_valid_devices;
113 uint32_t pbi_enabled_devices; 113 u32 pbi_enabled_devices;
114 114
115 spinlock_t pbi_lock; 115 spinlock_t pbi_lock;
116}; 116};
@@ -136,22 +136,22 @@ extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
136/* 136/*
137 * prototypes for the bridge asic register access routines in pcibr_reg.c 137 * prototypes for the bridge asic register access routines in pcibr_reg.c
138 */ 138 */
139extern void pcireg_control_bit_clr(struct pcibus_info *, uint64_t); 139extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
140extern void pcireg_control_bit_set(struct pcibus_info *, uint64_t); 140extern void pcireg_control_bit_set(struct pcibus_info *, u64);
141extern uint64_t pcireg_tflush_get(struct pcibus_info *); 141extern u64 pcireg_tflush_get(struct pcibus_info *);
142extern uint64_t pcireg_intr_status_get(struct pcibus_info *); 142extern u64 pcireg_intr_status_get(struct pcibus_info *);
143extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t); 143extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
144extern void pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t); 144extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
145extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t); 145extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
146extern void pcireg_force_intr_set(struct pcibus_info *, int); 146extern void pcireg_force_intr_set(struct pcibus_info *, int);
147extern uint64_t pcireg_wrb_flush_get(struct pcibus_info *, int); 147extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
148extern void pcireg_int_ate_set(struct pcibus_info *, int, uint64_t); 148extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
149extern uint64_t * pcireg_int_ate_addr(struct pcibus_info *, int); 149extern u64 * pcireg_int_ate_addr(struct pcibus_info *, int);
150extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info); 150extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
151extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info); 151extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
152extern int pcibr_ate_alloc(struct pcibus_info *, int); 152extern int pcibr_ate_alloc(struct pcibus_info *, int);
153extern void pcibr_ate_free(struct pcibus_info *, int); 153extern void pcibr_ate_free(struct pcibus_info *, int);
154extern void ate_write(struct pcibus_info *, int, int, uint64_t); 154extern void ate_write(struct pcibus_info *, int, int, u64);
155extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device, 155extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
156 void *resp); 156 void *resp);
157extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device, 157extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
index ad0e8e8ae53f..ce3f6c328241 100644
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ b/include/asm-ia64/sn/pcibus_provider_defs.h
@@ -29,13 +29,13 @@
29 */ 29 */
30 30
31struct pcibus_bussoft { 31struct pcibus_bussoft {
32 uint32_t bs_asic_type; /* chipset type */ 32 u32 bs_asic_type; /* chipset type */
33 uint32_t bs_xid; /* xwidget id */ 33 u32 bs_xid; /* xwidget id */
34 uint32_t bs_persist_busnum; /* Persistent Bus Number */ 34 u32 bs_persist_busnum; /* Persistent Bus Number */
35 uint32_t bs_persist_segment; /* Segment Number */ 35 u32 bs_persist_segment; /* Segment Number */
36 uint64_t bs_legacy_io; /* legacy io pio addr */ 36 u64 bs_legacy_io; /* legacy io pio addr */
37 uint64_t bs_legacy_mem; /* legacy mem pio addr */ 37 u64 bs_legacy_mem; /* legacy mem pio addr */
38 uint64_t bs_base; /* widget base */ 38 u64 bs_base; /* widget base */
39 struct xwidget_info *bs_xwidget_info; 39 struct xwidget_info *bs_xwidget_info;
40}; 40};
41 41
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
index f65d222ca5e8..38cdffbc4c7b 100644
--- a/include/asm-ia64/sn/pcidev.h
+++ b/include/asm-ia64/sn/pcidev.h
@@ -55,8 +55,8 @@ struct sn_pci_controller {
55#define PCIIO_VENDOR_ID_NONE (-1) 55#define PCIIO_VENDOR_ID_NONE (-1)
56 56
57struct pcidev_info { 57struct pcidev_info {
58 uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */ 58 u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
59 uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */ 59 u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
60 60
61 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */ 61 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
62 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */ 62 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h
index 0de82e6b0893..5f9da5fd6e56 100644
--- a/include/asm-ia64/sn/pic.h
+++ b/include/asm-ia64/sn/pic.h
@@ -74,120 +74,120 @@ struct pic {
74 /* 0x000000-0x00FFFF -- Local Registers */ 74 /* 0x000000-0x00FFFF -- Local Registers */
75 75
76 /* 0x000000-0x000057 -- Standard Widget Configuration */ 76 /* 0x000000-0x000057 -- Standard Widget Configuration */
77 uint64_t p_wid_id; /* 0x000000 */ 77 u64 p_wid_id; /* 0x000000 */
78 uint64_t p_wid_stat; /* 0x000008 */ 78 u64 p_wid_stat; /* 0x000008 */
79 uint64_t p_wid_err_upper; /* 0x000010 */ 79 u64 p_wid_err_upper; /* 0x000010 */
80 uint64_t p_wid_err_lower; /* 0x000018 */ 80 u64 p_wid_err_lower; /* 0x000018 */
81 #define p_wid_err p_wid_err_lower 81 #define p_wid_err p_wid_err_lower
82 uint64_t p_wid_control; /* 0x000020 */ 82 u64 p_wid_control; /* 0x000020 */
83 uint64_t p_wid_req_timeout; /* 0x000028 */ 83 u64 p_wid_req_timeout; /* 0x000028 */
84 uint64_t p_wid_int_upper; /* 0x000030 */ 84 u64 p_wid_int_upper; /* 0x000030 */
85 uint64_t p_wid_int_lower; /* 0x000038 */ 85 u64 p_wid_int_lower; /* 0x000038 */
86 #define p_wid_int p_wid_int_lower 86 #define p_wid_int p_wid_int_lower
87 uint64_t p_wid_err_cmdword; /* 0x000040 */ 87 u64 p_wid_err_cmdword; /* 0x000040 */
88 uint64_t p_wid_llp; /* 0x000048 */ 88 u64 p_wid_llp; /* 0x000048 */
89 uint64_t p_wid_tflush; /* 0x000050 */ 89 u64 p_wid_tflush; /* 0x000050 */
90 90
91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ 91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
92 uint64_t p_wid_aux_err; /* 0x000058 */ 92 u64 p_wid_aux_err; /* 0x000058 */
93 uint64_t p_wid_resp_upper; /* 0x000060 */ 93 u64 p_wid_resp_upper; /* 0x000060 */
94 uint64_t p_wid_resp_lower; /* 0x000068 */ 94 u64 p_wid_resp_lower; /* 0x000068 */
95 #define p_wid_resp p_wid_resp_lower 95 #define p_wid_resp p_wid_resp_lower
96 uint64_t p_wid_tst_pin_ctrl; /* 0x000070 */ 96 u64 p_wid_tst_pin_ctrl; /* 0x000070 */
97 uint64_t p_wid_addr_lkerr; /* 0x000078 */ 97 u64 p_wid_addr_lkerr; /* 0x000078 */
98 98
99 /* 0x000080-0x00008F -- PMU & MAP */ 99 /* 0x000080-0x00008F -- PMU & MAP */
100 uint64_t p_dir_map; /* 0x000080 */ 100 u64 p_dir_map; /* 0x000080 */
101 uint64_t _pad_000088; /* 0x000088 */ 101 u64 _pad_000088; /* 0x000088 */
102 102
103 /* 0x000090-0x00009F -- SSRAM */ 103 /* 0x000090-0x00009F -- SSRAM */
104 uint64_t p_map_fault; /* 0x000090 */ 104 u64 p_map_fault; /* 0x000090 */
105 uint64_t _pad_000098; /* 0x000098 */ 105 u64 _pad_000098; /* 0x000098 */
106 106
107 /* 0x0000A0-0x0000AF -- Arbitration */ 107 /* 0x0000A0-0x0000AF -- Arbitration */
108 uint64_t p_arb; /* 0x0000A0 */ 108 u64 p_arb; /* 0x0000A0 */
109 uint64_t _pad_0000A8; /* 0x0000A8 */ 109 u64 _pad_0000A8; /* 0x0000A8 */
110 110
111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ 111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
112 uint64_t p_ate_parity_err; /* 0x0000B0 */ 112 u64 p_ate_parity_err; /* 0x0000B0 */
113 uint64_t _pad_0000B8; /* 0x0000B8 */ 113 u64 _pad_0000B8; /* 0x0000B8 */
114 114
115 /* 0x0000C0-0x0000FF -- PCI/GIO */ 115 /* 0x0000C0-0x0000FF -- PCI/GIO */
116 uint64_t p_bus_timeout; /* 0x0000C0 */ 116 u64 p_bus_timeout; /* 0x0000C0 */
117 uint64_t p_pci_cfg; /* 0x0000C8 */ 117 u64 p_pci_cfg; /* 0x0000C8 */
118 uint64_t p_pci_err_upper; /* 0x0000D0 */ 118 u64 p_pci_err_upper; /* 0x0000D0 */
119 uint64_t p_pci_err_lower; /* 0x0000D8 */ 119 u64 p_pci_err_lower; /* 0x0000D8 */
120 #define p_pci_err p_pci_err_lower 120 #define p_pci_err p_pci_err_lower
121 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ 121 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
122 122
123 /* 0x000100-0x0001FF -- Interrupt */ 123 /* 0x000100-0x0001FF -- Interrupt */
124 uint64_t p_int_status; /* 0x000100 */ 124 u64 p_int_status; /* 0x000100 */
125 uint64_t p_int_enable; /* 0x000108 */ 125 u64 p_int_enable; /* 0x000108 */
126 uint64_t p_int_rst_stat; /* 0x000110 */ 126 u64 p_int_rst_stat; /* 0x000110 */
127 uint64_t p_int_mode; /* 0x000118 */ 127 u64 p_int_mode; /* 0x000118 */
128 uint64_t p_int_device; /* 0x000120 */ 128 u64 p_int_device; /* 0x000120 */
129 uint64_t p_int_host_err; /* 0x000128 */ 129 u64 p_int_host_err; /* 0x000128 */
130 uint64_t p_int_addr[8]; /* 0x0001{30,,,68} */ 130 u64 p_int_addr[8]; /* 0x0001{30,,,68} */
131 uint64_t p_err_int_view; /* 0x000170 */ 131 u64 p_err_int_view; /* 0x000170 */
132 uint64_t p_mult_int; /* 0x000178 */ 132 u64 p_mult_int; /* 0x000178 */
133 uint64_t p_force_always[8]; /* 0x0001{80,,,B8} */ 133 u64 p_force_always[8]; /* 0x0001{80,,,B8} */
134 uint64_t p_force_pin[8]; /* 0x0001{C0,,,F8} */ 134 u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */
135 135
136 /* 0x000200-0x000298 -- Device */ 136 /* 0x000200-0x000298 -- Device */
137 uint64_t p_device[4]; /* 0x0002{00,,,18} */ 137 u64 p_device[4]; /* 0x0002{00,,,18} */
138 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */ 138 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
139 uint64_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */ 139 u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */
140 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */ 140 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
141 uint64_t p_rrb_map[2]; /* 0x0002{80,,,88} */ 141 u64 p_rrb_map[2]; /* 0x0002{80,,,88} */
142 #define p_even_resp p_rrb_map[0] /* 0x000280 */ 142 #define p_even_resp p_rrb_map[0] /* 0x000280 */
143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */ 143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */
144 uint64_t p_resp_status; /* 0x000290 */ 144 u64 p_resp_status; /* 0x000290 */
145 uint64_t p_resp_clear; /* 0x000298 */ 145 u64 p_resp_clear; /* 0x000298 */
146 146
147 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ 147 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
148 148
149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ 149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
150 struct { 150 struct {
151 uint64_t upper; /* 0x0003{00,,,F0} */ 151 u64 upper; /* 0x0003{00,,,F0} */
152 uint64_t lower; /* 0x0003{08,,,F8} */ 152 u64 lower; /* 0x0003{08,,,F8} */
153 } p_buf_addr_match[16]; 153 } p_buf_addr_match[16];
154 154
155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ 155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
156 struct { 156 struct {
157 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */ 157 u64 flush_w_touch; /* 0x000{400,,,5C0} */
158 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */ 158 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
159 uint64_t inflight; /* 0x000{410,,,5D0} */ 159 u64 inflight; /* 0x000{410,,,5D0} */
160 uint64_t prefetch; /* 0x000{418,,,5D8} */ 160 u64 prefetch; /* 0x000{418,,,5D8} */
161 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */ 161 u64 total_pci_retry; /* 0x000{420,,,5E0} */
162 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */ 162 u64 max_pci_retry; /* 0x000{428,,,5E8} */
163 uint64_t max_latency; /* 0x000{430,,,5F0} */ 163 u64 max_latency; /* 0x000{430,,,5F0} */
164 uint64_t clear_all; /* 0x000{438,,,5F8} */ 164 u64 clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8]; 165 } p_buf_count[8];
166 166
167 167
168 /* 0x000600-0x0009FF -- PCI/X registers */ 168 /* 0x000600-0x0009FF -- PCI/X registers */
169 uint64_t p_pcix_bus_err_addr; /* 0x000600 */ 169 u64 p_pcix_bus_err_addr; /* 0x000600 */
170 uint64_t p_pcix_bus_err_attr; /* 0x000608 */ 170 u64 p_pcix_bus_err_attr; /* 0x000608 */
171 uint64_t p_pcix_bus_err_data; /* 0x000610 */ 171 u64 p_pcix_bus_err_data; /* 0x000610 */
172 uint64_t p_pcix_pio_split_addr; /* 0x000618 */ 172 u64 p_pcix_pio_split_addr; /* 0x000618 */
173 uint64_t p_pcix_pio_split_attr; /* 0x000620 */ 173 u64 p_pcix_pio_split_attr; /* 0x000620 */
174 uint64_t p_pcix_dma_req_err_attr; /* 0x000628 */ 174 u64 p_pcix_dma_req_err_attr; /* 0x000628 */
175 uint64_t p_pcix_dma_req_err_addr; /* 0x000630 */ 175 u64 p_pcix_dma_req_err_addr; /* 0x000630 */
176 uint64_t p_pcix_timeout; /* 0x000638 */ 176 u64 p_pcix_timeout; /* 0x000638 */
177 177
178 uint64_t _pad_000640[120]; /* 0x000{640,,,9F8} */ 178 u64 _pad_000640[120]; /* 0x000{640,,,9F8} */
179 179
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ 180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
181 struct { 181 struct {
182 uint64_t p_buf_addr; /* 0x000{A00,,,AF0} */ 182 u64 p_buf_addr; /* 0x000{A00,,,AF0} */
183 uint64_t p_buf_attr; /* 0X000{A08,,,AF8} */ 183 u64 p_buf_attr; /* 0X000{A08,,,AF8} */
184 } p_pcix_read_buf_64[16]; 184 } p_pcix_read_buf_64[16];
185 185
186 struct { 186 struct {
187 uint64_t p_buf_addr; /* 0x000{B00,,,BE0} */ 187 u64 p_buf_addr; /* 0x000{B00,,,BE0} */
188 uint64_t p_buf_attr; /* 0x000{B08,,,BE8} */ 188 u64 p_buf_attr; /* 0x000{B08,,,BE8} */
189 uint64_t p_buf_valid; /* 0x000{B10,,,BF0} */ 189 u64 p_buf_valid; /* 0x000{B10,,,BF0} */
190 uint64_t __pad1; /* 0x000{B18,,,BF8} */ 190 u64 __pad1; /* 0x000{B18,,,BF8} */
191 } p_pcix_write_buf_64[8]; 191 } p_pcix_write_buf_64[8];
192 192
193 /* End of Local Registers -- Start of Address Map space */ 193 /* End of Local Registers -- Start of Address Map space */
@@ -195,45 +195,45 @@ struct pic {
195 char _pad_000c00[0x010000 - 0x000c00]; 195 char _pad_000c00[0x010000 - 0x000c00];
196 196
197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */ 197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
198 uint64_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */ 198 u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */
199 199
200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */ 200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
201 uint64_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */ 201 u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
202 202
203 char _pad_014000[0x18000 - 0x014000]; 203 char _pad_014000[0x18000 - 0x014000];
204 204
205 /* 0x18000-0x197F8 -- PIC Write Request Ram */ 205 /* 0x18000-0x197F8 -- PIC Write Request Ram */
206 uint64_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ 206 u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
207 uint64_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ 207 u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
208 uint64_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ 208 u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
209 209
210 char _pad_019800[0x20000 - 0x019800]; 210 char _pad_019800[0x20000 - 0x019800];
211 211
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ 212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
213 union { 213 union {
214 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ 214 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
215 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ 215 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
216 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ 216 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
217 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ 217 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
218 union { 218 union {
219 uint8_t c[0x100 / 1]; 219 u8 c[0x100 / 1];
220 uint16_t s[0x100 / 2]; 220 u16 s[0x100 / 2];
221 uint32_t l[0x100 / 4]; 221 u32 l[0x100 / 4];
222 uint64_t d[0x100 / 8]; 222 u64 d[0x100 / 8];
223 } f[8]; 223 } f[8];
224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ 224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
225 225
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ 226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
227 union { 227 union {
228 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ 228 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
229 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ 229 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
230 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ 230 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
231 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ 231 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
232 union { 232 union {
233 uint8_t c[0x100 / 1]; 233 u8 c[0x100 / 1];
234 uint16_t s[0x100 / 2]; 234 u16 s[0x100 / 2];
235 uint32_t l[0x100 / 4]; 235 u32 l[0x100 / 4];
236 uint64_t d[0x100 / 8]; 236 u64 d[0x100 / 8];
237 } f[8]; 237 } f[8];
238 } p_type1_cfg; /* 0x028000-0x029000 */ 238 } p_type1_cfg; /* 0x028000-0x029000 */
239 239
@@ -241,20 +241,20 @@ struct pic {
241 241
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ 242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
243 union { 243 union {
244 uint8_t c[8 / 1]; 244 u8 c[8 / 1];
245 uint16_t s[8 / 2]; 245 u16 s[8 / 2];
246 uint32_t l[8 / 4]; 246 u32 l[8 / 4];
247 uint64_t d[8 / 8]; 247 u64 d[8 / 8];
248 } p_pci_iack; /* 0x030000-0x030007 */ 248 } p_pci_iack; /* 0x030000-0x030007 */
249 249
250 char _pad_030007[0x040000-0x030008]; 250 char _pad_030007[0x040000-0x030008];
251 251
252 /* 0x040000-0x030007 -- PCIX Special Cycle */ 252 /* 0x040000-0x030007 -- PCIX Special Cycle */
253 union { 253 union {
254 uint8_t c[8 / 1]; 254 u8 c[8 / 1];
255 uint16_t s[8 / 2]; 255 u16 s[8 / 2];
256 uint32_t l[8 / 4]; 256 u32 l[8 / 4];
257 uint64_t d[8 / 8]; 257 u64 d[8 / 8];
258 } p_pcix_cycle; /* 0x040000-0x040007 */ 258 } p_pcix_cycle; /* 0x040000-0x040007 */
259}; 259};
260 260
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h
index 831b72111fdc..22a6f18a5313 100644
--- a/include/asm-ia64/sn/shubio.h
+++ b/include/asm-ia64/sn/shubio.h
@@ -227,13 +227,13 @@
227 ************************************************************************/ 227 ************************************************************************/
228 228
229typedef union ii_wid_u { 229typedef union ii_wid_u {
230 uint64_t ii_wid_regval; 230 u64 ii_wid_regval;
231 struct { 231 struct {
232 uint64_t w_rsvd_1:1; 232 u64 w_rsvd_1:1;
233 uint64_t w_mfg_num:11; 233 u64 w_mfg_num:11;
234 uint64_t w_part_num:16; 234 u64 w_part_num:16;
235 uint64_t w_rev_num:4; 235 u64 w_rev_num:4;
236 uint64_t w_rsvd:32; 236 u64 w_rsvd:32;
237 } ii_wid_fld_s; 237 } ii_wid_fld_s;
238} ii_wid_u_t; 238} ii_wid_u_t;
239 239
@@ -246,18 +246,18 @@ typedef union ii_wid_u {
246 ************************************************************************/ 246 ************************************************************************/
247 247
248typedef union ii_wstat_u { 248typedef union ii_wstat_u {
249 uint64_t ii_wstat_regval; 249 u64 ii_wstat_regval;
250 struct { 250 struct {
251 uint64_t w_pending:4; 251 u64 w_pending:4;
252 uint64_t w_xt_crd_to:1; 252 u64 w_xt_crd_to:1;
253 uint64_t w_xt_tail_to:1; 253 u64 w_xt_tail_to:1;
254 uint64_t w_rsvd_3:3; 254 u64 w_rsvd_3:3;
255 uint64_t w_tx_mx_rty:1; 255 u64 w_tx_mx_rty:1;
256 uint64_t w_rsvd_2:6; 256 u64 w_rsvd_2:6;
257 uint64_t w_llp_tx_cnt:8; 257 u64 w_llp_tx_cnt:8;
258 uint64_t w_rsvd_1:8; 258 u64 w_rsvd_1:8;
259 uint64_t w_crazy:1; 259 u64 w_crazy:1;
260 uint64_t w_rsvd:31; 260 u64 w_rsvd:31;
261 } ii_wstat_fld_s; 261 } ii_wstat_fld_s;
262} ii_wstat_u_t; 262} ii_wstat_u_t;
263 263
@@ -269,16 +269,16 @@ typedef union ii_wstat_u {
269 ************************************************************************/ 269 ************************************************************************/
270 270
271typedef union ii_wcr_u { 271typedef union ii_wcr_u {
272 uint64_t ii_wcr_regval; 272 u64 ii_wcr_regval;
273 struct { 273 struct {
274 uint64_t w_wid:4; 274 u64 w_wid:4;
275 uint64_t w_tag:1; 275 u64 w_tag:1;
276 uint64_t w_rsvd_1:8; 276 u64 w_rsvd_1:8;
277 uint64_t w_dst_crd:3; 277 u64 w_dst_crd:3;
278 uint64_t w_f_bad_pkt:1; 278 u64 w_f_bad_pkt:1;
279 uint64_t w_dir_con:1; 279 u64 w_dir_con:1;
280 uint64_t w_e_thresh:5; 280 u64 w_e_thresh:5;
281 uint64_t w_rsvd:41; 281 u64 w_rsvd:41;
282 } ii_wcr_fld_s; 282 } ii_wcr_fld_s;
283} ii_wcr_u_t; 283} ii_wcr_u_t;
284 284
@@ -310,9 +310,9 @@ typedef union ii_wcr_u {
310 ************************************************************************/ 310 ************************************************************************/
311 311
312typedef union ii_ilapr_u { 312typedef union ii_ilapr_u {
313 uint64_t ii_ilapr_regval; 313 u64 ii_ilapr_regval;
314 struct { 314 struct {
315 uint64_t i_region:64; 315 u64 i_region:64;
316 } ii_ilapr_fld_s; 316 } ii_ilapr_fld_s;
317} ii_ilapr_u_t; 317} ii_ilapr_u_t;
318 318
@@ -330,9 +330,9 @@ typedef union ii_ilapr_u {
330 ************************************************************************/ 330 ************************************************************************/
331 331
332typedef union ii_ilapo_u { 332typedef union ii_ilapo_u {
333 uint64_t ii_ilapo_regval; 333 u64 ii_ilapo_regval;
334 struct { 334 struct {
335 uint64_t i_io_ovrride:64; 335 u64 i_io_ovrride:64;
336 } ii_ilapo_fld_s; 336 } ii_ilapo_fld_s;
337} ii_ilapo_u_t; 337} ii_ilapo_u_t;
338 338
@@ -344,12 +344,12 @@ typedef union ii_ilapo_u {
344 ************************************************************************/ 344 ************************************************************************/
345 345
346typedef union ii_iowa_u { 346typedef union ii_iowa_u {
347 uint64_t ii_iowa_regval; 347 u64 ii_iowa_regval;
348 struct { 348 struct {
349 uint64_t i_w0_oac:1; 349 u64 i_w0_oac:1;
350 uint64_t i_rsvd_1:7; 350 u64 i_rsvd_1:7;
351 uint64_t i_wx_oac:8; 351 u64 i_wx_oac:8;
352 uint64_t i_rsvd:48; 352 u64 i_rsvd:48;
353 } ii_iowa_fld_s; 353 } ii_iowa_fld_s;
354} ii_iowa_u_t; 354} ii_iowa_u_t;
355 355
@@ -363,12 +363,12 @@ typedef union ii_iowa_u {
363 ************************************************************************/ 363 ************************************************************************/
364 364
365typedef union ii_iiwa_u { 365typedef union ii_iiwa_u {
366 uint64_t ii_iiwa_regval; 366 u64 ii_iiwa_regval;
367 struct { 367 struct {
368 uint64_t i_w0_iac:1; 368 u64 i_w0_iac:1;
369 uint64_t i_rsvd_1:7; 369 u64 i_rsvd_1:7;
370 uint64_t i_wx_iac:8; 370 u64 i_wx_iac:8;
371 uint64_t i_rsvd:48; 371 u64 i_rsvd:48;
372 } ii_iiwa_fld_s; 372 } ii_iiwa_fld_s;
373} ii_iiwa_u_t; 373} ii_iiwa_u_t;
374 374
@@ -392,16 +392,16 @@ typedef union ii_iiwa_u {
392 ************************************************************************/ 392 ************************************************************************/
393 393
394typedef union ii_iidem_u { 394typedef union ii_iidem_u {
395 uint64_t ii_iidem_regval; 395 u64 ii_iidem_regval;
396 struct { 396 struct {
397 uint64_t i_w8_dxs:8; 397 u64 i_w8_dxs:8;
398 uint64_t i_w9_dxs:8; 398 u64 i_w9_dxs:8;
399 uint64_t i_wa_dxs:8; 399 u64 i_wa_dxs:8;
400 uint64_t i_wb_dxs:8; 400 u64 i_wb_dxs:8;
401 uint64_t i_wc_dxs:8; 401 u64 i_wc_dxs:8;
402 uint64_t i_wd_dxs:8; 402 u64 i_wd_dxs:8;
403 uint64_t i_we_dxs:8; 403 u64 i_we_dxs:8;
404 uint64_t i_wf_dxs:8; 404 u64 i_wf_dxs:8;
405 } ii_iidem_fld_s; 405 } ii_iidem_fld_s;
406} ii_iidem_u_t; 406} ii_iidem_u_t;
407 407
@@ -413,22 +413,22 @@ typedef union ii_iidem_u {
413 ************************************************************************/ 413 ************************************************************************/
414 414
415typedef union ii_ilcsr_u { 415typedef union ii_ilcsr_u {
416 uint64_t ii_ilcsr_regval; 416 u64 ii_ilcsr_regval;
417 struct { 417 struct {
418 uint64_t i_nullto:6; 418 u64 i_nullto:6;
419 uint64_t i_rsvd_4:2; 419 u64 i_rsvd_4:2;
420 uint64_t i_wrmrst:1; 420 u64 i_wrmrst:1;
421 uint64_t i_rsvd_3:1; 421 u64 i_rsvd_3:1;
422 uint64_t i_llp_en:1; 422 u64 i_llp_en:1;
423 uint64_t i_bm8:1; 423 u64 i_bm8:1;
424 uint64_t i_llp_stat:2; 424 u64 i_llp_stat:2;
425 uint64_t i_remote_power:1; 425 u64 i_remote_power:1;
426 uint64_t i_rsvd_2:1; 426 u64 i_rsvd_2:1;
427 uint64_t i_maxrtry:10; 427 u64 i_maxrtry:10;
428 uint64_t i_d_avail_sel:2; 428 u64 i_d_avail_sel:2;
429 uint64_t i_rsvd_1:4; 429 u64 i_rsvd_1:4;
430 uint64_t i_maxbrst:10; 430 u64 i_maxbrst:10;
431 uint64_t i_rsvd:22; 431 u64 i_rsvd:22;
432 432
433 } ii_ilcsr_fld_s; 433 } ii_ilcsr_fld_s;
434} ii_ilcsr_u_t; 434} ii_ilcsr_u_t;
@@ -441,11 +441,11 @@ typedef union ii_ilcsr_u {
441 ************************************************************************/ 441 ************************************************************************/
442 442
443typedef union ii_illr_u { 443typedef union ii_illr_u {
444 uint64_t ii_illr_regval; 444 u64 ii_illr_regval;
445 struct { 445 struct {
446 uint64_t i_sn_cnt:16; 446 u64 i_sn_cnt:16;
447 uint64_t i_cb_cnt:16; 447 u64 i_cb_cnt:16;
448 uint64_t i_rsvd:32; 448 u64 i_rsvd:32;
449 } ii_illr_fld_s; 449 } ii_illr_fld_s;
450} ii_illr_u_t; 450} ii_illr_u_t;
451 451
@@ -464,19 +464,19 @@ typedef union ii_illr_u {
464 ************************************************************************/ 464 ************************************************************************/
465 465
466typedef union ii_iidsr_u { 466typedef union ii_iidsr_u {
467 uint64_t ii_iidsr_regval; 467 u64 ii_iidsr_regval;
468 struct { 468 struct {
469 uint64_t i_level:8; 469 u64 i_level:8;
470 uint64_t i_pi_id:1; 470 u64 i_pi_id:1;
471 uint64_t i_node:11; 471 u64 i_node:11;
472 uint64_t i_rsvd_3:4; 472 u64 i_rsvd_3:4;
473 uint64_t i_enable:1; 473 u64 i_enable:1;
474 uint64_t i_rsvd_2:3; 474 u64 i_rsvd_2:3;
475 uint64_t i_int_sent:2; 475 u64 i_int_sent:2;
476 uint64_t i_rsvd_1:2; 476 u64 i_rsvd_1:2;
477 uint64_t i_pi0_forward_int:1; 477 u64 i_pi0_forward_int:1;
478 uint64_t i_pi1_forward_int:1; 478 u64 i_pi1_forward_int:1;
479 uint64_t i_rsvd:30; 479 u64 i_rsvd:30;
480 } ii_iidsr_fld_s; 480 } ii_iidsr_fld_s;
481} ii_iidsr_u_t; 481} ii_iidsr_u_t;
482 482
@@ -492,13 +492,13 @@ typedef union ii_iidsr_u {
492 ************************************************************************/ 492 ************************************************************************/
493 493
494typedef union ii_igfx0_u { 494typedef union ii_igfx0_u {
495 uint64_t ii_igfx0_regval; 495 u64 ii_igfx0_regval;
496 struct { 496 struct {
497 uint64_t i_w_num:4; 497 u64 i_w_num:4;
498 uint64_t i_pi_id:1; 498 u64 i_pi_id:1;
499 uint64_t i_n_num:12; 499 u64 i_n_num:12;
500 uint64_t i_p_num:1; 500 u64 i_p_num:1;
501 uint64_t i_rsvd:46; 501 u64 i_rsvd:46;
502 } ii_igfx0_fld_s; 502 } ii_igfx0_fld_s;
503} ii_igfx0_u_t; 503} ii_igfx0_u_t;
504 504
@@ -514,13 +514,13 @@ typedef union ii_igfx0_u {
514 ************************************************************************/ 514 ************************************************************************/
515 515
516typedef union ii_igfx1_u { 516typedef union ii_igfx1_u {
517 uint64_t ii_igfx1_regval; 517 u64 ii_igfx1_regval;
518 struct { 518 struct {
519 uint64_t i_w_num:4; 519 u64 i_w_num:4;
520 uint64_t i_pi_id:1; 520 u64 i_pi_id:1;
521 uint64_t i_n_num:12; 521 u64 i_n_num:12;
522 uint64_t i_p_num:1; 522 u64 i_p_num:1;
523 uint64_t i_rsvd:46; 523 u64 i_rsvd:46;
524 } ii_igfx1_fld_s; 524 } ii_igfx1_fld_s;
525} ii_igfx1_u_t; 525} ii_igfx1_u_t;
526 526
@@ -532,9 +532,9 @@ typedef union ii_igfx1_u {
532 ************************************************************************/ 532 ************************************************************************/
533 533
534typedef union ii_iscr0_u { 534typedef union ii_iscr0_u {
535 uint64_t ii_iscr0_regval; 535 u64 ii_iscr0_regval;
536 struct { 536 struct {
537 uint64_t i_scratch:64; 537 u64 i_scratch:64;
538 } ii_iscr0_fld_s; 538 } ii_iscr0_fld_s;
539} ii_iscr0_u_t; 539} ii_iscr0_u_t;
540 540
@@ -546,9 +546,9 @@ typedef union ii_iscr0_u {
546 ************************************************************************/ 546 ************************************************************************/
547 547
548typedef union ii_iscr1_u { 548typedef union ii_iscr1_u {
549 uint64_t ii_iscr1_regval; 549 u64 ii_iscr1_regval;
550 struct { 550 struct {
551 uint64_t i_scratch:64; 551 u64 i_scratch:64;
552 } ii_iscr1_fld_s; 552 } ii_iscr1_fld_s;
553} ii_iscr1_u_t; 553} ii_iscr1_u_t;
554 554
@@ -580,13 +580,13 @@ typedef union ii_iscr1_u {
580 ************************************************************************/ 580 ************************************************************************/
581 581
582typedef union ii_itte1_u { 582typedef union ii_itte1_u {
583 uint64_t ii_itte1_regval; 583 u64 ii_itte1_regval;
584 struct { 584 struct {
585 uint64_t i_offset:5; 585 u64 i_offset:5;
586 uint64_t i_rsvd_1:3; 586 u64 i_rsvd_1:3;
587 uint64_t i_w_num:4; 587 u64 i_w_num:4;
588 uint64_t i_iosp:1; 588 u64 i_iosp:1;
589 uint64_t i_rsvd:51; 589 u64 i_rsvd:51;
590 } ii_itte1_fld_s; 590 } ii_itte1_fld_s;
591} ii_itte1_u_t; 591} ii_itte1_u_t;
592 592
@@ -618,13 +618,13 @@ typedef union ii_itte1_u {
618 ************************************************************************/ 618 ************************************************************************/
619 619
620typedef union ii_itte2_u { 620typedef union ii_itte2_u {
621 uint64_t ii_itte2_regval; 621 u64 ii_itte2_regval;
622 struct { 622 struct {
623 uint64_t i_offset:5; 623 u64 i_offset:5;
624 uint64_t i_rsvd_1:3; 624 u64 i_rsvd_1:3;
625 uint64_t i_w_num:4; 625 u64 i_w_num:4;
626 uint64_t i_iosp:1; 626 u64 i_iosp:1;
627 uint64_t i_rsvd:51; 627 u64 i_rsvd:51;
628 } ii_itte2_fld_s; 628 } ii_itte2_fld_s;
629} ii_itte2_u_t; 629} ii_itte2_u_t;
630 630
@@ -656,13 +656,13 @@ typedef union ii_itte2_u {
656 ************************************************************************/ 656 ************************************************************************/
657 657
658typedef union ii_itte3_u { 658typedef union ii_itte3_u {
659 uint64_t ii_itte3_regval; 659 u64 ii_itte3_regval;
660 struct { 660 struct {
661 uint64_t i_offset:5; 661 u64 i_offset:5;
662 uint64_t i_rsvd_1:3; 662 u64 i_rsvd_1:3;
663 uint64_t i_w_num:4; 663 u64 i_w_num:4;
664 uint64_t i_iosp:1; 664 u64 i_iosp:1;
665 uint64_t i_rsvd:51; 665 u64 i_rsvd:51;
666 } ii_itte3_fld_s; 666 } ii_itte3_fld_s;
667} ii_itte3_u_t; 667} ii_itte3_u_t;
668 668
@@ -694,13 +694,13 @@ typedef union ii_itte3_u {
694 ************************************************************************/ 694 ************************************************************************/
695 695
696typedef union ii_itte4_u { 696typedef union ii_itte4_u {
697 uint64_t ii_itte4_regval; 697 u64 ii_itte4_regval;
698 struct { 698 struct {
699 uint64_t i_offset:5; 699 u64 i_offset:5;
700 uint64_t i_rsvd_1:3; 700 u64 i_rsvd_1:3;
701 uint64_t i_w_num:4; 701 u64 i_w_num:4;
702 uint64_t i_iosp:1; 702 u64 i_iosp:1;
703 uint64_t i_rsvd:51; 703 u64 i_rsvd:51;
704 } ii_itte4_fld_s; 704 } ii_itte4_fld_s;
705} ii_itte4_u_t; 705} ii_itte4_u_t;
706 706
@@ -732,13 +732,13 @@ typedef union ii_itte4_u {
732 ************************************************************************/ 732 ************************************************************************/
733 733
734typedef union ii_itte5_u { 734typedef union ii_itte5_u {
735 uint64_t ii_itte5_regval; 735 u64 ii_itte5_regval;
736 struct { 736 struct {
737 uint64_t i_offset:5; 737 u64 i_offset:5;
738 uint64_t i_rsvd_1:3; 738 u64 i_rsvd_1:3;
739 uint64_t i_w_num:4; 739 u64 i_w_num:4;
740 uint64_t i_iosp:1; 740 u64 i_iosp:1;
741 uint64_t i_rsvd:51; 741 u64 i_rsvd:51;
742 } ii_itte5_fld_s; 742 } ii_itte5_fld_s;
743} ii_itte5_u_t; 743} ii_itte5_u_t;
744 744
@@ -770,13 +770,13 @@ typedef union ii_itte5_u {
770 ************************************************************************/ 770 ************************************************************************/
771 771
772typedef union ii_itte6_u { 772typedef union ii_itte6_u {
773 uint64_t ii_itte6_regval; 773 u64 ii_itte6_regval;
774 struct { 774 struct {
775 uint64_t i_offset:5; 775 u64 i_offset:5;
776 uint64_t i_rsvd_1:3; 776 u64 i_rsvd_1:3;
777 uint64_t i_w_num:4; 777 u64 i_w_num:4;
778 uint64_t i_iosp:1; 778 u64 i_iosp:1;
779 uint64_t i_rsvd:51; 779 u64 i_rsvd:51;
780 } ii_itte6_fld_s; 780 } ii_itte6_fld_s;
781} ii_itte6_u_t; 781} ii_itte6_u_t;
782 782
@@ -808,13 +808,13 @@ typedef union ii_itte6_u {
808 ************************************************************************/ 808 ************************************************************************/
809 809
810typedef union ii_itte7_u { 810typedef union ii_itte7_u {
811 uint64_t ii_itte7_regval; 811 u64 ii_itte7_regval;
812 struct { 812 struct {
813 uint64_t i_offset:5; 813 u64 i_offset:5;
814 uint64_t i_rsvd_1:3; 814 u64 i_rsvd_1:3;
815 uint64_t i_w_num:4; 815 u64 i_w_num:4;
816 uint64_t i_iosp:1; 816 u64 i_iosp:1;
817 uint64_t i_rsvd:51; 817 u64 i_rsvd:51;
818 } ii_itte7_fld_s; 818 } ii_itte7_fld_s;
819} ii_itte7_u_t; 819} ii_itte7_u_t;
820 820
@@ -843,22 +843,22 @@ typedef union ii_itte7_u {
843 ************************************************************************/ 843 ************************************************************************/
844 844
845typedef union ii_iprb0_u { 845typedef union ii_iprb0_u {
846 uint64_t ii_iprb0_regval; 846 u64 ii_iprb0_regval;
847 struct { 847 struct {
848 uint64_t i_c:8; 848 u64 i_c:8;
849 uint64_t i_na:14; 849 u64 i_na:14;
850 uint64_t i_rsvd_2:2; 850 u64 i_rsvd_2:2;
851 uint64_t i_nb:14; 851 u64 i_nb:14;
852 uint64_t i_rsvd_1:2; 852 u64 i_rsvd_1:2;
853 uint64_t i_m:2; 853 u64 i_m:2;
854 uint64_t i_f:1; 854 u64 i_f:1;
855 uint64_t i_of_cnt:5; 855 u64 i_of_cnt:5;
856 uint64_t i_error:1; 856 u64 i_error:1;
857 uint64_t i_rd_to:1; 857 u64 i_rd_to:1;
858 uint64_t i_spur_wr:1; 858 u64 i_spur_wr:1;
859 uint64_t i_spur_rd:1; 859 u64 i_spur_rd:1;
860 uint64_t i_rsvd:11; 860 u64 i_rsvd:11;
861 uint64_t i_mult_err:1; 861 u64 i_mult_err:1;
862 } ii_iprb0_fld_s; 862 } ii_iprb0_fld_s;
863} ii_iprb0_u_t; 863} ii_iprb0_u_t;
864 864
@@ -887,22 +887,22 @@ typedef union ii_iprb0_u {
887 ************************************************************************/ 887 ************************************************************************/
888 888
889typedef union ii_iprb8_u { 889typedef union ii_iprb8_u {
890 uint64_t ii_iprb8_regval; 890 u64 ii_iprb8_regval;
891 struct { 891 struct {
892 uint64_t i_c:8; 892 u64 i_c:8;
893 uint64_t i_na:14; 893 u64 i_na:14;
894 uint64_t i_rsvd_2:2; 894 u64 i_rsvd_2:2;
895 uint64_t i_nb:14; 895 u64 i_nb:14;
896 uint64_t i_rsvd_1:2; 896 u64 i_rsvd_1:2;
897 uint64_t i_m:2; 897 u64 i_m:2;
898 uint64_t i_f:1; 898 u64 i_f:1;
899 uint64_t i_of_cnt:5; 899 u64 i_of_cnt:5;
900 uint64_t i_error:1; 900 u64 i_error:1;
901 uint64_t i_rd_to:1; 901 u64 i_rd_to:1;
902 uint64_t i_spur_wr:1; 902 u64 i_spur_wr:1;
903 uint64_t i_spur_rd:1; 903 u64 i_spur_rd:1;
904 uint64_t i_rsvd:11; 904 u64 i_rsvd:11;
905 uint64_t i_mult_err:1; 905 u64 i_mult_err:1;
906 } ii_iprb8_fld_s; 906 } ii_iprb8_fld_s;
907} ii_iprb8_u_t; 907} ii_iprb8_u_t;
908 908
@@ -931,22 +931,22 @@ typedef union ii_iprb8_u {
931 ************************************************************************/ 931 ************************************************************************/
932 932
933typedef union ii_iprb9_u { 933typedef union ii_iprb9_u {
934 uint64_t ii_iprb9_regval; 934 u64 ii_iprb9_regval;
935 struct { 935 struct {
936 uint64_t i_c:8; 936 u64 i_c:8;
937 uint64_t i_na:14; 937 u64 i_na:14;
938 uint64_t i_rsvd_2:2; 938 u64 i_rsvd_2:2;
939 uint64_t i_nb:14; 939 u64 i_nb:14;
940 uint64_t i_rsvd_1:2; 940 u64 i_rsvd_1:2;
941 uint64_t i_m:2; 941 u64 i_m:2;
942 uint64_t i_f:1; 942 u64 i_f:1;
943 uint64_t i_of_cnt:5; 943 u64 i_of_cnt:5;
944 uint64_t i_error:1; 944 u64 i_error:1;
945 uint64_t i_rd_to:1; 945 u64 i_rd_to:1;
946 uint64_t i_spur_wr:1; 946 u64 i_spur_wr:1;
947 uint64_t i_spur_rd:1; 947 u64 i_spur_rd:1;
948 uint64_t i_rsvd:11; 948 u64 i_rsvd:11;
949 uint64_t i_mult_err:1; 949 u64 i_mult_err:1;
950 } ii_iprb9_fld_s; 950 } ii_iprb9_fld_s;
951} ii_iprb9_u_t; 951} ii_iprb9_u_t;
952 952
@@ -975,22 +975,22 @@ typedef union ii_iprb9_u {
975 ************************************************************************/ 975 ************************************************************************/
976 976
977typedef union ii_iprba_u { 977typedef union ii_iprba_u {
978 uint64_t ii_iprba_regval; 978 u64 ii_iprba_regval;
979 struct { 979 struct {
980 uint64_t i_c:8; 980 u64 i_c:8;
981 uint64_t i_na:14; 981 u64 i_na:14;
982 uint64_t i_rsvd_2:2; 982 u64 i_rsvd_2:2;
983 uint64_t i_nb:14; 983 u64 i_nb:14;
984 uint64_t i_rsvd_1:2; 984 u64 i_rsvd_1:2;
985 uint64_t i_m:2; 985 u64 i_m:2;
986 uint64_t i_f:1; 986 u64 i_f:1;
987 uint64_t i_of_cnt:5; 987 u64 i_of_cnt:5;
988 uint64_t i_error:1; 988 u64 i_error:1;
989 uint64_t i_rd_to:1; 989 u64 i_rd_to:1;
990 uint64_t i_spur_wr:1; 990 u64 i_spur_wr:1;
991 uint64_t i_spur_rd:1; 991 u64 i_spur_rd:1;
992 uint64_t i_rsvd:11; 992 u64 i_rsvd:11;
993 uint64_t i_mult_err:1; 993 u64 i_mult_err:1;
994 } ii_iprba_fld_s; 994 } ii_iprba_fld_s;
995} ii_iprba_u_t; 995} ii_iprba_u_t;
996 996
@@ -1019,22 +1019,22 @@ typedef union ii_iprba_u {
1019 ************************************************************************/ 1019 ************************************************************************/
1020 1020
1021typedef union ii_iprbb_u { 1021typedef union ii_iprbb_u {
1022 uint64_t ii_iprbb_regval; 1022 u64 ii_iprbb_regval;
1023 struct { 1023 struct {
1024 uint64_t i_c:8; 1024 u64 i_c:8;
1025 uint64_t i_na:14; 1025 u64 i_na:14;
1026 uint64_t i_rsvd_2:2; 1026 u64 i_rsvd_2:2;
1027 uint64_t i_nb:14; 1027 u64 i_nb:14;
1028 uint64_t i_rsvd_1:2; 1028 u64 i_rsvd_1:2;
1029 uint64_t i_m:2; 1029 u64 i_m:2;
1030 uint64_t i_f:1; 1030 u64 i_f:1;
1031 uint64_t i_of_cnt:5; 1031 u64 i_of_cnt:5;
1032 uint64_t i_error:1; 1032 u64 i_error:1;
1033 uint64_t i_rd_to:1; 1033 u64 i_rd_to:1;
1034 uint64_t i_spur_wr:1; 1034 u64 i_spur_wr:1;
1035 uint64_t i_spur_rd:1; 1035 u64 i_spur_rd:1;
1036 uint64_t i_rsvd:11; 1036 u64 i_rsvd:11;
1037 uint64_t i_mult_err:1; 1037 u64 i_mult_err:1;
1038 } ii_iprbb_fld_s; 1038 } ii_iprbb_fld_s;
1039} ii_iprbb_u_t; 1039} ii_iprbb_u_t;
1040 1040
@@ -1063,22 +1063,22 @@ typedef union ii_iprbb_u {
1063 ************************************************************************/ 1063 ************************************************************************/
1064 1064
1065typedef union ii_iprbc_u { 1065typedef union ii_iprbc_u {
1066 uint64_t ii_iprbc_regval; 1066 u64 ii_iprbc_regval;
1067 struct { 1067 struct {
1068 uint64_t i_c:8; 1068 u64 i_c:8;
1069 uint64_t i_na:14; 1069 u64 i_na:14;
1070 uint64_t i_rsvd_2:2; 1070 u64 i_rsvd_2:2;
1071 uint64_t i_nb:14; 1071 u64 i_nb:14;
1072 uint64_t i_rsvd_1:2; 1072 u64 i_rsvd_1:2;
1073 uint64_t i_m:2; 1073 u64 i_m:2;
1074 uint64_t i_f:1; 1074 u64 i_f:1;
1075 uint64_t i_of_cnt:5; 1075 u64 i_of_cnt:5;
1076 uint64_t i_error:1; 1076 u64 i_error:1;
1077 uint64_t i_rd_to:1; 1077 u64 i_rd_to:1;
1078 uint64_t i_spur_wr:1; 1078 u64 i_spur_wr:1;
1079 uint64_t i_spur_rd:1; 1079 u64 i_spur_rd:1;
1080 uint64_t i_rsvd:11; 1080 u64 i_rsvd:11;
1081 uint64_t i_mult_err:1; 1081 u64 i_mult_err:1;
1082 } ii_iprbc_fld_s; 1082 } ii_iprbc_fld_s;
1083} ii_iprbc_u_t; 1083} ii_iprbc_u_t;
1084 1084
@@ -1107,22 +1107,22 @@ typedef union ii_iprbc_u {
1107 ************************************************************************/ 1107 ************************************************************************/
1108 1108
1109typedef union ii_iprbd_u { 1109typedef union ii_iprbd_u {
1110 uint64_t ii_iprbd_regval; 1110 u64 ii_iprbd_regval;
1111 struct { 1111 struct {
1112 uint64_t i_c:8; 1112 u64 i_c:8;
1113 uint64_t i_na:14; 1113 u64 i_na:14;
1114 uint64_t i_rsvd_2:2; 1114 u64 i_rsvd_2:2;
1115 uint64_t i_nb:14; 1115 u64 i_nb:14;
1116 uint64_t i_rsvd_1:2; 1116 u64 i_rsvd_1:2;
1117 uint64_t i_m:2; 1117 u64 i_m:2;
1118 uint64_t i_f:1; 1118 u64 i_f:1;
1119 uint64_t i_of_cnt:5; 1119 u64 i_of_cnt:5;
1120 uint64_t i_error:1; 1120 u64 i_error:1;
1121 uint64_t i_rd_to:1; 1121 u64 i_rd_to:1;
1122 uint64_t i_spur_wr:1; 1122 u64 i_spur_wr:1;
1123 uint64_t i_spur_rd:1; 1123 u64 i_spur_rd:1;
1124 uint64_t i_rsvd:11; 1124 u64 i_rsvd:11;
1125 uint64_t i_mult_err:1; 1125 u64 i_mult_err:1;
1126 } ii_iprbd_fld_s; 1126 } ii_iprbd_fld_s;
1127} ii_iprbd_u_t; 1127} ii_iprbd_u_t;
1128 1128
@@ -1151,22 +1151,22 @@ typedef union ii_iprbd_u {
1151 ************************************************************************/ 1151 ************************************************************************/
1152 1152
1153typedef union ii_iprbe_u { 1153typedef union ii_iprbe_u {
1154 uint64_t ii_iprbe_regval; 1154 u64 ii_iprbe_regval;
1155 struct { 1155 struct {
1156 uint64_t i_c:8; 1156 u64 i_c:8;
1157 uint64_t i_na:14; 1157 u64 i_na:14;
1158 uint64_t i_rsvd_2:2; 1158 u64 i_rsvd_2:2;
1159 uint64_t i_nb:14; 1159 u64 i_nb:14;
1160 uint64_t i_rsvd_1:2; 1160 u64 i_rsvd_1:2;
1161 uint64_t i_m:2; 1161 u64 i_m:2;
1162 uint64_t i_f:1; 1162 u64 i_f:1;
1163 uint64_t i_of_cnt:5; 1163 u64 i_of_cnt:5;
1164 uint64_t i_error:1; 1164 u64 i_error:1;
1165 uint64_t i_rd_to:1; 1165 u64 i_rd_to:1;
1166 uint64_t i_spur_wr:1; 1166 u64 i_spur_wr:1;
1167 uint64_t i_spur_rd:1; 1167 u64 i_spur_rd:1;
1168 uint64_t i_rsvd:11; 1168 u64 i_rsvd:11;
1169 uint64_t i_mult_err:1; 1169 u64 i_mult_err:1;
1170 } ii_iprbe_fld_s; 1170 } ii_iprbe_fld_s;
1171} ii_iprbe_u_t; 1171} ii_iprbe_u_t;
1172 1172
@@ -1195,22 +1195,22 @@ typedef union ii_iprbe_u {
1195 ************************************************************************/ 1195 ************************************************************************/
1196 1196
1197typedef union ii_iprbf_u { 1197typedef union ii_iprbf_u {
1198 uint64_t ii_iprbf_regval; 1198 u64 ii_iprbf_regval;
1199 struct { 1199 struct {
1200 uint64_t i_c:8; 1200 u64 i_c:8;
1201 uint64_t i_na:14; 1201 u64 i_na:14;
1202 uint64_t i_rsvd_2:2; 1202 u64 i_rsvd_2:2;
1203 uint64_t i_nb:14; 1203 u64 i_nb:14;
1204 uint64_t i_rsvd_1:2; 1204 u64 i_rsvd_1:2;
1205 uint64_t i_m:2; 1205 u64 i_m:2;
1206 uint64_t i_f:1; 1206 u64 i_f:1;
1207 uint64_t i_of_cnt:5; 1207 u64 i_of_cnt:5;
1208 uint64_t i_error:1; 1208 u64 i_error:1;
1209 uint64_t i_rd_to:1; 1209 u64 i_rd_to:1;
1210 uint64_t i_spur_wr:1; 1210 u64 i_spur_wr:1;
1211 uint64_t i_spur_rd:1; 1211 u64 i_spur_rd:1;
1212 uint64_t i_rsvd:11; 1212 u64 i_rsvd:11;
1213 uint64_t i_mult_err:1; 1213 u64 i_mult_err:1;
1214 } ii_iprbe_fld_s; 1214 } ii_iprbe_fld_s;
1215} ii_iprbf_u_t; 1215} ii_iprbf_u_t;
1216 1216
@@ -1232,10 +1232,10 @@ typedef union ii_iprbf_u {
1232 ************************************************************************/ 1232 ************************************************************************/
1233 1233
1234typedef union ii_ixcc_u { 1234typedef union ii_ixcc_u {
1235 uint64_t ii_ixcc_regval; 1235 u64 ii_ixcc_regval;
1236 struct { 1236 struct {
1237 uint64_t i_time_out:26; 1237 u64 i_time_out:26;
1238 uint64_t i_rsvd:38; 1238 u64 i_rsvd:38;
1239 } ii_ixcc_fld_s; 1239 } ii_ixcc_fld_s;
1240} ii_ixcc_u_t; 1240} ii_ixcc_u_t;
1241 1241
@@ -1256,16 +1256,16 @@ typedef union ii_ixcc_u {
1256 ************************************************************************/ 1256 ************************************************************************/
1257 1257
1258typedef union ii_imem_u { 1258typedef union ii_imem_u {
1259 uint64_t ii_imem_regval; 1259 u64 ii_imem_regval;
1260 struct { 1260 struct {
1261 uint64_t i_w0_esd:1; 1261 u64 i_w0_esd:1;
1262 uint64_t i_rsvd_3:3; 1262 u64 i_rsvd_3:3;
1263 uint64_t i_b0_esd:1; 1263 u64 i_b0_esd:1;
1264 uint64_t i_rsvd_2:3; 1264 u64 i_rsvd_2:3;
1265 uint64_t i_b1_esd:1; 1265 u64 i_b1_esd:1;
1266 uint64_t i_rsvd_1:3; 1266 u64 i_rsvd_1:3;
1267 uint64_t i_clr_precise:1; 1267 u64 i_clr_precise:1;
1268 uint64_t i_rsvd:51; 1268 u64 i_rsvd:51;
1269 } ii_imem_fld_s; 1269 } ii_imem_fld_s;
1270} ii_imem_u_t; 1270} ii_imem_u_t;
1271 1271
@@ -1294,13 +1294,13 @@ typedef union ii_imem_u {
1294 ************************************************************************/ 1294 ************************************************************************/
1295 1295
1296typedef union ii_ixtt_u { 1296typedef union ii_ixtt_u {
1297 uint64_t ii_ixtt_regval; 1297 u64 ii_ixtt_regval;
1298 struct { 1298 struct {
1299 uint64_t i_tail_to:26; 1299 u64 i_tail_to:26;
1300 uint64_t i_rsvd_1:6; 1300 u64 i_rsvd_1:6;
1301 uint64_t i_rrsp_ps:23; 1301 u64 i_rrsp_ps:23;
1302 uint64_t i_rrsp_to:5; 1302 u64 i_rrsp_to:5;
1303 uint64_t i_rsvd:4; 1303 u64 i_rsvd:4;
1304 } ii_ixtt_fld_s; 1304 } ii_ixtt_fld_s;
1305} ii_ixtt_u_t; 1305} ii_ixtt_u_t;
1306 1306
@@ -1316,37 +1316,37 @@ typedef union ii_ixtt_u {
1316 ************************************************************************/ 1316 ************************************************************************/
1317 1317
1318typedef union ii_ieclr_u { 1318typedef union ii_ieclr_u {
1319 uint64_t ii_ieclr_regval; 1319 u64 ii_ieclr_regval;
1320 struct { 1320 struct {
1321 uint64_t i_e_prb_0:1; 1321 u64 i_e_prb_0:1;
1322 uint64_t i_rsvd:7; 1322 u64 i_rsvd:7;
1323 uint64_t i_e_prb_8:1; 1323 u64 i_e_prb_8:1;
1324 uint64_t i_e_prb_9:1; 1324 u64 i_e_prb_9:1;
1325 uint64_t i_e_prb_a:1; 1325 u64 i_e_prb_a:1;
1326 uint64_t i_e_prb_b:1; 1326 u64 i_e_prb_b:1;
1327 uint64_t i_e_prb_c:1; 1327 u64 i_e_prb_c:1;
1328 uint64_t i_e_prb_d:1; 1328 u64 i_e_prb_d:1;
1329 uint64_t i_e_prb_e:1; 1329 u64 i_e_prb_e:1;
1330 uint64_t i_e_prb_f:1; 1330 u64 i_e_prb_f:1;
1331 uint64_t i_e_crazy:1; 1331 u64 i_e_crazy:1;
1332 uint64_t i_e_bte_0:1; 1332 u64 i_e_bte_0:1;
1333 uint64_t i_e_bte_1:1; 1333 u64 i_e_bte_1:1;
1334 uint64_t i_reserved_1:10; 1334 u64 i_reserved_1:10;
1335 uint64_t i_spur_rd_hdr:1; 1335 u64 i_spur_rd_hdr:1;
1336 uint64_t i_cam_intr_to:1; 1336 u64 i_cam_intr_to:1;
1337 uint64_t i_cam_overflow:1; 1337 u64 i_cam_overflow:1;
1338 uint64_t i_cam_read_miss:1; 1338 u64 i_cam_read_miss:1;
1339 uint64_t i_ioq_rep_underflow:1; 1339 u64 i_ioq_rep_underflow:1;
1340 uint64_t i_ioq_req_underflow:1; 1340 u64 i_ioq_req_underflow:1;
1341 uint64_t i_ioq_rep_overflow:1; 1341 u64 i_ioq_rep_overflow:1;
1342 uint64_t i_ioq_req_overflow:1; 1342 u64 i_ioq_req_overflow:1;
1343 uint64_t i_iiq_rep_overflow:1; 1343 u64 i_iiq_rep_overflow:1;
1344 uint64_t i_iiq_req_overflow:1; 1344 u64 i_iiq_req_overflow:1;
1345 uint64_t i_ii_xn_rep_cred_overflow:1; 1345 u64 i_ii_xn_rep_cred_overflow:1;
1346 uint64_t i_ii_xn_req_cred_overflow:1; 1346 u64 i_ii_xn_req_cred_overflow:1;
1347 uint64_t i_ii_xn_invalid_cmd:1; 1347 u64 i_ii_xn_invalid_cmd:1;
1348 uint64_t i_xn_ii_invalid_cmd:1; 1348 u64 i_xn_ii_invalid_cmd:1;
1349 uint64_t i_reserved_2:21; 1349 u64 i_reserved_2:21;
1350 } ii_ieclr_fld_s; 1350 } ii_ieclr_fld_s;
1351} ii_ieclr_u_t; 1351} ii_ieclr_u_t;
1352 1352
@@ -1360,12 +1360,12 @@ typedef union ii_ieclr_u {
1360 ************************************************************************/ 1360 ************************************************************************/
1361 1361
1362typedef union ii_ibcr_u { 1362typedef union ii_ibcr_u {
1363 uint64_t ii_ibcr_regval; 1363 u64 ii_ibcr_regval;
1364 struct { 1364 struct {
1365 uint64_t i_count:4; 1365 u64 i_count:4;
1366 uint64_t i_rsvd_1:4; 1366 u64 i_rsvd_1:4;
1367 uint64_t i_soft_reset:1; 1367 u64 i_soft_reset:1;
1368 uint64_t i_rsvd:55; 1368 u64 i_rsvd:55;
1369 } ii_ibcr_fld_s; 1369 } ii_ibcr_fld_s;
1370} ii_ibcr_u_t; 1370} ii_ibcr_u_t;
1371 1371
@@ -1399,22 +1399,22 @@ typedef union ii_ibcr_u {
1399 ************************************************************************/ 1399 ************************************************************************/
1400 1400
1401typedef union ii_ixsm_u { 1401typedef union ii_ixsm_u {
1402 uint64_t ii_ixsm_regval; 1402 u64 ii_ixsm_regval;
1403 struct { 1403 struct {
1404 uint64_t i_byte_en:32; 1404 u64 i_byte_en:32;
1405 uint64_t i_reserved:1; 1405 u64 i_reserved:1;
1406 uint64_t i_tag:3; 1406 u64 i_tag:3;
1407 uint64_t i_alt_pactyp:4; 1407 u64 i_alt_pactyp:4;
1408 uint64_t i_bo:1; 1408 u64 i_bo:1;
1409 uint64_t i_error:1; 1409 u64 i_error:1;
1410 uint64_t i_vbpm:1; 1410 u64 i_vbpm:1;
1411 uint64_t i_gbr:1; 1411 u64 i_gbr:1;
1412 uint64_t i_ds:2; 1412 u64 i_ds:2;
1413 uint64_t i_ct:1; 1413 u64 i_ct:1;
1414 uint64_t i_tnum:5; 1414 u64 i_tnum:5;
1415 uint64_t i_pactyp:4; 1415 u64 i_pactyp:4;
1416 uint64_t i_sidn:4; 1416 u64 i_sidn:4;
1417 uint64_t i_didn:4; 1417 u64 i_didn:4;
1418 } ii_ixsm_fld_s; 1418 } ii_ixsm_fld_s;
1419} ii_ixsm_u_t; 1419} ii_ixsm_u_t;
1420 1420
@@ -1426,11 +1426,11 @@ typedef union ii_ixsm_u {
1426 ************************************************************************/ 1426 ************************************************************************/
1427 1427
1428typedef union ii_ixss_u { 1428typedef union ii_ixss_u {
1429 uint64_t ii_ixss_regval; 1429 u64 ii_ixss_regval;
1430 struct { 1430 struct {
1431 uint64_t i_sideband:8; 1431 u64 i_sideband:8;
1432 uint64_t i_rsvd:55; 1432 u64 i_rsvd:55;
1433 uint64_t i_valid:1; 1433 u64 i_valid:1;
1434 } ii_ixss_fld_s; 1434 } ii_ixss_fld_s;
1435} ii_ixss_u_t; 1435} ii_ixss_u_t;
1436 1436
@@ -1447,17 +1447,17 @@ typedef union ii_ixss_u {
1447 ************************************************************************/ 1447 ************************************************************************/
1448 1448
1449typedef union ii_ilct_u { 1449typedef union ii_ilct_u {
1450 uint64_t ii_ilct_regval; 1450 u64 ii_ilct_regval;
1451 struct { 1451 struct {
1452 uint64_t i_test_seed:20; 1452 u64 i_test_seed:20;
1453 uint64_t i_test_mask:8; 1453 u64 i_test_mask:8;
1454 uint64_t i_test_data:20; 1454 u64 i_test_data:20;
1455 uint64_t i_test_valid:1; 1455 u64 i_test_valid:1;
1456 uint64_t i_test_cberr:1; 1456 u64 i_test_cberr:1;
1457 uint64_t i_test_flit:3; 1457 u64 i_test_flit:3;
1458 uint64_t i_test_clear:1; 1458 u64 i_test_clear:1;
1459 uint64_t i_test_err_capture:1; 1459 u64 i_test_err_capture:1;
1460 uint64_t i_rsvd:9; 1460 u64 i_rsvd:9;
1461 } ii_ilct_fld_s; 1461 } ii_ilct_fld_s;
1462} ii_ilct_u_t; 1462} ii_ilct_u_t;
1463 1463
@@ -1482,20 +1482,20 @@ typedef union ii_ilct_u {
1482 ************************************************************************/ 1482 ************************************************************************/
1483 1483
1484typedef union ii_iieph1_u { 1484typedef union ii_iieph1_u {
1485 uint64_t ii_iieph1_regval; 1485 u64 ii_iieph1_regval;
1486 struct { 1486 struct {
1487 uint64_t i_command:7; 1487 u64 i_command:7;
1488 uint64_t i_rsvd_5:1; 1488 u64 i_rsvd_5:1;
1489 uint64_t i_suppl:14; 1489 u64 i_suppl:14;
1490 uint64_t i_rsvd_4:1; 1490 u64 i_rsvd_4:1;
1491 uint64_t i_source:14; 1491 u64 i_source:14;
1492 uint64_t i_rsvd_3:1; 1492 u64 i_rsvd_3:1;
1493 uint64_t i_err_type:4; 1493 u64 i_err_type:4;
1494 uint64_t i_rsvd_2:4; 1494 u64 i_rsvd_2:4;
1495 uint64_t i_overrun:1; 1495 u64 i_overrun:1;
1496 uint64_t i_rsvd_1:3; 1496 u64 i_rsvd_1:3;
1497 uint64_t i_valid:1; 1497 u64 i_valid:1;
1498 uint64_t i_rsvd:13; 1498 u64 i_rsvd:13;
1499 } ii_iieph1_fld_s; 1499 } ii_iieph1_fld_s;
1500} ii_iieph1_u_t; 1500} ii_iieph1_u_t;
1501 1501
@@ -1511,13 +1511,13 @@ typedef union ii_iieph1_u {
1511 ************************************************************************/ 1511 ************************************************************************/
1512 1512
1513typedef union ii_iieph2_u { 1513typedef union ii_iieph2_u {
1514 uint64_t ii_iieph2_regval; 1514 u64 ii_iieph2_regval;
1515 struct { 1515 struct {
1516 uint64_t i_rsvd_0:3; 1516 u64 i_rsvd_0:3;
1517 uint64_t i_address:47; 1517 u64 i_address:47;
1518 uint64_t i_rsvd_1:10; 1518 u64 i_rsvd_1:10;
1519 uint64_t i_tail:1; 1519 u64 i_tail:1;
1520 uint64_t i_rsvd:3; 1520 u64 i_rsvd:3;
1521 } ii_iieph2_fld_s; 1521 } ii_iieph2_fld_s;
1522} ii_iieph2_u_t; 1522} ii_iieph2_u_t;
1523 1523
@@ -1532,9 +1532,9 @@ typedef union ii_iieph2_u {
1532 ************************************************************************/ 1532 ************************************************************************/
1533 1533
1534typedef union ii_islapr_u { 1534typedef union ii_islapr_u {
1535 uint64_t ii_islapr_regval; 1535 u64 ii_islapr_regval;
1536 struct { 1536 struct {
1537 uint64_t i_region:64; 1537 u64 i_region:64;
1538 } ii_islapr_fld_s; 1538 } ii_islapr_fld_s;
1539} ii_islapr_u_t; 1539} ii_islapr_u_t;
1540 1540
@@ -1547,10 +1547,10 @@ typedef union ii_islapr_u {
1547 ************************************************************************/ 1547 ************************************************************************/
1548 1548
1549typedef union ii_islapo_u { 1549typedef union ii_islapo_u {
1550 uint64_t ii_islapo_regval; 1550 u64 ii_islapo_regval;
1551 struct { 1551 struct {
1552 uint64_t i_io_sbx_ovrride:56; 1552 u64 i_io_sbx_ovrride:56;
1553 uint64_t i_rsvd:8; 1553 u64 i_rsvd:8;
1554 } ii_islapo_fld_s; 1554 } ii_islapo_fld_s;
1555} ii_islapo_u_t; 1555} ii_islapo_u_t;
1556 1556
@@ -1563,14 +1563,14 @@ typedef union ii_islapo_u {
1563 ************************************************************************/ 1563 ************************************************************************/
1564 1564
1565typedef union ii_iwi_u { 1565typedef union ii_iwi_u {
1566 uint64_t ii_iwi_regval; 1566 u64 ii_iwi_regval;
1567 struct { 1567 struct {
1568 uint64_t i_prescale:24; 1568 u64 i_prescale:24;
1569 uint64_t i_rsvd:8; 1569 u64 i_rsvd:8;
1570 uint64_t i_timeout:8; 1570 u64 i_timeout:8;
1571 uint64_t i_rsvd1:8; 1571 u64 i_rsvd1:8;
1572 uint64_t i_intrpt_retry_period:8; 1572 u64 i_intrpt_retry_period:8;
1573 uint64_t i_rsvd2:8; 1573 u64 i_rsvd2:8;
1574 } ii_iwi_fld_s; 1574 } ii_iwi_fld_s;
1575} ii_iwi_u_t; 1575} ii_iwi_u_t;
1576 1576
@@ -1582,26 +1582,26 @@ typedef union ii_iwi_u {
1582 ************************************************************************/ 1582 ************************************************************************/
1583 1583
1584typedef union ii_iwel_u { 1584typedef union ii_iwel_u {
1585 uint64_t ii_iwel_regval; 1585 u64 ii_iwel_regval;
1586 struct { 1586 struct {
1587 uint64_t i_intr_timed_out:1; 1587 u64 i_intr_timed_out:1;
1588 uint64_t i_rsvd:7; 1588 u64 i_rsvd:7;
1589 uint64_t i_cam_overflow:1; 1589 u64 i_cam_overflow:1;
1590 uint64_t i_cam_read_miss:1; 1590 u64 i_cam_read_miss:1;
1591 uint64_t i_rsvd1:2; 1591 u64 i_rsvd1:2;
1592 uint64_t i_ioq_rep_underflow:1; 1592 u64 i_ioq_rep_underflow:1;
1593 uint64_t i_ioq_req_underflow:1; 1593 u64 i_ioq_req_underflow:1;
1594 uint64_t i_ioq_rep_overflow:1; 1594 u64 i_ioq_rep_overflow:1;
1595 uint64_t i_ioq_req_overflow:1; 1595 u64 i_ioq_req_overflow:1;
1596 uint64_t i_iiq_rep_overflow:1; 1596 u64 i_iiq_rep_overflow:1;
1597 uint64_t i_iiq_req_overflow:1; 1597 u64 i_iiq_req_overflow:1;
1598 uint64_t i_rsvd2:6; 1598 u64 i_rsvd2:6;
1599 uint64_t i_ii_xn_rep_cred_over_under:1; 1599 u64 i_ii_xn_rep_cred_over_under:1;
1600 uint64_t i_ii_xn_req_cred_over_under:1; 1600 u64 i_ii_xn_req_cred_over_under:1;
1601 uint64_t i_rsvd3:6; 1601 u64 i_rsvd3:6;
1602 uint64_t i_ii_xn_invalid_cmd:1; 1602 u64 i_ii_xn_invalid_cmd:1;
1603 uint64_t i_xn_ii_invalid_cmd:1; 1603 u64 i_xn_ii_invalid_cmd:1;
1604 uint64_t i_rsvd4:30; 1604 u64 i_rsvd4:30;
1605 } ii_iwel_fld_s; 1605 } ii_iwel_fld_s;
1606} ii_iwel_u_t; 1606} ii_iwel_u_t;
1607 1607
@@ -1612,22 +1612,22 @@ typedef union ii_iwel_u {
1612 ************************************************************************/ 1612 ************************************************************************/
1613 1613
1614typedef union ii_iwc_u { 1614typedef union ii_iwc_u {
1615 uint64_t ii_iwc_regval; 1615 u64 ii_iwc_regval;
1616 struct { 1616 struct {
1617 uint64_t i_dma_byte_swap:1; 1617 u64 i_dma_byte_swap:1;
1618 uint64_t i_rsvd:3; 1618 u64 i_rsvd:3;
1619 uint64_t i_cam_read_lines_reset:1; 1619 u64 i_cam_read_lines_reset:1;
1620 uint64_t i_rsvd1:3; 1620 u64 i_rsvd1:3;
1621 uint64_t i_ii_xn_cred_over_under_log:1; 1621 u64 i_ii_xn_cred_over_under_log:1;
1622 uint64_t i_rsvd2:19; 1622 u64 i_rsvd2:19;
1623 uint64_t i_xn_rep_iq_depth:5; 1623 u64 i_xn_rep_iq_depth:5;
1624 uint64_t i_rsvd3:3; 1624 u64 i_rsvd3:3;
1625 uint64_t i_xn_req_iq_depth:5; 1625 u64 i_xn_req_iq_depth:5;
1626 uint64_t i_rsvd4:3; 1626 u64 i_rsvd4:3;
1627 uint64_t i_iiq_depth:6; 1627 u64 i_iiq_depth:6;
1628 uint64_t i_rsvd5:12; 1628 u64 i_rsvd5:12;
1629 uint64_t i_force_rep_cred:1; 1629 u64 i_force_rep_cred:1;
1630 uint64_t i_force_req_cred:1; 1630 u64 i_force_req_cred:1;
1631 } ii_iwc_fld_s; 1631 } ii_iwc_fld_s;
1632} ii_iwc_u_t; 1632} ii_iwc_u_t;
1633 1633
@@ -1638,12 +1638,12 @@ typedef union ii_iwc_u {
1638 ************************************************************************/ 1638 ************************************************************************/
1639 1639
1640typedef union ii_iws_u { 1640typedef union ii_iws_u {
1641 uint64_t ii_iws_regval; 1641 u64 ii_iws_regval;
1642 struct { 1642 struct {
1643 uint64_t i_xn_rep_iq_credits:5; 1643 u64 i_xn_rep_iq_credits:5;
1644 uint64_t i_rsvd:3; 1644 u64 i_rsvd:3;
1645 uint64_t i_xn_req_iq_credits:5; 1645 u64 i_xn_req_iq_credits:5;
1646 uint64_t i_rsvd1:51; 1646 u64 i_rsvd1:51;
1647 } ii_iws_fld_s; 1647 } ii_iws_fld_s;
1648} ii_iws_u_t; 1648} ii_iws_u_t;
1649 1649
@@ -1654,26 +1654,26 @@ typedef union ii_iws_u {
1654 ************************************************************************/ 1654 ************************************************************************/
1655 1655
1656typedef union ii_iweim_u { 1656typedef union ii_iweim_u {
1657 uint64_t ii_iweim_regval; 1657 u64 ii_iweim_regval;
1658 struct { 1658 struct {
1659 uint64_t i_intr_timed_out:1; 1659 u64 i_intr_timed_out:1;
1660 uint64_t i_rsvd:7; 1660 u64 i_rsvd:7;
1661 uint64_t i_cam_overflow:1; 1661 u64 i_cam_overflow:1;
1662 uint64_t i_cam_read_miss:1; 1662 u64 i_cam_read_miss:1;
1663 uint64_t i_rsvd1:2; 1663 u64 i_rsvd1:2;
1664 uint64_t i_ioq_rep_underflow:1; 1664 u64 i_ioq_rep_underflow:1;
1665 uint64_t i_ioq_req_underflow:1; 1665 u64 i_ioq_req_underflow:1;
1666 uint64_t i_ioq_rep_overflow:1; 1666 u64 i_ioq_rep_overflow:1;
1667 uint64_t i_ioq_req_overflow:1; 1667 u64 i_ioq_req_overflow:1;
1668 uint64_t i_iiq_rep_overflow:1; 1668 u64 i_iiq_rep_overflow:1;
1669 uint64_t i_iiq_req_overflow:1; 1669 u64 i_iiq_req_overflow:1;
1670 uint64_t i_rsvd2:6; 1670 u64 i_rsvd2:6;
1671 uint64_t i_ii_xn_rep_cred_overflow:1; 1671 u64 i_ii_xn_rep_cred_overflow:1;
1672 uint64_t i_ii_xn_req_cred_overflow:1; 1672 u64 i_ii_xn_req_cred_overflow:1;
1673 uint64_t i_rsvd3:6; 1673 u64 i_rsvd3:6;
1674 uint64_t i_ii_xn_invalid_cmd:1; 1674 u64 i_ii_xn_invalid_cmd:1;
1675 uint64_t i_xn_ii_invalid_cmd:1; 1675 u64 i_xn_ii_invalid_cmd:1;
1676 uint64_t i_rsvd4:30; 1676 u64 i_rsvd4:30;
1677 } ii_iweim_fld_s; 1677 } ii_iweim_fld_s;
1678} ii_iweim_u_t; 1678} ii_iweim_u_t;
1679 1679
@@ -1688,13 +1688,13 @@ typedef union ii_iweim_u {
1688 ************************************************************************/ 1688 ************************************************************************/
1689 1689
1690typedef union ii_ipca_u { 1690typedef union ii_ipca_u {
1691 uint64_t ii_ipca_regval; 1691 u64 ii_ipca_regval;
1692 struct { 1692 struct {
1693 uint64_t i_wid:4; 1693 u64 i_wid:4;
1694 uint64_t i_adjust:1; 1694 u64 i_adjust:1;
1695 uint64_t i_rsvd_1:3; 1695 u64 i_rsvd_1:3;
1696 uint64_t i_field:2; 1696 u64 i_field:2;
1697 uint64_t i_rsvd:54; 1697 u64 i_rsvd:54;
1698 } ii_ipca_fld_s; 1698 } ii_ipca_fld_s;
1699} ii_ipca_u_t; 1699} ii_ipca_u_t;
1700 1700
@@ -1709,12 +1709,12 @@ typedef union ii_ipca_u {
1709 ************************************************************************/ 1709 ************************************************************************/
1710 1710
1711typedef union ii_iprte0a_u { 1711typedef union ii_iprte0a_u {
1712 uint64_t ii_iprte0a_regval; 1712 u64 ii_iprte0a_regval;
1713 struct { 1713 struct {
1714 uint64_t i_rsvd_1:54; 1714 u64 i_rsvd_1:54;
1715 uint64_t i_widget:4; 1715 u64 i_widget:4;
1716 uint64_t i_to_cnt:5; 1716 u64 i_to_cnt:5;
1717 uint64_t i_vld:1; 1717 u64 i_vld:1;
1718 } ii_iprte0a_fld_s; 1718 } ii_iprte0a_fld_s;
1719} ii_iprte0a_u_t; 1719} ii_iprte0a_u_t;
1720 1720
@@ -1729,12 +1729,12 @@ typedef union ii_iprte0a_u {
1729 ************************************************************************/ 1729 ************************************************************************/
1730 1730
1731typedef union ii_iprte1a_u { 1731typedef union ii_iprte1a_u {
1732 uint64_t ii_iprte1a_regval; 1732 u64 ii_iprte1a_regval;
1733 struct { 1733 struct {
1734 uint64_t i_rsvd_1:54; 1734 u64 i_rsvd_1:54;
1735 uint64_t i_widget:4; 1735 u64 i_widget:4;
1736 uint64_t i_to_cnt:5; 1736 u64 i_to_cnt:5;
1737 uint64_t i_vld:1; 1737 u64 i_vld:1;
1738 } ii_iprte1a_fld_s; 1738 } ii_iprte1a_fld_s;
1739} ii_iprte1a_u_t; 1739} ii_iprte1a_u_t;
1740 1740
@@ -1749,12 +1749,12 @@ typedef union ii_iprte1a_u {
1749 ************************************************************************/ 1749 ************************************************************************/
1750 1750
1751typedef union ii_iprte2a_u { 1751typedef union ii_iprte2a_u {
1752 uint64_t ii_iprte2a_regval; 1752 u64 ii_iprte2a_regval;
1753 struct { 1753 struct {
1754 uint64_t i_rsvd_1:54; 1754 u64 i_rsvd_1:54;
1755 uint64_t i_widget:4; 1755 u64 i_widget:4;
1756 uint64_t i_to_cnt:5; 1756 u64 i_to_cnt:5;
1757 uint64_t i_vld:1; 1757 u64 i_vld:1;
1758 } ii_iprte2a_fld_s; 1758 } ii_iprte2a_fld_s;
1759} ii_iprte2a_u_t; 1759} ii_iprte2a_u_t;
1760 1760
@@ -1769,12 +1769,12 @@ typedef union ii_iprte2a_u {
1769 ************************************************************************/ 1769 ************************************************************************/
1770 1770
1771typedef union ii_iprte3a_u { 1771typedef union ii_iprte3a_u {
1772 uint64_t ii_iprte3a_regval; 1772 u64 ii_iprte3a_regval;
1773 struct { 1773 struct {
1774 uint64_t i_rsvd_1:54; 1774 u64 i_rsvd_1:54;
1775 uint64_t i_widget:4; 1775 u64 i_widget:4;
1776 uint64_t i_to_cnt:5; 1776 u64 i_to_cnt:5;
1777 uint64_t i_vld:1; 1777 u64 i_vld:1;
1778 } ii_iprte3a_fld_s; 1778 } ii_iprte3a_fld_s;
1779} ii_iprte3a_u_t; 1779} ii_iprte3a_u_t;
1780 1780
@@ -1789,12 +1789,12 @@ typedef union ii_iprte3a_u {
1789 ************************************************************************/ 1789 ************************************************************************/
1790 1790
1791typedef union ii_iprte4a_u { 1791typedef union ii_iprte4a_u {
1792 uint64_t ii_iprte4a_regval; 1792 u64 ii_iprte4a_regval;
1793 struct { 1793 struct {
1794 uint64_t i_rsvd_1:54; 1794 u64 i_rsvd_1:54;
1795 uint64_t i_widget:4; 1795 u64 i_widget:4;
1796 uint64_t i_to_cnt:5; 1796 u64 i_to_cnt:5;
1797 uint64_t i_vld:1; 1797 u64 i_vld:1;
1798 } ii_iprte4a_fld_s; 1798 } ii_iprte4a_fld_s;
1799} ii_iprte4a_u_t; 1799} ii_iprte4a_u_t;
1800 1800
@@ -1809,12 +1809,12 @@ typedef union ii_iprte4a_u {
1809 ************************************************************************/ 1809 ************************************************************************/
1810 1810
1811typedef union ii_iprte5a_u { 1811typedef union ii_iprte5a_u {
1812 uint64_t ii_iprte5a_regval; 1812 u64 ii_iprte5a_regval;
1813 struct { 1813 struct {
1814 uint64_t i_rsvd_1:54; 1814 u64 i_rsvd_1:54;
1815 uint64_t i_widget:4; 1815 u64 i_widget:4;
1816 uint64_t i_to_cnt:5; 1816 u64 i_to_cnt:5;
1817 uint64_t i_vld:1; 1817 u64 i_vld:1;
1818 } ii_iprte5a_fld_s; 1818 } ii_iprte5a_fld_s;
1819} ii_iprte5a_u_t; 1819} ii_iprte5a_u_t;
1820 1820
@@ -1829,12 +1829,12 @@ typedef union ii_iprte5a_u {
1829 ************************************************************************/ 1829 ************************************************************************/
1830 1830
1831typedef union ii_iprte6a_u { 1831typedef union ii_iprte6a_u {
1832 uint64_t ii_iprte6a_regval; 1832 u64 ii_iprte6a_regval;
1833 struct { 1833 struct {
1834 uint64_t i_rsvd_1:54; 1834 u64 i_rsvd_1:54;
1835 uint64_t i_widget:4; 1835 u64 i_widget:4;
1836 uint64_t i_to_cnt:5; 1836 u64 i_to_cnt:5;
1837 uint64_t i_vld:1; 1837 u64 i_vld:1;
1838 } ii_iprte6a_fld_s; 1838 } ii_iprte6a_fld_s;
1839} ii_iprte6a_u_t; 1839} ii_iprte6a_u_t;
1840 1840
@@ -1849,12 +1849,12 @@ typedef union ii_iprte6a_u {
1849 ************************************************************************/ 1849 ************************************************************************/
1850 1850
1851typedef union ii_iprte7a_u { 1851typedef union ii_iprte7a_u {
1852 uint64_t ii_iprte7a_regval; 1852 u64 ii_iprte7a_regval;
1853 struct { 1853 struct {
1854 uint64_t i_rsvd_1:54; 1854 u64 i_rsvd_1:54;
1855 uint64_t i_widget:4; 1855 u64 i_widget:4;
1856 uint64_t i_to_cnt:5; 1856 u64 i_to_cnt:5;
1857 uint64_t i_vld:1; 1857 u64 i_vld:1;
1858 } ii_iprtea7_fld_s; 1858 } ii_iprtea7_fld_s;
1859} ii_iprte7a_u_t; 1859} ii_iprte7a_u_t;
1860 1860
@@ -1869,12 +1869,12 @@ typedef union ii_iprte7a_u {
1869 ************************************************************************/ 1869 ************************************************************************/
1870 1870
1871typedef union ii_iprte0b_u { 1871typedef union ii_iprte0b_u {
1872 uint64_t ii_iprte0b_regval; 1872 u64 ii_iprte0b_regval;
1873 struct { 1873 struct {
1874 uint64_t i_rsvd_1:3; 1874 u64 i_rsvd_1:3;
1875 uint64_t i_address:47; 1875 u64 i_address:47;
1876 uint64_t i_init:3; 1876 u64 i_init:3;
1877 uint64_t i_source:11; 1877 u64 i_source:11;
1878 } ii_iprte0b_fld_s; 1878 } ii_iprte0b_fld_s;
1879} ii_iprte0b_u_t; 1879} ii_iprte0b_u_t;
1880 1880
@@ -1889,12 +1889,12 @@ typedef union ii_iprte0b_u {
1889 ************************************************************************/ 1889 ************************************************************************/
1890 1890
1891typedef union ii_iprte1b_u { 1891typedef union ii_iprte1b_u {
1892 uint64_t ii_iprte1b_regval; 1892 u64 ii_iprte1b_regval;
1893 struct { 1893 struct {
1894 uint64_t i_rsvd_1:3; 1894 u64 i_rsvd_1:3;
1895 uint64_t i_address:47; 1895 u64 i_address:47;
1896 uint64_t i_init:3; 1896 u64 i_init:3;
1897 uint64_t i_source:11; 1897 u64 i_source:11;
1898 } ii_iprte1b_fld_s; 1898 } ii_iprte1b_fld_s;
1899} ii_iprte1b_u_t; 1899} ii_iprte1b_u_t;
1900 1900
@@ -1909,12 +1909,12 @@ typedef union ii_iprte1b_u {
1909 ************************************************************************/ 1909 ************************************************************************/
1910 1910
1911typedef union ii_iprte2b_u { 1911typedef union ii_iprte2b_u {
1912 uint64_t ii_iprte2b_regval; 1912 u64 ii_iprte2b_regval;
1913 struct { 1913 struct {
1914 uint64_t i_rsvd_1:3; 1914 u64 i_rsvd_1:3;
1915 uint64_t i_address:47; 1915 u64 i_address:47;
1916 uint64_t i_init:3; 1916 u64 i_init:3;
1917 uint64_t i_source:11; 1917 u64 i_source:11;
1918 } ii_iprte2b_fld_s; 1918 } ii_iprte2b_fld_s;
1919} ii_iprte2b_u_t; 1919} ii_iprte2b_u_t;
1920 1920
@@ -1929,12 +1929,12 @@ typedef union ii_iprte2b_u {
1929 ************************************************************************/ 1929 ************************************************************************/
1930 1930
1931typedef union ii_iprte3b_u { 1931typedef union ii_iprte3b_u {
1932 uint64_t ii_iprte3b_regval; 1932 u64 ii_iprte3b_regval;
1933 struct { 1933 struct {
1934 uint64_t i_rsvd_1:3; 1934 u64 i_rsvd_1:3;
1935 uint64_t i_address:47; 1935 u64 i_address:47;
1936 uint64_t i_init:3; 1936 u64 i_init:3;
1937 uint64_t i_source:11; 1937 u64 i_source:11;
1938 } ii_iprte3b_fld_s; 1938 } ii_iprte3b_fld_s;
1939} ii_iprte3b_u_t; 1939} ii_iprte3b_u_t;
1940 1940
@@ -1949,12 +1949,12 @@ typedef union ii_iprte3b_u {
1949 ************************************************************************/ 1949 ************************************************************************/
1950 1950
1951typedef union ii_iprte4b_u { 1951typedef union ii_iprte4b_u {
1952 uint64_t ii_iprte4b_regval; 1952 u64 ii_iprte4b_regval;
1953 struct { 1953 struct {
1954 uint64_t i_rsvd_1:3; 1954 u64 i_rsvd_1:3;
1955 uint64_t i_address:47; 1955 u64 i_address:47;
1956 uint64_t i_init:3; 1956 u64 i_init:3;
1957 uint64_t i_source:11; 1957 u64 i_source:11;
1958 } ii_iprte4b_fld_s; 1958 } ii_iprte4b_fld_s;
1959} ii_iprte4b_u_t; 1959} ii_iprte4b_u_t;
1960 1960
@@ -1969,12 +1969,12 @@ typedef union ii_iprte4b_u {
1969 ************************************************************************/ 1969 ************************************************************************/
1970 1970
1971typedef union ii_iprte5b_u { 1971typedef union ii_iprte5b_u {
1972 uint64_t ii_iprte5b_regval; 1972 u64 ii_iprte5b_regval;
1973 struct { 1973 struct {
1974 uint64_t i_rsvd_1:3; 1974 u64 i_rsvd_1:3;
1975 uint64_t i_address:47; 1975 u64 i_address:47;
1976 uint64_t i_init:3; 1976 u64 i_init:3;
1977 uint64_t i_source:11; 1977 u64 i_source:11;
1978 } ii_iprte5b_fld_s; 1978 } ii_iprte5b_fld_s;
1979} ii_iprte5b_u_t; 1979} ii_iprte5b_u_t;
1980 1980
@@ -1989,12 +1989,12 @@ typedef union ii_iprte5b_u {
1989 ************************************************************************/ 1989 ************************************************************************/
1990 1990
1991typedef union ii_iprte6b_u { 1991typedef union ii_iprte6b_u {
1992 uint64_t ii_iprte6b_regval; 1992 u64 ii_iprte6b_regval;
1993 struct { 1993 struct {
1994 uint64_t i_rsvd_1:3; 1994 u64 i_rsvd_1:3;
1995 uint64_t i_address:47; 1995 u64 i_address:47;
1996 uint64_t i_init:3; 1996 u64 i_init:3;
1997 uint64_t i_source:11; 1997 u64 i_source:11;
1998 1998
1999 } ii_iprte6b_fld_s; 1999 } ii_iprte6b_fld_s;
2000} ii_iprte6b_u_t; 2000} ii_iprte6b_u_t;
@@ -2010,12 +2010,12 @@ typedef union ii_iprte6b_u {
2010 ************************************************************************/ 2010 ************************************************************************/
2011 2011
2012typedef union ii_iprte7b_u { 2012typedef union ii_iprte7b_u {
2013 uint64_t ii_iprte7b_regval; 2013 u64 ii_iprte7b_regval;
2014 struct { 2014 struct {
2015 uint64_t i_rsvd_1:3; 2015 u64 i_rsvd_1:3;
2016 uint64_t i_address:47; 2016 u64 i_address:47;
2017 uint64_t i_init:3; 2017 u64 i_init:3;
2018 uint64_t i_source:11; 2018 u64 i_source:11;
2019 } ii_iprte7b_fld_s; 2019 } ii_iprte7b_fld_s;
2020} ii_iprte7b_u_t; 2020} ii_iprte7b_u_t;
2021 2021
@@ -2038,13 +2038,13 @@ typedef union ii_iprte7b_u {
2038 ************************************************************************/ 2038 ************************************************************************/
2039 2039
2040typedef union ii_ipdr_u { 2040typedef union ii_ipdr_u {
2041 uint64_t ii_ipdr_regval; 2041 u64 ii_ipdr_regval;
2042 struct { 2042 struct {
2043 uint64_t i_te:3; 2043 u64 i_te:3;
2044 uint64_t i_rsvd_1:1; 2044 u64 i_rsvd_1:1;
2045 uint64_t i_pnd:1; 2045 u64 i_pnd:1;
2046 uint64_t i_init_rpcnt:1; 2046 u64 i_init_rpcnt:1;
2047 uint64_t i_rsvd:58; 2047 u64 i_rsvd:58;
2048 } ii_ipdr_fld_s; 2048 } ii_ipdr_fld_s;
2049} ii_ipdr_u_t; 2049} ii_ipdr_u_t;
2050 2050
@@ -2066,11 +2066,11 @@ typedef union ii_ipdr_u {
2066 ************************************************************************/ 2066 ************************************************************************/
2067 2067
2068typedef union ii_icdr_u { 2068typedef union ii_icdr_u {
2069 uint64_t ii_icdr_regval; 2069 u64 ii_icdr_regval;
2070 struct { 2070 struct {
2071 uint64_t i_crb_num:4; 2071 u64 i_crb_num:4;
2072 uint64_t i_pnd:1; 2072 u64 i_pnd:1;
2073 uint64_t i_rsvd:59; 2073 u64 i_rsvd:59;
2074 } ii_icdr_fld_s; 2074 } ii_icdr_fld_s;
2075} ii_icdr_u_t; 2075} ii_icdr_u_t;
2076 2076
@@ -2092,13 +2092,13 @@ typedef union ii_icdr_u {
2092 ************************************************************************/ 2092 ************************************************************************/
2093 2093
2094typedef union ii_ifdr_u { 2094typedef union ii_ifdr_u {
2095 uint64_t ii_ifdr_regval; 2095 u64 ii_ifdr_regval;
2096 struct { 2096 struct {
2097 uint64_t i_ioq_max_rq:7; 2097 u64 i_ioq_max_rq:7;
2098 uint64_t i_set_ioq_rq:1; 2098 u64 i_set_ioq_rq:1;
2099 uint64_t i_ioq_max_rp:7; 2099 u64 i_ioq_max_rp:7;
2100 uint64_t i_set_ioq_rp:1; 2100 u64 i_set_ioq_rp:1;
2101 uint64_t i_rsvd:48; 2101 u64 i_rsvd:48;
2102 } ii_ifdr_fld_s; 2102 } ii_ifdr_fld_s;
2103} ii_ifdr_u_t; 2103} ii_ifdr_u_t;
2104 2104
@@ -2114,12 +2114,12 @@ typedef union ii_ifdr_u {
2114 ************************************************************************/ 2114 ************************************************************************/
2115 2115
2116typedef union ii_iiap_u { 2116typedef union ii_iiap_u {
2117 uint64_t ii_iiap_regval; 2117 u64 ii_iiap_regval;
2118 struct { 2118 struct {
2119 uint64_t i_rq_mls:6; 2119 u64 i_rq_mls:6;
2120 uint64_t i_rsvd_1:2; 2120 u64 i_rsvd_1:2;
2121 uint64_t i_rp_mls:6; 2121 u64 i_rp_mls:6;
2122 uint64_t i_rsvd:50; 2122 u64 i_rsvd:50;
2123 } ii_iiap_fld_s; 2123 } ii_iiap_fld_s;
2124} ii_iiap_u_t; 2124} ii_iiap_u_t;
2125 2125
@@ -2133,22 +2133,22 @@ typedef union ii_iiap_u {
2133 ************************************************************************/ 2133 ************************************************************************/
2134 2134
2135typedef union ii_icmr_u { 2135typedef union ii_icmr_u {
2136 uint64_t ii_icmr_regval; 2136 u64 ii_icmr_regval;
2137 struct { 2137 struct {
2138 uint64_t i_sp_msg:1; 2138 u64 i_sp_msg:1;
2139 uint64_t i_rd_hdr:1; 2139 u64 i_rd_hdr:1;
2140 uint64_t i_rsvd_4:2; 2140 u64 i_rsvd_4:2;
2141 uint64_t i_c_cnt:4; 2141 u64 i_c_cnt:4;
2142 uint64_t i_rsvd_3:4; 2142 u64 i_rsvd_3:4;
2143 uint64_t i_clr_rqpd:1; 2143 u64 i_clr_rqpd:1;
2144 uint64_t i_clr_rppd:1; 2144 u64 i_clr_rppd:1;
2145 uint64_t i_rsvd_2:2; 2145 u64 i_rsvd_2:2;
2146 uint64_t i_fc_cnt:4; 2146 u64 i_fc_cnt:4;
2147 uint64_t i_crb_vld:15; 2147 u64 i_crb_vld:15;
2148 uint64_t i_crb_mark:15; 2148 u64 i_crb_mark:15;
2149 uint64_t i_rsvd_1:2; 2149 u64 i_rsvd_1:2;
2150 uint64_t i_precise:1; 2150 u64 i_precise:1;
2151 uint64_t i_rsvd:11; 2151 u64 i_rsvd:11;
2152 } ii_icmr_fld_s; 2152 } ii_icmr_fld_s;
2153} ii_icmr_u_t; 2153} ii_icmr_u_t;
2154 2154
@@ -2161,13 +2161,13 @@ typedef union ii_icmr_u {
2161 ************************************************************************/ 2161 ************************************************************************/
2162 2162
2163typedef union ii_iccr_u { 2163typedef union ii_iccr_u {
2164 uint64_t ii_iccr_regval; 2164 u64 ii_iccr_regval;
2165 struct { 2165 struct {
2166 uint64_t i_crb_num:4; 2166 u64 i_crb_num:4;
2167 uint64_t i_rsvd_1:4; 2167 u64 i_rsvd_1:4;
2168 uint64_t i_cmd:8; 2168 u64 i_cmd:8;
2169 uint64_t i_pending:1; 2169 u64 i_pending:1;
2170 uint64_t i_rsvd:47; 2170 u64 i_rsvd:47;
2171 } ii_iccr_fld_s; 2171 } ii_iccr_fld_s;
2172} ii_iccr_u_t; 2172} ii_iccr_u_t;
2173 2173
@@ -2178,10 +2178,10 @@ typedef union ii_iccr_u {
2178 ************************************************************************/ 2178 ************************************************************************/
2179 2179
2180typedef union ii_icto_u { 2180typedef union ii_icto_u {
2181 uint64_t ii_icto_regval; 2181 u64 ii_icto_regval;
2182 struct { 2182 struct {
2183 uint64_t i_timeout:8; 2183 u64 i_timeout:8;
2184 uint64_t i_rsvd:56; 2184 u64 i_rsvd:56;
2185 } ii_icto_fld_s; 2185 } ii_icto_fld_s;
2186} ii_icto_u_t; 2186} ii_icto_u_t;
2187 2187
@@ -2197,10 +2197,10 @@ typedef union ii_icto_u {
2197 ************************************************************************/ 2197 ************************************************************************/
2198 2198
2199typedef union ii_ictp_u { 2199typedef union ii_ictp_u {
2200 uint64_t ii_ictp_regval; 2200 u64 ii_ictp_regval;
2201 struct { 2201 struct {
2202 uint64_t i_prescale:24; 2202 u64 i_prescale:24;
2203 uint64_t i_rsvd:40; 2203 u64 i_rsvd:40;
2204 } ii_ictp_fld_s; 2204 } ii_ictp_fld_s;
2205} ii_ictp_u_t; 2205} ii_ictp_u_t;
2206 2206
@@ -2228,14 +2228,14 @@ typedef union ii_ictp_u {
2228 ************************************************************************/ 2228 ************************************************************************/
2229 2229
2230typedef union ii_icrb0_a_u { 2230typedef union ii_icrb0_a_u {
2231 uint64_t ii_icrb0_a_regval; 2231 u64 ii_icrb0_a_regval;
2232 struct { 2232 struct {
2233 uint64_t ia_iow:1; 2233 u64 ia_iow:1;
2234 uint64_t ia_vld:1; 2234 u64 ia_vld:1;
2235 uint64_t ia_addr:47; 2235 u64 ia_addr:47;
2236 uint64_t ia_tnum:5; 2236 u64 ia_tnum:5;
2237 uint64_t ia_sidn:4; 2237 u64 ia_sidn:4;
2238 uint64_t ia_rsvd:6; 2238 u64 ia_rsvd:6;
2239 } ii_icrb0_a_fld_s; 2239 } ii_icrb0_a_fld_s;
2240} ii_icrb0_a_u_t; 2240} ii_icrb0_a_u_t;
2241 2241
@@ -2249,30 +2249,30 @@ typedef union ii_icrb0_a_u {
2249 ************************************************************************/ 2249 ************************************************************************/
2250 2250
2251typedef union ii_icrb0_b_u { 2251typedef union ii_icrb0_b_u {
2252 uint64_t ii_icrb0_b_regval; 2252 u64 ii_icrb0_b_regval;
2253 struct { 2253 struct {
2254 uint64_t ib_xt_err:1; 2254 u64 ib_xt_err:1;
2255 uint64_t ib_mark:1; 2255 u64 ib_mark:1;
2256 uint64_t ib_ln_uce:1; 2256 u64 ib_ln_uce:1;
2257 uint64_t ib_errcode:3; 2257 u64 ib_errcode:3;
2258 uint64_t ib_error:1; 2258 u64 ib_error:1;
2259 uint64_t ib_stall__bte_1:1; 2259 u64 ib_stall__bte_1:1;
2260 uint64_t ib_stall__bte_0:1; 2260 u64 ib_stall__bte_0:1;
2261 uint64_t ib_stall__intr:1; 2261 u64 ib_stall__intr:1;
2262 uint64_t ib_stall_ib:1; 2262 u64 ib_stall_ib:1;
2263 uint64_t ib_intvn:1; 2263 u64 ib_intvn:1;
2264 uint64_t ib_wb:1; 2264 u64 ib_wb:1;
2265 uint64_t ib_hold:1; 2265 u64 ib_hold:1;
2266 uint64_t ib_ack:1; 2266 u64 ib_ack:1;
2267 uint64_t ib_resp:1; 2267 u64 ib_resp:1;
2268 uint64_t ib_ack_cnt:11; 2268 u64 ib_ack_cnt:11;
2269 uint64_t ib_rsvd:7; 2269 u64 ib_rsvd:7;
2270 uint64_t ib_exc:5; 2270 u64 ib_exc:5;
2271 uint64_t ib_init:3; 2271 u64 ib_init:3;
2272 uint64_t ib_imsg:8; 2272 u64 ib_imsg:8;
2273 uint64_t ib_imsgtype:2; 2273 u64 ib_imsgtype:2;
2274 uint64_t ib_use_old:1; 2274 u64 ib_use_old:1;
2275 uint64_t ib_rsvd_1:11; 2275 u64 ib_rsvd_1:11;
2276 } ii_icrb0_b_fld_s; 2276 } ii_icrb0_b_fld_s;
2277} ii_icrb0_b_u_t; 2277} ii_icrb0_b_u_t;
2278 2278
@@ -2286,17 +2286,17 @@ typedef union ii_icrb0_b_u {
2286 ************************************************************************/ 2286 ************************************************************************/
2287 2287
2288typedef union ii_icrb0_c_u { 2288typedef union ii_icrb0_c_u {
2289 uint64_t ii_icrb0_c_regval; 2289 u64 ii_icrb0_c_regval;
2290 struct { 2290 struct {
2291 uint64_t ic_source:15; 2291 u64 ic_source:15;
2292 uint64_t ic_size:2; 2292 u64 ic_size:2;
2293 uint64_t ic_ct:1; 2293 u64 ic_ct:1;
2294 uint64_t ic_bte_num:1; 2294 u64 ic_bte_num:1;
2295 uint64_t ic_gbr:1; 2295 u64 ic_gbr:1;
2296 uint64_t ic_resprqd:1; 2296 u64 ic_resprqd:1;
2297 uint64_t ic_bo:1; 2297 u64 ic_bo:1;
2298 uint64_t ic_suppl:15; 2298 u64 ic_suppl:15;
2299 uint64_t ic_rsvd:27; 2299 u64 ic_rsvd:27;
2300 } ii_icrb0_c_fld_s; 2300 } ii_icrb0_c_fld_s;
2301} ii_icrb0_c_u_t; 2301} ii_icrb0_c_u_t;
2302 2302
@@ -2310,14 +2310,14 @@ typedef union ii_icrb0_c_u {
2310 ************************************************************************/ 2310 ************************************************************************/
2311 2311
2312typedef union ii_icrb0_d_u { 2312typedef union ii_icrb0_d_u {
2313 uint64_t ii_icrb0_d_regval; 2313 u64 ii_icrb0_d_regval;
2314 struct { 2314 struct {
2315 uint64_t id_pa_be:43; 2315 u64 id_pa_be:43;
2316 uint64_t id_bte_op:1; 2316 u64 id_bte_op:1;
2317 uint64_t id_pr_psc:4; 2317 u64 id_pr_psc:4;
2318 uint64_t id_pr_cnt:4; 2318 u64 id_pr_cnt:4;
2319 uint64_t id_sleep:1; 2319 u64 id_sleep:1;
2320 uint64_t id_rsvd:11; 2320 u64 id_rsvd:11;
2321 } ii_icrb0_d_fld_s; 2321 } ii_icrb0_d_fld_s;
2322} ii_icrb0_d_u_t; 2322} ii_icrb0_d_u_t;
2323 2323
@@ -2331,14 +2331,14 @@ typedef union ii_icrb0_d_u {
2331 ************************************************************************/ 2331 ************************************************************************/
2332 2332
2333typedef union ii_icrb0_e_u { 2333typedef union ii_icrb0_e_u {
2334 uint64_t ii_icrb0_e_regval; 2334 u64 ii_icrb0_e_regval;
2335 struct { 2335 struct {
2336 uint64_t ie_timeout:8; 2336 u64 ie_timeout:8;
2337 uint64_t ie_context:15; 2337 u64 ie_context:15;
2338 uint64_t ie_rsvd:1; 2338 u64 ie_rsvd:1;
2339 uint64_t ie_tvld:1; 2339 u64 ie_tvld:1;
2340 uint64_t ie_cvld:1; 2340 u64 ie_cvld:1;
2341 uint64_t ie_rsvd_0:38; 2341 u64 ie_rsvd_0:38;
2342 } ii_icrb0_e_fld_s; 2342 } ii_icrb0_e_fld_s;
2343} ii_icrb0_e_u_t; 2343} ii_icrb0_e_u_t;
2344 2344
@@ -2351,12 +2351,12 @@ typedef union ii_icrb0_e_u {
2351 ************************************************************************/ 2351 ************************************************************************/
2352 2352
2353typedef union ii_icsml_u { 2353typedef union ii_icsml_u {
2354 uint64_t ii_icsml_regval; 2354 u64 ii_icsml_regval;
2355 struct { 2355 struct {
2356 uint64_t i_tt_addr:47; 2356 u64 i_tt_addr:47;
2357 uint64_t i_newsuppl_ex:14; 2357 u64 i_newsuppl_ex:14;
2358 uint64_t i_reserved:2; 2358 u64 i_reserved:2;
2359 uint64_t i_overflow:1; 2359 u64 i_overflow:1;
2360 } ii_icsml_fld_s; 2360 } ii_icsml_fld_s;
2361} ii_icsml_u_t; 2361} ii_icsml_u_t;
2362 2362
@@ -2369,10 +2369,10 @@ typedef union ii_icsml_u {
2369 ************************************************************************/ 2369 ************************************************************************/
2370 2370
2371typedef union ii_icsmm_u { 2371typedef union ii_icsmm_u {
2372 uint64_t ii_icsmm_regval; 2372 u64 ii_icsmm_regval;
2373 struct { 2373 struct {
2374 uint64_t i_tt_ack_cnt:11; 2374 u64 i_tt_ack_cnt:11;
2375 uint64_t i_reserved:53; 2375 u64 i_reserved:53;
2376 } ii_icsmm_fld_s; 2376 } ii_icsmm_fld_s;
2377} ii_icsmm_u_t; 2377} ii_icsmm_u_t;
2378 2378
@@ -2385,48 +2385,48 @@ typedef union ii_icsmm_u {
2385 ************************************************************************/ 2385 ************************************************************************/
2386 2386
2387typedef union ii_icsmh_u { 2387typedef union ii_icsmh_u {
2388 uint64_t ii_icsmh_regval; 2388 u64 ii_icsmh_regval;
2389 struct { 2389 struct {
2390 uint64_t i_tt_vld:1; 2390 u64 i_tt_vld:1;
2391 uint64_t i_xerr:1; 2391 u64 i_xerr:1;
2392 uint64_t i_ft_cwact_o:1; 2392 u64 i_ft_cwact_o:1;
2393 uint64_t i_ft_wact_o:1; 2393 u64 i_ft_wact_o:1;
2394 uint64_t i_ft_active_o:1; 2394 u64 i_ft_active_o:1;
2395 uint64_t i_sync:1; 2395 u64 i_sync:1;
2396 uint64_t i_mnusg:1; 2396 u64 i_mnusg:1;
2397 uint64_t i_mnusz:1; 2397 u64 i_mnusz:1;
2398 uint64_t i_plusz:1; 2398 u64 i_plusz:1;
2399 uint64_t i_plusg:1; 2399 u64 i_plusg:1;
2400 uint64_t i_tt_exc:5; 2400 u64 i_tt_exc:5;
2401 uint64_t i_tt_wb:1; 2401 u64 i_tt_wb:1;
2402 uint64_t i_tt_hold:1; 2402 u64 i_tt_hold:1;
2403 uint64_t i_tt_ack:1; 2403 u64 i_tt_ack:1;
2404 uint64_t i_tt_resp:1; 2404 u64 i_tt_resp:1;
2405 uint64_t i_tt_intvn:1; 2405 u64 i_tt_intvn:1;
2406 uint64_t i_g_stall_bte1:1; 2406 u64 i_g_stall_bte1:1;
2407 uint64_t i_g_stall_bte0:1; 2407 u64 i_g_stall_bte0:1;
2408 uint64_t i_g_stall_il:1; 2408 u64 i_g_stall_il:1;
2409 uint64_t i_g_stall_ib:1; 2409 u64 i_g_stall_ib:1;
2410 uint64_t i_tt_imsg:8; 2410 u64 i_tt_imsg:8;
2411 uint64_t i_tt_imsgtype:2; 2411 u64 i_tt_imsgtype:2;
2412 uint64_t i_tt_use_old:1; 2412 u64 i_tt_use_old:1;
2413 uint64_t i_tt_respreqd:1; 2413 u64 i_tt_respreqd:1;
2414 uint64_t i_tt_bte_num:1; 2414 u64 i_tt_bte_num:1;
2415 uint64_t i_cbn:1; 2415 u64 i_cbn:1;
2416 uint64_t i_match:1; 2416 u64 i_match:1;
2417 uint64_t i_rpcnt_lt_34:1; 2417 u64 i_rpcnt_lt_34:1;
2418 uint64_t i_rpcnt_ge_34:1; 2418 u64 i_rpcnt_ge_34:1;
2419 uint64_t i_rpcnt_lt_18:1; 2419 u64 i_rpcnt_lt_18:1;
2420 uint64_t i_rpcnt_ge_18:1; 2420 u64 i_rpcnt_ge_18:1;
2421 uint64_t i_rpcnt_lt_2:1; 2421 u64 i_rpcnt_lt_2:1;
2422 uint64_t i_rpcnt_ge_2:1; 2422 u64 i_rpcnt_ge_2:1;
2423 uint64_t i_rqcnt_lt_18:1; 2423 u64 i_rqcnt_lt_18:1;
2424 uint64_t i_rqcnt_ge_18:1; 2424 u64 i_rqcnt_ge_18:1;
2425 uint64_t i_rqcnt_lt_2:1; 2425 u64 i_rqcnt_lt_2:1;
2426 uint64_t i_rqcnt_ge_2:1; 2426 u64 i_rqcnt_ge_2:1;
2427 uint64_t i_tt_device:7; 2427 u64 i_tt_device:7;
2428 uint64_t i_tt_init:3; 2428 u64 i_tt_init:3;
2429 uint64_t i_reserved:5; 2429 u64 i_reserved:5;
2430 } ii_icsmh_fld_s; 2430 } ii_icsmh_fld_s;
2431} ii_icsmh_u_t; 2431} ii_icsmh_u_t;
2432 2432
@@ -2439,14 +2439,14 @@ typedef union ii_icsmh_u {
2439 ************************************************************************/ 2439 ************************************************************************/
2440 2440
2441typedef union ii_idbss_u { 2441typedef union ii_idbss_u {
2442 uint64_t ii_idbss_regval; 2442 u64 ii_idbss_regval;
2443 struct { 2443 struct {
2444 uint64_t i_iioclk_core_submenu:3; 2444 u64 i_iioclk_core_submenu:3;
2445 uint64_t i_rsvd:5; 2445 u64 i_rsvd:5;
2446 uint64_t i_fsbclk_wrapper_submenu:3; 2446 u64 i_fsbclk_wrapper_submenu:3;
2447 uint64_t i_rsvd_1:5; 2447 u64 i_rsvd_1:5;
2448 uint64_t i_iioclk_menu:5; 2448 u64 i_iioclk_menu:5;
2449 uint64_t i_rsvd_2:43; 2449 u64 i_rsvd_2:43;
2450 } ii_idbss_fld_s; 2450 } ii_idbss_fld_s;
2451} ii_idbss_u_t; 2451} ii_idbss_u_t;
2452 2452
@@ -2466,13 +2466,13 @@ typedef union ii_idbss_u {
2466 ************************************************************************/ 2466 ************************************************************************/
2467 2467
2468typedef union ii_ibls0_u { 2468typedef union ii_ibls0_u {
2469 uint64_t ii_ibls0_regval; 2469 u64 ii_ibls0_regval;
2470 struct { 2470 struct {
2471 uint64_t i_length:16; 2471 u64 i_length:16;
2472 uint64_t i_error:1; 2472 u64 i_error:1;
2473 uint64_t i_rsvd_1:3; 2473 u64 i_rsvd_1:3;
2474 uint64_t i_busy:1; 2474 u64 i_busy:1;
2475 uint64_t i_rsvd:43; 2475 u64 i_rsvd:43;
2476 } ii_ibls0_fld_s; 2476 } ii_ibls0_fld_s;
2477} ii_ibls0_u_t; 2477} ii_ibls0_u_t;
2478 2478
@@ -2487,11 +2487,11 @@ typedef union ii_ibls0_u {
2487 ************************************************************************/ 2487 ************************************************************************/
2488 2488
2489typedef union ii_ibsa0_u { 2489typedef union ii_ibsa0_u {
2490 uint64_t ii_ibsa0_regval; 2490 u64 ii_ibsa0_regval;
2491 struct { 2491 struct {
2492 uint64_t i_rsvd_1:7; 2492 u64 i_rsvd_1:7;
2493 uint64_t i_addr:42; 2493 u64 i_addr:42;
2494 uint64_t i_rsvd:15; 2494 u64 i_rsvd:15;
2495 } ii_ibsa0_fld_s; 2495 } ii_ibsa0_fld_s;
2496} ii_ibsa0_u_t; 2496} ii_ibsa0_u_t;
2497 2497
@@ -2506,11 +2506,11 @@ typedef union ii_ibsa0_u {
2506 ************************************************************************/ 2506 ************************************************************************/
2507 2507
2508typedef union ii_ibda0_u { 2508typedef union ii_ibda0_u {
2509 uint64_t ii_ibda0_regval; 2509 u64 ii_ibda0_regval;
2510 struct { 2510 struct {
2511 uint64_t i_rsvd_1:7; 2511 u64 i_rsvd_1:7;
2512 uint64_t i_addr:42; 2512 u64 i_addr:42;
2513 uint64_t i_rsvd:15; 2513 u64 i_rsvd:15;
2514 } ii_ibda0_fld_s; 2514 } ii_ibda0_fld_s;
2515} ii_ibda0_u_t; 2515} ii_ibda0_u_t;
2516 2516
@@ -2527,14 +2527,14 @@ typedef union ii_ibda0_u {
2527 ************************************************************************/ 2527 ************************************************************************/
2528 2528
2529typedef union ii_ibct0_u { 2529typedef union ii_ibct0_u {
2530 uint64_t ii_ibct0_regval; 2530 u64 ii_ibct0_regval;
2531 struct { 2531 struct {
2532 uint64_t i_zerofill:1; 2532 u64 i_zerofill:1;
2533 uint64_t i_rsvd_2:3; 2533 u64 i_rsvd_2:3;
2534 uint64_t i_notify:1; 2534 u64 i_notify:1;
2535 uint64_t i_rsvd_1:3; 2535 u64 i_rsvd_1:3;
2536 uint64_t i_poison:1; 2536 u64 i_poison:1;
2537 uint64_t i_rsvd:55; 2537 u64 i_rsvd:55;
2538 } ii_ibct0_fld_s; 2538 } ii_ibct0_fld_s;
2539} ii_ibct0_u_t; 2539} ii_ibct0_u_t;
2540 2540
@@ -2546,11 +2546,11 @@ typedef union ii_ibct0_u {
2546 ************************************************************************/ 2546 ************************************************************************/
2547 2547
2548typedef union ii_ibna0_u { 2548typedef union ii_ibna0_u {
2549 uint64_t ii_ibna0_regval; 2549 u64 ii_ibna0_regval;
2550 struct { 2550 struct {
2551 uint64_t i_rsvd_1:7; 2551 u64 i_rsvd_1:7;
2552 uint64_t i_addr:42; 2552 u64 i_addr:42;
2553 uint64_t i_rsvd:15; 2553 u64 i_rsvd:15;
2554 } ii_ibna0_fld_s; 2554 } ii_ibna0_fld_s;
2555} ii_ibna0_u_t; 2555} ii_ibna0_u_t;
2556 2556
@@ -2563,13 +2563,13 @@ typedef union ii_ibna0_u {
2563 ************************************************************************/ 2563 ************************************************************************/
2564 2564
2565typedef union ii_ibia0_u { 2565typedef union ii_ibia0_u {
2566 uint64_t ii_ibia0_regval; 2566 u64 ii_ibia0_regval;
2567 struct { 2567 struct {
2568 uint64_t i_rsvd_2:1; 2568 u64 i_rsvd_2:1;
2569 uint64_t i_node_id:11; 2569 u64 i_node_id:11;
2570 uint64_t i_rsvd_1:4; 2570 u64 i_rsvd_1:4;
2571 uint64_t i_level:7; 2571 u64 i_level:7;
2572 uint64_t i_rsvd:41; 2572 u64 i_rsvd:41;
2573 } ii_ibia0_fld_s; 2573 } ii_ibia0_fld_s;
2574} ii_ibia0_u_t; 2574} ii_ibia0_u_t;
2575 2575
@@ -2589,13 +2589,13 @@ typedef union ii_ibia0_u {
2589 ************************************************************************/ 2589 ************************************************************************/
2590 2590
2591typedef union ii_ibls1_u { 2591typedef union ii_ibls1_u {
2592 uint64_t ii_ibls1_regval; 2592 u64 ii_ibls1_regval;
2593 struct { 2593 struct {
2594 uint64_t i_length:16; 2594 u64 i_length:16;
2595 uint64_t i_error:1; 2595 u64 i_error:1;
2596 uint64_t i_rsvd_1:3; 2596 u64 i_rsvd_1:3;
2597 uint64_t i_busy:1; 2597 u64 i_busy:1;
2598 uint64_t i_rsvd:43; 2598 u64 i_rsvd:43;
2599 } ii_ibls1_fld_s; 2599 } ii_ibls1_fld_s;
2600} ii_ibls1_u_t; 2600} ii_ibls1_u_t;
2601 2601
@@ -2610,11 +2610,11 @@ typedef union ii_ibls1_u {
2610 ************************************************************************/ 2610 ************************************************************************/
2611 2611
2612typedef union ii_ibsa1_u { 2612typedef union ii_ibsa1_u {
2613 uint64_t ii_ibsa1_regval; 2613 u64 ii_ibsa1_regval;
2614 struct { 2614 struct {
2615 uint64_t i_rsvd_1:7; 2615 u64 i_rsvd_1:7;
2616 uint64_t i_addr:33; 2616 u64 i_addr:33;
2617 uint64_t i_rsvd:24; 2617 u64 i_rsvd:24;
2618 } ii_ibsa1_fld_s; 2618 } ii_ibsa1_fld_s;
2619} ii_ibsa1_u_t; 2619} ii_ibsa1_u_t;
2620 2620
@@ -2629,11 +2629,11 @@ typedef union ii_ibsa1_u {
2629 ************************************************************************/ 2629 ************************************************************************/
2630 2630
2631typedef union ii_ibda1_u { 2631typedef union ii_ibda1_u {
2632 uint64_t ii_ibda1_regval; 2632 u64 ii_ibda1_regval;
2633 struct { 2633 struct {
2634 uint64_t i_rsvd_1:7; 2634 u64 i_rsvd_1:7;
2635 uint64_t i_addr:33; 2635 u64 i_addr:33;
2636 uint64_t i_rsvd:24; 2636 u64 i_rsvd:24;
2637 } ii_ibda1_fld_s; 2637 } ii_ibda1_fld_s;
2638} ii_ibda1_u_t; 2638} ii_ibda1_u_t;
2639 2639
@@ -2650,14 +2650,14 @@ typedef union ii_ibda1_u {
2650 ************************************************************************/ 2650 ************************************************************************/
2651 2651
2652typedef union ii_ibct1_u { 2652typedef union ii_ibct1_u {
2653 uint64_t ii_ibct1_regval; 2653 u64 ii_ibct1_regval;
2654 struct { 2654 struct {
2655 uint64_t i_zerofill:1; 2655 u64 i_zerofill:1;
2656 uint64_t i_rsvd_2:3; 2656 u64 i_rsvd_2:3;
2657 uint64_t i_notify:1; 2657 u64 i_notify:1;
2658 uint64_t i_rsvd_1:3; 2658 u64 i_rsvd_1:3;
2659 uint64_t i_poison:1; 2659 u64 i_poison:1;
2660 uint64_t i_rsvd:55; 2660 u64 i_rsvd:55;
2661 } ii_ibct1_fld_s; 2661 } ii_ibct1_fld_s;
2662} ii_ibct1_u_t; 2662} ii_ibct1_u_t;
2663 2663
@@ -2669,11 +2669,11 @@ typedef union ii_ibct1_u {
2669 ************************************************************************/ 2669 ************************************************************************/
2670 2670
2671typedef union ii_ibna1_u { 2671typedef union ii_ibna1_u {
2672 uint64_t ii_ibna1_regval; 2672 u64 ii_ibna1_regval;
2673 struct { 2673 struct {
2674 uint64_t i_rsvd_1:7; 2674 u64 i_rsvd_1:7;
2675 uint64_t i_addr:33; 2675 u64 i_addr:33;
2676 uint64_t i_rsvd:24; 2676 u64 i_rsvd:24;
2677 } ii_ibna1_fld_s; 2677 } ii_ibna1_fld_s;
2678} ii_ibna1_u_t; 2678} ii_ibna1_u_t;
2679 2679
@@ -2686,13 +2686,13 @@ typedef union ii_ibna1_u {
2686 ************************************************************************/ 2686 ************************************************************************/
2687 2687
2688typedef union ii_ibia1_u { 2688typedef union ii_ibia1_u {
2689 uint64_t ii_ibia1_regval; 2689 u64 ii_ibia1_regval;
2690 struct { 2690 struct {
2691 uint64_t i_pi_id:1; 2691 u64 i_pi_id:1;
2692 uint64_t i_node_id:8; 2692 u64 i_node_id:8;
2693 uint64_t i_rsvd_1:7; 2693 u64 i_rsvd_1:7;
2694 uint64_t i_level:7; 2694 u64 i_level:7;
2695 uint64_t i_rsvd:41; 2695 u64 i_rsvd:41;
2696 } ii_ibia1_fld_s; 2696 } ii_ibia1_fld_s;
2697} ii_ibia1_u_t; 2697} ii_ibia1_u_t;
2698 2698
@@ -2712,12 +2712,12 @@ typedef union ii_ibia1_u {
2712 ************************************************************************/ 2712 ************************************************************************/
2713 2713
2714typedef union ii_ipcr_u { 2714typedef union ii_ipcr_u {
2715 uint64_t ii_ipcr_regval; 2715 u64 ii_ipcr_regval;
2716 struct { 2716 struct {
2717 uint64_t i_ippr0_c:4; 2717 u64 i_ippr0_c:4;
2718 uint64_t i_ippr1_c:4; 2718 u64 i_ippr1_c:4;
2719 uint64_t i_icct:8; 2719 u64 i_icct:8;
2720 uint64_t i_rsvd:48; 2720 u64 i_rsvd:48;
2721 } ii_ipcr_fld_s; 2721 } ii_ipcr_fld_s;
2722} ii_ipcr_u_t; 2722} ii_ipcr_u_t;
2723 2723
@@ -2728,10 +2728,10 @@ typedef union ii_ipcr_u {
2728 ************************************************************************/ 2728 ************************************************************************/
2729 2729
2730typedef union ii_ippr_u { 2730typedef union ii_ippr_u {
2731 uint64_t ii_ippr_regval; 2731 u64 ii_ippr_regval;
2732 struct { 2732 struct {
2733 uint64_t i_ippr0:32; 2733 u64 i_ippr0:32;
2734 uint64_t i_ippr1:32; 2734 u64 i_ippr1:32;
2735 } ii_ippr_fld_s; 2735 } ii_ippr_fld_s;
2736} ii_ippr_u_t; 2736} ii_ippr_u_t;
2737 2737
@@ -3267,15 +3267,15 @@ typedef ii_icrb0_e_u_t icrbe_t;
3267#define IO_PERF_SETS 32 3267#define IO_PERF_SETS 32
3268 3268
3269/* Bit for the widget in inbound access register */ 3269/* Bit for the widget in inbound access register */
3270#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) 3270#define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w))
3271/* Bit for the widget in outbound access register */ 3271/* Bit for the widget in outbound access register */
3272#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) 3272#define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w))
3273 3273
3274/* NOTE: The following define assumes that we are going to get 3274/* NOTE: The following define assumes that we are going to get
3275 * widget numbers from 8 thru F and the device numbers within 3275 * widget numbers from 8 thru F and the device numbers within
3276 * widget from 0 thru 7. 3276 * widget from 0 thru 7.
3277 */ 3277 */
3278#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) 3278#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d))))
3279 3279
3280/* IO Interrupt Destination Register */ 3280/* IO Interrupt Destination Register */
3281#define IIO_IIDSR_SENT_SHIFT 28 3281#define IIO_IIDSR_SENT_SHIFT 28
@@ -3302,9 +3302,9 @@ typedef ii_icrb0_e_u_t icrbe_t;
3302 */ 3302 */
3303 3303
3304typedef union hubii_wcr_u { 3304typedef union hubii_wcr_u {
3305 uint64_t wcr_reg_value; 3305 u64 wcr_reg_value;
3306 struct { 3306 struct {
3307 uint64_t wcr_widget_id:4, /* LLP crossbar credit */ 3307 u64 wcr_widget_id:4, /* LLP crossbar credit */
3308 wcr_tag_mode:1, /* Tag mode */ 3308 wcr_tag_mode:1, /* Tag mode */
3309 wcr_rsvd1:8, /* Reserved */ 3309 wcr_rsvd1:8, /* Reserved */
3310 wcr_xbar_crd:3, /* LLP crossbar credit */ 3310 wcr_xbar_crd:3, /* LLP crossbar credit */
@@ -3324,9 +3324,9 @@ performance registers */
3324 performed */ 3324 performed */
3325 3325
3326typedef union io_perf_sel { 3326typedef union io_perf_sel {
3327 uint64_t perf_sel_reg; 3327 u64 perf_sel_reg;
3328 struct { 3328 struct {
3329 uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; 3329 u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
3330 } perf_sel_bits; 3330 } perf_sel_bits;
3331} io_perf_sel_t; 3331} io_perf_sel_t;
3332 3332
@@ -3334,24 +3334,24 @@ typedef union io_perf_sel {
3334 hardware problems there is only one counter, not two. */ 3334 hardware problems there is only one counter, not two. */
3335 3335
3336typedef union io_perf_cnt { 3336typedef union io_perf_cnt {
3337 uint64_t perf_cnt; 3337 u64 perf_cnt;
3338 struct { 3338 struct {
3339 uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; 3339 u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
3340 } perf_cnt_bits; 3340 } perf_cnt_bits;
3341 3341
3342} io_perf_cnt_t; 3342} io_perf_cnt_t;
3343 3343
3344typedef union iprte_a { 3344typedef union iprte_a {
3345 uint64_t entry; 3345 u64 entry;
3346 struct { 3346 struct {
3347 uint64_t i_rsvd_1:3; 3347 u64 i_rsvd_1:3;
3348 uint64_t i_addr:38; 3348 u64 i_addr:38;
3349 uint64_t i_init:3; 3349 u64 i_init:3;
3350 uint64_t i_source:8; 3350 u64 i_source:8;
3351 uint64_t i_rsvd:2; 3351 u64 i_rsvd:2;
3352 uint64_t i_widget:4; 3352 u64 i_widget:4;
3353 uint64_t i_to_cnt:5; 3353 u64 i_to_cnt:5;
3354 uint64_t i_vld:1; 3354 u64 i_vld:1;
3355 } iprte_fields; 3355 } iprte_fields;
3356} iprte_a_t; 3356} iprte_a_t;
3357 3357
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index 8b9e10e7cdba..e77f0c9b7d3d 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -273,7 +273,7 @@ ia64_sn_console_putc(char ch)
273 ret_stuff.v0 = 0; 273 ret_stuff.v0 = 0;
274 ret_stuff.v1 = 0; 274 ret_stuff.v1 = 0;
275 ret_stuff.v2 = 0; 275 ret_stuff.v2 = 0;
276 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0); 276 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
277 277
278 return ret_stuff.status; 278 return ret_stuff.status;
279} 279}
@@ -290,7 +290,7 @@ ia64_sn_console_putb(const char *buf, int len)
290 ret_stuff.v0 = 0; 290 ret_stuff.v0 = 0;
291 ret_stuff.v1 = 0; 291 ret_stuff.v1 = 0;
292 ret_stuff.v2 = 0; 292 ret_stuff.v2 = 0;
293 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0); 293 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
294 294
295 if ( ret_stuff.status == 0 ) { 295 if ( ret_stuff.status == 0 ) {
296 return ret_stuff.v0; 296 return ret_stuff.v0;
@@ -310,7 +310,7 @@ ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
310 ret_stuff.v0 = 0; 310 ret_stuff.v0 = 0;
311 ret_stuff.v1 = 0; 311 ret_stuff.v1 = 0;
312 ret_stuff.v2 = 0; 312 ret_stuff.v2 = 0;
313 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); 313 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
314 314
315 return ret_stuff.status; 315 return ret_stuff.status;
316} 316}
@@ -398,7 +398,7 @@ ia64_sn_console_intr_status(void)
398 * Enable an interrupt on the SAL console device. 398 * Enable an interrupt on the SAL console device.
399 */ 399 */
400static inline void 400static inline void
401ia64_sn_console_intr_enable(uint64_t intr) 401ia64_sn_console_intr_enable(u64 intr)
402{ 402{
403 struct ia64_sal_retval ret_stuff; 403 struct ia64_sal_retval ret_stuff;
404 404
@@ -415,7 +415,7 @@ ia64_sn_console_intr_enable(uint64_t intr)
415 * Disable an interrupt on the SAL console device. 415 * Disable an interrupt on the SAL console device.
416 */ 416 */
417static inline void 417static inline void
418ia64_sn_console_intr_disable(uint64_t intr) 418ia64_sn_console_intr_disable(u64 intr)
419{ 419{
420 struct ia64_sal_retval ret_stuff; 420 struct ia64_sal_retval ret_stuff;
421 421
@@ -441,7 +441,7 @@ ia64_sn_console_xmit_chars(char *buf, int len)
441 ret_stuff.v1 = 0; 441 ret_stuff.v1 = 0;
442 ret_stuff.v2 = 0; 442 ret_stuff.v2 = 0;
443 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS, 443 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
444 (uint64_t)buf, (uint64_t)len, 444 (u64)buf, (u64)len,
445 0, 0, 0, 0, 0); 445 0, 0, 0, 0, 0);
446 446
447 if (ret_stuff.status == 0) { 447 if (ret_stuff.status == 0) {
diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h
index bc1aacfb9483..666222d7f0f6 100644
--- a/include/asm-ia64/sn/tioca.h
+++ b/include/asm-ia64/sn/tioca.h
@@ -19,47 +19,47 @@
19 */ 19 */
20 20
21struct tioca { 21struct tioca {
22 uint64_t ca_id; /* 0x000000 */ 22 u64 ca_id; /* 0x000000 */
23 uint64_t ca_control1; /* 0x000008 */ 23 u64 ca_control1; /* 0x000008 */
24 uint64_t ca_control2; /* 0x000010 */ 24 u64 ca_control2; /* 0x000010 */
25 uint64_t ca_status1; /* 0x000018 */ 25 u64 ca_status1; /* 0x000018 */
26 uint64_t ca_status2; /* 0x000020 */ 26 u64 ca_status2; /* 0x000020 */
27 uint64_t ca_gart_aperature; /* 0x000028 */ 27 u64 ca_gart_aperature; /* 0x000028 */
28 uint64_t ca_gfx_detach; /* 0x000030 */ 28 u64 ca_gfx_detach; /* 0x000030 */
29 uint64_t ca_inta_dest_addr; /* 0x000038 */ 29 u64 ca_inta_dest_addr; /* 0x000038 */
30 uint64_t ca_intb_dest_addr; /* 0x000040 */ 30 u64 ca_intb_dest_addr; /* 0x000040 */
31 uint64_t ca_err_int_dest_addr; /* 0x000048 */ 31 u64 ca_err_int_dest_addr; /* 0x000048 */
32 uint64_t ca_int_status; /* 0x000050 */ 32 u64 ca_int_status; /* 0x000050 */
33 uint64_t ca_int_status_alias; /* 0x000058 */ 33 u64 ca_int_status_alias; /* 0x000058 */
34 uint64_t ca_mult_error; /* 0x000060 */ 34 u64 ca_mult_error; /* 0x000060 */
35 uint64_t ca_mult_error_alias; /* 0x000068 */ 35 u64 ca_mult_error_alias; /* 0x000068 */
36 uint64_t ca_first_error; /* 0x000070 */ 36 u64 ca_first_error; /* 0x000070 */
37 uint64_t ca_int_mask; /* 0x000078 */ 37 u64 ca_int_mask; /* 0x000078 */
38 uint64_t ca_crm_pkterr_type; /* 0x000080 */ 38 u64 ca_crm_pkterr_type; /* 0x000080 */
39 uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */ 39 u64 ca_crm_pkterr_type_alias; /* 0x000088 */
40 uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */ 40 u64 ca_crm_ct_error_detail_1; /* 0x000090 */
41 uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */ 41 u64 ca_crm_ct_error_detail_2; /* 0x000098 */
42 uint64_t ca_crm_tnumto; /* 0x0000A0 */ 42 u64 ca_crm_tnumto; /* 0x0000A0 */
43 uint64_t ca_gart_err; /* 0x0000A8 */ 43 u64 ca_gart_err; /* 0x0000A8 */
44 uint64_t ca_pcierr_type; /* 0x0000B0 */ 44 u64 ca_pcierr_type; /* 0x0000B0 */
45 uint64_t ca_pcierr_addr; /* 0x0000B8 */ 45 u64 ca_pcierr_addr; /* 0x0000B8 */
46 46
47 uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */ 47 u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
48 48
49 uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */ 49 u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
50 uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */ 50 u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
51 uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */ 51 u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
52 uint64_t ca_force_inta; /* 0x0000F0 */ 52 u64 ca_force_inta; /* 0x0000F0 */
53 uint64_t ca_force_intb; /* 0x0000F8 */ 53 u64 ca_force_intb; /* 0x0000F8 */
54 uint64_t ca_debug_vector_sel; /* 0x000100 */ 54 u64 ca_debug_vector_sel; /* 0x000100 */
55 uint64_t ca_debug_mux_core_sel; /* 0x000108 */ 55 u64 ca_debug_mux_core_sel; /* 0x000108 */
56 uint64_t ca_debug_mux_pci_sel; /* 0x000110 */ 56 u64 ca_debug_mux_pci_sel; /* 0x000110 */
57 uint64_t ca_debug_domain_sel; /* 0x000118 */ 57 u64 ca_debug_domain_sel; /* 0x000118 */
58 58
59 uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */ 59 u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
60 60
61 uint64_t ca_gart_ptr_table; /* 0x200 */ 61 u64 ca_gart_ptr_table; /* 0x200 */
62 uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */ 62 u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
63}; 63};
64 64
65/* 65/*
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index b532ef6148ed..ab7fe2463468 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -56,31 +56,31 @@ struct tioca_kernel {
56 /* 56 /*
57 * General GART stuff 57 * General GART stuff
58 */ 58 */
59 uint64_t ca_ap_size; /* size of aperature in bytes */ 59 u64 ca_ap_size; /* size of aperature in bytes */
60 uint32_t ca_gart_entries; /* # uint64_t entries in gart */ 60 u32 ca_gart_entries; /* # u64 entries in gart */
61 uint32_t ca_ap_pagesize; /* aperature page size in bytes */ 61 u32 ca_ap_pagesize; /* aperature page size in bytes */
62 uint64_t ca_ap_bus_base; /* bus address of CA aperature */ 62 u64 ca_ap_bus_base; /* bus address of CA aperature */
63 uint64_t ca_gart_size; /* gart size in bytes */ 63 u64 ca_gart_size; /* gart size in bytes */
64 uint64_t *ca_gart; /* gart table vaddr */ 64 u64 *ca_gart; /* gart table vaddr */
65 uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */ 65 u64 ca_gart_coretalk_addr; /* gart coretalk addr */
66 uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */ 66 u8 ca_gart_iscoherent; /* used in tioca_tlbflush */
67 67
68 /* PCI GART convenience values */ 68 /* PCI GART convenience values */
69 uint64_t ca_pciap_base; /* pci aperature bus base address */ 69 u64 ca_pciap_base; /* pci aperature bus base address */
70 uint64_t ca_pciap_size; /* pci aperature size (bytes) */ 70 u64 ca_pciap_size; /* pci aperature size (bytes) */
71 uint64_t ca_pcigart_base; /* gfx GART bus base address */ 71 u64 ca_pcigart_base; /* gfx GART bus base address */
72 uint64_t *ca_pcigart; /* gfx GART vm address */ 72 u64 *ca_pcigart; /* gfx GART vm address */
73 uint32_t ca_pcigart_entries; 73 u32 ca_pcigart_entries;
74 uint32_t ca_pcigart_start; /* PCI start index in ca_gart */ 74 u32 ca_pcigart_start; /* PCI start index in ca_gart */
75 void *ca_pcigart_pagemap; 75 void *ca_pcigart_pagemap;
76 76
77 /* AGP GART convenience values */ 77 /* AGP GART convenience values */
78 uint64_t ca_gfxap_base; /* gfx aperature bus base address */ 78 u64 ca_gfxap_base; /* gfx aperature bus base address */
79 uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */ 79 u64 ca_gfxap_size; /* gfx aperature size (bytes) */
80 uint64_t ca_gfxgart_base; /* gfx GART bus base address */ 80 u64 ca_gfxgart_base; /* gfx GART bus base address */
81 uint64_t *ca_gfxgart; /* gfx GART vm address */ 81 u64 *ca_gfxgart; /* gfx GART vm address */
82 uint32_t ca_gfxgart_entries; 82 u32 ca_gfxgart_entries;
83 uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */ 83 u32 ca_gfxgart_start; /* agpgart start index in ca_gart */
84}; 84};
85 85
86/* 86/*
@@ -93,11 +93,11 @@ struct tioca_kernel {
93struct tioca_common { 93struct tioca_common {
94 struct pcibus_bussoft ca_common; /* common pciio header */ 94 struct pcibus_bussoft ca_common; /* common pciio header */
95 95
96 uint32_t ca_rev; 96 u32 ca_rev;
97 uint32_t ca_closest_nasid; 97 u32 ca_closest_nasid;
98 98
99 uint64_t ca_prom_private; 99 u64 ca_prom_private;
100 uint64_t ca_kernel_private; 100 u64 ca_kernel_private;
101}; 101};
102 102
103/** 103/**
@@ -139,9 +139,9 @@ tioca_paddr_to_gart(unsigned long paddr)
139 */ 139 */
140 140
141static inline unsigned long 141static inline unsigned long
142tioca_physpage_to_gart(uint64_t page_addr) 142tioca_physpage_to_gart(u64 page_addr)
143{ 143{
144 uint64_t coretalk_addr; 144 u64 coretalk_addr;
145 145
146 coretalk_addr = PHYS_TO_TIODMA(page_addr); 146 coretalk_addr = PHYS_TO_TIODMA(page_addr);
147 if (!coretalk_addr) { 147 if (!coretalk_addr) {
@@ -161,7 +161,7 @@ tioca_physpage_to_gart(uint64_t page_addr)
161static inline void 161static inline void
162tioca_tlbflush(struct tioca_kernel *tioca_kernel) 162tioca_tlbflush(struct tioca_kernel *tioca_kernel)
163{ 163{
164 volatile uint64_t tmp; 164 volatile u64 tmp;
165 volatile struct tioca *ca_base; 165 volatile struct tioca *ca_base;
166 struct tioca_common *tioca_common; 166 struct tioca_common *tioca_common;
167 167
@@ -200,7 +200,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
200 tmp = __sn_readq_relaxed(&ca_base->ca_control2); 200 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
201} 201}
202 202
203extern uint32_t tioca_gart_found; 203extern u32 tioca_gart_found;
204extern struct list_head tioca_list; 204extern struct list_head tioca_list;
205extern int tioca_init_provider(void); 205extern int tioca_init_provider(void);
206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern); 206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h
index ecaddf960086..d4c990712eac 100644
--- a/include/asm-ia64/sn/tioce.h
+++ b/include/asm-ia64/sn/tioce.h
@@ -35,72 +35,72 @@ typedef volatile struct tioce {
35 /* 35 /*
36 * ADMIN : Administration Registers 36 * ADMIN : Administration Registers
37 */ 37 */
38 uint64_t ce_adm_id; /* 0x000000 */ 38 u64 ce_adm_id; /* 0x000000 */
39 uint64_t ce_pad_000008; /* 0x000008 */ 39 u64 ce_pad_000008; /* 0x000008 */
40 uint64_t ce_adm_dyn_credit_status; /* 0x000010 */ 40 u64 ce_adm_dyn_credit_status; /* 0x000010 */
41 uint64_t ce_adm_last_credit_status; /* 0x000018 */ 41 u64 ce_adm_last_credit_status; /* 0x000018 */
42 uint64_t ce_adm_credit_limit; /* 0x000020 */ 42 u64 ce_adm_credit_limit; /* 0x000020 */
43 uint64_t ce_adm_force_credit; /* 0x000028 */ 43 u64 ce_adm_force_credit; /* 0x000028 */
44 uint64_t ce_adm_control; /* 0x000030 */ 44 u64 ce_adm_control; /* 0x000030 */
45 uint64_t ce_adm_mmr_chn_timeout; /* 0x000038 */ 45 u64 ce_adm_mmr_chn_timeout; /* 0x000038 */
46 uint64_t ce_adm_ssp_ure_timeout; /* 0x000040 */ 46 u64 ce_adm_ssp_ure_timeout; /* 0x000040 */
47 uint64_t ce_adm_ssp_dre_timeout; /* 0x000048 */ 47 u64 ce_adm_ssp_dre_timeout; /* 0x000048 */
48 uint64_t ce_adm_ssp_debug_sel; /* 0x000050 */ 48 u64 ce_adm_ssp_debug_sel; /* 0x000050 */
49 uint64_t ce_adm_int_status; /* 0x000058 */ 49 u64 ce_adm_int_status; /* 0x000058 */
50 uint64_t ce_adm_int_status_alias; /* 0x000060 */ 50 u64 ce_adm_int_status_alias; /* 0x000060 */
51 uint64_t ce_adm_int_mask; /* 0x000068 */ 51 u64 ce_adm_int_mask; /* 0x000068 */
52 uint64_t ce_adm_int_pending; /* 0x000070 */ 52 u64 ce_adm_int_pending; /* 0x000070 */
53 uint64_t ce_adm_force_int; /* 0x000078 */ 53 u64 ce_adm_force_int; /* 0x000078 */
54 uint64_t ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */ 54 u64 ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
55 uint64_t ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */ 55 u64 ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
56 uint64_t ce_adm_error_summary; /* 0x000100 */ 56 u64 ce_adm_error_summary; /* 0x000100 */
57 uint64_t ce_adm_error_summary_alias; /* 0x000108 */ 57 u64 ce_adm_error_summary_alias; /* 0x000108 */
58 uint64_t ce_adm_error_mask; /* 0x000110 */ 58 u64 ce_adm_error_mask; /* 0x000110 */
59 uint64_t ce_adm_first_error; /* 0x000118 */ 59 u64 ce_adm_first_error; /* 0x000118 */
60 uint64_t ce_adm_error_overflow; /* 0x000120 */ 60 u64 ce_adm_error_overflow; /* 0x000120 */
61 uint64_t ce_adm_error_overflow_alias; /* 0x000128 */ 61 u64 ce_adm_error_overflow_alias; /* 0x000128 */
62 uint64_t ce_pad_000130[2]; /* 0x000130 -- 0x000138 */ 62 u64 ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
63 uint64_t ce_adm_tnum_error; /* 0x000140 */ 63 u64 ce_adm_tnum_error; /* 0x000140 */
64 uint64_t ce_adm_mmr_err_detail; /* 0x000148 */ 64 u64 ce_adm_mmr_err_detail; /* 0x000148 */
65 uint64_t ce_adm_msg_sram_perr_detail; /* 0x000150 */ 65 u64 ce_adm_msg_sram_perr_detail; /* 0x000150 */
66 uint64_t ce_adm_bap_sram_perr_detail; /* 0x000158 */ 66 u64 ce_adm_bap_sram_perr_detail; /* 0x000158 */
67 uint64_t ce_adm_ce_sram_perr_detail; /* 0x000160 */ 67 u64 ce_adm_ce_sram_perr_detail; /* 0x000160 */
68 uint64_t ce_adm_ce_credit_oflow_detail; /* 0x000168 */ 68 u64 ce_adm_ce_credit_oflow_detail; /* 0x000168 */
69 uint64_t ce_adm_tx_link_idle_max_timer; /* 0x000170 */ 69 u64 ce_adm_tx_link_idle_max_timer; /* 0x000170 */
70 uint64_t ce_adm_pcie_debug_sel; /* 0x000178 */ 70 u64 ce_adm_pcie_debug_sel; /* 0x000178 */
71 uint64_t ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */ 71 u64 ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
72 72
73 uint64_t ce_adm_pcie_debug_sel_top; /* 0x000200 */ 73 u64 ce_adm_pcie_debug_sel_top; /* 0x000200 */
74 uint64_t ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */ 74 u64 ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
75 uint64_t ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */ 75 u64 ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
76 uint64_t ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */ 76 u64 ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
77 uint64_t ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */ 77 u64 ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
78 uint64_t ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */ 78 u64 ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
79 uint64_t ce_adm_pcie_trig_compare_top; /* 0x000230 */ 79 u64 ce_adm_pcie_trig_compare_top; /* 0x000230 */
80 uint64_t ce_adm_pcie_trig_compare_en_top; /* 0x000238 */ 80 u64 ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
81 uint64_t ce_adm_ssp_debug_sel_top; /* 0x000240 */ 81 u64 ce_adm_ssp_debug_sel_top; /* 0x000240 */
82 uint64_t ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */ 82 u64 ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
83 uint64_t ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */ 83 u64 ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
84 uint64_t ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */ 84 u64 ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
85 uint64_t ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */ 85 u64 ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
86 uint64_t ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */ 86 u64 ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
87 uint64_t ce_adm_ssp_trig_compare_top; /* 0x000270 */ 87 u64 ce_adm_ssp_trig_compare_top; /* 0x000270 */
88 uint64_t ce_adm_ssp_trig_compare_en_top; /* 0x000278 */ 88 u64 ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
89 uint64_t ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */ 89 u64 ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
90 90
91 uint64_t ce_adm_bap_ctrl; /* 0x000400 */ 91 u64 ce_adm_bap_ctrl; /* 0x000400 */
92 uint64_t ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */ 92 u64 ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
93 93
94 uint64_t ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */ 94 u64 ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
95 uint64_t ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */ 95 u64 ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
96 96
97 uint64_t ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */ 97 u64 ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
98 uint64_t ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */ 98 u64 ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
99 99
100 uint64_t ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */ 100 u64 ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
101 uint64_t ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */ 101 u64 ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
102 102
103 uint64_t ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */ 103 u64 ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
104 104
105 /* 105 /*
106 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2) 106 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
@@ -109,141 +109,141 @@ typedef volatile struct tioce {
109 */ 109 */
110 #define ce_lsi(link_num) ce_lsi[link_num-1] 110 #define ce_lsi(link_num) ce_lsi[link_num-1]
111 struct ce_lsi_reg { 111 struct ce_lsi_reg {
112 uint64_t ce_lsi_lpu_id; /* 0x00z000 */ 112 u64 ce_lsi_lpu_id; /* 0x00z000 */
113 uint64_t ce_lsi_rst; /* 0x00z008 */ 113 u64 ce_lsi_rst; /* 0x00z008 */
114 uint64_t ce_lsi_dbg_stat; /* 0x00z010 */ 114 u64 ce_lsi_dbg_stat; /* 0x00z010 */
115 uint64_t ce_lsi_dbg_cfg; /* 0x00z018 */ 115 u64 ce_lsi_dbg_cfg; /* 0x00z018 */
116 uint64_t ce_lsi_ltssm_ctrl; /* 0x00z020 */ 116 u64 ce_lsi_ltssm_ctrl; /* 0x00z020 */
117 uint64_t ce_lsi_lk_stat; /* 0x00z028 */ 117 u64 ce_lsi_lk_stat; /* 0x00z028 */
118 uint64_t ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */ 118 u64 ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
119 uint64_t ce_lsi_int_and_stat; /* 0x00z040 */ 119 u64 ce_lsi_int_and_stat; /* 0x00z040 */
120 uint64_t ce_lsi_int_mask; /* 0x00z048 */ 120 u64 ce_lsi_int_mask; /* 0x00z048 */
121 uint64_t ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */ 121 u64 ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
122 uint64_t ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */ 122 u64 ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
123 uint64_t ce_pad_00z108; /* 0x00z108 */ 123 u64 ce_pad_00z108; /* 0x00z108 */
124 uint64_t ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */ 124 u64 ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
125 uint64_t ce_pad_00z118; /* 0x00z118 */ 125 u64 ce_pad_00z118; /* 0x00z118 */
126 uint64_t ce_lsi_lk_perf_cnt1; /* 0x00z120 */ 126 u64 ce_lsi_lk_perf_cnt1; /* 0x00z120 */
127 uint64_t ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */ 127 u64 ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
128 uint64_t ce_lsi_lk_perf_cnt2; /* 0x00z130 */ 128 u64 ce_lsi_lk_perf_cnt2; /* 0x00z130 */
129 uint64_t ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */ 129 u64 ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
130 uint64_t ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */ 130 u64 ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
131 uint64_t ce_lsi_lk_lyr_cfg; /* 0x00z200 */ 131 u64 ce_lsi_lk_lyr_cfg; /* 0x00z200 */
132 uint64_t ce_lsi_lk_lyr_status; /* 0x00z208 */ 132 u64 ce_lsi_lk_lyr_status; /* 0x00z208 */
133 uint64_t ce_lsi_lk_lyr_int_stat; /* 0x00z210 */ 133 u64 ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
134 uint64_t ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */ 134 u64 ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
135 uint64_t ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */ 135 u64 ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
136 uint64_t ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */ 136 u64 ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
137 uint64_t ce_lsi_fc_upd_ctl; /* 0x00z240 */ 137 u64 ce_lsi_fc_upd_ctl; /* 0x00z240 */
138 uint64_t ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */ 138 u64 ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
139 uint64_t ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */ 139 u64 ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
140 uint64_t ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */ 140 u64 ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
141 uint64_t ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */ 141 u64 ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
142 uint64_t ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */ 142 u64 ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
143 uint64_t ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */ 143 u64 ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
144 uint64_t ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */ 144 u64 ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
145 uint64_t ce_lsi_rply_tmr_thr; /* 0x00z410 */ 145 u64 ce_lsi_rply_tmr_thr; /* 0x00z410 */
146 uint64_t ce_lsi_rply_tmr; /* 0x00z418 */ 146 u64 ce_lsi_rply_tmr; /* 0x00z418 */
147 uint64_t ce_lsi_rply_num_stat; /* 0x00z420 */ 147 u64 ce_lsi_rply_num_stat; /* 0x00z420 */
148 uint64_t ce_lsi_rty_buf_max_addr; /* 0x00z428 */ 148 u64 ce_lsi_rty_buf_max_addr; /* 0x00z428 */
149 uint64_t ce_lsi_rty_fifo_ptr; /* 0x00z430 */ 149 u64 ce_lsi_rty_fifo_ptr; /* 0x00z430 */
150 uint64_t ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */ 150 u64 ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
151 uint64_t ce_lsi_rty_fifo_cred; /* 0x00z440 */ 151 u64 ce_lsi_rty_fifo_cred; /* 0x00z440 */
152 uint64_t ce_lsi_seq_cnt; /* 0x00z448 */ 152 u64 ce_lsi_seq_cnt; /* 0x00z448 */
153 uint64_t ce_lsi_ack_sent_seq_num; /* 0x00z450 */ 153 u64 ce_lsi_ack_sent_seq_num; /* 0x00z450 */
154 uint64_t ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */ 154 u64 ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
155 uint64_t ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */ 155 u64 ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
156 uint64_t ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */ 156 u64 ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
157 uint64_t ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */ 157 u64 ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
158 uint64_t ce_pad_00z478; /* 0x00z478 */ 158 u64 ce_pad_00z478; /* 0x00z478 */
159 uint64_t ce_lsi_mem_addr_ctl; /* 0x00z480 */ 159 u64 ce_lsi_mem_addr_ctl; /* 0x00z480 */
160 uint64_t ce_lsi_mem_d_ld0; /* 0x00z488 */ 160 u64 ce_lsi_mem_d_ld0; /* 0x00z488 */
161 uint64_t ce_lsi_mem_d_ld1; /* 0x00z490 */ 161 u64 ce_lsi_mem_d_ld1; /* 0x00z490 */
162 uint64_t ce_lsi_mem_d_ld2; /* 0x00z498 */ 162 u64 ce_lsi_mem_d_ld2; /* 0x00z498 */
163 uint64_t ce_lsi_mem_d_ld3; /* 0x00z4A0 */ 163 u64 ce_lsi_mem_d_ld3; /* 0x00z4A0 */
164 uint64_t ce_lsi_mem_d_ld4; /* 0x00z4A8 */ 164 u64 ce_lsi_mem_d_ld4; /* 0x00z4A8 */
165 uint64_t ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */ 165 u64 ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
166 uint64_t ce_lsi_rty_d_cnt; /* 0x00z4C0 */ 166 u64 ce_lsi_rty_d_cnt; /* 0x00z4C0 */
167 uint64_t ce_lsi_seq_buf_cnt; /* 0x00z4C8 */ 167 u64 ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
168 uint64_t ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */ 168 u64 ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
169 uint64_t ce_pad_00z4D8; /* 0x00z4D8 */ 169 u64 ce_pad_00z4D8; /* 0x00z4D8 */
170 uint64_t ce_lsi_ack_lat_thr; /* 0x00z4E0 */ 170 u64 ce_lsi_ack_lat_thr; /* 0x00z4E0 */
171 uint64_t ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */ 171 u64 ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
172 uint64_t ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */ 172 u64 ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
173 uint64_t ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */ 173 u64 ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
174 uint64_t ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */ 174 u64 ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
175 uint64_t ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */ 175 u64 ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
176 uint64_t ce_lsi_phy_lyr_cfg; /* 0x00z600 */ 176 u64 ce_lsi_phy_lyr_cfg; /* 0x00z600 */
177 uint64_t ce_pad_00z608; /* 0x00z608 */ 177 u64 ce_pad_00z608; /* 0x00z608 */
178 uint64_t ce_lsi_phy_lyr_int_stat; /* 0x00z610 */ 178 u64 ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
179 uint64_t ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */ 179 u64 ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
180 uint64_t ce_lsi_phy_lyr_int_mask; /* 0x00z620 */ 180 u64 ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
181 uint64_t ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */ 181 u64 ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
182 uint64_t ce_lsi_rcv_phy_cfg; /* 0x00z680 */ 182 u64 ce_lsi_rcv_phy_cfg; /* 0x00z680 */
183 uint64_t ce_lsi_rcv_phy_stat1; /* 0x00z688 */ 183 u64 ce_lsi_rcv_phy_stat1; /* 0x00z688 */
184 uint64_t ce_lsi_rcv_phy_stat2; /* 0x00z690 */ 184 u64 ce_lsi_rcv_phy_stat2; /* 0x00z690 */
185 uint64_t ce_lsi_rcv_phy_stat3; /* 0x00z698 */ 185 u64 ce_lsi_rcv_phy_stat3; /* 0x00z698 */
186 uint64_t ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */ 186 u64 ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
187 uint64_t ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */ 187 u64 ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
188 uint64_t ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */ 188 u64 ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
189 uint64_t ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */ 189 u64 ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
190 uint64_t ce_lsi_tx_phy_cfg; /* 0x00z700 */ 190 u64 ce_lsi_tx_phy_cfg; /* 0x00z700 */
191 uint64_t ce_lsi_tx_phy_stat; /* 0x00z708 */ 191 u64 ce_lsi_tx_phy_stat; /* 0x00z708 */
192 uint64_t ce_lsi_tx_phy_int_stat; /* 0x00z710 */ 192 u64 ce_lsi_tx_phy_int_stat; /* 0x00z710 */
193 uint64_t ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */ 193 u64 ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
194 uint64_t ce_lsi_tx_phy_int_mask; /* 0x00z720 */ 194 u64 ce_lsi_tx_phy_int_mask; /* 0x00z720 */
195 uint64_t ce_lsi_tx_phy_stat2; /* 0x00z728 */ 195 u64 ce_lsi_tx_phy_stat2; /* 0x00z728 */
196 uint64_t ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */ 196 u64 ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
197 uint64_t ce_lsi_ltssm_cfg1; /* 0x00z780 */ 197 u64 ce_lsi_ltssm_cfg1; /* 0x00z780 */
198 uint64_t ce_lsi_ltssm_cfg2; /* 0x00z788 */ 198 u64 ce_lsi_ltssm_cfg2; /* 0x00z788 */
199 uint64_t ce_lsi_ltssm_cfg3; /* 0x00z790 */ 199 u64 ce_lsi_ltssm_cfg3; /* 0x00z790 */
200 uint64_t ce_lsi_ltssm_cfg4; /* 0x00z798 */ 200 u64 ce_lsi_ltssm_cfg4; /* 0x00z798 */
201 uint64_t ce_lsi_ltssm_cfg5; /* 0x00z7A0 */ 201 u64 ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
202 uint64_t ce_lsi_ltssm_stat1; /* 0x00z7A8 */ 202 u64 ce_lsi_ltssm_stat1; /* 0x00z7A8 */
203 uint64_t ce_lsi_ltssm_stat2; /* 0x00z7B0 */ 203 u64 ce_lsi_ltssm_stat2; /* 0x00z7B0 */
204 uint64_t ce_lsi_ltssm_int_stat; /* 0x00z7B8 */ 204 u64 ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
205 uint64_t ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */ 205 u64 ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
206 uint64_t ce_lsi_ltssm_int_mask; /* 0x00z7C8 */ 206 u64 ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
207 uint64_t ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */ 207 u64 ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
208 uint64_t ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */ 208 u64 ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
209 uint64_t ce_lsi_gb_cfg1; /* 0x00z800 */ 209 u64 ce_lsi_gb_cfg1; /* 0x00z800 */
210 uint64_t ce_lsi_gb_cfg2; /* 0x00z808 */ 210 u64 ce_lsi_gb_cfg2; /* 0x00z808 */
211 uint64_t ce_lsi_gb_cfg3; /* 0x00z810 */ 211 u64 ce_lsi_gb_cfg3; /* 0x00z810 */
212 uint64_t ce_lsi_gb_cfg4; /* 0x00z818 */ 212 u64 ce_lsi_gb_cfg4; /* 0x00z818 */
213 uint64_t ce_lsi_gb_stat; /* 0x00z820 */ 213 u64 ce_lsi_gb_stat; /* 0x00z820 */
214 uint64_t ce_lsi_gb_int_stat; /* 0x00z828 */ 214 u64 ce_lsi_gb_int_stat; /* 0x00z828 */
215 uint64_t ce_lsi_gb_int_stat_test; /* 0x00z830 */ 215 u64 ce_lsi_gb_int_stat_test; /* 0x00z830 */
216 uint64_t ce_lsi_gb_int_mask; /* 0x00z838 */ 216 u64 ce_lsi_gb_int_mask; /* 0x00z838 */
217 uint64_t ce_lsi_gb_pwr_dn1; /* 0x00z840 */ 217 u64 ce_lsi_gb_pwr_dn1; /* 0x00z840 */
218 uint64_t ce_lsi_gb_pwr_dn2; /* 0x00z848 */ 218 u64 ce_lsi_gb_pwr_dn2; /* 0x00z848 */
219 uint64_t ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */ 219 u64 ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
220 } ce_lsi[2]; 220 } ce_lsi[2];
221 221
222 uint64_t ce_pad_004000[10]; /* 0x004000 -- 0x004048 */ 222 u64 ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
223 223
224 /* 224 /*
225 * CRM: Coretalk Receive Module Registers 225 * CRM: Coretalk Receive Module Registers
226 */ 226 */
227 uint64_t ce_crm_debug_mux; /* 0x004050 */ 227 u64 ce_crm_debug_mux; /* 0x004050 */
228 uint64_t ce_pad_004058; /* 0x004058 */ 228 u64 ce_pad_004058; /* 0x004058 */
229 uint64_t ce_crm_ssp_err_cmd_wrd; /* 0x004060 */ 229 u64 ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
230 uint64_t ce_crm_ssp_err_addr; /* 0x004068 */ 230 u64 ce_crm_ssp_err_addr; /* 0x004068 */
231 uint64_t ce_crm_ssp_err_syn; /* 0x004070 */ 231 u64 ce_crm_ssp_err_syn; /* 0x004070 */
232 232
233 uint64_t ce_pad_004078[499]; /* 0x004078 -- 0x005008 */ 233 u64 ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
234 234
235 /* 235 /*
236 * CXM: Coretalk Xmit Module Registers 236 * CXM: Coretalk Xmit Module Registers
237 */ 237 */
238 uint64_t ce_cxm_dyn_credit_status; /* 0x005010 */ 238 u64 ce_cxm_dyn_credit_status; /* 0x005010 */
239 uint64_t ce_cxm_last_credit_status; /* 0x005018 */ 239 u64 ce_cxm_last_credit_status; /* 0x005018 */
240 uint64_t ce_cxm_credit_limit; /* 0x005020 */ 240 u64 ce_cxm_credit_limit; /* 0x005020 */
241 uint64_t ce_cxm_force_credit; /* 0x005028 */ 241 u64 ce_cxm_force_credit; /* 0x005028 */
242 uint64_t ce_cxm_disable_bypass; /* 0x005030 */ 242 u64 ce_cxm_disable_bypass; /* 0x005030 */
243 uint64_t ce_pad_005038[3]; /* 0x005038 -- 0x005048 */ 243 u64 ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
244 uint64_t ce_cxm_debug_mux; /* 0x005050 */ 244 u64 ce_cxm_debug_mux; /* 0x005050 */
245 245
246 uint64_t ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */ 246 u64 ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
247 247
248 /* 248 /*
249 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2) 249 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
@@ -258,209 +258,209 @@ typedef volatile struct tioce {
258 #define ce_utl(link_num) ce_dtl_utl[link_num-1] 258 #define ce_utl(link_num) ce_dtl_utl[link_num-1]
259 struct ce_dtl_utl_reg { 259 struct ce_dtl_utl_reg {
260 /* DTL */ 260 /* DTL */
261 uint64_t ce_dtl_dtdr_credit_limit; /* 0x00y000 */ 261 u64 ce_dtl_dtdr_credit_limit; /* 0x00y000 */
262 uint64_t ce_dtl_dtdr_credit_force; /* 0x00y008 */ 262 u64 ce_dtl_dtdr_credit_force; /* 0x00y008 */
263 uint64_t ce_dtl_dyn_credit_status; /* 0x00y010 */ 263 u64 ce_dtl_dyn_credit_status; /* 0x00y010 */
264 uint64_t ce_dtl_dtl_last_credit_stat; /* 0x00y018 */ 264 u64 ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
265 uint64_t ce_dtl_dtl_ctrl; /* 0x00y020 */ 265 u64 ce_dtl_dtl_ctrl; /* 0x00y020 */
266 uint64_t ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */ 266 u64 ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
267 uint64_t ce_dtl_debug_sel; /* 0x00y050 */ 267 u64 ce_dtl_debug_sel; /* 0x00y050 */
268 uint64_t ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */ 268 u64 ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
269 269
270 /* UTL */ 270 /* UTL */
271 uint64_t ce_utl_utl_ctrl; /* 0x00z000 */ 271 u64 ce_utl_utl_ctrl; /* 0x00z000 */
272 uint64_t ce_utl_debug_sel; /* 0x00z008 */ 272 u64 ce_utl_debug_sel; /* 0x00z008 */
273 uint64_t ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */ 273 u64 ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
274 } ce_dtl_utl[2]; 274 } ce_dtl_utl[2];
275 275
276 uint64_t ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */ 276 u64 ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
277 277
278 /* 278 /*
279 * URE: Upstream Request Engine 279 * URE: Upstream Request Engine
280 */ 280 */
281 uint64_t ce_ure_dyn_credit_status; /* 0x00B010 */ 281 u64 ce_ure_dyn_credit_status; /* 0x00B010 */
282 uint64_t ce_ure_last_credit_status; /* 0x00B018 */ 282 u64 ce_ure_last_credit_status; /* 0x00B018 */
283 uint64_t ce_ure_credit_limit; /* 0x00B020 */ 283 u64 ce_ure_credit_limit; /* 0x00B020 */
284 uint64_t ce_pad_00B028; /* 0x00B028 */ 284 u64 ce_pad_00B028; /* 0x00B028 */
285 uint64_t ce_ure_control; /* 0x00B030 */ 285 u64 ce_ure_control; /* 0x00B030 */
286 uint64_t ce_ure_status; /* 0x00B038 */ 286 u64 ce_ure_status; /* 0x00B038 */
287 uint64_t ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */ 287 u64 ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
288 uint64_t ce_ure_debug_sel; /* 0x00B050 */ 288 u64 ce_ure_debug_sel; /* 0x00B050 */
289 uint64_t ce_ure_pcie_debug_sel; /* 0x00B058 */ 289 u64 ce_ure_pcie_debug_sel; /* 0x00B058 */
290 uint64_t ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */ 290 u64 ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
291 uint64_t ce_ure_ssp_err_addr; /* 0x00B068 */ 291 u64 ce_ure_ssp_err_addr; /* 0x00B068 */
292 uint64_t ce_ure_page_map; /* 0x00B070 */ 292 u64 ce_ure_page_map; /* 0x00B070 */
293 uint64_t ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */ 293 u64 ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
294 uint64_t ce_ure_pipe_sel1; /* 0x00B088 */ 294 u64 ce_ure_pipe_sel1; /* 0x00B088 */
295 uint64_t ce_ure_pipe_mask1; /* 0x00B090 */ 295 u64 ce_ure_pipe_mask1; /* 0x00B090 */
296 uint64_t ce_ure_pipe_sel2; /* 0x00B098 */ 296 u64 ce_ure_pipe_sel2; /* 0x00B098 */
297 uint64_t ce_ure_pipe_mask2; /* 0x00B0A0 */ 297 u64 ce_ure_pipe_mask2; /* 0x00B0A0 */
298 uint64_t ce_ure_pcie1_credits_sent; /* 0x00B0A8 */ 298 u64 ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
299 uint64_t ce_ure_pcie1_credits_used; /* 0x00B0B0 */ 299 u64 ce_ure_pcie1_credits_used; /* 0x00B0B0 */
300 uint64_t ce_ure_pcie1_credit_limit; /* 0x00B0B8 */ 300 u64 ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
301 uint64_t ce_ure_pcie2_credits_sent; /* 0x00B0C0 */ 301 u64 ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
302 uint64_t ce_ure_pcie2_credits_used; /* 0x00B0C8 */ 302 u64 ce_ure_pcie2_credits_used; /* 0x00B0C8 */
303 uint64_t ce_ure_pcie2_credit_limit; /* 0x00B0D0 */ 303 u64 ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
304 uint64_t ce_ure_pcie_force_credit; /* 0x00B0D8 */ 304 u64 ce_ure_pcie_force_credit; /* 0x00B0D8 */
305 uint64_t ce_ure_rd_tnum_val; /* 0x00B0E0 */ 305 u64 ce_ure_rd_tnum_val; /* 0x00B0E0 */
306 uint64_t ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */ 306 u64 ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
307 uint64_t ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */ 307 u64 ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
308 uint64_t ce_ure_rd_tnum_error; /* 0x00B0F8 */ 308 u64 ce_ure_rd_tnum_error; /* 0x00B0F8 */
309 uint64_t ce_ure_rd_tnum_first_cl; /* 0x00B100 */ 309 u64 ce_ure_rd_tnum_first_cl; /* 0x00B100 */
310 uint64_t ce_ure_rd_tnum_link_buf; /* 0x00B108 */ 310 u64 ce_ure_rd_tnum_link_buf; /* 0x00B108 */
311 uint64_t ce_ure_wr_tnum_val; /* 0x00B110 */ 311 u64 ce_ure_wr_tnum_val; /* 0x00B110 */
312 uint64_t ce_ure_sram_err_addr0; /* 0x00B118 */ 312 u64 ce_ure_sram_err_addr0; /* 0x00B118 */
313 uint64_t ce_ure_sram_err_addr1; /* 0x00B120 */ 313 u64 ce_ure_sram_err_addr1; /* 0x00B120 */
314 uint64_t ce_ure_sram_err_addr2; /* 0x00B128 */ 314 u64 ce_ure_sram_err_addr2; /* 0x00B128 */
315 uint64_t ce_ure_sram_rd_addr0; /* 0x00B130 */ 315 u64 ce_ure_sram_rd_addr0; /* 0x00B130 */
316 uint64_t ce_ure_sram_rd_addr1; /* 0x00B138 */ 316 u64 ce_ure_sram_rd_addr1; /* 0x00B138 */
317 uint64_t ce_ure_sram_rd_addr2; /* 0x00B140 */ 317 u64 ce_ure_sram_rd_addr2; /* 0x00B140 */
318 uint64_t ce_ure_sram_wr_addr0; /* 0x00B148 */ 318 u64 ce_ure_sram_wr_addr0; /* 0x00B148 */
319 uint64_t ce_ure_sram_wr_addr1; /* 0x00B150 */ 319 u64 ce_ure_sram_wr_addr1; /* 0x00B150 */
320 uint64_t ce_ure_sram_wr_addr2; /* 0x00B158 */ 320 u64 ce_ure_sram_wr_addr2; /* 0x00B158 */
321 uint64_t ce_ure_buf_flush10; /* 0x00B160 */ 321 u64 ce_ure_buf_flush10; /* 0x00B160 */
322 uint64_t ce_ure_buf_flush11; /* 0x00B168 */ 322 u64 ce_ure_buf_flush11; /* 0x00B168 */
323 uint64_t ce_ure_buf_flush12; /* 0x00B170 */ 323 u64 ce_ure_buf_flush12; /* 0x00B170 */
324 uint64_t ce_ure_buf_flush13; /* 0x00B178 */ 324 u64 ce_ure_buf_flush13; /* 0x00B178 */
325 uint64_t ce_ure_buf_flush20; /* 0x00B180 */ 325 u64 ce_ure_buf_flush20; /* 0x00B180 */
326 uint64_t ce_ure_buf_flush21; /* 0x00B188 */ 326 u64 ce_ure_buf_flush21; /* 0x00B188 */
327 uint64_t ce_ure_buf_flush22; /* 0x00B190 */ 327 u64 ce_ure_buf_flush22; /* 0x00B190 */
328 uint64_t ce_ure_buf_flush23; /* 0x00B198 */ 328 u64 ce_ure_buf_flush23; /* 0x00B198 */
329 uint64_t ce_ure_pcie_control1; /* 0x00B1A0 */ 329 u64 ce_ure_pcie_control1; /* 0x00B1A0 */
330 uint64_t ce_ure_pcie_control2; /* 0x00B1A8 */ 330 u64 ce_ure_pcie_control2; /* 0x00B1A8 */
331 331
332 uint64_t ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */ 332 u64 ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
333 333
334 /* Upstream Data Buffer, Port1 */ 334 /* Upstream Data Buffer, Port1 */
335 struct ce_ure_maint_ups_dat1_data { 335 struct ce_ure_maint_ups_dat1_data {
336 uint64_t data63_0[512]; /* 0x00C000 -- 0x00CFF8 */ 336 u64 data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
337 uint64_t data127_64[512]; /* 0x00D000 -- 0x00DFF8 */ 337 u64 data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
338 uint64_t parity[512]; /* 0x00E000 -- 0x00EFF8 */ 338 u64 parity[512]; /* 0x00E000 -- 0x00EFF8 */
339 } ce_ure_maint_ups_dat1; 339 } ce_ure_maint_ups_dat1;
340 340
341 /* Upstream Header Buffer, Port1 */ 341 /* Upstream Header Buffer, Port1 */
342 struct ce_ure_maint_ups_hdr1_data { 342 struct ce_ure_maint_ups_hdr1_data {
343 uint64_t data63_0[512]; /* 0x00F000 -- 0x00FFF8 */ 343 u64 data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
344 uint64_t data127_64[512]; /* 0x010000 -- 0x010FF8 */ 344 u64 data127_64[512]; /* 0x010000 -- 0x010FF8 */
345 uint64_t parity[512]; /* 0x011000 -- 0x011FF8 */ 345 u64 parity[512]; /* 0x011000 -- 0x011FF8 */
346 } ce_ure_maint_ups_hdr1; 346 } ce_ure_maint_ups_hdr1;
347 347
348 /* Upstream Data Buffer, Port2 */ 348 /* Upstream Data Buffer, Port2 */
349 struct ce_ure_maint_ups_dat2_data { 349 struct ce_ure_maint_ups_dat2_data {
350 uint64_t data63_0[512]; /* 0x012000 -- 0x012FF8 */ 350 u64 data63_0[512]; /* 0x012000 -- 0x012FF8 */
351 uint64_t data127_64[512]; /* 0x013000 -- 0x013FF8 */ 351 u64 data127_64[512]; /* 0x013000 -- 0x013FF8 */
352 uint64_t parity[512]; /* 0x014000 -- 0x014FF8 */ 352 u64 parity[512]; /* 0x014000 -- 0x014FF8 */
353 } ce_ure_maint_ups_dat2; 353 } ce_ure_maint_ups_dat2;
354 354
355 /* Upstream Header Buffer, Port2 */ 355 /* Upstream Header Buffer, Port2 */
356 struct ce_ure_maint_ups_hdr2_data { 356 struct ce_ure_maint_ups_hdr2_data {
357 uint64_t data63_0[512]; /* 0x015000 -- 0x015FF8 */ 357 u64 data63_0[512]; /* 0x015000 -- 0x015FF8 */
358 uint64_t data127_64[512]; /* 0x016000 -- 0x016FF8 */ 358 u64 data127_64[512]; /* 0x016000 -- 0x016FF8 */
359 uint64_t parity[512]; /* 0x017000 -- 0x017FF8 */ 359 u64 parity[512]; /* 0x017000 -- 0x017FF8 */
360 } ce_ure_maint_ups_hdr2; 360 } ce_ure_maint_ups_hdr2;
361 361
362 /* Downstream Data Buffer */ 362 /* Downstream Data Buffer */
363 struct ce_ure_maint_dns_dat_data { 363 struct ce_ure_maint_dns_dat_data {
364 uint64_t data63_0[512]; /* 0x018000 -- 0x018FF8 */ 364 u64 data63_0[512]; /* 0x018000 -- 0x018FF8 */
365 uint64_t data127_64[512]; /* 0x019000 -- 0x019FF8 */ 365 u64 data127_64[512]; /* 0x019000 -- 0x019FF8 */
366 uint64_t parity[512]; /* 0x01A000 -- 0x01AFF8 */ 366 u64 parity[512]; /* 0x01A000 -- 0x01AFF8 */
367 } ce_ure_maint_dns_dat; 367 } ce_ure_maint_dns_dat;
368 368
369 /* Downstream Header Buffer */ 369 /* Downstream Header Buffer */
370 struct ce_ure_maint_dns_hdr_data { 370 struct ce_ure_maint_dns_hdr_data {
371 uint64_t data31_0[64]; /* 0x01B000 -- 0x01B1F8 */ 371 u64 data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
372 uint64_t data95_32[64]; /* 0x01B200 -- 0x01B3F8 */ 372 u64 data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
373 uint64_t parity[64]; /* 0x01B400 -- 0x01B5F8 */ 373 u64 parity[64]; /* 0x01B400 -- 0x01B5F8 */
374 } ce_ure_maint_dns_hdr; 374 } ce_ure_maint_dns_hdr;
375 375
376 /* RCI Buffer Data */ 376 /* RCI Buffer Data */
377 struct ce_ure_maint_rci_data { 377 struct ce_ure_maint_rci_data {
378 uint64_t data41_0[64]; /* 0x01B600 -- 0x01B7F8 */ 378 u64 data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
379 uint64_t data69_42[64]; /* 0x01B800 -- 0x01B9F8 */ 379 u64 data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
380 } ce_ure_maint_rci; 380 } ce_ure_maint_rci;
381 381
382 /* Response Queue */ 382 /* Response Queue */
383 uint64_t ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */ 383 u64 ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
384 384
385 uint64_t ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */ 385 u64 ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
386 386
387 /* Admin Build-a-Packet Buffer */ 387 /* Admin Build-a-Packet Buffer */
388 struct ce_adm_maint_bap_buf_data { 388 struct ce_adm_maint_bap_buf_data {
389 uint64_t data63_0[258]; /* 0x024000 -- 0x024808 */ 389 u64 data63_0[258]; /* 0x024000 -- 0x024808 */
390 uint64_t data127_64[258]; /* 0x024810 -- 0x025018 */ 390 u64 data127_64[258]; /* 0x024810 -- 0x025018 */
391 uint64_t parity[258]; /* 0x025020 -- 0x025828 */ 391 u64 parity[258]; /* 0x025020 -- 0x025828 */
392 } ce_adm_maint_bap_buf; 392 } ce_adm_maint_bap_buf;
393 393
394 uint64_t ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */ 394 u64 ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
395 395
396 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */ 396 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
397 uint64_t ce_ure_ate40[TIOCE_NUM_M40_ATES]; 397 u64 ce_ure_ate40[TIOCE_NUM_M40_ATES];
398 398
399 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */ 399 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
400 uint64_t ce_ure_ate3240[TIOCE_NUM_M3240_ATES]; 400 u64 ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
401 401
402 uint64_t ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */ 402 u64 ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
403 403
404 /* 404 /*
405 * DRE: Down Stream Request Engine 405 * DRE: Down Stream Request Engine
406 */ 406 */
407 uint64_t ce_dre_dyn_credit_status1; /* 0x040010 */ 407 u64 ce_dre_dyn_credit_status1; /* 0x040010 */
408 uint64_t ce_dre_dyn_credit_status2; /* 0x040018 */ 408 u64 ce_dre_dyn_credit_status2; /* 0x040018 */
409 uint64_t ce_dre_last_credit_status1; /* 0x040020 */ 409 u64 ce_dre_last_credit_status1; /* 0x040020 */
410 uint64_t ce_dre_last_credit_status2; /* 0x040028 */ 410 u64 ce_dre_last_credit_status2; /* 0x040028 */
411 uint64_t ce_dre_credit_limit1; /* 0x040030 */ 411 u64 ce_dre_credit_limit1; /* 0x040030 */
412 uint64_t ce_dre_credit_limit2; /* 0x040038 */ 412 u64 ce_dre_credit_limit2; /* 0x040038 */
413 uint64_t ce_dre_force_credit1; /* 0x040040 */ 413 u64 ce_dre_force_credit1; /* 0x040040 */
414 uint64_t ce_dre_force_credit2; /* 0x040048 */ 414 u64 ce_dre_force_credit2; /* 0x040048 */
415 uint64_t ce_dre_debug_mux1; /* 0x040050 */ 415 u64 ce_dre_debug_mux1; /* 0x040050 */
416 uint64_t ce_dre_debug_mux2; /* 0x040058 */ 416 u64 ce_dre_debug_mux2; /* 0x040058 */
417 uint64_t ce_dre_ssp_err_cmd_wrd; /* 0x040060 */ 417 u64 ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
418 uint64_t ce_dre_ssp_err_addr; /* 0x040068 */ 418 u64 ce_dre_ssp_err_addr; /* 0x040068 */
419 uint64_t ce_dre_comp_err_cmd_wrd; /* 0x040070 */ 419 u64 ce_dre_comp_err_cmd_wrd; /* 0x040070 */
420 uint64_t ce_dre_comp_err_addr; /* 0x040078 */ 420 u64 ce_dre_comp_err_addr; /* 0x040078 */
421 uint64_t ce_dre_req_status; /* 0x040080 */ 421 u64 ce_dre_req_status; /* 0x040080 */
422 uint64_t ce_dre_config1; /* 0x040088 */ 422 u64 ce_dre_config1; /* 0x040088 */
423 uint64_t ce_dre_config2; /* 0x040090 */ 423 u64 ce_dre_config2; /* 0x040090 */
424 uint64_t ce_dre_config_req_status; /* 0x040098 */ 424 u64 ce_dre_config_req_status; /* 0x040098 */
425 uint64_t ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */ 425 u64 ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
426 uint64_t ce_dre_dyn_fifo; /* 0x040100 */ 426 u64 ce_dre_dyn_fifo; /* 0x040100 */
427 uint64_t ce_pad_040108[3]; /* 0x040108 -- 0x040118 */ 427 u64 ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
428 uint64_t ce_dre_last_fifo; /* 0x040120 */ 428 u64 ce_dre_last_fifo; /* 0x040120 */
429 429
430 uint64_t ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */ 430 u64 ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
431 431
432 /* DRE Downstream Head Queue */ 432 /* DRE Downstream Head Queue */
433 struct ce_dre_maint_ds_head_queue { 433 struct ce_dre_maint_ds_head_queue {
434 uint64_t data63_0[32]; /* 0x040200 -- 0x0402F8 */ 434 u64 data63_0[32]; /* 0x040200 -- 0x0402F8 */
435 uint64_t data127_64[32]; /* 0x040300 -- 0x0403F8 */ 435 u64 data127_64[32]; /* 0x040300 -- 0x0403F8 */
436 uint64_t parity[32]; /* 0x040400 -- 0x0404F8 */ 436 u64 parity[32]; /* 0x040400 -- 0x0404F8 */
437 } ce_dre_maint_ds_head_q; 437 } ce_dre_maint_ds_head_q;
438 438
439 uint64_t ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */ 439 u64 ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
440 440
441 /* DRE Downstream Data Queue */ 441 /* DRE Downstream Data Queue */
442 struct ce_dre_maint_ds_data_queue { 442 struct ce_dre_maint_ds_data_queue {
443 uint64_t data63_0[256]; /* 0x041000 -- 0x0417F8 */ 443 u64 data63_0[256]; /* 0x041000 -- 0x0417F8 */
444 uint64_t ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */ 444 u64 ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
445 uint64_t data127_64[256]; /* 0x042000 -- 0x0427F8 */ 445 u64 data127_64[256]; /* 0x042000 -- 0x0427F8 */
446 uint64_t ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */ 446 u64 ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
447 uint64_t parity[256]; /* 0x043000 -- 0x0437F8 */ 447 u64 parity[256]; /* 0x043000 -- 0x0437F8 */
448 uint64_t ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */ 448 u64 ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
449 } ce_dre_maint_ds_data_q; 449 } ce_dre_maint_ds_data_q;
450 450
451 /* DRE URE Upstream Response Queue */ 451 /* DRE URE Upstream Response Queue */
452 struct ce_dre_maint_ure_us_rsp_queue { 452 struct ce_dre_maint_ure_us_rsp_queue {
453 uint64_t data63_0[8]; /* 0x044000 -- 0x044038 */ 453 u64 data63_0[8]; /* 0x044000 -- 0x044038 */
454 uint64_t ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */ 454 u64 ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
455 uint64_t data127_64[8]; /* 0x044100 -- 0x044138 */ 455 u64 data127_64[8]; /* 0x044100 -- 0x044138 */
456 uint64_t ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */ 456 u64 ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
457 uint64_t parity[8]; /* 0x044200 -- 0x044238 */ 457 u64 parity[8]; /* 0x044200 -- 0x044238 */
458 uint64_t ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */ 458 u64 ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
459 } ce_dre_maint_ure_us_rsp_q; 459 } ce_dre_maint_ure_us_rsp_q;
460 460
461 uint64_t ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */ 461 u64 ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
462 462
463 uint64_t ce_end_of_struct; /* 0x044400 */ 463 u64 ce_end_of_struct; /* 0x044400 */
464} tioce_t; 464} tioce_t;
465 465
466 466
@@ -625,11 +625,11 @@ typedef volatile struct tioce {
625#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT) 625#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
626#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT) 626#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
627#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT) 627#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
628#define CE_URE_PIPE_BUS(b) (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \ 628#define CE_URE_PIPE_BUS(b) (((u64)(b) << BUS_SRC_ID_SHFT) & \
629 CE_URE_BUS_MASK) 629 CE_URE_BUS_MASK)
630#define CE_URE_PIPE_DEV(d) (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \ 630#define CE_URE_PIPE_DEV(d) (((u64)(d) << DEV_SRC_ID_SHFT) & \
631 CE_URE_DEV_MASK) 631 CE_URE_DEV_MASK)
632#define CE_URE_PIPE_FNC(f) (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \ 632#define CE_URE_PIPE_FNC(f) (((u64)(f) << FNC_SRC_ID_SHFT) & \
633 CE_URE_FNC_MASK) 633 CE_URE_FNC_MASK)
634 634
635#define CE_URE_SEL1_SHFT 0 635#define CE_URE_SEL1_SHFT 0
@@ -660,9 +660,9 @@ typedef volatile struct tioce {
660#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT) 660#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
661#define CE_URE_PN2_SHFT 24 661#define CE_URE_PN2_SHFT 24
662#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT) 662#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
663#define CE_URE_PN1_SET(n) (((uint64_t)(n) << CE_URE_PN1_SHFT) & \ 663#define CE_URE_PN1_SET(n) (((u64)(n) << CE_URE_PN1_SHFT) & \
664 CE_URE_PN1_MASK) 664 CE_URE_PN1_MASK)
665#define CE_URE_PN2_SET(n) (((uint64_t)(n) << CE_URE_PN2_SHFT) & \ 665#define CE_URE_PN2_SET(n) (((u64)(n) << CE_URE_PN2_SHFT) & \
666 CE_URE_PN2_MASK) 666 CE_URE_PN2_MASK)
667 667
668/* ce_ure_pcie_control2 register bit masks & shifts */ 668/* ce_ure_pcie_control2 register bit masks & shifts */
@@ -681,9 +681,9 @@ typedef volatile struct tioce {
681#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT) 681#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
682#define CE_URE_PSN2_SHFT 32 682#define CE_URE_PSN2_SHFT 32
683#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT) 683#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
684#define CE_URE_PSN1_SET(n) (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \ 684#define CE_URE_PSN1_SET(n) (((u64)(n) << CE_URE_PSN1_SHFT) & \
685 CE_URE_PSN1_MASK) 685 CE_URE_PSN1_MASK)
686#define CE_URE_PSN2_SET(n) (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \ 686#define CE_URE_PSN2_SET(n) (((u64)(n) << CE_URE_PSN2_SHFT) & \
687 CE_URE_PSN2_MASK) 687 CE_URE_PSN2_MASK)
688 688
689/* 689/*
diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h
index cb414908671d..6d62b13f7ae7 100644
--- a/include/asm-ia64/sn/tioce_provider.h
+++ b/include/asm-ia64/sn/tioce_provider.h
@@ -21,9 +21,9 @@
21struct tioce_common { 21struct tioce_common {
22 struct pcibus_bussoft ce_pcibus; /* common pciio header */ 22 struct pcibus_bussoft ce_pcibus; /* common pciio header */
23 23
24 uint32_t ce_rev; 24 u32 ce_rev;
25 uint64_t ce_kernel_private; 25 u64 ce_kernel_private;
26 uint64_t ce_prom_private; 26 u64 ce_prom_private;
27}; 27};
28 28
29struct tioce_kernel { 29struct tioce_kernel {
@@ -31,31 +31,31 @@ struct tioce_kernel {
31 spinlock_t ce_lock; 31 spinlock_t ce_lock;
32 struct list_head ce_dmamap_list; 32 struct list_head ce_dmamap_list;
33 33
34 uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES]; 34 u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES];
35 uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES]; 35 u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
36 uint32_t ce_ate3240_pagesize; 36 u32 ce_ate3240_pagesize;
37 37
38 uint8_t ce_port1_secondary; 38 u8 ce_port1_secondary;
39 39
40 /* per-port resources */ 40 /* per-port resources */
41 struct { 41 struct {
42 int dirmap_refcnt; 42 int dirmap_refcnt;
43 uint64_t dirmap_shadow; 43 u64 dirmap_shadow;
44 } ce_port[TIOCE_NUM_PORTS]; 44 } ce_port[TIOCE_NUM_PORTS];
45}; 45};
46 46
47struct tioce_dmamap { 47struct tioce_dmamap {
48 struct list_head ce_dmamap_list; /* headed by tioce_kernel */ 48 struct list_head ce_dmamap_list; /* headed by tioce_kernel */
49 uint32_t refcnt; 49 u32 refcnt;
50 50
51 uint64_t nbytes; /* # bytes mapped */ 51 u64 nbytes; /* # bytes mapped */
52 52
53 uint64_t ct_start; /* coretalk start address */ 53 u64 ct_start; /* coretalk start address */
54 uint64_t pci_start; /* bus start address */ 54 u64 pci_start; /* bus start address */
55 55
56 uint64_t *ate_hw; /* hw ptr of first ate in map */ 56 u64 *ate_hw; /* hw ptr of first ate in map */
57 uint64_t *ate_shadow; /* shadow ptr of firat ate */ 57 u64 *ate_shadow; /* shadow ptr of firat ate */
58 uint16_t ate_count; /* # ate's in the map */ 58 u16 ate_count; /* # ate's in the map */
59}; 59};
60 60
61extern int tioce_init_provider(void); 61extern int tioce_init_provider(void);
diff --git a/include/asm-ia64/sn/tiocp.h b/include/asm-ia64/sn/tiocp.h
index 5f2489c9d2dd..f47c08ab483c 100644
--- a/include/asm-ia64/sn/tiocp.h
+++ b/include/asm-ia64/sn/tiocp.h
@@ -21,189 +21,189 @@ struct tiocp{
21 /* 0x000000-0x00FFFF -- Local Registers */ 21 /* 0x000000-0x00FFFF -- Local Registers */
22 22
23 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */ 23 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
24 uint64_t cp_id; /* 0x000000 */ 24 u64 cp_id; /* 0x000000 */
25 uint64_t cp_stat; /* 0x000008 */ 25 u64 cp_stat; /* 0x000008 */
26 uint64_t cp_err_upper; /* 0x000010 */ 26 u64 cp_err_upper; /* 0x000010 */
27 uint64_t cp_err_lower; /* 0x000018 */ 27 u64 cp_err_lower; /* 0x000018 */
28 #define cp_err cp_err_lower 28 #define cp_err cp_err_lower
29 uint64_t cp_control; /* 0x000020 */ 29 u64 cp_control; /* 0x000020 */
30 uint64_t cp_req_timeout; /* 0x000028 */ 30 u64 cp_req_timeout; /* 0x000028 */
31 uint64_t cp_intr_upper; /* 0x000030 */ 31 u64 cp_intr_upper; /* 0x000030 */
32 uint64_t cp_intr_lower; /* 0x000038 */ 32 u64 cp_intr_lower; /* 0x000038 */
33 #define cp_intr cp_intr_lower 33 #define cp_intr cp_intr_lower
34 uint64_t cp_err_cmdword; /* 0x000040 */ 34 u64 cp_err_cmdword; /* 0x000040 */
35 uint64_t _pad_000048; /* 0x000048 */ 35 u64 _pad_000048; /* 0x000048 */
36 uint64_t cp_tflush; /* 0x000050 */ 36 u64 cp_tflush; /* 0x000050 */
37 37
38 /* 0x000058-0x00007F -- Bridge-specific Configuration */ 38 /* 0x000058-0x00007F -- Bridge-specific Configuration */
39 uint64_t cp_aux_err; /* 0x000058 */ 39 u64 cp_aux_err; /* 0x000058 */
40 uint64_t cp_resp_upper; /* 0x000060 */ 40 u64 cp_resp_upper; /* 0x000060 */
41 uint64_t cp_resp_lower; /* 0x000068 */ 41 u64 cp_resp_lower; /* 0x000068 */
42 #define cp_resp cp_resp_lower 42 #define cp_resp cp_resp_lower
43 uint64_t cp_tst_pin_ctrl; /* 0x000070 */ 43 u64 cp_tst_pin_ctrl; /* 0x000070 */
44 uint64_t cp_addr_lkerr; /* 0x000078 */ 44 u64 cp_addr_lkerr; /* 0x000078 */
45 45
46 /* 0x000080-0x00008F -- PMU & MAP */ 46 /* 0x000080-0x00008F -- PMU & MAP */
47 uint64_t cp_dir_map; /* 0x000080 */ 47 u64 cp_dir_map; /* 0x000080 */
48 uint64_t _pad_000088; /* 0x000088 */ 48 u64 _pad_000088; /* 0x000088 */
49 49
50 /* 0x000090-0x00009F -- SSRAM */ 50 /* 0x000090-0x00009F -- SSRAM */
51 uint64_t cp_map_fault; /* 0x000090 */ 51 u64 cp_map_fault; /* 0x000090 */
52 uint64_t _pad_000098; /* 0x000098 */ 52 u64 _pad_000098; /* 0x000098 */
53 53
54 /* 0x0000A0-0x0000AF -- Arbitration */ 54 /* 0x0000A0-0x0000AF -- Arbitration */
55 uint64_t cp_arb; /* 0x0000A0 */ 55 u64 cp_arb; /* 0x0000A0 */
56 uint64_t _pad_0000A8; /* 0x0000A8 */ 56 u64 _pad_0000A8; /* 0x0000A8 */
57 57
58 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ 58 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
59 uint64_t cp_ate_parity_err; /* 0x0000B0 */ 59 u64 cp_ate_parity_err; /* 0x0000B0 */
60 uint64_t _pad_0000B8; /* 0x0000B8 */ 60 u64 _pad_0000B8; /* 0x0000B8 */
61 61
62 /* 0x0000C0-0x0000FF -- PCI/GIO */ 62 /* 0x0000C0-0x0000FF -- PCI/GIO */
63 uint64_t cp_bus_timeout; /* 0x0000C0 */ 63 u64 cp_bus_timeout; /* 0x0000C0 */
64 uint64_t cp_pci_cfg; /* 0x0000C8 */ 64 u64 cp_pci_cfg; /* 0x0000C8 */
65 uint64_t cp_pci_err_upper; /* 0x0000D0 */ 65 u64 cp_pci_err_upper; /* 0x0000D0 */
66 uint64_t cp_pci_err_lower; /* 0x0000D8 */ 66 u64 cp_pci_err_lower; /* 0x0000D8 */
67 #define cp_pci_err cp_pci_err_lower 67 #define cp_pci_err cp_pci_err_lower
68 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ 68 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
69 69
70 /* 0x000100-0x0001FF -- Interrupt */ 70 /* 0x000100-0x0001FF -- Interrupt */
71 uint64_t cp_int_status; /* 0x000100 */ 71 u64 cp_int_status; /* 0x000100 */
72 uint64_t cp_int_enable; /* 0x000108 */ 72 u64 cp_int_enable; /* 0x000108 */
73 uint64_t cp_int_rst_stat; /* 0x000110 */ 73 u64 cp_int_rst_stat; /* 0x000110 */
74 uint64_t cp_int_mode; /* 0x000118 */ 74 u64 cp_int_mode; /* 0x000118 */
75 uint64_t cp_int_device; /* 0x000120 */ 75 u64 cp_int_device; /* 0x000120 */
76 uint64_t cp_int_host_err; /* 0x000128 */ 76 u64 cp_int_host_err; /* 0x000128 */
77 uint64_t cp_int_addr[8]; /* 0x0001{30,,,68} */ 77 u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
78 uint64_t cp_err_int_view; /* 0x000170 */ 78 u64 cp_err_int_view; /* 0x000170 */
79 uint64_t cp_mult_int; /* 0x000178 */ 79 u64 cp_mult_int; /* 0x000178 */
80 uint64_t cp_force_always[8]; /* 0x0001{80,,,B8} */ 80 u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
81 uint64_t cp_force_pin[8]; /* 0x0001{C0,,,F8} */ 81 u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
82 82
83 /* 0x000200-0x000298 -- Device */ 83 /* 0x000200-0x000298 -- Device */
84 uint64_t cp_device[4]; /* 0x0002{00,,,18} */ 84 u64 cp_device[4]; /* 0x0002{00,,,18} */
85 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */ 85 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
86 uint64_t cp_wr_req_buf[4]; /* 0x0002{40,,,58} */ 86 u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
87 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */ 87 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
88 uint64_t cp_rrb_map[2]; /* 0x0002{80,,,88} */ 88 u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
89 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */ 89 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
90 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */ 90 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
91 uint64_t cp_resp_status; /* 0x000290 */ 91 u64 cp_resp_status; /* 0x000290 */
92 uint64_t cp_resp_clear; /* 0x000298 */ 92 u64 cp_resp_clear; /* 0x000298 */
93 93
94 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ 94 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
95 95
96 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ 96 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
97 struct { 97 struct {
98 uint64_t upper; /* 0x0003{00,,,F0} */ 98 u64 upper; /* 0x0003{00,,,F0} */
99 uint64_t lower; /* 0x0003{08,,,F8} */ 99 u64 lower; /* 0x0003{08,,,F8} */
100 } cp_buf_addr_match[16]; 100 } cp_buf_addr_match[16];
101 101
102 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ 102 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
103 struct { 103 struct {
104 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */ 104 u64 flush_w_touch; /* 0x000{400,,,5C0} */
105 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */ 105 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
106 uint64_t inflight; /* 0x000{410,,,5D0} */ 106 u64 inflight; /* 0x000{410,,,5D0} */
107 uint64_t prefetch; /* 0x000{418,,,5D8} */ 107 u64 prefetch; /* 0x000{418,,,5D8} */
108 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */ 108 u64 total_pci_retry; /* 0x000{420,,,5E0} */
109 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */ 109 u64 max_pci_retry; /* 0x000{428,,,5E8} */
110 uint64_t max_latency; /* 0x000{430,,,5F0} */ 110 u64 max_latency; /* 0x000{430,,,5F0} */
111 uint64_t clear_all; /* 0x000{438,,,5F8} */ 111 u64 clear_all; /* 0x000{438,,,5F8} */
112 } cp_buf_count[8]; 112 } cp_buf_count[8];
113 113
114 114
115 /* 0x000600-0x0009FF -- PCI/X registers */ 115 /* 0x000600-0x0009FF -- PCI/X registers */
116 uint64_t cp_pcix_bus_err_addr; /* 0x000600 */ 116 u64 cp_pcix_bus_err_addr; /* 0x000600 */
117 uint64_t cp_pcix_bus_err_attr; /* 0x000608 */ 117 u64 cp_pcix_bus_err_attr; /* 0x000608 */
118 uint64_t cp_pcix_bus_err_data; /* 0x000610 */ 118 u64 cp_pcix_bus_err_data; /* 0x000610 */
119 uint64_t cp_pcix_pio_split_addr; /* 0x000618 */ 119 u64 cp_pcix_pio_split_addr; /* 0x000618 */
120 uint64_t cp_pcix_pio_split_attr; /* 0x000620 */ 120 u64 cp_pcix_pio_split_attr; /* 0x000620 */
121 uint64_t cp_pcix_dma_req_err_attr; /* 0x000628 */ 121 u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
122 uint64_t cp_pcix_dma_req_err_addr; /* 0x000630 */ 122 u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
123 uint64_t cp_pcix_timeout; /* 0x000638 */ 123 u64 cp_pcix_timeout; /* 0x000638 */
124 124
125 uint64_t _pad_000640[24]; /* 0x000{640,,,6F8} */ 125 u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
126 126
127 /* 0x000700-0x000737 -- Debug Registers */ 127 /* 0x000700-0x000737 -- Debug Registers */
128 uint64_t cp_ct_debug_ctl; /* 0x000700 */ 128 u64 cp_ct_debug_ctl; /* 0x000700 */
129 uint64_t cp_br_debug_ctl; /* 0x000708 */ 129 u64 cp_br_debug_ctl; /* 0x000708 */
130 uint64_t cp_mux3_debug_ctl; /* 0x000710 */ 130 u64 cp_mux3_debug_ctl; /* 0x000710 */
131 uint64_t cp_mux4_debug_ctl; /* 0x000718 */ 131 u64 cp_mux4_debug_ctl; /* 0x000718 */
132 uint64_t cp_mux5_debug_ctl; /* 0x000720 */ 132 u64 cp_mux5_debug_ctl; /* 0x000720 */
133 uint64_t cp_mux6_debug_ctl; /* 0x000728 */ 133 u64 cp_mux6_debug_ctl; /* 0x000728 */
134 uint64_t cp_mux7_debug_ctl; /* 0x000730 */ 134 u64 cp_mux7_debug_ctl; /* 0x000730 */
135 135
136 uint64_t _pad_000738[89]; /* 0x000{738,,,9F8} */ 136 u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
137 137
138 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ 138 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
139 struct { 139 struct {
140 uint64_t cp_buf_addr; /* 0x000{A00,,,AF0} */ 140 u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
141 uint64_t cp_buf_attr; /* 0X000{A08,,,AF8} */ 141 u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
142 } cp_pcix_read_buf_64[16]; 142 } cp_pcix_read_buf_64[16];
143 143
144 struct { 144 struct {
145 uint64_t cp_buf_addr; /* 0x000{B00,,,BE0} */ 145 u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
146 uint64_t cp_buf_attr; /* 0x000{B08,,,BE8} */ 146 u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
147 uint64_t cp_buf_valid; /* 0x000{B10,,,BF0} */ 147 u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
148 uint64_t __pad1; /* 0x000{B18,,,BF8} */ 148 u64 __pad1; /* 0x000{B18,,,BF8} */
149 } cp_pcix_write_buf_64[8]; 149 } cp_pcix_write_buf_64[8];
150 150
151 /* End of Local Registers -- Start of Address Map space */ 151 /* End of Local Registers -- Start of Address Map space */
152 152
153 char _pad_000c00[0x010000 - 0x000c00]; 153 char _pad_000c00[0x010000 - 0x000c00];
154 154
155 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */ 155 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
156 uint64_t cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */ 156 u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
157 157
158 char _pad_012000[0x14000 - 0x012000]; 158 char _pad_012000[0x14000 - 0x012000];
159 159
160 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */ 160 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
161 uint64_t cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */ 161 u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
162 162
163 char _pad_016000[0x18000 - 0x016000]; 163 char _pad_016000[0x18000 - 0x016000];
164 164
165 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */ 165 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
166 uint64_t cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ 166 u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
167 uint64_t cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ 167 u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
168 uint64_t cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ 168 u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
169 169
170 char _pad_019800[0x1C000 - 0x019800]; 170 char _pad_019800[0x1C000 - 0x019800];
171 171
172 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */ 172 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
173 uint64_t cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */ 173 u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
174 uint64_t cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */ 174 u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
175 uint64_t cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */ 175 u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
176 176
177 char _pad_01F000[0x20000 - 0x01F000]; 177 char _pad_01F000[0x20000 - 0x01F000];
178 178
179 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */ 179 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
180 char _pad_020000[0x021000 - 0x20000]; 180 char _pad_020000[0x021000 - 0x20000];
181 181
182 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */ 182 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
183 union { 183 union {
184 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ 184 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
185 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ 185 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
186 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ 186 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
187 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ 187 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
188 union { 188 union {
189 uint8_t c[0x100 / 1]; 189 u8 c[0x100 / 1];
190 uint16_t s[0x100 / 2]; 190 u16 s[0x100 / 2];
191 uint32_t l[0x100 / 4]; 191 u32 l[0x100 / 4];
192 uint64_t d[0x100 / 8]; 192 u64 d[0x100 / 8];
193 } f[8]; 193 } f[8];
194 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */ 194 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
195 195
196 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ 196 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
197 union { 197 union {
198 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ 198 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
199 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ 199 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
200 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ 200 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
201 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ 201 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
202 union { 202 union {
203 uint8_t c[0x100 / 1]; 203 u8 c[0x100 / 1];
204 uint16_t s[0x100 / 2]; 204 u16 s[0x100 / 2];
205 uint32_t l[0x100 / 4]; 205 u32 l[0x100 / 4];
206 uint64_t d[0x100 / 8]; 206 u64 d[0x100 / 8];
207 } f[8]; 207 } f[8];
208 } cp_type1_cfg; /* 0x028000-0x029000 */ 208 } cp_type1_cfg; /* 0x028000-0x029000 */
209 209
@@ -211,30 +211,30 @@ struct tiocp{
211 211
212 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ 212 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
213 union { 213 union {
214 uint8_t c[8 / 1]; 214 u8 c[8 / 1];
215 uint16_t s[8 / 2]; 215 u16 s[8 / 2];
216 uint32_t l[8 / 4]; 216 u32 l[8 / 4];
217 uint64_t d[8 / 8]; 217 u64 d[8 / 8];
218 } cp_pci_iack; /* 0x030000-0x030007 */ 218 } cp_pci_iack; /* 0x030000-0x030007 */
219 219
220 char _pad_030007[0x040000-0x030008]; 220 char _pad_030007[0x040000-0x030008];
221 221
222 /* 0x040000-0x040007 -- PCIX Special Cycle */ 222 /* 0x040000-0x040007 -- PCIX Special Cycle */
223 union { 223 union {
224 uint8_t c[8 / 1]; 224 u8 c[8 / 1];
225 uint16_t s[8 / 2]; 225 u16 s[8 / 2];
226 uint32_t l[8 / 4]; 226 u32 l[8 / 4];
227 uint64_t d[8 / 8]; 227 u64 d[8 / 8];
228 } cp_pcix_cycle; /* 0x040000-0x040007 */ 228 } cp_pcix_cycle; /* 0x040000-0x040007 */
229 229
230 char _pad_040007[0x200000-0x040008]; 230 char _pad_040007[0x200000-0x040008];
231 231
232 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */ 232 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
233 union { 233 union {
234 uint8_t c[0x100000 / 1]; 234 u8 c[0x100000 / 1];
235 uint16_t s[0x100000 / 2]; 235 u16 s[0x100000 / 2];
236 uint32_t l[0x100000 / 4]; 236 u32 l[0x100000 / 4];
237 uint64_t d[0x100000 / 8]; 237 u64 d[0x100000 / 8];
238 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */ 238 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
239 239
240 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)] 240 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
@@ -243,10 +243,10 @@ struct tiocp{
243 243
244 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */ 244 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
245 union { 245 union {
246 uint8_t c[0x100000 / 1]; 246 u8 c[0x100000 / 1];
247 uint16_t s[0x100000 / 2]; 247 u16 s[0x100000 / 2];
248 uint32_t l[0x100000 / 4]; 248 u32 l[0x100000 / 4];
249 uint64_t d[0x100000 / 8]; 249 u64 d[0x100000 / 8];
250 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */ 250 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
251 251
252 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)] 252 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h
index 5699e75e5024..d29728492f36 100644
--- a/include/asm-ia64/sn/tiocx.h
+++ b/include/asm-ia64/sn/tiocx.h
@@ -40,10 +40,10 @@ struct cx_drv {
40}; 40};
41 41
42/* create DMA address by stripping AS bits */ 42/* create DMA address by stripping AS bits */
43#define TIOCX_DMA_ADDR(a) (uint64_t)((uint64_t)(a) & 0xffffcfffffffffUL) 43#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
44 44
45#define TIOCX_TO_TIOCX_DMA_ADDR(a) (uint64_t)(((uint64_t)(a) & 0xfffffffff) | \ 45#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \
46 ((((uint64_t)(a)) & 0xffffc000000000UL) <<2)) 46 ((((u64)(a)) & 0xffffc000000000UL) <<2))
47 47
48#define TIO_CE_ASIC_PARTNUM 0xce00 48#define TIO_CE_ASIC_PARTNUM 0xce00
49#define TIOCX_CORELET 3 49#define TIOCX_CORELET 3
@@ -63,10 +63,10 @@ extern int cx_device_unregister(struct cx_dev *);
63extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int); 63extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
64extern int cx_driver_unregister(struct cx_drv *); 64extern int cx_driver_unregister(struct cx_drv *);
65extern int cx_driver_register(struct cx_drv *); 65extern int cx_driver_register(struct cx_drv *);
66extern uint64_t tiocx_dma_addr(uint64_t addr); 66extern u64 tiocx_dma_addr(u64 addr);
67extern uint64_t tiocx_swin_base(int nasid); 67extern u64 tiocx_swin_base(int nasid);
68extern void tiocx_mmr_store(int nasid, uint64_t offset, uint64_t value); 68extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
69extern uint64_t tiocx_mmr_load(int nasid, uint64_t offset); 69extern u64 tiocx_mmr_load(int nasid, u64 offset);
70 70
71#endif // __KERNEL__ 71#endif // __KERNEL__
72#endif // _ASM_IA64_SN_TIO_TIOCX__ 72#endif // _ASM_IA64_SN_TIO_TIOCX__
diff --git a/include/asm-sh/bus-sh.h b/include/asm-sh/bus-sh.h
index 83c5d2fd057f..e42d63b65cb5 100644
--- a/include/asm-sh/bus-sh.h
+++ b/include/asm-sh/bus-sh.h
@@ -21,6 +21,7 @@ struct sh_dev {
21 void *mapbase; 21 void *mapbase;
22 unsigned int irq[6]; 22 unsigned int irq[6];
23 u64 *dma_mask; 23 u64 *dma_mask;
24 u64 coherent_dma_mask;
24}; 25};
25 26
26#define to_sh_dev(d) container_of((d), struct sh_dev, dev) 27#define to_sh_dev(d) container_of((d), struct sh_dev, dev)
diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h
new file mode 100644
index 000000000000..fdfb75b30f0d
--- /dev/null
+++ b/include/asm-sh/clock.h
@@ -0,0 +1,61 @@
1#ifndef __ASM_SH_CLOCK_H
2#define __ASM_SH_CLOCK_H
3
4#include <linux/kref.h>
5#include <linux/list.h>
6#include <linux/seq_file.h>
7
8struct clk;
9
10struct clk_ops {
11 void (*init)(struct clk *clk);
12 void (*enable)(struct clk *clk);
13 void (*disable)(struct clk *clk);
14 void (*recalc)(struct clk *clk);
15 int (*set_rate)(struct clk *clk, unsigned long rate);
16};
17
18struct clk {
19 struct list_head node;
20 const char *name;
21
22 struct module *owner;
23
24 struct clk *parent;
25 struct clk_ops *ops;
26
27 struct kref kref;
28
29 unsigned long rate;
30 unsigned long flags;
31};
32
33#define CLK_ALWAYS_ENABLED (1 << 0)
34#define CLK_RATE_PROPAGATES (1 << 1)
35
36/* Should be defined by processor-specific code */
37void arch_init_clk_ops(struct clk_ops **, int type);
38
39/* arch/sh/kernel/cpu/clock.c */
40int clk_init(void);
41
42int __clk_enable(struct clk *);
43int clk_enable(struct clk *);
44
45void __clk_disable(struct clk *);
46void clk_disable(struct clk *);
47
48int clk_set_rate(struct clk *, unsigned long rate);
49unsigned long clk_get_rate(struct clk *);
50void clk_recalc_rate(struct clk *);
51
52struct clk *clk_get(const char *id);
53void clk_put(struct clk *);
54
55int clk_register(struct clk *);
56void clk_unregister(struct clk *);
57
58int show_clocks(struct seq_file *m);
59
60#endif /* __ASM_SH_CLOCK_H */
61
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index b972e715f9ee..954801b46022 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -3,5 +3,34 @@
3 3
4#define SH_DMAC_BASE 0xa4000020 4#define SH_DMAC_BASE 0xa4000020
5 5
6#endif /* __ASM_CPU_SH3_DMA_H */ 6/* Definitions for the SuperH DMAC */
7#define TM_BURST 0x00000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_128 0x00000018
12
13#define CHCR_TS_MASK 0x18
14#define CHCR_TS_SHIFT 3
15
16#define DMAOR_INIT DMAOR_DME
7 17
18/*
19 * The SuperH DMAC supports a number of transmit sizes, we list them here,
20 * with their respective values as they appear in the CHCR registers.
21 */
22enum {
23 XMIT_SZ_8BIT,
24 XMIT_SZ_16BIT,
25 XMIT_SZ_32BIT,
26 XMIT_SZ_128BIT,
27};
28
29static unsigned int ts_shift[] __attribute__ ((used)) = {
30 [XMIT_SZ_8BIT] = 0,
31 [XMIT_SZ_16BIT] = 1,
32 [XMIT_SZ_32BIT] = 2,
33 [XMIT_SZ_128BIT] = 4,
34};
35
36#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
index e2b91adf821a..0dfe61f14802 100644
--- a/include/asm-sh/cpu-sh4/dma.h
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -1,17 +1,49 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4#ifdef CONFIG_CPU_SH4A
5#define SH_DMAC_BASE 0xfc808020
6#else
4#define SH_DMAC_BASE 0xffa00000 7#define SH_DMAC_BASE 0xffa00000
8#endif
5 9
6#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ 10/* Definitions for the SuperH DMAC */
7 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30}) 11#define TM_BURST 0x0000080
8#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ 12#define TS_8 0x00000010
9 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34}) 13#define TS_16 0x00000020
10#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ 14#define TS_32 0x00000030
11 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38}) 15#define TS_64 0x00000000
12#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
13 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c})
14#define DMAOR (SH_DMAC_BASE + 0x40)
15 16
16#endif /* __ASM_CPU_SH4_DMA_H */ 17#define CHCR_TS_MASK 0x30
18#define CHCR_TS_SHIFT 4
19
20#define DMAOR_COD 0x00000008
21
22#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
17 23
24/*
25 * The SuperH DMAC supports a number of transmit sizes, we list them here,
26 * with their respective values as they appear in the CHCR registers.
27 *
28 * Defaults to a 64-bit transfer size.
29 */
30enum {
31 XMIT_SZ_64BIT,
32 XMIT_SZ_8BIT,
33 XMIT_SZ_16BIT,
34 XMIT_SZ_32BIT,
35 XMIT_SZ_256BIT,
36};
37
38/*
39 * The DMA count is defined as the number of bytes to transfer.
40 */
41static unsigned int ts_shift[] __attribute__ ((used)) = {
42 [XMIT_SZ_64BIT] = 3,
43 [XMIT_SZ_8BIT] = 0,
44 [XMIT_SZ_16BIT] = 1,
45 [XMIT_SZ_32BIT] = 2,
46 [XMIT_SZ_256BIT] = 5,
47};
48
49#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index 201d94fd214f..ef2b9b1ae41f 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -12,6 +12,8 @@
12 12
13#if defined(CONFIG_CPU_SUBTYPE_SH73180) 13#if defined(CONFIG_CPU_SUBTYPE_SH73180)
14#define FRQCR 0xa4150000 14#define FRQCR 0xa4150000
15#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
16#define FRQCR 0xffc80000
15#else 17#else
16#define FRQCR 0xffc00000 18#define FRQCR 0xffc00000
17#endif 19#endif
diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h
index d3fa5c2b889d..48f1f42c5d14 100644
--- a/include/asm-sh/dma-mapping.h
+++ b/include/asm-sh/dma-mapping.h
@@ -4,6 +4,7 @@
4#include <linux/config.h> 4#include <linux/config.h>
5#include <linux/mm.h> 5#include <linux/mm.h>
6#include <asm/scatterlist.h> 6#include <asm/scatterlist.h>
7#include <asm/cacheflush.h>
7#include <asm/io.h> 8#include <asm/io.h>
8 9
9extern struct bus_type pci_bus_type; 10extern struct bus_type pci_bus_type;
@@ -141,24 +142,24 @@ static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
141 } 142 }
142} 143}
143 144
144static inline void dma_sync_single_for_cpu(struct device *dev, 145static void dma_sync_single_for_cpu(struct device *dev,
145 dma_addr_t dma_handle, size_t size, 146 dma_addr_t dma_handle, size_t size,
146 enum dma_data_direction dir) 147 enum dma_data_direction dir)
147 __attribute__ ((alias("dma_sync_single"))); 148 __attribute__ ((alias("dma_sync_single")));
148 149
149static inline void dma_sync_single_for_device(struct device *dev, 150static void dma_sync_single_for_device(struct device *dev,
150 dma_addr_t dma_handle, size_t size, 151 dma_addr_t dma_handle, size_t size,
151 enum dma_data_direction dir) 152 enum dma_data_direction dir)
152 __attribute__ ((alias("dma_sync_single"))); 153 __attribute__ ((alias("dma_sync_single")));
153 154
154static inline void dma_sync_sg_for_cpu(struct device *dev, 155static void dma_sync_sg_for_cpu(struct device *dev,
155 struct scatterlist *sg, int nelems, 156 struct scatterlist *sg, int nelems,
156 enum dma_data_direction dir) 157 enum dma_data_direction dir)
157 __attribute__ ((alias("dma_sync_sg"))); 158 __attribute__ ((alias("dma_sync_sg")));
158 159
159static inline void dma_sync_sg_for_device(struct device *dev, 160static void dma_sync_sg_for_device(struct device *dev,
160 struct scatterlist *sg, int nelems, 161 struct scatterlist *sg, int nelems,
161 enum dma_data_direction dir) 162 enum dma_data_direction dir)
162 __attribute__ ((alias("dma_sync_sg"))); 163 __attribute__ ((alias("dma_sync_sg")));
163 164
164static inline int dma_get_cache_alignment(void) 165static inline int dma_get_cache_alignment(void)
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index 8e9436093ca8..a118a0d43053 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -15,6 +15,7 @@
15#include <linux/spinlock.h> 15#include <linux/spinlock.h>
16#include <linux/wait.h> 16#include <linux/wait.h>
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/device.h>
18#include <asm/cpu/dma.h> 19#include <asm/cpu/dma.h>
19#include <asm/semaphore.h> 20#include <asm/semaphore.h>
20 21
@@ -54,8 +55,8 @@ enum {
54 * DMA channel capabilities / flags 55 * DMA channel capabilities / flags
55 */ 56 */
56enum { 57enum {
57 DMA_CONFIGURED = 0x00,
58 DMA_TEI_CAPABLE = 0x01, 58 DMA_TEI_CAPABLE = 0x01,
59 DMA_CONFIGURED = 0x02,
59}; 60};
60 61
61extern spinlock_t dma_spin_lock; 62extern spinlock_t dma_spin_lock;
@@ -74,7 +75,8 @@ struct dma_ops {
74struct dma_channel { 75struct dma_channel {
75 char dev_id[16]; 76 char dev_id[16];
76 77
77 unsigned int chan; 78 unsigned int chan; /* Physical channel number */
79 unsigned int vchan; /* Virtual channel number */
78 unsigned int mode; 80 unsigned int mode;
79 unsigned int count; 81 unsigned int count;
80 82
@@ -91,6 +93,8 @@ struct dma_channel {
91}; 93};
92 94
93struct dma_info { 95struct dma_info {
96 struct platform_device *pdev;
97
94 const char *name; 98 const char *name;
95 unsigned int nr_channels; 99 unsigned int nr_channels;
96 unsigned long flags; 100 unsigned long flags;
@@ -130,7 +134,11 @@ extern void unregister_dmac(struct dma_info *info);
130 134
131#ifdef CONFIG_SYSFS 135#ifdef CONFIG_SYSFS
132/* arch/sh/drivers/dma/dma-sysfs.c */ 136/* arch/sh/drivers/dma/dma-sysfs.c */
133extern int dma_create_sysfs_files(struct dma_channel *); 137extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
138extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
139#else
140#define dma_create_sysfs_file(channel, info) do { } while (0)
141#define dma_remove_sysfs_file(channel, info) do { } while (0)
134#endif 142#endif
135 143
136#ifdef CONFIG_PCI 144#ifdef CONFIG_PCI
diff --git a/include/asm-sh/freq.h b/include/asm-sh/freq.h
index 2c0fde46a0ed..39c0e091cf58 100644
--- a/include/asm-sh/freq.h
+++ b/include/asm-sh/freq.h
@@ -14,16 +14,5 @@
14 14
15#include <asm/cpu/freq.h> 15#include <asm/cpu/freq.h>
16 16
17/* arch/sh/kernel/time.c */
18extern void get_current_frequency_divisors(unsigned int *ifc, unsigned int *pfc, unsigned int *bfc);
19
20extern unsigned int get_ifc_divisor(unsigned int value);
21extern unsigned int get_ifc_divisor(unsigned int value);
22extern unsigned int get_ifc_divisor(unsigned int value);
23
24extern unsigned int get_ifc_value(unsigned int divisor);
25extern unsigned int get_pfc_value(unsigned int divisor);
26extern unsigned int get_bfc_value(unsigned int divisor);
27
28#endif /* __KERNEL__ */ 17#endif /* __KERNEL__ */
29#endif /* __ASM_SH_FREQ_H */ 18#endif /* __ASM_SH_FREQ_H */
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 6bc343fee7a0..b0b2937b6f83 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -11,7 +11,7 @@
11 * For read{b,w,l} and write{b,w,l} there are also __raw versions, which 11 * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
12 * do not have a memory barrier after them. 12 * do not have a memory barrier after them.
13 * 13 *
14 * In addition, we have 14 * In addition, we have
15 * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O. 15 * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
16 * which are processor specific. 16 * which are processor specific.
17 */ 17 */
@@ -23,19 +23,27 @@
23 * inb by default expands to _inb, but the machine specific code may 23 * inb by default expands to _inb, but the machine specific code may
24 * define it to __inb if it chooses. 24 * define it to __inb if it chooses.
25 */ 25 */
26 26#include <linux/config.h>
27#include <asm/cache.h> 27#include <asm/cache.h>
28#include <asm/system.h> 28#include <asm/system.h>
29#include <asm/addrspace.h> 29#include <asm/addrspace.h>
30#include <asm/machvec.h> 30#include <asm/machvec.h>
31#include <linux/config.h> 31#include <asm/pgtable.h>
32#include <asm-generic/iomap.h>
33
34#ifdef __KERNEL__
32 35
33/* 36/*
34 * Depending on which platform we are running on, we need different 37 * Depending on which platform we are running on, we need different
35 * I/O functions. 38 * I/O functions.
36 */ 39 */
40#define __IO_PREFIX generic
41#include <asm/io_generic.h>
42
43#define maybebadio(port) \
44 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
45 __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
37 46
38#ifdef __KERNEL__
39/* 47/*
40 * Since boards are able to define their own set of I/O routines through 48 * Since boards are able to define their own set of I/O routines through
41 * their respective machine vector, we always wrap through the mv. 49 * their respective machine vector, we always wrap through the mv.
@@ -44,113 +52,120 @@
44 * a given routine, it will be wrapped to generic code at run-time. 52 * a given routine, it will be wrapped to generic code at run-time.
45 */ 53 */
46 54
47# define __inb(p) sh_mv.mv_inb((p)) 55#define __inb(p) sh_mv.mv_inb((p))
48# define __inw(p) sh_mv.mv_inw((p)) 56#define __inw(p) sh_mv.mv_inw((p))
49# define __inl(p) sh_mv.mv_inl((p)) 57#define __inl(p) sh_mv.mv_inl((p))
50# define __outb(x,p) sh_mv.mv_outb((x),(p)) 58#define __outb(x,p) sh_mv.mv_outb((x),(p))
51# define __outw(x,p) sh_mv.mv_outw((x),(p)) 59#define __outw(x,p) sh_mv.mv_outw((x),(p))
52# define __outl(x,p) sh_mv.mv_outl((x),(p)) 60#define __outl(x,p) sh_mv.mv_outl((x),(p))
53 61
54# define __inb_p(p) sh_mv.mv_inb_p((p)) 62#define __inb_p(p) sh_mv.mv_inb_p((p))
55# define __inw_p(p) sh_mv.mv_inw_p((p)) 63#define __inw_p(p) sh_mv.mv_inw_p((p))
56# define __inl_p(p) sh_mv.mv_inl_p((p)) 64#define __inl_p(p) sh_mv.mv_inl_p((p))
57# define __outb_p(x,p) sh_mv.mv_outb_p((x),(p)) 65#define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
58# define __outw_p(x,p) sh_mv.mv_outw_p((x),(p)) 66#define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
59# define __outl_p(x,p) sh_mv.mv_outl_p((x),(p)) 67#define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
60 68
61# define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c)) 69#define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
62# define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c)) 70#define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
63# define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c)) 71#define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
64# define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c)) 72#define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
65# define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) 73#define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
66# define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) 74#define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
67 75
68# define __readb(a) sh_mv.mv_readb((a)) 76#define __readb(a) sh_mv.mv_readb((a))
69# define __readw(a) sh_mv.mv_readw((a)) 77#define __readw(a) sh_mv.mv_readw((a))
70# define __readl(a) sh_mv.mv_readl((a)) 78#define __readl(a) sh_mv.mv_readl((a))
71# define __writeb(v,a) sh_mv.mv_writeb((v),(a)) 79#define __writeb(v,a) sh_mv.mv_writeb((v),(a))
72# define __writew(v,a) sh_mv.mv_writew((v),(a)) 80#define __writew(v,a) sh_mv.mv_writew((v),(a))
73# define __writel(v,a) sh_mv.mv_writel((v),(a)) 81#define __writel(v,a) sh_mv.mv_writel((v),(a))
74 82
75# define __ioremap(a,s) sh_mv.mv_ioremap((a), (s)) 83#define inb __inb
76# define __iounmap(a) sh_mv.mv_iounmap((a)) 84#define inw __inw
77 85#define inl __inl
78# define __isa_port2addr(a) sh_mv.mv_isa_port2addr(a) 86#define outb __outb
79 87#define outw __outw
80# define inb __inb 88#define outl __outl
81# define inw __inw 89
82# define inl __inl 90#define inb_p __inb_p
83# define outb __outb 91#define inw_p __inw_p
84# define outw __outw 92#define inl_p __inl_p
85# define outl __outl 93#define outb_p __outb_p
86 94#define outw_p __outw_p
87# define inb_p __inb_p 95#define outl_p __outl_p
88# define inw_p __inw_p 96
89# define inl_p __inl_p 97#define insb __insb
90# define outb_p __outb_p 98#define insw __insw
91# define outw_p __outw_p 99#define insl __insl
92# define outl_p __outl_p 100#define outsb __outsb
93 101#define outsw __outsw
94# define insb __insb 102#define outsl __outsl
95# define insw __insw 103
96# define insl __insl 104#define __raw_readb(a) __readb((void __iomem *)(a))
97# define outsb __outsb 105#define __raw_readw(a) __readw((void __iomem *)(a))
98# define outsw __outsw 106#define __raw_readl(a) __readl((void __iomem *)(a))
99# define outsl __outsl 107#define __raw_writeb(v, a) __writeb(v, (void __iomem *)(a))
100 108#define __raw_writew(v, a) __writew(v, (void __iomem *)(a))
101# define __raw_readb __readb 109#define __raw_writel(v, a) __writel(v, (void __iomem *)(a))
102# define __raw_readw __readw
103# define __raw_readl __readl
104# define __raw_writeb __writeb
105# define __raw_writew __writew
106# define __raw_writel __writel
107 110
108/* 111/*
109 * The platform header files may define some of these macros to use 112 * The platform header files may define some of these macros to use
110 * the inlined versions where appropriate. These macros may also be 113 * the inlined versions where appropriate. These macros may also be
111 * redefined by userlevel programs. 114 * redefined by userlevel programs.
112 */ 115 */
113#ifdef __raw_readb 116#ifdef __readb
114# define readb(a) ({ unsigned long r_ = __raw_readb((unsigned long)a); mb(); r_; }) 117# define readb(a) ({ unsigned long r_ = __raw_readb(a); mb(); r_; })
115#endif 118#endif
116#ifdef __raw_readw 119#ifdef __raw_readw
117# define readw(a) ({ unsigned long r_ = __raw_readw((unsigned long)a); mb(); r_; }) 120# define readw(a) ({ unsigned long r_ = __raw_readw(a); mb(); r_; })
118#endif 121#endif
119#ifdef __raw_readl 122#ifdef __raw_readl
120# define readl(a) ({ unsigned long r_ = __raw_readl((unsigned long)a); mb(); r_; }) 123# define readl(a) ({ unsigned long r_ = __raw_readl(a); mb(); r_; })
121#endif 124#endif
122 125
123#ifdef __raw_writeb 126#ifdef __raw_writeb
124# define writeb(v,a) ({ __raw_writeb((v),(unsigned long)(a)); mb(); }) 127# define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
125#endif 128#endif
126#ifdef __raw_writew 129#ifdef __raw_writew
127# define writew(v,a) ({ __raw_writew((v),(unsigned long)(a)); mb(); }) 130# define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
128#endif 131#endif
129#ifdef __raw_writel 132#ifdef __raw_writel
130# define writel(v,a) ({ __raw_writel((v),(unsigned long)(a)); mb(); }) 133# define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
131#endif 134#endif
132 135
133#define readb_relaxed(a) readb(a) 136#define readb_relaxed(a) readb(a)
134#define readw_relaxed(a) readw(a) 137#define readw_relaxed(a) readw(a)
135#define readl_relaxed(a) readl(a) 138#define readl_relaxed(a) readl(a)
136 139
137#define mmiowb() 140/* Simple MMIO */
141#define ioread8(a) readb(a)
142#define ioread16(a) readw(a)
143#define ioread16be(a) be16_to_cpu(__raw_readw((a)))
144#define ioread32(a) readl(a)
145#define ioread32be(a) be32_to_cpu(__raw_readl((a)))
138 146
139/* 147#define iowrite8(v,a) writeb((v),(a))
140 * If the platform has PC-like I/O, this function converts the offset into 148#define iowrite16(v,a) writew((v),(a))
141 * an address. 149#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
142 */ 150#define iowrite32(v,a) writel((v),(a))
143static __inline__ unsigned long isa_port2addr(unsigned long offset) 151#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
144{ 152
145 return __isa_port2addr(offset); 153#define ioread8_rep(a,d,c) insb((a),(d),(c))
146} 154#define ioread16_rep(a,d,c) insw((a),(d),(c))
155#define ioread32_rep(a,d,c) insl((a),(d),(c))
156
157#define iowrite8_rep(a,s,c) outsb((a),(s),(c))
158#define iowrite16_rep(a,s,c) outsw((a),(s),(c))
159#define iowrite32_rep(a,s,c) outsl((a),(s),(c))
160
161#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
147 162
148/* 163/*
149 * This function provides a method for the generic case where a board-specific 164 * This function provides a method for the generic case where a board-specific
150 * isa_port2addr simply needs to return the port + some arbitrary port base. 165 * ioport_map simply needs to return the port + some arbitrary port base.
151 * 166 *
152 * We use this at board setup time to implicitly set the port base, and 167 * We use this at board setup time to implicitly set the port base, and
153 * as a result, we can use the generic isa_port2addr. 168 * as a result, we can use the generic ioport_map.
154 */ 169 */
155static inline void __set_io_port_base(unsigned long pbase) 170static inline void __set_io_port_base(unsigned long pbase)
156{ 171{
@@ -159,51 +174,52 @@ static inline void __set_io_port_base(unsigned long pbase)
159 generic_io_base = pbase; 174 generic_io_base = pbase;
160} 175}
161 176
162#define isa_readb(a) readb(isa_port2addr(a)) 177#define isa_readb(a) readb(ioport_map(a, 1))
163#define isa_readw(a) readw(isa_port2addr(a)) 178#define isa_readw(a) readw(ioport_map(a, 2))
164#define isa_readl(a) readl(isa_port2addr(a)) 179#define isa_readl(a) readl(ioport_map(a, 4))
165#define isa_writeb(b,a) writeb(b,isa_port2addr(a)) 180#define isa_writeb(b,a) writeb(b,ioport_map(a, 1))
166#define isa_writew(w,a) writew(w,isa_port2addr(a)) 181#define isa_writew(w,a) writew(w,ioport_map(a, 2))
167#define isa_writel(l,a) writel(l,isa_port2addr(a)) 182#define isa_writel(l,a) writel(l,ioport_map(a, 4))
183
168#define isa_memset_io(a,b,c) \ 184#define isa_memset_io(a,b,c) \
169 memset((void *)(isa_port2addr((unsigned long)a)),(b),(c)) 185 memset((void *)(ioport_map((unsigned long)(a), 1)),(b),(c))
170#define isa_memcpy_fromio(a,b,c) \ 186#define isa_memcpy_fromio(a,b,c) \
171 memcpy((a),(void *)(isa_port2addr((unsigned long)(b))),(c)) 187 memcpy((a),(void *)(ioport_map((unsigned long)(b), 1)),(c))
172#define isa_memcpy_toio(a,b,c) \ 188#define isa_memcpy_toio(a,b,c) \
173 memcpy((void *)(isa_port2addr((unsigned long)(a))),(b),(c)) 189 memcpy((void *)(ioport_map((unsigned long)(a), 1)),(b),(c))
174 190
175/* We really want to try and get these to memcpy etc */ 191/* We really want to try and get these to memcpy etc */
176extern void memcpy_fromio(void *, unsigned long, unsigned long); 192extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
177extern void memcpy_toio(unsigned long, const void *, unsigned long); 193extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
178extern void memset_io(unsigned long, int, unsigned long); 194extern void memset_io(volatile void __iomem *, int, unsigned long);
179 195
180/* SuperH on-chip I/O functions */ 196/* SuperH on-chip I/O functions */
181static __inline__ unsigned char ctrl_inb(unsigned long addr) 197static inline unsigned char ctrl_inb(unsigned long addr)
182{ 198{
183 return *(volatile unsigned char*)addr; 199 return *(volatile unsigned char*)addr;
184} 200}
185 201
186static __inline__ unsigned short ctrl_inw(unsigned long addr) 202static inline unsigned short ctrl_inw(unsigned long addr)
187{ 203{
188 return *(volatile unsigned short*)addr; 204 return *(volatile unsigned short*)addr;
189} 205}
190 206
191static __inline__ unsigned int ctrl_inl(unsigned long addr) 207static inline unsigned int ctrl_inl(unsigned long addr)
192{ 208{
193 return *(volatile unsigned long*)addr; 209 return *(volatile unsigned long*)addr;
194} 210}
195 211
196static __inline__ void ctrl_outb(unsigned char b, unsigned long addr) 212static inline void ctrl_outb(unsigned char b, unsigned long addr)
197{ 213{
198 *(volatile unsigned char*)addr = b; 214 *(volatile unsigned char*)addr = b;
199} 215}
200 216
201static __inline__ void ctrl_outw(unsigned short b, unsigned long addr) 217static inline void ctrl_outw(unsigned short b, unsigned long addr)
202{ 218{
203 *(volatile unsigned short*)addr = b; 219 *(volatile unsigned short*)addr = b;
204} 220}
205 221
206static __inline__ void ctrl_outl(unsigned int b, unsigned long addr) 222static inline void ctrl_outl(unsigned int b, unsigned long addr)
207{ 223{
208 *(volatile unsigned long*)addr = b; 224 *(volatile unsigned long*)addr = b;
209} 225}
@@ -214,12 +230,12 @@ static __inline__ void ctrl_outl(unsigned int b, unsigned long addr)
214 * Change virtual addresses to physical addresses and vv. 230 * Change virtual addresses to physical addresses and vv.
215 * These are trivial on the 1:1 Linux/SuperH mapping 231 * These are trivial on the 1:1 Linux/SuperH mapping
216 */ 232 */
217static __inline__ unsigned long virt_to_phys(volatile void * address) 233static inline unsigned long virt_to_phys(volatile void *address)
218{ 234{
219 return PHYSADDR(address); 235 return PHYSADDR(address);
220} 236}
221 237
222static __inline__ void * phys_to_virt(unsigned long address) 238static inline void *phys_to_virt(unsigned long address)
223{ 239{
224 return (void *)P1SEGADDR(address); 240 return (void *)P1SEGADDR(address);
225} 241}
@@ -234,27 +250,60 @@ static __inline__ void * phys_to_virt(unsigned long address)
234 * differently. On the x86 architecture, we just read/write the 250 * differently. On the x86 architecture, we just read/write the
235 * memory location directly. 251 * memory location directly.
236 * 252 *
237 * On SH, we have the whole physical address space mapped at all times 253 * On SH, we traditionally have the whole physical address space mapped
238 * (as MIPS does), so "ioremap()" and "iounmap()" do not need to do 254 * at all times (as MIPS does), so "ioremap()" and "iounmap()" do not
239 * anything. (This isn't true for all machines but we still handle 255 * need to do anything but place the address in the proper segment. This
240 * these cases with wired TLB entries anyway ...) 256 * is true for P1 and P2 addresses, as well as some P3 ones. However,
257 * most of the P3 addresses and newer cores using extended addressing
258 * need to map through page tables, so the ioremap() implementation
259 * becomes a bit more complicated. See arch/sh/mm/ioremap.c for
260 * additional notes on this.
241 * 261 *
242 * We cheat a bit and always return uncachable areas until we've fixed 262 * We cheat a bit and always return uncachable areas until we've fixed
243 * the drivers to handle caching properly. 263 * the drivers to handle caching properly.
244 */ 264 */
245static __inline__ void * ioremap(unsigned long offset, unsigned long size) 265#ifdef CONFIG_MMU
266void __iomem *__ioremap(unsigned long offset, unsigned long size,
267 unsigned long flags);
268void __iounmap(void __iomem *addr);
269#else
270#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
271#define __iounmap(addr) do { } while (0)
272#endif /* CONFIG_MMU */
273
274static inline void __iomem *
275__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
246{ 276{
247 return __ioremap(offset, size); 277 unsigned long last_addr = offset + size - 1;
278
279 /*
280 * For P1 and P2 space this is trivial, as everything is already
281 * mapped. Uncached access for P1 addresses are done through P2.
282 * In the P3 case or for addresses outside of the 29-bit space,
283 * mapping must be done by the PMB or by using page tables.
284 */
285 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
286 if (unlikely(flags & _PAGE_CACHABLE))
287 return (void __iomem *)P1SEGADDR(offset);
288
289 return (void __iomem *)P2SEGADDR(offset);
290 }
291
292 return __ioremap(offset, size, flags);
248} 293}
249 294
250static __inline__ void iounmap(void *addr) 295#define ioremap(offset, size) \
251{ 296 __ioremap_mode((offset), (size), 0)
252 return __iounmap(addr); 297#define ioremap_nocache(offset, size) \
253} 298 __ioremap_mode((offset), (size), 0)
254 299#define ioremap_cache(offset, size) \
255#define ioremap_nocache(off,size) ioremap(off,size) 300 __ioremap_mode((offset), (size), _PAGE_CACHABLE)
256 301#define p3_ioremap(offset, size, flags) \
257static __inline__ int check_signature(unsigned long io_addr, 302 __ioremap((offset), (size), (flags))
303#define iounmap(addr) \
304 __iounmap((addr))
305
306static inline int check_signature(char __iomem *io_addr,
258 const unsigned char *signature, int length) 307 const unsigned char *signature, int length)
259{ 308{
260 int retval = 0; 309 int retval = 0;
diff --git a/include/asm-sh/io_generic.h b/include/asm-sh/io_generic.h
index be14587342f7..92fc6070d7b3 100644
--- a/include/asm-sh/io_generic.h
+++ b/include/asm-sh/io_generic.h
@@ -1,51 +1,49 @@
1/* 1/*
2 * include/asm-sh/io_generic.h 2 * Trivial I/O routine definitions, intentionally meant to be included
3 * 3 * multiple times. Ugly I/O routine concatenation helpers taken from
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) 4 * alpha. Must be included _before_ io.h to avoid preprocessor-induced
5 * 5 * routine mismatch.
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * Generic IO functions
10 */ 6 */
11 7#define IO_CONCAT(a,b) _IO_CONCAT(a,b)
12#ifndef _ASM_SH_IO_GENERIC_H 8#define _IO_CONCAT(a,b) a ## _ ## b
13#define _ASM_SH_IO_GENERIC_H 9
14 10#ifndef __IO_PREFIX
15extern unsigned long generic_io_base; 11#error "Don't include this header without a valid system prefix"
16 12#endif
17extern unsigned char generic_inb(unsigned long port); 13
18extern unsigned short generic_inw(unsigned long port); 14u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
19extern unsigned int generic_inl(unsigned long port); 15u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
20 16u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
21extern void generic_outb(unsigned char value, unsigned long port); 17
22extern void generic_outw(unsigned short value, unsigned long port); 18void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
23extern void generic_outl(unsigned int value, unsigned long port); 19void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
24 20void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
25extern unsigned char generic_inb_p(unsigned long port); 21
26extern unsigned short generic_inw_p(unsigned long port); 22u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
27extern unsigned int generic_inl_p(unsigned long port); 23u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
28extern void generic_outb_p(unsigned char value, unsigned long port); 24u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
29extern void generic_outw_p(unsigned short value, unsigned long port); 25void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
30extern void generic_outl_p(unsigned int value, unsigned long port); 26void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
31 27void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
32extern void generic_insb(unsigned long port, void *addr, unsigned long count); 28
33extern void generic_insw(unsigned long port, void *addr, unsigned long count); 29void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
34extern void generic_insl(unsigned long port, void *addr, unsigned long count); 30void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
35extern void generic_outsb(unsigned long port, const void *addr, unsigned long count); 31void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
36extern void generic_outsw(unsigned long port, const void *addr, unsigned long count); 32void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
37extern void generic_outsl(unsigned long port, const void *addr, unsigned long count); 33void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
38 34void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
39extern unsigned char generic_readb(unsigned long addr); 35
40extern unsigned short generic_readw(unsigned long addr); 36u8 IO_CONCAT(__IO_PREFIX,readb)(void __iomem *);
41extern unsigned int generic_readl(unsigned long addr); 37u16 IO_CONCAT(__IO_PREFIX,readw)(void __iomem *);
42extern void generic_writeb(unsigned char b, unsigned long addr); 38u32 IO_CONCAT(__IO_PREFIX,readl)(void __iomem *);
43extern void generic_writew(unsigned short b, unsigned long addr); 39void IO_CONCAT(__IO_PREFIX,writeb)(u8, void __iomem *);
44extern void generic_writel(unsigned int b, unsigned long addr); 40void IO_CONCAT(__IO_PREFIX,writew)(u16, void __iomem *);
45 41void IO_CONCAT(__IO_PREFIX,writel)(u32, void __iomem *);
46extern void *generic_ioremap(unsigned long offset, unsigned long size); 42
47extern void generic_iounmap(void *addr); 43void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
48 44void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
49extern unsigned long generic_isa_port2addr(unsigned long offset); 45
50 46void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
51#endif /* _ASM_SH_IO_GENERIC_H */ 47void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
48
49#undef __IO_PREFIX
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
new file mode 100644
index 000000000000..8c8ca1281084
--- /dev/null
+++ b/include/asm-sh/irq-sh7780.h
@@ -0,0 +1,349 @@
1#ifndef __ASM_SH_IRQ_SH7780_H
2#define __ASM_SH_IRQ_SH7780_H
3
4/*
5 * linux/include/asm-sh/irq-sh7780.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9
10#ifdef CONFIG_IDE
11# ifndef IRQ_CFCARD
12# define IRQ_CFCARD 14
13# endif
14# ifndef IRQ_PCMCIA
15# define IRQ_PCMCIA 15
16# endif
17#endif
18
19#define INTC_BASE 0xffd00000
20#define INTC_ICR0 (INTC_BASE+0x0)
21#define INTC_ICR1 (INTC_BASE+0x1c)
22#define INTC_INTPRI (INTC_BASE+0x10)
23#define INTC_INTREQ (INTC_BASE+0x24)
24#define INTC_INTMSK0 (INTC_BASE+0x44)
25#define INTC_INTMSK1 (INTC_BASE+0x48)
26#define INTC_INTMSK2 (INTC_BASE+0x40080)
27#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
28#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
29#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
30#define INTC_NMIFCR (INTC_BASE+0xc0)
31#define INTC_USERIMASK (INTC_BASE+0x30000)
32
33#define INTC_INT2PRI0 (INTC_BASE+0x40000)
34#define INTC_INT2PRI1 (INTC_BASE+0x40004)
35#define INTC_INT2PRI2 (INTC_BASE+0x40008)
36#define INTC_INT2PRI3 (INTC_BASE+0x4000c)
37#define INTC_INT2PRI4 (INTC_BASE+0x40010)
38#define INTC_INT2PRI5 (INTC_BASE+0x40014)
39#define INTC_INT2PRI6 (INTC_BASE+0x40018)
40#define INTC_INT2PRI7 (INTC_BASE+0x4001c)
41#define INTC_INT2A0 (INTC_BASE+0x40030)
42#define INTC_INT2A1 (INTC_BASE+0x40034)
43#define INTC_INT2MSKR (INTC_BASE+0x40038)
44#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
45#define INTC_INT2B0 (INTC_BASE+0x40040)
46#define INTC_INT2B1 (INTC_BASE+0x40044)
47#define INTC_INT2B2 (INTC_BASE+0x40048)
48#define INTC_INT2B3 (INTC_BASE+0x4004c)
49#define INTC_INT2B4 (INTC_BASE+0x40050)
50#define INTC_INT2B5 (INTC_BASE+0x40054)
51#define INTC_INT2B6 (INTC_BASE+0x40058)
52#define INTC_INT2B7 (INTC_BASE+0x4005c)
53#define INTC_INT2GPIC (INTC_BASE+0x40090)
54/*
55 NOTE:
56 *_IRQ = (INTEVT2 - 0x200)/0x20
57*/
58/* IRQ 0-7 line external int*/
59#define IRQ0_IRQ 2
60#define IRQ0_IPR_ADDR INTC_INTPRI
61#define IRQ0_IPR_POS 7
62#define IRQ0_PRIORITY 2
63
64#define IRQ1_IRQ 4
65#define IRQ1_IPR_ADDR INTC_INTPRI
66#define IRQ1_IPR_POS 6
67#define IRQ1_PRIORITY 2
68
69#define IRQ2_IRQ 6
70#define IRQ2_IPR_ADDR INTC_INTPRI
71#define IRQ2_IPR_POS 5
72#define IRQ2_PRIORITY 2
73
74#define IRQ3_IRQ 8
75#define IRQ3_IPR_ADDR INTC_INTPRI
76#define IRQ3_IPR_POS 4
77#define IRQ3_PRIORITY 2
78
79#define IRQ4_IRQ 10
80#define IRQ4_IPR_ADDR INTC_INTPRI
81#define IRQ4_IPR_POS 3
82#define IRQ4_PRIORITY 2
83
84#define IRQ5_IRQ 12
85#define IRQ5_IPR_ADDR INTC_INTPRI
86#define IRQ5_IPR_POS 2
87#define IRQ5_PRIORITY 2
88
89#define IRQ6_IRQ 14
90#define IRQ6_IPR_ADDR INTC_INTPRI
91#define IRQ6_IPR_POS 1
92#define IRQ6_PRIORITY 2
93
94#define IRQ7_IRQ 0
95#define IRQ7_IPR_ADDR INTC_INTPRI
96#define IRQ7_IPR_POS 0
97#define IRQ7_PRIORITY 2
98
99/* TMU */
100/* ch0 */
101#define TMU_IRQ 28
102#define TMU_IPR_ADDR INTC_INT2PRI0
103#define TMU_IPR_POS 3
104#define TMU_PRIORITY 2
105
106#define TIMER_IRQ 28
107#define TIMER_IPR_ADDR INTC_INT2PRI0
108#define TIMER_IPR_POS 3
109#define TIMER_PRIORITY 2
110
111/* ch 1*/
112#define TMU_CH1_IRQ 29
113#define TMU_CH1_IPR_ADDR INTC_INT2PRI0
114#define TMU_CH1_IPR_POS 2
115#define TMU_CH1_PRIORITY 2
116
117#define TIMER1_IRQ 29
118#define TIMER1_IPR_ADDR INTC_INT2PRI0
119#define TIMER1_IPR_POS 2
120#define TIMER1_PRIORITY 2
121
122/* ch 2*/
123#define TMU_CH2_IRQ 30
124#define TMU_CH2_IPR_ADDR INTC_INT2PRI0
125#define TMU_CH2_IPR_POS 1
126#define TMU_CH2_PRIORITY 2
127/* ch 2 Input capture */
128#define TMU_CH2IC_IRQ 31
129#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0
130#define TMU_CH2IC_IPR_POS 0
131#define TMU_CH2IC_PRIORITY 2
132/* ch 3 */
133#define TMU_CH3_IRQ 96
134#define TMU_CH3_IPR_ADDR INTC_INT2PRI1
135#define TMU_CH3_IPR_POS 3
136#define TMU_CH3_PRIORITY 2
137/* ch 4 */
138#define TMU_CH4_IRQ 97
139#define TMU_CH4_IPR_ADDR INTC_INT2PRI1
140#define TMU_CH4_IPR_POS 2
141#define TMU_CH4_PRIORITY 2
142/* ch 5*/
143#define TMU_CH5_IRQ 98
144#define TMU_CH5_IPR_ADDR INTC_INT2PRI1
145#define TMU_CH5_IPR_POS 1
146#define TMU_CH5_PRIORITY 2
147
148#define RTC_IRQ 22
149#define RTC_IPR_ADDR INTC_INT2PRI1
150#define RTC_IPR_POS 0
151#define RTC_PRIORITY TIMER_PRIORITY
152
153/* SCIF0 */
154#define SCIF0_ERI_IRQ 40
155#define SCIF0_RXI_IRQ 41
156#define SCIF0_BRI_IRQ 42
157#define SCIF0_TXI_IRQ 43
158#define SCIF0_IPR_ADDR INTC_INT2PRI2
159#define SCIF0_IPR_POS 3
160#define SCIF0_PRIORITY 3
161
162/* SCIF1 */
163#define SCIF1_ERI_IRQ 76
164#define SCIF1_RXI_IRQ 77
165#define SCIF1_BRI_IRQ 78
166#define SCIF1_TXI_IRQ 79
167#define SCIF1_IPR_ADDR INTC_INT2PRI2
168#define SCIF1_IPR_POS 2
169#define SCIF1_PRIORITY 3
170
171#define WDT_IRQ 27
172#define WDT_IPR_ADDR INTC_INT2PRI2
173#define WDT_IPR_POS 1
174#define WDT_PRIORITY 2
175
176/* DMAC(0) */
177#define DMINT0_IRQ 34
178#define DMINT1_IRQ 35
179#define DMINT2_IRQ 36
180#define DMINT3_IRQ 37
181#define DMINT4_IRQ 44
182#define DMINT5_IRQ 45
183#define DMINT6_IRQ 46
184#define DMINT7_IRQ 47
185#define DMAE_IRQ 38
186#define DMA0_IPR_ADDR INTC_INT2PRI3
187#define DMA0_IPR_POS 2
188#define DMA0_PRIORITY 7
189
190/* DMAC(1) */
191#define DMINT8_IRQ 92
192#define DMINT9_IRQ 93
193#define DMINT10_IRQ 94
194#define DMINT11_IRQ 95
195#define DMA1_IPR_ADDR INTC_INT2PRI3
196#define DMA1_IPR_POS 1
197#define DMA1_PRIORITY 7
198
199#define DMTE0_IRQ DMINT0_IRQ
200#define DMTE4_IRQ DMINT4_IRQ
201#define DMA_IPR_ADDR DMA0_IPR_ADDR
202#define DMA_IPR_POS DMA0_IPR_POS
203#define DMA_PRIORITY DMA0_PRIORITY
204
205/* CMT */
206#define CMT_IRQ 56
207#define CMT_IPR_ADDR INTC_INT2PRI4
208#define CMT_IPR_POS 3
209#define CMT_PRIORITY 0
210
211/* HAC */
212#define HAC_IRQ 60
213#define HAC_IPR_ADDR INTC_INT2PRI4
214#define HAC_IPR_POS 2
215#define CMT_PRIORITY 0
216
217/* PCIC(0) */
218#define PCIC0_IRQ 64
219#define PCIC0_IPR_ADDR INTC_INT2PRI4
220#define PCIC0_IPR_POS 1
221#define PCIC0_PRIORITY 2
222
223/* PCIC(1) */
224#define PCIC1_IRQ 65
225#define PCIC1_IPR_ADDR INTC_INT2PRI4
226#define PCIC1_IPR_POS 0
227#define PCIC1_PRIORITY 2
228
229/* PCIC(2) */
230#define PCIC2_IRQ 66
231#define PCIC2_IPR_ADDR INTC_INT2PRI5
232#define PCIC2_IPR_POS 3
233#define PCIC2_PRIORITY 2
234
235/* PCIC(3) */
236#define PCIC3_IRQ 67
237#define PCIC3_IPR_ADDR INTC_INT2PRI5
238#define PCIC3_IPR_POS 2
239#define PCIC3_PRIORITY 2
240
241/* PCIC(4) */
242#define PCIC4_IRQ 68
243#define PCIC4_IPR_ADDR INTC_INT2PRI5
244#define PCIC4_IPR_POS 1
245#define PCIC4_PRIORITY 2
246
247/* PCIC(5) */
248#define PCICERR_IRQ 69
249#define PCICPWD3_IRQ 70
250#define PCICPWD2_IRQ 71
251#define PCICPWD1_IRQ 72
252#define PCICPWD0_IRQ 73
253#define PCIC5_IPR_ADDR INTC_INT2PRI5
254#define PCIC5_IPR_POS 0
255#define PCIC5_PRIORITY 2
256
257/* SIOF */
258#define SIOF_IRQ 80
259#define SIOF_IPR_ADDR INTC_INT2PRI6
260#define SIOF_IPR_POS 3
261#define SIOF_PRIORITY 3
262
263/* HSPI */
264#define HSPI_IRQ 84
265#define HSPI_IPR_ADDR INTC_INT2PRI6
266#define HSPI_IPR_POS 2
267#define HSPI_PRIORITY 3
268
269/* MMCIF */
270#define MMCIF_FSTAT_IRQ 88
271#define MMCIF_TRAN_IRQ 89
272#define MMCIF_ERR_IRQ 90
273#define MMCIF_FRDY_IRQ 91
274#define MMCIF_IPR_ADDR INTC_INT2PRI6
275#define MMCIF_IPR_POS 1
276#define HSPI_PRIORITY 3
277
278/* SSI */
279#define SSI_IRQ 100
280#define SSI_IPR_ADDR INTC_INT2PRI6
281#define SSI_IPR_POS 0
282#define SSI_PRIORITY 3
283
284/* FLCTL */
285#define FLCTL_FLSTE_IRQ 104
286#define FLCTL_FLTEND_IRQ 105
287#define FLCTL_FLTRQ0_IRQ 106
288#define FLCTL_FLTRQ1_IRQ 107
289#define FLCTL_IPR_ADDR INTC_INT2PRI7
290#define FLCTL_IPR_POS 3
291#define FLCTL_PRIORITY 3
292
293/* GPIO */
294#define GPIO0_IRQ 108
295#define GPIO1_IRQ 109
296#define GPIO2_IRQ 110
297#define GPIO3_IRQ 111
298#define GPIO_IPR_ADDR INTC_INT2PRI7
299#define GPIO_IPR_POS 2
300#define GPIO_PRIORITY 3
301
302/* ONCHIP_NR_IRQS */
303#define NR_IRQS 150 /* 111 + 16 */
304
305/* In a generic kernel, NR_IRQS is an upper bound, and we should use
306 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
307 */
308#define ACTUAL_NR_IRQS NR_IRQS
309
310extern void disable_irq(unsigned int);
311extern void disable_irq_nosync(unsigned int);
312extern void enable_irq(unsigned int);
313
314/*
315 * Simple Mask Register Support
316 */
317extern void make_maskreg_irq(unsigned int irq);
318extern unsigned short *irq_mask_register;
319
320/*
321 * Function for "on chip support modules".
322 */
323extern void make_imask_irq(unsigned int irq);
324
325#define INTC_TMU0_MSK 0
326#define INTC_TMU3_MSK 1
327#define INTC_RTC_MSK 2
328#define INTC_SCIF0_MSK 3
329#define INTC_SCIF1_MSK 4
330#define INTC_WDT_MSK 5
331#define INTC_HUID_MSK 7
332#define INTC_DMAC0_MSK 8
333#define INTC_DMAC1_MSK 9
334#define INTC_CMT_MSK 12
335#define INTC_HAC_MSK 13
336#define INTC_PCIC0_MSK 14
337#define INTC_PCIC1_MSK 15
338#define INTC_PCIC2_MSK 16
339#define INTC_PCIC3_MSK 17
340#define INTC_PCIC4_MSK 18
341#define INTC_PCIC5_MSK 19
342#define INTC_SIOF_MSK 20
343#define INTC_HSPI_MSK 21
344#define INTC_MMCIF_MSK 22
345#define INTC_SSI_MSK 23
346#define INTC_FLCTL_MSK 24
347#define INTC_GPIO_MSK 25
348
349#endif /* __ASM_SH_IRQ_SH7780_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 614a8c13b721..060ec3c27207 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -15,13 +15,20 @@
15#include <asm/machvec.h> 15#include <asm/machvec.h>
16#include <asm/ptrace.h> /* for pt_regs */ 16#include <asm/ptrace.h> /* for pt_regs */
17 17
18#if defined(CONFIG_SH_HP600) || \ 18#if defined(CONFIG_SH_HP6XX) || \
19 defined(CONFIG_SH_RTS7751R2D) || \ 19 defined(CONFIG_SH_RTS7751R2D) || \
20 defined(CONFIG_SH_HS7751RVOIP) || \ 20 defined(CONFIG_SH_HS7751RVOIP) || \
21 defined(CONFIG_SH_SH03) 21 defined(CONFIG_SH_HS7751RVOIP) || \
22 defined(CONFIG_SH_SH03) || \
23 defined(CONFIG_SH_R7780RP) || \
24 defined(CONFIG_SH_LANDISK)
22#include <asm/mach/ide.h> 25#include <asm/mach/ide.h>
23#endif 26#endif
24 27
28#ifndef CONFIG_CPU_SUBTYPE_SH7780
29
30#define INTC_DMAC0_MSK 0
31
25#if defined(CONFIG_CPU_SH3) 32#if defined(CONFIG_CPU_SH3)
26#define INTC_IPRA 0xfffffee2UL 33#define INTC_IPRA 0xfffffee2UL
27#define INTC_IPRB 0xfffffee4UL 34#define INTC_IPRB 0xfffffee4UL
@@ -235,8 +242,9 @@
235#define SCIF1_IPR_ADDR INTC_IPRB 242#define SCIF1_IPR_ADDR INTC_IPRB
236#define SCIF1_IPR_POS 1 243#define SCIF1_IPR_POS 1
237#define SCIF1_PRIORITY 3 244#define SCIF1_PRIORITY 3
238#endif 245#endif /* ST40STB1 */
239#endif 246
247#endif /* 775x / SH4-202 / ST40STB1 */
240 248
241/* NR_IRQS is made from three components: 249/* NR_IRQS is made from three components:
242 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules 250 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
@@ -245,37 +253,35 @@
245 */ 253 */
246 254
247/* 1. ONCHIP_NR_IRQS */ 255/* 1. ONCHIP_NR_IRQS */
248#ifdef CONFIG_SH_GENERIC 256#if defined(CONFIG_CPU_SUBTYPE_SH7604)
257# define ONCHIP_NR_IRQS 24 // Actually 21
258#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
259# define ONCHIP_NR_IRQS 64
260# define PINT_NR_IRQS 16
261#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
262# define ONCHIP_NR_IRQS 32
263#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7705)
265# define ONCHIP_NR_IRQS 64 // Actually 61
266# define PINT_NR_IRQS 16
267#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
268# define ONCHIP_NR_IRQS 48 // Actually 44
269#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
270# define ONCHIP_NR_IRQS 72
271#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
272# define ONCHIP_NR_IRQS 112 /* XXX */
273#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
274# define ONCHIP_NR_IRQS 72
275#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
276# define ONCHIP_NR_IRQS 144
277#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
278# define ONCHIP_NR_IRQS 109
279#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
249# define ONCHIP_NR_IRQS 144 280# define ONCHIP_NR_IRQS 144
250#else
251# if defined(CONFIG_CPU_SUBTYPE_SH7604)
252# define ONCHIP_NR_IRQS 24 // Actually 21
253# elif defined(CONFIG_CPU_SUBTYPE_SH7707)
254# define ONCHIP_NR_IRQS 64
255# define PINT_NR_IRQS 16
256# elif defined(CONFIG_CPU_SUBTYPE_SH7708)
257# define ONCHIP_NR_IRQS 32
258# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
259 defined(CONFIG_CPU_SUBTYPE_SH7705)
260# define ONCHIP_NR_IRQS 64 // Actually 61
261# define PINT_NR_IRQS 16
262# elif defined(CONFIG_CPU_SUBTYPE_SH7750)
263# define ONCHIP_NR_IRQS 48 // Actually 44
264# elif defined(CONFIG_CPU_SUBTYPE_SH7751)
265# define ONCHIP_NR_IRQS 72
266# elif defined(CONFIG_CPU_SUBTYPE_SH7760)
267# define ONCHIP_NR_IRQS 110
268# elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
269# define ONCHIP_NR_IRQS 72
270# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
271# define ONCHIP_NR_IRQS 144
272# elif defined(CONFIG_CPU_SUBTYPE_SH7300)
273# define ONCHIP_NR_IRQS 109
274# endif
275#endif 281#endif
276 282
277/* 2. PINT_NR_IRQS */ 283/* 2. PINT_NR_IRQS */
278#ifdef CONFIG_SH_GENERIC 284#ifdef CONFIG_SH_UNKNOWN
279# define PINT_NR_IRQS 16 285# define PINT_NR_IRQS 16
280#else 286#else
281# ifndef PINT_NR_IRQS 287# ifndef PINT_NR_IRQS
@@ -288,22 +294,22 @@
288#endif 294#endif
289 295
290/* 3. OFFCHIP_NR_IRQS */ 296/* 3. OFFCHIP_NR_IRQS */
291#ifdef CONFIG_SH_GENERIC 297#if defined(CONFIG_HD64461)
298# define OFFCHIP_NR_IRQS 18
299#elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
300# define OFFCHIP_NR_IRQS 48
301#elif defined(CONFIG_HD64465)
292# define OFFCHIP_NR_IRQS 16 302# define OFFCHIP_NR_IRQS 16
303#elif defined (CONFIG_SH_EC3104)
304# define OFFCHIP_NR_IRQS 16
305#elif defined (CONFIG_SH_DREAMCAST)
306# define OFFCHIP_NR_IRQS 96
307#elif defined (CONFIG_SH_TITAN)
308# define OFFCHIP_NR_IRQS 4
309#elif defined(CONFIG_SH_UNKNOWN)
310# define OFFCHIP_NR_IRQS 16 /* Must also be last */
293#else 311#else
294# if defined(CONFIG_HD64461) 312# define OFFCHIP_NR_IRQS 0
295# define OFFCHIP_NR_IRQS 18
296# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
297# define OFFCHIP_NR_IRQS 48
298# elif defined(CONFIG_HD64465)
299# define OFFCHIP_NR_IRQS 16
300# elif defined (CONFIG_SH_EC3104)
301# define OFFCHIP_NR_IRQS 16
302# elif defined (CONFIG_SH_DREAMCAST)
303# define OFFCHIP_NR_IRQS 96
304# else
305# define OFFCHIP_NR_IRQS 0
306# endif
307#endif 313#endif
308 314
309#if OFFCHIP_NR_IRQS > 0 315#if OFFCHIP_NR_IRQS > 0
@@ -313,16 +319,6 @@
313/* NR_IRQS. 1+2+3 */ 319/* NR_IRQS. 1+2+3 */
314#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) 320#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
315 321
316/* In a generic kernel, NR_IRQS is an upper bound, and we should use
317 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
318 */
319#ifdef CONFIG_SH_GENERIC
320# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
321#else
322# define ACTUAL_NR_IRQS NR_IRQS
323#endif
324
325
326extern void disable_irq(unsigned int); 322extern void disable_irq(unsigned int);
327extern void disable_irq_nosync(unsigned int); 323extern void disable_irq_nosync(unsigned int);
328extern void enable_irq(unsigned int); 324extern void enable_irq(unsigned int);
@@ -542,9 +538,6 @@ extern int ipr_irq_demux(int irq);
542 538
543extern int ipr_irq_demux(int irq); 539extern int ipr_irq_demux(int irq);
544#define __irq_demux(irq) ipr_irq_demux(irq) 540#define __irq_demux(irq) ipr_irq_demux(irq)
545
546#else
547#define __irq_demux(irq) irq
548#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */ 541#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
549 542
550#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 543#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
@@ -557,18 +550,35 @@ extern int ipr_irq_demux(int irq);
557#define INTC_ICR_IRLM (1<<7) 550#define INTC_ICR_IRLM (1<<7)
558#endif 551#endif
559 552
560#ifdef CONFIG_CPU_SUBTYPE_ST40STB1 553#else
554#include <asm/irq-sh7780.h>
555#endif
561 556
557/* SH with INTC2-style interrupts */
558#ifdef CONFIG_CPU_HAS_INTC2_IRQ
559#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
560#define INTC2_BASE 0xfe080000
562#define INTC2_FIRST_IRQ 64 561#define INTC2_FIRST_IRQ 64
563#define NR_INTC2_IRQS 25 562#define INTC2_INTREQ_OFFSET 0x20
564 563#define INTC2_INTMSK_OFFSET 0x40
564#define INTC2_INTMSKCLR_OFFSET 0x60
565#define NR_INTC2_IRQS 25
566#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
565#define INTC2_BASE 0xfe080000 567#define INTC2_BASE 0xfe080000
566#define INTC2_INTC2MODE (INTC2_BASE+0x80) 568#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
567
568#define INTC2_INTPRI_OFFSET 0x00
569#define INTC2_INTREQ_OFFSET 0x20 569#define INTC2_INTREQ_OFFSET 0x20
570#define INTC2_INTMSK_OFFSET 0x40 570#define INTC2_INTMSK_OFFSET 0x40
571#define INTC2_INTMSKCLR_OFFSET 0x60 571#define INTC2_INTMSKCLR_OFFSET 0x60
572#define NR_INTC2_IRQS 64
573#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
574#define INTC2_BASE 0xffd40000
575#define INTC2_FIRST_IRQ 22
576#define INTC2_INTMSK_OFFSET (0x38)
577#define INTC2_INTMSKCLR_OFFSET (0x3c)
578#define NR_INTC2_IRQS 60
579#endif
580
581#define INTC2_INTPRI_OFFSET 0x00
572 582
573void make_intc2_irq(unsigned int irq, 583void make_intc2_irq(unsigned int irq,
574 unsigned int ipr_offset, unsigned int ipr_shift, 584 unsigned int ipr_offset, unsigned int ipr_shift,
@@ -577,13 +587,16 @@ void make_intc2_irq(unsigned int irq,
577void init_IRQ_intc2(void); 587void init_IRQ_intc2(void);
578void intc2_add_clear_irq(int irq, int (*fn)(int)); 588void intc2_add_clear_irq(int irq, int (*fn)(int));
579 589
580#endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */ 590#endif
581 591
582static inline int generic_irq_demux(int irq) 592static inline int generic_irq_demux(int irq)
583{ 593{
584 return irq; 594 return irq;
585} 595}
586 596
597#ifndef __irq_demux
598#define __irq_demux(irq) (irq)
599#endif
587#define irq_canonicalize(irq) (irq) 600#define irq_canonicalize(irq) (irq)
588#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) 601#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
589 602
diff --git a/include/asm-sh/kexec.h b/include/asm-sh/kexec.h
new file mode 100644
index 000000000000..9dfe59f6fcb5
--- /dev/null
+++ b/include/asm-sh/kexec.h
@@ -0,0 +1,33 @@
1#ifndef _SH_KEXEC_H
2#define _SH_KEXEC_H
3
4/*
5 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
6 * I.e. Maximum page that is mapped directly into kernel memory,
7 * and kmap is not required.
8 *
9 * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
10 * calculation for the amount of memory directly mappable into the
11 * kernel memory space.
12 */
13
14/* Maximum physical address we can use pages from */
15#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
16/* Maximum address we can reach in physical address mode */
17#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
18/* Maximum address we can use for the control code buffer */
19#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
20
21#define KEXEC_CONTROL_CODE_SIZE 4096
22
23/* The native architecture */
24#define KEXEC_ARCH KEXEC_ARCH_SH
25
26#ifndef __ASSEMBLY__
27
28extern void machine_shutdown(void);
29extern void *crash_notes;
30
31#endif /* __ASSEMBLY__ */
32
33#endif /* _SH_KEXEC_H */
diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h
index 3f18aa180516..550c50a7359e 100644
--- a/include/asm-sh/machvec.h
+++ b/include/asm-sh/machvec.h
@@ -18,44 +18,37 @@
18#include <asm/machvec_init.h> 18#include <asm/machvec_init.h>
19 19
20struct device; 20struct device;
21struct timeval;
22 21
23struct sh_machine_vector 22struct sh_machine_vector {
24{
25 int mv_nr_irqs; 23 int mv_nr_irqs;
26 24
27 unsigned char (*mv_inb)(unsigned long); 25 u8 (*mv_inb)(unsigned long);
28 unsigned short (*mv_inw)(unsigned long); 26 u16 (*mv_inw)(unsigned long);
29 unsigned int (*mv_inl)(unsigned long); 27 u32 (*mv_inl)(unsigned long);
30 void (*mv_outb)(unsigned char, unsigned long); 28 void (*mv_outb)(u8, unsigned long);
31 void (*mv_outw)(unsigned short, unsigned long); 29 void (*mv_outw)(u16, unsigned long);
32 void (*mv_outl)(unsigned int, unsigned long); 30 void (*mv_outl)(u32, unsigned long);
33 31
34 unsigned char (*mv_inb_p)(unsigned long); 32 u8 (*mv_inb_p)(unsigned long);
35 unsigned short (*mv_inw_p)(unsigned long); 33 u16 (*mv_inw_p)(unsigned long);
36 unsigned int (*mv_inl_p)(unsigned long); 34 u32 (*mv_inl_p)(unsigned long);
37 void (*mv_outb_p)(unsigned char, unsigned long); 35 void (*mv_outb_p)(u8, unsigned long);
38 void (*mv_outw_p)(unsigned short, unsigned long); 36 void (*mv_outw_p)(u16, unsigned long);
39 void (*mv_outl_p)(unsigned int, unsigned long); 37 void (*mv_outl_p)(u32, unsigned long);
40 38
41 void (*mv_insb)(unsigned long port, void *addr, unsigned long count); 39 void (*mv_insb)(unsigned long, void *dst, unsigned long count);
42 void (*mv_insw)(unsigned long port, void *addr, unsigned long count); 40 void (*mv_insw)(unsigned long, void *dst, unsigned long count);
43 void (*mv_insl)(unsigned long port, void *addr, unsigned long count); 41 void (*mv_insl)(unsigned long, void *dst, unsigned long count);
44 void (*mv_outsb)(unsigned long port, const void *addr, unsigned long count); 42 void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
45 void (*mv_outsw)(unsigned long port, const void *addr, unsigned long count); 43 void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
46 void (*mv_outsl)(unsigned long port, const void *addr, unsigned long count); 44 void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
47 45
48 unsigned char (*mv_readb)(unsigned long); 46 u8 (*mv_readb)(void __iomem *);
49 unsigned short (*mv_readw)(unsigned long); 47 u16 (*mv_readw)(void __iomem *);
50 unsigned int (*mv_readl)(unsigned long); 48 u32 (*mv_readl)(void __iomem *);
51 void (*mv_writeb)(unsigned char, unsigned long); 49 void (*mv_writeb)(u8, void __iomem *);
52 void (*mv_writew)(unsigned short, unsigned long); 50 void (*mv_writew)(u16, void __iomem *);
53 void (*mv_writel)(unsigned int, unsigned long); 51 void (*mv_writel)(u32, void __iomem *);
54
55 void* (*mv_ioremap)(unsigned long offset, unsigned long size);
56 void (*mv_iounmap)(void *addr);
57
58 unsigned long (*mv_isa_port2addr)(unsigned long offset);
59 52
60 int (*mv_irq_demux)(int irq); 53 int (*mv_irq_demux)(int irq);
61 54
@@ -66,6 +59,9 @@ struct sh_machine_vector
66 59
67 void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, gfp_t); 60 void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, gfp_t);
68 int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t); 61 int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t);
62
63 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
64 void (*mv_ioport_unmap)(void __iomem *);
69}; 65};
70 66
71extern struct sh_machine_vector sh_mv; 67extern struct sh_machine_vector sh_mv;
diff --git a/include/asm-sh/timer.h b/include/asm-sh/timer.h
new file mode 100644
index 000000000000..dd6579c0b04c
--- /dev/null
+++ b/include/asm-sh/timer.h
@@ -0,0 +1,42 @@
1#ifndef __ASM_SH_TIMER_H
2#define __ASM_SH_TIMER_H
3
4#include <linux/sysdev.h>
5#include <asm/cpu/timer.h>
6
7struct sys_timer_ops {
8 int (*init)(void);
9 unsigned long (*get_offset)(void);
10 unsigned long (*get_frequency)(void);
11};
12
13struct sys_timer {
14 const char *name;
15
16 struct sys_device dev;
17 struct sys_timer_ops *ops;
18};
19
20#define TICK_SIZE (tick_nsec / 1000)
21
22extern struct sys_timer tmu_timer;
23extern struct sys_timer *sys_timer;
24
25static inline unsigned long get_timer_offset(void)
26{
27 return sys_timer->ops->get_offset();
28}
29
30static inline unsigned long get_timer_frequency(void)
31{
32 return sys_timer->ops->get_frequency();
33}
34
35/* arch/sh/kernel/timers/timer.c */
36struct sys_timer *get_sys_timer(void);
37
38/* arch/sh/kernel/time.c */
39void handle_timer_tick(struct pt_regs *);
40
41#endif /* __ASM_SH_TIMER_H */
42
diff --git a/include/asm-x86_64/ia32.h b/include/asm-x86_64/ia32.h
index c7bc9c0525ba..e6b7f2234e43 100644
--- a/include/asm-x86_64/ia32.h
+++ b/include/asm-x86_64/ia32.h
@@ -169,6 +169,8 @@ int ia32_child_tls(struct task_struct *p, struct pt_regs *childregs);
169struct linux_binprm; 169struct linux_binprm;
170extern int ia32_setup_arg_pages(struct linux_binprm *bprm, 170extern int ia32_setup_arg_pages(struct linux_binprm *bprm,
171 unsigned long stack_top, int exec_stack); 171 unsigned long stack_top, int exec_stack);
172struct mm_struct;
173extern void ia32_pick_mmap_layout(struct mm_struct *mm);
172 174
173#endif 175#endif
174 176
diff --git a/include/asm-x86_64/irq.h b/include/asm-x86_64/irq.h
index fb724ba37ae6..9db5a1b4f7b1 100644
--- a/include/asm-x86_64/irq.h
+++ b/include/asm-x86_64/irq.h
@@ -36,7 +36,7 @@
36#define NR_IRQ_VECTORS NR_IRQS 36#define NR_IRQ_VECTORS NR_IRQS
37#else 37#else
38#define NR_IRQS 224 38#define NR_IRQS 224
39#define NR_IRQ_VECTORS 1024 39#define NR_IRQ_VECTORS (32 * NR_CPUS)
40#endif 40#endif
41 41
42static __inline__ int irq_canonicalize(int irq) 42static __inline__ int irq_canonicalize(int irq)
diff --git a/include/asm-x86_64/page.h b/include/asm-x86_64/page.h
index dcbb4fcd9a18..615e3e494929 100644
--- a/include/asm-x86_64/page.h
+++ b/include/asm-x86_64/page.h
@@ -26,6 +26,13 @@
26#define IRQSTACK_ORDER 2 26#define IRQSTACK_ORDER 2
27#define IRQSTACKSIZE (PAGE_SIZE << IRQSTACK_ORDER) 27#define IRQSTACKSIZE (PAGE_SIZE << IRQSTACK_ORDER)
28 28
29#define STACKFAULT_STACK 1
30#define DOUBLEFAULT_STACK 2
31#define NMI_STACK 3
32#define DEBUG_STACK 4
33#define MCE_STACK 5
34#define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
35
29#define LARGE_PAGE_MASK (~(LARGE_PAGE_SIZE-1)) 36#define LARGE_PAGE_MASK (~(LARGE_PAGE_SIZE-1))
30#define LARGE_PAGE_SIZE (1UL << PMD_SHIFT) 37#define LARGE_PAGE_SIZE (1UL << PMD_SHIFT)
31 38
diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h
index 87a282b1043a..8c8d88c036ed 100644
--- a/include/asm-x86_64/processor.h
+++ b/include/asm-x86_64/processor.h
@@ -273,13 +273,6 @@ struct thread_struct {
273#define INIT_MMAP \ 273#define INIT_MMAP \
274{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } 274{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
275 275
276#define STACKFAULT_STACK 1
277#define DOUBLEFAULT_STACK 2
278#define NMI_STACK 3
279#define DEBUG_STACK 4
280#define MCE_STACK 5
281#define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
282
283#define start_thread(regs,new_rip,new_rsp) do { \ 276#define start_thread(regs,new_rip,new_rsp) do { \
284 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \ 277 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
285 load_gs_index(0); \ 278 load_gs_index(0); \
@@ -484,4 +477,6 @@ extern unsigned long boot_option_idle_override;
484/* Boot loader type from the setup header */ 477/* Boot loader type from the setup header */
485extern int bootloader_type; 478extern int bootloader_type;
486 479
480#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
481
487#endif /* __ASM_X86_64_PROCESSOR_H */ 482#endif /* __ASM_X86_64_PROCESSOR_H */
diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h
index 0eacbefb7dd0..a73f0c789d8b 100644
--- a/include/asm-x86_64/system.h
+++ b/include/asm-x86_64/system.h
@@ -354,11 +354,6 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
354#define local_irq_disable() __asm__ __volatile__("cli": : :"memory") 354#define local_irq_disable() __asm__ __volatile__("cli": : :"memory")
355#define local_irq_enable() __asm__ __volatile__("sti": : :"memory") 355#define local_irq_enable() __asm__ __volatile__("sti": : :"memory")
356 356
357/* used in the idle loop; sti takes one instruction cycle to complete */
358#define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory")
359/* used when interrupts are already enabled or to shutdown the processor */
360#define halt() __asm__ __volatile__("hlt": : :"memory")
361
362#define irqs_disabled() \ 357#define irqs_disabled() \
363({ \ 358({ \
364 unsigned long flags; \ 359 unsigned long flags; \
@@ -370,6 +365,11 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
370#define local_irq_save(x) do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_save \n\t pushfq ; popq %0 ; cli":"=g" (x): /* no input */ :"memory"); } while (0) 365#define local_irq_save(x) do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_save \n\t pushfq ; popq %0 ; cli":"=g" (x): /* no input */ :"memory"); } while (0)
371#endif 366#endif
372 367
368/* used in the idle loop; sti takes one instruction cycle to complete */
369#define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory")
370/* used when interrupts are already enabled or to shutdown the processor */
371#define halt() __asm__ __volatile__("hlt": : :"memory")
372
373void cpu_idle_wait(void); 373void cpu_idle_wait(void);
374 374
375extern unsigned long arch_align_stack(unsigned long sp); 375extern unsigned long arch_align_stack(unsigned long sp);
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 552cedfa6064..b77f2608eef9 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1290,6 +1290,9 @@ extern void mnt_set_mountpoint(struct vfsmount *, struct dentry *,
1290 1290
1291extern int vfs_statfs(struct super_block *, struct kstatfs *); 1291extern int vfs_statfs(struct super_block *, struct kstatfs *);
1292 1292
1293/* /sys/fs */
1294extern struct subsystem fs_subsys;
1295
1293#define FLOCK_VERIFY_READ 1 1296#define FLOCK_VERIFY_READ 1
1294#define FLOCK_VERIFY_WRITE 2 1297#define FLOCK_VERIFY_WRITE 2
1295 1298
diff --git a/include/linux/init.h b/include/linux/init.h
index 59008c3826cf..ff8d8b8632f4 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -241,6 +241,18 @@ void __init parse_early_param(void);
241#define __cpuexitdata __exitdata 241#define __cpuexitdata __exitdata
242#endif 242#endif
243 243
244#ifdef CONFIG_MEMORY_HOTPLUG
245#define __meminit
246#define __meminitdata
247#define __memexit
248#define __memexitdata
249#else
250#define __meminit __init
251#define __meminitdata __initdata
252#define __memexit __exit
253#define __memexitdata __exitdata
254#endif
255
244/* Functions marked as __devexit may be discarded at kernel link time, depending 256/* Functions marked as __devexit may be discarded at kernel link time, depending
245 on config options. Newer versions of binutils detect references from 257 on config options. Newer versions of binutils detect references from
246 retained sections to discarded sections and flag an error. Pointers to 258 retained sections to discarded sections and flag an error. Pointers to
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index 94abc07cb164..a311f58c8a7c 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -119,6 +119,7 @@ extern struct kimage *kexec_image;
119#define KEXEC_ARCH_PPC64 (21 << 16) 119#define KEXEC_ARCH_PPC64 (21 << 16)
120#define KEXEC_ARCH_IA_64 (50 << 16) 120#define KEXEC_ARCH_IA_64 (50 << 16)
121#define KEXEC_ARCH_S390 (22 << 16) 121#define KEXEC_ARCH_S390 (22 << 16)
122#define KEXEC_ARCH_SH (42 << 16)
122 123
123#define KEXEC_FLAGS (KEXEC_ON_CRASH) /* List of defined/legal kexec flags */ 124#define KEXEC_FLAGS (KEXEC_ON_CRASH) /* List of defined/legal kexec flags */
124 125
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 09:09:14 -0500