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-rw-r--r--include/asm-xtensa/coprocessor.h209
-rw-r--r--include/asm-xtensa/elf.h15
-rw-r--r--include/asm-xtensa/processor.h13
-rw-r--r--include/asm-xtensa/ptrace.h44
-rw-r--r--include/asm-xtensa/regs.h9
-rw-r--r--include/asm-xtensa/sigcontext.h1
-rw-r--r--include/asm-xtensa/system.h39
-rw-r--r--include/asm-xtensa/thread_info.h21
-rw-r--r--include/asm-xtensa/variant-fsf/tie-asm.h70
-rw-r--r--include/asm-xtensa/variant-fsf/tie.h75
10 files changed, 352 insertions, 144 deletions
diff --git a/include/asm-xtensa/coprocessor.h b/include/asm-xtensa/coprocessor.h
index aa2121034558..e5849bb9f6cf 100644
--- a/include/asm-xtensa/coprocessor.h
+++ b/include/asm-xtensa/coprocessor.h
@@ -5,81 +5,168 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 2003 - 2005 Tensilica Inc. 8 * Copyright (C) 2003 - 2007 Tensilica Inc.
9 */ 9 */
10 10
11
11#ifndef _XTENSA_COPROCESSOR_H 12#ifndef _XTENSA_COPROCESSOR_H
12#define _XTENSA_COPROCESSOR_H 13#define _XTENSA_COPROCESSOR_H
13 14
14#include <asm/variant/core.h> 15#include <linux/stringify.h>
15#include <asm/variant/tie.h> 16#include <asm/variant/tie.h>
17#include <asm/types.h>
18
19#ifdef __ASSEMBLY__
20# include <asm/variant/tie-asm.h>
21
22.macro xchal_sa_start a b
23 .set .Lxchal_pofs_, 0
24 .set .Lxchal_ofs_, 0
25.endm
26
27.macro xchal_sa_align ptr minofs maxofs ofsalign totalign
28 .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
29 .set .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
30.endm
31
32#define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \
33 | XTHAL_SAS_CC \
34 | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )
35
36.macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
37 .if XTREGS_OPT_SIZE > 0
38 addi \clb, \ptr, \offset
39 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
40 .endif
41.endm
42
43.macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
44 .if XTREGS_OPT_SIZE > 0
45 addi \clb, \ptr, \offset
46 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
47 .endif
48.endm
49#undef _SELECT
50
51#define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \
52 | XTHAL_SAS_NOCC \
53 | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )
54
55.macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
56 .if XTREGS_USER_SIZE > 0
57 addi \clb, \ptr, \offset
58 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
59 .endif
60.endm
61
62.macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
63 .if XTREGS_USER_SIZE > 0
64 addi \clb, \ptr, \offset
65 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
66 .endif
67.endm
68#undef _SELECT
69
70
71
72#endif /* __ASSEMBLY__ */
16 73
17#if !XCHAL_HAVE_CP
18
19#define XTENSA_CP_EXTRA_OFFSET 0
20#define XTENSA_CP_EXTRA_ALIGN 1 /* must be a power of 2 */
21#define XTENSA_CP_EXTRA_SIZE 0
22
23#else
24
25#define XTOFS(last_start,last_size,align) \
26 ((last_start+last_size+align-1) & -align)
27
28#define XTENSA_CP_EXTRA_OFFSET 0
29#define XTENSA_CP_EXTRA_ALIGN XCHAL_EXTRA_SA_ALIGN
30
31#define XTENSA_CPE_CP0_OFFSET \
32 XTOFS(XTENSA_CP_EXTRA_OFFSET, XCHAL_EXTRA_SA_SIZE, XCHAL_CP0_SA_ALIGN)
33#define XTENSA_CPE_CP1_OFFSET \
34 XTOFS(XTENSA_CPE_CP0_OFFSET, XCHAL_CP0_SA_SIZE, XCHAL_CP1_SA_ALIGN)
35#define XTENSA_CPE_CP2_OFFSET \
36 XTOFS(XTENSA_CPE_CP1_OFFSET, XCHAL_CP1_SA_SIZE, XCHAL_CP2_SA_ALIGN)
37#define XTENSA_CPE_CP3_OFFSET \
38 XTOFS(XTENSA_CPE_CP2_OFFSET, XCHAL_CP2_SA_SIZE, XCHAL_CP3_SA_ALIGN)
39#define XTENSA_CPE_CP4_OFFSET \
40 XTOFS(XTENSA_CPE_CP3_OFFSET, XCHAL_CP3_SA_SIZE, XCHAL_CP4_SA_ALIGN)
41#define XTENSA_CPE_CP5_OFFSET \
42 XTOFS(XTENSA_CPE_CP4_OFFSET, XCHAL_CP4_SA_SIZE, XCHAL_CP5_SA_ALIGN)
43#define XTENSA_CPE_CP6_OFFSET \
44 XTOFS(XTENSA_CPE_CP5_OFFSET, XCHAL_CP5_SA_SIZE, XCHAL_CP6_SA_ALIGN)
45#define XTENSA_CPE_CP7_OFFSET \
46 XTOFS(XTENSA_CPE_CP6_OFFSET, XCHAL_CP6_SA_SIZE, XCHAL_CP7_SA_ALIGN)
47#define XTENSA_CP_EXTRA_SIZE \
48 XTOFS(XTENSA_CPE_CP7_OFFSET, XCHAL_CP7_SA_SIZE, 16)
49
50#if XCHAL_CP_NUM > 0
51# ifndef __ASSEMBLY__
52/* 74/*
53 * Tasks that own contents of (last user) each coprocessor. 75 * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
54 * Entries are 0 for not-owned or non-existent coprocessors. 76 *
55 * Note: The size of this structure is fixed to 8 bytes in entry.S 77 * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
78 *
56 */ 79 */
57typedef struct {
58 struct task_struct *owner; /* owner */
59 int offset; /* offset in cpextra space. */
60} coprocessor_info_t;
61# else
62# define COPROCESSOR_INFO_OWNER 0
63# define COPROCESSOR_INFO_OFFSET 4
64# define COPROCESSOR_INFO_SIZE 8
65# endif
66#endif
67#endif /* XCHAL_HAVE_CP */
68 80
81#define XTENSA_HAVE_COPROCESSOR(x) \
82 ((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
83#define XTENSA_HAVE_COPROCESSORS \
84 (XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
85#define XTENSA_HAVE_IO_PORT(x) \
86 (XCHAL_CP_PORT_MASK & (1 << (x)))
87#define XTENSA_HAVE_IO_PORTS \
88 XCHAL_CP_PORT_MASK
69 89
70#ifndef __ASSEMBLY__ 90#ifndef __ASSEMBLY__
71# if XCHAL_CP_NUM > 0
72struct task_struct;
73extern void release_coprocessors (struct task_struct*);
74extern void save_coprocessor_registers(void*, int);
75# else
76# define release_coprocessors(task)
77# endif
78 91
79typedef unsigned char cp_state_t[XTENSA_CP_EXTRA_SIZE]
80 __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
81 92
82#endif /* !__ASSEMBLY__ */ 93#if XCHAL_HAVE_CP
83 94
95#define RSR_CPENABLE(x) do { \
96 __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
97 } while(0);
98#define WSR_CPENABLE(x) do { \
99 __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \
100 :: "a" (x)); \
101 } while(0);
84 102
103#endif /* XCHAL_HAVE_CP */
104
105
106/*
107 * Additional registers.
108 * We define three types of additional registers:
109 * ext: extra registers that are used by the compiler
110 * cpn: optional registers that can be used by a user application
111 * cpX: coprocessor registers that can only be used if the corresponding
112 * CPENABLE bit is set.
113 */
114
115#define XCHAL_SA_REG(list,compiler,x,type,y,name,z,align,size,...) \
116 __REG ## list (compiler, type, name, size, align)
117
118#define __REG0(compiler,t,name,s,a) __REG0_ ## compiler (name)
119#define __REG1(compiler,t,name,s,a) __REG1_ ## compiler (name)
120#define __REG2(c,type,...) __REG2_ ## type (__VA_ARGS__)
121
122#define __REG0_0(name)
123#define __REG0_1(name) __u32 name;
124#define __REG1_0(name) __u32 name;
125#define __REG1_1(name)
126#define __REG2_0(n,s,a) __u32 name;
127#define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
128#define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
129
130typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
131 __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
132typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
133 __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
134
135#if XTENSA_HAVE_COPROCESSORS
136
137typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
138 __attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
139typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
140 __attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
141typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
142 __attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
143typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
144 __attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
145typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
146 __attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
147typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
148 __attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
149typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
150 __attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
151typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
152 __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
153
154extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
155extern void coprocessor_save(void*, int);
156extern void coprocessor_load(void*, int);
157extern void coprocessor_flush(struct thread_info*, int);
158extern void coprocessor_restore(struct thread_info*, int);
159
160extern void coprocessor_release_all(struct thread_info*);
161extern void coprocessor_flush_all(struct thread_info*);
162
163static inline void coprocessor_clear_cpenable(void)
164{
165 unsigned long i = 0;
166 WSR_CPENABLE(i);
167}
168
169#endif /* XTENSA_HAVE_COPROCESSORS */
170
171#endif /* !__ASSEMBLY__ */
85#endif /* _XTENSA_COPROCESSOR_H */ 172#endif /* _XTENSA_COPROCESSOR_H */
diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h
index 86479b86c02e..11103e07d028 100644
--- a/include/asm-xtensa/elf.h
+++ b/include/asm-xtensa/elf.h
@@ -173,6 +173,21 @@ extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);
173 _r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \ 173 _r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \
174 } while (0) 174 } while (0)
175 175
176typedef struct {
177 xtregs_opt_t opt;
178 xtregs_user_t user;
179#if XTENSA_HAVE_COPROCESSORS
180 xtregs_cp0_t cp0;
181 xtregs_cp1_t cp1;
182 xtregs_cp2_t cp2;
183 xtregs_cp3_t cp3;
184 xtregs_cp4_t cp4;
185 xtregs_cp5_t cp5;
186 xtregs_cp6_t cp6;
187 xtregs_cp7_t cp7;
188#endif
189} elf_xtregs_t;
190
176#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT) 191#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
177 192
178struct task_struct; 193struct task_struct;
diff --git a/include/asm-xtensa/processor.h b/include/asm-xtensa/processor.h
index 96408f436624..4918a4e96d42 100644
--- a/include/asm-xtensa/processor.h
+++ b/include/asm-xtensa/processor.h
@@ -103,10 +103,6 @@ struct thread_struct {
103 unsigned long dbreaka[XCHAL_NUM_DBREAK]; 103 unsigned long dbreaka[XCHAL_NUM_DBREAK];
104 unsigned long dbreakc[XCHAL_NUM_DBREAK]; 104 unsigned long dbreakc[XCHAL_NUM_DBREAK];
105 105
106 /* Allocate storage for extra state and coprocessor state. */
107 unsigned char cp_save[XTENSA_CP_EXTRA_SIZE]
108 __attribute__ ((aligned(XTENSA_CP_EXTRA_ALIGN)));
109
110 /* Make structure 16 bytes aligned. */ 106 /* Make structure 16 bytes aligned. */
111 int align[0] __attribute__ ((aligned(16))); 107 int align[0] __attribute__ ((aligned(16)));
112}; 108};
@@ -162,21 +158,16 @@ struct thread_struct {
162struct task_struct; 158struct task_struct;
163struct mm_struct; 159struct mm_struct;
164 160
165// FIXME: do we need release_thread for CP??
166/* Free all resources held by a thread. */ 161/* Free all resources held by a thread. */
167#define release_thread(thread) do { } while(0) 162#define release_thread(thread) do { } while(0)
168 163
169// FIXME: do we need prepare_to_copy (lazy status) for CP??
170/* Prepare to copy thread state - unlazy all lazy status */ 164/* Prepare to copy thread state - unlazy all lazy status */
171#define prepare_to_copy(tsk) do { } while (0) 165extern void prepare_to_copy(struct task_struct*);
172 166
173/* 167/* Create a kernel thread without removing it from tasklists */
174 * create a kernel thread without removing it from tasklists
175 */
176extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); 168extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
177 169
178/* Copy and release all segment info associated with a VM */ 170/* Copy and release all segment info associated with a VM */
179
180#define copy_segments(p, mm) do { } while(0) 171#define copy_segments(p, mm) do { } while(0)
181#define release_segments(mm) do { } while(0) 172#define release_segments(mm) do { } while(0)
182#define forget_segments() do { } while (0) 173#define forget_segments() do { } while (0)
diff --git a/include/asm-xtensa/ptrace.h b/include/asm-xtensa/ptrace.h
index 77ff02d307bb..422c73e26937 100644
--- a/include/asm-xtensa/ptrace.h
+++ b/include/asm-xtensa/ptrace.h
@@ -53,33 +53,30 @@
53 53
54/* Registers used by strace */ 54/* Registers used by strace */
55 55
56#define REG_A_BASE 0xfc000000 56#define REG_A_BASE 0x0000
57#define REG_AR_BASE 0x04000000 57#define REG_AR_BASE 0x0100
58#define REG_PC 0x14000000 58#define REG_PC 0x0020
59#define REG_PS 0x080000e6 59#define REG_PS 0x02e6
60#define REG_WB 0x08000048 60#define REG_WB 0x0248
61#define REG_WS 0x08000049 61#define REG_WS 0x0249
62#define REG_LBEG 0x08000000 62#define REG_LBEG 0x0200
63#define REG_LEND 0x08000001 63#define REG_LEND 0x0201
64#define REG_LCOUNT 0x08000002 64#define REG_LCOUNT 0x0202
65#define REG_SAR 0x08000003 65#define REG_SAR 0x0203
66#define REG_DEPC 0x080000c0 66
67#define REG_EXCCAUSE 0x080000e8 67#define SYSCALL_NR 0x00ff
68#define REG_EXCVADDR 0x080000ee
69#define SYSCALL_NR 0x1
70
71#define AR_REGNO_TO_A_REGNO(ar, wb) (ar - wb*4) & ~(XCHAL_NUM_AREGS - 1)
72 68
73/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */ 69/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */
74 70
75#define PTRACE_GETREGS 12 71#define PTRACE_GETREGS 12
76#define PTRACE_SETREGS 13 72#define PTRACE_SETREGS 13
77#define PTRACE_GETFPREGS 14 73#define PTRACE_GETXTREGS 18
78#define PTRACE_SETFPREGS 15 74#define PTRACE_SETXTREGS 19
79#define PTRACE_GETFPREGSIZE 18
80 75
81#ifndef __ASSEMBLY__ 76#ifndef __ASSEMBLY__
82 77
78#ifdef __KERNEL__
79
83/* 80/*
84 * This struct defines the way the registers are stored on the 81 * This struct defines the way the registers are stored on the
85 * kernel stack during a system call or other kernel entry. 82 * kernel stack during a system call or other kernel entry.
@@ -102,6 +99,9 @@ struct pt_regs {
102 unsigned long icountlevel; /* 60 */ 99 unsigned long icountlevel; /* 60 */
103 int reserved[1]; /* 64 */ 100 int reserved[1]; /* 64 */
104 101
102 /* Additional configurable registers that are used by the compiler. */
103 xtregs_opt_t xtregs_opt;
104
105 /* Make sure the areg field is 16 bytes aligned. */ 105 /* Make sure the areg field is 16 bytes aligned. */
106 int align[0] __attribute__ ((aligned(16))); 106 int align[0] __attribute__ ((aligned(16)));
107 107
@@ -111,8 +111,6 @@ struct pt_regs {
111 unsigned long areg[16]; /* 128 (64) */ 111 unsigned long areg[16]; /* 128 (64) */
112}; 112};
113 113
114#ifdef __KERNEL__
115
116#include <asm/variant/core.h> 114#include <asm/variant/core.h>
117 115
118# define task_pt_regs(tsk) ((struct pt_regs*) \ 116# define task_pt_regs(tsk) ((struct pt_regs*) \
diff --git a/include/asm-xtensa/regs.h b/include/asm-xtensa/regs.h
index c913d259faaa..d4baed246928 100644
--- a/include/asm-xtensa/regs.h
+++ b/include/asm-xtensa/regs.h
@@ -100,7 +100,14 @@
100#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27 100#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
101#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 101#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
102#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 102#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
103#define EXCCAUSE_FLOATING_POINT 40 103#define EXCCAUSE_COPROCESSOR0_DISABLED 32
104#define EXCCAUSE_COPROCESSOR1_DISABLED 33
105#define EXCCAUSE_COPROCESSOR2_DISABLED 34
106#define EXCCAUSE_COPROCESSOR3_DISABLED 35
107#define EXCCAUSE_COPROCESSOR4_DISABLED 36
108#define EXCCAUSE_COPROCESSOR5_DISABLED 37
109#define EXCCAUSE_COPROCESSOR6_DISABLED 38
110#define EXCCAUSE_COPROCESSOR7_DISABLED 39
104 111
105/* PS register fields. */ 112/* PS register fields. */
106 113
diff --git a/include/asm-xtensa/sigcontext.h b/include/asm-xtensa/sigcontext.h
index dff3c54a3c12..03383af8c3b7 100644
--- a/include/asm-xtensa/sigcontext.h
+++ b/include/asm-xtensa/sigcontext.h
@@ -22,6 +22,7 @@ struct sigcontext {
22 unsigned long sc_acclo; 22 unsigned long sc_acclo;
23 unsigned long sc_acchi; 23 unsigned long sc_acchi;
24 unsigned long sc_a[16]; 24 unsigned long sc_a[16];
25 void *sc_xtregs;
25}; 26};
26 27
27#endif /* _XTENSA_SIGCONTEXT_H */ 28#endif /* _XTENSA_SIGCONTEXT_H */
diff --git a/include/asm-xtensa/system.h b/include/asm-xtensa/system.h
index e0cb9116d8ab..62b1e8f3c13c 100644
--- a/include/asm-xtensa/system.h
+++ b/include/asm-xtensa/system.h
@@ -46,42 +46,6 @@ static inline int irqs_disabled(void)
46 return flags & 0xf; 46 return flags & 0xf;
47} 47}
48 48
49#define RSR_CPENABLE(x) do { \
50 __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
51 } while(0);
52#define WSR_CPENABLE(x) do { \
53 __asm__ __volatile__("wsr %0," __stringify(CPENABLE)";rsync" \
54 :: "a" (x));} while(0);
55
56#define clear_cpenable() __clear_cpenable()
57
58static inline void __clear_cpenable(void)
59{
60#if XCHAL_HAVE_CP
61 unsigned long i = 0;
62 WSR_CPENABLE(i);
63#endif
64}
65
66static inline void enable_coprocessor(int i)
67{
68#if XCHAL_HAVE_CP
69 int cp;
70 RSR_CPENABLE(cp);
71 cp |= 1 << i;
72 WSR_CPENABLE(cp);
73#endif
74}
75
76static inline void disable_coprocessor(int i)
77{
78#if XCHAL_HAVE_CP
79 int cp;
80 RSR_CPENABLE(cp);
81 cp &= ~(1 << i);
82 WSR_CPENABLE(cp);
83#endif
84}
85 49
86#define smp_read_barrier_depends() do { } while(0) 50#define smp_read_barrier_depends() do { } while(0)
87#define read_barrier_depends() do { } while(0) 51#define read_barrier_depends() do { } while(0)
@@ -111,7 +75,6 @@ extern void *_switch_to(void *last, void *next);
111 75
112#define switch_to(prev,next,last) \ 76#define switch_to(prev,next,last) \
113do { \ 77do { \
114 clear_cpenable(); \
115 (last) = _switch_to(prev, next); \ 78 (last) = _switch_to(prev, next); \
116} while(0) 79} while(0)
117 80
@@ -244,7 +207,7 @@ static inline void spill_registers(void)
244 "wsr a13," __stringify(SAR) "\n\t" 207 "wsr a13," __stringify(SAR) "\n\t"
245 "wsr a14," __stringify(PS) "\n\t" 208 "wsr a14," __stringify(PS) "\n\t"
246 :: "a" (&a0), "a" (&ps) 209 :: "a" (&a0), "a" (&ps)
247 : "a2", "a3", "a12", "a13", "a14", "a15", "memory"); 210 : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
248} 211}
249 212
250#define arch_align_stack(x) (x) 213#define arch_align_stack(x) (x)
diff --git a/include/asm-xtensa/thread_info.h b/include/asm-xtensa/thread_info.h
index 52c958285bcb..a2c640682ed9 100644
--- a/include/asm-xtensa/thread_info.h
+++ b/include/asm-xtensa/thread_info.h
@@ -27,6 +27,21 @@
27 27
28#ifndef __ASSEMBLY__ 28#ifndef __ASSEMBLY__
29 29
30#if XTENSA_HAVE_COPROCESSORS
31
32typedef struct xtregs_coprocessor {
33 xtregs_cp0_t cp0;
34 xtregs_cp1_t cp1;
35 xtregs_cp2_t cp2;
36 xtregs_cp3_t cp3;
37 xtregs_cp4_t cp4;
38 xtregs_cp5_t cp5;
39 xtregs_cp6_t cp6;
40 xtregs_cp7_t cp7;
41} xtregs_coprocessor_t;
42
43#endif
44
30struct thread_info { 45struct thread_info {
31 struct task_struct *task; /* main task structure */ 46 struct task_struct *task; /* main task structure */
32 struct exec_domain *exec_domain; /* execution domain */ 47 struct exec_domain *exec_domain; /* execution domain */
@@ -38,7 +53,13 @@ struct thread_info {
38 mm_segment_t addr_limit; /* thread address space */ 53 mm_segment_t addr_limit; /* thread address space */
39 struct restart_block restart_block; 54 struct restart_block restart_block;
40 55
56 unsigned long cpenable;
41 57
58 /* Allocate storage for extra user states and coprocessor states. */
59#if XTENSA_HAVE_COPROCESSORS
60 xtregs_coprocessor_t xtregs_cp;
61#endif
62 xtregs_user_t xtregs_user;
42}; 63};
43 64
44#else /* !__ASSEMBLY__ */ 65#else /* !__ASSEMBLY__ */
diff --git a/include/asm-xtensa/variant-fsf/tie-asm.h b/include/asm-xtensa/variant-fsf/tie-asm.h
new file mode 100644
index 000000000000..68a73bf4ffc5
--- /dev/null
+++ b/include/asm-xtensa/variant-fsf/tie-asm.h
@@ -0,0 +1,70 @@
1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_ASM_H
14#define _XTENSA_CORE_TIE_ASM_H
15
16/* Selection parameter values for save-area save/restore macros: */
17/* Option vs. TIE: */
18#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20/* Whether used automatically by compiler: */
21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27/* Misc */
28#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29
30
31
32/* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
34 * Save area ptr (clobbered): ptr (1 byte aligned)
35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36 */
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 xchal_sa_start \continue, \ofs
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
40 xchal_sa_align \ptr, 0, 1024-4, 4, 4
41 rur \at1, THREADPTR // threadptr option
42 s32i \at1, \ptr, .Lxchal_ofs_ + 0
43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
44 .endif
45 .endm // xchal_ncp_store
46
47/* Macro to save all non-coprocessor (extra) custom TIE and optional state
48 * (not including zero-overhead loop registers).
49 * Save area ptr (clobbered): ptr (1 byte aligned)
50 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
51 */
52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
53 xchal_sa_start \continue, \ofs
54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
55 xchal_sa_align \ptr, 0, 1024-4, 4, 4
56 l32i \at1, \ptr, .Lxchal_ofs_ + 0
57 wur \at1, THREADPTR // threadptr option
58 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
59 .endif
60 .endm // xchal_ncp_load
61
62
63
64#define XCHAL_NCP_NUM_ATMPS 1
65
66
67#define XCHAL_SA_NUM_ATMPS 1
68
69#endif /*_XTENSA_CORE_TIE_ASM_H*/
70
diff --git a/include/asm-xtensa/variant-fsf/tie.h b/include/asm-xtensa/variant-fsf/tie.h
index a73c71664918..bf4020116df5 100644
--- a/include/asm-xtensa/variant-fsf/tie.h
+++ b/include/asm-xtensa/variant-fsf/tie.h
@@ -1,22 +1,77 @@
1/* 1/*
2 * Xtensa processor core configuration information. 2 * This header file describes this specific Xtensa processor's TIE extensions
3 * that extend basic Xtensa core functionality. It is customized to this
4 * Xtensa processor configuration.
3 * 5 *
4 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 8 * for more details.
7 * 9 *
8 * Copyright (C) 1999-2006 Tensilica Inc. 10 * Copyright (C) 1999-2007 Tensilica Inc.
9 */ 11 */
10 12
11#ifndef XTENSA_TIE_H 13#ifndef _XTENSA_CORE_TIE_H
12#define XTENSA_TIE_H 14#define _XTENSA_CORE_TIE_H
13
14/*----------------------------------------------------------------------
15 COPROCESSORS and EXTRA STATE
16 ----------------------------------------------------------------------*/
17 15
18#define XCHAL_CP_NUM 0 /* number of coprocessors */ 16#define XCHAL_CP_NUM 0 /* number of coprocessors */
19#define XCHAL_CP_MASK 0x00 17#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
18#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
19#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
20
21/* Basic parameters of each coprocessor: */
22#define XCHAL_CP7_NAME "XTIOP"
23#define XCHAL_CP7_IDENT XTIOP
24#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
25#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
26#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
27
28/* Filler info for unassigned coprocessors, to simplify arrays etc: */
29#define XCHAL_NCP_SA_SIZE 0
30#define XCHAL_NCP_SA_ALIGN 1
31#define XCHAL_CP0_SA_SIZE 0
32#define XCHAL_CP0_SA_ALIGN 1
33#define XCHAL_CP1_SA_SIZE 0
34#define XCHAL_CP1_SA_ALIGN 1
35#define XCHAL_CP2_SA_SIZE 0
36#define XCHAL_CP2_SA_ALIGN 1
37#define XCHAL_CP3_SA_SIZE 0
38#define XCHAL_CP3_SA_ALIGN 1
39#define XCHAL_CP4_SA_SIZE 0
40#define XCHAL_CP4_SA_ALIGN 1
41#define XCHAL_CP5_SA_SIZE 0
42#define XCHAL_CP5_SA_ALIGN 1
43#define XCHAL_CP6_SA_SIZE 0
44#define XCHAL_CP6_SA_ALIGN 1
45
46/* Save area for non-coprocessor optional and custom (TIE) state: */
47#define XCHAL_NCP_SA_SIZE 0
48#define XCHAL_NCP_SA_ALIGN 1
49
50/* Total save area for optional and custom state (NCP + CPn): */
51#define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */
52#define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */
53
54#define XCHAL_NCP_SA_NUM 0
55#define XCHAL_NCP_SA_LIST(s)
56#define XCHAL_CP0_SA_NUM 0
57#define XCHAL_CP0_SA_LIST(s)
58#define XCHAL_CP1_SA_NUM 0
59#define XCHAL_CP1_SA_LIST(s)
60#define XCHAL_CP2_SA_NUM 0
61#define XCHAL_CP2_SA_LIST(s)
62#define XCHAL_CP3_SA_NUM 0
63#define XCHAL_CP3_SA_LIST(s)
64#define XCHAL_CP4_SA_NUM 0
65#define XCHAL_CP4_SA_LIST(s)
66#define XCHAL_CP5_SA_NUM 0
67#define XCHAL_CP5_SA_LIST(s)
68#define XCHAL_CP6_SA_NUM 0
69#define XCHAL_CP6_SA_LIST(s)
70#define XCHAL_CP7_SA_NUM 0
71#define XCHAL_CP7_SA_LIST(s)
72
73/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
74#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
20 75
21#endif /*XTENSA_CONFIG_TIE_H*/ 76#endif /*_XTENSA_CORE_TIE_H*/
22 77
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 19:33:41 -0500