2 files changed, 31 insertions, 102 deletions

diff --git a/include/linux/amba/pl022.h b/include/linux/amba/pl022.h
index e4836c6b3dd7..abf26cc47a2b 100644
--- a/include/linux/amba/pl022.h
+++ b/include/linux/amba/pl022.h
@@ -71,6 +71,7 @@ struct ssp_clock_params {
 
 /**
  * enum ssp_rx_endian - endianess of Rx FIFO Data
+ * this feature is only available in ST versionf of PL022
  */
 enum ssp_rx_endian {
         SSP_RX_MSB,
@@ -181,7 +182,8 @@ enum ssp_microwire_wait_state {
 };
 
 /**
- * enum Microwire - whether Full/Half Duplex
+ * enum ssp_duplex - whether Full/Half Duplex on microwire, only
+ * available in the ST Micro variant.
  * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
  *     SSPRXD not used
  * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
@@ -193,6 +195,31 @@ enum ssp_duplex {
 };
 
 /**
+ * enum ssp_clkdelay - an optional clock delay on the feedback clock
+ * only available in the ST Micro PL023 variant.
+ * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
+ * slave is sampled directly
+ * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
+ * a delay of T-dt
+ * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
+ * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
+ * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
+ * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
+ * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
+ * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
+ */
+enum ssp_clkdelay {
+        SSP_FEEDBACK_CLK_DELAY_NONE,
+        SSP_FEEDBACK_CLK_DELAY_1T,
+        SSP_FEEDBACK_CLK_DELAY_2T,
+        SSP_FEEDBACK_CLK_DELAY_3T,
+        SSP_FEEDBACK_CLK_DELAY_4T,
+        SSP_FEEDBACK_CLK_DELAY_5T,
+        SSP_FEEDBACK_CLK_DELAY_6T,
+        SSP_FEEDBACK_CLK_DELAY_7T
+};
+
+/**
  * CHIP select/deselect commands
  */
 enum ssp_chip_select {
@@ -235,6 +262,8 @@ struct pl022_ssp_controller {
  * @ctrl_len: Microwire interface: Control length
  * @wait_state: Microwire interface: Wait state
  * @duplex: Microwire interface: Full/Half duplex
+ * @clkdelay: on the PL023 variant, the delay in feeback clock cycles
+ * before sampling the incoming line
  * @cs_control: function pointer to board-specific function to
  * assert/deassert I/O port to control HW generation of devices chip-select.
  * @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph)
@@ -258,6 +287,7 @@ struct pl022_config_chip {
         enum ssp_microwire_ctrl_len ctrl_len;
         enum ssp_microwire_wait_state wait_state;
         enum ssp_duplex duplex;
+        enum ssp_clkdelay clkdelay;
         void (*cs_control) (u32 control);
 };
 
diff --git a/include/linux/spi/spi_bitbang.h b/include/linux/spi/spi_bitbang.h
index 3274c507b8a9..f987a2bee16a 100644
--- a/include/linux/spi/spi_bitbang.h
+++ b/include/linux/spi/spi_bitbang.h
@@ -1,24 +1,6 @@
 #ifndef __SPI_BITBANG_H
 #define __SPI_BITBANG_H
 
-/*
- * Mix this utility code with some glue code to get one of several types of
- * simple SPI master driver.  Two do polled word-at-a-time I/O:
- *
- *   -  GPIO/parport bitbangers.  Provide chipselect() and txrx_word[](),
- *      expanding the per-word routines from the inline templates below.
- *
- *   -  Drivers for controllers resembling bare shift registers.  Provide
- *      chipselect() and txrx_word[](), with custom setup()/cleanup() methods
- *      that use your controller's clock and chipselect registers.
- *
- * Some hardware works well with requests at spi_transfer scope:
- *
- *   -  Drivers leveraging smarter hardware, with fifos or DMA; or for half
- *      duplex (MicroWire) controllers.  Provide chipselect() and txrx_bufs(),
- *      and custom setup()/cleanup() methods.
- */
-
 #include <linux/workqueue.h>
 
 struct spi_bitbang {
@@ -68,86 +50,3 @@ extern int spi_bitbang_start(struct spi_bitbang *spi);
 extern int spi_bitbang_stop(struct spi_bitbang *spi);
 
 #endif  /* __SPI_BITBANG_H */
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef  EXPAND_BITBANG_TXRX
-
-/*
- * The code that knows what GPIO pins do what should have declared four
- * functions, ideally as inlines, before #defining EXPAND_BITBANG_TXRX
- * and including this header:
- *
- *  void setsck(struct spi_device *, int is_on);
- *  void setmosi(struct spi_device *, int is_on);
- *  int getmiso(struct spi_device *);
- *  void spidelay(unsigned);
- *
- * setsck()'s is_on parameter is a zero/nonzero boolean.
- *
- * setmosi()'s is_on parameter is a zero/nonzero boolean.
- *
- * getmiso() is required to return 0 or 1 only. Any other value is invalid
- * and will result in improper operation.
- *
- * A non-inlined routine would call bitbang_txrx_*() routines.  The
- * main loop could easily compile down to a handful of instructions,
- * especially if the delay is a NOP (to run at peak speed).
- *
- * Since this is software, the timings may not be exactly what your board's
- * chips need ... there may be several reasons you'd need to tweak timings
- * in these routines, not just make to make it faster or slower to match a
- * particular CPU clock rate.
- */
-
-static inline u32
-bitbang_txrx_be_cpha0(struct spi_device *spi,
-                unsigned nsecs, unsigned cpol,
-                u32 word, u8 bits)
-{
-        /* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
-
-        /* clock starts at inactive polarity */
-        for (word <<= (32 - bits); likely(bits); bits--) {
-
-                /* setup MSB (to slave) on trailing edge */
-                setmosi(spi, word & (1 << 31));
-                spidelay(nsecs);        /* T(setup) */
-
-                setsck(spi, !cpol);
-                spidelay(nsecs);
-
-                /* sample MSB (from slave) on leading edge */
-                word <<= 1;
-                word |= getmiso(spi);
-                setsck(spi, cpol);
-        }
-        return word;
-}
-
-static inline u32
-bitbang_txrx_be_cpha1(struct spi_device *spi,
-                unsigned nsecs, unsigned cpol,
-                u32 word, u8 bits)
-{
-        /* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
-
-        /* clock starts at inactive polarity */
-        for (word <<= (32 - bits); likely(bits); bits--) {
-
-                /* setup MSB (to slave) on leading edge */
-                setsck(spi, !cpol);
-                setmosi(spi, word & (1 << 31));
-                spidelay(nsecs); /* T(setup) */
-
-                setsck(spi, cpol);
-                spidelay(nsecs);
-
-                /* sample MSB (from slave) on trailing edge */
-                word <<= 1;
-                word |= getmiso(spi);
-        }
-        return word;
-}
-
-#endif  /* EXPAND_BITBANG_TXRX */