4 files changed, 91 insertions, 38 deletions

diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index d78d28a733b1..5fd33dc1fe3a 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -198,6 +198,9 @@ extern u32 vmcoreinfo_note[VMCOREINFO_NOTE_SIZE/4];
 extern size_t vmcoreinfo_size;
 extern size_t vmcoreinfo_max_size;
 
+/* flag to track if kexec reboot is in progress */
+extern bool kexec_in_progress;
+
 int __init parse_crashkernel(char *cmdline, unsigned long long system_ram,
                 unsigned long long *crash_size, unsigned long long *crash_base);
 int parse_crashkernel_high(char *cmdline, unsigned long long system_ram,
diff --git a/include/linux/msi.h b/include/linux/msi.h
index 009b02481436..92a2f991262a 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -60,10 +60,10 @@ void arch_teardown_msi_irq(unsigned int irq);
 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
 void arch_teardown_msi_irqs(struct pci_dev *dev);
 int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
-void arch_restore_msi_irqs(struct pci_dev *dev, int irq);
+void arch_restore_msi_irqs(struct pci_dev *dev);
 
 void default_teardown_msi_irqs(struct pci_dev *dev);
-void default_restore_msi_irqs(struct pci_dev *dev, int irq);
+void default_restore_msi_irqs(struct pci_dev *dev);
 u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
 u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag);
 
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 095eb44fcbb6..f7d1dcc002fa 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -224,7 +224,8 @@ enum pci_bus_speed {
 };
 
 struct pci_cap_saved_data {
-        char cap_nr;
+        u16 cap_nr;
+        bool cap_extended;
         unsigned int size;
         u32 data[0];
 };
@@ -351,7 +352,7 @@ struct pci_dev {
         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
 #ifdef CONFIG_PCI_MSI
         struct list_head msi_list;
-        struct kset *msi_kset;
+        const struct attribute_group **msi_irq_groups;
 #endif
         struct pci_vpd *vpd;
 #ifdef CONFIG_PCI_ATS
@@ -634,8 +635,7 @@ struct pci_driver {
  * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
  * @_table: device table name
  *
- * This macro is used to create a struct pci_device_id array (a device table)
- * in a generic manner.
+ * This macro is deprecated and should not be used in new code.
  */
 #define DEFINE_PCI_DEVICE_TABLE(_table) \
         const struct pci_device_id _table[]
@@ -938,6 +938,7 @@ bool pci_check_and_unmask_intx(struct pci_dev *dev);
 void pci_msi_off(struct pci_dev *dev);
 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
+int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
 int pci_wait_for_pending_transaction(struct pci_dev *dev);
 int pcix_get_max_mmrbc(struct pci_dev *dev);
 int pcix_get_mmrbc(struct pci_dev *dev);
@@ -976,6 +977,12 @@ struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
 int pci_load_and_free_saved_state(struct pci_dev *dev,
                                   struct pci_saved_state **state);
+struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
+struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
+                                                   u16 cap);
+int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
+int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
+                                u16 cap, unsigned int size);
 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
@@ -997,6 +1004,11 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
         return __pci_enable_wake(dev, state, false, enable);
 }
 
+/* PCI Virtual Channel */
+int pci_save_vc_state(struct pci_dev *dev);
+void pci_restore_vc_state(struct pci_dev *dev);
+void pci_allocate_vc_save_buffers(struct pci_dev *dev);
+
 #define PCI_EXP_IDO_REQUEST     (1<<0)
 #define PCI_EXP_IDO_COMPLETION  (1<<1)
 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
@@ -1162,15 +1174,14 @@ struct msix_entry {
 
 
 #ifndef CONFIG_PCI_MSI
-static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
+static inline int pci_msi_vec_count(struct pci_dev *dev)
 {
-        return -1;
+        return -ENOSYS;
 }
 
-static inline int
-pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
+static inline int pci_enable_msi_block(struct pci_dev *dev, int nvec)
 {
-        return -1;
+        return -ENOSYS;
 }
 
 static inline void pci_msi_shutdown(struct pci_dev *dev)
@@ -1178,14 +1189,14 @@ static inline void pci_msi_shutdown(struct pci_dev *dev)
 static inline void pci_disable_msi(struct pci_dev *dev)
 { }
 
-static inline int pci_msix_table_size(struct pci_dev *dev)
+static inline int pci_msix_vec_count(struct pci_dev *dev)
 {
-        return 0;
+        return -ENOSYS;
 }
 static inline int pci_enable_msix(struct pci_dev *dev,
                                   struct msix_entry *entries, int nvec)
 {
-        return -1;
+        return -ENOSYS;
 }
 
 static inline void pci_msix_shutdown(struct pci_dev *dev)
@@ -1202,18 +1213,32 @@ static inline int pci_msi_enabled(void)
 {
         return 0;
 }
+
+static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
+                                       int maxvec)
+{
+        return -ENOSYS;
+}
+static inline int pci_enable_msix_range(struct pci_dev *dev,
+                      struct msix_entry *entries, int minvec, int maxvec)
+{
+        return -ENOSYS;
+}
 #else
-int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
-int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
+int pci_msi_vec_count(struct pci_dev *dev);
+int pci_enable_msi_block(struct pci_dev *dev, int nvec);
 void pci_msi_shutdown(struct pci_dev *dev);
 void pci_disable_msi(struct pci_dev *dev);
-int pci_msix_table_size(struct pci_dev *dev);
+int pci_msix_vec_count(struct pci_dev *dev);
 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
 void pci_msix_shutdown(struct pci_dev *dev);
 void pci_disable_msix(struct pci_dev *dev);
 void msi_remove_pci_irq_vectors(struct pci_dev *dev);
 void pci_restore_msi_state(struct pci_dev *dev);
 int pci_msi_enabled(void);
+int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
+int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
+                          int minvec, int maxvec);
 #endif
 
 #ifdef CONFIG_PCIEPORTBUS
@@ -1571,65 +1596,65 @@ enum pci_fixup_pass {
 /* Anonymous variables would be nice... */
 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
                                   class_shift, hook)                    \
-        static const struct pci_fixup __pci_fixup_##name __used         \
+        static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used       \
         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
                 = { vendor, device, class, class_shift, hook };
 
 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
-                vendor##device##hook, vendor, device, class, class_shift, hook)
+                hook, vendor, device, class, class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
-                vendor##device##hook, vendor, device, class, class_shift, hook)
+                hook, vendor, device, class, class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
-                vendor##device##hook, vendor, device, class, class_shift, hook)
+                hook, vendor, device, class, class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
-                vendor##device##hook, vendor, device, class, class_shift, hook)
+                hook, vendor, device, class, class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
-                resume##vendor##device##hook, vendor, device, class,    \
+                resume##hook, vendor, device, class,    \
                 class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
-                resume_early##vendor##device##hook, vendor, device,     \
+                resume_early##hook, vendor, device,     \
                 class, class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
-                suspend##vendor##device##hook, vendor, device, class,   \
+                suspend##hook, vendor, device, class,   \
                 class_shift, hook)
 
 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
-                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
+                hook, vendor, device, PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
-                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
+                hook, vendor, device, PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
-                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
+                hook, vendor, device, PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
-                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
+                hook, vendor, device, PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
-                resume##vendor##device##hook, vendor, device,           \
+                resume##hook, vendor, device,           \
                 PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
-                resume_early##vendor##device##hook, vendor, device,     \
+                resume_early##hook, vendor, device,     \
                 PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
-                suspend##vendor##device##hook, vendor, device,          \
+                suspend##hook, vendor, device,          \
                 PCI_ANY_ID, 0, hook)
 
 #ifdef CONFIG_PCI_QUIRKS
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 4a98e85438a7..ab6b4e7f6657 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -518,8 +518,16 @@
 #define  PCI_EXP_SLTCTL_CCIE    0x0010  /* Command Completed Interrupt Enable */
 #define  PCI_EXP_SLTCTL_HPIE    0x0020  /* Hot-Plug Interrupt Enable */
 #define  PCI_EXP_SLTCTL_AIC     0x00c0  /* Attention Indicator Control */
+#define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 /* Attention Indicator on */
+#define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
+#define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 /* Attention Indicator off */
 #define  PCI_EXP_SLTCTL_PIC     0x0300  /* Power Indicator Control */
+#define  PCI_EXP_SLTCTL_PWR_IND_ON     0x0100 /* Power Indicator on */
+#define  PCI_EXP_SLTCTL_PWR_IND_BLINK  0x0200 /* Power Indicator blinking */
+#define  PCI_EXP_SLTCTL_PWR_IND_OFF    0x0300 /* Power Indicator off */
 #define  PCI_EXP_SLTCTL_PCC     0x0400  /* Power Controller Control */
+#define  PCI_EXP_SLTCTL_PWR_ON         0x0000 /* Power On */
+#define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 /* Power Off */
 #define  PCI_EXP_SLTCTL_EIC     0x0800  /* Electromechanical Interlock Control */
 #define  PCI_EXP_SLTCTL_DLLSCE  0x1000  /* Data Link Layer State Changed Enable */
 #define PCI_EXP_SLTSTA          26      /* Slot Status */
@@ -677,17 +685,34 @@
 #define PCI_ERR_ROOT_ERR_SRC    52      /* Error Source Identification */
 
 /* Virtual Channel */
-#define PCI_VC_PORT_REG1        4
-#define  PCI_VC_REG1_EVCC       0x7     /* extended VC count */
-#define PCI_VC_PORT_REG2        8
-#define  PCI_VC_REG2_32_PHASE   0x2
-#define  PCI_VC_REG2_64_PHASE   0x4
-#define  PCI_VC_REG2_128_PHASE  0x8
+#define PCI_VC_PORT_CAP1        4
+#define  PCI_VC_CAP1_EVCC       0x00000007      /* extended VC count */
+#define  PCI_VC_CAP1_LPEVCC     0x00000070      /* low prio extended VC count */
+#define  PCI_VC_CAP1_ARB_SIZE   0x00000c00
+#define PCI_VC_PORT_CAP2        8
+#define  PCI_VC_CAP2_32_PHASE           0x00000002
+#define  PCI_VC_CAP2_64_PHASE           0x00000004
+#define  PCI_VC_CAP2_128_PHASE          0x00000008
+#define  PCI_VC_CAP2_ARB_OFF            0xff000000
 #define PCI_VC_PORT_CTRL        12
+#define  PCI_VC_PORT_CTRL_LOAD_TABLE    0x00000001
 #define PCI_VC_PORT_STATUS      14
+#define  PCI_VC_PORT_STATUS_TABLE       0x00000001
 #define PCI_VC_RES_CAP          16
+#define  PCI_VC_RES_CAP_32_PHASE        0x00000002
+#define  PCI_VC_RES_CAP_64_PHASE        0x00000004
+#define  PCI_VC_RES_CAP_128_PHASE       0x00000008
+#define  PCI_VC_RES_CAP_128_PHASE_TB    0x00000010
+#define  PCI_VC_RES_CAP_256_PHASE       0x00000020
+#define  PCI_VC_RES_CAP_ARB_OFF         0xff000000
 #define PCI_VC_RES_CTRL         20
+#define  PCI_VC_RES_CTRL_LOAD_TABLE     0x00010000
+#define  PCI_VC_RES_CTRL_ARB_SELECT     0x000e0000
+#define  PCI_VC_RES_CTRL_ID             0x07000000
+#define  PCI_VC_RES_CTRL_ENABLE         0x80000000
 #define PCI_VC_RES_STATUS       26
+#define  PCI_VC_RES_STATUS_TABLE        0x00000001
+#define  PCI_VC_RES_STATUS_NEGO         0x00000002
 #define PCI_CAP_VC_BASE_SIZEOF          0x10
 #define PCI_CAP_VC_PER_VC_SIZEOF        0x0C