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-rw-r--r--include/asm-x86/apic.h22
-rw-r--r--include/asm-x86/apicdef.h3
2 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h
index 6fda195337c5..bb54928373ca 100644
--- a/include/asm-x86/apic.h
+++ b/include/asm-x86/apic.h
@@ -7,6 +7,8 @@
7#include <asm/apicdef.h> 7#include <asm/apicdef.h>
8#include <asm/processor.h> 8#include <asm/processor.h>
9#include <asm/system.h> 9#include <asm/system.h>
10#include <asm/cpufeature.h>
11#include <asm/msr.h>
10 12
11#define ARCH_APICTIMER_STOPS_ON_C3 1 13#define ARCH_APICTIMER_STOPS_ON_C3 1
12 14
@@ -73,6 +75,26 @@ static inline u32 native_apic_mem_read(u32 reg)
73 return *((volatile u32 *)(APIC_BASE + reg)); 75 return *((volatile u32 *)(APIC_BASE + reg));
74} 76}
75 77
78static inline void native_apic_msr_write(u32 reg, u32 v)
79{
80 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
81 reg == APIC_LVR)
82 return;
83
84 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
85}
86
87static inline u32 native_apic_msr_read(u32 reg)
88{
89 u32 low, high;
90
91 if (reg == APIC_DFR)
92 return -1;
93
94 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
95 return low;
96}
97
76#ifdef CONFIG_X86_32 98#ifdef CONFIG_X86_32
77extern void apic_wait_icr_idle(void); 99extern void apic_wait_icr_idle(void);
78extern u32 safe_apic_wait_icr_idle(void); 100extern u32 safe_apic_wait_icr_idle(void);
diff --git a/include/asm-x86/apicdef.h b/include/asm-x86/apicdef.h
index 6b9008c78731..bcae297b30b2 100644
--- a/include/asm-x86/apicdef.h
+++ b/include/asm-x86/apicdef.h
@@ -105,6 +105,7 @@
105#define APIC_TMICT 0x380 105#define APIC_TMICT 0x380
106#define APIC_TMCCT 0x390 106#define APIC_TMCCT 0x390
107#define APIC_TDCR 0x3E0 107#define APIC_TDCR 0x3E0
108#define APIC_SELF_IPI 0x3F0
108#define APIC_TDR_DIV_TMBASE (1 << 2) 109#define APIC_TDR_DIV_TMBASE (1 << 2)
109#define APIC_TDR_DIV_1 0xB 110#define APIC_TDR_DIV_1 0xB
110#define APIC_TDR_DIV_2 0x0 111#define APIC_TDR_DIV_2 0x0
@@ -128,6 +129,8 @@
128#define APIC_EILVT3 0x530 129#define APIC_EILVT3 0x530
129 130
130#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 131#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
132#define APIC_BASE_MSR 0x800
133#define X2APIC_ENABLE (1UL << 10)
131 134
132#ifdef CONFIG_X86_32 135#ifdef CONFIG_X86_32
133# define MAX_IO_APICS 64 136# define MAX_IO_APICS 64