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-rw-r--r--include/asm-arm/arch-at91/at91sam9263.h131
-rw-r--r--include/asm-arm/arch-at91/at91sam9263_matrix.h129
-rw-r--r--include/asm-arm/arch-at91/at91sam926x_mc.h7
-rw-r--r--include/asm-arm/arch-at91/cpu.h7
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h5
6 files changed, 281 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
new file mode 100644
index 000000000000..f4af68ae0ea9
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -0,0 +1,131 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9263.h
3 *
4 * (C) 2007 Atmel Corporation.
5 *
6 * Common definitions.
7 * Based on AT91SAM9263 datasheet revision B (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9263_H
16#define AT91SAM9263_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Peripherals */
23#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
26#define AT91SAM9263_ID_US0 7 /* USART 0 */
27#define AT91SAM9263_ID_US1 8 /* USART 1 */
28#define AT91SAM9263_ID_US2 9 /* USART 2 */
29#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
30#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
31#define AT91SAM9263_ID_CAN 12 /* CAN */
32#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
33#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
34#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
35#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
36#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
37#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
38#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
39#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
40#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
41#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
42#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
43#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
44#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
45#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
46#define AT91SAM9263_ID_UHP 29 /* USB Host port */
47#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
48#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
49
50
51/*
52 * User Peripheral physical base addresses.
53 */
54#define AT91SAM9263_BASE_UDP 0xfff78000
55#define AT91SAM9263_BASE_TCB0 0xfff7c000
56#define AT91SAM9263_BASE_TC0 0xfff7c000
57#define AT91SAM9263_BASE_TC1 0xfff7c040
58#define AT91SAM9263_BASE_TC2 0xfff7c080
59#define AT91SAM9263_BASE_MCI0 0xfff80000
60#define AT91SAM9263_BASE_MCI1 0xfff84000
61#define AT91SAM9263_BASE_TWI 0xfff88000
62#define AT91SAM9263_BASE_US0 0xfff8c000
63#define AT91SAM9263_BASE_US1 0xfff90000
64#define AT91SAM9263_BASE_US2 0xfff94000
65#define AT91SAM9263_BASE_SSC0 0xfff98000
66#define AT91SAM9263_BASE_SSC1 0xfff9c000
67#define AT91SAM9263_BASE_AC97C 0xfffa0000
68#define AT91SAM9263_BASE_SPI0 0xfffa4000
69#define AT91SAM9263_BASE_SPI1 0xfffa8000
70#define AT91SAM9263_BASE_CAN 0xfffac000
71#define AT91SAM9263_BASE_PWMC 0xfffb8000
72#define AT91SAM9263_BASE_EMAC 0xfffbc000
73#define AT91SAM9263_BASE_ISI 0xfffc4000
74#define AT91SAM9263_BASE_2DGE 0xfffc8000
75#define AT91_BASE_SYS 0xffffe000
76
77/*
78 * System Peripherals (offset from AT91_BASE_SYS)
79 */
80#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
81#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
82#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
83#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
84#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
85#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
86#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
87#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
88#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
89#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
90#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
91#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
92#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
93#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
94#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
95#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
96#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
97#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
98#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
99#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
100#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
101#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
102#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
103
104#define AT91_SMC AT91_SMC0
105
106/*
107 * Internal Memory.
108 */
109#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
110#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
111
112#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
113#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
114
115#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
116#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
117
118#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
119#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
120#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
121
122#if 0
123/*
124 * PIO pin definitions (peripheral A/B multiplexing).
125 */
126
127// TODO: Add
128
129#endif
130
131#endif
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h
new file mode 100644
index 000000000000..6fc6e4be624e
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h
@@ -0,0 +1,129 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9263_matrix.h
3 *
4 * Copyright (C) 2006 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9263 datasheet revision B (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9263_MATRIX_H
16#define AT91SAM9263_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
28#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
29#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
30#define AT91_MATRIX_ULBT_FOUR (2 << 0)
31#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
33
34#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
35#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
36#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
37#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
38#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
39#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
40#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
41#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
47#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
51
52#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
53#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
54#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
55#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
56#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
57#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
58#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
59#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
61#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
62#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
63#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
64#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
65#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
66#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
67#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
71#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
72#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
73#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
74#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
77
78#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
81#define AT91_MATRIX_RCB2 (1 << 2)
82#define AT91_MATRIX_RCB3 (1 << 3)
83#define AT91_MATRIX_RCB4 (1 << 4)
84#define AT91_MATRIX_RCB5 (1 << 5)
85#define AT91_MATRIX_RCB6 (1 << 6)
86#define AT91_MATRIX_RCB7 (1 << 7)
87#define AT91_MATRIX_RCB8 (1 << 8)
88
89#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
91#define AT91_MATRIX_ITCM_0 (0 << 0)
92#define AT91_MATRIX_ITCM_16 (5 << 0)
93#define AT91_MATRIX_ITCM_32 (6 << 0)
94#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
95#define AT91_MATRIX_DTCM_0 (0 << 4)
96#define AT91_MATRIX_DTCM_16 (5 << 4)
97#define AT91_MATRIX_DTCM_32 (6 << 4)
98
99#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
103#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
104#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
105#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
106#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
107#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
108#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
109#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
110#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
111#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
112#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
113#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
116
117#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
121#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
122#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
123#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
124#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
125#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
126#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
127#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
128
129#endif
diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam926x_mc.h
index 355eee67ebca..d82631c251f1 100644
--- a/include/asm-arm/arch-at91/at91sam926x_mc.h
+++ b/include/asm-arm/arch-at91/at91sam926x_mc.h
@@ -131,4 +131,11 @@
131#define AT91_SMC_PS_16 (2 << 28) 131#define AT91_SMC_PS_16 (2 << 28)
132#define AT91_SMC_PS_32 (3 << 28) 132#define AT91_SMC_PS_32 (3 << 28)
133 133
134#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
135#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
136#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
137#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
138#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
139#endif
140
134#endif 141#endif
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 762eb41aa675..9efde0dad249 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -20,6 +20,7 @@
20#define ARCH_ID_AT91RM9200 0x09290780 20#define ARCH_ID_AT91RM9200 0x09290780
21#define ARCH_ID_AT91SAM9260 0x019803a0 21#define ARCH_ID_AT91SAM9260 0x019803a0
22#define ARCH_ID_AT91SAM9261 0x019703a0 22#define ARCH_ID_AT91SAM9261 0x019703a0
23#define ARCH_ID_AT91SAM9263 0x019607a0
23 24
24 25
25static inline unsigned long at91_cpu_identify(void) 26static inline unsigned long at91_cpu_identify(void)
@@ -46,4 +47,10 @@ static inline unsigned long at91_cpu_identify(void)
46#define cpu_is_at91sam9261() (0) 47#define cpu_is_at91sam9261() (0)
47#endif 48#endif
48 49
50#ifdef CONFIG_ARCH_AT91SAM9263
51#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
52#else
53#define cpu_is_at91sam9263() (0)
54#endif
55
49#endif 56#endif
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 1637fc4a0d8f..eaaf1c12b753 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -22,6 +22,8 @@
22#include <asm/arch/at91sam9260.h> 22#include <asm/arch/at91sam9260.h>
23#elif defined(CONFIG_ARCH_AT91SAM9261) 23#elif defined(CONFIG_ARCH_AT91SAM9261)
24#include <asm/arch/at91sam9261.h> 24#include <asm/arch/at91sam9261.h>
25#elif defined(CONFIG_ARCH_AT91SAM9263)
26#include <asm/arch/at91sam9263.h>
25#else 27#else
26#error "Unsupported AT91 processor" 28#error "Unsupported AT91 processor"
27#endif 29#endif
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index b24e364997e1..f41636d607a2 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -32,6 +32,11 @@
32#define AT91SAM9_MASTER_CLOCK 99300000 32#define AT91SAM9_MASTER_CLOCK 99300000
33#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 33#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
34 34
35#elif defined(CONFIG_ARCH_AT91SAM9263)
36
37#define AT91SAM9_MASTER_CLOCK 99959500
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39
35#endif 40#endif
36 41
37#endif 42#endif
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