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-rw-r--r--include/asm-x86/msr-index.h36
1 files changed, 25 insertions, 11 deletions
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index a02eb2991349..a4944732be04 100644
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -73,8 +73,32 @@
73#define MSR_P6_EVNTSEL0 0x00000186 73#define MSR_P6_EVNTSEL0 0x00000186
74#define MSR_P6_EVNTSEL1 0x00000187 74#define MSR_P6_EVNTSEL1 0x00000187
75 75
76/* K7/K8 MSRs. Not complete. See the architecture manual for a more 76/* AMD64 MSRs. Not complete. See the architecture manual for a more
77 complete list. */ 77 complete list. */
78
79#define MSR_AMD64_IBSFETCHCTL 0xc0011030
80#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
81#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
82#define MSR_AMD64_IBSOPCTL 0xc0011033
83#define MSR_AMD64_IBSOPRIP 0xc0011034
84#define MSR_AMD64_IBSOPDATA 0xc0011035
85#define MSR_AMD64_IBSOPDATA2 0xc0011036
86#define MSR_AMD64_IBSOPDATA3 0xc0011037
87#define MSR_AMD64_IBSDCLINAD 0xc0011038
88#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
89#define MSR_AMD64_IBSCTL 0xc001103a
90
91/* K8 MSRs */
92#define MSR_K8_TOP_MEM1 0xc001001a
93#define MSR_K8_TOP_MEM2 0xc001001d
94#define MSR_K8_SYSCFG 0xc0010010
95#define MSR_K8_HWCR 0xc0010015
96#define MSR_K8_ENABLE_C1E 0xc0010055
97#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
98#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
99#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
100
101/* K7 MSRs */
78#define MSR_K7_EVNTSEL0 0xc0010000 102#define MSR_K7_EVNTSEL0 0xc0010000
79#define MSR_K7_PERFCTR0 0xc0010004 103#define MSR_K7_PERFCTR0 0xc0010004
80#define MSR_K7_EVNTSEL1 0xc0010001 104#define MSR_K7_EVNTSEL1 0xc0010001
@@ -83,20 +107,10 @@
83#define MSR_K7_PERFCTR2 0xc0010006 107#define MSR_K7_PERFCTR2 0xc0010006
84#define MSR_K7_EVNTSEL3 0xc0010003 108#define MSR_K7_EVNTSEL3 0xc0010003
85#define MSR_K7_PERFCTR3 0xc0010007 109#define MSR_K7_PERFCTR3 0xc0010007
86#define MSR_K8_TOP_MEM1 0xc001001a
87#define MSR_K7_CLK_CTL 0xc001001b 110#define MSR_K7_CLK_CTL 0xc001001b
88#define MSR_K8_TOP_MEM2 0xc001001d
89#define MSR_K8_SYSCFG 0xc0010010
90
91#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
92#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
93#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
94
95#define MSR_K7_HWCR 0xc0010015 111#define MSR_K7_HWCR 0xc0010015
96#define MSR_K8_HWCR 0xc0010015
97#define MSR_K7_FID_VID_CTL 0xc0010041 112#define MSR_K7_FID_VID_CTL 0xc0010041
98#define MSR_K7_FID_VID_STATUS 0xc0010042 113#define MSR_K7_FID_VID_STATUS 0xc0010042
99#define MSR_K8_ENABLE_C1E 0xc0010055
100 114
101/* K6 MSRs */ 115/* K6 MSRs */
102#define MSR_K6_EFER 0xc0000080 116#define MSR_K6_EFER 0xc0000080