72 files changed, 1081 insertions, 2000 deletions
diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h
index 805ae3575e44..345a649ec838 100644
--- a/include/asm-arm/arch-omap/irda.h
+++ b/include/asm-arm/arch-omap/irda.h
@@ -24,7 +24,7 @@ struct omap_irda_config {
        /* Very specific to the needs of some platforms (h3,h4)
         * having calls which can sleep in irda_set_speed.
         */
-        struct work_struct gpio_expa;
+        struct delayed_work gpio_expa;
        int rx_channel;
        int tx_channel;
        unsigned long dest_start;
diff --git a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h
index 51a166242522..a6c024e2506f 100644
--- a/include/asm-i386/atomic.h
+++ b/include/asm-i386/atomic.h
@@ -14,7 +14,7 @@
 * on us. We need to use _exactly_ the address the user gave us,
 * not some alias that contains the same information.
 */
-typedef struct { volatile int counter; } atomic_t;
+typedef struct { int counter; } atomic_t;
 #define ATOMIC_INIT(i)  { (i) }
diff --git a/include/asm-i386/spinlock_types.h b/include/asm-i386/spinlock_types.h
index 59efe849f351..4da9345c1500 100644
--- a/include/asm-i386/spinlock_types.h
+++ b/include/asm-i386/spinlock_types.h
@@ -6,13 +6,13 @@
 #endif
 typedef struct {
-        volatile unsigned int slock;
+        unsigned int slock;
 } raw_spinlock_t;
 #define __RAW_SPIN_LOCK_UNLOCKED        { 1 }
 typedef struct {
-        volatile unsigned int lock;
+        unsigned int lock;
 } raw_rwlock_t;
 #define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
diff --git a/include/asm-m68knommu/irq.h b/include/asm-m68knommu/irq.h
index 45e7a2fd1689..7b8f874f8429 100644
--- a/include/asm-m68knommu/irq.h
+++ b/include/asm-m68knommu/irq.h
@@ -86,5 +86,6 @@ extern void (*mach_disable_irq)(unsigned int);
 #define enable_irq(x)   do { } while (0)
 #define disable_irq(x)  do { } while (0)
 #define disable_irq_nosync(x)   disable_irq(x)
+#define irq_canonicalize(irq)   (irq)
 #endif /* _M68K_IRQ_H_ */
diff --git a/include/asm-m68knommu/rtc.h b/include/asm-m68knommu/rtc.h
new file mode 100644
index 000000000000..eaf18ec83c8e
--- /dev/null
+++ b/include/asm-m68knommu/rtc.h
@@ -0,0 +1 @@
+#include <asm-m68k/rtc.h>
diff --git a/include/asm-m68knommu/ucontext.h b/include/asm-m68knommu/ucontext.h
index 5d570cedbb02..713a27f901cd 100644
--- a/include/asm-m68knommu/ucontext.h
+++ b/include/asm-m68knommu/ucontext.h
@@ -5,21 +5,17 @@ typedef int greg_t;
 #define NGREG 18
 typedef greg_t gregset_t[NGREG];
-#ifdef CONFIG_FPU
 typedef struct fpregset {
        int f_pcr;
        int f_psr;
        int f_fpiaddr;
        int f_fpregs[8][3];
 } fpregset_t;
-#endif
 struct mcontext {
        int version;
        gregset_t gregs;
-#ifdef CONFIG_FPU
        fpregset_t fpregs;
-#endif
 };
 #define MCONTEXT_VERSION 2
@@ -29,9 +25,7 @@ struct ucontext {
        struct ucontext  *uc_link;
        stack_t           uc_stack;
        struct mcontext   uc_mcontext;
-#ifdef CONFIG_FPU
        unsigned long     uc_filler[80];
-#endif
        sigset_t          uc_sigmask;   /* mask last for extensibility */
 };
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h
index 0214abe3f0af..4df8d8b118c0 100644
--- a/include/asm-mips/i8259.h
+++ b/include/asm-mips/i8259.h
@@ -19,10 +19,31 @@
 #include <asm/io.h>
+/* i8259A PIC registers */
+#define PIC_MASTER_CMD          0x20
+#define PIC_MASTER_IMR          0x21
+#define PIC_MASTER_ISR          PIC_MASTER_CMD
+#define PIC_MASTER_POLL         PIC_MASTER_ISR
+#define PIC_MASTER_OCW3         PIC_MASTER_ISR
+#define PIC_SLAVE_CMD           0xa0
+#define PIC_SLAVE_IMR           0xa1
+/* i8259A PIC related value */
+#define PIC_CASCADE_IR          2
+#define MASTER_ICW4_DEFAULT     0x01
+#define SLAVE_ICW4_DEFAULT      0x01
+#define PIC_ICW4_AEOI           2
 extern spinlock_t i8259A_lock;
+extern void init_8259A(int auto_eoi);
+extern void enable_8259A_irq(unsigned int irq);
+extern void disable_8259A_irq(unsigned int irq);
 extern void init_i8259_irqs(void);
+#define I8259A_IRQ_BASE 0
 /*
 * Do the traditional i8259 interrupt polling thing.  This is for the few
 * cases where no better interrupt acknowledge method is available and we
@@ -35,15 +56,15 @@ static inline int i8259_irq(void)
        spin_lock(&i8259A_lock);
        /* Perform an interrupt acknowledge cycle on controller 1. */
-        outb(0x0C, 0x20);               /* prepare for poll */
+        outb(0x0C, PIC_MASTER_CMD);             /* prepare for poll */
-        irq = inb(0x20) & 7;
+        irq = inb(PIC_MASTER_CMD) & 7;
-        if (irq == 2) {
+        if (irq == PIC_CASCADE_IR) {
                /*
                 * Interrupt is cascaded so perform interrupt
                 * acknowledge on controller 2.
                 */
-                outb(0x0C, 0xA0);               /* prepare for poll */
+                outb(0x0C, PIC_SLAVE_CMD);              /* prepare for poll */
-                irq = (inb(0xA0) & 7) + 8;
+                irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
        }
        if (unlikely(irq == 7)) {
@@ -54,14 +75,14 @@ static inline int i8259_irq(void)
                 * significant bit is not set then there is no valid
                 * interrupt.
                 */
-                outb(0x0B, 0x20);               /* ISR register */
+                outb(0x0B, PIC_MASTER_ISR);             /* ISR register */
-                if(~inb(0x20) & 0x80)
+                if(~inb(PIC_MASTER_ISR) & 0x80)
                        irq = -1;
        }
        spin_unlock(&i8259A_lock);
-        return irq;
+        return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
 }
 #endif /* _ASM_I8259_H */
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index d20f2e9b28be..2fbd47eba32d 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -156,9 +156,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define __pte_offset(address)                                           \
        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 #define pte_offset(dir, address)                                        \
-        ((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-#define pte_offset_kernel(dir, address) \
+#define pte_offset_kernel(dir, address)                                 \
-        ((pte_t *) pmd_page_vaddr(*(dir)) +  __pte_offset(address))
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 #define pte_offset_map(dir, address)                                    \
        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index b9b1e86493ee..a5b18710b6a4 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -212,9 +212,9 @@ static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
 #define __pte_offset(address)                                           \
        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 #define pte_offset(dir, address)                                        \
-        ((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 #define pte_offset_kernel(dir, address)                                 \
-        ((pte_t *) pmd_page_vaddr(*(dir)) +  __pte_offset(address))
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 #define pte_offset_map(dir, address)                                    \
        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
 #define pte_offset_map_nested(dir, address)                             \
diff --git a/include/asm-sh/atomic.h b/include/asm-sh/atomic.h
index 8bdc1ba56f73..28305c3cbddf 100644
--- a/include/asm-sh/atomic.h
+++ b/include/asm-sh/atomic.h
@@ -28,11 +28,11 @@ static inline void atomic_add(int i, atomic_t *v)
        unsigned long tmp;
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_add    \n"
+"1:     movli.l @%2, %0         ! atomic_add    \n"
-"       add     %2, %0                          \n"
+"       add     %1, %0                          \n"
-"       movco.l %0, @%3                         \n"
+"       movco.l %0, @%2                         \n"
 "       bf      1b                              \n"
-        : "=&z" (tmp), "=r" (&v->counter)
+        : "=&z" (tmp)
        : "r" (i), "r" (&v->counter)
        : "t");
 #else
@@ -50,11 +50,11 @@ static inline void atomic_sub(int i, atomic_t *v)
        unsigned long tmp;
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_sub    \n"
+"1:     movli.l @%2, %0         ! atomic_sub    \n"
-"       sub     %2, %0                          \n"
+"       sub     %1, %0                          \n"
-"       movco.l %0, @%3                         \n"
+"       movco.l %0, @%2                         \n"
 "       bf      1b                              \n"
-        : "=&z" (tmp), "=r" (&v->counter)
+        : "=&z" (tmp)
        : "r" (i), "r" (&v->counter)
        : "t");
 #else
@@ -80,12 +80,12 @@ static inline int atomic_add_return(int i, atomic_t *v)
 #ifdef CONFIG_CPU_SH4A
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_add_return     \n"
+"1:     movli.l @%2, %0         ! atomic_add_return     \n"
-"       add     %2, %0                                  \n"
+"       add     %1, %0                                  \n"
-"       movco.l %0, @%3                                 \n"
+"       movco.l %0, @%2                                 \n"
 "       bf      1b                                      \n"
 "       synco                                           \n"
-        : "=&z" (temp), "=r" (&v->counter)
+        : "=&z" (temp)
        : "r" (i), "r" (&v->counter)
        : "t");
 #else
@@ -109,12 +109,12 @@ static inline int atomic_sub_return(int i, atomic_t *v)
 #ifdef CONFIG_CPU_SH4A
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_sub_return     \n"
+"1:     movli.l @%2, %0         ! atomic_sub_return     \n"
-"       sub     %2, %0                                  \n"
+"       sub     %1, %0                                  \n"
-"       movco.l %0, @%3                                 \n"
+"       movco.l %0, @%2                                 \n"
 "       bf      1b                                      \n"
 "       synco                                           \n"
-        : "=&z" (temp), "=r" (&v->counter)
+        : "=&z" (temp)
        : "r" (i), "r" (&v->counter)
        : "t");
 #else
@@ -186,11 +186,11 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
        unsigned long tmp;
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_clear_mask     \n"
+"1:     movli.l @%2, %0         ! atomic_clear_mask     \n"
-"       and     %2, %0                                  \n"
+"       and     %1, %0                                  \n"
-"       movco.l %0, @%3                                 \n"
+"       movco.l %0, @%2                                 \n"
 "       bf      1b                                      \n"
-        : "=&z" (tmp), "=r" (&v->counter)
+        : "=&z" (tmp)
        : "r" (~mask), "r" (&v->counter)
        : "t");
 #else
@@ -208,11 +208,11 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
        unsigned long tmp;
        __asm__ __volatile__ (
-"1:     movli.l @%3, %0         ! atomic_set_mask       \n"
+"1:     movli.l @%2, %0         ! atomic_set_mask       \n"
-"       or      %2, %0                                  \n"
+"       or      %1, %0                                  \n"
-"       movco.l %0, @%3                                 \n"
+"       movco.l %0, @%2                                 \n"
 "       bf      1b                                      \n"
-        : "=&z" (tmp), "=r" (&v->counter)
+        : "=&z" (tmp)
        : "r" (mask), "r" (&v->counter)
        : "t");
 #else
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index beeea40f549e..795047da5e17 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -23,16 +23,20 @@ static void __init check_bugs(void)
        cpu_data->loops_per_jiffy = loops_per_jiffy;
        switch (cpu_data->type) {
-        case CPU_SH7604:
+        case CPU_SH7604 ... CPU_SH7619:
                *p++ = '2';
                break;
+        case CPU_SH7206:
+                *p++ = '2';
+                *p++ = 'a';
+                break;
        case CPU_SH7705 ... CPU_SH7300:
                *p++ = '3';
                break;
        case CPU_SH7750 ... CPU_SH4_501:
                *p++ = '4';
                break;
-        case CPU_SH7770 ... CPU_SH7781:
+        case CPU_SH7770 ... CPU_SH7785:
                *p++ = '4';
                *p++ = 'a';
                break;
diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h
index fdfb75b30f0d..1df92807f8c5 100644
--- a/include/asm-sh/clock.h
+++ b/include/asm-sh/clock.h
@@ -4,6 +4,7 @@
 #include <linux/kref.h>
 #include <linux/list.h>
 #include <linux/seq_file.h>
+#include <linux/clk.h>
 struct clk;
@@ -18,7 +19,7 @@ struct clk_ops {
 struct clk {
        struct list_head        node;
        const char              *name;
+        int                     id;
        struct module           *owner;
        struct clk              *parent;
@@ -40,22 +41,13 @@ void arch_init_clk_ops(struct clk_ops **, int type);
 int clk_init(void);
 int __clk_enable(struct clk *);
-int clk_enable(struct clk *);
 void __clk_disable(struct clk *);
-void clk_disable(struct clk *);
-int clk_set_rate(struct clk *, unsigned long rate);
-unsigned long clk_get_rate(struct clk *);
 void clk_recalc_rate(struct clk *);
-struct clk *clk_get(const char *id);
-void clk_put(struct clk *);
 int clk_register(struct clk *);
 void clk_unregister(struct clk *);
 int show_clocks(struct seq_file *m);
 #endif /* __ASM_SH_CLOCK_H */
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index cd96402e8562..20b9796842dc 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,6 +12,7 @@
 #define L1_CACHE_SHIFT  4
+#if defined(CONFIG_CPU_SUBTYPE_SH7604)
 #define CCR             0xfffffe92      /* Address of Cache Control Register */
 #define CCR_CACHE_CE    0x01    /* Cache enable */
@@ -27,5 +28,26 @@
 #define CCR_CACHE_ORA           CCR_CACHE_TW
 #define CCR_CACHE_WT            0x00    /* SH-2 is _always_ write-through */
+#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define CCR1            0xffffffec
+#define CCR             CCR1
+#define CCR_CACHE_CE    0x01    /* Cache enable */
+#define CCR_CACHE_WT    0x06    /* CCR[bit1=1,bit2=1] */
+                                /* 0x00000000-0x7fffffff: Write-through  */
+                                /* 0x80000000-0x9fffffff: Write-back     */
+                                /* 0xc0000000-0xdfffffff: Write-through  */
+#define CCR_CACHE_CB    0x00    /* CCR[bit1=0,bit2=0] */
+                                /* 0x00000000-0x7fffffff: Write-back     */
+                                /* 0x80000000-0x9fffffff: Write-through  */
+                                /* 0xc0000000-0xdfffffff: Write-back     */
+#define CCR_CACHE_CF    0x08    /* Cache invalidate */
+#define CACHE_OC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_DATA_ARRAY     0xf1000000
+#define CCR_CACHE_ENABLE        CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE    CCR_CACHE_CF
+#endif
 #endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/include/asm-sh/cpu-sh2/freq.h b/include/asm-sh/cpu-sh2/freq.h
new file mode 100644
index 000000000000..31de475da70b
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_FREQ_H
+#define __ASM_CPU_SH2_FREQ_H
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define FREQCR  0xf815ff80
+#endif
+#endif /* __ASM_CPU_SH2_FREQ_H */
diff --git a/include/asm-sh/cpu-sh2/mmu_context.h b/include/asm-sh/cpu-sh2/mmu_context.h
new file mode 100644
index 000000000000..beeb299e01ec
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/mmu_context.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-sh/cpu-sh2/mmu_context.h
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
+#define __ASM_CPU_SH2_MMU_CONTEXT_H
+/* No MMU */
+#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
diff --git a/include/asm-sh/cpu-sh2/timer.h b/include/asm-sh/cpu-sh2/timer.h
new file mode 100644
index 000000000000..a39c241e8195
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/timer.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_CPU_SH2_TIMER_H
+#define __ASM_CPU_SH2_TIMER_H
+/* Nothing needed yet */
+#endif /* __ASM_CPU_SH2_TIMER_H */
diff --git a/include/asm-sh/cpu-sh2a/addrspace.h b/include/asm-sh/cpu-sh2a/addrspace.h
new file mode 100644
index 000000000000..3d2e9aa21522
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/addrspace.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/addrspace.h>
diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
new file mode 100644
index 000000000000..3e4b9e480982
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cache.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-sh/cpu-sh2a/cache.h
+ *
+ * Copyright (C) 2004 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_CACHE_H
+#define __ASM_CPU_SH2A_CACHE_H
+#define L1_CACHE_SHIFT  4
+#define CCR1            0xfffc1000
+#define CCR2            0xfffc1004
+/* CCR1 behaves more like the traditional CCR */
+#define CCR             CCR1
+/*
+ * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
+ * listed here are reserved.
+ */
+#define CCR_CACHE_CB    0x0000  /* Hack */
+#define CCR_CACHE_OCE   0x0001
+#define CCR_CACHE_WT    0x0002
+#define CCR_CACHE_OCI   0x0008  /* OCF */
+#define CCR_CACHE_ICE   0x0100
+#define CCR_CACHE_ICI   0x0800  /* ICF */
+#define CACHE_IC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY  0xf0800000
+#define CCR_CACHE_ENABLE        (CCR_CACHE_OCE | CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI | CCR_CACHE_ICI)
+#endif /* __ASM_CPU_SH2A_CACHE_H */
diff --git a/include/asm-sh/cpu-sh2a/cacheflush.h b/include/asm-sh/cpu-sh2a/cacheflush.h
new file mode 100644
index 000000000000..fa3186c73350
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cacheflush.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/cacheflush.h>
diff --git a/include/asm-sh/cpu-sh2a/dma.h b/include/asm-sh/cpu-sh2a/dma.h
new file mode 100644
index 000000000000..0d5ad85c1de8
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/dma.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/dma.h>
diff --git a/include/asm-sh/cpu-sh2a/freq.h b/include/asm-sh/cpu-sh2a/freq.h
new file mode 100644
index 000000000000..e518fff6d10f
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2a/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_FREQ_H
+#define __ASM_CPU_SH2A_FREQ_H
+#if defined(CONFIG_CPU_SUBTYPE_SH7206)
+#define FREQCR  0xfffe0010
+#endif
+#endif /* __ASM_CPU_SH2A_FREQ_H */
diff --git a/include/asm-sh/cpu-sh2a/mmu_context.h b/include/asm-sh/cpu-sh2a/mmu_context.h
new file mode 100644
index 000000000000..cd2387f7db9e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/mmu_context.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/mmu_context.h>
diff --git a/include/asm-sh/cpu-sh2a/timer.h b/include/asm-sh/cpu-sh2a/timer.h
new file mode 100644
index 000000000000..fee504adf11e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/timer.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/timer.h>
diff --git a/include/asm-sh/cpu-sh2a/ubc.h b/include/asm-sh/cpu-sh2a/ubc.h
new file mode 100644
index 000000000000..cf28062b96a2
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/ubc.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/ubc.h>
diff --git a/include/asm-sh/cpu-sh2a/watchdog.h b/include/asm-sh/cpu-sh2a/watchdog.h
new file mode 100644
index 000000000000..c1b3e2488478
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/watchdog.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/watchdog.h>
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index d9daa028689f..faf3051cd429 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -14,9 +14,7 @@
 #include <linux/spinlock.h>
 #include <linux/wait.h>
 #include <linux/sysdev.h>
-#include <linux/device.h>
 #include <asm/cpu/dma.h>
-#include <asm/semaphore.h>
 /* The maximum address that we can perform a DMA transfer to on this platform */
 /* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
@@ -46,16 +44,21 @@
 * DMAC (dma_info) flags
 */
 enum {
-        DMAC_CHANNELS_CONFIGURED        = 0x00,
+        DMAC_CHANNELS_CONFIGURED        = 0x01,
-        DMAC_CHANNELS_TEI_CAPABLE       = 0x01,
+        DMAC_CHANNELS_TEI_CAPABLE       = 0x02, /* Transfer end interrupt */
 };
 /*
 * DMA channel capabilities / flags
 */
 enum {
-        DMA_TEI_CAPABLE                 = 0x01,
+        DMA_CONFIGURED                  = 0x01,
-        DMA_CONFIGURED                  = 0x02,
+        /*
+         * Transfer end interrupt, inherited from DMAC.
+         * wait_queue used in dma_wait_for_completion.
+         */
+        DMA_TEI_CAPABLE                 = 0x02,
 };
 extern spinlock_t dma_spin_lock;
@@ -68,28 +71,31 @@ struct dma_ops {
        int (*get_residue)(struct dma_channel *chan);
        int (*xfer)(struct dma_channel *chan);
-        void (*configure)(struct dma_channel *chan, unsigned long flags);
+        int (*configure)(struct dma_channel *chan, unsigned long flags);
+        int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
 };
 struct dma_channel {
-        char dev_id[16];
+        char dev_id[16];                /* unique name per DMAC of channel */
-        unsigned int chan;              /* Physical channel number */
+        unsigned int chan;              /* DMAC channel number */
        unsigned int vchan;             /* Virtual channel number */
        unsigned int mode;
        unsigned int count;
        unsigned long sar;
        unsigned long dar;
+        const char **caps;
        unsigned long flags;
        atomic_t busy;
-        struct semaphore sem;
        wait_queue_head_t wait_queue;
        struct sys_device dev;
-        char *name;
+        void *priv_data;
 };
 struct dma_info {
@@ -103,6 +109,12 @@ struct dma_info {
        struct dma_channel *channels;
        struct list_head list;
+        int first_channel_nr;
+};
+struct dma_chan_caps {
+        int ch_num;
+        const char **caplist;
 };
 #define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
@@ -121,6 +133,8 @@ extern int dma_xfer(unsigned int chan, unsigned long from,
 #define dma_read_page(chan, from, to)   \
        dma_read(chan, from, to, PAGE_SIZE)
+extern int request_dma_bycap(const char **dmac, const char **caps,
+                             const char *dev_id);
 extern int request_dma(unsigned int chan, const char *dev_id);
 extern void free_dma(unsigned int chan);
 extern int get_dma_residue(unsigned int chan);
@@ -131,6 +145,10 @@ extern void dma_configure_channel(unsigned int chan, unsigned long flags);
 extern int register_dmac(struct dma_info *info);
 extern void unregister_dmac(struct dma_info *info);
+extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
+extern int dma_extend(unsigned int chan, unsigned long op, void *param);
+extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
 #ifdef CONFIG_SYSFS
 /* arch/sh/drivers/dma/dma-sysfs.c */
diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h
index fc050fd7645e..43ca244564b1 100644
--- a/include/asm-sh/elf.h
+++ b/include/asm-sh/elf.h
@@ -74,7 +74,7 @@ typedef struct user_fpu_struct elf_fpregset_t;
 #define ELF_ARCH        EM_SH
 #define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
   use of this is to invoke "./ld.so someprog" to test out a new version of
diff --git a/include/asm-sh/entry-macros.S b/include/asm-sh/entry-macros.S
new file mode 100644
index 000000000000..500030eae7aa
--- /dev/null
+++ b/include/asm-sh/entry-macros.S
@@ -0,0 +1,33 @@
+! entry.S macro define
+        
+        .macro  cli
+        stc     sr, r0
+        or      #0xf0, r0
+        ldc     r0, sr
+        .endm
+        .macro  sti
+        mov     #0xf0, r11
+        extu.b  r11, r11
+        not     r11, r11
+        stc     sr, r10
+        and     r11, r10
+#ifdef CONFIG_HAS_SR_RB
+        stc     k_g_imask, r11
+        or      r11, r10
+#endif
+        ldc     r10, sr
+        .endm
+        .macro  get_current_thread_info, ti, tmp
+#ifdef CONFIG_HAS_SR_RB
+        stc     r7_bank, \ti
+#else
+        mov     #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
+        shll8   \tmp
+        shll2   \tmp
+        mov     r15, \ti
+        and     \tmp, \ti
+#endif  
+        .endm
diff --git a/include/asm-sh/irq-sh73180.h b/include/asm-sh/irq-sh73180.h
deleted file mode 100644
index b28af9a69d72..000000000000
--- a/include/asm-sh/irq-sh73180.h
+++ /dev/null
@@ -1,314 +0,0 @@
-#ifndef __ASM_SH_IRQ_SH73180_H
-#define __ASM_SH_IRQ_SH73180_H
-/*
- * linux/include/asm-sh/irq-sh73180.h
- *
- * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
- */
-#undef INTC_IPRA
-#undef INTC_IPRB
-#undef INTC_IPRC
-#undef INTC_IPRD
-#undef DMTE0_IRQ
-#undef DMTE1_IRQ
-#undef DMTE2_IRQ
-#undef DMTE3_IRQ
-#undef DMTE4_IRQ
-#undef DMTE5_IRQ
-#undef DMTE6_IRQ
-#undef DMTE7_IRQ
-#undef DMAE_IRQ
-#undef DMA_IPR_ADDR
-#undef DMA_IPR_POS
-#undef DMA_PRIORITY
-#undef INTC_IMCR0
-#undef INTC_IMCR1
-#undef INTC_IMCR2
-#undef INTC_IMCR3
-#undef INTC_IMCR4
-#undef INTC_IMCR5
-#undef INTC_IMCR6
-#undef INTC_IMCR7
-#undef INTC_IMCR8
-#undef INTC_IMCR9
-#undef INTC_IMCR10
-#define INTC_IPRA       0xA4080000UL
-#define INTC_IPRB       0xA4080004UL
-#define INTC_IPRC       0xA4080008UL
-#define INTC_IPRD       0xA408000CUL
-#define INTC_IPRE       0xA4080010UL
-#define INTC_IPRF       0xA4080014UL
-#define INTC_IPRG       0xA4080018UL
-#define INTC_IPRH       0xA408001CUL
-#define INTC_IPRI       0xA4080020UL
-#define INTC_IPRJ       0xA4080024UL
-#define INTC_IPRK       0xA4080028UL
-#define INTC_IMR0       0xA4080080UL
-#define INTC_IMR1       0xA4080084UL
-#define INTC_IMR2       0xA4080088UL
-#define INTC_IMR3       0xA408008CUL
-#define INTC_IMR4       0xA4080090UL
-#define INTC_IMR5       0xA4080094UL
-#define INTC_IMR6       0xA4080098UL
-#define INTC_IMR7       0xA408009CUL
-#define INTC_IMR8       0xA40800A0UL
-#define INTC_IMR9       0xA40800A4UL
-#define INTC_IMR10      0xA40800A8UL
-#define INTC_IMR11      0xA40800ACUL
-#define INTC_IMCR0      0xA40800C0UL
-#define INTC_IMCR1      0xA40800C4UL
-#define INTC_IMCR2      0xA40800C8UL
-#define INTC_IMCR3      0xA40800CCUL
-#define INTC_IMCR4      0xA40800D0UL
-#define INTC_IMCR5      0xA40800D4UL
-#define INTC_IMCR6      0xA40800D8UL
-#define INTC_IMCR7      0xA40800DCUL
-#define INTC_IMCR8      0xA40800E0UL
-#define INTC_IMCR9      0xA40800E4UL
-#define INTC_IMCR10     0xA40800E8UL
-#define INTC_IMCR11     0xA40800ECUL
-#define INTC_ICR0       0xA4140000UL
-#define INTC_ICR1       0xA414001CUL
-#define INTMSK0         0xa4140044
-#define INTMSKCLR0      0xa4140064
-#define INTC_INTPRI0    0xa4140010
-/*
-  NOTE:
-  *_IRQ = (INTEVT2 - 0x200)/0x20
-*/
-/* TMU0 */
-#define TMU0_IRQ        16
-#define TMU0_IPR_ADDR   INTC_IPRA
-#define TMU0_IPR_POS     3
-#define TMU0_PRIORITY    2
-#define TIMER_IRQ       16
-#define TIMER_IPR_ADDR  INTC_IPRA
-#define TIMER_IPR_POS    3
-#define TIMER_PRIORITY   2
-/* TMU1 */
-#define TMU1_IRQ        17
-#define TMU1_IPR_ADDR   INTC_IPRA
-#define TMU1_IPR_POS     2
-#define TMU1_PRIORITY    2
-/* TMU2 */
-#define TMU2_IRQ        18
-#define TMU2_IPR_ADDR   INTC_IPRA
-#define TMU2_IPR_POS     1
-#define TMU2_PRIORITY    2
-/* LCDC */
-#define LCDC_IRQ        28
-#define LCDC_IPR_ADDR   INTC_IPRB
-#define LCDC_IPR_POS     2
-#define LCDC_PRIORITY    2
-/* VIO (Video I/O) */
-#define CEU_IRQ         52
-#define BEU_IRQ         53
-#define VEU_IRQ         54
-#define VOU_IRQ         55
-#define VIO_IPR_ADDR    INTC_IPRE
-#define VIO_IPR_POS      2
-#define VIO_PRIORITY     2
-/* MFI (Multi Functional Interface) */
-#define MFI_IRQ         56
-#define MFI_IPR_ADDR    INTC_IPRE
-#define MFI_IPR_POS      1
-#define MFI_PRIORITY     2
-/* VPU (Video Processing Unit) */
-#define VPU_IRQ         60
-#define VPU_IPR_ADDR    INTC_IPRE
-#define VPU_IPR_POS      0
-#define VPU_PRIORITY     2
-/* 3DG */
-#define TDG_IRQ         63
-#define TDG_IPR_ADDR    INTC_IPRJ
-#define TDG_IPR_POS      2
-#define TDG_PRIORITY     2
-/* DMAC(1) */
-#define DMTE0_IRQ       48
-#define DMTE1_IRQ       49
-#define DMTE2_IRQ       50
-#define DMTE3_IRQ       51
-#define DMA1_IPR_ADDR   INTC_IPRE
-#define DMA1_IPR_POS    3
-#define DMA1_PRIORITY   7
-/* DMAC(2) */
-#define DMTE4_IRQ       76
-#define DMTE5_IRQ       77
-#define DMA2_IPR_ADDR   INTC_IPRF
-#define DMA2_IPR_POS    2
-#define DMA2_PRIORITY   7
-/* SCIF0 */
-#define SCIF_ERI_IRQ    80
-#define SCIF_RXI_IRQ    81
-#define SCIF_BRI_IRQ    82
-#define SCIF_TXI_IRQ    83
-#define SCIF_IPR_ADDR   INTC_IPRG
-#define SCIF_IPR_POS    3
-#define SCIF_PRIORITY   3
-/* SIOF0 */
-#define SIOF0_IRQ       84
-#define SIOF0_IPR_ADDR  INTC_IPRH
-#define SIOF0_IPR_POS   3
-#define SIOF0_PRIORITY  3
-/* FLCTL (Flash Memory Controller) */
-#define FLSTE_IRQ       92
-#define FLTEND_IRQ      93
-#define FLTRQ0_IRQ      94
-#define FLTRQ1_IRQ      95
-#define FLCTL_IPR_ADDR  INTC_IPRH
-#define FLCTL_IPR_POS   1
-#define FLCTL_PRIORITY  3
-/* IIC(0) (IIC Bus Interface) */
-#define IIC0_ALI_IRQ    96
-#define IIC0_TACKI_IRQ  97
-#define IIC0_WAITI_IRQ  98
-#define IIC0_DTEI_IRQ   99
-#define IIC0_IPR_ADDR   INTC_IPRH
-#define IIC0_IPR_POS    0
-#define IIC0_PRIORITY   3
-/* IIC(1) (IIC Bus Interface) */
-#define IIC1_ALI_IRQ    44
-#define IIC1_TACKI_IRQ  45
-#define IIC1_WAITI_IRQ  46
-#define IIC1_DTEI_IRQ   47
-#define IIC1_IPR_ADDR   INTC_IPRG
-#define IIC1_IPR_POS    0
-#define IIC1_PRIORITY   3
-/* SIO0 */
-#define SIO0_IRQ        88
-#define SIO0_IPR_ADDR   INTC_IPRI
-#define SIO0_IPR_POS    3
-#define SIO0_PRIORITY   3
-/* SDHI */
-#define SDHI_SDHII0_IRQ 100
-#define SDHI_SDHII1_IRQ 101
-#define SDHI_SDHII2_IRQ 102
-#define SDHI_SDHII3_IRQ 103
-#define SDHI_IPR_ADDR   INTC_IPRK
-#define SDHI_IPR_POS    0
-#define SDHI_PRIORITY   3
-/* SIU (Sound Interface Unit) */
-#define SIU_IRQ         108
-#define SIU_IPR_ADDR    INTC_IPRJ
-#define SIU_IPR_POS     1
-#define SIU_PRIORITY    3
-#define PORT_PACR       0xA4050100UL
-#define PORT_PBCR       0xA4050102UL
-#define PORT_PCCR       0xA4050104UL
-#define PORT_PDCR       0xA4050106UL
-#define PORT_PECR       0xA4050108UL
-#define PORT_PFCR       0xA405010AUL
-#define PORT_PGCR       0xA405010CUL
-#define PORT_PHCR       0xA405010EUL
-#define PORT_PJCR       0xA4050110UL
-#define PORT_PKCR       0xA4050112UL
-#define PORT_PLCR       0xA4050114UL
-#define PORT_SCPCR      0xA4050116UL
-#define PORT_PMCR       0xA4050118UL
-#define PORT_PNCR       0xA405011AUL
-#define PORT_PQCR       0xA405011CUL
-#define PORT_PRCR       0xA405011EUL
-#define PORT_PTCR       0xA405014CUL
-#define PORT_PUCR       0xA405014EUL
-#define PORT_PVCR       0xA4050150UL
-#define PORT_PSELA      0xA4050140UL
-#define PORT_PSELB      0xA4050142UL
-#define PORT_PSELC      0xA4050144UL
-#define PORT_PSELE      0xA4050158UL
-#define PORT_HIZCRA     0xA4050146UL
-#define PORT_HIZCRB     0xA4050148UL
-#define PORT_DRVCR      0xA405014AUL
-#define PORT_PADR       0xA4050120UL
-#define PORT_PBDR       0xA4050122UL
-#define PORT_PCDR       0xA4050124UL
-#define PORT_PDDR       0xA4050126UL
-#define PORT_PEDR       0xA4050128UL
-#define PORT_PFDR       0xA405012AUL
-#define PORT_PGDR       0xA405012CUL
-#define PORT_PHDR       0xA405012EUL
-#define PORT_PJDR       0xA4050130UL
-#define PORT_PKDR       0xA4050132UL
-#define PORT_PLDR       0xA4050134UL
-#define PORT_SCPDR      0xA4050136UL
-#define PORT_PMDR       0xA4050138UL
-#define PORT_PNDR       0xA405013AUL
-#define PORT_PQDR       0xA405013CUL
-#define PORT_PRDR       0xA405013EUL
-#define PORT_PTDR       0xA405016CUL
-#define PORT_PUDR       0xA405016EUL
-#define PORT_PVDR       0xA4050170UL
-#define IRQ0_IRQ        32
-#define IRQ1_IRQ        33
-#define IRQ2_IRQ        34
-#define IRQ3_IRQ        35
-#define IRQ4_IRQ        36
-#define IRQ5_IRQ        37
-#define IRQ6_IRQ        38
-#define IRQ7_IRQ        39
-#define INTPRI00        0xA4140010UL
-#define IRQ0_IPR_ADDR   INTPRI00
-#define IRQ1_IPR_ADDR   INTPRI00
-#define IRQ2_IPR_ADDR   INTPRI00
-#define IRQ3_IPR_ADDR   INTPRI00
-#define IRQ4_IPR_ADDR   INTPRI00
-#define IRQ5_IPR_ADDR   INTPRI00
-#define IRQ6_IPR_ADDR   INTPRI00
-#define IRQ7_IPR_ADDR   INTPRI00
-#define IRQ0_IPR_POS    7
-#define IRQ1_IPR_POS    6
-#define IRQ2_IPR_POS    5
-#define IRQ3_IPR_POS    4
-#define IRQ4_IPR_POS    3
-#define IRQ5_IPR_POS    2
-#define IRQ6_IPR_POS    1
-#define IRQ7_IPR_POS    0
-#define IRQ0_PRIORITY   1
-#define IRQ1_PRIORITY   1
-#define IRQ2_PRIORITY   1
-#define IRQ3_PRIORITY   1
-#define IRQ4_PRIORITY   1
-#define IRQ5_PRIORITY   1
-#define IRQ6_PRIORITY   1
-#define IRQ7_PRIORITY   1
-#endif /* __ASM_SH_IRQ_SH73180_H */
diff --git a/include/asm-sh/irq-sh7343.h b/include/asm-sh/irq-sh7343.h
deleted file mode 100644
index 5d15419b53b0..000000000000
--- a/include/asm-sh/irq-sh7343.h
+++ /dev/null
@@ -1,317 +0,0 @@
-#ifndef __ASM_SH_IRQ_SH7343_H
-#define __ASM_SH_IRQ_SH7343_H
-/*
- * linux/include/asm-sh/irq-sh7343.h
- *
- * Copyright (C) 2006 Kenati Technologies Inc.
- * Andre Mccurdy <andre@kenati.com>
- * Ranjit Deshpande <ranjit@kenati.com>
- */
-#undef INTC_IPRA
-#undef INTC_IPRB
-#undef INTC_IPRC
-#undef INTC_IPRD
-#undef DMTE0_IRQ
-#undef DMTE1_IRQ
-#undef DMTE2_IRQ
-#undef DMTE3_IRQ
-#undef DMTE4_IRQ
-#undef DMTE5_IRQ
-#undef DMTE6_IRQ
-#undef DMTE7_IRQ
-#undef DMAE_IRQ
-#undef DMA_IPR_ADDR
-#undef DMA_IPR_POS
-#undef DMA_PRIORITY
-#undef INTC_IMCR0
-#undef INTC_IMCR1
-#undef INTC_IMCR2
-#undef INTC_IMCR3
-#undef INTC_IMCR4
-#undef INTC_IMCR5
-#undef INTC_IMCR6
-#undef INTC_IMCR7
-#undef INTC_IMCR8
-#undef INTC_IMCR9
-#undef INTC_IMCR10
-#define INTC_IPRA       0xA4080000UL
-#define INTC_IPRB       0xA4080004UL
-#define INTC_IPRC       0xA4080008UL
-#define INTC_IPRD       0xA408000CUL
-#define INTC_IPRE       0xA4080010UL
-#define INTC_IPRF       0xA4080014UL
-#define INTC_IPRG       0xA4080018UL
-#define INTC_IPRH       0xA408001CUL
-#define INTC_IPRI       0xA4080020UL
-#define INTC_IPRJ       0xA4080024UL
-#define INTC_IPRK       0xA4080028UL
-#define INTC_IPRL       0xA408002CUL
-#define INTC_IMR0       0xA4080080UL
-#define INTC_IMR1       0xA4080084UL
-#define INTC_IMR2       0xA4080088UL
-#define INTC_IMR3       0xA408008CUL
-#define INTC_IMR4       0xA4080090UL
-#define INTC_IMR5       0xA4080094UL
-#define INTC_IMR6       0xA4080098UL
-#define INTC_IMR7       0xA408009CUL
-#define INTC_IMR8       0xA40800A0UL
-#define INTC_IMR9       0xA40800A4UL
-#define INTC_IMR10      0xA40800A8UL
-#define INTC_IMR11      0xA40800ACUL
-#define INTC_IMCR0      0xA40800C0UL
-#define INTC_IMCR1      0xA40800C4UL
-#define INTC_IMCR2      0xA40800C8UL
-#define INTC_IMCR3      0xA40800CCUL
-#define INTC_IMCR4      0xA40800D0UL
-#define INTC_IMCR5      0xA40800D4UL
-#define INTC_IMCR6      0xA40800D8UL
-#define INTC_IMCR7      0xA40800DCUL
-#define INTC_IMCR8      0xA40800E0UL
-#define INTC_IMCR9      0xA40800E4UL
-#define INTC_IMCR10     0xA40800E8UL
-#define INTC_IMCR11     0xA40800ECUL
-#define INTC_ICR0       0xA4140000UL
-#define INTC_ICR1       0xA414001CUL
-#define INTMSK0         0xa4140044
-#define INTMSKCLR0      0xa4140064
-#define INTC_INTPRI0    0xa4140010
-/*
-  NOTE:
-  *_IRQ = (INTEVT2 - 0x200)/0x20
-*/
-/* TMU0 */
-#define TMU0_IRQ        16
-#define TMU0_IPR_ADDR   INTC_IPRA
-#define TMU0_IPR_POS     3
-#define TMU0_PRIORITY    2
-#define TIMER_IRQ       16
-#define TIMER_IPR_ADDR  INTC_IPRA
-#define TIMER_IPR_POS    3
-#define TIMER_PRIORITY   2
-/* TMU1 */
-#define TMU1_IRQ        17
-#define TMU1_IPR_ADDR   INTC_IPRA
-#define TMU1_IPR_POS     2
-#define TMU1_PRIORITY    2
-/* TMU2 */
-#define TMU2_IRQ        18
-#define TMU2_IPR_ADDR   INTC_IPRA
-#define TMU2_IPR_POS     1
-#define TMU2_PRIORITY    2
-/* LCDC */
-#define LCDC_IRQ        28
-#define LCDC_IPR_ADDR   INTC_IPRB
-#define LCDC_IPR_POS     2
-#define LCDC_PRIORITY    2
-/* VIO (Video I/O) */
-#define CEU_IRQ         52
-#define BEU_IRQ         53
-#define VEU_IRQ         54
-#define VOU_IRQ         55
-#define VIO_IPR_ADDR    INTC_IPRE
-#define VIO_IPR_POS      2
-#define VIO_PRIORITY     2
-/* MFI (Multi Functional Interface) */
-#define MFI_IRQ         56
-#define MFI_IPR_ADDR    INTC_IPRE
-#define MFI_IPR_POS      1
-#define MFI_PRIORITY     2
-/* VPU (Video Processing Unit) */
-#define VPU_IRQ         60
-#define VPU_IPR_ADDR    INTC_IPRE
-#define VPU_IPR_POS      0
-#define VPU_PRIORITY     2
-/* 3DG */
-#define TDG_IRQ         63
-#define TDG_IPR_ADDR    INTC_IPRJ
-#define TDG_IPR_POS      2
-#define TDG_PRIORITY     2
-/* DMAC(1) */
-#define DMTE0_IRQ       48
-#define DMTE1_IRQ       49
-#define DMTE2_IRQ       50
-#define DMTE3_IRQ       51
-#define DMA1_IPR_ADDR   INTC_IPRE
-#define DMA1_IPR_POS    3
-#define DMA1_PRIORITY   7
-/* DMAC(2) */
-#define DMTE4_IRQ       76
-#define DMTE5_IRQ       77
-#define DMA2_IPR_ADDR   INTC_IPRF
-#define DMA2_IPR_POS    2
-#define DMA2_PRIORITY   7
-/* SCIF0 */
-#define SCIF_ERI_IRQ    80
-#define SCIF_RXI_IRQ    81
-#define SCIF_BRI_IRQ    82
-#define SCIF_TXI_IRQ    83
-#define SCIF_IPR_ADDR   INTC_IPRG
-#define SCIF_IPR_POS    3
-#define SCIF_PRIORITY   3
-/* SIOF0 */
-#define SIOF0_IRQ       84
-#define SIOF0_IPR_ADDR  INTC_IPRH
-#define SIOF0_IPR_POS   3
-#define SIOF0_PRIORITY  3
-/* FLCTL (Flash Memory Controller) */
-#define FLSTE_IRQ       92
-#define FLTEND_IRQ      93
-#define FLTRQ0_IRQ      94
-#define FLTRQ1_IRQ      95
-#define FLCTL_IPR_ADDR  INTC_IPRH
-#define FLCTL_IPR_POS   1
-#define FLCTL_PRIORITY  3
-/* IIC(0) (IIC Bus Interface) */
-#define IIC0_ALI_IRQ    96
-#define IIC0_TACKI_IRQ  97
-#define IIC0_WAITI_IRQ  98
-#define IIC0_DTEI_IRQ   99
-#define IIC0_IPR_ADDR   INTC_IPRH
-#define IIC0_IPR_POS    0
-#define IIC0_PRIORITY   3
-/* IIC(1) (IIC Bus Interface) */
-#define IIC1_ALI_IRQ    44
-#define IIC1_TACKI_IRQ  45
-#define IIC1_WAITI_IRQ  46
-#define IIC1_DTEI_IRQ   47
-#define IIC1_IPR_ADDR   INTC_IPRI
-#define IIC1_IPR_POS    0
-#define IIC1_PRIORITY   3
-/* SIO0 */
-#define SIO0_IRQ        88
-#define SIO0_IPR_ADDR   INTC_IPRI
-#define SIO0_IPR_POS    3
-#define SIO0_PRIORITY   3
-/* SDHI */
-#define SDHI_SDHII0_IRQ 100
-#define SDHI_SDHII1_IRQ 101
-#define SDHI_SDHII2_IRQ 102
-#define SDHI_SDHII3_IRQ 103
-#define SDHI_IPR_ADDR   INTC_IPRK
-#define SDHI_IPR_POS    0
-#define SDHI_PRIORITY   3
-/* SIU (Sound Interface Unit) */
-#define SIU_IRQ         108
-#define SIU_IPR_ADDR    INTC_IPRJ
-#define SIU_IPR_POS     1
-#define SIU_PRIORITY    3
-#define PORT_PACR       0xA4050100UL
-#define PORT_PBCR       0xA4050102UL
-#define PORT_PCCR       0xA4050104UL
-#define PORT_PDCR       0xA4050106UL
-#define PORT_PECR       0xA4050108UL
-#define PORT_PFCR       0xA405010AUL
-#define PORT_PGCR       0xA405010CUL
-#define PORT_PHCR       0xA405010EUL
-#define PORT_PJCR       0xA4050110UL
-#define PORT_PKCR       0xA4050112UL
-#define PORT_PLCR       0xA4050114UL
-#define PORT_SCPCR      0xA4050116UL
-#define PORT_PMCR       0xA4050118UL
-#define PORT_PNCR       0xA405011AUL
-#define PORT_PQCR       0xA405011CUL
-#define PORT_PRCR       0xA405011EUL
-#define PORT_PTCR       0xA405014CUL
-#define PORT_PUCR       0xA405014EUL
-#define PORT_PVCR       0xA4050150UL
-#define PORT_PSELA      0xA4050140UL
-#define PORT_PSELB      0xA4050142UL
-#define PORT_PSELC      0xA4050144UL
-#define PORT_PSELE      0xA4050158UL
-#define PORT_HIZCRA     0xA4050146UL
-#define PORT_HIZCRB     0xA4050148UL
-#define PORT_DRVCR      0xA405014AUL
-#define PORT_PADR       0xA4050120UL
-#define PORT_PBDR       0xA4050122UL
-#define PORT_PCDR       0xA4050124UL
-#define PORT_PDDR       0xA4050126UL
-#define PORT_PEDR       0xA4050128UL
-#define PORT_PFDR       0xA405012AUL
-#define PORT_PGDR       0xA405012CUL
-#define PORT_PHDR       0xA405012EUL
-#define PORT_PJDR       0xA4050130UL
-#define PORT_PKDR       0xA4050132UL
-#define PORT_PLDR       0xA4050134UL
-#define PORT_SCPDR      0xA4050136UL
-#define PORT_PMDR       0xA4050138UL
-#define PORT_PNDR       0xA405013AUL
-#define PORT_PQDR       0xA405013CUL
-#define PORT_PRDR       0xA405013EUL
-#define PORT_PTDR       0xA405016CUL
-#define PORT_PUDR       0xA405016EUL
-#define PORT_PVDR       0xA4050170UL
-#define IRQ0_IRQ        32
-#define IRQ1_IRQ        33
-#define IRQ2_IRQ        34
-#define IRQ3_IRQ        35
-#define IRQ4_IRQ        36
-#define IRQ5_IRQ        37
-#define IRQ6_IRQ        38
-#define IRQ7_IRQ        39
-#define INTPRI00        0xA4140010UL
-#define IRQ0_IPR_ADDR   INTPRI00
-#define IRQ1_IPR_ADDR   INTPRI00
-#define IRQ2_IPR_ADDR   INTPRI00
-#define IRQ3_IPR_ADDR   INTPRI00
-#define IRQ4_IPR_ADDR   INTPRI00
-#define IRQ5_IPR_ADDR   INTPRI00
-#define IRQ6_IPR_ADDR   INTPRI00
-#define IRQ7_IPR_ADDR   INTPRI00
-#define IRQ0_IPR_POS    7
-#define IRQ1_IPR_POS    6
-#define IRQ2_IPR_POS    5
-#define IRQ3_IPR_POS    4
-#define IRQ4_IPR_POS    3
-#define IRQ5_IPR_POS    2
-#define IRQ6_IPR_POS    1
-#define IRQ7_IPR_POS    0
-#define IRQ0_PRIORITY   1
-#define IRQ1_PRIORITY   1
-#define IRQ2_PRIORITY   1
-#define IRQ3_PRIORITY   1
-#define IRQ4_PRIORITY   1
-#define IRQ5_PRIORITY   1
-#define IRQ6_PRIORITY   1
-#define IRQ7_PRIORITY   1
-#endif /* __ASM_SH_IRQ_SH7343_H */
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
deleted file mode 100644
index 19912ae6a7f7..000000000000
--- a/include/asm-sh/irq-sh7780.h
+++ /dev/null
@@ -1,311 +0,0 @@
-#ifndef __ASM_SH_IRQ_SH7780_H
-#define __ASM_SH_IRQ_SH7780_H
-/*
- * linux/include/asm-sh/irq-sh7780.h
- *
- * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
- */
-#define INTC_BASE       0xffd00000
-#define INTC_ICR0       (INTC_BASE+0x0)
-#define INTC_ICR1       (INTC_BASE+0x1c)
-#define INTC_INTPRI     (INTC_BASE+0x10)
-#define INTC_INTREQ     (INTC_BASE+0x24)
-#define INTC_INTMSK0    (INTC_BASE+0x44)
-#define INTC_INTMSK1    (INTC_BASE+0x48)
-#define INTC_INTMSK2    (INTC_BASE+0x40080)
-#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
-#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
-#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
-#define INTC_NMIFCR     (INTC_BASE+0xc0)
-#define INTC_USERIMASK  (INTC_BASE+0x30000)
-#define INTC_INT2PRI0   (INTC_BASE+0x40000)
-#define INTC_INT2PRI1   (INTC_BASE+0x40004)
-#define INTC_INT2PRI2   (INTC_BASE+0x40008)
-#define INTC_INT2PRI3   (INTC_BASE+0x4000c)
-#define INTC_INT2PRI4   (INTC_BASE+0x40010)
-#define INTC_INT2PRI5   (INTC_BASE+0x40014)
-#define INTC_INT2PRI6   (INTC_BASE+0x40018)
-#define INTC_INT2PRI7   (INTC_BASE+0x4001c)
-#define INTC_INT2A0     (INTC_BASE+0x40030)
-#define INTC_INT2A1     (INTC_BASE+0x40034)
-#define INTC_INT2MSKR   (INTC_BASE+0x40038)
-#define INTC_INT2MSKCR  (INTC_BASE+0x4003c)
-#define INTC_INT2B0     (INTC_BASE+0x40040)
-#define INTC_INT2B1     (INTC_BASE+0x40044)
-#define INTC_INT2B2     (INTC_BASE+0x40048)
-#define INTC_INT2B3     (INTC_BASE+0x4004c)
-#define INTC_INT2B4     (INTC_BASE+0x40050)
-#define INTC_INT2B5     (INTC_BASE+0x40054)
-#define INTC_INT2B6     (INTC_BASE+0x40058)
-#define INTC_INT2B7     (INTC_BASE+0x4005c)
-#define INTC_INT2GPIC   (INTC_BASE+0x40090)
-/*
-  NOTE:
-  *_IRQ = (INTEVT2 - 0x200)/0x20
-*/
-/* IRQ 0-7 line external int*/
-#define IRQ0_IRQ        2
-#define IRQ0_IPR_ADDR   INTC_INTPRI
-#define IRQ0_IPR_POS    7
-#define IRQ0_PRIORITY   2
-#define IRQ1_IRQ        4
-#define IRQ1_IPR_ADDR   INTC_INTPRI
-#define IRQ1_IPR_POS    6
-#define IRQ1_PRIORITY   2
-#define IRQ2_IRQ        6
-#define IRQ2_IPR_ADDR   INTC_INTPRI
-#define IRQ2_IPR_POS    5
-#define IRQ2_PRIORITY   2
-#define IRQ3_IRQ        8
-#define IRQ3_IPR_ADDR   INTC_INTPRI
-#define IRQ3_IPR_POS    4
-#define IRQ3_PRIORITY   2
-#define IRQ4_IRQ        10
-#define IRQ4_IPR_ADDR   INTC_INTPRI
-#define IRQ4_IPR_POS    3
-#define IRQ4_PRIORITY   2
-#define IRQ5_IRQ        12
-#define IRQ5_IPR_ADDR   INTC_INTPRI
-#define IRQ5_IPR_POS    2
-#define IRQ5_PRIORITY   2
-#define IRQ6_IRQ        14
-#define IRQ6_IPR_ADDR   INTC_INTPRI
-#define IRQ6_IPR_POS    1
-#define IRQ6_PRIORITY   2
-#define IRQ7_IRQ        0
-#define IRQ7_IPR_ADDR   INTC_INTPRI
-#define IRQ7_IPR_POS    0
-#define IRQ7_PRIORITY   2
-/* TMU */
-/* ch0 */
-#define TMU_IRQ         28
-#define TMU_IPR_ADDR    INTC_INT2PRI0
-#define TMU_IPR_POS     3
-#define TMU_PRIORITY    2
-#define TIMER_IRQ       28
-#define TIMER_IPR_ADDR  INTC_INT2PRI0
-#define TIMER_IPR_POS   3
-#define TIMER_PRIORITY  2
-/* ch 1*/
-#define TMU_CH1_IRQ             29
-#define TMU_CH1_IPR_ADDR        INTC_INT2PRI0
-#define TMU_CH1_IPR_POS         2
-#define TMU_CH1_PRIORITY        2
-#define TIMER1_IRQ      29
-#define TIMER1_IPR_ADDR INTC_INT2PRI0
-#define TIMER1_IPR_POS  2
-#define TIMER1_PRIORITY 2
-/* ch 2*/
-#define TMU_CH2_IRQ             30
-#define TMU_CH2_IPR_ADDR        INTC_INT2PRI0
-#define TMU_CH2_IPR_POS         1
-#define TMU_CH2_PRIORITY        2
-/* ch 2 Input capture */
-#define TMU_CH2IC_IRQ           31
-#define TMU_CH2IC_IPR_ADDR      INTC_INT2PRI0
-#define TMU_CH2IC_IPR_POS       0
-#define TMU_CH2IC_PRIORITY      2
-/* ch 3 */
-#define TMU_CH3_IRQ             96
-#define TMU_CH3_IPR_ADDR        INTC_INT2PRI1
-#define TMU_CH3_IPR_POS         3
-#define TMU_CH3_PRIORITY        2
-/* ch 4 */
-#define TMU_CH4_IRQ             97
-#define TMU_CH4_IPR_ADDR        INTC_INT2PRI1
-#define TMU_CH4_IPR_POS         2
-#define TMU_CH4_PRIORITY        2
-/* ch 5*/
-#define TMU_CH5_IRQ             98
-#define TMU_CH5_IPR_ADDR        INTC_INT2PRI1
-#define TMU_CH5_IPR_POS         1
-#define TMU_CH5_PRIORITY        2
-/* SCIF0 */
-#define SCIF0_ERI_IRQ   40
-#define SCIF0_RXI_IRQ   41
-#define SCIF0_BRI_IRQ   42
-#define SCIF0_TXI_IRQ   43
-#define SCIF0_IPR_ADDR  INTC_INT2PRI2
-#define SCIF0_IPR_POS   3
-#define SCIF0_PRIORITY  3
-/* SCIF1 */
-#define SCIF1_ERI_IRQ   76
-#define SCIF1_RXI_IRQ   77
-#define SCIF1_BRI_IRQ   78
-#define SCIF1_TXI_IRQ   79
-#define SCIF1_IPR_ADDR  INTC_INT2PRI2
-#define SCIF1_IPR_POS   2
-#define SCIF1_PRIORITY  3
-#define WDT_IRQ         27
-#define WDT_IPR_ADDR    INTC_INT2PRI2
-#define WDT_IPR_POS     1
-#define WDT_PRIORITY    2
-/* DMAC(0) */
-#define DMINT0_IRQ      34
-#define DMINT1_IRQ      35
-#define DMINT2_IRQ      36
-#define DMINT3_IRQ      37
-#define DMINT4_IRQ      44
-#define DMINT5_IRQ      45
-#define DMINT6_IRQ      46
-#define DMINT7_IRQ      47
-#define DMAE_IRQ        38
-#define DMA0_IPR_ADDR   INTC_INT2PRI3
-#define DMA0_IPR_POS    2
-#define DMA0_PRIORITY   7
-/* DMAC(1) */
-#define DMINT8_IRQ      92
-#define DMINT9_IRQ      93
-#define DMINT10_IRQ     94
-#define DMINT11_IRQ     95
-#define DMA1_IPR_ADDR   INTC_INT2PRI3
-#define DMA1_IPR_POS    1
-#define DMA1_PRIORITY   7
-#define DMTE0_IRQ       DMINT0_IRQ
-#define DMTE4_IRQ       DMINT4_IRQ
-#define DMA_IPR_ADDR    DMA0_IPR_ADDR
-#define DMA_IPR_POS     DMA0_IPR_POS
-#define DMA_PRIORITY    DMA0_PRIORITY
-/* CMT */
-#define CMT_IRQ         56
-#define CMT_IPR_ADDR    INTC_INT2PRI4
-#define CMT_IPR_POS     3
-#define CMT_PRIORITY    0
-/* HAC */
-#define HAC_IRQ         60
-#define HAC_IPR_ADDR    INTC_INT2PRI4
-#define HAC_IPR_POS     2
-#define CMT_PRIORITY    0
-/* PCIC(0) */
-#define PCIC0_IRQ       64
-#define PCIC0_IPR_ADDR  INTC_INT2PRI4
-#define PCIC0_IPR_POS   1
-#define PCIC0_PRIORITY  2
-/* PCIC(1) */
-#define PCIC1_IRQ       65
-#define PCIC1_IPR_ADDR  INTC_INT2PRI4
-#define PCIC1_IPR_POS   0
-#define PCIC1_PRIORITY  2
-/* PCIC(2) */
-#define PCIC2_IRQ       66
-#define PCIC2_IPR_ADDR  INTC_INT2PRI5
-#define PCIC2_IPR_POS   3
-#define PCIC2_PRIORITY  2
-/* PCIC(3) */
-#define PCIC3_IRQ       67
-#define PCIC3_IPR_ADDR  INTC_INT2PRI5
-#define PCIC3_IPR_POS   2
-#define PCIC3_PRIORITY  2
-/* PCIC(4) */
-#define PCIC4_IRQ       68
-#define PCIC4_IPR_ADDR  INTC_INT2PRI5
-#define PCIC4_IPR_POS   1
-#define PCIC4_PRIORITY  2
-/* PCIC(5) */
-#define PCICERR_IRQ     69
-#define PCICPWD3_IRQ    70
-#define PCICPWD2_IRQ    71
-#define PCICPWD1_IRQ    72
-#define PCICPWD0_IRQ    73
-#define PCIC5_IPR_ADDR  INTC_INT2PRI5
-#define PCIC5_IPR_POS   0
-#define PCIC5_PRIORITY  2
-/* SIOF */
-#define SIOF_IRQ        80
-#define SIOF_IPR_ADDR   INTC_INT2PRI6
-#define SIOF_IPR_POS    3
-#define SIOF_PRIORITY   3
-/* HSPI */
-#define HSPI_IRQ        84
-#define HSPI_IPR_ADDR   INTC_INT2PRI6
-#define HSPI_IPR_POS    2
-#define HSPI_PRIORITY   3
-/* MMCIF */
-#define MMCIF_FSTAT_IRQ 88
-#define MMCIF_TRAN_IRQ  89
-#define MMCIF_ERR_IRQ   90
-#define MMCIF_FRDY_IRQ  91
-#define MMCIF_IPR_ADDR  INTC_INT2PRI6
-#define MMCIF_IPR_POS   1
-#define HSPI_PRIORITY   3
-/* SSI */
-#define SSI_IRQ         100
-#define SSI_IPR_ADDR    INTC_INT2PRI6
-#define SSI_IPR_POS     0
-#define SSI_PRIORITY    3
-/* FLCTL */
-#define FLCTL_FLSTE_IRQ         104
-#define FLCTL_FLTEND_IRQ        105
-#define FLCTL_FLTRQ0_IRQ        106
-#define FLCTL_FLTRQ1_IRQ        107
-#define FLCTL_IPR_ADDR          INTC_INT2PRI7
-#define FLCTL_IPR_POS           3
-#define FLCTL_PRIORITY          3
-/* GPIO */
-#define GPIO0_IRQ       108
-#define GPIO1_IRQ       109
-#define GPIO2_IRQ       110
-#define GPIO3_IRQ       111
-#define GPIO_IPR_ADDR   INTC_INT2PRI7
-#define GPIO_IPR_POS    2
-#define GPIO_PRIORITY   3
-#define INTC_TMU0_MSK   0
-#define INTC_TMU3_MSK   1
-#define INTC_RTC_MSK    2
-#define INTC_SCIF0_MSK  3
-#define INTC_SCIF1_MSK  4
-#define INTC_WDT_MSK    5
-#define INTC_HUID_MSK   7
-#define INTC_DMAC0_MSK  8
-#define INTC_DMAC1_MSK  9
-#define INTC_CMT_MSK    12
-#define INTC_HAC_MSK    13
-#define INTC_PCIC0_MSK  14
-#define INTC_PCIC1_MSK  15
-#define INTC_PCIC2_MSK  16
-#define INTC_PCIC3_MSK  17
-#define INTC_PCIC4_MSK  18
-#define INTC_PCIC5_MSK  19
-#define INTC_SIOF_MSK   20
-#define INTC_HSPI_MSK   21
-#define INTC_MMCIF_MSK  22
-#define INTC_SSI_MSK    23
-#define INTC_FLCTL_MSK  24
-#define INTC_GPIO_MSK   25
-#endif /* __ASM_SH_IRQ_SH7780_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 6cd3e9e2a76a..fd576088e47e 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -1,233 +1,9 @@
 #ifndef __ASM_SH_IRQ_H
 #define __ASM_SH_IRQ_H
-/*
- *
- * linux/include/asm-sh/irq.h
- *
- * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
- * Copyright (C) 2000  Kazumoto Kojima
- * Copyright (C) 2003  Paul Mundt
- *
- */
 #include <asm/machvec.h>
 #include <asm/ptrace.h>         /* for pt_regs */
-#ifndef CONFIG_CPU_SUBTYPE_SH7780
-#define INTC_DMAC0_MSK  0
-#if defined(CONFIG_CPU_SH3)
-#define INTC_IPRA       0xfffffee2UL
-#define INTC_IPRB       0xfffffee4UL
-#elif defined(CONFIG_CPU_SH4)
-#define INTC_IPRA       0xffd00004UL
-#define INTC_IPRB       0xffd00008UL
-#define INTC_IPRC       0xffd0000cUL
-#define INTC_IPRD       0xffd00010UL
-#endif
-#define TIMER_IRQ       16
-#define TIMER_IPR_ADDR  INTC_IPRA
-#define TIMER_IPR_POS    3
-#define TIMER_PRIORITY   2
-#define TIMER1_IRQ      17
-#define TIMER1_IPR_ADDR INTC_IPRA
-#define TIMER1_IPR_POS   2
-#define TIMER1_PRIORITY  4
-#define RTC_IRQ         22
-#define RTC_IPR_ADDR    INTC_IPRA
-#define RTC_IPR_POS      0
-#define RTC_PRIORITY    TIMER_PRIORITY
-#if defined(CONFIG_CPU_SH3)
-#define DMTE0_IRQ       48
-#define DMTE1_IRQ       49
-#define DMTE2_IRQ       50
-#define DMTE3_IRQ       51
-#define DMA_IPR_ADDR    INTC_IPRE
-#define DMA_IPR_POS     3
-#define DMA_PRIORITY    7
-#if defined(CONFIG_CPU_SUBTYPE_SH7300)
-/* TMU2 */
-#define TIMER2_IRQ      18
-#define TIMER2_IPR_ADDR INTC_IPRA
-#define TIMER2_IPR_POS   1
-#define TIMER2_PRIORITY  2
-/* WDT */
-#define WDT_IRQ         27
-#define WDT_IPR_ADDR    INTC_IPRB
-#define WDT_IPR_POS      3
-#define WDT_PRIORITY     2
-/* SIM (SIM Card Module) */
-#define SIM_ERI_IRQ     23
-#define SIM_RXI_IRQ     24
-#define SIM_TXI_IRQ     25
-#define SIM_TEND_IRQ    26
-#define SIM_IPR_ADDR    INTC_IPRB
-#define SIM_IPR_POS      1
-#define SIM_PRIORITY     2
-/* VIO (Video I/O) */
-#define VIO_IRQ         52
-#define VIO_IPR_ADDR    INTC_IPRE
-#define VIO_IPR_POS      2
-#define VIO_PRIORITY     2
-/* MFI (Multi Functional Interface) */
-#define MFI_IRQ         56
-#define MFI_IPR_ADDR    INTC_IPRE
-#define MFI_IPR_POS      1
-#define MFI_PRIORITY     2
-/* VPU (Video Processing Unit) */
-#define VPU_IRQ         60
-#define VPU_IPR_ADDR    INTC_IPRE
-#define VPU_IPR_POS      0
-#define VPU_PRIORITY     2
-/* KEY (Key Scan Interface) */
-#define KEY_IRQ         79
-#define KEY_IPR_ADDR    INTC_IPRF
-#define KEY_IPR_POS      3
-#define KEY_PRIORITY     2
-/* CMT (Compare Match Timer) */
-#define CMT_IRQ         104
-#define CMT_IPR_ADDR    INTC_IPRF
-#define CMT_IPR_POS      0
-#define CMT_PRIORITY     2
-/* DMAC(1) */
-#define DMTE0_IRQ       48
-#define DMTE1_IRQ       49
-#define DMTE2_IRQ       50
-#define DMTE3_IRQ       51
-#define DMA1_IPR_ADDR   INTC_IPRE
-#define DMA1_IPR_POS    3
-#define DMA1_PRIORITY   7
-/* DMAC(2) */
-#define DMTE4_IRQ       76
-#define DMTE5_IRQ       77
-#define DMA2_IPR_ADDR   INTC_IPRF
-#define DMA2_IPR_POS    2
-#define DMA2_PRIORITY   7
-/* SIOF0 */
-#define SIOF0_IRQ       84
-#define SIOF0_IPR_ADDR  INTC_IPRH
-#define SIOF0_IPR_POS   3
-#define SIOF0_PRIORITY  3
-/* FLCTL (Flash Memory Controller) */
-#define FLSTE_IRQ       92
-#define FLTEND_IRQ      93
-#define FLTRQ0_IRQ      94
-#define FLTRQ1_IRQ      95
-#define FLCTL_IPR_ADDR  INTC_IPRH
-#define FLCTL_IPR_POS   1
-#define FLCTL_PRIORITY  3
-/* IIC (IIC Bus Interface) */
-#define IIC_ALI_IRQ     96
-#define IIC_TACKI_IRQ   97
-#define IIC_WAITI_IRQ   98
-#define IIC_DTEI_IRQ    99
-#define IIC_IPR_ADDR    INTC_IPRH
-#define IIC_IPR_POS     0
-#define IIC_PRIORITY    3
-/* SIO0 */
-#define SIO0_IRQ        88
-#define SIO0_IPR_ADDR   INTC_IPRI
-#define SIO0_IPR_POS    3
-#define SIO0_PRIORITY   3
-/* SIU (Sound Interface Unit) */
-#define SIU_IRQ         108
-#define SIU_IPR_ADDR    INTC_IPRJ
-#define SIU_IPR_POS     1
-#define SIU_PRIORITY    3
-#endif
-#elif defined(CONFIG_CPU_SH4)
-#define DMTE0_IRQ       34
-#define DMTE1_IRQ       35
-#define DMTE2_IRQ       36
-#define DMTE3_IRQ       37
-#define DMTE4_IRQ       44      /* 7751R only */
-#define DMTE5_IRQ       45      /* 7751R only */
-#define DMTE6_IRQ       46      /* 7751R only */
-#define DMTE7_IRQ       47      /* 7751R only */
-#define DMAE_IRQ        38
-#define DMA_IPR_ADDR    INTC_IPRC
-#define DMA_IPR_POS     2
-#define DMA_PRIORITY    7
-#endif
-#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
-    defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
-    defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
-#define SCI_ERI_IRQ     23
-#define SCI_RXI_IRQ     24
-#define SCI_TXI_IRQ     25
-#define SCI_IPR_ADDR    INTC_IPRB
-#define SCI_IPR_POS     1
-#define SCI_PRIORITY    3
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7300)
-#define SCIF0_IRQ       80
-#define SCIF0_IPR_ADDR  INTC_IPRG
-#define SCIF0_IPR_POS   3
-#define SCIF0_PRIORITY  3
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7706) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7707) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7709)
-#define SCIF_ERI_IRQ    56
-#define SCIF_RXI_IRQ    57
-#define SCIF_BRI_IRQ    58
-#define SCIF_TXI_IRQ    59
-#define SCIF_IPR_ADDR   INTC_IPRE
-#define SCIF_IPR_POS    1
-#define SCIF_PRIORITY   3
-#define IRDA_ERI_IRQ    52
-#define IRDA_RXI_IRQ    53
-#define IRDA_BRI_IRQ    54
-#define IRDA_TXI_IRQ    55
-#define IRDA_IPR_ADDR   INTC_IPRE
-#define IRDA_IPR_POS    2
-#define IRDA_PRIORITY   3
-#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
-      defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
-#define SCIF_ERI_IRQ    40
-#define SCIF_RXI_IRQ    41
-#define SCIF_BRI_IRQ    42
-#define SCIF_TXI_IRQ    43
-#define SCIF_IPR_ADDR   INTC_IPRC
-#define SCIF_IPR_POS    1
-#define SCIF_PRIORITY   3
-#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
-#define SCIF1_ERI_IRQ   23
-#define SCIF1_RXI_IRQ   24
-#define SCIF1_BRI_IRQ   25
-#define SCIF1_TXI_IRQ   26
-#define SCIF1_IPR_ADDR  INTC_IPRB
-#define SCIF1_IPR_POS   1
-#define SCIF1_PRIORITY  3
-#endif /* ST40STB1 */
-#endif /* 775x / SH4-202 / ST40STB1 */
-#endif /* 7780 */
 /* NR_IRQS is made from three components:
 *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
 *   2. PINT_NR_IRQS   - number of PINT interrupts
@@ -265,6 +41,10 @@
 # define ONCHIP_NR_IRQS 109
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 # define ONCHIP_NR_IRQS 111
+#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
+# define ONCHIP_NR_IRQS 256
+#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+# define ONCHIP_NR_IRQS 128
 #elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
 # define ONCHIP_NR_IRQS 144
 #endif
@@ -312,9 +92,11 @@
 /* NR_IRQS. 1+2+3 */
 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
-extern void disable_irq(unsigned int);
+/*
-extern void disable_irq_nosync(unsigned int);
+ * Convert back and forth between INTEVT and IRQ values.
-extern void enable_irq(unsigned int);
+ */
+#define evt2irq(evt)            (((evt) >> 5) - 16)
+#define irq2evt(irq)            (((irq) + 16) << 5)
 /*
 * Simple Mask Register Support
@@ -327,362 +109,36 @@ extern unsigned short *irq_mask_register;
 */
 void init_IRQ_pint(void);
+/*
+ * The shift value is now the number of bits to shift, not the number of
+ * bits/4. This is to make it easier to read the value directly from the
+ * datasheets. The IPR address, addr, will be set from ipr_idx via the
+ * map_ipridx_to_addr function.
+ */
 struct ipr_data {
        unsigned int irq;
-        unsigned int addr;      /* Address of Interrupt Priority Register */
+        int ipr_idx;            /* Index for the IPR registered */
-        int shift;              /* Shifts of the 16-bit data */
+        int shift;              /* Number of bits to shift the data */
        int priority;           /* The priority */
+        unsigned int addr;      /* Address of Interrupt Priority Register */
 };
 /*
- * Function for "on chip support modules".
+ * Given an IPR IDX, map the value to an IPR register address.
 */
-extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
+unsigned int map_ipridx_to_addr(int idx);
-extern void make_imask_irq(unsigned int irq);
-#if defined(CONFIG_CPU_SUBTYPE_SH7300)
-#undef INTC_IPRA
-#undef INTC_IPRB
-#define INTC_IPRA       0xA414FEE2UL
-#define INTC_IPRB       0xA414FEE4UL
-#define INTC_IPRC       0xA4140016UL
-#define INTC_IPRD       0xA4140018UL
-#define INTC_IPRE       0xA414001AUL
-#define INTC_IPRF       0xA4080000UL
-#define INTC_IPRG       0xA4080002UL
-#define INTC_IPRH       0xA4080004UL
-#define INTC_IPRI       0xA4080006UL
-#define INTC_IPRJ       0xA4080008UL
-#define INTC_IMR0       0xA4080040UL
-#define INTC_IMR1       0xA4080042UL
-#define INTC_IMR2       0xA4080044UL
-#define INTC_IMR3       0xA4080046UL
-#define INTC_IMR4       0xA4080048UL
-#define INTC_IMR5       0xA408004AUL
-#define INTC_IMR6       0xA408004CUL
-#define INTC_IMR7       0xA408004EUL
-#define INTC_IMR8       0xA4080050UL
-#define INTC_IMR9       0xA4080052UL
-#define INTC_IMR10      0xA4080054UL
-#define INTC_IMCR0      0xA4080060UL
-#define INTC_IMCR1      0xA4080062UL
-#define INTC_IMCR2      0xA4080064UL
-#define INTC_IMCR3      0xA4080066UL
-#define INTC_IMCR4      0xA4080068UL
-#define INTC_IMCR5      0xA408006AUL
-#define INTC_IMCR6      0xA408006CUL
-#define INTC_IMCR7      0xA408006EUL
-#define INTC_IMCR8      0xA4080070UL
-#define INTC_IMCR9      0xA4080072UL
-#define INTC_IMCR10     0xA4080074UL
-#define INTC_ICR0       0xA414FEE0UL
-#define INTC_ICR1       0xA4140010UL
-#define INTC_IRR0       0xA4140004UL
-#define PORT_PACR       0xA4050100UL
-#define PORT_PBCR       0xA4050102UL
-#define PORT_PCCR       0xA4050104UL
-#define PORT_PDCR       0xA4050106UL
-#define PORT_PECR       0xA4050108UL
-#define PORT_PFCR       0xA405010AUL
-#define PORT_PGCR       0xA405010CUL
-#define PORT_PHCR       0xA405010EUL
-#define PORT_PJCR       0xA4050110UL
-#define PORT_PKCR       0xA4050112UL
-#define PORT_PLCR       0xA4050114UL
-#define PORT_SCPCR      0xA4050116UL
-#define PORT_PMCR       0xA4050118UL
-#define PORT_PNCR       0xA405011AUL
-#define PORT_PQCR       0xA405011CUL
-#define PORT_PSELA      0xA4050140UL
-#define PORT_PSELB      0xA4050142UL
-#define PORT_PSELC      0xA4050144UL
-#define PORT_HIZCRA     0xA4050146UL
-#define PORT_HIZCRB     0xA4050148UL
-#define PORT_DRVCR      0xA4050150UL
-#define PORT_PADR       0xA4050120UL
-#define PORT_PBDR       0xA4050122UL
-#define PORT_PCDR       0xA4050124UL
-#define PORT_PDDR       0xA4050126UL
-#define PORT_PEDR       0xA4050128UL
-#define PORT_PFDR       0xA405012AUL
-#define PORT_PGDR       0xA405012CUL
-#define PORT_PHDR       0xA405012EUL
-#define PORT_PJDR       0xA4050130UL
-#define PORT_PKDR       0xA4050132UL
-#define PORT_PLDR       0xA4050134UL
-#define PORT_SCPDR      0xA4050136UL
-#define PORT_PMDR       0xA4050138UL
-#define PORT_PNDR       0xA405013AUL
-#define PORT_PQDR       0xA405013CUL
-#define IRQ0_IRQ        32
-#define IRQ1_IRQ        33
-#define IRQ2_IRQ        34
-#define IRQ3_IRQ        35
-#define IRQ4_IRQ        36
-#define IRQ5_IRQ        37
-#define IRQ0_IPR_ADDR   INTC_IPRC
-#define IRQ1_IPR_ADDR   INTC_IPRC
-#define IRQ2_IPR_ADDR   INTC_IPRC
-#define IRQ3_IPR_ADDR   INTC_IPRC
-#define IRQ4_IPR_ADDR   INTC_IPRD
-#define IRQ5_IPR_ADDR   INTC_IPRD
-#define IRQ0_IPR_POS    0
-#define IRQ1_IPR_POS    1
-#define IRQ2_IPR_POS    2
-#define IRQ3_IPR_POS    3
-#define IRQ4_IPR_POS    0
-#define IRQ5_IPR_POS    1
-#define IRQ0_PRIORITY   1
+/*
-#define IRQ1_PRIORITY   1
+ * Enable individual interrupt mode for external IPR IRQs.
-#define IRQ2_PRIORITY   1
+ */
-#define IRQ3_PRIORITY   1
+void ipr_irq_enable_irlm(void);
-#define IRQ4_PRIORITY   1
-#define IRQ5_PRIORITY   1
-extern int ipr_irq_demux(int irq);
-#define __irq_demux(irq) ipr_irq_demux(irq)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
-#define INTC_IPRA       0xfffffee2UL
-#define INTC_IPRB       0xfffffe60UL
-#define INTC_VCRA       0xfffffe62UL
-#define INTC_VCRB       0xfffffe64UL
-#define INTC_VCRC       0xfffffe66UL
-#define INTC_VCRD       0xfffffe68UL
-#define INTC_VCRWDT     0xfffffee4UL
-#define INTC_VCRDIV     0xffffff0cUL
-#define INTC_VCRDMA0    0xffffffa0UL
-#define INTC_VCRDMA1    0xffffffa8UL
-#define INTC_ICR        0xfffffee0UL
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7706) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7707) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7709) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7710)
-#define INTC_IRR0       0xa4000004UL
-#define INTC_IRR1       0xa4000006UL
-#define INTC_IRR2       0xa4000008UL
-#define INTC_ICR0       0xfffffee0UL
-#define INTC_ICR1       0xa4000010UL
-#define INTC_ICR2       0xa4000012UL
-#define INTC_INTER      0xa4000014UL
-#define INTC_IPRC       0xa4000016UL
-#define INTC_IPRD       0xa4000018UL
-#define INTC_IPRE       0xa400001aUL
-#if defined(CONFIG_CPU_SUBTYPE_SH7707)
-#define INTC_IPRF       0xa400001cUL
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
-#define INTC_IPRF       0xa4080000UL
-#define INTC_IPRG       0xa4080002UL
-#define INTC_IPRH       0xa4080004UL
-#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
-/* Interrupt Controller Registers */
-#undef INTC_IPRA
-#undef INTC_IPRB
-#define INTC_IPRA       0xA414FEE2UL
-#define INTC_IPRB       0xA414FEE4UL
-#define INTC_IPRF       0xA4080000UL
-#define INTC_IPRG       0xA4080002UL
-#define INTC_IPRH       0xA4080004UL
-#define INTC_IPRI       0xA4080006UL
-#undef INTC_ICR0
-#undef INTC_ICR1
-#define INTC_ICR0       0xA414FEE0UL
-#define INTC_ICR1       0xA4140010UL
-#define INTC_IRR0       0xa4000004UL
-#define INTC_IRR1       0xa4000006UL
-#define INTC_IRR2       0xa4000008UL
-#define INTC_IRR3       0xa400000AUL
-#define INTC_IRR4       0xa400000CUL
-#define INTC_IRR5       0xa4080020UL
-#define INTC_IRR7       0xa4080024UL
-#define INTC_IRR8       0xa4080026UL
-/* Interrupt numbers */
-#define TIMER2_IRQ      18
-#define TIMER2_IPR_ADDR INTC_IPRA
-#define TIMER2_IPR_POS   1
-#define TIMER2_PRIORITY  2
-/* WDT */
-#define WDT_IRQ         27
-#define WDT_IPR_ADDR    INTC_IPRB
-#define WDT_IPR_POS      3
-#define WDT_PRIORITY     2
-#define SCIF0_ERI_IRQ   52
-#define SCIF0_RXI_IRQ   53
-#define SCIF0_BRI_IRQ   54
-#define SCIF0_TXI_IRQ   55
-#define SCIF0_IPR_ADDR  INTC_IPRE
-#define SCIF0_IPR_POS   2
-#define SCIF0_PRIORITY  3
-#define DMTE4_IRQ       76
-#define DMTE5_IRQ       77
-#define DMA2_IPR_ADDR   INTC_IPRF
-#define DMA2_IPR_POS    2
-#define DMA2_PRIORITY   7
-#define IPSEC_IRQ       79
-#define IPSEC_IPR_ADDR  INTC_IPRF
-#define IPSEC_IPR_POS   3
-#define IPSEC_PRIORITY  3
-/* EDMAC */
-#define EDMAC0_IRQ      80
-#define EDMAC0_IPR_ADDR INTC_IPRG
-#define EDMAC0_IPR_POS  3
-#define EDMAC0_PRIORITY 3
-#define EDMAC1_IRQ      81
-#define EDMAC1_IPR_ADDR INTC_IPRG
-#define EDMAC1_IPR_POS  2
-#define EDMAC1_PRIORITY 3
-#define EDMAC2_IRQ      82
-#define EDMAC2_IPR_ADDR INTC_IPRG
-#define EDMAC2_IPR_POS  1
-#define EDMAC2_PRIORITY 3
-/* SIOF */
-#define SIOF0_ERI_IRQ   96
-#define SIOF0_TXI_IRQ   97
-#define SIOF0_RXI_IRQ   98
-#define SIOF0_CCI_IRQ   99
-#define SIOF0_IPR_ADDR  INTC_IPRH
-#define SIOF0_IPR_POS   0
-#define SIOF0_PRIORITY  7
-#define SIOF1_ERI_IRQ   100
-#define SIOF1_TXI_IRQ   101
-#define SIOF1_RXI_IRQ   102
-#define SIOF1_CCI_IRQ   103
-#define SIOF1_IPR_ADDR  INTC_IPRI
-#define SIOF1_IPR_POS   1
-#define SIOF1_PRIORITY  7
-#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
-#if defined(CONFIG_CPU_SUBTYPE_SH7710)
-#define PORT_PACR       0xa4050100UL
-#define PORT_PBCR       0xa4050102UL
-#define PORT_PCCR       0xa4050104UL
-#define PORT_PETCR      0xa4050106UL
-#define PORT_PADR       0xa4050120UL
-#define PORT_PBDR       0xa4050122UL
-#define PORT_PCDR       0xa4050124UL
-#else
-#define PORT_PACR       0xa4000100UL
-#define PORT_PBCR       0xa4000102UL
-#define PORT_PCCR       0xa4000104UL
-#define PORT_PFCR       0xa400010aUL
-#define PORT_PADR       0xa4000120UL
-#define PORT_PBDR       0xa4000122UL
-#define PORT_PCDR       0xa4000124UL
-#define PORT_PFDR       0xa400012aUL
-#endif
-#define IRQ0_IRQ        32
-#define IRQ1_IRQ        33
-#define IRQ2_IRQ        34
-#define IRQ3_IRQ        35
-#define IRQ4_IRQ        36
-#define IRQ5_IRQ        37
-#define IRQ0_IPR_ADDR   INTC_IPRC
-#define IRQ1_IPR_ADDR   INTC_IPRC
-#define IRQ2_IPR_ADDR   INTC_IPRC
-#define IRQ3_IPR_ADDR   INTC_IPRC
-#define IRQ4_IPR_ADDR   INTC_IPRD
-#define IRQ5_IPR_ADDR   INTC_IPRD
-#define IRQ0_IPR_POS    0
-#define IRQ1_IPR_POS    1
-#define IRQ2_IPR_POS    2
-#define IRQ3_IPR_POS    3
-#define IRQ4_IPR_POS    0
-#define IRQ5_IPR_POS    1
-#define IRQ0_PRIORITY   1
-#define IRQ1_PRIORITY   1
-#define IRQ2_PRIORITY   1
-#define IRQ3_PRIORITY   1
-#define IRQ4_PRIORITY   1
-#define IRQ5_PRIORITY   1
-#define PINT0_IRQ       40
-#define PINT8_IRQ       41
-#define PINT0_IPR_ADDR  INTC_IPRD
-#define PINT8_IPR_ADDR  INTC_IPRD
-#define PINT0_IPR_POS   3
-#define PINT8_IPR_POS   2
-#define PINT0_PRIORITY  2
-#define PINT8_PRIORITY  2
-extern int ipr_irq_demux(int irq);
-#define __irq_demux(irq) ipr_irq_demux(irq)
-#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
-#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
-    defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
-#define INTC_ICR        0xffd00000
-#define INTC_ICR_NMIL   (1<<15)
-#define INTC_ICR_MAI    (1<<14)
-#define INTC_ICR_NMIB   (1<<9)
-#define INTC_ICR_NMIE   (1<<8)
-#define INTC_ICR_IRLM   (1<<7)
-#endif
-#ifdef CONFIG_CPU_SUBTYPE_SH7780
-#include <asm/irq-sh7780.h>
-#endif
-/* SH with INTC2-style interrupts */
-#ifdef CONFIG_CPU_HAS_INTC2_IRQ
-#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
-#define INTC2_BASE      0xfe080000
-#define INTC2_FIRST_IRQ 64
-#define INTC2_INTREQ_OFFSET     0x20
-#define INTC2_INTMSK_OFFSET     0x40
-#define INTC2_INTMSKCLR_OFFSET  0x60
-#define NR_INTC2_IRQS   25
-#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
-#define INTC2_BASE      0xfe080000
-#define INTC2_FIRST_IRQ 48      /* INTEVT 0x800 */
-#define INTC2_INTREQ_OFFSET     0x20
-#define INTC2_INTMSK_OFFSET     0x40
-#define INTC2_INTMSKCLR_OFFSET  0x60
-#define NR_INTC2_IRQS   64
-#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
-#define INTC2_BASE      0xffd40000
-#define INTC2_FIRST_IRQ 21
-#define INTC2_INTMSK_OFFSET     (0x38)
-#define INTC2_INTMSKCLR_OFFSET  (0x3c)
-#define NR_INTC2_IRQS   60
-#endif
-#define INTC2_INTPRI_OFFSET     0x00
+/*
+ * Function for "on chip support modules".
+ */
+void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
+void make_imask_irq(unsigned int irq);
+void init_IRQ_ipr(void);
 struct intc2_data {
        unsigned short irq;
@@ -693,20 +149,14 @@ struct intc2_data {
 void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
 void init_IRQ_intc2(void);
-#endif
-extern int shmse_irq_demux(int irq);
 static inline int generic_irq_demux(int irq)
 {
        return irq;
 }
-#ifndef __irq_demux
-#define __irq_demux(irq)        (irq)
-#endif
 #define irq_canonicalize(irq)   (irq)
-#define irq_demux(irq)          __irq_demux(sh_mv.mv_irq_demux(irq))
+#define irq_demux(irq)          sh_mv.mv_irq_demux(irq)
 #ifdef CONFIG_4KSTACKS
 extern void irq_ctx_init(int cpu);
@@ -717,12 +167,4 @@ extern void irq_ctx_exit(int cpu);
 # define irq_ctx_exit(cpu) do { } while (0)
 #endif
-#if defined(CONFIG_CPU_SUBTYPE_SH73180)
-#include <asm/irq-sh73180.h>
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7343)
-#include <asm/irq-sh7343.h>
-#endif
 #endif /* __ASM_SH_IRQ_H */
diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h
new file mode 100644
index 000000000000..9dedc1b693e3
--- /dev/null
+++ b/include/asm-sh/irqflags.h
@@ -0,0 +1,123 @@
+#ifndef __ASM_SH_IRQFLAGS_H
+#define __ASM_SH_IRQFLAGS_H
+static inline void raw_local_irq_enable(void)
+{
+        unsigned long __dummy0, __dummy1;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    %1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+                "stc    r6_bank, %1\n\t"
+                "or     %1, %0\n\t"
+#endif
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "1" (~0x000000f0)
+                : "memory"
+        );
+}
+static inline void raw_local_irq_disable(void)
+{
+        unsigned long flags;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "or     #0xf0, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&z" (flags)
+                : /* no inputs */
+                : "memory"
+        );
+}
+static inline void set_bl_bit(void)
+{
+        unsigned long __dummy0, __dummy1;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "or     %2, %0\n\t"
+                "and    %3, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "r" (0x10000000), "r" (0xffffff0f)
+                : "memory"
+        );
+}
+static inline void clear_bl_bit(void)
+{
+        unsigned long __dummy0, __dummy1;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    %2, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "1" (~0x10000000)
+                : "memory"
+        );
+}
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long flags;
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    #0xf0, %0\n\t"
+                : "=&z" (flags)
+                : /* no inputs */
+                : "memory"
+        );
+        return flags;
+}
+#define raw_local_save_flags(flags) \
+                do { (flags) = __raw_local_save_flags(); } while (0)
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags != 0);
+}
+static inline int raw_irqs_disabled(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+        return raw_irqs_disabled_flags(flags);
+}
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long flags, __dummy;
+        __asm__ __volatile__ (
+                "stc    sr, %1\n\t"
+                "mov    %1, %0\n\t"
+                "or     #0xf0, %0\n\t"
+                "ldc    %0, sr\n\t"
+                "mov    %1, %0\n\t"
+                "and    #0xf0, %0\n\t"
+                : "=&z" (flags), "=&r" (__dummy)
+                : /* no inputs */
+                : "memory"
+        );
+        return flags;
+}
+#define raw_local_irq_save(flags) \
+                do { (flags) = __raw_local_irq_save(); } while (0)
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        if ((flags & 0xf0) != 0xf0)
+                raw_local_irq_enable();
+}
+#endif /* __ASM_SH_IRQFLAGS_H */
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index c7088efe579a..46f04e23bd45 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -10,7 +10,6 @@
 #include <asm/cpu/mmu_context.h>
 #include <asm/tlbflush.h>
-#include <asm/pgalloc.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
@@ -42,10 +41,8 @@ extern unsigned long mmu_context_cache;
 /*
 * Get MMU context if needed.
 */
-static __inline__ void
+static inline void get_mmu_context(struct mm_struct *mm)
-get_mmu_context(struct mm_struct *mm)
 {
-        extern void flush_tlb_all(void);
        unsigned long mc = mmu_context_cache;
        /* Check if we have old version of context. */
@@ -61,6 +58,7 @@ get_mmu_context(struct mm_struct *mm)
                 * Flush all TLB and start new cycle.
                 */
                flush_tlb_all();
                /*
                 * Fix version; Note that we avoid version #0
                 * to distingush NO_CONTEXT.
@@ -75,11 +73,10 @@ get_mmu_context(struct mm_struct *mm)
 * Initialize the context related info for a new mm_struct
 * instance.
 */
-static __inline__ int init_new_context(struct task_struct *tsk,
+static inline int init_new_context(struct task_struct *tsk,
                                       struct mm_struct *mm)
 {
        mm->context.id = NO_CONTEXT;
        return 0;
 }
@@ -87,12 +84,12 @@ static __inline__ int init_new_context(struct task_struct *tsk,
 * Destroy context related info for an mm_struct that is about
 * to be put to rest.
 */
-static __inline__ void destroy_context(struct mm_struct *mm)
+static inline void destroy_context(struct mm_struct *mm)
 {
        /* Do nothing */
 }
-static __inline__ void set_asid(unsigned long asid)
+static inline void set_asid(unsigned long asid)
 {
        unsigned long __dummy;
@@ -105,7 +102,7 @@ static __inline__ void set_asid(unsigned long asid)
                                "r" (0xffffff00));
 }
-static __inline__ unsigned long get_asid(void)
+static inline unsigned long get_asid(void)
 {
        unsigned long asid;
@@ -120,24 +117,29 @@ static __inline__ unsigned long get_asid(void)
 * After we have set current->mm to a new value, this activates
 * the context for the new mm so we see the new mappings.
 */
-static __inline__ void activate_context(struct mm_struct *mm)
+static inline void activate_context(struct mm_struct *mm)
 {
        get_mmu_context(mm);
        set_asid(mm->context.id & MMU_CONTEXT_ASID_MASK);
 }
-/* MMU_TTB can be used for optimizing the fault handling.
+/* MMU_TTB is used for optimizing the fault handling. */
-   (Currently not used) */
+static inline void set_TTB(pgd_t *pgd)
-static __inline__ void switch_mm(struct mm_struct *prev,
-                                 struct mm_struct *next,
-                                 struct task_struct *tsk)
 {
-        if (likely(prev != next)) {
+        ctrl_outl((unsigned long)pgd, MMU_TTB);
-                unsigned long __pgdir = (unsigned long)next->pgd;
+}
-                __asm__ __volatile__("mov.l     %0, %1"
+static inline pgd_t *get_TTB(void)
-                                     : /* no output */
+{
-                                     : "r" (__pgdir), "m" (__m(MMU_TTB)));
+        return (pgd_t *)ctrl_inl(MMU_TTB);
+}
+static inline void switch_mm(struct mm_struct *prev,
+                             struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        if (likely(prev != next)) {
+                set_TTB(next->pgd);
                activate_context(next);
        }
 }
@@ -147,7 +149,7 @@ static __inline__ void switch_mm(struct mm_struct *prev,
 #define activate_mm(prev, next) \
        switch_mm((prev),(next),NULL)
-static __inline__ void
+static inline void
 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 }
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index ca8b26d90475..380fd62dd05a 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -13,9 +13,16 @@
   [ P4 control   ]             0xE0000000
 */
 /* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT      12
+#if defined(CONFIG_PAGE_SIZE_4KB)
+# define PAGE_SHIFT     12
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+# define PAGE_SHIFT     13
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+# define PAGE_SHIFT     16
+#else
+# error "Bogus kernel page size?"
+#endif
 #ifdef __ASSEMBLY__
 #define PAGE_SIZE       (1 << PAGE_SHIFT)
@@ -28,8 +35,14 @@
 #if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
 #define HPAGE_SHIFT     16
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
+#define HPAGE_SHIFT     18
 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
 #define HPAGE_SHIFT     20
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define HPAGE_SHIFT     22
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
+#define HPAGE_SHIFT     26
 #endif
 #ifdef CONFIG_HUGETLB_PAGE
@@ -69,15 +82,25 @@ extern void __copy_user_page(void *to, void *from, void *orig_to);
 /*
 * These are used to make use of C type-checking..
 */
-typedef struct { unsigned long pte; } pte_t;
+#ifdef CONFIG_X2TLB
-typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long pte_low, pte_high; } pte_t;
+typedef struct { unsigned long long pgprot; } pgprot_t;
+#define pte_val(x) \
+        ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+#define __pte(x) \
+        ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
+#else
+typedef struct { unsigned long pte_low; } pte_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
+#define pte_val(x)      ((x).pte_low)
+#define __pte(x) ((pte_t) { (x) } )
+#endif
+typedef struct { unsigned long pgd; } pgd_t;
-#define pte_val(x)      ((x).pte)
 #define pgd_val(x)      ((x).pgd)
 #define pgprot_val(x)   ((x).pgprot)
-#define __pte(x) ((pte_t) { (x) } )
 #define __pgd(x) ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
diff --git a/include/asm-sh/pgalloc.h b/include/asm-sh/pgalloc.h
index e841465ab4d2..888e4529e6fe 100644
--- a/include/asm-sh/pgalloc.h
+++ b/include/asm-sh/pgalloc.h
@@ -1,13 +1,16 @@
 #ifndef __ASM_SH_PGALLOC_H
 #define __ASM_SH_PGALLOC_H
-#define pmd_populate_kernel(mm, pmd, pte) \
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
-                set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
+                                       pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
 static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
                                struct page *pte)
 {
-        set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
 }
 /*
@@ -15,7 +18,16 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 */
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-        return (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
+        pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT);
+        if (pgd) {
+                memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
+                memcpy(pgd + USER_PTRS_PER_PGD,
+                       swapper_pg_dir + USER_PTRS_PER_PGD,
+                       (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+        }
+        return pgd;
 }
 static inline void pgd_free(pgd_t *pgd)
diff --git a/include/asm-sh/pgtable-2level.h b/include/asm-sh/pgtable-2level.h
deleted file mode 100644
index b525db6f61c6..000000000000
--- a/include/asm-sh/pgtable-2level.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef __ASM_SH_PGTABLE_2LEVEL_H
-#define __ASM_SH_PGTABLE_2LEVEL_H
-/*
- * traditional two-level paging structure:
- */
-#define PGDIR_SHIFT     22
-#define PTRS_PER_PGD    1024
-/*
- * this is two-level, so we don't really have any
- * PMD directory physically.
- */
-#define PMD_SHIFT       22
-#define PTRS_PER_PMD    1
-#define PTRS_PER_PTE    1024
-#ifndef __ASSEMBLY__
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd)           { return 0; }
-static inline int pgd_bad(pgd_t pgd)            { return 0; }
-static inline int pgd_present(pgd_t pgd)        { return 1; }
-static inline void pgd_clear (pgd_t * pgdp)     { }
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
-#define pgd_page_vaddr(pgd) \
-((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
-#define pgd_page(pgd) \
-        (phys_to_page(pgd_val(pgd)))
-static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
-        return (pmd_t *) dir;
-}
-#define pte_pfn(x)              ((unsigned long)(((x).pte >> PAGE_SHIFT)))
-#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#endif /* !__ASSEMBLY__ */
-#endif /* __ASM_SH_PGTABLE_2LEVEL_H */
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 2c8682ad1012..c84901dbd8e5 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -15,15 +15,10 @@
 #include <asm-generic/pgtable-nopmd.h>
 #include <asm/page.h>
-#define PTRS_PER_PGD            1024
 #ifndef __ASSEMBLY__
 #include <asm/addrspace.h>
 #include <asm/fixmap.h>
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-extern void paging_init(void);
 /*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
@@ -33,15 +28,28 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #endif /* !__ASSEMBLY__ */
-/* traditional two-level paging structure */
+/*
-#define PGDIR_SHIFT     22
+ * traditional two-level paging structure
-#define PTRS_PER_PMD    1
+ */
-#define PTRS_PER_PTE    1024
+/* PTE bits */
-#define PMD_SIZE        (1UL << PMD_SHIFT)
+#ifdef CONFIG_X2TLB
-#define PMD_MASK        (~(PMD_SIZE-1))
+# define PTE_MAGNITUDE  3       /* 64-bit PTEs on extended mode SH-X2 TLB */
-#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#else
+# define PTE_MAGNITUDE  2       /* 32-bit PTEs */
+#endif
+#define PTE_SHIFT       PAGE_SHIFT
+#define PTE_BITS        (PTE_SHIFT - PTE_MAGNITUDE)
+/* PGD bits */
+#define PGDIR_SHIFT     (PTE_SHIFT + PTE_BITS)
+#define PGDIR_BITS      (32 - PGDIR_SHIFT)
+#define PGDIR_SIZE      (1 << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
+/* Entries per level */
+#define PTRS_PER_PTE    (PAGE_SIZE / 4)
+#define PTRS_PER_PGD    (PAGE_SIZE / 4)
 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS      0
@@ -49,7 +57,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 /*
 * First 1MB map is used by fixed purpose.
- * Currently only 4-enty (16kB) is used (see arch/sh/mm/cache.c)
+ * Currently only 4-entry (16kB) is used (see arch/sh/mm/cache.c)
 */
 #define VMALLOC_START   (P3SEG+0x00100000)
 #define VMALLOC_END     (FIXADDR_START-2*PAGE_SIZE)
@@ -57,7 +65,8 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 /*
 * Linux PTEL encoding.
 *
- * Hardware and software bit definitions for the PTEL value:
+ * Hardware and software bit definitions for the PTEL value (see below for
+ * notes on SH-X2 MMUs and 64-bit PTEs):
 *
 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
 *
@@ -76,20 +85,57 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 *
 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future
 *   software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
+ *
+ * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
+ *
+ * SH-X2 MMUs and extended PTEs
+ *
+ * SH-X2 supports an extended mode TLB with split data arrays due to the
+ * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
+ * SZ bit placeholders still exist in data array 1, but are implemented as
+ * reserved bits, with the real logic existing in data array 2.
+ *
+ * The downside to this is that we can no longer fit everything in to a 32-bit
+ * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
+ * side, this gives us quite a few spare bits to play with for future usage.
 */
+/* Legacy and compat mode bits */
 #define _PAGE_WT        0x001           /* WT-bit on SH-4, 0 on SH-3 */
 #define _PAGE_HW_SHARED 0x002           /* SH-bit  : shared among processes */
 #define _PAGE_DIRTY     0x004           /* D-bit   : page changed */
 #define _PAGE_CACHABLE  0x008           /* C-bit   : cachable */
-#define _PAGE_SZ0       0x010           /* SZ0-bit : Size of page */
+#ifndef CONFIG_X2TLB
-#define _PAGE_RW        0x020           /* PR0-bit : write access allowed */
+# define _PAGE_SZ0      0x010           /* SZ0-bit : Size of page */
-#define _PAGE_USER      0x040           /* PR1-bit : user space access allowed */
+# define _PAGE_RW       0x020           /* PR0-bit : write access allowed */
-#define _PAGE_SZ1       0x080           /* SZ1-bit : Size of page (on SH-4) */
+# define _PAGE_USER     0x040           /* PR1-bit : user space access allowed*/
+# define _PAGE_SZ1      0x080           /* SZ1-bit : Size of page (on SH-4) */
+#endif
 #define _PAGE_PRESENT   0x100           /* V-bit   : page is valid */
 #define _PAGE_PROTNONE  0x200           /* software: if not present  */
 #define _PAGE_ACCESSED  0x400           /* software: page referenced */
 #define _PAGE_FILE      _PAGE_WT        /* software: pagecache or swap? */
+/* Extended mode bits */
+#define _PAGE_EXT_ESZ0          0x0010  /* ESZ0-bit: Size of page */
+#define _PAGE_EXT_ESZ1          0x0020  /* ESZ1-bit: Size of page */
+#define _PAGE_EXT_ESZ2          0x0040  /* ESZ2-bit: Size of page */
+#define _PAGE_EXT_ESZ3          0x0080  /* ESZ3-bit: Size of page */
+#define _PAGE_EXT_USER_EXEC     0x0100  /* EPR0-bit: User space executable */
+#define _PAGE_EXT_USER_WRITE    0x0200  /* EPR1-bit: User space writable */
+#define _PAGE_EXT_USER_READ     0x0400  /* EPR2-bit: User space readable */
+#define _PAGE_EXT_KERN_EXEC     0x0800  /* EPR3-bit: Kernel space executable */
+#define _PAGE_EXT_KERN_WRITE    0x1000  /* EPR4-bit: Kernel space writable */
+#define _PAGE_EXT_KERN_READ     0x2000  /* EPR5-bit: Kernel space readable */
+/* Wrapper for extended mode pgprot twiddling */
+#ifdef CONFIG_X2TLB
+# define _PAGE_EXT(x)           ((unsigned long long)(x) << 32)
+#else
+# define _PAGE_EXT(x)           (0)
+#endif
 /* software: moves to PTEA.TC (Timing Control) */
 #define _PAGE_PCC_AREA5 0x00000000      /* use BSC registers for area5 */
 #define _PAGE_PCC_AREA6 0x80000000      /* use BSC registers for area6 */
@@ -114,37 +160,160 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #define _PAGE_FLAGS_HARDWARE_MASK       (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
-/* Hardware flags: SZ0=1 (4k-byte) */
+/* Hardware flags, page size encoding */
-#define _PAGE_FLAGS_HARD        _PAGE_SZ0
+#if defined(CONFIG_X2TLB)
+# if defined(CONFIG_PAGE_SIZE_4KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ0)
+# elif defined(CONFIG_PAGE_SIZE_8KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ1)
+# elif defined(CONFIG_PAGE_SIZE_64KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ2)
+# endif
+#else
+# if defined(CONFIG_PAGE_SIZE_4KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_SZ0
+# elif defined(CONFIG_PAGE_SIZE_64KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_SZ1
+# endif
+#endif
-#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#if defined(CONFIG_X2TLB)
-#define _PAGE_SZHUGE    (_PAGE_SZ1)
+# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2)
-#define _PAGE_SZHUGE    (_PAGE_SZ0 | _PAGE_SZ1)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ3)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
+# endif
+#else
+# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#  define _PAGE_SZHUGE  (_PAGE_SZ1)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_SZ0 | _PAGE_SZ1)
+# endif
+#endif
+/*
+ * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
+ * to make pte_mkhuge() happy.
+ */
+#ifndef _PAGE_SZHUGE
+# define _PAGE_SZHUGE   (_PAGE_FLAGS_HARD)
 #endif
-#define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
+#define _PAGE_CHG_MASK \
-#define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
+        (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
-#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
 #ifndef __ASSEMBLY__
-#ifdef CONFIG_MMU
+#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
-#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
-#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
-#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
-#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
-#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_READ | \
+                                           _PAGE_EXT_USER_WRITE))
+#define PAGE_EXECREAD   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_EXEC | \
+                                           _PAGE_EXT_USER_READ))
+#define PAGE_COPY       PAGE_EXECREAD
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_READ))
+#define PAGE_WRITEONLY  __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_WRITE))
+#define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_USER_WRITE | \
+                                           _PAGE_EXT_USER_READ  | \
+                                           _PAGE_EXT_USER_EXEC))
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC))
 #define PAGE_KERNEL_NOCACHE \
-                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
-#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+                                 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
+                                 _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC))
+#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_EXEC))
+#define PAGE_KERNEL_PCC(slot, type) \
+                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC) \
+                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
+                                 (type))
+#elif defined(CONFIG_MMU) /* SH-X TLB */
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
+                                 _PAGE_CACHABLE | _PAGE_ACCESSED | \
+                                 _PAGE_FLAGS_HARD)
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+#define PAGE_EXECREAD   PAGE_READONLY
+#define PAGE_RWX        PAGE_SHARED
+#define PAGE_WRITEONLY  PAGE_SHARED
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+#define PAGE_KERNEL_NOCACHE \
+                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
+                                 _PAGE_FLAGS_HARD)
+#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
 #define PAGE_KERNEL_PCC(slot, type) \
-                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_FLAGS_HARD | (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | (type))
+                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
+                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
+                                 (type))
 #else /* no mmu */
 #define PAGE_NONE               __pgprot(0)
 #define PAGE_SHARED             __pgprot(0)
 #define PAGE_COPY               __pgprot(0)
+#define PAGE_EXECREAD           __pgprot(0)
+#define PAGE_RWX                __pgprot(0)
 #define PAGE_READONLY           __pgprot(0)
+#define PAGE_WRITEONLY          __pgprot(0)
 #define PAGE_KERNEL             __pgprot(0)
 #define PAGE_KERNEL_NOCACHE     __pgprot(0)
 #define PAGE_KERNEL_RO          __pgprot(0)
@@ -154,27 +323,32 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #endif /* __ASSEMBLY__ */
 /*
- * As i386 and MIPS, SuperH can't do page protection for execute, and
+ * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
- * considers that the same as a read.  Also, write permissions imply
+ * protection for execute, and considers it the same as a read. Also, write
- * read permissions. This is the closest we can get..
+ * permission implies read permission. This is the closest we can get..
+ *
+ * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
+ * not only supporting separate execute, read, and write bits, but having
+ * completely separate permission bits for user and kernel space.
 */
+         /*xwr*/
 #define __P000  PAGE_NONE
 #define __P001  PAGE_READONLY
 #define __P010  PAGE_COPY
 #define __P011  PAGE_COPY
-#define __P100  PAGE_READONLY
+#define __P100  PAGE_EXECREAD
-#define __P101  PAGE_READONLY
+#define __P101  PAGE_EXECREAD
 #define __P110  PAGE_COPY
 #define __P111  PAGE_COPY
 #define __S000  PAGE_NONE
 #define __S001  PAGE_READONLY
-#define __S010  PAGE_SHARED
+#define __S010  PAGE_WRITEONLY
 #define __S011  PAGE_SHARED
-#define __S100  PAGE_READONLY
+#define __S100  PAGE_EXECREAD
-#define __S101  PAGE_READONLY
+#define __S101  PAGE_EXECREAD
-#define __S110  PAGE_SHARED
+#define __S110  PAGE_RWX
-#define __S111  PAGE_SHARED
+#define __S111  PAGE_RWX
 #ifndef __ASSEMBLY__
@@ -183,7 +357,17 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
+#ifdef CONFIG_X2TLB
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+        ptep->pte_high = pte.pte_high;
+        smp_wmb();
+        ptep->pte_low = pte.pte_low;
+}
+#else
 #define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#endif
 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
 /*
@@ -192,18 +376,18 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 */
 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define pte_pfn(x)              ((unsigned long)(((x).pte >> PAGE_SHIFT)))
+#define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #define pte_none(x)     (!pte_val(x))
 #define pte_present(x)  (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
-#define pte_clear(mm,addr,xp)   do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
+#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
 #define pmd_none(x)     (!pmd_val(x))
-#define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
+#define pmd_present(x)  (pmd_val(x))
 #define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
+#define pmd_bad(x)      (pmd_val(x) & ~PAGE_MASK)
 #define pages_to_mb(x)  ((x) >> (20-PAGE_SHIFT))
 #define pte_page(x)     phys_to_page(pte_val(x)&PTE_PHYS_MASK)
@@ -212,28 +396,52 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
-static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
+#define pte_not_present(pte)    (!(pte_val(pte) & _PAGE_PRESENT))
-static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
+#define pte_dirty(pte)          (pte_val(pte) & _PAGE_DIRTY)
-static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; }
+#define pte_young(pte)          (pte_val(pte) & _PAGE_ACCESSED)
-static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; }
+#define pte_file(pte)           (pte_val(pte) & _PAGE_FILE)
-static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
-static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_RW; }
+#ifdef CONFIG_X2TLB
-static inline int pte_not_present(pte_t pte){ return !(pte_val(pte) & _PAGE_PRESENT); }
+#define pte_read(pte)           ((pte).pte_high & _PAGE_EXT_USER_READ)
+#define pte_exec(pte)           ((pte).pte_high & _PAGE_EXT_USER_EXEC)
-static inline pte_t pte_rdprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
+#define pte_write(pte)          ((pte).pte_high & _PAGE_EXT_USER_WRITE)
-static inline pte_t pte_exprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
+#else
-static inline pte_t pte_mkclean(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
+#define pte_read(pte)           (pte_val(pte) & _PAGE_USER)
-static inline pte_t pte_mkold(pte_t pte)        { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
+#define pte_exec(pte)           (pte_val(pte) & _PAGE_USER)
-static inline pte_t pte_wrprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; }
+#define pte_write(pte)          (pte_val(pte) & _PAGE_RW)
-static inline pte_t pte_mkread(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
-static inline pte_t pte_mkexec(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
-static inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
-static inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
-static inline pte_t pte_mkwrite(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
-#ifdef CONFIG_HUGETLB_PAGE
-static inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
 #endif
+#define PTE_BIT_FUNC(h,fn,op) \
+static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
+#ifdef CONFIG_X2TLB
+/*
+ * We cheat a bit in the SH-X2 TLB case. As the permission bits are
+ * individually toggled (and user permissions are entirely decoupled from
+ * kernel permissions), we attempt to couple them a bit more sanely here.
+ */
+PTE_BIT_FUNC(high, rdprotect, &= ~_PAGE_EXT_USER_READ);
+PTE_BIT_FUNC(high, mkread, |= _PAGE_EXT_USER_READ | _PAGE_EXT_KERN_READ);
+PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
+PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
+PTE_BIT_FUNC(high, exprotect, &= ~_PAGE_EXT_USER_EXEC);
+PTE_BIT_FUNC(high, mkexec, |= _PAGE_EXT_USER_EXEC | _PAGE_EXT_KERN_EXEC);
+PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
+#else
+PTE_BIT_FUNC(low, rdprotect, &= ~_PAGE_USER);
+PTE_BIT_FUNC(low, mkread, |= _PAGE_USER);
+PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
+PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
+PTE_BIT_FUNC(low, exprotect, &= ~_PAGE_USER);
+PTE_BIT_FUNC(low, mkexec, |= _PAGE_USER);
+PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
+#endif
+PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
+PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
+PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
+PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
 /*
 * Macro and implementation to make a page protection as uncachable.
 */
@@ -258,13 +466,14 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
+{
+        set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) |
-#define pmd_page_vaddr(pmd) \
+                            pgprot_val(newprot)));
-((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+        return pte;
+}
-#define pmd_page(pmd) \
+#define pmd_page_vaddr(pmd)     pmd_val(pmd)
-        (phys_to_page(pmd_val(pmd)))
+#define pmd_page(pmd)           (virt_to_page(pmd_val(pmd)))
 /* to find an entry in a page-table-directory. */
 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
@@ -283,8 +492,15 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pte_unmap(pte)          do { } while (0)
 #define pte_unmap_nested(pte)   do { } while (0)
+#ifdef CONFIG_X2TLB
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
+               &(e), (e).pte_high, (e).pte_low)
+#else
 #define pte_ERROR(e) \
        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#endif
 #define pgd_ERROR(e) \
        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
@@ -337,6 +553,9 @@ extern unsigned int kobjsize(const void *objp);
 extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
 #endif
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern void paging_init(void);
 #include <asm-generic/pgtable.h>
 #endif /* !__ASSEMBLY__ */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 45bb74e35d32..6f1dd7ca1b1d 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -36,7 +36,10 @@
 */
 enum cpu_type {
        /* SH-2 types */
-        CPU_SH7604,
+        CPU_SH7604, CPU_SH7619,
+        /* SH-2A types */
+        CPU_SH7206,
        /* SH-3 types */
        CPU_SH7705, CPU_SH7706, CPU_SH7707,
@@ -47,7 +50,10 @@ enum cpu_type {
        /* SH-4 types */
        CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
        CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
+        /* SH-4A types */
        CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781,
+        CPU_SH7785,
        /* Unknown subtype */
        CPU_SH_NONE
@@ -130,12 +136,11 @@ union sh_fpu_union {
 };
 struct thread_struct {
+        /* Saved registers when thread is descheduled */
        unsigned long sp;
        unsigned long pc;
-        unsigned long trap_no, error_code;
+        /* Hardware debugging registers */
-        unsigned long address;
-        /* Hardware debugging registers may come here */
        unsigned long ubc_pc;
        /* floating point info */
@@ -150,12 +155,7 @@ typedef struct {
 extern int ubc_usercnt;
 #define INIT_THREAD  {                                          \
-        sizeof(init_stack) + (long) &init_stack, /* sp */       \
+        .sp = sizeof(init_stack) + (long) &init_stack,          \
-        0,                                       /* pc */       \
-        0, 0,                                                   \
-        0,                                                      \
-        0,                                                      \
-        {{{0,}},}                               /* fpu state */ \
 }
 /*
@@ -259,8 +259,8 @@ void show_trace(struct task_struct *tsk, unsigned long *sp,
                struct pt_regs *regs);
 extern unsigned long get_wchan(struct task_struct *p);
-#define KSTK_EIP(tsk)  ((tsk)->thread.pc)
+#define KSTK_EIP(tsk)  (task_pt_regs(tsk)->pc)
-#define KSTK_ESP(tsk)  ((tsk)->thread.sp)
+#define KSTK_ESP(tsk)  (task_pt_regs(tsk)->regs[15])
 #define cpu_sleep()     __asm__ __volatile__ ("sleep" : : : "memory")
 #define cpu_relax()     barrier()
diff --git a/include/asm-sh/push-switch.h b/include/asm-sh/push-switch.h
new file mode 100644
index 000000000000..dfc6bad567f0
--- /dev/null
+++ b/include/asm-sh/push-switch.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_SH_PUSH_SWITCH_H
+#define __ASM_SH_PUSH_SWITCH_H
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+struct push_switch {
+        /* switch state */
+        unsigned int            state:1;
+        /* debounce timer */
+        struct timer_list       debounce;
+        /* workqueue */
+        struct work_struct      work;
+};
+struct push_switch_platform_info {
+        /* IRQ handler */
+        irqreturn_t             (*irq_handler)(int irq, void *data);
+        /* Special IRQ flags */
+        unsigned int            irq_flags;
+        /* Bit location of switch */
+        unsigned int            bit;
+        /* Symbolic switch name */
+        const char              *name;
+};
+#endif /* __ASM_SH_PUSH_SWITCH_H */
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
index 9d2aea5e8488..4931ba817d73 100644
--- a/include/asm-sh/rwsem.h
+++ b/include/asm-sh/rwsem.h
@@ -25,11 +25,21 @@ struct rw_semaphore {
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
        spinlock_t              wait_lock;
        struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
 };
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
 #define __RWSEM_INITIALIZER(name) \
        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
-          LIST_HEAD_INIT((name).wait_list) }
+          LIST_HEAD_INIT((name).wait_list) \
+          __RWSEM_DEP_MAP_INIT(name) }
 #define DECLARE_RWSEM(name)             \
        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
@@ -39,6 +49,16 @@ extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
 extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
 extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+#define init_rwsem(sem)                         \
+do {                                            \
+        static struct lock_class_key __key;     \
+                                                \
+        __init_rwsem((sem), #sem, &__key);      \
+} while (0)
 static inline void init_rwsem(struct rw_semaphore *sem)
 {
        sem->count = RWSEM_UNLOCKED_VALUE;
@@ -141,6 +161,11 @@ static inline void __downgrade_write(struct rw_semaphore *sem)
                rwsem_downgrade_wake(sem);
 }
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        __down_write(sem);
+}
 /*
 * implement exchange and add functionality
 */
diff --git a/include/asm-sh/se7206.h b/include/asm-sh/se7206.h
new file mode 100644
index 000000000000..698eb80389ab
--- /dev/null
+++ b/include/asm-sh/se7206.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SH_SE7206_H
+#define __ASM_SH_SE7206_H
+#define PA_SMSC         0x30000000
+#define PA_MRSHPC       0x34000000
+#define PA_LED          0x31400000
+void init_se7206_IRQ(void);
+#define __IO_PREFIX     se7206
+#include <asm/io_generic.h>
+#endif /* __ASM_SH_SE7206_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 3340126f4e0f..b1e42e7f998b 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -6,6 +6,7 @@
 * Copyright (C) 2002 Paul Mundt
 */
+#include <linux/irqflags.h>
 #include <asm/types.h>
 /*
@@ -131,103 +132,6 @@ static inline unsigned long tas(volatile int *m)
 #define set_mb(var, value) do { xchg(&var, value); } while (0)
-/* Interrupt Control */
-#ifdef CONFIG_CPU_HAS_SR_RB
-static inline void local_irq_enable(void)
-{
-        unsigned long __dummy0, __dummy1;
-        __asm__ __volatile__("stc       sr, %0\n\t"
-                             "and       %1, %0\n\t"
-                             "stc       r6_bank, %1\n\t"
-                             "or        %1, %0\n\t"
-                             "ldc       %0, sr"
-                             : "=&r" (__dummy0), "=r" (__dummy1)
-                             : "1" (~0x000000f0)
-                             : "memory");
-}
-#else
-static inline void local_irq_enable(void)
-{
-        unsigned long __dummy0, __dummy1;
-        __asm__ __volatile__ (
-                "stc    sr, %0\n\t"
-                "and    %1, %0\n\t"
-                "ldc    %0, sr\n\t"
-                : "=&r" (__dummy0), "=r" (__dummy1)
-                : "1" (~0x000000f0)
-                : "memory");
-}
-#endif
-static inline void local_irq_disable(void)
-{
-        unsigned long __dummy;
-        __asm__ __volatile__("stc       sr, %0\n\t"
-                             "or        #0xf0, %0\n\t"
-                             "ldc       %0, sr"
-                             : "=&z" (__dummy)
-                             : /* no inputs */
-                             : "memory");
-}
-static inline void set_bl_bit(void)
-{
-        unsigned long __dummy0, __dummy1;
-        __asm__ __volatile__ ("stc      sr, %0\n\t"
-                             "or        %2, %0\n\t"
-                             "and       %3, %0\n\t"
-                             "ldc       %0, sr"
-                             : "=&r" (__dummy0), "=r" (__dummy1)
-                             : "r" (0x10000000), "r" (0xffffff0f)
-                             : "memory");
-}
-static inline void clear_bl_bit(void)
-{
-        unsigned long __dummy0, __dummy1;
-        __asm__ __volatile__ ("stc      sr, %0\n\t"
-                             "and       %2, %0\n\t"
-                             "ldc       %0, sr"
-                             : "=&r" (__dummy0), "=r" (__dummy1)
-                             : "1" (~0x10000000)
-                             : "memory");
-}
-#define local_save_flags(x) \
-        __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
-#define irqs_disabled()                 \
-({                                      \
-        unsigned long flags;            \
-        local_save_flags(flags);        \
-        (flags != 0);                   \
-})
-static inline unsigned long local_irq_save(void)
-{
-        unsigned long flags, __dummy;
-        __asm__ __volatile__("stc       sr, %1\n\t"
-                             "mov       %1, %0\n\t"
-                             "or        #0xf0, %0\n\t"
-                             "ldc       %0, sr\n\t"
-                             "mov       %1, %0\n\t"
-                             "and       #0xf0, %0"
-                             : "=&z" (flags), "=&r" (__dummy)
-                             :/**/
-                             : "memory" );
-        return flags;
-}
-#define local_irq_restore(x) do {                       \
-        if ((x & 0x000000f0) != 0x000000f0)             \
-                local_irq_enable();                     \
-} while (0)
 /*
 * Jump to P2 area.
 * When handling TLB or caches, we need to do it from P2 area.
@@ -264,9 +168,6 @@ do {							\
                : "=&r" (__dummy));                     \
 } while (0)
-/* For spinlocks etc */
-#define local_irq_save(x)       x = local_irq_save()
 static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
 {
        unsigned long flags, retval;
diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h
index 3ebc3f9039eb..0c01dc550819 100644
--- a/include/asm-sh/thread_info.h
+++ b/include/asm-sh/thread_info.h
@@ -90,13 +90,7 @@ static inline struct thread_info *current_thread_info(void)
 #endif
 #define free_thread_info(ti)    kfree(ti)
-#else /* !__ASSEMBLY__ */
+#endif /* __ASSEMBLY__ */
-/* how to get the thread information struct from ASM */
-#define GET_THREAD_INFO(reg) \
-        stc     r7_bank, reg
-#endif
 /*
 * thread information flags
diff --git a/include/asm-sh/timer.h b/include/asm-sh/timer.h
index 5df842bcf7b6..17b5e76a4c31 100644
--- a/include/asm-sh/timer.h
+++ b/include/asm-sh/timer.h
@@ -18,11 +18,32 @@ struct sys_timer {
        struct sys_device       dev;
        struct sys_timer_ops    *ops;
+#ifdef CONFIG_NO_IDLE_HZ
+        struct dyn_tick_timer   *dyn_tick;
+#endif
 };
+#ifdef CONFIG_NO_IDLE_HZ
+#define DYN_TICK_ENABLED        (1 << 1)
+struct dyn_tick_timer {
+        spinlock_t      lock;
+        unsigned int    state;                  /* Current state */
+        int             (*enable)(void);        /* Enables dynamic tick */
+        int             (*disable)(void);       /* Disables dynamic tick */
+        void            (*reprogram)(unsigned long); /* Reprograms the timer */
+        int             (*handler)(int, void *);
+};
+void timer_dyn_reprogram(void);
+#else
+#define timer_dyn_reprogram()   do { } while (0)
+#endif
 #define TICK_SIZE (tick_nsec / 1000)
-extern struct sys_timer tmu_timer;
+extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
 extern struct sys_timer *sys_timer;
 #ifndef CONFIG_GENERIC_TIME
diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h
index 270a4f4bc8a9..03f3583c8918 100644
--- a/include/asm-sh/titan.h
+++ b/include/asm-sh/titan.h
@@ -1,9 +1,8 @@
 /*
 * Platform defintions for Titan
 */
+#ifndef _ASM_SH_TITAN_H
-#ifndef _ASM_SH_TITAN_TITAN_H
+#define _ASM_SH_TITAN_H
-#define _ASM_SH_TITAN_TITAN_H
 #define __IO_PREFIX titan
 #include <asm/io_generic.h>
@@ -15,29 +14,4 @@
 #define TITAN_IRQ_MPCIB         11      /* mPCI B */
 #define TITAN_IRQ_USB           11      /* USB */
-/*
+#endif /* __ASM_SH_TITAN_H */
- * The external interrupt lines, these take up ints 0 - 15 inclusive
- * depending on the priority for the interrupt.  In fact the priority
- * is the interrupt :-)
- */
-#define IRL0_IRQ        0
-#define IRL0_IPR_ADDR   INTC_IPRD
-#define IRL0_IPR_POS    3
-#define IRL0_PRIORITY   8
-#define IRL1_IRQ        1
-#define IRL1_IPR_ADDR   INTC_IPRD
-#define IRL1_IPR_POS    2
-#define IRL1_PRIORITY   8
-#define IRL2_IRQ        2
-#define IRL2_IPR_ADDR   INTC_IPRD
-#define IRL2_IPR_POS    1
-#define IRL2_PRIORITY   8
-#define IRL3_IRQ        3
-#define IRL3_IPR_ADDR   INTC_IPRD
-#define IRL3_IPR_POS    0
-#define IRL3_PRIORITY   8
-#endif
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index 1c2abde122cd..0cae1d248761 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -349,12 +349,30 @@ do { \
        return (type) (res); \
 } while (0)
+#if defined(__sh2__) || defined(__SH2E__) || defined(__SH2A__)
+#define SYSCALL_ARG0    "trapa #0x20"
+#define SYSCALL_ARG1    "trapa #0x21"
+#define SYSCALL_ARG2    "trapa #0x22"
+#define SYSCALL_ARG3    "trapa #0x23"
+#define SYSCALL_ARG4    "trapa #0x24"
+#define SYSCALL_ARG5    "trapa #0x25"
+#define SYSCALL_ARG6    "trapa #0x26"
+#else
+#define SYSCALL_ARG0    "trapa #0x10"
+#define SYSCALL_ARG1    "trapa #0x11"
+#define SYSCALL_ARG2    "trapa #0x12"
+#define SYSCALL_ARG3    "trapa #0x13"
+#define SYSCALL_ARG4    "trapa #0x14"
+#define SYSCALL_ARG5    "trapa #0x15"
+#define SYSCALL_ARG6    "trapa #0x16"
+#endif
 /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
 #define _syscall0(type,name) \
 type name(void) \
 { \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
-__asm__ __volatile__ ("trapa    #0x10" \
+__asm__ __volatile__ (SYSCALL_ARG0 \
        : "=z" (__sc0) \
        : "0" (__sc0) \
        : "memory" ); \
@@ -366,7 +384,7 @@ type name(type1 arg1) \
 { \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
-__asm__ __volatile__ ("trapa    #0x11" \
+__asm__ __volatile__ (SYSCALL_ARG1 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4) \
        : "memory"); \
@@ -379,7 +397,7 @@ type name(type1 arg1,type2 arg2) \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
-__asm__ __volatile__ ("trapa    #0x12" \
+__asm__ __volatile__ (SYSCALL_ARG2 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5) \
        : "memory"); \
@@ -393,7 +411,7 @@ register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
-__asm__ __volatile__ ("trapa    #0x13" \
+__asm__ __volatile__ (SYSCALL_ARG3 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
        : "memory"); \
@@ -408,7 +426,7 @@ register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
-__asm__ __volatile__ ("trapa    #0x14" \
+__asm__ __volatile__ (SYSCALL_ARG4 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6),  \
          "r" (__sc7) \
@@ -425,7 +443,7 @@ register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
 register long __sc0 __asm__ ("r0") = (long) arg5; \
-__asm__ __volatile__ ("trapa    #0x15" \
+__asm__ __volatile__ (SYSCALL_ARG5 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7),  \
          "r" (__sc3) \
@@ -443,7 +461,7 @@ register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
 register long __sc0 __asm__ ("r0") = (long) arg5; \
 register long __sc1 __asm__ ("r1") = (long) arg6; \
-__asm__ __volatile__ ("trapa    #0x16" \
+__asm__ __volatile__ (SYSCALL_ARG6 \
        : "=z" (__sc0) \
        : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7),  \
          "r" (__sc3), "r" (__sc1) \
diff --git a/include/asm-x86_64/atomic.h b/include/asm-x86_64/atomic.h
index 007e88d6d43f..93849f7abc24 100644
--- a/include/asm-x86_64/atomic.h
+++ b/include/asm-x86_64/atomic.h
@@ -21,7 +21,7 @@
 * on us. We need to use _exactly_ the address the user gave us,
 * not some alias that contains the same information.
 */
-typedef struct { volatile int counter; } atomic_t;
+typedef struct { int counter; } atomic_t;
 #define ATOMIC_INIT(i)  { (i) }
diff --git a/include/asm-x86_64/spinlock_types.h b/include/asm-x86_64/spinlock_types.h
index 59efe849f351..4da9345c1500 100644
--- a/include/asm-x86_64/spinlock_types.h
+++ b/include/asm-x86_64/spinlock_types.h
@@ -6,13 +6,13 @@
 #endif
 typedef struct {
-        volatile unsigned int slock;
+        unsigned int slock;
 } raw_spinlock_t;
 #define __RAW_SPIN_LOCK_UNLOCKED        { 1 }
 typedef struct {
-        volatile unsigned int lock;
+        unsigned int lock;
 } raw_rwlock_t;
 #define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
diff --git a/include/linux/aio.h b/include/linux/aio.h
index 0d71c0041f13..9e350fd44d77 100644
--- a/include/linux/aio.h
+++ b/include/linux/aio.h
@@ -194,7 +194,7 @@ struct kioctx {
        struct aio_ring_info    ring_info;
-        struct work_struct      wq;
+        struct delayed_work     wq;
 };
 /* prototypes */
diff --git a/include/linux/connector.h b/include/linux/connector.h
index 4c02119c6ab9..3ea1cd58de97 100644
--- a/include/linux/connector.h
+++ b/include/linux/connector.h
@@ -133,7 +133,7 @@ struct cn_callback_data {
 struct cn_callback_entry {
        struct list_head callback_entry;
        struct cn_callback *cb;
-        struct work_struct work;
+        struct delayed_work work;
        struct cn_queue_dev *pdev;
        struct cn_callback_id id;
@@ -170,7 +170,7 @@ void cn_queue_free_dev(struct cn_queue_dev *dev);
 int cn_cb_equal(struct cb_id *, struct cb_id *);
-void cn_queue_wrapper(void *data);
+void cn_queue_wrapper(struct work_struct *work);
 extern int cn_already_initialized;
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index c115e9e840b4..1fb02e17f6f6 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -461,7 +461,7 @@ struct i2o_driver {
        int (*reply) (struct i2o_controller *, u32, struct i2o_message *);
        /* Event handler */
-        void (*event) (struct i2o_event *);
+        work_func_t event;
        struct workqueue_struct *event_queue;   /* Event queue */
diff --git a/include/linux/kbd_kern.h b/include/linux/kbd_kern.h
index efe0ee4cc80b..06c58c423fe1 100644
--- a/include/linux/kbd_kern.h
+++ b/include/linux/kbd_kern.h
@@ -158,7 +158,7 @@ static inline void con_schedule_flip(struct tty_struct *t)
        if (t->buf.tail != NULL)
                t->buf.tail->commit = t->buf.tail->used;
        spin_unlock_irqrestore(&t->buf.lock, flags);
-        schedule_work(&t->buf.work);
+        schedule_delayed_work(&t->buf.work, 0);
 }
 #endif
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 202283b5df96..ab2754830322 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -575,8 +575,9 @@ struct ata_port {
        struct ata_host         *host;
        struct device           *dev;
-        struct work_struct      port_task;
+        void                    *port_task_data;
-        struct work_struct      hotplug_task;
+        struct delayed_work     port_task;
+        struct delayed_work     hotplug_task;
        struct work_struct      scsi_rescan_task;
        unsigned int            hsm_task_state;
@@ -755,7 +756,7 @@ extern void ata_host_resume(struct ata_host *host);
 extern int ata_ratelimit(void);
 extern int ata_busy_sleep(struct ata_port *ap,
                          unsigned long timeout_pat, unsigned long timeout);
-extern void ata_port_queue_task(struct ata_port *ap, void (*fn)(void *),
+extern void ata_port_queue_task(struct ata_port *ap, work_func_t fn,
                                void *data, unsigned long delay);
 extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
                             unsigned long interval_msec,
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 528e7d3fecb1..c15ae1986b98 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -110,7 +110,7 @@ struct mmc_host {
        struct mmc_card         *card_busy;     /* the MMC card claiming host */
        struct mmc_card         *card_selected; /* the selected MMC card */
-        struct work_struct      detect;
+        struct delayed_work     detect;
        unsigned long           private[0] ____cacheline_aligned;
 };
diff --git a/include/linux/ncp_fs_sb.h b/include/linux/ncp_fs_sb.h
index b089d9506283..a503052138bd 100644
--- a/include/linux/ncp_fs_sb.h
+++ b/include/linux/ncp_fs_sb.h
@@ -127,10 +127,10 @@ struct ncp_server {
        } unexpected_packet;
 };
-extern void ncp_tcp_rcv_proc(void *server);
+extern void ncp_tcp_rcv_proc(struct work_struct *work);
-extern void ncp_tcp_tx_proc(void *server);
+extern void ncp_tcp_tx_proc(struct work_struct *work);
-extern void ncpdgram_rcv_proc(void *server);
+extern void ncpdgram_rcv_proc(struct work_struct *work);
-extern void ncpdgram_timeout_proc(void *server);
+extern void ncpdgram_timeout_proc(struct work_struct *work);
 extern void ncpdgram_timeout_call(unsigned long server);
 extern void ncp_tcp_data_ready(struct sock* sk, int len);
 extern void ncp_tcp_write_space(struct sock* sk);
diff --git a/include/linux/netpoll.h b/include/linux/netpoll.h
index 2cc9867b1626..29930b71a9aa 100644
--- a/include/linux/netpoll.h
+++ b/include/linux/netpoll.h
@@ -32,7 +32,7 @@ struct netpoll_info {
        struct netpoll *rx_np; /* netpoll that registered an rx_hook */
        struct sk_buff_head arp_tx; /* list of arp requests to reply to */
        struct sk_buff_head txq;
-        struct work_struct tx_work;
+        struct delayed_work tx_work;
 };
 void netpoll_poll(struct netpoll *np);
diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h
index 7ccfc7ef0a83..95796e6924f1 100644
--- a/include/linux/nfs_fs_sb.h
+++ b/include/linux/nfs_fs_sb.h
@@ -51,7 +51,7 @@ struct nfs_client {
        unsigned long           cl_lease_time;
        unsigned long           cl_last_renewal;
-        struct work_struct      cl_renewd;
+        struct delayed_work     cl_renewd;
        struct rpc_wait_queue   cl_rpcwaitq;
diff --git a/include/linux/reiserfs_fs_sb.h b/include/linux/reiserfs_fs_sb.h
index 62a7169aed8b..3a28742d86f9 100644
--- a/include/linux/reiserfs_fs_sb.h
+++ b/include/linux/reiserfs_fs_sb.h
@@ -249,7 +249,8 @@ struct reiserfs_journal {
        int j_errno;
        /* when flushing ordered buffers, throttle new ordered writers */
-        struct work_struct j_work;
+        struct delayed_work j_work;
+        struct super_block *j_work_sb;
        atomic_t j_async_throttle;
 };
diff --git a/include/linux/relay.h b/include/linux/relay.h
index 24accb483849..0e3d91b76996 100644
--- a/include/linux/relay.h
+++ b/include/linux/relay.h
@@ -38,7 +38,7 @@ struct rchan_buf
        size_t subbufs_consumed;        /* count of sub-buffers consumed */
        struct rchan *chan;             /* associated channel */
        wait_queue_head_t read_wait;    /* reader wait queue */
-        struct work_struct wake_readers; /* reader wake-up work struct */
+        struct delayed_work wake_readers; /* reader wake-up work struct */
        struct dentry *dentry;          /* channel file dentry */
        struct kref kref;               /* channel buffer refcount */
        struct page **page_array;       /* array of current buffer pages */
diff --git a/include/linux/sunrpc/rpc_pipe_fs.h b/include/linux/sunrpc/rpc_pipe_fs.h
index a2eb9b4a9de3..4a68125b6de6 100644
--- a/include/linux/sunrpc/rpc_pipe_fs.h
+++ b/include/linux/sunrpc/rpc_pipe_fs.h
@@ -30,7 +30,7 @@ struct rpc_inode {
 #define RPC_PIPE_WAIT_FOR_OPEN  1
        int flags;
        struct rpc_pipe_ops *ops;
-        struct work_struct queue_timeout;
+        struct delayed_work queue_timeout;
 };
 static inline struct rpc_inode *
diff --git a/include/linux/tty.h b/include/linux/tty.h
index 65321f911c1e..f717f0898238 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -53,7 +53,7 @@ struct tty_buffer {
 };
 struct tty_bufhead {
-        struct work_struct              work;
+        struct delayed_work work;
        struct semaphore pty_sem;
        spinlock_t lock;
        struct tty_buffer *head;        /* Queue head */
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 0cd73edeef13..aab5b1b72021 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -388,7 +388,7 @@ struct usb_device {
        int pm_usage_cnt;               /* usage counter for autosuspend */
 #ifdef CONFIG_PM
-        struct work_struct autosuspend; /* for delayed autosuspends */
+        struct delayed_work autosuspend; /* for delayed autosuspends */
        struct mutex pm_mutex;          /* protects PM operations */
        unsigned auto_pm:1;             /* autosuspend/resume in progress */
diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index 9bca3539a1e5..4a3ea83c6d16 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -11,12 +11,23 @@
 struct workqueue_struct;
+struct work_struct;
+typedef void (*work_func_t)(struct work_struct *work);
 struct work_struct {
-        unsigned long pending;
+        /* the first word is the work queue pointer and the flags rolled into
+         * one */
+        unsigned long management;
+#define WORK_STRUCT_PENDING 0           /* T if work item pending execution */
+#define WORK_STRUCT_NOAUTOREL 1         /* F if work item automatically released on exec */
+#define WORK_STRUCT_FLAG_MASK (3UL)
+#define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK)
        struct list_head entry;
-        void (*func)(void *);
+        work_func_t func;
-        void *data;
+};
-        void *wq_data;
+struct delayed_work {
+        struct work_struct work;
        struct timer_list timer;
 };
@@ -24,36 +35,117 @@ struct execute_work {
        struct work_struct work;
 };
-#define __WORK_INITIALIZER(n, f, d) {                           \
+#define __WORK_INITIALIZER(n, f) {                              \
+        .management = 0,                                        \
+        .entry  = { &(n).entry, &(n).entry },                   \
+        .func = (f),                                            \
+        }
+#define __WORK_INITIALIZER_NAR(n, f) {                          \
+        .management = (1 << WORK_STRUCT_NOAUTOREL),             \
        .entry  = { &(n).entry, &(n).entry },                   \
        .func = (f),                                            \
-        .data = (d),                                            \
+        }
+#define __DELAYED_WORK_INITIALIZER(n, f) {                      \
+        .work = __WORK_INITIALIZER((n).work, (f)),              \
+        .timer = TIMER_INITIALIZER(NULL, 0, 0),                 \
+        }
+#define __DELAYED_WORK_INITIALIZER_NAR(n, f) {                  \
+        .work = __WORK_INITIALIZER_NAR((n).work, (f)),          \
        .timer = TIMER_INITIALIZER(NULL, 0, 0),                 \
        }
-#define DECLARE_WORK(n, f, d)                                   \
+#define DECLARE_WORK(n, f)                                      \
-        struct work_struct n = __WORK_INITIALIZER(n, f, d)
+        struct work_struct n = __WORK_INITIALIZER(n, f)
+#define DECLARE_WORK_NAR(n, f)                                  \
+        struct work_struct n = __WORK_INITIALIZER_NAR(n, f)
+#define DECLARE_DELAYED_WORK(n, f)                              \
+        struct delayed_work n = __DELAYED_WORK_INITIALIZER(n, f)
+#define DECLARE_DELAYED_WORK_NAR(n, f)                  \
+        struct dwork_struct n = __DELAYED_WORK_INITIALIZER_NAR(n, f)
 /*
- * initialize a work-struct's func and data pointers:
+ * initialize a work item's function pointer
 */
-#define PREPARE_WORK(_work, _func, _data)                       \
+#define PREPARE_WORK(_work, _func)                              \
        do {                                                    \
-                (_work)->func = _func;                          \
+                (_work)->func = (_func);                        \
-                (_work)->data = _data;                          \
        } while (0)
+#define PREPARE_DELAYED_WORK(_work, _func)                      \
+        PREPARE_WORK(&(_work)->work, (_func))
 /*
- * initialize all of a work-struct:
+ * initialize all of a work item in one go
 */
-#define INIT_WORK(_work, _func, _data)                          \
+#define INIT_WORK(_work, _func)                                 \
        do {                                                    \
+                (_work)->management = 0;                        \
                INIT_LIST_HEAD(&(_work)->entry);                \
-                (_work)->pending = 0;                           \
+                PREPARE_WORK((_work), (_func));                 \
-                PREPARE_WORK((_work), (_func), (_data));        \
+        } while (0)
+#define INIT_WORK_NAR(_work, _func)                                     \
+        do {                                                            \
+                (_work)->management = (1 << WORK_STRUCT_NOAUTOREL);     \
+                INIT_LIST_HEAD(&(_work)->entry);                        \
+                PREPARE_WORK((_work), (_func));                         \
+        } while (0)
+#define INIT_DELAYED_WORK(_work, _func)                         \
+        do {                                                    \
+                INIT_WORK(&(_work)->work, (_func));             \
+                init_timer(&(_work)->timer);                    \
+        } while (0)
+#define INIT_DELAYED_WORK_NAR(_work, _func)                     \
+        do {                                                    \
+                INIT_WORK_NAR(&(_work)->work, (_func));         \
                init_timer(&(_work)->timer);                    \
        } while (0)
+/**
+ * work_pending - Find out whether a work item is currently pending
+ * @work: The work item in question
+ */
+#define work_pending(work) \
+        test_bit(WORK_STRUCT_PENDING, &(work)->management)
+/**
+ * delayed_work_pending - Find out whether a delayable work item is currently
+ * pending
+ * @work: The work item in question
+ */
+#define delayed_work_pending(work) \
+        test_bit(WORK_STRUCT_PENDING, &(work)->work.management)
+/**
+ * work_release - Release a work item under execution
+ * @work: The work item to release
+ *
+ * This is used to release a work item that has been initialised with automatic
+ * release mode disabled (WORK_STRUCT_NOAUTOREL is set).  This gives the work
+ * function the opportunity to grab auxiliary data from the container of the
+ * work_struct before clearing the pending bit as the work_struct may be
+ * subject to deallocation the moment the pending bit is cleared.
+ *
+ * In such a case, this should be called in the work function after it has
+ * fetched any data it may require from the containter of the work_struct.
+ * After this function has been called, the work_struct may be scheduled for
+ * further execution or it may be deallocated unless other precautions are
+ * taken.
+ *
+ * This should also be used to release a delayed work item.
+ */
+#define work_release(work) \
+        clear_bit(WORK_STRUCT_PENDING, &(work)->management)
 extern struct workqueue_struct *__create_workqueue(const char *name,
                                                    int singlethread);
 #define create_workqueue(name) __create_workqueue((name), 0)
@@ -62,39 +154,38 @@ extern struct workqueue_struct *__create_workqueue(const char *name,
 extern void destroy_workqueue(struct workqueue_struct *wq);
 extern int FASTCALL(queue_work(struct workqueue_struct *wq, struct work_struct *work));
-extern int FASTCALL(queue_delayed_work(struct workqueue_struct *wq, struct work_struct *work, unsigned long delay));
+extern int FASTCALL(queue_delayed_work(struct workqueue_struct *wq, struct delayed_work *work, unsigned long delay));
 extern int queue_delayed_work_on(int cpu, struct workqueue_struct *wq,
-        struct work_struct *work, unsigned long delay);
+        struct delayed_work *work, unsigned long delay);
 extern void FASTCALL(flush_workqueue(struct workqueue_struct *wq));
 extern int FASTCALL(schedule_work(struct work_struct *work));
-extern int FASTCALL(schedule_delayed_work(struct work_struct *work, unsigned long delay));
+extern int FASTCALL(schedule_delayed_work(struct delayed_work *work, unsigned long delay));
-extern int schedule_delayed_work_on(int cpu, struct work_struct *work, unsigned long delay);
+extern int schedule_delayed_work_on(int cpu, struct delayed_work *work, unsigned long delay);
-extern int schedule_on_each_cpu(void (*func)(void *info), void *info);
+extern int schedule_on_each_cpu(work_func_t func);
 extern void flush_scheduled_work(void);
 extern int current_is_keventd(void);
 extern int keventd_up(void);
 extern void init_workqueues(void);
-void cancel_rearming_delayed_work(struct work_struct *work);
+void cancel_rearming_delayed_work(struct delayed_work *work);
 void cancel_rearming_delayed_workqueue(struct workqueue_struct *,
-                                       struct work_struct *);
+                                       struct delayed_work *);
-int execute_in_process_context(void (*fn)(void *), void *,
+int execute_in_process_context(work_func_t fn, struct execute_work *);
-                               struct execute_work *);
 /*
 * Kill off a pending schedule_delayed_work().  Note that the work callback
 * function may still be running on return from cancel_delayed_work().  Run
 * flush_scheduled_work() to wait on it.
 */
-static inline int cancel_delayed_work(struct work_struct *work)
+static inline int cancel_delayed_work(struct delayed_work *work)
 {
        int ret;
        ret = del_timer_sync(&work->timer);
        if (ret)
-                clear_bit(0, &work->pending);
+                clear_bit(WORK_STRUCT_PENDING, &work->work.management);
        return ret;
 }
diff --git a/include/net/ieee80211softmac.h b/include/net/ieee80211softmac.h
index 617b672b1132..89119277553d 100644
--- a/include/net/ieee80211softmac.h
+++ b/include/net/ieee80211softmac.h
@@ -108,8 +108,8 @@ struct ieee80211softmac_assoc_info {
        /* Scan retries remaining */
        int scan_retry;
-        struct work_struct work;
+        struct delayed_work work;
-        struct work_struct timeout;
+        struct delayed_work timeout;
 };
 struct ieee80211softmac_bss_info {
diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h
index 5f48748fe017..f7be1ac73601 100644
--- a/include/net/inet_timewait_sock.h
+++ b/include/net/inet_timewait_sock.h
@@ -84,7 +84,7 @@ struct inet_timewait_death_row {
 };
 extern void inet_twdr_hangman(unsigned long data);
-extern void inet_twdr_twkill_work(void *data);
+extern void inet_twdr_twkill_work(struct work_struct *work);
 extern void inet_twdr_twcal_tick(unsigned long data);
 #if (BITS_PER_LONG == 64)
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index f8cbe40f52c0..c089f93ba591 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -1030,7 +1030,7 @@ void sctp_inq_init(struct sctp_inq *);
 void sctp_inq_free(struct sctp_inq *);
 void sctp_inq_push(struct sctp_inq *, struct sctp_chunk *packet);
 struct sctp_chunk *sctp_inq_pop(struct sctp_inq *);
-void sctp_inq_set_th_handler(struct sctp_inq *, void (*)(void *), void *);
+void sctp_inq_set_th_handler(struct sctp_inq *, work_func_t);
 /* This is the structure we use to hold outbound chunks.  You push
 * chunks in and they automatically pop out the other end as bundled
diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h
index 44b2f82a6eec..9233ed5de664 100644
--- a/include/scsi/libsas.h
+++ b/include/scsi/libsas.h
@@ -201,9 +201,14 @@ struct domain_device {
        void *lldd_dev;
 };
+struct sas_discovery_event {
+        struct work_struct work;
+        struct asd_sas_port *port;
+};
 struct sas_discovery {
        spinlock_t disc_event_lock;
-        struct work_struct disc_work[DISC_NUM_EVENTS];
+        struct sas_discovery_event disc_work[DISC_NUM_EVENTS];
        unsigned long    pending;
        u8     fanout_sas_addr[8];
        u8     eeds_a[8];
@@ -249,14 +254,19 @@ struct asd_sas_port {
        void *lldd_port;          /* not touched by the sas class code */
 };
+struct asd_sas_event {
+        struct work_struct work;
+        struct asd_sas_phy *phy;
+};
 /* The phy pretty much is controlled by the LLDD.
 * The class only reads those fields.
 */
 struct asd_sas_phy {
 /* private: */
        /* protected by ha->event_lock */
-        struct work_struct   port_events[PORT_NUM_EVENTS];
+        struct asd_sas_event   port_events[PORT_NUM_EVENTS];
-        struct work_struct   phy_events[PHY_NUM_EVENTS];
+        struct asd_sas_event   phy_events[PHY_NUM_EVENTS];
        unsigned long port_events_pending;
        unsigned long phy_events_pending;
@@ -308,10 +318,15 @@ struct scsi_core {
        int               queue_thread_kill;
 };
+struct sas_ha_event {
+        struct work_struct work;
+        struct sas_ha_struct *ha;
+};
 struct sas_ha_struct {
 /* private: */
        spinlock_t       event_lock;
-        struct work_struct ha_events[HA_NUM_EVENTS];
+        struct sas_ha_event ha_events[HA_NUM_EVENTS];
        unsigned long    pending;
        struct scsi_core core;
@@ -631,6 +646,6 @@ void sas_unregister_dev(struct domain_device *);
 void sas_init_dev(struct domain_device *);
-void sas_task_abort(struct sas_task *task);
+void sas_task_abort(struct work_struct *);
 #endif /* _SASLIB_H_ */
diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h
index fd352323378b..798f7c7ee426 100644
--- a/include/scsi/scsi_transport_fc.h
+++ b/include/scsi/scsi_transport_fc.h
@@ -206,9 +206,9 @@ struct fc_rport {	/* aka fc_starget_attrs */
        u8 flags;
        struct list_head peers;
        struct device dev;
-        struct work_struct dev_loss_work;
+        struct delayed_work dev_loss_work;
        struct work_struct scan_work;
-        struct work_struct fail_io_work;
+        struct delayed_work fail_io_work;
        struct work_struct stgt_delete_work;
        struct work_struct rport_delete_work;
 } __attribute__((aligned(sizeof(unsigned long))));
diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h
index 4b95c89c95c9..d5c218ddc527 100644
--- a/include/scsi/scsi_transport_iscsi.h
+++ b/include/scsi/scsi_transport_iscsi.h
@@ -176,7 +176,7 @@ struct iscsi_cls_session {
        /* recovery fields */
        int recovery_tmo;
-        struct work_struct recovery_work;
+        struct delayed_work recovery_work;
        int target_id;
diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h
index 4c43521cc493..33720397a904 100644
--- a/include/sound/ac97_codec.h
+++ b/include/sound/ac97_codec.h
@@ -511,7 +511,7 @@ struct snd_ac97 {
 #ifdef CONFIG_SND_AC97_POWER_SAVE
        unsigned int power_up;  /* power states */
        struct workqueue_struct *power_workq;
-        struct work_struct power_work;
+        struct delayed_work power_work;
 #endif
        struct device dev;
 };
diff --git a/include/sound/ak4114.h b/include/sound/ak4114.h
index 11702aa0bea9..2ee061625fd0 100644
--- a/include/sound/ak4114.h
+++ b/include/sound/ak4114.h
@@ -182,7 +182,7 @@ struct ak4114 {
        unsigned char rcs0;
        unsigned char rcs1;
        struct workqueue_struct *workqueue;
-        struct work_struct work;
+        struct delayed_work work;
        void *change_callback_private;
        void (*change_callback)(struct ak4114 *ak4114, unsigned char c0, unsigned char c1);
 };