605 files changed, 17944 insertions, 11702 deletions
diff --git a/include/asm-alpha/barrier.h b/include/asm-alpha/barrier.h
index 229c83fe77cb..681ff581afa5 100644
--- a/include/asm-alpha/barrier.h
+++ b/include/asm-alpha/barrier.h
@@ -1,6 +1,8 @@
 #ifndef __BARRIER_H
 #define __BARRIER_H
+#include <asm/compiler.h>
 #define mb() \
 __asm__ __volatile__("mb": : :"memory")
diff --git a/include/asm-alpha/rwsem.h b/include/asm-alpha/rwsem.h
index 8e058a67c9a4..fafdd4f7010a 100644
--- a/include/asm-alpha/rwsem.h
+++ b/include/asm-alpha/rwsem.h
@@ -262,5 +262,10 @@ static inline long rwsem_atomic_update(long val, struct rw_semaphore *sem)
 #endif
 }
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
 #endif /* __KERNEL__ */
 #endif /* _ALPHA_RWSEM_H */
diff --git a/include/asm-alpha/semaphore.h b/include/asm-alpha/semaphore.h
index eb2cbd97d404..1a6295f2c2d4 100644
--- a/include/asm-alpha/semaphore.h
+++ b/include/asm-alpha/semaphore.h
@@ -26,9 +26,6 @@ struct semaphore {
        .wait   = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
 }
-#define __MUTEX_INITIALIZER(name)                       \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count)         \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 79c90813bc3e..d8209f8911d6 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -13,7 +13,7 @@
 #include <linux/config.h>
-#define PHYS_OFFSET     (0xf0000000UL)
+#define PHYS_OFFSET     UL(0xf0000000)
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
diff --git a/include/asm-arm/arch-cl7500/memory.h b/include/asm-arm/arch-cl7500/memory.h
index 9776bba8e585..34f40a6cec30 100644
--- a/include/asm-arm/arch-cl7500/memory.h
+++ b/include/asm-arm/arch-cl7500/memory.h
@@ -17,7 +17,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x10000000UL)
+#define PHYS_OFFSET     UL(0x10000000)
 /*
 * These are exactly the same on the RiscPC as the
diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h
index f864c367c934..1386871e1a5a 100644
--- a/include/asm-arm/arch-clps711x/hardware.h
+++ b/include/asm-arm/arch-clps711x/hardware.h
@@ -235,121 +235,4 @@
 #define CEIVA_PB0_BLK_BTN       (1<<0)
 #endif // #if defined (CONFIG_ARCH_CEIVA)
-#if defined (CONFIG_MACH_MP1000)
-/* NOR FLASH */
-#define MP1000_NIO_BASE         0xf9000000      /* virtual */
-#define MP1000_NIO_START        CS0_PHYS_BASE   /* physical */
-#define MP1000_NIO_SIZE         0x00400000
-/* DSP Interface */
-#define MP1000_DSP_BASE         0xfa000000      /* virtual */
-#define MP1000_DSP_START        CS1_PHYS_BASE   /* physical */
-#define MP1000_DSP_SIZE         0x00100000
-/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
-#define MP1000_LIO_BASE         0xfb000000      /* virtual */
-#define MP1000_LIO_START        CS2_PHYS_BASE   /* physical */
-#define MP1000_LIO_SIZE         0x00100000
-/* NAND FLASH */
-#define MP1000_FIO_BASE         0xfc000000      /* virtual */
-#define MP1000_FIO_START        CS3_PHYS_BASE   /* physical */
-#define MP1000_FIO_SIZE         0x00800000
-/* Ethernet */
-#define MP1000_EIO_BASE         0xfd000000      /* virtual      */
-#define MP1000_EIO_START        CS4_PHYS_BASE   /* physical     */
-#define MP1000_EIO_SIZE         0x00100000
-#define MP1000_LCD_OFFSET       0x00000000      /* LCD offset in CS2 */
-#define MP1000_DDD_OFFSET       0x00001000      /* DAA/DAI/DSP sft reset offst*/
-#define MP1000_RTC_OFFSET       0x00002000      /* RTC offset in CS2 */
-#define MP1000_DAA_OFFSET       0x00003000      /* DAA RW reg offset in CS2 */
-/* IDE */
-#define MP1000_IDE_BASE         0xfe000000      /* virtual */
-#define MP1000_IDE_START        CS5_PHYS_BASE      /* physical */
-#define MP1000_IDE_SIZE         0x00100000      /* actually it's only 0x1000 */
-#define IRQ_HARDDISK IRQ_EINT2
-/*
- * IDE registers definition
- */
-#define IDE_CONTROL_BASE                (MP1000_IDE_BASE + 0x1000)
-#define IDE_BASE_OFF                    (MP1000_IDE_BASE)
-#define IDE_WRITE_DEVICE_DATA           (IDE_BASE_OFF + 0x0)
-#define IDE_FEATURES_REGISTER           (IDE_BASE_OFF + 0x2)
-#define IDE_SECTOR_COUNT_REGISTER       (IDE_BASE_OFF + 0x4)
-#define IDE_SECTOR_NUMBER_REGISTER      (IDE_BASE_OFF + 0x6)
-#define IDE_CYLINDER_LOW_REGISTER       (IDE_BASE_OFF + 0x8)
-#define IDE_CYLINDER_HIGH_REGISTER      (IDE_BASE_OFF + 0xa)
-#define IDE_DEVICE_HEAD_REGISTER        (IDE_BASE_OFF + 0xc)
-#define IDE_COMMAND_DATA_REGISTER       (IDE_BASE_OFF + 0xe)
-#define IDE_DEVICE_CONTROL_REGISTER     (IDE_CONTROL_BASE + 0xc)
-#define IDE_IRQ                      IRQ_EINT2
-#define RTC_PORT(x)     (MP1000_LIO_BASE+0x2000 + (x*2))
-#define RTC_ALWAYS_BCD  0
-/*
-// Definitions of the bit fields in the HwPortA register for the
-// MP1000 board.
-*/
-#define HwPortAKeyboardRow1                     0x00000001
-#define HwPortAKeyboardRow2                     0x00000002
-#define HwPortAKeyboardRow3                     0x00000004
-#define HwPortAKeyboardRow4                     0x00000008
-#define HwPortAKeyboardRow5                     0x00000010
-#define HwPortAKeyboardRow6                     0x00000020
-#define HwPortALCDEnable                        0x00000040
-#define HwPortAOffhook                          0x00000080
-/*
-// Definitions of the bit fields in the HwPortB register for the
-// MP1000 board.
-*/
-#define HwPortBL3Mode                           0x00000001
-#define HwPortBL3Clk                            0x00000002
-#define HwPortBSClk                             0x00000001
-#define HwPortBSData                            0x00000002
-#define HwPortBL3Data                           0x00000004
-#define HwPortBMute                             0x00000008
-#define HwPortBQD0                              0x00000010
-#define HwPortBQD1                              0x00000020
-#define HwPortBQD2                              0x00000040
-#define HwPortBQD3                              0x00000080
-/*
-// Definitions of the bit fields in the HwPortD register for the
-// MP1000 board.
-*/
-#define HwPortDLED1                             0x00000001
-#define HwPortDLED2                             0x00000002
-#define HwPortDLED3                             0x00000004
-#define HwPortDLED4                             0x00000008
-#define HwPortDLED5                             0x00000010
-#define HwPortDEECS                             0x00000020
-#define HwPortBRTS                              0x00000040
-#define HwPortBRI                               0x00000080
-/*
-// Definitions of the bit fields in the HwPortE register for the
-// MP1000 board.
-*/
-#define HwPortECLE                              0x00000001
-#define HwPortESepromDOut                       0x00000001
-#define HwPortEALE                              0x00000002
-#define HwPortESepromDIn                        0x00000002
-#define HwPortENANDCS                           0x00000004
-#define HwPortESepromCLK                        0x00000004
-#endif // #if defined (CONFIG_MACH_MP1000)
 #endif
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index bd978947db42..61d8717406ce 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -25,7 +25,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-clps711x/mp1000-seprom.h b/include/asm-arm/arch-clps711x/mp1000-seprom.h
deleted file mode 100644
index 3e5566cf9666..000000000000
--- a/include/asm-arm/arch-clps711x/mp1000-seprom.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef MP1000_SEPROM_H
-#define MP1000_SEPROM_H
-/*
- * mp1000-seprom.h
- *
- *
- *  This file contains the Serial EEPROM definitions for the MP1000 board
- *
- *  Copyright (C) 2005 Comdial Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#define COMMAND_ERASE           (0x1C0)
-#define COMMAND_ERASE_ALL       (0x120)
-#define COMMAND_WRITE_DISABLE   (0x100)
-#define COMMAND_WRITE_ENABLE    (0x130)
-#define COMMAND_READ            (0x180)
-#define COMMAND_WRITE           (0x140)
-#define COMMAND_WRITE_ALL       (0x110)
-//
-// Serial EEPROM data format
-//
-#define PACKED __attribute__ ((packed))
-typedef struct _EEPROM {
-        union {
-                unsigned char eprom_byte_data[128];
-                unsigned short eprom_short_data[64];
-                struct {
-                        unsigned char version PACKED;   // EEPROM Version "1" for now
-                        unsigned char box_id PACKED;    // Box ID (Standalone, SOHO, embedded, etc)
-                        unsigned char major_hw_version PACKED;  // Major Hardware version (Hex)
-                        unsigned char minor_hw_version PACKED;  // Minor Hardware Version (Hex)
-                        unsigned char mfg_id[3] PACKED; // Manufacturer ID (3 character Alphabetic)
-                        unsigned char mfg_serial_number[10] PACKED;     // Manufacturer Serial number
-                        unsigned char mfg_date[3] PACKED;       // Date of Mfg (Formatted YY:MM:DD)
-                        unsigned char country PACKED;   // Country of deployment
-                        unsigned char mac_Address[6] PACKED;    // MAC Address
-                        unsigned char oem_string[20] PACKED;    // OEM ID string
-                        unsigned short feature_bits1 PACKED;    // Feature Bits 1
-                        unsigned short feature_bits2 PACKED;    // Feature Bits 2
-                        unsigned char filler[75] PACKED;                // Unused/Undefined     �0� initialized
-                        unsigned short checksum PACKED;         // byte accumulated short checksum
-                } eprom_struct;
-        } variant;
-}  eeprom_struct;
-/* These settings must be mutually exclusive */
-#define FEATURE_BITS1_DRAMSIZE_16MEG    0x0001  /* 0 signifies 4 MEG system */
-#define FEATURE_BITS1_DRAMSIZE_8MEG     0x0002  /* 1 in bit 1 = 8MEG system */
-#define FEATURE_BITS1_DRAMSIZE_64MEG    0x0004  /* 1 in bit 2 = 64MEG system */
-#define FEATURE_BITS1_CPUIS90MEG     0x0010
-extern void seprom_init(void);
-extern eeprom_struct* get_seprom_ptr(void);
-extern unsigned char* get_eeprom_mac_address(void);
-#endif /* MP1000_SEPROM_H */
diff --git a/include/asm-arm/arch-ebsa110/memory.h b/include/asm-arm/arch-ebsa110/memory.h
index 5a9493e12275..02f144520c10 100644
--- a/include/asm-arm/arch-ebsa110/memory.h
+++ b/include/asm-arm/arch-ebsa110/memory.h
@@ -19,7 +19,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * We keep this 1:1 so that we don't interfere
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index d0466f9987d3..09e335cd687d 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -46,14 +46,14 @@ extern unsigned long __bus_to_virt(unsigned long);
 #if defined(CONFIG_ARCH_FOOTBRIDGE)
 /* Task size and page offset at 3GB */
-#define TASK_SIZE               (0xbf000000UL)
+#define TASK_SIZE               UL(0xbf000000)
-#define PAGE_OFFSET             (0xc0000000UL)
+#define PAGE_OFFSET             UL(0xc0000000)
 #elif defined(CONFIG_ARCH_CO285)
 /* Task size and page offset at 1.5GB */
-#define TASK_SIZE               (0x5f000000UL)
+#define TASK_SIZE               UL(0x5f000000)
-#define PAGE_OFFSET             (0x60000000UL)
+#define PAGE_OFFSET             UL(0x60000000)
 #else
@@ -64,7 +64,7 @@ extern unsigned long __bus_to_virt(unsigned long);
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET             (0x00000000UL)
+#define PHYS_OFFSET             UL(0x00000000)
 /*
 * This decides where the kernel will search for a free chunk of vm
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h
index 3f86bf7f67f0..999541b6a9f5 100644
--- a/include/asm-arm/arch-epxa10db/memory.h
+++ b/include/asm-arm/arch-epxa10db/memory.h
@@ -23,7 +23,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-h720x/memory.h b/include/asm-arm/arch-h720x/memory.h
index 5633447af268..4a1bfd78a0fe 100644
--- a/include/asm-arm/arch-h720x/memory.h
+++ b/include/asm-arm/arch-h720x/memory.h
@@ -11,7 +11,7 @@
 * Page offset:
 *    ( 0xc0000000UL )
 */
-#define PHYS_OFFSET     (0x40000000UL)
+#define PHYS_OFFSET     UL(0x40000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h
index 116a91fa14f1..d09ae32cd2f4 100644
--- a/include/asm-arm/arch-imx/memory.h
+++ b/include/asm-arm/arch-imx/memory.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_MMU_H
 #define __ASM_ARCH_MMU_H
-#define PHYS_OFFSET     (0x08000000UL)
+#define PHYS_OFFSET     UL(0x08000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-integrator/memory.h b/include/asm-arm/arch-integrator/memory.h
index 2087ea7d28a9..1ab56d783e7c 100644
--- a/include/asm-arm/arch-integrator/memory.h
+++ b/include/asm-arm/arch-integrator/memory.h
@@ -23,8 +23,8 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
-#define BUS_OFFSET      (0x80000000UL)
+#define BUS_OFFSET      UL(0x80000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h
index 200621ff3690..f8df778a356f 100644
--- a/include/asm-arm/arch-iop3xx/iop321.h
+++ b/include/asm-arm/arch-iop3xx/iop321.h
@@ -40,7 +40,7 @@
 #define IOP321_PCI_UPPER_IO_BA      (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
 #define IOP321_PCI_IO_OFFSET        (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
-//#define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1)
+/* #define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1) */
 #define IOP321_PCI_MEM_WINDOW_SIZE  0x04000000 /* 64M outbound window */
 #define IOP321_PCI_LOWER_MEM_PA     0x80000000
 #define IOP321_PCI_LOWER_MEM_BA     (*IOP321_OMWTVR0)
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
index 45351f5cd904..bc62f4b13235 100644
--- a/include/asm-arm/arch-iop3xx/memory.h
+++ b/include/asm-arm/arch-iop3xx/memory.h
@@ -12,9 +12,9 @@
 * Physical DRAM offset.
 */
 #ifndef CONFIG_ARCH_IOP331
-#define PHYS_OFFSET     (0xa0000000UL)
+#define PHYS_OFFSET     UL(0xa0000000)
 #else
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 #endif
 /*
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
index 31ae88674968..95128d9f5026 100644
--- a/include/asm-arm/arch-ixp2000/enp2611.h
+++ b/include/asm-arm/arch-ixp2000/enp2611.h
@@ -21,8 +21,20 @@
 #ifndef __ENP2611_H
 #define __ENP2611_H
-#define ENP2611_GPIO_SCL        0x07
+#define ENP2611_CALEB_PHYS_BASE         0xc5000000
-#define ENP2611_GPIO_SDA        0x06
+#define ENP2611_CALEB_VIRT_BASE         0xfe000000
+#define ENP2611_CALEB_SIZE              0x00100000
+#define ENP2611_PM3386_0_PHYS_BASE      0xc6000000
+#define ENP2611_PM3386_0_VIRT_BASE      0xfe100000
+#define ENP2611_PM3386_0_SIZE           0x00100000
+#define ENP2611_PM3386_1_PHYS_BASE      0xc6400000
+#define ENP2611_PM3386_1_VIRT_BASE      0xfe200000
+#define ENP2611_PM3386_1_SIZE           0x00100000
+#define ENP2611_GPIO_SCL                7
+#define ENP2611_GPIO_SDA                6
 #endif
diff --git a/include/asm-arm/arch-ixp2000/irqs.h b/include/asm-arm/arch-ixp2000/irqs.h
index 0deb96c12adb..62f09c7ff420 100644
--- a/include/asm-arm/arch-ixp2000/irqs.h
+++ b/include/asm-arm/arch-ixp2000/irqs.h
@@ -67,12 +67,45 @@
 #define IRQ_IXP2000_PCIA                40
 #define IRQ_IXP2000_PCIB                41
-#define NR_IXP2000_IRQS                 42
+/* Int sources from IRQ_ERROR_STATUS */
+#define IRQ_IXP2000_DRAM0_MIN_ERR       42
+#define IRQ_IXP2000_DRAM0_MAJ_ERR       43
+#define IRQ_IXP2000_DRAM1_MIN_ERR       44
+#define IRQ_IXP2000_DRAM1_MAJ_ERR       45
+#define IRQ_IXP2000_DRAM2_MIN_ERR       46
+#define IRQ_IXP2000_DRAM2_MAJ_ERR       47
+/* 48-57 reserved */
+#define IRQ_IXP2000_SRAM0_ERR           58
+#define IRQ_IXP2000_SRAM1_ERR           59
+#define IRQ_IXP2000_SRAM2_ERR           60
+#define IRQ_IXP2000_SRAM3_ERR           61
+/* 62-65 reserved */
+#define IRQ_IXP2000_MEDIA_ERR           66
+#define IRQ_IXP2000_PCI_ERR                     67
+#define IRQ_IXP2000_SP_INT                      68
+#define NR_IXP2000_IRQS                         69
 #define IXP2000_BOARD_IRQ(x)            (NR_IXP2000_IRQS + (x))
 #define IXP2000_BOARD_IRQ_MASK(irq)     (1 << (irq - NR_IXP2000_IRQS))  
+#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
+#define IXP2000_VALID_ERR_IRQ_MASK (\
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT)        )
 /*
 * This allows for all the on-chip sources plus up to 32 CPLD based
 * IRQs. Should be more than enough.
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
index b768009c3a51..c6d51426e98f 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -22,7 +22,7 @@
 #define IXDP2X01_CPLD_REGION_SIZE       0x00100000
 #define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
-#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
+#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
 #define IXDP2X01_UART1_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x40)
 #define IXDP2X01_UART1_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x40)
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index def089d693d2..fc5ac6aec4f2 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -59,14 +59,15 @@
 #define IXP2000_CAP_SIZE                0x00100000
 /*
- * Addresses for specific on-chip peripherals
+ * Addresses for specific on-chip peripherals.
 */
 #define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
 #define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
 #define IXP2000_UART_PHYS_BASE          0xc0030000
 #define IXP2000_UART_VIRT_BASE          0xfef30000
 #define IXP2000_TIMER_VIRT_BASE         0xfef20000
-#define IXP2000_GPIO_VIRT_BASE          0Xfef10000
+#define IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
+#define IXP2000_GPIO_VIRT_BASE          0xfef10000
 /*
 * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
@@ -252,7 +253,7 @@
 #define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
 #define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
-#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Centrolfunction bit */
+#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Central function bit */
 #define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
 /* These are from the IRQ register in the PCI ISR register */
diff --git a/include/asm-arm/arch-ixp2000/memory.h b/include/asm-arm/arch-ixp2000/memory.h
index d0f415c6dae9..21e1de51e3f6 100644
--- a/include/asm-arm/arch-ixp2000/memory.h
+++ b/include/asm-arm/arch-ixp2000/memory.h
@@ -13,7 +13,7 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index abdcf51bd283..a66317ab2071 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -15,40 +15,40 @@
 #ifndef __ASSEMBLY__
+static inline unsigned long ixp2000_reg_read(volatile void *reg)
+{
+        return *((volatile unsigned long *)reg);
+}
+static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
 /*
- * The IXP2400 B0 silicon contains an erratum (#66) that causes writes
+ * On the IXP2400, we can't use XCB=000 due to chip bugs.  We use
- * to on-chip I/O register to not complete fully. What this means is
+ * XCB=101 instead, but that makes all I/O accesses bufferable.  This
- * that if you have a write to on-chip I/O followed by a back-to-back
+ * is not a problem in general, but we do have to be slightly more
- * read or write, the first write will happen twice. OR...if it's
+ * careful because I/O writes are no longer automatically flushed out
- * not a back-to-back transaction, the read or write will generate
+ * of the write buffer.
- * incorrect data.
- *
- * The official work around for this is to set the on-chip I/O regions
- * as XCB=101 and then force a read-back from the register.
 *
+ * In cases where we want to make sure that a write has been flushed
+ * out of the write buffer before we proceed, for example when masking
+ * a device interrupt before re-enabling IRQs in CPSR, we can use this
+ * function, ixp2000_reg_wrb, which performs a write, a readback, and
+ * issues a dummy instruction dependent on the value of the readback
+ * (mov rX, rX) to make sure that the readback has completed before we
+ * continue.
 */
-#if defined(CONFIG_ARCH_ENP2611) || defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
+static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
-#include <asm/system.h>         /* Pickup local_irq_ functions */
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
 {
        unsigned long dummy;
-        unsigned long flags;
-        local_irq_save(flags);
        *((volatile unsigned long *)reg) = val;
-        barrier();
        dummy = *((volatile unsigned long *)reg);
-        local_irq_restore(flags);
+        __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
-}
-#else
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
 }
-#endif  /* IXDP2400 || IXDP2401 */
-#define ixp2000_reg_read(reg)   (*((volatile unsigned long *)reg))
 /*
 * Boards may multiplex different devices on the 2nd channel of 
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
index 4f489cc0dfa5..ddbbb34b5f95 100644
--- a/include/asm-arm/arch-ixp2000/system.h
+++ b/include/asm-arm/arch-ixp2000/system.h
@@ -26,29 +26,24 @@ static inline void arch_reset(char mode)
         * RedBoot bank.
         */
        if (machine_is_ixdp2401()) {
-                *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
+                ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
-                                                | IXDP2X01_CPLD_FLASH_INTERN);
+                                        ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
-                *IXDP2X01_CPLD_RESET_REG = 0xffffffff;
+                                                | IXDP2X01_CPLD_FLASH_INTERN));
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
        }
        /*
         * On IXDP2801 we need to write this magic sequence to the CPLD
         * to cause a complete reset of the CPU and all external devices
-         * and moves the flash bank register back to 0.
+         * and move the flash bank register back to 0.
         */
        if (machine_is_ixdp2801()) {
                unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
                reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
-                *IXDP2X01_CPLD_RESET_REG = reset_reg;
+                ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
-                mb();
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
-                *IXDP2X01_CPLD_RESET_REG = 0x80000000;
        }
-        /*
+        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
-         * We do a reset all if we are PCI master. We could be a slave and we
-         * don't want to do anything funky on the PCI bus.
-         */
-        if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
-                *(IXP2000_RESET0) |= (RSTALL);
-        }
 }
diff --git a/include/asm-arm/arch-ixp2000/uengine.h b/include/asm-arm/arch-ixp2000/uengine.h
new file mode 100644
index 000000000000..b442d65c6593
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/uengine.h
@@ -0,0 +1,62 @@
+/*
+ * Generic library functions for the microengines found on the Intel
+ * IXP2000 series of network processors.
+ *
+ * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Dedicated to Marija Kulikova.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as
+ * published by the Free Software Foundation; either version 2.1 of the
+ * License, or (at your option) any later version.
+ */
+#ifndef __IXP2000_UENGINE_H
+#define __IXP2000_UENGINE_H
+extern u32 ixp2000_uengine_mask;
+struct ixp2000_uengine_code
+{
+        u32     cpu_model_bitmask;
+        u8      cpu_min_revision;
+        u8      cpu_max_revision;
+        u32     uengine_parameters;
+        struct ixp2000_reg_value {
+                int     reg;
+                u32     value;
+        } *initial_reg_values;
+        int     num_insns;
+        u8      *insns;
+};
+u32 ixp2000_uengine_csr_read(int uengine, int offset);
+void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
+void ixp2000_uengine_reset(u32 uengine_mask);
+void ixp2000_uengine_set_mode(int uengine, u32 mode);
+void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
+void ixp2000_uengine_init_context(int uengine, int context, int pc);
+void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
+void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
+int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
+#define IXP2000_UENGINE_8_CONTEXTS              0x00000000
+#define IXP2000_UENGINE_4_CONTEXTS              0x80000000
+#define IXP2000_UENGINE_PRN_UPDATE_EVERY        0x40000000
+#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS    0x00000000
+#define IXP2000_UENGINE_NN_FROM_SELF            0x00100000
+#define IXP2000_UENGINE_NN_FROM_PREVIOUS        0x00000000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3       0x000c0000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2       0x00080000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1       0x00040000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0       0x00000000
+#define IXP2000_UENGINE_LM_ADDR1_GLOBAL         0x00020000
+#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT    0x00000000
+#define IXP2000_UENGINE_LM_ADDR0_GLOBAL         0x00010000
+#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT    0x00000000
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index e350dcb544e8..688f7f90d93e 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -80,9 +80,9 @@ __ixp4xx_iounmap(void __iomem *addr)
 #define __arch_ioremap(a, s, f, x)      __ixp4xx_ioremap(a, s, f, x)
 #define __arch_iounmap(a)               __ixp4xx_iounmap(a)
-#define writeb(p, v)                    __ixp4xx_writeb(p, v)
+#define writeb(v, p)                    __ixp4xx_writeb(v, p)
-#define writew(p, v)                    __ixp4xx_writew(p, v)
+#define writew(v, p)                    __ixp4xx_writew(v, p)
-#define writel(p, v)                    __ixp4xx_writel(p, v)
+#define writel(v, p)                    __ixp4xx_writel(v, p)
 #define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
 #define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
@@ -97,8 +97,9 @@ __ixp4xx_iounmap(void __iomem *addr)
 #define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
 static inline void 
-__ixp4xx_writeb(u8 value, u32 addr)
+__ixp4xx_writeb(u8 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START) {
@@ -113,15 +114,16 @@ __ixp4xx_writeb(u8 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
+__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
 {
        while (count--)
                writeb(*vaddr++, bus_addr);
 }
 static inline void 
-__ixp4xx_writew(u16 value, u32 addr)
+__ixp4xx_writew(u16 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START) {
@@ -136,15 +138,16 @@ __ixp4xx_writew(u16 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
+__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
 {
        while (count--)
                writew(*vaddr++, bus_addr);
 }
 static inline void 
-__ixp4xx_writel(u32 value, u32 addr)
+__ixp4xx_writel(u32 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        if (addr >= VMALLOC_START) {
                __raw_writel(value, addr);
                return;
@@ -154,15 +157,16 @@ __ixp4xx_writel(u32 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
+__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
 {
        while (count--)
                writel(*vaddr++, bus_addr);
 }
 static inline unsigned char 
-__ixp4xx_readb(u32 addr)
+__ixp4xx_readb(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START)
@@ -177,15 +181,16 @@ __ixp4xx_readb(u32 addr)
 }
 static inline void
-__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count)
+__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readb(bus_addr);
 }
 static inline unsigned short 
-__ixp4xx_readw(u32 addr)
+__ixp4xx_readw(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START)
@@ -200,15 +205,16 @@ __ixp4xx_readw(u32 addr)
 }
 static inline void 
-__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count)
+__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readw(bus_addr);
 }
 static inline unsigned long 
-__ixp4xx_readl(u32 addr)
+__ixp4xx_readl(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 data;
        if (addr >= VMALLOC_START)
@@ -221,7 +227,7 @@ __ixp4xx_readl(u32 addr)
 }
 static inline void 
-__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
+__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readl(bus_addr);
@@ -239,7 +245,7 @@ __ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
                                eth_copy_and_sum((s),__mem_pci(c),(l),(b))
 static inline int
-check_signature(unsigned long bus_addr, const unsigned char *signature,
+check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature,
                int length)
 {
        int retval = 0;
@@ -389,7 +395,7 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
 #define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
                                        ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
 static inline unsigned int
-__ixp4xx_ioread8(void __iomem *addr)
+__ixp4xx_ioread8(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -398,12 +404,12 @@ __ixp4xx_ioread8(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return (unsigned int)__raw_readb(port);
 #else
-                return (unsigned int)__ixp4xx_readb(port);
+                return (unsigned int)__ixp4xx_readb(addr);
 #endif
 }
 static inline void
-__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -412,12 +418,12 @@ __ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsb(addr, vaddr, count);
 #else
-                __ixp4xx_readsb(port, vaddr, count);
+                __ixp4xx_readsb(addr, vaddr, count);
 #endif
 }
 static inline unsigned int
-__ixp4xx_ioread16(void __iomem *addr)
+__ixp4xx_ioread16(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -426,12 +432,12 @@ __ixp4xx_ioread16(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return le16_to_cpu(__raw_readw((u32)port));
 #else
-                return (unsigned int)__ixp4xx_readw((u32)port);
+                return (unsigned int)__ixp4xx_readw(addr);
 #endif
 }
 static inline void
-__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -440,12 +446,12 @@ __ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsw(addr, vaddr, count);
 #else
-                __ixp4xx_readsw(port, vaddr, count);
+                __ixp4xx_readsw(addr, vaddr, count);
 #endif
 }
 static inline unsigned int
-__ixp4xx_ioread32(void __iomem *addr)
+__ixp4xx_ioread32(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -454,13 +460,13 @@ __ixp4xx_ioread32(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return le32_to_cpu(__raw_readl((u32)port));
 #else
-                return (unsigned int)__ixp4xx_readl((u32)port);
+                return (unsigned int)__ixp4xx_readl(addr);
 #endif
        }
 }
 static inline void
-__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -469,7 +475,7 @@ __ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsl(addr, vaddr, count);
 #else
-                __ixp4xx_readsl(port, vaddr, count);
+                __ixp4xx_readsl(addr, vaddr, count);
 #endif
 }
@@ -483,7 +489,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writeb(value, port);
 #else
-                __ixp4xx_writeb(value, port);
+                __ixp4xx_writeb(value, addr);
 #endif
 }
@@ -497,7 +503,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesb(addr, vaddr, count);
 #else
-                __ixp4xx_writesb(port, vaddr, count);
+                __ixp4xx_writesb(addr, vaddr, count);
 #endif
 }
@@ -511,7 +517,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writew(cpu_to_le16(value), addr);
 #else
-                __ixp4xx_writew(value, port);
+                __ixp4xx_writew(value, addr);
 #endif
 }
@@ -525,7 +531,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesw(addr, vaddr, count);
 #else
-                __ixp4xx_writesw(port, vaddr, count);
+                __ixp4xx_writesw(addr, vaddr, count);
 #endif
 }
@@ -539,7 +545,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writel(cpu_to_le32(value), port);
 #else
-                __ixp4xx_writel(value, port);
+                __ixp4xx_writel(value, addr);
 #endif
 }
@@ -553,7 +559,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesl(addr, vaddr, count);
 #else
-                __ixp4xx_writesl(port, vaddr, count);
+                __ixp4xx_writesl(addr, vaddr, count);
 #endif
 }
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 004696a95bdb..2b149ed59149 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -36,11 +36,11 @@
 *
 * 0x6000000    0x00004000      ioremap'd       QMgr
 *
- * 0xC0000000   0x00001000      0xffbfe000      PCI CFG 
+ * 0xC0000000   0x00001000      0xffbff000      PCI CFG
 *
- * 0xC4000000   0x00001000      0xffbfd000      EXP CFG 
+ * 0xC4000000   0x00001000      0xffbfe000      EXP CFG
 *
- * 0xC8000000   0x0000C000      0xffbf2000      On-Chip Peripherals
+ * 0xC8000000   0x00013000      0xffbeb000      On-Chip Peripherals
 */
 /*
@@ -52,22 +52,22 @@
 * Expansion BUS Configuration registers
 */
 #define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFD000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
 /*
 * PCI Config registers
 */
 #define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
-#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
 /*
 * Peripheral space
 */
 #define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBF2000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
-#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x0000C000)
+#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
 /*
 * Debug UART
@@ -115,25 +115,48 @@
 /*
 * Peripheral Space Register Region Base Addresses
 */
-#define IXP4XX_UART1_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP4XX_UART1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP4XX_UART2_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP4XX_UART2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP4XX_PMU_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP4XX_PMU_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP4XX_INTC_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP4XX_INTC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP4XX_GPIO_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP4XX_GPIO_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP4XX_TIMER_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP4XX_TIMER_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP4XX_EthA_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP4XX_NPEA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP4XX_EthB_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP4XX_NPEB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP4XX_USB_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
+#define IXP4XX_NPEC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP4XX_UART1_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_EthC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP4XX_UART2_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_USB_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
-#define IXP4XX_PMU_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+/* ixp46X only */
-#define IXP4XX_INTC_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_EthA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
-#define IXP4XX_GPIO_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_EthB1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
-#define IXP4XX_TIMER_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_EthB2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
-#define IXP4XX_EthA_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthB3_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
-#define IXP4XX_EthB_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_TIMESYNC_BASE_PHYS       (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
-#define IXP4XX_USB_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+#define IXP4XX_I2C_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
+#define IXP4XX_SSP_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
+#define IXP4XX_UART1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_UART2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_PMU_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+#define IXP4XX_INTC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_GPIO_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_TIMER_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_NPEA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP4XX_NPEB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP4XX_NPEC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_USB_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+/* ixp46X only */
+#define IXP4XX_EthA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
+#define IXP4XX_EthB1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
+#define IXP4XX_EthB2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
+#define IXP4XX_EthB3_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
+#define IXP4XX_TIMESYNC_BASE_VIRT       (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
+#define IXP4XX_I2C_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
+#define IXP4XX_SSP_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
 /*
 * Constants to make it easy to access  Interrupt Controller registers
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h
index d348548b592b..e024d0a1a669 100644
--- a/include/asm-arm/arch-ixp4xx/memory.h
+++ b/include/asm-arm/arch-ixp4xx/memory.h
@@ -12,7 +12,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-l7200/memory.h b/include/asm-arm/arch-l7200/memory.h
index c5b9608cb137..9e50a171f78a 100644
--- a/include/asm-arm/arch-l7200/memory.h
+++ b/include/asm-arm/arch-l7200/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset on the L7200 SDB.
 */
-#define PHYS_OFFSET     (0xf0000000UL)
+#define PHYS_OFFSET     UL(0xf0000000)
 #define __virt_to_bus(x) __virt_to_phys(x)
 #define __bus_to_virt(x) __phys_to_virt(x)
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index c650e6feb9d5..c92bcb837629 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -17,7 +17,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index ef32d61eec7a..bf545b6e0a26 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -37,9 +37,9 @@
 * Physical DRAM offset.
 */
 #if defined(CONFIG_ARCH_OMAP1)
-#define PHYS_OFFSET             (0x10000000UL)
+#define PHYS_OFFSET             UL(0x10000000)
 #elif defined(CONFIG_ARCH_OMAP2)
-#define PHYS_OFFSET             (0x80000000UL)
+#define PHYS_OFFSET             UL(0x80000000)
 #endif
 /*
@@ -66,7 +66,7 @@
 /*
 * OMAP-1510 Local Bus address offset
 */
-#define OMAP1510_LB_OFFSET      (0x30000000UL)
+#define OMAP1510_LB_OFFSET      UL(0x30000000)
 #define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index 58bad9748b5c..eaf6d43939e9 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xa0000000UL)
+#define PHYS_OFFSET     UL(0xa0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S
new file mode 100644
index 000000000000..ed28bd012236
--- /dev/null
+++ b/include/asm-arm/arch-realview/debug-macro.S
@@ -0,0 +1,38 @@
+/* linux/include/asm-arm/arch-realview/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <asm/hardware/amba_serial.h>
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx,      #0x10000000
+                movne   \rx,      #0xf1000000   @ virtual base
+                orr     \rx, \rx, #0x00009000
+                .endm
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #UART01x_DR]
+                .endm
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/include/asm-ppc64/pmc.h b/include/asm-arm/arch-realview/dma.h
index d1d297dbccfe..744491a74bd9 100644
--- a/include/asm-ppc64/pmc.h
+++ b/include/asm-arm/arch-realview/dma.h
@@ -1,6 +1,8 @@
 /*
- * pmc.h
+ *  linux/include/asm-arm/arch-realview/dma.h
- * Copyright (C) 2004  David Gibson, IBM Corporation
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *  Copyright (C) 1997,1998 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -14,18 +16,12 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef _PPC64_PMC_H
+#ifndef __ASM_ARCH_DMA_H
-#define _PPC64_PMC_H
+#define __ASM_ARCH_DMA_H
-#include <asm/ptrace.h>
-typedef void (*perf_irq_t)(struct pt_regs *);
-int reserve_pmc_hardware(perf_irq_t new_perf_irq);
-void release_pmc_hardware(void);
-void power4_enable_pmcs(void);
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        0
-#endif /* _PPC64_PMC_H */
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
new file mode 100644
index 000000000000..2712ba77bb3a
--- /dev/null
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-realview/entry-macro.S
+ *
+ * Low-level IRQ helper macros for RealView platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware/gic.h>
+                .macro  disable_fiq
+                .endm
+                /*
+                 * The interrupt numbering scheme is defined in the
+                 * interrupt controller spec.  To wit:
+                 *
+                 * Interrupts 0-15 are IPI
+                 * 16-28 are reserved
+                 * 29-31 are local.  We allow 30 to be used for the watchdog.
+                 * 32-1020 are global
+                 * 1021-1022 are reserved
+                 * 1023 is "spurious" (no interrupt)
+                 *
+                 * For now, we ignore all local interrupts so only return an interrupt if it's
+                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+                 *
+                 * A simple read from the controller will tell us the number of the highest
+                 * priority enabled interrupt.  We then just need to check whether it is in the
+                 * valid range for an IRQ (30-1020 inclusive).
+                 */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
+                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
+                ldr     \tmp, =1021
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+                .endm
diff --git a/include/asm-ppc64/iSeries/ItSpCommArea.h b/include/asm-arm/arch-realview/hardware.h
index 5535f8271c9f..67879cdb6ef2 100644
--- a/include/asm-ppc64/iSeries/ItSpCommArea.h
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -1,6 +1,9 @@
 /*
- * ItSpCommArea.h
+ *  linux/include/asm-arm/arch-realview/hardware.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ *  This file contains the hardware definitions of the RealView boards.
+ *
+ *  Copyright (C) 2003 ARM Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -14,24 +17,15 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
-#ifndef _ITSPCOMMAREA_H
+#include <asm/sizes.h>
-#define _ITSPCOMMAREA_H
+#include <asm/arch/platform.h>
-struct SpCommArea {
-        u32     xDesc;                  // Descriptor (only in new formats)     000-003
-        u8      xFormat;                // Format (only in new formats)         004-004
-        u8      xRsvd1[11];             // Reserved                             005-00F
-        u64     xRawTbAtIplStart;       // Raw HW TB value when IPL is started  010-017
-        u64     xRawTodAtIplStart;      // Raw HW TOD value when IPL is started 018-01F
-        u64     xBcdTimeAtIplStart;     // BCD time when IPL is started         020-027
-        u64     xBcdTimeAtOsStart;      // BCD time when OS passed control      028-02F
-        u8      xRsvd2[80];             // Reserved                             030-07F
-};
-extern struct SpCommArea xSpCommArea;
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
-#endif /* _ITSPCOMMAREA_H */
+#endif
diff --git a/include/asm-ppc64/iSeries/HvCallSm.h b/include/asm-arm/arch-realview/io.h
index 8a3dbb071a43..d444a68ac330 100644
--- a/include/asm-ppc64/iSeries/HvCallSm.h
+++ b/include/asm-arm/arch-realview/io.h
@@ -1,6 +1,7 @@
 /*
- * HvCallSm.h
+ *  linux/include/asm-arm/arch-realview/io.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ *  Copyright (C) 2003 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -14,25 +15,20 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef _HVCALLSM_H
-#define _HVCALLSM_H
-/*
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from the OS.
 */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
-#include <asm/iSeries/HvCallSc.h>
+#define IO_SPACE_LIMIT 0xffffffff
-#include <asm/iSeries/HvTypes.h>
-#define HvCallSmGet64BitsOfAccessMap    HvCallSm  + 11
-static inline u64 HvCallSm_get64BitsOfAccessMap(HvLpIndex lpIndex,
+static inline void __iomem *__io(unsigned long addr)
-                u64 indexIntoBitMap)
 {
-        return HvCall2(HvCallSmGet64BitsOfAccessMap, lpIndex, indexIntoBitMap);
+        return (void __iomem *)addr;
 }
-#endif /* _HVCALLSM_H */
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
new file mode 100644
index 000000000000..ff376494e5b1
--- /dev/null
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -0,0 +1,103 @@
+/*
+ *  linux/include/asm-arm/arch-realview/irqs.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/arch/platform.h>
+/* 
+ *  IRQ interrupts definitions are the same the INT definitions
+ *  held within platform.h
+ */
+#define IRQ_GIC_START           32
+#define IRQ_WDOGINT             (IRQ_GIC_START + INT_WDOGINT)
+#define IRQ_SOFTINT             (IRQ_GIC_START + INT_SOFTINT)
+#define IRQ_COMMRx              (IRQ_GIC_START + INT_COMMRx)
+#define IRQ_COMMTx              (IRQ_GIC_START + INT_COMMTx)
+#define IRQ_TIMERINT0_1         (IRQ_GIC_START + INT_TIMERINT0_1)
+#define IRQ_TIMERINT2_3         (IRQ_GIC_START + INT_TIMERINT2_3)
+#define IRQ_GPIOINT0            (IRQ_GIC_START + INT_GPIOINT0)
+#define IRQ_GPIOINT1            (IRQ_GIC_START + INT_GPIOINT1)
+#define IRQ_GPIOINT2            (IRQ_GIC_START + INT_GPIOINT2)
+#define IRQ_GPIOINT3            (IRQ_GIC_START + INT_GPIOINT3)
+#define IRQ_RTCINT              (IRQ_GIC_START + INT_RTCINT)
+#define IRQ_SSPINT              (IRQ_GIC_START + INT_SSPINT)
+#define IRQ_UARTINT0            (IRQ_GIC_START + INT_UARTINT0)
+#define IRQ_UARTINT1            (IRQ_GIC_START + INT_UARTINT1)
+#define IRQ_UARTINT2            (IRQ_GIC_START + INT_UARTINT2)
+#define IRQ_UART3               (IRQ_GIC_START + INT_UARTINT3)
+#define IRQ_SCIINT              (IRQ_GIC_START + INT_SCIINT)
+#define IRQ_CLCDINT             (IRQ_GIC_START + INT_CLCDINT)
+#define IRQ_DMAINT              (IRQ_GIC_START + INT_DMAINT)
+#define IRQ_PWRFAILINT          (IRQ_GIC_START + INT_PWRFAILINT)
+#define IRQ_MBXINT              (IRQ_GIC_START + INT_MBXINT)
+#define IRQ_GNDINT              (IRQ_GIC_START + INT_GNDINT)
+#define IRQ_MMCI0B              (IRQ_GIC_START + INT_MMCI0B)
+#define IRQ_MMCI1B              (IRQ_GIC_START + INT_MMCI1B)
+#define IRQ_KMI0                (IRQ_GIC_START + INT_KMI0)
+#define IRQ_KMI1                (IRQ_GIC_START + INT_KMI1)
+#define IRQ_SCI3                (IRQ_GIC_START + INT_SCI3)
+#define IRQ_CLCD                (IRQ_GIC_START + INT_CLCD)
+#define IRQ_TOUCH               (IRQ_GIC_START + INT_TOUCH)
+#define IRQ_KEYPAD              (IRQ_GIC_START + INT_KEYPAD)
+#define IRQ_DoC                 (IRQ_GIC_START + INT_DoC)
+#define IRQ_MMCI0A              (IRQ_GIC_START + INT_MMCI0A)
+#define IRQ_MMCI1A              (IRQ_GIC_START + INT_MMCI1A)
+#define IRQ_AACI                (IRQ_GIC_START + INT_AACI)
+#define IRQ_ETH                 (IRQ_GIC_START + INT_ETH)
+#define IRQ_USB                 (IRQ_GIC_START + INT_USB)
+#define IRQMASK_WDOGINT         INTMASK_WDOGINT
+#define IRQMASK_SOFTINT         INTMASK_SOFTINT
+#define IRQMASK_COMMRx          INTMASK_COMMRx
+#define IRQMASK_COMMTx          INTMASK_COMMTx
+#define IRQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
+#define IRQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
+#define IRQMASK_GPIOINT0        INTMASK_GPIOINT0
+#define IRQMASK_GPIOINT1        INTMASK_GPIOINT1
+#define IRQMASK_GPIOINT2        INTMASK_GPIOINT2
+#define IRQMASK_GPIOINT3        INTMASK_GPIOINT3
+#define IRQMASK_RTCINT          INTMASK_RTCINT
+#define IRQMASK_SSPINT          INTMASK_SSPINT
+#define IRQMASK_UARTINT0        INTMASK_UARTINT0
+#define IRQMASK_UARTINT1        INTMASK_UARTINT1
+#define IRQMASK_UARTINT2        INTMASK_UARTINT2
+#define IRQMASK_SCIINT          INTMASK_SCIINT
+#define IRQMASK_CLCDINT         INTMASK_CLCDINT
+#define IRQMASK_DMAINT          INTMASK_DMAINT
+#define IRQMASK_PWRFAILINT      INTMASK_PWRFAILINT
+#define IRQMASK_MBXINT          INTMASK_MBXINT
+#define IRQMASK_GNDINT          INTMASK_GNDINT
+#define IRQMASK_MMCI0B          INTMASK_MMCI0B
+#define IRQMASK_MMCI1B          INTMASK_MMCI1B
+#define IRQMASK_KMI0            INTMASK_KMI0
+#define IRQMASK_KMI1            INTMASK_KMI1
+#define IRQMASK_SCI3            INTMASK_SCI3
+#define IRQMASK_UART3           INTMASK_UART3
+#define IRQMASK_CLCD            INTMASK_CLCD
+#define IRQMASK_TOUCH           INTMASK_TOUCH
+#define IRQMASK_KEYPAD          INTMASK_KEYPAD
+#define IRQMASK_DoC             INTMASK_DoC
+#define IRQMASK_MMCI0A          INTMASK_MMCI0A
+#define IRQMASK_MMCI1A          INTMASK_MMCI1A
+#define IRQMASK_AACI            INTMASK_AACI
+#define IRQMASK_ETH             INTMASK_ETH
+#define IRQMASK_USB             INTMASK_USB
+#define NR_IRQS                 (IRQ_GIC_START + 64)
diff --git a/include/asm-arm/arch-realview/memory.h b/include/asm-arm/arch-realview/memory.h
new file mode 100644
index 000000000000..ed370abb638f
--- /dev/null
+++ b/include/asm-arm/arch-realview/memory.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/arch-realview/memory.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x00000000)
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
+#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+#endif
diff --git a/include/asm-arm/arch-realview/param.h b/include/asm-arm/arch-realview/param.h
new file mode 100644
index 000000000000..89b1235d32bd
--- /dev/null
+++ b/include/asm-arm/arch-realview/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-realview/param.h
+ *
+ *  Copyright (C) 2002 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
new file mode 100644
index 000000000000..4b6de13a6b9a
--- /dev/null
+++ b/include/asm-arm/arch-realview/platform.h
@@ -0,0 +1,395 @@
+/*
+ * linux/include/asm-arm/arch-realview/platform.h
+ *
+ * Copyright (c) ARM Limited 2003.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __address_h
+#define __address_h                     1
+/*
+ * Memory definitions
+ */
+#define REALVIEW_BOOT_ROM_LO          0x30000000                /* DoC Base (64Mb)...*/
+#define REALVIEW_BOOT_ROM_HI          0x30000000
+#define REALVIEW_BOOT_ROM_BASE        REALVIEW_BOOT_ROM_HI       /*  Normal position */
+#define REALVIEW_BOOT_ROM_SIZE        SZ_64M
+#define REALVIEW_SSRAM_BASE           /* REALVIEW_SSMC_BASE ? */
+#define REALVIEW_SSRAM_SIZE           SZ_2M
+#define REALVIEW_FLASH_BASE           0x40000000
+#define REALVIEW_FLASH_SIZE           SZ_64M
+/* 
+ *  SDRAM
+ */
+#define REALVIEW_SDRAM_BASE           0x00000000
+/* 
+ *  Logic expansion modules
+ * 
+ */
+/* ------------------------------------------------------------------------
+ *  RealView Registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define REALVIEW_SYS_ID_OFFSET               0x00
+#define REALVIEW_SYS_SW_OFFSET               0x04
+#define REALVIEW_SYS_LED_OFFSET              0x08
+#define REALVIEW_SYS_OSC0_OFFSET             0x0C
+#define REALVIEW_SYS_OSC1_OFFSET             0x10
+#define REALVIEW_SYS_OSC2_OFFSET             0x14
+#define REALVIEW_SYS_OSC3_OFFSET             0x18
+#define REALVIEW_SYS_OSC4_OFFSET             0x1C       /* OSC1 for RealView/AB */
+#define REALVIEW_SYS_LOCK_OFFSET             0x20
+#define REALVIEW_SYS_100HZ_OFFSET            0x24
+#define REALVIEW_SYS_CFGDATA1_OFFSET         0x28
+#define REALVIEW_SYS_CFGDATA2_OFFSET         0x2C
+#define REALVIEW_SYS_FLAGS_OFFSET            0x30
+#define REALVIEW_SYS_FLAGSSET_OFFSET         0x30
+#define REALVIEW_SYS_FLAGSCLR_OFFSET         0x34
+#define REALVIEW_SYS_NVFLAGS_OFFSET          0x38
+#define REALVIEW_SYS_NVFLAGSSET_OFFSET       0x38
+#define REALVIEW_SYS_NVFLAGSCLR_OFFSET       0x3C
+#define REALVIEW_SYS_RESETCTL_OFFSET         0x40
+#define REALVIEW_SYS_PCICTL_OFFSET           0x44
+#define REALVIEW_SYS_MCI_OFFSET              0x48
+#define REALVIEW_SYS_FLASH_OFFSET            0x4C
+#define REALVIEW_SYS_CLCD_OFFSET             0x50
+#define REALVIEW_SYS_CLCDSER_OFFSET          0x54
+#define REALVIEW_SYS_BOOTCS_OFFSET           0x58
+#define REALVIEW_SYS_24MHz_OFFSET            0x5C
+#define REALVIEW_SYS_MISC_OFFSET             0x60
+#define REALVIEW_SYS_IOSEL_OFFSET            0x70
+#define REALVIEW_SYS_TEST_OSC0_OFFSET        0x80
+#define REALVIEW_SYS_TEST_OSC1_OFFSET        0x84
+#define REALVIEW_SYS_TEST_OSC2_OFFSET        0x88
+#define REALVIEW_SYS_TEST_OSC3_OFFSET        0x8C
+#define REALVIEW_SYS_TEST_OSC4_OFFSET        0x90
+#define REALVIEW_SYS_BASE                    0x10000000
+#define REALVIEW_SYS_ID                      (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
+#define REALVIEW_SYS_SW                      (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
+#define REALVIEW_SYS_LED                     (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
+#define REALVIEW_SYS_OSC0                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
+#define REALVIEW_SYS_OSC1                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
+#define REALVIEW_SYS_LOCK                    (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
+#define REALVIEW_SYS_100HZ                   (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
+#define REALVIEW_SYS_CFGDATA1                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
+#define REALVIEW_SYS_CFGDATA2                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
+#define REALVIEW_SYS_FLAGS                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
+#define REALVIEW_SYS_FLAGSSET                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
+#define REALVIEW_SYS_FLAGSCLR                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
+#define REALVIEW_SYS_NVFLAGS                 (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
+#define REALVIEW_SYS_NVFLAGSSET              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
+#define REALVIEW_SYS_NVFLAGSCLR              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
+#define REALVIEW_SYS_RESETCTL                (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
+#define REALVIEW_SYS_PCICTL                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
+#define REALVIEW_SYS_MCI                     (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
+#define REALVIEW_SYS_FLASH                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
+#define REALVIEW_SYS_CLCD                    (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
+#define REALVIEW_SYS_CLCDSER                 (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
+#define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
+#define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
+#define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
+#define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
+#define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
+#define REALVIEW_SYS_TEST_OSC1               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
+#define REALVIEW_SYS_TEST_OSC2               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
+#define REALVIEW_SYS_TEST_OSC3               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
+#define REALVIEW_SYS_TEST_OSC4               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
+/* 
+ * Values for REALVIEW_SYS_RESET_CTRL
+ */
+#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR    0x01
+#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT   0x02
+#define REALVIEW_SYS_CTRL_RESET_DLLRESET     0x03
+#define REALVIEW_SYS_CTRL_RESET_PLLRESET     0x04
+#define REALVIEW_SYS_CTRL_RESET_POR          0x05
+#define REALVIEW_SYS_CTRL_RESET_DoC          0x06
+#define REALVIEW_SYS_CTRL_LED         (1 << 0)
+/* ------------------------------------------------------------------------
+ *  RealView control registers
+ * ------------------------------------------------------------------------
+ */
+/* 
+ * REALVIEW_IDFIELD
+ *
+ * 31:24 = manufacturer (0x41 = ARM)
+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
+ * 11:4  = build value
+ * 3:0   = revision number (0x1 = rev B (AHB))
+ */
+/*
+ * REALVIEW_SYS_LOCK
+ *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
+ *     SYS_CLD, SYS_BOOTCS
+ */
+#define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
+#define REALVIEW_SYS_LOCKVAL_MASK       0xFFFF          /* write 0xA05F to enable write access */
+/*
+ * REALVIEW_SYS_FLASH
+ */
+#define REALVIEW_FLASHPROG_FLVPPEN      (1 << 0)        /* Enable writing to flash */
+/*
+ * REALVIEW_INTREG
+ *     - used to acknowledge and control MMCI and UART interrupts 
+ */
+#define REALVIEW_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
+#define REALVIEW_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
+#define REALVIEW_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
+                                                /* write 1 to acknowledge and clear               */
+#define REALVIEW_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
+#define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
+/*
+ * REALVIEW peripheral addresses
+ */
+#define REALVIEW_SCTL_BASE            0x10001000        /* System controller */
+#define REALVIEW_I2C_BASE             0x10002000        /* I2C control */
+        /* Reserved 0x10003000 */
+#define REALVIEW_AACI_BASE            0x10004000        /* Audio */
+#define REALVIEW_MMCI0_BASE           0x10005000        /* MMC interface */
+#define REALVIEW_KMI0_BASE            0x10006000        /* KMI interface */
+#define REALVIEW_KMI1_BASE            0x10007000        /* KMI 2nd interface */
+#define REALVIEW_CHAR_LCD_BASE        0x10008000        /* Character LCD */
+#define REALVIEW_UART0_BASE           0x10009000        /* UART 0 */
+#define REALVIEW_UART1_BASE           0x1000A000        /* UART 1 */
+#define REALVIEW_UART2_BASE           0x1000B000        /* UART 2 */
+#define REALVIEW_UART3_BASE           0x1000C000        /* UART 3 */
+#define REALVIEW_SSP_BASE             0x1000D000        /* Synchronous Serial Port */
+#define REALVIEW_SCI_BASE             0x1000E000        /* Smart card controller */
+        /* Reserved 0x1000F000 */
+#define REALVIEW_WATCHDOG_BASE        0x10010000        /* watchdog interface */
+#define REALVIEW_TIMER0_1_BASE        0x10011000        /* Timer 0 and 1 */
+#define REALVIEW_TIMER2_3_BASE        0x10012000        /* Timer 2 and 3 */
+#define REALVIEW_GPIO0_BASE           0x10013000        /* GPIO port 0 */
+#define REALVIEW_GPIO1_BASE           0x10014000        /* GPIO port 1 */
+#define REALVIEW_GPIO2_BASE           0x10015000        /* GPIO port 2 */
+        /* Reserved 0x10016000 */
+#define REALVIEW_RTC_BASE             0x10017000        /* Real Time Clock */
+#define REALVIEW_DMC_BASE             0x10018000        /* DMC configuration */
+#define REALVIEW_PCI_CORE_BASE        0x10019000        /* PCI configuration */
+        /* Reserved 0x1001A000 - 0x1001FFFF */
+#define REALVIEW_CLCD_BASE            0x10020000        /* CLCD */
+#define REALVIEW_DMAC_BASE            0x10030000        /* DMA controller */
+#define REALVIEW_GIC_CPU_BASE         0x10040000        /* Generic interrupt controller CPU interface */
+#define REALVIEW_GIC_DIST_BASE        0x10041000        /* Generic interrupt controller distributor */
+#define REALVIEW_SMC_BASE             0x10080000        /* SMC */
+        /* Reserved 0x10090000 - 0x100EFFFF */
+#define REALVIEW_ETH_BASE             0x4E000000        /* Ethernet */
+/* PCI space */
+#define REALVIEW_PCI_BASE             0x41000000        /* PCI Interface */
+#define REALVIEW_PCI_CFG_BASE         0x42000000
+#define REALVIEW_PCI_MEM_BASE0        0x44000000
+#define REALVIEW_PCI_MEM_BASE1        0x50000000
+#define REALVIEW_PCI_MEM_BASE2        0x60000000
+/* Sizes of above maps */
+#define REALVIEW_PCI_BASE_SIZE         0x01000000
+#define REALVIEW_PCI_CFG_BASE_SIZE    0x02000000
+#define REALVIEW_PCI_MEM_BASE0_SIZE   0x0c000000        /* 32Mb */
+#define REALVIEW_PCI_MEM_BASE1_SIZE   0x10000000        /* 256Mb */
+#define REALVIEW_PCI_MEM_BASE2_SIZE   0x10000000        /* 256Mb */
+#define REALVIEW_SDRAM67_BASE         0x70000000        /* SDRAM banks 6 and 7 */
+#define REALVIEW_LT_BASE              0x80000000        /* Logic Tile expansion */
+/*
+ * Disk on Chip
+ */
+#define REALVIEW_DOC_BASE             0x2C000000
+#define REALVIEW_DOC_SIZE             (16 << 20)
+#define REALVIEW_DOC_PAGE_SIZE        512
+#define REALVIEW_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
+#define ERASE_UNIT_PAGES    32
+#define START_PAGE          0x80
+/* 
+ *  LED settings, bits [7:0]
+ */
+#define REALVIEW_SYS_LED0             (1 << 0)
+#define REALVIEW_SYS_LED1             (1 << 1)
+#define REALVIEW_SYS_LED2             (1 << 2)
+#define REALVIEW_SYS_LED3             (1 << 3)
+#define REALVIEW_SYS_LED4             (1 << 4)
+#define REALVIEW_SYS_LED5             (1 << 5)
+#define REALVIEW_SYS_LED6             (1 << 6)
+#define REALVIEW_SYS_LED7             (1 << 7)
+#define ALL_LEDS                  0xFF
+#define LED_BANK                  REALVIEW_SYS_LED
+/* 
+ * Control registers
+ */
+#define REALVIEW_IDFIELD_OFFSET 0x0     /* RealView build information */
+#define REALVIEW_FLASHPROG_OFFSET       0x4     /* Flash devices */
+#define REALVIEW_INTREG_OFFSET          0x8     /* Interrupt control */
+#define REALVIEW_DECODE_OFFSET          0xC     /* Fitted logic modules */
+/* ------------------------------------------------------------------------
+ *  Interrupts - bit assignment (primary)
+ * ------------------------------------------------------------------------
+ */
+#define INT_WDOGINT                     0       /* Watchdog timer */
+#define INT_SOFTINT                     1       /* Software interrupt */
+#define INT_COMMRx                      2       /* Debug Comm Rx interrupt */
+#define INT_COMMTx                      3       /* Debug Comm Tx interrupt */
+#define INT_TIMERINT0_1                 4       /* Timer 0 and 1 */
+#define INT_TIMERINT2_3                 5       /* Timer 2 and 3 */
+#define INT_GPIOINT0                    6       /* GPIO 0 */
+#define INT_GPIOINT1                    7       /* GPIO 1 */
+#define INT_GPIOINT2                    8       /* GPIO 2 */
+/* 9 reserved */
+#define INT_RTCINT                      10      /* Real Time Clock */
+#define INT_SSPINT                      11      /* Synchronous Serial Port */
+#define INT_UARTINT0                    12      /* UART 0 on development chip */
+#define INT_UARTINT1                    13      /* UART 1 on development chip */
+#define INT_UARTINT2                    14      /* UART 2 on development chip */
+#define INT_UARTINT3                    15      /* UART 3 on development chip */
+#define INT_SCIINT                      16      /* Smart Card Interface */
+#define INT_MMCI0A                      17      /* Multimedia Card 0A */
+#define INT_MMCI0B                      18      /* Multimedia Card 0B */
+#define INT_AACI                        19      /* Audio Codec */
+#define INT_KMI0                        20      /* Keyboard/Mouse port 0 */
+#define INT_KMI1                        21      /* Keyboard/Mouse port 1 */
+#define INT_CHARLCD                     22      /* Character LCD */
+#define INT_CLCDINT                     23      /* CLCD controller */
+#define INT_DMAINT                      24      /* DMA controller */
+#define INT_PWRFAILINT                  25      /* Power failure */
+#define INT_PISMO                       26
+#define INT_DoC                         27      /* Disk on Chip memory controller */
+#define INT_ETH                         28      /* Ethernet controller */
+#define INT_USB                         29      /* USB controller */
+#define INT_TSPENINT                    30      /* Touchscreen pen */
+#define INT_TSKPADINT                   31      /* Touchscreen keypad */
+/* 
+ *  Interrupt bit positions
+ * 
+ */
+#define INTMASK_WDOGINT                 (1 << INT_WDOGINT)
+#define INTMASK_SOFTINT                 (1 << INT_SOFTINT)
+#define INTMASK_COMMRx                  (1 << INT_COMMRx)
+#define INTMASK_COMMTx                  (1 << INT_COMMTx)
+#define INTMASK_TIMERINT0_1             (1 << INT_TIMERINT0_1)
+#define INTMASK_TIMERINT2_3             (1 << INT_TIMERINT2_3)
+#define INTMASK_GPIOINT0                (1 << INT_GPIOINT0)
+#define INTMASK_GPIOINT1                (1 << INT_GPIOINT1)
+#define INTMASK_GPIOINT2                (1 << INT_GPIOINT2)
+#define INTMASK_RTCINT                  (1 << INT_RTCINT)
+#define INTMASK_SSPINT                  (1 << INT_SSPINT)
+#define INTMASK_UARTINT0                (1 << INT_UARTINT0)
+#define INTMASK_UARTINT1                (1 << INT_UARTINT1)
+#define INTMASK_UARTINT2                (1 << INT_UARTINT2)
+#define INTMASK_UARTINT3                (1 << INT_UARTINT3)
+#define INTMASK_SCIINT                  (1 << INT_SCIINT)
+#define INTMASK_MMCI0A                  (1 << INT_MMCI0A)
+#define INTMASK_MMCI0B                  (1 << INT_MMCI0B)
+#define INTMASK_AACI                    (1 << INT_AACI)
+#define INTMASK_KMI0                    (1 << INT_KMI0)
+#define INTMASK_KMI1                    (1 << INT_KMI1)
+#define INTMASK_CHARLCD                 (1 << INT_CHARLCD)
+#define INTMASK_CLCDINT                 (1 << INT_CLCDINT)
+#define INTMASK_DMAINT                  (1 << INT_DMAINT)
+#define INTMASK_PWRFAILINT              (1 << INT_PWRFAILINT)
+#define INTMASK_PISMO                   (1 << INT_PISMO)
+#define INTMASK_DoC                     (1 << INT_DoC)
+#define INTMASK_ETH                     (1 << INT_ETH)
+#define INTMASK_USB                     (1 << INT_USB)
+#define INTMASK_TSPENINT                (1 << INT_TSPENINT)
+#define INTMASK_TSKPADINT               (1 << INT_TSKPADINT)
+#define MAXIRQNUM                       31
+#define MAXFIQNUM                       31
+#define MAXSWINUM                       31
+/* 
+ *  Application Flash
+ * 
+ */
+#define FLASH_BASE                      REALVIEW_FLASH_BASE
+#define FLASH_SIZE                      REALVIEW_FLASH_SIZE
+#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
+#define FLASH_BLOCK_SIZE                SZ_128K
+/* 
+ *  Boot Flash
+ * 
+ */
+#define EPROM_BASE                      REALVIEW_BOOT_ROM_HI
+#define EPROM_SIZE                      REALVIEW_BOOT_ROM_SIZE
+#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
+/* 
+ *  Clean base - dummy
+ * 
+ */
+#define CLEAN_BASE                      EPROM_BASE
+/*
+ * System controller bit assignment
+ */
+#define REALVIEW_REFCLK 0
+#define REALVIEW_TIMCLK 1
+#define REALVIEW_TIMER1_EnSel   15
+#define REALVIEW_TIMER2_EnSel   17
+#define REALVIEW_TIMER3_EnSel   19
+#define REALVIEW_TIMER4_EnSel   21
+#define MAX_TIMER                       2
+#define MAX_PERIOD                      699050
+#define TICKS_PER_uSEC                  1
+/* 
+ *  These are useconds NOT ticks.  
+ * 
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+#define REALVIEW_CSR_BASE             0x10000000
+#define REALVIEW_CSR_SIZE             0x10000000
+#endif
+/*      END */
diff --git a/include/asm-arm/arch-realview/system.h b/include/asm-arm/arch-realview/system.h
new file mode 100644
index 000000000000..9f8fcbca0869
--- /dev/null
+++ b/include/asm-arm/arch-realview/system.h
@@ -0,0 +1,51 @@
+/*
+ *  linux/include/asm-arm/arch-realview/system.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        unsigned int hdr_ctrl = (IO_ADDRESS(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET);
+        unsigned int val;
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        val = __raw_readl(hdr_ctrl);
+        val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR;
+        __raw_writel(val, hdr_ctrl);
+}
+#endif
diff --git a/include/asm-arm/arch-realview/timex.h b/include/asm-arm/arch-realview/timex.h
new file mode 100644
index 000000000000..5b9d82d0a5e0
--- /dev/null
+++ b/include/asm-arm/arch-realview/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  linux/include/asm-arm/arch-realview/timex.h
+ *
+ *  RealView architecture timex specifications
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
new file mode 100644
index 000000000000..b5e4d360665b
--- /dev/null
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -0,0 +1,54 @@
+/*
+ *  linux/include/asm-arm/arch-realview/uncompress.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/hardware.h>
+#define AMBA_UART_DR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
+#define AMBA_UART_LCRH  (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
+#define AMBA_UART_CR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
+#define AMBA_UART_FR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18))
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                while (AMBA_UART_FR & (1 << 5))
+                        barrier();
+                AMBA_UART_DR = *s;
+                if (*s == '\n') {
+                        while (AMBA_UART_FR & (1 << 5))
+                                barrier();
+                        AMBA_UART_DR = '\r';
+                }
+                s++;
+        }
+        while (AMBA_UART_FR & (1 << 3))
+                barrier();
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-realview/vmalloc.h b/include/asm-arm/arch-realview/vmalloc.h
new file mode 100644
index 000000000000..0ad49af186af
--- /dev/null
+++ b/include/asm-arm/arch-realview/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-realview/vmalloc.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
diff --git a/include/asm-arm/arch-rpc/memory.h b/include/asm-arm/arch-rpc/memory.h
index 33fc75cdead0..0592cb3f0c74 100644
--- a/include/asm-arm/arch-rpc/memory.h
+++ b/include/asm-arm/arch-rpc/memory.h
@@ -21,7 +21,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x10000000UL)
+#define PHYS_OFFSET     UL(0x10000000)
 /*
 * These are exactly the same on the RiscPC as the
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 3380ab1d0749..6ab834a14c8e 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -28,9 +28,9 @@
 * and at 0x0C000000 for S3C2400
 */
 #ifdef CONFIG_CPU_S3C2400
-#define PHYS_OFFSET     (0x0C000000UL)
+#define PHYS_OFFSET     UL(0x0C000000)
 #else
-#define PHYS_OFFSET     (0x30000000UL)
+#define PHYS_OFFSET     UL(0x30000000)
 #endif
 /*
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index fdd62e8cd6cb..7fdde9b91cb4 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -55,6 +55,7 @@
 #define S3C2410_IISMOD_16FS       (0<<0)
 #define S3C2410_IISMOD_32FS       (1<<0)
 #define S3C2410_IISMOD_48FS       (2<<0)
+#define S3C2410_IISMOD_FS_MASK    (3<<0)
 #define S3C2410_IISPSR          (0x08)
 #define S3C2410_IISPSR_INTMASK  (31<<5)
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 8743ff5c1b23..0fc555b4c912 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -13,7 +13,7 @@
 /*
 * Physical DRAM offset is 0xc0000000 on the SA1100
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-shark/memory.h b/include/asm-arm/arch-shark/memory.h
index 8ff956d25463..95a29b4bc5d0 100644
--- a/include/asm-arm/arch-shark/memory.h
+++ b/include/asm-arm/arch-shark/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x08000000UL)
+#define PHYS_OFFSET     UL(0x08000000)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-versatile/memory.h b/include/asm-arm/arch-versatile/memory.h
index 7b8b7cc422fa..a9370976cc5e 100644
--- a/include/asm-arm/arch-versatile/memory.h
+++ b/include/asm-arm/arch-versatile/memory.h
@@ -23,7 +23,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/cpu.h b/include/asm-arm/cpu.h
index fcbdd40cb667..751bc7462074 100644
--- a/include/asm-arm/cpu.h
+++ b/include/asm-arm/cpu.h
@@ -16,6 +16,7 @@
 struct cpuinfo_arm {
        struct cpu      cpu;
 #ifdef CONFIG_SMP
+        struct task_struct *idle;
        unsigned int    loops_per_jiffy;
 #endif
 };
diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h
index ce4cf5c1c05d..6b8d73dc1ab0 100644
--- a/include/asm-arm/hardware/amba_clcd.h
+++ b/include/asm-arm/hardware/amba_clcd.h
@@ -22,7 +22,7 @@
 #define CLCD_UBAS               0x00000010
 #define CLCD_LBAS               0x00000014
-#ifndef CONFIG_ARCH_VERSATILE
+#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
 #define CLCD_IENB               0x00000018
 #define CLCD_CNTL               0x0000001c
 #else
diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h
index f97912fbb10f..59975ee43cf1 100644
--- a/include/asm-arm/irq.h
+++ b/include/asm-arm/irq.h
@@ -47,5 +47,6 @@ struct irqaction;
 struct pt_regs;
 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
+extern void migrate_irqs(void);
 #endif
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index 7273c6fd95b5..eb262e078c46 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -50,6 +50,7 @@ struct machine_desc {
 */
 #define MACHINE_START(_type,_name)                      \
 static const struct machine_desc __mach_desc_##_type    \
+ __attribute_used__                                     \
 __attribute__((__section__(".arch.info.init"))) = {    \
        .nr             = MACH_TYPE_##_type,            \
        .name           = _name,
diff --git a/include/asm-arm/mach/flash.h b/include/asm-arm/mach/flash.h
index a92887d4b2cb..cd57436d9874 100644
--- a/include/asm-arm/mach/flash.h
+++ b/include/asm-arm/mach/flash.h
@@ -14,6 +14,7 @@ struct mtd_partition;
 /*
 * map_name:    the map probe function name
+ * name:        flash device name (eg, as used with mtdparts=)
 * width:       width of mapped device
 * init:        method called at driver/device initialisation
 * exit:        method called at driver/device removal
@@ -23,6 +24,7 @@ struct mtd_partition;
 */
 struct flash_platform_data {
        const char      *map_name;
+        const char      *name;
        unsigned int    width;
        int             (*init)(void);
        void            (*exit)(void);
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
index 0619522bd926..b338936bde4f 100644
--- a/include/asm-arm/mach/map.h
+++ b/include/asm-arm/mach/map.h
@@ -27,8 +27,8 @@ struct meminfo;
 #define MT_ROM                  6
 #define MT_IXP2000_DEVICE       7
-#define __phys_to_pfn(paddr)    (paddr >> PAGE_SHIFT)
+#define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
-#define __pfn_to_phys(pfn)      (pfn << PAGE_SHIFT)
+#define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
 extern void create_memmap_holes(struct meminfo *);
 extern void memtable_init(struct meminfo *);
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index a8a933a775db..a547ee598c6c 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -12,6 +12,16 @@
 #ifndef __ASM_ARM_MEMORY_H
 #define __ASM_ARM_MEMORY_H
+/*
+ * Allow for constants defined here to be used from assembly code
+ * by prepending the UL suffix only with actual C code compilation.
+ */
+#ifndef __ASSEMBLY__
+#define UL(x) (x##UL)
+#else
+#define UL(x) (x)
+#endif
 #include <linux/config.h>
 #include <linux/compiler.h>
 #include <asm/arch/memory.h>
@@ -21,20 +31,20 @@
 * TASK_SIZE - the maximum size of a user space task.
 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
 */
-#define TASK_SIZE               (0xbf000000UL)
+#define TASK_SIZE               UL(0xbf000000)
-#define TASK_UNMAPPED_BASE      (0x40000000UL)
+#define TASK_UNMAPPED_BASE      UL(0x40000000)
 #endif
 /*
 * The maximum size of a 26-bit user space task.
 */
-#define TASK_SIZE_26            (0x04000000UL)
+#define TASK_SIZE_26            UL(0x04000000)
 /*
 * Page offset: 3GB
 */
 #ifndef PAGE_OFFSET
-#define PAGE_OFFSET             (0xc0000000UL)
+#define PAGE_OFFSET             UL(0xc0000000)
 #endif
 /*
@@ -58,6 +68,13 @@
 #error Top of user space clashes with start of module space
 #endif
+/*
+ * The XIP kernel gets mapped at the bottom of the module vm area.
+ * Since we use sections to map it, this macro replaces the physical address
+ * with its virtual address while keeping offset from the base section.
+ */
+#define XIP_VIRT_ADDR(physaddr)  (MODULE_START + ((physaddr) & 0x000fffff))
 #ifndef __ASSEMBLY__
 /*
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 4af9c411c617..57b8def83d41 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -86,7 +86,8 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
                cpu_set(cpu, next->cpu_vm_mask);
                check_context(next);
                cpu_switch_mm(next->pgd, next);
-                cpu_clear(cpu, prev->cpu_vm_mask);
+                if (cache_is_vivt())
+                        cpu_clear(cpu, prev->cpu_vm_mask);
        }
 }
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 366bafbdfbb1..5a0d19b466b0 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -397,9 +397,6 @@ static inline pte_t *pmd_page_kernel(pmd_t pmd)
 #define pgd_clear(pgdp)         do { } while (0)
 #define set_pgd(pgd,pgdp)       do { } while (0)
-#define page_pte_prot(page,prot)        mk_pte(page, prot)
-#define page_pte(page)          mk_pte(page, __pgprot(0))
 /* to find an entry in a page-table-directory */
 #define pgd_index(addr)         ((addr) >> PGDIR_SHIFT)
diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h
index 60f33e6eb800..71ca7d412687 100644
--- a/include/asm-arm/semaphore.h
+++ b/include/asm-arm/semaphore.h
@@ -24,8 +24,6 @@ struct semaphore {
        .wait   = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
 }
-#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INIT(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INIT(name,count)
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index dbb4d859c586..551cd3c3093c 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -66,4 +66,14 @@ struct secondary_data {
 };
 extern struct secondary_data secondary_data;
+extern int __cpu_disable(void);
+extern int mach_cpu_disable(unsigned int cpu);
+extern void __cpu_die(unsigned int cpu);
+extern void cpu_die(void);
+extern void platform_cpu_die(unsigned int cpu);
+extern int platform_cpu_kill(unsigned int cpu);
+extern void platform_cpu_enable(unsigned int cpu);
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index cb4906b45555..6ed4f916b166 100644
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -80,7 +80,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 */
 #define rwlock_is_locked(x)     (*((volatile unsigned int *)(x)) != 0)
-static inline void __raw_write_lock(rwlock_t *rw)
+static inline void __raw_write_lock(raw_rwlock_t *rw)
 {
        unsigned long tmp;
@@ -97,7 +97,7 @@ static inline void __raw_write_lock(rwlock_t *rw)
        smp_mb();
 }
-static inline int __raw_write_trylock(rwlock_t *rw)
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
        unsigned long tmp;
@@ -157,7 +157,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
        smp_mb();
 }
-static inline void __raw_read_unlock(rwlock_t *rw)
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
 {
        unsigned long tmp, tmp2;
diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h
index 9bb325c54645..f49bfb78c221 100644
--- a/include/asm-arm/tlb.h
+++ b/include/asm-arm/tlb.h
@@ -27,11 +27,7 @@
 */
 struct mmu_gather {
        struct mm_struct        *mm;
-        unsigned int            freed;
        unsigned int            fullmm;
-        unsigned int            flushes;
-        unsigned int            avoided_flushes;
 };
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -39,11 +35,9 @@ DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        int cpu = smp_processor_id();
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-        struct mmu_gather *tlb = &per_cpu(mmu_gathers, cpu);
        tlb->mm = mm;
-        tlb->freed = 0;
        tlb->fullmm = full_mm_flush;
        return tlb;
@@ -52,24 +46,13 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        struct mm_struct *mm = tlb->mm;
-        unsigned long freed = tlb->freed;
-        int rss = get_mm_counter(mm, rss);
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
        if (tlb->fullmm)
-                flush_tlb_mm(mm);
+                flush_tlb_mm(tlb->mm);
        /* keep the page table cache within bounds */
        check_pgt_cache();
-}
-static inline unsigned int tlb_is_full_mm(struct mmu_gather *tlb)
+        put_cpu_var(mmu_gathers);
-{
-        return tlb->fullmm;
 }
 #define tlb_remove_tlb_entry(tlb,ptep,address)  do { } while (0)
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index c49df635a80f..d626e70faded 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -544,7 +544,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
 asmlinkage int sys_fork(struct pt_regs *regs);
 asmlinkage int sys_vfork(struct pt_regs *regs);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-arm26/pgtable.h b/include/asm-arm26/pgtable.h
index f602cf572411..a590250277f8 100644
--- a/include/asm-arm26/pgtable.h
+++ b/include/asm-arm26/pgtable.h
@@ -98,8 +98,6 @@ extern struct page *empty_zero_page;
 #define pfn_pte(pfn,prot)       (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
 #define pages_to_mb(x)          ((x) >> (20 - PAGE_SHIFT))
 #define mk_pte(page,prot)       pfn_pte(page_to_pfn(page),prot)
-#define page_pte_prot(page,prot)        mk_pte(page, prot)
-#define page_pte(page)          mk_pte(page, __pgprot(0))
 /*
 * Terminology: PGD = Page Directory, PMD = Page Middle Directory,
diff --git a/include/asm-arm26/semaphore.h b/include/asm-arm26/semaphore.h
index c1b6a1edad92..ccf15e704109 100644
--- a/include/asm-arm26/semaphore.h
+++ b/include/asm-arm26/semaphore.h
@@ -25,9 +25,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INIT(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INIT(name,count)
diff --git a/include/asm-arm26/tlb.h b/include/asm-arm26/tlb.h
index 1316352a58f3..08ddd85b8d35 100644
--- a/include/asm-arm26/tlb.h
+++ b/include/asm-arm26/tlb.h
@@ -10,24 +10,20 @@
 */
 struct mmu_gather {
        struct mm_struct        *mm;
-        unsigned int            freed;
+        unsigned int            need_flush;
-        unsigned int            fullmm;
+        unsigned int            fullmm;
-        unsigned int            flushes;
-        unsigned int            avoided_flushes;
 };
-extern struct mmu_gather mmu_gathers[NR_CPUS];
+DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        int cpu = smp_processor_id();
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-        struct mmu_gather *tlb = &mmu_gathers[cpu];
        tlb->mm = mm;
-        tlb->freed = 0;
+        tlb->need_flush = 0;
-        tlb->fullmm = full_mm_flush;
+        tlb->fullmm = full_mm_flush;
        return tlb;
 }
@@ -35,30 +31,13 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        struct mm_struct *mm = tlb->mm;
+        if (tlb->need_flush)
-        unsigned long freed = tlb->freed;
+                flush_tlb_mm(tlb->mm);
-        int rss = get_mm_counter(mm, rss);
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
-        if (freed) {
-                flush_tlb_mm(mm);
-                tlb->flushes++;
-        } else {
-                tlb->avoided_flushes++;
-        }
        /* keep the page table cache within bounds */
        check_pgt_cache();
-}
-static inline unsigned int
+        put_cpu_var(mmu_gathers);
-tlb_is_full_mm(struct mmu_gather *tlb)
-{
-     return tlb->fullmm;
 }
 #define tlb_remove_tlb_entry(tlb,ptep,address)  do { } while (0)
@@ -71,7 +50,13 @@ tlb_is_full_mm(struct mmu_gather *tlb)
        } while (0)
 #define tlb_end_vma(tlb,vma)                    do { } while (0)
-#define tlb_remove_page(tlb,page)       free_page_and_swap_cache(page)
+static inline void
+tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        tlb->need_flush = 1;
+        free_page_and_swap_cache(page);
+}
 #define pte_free_tlb(tlb,ptep)          pte_free(ptep)
 #define pmd_free_tlb(tlb,pmdp)          pmd_free(pmdp)
diff --git a/include/asm-arm26/unistd.h b/include/asm-arm26/unistd.h
index dfa0b0c30aa3..be4c2fb9c049 100644
--- a/include/asm-arm26/unistd.h
+++ b/include/asm-arm26/unistd.h
@@ -480,7 +480,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
 asmlinkage int sys_fork(struct pt_regs *regs);
 asmlinkage int sys_vfork(struct pt_regs *regs);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-cris/semaphore.h b/include/asm-cris/semaphore.h
index 8ed7636ab311..39faf69bcf76 100644
--- a/include/asm-cris/semaphore.h
+++ b/include/asm-cris/semaphore.h
@@ -33,9 +33,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h
index 28232ad2ff34..156a34bfc583 100644
--- a/include/asm-cris/unistd.h
+++ b/include/asm-cris/unistd.h
@@ -367,7 +367,6 @@ asmlinkage int sys_fork(long r10, long r11, long r12, long r13,
 asmlinkage int sys_vfork(long r10, long r11, long r12, long r13,
                        long mof, long srp, struct pt_regs *regs);
 asmlinkage int sys_pipe(unsigned long __user *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h
index 473fb4bb6329..b247e99dff49 100644
--- a/include/asm-frv/pgtable.h
+++ b/include/asm-frv/pgtable.h
@@ -436,8 +436,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
        return pte;
 }
-#define page_pte(page)  page_pte_prot((page), __pgprot(0))
 /* to find an entry in a page-table-directory. */
 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
 #define pgd_index_k(addr) pgd_index(addr)
diff --git a/include/asm-frv/semaphore.h b/include/asm-frv/semaphore.h
index 393545630806..b18396288df1 100644
--- a/include/asm-frv/semaphore.h
+++ b/include/asm-frv/semaphore.h
@@ -47,9 +47,6 @@ struct semaphore {
 #define __SEMAPHORE_INITIALIZER(name,count) \
 { count, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) __SEM_DEBUG_INIT(name) }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-generic/4level-fixup.h b/include/asm-generic/4level-fixup.h
index c20ec257ecc0..68c6fea994d9 100644
--- a/include/asm-generic/4level-fixup.h
+++ b/include/asm-generic/4level-fixup.h
@@ -10,14 +10,9 @@
 #define pud_t                           pgd_t
-#define pmd_alloc(mm, pud, address)                     \
+#define pmd_alloc(mm, pud, address) \
-({      pmd_t *ret;                                     \
+        ((unlikely(pgd_none(*(pud))) && __pmd_alloc(mm, pud, address))? \
-        if (pgd_none(*pud))                             \
+                NULL: pmd_offset(pud, address))
-                ret = __pmd_alloc(mm, pud, address);    \
-        else                                            \
-                ret = pmd_offset(pud, address);         \
-        ret;                                            \
-})
 #define pud_alloc(mm, pgd, address)     (pgd)
 #define pud_offset(pgd, start)          (pgd)
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index ff28c8b31f58..7dca30a26c53 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -8,7 +8,7 @@
 *  - update the page tables
 *  - inform the TLB about the new one
 *
- * We hold the mm semaphore for reading and vma->vm_mm->page_table_lock.
+ * We hold the mm semaphore for reading, and the pte lock.
 *
 * Note: the old pte is known to not be writable, so we don't need to
 * worry about dirty bits etc getting lost.
diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h
index 7d0298347ee7..cdd4145243cd 100644
--- a/include/asm-generic/tlb.h
+++ b/include/asm-generic/tlb.h
@@ -35,16 +35,13 @@
 #endif
 /* struct mmu_gather is an opaque type used by the mm code for passing around
- * any data needed by arch specific code for tlb_remove_page.  This structure
+ * any data needed by arch specific code for tlb_remove_page.
- * can be per-CPU or per-MM as the page table lock is held for the duration of
- * TLB shootdown.
 */
 struct mmu_gather {
        struct mm_struct        *mm;
        unsigned int            nr;     /* set to ~0U means fast mode */
        unsigned int            need_flush;/* Really unmapped some ptes? */
        unsigned int            fullmm; /* non-zero means full mm flush */
-        unsigned long           freed;
        struct page *           pages[FREE_PTE_NR];
 };
@@ -57,7 +54,7 @@ DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *tlb = &per_cpu(mmu_gathers, smp_processor_id());
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
        tlb->mm = mm;
@@ -65,7 +62,6 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
        tlb->nr = num_online_cpus() > 1 ? 0U : ~0U;
        tlb->fullmm = full_mm_flush;
-        tlb->freed = 0;
        return tlb;
 }
@@ -85,28 +81,17 @@ tlb_flush_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 /* tlb_finish_mmu
 *      Called at the end of the shootdown operation to free up any resources
- *      that were required.  The page table lock is still held at this point.
+ *      that were required.
 */
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        int freed = tlb->freed;
-        struct mm_struct *mm = tlb->mm;
-        int rss = get_mm_counter(mm, rss);
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
        tlb_flush_mmu(tlb, start, end);
        /* keep the page table cache within bounds */
        check_pgt_cache();
-}
-static inline unsigned int
+        put_cpu_var(mmu_gathers);
-tlb_is_full_mm(struct mmu_gather *tlb)
-{
-        return tlb->fullmm;
 }
 /* tlb_remove_page
diff --git a/include/asm-h8300/semaphore.h b/include/asm-h8300/semaphore.h
index fe6ef3774297..81bae2a99192 100644
--- a/include/asm-h8300/semaphore.h
+++ b/include/asm-h8300/semaphore.h
@@ -35,9 +35,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-h8300/unistd.h b/include/asm-h8300/unistd.h
index 56a6401886fa..56a4a5686c88 100644
--- a/include/asm-h8300/unistd.h
+++ b/include/asm-h8300/unistd.h
@@ -528,7 +528,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
 asmlinkage int sys_execve(char *name, char **argv, char **envp,
                        int dummy, ...);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-i386/desc.h b/include/asm-i386/desc.h
index 6df1a53c190e..29b851a18c6e 100644
--- a/include/asm-i386/desc.h
+++ b/include/asm-i386/desc.h
@@ -17,6 +17,8 @@
 extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
 DECLARE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
+#define get_cpu_gdt_table(_cpu) (per_cpu(cpu_gdt_table,_cpu))
 DECLARE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
 struct Xgt_desc_struct {
@@ -60,7 +62,7 @@ __asm__ __volatile__ ("movw %w3,0(%2)\n\t" \
 static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *addr)
 {
-        _set_tssldt_desc(&per_cpu(cpu_gdt_table, cpu)[entry], (int)addr,
+        _set_tssldt_desc(&get_cpu_gdt_table(cpu)[entry], (int)addr,
                offsetof(struct tss_struct, __cacheline_filler) - 1, 0x89);
 }
@@ -68,7 +70,7 @@ static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *ad
 static inline void set_ldt_desc(unsigned int cpu, void *addr, unsigned int size)
 {
-        _set_tssldt_desc(&per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
+        _set_tssldt_desc(&get_cpu_gdt_table(cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
 }
 #define LDT_entry_a(info) \
@@ -109,7 +111,7 @@ static inline void write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 en
 static inline void load_TLS(struct thread_struct *t, unsigned int cpu)
 {
-#define C(i) per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
+#define C(i) get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
        C(0); C(1); C(2);
 #undef C
 }
diff --git a/include/asm-i386/mach-es7000/mach_mpparse.h b/include/asm-i386/mach-es7000/mach_mpparse.h
index 28a84f6185a7..4a0637a3e208 100644
--- a/include/asm-i386/mach-es7000/mach_mpparse.h
+++ b/include/asm-i386/mach-es7000/mach_mpparse.h
@@ -16,7 +16,7 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
 extern int parse_unisys_oem (char *oemptr);
 extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
-extern void setup_unisys();
+extern void setup_unisys(void);
 static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
                char *productid)
diff --git a/include/asm-i386/mach-summit/mach_mpparse.h b/include/asm-i386/mach-summit/mach_mpparse.h
index 2b9e6d55bef1..1cce2b924a80 100644
--- a/include/asm-i386/mach-summit/mach_mpparse.h
+++ b/include/asm-i386/mach-summit/mach_mpparse.h
@@ -22,7 +22,6 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
 {
 }
-extern int usb_early_handoff;
 static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, 
                char *productid)
 {
@@ -32,7 +31,6 @@ static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
                         || !strncmp(productid, "RUTHLESS SMP", 12))){
                use_cyclone = 1; /*enable cyclone-timer*/
                setup_summit();
-                usb_early_handoff = 1;
                return 1;
        }
        return 0;
@@ -46,7 +44,6 @@ static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
             || !strncmp(oem_table_id, "EXA", 3))){
                use_cyclone = 1; /*enable cyclone-timer*/
                setup_summit();
-                usb_early_handoff = 1;
                return 1;
        }
        return 0;
diff --git a/include/asm-i386/mmzone.h b/include/asm-i386/mmzone.h
index 348fe3a4879d..620a90641ea8 100644
--- a/include/asm-i386/mmzone.h
+++ b/include/asm-i386/mmzone.h
@@ -88,12 +88,6 @@ static inline int pfn_to_nid(unsigned long pfn)
        __pgdat->node_start_pfn + __pgdat->node_spanned_pages;          \
 })
-#define local_mapnr(kvaddr)                                             \
-({                                                                      \
-        unsigned long __pfn = __pa(kvaddr) >> PAGE_SHIFT;               \
-        (__pfn - node_start_pfn(pfn_to_nid(__pfn)));                    \
-})
 /* XXX: FIXME -- wli */
 #define kern_addr_valid(kaddr)  (0)
diff --git a/include/asm-i386/pgtable-2level.h b/include/asm-i386/pgtable-2level.h
index fa07bd6c7529..74ef721b534d 100644
--- a/include/asm-i386/pgtable-2level.h
+++ b/include/asm-i386/pgtable-2level.h
@@ -26,11 +26,6 @@
 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-#define pmd_page_kernel(pmd) \
-((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 /*
 * All present user pages are user-executable:
 */
diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-i386/pgtable-3level.h
index 2e3f4a344a2d..f1a8b454920a 100644
--- a/include/asm-i386/pgtable-3level.h
+++ b/include/asm-i386/pgtable-3level.h
@@ -74,11 +74,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
 */
 static inline void pud_clear (pud_t * pud) { }
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-#define pmd_page_kernel(pmd) \
-((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 #define pud_page(pud) \
 ((struct page *) __va(pud_val(pud) & PAGE_MASK))
diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h
index d101ac414f07..03f3c8ac6383 100644
--- a/include/asm-i386/pgtable.h
+++ b/include/asm-i386/pgtable.h
@@ -203,7 +203,8 @@ extern unsigned long pg0[];
 #define pte_present(x)  ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
 #define pte_clear(mm,addr,xp)   do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
-#define pmd_none(x)     (!pmd_val(x))
+/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
+#define pmd_none(x)     (!(unsigned long)pmd_val(x))
 #define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
 #define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
 #define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
@@ -322,8 +323,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
        return pte;
 }
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
 #define pmd_large(pmd) \
 ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
@@ -368,6 +367,11 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pte_offset_kernel(dir, address) \
        ((pte_t *) pmd_page_kernel(*(dir)) +  pte_index(address))
+#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
+#define pmd_page_kernel(pmd) \
+                ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 /*
 * Helper function that returns the kernel pagetable entry controlling
 * the virtual address 'address'. NULL means no pagetable entry present.
diff --git a/include/asm-i386/rwsem.h b/include/asm-i386/rwsem.h
index 7625a675852f..be4ab859238e 100644
--- a/include/asm-i386/rwsem.h
+++ b/include/asm-i386/rwsem.h
@@ -284,5 +284,10 @@ LOCK_PREFIX	"xadd %0,(%2)"
        return tmp+delta;
 }
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
 #endif /* __KERNEL__ */
 #endif /* _I386_RWSEM_H */
diff --git a/include/asm-i386/semaphore.h b/include/asm-i386/semaphore.h
index ea563da63e24..6a42b2142fd6 100644
--- a/include/asm-i386/semaphore.h
+++ b/include/asm-i386/semaphore.h
@@ -55,9 +55,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h
index acd5c26b69ba..97d52ac49e46 100644
--- a/include/asm-i386/system.h
+++ b/include/asm-i386/system.h
@@ -167,6 +167,8 @@ struct __xchg_dummy { unsigned long a[100]; };
 #define __xg(x) ((struct __xchg_dummy *)(x))
+#ifdef CONFIG_X86_CMPXCHG64
 /*
 * The semantics of XCHGCMP8B are a bit strange, this is why
 * there is a loop and the loading of %%eax and %%edx has to
@@ -221,6 +223,8 @@ static inline void __set_64bit_var (unsigned long long *ptr,
 __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
 __set_64bit(ptr, ll_low(value), ll_high(value)) )
+#endif
 /*
 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 * Note 2: xchg has side effect, so that attribute volatile is necessary,
@@ -259,7 +263,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 #ifdef CONFIG_X86_CMPXCHG
 #define __HAVE_ARCH_CMPXCHG 1
-#endif
 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
                                      unsigned long new, int size)
@@ -275,13 +278,13 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
        case 2:
                __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
                                     : "=a"(prev)
-                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
                                     : "memory");
                return prev;
        case 4:
                __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
                                     : "=a"(prev)
-                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
                                     : "memory");
                return prev;
        }
@@ -291,6 +294,30 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 #define cmpxchg(ptr,o,n)\
        ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
                                        (unsigned long)(n),sizeof(*(ptr))))
+#endif
+#ifdef CONFIG_X86_CMPXCHG64
+static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
+                                      unsigned long long new)
+{
+        unsigned long long prev;
+        __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
+                             : "=A"(prev)
+                             : "b"((unsigned long)new),
+                               "c"((unsigned long)(new >> 32)),
+                               "m"(*__xg(ptr)),
+                               "0"(old)
+                             : "memory");
+        return prev;
+}
+#define cmpxchg64(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
+                                        (unsigned long long)(n)))
+#endif
    
 #ifdef __KERNEL__
 struct alt_instr { 
diff --git a/include/asm-i386/unistd.h b/include/asm-i386/unistd.h
index fbaf90a3968c..0f92e78dfea1 100644
--- a/include/asm-i386/unistd.h
+++ b/include/asm-i386/unistd.h
@@ -448,7 +448,6 @@ asmlinkage int sys_clone(struct pt_regs regs);
 asmlinkage int sys_fork(struct pt_regs regs);
 asmlinkage int sys_vfork(struct pt_regs regs);
 asmlinkage int sys_pipe(unsigned long __user *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 asmlinkage long sys_iopl(unsigned long unused);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
index a2f6ac5aef7d..ca5ea994d688 100644
--- a/include/asm-ia64/machvec.h
+++ b/include/asm-ia64/machvec.h
@@ -26,7 +26,7 @@ typedef void ia64_mv_cpu_init_t (void);
 typedef void ia64_mv_irq_init_t (void);
 typedef void ia64_mv_send_ipi_t (int, int, int, int);
 typedef void ia64_mv_timer_interrupt_t (int, void *, struct pt_regs *);
-typedef void ia64_mv_global_tlb_purge_t (unsigned long, unsigned long, unsigned long);
+typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long);
 typedef void ia64_mv_tlb_migrate_finish_t (struct mm_struct *);
 typedef unsigned int ia64_mv_local_vector_to_irq (u8);
 typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *);
diff --git a/include/asm-ia64/machvec_hpzx1.h b/include/asm-ia64/machvec_hpzx1.h
index daafe504c5f4..e90daf9ce340 100644
--- a/include/asm-ia64/machvec_hpzx1.h
+++ b/include/asm-ia64/machvec_hpzx1.h
@@ -1,8 +1,7 @@
 #ifndef _ASM_IA64_MACHVEC_HPZX1_h
 #define _ASM_IA64_MACHVEC_HPZX1_h
-extern ia64_mv_setup_t dig_setup;
+extern ia64_mv_setup_t                  dig_setup;
-extern ia64_mv_setup_t                  sba_setup;
 extern ia64_mv_dma_alloc_coherent       sba_alloc_coherent;
 extern ia64_mv_dma_free_coherent        sba_free_coherent;
 extern ia64_mv_dma_map_single           sba_map_single;
@@ -19,15 +18,15 @@ extern ia64_mv_dma_mapping_error	sba_dma_mapping_error;
 * platform's machvec structure.  When compiling a non-generic kernel,
 * the macros are used directly.
 */
-#define platform_name                   "hpzx1"
+#define platform_name                           "hpzx1"
-#define platform_setup                  sba_setup
+#define platform_setup                          dig_setup
-#define platform_dma_init               machvec_noop
+#define platform_dma_init                       machvec_noop
-#define platform_dma_alloc_coherent     sba_alloc_coherent
+#define platform_dma_alloc_coherent             sba_alloc_coherent
-#define platform_dma_free_coherent      sba_free_coherent
+#define platform_dma_free_coherent              sba_free_coherent
-#define platform_dma_map_single         sba_map_single
+#define platform_dma_map_single                 sba_map_single
-#define platform_dma_unmap_single       sba_unmap_single
+#define platform_dma_unmap_single               sba_unmap_single
-#define platform_dma_map_sg             sba_map_sg
+#define platform_dma_map_sg                     sba_map_sg
-#define platform_dma_unmap_sg           sba_unmap_sg
+#define platform_dma_unmap_sg                   sba_unmap_sg
 #define platform_dma_sync_single_for_cpu        machvec_dma_sync_single
 #define platform_dma_sync_sg_for_cpu            machvec_dma_sync_sg
 #define platform_dma_sync_single_for_device     machvec_dma_sync_single
diff --git a/include/asm-ia64/machvec_hpzx1_swiotlb.h b/include/asm-ia64/machvec_hpzx1_swiotlb.h
index 9924b1b00a6c..f00a34a148ff 100644
--- a/include/asm-ia64/machvec_hpzx1_swiotlb.h
+++ b/include/asm-ia64/machvec_hpzx1_swiotlb.h
@@ -2,7 +2,6 @@
 #define _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
 extern ia64_mv_setup_t                          dig_setup;
-extern ia64_mv_dma_init                         hwsw_init;
 extern ia64_mv_dma_alloc_coherent               hwsw_alloc_coherent;
 extern ia64_mv_dma_free_coherent                hwsw_free_coherent;
 extern ia64_mv_dma_map_single                   hwsw_map_single;
@@ -26,7 +25,7 @@ extern ia64_mv_dma_sync_sg_for_device		hwsw_sync_sg_for_device;
 #define platform_name                           "hpzx1_swiotlb"
 #define platform_setup                          dig_setup
-#define platform_dma_init                       hwsw_init
+#define platform_dma_init                       machvec_noop
 #define platform_dma_alloc_coherent             hwsw_alloc_coherent
 #define platform_dma_free_coherent              hwsw_free_coherent
 #define platform_dma_map_single                 hwsw_map_single
diff --git a/include/asm-ia64/meminit.h b/include/asm-ia64/meminit.h
index 1590dc65b30b..46501b01a5c5 100644
--- a/include/asm-ia64/meminit.h
+++ b/include/asm-ia64/meminit.h
@@ -16,10 +16,11 @@
 *      - initrd (optional)
 *      - command line string
 *      - kernel code & data
+ *      - Kernel memory map built from EFI memory map
 *
 * More could be added if necessary
 */
-#define IA64_MAX_RSVD_REGIONS 5
+#define IA64_MAX_RSVD_REGIONS 6
 struct rsvd_region {
        unsigned long start;    /* virtual address of beginning of element */
@@ -33,6 +34,7 @@ extern void find_memory (void);
 extern void reserve_memory (void);
 extern void find_initrd (void);
 extern int filter_rsvd_memory (unsigned long start, unsigned long end, void *arg);
+extern void efi_memmap_init(unsigned long *, unsigned long *);
 /*
 * For rounding an address to the next IA64_GRANULE_SIZE or order
@@ -41,7 +43,7 @@ extern int filter_rsvd_memory (unsigned long start, unsigned long end, void *arg
 #define GRANULEROUNDUP(n)       (((n)+IA64_GRANULE_SIZE-1) & ~(IA64_GRANULE_SIZE-1))
 #define ORDERROUNDDOWN(n)       ((n) & ~((PAGE_SIZE<<MAX_ORDER)-1))
-#ifdef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_NUMA
  extern void call_pernode_memory (unsigned long start, unsigned long len, void *func);
 #else
 # define call_pernode_memory(start, len, func)  (*func)(start, len, 0)
diff --git a/include/asm-ia64/mmzone.h b/include/asm-ia64/mmzone.h
index d32f51e3d6c2..34efe88eb849 100644
--- a/include/asm-ia64/mmzone.h
+++ b/include/asm-ia64/mmzone.h
@@ -15,7 +15,7 @@
 #include <asm/page.h>
 #include <asm/meminit.h>
-#ifdef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_NUMA
 static inline int pfn_to_nid(unsigned long pfn)
 {
@@ -31,6 +31,10 @@ static inline int pfn_to_nid(unsigned long pfn)
 #endif
 }
+#ifdef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
+extern int early_pfn_to_nid(unsigned long pfn);
+#endif
 #ifdef CONFIG_IA64_DIG /* DIG systems are small */
 # define MAX_PHYSNODE_ID        8
 # define NR_NODE_MEMBLKS        (MAX_NUMNODES * 8)
@@ -39,8 +43,8 @@ static inline int pfn_to_nid(unsigned long pfn)
 # define NR_NODE_MEMBLKS        (MAX_NUMNODES * 4)
 #endif
-#else /* CONFIG_DISCONTIGMEM */
+#else /* CONFIG_NUMA */
 # define NR_NODE_MEMBLKS        (MAX_NUMNODES * 4)
-#endif /* CONFIG_DISCONTIGMEM */
+#endif /* CONFIG_NUMA */
 #endif /* _ASM_IA64_MMZONE_H */
diff --git a/include/asm-ia64/nodedata.h b/include/asm-ia64/nodedata.h
index 6b0f3ed89b7e..9978c7ce7549 100644
--- a/include/asm-ia64/nodedata.h
+++ b/include/asm-ia64/nodedata.h
@@ -17,7 +17,7 @@
 #include <asm/percpu.h>
 #include <asm/mmzone.h>
-#ifdef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_NUMA
 /*
 * Node Data. One of these structures is located on each node of a NUMA system.
@@ -47,6 +47,6 @@ struct ia64_node_data {
 */
 #define NODE_DATA(nid)          (local_node_data->pg_data_ptrs[nid])
-#endif /* CONFIG_DISCONTIGMEM */
+#endif /* CONFIG_NUMA */
 #endif /* _ASM_IA64_NODEDATA_H */
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
index 9edffad8c28b..ef436b9d06ad 100644
--- a/include/asm-ia64/page.h
+++ b/include/asm-ia64/page.h
@@ -102,15 +102,15 @@ do {						\
 #ifdef CONFIG_VIRTUAL_MEM_MAP
 extern int ia64_pfn_valid (unsigned long pfn);
-#else
+#elif defined(CONFIG_FLATMEM)
 # define ia64_pfn_valid(pfn) 1
 #endif
-#ifndef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_FLATMEM
 # define pfn_valid(pfn)         (((pfn) < max_mapnr) && ia64_pfn_valid(pfn))
 # define page_to_pfn(page)      ((unsigned long) (page - mem_map))
 # define pfn_to_page(pfn)       (mem_map + (pfn))
-#else
+#elif defined(CONFIG_DISCONTIGMEM)
 extern struct page *vmem_map;
 extern unsigned long max_low_pfn;
 # define pfn_valid(pfn)         (((pfn) < max_low_pfn) && ia64_pfn_valid(pfn))
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
index 3339c7b55a6f..21e32a06bc82 100644
--- a/include/asm-ia64/pgtable.h
+++ b/include/asm-ia64/pgtable.h
@@ -236,9 +236,6 @@ ia64_phys_addr_valid (unsigned long addr)
 #define pte_modify(_pte, newprot) \
        (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
-#define page_pte_prot(page,prot)        mk_pte(page, prot)
-#define page_pte(page)                  page_pte_prot(page, __pgprot(0))
 #define pte_none(pte)                   (!pte_val(pte))
 #define pte_present(pte)                (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
 #define pte_clear(mm,addr,pte)          (pte_val(*(pte)) = 0UL)
diff --git a/include/asm-ia64/rwsem.h b/include/asm-ia64/rwsem.h
index e18b5ab0cb75..1327c91ea39c 100644
--- a/include/asm-ia64/rwsem.h
+++ b/include/asm-ia64/rwsem.h
@@ -186,4 +186,9 @@ __downgrade_write (struct rw_semaphore *sem)
 #define rwsem_atomic_add(delta, sem)    atomic64_add(delta, (atomic64_t *)(&(sem)->count))
 #define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count))
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
 #endif /* _ASM_IA64_RWSEM_H */
diff --git a/include/asm-ia64/semaphore.h b/include/asm-ia64/semaphore.h
index 3a2f0f3f78f3..bb8906285fab 100644
--- a/include/asm-ia64/semaphore.h
+++ b/include/asm-ia64/semaphore.h
@@ -24,8 +24,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name)       __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count)                                 \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name, count)
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
index ab827d298569..1a3831c04af6 100644
--- a/include/asm-ia64/sn/arch.h
+++ b/include/asm-ia64/sn/arch.h
@@ -18,6 +18,32 @@
 #include <asm/sn/sn_cpuid.h>
 /*
+ * This is the maximum number of NUMALINK nodes that can be part of a single
+ * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
+ * remote partitions are NOT included in this number.
+ * The number of compact nodes cannot exceed size of a coherency domain.
+ * The purpose of this define is to specify a node count that includes
+ * all C/M/TIO nodes in an SSI system.
+ *
+ * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
+ *
+ *      Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
+ *      to ACPI3.0, this limit will be removed. The notion of "compact nodes"
+ *      should be deleted and TIOs should be included in MAX_NUMNODES.
+ */
+#define MAX_COMPACT_NODES       512
+/*
+ * Maximum number of nodes in all partitions and in all coherency domains.
+ * This is the total number of nodes accessible in the numalink fabric. It
+ * includes all C & M bricks, plus all TIOs.
+ *
+ * This value is also the value of the maximum number of NASIDs in the numalink
+ * fabric.
+ */
+#define MAX_NUMALINK_NODES      16384
+/*
 * The following defines attributes of the HUB chip. These attributes are
 * frequently referenced. They are kept in the per-cpu data areas of each cpu.
 * They are kept together in a struct to minimize cache misses.
@@ -41,15 +67,6 @@ DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
 /*
- * This is the maximum number of nodes that can be part of a kernel.
- * Effectively, it's the maximum number of compact node ids (cnodeid_t).
- * This is not necessarily the same as MAX_NASIDS.
- */
-#define MAX_COMPACT_NODES       2048
-#define CPUS_PER_NODE           4
-/*
 * Compact node ID to nasid mappings kept in the per-cpu data areas of each
 * cpu.
 */
@@ -57,7 +74,6 @@ DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_NUMNODES]);
 #define sn_cnodeid_to_nasid     (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
 extern u8 sn_partition_id;
 extern u8 sn_system_size;
 extern u8 sn_sharing_domain_size;
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h
index 42209733f6b1..41c73a735628 100644
--- a/include/asm-ia64/sn/io.h
+++ b/include/asm-ia64/sn/io.h
@@ -14,7 +14,7 @@
 extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
 extern void __sn_mmiowb(void); /* Forward definition */
-extern int numionodes;
+extern int num_cnodes;
 #define __sn_mf_a()   ia64_mfa()
@@ -36,6 +36,15 @@ extern void sn_dma_flush(unsigned long);
 #define __sn_readq_relaxed ___sn_readq_relaxed
 /*
+ * Convenience macros for setting/clearing bits using the above accessors
+ */
+#define __sn_setq_relaxed(addr, val) \
+        writeq((__sn_readq_relaxed(addr) | (val)), (addr))
+#define __sn_clrq_relaxed(addr, val) \
+        writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
+/*
 * The following routines are SN Platform specific, called when
 * a reference is made to inX/outX set macros.  SN Platform
 * inX set of macros ensures that Posted DMA writes on the
diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h
index 9f920c70a62a..bcbf209d63be 100644
--- a/include/asm-ia64/sn/klconfig.h
+++ b/include/asm-ia64/sn/klconfig.h
@@ -208,19 +208,6 @@ typedef struct lboard_s {
        klconf_off_t    brd_next_same;    /* Next BOARD with same nasid */
 } lboard_t;
-#define KLCF_NUM_COMPS(_brd)    ((_brd)->brd_numcompts)
-#define NODE_OFFSET_TO_KLINFO(n,off)    ((klinfo_t*) TO_NODE_CAC(n,off))
-#define KLCF_NEXT(_brd)         \
-        ((_brd)->brd_next_same ?     \
-         (NODE_OFFSET_TO_LBOARD((_brd)->brd_next_same_host, (_brd)->brd_next_same)): NULL)
-#define KLCF_NEXT_ANY(_brd)         \
-        ((_brd)->brd_next_any ?     \
-         (NODE_OFFSET_TO_LBOARD(NASID_GET(_brd), (_brd)->brd_next_any)): NULL)
-#define KLCF_COMP(_brd, _ndx)   \
-                ((((_brd)->brd_compts[(_ndx)]) == 0) ? 0 : \
-                        (NODE_OFFSET_TO_KLINFO(NASID_GET(_brd), (_brd)->brd_compts[(_ndx)])))
 /*
 * Generic info structure. This stores common info about a 
 * component.
@@ -249,24 +236,11 @@ typedef struct klinfo_s {                  /* Generic info */
 } klinfo_t ;
-static inline lboard_t *find_lboard_any(lboard_t * start, unsigned char brd_type)
+static inline lboard_t *find_lboard_next(lboard_t * brd)
 {
-        /* Search all boards stored on this node. */
+        if (brd && brd->brd_next_any)
+                return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
-        while (start) {
+        return NULL;
-                if (start->brd_type == brd_type)
-                        return start;
-                start = KLCF_NEXT_ANY(start);
-        }
-        /* Didn't find it. */
-        return (lboard_t *) NULL;
 }
-/* external declarations of Linux kernel functions. */
-extern lboard_t *root_lboard[];
-extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
-extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
 #endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 2e5f0aa38889..e3b819110d47 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -35,4 +35,16 @@
 #define L1_BRICKTYPE_ATHENA     0x2b            /* + */
 #define L1_BRICKTYPE_DAYTONA    0x7a            /* z */
+/* board type response codes */
+#define L1_BOARDTYPE_IP69       0x0100          /* CA */
+#define L1_BOARDTYPE_IP63       0x0200          /* CB */
+#define L1_BOARDTYPE_BASEIO     0x0300          /* IB */
+#define L1_BOARDTYPE_PCIE2SLOT  0x0400          /* IC */
+#define L1_BOARDTYPE_PCIX3SLOT  0x0500          /* ID */
+#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600       /* IE */
+#define L1_BOARDTYPE_ABACUS     0x0700          /* AB */
+#define L1_BOARDTYPE_DAYTONA    0x0800          /* AD */
+#define L1_BOARDTYPE_INVAL      (-1)            /* invalid brick type */
 #endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
index 47bb8100fd00..6f6d69e39ff5 100644
--- a/include/asm-ia64/sn/nodepda.h
+++ b/include/asm-ia64/sn/nodepda.h
@@ -55,7 +55,6 @@ struct nodepda_s {
         */
        struct phys_cpuid       phys_cpuid[NR_CPUS];
        spinlock_t              ptc_lock ____cacheline_aligned_in_smp;
-        spinlock_t              bist_lock;
 };
 typedef struct nodepda_s nodepda_t;
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
index d2c1d34dcce4..749deb2ca6c1 100644
--- a/include/asm-ia64/sn/sn_cpuid.h
+++ b/include/asm-ia64/sn/sn_cpuid.h
@@ -105,7 +105,6 @@ extern short physical_node_map[];	/* indexed by nasid to get cnode */
 #define cpuid_to_nasid(cpuid)           (sn_nodepda->phys_cpuid[cpuid].nasid)
 #define cpuid_to_subnode(cpuid)         (sn_nodepda->phys_cpuid[cpuid].subnode)
 #define cpuid_to_slice(cpuid)           (sn_nodepda->phys_cpuid[cpuid].slice)
-#define cpuid_to_cnodeid(cpuid)         (physical_node_map[cpuid_to_nasid(cpuid)])
 /*
@@ -113,8 +112,6 @@ extern short physical_node_map[];	/* indexed by nasid to get cnode */
 * of potentially large tables.
 */
 extern int nasid_slice_to_cpuid(int, int);
-#define nasid_slice_to_cpu_physical_id(nasid, slice)                    \
-        cpu_physical_id(nasid_slice_to_cpuid(nasid, slice))
 /*
 * cnodeid_to_nasid - convert a cnodeid to a NASID
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index fea35b33d4e4..3f7564dc0aa9 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -47,6 +47,7 @@
 #define  SN_SAL_CONSOLE_PUTB                       0x02000028
 #define  SN_SAL_CONSOLE_XMIT_CHARS                 0x0200002a
 #define  SN_SAL_CONSOLE_READC                      0x0200002b
+#define  SN_SAL_SYSCTL_OP                          0x02000030
 #define  SN_SAL_SYSCTL_MODID_GET                   0x02000031
 #define  SN_SAL_SYSCTL_GET                         0x02000032
 #define  SN_SAL_SYSCTL_IOBRICK_MODULE_GET          0x02000033
@@ -67,7 +68,7 @@
 #define  SN_SAL_IOIF_INTERRUPT                     0x0200004a
 #define  SN_SAL_HWPERF_OP                          0x02000050   // lock
 #define  SN_SAL_IOIF_ERROR_INTERRUPT               0x02000051
+#define  SN_SAL_IOIF_PCI_SAFE                      0x02000052
 #define  SN_SAL_IOIF_SLOT_ENABLE                   0x02000053
 #define  SN_SAL_IOIF_SLOT_DISABLE                  0x02000054
 #define  SN_SAL_IOIF_GET_HUBDEV_INFO               0x02000055
@@ -101,6 +102,13 @@
 #define SAL_INTR_FREE           2
 /*
+ * operations available on the generic SN_SAL_SYSCTL_OP
+ * runtime service
+ */
+#define SAL_SYSCTL_OP_IOBOARD           0x0001  /*  retrieve board type */
+#define SAL_SYSCTL_OP_TIO_JLCK_RST      0x0002  /* issue TIO clock reset */
+/*
 * IRouter (i.e. generalized system controller) operations
 */
 #define SAL_IROUTER_OPEN        0       /* open a subchannel */
@@ -198,26 +206,16 @@ ia64_sn_get_master_baseio_nasid(void)
        return ret_stuff.v0;
 }
-static inline char *
+static inline void *
 ia64_sn_get_klconfig_addr(nasid_t nasid)
 {
        struct ia64_sal_retval ret_stuff;
-        int cnodeid;
-        cnodeid = nasid_to_cnodeid(nasid);
        ret_stuff.status = 0;
        ret_stuff.v0 = 0;
        ret_stuff.v1 = 0;
        ret_stuff.v2 = 0;
        SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
-        /*
-         * We should panic if a valid cnode nasid does not produce
-         * a klconfig address.
-         */
-        if (ret_stuff.status != 0) {
-                panic("ia64_sn_get_klconfig_addr: Returned error %lx\n", ret_stuff.status);
-        }
        return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
 }
@@ -694,12 +692,10 @@ sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
        unsigned long irq_flags;
        cnodeid = nasid_to_cnodeid(get_node_number(paddr));
-        // spin_lock(&NODEPDA(cnodeid)->bist_lock);
        local_irq_save(irq_flags);
        ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
                                (u64)nasid_array, perms, 0, 0, 0);
        local_irq_restore(irq_flags);
-        // spin_unlock(&NODEPDA(cnodeid)->bist_lock);
        return ret_stuff.status;
 }
 #define SN_MEMPROT_ACCESS_CLASS_0               0x14a080
@@ -873,6 +869,41 @@ ia64_sn_sysctl_event_init(nasid_t nasid)
        return (int) rv.v0;
 }
+/*
+ * Ask the system controller on the specified nasid to reset
+ * the CX corelet clock.  Only valid on TIO nodes.
+ */
+static inline int
+ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
+                        nasid, 0, 0, 0, 0, 0);
+        if (rv.status != 0)
+                return (int)rv.status;
+        if (rv.v0 != 0)
+                return (int)rv.v0;
+        return 0;
+}
+/*
+ * Get the associated ioboard type for a given nasid.
+ */
+static inline int
+ia64_sn_sysctl_ioboard_get(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
+                        nasid, 0, 0, 0, 0, 0);
+        if (rv.v0 != 0)
+                return (int)rv.v0;
+        if (rv.v1 != 0)
+                return (int)rv.v1;
+        return 0;
+}
 /**
 * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
 * @nasid: NASID of node to read
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index 5ccec608d325..b532ef6148ed 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -182,11 +182,11 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
                         * touch every CL aligned GART entry.
                         */
-                        ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
+                        __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
-                        ca_base->ca_control2 |= CA_GART_FLUSH_TLB;
+                        __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
-                        ca_base->ca_control2 |=
+                        __sn_setq_relaxed(&ca_base->ca_control2,
-                            (0x2ull << CA_GART_MEM_PARAM_SHFT);
+                            (0x2ull << CA_GART_MEM_PARAM_SHFT));
-                        tmp = ca_base->ca_control2;
+                        tmp = __sn_readq_relaxed(&ca_base->ca_control2);
                }
                return;
@@ -196,8 +196,8 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
         * Gart in uncached mode ... need an explicit flush.
         */
-        ca_base->ca_control2 |= CA_GART_FLUSH_TLB;
+        __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
-        tmp = ca_base->ca_control2;
+        tmp = __sn_readq_relaxed(&ca_base->ca_control2);
 }
 extern uint32_t tioca_gart_found;
diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h
index c5447a504509..5699e75e5024 100644
--- a/include/asm-ia64/sn/tiocx.h
+++ b/include/asm-ia64/sn/tiocx.h
@@ -19,6 +19,7 @@ struct cx_id_s {
 struct cx_dev {
        struct cx_id_s cx_id;
+        int bt;                         /* board/blade type */
        void *soft;                     /* driver specific */
        struct hubdev_info *hubdev;
        struct device dev;
@@ -59,7 +60,7 @@ struct cx_drv {
 extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
 extern void tiocx_irq_free(struct sn_irq_info *);
 extern int cx_device_unregister(struct cx_dev *);
-extern int cx_device_register(nasid_t, int, int, struct hubdev_info *);
+extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
 extern int cx_driver_unregister(struct cx_drv *);
 extern int cx_driver_register(struct cx_drv *);
 extern uint64_t tiocx_dma_addr(uint64_t addr);
diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h
index 1df1c9f61a65..49faf8f26430 100644
--- a/include/asm-ia64/sn/xp.h
+++ b/include/asm-ia64/sn/xp.h
@@ -49,7 +49,7 @@
 * C-brick nasids, thus the need for bitmaps which don't account for
 * odd-numbered (non C-brick) nasids.
 */
-#define XP_MAX_PHYSNODE_ID      (MAX_PHYSNODE_ID / 2)
+#define XP_MAX_PHYSNODE_ID      (MAX_NUMALINK_NODES / 2)
 #define XP_NASID_MASK_BYTES     ((XP_MAX_PHYSNODE_ID + 7) / 8)
 #define XP_NASID_MASK_WORDS     ((XP_MAX_PHYSNODE_ID + 63) / 64)
@@ -217,7 +217,17 @@ enum xpc_retval {
        xpcInvalidPartid,       /* 42: invalid partition ID */
        xpcLocalPartid,         /* 43: local partition ID */
-        xpcUnknownReason        /* 44: unknown reason -- must be last in list */
+        xpcOtherGoingDown,      /* 44: other side going down, reason unknown */
+        xpcSystemGoingDown,     /* 45: system is going down, reason unknown */
+        xpcSystemHalt,          /* 46: system is being halted */
+        xpcSystemReboot,        /* 47: system is being rebooted */
+        xpcSystemPoweroff,      /* 48: system is being powered off */
+        xpcDisconnecting,       /* 49: channel disconnecting (closing) */
+        xpcOpenCloseError,      /* 50: channel open/close protocol error */
+        xpcUnknownReason        /* 51: unknown reason -- must be last in list */
 };
@@ -342,7 +352,7 @@ typedef void (*xpc_notify_func)(enum xpc_retval reason, partid_t partid,
 *
 * The 'func' field points to the function to call when aynchronous
 * notification is required for such events as: a connection established/lost,
- * or an incomming message received, or an error condition encountered. A
+ * or an incoming message received, or an error condition encountered. A
 * non-NULL 'func' field indicates that there is an active registration for
 * the channel.
 */
diff --git a/include/asm-ia64/sparsemem.h b/include/asm-ia64/sparsemem.h
new file mode 100644
index 000000000000..67a7c40ec27f
--- /dev/null
+++ b/include/asm-ia64/sparsemem.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_IA64_SPARSEMEM_H
+#define _ASM_IA64_SPARSEMEM_H
+#ifdef CONFIG_SPARSEMEM
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+#define SECTION_SIZE_BITS       (30)
+#define MAX_PHYSMEM_BITS        (50)
+#ifdef CONFIG_FORCE_MAX_ZONEORDER
+#if ((CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS)
+#undef SECTION_SIZE_BITS
+#define SECTION_SIZE_BITS (CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT)
+#endif
+#endif
+#endif /* CONFIG_SPARSEMEM */
+#endif /* _ASM_IA64_SPARSEMEM_H */
diff --git a/include/asm-ia64/tlb.h b/include/asm-ia64/tlb.h
index 3a9a6d1be75c..834370b9dea1 100644
--- a/include/asm-ia64/tlb.h
+++ b/include/asm-ia64/tlb.h
@@ -60,7 +60,6 @@ struct mmu_gather {
        unsigned int            nr;             /* == ~0U => fast mode */
        unsigned char           fullmm;         /* non-zero means full mm flush */
        unsigned char           need_flush;     /* really unmapped some PTEs? */
-        unsigned long           freed;          /* number of pages freed */
        unsigned long           start_addr;
        unsigned long           end_addr;
        struct page             *pages[FREE_PTE_NR];
@@ -129,7 +128,7 @@ ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long e
 static inline struct mmu_gather *
 tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *tlb = &__get_cpu_var(mmu_gathers);
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
        tlb->mm = mm;
        /*
@@ -147,25 +146,17 @@ tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
         */
        tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
        tlb->fullmm = full_mm_flush;
-        tlb->freed = 0;
        tlb->start_addr = ~0UL;
        return tlb;
 }
 /*
 * Called at the end of the shootdown operation to free up any resources that were
- * collected.  The page table lock is still held at this point.
+ * collected.
 */
 static inline void
 tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        unsigned long freed = tlb->freed;
-        struct mm_struct *mm = tlb->mm;
-        unsigned long rss = get_mm_counter(mm, rss);
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
        /*
         * Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and
         * tlb->end_addr.
@@ -174,12 +165,8 @@ tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
        /* keep the page table cache within bounds */
        check_pgt_cache();
-}
-static inline unsigned int
+        put_cpu_var(mmu_gathers);
-tlb_is_full_mm(struct mmu_gather *tlb)
-{
-     return tlb->fullmm;
 }
 /*
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
index 3a0c69524656..6d96a67439be 100644
--- a/include/asm-ia64/unistd.h
+++ b/include/asm-ia64/unistd.h
@@ -383,8 +383,6 @@ struct sigaction;
 long sys_execve(char __user *filename, char __user * __user *argv,
                           char __user * __user *envp, struct pt_regs *regs);
 asmlinkage long sys_pipe(void);
-asmlinkage long sys_ptrace(long request, pid_t pid,
-                           unsigned long addr, unsigned long data);
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
                                 struct sigaction __user *oact,
diff --git a/include/asm-m32r/mmzone.h b/include/asm-m32r/mmzone.h
index d58878ec899e..adc7970a77ec 100644
--- a/include/asm-m32r/mmzone.h
+++ b/include/asm-m32r/mmzone.h
@@ -21,12 +21,6 @@ extern struct pglist_data *node_data[];
        __pgdat->node_start_pfn + __pgdat->node_spanned_pages - 1;      \
 })
-#define local_mapnr(kvaddr)                                             \
-({                                                                      \
-        unsigned long __pfn = __pa(kvaddr) >> PAGE_SHIFT;               \
-        (__pfn - node_start_pfn(pfn_to_nid(__pfn)));                    \
-})
 #define pfn_to_page(pfn)                                                \
 ({                                                                      \
        unsigned long __pfn = pfn;                                      \
diff --git a/include/asm-m32r/pgtable.h b/include/asm-m32r/pgtable.h
index 388e5ee9fa27..1cd5fd4a5b2c 100644
--- a/include/asm-m32r/pgtable.h
+++ b/include/asm-m32r/pgtable.h
@@ -324,8 +324,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
        return pte;
 }
-#define page_pte(page)  page_pte_prot(page, __pgprot(0))
 /*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
diff --git a/include/asm-m32r/semaphore.h b/include/asm-m32r/semaphore.h
index 53e3c60f21ec..bf447c52a0a1 100644
--- a/include/asm-m32r/semaphore.h
+++ b/include/asm-m32r/semaphore.h
@@ -32,9 +32,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-m32r/thread_info.h b/include/asm-m32r/thread_info.h
index 7a6be7727a92..0f589363f619 100644
--- a/include/asm-m32r/thread_info.h
+++ b/include/asm-m32r/thread_info.h
@@ -95,7 +95,7 @@ static inline struct thread_info *current_thread_info(void)
 }
 /* thread information allocation */
-#if CONFIG_DEBUG_STACK_USAGE
+#ifdef CONFIG_DEBUG_STACK_USAGE
 #define alloc_thread_info(tsk)                                  \
        ({                                                      \
                struct thread_info *ret;                        \
diff --git a/include/asm-m32r/unistd.h b/include/asm-m32r/unistd.h
index 8552d8f45ab1..ac399e1f7bc0 100644
--- a/include/asm-m32r/unistd.h
+++ b/include/asm-m32r/unistd.h
@@ -452,7 +452,6 @@ asmlinkage int sys_clone(struct pt_regs regs);
 asmlinkage int sys_fork(struct pt_regs regs);
 asmlinkage int sys_vfork(struct pt_regs regs);
 asmlinkage int sys_pipe(unsigned long __user *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                 const struct sigaction __user *act,
diff --git a/include/asm-m68k/semaphore.h b/include/asm-m68k/semaphore.h
index ab94cf3ed447..fd4c7cc3d3be 100644
--- a/include/asm-m68k/semaphore.h
+++ b/include/asm-m68k/semaphore.h
@@ -36,9 +36,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-m68k/sun3xflop.h b/include/asm-m68k/sun3xflop.h
index 1ed3b787ee05..fda1eccf10aa 100644
--- a/include/asm-m68k/sun3xflop.h
+++ b/include/asm-m68k/sun3xflop.h
@@ -27,10 +27,8 @@
 /* We don't need no stinkin' I/O port allocation crap. */
 #undef release_region
-#undef check_region
 #undef request_region
 #define release_region(X, Y)    do { } while(0)
-#define check_region(X, Y)      (0)
 #define request_region(X, Y, Z) (1)
 struct sun3xflop_private {
diff --git a/include/asm-m68k/unistd.h b/include/asm-m68k/unistd.h
index cbabde4f8a45..c2554bcd1747 100644
--- a/include/asm-m68k/unistd.h
+++ b/include/asm-m68k/unistd.h
@@ -444,7 +444,6 @@ asmlinkage long sys_mmap2(
                        unsigned long fd, unsigned long pgoff);
 asmlinkage int sys_execve(char *name, char **argv, char **envp);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct pt_regs;
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
diff --git a/include/asm-m68knommu/anchor.h b/include/asm-m68knommu/anchor.h
index 75390e0b40c9..871c0d5cfc3d 100644
--- a/include/asm-m68knommu/anchor.h
+++ b/include/asm-m68knommu/anchor.h
@@ -14,7 +14,7 @@
 /*
 *      Define basic addressing info.
 */
-#if defined(CONFIG_MOTOROLA) && defined(CONFIG_M5407)
+#if defined(CONFIG_M5407C3)
 #define COMEM_BASE      0xFFFF0000      /* Base of CO-MEM address space */
 #define COMEM_IRQ       25              /* IRQ of anchor part */
 #else
@@ -96,7 +96,7 @@
 *      The PCI bus will be limited in what slots will actually be used.
 *      Define valid device numbers for different boards.
 */
-#if defined(CONFIG_MOTOROLA) && defined(CONFIG_M5407)
+#if defined(CONFIG_M5407C3)
 #define COMEM_MINDEV    14              /* Minimum valid DEVICE */
 #define COMEM_MAXDEV    14              /* Maximum valid DEVICE */
 #define COMEM_BRIDGEDEV 15              /* Slot bridge is in */
diff --git a/include/asm-m68knommu/asm-offsets.h b/include/asm-m68knommu/asm-offsets.h
deleted file mode 100644
index 825f6e210f19..000000000000
--- a/include/asm-m68knommu/asm-offsets.h
+++ /dev/null
@@ -1,49 +0,0 @@
-#ifndef __ASM_OFFSETS_H__
-#define __ASM_OFFSETS_H__
-/*
- * DO NOT MODIFY.
- *
- * This file was generated by arch/m68knommu/Makefile
- *
- */
-#define TASK_STATE 0 /* offsetof(struct task_struct, state) */
-#define TASK_FLAGS 12 /* offsetof(struct task_struct, flags) */
-#define TASK_PTRACE 16 /* offsetof(struct task_struct, ptrace) */
-#define TASK_BLOCKED 922 /* offsetof(struct task_struct, blocked) */
-#define TASK_THREAD 772 /* offsetof(struct task_struct, thread) */
-#define TASK_THREAD_INFO 4 /* offsetof(struct task_struct, thread_info) */
-#define TASK_MM 92 /* offsetof(struct task_struct, mm) */
-#define TASK_ACTIVE_MM 96 /* offsetof(struct task_struct, active_mm) */
-#define CPUSTAT_SOFTIRQ_PENDING 0 /* offsetof(irq_cpustat_t, __softirq_pending) */
-#define THREAD_KSP 0 /* offsetof(struct thread_struct, ksp) */
-#define THREAD_USP 4 /* offsetof(struct thread_struct, usp) */
-#define THREAD_SR 8 /* offsetof(struct thread_struct, sr) */
-#define THREAD_FS 10 /* offsetof(struct thread_struct, fs) */
-#define THREAD_CRP 12 /* offsetof(struct thread_struct, crp) */
-#define THREAD_ESP0 20 /* offsetof(struct thread_struct, esp0) */
-#define THREAD_FPREG 24 /* offsetof(struct thread_struct, fp) */
-#define THREAD_FPCNTL 120 /* offsetof(struct thread_struct, fpcntl) */
-#define THREAD_FPSTATE 132 /* offsetof(struct thread_struct, fpstate) */
-#define PT_D0 32 /* offsetof(struct pt_regs, d0) */
-#define PT_ORIG_D0 36 /* offsetof(struct pt_regs, orig_d0) */
-#define PT_D1 0 /* offsetof(struct pt_regs, d1) */
-#define PT_D2 4 /* offsetof(struct pt_regs, d2) */
-#define PT_D3 8 /* offsetof(struct pt_regs, d3) */
-#define PT_D4 12 /* offsetof(struct pt_regs, d4) */
-#define PT_D5 16 /* offsetof(struct pt_regs, d5) */
-#define PT_A0 20 /* offsetof(struct pt_regs, a0) */
-#define PT_A1 24 /* offsetof(struct pt_regs, a1) */
-#define PT_A2 28 /* offsetof(struct pt_regs, a2) */
-#define PT_PC 48 /* offsetof(struct pt_regs, pc) */
-#define PT_SR 46 /* offsetof(struct pt_regs, sr) */
-#define PT_VECTOR 52 /* offsetof(struct pt_regs, pc) + 4 */
-#define STAT_IRQ 5140 /* offsetof(struct kernel_stat, irqs) */
-#define SIGSEGV 11 /* SIGSEGV */
-#define SEGV_MAPERR 196609 /* SEGV_MAPERR */
-#define SIGTRAP 5 /* SIGTRAP */
-#define TRAP_TRACE 196610 /* TRAP_TRACE */
-#define PT_PTRACED 1 /* PT_PTRACED */
-#define PT_DTRACE 2 /* PT_DTRACE */
-#endif
diff --git a/include/asm-m68knommu/atomic.h b/include/asm-m68knommu/atomic.h
index b1957fba083b..a83631ed8c8f 100644
--- a/include/asm-m68knommu/atomic.h
+++ b/include/asm-m68knommu/atomic.h
@@ -100,7 +100,7 @@ static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v)
 #define smp_mb__before_atomic_inc()    barrier()
 #define smp_mb__after_atomic_inc() barrier()
-extern __inline__ int atomic_add_return(int i, atomic_t * v)
+static inline int atomic_add_return(int i, atomic_t * v)
 {
        unsigned long temp, flags;
@@ -115,7 +115,7 @@ extern __inline__ int atomic_add_return(int i, atomic_t * v)
 #define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-extern __inline__ int atomic_sub_return(int i, atomic_t * v)
+static inline int atomic_sub_return(int i, atomic_t * v)
 {
        unsigned long temp, flags;
diff --git a/include/asm-m68knommu/coldfire.h b/include/asm-m68knommu/coldfire.h
index 1df3f666a28e..6190f77b1e6c 100644
--- a/include/asm-m68knommu/coldfire.h
+++ b/include/asm-m68knommu/coldfire.h
@@ -20,9 +20,14 @@
 */
 #define MCF_MBAR        0x10000000
 #define MCF_MBAR2       0x80000000
+#if defined(CONFIG_M520x)
+#define MCF_IPSBAR      0xFC000000
+#else
 #define MCF_IPSBAR      0x40000000
+#endif
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
+#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+    defined(CONFIG_M520x)
 #undef MCF_MBAR
 #define MCF_MBAR        MCF_IPSBAR
 #endif
@@ -78,7 +83,8 @@
 *      One some ColdFire family members the bus clock (used by internal
 *      peripherals) is not the same as the CPU clock.
 */
-#if defined(CONFIG_M523x) || defined(CONFIG_M5249) || defined(CONFIG_M527x)
+#if defined(CONFIG_M523x) || defined(CONFIG_M5249) || defined(CONFIG_M527x) || \
+    defined(CONFIG_M520x)
 #define MCF_BUSCLK      (MCF_CLK / 2)
 #else
 #define MCF_BUSCLK      MCF_CLK
diff --git a/include/asm-m68knommu/delay.h b/include/asm-m68knommu/delay.h
index e3a976254672..04a20fd051cf 100644
--- a/include/asm-m68knommu/delay.h
+++ b/include/asm-m68knommu/delay.h
@@ -8,7 +8,7 @@
 #include <asm/param.h>
-extern __inline__ void __delay(unsigned long loops)
+static inline void __delay(unsigned long loops)
 {
 #if defined(CONFIG_COLDFIRE)
        /* The coldfire runs this loop at significantly different speeds
@@ -48,7 +48,7 @@ extern __inline__ void __delay(unsigned long loops)
 extern unsigned long loops_per_jiffy;
-extern __inline__ void _udelay(unsigned long usecs)
+static inline void _udelay(unsigned long usecs)
 {
 #if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \
    defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \
diff --git a/include/asm-m68knommu/ide.h b/include/asm-m68knommu/ide.h
deleted file mode 100644
index b1cbf8bb9232..000000000000
--- a/include/asm-m68knommu/ide.h
+++ /dev/null
@@ -1,444 +0,0 @@
-/****************************************************************************/
-/*
- *  linux/include/asm-m68knommu/ide.h
- *
- *  Copyright (C) 1994-1996  Linus Torvalds & authors
- *      Copyright (C) 2001       Lineo Inc., davidm@uclinux.org
- */
-/****************************************************************************/
-#ifndef _M68KNOMMU_IDE_H
-#define _M68KNOMMU_IDE_H
-#ifdef __KERNEL__
-/****************************************************************************/
-#include <linux/config.h>
-#include <linux/interrupt.h>
-#include <asm/setup.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-/****************************************************************************/
-/*
- *      some coldfire specifics
- */
-#ifdef CONFIG_COLDFIRE
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-/*
- *      Save some space,  only have 1 interface
- */
-#define MAX_HWIFS                 1     /* we only have one interface for now */
-#ifdef CONFIG_SECUREEDGEMP3
-#define MCFSIM_LOCALCS    MCFSIM_CSCR4
-#else
-#define MCFSIM_LOCALCS    MCFSIM_CSCR6
-#endif
-#endif /* CONFIG_COLDFIRE */
-/****************************************************************************/
-/*
- *      Fix up things that may not have been provided
- */
-#ifndef MAX_HWIFS
-#define MAX_HWIFS       4       /* same as the other archs */
-#endif
-#undef SUPPORT_SLOW_DATA_PORTS
-#define SUPPORT_SLOW_DATA_PORTS 0
-#undef SUPPORT_VLB_SYNC
-#define SUPPORT_VLB_SYNC 0
-/* this definition is used only on startup .. */
-#undef HD_DATA
-#define HD_DATA NULL
-#define DBGIDE(fmt,a...)
-// #define      DBGIDE(fmt,a...) printk(fmt, ##a)
-#define IDE_INLINE __inline__
-// #define IDE_INLINE
-/****************************************************************************/
-typedef union {
-        unsigned all                    : 8;    /* all of the bits together */
-        struct {
-                unsigned bit7           : 1;    /* always 1 */
-                unsigned lba            : 1;    /* using LBA instead of CHS */
-                unsigned bit5           : 1;    /* always 1 */
-                unsigned unit           : 1;    /* drive select number, 0 or 1 */
-                unsigned head           : 4;    /* always zeros here */
-        } b;
-} select_t;
-/*
- *      our list of ports/irq's for different boards
- */
-static struct m68k_ide_defaults {
-        ide_ioreg_t     base;
-        int                     irq;
-} m68k_ide_defaults[MAX_HWIFS] = {
-#if defined(CONFIG_SECUREEDGEMP3)
-        { ((ide_ioreg_t)0x30800000), 29 },
-#elif defined(CONFIG_eLIA)
-        { ((ide_ioreg_t)0x30c00000), 29 },
-#else
-        { ((ide_ioreg_t)0x0), 0 }
-#endif
-};
-/****************************************************************************/
-static IDE_INLINE int ide_default_irq(ide_ioreg_t base)
-{
-        int i;
-        for (i = 0; i < MAX_HWIFS; i++)
-                if (m68k_ide_defaults[i].base == base)
-                        return(m68k_ide_defaults[i].irq);
-        return 0;
-}
-static IDE_INLINE ide_ioreg_t ide_default_io_base(int index)
-{
-        if (index >= 0 && index < MAX_HWIFS)
-                return(m68k_ide_defaults[index].base);
-        return 0;
-}
-/*
- * Set up a hw structure for a specified data port, control port and IRQ.
- * This should follow whatever the default interface uses.
- */
-static IDE_INLINE void ide_init_hwif_ports(
-        hw_regs_t *hw,
-        ide_ioreg_t data_port,
-        ide_ioreg_t ctrl_port,
-        int *irq)
-{
-        ide_ioreg_t reg = data_port;
-        int i;
-        for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
-                hw->io_ports[i] = reg;
-                reg += 1;
-        }
-        if (ctrl_port) {
-                hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
-        } else {
-                hw->io_ports[IDE_CONTROL_OFFSET] = data_port + 0xe;
-        }
-}
-#define ide_init_default_irq(base)      ide_default_irq(base)
-static IDE_INLINE int
-ide_request_irq(
-        unsigned int irq,
-        void (*handler)(int, void *, struct pt_regs *),
-        unsigned long flags,
-        const char *device,
-        void *dev_id)
-{
-#ifdef CONFIG_COLDFIRE
-        mcf_autovector(irq);
-#endif
-        return(request_irq(irq, handler, flags, device, dev_id));
-}
-static IDE_INLINE void
-ide_free_irq(unsigned int irq, void *dev_id)
-{
-        free_irq(irq, dev_id);
-}
-static IDE_INLINE int
-ide_check_region(ide_ioreg_t from, unsigned int extent)
-{
-        return 0;
-}
-static IDE_INLINE void
-ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name)
-{
-}
-static IDE_INLINE void
-ide_release_region(ide_ioreg_t from, unsigned int extent)
-{
-}
-static IDE_INLINE void
-ide_fix_driveid(struct hd_driveid *id)
-{
-#ifdef CONFIG_COLDFIRE
-        int i, n;
-        unsigned short *wp = (unsigned short *) id;
-        int avoid[] = {49, 51, 52, 59, -1 }; /* do not swap these words */
-        /* Need to byte swap shorts,  but not char fields */
-        for (i = n = 0; i < sizeof(*id) / sizeof(*wp); i++, wp++) {
-                if (avoid[n] == i) {
-                        n++;
-                        continue;
-                }
-                *wp = ((*wp & 0xff) << 8) | ((*wp >> 8) & 0xff);
-        }
-        /* have to word swap the one 32 bit field */
-        id->lba_capacity = ((id->lba_capacity & 0xffff) << 16) |
-                                ((id->lba_capacity >> 16) & 0xffff);
-#endif
-}
-static IDE_INLINE void
-ide_release_lock (int *ide_lock)
-{
-}
-static IDE_INLINE void
-ide_get_lock(
-        int *ide_lock,
-        void (*handler)(int, void *, struct pt_regs *),
-        void *data)
-{
-}
-#define ide_ack_intr(hwif) \
-        ((hwif)->hw.ack_intr ? (hwif)->hw.ack_intr(hwif) : 1)
-#define ide__sti()      __sti()
-/****************************************************************************/
-/*
- *      System specific IO requirements
- */
-#ifdef CONFIG_COLDFIRE
-#ifdef CONFIG_SECUREEDGEMP3
-/* Replace standard IO functions for funky mapping of MP3 board */
-#undef outb
-#undef outb_p
-#undef inb
-#undef inb_p
-#define outb(v, a)          ide_outb(v, (unsigned long) (a))
-#define outb_p(v, a)        ide_outb(v, (unsigned long) (a))
-#define inb(a)              ide_inb((unsigned long) (a))
-#define inb_p(a)            ide_inb((unsigned long) (a))
-#define ADDR8_PTR(addr)         (((addr) & 0x1) ? (0x8000 + (addr) - 1) : (addr))
-#define ADDR16_PTR(addr)        (addr)
-#define ADDR32_PTR(addr)        (addr)
-#define SWAP8(w)                        ((((w) & 0xffff) << 8) | (((w) & 0xffff) >> 8))
-#define SWAP16(w)                       (w)
-#define SWAP32(w)                       (w)
-static IDE_INLINE void
-ide_outb(unsigned int val, unsigned int addr)
-{
-        volatile unsigned short *rp;
-        DBGIDE("%s(val=%x,addr=%x)\n", __FUNCTION__, val, addr);
-        rp = (volatile unsigned short *) ADDR8_PTR(addr);
-        *rp = SWAP8(val);
-}
-static IDE_INLINE int
-ide_inb(unsigned int addr)
-{
-        volatile unsigned short *rp, val;
-        DBGIDE("%s(addr=%x)\n", __FUNCTION__, addr);
-        rp = (volatile unsigned short *) ADDR8_PTR(addr);
-        val = *rp;
-        return(SWAP8(val));
-}
-static IDE_INLINE void
-ide_outw(unsigned int val, unsigned int addr)
-{
-        volatile unsigned short *rp;
-        DBGIDE("%s(val=%x,addr=%x)\n", __FUNCTION__, val, addr);
-        rp = (volatile unsigned short *) ADDR16_PTR(addr);
-        *rp = SWAP16(val);
-}
-static IDE_INLINE void
-ide_outsw(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        volatile unsigned short *rp, val;
-        unsigned short          *buf;
-        DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len);
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) ADDR16_PTR(addr);
-        for (; (len > 0); len--) {
-                val = *buf++;
-                *rp = SWAP16(val);
-        }
-}
-static IDE_INLINE int
-ide_inw(unsigned int addr)
-{
-        volatile unsigned short *rp, val;
-        DBGIDE("%s(addr=%x)\n", __FUNCTION__, addr);
-        rp = (volatile unsigned short *) ADDR16_PTR(addr);
-        val = *rp;
-        return(SWAP16(val));
-}
-static IDE_INLINE void
-ide_insw(unsigned int addr, void *vbuf, unsigned long len)
-{
-        volatile unsigned short *rp;
-        unsigned short          w, *buf;
-        DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len);
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) ADDR16_PTR(addr);
-        for (; (len > 0); len--) {
-                w = *rp;
-                *buf++ = SWAP16(w);
-        }
-}
-static IDE_INLINE void
-ide_insl(unsigned int addr, void *vbuf, unsigned long len)
-{
-        volatile unsigned long *rp;
-        unsigned long          w, *buf;
-        DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len);
-        buf = (unsigned long *) vbuf;
-        rp = (volatile unsigned long *) ADDR32_PTR(addr);
-        for (; (len > 0); len--) {
-                w = *rp;
-                *buf++ = SWAP32(w);
-        }
-}
-static IDE_INLINE void
-ide_outsl(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        volatile unsigned long  *rp, val;
-        unsigned long           *buf;
-        DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len);
-        buf = (unsigned long *) vbuf;
-        rp = (volatile unsigned long *) ADDR32_PTR(addr);
-        for (; (len > 0); len--) {
-                val = *buf++;
-                *rp = SWAP32(val);
-        }
-}
-#elif CONFIG_eLIA
-/* 8/16 bit acesses are controlled by flicking bits in the CS register */
-#define ACCESS_MODE_16BIT()     \
-        *((volatile unsigned short *) (MCF_MBAR + MCFSIM_LOCALCS)) = 0x0080
-#define ACCESS_MODE_8BIT()      \
-        *((volatile unsigned short *) (MCF_MBAR + MCFSIM_LOCALCS)) = 0x0040
-static IDE_INLINE void
-ide_outw(unsigned int val, unsigned int addr)
-{
-        ACCESS_MODE_16BIT();
-        outw(val, addr);
-        ACCESS_MODE_8BIT();
-}
-static IDE_INLINE void
-ide_outsw(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        ACCESS_MODE_16BIT();
-        outsw(addr, vbuf, len);
-        ACCESS_MODE_8BIT();
-}
-static IDE_INLINE int
-ide_inw(unsigned int addr)
-{
-        int ret;
-        ACCESS_MODE_16BIT();
-        ret = inw(addr);
-        ACCESS_MODE_8BIT();
-        return(ret);
-}
-static IDE_INLINE void
-ide_insw(unsigned int addr, void *vbuf, unsigned long len)
-{
-        ACCESS_MODE_16BIT();
-        insw(addr, vbuf, len);
-        ACCESS_MODE_8BIT();
-}
-static IDE_INLINE void
-ide_insl(unsigned int addr, void *vbuf, unsigned long len)
-{
-        ACCESS_MODE_16BIT();
-        insl(addr, vbuf, len);
-        ACCESS_MODE_8BIT();
-}
-static IDE_INLINE void
-ide_outsl(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        ACCESS_MODE_16BIT();
-        outsl(addr, vbuf, len);
-        ACCESS_MODE_8BIT();
-}
-#endif /* CONFIG_SECUREEDGEMP3 */
-#undef outw
-#undef outw_p
-#undef outsw
-#undef inw
-#undef inw_p
-#undef insw
-#undef insl
-#undef outsl
-#define outw(v, a)           ide_outw(v, (unsigned long) (a))
-#define outw_p(v, a)     ide_outw(v, (unsigned long) (a))
-#define outsw(a, b, n)   ide_outsw((unsigned long) (a), b, n)
-#define inw(a)           ide_inw((unsigned long) (a))
-#define inw_p(a)             ide_inw((unsigned long) (a))
-#define insw(a, b, n)    ide_insw((unsigned long) (a), b, n)
-#define insl(a, b, n)    ide_insl((unsigned long) (a), b, n)
-#define outsl(a, b, n)   ide_outsl((unsigned long) (a), b, n)
-#endif CONFIG_COLDFIRE
-/****************************************************************************/
-#endif /* __KERNEL__ */
-#endif /* _M68KNOMMU_IDE_H */
-/****************************************************************************/
diff --git a/include/asm-m68knommu/io.h b/include/asm-m68knommu/io.h
index 30fade4149b8..e08f2ee4b4a2 100644
--- a/include/asm-m68knommu/io.h
+++ b/include/asm-m68knommu/io.h
@@ -147,19 +147,19 @@ static inline void io_insl(unsigned int addr, void *buf, int len)
 extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
 extern void __iounmap(void *addr, unsigned long size);
-extern inline void *ioremap(unsigned long physaddr, unsigned long size)
+static inline void *ioremap(unsigned long physaddr, unsigned long size)
 {
        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
 }
-extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
+static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
 {
        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
 }
-extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
+static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
 {
        return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
 }
-extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
+static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
 {
        return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
 }
diff --git a/include/asm-m68knommu/m520xsim.h b/include/asm-m68knommu/m520xsim.h
new file mode 100644
index 000000000000..6dc62869e62b
--- /dev/null
+++ b/include/asm-m68knommu/m520xsim.h
@@ -0,0 +1,54 @@
+/****************************************************************************/
+/*
+ *  m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
+ *
+ *  (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
+ */
+/****************************************************************************/
+#ifndef m520xsim_h
+#define m520xsim_h
+/****************************************************************************/
+#include <linux/config.h>
+/*
+ *  Define the 5282 SIM register set addresses.
+ */
+#define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */
+#define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL        0x0c        /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH     0x10        /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL     0x14        /* Interrupt force 1-31 */
+#define MCFINTC_ICR0        0x40        /* Base ICR register */
+#define MCFINT_VECBASE      64
+#define MCFINT_UART0        26          /* Interrupt number for UART0 */
+#define MCFINT_UART1        27          /* Interrupt number for UART1 */
+#define MCFINT_UART2        28          /* Interrupt number for UART2 */
+#define MCFINT_QSPI         31          /* Interrupt number for QSPI */
+#define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */
+#define MCF_GPIO_PAR_UART                   (0xA4036)
+#define MCF_GPIO_PAR_FECI2C                 (0xA4033)
+#define MCF_GPIO_PAR_FEC                    (0xA4038)
+#define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
+#define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
+#define MCF_GPIO_PAR_UART_PAR_URXD1         (0x0040)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1         (0x0080)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
+#define ICR_INTRCONF            0x05
+#define MCFPIT_IMR              MCFINTC_IMRL
+#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
+/****************************************************************************/
+#endif  /* m520xsim_h */
diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h
index b17cd920977f..9cb401421835 100644
--- a/include/asm-m68knommu/mcfcache.h
+++ b/include/asm-m68knommu/mcfcache.h
@@ -117,6 +117,20 @@
 .endm
 #endif /* CONFIG_M5407 */
+#if defined(CONFIG_M520x)
+.macro CACHE_ENABLE
+        move.l  #0x01000000,%d0         /* invalidate whole cache */
+        movec   %d0,%CACR
+        nop
+        move.l  #0x0000c000,%d0         /* set SDRAM cached (write-thru) */
+        movec   %d0,%ACR0
+        move.l  #0x00000000,%d0         /* no other regions cached */
+        movec   %d0,%ACR1
+        move.l  #0x80400000,%d0         /* enable 8K instruction cache */
+        movec   %d0,%CACR
+        nop
+.endm
+#endif /* CONFIG_M520x */
 /****************************************************************************/
 #endif  /* __M68KNOMMU_MCFCACHE_H */
diff --git a/include/asm-m68knommu/mcfne.h b/include/asm-m68knommu/mcfne.h
index 045875651e4d..a71b1c8cb4f8 100644
--- a/include/asm-m68knommu/mcfne.h
+++ b/include/asm-m68knommu/mcfne.h
@@ -35,7 +35,7 @@
 *      Define the basic hardware resources of NE2000 boards.
 */
-#if defined(CONFIG_M5206) && defined(CONFIG_ARNEWSH)
+#if defined(CONFIG_ARN5206)
 #define NE2000_ADDR             0x40000300
 #define NE2000_ODDOFFSET        0x00010000
 #define NE2000_IRQ_VECTOR       0xf0
@@ -44,7 +44,7 @@
 #define NE2000_BYTE             volatile unsigned short
 #endif
-#if defined(CONFIG_M5206e) && defined(CONFIG_MOTOROLA)
+#if defined(CONFIG_M5206eC3)
 #define NE2000_ADDR             0x40000300
 #define NE2000_ODDOFFSET        0x00010000
 #define NE2000_IRQ_VECTOR       0x1c
@@ -61,7 +61,7 @@
 #define NE2000_BYTE             volatile unsigned char
 #endif
-#if defined(CONFIG_M5206e) && defined(CONFIG_CFV240)
+#if defined(CONFIG_CFV240)
 #define NE2000_ADDR             0x40010000
 #define NE2000_ADDR1            0x40010001
 #define NE2000_ODDOFFSET        0x00000000
@@ -72,7 +72,7 @@
 #define NE2000_BYTE             volatile unsigned char
 #endif
-#if defined(CONFIG_M5307) && defined(CONFIG_MOTOROLA)
+#if defined(CONFIG_M5307C3)
 #define NE2000_ADDR             0x40000300
 #define NE2000_ODDOFFSET        0x00010000
 #define NE2000_IRQ_VECTOR       0x1b
@@ -114,7 +114,7 @@
 #define RSWAP(w)                (((w) << 8) | ((w) >> 8))
 #endif
-#if defined(CONFIG_M5307) && defined(CONFIG_ARNEWSH)
+#if defined(CONFIG_ARN5307)
 #define NE2000_ADDR             0xfe600300
 #define NE2000_ODDOFFSET        0x00010000
 #define NE2000_IRQ_VECTOR       0x1b
@@ -123,7 +123,7 @@
 #define NE2000_BYTE             volatile unsigned short
 #endif
-#if defined(CONFIG_M5407)
+#if defined(CONFIG_M5407C3)
 #define NE2000_ADDR             0x40000300
 #define NE2000_ODDOFFSET        0x00010000
 #define NE2000_IRQ_VECTOR       0x1b
@@ -264,7 +264,7 @@ void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
 *      Minor differences between the different board types.
 */
-#if defined(CONFIG_M5206) && defined(CONFIG_ARNEWSH)
+#if defined(CONFIG_ARN5206)
 void ne2000_irqsetup(int irq)
 {
        volatile unsigned char  *icrp;
@@ -275,7 +275,7 @@ void ne2000_irqsetup(int irq)
 }
 #endif
-#if defined(CONFIG_M5206e) && defined(CONFIG_MOTOROLA)
+#if defined(CONFIG_M5206eC3)
 void ne2000_irqsetup(int irq)
 {
        volatile unsigned char  *icrp;
@@ -286,7 +286,7 @@ void ne2000_irqsetup(int irq)
 }
 #endif
-#if defined(CONFIG_M5206e) && defined(CONFIG_CFV240)
+#if defined(CONFIG_CFV240)
 void ne2000_irqsetup(int irq)
 {
        volatile unsigned char  *icrp;
diff --git a/include/asm-m68knommu/mcfpit.h b/include/asm-m68knommu/mcfpit.h
index 4cc2e9fd6ad0..a685f1b45401 100644
--- a/include/asm-m68knommu/mcfpit.h
+++ b/include/asm-m68knommu/mcfpit.h
@@ -14,13 +14,17 @@
 #include <linux/config.h>
 /*
- *      Get address specific defines for the 5270/5271 and 5280/5282.
+ *      Get address specific defines for the 5270/5271, 5280/5282, and 5208.
 */
+#if defined(CONFIG_M520x)
+#define MCFPIT_BASE1            0x00080000      /* Base address of TIMER1 */
+#define MCFPIT_BASE2            0x00084000      /* Base address of TIMER2 */
+#else
 #define MCFPIT_BASE1            0x00150000      /* Base address of TIMER1 */
 #define MCFPIT_BASE2            0x00160000      /* Base address of TIMER2 */
 #define MCFPIT_BASE3            0x00170000      /* Base address of TIMER3 */
 #define MCFPIT_BASE4            0x00180000      /* Base address of TIMER4 */
+#endif
 /*
 *      Define the PIT timer register set addresses.
diff --git a/include/asm-m68knommu/mcfsim.h b/include/asm-m68knommu/mcfsim.h
index b0c7736f7a99..81d74a31dc43 100644
--- a/include/asm-m68knommu/mcfsim.h
+++ b/include/asm-m68knommu/mcfsim.h
@@ -22,6 +22,8 @@
 #include <asm/m5204sim.h>
 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
 #include <asm/m5206sim.h>
+#elif defined(CONFIG_M520x)
+#include <asm/m520xsim.h>
 #elif defined(CONFIG_M523x)
 #include <asm/m523xsim.h>
 #elif defined(CONFIG_M5249)
@@ -99,6 +101,19 @@
 #define MCFSIM_IMR_MASKALL      0x3ffe          /* All intr sources */
 #endif
+/*
+ *      PIT interrupt settings, if not found in mXXXXsim.h file.
+ */
+#ifndef ICR_INTRCONF
+#define ICR_INTRCONF            0x2b            /* PIT1 level 5, priority 3 */
+#endif
+#ifndef MCFPIT_IMR
+#define MCFPIT_IMR              MCFINTC_IMRH
+#endif
+#ifndef MCFPIT_IMR_IBIT
+#define MCFPIT_IMR_IBIT         (1 << (MCFINT_PIT1 - 32))
+#endif
 #ifndef __ASSEMBLY__
 /*
diff --git a/include/asm-m68knommu/mcfuart.h b/include/asm-m68knommu/mcfuart.h
index 9c1210613bc7..b016fad83119 100644
--- a/include/asm-m68knommu/mcfuart.h
+++ b/include/asm-m68knommu/mcfuart.h
@@ -41,6 +41,10 @@
 #define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
 #define MCFUART_BASE2           0x200           /* Base address of UART2 */
 #endif
+#elif defined(CONFIG_M520x)
+#define MCFUART_BASE1           0x60000         /* Base address of UART1 */
+#define MCFUART_BASE2           0x64000         /* Base address of UART2 */
+#define MCFUART_BASE3           0x68000         /* Base address of UART2 */
 #endif
diff --git a/include/asm-m68knommu/mcfwdebug.h b/include/asm-m68knommu/mcfwdebug.h
index c425dd568155..6ceae103596b 100644
--- a/include/asm-m68knommu/mcfwdebug.h
+++ b/include/asm-m68knommu/mcfwdebug.h
@@ -90,7 +90,7 @@
 * that the debug module instructions (2 longs) must be long word aligned and
 * some pointer fiddling is performed to ensure this.
 */
-extern inline void wdebug(int reg, unsigned long data) {
+static inline void wdebug(int reg, unsigned long data) {
        unsigned short dbg_spc[6];
        unsigned short *dbg;
diff --git a/include/asm-m68knommu/mmu_context.h b/include/asm-m68knommu/mmu_context.h
index 9bc0fd49b8aa..1e080eca9ca8 100644
--- a/include/asm-m68knommu/mmu_context.h
+++ b/include/asm-m68knommu/mmu_context.h
@@ -10,7 +10,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 }
-extern inline int
+static inline int
 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
        // mm->context = virt_to_phys(mm->pgd);
@@ -25,7 +25,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, str
 #define deactivate_mm(tsk,mm)   do { } while (0)
-extern inline void activate_mm(struct mm_struct *prev_mm,
+static inline void activate_mm(struct mm_struct *prev_mm,
                               struct mm_struct *next_mm)
 {
 }
diff --git a/include/asm-m68knommu/processor.h b/include/asm-m68knommu/processor.h
index 85a054e758b1..ba393b1a023b 100644
--- a/include/asm-m68knommu/processor.h
+++ b/include/asm-m68knommu/processor.h
@@ -21,7 +21,7 @@
 #include <asm/ptrace.h>
 #include <asm/current.h>
-extern inline unsigned long rdusp(void)
+static inline unsigned long rdusp(void)
 {
 #ifdef CONFIG_COLDFIRE
        extern unsigned int sw_usp;
@@ -33,7 +33,7 @@ extern inline unsigned long rdusp(void)
 #endif
 }
-extern inline void wrusp(unsigned long usp)
+static inline void wrusp(unsigned long usp)
 {
 #ifdef CONFIG_COLDFIRE
        extern unsigned int sw_usp;
diff --git a/include/asm-m68knommu/semaphore.h b/include/asm-m68knommu/semaphore.h
index febe85add509..5cc1fdd86f50 100644
--- a/include/asm-m68knommu/semaphore.h
+++ b/include/asm-m68knommu/semaphore.h
@@ -35,16 +35,13 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
 #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
 #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0)
-extern inline void sema_init (struct semaphore *sem, int val)
+static inline void sema_init (struct semaphore *sem, int val)
 {
        *sem = (struct semaphore)__SEMAPHORE_INITIALIZER(*sem, val);
 }
@@ -76,7 +73,7 @@ extern spinlock_t semaphore_wake_lock;
 * "down_failed" is a special asm handler that calls the C
 * routine that actually waits. See arch/m68k/lib/semaphore.S
 */
-extern inline void down(struct semaphore * sem)
+static inline void down(struct semaphore * sem)
 {
        might_sleep();
        __asm__ __volatile__(
@@ -91,7 +88,7 @@ extern inline void down(struct semaphore * sem)
                : "cc", "%a0", "%a1", "memory");
 }
-extern inline int down_interruptible(struct semaphore * sem)
+static inline int down_interruptible(struct semaphore * sem)
 {
        int ret;
@@ -110,7 +107,7 @@ extern inline int down_interruptible(struct semaphore * sem)
        return(ret);
 }
-extern inline int down_trylock(struct semaphore * sem)
+static inline int down_trylock(struct semaphore * sem)
 {
        register struct semaphore *sem1 __asm__ ("%a1") = sem;
        register int result __asm__ ("%d0");
@@ -138,7 +135,7 @@ extern inline int down_trylock(struct semaphore * sem)
 * The default case (no contention) will result in NO
 * jumps for both down() and up().
 */
-extern inline void up(struct semaphore * sem)
+static inline void up(struct semaphore * sem)
 {
        __asm__ __volatile__(
                "| atomic up operation\n\t"
diff --git a/include/asm-m68knommu/system.h b/include/asm-m68knommu/system.h
index 53cbbad0f130..6338afc850ba 100644
--- a/include/asm-m68knommu/system.h
+++ b/include/asm-m68knommu/system.h
@@ -312,6 +312,19 @@ cmpxchg(volatile int *p, int old, int new)
        moveb #0x80, (%a0);             \
        ");                             \
 })
+#elif defined(CONFIG_M520x)
+        /*
+         * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register 
+         * RCR), that when set, resets the MCF5208.
+         */
+#define HARD_RESET_NOW()                \
+({                                      \
+        unsigned char volatile *reset;  \
+        asm("move.w     #0x2700, %sr"); \
+        reset = ((volatile unsigned short *)(MCF_IPSBAR + 0xA0000));    \
+        while(1)                        \
+                *reset |= 0x80;         \
+})
 #else
 #define HARD_RESET_NOW() ({             \
        asm("                           \
diff --git a/include/asm-m68knommu/tlbflush.h b/include/asm-m68knommu/tlbflush.h
index bf7004e1afe0..de858db28b00 100644
--- a/include/asm-m68knommu/tlbflush.h
+++ b/include/asm-m68knommu/tlbflush.h
@@ -47,12 +47,12 @@ static inline void flush_tlb_range(struct mm_struct *mm,
        BUG();
 }
-extern inline void flush_tlb_kernel_page(unsigned long addr)
+static inline void flush_tlb_kernel_page(unsigned long addr)
 {
        BUG();
 }
-extern inline void flush_tlb_pgtables(struct mm_struct *mm,
+static inline void flush_tlb_pgtables(struct mm_struct *mm,
                                      unsigned long start, unsigned long end)
 {
        BUG();
diff --git a/include/asm-m68knommu/unistd.h b/include/asm-m68knommu/unistd.h
index 84b6fa14459f..5373988a7e51 100644
--- a/include/asm-m68knommu/unistd.h
+++ b/include/asm-m68knommu/unistd.h
@@ -504,7 +504,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
                        unsigned long fd, unsigned long pgoff);
 asmlinkage int sys_execve(char *name, char **argv, char **envp);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct pt_regs;
 int sys_request_irq(unsigned int,
                        irqreturn_t (*)(int, void *, struct pt_regs *),
diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h
new file mode 100644
index 000000000000..2e7e651c3e3f
--- /dev/null
+++ b/include/asm-mips/abi.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 by Ralf Baechle
+ * Copyright (C) 2005 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_ABI_H
+#define _ASM_ABI_H
+#include <asm/signal.h>
+#include <asm/siginfo.h>
+struct mips_abi {
+        int (* const do_signal)(sigset_t *oldset, struct pt_regs *regs);
+        int (* const setup_frame)(struct k_sigaction * ka,
+                                  struct pt_regs *regs, int signr,
+                                  sigset_t *set);
+        int (* const setup_rt_frame)(struct k_sigaction * ka,
+                               struct pt_regs *regs, int signr,
+                               sigset_t *set, siginfo_t *info);
+};
+#endif /* _ASM_ABI_H */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 7dc2619f5006..42520cc84b0f 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -20,10 +20,12 @@
 #define _ATYPE_
 #define _ATYPE32_
 #define _ATYPE64_
+#define _LLCONST_(x)    x
 #else
 #define _ATYPE_         __PTRDIFF_TYPE__
 #define _ATYPE32_       int
 #define _ATYPE64_       long long
+#define _LLCONST_(x)    x ## LL
 #endif
 /*
@@ -45,8 +47,9 @@
 /*
 * Returns the physical address of a CKSEGx / XKPHYS address
 */
-#define CPHYSADDR(a)            ((_ACAST32_ (a)) & 0x1fffffff)
+#define CPHYSADDR(a)            ((_ACAST32_(a)) & 0x1fffffff)
-#define XPHYSADDR(a)            ((_ACAST64_ (a)) & 0x000000ffffffffff)
+#define XPHYSADDR(a)            ((_ACAST64_(a)) &                       \
+                                 _LLCONST_(0x000000ffffffffff))
 #ifdef CONFIG_64BIT
@@ -55,14 +58,14 @@
 * The compatibility segments use the full 64-bit sign extended value.  Note
 * the R8000 doesn't have them so don't reference these in generic MIPS code.
 */
-#define XKUSEG                  0x0000000000000000
+#define XKUSEG                  _LLCONST_(0x0000000000000000)
-#define XKSSEG                  0x4000000000000000
+#define XKSSEG                  _LLCONST_(0x4000000000000000)
-#define XKPHYS                  0x8000000000000000
+#define XKPHYS                  _LLCONST_(0x8000000000000000)
-#define XKSEG                   0xc000000000000000
+#define XKSEG                   _LLCONST_(0xc000000000000000)
-#define CKSEG0                  0xffffffff80000000
+#define CKSEG0                  _LLCONST_(0xffffffff80000000)
-#define CKSEG1                  0xffffffffa0000000
+#define CKSEG1                  _LLCONST_(0xffffffffa0000000)
-#define CKSSEG                  0xffffffffc0000000
+#define CKSSEG                  _LLCONST_(0xffffffffc0000000)
-#define CKSEG3                  0xffffffffe0000000
+#define CKSEG3                  _LLCONST_(0xffffffffe0000000)
 #define CKSEG0ADDR(a)           (CPHYSADDR(a) | CKSEG0)
 #define CKSEG1ADDR(a)           (CPHYSADDR(a) | CKSEG1)
@@ -120,7 +123,8 @@
 #define PHYS_TO_XKSEG_UNCACHED(p)       PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
 #define PHYS_TO_XKSEG_CACHED(p)         PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
 #define XKPHYS_TO_PHYS(p)               ((p) & TO_PHYS_MASK)
-#define PHYS_TO_XKPHYS(cm,a)            (0x8000000000000000 | ((cm)<<59) | (a))
+#define PHYS_TO_XKPHYS(cm,a)            (_LLCONST_(0x8000000000000000) | \
+                                         ((cm)<<59) | (a))
 #if defined (CONFIG_CPU_R4300)                                          \
    || defined (CONFIG_CPU_R4X00)                                       \
@@ -128,46 +132,56 @@
    || defined (CONFIG_CPU_NEVADA)                                      \
    || defined (CONFIG_CPU_TX49XX)                                      \
    || defined (CONFIG_CPU_MIPS64)
-#define KUSIZE                  0x0000010000000000      /* 2^^40 */
+#define KUSIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
+#define KUSIZE_64       _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define K0SIZE                  0x0000001000000000      /* 2^^36 */
+#define K0SIZE          _LLCONST_(0x0000001000000000)   /* 2^^36 */
-#define K1SIZE                  0x0000001000000000      /* 2^^36 */
+#define K1SIZE          _LLCONST_(0x0000001000000000)   /* 2^^36 */
-#define K2SIZE                  0x000000ff80000000
+#define K2SIZE          _LLCONST_(0x000000ff80000000)
-#define KSEGSIZE                0x000000ff80000000      /* max syssegsz */
+#define KSEGSIZE        _LLCONST_(0x000000ff80000000)   /* max syssegsz */
-#define TO_PHYS_MASK            0x0000000fffffffff      /* 2^^36 - 1 */
+#define TO_PHYS_MASK    _LLCONST_(0x0000000fffffffff)   /* 2^^36 - 1 */
 #endif
 #if defined (CONFIG_CPU_R8000)
 /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
-#define KUSIZE                  0x0000010000000000      /* 2^^40 */
+#define KUSIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
+#define KUSIZE_64       _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define K0SIZE                  0x0000010000000000      /* 2^^40 */
+#define K0SIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define K1SIZE                  0x0000010000000000      /* 2^^40 */
+#define K1SIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define K2SIZE                  0x0001000000000000
+#define K2SIZE          _LLCONST_(0x0001000000000000)
-#define KSEGSIZE                0x0000010000000000      /* max syssegsz */
+#define KSEGSIZE        _LLCONST_(0x0000010000000000)   /* max syssegsz */
-#define TO_PHYS_MASK            0x000000ffffffffff      /* 2^^40 - 1 */
+#define TO_PHYS_MASK    _LLCONST_(0x000000ffffffffff)   /* 2^^40 - 1 */
 #endif
 #if defined (CONFIG_CPU_R10000)
-#define KUSIZE                  0x0000010000000000      /* 2^^40 */
+#define KUSIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
+#define KUSIZE_64       _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define K0SIZE                  0x0000010000000000      /* 2^^40 */
+#define K0SIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define K1SIZE                  0x0000010000000000      /* 2^^40 */
+#define K1SIZE          _LLCONST_(0x0000010000000000)   /* 2^^40 */
-#define K2SIZE                  0x00000fff80000000
+#define K2SIZE          _LLCONST_(0x00000fff80000000)
-#define KSEGSIZE                0x00000fff80000000      /* max syssegsz */
+#define KSEGSIZE        _LLCONST_(0x00000fff80000000)   /* max syssegsz */
-#define TO_PHYS_MASK            0x000000ffffffffff      /* 2^^40 - 1 */
+#define TO_PHYS_MASK    _LLCONST_(0x000000ffffffffff)   /* 2^^40 - 1 */
+#endif
+#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
+#define KUSIZE          _LLCONST_(0x0000100000000000)   /* 2^^44 */
+#define KUSIZE_64       _LLCONST_(0x0000100000000000)   /* 2^^44 */
+#define K0SIZE          _LLCONST_(0x0000100000000000)   /* 2^^44 */
+#define K1SIZE          _LLCONST_(0x0000100000000000)   /* 2^^44 */
+#define K2SIZE          _LLCONST_(0x0000ffff80000000)
+#define KSEGSIZE        _LLCONST_(0x0000ffff80000000)   /* max syssegsz */
+#define TO_PHYS_MASK    _LLCONST_(0x00000fffffffffff)   /* 2^^44 - 1 */
 #endif
 /*
 * Further names for SGI source compatibility.  These are stolen from
 * IRIX's <sys/mips_addrspace.h>.
 */
-#define KUBASE                  0
+#define KUBASE          _LLCONST_(0)
-#define KUSIZE_32               0x0000000080000000      /* KUSIZE
+#define KUSIZE_32       _LLCONST_(0x0000000080000000)   /* KUSIZE
                                                           for a 32 bit proc */
-#define K0BASE_EXL_WR           0xa800000000000000      /* exclusive on write */
+#define K0BASE_EXL_WR   _LLCONST_(0xa800000000000000)   /* exclusive on write */
-#define K0BASE_NONCOH           0x9800000000000000      /* noncoherent */
+#define K0BASE_NONCOH   _LLCONST_(0x9800000000000000)   /* noncoherent */
-#define K0BASE_EXL              0xa000000000000000      /* exclusive */
+#define K0BASE_EXL      _LLCONST_(0xa000000000000000)   /* exclusive */
 #ifndef CONFIG_CPU_R8000
@@ -176,7 +190,7 @@
 * in order to catch bugs in the source code.
 */
-#define COMPAT_K1BASE32         0xffffffffa0000000
+#define COMPAT_K1BASE32         _LLCONST_(0xffffffffa0000000)
 #define PHYS_TO_COMPATK1(x)     ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
 #endif
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
index f53237772985..4b090f3142e0 100644
--- a/include/asm-mips/asm.h
+++ b/include/asm-mips/asm.h
@@ -107,6 +107,7 @@ symbol		=	value
 /*
 * Print formatted string
 */
+#ifdef CONFIG_PRINTK
 #define PRINT(string)                                   \
                .set    push;                           \
                .set    reorder;                        \
@@ -114,6 +115,9 @@ symbol		=	value
                jal     printk;                         \
                .set    pop;                            \
                TEXT(string)
+#else
+#define PRINT(string)
+#endif
 #define TEXT(msg)                                       \
                .pushsection .data;                     \
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index c0bd8d014e14..6202eb8a14b7 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -62,20 +62,24 @@ static __inline__ void atomic_add(int i, atomic_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %0, %1          # atomic_add            \n"
                "       addu    %0, %2                                  \n"
                "       sc      %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %0, %1          # atomic_add            \n"
                "       addu    %0, %2                                  \n"
                "       sc      %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else {
@@ -100,20 +104,24 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %0, %1          # atomic_sub            \n"
                "       subu    %0, %2                                  \n"
                "       sc      %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %0, %1          # atomic_sub            \n"
                "       subu    %0, %2                                  \n"
                "       sc      %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else {
@@ -136,12 +144,14 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %1, %2          # atomic_add_return     \n"
                "       addu    %0, %1, %3                              \n"
                "       sc      %0, %2                                  \n"
                "       beqzl   %0, 1b                                  \n"
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -149,12 +159,14 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %1, %2          # atomic_add_return     \n"
                "       addu    %0, %1, %3                              \n"
                "       sc      %0, %2                                  \n"
                "       beqz    %0, 1b                                  \n"
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -179,12 +191,14 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %1, %2          # atomic_sub_return     \n"
                "       subu    %0, %1, %3                              \n"
                "       sc      %0, %2                                  \n"
                "       beqzl   %0, 1b                                  \n"
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -192,12 +206,14 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %1, %2          # atomic_sub_return     \n"
                "       subu    %0, %1, %3                              \n"
                "       sc      %0, %2                                  \n"
                "       beqz    %0, 1b                                  \n"
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -229,6 +245,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
                "       subu    %0, %1, %3                              \n"
                "       bltz    %0, 1f                                  \n"
@@ -236,6 +253,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                "       beqzl   %0, 1b                                  \n"
                "       sync                                            \n"
                "1:                                                     \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -243,6 +261,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
                "       subu    %0, %1, %3                              \n"
                "       bltz    %0, 1f                                  \n"
@@ -250,6 +269,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                "       beqz    %0, 1b                                  \n"
                "       sync                                            \n"
                "1:                                                     \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -367,20 +387,24 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %0, %1          # atomic64_add          \n"
                "       addu    %0, %2                                  \n"
                "       scd     %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %0, %1          # atomic64_add          \n"
                "       addu    %0, %2                                  \n"
                "       scd     %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else {
@@ -405,20 +429,24 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %0, %1          # atomic64_sub          \n"
                "       subu    %0, %2                                  \n"
                "       scd     %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %0, %1          # atomic64_sub          \n"
                "       subu    %0, %2                                  \n"
                "       scd     %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else {
@@ -441,12 +469,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %1, %2          # atomic64_add_return   \n"
                "       addu    %0, %1, %3                              \n"
                "       scd     %0, %2                                  \n"
                "       beqzl   %0, 1b                                  \n"
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -454,12 +484,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %1, %2          # atomic64_add_return   \n"
                "       addu    %0, %1, %3                              \n"
                "       scd     %0, %2                                  \n"
                "       beqz    %0, 1b                                  \n"
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -484,12 +516,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %1, %2          # atomic64_sub_return   \n"
                "       subu    %0, %1, %3                              \n"
                "       scd     %0, %2                                  \n"
                "       beqzl   %0, 1b                                  \n"
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -497,12 +531,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %1, %2          # atomic64_sub_return   \n"
                "       subu    %0, %1, %3                              \n"
                "       scd     %0, %2                                  \n"
                "       beqz    %0, 1b                                  \n"
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -534,6 +570,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
                "       dsubu   %0, %1, %3                              \n"
                "       bltz    %0, 1f                                  \n"
@@ -541,6 +578,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                "       beqzl   %0, 1b                                  \n"
                "       sync                                            \n"
                "1:                                                     \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
@@ -548,6 +586,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
                "       dsubu   %0, %1, %3                              \n"
                "       bltz    %0, 1f                                  \n"
@@ -555,6 +594,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                "       beqz    %0, 1b                                  \n"
                "       sync                                            \n"
                "1:                                                     \n"
+                "       .set    mips0                                   \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter)
                : "memory");
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index eb8d79dba11c..5496f9064a6a 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -12,20 +12,21 @@
 #include <linux/config.h>
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <asm/bug.h>
 #include <asm/byteorder.h>              /* sigh ... */
 #include <asm/cpu-features.h>
 #if (_MIPS_SZLONG == 32)
 #define SZLONG_LOG 5
 #define SZLONG_MASK 31UL
-#define __LL    "ll     "
+#define __LL            "ll     "
-#define __SC    "sc     "
+#define __SC            "sc     "
 #define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
 #elif (_MIPS_SZLONG == 64)
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
-#define __LL    "lld    "
+#define __LL            "lld    "
-#define __SC    "scd    "
+#define __SC            "scd    "
 #define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
 #endif
@@ -72,18 +73,22 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     " __LL "%0, %1                  # set_bit       \n"
                "       or      %0, %2                                  \n"
-                "       "__SC   "%0, %1                                 \n"
+                "       " __SC  "%0, %1                                 \n"
                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m)
                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
        } else if (cpu_has_llsc) {
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     " __LL "%0, %1                  # set_bit       \n"
                "       or      %0, %2                                  \n"
-                "       "__SC   "%0, %1                                 \n"
+                "       " __SC  "%0, %1                                 \n"
                "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m)
                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
        } else {
@@ -132,18 +137,22 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     " __LL "%0, %1                  # clear_bit     \n"
                "       and     %0, %2                                  \n"
                "       " __SC "%0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m)
                : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
        } else if (cpu_has_llsc) {
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     " __LL "%0, %1                  # clear_bit     \n"
                "       and     %0, %2                                  \n"
                "       " __SC "%0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m)
                : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
        } else {
@@ -191,10 +200,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                           \n"
                "1:     " __LL "%0, %1          # change_bit    \n"
                "       xor     %0, %2                          \n"
-                "       "__SC   "%0, %1                         \n"
+                "       " __SC  "%0, %1                         \n"
                "       beqzl   %0, 1b                          \n"
+                "       .set    mips0                           \n"
                : "=&r" (temp), "=m" (*m)
                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
        } else if (cpu_has_llsc) {
@@ -202,10 +213,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                unsigned long temp;
                __asm__ __volatile__(
+                "       .set    mips3                           \n"
                "1:     " __LL "%0, %1          # change_bit    \n"
                "       xor     %0, %2                          \n"
-                "       "__SC   "%0, %1                         \n"
+                "       " __SC  "%0, %1                         \n"
                "       beqz    %0, 1b                          \n"
+                "       .set    mips0                           \n"
                : "=&r" (temp), "=m" (*m)
                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
        } else {
@@ -253,14 +266,16 @@ static inline int test_and_set_bit(unsigned long nr,
                unsigned long temp, res;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
                "       or      %2, %0, %3                              \n"
                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
-                "sync                                                   \n"
+                "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                : "memory");
@@ -271,16 +286,18 @@ static inline int test_and_set_bit(unsigned long nr,
                unsigned long temp, res;
                __asm__ __volatile__(
-                "       .set    noreorder       # test_and_set_bit      \n"
+                "       .set    push                                    \n"
-                "1:     " __LL "%0, %1                                  \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
                "       or      %2, %0, %3                              \n"
                "       " __SC  "%2, %1                                 \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
-                "sync                                                   \n"
+                "       sync                                            \n"
 #endif
-                ".set\treorder"
+                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                : "memory");
@@ -343,15 +360,17 @@ static inline int test_and_clear_bit(unsigned long nr,
                unsigned long temp, res;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
                "       or      %2, %0, %3                              \n"
                "       xor     %2, %3                                  \n"
-                        __SC    "%2, %1                                 \n"
+                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                : "memory");
@@ -362,17 +381,19 @@ static inline int test_and_clear_bit(unsigned long nr,
                unsigned long temp, res;
                __asm__ __volatile__(
-                "       .set    noreorder       # test_and_clear_bit    \n"
+                "       .set    push                                    \n"
-                "1:     " __LL  "%0, %1                                 \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
                "       or      %2, %0, %3                              \n"
                "       xor     %2, %3                                  \n"
-                        __SC    "%2, %1                                 \n"
+                "       " __SC  "%2, %1                                 \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
-                "       .set    reorder                                 \n"
+                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                : "memory");
@@ -435,14 +456,16 @@ static inline int test_and_change_bit(unsigned long nr,
                unsigned long temp, res;
                __asm__ __volatile__(
-                "1:     " __LL  " %0, %1        # test_and_change_bit   \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
                "       xor     %2, %0, %3                              \n"
-                "       "__SC   "%2, %1                                 \n"
+                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                : "memory");
@@ -453,16 +476,18 @@ static inline int test_and_change_bit(unsigned long nr,
                unsigned long temp, res;
                __asm__ __volatile__(
-                "       .set    noreorder       # test_and_change_bit   \n"
+                "       .set    push                                    \n"
-                "1:     " __LL  " %0, %1                                \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
                "       xor     %2, %0, %3                              \n"
-                "       "__SC   "\t%2, %1                               \n"
+                "       " __SC  "\t%2, %1                               \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
-                "       .set    reorder                                 \n"
+                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
                : "memory");
@@ -523,22 +548,60 @@ static inline int test_bit(unsigned long nr, const volatile unsigned long *addr)
 }
 /*
- * ffz - find first zero in word.
+ * Return the bit position (0..63) of the most significant 1 bit in a word
+ * Returns -1 if no 1 bit exists
+ */
+static inline int __ilog2(unsigned long x)
+{
+        int lz;
+        if (sizeof(x) == 4) {
+                __asm__ (
+                "       .set    push                                    \n"
+                "       .set    mips32                                  \n"
+                "       clz     %0, %1                                  \n"
+                "       .set    pop                                     \n"
+                : "=r" (lz)
+                : "r" (x));
+                return 31 - lz;
+        }
+        BUG_ON(sizeof(x) != 8);
+        __asm__ (
+        "       .set    push                                            \n"
+        "       .set    mips64                                          \n"
+        "       dclz    %0, %1                                          \n"
+        "       .set    pop                                             \n"
+        : "=r" (lz)
+        : "r" (x));
+        return 63 - lz;
+}
+/*
+ * __ffs - find first bit in word.
 * @word: The word to search
 *
- * Undefined if no zero exists, so code should check against ~0UL first.
+ * Returns 0..SZLONG-1
+ * Undefined if no bit exists, so code should check against 0 first.
 */
-static inline unsigned long ffz(unsigned long word)
+static inline unsigned long __ffs(unsigned long word)
 {
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+        return __ilog2(word & -word);
+#else
        int b = 0, s;
-        word = ~word;
 #ifdef CONFIG_32BIT
        s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s;
        s =  8; if (word << 24 != 0) s = 0; b += s; word >>= s;
        s =  4; if (word << 28 != 0) s = 0; b += s; word >>= s;
        s =  2; if (word << 30 != 0) s = 0; b += s; word >>= s;
        s =  1; if (word << 31 != 0) s = 0; b += s;
+        return b;
 #endif
 #ifdef CONFIG_64BIT
        s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
@@ -547,27 +610,92 @@ static inline unsigned long ffz(unsigned long word)
        s =  4; if (word << 60 != 0) s = 0; b += s; word >>= s;
        s =  2; if (word << 62 != 0) s = 0; b += s; word >>= s;
        s =  1; if (word << 63 != 0) s = 0; b += s;
-#endif
        return b;
+#endif
+#endif
 }
 /*
- * __ffs - find first bit in word.
+ * ffs - find first bit set.
 * @word: The word to search
 *
- * Undefined if no bit exists, so code should check against 0 first.
+ * Returns 1..SZLONG
+ * Returns 0 if no bit exists
 */
-static inline unsigned long __ffs(unsigned long word)
+static inline unsigned long ffs(unsigned long word)
 {
-        return ffz(~word);
+        if (!word)
+                return 0;
+        return __ffs(word) + 1;
 }
 /*
- * fls: find last bit set.
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+        return __ffs (~word);
+}
+/*
+ * flz - find last zero in word.
+ * @word: The word to search
+ *
+ * Returns 0..SZLONG-1
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static inline unsigned long flz(unsigned long word)
+{
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+        return __ilog2(~word);
+#else
+#ifdef CONFIG_32BIT
+        int r = 31, s;
+        word = ~word;
+        s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s;
+        s = 8;  if ((word & 0xff000000)) s = 0; r -= s; word <<= s;
+        s = 4;  if ((word & 0xf0000000)) s = 0; r -= s; word <<= s;
+        s = 2;  if ((word & 0xc0000000)) s = 0; r -= s; word <<= s;
+        s = 1;  if ((word & 0x80000000)) s = 0; r -= s;
+        return r;
+#endif
+#ifdef CONFIG_64BIT
+        int r = 63, s;
+        word = ~word;
+        s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s;
+        s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s;
+        s = 8;  if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s;
+        s = 4;  if ((word & 0xf000000000000000UL)) s = 0; r -= s; word <<= s;
+        s = 2;  if ((word & 0xc000000000000000UL)) s = 0; r -= s; word <<= s;
+        s = 1;  if ((word & 0x8000000000000000UL)) s = 0; r -= s;
+        return r;
+#endif
+#endif
+}
+/*
+ * fls - find last bit set.
+ * @word: The word to search
+ *
+ * Returns 1..SZLONG
+ * Returns 0 if no bit exists
 */
+static inline unsigned long fls(unsigned long word)
+{
+        if (word == 0)
+                return 0;
+        return flz(~word) + 1;
+}
-#define fls(x) generic_fls(x)
 /*
 * find_next_zero_bit - find the first zero bit in a memory region
@@ -704,17 +832,6 @@ static inline int sched_find_first_bit(const unsigned long *b)
 }
 /*
- * ffs - find first bit set
- * @x: the word to search
- *
- * This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-#define ffs(x) generic_ffs(x)
-/*
 * hweightN - returns the hamming weight of a N-bit word
 * @x: the word to weigh
 *
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b1e57d783604..14fc88f27226 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -77,6 +77,7 @@
 #define  MACH_SGI_IP27          1       /* Origin 200, Origin 2000, Onyx 2 */
 #define  MACH_SGI_IP28          2       /* Indigo2 Impact               */
 #define  MACH_SGI_IP32          3       /* O2                           */
+#define  MACH_SGI_IP30          4       /* Octane, Octane2              */
 /*
 * Valid machtype for group COBALT
@@ -136,6 +137,7 @@
 #define MACH_GROUP_PHILIPS     14
 #define  MACH_PHILIPS_NINO      0       /* Nino */
 #define  MACH_PHILIPS_VELO      1       /* Velo */
+#define  MACH_PHILIPS_JBS       2       /* JBS */
 /*
 * Valid machtype for group Globespan
@@ -159,6 +161,7 @@
 #define  MACH_TOSHIBA_JMR3927   3       /* JMR-TX3927 CPU/IO board */
 #define  MACH_TOSHIBA_RBTX4927  4
 #define  MACH_TOSHIBA_RBTX4937  5
+#define  MACH_TOSHIBA_RBTX4938  6
 #define GROUP_TOSHIBA_NAMES     { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
                                  "RBTX4927", "RBTX4937" }
@@ -177,6 +180,8 @@
 #define  MACH_MTX1              7       /* 4G MTX-1 Au1500-based board */
 #define  MACH_PB1550            8       /* Au1550-based eval board */
 #define  MACH_DB1550            9       /* Au1550-based eval board */
+#define  MACH_PB1200            10       /* Au1200-based eval board */
+#define  MACH_DB1200            11       /* Au1200-based eval board */
 /*
 * Valid machtype for group NEC_VR41XX
diff --git a/include/asm-mips/break.h b/include/asm-mips/break.h
index 2e6de788f207..25b980c91e7e 100644
--- a/include/asm-mips/break.h
+++ b/include/asm-mips/break.h
@@ -28,6 +28,7 @@
 #define BRK_NORLD       10      /* No rld found - not used by Linux/MIPS */
 #define _BRK_THREADBP   11      /* For threads, user bp (used by debuggers) */
 #define BRK_BUG         512     /* Used by BUG() */
+#define BRK_KDB         513     /* Used in KDB_ENTER() */
 #define BRK_MULOVF      1023    /* Multiply overflow */
 #endif /* __ASM_BREAK_H */
diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h
index 3f594b440abc..87d49a5bdc63 100644
--- a/include/asm-mips/bug.h
+++ b/include/asm-mips/bug.h
@@ -1,16 +1,21 @@
 #ifndef __ASM_BUG_H
 #define __ASM_BUG_H
-#include <asm/break.h>
+#include <linux/config.h>
 #ifdef CONFIG_BUG
-#define HAVE_ARCH_BUG
+#include <asm/break.h>
 #define BUG()                                                           \
 do {                                                                    \
        __asm__ __volatile__("break %0" : : "i" (BRK_BUG));             \
 } while (0)
+#define HAVE_ARCH_BUG
 #endif
 #include <asm-generic/bug.h>
-#endif
+#endif /* __ASM_BUG_H */
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
index b14b961c2100..cb2ea7c15c7a 100644
--- a/include/asm-mips/bugs.h
+++ b/include/asm-mips/bugs.h
@@ -8,12 +8,18 @@
 #define _ASM_BUGS_H
 #include <linux/config.h>
+#include <linux/delay.h>
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
 extern void check_bugs32(void);
 extern void check_bugs64(void);
 static inline void check_bugs(void)
 {
+        unsigned int cpu = smp_processor_id();
+        cpu_data[cpu].udelay_val = loops_per_jiffy;
        check_bugs32();
 #ifdef CONFIG_64BIT
        check_bugs64();
diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
index 4517bdf20953..1a5d1a669db3 100644
--- a/include/asm-mips/cache.h
+++ b/include/asm-mips/cache.h
@@ -10,6 +10,7 @@
 #define _ASM_CACHE_H
 #include <linux/config.h>
+#include <kmalloc.h>
 #define L1_CACHE_SHIFT          CONFIG_MIPS_L1_CACHE_SHIFT
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
@@ -18,6 +19,4 @@
 #define SMP_CACHE_SHIFT         L1_CACHE_SHIFT
 #define SMP_CACHE_BYTES         L1_CACHE_BYTES
-#define ARCH_KMALLOC_MINALIGN   8
 #endif /* _ASM_CACHE_H */
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 635f1bfb403e..a18ba2edc0b6 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -49,17 +49,29 @@ static inline void flush_dcache_page(struct page *page)
 extern void (*flush_icache_page)(struct vm_area_struct *vma,
        struct page *page);
-extern void (*flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*flush_icache_range)(unsigned long __user start,
+        unsigned long __user end);
 #define flush_cache_vmap(start, end)            flush_cache_all()
 #define flush_cache_vunmap(start, end)          flush_cache_all()
-#define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
+static inline void copy_to_user_page(struct vm_area_struct *vma,
-do {                                                                    \
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
-        memcpy(dst, (void *) src, len);                                 \
+        unsigned long len)
-        flush_icache_page(vma, page);                                   \
+{
-} while (0)
+        if (cpu_has_dc_aliases)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len)            \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));
-        memcpy(dst, src, len)
+        memcpy(dst, src, len);
+        flush_icache_page(vma, page);
+}
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len)
+{
+        if (cpu_has_dc_aliases)
+                flush_cache_page(vma, vaddr, page_to_pfn(page));
+        memcpy(dst, src, len);
+}
 extern void (*flush_cache_sigtramp)(unsigned long addr);
 extern void (*flush_icache_all)(void);
@@ -78,4 +90,7 @@ extern void (*flush_data_cache_page)(unsigned long addr);
 #define ClearPageDcacheDirty(page)      \
        clear_bit(PG_dcache_dirty, &(page)->flags)
+/* Run kernel code uncached, useful for cache probing functions. */
+unsigned long __init run_uncached(void *func);
 #endif /* _ASM_CACHEFLUSH_H */
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
index c1ea5a8714f3..b09f8971e95d 100644
--- a/include/asm-mips/checksum.h
+++ b/include/asm-mips/checksum.h
@@ -34,8 +34,9 @@ unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
 * this is a new version of the above that records errors it finds in *errp,
 * but continues and zeros the rest of the buffer.
 */
-unsigned int csum_partial_copy_from_user(const unsigned char *src, unsigned char *dst, int len,
+unsigned int csum_partial_copy_from_user(const unsigned char __user *src,
-                                         unsigned int sum, int *errp);
+                                         unsigned char *dst, int len,
+                                         unsigned int sum, int *errp);
 /*
 * Copy and checksum to user
@@ -70,14 +71,15 @@ unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *
 static inline unsigned short int csum_fold(unsigned int sum)
 {
        __asm__(
-        ".set\tnoat\t\t\t# csum_fold\n\t"
+        "       .set    push            # csum_fold\n"
-        "sll\t$1,%0,16\n\t"
+        "       .set    noat            \n"
-        "addu\t%0,$1\n\t"
+        "       sll     $1, %0, 16      \n"
-        "sltu\t$1,%0,$1\n\t"
+        "       addu    %0, $1          \n"
-        "srl\t%0,%0,16\n\t"
+        "       sltu    $1, %0, $1      \n"
-        "addu\t%0,$1\n\t"
+        "       srl     %0, %0, 16      \n"
-        "xori\t%0,0xffff\n\t"
+        "       addu    %0, $1          \n"
-        ".set\tat"
+        "       xori    %0, 0xffff      \n"
+        "       .set    pop"
        : "=r" (sum)
        : "0" (sum));
@@ -127,29 +129,30 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
        unsigned int sum)
 {
        __asm__(
-        ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t"
+        "       .set    push            # csum_tcpudp_nofold\n"
+        "       .set    noat            \n"
 #ifdef CONFIG_32BIT
-        "addu\t%0, %2\n\t"
+        "       addu    %0, %2          \n"
-        "sltu\t$1, %0, %2\n\t"
+        "       sltu    $1, %0, %2      \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %3\n\t"
+        "       addu    %0, %3          \n"
-        "sltu\t$1, %0, %3\n\t"
+        "       sltu    $1, %0, %3      \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %4\n\t"
+        "       addu    %0, %4          \n"
-        "sltu\t$1, %0, %4\n\t"
+        "       sltu    $1, %0, %4      \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
 #endif
 #ifdef CONFIG_64BIT
-        "daddu\t%0, %2\n\t"
+        "       daddu   %0, %2          \n"
-        "daddu\t%0, %3\n\t"
+        "       daddu   %0, %3          \n"
-        "daddu\t%0, %4\n\t"
+        "       daddu   %0, %4          \n"
-        "dsll32\t$1, %0, 0\n\t"
+        "       dsll32  $1, %0, 0       \n"
-        "daddu\t%0, $1\n\t"
+        "       daddu   %0, $1          \n"
-        "dsrl32\t%0, %0, 0\n\t"
+        "       dsra32  %0, %0, 0       \n"
 #endif
-        ".set\tat"
+        "       .set    pop"
        : "=r" (sum)
        : "0" (daddr), "r"(saddr),
 #ifdef __MIPSEL__
@@ -192,57 +195,57 @@ static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
                                                     unsigned int sum)
 {
        __asm__(
-        ".set\tpush\t\t\t# csum_ipv6_magic\n\t"
+        "       .set    push            # csum_ipv6_magic\n"
-        ".set\tnoreorder\n\t"
+        "       .set    noreorder       \n"
-        ".set\tnoat\n\t"
+        "       .set    noat            \n"
-        "addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t"
+        "       addu    %0, %5          # proto (long in network byte order)\n"
-        "sltu\t$1, %0, %5\n\t"
+        "       sltu    $1, %0, %5      \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %6\t\t\t# csum\n\t"
+        "       addu    %0, %6          # csum\n"
-        "sltu\t$1, %0, %6\n\t"
+        "       sltu    $1, %0, %6      \n"
-        "lw\t%1, 0(%2)\t\t\t# four words source address\n\t"
+        "       lw      %1, 0(%2)       # four words source address\n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %1\n\t"
+        "       addu    %0, %1          \n"
-        "sltu\t$1, %0, %1\n\t"
+        "       sltu    $1, %0, %1      \n"
-        "lw\t%1, 4(%2)\n\t"
+        "       lw      %1, 4(%2)       \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %1\n\t"
+        "       addu    %0, %1          \n"
-        "sltu\t$1, %0, %1\n\t"
+        "       sltu    $1, %0, %1      \n"
-        "lw\t%1, 8(%2)\n\t"
+        "       lw      %1, 8(%2)       \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %1\n\t"
+        "       addu    %0, %1          \n"
-        "sltu\t$1, %0, %1\n\t"
+        "       sltu    $1, %0, %1      \n"
-        "lw\t%1, 12(%2)\n\t"
+        "       lw      %1, 12(%2)      \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %1\n\t"
+        "       addu    %0, %1          \n"
-        "sltu\t$1, %0, %1\n\t"
+        "       sltu    $1, %0, %1      \n"
-        "lw\t%1, 0(%3)\n\t"
+        "       lw      %1, 0(%3)       \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %1\n\t"
+        "       addu    %0, %1          \n"
-        "sltu\t$1, %0, %1\n\t"
+        "       sltu    $1, %0, %1      \n"
-        "lw\t%1, 4(%3)\n\t"
+        "       lw      %1, 4(%3)       \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %1\n\t"
+        "       addu    %0, %1          \n"
-        "sltu\t$1, %0, %1\n\t"
+        "       sltu    $1, %0, %1      \n"
-        "lw\t%1, 8(%3)\n\t"
+        "       lw      %1, 8(%3)       \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %1\n\t"
+        "       addu    %0, %1          \n"
-        "sltu\t$1, %0, %1\n\t"
+        "       sltu    $1, %0, %1      \n"
-        "lw\t%1, 12(%3)\n\t"
+        "       lw      %1, 12(%3)      \n"
-        "addu\t%0, $1\n\t"
+        "       addu    %0, $1          \n"
-        "addu\t%0, %1\n\t"
+        "       addu    %0, %1          \n"
-        "sltu\t$1, %0, %1\n\t"
+        "       sltu    $1, %0, %1      \n"
-        "addu\t%0, $1\t\t\t# Add final carry\n\t"
+        "       addu    %0, $1          # Add final carry\n"
-        ".set\tpop"
+        "       .set    pop"
        : "=r" (sum), "=r" (proto)
        : "r" (saddr), "r" (daddr),
          "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/cobalt/cobalt.h
index ca1fbc0579fe..78e1df2095fb 100644
--- a/include/asm-mips/cobalt/cobalt.h
+++ b/include/asm-mips/cobalt/cobalt.h
@@ -19,18 +19,23 @@
 *     9  - PCI
 *    14  - IDE0
 *    15  - IDE1
- *
+ */
+#define COBALT_QUBE_SLOT_IRQ    9
+/*
 * CPU IRQs  are 16 ... 23
 */
-#define COBALT_TIMER_IRQ        18
+#define COBALT_CPU_IRQ          16
-#define COBALT_SCC_IRQ          19              /* pre-production has 85C30 */
-#define COBALT_RAQ_SCSI_IRQ     19
+#define COBALT_GALILEO_IRQ      (COBALT_CPU_IRQ + 2)
-#define COBALT_ETH0_IRQ         19
+#define COBALT_SCC_IRQ          (COBALT_CPU_IRQ + 3)    /* pre-production has 85C30 */
-#define COBALT_ETH1_IRQ         20
+#define COBALT_RAQ_SCSI_IRQ     (COBALT_CPU_IRQ + 3)
-#define COBALT_SERIAL_IRQ       21
+#define COBALT_ETH0_IRQ         (COBALT_CPU_IRQ + 3)
-#define COBALT_SCSI_IRQ         21
+#define COBALT_QUBE1_ETH0_IRQ   (COBALT_CPU_IRQ + 4)
-#define COBALT_VIA_IRQ          22              /* Chained to VIA ISA bridge */
+#define COBALT_ETH1_IRQ         (COBALT_CPU_IRQ + 4)
-#define COBALT_QUBE_SLOT_IRQ    23
+#define COBALT_SERIAL_IRQ       (COBALT_CPU_IRQ + 5)
+#define COBALT_SCSI_IRQ         (COBALT_CPU_IRQ + 5)
+#define COBALT_VIA_IRQ          (COBALT_CPU_IRQ + 6)    /* Chained to VIA ISA bridge */
 /*
 * PCI configuration space manifest constants.  These are wired into
@@ -69,16 +74,21 @@
 * Most of this really should go into a separate GT64111 header file.
 */
 #define GT64111_IO_BASE         0x10000000UL
+#define GT64111_IO_END          0x11ffffffUL
+#define GT64111_MEM_BASE        0x12000000UL
+#define GT64111_MEM_END         0x13ffffffUL
 #define GT64111_BASE            0x14000000UL
-#define GALILEO_REG(ofs)        (KSEG0 + GT64111_BASE + (unsigned long)(ofs))
+#define GALILEO_REG(ofs)        CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
 #define GALILEO_INL(port)       (*(volatile unsigned int *) GALILEO_REG(port))
 #define GALILEO_OUTL(val, port)                                         \
 do {                                                                    \
-        *(volatile unsigned int *) GALILEO_REG(port) = (port);          \
+        *(volatile unsigned int *) GALILEO_REG(port) = (val);           \
 } while (0)
-#define GALILEO_T0EXP           0x0100
+#define GALILEO_INTR_T0EXP      (1 << 8)
+#define GALILEO_INTR_RETRY_CTR  (1 << 20)
 #define GALILEO_ENTC0           0x01
 #define GALILEO_SELTC0          0x02
@@ -86,5 +96,21 @@ do {									\
        GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) |           \
                (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
+#define COBALT_LED_PORT         (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
+# define COBALT_LED_BAR_LEFT    (1 << 0)        /* Qube */
+# define COBALT_LED_BAR_RIGHT   (1 << 1)        /* Qube */
+# define COBALT_LED_WEB         (1 << 2)        /* RaQ */
+# define COBALT_LED_POWER_OFF   (1 << 3)        /* RaQ */
+# define COBALT_LED_RESET       0x0f
+#define COBALT_KEY_PORT         ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
+# define COBALT_KEY_CLEAR       (1 << 1)
+# define COBALT_KEY_LEFT        (1 << 2)
+# define COBALT_KEY_UP          (1 << 3)
+# define COBALT_KEY_DOWN        (1 << 4)
+# define COBALT_KEY_RIGHT       (1 << 5)
+# define COBALT_KEY_ENTER       (1 << 6)
+# define COBALT_KEY_SELECT      (1 << 7)
+# define COBALT_KEY_MASK        0xfe
 #endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/cobalt/mach-gt64120.h b/include/asm-mips/cobalt/mach-gt64120.h
new file mode 100644
index 000000000000..587fc4378f44
--- /dev/null
+++ b/include/asm-mips/cobalt/mach-gt64120.h
@@ -0,0 +1 @@
+/* there's something here ... in the dark */
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
index 2c084cd4bc0a..35d2604fe69c 100644
--- a/include/asm-mips/compat.h
+++ b/include/asm-mips/compat.h
@@ -15,10 +15,10 @@ typedef s32		compat_clock_t;
 typedef s32             compat_suseconds_t;
 typedef s32             compat_pid_t;
-typedef u32             __compat_uid_t;
+typedef s32             __compat_uid_t;
-typedef u32             __compat_gid_t;
+typedef s32             __compat_gid_t;
-typedef u32             __compat_uid32_t;
+typedef __compat_uid_t  __compat_uid32_t;
-typedef u32             __compat_gid32_t;
+typedef __compat_gid_t  __compat_gid32_t;
 typedef u32             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u32             compat_dev_t;
@@ -54,8 +54,8 @@ struct compat_stat {
        compat_ino_t    st_ino;
        compat_mode_t   st_mode;
        compat_nlink_t  st_nlink;
-        __compat_uid32_t        st_uid;
+        __compat_uid_t  st_uid;
-        __compat_gid32_t        st_gid;
+        __compat_gid_t  st_gid;
        compat_dev_t    st_rdev;
        s32             st_pad2[2];
        compat_off_t    st_size;
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 9a2de642eee6..03627cfb3e45 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -4,6 +4,7 @@
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
 */
 #ifndef __ASM_CPU_FEATURES_H
 #define __ASM_CPU_FEATURES_H
@@ -24,8 +25,19 @@
 #ifndef cpu_has_4kex
 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
 #endif
-#ifndef cpu_has_4ktlb
+#ifndef cpu_has_3k_cache
-#define cpu_has_4ktlb           (cpu_data[0].options & MIPS_CPU_4KTLB)
+#define cpu_has_3k_cache        (cpu_data[0].options & MIPS_CPU_3K_CACHE)
+#endif
+#define cpu_has_6k_cache        0
+#define cpu_has_8k_cache        0
+#ifndef cpu_has_4k_cache
+#define cpu_has_4k_cache        (cpu_data[0].options & MIPS_CPU_4K_CACHE)
+#endif
+#ifndef cpu_has_tx39_cache
+#define cpu_has_tx39_cache      (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
+#endif
+#ifndef cpu_has_sb1_cache
+#define cpu_has_sb1_cache       (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
 #endif
 #ifndef cpu_has_fpu
 #define cpu_has_fpu             (cpu_data[0].options & MIPS_CPU_FPU)
@@ -39,9 +51,6 @@
 #ifndef cpu_has_watch
 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
 #endif
-#ifndef cpu_has_mips16
-#define cpu_has_mips16          (cpu_data[0].options & MIPS_CPU_MIPS16)
-#endif
 #ifndef cpu_has_divec
 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
 #endif
@@ -66,6 +75,18 @@
 #ifndef cpu_has_llsc
 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
 #endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
+#endif
+#ifndef cpu_has_mdmx
+#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
+#endif
+#ifndef cpu_has_mips3d
+#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#endif
+#ifndef cpu_has_smartmips
+#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 #endif
@@ -95,15 +116,16 @@
 #endif
 #endif
-/*
+#ifndef cpu_has_dsp
- * Certain CPUs may throw bizarre exceptions if not the whole cacheline
+#define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
- * contains valid instructions.  For these we ensure proper alignment of
+#endif
- * signal trampolines and pad them to the size of a full cache lines with
- * nops.  This is also used in structure definitions so can't be a test macro
+#ifdef CONFIG_MIPS_MT
- * like the others.
+#ifndef cpu_has_mipsmt
- */
+# define cpu_has_mipsmt         (cpu_data[0].ases & MIPS_ASE_MIPSMT)
-#ifndef PLAT_TRAMPOLINE_STUFF_LINE
+#endif
-#define PLAT_TRAMPOLINE_STUFF_LINE      0UL
+#else
+# define cpu_has_mipsmt         0
 #endif
 #ifdef CONFIG_32BIT
@@ -142,6 +164,22 @@
 # endif
 #endif
+#ifdef CONFIG_CPU_MIPSR2
+# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
+#  define cpu_has_vint          (cpu_data[0].options & MIPS_CPU_VINT)
+# else
+#  define cpu_has_vint                  0
+# endif
+# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
+#  define cpu_has_veic          (cpu_data[0].options & MIPS_CPU_VEIC)
+# else
+#  define cpu_has_veic                  0
+# endif
+#else
+# define cpu_has_vint                   0
+# define cpu_has_veic                   0
+#endif
 #ifndef cpu_has_subset_pcaches
 #define cpu_has_subset_pcaches  (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
 #endif
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 20a35b15a31d..d5cf519f8fcc 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -7,6 +7,7 @@
 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004  Maciej W. Rozycki
 */
 #ifndef __ASM_CPU_INFO_H
 #define __ASM_CPU_INFO_H
@@ -61,6 +62,7 @@ struct cpuinfo_mips {
         * Capability and feature descriptor structure for MIPS CPU
         */
        unsigned long           options;
+        unsigned long           ases;
        unsigned int            processor_id;
        unsigned int            fpu_id;
        unsigned int            cputype;
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index dec060b49556..48eac296060f 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -3,6 +3,7 @@
 *        various MIPS cpu types.
 *
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 2004  Maciej W. Rozycki
 */
 #ifndef _ASM_CPU_H
 #define _ASM_CPU_H
@@ -22,12 +23,17 @@
   spec.
 */
-#define PRID_COMP_LEGACY       0x000000
+#define PRID_COMP_LEGACY        0x000000
-#define PRID_COMP_MIPS         0x010000
+#define PRID_COMP_MIPS          0x010000
-#define PRID_COMP_BROADCOM     0x020000
+#define PRID_COMP_BROADCOM      0x020000
-#define PRID_COMP_ALCHEMY      0x030000
+#define PRID_COMP_ALCHEMY       0x030000
-#define PRID_COMP_SIBYTE       0x040000
+#define PRID_COMP_SIBYTE        0x040000
-#define PRID_COMP_SANDCRAFT    0x050000
+#define PRID_COMP_SANDCRAFT     0x050000
+#define PRID_COMP_PHILIPS       0x060000
+#define PRID_COMP_TOSHIBA       0x070000
+#define PRID_COMP_LSI           0x080000
+#define PRID_COMP_LEXRA         0x0b0000
 /*
 * Assigned values for the product ID register.  In order to detect a
@@ -46,6 +52,7 @@
 #define PRID_IMP_VR41XX         0x0c00
 #define PRID_IMP_R12000         0x0e00
 #define PRID_IMP_R8000          0x1000
+#define PRID_IMP_PR4450         0x1200
 #define PRID_IMP_R4600          0x2000
 #define PRID_IMP_R4700          0x2100
 #define PRID_IMP_TX39           0x2200
@@ -60,6 +67,13 @@
 #define PRID_IMP_RM9000         0x3400
 #define PRID_IMP_R5432          0x5400
 #define PRID_IMP_R5500          0x5500
+#define PRID_IMP_UNKNOWN        0xff00
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_MIPS
+ */
 #define PRID_IMP_4KC            0x8000
 #define PRID_IMP_5KC            0x8100
 #define PRID_IMP_20KC           0x8200
@@ -71,14 +85,15 @@
 #define PRID_IMP_4KEMPR2        0x9100
 #define PRID_IMP_4KSD           0x9200
 #define PRID_IMP_24K            0x9300
+#define PRID_IMP_34K            0x9500
-#define PRID_IMP_UNKNOWN        0xff00
+#define PRID_IMP_24KE           0x9600
 /*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 */
 #define PRID_IMP_SB1            0x0100
+#define PRID_IMP_SB1A           0x1100
 /*
 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
@@ -177,7 +192,11 @@
 #define CPU_VR4133              56
 #define CPU_AU1550              57
 #define CPU_24K                 58
-#define CPU_LAST                58
+#define CPU_AU1200              59
+#define CPU_34K                 60
+#define CPU_PR4450              61
+#define CPU_SB1A                62
+#define CPU_LAST                62
 /*
 * ISA Level encodings
@@ -200,23 +219,37 @@
 * CPU Option encodings
 */
 #define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
-/* Leave a spare bit for variant MMU types... */
+#define MIPS_CPU_4KEX           0x00000002 /* "R4K" exception model */
-#define MIPS_CPU_4KEX           0x00000004 /* "R4K" exception model */
+#define MIPS_CPU_3K_CACHE       0x00000004 /* R3000-style caches */
-#define MIPS_CPU_4KTLB          0x00000008 /* "R4K" TLB handler */
+#define MIPS_CPU_4K_CACHE       0x00000008 /* R4000-style caches */
-#define MIPS_CPU_FPU            0x00000010 /* CPU has FPU */
+#define MIPS_CPU_TX39_CACHE     0x00000010 /* TX3900-style caches */
-#define MIPS_CPU_32FPR          0x00000020 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_SB1_CACHE      0x00000020 /* SB1-style caches */
-#define MIPS_CPU_COUNTER        0x00000040 /* Cycle count/compare */
+#define MIPS_CPU_FPU            0x00000040 /* CPU has FPU */
-#define MIPS_CPU_WATCH          0x00000080 /* watchpoint registers */
+#define MIPS_CPU_32FPR          0x00000080 /* 32 dbl. prec. FP registers */
-#define MIPS_CPU_MIPS16         0x00000100 /* code compression */
+#define MIPS_CPU_COUNTER        0x00000100 /* Cycle count/compare */
-#define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
+#define MIPS_CPU_WATCH          0x00000200 /* watchpoint registers */
-#define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
+#define MIPS_CPU_DIVEC          0x00000400 /* dedicated interrupt vector */
-#define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_VCE            0x00000800 /* virt. coherence conflict possible */
-#define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
+#define MIPS_CPU_CACHE_CDEX_P   0x00001000 /* Create_Dirty_Exclusive CACHE op */
-#define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
+#define MIPS_CPU_CACHE_CDEX_S   0x00002000 /* ... same for seconary cache ... */
-#define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
+#define MIPS_CPU_MCHECK         0x00004000 /* Machine check exception */
-#define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
+#define MIPS_CPU_EJTAG          0x00008000 /* EJTAG exception */
-#define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
+#define MIPS_CPU_NOFPUEX        0x00010000 /* no FPU exception */
-#define MIPS_CPU_SUBSET_CACHES  0x00020000 /* P-cache subset enforced */
+#define MIPS_CPU_LLSC           0x00020000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
+#define MIPS_CPU_SUBSET_CACHES  0x00040000 /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH       0x00080000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT           0x00100000 /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC           0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
+/*
+ * CPU ASE encodings
+ */
+#define MIPS_ASE_MIPS16         0x00000001 /* code compression */
+#define MIPS_ASE_MDMX           0x00000002 /* MIPS digital media extension */
+#define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
+#define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
+#define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
+#define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
 #endif /* _ASM_CPU_H */
diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h
index 724908b0bf13..19495a490e72 100644
--- a/include/asm-mips/dec/ecc.h
+++ b/include/asm-mips/dec/ecc.h
@@ -49,7 +49,8 @@ struct pt_regs;
 extern void dec_ecc_be_init(void);
 extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id,
+                                        struct pt_regs *regs);
 #endif
 #endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h
index 5e18a7510592..4cbc1f8a1129 100644
--- a/include/asm-mips/dec/ioasic_addrs.h
+++ b/include/asm-mips/dec/ioasic_addrs.h
@@ -45,7 +45,8 @@
 /*
- * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)).
+ * Offsets for I/O ASIC registers
+ * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
 */
                                        /* all systems */
 #define IO_REG_SCSI_DMA_P       0x00    /* SCSI DMA Pointer */
diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h
index 946943502f83..eb522aa1e226 100644
--- a/include/asm-mips/dec/kn01.h
+++ b/include/asm-mips/dec/kn01.h
@@ -8,14 +8,12 @@
 *
 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
 * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
 */
 #ifndef __ASM_MIPS_DEC_KN01_H
 #define __ASM_MIPS_DEC_KN01_H
-#include <asm/addrspace.h>
+#define KN01_SLOT_BASE  0x10000000
-#define KN01_SLOT_BASE  KSEG1ADDR(0x10000000)
 #define KN01_SLOT_SIZE  0x01000000
 /*
@@ -41,17 +39,9 @@
 /*
- * Some port addresses...
- */
-#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE)   /* 0xB8000000 */
-#define KN01_DZ11_BASE  (KN01_SLOT_BASE + KN01_DZ11)    /* 0xBC000000 */
-#define KN01_RTC_BASE   (KN01_SLOT_BASE + KN01_RTC)     /* 0xBD000000 */
-/*
 * Frame buffer memory address.
 */
-#define KN01_VFB_MEM    KSEG1ADDR(0x0fc00000)
+#define KN01_VFB_MEM    0x0fc00000
 /*
 * CPU interrupt bits.
@@ -80,4 +70,22 @@
 #define KN01_CSR_VRGTRB         (1<<0)  /* red DAC voltage over blue (r/o) */
 #define KN01_CSR_LEDS           (0xff<<0) /* ~diagnostic LEDs (w/o) */
+#ifndef __ASSEMBLY__
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+struct pt_regs;
+extern u16 cached_kn01_csr;
+extern spinlock_t kn01_lock;
+extern void dec_kn01_be_init(void);
+extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
+                                         struct pt_regs *regs);
+#endif
 #endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
index f797f7045920..8319ad77b250 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/include/asm-mips/dec/kn02.h
@@ -8,21 +8,12 @@
 *
 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
 * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
 */
 #ifndef __ASM_MIPS_DEC_KN02_H
 #define __ASM_MIPS_DEC_KN02_H
-#ifndef __ASSEMBLY__
+#define KN02_SLOT_BASE  0x1fc00000
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#endif
-#include <asm/addrspace.h>
-#include <asm/dec/ecc.h>
-#define KN02_SLOT_BASE  KSEG1ADDR(0x1fc00000)
 #define KN02_SLOT_SIZE  0x00080000
 /*
@@ -39,22 +30,14 @@
 /*
- * Some port addresses...
- */
-#define KN02_DZ11_BASE  (KN02_SLOT_BASE + KN02_DZ11)    /* DZ11 */
-#define KN02_RTC_BASE   (KN02_SLOT_BASE + KN02_RTC)     /* RTC */
-#define KN02_CSR_BASE   (KN02_SLOT_BASE + KN02_CSR)     /* CSR */
-/*
 * System Control & Status Register bits.
 */
 #define KN02_CSR_RES_28         (0xf<<28)       /* unused */
 #define KN02_CSR_PSU            (1<<27)         /* power supply unit warning */
 #define KN02_CSR_NVRAM          (1<<26)         /* ~NVRAM clear jumper */
 #define KN02_CSR_REFEVEN        (1<<25)         /* mem refresh bank toggle */
-#define KN03_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
+#define KN02_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
-#define KN03_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
+#define KN02_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
 #define KN02_CSR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
 #define KN02_CSR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
 #define KN02_CSR_CORRECT        (1<<13)         /* ECC correct/check */
@@ -63,8 +46,8 @@
 #define KN02_CSR_BNK32M         (1<<10)         /* 32M/8M stride */
 #define KN02_CSR_DIAGDN         (1<<9)          /* DIAGDN manufact. jumper */
 #define KN02_CSR_BAUD38         (1<<8)          /* DZ11 38/19kbps ext. rate */
-#define KN03_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
+#define KN02_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
-#define KN03_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
+#define KN02_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
 /*
@@ -98,6 +81,10 @@
 #ifndef __ASSEMBLY__
+#include <linux/spinlock.h>
+#include <linux/types.h>
 extern u32 cached_kn02_csr;
 extern spinlock_t kn02_lock;
 extern void init_kn02_irqs(int base);
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
index 648c4dcbba1d..a25f3d7da7f7 100644
--- a/include/asm-mips/dec/kn02xa.h
+++ b/include/asm-mips/dec/kn02xa.h
@@ -9,7 +9,7 @@
 *
 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
 * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
 *
 * These are addresses which have to be known early in the boot process.
 * For other addresses refer to tc.h, ioasic_addrs.h and friends.
@@ -17,31 +17,23 @@
 #ifndef __ASM_MIPS_DEC_KN02XA_H
 #define __ASM_MIPS_DEC_KN02XA_H
-#include <asm/addrspace.h>
 #include <asm/dec/ioasic_addrs.h>
-#define KN02XA_SLOT_BASE        KSEG1ADDR(0x1c000000)
+#define KN02XA_SLOT_BASE        0x1c000000
-/*
- * Some port addresses...
- */
-#define KN02XA_IOASIC_BASE    (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
-#define KN02XA_RTC_BASE         (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
 /*
 * Memory control ASIC registers.
 */
-#define KN02XA_MER      KSEG1ADDR(0x0c400000)   /* memory error register */
+#define KN02XA_MER              0x0c400000      /* memory error register */
-#define KN02XA_MSR      KSEG1ADDR(0x0c800000)   /* memory size register */
+#define KN02XA_MSR              0x0c800000      /* memory size register */
 /*
 * CPU control ASIC registers.
 */
-#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000)   /* write timeout config */
+#define KN02XA_MEM_CONF         0x0e000000      /* write timeout config */
-#define KN02XA_EAR      KSEG1ADDR(0x0e000004)   /* error address register */
+#define KN02XA_EAR              0x0e000004      /* error address register */
-#define KN02XA_BOOT0    KSEG1ADDR(0x0e000008)   /* boot 0 register */
+#define KN02XA_BOOT0            0x0e000008      /* boot 0 register */
-#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c)   /* write err IRQ stat & ack */
+#define KN02XA_MEM_INTR         0x0e00000c      /* write err IRQ stat & ack */
 /*
 * Memory Error Register bits, common definitions.
@@ -52,8 +44,13 @@
 #define KN02XA_MER_PAGERR       (1<<16)         /* 2k page boundary error */
 #define KN02XA_MER_TRANSERR     (1<<15)         /* transfer length error */
 #define KN02XA_MER_PARDIS       (1<<14)         /* parity error disable */
-#define KN02XA_MER_RES_12       (0x3<<12)       /* unused */
+#define KN02XA_MER_SIZE         (1<<13)         /* r/o mirror of MSR_SIZE */
-#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask */
+#define KN02XA_MER_RES_12       (1<<12)         /* unused */
+#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask: */
+#define KN02XA_MER_BYTERR_3     (0x8<<8)        /* byte lane #3 */
+#define KN02XA_MER_BYTERR_2     (0x4<<8)        /* byte lane #2 */
+#define KN02XA_MER_BYTERR_1     (0x2<<8)        /* byte lane #1 */
+#define KN02XA_MER_BYTERR_0     (0x1<<8)        /* byte lane #0 */
 #define KN02XA_MER_RES_0        (0xff<<0)       /* unused */
 /*
@@ -72,4 +69,17 @@
 #define KN02XA_EAR_ADDRESS      (0x7ffffff<<2)  /* address involved */
 #define KN02XA_EAR_RES_0        (0x3<<0)        /* unused */
+#ifndef __ASSEMBLY__
+#include <linux/interrupt.h>
+struct pt_regs;
+extern void dec_kn02xa_be_init(void);
+extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
+                                           struct pt_regs *regs);
+#endif
 #endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h
index 676abd17c6a4..edede923ffb8 100644
--- a/include/asm-mips/dec/kn03.h
+++ b/include/asm-mips/dec/kn03.h
@@ -10,24 +10,15 @@
 *
 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
 * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
 */
 #ifndef __ASM_MIPS_DEC_KN03_H
 #define __ASM_MIPS_DEC_KN03_H
-#include <asm/addrspace.h>
 #include <asm/dec/ecc.h>
 #include <asm/dec/ioasic_addrs.h>
-#define KN03_SLOT_BASE  KSEG1ADDR(0x1f800000)
+#define KN03_SLOT_BASE          0x1f800000
-/*
- * Some port addresses...
- */
-#define KN03_IOASIC_BASE        (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
-#define KN03_RTC_BASE           (KN03_SLOT_BASE + IOASIC_TOY)   /* RTC */
-#define KN03_MCR_BASE           (KN03_SLOT_BASE + IOASIC_MCR)   /* MCR */
 /*
 * CPU interrupt bits.
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
index b120362b8f13..15fe8f881e60 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/include/asm-mips/dec/kn05.h
@@ -1,10 +1,12 @@
 /*
 *      include/asm-mips/dec/kn05.h
 *
- *      DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260
+ *      DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
+ *      or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
+ *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
 *      definitions.
 *
- *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *      Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
 *
 *      This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
@@ -13,8 +15,8 @@
 *
 *      WARNING!  All this information is pure guesswork based on the
 *      ROM.  It is provided here in hope it will give someone some
- *      food for thought.  No documentation for the KN05 module has
+ *      food for thought.  No documentation for the KN05 nor the KN04
- *      been located so far.
+ *      module has been located so far.
 */
 #ifndef __ASM_MIPS_DEC_KN05_H
 #define __ASM_MIPS_DEC_KN05_H
@@ -24,48 +26,50 @@
 /*
 * The oncard MB (Memory Buffer) ASIC provides an additional address
 * decoder.  Certain address ranges within the "high" 16 slots are
- * passed to the I/O ASIC's decoder like with the KN03.  Others are
+ * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
- * handled locally.  "Low" slots are always passed.
+ * Others are handled locally.  "Low" slots are always passed.
 */
-#define KN05_MB_ROM     (16*IOASIC_SLOT_SIZE)   /* KN05 card ROM */
+#define KN4K_SLOT_BASE  0x1fc00000
-#define KN05_IOCTL      (17*IOASIC_SLOT_SIZE)   /* I/O ASIC */
-#define KN05_ESAR       (18*IOASIC_SLOT_SIZE)   /* LANCE MAC address chip */
+#define KN4K_MB_ROM     (0*IOASIC_SLOT_SIZE)    /* KN05/KN04 card ROM */
-#define KN05_LANCE      (19*IOASIC_SLOT_SIZE)   /* LANCE Ethernet */
+#define KN4K_IOCTL      (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
-#define KN05_MB_INT     (20*IOASIC_SLOT_SIZE)   /* MB interrupt register */
+#define KN4K_ESAR       (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
-#define KN05_MB_EA      (21*IOASIC_SLOT_SIZE)   /* MB error address? */
+#define KN4K_LANCE      (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
-#define KN05_MB_EC      (22*IOASIC_SLOT_SIZE)   /* MB error ??? */
+#define KN4K_MB_INT     (4*IOASIC_SLOT_SIZE)    /* MB interrupt register */
-#define KN05_MB_CSR     (23*IOASIC_SLOT_SIZE)   /* MB control & status */
+#define KN4K_MB_EA      (5*IOASIC_SLOT_SIZE)    /* MB error address? */
-#define KN05_RES_24     (24*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_MB_EC      (6*IOASIC_SLOT_SIZE)    /* MB error ??? */
-#define KN05_RES_25     (25*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_MB_CSR     (7*IOASIC_SLOT_SIZE)    /* MB control & status */
-#define KN05_RES_26     (26*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_08     (8*IOASIC_SLOT_SIZE)    /* unused? */
-#define KN05_RES_27     (27*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_09     (9*IOASIC_SLOT_SIZE)    /* unused? */
-#define KN05_SCSI       (28*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define KN4K_RES_10     (10*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_29     (29*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_11     (11*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN05_RES_30     (30*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_SCSI       (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
-#define KN05_RES_31     (31*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_13     (13*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_14     (14*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_15     (15*IOASIC_SLOT_SIZE)   /* unused? */
 /*
 * Bits for the MB interrupt register.
 * The register appears read-only.
 */
-#define KN05_MB_INT_TC          (1<<0)          /* TURBOchannel? */
+#define KN4K_MB_INT_TC          (1<<0)          /* TURBOchannel? */
-#define KN05_MB_INT_RTC         (1<<1)          /* RTC? */
+#define KN4K_MB_INT_RTC         (1<<1)          /* RTC? */
-#define KN05_MB_INT_MT          (1<<3)          /* ??? */
+#define KN4K_MB_INT_MT          (1<<3)          /* ??? */
 /*
 * Bits for the MB control & status register.
 * Set to 0x00bf8001 on my system by the ROM.
 */
-#define KN05_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
+#define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
-#define KN05_MB_CSR_F           (1<<1)          /* ??? */
+#define KN4K_MB_CSR_F           (1<<1)          /* ??? */
-#define KN05_MB_CSR_ECC         (0xff<<2)       /* ??? */
+#define KN4K_MB_CSR_ECC         (0xff<<2)       /* ??? */
-#define KN05_MB_CSR_OD          (1<<10)         /* ??? */
+#define KN4K_MB_CSR_OD          (1<<10)         /* ??? */
-#define KN05_MB_CSR_CP          (1<<11)         /* ??? */
+#define KN4K_MB_CSR_CP          (1<<11)         /* ??? */
-#define KN05_MB_CSR_UNC         (1<<12)         /* ??? */
+#define KN4K_MB_CSR_UNC         (1<<12)         /* ??? */
-#define KN05_MB_CSR_IM          (1<<13)         /* ??? */
+#define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
-#define KN05_MB_CSR_NC          (1<<14)         /* ??? */
+#define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
-#define KN05_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
+#define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
-#define KN05_MB_CSR_MSK         (0x1f<<16)      /* ??? */
+#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* ??? */
-#define KN05_MB_CSR_FW          (1<<21)         /* ??? */
+#define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
 #endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h
index a05d6d3395fe..1384dd0964b9 100644
--- a/include/asm-mips/dec/prom.h
+++ b/include/asm-mips/dec/prom.h
@@ -24,7 +24,7 @@
 * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
 * Many of these will work for MIPSen as well!
 */
-#define VEC_RESET               (u64 *)KSEG1ADDR(0x1fc00000)
+#define VEC_RESET               (u64 *)CKSEG1ADDR(0x1fc00000)
                                                        /* Prom base address */
 #define PMAX_PROM_ENTRY(x)      (VEC_RESET + (x))       /* Prom jump table */
@@ -111,19 +111,21 @@ extern int (*__pmax_close)(int);
 * On MIPS64 we have to call PROM functions via a helper
 * dispatcher to accomodate ABI incompatibilities.
 */
-#define __DEC_PROM_O32 __attribute__((alias("call_o32")))
+#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
+                                 __asm__(#fun " = call_o32")
-int _rex_bootinit(int (*)(void)) __DEC_PROM_O32;
-int _rex_bootread(int (*)(void)) __DEC_PROM_O32;
+int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
-int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32;
+int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
-unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32;
+int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
-void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32;
+unsigned long *__DEC_PROM_O32(_rex_slot_address,
-int _rex_getsysid(int (*)(void)) __DEC_PROM_O32;
+                             (unsigned long *(*)(int), int));
-void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32;
+void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
+int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
-int _prom_getchar(int (*)(void)) __DEC_PROM_O32;
+void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
-char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32;
-int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
+int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
+char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
+int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
 #define rex_bootinit()          _rex_bootinit(__rex_bootinit)
diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h
new file mode 100644
index 000000000000..78af51fbc797
--- /dev/null
+++ b/include/asm-mips/dec/system.h
@@ -0,0 +1,18 @@
+/*
+ *      include/asm-mips/dec/system.h
+ *
+ *      Generic DECstation/DECsystem bits.
+ *
+ *      Copyright (C) 2005  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_DEC_SYSTEM_H
+#define __ASM_DEC_SYSTEM_H
+extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
+#endif /* __ASM_DEC_SYSTEM_H */
diff --git a/include/asm-mips/dec/tc.h b/include/asm-mips/dec/tc.h
index d7bba43f863a..9cb51f24d42c 100644
--- a/include/asm-mips/dec/tc.h
+++ b/include/asm-mips/dec/tc.h
@@ -7,10 +7,8 @@
 *
 * Copyright (c) 1998 Harald Koerfgen
 */
-#ifndef ASM_TC_H
+#ifndef __ASM_DEC_TC_H
-#define ASM_TC_H
+#define __ASM_DEC_TC_H
-extern unsigned long system_base;
 /*
 * Search for a TURBOchannel Option Module
@@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(int);
 */
 extern unsigned long get_tc_irq_nr(int);
 /*
- * Return TURBOchannel clock frequency in hz
+ * Return TURBOchannel clock frequency in Hz
 */
 extern unsigned long get_tc_speed(void);
-#endif
+#endif /* __ASM_DEC_TC_H */
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index a606dbee0412..85435a8d4e52 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -12,11 +12,9 @@
 #include <linux/config.h>
 #include <linux/param.h>
+#include <linux/smp.h>
 #include <asm/compiler.h>
-extern unsigned long loops_per_jiffy;
 static inline void __delay(unsigned long loops)
 {
        if (sizeof(long) == 4)
@@ -82,11 +80,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
        __delay(usecs);
 }
-#ifdef CONFIG_SMP
 #define __udelay_val cpu_data[smp_processor_id()].udelay_val
-#else
-#define __udelay_val loops_per_jiffy
-#endif
 #define udelay(usecs) __udelay((usecs),__udelay_val)
diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h
new file mode 100644
index 000000000000..50f556bb4978
--- /dev/null
+++ b/include/asm-mips/dsp.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2005 Mips Technologies
+ * Author: Chris Dearman, chris@mips.com derived from fpu.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_DSP_H
+#define _ASM_DSP_H
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/hazards.h>
+#include <asm/mipsregs.h>
+#define DSP_DEFAULT     0x00000000
+#define DSP_MASK        0x1f
+#define __enable_dsp_hazard()                                           \
+do {                                                                    \
+        asm("_ehb");                                                    \
+} while (0)
+static inline void __init_dsp(void)
+{
+        mthi1(0);
+        mtlo1(0);
+        mthi2(0);
+        mtlo2(0);
+        mthi3(0);
+        mtlo3(0);
+        wrdsp(DSP_DEFAULT, DSP_MASK);
+}
+static inline void init_dsp(void)
+{
+        if (cpu_has_dsp)
+                __init_dsp();
+}
+#define __save_dsp(tsk)                                                 \
+do {                                                                    \
+        tsk->thread.dsp.dspr[0] = mfhi1();                              \
+        tsk->thread.dsp.dspr[1] = mflo1();                              \
+        tsk->thread.dsp.dspr[2] = mfhi2();                              \
+        tsk->thread.dsp.dspr[3] = mflo2();                              \
+        tsk->thread.dsp.dspr[4] = mfhi3();                              \
+        tsk->thread.dsp.dspr[5] = mflo3();                              \
+} while (0)
+#define save_dsp(tsk)                                                   \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __save_dsp(tsk);                                        \
+} while (0)
+#define __restore_dsp(tsk)                                              \
+do {                                                                    \
+        mthi1(tsk->thread.dsp.dspr[0]);                                 \
+        mtlo1(tsk->thread.dsp.dspr[1]);                                 \
+        mthi2(tsk->thread.dsp.dspr[2]);                                 \
+        mtlo2(tsk->thread.dsp.dspr[3]);                                 \
+        mthi3(tsk->thread.dsp.dspr[4]);                                 \
+        mtlo3(tsk->thread.dsp.dspr[5]);                                 \
+} while (0)
+#define restore_dsp(tsk)                                                \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __restore_dsp(tsk);                                     \
+} while (0)
+#define __get_dsp_regs(tsk)                                             \
+({                                                                      \
+        if (tsk == current)                                             \
+                __save_dsp(current);                                    \
+                                                                        \
+        tsk->thread.dsp.dspr;                                           \
+})
+#endif /* _ASM_DSP_H */
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index e48811440015..7420f12742bb 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -2,6 +2,8 @@
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
+ *
+ * Much of this is taken from binutils and GNU libc ...
 */
 #ifndef _ASM_ELF_H
 #define _ASM_ELF_H
@@ -17,6 +19,8 @@
 #define EF_MIPS_ARCH_5          0x40000000      /* -mips5 code.  */
 #define EF_MIPS_ARCH_32         0x50000000      /* MIPS32 code.  */
 #define EF_MIPS_ARCH_64         0x60000000      /* MIPS64 code.  */
+#define EF_MIPS_ARCH_32R2       0x70000000      /* MIPS32 R2 code.  */
+#define EF_MIPS_ARCH_64R2       0x80000000      /* MIPS64 R2 code.  */
 /* The ABI of a file. */
 #define EF_MIPS_ABI_O32         0x00001000      /* O32 ABI.  */
@@ -105,7 +109,11 @@
 #define R_MIPS_LOVENDOR         100
 #define R_MIPS_HIVENDOR         127
-#define SHN_MIPS_ACCOMON        0xff00
+#define SHN_MIPS_ACCOMON        0xff00          /* Allocated common symbols */
+#define SHN_MIPS_TEXT           0xff01          /* Allocated test symbols.  */
+#define SHN_MIPS_DATA           0xff02          /* Allocated data symbols.  */
+#define SHN_MIPS_SCOMMON        0xff03          /* Small common symbols */
+#define SHN_MIPS_SUNDEFINED     0xff04          /* Small undefined symbols */
 #define SHT_MIPS_LIST           0x70000000
 #define SHT_MIPS_CONFLICT       0x70000002
@@ -193,50 +201,92 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 #ifdef __KERNEL__
+struct mips_abi;
+extern struct mips_abi mips_abi;
+extern struct mips_abi mips_abi_32;
+extern struct mips_abi mips_abi_n32;
 #ifdef CONFIG_32BIT
-#define SET_PERSONALITY(ex, ibcs2)                      \
+#define SET_PERSONALITY(ex, ibcs2)                                      \
-do {                                                    \
+do {                                                                    \
-        if (ibcs2)                                      \
+        if (ibcs2)                                                      \
-                set_personality(PER_SVR4);              \
+                set_personality(PER_SVR4);                              \
-        set_personality(PER_LINUX);                     \
+        set_personality(PER_LINUX);                                     \
+                                                                        \
+        current->thread.abi = &mips_abi;                                \
 } while (0)
 #endif /* CONFIG_32BIT */
 #ifdef CONFIG_64BIT
-#define SET_PERSONALITY(ex, ibcs2)                              \
+#ifdef CONFIG_MIPS32_N32
-do {    current->thread.mflags &= ~MF_ABI_MASK;                 \
+#define __SET_PERSONALITY32_N32()                                       \
-        if ((ex).e_ident[EI_CLASS] == ELFCLASS32) {             \
+        do {                                                            \
-                if ((((ex).e_flags & EF_MIPS_ABI2) != 0) &&     \
+                current->thread.mflags |= MF_N32;                       \
-                     ((ex).e_flags & EF_MIPS_ABI) == 0)         \
+                current->thread.abi = &mips_abi_n32;                    \
-                        current->thread.mflags |= MF_N32;       \
+        } while (0)
-                else                                            \
+#else
-                        current->thread.mflags |= MF_O32;       \
+#define __SET_PERSONALITY32_N32()                                       \
-        } else                                                  \
+        do { } while (0)
-                current->thread.mflags |= MF_N64;               \
+#endif
-        if (ibcs2)                                              \
-                set_personality(PER_SVR4);                      \
+#ifdef CONFIG_MIPS32_O32
-        else if (current->personality != PER_LINUX32)           \
+#define __SET_PERSONALITY32_O32()                                       \
-                set_personality(PER_LINUX);                     \
+        do {                                                            \
+                current->thread.mflags |= MF_O32;                       \
+                current->thread.abi = &mips_abi_32;                     \
+        } while (0)
+#else
+#define __SET_PERSONALITY32_O32()                                       \
+        do { } while (0)
+#endif
+#ifdef CONFIG_MIPS32_COMPAT
+#define __SET_PERSONALITY32(ex)                                         \
+do {                                                                    \
+        if ((((ex).e_flags & EF_MIPS_ABI2) != 0) &&                     \
+             ((ex).e_flags & EF_MIPS_ABI) == 0)                         \
+                __SET_PERSONALITY32_N32();                              \
+        else                                                            \
+                __SET_PERSONALITY32_O32();                              \
+} while (0)
+#else
+#define __SET_PERSONALITY32(ex) do { } while (0)
+#endif
+#define SET_PERSONALITY(ex, ibcs2)                                      \
+do {                                                                    \
+        current->thread.mflags &= ~MF_ABI_MASK;                         \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)                       \
+                __SET_PERSONALITY32(ex);                                \
+        else {                                                          \
+                current->thread.mflags |= MF_N64;                       \
+                current->thread.abi = &mips_abi;                        \
+        }                                                               \
+                                                                        \
+        if (ibcs2)                                                      \
+                set_personality(PER_SVR4);                              \
+        else if (current->personality != PER_LINUX32)                   \
+                set_personality(PER_LINUX);                             \
 } while (0)
 #endif /* CONFIG_64BIT */
 extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
+extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
 extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
 #define ELF_CORE_COPY_REGS(elf_regs, regs)                      \
        dump_regs((elf_greg_t *)&(elf_regs), regs);
+#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
 #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs)                   \
        dump_task_fpu(tsk, elf_fpregs)
 #endif /* __KERNEL__ */
-/* This one accepts IRIX binaries.  */
-#define irix_elf_check_arch(hdr)        ((hdr)->e_flags & RHF_SGI_ONLY)
 #define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h
index 3c0d840e4577..9d3e6e7cdb92 100644
--- a/include/asm-mips/errno.h
+++ b/include/asm-mips/errno.h
@@ -119,6 +119,10 @@
 #define EOWNERDEAD      165     /* Owner died */
 #define ENOTRECOVERABLE 166     /* State not recoverable */
+/* for robust mutexes */
+#define EOWNERDEAD      165     /* Owner died */
+#define ENOTRECOVERABLE 166     /* State not recoverable */
 #define EDQUOT          1133    /* Quota exceeded */
 #ifdef __KERNEL__
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
index 06c5d13faf66..43d047a9a6af 100644
--- a/include/asm-mips/fcntl.h
+++ b/include/asm-mips/fcntl.h
@@ -3,11 +3,13 @@
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
- * Copyright (C) 1995, 96, 97, 98, 99, 2003 Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
 */
 #ifndef _ASM_FCNTL_H
 #define _ASM_FCNTL_H
+#include <linux/config.h>
 #define O_APPEND        0x0008
 #define O_SYNC          0x0010
 #define O_NONBLOCK      0x0080
@@ -40,13 +42,13 @@
 * contain all the same fields as struct flock.
 */
-#ifndef __mips64
+#ifdef CONFIG_32BIT
 struct flock {
        short   l_type;
        short   l_whence;
-        __kernel_off_t l_start;
+        off_t   l_start;
-        __kernel_off_t l_len;
+        off_t   l_len;
        long    l_sysid;
        __kernel_pid_t l_pid;
        long    pad[4];
@@ -54,13 +56,8 @@ struct flock {
 #define HAVE_ARCH_STRUCT_FLOCK
-#endif
+#endif /* CONFIG_32BIT */
 #include <asm-generic/fcntl.h>
-typedef struct flock flock_t;
-#ifndef __mips64
-typedef struct flock64 flock64_t;
-#endif
 #endif /* _ASM_FCNTL_H */
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index 26b6a90a690b..73a3028dd9f9 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -107,4 +107,11 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr)
        return __virt_to_fix(vaddr);
 }
+/*
+ * Called from pgtable_init()
+ */
+extern void fixrange_init(unsigned long start, unsigned long end,
+        pgd_t *pgd_base);
 #endif
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index ea24e733b1bc..9c828b1f8218 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -80,9 +80,14 @@ do {									\
 #define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
+static inline int __is_fpu_owner(void)
+{
+        return test_thread_flag(TIF_USEDFPU);
+}
 static inline int is_fpu_owner(void)
 {
-        return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
+        return cpu_has_fpu && __is_fpu_owner();
 }
 static inline void own_fpu(void)
@@ -127,7 +132,7 @@ static inline void restore_fp(struct task_struct *tsk)
 static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
 {
        if (cpu_has_fpu) {
-                if ((tsk == current) && is_fpu_owner())
+                if ((tsk == current) && __is_fpu_owner())
                        _save_fp(current);
                return tsk->thread.fpu.hard.fpr;
        }
diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h
index 46972ae2b95d..16cb4d11dd0b 100644
--- a/include/asm-mips/fpu_emulator.h
+++ b/include/asm-mips/fpu_emulator.h
@@ -23,16 +23,15 @@
 #ifndef _ASM_FPU_EMULATOR_H
 #define _ASM_FPU_EMULATOR_H
-struct mips_fpu_emulator_private {
+struct mips_fpu_emulator_stats {
-        unsigned int eir;
+        unsigned int emulated;
-        struct {
+        unsigned int loads;
-                unsigned int emulated;
+        unsigned int stores;
-                unsigned int loads;
+        unsigned int cp1ops;
-                unsigned int stores;
+        unsigned int cp1xops;
-                unsigned int cp1ops;
+        unsigned int errors;
-                unsigned int cp1xops;
-                unsigned int errors;
-        } stats;
 };
+extern struct mips_fpu_emulator_stats fpuemustats;
 #endif /* _ASM_FPU_EMULATOR_H */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 9feff4ce1424..2454c44a8f54 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -3,10 +3,45 @@
 #ifdef __KERNEL__
+#include <linux/config.h>
 #include <linux/futex.h>
 #include <asm/errno.h>
 #include <asm/uaccess.h>
+#ifdef CONFIG_SMP
+#define __FUTEX_SMP_SYNC "      sync                                    \n"
+#else
+#define __FUTEX_SMP_SYNC
+#endif
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)              \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       .set    mips3                                   \n"     \
+        "1:     ll      %1, (%3)        # __futex_atomic_op1    \n"     \
+        "       .set    mips0                                   \n"     \
+        "       " insn  "                                       \n"     \
+        "       .set    mips3                                   \n"     \
+        "2:     sc      $1, (%3)                                \n"     \
+        "       beqzl   $1, 1b                                  \n"     \
+        __FUTEX_SMP_SYNC                                                \
+        "3:                                                     \n"     \
+        "       .set    pop                                     \n"     \
+        "       .set    mips0                                   \n"     \
+        "       .section .fixup,\"ax\"                          \n"     \
+        "4:     li      %0, %5                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section __ex_table,\"a\"                       \n"     \
+        "       "__UA_ADDR "\t1b, 4b                            \n"     \
+        "       "__UA_ADDR "\t2b, 4b                            \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (ret), "=r" (oldval)                                     \
+        : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT));           \
+}
 static inline int
 futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
 {
@@ -25,10 +60,25 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
        switch (op) {
        case FUTEX_OP_SET:
+                __futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg);
+                break;
        case FUTEX_OP_ADD:
+                __futex_atomic_op("addu $1, %1, %z4",
+                                  ret, oldval, uaddr, oparg);
+                break;
        case FUTEX_OP_OR:
+                __futex_atomic_op("or   $1, %1, %z4",
+                                  ret, oldval, uaddr, oparg);
+                break;
        case FUTEX_OP_ANDN:
+                __futex_atomic_op("and  $1, %1, %z4",
+                                  ret, oldval, uaddr, ~oparg);
+                break;
        case FUTEX_OP_XOR:
+                __futex_atomic_op("xor  $1, %1, %z4",
+                                  ret, oldval, uaddr, oparg);
+                break;
        default:
                ret = -ENOSYS;
        }
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index f524eaccd5f1..7517189e469f 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -74,7 +74,8 @@
 #define irq_disable_hazard
        _ehb
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
+      defined(CONFIG_CPU_SB1)
 /*
 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -107,6 +108,7 @@ __asm__(
        "       .endm                                           \n\t");
 #ifdef CONFIG_CPU_RM9000
 /*
 * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
@@ -124,6 +126,9 @@ __asm__(
                ".set\tmips32\n\t"                                      \
                "_ssnop; _ssnop; _ssnop; _ssnop\n\t"                    \
                ".set\tmips0")
+#define back_to_back_c0_hazard()        do { } while (0)
 #else
 /*
@@ -144,15 +149,13 @@ __asm__(
 #endif
 /*
- * mtc0->mfc0 hazard
+ * Interrupt enable/disable hazards
- * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
+ * Some processors have hazards when modifying
- * It is a MIPS32R2 processor so ehb will clear the hazard.
+ * the status register to change the interrupt state
 */
 #ifdef CONFIG_CPU_MIPSR2
-/*
- * Use a macro for ehb unless explicit support for MIPSR2 is enabled
- */
 __asm__(
        "       .macro\tirq_enable_hazard                       \n\t"
        "       _ehb                                            \n\t"
@@ -160,17 +163,26 @@ __asm__(
        "                                                       \n\t"
        "       .macro\tirq_disable_hazard                      \n\t"
        "       _ehb                                            \n\t"
+        "       .endm                                           \n\t"
+        "                                                       \n\t"
+        "       .macro\tback_to_back_c0_hazard                  \n\t"
+        "       _ehb                                            \n\t"
        "       .endm");
 #define irq_enable_hazard()                                             \
        __asm__ __volatile__(                                           \
-        "_ehb\t\t\t\t# irq_enable_hazard")
+        "irq_enable_hazard")
 #define irq_disable_hazard()                                            \
        __asm__ __volatile__(                                           \
-        "_ehb\t\t\t\t# irq_disable_hazard")
+        "irq_disable_hazard")
+#define back_to_back_c0_hazard()                                        \
+        __asm__ __volatile__(                                           \
+        "back_to_back_c0_hazard")
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
+      defined(CONFIG_CPU_SB1)
 /*
 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -186,6 +198,8 @@ __asm__(
 #define irq_enable_hazard()     do { } while (0)
 #define irq_disable_hazard()    do { } while (0)
+#define back_to_back_c0_hazard()        do { } while (0)
 #else
 /*
@@ -208,10 +222,32 @@ __asm__(
 #define irq_enable_hazard()     do { } while (0)
 #define irq_disable_hazard()                                            \
        __asm__ __volatile__(                                           \
-        "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
+        "irq_disable_hazard")
+#define back_to_back_c0_hazard()                                        \
+        __asm__ __volatile__(                                           \
+        "       .set noreorder                          \n"             \
+        "       nop; nop; nop                           \n"             \
+        "       .set reorder                            \n")
 #endif
+#ifdef CONFIG_CPU_MIPSR2
+#define instruction_hazard()                                            \
+do {                                                                    \
+__label__ __next;                                                       \
+        __asm__ __volatile__(                                           \
+        "       jr.hb   %0                                      \n"     \
+        :                                                               \
+        : "r" (&&__next));                                              \
+__next:                                                                 \
+        ;                                                               \
+} while (0)
+#else
+#define instruction_hazard() do { } while (0)
+#endif
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_HAZARDS_H */
diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h
index f49930d947d4..8cf598402492 100644
--- a/include/asm-mips/highmem.h
+++ b/include/asm-mips/highmem.h
@@ -75,6 +75,7 @@ static inline void *kmap_atomic(struct page *page, enum km_type type)
 }
 static inline void kunmap_atomic(void *kvaddr, enum km_type type) { }
+#define kmap_atomic_pfn(pfn, idx)       page_address(pfn_to_page(pfn))
 #define kmap_atomic_to_page(ptr) virt_to_page(ptr)
@@ -86,6 +87,7 @@ extern void *__kmap(struct page *page);
 extern void __kunmap(struct page *page);
 extern void *__kmap_atomic(struct page *page, enum km_type type);
 extern void __kunmap_atomic(void *kvaddr, enum km_type type);
+extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
 extern struct page *__kmap_atomic_to_page(void *ptr);
 #define kmap                    __kmap
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h
index 6ad517241768..e0745f4ff624 100644
--- a/include/asm-mips/inst.h
+++ b/include/asm-mips/inst.h
@@ -28,7 +28,7 @@ enum major_op {
        sdl_op, sdr_op, swr_op, cache_op,
        ll_op, lwc1_op, lwc2_op, pref_op,
        lld_op, ldc1_op, ldc2_op, ld_op,
-        sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */
+        sc_op, swc1_op, swc2_op, rdhwr_op,
        scd_op, sdc1_op, sdc2_op, sd_op
 };
@@ -62,10 +62,10 @@ enum rt_op {
        spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
        tgei_op, tgeiu_op, tlti_op, tltiu_op,
        teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
-        bltzal_op, bgezal_op, bltzall_op, bgezall_op
+        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
-        /*
+        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
-         * The others (0x14 - 0x1f) are unused.
+        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
-         */
+        bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
 };
 /*
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h
index e8357f5379fa..a5735761f5e5 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/interrupt.h
@@ -11,20 +11,25 @@
 #ifndef _ASM_INTERRUPT_H
 #define _ASM_INTERRUPT_H
+#include <linux/config.h>
 #include <asm/hazards.h>
 __asm__ (
-        ".macro\tlocal_irq_enable\n\t"
+        "       .macro  local_irq_enable                                \n"
-        ".set\tpush\n\t"
+        "       .set    push                                            \n"
-        ".set\treorder\n\t"
+        "       .set    reorder                                         \n"
-        ".set\tnoat\n\t"
+        "       .set    noat                                            \n"
-        "mfc0\t$1,$12\n\t"
+#ifdef CONFIG_CPU_MIPSR2
-        "ori\t$1,0x1f\n\t"
+        "       ei                                                      \n"
-        "xori\t$1,0x1e\n\t"
+#else
-        "mtc0\t$1,$12\n\t"
+        "       mfc0    $1,$12                                          \n"
-        "irq_enable_hazard\n\t"
+        "       ori     $1,0x1f                                         \n"
-        ".set\tpop\n\t"
+        "       xori    $1,0x1e                                         \n"
-        ".endm");
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_enable_hazard                                       \n"
+        "       .set    pop                                             \n"
+        "       .endm");
 static inline void local_irq_enable(void)
 {
@@ -43,17 +48,21 @@ static inline void local_irq_enable(void)
 * no nops at all.
 */
 __asm__ (
-        ".macro\tlocal_irq_disable\n\t"
+        "       .macro  local_irq_disable\n"
-        ".set\tpush\n\t"
+        "       .set    push                                            \n"
-        ".set\tnoat\n\t"
+        "       .set    noat                                            \n"
-        "mfc0\t$1,$12\n\t"
+#ifdef CONFIG_CPU_MIPSR2
-        "ori\t$1,1\n\t"
+        "       di                                                      \n"
-        "xori\t$1,1\n\t"
+#else
-        ".set\tnoreorder\n\t"
+        "       mfc0    $1,$12                                          \n"
-        "mtc0\t$1,$12\n\t"
+        "       ori     $1,1                                            \n"
-        "irq_disable_hazard\n\t"
+        "       xori    $1,1                                            \n"
-        ".set\tpop\n\t"
+        "       .set    noreorder                                       \n"
-        ".endm");
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
 static inline void local_irq_disable(void)
 {
@@ -65,12 +74,12 @@ static inline void local_irq_disable(void)
 }
 __asm__ (
-        ".macro\tlocal_save_flags flags\n\t"
+        "       .macro  local_save_flags flags                          \n"
-        ".set\tpush\n\t"
+        "       .set    push                                            \n"
-        ".set\treorder\n\t"
+        "       .set    reorder                                         \n"
-        "mfc0\t\\flags, $12\n\t"
+        "       mfc0    \\flags, $12                                    \n"
-        ".set\tpop\n\t"
+        "       .set    pop                                             \n"
-        ".endm");
+        "       .endm                                                   \n");
 #define local_save_flags(x)                                             \
 __asm__ __volatile__(                                                   \
@@ -78,18 +87,22 @@ __asm__ __volatile__(							\
        : "=r" (x))
 __asm__ (
-        ".macro\tlocal_irq_save result\n\t"
+        "       .macro  local_irq_save result                           \n"
-        ".set\tpush\n\t"
+        "       .set    push                                            \n"
-        ".set\treorder\n\t"
+        "       .set    reorder                                         \n"
-        ".set\tnoat\n\t"
+        "       .set    noat                                            \n"
-        "mfc0\t\\result, $12\n\t"
+#ifdef CONFIG_CPU_MIPSR2
-        "ori\t$1, \\result, 1\n\t"
+        "       di      \\result                                        \n"
-        "xori\t$1, 1\n\t"
+#else
-        ".set\tnoreorder\n\t"
+        "       mfc0    \\result, $12                                   \n"
-        "mtc0\t$1, $12\n\t"
+        "       ori     $1, \\result, 1                                 \n"
-        "irq_disable_hazard\n\t"
+        "       xori    $1, 1                                           \n"
-        ".set\tpop\n\t"
+        "       .set    noreorder                                       \n"
-        ".endm");
+        "       mtc0    $1, $12                                         \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
 #define local_irq_save(x)                                               \
 __asm__ __volatile__(                                                   \
@@ -99,19 +112,37 @@ __asm__ __volatile__(							\
        : "memory")
 __asm__ (
-        ".macro\tlocal_irq_restore flags\n\t"
+        "       .macro  local_irq_restore flags                         \n"
-        ".set\tnoreorder\n\t"
+        "       .set    noreorder                                       \n"
-        ".set\tnoat\n\t"
+        "       .set    noat                                            \n"
-        "mfc0\t$1, $12\n\t"
+#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
-        "andi\t\\flags, 1\n\t"
+        /*
-        "ori\t$1, 1\n\t"
+         * Slow, but doesn't suffer from a relativly unlikely race
-        "xori\t$1, 1\n\t"
+         * condition we're having since days 1.
-        "or\t\\flags, $1\n\t"
+         */
-        "mtc0\t\\flags, $12\n\t"
+        "       beqz    \\flags, 1f                                     \n"
-        "irq_disable_hazard\n\t"
+        "        di                                                     \n"
-        ".set\tat\n\t"
+        "       ei                                                      \n"
-        ".set\treorder\n\t"
+        "1:                                                             \n"
-        ".endm");
+#elif defined(CONFIG_CPU_MIPSR2)
+        /*
+         * Fast, dangerous.  Life is fun, life is good.
+         */
+        "       mfc0    $1, $12                                         \n"
+        "       ins     $1, \\flags, 0, 1                               \n"
+        "       mtc0    $1, $12                                         \n"
+#else
+        "       mfc0    $1, $12                                         \n"
+        "       andi    \\flags, 1                                      \n"
+        "       ori     $1, 1                                           \n"
+        "       xori    $1, 1                                           \n"
+        "       or      \\flags, $1                                     \n"
+        "       mtc0    \\flags, $12                                    \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    at                                              \n"
+        "       .set    reorder                                         \n"
+        "       .endm                                                   \n");
 #define local_irq_restore(flags)                                        \
 do {                                                                    \
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
index 4cd36fe98173..92d90f75a636 100644
--- a/include/asm-mips/inventory.h
+++ b/include/asm-mips/inventory.h
@@ -4,6 +4,8 @@
 #ifndef __ASM_INVENTORY_H
 #define __ASM_INVENTORY_H
+#include <linux/compiler.h>
 typedef struct inventory_s {
        struct inventory_s *inv_next;
        int    inv_class;
@@ -14,7 +16,9 @@ typedef struct inventory_s {
 } inventory_t;
 extern int inventory_items;
-void add_to_inventory (int class, int type, int controller, int unit, int state);
-int dump_inventory_to_user (void *userbuf, int size);
+extern void add_to_inventory (int class, int type, int controller, int unit, int state);
+extern int dump_inventory_to_user (void __user *userbuf, int size);
+extern int __init init_inventory(void);
 #endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 039845f2e6b0..3061870b7f6c 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -25,7 +25,9 @@
 #include <asm/page.h>
 #include <asm/pgtable-bits.h>
 #include <asm/processor.h>
+#include <asm/string.h>
+#include <ioremap.h>
 #include <mangle-port.h>
 /*
@@ -34,7 +36,7 @@
 #undef CONF_SLOWDOWN_IO
 /*
- * Raw operations are never swapped in software.  Otoh values that raw
+ * Raw operations are never swapped in software.  OTOH values that raw
 * operations are working on may or may not have been swapped by the bus
 * hardware.  An example use would be for flash memory that's used for
 * execute in place.
@@ -43,45 +45,53 @@
 # define __raw_ioswabw(x)       (x)
 # define __raw_ioswabl(x)       (x)
 # define __raw_ioswabq(x)       (x)
+# define ____raw_ioswabq(x)     (x)
 /*
 * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
 * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "mem_" prefix.
 */
 #if defined(CONFIG_SWAP_IO_SPACE)
 # define ioswabb(x)             (x)
+# define mem_ioswabb(x)         (x)
 # ifdef CONFIG_SGI_IP22
 /*
 * IP22 seems braindead enough to swap 16bits values in hardware, but
 * not 32bits.  Go figure... Can't tell without documentation.
 */
 #  define ioswabw(x)            (x)
+#  define mem_ioswabw(x)        le16_to_cpu(x)
 # else
 #  define ioswabw(x)            le16_to_cpu(x)
+#  define mem_ioswabw(x)        (x)
 # endif
 # define ioswabl(x)             le32_to_cpu(x)
+# define mem_ioswabl(x)         (x)
 # define ioswabq(x)             le64_to_cpu(x)
+# define mem_ioswabq(x)         (x)
 #else
 # define ioswabb(x)             (x)
+# define mem_ioswabb(x)         (x)
 # define ioswabw(x)             (x)
+# define mem_ioswabw(x)         cpu_to_le16(x)
 # define ioswabl(x)             (x)
+# define mem_ioswabl(x)         cpu_to_le32(x)
 # define ioswabq(x)             (x)
+# define mem_ioswabq(x)         cpu_to_le32(x)
 #endif
-/*
- * Native bus accesses never swapped.
- */
-#define bus_ioswabb(x)          (x)
-#define bus_ioswabw(x)          (x)
-#define bus_ioswabl(x)          (x)
-#define bus_ioswabq(x)          (x)
-#define __bus_ioswabq           bus_ioswabq
 #define IO_SPACE_LIMIT 0xffff
 /*
@@ -194,12 +204,14 @@ extern unsigned long isa_slot_offset;
 */
 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
-extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
+extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
 extern void __iounmap(volatile void __iomem *addr);
-static inline void * __ioremap_mode(phys_t offset, unsigned long size,
+static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
        unsigned long flags)
 {
+#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
        if (cpu_has_64bit_addresses) {
                u64 base = UNCAC_BASE;
@@ -209,10 +221,30 @@ static inline void * __ioremap_mode(phys_t offset, unsigned long size,
                 */
                if (flags == _CACHE_UNCACHED)
                        base = (u64) IO_BASE;
-                return (void *) (unsigned long) (base + offset);
+                return (void __iomem *) (unsigned long) (base + offset);
+        } else if (__builtin_constant_p(offset) &&
+                   __builtin_constant_p(size) && __builtin_constant_p(flags)) {
+                phys_t phys_addr, last_addr;
+                phys_addr = fixup_bigphys_addr(offset, size);
+                /* Don't allow wraparound or zero size. */
+                last_addr = phys_addr + size - 1;
+                if (!size || last_addr < phys_addr)
+                        return NULL;
+                /*
+                 * Map uncached objects in the low 512MB of address
+                 * space using KSEG1.
+                 */
+                if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
+                    flags == _CACHE_UNCACHED)
+                        return (void __iomem *)CKSEG1ADDR(phys_addr);
        }
        return __ioremap(offset, size, flags);
+#undef __IS_LOW512
 }
 /*
@@ -264,12 +296,16 @@ static inline void * __ioremap_mode(phys_t offset, unsigned long size,
 static inline void iounmap(volatile void __iomem *addr)
 {
-        if (cpu_has_64bit_addresses)
+#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
+        if (cpu_has_64bit_addresses ||
+            (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
                return;
        __iounmap(addr);
-}
+#undef __IS_KSEG1
+}
 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
                                                                        \
@@ -319,7 +355,8 @@ static inline type pfx##read##bwlq(volatile void __iomem *mem)		\
        else if (cpu_has_64bits) {                                      \
                unsigned long __flags;                                  \
                                                                        \
-                local_irq_save(__flags);                                \
+                if (irq)                                                \
+                        local_irq_save(__flags);                        \
                __asm__ __volatile__(                                   \
                        ".set   mips3"          "\t\t# __readq" "\n\t"  \
                        "ld     %L0, %1"                        "\n\t"  \
@@ -328,7 +365,8 @@ static inline type pfx##read##bwlq(volatile void __iomem *mem)		\
                        ".set   mips0"                          "\n"    \
                        : "=r" (__val)                                  \
                        : "m" (*__mem));                                \
-                local_irq_restore(__flags);                             \
+                if (irq)                                                \
+                        local_irq_restore(__flags);                     \
        } else {                                                        \
                __val = 0;                                              \
                BUG();                                                  \
@@ -349,11 +387,11 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
                                                                        \
        __val = pfx##ioswab##bwlq(val);                                 \
                                                                        \
-        if (sizeof(type) != sizeof(u64)) {                              \
+        /* Really, we want this to be atomic */                         \
-                *__addr = __val;                                        \
+        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
-                slow;                                                   \
+                                                                        \
-        } else                                                          \
+        *__addr = __val;                                                \
-                BUILD_BUG();                                            \
+        slow;                                                           \
 }                                                                       \
                                                                        \
 static inline type pfx##in##bwlq##p(unsigned long port)                 \
@@ -364,13 +402,10 @@ static inline type pfx##in##bwlq##p(unsigned long port)			\
        port = __swizzle_addr_##bwlq(port);                             \
        __addr = (void *)(mips_io_port_base + port);                    \
                                                                        \
-        if (sizeof(type) != sizeof(u64)) {                              \
+        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
-                __val = *__addr;                                        \
+                                                                        \
-                slow;                                                   \
+        __val = *__addr;                                                \
-        } else {                                                        \
+        slow;                                                           \
-                __val = 0;                                              \
-                BUILD_BUG();                                            \
-        }                                                               \
                                                                        \
        return pfx##ioswab##bwlq(__val);                                \
 }
@@ -379,27 +414,35 @@ static inline type pfx##in##bwlq##p(unsigned long port)			\
                                                                        \
 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
-#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
+#define BUILDIO_MEM(bwlq, type)                                         \
-                                                                        \
-__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                               \
-__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
-#define BUILDIO(bwlq, type)                                             \
                                                                        \
-__BUILD_MEMORY_PFX(, bwlq, type)                                        \
 __BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
-__BUILD_MEMORY_PFX(bus_, bwlq, type)                                    \
+__BUILD_MEMORY_PFX(, bwlq, type)                                        \
-__BUILD_IOPORT_PFX(, bwlq, type)                                        \
+__BUILD_MEMORY_PFX(mem_, bwlq, type)                                    \
-__BUILD_IOPORT_PFX(__raw_, bwlq, type)
+BUILDIO_MEM(b, u8)
+BUILDIO_MEM(w, u16)
+BUILDIO_MEM(l, u32)
+BUILDIO_MEM(q, u64)
+#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+#define BUILDIO_IOPORT(bwlq, type)                                      \
+        __BUILD_IOPORT_PFX(, bwlq, type)                                \
+        __BUILD_IOPORT_PFX(mem_, bwlq, type)
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_IOPORT(q, u64)
+#endif
 #define __BUILDIO(bwlq, type)                                           \
                                                                        \
-__BUILD_MEMORY_SINGLE(__bus_, bwlq, type, 0)
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
-BUILDIO(b, u8)
-BUILDIO(w, u16)
-BUILDIO(l, u32)
-BUILDIO(q, u64)
 __BUILDIO(q, u64)
@@ -422,7 +465,7 @@ static inline void writes##bwlq(volatile void __iomem *mem, void *addr,	\
        volatile type *__addr = addr;                                   \
                                                                        \
        while (count--) {                                               \
-                __raw_write##bwlq(*__addr, mem);                        \
+                mem_write##bwlq(*__addr, mem);                          \
                __addr++;                                               \
        }                                                               \
 }                                                                       \
@@ -433,20 +476,20 @@ static inline void reads##bwlq(volatile void __iomem *mem, void *addr,	\
        volatile type *__addr = addr;                                   \
                                                                        \
        while (count--) {                                               \
-                *__addr = __raw_read##bwlq(mem);                        \
+                *__addr = mem_read##bwlq(mem);                          \
                __addr++;                                               \
        }                                                               \
 }
 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
                                                                        \
-static inline void outs##bwlq(unsigned long port, void *addr,           \
+static inline void outs##bwlq(unsigned long port, const void *addr,     \
                              unsigned int count)                       \
 {                                                                       \
-        volatile type *__addr = addr;                                   \
+        const volatile type *__addr = addr;                             \
                                                                        \
        while (count--) {                                               \
-                __raw_out##bwlq(*__addr, port);                         \
+                mem_out##bwlq(*__addr, port);                           \
                __addr++;                                               \
        }                                                               \
 }                                                                       \
@@ -457,7 +500,7 @@ static inline void ins##bwlq(unsigned long port, void *addr,		\
        volatile type *__addr = addr;                                   \
                                                                        \
        while (count--) {                                               \
-                *__addr = __raw_in##bwlq(port);                         \
+                *__addr = mem_in##bwlq(port);                           \
                __addr++;                                               \
        }                                                               \
 }
@@ -470,15 +513,26 @@ __BUILD_IOPORT_STRING(bwlq, type)
 BUILDSTRING(b, u8)
 BUILDSTRING(w, u16)
 BUILDSTRING(l, u32)
+#ifdef CONFIG_64BIT
 BUILDSTRING(q, u64)
+#endif
 /* Depends on MIPS II instruction set */
 #define mmiowb() asm volatile ("sync" ::: "memory")
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
+{
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+        memset((void __force *) addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+        memcpy(dst, (void __force *) src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+        memcpy((void __force *) dst, src, count);
+}
 /*
 * Memory Mapped I/O
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 3f2470e9e678..8a342ccb34a8 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -24,11 +24,9 @@ static inline int irq_canonicalize(int irq)
 struct pt_regs;
-#ifdef CONFIG_PREEMPT
 extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
-#else
+#ifdef CONFIG_PREEMPT
 /*
 * do_IRQ handles all normal device IRQ's (the special
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 86df317b4078..baf412967afa 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -202,20 +202,6 @@ static inline int jmr3927_have_isac(void)
 #endif /* !__ASSEMBLY__ */
 /*
- * UART defines for serial.h
- */
-/* use Pre-scaler T0 (1/2) */
-#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)
-#define UART0_ADDR   0xfffef300
-#define UART1_ADDR   0xfffef400
-#define UART0_INT    JMR3927_IRQ_IRC_SIO0
-#define UART1_INT    JMR3927_IRQ_IRC_SIO1
-#define UART0_FLAGS  ASYNC_BOOT_AUTOCONF
-#define UART1_FLAGS  0
-/*
 * IRQ mappings
 */
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 148bae2fa7d3..8327ec341c18 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -60,59 +60,36 @@ void static inline au_sync_delay(int ms)
        mdelay(ms);
 }
-void static inline au_writeb(u8 val, int reg)
+void static inline au_writeb(u8 val, unsigned long reg)
 {
        *(volatile u8 *)(reg) = val;
 }
-void static inline au_writew(u16 val, int reg)
+void static inline au_writew(u16 val, unsigned long reg)
 {
        *(volatile u16 *)(reg) = val;
 }
-void static inline au_writel(u32 val, int reg)
+void static inline au_writel(u32 val, unsigned long reg)
 {
        *(volatile u32 *)(reg) = val;
 }
-static inline u8 au_readb(unsigned long port)
+static inline u8 au_readb(unsigned long reg)
 {
-        return (*(volatile u8 *)port);
+        return (*(volatile u8 *)reg);
 }
-static inline u16 au_readw(unsigned long port)
+static inline u16 au_readw(unsigned long reg)
 {
-        return (*(volatile u16 *)port);
+        return (*(volatile u16 *)reg);
 }
-static inline u32 au_readl(unsigned long port)
+static inline u32 au_readl(unsigned long reg)
 {
-        return (*(volatile u32 *)port);
+        return (*(volatile u32 *)reg);
 }
-/* These next three functions should be a generic part of the MIPS
- * kernel (with the 'au_' removed from the name) and selected for
- * processors that support the instructions.
- * Taken from PPC tree.  -- Dan
- */
-/* Return the bit position of the most significant 1 bit in a word */
-static __inline__ int __ilog2(unsigned int x)
-{
-        int lz;
-        asm volatile (
-                ".set\tnoreorder\n\t"
-                ".set\tnoat\n\t"
-                ".set\tmips32\n\t"
-                "clz\t%0,%1\n\t"
-                ".set\tmips0\n\t"
-                ".set\tat\n\t"
-                ".set\treorder"
-                : "=r" (lz)
-                : "r" (x));
-        return 31 - lz;
-}
 static __inline__ int au_ffz(unsigned int x)
 {
@@ -162,28 +139,293 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 #endif
-/* SDRAM Controller */
+/*
+ * SDRAM Register Offsets
+ */
 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0                0xB4000000
+#define MEM_SDMODE0             (0x0000)
-#define MEM_SDMODE1                0xB4000004
+#define MEM_SDMODE1             (0x0004)
-#define MEM_SDMODE2                0xB4000008
+#define MEM_SDMODE2             (0x0008)
+#define MEM_SDADDR0             (0x000C)
+#define MEM_SDADDR1             (0x0010)
+#define MEM_SDADDR2             (0x0014)
+#define MEM_SDREFCFG    (0x0018)
+#define MEM_SDPRECMD    (0x001C)
+#define MEM_SDAUTOREF   (0x0020)
+#define MEM_SDWRMD0             (0x0024)
+#define MEM_SDWRMD1             (0x0028)
+#define MEM_SDWRMD2             (0x002C)
+#define MEM_SDSLEEP             (0x0030)
+#define MEM_SDSMCKE             (0x0034)
-#define MEM_SDADDR0                0xB400000C
+/*
-#define MEM_SDADDR1                0xB4000010
+ * MEM_SDMODE register content definitions
-#define MEM_SDADDR2                0xB4000014
+ */
+#define MEM_SDMODE_F            (1<<22)
+#define MEM_SDMODE_SR           (1<<21)
+#define MEM_SDMODE_BS           (1<<20)
+#define MEM_SDMODE_RS           (3<<18)
+#define MEM_SDMODE_CS           (7<<15)
+#define MEM_SDMODE_TRAS         (15<<11)
+#define MEM_SDMODE_TMRD         (3<<9)
+#define MEM_SDMODE_TWR          (3<<7)
+#define MEM_SDMODE_TRP          (3<<5)
+#define MEM_SDMODE_TRCD         (3<<3)
+#define MEM_SDMODE_TCL          (7<<0)
+#define MEM_SDMODE_BS_2Bank     (0<<20)
+#define MEM_SDMODE_BS_4Bank     (1<<20)
+#define MEM_SDMODE_RS_11Row     (0<<18)
+#define MEM_SDMODE_RS_12Row     (1<<18)
+#define MEM_SDMODE_RS_13Row     (2<<18)
+#define MEM_SDMODE_RS_N(N)      ((N)<<18)
+#define MEM_SDMODE_CS_7Col      (0<<15)
+#define MEM_SDMODE_CS_8Col      (1<<15)
+#define MEM_SDMODE_CS_9Col      (2<<15)
+#define MEM_SDMODE_CS_10Col     (3<<15)
+#define MEM_SDMODE_CS_11Col     (4<<15)
+#define MEM_SDMODE_CS_N(N)              ((N)<<15)
+#define MEM_SDMODE_TRAS_N(N)    ((N)<<11)
+#define MEM_SDMODE_TMRD_N(N)    ((N)<<9)
+#define MEM_SDMODE_TWR_N(N)             ((N)<<7)
+#define MEM_SDMODE_TRP_N(N)             ((N)<<5)
+#define MEM_SDMODE_TRCD_N(N)    ((N)<<3)
+#define MEM_SDMODE_TCL_N(N)             ((N)<<0)
-#define MEM_SDREFCFG               0xB4000018
+/*
-#define MEM_SDPRECMD               0xB400001C
+ * MEM_SDADDR register contents definitions
-#define MEM_SDAUTOREF              0xB4000020
+ */
+#define MEM_SDADDR_E                    (1<<20)
+#define MEM_SDADDR_CSBA                 (0x03FF<<10)
+#define MEM_SDADDR_CSMASK               (0x03FF<<0)
+#define MEM_SDADDR_CSBA_N(N)    ((N)&(0x03FF<<22)>>12)
+#define MEM_SDADDR_CSMASK_N(N)  ((N)&(0x03FF<<22)>>22)
+/*
+ * MEM_SDREFCFG register content definitions
+ */
+#define MEM_SDREFCFG_TRC                (15<<28)
+#define MEM_SDREFCFG_TRPM               (3<<26)
+#define MEM_SDREFCFG_E                  (1<<25)
+#define MEM_SDREFCFG_RE                 (0x1ffffff<<0)
+#define MEM_SDREFCFG_TRC_N(N)   ((N)<<MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N)  ((N)<<MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_REF_N(N)   (N)
+#endif
-#define MEM_SDWRMD0                0xB4000024
+/***********************************************************************/
-#define MEM_SDWRMD1                0xB4000028
-#define MEM_SDWRMD2                0xB400002C
-#define MEM_SDSLEEP                0xB4000030
+/*
-#define MEM_SDSMCKE                0xB4000034
+ * Au1550 SDRAM Register Offsets
+ */
+/***********************************************************************/
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_SDMODE0             (0x0800)
+#define MEM_SDMODE1             (0x0808)
+#define MEM_SDMODE2             (0x0810)
+#define MEM_SDADDR0             (0x0820)
+#define MEM_SDADDR1             (0x0828)
+#define MEM_SDADDR2             (0x0830)
+#define MEM_SDCONFIGA   (0x0840)
+#define MEM_SDCONFIGB   (0x0848)
+#define MEM_SDSTAT              (0x0850)
+#define MEM_SDERRADDR   (0x0858)
+#define MEM_SDSTRIDE0   (0x0860)
+#define MEM_SDSTRIDE1   (0x0868)
+#define MEM_SDSTRIDE2   (0x0870)
+#define MEM_SDWRMD0             (0x0880)
+#define MEM_SDWRMD1             (0x0888)
+#define MEM_SDWRMD2             (0x0890)
+#define MEM_SDPRECMD    (0x08C0)
+#define MEM_SDAUTOREF   (0x08C8)
+#define MEM_SDSREF              (0x08D0)
+#define MEM_SDSLEEP             MEM_SDSREF
+#endif
+/*
+ * Physical base addresses for integrated peripherals
+ */
+#ifdef CONFIG_SOC_AU1000
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define IRDA_PHYS_ADDR          0x10300000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MAC1_PHYS_ADDR          0x10510000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART2_PHYS_ADDR         0x11300000
+#define UART3_PHYS_ADDR         0x11400000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define SYS_PHYS_ADDR           0x11900000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
 #endif
+/********************************************************************/
+#ifdef CONFIG_SOC_AU1500
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR           0x14005000
+#define MAC0_PHYS_ADDR          0x11500000
+#define MAC1_PHYS_ADDR          0x11510000
+#define MACEN_PHYS_ADDR         0x11520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define PCI_MEM_PHYS_ADDR     0x400000000ULL
+#define PCI_IO_PHYS_ADDR      0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
+#endif
+/********************************************************************/
+#ifdef CONFIG_SOC_AU1100
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define SD0_PHYS_ADDR           0x10600000
+#define SD1_PHYS_ADDR           0x10680000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define IRDA_PHYS_ADDR          0x10300000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART3_PHYS_ADDR         0x11400000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define LCD_PHYS_ADDR           0x15000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
+#endif
+/***********************************************************************/
+#ifdef CONFIG_SOC_AU1550
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define USBH_PHYS_ADDR          0x14020000
+#define USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR           0x14005000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MAC1_PHYS_ADDR          0x10510000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define DDMA_PHYS_ADDR          0x14002000
+#define PE_PHYS_ADDR            0x14008000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define PSC2_PHYS_ADDR          0x10A00000
+#define PSC3_PHYS_ADDR          0x10B00000
+#define PCI_MEM_PHYS_ADDR     0x400000000ULL
+#define PCI_IO_PHYS_ADDR      0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
+#endif
+/***********************************************************************/
+#ifdef CONFIG_SOC_AU1200
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define AES_PHYS_ADDR           0x10300000
+#define CIM_PHYS_ADDR           0x14004000
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define USBM_PHYS_ADDR          0x14020000
+#define USBH_PHYS_ADDR          0x14020100
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define DDMA_PHYS_ADDR          0x14002000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define SD0_PHYS_ADDR           0x10600000
+#define SD1_PHYS_ADDR           0x10680000
+#define LCD_PHYS_ADDR           0x15000000
+#define SWCNT_PHYS_ADDR         0x1110010C
+#define MAEFE_PHYS_ADDR         0x14012000
+#define MAEBE_PHYS_ADDR         0x14010000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
+#endif
 /* Static Bus Controller */
 #define MEM_STCFG0                 0xB4001000
 #define MEM_STTIME0                0xB4001004
@@ -369,7 +611,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_MAC0_ENABLE       0xB0520000
 #define AU1000_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1000
+#endif /* CONFIG_SOC_AU1000 */
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
@@ -429,6 +671,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_GPIO_207           62
 #define AU1500_GPIO_208_215       63
+/* shortcuts */
+#define INTA AU1000_PCI_INTA
+#define INTB AU1000_PCI_INTB
+#define INTC AU1000_PCI_INTC
+#define INTD AU1000_PCI_INTD
 #define UART0_ADDR                0xB1100000
 #define UART3_ADDR                0xB1400000
@@ -440,7 +688,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_MAC0_ENABLE       0xB1520000
 #define AU1500_MAC1_ENABLE       0xB1520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1500
+#endif /* CONFIG_SOC_AU1500 */
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
@@ -485,6 +733,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_GPIO_13            45
 #define AU1000_GPIO_14            46
 #define AU1000_GPIO_15            47
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
@@ -496,7 +760,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1100_ETH0_BASE          0xB0500000
 #define AU1100_MAC0_ENABLE       0xB0520000
 #define NUM_ETH_INTERFACES 1
-#endif // CONFIG_SOC_AU1100
+#endif /* CONFIG_SOC_AU1100 */
 #ifdef CONFIG_SOC_AU1550
 #define AU1550_UART0_INT          0
@@ -513,14 +777,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1550_PSC1_INT           11
 #define AU1550_PSC2_INT           12
 #define AU1550_PSC3_INT           13
-#define AU1550_TOY_INT                    14
+#define AU1000_TOY_INT                    14
-#define AU1550_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH0_INT     15
-#define AU1550_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH1_INT     16
-#define AU1550_TOY_MATCH2_INT     17
+#define AU1000_TOY_MATCH2_INT     17
-#define AU1550_RTC_INT            18
+#define AU1000_RTC_INT            18
-#define AU1550_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH0_INT     19
-#define AU1550_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH1_INT     20
-#define AU1550_RTC_MATCH2_INT     21
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1550_NAND_INT           23
 #define AU1550_USB_DEV_REQ_INT    24
 #define AU1550_USB_DEV_SUS_INT    25
@@ -563,6 +827,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_GPIO_207           62
 #define AU1500_GPIO_208_218       63    // Logical or of GPIO208:218
+/* shortcuts */
+#define INTA AU1550_PCI_INTA
+#define INTB AU1550_PCI_INTB
+#define INTC AU1550_PCI_INTC
+#define INTD AU1550_PCI_INTD
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
 #define UART3_ADDR                0xB1400000
@@ -575,7 +845,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1550_MAC0_ENABLE       0xB0520000
 #define AU1550_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1550
+#endif /* CONFIG_SOC_AU1550 */
 #ifdef CONFIG_SOC_AU1200
 #define AU1200_UART0_INT          0
@@ -592,14 +862,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1200_PSC1_INT           11
 #define AU1200_AES_INT            12
 #define AU1200_CAMERA_INT         13
-#define AU1200_TOY_INT                    14
+#define AU1000_TOY_INT                    14
-#define AU1200_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH0_INT     15
-#define AU1200_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH1_INT     16
-#define AU1200_TOY_MATCH2_INT     17
+#define AU1000_TOY_MATCH2_INT     17
-#define AU1200_RTC_INT            18
+#define AU1000_RTC_INT            18
-#define AU1200_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH0_INT     19
-#define AU1200_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH1_INT     20
-#define AU1200_RTC_MATCH2_INT     21
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1200_NAND_INT           23
 #define AU1200_GPIO_204           24
 #define AU1200_GPIO_205           25
@@ -607,6 +877,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1200_GPIO_207           27
 #define AU1200_GPIO_208_215       28 // Logical OR of 208:215
 #define AU1200_USB_INT            29
+#define AU1000_USB_HOST_INT               AU1200_USB_INT
 #define AU1200_LCD_INT            30
 #define AU1200_MAE_BOTH_INT       31
 #define AU1000_GPIO_0             32
@@ -645,20 +916,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
-#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
+#define USB_UOC_BASE              0x14020020
-#define USB_HOST_CONFIG           0xB4027ffc
+#define USB_UOC_LEN               0x20
+#define USB_OHCI_BASE             0x14020100
-// these are here for prototyping on au1550 (do not exist on au1200)
+#define USB_OHCI_LEN              0x100
-#define AU1200_ETH0_BASE      0xB0500000
+#define USB_EHCI_BASE             0x14020200
-#define AU1200_ETH1_BASE      0xB0510000
+#define USB_EHCI_LEN              0x100
-#define AU1200_MAC0_ENABLE       0xB0520000
+#define USB_UDC_BASE              0x14022000
-#define AU1200_MAC1_ENABLE       0xB0520004
+#define USB_UDC_LEN               0x2000
-#define NUM_ETH_INTERFACES 2
+#define USB_MSR_BASE                      0xB4020000
-#endif // CONFIG_SOC_AU1200
+#define USB_MSR_MCFG              4
+#define USBMSRMCFG_OMEMEN         0
+#define USBMSRMCFG_OBMEN          1
+#define USBMSRMCFG_EMEMEN         2
+#define USBMSRMCFG_EBMEN          3
+#define USBMSRMCFG_DMEMEN         4
+#define USBMSRMCFG_DBMEN          5
+#define USBMSRMCFG_GMEMEN         6
+#define USBMSRMCFG_OHCCLKEN       16
+#define USBMSRMCFG_EHCCLKEN       17
+#define USBMSRMCFG_UDCCLKEN       18
+#define USBMSRMCFG_PHYPLLEN       19
+#define USBMSRMCFG_RDCOMB         30
+#define USBMSRMCFG_PFEN           31
+#endif /* CONFIG_SOC_AU1200 */
 #define AU1000_LAST_INTC0_INT     31
+#define AU1000_LAST_INTC1_INT     63
 #define AU1000_MAX_INTR           63
+#define INTX                    0xFF /* not valid */
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE                   0xB1900000
@@ -730,6 +1017,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
  #define I2S_CONTROL_D         (1<<1)
  #define I2S_CONTROL_CE        (1<<0)
+#ifndef CONFIG_SOC_AU1200
 /* USB Host Controller */
 #define USB_OHCI_LEN              0x00100000
@@ -775,6 +1064,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
  #define USBDEV_ENABLE (1<<1)
  #define USBDEV_CE     (1<<0)
+#endif /* !CONFIG_SOC_AU1200 */
 /* Ethernet Controllers  */
 /* 4 byte offsets from AU1000_ETH_BASE */
@@ -1173,6 +1464,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
  #define SYS_PF_PSC1_S1                (1 << 1)
  #define SYS_PF_MUST_BE_SET            ((1 << 5) | (1 << 2))
+/* Au1200 Only */
+#ifdef CONFIG_SOC_AU1200
+#define SYS_PINFUNC_DMA         (1<<31)
+#define SYS_PINFUNC_S0A         (1<<30)
+#define SYS_PINFUNC_S1A         (1<<29)
+#define SYS_PINFUNC_LP0         (1<<28)
+#define SYS_PINFUNC_LP1         (1<<27)
+#define SYS_PINFUNC_LD16        (1<<26)
+#define SYS_PINFUNC_LD8         (1<<25)
+#define SYS_PINFUNC_LD1         (1<<24)
+#define SYS_PINFUNC_LD0         (1<<23)
+#define SYS_PINFUNC_P1A         (3<<21)
+#define SYS_PINFUNC_P1B         (1<<20)
+#define SYS_PINFUNC_FS3         (1<<19)
+#define SYS_PINFUNC_P0A         (3<<17)
+#define SYS_PINFUNC_CS          (1<<16)
+#define SYS_PINFUNC_CIM         (1<<15)
+#define SYS_PINFUNC_P1C         (1<<14)
+#define SYS_PINFUNC_U1T         (1<<12)
+#define SYS_PINFUNC_U1R         (1<<11)
+#define SYS_PINFUNC_EX1         (1<<10)
+#define SYS_PINFUNC_EX0         (1<<9)
+#define SYS_PINFUNC_U0R         (1<<8)
+#define SYS_PINFUNC_MC          (1<<7)
+#define SYS_PINFUNC_S0B         (1<<6)
+#define SYS_PINFUNC_S0C         (1<<5)
+#define SYS_PINFUNC_P0B         (1<<4)
+#define SYS_PINFUNC_U0T         (1<<3)
+#define SYS_PINFUNC_S1B         (1<<2)
+#endif
 #define SYS_TRIOUTRD              0xB1900100
 #define SYS_TRIOUTCLR             0xB1900100
 #define SYS_OUTPUTRD              0xB1900108
@@ -1239,6 +1561,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
  #define SYS_CS_MI2_MASK           (0x7<<SYS_CS_MI2_BIT)
  #define SYS_CS_DI2                (1<<16)
  #define SYS_CS_CI2                (1<<15)
+#ifdef CONFIG_SOC_AU1100
+  #define SYS_CS_ML_BIT             7
+  #define SYS_CS_ML_MASK            (0x7<<SYS_CS_ML_BIT)
+  #define SYS_CS_DL                 (1<<6)
+  #define SYS_CS_CL                 (1<<5)
+#else
  #define SYS_CS_MUH_BIT            12
  #define SYS_CS_MUH_MASK           (0x7<<SYS_CS_MUH_BIT)
  #define SYS_CS_DUH                (1<<11)
@@ -1247,6 +1575,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
  #define SYS_CS_MUD_MASK           (0x7<<SYS_CS_MUD_BIT)
  #define SYS_CS_DUD                (1<<6)
  #define SYS_CS_CUD                (1<<5)
+#endif
  #define SYS_CS_MIR_BIT            2
  #define SYS_CS_MIR_MASK           (0x7<<SYS_CS_MIR_BIT)
  #define SYS_CS_DIR                (1<<1)
@@ -1300,7 +1629,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define SD1_XMIT_FIFO   0xB0680000
 #define SD1_RECV_FIFO   0xB0680004
 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE           0xB4005000 // virtual, kseg0 addr
@@ -1363,36 +1691,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
                      _ctl_; })
-#else /* Au1000 and Au1100 */
+#else /* Au1000 and Au1100 and Au1200 */
 /* don't allow any legacy ports probing */
-#define IOPORT_RESOURCE_START 0x10000000;
+#define IOPORT_RESOURCE_START 0x10000000
 #define IOPORT_RESOURCE_END   0xffffffff
 #define IOMEM_RESOURCE_START  0x10000000
 #define IOMEM_RESOURCE_END    0xffffffff
-#ifdef CONFIG_MIPS_PB1000
-#define PCI_IO_START      0x10000000
-#define PCI_IO_END        0x1000ffff
-#define PCI_MEM_START     0x18000000
-#define PCI_MEM_END       0x18ffffff
-#define PCI_FIRST_DEVFN   0
-#define PCI_LAST_DEVFN    1
-#else
-/* no PCI bus controller */
 #define PCI_IO_START    0
 #define PCI_IO_END      0
 #define PCI_MEM_START   0
 #define PCI_MEM_END     0
 #define PCI_FIRST_DEVFN 0
 #define PCI_LAST_DEVFN  0
-#endif
 #endif
+#ifndef _LANGUAGE_ASSEMBLY
+typedef volatile struct
+{
+        /* 0x0000 */ u32 toytrim;
+        /* 0x0004 */ u32 toywrite;
+        /* 0x0008 */ u32 toymatch0;
+        /* 0x000C */ u32 toymatch1;
+        /* 0x0010 */ u32 toymatch2;
+        /* 0x0014 */ u32 cntrctrl;
+        /* 0x0018 */ u32 scratch0;
+        /* 0x001C */ u32 scratch1;
+        /* 0x0020 */ u32 freqctrl0;
+        /* 0x0024 */ u32 freqctrl1;
+        /* 0x0028 */ u32 clksrc;
+        /* 0x002C */ u32 pinfunc;
+        /* 0x0030 */ u32 reserved0;
+        /* 0x0034 */ u32 wakemsk;
+        /* 0x0038 */ u32 endian;
+        /* 0x003C */ u32 powerctrl;
+        /* 0x0040 */ u32 toyread;
+        /* 0x0044 */ u32 rtctrim;
+        /* 0x0048 */ u32 rtcwrite;
+        /* 0x004C */ u32 rtcmatch0;
+        /* 0x0050 */ u32 rtcmatch1;
+        /* 0x0054 */ u32 rtcmatch2;
+        /* 0x0058 */ u32 rtcread;
+        /* 0x005C */ u32 wakesrc;
+        /* 0x0060 */ u32 cpupll;
+        /* 0x0064 */ u32 auxpll;
+        /* 0x0068 */ u32 reserved1;
+        /* 0x006C */ u32 reserved2;
+        /* 0x0070 */ u32 reserved3;
+        /* 0x0074 */ u32 reserved4;
+        /* 0x0078 */ u32 slppwr;
+        /* 0x007C */ u32 sleep;
+        /* 0x0080 */ u32 reserved5[32];
+        /* 0x0100 */ u32 trioutrd;
+#define trioutclr trioutrd
+        /* 0x0104 */ u32 reserved6;
+        /* 0x0108 */ u32 outputrd;
+#define outputset outputrd
+        /* 0x010C */ u32 outputclr;
+        /* 0x0110 */ u32 pinstaterd;
+#define pininputen pinstaterd
+} AU1X00_SYS;
+static AU1X00_SYS* const sys  = (AU1X00_SYS *)SYS_BASE;
+#endif
 /* Processor information base on prid.
 * Copied from PowerPC.
 */
+#ifndef _LANGUAGE_ASSEMBLY
 struct cpu_spec {
        /* CPU is matched via (PRID & prid_mask) == prid_value */
        unsigned int    prid_mask;
@@ -1406,3 +1775,6 @@ struct cpu_spec {
 extern struct cpu_spec          cpu_specs[];
 extern struct cpu_spec          *cur_cpu_spec[];
 #endif
+#endif
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h
new file mode 100644
index 000000000000..b7b46dd9b929
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx.h
@@ -0,0 +1,44 @@
+/*
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _AU1XXX_H_
+#define _AU1XXX_H_
+#include <linux/config.h>
+#include <asm/mach-au1x00/au1000.h>
+#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
+#include <asm/mach-db1x00/db1x00.h>
+#elif defined(CONFIG_MIPS_PB1550)
+#include <asm/mach-pb1x00/pb1550.h>
+#elif defined(CONFIG_MIPS_PB1200)
+#include <asm/mach-pb1x00/pb1200.h>
+#elif defined(CONFIG_MIPS_DB1200)
+#include <asm/mach-db1x00/db1200.h>
+#endif
+#endif /* _AU1XXX_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index d5eb88cd7d51..b327bcd3fee1 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -45,7 +45,7 @@
 #define DDMA_GLOBAL_BASE        0xb4003000
 #define DDMA_CHANNEL_BASE       0xb4002000
-typedef struct dbdma_global {
+typedef volatile struct dbdma_global {
        u32     ddma_config;
        u32     ddma_intstat;
        u32     ddma_throttle;
@@ -62,7 +62,7 @@ typedef struct dbdma_global {
 /* The structure of a DMA Channel.
 */
-typedef struct au1xxx_dma_channel {
+typedef volatile struct au1xxx_dma_channel {
        u32     ddma_cfg;       /* See below */
        u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
        u32     ddma_statptr;   /* word aligned pointer to status word */
@@ -98,7 +98,7 @@ typedef struct au1xxx_dma_channel {
 /* "Standard" DDMA Descriptor.
 * Must be 32-byte aligned.
 */
-typedef struct au1xxx_ddma_desc {
+typedef volatile struct au1xxx_ddma_desc {
        u32     dscr_cmd0;              /* See below */
        u32     dscr_cmd1;              /* See below */
        u32     dscr_source0;           /* source phys address */
@@ -107,6 +107,12 @@ typedef struct au1xxx_ddma_desc {
        u32     dscr_dest1;             /* See below */
        u32     dscr_stat;              /* completion status */
        u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
+        /* First 32bytes are HW specific!!!
+           Lets have some SW data following.. make sure its 32bytes
+         */
+        u32     sw_status;
+        u32     sw_context;
+        u32     sw_reserved[6];
 } au1x_ddma_desc_t;
 #define DSCR_CMD0_V             (1 << 31)       /* Descriptor valid */
@@ -125,8 +131,11 @@ typedef struct au1xxx_ddma_desc {
 #define DSCR_CMD0_CV            (0x1 << 2)      /* Clear Valid when done */
 #define DSCR_CMD0_ST_MASK       (0x3 << 0)      /* Status instruction */
+#define SW_STATUS_INUSE         (1<<0)
 /* Command 0 device IDs.
 */
+#ifdef CONFIG_SOC_AU1550
 #define DSCR_CMD0_UART0_TX      0
 #define DSCR_CMD0_UART0_RX      1
 #define DSCR_CMD0_UART3_TX      2
@@ -155,9 +164,45 @@ typedef struct au1xxx_ddma_desc {
 #define DSCR_CMD0_MAC0_TX       25
 #define DSCR_CMD0_MAC1_RX       26
 #define DSCR_CMD0_MAC1_TX       27
+#endif /* CONFIG_SOC_AU1550 */
+#ifdef CONFIG_SOC_AU1200
+#define DSCR_CMD0_UART0_TX      0
+#define DSCR_CMD0_UART0_RX      1
+#define DSCR_CMD0_UART1_TX      2
+#define DSCR_CMD0_UART1_RX      3
+#define DSCR_CMD0_DMA_REQ0      4
+#define DSCR_CMD0_DMA_REQ1      5
+#define DSCR_CMD0_MAE_BE        6
+#define DSCR_CMD0_MAE_FE        7
+#define DSCR_CMD0_SDMS_TX0      8
+#define DSCR_CMD0_SDMS_RX0      9
+#define DSCR_CMD0_SDMS_TX1      10
+#define DSCR_CMD0_SDMS_RX1      11
+#define DSCR_CMD0_AES_TX        13
+#define DSCR_CMD0_AES_RX        12
+#define DSCR_CMD0_PSC0_TX       14
+#define DSCR_CMD0_PSC0_RX       15
+#define DSCR_CMD0_PSC1_TX       16
+#define DSCR_CMD0_PSC1_RX       17
+#define DSCR_CMD0_CIM_RXA       18
+#define DSCR_CMD0_CIM_RXB       19
+#define DSCR_CMD0_CIM_RXC       20
+#define DSCR_CMD0_MAE_BOTH      21
+#define DSCR_CMD0_LCD           22
+#define DSCR_CMD0_NAND_FLASH    23
+#define DSCR_CMD0_PSC0_SYNC     24
+#define DSCR_CMD0_PSC1_SYNC     25
+#define DSCR_CMD0_CIM_SYNC      26
+#endif /* CONFIG_SOC_AU1200 */
 #define DSCR_CMD0_THROTTLE      30
 #define DSCR_CMD0_ALWAYS        31
 #define DSCR_NDEV_IDS           32
+/* THis macro is used to find/create custom device types */
+#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
+#define DSCR_CUSTOM2DEV_ID(x)   ((x)&0xFF)
 #define DSCR_CMD0_SID(x)        (((x) & 0x1f) << 25)
 #define DSCR_CMD0_DID(x)        (((x) & 0x1f) << 20)
@@ -246,6 +291,43 @@ typedef struct au1xxx_ddma_desc {
 */
 #define NUM_DBDMA_CHANS 16
+/*
+ * Ddma API definitions
+ * FIXME: may not fit to this header file
+ */
+typedef struct dbdma_device_table {
+        u32             dev_id;
+        u32             dev_flags;
+        u32             dev_tsize;
+        u32             dev_devwidth;
+        u32             dev_physaddr;           /* If FIFO */
+        u32             dev_intlevel;
+        u32             dev_intpolarity;
+} dbdev_tab_t;
+typedef struct dbdma_chan_config {
+        spinlock_t      lock;
+        u32                     chan_flags;
+        u32                     chan_index;
+        dbdev_tab_t             *chan_src;
+        dbdev_tab_t             *chan_dest;
+        au1x_dma_chan_t         *chan_ptr;
+        au1x_ddma_desc_t        *chan_desc_base;
+        au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
+        void                    *chan_callparam;
+        void (*chan_callback)(int, void *, struct pt_regs *);
+} chan_tab_t;
+#define DEV_FLAGS_INUSE         (1 << 0)
+#define DEV_FLAGS_ANYUSE        (1 << 1)
+#define DEV_FLAGS_OUT           (1 << 2)
+#define DEV_FLAGS_IN            (1 << 3)
+#define DEV_FLAGS_BURSTABLE (1 << 4)
+#define DEV_FLAGS_SYNC          (1 << 5)
+/* end Ddma API definitions */
 /* External functions for drivers to use.
 */
 /* Use this to allocate a dbdma channel.  The device ids are one of the
@@ -258,18 +340,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
 #define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
-/* ACK!  These should be in a board specific description file.
-*/
-#ifdef CONFIG_MIPS_PB1550
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#endif
-#ifdef CONFIG_MIPS_DB1550
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#endif
 /* Set the device width of a in/out fifo.
 */
 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
@@ -280,8 +350,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
 /* Put buffers on source/destination descriptors.
 */
-u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
+u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
-u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
+u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
 /* Get a buffer from the destination descriptor.
 */
@@ -295,5 +365,29 @@ u32 au1xxx_get_dma_residue(u32 chanid);
 void au1xxx_dbdma_chan_free(u32 chanid);
 void au1xxx_dbdma_dump(u32 chanid);
+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
+u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
+void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
+/*
+        Some compatibilty macros --
+                Needed to make changes to API without breaking existing drivers
+*/
+#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
+#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags)
+#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
+#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags)
+/*
+ *      Flags for the put_source/put_dest functions.
+ */
+#define DDMA_FLAGS_IE   (1<<0)
+#define DDMA_FLAGS_NOIE (1<<1)
 #endif /* _LANGUAGE_ASSEMBLY */
 #endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
new file mode 100644
index 000000000000..27911e054ffc
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
@@ -0,0 +1,20 @@
+#ifndef __AU1XXX_GPIO_H
+#define __AU1XXX_GPIO_H
+void au1xxx_gpio1_set_inputs(void);
+void au1xxx_gpio_tristate(int signal);
+void au1xxx_gpio_write(int signal, int value);
+int  au1xxx_gpio_read(int signal);
+typedef volatile struct
+{
+        u32 dir;
+        u32 reserved;
+        u32 output;
+        u32 pinstate;
+        u32 inten;
+        u32 enable;
+} AU1X00_GPIO2;
+#endif //__AU1XXX_GPIO_H
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
new file mode 100644
index 000000000000..33d275c3b84c
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -0,0 +1,301 @@
+/*
+ * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
+ *
+ * BRIEF MODULE DESCRIPTION
+ * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
+ *
+ * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
+ *       Interface and Linux Device Driver" Application Note.
+ */
+#include <linux/config.h>
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+        #define DMA_WAIT_TIMEOUT        100
+        #define NUM_DESCRIPTORS         PRD_ENTRIES
+#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
+        #define NUM_DESCRIPTORS         2
+#endif
+#ifndef AU1XXX_ATA_RQSIZE
+        #define AU1XXX_ATA_RQSIZE       128
+#endif
+/* Disable Burstable-Support for DBDMA */
+#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
+        #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON  0
+#endif
+#ifdef CONFIG_PM
+/*
+* This will enable the device to be powered up when write() or read()
+* is called. If this is not defined, the driver will return -EBUSY.
+*/
+#define WAKE_ON_ACCESS 1
+typedef struct
+{
+        spinlock_t         lock;       /* Used to block on state transitions */
+        au1xxx_power_dev_t *dev;       /* Power Managers device structure */
+        unsigned           stopped;    /* USed to signaling device is stopped */
+} pm_state;
+#endif
+typedef struct
+{
+        u32                     tx_dev_id, rx_dev_id, target_dev_id;
+        u32                     tx_chan, rx_chan;
+        void                    *tx_desc_head, *rx_desc_head;
+        ide_hwif_t              *hwif;
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+        ide_drive_t             *drive;
+        u8                      white_list, black_list;
+        struct dbdma_cmd        *dma_table_cpu;
+        dma_addr_t              dma_table_dma;
+        struct scatterlist      *sg_table;
+        int                     sg_nents;
+        int                     sg_dma_direction;
+#endif
+        struct device           *dev;
+        int                     irq;
+        u32                     regbase;
+#ifdef CONFIG_PM
+        pm_state                pm;
+#endif
+} _auide_hwif;
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+struct drive_list_entry {
+        const char * id_model;
+        const char * id_firmware;
+};
+/* HD white list */
+static const struct drive_list_entry dma_white_list [] = {
+/*
+ * Hitachi
+ */
+        { "HITACHI_DK14FA-20"    ,       "ALL"           },
+        { "HTS726060M9AT00"      ,       "ALL"           },
+/*
+ * Maxtor
+ */
+        { "Maxtor 6E040L0"      ,       "ALL"           },
+        { "Maxtor 6Y080P0"      ,       "ALL"           },
+        { "Maxtor 6Y160P0"      ,       "ALL"           },
+/*
+ * Seagate
+ */
+        { "ST3120026A"          ,       "ALL"           },
+        { "ST320014A"           ,       "ALL"           },
+        { "ST94011A"            ,       "ALL"           },
+        { "ST340016A"           ,       "ALL"           },
+/*
+ * Western Digital
+ */
+        { "WDC WD400UE-00HCT0"  ,       "ALL"           },
+        { "WDC WD400JB-00JJC0"  ,       "ALL"           },
+        { NULL                  ,       NULL            }
+};
+/* HD black list */
+static const struct drive_list_entry dma_black_list [] = {
+/*
+ * Western Digital
+ */
+        { "WDC WD100EB-00CGH0"  ,       "ALL"           },
+        { "WDC WD200BB-00AUA1"  ,       "ALL"           },
+        { "WDC AC24300L"        ,       "ALL"           },
+        { NULL                  ,       NULL            }
+};
+#endif
+/* function prototyping */
+u8 auide_inb(unsigned long port);
+u16 auide_inw(unsigned long port);
+u32 auide_inl(unsigned long port);
+void auide_insw(unsigned long port, void *addr, u32 count);
+void auide_insl(unsigned long port, void *addr, u32 count);
+void auide_outb(u8 addr, unsigned long port);
+void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port);
+void auide_outw(u16 addr, unsigned long port);
+void auide_outl(u32 addr, unsigned long port);
+void auide_outsw(unsigned long port, void *addr, u32 count);
+void auide_outsl(unsigned long port, void *addr, u32 count);
+static void auide_tune_drive(ide_drive_t *drive, byte pio);
+static int auide_tune_chipset (ide_drive_t *drive, u8 speed);
+static int auide_ddma_init( _auide_hwif *auide );
+static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
+int __init auide_probe(void);
+#ifdef CONFIG_PM
+        int au1200ide_pm_callback( au1xxx_power_dev_t *dev,
+                                   au1xxx_request_t request, void *data);
+        static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_access( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev );
+        static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev );
+#endif
+/*
+ * Multi-Word DMA + DbDMA functions
+ */
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+        static int in_drive_list(struct hd_driveid *id,
+                                 const struct drive_list_entry *drive_table);
+        static int auide_build_sglist(ide_drive_t *drive,  struct request *rq);
+        static int auide_build_dmatable(ide_drive_t *drive);
+        static int auide_dma_end(ide_drive_t *drive);
+        static void auide_dma_start(ide_drive_t *drive );
+        ide_startstop_t auide_dma_intr (ide_drive_t *drive);
+        static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command);
+        static int auide_dma_setup(ide_drive_t *drive);
+        static int auide_dma_check(ide_drive_t *drive);
+        static int auide_dma_test_irq(ide_drive_t *drive);
+        static int auide_dma_host_off(ide_drive_t *drive);
+        static int auide_dma_host_on(ide_drive_t *drive);
+        static int auide_dma_lostirq(ide_drive_t *drive);
+        static int auide_dma_on(ide_drive_t *drive);
+        static void auide_ddma_tx_callback(int irq, void *param,
+                                           struct pt_regs *regs);
+        static void auide_ddma_rx_callback(int irq, void *param,
+                                           struct pt_regs *regs);
+        static int auide_dma_off_quietly(ide_drive_t *drive);
+        static int auide_dma_timeout(ide_drive_t *drive);
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
+/*******************************************************************************
+* PIO Mode timing calculation :                                                *
+*                                                                              *
+* Static Bus Spec   ATA Spec                                                   *
+*      Tcsoe      =   t1                                                       *
+*      Toecs      =   t9                                                       *
+*      Twcs       =   t9                                                       *
+*      Tcsh       =   t2i | t2                                                 *
+*      Tcsoff     =   t2i | t2                                                 *
+*      Twp        =   t2                                                       *
+*      Tcsw       =   t1                                                       *
+*      Tpm        =   0                                                        *
+*      Ta         =   t1+t2                                                    *
+*******************************************************************************/
+#define TCSOE_MASK            (0x07<<29)
+#define TOECS_MASK            (0x07<<26)
+#define TWCS_MASK             (0x07<<28)
+#define TCSH_MASK             (0x0F<<24)
+#define TCSOFF_MASK           (0x07<<20)
+#define TWP_MASK              (0x3F<<14)
+#define TCSW_MASK             (0x0F<<10)
+#define TPM_MASK              (0x0F<<6)
+#define TA_MASK               (0x3F<<0)
+#define TS_MASK               (1<<8)
+/* Timing parameters PIO mode 0 */
+#define SBC_IDE_PIO0_TCSOE    (0x04<<29)
+#define SBC_IDE_PIO0_TOECS    (0x01<<26)
+#define SBC_IDE_PIO0_TWCS     (0x02<<28)
+#define SBC_IDE_PIO0_TCSH     (0x08<<24)
+#define SBC_IDE_PIO0_TCSOFF   (0x07<<20)
+#define SBC_IDE_PIO0_TWP      (0x10<<14)
+#define SBC_IDE_PIO0_TCSW     (0x04<<10)
+#define SBC_IDE_PIO0_TPM      (0x0<<6)
+#define SBC_IDE_PIO0_TA       (0x15<<0)
+/* Timing parameters PIO mode 1 */
+#define SBC_IDE_PIO1_TCSOE    (0x03<<29)
+#define SBC_IDE_PIO1_TOECS    (0x01<<26)
+#define SBC_IDE_PIO1_TWCS     (0x01<<28)
+#define SBC_IDE_PIO1_TCSH     (0x06<<24)
+#define SBC_IDE_PIO1_TCSOFF   (0x06<<20)
+#define SBC_IDE_PIO1_TWP      (0x08<<14)
+#define SBC_IDE_PIO1_TCSW     (0x03<<10)
+#define SBC_IDE_PIO1_TPM      (0x00<<6)
+#define SBC_IDE_PIO1_TA       (0x0B<<0)
+/* Timing parameters PIO mode 2 */
+#define SBC_IDE_PIO2_TCSOE    (0x05<<29)
+#define SBC_IDE_PIO2_TOECS    (0x01<<26)
+#define SBC_IDE_PIO2_TWCS     (0x01<<28)
+#define SBC_IDE_PIO2_TCSH     (0x07<<24)
+#define SBC_IDE_PIO2_TCSOFF   (0x07<<20)
+#define SBC_IDE_PIO2_TWP      (0x1F<<14)
+#define SBC_IDE_PIO2_TCSW     (0x05<<10)
+#define SBC_IDE_PIO2_TPM      (0x00<<6)
+#define SBC_IDE_PIO2_TA       (0x22<<0)
+/* Timing parameters PIO mode 3 */
+#define SBC_IDE_PIO3_TCSOE    (0x05<<29)
+#define SBC_IDE_PIO3_TOECS    (0x01<<26)
+#define SBC_IDE_PIO3_TWCS     (0x01<<28)
+#define SBC_IDE_PIO3_TCSH     (0x0D<<24)
+#define SBC_IDE_PIO3_TCSOFF   (0x0D<<20)
+#define SBC_IDE_PIO3_TWP      (0x15<<14)
+#define SBC_IDE_PIO3_TCSW     (0x05<<10)
+#define SBC_IDE_PIO3_TPM      (0x00<<6)
+#define SBC_IDE_PIO3_TA       (0x1A<<0)
+/* Timing parameters PIO mode 4 */
+#define SBC_IDE_PIO4_TCSOE    (0x04<<29)
+#define SBC_IDE_PIO4_TOECS    (0x01<<26)
+#define SBC_IDE_PIO4_TWCS     (0x01<<28)
+#define SBC_IDE_PIO4_TCSH     (0x04<<24)
+#define SBC_IDE_PIO4_TCSOFF   (0x04<<20)
+#define SBC_IDE_PIO4_TWP      (0x0D<<14)
+#define SBC_IDE_PIO4_TCSW     (0x03<<10)
+#define SBC_IDE_PIO4_TPM      (0x00<<6)
+#define SBC_IDE_PIO4_TA       (0x12<<0)
+/* Timing parameters MDMA mode 0 */
+#define SBC_IDE_MDMA0_TCSOE   (0x03<<29)
+#define SBC_IDE_MDMA0_TOECS   (0x01<<26)
+#define SBC_IDE_MDMA0_TWCS    (0x01<<28)
+#define SBC_IDE_MDMA0_TCSH    (0x07<<24)
+#define SBC_IDE_MDMA0_TCSOFF  (0x07<<20)
+#define SBC_IDE_MDMA0_TWP     (0x0C<<14)
+#define SBC_IDE_MDMA0_TCSW    (0x03<<10)
+#define SBC_IDE_MDMA0_TPM     (0x00<<6)
+#define SBC_IDE_MDMA0_TA      (0x0F<<0)
+/* Timing parameters MDMA mode 1 */
+#define SBC_IDE_MDMA1_TCSOE   (0x05<<29)
+#define SBC_IDE_MDMA1_TOECS   (0x01<<26)
+#define SBC_IDE_MDMA1_TWCS    (0x01<<28)
+#define SBC_IDE_MDMA1_TCSH    (0x05<<24)
+#define SBC_IDE_MDMA1_TCSOFF  (0x05<<20)
+#define SBC_IDE_MDMA1_TWP     (0x0F<<14)
+#define SBC_IDE_MDMA1_TCSW    (0x05<<10)
+#define SBC_IDE_MDMA1_TPM     (0x00<<6)
+#define SBC_IDE_MDMA1_TA      (0x15<<0)
+/* Timing parameters MDMA mode 2 */
+#define SBC_IDE_MDMA2_TCSOE   (0x04<<29)
+#define SBC_IDE_MDMA2_TOECS   (0x01<<26)
+#define SBC_IDE_MDMA2_TWCS    (0x01<<28)
+#define SBC_IDE_MDMA2_TCSH    (0x04<<24)
+#define SBC_IDE_MDMA2_TCSOFF  (0x04<<20)
+#define SBC_IDE_MDMA2_TWP     (0x0D<<14)
+#define SBC_IDE_MDMA2_TCSW    (0x04<<10)
+#define SBC_IDE_MDMA2_TPM     (0x00<<6)
+#define SBC_IDE_MDMA2_TA      (0x12<<0)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index 283519dfdec4..8e5fb3c7da4d 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -33,6 +33,8 @@
 #ifndef _AU1000_PSC_H_
 #define _AU1000_PSC_H_
+#include <linux/config.h>
 /* The PSC base addresses.  */
 #ifdef CONFIG_SOC_AU1550
 #define PSC0_BASE_ADDR          0xb1a00000
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
new file mode 100644
index 000000000000..d3ec6274575a
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/ioremap.h
@@ -0,0 +1,32 @@
+/*
+ *      include/asm-mips/mach-au1x00/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_AU1X00_IOREMAP_H
+#define __ASM_MACH_AU1X00_IOREMAP_H
+#include <linux/config.h>
+#include <linux/types.h>
+#ifdef CONFIG_64BIT_PHYS_ADDR
+extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
+#else
+static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+#endif
+/*
+ * Allow physical addresses to be fixed up to help 36-bit peripherals.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return __fixup_bigphys_addr(phys_addr, size);
+}
+#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
new file mode 100644
index 000000000000..5d894376fc1a
--- /dev/null
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -0,0 +1,224 @@
+/*
+ * AMD Alchemy DB1200 Referrence Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_DB1200_H
+#define __ASM_DB1200_H
+#include <linux/types.h>
+// This is defined in au1000.h with bogus value
+#undef AU1X00_EXTERNAL_INT
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+/* SPI and SMB are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
+/* AC97 and I2S are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE            PSC1_BASE_ADDR
+#define BCSR_KSEG1_ADDR 0xB9800000
+typedef volatile struct
+{
+        /*00*/  u16 whoami;
+                u16 reserved0;
+        /*04*/  u16 status;
+                u16 reserved1;
+        /*08*/  u16 switches;
+                u16 reserved2;
+        /*0C*/  u16 resets;
+                u16 reserved3;
+        /*10*/  u16 pcmcia;
+                u16 reserved4;
+        /*14*/  u16 board;
+                u16 reserved5;
+        /*18*/  u16 disk_leds;
+                u16 reserved6;
+        /*1C*/  u16 system;
+                u16 reserved7;
+        /*20*/  u16 intclr;
+                u16 reserved8;
+        /*24*/  u16 intset;
+                u16 reserved9;
+        /*28*/  u16 intclr_mask;
+                u16 reserved10;
+        /*2C*/  u16 intset_mask;
+                u16 reserved11;
+        /*30*/  u16 sig_status;
+                u16 reserved12;
+        /*34*/  u16 int_status;
+                u16 reserved13;
+        /*38*/  u16 reserved14;
+                u16 reserved15;
+        /*3C*/  u16 reserved16;
+                u16 reserved17;
+} BCSR;
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID        0x000F
+#define BCSR_WHOAMI_CPLD        0x00F0
+#define BCSR_WHOAMI_BOARD       0x0F00
+#define BCSR_STATUS_PCMCIA0VS   0x0003
+#define BCSR_STATUS_PCMCIA1VS   0x000C
+#define BCSR_STATUS_SWAPBOOT    0x0040
+#define BCSR_STATUS_FLASHBUSY   0x0100
+#define BCSR_STATUS_IDECBLID    0x0200
+#define BCSR_STATUS_SD0WP               0x0400
+#define BCSR_STATUS_U0RXD               0x1000
+#define BCSR_STATUS_U1RXD               0x2000
+#define BCSR_SWITCHES_OCTAL     0x00FF
+#define BCSR_SWITCHES_DIP_1     0x0080
+#define BCSR_SWITCHES_DIP_2     0x0040
+#define BCSR_SWITCHES_DIP_3     0x0020
+#define BCSR_SWITCHES_DIP_4     0x0010
+#define BCSR_SWITCHES_DIP_5     0x0008
+#define BCSR_SWITCHES_DIP_6     0x0004
+#define BCSR_SWITCHES_DIP_7     0x0002
+#define BCSR_SWITCHES_DIP_8     0x0001
+#define BCSR_SWITCHES_ROTARY    0x0F00
+#define BCSR_RESETS_ETH         0x0001
+#define BCSR_RESETS_CAMERA      0x0002
+#define BCSR_RESETS_DC          0x0004
+#define BCSR_RESETS_IDE         0x0008
+#define BCSR_RESETS_TV          0x0010
+/* not resets but in the same register */
+#define BCSR_RESETS_PWMR1mUX 0x0800
+#define BCSR_RESETS_PCS0MUX     0x1000
+#define BCSR_RESETS_PCS1MUX     0x2000
+#define BCSR_RESETS_SPISEL      0x4000
+#define BCSR_PCMCIA_PC0VPP      0x0003
+#define BCSR_PCMCIA_PC0VCC      0x000C
+#define BCSR_PCMCIA_PC0DRVEN    0x0010
+#define BCSR_PCMCIA_PC0RST      0x0080
+#define BCSR_PCMCIA_PC1VPP      0x0300
+#define BCSR_PCMCIA_PC1VCC      0x0C00
+#define BCSR_PCMCIA_PC1DRVEN    0x1000
+#define BCSR_PCMCIA_PC1RST      0x8000
+#define BCSR_BOARD_LCDVEE       0x0001
+#define BCSR_BOARD_LCDVDD       0x0002
+#define BCSR_BOARD_LCDBL        0x0004
+#define BCSR_BOARD_CAMSNAP      0x0010
+#define BCSR_BOARD_CAMPWR       0x0020
+#define BCSR_BOARD_SD0PWR       0x0040
+#define BCSR_LEDS_DECIMALS      0x0003
+#define BCSR_LEDS_LED0          0x0100
+#define BCSR_LEDS_LED1          0x0200
+#define BCSR_LEDS_LED2          0x0400
+#define BCSR_LEDS_LED3          0x0800
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE            0x0001
+#define BCSR_INT_ETH            0x0002
+#define BCSR_INT_PC0            0x0004
+#define BCSR_INT_PC0STSCHG      0x0008
+#define BCSR_INT_PC1            0x0010
+#define BCSR_INT_PC1STSCHG      0x0020
+#define BCSR_INT_DC                     0x0040
+#define BCSR_INT_FLASHBUSY      0x0080
+#define BCSR_INT_PC0INSERT      0x0100
+#define BCSR_INT_PC0EJECT       0x0200
+#define BCSR_INT_PC1INSERT      0x0400
+#define BCSR_INT_PC1EJECT       0x0800
+#define BCSR_INT_SD0INSERT      0x1000
+#define BCSR_INT_SD0EJECT       0x2000
+#define AU1XXX_SMC91111_PHYS_ADDR       (0x19000300)
+#define AU1XXX_SMC91111_IRQ                     DB1200_ETH_INT
+#define AU1XXX_ATA_PHYS_ADDR            (0x18800000)
+#define AU1XXX_ATA_PHYS_LEN                     (0x100)
+#define AU1XXX_ATA_REG_OFFSET   (5)
+#define AU1XXX_ATA_INT                  DB1200_IDE_INT
+#define AU1XXX_ATA_DDMA_REQ             DSCR_CMD0_DMA_REQ1;
+#define AU1XXX_ATA_RQSIZE               128
+#define NAND_PHYS_ADDR   0x20000000
+/*
+ *      External Interrupts for Pb1200 as of 8/6/2004.
+ *   Bit positions in the CPLD registers can be calculated by taking
+ *   the interrupt define and subtracting the DB1200_INT_BEGIN value.
+ *    *example: IDE bis pos is  = 64 - 64
+                ETH bit pos is  = 65 - 64
+ */
+#define DB1200_INT_BEGIN                (AU1000_LAST_INTC1_INT + 1)
+#define DB1200_IDE_INT                  (DB1200_INT_BEGIN + 0)
+#define DB1200_ETH_INT                  (DB1200_INT_BEGIN + 1)
+#define DB1200_PC0_INT                  (DB1200_INT_BEGIN + 2)
+#define DB1200_PC0_STSCHG_INT   (DB1200_INT_BEGIN + 3)
+#define DB1200_PC1_INT                  (DB1200_INT_BEGIN + 4)
+#define DB1200_PC1_STSCHG_INT   (DB1200_INT_BEGIN + 5)
+#define DB1200_DC_INT                   (DB1200_INT_BEGIN + 6)
+#define DB1200_FLASHBUSY_INT    (DB1200_INT_BEGIN + 7)
+#define DB1200_PC0_INSERT_INT   (DB1200_INT_BEGIN + 8)
+#define DB1200_PC0_EJECT_INT    (DB1200_INT_BEGIN + 9)
+#define DB1200_PC1_INSERT_INT   (DB1200_INT_BEGIN + 10)
+#define DB1200_PC1_EJECT_INT    (DB1200_INT_BEGIN + 11)
+#define DB1200_SD0_INSERT_INT   (DB1200_INT_BEGIN + 12)
+#define DB1200_SD0_EJECT_INT    (DB1200_INT_BEGIN + 13)
+#define DB1200_INT_END                  (DB1200_INT_BEGIN + 15)
+/* For drivers/pcmcia/au1000_db1x00.c */
+/* PCMCIA Db1x00 specific defines */
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+        ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+#define BOARD_PC0_INT DB1200_PC0_INT
+#define BOARD_PC1_INT DB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+#endif /* __ASM_DB1200_H */
diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h
index a326f451253b..6d37a5675803 100644
--- a/include/asm-mips/mach-dec/mc146818rtc.h
+++ b/include/asm-mips/mach-dec/mc146818rtc.h
@@ -3,7 +3,7 @@
 *
 * Copyright (C) 1998, 2001 by Ralf Baechle
 * Copyright (C) 1998 by Harald Koerfgen
- * Copyright (C) 2002  Maciej W. Rozycki
+ * Copyright (C) 2002, 2005  Maciej W. Rozycki
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
@@ -14,23 +14,18 @@
 #define __ASM_MIPS_DEC_RTC_DEC_H
 #include <linux/types.h>
 #include <asm/addrspace.h>
+#include <asm/dec/system.h>
 extern volatile u8 *dec_rtc_base;
-extern unsigned long dec_kn_slot_size;
-#define RTC_PORT(x)     CPHYSADDR(dec_rtc_base)
+#define RTC_PORT(x)     CPHYSADDR((long)dec_rtc_base)
 #define RTC_IO_EXTENT   dec_kn_slot_size
 #define RTC_IOMAPPED    0
 #undef RTC_IRQ
 #define RTC_DEC_YEAR    0x3f    /* Where we store the real year on DECs.  */
-#include <linux/mc146818rtc.h>
-#include <linux/module.h>
-#include <linux/types.h>
 static inline unsigned char CMOS_READ(unsigned long addr)
 {
        return dec_rtc_base[addr * 4];
diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/include/asm-mips/mach-generic/cpu-feature-overrides.h
index 0aecfd08e39a..7c185bb06f13 100644
--- a/include/asm-mips/mach-generic/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-generic/cpu-feature-overrides.h
@@ -8,6 +8,6 @@
 #ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
 #define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
-/* Intensionally empty file ...  */
+/* Intentionally empty file ...  */
 #endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index cb2edd018ad6..961006948c7c 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -18,6 +18,7 @@
 #include <linux/config.h>
 #include <linux/pci.h>
 #include <linux/stddef.h>
+#include <asm/processor.h>
 #ifndef MAX_HWIFS
 # ifdef CONFIG_BLK_DEV_IDEPCI
@@ -104,15 +105,71 @@ static __inline__ unsigned long ide_default_io_base(int index)
 /* MIPS port and memory-mapped I/O string operations.  */
-#define __ide_insw      insw
+static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
-#define __ide_insl      insl
+{
-#define __ide_outsw     outsw
+        if (cpu_has_dc_aliases) {
-#define __ide_outsl     outsl
+                unsigned long end = addr + size;
+                for (; addr < end; addr += PAGE_SIZE)
+                        flush_dcache_page(virt_to_page(addr));
+        }
+}
+static inline void __ide_insw(unsigned long port, void *addr,
+        unsigned int count)
+{
+        insw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+}
+static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
+{
+        insl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+}
+static inline void __ide_outsw(unsigned long port, const void *addr,
+        unsigned long count)
+{
+        outsw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+}
+static inline void __ide_outsl(unsigned long port, const void *addr,
+        unsigned long count)
+{
+        outsl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+}
+static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
+{
+        readsw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+}
+static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
+{
+        readsl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+}
+static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
+{
+        writesw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+}
+static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
+{
+        writesl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+}
-#define __ide_mm_insw   readsw
+/* ide_insw calls insw, not __ide_insw.  Why? */
-#define __ide_mm_insl   readsl
+#undef insw
-#define __ide_mm_outsw  writesw
+#undef insl
-#define __ide_mm_outsl  writesl
+#define insw(port, addr, count) __ide_insw(port, addr, count)
+#define insl(port, addr, count) __ide_insl(port, addr, count)
 #endif /* __KERNEL__ */
diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h
new file mode 100644
index 000000000000..9b64ff6e485d
--- /dev/null
+++ b/include/asm-mips/mach-generic/ioremap.h
@@ -0,0 +1,23 @@
+/*
+ *      include/asm-mips/mach-generic/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+#include <linux/types.h>
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/include/asm-mips/mach-generic/kernel-entry-init.h b/include/asm-mips/mach-generic/kernel-entry-init.h
new file mode 100644
index 000000000000..7e66505fa574
--- /dev/null
+++ b/include/asm-mips/mach-generic/kernel-entry-init.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+/* Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+.macro  kernel_entry_setup
+.endm
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
diff --git a/include/asm-mips/mach-generic/kmalloc.h b/include/asm-mips/mach-generic/kmalloc.h
new file mode 100644
index 000000000000..373d66dee9d7
--- /dev/null
+++ b/include/asm-mips/mach-generic/kmalloc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_MACH_GENERIC_KMALLOC_H
+#define __ASM_MACH_GENERIC_KMALLOC_H
+#include <linux/config.h>
+#ifndef CONFIG_DMA_COHERENT
+/*
+ * Total overkill for most systems but need as a safe default.
+ */
+#define ARCH_KMALLOC_MINALIGN   128
+#endif
+#endif /* __ASM_MACH_GENERIC_KMALLOC_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 5a2c1efb4eb7..b849d8dd7e78 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -55,13 +55,13 @@
 #endif
 #ifdef CONFIG_DMA_NONCOHERENT
-#define CAC_BASE                0x9800000000000000
+#define CAC_BASE                0x9800000000000000UL
 #else
-#define CAC_BASE                0xa800000000000000
+#define CAC_BASE                0xa800000000000000UL
 #endif
-#define IO_BASE                 0x9000000000000000
+#define IO_BASE                 0x9000000000000000UL
-#define UNCAC_BASE              0x9000000000000000
+#define UNCAC_BASE              0x9000000000000000UL
-#define MAP_BASE                0xc000000000000000
+#define MAP_BASE                0xc000000000000000UL
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
index 3c8896d9b133..ab9714668177 100644
--- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
@@ -11,6 +11,12 @@
 /*
 * IP22 with a variety of processors so we can't use defaults for everything.
 */
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4kcache         1
+#define cpu_has_fpu             1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
 #define cpu_has_mips16          0
 #define cpu_has_divec           0
 #define cpu_has_cache_cdex_p    1
@@ -23,6 +29,8 @@
 #define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
index e96166f27c49..8385f716798d 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -44,7 +44,7 @@
 #define CAC_BASE                0xffffffff80000000
 #define IO_BASE                 0xffffffffa0000000
 #define UNCAC_BASE              0xffffffffa0000000
-#define MAP_BASE                0xffffffffc0000000
+#define MAP_BASE                0xc000000000000000
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
index fe96d7358517..4c8a90051fd0 100644
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  1
 #define cpu_has_nofpuex         0
diff --git a/include/asm-mips/mach-ip27/kernel-entry-init.h b/include/asm-mips/mach-ip27/kernel-entry-init.h
new file mode 100644
index 000000000000..c1a10314b317
--- /dev/null
+++ b/include/asm-mips/mach-ip27/kernel-entry-init.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H
+#define __ASM_MACH_IP27_KERNEL_ENTRY_H
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn0/hubni.h>
+#include <asm/sn/klkernvars.h>
+/*
+ * Returns the local nasid into res.
+ */
+        .macro GET_NASID_ASM res
+        dli     \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
+        ld      \res, (\res)
+        and     \res, NSRI_NODEID_MASK
+        dsrl    \res, NSRI_NODEID_SHFT
+        .endm
+/*
+ * Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+        .macro  kernel_entry_setup
+        GET_NASID_ASM   t1
+        move            t2, t1                  # text and data are here
+        MAPPED_KERNEL_SETUP_TLB
+        .endm
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+        .macro  smp_slave_setup
+        GET_NASID_ASM   t1
+        dli     t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
+                    KLDIR_OFF_POINTER + CAC_BASE
+        dsll    t1, NASID_SHFT
+        or      t0, t0, t1
+        ld      t0, 0(t0)                       # t0 points to kern_vars struct
+        lh      t1, KV_RO_NASID_OFFSET(t0)
+        lh      t2, KV_RW_NASID_OFFSET(t0)
+        MAPPED_KERNEL_SETUP_TLB
+        ARC64_TWIDDLE_PC
+        .endm
+#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */
diff --git a/include/asm-mips/mach-ip27/kmalloc.h b/include/asm-mips/mach-ip27/kmalloc.h
new file mode 100644
index 000000000000..426bd049b2d7
--- /dev/null
+++ b/include/asm-mips/mach-ip27/kmalloc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_MACH_IP27_KMALLOC_H
+#define __ASM_MACH_IP27_KMALLOC_H
+/*
+ * All happy, no need to define ARCH_KMALLOC_MINALIGN
+ */
+#endif /* __ASM_MACH_IP27_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h
index d3f566362e9d..986a3b9b59a7 100644
--- a/include/asm-mips/mach-ip27/mmzone.h
+++ b/include/asm-mips/mach-ip27/mmzone.h
@@ -10,7 +10,6 @@
 #define LEVELS_PER_SLICE        128
 struct slice_data {
-        unsigned long irq_alloc_mask[2];
        unsigned long irq_enable_mask[2];
        int level_to_irq[LEVELS_PER_SLICE];
 };
@@ -20,6 +19,7 @@ struct hub_data {
        DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
        cpumask_t       h_cpus;
        unsigned long slice_map;
+        unsigned long irq_alloc_mask[2];
        struct slice_data slice[2];
 };
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
index e3b3fe32eeb1..45e61785ef42 100644
--- a/include/asm-mips/mach-ip27/spaces.h
+++ b/include/asm-mips/mach-ip27/spaces.h
@@ -20,6 +20,7 @@
 #define IO_BASE                 0x9200000000000000
 #define MSPEC_BASE              0x9400000000000000
 #define UNCAC_BASE              0x9600000000000000
+#define MAP_BASE                0xc000000000000000
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
index a70a81257c3d..82141c711c33 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -9,6 +9,9 @@
 #define parent_node(node)       (node)
 #define node_to_cpumask(node)   (hub_data(node)->h_cpus)
 #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
+struct pci_bus;
+extern int pcibus_to_node(struct pci_bus *);
 #define pcibus_to_cpumask(bus)  (cpu_online_map)
 extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
index 04713973c6c3..ab37fc1842ba 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -37,5 +37,6 @@
 #define cpu_has_ejtag           0
 #define cpu_has_vtag_icache     0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h
new file mode 100644
index 000000000000..9d2d4d9ac036
--- /dev/null
+++ b/include/asm-mips/mach-ip32/kmalloc.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_MACH_IP32_KMALLOC_H
+#define __ASM_MACH_IP32_KMALLOC_H
+#include <linux/config.h>
+#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000)
+#define ARCH_KMALLOC_MINALIGN   32
+#else
+#define ARCH_KMALLOC_MINALIGN   128
+#endif
+#endif /* __ASM_MACH_IP32_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h
index c7839f85c68d..44abe5c02389 100644
--- a/include/asm-mips/mach-ip32/spaces.h
+++ b/include/asm-mips/mach-ip32/spaces.h
@@ -19,10 +19,10 @@
 #define HIGHMEM_START           (1UL << 59UL)
 #endif
-#define CAC_BASE                0x9800000000000000
+#define CAC_BASE                0x9800000000000000UL
-#define IO_BASE                 0x9000000000000000
+#define IO_BASE                 0x9000000000000000UL
-#define UNCAC_BASE              0x9000000000000000
+#define UNCAC_BASE              0x9000000000000000UL
-#define MAP_BASE                0xc000000000000000
+#define MAP_BASE                0xc000000000000000UL
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h
index ca57e7db98bb..a0fde405d4c4 100644
--- a/include/asm-mips/mach-ja/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  0
 #define cpu_has_nofpuex         0
@@ -36,10 +37,4 @@
 #define cpu_icache_line_size()  32
 #define cpu_scache_line_size()  32
-/*
- * On the RM9000 we need to ensure that I-cache lines being fetches only
- * contain valid instructions are funny things will happen.
- */
-#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h
index 6f51be571bf0..9f92aed17754 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h
@@ -17,7 +17,7 @@
 #ifdef CONFIG_CPU_MIPS32
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
-#define cpu_has_4ktlb           1
+#define cpu_has_4kcache         1
 /* #define cpu_has_fpu          ? */
 /* #define cpu_has_32fpr        ? */
 #define cpu_has_counter         1
@@ -37,12 +37,13 @@
 /* #define cpu_has_64bits       ? */
 /* #define cpu_has_64bit_zero_reg ? */
 /* #define cpu_has_subset_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
 #endif
 #ifdef CONFIG_CPU_MIPS64
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
-#define cpu_has_4ktlb           1
+#define cpu_has_4kcache         1
 /* #define cpu_has_fpu          ? */
 /* #define cpu_has_32fpr        ? */
 #define cpu_has_counter         1
@@ -62,6 +63,7 @@
 /* #define cpu_has_64bits       ? */
 /* #define cpu_has_64bit_zero_reg ? */
 /* #define cpu_has_subset_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
 #endif
 #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-mips/irq.h
new file mode 100644
index 000000000000..f8579696ca54
--- /dev/null
+++ b/include/asm-mips/mach-mips/irq.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_MACH_MIPS_IRQ_H
+#define __ASM_MACH_MIPS_IRQ_H
+#include <linux/config.h>
+#define NR_IRQS 256
+#ifdef CONFIG_SMP
+#define ARCH_HAS_IRQ_PER_CPU
+#endif
+#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
index 7473512384bc..825c5f674dfc 100644
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -28,6 +28,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  0
 #define cpu_has_nofpuex         0
@@ -39,10 +40,4 @@
 #define cpu_icache_line_size()  32
 #define cpu_scache_line_size()  32
-/*
- * On the RM9000 we need to ensure that I-cache lines being fetches only
- * contain valid instructions are funny things will happen.
- */
-#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
new file mode 100644
index 000000000000..9a3088b19bf3
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -0,0 +1,252 @@
+/*
+ * AMD Alchemy PB1200 Referrence Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1200_H
+#define __ASM_PB1200_H
+#include <linux/types.h>
+// This is defined in au1000.h with bogus value
+#undef AU1X00_EXTERNAL_INT
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+/* SPI and SMB are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
+/* AC97 and I2S are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE            PSC1_BASE_ADDR
+#define BCSR_KSEG1_ADDR 0xAD800000
+typedef volatile struct
+{
+        /*00*/  u16 whoami;
+                u16 reserved0;
+        /*04*/  u16 status;
+                u16 reserved1;
+        /*08*/  u16 switches;
+                u16 reserved2;
+        /*0C*/  u16 resets;
+                u16 reserved3;
+        /*10*/  u16 pcmcia;
+                u16 reserved4;
+        /*14*/  u16 board;
+                u16 reserved5;
+        /*18*/  u16 disk_leds;
+                u16 reserved6;
+        /*1C*/  u16 system;
+                u16 reserved7;
+        /*20*/  u16 intclr;
+                u16 reserved8;
+        /*24*/  u16 intset;
+                u16 reserved9;
+        /*28*/  u16 intclr_mask;
+                u16 reserved10;
+        /*2C*/  u16 intset_mask;
+                u16 reserved11;
+        /*30*/  u16 sig_status;
+                u16 reserved12;
+        /*34*/  u16 int_status;
+                u16 reserved13;
+        /*38*/  u16 reserved14;
+                u16 reserved15;
+        /*3C*/  u16 reserved16;
+                u16 reserved17;
+} BCSR;
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID        0x000F
+#define BCSR_WHOAMI_CPLD        0x00F0
+#define BCSR_WHOAMI_BOARD       0x0F00
+#define BCSR_STATUS_PCMCIA0VS   0x0003
+#define BCSR_STATUS_PCMCIA1VS   0x000C
+#define BCSR_STATUS_SWAPBOOT    0x0040
+#define BCSR_STATUS_FLASHBUSY   0x0100
+#define BCSR_STATUS_IDECBLID    0x0200
+#define BCSR_STATUS_SD0WP               0x0400
+#define BCSR_STATUS_SD1WP               0x0800
+#define BCSR_STATUS_U0RXD               0x1000
+#define BCSR_STATUS_U1RXD               0x2000
+#define BCSR_SWITCHES_OCTAL     0x00FF
+#define BCSR_SWITCHES_DIP_1     0x0080
+#define BCSR_SWITCHES_DIP_2     0x0040
+#define BCSR_SWITCHES_DIP_3     0x0020
+#define BCSR_SWITCHES_DIP_4     0x0010
+#define BCSR_SWITCHES_DIP_5     0x0008
+#define BCSR_SWITCHES_DIP_6     0x0004
+#define BCSR_SWITCHES_DIP_7     0x0002
+#define BCSR_SWITCHES_DIP_8     0x0001
+#define BCSR_SWITCHES_ROTARY    0x0F00
+#define BCSR_RESETS_ETH         0x0001
+#define BCSR_RESETS_CAMERA      0x0002
+#define BCSR_RESETS_DC          0x0004
+#define BCSR_RESETS_IDE         0x0008
+/* not resets but in the same register */
+#define BCSR_RESETS_WSCFSM  0x0800
+#define BCSR_RESETS_PCS0MUX     0x1000
+#define BCSR_RESETS_PCS1MUX     0x2000
+#define BCSR_RESETS_SPISEL      0x4000
+#define BCSR_RESETS_SD1MUX  0x8000
+#define BCSR_PCMCIA_PC0VPP      0x0003
+#define BCSR_PCMCIA_PC0VCC      0x000C
+#define BCSR_PCMCIA_PC0DRVEN    0x0010
+#define BCSR_PCMCIA_PC0RST      0x0080
+#define BCSR_PCMCIA_PC1VPP      0x0300
+#define BCSR_PCMCIA_PC1VCC      0x0C00
+#define BCSR_PCMCIA_PC1DRVEN    0x1000
+#define BCSR_PCMCIA_PC1RST      0x8000
+#define BCSR_BOARD_LCDVEE       0x0001
+#define BCSR_BOARD_LCDVDD       0x0002
+#define BCSR_BOARD_LCDBL        0x0004
+#define BCSR_BOARD_CAMSNAP      0x0010
+#define BCSR_BOARD_CAMPWR       0x0020
+#define BCSR_BOARD_SD0PWR       0x0040
+#define BCSR_BOARD_SD1PWR       0x0080
+#define BCSR_LEDS_DECIMALS      0x00FF
+#define BCSR_LEDS_LED0          0x0100
+#define BCSR_LEDS_LED1          0x0200
+#define BCSR_LEDS_LED2          0x0400
+#define BCSR_LEDS_LED3          0x0800
+#define BCSR_SYSTEM_VDDI        0x001F
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE            0x0001
+#define BCSR_INT_ETH            0x0002
+#define BCSR_INT_PC0            0x0004
+#define BCSR_INT_PC0STSCHG      0x0008
+#define BCSR_INT_PC1            0x0010
+#define BCSR_INT_PC1STSCHG      0x0020
+#define BCSR_INT_DC                     0x0040
+#define BCSR_INT_FLASHBUSY      0x0080
+#define BCSR_INT_PC0INSERT      0x0100
+#define BCSR_INT_PC0EJECT       0x0200
+#define BCSR_INT_PC1INSERT      0x0400
+#define BCSR_INT_PC1EJECT       0x0800
+#define BCSR_INT_SD0INSERT      0x1000
+#define BCSR_INT_SD0EJECT       0x2000
+#define BCSR_INT_SD1INSERT      0x4000
+#define BCSR_INT_SD1EJECT       0x8000
+/* PCMCIA Db1x00 specific defines */
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+        ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+#define AU1XXX_SMC91111_PHYS_ADDR       (0x0D000300)
+#define AU1XXX_SMC91111_IRQ                     PB1200_ETH_INT
+#define AU1XXX_ATA_PHYS_ADDR            (0x0C800000)
+#define AU1XXX_ATA_PHYS_LEN                     (0x100)
+#define AU1XXX_ATA_REG_OFFSET   (5)
+#define AU1XXX_ATA_INT                  PB1200_IDE_INT
+#define AU1XXX_ATA_DDMA_REQ             DSCR_CMD0_DMA_REQ1;
+#define AU1XXX_ATA_RQSIZE               128
+#define NAND_PHYS_ADDR   0x1C000000
+/* Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1200 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                        (18 >> 2)
+#define NAND_T_PUL                      (30 >> 2)
+#define NAND_T_SU                       (30 >> 2)
+#define NAND_T_WH                       (30 >> 2)
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+#define NAND_TIMING     ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
+                        ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
+                        ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
+                        ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+/*
+ *      External Interrupts for Pb1200 as of 8/6/2004.
+ *   Bit positions in the CPLD registers can be calculated by taking
+ *   the interrupt define and subtracting the PB1200_INT_BEGIN value.
+ *    *example: IDE bis pos is  = 64 - 64
+                ETH bit pos is  = 65 - 64
+ */
+#define PB1200_INT_BEGIN                (AU1000_LAST_INTC1_INT + 1)
+#define PB1200_IDE_INT                  (PB1200_INT_BEGIN + 0)
+#define PB1200_ETH_INT                  (PB1200_INT_BEGIN + 1)
+#define PB1200_PC0_INT                  (PB1200_INT_BEGIN + 2)
+#define PB1200_PC0_STSCHG_INT   (PB1200_INT_BEGIN + 3)
+#define PB1200_PC1_INT                  (PB1200_INT_BEGIN + 4)
+#define PB1200_PC1_STSCHG_INT   (PB1200_INT_BEGIN + 5)
+#define PB1200_DC_INT                   (PB1200_INT_BEGIN + 6)
+#define PB1200_FLASHBUSY_INT    (PB1200_INT_BEGIN + 7)
+#define PB1200_PC0_INSERT_INT   (PB1200_INT_BEGIN + 8)
+#define PB1200_PC0_EJECT_INT    (PB1200_INT_BEGIN + 9)
+#define PB1200_PC1_INSERT_INT   (PB1200_INT_BEGIN + 10)
+#define PB1200_PC1_EJECT_INT    (PB1200_INT_BEGIN + 11)
+#define PB1200_SD0_INSERT_INT   (PB1200_INT_BEGIN + 12)
+#define PB1200_SD0_EJECT_INT    (PB1200_INT_BEGIN + 13)
+#define PB1200_SD1_INSERT_INT   (PB1200_INT_BEGIN + 14)
+#define PB1200_SD1_EJECT_INT    (PB1200_INT_BEGIN + 15)
+#define PB1200_INT_END                  (PB1200_INT_BEGIN + 15)
+/* For drivers/pcmcia/au1000_db1x00.c */
+#define BOARD_PC0_INT PB1200_PC0_INT
+#define BOARD_PC1_INT PB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+#endif /* __ASM_PB1200_H */
diff --git a/include/asm-mips/mach-pnx8550/cm.h b/include/asm-mips/mach-pnx8550/cm.h
new file mode 100644
index 000000000000..bb0a56c7d011
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/cm.h
@@ -0,0 +1,43 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   Clock module specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef __PNX8550_CM_H
+#define __PNX8550_CM_H
+#define PNX8550_CM_BASE 0xBBE47000
+#define PNX8550_CM_PLL0_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
+#define PNX8550_CM_PLL1_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
+#define PNX8550_CM_PLL2_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
+#define PNX8550_CM_PLL3_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
+// Table not complete.....
+#define PNX8550_CM_PLL_BLOCKED_MASK     0x80000000
+#define PNX8550_CM_PLL_LOCK_MASK        0x40000000
+#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
+#define PNX8550_CM_PLL_N_MASK           0x01ff0000
+#define PNX8550_CM_PLL_M_MASK           0x00003f00
+#define PNX8550_CM_PLL_P_MASK           0x0000000c
+#define PNX8550_CM_PLL_PD_MASK          0x00000002
+#endif
diff --git a/include/asm-mips/mach-pnx8550/glb.h b/include/asm-mips/mach-pnx8550/glb.h
new file mode 100644
index 000000000000..07aa85e609bc
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/glb.h
@@ -0,0 +1,86 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   PNX8550 global definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef __PNX8550_GLB_H
+#define __PNX8550_GLB_H
+#define PNX8550_GLB1_BASE       0xBBE63000
+#define PNX8550_GLB2_BASE       0xBBE4d000
+#define PNX8550_RESET_BASE      0xBBE60000
+/* PCI Inta Output Enable Registers */
+#define PNX8550_GLB2_ENAB_INTA_O        *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
+/* Bit 1:Enable DAC Powerdown
+     0:DACs are enabled and are working normally
+     1:DACs are powerdown
+*/
+#define PNX8550_GLB_DAC_PD      0x2
+/*   Bit 0:Enable of PCI inta output
+     0 = Disable PCI inta output
+     1 = Enable PCI inta output
+*/
+#define PNX8550_GLB_ENABLE_INTA_O 0x1
+/* PCI Direct Mappings */
+#define PNX8550_PCIMEM          0x12000000
+#define PNX8550_PCIMEM_SIZE     0x08000000
+#define PNX8550_PCIIO           0x1c000000
+#define PNX8550_PCIIO_SIZE      0x02000000      /* 32M */
+#define PNX8550_PORT_BASE       KSEG1
+// GPIO def
+#define PNX8550_GPIO_BASE       0x1Be00000
+#define PNX8550_GPIO_DIRQ0       (PNX8550_GPIO_BASE + 0x104500)
+#define PNX8550_GPIO_MC1         (PNX8550_GPIO_BASE + 0x104004)
+#define PNX8550_GPIO_MC_31_BIT   30
+#define PNX8550_GPIO_MC_30_BIT   28
+#define PNX8550_GPIO_MC_29_BIT   26
+#define PNX8550_GPIO_MC_28_BIT   24
+#define PNX8550_GPIO_MC_27_BIT   22
+#define PNX8550_GPIO_MC_26_BIT   20
+#define PNX8550_GPIO_MC_25_BIT   18
+#define PNX8550_GPIO_MC_24_BIT   16
+#define PNX8550_GPIO_MC_23_BIT   14
+#define PNX8550_GPIO_MC_22_BIT   12
+#define PNX8550_GPIO_MC_21_BIT   10
+#define PNX8550_GPIO_MC_20_BIT   8
+#define PNX8550_GPIO_MC_19_BIT   6
+#define PNX8550_GPIO_MC_18_BIT   4
+#define PNX8550_GPIO_MC_17_BIT   2
+#define PNX8550_GPIO_MC_16_BIT   0
+#define PNX8550_GPIO_MODE_PRIMOP    0x1
+#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
+#define PNX8550_GPIO_MODE_OPENDR    0x3
+// RESET module
+#define PNX8550_RST_CTL             *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
+#define PNX8550_RST_CAUSE           *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
+#define PNX8550_RST_EN_WATCHDOG     *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
+#define PNX8550_RST_REL_MIPS_RST_N     0x8
+#define PNX8550_RST_DO_SW_RST          0x4
+#define PNX8550_RST_REL_SYS_RST_OUT    0x2
+#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
+#endif
diff --git a/include/asm-mips/mach-pnx8550/int.h b/include/asm-mips/mach-pnx8550/int.h
new file mode 100644
index 000000000000..0e0668b524f4
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/int.h
@@ -0,0 +1,140 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   Interrupt specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef __PNX8550_INT_H
+#define __PNX8550_INT_H
+#define PNX8550_GIC_BASE        0xBBE3E000
+#define PNX8550_GIC_PRIMASK_0   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
+#define PNX8550_GIC_PRIMASK_1   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
+#define PNX8550_GIC_VECTOR_0    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
+#define PNX8550_GIC_VECTOR_1    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
+#define PNX8550_GIC_PEND_1_31   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
+#define PNX8550_GIC_PEND_32_63  *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
+#define PNX8550_GIC_PEND_64_70  *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
+#define PNX8550_GIC_FEATURES    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
+#define PNX8550_GIC_REQ(x)      *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
+#define PNX8550_GIC_MOD_ID      *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
+// cp0 is two software + six hw exceptions
+#define PNX8550_INT_CP0_TOTINT  8
+#define PNX8550_INT_CP0_MIN     0
+#define PNX8550_INT_CP0_MAX     (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
+#define MIPS_CPU_GIC_IRQ        2
+#define MIPS_CPU_TIMER_IRQ      7
+// GIC are 71 exceptions connected to cp0's first hardware exception
+#define PNX8550_INT_GIC_TOTINT  71
+#define PNX8550_INT_GIC_MIN     (PNX8550_INT_CP0_MAX+1)
+#define PNX8550_INT_GIC_MAX     (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
+#define PNX8550_INT_UNDEF              (PNX8550_INT_GIC_MIN+0)
+#define PNX8550_INT_IPC_TARGET0_MIPS   (PNX8550_INT_GIC_MIN+1)
+#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
+#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
+#define PNX8550_INT_RESERVED_4         (PNX8550_INT_GIC_MIN+4)
+#define PNX8550_INT_USB                (PNX8550_INT_GIC_MIN+5)
+#define PNX8550_INT_GPIO_EQ1           (PNX8550_INT_GIC_MIN+6)
+#define PNX8550_INT_GPIO_EQ2           (PNX8550_INT_GIC_MIN+7)
+#define PNX8550_INT_GPIO_EQ3           (PNX8550_INT_GIC_MIN+8)
+#define PNX8550_INT_GPIO_EQ4           (PNX8550_INT_GIC_MIN+9)
+#define PNX8550_INT_GPIO_EQ5           (PNX8550_INT_GIC_MIN+10)
+#define PNX8550_INT_GPIO_EQ6           (PNX8550_INT_GIC_MIN+11)
+#define PNX8550_INT_RESERVED_12        (PNX8550_INT_GIC_MIN+12)
+#define PNX8550_INT_QVCP1              (PNX8550_INT_GIC_MIN+13)
+#define PNX8550_INT_QVCP2              (PNX8550_INT_GIC_MIN+14)
+#define PNX8550_INT_I2C1               (PNX8550_INT_GIC_MIN+15)
+#define PNX8550_INT_I2C2               (PNX8550_INT_GIC_MIN+16)
+#define PNX8550_INT_ISO_UART1          (PNX8550_INT_GIC_MIN+17)
+#define PNX8550_INT_ISO_UART2          (PNX8550_INT_GIC_MIN+18)
+#define PNX8550_INT_UART1              (PNX8550_INT_GIC_MIN+19)
+#define PNX8550_INT_UART2              (PNX8550_INT_GIC_MIN+20)
+#define PNX8550_INT_QNTR               (PNX8550_INT_GIC_MIN+21)
+#define PNX8550_INT_RESERVED22         (PNX8550_INT_GIC_MIN+22)
+#define PNX8550_INT_T_DSC              (PNX8550_INT_GIC_MIN+23)
+#define PNX8550_INT_M_DSC              (PNX8550_INT_GIC_MIN+24)
+#define PNX8550_INT_RESERVED25         (PNX8550_INT_GIC_MIN+25)
+#define PNX8550_INT_2D_DRAW_ENG        (PNX8550_INT_GIC_MIN+26)
+#define PNX8550_INT_MEM_BASED_SCALAR1  (PNX8550_INT_GIC_MIN+27)
+#define PNX8550_INT_VIDEO_MPEG         (PNX8550_INT_GIC_MIN+28)
+#define PNX8550_INT_VIDEO_INPUT_P1     (PNX8550_INT_GIC_MIN+29)
+#define PNX8550_INT_VIDEO_INPUT_P2     (PNX8550_INT_GIC_MIN+30)
+#define PNX8550_INT_SPDI1              (PNX8550_INT_GIC_MIN+31)
+#define PNX8550_INT_SPDO               (PNX8550_INT_GIC_MIN+32)
+#define PNX8550_INT_AUDIO_INPUT1       (PNX8550_INT_GIC_MIN+33)
+#define PNX8550_INT_AUDIO_OUTPUT1      (PNX8550_INT_GIC_MIN+34)
+#define PNX8550_INT_AUDIO_INPUT2       (PNX8550_INT_GIC_MIN+35)
+#define PNX8550_INT_AUDIO_OUTPUT2      (PNX8550_INT_GIC_MIN+36)
+#define PNX8550_INT_MEMBASED_SCALAR2   (PNX8550_INT_GIC_MIN+37)
+#define PNX8550_INT_VPK                (PNX8550_INT_GIC_MIN+38)
+#define PNX8550_INT_MPEG1_MIPS         (PNX8550_INT_GIC_MIN+39)
+#define PNX8550_INT_MPEG1_TM           (PNX8550_INT_GIC_MIN+40)
+#define PNX8550_INT_MPEG2_MIPS         (PNX8550_INT_GIC_MIN+41)
+#define PNX8550_INT_MPEG2_TM           (PNX8550_INT_GIC_MIN+42)
+#define PNX8550_INT_TS_DMA             (PNX8550_INT_GIC_MIN+43)
+#define PNX8550_INT_EDMA               (PNX8550_INT_GIC_MIN+44)
+#define PNX8550_INT_TM_DEBUG1          (PNX8550_INT_GIC_MIN+45)
+#define PNX8550_INT_TM_DEBUG2          (PNX8550_INT_GIC_MIN+46)
+#define PNX8550_INT_PCI_INTA           (PNX8550_INT_GIC_MIN+47)
+#define PNX8550_INT_CLOCK_MODULE       (PNX8550_INT_GIC_MIN+48)
+#define PNX8550_INT_PCI_XIO_INTA_PCI   (PNX8550_INT_GIC_MIN+49)
+#define PNX8550_INT_PCI_XIO_INTB_DMA   (PNX8550_INT_GIC_MIN+50)
+#define PNX8550_INT_PCI_XIO_INTC_GPPM  (PNX8550_INT_GIC_MIN+51)
+#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
+#define PNX8550_INT_DVD_CSS            (PNX8550_INT_GIC_MIN+53)
+#define PNX8550_INT_VLD                (PNX8550_INT_GIC_MIN+54)
+#define PNX8550_INT_GPIO_TSU_7_0       (PNX8550_INT_GIC_MIN+55)
+#define PNX8550_INT_GPIO_TSU_15_8      (PNX8550_INT_GIC_MIN+56)
+#define PNX8550_INT_GPIO_CTU_IR        (PNX8550_INT_GIC_MIN+57)
+#define PNX8550_INT_GPIO0              (PNX8550_INT_GIC_MIN+58)
+#define PNX8550_INT_GPIO1              (PNX8550_INT_GIC_MIN+59)
+#define PNX8550_INT_GPIO2              (PNX8550_INT_GIC_MIN+60)
+#define PNX8550_INT_GPIO3              (PNX8550_INT_GIC_MIN+61)
+#define PNX8550_INT_GPIO4              (PNX8550_INT_GIC_MIN+62)
+#define PNX8550_INT_GPIO5              (PNX8550_INT_GIC_MIN+63)
+#define PNX8550_INT_GPIO6              (PNX8550_INT_GIC_MIN+64)
+#define PNX8550_INT_GPIO7              (PNX8550_INT_GIC_MIN+65)
+#define PNX8550_INT_PMAN_SECURITY      (PNX8550_INT_GIC_MIN+66)
+#define PNX8550_INT_I2C3               (PNX8550_INT_GIC_MIN+67)
+#define PNX8550_INT_RESERVED_68        (PNX8550_INT_GIC_MIN+68)
+#define PNX8550_INT_SPDI2              (PNX8550_INT_GIC_MIN+69)
+#define PNX8550_INT_I2C4               (PNX8550_INT_GIC_MIN+70)
+// Timer are 3 exceptions connected to cp0's 7th hardware exception
+#define PNX8550_INT_TIMER_TOTINT       3
+#define PNX8550_INT_TIMER_MIN          (PNX8550_INT_GIC_MAX+1)
+#define PNX8550_INT_TIMER_MAX          (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
+#define PNX8550_INT_TIMER1             (PNX8550_INT_TIMER_MIN+0)
+#define PNX8550_INT_TIMER2             (PNX8550_INT_TIMER_MIN+1)
+#define PNX8550_INT_TIMER3             (PNX8550_INT_TIMER_MIN+2)
+#define PNX8550_INT_WATCHDOG           PNX8550_INT_TIMER3
+#endif
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
new file mode 100644
index 000000000000..57102fa9da51
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -0,0 +1,262 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ */
+#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_KERNEL_ENTRY_INIT_H
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+#define CO_CONFIGPR_VALID  0x3F1F41FF    /* valid bits to write to ConfigPR */
+#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
+#define CACHE_OPC      0xBC000000  /* MIPS cache instruction opcode */
+#define ICACHE_LINE_SIZE        32      /* Instruction cache line size bytes */
+#define DCACHE_LINE_SIZE        32      /* Data cache line size in bytes */
+#define ICACHE_SET_COUNT        256     /* Instruction cache set count */
+#define DCACHE_SET_COUNT        128     /* Data cache set count */
+#define ICACHE_SET_SIZE         (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
+#define DCACHE_SET_SIZE         (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
+        .macro  kernel_entry_setup
+        .set    push
+        .set    noreorder
+        /*
+         * PNX8550 entry point, when running a non compressed
+         * kernel. When loading a zImage, the head.S code in
+         * arch/mips/zboot/pnx8550 will init the caches and,
+         * decompress the kernel, and branch to kernel_entry.
+                 */
+cache_begin:    li      t0, (1<<28)
+        mtc0    t0, CP0_STATUS /* cp0 usable */
+        HAZARD_CP0
+        mtc0    zero, CP0_CAUSE
+        HAZARD_CP0
+        /* Set static virtual to phys address translation and TLB disabled */
+        mfc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+        and t0,~((1<<19) | (1<<20))     /* TLB/MAP cleared */
+        mtc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+        /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
+        init_icache
+        nop
+        init_dcache
+        nop
+        cachePr4450ICReset
+        nop
+        cachePr4450DCReset
+        nop
+        /* read ConfigPR into t0 */
+        mfc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+        /*  enable the TLB */
+        or      t0, (1<<19)
+        /* disable the ICACHE: at least 10x slower */
+        /* or      t0, (1<<26) */
+        /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set  */
+        /* or      t0, (1<<27) */
+        and     t0, CO_CONFIGPR_VALID
+        /* enable TLB. */
+        mtc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+cache_end:
+        /* Setup CMEM_0 to MMIO address space, 2MB */
+        lui    t0, 0x1BE0
+        addi   t0, t0, 0x3
+        mtc0   $8, $22, 4
+        nop
+        /* Setup CMEM_1, 128MB */
+        lui    t0, 0x1000
+        addi   t0, t0, 0xf
+        mtc0   $8, $22, 5
+        nop
+        /* Setup CMEM_2, 32MB */
+        lui    t0, 0x1C00
+        addi   t0, t0, 0xb
+        mtc0   $8, $22, 6
+        nop
+        /* Setup CMEM_3, 0MB */
+        lui    t0, 0x0
+        addi   t0, t0, 0x0
+        mtc0   $8, $22, 7
+        nop
+        /* Enable cache */
+        mfc0    t0, CP0_CONFIG
+        HAZARD_CP0
+        and     t0, t0, 0xFFFFFFF8
+        or      t0, t0, 3
+        mtc0    t0, CP0_CONFIG
+        HAZARD_CP0
+        .set    pop
+        .endm
+        .macro  init_icache
+        .set    push
+        .set    noreorder
+        /* Get Cache Configuration */
+        mfc0    t3, CP0_CONFIG, 1
+        HAZARD_CP0
+        /* get cache Line size */
+        srl   t1, t3, 19   /* C0_CONFIGPR_IL_SHIFT */
+        andi  t1, t1, 0x7  /* C0_CONFIGPR_IL_MASK */
+        beq   t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
+        nop
+        addiu t0, t1, 1
+        ori   t1, zero, 1
+        sllv  t1, t1, t0
+        /* get max cache Index */
+        srl   t2, t3, 22  /* C0_CONFIGPR_IS_SHIFT */
+        andi  t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
+        addiu t0, t2, 6
+        ori   t2, zero, 1
+        sllv  t2, t2, t0
+        /* get max cache way */
+        srl   t3, t3, 16  /* C0_CONFIGPR_IA_SHIFT */
+        andi  t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
+        addiu t3, t3, 1
+        /* total no of cache lines */
+        multu t2, t3             /* max index * max way */
+        mflo  t2
+        addiu t2, t2, -1
+        move  t0, zero
+pr4450_next_instruction_cache_set:
+        cache  Index_Invalidate_I, 0(t0)
+        addu  t0, t0, t1         /* add bytes in a line */
+        bne   t2, zero, pr4450_next_instruction_cache_set
+        addiu t2, t2, -1   /* reduce no of lines to invalidate by one */
+pr4450_instr_cache_invalidated:
+        .set    pop
+        .endm
+        .macro  init_dcache
+        .set    push
+        .set    noreorder
+        move t1, zero
+        /* Store Tag Information */
+        mtc0    zero, CP0_TAGLO, 0
+        HAZARD_CP0
+        mtc0    zero, CP0_TAGHI, 0
+        HAZARD_CP0
+        /* Cache size is 16384 = 512 lines x 32 bytes per line */
+        or       t2, zero, (128*4)-1  /* 512 lines  */
+        /* Invalidate all lines */
+2:
+        cache Index_Store_Tag_D, 0(t1)
+        addiu    t2, t2, -1
+        bne      t2, zero, 2b
+        addiu    t1, t1, 32        /* 32 bytes in a line */
+        .set pop
+        .endm
+        .macro  cachePr4450ICReset
+        .set    push
+        .set    noreorder
+        /* Save CP0 status reg on entry; */
+        /* disable interrupts during cache reset */
+        mfc0    t0, CP0_STATUS      /* T0 = interrupt status on entry */
+        HAZARD_CP0
+        mtc0    zero, CP0_STATUS   /* disable CPU interrupts */
+        HAZARD_CP0
+        or      t1, zero, zero              /* T1 = starting cache index (0) */
+        ori     t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
+        icache_invd_loop:
+        /* 9 == register t1 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
+                (0 * ICACHE_SET_SIZE))  /* invalidate inst cache WAY0 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
+                (1 * ICACHE_SET_SIZE))  /* invalidate inst cache WAY1 */
+        addiu   t1, t1, ICACHE_LINE_SIZE    /* T1 = next cache line index */
+        bne     t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
+        addiu   t2, t2, -1        /* decrement T2 set cnt (delay slot) */
+        /* Initialize the latches in the instruction cache tag */
+        /* that drive the way selection tri-state bus drivers, by doing a */
+        /* dummy load while the instruction cache is still disabled. */
+        /* TODO: Is this needed ? */
+        la      t1, KSEG0            /* T1 = cached memory base address */
+        lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
+        mtc0    t0, CP0_STATUS        /* restore interrupt status on entry */
+        HAZARD_CP0
+        .set    pop
+        .endm
+        .macro  cachePr4450DCReset
+        .set    push
+        .set    noreorder
+        mfc0    t0, CP0_STATUS           /* T0 = interrupt status on entry */
+        HAZARD_CP0
+        mtc0    zero, CP0_STATUS         /* disable CPU interrupts */
+        HAZARD_CP0
+        /* Writeback/invalidate entire data cache sets/ways/lines */
+        or      t1, zero, zero              /* T1 = starting cache index (0) */
+        ori     t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
+        dcache_wbinvd_loop:
+        /* 9 == register t1 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (0 * DCACHE_SET_SIZE))  /* writeback/invalidate WAY0 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (1 * DCACHE_SET_SIZE))  /* writeback/invalidate WAY1 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (2 * DCACHE_SET_SIZE))  /* writeback/invalidate WAY2 */
+        .word   (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (3 * DCACHE_SET_SIZE))  /* writeback/invalidate WAY3 */
+        addiu   t1, t1, DCACHE_LINE_SIZE  /* T1 = next data cache line index */
+        bne     t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
+        addiu   t2, t2, -1          /* decrement T2 set cnt (delay slot) */
+        /* Initialize the latches in the data cache tag that drive the way
+        selection tri-state bus drivers, by doing a dummy load while the
+        data cache is still in the disabled mode.  TODO: Is this needed ? */
+        la      t1, KSEG0            /* T1 = cached memory base address */
+        lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
+        mtc0    t0, CP0_STATUS       /* restore interrupt status on entry */
+        HAZARD_CP0
+        .set    pop
+        .endm
+#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-pnx8550/nand.h b/include/asm-mips/mach-pnx8550/nand.h
new file mode 100644
index 000000000000..aefbc514ab09
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/nand.h
@@ -0,0 +1,121 @@
+#ifndef __PNX8550_NAND_H
+#define __PNX8550_NAND_H
+#define PNX8550_NAND_BASE_ADDR   0x10000000
+#define PNX8550_PCIXIO_BASE      0xBBE40000
+#define PNX8550_DMA_EXT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
+#define PNX8550_DMA_INT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
+#define PNX8550_DMA_TRANS_SIZE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
+#define PNX8550_DMA_CTRL         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
+#define PNX8550_XIO_SEL0         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
+#define PNX8550_GPXIO_ADDR       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
+#define PNX8550_GPXIO_WR         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
+#define PNX8550_GPXIO_RD         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
+#define PNX8550_GPXIO_CTRL       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
+#define PNX8550_XIO_FLASH_CTRL   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
+#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
+#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
+#define PNX8550_GPXIO_INT_CLEAR  *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
+#define PNX8550_DMA_INT_STATUS   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
+#define PNX8550_DMA_INT_ENABLE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
+#define PNX8550_DMA_INT_CLEAR    *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
+#define PNX8550_XIO_SEL0_EN_16BIT    0x00800000
+#define PNX8550_XIO_SEL0_USE_ACK     0x00400000
+#define PNX8550_XIO_SEL0_REN_HIGH    0x00100000
+#define PNX8550_XIO_SEL0_REN_LOW     0x00040000
+#define PNX8550_XIO_SEL0_WEN_HIGH    0x00010000
+#define PNX8550_XIO_SEL0_WEN_LOW     0x00004000
+#define PNX8550_XIO_SEL0_WAIT        0x00000200
+#define PNX8550_XIO_SEL0_OFFSET      0x00000020
+#define PNX8550_XIO_SEL0_TYPE_68360  0x00000000
+#define PNX8550_XIO_SEL0_TYPE_NOR    0x00000008
+#define PNX8550_XIO_SEL0_TYPE_NAND   0x00000010
+#define PNX8550_XIO_SEL0_TYPE_IDE    0x00000018
+#define PNX8550_XIO_SEL0_SIZE_8MB    0x00000000
+#define PNX8550_XIO_SEL0_SIZE_16MB   0x00000002
+#define PNX8550_XIO_SEL0_SIZE_32MB   0x00000004
+#define PNX8550_XIO_SEL0_SIZE_64MB   0x00000006
+#define PNX8550_XIO_SEL0_ENAB        0x00000001
+#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT)  | \
+                              (PNX8550_XIO_SEL0_REN_HIGH*0)| \
+                              (PNX8550_XIO_SEL0_REN_LOW*2) | \
+                              (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
+                              (PNX8550_XIO_SEL0_WEN_LOW*2) | \
+                              (PNX8550_XIO_SEL0_WAIT*4)    | \
+                              (PNX8550_XIO_SEL0_OFFSET*0)  | \
+                              (PNX8550_XIO_SEL0_TYPE_NAND) | \
+                              (PNX8550_XIO_SEL0_SIZE_32MB) | \
+                              (PNX8550_XIO_SEL0_ENAB))
+#define PNX8550_GPXIO_PENDING        0x00000200
+#define PNX8550_GPXIO_DONE           0x00000100
+#define PNX8550_GPXIO_CLR_DONE       0x00000080
+#define PNX8550_GPXIO_INIT           0x00000040
+#define PNX8550_GPXIO_READ_CMD       0x00000010
+#define PNX8550_GPXIO_BEN            0x0000000F
+#define PNX8550_XIO_FLASH_64MB       0x00200000
+#define PNX8550_XIO_FLASH_INC_DATA   0x00100000
+#define PNX8550_XIO_FLASH_CMD_PH     0x000C0000
+#define PNX8550_XIO_FLASH_CMD_PH2    0x00080000
+#define PNX8550_XIO_FLASH_CMD_PH1    0x00040000
+#define PNX8550_XIO_FLASH_CMD_PH0    0x00000000
+#define PNX8550_XIO_FLASH_ADR_PH     0x00030000
+#define PNX8550_XIO_FLASH_ADR_PH3    0x00030000
+#define PNX8550_XIO_FLASH_ADR_PH2    0x00020000
+#define PNX8550_XIO_FLASH_ADR_PH1    0x00010000
+#define PNX8550_XIO_FLASH_ADR_PH0    0x00000000
+#define PNX8550_XIO_FLASH_CMD_B(x)   ((x<<8) & 0x0000FF00)
+#define PNX8550_XIO_FLASH_CMD_A(x)   (x & 0x000000FF)
+#define PNX8550_XIO_INT_ACK          0x00004000
+#define PNX8550_XIO_INT_COMPL        0x00002000
+#define PNX8550_XIO_INT_NONSUP       0x00000200
+#define PNX8550_XIO_INT_ABORT        0x00000004
+#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
+#define PNX8550_DMA_CTRL_SND2XIO     0x00000200
+#define PNX8550_DMA_CTRL_FIX_ADDR    0x00000100
+#define PNX8550_DMA_CTRL_BURST_8     0x00000000
+#define PNX8550_DMA_CTRL_BURST_16    0x00000020
+#define PNX8550_DMA_CTRL_BURST_32    0x00000040
+#define PNX8550_DMA_CTRL_BURST_64    0x00000060
+#define PNX8550_DMA_CTRL_BURST_128   0x00000080
+#define PNX8550_DMA_CTRL_BURST_256   0x000000A0
+#define PNX8550_DMA_CTRL_BURST_512   0x000000C0
+#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
+#define PNX8550_DMA_CTRL_INIT_DMA    0x00000010
+#define PNX8550_DMA_CTRL_CMD_TYPE    0x0000000F
+/* see PCI system arch, page 100 for the full list: */
+#define PNX8550_DMA_CTRL_PCI_CMD_READ    0x00000006
+#define PNX8550_DMA_CTRL_PCI_CMD_WRITE   0x00000007
+#define PNX8550_DMA_INT_STAT_ACK_DONE   (1<<14)
+#define PNX8550_DMA_INT_STAT_DMA_DONE   (1<<12)
+#define PNX8550_DMA_INT_STAT_DMA_ERR    (1<<9)
+#define PNX8550_DMA_INT_STAT_PERR5      (1<<5)
+#define PNX8550_DMA_INT_STAT_PERR4      (1<<4)
+#define PNX8550_DMA_INT_STAT_M_ABORT    (1<<2)
+#define PNX8550_DMA_INT_STAT_T_ABORT    (1<<1)
+#define PNX8550_DMA_INT_EN_ACK_DONE     (1<<14)
+#define PNX8550_DMA_INT_EN_DMA_DONE     (1<<12)
+#define PNX8550_DMA_INT_EN_DMA_ERR      (1<<9)
+#define PNX8550_DMA_INT_EN_PERR5        (1<<5)
+#define PNX8550_DMA_INT_EN_PERR4        (1<<4)
+#define PNX8550_DMA_INT_EN_M_ABORT      (1<<2)
+#define PNX8550_DMA_INT_EN_T_ABORT      (1<<1)
+#define PNX8550_DMA_INT_CLR_ACK_DONE    (1<<14)
+#define PNX8550_DMA_INT_CLR_DMA_DONE    (1<<12)
+#define PNX8550_DMA_INT_CLR_DMA_ERR     (1<<9)
+#define PNX8550_DMA_INT_CLR_PERR5       (1<<5)
+#define PNX8550_DMA_INT_CLR_PERR4       (1<<4)
+#define PNX8550_DMA_INT_CLR_M_ABORT     (1<<2)
+#define PNX8550_DMA_INT_CLR_T_ABORT     (1<<1)
+#endif
diff --git a/include/asm-mips/mach-pnx8550/pci.h b/include/asm-mips/mach-pnx8550/pci.h
new file mode 100644
index 000000000000..b921508d701b
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/pci.h
@@ -0,0 +1,185 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * PCI specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef __PNX8550_PCI_H
+#define __PNX8550_PCI_H
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+#define PCI_CMD_IOR                     0x20
+#define PCI_CMD_IOW                     0x30
+#define PCI_CMD_CONFIG_READ             0xa0
+#define PCI_CMD_CONFIG_WRITE            0xb0
+#define PCI_IO_TIMEOUT                  1000
+#define PCI_IO_RETRY                    5
+/* Timeout for IO and CFG accesses.
+   This is in 1/1024 th of a jiffie(=10ms)
+   i.e. approx 10us */
+#define PCI_IO_JIFFIES_TIMEOUT          40
+#define PCI_IO_JIFFIES_SHIFT            10
+#define PCI_BYTE_ENABLE_MASK            0x0000000f
+#define PCI_CFG_BUS_SHIFT               16
+#define PCI_CFG_FUNC_SHIFT              8
+#define PCI_CFG_REG_SHIFT               2
+#define PCI_BASE                  0x1be00000
+#define PCI_SETUP                 0x00040010
+#define PCI_DIS_REQGNT           (1<<30)
+#define PCI_DIS_REQGNTA          (1<<29)
+#define PCI_DIS_REQGNTB          (1<<28)
+#define PCI_D2_SUPPORT           (1<<27)
+#define PCI_D1_SUPPORT           (1<<26)
+#define PCI_EN_TA                (1<<24)
+#define PCI_EN_PCI2MMI           (1<<23)
+#define PCI_EN_XIO               (1<<22)
+#define PCI_BASE18_PREF          (1<<21)
+#define SIZE_16M                 0x3
+#define SIZE_32M                 0x4
+#define SIZE_64M                 0x5
+#define SIZE_128M                0x6
+#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
+#define PCI_SETUP_BASE18_EN      (1<<17)
+#define PCI_SETUP_BASE14_PREF    (1<<16)
+#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
+#define PCI_SETUP_BASE14_EN      (1<<11)
+#define PCI_SETUP_BASE10_PREF    (1<<10)
+#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
+#define PCI_SETUP_CFGMANAGE_EN   (1<<1)
+#define PCI_SETUP_PCIARB_EN      (1<<0)
+#define PCI_CTRL                  0x040014
+#define PCI_SWPB_DCS_PCI         (1<<16)
+#define PCI_SWPB_PCI_PCI         (1<<15)
+#define PCI_SWPB_PCI_DCS         (1<<14)
+#define PCI_REG_WR_POST          (1<<13)
+#define PCI_XIO_WR_POST          (1<<12)
+#define PCI_PCI2_WR_POST         (1<<13)
+#define PCI_PCI1_WR_POST         (1<<12)
+#define PCI_SERR_SEEN            (1<<11)
+#define PCI_B10_SPEC_RD          (1<<6)
+#define PCI_B14_SPEC_RD          (1<<5)
+#define PCI_B18_SPEC_RD          (1<<4)
+#define PCI_B10_NOSUBWORD        (1<<3)
+#define PCI_B14_NOSUBWORD        (1<<2)
+#define PCI_B18_NOSUBWORD        (1<<1)
+#define PCI_RETRY_TMREN          (1<<0)
+#define PCI_BASE1_LO              0x040018
+#define PCI_BASE1_HI              0x04001C
+#define PCI_BASE2_LO              0x040020
+#define PCI_BASE2_HI              0x040024
+#define PCI_RDLIFETIM             0x040028
+#define PCI_GPPM_ADDR             0x04002C
+#define PCI_GPPM_WDAT             0x040030
+#define PCI_GPPM_RDAT             0x040034
+#define PCI_GPPM_CTRL             0x040038
+#define GPPM_DONE                (1<<10)
+#define INIT_PCI_CYCLE           (1<<9)
+#define GPPM_CMD(X)              (((X)&0xf)<<4)
+#define GPPM_BYTEEN(X)           ((X)&0xf)
+#define PCI_UNLOCKREG             0x04003C
+#define UNLOCK_SSID(X)           (((X)&0xff)<<8)
+#define UNLOCK_SETUP(X)          (((X)&0xff)<<0)
+#define UNLOCK_MAGIC             0xCA
+#define PCI_DEV_VEND_ID           0x040040
+#define DEVICE_ID(X)             (((X)>>16)&0xffff)
+#define VENDOR_ID(X)             (((X)&0xffff))
+#define PCI_CFG_CMDSTAT           0x040044
+#define PCI_CFG_STATUS(X)            (((X)>>16)&0xffff)
+#define PCI_CFG_COMMAND(X)           ((X)&0xffff)
+#define PCI_CLASS_REV             0x040048
+#define PCI_CLASSCODE(X)         (((X)>>8)&0xffffff)
+#define PCI_REVID(X)             ((X)&0xff)
+#define PCI_LAT_TMR     0x04004c
+#define PCI_BASE10      0x040050
+#define PCI_BASE14      0x040054
+#define PCI_BASE18      0x040058
+#define PCI_SUBSYS_ID   0x04006c
+#define PCI_CAP_PTR     0x040074
+#define PCI_CFG_MISC    0x04007c
+#define PCI_PMC         0x040080
+#define PCI_PWR_STATE   0x040084
+#define PCI_IO          0x040088
+#define PCI_SLVTUNING   0x04008C
+#define PCI_DMATUNING   0x040090
+#define PCI_DMAEADDR    0x040800
+#define PCI_DMAIADDR    0x040804
+#define PCI_DMALEN      0x040808
+#define PCI_DMACTRL     0x04080C
+#define PCI_XIOCTRL     0x040810
+#define PCI_SEL0PROF    0x040814
+#define PCI_SEL1PROF    0x040818
+#define PCI_SEL2PROF    0x04081C
+#define PCI_GPXIOADDR   0x040820
+#define PCI_NANDCTRLS   0x400830
+#define PCI_SEL3PROF    0x040834
+#define PCI_SEL4PROF    0x040838
+#define PCI_GPXIO_STAT  0x040FB0
+#define PCI_GPXIO_IMASK 0x040FB4
+#define PCI_GPXIO_ICLR  0x040FB8
+#define PCI_GPXIO_ISET  0x040FBC
+#define PCI_GPPM_STATUS 0x040FC0
+#define GPPM_DONE      (1<<10)
+#define GPPM_ERR       (1<<9)
+#define GPPM_MPAR_ERR  (1<<8)
+#define GPPM_PAR_ERR   (1<<7)
+#define GPPM_R_MABORT  (1<<2)
+#define GPPM_R_TABORT  (1<<1)
+#define PCI_GPPM_IMASK  0x040FC4
+#define PCI_GPPM_ICLR   0x040FC8
+#define PCI_GPPM_ISET   0x040FCC
+#define PCI_DMA_STATUS  0x040FD0
+#define PCI_DMA_IMASK   0x040FD4
+#define PCI_DMA_ICLR    0x040FD8
+#define PCI_DMA_ISET    0x040FDC
+#define PCI_ISTATUS     0x040FE0
+#define PCI_IMASK       0x040FE4
+#define PCI_ICLR        0x040FE8
+#define PCI_ISET        0x040FEC
+#define PCI_MOD_ID      0x040FFC
+/*
+ *  PCI configuration cycle AD bus definition
+ */
+/* Type 0 */
+#define PCI_CFG_TYPE0_REG_SHF           0
+#define PCI_CFG_TYPE0_FUNC_SHF          8
+/* Type 1 */
+#define PCI_CFG_TYPE1_REG_SHF           0
+#define PCI_CFG_TYPE1_FUNC_SHF          8
+#define PCI_CFG_TYPE1_DEV_SHF           11
+#define PCI_CFG_TYPE1_BUS_SHF           16
+/*
+ *  Ethernet device DP83816 definition
+ */
+#define DP83816_IRQ_ETHER               66
+#endif
diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h
new file mode 100644
index 000000000000..e32b9a23d70e
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/uart.h
@@ -0,0 +1,16 @@
+#ifndef __IP3106_UART_H
+#define __IP3106_UART_H
+#include <int.h>
+/* early macros for kgdb use. fixme: clean this up */
+#define UART_BASE               0xbbe4a000      /* PNX8550 */
+#define PNX8550_UART_PORT0      (UART_BASE)
+#define PNX8550_UART_PORT1      (UART_BASE + 0x1000)
+#define PNX8550_UART_INT(x)             (PNX8550_INT_GIC_MIN+19+x)
+#define IRQ_TO_UART(x)                  (x-PNX8550_INT_GIC_MIN-19)
+#endif
diff --git a/include/asm-mips/mach-pnx8550/usb.h b/include/asm-mips/mach-pnx8550/usb.h
new file mode 100644
index 000000000000..483b7fc65d41
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/usb.h
@@ -0,0 +1,32 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *  USB specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef __PNX8550_USB_H
+#define __PNX8550_USB_H
+/*
+ * USB Host controller
+ */
+#define PNX8550_USB_OHCI_OP_BASE        0x1be48000
+#define PNX8550_USB_OHCI_OP_LEN         0x1000
+#endif
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
index f48736032b2a..79f9b064c864 100644
--- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
@@ -14,7 +14,7 @@
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
-#define cpu_has_4ktlb           1
+#define cpu_has_4kcache         1
 #define cpu_has_fpu             1
 #define cpu_has_32fpr           1
 #define cpu_has_counter         1
@@ -31,6 +31,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
index a3a2cc6014b2..193a666cd131 100644
--- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
 #define cpu_has_vtag_icache     1
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  0
 #define cpu_has_nofpuex         0
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h
new file mode 100644
index 000000000000..cadbe8eda79c
--- /dev/null
+++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h
@@ -0,0 +1,66 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Chris Dearman
+ */
+#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+#include <linux/config.h>
+/*
+ * CPU feature overrides for MIPS boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4kcache         1
+#define cpu_has_fpu             0
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_subset_pcaches ? */
+#endif
+#ifdef CONFIG_CPU_MIPS64
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4kcache         1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_subset_pcaches ? */
+#endif
+#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
index 58603e3daca6..463d051f4683 100644
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
 #define cpu_icache_snoops_remote_store  0
 #define cpu_has_nofpuex         0
@@ -36,10 +37,4 @@
 #define cpu_icache_line_size()  32
 #define cpu_scache_line_size()  32
-/*
- * On the RM9000 we need to ensure that I-cache lines being fetches only
- * contain valid instructions are funny things will happen.
- */
-#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
 #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index 65d1d16eab16..25b6ffc26623 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -66,6 +66,7 @@
 #define MIPS_REVISION_CORID_CORE_EMUL      6
 #define MIPS_REVISION_CORID_CORE_FPGA2     7
 #define MIPS_REVISION_CORID_CORE_FPGAR2    8
+#define MIPS_REVISION_CORID_CORE_FPGA3     9
 /**** Artificial corid defines ****/
 /*
@@ -79,4 +80,10 @@
 extern unsigned int mips_revision_corid;
+#ifdef CONFIG_PCI
+extern void mips_pcibios_init(void);
+#else
+#define mips_pcibios_init() do { } while (0)
+#endif
 #endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 376181882e81..da6cc2fbbc78 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -25,9 +25,63 @@
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
-/* Number of IRQ supported on hw interrupt 0. */
+/*
-#define MALTAINT_END      16
+ * Interrupts 0..15 are used for Malta ISA compatible interrupts
+ */
+#define MALTA_INT_BASE          0
+/*
+ * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
+ */
+#define MIPSCPU_INT_BASE        16
+/* CPU interrupt offsets */
+#define MIPSCPU_INT_SW0         0
+#define MIPSCPU_INT_SW1         1
+#define MIPSCPU_INT_MB0         2
+#define MIPSCPU_INT_I8259A      MIPSCPU_INT_MB0
+#define MIPSCPU_INT_MB1         3
+#define MIPSCPU_INT_SMI         MIPSCPU_INT_MB1
+#define MIPSCPU_INT_MB2         4
+#define MIPSCPU_INT_MB3         5
+#define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
+#define MIPSCPU_INT_MB4         6
+#define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
+#define MIPSCPU_INT_CPUCTR      7
+/*
+ * Interrupts 64..127 are used for Soc-it Classic interrupts
+ */
+#define MSC01C_INT_BASE         64
+/* SOC-it Classic interrupt offsets */
+#define MSC01C_INT_TMR          0
+#define MSC01C_INT_PCI          1
+/*
+ * Interrupts 64..127 are used for Soc-it EIC interrupts
+ */
+#define MSC01E_INT_BASE         64
+/* SOC-it EIC interrupt offsets */
+#define MSC01E_INT_SW0          1
+#define MSC01E_INT_SW1          2
+#define MSC01E_INT_MB0          3
+#define MSC01E_INT_I8259A       MSC01E_INT_MB0
+#define MSC01E_INT_MB1          4
+#define MSC01E_INT_SMI          MSC01E_INT_MB1
+#define MSC01E_INT_MB2          5
+#define MSC01E_INT_MB3          6
+#define MSC01E_INT_COREHI       MSC01E_INT_MB3
+#define MSC01E_INT_MB4          7
+#define MSC01E_INT_CORELO       MSC01E_INT_MB4
+#define MSC01E_INT_TMR          8
+#define MSC01E_INT_PCI          9
+#define MSC01E_INT_PERFCTR      10
+#define MSC01E_INT_CPUCTR       11
+#ifndef __ASSEMBLY__
 extern void maltaint_init(void);
+#endif
 #endif /* !(_MIPS_MALTAINT_H) */
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 6b2a87a38f4b..8eaefb837b9d 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -1,8 +1,9 @@
 /*
 * PCI Register definitions for the MIPS System Controller.
 *
- * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2002, 2005  MIPS Technologies, Inc.  All rights reserved.
- * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
@@ -29,22 +30,22 @@
 #define MSC01_PCI_CFGADDR_OFS           0x0610
 #define MSC01_PCI_CFGDATA_OFS           0x0618
 #define MSC01_PCI_IACK_OFS              0x0620
-#define MSC01_PCI_HEAD0_OFS             0x2000  /* DevID, VendorID */
+#define MSC01_PCI_HEAD0_OFS             0x2000  /* DevID, VendorID */
-#define MSC01_PCI_HEAD1_OFS             0x2008  /* Status, Command */
+#define MSC01_PCI_HEAD1_OFS             0x2008  /* Status, Command */
-#define MSC01_PCI_HEAD2_OFS             0x2010  /* Class code, RevID */
+#define MSC01_PCI_HEAD2_OFS             0x2010  /* Class code, RevID */
-#define MSC01_PCI_HEAD3_OFS             0x2018  /* bist, header, latency */
+#define MSC01_PCI_HEAD3_OFS             0x2018  /* bist, header, latency */
-#define MSC01_PCI_HEAD4_OFS             0x2020  /* BAR 0 */
+#define MSC01_PCI_HEAD4_OFS             0x2020  /* BAR 0 */
-#define MSC01_PCI_HEAD5_OFS             0x2028  /* BAR 1 */
+#define MSC01_PCI_HEAD5_OFS             0x2028  /* BAR 1 */
-#define MSC01_PCI_HEAD6_OFS             0x2030  /* BAR 2 */
+#define MSC01_PCI_HEAD6_OFS             0x2030  /* BAR 2 */
-#define MSC01_PCI_HEAD7_OFS             0x2038  /* BAR 3 */
+#define MSC01_PCI_HEAD7_OFS             0x2038  /* BAR 3 */
-#define MSC01_PCI_HEAD8_OFS             0x2040  /* BAR 4 */
+#define MSC01_PCI_HEAD8_OFS             0x2040  /* BAR 4 */
-#define MSC01_PCI_HEAD9_OFS             0x2048  /* BAR 5 */
+#define MSC01_PCI_HEAD9_OFS             0x2048  /* BAR 5 */
-#define MSC01_PCI_HEAD10_OFS            0x2050  /* CardBus CIS Ptr */
+#define MSC01_PCI_HEAD10_OFS            0x2050  /* CardBus CIS Ptr */
-#define MSC01_PCI_HEAD11_OFS            0x2058  /* SubSystem ID, -VendorID */
+#define MSC01_PCI_HEAD11_OFS            0x2058  /* SubSystem ID, -VendorID */
-#define MSC01_PCI_HEAD12_OFS            0x2060  /* ROM BAR */
+#define MSC01_PCI_HEAD12_OFS            0x2060  /* ROM BAR */
-#define MSC01_PCI_HEAD13_OFS            0x2068  /* Capabilities ptr */
+#define MSC01_PCI_HEAD13_OFS            0x2068  /* Capabilities ptr */
-#define MSC01_PCI_HEAD14_OFS            0x2070  /* reserved */
+#define MSC01_PCI_HEAD14_OFS            0x2070  /* reserved */
-#define MSC01_PCI_HEAD15_OFS            0x2078  /* Maxl, ming, intpin, int */
+#define MSC01_PCI_HEAD15_OFS            0x2078  /* Maxl, ming, intpin, int */
 #define MSC01_PCI_BAR0_OFS              0x2220
 #define MSC01_PCI_CFG_OFS               0x2380
 #define MSC01_PCI_SWAP_OFS              0x2388
@@ -86,73 +87,73 @@
 #define MSC01_PCI_P2SCMAPL_MAP_SHF      24
 #define MSC01_PCI_P2SCMAPL_MAP_MSK      0xff000000
-#define MSC01_PCI_INTCFG_RST_SHF        10
+#define MSC01_PCI_INTCFG_RST_SHF        10
-#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
+#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
-#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
+#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
-#define MSC01_PCI_INTCFG_MWE_SHF        9
+#define MSC01_PCI_INTCFG_MWE_SHF        9
-#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
+#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
-#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
+#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
-#define MSC01_PCI_INTCFG_DTO_SHF        8
+#define MSC01_PCI_INTCFG_DTO_SHF        8
-#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
+#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
-#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
+#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
-#define MSC01_PCI_INTCFG_MA_SHF         7
+#define MSC01_PCI_INTCFG_MA_SHF         7
-#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
+#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
-#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
+#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
-#define MSC01_PCI_INTCFG_TA_SHF         6
+#define MSC01_PCI_INTCFG_TA_SHF         6
-#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
+#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
-#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
+#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
-#define MSC01_PCI_INTCFG_RTY_SHF        5
+#define MSC01_PCI_INTCFG_RTY_SHF        5
-#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
+#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
-#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
+#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
-#define MSC01_PCI_INTCFG_MWP_SHF        4
+#define MSC01_PCI_INTCFG_MWP_SHF        4
-#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
+#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
-#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
+#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
-#define MSC01_PCI_INTCFG_MRP_SHF        3
+#define MSC01_PCI_INTCFG_MRP_SHF        3
-#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
+#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
-#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
+#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
-#define MSC01_PCI_INTCFG_SWP_SHF        2
+#define MSC01_PCI_INTCFG_SWP_SHF        2
-#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
+#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
-#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
+#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
-#define MSC01_PCI_INTCFG_SRP_SHF        1
+#define MSC01_PCI_INTCFG_SRP_SHF        1
-#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
+#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
-#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
+#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
-#define MSC01_PCI_INTCFG_SE_SHF         0
+#define MSC01_PCI_INTCFG_SE_SHF         0
-#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
+#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
-#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
+#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
-#define MSC01_PCI_INTSTAT_RST_SHF       10
+#define MSC01_PCI_INTSTAT_RST_SHF       10
-#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
+#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
-#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
+#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
-#define MSC01_PCI_INTSTAT_MWE_SHF       9
+#define MSC01_PCI_INTSTAT_MWE_SHF       9
-#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
+#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
-#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
+#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
-#define MSC01_PCI_INTSTAT_DTO_SHF       8
+#define MSC01_PCI_INTSTAT_DTO_SHF       8
-#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
+#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
-#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
+#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
-#define MSC01_PCI_INTSTAT_MA_SHF        7
+#define MSC01_PCI_INTSTAT_MA_SHF        7
-#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
+#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
-#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
+#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
-#define MSC01_PCI_INTSTAT_TA_SHF        6
+#define MSC01_PCI_INTSTAT_TA_SHF        6
-#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
+#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
-#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
+#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
-#define MSC01_PCI_INTSTAT_RTY_SHF       5
+#define MSC01_PCI_INTSTAT_RTY_SHF       5
-#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
+#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
-#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
+#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
-#define MSC01_PCI_INTSTAT_MWP_SHF       4
+#define MSC01_PCI_INTSTAT_MWP_SHF       4
-#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
+#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
-#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
+#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
-#define MSC01_PCI_INTSTAT_MRP_SHF       3
+#define MSC01_PCI_INTSTAT_MRP_SHF       3
-#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
+#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
-#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
+#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
-#define MSC01_PCI_INTSTAT_SWP_SHF       2
+#define MSC01_PCI_INTSTAT_SWP_SHF       2
-#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
+#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
-#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
+#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
-#define MSC01_PCI_INTSTAT_SRP_SHF       1
+#define MSC01_PCI_INTSTAT_SRP_SHF       1
-#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
+#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
-#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
+#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
-#define MSC01_PCI_INTSTAT_SE_SHF        0
+#define MSC01_PCI_INTSTAT_SE_SHF        0
-#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
+#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
-#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
+#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
 #define MSC01_PCI_CFGADDR_BNUM_SHF      16
 #define MSC01_PCI_CFGADDR_BNUM_MSK      0x00ff0000
@@ -167,29 +168,29 @@
 #define MSC01_PCI_CFGDATA_DATA_MSK      0xffffffff
 /* The defines below are ONLY valid for a MEM bar! */
-#define MSC01_PCI_BAR0_SIZE_SHF         4
+#define MSC01_PCI_BAR0_SIZE_SHF         4
-#define MSC01_PCI_BAR0_SIZE_MSK         0xfffffff0
+#define MSC01_PCI_BAR0_SIZE_MSK         0xfffffff0
-#define MSC01_PCI_BAR0_P_SHF            3
+#define MSC01_PCI_BAR0_P_SHF            3
-#define MSC01_PCI_BAR0_P_MSK            0x00000008
+#define MSC01_PCI_BAR0_P_MSK            0x00000008
-#define MSC01_PCI_BAR0_P_BIT            MSC01_PCI_BAR0_P_MSK
+#define MSC01_PCI_BAR0_P_BIT            MSC01_PCI_BAR0_P_MSK
-#define MSC01_PCI_BAR0_D_SHF            1
+#define MSC01_PCI_BAR0_D_SHF            1
-#define MSC01_PCI_BAR0_D_MSK            0x00000006
+#define MSC01_PCI_BAR0_D_MSK            0x00000006
-#define MSC01_PCI_BAR0_T_SHF            0
+#define MSC01_PCI_BAR0_T_SHF            0
-#define MSC01_PCI_BAR0_T_MSK            0x00000001
+#define MSC01_PCI_BAR0_T_MSK            0x00000001
-#define MSC01_PCI_BAR0_T_BIT            MSC01_PCI_BAR0_T_MSK
+#define MSC01_PCI_BAR0_T_BIT            MSC01_PCI_BAR0_T_MSK
-#define MSC01_PCI_CFG_RA_SHF            17
+#define MSC01_PCI_CFG_RA_SHF            17
-#define MSC01_PCI_CFG_RA_MSK            0x00020000
+#define MSC01_PCI_CFG_RA_MSK            0x00020000
-#define MSC01_PCI_CFG_RA_BIT            MSC01_PCI_CFG_RA_MSK
+#define MSC01_PCI_CFG_RA_BIT            MSC01_PCI_CFG_RA_MSK
-#define MSC01_PCI_CFG_G_SHF             16
+#define MSC01_PCI_CFG_G_SHF             16
-#define MSC01_PCI_CFG_G_MSK             0x00010000
+#define MSC01_PCI_CFG_G_MSK             0x00010000
-#define MSC01_PCI_CFG_G_BIT             MSC01_PCI_CFG_G_MSK
+#define MSC01_PCI_CFG_G_BIT             MSC01_PCI_CFG_G_MSK
-#define MSC01_PCI_CFG_EN_SHF            15
+#define MSC01_PCI_CFG_EN_SHF            15
-#define MSC01_PCI_CFG_EN_MSK            0x00008000
+#define MSC01_PCI_CFG_EN_MSK            0x00008000
-#define MSC01_PCI_CFG_EN_BIT            MSC01_PCI_CFG_EN_MSK
+#define MSC01_PCI_CFG_EN_BIT            MSC01_PCI_CFG_EN_MSK
-#define MSC01_PCI_CFG_MAXRTRY_SHF       0
+#define MSC01_PCI_CFG_MAXRTRY_SHF       0
-#define MSC01_PCI_CFG_MAXRTRY_MSK       0x000000ff
+#define MSC01_PCI_CFG_MAXRTRY_MSK       0x00000fff
 #define MSC01_PCI_SWAP_IO_SHF           18
 #define MSC01_PCI_SWAP_IO_MSK           0x000c0000
@@ -206,7 +207,7 @@
 * FIXME - are these macros specific to Malta and co or to the MSC?  If the
 * latter, they should be moved elsewhere.
 */
-#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
+#define MIPS_MSC01_PCI_REG_BASE         0x1bd00000
 extern unsigned long _pcictrl_msc;
@@ -219,19 +220,19 @@ extern unsigned long _pcictrl_msc;
 * Registers absolute addresses
 */
-#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
+#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
-#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
+#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
-#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
+#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
-#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
+#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
-#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
+#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
-#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
+#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
-#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
+#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
-#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
+#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
-#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
+#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
-#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
+#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
-#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
+#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
-#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
+#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
-#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
+#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
 #define MSC01_PCI_IACK          (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
 #define MSC01_PCI_HEAD0         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
 #define MSC01_PCI_HEAD1         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
@@ -248,7 +249,7 @@ extern unsigned long _pcictrl_msc;
 #define MSC01_PCI_HEAD12        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_HEAD13        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_HEAD14        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_BAR0          (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
 #define MSC01_PCI_CFG           (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
 #define MSC01_PCI_SWAP          (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h
new file mode 100644
index 000000000000..acb7c2331d98
--- /dev/null
+++ b/include/asm-mips/mips-boards/sim.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#ifndef _ASM_MIPS_BOARDS_SIM_H
+#define _ASM_MIPS_BOARDS_SIM_H
+#define STATS_ON        1
+#define STATS_OFF       2
+#define STATS_CLEAR     3
+#define STATS_DUMP      4
+#define TRACE_ON                5
+#define TRACE_OFF       6
+#define simcfg(code)                                            \
+({                                         \
+        __asm__  __volatile__( \
+        "sltiu $0,$0, %0" \
+                ::"i"(code)                                     \
+                ); \
+})
+#endif
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
new file mode 100644
index 000000000000..4952e0b3bf11
--- /dev/null
+++ b/include/asm-mips/mips-boards/simint.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef _MIPS_SIMINT_H
+#define _MIPS_SIMINT_H
+#define SIM_INT_BASE            0
+#define MIPSCPU_INT_MB0         2
+#define MIPSCPU_INT_BASE        16
+#define MIPS_CPU_TIMER_IRQ      7
+#define MIPSCPU_INT_CPUCTR      7
+#define MSC01E_INT_BASE         64
+#define MIPSCPU_INT_CPUCTR      7
+#define MSC01E_INT_CPUCTR       11
+#endif
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h
new file mode 100644
index 000000000000..a669c0702c66
--- /dev/null
+++ b/include/asm-mips/mipsmtregs.h
@@ -0,0 +1,391 @@
+/*
+ * MT regs definitions, follows on from mipsregs.h
+ * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Elizabeth Clarke et. al.
+ *
+ */
+#ifndef _ASM_MIPSMTREGS_H
+#define _ASM_MIPSMTREGS_H
+#include <asm/mipsregs.h>
+#include <asm/war.h>
+#ifndef __ASSEMBLY__
+/*
+ * C macros
+ */
+#define read_c0_mvpcontrol()            __read_32bit_c0_register($0, 1)
+#define write_c0_mvpcontrol(val)        __write_32bit_c0_register($0, 1, val)
+#define read_c0_mvpconf0()              __read_32bit_c0_register($0, 2)
+#define read_c0_mvpconf1()              __read_32bit_c0_register($0, 3)
+#define read_c0_vpecontrol()            __read_32bit_c0_register($1, 1)
+#define write_c0_vpecontrol(val)        __write_32bit_c0_register($1, 1, val)
+#define read_c0_vpeconf0()              __read_32bit_c0_register($1, 2)
+#define write_c0_vpeconf0(val)          __write_32bit_c0_register($1, 2, val)
+#define read_c0_tcstatus()              __read_32bit_c0_register($2, 1)
+#define write_c0_tcstatus(val)          __write_32bit_c0_register($2, 1, val)
+#define read_c0_tcbind()                __read_32bit_c0_register($2, 2)
+#define read_c0_tccontext()             __read_32bit_c0_register($2, 5)
+#define write_c0_tccontext(val)         __write_32bit_c0_register($2, 5, val)
+#else /* Assembly */
+/*
+ * Macros for use in assembly language code
+ */
+#define CP0_MVPCONTROL          $0,1
+#define CP0_MVPCONF0            $0,2
+#define CP0_MVPCONF1            $0,3
+#define CP0_VPECONTROL          $1,1
+#define CP0_VPECONF0            $1,2
+#define CP0_VPECONF1            $1,3
+#define CP0_YQMASK              $1,4
+#define CP0_VPESCHEDULE $1,5
+#define CP0_VPESCHEFBK          $1,6
+#define CP0_TCSTATUS            $2,1
+#define CP0_TCBIND              $2,2
+#define CP0_TCRESTART           $2,3
+#define CP0_TCHALT              $2,4
+#define CP0_TCCONTEXT           $2,5
+#define CP0_TCSCHEDULE          $2,6
+#define CP0_TCSCHEFBK           $2,7
+#define CP0_SRSCONF0            $6,1
+#define CP0_SRSCONF1            $6,2
+#define CP0_SRSCONF2            $6,3
+#define CP0_SRSCONF3            $6,4
+#define CP0_SRSCONF4            $6,5
+#endif
+/* MVPControl fields */
+#define MVPCONTROL_EVP          (_ULCAST_(1))
+#define MVPCONTROL_VPC_SHIFT    1
+#define MVPCONTROL_VPC          (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
+#define MVPCONTROL_STLB_SHIFT   2
+#define MVPCONTROL_STLB         (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
+/* MVPConf0 fields */
+#define MVPCONF0_PTC_SHIFT      0
+#define MVPCONF0_PTC            ( _ULCAST_(0xff))
+#define MVPCONF0_PVPE_SHIFT     10
+#define MVPCONF0_PVPE           ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
+#define MVPCONF0_TCA_SHIFT      15
+#define MVPCONF0_TCA            ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
+#define MVPCONF0_PTLBE_SHIFT    16
+#define MVPCONF0_PTLBE          (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
+#define MVPCONF0_TLBS_SHIFT     29
+#define MVPCONF0_TLBS           (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
+#define MVPCONF0_M_SHIFT        31
+#define MVPCONF0_M              (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
+/* config3 fields */
+#define CONFIG3_MT_SHIFT        2
+#define CONFIG3_MT              (_ULCAST_(1) << CONFIG3_MT_SHIFT)
+/* VPEControl fields (per VPE) */
+#define VPECONTROL_TARGTC       (_ULCAST_(0xff))
+#define VPECONTROL_TE_SHIFT     15
+#define VPECONTROL_TE           (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
+#define VPECONTROL_EXCPT_SHIFT  16
+#define VPECONTROL_EXCPT        (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
+/* Thread Exception Codes for EXCPT field */
+#define THREX_TU                0
+#define THREX_TO                1
+#define THREX_IYQ               2
+#define THREX_GSX               3
+#define THREX_YSCH              4
+#define THREX_GSSCH             5
+#define VPECONTROL_GSI_SHIFT    20
+#define VPECONTROL_GSI          (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
+#define VPECONTROL_YSI_SHIFT    21
+#define VPECONTROL_YSI          (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
+/* VPEConf0 fields (per VPE) */
+#define VPECONF0_VPA_SHIFT      0
+#define VPECONF0_VPA            (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
+#define VPECONF0_MVP_SHIFT      1
+#define VPECONF0_MVP            (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
+#define VPECONF0_XTC_SHIFT      21
+#define VPECONF0_XTC            (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
+/* TCStatus fields (per TC) */
+#define TCSTATUS_TASID          (_ULCAST_(0xff))
+#define TCSTATUS_IXMT_SHIFT     10
+#define TCSTATUS_IXMT           (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
+#define TCSTATUS_TKSU_SHIFT     11
+#define TCSTATUS_TKSU           (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
+#define TCSTATUS_A_SHIFT        13
+#define TCSTATUS_A              (_ULCAST_(1) << TCSTATUS_A_SHIFT)
+#define TCSTATUS_DA_SHIFT       15
+#define TCSTATUS_DA             (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
+#define TCSTATUS_DT_SHIFT       20
+#define TCSTATUS_DT             (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
+#define TCSTATUS_TDS_SHIFT      21
+#define TCSTATUS_TDS            (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
+#define TCSTATUS_TSST_SHIFT     22
+#define TCSTATUS_TSST           (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
+#define TCSTATUS_RNST_SHIFT     23
+#define TCSTATUS_RNST           (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
+/* Codes for RNST */
+#define TC_RUNNING              0
+#define TC_WAITING              1
+#define TC_YIELDING             2
+#define TC_GATED                3
+#define TCSTATUS_TMX_SHIFT      27
+#define TCSTATUS_TMX            (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
+/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
+/* TCBind */
+#define TCBIND_CURVPE_SHIFT     0
+#define TCBIND_CURVPE           (_ULCAST_(0xf))
+#define TCBIND_CURTC_SHIFT      21
+#define TCBIND_CURTC            (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
+/* TCHalt */
+#define TCHALT_H                (_ULCAST_(1))
+#ifndef __ASSEMBLY__
+extern void mips_mt_regdump(void);
+static inline unsigned int dvpe(void)
+{
+        int res = 0;
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41610001              # dvpe $1               \n"
+        "       move    %0, $1                                          \n"
+        "       ehb                                                     \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+        instruction_hazard();
+        return res;
+}
+static inline void __raw_evpe(void)
+{
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41600021              # evpe                  \n"
+        "       ehb                                                     \n"
+        "       .set    pop                                             \n");
+}
+/* Enable multiMT if previous suggested it should be.
+   EMT_ENABLE to force */
+#define EVPE_ENABLE MVPCONTROL_EVP
+static inline void evpe(int previous)
+{
+        if ((previous & MVPCONTROL_EVP))
+                __raw_evpe();
+}
+static inline unsigned int dmt(void)
+{
+        int res;
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .set    noat                                            \n"
+        "       .word   0x41610BC1                      # dmt $1        \n"
+        "       ehb                                                     \n"
+        "       move    %0, $1                                          \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+        instruction_hazard();
+        return res;
+}
+static inline void __raw_emt(void)
+{
+        __asm__ __volatile__(
+        "       .set    noreorder                                       \n"
+        "       .set    mips32r2                                        \n"
+        "       emt                                                     \n"
+        "       ehb                                                     \n"
+        "       .set    mips0                                           \n"
+        "       .set    reorder");
+}
+/* enable multiVPE if previous suggested it should be.
+   EVPE_ENABLE to force */
+#define EMT_ENABLE VPECONTROL_TE
+static inline void emt(int previous)
+{
+        if ((previous & EMT_ENABLE))
+                __raw_emt();
+}
+static inline void ehb(void)
+{
+        __asm__ __volatile__(
+        "       .set    mips32r2                                \n"
+        "       ehb                                             \n"
+        "       .set    mips0                                   \n");
+}
+#define mftc0(rt,sel)                                                   \
+({                                                                      \
+         unsigned long  __res;                                          \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       # mftc0 $1, $" #rt ", " #sel "                  \n"     \
+        "       .word   0x41000800 | (" #rt " << 16) | " #sel " \n"     \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+#define mftgpr(rt)                                                      \
+({                                                                      \
+        unsigned long __res;                                            \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       mftgpr  %0," #rt "                              \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+#define mftr(rt,u,sel)                                                  \
+({                                                                      \
+        unsigned long __res;                                            \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        ".set noat\n\t"                                                 \
+        "mftr\t%0, " #rt ", " #u ", " #sel "\n\t"                       \
+        ".set at\n\t"                                                   \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+#define mttgpr(rd,v)                                                    \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mttgpr $1, " #rd "                            \n"     \
+        "       .word   0x41810020 | (" #rd " << 11)            \n"     \
+        "       .set    pop                                     \n"     \
+        : : "r" (v));                                                   \
+} while (0)
+#define mttc0(rd,sel,v)                                                 \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mttc0 %0," #rd ", " #sel "                    \n"     \
+        "       .word   0x41810000 | (" #rd " << 11) | " #sel " \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (v));                                                     \
+})
+#define mttr(rd,u,sel,v)                                                \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "mttr   %0," #rd ", " #u ", " #sel                              \
+        : : "r" (v));                                                   \
+})
+#define settc(tc)                                                       \
+do {                                                                    \
+        write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
+        ehb();                                                          \
+} while (0)
+/* you *must* set the target tc (settc) before trying to use these */
+#define read_vpe_c0_vpecontrol()        mftc0(1, 1)
+#define write_vpe_c0_vpecontrol(val)    mttc0(1, 1, val)
+#define read_vpe_c0_vpeconf0()          mftc0(1, 2)
+#define write_vpe_c0_vpeconf0(val)      mttc0(1, 2, val)
+#define read_vpe_c0_status()            mftc0(12, 0)
+#define write_vpe_c0_status(val)        mttc0(12, 0, val)
+#define read_vpe_c0_cause()             mftc0(13, 0)
+#define write_vpe_c0_cause(val)         mttc0(13, 0, val)
+#define read_vpe_c0_config()            mftc0(16, 0)
+#define write_vpe_c0_config(val)        mttc0(16, 0, val)
+#define read_vpe_c0_config1()           mftc0(16, 1)
+#define write_vpe_c0_config1(val)       mttc0(16, 1, val)
+#define read_vpe_c0_config7()           mftc0(16, 7)
+#define write_vpe_c0_config7(val)       mttc0(16, 7, val)
+#define read_vpe_c0_ebase()             mftc0(15,1)
+#define write_vpe_c0_ebase(val)         mttc0(15, 1, val)
+#define write_vpe_c0_compare(val)       mttc0(11, 0, val)
+/* TC */
+#define read_tc_c0_tcstatus()           mftc0(2, 1)
+#define write_tc_c0_tcstatus(val)       mttc0(2,1,val)
+#define read_tc_c0_tcbind()             mftc0(2, 2)
+#define write_tc_c0_tcbind(val)         mttc0(2,2,val)
+#define read_tc_c0_tcrestart()          mftc0(2, 3)
+#define write_tc_c0_tcrestart(val)      mttc0(2,3,val)
+#define read_tc_c0_tchalt()             mftc0(2, 4)
+#define write_tc_c0_tchalt(val)         mttc0(2,4,val)
+#define read_tc_c0_tccontext()          mftc0(2, 5)
+#define write_tc_c0_tccontext(val)      mttc0(2,5,val)
+/* GPR */
+#define read_tc_gpr_sp()                mftgpr(29)
+#define write_tc_gpr_sp(val)            mttgpr(29, val)
+#define read_tc_gpr_gp()                mftgpr(28)
+#define write_tc_gpr_gp(val)            mttgpr(28, val)
+__BUILD_SET_C0(mvpcontrol)
+#endif /* Not __ASSEMBLY__ */
+#endif
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 2197aa4ce456..80370e0a5589 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -8,7 +8,7 @@
 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- * Copyright (C) 2003  Maciej W. Rozycki
+ * Copyright (C) 2003, 2004  Maciej W. Rozycki
 */
 #ifndef _ASM_MIPSREGS_H
 #define _ASM_MIPSREGS_H
@@ -96,6 +96,16 @@
 #define CP0_S1_INTCONTROL $20
 /*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL     $12   /* MIPSR2 */
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP     $12   /* MIPSR2 */
+/*
 *  TX39 Series
 */
 #define CP0_TX39_CACHE  $7
@@ -281,6 +291,11 @@
 #define ST0_DL                  (_ULCAST_(1) << 24)
 /*
+ * Enable the MIPS DSP ASE
+ */
+#define ST0_MX                  0x01000000
+/*
 * Bitfields in the TX39 family CP0 Configuration Register 3
 */
 #define TX39_CONF_ICS_SHIFT     19
@@ -433,6 +448,14 @@
 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
+/* Bits specific to the RM7000.  */
+#define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
+#define RM7K_CONF_TE            (_ULCAST_(1) << 12)
+#define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
+#define RM7K_CONF_TC            (_ULCAST_(1) << 17)
+#define RM7K_CONF_SI            (_ULCAST_(3) << 20)
+#define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 /* Bits specific to the R10000.  */
 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
@@ -475,6 +498,53 @@
 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 /*
+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
+ */
+#define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
+#define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
+#define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
+#define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
+#define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
+#define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
+#define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
+#define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
+#define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
+#define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
+#define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
+#define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
+#define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
+#define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
+#define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
+#define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
+#define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
+#define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
+#define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
+#define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
+#define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
+#define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
+#define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
+#define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S             (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D             (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W             (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L             (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
+/*
 * R10000 performance counter definitions.
 *
 * FIXME: The R10000 performance counter opens a nice way to implement CPU
@@ -621,13 +691,13 @@ do {									\
        if (sel == 0)                                                   \
                __asm__ __volatile__(                                   \
                        "mtc0\t%z0, " #register "\n\t"                  \
-                        : : "Jr" ((unsigned int)value));                \
+                        : : "Jr" ((unsigned int)(value)));              \
        else                                                            \
                __asm__ __volatile__(                                   \
                        ".set\tmips32\n\t"                              \
                        "mtc0\t%z0, " #register ", " #sel "\n\t"        \
                        ".set\tmips0"                                   \
-                        : : "Jr" ((unsigned int)value));                \
+                        : : "Jr" ((unsigned int)(value)));              \
 } while (0)
 #define __write_64bit_c0_register(register, sel, value)                 \
@@ -676,7 +746,7 @@ do {									\
 do {                                                                    \
        __asm__ __volatile__(                                           \
                "ctc0\t%z0, " #register "\n\t"                          \
-                : : "Jr" ((unsigned int)value));                        \
+                : : "Jr" ((unsigned int)(value)));                      \
 } while (0)
 /*
@@ -769,12 +839,24 @@ do {									\
 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
+#define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
+#define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
+#define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
+#define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
+#define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
+#define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
+#define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
+#define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
@@ -790,10 +872,18 @@ do {									\
 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
+#define read_c0_config4()       __read_32bit_c0_register($16, 4)
+#define read_c0_config5()       __read_32bit_c0_register($16, 5)
+#define read_c0_config6()       __read_32bit_c0_register($16, 6)
+#define read_c0_config7()       __read_32bit_c0_register($16, 7)
 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
+#define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
+#define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
+#define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
+#define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 /*
 * The WatchLo register.  There may be upto 8 of them.
@@ -917,6 +1007,22 @@ do {									\
 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
+/* MIPSR2 */
+#define read_c0_hwrena()        __read_32bit_c0_register($7,0)
+#define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
+#define read_c0_intctl()        __read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
+#define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
+#define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
+#define read_c0_ebase()         __read_32bit_c0_register($15,1)
+#define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
 /*
 * Macros to access the floating point coprocessor control registers
 */
@@ -930,6 +1036,284 @@ do {									\
        : "=r" (__res));                                        \
        __res;})
+#define rddsp(mask)                                                     \
+({                                                                      \
+        unsigned int __res;                                             \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                            \n"             \
+        "       .set    noat                            \n"             \
+        "       # rddsp $1, %x1                         \n"             \
+        "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
+        "       move    %0, $1                          \n"             \
+        "       .set    pop                             \n"             \
+        : "=r" (__res)                                                  \
+        : "i" (mask));                                                  \
+        __res;                                                          \
+})
+#define wrdsp(val, mask)                                                \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # wrdsp $1, %x1                                 \n"     \
+        "       .word   0x7c2004f8 | (%x1 << 15)                \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (val), "i" (mask));                                       \
+} while (0)
+#if 0   /* Need DSP ASE capable assembler ... */
+#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
+#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
+#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
+#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
+#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
+#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
+#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
+#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
+#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
+#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
+#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
+#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
+#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
+#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
+#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
+#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
+#else
+#define mfhi0()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac0                \n"                     \
+        "       .word   0x00000810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+#define mfhi1()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac1                \n"                     \
+        "       .word   0x00200810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+#define mfhi2()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac2                \n"                     \
+        "       .word   0x00400810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+#define mfhi3()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac3                \n"                     \
+        "       .word   0x00600810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+#define mflo0()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac0                \n"                     \
+        "       .word   0x00000812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+#define mflo1()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac1                \n"                     \
+        "       .word   0x00200812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+#define mflo2()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac2                \n"                     \
+        "       .word   0x00400812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+#define mflo3()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac3                \n"                     \
+        "       .word   0x00600812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+#define mthi0(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac0                                \n"     \
+        "       .word   0x00200011                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+#define mthi1(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac1                                \n"     \
+        "       .word   0x00200811                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+#define mthi2(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac2                                \n"     \
+        "       .word   0x00201011                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+#define mthi3(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac3                                \n"     \
+        "       .word   0x00201811                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+#define mtlo0(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac0                                \n"     \
+        "       .word   0x00200013                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+#define mtlo1(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac1                                \n"     \
+        "       .word   0x00200813                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+#define mtlo2(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac2                                \n"     \
+        "       .word   0x00201013                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+#define mtlo3(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac3                                \n"     \
+        "       .word   0x00201813                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+#endif
 /*
 * TLB operations.
 *
@@ -1012,6 +1396,8 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
+__BUILD_SET_C0(intctl)
+__BUILD_SET_C0(srsmap)
 #endif /* !__ASSEMBLY__ */
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 45cd72d172e8..19cdf7642e66 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -30,7 +30,7 @@ extern unsigned long pgd_current[];
 #ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()                                         \
-        write_c0_context((unsigned long) smp_processor_id() << 23);     \
+        write_c0_context((unsigned long) smp_processor_id() << 25);     \
        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
 #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
@@ -40,7 +40,7 @@ extern unsigned long pgd_current[];
 #endif
 #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
 #define TLBMISS_HANDLER_SETUP()                                         \
-        write_c0_context((unsigned long) smp_processor_id() << 23);     \
+        write_c0_context((unsigned long) smp_processor_id() << 26);     \
        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
index d721143dbd47..011caebac369 100644
--- a/include/asm-mips/mmzone.h
+++ b/include/asm-mips/mmzone.h
@@ -5,6 +5,7 @@
 #ifndef _ASM_MMZONE_H_
 #define _ASM_MMZONE_H_
+#include <linux/config.h>
 #include <asm/page.h>
 #include <mmzone.h>
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index 0be58b2aeb9f..2be399311eec 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -14,15 +14,23 @@ struct mod_arch_specific {
 typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
-typedef struct
+typedef struct {
-{
+        Elf64_Addr r_offset;                    /* Address of relocation.  */
-  Elf64_Addr r_offset;                  /* Address of relocation.  */
+        Elf64_Word r_sym;                       /* Symbol index.  */
-  Elf64_Word r_sym;                     /* Symbol index.  */
+        Elf64_Byte r_ssym;                      /* Special symbol.  */
-  Elf64_Byte r_ssym;                    /* Special symbol.  */
+        Elf64_Byte r_type3;                     /* Third relocation.  */
-  Elf64_Byte r_type3;                   /* Third relocation.  */
+        Elf64_Byte r_type2;                     /* Second relocation.  */
-  Elf64_Byte r_type2;                   /* Second relocation.  */
+        Elf64_Byte r_type;                      /* First relocation.  */
-  Elf64_Byte r_type;                    /* First relocation.  */
+} Elf64_Mips_Rel;
-  Elf64_Sxword r_addend;                /* Addend.  */
+typedef struct {
+        Elf64_Addr r_offset;                    /* Address of relocation.  */
+        Elf64_Word r_sym;                       /* Symbol index.  */
+        Elf64_Byte r_ssym;                      /* Special symbol.  */
+        Elf64_Byte r_type3;                     /* Third relocation.  */
+        Elf64_Byte r_type2;                     /* Second relocation.  */
+        Elf64_Byte r_type;                      /* First relocation.  */
+        Elf64_Sxword r_addend;                  /* Addend.  */
 } Elf64_Mips_Rela;
 #ifdef CONFIG_32BIT
@@ -30,6 +38,13 @@ typedef struct
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
 #define Elf_Ehdr        Elf32_Ehdr
+#define Elf_Addr        Elf32_Addr
+#define Elf_Mips_Rel    Elf32_Rel
+#define Elf_Mips_Rela   Elf32_Rela
+#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info)
+#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info)
 #endif
@@ -38,6 +53,13 @@ typedef struct
 #define Elf_Shdr        Elf64_Shdr
 #define Elf_Sym         Elf64_Sym
 #define Elf_Ehdr        Elf64_Ehdr
+#define Elf_Addr        Elf64_Addr
+#define Elf_Mips_Rel    Elf64_Mips_Rel
+#define Elf_Mips_Rela   Elf64_Mips_Rela
+#define ELF_MIPS_R_SYM(rel) (rel.r_sym)
+#define ELF_MIPS_R_TYPE(rel) (rel.r_type)
 #endif
@@ -53,4 +75,54 @@ search_module_dbetables(unsigned long addr)
 }
 #endif
+#ifdef CONFIG_CPU_MIPS32_R1
+#define MODULE_PROC_FAMILY "MIPS32_R1"
+#elif defined CONFIG_CPU_MIPS32_R2
+#define MODULE_PROC_FAMILY "MIPS32_R2"
+#elif defined CONFIG_CPU_MIPS64_R1
+#define MODULE_PROC_FAMILY "MIPS64_R1"
+#elif defined CONFIG_CPU_MIPS64_R2
+#define MODULE_PROC_FAMILY "MIPS64_R2"
+#elif defined CONFIG_CPU_R3000
+#define MODULE_PROC_FAMILY "R3000"
+#elif defined CONFIG_CPU_TX39XX
+#define MODULE_PROC_FAMILY "TX39XX"
+#elif defined CONFIG_CPU_VR41XX
+#define MODULE_PROC_FAMILY "VR41XX"
+#elif defined CONFIG_CPU_R4300
+#define MODULE_PROC_FAMILY "R4300"
+#elif defined CONFIG_CPU_R4X00
+#define MODULE_PROC_FAMILY "R4X00"
+#elif defined CONFIG_CPU_TX49XX
+#define MODULE_PROC_FAMILY "TX49XX"
+#elif defined CONFIG_CPU_R5000
+#define MODULE_PROC_FAMILY "R5000"
+#elif defined CONFIG_CPU_R5432
+#define MODULE_PROC_FAMILY "R5432"
+#elif defined CONFIG_CPU_R6000
+#define MODULE_PROC_FAMILY "R6000"
+#elif defined CONFIG_CPU_NEVADA
+#define MODULE_PROC_FAMILY "NEVADA"
+#elif defined CONFIG_CPU_R8000
+#define MODULE_PROC_FAMILY "R8000"
+#elif defined CONFIG_CPU_R10000
+#define MODULE_PROC_FAMILY "R10000"
+#elif defined CONFIG_CPU_RM7000
+#define MODULE_PROC_FAMILY "RM7000"
+#elif defined CONFIG_CPU_RM9000
+#define MODULE_PROC_FAMILY "RM9000"
+#elif defined CONFIG_CPU_SB1
+#define MODULE_PROC_FAMILY "SB1"
+#else
+#error MODULE_PROC_FAMILY undefined for your processor configuration
+#endif
+#ifdef CONFIG_32BIT
+#define MODULE_KERNEL_TYPE "32BIT "
+#elif defined CONFIG_64BIT
+#define MODULE_KERNEL_TYPE "64BIT "
+#endif
+#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE
 #endif /* _ASM_MODULE_H */
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
index 309bc3099f68..46f2d23d2697 100644
--- a/include/asm-mips/paccess.h
+++ b/include/asm-mips/paccess.h
@@ -52,7 +52,7 @@ struct __large_pstruct { unsigned long buf[100]; };
 })
 #define __get_dbe_asm(insn)                                             \
-({                                                                      \
+{                                                                       \
        __asm__ __volatile__(                                           \
        "1:\t" insn "\t%1,%2\n\t"                                       \
        "move\t%0,$0\n"                                                 \
@@ -67,7 +67,7 @@ struct __large_pstruct { unsigned long buf[100]; };
        ".previous"                                                     \
        :"=r" (__gu_err), "=r" (__gu_val)                               \
        :"o" (__mp(__gu_addr)), "i" (-EFAULT));                         \
-})
+}
 extern void __get_dbe_unknown(void);
@@ -90,7 +90,7 @@ extern void __get_dbe_unknown(void);
 })
 #define __put_dbe_asm(insn)                                             \
-({                                                                      \
+{                                                                       \
        __asm__ __volatile__(                                           \
        "1:\t" insn "\t%1,%2\n\t"                                       \
        "move\t%0,$0\n"                                                 \
@@ -104,7 +104,7 @@ extern void __get_dbe_unknown(void);
        ".previous"                                                     \
        : "=r" (__pu_err)                                               \
        : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT));        \
-})
+}
 extern void __put_dbe_unknown(void);
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 652b6d67a571..ee25a779bf49 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -87,22 +87,48 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 typedef struct { unsigned long pte; } pte_t;
 #define pte_val(x)      ((x).pte)
 #endif
+#define __pte(x)        ((pte_t) { (x) } )
-typedef struct { unsigned long pmd; } pmd_t;
+/*
-typedef struct { unsigned long pgd; } pgd_t;
+ * For 3-level pagetables we defines these ourselves, for 2-level the
-typedef struct { unsigned long pgprot; } pgprot_t;
+ * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
+ */
+#ifdef CONFIG_64BIT
+typedef struct { unsigned long pmd; } pmd_t;
 #define pmd_val(x)      ((x).pmd)
-#define pgd_val(x)      ((x).pgd)
+#define __pmd(x)        ((pmd_t) { (x) } )
-#define pgprot_val(x)   ((x).pgprot)
-#define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
+#endif
-#define __pte(x)        ((pte_t) { (x) } )
+/*
-#define __pmd(x)        ((pmd_t) { (x) } )
+ * Right now we don't support 4-level pagetables, so all pud-related
+ * definitions come from <asm-generic/pgtable-nopud.h>.
+ */
+/*
+ * Finall the top of the hierarchy, the pgd
+ */
+typedef struct { unsigned long pgd; } pgd_t;
+#define pgd_val(x)      ((x).pgd)
 #define __pgd(x)        ((pgd_t) { (x) } )
+/*
+ * Manipulate page protection bits
+ */
+typedef struct { unsigned long pgprot; } pgprot_t;
+#define pgprot_val(x)   ((x).pgprot)
 #define __pgprot(x)     ((pgprot_t) { (x) } )
+/*
+ * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
+ * pair of pages we only have a single global bit per pair of pages.  When
+ * writing to the TLB make sure we always have the bit set for both pages
+ * or none.  This macro is used to access the `buddy' of the pte we're just
+ * working on.
+ */
+#define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
 #endif /* !__ASSEMBLY__ */
 /* to align the pointer to the (next) page boundary */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c9a00ca1c012..6c9ad8171a77 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -40,6 +40,11 @@ struct pci_controller {
        unsigned int need_domain_info;
        int iommu;
+        /* Optional access methods for reading/writing the bus number
+           of the PCI controller */
+        int (*get_busno)(void);
+        void (*set_busno)(int busno);
 };
 /*
@@ -142,8 +147,22 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 extern void pcibios_resource_to_bus(struct pci_dev *dev,
        struct pci_bus_region *region, struct resource *res);
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-        struct resource *res, struct pci_bus_region *region);
+extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                                    struct pci_bus_region *region);
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        return root;
+}
 #ifdef CONFIG_PCI_DOMAINS
@@ -169,17 +188,4 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 /* Do platform specific device initialization at pci_enable_device() time */
 extern int pcibios_plat_dev_init(struct pci_dev *dev);
-static inline struct resource *
-pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-{
-        struct resource *root = NULL;
-        if (res->flags & IORESOURCE_IO)
-                root = &ioport_resource;
-        if (res->flags & IORESOURCE_MEM)
-                root = &iomem_resource;
-        return root;
-}
 #endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index ce57288d43bd..fe1df572318b 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -26,10 +26,22 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 }
 /*
+ * Initialize a new pmd table with invalid pointers.
+ */
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+#ifdef CONFIG_64BIT
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        set_pud(pud, __pud((unsigned long)pmd));
+}
+#endif
+/*
 * Initialize a new pgd / pmd table with invalid pointers.
 */
 extern void pgd_init(unsigned long page);
-extern void pmd_init(unsigned long page, unsigned long pagetable);
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
@@ -86,21 +98,18 @@ static inline void pte_free(struct page *pte)
 #define __pte_free_tlb(tlb,pte)         tlb_remove_page((tlb),(pte))
 #ifdef CONFIG_32BIT
-#define pgd_populate(mm, pmd, pte)      BUG()
 /*
 * allocating and freeing a pmd is trivial: the 1-entry pmd is
 * inside the pgd, so has no extra memory associated with it.
 */
-#define pmd_alloc_one(mm, addr)         ({ BUG(); ((pmd_t *)2); })
 #define pmd_free(x)                     do { } while (0)
 #define __pmd_free_tlb(tlb,x)           do { } while (0)
 #endif
 #ifdef CONFIG_64BIT
-#define pgd_populate(mm, pgd, pmd)      set_pgd(pgd, __pgd(pmd))
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 {
        pmd_t *pmd;
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 7fec93b76da9..0cff64ce0fb8 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -17,6 +17,8 @@
 #include <asm/cachectl.h>
 #include <asm/fixmap.h>
+#include <asm-generic/pgtable-nopmd.h>
 /*
 * - add_wired_entry() add a fixed TLB entry, and move wired register
 */
@@ -41,42 +43,38 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 * works even with the cache aliasing problem the R4k and above have.
 */
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
 #ifdef CONFIG_64BIT_PHYS_ADDR
-#define PMD_SHIFT       21
+#define PGDIR_SHIFT     21
 #else
-#define PMD_SHIFT       22
+#define PGDIR_SHIFT     22
 #endif
-#define PMD_SIZE        (1UL << PMD_SHIFT)
-#define PMD_MASK        (~(PMD_SIZE-1))
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     PMD_SHIFT
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 /*
 * Entries per page directory level: we use two-level, so
- * we don't really have any PMD directory physically.
+ * we don't really have any PUD/PMD directory physically.
 */
 #ifdef CONFIG_64BIT_PHYS_ADDR
 #define PGD_ORDER       1
-#define PMD_ORDER       0
+#define PUD_ORDER       aieeee_attempt_to_allocate_pud
+#define PMD_ORDER       1
 #define PTE_ORDER       0
 #else
 #define PGD_ORDER       0
-#define PMD_ORDER       0
+#define PUD_ORDER       aieeee_attempt_to_allocate_pud
+#define PMD_ORDER       1
 #define PTE_ORDER       0
 #endif
 #define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
-#define PTRS_PER_PMD    1
 #define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 #define USER_PTRS_PER_PGD       (0x80000000UL/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS      0
-#define VMALLOC_START     KSEG2
+#define VMALLOC_START     MAP_BASE
 #ifdef CONFIG_HIGHMEM
 # define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
@@ -91,8 +89,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 #define pte_ERROR(e) \
        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 #endif
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 #define pgd_ERROR(e) \
        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
@@ -120,17 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp)
        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
 }
-/*
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd)           { return 0; }
-static inline int pgd_bad(pgd_t pgd)            { return 0; }
-static inline int pgd_present(pgd_t pgd)        { return 1; }
-static inline void pgd_clear(pgd_t *pgdp)       { }
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 #define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
 static inline pte_t
@@ -151,27 +137,22 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
 #else
 #define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pte(pfn, prot)      __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #endif
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
 #define __pgd_offset(address)   pgd_index(address)
+#define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
 #define __pmd_offset(address)   (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
-#define pgd_index(address)      ((address) >> PGDIR_SHIFT)
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 /* to find an entry in a page-table-directory */
 #define pgd_offset(mm,addr)     ((mm)->pgd + pgd_index(addr))
-/* Find an entry in the second-level page table.. */
-static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
-{
-        return (pmd_t *) dir;
-}
 /* Find an entry in the third-level page table.. */
 #define __pte_offset(address)                                           \
        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
@@ -221,7 +202,7 @@ static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
 */
 #define PTE_FILE_MAX_BITS       27
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
        /* fixme */
 #define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
 #define pgoff_to_pte(off) \
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 1011e0635f56..82166b254b27 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -16,13 +16,15 @@
 #include <asm/page.h>
 #include <asm/cachectl.h>
+#include <asm-generic/pgtable-nopud.h>
 /*
 * Each address space has 2 4K pages as its page directory, giving 1024
 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
- * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to
+ * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
- * page tables. Each page table is a single 4K page, giving 512 (==
+ * tables. Each page table is also a single 4K page, giving 512 (==
- * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to
+ * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
- * invalid_pmd_table, each pmde is initialized to point to
+ * invalid_pmd_table, each pmd entry is initialized to point to
 * invalid_pte_table, each pte is initialized to 0. When memory is low,
 * and a pmd table or a page table allocation fails, empty_bad_pmd_table
 * and empty_bad_page_table is returned back to higher layer code, so
@@ -36,17 +38,17 @@
 */
 /* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT - 3))
+#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
 #define PMD_SIZE        (1UL << PMD_SHIFT)
 #define PMD_MASK        (~(PMD_SIZE-1))
 /* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     (PMD_SHIFT + (PAGE_SHIFT + 1 - 3))
+#define PGDIR_SHIFT     (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 /*
- * For 4kB page size we use a 3 level page tree and a 8kB pmd and pgds which
+ * For 4kB page size we use a 3 level page tree and an 8kB pud, which
 * permits us mapping 40 bits of virtual address space.
 *
 * We used to implement 41 bits by having an order 1 pmd level but that seemed
@@ -57,7 +59,7 @@
 * two levels would be easy to implement.
 *
 * For 16kB page size we use a 2 level page tree which permits a total of
- * 36 bits of virtual address space.  We could add a third leve. but it seems
+ * 36 bits of virtual address space.  We could add a third level but it seems
 * like at the moment there's no need for this.
 *
 * For 64kB page size we use a 2 level page table tree for a total of 42 bits
@@ -65,21 +67,25 @@
 */
 #ifdef CONFIG_PAGE_SIZE_4KB
 #define PGD_ORDER               1
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
 #define PMD_ORDER               0
 #define PTE_ORDER               0
 #endif
 #ifdef CONFIG_PAGE_SIZE_8KB
 #define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
 #define PMD_ORDER               0
 #define PTE_ORDER               0
 #endif
 #ifdef CONFIG_PAGE_SIZE_16KB
 #define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
 #define PMD_ORDER               0
 #define PTE_ORDER               0
 #endif
 #ifdef CONFIG_PAGE_SIZE_64KB
 #define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
 #define PMD_ORDER               0
 #define PTE_ORDER               0
 #endif
@@ -91,7 +97,7 @@
 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
 #define FIRST_USER_ADDRESS      0
-#define VMALLOC_START           XKSEG
+#define VMALLOC_START           MAP_BASE
 #define VMALLOC_END     \
        (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
@@ -102,13 +108,13 @@
 #define pgd_ERROR(e) \
        printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
-extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
+extern pte_t invalid_pte_table[PTRS_PER_PTE];
-extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)];
+extern pte_t empty_bad_page_table[PTRS_PER_PTE];
-extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
+extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
-extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
+extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
 /*
- * Empty pmd entries point to the invalid_pte_table.
+ * Empty pgd/pmd entries point to the invalid_pte_table.
 */
 static inline int pmd_none(pmd_t pmd)
 {
@@ -128,26 +134,30 @@ static inline void pmd_clear(pmd_t *pmdp)
 }
 /*
- * Empty pgd entries point to the invalid_pmd_table.
+ * Empty pud entries point to the invalid_pmd_table.
 */
-static inline int pgd_none(pgd_t pgd)
+static inline int pud_none(pud_t pud)
 {
-        return pgd_val(pgd) == (unsigned long) invalid_pmd_table;
+        return pud_val(pud) == (unsigned long) invalid_pmd_table;
 }
-#define pgd_bad(pgd)            (pgd_val(pgd) &~ PAGE_MASK)
+static inline int pud_bad(pud_t pud)
+{
+        return pud_val(pud) & ~PAGE_MASK;
+}
-static inline int pgd_present(pgd_t pgd)
+static inline int pud_present(pud_t pud)
 {
-        return pgd_val(pgd) != (unsigned long) invalid_pmd_table;
+        return pud_val(pud) != (unsigned long) invalid_pmd_table;
 }
-static inline void pgd_clear(pgd_t *pgdp)
+static inline void pud_clear(pud_t *pudp)
 {
-        pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table);
+        pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
 }
-#define pte_page(x)             pfn_to_page((unsigned long)((pte_val(x) >> PAGE_SHIFT)))
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
 #ifdef CONFIG_CPU_VR41XX
 #define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
 #define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
@@ -157,26 +167,27 @@ static inline void pgd_clear(pgd_t *pgdp)
 #endif
 #define __pgd_offset(address)   pgd_index(address)
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
+#define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+#define __pmd_offset(address)   pmd_index(address)
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(address) pgd_offset(&init_mm, 0)
-#define pgd_index(address)              ((address) >> PGDIR_SHIFT)
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pmd_index(address)      (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 /* to find an entry in a page-table-directory */
 #define pgd_offset(mm,addr)     ((mm)->pgd + pgd_index(addr))
-static inline unsigned long pgd_page(pgd_t pgd)
+static inline unsigned long pud_page(pud_t pud)
 {
-        return pgd_val(pgd);
+        return pud_val(pud);
 }
 /* Find an entry in the second-level page table.. */
-static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
+static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
 {
-        return (pmd_t *) pgd_page(*dir) +
+        return (pmd_t *) pud_page(*pud) + pmd_index(address);
-               ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 }
 /* Find an entry in the third-level page table.. */
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 3aad751ccd5f..01e76e932e3f 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -33,7 +33,7 @@
 * unpredictable things.  The code (when it is written) to deal with
 * this problem will be in the update_mmu_cache() code for the r4k.
 */
-#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
 #define _PAGE_PRESENT               (1<<6)  /* implemented in software */
 #define _PAGE_READ                  (1<<7)  /* implemented in software */
@@ -123,7 +123,7 @@
 #endif
 #endif
-#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
+#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
 #define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
 #define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -140,7 +140,7 @@
 #define PAGE_CACHABLE_DEFAULT   _CACHE_CACHABLE_COW
 #endif
-#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
 #define CONF_CM_DEFAULT         (PAGE_CACHABLE_DEFAULT >> 3)
 #else
 #define CONF_CM_DEFAULT         (PAGE_CACHABLE_DEFAULT >> 9)
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index eaf5d9b3a0e1..34facd996503 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -8,8 +8,6 @@
 #ifndef _ASM_PGTABLE_H
 #define _ASM_PGTABLE_H
-#include <asm-generic/4level-fixup.h>
 #include <linux/config.h>
 #ifdef CONFIG_32BIT
 #include <asm/pgtable-32.h>
@@ -18,6 +16,7 @@
 #include <asm/pgtable-64.h>
 #endif
+#include <asm/io.h>
 #include <asm/pgtable-bits.h>
 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
@@ -76,7 +75,6 @@ extern void paging_init(void);
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
-#define page_pte(page)          page_pte_prot(page, __pgprot(0))
 #define pmd_phys(pmd)           (pmd_val(pmd) - PAGE_OFFSET)
 #define pmd_page(pmd)           (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
 #define pmd_page_kernel(pmd)    pmd_val(pmd)
@@ -84,7 +82,7 @@ extern void paging_init(void);
 #define pte_none(pte)           (!(pte_val(pte) & ~_PAGE_GLOBAL))
 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 static inline void set_pte(pte_t *ptep, pte_t pte)
 {
        ptep->pte_high = pte.pte_high;
@@ -148,11 +146,18 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
 #endif
 /*
- * (pmds are folded into pgds so this doesn't get actually called,
+ * (pmds are folded into puds so this doesn't get actually called,
 * but the define is needed for a generic inline function.)
 */
 #define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
-#define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0)
+#ifdef CONFIG_64BIT
+/*
+ * (puds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
+#endif
 #define PGD_T_LOG2      ffz(~sizeof(pgd_t))
 #define PMD_T_LOG2      ffz(~sizeof(pmd_t))
@@ -165,7 +170,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 * Undefined behaviour if not..
 */
 static inline int pte_user(pte_t pte)   { BUG(); return 0; }
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 static inline int pte_read(pte_t pte)   { return (pte).pte_low & _PAGE_READ; }
 static inline int pte_write(pte_t pte)  { return (pte).pte_low & _PAGE_WRITE; }
 static inline int pte_dirty(pte_t pte)  { return (pte).pte_low & _PAGE_MODIFIED; }
@@ -324,7 +329,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 */
 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
        pte.pte_low &= _PAGE_CHG_MASK;
@@ -357,7 +362,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 #endif
 #ifdef CONFIG_64BIT_PHYS_ADDR
-extern phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size);
 extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
@@ -367,7 +371,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
                pgprot_t prot)
 {
        phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
-        return remap_pfn_range(vma, vaddr, pfn, size, prot);
+        return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
 }
 #else
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index d6466aa09fb7..f1980c6c3bcc 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -96,12 +96,26 @@ union mips_fpu_union {
        {{0,},} \
 }
+#define NUM_DSP_REGS   6
+typedef __u32 dspreg_t;
+struct mips_dsp_state {
+        dspreg_t        dspr[NUM_DSP_REGS];
+        unsigned int    dspcontrol;
+        unsigned short  used_dsp;
+};
+#define INIT_DSP {{0,},}
 typedef struct {
        unsigned long seg;
 } mm_segment_t;
 #define ARCH_MIN_TASKALIGN      8
+struct mips_abi;
 /*
 * If you change thread_struct remember to change the #defines below too!
 */
@@ -117,6 +131,9 @@ struct thread_struct {
        /* Saved fpu/fpu emulator stuff. */
        union mips_fpu_union fpu;
+        /* Saved state of the DSP ASE, if available. */
+        struct mips_dsp_state dsp;
        /* Other stuff associated with the thread. */
        unsigned long cp0_badvaddr;     /* Last user fault */
        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
@@ -129,6 +146,7 @@ struct thread_struct {
        unsigned long mflags;
        unsigned long irix_trampoline;  /* Wheee... */
        unsigned long irix_oldctx;
+        struct mips_abi *abi;
 };
 #define MF_ABI_MASK     (MF_32BIT_REGS | MF_32BIT_ADDR)
@@ -151,6 +169,10 @@ struct thread_struct {
         */ \
        INIT_FPU, \
        /* \
+         * saved dsp/dsp emulator stuff \
+         */ \
+        INIT_DSP, \
+        /* \
         * Other stuff associated with the process \
         */ \
        0, 0, 0, 0, \
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 2b5c624c3d4f..95c5839ac465 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -22,6 +22,8 @@
 #define MMLO            68
 #define FPC_CSR         69
 #define FPC_EIR         70
+#define DSP_BASE        71              /* 3 more hi / lo register pairs */
+#define DSP_CONTROL     77
 /*
 * This struct defines the way the registers are stored on the stack during a
@@ -38,18 +40,18 @@ struct pt_regs {
        /* Saved special registers. */
        unsigned long cp0_status;
-        unsigned long lo;
        unsigned long hi;
+        unsigned long lo;
        unsigned long cp0_badvaddr;
        unsigned long cp0_cause;
        unsigned long cp0_epc;
 };
 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-/* #define PTRACE_GETREGS               12 */
+#define PTRACE_GETREGS          12
-/* #define PTRACE_SETREGS               13 */
+#define PTRACE_SETREGS          13
-/* #define PTRACE_GETFPREGS             14 */
+#define PTRACE_GETFPREGS                14
-/* #define PTRACE_SETFPREGS             15 */
+#define PTRACE_SETFPREGS                15
 /* #define PTRACE_GETFPXREGS            18 */
 /* #define PTRACE_SETFPXREGS            19 */
@@ -58,6 +60,13 @@ struct pt_regs {
 #define PTRACE_GET_THREAD_AREA  25
 #define PTRACE_SET_THREAD_AREA  26
+/* Calls to trace a 64bit program from a 32bit program.  */
+#define PTRACE_PEEKTEXT_3264    0xc0
+#define PTRACE_PEEKDATA_3264    0xc1
+#define PTRACE_POKETEXT_3264    0xc2
+#define PTRACE_POKEDATA_3264    0xc3
+#define PTRACE_GET_THREAD_AREA_3264     0xc4
 #ifdef __KERNEL__
 #include <linux/linkage.h>
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 5bea49feec66..a5ea9d828aee 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -21,7 +21,7 @@
 *
 *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
 *    the index bits from the virtual address.  This breaks with tradition
- *    set by the R4000.  To keep unpleassant surprises from happening we pick
+ *    set by the R4000.  To keep unpleasant surprises from happening we pick
 *    an address in KSEG0 / CKSEG0.
 *  - We need a properly sign extended address for 64-bit code.  To get away
 *    without ifdefs we let the compiler do it by a type cast.
@@ -30,11 +30,11 @@
 #define cache_op(op,addr)                                               \
        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
        "       .set    noreorder                               \n"     \
        "       .set    mips3\n\t                               \n"     \
        "       cache   %0, %1                                  \n"     \
-        "       .set    mips0                                   \n"     \
+        "       .set    pop                                     \n"     \
-        "       .set    reorder"                                        \
        :                                                               \
        : "i" (op), "m" (*(unsigned char *)(addr)))
@@ -84,14 +84,14 @@ static inline void flush_scache_line(unsigned long addr)
 static inline void protected_flush_icache_line(unsigned long addr)
 {
        __asm__ __volatile__(
-                ".set noreorder\n\t"
+                "       .set    push                    \n"
-                ".set mips3\n"
+                "       .set    noreorder               \n"
-                "1:\tcache %0,(%1)\n"
+                "       .set    mips3                   \n"
-                "2:\t.set mips0\n\t"
+                "1:     cache   %0, (%1)                \n"
-                ".set reorder\n\t"
+                "2:     .set    pop                     \n"
-                ".section\t__ex_table,\"a\"\n\t"
+                "       .section __ex_table,\"a\"       \n"
-                STR(PTR)"\t1b,2b\n\t"
+                "       "STR(PTR)" 1b, 2b               \n"
-                ".previous"
+                "       .previous"
                :
                : "i" (Hit_Invalidate_I), "r" (addr));
 }
@@ -100,19 +100,19 @@ static inline void protected_flush_icache_line(unsigned long addr)
 * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
 * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
 * caches.  We're talking about one cacheline unnecessarily getting invalidated
- * here so the penaltiy isn't overly hard.
+ * here so the penalty isn't overly hard.
 */
 static inline void protected_writeback_dcache_line(unsigned long addr)
 {
        __asm__ __volatile__(
-                ".set noreorder\n\t"
+                "       .set    push                    \n"
-                ".set mips3\n"
+                "       .set    noreorder               \n"
-                "1:\tcache %0,(%1)\n"
+                "       .set    mips3                   \n"
-                "2:\t.set mips0\n\t"
+                "1:     cache   %0, (%1)                \n"
-                ".set reorder\n\t"
+                "2:     .set    pop                     \n"
-                ".section\t__ex_table,\"a\"\n\t"
+                "       .section __ex_table,\"a\"       \n"
-                STR(PTR)"\t1b,2b\n\t"
+                "       "STR(PTR)" 1b, 2b               \n"
-                ".previous"
+                "       .previous"
                :
                : "i" (Hit_Writeback_Inv_D), "r" (addr));
 }
@@ -120,14 +120,14 @@ static inline void protected_writeback_dcache_line(unsigned long addr)
 static inline void protected_writeback_scache_line(unsigned long addr)
 {
        __asm__ __volatile__(
-                ".set noreorder\n\t"
+                "       .set    push                    \n"
-                ".set mips3\n"
+                "       .set    noreorder               \n"
-                "1:\tcache %0,(%1)\n"
+                "       .set    mips3                   \n"
-                "2:\t.set mips0\n\t"
+                "1:     cache   %0, (%1)                \n"
-                ".set reorder\n\t"
+                "2:     .set    pop                     \n"
-                ".section\t__ex_table,\"a\"\n\t"
+                "       .section __ex_table,\"a\"       \n"
-                STR(PTR)"\t1b,2b\n\t"
+                "       "STR(PTR)" 1b, 2b               \n"
-                ".previous"
+                "       .previous"
                :
                : "i" (Hit_Writeback_Inv_SD), "r" (addr));
 }
@@ -142,6 +142,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
 #define cache16_unroll32(base,op)                                       \
        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
        "       .set noreorder                                  \n"     \
        "       .set mips3                                      \n"     \
        "       cache %1, 0x000(%0); cache %1, 0x010(%0)        \n"     \
@@ -160,8 +161,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
        "       cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)        \n"     \
        "       cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)        \n"     \
        "       cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)        \n"     \
-        "       .set mips0                                      \n"     \
+        "       .set pop                                        \n"     \
-        "       .set reorder                                    \n"     \
                :                                                       \
                : "r" (base),                                           \
                  "i" (op));
@@ -285,6 +285,7 @@ static inline void blast_scache16_page_indexed(unsigned long page)
 #define cache32_unroll32(base,op)                                       \
        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
        "       .set noreorder                                  \n"     \
        "       .set mips3                                      \n"     \
        "       cache %1, 0x000(%0); cache %1, 0x020(%0)        \n"     \
@@ -303,8 +304,7 @@ static inline void blast_scache16_page_indexed(unsigned long page)
        "       cache %1, 0x340(%0); cache %1, 0x360(%0)        \n"     \
        "       cache %1, 0x380(%0); cache %1, 0x3a0(%0)        \n"     \
        "       cache %1, 0x3c0(%0); cache %1, 0x3e0(%0)        \n"     \
-        "       .set mips0                                      \n"     \
+        "       .set pop                                        \n"     \
-        "       .set reorder                                    \n"     \
                :                                                       \
                : "r" (base),                                           \
                  "i" (op));
@@ -428,6 +428,7 @@ static inline void blast_scache32_page_indexed(unsigned long page)
 #define cache64_unroll32(base,op)                                       \
        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
        "       .set noreorder                                  \n"     \
        "       .set mips3                                      \n"     \
        "       cache %1, 0x000(%0); cache %1, 0x040(%0)        \n"     \
@@ -446,8 +447,7 @@ static inline void blast_scache32_page_indexed(unsigned long page)
        "       cache %1, 0x680(%0); cache %1, 0x6c0(%0)        \n"     \
        "       cache %1, 0x700(%0); cache %1, 0x740(%0)        \n"     \
        "       cache %1, 0x780(%0); cache %1, 0x7c0(%0)        \n"     \
-        "       .set mips0                                      \n"     \
+        "       .set pop                                        \n"     \
-        "       .set reorder                                    \n"     \
                :                                                       \
                : "r" (base),                                           \
                  "i" (op));
@@ -532,6 +532,7 @@ static inline void blast_scache64_page_indexed(unsigned long page)
 #define cache128_unroll32(base,op)                                      \
        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
        "       .set noreorder                                  \n"     \
        "       .set mips3                                      \n"     \
        "       cache %1, 0x000(%0); cache %1, 0x080(%0)        \n"     \
@@ -550,8 +551,7 @@ static inline void blast_scache64_page_indexed(unsigned long page)
        "       cache %1, 0xd00(%0); cache %1, 0xd80(%0)        \n"     \
        "       cache %1, 0xe00(%0); cache %1, 0xe80(%0)        \n"     \
        "       cache %1, 0xf00(%0); cache %1, 0xf80(%0)        \n"     \
-        "       .set mips0                                      \n"     \
+        "       .set pop                                        \n"     \
-        "       .set reorder                                    \n"     \
                :                                                       \
                : "r" (base),                                           \
                  "i" (op));
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
index 3c4b637fd925..a60e0dc7c9b9 100644
--- a/include/asm-mips/rtc.h
+++ b/include/asm-mips/rtc.h
@@ -14,7 +14,9 @@
 #ifdef __KERNEL__
+#include <linux/spinlock.h>
 #include <linux/rtc.h>
+#include <asm/time.h>
 #define RTC_PIE 0x40            /* periodic interrupt enable */
 #define RTC_AIE 0x20            /* alarm interrupt enable */
@@ -27,11 +29,52 @@
 #define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
 #define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
-unsigned int get_rtc_time(struct rtc_time *time);
+static DEFINE_SPINLOCK(mips_rtc_lock);
-int set_rtc_time(struct rtc_time *time);
-unsigned int get_rtc_ss(void);
-int get_rtc_pll(struct rtc_pll_info *pll);
-int set_rtc_pll(struct rtc_pll_info *pll);
+static inline unsigned int get_rtc_time(struct rtc_time *time)
+{
+        unsigned long nowtime;
+        spin_lock(&mips_rtc_lock);
+        nowtime = rtc_get_time();
+        to_tm(nowtime, time);
+        time->tm_year -= 1900;
+        spin_unlock(&mips_rtc_lock);
+        return RTC_24H;
+}
+static inline int set_rtc_time(struct rtc_time *time)
+{
+        unsigned long nowtime;
+        int ret;
+        spin_lock(&mips_rtc_lock);
+        nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
+                        time->tm_mday, time->tm_hour, time->tm_min,
+                        time->tm_sec);
+        ret = rtc_set_time(nowtime);
+        spin_unlock(&mips_rtc_lock);
+        return ret;
+}
+static inline unsigned int get_rtc_ss(void)
+{
+        struct rtc_time h;
+        get_rtc_time(&h);
+        return h.tm_sec;
+}
+static inline int get_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+static inline int set_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
 #endif
 #endif
diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h
new file mode 100644
index 000000000000..83cdf6ab0d1f
--- /dev/null
+++ b/include/asm-mips/rtlx.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ */
+#ifndef _RTLX_H
+#define _RTLX_H_
+#define LX_NODE_BASE 10
+#define MIPSCPU_INT_BASE       16
+#define MIPS_CPU_RTLX_IRQ 0
+#define RTLX_VERSION 1
+#define RTLX_xID 0x12345600
+#define RTLX_ID (RTLX_xID | RTLX_VERSION)
+#define RTLX_CHANNELS 8
+enum rtlx_state {
+        RTLX_STATE_UNUSED = 0,
+        RTLX_STATE_INITIALISED,
+        RTLX_STATE_REMOTE_READY,
+        RTLX_STATE_OPENED
+};
+#define RTLX_BUFFER_SIZE 1024
+/* each channel supports read and write.
+   linux (vpe0) reads lx_buffer  and writes rt_buffer
+   SP (vpe1) reads rt_buffer and writes lx_buffer
+*/
+typedef struct rtlx_channel {
+        enum rtlx_state rt_state;
+        enum rtlx_state lx_state;
+        int buffer_size;
+        /* read and write indexes per buffer */
+        int rt_write, rt_read;
+        char *rt_buffer;
+        int lx_write, lx_read;
+        char *lx_buffer;
+        void *queues;
+} rtlx_channel_t;
+typedef struct rtlx_info {
+        unsigned long id;
+        enum rtlx_state state;
+        struct rtlx_channel channel[RTLX_CHANNELS];
+} rtlx_info_t;
+#endif
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
index c2c97dec661b..3d6aa7c7ea81 100644
--- a/include/asm-mips/semaphore.h
+++ b/include/asm-mips/semaphore.h
@@ -45,9 +45,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name, 1)
 #define __DECLARE_SEMAPHORE_GENERIC(name, count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 4eed8e2acdc3..e796d75f027e 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -52,16 +52,6 @@
 #define JAZZ_SERIAL_PORT_DEFNS
 #endif
-#ifdef CONFIG_MIPS_COBALT
-#include <asm/cobalt/cobalt.h>
-#define COBALT_BASE_BAUD  (18432000 / 16)
-#define COBALT_SERIAL_PORT_DEFNS                \
-        /* UART CLK   PORT  IRQ  FLAGS    */            \
-        { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS },   /* ttyS0 */
-#else
-#define COBALT_SERIAL_PORT_DEFNS
-#endif
 /*
 * Both Galileo boards have the same UART mappings.
 */
@@ -113,17 +103,6 @@
 #define IVR_SERIAL_PORT_DEFNS
 #endif
-#ifdef CONFIG_TOSHIBA_JMR3927
-#include <asm/jmr3927/jmr3927.h>
-#define TXX927_SERIAL_PORT_DEFNS                              \
-    { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT,  \
-      .flags = UART0_FLAGS, .type = 1 },                        \
-    { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT,  \
-      .flags = UART1_FLAGS, .type = 1 },
-#else
-#define TXX927_SERIAL_PORT_DEFNS
-#endif
 #ifdef CONFIG_SERIAL_AU1X00
 #include <asm/mach-au1x00/au1000.h>
 #ifdef CONFIG_SOC_AU1000
@@ -227,9 +206,9 @@
 #define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
 #define _JAGUAR_ATX_SERIAL_INIT(int, base)                              \
-        { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int,                    \
+        { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int,                  \
-          flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),               \
+          .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),             \
-          iomem_base: (u8 *) base, iomem_reg_shift: 2,                  \
+          .iomem_base = (u8 *) base, iomem_reg_shift: 2,                        \
          io_type: SERIAL_IO_MEM }
 #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS                            \
        _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
@@ -243,9 +222,9 @@
 #define OCELOT_3_SERIAL_BASE    (signed)0xfd000020
 #define _OCELOT_3_SERIAL_INIT(int, base)                                \
-        { baud_base: OCELOT_3_BASE_BAUD, irq: int,                      \
+        { .baud_base = OCELOT_3_BASE_BAUD, irq: int,                    \
-          flags: STD_COM_FLAGS,                                         \
+          .flags = STD_COM_FLAGS,                                               \
-          iomem_base: (u8 *) base, iomem_reg_shift: 2,                  \
+          .iomem_base = (u8 *) base, iomem_reg_shift: 2,                        \
          io_type: SERIAL_IO_MEM }
 #define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS                              \
@@ -342,7 +321,6 @@
 #endif /* CONFIG_SGI_IP32 */
 #define SERIAL_PORT_DFNS                                \
-        COBALT_SERIAL_PORT_DEFNS                        \
        DDB5477_SERIAL_PORT_DEFNS                       \
        EV96100_SERIAL_PORT_DEFNS                       \
        IP32_SERIAL_PORT_DEFNS                          \
@@ -354,7 +332,6 @@
        MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS              \
        MOMENCO_OCELOT_SERIAL_PORT_DEFNS                \
        MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS              \
-        TXX927_SERIAL_PORT_DEFNS                        \
        AU1000_SERIAL_PORT_DEFNS
 #endif /* _ASM_SERIAL_H */
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
new file mode 100644
index 000000000000..42d4cf00efd3
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_int.h
@@ -0,0 +1,310 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  Interrupt Mapper definitions             File: bcm1480_int.h
+    *
+    *  This module contains constants for manipulating the
+    *  BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
+    *  definitions for the interrupt sources.
+    *
+    *  BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+#ifndef _BCM1480_INT_H
+#define _BCM1480_INT_H
+#include "sb1250_defs.h"
+/*  *********************************************************************
+    *  Interrupt Mapper Constants
+    ********************************************************************* */
+/*
+ * The interrupt mapper deals with 128-bit logical registers that are
+ * implemented as pairs of 64-bit registers, with the "low" 64 bits in
+ * a register that has an address 0x1000 higher(!) than the
+ * corresponding "high" register.
+ *
+ * For appropriate registers, bit 0 of the "high" register is a
+ * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
+ * register.
+ */
+/*
+ * This entire file uses _BCM1480_ in all the symbols because it is
+ * entirely BCM1480 specific.
+ */
+/*
+ * Interrupt sources (Table 22)
+ */
+#define K_BCM1480_INT_SOURCES               128
+#define _BCM1480_INT_HIGH(k)   (k)
+#define _BCM1480_INT_LOW(k)    ((k)+64)
+#define K_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_HIGH(1)
+#define K_BCM1480_INT_GPIO_0                _BCM1480_INT_HIGH(4)
+#define K_BCM1480_INT_GPIO_1                _BCM1480_INT_HIGH(5)
+#define K_BCM1480_INT_GPIO_2                _BCM1480_INT_HIGH(6)
+#define K_BCM1480_INT_GPIO_3                _BCM1480_INT_HIGH(7)
+#define K_BCM1480_INT_PCI_INTA              _BCM1480_INT_HIGH(8)
+#define K_BCM1480_INT_PCI_INTB              _BCM1480_INT_HIGH(9)
+#define K_BCM1480_INT_PCI_INTC              _BCM1480_INT_HIGH(10)
+#define K_BCM1480_INT_PCI_INTD              _BCM1480_INT_HIGH(11)
+#define K_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_HIGH(12)
+#define K_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_HIGH(13)
+#define K_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_HIGH(14)
+#define K_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_HIGH(15)
+#define K_BCM1480_INT_TIMER_0               _BCM1480_INT_HIGH(20)
+#define K_BCM1480_INT_TIMER_1               _BCM1480_INT_HIGH(21)
+#define K_BCM1480_INT_TIMER_2               _BCM1480_INT_HIGH(22)
+#define K_BCM1480_INT_TIMER_3               _BCM1480_INT_HIGH(23)
+#define K_BCM1480_INT_DM_CH_0               _BCM1480_INT_HIGH(28)
+#define K_BCM1480_INT_DM_CH_1               _BCM1480_INT_HIGH(29)
+#define K_BCM1480_INT_DM_CH_2               _BCM1480_INT_HIGH(30)
+#define K_BCM1480_INT_DM_CH_3               _BCM1480_INT_HIGH(31)
+#define K_BCM1480_INT_MAC_0                 _BCM1480_INT_HIGH(36)
+#define K_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_HIGH(37)
+#define K_BCM1480_INT_MAC_1                 _BCM1480_INT_HIGH(38)
+#define K_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_HIGH(39)
+#define K_BCM1480_INT_MAC_2                 _BCM1480_INT_HIGH(40)
+#define K_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_HIGH(41)
+#define K_BCM1480_INT_MAC_3                 _BCM1480_INT_HIGH(42)
+#define K_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_HIGH(43)
+#define K_BCM1480_INT_PMI_LOW               _BCM1480_INT_HIGH(52)
+#define K_BCM1480_INT_PMI_HIGH              _BCM1480_INT_HIGH(53)
+#define K_BCM1480_INT_PMO_LOW               _BCM1480_INT_HIGH(54)
+#define K_BCM1480_INT_PMO_HIGH              _BCM1480_INT_HIGH(55)
+#define K_BCM1480_INT_MBOX_0_0              _BCM1480_INT_HIGH(56)
+#define K_BCM1480_INT_MBOX_0_1              _BCM1480_INT_HIGH(57)
+#define K_BCM1480_INT_MBOX_0_2              _BCM1480_INT_HIGH(58)
+#define K_BCM1480_INT_MBOX_0_3              _BCM1480_INT_HIGH(59)
+#define K_BCM1480_INT_MBOX_1_0              _BCM1480_INT_HIGH(60)
+#define K_BCM1480_INT_MBOX_1_1              _BCM1480_INT_HIGH(61)
+#define K_BCM1480_INT_MBOX_1_2              _BCM1480_INT_HIGH(62)
+#define K_BCM1480_INT_MBOX_1_3              _BCM1480_INT_HIGH(63)
+#define K_BCM1480_INT_BAD_ECC               _BCM1480_INT_LOW(1)
+#define K_BCM1480_INT_COR_ECC               _BCM1480_INT_LOW(2)
+#define K_BCM1480_INT_IO_BUS                _BCM1480_INT_LOW(3)
+#define K_BCM1480_INT_PERF_CNT              _BCM1480_INT_LOW(4)
+#define K_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_LOW(5)
+#define K_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_LOW(6)
+#define K_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_LOW(7)
+#define K_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_LOW(8)
+#define K_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_LOW(9)
+#define K_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_LOW(10)
+#define K_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_LOW(11)
+#define K_BCM1480_INT_PCI_ERROR             _BCM1480_INT_LOW(16)
+#define K_BCM1480_INT_PCI_RESET             _BCM1480_INT_LOW(17)
+#define K_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_LOW(18)
+#define K_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_LOW(19)
+#define K_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_LOW(20)
+#define K_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_LOW(21)
+#define K_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_LOW(22)
+#define K_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_LOW(23)
+#define K_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_LOW(24)
+#define K_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_LOW(25)
+#define K_BCM1480_INT_LDT_SMI               _BCM1480_INT_LOW(32)
+#define K_BCM1480_INT_LDT_NMI               _BCM1480_INT_LOW(33)
+#define K_BCM1480_INT_LDT_INIT              _BCM1480_INT_LOW(34)
+#define K_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_LOW(35)
+#define K_BCM1480_INT_LDT_EXT               _BCM1480_INT_LOW(36)
+#define K_BCM1480_INT_SMB_0                 _BCM1480_INT_LOW(40)
+#define K_BCM1480_INT_SMB_1                 _BCM1480_INT_LOW(41)
+#define K_BCM1480_INT_PCMCIA                _BCM1480_INT_LOW(42)
+#define K_BCM1480_INT_UART_0                _BCM1480_INT_LOW(44)
+#define K_BCM1480_INT_UART_1                _BCM1480_INT_LOW(45)
+#define K_BCM1480_INT_UART_2                _BCM1480_INT_LOW(46)
+#define K_BCM1480_INT_UART_3                _BCM1480_INT_LOW(47)
+#define K_BCM1480_INT_GPIO_4                _BCM1480_INT_LOW(52)
+#define K_BCM1480_INT_GPIO_5                _BCM1480_INT_LOW(53)
+#define K_BCM1480_INT_GPIO_6                _BCM1480_INT_LOW(54)
+#define K_BCM1480_INT_GPIO_7                _BCM1480_INT_LOW(55)
+#define K_BCM1480_INT_GPIO_8                _BCM1480_INT_LOW(56)
+#define K_BCM1480_INT_GPIO_9                _BCM1480_INT_LOW(57)
+#define K_BCM1480_INT_GPIO_10               _BCM1480_INT_LOW(58)
+#define K_BCM1480_INT_GPIO_11               _BCM1480_INT_LOW(59)
+#define K_BCM1480_INT_GPIO_12               _BCM1480_INT_LOW(60)
+#define K_BCM1480_INT_GPIO_13               _BCM1480_INT_LOW(61)
+#define K_BCM1480_INT_GPIO_14               _BCM1480_INT_LOW(62)
+#define K_BCM1480_INT_GPIO_15               _BCM1480_INT_LOW(63)
+/*
+ * Mask values for each interrupt
+ */
+#define _BCM1480_INT_MASK1(n)               _SB_MAKEMASK1(((n) & 0x3F))
+#define _BCM1480_INT_OFFSET(n)              (((n) & 0x40) << 6)
+#define M_BCM1480_INT_CASCADE               _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
+#define M_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
+#define M_BCM1480_INT_GPIO_0                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
+#define M_BCM1480_INT_GPIO_1                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
+#define M_BCM1480_INT_GPIO_2                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
+#define M_BCM1480_INT_GPIO_3                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
+#define M_BCM1480_INT_PCI_INTA              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
+#define M_BCM1480_INT_PCI_INTB              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
+#define M_BCM1480_INT_PCI_INTC              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
+#define M_BCM1480_INT_PCI_INTD              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
+#define M_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
+#define M_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
+#define M_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
+#define M_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
+#define M_BCM1480_INT_TIMER_0               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
+#define M_BCM1480_INT_TIMER_1               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
+#define M_BCM1480_INT_TIMER_2               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
+#define M_BCM1480_INT_TIMER_3               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
+#define M_BCM1480_INT_DM_CH_0               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
+#define M_BCM1480_INT_DM_CH_1               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
+#define M_BCM1480_INT_DM_CH_2               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
+#define M_BCM1480_INT_DM_CH_3               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
+#define M_BCM1480_INT_MAC_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
+#define M_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
+#define M_BCM1480_INT_MAC_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
+#define M_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
+#define M_BCM1480_INT_MAC_2                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
+#define M_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
+#define M_BCM1480_INT_MAC_3                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
+#define M_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
+#define M_BCM1480_INT_PMI_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
+#define M_BCM1480_INT_PMI_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
+#define M_BCM1480_INT_PMO_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
+#define M_BCM1480_INT_PMO_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
+#define M_BCM1480_INT_MBOX_0_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
+#define M_BCM1480_INT_MBOX_0_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
+#define M_BCM1480_INT_MBOX_0_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
+#define M_BCM1480_INT_MBOX_0_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
+#define M_BCM1480_INT_MBOX_1_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
+#define M_BCM1480_INT_MBOX_1_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
+#define M_BCM1480_INT_MBOX_1_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
+#define M_BCM1480_INT_MBOX_1_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
+#define M_BCM1480_INT_BAD_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
+#define M_BCM1480_INT_COR_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
+#define M_BCM1480_INT_IO_BUS                _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
+#define M_BCM1480_INT_PERF_CNT              _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
+#define M_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
+#define M_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
+#define M_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
+#define M_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
+#define M_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
+#define M_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
+#define M_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
+#define M_BCM1480_INT_PCI_ERROR             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
+#define M_BCM1480_INT_PCI_RESET             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
+#define M_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
+#define M_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
+#define M_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
+#define M_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
+#define M_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
+#define M_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
+#define M_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
+#define M_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
+#define M_BCM1480_INT_LDT_SMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
+#define M_BCM1480_INT_LDT_NMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
+#define M_BCM1480_INT_LDT_INIT              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
+#define M_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
+#define M_BCM1480_INT_LDT_EXT               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
+#define M_BCM1480_INT_SMB_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
+#define M_BCM1480_INT_SMB_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
+#define M_BCM1480_INT_PCMCIA                _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
+#define M_BCM1480_INT_UART_0                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
+#define M_BCM1480_INT_UART_1                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
+#define M_BCM1480_INT_UART_2                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
+#define M_BCM1480_INT_UART_3                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
+#define M_BCM1480_INT_GPIO_4                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
+#define M_BCM1480_INT_GPIO_5                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
+#define M_BCM1480_INT_GPIO_6                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
+#define M_BCM1480_INT_GPIO_7                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
+#define M_BCM1480_INT_GPIO_8                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
+#define M_BCM1480_INT_GPIO_9                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
+#define M_BCM1480_INT_GPIO_10               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
+#define M_BCM1480_INT_GPIO_11               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
+#define M_BCM1480_INT_GPIO_12               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
+#define M_BCM1480_INT_GPIO_13               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
+#define M_BCM1480_INT_GPIO_14               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
+#define M_BCM1480_INT_GPIO_15               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
+/*
+ * Interrupt mappings (Table 18)
+ */
+#define K_BCM1480_INT_MAP_I0    0               /* interrupt pins on processor */
+#define K_BCM1480_INT_MAP_I1    1
+#define K_BCM1480_INT_MAP_I2    2
+#define K_BCM1480_INT_MAP_I3    3
+#define K_BCM1480_INT_MAP_I4    4
+#define K_BCM1480_INT_MAP_I5    5
+#define K_BCM1480_INT_MAP_NMI   6               /* nonmaskable */
+#define K_BCM1480_INT_MAP_DINT  7               /* debug interrupt */
+/*
+ * Interrupt LDT Set Register (Table 19)
+ */
+#define S_BCM1480_INT_HT_INTMSG             0
+#define M_BCM1480_INT_HT_INTMSG             _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG)
+#define V_BCM1480_INT_HT_INTMSG(x)          _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG)
+#define G_BCM1480_INT_HT_INTMSG(x)          _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG)
+#define K_BCM1480_INT_HT_INTMSG_FIXED       0
+#define K_BCM1480_INT_HT_INTMSG_ARBITRATED  1
+#define K_BCM1480_INT_HT_INTMSG_SMI         2
+#define K_BCM1480_INT_HT_INTMSG_NMI         3
+#define K_BCM1480_INT_HT_INTMSG_INIT        4
+#define K_BCM1480_INT_HT_INTMSG_STARTUP     5
+#define K_BCM1480_INT_HT_INTMSG_EXTINT      6
+#define K_BCM1480_INT_HT_INTMSG_RESERVED    7
+#define M_BCM1480_INT_HT_TRIGGERMODE        _SB_MAKEMASK1(3)
+#define V_BCM1480_INT_HT_EDGETRIGGER        0
+#define V_BCM1480_INT_HT_LEVELTRIGGER       M_BCM1480_INT_HT_TRIGGERMODE
+#define M_BCM1480_INT_HT_DESTMODE           _SB_MAKEMASK1(4)
+#define V_BCM1480_INT_HT_PHYSICALDEST       0
+#define V_BCM1480_INT_HT_LOGICALDEST        M_BCM1480_INT_HT_DESTMODE
+#define S_BCM1480_INT_HT_INTDEST            5
+#define M_BCM1480_INT_HT_INTDEST            _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST)
+#define V_BCM1480_INT_HT_INTDEST(x)         _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST)
+#define G_BCM1480_INT_HT_INTDEST(x)         _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST)
+#define S_BCM1480_INT_HT_VECTOR             13
+#define M_BCM1480_INT_HT_VECTOR             _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR)
+#define V_BCM1480_INT_HT_VECTOR(x)          _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR)
+#define G_BCM1480_INT_HT_VECTOR(x)          _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR)
+/*
+ * Vector prefix (Table 4-7)
+ */
+#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH  0x00
+#define M_BCM1480_HTVECT_RAISE_MBOX_0       0x40
+#define M_BCM1480_HTVECT_RAISE_INTLDT_LO    0x80
+#define M_BCM1480_HTVECT_RAISE_MBOX_1       0xC0
+#endif /* _BCM1480_INT_H */
diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h
new file mode 100644
index 000000000000..886b099565e6
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_l2c.h
@@ -0,0 +1,176 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  L2 Cache constants and macros            File: bcm1480_l2c.h
+    *
+    *  This module contains constants useful for manipulating the
+    *  level 2 cache.
+    *
+    *  BCM1400 specification level:  1280-UM100-D2 (11/14/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+#ifndef _BCM1480_L2C_H
+#define _BCM1480_L2C_H
+#include "sb1250_defs.h"
+/*
+ * Format of level 2 cache management address (Table 55)
+ */
+#define S_BCM1480_L2C_MGMT_INDEX            5
+#define M_BCM1480_L2C_MGMT_INDEX            _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX)
+#define V_BCM1480_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX)
+#define G_BCM1480_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX)
+#define S_BCM1480_L2C_MGMT_WAY              17
+#define M_BCM1480_L2C_MGMT_WAY              _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY)
+#define V_BCM1480_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY)
+#define G_BCM1480_L2C_MGMT_WAY(x)           _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY)
+#define M_BCM1480_L2C_MGMT_DIRTY            _SB_MAKEMASK1(20)
+#define M_BCM1480_L2C_MGMT_VALID            _SB_MAKEMASK1(21)
+#define S_BCM1480_L2C_MGMT_ECC_DIAG         22
+#define M_BCM1480_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define V_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define G_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG)
+#define A_BCM1480_L2C_MGMT_TAG_BASE         0x00D0000000
+#define BCM1480_L2C_ENTRIES_PER_WAY         4096
+#define BCM1480_L2C_NUM_WAYS                8
+/*
+ * Level 2 Cache Tag register (Table 59)
+ */
+#define S_BCM1480_L2C_TAG_MBZ               0
+#define M_BCM1480_L2C_TAG_MBZ               _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ)
+#define S_BCM1480_L2C_TAG_INDEX             5
+#define M_BCM1480_L2C_TAG_INDEX             _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX)
+#define V_BCM1480_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX)
+#define G_BCM1480_L2C_TAG_INDEX(x)          _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX)
+/* Note that index bit 16 is also tag bit 40 */
+#define S_BCM1480_L2C_TAG_TAG               17
+#define M_BCM1480_L2C_TAG_TAG               _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG)
+#define V_BCM1480_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG)
+#define G_BCM1480_L2C_TAG_TAG(x)            _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG)
+#define S_BCM1480_L2C_TAG_ECC               40
+#define M_BCM1480_L2C_TAG_ECC               _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC)
+#define V_BCM1480_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC)
+#define G_BCM1480_L2C_TAG_ECC(x)            _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC)
+#define S_BCM1480_L2C_TAG_WAY               46
+#define M_BCM1480_L2C_TAG_WAY               _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY)
+#define V_BCM1480_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY)
+#define G_BCM1480_L2C_TAG_WAY(x)            _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY)
+#define M_BCM1480_L2C_TAG_DIRTY             _SB_MAKEMASK1(49)
+#define M_BCM1480_L2C_TAG_VALID             _SB_MAKEMASK1(50)
+#define S_BCM1480_L2C_DATA_ECC              51
+#define M_BCM1480_L2C_DATA_ECC              _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC)
+#define V_BCM1480_L2C_DATA_ECC(x)           _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC)
+#define G_BCM1480_L2C_DATA_ECC(x)           _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC)
+/*
+ * L2 Misc0 Value Register (Table 60)
+ */
+#define S_BCM1480_L2C_MISC0_WAY_REMOTE      0
+#define M_BCM1480_L2C_MISC0_WAY_REMOTE      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE)
+#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE)
+#define S_BCM1480_L2C_MISC0_WAY_LOCAL       8
+#define M_BCM1480_L2C_MISC0_WAY_LOCAL       _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL)
+#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x)    _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL)
+#define S_BCM1480_L2C_MISC0_WAY_ENABLE      16
+#define M_BCM1480_L2C_MISC0_WAY_ENABLE      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE)
+#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE)
+#define S_BCM1480_L2C_MISC0_CACHE_DISABLE   24
+#define M_BCM1480_L2C_MISC0_CACHE_DISABLE   _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE)
+#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE)
+#define S_BCM1480_L2C_MISC0_CACHE_QUAD      26
+#define M_BCM1480_L2C_MISC0_CACHE_QUAD      _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD)
+#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD)
+#define S_BCM1480_L2C_MISC0_MC_PRIORITY      30
+#define M_BCM1480_L2C_MISC0_MC_PRIORITY      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
+#define S_BCM1480_L2C_MISC0_ECC_CLEANUP      31
+#define M_BCM1480_L2C_MISC0_ECC_CLEANUP      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
+/*
+ * L2 Misc1 Value Register (Table 60)
+ */
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_0      0
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_0      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_1      8
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_1      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_2      16
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_2      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_3      24
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_3      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_4      32
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_4      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4)
+/*
+ * L2 Misc2 Value Register (Table 60)
+ */
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_8      0
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_8      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8)
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_9      8
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_9      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9)
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_A      16
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_A      _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x)   _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A)
+#endif /* _BCM1480_L2C_H */
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h
new file mode 100644
index 000000000000..6bdc941afc91
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_mc.h
@@ -0,0 +1,962 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  Memory Controller constants              File: bcm1480_mc.h
+    *
+    *  This module contains constants and macros useful for
+    *  programming the memory controller.
+    *
+    *  BCM1400 specification level:  1280-UM100-D1 (11/14/03 Review Copy)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+#ifndef _BCM1480_MC_H
+#define _BCM1480_MC_H
+#include "sb1250_defs.h"
+/*
+ * Memory Channel Configuration Register (Table 81)
+ */
+#define S_BCM1480_MC_INTLV0                 0
+#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0_DEFAULT         V_BCM1480_MC_INTLV0(0)
+#define S_BCM1480_MC_INTLV1                 8
+#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1_DEFAULT         V_BCM1480_MC_INTLV1(0)
+#define S_BCM1480_MC_INTLV2                 16
+#define M_BCM1480_MC_INTLV2                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2)
+#define G_BCM1480_MC_INTLV2(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2_DEFAULT         V_BCM1480_MC_INTLV2(0)
+#define S_BCM1480_MC_CS_MODE                32
+#define M_BCM1480_MC_CS_MODE                _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE)
+#define G_BCM1480_MC_CS_MODE(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE_DEFAULT        V_BCM1480_MC_CS_MODE(0)
+#define V_BCM1480_MC_CONFIG_DEFAULT         (V_BCM1480_MC_INTLV0_DEFAULT  | \
+                                     V_BCM1480_MC_INTLV1_DEFAULT  | \
+                                     V_BCM1480_MC_INTLV2_DEFAULT  | \
+                                     V_BCM1480_MC_CS_MODE_DEFAULT)
+#define K_BCM1480_MC_CS01_MODE              0x03
+#define K_BCM1480_MC_CS02_MODE              0x05
+#define K_BCM1480_MC_CS0123_MODE            0x0F
+#define K_BCM1480_MC_CS0246_MODE            0x55
+#define K_BCM1480_MC_CS0145_MODE            0x33
+#define K_BCM1480_MC_CS0167_MODE            0xC3
+#define K_BCM1480_MC_CSFULL_MODE            0xFF
+/*
+ * Chip Select Start Address Register (Table 82)
+ */
+#define S_BCM1480_MC_CS0_START              0
+#define M_BCM1480_MC_CS0_START              _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START)
+#define V_BCM1480_MC_CS0_START(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START)
+#define G_BCM1480_MC_CS0_START(x)           _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START)
+#define S_BCM1480_MC_CS1_START              16
+#define M_BCM1480_MC_CS1_START              _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START)
+#define V_BCM1480_MC_CS1_START(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START)
+#define G_BCM1480_MC_CS1_START(x)           _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START)
+#define S_BCM1480_MC_CS2_START              32
+#define M_BCM1480_MC_CS2_START              _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START)
+#define V_BCM1480_MC_CS2_START(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START)
+#define G_BCM1480_MC_CS2_START(x)           _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START)
+#define S_BCM1480_MC_CS3_START              48
+#define M_BCM1480_MC_CS3_START              _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START)
+#define V_BCM1480_MC_CS3_START(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START)
+#define G_BCM1480_MC_CS3_START(x)           _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START)
+/*
+ * Chip Select End Address Register (Table 83)
+ */
+#define S_BCM1480_MC_CS0_END                0
+#define M_BCM1480_MC_CS0_END                _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END)
+#define V_BCM1480_MC_CS0_END(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END)
+#define G_BCM1480_MC_CS0_END(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END)
+#define S_BCM1480_MC_CS1_END                16
+#define M_BCM1480_MC_CS1_END                _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END)
+#define V_BCM1480_MC_CS1_END(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END)
+#define G_BCM1480_MC_CS1_END(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END)
+#define S_BCM1480_MC_CS2_END                32
+#define M_BCM1480_MC_CS2_END                _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END)
+#define V_BCM1480_MC_CS2_END(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END)
+#define G_BCM1480_MC_CS2_END(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END)
+#define S_BCM1480_MC_CS3_END                48
+#define M_BCM1480_MC_CS3_END                _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END)
+#define V_BCM1480_MC_CS3_END(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END)
+#define G_BCM1480_MC_CS3_END(x)             _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END)
+/*
+ * Row Address Bit Select Register 0 (Table 84)
+ */
+#define S_BCM1480_MC_ROW00                  0
+#define M_BCM1480_MC_ROW00                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW00)
+#define V_BCM1480_MC_ROW00(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00)
+#define G_BCM1480_MC_ROW00(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00)
+#define S_BCM1480_MC_ROW01                  8
+#define M_BCM1480_MC_ROW01                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW01)
+#define V_BCM1480_MC_ROW01(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01)
+#define G_BCM1480_MC_ROW01(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01)
+#define S_BCM1480_MC_ROW02                  16
+#define M_BCM1480_MC_ROW02                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW02)
+#define V_BCM1480_MC_ROW02(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02)
+#define G_BCM1480_MC_ROW02(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02)
+#define S_BCM1480_MC_ROW03                  24
+#define M_BCM1480_MC_ROW03                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW03)
+#define V_BCM1480_MC_ROW03(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03)
+#define G_BCM1480_MC_ROW03(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03)
+#define S_BCM1480_MC_ROW04                  32
+#define M_BCM1480_MC_ROW04                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW04)
+#define V_BCM1480_MC_ROW04(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04)
+#define G_BCM1480_MC_ROW04(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04)
+#define S_BCM1480_MC_ROW05                  40
+#define M_BCM1480_MC_ROW05                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW05)
+#define V_BCM1480_MC_ROW05(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05)
+#define G_BCM1480_MC_ROW05(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05)
+#define S_BCM1480_MC_ROW06                  48
+#define M_BCM1480_MC_ROW06                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW06)
+#define V_BCM1480_MC_ROW06(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06)
+#define G_BCM1480_MC_ROW06(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06)
+#define S_BCM1480_MC_ROW07                  56
+#define M_BCM1480_MC_ROW07                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW07)
+#define V_BCM1480_MC_ROW07(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07)
+#define G_BCM1480_MC_ROW07(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07)
+/*
+ * Row Address Bit Select Register 1 (Table 85)
+ */
+#define S_BCM1480_MC_ROW08                  0
+#define M_BCM1480_MC_ROW08                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW08)
+#define V_BCM1480_MC_ROW08(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08)
+#define G_BCM1480_MC_ROW08(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08)
+#define S_BCM1480_MC_ROW09                  8
+#define M_BCM1480_MC_ROW09                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW09)
+#define V_BCM1480_MC_ROW09(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09)
+#define G_BCM1480_MC_ROW09(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09)
+#define S_BCM1480_MC_ROW10                  16
+#define M_BCM1480_MC_ROW10                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW10)
+#define V_BCM1480_MC_ROW10(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10)
+#define G_BCM1480_MC_ROW10(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10)
+#define S_BCM1480_MC_ROW11                  24
+#define M_BCM1480_MC_ROW11                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW11)
+#define V_BCM1480_MC_ROW11(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11)
+#define G_BCM1480_MC_ROW11(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11)
+#define S_BCM1480_MC_ROW12                  32
+#define M_BCM1480_MC_ROW12                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW12)
+#define V_BCM1480_MC_ROW12(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12)
+#define G_BCM1480_MC_ROW12(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12)
+#define S_BCM1480_MC_ROW13                  40
+#define M_BCM1480_MC_ROW13                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW13)
+#define V_BCM1480_MC_ROW13(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13)
+#define G_BCM1480_MC_ROW13(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13)
+#define S_BCM1480_MC_ROW14                  48
+#define M_BCM1480_MC_ROW14                  _SB_MAKEMASK(6,S_BCM1480_MC_ROW14)
+#define V_BCM1480_MC_ROW14(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14)
+#define G_BCM1480_MC_ROW14(x)               _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14)
+#define K_BCM1480_MC_ROWX_BIT_SPACING       8
+/*
+ * Column Address Bit Select Register 0 (Table 86)
+ */
+#define S_BCM1480_MC_COL00                  0
+#define M_BCM1480_MC_COL00                  _SB_MAKEMASK(6,S_BCM1480_MC_COL00)
+#define V_BCM1480_MC_COL00(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL00)
+#define G_BCM1480_MC_COL00(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00)
+#define S_BCM1480_MC_COL01                  8
+#define M_BCM1480_MC_COL01                  _SB_MAKEMASK(6,S_BCM1480_MC_COL01)
+#define V_BCM1480_MC_COL01(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL01)
+#define G_BCM1480_MC_COL01(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01)
+#define S_BCM1480_MC_COL02                  16
+#define M_BCM1480_MC_COL02                  _SB_MAKEMASK(6,S_BCM1480_MC_COL02)
+#define V_BCM1480_MC_COL02(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL02)
+#define G_BCM1480_MC_COL02(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02)
+#define S_BCM1480_MC_COL03                  24
+#define M_BCM1480_MC_COL03                  _SB_MAKEMASK(6,S_BCM1480_MC_COL03)
+#define V_BCM1480_MC_COL03(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL03)
+#define G_BCM1480_MC_COL03(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03)
+#define S_BCM1480_MC_COL04                  32
+#define M_BCM1480_MC_COL04                  _SB_MAKEMASK(6,S_BCM1480_MC_COL04)
+#define V_BCM1480_MC_COL04(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL04)
+#define G_BCM1480_MC_COL04(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04)
+#define S_BCM1480_MC_COL05                  40
+#define M_BCM1480_MC_COL05                  _SB_MAKEMASK(6,S_BCM1480_MC_COL05)
+#define V_BCM1480_MC_COL05(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL05)
+#define G_BCM1480_MC_COL05(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05)
+#define S_BCM1480_MC_COL06                  48
+#define M_BCM1480_MC_COL06                  _SB_MAKEMASK(6,S_BCM1480_MC_COL06)
+#define V_BCM1480_MC_COL06(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL06)
+#define G_BCM1480_MC_COL06(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06)
+#define S_BCM1480_MC_COL07                  56
+#define M_BCM1480_MC_COL07                  _SB_MAKEMASK(6,S_BCM1480_MC_COL07)
+#define V_BCM1480_MC_COL07(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL07)
+#define G_BCM1480_MC_COL07(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07)
+/*
+ * Column Address Bit Select Register 1 (Table 87)
+ */
+#define S_BCM1480_MC_COL08                  0
+#define M_BCM1480_MC_COL08                  _SB_MAKEMASK(6,S_BCM1480_MC_COL08)
+#define V_BCM1480_MC_COL08(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL08)
+#define G_BCM1480_MC_COL08(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08)
+#define S_BCM1480_MC_COL09                  8
+#define M_BCM1480_MC_COL09                  _SB_MAKEMASK(6,S_BCM1480_MC_COL09)
+#define V_BCM1480_MC_COL09(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL09)
+#define G_BCM1480_MC_COL09(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09)
+#define S_BCM1480_MC_COL10                  16   /* not a valid position, must be prog as 0 */
+#define S_BCM1480_MC_COL11                  24
+#define M_BCM1480_MC_COL11                  _SB_MAKEMASK(6,S_BCM1480_MC_COL11)
+#define V_BCM1480_MC_COL11(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL11)
+#define G_BCM1480_MC_COL11(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11)
+#define S_BCM1480_MC_COL12                  32
+#define M_BCM1480_MC_COL12                  _SB_MAKEMASK(6,S_BCM1480_MC_COL12)
+#define V_BCM1480_MC_COL12(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL12)
+#define G_BCM1480_MC_COL12(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12)
+#define S_BCM1480_MC_COL13                  40
+#define M_BCM1480_MC_COL13                  _SB_MAKEMASK(6,S_BCM1480_MC_COL13)
+#define V_BCM1480_MC_COL13(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL13)
+#define G_BCM1480_MC_COL13(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13)
+#define S_BCM1480_MC_COL14                  48
+#define M_BCM1480_MC_COL14                  _SB_MAKEMASK(6,S_BCM1480_MC_COL14)
+#define V_BCM1480_MC_COL14(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_COL14)
+#define G_BCM1480_MC_COL14(x)               _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14)
+#define K_BCM1480_MC_COLX_BIT_SPACING       8
+/*
+ * CS0 and CS1 Bank Address Bit Select Register (Table 88)
+ */
+#define S_BCM1480_MC_CS01_BANK0             0
+#define M_BCM1480_MC_CS01_BANK0             _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0)
+#define V_BCM1480_MC_CS01_BANK0(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0)
+#define G_BCM1480_MC_CS01_BANK0(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0)
+#define S_BCM1480_MC_CS01_BANK1             8
+#define M_BCM1480_MC_CS01_BANK1             _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1)
+#define V_BCM1480_MC_CS01_BANK1(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1)
+#define G_BCM1480_MC_CS01_BANK1(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1)
+#define S_BCM1480_MC_CS01_BANK2             16
+#define M_BCM1480_MC_CS01_BANK2             _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2)
+#define V_BCM1480_MC_CS01_BANK2(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2)
+#define G_BCM1480_MC_CS01_BANK2(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2)
+/*
+ * CS2 and CS3 Bank Address Bit Select Register (Table 89)
+ */
+#define S_BCM1480_MC_CS23_BANK0             0
+#define M_BCM1480_MC_CS23_BANK0             _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0)
+#define V_BCM1480_MC_CS23_BANK0(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0)
+#define G_BCM1480_MC_CS23_BANK0(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0)
+#define S_BCM1480_MC_CS23_BANK1             8
+#define M_BCM1480_MC_CS23_BANK1             _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1)
+#define V_BCM1480_MC_CS23_BANK1(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1)
+#define G_BCM1480_MC_CS23_BANK1(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1)
+#define S_BCM1480_MC_CS23_BANK2             16
+#define M_BCM1480_MC_CS23_BANK2             _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2)
+#define V_BCM1480_MC_CS23_BANK2(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2)
+#define G_BCM1480_MC_CS23_BANK2(x)          _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2)
+#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING  8
+/*
+ * DRAM Command Register (Table 90)
+ */
+#define S_BCM1480_MC_COMMAND                0
+#define M_BCM1480_MC_COMMAND                _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND)
+#define V_BCM1480_MC_COMMAND(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND)
+#define G_BCM1480_MC_COMMAND(x)             _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND)
+#define K_BCM1480_MC_COMMAND_EMRS           0
+#define K_BCM1480_MC_COMMAND_MRS            1
+#define K_BCM1480_MC_COMMAND_PRE            2
+#define K_BCM1480_MC_COMMAND_AR             3
+#define K_BCM1480_MC_COMMAND_SETRFSH        4
+#define K_BCM1480_MC_COMMAND_CLRRFSH        5
+#define K_BCM1480_MC_COMMAND_SETPWRDN       6
+#define K_BCM1480_MC_COMMAND_CLRPWRDN       7
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define K_BCM1480_MC_COMMAND_EMRS2          8
+#define K_BCM1480_MC_COMMAND_EMRS3          9
+#define K_BCM1480_MC_COMMAND_ENABLE_MCLK    10
+#define K_BCM1480_MC_COMMAND_DISABLE_MCLK   11
+#endif
+#define V_BCM1480_MC_COMMAND_EMRS           V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
+#define V_BCM1480_MC_COMMAND_MRS            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
+#define V_BCM1480_MC_COMMAND_PRE            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
+#define V_BCM1480_MC_COMMAND_AR             V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
+#define V_BCM1480_MC_COMMAND_SETRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
+#define V_BCM1480_MC_COMMAND_CLRRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
+#define V_BCM1480_MC_COMMAND_SETPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
+#define V_BCM1480_MC_COMMAND_CLRPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define V_BCM1480_MC_COMMAND_EMRS2          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
+#define V_BCM1480_MC_COMMAND_EMRS3          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)
+#define V_BCM1480_MC_COMMAND_ENABLE_MCLK    V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
+#define V_BCM1480_MC_COMMAND_DISABLE_MCLK   V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
+#endif
+#define S_BCM1480_MC_CS0                    4
+#define M_BCM1480_MC_CS0                    _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_CS1                    _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_CS2                    _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_CS3                    _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_CS4                    _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_CS5                    _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_CS6                    _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_CS7                    _SB_MAKEMASK1(11)
+#define M_BCM1480_MC_CMD_ACTIVE             _SB_MAKEMASK1(16)
+/*
+ * DRAM Mode Register (Table 91)
+ */
+#define S_BCM1480_MC_EMODE                  0
+#define M_BCM1480_MC_EMODE                  _SB_MAKEMASK(15,S_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE)
+#define G_BCM1480_MC_EMODE(x)               _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE_DEFAULT          V_BCM1480_MC_EMODE(0)
+#define S_BCM1480_MC_MODE                   16
+#define M_BCM1480_MC_MODE                   _SB_MAKEMASK(15,S_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_MODE)
+#define G_BCM1480_MC_MODE(x)                _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE_DEFAULT           V_BCM1480_MC_MODE(0)
+#define S_BCM1480_MC_DRAM_TYPE              32
+#define M_BCM1480_MC_DRAM_TYPE              _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE)
+#define V_BCM1480_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE)
+#define G_BCM1480_MC_DRAM_TYPE(x)           _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE)
+#define K_BCM1480_MC_DRAM_TYPE_JEDEC        0
+#define K_BCM1480_MC_DRAM_TYPE_FCRAM        1
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define K_BCM1480_MC_DRAM_TYPE_DDR2         2
+#endif
+#define V_BCM1480_MC_DRAM_TYPE_JEDEC        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
+#define V_BCM1480_MC_DRAM_TYPE_FCRAM        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define V_BCM1480_MC_DRAM_TYPE_DDR2         V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
+#endif
+#define M_BCM1480_MC_GANGED                 _SB_MAKEMASK1(36)
+#define M_BCM1480_MC_BY9_INTF               _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_FORCE_ECC64            _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_ECC_DISABLE            _SB_MAKEMASK1(39)
+#define S_BCM1480_MC_PG_POLICY              40
+#define M_BCM1480_MC_PG_POLICY              _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY)
+#define V_BCM1480_MC_PG_POLICY(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY)
+#define G_BCM1480_MC_PG_POLICY(x)           _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY)
+#define K_BCM1480_MC_PG_POLICY_CLOSED       0
+#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
+#define V_BCM1480_MC_PG_POLICY_CLOSED       V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)
+#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_2T_CMD                 _SB_MAKEMASK1(42)
+#define M_BCM1480_MC_ECC_COR_DIS            _SB_MAKEMASK1(43)
+#endif
+#define V_BCM1480_MC_DRAMMODE_DEFAULT   V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \
+                                V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+/*
+ * Memory Clock Configuration Register (Table 92)
+ */
+#define S_BCM1480_MC_CLK_RATIO              0
+#define M_BCM1480_MC_CLK_RATIO              _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO)
+#define V_BCM1480_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO)
+#define G_BCM1480_MC_CLK_RATIO(x)           _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO)
+#define V_BCM1480_MC_CLK_RATIO_DEFAULT      V_BCM1480_MC_CLK_RATIO(10)
+#define S_BCM1480_MC_REF_RATE               8
+#define M_BCM1480_MC_REF_RATE               _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE)
+#define V_BCM1480_MC_REF_RATE(x)            _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE)
+#define G_BCM1480_MC_REF_RATE(x)            _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE)
+#define K_BCM1480_MC_REF_RATE_100MHz        0x31
+#define K_BCM1480_MC_REF_RATE_200MHz        0x62
+#define K_BCM1480_MC_REF_RATE_400MHz        0xC4
+#define V_BCM1480_MC_REF_RATE_100MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
+#define V_BCM1480_MC_REF_RATE_200MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
+#define V_BCM1480_MC_REF_RATE_400MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
+#define V_BCM1480_MC_REF_RATE_DEFAULT       V_BCM1480_MC_REF_RATE_400MHz
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_AUTO_REF_DIS           _SB_MAKEMASK1(16)
+#endif
+/*
+ * ODT Register (Table 99)
+ */
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_RD_ODT0_CS0            _SB_MAKEMASK1(0)
+#define M_BCM1480_MC_RD_ODT0_CS2            _SB_MAKEMASK1(1)
+#define M_BCM1480_MC_RD_ODT0_CS4            _SB_MAKEMASK1(2)
+#define M_BCM1480_MC_RD_ODT0_CS6            _SB_MAKEMASK1(3)
+#define M_BCM1480_MC_WR_ODT0_CS0            _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_WR_ODT0_CS2            _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_WR_ODT0_CS4            _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_WR_ODT0_CS6            _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_RD_ODT2_CS0            _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RD_ODT2_CS2            _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_RD_ODT2_CS4            _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_RD_ODT2_CS6            _SB_MAKEMASK1(11)
+#define M_BCM1480_MC_WR_ODT2_CS0            _SB_MAKEMASK1(12)
+#define M_BCM1480_MC_WR_ODT2_CS2            _SB_MAKEMASK1(13)
+#define M_BCM1480_MC_WR_ODT2_CS4            _SB_MAKEMASK1(14)
+#define M_BCM1480_MC_WR_ODT2_CS6            _SB_MAKEMASK1(15)
+#define M_BCM1480_MC_RD_ODT4_CS0            _SB_MAKEMASK1(16)
+#define M_BCM1480_MC_RD_ODT4_CS2            _SB_MAKEMASK1(17)
+#define M_BCM1480_MC_RD_ODT4_CS4            _SB_MAKEMASK1(18)
+#define M_BCM1480_MC_RD_ODT4_CS6            _SB_MAKEMASK1(19)
+#define M_BCM1480_MC_WR_ODT4_CS0            _SB_MAKEMASK1(20)
+#define M_BCM1480_MC_WR_ODT4_CS2            _SB_MAKEMASK1(21)
+#define M_BCM1480_MC_WR_ODT4_CS4            _SB_MAKEMASK1(22)
+#define M_BCM1480_MC_WR_ODT4_CS6            _SB_MAKEMASK1(23)
+#define M_BCM1480_MC_RD_ODT6_CS0            _SB_MAKEMASK1(24)
+#define M_BCM1480_MC_RD_ODT6_CS2            _SB_MAKEMASK1(25)
+#define M_BCM1480_MC_RD_ODT6_CS4            _SB_MAKEMASK1(26)
+#define M_BCM1480_MC_RD_ODT6_CS6            _SB_MAKEMASK1(27)
+#define M_BCM1480_MC_WR_ODT6_CS0            _SB_MAKEMASK1(28)
+#define M_BCM1480_MC_WR_ODT6_CS2            _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_WR_ODT6_CS4            _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_WR_ODT6_CS6            _SB_MAKEMASK1(31)
+#define M_BCM1480_MC_CS_ODD_ODT_EN          _SB_MAKEMASK1(32)
+#endif
+/*
+ * Memory DLL Configuration Register (Table 93)
+ */
+#define S_BCM1480_MC_ADDR_COARSE_ADJ         0
+#define M_BCM1480_MC_ADDR_COARSE_ADJ         _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define G_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_ADDR_FREQ_RANGE            8
+#define M_BCM1480_MC_ADDR_FREQ_RANGE            _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define G_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT    V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
+#endif
+#define S_BCM1480_MC_ADDR_FINE_ADJ          8
+#define M_BCM1480_MC_ADDR_FINE_ADJ          _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ)
+#define G_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT  V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
+#define S_BCM1480_MC_DQI_COARSE_ADJ         16
+#define M_BCM1480_MC_DQI_COARSE_ADJ         _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ)
+#define G_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DQI_FREQ_RANGE             24
+#define M_BCM1480_MC_DQI_FREQ_RANGE             _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE)
+#define G_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
+#endif
+#define S_BCM1480_MC_DQI_FINE_ADJ           24
+#define M_BCM1480_MC_DQI_FINE_ADJ           _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ)
+#define G_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQI_FINE_ADJ(0x8)
+#define S_BCM1480_MC_DQO_COARSE_ADJ         32
+#define M_BCM1480_MC_DQO_COARSE_ADJ         _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ)
+#define G_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DQO_FREQ_RANGE             40
+#define M_BCM1480_MC_DQO_FREQ_RANGE             _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE)
+#define G_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
+#endif
+#define S_BCM1480_MC_DQO_FINE_ADJ           40
+#define M_BCM1480_MC_DQO_FINE_ADJ           _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ)
+#define G_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQO_FINE_ADJ(0x8)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_PDSEL            44
+#define M_BCM1480_MC_DLL_PDSEL            _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_PDSEL(x)         _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL)
+#define G_BCM1480_MC_DLL_PDSEL(x)         _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_DEFAULT_PDSEL    V_BCM1480_MC_DLL_PDSEL(0x0)
+#define M_BCM1480_MC_DLL_REGBYPASS        _SB_MAKEMASK1(46)
+#define M_BCM1480_MC_DQO_SHIFT            _SB_MAKEMASK1(47)
+#endif
+#define S_BCM1480_MC_DLL_DEFAULT            48
+#define M_BCM1480_MC_DLL_DEFAULT            _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT(x)         _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT)
+#define G_BCM1480_MC_DLL_DEFAULT(x)         _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT    V_BCM1480_MC_DLL_DEFAULT(0x10)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_REGCTRL          54
+#define M_BCM1480_MC_DLL_REGCTRL          _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_REGCTRL(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL)
+#define G_BCM1480_MC_DLL_REGCTRL(x)       _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL  V_BCM1480_MC_DLL_REGCTRL(0x0)
+#endif
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_FREQ_RANGE             56
+#define M_BCM1480_MC_DLL_FREQ_RANGE             _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE)
+#define G_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
+#endif
+#define S_BCM1480_MC_DLL_STEP_SIZE          56
+#define M_BCM1480_MC_DLL_STEP_SIZE          _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE)
+#define G_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT  V_BCM1480_MC_DLL_STEP_SIZE(0x8)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_BGCTRL   60
+#define M_BCM1480_MC_DLL_BGCTRL           _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_BGCTRL(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL)
+#define G_BCM1480_MC_DLL_BGCTRL(x)       _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL  V_BCM1480_MC_DLL_BGCTRL(0x0)
+#endif
+#define M_BCM1480_MC_DLL_BYPASS             _SB_MAKEMASK1(63)
+/*
+ * Memory Drive Configuration Register (Table 94)
+ */
+#define S_BCM1480_MC_RTT_BYP_PULLDOWN       0
+#define M_BCM1480_MC_RTT_BYP_PULLDOWN       _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define S_BCM1480_MC_RTT_BYP_PULLUP         6
+#define M_BCM1480_MC_RTT_BYP_PULLUP         _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP)
+#define V_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP)
+#define G_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP)
+#define M_BCM1480_MC_RTT_BYPASS             _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RTT_COMP_MOV_AVG       _SB_MAKEMASK1(9)
+#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN    10
+#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN    _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define S_BCM1480_MC_PVT_BYP_C1_PULLUP      15
+#define M_BCM1480_MC_PVT_BYP_C1_PULLUP      _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN    20
+#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN    _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define S_BCM1480_MC_PVT_BYP_C2_PULLUP      25
+#define M_BCM1480_MC_PVT_BYP_C2_PULLUP      _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define M_BCM1480_MC_PVT_BYPASS             _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_PVT_COMP_MOV_AVG       _SB_MAKEMASK1(31)
+#define M_BCM1480_MC_CLK_CLASS              _SB_MAKEMASK1(34)
+#define M_BCM1480_MC_DATA_CLASS             _SB_MAKEMASK1(35)
+#define M_BCM1480_MC_ADDR_CLASS             _SB_MAKEMASK1(36)
+#define M_BCM1480_MC_DQ_ODT_75              _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_DQ_ODT_150             _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_DQS_ODT_75             _SB_MAKEMASK1(39)
+#define M_BCM1480_MC_DQS_ODT_150            _SB_MAKEMASK1(40)
+#define M_BCM1480_MC_DQS_DIFF               _SB_MAKEMASK1(41)
+/*
+ * ECC Test Data Register (Table 95)
+ */
+#define S_BCM1480_MC_DATA_INVERT            0
+#define M_DATA_ECC_INVERT           _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT)
+/*
+ * ECC Test ECC Register (Table 96)
+ */
+#define S_BCM1480_MC_ECC_INVERT             0
+#define M_BCM1480_MC_ECC_INVERT             _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT)
+/*
+ * SDRAM Timing Register  (Table 97)
+ */
+#define S_BCM1480_MC_tRCD                   0
+#define M_BCM1480_MC_tRCD                   _SB_MAKEMASK(4,S_BCM1480_MC_tRCD)
+#define V_BCM1480_MC_tRCD(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD)
+#define G_BCM1480_MC_tRCD(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD)
+#define K_BCM1480_MC_tRCD_DEFAULT           3
+#define V_BCM1480_MC_tRCD_DEFAULT           V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
+#define S_BCM1480_MC_tCL                    4
+#define M_BCM1480_MC_tCL                    _SB_MAKEMASK(4,S_BCM1480_MC_tCL)
+#define V_BCM1480_MC_tCL(x)                 _SB_MAKEVALUE(x,S_BCM1480_MC_tCL)
+#define G_BCM1480_MC_tCL(x)                 _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL)
+#define K_BCM1480_MC_tCL_DEFAULT            2
+#define V_BCM1480_MC_tCL_DEFAULT            V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
+#define M_BCM1480_MC_tCrDh                  _SB_MAKEMASK1(8)
+#define S_BCM1480_MC_tWR                    9
+#define M_BCM1480_MC_tWR                    _SB_MAKEMASK(3,S_BCM1480_MC_tWR)
+#define V_BCM1480_MC_tWR(x)                 _SB_MAKEVALUE(x,S_BCM1480_MC_tWR)
+#define G_BCM1480_MC_tWR(x)                 _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR)
+#define K_BCM1480_MC_tWR_DEFAULT            2
+#define V_BCM1480_MC_tWR_DEFAULT            V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
+#define S_BCM1480_MC_tCwD                   12
+#define M_BCM1480_MC_tCwD                   _SB_MAKEMASK(4,S_BCM1480_MC_tCwD)
+#define V_BCM1480_MC_tCwD(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD)
+#define G_BCM1480_MC_tCwD(x)                _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD)
+#define K_BCM1480_MC_tCwD_DEFAULT           1
+#define V_BCM1480_MC_tCwD_DEFAULT           V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
+#define S_BCM1480_MC_tRP                    16
+#define M_BCM1480_MC_tRP                    _SB_MAKEMASK(4,S_BCM1480_MC_tRP)
+#define V_BCM1480_MC_tRP(x)                 _SB_MAKEVALUE(x,S_BCM1480_MC_tRP)
+#define G_BCM1480_MC_tRP(x)                 _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP)
+#define K_BCM1480_MC_tRP_DEFAULT            4
+#define V_BCM1480_MC_tRP_DEFAULT            V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
+#define S_BCM1480_MC_tRRD                   20
+#define M_BCM1480_MC_tRRD                   _SB_MAKEMASK(4,S_BCM1480_MC_tRRD)
+#define V_BCM1480_MC_tRRD(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD)
+#define G_BCM1480_MC_tRRD(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD)
+#define K_BCM1480_MC_tRRD_DEFAULT           2
+#define V_BCM1480_MC_tRRD_DEFAULT           V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
+#define S_BCM1480_MC_tRCw                   24
+#define M_BCM1480_MC_tRCw                   _SB_MAKEMASK(5,S_BCM1480_MC_tRCw)
+#define V_BCM1480_MC_tRCw(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw)
+#define G_BCM1480_MC_tRCw(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw)
+#define K_BCM1480_MC_tRCw_DEFAULT           10
+#define V_BCM1480_MC_tRCw_DEFAULT           V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
+#define S_BCM1480_MC_tRCr                   32
+#define M_BCM1480_MC_tRCr                   _SB_MAKEMASK(5,S_BCM1480_MC_tRCr)
+#define V_BCM1480_MC_tRCr(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr)
+#define G_BCM1480_MC_tRCr(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr)
+#define K_BCM1480_MC_tRCr_DEFAULT           9
+#define V_BCM1480_MC_tRCr_DEFAULT           V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_tFAW                   40
+#define M_BCM1480_MC_tFAW                   _SB_MAKEMASK(6,S_BCM1480_MC_tFAW)
+#define V_BCM1480_MC_tFAW(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW)
+#define G_BCM1480_MC_tFAW(x)                _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW)
+#define K_BCM1480_MC_tFAW_DEFAULT           0
+#define V_BCM1480_MC_tFAW_DEFAULT           V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
+#endif
+#define S_BCM1480_MC_tRFC                   48
+#define M_BCM1480_MC_tRFC                   _SB_MAKEMASK(7,S_BCM1480_MC_tRFC)
+#define V_BCM1480_MC_tRFC(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC)
+#define G_BCM1480_MC_tRFC(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC)
+#define K_BCM1480_MC_tRFC_DEFAULT           12
+#define V_BCM1480_MC_tRFC_DEFAULT           V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
+#define S_BCM1480_MC_tFIFO                  56
+#define M_BCM1480_MC_tFIFO                  _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO)
+#define V_BCM1480_MC_tFIFO(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO)
+#define G_BCM1480_MC_tFIFO(x)               _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO)
+#define K_BCM1480_MC_tFIFO_DEFAULT          0
+#define V_BCM1480_MC_tFIFO_DEFAULT          V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
+#define S_BCM1480_MC_tW2R                  58
+#define M_BCM1480_MC_tW2R                  _SB_MAKEMASK(2,S_BCM1480_MC_tW2R)
+#define V_BCM1480_MC_tW2R(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R)
+#define G_BCM1480_MC_tW2R(x)               _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R)
+#define K_BCM1480_MC_tW2R_DEFAULT          1
+#define V_BCM1480_MC_tW2R_DEFAULT          V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
+#define S_BCM1480_MC_tR2W                  60
+#define M_BCM1480_MC_tR2W                  _SB_MAKEMASK(2,S_BCM1480_MC_tR2W)
+#define V_BCM1480_MC_tR2W(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W)
+#define G_BCM1480_MC_tR2W(x)               _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W)
+#define K_BCM1480_MC_tR2W_DEFAULT          0
+#define V_BCM1480_MC_tR2W_DEFAULT          V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
+#define M_BCM1480_MC_tR2R                   _SB_MAKEMASK1(62)
+#define V_BCM1480_MC_TIMING_DEFAULT         (M_BCM1480_MC_tR2R | \
+                                     V_BCM1480_MC_tFIFO_DEFAULT | \
+                                     V_BCM1480_MC_tR2W_DEFAULT | \
+                                     V_BCM1480_MC_tW2R_DEFAULT | \
+                                     V_BCM1480_MC_tRFC_DEFAULT | \
+                                     V_BCM1480_MC_tRCr_DEFAULT | \
+                                     V_BCM1480_MC_tRCw_DEFAULT | \
+                                     V_BCM1480_MC_tRRD_DEFAULT | \
+                                     V_BCM1480_MC_tRP_DEFAULT | \
+                                     V_BCM1480_MC_tCwD_DEFAULT | \
+                                     V_BCM1480_MC_tWR_DEFAULT | \
+                                     M_BCM1480_MC_tCrDh | \
+                                     V_BCM1480_MC_tCL_DEFAULT | \
+                                     V_BCM1480_MC_tRCD_DEFAULT)
+/*
+ * SDRAM Timing Register 2
+ */
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_tAL                   0
+#define M_BCM1480_MC_tAL                   _SB_MAKEMASK(4,S_BCM1480_MC_tAL)
+#define V_BCM1480_MC_tAL(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tAL)
+#define G_BCM1480_MC_tAL(x)                _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL)
+#define K_BCM1480_MC_tAL_DEFAULT           0
+#define V_BCM1480_MC_tAL_DEFAULT           V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
+#define S_BCM1480_MC_tRTP                   4
+#define M_BCM1480_MC_tRTP                   _SB_MAKEMASK(3,S_BCM1480_MC_tRTP)
+#define V_BCM1480_MC_tRTP(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP)
+#define G_BCM1480_MC_tRTP(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP)
+#define K_BCM1480_MC_tRTP_DEFAULT           2
+#define V_BCM1480_MC_tRTP_DEFAULT           V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
+#define S_BCM1480_MC_tW2W                   8
+#define M_BCM1480_MC_tW2W                   _SB_MAKEMASK(2,S_BCM1480_MC_tW2W)
+#define V_BCM1480_MC_tW2W(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W)
+#define G_BCM1480_MC_tW2W(x)                _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W)
+#define K_BCM1480_MC_tW2W_DEFAULT           0
+#define V_BCM1480_MC_tW2W_DEFAULT           V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
+#define S_BCM1480_MC_tRAP                   12
+#define M_BCM1480_MC_tRAP                  _SB_MAKEMASK(4,S_BCM1480_MC_tRAP)
+#define V_BCM1480_MC_tRAP(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP)
+#define G_BCM1480_MC_tRAP(x)                _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP)
+#define K_BCM1480_MC_tRAP_DEFAULT           0
+#define V_BCM1480_MC_tRAP_DEFAULT           V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
+#endif
+/*
+ * Global Registers: single instances per BCM1480
+ */
+/*
+ * Global Configuration Register (Table 99)
+ */
+#define S_BCM1480_MC_BLK_SET_MARK           8
+#define M_BCM1480_MC_BLK_SET_MARK           _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK)
+#define V_BCM1480_MC_BLK_SET_MARK(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK)
+#define G_BCM1480_MC_BLK_SET_MARK(x)        _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK)
+#define S_BCM1480_MC_BLK_CLR_MARK           12
+#define M_BCM1480_MC_BLK_CLR_MARK           _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK)
+#define V_BCM1480_MC_BLK_CLR_MARK(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK)
+#define G_BCM1480_MC_BLK_CLR_MARK(x)        _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK)
+#define M_BCM1480_MC_PKT_PRIORITY           _SB_MAKEMASK1(16)
+#define S_BCM1480_MC_MAX_AGE                20
+#define M_BCM1480_MC_MAX_AGE                _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE)
+#define V_BCM1480_MC_MAX_AGE(x)             _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE)
+#define G_BCM1480_MC_MAX_AGE(x)             _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE)
+#define M_BCM1480_MC_BERR_DISABLE           _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_FORCE_SEQ              _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_VGEN                   _SB_MAKEMASK1(32)
+#define S_BCM1480_MC_SLEW                   33
+#define M_BCM1480_MC_SLEW                   _SB_MAKEMASK(2,S_BCM1480_MC_SLEW)
+#define V_BCM1480_MC_SLEW(x)                _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW)
+#define G_BCM1480_MC_SLEW(x)                _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW)
+#define M_BCM1480_MC_SSTL_VOLTAGE           _SB_MAKEMASK1(35)
+/*
+ * Global Channel Interleave Register (Table 100)
+ */
+#define S_BCM1480_MC_INTLV0                 0
+#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0)
+#define S_BCM1480_MC_INTLV1                 8
+#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1)
+#define S_BCM1480_MC_INTLV_MODE             16
+#define M_BCM1480_MC_INTLV_MODE             _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE)
+#define V_BCM1480_MC_INTLV_MODE(x)          _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE)
+#define G_BCM1480_MC_INTLV_MODE(x)          _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE)
+#define K_BCM1480_MC_INTLV_MODE_NONE        0x0
+#define K_BCM1480_MC_INTLV_MODE_01          0x1
+#define K_BCM1480_MC_INTLV_MODE_23          0x2
+#define K_BCM1480_MC_INTLV_MODE_01_23       0x3
+#define K_BCM1480_MC_INTLV_MODE_0123        0x4
+#define V_BCM1480_MC_INTLV_MODE_NONE        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
+#define V_BCM1480_MC_INTLV_MODE_01          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
+#define V_BCM1480_MC_INTLV_MODE_23          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
+#define V_BCM1480_MC_INTLV_MODE_01_23       V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
+#define V_BCM1480_MC_INTLV_MODE_0123        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)
+/*
+ * ECC Status Register
+ */
+#define S_BCM1480_MC_ECC_ERR_ADDR           0
+#define M_BCM1480_MC_ECC_ERR_ADDR           _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR)
+#define V_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR)
+#define G_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR)
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_ECC_ERR_RMW            _SB_MAKEMASK1(60)
+#endif
+#define M_BCM1480_MC_ECC_MULT_ERR_DET       _SB_MAKEMASK1(61)
+#define M_BCM1480_MC_ECC_UERR_DET           _SB_MAKEMASK1(62)
+#define M_BCM1480_MC_ECC_CERR_DET           _SB_MAKEMASK1(63)
+/*
+ * Global ECC Address Register (Table 102)
+ */
+#define S_BCM1480_MC_ECC_CORR_ADDR          0
+#define M_BCM1480_MC_ECC_CORR_ADDR          _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR)
+#define V_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR)
+#define G_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR)
+/*
+ * Global ECC Correction Register (Table 103)
+ */
+#define S_BCM1480_MC_ECC_CORRECT            0
+#define M_BCM1480_MC_ECC_CORRECT            _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT)
+#define V_BCM1480_MC_ECC_CORRECT(x)         _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT)
+#define G_BCM1480_MC_ECC_CORRECT(x)         _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT)
+/*
+ * Global ECC Performance Counters Control Register (Table 104)
+ */
+#define S_BCM1480_MC_CHANNEL_SELECT         0
+#define M_BCM1480_MC_CHANNEL_SELECT         _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT)
+#define V_BCM1480_MC_CHANNEL_SELECT(x)      _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT)
+#define G_BCM1480_MC_CHANNEL_SELECT(x)      _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT)
+#define K_BCM1480_MC_CHANNEL_SELECT_0       0x1
+#define K_BCM1480_MC_CHANNEL_SELECT_1       0x2
+#define K_BCM1480_MC_CHANNEL_SELECT_2       0x4
+#define K_BCM1480_MC_CHANNEL_SELECT_3       0x8
+#endif /* _BCM1480_MC_H */
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
new file mode 100644
index 000000000000..c2dd2fe3047c
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -0,0 +1,869 @@
+/*  *********************************************************************
+    *  BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
+    *
+    *  Register Definitions                     File: bcm1480_regs.h
+    *
+    *  This module contains the addresses of the on-chip peripherals
+    *  on the BCM1280 and BCM1480.
+    *
+    *  BCM1480 specification level:  1X55_1X80-UM100-D4 (11/24/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+#ifndef _BCM1480_REGS_H
+#define _BCM1480_REGS_H
+#include "sb1250_defs.h"
+/*  *********************************************************************
+    *  Pull in the BCM1250's registers since a great deal of the 1480's
+    *  functions are the same as the BCM1250.
+    ********************************************************************* */
+#include "sb1250_regs.h"
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  Register addresses are grouped by function and follow the order
+    *  of the User Manual.
+    *
+    *  For the most part, when there is more than one peripheral
+    *  of the same type on the SOC, the constants below will be
+    *  offsets from the base of each peripheral.  For example,
+    *  the MAC registers are described as offsets from the first
+    *  MAC register, and there will be a MAC_REGISTER() macro
+    *  to calculate the base address of a given MAC.
+    *
+    *  The information in this file is based on the BCM1X55/BCM1X80
+    *  User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
+    *
+    *  This file is basically a "what's new" header file.  Since the
+    *  BCM1250 and the new BCM1480 (and derivatives) share many common
+    *  features, this file contains only what's new or changed from
+    *  the 1250.  (above, you can see that we include the 1250 symbols
+    *  to get the base functionality).
+    *
+    *  In software, be sure to use the correct symbols, particularly
+    *  for blocks that are different between the two chip families.
+    *  All BCM1480-specific symbols have _BCM1480_ in their names,
+    *  and all BCM1250-specific and "base" functions that are common in
+    *  both chips have no special names (this is for compatibility with
+    *  older include files).  Therefore, if you're working with the
+    *  SCD, which is very different on each chip, A_SCD_xxx implies
+    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
+    *  version.
+    ********************************************************************* */
+/*  *********************************************************************
+    * Memory Controller Registers (Section 6)
+    ********************************************************************* */
+#define A_BCM1480_MC_BASE_0                 0x0010050000
+#define A_BCM1480_MC_BASE_1                 0x0010051000
+#define A_BCM1480_MC_BASE_2                 0x0010052000
+#define A_BCM1480_MC_BASE_3                 0x0010053000
+#define BCM1480_MC_REGISTER_SPACING         0x1000
+#define A_BCM1480_MC_BASE(ctlid)            (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
+#define A_BCM1480_MC_REGISTER(ctlid,reg)    (A_BCM1480_MC_BASE(ctlid)+(reg))
+#define R_BCM1480_MC_CONFIG                 0x0000000100
+#define R_BCM1480_MC_CS_START               0x0000000120
+#define R_BCM1480_MC_CS_END                 0x0000000140
+#define S_BCM1480_MC_CS_STARTEND            24
+#define R_BCM1480_MC_CS01_ROW0              0x0000000180
+#define R_BCM1480_MC_CS01_ROW1              0x00000001A0
+#define R_BCM1480_MC_CS23_ROW0              0x0000000200
+#define R_BCM1480_MC_CS23_ROW1              0x0000000220
+#define R_BCM1480_MC_CS01_COL0              0x0000000280
+#define R_BCM1480_MC_CS01_COL1              0x00000002A0
+#define R_BCM1480_MC_CS23_COL0              0x0000000300
+#define R_BCM1480_MC_CS23_COL1              0x0000000320
+#define R_BCM1480_MC_CSX_BASE               0x0000000180
+#define R_BCM1480_MC_CSX_ROW0               0x0000000000   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_ROW1               0x0000000020   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL0               0x0000000100   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL1               0x0000000120   /* relative to CSX_BASE */
+#define BCM1480_MC_CSX_SPACING              0x0000000080   /* CS23 relative to CS01 */
+#define R_BCM1480_MC_CS01_BA                0x0000000380
+#define R_BCM1480_MC_CS23_BA                0x00000003A0
+#define R_BCM1480_MC_DRAMCMD                0x0000000400
+#define R_BCM1480_MC_DRAMMODE               0x0000000420
+#define R_BCM1480_MC_CLOCK_CFG              0x0000000440
+#define R_BCM1480_MC_MCLK_CFG               R_BCM1480_MC_CLOCK_CFG
+#define R_BCM1480_MC_TEST_DATA              0x0000000480
+#define R_BCM1480_MC_TEST_ECC               0x00000004A0
+#define R_BCM1480_MC_TIMING1                0x00000004C0
+#define R_BCM1480_MC_TIMING2                0x00000004E0
+#define R_BCM1480_MC_DLL_CFG                0x0000000500
+#define R_BCM1480_MC_DRIVE_CFG              0x0000000520
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define R_BCM1480_MC_ODT                    0x0000000460
+#define R_BCM1480_MC_ECC_STATUS             0x0000000540
+#endif
+/* Global registers (single instance) */
+#define A_BCM1480_MC_GLB_CONFIG             0x0010054100
+#define A_BCM1480_MC_GLB_INTLV              0x0010054120
+#define A_BCM1480_MC_GLB_ECC_STATUS         0x0010054140
+#define A_BCM1480_MC_GLB_ECC_ADDR           0x0010054160
+#define A_BCM1480_MC_GLB_ECC_CORRECT        0x0010054180
+#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL   0x00100541A0
+/*  *********************************************************************
+    * L2 Cache Control Registers (Section 5)
+    ********************************************************************* */
+#define A_BCM1480_L2_BASE                   0x0010040000
+#define A_BCM1480_L2_READ_TAG               0x0010040018
+#define A_BCM1480_L2_ECC_TAG                0x0010040038
+#define A_BCM1480_L2_MISC0_VALUE            0x0010040058
+#define A_BCM1480_L2_MISC1_VALUE            0x0010040078
+#define A_BCM1480_L2_MISC2_VALUE            0x0010040098
+#define A_BCM1480_L2_MISC_CONFIG            0x0010040040        /* x040 */
+#define A_BCM1480_L2_CACHE_DISABLE          0x0010040060        /* x060 */
+#define A_BCM1480_L2_MAKECACHEDISABLE(x)    (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
+#define A_BCM1480_L2_WAY_ENABLE_3_0         0x0010040080        /* x080 */
+#define A_BCM1480_L2_WAY_ENABLE_7_4         0x00100400A0        /* x0A0 */
+#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
+#define A_BCM1480_L2_WAY_LOCAL_3_0          0x0010040100        /* x100 */
+#define A_BCM1480_L2_WAY_LOCAL_7_4          0x0010040120        /* x120 */
+#define A_BCM1480_L2_WAY_REMOTE_3_0         0x0010040140        /* x140 */
+#define A_BCM1480_L2_WAY_REMOTE_7_4         0x0010040160        /* x160 */
+#define A_BCM1480_L2_WAY_AGENT_3_0          0x00100400C0        /* xxC0 */
+#define A_BCM1480_L2_WAY_AGENT_7_4          0x00100400E0        /* xxE0 */
+#define A_BCM1480_L2_WAY_ENABLE(A, banks)   (A | (((~(banks))&0x0F) << 8))
+#define A_BCM1480_L2_BANK_BASE              0x00D0300000
+#define A_BCM1480_L2_BANK_ADDRESS(b)        (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
+#define A_BCM1480_L2_MGMT_TAG_BASE          0x00D0000000
+/*  *********************************************************************
+    * PCI-X Interface Registers (Section 7)
+    ********************************************************************* */
+#define A_BCM1480_PCI_BASE                  0x0010061400
+#define A_BCM1480_PCI_RESET                 0x0010061400
+#define A_BCM1480_PCI_DLL                   0x0010061500
+#define A_BCM1480_PCI_TYPE00_HEADER         0x002E000000
+/*  *********************************************************************
+    * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
+    ********************************************************************* */
+/* No register changes with Rev.C BCM1250, but one additional MAC */
+#define A_BCM1480_MAC_BASE_2        0x0010066000
+#ifndef A_MAC_BASE_2
+#define A_MAC_BASE_2                A_BCM1480_MAC_BASE_2
+#endif
+#define A_BCM1480_MAC_BASE_3        0x0010067000
+#define A_MAC_BASE_3                A_BCM1480_MAC_BASE_3
+#define R_BCM1480_MAC_DMA_OODPKTLOST        0x00000038
+#ifndef R_MAC_DMA_OODPKTLOST
+#define R_MAC_DMA_OODPKTLOST        R_BCM1480_MAC_DMA_OODPKTLOST
+#endif
+/*  *********************************************************************
+    * DUART Registers (Section 14)
+    ********************************************************************* */
+/* No significant differences from BCM1250, two DUARTs */
+/*  Conventions, per user manual:
+ *     DUART    generic, channels A,B,C,D
+ *     DUART0   implementing channels A,B
+ *     DUART1   inplementing channels C,D
+ */
+#define BCM1480_DUART_NUM_PORTS           4
+#define A_BCM1480_DUART0                    0x0010060000
+#define A_BCM1480_DUART1                    0x0010060400
+#define A_BCM1480_DUART(chan)               ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
+#define BCM1480_DUART_CHANREG_SPACING       0x100
+#define A_BCM1480_DUART_CHANREG(chan,reg)   (A_BCM1480_DUART(chan) \
+                                     + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \
+                                     + (reg))
+#define R_BCM1480_DUART_CHANREG(chan,reg)   (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg))
+#define R_BCM1480_DUART_IMRREG(chan)        (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING)
+#define R_BCM1480_DUART_ISRREG(chan)        (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING)
+#define A_BCM1480_DUART_IMRREG(chan)        (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))
+#define A_BCM1480_DUART_ISRREG(chan)        (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))
+/*
+ * These constants are the absolute addresses.
+ */
+#define A_BCM1480_DUART_MODE_REG_1_C        0x0010060400
+#define A_BCM1480_DUART_MODE_REG_2_C        0x0010060410
+#define A_BCM1480_DUART_STATUS_C            0x0010060420
+#define A_BCM1480_DUART_CLK_SEL_C           0x0010060430
+#define A_BCM1480_DUART_FULL_CTL_C          0x0010060440
+#define A_BCM1480_DUART_CMD_C               0x0010060450
+#define A_BCM1480_DUART_RX_HOLD_C           0x0010060460
+#define A_BCM1480_DUART_TX_HOLD_C           0x0010060470
+#define A_BCM1480_DUART_OPCR_C              0x0010060480
+#define A_BCM1480_DUART_AUX_CTRL_C          0x0010060490
+#define A_BCM1480_DUART_MODE_REG_1_D        0x0010060500
+#define A_BCM1480_DUART_MODE_REG_2_D        0x0010060510
+#define A_BCM1480_DUART_STATUS_D            0x0010060520
+#define A_BCM1480_DUART_CLK_SEL_D           0x0010060530
+#define A_BCM1480_DUART_FULL_CTL_D          0x0010060540
+#define A_BCM1480_DUART_CMD_D               0x0010060550
+#define A_BCM1480_DUART_RX_HOLD_D           0x0010060560
+#define A_BCM1480_DUART_TX_HOLD_D           0x0010060570
+#define A_BCM1480_DUART_OPCR_D              0x0010060580
+#define A_BCM1480_DUART_AUX_CTRL_D          0x0010060590
+#define A_BCM1480_DUART_INPORT_CHNG_CD      0x0010060600
+#define A_BCM1480_DUART_AUX_CTRL_CD         0x0010060610
+#define A_BCM1480_DUART_ISR_C               0x0010060620
+#define A_BCM1480_DUART_IMR_C               0x0010060630
+#define A_BCM1480_DUART_ISR_D               0x0010060640
+#define A_BCM1480_DUART_IMR_D               0x0010060650
+#define A_BCM1480_DUART_OUT_PORT_CD         0x0010060660
+#define A_BCM1480_DUART_OPCR_CD             0x0010060670
+#define A_BCM1480_DUART_IN_PORT_CD          0x0010060680
+#define A_BCM1480_DUART_ISR_CD              0x0010060690
+#define A_BCM1480_DUART_IMR_CD              0x00100606A0
+#define A_BCM1480_DUART_SET_OPR_CD          0x00100606B0
+#define A_BCM1480_DUART_CLEAR_OPR_CD        0x00100606C0
+#define A_BCM1480_DUART_INPORT_CHNG_C       0x00100606D0
+#define A_BCM1480_DUART_INPORT_CHNG_D       0x00100606E0
+/*  *********************************************************************
+    * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
+    ********************************************************************* */
+#define A_BCM1480_IO_PCMCIA_CFG_B       0x0010061A58
+#define A_BCM1480_IO_PCMCIA_STATUS_B    0x0010061A68
+/*  *********************************************************************
+    * GPIO Registers (Section 17)
+    ********************************************************************* */
+/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
+#define A_BCM1480_GPIO_INT_ADD_TYPE         0x0010061A78
+#define R_BCM1480_GPIO_INT_ADD_TYPE         (-8)
+#define A_GPIO_INT_ADD_TYPE     A_BCM1480_GPIO_INT_ADD_TYPE
+#define R_GPIO_INT_ADD_TYPE     R_BCM1480_GPIO_INT_ADD_TYPE
+/*  *********************************************************************
+    * SMBus Registers (Section 18)
+    ********************************************************************* */
+/* No changes from BCM1250 */
+/*  *********************************************************************
+    * Timer Registers (Sections 4.6)
+    ********************************************************************* */
+/* BCM1480 has two additional watchdogs */
+/* Watchdog timers */
+#define A_BCM1480_SCD_WDOG_2                0x0010022050
+#define A_BCM1480_SCD_WDOG_3                0x0010022150
+#define BCM1480_SCD_NUM_WDOGS               4
+#define A_BCM1480_SCD_WDOG_BASE(w)       (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
+#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
+#define A_BCM1480_SCD_WDOG_INIT_2       0x0010022050
+#define A_BCM1480_SCD_WDOG_CNT_2        0x0010022058
+#define A_BCM1480_SCD_WDOG_CFG_2        0x0010022060
+#define A_BCM1480_SCD_WDOG_INIT_3       0x0010022150
+#define A_BCM1480_SCD_WDOG_CNT_3        0x0010022158
+#define A_BCM1480_SCD_WDOG_CFG_3        0x0010022160
+/* BCM1480 has two additional compare registers */
+#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT         A_SCD_ZBBUS_CYCLE_COUNT
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE       0x0010020C00
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0           A_SCD_ZBBUS_CYCLE_CP0
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1           A_SCD_ZBBUS_CYCLE_CP1
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2           0x0010020C10
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3           0x0010020C18
+/*  *********************************************************************
+    * System Control Registers (Section 4.2)
+    ********************************************************************* */
+/* Scratch register in different place */
+#define A_BCM1480_SCD_SCRATCH           0x100200A0
+/*  *********************************************************************
+    * System Address Trap Registers (Section 4.9)
+    ********************************************************************* */
+/* No changes from BCM1250 */
+/*  *********************************************************************
+    * System Interrupt Mapper Registers (Sections 4.3-4.5)
+    ********************************************************************* */
+#define A_BCM1480_IMR_CPU0_BASE             0x0010020000
+#define A_BCM1480_IMR_CPU1_BASE             0x0010022000
+#define A_BCM1480_IMR_CPU2_BASE             0x0010024000
+#define A_BCM1480_IMR_CPU3_BASE             0x0010026000
+#define BCM1480_IMR_REGISTER_SPACING        0x2000
+#define BCM1480_IMR_REGISTER_SPACING_SHIFT  13
+#define A_BCM1480_IMR_MAPPER(cpu)       (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
+#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
+/* Most IMR registers are 128 bits, implemented as non-contiguous
+   64-bit registers high (_H) and low (_L) */
+#define BCM1480_IMR_HL_SPACING                  0x1000
+#define R_BCM1480_IMR_INTERRUPT_DIAG_H          0x0010
+#define R_BCM1480_IMR_LDT_INTERRUPT_H           0x0018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H       0x0020
+#define R_BCM1480_IMR_INTERRUPT_MASK_H          0x0028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_H         0x0038
+#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
+#define R_BCM1480_IMR_LDT_INTERRUPT_SET         0x0048
+#define R_BCM1480_IMR_MAILBOX_0_CPU             0x00C0
+#define R_BCM1480_IMR_MAILBOX_0_SET_CPU         0x00C8
+#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU         0x00D0
+#define R_BCM1480_IMR_MAILBOX_1_CPU             0x00E0
+#define R_BCM1480_IMR_MAILBOX_1_SET_CPU         0x00E8
+#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU         0x00F0
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H   0x0100
+#define BCM1480_IMR_INTERRUPT_STATUS_COUNT      8
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H      0x0200
+#define BCM1480_IMR_INTERRUPT_MAP_COUNT         64
+#define R_BCM1480_IMR_INTERRUPT_DIAG_L          0x1010
+#define R_BCM1480_IMR_LDT_INTERRUPT_L           0x1018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L       0x1020
+#define R_BCM1480_IMR_INTERRUPT_MASK_L          0x1028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_L         0x1038
+#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L   0x1100
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L      0x1200
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE   0x0010028000
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE   0x0010028100
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE   0x0010028200
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE   0x0010028300
+#define BCM1480_IMR_ALIAS_MAILBOX_SPACING       0100
+#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu)     (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
+                                        (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
+#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000          /* 0x0x0 */
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008          /* 0x0x8 */
+/*  *********************************************************************
+    * System Performance Counter Registers (Section 4.7)
+    ********************************************************************* */
+/* BCM1480 has four more performance counter registers, and two control
+   registers. */
+#define A_BCM1480_SCD_PERF_CNT_BASE         0x00100204C0
+#define A_BCM1480_SCD_PERF_CNT_CFG0         0x00100204C0
+#define A_BCM1480_SCD_PERF_CNT_CFG_0        A_BCM1480_SCD_PERF_CNT_CFG0
+#define A_BCM1480_SCD_PERF_CNT_CFG1         0x00100204C8
+#define A_BCM1480_SCD_PERF_CNT_CFG_1        A_BCM1480_SCD_PERF_CNT_CFG1
+#define A_BCM1480_SCD_PERF_CNT_0            A_SCD_PERF_CNT_0
+#define A_BCM1480_SCD_PERF_CNT_1            A_SCD_PERF_CNT_1
+#define A_BCM1480_SCD_PERF_CNT_2            A_SCD_PERF_CNT_2
+#define A_BCM1480_SCD_PERF_CNT_3            A_SCD_PERF_CNT_3
+#define A_BCM1480_SCD_PERF_CNT_4            0x00100204F0
+#define A_BCM1480_SCD_PERF_CNT_5            0x00100204F8
+#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500
+#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508
+/*  *********************************************************************
+    * System Bus Watcher Registers (Section 4.8)
+    ********************************************************************* */
+/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
+#define A_BCM1480_BUS_ERR_STATUS_DEBUG      0x00100208D8
+/*  *********************************************************************
+    * System Debug Controller Registers (Section 19)
+    ********************************************************************* */
+/* Same as 1250 */
+/*  *********************************************************************
+    * System Trace Unit Registers (Sections 4.10)
+    ********************************************************************* */
+/* Same as 1250 */
+/*  *********************************************************************
+    * Data Mover DMA Registers (Section 10.7)
+    ********************************************************************* */
+/* Same as 1250 */
+/*  *********************************************************************
+    * HyperTransport Interface Registers (Section 8)
+    ********************************************************************* */
+#define BCM1480_HT_NUM_PORTS               3
+#define BCM1480_HT_PORT_SPACING            0x800
+#define A_BCM1480_HT_PORT_HEADER(x)        (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
+#define A_BCM1480_HT_PORT0_HEADER          0x00FE000000
+#define A_BCM1480_HT_PORT1_HEADER          0x00FE000800
+#define A_BCM1480_HT_PORT2_HEADER          0x00FE001000
+#define A_BCM1480_HT_TYPE00_HEADER         0x00FE002000
+/*  *********************************************************************
+    * Node Controller Registers (Section 9)
+    ********************************************************************* */
+#define A_BCM1480_NC_BASE                   0x00DFBD0000
+#define A_BCM1480_NC_RLD_FIELD              0x00DFBD0000
+#define A_BCM1480_NC_RLD_TRIGGER            0x00DFBD0020
+#define A_BCM1480_NC_RLD_BAD_ERROR          0x00DFBD0040
+#define A_BCM1480_NC_RLD_COR_ERROR          0x00DFBD0060
+#define A_BCM1480_NC_RLD_ECC_STATUS         0x00DFBD0080
+#define A_BCM1480_NC_RLD_WAY_ENABLE         0x00DFBD00A0
+#define A_BCM1480_NC_RLD_RANDOM_LFSR        0x00DFBD00C0
+#define A_BCM1480_NC_INTERRUPT_STATUS       0x00DFBD00E0
+#define A_BCM1480_NC_INTERRUPT_ENABLE       0x00DFBD0100
+#define A_BCM1480_NC_TIMEOUT_COUNTER        0x00DFBD0120
+#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL    0x00DFBD0140
+#define A_BCM1480_NC_CREDIT_STATUS_REG0     0x00DFBD0200
+#define A_BCM1480_NC_CREDIT_STATUS_REG1     0x00DFBD0220
+#define A_BCM1480_NC_CREDIT_STATUS_REG2     0x00DFBD0240
+#define A_BCM1480_NC_CREDIT_STATUS_REG3     0x00DFBD0260
+#define A_BCM1480_NC_CREDIT_STATUS_REG4     0x00DFBD0280
+#define A_BCM1480_NC_CREDIT_STATUS_REG5     0x00DFBD02A0
+#define A_BCM1480_NC_CREDIT_STATUS_REG6     0x00DFBD02C0
+#define A_BCM1480_NC_CREDIT_STATUS_REG7     0x00DFBD02E0
+#define A_BCM1480_NC_CREDIT_STATUS_REG8     0x00DFBD0300
+#define A_BCM1480_NC_CREDIT_STATUS_REG9     0x00DFBD0320
+#define A_BCM1480_NC_CREDIT_STATUS_REG10    0x00DFBE0000
+#define A_BCM1480_NC_CREDIT_STATUS_REG11    0x00DFBE0020
+#define A_BCM1480_NC_CREDIT_STATUS_REG12    0x00DFBE0040
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER     0x00DFBE0060
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
+/*  *********************************************************************
+    * H&R Block Configuration Registers (Section 12.4)
+    ********************************************************************* */
+#define A_BCM1480_HR_BASE_0                 0x00DF820000
+#define A_BCM1480_HR_BASE_1                 0x00DF8A0000
+#define A_BCM1480_HR_BASE_2                 0x00DF920000
+#define BCM1480_HR_REGISTER_SPACING         0x80000
+#define A_BCM1480_HR_BASE(idx)              (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
+#define A_BCM1480_HR_REGISTER(idx,reg)      (A_BCM1480_HR_BASE(idx) + (reg))
+#define R_BCM1480_HR_CFG                    0x0000000000
+#define R_BCM1480_HR_MAPPING                0x0000010010
+#define BCM1480_HR_RULE_SPACING             0x0000000010
+#define BCM1480_HR_NUM_RULES                16
+#define BCM1480_HR_OP_OFFSET                0x0000000100
+#define BCM1480_HR_TYPE_OFFSET              0x0000000108
+#define R_BCM1480_HR_RULE_OP(idx)           (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+#define R_BCM1480_HR_RULE_TYPE(idx)         (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+#define BCM1480_HR_LEAF_SPACING             0x0000000010
+#define BCM1480_HR_NUM_LEAVES               10
+#define BCM1480_HR_LEAF_OFFSET              0x0000000300
+#define R_BCM1480_HR_HA_LEAF0(idx)          (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
+#define R_BCM1480_HR_EX_LEAF0               0x00000003A0
+#define BCM1480_HR_PATH_SPACING             0x0000000010
+#define BCM1480_HR_NUM_PATHS                16
+#define BCM1480_HR_PATH_OFFSET              0x0000000600
+#define R_BCM1480_HR_PATH(idx)              (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
+#define R_BCM1480_HR_PATH_DEFAULT           0x0000000700
+#define BCM1480_HR_ROUTE_SPACING            8
+#define BCM1480_HR_NUM_ROUTES               512
+#define BCM1480_HR_ROUTE_OFFSET             0x0000001000
+#define R_BCM1480_HR_RT_WORD(idx)           (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
+/* checked to here - ehs */
+/*  *********************************************************************
+    * Packet Manager DMA Registers (Section 12.5)
+    ********************************************************************* */
+#define A_BCM1480_PM_BASE                   0x0010056000
+#define A_BCM1480_PMI_LCL_0                 0x0010058000
+#define A_BCM1480_PMO_LCL_0                 0x001005C000
+#define A_BCM1480_PMI_OFFSET_0              (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_OFFSET_0              (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
+#define BCM1480_PM_LCL_REGISTER_SPACING     0x100
+#define BCM1480_PM_NUM_CHANNELS             32
+#define A_BCM1480_PMI_LCL_BASE(idx)             (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMI_LCL_REGISTER(idx,reg)     (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
+#define A_BCM1480_PMO_LCL_BASE(idx)             (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMO_LCL_REGISTER(idx,reg)     (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
+#define BCM1480_PM_INT_PACKING              8
+#define BCM1480_PM_INT_FUNCTION_SPACING     0x40
+#define BCM1480_PM_INT_NUM_FUNCTIONS        3
+/*
+ * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
+ */
+#define R_BCM1480_PM_BASE_SIZE              0x0000000000
+#define R_BCM1480_PM_CNT                    0x0000000008
+#define R_BCM1480_PM_PFCNT                  0x0000000010
+#define R_BCM1480_PM_LAST                   0x0000000018
+#define R_BCM1480_PM_PFINDX                 0x0000000020
+#define R_BCM1480_PM_INT_WMK                0x0000000028
+#define R_BCM1480_PM_CONFIG0                0x0000000030
+#define R_BCM1480_PM_LOCALDEBUG             0x0000000078
+#define R_BCM1480_PM_CACHEABILITY           0x0000000080   /* PMI only */
+#define R_BCM1480_PM_INT_CNFG               0x0000000088
+#define R_BCM1480_PM_DESC_MERGE_TIMER       0x0000000090
+#define R_BCM1480_PM_LOCALDEBUG_PIB         0x00000000F8   /* PMI only */
+#define R_BCM1480_PM_LOCALDEBUG_POB         0x00000000F8   /* PMO only */
+/*
+ * Global Registers (Not Channelized)
+ */
+#define A_BCM1480_PMI_GLB_0                 0x0010056000
+#define A_BCM1480_PMO_GLB_0                 0x0010057000
+/*
+ * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
+ */
+#define R_BCM1480_PM_PMO_MAPPING            0x00000008C8   /* PMO only */
+#define A_BCM1480_PM_PMO_MAPPING        (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
+/*
+ * Interrupt mapping registers
+ */
+#define A_BCM1480_PMI_INT_0                 0x0010056800
+#define A_BCM1480_PMI_INT(q)                (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMI_INT_OFFSET_0          (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_INT_0                 0x0010057800
+#define A_BCM1480_PMO_INT(q)                (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMO_INT_OFFSET_0          (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
+/*
+ * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
+ */
+#define R_BCM1480_PM_INT_ST                 0x0000000000
+#define R_BCM1480_PM_INT_MSK                0x0000000040
+#define R_BCM1480_PM_INT_CLR                0x0000000080
+#define R_BCM1480_PM_MRGD_INT               0x00000000C0
+/*
+ * Debug registers (global)
+ */
+#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI    0x0010056000
+#define A_BCM1480_PM_GLOBALDEBUG_PID        0x00100567F8
+#define A_BCM1480_PM_GLOBALDEBUG_PIB        0x0010056FF8
+#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO    0x0010057000
+#define A_BCM1480_PM_GLOBALDEBUG_POD        0x00100577F8
+#define A_BCM1480_PM_GLOBALDEBUG_POB        0x0010057FF8
+/*  *********************************************************************
+    *  Switch performance counters
+    ********************************************************************* */
+#define A_BCM1480_SWPERF_CFG    0xdfb91800
+#define A_BCM1480_SWPERF_CNT0   0xdfb91880
+#define A_BCM1480_SWPERF_CNT1   0xdfb91888
+#define A_BCM1480_SWPERF_CNT2   0xdfb91890
+#define A_BCM1480_SWPERF_CNT3   0xdfb91898
+/*  *********************************************************************
+    *  Switch Trace Unit
+    ********************************************************************* */
+#define A_BCM1480_SWTRC_MATCH_CONTROL_0         0xDFB91000
+#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0      0xDFB91100
+#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0       0xDFB91108
+#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0       0xDFB91200
+#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0        0xDFB91208
+#define A_BCM1480_SWTRC_EVENT_0                 0xDFB91300
+#define A_BCM1480_SWTRC_SEQUENCE_0              0xDFB91400
+#define A_BCM1480_SWTRC_CFG                     0xDFB91500
+#define A_BCM1480_SWTRC_READ                    0xDFB91508
+#define A_BCM1480_SWDEBUG_SCHEDSTOP             0xDFB92000
+#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
+#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
+#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))
+#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))
+/*  *********************************************************************
+    *  High-Speed Port Registers (Section 13)
+    ********************************************************************* */
+#define A_BCM1480_HSP_BASE_0                0x00DF810000
+#define A_BCM1480_HSP_BASE_1                0x00DF890000
+#define A_BCM1480_HSP_BASE_2                0x00DF910000
+#define BCM1480_HSP_REGISTER_SPACING        0x80000
+#define A_BCM1480_HSP_BASE(idx)             (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
+#define A_BCM1480_HSP_REGISTER(idx,reg)     (A_BCM1480_HSP_BASE(idx) + (reg))
+#define R_BCM1480_HSP_RX_SPI4_CFG_0           0x0000000000
+#define R_BCM1480_HSP_RX_SPI4_CFG_1           0x0000000008
+#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
+#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
+#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN     0x0000000020
+#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028
+#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0      0x0000000200
+#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1      0x0000000208
+#define R_BCM1480_HSP_RX_PLL_CNFG             0x0000000800
+#define R_BCM1480_HSP_RX_CALIBRATION          0x0000000808
+#define R_BCM1480_HSP_RX_TEST                 0x0000000810
+#define R_BCM1480_HSP_RX_DIAG_DETAILS         0x0000000818
+#define R_BCM1480_HSP_RX_DIAG_CRC_0           0x0000000820
+#define R_BCM1480_HSP_RX_DIAG_CRC_1           0x0000000828
+#define R_BCM1480_HSP_RX_DIAG_HTCMD           0x0000000830
+#define R_BCM1480_HSP_RX_DIAG_PKTCTL          0x0000000838
+#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER   0x0000000870
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0       0x0000020020
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1       0x0000020028
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2       0x0000020030
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3       0x0000020038
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4       0x0000020040
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5       0x0000020048
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6       0x0000020050
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7       0x0000020058
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
+/* XXX Following registers were shuffled.  Renamed/renumbered per errata. */
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_0      0x0000020078
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_1      0x0000020080
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_2      0x0000020088
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_3      0x0000020090
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_4      0x0000020098
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_5      0x00000200A0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_0      0x00000200B0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_1      0x00000200B8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_2      0x00000200C0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_3      0x00000200C8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_4      0x00000200D0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_5      0x00000200D8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_6      0x00000200E0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_7      0x00000200E8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx)   (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
+#define R_BCM1480_HSP_RX_VIS_CMDQ_0           0x00000200F0
+#define R_BCM1480_HSP_RX_VIS_CMDQ_1           0x00000200F8
+#define R_BCM1480_HSP_RX_VIS_CMDQ_2           0x0000020100
+#define R_BCM1480_HSP_RX_RAM_READCTL          0x0000020108
+#define R_BCM1480_HSP_RX_RAM_READWINDOW       0x0000020110
+#define R_BCM1480_HSP_RX_RF_READCTL           0x0000020118
+#define R_BCM1480_HSP_RX_RF_READWINDOW        0x0000020120
+#define R_BCM1480_HSP_TX_SPI4_CFG_0           0x0000040000
+#define R_BCM1480_HSP_TX_SPI4_CFG_1           0x0000040008
+#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT    0x0000040010
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0       0x0000040020
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1       0x0000040028
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2       0x0000040030
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3       0x0000040038
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4       0x0000040040
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5       0x0000040048
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6       0x0000040050
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7       0x0000040058
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_NPC_RAMALLOC         0x0000040078
+#define R_BCM1480_HSP_TX_RSP_RAMALLOC         0x0000040080
+#define R_BCM1480_HSP_TX_PC_RAMALLOC          0x0000040088
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0      0x0000040090
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1      0x0000040098
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2      0x00000400A0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0      0x00000400B0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1      0x00000400B8
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2      0x00000400C0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3      0x00000400C8
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT       0x00000400D0
+#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT       0x00000400D8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0      0x00000400E0
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1      0x00000400E8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2      0x00000400F0
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3      0x00000400F8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT       0x0000040100
+#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT       0x0000040108
+#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0      0x0000040200
+#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1      0x0000040208
+#define R_BCM1480_HSP_TX_PLL_CNFG             0x0000040800
+#define R_BCM1480_HSP_TX_CALIBRATION          0x0000040808
+#define R_BCM1480_HSP_TX_TEST                 0x0000040810
+#define R_BCM1480_HSP_TX_VIS_CMDQ_0           0x0000040840
+#define R_BCM1480_HSP_TX_VIS_CMDQ_1           0x0000040848
+#define R_BCM1480_HSP_TX_VIS_CMDQ_2           0x0000040850
+#define R_BCM1480_HSP_TX_RAM_READCTL          0x0000040860
+#define R_BCM1480_HSP_TX_RAM_READWINDOW       0x0000040868
+#define R_BCM1480_HSP_TX_RF_READCTL           0x0000040870
+#define R_BCM1480_HSP_TX_RF_READWINDOW        0x0000040878
+#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
+#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN     0x0000040888
+#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
+#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x)  (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
+/*  *********************************************************************
+    *  Physical Address Map (Table 10 and Figure 7)
+    ********************************************************************* */
+#define A_BCM1480_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
+#define A_BCM1480_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
+#define A_BCM1480_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
+#define A_BCM1480_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
+#define A_BCM1480_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
+#define A_BCM1480_PHYS_GENBUS_END               _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES     _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES     _SB_MAKE64(0x0029000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES       _SB_MAKE64(0x002C000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES      _SB_MAKE64(0x002E000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES     _SB_MAKE64(0x002F000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES      _SB_MAKE64(0x0030000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES       _SB_MAKE64(0x0040000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS        _SB_MAKE64(0x0060000000)
+#define A_BCM1480_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
+#define A_BCM1480_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS      _SB_MAKE64(0x00A8000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS      _SB_MAKE64(0x00A9000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS        _SB_MAKE64(0x00AC000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS       _SB_MAKE64(0x00AE000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS      _SB_MAKE64(0x00AF000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS       _SB_MAKE64(0x00B0000000)
+#define A_BCM1480_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
+#define A_BCM1480_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES   _SB_MAKE64(0x00D8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES        _SB_MAKE64(0x00DC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES       _SB_MAKE64(0x00DE000000)
+#define A_BCM1480_PHYS_HS_SUBSYS                _SB_MAKE64(0x00DF000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS    _SB_MAKE64(0x00F8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BITS         _SB_MAKE64(0x00FC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS        _SB_MAKE64(0x00FE000000)
+#define A_BCM1480_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
+#define A_BCM1480_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
+#define A_BCM1480_PHYS_PCI_UPPER                _SB_MAKE64(0x1000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES     _SB_MAKE64(0x2000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS      _SB_MAKE64(0x3000000000)
+#define A_BCM1480_PHYS_HT_NODE_ALIAS            _SB_MAKE64(0x4000000000)
+#define A_BCM1480_PHYS_HT_FULLACCESS            _SB_MAKE64(0xF000000000)
+/*  *********************************************************************
+    *  L2 Cache as RAM (Table 54)
+    ********************************************************************* */
+#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
+#define BCM1480_PHYS_L2CACHE_NUM_WAYS           8
+#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000100000)
+#define A_BCM1480_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0300000)
+#define A_BCM1480_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D0320000)
+#define A_BCM1480_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D0340000)
+#define A_BCM1480_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D0360000)
+#define A_BCM1480_PHYS_L2CACHE_WAY4             _SB_MAKE64(0x00D0380000)
+#define A_BCM1480_PHYS_L2CACHE_WAY5             _SB_MAKE64(0x00D03A0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY6             _SB_MAKE64(0x00D03C0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY7             _SB_MAKE64(0x00D03E0000)
+#endif /* _BCM1480_REGS_H */
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h
new file mode 100644
index 000000000000..648bed96780f
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_scd.h
@@ -0,0 +1,436 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1400 Board Support Package
+    *
+    *  SCD Constants and Macros                     File: bcm1480_scd.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the System Control and Debug module.
+    *
+    *  BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+#ifndef _BCM1480_SCD_H
+#define _BCM1480_SCD_H
+#include "sb1250_defs.h"
+/*  *********************************************************************
+    *  Pull in the BCM1250's SCD since lots of stuff is the same.
+    ********************************************************************* */
+#include "sb1250_scd.h"
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  This file is basically a "what's new" header file.  Since the
+    *  BCM1250 and the new BCM1480 (and derivatives) share many common
+    *  features, this file contains only what's new or changed from
+    *  the 1250.  (above, you can see that we include the 1250 symbols
+    *  to get the base functionality).
+    *
+    *  In software, be sure to use the correct symbols, particularly
+    *  for blocks that are different between the two chip families.
+    *  All BCM1480-specific symbols have _BCM1480_ in their names,
+    *  and all BCM1250-specific and "base" functions that are common in
+    *  both chips have no special names (this is for compatibility with
+    *  older include files).  Therefore, if you're working with the
+    *  SCD, which is very different on each chip, A_SCD_xxx implies
+    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
+    *  version.
+    ********************************************************************* */
+/*  *********************************************************************
+    *  System control/debug registers
+    ********************************************************************* */
+/*
+ * System Identification and Revision Register (Table 12)
+ * Register: SCD_SYSTEM_REVISION
+ * This register is field compatible with the 1250.
+ */
+/*
+ * New part definitions
+ */
+#define K_SYS_PART_BCM1480          0x1406
+#define K_SYS_PART_BCM1280          0x1206
+#define K_SYS_PART_BCM1455          0x1407
+#define K_SYS_PART_BCM1255          0x1257
+/*
+ * Manufacturing Information Register (Table 14)
+ * Register: SCD_SYSTEM_MANUF
+ */
+/*
+ * System Configuration Register (Table 15)
+ * Register: SCD_SYSTEM_CFG
+ * Entire register is different from 1250, all new constants below
+ */
+#define M_BCM1480_SYS_RESERVED0             _SB_MAKEMASK1(0)
+#define M_BCM1480_SYS_HT_MINRSTCNT          _SB_MAKEMASK1(1)
+#define M_BCM1480_SYS_RESERVED2             _SB_MAKEMASK1(2)
+#define M_BCM1480_SYS_RESERVED3             _SB_MAKEMASK1(3)
+#define M_BCM1480_SYS_RESERVED4             _SB_MAKEMASK1(4)
+#define M_BCM1480_SYS_IOB_DIV               _SB_MAKEMASK1(5)
+#define S_BCM1480_SYS_PLL_DIV               _SB_MAKE64(6)
+#define M_BCM1480_SYS_PLL_DIV               _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV)
+#define V_BCM1480_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV)
+#define G_BCM1480_SYS_PLL_DIV(x)            _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV)
+#define S_BCM1480_SYS_SW_DIV                _SB_MAKE64(11)
+#define M_BCM1480_SYS_SW_DIV                _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV)
+#define V_BCM1480_SYS_SW_DIV(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV)
+#define G_BCM1480_SYS_SW_DIV(x)             _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV)
+#define M_BCM1480_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
+#define M_BCM1480_SYS_DUART1_ENABLE         _SB_MAKEMASK1(17)
+#define S_BCM1480_SYS_BOOT_MODE             _SB_MAKE64(18)
+#define M_BCM1480_SYS_BOOT_MODE             _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE)
+#define V_BCM1480_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE)
+#define G_BCM1480_SYS_BOOT_MODE(x)          _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE)
+#define K_BCM1480_SYS_BOOT_MODE_ROM32       0
+#define K_BCM1480_SYS_BOOT_MODE_ROM8        1
+#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
+#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3
+#define M_BCM1480_SYS_BOOT_MODE_SMBUS       _SB_MAKEMASK1(19)
+#define M_BCM1480_SYS_PCI_HOST              _SB_MAKEMASK1(20)
+#define M_BCM1480_SYS_PCI_ARBITER           _SB_MAKEMASK1(21)
+#define M_BCM1480_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
+#define M_BCM1480_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
+#define M_BCM1480_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(24)
+#define M_BCM1480_SYS_RESERVED25            _SB_MAKEMASK1(25)
+#define S_BCM1480_SYS_CONFIG                26
+#define M_BCM1480_SYS_CONFIG                _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG)
+#define V_BCM1480_SYS_CONFIG(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG)
+#define G_BCM1480_SYS_CONFIG(x)             _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG)
+#define M_BCM1480_SYS_RESERVED32            _SB_MAKEMASK(32,15)
+#define S_BCM1480_SYS_NODEID                47
+#define M_BCM1480_SYS_NODEID                _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID)
+#define V_BCM1480_SYS_NODEID(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID)
+#define G_BCM1480_SYS_NODEID(x)             _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID)
+#define M_BCM1480_SYS_CCNUMA_EN             _SB_MAKEMASK1(51)
+#define M_BCM1480_SYS_CPU_RESET_0           _SB_MAKEMASK1(52)
+#define M_BCM1480_SYS_CPU_RESET_1           _SB_MAKEMASK1(53)
+#define M_BCM1480_SYS_CPU_RESET_2           _SB_MAKEMASK1(54)
+#define M_BCM1480_SYS_CPU_RESET_3           _SB_MAKEMASK1(55)
+#define S_BCM1480_SYS_DISABLECPU0           56
+#define M_BCM1480_SYS_DISABLECPU0           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
+#define S_BCM1480_SYS_DISABLECPU1           57
+#define M_BCM1480_SYS_DISABLECPU1           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
+#define S_BCM1480_SYS_DISABLECPU2           58
+#define M_BCM1480_SYS_DISABLECPU2           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
+#define S_BCM1480_SYS_DISABLECPU3           59
+#define M_BCM1480_SYS_DISABLECPU3           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
+#define M_BCM1480_SYS_SB_SOFTRES            _SB_MAKEMASK1(60)
+#define M_BCM1480_SYS_EXT_RESET             _SB_MAKEMASK1(61)
+#define M_BCM1480_SYS_SYSTEM_RESET          _SB_MAKEMASK1(62)
+#define M_BCM1480_SYS_SW_FLAG               _SB_MAKEMASK1(63)
+/*
+ * Scratch Register (Table 16)
+ * Register: SCD_SYSTEM_SCRATCH
+ * Same as BCM1250
+ */
+/*
+ * Mailbox Registers (Table 17)
+ * Registers: SCD_MBOX_{0,1}_CPU_x
+ * Same as BCM1250
+ */
+/*
+ * See bcm1480_int.h for interrupt mapper registers.
+ */
+/*
+ * Watchdog Timer Initial Count Registers (Table 23)
+ * Registers: SCD_WDOG_INIT_CNT_x
+ *
+ * The watchdogs are almost the same as the 1250, except
+ * the configuration register has more bits to control the
+ * other CPUs.
+ */
+/*
+ * Watchdog Timer Configuration Registers (Table 25)
+ * Registers: SCD_WDOG_CFG_x
+ */
+#define M_BCM1480_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)
+#define S_BCM1480_SCD_WDOG_RESET_TYPE       2
+#define M_BCM1480_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE)
+#define K_BCM1480_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
+#define K_BCM1480_SCD_WDOG_RESET_SOFT       1
+#define K_BCM1480_SCD_WDOG_RESET_CPU0       3
+#define K_BCM1480_SCD_WDOG_RESET_CPU1       5
+#define K_BCM1480_SCD_WDOG_RESET_CPU2       9
+#define K_BCM1480_SCD_WDOG_RESET_CPU3       17
+#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
+#define M_BCM1480_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(8)
+/*
+ * General Timer Initial Count Registers (Table 26)
+ * Registers: SCD_TIMER_INIT_x
+ *
+ * The timer registers are the same as the BCM1250
+ */
+/*
+ * ZBbus Count Register (Table 29)
+ * Register: ZBBUS_CYCLE_COUNT
+ *
+ * Same as BCM1250
+ */
+/*
+ * ZBbus Compare Registers (Table 30)
+ * Registers: ZBBUS_CYCLE_CPx
+ *
+ * Same as BCM1250
+ */
+/*
+ * System Performance Counter Configuration Register (Table 31)
+ * Register: PERF_CNT_CFG_0
+ *
+ * Since the clear/enable bits are moved compared to the
+ * 1250 and there are more fields, this register will be BCM1480 specific.
+ */
+#define S_BCM1480_SPC_CFG_SRC0              0
+#define M_BCM1480_SPC_CFG_SRC0              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0)
+#define V_BCM1480_SPC_CFG_SRC0(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0)
+#define G_BCM1480_SPC_CFG_SRC0(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0)
+#define S_BCM1480_SPC_CFG_SRC1              8
+#define M_BCM1480_SPC_CFG_SRC1              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1)
+#define V_BCM1480_SPC_CFG_SRC1(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1)
+#define G_BCM1480_SPC_CFG_SRC1(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1)
+#define S_BCM1480_SPC_CFG_SRC2              16
+#define M_BCM1480_SPC_CFG_SRC2              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2)
+#define V_BCM1480_SPC_CFG_SRC2(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2)
+#define G_BCM1480_SPC_CFG_SRC2(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2)
+#define S_BCM1480_SPC_CFG_SRC3              24
+#define M_BCM1480_SPC_CFG_SRC3              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3)
+#define V_BCM1480_SPC_CFG_SRC3(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3)
+#define G_BCM1480_SPC_CFG_SRC3(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3)
+#define S_BCM1480_SPC_CFG_SRC4              32
+#define M_BCM1480_SPC_CFG_SRC4              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4)
+#define V_BCM1480_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4)
+#define G_BCM1480_SPC_CFG_SRC4(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4)
+#define S_BCM1480_SPC_CFG_SRC5              40
+#define M_BCM1480_SPC_CFG_SRC5              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5)
+#define V_BCM1480_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5)
+#define G_BCM1480_SPC_CFG_SRC5(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5)
+#define S_BCM1480_SPC_CFG_SRC6              48
+#define M_BCM1480_SPC_CFG_SRC6              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6)
+#define V_BCM1480_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6)
+#define G_BCM1480_SPC_CFG_SRC6(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6)
+#define S_BCM1480_SPC_CFG_SRC7              56
+#define M_BCM1480_SPC_CFG_SRC7              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7)
+#define V_BCM1480_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7)
+#define G_BCM1480_SPC_CFG_SRC7(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7)
+/*
+ * System Performance Counter Control Register (Table 32)
+ * Register: PERF_CNT_CFG_1
+ * BCM1480 specific
+ */
+#define M_BCM1480_SPC_CFG_CLEAR             _SB_MAKEMASK1(0)
+#define M_BCM1480_SPC_CFG_ENABLE            _SB_MAKEMASK1(1)
+/*
+ * System Performance Counters (Table 33)
+ * Registers: PERF_CNT_x
+ */
+#define S_BCM1480_SPC_CNT_COUNT             0
+#define M_BCM1480_SPC_CNT_COUNT             _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT)
+#define V_BCM1480_SPC_CNT_COUNT(x)          _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT)
+#define G_BCM1480_SPC_CNT_COUNT(x)          _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT)
+#define M_BCM1480_SPC_CNT_OFLOW             _SB_MAKEMASK1(40)
+/*
+ * Bus Watcher Error Status Register (Tables 36, 37)
+ * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
+ * Same as BCM1250.
+ */
+/*
+ * Bus Watcher Error Data Registers (Table 38)
+ * Registers: BUS_ERR_DATA_x
+ * Same as BCM1250.
+ */
+/*
+ * Bus Watcher L2 ECC Counter Register (Table 39)
+ * Register: BUS_L2_ERRORS
+ * Same as BCM1250.
+ */
+/*
+ * Bus Watcher Memory and I/O Error Counter Register (Table 40)
+ * Register: BUS_MEM_IO_ERRORS
+ * Same as BCM1250.
+ */
+/*
+ * Address Trap Registers
+ *
+ * Register layout same as BCM1250, almost.  The bus agents
+ * are different, and the address trap configuration bits are
+ * slightly different.
+ */
+#define M_BCM1480_ATRAP_INDEX             _SB_MAKEMASK(4,0)
+#define M_BCM1480_ATRAP_ADDRESS           _SB_MAKEMASK(40,0)
+#define S_BCM1480_ATRAP_CFG_CNT            0
+#define M_BCM1480_ATRAP_CFG_CNT            _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT)
+#define V_BCM1480_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT)
+#define G_BCM1480_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT)
+#define M_BCM1480_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
+#define M_BCM1480_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
+#define M_BCM1480_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
+#define M_BCM1480_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
+#define M_BCM1480_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
+#define S_BCM1480_ATRAP_CFG_AGENTID     8
+#define M_BCM1480_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID)
+#define V_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID)
+#define G_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID)
+#define K_BCM1480_BUS_AGENT_CPU0            0
+#define K_BCM1480_BUS_AGENT_CPU1            1
+#define K_BCM1480_BUS_AGENT_NC              2
+#define K_BCM1480_BUS_AGENT_IOB             3
+#define K_BCM1480_BUS_AGENT_SCD             4
+#define K_BCM1480_BUS_AGENT_L2C             6
+#define K_BCM1480_BUS_AGENT_MC              7
+#define K_BCM1480_BUS_AGENT_CPU2            8
+#define K_BCM1480_BUS_AGENT_CPU3            9
+#define K_BCM1480_BUS_AGENT_PM              10
+#define S_BCM1480_ATRAP_CFG_CATTR           12
+#define M_BCM1480_ATRAP_CFG_CATTR           _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR)
+#define V_BCM1480_ATRAP_CFG_CATTR(x)        _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR)
+#define G_BCM1480_ATRAP_CFG_CATTR(x)        _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR)
+#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0
+#define K_BCM1480_ATRAP_CFG_CATTR_UNC       1
+#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
+#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
+#define M_BCM1480_ATRAP_CFG_CATTRINV        _SB_MAKEMASK1(14)
+/*
+ * Trace Event Registers (Table 47)
+ * Same as BCM1250.
+ */
+/*
+ * Trace Sequence Control Registers (Table 48)
+ * Registers: TRACE_SEQUENCE_x
+ *
+ * Same as BCM1250 except for two new fields.
+ */
+#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
+#define S_BCM1480_SCD_TRSEQ_SWFUNC          26
+#define M_BCM1480_SCD_TRSEQ_SWFUNC          _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define V_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define G_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC)
+/*
+ * Trace Control Register (Table 49)
+ * Register: TRACE_CFG
+ *
+ * Bits 0..8 are the same as the BCM1250, rest are different.
+ * Entire register is redefined below.
+ */
+#define M_BCM1480_SCD_TRACE_CFG_RESET       _SB_MAKEMASK1(0)
+#define M_BCM1480_SCD_TRACE_CFG_START_READ  _SB_MAKEMASK1(1)
+#define M_BCM1480_SCD_TRACE_CFG_START       _SB_MAKEMASK1(2)
+#define M_BCM1480_SCD_TRACE_CFG_STOP        _SB_MAKEMASK1(3)
+#define M_BCM1480_SCD_TRACE_CFG_FREEZE      _SB_MAKEMASK1(4)
+#define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
+#define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL  _SB_MAKEMASK1(6)
+#define M_BCM1480_SCD_TRACE_CFG_FULL        _SB_MAKEMASK1(7)
+#define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT   _SB_MAKEMASK1(8)
+#define S_BCM1480_SCD_TRACE_CFG_MODE        16
+#define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)
+#define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)
+#define G_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE)
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS   0
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
+#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID    2
+#define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR    24
+#define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR    _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
+#define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
+#define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
+#endif /* _BCM1480_SCD_H */
diff --git a/include/asm-mips/sibyte/bigsur.h b/include/asm-mips/sibyte/bigsur.h
new file mode 100644
index 000000000000..ebefe797fc1d
--- /dev/null
+++ b/include/asm-mips/sibyte/bigsur.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_BIGSUR_H
+#define __ASM_SIBYTE_BIGSUR_H
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/bcm1480_int.h>
+#ifdef CONFIG_SIBYTE_BIGSUR
+#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
+#define SIBYTE_HAVE_PCMCIA 1
+#define SIBYTE_HAVE_IDE    1
+#endif
+/* Generic bus chip selects */
+#define LEDS_CS         3
+#define LEDS_PHYS       0x100a0000
+#ifdef SIBYTE_HAVE_IDE
+#define IDE_CS          4
+#define IDE_PHYS        0x100b0000
+#define K_GPIO_GB_IDE   4
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+#ifdef SIBYTE_HAVE_PCMCIA
+#define PCMCIA_CS       6
+#define PCMCIA_PHYS     0x11000000
+#define K_GPIO_PC_READY 9
+#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#endif
+#endif /* __ASM_SIBYTE_BIGSUR_H */
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index d7b11b6c7c32..900edcbeec37 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -21,8 +21,6 @@
 #include <linux/config.h>
-#ifdef CONFIG_SIBYTE_BOARD
 #if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
    defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
    defined(CONFIG_SIBYTE_LITTLESUR)
@@ -37,6 +35,10 @@
 #include <asm/sibyte/carmel.h>
 #endif
+#ifdef CONFIG_SIBYTE_BIGSUR
+#include <asm/sibyte/bigsur.h>
+#endif
 #ifdef __ASSEMBLY__
 #ifdef LEDS_PHYS
@@ -54,16 +56,6 @@
 #define setleds(t0,t1,c0,c1,c2,c3)
 #endif /* LEDS_PHYS */
-#else
-#ifdef LEDS_PHYS
-extern void setleds(char *str);
-#else
-#define setleds(s) do { } while (0)
-#endif /* LEDS_PHYS */
 #endif /* __ASSEMBLY__ */
-#endif /* CONFIG_SIBYTE_BOARD */
 #endif /* _SIBYTE_BOARD_H */
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
index d62da4e2dd36..a474c29cd701 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -27,6 +27,9 @@
 #define SB1250_NR_IRQS 64
+#define BCM1480_NR_IRQS                 128
+#define BCM1480_NR_IRQS_HALF            64
 #define SB1250_DUART_MINOR_BASE         64
 #ifndef __ASSEMBLY__
@@ -35,6 +38,7 @@
 /* For revision/pass information */
 #include <asm/sibyte/sb1250_scd.h>
+#include <asm/sibyte/bcm1480_scd.h>
 extern unsigned int sb1_pass;
 extern unsigned int soc_pass;
 extern unsigned int soc_type;
@@ -46,6 +50,13 @@ extern unsigned long sb1250_gettimeoffset(void);
 extern void sb1250_mask_irq(int cpu, int irq);
 extern void sb1250_unmask_irq(int cpu, int irq);
 extern void sb1250_smp_finish(void);
+extern void bcm1480_time_init(void);
+extern unsigned long bcm1480_gettimeoffset(void);
+extern void bcm1480_mask_irq(int cpu, int irq);
+extern void bcm1480_unmask_irq(int cpu, int irq);
+extern void bcm1480_smp_finish(void);
 extern void prom_printf(char *fmt, ...);
 #define AT_spin \
@@ -58,6 +69,6 @@ extern void prom_printf(char *fmt, ...);
 #endif
-#define IOADDR(a) (IO_BASE + (a))
+#define IOADDR(a) ((volatile void __iomem *)(IO_BASE + (a)))
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 40ef97c76c8b..335dbaf1d831 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
@@ -97,13 +95,17 @@
    *  ordering, so be careful when adding support for new minor revs.
    ********************************************************************* */
-#define SIBYTE_HDR_FMASK_1250_ALL               0x00000ff
+#define SIBYTE_HDR_FMASK_1250_ALL               0x000000ff
-#define SIBYTE_HDR_FMASK_1250_PASS1             0x0000001
+#define SIBYTE_HDR_FMASK_1250_PASS1             0x00000001
-#define SIBYTE_HDR_FMASK_1250_PASS2             0x0000002
+#define SIBYTE_HDR_FMASK_1250_PASS2             0x00000002
-#define SIBYTE_HDR_FMASK_1250_PASS3             0x0000004
+#define SIBYTE_HDR_FMASK_1250_PASS3             0x00000004
+#define SIBYTE_HDR_FMASK_112x_ALL               0x00000f00
+#define SIBYTE_HDR_FMASK_112x_PASS1             0x00000100
-#define SIBYTE_HDR_FMASK_112x_ALL               0x0000f00
+#define SIBYTE_HDR_FMASK_1480_ALL               0x0000f000
-#define SIBYTE_HDR_FMASK_112x_PASS1             0x0000100
+#define SIBYTE_HDR_FMASK_1480_PASS1             0x00001000
+#define SIBYTE_HDR_FMASK_1480_PASS2             0x00002000
 /* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
 #define SIBYTE_HDR_FMASK(chip, pass)                                    \
@@ -111,8 +113,17 @@
 #define SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
    (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
+/* Default constant value for all chips, all revisions */
 #define SIBYTE_HDR_FMASK_ALL                                            \
+    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL              \
+     | SIBYTE_HDR_FMASK_1480_ALL)
+/* This one is used for the "original" BCM1250/BCM112x chips.  We use this
+   to weed out constants and macros that do not exist on later chips like
+   the BCM1480  */
+#define SIBYTE_HDR_FMASK_1250_112x_ALL                                  \
    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
+#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
 #ifndef SIBYTE_HDR_FEATURES
 #define SIBYTE_HDR_FEATURES                     SIBYTE_HDR_FMASK_ALL
@@ -133,6 +144,12 @@
 #define SIBYTE_HDR_FEATURE_CHIP(chip)                                   \
    (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
+/* True for all versions of the BCM1250 and BCM1125, but not true for
+   anything else */
+#define SIBYTE_HDR_FEATURE_1250_112x \
+      (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
+/*    (!!  (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
 /* True if header features enabled for that rev or later, inclusive.  */
 #define SIBYTE_HDR_FEATURE(chip, pass)                                  \
    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index 3cdb48f50ed0..e6145f524fbd 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -7,9 +7,8 @@
    *  programming the SB1250's DMA controllers, both the data mover
    *  and the Ethernet DMA.
    *
-    *  SB1250 specification level:  User's manual 1/02/02
+    *  SB1250 specification level:  User's manual 10/21/02
-    *
+    *  BCM1280 specification level: User's manual 11/24/03
-    *  Author:  Mitch Lichtenberg
    *
    *********************************************************************
    *
@@ -58,17 +57,17 @@
 #define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
 #define S_DMA_DESC_TYPE             _SB_MAKE64(1)
-#define M_DMA_DESC_TYPE             _SB_MAKE64(2,S_DMA_DESC_TYPE)
+#define M_DMA_DESC_TYPE             _SB_MAKEMASK(2,S_DMA_DESC_TYPE)
 #define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
 #define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
 #define K_DMA_DESC_TYPE_RING_AL         0
 #define K_DMA_DESC_TYPE_CHAIN_AL        1
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define K_DMA_DESC_TYPE_RING_UAL_WI     2
 #define K_DMA_DESC_TYPE_RING_UAL_RMW    3
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
 #define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
@@ -111,11 +110,11 @@
 #define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
 #define M_DMA_L2CA                  _SB_MAKEMASK1(5)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DMA_RX_XTRA_STATUS        _SB_MAKEMASK1(6)
 #define M_DMA_TX_CPU_PAUSE          _SB_MAKEMASK1(6)
 #define M_DMA_TX_FC_PAUSE_EN        _SB_MAKEMASK1(7)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define M_DMA_MBZ1                  _SB_MAKEMASK(6,15)
@@ -165,14 +164,14 @@
 #define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
 #define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DMA_TX_CH_PAUSE_ON        _SB_MAKEMASK1(56)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 /*
 * Receive Packet Drop Registers
 */
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_OODLOST_RX           _SB_MAKE64(0)
 #define M_DMA_OODLOST_RX           _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
 #define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
@@ -180,7 +179,7 @@
 #define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
 #define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
 #define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 /*  *********************************************************************
    *  DMA Descriptors
@@ -201,21 +200,21 @@
 #define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
 #define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
 #define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
 #define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
 #define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRA_DSCR_CNT        _SB_MAKE64(40)
 #define M_DMA_DSCRA_DSCR_CNT        _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
 #define G_DMA_DSCRA_DSCR_CNT(x)     _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
 #define M_DMA_DSCRA_OFFSETB         _SB_MAKEMASK1(50)
@@ -235,12 +234,12 @@
 #define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
 #define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
 #define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
 #define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
 #define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
@@ -255,12 +254,12 @@
 #define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
 #define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
 #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
 #define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
@@ -282,15 +281,16 @@
 #define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
 #define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-/* Note: BADTCPCS is actually in DSCR_B options field */
+/* Note: This bit is in the DSCR_B options field */
 #define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/* Note: These bits are in the DSCR_B options field */
 #define M_DMA_ETH_VLAN_FLAG     _SB_MAKEMASK1(1)
 #define M_DMA_ETH_CRC_FLAG      _SB_MAKEMASK1(2)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define S_DMA_ETHRX_RXCH            53
 #define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
@@ -438,7 +438,7 @@
                                     M_DM_CUR_DSCR_DSCR_COUNT)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 /*
 * Data Mover Channel Partial Result Registers
 * Register: DM_PARTIAL_0
@@ -459,10 +459,10 @@
                                       M_DM_PARTIAL_TCPCS_PARTIAL)
 #define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 /*
 * Data Mover CRC Definition Registers
 * Register: CRC_DEF_0
@@ -479,10 +479,10 @@
 #define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
 #define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
                                       M_CRC_DEF_CRC_POLY)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 /*
 * Data Mover CRC/Checksum Definition Registers
 * Register: CTCP_DEF_0
@@ -511,7 +511,7 @@
 #define K_CTCP_DEF_CRC_WIDTH_1        2
 #define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 /*
@@ -560,12 +560,12 @@
 #define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
 #define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DM_DSCRA_RD_BKOFF         _SB_MAKEMASK1(52)
 #define M_DM_DSCRA_WR_BKOFF         _SB_MAKEMASK1(53)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
 #define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
 #define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
@@ -574,7 +574,7 @@
 #define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
 #define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
 #define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3,61)
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
index f1f509f295c4..1b5cbc5c6454 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -6,9 +6,8 @@
    *  This module contains constants and macros useful for
    *  manipulating the SB1250's Generic Bus interface
    *
-    *  SB1250 specification level:  User's manual 1/02/02
+    *  SB1250 specification level:  User's manual 10/21/02
-    *
+    *  BCM1280 specification level: User's Manual 11/14/03
-    *  Author:  Mitch Lichtenberg
    *
    *********************************************************************
    *
@@ -51,19 +50,21 @@
 #define M_IO_WIDTH_SEL          _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
 #define K_IO_WIDTH_SEL_1        0
 #define K_IO_WIDTH_SEL_2        1
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define K_IO_WIDTH_SEL_1L       2
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define K_IO_WIDTH_SEL_4        3
 #define V_IO_WIDTH_SEL(x)       _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
 #define G_IO_WIDTH_SEL(x)       _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
 #define S_IO_PARITY_ENA         4
 #define M_IO_PARITY_ENA         _SB_MAKEMASK1(S_IO_PARITY_ENA)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_IO_BURST_EN           5
 #define M_IO_BURST_EN           _SB_MAKEMASK1(S_IO_BURST_EN)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define S_IO_PARITY_ODD         6
 #define M_IO_PARITY_ODD         _SB_MAKEMASK1(S_IO_PARITY_ODD)
 #define S_IO_NONMUX             7
@@ -96,8 +97,11 @@
 #define S_IO_ADDRBASE           16       /* # bits to shift addr for this reg */
+#define M_IO_BLK_CACHE          _SB_MAKEMASK1(15)
 /*
- * Generic Bus Region 0 Timing Registers (Table 11-7)
+ * Generic Bus Timing 0 Registers (Table 11-7)
 */
 #define S_IO_ALE_WIDTH          0
@@ -105,21 +109,23 @@
 #define V_IO_ALE_WIDTH(x)       _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
 #define G_IO_ALE_WIDTH(x)       _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_IO_EARLY_CS           _SB_MAKEMASK1(3)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define S_IO_ALE_TO_CS          4
 #define M_IO_ALE_TO_CS          _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
 #define V_IO_ALE_TO_CS(x)       _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
 #define G_IO_ALE_TO_CS(x)       _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_IO_BURST_WIDTH           _SB_MAKE64(6)
 #define M_IO_BURST_WIDTH           _SB_MAKEMASK(2,S_IO_BURST_WIDTH)
 #define V_IO_BURST_WIDTH(x)        _SB_MAKEVALUE(x,S_IO_BURST_WIDTH)
 #define G_IO_BURST_WIDTH(x)        _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define S_IO_CS_WIDTH           8
 #define M_IO_CS_WIDTH           _SB_MAKEMASK(5,S_IO_CS_WIDTH)
@@ -141,9 +147,10 @@
 #define V_IO_ALE_TO_WRITE(x)    _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
 #define G_IO_ALE_TO_WRITE(x)    _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_IO_RDY_SYNC           _SB_MAKEMASK1(3)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define S_IO_WRITE_WIDTH        4
 #define M_IO_WRITE_WIDTH        _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
@@ -183,9 +190,127 @@
 #define M_IO_TIMEOUT_INT        _SB_MAKEMASK1(10)
 #define M_IO_ILL_ADDR_INT       _SB_MAKEMASK1(11)
 #define M_IO_MULT_CS_INT        _SB_MAKEMASK1(12)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_IO_COH_ERR            _SB_MAKEMASK1(14)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+/*
+ * Generic Bus Output Drive Control Register 0 (Table 14-18)
+ */
+#define S_IO_SLEW0              0
+#define M_IO_SLEW0              _SB_MAKEMASK(2,S_IO_SLEW0)
+#define V_IO_SLEW0(x)           _SB_MAKEVALUE(x,S_IO_SLEW0)
+#define G_IO_SLEW0(x)           _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0)
+#define S_IO_DRV_A              2
+#define M_IO_DRV_A              _SB_MAKEMASK(2,S_IO_DRV_A)
+#define V_IO_DRV_A(x)           _SB_MAKEVALUE(x,S_IO_DRV_A)
+#define G_IO_DRV_A(x)           _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A)
+#define S_IO_DRV_B              6
+#define M_IO_DRV_B              _SB_MAKEMASK(2,S_IO_DRV_B)
+#define V_IO_DRV_B(x)           _SB_MAKEVALUE(x,S_IO_DRV_B)
+#define G_IO_DRV_B(x)           _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B)
+#define S_IO_DRV_C              10
+#define M_IO_DRV_C              _SB_MAKEMASK(2,S_IO_DRV_C)
+#define V_IO_DRV_C(x)           _SB_MAKEVALUE(x,S_IO_DRV_C)
+#define G_IO_DRV_C(x)           _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C)
+#define S_IO_DRV_D              14
+#define M_IO_DRV_D              _SB_MAKEMASK(2,S_IO_DRV_D)
+#define V_IO_DRV_D(x)           _SB_MAKEVALUE(x,S_IO_DRV_D)
+#define G_IO_DRV_D(x)           _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D)
+/*
+ * Generic Bus Output Drive Control Register 1 (Table 14-19)
+ */
+#define S_IO_DRV_E              2
+#define M_IO_DRV_E              _SB_MAKEMASK(2,S_IO_DRV_E)
+#define V_IO_DRV_E(x)           _SB_MAKEVALUE(x,S_IO_DRV_E)
+#define G_IO_DRV_E(x)           _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E)
+#define S_IO_DRV_F              6
+#define M_IO_DRV_F              _SB_MAKEMASK(2,S_IO_DRV_F)
+#define V_IO_DRV_F(x)           _SB_MAKEVALUE(x,S_IO_DRV_F)
+#define G_IO_DRV_F(x)           _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F)
+#define S_IO_SLEW1              8
+#define M_IO_SLEW1              _SB_MAKEMASK(2,S_IO_SLEW1)
+#define V_IO_SLEW1(x)           _SB_MAKEVALUE(x,S_IO_SLEW1)
+#define G_IO_SLEW1(x)           _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1)
+#define S_IO_DRV_G              10
+#define M_IO_DRV_G              _SB_MAKEMASK(2,S_IO_DRV_G)
+#define V_IO_DRV_G(x)           _SB_MAKEVALUE(x,S_IO_DRV_G)
+#define G_IO_DRV_G(x)           _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G)
+#define S_IO_SLEW2              12
+#define M_IO_SLEW2              _SB_MAKEMASK(2,S_IO_SLEW2)
+#define V_IO_SLEW2(x)           _SB_MAKEVALUE(x,S_IO_SLEW2)
+#define G_IO_SLEW2(x)           _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2)
+#define S_IO_DRV_H              14
+#define M_IO_DRV_H              _SB_MAKEMASK(2,S_IO_DRV_H)
+#define V_IO_DRV_H(x)           _SB_MAKEVALUE(x,S_IO_DRV_H)
+#define G_IO_DRV_H(x)           _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H)
+/*
+ * Generic Bus Output Drive Control Register 2 (Table 14-20)
+ */
+#define S_IO_DRV_J              2
+#define M_IO_DRV_J              _SB_MAKEMASK(2,S_IO_DRV_J)
+#define V_IO_DRV_J(x)           _SB_MAKEVALUE(x,S_IO_DRV_J)
+#define G_IO_DRV_J(x)           _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J)
+#define S_IO_DRV_K              6
+#define M_IO_DRV_K              _SB_MAKEMASK(2,S_IO_DRV_K)
+#define V_IO_DRV_K(x)           _SB_MAKEVALUE(x,S_IO_DRV_K)
+#define G_IO_DRV_K(x)           _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K)
+#define S_IO_DRV_L              10
+#define M_IO_DRV_L              _SB_MAKEMASK(2,S_IO_DRV_L)
+#define V_IO_DRV_L(x)           _SB_MAKEVALUE(x,S_IO_DRV_L)
+#define G_IO_DRV_L(x)           _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L)
+#define S_IO_DRV_M              14
+#define M_IO_DRV_M              _SB_MAKEMASK(2,S_IO_DRV_M)
+#define V_IO_DRV_M(x)           _SB_MAKEVALUE(x,S_IO_DRV_M)
+#define G_IO_DRV_M(x)           _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M)
+/*
+ * Generic Bus Output Drive Control Register 3 (Table 14-21)
+ */
+#define S_IO_SLEW3              0
+#define M_IO_SLEW3              _SB_MAKEMASK(2,S_IO_SLEW3)
+#define V_IO_SLEW3(x)           _SB_MAKEVALUE(x,S_IO_SLEW3)
+#define G_IO_SLEW3(x)           _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3)
+#define S_IO_DRV_N              2
+#define M_IO_DRV_N              _SB_MAKEMASK(2,S_IO_DRV_N)
+#define V_IO_DRV_N(x)           _SB_MAKEVALUE(x,S_IO_DRV_N)
+#define G_IO_DRV_N(x)           _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N)
+#define S_IO_DRV_P              6
+#define M_IO_DRV_P              _SB_MAKEMASK(2,S_IO_DRV_P)
+#define V_IO_DRV_P(x)           _SB_MAKEVALUE(x,S_IO_DRV_P)
+#define G_IO_DRV_P(x)           _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P)
+#define S_IO_DRV_Q              10
+#define M_IO_DRV_Q              _SB_MAKEMASK(2,S_IO_DRV_Q)
+#define V_IO_DRV_Q(x)           _SB_MAKEVALUE(x,S_IO_DRV_Q)
+#define G_IO_DRV_Q(x)           _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q)
+#define S_IO_DRV_R              14
+#define M_IO_DRV_R              _SB_MAKEMASK(2,S_IO_DRV_R)
+#define V_IO_DRV_R(x)           _SB_MAKEVALUE(x,S_IO_DRV_R)
+#define G_IO_DRV_R(x)           _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R)
 /*
 * PCMCIA configuration register (Table 12-6)
@@ -202,6 +327,22 @@
 #define M_PCMCIA_CFG_RDYMASK    _SB_MAKEMASK1(8)
 #define M_PCMCIA_CFG_PWRCTL     _SB_MAKEMASK1(9)
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_PCMCIA_MODE           16
+#define M_PCMCIA_MODE           _SB_MAKEMASK(3,S_PCMCIA_MODE)
+#define V_PCMCIA_MODE(x)        _SB_MAKEVALUE(x,S_PCMCIA_MODE)
+#define G_PCMCIA_MODE(x)        _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE)
+#define K_PCMCIA_MODE_PCMA_NOB  0       /* standard PCMCIA "A", no "B" */
+#define K_PCMCIA_MODE_IDEA_NOB  1       /* IDE "A", no "B" */
+#define K_PCMCIA_MODE_PCMIOA_NOB 2      /* PCMCIA with I/O "A", no "B" */
+#define K_PCMCIA_MODE_PCMA_PCMB 4       /* standard PCMCIA "A", standard PCMCIA "B" */
+#define K_PCMCIA_MODE_IDEA_PCMB 5       /* IDE "A", standard PCMCIA "B" */
+#define K_PCMCIA_MODE_PCMA_IDEB 6       /* standard PCMCIA "A", IDE "B" */
+#define K_PCMCIA_MODE_IDEA_IDEB 7       /* IDE "A", IDE "B" */
+#endif
 /*
 * PCMCIA status register (Table 12-7)
 */
@@ -272,5 +413,62 @@
 #define V_GPIO_INTR_TYPE14(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
 #define G_GPIO_INTR_TYPE14(x)   _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * GPIO Interrupt Additional Type Register
+ */
+#define K_GPIO_INTR_BOTHEDGE    0
+#define K_GPIO_INTR_RISEEDGE    1
+#define K_GPIO_INTR_UNPRED1     2
+#define K_GPIO_INTR_UNPRED2     3
+#define S_GPIO_INTR_ATYPEX(n)   (((n)/2)*2)
+#define M_GPIO_INTR_ATYPEX(n)   _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n))
+#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n))
+#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n))
+#define S_GPIO_INTR_ATYPE0      0
+#define M_GPIO_INTR_ATYPE0      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0)
+#define V_GPIO_INTR_ATYPE0(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0)
+#define G_GPIO_INTR_ATYPE0(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0)
+#define S_GPIO_INTR_ATYPE2      2
+#define M_GPIO_INTR_ATYPE2      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2)
+#define V_GPIO_INTR_ATYPE2(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2)
+#define G_GPIO_INTR_ATYPE2(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2)
+#define S_GPIO_INTR_ATYPE4      4
+#define M_GPIO_INTR_ATYPE4      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4)
+#define V_GPIO_INTR_ATYPE4(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4)
+#define G_GPIO_INTR_ATYPE4(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4)
+#define S_GPIO_INTR_ATYPE6      6
+#define M_GPIO_INTR_ATYPE6      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6)
+#define V_GPIO_INTR_ATYPE6(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6)
+#define G_GPIO_INTR_ATYPE6(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6)
+#define S_GPIO_INTR_ATYPE8      8
+#define M_GPIO_INTR_ATYPE8      _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8)
+#define V_GPIO_INTR_ATYPE8(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8)
+#define G_GPIO_INTR_ATYPE8(x)   _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8)
+#define S_GPIO_INTR_ATYPE10     10
+#define M_GPIO_INTR_ATYPE10     _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10)
+#define V_GPIO_INTR_ATYPE10(x)  _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10)
+#define G_GPIO_INTR_ATYPE10(x)  _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10)
+#define S_GPIO_INTR_ATYPE12     12
+#define M_GPIO_INTR_ATYPE12     _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12)
+#define V_GPIO_INTR_ATYPE12(x)  _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12)
+#define G_GPIO_INTR_ATYPE12(x)  _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12)
+#define S_GPIO_INTR_ATYPE14     14
+#define M_GPIO_INTR_ATYPE14     _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14)
+#define V_GPIO_INTR_ATYPE14(x)  _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14)
+#define G_GPIO_INTR_ATYPE14(x)  _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14)
+#endif
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index e173e2ea4c98..05c7b39f1b02 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
@@ -47,6 +45,10 @@
 * First, the interrupt numbers.
 */
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define K_INT_SOURCES               64
 #define K_INT_WATCHDOG_TIMER_0      0
 #define K_INT_WATCHDOG_TIMER_1      1
 #define K_INT_TIMER_0               2
@@ -244,4 +246,6 @@
 #define M_LDTVECT_RAISEMBOX             0x40
+#endif  /* 1250/112x */
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
index 8afe8e01581b..842f205094af 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
@@ -89,8 +87,13 @@
 #define V_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
 #define G_L2C_MGMT_WAY(x)           _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
-#define S_L2C_MGMT_TAG              21
+#define S_L2C_MGMT_ECC_DIAG         21
-#define M_L2C_MGMT_TAG              _SB_MAKEMASK(6,S_L2C_MGMT_TAG)
+#define M_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG)
+#define V_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG)
+#define G_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG)
+#define S_L2C_MGMT_TAG              23
+#define M_L2C_MGMT_TAG              _SB_MAKEMASK(4,S_L2C_MGMT_TAG)
 #define V_L2C_MGMT_TAG(x)           _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
 #define G_L2C_MGMT_TAG(x)           _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
index f2617ded0a8f..7092535d1108 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index 18e74e43f4a2..adfc688fa559 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
@@ -81,7 +79,10 @@
 #define M_MAC_RESERVED1             _SB_MAKEMASK(8,9)
 #define M_MAC_AP_STAT_EN            _SB_MAKEMASK1(17)
-#define M_MAC_RESERVED2             _SB_MAKEMASK1(18)
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TIMESTAMP             _SB_MAKEMASK1(18)
+#endif
 #define M_MAC_DRP_ERRPKT_EN         _SB_MAKEMASK1(19)
 #define M_MAC_DRP_FCSERRPKT_EN      _SB_MAKEMASK1(20)
 #define M_MAC_DRP_CODEERRPKT_EN     _SB_MAKEMASK1(21)
@@ -132,9 +133,9 @@
 #define M_MAC_RX_CH_SEL_MSB         _SB_MAKEMASK1(44)
 #endif /* 1250 PASS2 || 112x PASS1 */
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_SPLIT_CH_SEL          _SB_MAKEMASK1(45)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define S_MAC_BYPASS_IFG            _SB_MAKE64(46)
 #define M_MAC_BYPASS_IFG            _SB_MAKEMASK(8,S_MAC_BYPASS_IFG)
@@ -176,10 +177,22 @@
 #define M_MAC_PORT_RESET            _SB_MAKEMASK1(8)
+#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
 #define M_MAC_RX_ENABLE             _SB_MAKEMASK1(10)
 #define M_MAC_TX_ENABLE             _SB_MAKEMASK1(11)
 #define M_MAC_BYP_RX_ENABLE         _SB_MAKEMASK1(12)
 #define M_MAC_BYP_TX_ENABLE         _SB_MAKEMASK1(13)
+#endif
+/*
+ * MAC reset information register (1280/1255)
+ */
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_RX_CH0_PAUSE_ON   _SB_MAKEMASK1(8)
+#define M_MAC_RX_CH1_PAUSE_ON   _SB_MAKEMASK1(16)
+#define M_MAC_TX_CH0_PAUSE_ON   _SB_MAKEMASK1(24)
+#define M_MAC_TX_CH1_PAUSE_ON   _SB_MAKEMASK1(32)
+#endif
 /*
 * MAC DMA Control Register
@@ -267,12 +280,12 @@
 #define V_MAC_IFG_RX(x)             _SB_MAKEVALUE(x,S_MAC_IFG_RX)
 #define G_MAC_IFG_RX(x)             _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_MAC_PRE_LEN               _SB_MAKE64(0)
 #define M_MAC_PRE_LEN               _SB_MAKEMASK(6,S_MAC_PRE_LEN)
 #define V_MAC_PRE_LEN(x)            _SB_MAKEVALUE(x,S_MAC_PRE_LEN)
 #define G_MAC_PRE_LEN(x)            _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define S_MAC_IFG_TX                _SB_MAKE64(6)
 #define M_MAC_IFG_TX                _SB_MAKEMASK(6,S_MAC_IFG_TX)
@@ -458,9 +471,9 @@
 #define V_MAC_COUNTER_ADDR(x)       _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)
 #define G_MAC_COUNTER_ADDR(x)       _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_TX_PAUSE_ON           _SB_MAKEMASK1(52)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 /*
 * MAC Fifo Pointer Registers (Table 9-19)    [Debug register]
@@ -594,7 +607,7 @@
 #define V_MAC_IPHDR_OFFSET(x)   _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)
 #define G_MAC_IPHDR_OFFSET(x)   _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_MAC_RX_CRC_OFFSET     _SB_MAKE64(16)
 #define M_MAC_RX_CRC_OFFSET     _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)
 #define V_MAC_RX_CRC_OFFSET(x)  _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)
@@ -612,7 +625,7 @@
 #define M_MAC_RX_CH_MSN_SEL     _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)
 #define V_MAC_RX_CH_MSN_SEL(x)  _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)
 #define G_MAC_RX_CH_MSN_SEL(x)  _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)
-#endif /* 1250 PASS3 || 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 /*
 * MAC Receive Channel Select Registers (Table 9-25)
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 1dd41c927996..26e421498c97 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
@@ -324,6 +322,10 @@
 #define K_MC_tRFC_DEFAULT         12
 #define V_MC_tRFC_DEFAULT         V_MC_tRFC(K_MC_tRFC_DEFAULT)
+#if SIBYTE_HDR_FEATURE(1250, PASS3)
+#define M_MC_tRFC_PLUS16          _SB_MAKEMASK1(51)     /* 1250C3 and later.  */
+#endif
 #define S_MC_tCwCr                40
 #define M_MC_tCwCr                _SB_MAKEMASK(4,S_MC_tCwCr)
 #define V_MC_tCwCr(x)             _SB_MAKEVALUE(x,S_MC_tCwCr)
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 9db80cd13a79..bab3a4580a36 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  01/02/2002
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
@@ -61,6 +59,8 @@
 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
 * since there is one reg there (but it could get its addr/offset constant).
 */
+#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
 #define A_MC_BASE_0                 0x0010051000
 #define A_MC_BASE_1                 0x0010052000
 #define MC_REGISTER_SPACING         0x1000
@@ -101,10 +101,14 @@
 #define R_MC_TEST_ECC               0x0000000420
 #define R_MC_MCLK_CFG               0x0000000500
+#endif  /* 1250 & 112x */
 /*  *********************************************************************
    * L2 Cache Control Registers
    ********************************************************************* */
+#if SIBYTE_HDR_FEATURE_1250_112x        /* This L2C only on 1250/112x */
 #define A_L2_READ_TAG               0x0010040018
 #define A_L2_ECC_TAG                0x0010040038
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
@@ -125,13 +129,16 @@
 #define A_L2_READ_ADDRESS           A_L2_READ_TAG
 #define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
+#endif
 /*  *********************************************************************
    * PCI Interface Registers
    ********************************************************************* */
+#if SIBYTE_HDR_FEATURE_1250_112x        /* This PCI/HT only on 1250/112x */
 #define A_PCI_TYPE00_HEADER         0x00DE000000
 #define A_PCI_TYPE01_HEADER         0x00DE000800
+#endif
 /*  *********************************************************************
@@ -264,15 +271,15 @@
    ********************************************************************* */
+#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
 #define R_DUART_NUM_PORTS           2
 #define A_DUART                     0x0010060000
-#define A_DUART_REG(r)
 #define DUART_CHANREG_SPACING       0x100
 #define A_DUART_CHANREG(chan,reg)   (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
 #define R_DUART_CHANREG(chan,reg)   (DUART_CHANREG_SPACING*(chan) + (reg))
+#endif  /* 1250 & 112x */
 #define R_DUART_MODE_REG_1          0x100
 #define R_DUART_MODE_REG_2          0x110
@@ -307,11 +314,13 @@
 #define DUART_IMRISR_SPACING        0x20
+#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
 #define R_DUART_IMRREG(chan)        (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
 #define R_DUART_ISRREG(chan)        (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)
 #define A_DUART_IMRREG(chan)        (A_DUART + R_DUART_IMRREG(chan))
 #define A_DUART_ISRREG(chan)        (A_DUART + R_DUART_ISRREG(chan))
+#endif  /* 1250 & 112x */
@@ -368,6 +377,8 @@
    ********************************************************************* */
+#if SIBYTE_HDR_FEATURE_1250_112x        /* sync serial only on 1250/112x */
 #define A_SER_BASE_0                0x0010060400
 #define A_SER_BASE_1                0x0010060800
 #define SER_SPACING                 0x400
@@ -457,6 +468,8 @@
 #define R_SER_RMON_RX_ERRORS        0x000001F0
 #define R_SER_RMON_RX_BADADDR       0x000001F8
+#endif  /* 1250/112x */
 /*  *********************************************************************
    * Generic Bus Registers
    ********************************************************************* */
@@ -634,12 +647,13 @@
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_SCD_SCRATCH              0x0010020C10
+#endif /* 1250 PASS2 || 112x PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define A_SCD_ZBBUS_CYCLE_COUNT    0x0010030000
 #define A_SCD_ZBBUS_CYCLE_CP0      0x0010020C00
 #define A_SCD_ZBBUS_CYCLE_CP1      0x0010020C08
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif
 /*  *********************************************************************
    * System Control Registers
@@ -667,15 +681,16 @@
 #define A_ADDR_TRAP_CFG_1           0x0010020448
 #define A_ADDR_TRAP_CFG_2           0x0010020450
 #define A_ADDR_TRAP_CFG_3           0x0010020458
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define A_ADDR_TRAP_REG_DEBUG       0x0010020460
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 /*  *********************************************************************
    * System Interrupt Mapper Registers
    ********************************************************************* */
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define A_IMR_CPU0_BASE                 0x0010020000
 #define A_IMR_CPU1_BASE                 0x0010022000
 #define IMR_REGISTER_SPACING            0x2000
@@ -700,6 +715,7 @@
 #define R_IMR_INTERRUPT_STATUS_COUNT    7
 #define R_IMR_INTERRUPT_MAP_BASE        0x0200
 #define R_IMR_INTERRUPT_MAP_COUNT       64
+#endif  /* 1250/112x */
 /*  *********************************************************************
    * System Performance Counter Registers
@@ -718,6 +734,7 @@
 #define A_SCD_BUS_ERR_STATUS        0x0010020880
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
+#define A_BUS_ERR_STATUS_DEBUG  0x00100208D0
 #endif /* 1250 PASS2 || 112x PASS1 */
 #define A_BUS_ERR_DATA_0            0x00100208A0
 #define A_BUS_ERR_DATA_1            0x00100208A8
@@ -798,6 +815,7 @@
    *  Physical Address Map
    ********************************************************************* */
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
 #define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
 #define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
@@ -831,6 +849,7 @@
 #define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
 #define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
 #define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
+#endif
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index dbbd682fb47e..a667bc14a7cd 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
@@ -51,26 +49,70 @@
 #define V_SYS_REVISION(x)           _SB_MAKEVALUE(x,S_SYS_REVISION)
 #define G_SYS_REVISION(x)           _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
-#if SIBYTE_HDR_FEATURE_CHIP(1250)
+#define K_SYS_REVISION_BCM1250_PASS1    0x01
-#define K_SYS_REVISION_BCM1250_PASS1    1
-#define K_SYS_REVISION_BCM1250_PASS2    3
+#define K_SYS_REVISION_BCM1250_PASS2    0x03
-#define K_SYS_REVISION_BCM1250_A10      11
+#define K_SYS_REVISION_BCM1250_A1       0x03    /* Pass 2.0 WB */
-#define K_SYS_REVISION_BCM1250_PASS2_2  16
+#define K_SYS_REVISION_BCM1250_A2       0x04    /* Pass 2.0 FC */
-#define K_SYS_REVISION_BCM1250_B2       17
+#define K_SYS_REVISION_BCM1250_A3       0x05    /* Pass 2.1 FC */
-#define K_SYS_REVISION_BCM1250_PASS3    32
+#define K_SYS_REVISION_BCM1250_A4       0x06    /* Pass 2.1 WB */
-#define K_SYS_REVISION_BCM1250_C1       33
+#define K_SYS_REVISION_BCM1250_A6       0x07    /* OR 0x04 (A2) w/WID != 0 */
+#define K_SYS_REVISION_BCM1250_A8       0x0b    /* A8/A10 */
+#define K_SYS_REVISION_BCM1250_A9       0x08
+#define K_SYS_REVISION_BCM1250_A10      K_SYS_REVISION_BCM1250_A8
+#define K_SYS_REVISION_BCM1250_PASS2_2  0x10
+#define K_SYS_REVISION_BCM1250_B0       K_SYS_REVISION_BCM1250_B1
+#define K_SYS_REVISION_BCM1250_B1       0x10
+#define K_SYS_REVISION_BCM1250_B2       0x11
+#define K_SYS_REVISION_BCM1250_C0       0x20
+#define K_SYS_REVISION_BCM1250_C1       0x21
+#define K_SYS_REVISION_BCM1250_C2       0x22
+#define K_SYS_REVISION_BCM1250_C3       0x23
+#if SIBYTE_HDR_FEATURE_CHIP(1250)
 /* XXX: discourage people from using these constants.  */
 #define K_SYS_REVISION_PASS1        K_SYS_REVISION_BCM1250_PASS1
 #define K_SYS_REVISION_PASS2        K_SYS_REVISION_BCM1250_PASS2
 #define K_SYS_REVISION_PASS2_2      K_SYS_REVISION_BCM1250_PASS2_2
 #define K_SYS_REVISION_PASS3        K_SYS_REVISION_BCM1250_PASS3
+#define K_SYS_REVISION_BCM1250_PASS3    K_SYS_REVISION_BCM1250_C0
 #endif /* 1250 */
-#if SIBYTE_HDR_FEATURE_CHIP(112x)
+#define K_SYS_REVISION_BCM112x_A1       0x20
-#define K_SYS_REVISION_BCM112x_A1       32
+#define K_SYS_REVISION_BCM112x_A2       0x21
-#define K_SYS_REVISION_BCM112x_A2       33
+#define K_SYS_REVISION_BCM112x_A3       0x22
-#endif /* 112x */
+#define K_SYS_REVISION_BCM112x_A4       0x23
+#define K_SYS_REVISION_BCM1480_S0       0x01
+#define K_SYS_REVISION_BCM1480_A1       0x02
+#define K_SYS_REVISION_BCM1480_A2       0x03
+#define K_SYS_REVISION_BCM1480_A3       0x04
+#define K_SYS_REVISION_BCM1480_B0       0x11
+/*Cache size - 23:20  of revision register*/
+#define S_SYS_L2C_SIZE            _SB_MAKE64(20)
+#define M_SYS_L2C_SIZE            _SB_MAKEMASK(4,S_SYS_L2C_SIZE)
+#define V_SYS_L2C_SIZE(x)         _SB_MAKEVALUE(x,S_SYS_L2C_SIZE)
+#define G_SYS_L2C_SIZE(x)         _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE)
+#define K_SYS_L2C_SIZE_1MB      0
+#define K_SYS_L2C_SIZE_512KB    5
+#define K_SYS_L2C_SIZE_256KB    2
+#define K_SYS_L2C_SIZE_128KB    1
+#define K_SYS_L2C_SIZE_BCM1250  K_SYS_L2C_SIZE_512KB
+#define K_SYS_L2C_SIZE_BCM1125  K_SYS_L2C_SIZE_256KB
+#define K_SYS_L2C_SIZE_BCM1122  K_SYS_L2C_SIZE_128KB
+/* Number of CPU cores, bits 27:24  of revision register*/
+#define S_SYS_NUM_CPUS            _SB_MAKE64(24)
+#define M_SYS_NUM_CPUS            _SB_MAKEMASK(4,S_SYS_NUM_CPUS)
+#define V_SYS_NUM_CPUS(x)         _SB_MAKEVALUE(x,S_SYS_NUM_CPUS)
+#define G_SYS_NUM_CPUS(x)         _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS)
 /* XXX: discourage people from using these constants.  */
 #define S_SYS_PART                  _SB_MAKE64(16)
@@ -83,6 +125,8 @@
 #define K_SYS_PART_BCM1120          0x1121
 #define K_SYS_PART_BCM1125          0x1123
 #define K_SYS_PART_BCM1125H         0x1124
+#define K_SYS_PART_BCM1122          0x1113
 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
 #define S_SYS_SOC_TYPE              _SB_MAKE64(16)
@@ -96,6 +140,8 @@
 #define K_SYS_SOC_TYPE_BCM1125      0x3
 #define K_SYS_SOC_TYPE_BCM1125H     0x4
 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5         /* 1250pass2 w/ 1/2 L2.  */
+#define K_SYS_SOC_TYPE_BCM1x80      0x6
+#define K_SYS_SOC_TYPE_BCM1x55      0x7
 /*
 * Calculate correct SOC type given a copy of system revision register.
@@ -127,10 +173,12 @@
 #define V_SYS_WID(x)                _SB_MAKEVALUE(x,S_SYS_WID)
 #define G_SYS_WID(x)                _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
-/* System Manufacturing Register
+/*
-* Register: SCD_SYSTEM_MANUF
+ * System Manufacturing Register
-*/
+ * Register: SCD_SYSTEM_MANUF
+ */
+#if SIBYTE_HDR_FEATURE_1250_112x
 /* Wafer ID: bits 31:0 */
 #define S_SYS_WAFERID1_200        _SB_MAKE64(0)
 #define M_SYS_WAFERID1_200        _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
@@ -139,8 +187,8 @@
 #define S_SYS_BIN                 _SB_MAKE64(32)
 #define M_SYS_BIN                 _SB_MAKEMASK(4,S_SYS_BIN)
-#define V_SYS_BIN                 _SB_MAKEVALUE(x,S_SYS_BIN)
+#define V_SYS_BIN(x)              _SB_MAKEVALUE(x,S_SYS_BIN)
-#define G_SYS_BIN                 _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
+#define G_SYS_BIN(x)              _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
 /* Wafer ID: bits 39:36 */
 #define S_SYS_WAFERID2_200        _SB_MAKE64(36)
@@ -163,12 +211,14 @@
 #define M_SYS_YPOS                _SB_MAKEMASK(6,S_SYS_YPOS)
 #define V_SYS_YPOS(x)             _SB_MAKEVALUE(x,S_SYS_YPOS)
 #define G_SYS_YPOS(x)             _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
+#endif
 /*
 * System Config Register (Table 4-2)
 * Register: SCD_SYSTEM_CFG
 */
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
 #define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
 #define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
@@ -253,6 +303,8 @@
 #define M_SYS_SW_FLAG               _SB_MAKEMASK1(63)
 #endif /* 1250 PASS2 || 112x PASS1 */
+#endif
 /*
 * Mailbox Registers (Table 4-3)
@@ -326,6 +378,7 @@
 * System Performance Counters
 */
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define S_SPC_CFG_SRC0            0
 #define M_SPC_CFG_SRC0            _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
 #define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
@@ -348,6 +401,7 @@
 #define M_SPC_CFG_CLEAR         _SB_MAKEMASK1(32)
 #define M_SPC_CFG_ENABLE        _SB_MAKEMASK1(33)
+#endif
 /*
@@ -412,6 +466,7 @@
 * Address Trap Registers
 */
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define M_ATRAP_INDEX             _SB_MAKEMASK(4,0)
 #define M_ATRAP_ADDRESS           _SB_MAKEMASK(40,0)
@@ -436,7 +491,6 @@
 #define K_BUS_AGENT_IOB0        2
 #define K_BUS_AGENT_IOB1        3
 #define K_BUS_AGENT_SCD 4
-#define K_BUS_AGENT_RESERVED    5
 #define K_BUS_AGENT_L2C 6
 #define K_BUS_AGENT_MC  7
@@ -454,10 +508,14 @@
 #define K_ATRAP_CFG_CATTR_NOTNONCOH     6
 #define K_ATRAP_CFG_CATTR_NOTCOHERENT   7
+#endif  /* 1250/112x */
 /*
 * Trace Buffer Config register
 */
+#if SIBYTE_HDR_FEATURE_1250_112x
 #define M_SCD_TRACE_CFG_RESET           _SB_MAKEMASK1(0)
 #define M_SCD_TRACE_CFG_START_READ      _SB_MAKEMASK1(1)
 #define M_SCD_TRACE_CFG_START           _SB_MAKEMASK1(2)
@@ -475,6 +533,8 @@
 #define V_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
 #define G_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
+#endif  /* 1250/112x */
 /*
 * Trace Event registers
 */
@@ -578,5 +638,7 @@
 #define M_SCD_TRSEQ_DEBUGPIN            _SB_MAKEMASK1(20)
 #define M_SCD_TRSEQ_DEBUGCPU            _SB_MAKEMASK1(21)
 #define M_SCD_TRSEQ_CLEARUSE            _SB_MAKEMASK1(22)
+#define M_SCD_TRSEQ_ALLD_A              _SB_MAKEMASK1(23)
+#define M_SCD_TRSEQ_ALL_A               _SB_MAKEMASK1(24)
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
index 335c53e92936..279a912213cd 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -6,9 +6,8 @@
    *  This module contains constants and macros useful for
    *  manipulating the SB1250's SMbus devices.
    *
-    *  SB1250 specification level:  01/02/2002
+    *  SB1250 specification level:  10/21/02
-    *
+    *  BCM1280 specification level:  11/24/03
-    *  Author:  Mitch Lichtenberg
    *
    *********************************************************************
    *
@@ -47,6 +46,7 @@
 #define K_SMB_FREQ_400KHZ           0x1F
 #define K_SMB_FREQ_100KHZ           0x7D
+#define K_SMB_FREQ_10KHZ            1250
 #define S_SMB_CMD                   0
 #define M_SMB_CMD                   _SB_MAKEMASK(8,S_SMB_CMD)
@@ -58,7 +58,11 @@
 #define M_SMB_ERR_INTR              _SB_MAKEMASK1(0)
 #define M_SMB_FINISH_INTR           _SB_MAKEMASK1(1)
-#define M_SMB_DATA_OUT              _SB_MAKEMASK1(4)
+#define S_SMB_DATA_OUT              4
+#define M_SMB_DATA_OUT              _SB_MAKEMASK1(S_SMB_DATA_OUT)
+#define V_SMB_DATA_OUT(x)           _SB_MAKEVALUE(x,S_SMB_DATA_OUT)
 #define M_SMB_DATA_DIR              _SB_MAKEMASK1(5)
 #define M_SMB_DATA_DIR_OUTPUT       M_SMB_DATA_DIR
 #define M_SMB_CLK_OUT               _SB_MAKEMASK1(6)
@@ -71,8 +75,23 @@
 #define M_SMB_BUSY                  _SB_MAKEMASK1(0)
 #define M_SMB_ERROR                 _SB_MAKEMASK1(1)
 #define M_SMB_ERROR_TYPE            _SB_MAKEMASK1(2)
-#define M_SMB_REF                   _SB_MAKEMASK1(6)
-#define M_SMB_DATA_IN               _SB_MAKEMASK1(7)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_SMB_SCL_IN                5
+#define M_SMB_SCL_IN                _SB_MAKEMASK1(S_SMB_SCL_IN)
+#define V_SMB_SCL_IN(x)             _SB_MAKEVALUE(x,S_SMB_SCL_IN)
+#define G_SMB_SCL_IN(x)             _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+#define S_SMB_REF                   6
+#define M_SMB_REF                   _SB_MAKEMASK1(S_SMB_REF)
+#define V_SMB_REF(x)                _SB_MAKEVALUE(x,S_SMB_REF)
+#define G_SMB_REF(x)                _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF)
+#define S_SMB_DATA_IN               7
+#define M_SMB_DATA_IN               _SB_MAKEMASK1(S_SMB_DATA_IN)
+#define V_SMB_DATA_IN(x)            _SB_MAKEVALUE(x,S_SMB_DATA_IN)
+#define G_SMB_DATA_IN(x)            _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN)
 /*
 * SMBus Start/Command registers (Table 14-9)
@@ -132,16 +151,14 @@
 #define V_SPEC_MB(x)                _SB_MAKEVALUE(x,S_SPEC_PEC)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_SMB_CMDH                  8
-#define M_SMB_CMDH                  _SB_MAKEMASK(8,S_SMBH_CMD)
+#define M_SMB_CMDH                  _SB_MAKEMASK(8,S_SMB_CMDH)
-#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x,S_SMBH_CMD)
+#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x,S_SMB_CMDH)
 #define M_SMB_EXTEND                _SB_MAKEMASK1(14)
-#define M_SMB_DIR                   _SB_MAKEMASK1(13)
 #define S_SMB_DFMT                  8
 #define M_SMB_DFMT                  _SB_MAKEMASK(3,S_SMB_DFMT)
 #define V_SMB_DFMT(x)               _SB_MAKEVALUE(x,S_SMB_DFMT)
@@ -165,6 +182,23 @@
 #define V_SMB_DFMT_CMD5BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
 #define V_SMB_DFMT_RESERVED         V_SMB_DFMT(K_SMB_DFMT_RESERVED)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#define S_SMB_AFMT                  11
+#define M_SMB_AFMT                  _SB_MAKEMASK(2,S_SMB_AFMT)
+#define V_SMB_AFMT(x)               _SB_MAKEVALUE(x,S_SMB_AFMT)
+#define G_SMB_AFMT(x)               _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT)
+#define K_SMB_AFMT_NONE             0
+#define K_SMB_AFMT_ADDR             1
+#define K_SMB_AFMT_ADDR_CMD1BYTE    2
+#define K_SMB_AFMT_ADDR_CMD2BYTE    3
+#define V_SMB_AFMT_NONE             V_SMB_AFMT(K_SMB_AFMT_NONE)
+#define V_SMB_AFMT_ADDR             V_SMB_AFMT(K_SMB_AFMT_ADDR)
+#define V_SMB_AFMT_ADDR_CMD1BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE)
+#define V_SMB_AFMT_ADDR_CMD2BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE)
+#define M_SMB_DIR                   _SB_MAKEMASK1(13)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
index fa2760d38b8b..dd154ac505d8 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
index 923ea4f44e0f..e87045e62bf0 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -8,8 +8,6 @@
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
-    *  Author:  Mitch Lichtenberg
-    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
@@ -240,7 +238,12 @@
 */
 #define M_DUART_ISR_TX_A            _SB_MAKEMASK1(0)
-#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(1)
+#define S_DUART_ISR_RX_A            1
+#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(S_DUART_ISR_RX_A)
+#define V_DUART_ISR_RX_A(x)         _SB_MAKEVALUE(x,S_DUART_ISR_RX_A)
+#define G_DUART_ISR_RX_A(x)         _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A)
 #define M_DUART_ISR_BRK_A           _SB_MAKEMASK1(2)
 #define M_DUART_ISR_IN_A            _SB_MAKEMASK1(3)
 #define M_DUART_ISR_TX_B            _SB_MAKEMASK1(4)
@@ -331,7 +334,7 @@
 #define M_DUART_OUT_PIN_CLR(chan) \
    (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 /*
 * Full Interrupt Control Register
 */
@@ -345,7 +348,7 @@
 #define M_DUART_INT_TIME           _SB_MAKEMASK(4,S_DUART_INT_TIME)
 #define V_DUART_INT_TIME(x)        _SB_MAKEVALUE(x,S_DUART_INT_TIME)
 #define G_DUART_INT_TIME(x)        _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME)
-#endif /* 1250 PASS2 || 112x PASS1 */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 /* ********************************************************************** */
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
index 97fa0494c30c..06e1d528e03a 100644
--- a/include/asm-mips/sibyte/swarm.h
+++ b/include/asm-mips/sibyte/swarm.h
@@ -34,7 +34,7 @@
 #define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
 #endif
 #ifdef CONFIG_SIBYTE_LITTLESUR
-#define SIBYTE_BOARD_NAME "BCM1250C2 (LittleSur)"
+#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
 #define SIBYTE_HAVE_PCMCIA 0
 #define SIBYTE_HAVE_IDE    1
 #define SIBYTE_DEFAULT_CONSOLE "cfe0"
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
index f7fbebaa0744..8edabb0be23f 100644
--- a/include/asm-mips/sigcontext.h
+++ b/include/asm-mips/sigcontext.h
@@ -27,14 +27,15 @@ struct sigcontext {
        unsigned int            sc_fpc_csr;
        unsigned int            sc_fpc_eir;     /* Unused */
        unsigned int            sc_used_math;
-        unsigned int            sc_ssflags;     /* Unused */
+        unsigned int            sc_dsp;         /* dsp status, was sc_ssflags */
        unsigned long long      sc_mdhi;
        unsigned long long      sc_mdlo;
+        unsigned long           sc_hi1;         /* Was sc_cause */
-        unsigned int            sc_cause;       /* Unused */
+        unsigned long           sc_lo1;         /* Was sc_badvaddr */
-        unsigned int            sc_badvaddr;    /* Unused */
+        unsigned long           sc_hi2;         /* Was sc_sigset[4] */
+        unsigned long           sc_lo2;
-        unsigned long           sc_sigset[4];   /* kernel's sigset_t */
+        unsigned long           sc_hi3;
+        unsigned long           sc_lo3;
 };
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
@@ -48,19 +49,19 @@ struct sigcontext {
 * Warning: this structure illdefined with sc_badvaddr being just an unsigned
 * int so it was changed to unsigned long in 2.6.0-test1.  This may break
 * binary compatibility - no prisoners.
+ * DSP ASE in 2.6.12-rc4.  Turn sc_mdhi and sc_mdlo into an array of four
+ * entries, add sc_dsp and sc_reserved for padding.  No prisoners.
 */
 struct sigcontext {
        unsigned long   sc_regs[32];
        unsigned long   sc_fpregs[32];
-        unsigned long   sc_mdhi;
+        unsigned long   sc_hi[4];
-        unsigned long   sc_mdlo;
+        unsigned long   sc_lo[4];
        unsigned long   sc_pc;
-        unsigned long   sc_badvaddr;
-        unsigned int    sc_status;
        unsigned int    sc_fpc_csr;
-        unsigned int    sc_fpc_eir;
        unsigned int    sc_used_math;
-        unsigned int    sc_cause;
+        unsigned int    sc_dsp;
+        unsigned int    sc_reserved;
 };
 #ifdef __KERNEL__
@@ -68,23 +69,24 @@ struct sigcontext {
 #include <linux/posix_types.h>
 struct sigcontext32 {
-        __u32   sc_regmask;             /* Unused */
+        __u32           sc_regmask;     /* Unused */
-        __u32   sc_status;
+        __u32           sc_status;
-        __u64   sc_pc;
+        __u64           sc_pc;
-        __u64   sc_regs[32];
+        __u64           sc_regs[32];
-        __u64   sc_fpregs[32];
+        __u64           sc_fpregs[32];
-        __u32   sc_ownedfp;             /* Unused */
+        __u32           sc_ownedfp;     /* Unused */
-        __u32   sc_fpc_csr;
+        __u32           sc_fpc_csr;
-        __u32   sc_fpc_eir;             /* Unused */
+        __u32           sc_fpc_eir;     /* Unused */
-        __u32   sc_used_math;
+        __u32           sc_used_math;
-        __u32   sc_ssflags;             /* Unused */
+        __u32           sc_dsp;         /* dsp status, was sc_ssflags */
-        __u64   sc_mdhi;
+        __u64           sc_mdhi;
-        __u64   sc_mdlo;
+        __u64           sc_mdlo;
+        __u32           sc_hi1;         /* Was sc_cause */
-        __u32   sc_cause;               /* Unused */
+        __u32           sc_lo1;         /* Was sc_badvaddr */
-        __u32   sc_badvaddr;            /* Unused */
+        __u32           sc_hi2;         /* Was sc_sigset[4] */
+        __u32           sc_lo2;
-        __u32   sc_sigset[4];           /* kernel's sigset_t */
+        __u32           sc_hi3;
+        __u32           sc_lo3;
 };
 #endif /* __KERNEL__ */
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index 698becab5a9e..2ba313d94a78 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -11,6 +11,7 @@
 #include <linux/config.h>
+#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
 #undef __ARCH_SI_TRAPNO /* exception code needs to fill this ...  */
 #define HAVE_ARCH_SIGINFO_T
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index f2c470f1d369..8ca539e80d87 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -98,12 +98,39 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
 #define MINSIGSTKSZ    2048
 #define SIGSTKSZ       8192
+#ifdef __KERNEL__
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ flag is for shared interrupt support on PCI and EISA.
+ */
+#define SA_SAMPLE_RANDOM        SA_RESTART
+#ifdef CONFIG_TRAD_SIGNALS
+#define sig_uses_siginfo(ka)    ((ka)->sa.sa_flags & SA_SIGINFO)
+#else
+#define sig_uses_siginfo(ka)    (1)
+#endif
+#endif /* __KERNEL__ */
 #define SIG_BLOCK       1       /* for blocking signals */
 #define SIG_UNBLOCK     2       /* for unblocking signals */
 #define SIG_SETMASK     3       /* for setting the signal mask */
 #define SIG_SETMASK32   256     /* Goodie from SGI for BSD compatibility:
                                   set only the low 32 bit of the sigset.  */
-#include <asm-generic/signal.h>
+/* Type of a signal handler.  */
+typedef void __signalfn_t(int);
+typedef __signalfn_t __user *__sighandler_t;
+/* Fake signal functions */
+#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
+#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
+#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
 struct sigaction {
        unsigned int    sa_flags;
diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h
index 0e00dd474afc..fb78773a5efe 100644
--- a/include/asm-mips/sn/sn0/arch.h
+++ b/include/asm-mips/sn/sn0/arch.h
@@ -74,13 +74,8 @@
 #define MAX_MEM_SLOTS   32                      /* max slots per node */
 #endif /* defined(N_MODE) */
-#if SABLE_RTL
-#define SLOT_SHIFT              (28)
-#define SLOT_MIN_MEM_SIZE       (16*1024*1024)
-#else
 #define SLOT_SHIFT              (27)
 #define SLOT_MIN_MEM_SIZE       (32*1024*1024)
-#endif
 #define CPUS_PER_NODE           2       /* CPUs on a single hub */
 #define CPUS_PER_NODE_SHFT      1       /* Bits to shift in the node number */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index 753b6620e6fa..0bb31e5aaca6 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -37,8 +37,6 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
 #define SO_ERROR        0x1007  /* get error status and clear */
 #define SO_SNDBUF       0x1001  /* Send buffer size. */
 #define SO_RCVBUF       0x1002  /* Receive buffer. */
-#define SO_SNDBUFFORCE  0x100a
-#define SO_RCVBUFFORCE  0x100b
 #define SO_SNDLOWAT     0x1003  /* send low-water mark */
 #define SO_RCVLOWAT     0x1004  /* receive low-water mark */
 #define SO_SNDTIMEO     0x1005  /* send timeout */
@@ -69,6 +67,8 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
 #define SCM_TIMESTAMP           SO_TIMESTAMP
 #define SO_PEERSEC              30
+#define SO_SNDBUFFORCE          31
+#define SO_RCVBUFFORCE          33
 #ifdef __KERNEL__
@@ -92,6 +92,7 @@ enum sock_type {
        SOCK_RAW        = 3,
        SOCK_RDM        = 4,
        SOCK_SEQPACKET  = 5,
+        SOCK_DCCP       = 6,
        SOCK_PACKET     = 10,
 };
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index 4d0135b11156..669b8e349ff2 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -9,17 +9,16 @@
 #ifndef _ASM_SPINLOCK_H
 #define _ASM_SPINLOCK_H
-#include <linux/config.h>
 #include <asm/war.h>
 /*
 * Your basic SMP spinlocks, allowing only a single CPU anywhere
 */
-#define __raw_spin_is_locked(x) ((x)->lock != 0)
+#define __raw_spin_is_locked(x)       ((x)->lock != 0)
 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
 #define __raw_spin_unlock_wait(x) \
-                do { cpu_relax(); } while ((x)->lock)
+        do { cpu_relax(); } while ((x)->lock)
 /*
 * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -119,6 +118,18 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
 * read-locks.
 */
+/*
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
+/*
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_write_can_lock(rw)        (!(rw)->lock)
 static inline void __raw_read_lock(raw_rwlock_t *rw)
 {
        unsigned int tmp;
@@ -197,8 +208,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
                "        lui    %1, 0x8000                              \n"
                "       sc      %1, %0                                  \n"
                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
+                "        sync                                           \n"
-                "       sync                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (rw->lock), "=&r" (tmp)
                : "m" (rw->lock)
@@ -211,8 +221,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
                "        lui    %1, 0x8000                              \n"
                "       sc      %1, %0                                  \n"
                "       beqz    %1, 1b                                  \n"
-                "        nop                                            \n"
+                "        sync                                           \n"
-                "       sync                                            \n"
                "       .set    reorder                                 \n"
                : "=m" (rw->lock), "=&r" (tmp)
                : "m" (rw->lock)
@@ -246,8 +255,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
                "        lui    %1, 0x8000                              \n"
                "       sc      %1, %0                                  \n"
                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
+                "        sync                                           \n"
-                "       sync                                            \n"
                "       li      %2, 1                                   \n"
                "       .set    reorder                                 \n"
                "2:                                                     \n"
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 7b5e64600bc8..a8919dcc93c8 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -60,7 +60,6 @@
                mfc0    k0, CP0_CONTEXT
                lui     k1, %hi(kernelsp)
                srl     k0, k0, 23
-                sll     k0, k0, 2
                addu    k1, k0
                LONG_L  k1, %lo(kernelsp)(k1)
 #endif
@@ -76,9 +75,14 @@
 #endif
 #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
                MFC0    k1, CP0_CONTEXT
+                lui     k0, %highest(kernelsp)
                dsrl    k1, 23
-                dsll    k1, k1, 3
+                daddiu  k0, %higher(kernelsp)
-                LONG_L  k1, kernelsp(k1)
+                dsll    k0, k0, 16
+                daddiu  k0, %hi(kernelsp)
+                dsll    k0, k0, 16
+                daddu   k1, k1, k0
+                LONG_L  k1, %lo(kernelsp)(k1)
 #endif
                .endm
@@ -86,25 +90,28 @@
 #ifdef CONFIG_32BIT
                mfc0    \temp, CP0_CONTEXT
                srl     \temp, 23
-                sll     \temp, 2
-                LONG_S  \stackp, kernelsp(\temp)
 #endif
 #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
                lw      \temp, TI_CPU(gp)
                dsll    \temp, 3
-                lui     \temp2, %hi(kernelsp)
-                daddu   \temp, \temp2
-                LONG_S  \stackp, %lo(kernelsp)(\temp)
 #endif
 #if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
-                lw      \temp, TI_CPU(gp)
+                MFC0    \temp, CP0_CONTEXT
-                dsll    \temp, 3
+                dsrl    \temp, 23
-                LONG_S  \stackp, kernelsp(\temp)
 #endif
+                LONG_S  \stackp, kernelsp(\temp)
                .endm
 #else
                .macro  get_saved_sp    /* Uniprocessor variation */
+#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
+                lui     k1, %highest(kernelsp)
+                daddiu  k1, %higher(kernelsp)
+                dsll    k1, k1, 16
+                daddiu  k1, %hi(kernelsp)
+                dsll    k1, k1, 16
+#else
                lui     k1, %hi(kernelsp)
+#endif
                LONG_L  k1, %lo(kernelsp)(k1)
                .endm
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 6663efd49b27..330c4e497af3 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -17,6 +17,7 @@
 #include <asm/addrspace.h>
 #include <asm/cpu-features.h>
+#include <asm/dsp.h>
 #include <asm/ptrace.h>
 #include <asm/war.h>
 #include <asm/interrupt.h>
@@ -70,7 +71,7 @@
 * does not enforce ordering, since there is no data dependency between
 * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
- * in cases like thiswhere there are no data dependencies.
+ * in cases like this where there are no data dependencies.
 */
 #define read_barrier_depends()  do { } while(0)
@@ -154,15 +155,15 @@ extern asmlinkage void *resume(void *last, void *next, void *next_ti);
 struct task_struct;
-#define switch_to(prev,next,last) \
+#define switch_to(prev,next,last)                                       \
-do { \
+do {                                                                    \
-        (last) = resume(prev, next, next->thread_info); \
+        if (cpu_has_dsp)                                                \
+                __save_dsp(prev);                                       \
+        (last) = resume(prev, next, next->thread_info);                 \
+        if (cpu_has_dsp)                                                \
+                __restore_dsp(current);                                 \
 } while(0)
-#define ROT_IN_PIECES                                                   \
-        "       .set    noreorder       \n"                             \
-        "       .set    reorder         \n"
 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 {
        __u32 retval;
@@ -171,14 +172,17 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                unsigned long dummy;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       .set    mips0                                   \n"
                "       move    %2, %z4                                 \n"
+                "       .set    mips3                                   \n"
                "       sc      %2, %1                                  \n"
                "       beqzl   %2, 1b                                  \n"
-                ROT_IN_PIECES
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                : "R" (*m), "Jr" (val)
                : "memory");
@@ -186,13 +190,17 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                unsigned long dummy;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       .set    mips0                                   \n"
                "       move    %2, %z4                                 \n"
+                "       .set    mips3                                   \n"
                "       sc      %2, %1                                  \n"
                "       beqz    %2, 1b                                  \n"
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                : "R" (*m), "Jr" (val)
                : "memory");
@@ -217,14 +225,15 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                unsigned long dummy;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %0, %3                  # xchg_u64      \n"
                "       move    %2, %z4                                 \n"
                "       scd     %2, %1                                  \n"
                "       beqzl   %2, 1b                                  \n"
-                ROT_IN_PIECES
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                : "R" (*m), "Jr" (val)
                : "memory");
@@ -232,6 +241,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                unsigned long dummy;
                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
                "1:     lld     %0, %3                  # xchg_u64      \n"
                "       move    %2, %z4                                 \n"
                "       scd     %2, %1                                  \n"
@@ -239,6 +249,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
+                "       .set    mips0                                   \n"
                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
                : "R" (*m), "Jr" (val)
                : "memory");
@@ -286,34 +297,41 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                __asm__ __volatile__(
+                "       .set    push                                    \n"
                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
                "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
                "       bne     %0, %z3, 2f                             \n"
+                "       .set    mips0                                   \n"
                "       move    $1, %z4                                 \n"
+                "       .set    mips3                                   \n"
                "       sc      $1, %1                                  \n"
                "       beqzl   $1, 1b                                  \n"
-                ROT_IN_PIECES
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
                "2:                                                     \n"
-                "       .set    at                                      \n"
+                "       .set    pop                                     \n"
                : "=&r" (retval), "=m" (*m)
                : "R" (*m), "Jr" (old), "Jr" (new)
                : "memory");
        } else if (cpu_has_llsc) {
                __asm__ __volatile__(
+                "       .set    push                                    \n"
                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
                "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
                "       bne     %0, %z3, 2f                             \n"
+                "       .set    mips0                                   \n"
                "       move    $1, %z4                                 \n"
+                "       .set    mips3                                   \n"
                "       sc      $1, %1                                  \n"
                "       beqz    $1, 1b                                  \n"
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
                "2:                                                     \n"
-                "       .set    at                                      \n"
+                "       .set    pop                                     \n"
                : "=&r" (retval), "=m" (*m)
                : "R" (*m), "Jr" (old), "Jr" (new)
                : "memory");
@@ -338,24 +356,27 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
        if (cpu_has_llsc) {
                __asm__ __volatile__(
+                "       .set    push                                    \n"
                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
                "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
                "       bne     %0, %z3, 2f                             \n"
                "       move    $1, %z4                                 \n"
                "       scd     $1, %1                                  \n"
                "       beqzl   $1, 1b                                  \n"
-                ROT_IN_PIECES
 #ifdef CONFIG_SMP
                "       sync                                            \n"
 #endif
                "2:                                                     \n"
-                "       .set    at                                      \n"
+                "       .set    pop                                     \n"
                : "=&r" (retval), "=m" (*m)
                : "R" (*m), "Jr" (old), "Jr" (new)
                : "memory");
        } else if (cpu_has_llsc) {
                __asm__ __volatile__(
+                "       .set    push                                    \n"
                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
                "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
                "       bne     %0, %z3, 2f                             \n"
                "       move    $1, %z4                                 \n"
@@ -365,7 +386,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
                "       sync                                            \n"
 #endif
                "2:                                                     \n"
-                "       .set    at                                      \n"
+                "       .set    pop                                     \n"
                : "=&r" (retval), "=m" (*m)
                : "R" (*m), "Jr" (old), "Jr" (new)
                : "memory");
@@ -406,18 +427,20 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
+extern void set_handler (unsigned long offset, void *addr, unsigned long len);
+extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
+extern void *set_vi_handler (int n, void *addr);
+extern void *set_vi_srs_handler (int n, void *addr, int regset);
 extern void *set_except_vector(int n, void *addr);
 extern void per_cpu_trap_init(void);
-extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file,
+extern NORET_TYPE void die(const char *, struct pt_regs *);
-        const char *func, unsigned long line);
-extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
-        const char *func, unsigned long line);
-#define die(msg, regs)                                                  \
+static inline void die_if_kernel(const char *str, struct pt_regs *regs)
-        __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
+{
-#define die_if_kernel(msg, regs)                                        \
+        if (unlikely(!user_mode(regs)))
-        __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
+                die(str, regs);
+}
 extern int stop_a_enabled;
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
index a70cb0854c8a..e6c24472e03f 100644
--- a/include/asm-mips/thread_info.h
+++ b/include/asm-mips/thread_info.h
@@ -26,6 +26,7 @@ struct thread_info {
        struct task_struct      *task;          /* main task structure */
        struct exec_domain      *exec_domain;   /* execution domain */
        unsigned long           flags;          /* low level flags */
+        unsigned long           tp_value;       /* thread pointer */
        __u32                   cpu;            /* current CPU */
        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
@@ -114,6 +115,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_SIGPENDING          2       /* signal pending */
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
 #define TIF_SYSCALL_AUDIT       4       /* syscall auditing active */
+#define TIF_SECCOMP             5       /* secure computing */
 #define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
 #define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
 #define TIF_MEMDIE              18
@@ -124,13 +126,14 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_USEDFPU            (1<<TIF_USEDFPU)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_WORK_MASK          0x0000ffef      /* work to do on
+/* work to do on interrupt/exception return */
-                                                   interrupt/exception return */
+#define _TIF_WORK_MASK          (0x0000ffef & ~_TIF_SECCOMP)
-#define _TIF_ALLWORK_MASK       0x8000ffff      /* work to do on any return to
+/* work to do on any return to u-space */
-                                                   u-space */
+#define _TIF_ALLWORK_MASK       (0x8000ffff & ~_TIF_SECCOMP)
 #endif /* __KERNEL__ */
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
index 179012263007..d02e019b0127 100644
--- a/include/asm-mips/traps.h
+++ b/include/asm-mips/traps.h
@@ -21,4 +21,7 @@
 extern void (*board_be_init)(void);
 extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
+extern void (*board_nmi_handler_setup)(void);
+extern void (*board_ejtag_handler_setup)(void);
 #endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
new file mode 100644
index 000000000000..0fbedafdcea8
--- /dev/null
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -0,0 +1,207 @@
+/*
+ * linux/include/asm-mips/tx4938/rbtx4938.h
+ * Definitions for TX4937/TX4938
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TX_BOARDS_RBTX4938_H
+#define __ASM_TX_BOARDS_RBTX4938_H
+#include <asm/addrspace.h>
+#include <asm/tx4938/tx4938.h>
+/* CS */
+#define RBTX4938_CE0    0x1c000000      /* 64M */
+#define RBTX4938_CE2    0x17f00000      /* 1M */
+/* Address map */
+#define RBTX4938_FPGA_REG_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00000000)
+#define RBTX4938_FPGA_REV_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00000002)
+#define RBTX4938_CONFIG1_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000004)
+#define RBTX4938_CONFIG2_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000006)
+#define RBTX4938_CONFIG3_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000008)
+#define RBTX4938_LED_ADDR       (KSEG1 + RBTX4938_CE2 + 0x00001000)
+#define RBTX4938_DIPSW_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00001002)
+#define RBTX4938_BDIPSW_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00001004)
+#define RBTX4938_IMASK_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00002000)
+#define RBTX4938_IMASK2_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002002)
+#define RBTX4938_INTPOL_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002004)
+#define RBTX4938_ISTAT_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00002006)
+#define RBTX4938_ISTAT2_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002008)
+#define RBTX4938_IMSTAT_ADDR    (KSEG1 + RBTX4938_CE2 + 0x0000200a)
+#define RBTX4938_IMSTAT2_ADDR   (KSEG1 + RBTX4938_CE2 + 0x0000200c)
+#define RBTX4938_SOFTINT_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00003000)
+#define RBTX4938_PIOSEL_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00005000)
+#define RBTX4938_SPICS_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00005002)
+#define RBTX4938_SFPWR_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00005008)
+#define RBTX4938_SFVOL_ADDR     (KSEG1 + RBTX4938_CE2 + 0x0000500a)
+#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
+#define RBTX4938_SOFTRESETLOCK_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00007002)
+#define RBTX4938_PCIRESET_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00007004)
+#define RBTX4938_ETHER_BASE     (KSEG1 + RBTX4938_CE2 + 0x00020000)
+/* Ethernet port address (Jumperless Mode (W12:Open)) */
+#define RBTX4938_ETHER_ADDR     (RBTX4938_ETHER_BASE + 0x280)
+/* bits for ISTAT/IMASK/IMSTAT */
+#define RBTX4938_INTB_PCID      0
+#define RBTX4938_INTB_PCIC      1
+#define RBTX4938_INTB_PCIB      2
+#define RBTX4938_INTB_PCIA      3
+#define RBTX4938_INTB_RTC       4
+#define RBTX4938_INTB_ATA       5
+#define RBTX4938_INTB_MODEM     6
+#define RBTX4938_INTB_SWINT     7
+#define RBTX4938_INTF_PCID      (1 << RBTX4938_INTB_PCID)
+#define RBTX4938_INTF_PCIC      (1 << RBTX4938_INTB_PCIC)
+#define RBTX4938_INTF_PCIB      (1 << RBTX4938_INTB_PCIB)
+#define RBTX4938_INTF_PCIA      (1 << RBTX4938_INTB_PCIA)
+#define RBTX4938_INTF_RTC       (1 << RBTX4938_INTB_RTC)
+#define RBTX4938_INTF_ATA       (1 << RBTX4938_INTB_ATA)
+#define RBTX4938_INTF_MODEM     (1 << RBTX4938_INTB_MODEM)
+#define RBTX4938_INTF_SWINT     (1 << RBTX4938_INTB_SWINT)
+#define rbtx4938_fpga_rev_ptr   \
+        ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
+#define rbtx4938_led_ptr        \
+        ((volatile unsigned char *)RBTX4938_LED_ADDR)
+#define rbtx4938_dipsw_ptr      \
+        ((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
+#define rbtx4938_bdipsw_ptr     \
+        ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
+#define rbtx4938_imask_ptr      \
+        ((volatile unsigned char *)RBTX4938_IMASK_ADDR)
+#define rbtx4938_imask2_ptr     \
+        ((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
+#define rbtx4938_intpol_ptr     \
+        ((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
+#define rbtx4938_istat_ptr      \
+        ((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
+#define rbtx4938_istat2_ptr     \
+        ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
+#define rbtx4938_imstat_ptr     \
+        ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
+#define rbtx4938_imstat2_ptr    \
+        ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
+#define rbtx4938_softint_ptr    \
+        ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
+#define rbtx4938_piosel_ptr     \
+        ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
+#define rbtx4938_spics_ptr      \
+        ((volatile unsigned char *)RBTX4938_SPICS_ADDR)
+#define rbtx4938_sfpwr_ptr      \
+        ((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
+#define rbtx4938_sfvol_ptr      \
+        ((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
+#define rbtx4938_softreset_ptr  \
+        ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
+#define rbtx4938_softresetlock_ptr      \
+        ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
+#define rbtx4938_pcireset_ptr   \
+        ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
+/* SPI */
+#define RBTX4938_SEEPROM1_CHIPID        0
+#define RBTX4938_SEEPROM2_CHIPID        1
+#define RBTX4938_SEEPROM3_CHIPID        2
+#define RBTX4938_SRTC_CHIPID    3
+/*
+ * IRQ mappings
+ */
+#define RBTX4938_SOFT_INT0      0       /* not used */
+#define RBTX4938_SOFT_INT1      1       /* not used */
+#define RBTX4938_IRC_INT        2
+#define RBTX4938_TIMER_INT      7
+/* These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
+ * IRQ hardware is supported.
+ */
+#define RBTX4938_NR_IRQ_LOCAL   8
+#define RBTX4938_NR_IRQ_IRC     32      /* On-Chip IRC */
+#define RBTX4938_NR_IRQ_IOC     8
+#define MI8259_IRQ_ISA_RAW_BEG   0      /* optional backplane i8259 */
+#define MI8259_IRQ_ISA_RAW_END  15
+#define TX4938_IRQ_CP0_RAW_BEG   0      /* tx4938 cpu built-in cp0 */
+#define TX4938_IRQ_CP0_RAW_END   7
+#define TX4938_IRQ_PIC_RAW_BEG   0      /* tx4938 cpu build-in pic */
+#define TX4938_IRQ_PIC_RAW_END  31
+#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG      /*  0 */
+#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END      /* 15 */
+#define TX4938_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG)     /* 16 */
+#define TX4938_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END)     /* 23 */
+#define TX4938_IRQ_PIC_BEG  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG)     /* 24 */
+#define TX4938_IRQ_PIC_END  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END)     /* 55 */
+#define TX4938_IRQ_NEST_EXT_ON_PIC  (TX4938_IRQ_PIC_BEG+2)
+#define TX4938_IRQ_NEST_PIC_ON_CP0  (TX4938_IRQ_CP0_BEG+2)
+#define TX4938_IRQ_USER0            (TX4938_IRQ_CP0_BEG+0)
+#define TX4938_IRQ_USER1            (TX4938_IRQ_CP0_BEG+1)
+#define TX4938_IRQ_CPU_TIMER        (TX4938_IRQ_CP0_BEG+7)
+#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG   0
+#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END   7
+#define TOSHIBA_RBTX4938_IRQ_IOC_BEG  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
+#define TOSHIBA_RBTX4938_IRQ_IOC_END  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
+#define RBTX4938_IRQ_LOCAL      TX4938_IRQ_CP0_BEG
+#define RBTX4938_IRQ_IRC        (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
+#define RBTX4938_IRQ_IOC        (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
+#define RBTX4938_IRQ_END        (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
+#define RBTX4938_IRQ_LOCAL_SOFT0        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
+#define RBTX4938_IRQ_LOCAL_SOFT1        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
+#define RBTX4938_IRQ_LOCAL_IRC  (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
+#define RBTX4938_IRQ_LOCAL_TIMER        (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
+#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
+#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
+#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
+#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
+#define RBTX4938_IRQ_IRC_DMA(ch,n)      (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n))
+#define RBTX4938_IRQ_IRC_PIO    (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
+#define RBTX4938_IRQ_IRC_PDMAC  (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
+#define RBTX4938_IRQ_IRC_PCIC   (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
+#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
+#define RBTX4938_IRQ_IRC_NDFMC  (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
+#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
+#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
+#define RBTX4938_IRQ_IRC_ACLC   (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
+#define RBTX4938_IRQ_IRC_ACLCPME        (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
+#define RBTX4938_IRQ_IRC_PCIC1  (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
+#define RBTX4938_IRQ_IRC_SPI    (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
+#define RBTX4938_IRQ_IOC_PCID   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
+#define RBTX4938_IRQ_IOC_PCIC   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
+#define RBTX4938_IRQ_IOC_PCIB   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
+#define RBTX4938_IRQ_IOC_PCIA   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
+#define RBTX4938_IRQ_IOC_RTC    (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
+#define RBTX4938_IRQ_IOC_ATA    (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
+#define RBTX4938_IRQ_IOC_MODEM  (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
+#define RBTX4938_IRQ_IOC_SWINT  (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
+/* IOC (PCI, etc) */
+#define RBTX4938_IRQ_IOCINT     (TX4938_IRQ_NEST_EXT_ON_PIC)
+/* Onboard 10M Ether */
+#define RBTX4938_IRQ_ETHER      (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
+#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
+#define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
+/* IRCR : Int. Control */
+#define TX4938_IRCR_LOW  0x00000000
+#define TX4938_IRCR_HIGH 0x00000001
+#define TX4938_IRCR_DOWN 0x00000002
+#define TX4938_IRCR_UP   0x00000003
+#endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h
new file mode 100644
index 000000000000..0dbbab820a5a
--- /dev/null
+++ b/include/asm-mips/tx4938/spi.h
@@ -0,0 +1,74 @@
+/*
+ * linux/include/asm-mips/tx4938/spi.h
+ * Definitions for TX4937/TX4938 SPI
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
+#define __ASM_TX_BOARDS_TX4938_SPI_H
+/* SPI */
+struct spi_dev_desc {
+        unsigned int baud;
+        unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
+        unsigned int byteorder:1;       /* 0:LSB-First, 1:MSB-First */
+        unsigned int polarity:1;        /* 0:High-Active */
+        unsigned int phase:1;           /* 0:Sample-Then-Shift */
+};
+extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
+extern void txx9_spi_irqinit(int irc_irq) __init;
+extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
+                       unsigned char **inbufs, unsigned int *incounts,
+                       unsigned char **outbufs, unsigned int *outcounts,
+                       int cansleep);
+extern int spi_eeprom_write_enable(int chipid, int enable);
+extern int spi_eeprom_read_status(int chipid);
+extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
+extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
+extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
+#define TXX9_IMCLK     (txx9_gbus_clock / 2)
+/*
+* SPI
+*/
+/* SPMCR : SPI Master Control */
+#define TXx9_SPMCR_OPMODE       0xc0
+#define TXx9_SPMCR_CONFIG       0x40
+#define TXx9_SPMCR_ACTIVE       0x80
+#define TXx9_SPMCR_SPSTP        0x02
+#define TXx9_SPMCR_BCLR 0x01
+/* SPCR0 : SPI Status */
+#define TXx9_SPCR0_TXIFL_MASK   0xc000
+#define TXx9_SPCR0_RXIFL_MASK   0x3000
+#define TXx9_SPCR0_SIDIE        0x0800
+#define TXx9_SPCR0_SOEIE        0x0400
+#define TXx9_SPCR0_RBSIE        0x0200
+#define TXx9_SPCR0_TBSIE        0x0100
+#define TXx9_SPCR0_IFSPSE       0x0010
+#define TXx9_SPCR0_SBOS 0x0004
+#define TXx9_SPCR0_SPHA 0x0002
+#define TXx9_SPCR0_SPOL 0x0001
+/* SPSR : SPI Status */
+#define TXx9_SPSR_TBSI  0x8000
+#define TXx9_SPSR_RBSI  0x4000
+#define TXx9_SPSR_TBS_MASK      0x3800
+#define TXx9_SPSR_RBS_MASK      0x0700
+#define TXx9_SPSR_SPOE  0x0080
+#define TXx9_SPSR_IFSD  0x0008
+#define TXx9_SPSR_SIDLE 0x0004
+#define TXx9_SPSR_STRDY 0x0002
+#define TXx9_SPSR_SRRDY 0x0001
+#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
new file mode 100644
index 000000000000..e25b1a0975cb
--- /dev/null
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -0,0 +1,706 @@
+/*
+ * linux/include/asm-mips/tx4938/tx4938.h
+ * Definitions for TX4937/TX4938
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TX_BOARDS_TX4938_H
+#define __ASM_TX_BOARDS_TX4938_H
+#include <asm/tx4938/tx4938_mips.h>
+#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
+#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b)
+#define TX4938_NR_IRQ_LOCAL     TX4938_IRQ_PIC_BEG
+#define TX4938_IRQ_IRC_PCIC     (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
+#define TX4938_IRQ_IRC_PCIERR   (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
+#define TX4938_PCIIO_0 0x10000000
+#define TX4938_PCIIO_1 0x01010000
+#define TX4938_PCIMEM_0 0x08000000
+#define TX4938_PCIMEM_1 0x11000000
+#define TX4938_PCIIO_SIZE_0 0x01000000
+#define TX4938_PCIIO_SIZE_1 0x00010000
+#define TX4938_PCIMEM_SIZE_0 0x08000000
+#define TX4938_PCIMEM_SIZE_1 0x00010000
+#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
+#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
+/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
+#define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
+#define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
+#define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
+#define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
+#define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
+#define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
+#define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
+#define TX4938_NR_TMR   3
+#define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
+#define TX4938_NR_SIO   2
+#define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
+#define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
+#define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
+#define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
+#define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
+#ifndef _LANGUAGE_ASSEMBLY
+#include <asm/byteorder.h>
+#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))
+#define TX4938_RD08( reg      )   (*(vu08*)(reg))
+#define TX4938_WR08( reg, val )  ((*(vu08*)(reg))=(val))
+#define TX4938_RD16( reg      )   (*(vu16*)(reg))
+#define TX4938_WR16( reg, val )  ((*(vu16*)(reg))=(val))
+#define TX4938_RD32( reg      )   (*(vu32*)(reg))
+#define TX4938_WR32( reg, val )  ((*(vu32*)(reg))=(val))
+#define TX4938_RD64( reg      )   (*(vu64*)(reg))
+#define TX4938_WR64( reg, val )  ((*(vu64*)(reg))=(val))
+#define TX4938_RD( reg      ) TX4938_RD32( reg )
+#define TX4938_WR( reg, val ) TX4938_WR32( reg, val )
+#endif /* !__ASSEMBLY__ */
+#ifdef __ASSEMBLY__
+#define _CONST64(c)     c
+#else
+#define _CONST64(c)     c##ull
+#include <asm/byteorder.h>
+#ifdef __BIG_ENDIAN
+#define endian_def_l2(e1,e2)    \
+        volatile unsigned long e1,e2
+#define endian_def_s2(e1,e2)    \
+        volatile unsigned short e1,e2
+#define endian_def_sb2(e1,e2,e3)        \
+        volatile unsigned short e1;volatile unsigned char e2,e3
+#define endian_def_b2s(e1,e2,e3)        \
+        volatile unsigned char e1,e2;volatile unsigned short e3
+#define endian_def_b4(e1,e2,e3,e4)      \
+        volatile unsigned char e1,e2,e3,e4
+#else
+#define endian_def_l2(e1,e2)    \
+        volatile unsigned long e2,e1
+#define endian_def_s2(e1,e2)    \
+        volatile unsigned short e2,e1
+#define endian_def_sb2(e1,e2,e3)        \
+        volatile unsigned char e3,e2;volatile unsigned short e1
+#define endian_def_b2s(e1,e2,e3)        \
+        volatile unsigned short e3;volatile unsigned char e2,e1
+#define endian_def_b4(e1,e2,e3,e4)      \
+        volatile unsigned char e4,e3,e2,e1
+#endif
+struct tx4938_sdramc_reg {
+        volatile unsigned long long cr[4];
+        volatile unsigned long long unused0[4];
+        volatile unsigned long long tr;
+        volatile unsigned long long unused1[2];
+        volatile unsigned long long cmd;
+        volatile unsigned long long sfcmd;
+};
+struct tx4938_ebusc_reg {
+        volatile unsigned long long cr[8];
+};
+struct tx4938_dma_reg {
+        struct tx4938_dma_ch_reg {
+                volatile unsigned long long cha;
+                volatile unsigned long long sar;
+                volatile unsigned long long dar;
+                endian_def_l2(unused0, cntr);
+                endian_def_l2(unused1, sair);
+                endian_def_l2(unused2, dair);
+                endian_def_l2(unused3, ccr);
+                endian_def_l2(unused4, csr);
+        } ch[4];
+        volatile unsigned long long dbr[8];
+        volatile unsigned long long tdhr;
+        volatile unsigned long long midr;
+        endian_def_l2(unused0, mcr);
+};
+struct tx4938_pcic_reg {
+        volatile unsigned long pciid;
+        volatile unsigned long pcistatus;
+        volatile unsigned long pciccrev;
+        volatile unsigned long pcicfg1;
+        volatile unsigned long p2gm0plbase;             /* +10 */
+        volatile unsigned long p2gm0pubase;
+        volatile unsigned long p2gm1plbase;
+        volatile unsigned long p2gm1pubase;
+        volatile unsigned long p2gm2pbase;              /* +20 */
+        volatile unsigned long p2giopbase;
+        volatile unsigned long unused0;
+        volatile unsigned long pcisid;
+        volatile unsigned long unused1;         /* +30 */
+        volatile unsigned long pcicapptr;
+        volatile unsigned long unused2;
+        volatile unsigned long pcicfg2;
+        volatile unsigned long g2ptocnt;                /* +40 */
+        volatile unsigned long unused3[15];
+        volatile unsigned long g2pstatus;               /* +80 */
+        volatile unsigned long g2pmask;
+        volatile unsigned long pcisstatus;
+        volatile unsigned long pcimask;
+        volatile unsigned long p2gcfg;          /* +90 */
+        volatile unsigned long p2gstatus;
+        volatile unsigned long p2gmask;
+        volatile unsigned long p2gccmd;
+        volatile unsigned long unused4[24];             /* +a0 */
+        volatile unsigned long pbareqport;              /* +100 */
+        volatile unsigned long pbacfg;
+        volatile unsigned long pbastatus;
+        volatile unsigned long pbamask;
+        volatile unsigned long pbabm;           /* +110 */
+        volatile unsigned long pbacreq;
+        volatile unsigned long pbacgnt;
+        volatile unsigned long pbacstate;
+        volatile unsigned long long g2pmgbase[3];               /* +120 */
+        volatile unsigned long long g2piogbase;
+        volatile unsigned long g2pmmask[3];             /* +140 */
+        volatile unsigned long g2piomask;
+        volatile unsigned long long g2pmpbase[3];               /* +150 */
+        volatile unsigned long long g2piopbase;
+        volatile unsigned long pciccfg;         /* +170 */
+        volatile unsigned long pcicstatus;
+        volatile unsigned long pcicmask;
+        volatile unsigned long unused5;
+        volatile unsigned long long p2gmgbase[3];               /* +180 */
+        volatile unsigned long long p2giogbase;
+        volatile unsigned long g2pcfgadrs;              /* +1a0 */
+        volatile unsigned long g2pcfgdata;
+        volatile unsigned long unused6[8];
+        volatile unsigned long g2pintack;
+        volatile unsigned long g2pspc;
+        volatile unsigned long unused7[12];             /* +1d0 */
+        volatile unsigned long long pdmca;              /* +200 */
+        volatile unsigned long long pdmga;
+        volatile unsigned long long pdmpa;
+        volatile unsigned long long pdmctr;
+        volatile unsigned long long pdmcfg;             /* +220 */
+        volatile unsigned long long pdmsts;
+};
+struct tx4938_aclc_reg {
+        volatile unsigned long acctlen;
+        volatile unsigned long acctldis;
+        volatile unsigned long acregacc;
+        volatile unsigned long unused0;
+        volatile unsigned long acintsts;
+        volatile unsigned long acintmsts;
+        volatile unsigned long acinten;
+        volatile unsigned long acintdis;
+        volatile unsigned long acsemaph;
+        volatile unsigned long unused1[7];
+        volatile unsigned long acgpidat;
+        volatile unsigned long acgpodat;
+        volatile unsigned long acslten;
+        volatile unsigned long acsltdis;
+        volatile unsigned long acfifosts;
+        volatile unsigned long unused2[11];
+        volatile unsigned long acdmasts;
+        volatile unsigned long acdmasel;
+        volatile unsigned long unused3[6];
+        volatile unsigned long acaudodat;
+        volatile unsigned long acsurrdat;
+        volatile unsigned long accentdat;
+        volatile unsigned long aclfedat;
+        volatile unsigned long acaudiat;
+        volatile unsigned long unused4;
+        volatile unsigned long acmodoat;
+        volatile unsigned long acmodidat;
+        volatile unsigned long unused5[15];
+        volatile unsigned long acrevid;
+};
+struct tx4938_tmr_reg {
+        volatile unsigned long tcr;
+        volatile unsigned long tisr;
+        volatile unsigned long cpra;
+        volatile unsigned long cprb;
+        volatile unsigned long itmr;
+        volatile unsigned long unused0[3];
+        volatile unsigned long ccdr;
+        volatile unsigned long unused1[3];
+        volatile unsigned long pgmr;
+        volatile unsigned long unused2[3];
+        volatile unsigned long wtmr;
+        volatile unsigned long unused3[43];
+        volatile unsigned long trr;
+};
+struct tx4938_sio_reg {
+        volatile unsigned long lcr;
+        volatile unsigned long dicr;
+        volatile unsigned long disr;
+        volatile unsigned long cisr;
+        volatile unsigned long fcr;
+        volatile unsigned long flcr;
+        volatile unsigned long bgr;
+        volatile unsigned long tfifo;
+        volatile unsigned long rfifo;
+};
+struct tx4938_pio_reg {
+        volatile unsigned long dout;
+        volatile unsigned long din;
+        volatile unsigned long dir;
+        volatile unsigned long od;
+        volatile unsigned long flag[2];
+        volatile unsigned long pol;
+        volatile unsigned long intc;
+        volatile unsigned long maskcpu;
+        volatile unsigned long maskext;
+};
+struct tx4938_irc_reg {
+        volatile unsigned long cer;
+        volatile unsigned long cr[2];
+        volatile unsigned long unused0;
+        volatile unsigned long ilr[8];
+        volatile unsigned long unused1[4];
+        volatile unsigned long imr;
+        volatile unsigned long unused2[7];
+        volatile unsigned long scr;
+        volatile unsigned long unused3[7];
+        volatile unsigned long ssr;
+        volatile unsigned long unused4[7];
+        volatile unsigned long csr;
+};
+struct tx4938_ndfmc_reg {
+        endian_def_l2(unused0, dtr);
+        endian_def_l2(unused1, mcr);
+        endian_def_l2(unused2, sr);
+        endian_def_l2(unused3, isr);
+        endian_def_l2(unused4, imr);
+        endian_def_l2(unused5, spr);
+        endian_def_l2(unused6, rstr);
+};
+struct tx4938_spi_reg {
+        volatile unsigned long mcr;
+        volatile unsigned long cr0;
+        volatile unsigned long cr1;
+        volatile unsigned long fs;
+        volatile unsigned long unused1;
+        volatile unsigned long sr;
+        volatile unsigned long dr;
+        volatile unsigned long unused2;
+};
+struct tx4938_sramc_reg {
+        volatile unsigned long long cr;
+};
+struct tx4938_ccfg_reg {
+        volatile unsigned long long ccfg;
+        volatile unsigned long long crir;
+        volatile unsigned long long pcfg;
+        volatile unsigned long long tear;
+        volatile unsigned long long clkctr;
+        volatile unsigned long long unused0;
+        volatile unsigned long long garbc;
+        volatile unsigned long long unused1;
+        volatile unsigned long long unused2;
+        volatile unsigned long long ramp;
+        volatile unsigned long long unused3;
+        volatile unsigned long long jmpadr;
+};
+#undef endian_def_l2
+#undef endian_def_s2
+#undef endian_def_sb2
+#undef endian_def_b2s
+#undef endian_def_b4
+#endif /* __ASSEMBLY__ */
+/*
+ * NDFMC
+ */
+/* NDFMCR : NDFMC Mode Control */
+#define TX4938_NDFMCR_WE        0x80
+#define TX4938_NDFMCR_ECC_ALL   0x60
+#define TX4938_NDFMCR_ECC_RESET 0x60
+#define TX4938_NDFMCR_ECC_READ  0x40
+#define TX4938_NDFMCR_ECC_ON    0x20
+#define TX4938_NDFMCR_ECC_OFF   0x00
+#define TX4938_NDFMCR_CE        0x10
+#define TX4938_NDFMCR_BSPRT     0x04
+#define TX4938_NDFMCR_ALE       0x02
+#define TX4938_NDFMCR_CLE       0x01
+/* NDFMCR : NDFMC Status */
+#define TX4938_NDFSR_BUSY       0x80
+/* NDFMCR : NDFMC Reset */
+#define TX4938_NDFRSTR_RST      0x01
+/*
+ * IRC
+ */
+#define TX4938_IR_ECCERR        0
+#define TX4938_IR_WTOERR        1
+#define TX4938_NUM_IR_INT       6
+#define TX4938_IR_INT(n)        (2 + (n))
+#define TX4938_NUM_IR_SIO       2
+#define TX4938_IR_SIO(n)        (8 + (n))
+#define TX4938_NUM_IR_DMA       4
+#define TX4938_IR_DMA(ch,n)     ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */
+#define TX4938_IR_PIO   14
+#define TX4938_IR_PDMAC 15
+#define TX4938_IR_PCIC  16
+#define TX4938_NUM_IR_TMR       3
+#define TX4938_IR_TMR(n)        (17 + (n))
+#define TX4938_IR_NDFMC 21
+#define TX4938_IR_PCIERR        22
+#define TX4938_IR_PCIPME        23
+#define TX4938_IR_ACLC  24
+#define TX4938_IR_ACLCPME       25
+#define TX4938_IR_PCIC1 26
+#define TX4938_IR_SPI   31
+#define TX4938_NUM_IR   32
+/* multiplex */
+#define TX4938_IR_ETH0  TX4938_IR_INT(4)
+#define TX4938_IR_ETH1  TX4938_IR_INT(3)
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4938_CCFG_WDRST       _CONST64(0x0000020000000000)
+#define TX4938_CCFG_WDREXEN     _CONST64(0x0000010000000000)
+#define TX4938_CCFG_BCFG_MASK   _CONST64(0x000000ff00000000)
+#define TX4938_CCFG_TINTDIS     0x01000000
+#define TX4938_CCFG_PCI66       0x00800000
+#define TX4938_CCFG_PCIMODE     0x00400000
+#define TX4938_CCFG_PCI1_66     0x00200000
+#define TX4938_CCFG_DIVMODE_MASK        0x001e0000
+#define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
+#define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
+#define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4938_CCFG_DIVMODE_10  (0xb << 17)
+#define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
+#define TX4938_CCFG_BEOW        0x00010000
+#define TX4938_CCFG_WR  0x00008000
+#define TX4938_CCFG_TOE 0x00004000
+#define TX4938_CCFG_PCIXARB     0x00002000
+#define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
+#define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
+#define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
+#define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
+#define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
+#define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
+#define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
+#define TX4938_CCFG_PCI1DMD     0x00000100
+#define TX4938_CCFG_SYSSP_MASK  0x000000c0
+#define TX4938_CCFG_ENDIAN      0x00000004
+#define TX4938_CCFG_HALT        0x00000002
+#define TX4938_CCFG_ACEHOLD     0x00000001
+/* PCFG : Pin Configuration */
+#define TX4938_PCFG_ETH0_SEL    _CONST64(0x8000000000000000)
+#define TX4938_PCFG_ETH1_SEL    _CONST64(0x4000000000000000)
+#define TX4938_PCFG_ATA_SEL     _CONST64(0x2000000000000000)
+#define TX4938_PCFG_ISA_SEL     _CONST64(0x1000000000000000)
+#define TX4938_PCFG_SPI_SEL     _CONST64(0x0800000000000000)
+#define TX4938_PCFG_NDF_SEL     _CONST64(0x0400000000000000)
+#define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4938_PCFG_SYSCLKEN    0x08000000
+#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4938_PCFG_SEL2        0x00000200
+#define TX4938_PCFG_SEL1        0x00000100
+#define TX4938_PCFG_DMASEL_ALL  0x0000000f
+#define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4938_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4938_PCFG_DMASEL1_SIO1        0x00000002
+#define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
+#define TX4938_PCFG_DMASEL2_SIO0        0x00000004
+#define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4938_PCFG_DMASEL3_SIO0        0x00000008
+/* CLKCTR : Clock Control */
+#define TX4938_CLKCTR_NDFCKD    _CONST64(0x0001000000000000)
+#define TX4938_CLKCTR_NDFRST    _CONST64(0x0000000100000000)
+#define TX4938_CLKCTR_ETH1CKD   0x80000000
+#define TX4938_CLKCTR_ETH0CKD   0x40000000
+#define TX4938_CLKCTR_SPICKD    0x20000000
+#define TX4938_CLKCTR_SRAMCKD   0x10000000
+#define TX4938_CLKCTR_PCIC1CKD  0x08000000
+#define TX4938_CLKCTR_DMA1CKD   0x04000000
+#define TX4938_CLKCTR_ACLCKD    0x02000000
+#define TX4938_CLKCTR_PIOCKD    0x01000000
+#define TX4938_CLKCTR_DMACKD    0x00800000
+#define TX4938_CLKCTR_PCICKD    0x00400000
+#define TX4938_CLKCTR_TM0CKD    0x00100000
+#define TX4938_CLKCTR_TM1CKD    0x00080000
+#define TX4938_CLKCTR_TM2CKD    0x00040000
+#define TX4938_CLKCTR_SIO0CKD   0x00020000
+#define TX4938_CLKCTR_SIO1CKD   0x00010000
+#define TX4938_CLKCTR_ETH1RST   0x00008000
+#define TX4938_CLKCTR_ETH0RST   0x00004000
+#define TX4938_CLKCTR_SPIRST    0x00002000
+#define TX4938_CLKCTR_SRAMRST   0x00001000
+#define TX4938_CLKCTR_PCIC1RST  0x00000800
+#define TX4938_CLKCTR_DMA1RST   0x00000400
+#define TX4938_CLKCTR_ACLRST    0x00000200
+#define TX4938_CLKCTR_PIORST    0x00000100
+#define TX4938_CLKCTR_DMARST    0x00000080
+#define TX4938_CLKCTR_PCIRST    0x00000040
+#define TX4938_CLKCTR_TM0RST    0x00000010
+#define TX4938_CLKCTR_TM1RST    0x00000008
+#define TX4938_CLKCTR_TM2RST    0x00000004
+#define TX4938_CLKCTR_SIO0RST   0x00000002
+#define TX4938_CLKCTR_SIO1RST   0x00000001
+/* bits for G2PSTATUS/G2PMASK */
+#define TX4938_PCIC_G2PSTATUS_ALL       0x00000003
+#define TX4938_PCIC_G2PSTATUS_TTOE      0x00000002
+#define TX4938_PCIC_G2PSTATUS_RTOE      0x00000001
+/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
+#define TX4938_PCIC_PCISTATUS_ALL       0x0000f900
+/* bits for PBACFG */
+#define TX4938_PCIC_PBACFG_FIXPA        0x00000008
+#define TX4938_PCIC_PBACFG_RPBA 0x00000004
+#define TX4938_PCIC_PBACFG_PBAEN        0x00000002
+#define TX4938_PCIC_PBACFG_BMCEN        0x00000001
+/* bits for G2PMnGBASE */
+#define TX4938_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
+#define TX4938_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
+/* bits for G2PIOGBASE */
+#define TX4938_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
+#define TX4938_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
+/* bits for PCICSTATUS/PCICMASK */
+#define TX4938_PCIC_PCICSTATUS_ALL      0x000007b8
+#define TX4938_PCIC_PCICSTATUS_PME      0x00000400
+#define TX4938_PCIC_PCICSTATUS_TLB      0x00000200
+#define TX4938_PCIC_PCICSTATUS_NIB      0x00000100
+#define TX4938_PCIC_PCICSTATUS_ZIB      0x00000080
+#define TX4938_PCIC_PCICSTATUS_PERR     0x00000020
+#define TX4938_PCIC_PCICSTATUS_SERR     0x00000010
+#define TX4938_PCIC_PCICSTATUS_GBE      0x00000008
+#define TX4938_PCIC_PCICSTATUS_IWB      0x00000002
+#define TX4938_PCIC_PCICSTATUS_E2PDONE  0x00000001
+/* bits for PCICCFG */
+#define TX4938_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
+#define TX4938_PCIC_PCICCFG_HRST        0x00000800
+#define TX4938_PCIC_PCICCFG_SRST        0x00000400
+#define TX4938_PCIC_PCICCFG_IRBER       0x00000200
+#define TX4938_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
+#define TX4938_PCIC_PCICCFG_G2PM0EN     0x00000100
+#define TX4938_PCIC_PCICCFG_G2PM1EN     0x00000080
+#define TX4938_PCIC_PCICCFG_G2PM2EN     0x00000040
+#define TX4938_PCIC_PCICCFG_G2PIOEN     0x00000020
+#define TX4938_PCIC_PCICCFG_TCAR        0x00000010
+#define TX4938_PCIC_PCICCFG_ICAEN       0x00000008
+/* bits for P2GMnGBASE */
+#define TX4938_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
+#define TX4938_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
+#define TX4938_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
+/* bits for P2GIOGBASE */
+#define TX4938_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
+#define TX4938_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
+#define TX4938_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
+#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX4938_PCIC_MAX_DEVNU   TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
+/* bits for PDMCFG */
+#define TX4938_PCIC_PDMCFG_RSTFIFO      0x00200000
+#define TX4938_PCIC_PDMCFG_EXFER        0x00100000
+#define TX4938_PCIC_PDMCFG_REQDLY_MASK  0x00003800
+#define TX4938_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_16    (1 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_32    (2 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_64    (3 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_128   (4 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_256   (5 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_512   (6 << 11)
+#define TX4938_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
+#define TX4938_PCIC_PDMCFG_ERRIE        0x00000400
+#define TX4938_PCIC_PDMCFG_NCCMPIE      0x00000200
+#define TX4938_PCIC_PDMCFG_NTCMPIE      0x00000100
+#define TX4938_PCIC_PDMCFG_CHNEN        0x00000080
+#define TX4938_PCIC_PDMCFG_XFRACT       0x00000040
+#define TX4938_PCIC_PDMCFG_BSWAP        0x00000020
+#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
+#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
+#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
+#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
+#define TX4938_PCIC_PDMCFG_XFRDIRC      0x00000002
+#define TX4938_PCIC_PDMCFG_CHRST        0x00000001
+/* bits for PDMSTS */
+#define TX4938_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
+#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
+#define TX4938_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
+#define TX4938_PCIC_PDMSTS_FIFORP_MASK  0x00030000
+#define TX4938_PCIC_PDMSTS_ERRINT       0x00000800
+#define TX4938_PCIC_PDMSTS_DONEINT      0x00000400
+#define TX4938_PCIC_PDMSTS_CHNEN        0x00000200
+#define TX4938_PCIC_PDMSTS_XFRACT       0x00000100
+#define TX4938_PCIC_PDMSTS_ACCMP        0x00000080
+#define TX4938_PCIC_PDMSTS_NCCMP        0x00000040
+#define TX4938_PCIC_PDMSTS_NTCMP        0x00000020
+#define TX4938_PCIC_PDMSTS_CFGERR       0x00000008
+#define TX4938_PCIC_PDMSTS_PCIERR       0x00000004
+#define TX4938_PCIC_PDMSTS_CHNERR       0x00000002
+#define TX4938_PCIC_PDMSTS_DATAERR      0x00000001
+#define TX4938_PCIC_PDMSTS_ALL_CMP      0x000000e0
+#define TX4938_PCIC_PDMSTS_ALL_ERR      0x0000000f
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX4938_DMA_MCR_RSFIF    0x00000080
+#define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX4938_DMA_MCR_RPRT     0x00000002
+#define TX4938_DMA_MCR_MSTEN    0x00000001
+/* bits for CCRn */
+#define TX4938_DMA_CCR_IMMCHN   0x20000000
+#define TX4938_DMA_CCR_USEXFSZ  0x10000000
+#define TX4938_DMA_CCR_LE       0x08000000
+#define TX4938_DMA_CCR_DBINH    0x04000000
+#define TX4938_DMA_CCR_SBINH    0x02000000
+#define TX4938_DMA_CCR_CHRST    0x01000000
+#define TX4938_DMA_CCR_RVBYTE   0x00800000
+#define TX4938_DMA_CCR_ACKPOL   0x00400000
+#define TX4938_DMA_CCR_REQPL    0x00200000
+#define TX4938_DMA_CCR_EGREQ    0x00100000
+#define TX4938_DMA_CCR_CHDN     0x00080000
+#define TX4938_DMA_CCR_DNCTL    0x00060000
+#define TX4938_DMA_CCR_EXTRQ    0x00010000
+#define TX4938_DMA_CCR_INTRQD   0x0000e000
+#define TX4938_DMA_CCR_INTENE   0x00001000
+#define TX4938_DMA_CCR_INTENC   0x00000800
+#define TX4938_DMA_CCR_INTENT   0x00000400
+#define TX4938_DMA_CCR_CHNEN    0x00000200
+#define TX4938_DMA_CCR_XFACT    0x00000100
+#define TX4938_DMA_CCR_SMPCHN   0x00000020
+#define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
+#define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
+#define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
+#define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
+#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
+#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
+#define TX4938_DMA_CCR_MEMIO    0x00000002
+#define TX4938_DMA_CCR_SNGAD    0x00000001
+/* bits for CSRn */
+#define TX4938_DMA_CSR_CHNEN    0x00000400
+#define TX4938_DMA_CSR_STLXFER  0x00000200
+#define TX4938_DMA_CSR_CHNACT   0x00000100
+#define TX4938_DMA_CSR_ABCHC    0x00000080
+#define TX4938_DMA_CSR_NCHNC    0x00000040
+#define TX4938_DMA_CSR_NTRNFC   0x00000020
+#define TX4938_DMA_CSR_EXTDN    0x00000010
+#define TX4938_DMA_CSR_CFERR    0x00000008
+#define TX4938_DMA_CSR_CHERR    0x00000004
+#define TX4938_DMA_CSR_DESERR   0x00000002
+#define TX4938_DMA_CSR_SORERR   0x00000001
+/* TX4938 Interrupt Controller (32-bit registers) */
+#define TX4938_IRC_BASE                 0xf510
+#define TX4938_IRC_IRFLAG0              0xf510
+#define TX4938_IRC_IRFLAG1              0xf514
+#define TX4938_IRC_IRPOL                0xf518
+#define TX4938_IRC_IRRCNT               0xf51c
+#define TX4938_IRC_IRMASKINT            0xf520
+#define TX4938_IRC_IRMASKEXT            0xf524
+#define TX4938_IRC_IRDEN                0xf600
+#define TX4938_IRC_IRDM0                0xf604
+#define TX4938_IRC_IRDM1                0xf608
+#define TX4938_IRC_IRLVL0               0xf610
+#define TX4938_IRC_IRLVL1               0xf614
+#define TX4938_IRC_IRLVL2               0xf618
+#define TX4938_IRC_IRLVL3               0xf61c
+#define TX4938_IRC_IRLVL4               0xf620
+#define TX4938_IRC_IRLVL5               0xf624
+#define TX4938_IRC_IRLVL6               0xf628
+#define TX4938_IRC_IRLVL7               0xf62c
+#define TX4938_IRC_IRMSK                0xf640
+#define TX4938_IRC_IREDC                0xf660
+#define TX4938_IRC_IRPND                0xf680
+#define TX4938_IRC_IRCS                 0xf6a0
+#define TX4938_IRC_LIMIT                0xf6ff
+#ifndef __ASSEMBLY__
+#define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
+#define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
+#define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
+#define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
+#define tx4938_ircptr           ((struct tx4938_irc_reg *)TX4938_IRC_REG)
+#define tx4938_pcicptr          ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
+#define tx4938_pcic1ptr         ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
+#define tx4938_ccfgptr          ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
+#define tx4938_tmrptr(ch)       ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
+#define tx4938_sioptr(ch)       ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
+#define tx4938_pioptr           ((struct tx4938_pio_reg *)TX4938_PIO_REG)
+#define tx4938_aclcptr          ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
+#define tx4938_spiptr           ((struct tx4938_spi_reg *)TX4938_SPI_REG)
+#define tx4938_sramcptr         ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
+#define TX4938_REV_MAJ_MIN()    ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
+#define TX4938_REV_PCODE()      ((unsigned long)tx4938_ccfgptr->crir >> 16)
+#define TX4938_SDRAMC_BA(ch)    ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
+#define TX4938_SDRAMC_SIZE(ch)  (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
+#define TX4938_EBUSC_BA(ch)     ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
+#define TX4938_EBUSC_SIZE(ch)   \
+        (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
+#endif /* !__ASSEMBLY__ */
+#endif
diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h
new file mode 100644
index 000000000000..cf89b205f103
--- /dev/null
+++ b/include/asm-mips/tx4938/tx4938_mips.h
@@ -0,0 +1,54 @@
+/*
+ * linux/include/asm-mips/tx4938/tx4938_bitmask.h
+ * Generic bitmask definitions
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef TX4938_TX4938_MIPS_H
+#define TX4938_TX4938_MIPS_H
+#ifndef __ASSEMBLY__
+#define reg_rd08(r)    ((u8 )(*((vu8 *)(r))))
+#define reg_rd16(r)    ((u16)(*((vu16*)(r))))
+#define reg_rd32(r)    ((u32)(*((vu32*)(r))))
+#define reg_rd64(r)    ((u64)(*((vu64*)(r))))
+#define reg_wr08(r,v)  ((*((vu8 *)(r)))=((u8 )(v)))
+#define reg_wr16(r,v)  ((*((vu16*)(r)))=((u16)(v)))
+#define reg_wr32(r,v)  ((*((vu32*)(r)))=((u32)(v)))
+#define reg_wr64(r,v)  ((*((vu64*)(r)))=((u64)(v)))
+typedef volatile __signed char vs8;
+typedef volatile unsigned char vu8;
+typedef volatile __signed short vs16;
+typedef volatile unsigned short vu16;
+typedef volatile __signed int vs32;
+typedef volatile unsigned int vu32;
+typedef s8 s08;
+typedef vs8 vs08;
+typedef u8 u08;
+typedef vu8 vu08;
+#if (_MIPS_SZLONG == 64)
+typedef volatile __signed__ long vs64;
+typedef volatile unsigned long vu64;
+#else
+typedef volatile __signed__ long long vs64;
+typedef volatile unsigned long long vu64;
+#endif
+#endif
+#endif
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index 5c2c98329012..41bb96bb2120 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -196,63 +196,55 @@
        __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
 struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
+#define __m(x) (*(struct __large_struct __user *)(x))
 /*
 * Yuck.  We need two variants, one for 64bit operation and one
 * for 32 bit mode and old iron.
 */
 #ifdef __mips64
-#define __GET_USER_DW(__gu_err) __get_user_asm("ld", __gu_err)
+#define __GET_USER_DW(ptr) __get_user_asm("ld", ptr)
 #else
-#define __GET_USER_DW(__gu_err) __get_user_asm_ll32(__gu_err)
+#define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr)
 #endif
 #define __get_user_nocheck(x,ptr,size)                                  \
 ({                                                                      \
-        __typeof(*(ptr)) __gu_val = 0;                                  \
+        __typeof(*(ptr)) __gu_val =  (__typeof(*(ptr))) 0;              \
-        long __gu_addr;                                                 \
        long __gu_err = 0;                                              \
                                                                        \
-        might_sleep();                                                  \
-        __gu_addr = (long) (ptr);                                       \
        switch (size) {                                                 \
-        case 1: __get_user_asm("lb", __gu_err); break;                  \
+        case 1: __get_user_asm("lb", ptr); break;                       \
-        case 2: __get_user_asm("lh", __gu_err); break;                  \
+        case 2: __get_user_asm("lh", ptr); break;                       \
-        case 4: __get_user_asm("lw", __gu_err); break;                  \
+        case 4: __get_user_asm("lw", ptr); break;                       \
-        case 8: __GET_USER_DW(__gu_err); break;                         \
+        case 8: __GET_USER_DW(ptr); break;                              \
        default: __get_user_unknown(); break;                           \
        }                                                               \
-        x = (__typeof__(*(ptr))) __gu_val;                              \
+        (x) = (__typeof__(*(ptr))) __gu_val;                            \
        __gu_err;                                                       \
 })
 #define __get_user_check(x,ptr,size)                                    \
 ({                                                                      \
+        const __typeof__(*(ptr)) __user * __gu_addr = (ptr);            \
        __typeof__(*(ptr)) __gu_val = 0;                                \
-        long __gu_addr;                                                 \
+        long __gu_err = -EFAULT;                                        \
-        long __gu_err;                                                  \
-                                                                        \
-        might_sleep();                                                  \
-        __gu_addr = (long) (ptr);                                       \
-        __gu_err = access_ok(VERIFY_READ, (void *) __gu_addr, size)     \
-                                ? 0 : -EFAULT;                          \
                                                                        \
-        if (likely(!__gu_err)) {                                        \
+        if (likely(access_ok(VERIFY_READ,  __gu_addr, size))) {         \
                switch (size) {                                         \
-                case 1: __get_user_asm("lb", __gu_err); break;          \
+                case 1: __get_user_asm("lb", __gu_addr); break;         \
-                case 2: __get_user_asm("lh", __gu_err); break;          \
+                case 2: __get_user_asm("lh", __gu_addr); break;         \
-                case 4: __get_user_asm("lw", __gu_err); break;          \
+                case 4: __get_user_asm("lw", __gu_addr); break;         \
-                case 8: __GET_USER_DW(__gu_err); break;                 \
+                case 8: __GET_USER_DW(__gu_addr); break;                \
                default: __get_user_unknown(); break;                   \
                }                                                       \
        }                                                               \
-        x = (__typeof__(*(ptr))) __gu_val;                              \
+        (x) = (__typeof__(*(ptr))) __gu_val;                            \
        __gu_err;                                                       \
 })
-#define __get_user_asm(insn,__gu_err)                                   \
+#define __get_user_asm(insn, addr)                                      \
-({                                                                      \
+{                                                                       \
        __asm__ __volatile__(                                           \
        "1:     " insn "        %1, %3                          \n"     \
        "2:                                                     \n"     \
@@ -264,20 +256,20 @@ struct __large_struct { unsigned long buf[100]; };
        "       "__UA_ADDR "\t1b, 3b                            \n"     \
        "       .previous                                       \n"     \
        : "=r" (__gu_err), "=r" (__gu_val)                              \
-        : "0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT));         \
+        : "0" (0), "o" (__m(addr)), "i" (-EFAULT));                     \
-})
+}
 /*
 * Get a long long 64 using 32 bit registers.
 */
-#define __get_user_asm_ll32(__gu_err)                                   \
+#define __get_user_asm_ll32(addr)                                       \
-({                                                                      \
+{                                                                       \
        __asm__ __volatile__(                                           \
-        "1:     lw      %1, %3                                  \n"     \
+        "1:     lw      %1, (%3)                                \n"     \
-        "2:     lw      %D1, %4                                 \n"     \
+        "2:     lw      %D1, 4(%3)                              \n"     \
        "       move    %0, $0                                  \n"     \
        "3:     .section        .fixup,\"ax\"                   \n"     \
-        "4:     li      %0, %5                                  \n"     \
+        "4:     li      %0, %4                                  \n"     \
        "       move    %1, $0                                  \n"     \
        "       move    %D1, $0                                 \n"     \
        "       j       3b                                      \n"     \
@@ -287,9 +279,8 @@ struct __large_struct { unsigned long buf[100]; };
        "       " __UA_ADDR "   2b, 4b                          \n"     \
        "       .previous                                       \n"     \
        : "=r" (__gu_err), "=&r" (__gu_val)                             \
-        : "0" (__gu_err), "o" (__m(__gu_addr)),                         \
+        : "0" (0), "r" (addr), "i" (-EFAULT));                          \
-          "o" (__m(__gu_addr + 4)), "i" (-EFAULT));                     \
+}
-})
 extern void __get_user_unknown(void);
@@ -298,25 +289,22 @@ extern void __get_user_unknown(void);
 * for 32 bit mode and old iron.
 */
 #ifdef __mips64
-#define __PUT_USER_DW(__pu_val) __put_user_asm("sd", __pu_val)
+#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
 #else
-#define __PUT_USER_DW(__pu_val) __put_user_asm_ll32(__pu_val)
+#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
 #endif
 #define __put_user_nocheck(x,ptr,size)                                  \
 ({                                                                      \
        __typeof__(*(ptr)) __pu_val;                                    \
-        long __pu_addr;                                                 \
        long __pu_err = 0;                                              \
                                                                        \
-        might_sleep();                                                  \
        __pu_val = (x);                                                 \
-        __pu_addr = (long) (ptr);                                       \
        switch (size) {                                                 \
-        case 1: __put_user_asm("sb", __pu_val); break;                  \
+        case 1: __put_user_asm("sb", ptr); break;                       \
-        case 2: __put_user_asm("sh", __pu_val); break;                  \
+        case 2: __put_user_asm("sh", ptr); break;                       \
-        case 4: __put_user_asm("sw", __pu_val); break;                  \
+        case 4: __put_user_asm("sw", ptr); break;                       \
-        case 8: __PUT_USER_DW(__pu_val); break;                         \
+        case 8: __PUT_USER_DW(ptr); break;                              \
        default: __put_user_unknown(); break;                           \
        }                                                               \
        __pu_err;                                                       \
@@ -324,30 +312,24 @@ extern void __get_user_unknown(void);
 #define __put_user_check(x,ptr,size)                                    \
 ({                                                                      \
-        __typeof__(*(ptr)) __pu_val;                                    \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
-        long __pu_addr;                                                 \
+        __typeof__(*(ptr)) __pu_val = (x);                              \
-        long __pu_err;                                                  \
+        long __pu_err = -EFAULT;                                        \
                                                                        \
-        might_sleep();                                                  \
+        if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {        \
-        __pu_val = (x);                                                 \
-        __pu_addr = (long) (ptr);                                       \
-        __pu_err = access_ok(VERIFY_WRITE, (void *) __pu_addr, size)    \
-                                ? 0 : -EFAULT;                          \
-                                                                        \
-        if (likely(!__pu_err)) {                                        \
                switch (size) {                                         \
-                case 1: __put_user_asm("sb", __pu_val); break;          \
+                case 1: __put_user_asm("sb", __pu_addr); break;         \
-                case 2: __put_user_asm("sh", __pu_val); break;          \
+                case 2: __put_user_asm("sh", __pu_addr); break;         \
-                case 4: __put_user_asm("sw", __pu_val); break;          \
+                case 4: __put_user_asm("sw", __pu_addr); break;         \
-                case 8: __PUT_USER_DW(__pu_val); break;                 \
+                case 8: __PUT_USER_DW(__pu_addr); break;                \
                default: __put_user_unknown(); break;                   \
                }                                                       \
        }                                                               \
        __pu_err;                                                       \
 })
-#define __put_user_asm(insn, __pu_val)                                  \
+#define __put_user_asm(insn, ptr)                                       \
-({                                                                      \
+{                                                                       \
        __asm__ __volatile__(                                           \
        "1:     " insn "        %z2, %3         # __put_user_asm\n"     \
        "2:                                                     \n"     \
@@ -359,18 +341,18 @@ extern void __get_user_unknown(void);
        "       " __UA_ADDR "   1b, 3b                          \n"     \
        "       .previous                                       \n"     \
        : "=r" (__pu_err)                                               \
-        : "0" (__pu_err), "Jr" (__pu_val), "o" (__m(__pu_addr)),        \
+        : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)),                     \
          "i" (-EFAULT));                                               \
-})
+}
-#define __put_user_asm_ll32(__pu_val)                                   \
+#define __put_user_asm_ll32(ptr)                                        \
-({                                                                      \
+{                                                                       \
        __asm__ __volatile__(                                           \
-        "1:     sw      %2, %3          # __put_user_asm_ll32   \n"     \
+        "1:     sw      %2, (%3)        # __put_user_asm_ll32   \n"     \
-        "2:     sw      %D2, %4                                 \n"     \
+        "2:     sw      %D2, 4(%3)                              \n"     \
        "3:                                                     \n"     \
        "       .section        .fixup,\"ax\"                   \n"     \
-        "4:     li      %0, %5                                  \n"     \
+        "4:     li      %0, %4                                  \n"     \
        "       j       3b                                      \n"     \
        "       .previous                                       \n"     \
        "       .section        __ex_table,\"a\"                \n"     \
@@ -378,9 +360,9 @@ extern void __get_user_unknown(void);
        "       " __UA_ADDR "   2b, 4b                          \n"     \
        "       .previous"                                              \
        : "=r" (__pu_err)                                               \
-        : "0" (__pu_err), "r" (__pu_val), "o" (__m(__pu_addr)),         \
+        : "0" (0), "r" (__pu_val), "r" (ptr),                           \
-          "o" (__m(__pu_addr + 4)), "i" (-EFAULT));                     \
+          "i" (-EFAULT));                                               \
-})
+}
 extern void __put_user_unknown(void);
@@ -403,7 +385,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 #define __invoke_copy_to_user(to,from,n)                                \
 ({                                                                      \
-        register void *__cu_to_r __asm__ ("$4");                        \
+        register void __user *__cu_to_r __asm__ ("$4");                 \
        register const void *__cu_from_r __asm__ ("$5");                \
        register long __cu_len_r __asm__ ("$6");                        \
                                                                        \
@@ -435,7 +417,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 */
 #define __copy_to_user(to,from,n)                                       \
 ({                                                                      \
-        void *__cu_to;                                                  \
+        void __user *__cu_to;                                           \
        const void *__cu_from;                                          \
        long __cu_len;                                                  \
                                                                        \
@@ -465,7 +447,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 */
 #define copy_to_user(to,from,n)                                         \
 ({                                                                      \
-        void *__cu_to;                                                  \
+        void __user *__cu_to;                                           \
        const void *__cu_from;                                          \
        long __cu_len;                                                  \
                                                                        \
@@ -482,7 +464,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 #define __invoke_copy_from_user(to,from,n)                              \
 ({                                                                      \
        register void *__cu_to_r __asm__ ("$4");                        \
-        register const void *__cu_from_r __asm__ ("$5");                \
+        register const void __user *__cu_from_r __asm__ ("$5");         \
        register long __cu_len_r __asm__ ("$6");                        \
                                                                        \
        __cu_to_r = (to);                                               \
@@ -521,7 +503,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 #define __copy_from_user(to,from,n)                                     \
 ({                                                                      \
        void *__cu_to;                                                  \
-        const void *__cu_from;                                          \
+        const void __user *__cu_from;                                   \
        long __cu_len;                                                  \
                                                                        \
        might_sleep();                                                  \
@@ -552,7 +534,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 #define copy_from_user(to,from,n)                                       \
 ({                                                                      \
        void *__cu_to;                                                  \
-        const void *__cu_from;                                          \
+        const void __user *__cu_from;                                   \
        long __cu_len;                                                  \
                                                                        \
        might_sleep();                                                  \
@@ -569,8 +551,8 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 #define copy_in_user(to,from,n)                                         \
 ({                                                                      \
-        void *__cu_to;                                                  \
+        void __user *__cu_to;                                           \
-        const void *__cu_from;                                          \
+        const void __user *__cu_from;                                   \
        long __cu_len;                                                  \
                                                                        \
        might_sleep();                                                  \
@@ -596,7 +578,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 * On success, this will be zero.
 */
 static inline __kernel_size_t
-__clear_user(void *addr, __kernel_size_t size)
+__clear_user(void __user *addr, __kernel_size_t size)
 {
        __kernel_size_t res;
@@ -616,7 +598,7 @@ __clear_user(void *addr, __kernel_size_t size)
 #define clear_user(addr,n)                                              \
 ({                                                                      \
-        void * __cl_addr = (addr);                                      \
+        void __user * __cl_addr = (addr);                               \
        unsigned long __cl_size = (n);                                  \
        if (__cl_size && access_ok(VERIFY_WRITE,                        \
                ((unsigned long)(__cl_addr)), __cl_size))               \
@@ -645,7 +627,7 @@ __clear_user(void *addr, __kernel_size_t size)
 * and returns @count.
 */
 static inline long
-__strncpy_from_user(char *__to, const char *__from, long __len)
+__strncpy_from_user(char *__to, const char __user *__from, long __len)
 {
        long res;
@@ -682,7 +664,7 @@ __strncpy_from_user(char *__to, const char *__from, long __len)
 * and returns @count.
 */
 static inline long
-strncpy_from_user(char *__to, const char *__from, long __len)
+strncpy_from_user(char *__to, const char __user *__from, long __len)
 {
        long res;
@@ -701,7 +683,7 @@ strncpy_from_user(char *__to, const char *__from, long __len)
 }
 /* Returns: 0 if bad, string length+1 (memory size) of string if ok */
-static inline long __strlen_user(const char *s)
+static inline long __strlen_user(const char __user *s)
 {
        long res;
@@ -731,7 +713,7 @@ static inline long __strlen_user(const char *s)
 * If there is a limit on the length of a valid string, you may wish to
 * consider using strnlen_user() instead.
 */
-static inline long strlen_user(const char *s)
+static inline long strlen_user(const char __user *s)
 {
        long res;
@@ -748,7 +730,7 @@ static inline long strlen_user(const char *s)
 }
 /* Returns: 0 if bad, string length+1 (memory size) of string if ok */
-static inline long __strnlen_user(const char *s, long n)
+static inline long __strnlen_user(const char __user *s, long n)
 {
        long res;
@@ -779,7 +761,7 @@ static inline long __strnlen_user(const char *s, long n)
 * If there is a limit on the length of a valid string, you may wish to
 * consider using strnlen_user() instead.
 */
-static inline long strnlen_user(const char *s, long n)
+static inline long strnlen_user(const char __user *s, long n)
 {
        long res;
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index ad4d48056307..89ea8b60e945 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -303,16 +303,21 @@
 #define __NR_add_key                    (__NR_Linux + 280)
 #define __NR_request_key                (__NR_Linux + 281)
 #define __NR_keyctl                     (__NR_Linux + 282)
+#define __NR_set_thread_area            (__NR_Linux + 283)
+#define __NR_inotify_init               (__NR_Linux + 284)
+#define __NR_inotify_add_watch          (__NR_Linux + 285)
+#define __NR_inotify_rm_watch           (__NR_Linux + 286)
 /*
 * Offset of the last Linux o32 flavoured syscall
 */
-#define __NR_Linux_syscalls             282
+#define __NR_Linux_syscalls             286
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         282
+#define __NR_O32_Linux_syscalls         283
 #if _MIPS_SIM == _MIPS_SIM_ABI64
@@ -562,16 +567,20 @@
 #define __NR_add_key                    (__NR_Linux + 239)
 #define __NR_request_key                (__NR_Linux + 240)
 #define __NR_keyctl                     (__NR_Linux + 241)
+#define __NR_set_thread_area            (__NR_Linux + 242)
+#define __NR_inotify_init               (__NR_Linux + 243)
+#define __NR_inotify_add_watch          (__NR_Linux + 244)
+#define __NR_inotify_rm_watch           (__NR_Linux + 245)
 /*
 * Offset of the last Linux 64-bit flavoured syscall
 */
-#define __NR_Linux_syscalls             241
+#define __NR_Linux_syscalls             245
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          241
+#define __NR_64_Linux_syscalls          242
 #if _MIPS_SIM == _MIPS_SIM_NABI32
@@ -825,16 +834,20 @@
 #define __NR_add_key                    (__NR_Linux + 243)
 #define __NR_request_key                (__NR_Linux + 244)
 #define __NR_keyctl                     (__NR_Linux + 245)
+#define __NR_set_thread_area            (__NR_Linux + 246)
+#define __NR_inotify_init               (__NR_Linux + 247)
+#define __NR_inotify_add_watch          (__NR_Linux + 248)
+#define __NR_inotify_rm_watch           (__NR_Linux + 249)
 /*
 * Offset of the last N32 flavoured syscall
 */
-#define __NR_Linux_syscalls             245
+#define __NR_Linux_syscalls             249
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         245
+#define __NR_N32_Linux_syscalls         246
 #ifndef __ASSEMBLY__
@@ -1164,7 +1177,6 @@ asmlinkage long sys_mmap2(
                        unsigned long fd, unsigned long pgoff);
 asmlinkage int sys_execve(nabi_no_regargs struct pt_regs regs);
 asmlinkage int sys_pipe(nabi_no_regargs struct pt_regs regs);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
index 6b35cf054c79..ca5cec97e167 100644
--- a/include/asm-mips/vga.h
+++ b/include/asm-mips/vga.h
@@ -6,6 +6,8 @@
 #ifndef _ASM_VGA_H
 #define _ASM_VGA_H
+#include <asm/byteorder.h>
 /*
 *      On the PC, we can just recalculate addresses and then
 *      access the videoram directly without any black magic.
@@ -16,4 +18,27 @@
 #define vga_readb(x)    (*(x))
 #define vga_writeb(x,y) (*(y) = (x))
+#define VT_BUF_HAVE_RW
+/*
+ *  These are only needed for supporting VGA or MDA text mode, which use little
+ *  endian byte ordering.
+ *  In other cases, we can optimize by using native byte ordering and
+ *  <linux/vt_buffer.h> has already done the right job for us.
+ */
+static inline void scr_writew(u16 val, volatile u16 *addr)
+{
+        *addr = cpu_to_le16(val);
+}
+static inline u16 scr_readw(volatile const u16 *addr)
+{
+        return le16_to_cpu(*addr);
+}
+#define scr_memcpyw(d, s, c) memcpy(d, s, c)
+#define scr_memmovew(d, s, c) memmove(d, s, c)
+#define VT_BUF_HAVE_MEMCPYW
+#define VT_BUF_HAVE_MEMMOVEW
 #endif /* _ASM_VGA_H */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index 04ee53b34c2e..ad374bd3f130 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -177,6 +177,17 @@
 #endif
 /*
+ * The RM9000 has a bug (though PMC-Sierra opposes it being called that)
+ * where invalid instructions in the same I-cache line worth of instructions
+ * being fetched may case spurious exceptions.
+ */
+#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
+    defined(CONFIG_PMC_YOSEMITE)
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#endif
+/*
 * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
 * may cause ll / sc and lld / scd sequences to execute non-atomically.
 */
@@ -187,6 +198,9 @@
 /*
 * Workarounds default to off
 */
+#ifndef ICACHE_REFILLS_WORKAROUND_WAR
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#endif
 #ifndef R4600_V1_INDEX_ICACHEOP_WAR
 #define R4600_V1_INDEX_ICACHEOP_WAR     0
 #endif
diff --git a/include/asm-parisc/cacheflush.h b/include/asm-parisc/cacheflush.h
index aa592d8c0e39..1bc3c83ee74b 100644
--- a/include/asm-parisc/cacheflush.h
+++ b/include/asm-parisc/cacheflush.h
@@ -100,30 +100,34 @@ static inline void flush_cache_range(struct vm_area_struct *vma,
 /* Simple function to work out if we have an existing address translation
 * for a user space vma. */
-static inline pte_t *__translation_exists(struct mm_struct *mm,
+static inline int translation_exists(struct vm_area_struct *vma,
-                                          unsigned long addr)
+                                unsigned long addr, unsigned long pfn)
 {
-        pgd_t *pgd = pgd_offset(mm, addr);
+        pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
        pmd_t *pmd;
-        pte_t *pte;
+        pte_t pte;
        if(pgd_none(*pgd))
-                return NULL;
+                return 0;
        pmd = pmd_offset(pgd, addr);
        if(pmd_none(*pmd) || pmd_bad(*pmd))
-                return NULL;
+                return 0;
-        pte = pte_offset_map(pmd, addr);
+        /* We cannot take the pte lock here: flush_cache_page is usually
+         * called with pte lock already held.  Whereas flush_dcache_page
+         * takes flush_dcache_mmap_lock, which is lower in the hierarchy:
+         * the vma itself is secure, but the pte might come or go racily.
+         */
+        pte = *pte_offset_map(pmd, addr);
+        /* But pte_unmap() does nothing on this architecture */
-        /* The PA flush mappings show up as pte_none, but they're
+        /* Filter out coincidental file entries and swap entries */
-         * valid none the less */
+        if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
-        if(pte_none(*pte) && ((pte_val(*pte) & _PAGE_FLUSH) == 0))
+                return 0;
-                return NULL;
-        return pte;
-}
-#define translation_exists(vma, addr)   __translation_exists((vma)->vm_mm, addr)
+        return pte_pfn(pte) == pfn;
+}
 /* Private function to flush a page from the cache of a non-current
 * process.  cr25 contains the Page Directory of the current user
@@ -175,9 +179,8 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
 {
        BUG_ON(!vma->vm_mm->context);
-        if(likely(translation_exists(vma, vmaddr)))
+        if (likely(translation_exists(vma, vmaddr, pfn)))
                __flush_cache_page(vma, vmaddr);
 }
 #endif
diff --git a/include/asm-parisc/ide.h b/include/asm-parisc/ide.h
index 3243cf2cd227..b27bf7aeb256 100644
--- a/include/asm-parisc/ide.h
+++ b/include/asm-parisc/ide.h
@@ -22,7 +22,6 @@
 #define ide_request_irq(irq,hand,flg,dev,id)    request_irq((irq),(hand),(flg),(dev),(id))
 #define ide_free_irq(irq,dev_id)                free_irq((irq), (dev_id))
-#define ide_check_region(from,extent)           check_region((from), (extent))
 #define ide_request_region(from,extent,name)    request_region((from), (extent), (name))
 #define ide_release_region(from,extent)         release_region((from), (extent))
 /* Generic I/O and MEMIO string operations.  */
diff --git a/include/asm-parisc/mmzone.h b/include/asm-parisc/mmzone.h
index 595d3dce120a..ae039f4fd711 100644
--- a/include/asm-parisc/mmzone.h
+++ b/include/asm-parisc/mmzone.h
@@ -27,12 +27,6 @@ extern struct node_map_data node_data[];
 })
 #define node_localnr(pfn, nid)          ((pfn) - node_start_pfn(nid))
-#define local_mapnr(kvaddr)                                             \
-({                                                                      \
-        unsigned long __pfn = __pa(kvaddr) >> PAGE_SHIFT;               \
-        (__pfn - node_start_pfn(pfn_to_nid(__pfn)));                    \
-})
 #define pfn_to_page(pfn)                                                \
 ({                                                                      \
        unsigned long __pfn = (pfn);                                    \
diff --git a/include/asm-parisc/semaphore.h b/include/asm-parisc/semaphore.h
index f78bb2e34538..c9ee41cd0707 100644
--- a/include/asm-parisc/semaphore.h
+++ b/include/asm-parisc/semaphore.h
@@ -49,9 +49,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-parisc/tlbflush.h b/include/asm-parisc/tlbflush.h
index 84af4ab1fe51..e97aa8d1eff5 100644
--- a/include/asm-parisc/tlbflush.h
+++ b/include/asm-parisc/tlbflush.h
@@ -88,7 +88,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
        if (npages >= 512)  /* 2MB of space: arbitrary, should be tuned */
                flush_tlb_all();
        else {
+                preempt_disable();
                mtsp(vma->vm_mm->context,1);
                purge_tlb_start();
                if (split_tlb) {
@@ -102,6 +102,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
                                pdtlb(start);
                                start += PAGE_SIZE;
                        }
+                preempt_enable();
                }
                purge_tlb_end();
        }
diff --git a/include/asm-parisc/unistd.h b/include/asm-parisc/unistd.h
index e7a620c5c5e6..80b7b98c70a1 100644
--- a/include/asm-parisc/unistd.h
+++ b/include/asm-parisc/unistd.h
@@ -1011,7 +1011,6 @@ int sys_clone(unsigned long clone_flags, unsigned long usp,
                struct pt_regs *regs);
 int sys_vfork(struct pt_regs *regs);
 int sys_pipe(int *fildes);
-long sys_ptrace(long request, pid_t pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-ppc64/a.out.h b/include/asm-powerpc/a.out.h
index 3871e252a6f1..c7393a977364 100644
--- a/include/asm-ppc64/a.out.h
+++ b/include/asm-powerpc/a.out.h
@@ -1,14 +1,5 @@
-#ifndef __PPC64_A_OUT_H__
+#ifndef _ASM_POWERPC_A_OUT_H
-#define __PPC64_A_OUT_H__
+#define _ASM_POWERPC_A_OUT_H
-/*
- * c 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
 struct exec
 {
@@ -27,6 +18,7 @@ struct exec
 #define N_SYMSIZE(a)    ((a).a_syms)
 #ifdef __KERNEL__
+#ifdef __powerpc64__
 #define STACK_TOP_USER64 TASK_SIZE_USER64
 #define STACK_TOP_USER32 TASK_SIZE_USER32
@@ -34,6 +26,11 @@ struct exec
 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
                   STACK_TOP_USER32 : STACK_TOP_USER64)
+#else /* __powerpc64__ */
+#define STACK_TOP TASK_SIZE
+#endif /* __powerpc64__ */
 #endif /* __KERNEL__ */
-#endif /* __PPC64_A_OUT_H__ */
+#endif /* _ASM_POWERPC_A_OUT_H */
diff --git a/include/asm-ppc/atomic.h b/include/asm-powerpc/atomic.h
index eeafd505836e..ed4b345ed75d 100644
--- a/include/asm-ppc/atomic.h
+++ b/include/asm-powerpc/atomic.h
@@ -1,29 +1,20 @@
+#ifndef _ASM_POWERPC_ATOMIC_H_
+#define _ASM_POWERPC_ATOMIC_H_
 /*
 * PowerPC atomic operations
 */
-#ifndef _ASM_PPC_ATOMIC_H_
-#define _ASM_PPC_ATOMIC_H_
 typedef struct { volatile int counter; } atomic_t;
 #ifdef __KERNEL__
+#include <asm/synch.h>
-#define ATOMIC_INIT(i)  { (i) }
+#define ATOMIC_INIT(i)          { (i) }
 #define atomic_read(v)          ((v)->counter)
 #define atomic_set(v,i)         (((v)->counter) = (i))
-extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
-#ifdef CONFIG_SMP
-#define SMP_SYNC        "sync"
-#define SMP_ISYNC       "\n\tisync"
-#else
-#define SMP_SYNC        ""
-#define SMP_ISYNC
-#endif
 /* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
 * The old ATOMIC_SYNC_FIX covered some but not all of this.
 */
@@ -53,12 +44,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
        int t;
        __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%2         # atomic_add_return\n\
        add     %0,%1,%0\n"
        PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
        bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
        : "=&r" (t)
        : "r" (a), "r" (&v->counter)
        : "cc", "memory");
@@ -88,12 +80,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
        int t;
        __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%2         # atomic_sub_return\n\
        subf    %0,%1,%0\n"
        PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
        bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
        : "=&r" (t)
        : "r" (a), "r" (&v->counter)
        : "cc", "memory");
@@ -121,12 +114,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
        int t;
        __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_inc_return\n\
        addic   %0,%0,1\n"
        PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1 \n\
        bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
        : "=&r" (t)
        : "r" (&v->counter)
        : "cc", "memory");
@@ -164,12 +158,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
        int t;
        __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_dec_return\n\
        addic   %0,%0,-1\n"
        PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
        bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
        : "=&r" (t)
        : "r" (&v->counter)
        : "cc", "memory");
@@ -189,13 +184,14 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
        int t;
        __asm__ __volatile__(
+        EIEIO_ON_SMP
 "1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
        addic.  %0,%0,-1\n\
        blt-    2f\n"
        PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
        bne-    1b"
-        SMP_ISYNC
+        ISYNC_ON_SMP
        "\n\
 2:"     : "=&r" (t)
        : "r" (&v->counter)
@@ -204,11 +200,10 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
        return t;
 }
-#define __MB    __asm__ __volatile__ (SMP_SYNC : : : "memory")
+#define smp_mb__before_atomic_dec()     smp_mb()
-#define smp_mb__before_atomic_dec()     __MB
+#define smp_mb__after_atomic_dec()      smp_mb()
-#define smp_mb__after_atomic_dec()      __MB
+#define smp_mb__before_atomic_inc()     smp_mb()
-#define smp_mb__before_atomic_inc()     __MB
+#define smp_mb__after_atomic_inc()      smp_mb()
-#define smp_mb__after_atomic_inc()      __MB
 #endif /* __KERNEL__ */
-#endif /* _ASM_PPC_ATOMIC_H_ */
+#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/include/asm-ppc64/auxvec.h b/include/asm-powerpc/auxvec.h
index ac6381a106e1..79d8c4732309 100644
--- a/include/asm-ppc64/auxvec.h
+++ b/include/asm-powerpc/auxvec.h
@@ -1,5 +1,5 @@
-#ifndef __PPC64_AUXVEC_H
+#ifndef _ASM_POWERPC_AUXVEC_H
-#define __PPC64_AUXVEC_H
+#define _ASM_POWERPC_AUXVEC_H
 /*
 * We need to put in some extra aux table entries to tell glibc what
@@ -14,6 +14,8 @@
 /* The vDSO location. We have to use the same value as x86 for glibc's
 * sake :-)
 */
+#ifdef __powerpc64__
 #define AT_SYSINFO_EHDR         33
+#endif
-#endif /* __PPC64_AUXVEC_H */
+#endif
diff --git a/include/asm-ppc/backlight.h b/include/asm-powerpc/backlight.h
index 3a1c3dede2a0..1ba1f27a0b63 100644
--- a/include/asm-ppc/backlight.h
+++ b/include/asm-powerpc/backlight.h
@@ -1,12 +1,13 @@
 /*
 * Routines for handling backlight control on PowerBooks
 *
- * For now, implementation resides in arch/ppc/kernel/pmac_support.c
+ * For now, implementation resides in
+ * arch/powerpc/platforms/powermac/pmac_support.c
 *
 */
+#ifndef __ASM_POWERPC_BACKLIGHT_H
+#define __ASM_POWERPC_BACKLIGHT_H
 #ifdef __KERNEL__
-#ifndef __ASM_PPC_BACKLIGHT_H
-#define __ASM_PPC_BACKLIGHT_H
 /* Abstract values */
 #define BACKLIGHT_OFF   0
@@ -26,5 +27,5 @@ extern int get_backlight_enable(void);
 extern int set_backlight_level(int level);
 extern int get_backlight_level(void);
-#endif
 #endif /* __KERNEL__ */
+#endif
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
new file mode 100644
index 000000000000..dc25c53704d5
--- /dev/null
+++ b/include/asm-powerpc/bitops.h
@@ -0,0 +1,437 @@
+/*
+ * PowerPC atomic bit operations.
+ *
+ * Merged version by David Gibson <david@gibson.dropbear.id.au>.
+ * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
+ * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard.  They
+ * originally took it from the ppc32 code.
+ *
+ * Within a word, bits are numbered LSB first.  Lot's of places make
+ * this assumption by directly testing bits with (val & (1<<nr)).
+ * This can cause confusion for large (> 1 word) bitmaps on a
+ * big-endian system because, unlike little endian, the number of each
+ * bit depends on the word size.
+ *
+ * The bitop functions are defined to work on unsigned longs, so for a
+ * ppc64 system the bits end up numbered:
+ *   |63..............0|127............64|191...........128|255...........196|
+ * and on ppc32:
+ *   |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
+ *
+ * There are a few little-endian macros used mostly for filesystem
+ * bitmaps, these work on similar bit arrays layouts, but
+ * byte-oriented:
+ *   |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
+ *
+ * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
+ * number field needs to be reversed compared to the big-endian bit
+ * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_BITOPS_H
+#define _ASM_POWERPC_BITOPS_H
+#ifdef __KERNEL__
+#include <linux/compiler.h>
+#include <asm/atomic.h>
+#include <asm/synch.h>
+/*
+ * clear_bit doesn't imply a memory barrier
+ */
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       smp_mb()
+#define BITOP_MASK(nr)          (1UL << ((nr) % BITS_PER_LONG))
+#define BITOP_WORD(nr)          ((nr) / BITS_PER_LONG)
+#define BITOP_LE_SWIZZLE        ((BITS_PER_LONG-1) & ~0x7)
+#ifdef CONFIG_PPC64
+#define LARXL           "ldarx"
+#define STCXL           "stdcx."
+#define CNTLZL          "cntlzd"
+#else
+#define LARXL           "lwarx"
+#define STCXL           "stwcx."
+#define CNTLZL          "cntlzw"
+#endif
+static __inline__ void set_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        __asm__ __volatile__(
+"1:"    LARXL " %0,0,%3 # set_bit\n"
+        "or     %0,%0,%2\n"
+        PPC405_ERR77(0,%3)
+        STCXL " %0,0,%3\n"
+        "bne-   1b"
+        : "=&r"(old), "=m"(*p)
+        : "r"(mask), "r"(p), "m"(*p)
+        : "cc" );
+}
+static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        __asm__ __volatile__(
+"1:"    LARXL " %0,0,%3 # set_bit\n"
+        "andc   %0,%0,%2\n"
+        PPC405_ERR77(0,%3)
+        STCXL " %0,0,%3\n"
+        "bne-   1b"
+        : "=&r"(old), "=m"(*p)
+        : "r"(mask), "r"(p), "m"(*p)
+        : "cc" );
+}
+static __inline__ void change_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        __asm__ __volatile__(
+"1:"    LARXL " %0,0,%3 # set_bit\n"
+        "xor    %0,%0,%2\n"
+        PPC405_ERR77(0,%3)
+        STCXL " %0,0,%3\n"
+        "bne-   1b"
+        : "=&r"(old), "=m"(*p)
+        : "r"(mask), "r"(p), "m"(*p)
+        : "cc" );
+}
+static __inline__ int test_and_set_bit(unsigned long nr,
+                                       volatile unsigned long *addr)
+{
+        unsigned long old, t;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        __asm__ __volatile__(
+        EIEIO_ON_SMP
+"1:"    LARXL " %0,0,%3         # test_and_set_bit\n"
+        "or     %1,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+        STCXL " %1,0,%3 \n"
+        "bne-   1b"
+        ISYNC_ON_SMP
+        : "=&r" (old), "=&r" (t)
+        : "r" (mask), "r" (p)
+        : "cc", "memory");
+        return (old & mask) != 0;
+}
+static __inline__ int test_and_clear_bit(unsigned long nr,
+                                         volatile unsigned long *addr)
+{
+        unsigned long old, t;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        __asm__ __volatile__(
+        EIEIO_ON_SMP
+"1:"    LARXL " %0,0,%3         # test_and_clear_bit\n"
+        "andc   %1,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+        STCXL " %1,0,%3 \n"
+        "bne-   1b"
+        ISYNC_ON_SMP
+        : "=&r" (old), "=&r" (t)
+        : "r" (mask), "r" (p)
+        : "cc", "memory");
+        return (old & mask) != 0;
+}
+static __inline__ int test_and_change_bit(unsigned long nr,
+                                          volatile unsigned long *addr)
+{
+        unsigned long old, t;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        __asm__ __volatile__(
+        EIEIO_ON_SMP
+"1:"    LARXL " %0,0,%3         # test_and_change_bit\n"
+        "xor    %1,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+        STCXL " %1,0,%3 \n"
+        "bne-   1b"
+        ISYNC_ON_SMP
+        : "=&r" (old), "=&r" (t)
+        : "r" (mask), "r" (p)
+        : "cc", "memory");
+        return (old & mask) != 0;
+}
+static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
+{
+        unsigned long old;
+        __asm__ __volatile__(
+"1:"    LARXL " %0,0,%3         # set_bit\n"
+        "or     %0,%0,%2\n"
+        STCXL " %0,0,%3\n"
+        "bne-   1b"
+        : "=&r" (old), "=m" (*addr)
+        : "r" (mask), "r" (addr), "m" (*addr)
+        : "cc");
+}
+/* Non-atomic versions */
+static __inline__ int test_bit(unsigned long nr,
+                               __const__ volatile unsigned long *addr)
+{
+        return 1UL & (addr[BITOP_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+}
+static __inline__ void __set_bit(unsigned long nr,
+                                 volatile unsigned long *addr)
+{
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        *p  |= mask;
+}
+static __inline__ void __clear_bit(unsigned long nr,
+                                   volatile unsigned long *addr)
+{
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        *p &= ~mask;
+}
+static __inline__ void __change_bit(unsigned long nr,
+                                    volatile unsigned long *addr)
+{
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        *p ^= mask;
+}
+static __inline__ int __test_and_set_bit(unsigned long nr,
+                                         volatile unsigned long *addr)
+{
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        unsigned long old = *p;
+        *p = old | mask;
+        return (old & mask) != 0;
+}
+static __inline__ int __test_and_clear_bit(unsigned long nr,
+                                           volatile unsigned long *addr)
+{
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        unsigned long old = *p;
+        *p = old & ~mask;
+        return (old & mask) != 0;
+}
+static __inline__ int __test_and_change_bit(unsigned long nr,
+                                            volatile unsigned long *addr)
+{
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+        unsigned long old = *p;
+        *p = old ^ mask;
+        return (old & mask) != 0;
+}
+/*
+ * Return the zero-based bit position (LE, not IBM bit numbering) of
+ * the most significant 1-bit in a double word.
+ */
+static __inline__ int __ilog2(unsigned long x)
+{
+        int lz;
+        asm (CNTLZL " %0,%1" : "=r" (lz) : "r" (x));
+        return BITS_PER_LONG - 1 - lz;
+}
+/*
+ * Determines the bit position of the least significant 0 bit in the
+ * specified double word. The returned bit position will be
+ * zero-based, starting from the right side (63/31 - 0).
+ */
+static __inline__ unsigned long ffz(unsigned long x)
+{
+        /* no zero exists anywhere in the 8 byte area. */
+        if ((x = ~x) == 0)
+                return BITS_PER_LONG;
+        /*
+         * Calculate the bit position of the least signficant '1' bit in x
+         * (since x has been changed this will actually be the least signficant
+         * '0' bit in * the original x).  Note: (x & -x) gives us a mask that
+         * is the least significant * (RIGHT-most) 1-bit of the value in x.
+         */
+        return __ilog2(x & -x);
+}
+static __inline__ int __ffs(unsigned long x)
+{
+        return __ilog2(x & -x);
+}
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int ffs(int x)
+{
+        unsigned long i = (unsigned long)x;
+        return __ilog2(i & -i) + 1;
+}
+/*
+ * fls: find last (most-significant) bit set.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static __inline__ int fls(unsigned int x)
+{
+        int lz;
+        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+        return 32 - lz;
+}
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+#define hweight64(x) generic_hweight64(x)
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
+unsigned long find_next_zero_bit(const unsigned long *addr,
+                                 unsigned long size, unsigned long offset);
+/**
+ * find_first_bit - find the first set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first set bit, not the number of the byte
+ * containing a bit.
+ */
+#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
+unsigned long find_next_bit(const unsigned long *addr,
+                            unsigned long size, unsigned long offset);
+/* Little-endian versions */
+static __inline__ int test_le_bit(unsigned long nr,
+                                  __const__ unsigned long *addr)
+{
+        __const__ unsigned char *tmp = (__const__ unsigned char *) addr;
+        return (tmp[nr >> 3] >> (nr & 7)) & 1;
+}
+#define __set_le_bit(nr, addr) \
+        __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define __clear_le_bit(nr, addr) \
+        __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define test_and_set_le_bit(nr, addr) \
+        test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define test_and_clear_le_bit(nr, addr) \
+        test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define __test_and_set_le_bit(nr, addr) \
+        __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define __test_and_clear_le_bit(nr, addr) \
+        __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define find_first_zero_le_bit(addr, size) find_next_zero_le_bit((addr), (size), 0)
+unsigned long find_next_zero_le_bit(const unsigned long *addr,
+                                    unsigned long size, unsigned long offset);
+/* Bitmap functions for the ext2 filesystem */
+#define ext2_set_bit(nr,addr) \
+        __test_and_set_le_bit((nr), (unsigned long*)addr)
+#define ext2_clear_bit(nr, addr) \
+        __test_and_clear_le_bit((nr), (unsigned long*)addr)
+#define ext2_set_bit_atomic(lock, nr, addr) \
+        test_and_set_le_bit((nr), (unsigned long*)addr)
+#define ext2_clear_bit_atomic(lock, nr, addr) \
+        test_and_clear_le_bit((nr), (unsigned long*)addr)
+#define ext2_test_bit(nr, addr)      test_le_bit((nr),(unsigned long*)addr)
+#define ext2_find_first_zero_bit(addr, size) \
+        find_first_zero_le_bit((unsigned long*)addr, size)
+#define ext2_find_next_zero_bit(addr, size, off) \
+        find_next_zero_le_bit((unsigned long*)addr, size, off)
+/* Bitmap functions for the minix filesystem.  */
+#define minix_test_and_set_bit(nr,addr) \
+        __test_and_set_le_bit(nr, (unsigned long *)addr)
+#define minix_set_bit(nr,addr) \
+        __set_le_bit(nr, (unsigned long *)addr)
+#define minix_test_and_clear_bit(nr,addr) \
+        __test_and_clear_le_bit(nr, (unsigned long *)addr)
+#define minix_test_bit(nr,addr) \
+        test_le_bit(nr, (unsigned long *)addr)
+#define minix_find_first_zero_bit(addr,size) \
+        find_first_zero_le_bit((unsigned long *)addr, size)
+/*
+ * Every architecture must define this function. It's the fastest
+ * way of searching a 140-bit bitmap where the first 100 bits are
+ * unlikely to be set. It's guaranteed that at least one of the 140
+ * bits is cleared.
+ */
+static inline int sched_find_first_bit(const unsigned long *b)
+{
+#ifdef CONFIG_PPC64
+        if (unlikely(b[0]))
+                return __ffs(b[0]);
+        if (unlikely(b[1]))
+                return __ffs(b[1]) + 64;
+        return __ffs(b[2]) + 128;
+#else
+        if (unlikely(b[0]))
+                return __ffs(b[0]);
+        if (unlikely(b[1]))
+                return __ffs(b[1]) + 32;
+        if (unlikely(b[2]))
+                return __ffs(b[2]) + 64;
+        if (b[3])
+                return __ffs(b[3]) + 96;
+        return __ffs(b[4]) + 128;
+#endif
+}
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_BITOPS_H */
diff --git a/include/asm-ppc64/bug.h b/include/asm-powerpc/bug.h
index 160178278861..d625ee55f957 100644
--- a/include/asm-ppc64/bug.h
+++ b/include/asm-powerpc/bug.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_BUG_H
+#ifndef _ASM_POWERPC_BUG_H
-#define _PPC64_BUG_H
+#define _ASM_POWERPC_BUG_H
 /*
 * Define an illegal instr to trap on the bug.
@@ -11,6 +11,14 @@
 #ifndef __ASSEMBLY__
+#ifdef __powerpc64__
+#define BUG_TABLE_ENTRY         ".llong"
+#define BUG_TRAP_OP             "tdnei"
+#else 
+#define BUG_TABLE_ENTRY         ".long"
+#define BUG_TRAP_OP             "twnei"
+#endif /* __powerpc64__ */
 struct bug_entry {
        unsigned long   bug_addr;
        long            line;
@@ -31,29 +39,29 @@ struct bug_entry *find_bug(unsigned long bugaddr);
 #define BUG() do {                                                       \
        __asm__ __volatile__(                                            \
                "1:     twi 31,0,0\n"                                    \
-                ".section __bug_table,\"a\"\n\t"                         \
+                ".section __bug_table,\"a\"\n"                           \
-                "       .llong 1b,%0,%1,%2\n"                            \
+                "\t"BUG_TABLE_ENTRY"    1b,%0,%1,%2\n"                   \
                ".previous"                                              \
                : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
 } while (0)
 #define BUG_ON(x) do {                                          \
        __asm__ __volatile__(                                   \
-                "1:     tdnei %0,0\n"                           \
+                "1:     "BUG_TRAP_OP"   %0,0\n"                 \
-                ".section __bug_table,\"a\"\n\t"                \
+                ".section __bug_table,\"a\"\n"                  \
-                "       .llong 1b,%1,%2,%3\n"                   \
+                "\t"BUG_TABLE_ENTRY"    1b,%1,%2,%3\n"          \
                ".previous"                                     \
-                : : "r" ((long long)(x)), "i" (__LINE__),       \
+                : : "r" ((long)(x)), "i" (__LINE__),            \
                    "i" (__FILE__), "i" (__FUNCTION__));        \
 } while (0)
 #define WARN_ON(x) do {                                         \
        __asm__ __volatile__(                                   \
-                "1:     tdnei %0,0\n"                           \
+                "1:     "BUG_TRAP_OP"   %0,0\n"                 \
-                ".section __bug_table,\"a\"\n\t"                \
+                ".section __bug_table,\"a\"\n"                  \
-                "       .llong 1b,%1,%2,%3\n"                   \
+                "\t"BUG_TABLE_ENTRY"    1b,%1,%2,%3\n"          \
                ".previous"                                     \
-                : : "r" ((long long)(x)),                       \
+                : : "r" ((long)(x)),                            \
                    "i" (__LINE__ + BUG_WARNING_TRAP),          \
                    "i" (__FILE__), "i" (__FUNCTION__));        \
 } while (0)
@@ -61,9 +69,9 @@ struct bug_entry *find_bug(unsigned long bugaddr);
 #define HAVE_ARCH_BUG
 #define HAVE_ARCH_BUG_ON
 #define HAVE_ARCH_WARN_ON
-#endif
+#endif /* CONFIG_BUG */
-#endif
+#endif /* __ASSEMBLY __ */
 #include <asm-generic/bug.h>
-#endif
+#endif /* _ASM_POWERPC_BUG_H */
diff --git a/include/asm-ppc64/byteorder.h b/include/asm-powerpc/byteorder.h
index 8b57da62b674..b37752214a16 100644
--- a/include/asm-ppc64/byteorder.h
+++ b/include/asm-powerpc/byteorder.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_BYTEORDER_H
+#ifndef _ASM_POWERPC_BYTEORDER_H
-#define _PPC64_BYTEORDER_H
+#define _ASM_POWERPC_BYTEORDER_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -77,10 +77,13 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
 #ifndef __STRICT_ANSI__
 #define __BYTEORDER_HAS_U64__
-#endif
+#ifndef __powerpc64__
+#define __SWAB_64_THRU_32__
+#endif /* __powerpc64__ */
+#endif /* __STRICT_ANSI__ */
 #endif /* __GNUC__ */
 #include <linux/byteorder/big_endian.h>
-#endif /* _PPC64_BYTEORDER_H */
+#endif /* _ASM_POWERPC_BYTEORDER_H */
diff --git a/include/asm-ppc64/checksum.h b/include/asm-powerpc/checksum.h
index d22d4469de43..d8354d8a49ce 100644
--- a/include/asm-ppc64/checksum.h
+++ b/include/asm-powerpc/checksum.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_CHECKSUM_H
+#ifndef _ASM_POWERPC_CHECKSUM_H
-#define _PPC64_CHECKSUM_H
+#define _ASM_POWERPC_CHECKSUM_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -41,8 +41,14 @@ extern unsigned int csum_partial(const unsigned char * buff, int len,
                                 unsigned int sum);
 /*
- * the same as csum_partial, but copies from src to dst while it
+ * Computes the checksum of a memory block at src, length len,
- * checksums
+ * and adds in "sum" (32-bit), while copying the block to dst.
+ * If an access exception occurs on src or dst, it stores -EFAULT
+ * to *src_err or *dst_err respectively (if that pointer is not
+ * NULL), and, for an error on src, zeroes the rest of dst.
+ *
+ * Like csum_partial, this must be called with even lengths,
+ * except for the last fragment.
 */
 extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
                                              int len, unsigned int sum,
@@ -51,12 +57,18 @@ extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
 * the same as csum_partial, but copies from src to dst while it
 * checksums.
 */
 unsigned int csum_partial_copy_nocheck(const char *src, 
                                       char *dst, 
                                       int len, 
                                       unsigned int sum);
+#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
+        csum_partial_copy_generic((src), (dst), (len), (sum), (errp), NULL)
+#define csum_partial_copy_nocheck(src, dst, len, sum)   \
+        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
 /*
 * turns a 32-bit partial checksum (e.g. from csum_partial) into a
 * 1's complement 16-bit checksum.
@@ -83,12 +95,7 @@ static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
        return csum_fold(csum_partial(buff, len, 0));
 }
-#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
+#ifdef __powerpc64__
-        csum_partial_copy_generic((src), (dst), (len), (sum), (errp), NULL)
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
 static inline u32 csum_tcpudp_nofold(u32 saddr,
                                     u32 daddr,
                                     unsigned short len,
@@ -103,5 +110,23 @@ static inline u32 csum_tcpudp_nofold(u32 saddr,
        s += (s >> 32);
        return (u32) s;
 }
+#else
+static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
+                                                   unsigned long daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   unsigned int sum)
+{
+    __asm__("\n\
+        addc %0,%0,%1 \n\
+        adde %0,%0,%2 \n\
+        adde %0,%0,%3 \n\
+        addze %0,%0 \n\
+        "
+        : "=r" (sum)
+        : "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum));
+    return sum;
+}
 #endif
+#endif
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
new file mode 100644
index 000000000000..c019501daceb
--- /dev/null
+++ b/include/asm-powerpc/cputable.h
@@ -0,0 +1,427 @@
+#ifndef __ASM_POWERPC_CPUTABLE_H
+#define __ASM_POWERPC_CPUTABLE_H
+#include <linux/config.h>
+#include <asm/ppc_asm.h> /* for ASM_CONST */
+#define PPC_FEATURE_32                  0x80000000
+#define PPC_FEATURE_64                  0x40000000
+#define PPC_FEATURE_601_INSTR           0x20000000
+#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
+#define PPC_FEATURE_HAS_FPU             0x08000000
+#define PPC_FEATURE_HAS_MMU             0x04000000
+#define PPC_FEATURE_HAS_4xxMAC          0x02000000
+#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
+#define PPC_FEATURE_HAS_SPE             0x00800000
+#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
+#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
+#define PPC_FEATURE_NO_TB               0x00100000
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+/* This structure can grow, it's real size is used by head.S code
+ * via the mkdefs mechanism.
+ */
+struct cpu_spec;
+struct op_powerpc_model;
+typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
+struct cpu_spec {
+        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
+        unsigned int    pvr_mask;
+        unsigned int    pvr_value;
+        char            *cpu_name;
+        unsigned long   cpu_features;           /* Kernel features */
+        unsigned int    cpu_user_features;      /* Userland features */
+        /* cache line sizes */
+        unsigned int    icache_bsize;
+        unsigned int    dcache_bsize;
+        /* number of performance monitor counters */
+        unsigned int    num_pmcs;
+        /* this is called to initialize various CPU bits like L1 cache,
+         * BHT, SPD, etc... from head.S before branching to identify_machine
+         */
+        cpu_setup_t     cpu_setup;
+        /* Used by oprofile userspace to select the right counters */
+        char            *oprofile_cpu_type;
+        /* Processor specific oprofile operations */
+        struct op_powerpc_model *oprofile_model;
+};
+extern struct cpu_spec          *cur_cpu_spec;
+extern void identify_cpu(unsigned long offset, unsigned long cpu);
+extern void do_cpu_ftr_fixups(unsigned long offset);
+#endif /* __ASSEMBLY__ */
+/* CPU kernel features */
+/* Retain the 32b definitions all use bottom half of word */
+#define CPU_FTR_SPLIT_ID_CACHE          ASM_CONST(0x0000000000000001)
+#define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
+#define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
+#define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
+#define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
+#define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
+#define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
+#define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
+#define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
+#define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
+#define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
+#define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
+#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
+#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
+#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
+#define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
+#define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
+#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
+#define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
+#define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
+#ifdef __powerpc64__
+/* Add the 64b processor unique features in the top half of the word */
+#define CPU_FTR_SLB                     ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE                ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL                  ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000800000000)
+#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000001000000000)
+#define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
+#define CPU_FTR_CTRL                    ASM_CONST(0x0000008000000000)
+#define CPU_FTR_SMT                     ASM_CONST(0x0000010000000000)
+#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000020000000000)
+#define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0000040000000000)
+#define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
+#else
+/* ensure on 32b processors the flags are available for compiling but
+ * don't do anything */
+#define CPU_FTR_SLB                     ASM_CONST(0x0)
+#define CPU_FTR_16M_PAGE                ASM_CONST(0x0)
+#define CPU_FTR_TLBIEL                  ASM_CONST(0x0)
+#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0)
+#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0)
+#define CPU_FTR_IABR                    ASM_CONST(0x0)
+#define CPU_FTR_MMCRA                   ASM_CONST(0x0)
+#define CPU_FTR_CTRL                    ASM_CONST(0x0)
+#define CPU_FTR_SMT                     ASM_CONST(0x0)
+#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0)
+#define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0)
+#define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0)
+#endif
+#ifndef __ASSEMBLY__
+#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
+                                        CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
+                                        CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
+/* iSeries doesn't support large pages */
+#ifdef CONFIG_PPC_ISERIES
+#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
+#else
+#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
+#endif /* CONFIG_PPC_ISERIES */
+/* We only set the altivec features if the kernel was compiled with altivec
+ * support
+ */
+#ifdef CONFIG_ALTIVEC
+#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
+#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
+#else
+#define CPU_FTR_ALTIVEC_COMP    0
+#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
+#endif
+/* We need to mark all pages as being coherent if we're SMP or we
+ * have a 74[45]x and an MPC107 host bridge.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
+#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
+#else
+#define CPU_FTR_COMMON                  0
+#endif
+/* The powersave features NAP & DOZE seems to confuse BDI when
+   debugging. So if a BDI is used, disable theses
+ */
+#ifndef CONFIG_BDI_SWITCH
+#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
+#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
+#else
+#define CPU_FTR_MAYBE_CAN_DOZE  0
+#define CPU_FTR_MAYBE_CAN_NAP   0
+#endif
+#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
+                     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
+                     !defined(CONFIG_BOOKE))
+enum {
+        CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
+        CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+            CPU_FTR_NO_DPM,
+        CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+            CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+            CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+            CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+        CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB |
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_NEED_COHERENT,
+        CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
+        CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+        CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+        CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
+            CPU_FTR_MAYBE_CAN_NAP,
+        CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_E200 = CPU_FTR_USE_TB,
+        CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_BIG_PHYS,
+        CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
+#ifdef __powerpc64__
+        CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
+        CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+            CPU_FTR_MMCRA | CPU_FTR_CTRL,
+        CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+        CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+        CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+            CPU_FTR_MMCRA | CPU_FTR_SMT |
+            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+            CPU_FTR_MMCRA_SIHV,
+        CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
+        CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
+#endif
+        CPU_FTRS_POSSIBLE =
+#if CLASSIC_PPC
+            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
+            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
+            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
+            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
+            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
+            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
+            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
+            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
+#else
+            CPU_FTRS_GENERIC_32 |
+#endif
+#ifdef CONFIG_PPC64BRIDGE
+            CPU_FTRS_POWER3_32 |
+#endif
+#ifdef CONFIG_POWER4
+            CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
+#endif
+#ifdef CONFIG_8xx
+            CPU_FTRS_8XX |
+#endif
+#ifdef CONFIG_40x
+            CPU_FTRS_40X |
+#endif
+#ifdef CONFIG_44x
+            CPU_FTRS_44X |
+#endif
+#ifdef CONFIG_E200
+            CPU_FTRS_E200 |
+#endif
+#ifdef CONFIG_E500
+            CPU_FTRS_E500 | CPU_FTRS_E500_2 |
+#endif
+#ifdef __powerpc64__
+            CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
+            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
+#endif
+            0,
+        CPU_FTRS_ALWAYS =
+#if CLASSIC_PPC
+            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
+            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
+            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
+            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
+            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
+            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
+            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
+            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
+#else
+            CPU_FTRS_GENERIC_32 &
+#endif
+#ifdef CONFIG_PPC64BRIDGE
+            CPU_FTRS_POWER3_32 &
+#endif
+#ifdef CONFIG_POWER4
+            CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
+#endif
+#ifdef CONFIG_8xx
+            CPU_FTRS_8XX &
+#endif
+#ifdef CONFIG_40x
+            CPU_FTRS_40X &
+#endif
+#ifdef CONFIG_44x
+            CPU_FTRS_44X &
+#endif
+#ifdef CONFIG_E200
+            CPU_FTRS_E200 &
+#endif
+#ifdef CONFIG_E500
+            CPU_FTRS_E500 & CPU_FTRS_E500_2 &
+#endif
+#ifdef __powerpc64__
+            CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
+            CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
+#endif
+            CPU_FTRS_POSSIBLE,
+};
+static inline int cpu_has_feature(unsigned long feature)
+{
+        return (CPU_FTRS_ALWAYS & feature) ||
+               (CPU_FTRS_POSSIBLE
+                & cur_cpu_spec->cpu_features
+                & feature);
+}
+#endif /* !__ASSEMBLY__ */
+#ifdef __ASSEMBLY__
+#define BEGIN_FTR_SECTION               98:
+#ifndef __powerpc64__
+#define END_FTR_SECTION(msk, val)               \
+99:                                             \
+        .section __ftr_fixup,"a";               \
+        .align 2;                               \
+        .long msk;                              \
+        .long val;                              \
+        .long 98b;                              \
+        .long 99b;                              \
+        .previous
+#else /* __powerpc64__ */
+#define END_FTR_SECTION(msk, val)               \
+99:                                             \
+        .section __ftr_fixup,"a";               \
+        .align 3;                               \
+        .llong msk;                             \
+        .llong val;                             \
+        .llong 98b;                             \
+        .llong 99b;                             \
+        .previous
+#endif /* __powerpc64__ */
+#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
+#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/include/asm-ppc/dbdma.h b/include/asm-powerpc/dbdma.h
index 8973565f95d3..8973565f95d3 100644
--- a/include/asm-ppc/dbdma.h
+++ b/include/asm-powerpc/dbdma.h
diff --git a/include/asm-ppc/dma.h b/include/asm-powerpc/dma.h
index cc8e5cd8c9d2..926378d2cd94 100644
--- a/include/asm-ppc/dma.h
+++ b/include/asm-powerpc/dma.h
@@ -1,18 +1,14 @@
+#ifndef _ASM_POWERPC_DMA_H
+#define _ASM_POWERPC_DMA_H
 /*
- * include/asm-ppc/dma.h: Defines for using and allocating dma channels.
+ * Defines for using and allocating dma channels.
 * Written by Hennus Bergman, 1992.
 * High DMA channel support & info by Hannu Savolainen
 * and John Boyd, Nov. 1992.
 * Changes for ppc sound by Christoph Nadig
 */
-#ifdef __KERNEL__
-#include <linux/config.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-#include <asm/system.h>
 /*
 * Note: Adapted for PowerPC by Gary Thomas
 * Modified by Cort Dougan <cort@cs.nmt.edu>
@@ -25,8 +21,10 @@
 * with a grain of salt.
 */
-#ifndef _ASM_DMA_H
+#include <linux/config.h>
-#define _ASM_DMA_H
+#include <asm/io.h>
+#include <linux/spinlock.h>
+#include <asm/system.h>
 #ifndef MAX_DMA_CHANNELS
 #define MAX_DMA_CHANNELS        8
@@ -34,11 +32,9 @@
 /* The maximum address that we can perform a DMA transfer to on this platform */
 /* Doesn't really apply... */
-#define MAX_DMA_ADDRESS         0xFFFFFFFF
+#define MAX_DMA_ADDRESS         (~0UL)
-/* in arch/ppc/kernel/setup.c -- Cort */
+#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
-extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
-extern unsigned long ISA_DMA_THRESHOLD;
 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
 #define dma_outb        outb_p
@@ -171,7 +167,18 @@ extern long ppc_cs4232_dma, ppc_cs4232_dma2;
 #define DMA1_EXT_REG            0x40B
 #define DMA2_EXT_REG            0x4D6
+#ifndef __powerpc64__
+    /* in arch/ppc/kernel/setup.c -- Cort */
+    extern unsigned int DMA_MODE_WRITE;
+    extern unsigned int DMA_MODE_READ;
+    extern unsigned long ISA_DMA_THRESHOLD;
+#else
+    #define DMA_MODE_READ       0x44    /* I/O to memory, no autoinit, increment, single mode */
+    #define DMA_MODE_WRITE      0x48    /* memory to I/O, no autoinit, increment, single mode */
+#endif
 #define DMA_MODE_CASCADE        0xC0    /* pass thru DREQ->HRQ, DACK<-HLDA only */
 #define DMA_AUTOINIT            0x10
 extern spinlock_t dma_spin_lock;
@@ -200,8 +207,9 @@ static __inline__ void enable_dma(unsigned int dmanr)
        if (dmanr <= 3) {
                dma_outb(dmanr, DMA1_MASK_REG);
                dma_outb(ucDmaCmd, DMA1_CMD_REG);       /* Enable group */
-        } else
+        } else {
                dma_outb(dmanr & 3, DMA2_MASK_REG);
+        }
 }
 static __inline__ void disable_dma(unsigned int dmanr)
@@ -290,19 +298,26 @@ static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
 {
        if (dmanr <= 3) {
-                dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
+                dma_outb(phys & 0xff,
-                dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
+                         ((dmanr & 3) << 1) + IO_DMA1_BASE);
+                dma_outb((phys >> 8) & 0xff,
+                         ((dmanr & 3) << 1) + IO_DMA1_BASE);
        } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
-                dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb(phys & 0xff,
-                dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 8) & 0xff,
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
                dma_outb((dmanr & 3), DMA2_EXT_REG);
        } else {
-                dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 1) & 0xff,
-                dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 9) & 0xff,
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
        }
        set_dma_page(dmanr, phys >> 16);
 }
 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 * a specific DMA channel.
 * You must ensure the parameters are valid.
@@ -315,21 +330,24 @@ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 {
        count--;
        if (dmanr <= 3) {
-                dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
+                dma_outb(count & 0xff,
-                dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
+                         ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
-                         IO_DMA1_BASE);
+                dma_outb((count >> 8) & 0xff,
+                         ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
        } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
-                dma_outb(count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
+                dma_outb(count & 0xff,
-                dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
-                         IO_DMA2_BASE);
+                dma_outb((count >> 8) & 0xff,
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
        } else {
-                dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
+                dma_outb((count >> 1) & 0xff,
-                         IO_DMA2_BASE);
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
-                dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
+                dma_outb((count >> 9) & 0xff,
-                         IO_DMA2_BASE);
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
        }
 }
 /* Get DMA residue count. After a DMA transfer, this
 * should return zero. Reading this while a DMA transfer is
 * still in progress will return unpredictable results.
@@ -340,8 +358,8 @@ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 */
 static __inline__ int get_dma_residue(unsigned int dmanr)
 {
-        unsigned int io_port = (dmanr <= 3) ?
+        unsigned int io_port = (dmanr <= 3)
-            ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
+            ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
            : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
        /* using short to get 16-bit wrap around */
@@ -352,7 +370,6 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
        return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
            ? count : (count << 1);
 }
 /* These are in kernel/dma.c: */
@@ -367,5 +384,7 @@ extern int isa_dma_bridge_buggy;
 #else
 #define isa_dma_bridge_buggy    (0)
 #endif
-#endif                          /* _ASM_DMA_H */
-#endif                          /* __KERNEL__ */
+#endif  /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
+#endif  /* _ASM_POWERPC_DMA_H */
diff --git a/include/asm-ppc64/elf.h b/include/asm-powerpc/elf.h
index c919a89343db..d140577d0a05 100644
--- a/include/asm-ppc64/elf.h
+++ b/include/asm-powerpc/elf.h
@@ -1,10 +1,11 @@
-#ifndef __PPC64_ELF_H
+#ifndef _ASM_POWERPC_ELF_H
-#define __PPC64_ELF_H
+#define _ASM_POWERPC_ELF_H
 #include <asm/types.h>
 #include <asm/ptrace.h>
 #include <asm/cputable.h>
 #include <asm/auxvec.h>
+#include <asm/page.h>
 /* PowerPC relocations defined by the ABIs */
 #define R_PPC_NONE              0
@@ -75,7 +76,7 @@
 #define R_PPC_GOT_DTPREL16_HI   93 /* half16*   (sym+add)@got@dtprel@h */
 #define R_PPC_GOT_DTPREL16_HA   94 /* half16*   (sym+add)@got@dtprel@ha */
-/* Keep this the last entry.  */
+/* keep this the last entry. */
 #define R_PPC_NUM               95
 /*
@@ -90,8 +91,6 @@
 #define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
 #define ELF_NFPREG      33      /* includes fpscr */
-#define ELF_NVRREG32    33      /* includes vscr & vrsave stuffed together */
-#define ELF_NVRREG      34      /* includes vscr & vrsave in split vectors */
 typedef unsigned long elf_greg_t64;
 typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
@@ -100,8 +99,21 @@ typedef unsigned int elf_greg_t32;
 typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
 /*
- * These are used to set parameters in the core dumps.
+ * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
 */
+#ifdef __powerpc64__
+# define ELF_NVRREG32   33      /* includes vscr & vrsave stuffed together */
+# define ELF_NVRREG     34      /* includes vscr & vrsave in split vectors */
+# define ELF_GREG_TYPE  elf_greg_t64
+#else
+# define ELF_NEVRREG    34      /* includes acc (as 2) */
+# define ELF_NVRREG     33      /* includes vscr */
+# define ELF_GREG_TYPE  elf_greg_t32
+# define ELF_ARCH       EM_PPC
+# define ELF_CLASS      ELFCLASS32
+# define ELF_DATA       ELFDATA2MSB
+#endif /* __powerpc64__ */
 #ifndef ELF_ARCH
 # define ELF_ARCH       EM_PPC64
 # define ELF_CLASS      ELFCLASS64
@@ -114,8 +126,9 @@ typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
  typedef elf_greg_t32 elf_greg_t;
  typedef elf_gregset_t32 elf_gregset_t;
 # define elf_addr_t u32
-#endif
+#endif /* ELF_ARCH */
+/* Floating point registers */
 typedef double elf_fpreg_t;
 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
@@ -125,7 +138,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 * The entry with index 32 contains the vscr as the last word (offset 12) 
 * within the quadword.  This allows the vscr to be stored as either a 
 * quadword (since it must be copied via a vector register to/from storage) 
- * or as a word.  The entry with index 33 contains the vrsave as the first 
+ * or as a word.  
+ *
+ * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first  
 * word (offset 0) within the quadword.
 *
 * This definition of the VMX state is compatible with the current PPC32 
@@ -138,7 +153,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 */
 typedef __vector128 elf_vrreg_t;
 typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
+#ifdef __powerpc64__
 typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
+#endif
 /*
 * This is used to ensure we don't load something for the wrong architecture.
@@ -146,7 +163,7 @@ typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
 #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
 #define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
   use of this is to invoke "./ld.so someprog" to test out a new version of
@@ -158,26 +175,34 @@ typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
 #ifdef __KERNEL__
 /* Common routine for both 32-bit and 64-bit processes */
-static inline void ppc64_elf_core_copy_regs(elf_gregset_t elf_regs,
+static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
                                            struct pt_regs *regs)
 {
-        int i;
+        int i, nregs;
-        int gprs = sizeof(struct pt_regs)/sizeof(elf_greg_t64);
+        memset((void *)elf_regs, 0, sizeof(elf_gregset_t));
-        if (gprs > ELF_NGREG)
-                gprs = ELF_NGREG;
+        /* Our registers are always unsigned longs, whether we're a 32 bit
+         * process or 64 bit, on either a 64 bit or 32 bit kernel.
-        for (i=0; i < gprs; i++)
+         * Don't use ELF_GREG_TYPE here. */
-                elf_regs[i] = (elf_greg_t)((elf_greg_t64 *)regs)[i];
+        nregs = sizeof(struct pt_regs) / sizeof(unsigned long);
+        if (nregs > ELF_NGREG)
+                nregs = ELF_NGREG;
+        for (i = 0; i < nregs; i++) {
+                /* This will correctly truncate 64 bit registers to 32 bits
+                 * for a 32 bit process on a 64 bit kernel. */
+                elf_regs[i] = (elf_greg_t)((ELF_GREG_TYPE *)regs)[i];
+        }
 }
-#define ELF_CORE_COPY_REGS(gregs, regs) ppc64_elf_core_copy_regs(gregs, regs);
+#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
 static inline int dump_task_regs(struct task_struct *tsk,
                                 elf_gregset_t *elf_regs)
 {
        struct pt_regs *regs = tsk->thread.regs;
        if (regs)
-                ppc64_elf_core_copy_regs(*elf_regs, regs);
+                ppc_elf_core_copy_regs(*elf_regs, regs);
        return 1;
 }
@@ -186,15 +211,17 @@ static inline int dump_task_regs(struct task_struct *tsk,
 extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 
 #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
-/* XXX Should we define the XFPREGS using altivec ??? */
+#endif /* __KERNEL__ */
-#endif
-/* This yields a mask that user programs can use to figure out what
+/* ELF_HWCAP yields a mask that user programs can use to figure out what
   instruction set this cpu supports.  This could be done in userspace,
   but it's not easy, and we've already done it here.  */
+# define ELF_HWCAP      (cur_cpu_spec->cpu_user_features)
-#define ELF_HWCAP       (cur_cpu_spec->cpu_user_features)
+#ifdef __powerpc64__
+# define ELF_PLAT_INIT(_r, load_addr)   do {    \
+        _r->gpr[2] = load_addr;                 \
+} while (0)
+#endif /* __powerpc64__ */
 /* This yields a string that ld.so will use to load implementation
   specific libraries for optimization.  This is more specific in
@@ -205,14 +232,10 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
 #define ELF_PLATFORM    (NULL)
-#define ELF_PLAT_INIT(_r, load_addr)    do { \
-        memset(_r->gpr, 0, sizeof(_r->gpr)); \
-        _r->ctr = _r->link = _r->xer = _r->ccr = 0; \
-        _r->gpr[2] = load_addr; \
-} while (0)
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex, ibcs2)                              \
+#ifdef __powerpc64__
+# define SET_PERSONALITY(ex, ibcs2)                             \
 do {                                                            \
        unsigned long new_flags = 0;                            \
        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)               \
@@ -225,7 +248,6 @@ do {								\
        if (personality(current->personality) != PER_LINUX32)   \
                set_personality(PER_LINUX);                     \
 } while (0)
 /*
 * An executable for which elf_read_implies_exec() returns TRUE will
 * have the READ_IMPLIES_EXEC personality flag set automatically. This
@@ -233,19 +255,26 @@ do {								\
 * the 64bit ABI has never had these issues dont enable the workaround
 * even if we have an executable stack.
 */
-#define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
+# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
                (exec_stk != EXSTACK_DISABLE_X) : 0)
+#else 
+# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#endif /* __powerpc64__ */
-#endif
+#endif /* __KERNEL__ */
 extern int dcache_bsize;
 extern int icache_bsize;
 extern int ucache_bsize;
-/* We do have an arch_setup_additional_pages for vDSO matters */
+#ifdef __powerpc64__
-#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
 struct linux_binprm;
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES /* vDSO has arch_setup_additional_pages */
 extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
+#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
+#else
+#define VDSO_AUX_ENT(a,b)
+#endif /* __powerpc64__ */
 /*
 * The requirements here are:
@@ -265,9 +294,8 @@ do {									\
        NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);                      \
        NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);                      \
        NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);                      \
-        /* vDSO base */                                                 \
+        VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base)        \
-        NEW_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base);        \
+} while (0)
- } while (0)
 /* PowerPC64 relocations defined by the ABIs */
 #define R_PPC64_NONE    R_PPC_NONE
@@ -384,4 +412,4 @@ do {									\
 /* Keep this the last entry.  */
 #define R_PPC64_NUM             107
-#endif /* __PPC64_ELF_H */
+#endif /* _ASM_POWERPC_ELF_H */
diff --git a/include/asm-ppc64/firmware.h b/include/asm-powerpc/firmware.h
index 22bb85cf60af..806c142ae9ea 100644
--- a/include/asm-ppc64/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -1,8 +1,4 @@
 /*
- *  include/asm-ppc64/firmware.h
- *
- *  Extracted from include/asm-ppc64/cputable.h
- *
 *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
 *
 *  Modifications for ppc64:
@@ -13,8 +9,8 @@
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */
-#ifndef __ASM_PPC_FIRMWARE_H
+#ifndef __ASM_POWERPC_FIRMWARE_H
-#define __ASM_PPC_FIRMWARE_H
+#define __ASM_POWERPC_FIRMWARE_H
 #ifdef __KERNEL__
@@ -98,4 +94,4 @@ extern firmware_feature_t firmware_features_table[];
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
-#endif /* __ASM_PPC_FIRMWARE_H */
+#endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/include/asm-ppc64/futex.h b/include/asm-powerpc/futex.h
index cb2640b3a408..37c94e52ab6d 100644
--- a/include/asm-ppc64/futex.h
+++ b/include/asm-powerpc/futex.h
@@ -1,34 +1,35 @@
-#ifndef _ASM_FUTEX_H
+#ifndef _ASM_POWERPC_FUTEX_H
-#define _ASM_FUTEX_H
+#define _ASM_POWERPC_FUTEX_H
 #ifdef __KERNEL__
 #include <linux/futex.h>
 #include <asm/errno.h>
-#include <asm/memory.h>
+#include <asm/synch.h>
 #include <asm/uaccess.h>
+#include <asm/ppc_asm.h>
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
-  __asm__ __volatile (SYNC_ON_SMP                               \
+  __asm__ __volatile ( \
-"1:     lwarx   %0,0,%2\n"                                      \
+        SYNC_ON_SMP \
-        insn                                                    \
+"1:     lwarx   %0,0,%2\n" \
-"2:     stwcx.  %1,0,%2\n\
+        insn \
-        bne-    1b\n\
+"2:     stwcx.  %1,0,%2\n" \
-        li      %1,0\n\
+        "bne-   1b\n" \
-3:      .section .fixup,\"ax\"\n\
+        "li     %1,0\n" \
-4:      li      %1,%3\n\
+"3:     .section .fixup,\"ax\"\n" \
-        b       3b\n\
+"4:     li      %1,%3\n" \
-        .previous\n\
+        "b      3b\n" \
-        .section __ex_table,\"a\"\n\
+        ".previous\n" \
-        .align 3\n\
+        ".section __ex_table,\"a\"\n" \
-        .llong  1b,4b,2b,4b\n\
+        ".align 3\n" \
-        .previous"                                              \
+        DATAL " 1b,4b,2b,4b\n" \
-        : "=&r" (oldval), "=&r" (ret)                           \
+        ".previous" \
-        : "b" (uaddr), "i" (-EFAULT), "1" (oparg)               \
+        : "=&r" (oldval), "=&r" (ret) \
+        : "b" (uaddr), "i" (-EFAULT), "1" (oparg) \
        : "cr0", "memory")
-static inline int
+static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
-futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
 {
        int op = (encoded_op >> 28) & 7;
        int cmp = (encoded_op >> 24) & 15;
@@ -79,5 +80,5 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
        return ret;
 }
-#endif
+#endif /* __KERNEL__ */
-#endif
+#endif /* _ASM_POWERPC_FUTEX_H */
diff --git a/include/asm-powerpc/grackle.h b/include/asm-powerpc/grackle.h
new file mode 100644
index 000000000000..563c7a5e64c9
--- /dev/null
+++ b/include/asm-powerpc/grackle.h
@@ -0,0 +1,7 @@
+/*
+ * Functions for setting up and using a MPC106 northbridge
+ */
+#include <asm/pci-bridge.h>
+extern void setup_grackle(struct pci_controller *hose);
diff --git a/include/asm-ppc/hardirq.h b/include/asm-powerpc/hardirq.h
index 94f1411b1a93..3b3e3b49ec12 100644
--- a/include/asm-ppc/hardirq.h
+++ b/include/asm-powerpc/hardirq.h
@@ -1,11 +1,8 @@
-#ifdef __KERNEL__
+#ifndef _ASM_POWERPC_HARDIRQ_H
-#ifndef __ASM_HARDIRQ_H
+#define _ASM_POWERPC_HARDIRQ_H
-#define __ASM_HARDIRQ_H
-#include <linux/config.h>
-#include <linux/cache.h>
-#include <linux/smp_lock.h>
 #include <asm/irq.h>
+#include <asm/bug.h>
 /* The __last_jiffy_stamp field is needed to ensure that no decrementer
 * interrupt is lost on SMP machines. Since on most CPUs it is in the same
@@ -13,7 +10,7 @@
 * for uniformity.
 */
 typedef struct {
-        unsigned long __softirq_pending;        /* set_bit is used on this */
+        unsigned int __softirq_pending; /* set_bit is used on this */
        unsigned int __last_jiffy_stamp;
 } ____cacheline_aligned irq_cpustat_t;
@@ -27,5 +24,4 @@ static inline void ack_bad_irq(int irq)
        BUG();
 }
-#endif /* __ASM_HARDIRQ_H */
+#endif /* _ASM_POWERPC_HARDIRQ_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/heathrow.h b/include/asm-powerpc/heathrow.h
index 22ac179856b9..22ac179856b9 100644
--- a/include/asm-ppc/heathrow.h
+++ b/include/asm-powerpc/heathrow.h
diff --git a/include/asm-ppc64/hw_irq.h b/include/asm-powerpc/hw_irq.h
index baea40e695ec..c37b31b96337 100644
--- a/include/asm-ppc64/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -1,22 +1,17 @@
 /*
 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- *
- * Use inline IRQs where possible - Anton Blanchard <anton@au.ibm.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
 */
+#ifndef _ASM_POWERPC_HW_IRQ_H
+#define _ASM_POWERPC_HW_IRQ_H
 #ifdef __KERNEL__
-#ifndef _PPC64_HW_IRQ_H
-#define _PPC64_HW_IRQ_H
 #include <linux/config.h>
 #include <linux/errno.h>
-#include <asm/irq.h>
+#include <asm/ptrace.h>
+#include <asm/processor.h>
-int timer_interrupt(struct pt_regs *);
+extern void timer_interrupt(struct pt_regs *);
 extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq);
 #ifdef CONFIG_PPC_ISERIES
@@ -33,45 +28,60 @@ extern void local_irq_restore(unsigned long);
 #else
-#define local_save_flags(flags) ((flags) = mfmsr())
+#if defined(CONFIG_BOOKE)
+#define SET_MSR_EE(x)   mtmsr(x)
+#define local_irq_restore(flags)        __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
+#elif defined(__powerpc64__)
+#define SET_MSR_EE(x)   __mtmsrd(x, 1)
 #define local_irq_restore(flags) do { \
        __asm__ __volatile__("": : :"memory"); \
        __mtmsrd((flags), 1); \
 } while(0)
+#else
+#define SET_MSR_EE(x)   mtmsr(x)
+#define local_irq_restore(flags)        mtmsr(flags)
+#endif
 static inline void local_irq_disable(void)
 {
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 0": : :"memory");
+#else
        unsigned long msr;
-        msr = mfmsr();
-        __mtmsrd(msr & ~MSR_EE, 1);
        __asm__ __volatile__("": : :"memory");
+        msr = mfmsr();
+        SET_MSR_EE(msr & ~MSR_EE);
+#endif
 }
 static inline void local_irq_enable(void)
 {
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 1": : :"memory");
+#else
        unsigned long msr;
        __asm__ __volatile__("": : :"memory");
        msr = mfmsr();
-        __mtmsrd(msr | MSR_EE, 1);
+        SET_MSR_EE(msr | MSR_EE);
+#endif
 }
-static inline void __do_save_and_cli(unsigned long *flags)
+static inline void local_irq_save_ptr(unsigned long *flags)
 {
        unsigned long msr;
        msr = mfmsr();
        *flags = msr;
-        __mtmsrd(msr & ~MSR_EE, 1);
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 0": : :"memory");
+#else
+        SET_MSR_EE(msr & ~MSR_EE);
+#endif
        __asm__ __volatile__("": : :"memory");
 }
-#define local_irq_save(flags)          __do_save_and_cli(&flags)
+#define local_save_flags(flags) ((flags) = mfmsr())
+#define local_irq_save(flags)   local_irq_save_ptr(&flags)
-#define irqs_disabled()                         \
+#define irqs_disabled()         ((mfmsr() & MSR_EE) == 0)
-({                                              \
-        unsigned long flags;                    \
-        local_save_flags(flags);                \
-        !(flags & MSR_EE);                      \
-})
 #endif /* CONFIG_PPC_ISERIES */
@@ -99,6 +109,6 @@ static inline void __do_save_and_cli(unsigned long *flags)
 */
 struct hw_interrupt_type;
 static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
- 
-#endif /* _PPC64_HW_IRQ_H */
+#endif  /* __KERNEL__ */
-#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/include/asm-powerpc/i8259.h b/include/asm-powerpc/i8259.h
new file mode 100644
index 000000000000..fc4bfee124d7
--- /dev/null
+++ b/include/asm-powerpc/i8259.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_POWERPC_I8259_H
+#define _ASM_POWERPC_I8259_H
+#include <linux/irq.h>
+extern struct hw_interrupt_type i8259_pic;
+extern void i8259_init(unsigned long intack_addr, int offset);
+extern int i8259_irq(struct pt_regs *regs);
+extern int i8259_irq_cascade(struct pt_regs *regs, void *unused);
+#endif /* _ASM_POWERPC_I8259_H */
diff --git a/include/asm-powerpc/ioctls.h b/include/asm-powerpc/ioctls.h
index 5b94ff489b8b..279a6229584b 100644
--- a/include/asm-powerpc/ioctls.h
+++ b/include/asm-powerpc/ioctls.h
@@ -62,6 +62,9 @@
 # define TIOCM_DSR      0x100
 # define TIOCM_CD       TIOCM_CAR
 # define TIOCM_RI       TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
 #define TIOCGSOFTCAR    0x5419
 #define TIOCSSOFTCAR    0x541A
diff --git a/include/asm-ppc64/iommu.h b/include/asm-powerpc/iommu.h
index c2f3b6e8a42f..9d91bdd667ae 100644
--- a/include/asm-ppc64/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -1,5 +1,4 @@
 /*
- * iommu.h
 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
 * Rewrite, cleanup:
 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
@@ -22,6 +21,7 @@
 #ifndef _ASM_IOMMU_H
 #define _ASM_IOMMU_H
+#include <linux/config.h>
 #include <asm/types.h>
 #include <linux/spinlock.h>
 #include <linux/device.h>
@@ -29,44 +29,11 @@
 /*
 * IOMAP_MAX_ORDER defines the largest contiguous block
- * of dma (tce) space we can get.  IOMAP_MAX_ORDER = 13
+ * of dma space we can get.  IOMAP_MAX_ORDER = 13
 * allows up to 2**12 pages (4096 * 4096) = 16 MB
 */
 #define IOMAP_MAX_ORDER 13
-/*
- * Tces come in two formats, one for the virtual bus and a different
- * format for PCI
- */
-#define TCE_VB  0
-#define TCE_PCI 1
-/* tce_entry
- * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
- * abstracted so layout is irrelevant.
- */
-union tce_entry {
-        unsigned long te_word;
-        struct {
-                unsigned int  tb_cacheBits :6;  /* Cache hash bits - not used */
-                unsigned int  tb_rsvd      :6;
-                unsigned long tb_rpn       :40; /* Real page number */
-                unsigned int  tb_valid     :1;  /* Tce is valid (vb only) */
-                unsigned int  tb_allio     :1;  /* Tce is valid for all lps (vb only) */
-                unsigned int  tb_lpindex   :8;  /* LpIndex for user of TCE (vb only) */
-                unsigned int  tb_pciwr     :1;  /* Write allowed (pci only) */
-                unsigned int  tb_rdwr      :1;  /* Read allowed  (pci), Write allowed (vb) */
-        } te_bits;
-#define te_cacheBits te_bits.tb_cacheBits
-#define te_rpn       te_bits.tb_rpn
-#define te_valid     te_bits.tb_valid
-#define te_allio     te_bits.tb_allio
-#define te_lpindex   te_bits.tb_lpindex
-#define te_pciwr     te_bits.tb_pciwr
-#define te_rdwr      te_bits.tb_rdwr
-};
 struct iommu_table {
        unsigned long  it_busno;     /* Bus number this table belongs to */
        unsigned long  it_size;      /* Size of iommu table in entries */
@@ -83,6 +50,7 @@ struct iommu_table {
 };
 struct scatterlist;
+struct device_node;
 #ifdef CONFIG_PPC_MULTIPLATFORM
@@ -104,9 +72,8 @@ extern void iommu_devnode_init_pSeries(struct device_node *dn);
 #ifdef CONFIG_PPC_ISERIES
-struct iSeries_Device_Node;
 /* Creates table for an individual device node */
-extern void iommu_devnode_init_iSeries(struct iSeries_Device_Node *dn);
+extern void iommu_devnode_init_iSeries(struct device_node *dn);
 #endif /* CONFIG_PPC_ISERIES */
diff --git a/include/asm-powerpc/ipcbuf.h b/include/asm-powerpc/ipcbuf.h
new file mode 100644
index 000000000000..2c3e1d94db1d
--- /dev/null
+++ b/include/asm-powerpc/ipcbuf.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_POWERPC_IPCBUF_H
+#define _ASM_POWERPC_IPCBUF_H
+/*
+ * The ipc64_perm structure for the powerpc is identical to
+ * kern_ipc_perm as we have always had 32-bit UIDs and GIDs in the
+ * kernel.  Note extra padding because this structure is passed back
+ * and forth between kernel and user space.  Pad space is left for:
+ *      - 1 32-bit value to fill up for 8-byte alignment
+ *      - 2 miscellaneous 64-bit values
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/types.h>
+struct ipc64_perm
+{
+        __kernel_key_t  key;
+        __kernel_uid_t  uid;
+        __kernel_gid_t  gid;
+        __kernel_uid_t  cuid;
+        __kernel_gid_t  cgid;
+        __kernel_mode_t mode;
+        unsigned int    seq;
+        unsigned int    __pad1;
+        unsigned long long __unused1;
+        unsigned long long __unused2;
+};
+#endif /* _ASM_POWERPC_IPCBUF_H */
diff --git a/include/asm-ppc/irq.h b/include/asm-powerpc/irq.h
index bd9674807f05..b3935ea28fff 100644
--- a/include/asm-ppc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -1,11 +1,23 @@
 #ifdef __KERNEL__
-#ifndef _ASM_IRQ_H
+#ifndef _ASM_POWERPC_IRQ_H
-#define _ASM_IRQ_H
+#define _ASM_POWERPC_IRQ_H
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
 #include <linux/config.h>
-#include <asm/machdep.h>                /* ppc_md */
+#include <linux/threads.h>
+#include <asm/types.h>
 #include <asm/atomic.h>
+/* this number is used when no interrupt has been assigned */
+#define NO_IRQ                  (-1)
 /*
 * These constants are used for passing information about interrupt
 * signal polarity and level/edge sensing to the low-level PIC chip
@@ -24,6 +36,50 @@
 */
 #define ARCH_HAS_IRQ_PER_CPU
+#define get_irq_desc(irq) (&irq_desc[(irq)])
+/* Define a way to iterate across irqs. */
+#define for_each_irq(i) \
+        for ((i) = 0; (i) < NR_IRQS; ++(i))
+#ifdef CONFIG_PPC64
+/*
+ * Maximum number of interrupt sources that we can handle.
+ */
+#define NR_IRQS         512
+/* Interrupt numbers are virtual in case they are sparsely
+ * distributed by the hardware.
+ */
+extern unsigned int virt_irq_to_real_map[NR_IRQS];
+/* Create a mapping for a real_irq if it doesn't already exist.
+ * Return the virtual irq as a convenience.
+ */
+int virt_irq_create_mapping(unsigned int real_irq);
+void virt_irq_init(void);
+static inline unsigned int virt_irq_to_real(unsigned int virt_irq)
+{
+        return virt_irq_to_real_map[virt_irq];
+}
+extern unsigned int real_irq_to_virt_slowpath(unsigned int real_irq);
+/*
+ * List of interrupt controllers.
+ */
+#define IC_INVALID    0
+#define IC_OPEN_PIC   1
+#define IC_PPC_XIC    2
+#define IC_CELL_PIC   3
+#define IC_ISERIES    4
+extern u64 ppc64_interrupt_controller;
+#else /* 32-bit */
 #if defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
@@ -66,11 +122,6 @@
 #define NR_UIC_IRQS UIC_WIDTH
 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
 #endif
-static __inline__ int
-irq_canonicalize(int irq)
-{
-        return (irq);
-}
 #elif defined(CONFIG_44x)
 #include <asm/ibm44x.h>
@@ -78,12 +129,6 @@ irq_canonicalize(int irq)
 #define NR_UIC_IRQS     32
 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
-static __inline__ int
-irq_canonicalize(int irq)
-{
-        return (irq);
-}
 #elif defined(CONFIG_8xx)
 /* Now include the board configuration specific associations.
@@ -170,20 +215,9 @@ irq_canonicalize(int irq)
 */
 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
-/* always the same on 8xx -- Cort */
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
 #elif defined(CONFIG_83xx)
 #include <asm/mpc83xx.h>
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
 #define NR_IRQS (NR_IPIC_INTS)
 #elif defined(CONFIG_85xx)
@@ -307,17 +341,13 @@ static __inline__ int irq_canonicalize(int irq)
 #define SIU_INT_PC1             ((uint)0x3e+CPM_IRQ_OFFSET)
 #define SIU_INT_PC0             ((uint)0x3f+CPM_IRQ_OFFSET)
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
 #else /* CONFIG_40x + CONFIG_8xx */
 /*
 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
 * so it is the max of them all
 */
 #define NR_IRQS                 256
+#define __DO_IRQ_CANON  1
 #ifndef CONFIG_8260
@@ -394,25 +424,81 @@ static __inline__ int irq_canonicalize(int irq)
 #endif /* CONFIG_8260 */
+#endif
+#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
+/* pedantic: these are long because they are used with set_bit --RR */
+extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
+extern atomic_t ppc_n_lost_interrupts;
+#define virt_irq_create_mapping(x)      (x)
+#endif
 /*
- * This gets called from serial.c, which is now used on
+ * Because many systems have two overlapping names spaces for
- * powermacs as well as prep/chrp boxes.
+ * interrupts (ISA and XICS for example), and the ISA interrupts
- * Prep and chrp both have cascaded 8259 PICs.
+ * have historically not been easy to renumber, we allow ISA
+ * interrupts to take values 0 - 15, and shift up the remaining
+ * interrupts by 0x10.
 */
+#define NUM_ISA_INTERRUPTS      0x10
+extern int __irq_offset_value;
+static inline int irq_offset_up(int irq)
+{
+        return(irq + __irq_offset_value);
+}
+static inline int irq_offset_down(int irq)
+{
+        return(irq - __irq_offset_value);
+}
+static inline int irq_offset_value(void)
+{
+        return __irq_offset_value;
+}
+#ifdef __DO_IRQ_CANON
+extern int ppc_do_canonicalize_irqs;
+#else
+#define ppc_do_canonicalize_irqs        0
+#endif
 static __inline__ int irq_canonicalize(int irq)
 {
-        if (ppc_md.irq_canonicalize)
+        if (ppc_do_canonicalize_irqs && irq == 2)
-                return ppc_md.irq_canonicalize(irq);
+                irq = 9;
        return irq;
 }
-#endif
+extern int distribute_irqs;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
+struct irqaction;
-/* pedantic: these are long because they are used with set_bit --RR */
+struct pt_regs;
-extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
-extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
+#ifdef CONFIG_IRQSTACKS
-extern atomic_t ppc_n_lost_interrupts;
+/*
+ * Per-cpu stacks for handling hard and soft interrupts.
+ */
+extern struct thread_info *hardirq_ctx[NR_CPUS];
+extern struct thread_info *softirq_ctx[NR_CPUS];
+extern void irq_ctx_init(void);
+extern void call_do_softirq(struct thread_info *tp);
+extern int call_handle_IRQ_event(int irq, struct pt_regs *regs,
+                        struct irqaction *action, struct thread_info *tp);
+#define __ARCH_HAS_DO_SOFTIRQ
+#else
+#define irq_ctx_init()
+#endif /* CONFIG_IRQSTACKS */
+extern void do_IRQ(struct pt_regs *regs);
 #endif /* _ASM_IRQ_H */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/iSeries/HvCall.h b/include/asm-powerpc/iseries/hv_call.h
index c3f19475c0d9..e9f831c9a5e5 100644
--- a/include/asm-ppc64/iSeries/HvCall.h
+++ b/include/asm-powerpc/iseries/hv_call.h
@@ -20,11 +20,11 @@
 * This file contains the "hypervisor call" interface which is used to
 * drive the hypervisor from the OS.
 */
-#ifndef _HVCALL_H
+#ifndef _ASM_POWERPC_ISERIES_HV_CALL_H
-#define _HVCALL_H
+#define _ASM_POWERPC_ISERIES_HV_CALL_H
-#include <asm/iSeries/HvCallSc.h>
+#include <asm/iseries/hv_call_sc.h>
-#include <asm/iSeries/HvTypes.h>
+#include <asm/iseries/hv_types.h>
 #include <asm/paca.h>
 /* Type of yield for HvCallBaseYieldProcessor */
@@ -110,4 +110,4 @@ static inline void HvCall_sendIPI(struct paca_struct *targetPaca)
        HvCall1(HvCallBaseSendIPI, targetPaca->paca_index);
 }
-#endif /* _HVCALL_H */
+#endif /* _ASM_POWERPC_ISERIES_HV_CALL_H */
diff --git a/include/asm-ppc64/iSeries/HvCallEvent.h b/include/asm-powerpc/iseries/hv_call_event.h
index 5d9a327d0122..46763a30590a 100644
--- a/include/asm-ppc64/iSeries/HvCallEvent.h
+++ b/include/asm-powerpc/iseries/hv_call_event.h
@@ -20,11 +20,11 @@
 * This file contains the "hypervisor call" interface which is used to
 * drive the hypervisor from the OS.
 */
-#ifndef _HVCALLEVENT_H
+#ifndef _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
-#define _HVCALLEVENT_H
+#define _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
-#include <asm/iSeries/HvCallSc.h>
+#include <asm/iseries/hv_call_sc.h>
-#include <asm/iSeries/HvTypes.h>
+#include <asm/iseries/hv_types.h>
 #include <asm/abs_addr.h>
 struct HvLpEvent;
@@ -250,4 +250,4 @@ static inline HvLpDma_Rc HvCallEvent_dmaToSp(void *local, u32 remote,
        return HvCall4(HvCallEventDmaToSp, abs_addr, remote, length, dir);
 }
-#endif /* _HVCALLEVENT_H */
+#endif /* _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H */
diff --git a/include/asm-ppc64/iSeries/HvCallSc.h b/include/asm-powerpc/iseries/hv_call_sc.h
index a62cef3822f9..dec7e9d9ab78 100644
--- a/include/asm-ppc64/iSeries/HvCallSc.h
+++ b/include/asm-powerpc/iseries/hv_call_sc.h
@@ -16,8 +16,8 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _HVCALLSC_H
+#ifndef _ASM_POWERPC_ISERIES_HV_CALL_SC_H
-#define _HVCALLSC_H
+#define _ASM_POWERPC_ISERIES_HV_CALL_SC_H
 #include <linux/types.h>
@@ -48,4 +48,4 @@ extern u64 HvCall5Ret16(u64, void *, u64, u64, u64, u64, u64);
 extern u64 HvCall6Ret16(u64, void *, u64, u64, u64, u64, u64, u64);
 extern u64 HvCall7Ret16(u64, void *, u64, u64 ,u64 ,u64 ,u64 ,u64 ,u64);
-#endif /* _HVCALLSC_H */
+#endif /* _ASM_POWERPC_ISERIES_HV_CALL_SC_H */
diff --git a/include/asm-ppc64/iSeries/HvCallXm.h b/include/asm-powerpc/iseries/hv_call_xm.h
index 8b9ba608daaf..ca9202cb01ed 100644
--- a/include/asm-ppc64/iSeries/HvCallXm.h
+++ b/include/asm-powerpc/iseries/hv_call_xm.h
@@ -2,11 +2,11 @@
 * This file contains the "hypervisor call" interface which is used to
 * drive the hypervisor from SLIC.
 */
-#ifndef _HVCALLXM_H
+#ifndef _ASM_POWERPC_ISERIES_HV_CALL_XM_H
-#define _HVCALLXM_H
+#define _ASM_POWERPC_ISERIES_HV_CALL_XM_H
-#include <asm/iSeries/HvCallSc.h>
+#include <asm/iseries/hv_call_sc.h>
-#include <asm/iSeries/HvTypes.h>
+#include <asm/iseries/hv_types.h>
 #define HvCallXmGetTceTableParms        HvCallXm +  0
 #define HvCallXmTestBus                 HvCallXm +  1
@@ -75,4 +75,4 @@ static inline u64 HvCallXm_loadTod(void)
        return HvCall0(HvCallXmLoadTod);
 }
-#endif /* _HVCALLXM_H */
+#endif /* _ASM_POWERPC_ISERIES_HV_CALL_XM_H */
diff --git a/include/asm-ppc64/iSeries/HvLpConfig.h b/include/asm-powerpc/iseries/hv_lp_config.h
index f1cf1e70ca3c..bc00f036bca0 100644
--- a/include/asm-ppc64/iSeries/HvLpConfig.h
+++ b/include/asm-powerpc/iseries/hv_lp_config.h
@@ -16,17 +16,17 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _HVLPCONFIG_H
+#ifndef _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
-#define _HVLPCONFIG_H
+#define _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
 /*
 * This file contains the interface to the LPAR configuration data
 * to determine which resources should be allocated to each partition.
 */
-#include <asm/iSeries/HvCallSc.h>
+#include <asm/iseries/hv_call_sc.h>
-#include <asm/iSeries/HvTypes.h>
+#include <asm/iseries/hv_types.h>
-#include <asm/iSeries/ItLpNaca.h>
+#include <asm/iseries/it_lp_naca.h>
 enum {
        HvCallCfg_Cur   = 0,
@@ -135,4 +135,4 @@ static inline HvLpIndex HvLpConfig_getHostingLpIndex(HvLpIndex lp)
        return HvCall1(HvCallCfgGetHostingLpIndex, lp);
 }
-#endif /* _HVLPCONFIG_H */
+#endif /* _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H */
diff --git a/include/asm-ppc64/iSeries/HvLpEvent.h b/include/asm-powerpc/iseries/hv_lp_event.h
index 865000de79b6..499ab1ad0185 100644
--- a/include/asm-ppc64/iSeries/HvLpEvent.h
+++ b/include/asm-powerpc/iseries/hv_lp_event.h
@@ -19,13 +19,13 @@
 /* This file contains the class for HV events in the system. */
-#ifndef _HVLPEVENT_H
+#ifndef _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
-#define _HVLPEVENT_H
+#define _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
 #include <asm/types.h>
 #include <asm/ptrace.h>
-#include <asm/iSeries/HvTypes.h>
+#include <asm/iseries/hv_types.h>
-#include <asm/iSeries/HvCallEvent.h>
+#include <asm/iseries/hv_call_event.h>
 /*
 * HvLpEvent is the structure for Lp Event messages passed between
@@ -139,4 +139,4 @@ extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
 #define HvLpDma_Rc_InvalidAddress 4
 #define HvLpDma_Rc_InvalidLength 5
-#endif /* _HVLPEVENT_H */
+#endif /* _ASM_POWERPC_ISERIES_HV_LP_EVENT_H */
diff --git a/include/asm-ppc64/iSeries/HvTypes.h b/include/asm-powerpc/iseries/hv_types.h
index b1ef2b4cb3e3..c38f7e3d01dc 100644
--- a/include/asm-ppc64/iSeries/HvTypes.h
+++ b/include/asm-powerpc/iseries/hv_types.h
@@ -16,8 +16,8 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _HVTYPES_H
+#ifndef _ASM_POWERPC_ISERIES_HV_TYPES_H
-#define _HVTYPES_H
+#define _ASM_POWERPC_ISERIES_HV_TYPES_H
 /*
 * General typedefs for the hypervisor.
@@ -110,4 +110,4 @@ struct HvLpBufferList {
        u64 len;
 };
-#endif /* _HVTYPES_H */
+#endif /* _ASM_POWERPC_ISERIES_HV_TYPES_H */
diff --git a/include/asm-ppc64/iSeries/iSeries_io.h b/include/asm-powerpc/iseries/iseries_io.h
index 9f79413342b3..56b2113ff0f5 100644
--- a/include/asm-ppc64/iSeries/iSeries_io.h
+++ b/include/asm-powerpc/iseries/iseries_io.h
@@ -1,5 +1,5 @@
-#ifndef _ISERIES_IO_H
+#ifndef _ASM_POWERPC_ISERIES_ISERIES_IO_H
-#define _ISERIES_IO_H
+#define _ASM_POWERPC_ISERIES_ISERIES_IO_H
 #include <linux/config.h>
@@ -46,4 +46,4 @@ extern void iSeries_memcpy_fromio(void *dest,
                const volatile void __iomem *source, size_t n);
 #endif /* CONFIG_PPC_ISERIES */
-#endif /* _ISERIES_IO_H */
+#endif /* _ASM_POWERPC_ISERIES_ISERIES_IO_H */
diff --git a/include/asm-ppc64/iSeries/ItExtVpdPanel.h b/include/asm-powerpc/iseries/it_exp_vpd_panel.h
index 4c546a8802b4..66a17a230c52 100644
--- a/include/asm-ppc64/iSeries/ItExtVpdPanel.h
+++ b/include/asm-powerpc/iseries/it_exp_vpd_panel.h
@@ -16,8 +16,8 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _ITEXTVPDPANEL_H
+#ifndef _ASM_POWERPC_ISERIES_IT_EXT_VPD_PANEL_H
-#define _ITEXTVPDPANEL_H
+#define _ASM_POWERPC_ISERIES_IT_EXT_VPD_PANEL_H
 /*
 *      This struct maps the panel information
@@ -49,4 +49,4 @@ struct ItExtVpdPanel {
 extern struct ItExtVpdPanel     xItExtVpdPanel;
-#endif /* _ITEXTVPDPANEL_H */
+#endif /* _ASM_POWERPC_ISERIES_IT_EXT_VPD_PANEL_H */
diff --git a/include/asm-ppc64/iSeries/ItLpNaca.h b/include/asm-powerpc/iseries/it_lp_naca.h
index 225d0176779d..c3ef1de45d82 100644
--- a/include/asm-ppc64/iSeries/ItLpNaca.h
+++ b/include/asm-powerpc/iseries/it_lp_naca.h
@@ -16,8 +16,8 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _ITLPNACA_H
+#ifndef _ASM_POWERPC_ISERIES_IT_LP_NACA_H
-#define _ITLPNACA_H
+#define _ASM_POWERPC_ISERIES_IT_LP_NACA_H
 #include <linux/types.h>
@@ -77,4 +77,4 @@ struct ItLpNaca {
 extern struct ItLpNaca          itLpNaca;
-#endif /* _ITLPNACA_H */
+#endif /* _ASM_POWERPC_ISERIES_IT_LP_NACA_H */
diff --git a/include/asm-ppc64/iSeries/ItLpQueue.h b/include/asm-powerpc/iseries/it_lp_queue.h
index 69b26ad74135..a60d03afbf95 100644
--- a/include/asm-ppc64/iSeries/ItLpQueue.h
+++ b/include/asm-powerpc/iseries/it_lp_queue.h
@@ -16,8 +16,8 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _ITLPQUEUE_H
+#ifndef _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
-#define _ITLPQUEUE_H
+#define _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
 /*
 *      This control block defines the simple LP queue structure that is
@@ -78,4 +78,4 @@ extern int hvlpevent_is_pending(void);
 extern void process_hvlpevents(struct pt_regs *);
 extern void setup_hvlpevent_queue(void);
-#endif /* _ITLPQUEUE_H */
+#endif /* _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H */
diff --git a/include/asm-ppc64/iSeries/ItLpRegSave.h b/include/asm-powerpc/iseries/it_lp_reg_save.h
index 1b3087e76205..288044b702de 100644
--- a/include/asm-ppc64/iSeries/ItLpRegSave.h
+++ b/include/asm-powerpc/iseries/it_lp_reg_save.h
@@ -16,8 +16,8 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _ITLPREGSAVE_H
+#ifndef _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
-#define _ITLPREGSAVE_H
+#define _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
 /*
 * This control block contains the data that is shared between PLIC
diff --git a/include/asm-ppc64/iSeries/LparMap.h b/include/asm-powerpc/iseries/lpar_map.h
index a6840b186d03..84fc321615bf 100644
--- a/include/asm-ppc64/iSeries/LparMap.h
+++ b/include/asm-powerpc/iseries/lpar_map.h
@@ -16,8 +16,8 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _LPARMAP_H
+#ifndef _ASM_POWERPC_ISERIES_LPAR_MAP_H
-#define _LPARMAP_H
+#define _ASM_POWERPC_ISERIES_LPAR_MAP_H
 #ifndef __ASSEMBLY__
@@ -80,4 +80,4 @@ extern const struct LparMap	xLparMap;
 /* the fixed address where the LparMap exists */
 #define LPARMAP_PHYS            0x7000
-#endif /* _LPARMAP_H */
+#endif /* _ASM_POWERPC_ISERIES_LPAR_MAP_H */
diff --git a/include/asm-ppc64/iSeries/mf.h b/include/asm-powerpc/iseries/mf.h
index 7e6a0d936999..e7bd57a03fb1 100644
--- a/include/asm-ppc64/iSeries/mf.h
+++ b/include/asm-powerpc/iseries/mf.h
@@ -23,13 +23,13 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef _ASM_PPC64_ISERIES_MF_H
+#ifndef _ASM_POWERPC_ISERIES_MF_H
-#define _ASM_PPC64_ISERIES_MF_H
+#define _ASM_POWERPC_ISERIES_MF_H
 #include <linux/types.h>
-#include <asm/iSeries/HvTypes.h>
+#include <asm/iseries/hv_types.h>
-#include <asm/iSeries/HvCallEvent.h>
+#include <asm/iseries/hv_call_event.h>
 struct rtc_time;
@@ -54,4 +54,4 @@ extern int mf_get_rtc(struct rtc_time *tm);
 extern int mf_get_boot_rtc(struct rtc_time *tm);
 extern int mf_set_rtc(struct rtc_time *tm);
-#endif /* _ASM_PPC64_ISERIES_MF_H */
+#endif /* _ASM_POWERPC_ISERIES_MF_H */
diff --git a/include/asm-ppc64/iSeries/vio.h b/include/asm-powerpc/iseries/vio.h
index 6c05e6257f53..7e3a469420dd 100644
--- a/include/asm-ppc64/iSeries/vio.h
+++ b/include/asm-powerpc/iseries/vio.h
@@ -38,11 +38,11 @@
 * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */
-#ifndef _ISERIES_VIO_H
+#ifndef _ASM_POWERPC_ISERIES_VIO_H
-#define _ISERIES_VIO_H
+#define _ASM_POWERPC_ISERIES_VIO_H
-#include <asm/iSeries/HvTypes.h>
+#include <asm/iseries/hv_types.h>
-#include <asm/iSeries/HvLpEvent.h>
+#include <asm/iseries/hv_lp_event.h>
 /*
 * iSeries virtual I/O events use the subtype field in
@@ -127,4 +127,4 @@ struct device;
 extern struct device *iSeries_vio_dev;
-#endif /* _ISERIES_VIO_H */
+#endif /* _ASM_POWERPC_ISERIES_VIO_H */
diff --git a/include/asm-ppc64/kdebug.h b/include/asm-powerpc/kdebug.h
index d383d161cf8d..9dcbac674811 100644
--- a/include/asm-ppc64/kdebug.h
+++ b/include/asm-powerpc/kdebug.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_KDEBUG_H
+#ifndef _ASM_POWERPC_KDEBUG_H
-#define _PPC64_KDEBUG_H 1
+#define _ASM_POWERPC_KDEBUG_H
 /* nearly identical to x86_64/i386 code */
@@ -21,7 +21,7 @@ struct die_args {
   then free.
 */
 int register_die_notifier(struct notifier_block *nb);
-extern struct notifier_block *ppc64_die_chain;
+extern struct notifier_block *powerpc_die_chain;
 /* Grossly misnamed. */
 enum die_val {
@@ -30,14 +30,13 @@ enum die_val {
        DIE_DABR_MATCH,
        DIE_BPT,
        DIE_SSTEP,
-        DIE_GPF,
        DIE_PAGE_FAULT,
 };
 static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig)
 {
        struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig };
-        return notifier_call_chain(&ppc64_die_chain, val, &args);
+        return notifier_call_chain(&powerpc_die_chain, val, &args);
 }
-#endif
+#endif /* _ASM_POWERPC_KDEBUG_H */
diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h
new file mode 100644
index 000000000000..062ab9ba68eb
--- /dev/null
+++ b/include/asm-powerpc/kexec.h
@@ -0,0 +1,49 @@
+#ifndef _ASM_POWERPC_KEXEC_H
+#define _ASM_POWERPC_KEXEC_H
+/*
+ * Maximum page that is mapped directly into kernel memory.
+ * XXX: Since we copy virt we can use any page we allocate
+ */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/*
+ * Maximum address we can reach in physical address mode.
+ * XXX: I want to allow initrd in highmem. Otherwise set to rmo on LPAR.
+ */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#ifdef __powerpc64__
+#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
+#else
+/* TASK_SIZE, probably left over from use_mm ?? */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+#endif
+#define KEXEC_CONTROL_CODE_SIZE 4096
+/* The native architecture */
+#ifdef __powerpc64__
+#define KEXEC_ARCH KEXEC_ARCH_PPC64
+#else
+#define KEXEC_ARCH KEXEC_ARCH_PPC
+#endif
+#ifndef __ASSEMBLY__
+#define MAX_NOTE_BYTES 1024
+typedef u32 note_buf_t[MAX_NOTE_BYTES / sizeof(u32)];
+extern note_buf_t crash_notes[];
+#ifdef __powerpc64__
+extern void kexec_smp_wait(void);       /* get and clear naca physid, wait for
+                                          master to copy new code to 0 */
+#else
+struct kimage;
+extern void machine_kexec_simple(struct kimage *image);
+#endif
+#endif /* ! __ASSEMBLY__ */
+#endif /* _ASM_POWERPC_KEXEC_H */
diff --git a/include/asm-ppc/keylargo.h b/include/asm-powerpc/keylargo.h
index a669a3f0f5a2..a669a3f0f5a2 100644
--- a/include/asm-ppc/keylargo.h
+++ b/include/asm-powerpc/keylargo.h
diff --git a/include/asm-powerpc/kmap_types.h b/include/asm-powerpc/kmap_types.h
new file mode 100644
index 000000000000..b6bac6f61c16
--- /dev/null
+++ b/include/asm-powerpc/kmap_types.h
@@ -0,0 +1,33 @@
+#ifndef _ASM_POWERPC_KMAP_TYPES_H
+#define _ASM_POWERPC_KMAP_TYPES_H
+#ifdef __KERNEL__
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+enum km_type {
+        KM_BOUNCE_READ,
+        KM_SKB_SUNRPC_DATA,
+        KM_SKB_DATA_SOFTIRQ,
+        KM_USER0,
+        KM_USER1,
+        KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
+        KM_IRQ0,
+        KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
+        KM_PPC_SYNC_PAGE,
+        KM_PPC_SYNC_ICACHE,
+        KM_TYPE_NR
+};
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/include/asm-ppc64/kprobes.h b/include/asm-powerpc/kprobes.h
index d9129d2b038e..b2f09f17fbe0 100644
--- a/include/asm-ppc64/kprobes.h
+++ b/include/asm-powerpc/kprobes.h
@@ -1,8 +1,7 @@
-#ifndef _ASM_KPROBES_H
+#ifndef _ASM_POWERPC_KPROBES_H
-#define _ASM_KPROBES_H
+#define _ASM_POWERPC_KPROBES_H
 /*
 *  Kernel Probes (KProbes)
- *  include/asm-ppc64/kprobes.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -64,4 +63,4 @@ static inline int kprobe_exceptions_notify(struct notifier_block *self,
        return 0;
 }
 #endif
-#endif                          /* _ASM_KPROBES_H */
+#endif  /* _ASM_POWERPC_KPROBES_H */
diff --git a/include/asm-ppc64/lmb.h b/include/asm-powerpc/lmb.h
index de91e034bd98..ea0afe343545 100644
--- a/include/asm-ppc64/lmb.h
+++ b/include/asm-powerpc/lmb.h
@@ -50,7 +50,7 @@ extern unsigned long __init lmb_alloc_base(unsigned long, unsigned long,
 extern unsigned long __init lmb_phys_mem_size(void);
 extern unsigned long __init lmb_end_of_DRAM(void);
 extern unsigned long __init lmb_abs_to_phys(unsigned long);
-extern void __init lmb_enforce_memory_limit(void);
+extern void __init lmb_enforce_memory_limit(unsigned long);
 extern void lmb_dump_all(void);
diff --git a/include/asm-ppc64/machdep.h b/include/asm-powerpc/machdep.h
index 8027160ec96d..629ca964b974 100644
--- a/include/asm-ppc64/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -1,6 +1,6 @@
+#ifndef _ASM_POWERPC_MACHDEP_H
+#define _ASM_POWERPC_MACHDEP_H
 #ifdef __KERNEL__
-#ifndef _PPC64_MACHDEP_H
-#define _PPC64_MACHDEP_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -16,6 +16,11 @@
 #include <asm/setup.h>
+/* We export this macro for external modules like Alsa to know if
+ * ppc_md.feature_call is implemented or not
+ */
+#define CONFIG_PPC_HAS_FEATURE_CALLS
 struct pt_regs;
 struct pci_bus; 
 struct device_node;
@@ -39,6 +44,7 @@ struct smp_ops_t {
 #endif
 struct machdep_calls {
+#ifdef CONFIG_PPC64
        void            (*hpte_invalidate)(unsigned long slot,
                                           unsigned long va,
                                           int large,
@@ -56,9 +62,8 @@ struct machdep_calls {
                                       unsigned long vflags,
                                       unsigned long rflags);
        long            (*hpte_remove)(unsigned long hpte_group);
-        void            (*flush_hash_range)(unsigned long context,
+        void            (*flush_hash_range)(unsigned long number, int local);
-                                            unsigned long number,
-                                            int local);
        /* special for kexec, to be called in real mode, linar mapping is
         * destroyed as well */
        void            (*hpte_clear_all)(void);
@@ -75,18 +80,22 @@ struct machdep_calls {
        void            (*iommu_dev_setup)(struct pci_dev *dev);
        void            (*iommu_bus_setup)(struct pci_bus *bus);
        void            (*irq_bus_setup)(struct pci_bus *bus);
+        int             (*set_dabr)(unsigned long dabr);
+#endif
        int             (*probe)(int platform);
        void            (*setup_arch)(void);
        void            (*init_early)(void);
        /* Optional, may be NULL. */
-        void            (*get_cpuinfo)(struct seq_file *m);
+        void            (*show_cpuinfo)(struct seq_file *m);
+        void            (*show_percpuinfo)(struct seq_file *m, int i);
        void            (*init_IRQ)(void);
        int             (*get_irq)(struct pt_regs *);
        void            (*cpu_irq_down)(int secondary);
        /* PCI stuff */
+        /* Called after scanning the bus, before allocating resources */
        void            (*pcibios_fixup)(void);
        int             (*pci_probe_mode)(struct pci_bus *);
@@ -96,9 +105,13 @@ struct machdep_calls {
        void            (*panic)(char *str);
        void            (*cpu_die)(void);
+        long            (*time_init)(void); /* Optional, may be NULL */
        int             (*set_rtc_time)(struct rtc_time *);
        void            (*get_rtc_time)(struct rtc_time *);
-        void            (*get_boot_time)(struct rtc_time *);
+        unsigned long   (*get_boot_time)(void);
+        unsigned char   (*rtc_read_val)(int addr);
+        void            (*rtc_write_val)(int addr, unsigned char val);
        void            (*calibrate_decr)(void);
@@ -107,10 +120,12 @@ struct machdep_calls {
        /* Interface for platform error logging */
        void            (*log_error)(char *buf, unsigned int err_type, int fatal);
+        unsigned char   (*nvram_read_val)(int addr);
+        void            (*nvram_write_val)(int addr, unsigned char val);
        ssize_t         (*nvram_write)(char *buf, size_t count, loff_t *index);
        ssize_t         (*nvram_read)(char *buf, size_t count, loff_t *index);  
        ssize_t         (*nvram_size)(void);            
-        int             (*nvram_sync)(void);
+        void            (*nvram_sync)(void);
        /* Exception handlers */
        void            (*system_reset_exception)(struct pt_regs *regs);
@@ -130,19 +145,97 @@ struct machdep_calls {
        
        /* Get access protection for /dev/mem */
        pgprot_t        (*phys_mem_access_prot)(struct file *file,
-                                                unsigned long offset,
+                                                unsigned long pfn,
                                                unsigned long size,
                                                pgprot_t vma_prot);
        /* Idle loop for this platform, leave empty for default idle loop */
-        int             (*idle_loop)(void);
+        void            (*idle_loop)(void);
-        /* Function to enable pmcs for this platform, called once per cpu. */
+        /* Function to enable performance monitor counters for this
+           platform, called once per cpu. */
        void            (*enable_pmcs)(void);
+#ifdef CONFIG_PPC32     /* XXX for now */
+        /* A general init function, called by ppc_init in init/main.c.
+           May be NULL. */
+        void            (*init)(void);
+        void            (*idle)(void);
+        void            (*power_save)(void);
+        void            (*heartbeat)(void);
+        unsigned long   heartbeat_reset;
+        unsigned long   heartbeat_count;
+        void            (*setup_io_mappings)(void);
+        void            (*early_serial_map)(void);
+        void            (*kgdb_map_scc)(void);
+        /*
+         * optional PCI "hooks"
+         */
+        /* Called after PPC generic resource fixup to perform
+           machine specific fixups */
+        void (*pcibios_fixup_resources)(struct pci_dev *);
+        /* Called for each PCI bus in the system when it's probed */
+        void (*pcibios_fixup_bus)(struct pci_bus *);
+        /* Called when pci_enable_device() is called (initial=0) or
+         * when a device with no assigned resource is found (initial=1).
+         * Returns 0 to allow assignment/enabling of the device. */
+        int  (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
+        /* For interrupt routing */
+        unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
+        int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
+        /* Called in indirect_* to avoid touching devices */
+        int (*pci_exclude_device)(unsigned char, unsigned char);
+        /* Called at then very end of pcibios_init() */
+        void (*pcibios_after_init)(void);
+        /* this is for modules, since _machine can be a define -- Cort */
+        int ppc_machine;
+#ifdef CONFIG_KEXEC
+        /* Called to shutdown machine specific hardware not already controlled
+         * by other drivers.
+         * XXX Should we move this one out of kexec scope?
+         */
+        void (*machine_shutdown)(void);
+        /* Called to do the minimal shutdown needed to run a kexec'd kernel
+         * to run successfully.
+         * XXX Should we move this one out of kexec scope?
+         */
+        void (*machine_crash_shutdown)(void);
+        /* Called to do what every setup is needed on image and the
+         * reboot code buffer. Returns 0 on success.
+         * Provide your own (maybe dummy) implementation if your platform
+         * claims to support kexec.
+         */
+        int (*machine_kexec_prepare)(struct kimage *image);
+        /* Called to handle any machine specific cleanup on image */
+        void (*machine_kexec_cleanup)(struct kimage *image);
+        /* Called to perform the _real_ kexec.
+         * Do NOT allocate memory or fail here. We are past the point of
+         * no return.
+         */
+        void (*machine_kexec)(struct kimage *image);
+#endif /* CONFIG_KEXEC */
+#endif /* CONFIG_PPC32 */
 };
-extern int default_idle(void);
+extern void default_idle(void);
-extern int native_idle(void);
+extern void native_idle(void);
 extern struct machdep_calls ppc_md;
 extern char cmd_line[COMMAND_LINE_SIZE];
@@ -162,6 +255,13 @@ extern sys_ctrler_t sys_ctrler;
 #endif /* CONFIG_PPC_PMAC */
+extern void setup_pci_ptrs(void);
+#ifdef CONFIG_SMP
+/* Poor default implementations */
+extern void __devinit smp_generic_give_timebase(void);
+extern void __devinit smp_generic_take_timebase(void);
+#endif /* CONFIG_SMP */
 /* Functions to produce codes on the leds.
@@ -181,5 +281,5 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal)
                ppc_md.log_error(buf, err_type, fatal);
 }
-#endif /* _PPC64_MACHDEP_H */
 #endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/include/asm-ppc/macio.h b/include/asm-powerpc/macio.h
index b553dd4b139e..b553dd4b139e 100644
--- a/include/asm-ppc/macio.h
+++ b/include/asm-powerpc/macio.h
diff --git a/include/asm-ppc/mediabay.h b/include/asm-powerpc/mediabay.h
index 9daa3252d7b6..9daa3252d7b6 100644
--- a/include/asm-ppc/mediabay.h
+++ b/include/asm-powerpc/mediabay.h
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
new file mode 100644
index 000000000000..7083d1f74260
--- /dev/null
+++ b/include/asm-powerpc/mpic.h
@@ -0,0 +1,287 @@
+#ifndef _ASM_POWERPC_MPIC_H
+#define _ASM_POWERPC_MPIC_H
+#include <linux/irq.h>
+/*
+ * Global registers
+ */
+#define MPIC_GREG_BASE                  0x01000
+#define MPIC_GREG_FEATURE_0             0x00000
+#define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
+#define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
+#define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
+#define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
+#define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
+#define MPIC_GREG_FEATURE_1             0x00010
+#define MPIC_GREG_GLOBAL_CONF_0         0x00020
+#define         MPIC_GREG_GCONF_RESET                   0x80000000
+#define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
+#define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
+#define MPIC_GREG_GLOBAL_CONF_1         0x00030
+#define MPIC_GREG_VENDOR_0              0x00040
+#define MPIC_GREG_VENDOR_1              0x00050
+#define MPIC_GREG_VENDOR_2              0x00060
+#define MPIC_GREG_VENDOR_3              0x00070
+#define MPIC_GREG_VENDOR_ID             0x00080
+#define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
+#define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
+#define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
+#define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
+#define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
+#define MPIC_GREG_PROCESSOR_INIT        0x00090
+#define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
+#define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
+#define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
+#define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
+#define MPIC_GREG_SPURIOUS              0x000e0
+#define MPIC_GREG_TIMER_FREQ            0x000f0
+/*
+ *
+ * Timer registers
+ */
+#define MPIC_TIMER_BASE                 0x01100
+#define MPIC_TIMER_STRIDE               0x40
+#define MPIC_TIMER_CURRENT_CNT          0x00000
+#define MPIC_TIMER_BASE_CNT             0x00010
+#define MPIC_TIMER_VECTOR_PRI           0x00020
+#define MPIC_TIMER_DESTINATION          0x00030
+/*
+ * Per-Processor registers
+ */
+#define MPIC_CPU_THISBASE               0x00000
+#define MPIC_CPU_BASE                   0x20000
+#define MPIC_CPU_STRIDE                 0x01000
+#define MPIC_CPU_IPI_DISPATCH_0         0x00040
+#define MPIC_CPU_IPI_DISPATCH_1         0x00050
+#define MPIC_CPU_IPI_DISPATCH_2         0x00060
+#define MPIC_CPU_IPI_DISPATCH_3         0x00070
+#define MPIC_CPU_CURRENT_TASK_PRI       0x00080
+#define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
+#define MPIC_CPU_WHOAMI                 0x00090
+#define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
+#define MPIC_CPU_INTACK                 0x000a0
+#define MPIC_CPU_EOI                    0x000b0
+/*
+ * Per-source registers
+ */
+#define MPIC_IRQ_BASE                   0x10000
+#define MPIC_IRQ_STRIDE                 0x00020
+#define MPIC_IRQ_VECTOR_PRI             0x00000
+#define         MPIC_VECPRI_MASK                        0x80000000
+#define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
+#define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
+#define         MPIC_VECPRI_PRIORITY_SHIFT              16
+#define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
+#define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
+#define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
+#define         MPIC_VECPRI_POLARITY_MASK               0x00800000
+#define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
+#define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
+#define         MPIC_VECPRI_SENSE_MASK                  0x00400000
+#define MPIC_IRQ_DESTINATION            0x00010
+#define MPIC_MAX_IRQ_SOURCES    2048
+#define MPIC_MAX_CPUS           32
+#define MPIC_MAX_ISU            32
+/*
+ * Special vector numbers (internal use only)
+ */
+#define MPIC_VEC_SPURRIOUS      255
+#define MPIC_VEC_IPI_3          254
+#define MPIC_VEC_IPI_2          253
+#define MPIC_VEC_IPI_1          252
+#define MPIC_VEC_IPI_0          251
+/* unused */
+#define MPIC_VEC_TIMER_3        250
+#define MPIC_VEC_TIMER_2        249
+#define MPIC_VEC_TIMER_1        248
+#define MPIC_VEC_TIMER_0        247
+/* Type definition of the cascade handler */
+typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
+#ifdef CONFIG_MPIC_BROKEN_U3
+/* Fixup table entry */
+struct mpic_irq_fixup
+{
+        u8 __iomem      *base;
+        unsigned int   irq;
+};
+#endif /* CONFIG_MPIC_BROKEN_U3 */
+/* The instance data of a given MPIC */
+struct mpic
+{
+        /* The "linux" controller struct */
+        hw_irq_controller       hc_irq;
+#ifdef CONFIG_SMP
+        hw_irq_controller       hc_ipi;
+#endif
+        const char              *name;
+        /* Flags */
+        unsigned int            flags;
+        /* How many irq sources in a given ISU */
+        unsigned int            isu_size;
+        unsigned int            isu_shift;
+        unsigned int            isu_mask;
+        /* Offset of irq vector numbers */
+        unsigned int            irq_offset;     
+        unsigned int            irq_count;
+        /* Offset of ipi vector numbers */
+        unsigned int            ipi_offset;
+        /* Number of sources */
+        unsigned int            num_sources;
+        /* Number of CPUs */
+        unsigned int            num_cpus;
+        /* cascade handler */
+        mpic_cascade_t          cascade;
+        void                    *cascade_data;
+        unsigned int            cascade_vec;
+        /* senses array */
+        unsigned char           *senses;
+        unsigned int            senses_count;
+#ifdef CONFIG_MPIC_BROKEN_U3
+        /* The fixup table */
+        struct mpic_irq_fixup   *fixups;
+        spinlock_t              fixup_lock;
+#endif
+        /* The various ioremap'ed bases */
+        volatile u32 __iomem    *gregs;
+        volatile u32 __iomem    *tmregs;
+        volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
+        volatile u32 __iomem    *isus[MPIC_MAX_ISU];
+        /* link */
+        struct mpic             *next;
+};
+/* This is the primary controller, only that one has IPIs and
+ * has afinity control. A non-primary MPIC always uses CPU0
+ * registers only
+ */
+#define MPIC_PRIMARY                    0x00000001
+/* Set this for a big-endian MPIC */
+#define MPIC_BIG_ENDIAN                 0x00000002
+/* Broken U3 MPIC */
+#define MPIC_BROKEN_U3                  0x00000004
+/* Broken IPI registers (autodetected) */
+#define MPIC_BROKEN_IPI                 0x00000008
+/* MPIC wants a reset */
+#define MPIC_WANTS_RESET                0x00000010
+/* Allocate the controller structure and setup the linux irq descs
+ * for the range if interrupts passed in. No HW initialization is
+ * actually performed.
+ * 
+ * @phys_addr:  physial base address of the MPIC
+ * @flags:      flags, see constants above
+ * @isu_size:   number of interrupts in an ISU. Use 0 to use a
+ *              standard ISU-less setup (aka powermac)
+ * @irq_offset: first irq number to assign to this mpic
+ * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
+ *              to match the number of sources
+ * @ipi_offset: first irq number to assign to this mpic IPI sources,
+ *              used only on primary mpic
+ * @senses:     array of sense values
+ * @senses_num: number of entries in the array
+ *
+ * Note about the sense array. If none is passed, all interrupts are
+ * setup to be level negative unless MPIC_BROKEN_U3 is set in which
+ * case they are edge positive (and the array is ignored anyway).
+ * The values in the array start at the first source of the MPIC,
+ * that is senses[0] correspond to linux irq "irq_offset".
+ */
+extern struct mpic *mpic_alloc(unsigned long phys_addr,
+                               unsigned int flags,
+                               unsigned int isu_size,
+                               unsigned int irq_offset,
+                               unsigned int irq_count,
+                               unsigned int ipi_offset,
+                               unsigned char *senses,
+                               unsigned int senses_num,
+                               const char *name);
+/* Assign ISUs, to call before mpic_init()
+ *
+ * @mpic:       controller structure as returned by mpic_alloc()
+ * @isu_num:    ISU number
+ * @phys_addr:  physical address of the ISU
+ */
+extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
+                            unsigned long phys_addr);
+/* Initialize the controller. After this has been called, none of the above
+ * should be called again for this mpic
+ */
+extern void mpic_init(struct mpic *mpic);
+/* Setup a cascade. Currently, only one cascade is supported this
+ * way, though you can always do a normal request_irq() and add
+ * other cascades this way. You should call this _after_ having
+ * added all the ISUs
+ *
+ * @irq_no:     "linux" irq number of the cascade (that is offset'ed vector)
+ * @handler:    cascade handler function
+ */
+extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
+                               void *data);
+/*
+ * All of the following functions must only be used after the
+ * ISUs have been assigned and the controller fully initialized
+ * with mpic_init()
+ */
+/* Change/Read the priority of an interrupt. Default is 8 for irqs and
+ * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
+ * IPI number is then the offset'ed (linux irq number mapped to the IPI)
+ */
+extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
+extern unsigned int mpic_irq_get_priority(unsigned int irq);
+/* Setup a non-boot CPU */
+extern void mpic_setup_this_cpu(void);
+/* Clean up for kexec (or cpu offline or ...) */
+extern void mpic_teardown_this_cpu(int secondary);
+/* Get the current cpu priority for this cpu (0..15) */
+extern int mpic_cpu_get_priority(void);
+/* Set the current cpu priority for this cpu */
+extern void mpic_cpu_set_priority(int prio);
+/* Request IPIs on primary mpic */
+extern void mpic_request_ipis(void);
+/* Send an IPI (non offseted number 0..3) */
+extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
+/* Send a message (IPI) to a given target (cpu number or MSG_*) */
+void smp_mpic_message_pass(int target, int msg);
+/* Fetch interrupt from a given mpic */
+extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
+/* This one gets to the primary mpic */
+extern int mpic_get_irq(struct pt_regs *regs);
+/* global mpic for pSeries */
+extern struct mpic *pSeries_mpic;
+#endif  /* _ASM_POWERPC_MPIC_H */
diff --git a/include/asm-powerpc/numnodes.h b/include/asm-powerpc/numnodes.h
new file mode 100644
index 000000000000..795533aca095
--- /dev/null
+++ b/include/asm-powerpc/numnodes.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_POWERPC_MAX_NUMNODES_H
+#define _ASM_POWERPC_MAX_NUMNODES_H
+/* Max 16 Nodes */
+#define NODES_SHIFT     4
+#endif /* _ASM_POWERPC_MAX_NUMNODES_H */
diff --git a/include/asm-ppc/of_device.h b/include/asm-powerpc/of_device.h
index 575bce418f80..ddb16aae0bd6 100644
--- a/include/asm-ppc/of_device.h
+++ b/include/asm-powerpc/of_device.h
@@ -1,5 +1,5 @@
-#ifndef __OF_DEVICE_H__
+#ifndef _ASM_POWERPC_OF_DEVICE_H
-#define __OF_DEVICE_H__
+#define _ASM_POWERPC_OF_DEVICE_H
 #include <linux/device.h>
 #include <linux/mod_devicetable.h>
@@ -61,5 +61,4 @@ extern struct of_device *of_platform_device_create(struct device_node *np,
                                                   struct device *parent);
 extern void of_release_dev(struct device *dev);
-#endif /* __OF_DEVICE_H__ */
+#endif /* _ASM_POWERPC_OF_DEVICE_H */
diff --git a/include/asm-ppc/ohare.h b/include/asm-powerpc/ohare.h
index 023b59772231..023b59772231 100644
--- a/include/asm-ppc/ohare.h
+++ b/include/asm-powerpc/ohare.h
diff --git a/include/asm-ppc64/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h
index b04f1dfb1421..8013cd273ced 100644
--- a/include/asm-ppc64/oprofile_impl.h
+++ b/include/asm-powerpc/oprofile_impl.h
@@ -9,39 +9,49 @@
 * 2 of the License, or (at your option) any later version.
 */
-#ifndef OP_IMPL_H
+#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
-#define OP_IMPL_H 1
+#define _ASM_POWERPC_OPROFILE_IMPL_H
 #define OP_MAX_COUNTER 8
 /* Per-counter configuration as set via oprofilefs.  */
 struct op_counter_config {
+#ifdef __powerpc64__
        unsigned long valid;
+#endif
        unsigned long enabled;
        unsigned long event;
        unsigned long count;
        unsigned long kernel;
+#ifdef __powerpc64__
        /* We dont support per counter user/kernel selection */
+#endif
        unsigned long user;
        unsigned long unit_mask;
 };
 /* System-wide configuration as set via oprofilefs.  */
 struct op_system_config {
+#ifdef __powerpc64__
        unsigned long mmcr0;
        unsigned long mmcr1;
        unsigned long mmcra;
+#endif
        unsigned long enable_kernel;
        unsigned long enable_user;
+#ifdef __powerpc64__
        unsigned long backtrace_spinlocks;
+#endif
 };
 /* Per-arch configuration */
-struct op_ppc64_model {
+struct op_powerpc_model {
        void (*reg_setup) (struct op_counter_config *,
                           struct op_system_config *,
                           int num_counters);
+#ifdef __powerpc64__
        void (*cpu_setup) (void *);
+#endif
        void (*start) (struct op_counter_config *);
        void (*stop) (void);
        void (*handle_interrupt) (struct pt_regs *,
@@ -49,8 +59,9 @@ struct op_ppc64_model {
        int num_counters;
 };
-extern struct op_ppc64_model op_model_rs64;
+#ifdef __powerpc64__
-extern struct op_ppc64_model op_model_power4;
+extern struct op_powerpc_model op_model_rs64;
+extern struct op_powerpc_model op_model_power4;
 static inline unsigned int ctr_read(unsigned int i)
 {
@@ -107,5 +118,6 @@ static inline void ctr_write(unsigned int i, unsigned int val)
                break;
        }
 }
+#endif /* __powerpc64__ */
-#endif
+#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
diff --git a/include/asm-ppc64/pSeries_reconfig.h b/include/asm-powerpc/pSeries_reconfig.h
index c0db1ea7f7d1..c0db1ea7f7d1 100644
--- a/include/asm-ppc64/pSeries_reconfig.h
+++ b/include/asm-powerpc/pSeries_reconfig.h
diff --git a/include/asm-ppc64/parport.h b/include/asm-powerpc/parport.h
index 2f8874c581cc..d86b410a6f8b 100644
--- a/include/asm-ppc64/parport.h
+++ b/include/asm-powerpc/parport.h
@@ -6,8 +6,8 @@
 * This file should only be included by drivers/parport/parport_pc.c.
 */
-#ifndef _ASM_PPC64_PARPORT_H
+#ifndef _ASM_POWERPC_PARPORT_H
-#define _ASM_PPC64_PARPORT_H
+#define _ASM_POWERPC_PARPORT_H
 static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
 static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
@@ -15,4 +15,4 @@ static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
        return parport_pc_find_isa_ports (autoirq, autodma);
 }
-#endif /* !(_ASM_PPC_PARPORT_H) */
+#endif /* !(_ASM_POWERPC_PARPORT_H) */
diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h
index e9683bcff19b..e9683bcff19b 100644
--- a/include/asm-ppc/pmac_feature.h
+++ b/include/asm-powerpc/pmac_feature.h
diff --git a/include/asm-ppc/pmac_low_i2c.h b/include/asm-powerpc/pmac_low_i2c.h
index 809a5963d5e7..809a5963d5e7 100644
--- a/include/asm-ppc/pmac_low_i2c.h
+++ b/include/asm-powerpc/pmac_low_i2c.h
diff --git a/include/asm-powerpc/pmc.h b/include/asm-powerpc/pmc.h
new file mode 100644
index 000000000000..2f3c3fc2b796
--- /dev/null
+++ b/include/asm-powerpc/pmc.h
@@ -0,0 +1,46 @@
+/*
+ * pmc.h
+ * Copyright (C) 2004  David Gibson, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _POWERPC_PMC_H
+#define _POWERPC_PMC_H
+#include <asm/ptrace.h>
+typedef void (*perf_irq_t)(struct pt_regs *);
+int reserve_pmc_hardware(perf_irq_t new_perf_irq);
+void release_pmc_hardware(void);
+#ifdef CONFIG_PPC64
+void power4_enable_pmcs(void);
+#endif
+#ifdef CONFIG_FSL_BOOKE
+void init_pmc_stop(int ctr);
+void set_pmc_event(int ctr, int event);
+void set_pmc_user_kernel(int ctr, int user, int kernel);
+void set_pmc_marked(int ctr, int mark0, int mark1);
+void pmc_start_ctr(int ctr, int enable);
+void pmc_start_ctrs(int enable);
+void pmc_stop_ctrs(void);
+void dump_pmcs(void);
+extern struct op_powerpc_model op_model_fsl_booke;
+#endif
+#endif /* _POWERPC_PMC_H */
diff --git a/include/asm-ppc64/posix_types.h b/include/asm-powerpc/posix_types.h
index 516de7201b5d..c6391077224f 100644
--- a/include/asm-ppc64/posix_types.h
+++ b/include/asm-powerpc/posix_types.h
@@ -1,44 +1,54 @@
-#ifndef _PPC64_POSIX_TYPES_H
+#ifndef _ASM_POWERPC_POSIX_TYPES_H
-#define _PPC64_POSIX_TYPES_H
+#define _ASM_POWERPC_POSIX_TYPES_H
 /*
 * This file is generally used by user-level software, so you need to
 * be a little careful about namespace pollution etc.  Also, we cannot
 * assume GCC is being used.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
 */
 typedef unsigned long   __kernel_ino_t;
-typedef unsigned long   __kernel_nlink_t;
 typedef unsigned int    __kernel_mode_t;
 typedef long            __kernel_off_t;
-typedef long long       __kernel_loff_t;
 typedef int             __kernel_pid_t;
-typedef int             __kernel_ipc_pid_t;
 typedef unsigned int    __kernel_uid_t;
 typedef unsigned int    __kernel_gid_t;
-typedef unsigned long   __kernel_size_t;
-typedef long            __kernel_ssize_t;
 typedef long            __kernel_ptrdiff_t;
 typedef long            __kernel_time_t;
+typedef long            __kernel_clock_t;
 typedef int             __kernel_timer_t;
 typedef int             __kernel_clockid_t;
 typedef long            __kernel_suseconds_t;
-typedef long            __kernel_clock_t;
 typedef int             __kernel_daddr_t;
 typedef char *          __kernel_caddr_t;
 typedef unsigned short  __kernel_uid16_t;
 typedef unsigned short  __kernel_gid16_t;
 typedef unsigned int    __kernel_uid32_t;
 typedef unsigned int    __kernel_gid32_t;
 typedef unsigned int    __kernel_old_uid_t;
 typedef unsigned int    __kernel_old_gid_t;
+#ifdef __powerpc64__
+typedef unsigned long   __kernel_nlink_t;
+typedef int             __kernel_ipc_pid_t;
+typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_ssize_t;
 typedef unsigned long   __kernel_old_dev_t;
+#else
+typedef unsigned short  __kernel_nlink_t;
+typedef short           __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef unsigned int    __kernel_old_dev_t;
+#endif
+#ifdef __powerpc64__
+typedef long long       __kernel_loff_t;
+#else
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+#endif
 typedef struct {
        int     val[2];
@@ -116,4 +126,4 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *p)
 #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
 #endif /* __GNUC__ */
-#endif /* _PPC64_POSIX_TYPES_H */
+#endif /* _ASM_POWERPC_POSIX_TYPES_H */
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
new file mode 100644
index 000000000000..a88728fba8f6
--- /dev/null
+++ b/include/asm-powerpc/ppc-pci.h
@@ -0,0 +1,54 @@
+/*
+ * c 2001 PPC 64 Team, IBM Corp
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_PPC_PCI_H
+#define _ASM_POWERPC_PPC_PCI_H
+#include <linux/pci.h>
+#include <asm/pci-bridge.h>
+extern unsigned long isa_io_base;
+extern void pci_setup_pci_controller(struct pci_controller *hose);
+extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
+extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
+extern struct list_head hose_list;
+extern int global_phb_number;
+extern unsigned long find_and_init_phbs(void);
+extern struct pci_dev *ppc64_isabridge_dev;     /* may be NULL if no ISA bus */
+/* PCI device_node operations */
+struct device_node;
+typedef void *(*traverse_func)(struct device_node *me, void *data);
+void *traverse_pci_devices(struct device_node *start, traverse_func pre,
+                void *data);
+void pci_devs_phb_init(void);
+void pci_devs_phb_init_dynamic(struct pci_controller *phb);
+/* PCI address cache management routines */
+void pci_addr_cache_insert_device(struct pci_dev *dev);
+void pci_addr_cache_remove_device(struct pci_dev *dev);
+/* From rtas_pci.h */
+void init_pci_config_tokens (void);
+unsigned long get_phb_buid (struct device_node *);
+/* From pSeries_pci.h */
+extern void pSeries_final_fixup(void);
+extern void pSeries_irq_bus_setup(struct pci_bus *bus);
+extern unsigned long pci_probe_only;
+extern unsigned long pci_assign_all_buses;
+extern int pci_read_irq_line(struct pci_dev *pci_dev);
+#endif /* _ASM_POWERPC_PPC_PCI_H */
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
index bb53e2def363..c534ca41224b 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-powerpc/ppc_asm.h
@@ -1,38 +1,42 @@
 /*
- * include/asm-ppc/ppc_asm.h
- *
- * Definitions used by various bits of low-level assembly code on PowerPC.
- *
 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
 */
+#ifndef _ASM_POWERPC_PPC_ASM_H
+#define _ASM_POWERPC_PPC_ASM_H
+#include <linux/stringify.h>
 #include <linux/config.h>
+#ifdef __ASSEMBLY__
 /*
 * Macros for storing registers into and loading registers from
 * exception frames.
 */
+#ifdef __powerpc64__
+#define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
+#define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
+#define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
+#else
 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
+#define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
+#define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
+                                SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
+                                REST_10GPRS(22, base)
+#endif
 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
-#define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
-                                SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
-                                REST_10GPRS(22, base)
 #define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
@@ -47,32 +51,170 @@
 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
 #define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
-#define SAVE_2VR(n,b,base)      SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
+#define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
-#define SAVE_4VR(n,b,base)      SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
+#define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
-#define SAVE_8VR(n,b,base)      SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
+#define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
-#define SAVE_16VR(n,b,base)     SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
+#define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
-#define SAVE_32VR(n,b,base)     SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
+#define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
 #define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
-#define REST_2VR(n,b,base)      REST_VR(n,b,base); REST_VR(n+1,b,base)
+#define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
-#define REST_4VR(n,b,base)      REST_2VR(n,b,base); REST_2VR(n+2,b,base)
+#define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
-#define REST_8VR(n,b,base)      REST_4VR(n,b,base); REST_4VR(n+4,b,base)
+#define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
-#define REST_16VR(n,b,base)     REST_8VR(n,b,base); REST_8VR(n+8,b,base)
+#define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
-#define REST_32VR(n,b,base)     REST_16VR(n,b,base); REST_16VR(n+16,b,base)
+#define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 #define SAVE_EVR(n,s,base)      evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
-#define SAVE_2EVR(n,s,base)     SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
+#define SAVE_2EVRS(n,s,base)    SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
-#define SAVE_4EVR(n,s,base)     SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)
+#define SAVE_4EVRS(n,s,base)    SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
-#define SAVE_8EVR(n,s,base)     SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)
+#define SAVE_8EVRS(n,s,base)    SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
-#define SAVE_16EVR(n,s,base)    SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)
+#define SAVE_16EVRS(n,s,base)   SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
-#define SAVE_32EVR(n,s,base)    SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)
+#define SAVE_32EVRS(n,s,base)   SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
 #define REST_EVR(n,s,base)      lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
-#define REST_2EVR(n,s,base)     REST_EVR(n,s,base); REST_EVR(n+1,s,base)
+#define REST_2EVRS(n,s,base)    REST_EVR(n,s,base); REST_EVR(n+1,s,base)
-#define REST_4EVR(n,s,base)     REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)
+#define REST_4EVRS(n,s,base)    REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
-#define REST_8EVR(n,s,base)     REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)
+#define REST_8EVRS(n,s,base)    REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
-#define REST_16EVR(n,s,base)    REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)
+#define REST_16EVRS(n,s,base)   REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
-#define REST_32EVR(n,s,base)    REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)
+#define REST_32EVRS(n,s,base)   REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
+/* Macros to adjust thread priority for hardware multithreading */
+#define HMT_VERY_LOW    or      31,31,31        # very low priority
+#define HMT_LOW         or      1,1,1
+#define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
+#define HMT_MEDIUM      or      2,2,2
+#define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
+#define HMT_HIGH        or      3,3,3
+/* handle instructions that older assemblers may not know */
+#define RFCI            .long 0x4c000066        /* rfci instruction */
+#define RFDI            .long 0x4c00004e        /* rfdi instruction */
+#define RFMCI           .long 0x4c00004c        /* rfmci instruction */
+#ifdef CONFIG_PPC64
+#define XGLUE(a,b) a##b
+#define GLUE(a,b) XGLUE(a,b)
+#define _GLOBAL(name) \
+        .section ".text"; \
+        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+#define _KPROBE(name) \
+        .section ".kprobes.text","a"; \
+        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+#define _STATIC(name) \
+        .section ".text"; \
+        .align 2 ; \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+#else /* 32-bit */
+#define _GLOBAL(n)      \
+        .text;          \
+        .stabs __stringify(n:F-1),N_FUN,0,0,n;\
+        .globl n;       \
+n:
+#define _KPROBE(n)      \
+        .section ".kprobes.text","a";   \
+        .globl  n;      \
+n:
+#endif
+/* 
+ * LOADADDR( rn, name )
+ *   loads the address of 'name' into 'rn'
+ *
+ * LOADBASE( rn, name )
+ *   loads the address (possibly without the low 16 bits) of 'name' into 'rn'
+ *   suitable for base+disp addressing
+ */
+#ifdef __powerpc64__
+#define LOADADDR(rn,name) \
+        lis     rn,name##@highest;      \
+        ori     rn,rn,name##@higher;    \
+        rldicr  rn,rn,32,31;            \
+        oris    rn,rn,name##@h;         \
+        ori     rn,rn,name##@l
+#define LOADBASE(rn,name)               \
+        ld      rn,name@got(r2)
+#define OFF(name)       0
+#define SET_REG_TO_CONST(reg, value)                    \
+        lis     reg,(((value)>>48)&0xFFFF);             \
+        ori     reg,reg,(((value)>>32)&0xFFFF);         \
+        rldicr  reg,reg,32,31;                          \
+        oris    reg,reg,(((value)>>16)&0xFFFF);         \
+        ori     reg,reg,((value)&0xFFFF);
+#define SET_REG_TO_LABEL(reg, label)                    \
+        lis     reg,(label)@highest;                    \
+        ori     reg,reg,(label)@higher;                 \
+        rldicr  reg,reg,32,31;                          \
+        oris    reg,reg,(label)@h;                      \
+        ori     reg,reg,(label)@l;
+/* operations for longs and pointers */
+#define LDL     ld
+#define STL     std
+#define CMPI    cmpdi
+#define SZL     8
+/* offsets for stack frame layout */
+#define LRSAVE  16
+#else /* 32-bit */
+#define LOADADDR(rn,name) \
+        lis     rn,name@ha;     \
+        addi    rn,rn,name@l
+#define LOADBASE(rn,name)       \
+        lis     rn,name@ha
+#define OFF(name)       name@l
+/* operations for longs and pointers */
+#define LDL     lwz
+#define STL     stw
+#define CMPI    cmpwi
+#define SZL     4
+/* offsets for stack frame layout */
+#define LRSAVE  4
+#endif
+/* various errata or part fixups */
 #ifdef CONFIG_PPC601_SYNC_FIX
 #define SYNC                            \
 BEGIN_FTR_SECTION                       \
@@ -93,6 +235,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
 #define ISYNC_601
 #endif
 #ifndef CONFIG_SMP
 #define TLBSYNC
 #else /* CONFIG_SMP */
@@ -104,6 +247,7 @@ BEGIN_FTR_SECTION			\
 END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #endif
+        
 /*
 * This instruction is not implemented on the PPC 603 or 601; however, on
 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
@@ -121,18 +265,52 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
        bdnz    0b
 #endif
-#ifdef CONFIG_BOOKE
+#ifdef CONFIG_IBM405_ERR77
+#define PPC405_ERR77(ra,rb)     dcbt    ra, rb;
+#define PPC405_ERR77_SYNC       sync;
+#else
+#define PPC405_ERR77(ra,rb)
+#define PPC405_ERR77_SYNC
+#endif
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+#if defined(CONFIG_BOOKE)
+#define toreal(rd)
+#define fromreal(rd)
 #define tophys(rd,rs)                           \
        addis   rd,rs,0
 #define tovirt(rd,rs)                           \
        addis   rd,rs,0
-#else  /* CONFIG_BOOKE */
+#elif defined(CONFIG_PPC64)
+#define toreal(rd)              /* we can access c000... in real mode */
+#define fromreal(rd)
+#define tophys(rd,rs)                           \
+        clrldi  rd,rs,2
+#define tovirt(rd,rs)                           \
+        rotldi  rd,rs,16;                       \
+        ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
+        rotldi  rd,rd,48
+#else
 /*
 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 * physical base address of RAM at compile time.
 */
+#define toreal(rd)      tophys(rd,rd)
+#define fromreal(rd)    tovirt(rd,rd)
 #define tophys(rd,rs)                           \
 0:      addis   rd,rs,-KERNELBASE@h;            \
        .section ".vtop_fixup","aw";            \
@@ -146,22 +324,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
        .align  1;                              \
        .long   0b;                             \
        .previous
-#endif  /* CONFIG_BOOKE */
+#endif
-/*
+#ifdef CONFIG_PPC64
- * On 64-bit cpus, we use the rfid instruction instead of rfi, but
+#define RFI             rfid
- * we then have to make sure we preserve the top 32 bits except for
+#define MTMSRD(r)       mtmsrd  r
- * the 64-bit mode bit, which we clear.
- */
-#ifdef CONFIG_PPC64BRIDGE
-#define FIX_SRR1(ra, rb)        \
-        mr      rb,ra;          \
-        mfmsr   ra;             \
-        clrldi  ra,ra,1;                /* turn off 64-bit mode */ \
-        rldimi  ra,rb,0,32
-#define RFI             .long   0x4c000024      /* rfid instruction */
-#define MTMSRD(r)       .long   (0x7c000164 + ((r) << 21))      /* mtmsrd */
-#define CLR_TOP32(r)    rlwinm  (r),(r),0,0,31  /* clear top 32 bits */
 #else
 #define FIX_SRR1(ra, rb)
@@ -172,24 +339,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #endif
 #define MTMSRD(r)       mtmsr   r
 #define CLR_TOP32(r)
-#endif /* CONFIG_PPC64BRIDGE */
-#define RFCI            .long 0x4c000066        /* rfci instruction */
-#define RFDI            .long 0x4c00004e        /* rfdi instruction */
-#define RFMCI           .long 0x4c00004c        /* rfmci instruction */
-#ifdef CONFIG_IBM405_ERR77
-#define PPC405_ERR77(ra,rb)     dcbt    ra, rb;
-#define PPC405_ERR77_SYNC       sync;
-#else
-#define PPC405_ERR77(ra,rb)
-#define PPC405_ERR77_SYNC
-#endif
-#ifdef CONFIG_IBM440EP_ERR42
-#define PPC440EP_ERR42 isync
-#else
-#define PPC440EP_ERR42
 #endif
 /* The boring bits... */
@@ -277,6 +426,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define fr30    30
 #define fr31    31
+/* AltiVec Registers (VPRs) */
 #define vr0     0
 #define vr1     1
 #define vr2     2
@@ -310,6 +461,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define vr30    30
 #define vr31    31
+/* SPE Registers (EVPRs) */
 #define evr0    0
 #define evr1    1
 #define evr2    2
@@ -348,3 +501,18 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define N_RSYM  64
 #define N_SLINE 68
 #define N_SO    100
+#define ASM_CONST(x) x
+#else
+  #define __ASM_CONST(x) x##UL
+  #define ASM_CONST(x) __ASM_CONST(x)
+#ifdef CONFIG_PPC64
+#define DATAL   ".llong"
+#else
+#define DATAL   ".long"
+#endif
+#endif /*  __ASSEMBLY__ */
+#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/include/asm-ppc/processor.h b/include/asm-powerpc/processor.h
index b05b5d9cae20..1dc4bf7b52b3 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -1,21 +1,28 @@
-#ifdef __KERNEL__
+#ifndef _ASM_POWERPC_PROCESSOR_H
-#ifndef __ASM_PPC_PROCESSOR_H
+#define _ASM_POWERPC_PROCESSOR_H
-#define __ASM_PPC_PROCESSOR_H
 /*
- * Default implementation of macro that returns current
+ * Copyright (C) 2001 PPC 64 Team, IBM Corp
- * instruction pointer ("program counter").
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
 */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
 #include <linux/config.h>
-#include <linux/stringify.h>
+#include <asm/reg.h>
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
-#include <asm/mpc8xx.h>
+#ifdef CONFIG_PPC64
-#include <asm/reg.h>
+#include <asm/systemcfg.h>
+#endif
+#ifdef CONFIG_PPC32
+/* 32-bit platform types */
 /* We only need to define a new _MACH_xxx for machines which are part of
 * a configuration which supports more than one type of different machine.
 * This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac.
@@ -36,20 +43,6 @@
 #define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
 #define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
-#define _GLOBAL(n)\
-        .stabs __stringify(n:F-1),N_FUN,0,0,n;\
-        .globl n;\
-n:
-/*
- * this is the minimum allowable io space due to the location
- * of the io areas on prep (first one at 0x80000000) but
- * as soon as I get around to remapping the io areas with the BATs
- * to match the mac we can raise this. -- Cort
- */
-#define TASK_SIZE       (CONFIG_TASK_SIZE)
-#ifndef __ASSEMBLY__
 #ifdef CONFIG_PPC_MULTIPLATFORM
 extern int _machine;
@@ -67,17 +60,49 @@ extern unsigned char ucBoardRevMaj, ucBoardRevMin;
 #else
 #define _machine 0
 #endif /* CONFIG_PPC_MULTIPLATFORM */
+#endif /* CONFIG_PPC32 */
+#ifdef CONFIG_PPC64
+/* Platforms supported by PPC64 */
+#define PLATFORM_PSERIES      0x0100
+#define PLATFORM_PSERIES_LPAR 0x0101
+#define PLATFORM_ISERIES_LPAR 0x0201
+#define PLATFORM_LPAR         0x0001
+#define PLATFORM_POWERMAC     0x0400
+#define PLATFORM_MAPLE        0x0500
+#define PLATFORM_CELL         0x1000
+/* Compatibility with drivers coming from PPC32 world */
+#define _machine        (systemcfg->platform)
+#define _MACH_Pmac      PLATFORM_POWERMAC
+#endif
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+/* Macros for adjusting thread priority (hardware multi-threading) */
+#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
+#define HMT_low()        asm volatile("or 1,1,1      # low priority")
+#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
+#define HMT_medium()     asm volatile("or 2,2,2      # medium priority")
+#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
+#define HMT_high()       asm volatile("or 3,3,3      # high priority")
+#ifdef __KERNEL__
+extern int have_of;
 struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
+void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
 void release_thread(struct task_struct *);
 /* Prepare to copy thread state - unlazy all lazy status */
 extern void prepare_to_copy(struct task_struct *tsk);
-/*
+/* Create a new kernel thread. */
- * Create a new kernel thread.
- */
 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 /* Lazy FPU handling on uni-processor */
@@ -85,10 +110,37 @@ extern struct task_struct *last_task_used_math;
 extern struct task_struct *last_task_used_altivec;
 extern struct task_struct *last_task_used_spe;
+#ifdef CONFIG_PPC32
+#define TASK_SIZE       (CONFIG_TASK_SIZE)
 /* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
+#endif
+#ifdef CONFIG_PPC64
+/* 64-bit user address space is 44-bits (16TB user VM) */
+#define TASK_SIZE_USER64 (0x0000100000000000UL)
+/* 
+ * 32-bit user address space is 4GB - 1 page 
+ * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
+ */
+#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
+#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
+                TASK_SIZE_USER32 : TASK_SIZE_USER64)
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
+#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
+#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)) ? \
+                TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
+#endif
 typedef struct {
        unsigned long seg;
@@ -96,18 +148,32 @@ typedef struct {
 struct thread_struct {
        unsigned long   ksp;            /* Kernel stack pointer */
+#ifdef CONFIG_PPC64
+        unsigned long   ksp_vsid;
+#endif
        struct pt_regs  *regs;          /* Pointer to saved register state */
        mm_segment_t    fs;             /* for get_fs() validation */
+#ifdef CONFIG_PPC32
        void            *pgdir;         /* root of page-table tree */
-        int             fpexc_mode;     /* floating-point exception mode */
        signed long     last_syscall;
+#endif
 #if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
        unsigned long   dbcr0;          /* debug control register values */
        unsigned long   dbcr1;
 #endif
        double          fpr[32];        /* Complete floating point set */
-        unsigned long   fpscr_pad;      /* fpr ... fpscr must be contiguous */
+        struct {                        /* fpr ... fpscr must be contiguous */
-        unsigned long   fpscr;          /* Floating point status */
+                unsigned int pad;
+                unsigned int val;       /* Floating point status */
+        } fpscr;
+        int             fpexc_mode;     /* floating-point exception mode */
+#ifdef CONFIG_PPC64
+        unsigned long   start_tb;       /* Start purr when proc switched in */
+        unsigned long   accum_tb;       /* Total accumilated purr for process */
+        unsigned long   vdso_base;      /* base of the vDSO library */
+#endif
+        unsigned long   dabr;           /* Data address breakpoint register */
 #ifdef CONFIG_ALTIVEC
        /* Complete AltiVec register set */
        vector128       vr[32] __attribute((aligned(16)));
@@ -128,51 +194,58 @@ struct thread_struct {
 #define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
+#ifdef CONFIG_PPC32
 #define INIT_THREAD { \
        .ksp = INIT_SP, \
        .fs = KERNEL_DS, \
        .pgdir = swapper_pg_dir, \
        .fpexc_mode = MSR_FE0 | MSR_FE1, \
 }
+#else
+#define INIT_THREAD  { \
+        .ksp = INIT_SP, \
+        .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
+        .fs = KERNEL_DS, \
+        .fpr = {0}, \
+        .fpscr = { .val = 0, }, \
+        .fpexc_mode = MSR_FE0|MSR_FE1, \
+}
+#endif
 /*
 * Return saved PC of a blocked thread. For now, this is the "user" PC
 */
-#define thread_saved_pc(tsk)    \
+#define thread_saved_pc(tsk)    \
-        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
+        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 unsigned long get_wchan(struct task_struct *p);
-#define KSTK_EIP(tsk)   ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
+#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
-#define KSTK_ESP(tsk)   ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
+#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 /* Get/set floating-point exception mode */
-#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
+#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
-#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
+#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
-static inline unsigned int __unpack_fe01(unsigned int msr_bits)
+static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 {
        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 }
-static inline unsigned int __pack_fe01(unsigned int fpmode)
+static inline unsigned long __pack_fe01(unsigned int fpmode)
 {
        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 }
-/* in process.c - for early bootup debug -- Cort */
+#ifdef CONFIG_PPC64
-int ll_printk(const char *, ...);
+#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
-void ll_puts(const char *);
+#else
-/* In misc.c */
-void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac)
 #define cpu_relax()     barrier()
+#endif
 /*
 * Prefetch macros.
@@ -181,21 +254,28 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #define ARCH_HAS_PREFETCHW
 #define ARCH_HAS_SPINLOCK_PREFETCH
-extern inline void prefetch(const void *x)
+static inline void prefetch(const void *x)
 {
-         __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
+        if (unlikely(!x))
+                return;
+        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 }
-extern inline void prefetchw(const void *x)
+static inline void prefetchw(const void *x)
 {
-         __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
+        if (unlikely(!x))
+                return;
+        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 }
 #define spin_lock_prefetch(x)   prefetchw(x)
-extern int emulate_altivec(struct pt_regs *regs);
+#ifdef CONFIG_PPC64
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
-#endif /* !__ASSEMBLY__ */
+#endif
-#endif /* __ASM_PPC_PROCESSOR_H */
 #endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
new file mode 100644
index 000000000000..3a0104fa0462
--- /dev/null
+++ b/include/asm-powerpc/prom.h
@@ -0,0 +1,219 @@
+#ifndef _POWERPC_PROM_H
+#define _POWERPC_PROM_H
+#ifdef __KERNEL__
+/*
+ * Definitions for talking to the Open Firmware PROM on
+ * Power Macintosh computers.
+ *
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <asm/atomic.h>
+/* Definitions used by the flattened device tree */
+#define OF_DT_HEADER            0xd00dfeed      /* marker */
+#define OF_DT_BEGIN_NODE        0x1             /* Start of node, full name */
+#define OF_DT_END_NODE          0x2             /* End node */
+#define OF_DT_PROP              0x3             /* Property: name off, size,
+                                                 * content */
+#define OF_DT_NOP               0x4             /* nop */
+#define OF_DT_END               0x9
+#define OF_DT_VERSION           0x10
+/*
+ * This is what gets passed to the kernel by prom_init or kexec
+ *
+ * The dt struct contains the device tree structure, full pathes and
+ * property contents. The dt strings contain a separate block with just
+ * the strings for the property names, and is fully page aligned and
+ * self contained in a page, so that it can be kept around by the kernel,
+ * each property name appears only once in this page (cheap compression)
+ *
+ * the mem_rsvmap contains a map of reserved ranges of physical memory,
+ * passing it here instead of in the device-tree itself greatly simplifies
+ * the job of everybody. It's just a list of u64 pairs (base/size) that
+ * ends when size is 0
+ */
+struct boot_param_header
+{
+        u32     magic;                  /* magic word OF_DT_HEADER */
+        u32     totalsize;              /* total size of DT block */
+        u32     off_dt_struct;          /* offset to structure */
+        u32     off_dt_strings;         /* offset to strings */
+        u32     off_mem_rsvmap;         /* offset to memory reserve map */
+        u32     version;                /* format version */
+        u32     last_comp_version;      /* last compatible version */
+        /* version 2 fields below */
+        u32     boot_cpuid_phys;        /* Physical CPU id we're booting on */
+        /* version 3 fields below */
+        u32     dt_strings_size;        /* size of the DT strings block */
+};
+typedef u32 phandle;
+typedef u32 ihandle;
+struct address_range {
+        unsigned long space;
+        unsigned long address;
+        unsigned long size;
+};
+struct interrupt_info {
+        int     line;
+        int     sense;          /* +ve/-ve logic, edge or level, etc. */
+};
+struct pci_address {
+        u32 a_hi;
+        u32 a_mid;
+        u32 a_lo;
+};
+struct isa_address {
+        u32 a_hi;
+        u32 a_lo;
+};
+struct isa_range {
+        struct isa_address isa_addr;
+        struct pci_address pci_addr;
+        unsigned int size;
+};
+struct reg_property {
+        unsigned long address;
+        unsigned long size;
+};
+struct reg_property32 {
+        unsigned int address;
+        unsigned int size;
+};
+struct reg_property64 {
+        u64 address;
+        u64 size;
+};
+struct property {
+        char    *name;
+        int     length;
+        unsigned char *value;
+        struct property *next;
+};
+struct device_node {
+        char    *name;
+        char    *type;
+        phandle node;
+        phandle linux_phandle;
+        int     n_addrs;
+        struct  address_range *addrs;
+        int     n_intrs;
+        struct  interrupt_info *intrs;
+        char    *full_name;
+        struct  property *properties;
+        struct  device_node *parent;
+        struct  device_node *child;
+        struct  device_node *sibling;
+        struct  device_node *next;      /* next device of same type */
+        struct  device_node *allnext;   /* next in list of all nodes */
+        struct  proc_dir_entry *pde;    /* this node's proc directory */
+        struct  kref kref;
+        unsigned long _flags;
+        void    *data;
+};
+extern struct device_node *of_chosen;
+/* flag descriptions */
+#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */
+#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
+#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
+#define HAVE_ARCH_DEVTREE_FIXUPS
+static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de)
+{
+        dn->pde = de;
+}
+/* OBSOLETE: Old style node lookup */
+extern struct device_node *find_devices(const char *name);
+extern struct device_node *find_type_devices(const char *type);
+extern struct device_node *find_path_device(const char *path);
+extern struct device_node *find_compatible_devices(const char *type,
+                                                   const char *compat);
+extern struct device_node *find_all_nodes(void);
+/* New style node lookup */
+extern struct device_node *of_find_node_by_name(struct device_node *from,
+        const char *name);
+extern struct device_node *of_find_node_by_type(struct device_node *from,
+        const char *type);
+extern struct device_node *of_find_compatible_node(struct device_node *from,
+        const char *type, const char *compat);
+extern struct device_node *of_find_node_by_path(const char *path);
+extern struct device_node *of_find_node_by_phandle(phandle handle);
+extern struct device_node *of_find_all_nodes(struct device_node *prev);
+extern struct device_node *of_get_parent(const struct device_node *node);
+extern struct device_node *of_get_next_child(const struct device_node *node,
+                                             struct device_node *prev);
+extern struct device_node *of_node_get(struct device_node *node);
+extern void of_node_put(struct device_node *node);
+/* For updating the device tree at runtime */
+extern void of_attach_node(struct device_node *);
+extern void of_detach_node(const struct device_node *);
+/* Other Prototypes */
+extern void finish_device_tree(void);
+extern void unflatten_device_tree(void);
+extern void early_init_devtree(void *);
+extern int device_is_compatible(struct device_node *device, const char *);
+extern int machine_is_compatible(const char *compat);
+extern unsigned char *get_property(struct device_node *node, const char *name,
+                                   int *lenp);
+extern void print_properties(struct device_node *node);
+extern int prom_n_addr_cells(struct device_node* np);
+extern int prom_n_size_cells(struct device_node* np);
+extern int prom_n_intr_cells(struct device_node* np);
+extern void prom_get_irq_senses(unsigned char *senses, int off, int max);
+extern void prom_add_property(struct device_node* np, struct property* prop);
+#ifdef CONFIG_PPC32
+/*
+ * PCI <-> OF matching functions
+ * (XXX should these be here?)
+ */
+struct pci_bus;
+struct pci_dev;
+extern int pci_device_from_OF_node(struct device_node *node,
+                                   u8* bus, u8* devfn);
+extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
+extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
+extern void pci_create_OF_bus_map(void);
+#endif
+extern struct resource *request_OF_resource(struct device_node* node,
+                                int index, const char* name_postfix);
+extern int release_OF_resource(struct device_node* node, int index);
+#endif /* __KERNEL__ */
+#endif /* _POWERPC_PROM_H */
diff --git a/include/asm-ppc64/ptrace.h b/include/asm-powerpc/ptrace.h
index 3a55377f1fd3..1f7ecdb0b6ce 100644
--- a/include/asm-ppc64/ptrace.h
+++ b/include/asm-powerpc/ptrace.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_PTRACE_H
+#ifndef _ASM_POWERPC_PTRACE_H
-#define _PPC64_PTRACE_H
+#define _ASM_POWERPC_PTRACE_H
 /*
 * Copyright (C) 2001 PPC64 Team, IBM Corp
@@ -16,7 +16,7 @@
 * that the overall structure is a multiple of 16 bytes in length.
 *
 * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below.  This simplifies arch/ppc64/kernel/ptrace.c.
+ * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
@@ -30,70 +30,96 @@ struct pt_regs {
        unsigned long gpr[32];
        unsigned long nip;
        unsigned long msr;
-        unsigned long orig_gpr3; /* Used for restarting system calls */
+        unsigned long orig_gpr3;        /* Used for restarting system calls */
        unsigned long ctr;
        unsigned long link;
        unsigned long xer;
        unsigned long ccr;
-        unsigned long softe;    /* Soft enabled/disabled */
+#ifdef __powerpc64__
-        unsigned long trap;     /* Reason for being here */
+        unsigned long softe;            /* Soft enabled/disabled */
-        unsigned long dar;      /* Fault registers */
+#else
-        unsigned long dsisr;
+        unsigned long mq;               /* 601 only (not used at present) */
-        unsigned long result;   /* Result of a system call */
+                                        /* Used on APUS to hold IPL value. */
+#endif
+        unsigned long trap;             /* Reason for being here */
+        /* N.B. for critical exceptions on 4xx, the dar and dsisr
+           fields are overloaded to hold srr0 and srr1. */
+        unsigned long dar;              /* Fault registers */
+        unsigned long dsisr;            /* on 4xx/Book-E used for ESR */
+        unsigned long result;           /* Result of a system call */
 };
-struct pt_regs32 {
+#endif /* __ASSEMBLY__ */
-        unsigned int gpr[32];
-        unsigned int nip;
-        unsigned int msr;
-        unsigned int orig_gpr3; /* Used for restarting system calls */
-        unsigned int ctr;
-        unsigned int link;
-        unsigned int xer;
-        unsigned int ccr;
-        unsigned int mq;        /* 601 only (not used at present) */
-        unsigned int trap;      /* Reason for being here */
-        unsigned int dar;       /* Fault registers */
-        unsigned int dsisr;
-        unsigned int result;    /* Result of a system call */
-};
 #ifdef __KERNEL__
-#define instruction_pointer(regs) ((regs)->nip)
+#ifdef __powerpc64__
+#define STACK_FRAME_OVERHEAD    112     /* size of minimum stack frame */
+/* Size of dummy stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE      128
+#define __SIGNAL_FRAMESIZE32    64
+#else /* __powerpc64__ */
+#define STACK_FRAME_OVERHEAD    16      /* size of minimum stack frame */
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE      64
+#endif /* __powerpc64__ */
+#ifndef __ASSEMBLY__
+#define instruction_pointer(regs) ((regs)->nip)
 #ifdef CONFIG_SMP
 extern unsigned long profile_pc(struct pt_regs *regs);
 #else
 #define profile_pc(regs) instruction_pointer(regs)
 #endif
+#ifdef __powerpc64__
 #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
+#else
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+#endif
 #define force_successful_syscall_return()   \
-                (current_thread_info()->syscall_noerror = 1)
+        do { \
+                current_thread_info()->syscall_noerror = 1; \
+        } while(0)
 /*
 * We use the least-significant bit of the trap field to indicate
 * whether we have saved the full set of registers, or only a
 * partial set.  A 1 there means the partial set.
+ * On 4xx we use the next bit to indicate whether the exception
+ * is a critical exception (1 means it is).
 */
 #define FULL_REGS(regs)         (((regs)->trap & 1) == 0)
+#ifndef __powerpc64__
+#define IS_CRITICAL_EXC(regs)   (((regs)->trap & 2) == 0)
+#endif /* ! __powerpc64__ */
 #define TRAP(regs)              ((regs)->trap & ~0xF)
+#ifdef __powerpc64__
 #define CHECK_FULL_REGS(regs)   BUG_ON(regs->trap & 1)
+#else
-#endif /* __KERNEL__ */
+#define CHECK_FULL_REGS(regs)                                                 \
+do {                                                                          \
+        if ((regs)->trap & 1)                                                 \
+                printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
+} while (0)
+#endif /* __powerpc64__ */
 #endif /* __ASSEMBLY__ */
-#define STACK_FRAME_OVERHEAD    112     /* size of minimum stack frame */
+#endif /* __KERNEL__ */
-/* Size of dummy stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE      128
-#define __SIGNAL_FRAMESIZE32    64
 /*
 * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
 */
 #define PT_R0   0
 #define PT_R1   1
@@ -137,18 +163,25 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define PT_LNK  36
 #define PT_XER  37
 #define PT_CCR  38
+#ifndef __powerpc64__
+#define PT_MQ   39
+#else
 #define PT_SOFTE 39
 #define PT_TRAP 40
 #define PT_DAR  41
 #define PT_DSISR 42
 #define PT_RESULT 43
+#endif
-#define PT_FPR0 48
+#define PT_FPR0 48      /* each FP reg occupies 2 slots in this space */
+#ifndef __powerpc64__
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+#else /* __powerpc64__ */
-/*
- * Kernel and userspace will both use this PT_FPSCR value.  32-bit apps will
- * have visibility to the asm-ppc/ptrace.h header instead of this one.
- */
 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
 #ifdef __KERNEL__
@@ -165,29 +198,29 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define PT_VRSAVE_32 (PT_VR0 + 33*4)
 #endif
+#endif /* __powerpc64__ */
 /*
- * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. 
+ * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
- * The transfer totals 34 quadword.  Quadwords 0-31 contain the 
+ * The transfer totals 34 quadword.  Quadwords 0-31 contain the
- * corresponding vector registers.  Quadword 32 contains the vscr as the 
+ * corresponding vector registers.  Quadword 32 contains the vscr as the
- * last word (offset 12) within that quadword.  Quadword 33 contains the 
+ * last word (offset 12) within that quadword.  Quadword 33 contains the
 * vrsave as the first word (offset 0) within the quadword.
 *
- * This definition of the VMX state is compatible with the current PPC32 
+ * This definition of the VMX state is compatible with the current PPC32
- * ptrace interface.  This allows signal handling and ptrace to use the same 
+ * ptrace interface.  This allows signal handling and ptrace to use the same
- * structures.  This also simplifies the implementation of a bi-arch 
+ * structures.  This also simplifies the implementation of a bi-arch
 * (combined (32- and 64-bit) gdb.
 */
 #define PTRACE_GETVRREGS        18
 #define PTRACE_SETVRREGS        19
-/*
+#ifndef __powerpc64__
- * While we dont have 64bit book E processors, we need to reserve the
+/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
- * relevant ptrace calls for 32bit compatibility.
+ * spefscr, in one go */
- */
+#define PTRACE_GETEVRREGS       20
-#if 0
+#define PTRACE_SETEVRREGS       21
-#define PTRACE_GETEVRREGS       20
+#endif /* __powerpc64__ */
-#define PTRACE_SETEVRREGS       21
-#endif
 /*
 * Get or set a debug register. The first 16 are DABR registers and the
@@ -196,6 +229,7 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define PTRACE_GET_DEBUGREG     25
 #define PTRACE_SET_DEBUGREG     26
+#ifdef __powerpc64__
 /* Additional PTRACE requests implemented on PowerPC. */
 #define PPC_PTRACE_GETREGS      0x99    /* Get GPRs 0 - 31 */
 #define PPC_PTRACE_SETREGS      0x98    /* Set GPRs 0 - 31 */
@@ -209,5 +243,6 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define PPC_PTRACE_POKEDATA_3264 0x92
 #define PPC_PTRACE_PEEKUSR_3264  0x91
 #define PPC_PTRACE_POKEUSR_3264  0x90
+#endif /* __powerpc64__ */
-#endif /* _PPC64_PTRACE_H */
+#endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/include/asm-ppc/reg.h b/include/asm-powerpc/reg.h
index 73c33e3ef9c6..da848412f11b 100644
--- a/include/asm-ppc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -6,53 +6,107 @@
 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
 */
+#ifndef _ASM_POWERPC_REG_H
+#define _ASM_POWERPC_REG_H
 #ifdef __KERNEL__
-#ifndef __ASM_PPC_REGS_H__
-#define __ASM_PPC_REGS_H__
 #include <linux/stringify.h>
+#include <asm/cputable.h>
 /* Pickup Book E specific registers. */
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 #include <asm/reg_booke.h>
 #endif
-/* Machine State Register (MSR) Fields */
+#define MSR_SF_LG       63              /* Enable 64 bit mode */
-#define MSR_SF          (1<<63)
+#define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
-#define MSR_ISF         (1<<61)
+#define MSR_HV_LG       60              /* Hypervisor state */
-#define MSR_VEC         (1<<25)         /* Enable AltiVec */
+#define MSR_VEC_LG      25              /* Enable AltiVec */
-#define MSR_POW         (1<<18)         /* Enable Power Management */
+#define MSR_POW_LG      18              /* Enable Power Management */
-#define MSR_WE          (1<<18)         /* Wait State Enable */
+#define MSR_WE_LG       18              /* Wait State Enable */
-#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
+#define MSR_TGPR_LG     17              /* TLB Update registers in use */
-#define MSR_CE          (1<<17)         /* Critical Interrupt Enable */
+#define MSR_CE_LG       17              /* Critical Interrupt Enable */
-#define MSR_ILE         (1<<16)         /* Interrupt Little Endian */
+#define MSR_ILE_LG      16              /* Interrupt Little Endian */
-#define MSR_EE          (1<<15)         /* External Interrupt Enable */
+#define MSR_EE_LG       15              /* External Interrupt Enable */
-#define MSR_PR          (1<<14)         /* Problem State / Privilege Level */
+#define MSR_PR_LG       14              /* Problem State / Privilege Level */
-#define MSR_FP          (1<<13)         /* Floating Point enable */
+#define MSR_FP_LG       13              /* Floating Point enable */
-#define MSR_ME          (1<<12)         /* Machine Check Enable */
+#define MSR_ME_LG       12              /* Machine Check Enable */
-#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
+#define MSR_FE0_LG      11              /* Floating Exception mode 0 */
-#define MSR_SE          (1<<10)         /* Single Step */
+#define MSR_SE_LG       10              /* Single Step */
-#define MSR_BE          (1<<9)          /* Branch Trace */
+#define MSR_BE_LG       9               /* Branch Trace */
-#define MSR_DE          (1<<9)          /* Debug Exception Enable */
+#define MSR_DE_LG       9               /* Debug Exception Enable */
-#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
+#define MSR_FE1_LG      8               /* Floating Exception mode 1 */
-#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
+#define MSR_IP_LG       6               /* Exception prefix 0x000/0xFFF */
-#define MSR_IR          (1<<5)          /* Instruction Relocate */
+#define MSR_IR_LG       5               /* Instruction Relocate */
-#define MSR_DR          (1<<4)          /* Data Relocate */
+#define MSR_DR_LG       4               /* Data Relocate */
-#define MSR_PE          (1<<3)          /* Protection Enable */
+#define MSR_PE_LG       3               /* Protection Enable */
-#define MSR_PX          (1<<2)          /* Protection Exclusive Mode */
+#define MSR_PX_LG       2               /* Protection Exclusive Mode */
-#define MSR_RI          (1<<1)          /* Recoverable Exception */
+#define MSR_PMM_LG      2               /* Performance monitor */
-#define MSR_LE          (1<<0)          /* Little Endian */
+#define MSR_RI_LG       1               /* Recoverable Exception */
+#define MSR_LE_LG       0               /* Little Endian */
+#ifdef __ASSEMBLY__
+#define __MASK(X)       (1<<(X))
+#else
+#define __MASK(X)       (1UL<<(X))
+#endif
+#ifdef CONFIG_PPC64
+#define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
+#define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
+#define MSR_HV          __MASK(MSR_HV_LG)       /* Hypervisor state */
+#else
+/* so tests for these bits fail on 32-bit */
+#define MSR_SF          0
+#define MSR_ISF         0
+#define MSR_HV          0
+#endif
+#define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
+#define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
+#define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
+#define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
+#define MSR_CE          __MASK(MSR_CE_LG)       /* Critical Interrupt Enable */
+#define MSR_ILE         __MASK(MSR_ILE_LG)      /* Interrupt Little Endian */
+#define MSR_EE          __MASK(MSR_EE_LG)       /* External Interrupt Enable */
+#define MSR_PR          __MASK(MSR_PR_LG)       /* Problem State / Privilege Level */
+#define MSR_FP          __MASK(MSR_FP_LG)       /* Floating Point enable */
+#define MSR_ME          __MASK(MSR_ME_LG)       /* Machine Check Enable */
+#define MSR_FE0         __MASK(MSR_FE0_LG)      /* Floating Exception mode 0 */
+#define MSR_SE          __MASK(MSR_SE_LG)       /* Single Step */
+#define MSR_BE          __MASK(MSR_BE_LG)       /* Branch Trace */
+#define MSR_DE          __MASK(MSR_DE_LG)       /* Debug Exception Enable */
+#define MSR_FE1         __MASK(MSR_FE1_LG)      /* Floating Exception mode 1 */
+#define MSR_IP          __MASK(MSR_IP_LG)       /* Exception prefix 0x000/0xFFF */
+#define MSR_IR          __MASK(MSR_IR_LG)       /* Instruction Relocate */
+#define MSR_DR          __MASK(MSR_DR_LG)       /* Data Relocate */
+#define MSR_PE          __MASK(MSR_PE_LG)       /* Protection Enable */
+#define MSR_PX          __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
+#ifndef MSR_PMM
+#define MSR_PMM         __MASK(MSR_PMM_LG)      /* Performance monitor */
+#endif
+#define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
+#define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
+#ifdef CONFIG_PPC64
+#define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
+#define MSR_KERNEL      MSR_ | MSR_SF | MSR_HV
+#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
+#define MSR_USER64      MSR_USER32 | MSR_SF
+#else /* 32-bit */
 /* Default MSR for kernel mode. */
+#ifndef MSR_KERNEL      /* reg_booke.h also defines this */
 #ifdef CONFIG_APUS_FAST_EXCEPT
 #define MSR_KERNEL      (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR)
-#endif
+#else
-#ifndef MSR_KERNEL
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
 #endif
+#endif
 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
+#endif
 /* Floating Point Status and Control Register (FPSCR) Fields */
 #define FPSCR_FX        0x80000000      /* FPU exception summary */
@@ -60,7 +114,7 @@
 #define FPSCR_VX        0x20000000      /* Invalid operation summary */
 #define FPSCR_OX        0x10000000      /* Overflow exception summary */
 #define FPSCR_UX        0x08000000      /* Underflow exception summary */
-#define FPSCR_ZX        0x04000000      /* Zero-devide exception summary */
+#define FPSCR_ZX        0x04000000      /* Zero-divide exception summary */
 #define FPSCR_XX        0x02000000      /* Inexact exception summary */
 #define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
 #define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
@@ -85,8 +139,18 @@
 /* Special Purpose Registers (SPRNs)*/
 #define SPRN_CTR        0x009   /* Count Register */
+#define SPRN_CTRLF      0x088
+#define SPRN_CTRLT      0x098
+#define   CTRL_RUNLATCH 0x1
 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
+#define   DABR_TRANSLATION      (1UL << 2)
 #define SPRN_DAR        0x013   /* Data Address Register */
+#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
+#define   DSISR_NOHPTE          0x40000000      /* no translation found */
+#define   DSISR_PROTFAULT       0x08000000      /* protection fault */
+#define   DSISR_ISSTORE         0x02000000      /* access was a store */
+#define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
+#define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
 #define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
 #define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
@@ -131,7 +195,6 @@
 #define DER_EBRKE       0x00000002      /* External Breakpoint Interrupt */
 #define DER_DPIE        0x00000001      /* Dev. Port Nonmaskable Request */
 #define SPRN_DMISS      0x3D0           /* Data TLB Miss Register */
-#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 #define SPRN_EAR        0x11A           /* External Address Register */
 #define SPRN_HASH1      0x3D2           /* Primary Hash Address Register */
 #define SPRN_HASH2      0x3D3           /* Secondary Hash Address Resgister */
@@ -187,6 +250,16 @@
 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 #define SPRN_HID4       0x3F4           /* 970 HID4 */
 #define SPRN_HID5       0x3F6           /* 970 HID5 */
+#define SPRN_HID6       0x3F9   /* BE HID 6 */
+#define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
+#define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
+#define SPRN_TSCR       0x399   /* Thread switch control on BE */
+#define SPRN_TTR        0x39A   /* Thread switch timeout on BE */
+#define   TSCR_DEC_ENABLE       0x200000 /* Decrementer Interrupt */
+#define   TSCR_EE_ENABLE        0x100000 /* External Interrupt */
+#define   TSCR_EE_BOOST         0x080000 /* External Interrupt Boost */
+#define SPRN_TSC        0x3FD   /* Thread switch control on others */
+#define SPRN_TST        0x3FC   /* Thread switch timeout on others */
 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
 #define SPRN_IAC1       0x3F4           /* Instruction Address Compare 1 */
 #define SPRN_IAC2       0x3F5           /* Instruction Address Compare 2 */
@@ -270,22 +343,18 @@
 #define L3CR_L3DO               0x00000040      /* L3 data only mode */
 #define L3CR_PMEN               0x00000004      /* L3 private memory enable */
 #define L3CR_PMSIZ              0x00000001      /* L3 private memory size */
 #define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
 #define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
 #define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
 #define SPRN_LDSTDB     0x3f4   /* */
 #define SPRN_LR         0x008   /* Link Register */
-#define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
-#define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
 #ifndef SPRN_PIR
 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
 #endif
-#define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
-#define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
-#define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
-#define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
 #define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
 #define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
+#define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
 #define SPRN_PVR        0x11F   /* Processor Version Register */
 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
@@ -327,6 +396,52 @@
 #define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
 #define SPRN_XER        0x001   /* Fixed Point Exception Register */
+/* Performance monitor SPRs */
+#ifdef CONFIG_PPC64
+#define SPRN_MMCR0      795
+#define   MMCR0_FC      0x80000000UL /* freeze counters */
+#define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
+#define   MMCR0_KERNEL_DISABLE MMCR0_FCS
+#define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
+#define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
+#define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
+#define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
+#define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
+#define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
+#define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
+#define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
+#define   MMCR0_PMCjCE  0x00004000UL /* PMCj count enable*/
+#define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+#define   MMCR0_PMAO    0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
+#define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
+#define   MMCR0_FCTI    0x00000008UL /* freeze counters in tags inactive mode */
+#define   MMCR0_FCTA    0x00000004UL /* freeze counters in tags active mode */
+#define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
+#define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
+#define SPRN_MMCR1      798
+#define SPRN_MMCRA      0x312
+#define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
+#define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
+#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
+#define SPRN_PMC1       787
+#define SPRN_PMC2       788
+#define SPRN_PMC3       789
+#define SPRN_PMC4       790
+#define SPRN_PMC5       791
+#define SPRN_PMC6       792
+#define SPRN_PMC7       793
+#define SPRN_PMC8       794
+#define SPRN_SIAR       780
+#define SPRN_SDAR       781
+#else /* 32-bit */
+#define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
+#define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
+#define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
+#define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
+#define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
+#define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
 #define MMCR0_PMC1_CYCLES       (1 << 7)
 #define MMCR0_PMC1_ICACHEMISS   (5 << 7)
@@ -336,14 +451,15 @@
 #define MMCR0_PMC2_ITLB         0x7
 #define MMCR0_PMC2_LOADMISSTIME 0x5
 #define MMCR0_PMXE      (1 << 26)
+#endif
-/* Processor Version Register */
 /* Processor Version Register (PVR) field extraction */
 #define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)       /* Version field */
 #define PVR_REV(pvr)    (((pvr) >>   0) & 0xFFFF)       /* Revison field */
+#define __is_processor(pv)      (PVR_VER(mfspr(SPRN_PVR)) == (pv))
 /*
 * IBM has further subdivided the standard PowerPC 16-bit version and
 * revision subfields of the PVR for the PowerPC 403s into the following:
@@ -399,42 +515,99 @@
 #define PVR_8245        0x80811014
 #define PVR_8260        PVR_8240
-#if 0
+/* 64-bit processors */
-/* Segment Registers */
+/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
-#define SR0     0
+#define PV_NORTHSTAR    0x0033
-#define SR1     1
+#define PV_PULSAR       0x0034
-#define SR2     2
+#define PV_POWER4       0x0035
-#define SR3     3
+#define PV_ICESTAR      0x0036
-#define SR4     4
+#define PV_SSTAR        0x0037
-#define SR5     5
+#define PV_POWER4p      0x0038
-#define SR6     6
+#define PV_970          0x0039
-#define SR7     7
+#define PV_POWER5       0x003A
-#define SR8     8
+#define PV_POWER5p      0x003B
-#define SR9     9
+#define PV_970FX        0x003C
-#define SR10    10
+#define PV_630          0x0040
-#define SR11    11
+#define PV_630p 0x0041
-#define SR12    12
+#define PV_970MP        0x0044
-#define SR13    13
+#define PV_BE           0x0070
-#define SR14    14
-#define SR15    15
+/*
-#endif
+ * Number of entries in the SLB. If this ever changes we should handle
+ * it with a use a cpu feature fixup.
+ */
+#define SLB_NUM_ENTRIES 64
 /* Macros for setting and retrieving special purpose registers */
 #ifndef __ASSEMBLY__
-#define mfmsr()         ({unsigned int rval; \
+#define mfmsr()         ({unsigned long rval; \
                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+#ifdef CONFIG_PPC64
+#define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
+                                     : : "r" (v))
+#define mtmsrd(v)       __mtmsrd((v), 0)
+#define mtmsr(v)        mtmsrd(v)
+#else
 #define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v))
+#endif
-#define mfspr(rn)       ({unsigned int rval; \
+#define mfspr(rn)       ({unsigned long rval; \
                        asm volatile("mfspr %0," __stringify(rn) \
                                : "=r" (rval)); rval;})
 #define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
+#define mftb()          ({unsigned long rval;   \
+                        asm volatile("mftb %0" : "=r" (rval)); rval;})
+#define mftbl()         ({unsigned long rval;   \
+                        asm volatile("mftbl %0" : "=r" (rval)); rval;})
+#define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
+#define mttbu(v)        asm volatile("mttbu %0":: "r"(v))
+#ifdef CONFIG_PPC32
 #define mfsrin(v)       ({unsigned int rval; \
                        asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
                                        rval;})
+#endif
 #define proc_trap()     asm volatile("trap")
+#ifdef CONFIG_PPC64
+static inline void ppc64_runlatch_on(void)
+{
+        unsigned long ctrl;
+        if (cpu_has_feature(CPU_FTR_CTRL)) {
+                ctrl = mfspr(SPRN_CTRLF);
+                ctrl |= CTRL_RUNLATCH;
+                mtspr(SPRN_CTRLT, ctrl);
+        }
+}
+static inline void ppc64_runlatch_off(void)
+{
+        unsigned long ctrl;
+        if (cpu_has_feature(CPU_FTR_CTRL)) {
+                ctrl = mfspr(SPRN_CTRLF);
+                ctrl &= ~CTRL_RUNLATCH;
+                mtspr(SPRN_CTRLT, ctrl);
+        }
+}
+#endif
+#define __get_SP()      ({unsigned long sp; \
+                        asm volatile("mr %0,1": "=r" (sp)); sp;})
+#else /* __ASSEMBLY__ */
+#define RUNLATCH_ON(REG)                        \
+BEGIN_FTR_SECTION                               \
+        mfspr   (REG),SPRN_CTRLF;               \
+        ori     (REG),(REG),CTRL_RUNLATCH;      \
+        mtspr   SPRN_CTRLT,(REG);               \
+END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
 #endif /* __ASSEMBLY__ */
-#endif /* __ASM_PPC_REGS_H__ */
 #endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_REG_H */
diff --git a/include/asm-ppc64/rtas.h b/include/asm-powerpc/rtas.h
index e7d1b5222802..d1bb611ea626 100644
--- a/include/asm-ppc64/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_RTAS_H
+#ifndef _POWERPC_RTAS_H
-#define _PPC64_RTAS_H
+#define _POWERPC_RTAS_H
 #include <linux/spinlock.h>
 #include <asm/page.h>
@@ -149,28 +149,11 @@ struct rtas_error_log {
        unsigned char buffer[1];
 };
-struct flash_block {
+/*
-        char *data;
+ * This can be set by the rtas_flash module so that it can get called
-        unsigned long length;
+ * as the absolutely last thing before the kernel terminates.
-};
-/* This struct is very similar but not identical to
- * that needed by the rtas flash update.
- * All we need to do for rtas is rewrite num_blocks
- * into a version/length and translate the pointers
- * to absolute.
 */
-#define FLASH_BLOCKS_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct flash_block))
+extern void (*rtas_flash_term_hook)(int);
-struct flash_block_list {
-        unsigned long num_blocks;
-        struct flash_block_list *next;
-        struct flash_block blocks[FLASH_BLOCKS_PER_NODE];
-};
-struct flash_block_list_header { /* just the header of flash_block_list */
-        unsigned long num_blocks;
-        struct flash_block_list *next;
-};
-extern struct flash_block_list_header rtas_firmware_flash_list;
 extern struct rtas_t rtas;
@@ -190,7 +173,7 @@ extern void rtas_progress(char *s, unsigned short hex);
 extern void rtas_initialize(void);
 struct rtc_time;
-extern void rtas_get_boot_time(struct rtc_time *rtc_time);
+extern unsigned long rtas_get_boot_time(void);
 extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
 extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
@@ -246,4 +229,4 @@ extern unsigned long rtas_rmo_buf;
 #define GLOBAL_INTERRUPT_QUEUE 9005
-#endif /* _PPC64_RTAS_H */
+#endif /* _POWERPC_RTAS_H */
diff --git a/include/asm-powerpc/rtc.h b/include/asm-powerpc/rtc.h
new file mode 100644
index 000000000000..f5802926b6c0
--- /dev/null
+++ b/include/asm-powerpc/rtc.h
@@ -0,0 +1,78 @@
+/*
+ * Real-time clock definitions and interfaces
+ *
+ * Author: Tom Rini <trini@mvista.com>
+ *
+ * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Based on:
+ * include/asm-m68k/rtc.h
+ *
+ * Copyright Richard Zidlicky
+ * implementation details for genrtc/q40rtc driver
+ *
+ * And the old drivers/macintosh/rtc.c which was heavily based on:
+ * Linux/SPARC Real Time Clock Driver
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ *
+ * With additional work by Paul Mackerras and Franz Sirl.
+ */
+#ifndef __ASM_POWERPC_RTC_H__
+#define __ASM_POWERPC_RTC_H__
+#ifdef __KERNEL__
+#include <linux/rtc.h>
+#include <asm/machdep.h>
+#include <asm/time.h>
+#define RTC_PIE 0x40            /* periodic interrupt enable */
+#define RTC_AIE 0x20            /* alarm interrupt enable */
+#define RTC_UIE 0x10            /* update-finished interrupt enable */
+/* some dummy definitions */
+#define RTC_BATT_BAD 0x100      /* battery bad */
+#define RTC_SQWE 0x08           /* enable square-wave output */
+#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
+#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
+#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
+static inline unsigned int get_rtc_time(struct rtc_time *time)
+{
+        if (ppc_md.get_rtc_time)
+                ppc_md.get_rtc_time(time);
+        return RTC_24H;
+}
+/* Set the current date and time in the real time clock. */
+static inline int set_rtc_time(struct rtc_time *time)
+{
+        if (ppc_md.set_rtc_time)
+                return ppc_md.set_rtc_time(time);
+        return -EINVAL;
+}
+static inline unsigned int get_rtc_ss(void)
+{
+        struct rtc_time h;
+        get_rtc_time(&h);
+        return h.tm_sec;
+}
+static inline int get_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+static inline int set_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_RTC_H__ */
diff --git a/include/asm-ppc64/rwsem.h b/include/asm-powerpc/rwsem.h
index bd5c2f093575..79bae4933b73 100644
--- a/include/asm-ppc64/rwsem.h
+++ b/include/asm-powerpc/rwsem.h
@@ -1,18 +1,14 @@
+#ifndef _ASM_POWERPC_RWSEM_H
+#define _ASM_POWERPC_RWSEM_H
+#ifdef __KERNEL__
 /*
 * include/asm-ppc64/rwsem.h: R/W semaphores for PPC using the stuff
 * in lib/rwsem.c.  Adapted largely from include/asm-i386/rwsem.h
 * by Paul Mackerras <paulus@samba.org>.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
 */
-#ifndef _PPC64_RWSEM_H
-#define _PPC64_RWSEM_H
-#ifdef __KERNEL__
 #include <linux/list.h>
 #include <linux/spinlock.h>
 #include <asm/atomic.h>
@@ -163,5 +159,10 @@ static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
        return atomic_add_return(delta, (atomic_t *)(&sem->count));
 }
-#endif /* __KERNEL__ */
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
-#endif /* _PPC_RWSEM_XADD_H */
+{
+        return (sem->count != 0);
+}
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_RWSEM_H */
diff --git a/include/asm-ppc64/scatterlist.h b/include/asm-powerpc/scatterlist.h
index cecce6c6dfbb..8c992d1491d4 100644
--- a/include/asm-ppc64/scatterlist.h
+++ b/include/asm-powerpc/scatterlist.h
@@ -1,6 +1,5 @@
-#ifndef _PPC64_SCATTERLIST_H
+#ifndef _ASM_POWERPC_SCATTERLIST_H
-#define _PPC64_SCATTERLIST_H
+#define _ASM_POWERPC_SCATTERLIST_H
 /*
 * Copyright (C) 2001 PPC64 Team, IBM Corp
 *
@@ -10,6 +9,7 @@
 * 2 of the License, or (at your option) any later version.
 */
+#ifdef __KERNEL__
 #include <linux/types.h>
 #include <asm/dma.h>
@@ -19,13 +19,27 @@ struct scatterlist {
        unsigned int length;
        /* For TCE support */
-        u32 dma_address;
+        dma_addr_t dma_address;
        u32 dma_length;
 };
+/*
+ * These macros should be used after a dma_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
 #define sg_dma_address(sg)      ((sg)->dma_address)
+#ifdef __powerpc64__
 #define sg_dma_len(sg)          ((sg)->dma_length)
+#else
+#define sg_dma_len(sg)          ((sg)->length)
+#endif
+#ifdef __powerpc64__
 #define ISA_DMA_THRESHOLD       (~0UL)
+#endif
-#endif /* !(_PPC64_SCATTERLIST_H) */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SCATTERLIST_H */
diff --git a/include/asm-ppc64/seccomp.h b/include/asm-powerpc/seccomp.h
index c130c334bda1..1e1cfe12882b 100644
--- a/include/asm-ppc64/seccomp.h
+++ b/include/asm-powerpc/seccomp.h
@@ -1,11 +1,6 @@
-#ifndef _ASM_SECCOMP_H
+#ifndef _ASM_POWERPC_SECCOMP_H
-#include <linux/thread_info.h> /* already defines TIF_32BIT */
-#ifndef TIF_32BIT
-#error "unexpected TIF_32BIT on ppc64"
-#endif
+#include <linux/thread_info.h>
 #include <linux/unistd.h>
 #define __NR_seccomp_read __NR_read
@@ -18,4 +13,4 @@
 #define __NR_seccomp_exit_32 __NR_exit
 #define __NR_seccomp_sigreturn_32 __NR_sigreturn
-#endif /* _ASM_SECCOMP_H */
+#endif  /* _ASM_POWERPC_SECCOMP_H */
diff --git a/include/asm-ppc64/sections.h b/include/asm-powerpc/sections.h
index 308ca6f5ced2..47be2ac2a925 100644
--- a/include/asm-ppc64/sections.h
+++ b/include/asm-powerpc/sections.h
@@ -1,22 +1,11 @@
-#ifndef _PPC64_SECTIONS_H
+#ifndef _ASM_POWERPC_SECTIONS_H
-#define _PPC64_SECTIONS_H
+#define _ASM_POWERPC_SECTIONS_H
-extern char _end[];
 #include <asm-generic/sections.h>
-#define __pmac
+#ifdef __powerpc64__
-#define __pmacdata
-#define __prep
-#define __prepdata
-#define __chrp
-#define __chrpdata
-#define __openfirmware
-#define __openfirmwaredata
+extern char _end[];
 static inline int in_kernel_text(unsigned long addr)
 {
@@ -27,3 +16,5 @@ static inline int in_kernel_text(unsigned long addr)
 }
 #endif
+#endif  /* _ASM_POWERPC_SECTIONS_H */
diff --git a/include/asm-ppc64/semaphore.h b/include/asm-powerpc/semaphore.h
index aefe7753ea41..57369d2cadef 100644
--- a/include/asm-ppc64/semaphore.h
+++ b/include/asm-powerpc/semaphore.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_SEMAPHORE_H
+#ifndef _ASM_POWERPC_SEMAPHORE_H
-#define _PPC64_SEMAPHORE_H
+#define _ASM_POWERPC_SEMAPHORE_H
 /*
 * Remove spinlock-based RW semaphores; RW semaphore definitions are
@@ -31,9 +31,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name, 1)
 #define __DECLARE_SEMAPHORE_GENERIC(name, count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
@@ -95,4 +92,4 @@ static inline void up(struct semaphore * sem)
 #endif /* __KERNEL__ */
-#endif /* !(_PPC64_SEMAPHORE_H) */
+#endif /* _ASM_POWERPC_SEMAPHORE_H */
diff --git a/include/asm-ppc64/sigcontext.h b/include/asm-powerpc/sigcontext.h
index 6f8aee768c5e..165d630e1cf3 100644
--- a/include/asm-ppc64/sigcontext.h
+++ b/include/asm-powerpc/sigcontext.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_PPC64_SIGCONTEXT_H
+#ifndef _ASM_POWERPC_SIGCONTEXT_H
-#define _ASM_PPC64_SIGCONTEXT_H
+#define _ASM_POWERPC_SIGCONTEXT_H
 /*
 * This program is free software; you can redistribute it and/or
@@ -9,39 +9,44 @@
 */
 #include <linux/compiler.h>
 #include <asm/ptrace.h>
+#ifdef __powerpc64__
 #include <asm/elf.h>
+#endif
 struct sigcontext {
        unsigned long   _unused[4];
        int             signal;
+#ifdef __powerpc64__
        int             _pad0;
+#endif
        unsigned long   handler;
        unsigned long   oldmask;
        struct pt_regs  __user *regs;
+#ifdef __powerpc64__
        elf_gregset_t   gp_regs;
        elf_fpregset_t  fp_regs;
 /*
- * To maintain compatibility with current implementations the sigcontext is 
+ * To maintain compatibility with current implementations the sigcontext is
- * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) 
+ * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
- * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This 
+ * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This
- * allows the array of vector registers to be quadword aligned independent of 
+ * allows the array of vector registers to be quadword aligned independent of
- * the alignment of the containing sigcontext or ucontext. It is the 
+ * the alignment of the containing sigcontext or ucontext. It is the
- * responsibility of the code setting the sigcontext to set this pointer to 
+ * responsibility of the code setting the sigcontext to set this pointer to
- * either NULL (if this processor does not support the VMX feature) or the 
+ * either NULL (if this processor does not support the VMX feature) or the
 * address of the first quadword within the allocated (vmx_reserve) area.
 *
- * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with 
+ * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
- * an array of 34 quadword entries (elf_vrregset_t).  The entries with 
+ * an array of 34 quadword entries (elf_vrregset_t).  The entries with
- * indexes 0-31 contain the corresponding vector registers.  The entry with 
+ * indexes 0-31 contain the corresponding vector registers.  The entry with
- * index 32 contains the vscr as the last word (offset 12) within the 
+ * index 32 contains the vscr as the last word (offset 12) within the
- * quadword.  This allows the vscr to be stored as either a quadword (since 
+ * quadword.  This allows the vscr to be stored as either a quadword (since
- * it must be copied via a vector register to/from storage) or as a word.  
+ * it must be copied via a vector register to/from storage) or as a word.
- * The entry with index 33 contains the vrsave as the first word (offset 0) 
+ * The entry with index 33 contains the vrsave as the first word (offset 0)
 * within the quadword.
 */
        elf_vrreg_t     __user *v_regs;
        long            vmx_reserve[ELF_NVRREG+ELF_NVRREG+1];
+#endif
 };
-#endif /* _ASM_PPC64_SIGCONTEXT_H */
+#endif /* _ASM_POWERPC_SIGCONTEXT_H */
diff --git a/include/asm-ppc64/smp.h b/include/asm-powerpc/smp.h
index d86f742e9a21..8bcdd0faefea 100644
--- a/include/asm-ppc64/smp.h
+++ b/include/asm-powerpc/smp.h
@@ -1,5 +1,5 @@
 /* 
- * smp.h: PPC64 specific SMP code.
+ * smp.h: PowerPC-specific SMP code.
 *
 * Original was a copy of sparc smp.h.  Now heavily modified
 * for PPC.
@@ -13,9 +13,9 @@
 * 2 of the License, or (at your option) any later version.
 */
+#ifndef _ASM_POWERPC_SMP_H
+#define _ASM_POWERPC_SMP_H
 #ifdef __KERNEL__
-#ifndef _PPC64_SMP_H
-#define _PPC64_SMP_H
 #include <linux/config.h>
 #include <linux/threads.h>
@@ -24,7 +24,9 @@
 #ifndef __ASSEMBLY__
+#ifdef CONFIG_PPC64
 #include <asm/paca.h>
+#endif
 extern int boot_cpuid;
 extern int boot_cpuid_phys;
@@ -45,8 +47,19 @@ void generic_cpu_die(unsigned int cpu);
 void generic_mach_cpu_die(void);
 #endif
+#ifdef CONFIG_PPC64
 #define raw_smp_processor_id()  (get_paca()->paca_index)
 #define hard_smp_processor_id() (get_paca()->hw_cpu_id)
+#else
+/* 32-bit */
+extern int smp_hw_index[];
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
+#define hard_smp_processor_id()         (smp_hw_index[smp_processor_id()])
+#define get_hard_smp_processor_id(cpu)  (smp_hw_index[(cpu)])
+#define set_hard_smp_processor_id(cpu, phys)\
+                                        (smp_hw_index[(cpu)] = (phys))
+#endif
 extern cpumask_t cpu_sibling_map[NR_CPUS];
@@ -64,20 +77,35 @@ extern cpumask_t cpu_sibling_map[NR_CPUS];
 void smp_init_iSeries(void);
 void smp_init_pSeries(void);
+void smp_init_cell(void);
+void smp_setup_cpu_maps(void);
 extern int __cpu_disable(void);
 extern void __cpu_die(unsigned int cpu);
+#else
+/* for UP */
+#define smp_setup_cpu_maps()
+#define smp_release_cpus()
 #endif /* CONFIG_SMP */
+#ifdef CONFIG_PPC64
 #define get_hard_smp_processor_id(CPU) (paca[(CPU)].hw_cpu_id)
 #define set_hard_smp_processor_id(CPU, VAL) \
        do { (paca[(CPU)].hw_cpu_id = (VAL)); } while (0)
+#else
+/* 32-bit */
+#ifndef CONFIG_SMP
+#define get_hard_smp_processor_id(cpu)  boot_cpuid_phys
+#define set_hard_smp_processor_id(cpu, phys)
+#endif
+#endif
 extern int smt_enabled_at_boot;
 extern int smp_mpic_probe(void);
 extern void smp_mpic_setup_cpu(int cpu);
-extern void smp_mpic_message_pass(int target, int msg);
 extern void smp_generic_kick_cpu(int nr);
 extern void smp_generic_give_timebase(void);
@@ -85,15 +113,7 @@ extern void smp_generic_take_timebase(void);
 extern struct smp_ops_t *smp_ops;
-#ifdef CONFIG_PPC_PSERIES
-void vpa_init(int cpu);
-#else
-static inline void vpa_init(int cpu)
-{
-}
-#endif /* CONFIG_PPC_PSERIES */
 #endif /* __ASSEMBLY__ */
-#endif /* !(_PPC64_SMP_H) */
 #endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SMP_H) */
diff --git a/include/asm-ppc64/smu.h b/include/asm-powerpc/smu.h
index dee8eefe47bc..dee8eefe47bc 100644
--- a/include/asm-ppc64/smu.h
+++ b/include/asm-powerpc/smu.h
diff --git a/include/asm-ppc64/sparsemem.h b/include/asm-powerpc/sparsemem.h
index c5bd47e57f17..1c95ab99deb3 100644
--- a/include/asm-ppc64/sparsemem.h
+++ b/include/asm-powerpc/sparsemem.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_PPC64_SPARSEMEM_H
+#ifndef _ASM_POWERPC_SPARSEMEM_H
-#define _ASM_PPC64_SPARSEMEM_H 1
+#define _ASM_POWERPC_SPARSEMEM_H 1
 #ifdef CONFIG_SPARSEMEM
 /*
@@ -13,4 +13,4 @@
 #endif /* CONFIG_SPARSEMEM */
-#endif /* _ASM_PPC64_SPARSEMEM_H */
+#endif /* _ASM_POWERPC_SPARSEMEM_H */
diff --git a/include/asm-ppc64/spinlock_types.h b/include/asm-powerpc/spinlock_types.h
index a37c8eabb9f2..74236c9f05b1 100644
--- a/include/asm-ppc64/spinlock_types.h
+++ b/include/asm-powerpc/spinlock_types.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_SPINLOCK_TYPES_H
+#ifndef _ASM_POWERPC_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
+#define _ASM_POWERPC_SPINLOCK_TYPES_H
 #ifndef __LINUX_SPINLOCK_TYPES_H
 # error "please don't include this file directly"
diff --git a/include/asm-ppc64/sstep.h b/include/asm-powerpc/sstep.h
index 4a68db50ee6f..630a9889c07c 100644
--- a/include/asm-ppc64/sstep.h
+++ b/include/asm-powerpc/sstep.h
@@ -16,8 +16,10 @@ struct pt_regs;
 * we don't allow putting a breakpoint on an mtmsrd instruction.
 * Similarly we don't allow breakpoints on rfid instructions.
 * These macros tell us if an instruction is a mtmsrd or rfid.
+ * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
+ * and an mtmsrd (64-bit).
 */
-#define IS_MTMSRD(instr)        (((instr) & 0xfc0007fe) == 0x7c000164)
+#define IS_MTMSRD(instr)        (((instr) & 0xfc0007be) == 0x7c000124)
 #define IS_RFID(instr)          (((instr) & 0xfc0007fe) == 0x4c000024)
 /* Emulate instructions that cause a transfer of control. */
diff --git a/include/asm-powerpc/stat.h b/include/asm-powerpc/stat.h
new file mode 100644
index 000000000000..e4edc510b530
--- /dev/null
+++ b/include/asm-powerpc/stat.h
@@ -0,0 +1,81 @@
+#ifndef _ASM_POWERPC_STAT_H
+#define _ASM_POWERPC_STAT_H
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/types.h>
+#define STAT_HAVE_NSEC 1
+#ifndef __powerpc64__
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+#endif /* !__powerpc64__ */
+struct stat {
+        unsigned long   st_dev;
+        ino_t           st_ino;
+#ifdef __powerpc64__
+        nlink_t         st_nlink;
+        mode_t          st_mode;
+#else
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+#endif
+        uid_t           st_uid;
+        gid_t           st_gid;
+        unsigned long   st_rdev;
+        off_t           st_size;
+        unsigned long   st_blksize;
+        unsigned long   st_blocks;
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+        unsigned long   __unused4;
+        unsigned long   __unused5;
+#ifdef __powerpc64__
+        unsigned long   __unused6;
+#endif
+};
+/* This matches struct stat64 in glibc2.1. Only used for 32 bit. */
+struct stat64 {
+        unsigned long long st_dev;              /* Device.  */
+        unsigned long long st_ino;              /* File serial number.  */
+        unsigned int    st_mode;        /* File mode.  */
+        unsigned int    st_nlink;       /* Link count.  */
+        unsigned int    st_uid;         /* User ID of the file's owner.  */
+        unsigned int    st_gid;         /* Group ID of the file's group. */
+        unsigned long long st_rdev;     /* Device number, if device.  */
+        unsigned short  __pad2;
+        long long       st_size;        /* Size of file, in bytes.  */
+        int             st_blksize;     /* Optimal block size for I/O.  */
+        long long       st_blocks;      /* Number 512-byte blocks allocated. */
+        int             st_atime;       /* Time of last access.  */
+        unsigned int    st_atime_nsec;
+        int             st_mtime;       /* Time of last modification.  */
+        unsigned int    st_mtime_nsec;
+        int             st_ctime;       /* Time of last status change.  */
+        unsigned int    st_ctime_nsec;
+        unsigned int    __unused4;
+        unsigned int    __unused5;
+};
+#endif /* _ASM_POWERPC_STAT_H */
diff --git a/include/asm-ppc64/statfs.h b/include/asm-powerpc/statfs.h
index 3c985e5246a7..67024026c10d 100644
--- a/include/asm-ppc64/statfs.h
+++ b/include/asm-powerpc/statfs.h
@@ -1,12 +1,11 @@
-#ifndef _PPC64_STATFS_H
+#ifndef _ASM_POWERPC_STATFS_H
-#define _PPC64_STATFS_H
+#define _ASM_POWERPC_STATFS_H
-/*
+/* For ppc32 we just use the generic definitions, not so simple on ppc64 */
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
+#ifndef __powerpc64__
- * as published by the Free Software Foundation; either version
+#include <asm-generic/statfs.h>
- * 2 of the License, or (at your option) any later version.
+#else
- */
 #ifndef __KERNEL_STRICT_NAMES
 #include <linux/types.h>
@@ -57,5 +56,5 @@ struct compat_statfs64 {
        __u32 f_frsize;
        __u32 f_spare[5];
 };
+#endif /* ! __powerpc64__ */
-#endif  /* _PPC64_STATFS_H */
+#endif
diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
new file mode 100644
index 000000000000..4660c0394a77
--- /dev/null
+++ b/include/asm-powerpc/synch.h
@@ -0,0 +1,51 @@
+#ifndef _ASM_POWERPC_SYNCH_H 
+#define _ASM_POWERPC_SYNCH_H 
+#include <linux/config.h>
+#ifdef __powerpc64__
+#define __SUBARCH_HAS_LWSYNC
+#endif
+#ifdef __SUBARCH_HAS_LWSYNC
+#    define LWSYNC      lwsync
+#else
+#    define LWSYNC      sync
+#endif
+/*
+ * Arguably the bitops and *xchg operations don't imply any memory barrier
+ * or SMP ordering, but in fact a lot of drivers expect them to imply
+ * both, since they do on x86 cpus.
+ */
+#ifdef CONFIG_SMP
+#define EIEIO_ON_SMP    "eieio\n"
+#define ISYNC_ON_SMP    "\n\tisync"
+#define SYNC_ON_SMP     __stringify(LWSYNC) "\n"
+#else
+#define EIEIO_ON_SMP
+#define ISYNC_ON_SMP
+#define SYNC_ON_SMP
+#endif
+static inline void eieio(void)
+{
+        __asm__ __volatile__ ("eieio" : : : "memory");
+}
+static inline void isync(void)
+{
+        __asm__ __volatile__ ("isync" : : : "memory");
+}
+#ifdef CONFIG_SMP
+#define eieio_on_smp()  eieio()
+#define isync_on_smp()  isync()
+#else
+#define eieio_on_smp()  __asm__ __volatile__("": : :"memory")
+#define isync_on_smp()  __asm__ __volatile__("": : :"memory")
+#endif
+#endif  /* _ASM_POWERPC_SYNCH_H */
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
new file mode 100644
index 000000000000..b5da0b851e02
--- /dev/null
+++ b/include/asm-powerpc/system.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
+ */
+#ifndef _ASM_POWERPC_SYSTEM_H
+#define _ASM_POWERPC_SYSTEM_H
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <asm/hw_irq.h>
+#include <asm/ppc_asm.h>
+#include <asm/atomic.h>
+/*
+ * Memory barrier.
+ * The sync instruction guarantees that all memory accesses initiated
+ * by this processor have been performed (with respect to all other
+ * mechanisms that access memory).  The eieio instruction is a barrier
+ * providing an ordering (separately) for (a) cacheable stores and (b)
+ * loads and stores to non-cacheable memory (e.g. I/O devices).
+ *
+ * mb() prevents loads and stores being reordered across this point.
+ * rmb() prevents loads being reordered across this point.
+ * wmb() prevents stores being reordered across this point.
+ * read_barrier_depends() prevents data-dependent loads being reordered
+ *      across this point (nop on PPC).
+ *
+ * We have to use the sync instructions for mb(), since lwsync doesn't
+ * order loads with respect to previous stores.  Lwsync is fine for
+ * rmb(), though.  Note that lwsync is interpreted as sync by
+ * 32-bit and older 64-bit CPUs.
+ *
+ * For wmb(), we use sync since wmb is used in drivers to order
+ * stores to system memory with respect to writes to the device.
+ * However, smp_wmb() can be a lighter-weight eieio barrier on
+ * SMP since it is only used to order updates to system memory.
+ */
+#define mb()   __asm__ __volatile__ ("sync" : : : "memory")
+#define rmb()  __asm__ __volatile__ ("lwsync" : : : "memory")
+#define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
+#define read_barrier_depends()  do { } while(0)
+#define set_mb(var, value)      do { var = value; mb(); } while (0)
+#define set_wmb(var, value)     do { var = value; wmb(); } while (0)
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while(0)
+#endif /* CONFIG_SMP */
+#ifdef __KERNEL__
+struct task_struct;
+struct pt_regs;
+#ifdef CONFIG_DEBUGGER
+extern int (*__debugger)(struct pt_regs *regs);
+extern int (*__debugger_ipi)(struct pt_regs *regs);
+extern int (*__debugger_bpt)(struct pt_regs *regs);
+extern int (*__debugger_sstep)(struct pt_regs *regs);
+extern int (*__debugger_iabr_match)(struct pt_regs *regs);
+extern int (*__debugger_dabr_match)(struct pt_regs *regs);
+extern int (*__debugger_fault_handler)(struct pt_regs *regs);
+#define DEBUGGER_BOILERPLATE(__NAME) \
+static inline int __NAME(struct pt_regs *regs) \
+{ \
+        if (unlikely(__ ## __NAME)) \
+                return __ ## __NAME(regs); \
+        return 0; \
+}
+DEBUGGER_BOILERPLATE(debugger)
+DEBUGGER_BOILERPLATE(debugger_ipi)
+DEBUGGER_BOILERPLATE(debugger_bpt)
+DEBUGGER_BOILERPLATE(debugger_sstep)
+DEBUGGER_BOILERPLATE(debugger_iabr_match)
+DEBUGGER_BOILERPLATE(debugger_dabr_match)
+DEBUGGER_BOILERPLATE(debugger_fault_handler)
+#ifdef CONFIG_XMON
+extern void xmon_init(int enable);
+#endif
+#else
+static inline int debugger(struct pt_regs *regs) { return 0; }
+static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
+static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
+static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
+static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
+static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
+static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
+#endif
+extern int set_dabr(unsigned long dabr);
+extern void print_backtrace(unsigned long *);
+extern void show_regs(struct pt_regs * regs);
+extern void flush_instruction_cache(void);
+extern void hard_reset_now(void);
+extern void poweroff_now(void);
+#ifdef CONFIG_6xx
+extern long _get_L2CR(void);
+extern long _get_L3CR(void);
+extern void _set_L2CR(unsigned long);
+extern void _set_L3CR(unsigned long);
+#else
+#define _get_L2CR()     0L
+#define _get_L3CR()     0L
+#define _set_L2CR(val)  do { } while(0)
+#define _set_L3CR(val)  do { } while(0)
+#endif
+extern void via_cuda_init(void);
+extern void read_rtc_time(void);
+extern void pmac_find_display(void);
+extern void giveup_fpu(struct task_struct *);
+extern void disable_kernel_fp(void);
+extern void enable_kernel_fp(void);
+extern void flush_fp_to_thread(struct task_struct *);
+extern void enable_kernel_altivec(void);
+extern void giveup_altivec(struct task_struct *);
+extern void load_up_altivec(struct task_struct *);
+extern int emulate_altivec(struct pt_regs *);
+extern void giveup_spe(struct task_struct *);
+extern void load_up_spe(struct task_struct *);
+extern int fix_alignment(struct pt_regs *);
+extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
+extern void cvt_df(double *from, float *to, struct thread_struct *thread);
+#ifdef CONFIG_ALTIVEC
+extern void flush_altivec_to_thread(struct task_struct *);
+#else
+static inline void flush_altivec_to_thread(struct task_struct *t)
+{
+}
+#endif
+#ifdef CONFIG_SPE
+extern void flush_spe_to_thread(struct task_struct *);
+#else
+static inline void flush_spe_to_thread(struct task_struct *t)
+{
+}
+#endif
+extern int call_rtas(const char *, int, int, unsigned long *, ...);
+extern void cacheable_memzero(void *p, unsigned int nb);
+extern void *cacheable_memcpy(void *, const void *, unsigned int);
+extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
+extern void bad_page_fault(struct pt_regs *, unsigned long, int);
+extern int die(const char *, struct pt_regs *, long);
+extern void _exception(int, struct pt_regs *, int, unsigned long);
+#ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+#endif /* CONFIG_BOOKE_WDT */
+/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
+extern unsigned char e2a(unsigned char);
+struct device_node;
+extern void note_scsi_host(struct device_node *, void *);
+extern struct task_struct *__switch_to(struct task_struct *,
+        struct task_struct *);
+#define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
+struct thread_struct;
+extern struct task_struct *_switch(struct thread_struct *prev,
+                                   struct thread_struct *next);
+extern unsigned int rtas_data;
+extern int mem_init_done;       /* set on boot once kmalloc can be called */
+extern unsigned long memory_limit;
+extern int powersave_nap;       /* set if nap mode can be used in idle loop */
+/*
+ * Atomic exchange
+ *
+ * Changes the memory location '*ptr' to be val and returns
+ * the previous value stored there.
+ */
+static __inline__ unsigned long
+__xchg_u32(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+        __asm__ __volatile__(
+        EIEIO_ON_SMP
+"1:     lwarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %3,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (prev), "=m" (*(volatile unsigned int *)p)
+        : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p)
+        : "cc", "memory");
+        return prev;
+}
+#ifdef CONFIG_PPC64
+static __inline__ unsigned long
+__xchg_u64(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+        __asm__ __volatile__(
+        EIEIO_ON_SMP
+"1:     ldarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stdcx.  %3,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
+        : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
+        : "cc", "memory");
+        return prev;
+}
+#endif
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid xchg().
+ */
+extern void __xchg_called_with_bad_pointer(void);
+static __inline__ unsigned long
+__xchg(volatile void *ptr, unsigned long x, unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __xchg_u32(ptr, x);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __xchg_u64(ptr, x);
+#endif
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+#define xchg(ptr,x)                                                          \
+  ({                                                                         \
+     __typeof__(*(ptr)) _x_ = (x);                                           \
+     (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
+  })
+#define tas(ptr) (xchg((ptr),1))
+/*
+ * Compare and exchange - if *p == old, set it to new,
+ * and return the old value of *p.
+ */
+#define __HAVE_ARCH_CMPXCHG     1
+static __inline__ unsigned long
+__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
+{
+        unsigned int prev;
+        __asm__ __volatile__ (
+        EIEIO_ON_SMP
+"1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
+        cmpw    0,%0,%3\n\
+        bne-    2f\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %4,0,%2\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        "\n\
+2:"
+        : "=&r" (prev), "=m" (*p)
+        : "r" (p), "r" (old), "r" (new), "m" (*p)
+        : "cc", "memory");
+        return prev;
+}
+#ifdef CONFIG_PPC64
+static __inline__ unsigned long
+__cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new)
+{
+        unsigned long prev;
+        __asm__ __volatile__ (
+        EIEIO_ON_SMP
+"1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
+        cmpd    0,%0,%3\n\
+        bne-    2f\n\
+        stdcx.  %4,0,%2\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        "\n\
+2:"
+        : "=&r" (prev), "=m" (*p)
+        : "r" (p), "r" (old), "r" (new), "m" (*p)
+        : "cc", "memory");
+        return prev;
+}
+#endif
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid cmpxchg().  */
+extern void __cmpxchg_called_with_bad_pointer(void);
+static __inline__ unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
+          unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32(ptr, old, new);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __cmpxchg_u64(ptr, old, new);
+#endif
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+#define cmpxchg(ptr,o,n)                                                 \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+#ifdef CONFIG_PPC64
+/*
+ * We handle most unaligned accesses in hardware. On the other hand 
+ * unaligned DMA can be very expensive on some ppc64 IO chips (it does
+ * powers of 2 writes until it reaches sufficient alignment).
+ *
+ * Based on this we disable the IP header alignment in network drivers.
+ */
+#define NET_IP_ALIGN   0
+#endif
+#define arch_align_stack(x) (x)
+/* Used in very early kernel initialization. */
+extern unsigned long reloc_offset(void);
+extern unsigned long add_reloc_offset(unsigned long);
+extern void reloc_got2(unsigned long);
+#define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
+static inline void create_instruction(unsigned long addr, unsigned int instr)
+{
+        unsigned int *p;
+        p  = (unsigned int *)addr;
+        *p = instr;
+        asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
+}
+/* Flags for create_branch:
+ * "b"   == create_branch(addr, target, 0);
+ * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
+ * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
+ * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
+ */
+#define BRANCH_SET_LINK 0x1
+#define BRANCH_ABSOLUTE 0x2
+static inline void create_branch(unsigned long addr,
+                unsigned long target, int flags)
+{
+        unsigned int instruction;
+        if (! (flags & BRANCH_ABSOLUTE))
+                target = target - addr;
+        /* Mask out the flags and target, so they don't step on each other. */
+        instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
+        create_instruction(addr, instruction);
+}
+static inline void create_function_call(unsigned long addr, void * func)
+{
+        unsigned long func_addr;
+#ifdef CONFIG_PPC64
+        /*
+         * On PPC64 the function pointer actually points to the function's
+         * descriptor. The first entry in the descriptor is the address
+         * of the function text.
+         */
+        func_addr = *(unsigned long *)func;
+#else
+        func_addr = (unsigned long)func;
+#endif
+        create_branch(addr, func_addr, BRANCH_SET_LINK);
+}
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SYSTEM_H */
diff --git a/include/asm-powerpc/termios.h b/include/asm-powerpc/termios.h
index c5b8e5358f83..7f80a019b6a0 100644
--- a/include/asm-powerpc/termios.h
+++ b/include/asm-powerpc/termios.h
@@ -94,142 +94,9 @@ struct termio {
 #define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025" 
 #endif
-#define FIOCLEX         _IO('f', 1)
-#define FIONCLEX        _IO('f', 2)
-#define FIOASYNC        _IOW('f', 125, int)
-#define FIONBIO         _IOW('f', 126, int)
-#define FIONREAD        _IOR('f', 127, int)
-#define TIOCINQ         FIONREAD
-#define TIOCGETP        _IOR('t', 8, struct sgttyb)
-#define TIOCSETP        _IOW('t', 9, struct sgttyb)
-#define TIOCSETN        _IOW('t', 10, struct sgttyb)    /* TIOCSETP wo flush */
-#define TIOCSETC        _IOW('t', 17, struct tchars)
-#define TIOCGETC        _IOR('t', 18, struct tchars)
-#define TCGETS          _IOR('t', 19, struct termios)
-#define TCSETS          _IOW('t', 20, struct termios)
-#define TCSETSW         _IOW('t', 21, struct termios)
-#define TCSETSF         _IOW('t', 22, struct termios)
-#define TCGETA          _IOR('t', 23, struct termio)
-#define TCSETA          _IOW('t', 24, struct termio)
-#define TCSETAW         _IOW('t', 25, struct termio)
-#define TCSETAF         _IOW('t', 28, struct termio)
-#define TCSBRK          _IO('t', 29)
-#define TCXONC          _IO('t', 30)
-#define TCFLSH          _IO('t', 31)
-#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
-#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
-#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
-#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
-#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
-#define TIOCGLTC        _IOR('t', 116, struct ltchars)
-#define TIOCSLTC        _IOW('t', 117, struct ltchars)
-#define TIOCSPGRP       _IOW('t', 118, int)
-#define TIOCGPGRP       _IOR('t', 119, int)
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-#define TIOCSTI         0x5412
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-/* Used for packet mode */
-#define TIOCPKT_DATA             0
-#define TIOCPKT_FLUSHREAD        1
-#define TIOCPKT_FLUSHWRITE       2
-#define TIOCPKT_STOP             4
-#define TIOCPKT_START            8
-#define TIOCPKT_NOSTOP          16
-#define TIOCPKT_DOSTOP          32
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
 #ifdef __KERNEL__
-/*
+#include <asm-generic/termios.h>
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
-        unsigned short __tmp; \
-        get_user(__tmp,&(termio)->x); \
-        (termios)->x = (0xffff0000 & (termios)->x) | __tmp; \
-}
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
 #endif  /* __KERNEL__ */
diff --git a/include/asm-ppc64/thread_info.h b/include/asm-powerpc/thread_info.h
index 0494df6fca74..ab17db79f69d 100644
--- a/include/asm-ppc64/thread_info.h
+++ b/include/asm-powerpc/thread_info.h
@@ -1,15 +1,25 @@
-/* thread_info.h: PPC low-level thread information
+/* thread_info.h: PowerPC low-level thread information
 * adapted from the i386 version by Paul Mackerras
 *
 * Copyright (C) 2002  David Howells (dhowells@redhat.com)
 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
 */
-#ifndef _ASM_THREAD_INFO_H
+#ifndef _ASM_POWERPC_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
+#define _ASM_POWERPC_THREAD_INFO_H
 #ifdef __KERNEL__
+/* We have 8k stacks on ppc32 and 16k on ppc64 */
+#ifdef CONFIG_PPC64
+#define THREAD_SHIFT            14
+#else
+#define THREAD_SHIFT            13
+#endif
+#define THREAD_SIZE             (1 << THREAD_SHIFT)
 #ifndef __ASSEMBLY__
 #include <linux/config.h>
 #include <linux/cache.h>
@@ -24,7 +34,8 @@ struct thread_info {
        struct task_struct *task;               /* main task structure */
        struct exec_domain *exec_domain;        /* execution domain */
        int             cpu;                    /* cpu we're on */
-        int             preempt_count;          /* 0 => preemptable, <0 => BUG */
+        int             preempt_count;          /* 0 => preemptable,
+                                                   <0 => BUG */
        struct restart_block restart_block;
        /* set by force_successful_syscall_return */
        unsigned char   syscall_noerror;
@@ -54,32 +65,38 @@ struct thread_info {
 /* thread information allocation */
-#define THREAD_ORDER            2
-#define THREAD_SIZE             (PAGE_SIZE << THREAD_ORDER)
-#define THREAD_SHIFT            (PAGE_SHIFT + THREAD_ORDER)
 #ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info(tsk)                                  \
+#define THREAD_INFO_GFP         GFP_KERNEL | __GFP_ZERO
-        ({                                                      \
-                struct thread_info *ret;                        \
-                                                                \
-                ret = kmalloc(THREAD_SIZE, GFP_KERNEL);         \
-                if (ret)                                        \
-                        memset(ret, 0, THREAD_SIZE);            \
-                ret;                                            \
-        })
 #else
-#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
+#define THREAD_INFO_GFP         GFP_KERNEL
 #endif
+#if THREAD_SHIFT >= PAGE_SHIFT
+#define THREAD_ORDER    (THREAD_SHIFT - PAGE_SHIFT)
+#define alloc_thread_info(tsk)  \
+        ((struct thread_info *)__get_free_pages(THREAD_INFO_GFP, THREAD_ORDER))
+#define free_thread_info(ti)    free_pages((unsigned long)ti, THREAD_ORDER)
+#else /* THREAD_SHIFT < PAGE_SHIFT */
+#define alloc_thread_info(tsk)  kmalloc(THREAD_SIZE, THREAD_INFO_GFP)
 #define free_thread_info(ti)    kfree(ti)
+#endif /* THREAD_SHIFT < PAGE_SHIFT */
 #define get_thread_info(ti)     get_task_struct((ti)->task)
 #define put_thread_info(ti)     put_task_struct((ti)->task)
 /* how to get the thread information struct from C */
 static inline struct thread_info *current_thread_info(void)
 {
-        struct thread_info *ti;
+        register unsigned long sp asm("r1");
-        __asm__("clrrdi %0,1,%1" : "=r"(ti) : "i" (THREAD_SHIFT));
-        return ti;
+        /* gcc4, at least, is smart enough to turn this into a single
+         * rlwinm for ppc32 and clrrdi for ppc64 */
+        return (struct thread_info *)(sp & ~(THREAD_SIZE-1));
 }
 #endif /* __ASSEMBLY__ */
@@ -122,4 +139,4 @@ static inline struct thread_info *current_thread_info(void)
 #endif /* __KERNEL__ */
-#endif /* _ASM_THREAD_INFO_H */
+#endif /* _ASM_POWERPC_THREAD_INFO_H */
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
new file mode 100644
index 000000000000..d9b86a17271b
--- /dev/null
+++ b/include/asm-powerpc/time.h
@@ -0,0 +1,226 @@
+/*
+ * Common time prototypes and such for all ppc machines.
+ *
+ * Written by Cort Dougan (cort@cs.nmt.edu) to merge
+ * Paul Mackerras' version and mine for PReP and Pmac.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef __POWERPC_TIME_H
+#define __POWERPC_TIME_H
+#ifdef __KERNEL__
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/percpu.h>
+#include <asm/processor.h>
+#ifdef CONFIG_PPC64
+#include <asm/paca.h>
+#include <asm/iseries/hv_call.h>
+#endif
+/* time.c */
+extern unsigned long tb_ticks_per_jiffy;
+extern unsigned long tb_ticks_per_usec;
+extern unsigned long tb_ticks_per_sec;
+extern u64 tb_to_xs;
+extern unsigned      tb_to_us;
+extern unsigned long tb_last_stamp;
+extern u64 tb_last_jiffy;
+DECLARE_PER_CPU(unsigned long, last_jiffy);
+struct rtc_time;
+extern void to_tm(int tim, struct rtc_time * tm);
+extern time_t last_rtc_update;
+extern void generic_calibrate_decr(void);
+extern void wakeup_decrementer(void);
+/* Some sane defaults: 125 MHz timebase, 1GHz processor */
+extern unsigned long ppc_proc_freq;
+#define DEFAULT_PROC_FREQ       (DEFAULT_TB_FREQ * 8)
+extern unsigned long ppc_tb_freq;
+#define DEFAULT_TB_FREQ         125000000UL
+/*
+ * By putting all of this stuff into a single struct we 
+ * reduce the number of cache lines touched by do_gettimeofday.
+ * Both by collecting all of the data in one cache line and
+ * by touching only one TOC entry on ppc64.
+ */
+struct gettimeofday_vars {
+        u64 tb_to_xs;
+        u64 stamp_xsec;
+        u64 tb_orig_stamp;
+};
+struct gettimeofday_struct {
+        unsigned long tb_ticks_per_sec;
+        struct gettimeofday_vars vars[2];
+        struct gettimeofday_vars * volatile varp;
+        unsigned      var_idx;
+        unsigned      tb_to_us;
+};
+struct div_result {
+        u64 result_high;
+        u64 result_low;
+};
+/* Accessor functions for the timebase (RTC on 601) registers. */
+/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
+#ifdef CONFIG_6xx
+#define __USE_RTC()     (!cpu_has_feature(CPU_FTR_USE_TB))
+#else
+#define __USE_RTC()     0
+#endif
+/* On ppc64 this gets us the whole timebase; on ppc32 just the lower half */
+static inline unsigned long get_tbl(void)
+{
+        unsigned long tbl;
+#if defined(CONFIG_403GCX)
+        asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
+#else
+        asm volatile("mftb %0" : "=r" (tbl));
+#endif
+        return tbl;
+}
+static inline unsigned int get_tbu(void)
+{
+        unsigned int tbu;
+#if defined(CONFIG_403GCX)
+        asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
+#else
+        asm volatile("mftbu %0" : "=r" (tbu));
+#endif
+        return tbu;
+}
+static inline unsigned int get_rtcl(void)
+{
+        unsigned int rtcl;
+        asm volatile("mfrtcl %0" : "=r" (rtcl));
+        return rtcl;
+}
+static inline u64 get_rtc(void)
+{
+        unsigned int hi, lo, hi2;
+        do {
+                asm volatile("mfrtcu %0; mfrtcl %1; mfrtcu %2"
+                             : "=r" (hi), "=r" (lo), "=r" (hi2));
+        } while (hi2 != hi);
+        return (u64)hi * 1000000000 + lo;
+}
+#ifdef CONFIG_PPC64
+static inline u64 get_tb(void)
+{
+        return mftb();
+}
+#else
+static inline u64 get_tb(void)
+{
+        unsigned int tbhi, tblo, tbhi2;
+        do {
+                tbhi = get_tbu();
+                tblo = get_tbl();
+                tbhi2 = get_tbu();
+        } while (tbhi != tbhi2);
+        return ((u64)tbhi << 32) | tblo;
+}
+#endif
+static inline void set_tb(unsigned int upper, unsigned int lower)
+{
+        mtspr(SPRN_TBWL, 0);
+        mtspr(SPRN_TBWU, upper);
+        mtspr(SPRN_TBWL, lower);
+}
+/* Accessor functions for the decrementer register.
+ * The 4xx doesn't even have a decrementer.  I tried to use the
+ * generic timer interrupt code, which seems OK, with the 4xx PIT
+ * in auto-reload mode.  The problem is PIT stops counting when it
+ * hits zero.  If it would wrap, we could use it just like a decrementer.
+ */
+static inline unsigned int get_dec(void)
+{
+#if defined(CONFIG_40x)
+        return (mfspr(SPRN_PIT));
+#else
+        return (mfspr(SPRN_DEC));
+#endif
+}
+static inline void set_dec(int val)
+{
+#if defined(CONFIG_40x)
+        return;         /* Have to let it auto-reload */
+#elif defined(CONFIG_8xx_CPU6)
+        set_dec_cpu6(val);
+#else
+#ifdef CONFIG_PPC_ISERIES
+        struct paca_struct *lpaca = get_paca();
+        int cur_dec;
+        if (lpaca->lppaca.shared_proc) {
+                lpaca->lppaca.virtual_decr = val;
+                cur_dec = get_dec();
+                if (cur_dec > val)
+                        HvCall_setVirtualDecr();
+        } else
+#endif
+                mtspr(SPRN_DEC, val);
+#endif /* not 40x or 8xx_CPU6 */
+}
+static inline unsigned long tb_ticks_since(unsigned long tstamp)
+{
+        if (__USE_RTC()) {
+                int delta = get_rtcl() - (unsigned int) tstamp;
+                return delta < 0 ? delta + 1000000000 : delta;
+        }
+        return get_tbl() - tstamp;
+}
+#define mulhwu(x,y) \
+({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
+#ifdef CONFIG_PPC64
+#define mulhdu(x,y) \
+({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
+#else
+extern u64 mulhdu(u64, u64);
+#endif
+extern void smp_space_timers(unsigned int);
+extern unsigned mulhwu_scale_factor(unsigned, unsigned);
+extern void div128_by_32(u64 dividend_high, u64 dividend_low,
+                         unsigned divisor, struct div_result *dr);
+/* Used to store Processor Utilization register (purr) values */
+struct cpu_usage {
+        u64 current_tb;  /* Holds the current purr register values */
+};
+DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
+#endif /* __KERNEL__ */
+#endif /* __PPC64_TIME_H */
diff --git a/include/asm-ppc/tlb.h b/include/asm-powerpc/tlb.h
index 2c142c5d8584..56659f121779 100644
--- a/include/asm-ppc/tlb.h
+++ b/include/asm-powerpc/tlb.h
@@ -1,6 +1,7 @@
 /*
- *      TLB shootdown specifics for PPC
+ *      TLB shootdown specifics for powerpc
 *
+ * Copyright (C) 2002 Anton Blanchard, IBM Corp.
 * Copyright (C) 2002 Paul Mackerras, IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
@@ -8,29 +9,53 @@
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
-#ifndef _PPC_TLB_H
+#ifndef _ASM_POWERPC_TLB_H
-#define _PPC_TLB_H
+#define _ASM_POWERPC_TLB_H
 #include <linux/config.h>
+#ifndef __powerpc64__
 #include <asm/pgtable.h>
+#endif
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
+#ifndef __powerpc64__
 #include <asm/page.h>
 #include <asm/mmu.h>
+#endif
-#ifdef CONFIG_PPC_STD_MMU
-/* Classic PPC with hash-table based MMU... */
 struct mmu_gather;
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma)   do { } while (0)
+#if !defined(CONFIG_PPC_STD_MMU)
+#define tlb_flush(tlb)                  flush_tlb_mm((tlb)->mm)
+#elif defined(__powerpc64__)
+extern void pte_free_finish(void);
+static inline void tlb_flush(struct mmu_gather *tlb)
+{
+        flush_tlb_pending();
+        pte_free_finish();
+}
+#else
 extern void tlb_flush(struct mmu_gather *tlb);
+#endif
 /* Get the generic bits... */
 #include <asm-generic/tlb.h>
-/* Nothing needed here in fact... */
+#if !defined(CONFIG_PPC_STD_MMU) || defined(__powerpc64__)
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma)   do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
+#else
 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
                             unsigned long address);
@@ -41,17 +66,5 @@ static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
                flush_hash_entry(tlb->mm, ptep, address);
 }
-#else
+#endif
-/* Embedded PPC with software-loaded TLB, very simple... */
+#endif /* __ASM_POWERPC_TLB_H */
-#define tlb_start_vma(tlb, vma)         do { } while (0)
-#define tlb_end_vma(tlb, vma)           do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
-#define tlb_flush(tlb)                  flush_tlb_mm((tlb)->mm)
-/* Get the generic bits... */
-#include <asm-generic/tlb.h>
-#endif /* CONFIG_PPC_STD_MMU */
-#endif /* __PPC_TLB_H */
diff --git a/include/asm-powerpc/tlbflush.h b/include/asm-powerpc/tlbflush.h
new file mode 100644
index 000000000000..ca3655672bbc
--- /dev/null
+++ b/include/asm-powerpc/tlbflush.h
@@ -0,0 +1,146 @@
+#ifndef _ASM_POWERPC_TLBFLUSH_H
+#define _ASM_POWERPC_TLBFLUSH_H
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifdef __KERNEL__
+#include <linux/config.h>
+struct mm_struct;
+#ifdef CONFIG_PPC64
+#include <linux/percpu.h>
+#include <asm/page.h>
+#define PPC64_TLB_BATCH_NR 192
+struct ppc64_tlb_batch {
+        unsigned long index;
+        struct mm_struct *mm;
+        pte_t pte[PPC64_TLB_BATCH_NR];
+        unsigned long vaddr[PPC64_TLB_BATCH_NR];
+        unsigned int large;
+};
+DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
+extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
+static inline void flush_tlb_pending(void)
+{
+        struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
+        if (batch->index)
+                __flush_tlb_pending(batch);
+        put_cpu_var(ppc64_tlb_batch);
+}
+extern void flush_hash_page(unsigned long va, pte_t pte, int local);
+void flush_hash_range(unsigned long number, int local);
+#else /* CONFIG_PPC64 */
+#include <linux/mm.h>
+extern void _tlbie(unsigned long address);
+extern void _tlbia(void);
+/*
+ * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
+ * flush_tlb_kernel_range are best implemented as tlbia vs
+ * specific tlbie's
+ */
+#if (defined(CONFIG_4xx) && !defined(CONFIG_44x)) || defined(CONFIG_8xx)
+#define flush_tlb_pending()     asm volatile ("tlbia; sync" : : : "memory")
+#elif defined(CONFIG_4xx) || defined(CONFIG_FSL_BOOKE)
+#define flush_tlb_pending()     _tlbia()
+#endif
+/*
+ * This gets called at the end of handling a page fault, when
+ * the kernel has put a new PTE into the page table for the process.
+ * We use it to ensure coherency between the i-cache and d-cache
+ * for the page which has just been mapped in.
+ * On machines which use an MMU hash table, we use this to put a
+ * corresponding HPTE into the hash table ahead of time, instead of
+ * waiting for the inevitable extra hash-table miss exception.
+ */
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+#endif /* CONFIG_PPC64 */
+#if defined(CONFIG_PPC64) || defined(CONFIG_4xx) || \
+        defined(CONFIG_FSL_BOOKE) || defined(CONFIG_8xx)
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+        flush_tlb_pending();
+}
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                unsigned long vmaddr)
+{
+#ifdef CONFIG_PPC64
+        flush_tlb_pending();
+#else
+        _tlbie(vmaddr);
+#endif
+}
+static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
+                                         unsigned long vmaddr)
+{
+#ifndef CONFIG_PPC64
+        _tlbie(vmaddr);
+#endif
+}
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+                unsigned long start, unsigned long end)
+{
+        flush_tlb_pending();
+}
+static inline void flush_tlb_kernel_range(unsigned long start,
+                unsigned long end)
+{
+        flush_tlb_pending();
+}
+#else   /* 6xx, 7xx, 7xxx cpus */
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
+extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+                            unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+#endif
+/*
+ * This is called in munmap when we have freed up some page-table
+ * pages.  We don't need to do anything here, there's nothing special
+ * about our page-table pages.  -- paulus
+ */
+static inline void flush_tlb_pgtables(struct mm_struct *mm,
+                unsigned long start, unsigned long end)
+{
+}
+#endif /*__KERNEL__ */
+#endif /* _ASM_POWERPC_TLBFLUSH_H */
diff --git a/include/asm-ppc64/types.h b/include/asm-powerpc/types.h
index bf294c1761b2..ec3c2ee8bf86 100644
--- a/include/asm-ppc64/types.h
+++ b/include/asm-powerpc/types.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_TYPES_H
+#ifndef _ASM_POWERPC_TYPES_H
-#define _PPC64_TYPES_H
+#define _ASM_POWERPC_TYPES_H
 #ifndef __ASSEMBLY__
@@ -16,7 +16,11 @@
 * 2 of the License, or (at your option) any later version.
 */
+#ifdef __powerpc64__
 typedef unsigned int umode_t;
+#else
+typedef unsigned short umode_t;
+#endif
 /*
 * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
@@ -32,8 +36,15 @@ typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
+#ifdef __powerpc64__
 typedef __signed__ long __s64;
 typedef unsigned long __u64;
+#else
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+#endif /* __powerpc64__ */
 typedef struct {
        __u32 u[4];
@@ -45,10 +56,16 @@ typedef struct {
 /*
 * These aren't exported outside the kernel to avoid name space clashes
 */
+#ifdef __powerpc64__
 #define BITS_PER_LONG 64
+#else
+#define BITS_PER_LONG 32
+#endif
 #ifndef __ASSEMBLY__
+#include <linux/config.h>
 typedef signed char s8;
 typedef unsigned char u8;
@@ -58,12 +75,21 @@ typedef unsigned short u16;
 typedef signed int s32;
 typedef unsigned int u32;
+#ifdef __powerpc64__
 typedef signed long s64;
 typedef unsigned long u64;
+#else
+typedef signed long long s64;
+typedef unsigned long long u64;
+#endif
 typedef __vector128 vector128;
+#ifdef __powerpc64__
+typedef u64 dma_addr_t;
+#else
 typedef u32 dma_addr_t;
+#endif
 typedef u64 dma64_addr_t;
 typedef struct {
@@ -72,8 +98,13 @@ typedef struct {
        unsigned long env;
 } func_descr_t;
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#define HAVE_SECTOR_T
+#endif
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
-#endif /* _PPC64_TYPES_H */
+#endif /* _ASM_POWERPC_TYPES_H */
diff --git a/include/asm-powerpc/uaccess.h b/include/asm-powerpc/uaccess.h
new file mode 100644
index 000000000000..33af730f0d19
--- /dev/null
+++ b/include/asm-powerpc/uaccess.h
@@ -0,0 +1,468 @@
+#ifndef _ARCH_POWERPC_UACCESS_H
+#define _ARCH_POWERPC_UACCESS_H
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <asm/processor.h>
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ *
+ * The fs/ds values are now the highest legal address in the "segment".
+ * This simplifies the checking in the routines below.
+ */
+#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
+#define KERNEL_DS       MAKE_MM_SEG(~0UL)
+#ifdef __powerpc64__
+/* We use TASK_SIZE_USER64 as TASK_SIZE is not constant */
+#define USER_DS         MAKE_MM_SEG(TASK_SIZE_USER64 - 1)
+#else
+#define USER_DS         MAKE_MM_SEG(TASK_SIZE - 1)
+#endif
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current->thread.fs)
+#define set_fs(val)     (current->thread.fs = (val))
+#define segment_eq(a, b)        ((a).seg == (b).seg)
+#ifdef __powerpc64__
+/*
+ * This check is sufficient because there is a large enough
+ * gap between user addresses and the kernel addresses
+ */
+#define __access_ok(addr, size, segment)        \
+        (((addr) <= (segment).seg) && ((size) <= (segment).seg))
+#else
+#define __access_ok(addr, size, segment)        \
+        (((addr) <= (segment).seg) &&           \
+         (((size) == 0) || (((size) - 1) <= ((segment).seg - (addr)))))
+#endif
+#define access_ok(type, addr, size)             \
+        (__chk_user_ptr(addr),                  \
+         __access_ok((__force unsigned long)(addr), (size), get_fs()))
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+struct exception_table_entry {
+        unsigned long insn;
+        unsigned long fixup;
+};
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on the
+ * PowerPC, we can just do these as direct assignments.  (Of course, the
+ * exception handling means that it's no longer "just"...)
+ *
+ * The "user64" versions of the user access functions are versions that
+ * allow access of 64-bit data. The "get_user" functions do not
+ * properly handle 64-bit data because the value gets down cast to a long.
+ * The "put_user" functions already handle 64-bit data properly but we add
+ * "user64" versions for completeness
+ */
+#define get_user(x, ptr) \
+        __get_user_check((x), (ptr), sizeof(*(ptr)))
+#define put_user(x, ptr) \
+        __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
+#define __get_user(x, ptr) \
+        __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+#define __put_user(x, ptr) \
+        __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
+#ifndef __powerpc64__
+#define __get_user64(x, ptr) \
+        __get_user64_nocheck((x), (ptr), sizeof(*(ptr)))
+#define __put_user64(x, ptr) __put_user(x, ptr)
+#endif
+#define __get_user_unaligned __get_user
+#define __put_user_unaligned __put_user
+extern long __put_user_bad(void);
+#ifdef __powerpc64__
+#define __EX_TABLE_ALIGN        "3"
+#define __EX_TABLE_TYPE         "llong"
+#else
+#define __EX_TABLE_ALIGN        "2"
+#define __EX_TABLE_TYPE         "long"
+#endif
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memory gcc knows about, so there
+ * are no aliasing issues.
+ */
+#define __put_user_asm(x, addr, err, op)                        \
+        __asm__ __volatile__(                                   \
+                "1:     " op " %1,0(%2) # put_user\n"           \
+                "2:\n"                                          \
+                ".section .fixup,\"ax\"\n"                      \
+                "3:     li %0,%3\n"                             \
+                "       b 2b\n"                                 \
+                ".previous\n"                                   \
+                ".section __ex_table,\"a\"\n"                   \
+                "       .align " __EX_TABLE_ALIGN "\n"          \
+                "       ."__EX_TABLE_TYPE" 1b,3b\n"             \
+                ".previous"                                     \
+                : "=r" (err)                                    \
+                : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
+#ifdef __powerpc64__
+#define __put_user_asm2(x, ptr, retval)                         \
+          __put_user_asm(x, ptr, retval, "std")
+#else /* __powerpc64__ */
+#define __put_user_asm2(x, addr, err)                           \
+        __asm__ __volatile__(                                   \
+                "1:     stw %1,0(%2)\n"                         \
+                "2:     stw %1+1,4(%2)\n"                       \
+                "3:\n"                                          \
+                ".section .fixup,\"ax\"\n"                      \
+                "4:     li %0,%3\n"                             \
+                "       b 3b\n"                                 \
+                ".previous\n"                                   \
+                ".section __ex_table,\"a\"\n"                   \
+                "       .align " __EX_TABLE_ALIGN "\n"          \
+                "       ." __EX_TABLE_TYPE " 1b,4b\n"           \
+                "       ." __EX_TABLE_TYPE " 2b,4b\n"           \
+                ".previous"                                     \
+                : "=r" (err)                                    \
+                : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
+#endif /* __powerpc64__ */
+#define __put_user_size(x, ptr, size, retval)                   \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+          case 1: __put_user_asm(x, ptr, retval, "stb"); break; \
+          case 2: __put_user_asm(x, ptr, retval, "sth"); break; \
+          case 4: __put_user_asm(x, ptr, retval, "stw"); break; \
+          case 8: __put_user_asm2(x, ptr, retval); break;       \
+          default: __put_user_bad();                            \
+        }                                                       \
+} while (0)
+#define __put_user_nocheck(x, ptr, size)                        \
+({                                                              \
+        long __pu_err;                                          \
+        might_sleep();                                          \
+        __chk_user_ptr(ptr);                                    \
+        __put_user_size((x), (ptr), (size), __pu_err);          \
+        __pu_err;                                               \
+})
+#define __put_user_check(x, ptr, size)                                  \
+({                                                                      \
+        long __pu_err = -EFAULT;                                        \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
+        might_sleep();                                                  \
+        if (access_ok(VERIFY_WRITE, __pu_addr, size))                   \
+                __put_user_size((x), __pu_addr, (size), __pu_err);      \
+        __pu_err;                                                       \
+})
+extern long __get_user_bad(void);
+#define __get_user_asm(x, addr, err, op)                \
+        __asm__ __volatile__(                           \
+                "1:     "op" %1,0(%2)   # get_user\n"   \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li %0,%3\n"                     \
+                "       li %1,0\n"                      \
+                "       b 2b\n"                         \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align "__EX_TABLE_ALIGN "\n"   \
+                "       ." __EX_TABLE_TYPE " 1b,3b\n"   \
+                ".previous"                             \
+                : "=r" (err), "=r" (x)                  \
+                : "b" (addr), "i" (-EFAULT), "0" (err))
+#ifdef __powerpc64__
+#define __get_user_asm2(x, addr, err)                   \
+        __get_user_asm(x, addr, err, "ld")
+#else /* __powerpc64__ */
+#define __get_user_asm2(x, addr, err)                   \
+        __asm__ __volatile__(                           \
+                "1:     lwz %1,0(%2)\n"                 \
+                "2:     lwz %1+1,4(%2)\n"               \
+                "3:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "4:     li %0,%3\n"                     \
+                "       li %1,0\n"                      \
+                "       li %1+1,0\n"                    \
+                "       b 3b\n"                         \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align " __EX_TABLE_ALIGN "\n"  \
+                "       ." __EX_TABLE_TYPE " 1b,4b\n"   \
+                "       ." __EX_TABLE_TYPE " 2b,4b\n"   \
+                ".previous"                             \
+                : "=r" (err), "=&r" (x)                 \
+                : "b" (addr), "i" (-EFAULT), "0" (err))
+#endif /* __powerpc64__ */
+#define __get_user_size(x, ptr, size, retval)                   \
+do {                                                            \
+        retval = 0;                                             \
+        __chk_user_ptr(ptr);                                    \
+        if (size > sizeof(x))                                   \
+                (x) = __get_user_bad();                         \
+        switch (size) {                                         \
+        case 1: __get_user_asm(x, ptr, retval, "lbz"); break;   \
+        case 2: __get_user_asm(x, ptr, retval, "lhz"); break;   \
+        case 4: __get_user_asm(x, ptr, retval, "lwz"); break;   \
+        case 8: __get_user_asm2(x, ptr, retval);  break;        \
+        default: (x) = __get_user_bad();                        \
+        }                                                       \
+} while (0)
+#define __get_user_nocheck(x, ptr, size)                        \
+({                                                              \
+        long __gu_err;                                          \
+        unsigned long __gu_val;                                 \
+        __chk_user_ptr(ptr);                                    \
+        might_sleep();                                          \
+        __get_user_size(__gu_val, (ptr), (size), __gu_err);     \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+#ifndef __powerpc64__
+#define __get_user64_nocheck(x, ptr, size)                      \
+({                                                              \
+        long __gu_err;                                          \
+        long long __gu_val;                                     \
+        __chk_user_ptr(ptr);                                    \
+        might_sleep();                                          \
+        __get_user_size(__gu_val, (ptr), (size), __gu_err);     \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+#endif /* __powerpc64__ */
+#define __get_user_check(x, ptr, size)                                  \
+({                                                                      \
+        long __gu_err = -EFAULT;                                        \
+        unsigned long  __gu_val = 0;                                    \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);             \
+        might_sleep();                                                  \
+        if (access_ok(VERIFY_READ, __gu_addr, (size)))                  \
+                __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                             \
+        __gu_err;                                                       \
+})
+/* more complex routines */
+extern unsigned long __copy_tofrom_user(void __user *to,
+                const void __user *from, unsigned long size);
+#ifndef __powerpc64__
+extern inline unsigned long copy_from_user(void *to,
+                const void __user *from, unsigned long n)
+{
+        unsigned long over;
+        if (access_ok(VERIFY_READ, from, n))
+                return __copy_tofrom_user((__force void __user *)to, from, n);
+        if ((unsigned long)from < TASK_SIZE) {
+                over = (unsigned long)from + n - TASK_SIZE;
+                return __copy_tofrom_user((__force void __user *)to, from,
+                                n - over) + over;
+        }
+        return n;
+}
+extern inline unsigned long copy_to_user(void __user *to,
+                const void *from, unsigned long n)
+{
+        unsigned long over;
+        if (access_ok(VERIFY_WRITE, to, n))
+                return __copy_tofrom_user(to, (__force void __user *)from, n);
+        if ((unsigned long)to < TASK_SIZE) {
+                over = (unsigned long)to + n - TASK_SIZE;
+                return __copy_tofrom_user(to, (__force void __user *)from,
+                                n - over) + over;
+        }
+        return n;
+}
+#else /* __powerpc64__ */
+#define __copy_in_user(to, from, size) \
+        __copy_tofrom_user((to), (from), (size))
+extern unsigned long copy_from_user(void *to, const void __user *from,
+                                    unsigned long n);
+extern unsigned long copy_to_user(void __user *to, const void *from,
+                                  unsigned long n);
+extern unsigned long copy_in_user(void __user *to, const void __user *from,
+                                  unsigned long n);
+#endif /* __powerpc64__ */
+static inline unsigned long __copy_from_user_inatomic(void *to,
+                const void __user *from, unsigned long n)
+{
+        if (__builtin_constant_p(n) && (n <= 8)) {
+                unsigned long ret;
+                switch (n) {
+                case 1:
+                        __get_user_size(*(u8 *)to, from, 1, ret);
+                        break;
+                case 2:
+                        __get_user_size(*(u16 *)to, from, 2, ret);
+                        break;
+                case 4:
+                        __get_user_size(*(u32 *)to, from, 4, ret);
+                        break;
+                case 8:
+                        __get_user_size(*(u64 *)to, from, 8, ret);
+                        break;
+                }
+                if (ret == 0)
+                        return 0;
+        }
+        return __copy_tofrom_user((__force void __user *)to, from, n);
+}
+static inline unsigned long __copy_to_user_inatomic(void __user *to,
+                const void *from, unsigned long n)
+{
+        if (__builtin_constant_p(n) && (n <= 8)) {
+                unsigned long ret;
+                switch (n) {
+                case 1:
+                        __put_user_size(*(u8 *)from, (u8 __user *)to, 1, ret);
+                        break;
+                case 2:
+                        __put_user_size(*(u16 *)from, (u16 __user *)to, 2, ret);
+                        break;
+                case 4:
+                        __put_user_size(*(u32 *)from, (u32 __user *)to, 4, ret);
+                        break;
+                case 8:
+                        __put_user_size(*(u64 *)from, (u64 __user *)to, 8, ret);
+                        break;
+                }
+                if (ret == 0)
+                        return 0;
+        }
+        return __copy_tofrom_user(to, (__force const void __user *)from, n);
+}
+static inline unsigned long __copy_from_user(void *to,
+                const void __user *from, unsigned long size)
+{
+        might_sleep();
+        return __copy_from_user_inatomic(to, from, size);
+}
+static inline unsigned long __copy_to_user(void __user *to,
+                const void *from, unsigned long size)
+{
+        might_sleep();
+        return __copy_to_user_inatomic(to, from, size);
+}
+extern unsigned long __clear_user(void __user *addr, unsigned long size);
+static inline unsigned long clear_user(void __user *addr, unsigned long size)
+{
+        might_sleep();
+        if (likely(access_ok(VERIFY_WRITE, addr, size)))
+                return __clear_user(addr, size);
+        if ((unsigned long)addr < TASK_SIZE) {
+                unsigned long over = (unsigned long)addr + size - TASK_SIZE;
+                return __clear_user(addr, size - over) + over;
+        }
+        return size;
+}
+extern int __strncpy_from_user(char *dst, const char __user *src, long count);
+static inline long strncpy_from_user(char *dst, const char __user *src,
+                long count)
+{
+        might_sleep();
+        if (likely(access_ok(VERIFY_READ, src, 1)))
+                return __strncpy_from_user(dst, src, count);
+        return -EFAULT;
+}
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 for error
+ */
+extern int __strnlen_user(const char __user *str, long len, unsigned long top);
+/*
+ * Returns the length of the string at str (including the null byte),
+ * or 0 if we hit a page we can't access,
+ * or something > len if we didn't find a null byte.
+ *
+ * The `top' parameter to __strnlen_user is to make sure that
+ * we can never overflow from the user area into kernel space.
+ */
+static inline int strnlen_user(const char __user *str, long len)
+{
+        unsigned long top = current->thread.fs.seg;
+        if ((unsigned long)str > top)
+                return 0;
+        return __strnlen_user(str, len, top);
+}
+#define strlen_user(str)        strnlen_user((str), 0x7ffffffe)
+#endif  /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif  /* _ARCH_POWERPC_UACCESS_H */
diff --git a/include/asm-powerpc/ucontext.h b/include/asm-powerpc/ucontext.h
new file mode 100644
index 000000000000..d9a4ddf0cc86
--- /dev/null
+++ b/include/asm-powerpc/ucontext.h
@@ -0,0 +1,40 @@
+#ifndef _ASM_POWERPC_UCONTEXT_H
+#define _ASM_POWERPC_UCONTEXT_H
+#ifdef __powerpc64__
+#include <asm/sigcontext.h>
+#else
+#include <asm/elf.h>
+#endif
+#include <asm/signal.h>
+#ifndef __powerpc64__
+struct mcontext {
+        elf_gregset_t   mc_gregs;
+        elf_fpregset_t  mc_fregs;
+        unsigned long   mc_pad[2];
+        elf_vrregset_t  mc_vregs __attribute__((__aligned__(16)));
+};
+#endif
+struct ucontext {
+        unsigned long   uc_flags;
+        struct ucontext __user *uc_link;
+        stack_t         uc_stack;
+#ifndef __powerpc64__
+        int             uc_pad[7];
+        struct mcontext __user *uc_regs;/* points to uc_mcontext field */
+#endif
+        sigset_t        uc_sigmask;
+        /* glibc has 1024-bit signal masks, ours are 64-bit */
+#ifdef __powerpc64__
+        sigset_t        __unused[15];   /* Allow for uc_sigmask growth */
+        struct sigcontext uc_mcontext;  /* last for extensibility */
+#else
+        int             uc_maskext[30];
+        int             uc_pad2[3];
+        struct mcontext uc_mcontext;
+#endif
+};
+#endif /* _ASM_POWERPC_UCONTEXT_H */
diff --git a/include/asm-ppc/uninorth.h b/include/asm-powerpc/uninorth.h
index f737732c3861..f737732c3861 100644
--- a/include/asm-ppc/uninorth.h
+++ b/include/asm-powerpc/uninorth.h
diff --git a/include/asm-ppc/unistd.h b/include/asm-powerpc/unistd.h
index 3173ab3d2eb9..0991dfceef1d 100644
--- a/include/asm-ppc/unistd.h
+++ b/include/asm-powerpc/unistd.h
@@ -3,7 +3,13 @@
 /*
 * This file contains the system call numbers.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
 */
 #define __NR_restart_syscall      0
 #define __NR_exit                 1
 #define __NR_fork                 2
@@ -196,19 +202,23 @@
 #define __NR_vfork              189
 #define __NR_ugetrlimit         190     /* SuS compliant getrlimit */
 #define __NR_readahead          191
+#ifndef __powerpc64__                   /* these are 32-bit only */
 #define __NR_mmap2              192
 #define __NR_truncate64         193
 #define __NR_ftruncate64        194
 #define __NR_stat64             195
 #define __NR_lstat64            196
 #define __NR_fstat64            197
+#endif
 #define __NR_pciconfig_read     198
 #define __NR_pciconfig_write    199
 #define __NR_pciconfig_iobase   200
 #define __NR_multiplexer        201
 #define __NR_getdents64         202
 #define __NR_pivot_root         203
+#ifndef __powerpc64__
 #define __NR_fcntl64            204
+#endif
 #define __NR_madvise            205
 #define __NR_mincore            206
 #define __NR_gettid             207
@@ -230,7 +240,9 @@
 #define __NR_sched_getaffinity  223
 /* 224 currently unused */
 #define __NR_tuxcall            225
+#ifndef __powerpc64__
 #define __NR_sendfile64         226
+#endif
 #define __NR_io_setup           227
 #define __NR_io_destroy         228
 #define __NR_io_getevents       229
@@ -258,14 +270,16 @@
 #define __NR_utimes             251
 #define __NR_statfs64           252
 #define __NR_fstatfs64          253
+#ifndef __powerpc64__
 #define __NR_fadvise64_64       254
+#endif
 #define __NR_rtas               255
 #define __NR_sys_debug_setcontext 256
 /* Number 257 is reserved for vserver */
 /* 258 currently unused */
-/* Number 259 is reserved for new sys_mbind */
+#define __NR_mbind              259
-/* Number 260 is reserved for new sys_get_mempolicy */
+#define __NR_get_mempolicy      260
-/* Number 261 is reserved for new sys_set_mempolicy */
+#define __NR_set_mempolicy      261
 #define __NR_mq_open            262
 #define __NR_mq_unlink          263
 #define __NR_mq_timedsend       264
@@ -285,7 +299,12 @@
 #define __NR_syscalls           278
-#define __NR(n) #n
+#ifdef __KERNEL__
+#define __NR__exit __NR_exit
+#define NR_syscalls     __NR_syscalls
+#endif
+#ifndef __ASSEMBLY__
 /* On powerpc a system call basically clobbers the same registers like a
 * function call, with the exception of LR (which is needed for the
@@ -389,7 +408,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5)	\
 {                                                                       \
        __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5);      \
 }
 #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
 type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \
 {                                                                       \
@@ -398,12 +416,13 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 #ifdef __KERNEL__
-#define __NR__exit __NR_exit
+#include <linux/config.h>
-#define NR_syscalls     __NR_syscalls
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <linux/linkage.h>
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
@@ -423,23 +442,17 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 #define __ARCH_WANT_SYS_SIGPENDING
 #define __ARCH_WANT_SYS_SIGPROCMASK
 #define __ARCH_WANT_SYS_RT_SIGACTION
+#ifdef CONFIG_PPC32
-/*
+#define __ARCH_WANT_OLD_STAT
- * Forking from kernel space will result in the child getting a new,
+#endif
- * empty kernel stack area.  Thus the child cannot access automatic
+#ifdef CONFIG_PPC64
- * variables set in the parent unless they are in registers, and the
+#define __ARCH_WANT_COMPAT_SYS_TIME
- * procedure where the fork was done cannot return to its caller in
+#endif
- * the child.
- */
-#ifdef __KERNEL_SYSCALLS__
-#include <linux/compiler.h>
-#include <linux/types.h>
 /*
 * System call prototypes.
 */
+#ifdef __KERNEL_SYSCALLS__
 extern pid_t setsid(void);
 extern int write(int fd, const char *buf, off_t count);
 extern int read(int fd, char *buf, off_t count);
@@ -449,10 +462,13 @@ extern int execve(const char *file, char **argv, char **envp);
 extern int open(const char *file, int flag, int mode);
 extern int close(int fd);
 extern pid_t waitpid(pid_t pid, int *wait_stat, int options);
+#endif /* __KERNEL_SYSCALLS__ */
-unsigned long sys_mmap(unsigned long addr, size_t len,
+/*
-                        unsigned long prot, unsigned long flags,
+ * Functions that implement syscalls.
-                        unsigned long fd, off_t offset);
+ */
+unsigned long sys_mmap(unsigned long addr, size_t len, unsigned long prot,
+                       unsigned long flags, unsigned long fd, off_t offset);
 unsigned long sys_mmap2(unsigned long addr, size_t len,
                        unsigned long prot, unsigned long flags,
                        unsigned long fd, unsigned long pgoff);
@@ -461,22 +477,18 @@ int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
                unsigned long a3, unsigned long a4, unsigned long a5,
                struct pt_regs *regs);
 int sys_clone(unsigned long clone_flags, unsigned long usp,
-              int __user *parent_tidp, void __user *child_threadptr,
+                int __user *parent_tidp, void __user *child_threadptr,
-              int __user *child_tidp, int p6,
+                int __user *child_tidp, int p6, struct pt_regs *regs);
-              struct pt_regs *regs);
+int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
-int sys_fork(int p1, int p2, int p3, int p4, int p5, int p6,
+                unsigned long p4, unsigned long p5, unsigned long p6,
                struct pt_regs *regs);
-int sys_vfork(int p1, int p2, int p3, int p4, int p5, int p6,
+int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
+                unsigned long p4, unsigned long p5, unsigned long p6,
                struct pt_regs *regs);
 int sys_pipe(int __user *fildes);
-int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
-long sys_rt_sigaction(int sig,
+long sys_rt_sigaction(int sig, const struct sigaction __user *act,
-                      const struct sigaction __user *act,
+                      struct sigaction __user *oact, size_t sigsetsize);
-                      struct sigaction __user *oact,
-                      size_t sigsetsize);
-#endif /* __KERNEL_SYSCALLS__ */
 /*
 * "Conditional" syscalls
@@ -484,10 +496,14 @@ long sys_rt_sigaction(int sig,
 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
 * but it doesn't work on all toolchains, so we just do it by hand
 */
-#ifndef cond_syscall
+#ifdef CONFIG_PPC32
 #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+#else
+#define cond_syscall(x) asm(".weak\t." #x "\n\t.set\t." #x ",.sys_ni_syscall")
 #endif
-#endif /* __KERNEL__ */
+#endif          /* __KERNEL__ */
+#endif          /* __ASSEMBLY__ */
 #endif /* _ASM_PPC_UNISTD_H_ */
diff --git a/include/asm-ppc64/vga.h b/include/asm-powerpc/vga.h
index c09849743f45..f8d350aabf1a 100644
--- a/include/asm-ppc64/vga.h
+++ b/include/asm-powerpc/vga.h
@@ -1,16 +1,14 @@
+#ifndef _ASM_POWERPC_VGA_H_
+#define _ASM_POWERPC_VGA_H_
+#ifdef __KERNEL__
 /*
 *      Access to VGA videoram
 *
 *      (c) 1998 Martin Mares <mj@ucw.cz>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
 */
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
 #include <asm/io.h>
@@ -42,9 +40,15 @@ static inline u16 scr_readw(volatile const u16 *addr)
 #endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
 extern unsigned long vgacon_remap_base;
+#ifdef __powerpc64__
 #define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0))
+#else
+#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
+#endif
 #define vga_readb(x) (*(x))
 #define vga_writeb(x,y) (*(y) = (x))
-#endif
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_VGA_H_ */
diff --git a/include/asm-ppc64/vio.h b/include/asm-powerpc/vio.h
index 03f1b95f433b..e0ccf108277c 100644
--- a/include/asm-ppc64/vio.h
+++ b/include/asm-powerpc/vio.h
@@ -1,18 +1,18 @@
 /*
 * IBM PowerPC Virtual I/O Infrastructure Support.
 *
- *    Copyright (c) 2003 IBM Corp.
+ * Copyright (c) 2003 IBM Corp.
- *     Dave Engebretsen engebret@us.ibm.com
+ *  Dave Engebretsen engebret@us.ibm.com
- *     Santiago Leon santil@us.ibm.com
+ *  Santiago Leon santil@us.ibm.com
 *
- *      This program is free software; you can redistribute it and/or
+ * This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
+ * modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
+ * as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
+ * 2 of the License, or (at your option) any later version.
 */
-#ifndef _ASM_VIO_H
+#ifndef _ASM_POWERPC_VIO_H
-#define _ASM_VIO_H
+#define _ASM_POWERPC_VIO_H
 #include <linux/config.h>
 #include <linux/init.h>
@@ -55,10 +55,10 @@ struct vio_dev {
 struct vio_driver {
        struct list_head node;
-        char *name;
        const struct vio_device_id *id_table;
        int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
        int (*remove)(struct vio_dev *dev);
+        void (*shutdown)(struct vio_dev *dev);
        unsigned long driver_data;
        struct device_driver driver;
 };
@@ -103,4 +103,4 @@ static inline struct vio_dev *to_vio_dev(struct device *dev)
        return container_of(dev, struct vio_dev, dev);
 }
-#endif /* _ASM_VIO_H */
+#endif /* _ASM_POWERPC_VIO_H */
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
new file mode 100644
index 000000000000..43f7129984c7
--- /dev/null
+++ b/include/asm-powerpc/xmon.h
@@ -0,0 +1,12 @@
+#ifndef __PPC_XMON_H
+#define __PPC_XMON_H
+#ifdef __KERNEL__
+struct pt_regs;
+extern int xmon(struct pt_regs *excp);
+extern void xmon_printf(const char *fmt, ...);
+extern void xmon_init(int);
+#endif
+#endif
diff --git a/include/asm-ppc/a.out.h b/include/asm-ppc/a.out.h
deleted file mode 100644
index 8979a94c4a81..000000000000
--- a/include/asm-ppc/a.out.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __PPC_A_OUT_H__
-#define __PPC_A_OUT_H__
-/* grabbed from the intel stuff  */
-#define STACK_TOP TASK_SIZE
-struct exec
-{
-  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
-  unsigned a_text;              /* length of text, in bytes */
-  unsigned a_data;              /* length of data, in bytes */
-  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
-  unsigned a_syms;              /* length of symbol table data in file, in bytes */
-  unsigned a_entry;             /* start address */
-  unsigned a_trsize;            /* length of relocation info for text, in bytes */
-  unsigned a_drsize;            /* length of relocation info for data, in bytes */
-};
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-#endif
diff --git a/include/asm-ppc/auxvec.h b/include/asm-ppc/auxvec.h
deleted file mode 100644
index 172358df29c8..000000000000
--- a/include/asm-ppc/auxvec.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __PPC_AUXVEC_H
-#define __PPC_AUXVEC_H
-/*
- * We need to put in some extra aux table entries to tell glibc what
- * the cache block size is, so it can use the dcbz instruction safely.
- */
-#define AT_DCACHEBSIZE          19
-#define AT_ICACHEBSIZE          20
-#define AT_UCACHEBSIZE          21
-/* A special ignored type value for PPC, for glibc compatibility.  */
-#define AT_IGNOREPPC            22
-#endif
diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h
deleted file mode 100644
index e30f536fd830..000000000000
--- a/include/asm-ppc/bitops.h
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * bitops.h: Bit string operations on the ppc
- */
-#ifdef __KERNEL__
-#ifndef _PPC_BITOPS_H
-#define _PPC_BITOPS_H
-#include <linux/config.h>
-#include <linux/compiler.h>
-#include <asm/byteorder.h>
-#include <asm/atomic.h>
-/*
- * The test_and_*_bit operations are taken to imply a memory barrier
- * on SMP systems.
- */
-#ifdef CONFIG_SMP
-#define SMP_WMB         "eieio\n"
-#define SMP_MB          "\nsync"
-#else
-#define SMP_WMB
-#define SMP_MB
-#endif /* CONFIG_SMP */
-static __inline__ void set_bit(int nr, volatile unsigned long * addr)
-{
-        unsigned long old;
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        
-        __asm__ __volatile__("\n\
-1:      lwarx   %0,0,%3 \n\
-        or      %0,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-"       stwcx.  %0,0,%3 \n\
-        bne-    1b"
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc" );
-}
-/*
- * non-atomic version
- */
-static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        *p |= mask;
-}
-/*
- * clear_bit doesn't imply a memory barrier
- */
-#define smp_mb__before_clear_bit()      smp_mb()
-#define smp_mb__after_clear_bit()       smp_mb()
-static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned long old;
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        __asm__ __volatile__("\n\
-1:      lwarx   %0,0,%3 \n\
-        andc    %0,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-"       stwcx.  %0,0,%3 \n\
-        bne-    1b"
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-}
-/*
- * non-atomic version
- */
-static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        *p &= ~mask;
-}
-static __inline__ void change_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned long old;
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        __asm__ __volatile__("\n\
-1:      lwarx   %0,0,%3 \n\
-        xor     %0,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-"       stwcx.  %0,0,%3 \n\
-        bne-    1b"
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-}
-/*
- * non-atomic version
- */
-static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        *p ^= mask;
-}
-/*
- * test_and_*_bit do imply a memory barrier (?)
- */
-static __inline__ int test_and_set_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned int old, t;
-        unsigned int mask = 1 << (nr & 0x1f);
-        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%4 \n\
-        or      %1,%0,%3 \n"
-        PPC405_ERR77(0,%4)
-"       stwcx.  %1,0,%4 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=&r" (t), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc", "memory");
-        return (old & mask) != 0;
-}
-/*
- * non-atomic version
- */
-static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        unsigned long old = *p;
-        *p = old | mask;
-        return (old & mask) != 0;
-}
-static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned int old, t;
-        unsigned int mask = 1 << (nr & 0x1f);
-        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%4 \n\
-        andc    %1,%0,%3 \n"
-        PPC405_ERR77(0,%4)
-"       stwcx.  %1,0,%4 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=&r" (t), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc", "memory");
-        return (old & mask) != 0;
-}
-/*
- * non-atomic version
- */
-static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        unsigned long old = *p;
-        *p = old & ~mask;
-        return (old & mask) != 0;
-}
-static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned int old, t;
-        unsigned int mask = 1 << (nr & 0x1f);
-        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%4 \n\
-        xor     %1,%0,%3 \n"
-        PPC405_ERR77(0,%4)
-"       stwcx.  %1,0,%4 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=&r" (t), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc", "memory");
-        return (old & mask) != 0;
-}
-/*
- * non-atomic version
- */
-static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        unsigned long old = *p;
-        *p = old ^ mask;
-        return (old & mask) != 0;
-}
-static __inline__ int test_bit(int nr, __const__ volatile unsigned long *addr)
-{
-        return ((addr[nr >> 5] >> (nr & 0x1f)) & 1) != 0;
-}
-/* Return the bit position of the most significant 1 bit in a word */
-static __inline__ int __ilog2(unsigned long x)
-{
-        int lz;
-        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
-        return 31 - lz;
-}
-static __inline__ int ffz(unsigned long x)
-{
-        if ((x = ~x) == 0)
-                return 32;
-        return __ilog2(x & -x);
-}
-static inline int __ffs(unsigned long x)
-{
-        return __ilog2(x & -x);
-}
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int ffs(int x)
-{
-        return __ilog2(x & -x) + 1;
-}
-/*
- * fls: find last (most-significant) bit set.
- * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
- */
-static __inline__ int fls(unsigned int x)
-{
-        int lz;
-        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
-        return 32 - lz;
-}
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-/*
- * Find the first bit set in a 140-bit bitmap.
- * The first 100 bits are unlikely to be set.
- */
-static inline int sched_find_first_bit(const unsigned long *b)
-{
-        if (unlikely(b[0]))
-                return __ffs(b[0]);
-        if (unlikely(b[1]))
-                return __ffs(b[1]) + 32;
-        if (unlikely(b[2]))
-                return __ffs(b[2]) + 64;
-        if (b[3])
-                return __ffs(b[3]) + 96;
-        return __ffs(b[4]) + 128;
-}
-/**
- * find_next_bit - find the next set bit in a memory region
- * @addr: The address to base the search on
- * @offset: The bitnumber to start searching at
- * @size: The maximum size to search
- */
-static __inline__ unsigned long find_next_bit(const unsigned long *addr,
-        unsigned long size, unsigned long offset)
-{
-        unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
-        unsigned int result = offset & ~31UL;
-        unsigned int tmp;
-        if (offset >= size)
-                return size;
-        size -= result;
-        offset &= 31UL;
-        if (offset) {
-                tmp = *p++;
-                tmp &= ~0UL << offset;
-                if (size < 32)
-                        goto found_first;
-                if (tmp)
-                        goto found_middle;
-                size -= 32;
-                result += 32;
-        }
-        while (size >= 32) {
-                if ((tmp = *p++) != 0)
-                        goto found_middle;
-                result += 32;
-                size -= 32;
-        }
-        if (!size)
-                return result;
-        tmp = *p;
-found_first:
-        tmp &= ~0UL >> (32 - size);
-        if (tmp == 0UL)        /* Are any bits set? */
-                return result + size; /* Nope. */
-found_middle:
-        return result + __ffs(tmp);
-}
-/**
- * find_first_bit - find the first set bit in a memory region
- * @addr: The address to start the search at
- * @size: The maximum size to search
- *
- * Returns the bit-number of the first set bit, not the number of the byte
- * containing a bit.
- */
-#define find_first_bit(addr, size) \
-        find_next_bit((addr), (size), 0)
-/*
- * This implementation of find_{first,next}_zero_bit was stolen from
- * Linus' asm-alpha/bitops.h.
- */
-#define find_first_zero_bit(addr, size) \
-        find_next_zero_bit((addr), (size), 0)
-static __inline__ unsigned long find_next_zero_bit(const unsigned long *addr,
-        unsigned long size, unsigned long offset)
-{
-        unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
-        unsigned int result = offset & ~31UL;
-        unsigned int tmp;
-        if (offset >= size)
-                return size;
-        size -= result;
-        offset &= 31UL;
-        if (offset) {
-                tmp = *p++;
-                tmp |= ~0UL >> (32-offset);
-                if (size < 32)
-                        goto found_first;
-                if (tmp != ~0U)
-                        goto found_middle;
-                size -= 32;
-                result += 32;
-        }
-        while (size >= 32) {
-                if ((tmp = *p++) != ~0U)
-                        goto found_middle;
-                result += 32;
-                size -= 32;
-        }
-        if (!size)
-                return result;
-        tmp = *p;
-found_first:
-        tmp |= ~0UL << size;
-        if (tmp == ~0UL)        /* Are any bits zero? */
-                return result + size; /* Nope. */
-found_middle:
-        return result + ffz(tmp);
-}
-#define ext2_set_bit(nr, addr)  __test_and_set_bit((nr) ^ 0x18, (unsigned long *)(addr))
-#define ext2_set_bit_atomic(lock, nr, addr)  test_and_set_bit((nr) ^ 0x18, (unsigned long *)(addr))
-#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 0x18, (unsigned long *)(addr))
-#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 0x18, (unsigned long *)(addr))
-static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
-{
-        __const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
-        return (ADDR[nr >> 3] >> (nr & 7)) & 1;
-}
-/*
- * This implementation of ext2_find_{first,next}_zero_bit was stolen from
- * Linus' asm-alpha/bitops.h and modified for a big-endian machine.
- */
-#define ext2_find_first_zero_bit(addr, size) \
-        ext2_find_next_zero_bit((addr), (size), 0)
-static __inline__ unsigned long ext2_find_next_zero_bit(const void *addr,
-        unsigned long size, unsigned long offset)
-{
-        unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
-        unsigned int result = offset & ~31UL;
-        unsigned int tmp;
-        if (offset >= size)
-                return size;
-        size -= result;
-        offset &= 31UL;
-        if (offset) {
-                tmp = cpu_to_le32p(p++);
-                tmp |= ~0UL >> (32-offset);
-                if (size < 32)
-                        goto found_first;
-                if (tmp != ~0U)
-                        goto found_middle;
-                size -= 32;
-                result += 32;
-        }
-        while (size >= 32) {
-                if ((tmp = cpu_to_le32p(p++)) != ~0U)
-                        goto found_middle;
-                result += 32;
-                size -= 32;
-        }
-        if (!size)
-                return result;
-        tmp = cpu_to_le32p(p);
-found_first:
-        tmp |= ~0U << size;
-        if (tmp == ~0UL)        /* Are any bits zero? */
-                return result + size; /* Nope. */
-found_middle:
-        return result + ffz(tmp);
-}
-/* Bitmap functions for the minix filesystem.  */
-#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
-#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
-#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr)
-#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr)
-#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size)
-#endif /* _PPC_BITOPS_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h
deleted file mode 100644
index 8b34fd682b0d..000000000000
--- a/include/asm-ppc/bug.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PPC_BUG_H
-#define _PPC_BUG_H
-struct bug_entry {
-        unsigned long   bug_addr;
-        int             line;
-        const char      *file;
-        const char      *function;
-};
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP        0x1000000
-#ifdef CONFIG_BUG
-#define BUG() do {                                                       \
-        __asm__ __volatile__(                                            \
-                "1:     twi 31,0,0\n"                                    \
-                ".section __bug_table,\"a\"\n\t"                         \
-                "       .long 1b,%0,%1,%2\n"                             \
-                ".previous"                                              \
-                : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-#define BUG_ON(x) do {                                                  \
-        if (!__builtin_constant_p(x) || (x)) {                          \
-                __asm__ __volatile__(                                   \
-                        "1:     twnei %0,0\n"                           \
-                        ".section __bug_table,\"a\"\n\t"                \
-                        "       .long 1b,%1,%2,%3\n"                    \
-                        ".previous"                                     \
-                        : : "r" (x), "i" (__LINE__), "i" (__FILE__),    \
-                            "i" (__FUNCTION__));                        \
-        }                                                               \
-} while (0)
-#define WARN_ON(x) do {                                                 \
-        if (!__builtin_constant_p(x) || (x)) {                          \
-                __asm__ __volatile__(                                   \
-                        "1:     twnei %0,0\n"                           \
-                        ".section __bug_table,\"a\"\n\t"                \
-                        "       .long 1b,%1,%2,%3\n"                    \
-                        ".previous"                                     \
-                        : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
-                            "i" (__FILE__), "i" (__FUNCTION__));        \
-        }                                                               \
-} while (0)
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif
-#include <asm-generic/bug.h>
-#endif
diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h
deleted file mode 100644
index c63c81ec7968..000000000000
--- a/include/asm-ppc/byteorder.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef _PPC_BYTEORDER_H
-#define _PPC_BYTEORDER_H
-#include <asm/types.h>
-#include <linux/compiler.h>
-#ifdef __GNUC__
-#ifdef __KERNEL__
-extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
-{
-        unsigned val;
-        __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
-        return val;
-}
-extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
-{
-        __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
-}
-extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
-{
-        unsigned val;
-        __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
-        return val;
-}
-extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
-{
-        __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
-}
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
-{
-        __u16 result;
-        __asm__("rlwimi %0,%2,8,16,23" : "=&r" (result) : "0" (value >> 8), "r" (value));
-        return result;
-}
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
-{
-        __u32 result;
-        __asm__("rlwimi %0,%2,24,16,23" : "=&r" (result) : "0" (value>>24), "r" (value));
-        __asm__("rlwimi %0,%2,8,8,15"   : "=&r" (result) : "0" (result),    "r" (value));
-        __asm__("rlwimi %0,%2,24,0,7"   : "=&r" (result) : "0" (result),    "r" (value));
-        return result;
-}
-#define __arch__swab32(x) ___arch__swab32(x)
-#define __arch__swab16(x) ___arch__swab16(x)
-/* The same, but returns converted value from the location pointer by addr. */
-#define __arch__swab16p(addr) ld_le16(addr)
-#define __arch__swab32p(addr) ld_le32(addr)
-/* The same, but do the conversion in situ, ie. put the value back to addr. */
-#define __arch__swab16s(addr) st_le16(addr,*addr)
-#define __arch__swab32s(addr) st_le32(addr,*addr)
-#endif /* __KERNEL__ */
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-#endif /* __GNUC__ */
-#include <linux/byteorder/big_endian.h>
-#endif /* _PPC_BYTEORDER_H */
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
index 38f2f1be4a87..7a157d0f4b5f 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-ppc/cache.h
@@ -9,21 +9,18 @@
 /* bytes per L1 cache line */
 #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
-#define L1_CACHE_LINE_SIZE      16
+#define L1_CACHE_SHIFT  4
-#define LG_L1_CACHE_LINE_SIZE   4
 #define MAX_COPY_PREFETCH       1
 #elif defined(CONFIG_PPC64BRIDGE)
-#define L1_CACHE_LINE_SIZE      128
+#define L1_CACHE_SHIFT  7
-#define LG_L1_CACHE_LINE_SIZE   7
 #define MAX_COPY_PREFETCH       1
 #else
-#define L1_CACHE_LINE_SIZE      32
+#define L1_CACHE_SHIFT  5
-#define LG_L1_CACHE_LINE_SIZE   5
 #define MAX_COPY_PREFETCH       4
 #endif
-#define L1_CACHE_BYTES L1_CACHE_LINE_SIZE
+#define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
-#define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 #define L1_CACHE_SHIFT_MAX 7    /* largest L1 which this arch supports */
diff --git a/include/asm-ppc/checksum.h b/include/asm-ppc/checksum.h
deleted file mode 100644
index cf953a92c7ab..000000000000
--- a/include/asm-ppc/checksum.h
+++ /dev/null
@@ -1,107 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_CHECKSUM_H
-#define _PPC_CHECKSUM_H
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-extern unsigned int csum_partial(const unsigned char * buff, int len,
-                                 unsigned int sum);
-/*
- * Computes the checksum of a memory block at src, length len,
- * and adds in "sum" (32-bit), while copying the block to dst.
- * If an access exception occurs on src or dst, it stores -EFAULT
- * to *src_err or *dst_err respectively (if that pointer is not
- * NULL), and, for an error on src, zeroes the rest of dst.
- *
- * Like csum_partial, this must be called with even lengths,
- * except for the last fragment.
- */
-extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
-                                              int len, unsigned int sum,
-                                              int *src_err, int *dst_err);
-#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
-        csum_partial_copy_generic((__force void *)(src), (dst), (len), (sum), (errp), NULL)
-/* FIXME: this needs to be written to really do no check -- Cort */
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
-/*
- * turns a 32-bit partial checksum (e.g. from csum_partial) into a
- * 1's complement 16-bit checksum.
- */
-static inline unsigned int csum_fold(unsigned int sum)
-{
-        unsigned int tmp;
-        /* swap the two 16-bit halves of sum */
-        __asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
-        /* if there is a carry from adding the two 16-bit halves,
-           it will carry from the lower half into the upper half,
-           giving us the correct sum in the upper half. */
-        sum = ~(sum + tmp) >> 16;
-        return sum;
-}
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
-{
-        return csum_fold(csum_partial(buff, len, 0));
-}
-/*
- * FIXME: I swiped this one from the sparc and made minor modifications.
- * It may not be correct.  -- Cort
- */
-static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
-                                                   unsigned long daddr,
-                                                   unsigned short len,
-                                                   unsigned short proto,
-                                                   unsigned int sum)
-{
-    __asm__("\n\
-        addc %0,%0,%1 \n\
-        adde %0,%0,%2 \n\
-        adde %0,%0,%3 \n\
-        addze %0,%0 \n\
-        "
-        : "=r" (sum)
-        : "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum));
-    return sum;
-}
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.  ihl is the number
- * of 32-bit words and is always >= 5.
- */
-extern unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl);
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-extern unsigned short csum_tcpudp_magic(unsigned long saddr,
-                                        unsigned long daddr,
-                                        unsigned short len,
-                                        unsigned short proto,
-                                        unsigned int sum);
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/commproc.h
index 5bbb8e2c1c6d..973e60908234 100644
--- a/include/asm-ppc/commproc.h
+++ b/include/asm-ppc/commproc.h
@@ -83,6 +83,8 @@ extern uint m8xx_cpm_hostalloc(uint size);
 extern int  m8xx_cpm_hostfree(uint start);
 extern void m8xx_cpm_hostdump(void);
+extern void cpm_load_patch(volatile immap_t *immr);
 /* Buffer descriptors used by many of the CPM protocols.
 */
 typedef struct cpm_buf_desc {
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index 9483d4bfacf7..43d2ebbc7748 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -1087,6 +1087,9 @@ typedef struct im_idma {
 #define SCCR_PCIDF_MSK  0x00000078      /* PCI division factor  */
 #define SCCR_PCIDF_SHIFT 3
+#ifndef CPM_IMMR_OFFSET
+#define CPM_IMMR_OFFSET 0x101a8
+#endif
 #endif /* __CPM2__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h
deleted file mode 100644
index e17c492c870b..000000000000
--- a/include/asm-ppc/cputable.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- *  include/asm-ppc/cputable.h
- *
- *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_PPC_CPUTABLE_H
-#define __ASM_PPC_CPUTABLE_H
-/* Exposed to userland CPU features */
-#define PPC_FEATURE_32                  0x80000000
-#define PPC_FEATURE_64                  0x40000000
-#define PPC_FEATURE_601_INSTR           0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
-#define PPC_FEATURE_HAS_FPU             0x08000000
-#define PPC_FEATURE_HAS_MMU             0x04000000
-#define PPC_FEATURE_HAS_4xxMAC          0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
-#define PPC_FEATURE_HAS_SPE             0x00800000
-#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
-#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
-#define PPC_FEATURE_NO_TB               0x00100000
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mecanism.
- */
-struct cpu_spec;
-typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
-struct cpu_spec {
-        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
-        unsigned int    pvr_mask;
-        unsigned int    pvr_value;
-        char            *cpu_name;
-        unsigned int    cpu_features;           /* Kernel features */
-        unsigned int    cpu_user_features;      /* Userland features */
-        /* cache line sizes */
-        unsigned int    icache_bsize;
-        unsigned int    dcache_bsize;
-        /* number of performance monitor counters */
-        unsigned int    num_pmcs;
-        /* this is called to initialize various CPU bits like L1 cache,
-         * BHT, SPD, etc... from head.S before branching to identify_machine
-         */
-        cpu_setup_t     cpu_setup;
-};
-extern struct cpu_spec          cpu_specs[];
-extern struct cpu_spec          *cur_cpu_spec[];
-static inline unsigned int cpu_has_feature(unsigned int feature)
-{
-        return cur_cpu_spec[0]->cpu_features & feature;
-}
-#endif /* __ASSEMBLY__ */
-/* CPU kernel features */
-#define CPU_FTR_SPLIT_ID_CACHE          0x00000001
-#define CPU_FTR_L2CR                    0x00000002
-#define CPU_FTR_SPEC7450                0x00000004
-#define CPU_FTR_ALTIVEC                 0x00000008
-#define CPU_FTR_TAU                     0x00000010
-#define CPU_FTR_CAN_DOZE                0x00000020
-#define CPU_FTR_USE_TB                  0x00000040
-#define CPU_FTR_604_PERF_MON            0x00000080
-#define CPU_FTR_601                     0x00000100
-#define CPU_FTR_HPTE_TABLE              0x00000200
-#define CPU_FTR_CAN_NAP                 0x00000400
-#define CPU_FTR_L3CR                    0x00000800
-#define CPU_FTR_L3_DISABLE_NAP          0x00001000
-#define CPU_FTR_NAP_DISABLE_L2_PR       0x00002000
-#define CPU_FTR_DUAL_PLL_750FX          0x00004000
-#define CPU_FTR_NO_DPM                  0x00008000
-#define CPU_FTR_HAS_HIGH_BATS           0x00010000
-#define CPU_FTR_NEED_COHERENT           0x00020000
-#define CPU_FTR_NO_BTIC                 0x00040000
-#define CPU_FTR_BIG_PHYS                0x00080000
-#ifdef __ASSEMBLY__
-#define BEGIN_FTR_SECTION               98:
-#define END_FTR_SECTION(msk, val)               \
-99:                                             \
-        .section __ftr_fixup,"a";               \
-        .align 2;                               \
-        .long msk;                              \
-        .long val;                              \
-        .long 98b;                              \
-        .long 99b;                              \
-        .previous
-#else
-#define BEGIN_FTR_SECTION               "98:\n"
-#define END_FTR_SECTION(msk, val)               \
-"99:\n"                                         \
-"       .section __ftr_fixup,\"a\";\n"          \
-"       .align 2;\n"                            \
-"       .long "#msk";\n"                        \
-"       .long "#val";\n"                        \
-"       .long 98b;\n"                           \
-"       .long 99b;\n"                           \
-"       .previous\n"
-#endif /* __ASSEMBLY__ */
-#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
-#endif /* __ASM_PPC_CPUTABLE_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h
deleted file mode 100644
index c25cc35e6ab5..000000000000
--- a/include/asm-ppc/elf.h
+++ /dev/null
@@ -1,151 +0,0 @@
-#ifndef __PPC_ELF_H
-#define __PPC_ELF_H
-/*
- * ELF register definitions..
- */
-#include <asm/types.h>
-#include <asm/ptrace.h>
-#include <asm/cputable.h>
-#include <asm/auxvec.h>
-/* PowerPC relocations defined by the ABIs */
-#define R_PPC_NONE              0
-#define R_PPC_ADDR32            1       /* 32bit absolute address */
-#define R_PPC_ADDR24            2       /* 26bit address, 2 bits ignored.  */
-#define R_PPC_ADDR16            3       /* 16bit absolute address */
-#define R_PPC_ADDR16_LO         4       /* lower 16bit of absolute address */
-#define R_PPC_ADDR16_HI         5       /* high 16bit of absolute address */
-#define R_PPC_ADDR16_HA         6       /* adjusted high 16bit */
-#define R_PPC_ADDR14            7       /* 16bit address, 2 bits ignored */
-#define R_PPC_ADDR14_BRTAKEN    8
-#define R_PPC_ADDR14_BRNTAKEN   9
-#define R_PPC_REL24             10      /* PC relative 26 bit */
-#define R_PPC_REL14             11      /* PC relative 16 bit */
-#define R_PPC_REL14_BRTAKEN     12
-#define R_PPC_REL14_BRNTAKEN    13
-#define R_PPC_GOT16             14
-#define R_PPC_GOT16_LO          15
-#define R_PPC_GOT16_HI          16
-#define R_PPC_GOT16_HA          17
-#define R_PPC_PLTREL24          18
-#define R_PPC_COPY              19
-#define R_PPC_GLOB_DAT          20
-#define R_PPC_JMP_SLOT          21
-#define R_PPC_RELATIVE          22
-#define R_PPC_LOCAL24PC         23
-#define R_PPC_UADDR32           24
-#define R_PPC_UADDR16           25
-#define R_PPC_REL32             26
-#define R_PPC_PLT32             27
-#define R_PPC_PLTREL32          28
-#define R_PPC_PLT16_LO          29
-#define R_PPC_PLT16_HI          30
-#define R_PPC_PLT16_HA          31
-#define R_PPC_SDAREL16          32
-#define R_PPC_SECTOFF           33
-#define R_PPC_SECTOFF_LO        34
-#define R_PPC_SECTOFF_HI        35
-#define R_PPC_SECTOFF_HA        36
-/* Keep this the last entry.  */
-#define R_PPC_NUM               37
-#define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
-#define ELF_NFPREG      33      /* includes fpscr */
-#define ELF_NVRREG      33      /* includes vscr */
-#define ELF_NEVRREG     34      /* includes acc (as 2) */
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_ARCH        EM_PPC
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2MSB
-/* General registers */
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-/* Floating point registers */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-/* Altivec registers */
-typedef __vector128 elf_vrreg_t;
-typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
-#ifdef __KERNEL__
-struct task_struct;
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_PPC)
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-#define ELF_ET_DYN_BASE         (0x08000000)
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
-#define ELF_CORE_COPY_REGS(gregs, regs)                         \
-        memcpy((gregs), (regs), sizeof(struct pt_regs));        \
-        memset((char *)(gregs) + sizeof(struct pt_regs), 0,     \
-               sizeof(elf_gregset_t) - sizeof(struct pt_regs));
-#define ELF_CORE_COPY_TASK_REGS(t, elfregs)                     \
-        ((t)->thread.regs?                                      \
-         ({ ELF_CORE_COPY_REGS((elfregs), (t)->thread.regs); 1; }): 0)
-extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu);
-#define ELF_CORE_COPY_FPREGS(t, fpu)    dump_task_fpu((t), (fpu))
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  This could be done in userspace,
-   but it's not easy, and we've already done it here.  */
-#define ELF_HWCAP       (cur_cpu_spec[0]->cpu_user_features)
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.
-   For the moment, we have only optimizations for the Intel generations,
-   but that could change... */
-#define ELF_PLATFORM    (NULL)
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
-extern int dcache_bsize;
-extern int icache_bsize;
-extern int ucache_bsize;
-/*
- * The requirements here are:
- * - keep the final alignment of sp (sp & 0xf)
- * - make sure the 32-bit value at the first 16 byte aligned position of
- *   AUXV is greater than 16 for glibc compatibility.
- *   AT_IGNOREPPC is used for that.
- * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
- *   even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
- */
-#define ARCH_DLINFO                                                     \
-do {                                                                    \
-        /* Handle glibc compatibility. */                               \
-        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
-        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
-        /* Cache size items */                                          \
-        NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);                      \
-        NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);                      \
-        NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);                      \
- } while (0)
-#endif /* __KERNEL__ */
-#endif
diff --git a/include/asm-ppc/futex.h b/include/asm-ppc/futex.h
deleted file mode 100644
index 9feff4ce1424..000000000000
--- a/include/asm-ppc/futex.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-#ifdef __KERNEL__
-#include <linux/futex.h>
-#include <asm/errno.h>
-#include <asm/uaccess.h>
-static inline int
-futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
-{
-        int op = (encoded_op >> 28) & 7;
-        int cmp = (encoded_op >> 24) & 15;
-        int oparg = (encoded_op << 8) >> 20;
-        int cmparg = (encoded_op << 20) >> 20;
-        int oldval = 0, ret;
-        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
-                oparg = 1 << oparg;
-        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
-                return -EFAULT;
-        inc_preempt_count();
-        switch (op) {
-        case FUTEX_OP_SET:
-        case FUTEX_OP_ADD:
-        case FUTEX_OP_OR:
-        case FUTEX_OP_ANDN:
-        case FUTEX_OP_XOR:
-        default:
-                ret = -ENOSYS;
-        }
-        dec_preempt_count();
-        if (!ret) {
-                switch (cmp) {
-                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
-                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
-                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
-                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
-                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
-                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
-                default: ret = -ENOSYS;
-                }
-        }
-        return ret;
-}
-#endif
-#endif
diff --git a/include/asm-ppc/hw_irq.h b/include/asm-ppc/hw_irq.h
deleted file mode 100644
index 47dc7990fb26..000000000000
--- a/include/asm-ppc/hw_irq.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifdef __KERNEL__
-#ifndef _PPC_HW_IRQ_H
-#define _PPC_HW_IRQ_H
-#include <asm/ptrace.h>
-#include <asm/reg.h>
-extern void timer_interrupt(struct pt_regs *);
-#define INLINE_IRQS
-#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
-#ifdef INLINE_IRQS
-static inline void local_irq_disable(void)
-{
-        unsigned long msr;
-        msr = mfmsr();
-        mtmsr(msr & ~MSR_EE);
-        __asm__ __volatile__("": : :"memory");
-}
-static inline void local_irq_enable(void)
-{
-        unsigned long msr;
-        __asm__ __volatile__("": : :"memory");
-        msr = mfmsr();
-        mtmsr(msr | MSR_EE);
-}
-static inline void local_irq_save_ptr(unsigned long *flags)
-{
-        unsigned long msr;
-        msr = mfmsr();
-        *flags = msr;
-        mtmsr(msr & ~MSR_EE);
-        __asm__ __volatile__("": : :"memory");
-}
-#define local_save_flags(flags)         ((flags) = mfmsr())
-#define local_irq_save(flags)           local_irq_save_ptr(&flags)
-#define local_irq_restore(flags)        mtmsr(flags)
-#else
-extern void local_irq_enable(void);
-extern void local_irq_disable(void);
-extern void local_irq_restore(unsigned long);
-extern void local_save_flags_ptr(unsigned long *);
-#define local_save_flags(flags) local_save_flags_ptr(&flags)
-#define local_irq_save(flags) ({local_save_flags(flags);local_irq_disable();})
-#endif
-extern void do_lost_interrupts(unsigned long);
-#define mask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->disable) irq_desc[irq].handler->disable(irq);})
-#define unmask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->enable) irq_desc[irq].handler->enable(irq);})
-#define ack_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->ack) irq_desc[irq].handler->ack(irq);})
-/* Should we handle this via lost interrupts and IPIs or should we don't care like
- * we do now ? --BenH.
- */
-struct hw_interrupt_type;
-static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
-#endif /* _PPC_HW_IRQ_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/i8259.h b/include/asm-ppc/i8259.h
deleted file mode 100644
index 091b71295de4..000000000000
--- a/include/asm-ppc/i8259.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _PPC_KERNEL_i8259_H
-#define _PPC_KERNEL_i8259_H
-#include <linux/irq.h>
-extern struct hw_interrupt_type i8259_pic;
-extern void i8259_init(long intack_addr);
-extern int i8259_irq(struct pt_regs *regs);
-#endif /* _PPC_KERNEL_i8259_H */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 94d83998a759..f7f614dfc648 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -8,6 +8,7 @@
 #include <asm/page.h>
 #include <asm/byteorder.h>
+#include <asm/synch.h>
 #include <asm/mmu.h>
 #define SIO_CONFIG_RA   0x398
@@ -440,16 +441,6 @@ extern inline void * phys_to_virt(unsigned long address)
 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
-/*
- * Enforce In-order Execution of I/O:
- * Acts as a barrier to ensure all previous I/O accesses have
- * completed before any further ones are issued.
- */
-extern inline void eieio(void)
-{
-        __asm__ __volatile__ ("eieio" : : : "memory");
-}
 /* Enforce in-order execution of data I/O.
 * No distinction between read/write on PPC; use eieio for all three.
 */
diff --git a/include/asm-ppc/ipcbuf.h b/include/asm-ppc/ipcbuf.h
deleted file mode 100644
index fab6752c7480..000000000000
--- a/include/asm-ppc/ipcbuf.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __PPC_IPCBUF_H__
-#define __PPC_IPCBUF_H__
-/*
- * The ipc64_perm structure for PPC architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 1 32-bit value to fill up for 8-byte alignment
- * - 2 miscellaneous 64-bit values (so that this structure matches
- *                                  PPC64 ipc64_perm)
- */
-struct ipc64_perm
-{
-        __kernel_key_t          key;
-        __kernel_uid_t          uid;
-        __kernel_gid_t          gid;
-        __kernel_uid_t          cuid;
-        __kernel_gid_t          cgid;
-        __kernel_mode_t         mode;
-        unsigned long           seq;
-        unsigned int            __pad2;
-        unsigned long long      __unused1;
-        unsigned long long      __unused2;
-};
-#endif /* __PPC_IPCBUF_H__ */
diff --git a/include/asm-ppc/kexec.h b/include/asm-ppc/kexec.h
deleted file mode 100644
index 6d2aa0aa4642..000000000000
--- a/include/asm-ppc/kexec.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef _PPC_KEXEC_H
-#define _PPC_KEXEC_H
-#ifdef CONFIG_KEXEC
-/*
- * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
- * I.e. Maximum page that is mapped directly into kernel memory,
- * and kmap is not required.
- *
- * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
- * calculation for the amount of memory directly mappable into the
- * kernel memory space.
- */
-/* Maximum physical address we can use pages from */
-#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
-/* Maximum address we can reach in physical address mode */
-#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
-/* Maximum address we can use for the control code buffer */
-#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
-#define KEXEC_CONTROL_CODE_SIZE 4096
-/* The native architecture */
-#define KEXEC_ARCH KEXEC_ARCH_PPC
-#ifndef __ASSEMBLY__
-extern void *crash_notes;
-struct kimage;
-extern void machine_kexec_simple(struct kimage *image);
-#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_KEXEC */
-#endif /* _PPC_KEXEC_H */
diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h
deleted file mode 100644
index 6d6fc78731e5..000000000000
--- a/include/asm-ppc/kmap_types.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_PPC_SYNC_PAGE,
-        KM_PPC_SYNC_ICACHE,
-        KM_TYPE_NR
-};
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
index 1d4ab70a56f3..f01255bd1dc3 100644
--- a/include/asm-ppc/machdep.h
+++ b/include/asm-ppc/machdep.h
@@ -98,7 +98,7 @@ struct machdep_calls {
        /* Get access protection for /dev/mem */
        pgprot_t        (*phys_mem_access_prot)(struct file *file,
-                                                unsigned long offset,
+                                                unsigned long pfn,
                                                unsigned long size,
                                                pgprot_t vma_prot);
@@ -167,7 +167,7 @@ extern sys_ctrler_t sys_ctrler;
 #ifdef CONFIG_SMP
 struct smp_ops_t {
-        void  (*message_pass)(int target, int msg, unsigned long data, int wait);
+        void  (*message_pass)(int target, int msg);
        int   (*probe)(void);
        void  (*kick_cpu)(int nr);
        void  (*setup_cpu)(int nr);
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index afe26ffc2e2d..4f152cca13c1 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -164,13 +164,11 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                             struct task_struct *tsk)
 {
 #ifdef CONFIG_ALTIVEC
-        asm volatile (
+        if (cpu_has_feature(CPU_FTR_ALTIVEC))
- BEGIN_FTR_SECTION
+        asm volatile ("dssall;\n"
-        "dssall;\n"
 #ifndef CONFIG_POWER4
         "sync;\n" /* G4 needs a sync here, G5 apparently not */
 #endif
- END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
         : : );
 #endif /* CONFIG_ALTIVEC */
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index 9694eca16e92..321452695039 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -92,6 +92,10 @@ enum ppc_sys_devices {
 extern unsigned char __res[];
 #endif
+#ifndef BOARD_CHIP_NAME
+#define BOARD_CHIP_NAME ""
+#endif
 #endif /* CONFIG_8260 */
 #endif /* !__ASM_PPC_MPC8260_H__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 516984ee14b5..d98db980cd49 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -67,6 +67,8 @@ extern unsigned char __res[];
 #define MPC85xx_DMA3_SIZE       (0x00080)
 #define MPC85xx_ENET1_OFFSET    (0x24000)
 #define MPC85xx_ENET1_SIZE      (0x01000)
+#define MPC85xx_MIIM_OFFSET     (0x24520)
+#define MPC85xx_MIIM_SIZE       (0x00018)
 #define MPC85xx_ENET2_OFFSET    (0x25000)
 #define MPC85xx_ENET2_SIZE      (0x01000)
 #define MPC85xx_ENET3_OFFSET    (0x26000)
@@ -132,6 +134,7 @@ enum ppc_sys_devices {
        MPC85xx_eTSEC3,
        MPC85xx_eTSEC4,
        MPC85xx_IIC2,
+        MPC85xx_MDIO,
 };
 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
index 208a2e11daee..46f159cf589e 100644
--- a/include/asm-ppc/mpc8xx.h
+++ b/include/asm-ppc/mpc8xx.h
@@ -113,6 +113,10 @@ enum ppc_sys_devices {
        MPC8xx_CPM_USB,
 };
+#ifndef BOARD_CHIP_NAME
+#define BOARD_CHIP_NAME ""
+#endif
 #endif /* !__ASSEMBLY__ */
 #endif /* CONFIG_8xx */
 #endif /* __CONFIG_8xx_DEFS */
diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h
index ee2f9188cc64..4f2405b83612 100644
--- a/include/asm-ppc/mv64x60.h
+++ b/include/asm-ppc/mv64x60.h
@@ -27,6 +27,8 @@
 #include <asm/pci-bridge.h>
 #include <asm/mv64x60_defs.h>
+struct platform_device;
 extern u8       mv64x60_pci_exclude_bridge;
 extern spinlock_t mv64x60_lock;
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
index 7848aa610c05..ec2f46629ca2 100644
--- a/include/asm-ppc/open_pic.h
+++ b/include/asm-ppc/open_pic.h
@@ -58,8 +58,7 @@ extern int openpic_get_irq(struct pt_regs *regs);
 extern void openpic_reset_processor_phys(u_int cpumask);
 extern void openpic_setup_ISU(int isu_num, unsigned long addr);
 extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
-extern void smp_openpic_message_pass(int target, int msg, unsigned long data,
+extern void smp_openpic_message_pass(int target, int msg);
-                                     int wait);
 extern void openpic_set_k2_cascade(int irq);
 extern void openpic_set_priority(u_int pri);
 extern u_int openpic_get_priority(void);
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h
index 4789dc024240..fc44f7ca62d7 100644
--- a/include/asm-ppc/page.h
+++ b/include/asm-ppc/page.h
@@ -34,6 +34,17 @@ typedef unsigned long pte_basic_t;
 #define PTE_FMT         "%.8lx"
 #endif
+/* align addr on a size boundary - adjust address up/down if needed */
+#define _ALIGN_UP(addr,size)    (((addr)+((size)-1))&(~((size)-1)))
+#define _ALIGN_DOWN(addr,size)  ((addr)&(~((size)-1)))
+/* align addr on a size boundary - adjust address up if needed */
+#define _ALIGN(addr,size)     _ALIGN_UP(addr,size)
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)        _ALIGN(addr, PAGE_SIZE)
 #undef STRICT_MM_TYPECHECKS
 #ifdef STRICT_MM_TYPECHECKS
@@ -76,13 +87,6 @@ typedef unsigned long pgprot_t;
 #endif
-/* align addr on a size boundary - adjust address up if needed -- Cort */
-#define _ALIGN(addr,size)       (((addr)+(size)-1)&(~((size)-1)))
-/* to align the pointer to the (next) page boundary */
-#define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
 struct page;
 extern void clear_pages(void *page, int order);
 static inline void clear_page(void *page) { clear_pages(page, 0); }
diff --git a/include/asm-ppc/parport.h b/include/asm-ppc/parport.h
deleted file mode 100644
index 11f96d3de5b6..000000000000
--- a/include/asm-ppc/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * parport.h: platform-specific PC-style parport initialisation
- *
- * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-#ifndef _ASM_PPC_PARPORT_H
-#define _ASM_PPC_PARPORT_H
-static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-        return parport_pc_find_isa_ports (autoirq, autodma);
-}
-#endif /* !(_ASM_PPC_PARPORT_H) */
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
index ffa423456c2b..e58c78f90a5a 100644
--- a/include/asm-ppc/pci-bridge.h
+++ b/include/asm-ppc/pci-bridge.h
@@ -79,6 +79,11 @@ struct pci_controller {
        struct resource mem_space;
 };
+static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
+{
+        return bus->sysdata;
+}
 /* These are used for config access before all the PCI probing
   has been done. */
 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index 9dd06cd40096..61434edbad7b 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -24,9 +24,9 @@ struct pci_dev;
 * Set this to 1 if you want the kernel to re-assign all PCI
 * bus numbers
 */
-extern int pci_assign_all_busses;
+extern int pci_assign_all_buses;
-#define pcibios_assign_all_busses()     (pci_assign_all_busses)
+#define pcibios_assign_all_busses()     (pci_assign_all_buses)
 #define pcibios_scan_all_fns(a, b)      0
 #define PCIBIOS_MIN_IO          0x1000
@@ -126,7 +126,7 @@ extern void pcibios_add_platform_entries(struct pci_dev *dev);
 struct file;
 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
-                                         unsigned long offset,
+                                         unsigned long pfn,
                                         unsigned long size,
                                         pgprot_t prot);
diff --git a/include/asm-ppc/perfmon.h b/include/asm-ppc/perfmon.h
deleted file mode 100644
index 5e7a89c47b5b..000000000000
--- a/include/asm-ppc/perfmon.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __PERFMON_H
-#define __PERFMON_H
-extern void (*perf_irq)(struct pt_regs *);
-int request_perfmon_irq(void (*handler)(struct pt_regs *));
-void free_perfmon_irq(void);
-#ifdef CONFIG_FSL_BOOKE
-void init_pmc_stop(int ctr);
-void set_pmc_event(int ctr, int event);
-void set_pmc_user_kernel(int ctr, int user, int kernel);
-void set_pmc_marked(int ctr, int mark0, int mark1);
-void pmc_start_ctr(int ctr, int enable);
-void pmc_start_ctrs(int enable);
-void pmc_stop_ctrs(void);
-void dump_pmcs(void);
-extern struct op_ppc32_model op_model_fsl_booke;
-#endif
-#endif /* __PERFMON_H */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index eee601bb9ada..b28a713ba862 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -705,7 +705,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
                                     unsigned long size, pgprot_t vma_prot);
 #define __HAVE_PHYS_MEM_ACCESS_PROT
diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h
deleted file mode 100644
index a14a82abe8d2..000000000000
--- a/include/asm-ppc/posix_types.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef _PPC_POSIX_TYPES_H
-#define _PPC_POSIX_TYPES_H
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-typedef unsigned long   __kernel_ino_t;
-typedef unsigned int    __kernel_mode_t;
-typedef unsigned short  __kernel_nlink_t;
-typedef long            __kernel_off_t;
-typedef int             __kernel_pid_t;
-typedef unsigned int    __kernel_uid_t;
-typedef unsigned int    __kernel_gid_t;
-typedef unsigned int    __kernel_size_t;
-typedef int             __kernel_ssize_t;
-typedef long            __kernel_ptrdiff_t;
-typedef long            __kernel_time_t;
-typedef long            __kernel_suseconds_t;
-typedef long            __kernel_clock_t;
-typedef int             __kernel_timer_t;
-typedef int             __kernel_clockid_t;
-typedef int             __kernel_daddr_t;
-typedef char *          __kernel_caddr_t;
-typedef short             __kernel_ipc_pid_t;
-typedef unsigned short  __kernel_uid16_t;
-typedef unsigned short  __kernel_gid16_t;
-typedef unsigned int    __kernel_uid32_t;
-typedef unsigned int    __kernel_gid32_t;
-typedef unsigned int    __kernel_old_uid_t;
-typedef unsigned int    __kernel_old_gid_t;
-typedef unsigned int    __kernel_old_dev_t;
-#ifdef __GNUC__
-typedef long long       __kernel_loff_t;
-#endif
-typedef struct {
-        int     val[2];
-} __kernel_fsid_t;
-#ifndef __GNUC__
-#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-#define __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-#define __FD_ZERO(set)  \
-  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
-#else /* __GNUC__ */
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
-    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
-/* With GNU C, use inline functions instead so args are evaluated only once: */
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
-{
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
-}
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
-{
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
-}
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
-{
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
-}
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *p)
-{
-        unsigned int *tmp = (unsigned int *)p->fds_bits;
-        int i;
-        if (__builtin_constant_p(__FDSET_LONGS)) {
-                switch (__FDSET_LONGS) {
-                        case 8:
-                                tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
-                                tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
-                                return;
-                }
-        }
-        i = __FDSET_LONGS;
-        while (i) {
-                i--;
-                *tmp = 0;
-                tmp++;
-        }
-}
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-#endif /* __GNUC__ */
-#endif /* _PPC_POSIX_TYPES_H */
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
index 549f44843c5e..bba5305c29ed 100644
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -18,7 +18,7 @@
 #define __ASM_PPC_SYS_H
 #include <linux/init.h>
-#include <linux/device.h>
+#include <linux/platform_device.h>
 #include <linux/types.h>
 #if defined(CONFIG_8260)
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h
deleted file mode 100644
index 7043c164b537..000000000000
--- a/include/asm-ppc/ptrace.h
+++ /dev/null
@@ -1,152 +0,0 @@
-#ifndef _PPC_PTRACE_H
-#define _PPC_PTRACE_H
-/*
- * This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry.
- *
- * this should only contain volatile regs
- * since we can keep non-volatile in the thread_struct
- * should set this up when only volatiles are saved
- * by intr code.
- *
- * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
- * that the overall structure is a multiple of 16 bytes in length.
- *
- * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below.  This simplifies arch/ppc/kernel/ptrace.c.
- */
-#ifndef __ASSEMBLY__
-struct pt_regs {
-        unsigned long gpr[32];
-        unsigned long nip;
-        unsigned long msr;
-        unsigned long orig_gpr3;        /* Used for restarting system calls */
-        unsigned long ctr;
-        unsigned long link;
-        unsigned long xer;
-        unsigned long ccr;
-        unsigned long mq;               /* 601 only (not used at present) */
-                                        /* Used on APUS to hold IPL value. */
-        unsigned long trap;             /* Reason for being here */
-        /* N.B. for critical exceptions on 4xx, the dar and dsisr
-           fields are overloaded to hold srr0 and srr1. */
-        unsigned long dar;              /* Fault registers */
-        unsigned long dsisr;            /* on 4xx/Book-E used for ESR */
-        unsigned long result;           /* Result of a system call */
-};
-#endif /* __ASSEMBLY__ */
-#ifdef __KERNEL__
-#define STACK_FRAME_OVERHEAD    16      /* size of minimum stack frame */
-/* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE      64
-#ifndef __ASSEMBLY__
-#define instruction_pointer(regs) ((regs)->nip)
-#ifdef CONFIG_SMP
-extern unsigned long profile_pc(struct pt_regs *regs);
-#else
-#define profile_pc(regs) instruction_pointer(regs)
-#endif
-#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
-#define force_successful_syscall_return()   \
-        do { \
-                current_thread_info()->local_flags |= _TIFL_FORCE_NOERROR; \
-        } while(0)
-/*
- * We use the least-significant bit of the trap field to indicate
- * whether we have saved the full set of registers, or only a
- * partial set.  A 1 there means the partial set.
- * On 4xx we use the next bit to indicate whether the exception
- * is a critical exception (1 means it is).
- */
-#define FULL_REGS(regs)         (((regs)->trap & 1) == 0)
-#define IS_CRITICAL_EXC(regs)   (((regs)->trap & 2) == 0)
-#define TRAP(regs)              ((regs)->trap & ~0xF)
-#define CHECK_FULL_REGS(regs)                                                 \
-do {                                                                          \
-        if ((regs)->trap & 1)                                                 \
-                printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
-} while (0)
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-/*
- * Offsets used by 'ptrace' system call interface.
- * These can't be changed without breaking binary compatibility
- * with MkLinux, etc.
- */
-#define PT_R0   0
-#define PT_R1   1
-#define PT_R2   2
-#define PT_R3   3
-#define PT_R4   4
-#define PT_R5   5
-#define PT_R6   6
-#define PT_R7   7
-#define PT_R8   8
-#define PT_R9   9
-#define PT_R10  10
-#define PT_R11  11
-#define PT_R12  12
-#define PT_R13  13
-#define PT_R14  14
-#define PT_R15  15
-#define PT_R16  16
-#define PT_R17  17
-#define PT_R18  18
-#define PT_R19  19
-#define PT_R20  20
-#define PT_R21  21
-#define PT_R22  22
-#define PT_R23  23
-#define PT_R24  24
-#define PT_R25  25
-#define PT_R26  26
-#define PT_R27  27
-#define PT_R28  28
-#define PT_R29  29
-#define PT_R30  30
-#define PT_R31  31
-#define PT_NIP  32
-#define PT_MSR  33
-#ifdef __KERNEL__
-#define PT_ORIG_R3 34
-#endif
-#define PT_CTR  35
-#define PT_LNK  36
-#define PT_XER  37
-#define PT_CCR  38
-#define PT_MQ   39
-#define PT_FPR0 48      /* each FP reg occupies 2 slots in this space */
-#define PT_FPR31 (PT_FPR0 + 2*31)
-#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
-/* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go */
-#define PTRACE_GETVRREGS        18
-#define PTRACE_SETVRREGS        19
-/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
- * spefscr, in one go */
-#define PTRACE_GETEVRREGS       20
-#define PTRACE_SETEVRREGS       21
-/*
- * Get or set a debug register. The first 16 are DABR registers and the
- * second 16 are IABR registers.
- */
-#define PTRACE_GET_DEBUGREG     25
-#define PTRACE_SET_DEBUGREG     26
-#endif
diff --git a/include/asm-ppc/rwsem.h b/include/asm-ppc/rwsem.h
deleted file mode 100644
index 3e738f483c11..000000000000
--- a/include/asm-ppc/rwsem.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * include/asm-ppc/rwsem.h: R/W semaphores for PPC using the stuff
- * in lib/rwsem.c.  Adapted largely from include/asm-i386/rwsem.h
- * by Paul Mackerras <paulus@samba.org>.
- */
-#ifndef _PPC_RWSEM_H
-#define _PPC_RWSEM_H
-#ifdef __KERNEL__
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <asm/atomic.h>
-#include <asm/system.h>
-/*
- * the semaphore definition
- */
-struct rw_semaphore {
-        /* XXX this should be able to be an atomic_t  -- paulus */
-        signed long             count;
-#define RWSEM_UNLOCKED_VALUE            0x00000000
-#define RWSEM_ACTIVE_BIAS               0x00000001
-#define RWSEM_ACTIVE_MASK               0x0000ffff
-#define RWSEM_WAITING_BIAS              (-0x00010000)
-#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
-        spinlock_t              wait_lock;
-        struct list_head        wait_list;
-#if RWSEM_DEBUG
-        int                     debug;
-#endif
-};
-/*
- * initialisation
- */
-#if RWSEM_DEBUG
-#define __RWSEM_DEBUG_INIT      , 0
-#else
-#define __RWSEM_DEBUG_INIT      /* */
-#endif
-#define __RWSEM_INITIALIZER(name) \
-        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
-          LIST_HEAD_INIT((name).wait_list) \
-          __RWSEM_DEBUG_INIT }
-#define DECLARE_RWSEM(name)             \
-        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
-extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
-static inline void init_rwsem(struct rw_semaphore *sem)
-{
-        sem->count = RWSEM_UNLOCKED_VALUE;
-        spin_lock_init(&sem->wait_lock);
-        INIT_LIST_HEAD(&sem->wait_list);
-#if RWSEM_DEBUG
-        sem->debug = 0;
-#endif
-}
-/*
- * lock for reading
- */
-static inline void __down_read(struct rw_semaphore *sem)
-{
-        if (atomic_inc_return((atomic_t *)(&sem->count)) > 0)
-                smp_wmb();
-        else
-                rwsem_down_read_failed(sem);
-}
-static inline int __down_read_trylock(struct rw_semaphore *sem)
-{
-        int tmp;
-        while ((tmp = sem->count) >= 0) {
-                if (tmp == cmpxchg(&sem->count, tmp,
-                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
-                        smp_wmb();
-                        return 1;
-                }
-        }
-        return 0;
-}
-/*
- * lock for writing
- */
-static inline void __down_write(struct rw_semaphore *sem)
-{
-        int tmp;
-        tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
-                                (atomic_t *)(&sem->count));
-        if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
-                smp_wmb();
-        else
-                rwsem_down_write_failed(sem);
-}
-static inline int __down_write_trylock(struct rw_semaphore *sem)
-{
-        int tmp;
-        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
-                      RWSEM_ACTIVE_WRITE_BIAS);
-        smp_wmb();
-        return tmp == RWSEM_UNLOCKED_VALUE;
-}
-/*
- * unlock after reading
- */
-static inline void __up_read(struct rw_semaphore *sem)
-{
-        int tmp;
-        smp_wmb();
-        tmp = atomic_dec_return((atomic_t *)(&sem->count));
-        if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
-                rwsem_wake(sem);
-}
-/*
- * unlock after writing
- */
-static inline void __up_write(struct rw_semaphore *sem)
-{
-        smp_wmb();
-        if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
-                              (atomic_t *)(&sem->count)) < 0)
-                rwsem_wake(sem);
-}
-/*
- * implement atomic add functionality
- */
-static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
-{
-        atomic_add(delta, (atomic_t *)(&sem->count));
-}
-/*
- * downgrade write lock to read lock
- */
-static inline void __downgrade_write(struct rw_semaphore *sem)
-{
-        int tmp;
-        smp_wmb();
-        tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
-        if (tmp < 0)
-                rwsem_downgrade_wake(sem);
-}
-/*
- * implement exchange and add functionality
- */
-static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
-{
-        smp_mb();
-        return atomic_add_return(delta, (atomic_t *)(&sem->count));
-}
-#endif /* __KERNEL__ */
-#endif /* _PPC_RWSEM_XADD_H */
diff --git a/include/asm-ppc/scatterlist.h b/include/asm-ppc/scatterlist.h
deleted file mode 100644
index f21f18f56548..000000000000
--- a/include/asm-ppc/scatterlist.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_SCATTERLIST_H
-#define _PPC_SCATTERLIST_H
-#include <asm/dma.h>
-struct scatterlist {
-        struct page     *page;
-        unsigned int    offset;
-        dma_addr_t      dma_address;
-        unsigned int    length;
-};
-/*
- * These macros should be used after a pci_map_sg call has been done
- * to get bus addresses of each of the SG entries and their lengths.
- * You should only work with the number of sg entries pci_map_sg
- * returns, or alternatively stop on the first sg_dma_len(sg) which
- * is 0.
- */
-#define sg_dma_address(sg)      ((sg)->dma_address)
-#define sg_dma_len(sg)          ((sg)->length)
-#endif /* !(_PPC_SCATTERLIST_H) */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/seccomp.h b/include/asm-ppc/seccomp.h
deleted file mode 100644
index 666c4da96d87..000000000000
--- a/include/asm-ppc/seccomp.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _ASM_SECCOMP_H
-#include <linux/unistd.h>
-#define __NR_seccomp_read __NR_read
-#define __NR_seccomp_write __NR_write
-#define __NR_seccomp_exit __NR_exit
-#define __NR_seccomp_sigreturn __NR_rt_sigreturn
-#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-ppc/sections.h b/include/asm-ppc/sections.h
deleted file mode 100644
index ba8f43ac9bf3..000000000000
--- a/include/asm-ppc/sections.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_SECTIONS_H
-#define _PPC_SECTIONS_H
-#include <asm-generic/sections.h>
-#define __pmac __attribute__ ((__section__ (".pmac.text")))
-#define __pmacdata __attribute__ ((__section__ (".pmac.data")))
-#define __pmacfunc(__argpmac) \
-        __argpmac __pmac; \
-        __argpmac
-        
-#define __prep __attribute__ ((__section__ (".prep.text")))
-#define __prepdata __attribute__ ((__section__ (".prep.data")))
-#define __prepfunc(__argprep) \
-        __argprep __prep; \
-        __argprep
-#define __chrp __attribute__ ((__section__ (".chrp.text")))
-#define __chrpdata __attribute__ ((__section__ (".chrp.data")))
-#define __chrpfunc(__argchrp) \
-        __argchrp __chrp; \
-        __argchrp
-/* this is actually just common chrp/pmac code, not OF code -- Cort */
-#define __openfirmware __attribute__ ((__section__ (".openfirmware.text")))
-#define __openfirmwaredata __attribute__ ((__section__ (".openfirmware.data")))
-#define __openfirmwarefunc(__argopenfirmware) \
-        __argopenfirmware __openfirmware; \
-        __argopenfirmware
-        
-#endif /* _PPC_SECTIONS_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/semaphore.h b/include/asm-ppc/semaphore.h
deleted file mode 100644
index 89e6e73be08c..000000000000
--- a/include/asm-ppc/semaphore.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef _PPC_SEMAPHORE_H
-#define _PPC_SEMAPHORE_H
-/*
- * Swiped from asm-sparc/semaphore.h and modified
- * -- Cort (cort@cs.nmt.edu)
- *
- * Stole some rw spinlock-based semaphore stuff from asm-alpha/semaphore.h
- * -- Ani Joshi (ajoshi@unixbox.com)
- *
- * Remove spinlock-based RW semaphores; RW semaphore definitions are
- * now in rwsem.h and we use the generic lib/rwsem.c implementation.
- * Rework semaphores to use atomic_dec_if_positive.
- * -- Paul Mackerras (paulus@samba.org)
- */
-#ifdef __KERNEL__
-#include <asm/atomic.h>
-#include <asm/system.h>
-#include <linux/wait.h>
-#include <linux/rwsem.h>
-struct semaphore {
-        /*
-         * Note that any negative value of count is equivalent to 0,
-         * but additionally indicates that some process(es) might be
-         * sleeping on `wait'.
-         */
-        atomic_t count;
-        wait_queue_head_t wait;
-};
-#define __SEMAPHORE_INITIALIZER(name, n)                                \
-{                                                                       \
-        .count          = ATOMIC_INIT(n),                               \
-        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
-}
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name, 1)
-#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
-        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
-#define DECLARE_MUTEX(name)             __DECLARE_SEMAPHORE_GENERIC(name, 1)
-#define DECLARE_MUTEX_LOCKED(name)      __DECLARE_SEMAPHORE_GENERIC(name, 0)
-static inline void sema_init (struct semaphore *sem, int val)
-{
-        atomic_set(&sem->count, val);
-        init_waitqueue_head(&sem->wait);
-}
-static inline void init_MUTEX (struct semaphore *sem)
-{
-        sema_init(sem, 1);
-}
-static inline void init_MUTEX_LOCKED (struct semaphore *sem)
-{
-        sema_init(sem, 0);
-}
-extern void __down(struct semaphore * sem);
-extern int  __down_interruptible(struct semaphore * sem);
-extern void __up(struct semaphore * sem);
-extern inline void down(struct semaphore * sem)
-{
-        might_sleep();
-        /*
-         * Try to get the semaphore, take the slow path if we fail.
-         */
-        if (atomic_dec_return(&sem->count) < 0)
-                __down(sem);
-        smp_wmb();
-}
-extern inline int down_interruptible(struct semaphore * sem)
-{
-        int ret = 0;
-        might_sleep();
-        if (atomic_dec_return(&sem->count) < 0)
-                ret = __down_interruptible(sem);
-        smp_wmb();
-        return ret;
-}
-extern inline int down_trylock(struct semaphore * sem)
-{
-        int ret;
-        ret = atomic_dec_if_positive(&sem->count) < 0;
-        smp_wmb();
-        return ret;
-}
-extern inline void up(struct semaphore * sem)
-{
-        smp_wmb();
-        if (atomic_inc_return(&sem->count) <= 0)
-                __up(sem);
-}
-#endif /* __KERNEL__ */
-#endif /* !(_PPC_SEMAPHORE_H) */
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h
deleted file mode 100644
index b7a417e0a921..000000000000
--- a/include/asm-ppc/sigcontext.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ASM_PPC_SIGCONTEXT_H
-#define _ASM_PPC_SIGCONTEXT_H
-#include <asm/ptrace.h>
-#include <linux/compiler.h>
-struct sigcontext {
-        unsigned long   _unused[4];
-        int             signal;
-        unsigned long   handler;
-        unsigned long   oldmask;
-        struct pt_regs  __user *regs;
-};
-#endif
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h
index 829481c0a9dc..30e9268a888c 100644
--- a/include/asm-ppc/smp.h
+++ b/include/asm-ppc/smp.h
@@ -35,6 +35,7 @@ extern cpumask_t cpu_possible_map;
 extern unsigned long smp_proc_in_lock[];
 extern volatile unsigned long cpu_callin_map[];
 extern int smp_tb_synchronized;
+extern struct smp_ops_t *smp_ops;
 extern void smp_send_tlb_invalidate(int);
 extern void smp_send_xmon_break(int cpu);
@@ -45,32 +46,31 @@ extern int __cpu_disable(void);
 extern void __cpu_die(unsigned int cpu);
 extern void cpu_die(void) __attribute__((noreturn));
-#define NO_PROC_ID              0xFF            /* No processor magic marker */
-#define PROC_CHANGE_PENALTY     20
 #define raw_smp_processor_id()  (current_thread_info()->cpu)
 extern int __cpu_up(unsigned int cpu);
 extern int smp_hw_index[];
-#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()])
+#define hard_smp_processor_id()         (smp_hw_index[smp_processor_id()])
+#define get_hard_smp_processor_id(cpu)  (smp_hw_index[(cpu)])
-struct klock_info_struct {
+#define set_hard_smp_processor_id(cpu, phys)\
-        unsigned long kernel_flag;
+                                        (smp_hw_index[(cpu)] = (phys))
-        unsigned char akp;
+ 
-};
-extern struct klock_info_struct klock_info;
-#define KLOCK_HELD       0xffffffff
-#define KLOCK_CLEAR      0x0
 #endif /* __ASSEMBLY__ */
 #else /* !(CONFIG_SMP) */
 static inline void cpu_die(void) { }
+#define get_hard_smp_processor_id(cpu) 0
+#define set_hard_smp_processor_id(cpu, phys)
+#define hard_smp_processor_id() 0
 #endif /* !(CONFIG_SMP) */
+#ifndef __ASSEMBLY__
+extern int boot_cpuid;
+extern int boot_cpuid_phys;
+#endif
 #endif /* !(_PPC_SMP_H) */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h
index 20edcf2a6e0c..5c64b75f0295 100644
--- a/include/asm-ppc/spinlock.h
+++ b/include/asm-ppc/spinlock.h
@@ -9,7 +9,7 @@
 * (the type definitions are in asm/raw_spinlock_types.h)
 */
-#define __raw_spin_is_locked(x)         ((x)->lock != 0)
+#define __raw_spin_is_locked(x)         ((x)->slock != 0)
 #define __raw_spin_unlock_wait(lock) \
        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
@@ -31,17 +31,17 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
        bne-    2b\n\
        isync"
        : "=&r"(tmp)
-        : "r"(&lock->lock), "r"(1)
+        : "r"(&lock->slock), "r"(1)
        : "cr0", "memory");
 }
 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 {
        __asm__ __volatile__("eieio     # __raw_spin_unlock": : :"memory");
-        lock->lock = 0;
+        lock->slock = 0;
 }
-#define __raw_spin_trylock(l) (!test_and_set_bit(0,&(l)->lock))
+#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock)))
 /*
 * Read-write spinlocks, allowing multiple readers
diff --git a/include/asm-ppc/spinlock_types.h b/include/asm-ppc/spinlock_types.h
deleted file mode 100644
index 7919ccc75b8a..000000000000
--- a/include/asm-ppc/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-typedef struct {
-        volatile unsigned long lock;
-} raw_spinlock_t;
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
-typedef struct {
-        volatile signed int lock;
-} raw_rwlock_t;
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
-#endif
diff --git a/include/asm-ppc/stat.h b/include/asm-ppc/stat.h
deleted file mode 100644
index cadb34298496..000000000000
--- a/include/asm-ppc/stat.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _PPC_STAT_H
-#define _PPC_STAT_H
-#ifdef __KERNEL__
-#include <linux/types.h>
-#endif /* __KERNEL__ */
-struct __old_kernel_stat {
-        unsigned short st_dev;
-        unsigned short st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned short st_rdev;
-        unsigned long  st_size;
-        unsigned long  st_atime;
-        unsigned long  st_mtime;
-        unsigned long  st_ctime;
-};
-#define STAT_HAVE_NSEC 1
-struct stat {
-        unsigned        st_dev;
-        ino_t           st_ino;
-        mode_t          st_mode;
-        nlink_t         st_nlink;
-        uid_t           st_uid;
-        gid_t           st_gid;
-        unsigned        st_rdev;
-        off_t           st_size;
-        unsigned long   st_blksize;
-        unsigned long   st_blocks;
-        unsigned long   st_atime;
-        unsigned long   st_atime_nsec;
-        unsigned long   st_mtime;
-        unsigned long   st_mtime_nsec;
-        unsigned long   st_ctime;
-        unsigned long   st_ctime_nsec;
-        unsigned long   __unused4;
-        unsigned long   __unused5;
-};
-/* This matches struct stat64 in glibc2.1.
- */
-struct stat64 {
-        unsigned long long st_dev;      /* Device.  */
-        unsigned long long st_ino;      /* File serial number.  */
-        unsigned int st_mode;           /* File mode.  */
-        unsigned int st_nlink;          /* Link count.  */
-        unsigned int st_uid;            /* User ID of the file's owner.  */
-        unsigned int st_gid;            /* Group ID of the file's group. */
-        unsigned long long st_rdev;     /* Device number, if device.  */
-        unsigned short int __pad2;
-        long long st_size;              /* Size of file, in bytes.  */
-        long st_blksize;                /* Optimal block size for I/O.  */
-        long long st_blocks;            /* Number 512-byte blocks allocated. */
-        long st_atime;                  /* Time of last access.  */
-        unsigned long st_atime_nsec;
-        long st_mtime;                  /* Time of last modification.  */
-        unsigned long int st_mtime_nsec;
-        long st_ctime;                  /* Time of last status change.  */
-        unsigned long int st_ctime_nsec;
-        unsigned long int __unused4;
-        unsigned long int __unused5;
-};
-#endif
diff --git a/include/asm-ppc/statfs.h b/include/asm-ppc/statfs.h
deleted file mode 100644
index 807c69954a1b..000000000000
--- a/include/asm-ppc/statfs.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _PPC_STATFS_H
-#define _PPC_STATFS_H
-#include <asm-generic/statfs.h>
-#endif
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
index d754ab570fe0..bd99cb53a19f 100644
--- a/include/asm-ppc/system.h
+++ b/include/asm-ppc/system.h
@@ -70,25 +70,47 @@ extern void _set_L3CR(unsigned long);
 #endif
 extern void via_cuda_init(void);
 extern void pmac_nvram_init(void);
+extern void chrp_nvram_init(void);
 extern void read_rtc_time(void);
 extern void pmac_find_display(void);
 extern void giveup_fpu(struct task_struct *);
 extern void enable_kernel_fp(void);
+extern void flush_fp_to_thread(struct task_struct *);
 extern void enable_kernel_altivec(void);
 extern void giveup_altivec(struct task_struct *);
 extern void load_up_altivec(struct task_struct *);
+extern int emulate_altivec(struct pt_regs *);
 extern void giveup_spe(struct task_struct *);
 extern void load_up_spe(struct task_struct *);
 extern int fix_alignment(struct pt_regs *);
-extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
+extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
-extern void cvt_df(double *from, float *to, unsigned long *fpscr);
+extern void cvt_df(double *from, float *to, struct thread_struct *thread);
+#ifdef CONFIG_ALTIVEC
+extern void flush_altivec_to_thread(struct task_struct *);
+#else
+static inline void flush_altivec_to_thread(struct task_struct *t)
+{
+}
+#endif
+#ifdef CONFIG_SPE
+extern void flush_spe_to_thread(struct task_struct *);
+#else
+static inline void flush_spe_to_thread(struct task_struct *t)
+{
+}
+#endif
 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 extern void cacheable_memzero(void *p, unsigned int nb);
 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
-extern void die(const char *, struct pt_regs *, long);
+extern int die(const char *, struct pt_regs *, long);
 extern void _exception(int, struct pt_regs *, int, unsigned long);
+void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #ifdef CONFIG_BOOKE_WDT
 extern u32 booke_wdt_enabled;
 extern u32 booke_wdt_period;
diff --git a/include/asm-ppc/thread_info.h b/include/asm-ppc/thread_info.h
deleted file mode 100644
index 27903db42efc..000000000000
--- a/include/asm-ppc/thread_info.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* thread_info.h: PPC low-level thread information
- * adapted from the i386 version by Paul Mackerras
- *
- * Copyright (C) 2002  David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- */
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-struct thread_info {
-        struct task_struct      *task;          /* main task structure */
-        struct exec_domain      *exec_domain;   /* execution domain */
-        unsigned long           flags;          /* low level flags */
-        unsigned long           local_flags;    /* non-racy flags */
-        int                     cpu;            /* cpu we're on */
-        int                     preempt_count;  /* 0 => preemptable,
-                                                   <0 => BUG */
-        struct restart_block    restart_block;
-};
-#define INIT_THREAD_INFO(tsk)                   \
-{                                               \
-        .task =         &tsk,                   \
-        .exec_domain =  &default_exec_domain,   \
-        .flags =        0,                      \
-        .local_flags =  0,                      \
-        .cpu =          0,                      \
-        .preempt_count = 1,                     \
-        .restart_block = {                      \
-                .fn = do_no_restart_syscall,    \
-        },                                      \
-}
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-/*
- * macros/functions for gaining access to the thread information structure
- */
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
-        struct thread_info *ti;
-        __asm__("rlwinm %0,1,0,0,18" : "=r"(ti));
-        return ti;
-}
-/* thread information allocation */
-#define alloc_thread_info(tsk) ((struct thread_info *) \
-                                __get_free_pages(GFP_KERNEL, 1))
-#define free_thread_info(ti)    free_pages((unsigned long) (ti), 1)
-#define get_thread_info(ti)     get_task_struct((ti)->task)
-#define put_thread_info(ti)     put_task_struct((ti)->task)
-#endif /* __ASSEMBLY__ */
-/*
- * Size of kernel stack for each process.
- */
-#define THREAD_SIZE             8192    /* 2 pages */
-#define PREEMPT_ACTIVE          0x10000000
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
-#define TIF_NOTIFY_RESUME       1       /* resumption notification requested */
-#define TIF_SIGPENDING          2       /* signal pending */
-#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
-#define TIF_POLLING_NRFLAG      4       /* true if poll_idle() is polling
-                                           TIF_NEED_RESCHED */
-#define TIF_MEMDIE              5
-#define TIF_SYSCALL_AUDIT       6       /* syscall auditing active */
-#define TIF_SECCOMP             7      /* secure computing */
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
-#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
-#define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
-/*
- * Non racy (local) flags bit numbers
- */
-#define TIFL_FORCE_NOERROR      0       /* don't return error from current
-                                           syscall even if result < 0 */
-/* as above, but as bit values */
-#define _TIFL_FORCE_NOERROR     (1<<TIFL_FORCE_NOERROR)
-#endif /* __KERNEL__ */
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-ppc/tlbflush.h b/include/asm-ppc/tlbflush.h
deleted file mode 100644
index 9afee4ffc835..000000000000
--- a/include/asm-ppc/tlbflush.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * include/asm-ppc/tlbflush.h
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifdef __KERNEL__
-#ifndef _PPC_TLBFLUSH_H
-#define _PPC_TLBFLUSH_H
-#include <linux/config.h>
-#include <linux/mm.h>
-extern void _tlbie(unsigned long address);
-extern void _tlbia(void);
-#if defined(CONFIG_4xx)
-#ifndef CONFIG_44x
-#define __tlbia()       asm volatile ("sync; tlbia; isync" : : : "memory")
-#else
-#define __tlbia         _tlbia
-#endif
-static inline void flush_tlb_mm(struct mm_struct *mm)
-        { __tlbia(); }
-static inline void flush_tlb_page(struct vm_area_struct *vma,
-                                unsigned long vmaddr)
-        { _tlbie(vmaddr); }
-static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
-                                         unsigned long vmaddr)
-        { _tlbie(vmaddr); }
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-                                unsigned long start, unsigned long end)
-        { __tlbia(); }
-static inline void flush_tlb_kernel_range(unsigned long start,
-                                unsigned long end)
-        { __tlbia(); }
-#elif defined(CONFIG_FSL_BOOKE)
-/* TODO: determine if flush_tlb_range & flush_tlb_kernel_range
- * are best implemented as tlbia vs specific tlbie's */
-#define __tlbia()       _tlbia()
-static inline void flush_tlb_mm(struct mm_struct *mm)
-        { __tlbia(); }
-static inline void flush_tlb_page(struct vm_area_struct *vma,
-                                unsigned long vmaddr)
-        { _tlbie(vmaddr); }
-static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
-                                         unsigned long vmaddr)
-        { _tlbie(vmaddr); }
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-                                unsigned long start, unsigned long end)
-        { __tlbia(); }
-static inline void flush_tlb_kernel_range(unsigned long start,
-                                unsigned long end)
-        { __tlbia(); }
-#elif defined(CONFIG_8xx)
-#define __tlbia()       asm volatile ("tlbia; sync" : : : "memory")
-static inline void flush_tlb_mm(struct mm_struct *mm)
-        { __tlbia(); }
-static inline void flush_tlb_page(struct vm_area_struct *vma,
-                                unsigned long vmaddr)
-        { _tlbie(vmaddr); }
-static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
-                                         unsigned long vmaddr)
-        { _tlbie(vmaddr); }
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-                                unsigned long start, unsigned long end)
-        { __tlbia(); }
-static inline void flush_tlb_kernel_range(unsigned long start,
-                                unsigned long end)
-        { __tlbia(); }
-#else   /* 6xx, 7xx, 7xxx cpus */
-struct mm_struct;
-struct vm_area_struct;
-extern void flush_tlb_mm(struct mm_struct *mm);
-extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
-extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
-extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-                            unsigned long end);
-extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
-#endif
-/*
- * This is called in munmap when we have freed up some page-table
- * pages.  We don't need to do anything here, there's nothing special
- * about our page-table pages.  -- paulus
- */
-static inline void flush_tlb_pgtables(struct mm_struct *mm,
-                                      unsigned long start, unsigned long end)
-{
-}
-/*
- * This gets called at the end of handling a page fault, when
- * the kernel has put a new PTE into the page table for the process.
- * We use it to ensure coherency between the i-cache and d-cache
- * for the page which has just been mapped in.
- * On machines which use an MMU hash table, we use this to put a
- * corresponding HPTE into the hash table ahead of time, instead of
- * waiting for the inevitable extra hash-table miss exception.
- */
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
-#endif /* _PPC_TLBFLUSH_H */
-#endif /*__KERNEL__ */
diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h
deleted file mode 100644
index 77dc24d7d2ad..000000000000
--- a/include/asm-ppc/types.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _PPC_TYPES_H
-#define _PPC_TYPES_H
-#ifndef __ASSEMBLY__
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
-#endif
-typedef struct {
-        __u32 u[4];
-} __vector128;
-/*
- * XXX allowed outside of __KERNEL__ for now, until glibc gets
- * a proper set of asm headers of its own.  -- paulus
- */
-typedef unsigned short umode_t;
-#endif /* __ASSEMBLY__ */
-#ifdef __KERNEL__
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#define BITS_PER_LONG 32
-#ifndef __ASSEMBLY__
-#include <linux/config.h>
-typedef signed char s8;
-typedef unsigned char u8;
-typedef signed short s16;
-typedef unsigned short u16;
-typedef signed int s32;
-typedef unsigned int u32;
-typedef signed long long s64;
-typedef unsigned long long u64;
-typedef __vector128 vector128;
-/* DMA addresses are 32-bits wide */
-typedef u32 dma_addr_t;
-typedef u64 dma64_addr_t;
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif
diff --git a/include/asm-ppc/uaccess.h b/include/asm-ppc/uaccess.h
deleted file mode 100644
index 63f56224da8c..000000000000
--- a/include/asm-ppc/uaccess.h
+++ /dev/null
@@ -1,393 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_UACCESS_H
-#define _PPC_UACCESS_H
-#ifndef __ASSEMBLY__
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <asm/processor.h>
-#define VERIFY_READ     0
-#define VERIFY_WRITE    1
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- *
- * The fs/ds values are now the highest legal address in the "segment".
- * This simplifies the checking in the routines below.
- */
-#define KERNEL_DS       ((mm_segment_t) { ~0UL })
-#define USER_DS         ((mm_segment_t) { TASK_SIZE - 1 })
-#define get_ds()        (KERNEL_DS)
-#define get_fs()        (current->thread.fs)
-#define set_fs(val)     (current->thread.fs = (val))
-#define segment_eq(a,b) ((a).seg == (b).seg)
-#define __access_ok(addr,size)                                              \
-        ((addr) <= current->thread.fs.seg                                   \
-         && ((size) == 0 || (size) - 1 <= current->thread.fs.seg - (addr)))
-#define access_ok(type, addr, size) \
-        (__chk_user_ptr(addr),__access_ok((unsigned long)(addr),(size)))
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-struct exception_table_entry
-{
-        unsigned long insn, fixup;
-};
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- *
- * As we use the same address space for kernel and user data on the
- * PowerPC, we can just do these as direct assignments.  (Of course, the
- * exception handling means that it's no longer "just"...)
- *
- * The "user64" versions of the user access functions are versions that 
- * allow access of 64-bit data. The "get_user" functions do not 
- * properly handle 64-bit data because the value gets down cast to a long. 
- * The "put_user" functions already handle 64-bit data properly but we add 
- * "user64" versions for completeness
- */
-#define get_user(x,ptr) \
-  __get_user_check((x),(ptr),sizeof(*(ptr)))
-#define get_user64(x,ptr) \
-  __get_user64_check((x),(ptr),sizeof(*(ptr)))
-#define put_user(x,ptr) \
-  __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
-#define put_user64(x,ptr) put_user(x,ptr)
-#define __get_user(x,ptr) \
-  __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
-#define __get_user64(x,ptr) \
-  __get_user64_nocheck((x),(ptr),sizeof(*(ptr)))
-#define __put_user(x,ptr) \
-  __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
-#define __put_user64(x,ptr) __put_user(x,ptr)
-extern long __put_user_bad(void);
-#define __put_user_nocheck(x,ptr,size)                  \
-({                                                      \
-        long __pu_err;                                  \
-        __chk_user_ptr(ptr);                            \
-        __put_user_size((x),(ptr),(size),__pu_err);     \
-        __pu_err;                                       \
-})
-#define __put_user_check(x,ptr,size)                            \
-({                                                              \
-        long __pu_err = -EFAULT;                                \
-        __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
-        if (access_ok(VERIFY_WRITE,__pu_addr,size))             \
-                __put_user_size((x),__pu_addr,(size),__pu_err); \
-        __pu_err;                                               \
-})
-#define __put_user_size(x,ptr,size,retval)              \
-do {                                                    \
-        retval = 0;                                     \
-        switch (size) {                                 \
-        case 1:                                         \
-                __put_user_asm(x, ptr, retval, "stb");  \
-                break;                                  \
-        case 2:                                         \
-                __put_user_asm(x, ptr, retval, "sth");  \
-                break;                                  \
-        case 4:                                         \
-                __put_user_asm(x, ptr, retval, "stw");  \
-                break;                                  \
-        case 8:                                         \
-                __put_user_asm2(x, ptr, retval);        \
-                break;                                  \
-        default:                                        \
-                __put_user_bad();                       \
-        }                                               \
-} while (0)
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- */
-#define __put_user_asm(x, addr, err, op)                        \
-        __asm__ __volatile__(                                   \
-                "1:     "op" %1,0(%2)\n"                        \
-                "2:\n"                                          \
-                ".section .fixup,\"ax\"\n"                      \
-                "3:     li %0,%3\n"                             \
-                "       b 2b\n"                                 \
-                ".previous\n"                                   \
-                ".section __ex_table,\"a\"\n"                   \
-                "       .align 2\n"                             \
-                "       .long 1b,3b\n"                          \
-                ".previous"                                     \
-                : "=r" (err)                                    \
-                : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
-#define __put_user_asm2(x, addr, err)                           \
-        __asm__ __volatile__(                                   \
-                "1:     stw %1,0(%2)\n"                         \
-                "2:     stw %1+1,4(%2)\n"                       \
-                "3:\n"                                          \
-                ".section .fixup,\"ax\"\n"                      \
-                "4:     li %0,%3\n"                             \
-                "       b 3b\n"                                 \
-                ".previous\n"                                   \
-                ".section __ex_table,\"a\"\n"                   \
-                "       .align 2\n"                             \
-                "       .long 1b,4b\n"                          \
-                "       .long 2b,4b\n"                          \
-                ".previous"                                     \
-                : "=r" (err)                                    \
-                : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
-#define __get_user_nocheck(x, ptr, size)                        \
-({                                                              \
-        long __gu_err;                                          \
-        unsigned long __gu_val;                                 \
-        __chk_user_ptr(ptr);                                    \
-        __get_user_size(__gu_val, (ptr), (size), __gu_err);     \
-        (x) = (__typeof__(*(ptr)))__gu_val;                     \
-        __gu_err;                                               \
-})
-#define __get_user64_nocheck(x, ptr, size)                      \
-({                                                              \
-        long __gu_err;                                          \
-        long long __gu_val;                                     \
-        __chk_user_ptr(ptr);                                    \
-        __get_user_size64(__gu_val, (ptr), (size), __gu_err);   \
-        (x) = (__typeof__(*(ptr)))__gu_val;                     \
-        __gu_err;                                               \
-})
-#define __get_user_check(x, ptr, size)                                  \
-({                                                                      \
-        long __gu_err = -EFAULT;                                        \
-        unsigned long  __gu_val = 0;                                    \
-        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);             \
-        if (access_ok(VERIFY_READ, __gu_addr, (size)))                  \
-                __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
-        (x) = (__typeof__(*(ptr)))__gu_val;                             \
-        __gu_err;                                                       \
-})
-#define __get_user64_check(x, ptr, size)                                  \
-({                                                                        \
-        long __gu_err = -EFAULT;                                          \
-        long long __gu_val = 0;                                           \
-        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);               \
-        if (access_ok(VERIFY_READ, __gu_addr, (size)))                    \
-                __get_user_size64(__gu_val, __gu_addr, (size), __gu_err); \
-        (x) = (__typeof__(*(ptr)))__gu_val;                               \
-        __gu_err;                                                         \
-})
-extern long __get_user_bad(void);
-#define __get_user_size(x, ptr, size, retval)                   \
-do {                                                            \
-        retval = 0;                                             \
-        switch (size) {                                         \
-        case 1:                                                 \
-                __get_user_asm(x, ptr, retval, "lbz");          \
-                break;                                          \
-        case 2:                                                 \
-                __get_user_asm(x, ptr, retval, "lhz");          \
-                break;                                          \
-        case 4:                                                 \
-                __get_user_asm(x, ptr, retval, "lwz");          \
-                break;                                          \
-        default:                                                \
-                x = __get_user_bad();                           \
-        }                                                       \
-} while (0)
-#define __get_user_size64(x, ptr, size, retval)                 \
-do {                                                            \
-        retval = 0;                                             \
-        switch (size) {                                         \
-        case 1:                                                 \
-                __get_user_asm(x, ptr, retval, "lbz");          \
-                break;                                          \
-        case 2:                                                 \
-                __get_user_asm(x, ptr, retval, "lhz");          \
-                break;                                          \
-        case 4:                                                 \
-                __get_user_asm(x, ptr, retval, "lwz");          \
-                break;                                          \
-        case 8:                                                 \
-                __get_user_asm2(x, ptr, retval);                \
-                break;                                          \
-        default:                                                \
-                x = __get_user_bad();                           \
-        }                                                       \
-} while (0)
-#define __get_user_asm(x, addr, err, op)                \
-        __asm__ __volatile__(                           \
-                "1:     "op" %1,0(%2)\n"                \
-                "2:\n"                                  \
-                ".section .fixup,\"ax\"\n"              \
-                "3:     li %0,%3\n"                     \
-                "       li %1,0\n"                      \
-                "       b 2b\n"                         \
-                ".previous\n"                           \
-                ".section __ex_table,\"a\"\n"           \
-                "       .align 2\n"                     \
-                "       .long 1b,3b\n"                  \
-                ".previous"                             \
-                : "=r"(err), "=r"(x)                    \
-                : "b"(addr), "i"(-EFAULT), "0"(err))
-#define __get_user_asm2(x, addr, err)                   \
-        __asm__ __volatile__(                           \
-                "1:     lwz %1,0(%2)\n"                 \
-                "2:     lwz %1+1,4(%2)\n"               \
-                "3:\n"                                  \
-                ".section .fixup,\"ax\"\n"              \
-                "4:     li %0,%3\n"                     \
-                "       li %1,0\n"                      \
-                "       li %1+1,0\n"                    \
-                "       b 3b\n"                         \
-                ".previous\n"                           \
-                ".section __ex_table,\"a\"\n"           \
-                "       .align 2\n"                     \
-                "       .long 1b,4b\n"                  \
-                "       .long 2b,4b\n"                  \
-                ".previous"                             \
-                : "=r"(err), "=&r"(x)                   \
-                : "b"(addr), "i"(-EFAULT), "0"(err))
-/* more complex routines */
-extern int __copy_tofrom_user(void __user *to, const void __user *from,
-                              unsigned long size);
-extern inline unsigned long
-copy_from_user(void *to, const void __user *from, unsigned long n)
-{
-        unsigned long over;
-        if (access_ok(VERIFY_READ, from, n))
-                return __copy_tofrom_user((__force void __user *)to, from, n);
-        if ((unsigned long)from < TASK_SIZE) {
-                over = (unsigned long)from + n - TASK_SIZE;
-                return __copy_tofrom_user((__force void __user *)to, from, n - over) + over;
-        }
-        return n;
-}
-extern inline unsigned long
-copy_to_user(void __user *to, const void *from, unsigned long n)
-{
-        unsigned long over;
-        if (access_ok(VERIFY_WRITE, to, n))
-                return __copy_tofrom_user(to, (__force void __user *) from, n);
-        if ((unsigned long)to < TASK_SIZE) {
-                over = (unsigned long)to + n - TASK_SIZE;
-                return __copy_tofrom_user(to, (__force void __user *) from, n - over) + over;
-        }
-        return n;
-}
-static inline unsigned long __copy_from_user(void *to, const void __user *from, unsigned long size)
-{
-        return __copy_tofrom_user((__force void __user *)to, from, size);
-}
-static inline unsigned long __copy_to_user(void __user *to, const void *from, unsigned long size)
-{
-        return __copy_tofrom_user(to, (__force void __user *)from, size);
-}
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-extern unsigned long __clear_user(void __user *addr, unsigned long size);
-extern inline unsigned long
-clear_user(void __user *addr, unsigned long size)
-{
-        if (access_ok(VERIFY_WRITE, addr, size))
-                return __clear_user(addr, size);
-        if ((unsigned long)addr < TASK_SIZE) {
-                unsigned long over = (unsigned long)addr + size - TASK_SIZE;
-                return __clear_user(addr, size - over) + over;
-        }
-        return size;
-}
-extern int __strncpy_from_user(char *dst, const char __user *src, long count);
-extern inline long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        if (access_ok(VERIFY_READ, src, 1))
-                return __strncpy_from_user(dst, src, count);
-        return -EFAULT;
-}
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 for error
- */
-extern int __strnlen_user(const char __user *str, long len, unsigned long top);
-/*
- * Returns the length of the string at str (including the null byte),
- * or 0 if we hit a page we can't access,
- * or something > len if we didn't find a null byte.
- *
- * The `top' parameter to __strnlen_user is to make sure that
- * we can never overflow from the user area into kernel space.
- */
-extern __inline__ int strnlen_user(const char __user *str, long len)
-{
-        unsigned long top = current->thread.fs.seg;
-        if ((unsigned long)str > top)
-                return 0;
-        return __strnlen_user(str, len, top);
-}
-#define strlen_user(str)        strnlen_user((str), 0x7ffffffe)
-#endif  /* __ASSEMBLY__ */
-#endif  /* _PPC_UACCESS_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ucontext.h b/include/asm-ppc/ucontext.h
deleted file mode 100644
index 664bc984d51f..000000000000
--- a/include/asm-ppc/ucontext.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _ASMPPC_UCONTEXT_H
-#define _ASMPPC_UCONTEXT_H
-#include <asm/elf.h>
-#include <asm/signal.h>
-struct mcontext {
-        elf_gregset_t   mc_gregs;
-        elf_fpregset_t  mc_fregs;
-        unsigned long   mc_pad[2];
-        elf_vrregset_t  mc_vregs __attribute__((__aligned__(16)));
-};
-struct ucontext {
-        unsigned long    uc_flags;
-        struct ucontext __user *uc_link;
-        stack_t          uc_stack;
-        int              uc_pad[7];
-        struct mcontext __user *uc_regs;/* points to uc_mcontext field */
-        sigset_t         uc_sigmask;
-        /* glibc has 1024-bit signal masks, ours are 64-bit */
-        int              uc_maskext[30];
-        int              uc_pad2[3];
-        struct mcontext  uc_mcontext;
-};
-#endif /* !_ASMPPC_UCONTEXT_H */
diff --git a/include/asm-ppc/vga.h b/include/asm-ppc/vga.h
deleted file mode 100644
index c5864734e3e1..000000000000
--- a/include/asm-ppc/vga.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *      Access to VGA videoram
- *
- *      (c) 1998 Martin Mares <mj@ucw.cz>
- */
-#ifdef __KERNEL__
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
-#include <asm/io.h>
-#include <linux/config.h>
-#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
-#define VT_BUF_HAVE_RW
-/*
- *  These are only needed for supporting VGA or MDA text mode, which use little
- *  endian byte ordering.
- *  In other cases, we can optimize by using native byte ordering and
- *  <linux/vt_buffer.h> has already done the right job for us.
- */
-extern inline void scr_writew(u16 val, volatile u16 *addr)
-{
-    st_le16(addr, val);
-}
-extern inline u16 scr_readw(volatile const u16 *addr)
-{
-    return ld_le16(addr);
-}
-#define VT_BUF_HAVE_MEMCPYW
-#define scr_memcpyw     memcpy
-#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
-extern unsigned long vgacon_remap_base;
-#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
-#define vga_readb(x) (*(x))
-#define vga_writeb(x,y) (*(y) = (x))
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/xmon.h b/include/asm-ppc/xmon.h
deleted file mode 100644
index 042b83e6680d..000000000000
--- a/include/asm-ppc/xmon.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __PPC_XMON_H
-#define __PPC_XMON_H
-#ifdef __KERNEL__
-struct pt_regs;
-extern void xmon(struct pt_regs *excp);
-extern void xmon_printf(const char *fmt, ...);
-extern void xmon_map_scc(void);
-extern int xmon_bpt(struct pt_regs *regs);
-extern int xmon_sstep(struct pt_regs *regs);
-extern int xmon_iabr_match(struct pt_regs *regs);
-extern int xmon_dabr_match(struct pt_regs *regs);
-extern void (*xmon_fault_handler)(struct pt_regs *regs);
-#endif
-#endif
diff --git a/include/asm-ppc64/abs_addr.h b/include/asm-ppc64/abs_addr.h
index 84c24d4cdb71..dc3fc3fefef2 100644
--- a/include/asm-ppc64/abs_addr.h
+++ b/include/asm-ppc64/abs_addr.h
@@ -63,4 +63,11 @@ static inline unsigned long phys_to_abs(unsigned long pa)
 #define virt_to_abs(va) phys_to_abs(__pa(va))
 #define abs_to_virt(aa) __va(aa)
+/*
+ * Converts Virtual Address to Real Address for
+ * Legacy iSeries Hypervisor calls
+ */
+#define iseries_hv_addr(virtaddr)       \
+        (0x8000000000000000 | virt_to_abs(virtaddr))
 #endif /* _ABS_ADDR_H */
diff --git a/include/asm-ppc64/atomic.h b/include/asm-ppc64/atomic.h
deleted file mode 100644
index 0e5f25e83bc0..000000000000
--- a/include/asm-ppc64/atomic.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * PowerPC64 atomic operations
- *
- * Copyright (C) 2001 Paul Mackerras <paulus@au.ibm.com>, IBM
- * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_PPC64_ATOMIC_H_ 
-#define _ASM_PPC64_ATOMIC_H_
-#include <asm/memory.h>
-typedef struct { volatile int counter; } atomic_t;
-#define ATOMIC_INIT(i)  { (i) }
-#define atomic_read(v)          ((v)->counter)
-#define atomic_set(v,i)         (((v)->counter) = (i))
-static __inline__ void atomic_add(int a, atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-"1:     lwarx   %0,0,%3         # atomic_add\n\
-        add     %0,%2,%0\n\
-        stwcx.  %0,0,%3\n\
-        bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (a), "r" (&v->counter), "m" (v->counter)
-        : "cc");
-}
-static __inline__ int atomic_add_return(int a, atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%2         # atomic_add_return\n\
-        add     %0,%1,%0\n\
-        stwcx.  %0,0,%2\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (t)
-        : "r" (a), "r" (&v->counter)
-        : "cc", "memory");
-        return t;
-}
-#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-static __inline__ void atomic_sub(int a, atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-"1:     lwarx   %0,0,%3         # atomic_sub\n\
-        subf    %0,%2,%0\n\
-        stwcx.  %0,0,%3\n\
-        bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (a), "r" (&v->counter), "m" (v->counter)
-        : "cc");
-}
-static __inline__ int atomic_sub_return(int a, atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%2         # atomic_sub_return\n\
-        subf    %0,%1,%0\n\
-        stwcx.  %0,0,%2\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (t)
-        : "r" (a), "r" (&v->counter)
-        : "cc", "memory");
-        return t;
-}
-static __inline__ void atomic_inc(atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-"1:     lwarx   %0,0,%2         # atomic_inc\n\
-        addic   %0,%0,1\n\
-        stwcx.  %0,0,%2\n\
-        bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (&v->counter), "m" (v->counter)
-        : "cc");
-}
-static __inline__ int atomic_inc_return(atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%1         # atomic_inc_return\n\
-        addic   %0,%0,1\n\
-        stwcx.  %0,0,%1\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (t)
-        : "r" (&v->counter)
-        : "cc", "memory");
-        return t;
-}
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-static __inline__ void atomic_dec(atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-"1:     lwarx   %0,0,%2         # atomic_dec\n\
-        addic   %0,%0,-1\n\
-        stwcx.  %0,0,%2\n\
-        bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (&v->counter), "m" (v->counter)
-        : "cc");
-}
-static __inline__ int atomic_dec_return(atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%1         # atomic_dec_return\n\
-        addic   %0,%0,-1\n\
-        stwcx.  %0,0,%1\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (t)
-        : "r" (&v->counter)
-        : "cc", "memory");
-        return t;
-}
-#define atomic_sub_and_test(a, v)       (atomic_sub_return((a), (v)) == 0)
-#define atomic_dec_and_test(v)          (atomic_dec_return((v)) == 0)
-/*
- * Atomically test *v and decrement if it is greater than 0.
- * The function returns the old value of *v minus 1.
- */
-static __inline__ int atomic_dec_if_positive(atomic_t *v)
-{
-        int t;
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
-        addic.  %0,%0,-1\n\
-        blt-    2f\n\
-        stwcx.  %0,0,%1\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        "\n\
-2:"     : "=&r" (t)
-        : "r" (&v->counter)
-        : "cc", "memory");
-        return t;
-}
-#define smp_mb__before_atomic_dec()     smp_mb()
-#define smp_mb__after_atomic_dec()      smp_mb()
-#define smp_mb__before_atomic_inc()     smp_mb()
-#define smp_mb__after_atomic_inc()      smp_mb()
-#endif /* _ASM_PPC64_ATOMIC_H_ */
diff --git a/include/asm-ppc64/bitops.h b/include/asm-ppc64/bitops.h
deleted file mode 100644
index a0f831224f96..000000000000
--- a/include/asm-ppc64/bitops.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * PowerPC64 atomic bit operations.
- * Dave Engebretsen, Todd Inglett, Don Reed, Pat McCarthy, Peter Bergner,
- * Anton Blanchard
- *
- * Originally taken from the 32b PPC code.  Modified to use 64b values for
- * the various counters & memory references.
- *
- * Bitops are odd when viewed on big-endian systems.  They were designed
- * on little endian so the size of the bitset doesn't matter (low order bytes
- * come first) as long as the bit in question is valid.
- *
- * Bits are "tested" often using the C expression (val & (1<<nr)) so we do
- * our best to stay compatible with that.  The assumption is that val will
- * be unsigned long for such tests.  As such, we assume the bits are stored
- * as an array of unsigned long (the usual case is a single unsigned long,
- * of course).  Here's an example bitset with bit numbering:
- *
- *   |63..........0|127........64|195.......128|255.......196|
- *
- * This leads to a problem. If an int, short or char is passed as a bitset
- * it will be a bad memory reference since we want to store in chunks
- * of unsigned long (64 bits here) size.
- *
- * There are a few little-endian macros used mostly for filesystem bitmaps,
- * these work on similar bit arrays layouts, but byte-oriented:
- *
- *   |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
- *
- * The main difference is that bit 3-5 in the bit number field needs to be
- * reversed compared to the big-endian bit fields. This can be achieved
- * by XOR with 0b111000 (0x38).
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _PPC64_BITOPS_H
-#define _PPC64_BITOPS_H
-#ifdef __KERNEL__
-#include <asm/memory.h>
-/*
- * clear_bit doesn't imply a memory barrier
- */
-#define smp_mb__before_clear_bit()      smp_mb()
-#define smp_mb__after_clear_bit()       smp_mb()
-static __inline__ int test_bit(unsigned long nr, __const__ volatile unsigned long *addr)
-{
-        return (1UL & (addr[nr >> 6] >> (nr & 63)));
-}
-static __inline__ void set_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long old;
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        __asm__ __volatile__(
-"1:     ldarx   %0,0,%3         # set_bit\n\
-        or      %0,%0,%2\n\
-        stdcx.  %0,0,%3\n\
-        bne-    1b"
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-}
-static __inline__ void clear_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long old;
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        __asm__ __volatile__(
-"1:     ldarx   %0,0,%3         # clear_bit\n\
-        andc    %0,%0,%2\n\
-        stdcx.  %0,0,%3\n\
-        bne-    1b"
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-}
-static __inline__ void change_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long old;
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        __asm__ __volatile__(
-"1:     ldarx   %0,0,%3         # change_bit\n\
-        xor     %0,%0,%2\n\
-        stdcx.  %0,0,%3\n\
-        bne-    1b"
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-}
-static __inline__ int test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long old, t;
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     ldarx   %0,0,%3         # test_and_set_bit\n\
-        or      %1,%0,%2 \n\
-        stdcx.  %1,0,%3 \n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-        return (old & mask) != 0;
-}
-static __inline__ int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long old, t;
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     ldarx   %0,0,%3         # test_and_clear_bit\n\
-        andc    %1,%0,%2\n\
-        stdcx.  %1,0,%3\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-        return (old & mask) != 0;
-}
-static __inline__ int test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long old, t;
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        __asm__ __volatile__(
-        EIEIO_ON_SMP
-"1:     ldarx   %0,0,%3         # test_and_change_bit\n\
-        xor     %1,%0,%2\n\
-        stdcx.  %1,0,%3\n\
-        bne-    1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-        return (old & mask) != 0;
-}
-static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
-{
-        unsigned long old;
-        __asm__ __volatile__(
-"1:     ldarx   %0,0,%3         # set_bit\n\
-        or      %0,%0,%2\n\
-        stdcx.  %0,0,%3\n\
-        bne-    1b"
-        : "=&r" (old), "=m" (*addr)
-        : "r" (mask), "r" (addr), "m" (*addr)
-        : "cc");
-}
-/*
- * non-atomic versions
- */
-static __inline__ void __set_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        *p |= mask;
-}
-static __inline__ void __clear_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        *p &= ~mask;
-}
-static __inline__ void __change_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        *p ^= mask;
-}
-static __inline__ int __test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        unsigned long old = *p;
-        *p = old | mask;
-        return (old & mask) != 0;
-}
-static __inline__ int __test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        unsigned long old = *p;
-        *p = old & ~mask;
-        return (old & mask) != 0;
-}
-static __inline__ int __test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long mask = 1UL << (nr & 0x3f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 6);
-        unsigned long old = *p;
-        *p = old ^ mask;
-        return (old & mask) != 0;
-}
-/*
- * Return the zero-based bit position (from RIGHT TO LEFT, 63 -> 0) of the
- * most significant (left-most) 1-bit in a double word.
- */
-static __inline__ int __ilog2(unsigned long x)
-{
-        int lz;
-        asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
-        return 63 - lz;
-}
-/*
- * Determines the bit position of the least significant (rightmost) 0 bit
- * in the specified double word. The returned bit position will be zero-based,
- * starting from the right side (63 - 0).
- */
-static __inline__ unsigned long ffz(unsigned long x)
-{
-        /* no zero exists anywhere in the 8 byte area. */
-        if ((x = ~x) == 0)
-                return 64;
-        /*
-         * Calculate the bit position of the least signficant '1' bit in x
-         * (since x has been changed this will actually be the least signficant
-         * '0' bit in * the original x).  Note: (x & -x) gives us a mask that
-         * is the least significant * (RIGHT-most) 1-bit of the value in x.
-         */
-        return __ilog2(x & -x);
-}
-static __inline__ int __ffs(unsigned long x)
-{
-        return __ilog2(x & -x);
-}
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int ffs(int x)
-{
-        unsigned long i = (unsigned long)x;
-        return __ilog2(i & -i) + 1;
-}
-/*
- * fls: find last (most-significant) bit set.
- * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
- */
-#define fls(x) generic_fls(x)
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-#define hweight64(x) generic_hweight64(x)
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-extern unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, unsigned long offset);
-#define find_first_zero_bit(addr, size) \
-        find_next_zero_bit((addr), (size), 0)
-extern unsigned long find_next_bit(const unsigned long *addr, unsigned long size, unsigned long offset);
-#define find_first_bit(addr, size) \
-        find_next_bit((addr), (size), 0)
-extern unsigned long find_next_zero_le_bit(const unsigned long *addr, unsigned long size, unsigned long offset);
-#define find_first_zero_le_bit(addr, size) \
-        find_next_zero_le_bit((addr), (size), 0)
-static __inline__ int test_le_bit(unsigned long nr, __const__ unsigned long * addr)
-{
-        __const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
-        return (ADDR[nr >> 3] >> (nr & 7)) & 1;
-}
-#define test_and_clear_le_bit(nr, addr) \
-        test_and_clear_bit((nr) ^ 0x38, (addr))
-#define test_and_set_le_bit(nr, addr) \
-        test_and_set_bit((nr) ^ 0x38, (addr))
-/*
- * non-atomic versions
- */
-#define __set_le_bit(nr, addr) \
-        __set_bit((nr) ^ 0x38, (addr))
-#define __clear_le_bit(nr, addr) \
-        __clear_bit((nr) ^ 0x38, (addr))
-#define __test_and_clear_le_bit(nr, addr) \
-        __test_and_clear_bit((nr) ^ 0x38, (addr))
-#define __test_and_set_le_bit(nr, addr) \
-        __test_and_set_bit((nr) ^ 0x38, (addr))
-#define ext2_set_bit(nr,addr) \
-        __test_and_set_le_bit((nr), (unsigned long*)addr)
-#define ext2_clear_bit(nr, addr) \
-        __test_and_clear_le_bit((nr), (unsigned long*)addr)
-#define ext2_set_bit_atomic(lock, nr, addr) \
-        test_and_set_le_bit((nr), (unsigned long*)addr)
-#define ext2_clear_bit_atomic(lock, nr, addr) \
-        test_and_clear_le_bit((nr), (unsigned long*)addr)
-#define ext2_test_bit(nr, addr)      test_le_bit((nr),(unsigned long*)addr)
-#define ext2_find_first_zero_bit(addr, size) \
-        find_first_zero_le_bit((unsigned long*)addr, size)
-#define ext2_find_next_zero_bit(addr, size, off) \
-        find_next_zero_le_bit((unsigned long*)addr, size, off)
-#define minix_test_and_set_bit(nr,addr)         test_and_set_bit(nr,addr)
-#define minix_set_bit(nr,addr)                  set_bit(nr,addr)
-#define minix_test_and_clear_bit(nr,addr)       test_and_clear_bit(nr,addr)
-#define minix_test_bit(nr,addr)                 test_bit(nr,addr)
-#define minix_find_first_zero_bit(addr,size)    find_first_zero_bit(addr,size)
-#endif /* __KERNEL__ */
-#endif /* _PPC64_BITOPS_H */
diff --git a/include/asm-ppc64/bootinfo.h b/include/asm-ppc64/bootinfo.h
deleted file mode 100644
index f55e7cb48f46..000000000000
--- a/include/asm-ppc64/bootinfo.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Non-machine dependent bootinfo structure.  Basic idea
- * borrowed from the m68k.
- *
- * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
- * Copyright (c) 2001 PPC64 Team, IBM Corp 
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _PPC64_BOOTINFO_H
-#define _PPC64_BOOTINFO_H
-#include <asm/types.h>
-/* We use a u32 for the type of the fields since they're written by
- * the bootloader which is a 32-bit process and read by the kernel
- * which is a 64-bit process.  This way they can both agree on the
- * size of the type.
- */
-typedef u32 bi_rec_field;
-struct bi_record {
-        bi_rec_field tag;       /* tag ID */
-        bi_rec_field size;      /* size of record (in bytes) */
-        bi_rec_field data[0];   /* data */
-};
-#define BI_FIRST                0x1010  /* first record - marker */
-#define BI_LAST                 0x1011  /* last record - marker */
-#define BI_CMD_LINE             0x1012
-#define BI_BOOTLOADER_ID        0x1013
-#define BI_INITRD               0x1014
-#define BI_SYSMAP               0x1015
-#define BI_MACHTYPE             0x1016
-static __inline__ struct bi_record * bi_rec_init(unsigned long addr)
-{
-        struct bi_record *bi_recs;
-        bi_recs = (struct bi_record *)_ALIGN(addr, PAGE_SIZE);
-        bi_recs->size = 0;
-        return bi_recs;
-}
-static __inline__ struct bi_record * bi_rec_alloc(struct bi_record *rec,
-                                                  unsigned long args)
-{
-        rec = (struct bi_record *)((unsigned long)rec + rec->size);
-        rec->size = sizeof(struct bi_record) + args*sizeof(bi_rec_field);
-        return rec;
-}
-static __inline__ struct bi_record * bi_rec_alloc_bytes(struct bi_record *rec,
-                                                        unsigned long bytes)
-{
-        rec = (struct bi_record *)((unsigned long)rec + rec->size);
-        rec->size = sizeof(struct bi_record) + bytes;
-        return rec;
-}
-static __inline__ struct bi_record * bi_rec_next(struct bi_record *rec)
-{
-        return (struct bi_record *)((unsigned long)rec + rec->size);
-}
-#endif /* _PPC64_BOOTINFO_H */
diff --git a/include/asm-ppc64/btext.h b/include/asm-ppc64/btext.h
index 67aef0cc72c0..71cce36bc630 100644
--- a/include/asm-ppc64/btext.h
+++ b/include/asm-ppc64/btext.h
@@ -15,6 +15,7 @@ extern int boot_text_mapped;
 extern int btext_initialize(struct device_node *np);
 extern void map_boot_text(void);
+extern void init_boot_display(void);
 extern void btext_update_display(unsigned long phys, int width, int height,
                                 int depth, int pitch);
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
deleted file mode 100644
index acc9b4d6c168..000000000000
--- a/include/asm-ppc64/cputable.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- *  include/asm-ppc64/cputable.h
- *
- *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- *  Modifications for ppc64:
- *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
- * 
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_PPC_CPUTABLE_H
-#define __ASM_PPC_CPUTABLE_H
-#include <linux/config.h>
-#include <asm/page.h> /* for ASM_CONST */
-/* Exposed to userland CPU features - Must match ppc32 definitions */
-#define PPC_FEATURE_32                  0x80000000
-#define PPC_FEATURE_64                  0x40000000
-#define PPC_FEATURE_601_INSTR           0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
-#define PPC_FEATURE_HAS_FPU             0x08000000
-#define PPC_FEATURE_HAS_MMU             0x04000000
-#define PPC_FEATURE_HAS_4xxMAC          0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mechanism.
- */
-struct cpu_spec;
-struct op_ppc64_model;
-typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
-struct cpu_spec {
-        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
-        unsigned int    pvr_mask;
-        unsigned int    pvr_value;
-        char            *cpu_name;
-        unsigned long   cpu_features;           /* Kernel features */
-        unsigned int    cpu_user_features;      /* Userland features */
-        /* cache line sizes */
-        unsigned int    icache_bsize;
-        unsigned int    dcache_bsize;
-        /* number of performance monitor counters */
-        unsigned int    num_pmcs;
-        /* this is called to initialize various CPU bits like L1 cache,
-         * BHT, SPD, etc... from head.S before branching to identify_machine
-         */
-        cpu_setup_t     cpu_setup;
-        /* Used by oprofile userspace to select the right counters */
-        char            *oprofile_cpu_type;
-        /* Processor specific oprofile operations */
-        struct op_ppc64_model *oprofile_model;
-};
-extern struct cpu_spec          cpu_specs[];
-extern struct cpu_spec          *cur_cpu_spec;
-static inline unsigned long cpu_has_feature(unsigned long feature)
-{
-        return cur_cpu_spec->cpu_features & feature;
-}
-#endif /* __ASSEMBLY__ */
-/* CPU kernel features */
-/* Retain the 32b definitions for the time being - use bottom half of word */
-#define CPU_FTR_SPLIT_ID_CACHE          ASM_CONST(0x0000000000000001)
-#define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
-#define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
-#define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
-#define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
-#define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
-#define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
-#define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
-#define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
-#define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
-#define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
-#define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
-#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
-#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
-#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
-/* Add the 64b processor unique features in the top half of the word */
-#define CPU_FTR_SLB                     ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE                ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL                  ASM_CONST(0x0000000400000000)
-#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000800000000)
-#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000001000000000)
-#define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
-#define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
-/* unused                               ASM_CONST(0x0000008000000000) */
-#define CPU_FTR_SMT                     ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000020000000000)
-#define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0000040000000000)
-#define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
-#define CPU_FTR_CTRL                    ASM_CONST(0x0000100000000000)
-#ifndef __ASSEMBLY__
-#define COMMON_USER_PPC64       (PPC_FEATURE_32 | PPC_FEATURE_64 | \
-                                 PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
-#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
-                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
-                                 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
-/* iSeries doesn't support large pages */
-#ifdef CONFIG_PPC_ISERIES
-#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
-#else
-#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
-#endif /* CONFIG_PPC_ISERIES */
-#endif /* __ASSEMBLY */
-#ifdef __ASSEMBLY__
-#define BEGIN_FTR_SECTION               98:
-#define END_FTR_SECTION(msk, val)               \
-99:                                             \
-        .section __ftr_fixup,"a";               \
-        .align 3;                               \
-        .llong msk;                             \
-        .llong val;                             \
-        .llong 98b;                             \
-        .llong 99b;                             \
-        .previous
-#else
-#define BEGIN_FTR_SECTION               "98:\n"
-#define END_FTR_SECTION(msk, val)               \
-"99:\n"                                         \
-"       .section __ftr_fixup,\"a\";\n"          \
-"       .align 3;\n"                            \
-"       .llong "#msk";\n"                       \
-"       .llong "#val";\n"                       \
-"       .llong 98b;\n"                          \
-"       .llong 99b;\n"                          \
-"       .previous\n"
-#endif /* __ASSEMBLY__ */
-#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
-#endif /* __ASM_PPC_CPUTABLE_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/dbdma.h b/include/asm-ppc64/dbdma.h
deleted file mode 100644
index f2d5d5dc3377..000000000000
--- a/include/asm-ppc64/dbdma.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/dbdma.h>
diff --git a/include/asm-ppc64/dma.h b/include/asm-ppc64/dma.h
deleted file mode 100644
index dfd1f69059ba..000000000000
--- a/include/asm-ppc64/dma.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/* 
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- * Changes for ppc sound by Christoph Nadig
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-#include <linux/config.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-#include <asm/system.h>
-#ifndef MAX_DMA_CHANNELS
-#define MAX_DMA_CHANNELS        8
-#endif
-/* The maximum address that we can perform a DMA transfer to on this platform */
-/* Doesn't really apply... */
-#define MAX_DMA_ADDRESS  (~0UL)
-#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
-#define dma_outb        outb
-#define dma_inb         inb
-/*
- * NOTES about DMA transfers:
- *
- *  controller 1: channels 0-3, byte operations, ports 00-1F
- *  controller 2: channels 4-7, word operations, ports C0-DF
- *
- *  - ALL registers are 8 bits only, regardless of transfer size
- *  - channel 4 is not used - cascades 1 into 2.
- *  - channels 0-3 are byte - addresses/counts are for physical bytes
- *  - channels 5-7 are word - addresses/counts are for physical words
- *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- *  - transfer count loaded to registers is 1 less than actual count
- *  - controller 2 offsets are all even (2x offsets for controller 1)
- *  - page registers for 5-7 don't use data bit 0, represent 128K pages
- *  - page registers for 0-3 use bit 0, represent 64K pages
- *
- * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.  
- * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- *  Address mapping for channels 0-3:
- *
- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0   
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
- *
- *  Address mapping for channels 5-7:
- *
- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
- *
- */
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
-/* DMA controller registers */
-#define DMA1_CMD_REG            0x08    /* command register (w) */
-#define DMA1_STAT_REG           0x08    /* status register (r) */
-#define DMA1_REQ_REG            0x09    /* request register (w) */
-#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
-#define DMA1_MODE_REG           0x0B    /* mode register (w) */
-#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
-#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
-#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
-#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
-#define DMA2_CMD_REG            0xD0    /* command register (w) */
-#define DMA2_STAT_REG           0xD0    /* status register (r) */
-#define DMA2_REQ_REG            0xD2    /* request register (w) */
-#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
-#define DMA2_MODE_REG           0xD6    /* mode register (w) */
-#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
-#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
-#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
-#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
-#define DMA_ADDR_0              0x00    /* DMA address registers */
-#define DMA_ADDR_1              0x02
-#define DMA_ADDR_2              0x04
-#define DMA_ADDR_3              0x06
-#define DMA_ADDR_4              0xC0
-#define DMA_ADDR_5              0xC4
-#define DMA_ADDR_6              0xC8
-#define DMA_ADDR_7              0xCC
-#define DMA_CNT_0               0x01    /* DMA count registers */
-#define DMA_CNT_1               0x03
-#define DMA_CNT_2               0x05
-#define DMA_CNT_3               0x07
-#define DMA_CNT_4               0xC2
-#define DMA_CNT_5               0xC6
-#define DMA_CNT_6               0xCA
-#define DMA_CNT_7               0xCE
-#define DMA_LO_PAGE_0              0x87    /* DMA page registers */
-#define DMA_LO_PAGE_1              0x83
-#define DMA_LO_PAGE_2              0x81
-#define DMA_LO_PAGE_3              0x82
-#define DMA_LO_PAGE_5              0x8B
-#define DMA_LO_PAGE_6              0x89
-#define DMA_LO_PAGE_7              0x8A
-#define DMA_HI_PAGE_0              0x487    /* DMA page registers */
-#define DMA_HI_PAGE_1              0x483
-#define DMA_HI_PAGE_2              0x481
-#define DMA_HI_PAGE_3              0x482
-#define DMA_HI_PAGE_5              0x48B
-#define DMA_HI_PAGE_6              0x489
-#define DMA_HI_PAGE_7              0x48A
-#define DMA1_EXT_REG               0x40B
-#define DMA2_EXT_REG               0x4D6
-#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
-#define DMA_AUTOINIT     0x10
-extern spinlock_t  dma_spin_lock;
-static __inline__ unsigned long claim_dma_lock(void)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&dma_spin_lock, flags);
-        return flags;
-}
-static __inline__ void release_dma_lock(unsigned long flags)
-{
-        spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-        unsigned char ucDmaCmd=0x00;
-        if (dmanr != 4)
-        {
-                dma_outb(0, DMA2_MASK_REG);  /* This may not be enabled */
-                dma_outb(ucDmaCmd, DMA2_CMD_REG);  /* Enable group */
-        }
-        if (dmanr<=3)
-        {
-                dma_outb(dmanr,  DMA1_MASK_REG);
-                dma_outb(ucDmaCmd, DMA1_CMD_REG);  /* Enable group */
-        } else
-        {
-                dma_outb(dmanr & 3,  DMA2_MASK_REG);
-        }
-}
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr | 4,  DMA1_MASK_REG);
-        else
-                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
-}
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while interrupts are disabled! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(0,  DMA1_CLEAR_FF_REG);
-        else
-                dma_outb(0,  DMA2_CLEAR_FF_REG);
-}
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-        if (dmanr<=3)
-                dma_outb(mode | dmanr,  DMA1_MODE_REG);
-        else
-                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
-}
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
-{
-        switch(dmanr) {
-                case 0:
-                        dma_outb(pagenr, DMA_LO_PAGE_0);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_0);
-                        break;
-                case 1:
-                        dma_outb(pagenr, DMA_LO_PAGE_1);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_1);
-                        break;
-                case 2:
-                        dma_outb(pagenr, DMA_LO_PAGE_2);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_2); 
-                        break;
-                case 3:
-                        dma_outb(pagenr, DMA_LO_PAGE_3);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_3); 
-                        break;
-                case 5:
-                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_5);
-                        break;
-                case 6:
-                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_6);
-                        break;
-                case 7:
-                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
-                        dma_outb(pagenr>>8, DMA_HI_PAGE_7);
-                  break;
-        }
-}
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
-{
-        if (dmanr <= 3)  {
-            dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-            dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-        }  else  {
-            dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-            dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-        }
-        set_dma_page(dmanr, phys>>16);
-}
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-        count--;
-        if (dmanr <= 3)  {
-            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-        } else {
-            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-        }
-}
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
-                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-        /* using short to get 16-bit wrap around */
-        unsigned short count;
-        count = 1 + dma_inb(io_port);
-        count += dma_inb(io_port) << 8;
-        
-        return (dmanr <= 3)? count : (count<<1);
-}
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr);       /* release it again */
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;                                        
-#else                                                         
-#define isa_dma_bridge_buggy   (0)
-#endif
-#endif  /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
-#endif /* _ASM_DMA_H */
diff --git a/include/asm-ppc64/hardirq.h b/include/asm-ppc64/hardirq.h
deleted file mode 100644
index 4ee72bb1fd48..000000000000
--- a/include/asm-ppc64/hardirq.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/config.h>
-#include <linux/cache.h>
-#include <linux/preempt.h>
-typedef struct {
-        unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-static inline void ack_bad_irq(int irq)
-{
-        printk(KERN_CRIT "illegal vector %d received!\n", irq);
-        BUG();
-}
-#endif /* __ASM_HARDIRQ_H */
diff --git a/include/asm-ppc64/iSeries/HvCallHpt.h b/include/asm-ppc64/iSeries/HvCallHpt.h
deleted file mode 100644
index 43a1969230b8..000000000000
--- a/include/asm-ppc64/iSeries/HvCallHpt.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * HvCallHpt.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _HVCALLHPT_H
-#define _HVCALLHPT_H
-/*
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from the OS.
- */
-#include <asm/iSeries/HvCallSc.h>
-#include <asm/iSeries/HvTypes.h>
-#include <asm/mmu.h>
-#define HvCallHptGetHptAddress          HvCallHpt +  0
-#define HvCallHptGetHptPages            HvCallHpt +  1
-#define HvCallHptSetPp                  HvCallHpt +  5
-#define HvCallHptSetSwBits              HvCallHpt +  6
-#define HvCallHptUpdate                 HvCallHpt +  7
-#define HvCallHptInvalidateNoSyncICache HvCallHpt +  8
-#define HvCallHptGet                    HvCallHpt + 11
-#define HvCallHptFindNextValid          HvCallHpt + 12
-#define HvCallHptFindValid              HvCallHpt + 13
-#define HvCallHptAddValidate            HvCallHpt + 16
-#define HvCallHptInvalidateSetSwBitsGet HvCallHpt + 18
-static inline u64 HvCallHpt_getHptAddress(void)
-{
-        return HvCall0(HvCallHptGetHptAddress);
-}
-static inline u64 HvCallHpt_getHptPages(void)
-{
-        return HvCall0(HvCallHptGetHptPages);
-}
-static inline void HvCallHpt_setPp(u32 hpteIndex, u8 value)
-{
-        HvCall2(HvCallHptSetPp, hpteIndex, value);
-}
-static inline void HvCallHpt_setSwBits(u32 hpteIndex, u8 bitson, u8 bitsoff)
-{
-        HvCall3(HvCallHptSetSwBits, hpteIndex, bitson, bitsoff);
-}
-static inline void HvCallHpt_invalidateNoSyncICache(u32 hpteIndex)
-{
-        HvCall1(HvCallHptInvalidateNoSyncICache, hpteIndex);
-}
-static inline u64 HvCallHpt_invalidateSetSwBitsGet(u32 hpteIndex, u8 bitson,
-                u8 bitsoff)
-{
-        u64 compressedStatus;
-        compressedStatus = HvCall4(HvCallHptInvalidateSetSwBitsGet,
-                        hpteIndex, bitson, bitsoff, 1);
-        HvCall1(HvCallHptInvalidateNoSyncICache, hpteIndex);
-        return compressedStatus;
-}
-static inline u64 HvCallHpt_findValid(hpte_t *hpte, u64 vpn)
-{
-        return HvCall3Ret16(HvCallHptFindValid, hpte, vpn, 0, 0);
-}
-static inline u64 HvCallHpt_findNextValid(hpte_t *hpte, u32 hpteIndex,
-                u8 bitson, u8 bitsoff)
-{
-        return HvCall3Ret16(HvCallHptFindNextValid, hpte, hpteIndex,
-                        bitson, bitsoff);
-}
-static inline void HvCallHpt_get(hpte_t *hpte, u32 hpteIndex)
-{
-        HvCall2Ret16(HvCallHptGet, hpte, hpteIndex, 0);
-}
-static inline void HvCallHpt_addValidate(u32 hpteIndex, u32 hBit, hpte_t *hpte)
-{
-        HvCall4(HvCallHptAddValidate, hpteIndex, hBit, hpte->v, hpte->r);
-}
-#endif /* _HVCALLHPT_H */
diff --git a/include/asm-ppc64/iSeries/HvCallPci.h b/include/asm-ppc64/iSeries/HvCallPci.h
deleted file mode 100644
index c8d675c40f5e..000000000000
--- a/include/asm-ppc64/iSeries/HvCallPci.h
+++ /dev/null
@@ -1,533 +0,0 @@
-/*
- * Provides the Hypervisor PCI calls for iSeries Linux Parition.
- * Copyright (C) 2001  <Wayne G Holm> <IBM Corporation>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the:
- * Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330,
- * Boston, MA  02111-1307  USA
- *
- * Change Activity:
- *   Created, Jan 9, 2001
- */
-#ifndef _HVCALLPCI_H
-#define _HVCALLPCI_H
-#include <asm/iSeries/HvCallSc.h>
-#include <asm/iSeries/HvTypes.h>
-/*
- * DSA == Direct Select Address
- * this struct must be 64 bits in total
- */
-struct HvCallPci_DsaAddr {
-        u16             busNumber;              /* PHB index? */
-        u8              subBusNumber;           /* PCI bus number? */
-        u8              deviceId;               /* device and function? */
-        u8              barNumber;
-        u8              reserved[3];
-};
-union HvDsaMap {
-        u64     DsaAddr;
-        struct HvCallPci_DsaAddr Dsa;
-};
-struct HvCallPci_LoadReturn {
-        u64             rc;
-        u64             value;
-};
-enum HvCallPci_DeviceType {
-        HvCallPci_NodeDevice    = 1,
-        HvCallPci_SpDevice      = 2,
-        HvCallPci_IopDevice     = 3,
-        HvCallPci_BridgeDevice  = 4,
-        HvCallPci_MultiFunctionDevice = 5,
-        HvCallPci_IoaDevice     = 6
-};
-struct HvCallPci_DeviceInfo {
-        u32     deviceType;             /* See DeviceType enum for values */
-};
-struct HvCallPci_BusUnitInfo {
-        u32     sizeReturned;           /* length of data returned */
-        u32     deviceType;             /* see DeviceType enum for values */
-};
-struct HvCallPci_BridgeInfo {
-        struct HvCallPci_BusUnitInfo busUnitInfo;  /* Generic bus unit info */
-        u8              subBusNumber;   /* Bus number of secondary bus */
-        u8              maxAgents;      /* Max idsels on secondary bus */
-        u8              maxSubBusNumber; /* Max Sub Bus */
-        u8              logicalSlotNumber; /* Logical Slot Number for IOA */
-};
-/*
- * Maximum BusUnitInfo buffer size.  Provided for clients so
- * they can allocate a buffer big enough for any type of bus
- * unit.  Increase as needed.
- */
-enum {HvCallPci_MaxBusUnitInfoSize = 128};
-struct HvCallPci_BarParms {
-        u64             vaddr;
-        u64             raddr;
-        u64             size;
-        u64             protectStart;
-        u64             protectEnd;
-        u64             relocationOffset;
-        u64             pciAddress;
-        u64             reserved[3];
-};
-enum HvCallPci_VpdType {
-        HvCallPci_BusVpd        = 1,
-        HvCallPci_BusAdapterVpd = 2
-};
-#define HvCallPciConfigLoad8            HvCallPci + 0
-#define HvCallPciConfigLoad16           HvCallPci + 1
-#define HvCallPciConfigLoad32           HvCallPci + 2
-#define HvCallPciConfigStore8           HvCallPci + 3
-#define HvCallPciConfigStore16          HvCallPci + 4
-#define HvCallPciConfigStore32          HvCallPci + 5
-#define HvCallPciEoi                    HvCallPci + 16
-#define HvCallPciGetBarParms            HvCallPci + 18
-#define HvCallPciMaskFisr               HvCallPci + 20
-#define HvCallPciUnmaskFisr             HvCallPci + 21
-#define HvCallPciSetSlotReset           HvCallPci + 25
-#define HvCallPciGetDeviceInfo          HvCallPci + 27
-#define HvCallPciGetCardVpd             HvCallPci + 28
-#define HvCallPciBarLoad8               HvCallPci + 40
-#define HvCallPciBarLoad16              HvCallPci + 41
-#define HvCallPciBarLoad32              HvCallPci + 42
-#define HvCallPciBarLoad64              HvCallPci + 43
-#define HvCallPciBarStore8              HvCallPci + 44
-#define HvCallPciBarStore16             HvCallPci + 45
-#define HvCallPciBarStore32             HvCallPci + 46
-#define HvCallPciBarStore64             HvCallPci + 47
-#define HvCallPciMaskInterrupts         HvCallPci + 48
-#define HvCallPciUnmaskInterrupts       HvCallPci + 49
-#define HvCallPciGetBusUnitInfo         HvCallPci + 50
-static inline u64 HvCallPci_configLoad8(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u8 *value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-        HvCall3Ret16(HvCallPciConfigLoad8, &retVal, *(u64 *)&dsa, offset, 0);
-        *value = retVal.value;
-        return retVal.rc;
-}
-static inline u64 HvCallPci_configLoad16(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u16 *value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-        HvCall3Ret16(HvCallPciConfigLoad16, &retVal, *(u64 *)&dsa, offset, 0);
-        *value = retVal.value;
-        return retVal.rc;
-}
-static inline u64 HvCallPci_configLoad32(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u32 *value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-        HvCall3Ret16(HvCallPciConfigLoad32, &retVal, *(u64 *)&dsa, offset, 0);
-        *value = retVal.value;
-        return retVal.rc;
-}
-static inline u64 HvCallPci_configStore8(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u8 value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-        return HvCall4(HvCallPciConfigStore8, *(u64 *)&dsa, offset, value, 0);
-}
-static inline u64 HvCallPci_configStore16(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u16 value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-        return HvCall4(HvCallPciConfigStore16, *(u64 *)&dsa, offset, value, 0);
-}
-static inline u64 HvCallPci_configStore32(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u32 value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-        return HvCall4(HvCallPciConfigStore32, *(u64 *)&dsa, offset, value, 0);
-}
-static inline u64 HvCallPci_barLoad8(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u8 *valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        HvCall3Ret16(HvCallPciBarLoad8, &retVal, *(u64 *)&dsa, offsetParm, 0);
-        *valueParm = retVal.value;
-        return retVal.rc;
-}
-static inline u64 HvCallPci_barLoad16(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u16 *valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        HvCall3Ret16(HvCallPciBarLoad16, &retVal, *(u64 *)&dsa, offsetParm, 0);
-        *valueParm = retVal.value;
-        return retVal.rc;
-}
-static inline u64 HvCallPci_barLoad32(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u32 *valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        HvCall3Ret16(HvCallPciBarLoad32, &retVal, *(u64 *)&dsa, offsetParm, 0);
-        *valueParm = retVal.value;
-        return retVal.rc;
-}
-static inline u64 HvCallPci_barLoad64(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u64 *valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        HvCall3Ret16(HvCallPciBarLoad64, &retVal, *(u64 *)&dsa, offsetParm, 0);
-        *valueParm = retVal.value;
-        return retVal.rc;
-}
-static inline u64 HvCallPci_barStore8(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u8 valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        return HvCall4(HvCallPciBarStore8, *(u64 *)&dsa, offsetParm,
-                        valueParm, 0);
-}
-static inline u64 HvCallPci_barStore16(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u16 valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        return HvCall4(HvCallPciBarStore16, *(u64 *)&dsa, offsetParm,
-                        valueParm, 0);
-}
-static inline u64 HvCallPci_barStore32(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u32 valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        return HvCall4(HvCallPciBarStore32, *(u64 *)&dsa, offsetParm,
-                        valueParm, 0);
-}
-static inline u64 HvCallPci_barStore64(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
-                u64 valueParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        return HvCall4(HvCallPciBarStore64, *(u64 *)&dsa, offsetParm,
-                        valueParm, 0);
-}
-static inline u64 HvCallPci_eoi(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        HvCall1Ret16(HvCallPciEoi, &retVal, *(u64*)&dsa);
-        return retVal.rc;
-}
-static inline u64 HvCallPci_getBarParms(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-        return HvCall3(HvCallPciGetBarParms, *(u64*)&dsa, parms, sizeofParms);
-}
-static inline u64 HvCallPci_maskFisr(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 fisrMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        return HvCall2(HvCallPciMaskFisr, *(u64*)&dsa, fisrMask);
-}
-static inline u64 HvCallPci_unmaskFisr(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 fisrMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        return HvCall2(HvCallPciUnmaskFisr, *(u64*)&dsa, fisrMask);
-}
-static inline u64 HvCallPci_setSlotReset(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 onNotOff)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        return HvCall2(HvCallPciSetSlotReset, *(u64*)&dsa, onNotOff);
-}
-static inline u64 HvCallPci_getDeviceInfo(u16 busNumberParm, u8 subBusParm,
-                u8 deviceNumberParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceNumberParm << 4;
-        return HvCall3(HvCallPciGetDeviceInfo, *(u64*)&dsa, parms, sizeofParms);
-}
-static inline u64 HvCallPci_maskInterrupts(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 interruptMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        return HvCall2(HvCallPciMaskInterrupts, *(u64*)&dsa, interruptMask);
-}
-static inline u64 HvCallPci_unmaskInterrupts(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 interruptMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        return HvCall2(HvCallPciUnmaskInterrupts, *(u64*)&dsa, interruptMask);
-}
-static inline u64 HvCallPci_getBusUnitInfo(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-        *((u64*)&dsa) = 0;
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        return HvCall3(HvCallPciGetBusUnitInfo, *(u64*)&dsa, parms,
-                        sizeofParms);
-}
-static inline int HvCallPci_getBusVpd(u16 busNumParm, u64 destParm,
-                u16 sizeParm)
-{
-        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm,
-                        sizeParm, HvCallPci_BusVpd);
-        if (xRc == -1)
-                return -1;
-        else
-                return xRc & 0xFFFF;
-}
-static inline int HvCallPci_getBusAdapterVpd(u16 busNumParm, u64 destParm,
-                u16 sizeParm)
-{
-        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm,
-                        sizeParm, HvCallPci_BusAdapterVpd);
-        if (xRc == -1)
-                return -1;
-        else
-                return xRc & 0xFFFF;
-}
-#endif /* _HVCALLPCI_H */
diff --git a/include/asm-ppc64/iSeries/HvReleaseData.h b/include/asm-ppc64/iSeries/HvReleaseData.h
deleted file mode 100644
index c8162e5ccb21..000000000000
--- a/include/asm-ppc64/iSeries/HvReleaseData.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * HvReleaseData.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _HVRELEASEDATA_H
-#define _HVRELEASEDATA_H
-/*
- * This control block contains the critical information about the
- * release so that it can be changed in the future (ie, the virtual
- * address of the OS's NACA).
- */
-#include <asm/types.h>
-#include <asm/naca.h>
-/*
- * When we IPL a secondary partition, we will check if if the
- * secondary xMinPlicVrmIndex > the primary xVrmIndex.
- * If it is then this tells PLIC that this secondary is not
- * supported running on this "old" of a level of PLIC.
- *
- * Likewise, we will compare the primary xMinSlicVrmIndex to
- * the secondary xVrmIndex.
- * If the primary xMinSlicVrmDelta > secondary xVrmDelta then we
- * know that this PLIC does not support running an OS "that old".
- */
-#define HVREL_TAGSINACTIVE      0x8000
-#define HVREL_32BIT             0x4000
-#define HVREL_NOSHAREDPROCS     0x2000
-#define HVREL_NOHMT             0x1000
-struct HvReleaseData {
-        u32     xDesc;          /* Descriptor "HvRD" ebcdic     x00-x03 */
-        u16     xSize;          /* Size of this control block   x04-x05 */
-        u16     xVpdAreasPtrOffset; /* Offset in NACA of ItVpdAreas x06-x07 */
-        struct  naca_struct     *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */
-        u32     xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */
-        u32     xRsvd1;         /* Reserved                     x14-x17 */
-        u16     xFlags;
-        u16     xVrmIndex;      /* VRM Index of OS image        x1A-x1B */
-        u16     xMinSupportedPlicVrmIndex; /* Min PLIC level  (soft) x1C-x1D */
-        u16     xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */
-        char    xVrmName[12];   /* Displayable name             x20-x2B */
-        char    xRsvd3[20];     /* Reserved                     x2C-x3F */
-};
-extern struct HvReleaseData     hvReleaseData;
-#endif /* _HVRELEASEDATA_H */
diff --git a/include/asm-ppc64/iSeries/IoHriMainStore.h b/include/asm-ppc64/iSeries/IoHriMainStore.h
deleted file mode 100644
index 45ed3ea67d06..000000000000
--- a/include/asm-ppc64/iSeries/IoHriMainStore.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * IoHriMainStore.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _IOHRIMAINSTORE_H
-#define _IOHRIMAINSTORE_H
-/* Main Store Vpd for Condor,iStar,sStar */
-struct IoHriMainStoreSegment4 {
-        u8      msArea0Exists:1;
-        u8      msArea1Exists:1;
-        u8      msArea2Exists:1;
-        u8      msArea3Exists:1;
-        u8      reserved1:4;
-        u8      reserved2;
-        u8      msArea0Functional:1;
-        u8      msArea1Functional:1;
-        u8      msArea2Functional:1;
-        u8      msArea3Functional:1;
-        u8      reserved3:4;
-        u8      reserved4;
-        u32     totalMainStore;
-        u64     msArea0Ptr;
-        u64     msArea1Ptr;
-        u64     msArea2Ptr;
-        u64     msArea3Ptr;
-        u32     cardProductionLevel;
-        u32     msAdrHole;
-        u8      msArea0HasRiserVpd:1;
-        u8      msArea1HasRiserVpd:1;
-        u8      msArea2HasRiserVpd:1;
-        u8      msArea3HasRiserVpd:1;
-        u8      reserved5:4;
-        u8      reserved6;
-        u16     reserved7;
-        u8      reserved8[28];
-        u64     nonInterleavedBlocksStartAdr;
-        u64     nonInterleavedBlocksEndAdr;
-};
-/* Main Store VPD for Power4 */
-struct IoHriMainStoreChipInfo1 {
-        u32     chipMfgID       __attribute((packed));
-        char    chipECLevel[4]  __attribute((packed));
-};
-struct IoHriMainStoreVpdIdData {
-        char    typeNumber[4];
-        char    modelNumber[4];
-        char    partNumber[12];
-        char    serialNumber[12];
-};
-struct IoHriMainStoreVpdFruData {
-        char    fruLabel[8]     __attribute((packed));
-        u8      numberOfSlots   __attribute((packed));
-        u8      pluggingType    __attribute((packed));
-        u16     slotMapIndex    __attribute((packed));
-};
-struct IoHriMainStoreAdrRangeBlock {
-        void    *blockStart      __attribute((packed));
-        void    *blockEnd        __attribute((packed));
-        u32     blockProcChipId __attribute((packed));
-};
-#define MaxAreaAdrRangeBlocks 4
-struct IoHriMainStoreArea4 {
-        u32     msVpdFormat                     __attribute((packed));
-        u8      containedVpdType                __attribute((packed));
-        u8      reserved1                       __attribute((packed));
-        u16     reserved2                       __attribute((packed));
-        u64     msExists                        __attribute((packed));
-        u64     msFunctional                    __attribute((packed));
-        u32     memorySize                      __attribute((packed));
-        u32     procNodeId                      __attribute((packed));
-        u32     numAdrRangeBlocks               __attribute((packed));
-        struct IoHriMainStoreAdrRangeBlock xAdrRangeBlock[MaxAreaAdrRangeBlocks]        __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo0       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo1       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo2       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo3       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo4       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo5       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo6       __attribute((packed));
-        struct IoHriMainStoreChipInfo1  chipInfo7       __attribute((packed));
-        void    *msRamAreaArray                 __attribute((packed));
-        u32     msRamAreaArrayNumEntries        __attribute((packed));
-        u32     msRamAreaArrayEntrySize         __attribute((packed));
-        u32     numaDimmExists                  __attribute((packed));
-        u32     numaDimmFunctional              __attribute((packed));
-        void    *numaDimmArray                  __attribute((packed));
-        u32     numaDimmArrayNumEntries         __attribute((packed));
-        u32     numaDimmArrayEntrySize          __attribute((packed));
-        struct IoHriMainStoreVpdIdData idData   __attribute((packed));
-        u64     powerData                       __attribute((packed));
-        u64     cardAssemblyPartNum             __attribute((packed));
-        u64     chipSerialNum                   __attribute((packed));
-        u64     reserved3                       __attribute((packed));
-        char    reserved4[16]                   __attribute((packed));
-        struct IoHriMainStoreVpdFruData fruData __attribute((packed));
-        u8      vpdPortNum                      __attribute((packed));
-        u8      reserved5                       __attribute((packed));
-        u8      frameId                         __attribute((packed));
-        u8      rackUnit                        __attribute((packed));
-        char    asciiKeywordVpd[256]            __attribute((packed));
-        u32     reserved6                       __attribute((packed));
-};
-struct IoHriMainStoreSegment5 {
-        u16     reserved1;
-        u8      reserved2;
-        u8      msVpdFormat;
-        u32     totalMainStore;
-        u64     maxConfiguredMsAdr;
-        struct IoHriMainStoreArea4      *msAreaArray;
-        u32     msAreaArrayNumEntries;
-        u32     msAreaArrayEntrySize;
-        u32     msAreaExists;
-        u32     msAreaFunctional;
-        u64     reserved3;
-};
-extern u64      xMsVpd[];
-#endif  /* _IOHRIMAINSTORE_H */
diff --git a/include/asm-ppc64/iSeries/IoHriProcessorVpd.h b/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
deleted file mode 100644
index 73b73d80b8b1..000000000000
--- a/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * IoHriProcessorVpd.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _IOHRIPROCESSORVPD_H
-#define _IOHRIPROCESSORVPD_H
-#include <asm/types.h>
-/*
- * This struct maps Processor Vpd that is DMAd to SLIC by CSP
- */
-struct IoHriProcessorVpd {
-        u8      xFormat;                // VPD format indicator         x00-x00
-        u8      xProcStatus:8;          // Processor State              x01-x01
-        u8      xSecondaryThreadCount;  // Secondary thread cnt         x02-x02
-        u8      xSrcType:1;             // Src Type                     x03-x03
-        u8      xSrcSoft:1;             // Src stay soft                ...
-        u8      xSrcParable:1;          // Src parable                  ...
-        u8      xRsvd1:5;               // Reserved                     ...
-        u16     xHvPhysicalProcIndex;   // Hypervisor physical proc index04-x05
-        u16     xRsvd2;                 // Reserved                     x06-x07
-        u32     xHwNodeId;              // Hardware node id             x08-x0B
-        u32     xHwProcId;              // Hardware processor id        x0C-x0F
-        u32     xTypeNum;               // Card Type/CCIN number        x10-x13
-        u32     xModelNum;              // Model/Feature number         x14-x17
-        u64     xSerialNum;             // Serial number                x18-x1F
-        char    xPartNum[12];           // Book Part or FPU number      x20-x2B
-        char    xMfgID[4];              // Manufacturing ID             x2C-x2F
-        u32     xProcFreq;              // Processor Frequency          x30-x33
-        u32     xTimeBaseFreq;          // Time Base Frequency          x34-x37
-        u32     xChipEcLevel;           // Chip EC Levels               x38-x3B
-        u32     xProcIdReg;             // PIR SPR value                x3C-x3F
-        u32     xPVR;                   // PVR value                    x40-x43
-        u8      xRsvd3[12];             // Reserved                     x44-x4F
-        u32     xInstCacheSize;         // Instruction cache size in KB x50-x53
-        u32     xInstBlockSize;         // Instruction cache block size x54-x57
-        u32     xDataCacheOperandSize;  // Data cache operand size      x58-x5B
-        u32     xInstCacheOperandSize;  // Inst cache operand size      x5C-x5F
-        u32     xDataL1CacheSizeKB;     // L1 data cache size in KB     x60-x63
-        u32     xDataL1CacheLineSize;   // L1 data cache block size     x64-x67
-        u64     xRsvd4;                 // Reserved                     x68-x6F
-        u32     xDataL2CacheSizeKB;     // L2 data cache size in KB     x70-x73
-        u32     xDataL2CacheLineSize;   // L2 data cache block size     x74-x77
-        u64     xRsvd5;                 // Reserved                     x78-x7F
-        u32     xDataL3CacheSizeKB;     // L3 data cache size in KB     x80-x83
-        u32     xDataL3CacheLineSize;   // L3 data cache block size     x84-x87
-        u64     xRsvd6;                 // Reserved                     x88-x8F
-        u64     xFruLabel;              // Card Location Label          x90-x97
-        u8      xSlotsOnCard;           // Slots on card (0=no slots)   x98-x98
-        u8      xPartLocFlag;           // Location flag (0-pluggable 1-imbedded) x99-x99
-        u16     xSlotMapIndex;          // Index in slot map table      x9A-x9B
-        u8      xSmartCardPortNo;       // Smart card port number       x9C-x9C
-        u8      xRsvd7;                 // Reserved                     x9D-x9D
-        u16     xFrameIdAndRackUnit;    // Frame ID and rack unit adr   x9E-x9F
-        u8      xRsvd8[24];             // Reserved                     xA0-xB7
-        char    xProcSrc[72];           // CSP format SRC               xB8-xFF
-};
-extern struct IoHriProcessorVpd xIoHriProcessorVpd[];
-#endif /* _IOHRIPROCESSORVPD_H */
diff --git a/include/asm-ppc64/iSeries/ItIplParmsReal.h b/include/asm-ppc64/iSeries/ItIplParmsReal.h
deleted file mode 100644
index ae3417dc599e..000000000000
--- a/include/asm-ppc64/iSeries/ItIplParmsReal.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * ItIplParmsReal.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ITIPLPARMSREAL_H
-#define _ITIPLPARMSREAL_H
-/*
- *      This struct maps the IPL Parameters DMA'd from the SP.
- *
- * Warning:
- *      This data must map in exactly 64 bytes and match the architecture for
- *      the IPL parms
- */
-#include <asm/types.h>
-struct ItIplParmsReal {
-        u8      xFormat;                // Defines format of IplParms   x00-x00
-        u8      xRsvd01:6;              // Reserved                     x01-x01
-        u8      xAlternateSearch:1;     // Alternate search indicator   ...
-        u8      xUaSupplied:1;          // UA Supplied on programmed IPL...
-        u8      xLsUaFormat;            // Format byte for UA           x02-x02
-        u8      xRsvd02;                // Reserved                     x03-x03
-        u32     xLsUa;                  // LS UA                        x04-x07
-        u32     xUnusedLsLid;           // First OS LID to load         x08-x0B
-        u16     xLsBusNumber;           // LS Bus Number                x0C-x0D
-        u8      xLsCardAdr;             // LS Card Address              x0E-x0E
-        u8      xLsBoardAdr;            // LS Board Address             x0F-x0F
-        u32     xRsvd03;                // Reserved                     x10-x13
-        u8      xSpcnPresent:1;         // SPCN present                 x14-x14
-        u8      xCpmPresent:1;          // CPM present                  ...
-        u8      xRsvd04:6;              // Reserved                     ...
-        u8      xRsvd05:4;              // Reserved                     x15-x15
-        u8      xKeyLock:4;             // Keylock setting              ...
-        u8      xRsvd06:6;              // Reserved                     x16-x16
-        u8      xIplMode:2;             // Ipl mode (A|B|C|D)           ...
-        u8      xHwIplType;             // Fast v slow v slow EC HW IPL x17-x17
-        u16     xCpmEnabledIpl:1;       // CPM in effect when IPL initiatedx18-x19
-        u16     xPowerOnResetIpl:1;     // Indicate POR condition       ...
-        u16     xMainStorePreserved:1;  // Main Storage is preserved    ...
-        u16     xRsvd07:13;             // Reserved                     ...
-        u16     xIplSource:16;          // Ipl source                   x1A-x1B
-        u8      xIplReason:8;           // Reason for this IPL          x1C-x1C
-        u8      xRsvd08;                // Reserved                     x1D-x1D
-        u16     xRsvd09;                // Reserved                     x1E-x1F
-        u16     xSysBoxType;            // System Box Type              x20-x21
-        u16     xSysProcType;           // System Processor Type        x22-x23
-        u32     xRsvd10;                // Reserved                     x24-x27
-        u64     xRsvd11;                // Reserved                     x28-x2F
-        u64     xRsvd12;                // Reserved                     x30-x37
-        u64     xRsvd13;                // Reserved                     x38-x3F
-};
-extern struct ItIplParmsReal    xItIplParmsReal;
-#endif /* _ITIPLPARMSREAL_H */
diff --git a/include/asm-ppc64/iSeries/ItVpdAreas.h b/include/asm-ppc64/iSeries/ItVpdAreas.h
deleted file mode 100644
index 71b3ad24f95a..000000000000
--- a/include/asm-ppc64/iSeries/ItVpdAreas.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * ItVpdAreas.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ITVPDAREAS_H
-#define _ITVPDAREAS_H
-/*
- * This file defines the address and length of all of the VPD area passed to
- * the OS from PLIC (most of which start from the SP).
- */
-#include <asm/types.h>
-/* VPD Entry index is carved in stone - cannot be changed (easily). */
-#define ItVpdCecVpd                             0
-#define ItVpdDynamicSpace                       1
-#define ItVpdExtVpd                             2
-#define ItVpdExtVpdOnPanel                      3
-#define ItVpdFirstPaca                          4
-#define ItVpdIoVpd                              5
-#define ItVpdIplParms                           6
-#define ItVpdMsVpd                              7
-#define ItVpdPanelVpd                           8
-#define ItVpdLpNaca                             9
-#define ItVpdBackplaneAndMaybeClockCardVpd      10
-#define ItVpdRecoveryLogBuffer                  11
-#define ItVpdSpCommArea                         12
-#define ItVpdSpLogBuffer                        13
-#define ItVpdSpLogBufferSave                    14
-#define ItVpdSpCardVpd                          15
-#define ItVpdFirstProcVpd                       16
-#define ItVpdApModelVpd                         17
-#define ItVpdClockCardVpd                       18
-#define ItVpdBusExtCardVpd                      19
-#define ItVpdProcCapacityVpd                    20
-#define ItVpdInteractiveCapacityVpd             21
-#define ItVpdFirstSlotLabel                     22
-#define ItVpdFirstLpQueue                       23
-#define ItVpdFirstL3CacheVpd                    24
-#define ItVpdFirstProcFruVpd                    25
-#define ItVpdMaxEntries                         26
-#define ItDmaMaxEntries                         10
-#define ItVpdAreasMaxSlotLabels                 192
-struct ItVpdAreas {
-        u32     xSlicDesc;              // Descriptor                   000-003
-        u16     xSlicSize;              // Size of this control block   004-005
-        u16     xPlicAdjustVpdLens:1;   // Flag to indicate new interface006-007
-        u16     xRsvd1:15;              // Reserved bits                ...
-        u16     xSlicVpdEntries;        // Number of VPD entries        008-009
-        u16     xSlicDmaEntries;        // Number of DMA entries        00A-00B
-        u16     xSlicMaxLogicalProcs;   // Maximum logical processors   00C-00D
-        u16     xSlicMaxPhysicalProcs;  // Maximum physical processors  00E-00F
-        u16     xSlicDmaToksOffset;     // Offset into this of array    010-011
-        u16     xSlicVpdAdrsOffset;     // Offset into this of array    012-013
-        u16     xSlicDmaLensOffset;     // Offset into this of array    014-015
-        u16     xSlicVpdLensOffset;     // Offset into this of array    016-017
-        u16     xSlicMaxSlotLabels;     // Maximum number of slot labels018-019
-        u16     xSlicMaxLpQueues;       // Maximum number of LP Queues  01A-01B
-        u8      xRsvd2[4];              // Reserved                     01C-01F
-        u64     xRsvd3[12];             // Reserved                     020-07F
-        u32     xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths   080-0A7
-        u32     xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens    0A8-0CF
-        u32     xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths   0D0-12F
-        void    *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers  130-1EF
-};
-extern struct ItVpdAreas        itVpdAreas;
-#endif /* _ITVPDAREAS_H */
diff --git a/include/asm-ppc64/iSeries/iSeries_irq.h b/include/asm-ppc64/iSeries/iSeries_irq.h
deleted file mode 100644
index 6c9767ac1302..000000000000
--- a/include/asm-ppc64/iSeries/iSeries_irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ISERIES_IRQ_H__
-#define __ISERIES_IRQ_H__
-extern void iSeries_init_IRQ(void);
-extern int  iSeries_allocate_IRQ(HvBusNumber, HvSubBusNumber, HvAgentId);
-extern void iSeries_activate_IRQs(void);
-#endif /* __ISERIES_IRQ_H__ */
diff --git a/include/asm-ppc64/iSeries/iSeries_pci.h b/include/asm-ppc64/iSeries/iSeries_pci.h
deleted file mode 100644
index 575f611f8b33..000000000000
--- a/include/asm-ppc64/iSeries/iSeries_pci.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef _ISERIES_64_PCI_H
-#define _ISERIES_64_PCI_H
-/*
- * File iSeries_pci.h created by Allan Trautman on Tue Feb 20, 2001.
- *
- * Define some useful macros for the iSeries pci routines.
- * Copyright (C) 2001  Allan H Trautman, IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the:
- * Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330,
- * Boston, MA  02111-1307  USA
- *
- * Change Activity:
- *   Created Feb 20, 2001
- *   Added device reset, March 22, 2001
- *   Ported to ppc64, May 25, 2001
- * End Change Activity
- */
-#include <asm/iSeries/HvCallPci.h>
-#include <asm/abs_addr.h>
-struct pci_dev;                         /* For Forward Reference */
-struct iSeries_Device_Node;
-/*
- * Gets iSeries Bus, SubBus, DevFn using iSeries_Device_Node structure
- */
-#define ISERIES_BUS(DevPtr)     DevPtr->DsaAddr.Dsa.busNumber
-#define ISERIES_SUBBUS(DevPtr)  DevPtr->DsaAddr.Dsa.subBusNumber
-#define ISERIES_DEVICE(DevPtr)  DevPtr->DsaAddr.Dsa.deviceId
-#define ISERIES_DSA(DevPtr)     DevPtr->DsaAddr.DsaAddr
-#define ISERIES_DEVNODE(PciDev) ((struct iSeries_Device_Node *)PciDev->sysdata)
-#define EADsMaxAgents 7
-/*
- * Decodes Linux DevFn to iSeries DevFn, bridge device, or function.
- * For Linux, see PCI_SLOT and PCI_FUNC in include/linux/pci.h
- */
-#define ISERIES_PCI_AGENTID(idsel, func)        \
-        (((idsel & 0x0F) << 4) | (func & 0x07))
-#define ISERIES_ENCODE_DEVICE(agentid)          \
-        ((0x10) | ((agentid & 0x20) >> 2) | (agentid & 0x07))
-#define ISERIES_GET_DEVICE_FROM_SUBBUS(subbus)          ((subbus >> 5) & 0x7)
-#define ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus)        ((subbus >> 2) & 0x7)
-/*
- * Converts Virtual Address to Real Address for Hypervisor calls
- */
-#define ISERIES_HV_ADDR(virtaddr)       \
-        (0x8000000000000000 | virt_to_abs(virtaddr))
-/*
- * iSeries Device Information
- */
-struct iSeries_Device_Node {
-        struct list_head Device_List;
-        struct pci_dev  *PciDev;
-        union HvDsaMap  DsaAddr;        /* Direct Select Address */
-                                        /* busNumber, subBusNumber, */
-                                        /* deviceId, barNumber */
-        int             DevFn;          /* Linux devfn */
-        int             Irq;            /* Assigned IRQ */
-        int             Flags;          /* Possible flags(disable/bist)*/
-        u8              LogicalSlot;    /* Hv Slot Index for Tces */
-        struct iommu_table *iommu_table;/* Device TCE Table */
-};
-extern void     iSeries_Device_Information(struct pci_dev*, int);
-#endif /* _ISERIES_64_PCI_H */
diff --git a/include/asm-ppc64/io.h b/include/asm-ppc64/io.h
index 59c958aea4db..77fc07c3c6bd 100644
--- a/include/asm-ppc64/io.h
+++ b/include/asm-ppc64/io.h
@@ -13,9 +13,9 @@
 #include <asm/page.h>
 #include <asm/byteorder.h>
 #ifdef CONFIG_PPC_ISERIES 
-#include <asm/iSeries/iSeries_io.h>
+#include <asm/iseries/iseries_io.h>
 #endif  
-#include <asm/memory.h>
+#include <asm/synch.h>
 #include <asm/delay.h>
 #include <asm-generic/iomap.h>
diff --git a/include/asm-ppc64/ipcbuf.h b/include/asm-ppc64/ipcbuf.h
deleted file mode 100644
index fa393c8342af..000000000000
--- a/include/asm-ppc64/ipcbuf.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __PPC64_IPCBUF_H__
-#define __PPC64_IPCBUF_H__
-/*
- * The ipc64_perm structure for the PPC is identical to kern_ipc_perm
- * as we have always had 32-bit UIDs and GIDs in the kernel.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-struct ipc64_perm
-{
-        __kernel_key_t  key;
-        __kernel_uid_t  uid;
-        __kernel_gid_t  gid;
-        __kernel_uid_t  cuid;
-        __kernel_gid_t  cgid;
-        __kernel_mode_t mode;
-        unsigned int    seq;
-        unsigned int    __pad1;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-};
-#endif /* __PPC64_IPCBUF_H__ */
diff --git a/include/asm-ppc64/irq.h b/include/asm-ppc64/irq.h
deleted file mode 100644
index 99782afb4cde..000000000000
--- a/include/asm-ppc64/irq.h
+++ /dev/null
@@ -1,120 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/config.h>
-#include <linux/threads.h>
-/*
- * Maximum number of interrupt sources that we can handle.
- */
-#define NR_IRQS         512
-/* this number is used when no interrupt has been assigned */
-#define NO_IRQ                  (-1)
-/*
- * These constants are used for passing information about interrupt
- * signal polarity and level/edge sensing to the low-level PIC chip
- * drivers.
- */
-#define IRQ_SENSE_MASK          0x1
-#define IRQ_SENSE_LEVEL         0x1     /* interrupt on active level */
-#define IRQ_SENSE_EDGE          0x0     /* interrupt triggered by edge */
-#define IRQ_POLARITY_MASK       0x2
-#define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
-#define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
-/*
- * IRQ line status macro IRQ_PER_CPU is used
- */
-#define ARCH_HAS_IRQ_PER_CPU
-#define get_irq_desc(irq) (&irq_desc[(irq)])
-/* Define a way to iterate across irqs. */
-#define for_each_irq(i) \
-        for ((i) = 0; (i) < NR_IRQS; ++(i))
-/* Interrupt numbers are virtual in case they are sparsely
- * distributed by the hardware.
- */
-extern unsigned int virt_irq_to_real_map[NR_IRQS];
-/* Create a mapping for a real_irq if it doesn't already exist.
- * Return the virtual irq as a convenience.
- */
-int virt_irq_create_mapping(unsigned int real_irq);
-void virt_irq_init(void);
-static inline unsigned int virt_irq_to_real(unsigned int virt_irq)
-{
-        return virt_irq_to_real_map[virt_irq];
-}
-extern unsigned int real_irq_to_virt_slowpath(unsigned int real_irq);
-/*
- * Because many systems have two overlapping names spaces for
- * interrupts (ISA and XICS for example), and the ISA interrupts
- * have historically not been easy to renumber, we allow ISA
- * interrupts to take values 0 - 15, and shift up the remaining
- * interrupts by 0x10.
- */
-#define NUM_ISA_INTERRUPTS      0x10
-extern int __irq_offset_value;
-static inline int irq_offset_up(int irq)
-{
-        return(irq + __irq_offset_value);
-}
-static inline int irq_offset_down(int irq)
-{
-        return(irq - __irq_offset_value);
-}
-static inline int irq_offset_value(void)
-{
-        return __irq_offset_value;
-}
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
-extern int distribute_irqs;
-struct irqaction;
-struct pt_regs;
-#ifdef CONFIG_IRQSTACKS
-/*
- * Per-cpu stacks for handling hard and soft interrupts.
- */
-extern struct thread_info *hardirq_ctx[NR_CPUS];
-extern struct thread_info *softirq_ctx[NR_CPUS];
-extern void irq_ctx_init(void);
-extern void call_do_softirq(struct thread_info *tp);
-extern int call_handle_IRQ_event(int irq, struct pt_regs *regs,
-                        struct irqaction *action, struct thread_info *tp);
-#define __ARCH_HAS_DO_SOFTIRQ
-#else
-#define irq_ctx_init()
-#endif /* CONFIG_IRQSTACKS */
-#endif /* _ASM_IRQ_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/kexec.h b/include/asm-ppc64/kexec.h
deleted file mode 100644
index 511908afaeeb..000000000000
--- a/include/asm-ppc64/kexec.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef _PPC64_KEXEC_H
-#define _PPC64_KEXEC_H
-/*
- * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
- * I.e. Maximum page that is mapped directly into kernel memory,
- * and kmap is not required.
- */
-/* Maximum physical address we can use pages from */
-/* XXX: since we copy virt we can use any page we allocate */
-#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
-/* Maximum address we can reach in physical address mode */
-/* XXX: I want to allow initrd in highmem.  otherwise set to rmo on lpar */
-#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
-/* Maximum address we can use for the control code buffer */
-/* XXX: unused today, ppc32 uses TASK_SIZE, probably left over from use_mm  */
-#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
-/* XXX: today we don't use this at all, althogh we have a static stack */
-#define KEXEC_CONTROL_CODE_SIZE 4096
-/* The native architecture */
-#define KEXEC_ARCH KEXEC_ARCH_PPC64
-#define MAX_NOTE_BYTES 1024
-#ifndef __ASSEMBLY__
-typedef u32 note_buf_t[MAX_NOTE_BYTES/4];
-extern note_buf_t crash_notes[];
-extern void kexec_smp_wait(void);       /* get and clear naca physid, wait for
-                                          master to copy new code to 0 */
-#endif /* __ASSEMBLY__ */
-#endif /* _PPC_KEXEC_H */
diff --git a/include/asm-ppc64/keylargo.h b/include/asm-ppc64/keylargo.h
deleted file mode 100644
index 4d78e3d0314c..000000000000
--- a/include/asm-ppc64/keylargo.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/keylargo.h>
diff --git a/include/asm-ppc64/kmap_types.h b/include/asm-ppc64/kmap_types.h
deleted file mode 100644
index fd1574648223..000000000000
--- a/include/asm-ppc64/kmap_types.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,    
-        KM_TYPE_NR
-};
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/macio.h b/include/asm-ppc64/macio.h
deleted file mode 100644
index a3028b364f70..000000000000
--- a/include/asm-ppc64/macio.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/macio.h>
diff --git a/include/asm-ppc64/memory.h b/include/asm-ppc64/memory.h
deleted file mode 100644
index af53ffb55726..000000000000
--- a/include/asm-ppc64/memory.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef _ASM_PPC64_MEMORY_H_ 
-#define _ASM_PPC64_MEMORY_H_ 
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/config.h>
-/*
- * Arguably the bitops and *xchg operations don't imply any memory barrier
- * or SMP ordering, but in fact a lot of drivers expect them to imply
- * both, since they do on x86 cpus.
- */
-#ifdef CONFIG_SMP
-#define EIEIO_ON_SMP    "eieio\n"
-#define ISYNC_ON_SMP    "\n\tisync"
-#define SYNC_ON_SMP     "lwsync\n\t"
-#else
-#define EIEIO_ON_SMP
-#define ISYNC_ON_SMP
-#define SYNC_ON_SMP
-#endif
-static inline void eieio(void)
-{
-        __asm__ __volatile__ ("eieio" : : : "memory");
-}
-static inline void isync(void)
-{
-        __asm__ __volatile__ ("isync" : : : "memory");
-}
-#ifdef CONFIG_SMP
-#define eieio_on_smp()  eieio()
-#define isync_on_smp()  isync()
-#else
-#define eieio_on_smp()  __asm__ __volatile__("": : :"memory")
-#define isync_on_smp()  __asm__ __volatile__("": : :"memory")
-#endif
-/* Macros for adjusting thread priority (hardware multi-threading) */
-#define HMT_very_low()    asm volatile("or 31,31,31   # very low priority")
-#define HMT_low()       asm volatile("or 1,1,1          # low priority")
-#define HMT_medium_low()  asm volatile("or 6,6,6      # medium low priority")
-#define HMT_medium()    asm volatile("or 2,2,2          # medium priority")
-#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
-#define HMT_high()      asm volatile("or 3,3,3          # high priority")
-#define HMT_VERY_LOW    "\tor   31,31,31        # very low priority\n"
-#define HMT_LOW         "\tor   1,1,1           # low priority\n"
-#define HMT_MEDIUM_LOW  "\tor   6,6,6           # medium low priority\n"
-#define HMT_MEDIUM      "\tor   2,2,2           # medium priority\n"
-#define HMT_MEDIUM_HIGH "\tor   5,5,5           # medium high priority\n"
-#define HMT_HIGH        "\tor   3,3,3           # high priority\n"
-#endif
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index 7bc42eb087ad..e0505acb77d9 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -14,6 +14,7 @@
 #define _PPC64_MMU_H_
 #include <linux/config.h>
+#include <asm/ppc_asm.h> /* for ASM_CONST */
 #include <asm/page.h>
 /*
@@ -29,7 +30,7 @@
 /* Location of cpu0's segment table */
 #define STAB0_PAGE      0x6
-#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
+#define STAB0_PHYS_ADDR (STAB0_PAGE<<12)
 #ifndef __ASSEMBLY__
 extern char initial_stab[];
@@ -205,6 +206,10 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
                               unsigned long prpn,
                               unsigned long vflags, unsigned long rflags);
+extern long iSeries_hpte_bolt_or_insert(unsigned long hpte_group,
+                unsigned long va, unsigned long prpn,
+                unsigned long vflags, unsigned long rflags);
 extern void stabs_alloc(void);
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-ppc64/mmu_context.h b/include/asm-ppc64/mmu_context.h
index 77a743402db4..820dd729b895 100644
--- a/include/asm-ppc64/mmu_context.h
+++ b/include/asm-ppc64/mmu_context.h
@@ -16,21 +16,6 @@
 * 2 of the License, or (at your option) any later version.
 */
-/*
- * Every architecture must define this function. It's the fastest
- * way of searching a 140-bit bitmap where the first 100 bits are
- * unlikely to be set. It's guaranteed that at least one of the 140
- * bits is cleared.
- */
-static inline int sched_find_first_bit(unsigned long *b)
-{
-        if (unlikely(b[0]))
-                return __ffs(b[0]);
-        if (unlikely(b[1]))
-                return __ffs(b[1]) + 64;
-        return __ffs(b[2]) + 128;
-}
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 }
diff --git a/include/asm-ppc64/mmzone.h b/include/asm-ppc64/mmzone.h
index ed473f4b0152..80a708e7093a 100644
--- a/include/asm-ppc64/mmzone.h
+++ b/include/asm-ppc64/mmzone.h
@@ -67,9 +67,6 @@ static inline int pa_to_nid(unsigned long pa)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)       (NODE_DATA(nid)->node_end_pfn)
-#define local_mapnr(kvaddr) \
-        ( (__pa(kvaddr) >> PAGE_SHIFT) - node_start_pfn(kvaddr_to_nid(kvaddr)) 
 #ifdef CONFIG_DISCONTIGMEM
 /*
diff --git a/include/asm-ppc64/naca.h b/include/asm-ppc64/naca.h
deleted file mode 100644
index d2afe6447597..000000000000
--- a/include/asm-ppc64/naca.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef _NACA_H
-#define _NACA_H
-/* 
- * c 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <asm/types.h>
-struct naca_struct {
-        /* Kernel only data - undefined for user space */
-        void *xItVpdAreas;              /* VPD Data                  0x00 */
-        void *xRamDisk;                 /* iSeries ramdisk           0x08 */
-        u64   xRamDiskSize;             /* In pages                  0x10 */
-};
-extern struct naca_struct naca;
-#endif /* _NACA_H */
diff --git a/include/asm-ppc64/numnodes.h b/include/asm-ppc64/numnodes.h
deleted file mode 100644
index 75ae0b906708..000000000000
--- a/include/asm-ppc64/numnodes.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _ASM_MAX_NUMNODES_H
-#define _ASM_MAX_NUMNODES_H
-/* Max 16 Nodes */
-#define NODES_SHIFT     4
-#endif /* _ASM_MAX_NUMNODES_H */
diff --git a/include/asm-ppc64/nvram.h b/include/asm-ppc64/nvram.h
index dfaa21566c9a..def47d720d3d 100644
--- a/include/asm-ppc64/nvram.h
+++ b/include/asm-ppc64/nvram.h
@@ -70,7 +70,7 @@ extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
 extern int pSeries_nvram_init(void);
 extern int pmac_nvram_init(void);
-extern int bpa_nvram_init(void);
+extern int mmio_nvram_init(void);
 /* PowerMac specific nvram stuffs */
diff --git a/include/asm-ppc64/of_device.h b/include/asm-ppc64/of_device.h
deleted file mode 100644
index 7bc136e22590..000000000000
--- a/include/asm-ppc64/of_device.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/of_device.h>
diff --git a/include/asm-ppc64/paca.h b/include/asm-ppc64/paca.h
index 2f0f36f73d38..f68fe91debaf 100644
--- a/include/asm-ppc64/paca.h
+++ b/include/asm-ppc64/paca.h
@@ -19,7 +19,7 @@
 #include        <linux/config.h>
 #include        <asm/types.h>
 #include        <asm/lppaca.h>
-#include        <asm/iSeries/ItLpRegSave.h>
+#include        <asm/iseries/it_lp_reg_save.h>
 #include        <asm/mmu.h>
 register struct paca_struct *local_paca asm("r13");
diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h
index a15422bcf30d..d404431f0a9a 100644
--- a/include/asm-ppc64/page.h
+++ b/include/asm-ppc64/page.h
@@ -11,13 +11,7 @@
 */
 #include <linux/config.h>
+#include <asm/ppc_asm.h> /* for ASM_CONST */
-#ifdef __ASSEMBLY__
-  #define ASM_CONST(x) x
-#else
-  #define __ASM_CONST(x) x##UL
-  #define ASM_CONST(x) __ASM_CONST(x)
-#endif
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT      12
diff --git a/include/asm-ppc64/pci-bridge.h b/include/asm-ppc64/pci-bridge.h
index d8991389ab39..60cf8c838af0 100644
--- a/include/asm-ppc64/pci-bridge.h
+++ b/include/asm-ppc64/pci-bridge.h
@@ -2,7 +2,9 @@
 #ifndef _ASM_PCI_BRIDGE_H
 #define _ASM_PCI_BRIDGE_H
+#include <linux/config.h>
 #include <linux/pci.h>
+#include <linux/list.h>
 /*
 * This program is free software; you can redistribute it and/or
@@ -34,7 +36,7 @@ struct pci_controller {
        struct pci_ops *ops;
        volatile unsigned int __iomem *cfg_addr;
-        volatile unsigned char __iomem *cfg_data;
+        volatile void __iomem *cfg_data;
        /* Currently, we limit ourselves to 1 IO range and 3 mem
         * ranges since the common pci_bus structure can't handle more
@@ -71,6 +73,12 @@ struct pci_dn {
        struct  iommu_table *iommu_table;       /* for phb's or bridges */
        struct  pci_dev *pcidev;        /* back-pointer to the pci device */
        struct  device_node *node;      /* back-pointer to the device_node */
+#ifdef CONFIG_PPC_ISERIES
+        struct  list_head Device_List;
+        int             Irq;            /* Assigned IRQ */
+        int             Flags;          /* Possible flags(disable/bist)*/
+        u8              LogicalSlot;    /* Hv Slot Index for Tces */
+#endif
        u32     config_space[16];       /* saved PCI config space */
 };
@@ -96,6 +104,16 @@ static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
        return fetch_dev_dn(dev);
 }
+static inline int pci_device_from_OF_node(struct device_node *np,
+                                          u8 *bus, u8 *devfn)
+{
+        if (!PCI_DN(np))
+                return -ENODEV;
+        *bus = PCI_DN(np)->busno;
+        *devfn = PCI_DN(np)->devfn;
+        return 0;
+}
 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
 {
        if (bus->self)
@@ -105,7 +123,7 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
 }
 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
-                                         struct device_node *dev);
+                                         struct device_node *dev, int primary);
 extern int pcibios_remove_root_bus(struct pci_controller *phb);
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index a88bbfc26967..342e2d755550 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -168,7 +168,7 @@ extern void pcibios_add_platform_entries(struct pci_dev *dev);
 struct file;
 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
-                                         unsigned long offset,
+                                         unsigned long pfn,
                                         unsigned long size,
                                         pgprot_t prot);
diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h
index c83679c9d2b0..8c3f574046b6 100644
--- a/include/asm-ppc64/pgtable.h
+++ b/include/asm-ppc64/pgtable.h
@@ -471,17 +471,19 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
                                     unsigned long size, pgprot_t vma_prot);
 #define __HAVE_PHYS_MEM_ACCESS_PROT
 #define __HAVE_ARCH_PTE_SAME
 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 #define pmd_ERROR(e) \
        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 #define pud_ERROR(e) \
-        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pud_val(e))
+        printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
 #define pgd_ERROR(e) \
        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
diff --git a/include/asm-ppc64/plpar_wrappers.h b/include/asm-ppc64/plpar_wrappers.h
deleted file mode 100644
index 72dd2449ee76..000000000000
--- a/include/asm-ppc64/plpar_wrappers.h
+++ /dev/null
@@ -1,120 +0,0 @@
-#ifndef _PPC64_PLPAR_WRAPPERS_H
-#define _PPC64_PLPAR_WRAPPERS_H
-#include <asm/hvcall.h>
-static inline long poll_pending(void)
-{
-        unsigned long dummy;
-        return plpar_hcall(H_POLL_PENDING, 0, 0, 0, 0,
-                           &dummy, &dummy, &dummy);
-}
-static inline long prod_processor(void)
-{
-        plpar_hcall_norets(H_PROD);
-        return(0); 
-}
-static inline long cede_processor(void)
-{
-        plpar_hcall_norets(H_CEDE);
-        return(0); 
-}
-static inline long register_vpa(unsigned long flags, unsigned long proc,
-                                unsigned long vpa)
-{
-        return plpar_hcall_norets(H_REGISTER_VPA, flags, proc, vpa);
-}
-void vpa_init(int cpu);
-static inline long plpar_pte_remove(unsigned long flags,
-                                    unsigned long ptex,
-                                    unsigned long avpn,
-                                    unsigned long *old_pteh_ret,
-                                    unsigned long *old_ptel_ret)
-{
-        unsigned long dummy;
-        return plpar_hcall(H_REMOVE, flags, ptex, avpn, 0,
-                           old_pteh_ret, old_ptel_ret, &dummy);
-}
-static inline long plpar_pte_read(unsigned long flags,
-                                  unsigned long ptex,
-                                  unsigned long *old_pteh_ret, unsigned long *old_ptel_ret)
-{
-        unsigned long dummy;
-        return plpar_hcall(H_READ, flags, ptex, 0, 0,
-                           old_pteh_ret, old_ptel_ret, &dummy);
-}
-static inline long plpar_pte_protect(unsigned long flags,
-                                     unsigned long ptex,
-                                     unsigned long avpn)
-{
-        return plpar_hcall_norets(H_PROTECT, flags, ptex, avpn);
-}
-static inline long plpar_tce_get(unsigned long liobn,
-                                 unsigned long ioba,
-                                 unsigned long *tce_ret)
-{
-        unsigned long dummy;
-        return plpar_hcall(H_GET_TCE, liobn, ioba, 0, 0,
-                           tce_ret, &dummy, &dummy);
-}
-static inline long plpar_tce_put(unsigned long liobn,
-                                 unsigned long ioba,
-                                 unsigned long tceval)
-{
-        return plpar_hcall_norets(H_PUT_TCE, liobn, ioba, tceval);
-}
-static inline long plpar_tce_put_indirect(unsigned long liobn,
-                                          unsigned long ioba,
-                                          unsigned long page,
-                                          unsigned long count)
-{
-        return plpar_hcall_norets(H_PUT_TCE_INDIRECT, liobn, ioba, page, count);
-}
-static inline long plpar_tce_stuff(unsigned long liobn,
-                                   unsigned long ioba,
-                                   unsigned long tceval,
-                                   unsigned long count)
-{
-        return plpar_hcall_norets(H_STUFF_TCE, liobn, ioba, tceval, count);
-}
-static inline long plpar_get_term_char(unsigned long termno,
-                                       unsigned long *len_ret,
-                                       char *buf_ret)
-{
-        unsigned long *lbuf = (unsigned long *)buf_ret;  /* ToDo: alignment? */
-        return plpar_hcall(H_GET_TERM_CHAR, termno, 0, 0, 0,
-                           len_ret, lbuf+0, lbuf+1);
-}
-static inline long plpar_put_term_char(unsigned long termno,
-                                       unsigned long len,
-                                       const char *buffer)
-{
-        unsigned long *lbuf = (unsigned long *)buffer;  /* ToDo: alignment? */
-        return plpar_hcall_norets(H_PUT_TERM_CHAR, termno, len, lbuf[0],
-                                  lbuf[1]);
-}
-static inline long plpar_set_xdabr(unsigned long address, unsigned long flags)
-{
-        return plpar_hcall_norets(H_SET_XDABR, address, flags);
-}
-static inline long plpar_set_dabr(unsigned long val)
-{
-        return plpar_hcall_norets(H_SET_DABR, val);
-}
-#endif /* _PPC64_PLPAR_WRAPPERS_H */
diff --git a/include/asm-ppc64/pmac_feature.h b/include/asm-ppc64/pmac_feature.h
deleted file mode 100644
index e07e36c4cbb2..000000000000
--- a/include/asm-ppc64/pmac_feature.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/pmac_feature.h>
diff --git a/include/asm-ppc64/pmac_low_i2c.h b/include/asm-ppc64/pmac_low_i2c.h
deleted file mode 100644
index 7bcfc72c5c8a..000000000000
--- a/include/asm-ppc64/pmac_low_i2c.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/pmac_low_i2c.h>
diff --git a/include/asm-ppc64/ppc32.h b/include/asm-ppc64/ppc32.h
deleted file mode 100644
index 6b44a8caf395..000000000000
--- a/include/asm-ppc64/ppc32.h
+++ /dev/null
@@ -1,122 +0,0 @@
-#ifndef _PPC64_PPC32_H
-#define _PPC64_PPC32_H
-#include <linux/compat.h>
-#include <asm/siginfo.h>
-#include <asm/signal.h>
-/*
- * Data types and macros for providing 32b PowerPC support.
- * 
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-/* These are here to support 32-bit syscalls on a 64-bit kernel. */
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-        union {
-                int _pad[SI_PAD_SIZE32];
-                /* kill() */
-                struct {
-                        compat_pid_t _pid;              /* sender's pid */
-                        compat_uid_t _uid;              /* sender's uid */
-                } _kill;
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;                    /* timer id */
-                        int _overrun;                   /* overrun count */
-                        compat_sigval_t _sigval;                /* same as below */
-                        int _sys_private;               /* not to be passed to user */
-                } _timer;
-                /* POSIX.1b signals */
-                struct {
-                        compat_pid_t _pid;              /* sender's pid */
-                        compat_uid_t _uid;              /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-                /* SIGCHLD */
-                struct {
-                        compat_pid_t _pid;              /* which child */
-                        compat_uid_t _uid;              /* sender's uid */
-                        int _status;                    /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGEMT */
-                struct {
-                        unsigned int _addr; /* faulting insn/memory ref. */
-                } _sigfault;
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-} compat_siginfo_t;
-#define __old_sigaction32       old_sigaction32
-struct __old_sigaction32 {
-        unsigned                sa_handler;
-        compat_old_sigset_t     sa_mask;
-        unsigned int            sa_flags;
-        unsigned                sa_restorer;     /* not used by Linux/SPARC yet */
-};
-struct sigaction32 {
-       unsigned int  sa_handler;        /* Really a pointer, but need to deal with 32 bits */
-       unsigned int sa_flags;
-       unsigned int sa_restorer;        /* Another 32 bit pointer */
-       compat_sigset_t sa_mask;         /* A 32 bit mask */
-};
-typedef struct sigaltstack_32 {
-        unsigned int ss_sp;
-        int ss_flags;
-        compat_size_t ss_size;
-} stack_32_t;
-struct sigcontext32 {
-        unsigned int    _unused[4];
-        int             signal;
-        unsigned int    handler;
-        unsigned int    oldmask;
-        u32 regs;  /* 4 byte pointer to the pt_regs32 structure. */
-};
-struct mcontext32 {
-        elf_gregset_t32         mc_gregs;
-        elf_fpregset_t          mc_fregs;
-        unsigned int            mc_pad[2];
-        elf_vrregset_t32        mc_vregs __attribute__((__aligned__(16)));
-};
-struct ucontext32 { 
-        unsigned int            uc_flags;
-        unsigned int            uc_link;
-        stack_32_t              uc_stack;
-        int                     uc_pad[7];
-        u32                     uc_regs;        /* points to uc_mcontext field */
-        compat_sigset_t         uc_sigmask;     /* mask last for extensibility */
-        /* glibc has 1024-bit signal masks, ours are 64-bit */
-        int                     uc_maskext[30];
-        int                     uc_pad2[3];
-        struct mcontext32       uc_mcontext;
-};
-#endif  /* _PPC64_PPC32_H */
diff --git a/include/asm-ppc64/ppc_asm.h b/include/asm-ppc64/ppc_asm.h
deleted file mode 100644
index 9031d8a29aca..000000000000
--- a/include/asm-ppc64/ppc_asm.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * arch/ppc64/kernel/ppc_asm.h
- *
- * Definitions used by various bits of low-level assembly code on PowerPC.
- *
- * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifndef _PPC64_PPC_ASM_H
-#define _PPC64_PPC_ASM_H
-/*
- * Macros for storing registers into and loading registers from
- * exception frames.
- */
-#define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
-#define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
-#define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
-#define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
-#define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
-#define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
-#define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
-#define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
-#define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
-#define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
-#define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
-#define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
-#define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
-#define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
-#define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
-#define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
-#define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*(n)(base)
-#define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
-#define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
-#define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
-#define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
-#define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
-#define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
-#define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
-#define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
-#define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
-#define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
-#define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
-#define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
-#define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
-#define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
-#define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
-#define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
-#define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
-/* Macros to adjust thread priority for Iseries hardware multithreading */
-#define HMT_LOW         or 1,1,1
-#define HMT_MEDIUM      or 2,2,2
-#define HMT_HIGH        or 3,3,3
-/* Insert the high 32 bits of the MSR into what will be the new
-   MSR (via SRR1 and rfid)  This preserves the MSR.SF and MSR.ISF
-   bits. */
-#define FIX_SRR1(ra, rb)        \
-        mr      rb,ra;          \
-        mfmsr   ra;             \
-        rldimi  ra,rb,0,32
-#define CLR_TOP32(r)    rlwinm  (r),(r),0,0,31  /* clear top 32 bits */
-/* 
- * LOADADDR( rn, name )
- *   loads the address of 'name' into 'rn'
- *
- * LOADBASE( rn, name )
- *   loads the address (less the low 16 bits) of 'name' into 'rn'
- *   suitable for base+disp addressing
- */
-#define LOADADDR(rn,name) \
-        lis     rn,name##@highest;      \
-        ori     rn,rn,name##@higher;    \
-        rldicr  rn,rn,32,31;            \
-        oris    rn,rn,name##@h;         \
-        ori     rn,rn,name##@l
-#define LOADBASE(rn,name) \
-        lis     rn,name@highest;        \
-        ori     rn,rn,name@higher;      \
-        rldicr  rn,rn,32,31;            \
-        oris    rn,rn,name@ha
-#define SET_REG_TO_CONST(reg, value)                    \
-        lis     reg,(((value)>>48)&0xFFFF);             \
-        ori     reg,reg,(((value)>>32)&0xFFFF);         \
-        rldicr  reg,reg,32,31;                          \
-        oris    reg,reg,(((value)>>16)&0xFFFF);         \
-        ori     reg,reg,((value)&0xFFFF);
-#define SET_REG_TO_LABEL(reg, label)                    \
-        lis     reg,(label)@highest;                    \
-        ori     reg,reg,(label)@higher;                 \
-        rldicr  reg,reg,32,31;                          \
-        oris    reg,reg,(label)@h;                      \
-        ori     reg,reg,(label)@l;
-/* PPPBBB - DRENG  If KERNELBASE is always 0xC0...,
- * Then we can easily do this with one asm insn. -Peter
- */
-#define tophys(rd,rs)                           \
-        lis     rd,((KERNELBASE>>48)&0xFFFF);   \
-        rldicr  rd,rd,32,31;                    \
-        sub     rd,rs,rd
-#define tovirt(rd,rs)                           \
-        lis     rd,((KERNELBASE>>48)&0xFFFF);   \
-        rldicr  rd,rd,32,31;                    \
-        add     rd,rs,rd
-/* Condition Register Bit Fields */
-#define cr0     0
-#define cr1     1
-#define cr2     2
-#define cr3     3
-#define cr4     4
-#define cr5     5
-#define cr6     6
-#define cr7     7
-/* General Purpose Registers (GPRs) */
-#define r0      0
-#define r1      1
-#define r2      2
-#define r3      3
-#define r4      4
-#define r5      5
-#define r6      6
-#define r7      7
-#define r8      8
-#define r9      9
-#define r10     10
-#define r11     11
-#define r12     12
-#define r13     13
-#define r14     14
-#define r15     15
-#define r16     16
-#define r17     17
-#define r18     18
-#define r19     19
-#define r20     20
-#define r21     21
-#define r22     22
-#define r23     23
-#define r24     24
-#define r25     25
-#define r26     26
-#define r27     27
-#define r28     28
-#define r29     29
-#define r30     30
-#define r31     31
-/* Floating Point Registers (FPRs) */
-#define fr0     0
-#define fr1     1
-#define fr2     2
-#define fr3     3
-#define fr4     4
-#define fr5     5
-#define fr6     6
-#define fr7     7
-#define fr8     8
-#define fr9     9
-#define fr10    10
-#define fr11    11
-#define fr12    12
-#define fr13    13
-#define fr14    14
-#define fr15    15
-#define fr16    16
-#define fr17    17
-#define fr18    18
-#define fr19    19
-#define fr20    20
-#define fr21    21
-#define fr22    22
-#define fr23    23
-#define fr24    24
-#define fr25    25
-#define fr26    26
-#define fr27    27
-#define fr28    28
-#define fr29    29
-#define fr30    30
-#define fr31    31
-#define vr0     0
-#define vr1     1
-#define vr2     2
-#define vr3     3
-#define vr4     4
-#define vr5     5
-#define vr6     6
-#define vr7     7
-#define vr8     8
-#define vr9     9
-#define vr10    10
-#define vr11    11
-#define vr12    12
-#define vr13    13
-#define vr14    14
-#define vr15    15
-#define vr16    16
-#define vr17    17
-#define vr18    18
-#define vr19    19
-#define vr20    20
-#define vr21    21
-#define vr22    22
-#define vr23    23
-#define vr24    24
-#define vr25    25
-#define vr26    26
-#define vr27    27
-#define vr28    28
-#define vr29    29
-#define vr30    30
-#define vr31    31
-#endif /* _PPC64_PPC_ASM_H */
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
deleted file mode 100644
index 4146189006e3..000000000000
--- a/include/asm-ppc64/processor.h
+++ /dev/null
@@ -1,558 +0,0 @@
-#ifndef __ASM_PPC64_PROCESSOR_H
-#define __ASM_PPC64_PROCESSOR_H
-/*
- * Copyright (C) 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/stringify.h>
-#ifndef __ASSEMBLY__
-#include <linux/config.h>
-#include <asm/atomic.h>
-#include <asm/ppcdebug.h>
-#include <asm/a.out.h>
-#endif
-#include <asm/ptrace.h>
-#include <asm/types.h>
-#include <asm/systemcfg.h>
-#include <asm/cputable.h>
-/* Machine State Register (MSR) Fields */
-#define MSR_SF_LG       63              /* Enable 64 bit mode */
-#define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
-#define MSR_HV_LG       60              /* Hypervisor state */
-#define MSR_VEC_LG      25              /* Enable AltiVec */
-#define MSR_POW_LG      18              /* Enable Power Management */
-#define MSR_WE_LG       18              /* Wait State Enable */
-#define MSR_TGPR_LG     17              /* TLB Update registers in use */
-#define MSR_CE_LG       17              /* Critical Interrupt Enable */
-#define MSR_ILE_LG      16              /* Interrupt Little Endian */
-#define MSR_EE_LG       15              /* External Interrupt Enable */
-#define MSR_PR_LG       14              /* Problem State / Privilege Level */
-#define MSR_FP_LG       13              /* Floating Point enable */
-#define MSR_ME_LG       12              /* Machine Check Enable */
-#define MSR_FE0_LG      11              /* Floating Exception mode 0 */
-#define MSR_SE_LG       10              /* Single Step */
-#define MSR_BE_LG       9               /* Branch Trace */
-#define MSR_DE_LG       9               /* Debug Exception Enable */
-#define MSR_FE1_LG      8               /* Floating Exception mode 1 */
-#define MSR_IP_LG       6               /* Exception prefix 0x000/0xFFF */
-#define MSR_IR_LG       5               /* Instruction Relocate */
-#define MSR_DR_LG       4               /* Data Relocate */
-#define MSR_PE_LG       3               /* Protection Enable */
-#define MSR_PX_LG       2               /* Protection Exclusive Mode */
-#define MSR_PMM_LG      2               /* Performance monitor */
-#define MSR_RI_LG       1               /* Recoverable Exception */
-#define MSR_LE_LG       0               /* Little Endian */
-#ifdef __ASSEMBLY__
-#define __MASK(X)       (1<<(X))
-#else
-#define __MASK(X)       (1UL<<(X))
-#endif
-#define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
-#define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
-#define MSR_HV          __MASK(MSR_HV_LG)       /* Hypervisor state */
-#define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
-#define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
-#define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
-#define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
-#define MSR_CE          __MASK(MSR_CE_LG)       /* Critical Interrupt Enable */
-#define MSR_ILE         __MASK(MSR_ILE_LG)      /* Interrupt Little Endian */
-#define MSR_EE          __MASK(MSR_EE_LG)       /* External Interrupt Enable */
-#define MSR_PR          __MASK(MSR_PR_LG)       /* Problem State / Privilege Level */
-#define MSR_FP          __MASK(MSR_FP_LG)       /* Floating Point enable */
-#define MSR_ME          __MASK(MSR_ME_LG)       /* Machine Check Enable */
-#define MSR_FE0         __MASK(MSR_FE0_LG)      /* Floating Exception mode 0 */
-#define MSR_SE          __MASK(MSR_SE_LG)       /* Single Step */
-#define MSR_BE          __MASK(MSR_BE_LG)       /* Branch Trace */
-#define MSR_DE          __MASK(MSR_DE_LG)       /* Debug Exception Enable */
-#define MSR_FE1         __MASK(MSR_FE1_LG)      /* Floating Exception mode 1 */
-#define MSR_IP          __MASK(MSR_IP_LG)       /* Exception prefix 0x000/0xFFF */
-#define MSR_IR          __MASK(MSR_IR_LG)       /* Instruction Relocate */
-#define MSR_DR          __MASK(MSR_DR_LG)       /* Data Relocate */
-#define MSR_PE          __MASK(MSR_PE_LG)       /* Protection Enable */
-#define MSR_PX          __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
-#define MSR_PMM         __MASK(MSR_PMM_LG)      /* Performance monitor */
-#define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
-#define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
-#define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
-#define MSR_KERNEL      MSR_ | MSR_SF | MSR_HV
-#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64      MSR_USER32 | MSR_SF
-/* Floating Point Status and Control Register (FPSCR) Fields */
-#define FPSCR_FX        0x80000000      /* FPU exception summary */
-#define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
-#define FPSCR_VX        0x20000000      /* Invalid operation summary */
-#define FPSCR_OX        0x10000000      /* Overflow exception summary */
-#define FPSCR_UX        0x08000000      /* Underflow exception summary */
-#define FPSCR_ZX        0x04000000      /* Zero-divide exception summary */
-#define FPSCR_XX        0x02000000      /* Inexact exception summary */
-#define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
-#define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
-#define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
-#define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
-#define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
-#define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
-#define FPSCR_FR        0x00040000      /* Fraction rounded */
-#define FPSCR_FI        0x00020000      /* Fraction inexact */
-#define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
-#define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
-#define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
-#define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
-#define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
-#define FPSCR_VE        0x00000080      /* Invalid op exception enable */
-#define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
-#define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
-#define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
-#define FPSCR_XE        0x00000008      /* FP inexact exception enable */
-#define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
-#define FPSCR_RN        0x00000003      /* FPU rounding control */
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_CTR        0x009   /* Count Register */
-#define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
-#define   DABR_TRANSLATION      (1UL << 2)
-#define SPRN_DAR        0x013   /* Data Address Register */
-#define SPRN_DEC        0x016   /* Decrement Register */
-#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
-#define   DSISR_NOHPTE          0x40000000      /* no translation found */
-#define   DSISR_PROTFAULT       0x08000000      /* protection fault */
-#define   DSISR_ISSTORE         0x02000000      /* access was a store */
-#define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
-#define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
-#define SPRN_HID0       0x3F0   /* Hardware Implementation Register 0 */
-#define SPRN_MSRDORM    0x3F1   /* Hardware Implementation Register 1 */
-#define SPRN_HID1       0x3F1   /* Hardware Implementation Register 1 */
-#define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
-#define SPRN_NIADORM    0x3F3   /* Hardware Implementation Register 2 */
-#define SPRN_HID4       0x3F4   /* 970 HID4 */
-#define SPRN_HID5       0x3F6   /* 970 HID5 */
-#define SPRN_HID6       0x3F9   /* BE HID 6 */
-#define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
-#define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
-#define SPRN_TSCR       0x399   /* Thread switch control on BE */
-#define SPRN_TTR        0x39A   /* Thread switch timeout on BE */
-#define   TSCR_DEC_ENABLE       0x200000 /* Decrementer Interrupt */
-#define   TSCR_EE_ENABLE        0x100000 /* External Interrupt */
-#define   TSCR_EE_BOOST         0x080000 /* External Interrupt Boost */
-#define SPRN_TSC        0x3FD   /* Thread switch control on others */
-#define SPRN_TST        0x3FC   /* Thread switch timeout on others */
-#define SPRN_L2CR       0x3F9   /* Level 2 Cache Control Regsiter */
-#define SPRN_LR         0x008   /* Link Register */
-#define SPRN_PIR        0x3FF   /* Processor Identification Register */
-#define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
-#define SPRN_PURR       0x135   /* Processor Utilization of Resources Register */
-#define SPRN_PVR        0x11F   /* Processor Version Register */
-#define SPRN_RPA        0x3D6   /* Required Physical Address Register */
-#define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
-#define SPRN_SDR1       0x019   /* MMU Hash Base Register */
-#define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
-#define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
-#define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
-#define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
-#define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
-#define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
-#define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
-#define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
-#define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
-#define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, W/O) */
-#define SPRN_TBWU       0x11D   /* Time Base Write Upper Register (super, W/O) */
-#define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
-#define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
-#define SPRN_XER        0x001   /* Fixed Point Exception Register */
-#define SPRN_VRSAVE     0x100   /* Vector save */
-#define SPRN_CTRLF      0x088
-#define SPRN_CTRLT      0x098
-#define   CTRL_RUNLATCH 0x1
-/* Performance monitor SPRs */
-#define SPRN_SIAR       780
-#define SPRN_SDAR       781
-#define SPRN_MMCRA      786
-#define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
-#define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
-#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
-#define SPRN_PMC1       787
-#define SPRN_PMC2       788
-#define SPRN_PMC3       789
-#define SPRN_PMC4       790
-#define SPRN_PMC5       791
-#define SPRN_PMC6       792
-#define SPRN_PMC7       793
-#define SPRN_PMC8       794
-#define SPRN_MMCR0      795
-#define   MMCR0_FC      0x80000000UL /* freeze counters. set to 1 on a perfmon exception */
-#define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
-#define   MMCR0_KERNEL_DISABLE MMCR0_FCS
-#define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
-#define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
-#define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
-#define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
-#define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
-#define   MMCR0_FCECE   0x02000000UL /* freeze counters on enabled condition or event */
-/* time base exception enable */
-#define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
-#define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
-#define   MMCR0_PMCjCE  0x00004000UL /* PMCj count enable*/
-#define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
-#define   MMCR0_PMAO    0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
-#define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
-#define   MMCR0_FCTI    0x00000008UL /* freeze counters in tags inactive mode */
-#define   MMCR0_FCTA    0x00000004UL /* freeze counters in tags active mode */
-#define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
-#define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
-#define SPRN_MMCR1      798
-/* Short-hand versions for a number of the above SPRNs */
-#define CTR     SPRN_CTR        /* Counter Register */
-#define DAR     SPRN_DAR        /* Data Address Register */
-#define DABR    SPRN_DABR       /* Data Address Breakpoint Register */
-#define DEC     SPRN_DEC        /* Decrement Register */
-#define DSISR   SPRN_DSISR      /* Data Storage Interrupt Status Register */
-#define HID0    SPRN_HID0       /* Hardware Implementation Register 0 */
-#define MSRDORM SPRN_MSRDORM    /* MSR Dormant Register */
-#define NIADORM SPRN_NIADORM    /* NIA Dormant Register */
-#define TSC     SPRN_TSC        /* Thread switch control */
-#define TST     SPRN_TST        /* Thread switch timeout */
-#define IABR    SPRN_IABR       /* Instruction Address Breakpoint Register */
-#define L2CR    SPRN_L2CR       /* PPC 750 L2 control register */
-#define __LR    SPRN_LR
-#define PVR     SPRN_PVR        /* Processor Version */
-#define PIR     SPRN_PIR        /* Processor ID */
-#define PURR    SPRN_PURR       /* Processor Utilization of Resource Register */
-#define SDR1    SPRN_SDR1       /* MMU hash base register */
-#define SPR0    SPRN_SPRG0      /* Supervisor Private Registers */
-#define SPR1    SPRN_SPRG1
-#define SPR2    SPRN_SPRG2
-#define SPR3    SPRN_SPRG3
-#define SPRG0   SPRN_SPRG0
-#define SPRG1   SPRN_SPRG1
-#define SPRG2   SPRN_SPRG2
-#define SPRG3   SPRN_SPRG3
-#define SRR0    SPRN_SRR0       /* Save and Restore Register 0 */
-#define SRR1    SPRN_SRR1       /* Save and Restore Register 1 */
-#define TBRL    SPRN_TBRL       /* Time Base Read Lower Register */
-#define TBRU    SPRN_TBRU       /* Time Base Read Upper Register */
-#define TBWL    SPRN_TBWL       /* Time Base Write Lower Register */
-#define TBWU    SPRN_TBWU       /* Time Base Write Upper Register */
-#define XER     SPRN_XER
-/* Processor Version Register (PVR) field extraction */
-#define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF) /* Version field */
-#define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF) /* Revison field */
-/* Processor Version Numbers */
-#define PV_NORTHSTAR    0x0033
-#define PV_PULSAR       0x0034
-#define PV_POWER4       0x0035
-#define PV_ICESTAR      0x0036
-#define PV_SSTAR        0x0037
-#define PV_POWER4p      0x0038
-#define PV_970          0x0039
-#define PV_POWER5       0x003A
-#define PV_POWER5p      0x003B
-#define PV_970FX        0x003C
-#define PV_630          0x0040
-#define PV_630p         0x0041
-#define PV_970MP        0x0044
-#define PV_BE           0x0070
-/* Platforms supported by PPC64 */
-#define PLATFORM_PSERIES      0x0100
-#define PLATFORM_PSERIES_LPAR 0x0101
-#define PLATFORM_ISERIES_LPAR 0x0201
-#define PLATFORM_LPAR         0x0001
-#define PLATFORM_POWERMAC     0x0400
-#define PLATFORM_MAPLE        0x0500
-#define PLATFORM_BPA          0x1000
-/* Compatibility with drivers coming from PPC32 world */
-#define _machine        (systemcfg->platform)
-#define _MACH_Pmac      PLATFORM_POWERMAC
-/*
- * List of interrupt controllers.
- */
-#define IC_INVALID    0
-#define IC_OPEN_PIC   1
-#define IC_PPC_XIC    2
-#define IC_BPA_IIC    3
-#define XGLUE(a,b) a##b
-#define GLUE(a,b) XGLUE(a,b)
-#ifdef __ASSEMBLY__
-#define _GLOBAL(name) \
-        .section ".text"; \
-        .align 2 ; \
-        .globl name; \
-        .globl GLUE(.,name); \
-        .section ".opd","aw"; \
-name: \
-        .quad GLUE(.,name); \
-        .quad .TOC.@tocbase; \
-        .quad 0; \
-        .previous; \
-        .type GLUE(.,name),@function; \
-GLUE(.,name):
-#define _KPROBE(name) \
-        .section ".kprobes.text","a"; \
-        .align 2 ; \
-        .globl name; \
-        .globl GLUE(.,name); \
-        .section ".opd","aw"; \
-name: \
-        .quad GLUE(.,name); \
-        .quad .TOC.@tocbase; \
-        .quad 0; \
-        .previous; \
-        .type GLUE(.,name),@function; \
-GLUE(.,name):
-#define _STATIC(name) \
-        .section ".text"; \
-        .align 2 ; \
-        .section ".opd","aw"; \
-name: \
-        .quad GLUE(.,name); \
-        .quad .TOC.@tocbase; \
-        .quad 0; \
-        .previous; \
-        .type GLUE(.,name),@function; \
-GLUE(.,name):
-#else /* __ASSEMBLY__ */
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-/* Macros for setting and retrieving special purpose registers */
-#define mfmsr()         ({unsigned long rval; \
-                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-#define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
-                                     : : "r" (v))
-#define mtmsrd(v)       __mtmsrd((v), 0)
-#define mfspr(rn)       ({unsigned long rval; \
-                        asm volatile("mfspr %0," __stringify(rn) \
-                                     : "=r" (rval)); rval;})
-#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
-#define mftb()          ({unsigned long rval;   \
-                        asm volatile("mftb %0" : "=r" (rval)); rval;})
-#define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
-#define mttbu(v)        asm volatile("mttbu %0":: "r"(v))
-#define mfasr()         ({unsigned long rval; \
-                        asm volatile("mfasr %0" : "=r" (rval)); rval;})
-static inline void set_tb(unsigned int upper, unsigned int lower)
-{
-        mttbl(0);
-        mttbu(upper);
-        mttbl(lower);
-}
-#define __get_SP()      ({unsigned long sp; \
-                        asm volatile("mr %0,1": "=r" (sp)); sp;})
-#ifdef __KERNEL__
-extern int have_of;
-extern u64 ppc64_interrupt_controller;
-struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
-void release_thread(struct task_struct *);
-/* Prepare to copy thread state - unlazy all lazy status */
-extern void prepare_to_copy(struct task_struct *tsk);
-/* Create a new kernel thread. */
-extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
-extern struct task_struct *last_task_used_altivec;
-/* 64-bit user address space is 44-bits (16TB user VM) */
-#define TASK_SIZE_USER64 (0x0000100000000000UL)
-/* 
- * 32-bit user address space is 4GB - 1 page 
- * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
- */
-#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
-#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
-                TASK_SIZE_USER32 : TASK_SIZE_USER64)
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
-#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
-#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)||(ppcdebugset(PPCDBG_BINFMT_32ADDR))) ? \
-                TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
-typedef struct {
-        unsigned long seg;
-} mm_segment_t;
-struct thread_struct {
-        unsigned long   ksp;            /* Kernel stack pointer */
-        unsigned long   ksp_vsid;
-        struct pt_regs  *regs;          /* Pointer to saved register state */
-        mm_segment_t    fs;             /* for get_fs() validation */
-        double          fpr[32];        /* Complete floating point set */
-        unsigned long   fpscr;          /* Floating point status (plus pad) */
-        unsigned long   fpexc_mode;     /* Floating-point exception mode */
-        unsigned long   start_tb;       /* Start purr when proc switched in */
-        unsigned long   accum_tb;       /* Total accumilated purr for process */
-        unsigned long   vdso_base;      /* base of the vDSO library */
-        unsigned long   dabr;           /* Data address breakpoint register */
-#ifdef CONFIG_ALTIVEC
-        /* Complete AltiVec register set */
-        vector128       vr[32] __attribute((aligned(16)));
-        /* AltiVec status */
-        vector128       vscr __attribute((aligned(16)));
-        unsigned long   vrsave;
-        int             used_vr;        /* set if process has used altivec */
-#endif /* CONFIG_ALTIVEC */
-};
-#define ARCH_MIN_TASKALIGN 16
-#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
-#define INIT_THREAD  { \
-        .ksp = INIT_SP, \
-        .regs = (struct pt_regs *)INIT_SP - 1, \
-        .fs = KERNEL_DS, \
-        .fpr = {0}, \
-        .fpscr = 0, \
-        .fpexc_mode = MSR_FE0|MSR_FE1, \
-}
-/*
- * Return saved PC of a blocked thread. For now, this is the "user" PC
- */
-#define thread_saved_pc(tsk)    \
-        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
-unsigned long get_wchan(struct task_struct *p);
-#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
-#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
-/* Get/set floating-point exception mode */
-#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
-#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
-extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
-extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
-static inline unsigned int __unpack_fe01(unsigned long msr_bits)
-{
-        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
-}
-static inline unsigned long __pack_fe01(unsigned int fpmode)
-{
-        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
-}
-#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
-/*
- * Prefetch macros.
- */
-#define ARCH_HAS_PREFETCH
-#define ARCH_HAS_PREFETCHW
-#define ARCH_HAS_SPINLOCK_PREFETCH
-static inline void prefetch(const void *x)
-{
-        if (unlikely(!x))
-                return;
-        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
-}
-static inline void prefetchw(const void *x)
-{
-        if (unlikely(!x))
-                return;
-        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
-}
-#define spin_lock_prefetch(x)   prefetchw(x)
-#define HAVE_ARCH_PICK_MMAP_LAYOUT
-static inline void ppc64_runlatch_on(void)
-{
-        unsigned long ctrl;
-        if (cpu_has_feature(CPU_FTR_CTRL)) {
-                ctrl = mfspr(SPRN_CTRLF);
-                ctrl |= CTRL_RUNLATCH;
-                mtspr(SPRN_CTRLT, ctrl);
-        }
-}
-static inline void ppc64_runlatch_off(void)
-{
-        unsigned long ctrl;
-        if (cpu_has_feature(CPU_FTR_CTRL)) {
-                ctrl = mfspr(SPRN_CTRLF);
-                ctrl &= ~CTRL_RUNLATCH;
-                mtspr(SPRN_CTRLT, ctrl);
-        }
-}
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-#ifdef __KERNEL__
-#define RUNLATCH_ON(REG)                        \
-BEGIN_FTR_SECTION                               \
-        mfspr   (REG),SPRN_CTRLF;               \
-        ori     (REG),(REG),CTRL_RUNLATCH;      \
-        mtspr   SPRN_CTRLT,(REG);               \
-END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
-#endif
-/*
- * Number of entries in the SLB. If this ever changes we should handle
- * it with a use a cpu feature fixup.
- */
-#define SLB_NUM_ENTRIES 64
-#endif /* __ASM_PPC64_PROCESSOR_H */
diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h
index c02ec1d6b909..e8d0d2ab4c0f 100644
--- a/include/asm-ppc64/prom.h
+++ b/include/asm-ppc64/prom.h
@@ -14,6 +14,7 @@
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
+#include <linux/config.h>
 #include <linux/proc_fs.h>
 #include <asm/atomic.h>
@@ -137,6 +138,9 @@ struct device_node {
        struct  kref kref;
        unsigned long _flags;
        void    *data;
+#ifdef CONFIG_PPC_ISERIES
+        struct list_head Device_List;
+#endif
 };
 extern struct device_node *of_chosen;
diff --git a/include/asm-ppc64/spinlock.h b/include/asm-ppc64/spinlock.h
index 14cb895bb607..7d84fb5e39f1 100644
--- a/include/asm-ppc64/spinlock.h
+++ b/include/asm-ppc64/spinlock.h
@@ -21,7 +21,7 @@
 #include <linux/config.h>
 #include <asm/paca.h>
 #include <asm/hvcall.h>
-#include <asm/iSeries/HvCall.h>
+#include <asm/iseries/hv_call.h>
 #define __raw_spin_is_locked(x)         ((x)->slock != 0)
diff --git a/include/asm-ppc64/stat.h b/include/asm-ppc64/stat.h
deleted file mode 100644
index 973a5f97951d..000000000000
--- a/include/asm-ppc64/stat.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef _PPC64_STAT_H
-#define _PPC64_STAT_H
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/types.h>
-struct stat {
-        unsigned long   st_dev;
-        ino_t           st_ino;
-        nlink_t         st_nlink;
-        mode_t          st_mode;
-        uid_t           st_uid;
-        gid_t           st_gid;
-        unsigned long   st_rdev;
-        off_t           st_size;
-        unsigned long   st_blksize;
-        unsigned long   st_blocks;
-        unsigned long   st_atime;
-        unsigned long   st_atime_nsec;
-        unsigned long   st_mtime;
-        unsigned long   st_mtime_nsec;
-        unsigned long   st_ctime;
-        unsigned long   st_ctime_nsec;
-        unsigned long   __unused4;
-        unsigned long   __unused5;
-        unsigned long   __unused6;
-};
-#define STAT_HAVE_NSEC 1
-/* This matches struct stat64 in glibc2.1. Only used for 32 bit. */
-struct stat64 {
-        unsigned long st_dev;           /* Device.  */
-        unsigned long st_ino;           /* File serial number.  */
-        unsigned int st_mode;           /* File mode.  */
-        unsigned int st_nlink;          /* Link count.  */
-        unsigned int st_uid;            /* User ID of the file's owner.  */
-        unsigned int st_gid;            /* Group ID of the file's group. */
-        unsigned long st_rdev;          /* Device number, if device.  */
-        unsigned short __pad2;
-        long st_size;                   /* Size of file, in bytes.  */
-        int  st_blksize;                /* Optimal block size for I/O.  */
-        long st_blocks;                 /* Number 512-byte blocks allocated. */
-        int   st_atime;                 /* Time of last access.  */
-        int   st_atime_nsec;
-        int   st_mtime;                 /* Time of last modification.  */
-        int   st_mtime_nsec;
-        int   st_ctime;                 /* Time of last status change.  */
-        int   st_ctime_nsec;
-        unsigned int   __unused4;
-        unsigned int   __unused5;
-};
-#endif
diff --git a/include/asm-ppc64/system.h b/include/asm-ppc64/system.h
index 375015c62f20..99b8ca52f101 100644
--- a/include/asm-ppc64/system.h
+++ b/include/asm-ppc64/system.h
@@ -13,7 +13,7 @@
 #include <asm/page.h>
 #include <asm/processor.h>
 #include <asm/hw_irq.h>
-#include <asm/memory.h>
+#include <asm/synch.h>
 /*
 * Memory barrier.
@@ -48,7 +48,7 @@
 #ifdef CONFIG_SMP
 #define smp_mb()        mb()
 #define smp_rmb()       rmb()
-#define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
+#define smp_wmb()       eieio()
 #define smp_read_barrier_depends()  read_barrier_depends()
 #else
 #define smp_mb()        __asm__ __volatile__("": : :"memory")
@@ -120,8 +120,8 @@ extern void giveup_altivec(struct task_struct *);
 extern void disable_kernel_altivec(void);
 extern void enable_kernel_altivec(void);
 extern int emulate_altivec(struct pt_regs *);
-extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
+extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
-extern void cvt_df(double *from, float *to, unsigned long *fpscr);
+extern void cvt_df(double *from, float *to, struct thread_struct *thread);
 #ifdef CONFIG_ALTIVEC
 extern void flush_altivec_to_thread(struct task_struct *);
@@ -131,7 +131,12 @@ static inline void flush_altivec_to_thread(struct task_struct *t)
 }
 #endif
+static inline void flush_spe_to_thread(struct task_struct *t)
+{
+}
 extern int mem_init_done;       /* set on boot once kmalloc can be called */
+extern unsigned long memory_limit;
 /* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
 extern unsigned char e2a(unsigned char);
@@ -144,12 +149,7 @@ struct thread_struct;
 extern struct task_struct * _switch(struct thread_struct *prev,
                                    struct thread_struct *next);
-static inline int __is_processor(unsigned long pv)
+extern int powersave_nap;       /* set if nap mode can be used in idle loop */
-{
-        unsigned long pvr;
-        asm("mfspr %0, 0x11F" : "=r" (pvr)); 
-        return(PVR_VER(pvr) == pv);
-}
 /*
 * Atomic exchange
diff --git a/include/asm-ppc64/tce.h b/include/asm-ppc64/tce.h
new file mode 100644
index 000000000000..d40b6b42ab35
--- /dev/null
+++ b/include/asm-ppc64/tce.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
+ * Rewrite, cleanup:
+ * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_TCE_H
+#define _ASM_TCE_H
+/*
+ * Tces come in two formats, one for the virtual bus and a different
+ * format for PCI
+ */
+#define TCE_VB  0
+#define TCE_PCI 1
+/* TCE page size is 4096 bytes (1 << 12) */
+#define TCE_SHIFT       12
+#define TCE_PAGE_SIZE   (1 << TCE_SHIFT)
+#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
+/* tce_entry
+ * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
+ * abstracted so layout is irrelevant.
+ */
+union tce_entry {
+        unsigned long te_word;
+        struct {
+                unsigned int  tb_cacheBits :6;  /* Cache hash bits - not used */
+                unsigned int  tb_rsvd      :6;
+                unsigned long tb_rpn       :40; /* Real page number */
+                unsigned int  tb_valid     :1;  /* Tce is valid (vb only) */
+                unsigned int  tb_allio     :1;  /* Tce is valid for all lps (vb only) */
+                unsigned int  tb_lpindex   :8;  /* LpIndex for user of TCE (vb only) */
+                unsigned int  tb_pciwr     :1;  /* Write allowed (pci only) */
+                unsigned int  tb_rdwr      :1;  /* Read allowed  (pci), Write allowed (vb) */
+        } te_bits;
+#define te_cacheBits te_bits.tb_cacheBits
+#define te_rpn       te_bits.tb_rpn
+#define te_valid     te_bits.tb_valid
+#define te_allio     te_bits.tb_allio
+#define te_lpindex   te_bits.tb_lpindex
+#define te_pciwr     te_bits.tb_pciwr
+#define te_rdwr      te_bits.tb_rdwr
+};
+#endif
diff --git a/include/asm-ppc64/time.h b/include/asm-ppc64/time.h
deleted file mode 100644
index c6c762cad8b0..000000000000
--- a/include/asm-ppc64/time.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Common time prototypes and such for all ppc machines.
- *
- * Written by Cort Dougan (cort@cs.nmt.edu) to merge
- * Paul Mackerras' version and mine for PReP and Pmac.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __PPC64_TIME_H
-#define __PPC64_TIME_H
-#ifdef __KERNEL__
-#include <linux/config.h>
-#include <linux/types.h>
-#include <linux/mc146818rtc.h>
-#include <asm/processor.h>
-#include <asm/paca.h>
-#include <asm/iSeries/HvCall.h>
-/* time.c */
-extern unsigned long tb_ticks_per_jiffy;
-extern unsigned long tb_ticks_per_usec;
-extern unsigned long tb_ticks_per_sec;
-extern unsigned long tb_to_xs;
-extern unsigned      tb_to_us;
-extern unsigned long tb_last_stamp;
-struct rtc_time;
-extern void to_tm(int tim, struct rtc_time * tm);
-extern time_t last_rtc_update;
-void generic_calibrate_decr(void);
-void setup_default_decr(void);
-/* Some sane defaults: 125 MHz timebase, 1GHz processor */
-extern unsigned long ppc_proc_freq;
-#define DEFAULT_PROC_FREQ       (DEFAULT_TB_FREQ * 8)
-extern unsigned long ppc_tb_freq;
-#define DEFAULT_TB_FREQ         125000000UL
-/*
- * By putting all of this stuff into a single struct we 
- * reduce the number of cache lines touched by do_gettimeofday.
- * Both by collecting all of the data in one cache line and
- * by touching only one TOC entry
- */
-struct gettimeofday_vars {
-        unsigned long tb_to_xs;
-        unsigned long stamp_xsec;
-        unsigned long tb_orig_stamp;
-};
-struct gettimeofday_struct {
-        unsigned long tb_ticks_per_sec;
-        struct gettimeofday_vars vars[2];
-        struct gettimeofday_vars * volatile varp;
-        unsigned      var_idx;
-        unsigned      tb_to_us;
-};
-struct div_result {
-        unsigned long result_high;
-        unsigned long result_low;
-};
-int via_calibrate_decr(void);
-static __inline__ unsigned long get_tb(void)
-{
-        return mftb();
-}
-/* Accessor functions for the decrementer register. */
-static __inline__ unsigned int get_dec(void)
-{
-        return (mfspr(SPRN_DEC));
-}
-static __inline__ void set_dec(int val)
-{
-#ifdef CONFIG_PPC_ISERIES
-        struct paca_struct *lpaca = get_paca();
-        int cur_dec;
-        if (lpaca->lppaca.shared_proc) {
-                lpaca->lppaca.virtual_decr = val;
-                cur_dec = get_dec();
-                if (cur_dec > val)
-                        HvCall_setVirtualDecr();
-        } else
-#endif
-                mtspr(SPRN_DEC, val);
-}
-static inline unsigned long tb_ticks_since(unsigned long tstamp)
-{
-        return get_tb() - tstamp;
-}
-#define mulhwu(x,y) \
-({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
-#define mulhdu(x,y) \
-({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
-unsigned mulhwu_scale_factor(unsigned, unsigned);
-void div128_by_32( unsigned long dividend_high, unsigned long dividend_low,
-                   unsigned divisor, struct div_result *dr );
-/* Used to store Processor Utilization register (purr) values */
-struct cpu_usage {
-        u64 current_tb;  /* Holds the current purr register values */
-};
-DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
-#endif /* __KERNEL__ */
-#endif /* __PPC64_TIME_H */
diff --git a/include/asm-ppc64/tlb.h b/include/asm-ppc64/tlb.h
deleted file mode 100644
index 97cb696ce68d..000000000000
--- a/include/asm-ppc64/tlb.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *      TLB shootdown specifics for PPC64
- *
- * Copyright (C) 2002 Anton Blanchard, IBM Corp.
- * Copyright (C) 2002 Paul Mackerras, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _PPC64_TLB_H
-#define _PPC64_TLB_H
-#include <asm/tlbflush.h>
-struct mmu_gather;
-extern void pte_free_finish(void);
-static inline void tlb_flush(struct mmu_gather *tlb)
-{
-        flush_tlb_pending();
-        pte_free_finish();
-}
-/* Avoid pulling in another include just for this */
-#define check_pgt_cache()       do { } while (0)
-/* Get the generic bits... */
-#include <asm-generic/tlb.h>
-/* Nothing needed here in fact... */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma)   do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
-#endif /* _PPC64_TLB_H */
diff --git a/include/asm-ppc64/tlbflush.h b/include/asm-ppc64/tlbflush.h
deleted file mode 100644
index 74271d7c1d16..000000000000
--- a/include/asm-ppc64/tlbflush.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _PPC64_TLBFLUSH_H
-#define _PPC64_TLBFLUSH_H
-/*
- * TLB flushing:
- *
- *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
- *  - flush_tlb_page(vma, vmaddr) flushes one page
- *  - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
- *  - flush_tlb_range(vma, start, end) flushes a range of pages
- *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
- */
-#include <linux/percpu.h>
-#include <asm/page.h>
-#define PPC64_TLB_BATCH_NR 192
-struct mm_struct;
-struct ppc64_tlb_batch {
-        unsigned long index;
-        unsigned long context;
-        struct mm_struct *mm;
-        pte_t pte[PPC64_TLB_BATCH_NR];
-        unsigned long addr[PPC64_TLB_BATCH_NR];
-        unsigned long vaddr[PPC64_TLB_BATCH_NR];
-        unsigned int large;
-};
-DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
-extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
-static inline void flush_tlb_pending(void)
-{
-        struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
-        if (batch->index)
-                __flush_tlb_pending(batch);
-        put_cpu_var(ppc64_tlb_batch);
-}
-#define flush_tlb_mm(mm)                        flush_tlb_pending()
-#define flush_tlb_page(vma, addr)               flush_tlb_pending()
-#define flush_tlb_page_nohash(vma, addr)        do { } while (0)
-#define flush_tlb_range(vma, start, end) \
-                do { (void)(start); flush_tlb_pending(); } while (0)
-#define flush_tlb_kernel_range(start, end)      flush_tlb_pending()
-#define flush_tlb_pgtables(mm, start, end)      do { } while (0)
-extern void flush_hash_page(unsigned long context, unsigned long ea, pte_t pte,
-                            int local);
-void flush_hash_range(unsigned long context, unsigned long number, int local);
-#endif /* _PPC64_TLBFLUSH_H */
diff --git a/include/asm-ppc64/uaccess.h b/include/asm-ppc64/uaccess.h
deleted file mode 100644
index 132c1276547b..000000000000
--- a/include/asm-ppc64/uaccess.h
+++ /dev/null
@@ -1,341 +0,0 @@
-#ifndef _PPC64_UACCESS_H
-#define _PPC64_UACCESS_H
-/* 
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASSEMBLY__
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <asm/processor.h>
-#define VERIFY_READ     0
-#define VERIFY_WRITE    1
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
-#define KERNEL_DS       MAKE_MM_SEG(0UL)
-#define USER_DS         MAKE_MM_SEG(0xf000000000000000UL)
-#define get_ds()        (KERNEL_DS)
-#define get_fs()        (current->thread.fs)
-#define set_fs(val)     (current->thread.fs = (val))
-#define segment_eq(a,b) ((a).seg == (b).seg)
-/*
- * Use the alpha trick for checking ranges:
- *
- * Is a address valid? This does a straightforward calculation rather
- * than tests.
- *
- * Address valid if:
- *  - "addr" doesn't have any high-bits set
- *  - AND "size" doesn't have any high-bits set
- *  - OR we are in kernel mode.
- *
- * We dont have to check for high bits in (addr+size) because the first
- * two checks force the maximum result to be below the start of the
- * kernel region.
- */
-#define __access_ok(addr,size,segment) \
-        (((segment).seg & (addr | size )) == 0)
-#define access_ok(type,addr,size) \
-        __access_ok(((__force unsigned long)(addr)),(size),get_fs())
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-struct exception_table_entry
-{
-        unsigned long insn, fixup;
-};
-/* Returns 0 if exception not found and fixup otherwise.  */
-extern unsigned long search_exception_table(unsigned long);
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- *
- * As we use the same address space for kernel and user data on the
- * PowerPC, we can just do these as direct assignments.  (Of course, the
- * exception handling means that it's no longer "just"...)
- */
-#define get_user(x,ptr) \
-  __get_user_check((x),(ptr),sizeof(*(ptr)))
-#define put_user(x,ptr) \
-  __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
-#define __get_user(x,ptr) \
-  __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
-#define __put_user(x,ptr) \
-  __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
-#define __get_user_unaligned __get_user
-#define __put_user_unaligned __put_user
-extern long __put_user_bad(void);
-#define __put_user_nocheck(x,ptr,size)                          \
-({                                                              \
-        long __pu_err;                                          \
-        might_sleep();                                          \
-        __chk_user_ptr(ptr);                                    \
-        __put_user_size((x),(ptr),(size),__pu_err,-EFAULT);     \
-        __pu_err;                                               \
-})
-#define __put_user_check(x,ptr,size)                                    \
-({                                                                      \
-        long __pu_err = -EFAULT;                                        \
-        void __user *__pu_addr = (ptr);                                 \
-        might_sleep();                                                  \
-        if (access_ok(VERIFY_WRITE,__pu_addr,size))                     \
-                __put_user_size((x),__pu_addr,(size),__pu_err,-EFAULT); \
-        __pu_err;                                                       \
-})
-#define __put_user_size(x,ptr,size,retval,errret)                       \
-do {                                                                    \
-        retval = 0;                                                     \
-        switch (size) {                                                 \
-          case 1: __put_user_asm(x,ptr,retval,"stb",errret); break;     \
-          case 2: __put_user_asm(x,ptr,retval,"sth",errret); break;     \
-          case 4: __put_user_asm(x,ptr,retval,"stw",errret); break;     \
-          case 8: __put_user_asm(x,ptr,retval,"std",errret); break;     \
-          default: __put_user_bad();                                    \
-        }                                                               \
-} while (0)
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- */
-#define __put_user_asm(x, addr, err, op, errret)                \
-        __asm__ __volatile__(                                   \
-                "1:     "op" %1,0(%2)   # put_user\n"           \
-                "2:\n"                                          \
-                ".section .fixup,\"ax\"\n"                      \
-                "3:     li %0,%3\n"                             \
-                "       b 2b\n"                                 \
-                ".previous\n"                                   \
-                ".section __ex_table,\"a\"\n"                   \
-                "       .align 3\n"                             \
-                "       .llong 1b,3b\n"                         \
-                ".previous"                                     \
-                : "=r"(err)                                     \
-                : "r"(x), "b"(addr), "i"(errret), "0"(err))
-#define __get_user_nocheck(x,ptr,size)                          \
-({                                                              \
-        long __gu_err;                                          \
-        unsigned long __gu_val;                                 \
-        might_sleep();                                          \
-        __get_user_size(__gu_val,(ptr),(size),__gu_err,-EFAULT);\
-        (x) = (__typeof__(*(ptr)))__gu_val;                     \
-        __gu_err;                                               \
-})
-#define __get_user_check(x,ptr,size)                                    \
-({                                                                      \
-        long __gu_err = -EFAULT;                                        \
-        unsigned long __gu_val = 0;                                     \
-        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);             \
-        might_sleep();                                                  \
-        if (access_ok(VERIFY_READ,__gu_addr,size))                      \
-                __get_user_size(__gu_val,__gu_addr,(size),__gu_err,-EFAULT);\
-        (x) = (__typeof__(*(ptr)))__gu_val;                             \
-        __gu_err;                                                       \
-})
-extern long __get_user_bad(void);
-#define __get_user_size(x,ptr,size,retval,errret)                       \
-do {                                                                    \
-        retval = 0;                                                     \
-        __chk_user_ptr(ptr);                                            \
-        switch (size) {                                                 \
-          case 1: __get_user_asm(x,ptr,retval,"lbz",errret); break;     \
-          case 2: __get_user_asm(x,ptr,retval,"lhz",errret); break;     \
-          case 4: __get_user_asm(x,ptr,retval,"lwz",errret); break;     \
-          case 8: __get_user_asm(x,ptr,retval,"ld",errret);  break;     \
-          default: (x) = __get_user_bad();                              \
-        }                                                               \
-} while (0)
-#define __get_user_asm(x, addr, err, op, errret)        \
-        __asm__ __volatile__(                           \
-                "1:     "op" %1,0(%2)   # get_user\n"   \
-                "2:\n"                                  \
-                ".section .fixup,\"ax\"\n"              \
-                "3:     li %0,%3\n"                     \
-                "       li %1,0\n"                      \
-                "       b 2b\n"                         \
-                ".previous\n"                           \
-                ".section __ex_table,\"a\"\n"           \
-                "       .align 3\n"                     \
-                "       .llong 1b,3b\n"                 \
-                ".previous"                             \
-                : "=r"(err), "=r"(x)                    \
-                : "b"(addr), "i"(errret), "0"(err))
-/* more complex routines */
-extern unsigned long __copy_tofrom_user(void __user *to, const void __user *from,
-                                        unsigned long size);
-static inline unsigned long
-__copy_from_user_inatomic(void *to, const void __user *from, unsigned long n)
-{
-        if (__builtin_constant_p(n)) {
-                unsigned long ret;
-                switch (n) {
-                case 1:
-                        __get_user_size(*(u8 *)to, from, 1, ret, 1);
-                        return ret;
-                case 2:
-                        __get_user_size(*(u16 *)to, from, 2, ret, 2);
-                        return ret;
-                case 4:
-                        __get_user_size(*(u32 *)to, from, 4, ret, 4);
-                        return ret;
-                case 8:
-                        __get_user_size(*(u64 *)to, from, 8, ret, 8);
-                        return ret;
-                }
-        }
-        return __copy_tofrom_user((__force void __user *) to, from, n);
-}
-static inline unsigned long
-__copy_from_user(void *to, const void __user *from, unsigned long n)
-{
-        might_sleep();
-        return __copy_from_user_inatomic(to, from, n);
-}
-static inline unsigned long
-__copy_to_user_inatomic(void __user *to, const void *from, unsigned long n)
-{
-        if (__builtin_constant_p(n)) {
-                unsigned long ret;
-                switch (n) {
-                case 1:
-                        __put_user_size(*(u8 *)from, (u8 __user *)to, 1, ret, 1);
-                        return ret;
-                case 2:
-                        __put_user_size(*(u16 *)from, (u16 __user *)to, 2, ret, 2);
-                        return ret;
-                case 4:
-                        __put_user_size(*(u32 *)from, (u32 __user *)to, 4, ret, 4);
-                        return ret;
-                case 8:
-                        __put_user_size(*(u64 *)from, (u64 __user *)to, 8, ret, 8);
-                        return ret;
-                }
-        }
-        return __copy_tofrom_user(to, (__force const void __user *) from, n);
-}
-static inline unsigned long
-__copy_to_user(void __user *to, const void *from, unsigned long n)
-{
-        might_sleep();
-        return __copy_to_user_inatomic(to, from, n);
-}
-#define __copy_in_user(to, from, size) \
-        __copy_tofrom_user((to), (from), (size))
-extern unsigned long copy_from_user(void *to, const void __user *from,
-                                    unsigned long n);
-extern unsigned long copy_to_user(void __user *to, const void *from,
-                                  unsigned long n);
-extern unsigned long copy_in_user(void __user *to, const void __user *from,
-                                  unsigned long n);
-extern unsigned long __clear_user(void __user *addr, unsigned long size);
-static inline unsigned long
-clear_user(void __user *addr, unsigned long size)
-{
-        might_sleep();
-        if (likely(access_ok(VERIFY_WRITE, addr, size)))
-                size = __clear_user(addr, size);
-        return size;
-}
-extern int __strncpy_from_user(char *dst, const char __user *src, long count);
-static inline long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        might_sleep();
-        if (likely(access_ok(VERIFY_READ, src, 1)))
-                return __strncpy_from_user(dst, src, count);
-        return -EFAULT;
-}
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 for error
- */
-extern int __strnlen_user(const char __user *str, long len);
-/*
- * Returns the length of the string at str (including the null byte),
- * or 0 if we hit a page we can't access,
- * or something > len if we didn't find a null byte.
- */
-static inline int strnlen_user(const char __user *str, long len)
-{
-        might_sleep();
-        if (likely(access_ok(VERIFY_READ, str, 1)))
-                return __strnlen_user(str, len);
-        return 0;
-}
-#define strlen_user(str)        strnlen_user((str), 0x7ffffffe)
-#endif  /* __ASSEMBLY__ */
-#endif  /* _PPC64_UACCESS_H */
diff --git a/include/asm-ppc64/ucontext.h b/include/asm-ppc64/ucontext.h
deleted file mode 100644
index ef8cc5b37542..000000000000
--- a/include/asm-ppc64/ucontext.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _ASMPPC64_UCONTEXT_H
-#define _ASMPPC64_UCONTEXT_H
-#include <asm/sigcontext.h>
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-struct ucontext {
-        unsigned long     uc_flags;
-        struct ucontext  *uc_link;
-        stack_t           uc_stack;
-        sigset_t          uc_sigmask;
-        sigset_t          __unsued[15]; /* Allow for uc_sigmask growth */
-        struct sigcontext uc_mcontext;  /* last for extensibility */
-};
-#endif /* _ASMPPC64_UCONTEXT_H */
diff --git a/include/asm-ppc64/udbg.h b/include/asm-ppc64/udbg.h
index c786604aef02..8192fb8541cc 100644
--- a/include/asm-ppc64/udbg.h
+++ b/include/asm-ppc64/udbg.h
@@ -28,4 +28,7 @@ extern unsigned long udbg_ifdebug(unsigned long flags);
 extern void __init ppcdbg_initialize(void);
 extern void udbg_init_uart(void __iomem *comport, unsigned int speed);
+struct device_node;
+extern void udbg_init_scc(struct device_node *np);
 #endif
diff --git a/include/asm-ppc64/uninorth.h b/include/asm-ppc64/uninorth.h
deleted file mode 100644
index 7ad7059f2c80..000000000000
--- a/include/asm-ppc64/uninorth.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-ppc/uninorth.h>
diff --git a/include/asm-ppc64/unistd.h b/include/asm-ppc64/unistd.h
deleted file mode 100644
index 977bc980c1af..000000000000
--- a/include/asm-ppc64/unistd.h
+++ /dev/null
@@ -1,487 +0,0 @@
-#ifndef _ASM_PPC_UNISTD_H_
-#define _ASM_PPC_UNISTD_H_
-/*
- * This file contains the system call numbers.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#define __NR_restart_syscall      0
-#define __NR_exit                 1
-#define __NR_fork                 2
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_open                 5
-#define __NR_close                6
-#define __NR_waitpid              7
-#define __NR_creat                8
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_execve              11
-#define __NR_chdir               12
-#define __NR_time                13
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_lchown              16
-#define __NR_break               17
-#define __NR_oldstat             18
-#define __NR_lseek               19
-#define __NR_getpid              20
-#define __NR_mount               21
-#define __NR_umount              22
-#define __NR_setuid              23
-#define __NR_getuid              24
-#define __NR_stime               25
-#define __NR_ptrace              26
-#define __NR_alarm               27
-#define __NR_oldfstat            28
-#define __NR_pause               29
-#define __NR_utime               30
-#define __NR_stty                31
-#define __NR_gtty                32
-#define __NR_access              33
-#define __NR_nice                34
-#define __NR_ftime               35
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_rename              38
-#define __NR_mkdir               39
-#define __NR_rmdir               40
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_times               43
-#define __NR_prof                44
-#define __NR_brk                 45
-#define __NR_setgid              46
-#define __NR_getgid              47
-#define __NR_signal              48
-#define __NR_geteuid             49
-#define __NR_getegid             50
-#define __NR_acct                51
-#define __NR_umount2             52
-#define __NR_lock                53
-#define __NR_ioctl               54
-#define __NR_fcntl               55
-#define __NR_mpx                 56
-#define __NR_setpgid             57
-#define __NR_ulimit              58
-#define __NR_oldolduname         59
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_ustat               62
-#define __NR_dup2                63
-#define __NR_getppid             64
-#define __NR_getpgrp             65
-#define __NR_setsid              66
-#define __NR_sigaction           67
-#define __NR_sgetmask            68
-#define __NR_ssetmask            69
-#define __NR_setreuid            70
-#define __NR_setregid            71
-#define __NR_sigsuspend          72
-#define __NR_sigpending          73
-#define __NR_sethostname         74
-#define __NR_setrlimit           75
-#define __NR_getrlimit           76
-#define __NR_getrusage           77
-#define __NR_gettimeofday        78
-#define __NR_settimeofday        79
-#define __NR_getgroups           80
-#define __NR_setgroups           81
-#define __NR_select              82
-#define __NR_symlink             83
-#define __NR_oldlstat            84
-#define __NR_readlink            85
-#define __NR_uselib              86
-#define __NR_swapon              87
-#define __NR_reboot              88
-#define __NR_readdir             89
-#define __NR_mmap                90
-#define __NR_munmap              91
-#define __NR_truncate            92
-#define __NR_ftruncate           93
-#define __NR_fchmod              94
-#define __NR_fchown              95
-#define __NR_getpriority         96
-#define __NR_setpriority         97
-#define __NR_profil              98
-#define __NR_statfs              99
-#define __NR_fstatfs            100
-#define __NR_ioperm             101
-#define __NR_socketcall         102
-#define __NR_syslog             103
-#define __NR_setitimer          104
-#define __NR_getitimer          105
-#define __NR_stat               106
-#define __NR_lstat              107
-#define __NR_fstat              108
-#define __NR_olduname           109
-#define __NR_iopl               110
-#define __NR_vhangup            111
-#define __NR_idle               112
-#define __NR_vm86               113
-#define __NR_wait4              114
-#define __NR_swapoff            115
-#define __NR_sysinfo            116
-#define __NR_ipc                117
-#define __NR_fsync              118
-#define __NR_sigreturn          119
-#define __NR_clone              120
-#define __NR_setdomainname      121
-#define __NR_uname              122
-#define __NR_modify_ldt         123
-#define __NR_adjtimex           124
-#define __NR_mprotect           125
-#define __NR_sigprocmask        126
-#define __NR_create_module      127
-#define __NR_init_module        128
-#define __NR_delete_module      129
-#define __NR_get_kernel_syms    130
-#define __NR_quotactl           131
-#define __NR_getpgid            132
-#define __NR_fchdir             133
-#define __NR_bdflush            134
-#define __NR_sysfs              135
-#define __NR_personality        136
-#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
-#define __NR_setfsuid           138
-#define __NR_setfsgid           139
-#define __NR__llseek            140
-#define __NR_getdents           141
-#define __NR__newselect         142
-#define __NR_flock              143
-#define __NR_msync              144
-#define __NR_readv              145
-#define __NR_writev             146
-#define __NR_getsid             147
-#define __NR_fdatasync          148
-#define __NR__sysctl            149
-#define __NR_mlock              150
-#define __NR_munlock            151
-#define __NR_mlockall           152
-#define __NR_munlockall         153
-#define __NR_sched_setparam             154
-#define __NR_sched_getparam             155
-#define __NR_sched_setscheduler         156
-#define __NR_sched_getscheduler         157
-#define __NR_sched_yield                158
-#define __NR_sched_get_priority_max     159
-#define __NR_sched_get_priority_min     160
-#define __NR_sched_rr_get_interval      161
-#define __NR_nanosleep          162
-#define __NR_mremap             163
-#define __NR_setresuid          164
-#define __NR_getresuid          165
-#define __NR_query_module       166
-#define __NR_poll               167
-#define __NR_nfsservctl         168
-#define __NR_setresgid          169
-#define __NR_getresgid          170
-#define __NR_prctl              171
-#define __NR_rt_sigreturn       172
-#define __NR_rt_sigaction       173
-#define __NR_rt_sigprocmask     174
-#define __NR_rt_sigpending      175
-#define __NR_rt_sigtimedwait    176
-#define __NR_rt_sigqueueinfo    177
-#define __NR_rt_sigsuspend      178
-#define __NR_pread64            179
-#define __NR_pwrite64           180
-#define __NR_chown              181
-#define __NR_getcwd             182
-#define __NR_capget             183
-#define __NR_capset             184
-#define __NR_sigaltstack        185
-#define __NR_sendfile           186
-#define __NR_getpmsg            187     /* some people actually want streams */
-#define __NR_putpmsg            188     /* some people actually want streams */
-#define __NR_vfork              189
-#define __NR_ugetrlimit         190     /* SuS compliant getrlimit */
-#define __NR_readahead          191
-/* #define __NR_mmap2           192     32bit only */
-/* #define __NR_truncate64      193     32bit only */
-/* #define __NR_ftruncate64     194     32bit only */
-/* #define __NR_stat64          195     32bit only */
-/* #define __NR_lstat64         196     32bit only */
-/* #define __NR_fstat64         197     32bit only */
-#define __NR_pciconfig_read     198
-#define __NR_pciconfig_write    199
-#define __NR_pciconfig_iobase   200
-#define __NR_multiplexer        201
-#define __NR_getdents64         202
-#define __NR_pivot_root         203
-/* #define __NR_fcntl64         204     32bit only */
-#define __NR_madvise            205
-#define __NR_mincore            206
-#define __NR_gettid             207
-#define __NR_tkill              208
-#define __NR_setxattr           209
-#define __NR_lsetxattr          210
-#define __NR_fsetxattr          211
-#define __NR_getxattr           212
-#define __NR_lgetxattr          213
-#define __NR_fgetxattr          214
-#define __NR_listxattr          215
-#define __NR_llistxattr         216
-#define __NR_flistxattr         217
-#define __NR_removexattr        218
-#define __NR_lremovexattr       219
-#define __NR_fremovexattr       220
-#define __NR_futex              221
-#define __NR_sched_setaffinity  222
-#define __NR_sched_getaffinity  223
-/* 224 currently unused */
-#define __NR_tuxcall            225
-/* #define __NR_sendfile64      226     32bit only */
-#define __NR_io_setup           227
-#define __NR_io_destroy         228
-#define __NR_io_getevents       229
-#define __NR_io_submit          230
-#define __NR_io_cancel          231
-#define __NR_set_tid_address    232
-#define __NR_fadvise64          233
-#define __NR_exit_group         234
-#define __NR_lookup_dcookie     235
-#define __NR_epoll_create       236
-#define __NR_epoll_ctl          237
-#define __NR_epoll_wait         238
-#define __NR_remap_file_pages   239
-#define __NR_timer_create       240
-#define __NR_timer_settime      241
-#define __NR_timer_gettime      242
-#define __NR_timer_getoverrun   243
-#define __NR_timer_delete       244
-#define __NR_clock_settime      245
-#define __NR_clock_gettime      246
-#define __NR_clock_getres       247
-#define __NR_clock_nanosleep    248
-#define __NR_swapcontext        249
-#define __NR_tgkill             250
-#define __NR_utimes             251
-#define __NR_statfs64           252
-#define __NR_fstatfs64          253
-/* #define __NR_fadvise64_64    254     32bit only */
-#define __NR_rtas               255
-/* Number 256 is reserved for sys_debug_setcontext */
-/* Number 257 is reserved for vserver */
-/* 258 currently unused */
-#define __NR_mbind              259
-#define __NR_get_mempolicy      260
-#define __NR_set_mempolicy      261
-#define __NR_mq_open            262
-#define __NR_mq_unlink          263
-#define __NR_mq_timedsend       264
-#define __NR_mq_timedreceive    265
-#define __NR_mq_notify          266
-#define __NR_mq_getsetattr      267
-#define __NR_kexec_load         268
-#define __NR_add_key            269
-#define __NR_request_key        270
-#define __NR_keyctl             271
-#define __NR_waitid             272
-#define __NR_ioprio_set         273
-#define __NR_ioprio_get         274
-#define __NR_inotify_init       275
-#define __NR_inotify_add_watch  276
-#define __NR_inotify_rm_watch   277
-#define __NR_syscalls           278
-#ifdef __KERNEL__
-#define NR_syscalls     __NR_syscalls
-#endif
-#ifndef __ASSEMBLY__
-/* On powerpc a system call basically clobbers the same registers like a
- * function call, with the exception of LR (which is needed for the
- * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal
- * an error return status).
- */
-#define __syscall_nr(nr, type, name, args...)                           \
-        unsigned long __sc_ret, __sc_err;                               \
-        {                                                               \
-                register unsigned long __sc_0  __asm__ ("r0");          \
-                register unsigned long __sc_3  __asm__ ("r3");          \
-                register unsigned long __sc_4  __asm__ ("r4");          \
-                register unsigned long __sc_5  __asm__ ("r5");          \
-                register unsigned long __sc_6  __asm__ ("r6");          \
-                register unsigned long __sc_7  __asm__ ("r7");          \
-                register unsigned long __sc_8  __asm__ ("r8");          \
-                                                                        \
-                __sc_loadargs_##nr(name, args);                         \
-                __asm__ __volatile__                                    \
-                        ("sc           \n\t"                            \
-                         "mfcr %0      "                                \
-                        : "=&r" (__sc_0),                               \
-                          "=&r" (__sc_3),  "=&r" (__sc_4),              \
-                          "=&r" (__sc_5),  "=&r" (__sc_6),              \
-                          "=&r" (__sc_7),  "=&r" (__sc_8)               \
-                        : __sc_asm_input_##nr                           \
-                        : "cr0", "ctr", "memory",                       \
-                                "r9", "r10","r11", "r12");              \
-                __sc_ret = __sc_3;                                      \
-                __sc_err = __sc_0;                                      \
-        }                                                               \
-        if (__sc_err & 0x10000000)                                      \
-        {                                                               \
-                errno = __sc_ret;                                       \
-                __sc_ret = -1;                                          \
-        }                                                               \
-        return (type) __sc_ret
-#define __sc_loadargs_0(name, dummy...)                                 \
-        __sc_0 = __NR_##name
-#define __sc_loadargs_1(name, arg1)                                     \
-        __sc_loadargs_0(name);                                          \
-        __sc_3 = (unsigned long) (arg1)
-#define __sc_loadargs_2(name, arg1, arg2)                               \
-        __sc_loadargs_1(name, arg1);                                    \
-        __sc_4 = (unsigned long) (arg2)
-#define __sc_loadargs_3(name, arg1, arg2, arg3)                         \
-        __sc_loadargs_2(name, arg1, arg2);                              \
-        __sc_5 = (unsigned long) (arg3)
-#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4)                   \
-        __sc_loadargs_3(name, arg1, arg2, arg3);                        \
-        __sc_6 = (unsigned long) (arg4)
-#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5)             \
-        __sc_loadargs_4(name, arg1, arg2, arg3, arg4);                  \
-        __sc_7 = (unsigned long) (arg5)
-#define __sc_loadargs_6(name, arg1, arg2, arg3, arg4, arg5, arg6)       \
-        __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5);            \
-        __sc_8 = (unsigned long) (arg6)
-#define __sc_asm_input_0 "0" (__sc_0)
-#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3)
-#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4)
-#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5)
-#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6)
-#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7)
-#define __sc_asm_input_6 __sc_asm_input_5, "6" (__sc_8)
-#define _syscall0(type,name)                                            \
-type name(void)                                                         \
-{                                                                       \
-        __syscall_nr(0, type, name);                                    \
-}
-#define _syscall1(type,name,type1,arg1)                                 \
-type name(type1 arg1)                                                   \
-{                                                                       \
-        __syscall_nr(1, type, name, arg1);                              \
-}
-#define _syscall2(type,name,type1,arg1,type2,arg2)                      \
-type name(type1 arg1, type2 arg2)                                       \
-{                                                                       \
-        __syscall_nr(2, type, name, arg1, arg2);                        \
-}
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)           \
-type name(type1 arg1, type2 arg2, type3 arg3)                           \
-{                                                                       \
-        __syscall_nr(3, type, name, arg1, arg2, arg3);                  \
-}
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4)               \
-{                                                                       \
-        __syscall_nr(4, type, name, arg1, arg2, arg3, arg4);            \
-}
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5)   \
-{                                                                       \
-        __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5);      \
-}
-#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6)       \
-{                                                                       \
-        __syscall_nr(6, type, name, arg1, arg2, arg3, arg4, arg5, arg6);        \
-}
-#ifdef __KERNEL_SYSCALLS__
-/*
- * Forking from kernel space will result in the child getting a new,
- * empty kernel stack area.  Thus the child cannot access automatic
- * variables set in the parent unless they are in registers, and the
- * procedure where the fork was done cannot return to its caller in
- * the child.
- */
-/*
- * System call prototypes.
- */
-static inline _syscall3(int, execve, __const__ char *, file, char **, argv,
-                        char **,envp)
-#endif /* __KERNEL_SYSCALLS__ */
-#ifdef __KERNEL__
-#include <linux/types.h>
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_COMPAT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-unsigned long sys_mmap(unsigned long addr, size_t len, unsigned long prot,
-                       unsigned long flags, unsigned long fd, off_t offset);
-struct pt_regs;
-int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
-                unsigned long a3, unsigned long a4, unsigned long a5,
-                struct pt_regs *regs);
-int sys_clone(unsigned long clone_flags, unsigned long p2, unsigned long p3,
-                unsigned long p4, unsigned long p5, unsigned long p6,
-                struct pt_regs *regs);
-int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
-                unsigned long p4, unsigned long p5, unsigned long p6,
-                struct pt_regs *regs);
-int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
-                unsigned long p4, unsigned long p5, unsigned long p6,
-                struct pt_regs *regs);
-int sys_pipe(int __user *fildes);
-int sys_ptrace(long request, long pid, long addr, long data);
-struct sigaction;
-long sys_rt_sigaction(int sig, const struct sigaction __user *act,
-                      struct sigaction __user *oact, size_t sigsetsize);
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t." #x "\n\t.set\t." #x ",.sys_ni_syscall")
-#endif          /* __KERNEL__ */
-#endif          /* __ASSEMBLY__ */
-#endif /* _ASM_PPC_UNISTD_H_ */
diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h
deleted file mode 100644
index 1092af55d707..000000000000
--- a/include/asm-ppc64/xics.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* 
- * arch/ppc64/kernel/xics.h
- *
- * Copyright 2000 IBM Corporation.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifndef _PPC64_KERNEL_XICS_H
-#define _PPC64_KERNEL_XICS_H
-#include <linux/cache.h>
-void xics_init_IRQ(void);
-int xics_get_irq(struct pt_regs *);
-void xics_setup_cpu(void);
-void xics_teardown_cpu(int secondary);
-void xics_cause_IPI(int cpu);
-void xics_request_IPIs(void);
-void xics_migrate_irqs_away(void);
-/* first argument is ignored for now*/
-void pSeriesLP_cppr_info(int n_cpu, u8 value);
-struct xics_ipi_struct {
-        volatile unsigned long value;
-} ____cacheline_aligned;
-extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
-#endif /* _PPC64_KERNEL_XICS_H */
diff --git a/include/asm-s390/rwsem.h b/include/asm-s390/rwsem.h
index 8c0cebbfc034..0422a085dd56 100644
--- a/include/asm-s390/rwsem.h
+++ b/include/asm-s390/rwsem.h
@@ -351,5 +351,10 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
        return new;
 }
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
 #endif /* __KERNEL__ */
 #endif /* _S390_RWSEM_H */
diff --git a/include/asm-s390/semaphore.h b/include/asm-s390/semaphore.h
index 873def6f363a..702cf436698c 100644
--- a/include/asm-s390/semaphore.h
+++ b/include/asm-s390/semaphore.h
@@ -29,9 +29,6 @@ struct semaphore {
 #define __SEMAPHORE_INITIALIZER(name,count) \
        { ATOMIC_INIT(count), __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-s390/setup.h b/include/asm-s390/setup.h
index 0d51c484c2ea..348a88137445 100644
--- a/include/asm-s390/setup.h
+++ b/include/asm-s390/setup.h
@@ -8,11 +8,14 @@
 #ifndef _ASM_S390_SETUP_H
 #define _ASM_S390_SETUP_H
+#include <asm/types.h>
 #define PARMAREA                0x10400
 #define COMMAND_LINE_SIZE       896
 #define RAMDISK_ORIGIN          0x800000
 #define RAMDISK_SIZE            0x800000
 #define MEMORY_CHUNKS           16      /* max 0x7fff */
+#define IPL_PARMBLOCK_ORIGIN    0x2000
 #ifndef __ASSEMBLY__
@@ -64,6 +67,53 @@ extern unsigned int console_irq;
 #define SET_CONSOLE_3215        do { console_mode = 2; } while (0)
 #define SET_CONSOLE_3270        do { console_mode = 3; } while (0)
+struct ipl_list_header {
+        u32 length;
+        u8  reserved[3];
+        u8  version;
+} __attribute__((packed));
+struct ipl_block_fcp {
+        u32 length;
+        u8  pbt;
+        u8  reserved1[322-1];
+        u16 devno;
+        u8  reserved2[4];
+        u64 wwpn;
+        u64 lun;
+        u32 bootprog;
+        u8  reserved3[12];
+        u64 br_lba;
+        u32 scp_data_len;
+        u8  reserved4[260];
+        u8  scp_data[];
+} __attribute__((packed));
+struct ipl_parameter_block {
+        union {
+                u32 length;
+                struct ipl_list_header header;
+        } hdr;
+        struct ipl_block_fcp fcp;
+} __attribute__((packed));
+#define IPL_MAX_SUPPORTED_VERSION (0)
+#define IPL_TYPE_FCP (0)
+/*
+ * IPL validity flags and parameters as detected in head.S
+ */
+extern u32 ipl_parameter_flags;
+extern u16 ipl_devno;
+#define IPL_DEVNO_VALID         (ipl_parameter_flags & 1)
+#define IPL_PARMBLOCK_VALID     (ipl_parameter_flags & 2)
+#define IPL_PARMBLOCK_START     ((struct ipl_parameter_block *) \
+                                 IPL_PARMBLOCK_ORIGIN)
+#define IPL_PARMBLOCK_SIZE      (IPL_PARMBLOCK_START->hdr.length)
 #else 
 #ifndef __s390x__
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index 221e965da924..f97d92691f17 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -590,7 +590,6 @@ asmlinkage long sys_clone(struct pt_regs regs);
 asmlinkage long sys_fork(struct pt_regs regs);
 asmlinkage long sys_vfork(struct pt_regs regs);
 asmlinkage long sys_pipe(unsigned long __user *fildes);
-asmlinkage long sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 0f4bcaae61bd..aef8ae43de13 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -224,8 +224,6 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 { set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
 #define pmd_page_kernel(pmd) \
 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
index 1be4337f5259..0262d3d1e5e0 100644
--- a/include/asm-sh/rwsem.h
+++ b/include/asm-sh/rwsem.h
@@ -166,5 +166,10 @@ static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
        return atomic_add_return(delta, (atomic_t *)(&sem->count));
 }
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
 #endif /* __KERNEL__ */
 #endif /* _ASM_SH_RWSEM_H */
diff --git a/include/asm-sh/semaphore.h b/include/asm-sh/semaphore.h
index b923a77a8a7e..489f7847c5d9 100644
--- a/include/asm-sh/semaphore.h
+++ b/include/asm-sh/semaphore.h
@@ -33,9 +33,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index ea89e8f223ea..f2c8e14d1fd9 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -503,7 +503,6 @@ asmlinkage int sys_vfork(unsigned long r4, unsigned long r5,
 asmlinkage int sys_pipe(unsigned long r4, unsigned long r5,
                        unsigned long r6, unsigned long r7,
                        struct pt_regs regs);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char *buf,
                                size_t count, long dummy, loff_t pos);
 asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char *buf,
diff --git a/include/asm-sh64/pgtable.h b/include/asm-sh64/pgtable.h
index 51db4307bfaf..51b05818e4eb 100644
--- a/include/asm-sh64/pgtable.h
+++ b/include/asm-sh64/pgtable.h
@@ -457,9 +457,6 @@ extern inline pte_t pte_mkhuge(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _
 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 { set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
-#define page_pte_prot(page, prot) mk_pte(page, prot)
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
 typedef pte_t *pte_addr_t;
 #define pgtable_cache_init()    do { } while (0)
diff --git a/include/asm-sh64/semaphore.h b/include/asm-sh64/semaphore.h
index fce22bb9a546..469526459149 100644
--- a/include/asm-sh64/semaphore.h
+++ b/include/asm-sh64/semaphore.h
@@ -40,9 +40,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-sparc/floppy.h b/include/asm-sparc/floppy.h
index caf926116506..7a941b800b6b 100644
--- a/include/asm-sparc/floppy.h
+++ b/include/asm-sparc/floppy.h
@@ -17,10 +17,8 @@
 /* We don't need no stinkin' I/O port allocation crap. */
 #undef release_region
-#undef check_region
 #undef request_region
 #define release_region(X, Y)    do { } while(0)
-#define check_region(X, Y)      (0)
 #define request_region(X, Y, Z) (1)
 /* References:
diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h
index a14e98677500..b33c35411e82 100644
--- a/include/asm-sparc/pgtable.h
+++ b/include/asm-sparc/pgtable.h
@@ -255,8 +255,6 @@ BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t)
 #define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte)
 #define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte)
-#define page_pte_prot(page, prot)       mk_pte(page, prot)
-#define page_pte(page)                  mk_pte(page, __pgprot(0))
 #define pfn_pte(pfn, prot)              mk_pte(pfn_to_page(pfn), prot)
 BTFIXUPDEF_CALL(unsigned long,   pte_pfn, pte_t)
diff --git a/include/asm-sparc/semaphore.h b/include/asm-sparc/semaphore.h
index 60ac5fd9eb48..f74ba31e265b 100644
--- a/include/asm-sparc/semaphore.h
+++ b/include/asm-sparc/semaphore.h
@@ -22,9 +22,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
index 8c6dfc6c7af6..9a02879b235d 100644
--- a/include/asm-sparc64/pgtable.h
+++ b/include/asm-sparc64/pgtable.h
@@ -231,9 +231,6 @@ extern struct page *mem_map_zero;
 #define pte_pfn(x)              ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT)
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
-#define page_pte_prot(page, prot)       mk_pte(page, prot)
-#define page_pte(page)                  page_pte_prot(page, __pgprot(0))
 static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
 {
        pte_t __pte;
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
index 4568ee4022df..cef5e8270421 100644
--- a/include/asm-sparc64/rwsem.h
+++ b/include/asm-sparc64/rwsem.h
@@ -56,6 +56,11 @@ static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
        atomic_add(delta, (atomic_t *)(&sem->count));
 }
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
 #endif /* __KERNEL__ */
 #endif /* _SPARC64_RWSEM_H */
diff --git a/include/asm-sparc64/semaphore.h b/include/asm-sparc64/semaphore.h
index 7419dd88b49e..093dcc6788db 100644
--- a/include/asm-sparc64/semaphore.h
+++ b/include/asm-sparc64/semaphore.h
@@ -22,9 +22,6 @@ struct semaphore {
        { ATOMIC_INIT(count), \
          __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name, 1)
 #define __DECLARE_SEMAPHORE_GENERIC(name, count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-sparc64/tlb.h b/include/asm-sparc64/tlb.h
index 9baf57db01d2..66138d959df5 100644
--- a/include/asm-sparc64/tlb.h
+++ b/include/asm-sparc64/tlb.h
@@ -25,9 +25,8 @@ struct mmu_gather {
        struct mm_struct *mm;
        unsigned int pages_nr;
        unsigned int need_flush;
-        unsigned int tlb_frozen;
+        unsigned int fullmm;
        unsigned int tlb_nr;
-        unsigned long freed;
        unsigned long vaddrs[TLB_BATCH_NR];
        struct page *pages[FREE_PTE_NR];
 };
@@ -44,14 +43,13 @@ extern void flush_tlb_pending(void);
 static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
+        struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
        BUG_ON(mp->tlb_nr);
        mp->mm = mm;
        mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
-        mp->tlb_frozen = full_mm_flush;
+        mp->fullmm = full_mm_flush;
-        mp->freed = 0;
        return mp;
 }
@@ -78,30 +76,19 @@ extern void smp_flush_tlb_mm(struct mm_struct *mm);
 static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
 {
-        unsigned long freed = mp->freed;
-        struct mm_struct *mm = mp->mm;
-        unsigned long rss = get_mm_counter(mm, rss);
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
        tlb_flush_mmu(mp);
-        if (mp->tlb_frozen) {
+        if (mp->fullmm) {
-                if (CTX_VALID(mm->context))
+                if (CTX_VALID(mp->mm->context))
-                        do_flush_tlb_mm(mm);
+                        do_flush_tlb_mm(mp->mm);
-                mp->tlb_frozen = 0;
+                mp->fullmm = 0;
        } else
                flush_tlb_pending();
        /* keep the page table cache within bounds */
        check_pgt_cache();
-}
-static inline unsigned int tlb_is_full_mm(struct mmu_gather *mp)
+        put_cpu_var(mmu_gathers);
-{
-        return mp->tlb_frozen;
 }
 static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
diff --git a/include/asm-um/cache.h b/include/asm-um/cache.h
index 4b134fe8504e..a10602a5b2d6 100644
--- a/include/asm-um/cache.h
+++ b/include/asm-um/cache.h
@@ -1,10 +1,21 @@
 #ifndef __UM_CACHE_H
 #define __UM_CACHE_H
-/* These are x86 numbers */
+#include <linux/config.h>
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define L1_CACHE_SHIFT_MAX 7    /* largest L1 which this arch supports */
+#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
+# define L1_CACHE_SHIFT         (CONFIG_X86_L1_CACHE_SHIFT)
+#elif defined(CONFIG_UML_X86) /* 64-bit */
+# define L1_CACHE_SHIFT         6 /* Should be 7 on Intel */
+#else
+/* XXX: this was taken from x86, now it's completely random. Luckily only
+ * affects SMP padding. */
+# define L1_CACHE_SHIFT         5
+#endif
+/* XXX: this is valid for x86 and x86_64. */
+#define L1_CACHE_SHIFT_MAX      7       /* largest L1 which this arch supports */
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 #endif
diff --git a/include/asm-um/linkage.h b/include/asm-um/linkage.h
index 7dfce37adc8b..e3d62dcbd356 100644
--- a/include/asm-um/linkage.h
+++ b/include/asm-um/linkage.h
@@ -3,4 +3,12 @@
 #include "asm/arch/linkage.h"
+#include <linux/config.h>
+/* <linux/linkage.h> will pick sane defaults */
+#ifdef CONFIG_GPROF
+#undef FASTCALL
+#undef fastcall
+#endif
 #endif
diff --git a/include/asm-um/pgtable.h b/include/asm-um/pgtable.h
index 616d02b57ea9..ac64eb955868 100644
--- a/include/asm-um/pgtable.h
+++ b/include/asm-um/pgtable.h
@@ -138,7 +138,7 @@ extern unsigned long pg0[1024];
 #define pte_clear(mm,addr,xp) pte_set_val(*(xp), (phys_t) 0, __pgprot(_PAGE_NEWPAGE))
-#define pmd_none(x)     (!(pmd_val(x) & ~_PAGE_NEWPAGE))
+#define pmd_none(x)     (!((unsigned long)pmd_val(x) & ~_PAGE_NEWPAGE))
 #define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
 #define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
 #define pmd_clear(xp)   do { pmd_val(*(xp)) = _PAGE_NEWPAGE; } while (0)
diff --git a/include/asm-v850/semaphore.h b/include/asm-v850/semaphore.h
index c514062bb69e..df6cdecf6c1f 100644
--- a/include/asm-v850/semaphore.h
+++ b/include/asm-v850/semaphore.h
@@ -18,9 +18,6 @@ struct semaphore {
        { ATOMIC_INIT (count), 0,                                             \
          __WAIT_QUEUE_HEAD_INITIALIZER ((name).wait) }
-#define __MUTEX_INITIALIZER(name)                                             \
-        __SEMAPHORE_INITIALIZER (name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER (name,count)
diff --git a/include/asm-v850/unistd.h b/include/asm-v850/unistd.h
index 3b552096c0e8..5a86f8e976ec 100644
--- a/include/asm-v850/unistd.h
+++ b/include/asm-v850/unistd.h
@@ -452,7 +452,6 @@ unsigned long sys_mmap2(unsigned long addr, size_t len,
 struct pt_regs;
 int sys_execve (char *name, char **argv, char **envp, struct pt_regs *regs);
 int sys_pipe (int *fildes);
-int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,
diff --git a/include/asm-x86_64/dma-mapping.h b/include/asm-x86_64/dma-mapping.h
index 54a380efed41..36d16dfbac88 100644
--- a/include/asm-x86_64/dma-mapping.h
+++ b/include/asm-x86_64/dma-mapping.h
@@ -85,10 +85,33 @@ static inline void dma_sync_single_for_device(struct device *hwdev,
        flush_write_buffers();
 }
-#define dma_sync_single_range_for_cpu(dev, dma_handle, offset, size, dir)       \
+static inline void dma_sync_single_range_for_cpu(struct device *hwdev,
-        dma_sync_single_for_cpu(dev, dma_handle, size, dir)
+                                                 dma_addr_t dma_handle,
-#define dma_sync_single_range_for_device(dev, dma_handle, offset, size, dir)    \
+                                                 unsigned long offset,
-        dma_sync_single_for_device(dev, dma_handle, size, dir)
+                                                 size_t size, int direction)
+{
+        if (direction == DMA_NONE)
+                out_of_line_bug();
+        if (swiotlb)
+                return swiotlb_sync_single_range_for_cpu(hwdev,dma_handle,offset,size,direction);
+        flush_write_buffers();
+}
+static inline void dma_sync_single_range_for_device(struct device *hwdev,
+                                                    dma_addr_t dma_handle,
+                                                    unsigned long offset,
+                                                    size_t size, int direction)
+{
+        if (direction == DMA_NONE)
+                out_of_line_bug();
+        if (swiotlb)
+                return swiotlb_sync_single_range_for_device(hwdev,dma_handle,offset,size,direction);
+        flush_write_buffers();
+}
 static inline void dma_sync_sg_for_cpu(struct device *hwdev,
                                       struct scatterlist *sg,
diff --git a/include/asm-x86_64/mtrr.h b/include/asm-x86_64/mtrr.h
index c5959d6418bb..66ac1c0f27e1 100644
--- a/include/asm-x86_64/mtrr.h
+++ b/include/asm-x86_64/mtrr.h
@@ -25,6 +25,7 @@
 #include <linux/config.h>
 #include <linux/ioctl.h>
+#include <linux/compat.h>
 #define MTRR_IOCTL_BASE 'M'
@@ -105,4 +106,36 @@ static __inline__ int mtrr_del_page (int reg, unsigned long base,
 #endif
+#ifdef CONFIG_COMPAT
+struct mtrr_sentry32
+{
+    compat_ulong_t base;    /*  Base address     */
+    compat_uint_t size;    /*  Size of region   */
+    compat_uint_t type;     /*  Type of region   */
+};
+struct mtrr_gentry32
+{
+    compat_ulong_t regnum;   /*  Register number  */
+    compat_uint_t base;    /*  Base address     */
+    compat_uint_t size;    /*  Size of region   */
+    compat_uint_t type;     /*  Type of region   */
+};
+#define MTRR_IOCTL_BASE 'M'
+#define MTRRIOC32_ADD_ENTRY        _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry32)
+#define MTRRIOC32_SET_ENTRY        _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry32)
+#define MTRRIOC32_DEL_ENTRY        _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry32)
+#define MTRRIOC32_GET_ENTRY        _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry32)
+#define MTRRIOC32_KILL_ENTRY       _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry32)
+#define MTRRIOC32_ADD_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry32)
+#define MTRRIOC32_SET_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry32)
+#define MTRRIOC32_DEL_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry32)
+#define MTRRIOC32_GET_PAGE_ENTRY   _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry32)
+#define MTRRIOC32_KILL_PAGE_ENTRY  _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry32)
+#endif /* CONFIG_COMPAT */
 #endif  /*  _LINUX_MTRR_H  */
diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h
index dd8711ecaf2f..7a07196a7202 100644
--- a/include/asm-x86_64/pgtable.h
+++ b/include/asm-x86_64/pgtable.h
@@ -318,8 +318,6 @@ static inline int pmd_large(pmd_t pte) {
 * and a page entry and page directory to the page they refer to.
 */
-#define page_pte(page) page_pte_prot(page, __pgprot(0))
 /*
 * Level 4 access.
 */
diff --git a/include/asm-x86_64/rwsem.h b/include/asm-x86_64/rwsem.h
index c002175b6e82..46077e9c1910 100644
--- a/include/asm-x86_64/rwsem.h
+++ b/include/asm-x86_64/rwsem.h
@@ -274,5 +274,10 @@ LOCK_PREFIX	"xaddl %0,(%2)"
        return tmp+delta;
 }
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
 #endif /* __KERNEL__ */
 #endif /* _X8664_RWSEM_H */
diff --git a/include/asm-x86_64/semaphore.h b/include/asm-x86_64/semaphore.h
index f325e39bf3b9..a389aa6fe80f 100644
--- a/include/asm-x86_64/semaphore.h
+++ b/include/asm-x86_64/semaphore.h
@@ -56,9 +56,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name) \
-        __SEMAPHORE_INITIALIZER(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/asm-x86_64/swiotlb.h b/include/asm-x86_64/swiotlb.h
index 7cbfd10ecc3c..dddf1b218681 100644
--- a/include/asm-x86_64/swiotlb.h
+++ b/include/asm-x86_64/swiotlb.h
@@ -15,6 +15,14 @@ extern void swiotlb_sync_single_for_cpu(struct device *hwdev,
 extern void swiotlb_sync_single_for_device(struct device *hwdev,
                                            dma_addr_t dev_addr,
                                            size_t size, int dir);
+extern void swiotlb_sync_single_range_for_cpu(struct device *hwdev,
+                                              dma_addr_t dev_addr,
+                                              unsigned long offset,
+                                              size_t size, int dir);
+extern void swiotlb_sync_single_range_for_device(struct device *hwdev,
+                                                 dma_addr_t dev_addr,
+                                                 unsigned long offset,
+                                                 size_t size, int dir);
 extern void swiotlb_sync_sg_for_cpu(struct device *hwdev,
                                     struct scatterlist *sg, int nelems,
                                     int dir);
diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h
index 11ba931cf82f..3c494b65d33a 100644
--- a/include/asm-x86_64/unistd.h
+++ b/include/asm-x86_64/unistd.h
@@ -780,8 +780,6 @@ asmlinkage long sys_pipe(int *fildes);
 #include <linux/types.h>
 #include <asm/ptrace.h>
-asmlinkage long sys_ptrace(long request, long pid,
-                                unsigned long addr, long data);
 asmlinkage long sys_iopl(unsigned int level, struct pt_regs *regs);
 asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on);
 struct sigaction;
diff --git a/include/asm-xtensa/semaphore.h b/include/asm-xtensa/semaphore.h
index 09e89ab3eb61..2a10e193b929 100644
--- a/include/asm-xtensa/semaphore.h
+++ b/include/asm-xtensa/semaphore.h
@@ -29,9 +29,6 @@ struct semaphore {
        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
 }
-#define __MUTEX_INITIALIZER(name)                                       \
-        __SEMAPHORE_INITIALIZER(name, 1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count)                         \
        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
diff --git a/include/keys/user-type.h b/include/keys/user-type.h
new file mode 100644
index 000000000000..26f6ec38577a
--- /dev/null
+++ b/include/keys/user-type.h
@@ -0,0 +1,47 @@
+/* user-type.h: User-defined key type
+ *
+ * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _KEYS_USER_TYPE_H
+#define _KEYS_USER_TYPE_H
+#include <linux/key.h>
+#include <linux/rcupdate.h>
+/*****************************************************************************/
+/*
+ * the payload for a key of type "user"
+ * - once filled in and attached to a key:
+ *   - the payload struct is invariant may not be changed, only replaced
+ *   - the payload must be read with RCU procedures or with the key semaphore
+ *     held
+ *   - the payload may only be replaced with the key semaphore write-locked
+ * - the key's data length is the size of the actual data, not including the
+ *   payload wrapper
+ */
+struct user_key_payload {
+        struct rcu_head rcu;            /* RCU destructor */
+        unsigned short  datalen;        /* length of this data */
+        char            data[0];        /* actual data */
+};
+extern struct key_type key_type_user;
+extern int user_instantiate(struct key *key, const void *data, size_t datalen);
+extern int user_duplicate(struct key *key, const struct key *source);
+extern int user_update(struct key *key, const void *data, size_t datalen);
+extern int user_match(const struct key *key, const void *criterion);
+extern void user_destroy(struct key *key);
+extern void user_describe(const struct key *user, struct seq_file *m);
+extern long user_read(const struct key *key,
+                      char __user *buffer, size_t buflen);
+#endif /* _KEYS_USER_TYPE_H */
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index 86dd5502b05c..7d8ff97b3e92 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -40,6 +40,8 @@
 * bitmap_weight(src, nbits)                    Hamming Weight: number set bits
 * bitmap_shift_right(dst, src, n, nbits)       *dst = *src >> n
 * bitmap_shift_left(dst, src, n, nbits)        *dst = *src << n
+ * bitmap_remap(dst, src, old, new, nbits)      *dst = map(old, new)(src)
+ * bitmap_bitremap(oldbit, old, new, nbits)     newbit = map(old, new)(oldbit)
 * bitmap_scnprintf(buf, len, src, nbits)       Print bitmap src to buf
 * bitmap_parse(ubuf, ulen, dst, nbits)         Parse bitmap dst from user buf
 * bitmap_scnlistprintf(buf, len, src, nbits)   Print bitmap src as list to buf
@@ -104,6 +106,10 @@ extern int bitmap_scnlistprintf(char *buf, unsigned int len,
                        const unsigned long *src, int nbits);
 extern int bitmap_parselist(const char *buf, unsigned long *maskp,
                        int nmaskbits);
+extern void bitmap_remap(unsigned long *dst, const unsigned long *src,
+                const unsigned long *old, const unsigned long *new, int bits);
+extern int bitmap_bitremap(int oldbit,
+                const unsigned long *old, const unsigned long *new, int bits);
 extern int bitmap_find_free_region(unsigned long *bitmap, int bits, int order);
 extern void bitmap_release_region(unsigned long *bitmap, int pos, int order);
 extern int bitmap_allocate_region(unsigned long *bitmap, int pos, int order);
diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h
index 88af42f5e04a..1db061bb6b08 100644
--- a/include/linux/buffer_head.h
+++ b/include/linux/buffer_head.h
@@ -126,8 +126,8 @@ BUFFER_FNS(Eopnotsupp, eopnotsupp)
 /* If we *know* page->private refers to buffer_heads */
 #define page_buffers(page)                                      \
        ({                                                      \
-                BUG_ON(!PagePrivate(page));             \
+                BUG_ON(!PagePrivate(page));                     \
-                ((struct buffer_head *)(page)->private);        \
+                ((struct buffer_head *)page_private(page));     \
        })
 #define page_has_buffers(page)  PagePrivate(page)
@@ -190,6 +190,7 @@ extern int buffer_heads_over_limit;
 */
 int try_to_release_page(struct page * page, gfp_t gfp_mask);
 int block_invalidatepage(struct page *page, unsigned long offset);
+int do_invalidatepage(struct page *page, unsigned long offset);
 int block_write_full_page(struct page *page, get_block_t *get_block,
                                struct writeback_control *wbc);
 int block_read_full_page(struct page*, get_block_t*);
@@ -219,7 +220,7 @@ static inline void attach_page_buffers(struct page *page,
 {
        page_cache_get(page);
        SetPagePrivate(page);
-        page->private = (unsigned long)head;
+        set_page_private(page, (unsigned long)head);
 }
 static inline void get_bh(struct buffer_head *bh)
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 86980c68234a..1f7b2c097503 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -32,6 +32,7 @@ struct cpu {
 };
 extern int register_cpu(struct cpu *, int, struct node *);
+extern struct sys_device *get_cpu_sysdev(int cpu);
 #ifdef CONFIG_HOTPLUG_CPU
 extern void unregister_cpu(struct cpu *, struct node *);
 #endif
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index ff7f80f48df1..d068176b7ad7 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -23,6 +23,7 @@
 #include <linux/completion.h>
 #include <linux/workqueue.h>
 #include <linux/cpumask.h>
+#include <asm/div64.h>
 #define CPUFREQ_NAME_LEN 16
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 9bdba8169b41..13e9f4a3ab26 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -12,6 +12,8 @@
 * see bitmap_scnprintf() and bitmap_parse() in lib/bitmap.c.
 * For details of cpulist_scnprintf() and cpulist_parse(), see
 * bitmap_scnlistprintf() and bitmap_parselist(), also in bitmap.c.
+ * For details of cpu_remap(), see bitmap_bitremap in lib/bitmap.c
+ * For details of cpus_remap(), see bitmap_remap in lib/bitmap.c.
 *
 * The available cpumask operations are:
 *
@@ -50,6 +52,8 @@
 * int cpumask_parse(ubuf, ulen, mask)  Parse ascii string as cpumask
 * int cpulist_scnprintf(buf, len, mask) Format cpumask as list for printing
 * int cpulist_parse(buf, map)          Parse ascii string as cpulist
+ * int cpu_remap(oldbit, old, new)      newbit = map(old, new)(oldbit)
+ * int cpus_remap(dst, src, old, new)   *dst = map(old, new)(src)
 *
 * for_each_cpu_mask(cpu, mask)         for-loop cpu over mask
 *
@@ -294,6 +298,22 @@ static inline int __cpulist_parse(const char *buf, cpumask_t *dstp, int nbits)
        return bitmap_parselist(buf, dstp->bits, nbits);
 }
+#define cpu_remap(oldbit, old, new) \
+                __cpu_remap((oldbit), &(old), &(new), NR_CPUS)
+static inline int __cpu_remap(int oldbit,
+                const cpumask_t *oldp, const cpumask_t *newp, int nbits)
+{
+        return bitmap_bitremap(oldbit, oldp->bits, newp->bits, nbits);
+}
+#define cpus_remap(dst, src, old, new) \
+                __cpus_remap(&(dst), &(src), &(old), &(new), NR_CPUS)
+static inline void __cpus_remap(cpumask_t *dstp, const cpumask_t *srcp,
+                const cpumask_t *oldp, const cpumask_t *newp, int nbits)
+{
+        bitmap_remap(dstp->bits, srcp->bits, oldp->bits, newp->bits, nbits);
+}
 #if NR_CPUS > 1
 #define for_each_cpu_mask(cpu, mask)            \
        for ((cpu) = first_cpu(mask);           \
diff --git a/include/linux/device.h b/include/linux/device.h
index a9e72ac3fb9f..17cbc6db67b4 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -396,32 +396,6 @@ extern struct device * get_device(struct device * dev);
 extern void put_device(struct device * dev);
-/* drivers/base/platform.c */
-struct platform_device {
-        const char      * name;
-        u32             id;
-        struct device   dev;
-        u32             num_resources;
-        struct resource * resource;
-};
-#define to_platform_device(x) container_of((x), struct platform_device, dev)
-extern int platform_device_register(struct platform_device *);
-extern void platform_device_unregister(struct platform_device *);
-extern struct bus_type platform_bus_type;
-extern struct device platform_bus;
-extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int);
-extern int platform_get_irq(struct platform_device *, unsigned int);
-extern struct resource *platform_get_resource_byname(struct platform_device *, unsigned int, char *);
-extern int platform_get_irq_byname(struct platform_device *, char *);
-extern int platform_add_devices(struct platform_device **, int);
-extern struct platform_device *platform_device_register_simple(char *, unsigned int, struct resource *, unsigned int);
 /* drivers/base/power.c */
 extern void device_shutdown(void);
diff --git a/include/linux/dmi.h b/include/linux/dmi.h
index a415f1d93e9a..05f4132622fc 100644
--- a/include/linux/dmi.h
+++ b/include/linux/dmi.h
@@ -60,7 +60,7 @@ struct dmi_device {
        void *device_data;      /* Type specific data */
 };
-#if defined(CONFIG_X86) && !defined(CONFIG_X86_64)
+#if defined(CONFIG_X86_32)
 extern int dmi_check_system(struct dmi_system_id *list);
 extern char * dmi_get_system_info(int field);
diff --git a/include/linux/dqblk_xfs.h b/include/linux/dqblk_xfs.h
index cb31719ee192..2fda1b2aabd9 100644
--- a/include/linux/dqblk_xfs.h
+++ b/include/linux/dqblk_xfs.h
@@ -1,22 +1,18 @@
 /*
 * Copyright (c) 1995-2001,2004 Silicon Graphics, Inc.  All Rights Reserved.
 *
- * This program is free software; you can redistribute it and/or modify it
+ * This program is free software; you can redistribute it and/or
- * under the terms of version 2.1 of the GNU Lesser General Public License
+ * modify it under the terms of the GNU Lesser General Public License
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * GNU Lesser General Public License for more details.
 *
- * You should have received a copy of the GNU General Public License
+ * You should have received a copy of the GNU Lesset General Public License
- * along with this program; if not, write to the Free Software
+ * along with this program; if not, write to the Free Software Foundation,
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
+ * Inc.,  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- * USA
- *
- * Contact information: Silicon Graphics, Inc., 1500 Crittenden Lane,
- * Mountain View, CA 94043, USA, or: http://www.sgi.com
 */
 #ifndef _LINUX_DQBLK_XFS_H
 #define _LINUX_DQBLK_XFS_H
@@ -32,7 +28,8 @@
 #define XQM_USRQUOTA    0       /* system call user quota type */
 #define XQM_GRPQUOTA    1       /* system call group quota type */
-#define XQM_MAXQUOTAS   2
+#define XQM_PRJQUOTA    2       /* system call project quota type */
+#define XQM_MAXQUOTAS   3
 #define Q_XQUOTAON      XQM_CMD(1)      /* enable accounting/enforcement */
 #define Q_XQUOTAOFF     XQM_CMD(2)      /* disable accounting/enforcement */
@@ -40,6 +37,7 @@
 #define Q_XSETQLIM      XQM_CMD(4)      /* set disk limits */
 #define Q_XGETQSTAT     XQM_CMD(5)      /* get quota subsystem status */
 #define Q_XQUOTARM      XQM_CMD(6)      /* free disk space used by dquots */
+#define Q_XQUOTASYNC    XQM_CMD(7)      /* delalloc flush, updates dquots */
 /*
 * fs_disk_quota structure:
diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h
index 4522c7186bf3..5f49a30eb6f2 100644
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -48,8 +48,10 @@ static inline void eth_copy_and_sum (struct sk_buff *dest,
 }
 /**
- * is_zero_ether_addr - Determine if give Ethernet address is all
+ * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
- * zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
 */
 static inline int is_zero_ether_addr(const u8 *addr)
 {
@@ -57,9 +59,7 @@ static inline int is_zero_ether_addr(const u8 *addr)
 }
 /**
- * is_multicast_ether_addr - Determine if the given Ethernet address is a
+ * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
- * multicast address.
- *
 * @addr: Pointer to a six-byte array containing the Ethernet address
 *
 * Return true if the address is a multicast address.
@@ -69,10 +69,15 @@ static inline int is_multicast_ether_addr(const u8 *addr)
        return ((addr[0] != 0xff) && (0x01 & addr[0]));
 }
+/**
+ * is_broadcast_ether_addr - Determine if the Ethernet address is broadcast
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is the broadcast address.
+ */
 static inline int is_broadcast_ether_addr(const u8 *addr)
 {
-        return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) &&  
+        return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff;
-                (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
 }
 /**
@@ -104,6 +109,22 @@ static inline void random_ether_addr(u8 *addr)
        addr [0] &= 0xfe;       /* clear multicast bit */
        addr [0] |= 0x02;       /* set local assignment bit (IEEE802) */
 }
+/**
+ * compare_ether_addr - Compare two Ethernet addresses
+ * @addr1: Pointer to a six-byte array containing the Ethernet address
+ * @addr2: Pointer other six-byte array containing the Ethernet address
+ *
+ * Compare two ethernet addresses, returns 0 if equal
+ */
+static inline unsigned compare_ether_addr(const u8 *addr1, const u8 *addr2)
+{
+        const u16 *a = (const u16 *) addr1;
+        const u16 *b = (const u16 *) addr2;
+        BUILD_BUG_ON(ETH_ALEN != 6);
+        return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
+}
 #endif  /* __KERNEL__ */
 #endif  /* _LINUX_ETHERDEVICE_H */
diff --git a/include/linux/fs.h b/include/linux/fs.h
index f83d997c5582..6d6226732c93 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -574,7 +574,14 @@ struct file_ra_state {
 #define RA_FLAG_INCACHE 0x02    /* file is already in cache */
 struct file {
-        struct list_head        f_list;
+        /*
+         * fu_list becomes invalid after file_free is called and queued via
+         * fu_rcuhead for RCU freeing
+         */
+        union {
+                struct list_head        fu_list;
+                struct rcu_head         fu_rcuhead;
+        } f_u;
        struct dentry           *f_dentry;
        struct vfsmount         *f_vfsmnt;
        struct file_operations  *f_op;
@@ -598,7 +605,6 @@ struct file {
        spinlock_t              f_ep_lock;
 #endif /* #ifdef CONFIG_EPOLL */
        struct address_space    *f_mapping;
-        struct rcu_head         f_rcuhead;
 };
 extern spinlock_t files_lock;
 #define file_list_lock() spin_lock(&files_lock);
diff --git a/include/linux/fs_enet_pd.h b/include/linux/fs_enet_pd.h
new file mode 100644
index 000000000000..bef23bbf8690
--- /dev/null
+++ b/include/linux/fs_enet_pd.h
@@ -0,0 +1,136 @@
+/*
+ * Platform information definitions for the
+ * universal Freescale Ethernet driver.
+ *
+ * Copyright (c) 2003 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ *
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+#ifndef FS_ENET_PD_H
+#define FS_ENET_PD_H
+#include <linux/version.h>
+#include <asm/types.h>
+#define FS_ENET_NAME    "fs_enet"
+enum fs_id {
+        fsid_fec1,
+        fsid_fec2,
+        fsid_fcc1,
+        fsid_fcc2,
+        fsid_fcc3,
+        fsid_scc1,
+        fsid_scc2,
+        fsid_scc3,
+        fsid_scc4,
+};
+#define FS_MAX_INDEX    9
+static inline int fs_get_fec_index(enum fs_id id)
+{
+        if (id >= fsid_fec1 && id <= fsid_fec2)
+                return id - fsid_fec1;
+        return -1;
+}
+static inline int fs_get_fcc_index(enum fs_id id)
+{
+        if (id >= fsid_fcc1 && id <= fsid_fcc3)
+                return id - fsid_fcc1;
+        return -1;
+}
+static inline int fs_get_scc_index(enum fs_id id)
+{
+        if (id >= fsid_scc1 && id <= fsid_scc4)
+                return id - fsid_scc1;
+        return -1;
+}
+enum fs_mii_method {
+        fsmii_fixed,
+        fsmii_fec,
+        fsmii_bitbang,
+};
+enum fs_ioport {
+        fsiop_porta,
+        fsiop_portb,
+        fsiop_portc,
+        fsiop_portd,
+        fsiop_porte,
+};
+struct fs_mii_bus_info {
+        int method;             /* mii method                  */
+        int id;                 /* the id of the mii_bus       */
+        int disable_aneg;       /* if the controller needs to negothiate speed & duplex */
+        int lpa;                /* the default board-specific vallues will be applied otherwise */
+        union {
+                struct {
+                        int duplex;
+                        int speed;
+                } fixed;
+                struct {
+                        /* nothing */
+                } fec;
+                
+                struct {
+                        /* nothing */
+                } scc;
+                struct {
+                        int mdio_port;  /* port & bit for MDIO */
+                        int mdio_bit;
+                        int mdc_port;   /* port & bit for MDC  */
+                        int mdc_bit;
+                        int delay;      /* delay in us         */
+                } bitbang;
+        } i;
+};
+struct fs_platform_info {
+        
+        void(*init_ioports)(void);
+        /* device specific information */
+        int fs_no;              /* controller index            */
+        u32 cp_page;            /* CPM page */
+        u32 cp_block;           /* CPM sblock */
+        
+        u32 clk_trx;            /* some stuff for pins & mux configuration*/
+        u32 clk_route;
+        u32 clk_mask;
+        
+        u32 mem_offset;
+        u32 dpram_offset;
+        u32 fcc_regs_c;
+        
+        u32 device_flags;
+        int phy_addr;           /* the phy address (-1 no phy) */
+        int phy_irq;            /* the phy irq (if it exists)  */
+        const struct fs_mii_bus_info *bus_info;
+        int rx_ring, tx_ring;   /* number of buffers on rx     */
+        __u8 macaddr[6];        /* mac address                 */
+        int rx_copybreak;       /* limit we copy small frames  */
+        int use_napi;           /* use NAPI                    */
+        int napi_weight;        /* NAPI weight                 */
+        int use_rmii;           /* use RMII mode               */
+};
+#endif
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 70f54af87b9f..114d5d59f695 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -47,16 +47,21 @@
 struct gianfar_platform_data {
        /* device specific information */
        u32 device_flags;
-        u32 phy_reg_addr;
        /* board specific information */
        u32 board_flags;
-        u32 phy_flags;
+        const char *bus_id;
-        u32 phyid;
-        u32 interruptPHY;
        u8 mac_addr[6];
 };
+struct gianfar_mdio_data {
+        /* device specific information */
+        u32 paddr;
+        /* board specific information */
+        int irq[32];
+};
 /* Flags related to gianfar device features */
 #define FSL_GIANFAR_DEV_HAS_GIGABIT             0x00000001
 #define FSL_GIANFAR_DEV_HAS_COALESCE            0x00000002
diff --git a/include/linux/fuse.h b/include/linux/fuse.h
index acbeb96a3353..f98854c2abd7 100644
--- a/include/linux/fuse.h
+++ b/include/linux/fuse.h
@@ -61,7 +61,6 @@ struct fuse_kstatfs {
 #define FATTR_SIZE      (1 << 3)
 #define FATTR_ATIME     (1 << 4)
 #define FATTR_MTIME     (1 << 5)
-#define FATTR_CTIME     (1 << 6)
 /**
 * Flags returned by the OPEN request
diff --git a/include/linux/gameport.h b/include/linux/gameport.h
index cd623eccdbea..2401dea2b867 100644
--- a/include/linux/gameport.h
+++ b/include/linux/gameport.h
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <linux/list.h>
 #include <linux/device.h>
+#include <linux/timer.h>
 struct gameport {
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index eabdb5cce357..8eeaa53a68c9 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -78,7 +78,7 @@ struct hd_struct {
        sector_t start_sect;
        sector_t nr_sects;
        struct kobject kobj;
-        unsigned reads, read_sectors, writes, write_sectors;
+        unsigned ios[2], sectors[2];
        int policy, partno;
 };
@@ -89,10 +89,10 @@ struct hd_struct {
 #define GENHD_FL_SUPPRESS_PARTITION_INFO        32
 struct disk_stats {
-        unsigned read_sectors, write_sectors;
+        unsigned sectors[2];
-        unsigned reads, writes;
+        unsigned ios[2];
-        unsigned read_merges, write_merges;
+        unsigned merges[2];
-        unsigned read_ticks, write_ticks;
+        unsigned ticks[2];
        unsigned io_ticks;
        unsigned time_in_queue;
 };
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index d664330d900e..0cea162b08c0 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -16,7 +16,6 @@ static inline int is_vm_hugetlb_page(struct vm_area_struct *vma)
 int hugetlb_sysctl_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *);
 int copy_hugetlb_page_range(struct mm_struct *, struct mm_struct *, struct vm_area_struct *);
 int follow_hugetlb_page(struct mm_struct *, struct vm_area_struct *, struct page **, struct vm_area_struct **, unsigned long *, int *, int);
-void zap_hugepage_range(struct vm_area_struct *, unsigned long, unsigned long);
 void unmap_hugepage_range(struct vm_area_struct *, unsigned long, unsigned long);
 int hugetlb_prefault(struct address_space *, struct vm_area_struct *);
 int hugetlb_report_meminfo(char *);
@@ -87,7 +86,6 @@ static inline unsigned long hugetlb_total_pages(void)
 #define follow_huge_addr(mm, addr, write)       ERR_PTR(-EINVAL)
 #define copy_hugetlb_page_range(src, dst, vma)  ({ BUG(); 0; })
 #define hugetlb_prefault(mapping, vma)          ({ BUG(); 0; })
-#define zap_hugepage_range(vma, start, len)     BUG()
 #define unmap_hugepage_range(vma, start, end)   BUG()
 #define is_hugepage_mem_enough(size)            0
 #define hugetlb_report_meminfo(buf)             0
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index f88577ca3b3a..5e19a7ba69b2 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -31,6 +31,7 @@
 #include <linux/i2c-id.h>
 #include <linux/mod_devicetable.h>
 #include <linux/device.h>       /* for struct device */
+#include <linux/sched.h>        /* for completion */
 #include <asm/semaphore.h>
 /* --- For i2c-isa ---------------------------------------------------- */
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index 92300325dbcd..d79c8a4bc4f8 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -25,10 +25,14 @@
 /* How many different OSM's are we allowing */
 #define I2O_MAX_DRIVERS         8
-#include <asm/io.h>
-#include <asm/semaphore.h>      /* Needed for MUTEX init macros */
 #include <linux/pci.h>
 #include <linux/dma-mapping.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>    /* work_struct */
+#include <asm/io.h>
+#include <asm/semaphore.h>      /* Needed for MUTEX init macros */
 /* message queue empty */
 #define I2O_QUEUE_EMPTY         0xffffffff
diff --git a/include/linux/ide.h b/include/linux/ide.h
index a6dbb51ecd7b..3461abc1e854 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -218,7 +218,7 @@ typedef enum {	ide_unknown,	ide_generic,	ide_pci,
                ide_rz1000,     ide_trm290,
                ide_cmd646,     ide_cy82c693,   ide_4drives,
                ide_pmac,       ide_etrax100,   ide_acorn,
-                ide_forced
+                ide_au1xxx, ide_forced
 } hwif_chipset_t;
 /*
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 4367ce4db52a..f1925ccc9fe1 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -307,7 +307,7 @@ struct sysinfo {
        char _f[20-2*sizeof(long)-sizeof(int)]; /* Padding: libc5 uses this.. */
 };
-/* Force a compilation error if condition is false */
+/* Force a compilation error if condition is true */
 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
 #ifdef CONFIG_SYSCTL
diff --git a/include/linux/key-ui.h b/include/linux/key-ui.h
index 7a2e332067c3..e8b8a7a5c496 100644
--- a/include/linux/key-ui.h
+++ b/include/linux/key-ui.h
@@ -24,7 +24,8 @@ extern spinlock_t key_serial_lock;
 #define KEY_WRITE       0x04    /* require permission to update / modify */
 #define KEY_SEARCH      0x08    /* require permission to search (keyring) or find (key) */
 #define KEY_LINK        0x10    /* require permission to link */
-#define KEY_ALL         0x1f    /* all the above permissions */
+#define KEY_SETATTR     0x20    /* require permission to change attributes */
+#define KEY_ALL         0x3f    /* all the above permissions */
 /*
 * the keyring payload contains a list of the keys to which the keyring is
diff --git a/include/linux/key.h b/include/linux/key.h
index f1efa016dbf3..53513a3be53b 100644
--- a/include/linux/key.h
+++ b/include/linux/key.h
@@ -40,28 +40,32 @@ struct key;
 #define KEY_POS_WRITE   0x04000000      /* possessor can update key payload / add link to keyring */
 #define KEY_POS_SEARCH  0x08000000      /* possessor can find a key in search / search a keyring */
 #define KEY_POS_LINK    0x10000000      /* possessor can create a link to a key/keyring */
-#define KEY_POS_ALL     0x1f000000
+#define KEY_POS_SETATTR 0x20000000      /* possessor can set key attributes */
+#define KEY_POS_ALL     0x3f000000
 #define KEY_USR_VIEW    0x00010000      /* user permissions... */
 #define KEY_USR_READ    0x00020000
 #define KEY_USR_WRITE   0x00040000
 #define KEY_USR_SEARCH  0x00080000
 #define KEY_USR_LINK    0x00100000
-#define KEY_USR_ALL     0x001f0000
+#define KEY_USR_SETATTR 0x00200000
+#define KEY_USR_ALL     0x003f0000
 #define KEY_GRP_VIEW    0x00000100      /* group permissions... */
 #define KEY_GRP_READ    0x00000200
 #define KEY_GRP_WRITE   0x00000400
 #define KEY_GRP_SEARCH  0x00000800
 #define KEY_GRP_LINK    0x00001000
-#define KEY_GRP_ALL     0x00001f00
+#define KEY_GRP_SETATTR 0x00002000
+#define KEY_GRP_ALL     0x00003f00
 #define KEY_OTH_VIEW    0x00000001      /* third party permissions... */
 #define KEY_OTH_READ    0x00000002
 #define KEY_OTH_WRITE   0x00000004
 #define KEY_OTH_SEARCH  0x00000008
 #define KEY_OTH_LINK    0x00000010
-#define KEY_OTH_ALL     0x0000001f
+#define KEY_OTH_SETATTR 0x00000020
+#define KEY_OTH_ALL     0x0000003f
 struct seq_file;
 struct user_struct;
@@ -119,6 +123,7 @@ struct key {
        struct key_type         *type;          /* type of key */
        struct rw_semaphore     sem;            /* change vs change sem */
        struct key_user         *user;          /* owner of this key */
+        void                    *security;      /* security data for this key */
        time_t                  expiry;         /* time at which key expires (or 0) */
        uid_t                   uid;
        gid_t                   gid;
diff --git a/include/linux/kobj_map.h b/include/linux/kobj_map.h
index b6cc10bf8dfc..cbe7d8008042 100644
--- a/include/linux/kobj_map.h
+++ b/include/linux/kobj_map.h
@@ -1,5 +1,7 @@
 #ifdef __KERNEL__
+#include <asm/semaphore.h>
 typedef struct kobject *kobj_probe_t(dev_t, int *, void *);
 struct kobj_map;
diff --git a/include/linux/kthread.h b/include/linux/kthread.h
index 3fa786448db3..ebdd41fd1082 100644
--- a/include/linux/kthread.h
+++ b/include/linux/kthread.h
@@ -70,6 +70,18 @@ void kthread_bind(struct task_struct *k, unsigned int cpu);
 int kthread_stop(struct task_struct *k);
 /**
+ * kthread_stop_sem: stop a thread created by kthread_create().
+ * @k: thread created by kthread_create().
+ * @s: semaphore that @k waits on while idle.
+ *
+ * Does essentially the same thing as kthread_stop() above, but wakes
+ * @k by calling up(@s).
+ *
+ * Returns the result of threadfn(), or -EINTR if wake_up_process()
+ * was never called. */
+int kthread_stop_sem(struct task_struct *k, struct semaphore *s);
+/**
 * kthread_should_stop: should this kthread return now?
 *
 * When someone calls kthread_stop on your kthread, it will be woken
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 00a8a5738858..0ba3af7a1236 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -172,6 +172,13 @@ enum hsm_task_states {
        HSM_ST_ERR,
 };
+enum ata_completion_errors {
+        AC_ERR_OTHER            = (1 << 0),
+        AC_ERR_DEV              = (1 << 1),
+        AC_ERR_ATA_BUS          = (1 << 2),
+        AC_ERR_HOST_BUS         = (1 << 3),
+};
 /* forward declarations */
 struct scsi_device;
 struct ata_port_operations;
@@ -179,7 +186,7 @@ struct ata_port;
 struct ata_queued_cmd;
 /* typedefs */
-typedef int (*ata_qc_cb_t) (struct ata_queued_cmd *qc, u8 drv_stat);
+typedef int (*ata_qc_cb_t) (struct ata_queued_cmd *qc, unsigned int err_mask);
 struct ata_ioports {
        unsigned long           cmd_addr;
@@ -347,7 +354,6 @@ struct ata_port_operations {
        void (*exec_command)(struct ata_port *ap, const struct ata_taskfile *tf);
        u8   (*check_status)(struct ata_port *ap);
        u8   (*check_altstatus)(struct ata_port *ap);
-        u8   (*check_err)(struct ata_port *ap);
        void (*dev_select)(struct ata_port *ap, unsigned int device);
        void (*phy_reset) (struct ata_port *ap);
@@ -434,7 +440,6 @@ extern void ata_noop_dev_select (struct ata_port *ap, unsigned int device);
 extern void ata_std_dev_select (struct ata_port *ap, unsigned int device);
 extern u8 ata_check_status(struct ata_port *ap);
 extern u8 ata_altstatus(struct ata_port *ap);
-extern u8 ata_chk_err(struct ata_port *ap);
 extern void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf);
 extern int ata_port_start (struct ata_port *ap);
 extern void ata_port_stop (struct ata_port *ap);
@@ -455,7 +460,7 @@ extern void ata_bmdma_start (struct ata_queued_cmd *qc);
 extern void ata_bmdma_stop(struct ata_queued_cmd *qc);
 extern u8   ata_bmdma_status(struct ata_port *ap);
 extern void ata_bmdma_irq_clear(struct ata_port *ap);
-extern void ata_qc_complete(struct ata_queued_cmd *qc, u8 drv_stat);
+extern void ata_qc_complete(struct ata_queued_cmd *qc, unsigned int err_mask);
 extern void ata_eng_timeout(struct ata_port *ap);
 extern void ata_scsi_simulate(u16 *id, struct scsi_cmnd *cmd,
                              void (*done)(struct scsi_cmnd *));
@@ -718,4 +723,21 @@ static inline int ata_try_flush_cache(const struct ata_device *dev)
               ata_id_has_flush_ext(dev->id);
 }
+static inline unsigned int ac_err_mask(u8 status)
+{
+        if (status & ATA_BUSY)
+                return AC_ERR_ATA_BUS;
+        if (status & (ATA_ERR | ATA_DF))
+                return AC_ERR_DEV;
+        return 0;
+}
+static inline unsigned int __ac_err_mask(u8 status)
+{
+        unsigned int mask = ac_err_mask(status);
+        if (mask == 0)
+                return AC_ERR_OTHER;
+        return mask;
+}
 #endif /* __LINUX_LIBATA_H__ */
diff --git a/include/linux/memory.h b/include/linux/memory.h
new file mode 100644
index 000000000000..0def328ab5cf
--- /dev/null
+++ b/include/linux/memory.h
@@ -0,0 +1,94 @@
+/*
+ * include/linux/memory.h - generic memory definition
+ *
+ * This is mainly for topological representation. We define the
+ * basic "struct memory_block" here, which can be embedded in per-arch
+ * definitions or NUMA information.
+ *
+ * Basic handling of the devices is done in drivers/base/memory.c
+ * and system devices are handled in drivers/base/sys.c.
+ *
+ * Memory block are exported via sysfs in the class/memory/devices/
+ * directory.
+ *
+ */
+#ifndef _LINUX_MEMORY_H_
+#define _LINUX_MEMORY_H_
+#include <linux/sysdev.h>
+#include <linux/node.h>
+#include <linux/compiler.h>
+#include <asm/semaphore.h>
+struct memory_block {
+        unsigned long phys_index;
+        unsigned long state;
+        /*
+         * This serializes all state change requests.  It isn't
+         * held during creation because the control files are
+         * created long after the critical areas during
+         * initialization.
+         */
+        struct semaphore state_sem;
+        int phys_device;                /* to which fru does this belong? */
+        void *hw;                       /* optional pointer to fw/hw data */
+        int (*phys_callback)(struct memory_block *);
+        struct sys_device sysdev;
+};
+/* These states are exposed to userspace as text strings in sysfs */
+#define MEM_ONLINE              (1<<0) /* exposed to userspace */
+#define MEM_GOING_OFFLINE       (1<<1) /* exposed to userspace */
+#define MEM_OFFLINE             (1<<2) /* exposed to userspace */
+/*
+ * All of these states are currently kernel-internal for notifying
+ * kernel components and architectures.
+ *
+ * For MEM_MAPPING_INVALID, all notifier chains with priority >0
+ * are called before pfn_to_page() becomes invalid.  The priority=0
+ * entry is reserved for the function that actually makes
+ * pfn_to_page() stop working.  Any notifiers that want to be called
+ * after that should have priority <0.
+ */
+#define MEM_MAPPING_INVALID     (1<<3)
+#ifndef CONFIG_MEMORY_HOTPLUG
+static inline int memory_dev_init(void)
+{
+        return 0;
+}
+static inline int register_memory_notifier(struct notifier_block *nb)
+{
+        return 0;
+}
+static inline void unregister_memory_notifier(struct notifier_block *nb)
+{
+}
+#else
+extern int register_memory(struct memory_block *, struct mem_section *section, struct node *);
+extern int register_new_memory(struct mem_section *);
+extern int unregister_memory_section(struct mem_section *);
+extern int memory_dev_init(void);
+extern int register_memory_notifier(struct notifier_block *nb);
+extern void unregister_memory_notifier(struct notifier_block *nb);
+#define CONFIG_MEM_BLOCK_SIZE   (PAGES_PER_SECTION<<PAGE_SHIFT)
+extern int invalidate_phys_mapping(unsigned long, unsigned long);
+struct notifier_block;
+extern int register_memory_notifier(struct notifier_block *nb);
+extern void unregister_memory_notifier(struct notifier_block *nb);
+extern struct sysdev_class memory_sysdev_class;
+#endif /* CONFIG_MEMORY_HOTPLUG */
+#define hotplug_memory_notifier(fn, pri) {                      \
+        static struct notifier_block fn##_mem_nb =              \
+                { .notifier_call = fn, .priority = pri };       \
+        register_memory_notifier(&fn##_mem_nb);                 \
+}
+#endif /* _LINUX_MEMORY_H_ */
diff --git a/include/linux/memory_hotplug.h b/include/linux/memory_hotplug.h
new file mode 100644
index 000000000000..01f03bc06eff
--- /dev/null
+++ b/include/linux/memory_hotplug.h
@@ -0,0 +1,104 @@
+#ifndef __LINUX_MEMORY_HOTPLUG_H
+#define __LINUX_MEMORY_HOTPLUG_H
+#include <linux/mmzone.h>
+#include <linux/spinlock.h>
+#include <linux/mmzone.h>
+#include <linux/notifier.h>
+#ifdef CONFIG_MEMORY_HOTPLUG
+/*
+ * pgdat resizing functions
+ */
+static inline
+void pgdat_resize_lock(struct pglist_data *pgdat, unsigned long *flags)
+{
+        spin_lock_irqsave(&pgdat->node_size_lock, *flags);
+}
+static inline
+void pgdat_resize_unlock(struct pglist_data *pgdat, unsigned long *flags)
+{
+        spin_unlock_irqrestore(&pgdat->node_size_lock, *flags);
+}
+static inline
+void pgdat_resize_init(struct pglist_data *pgdat)
+{
+        spin_lock_init(&pgdat->node_size_lock);
+}
+/*
+ * Zone resizing functions
+ */
+static inline unsigned zone_span_seqbegin(struct zone *zone)
+{
+        return read_seqbegin(&zone->span_seqlock);
+}
+static inline int zone_span_seqretry(struct zone *zone, unsigned iv)
+{
+        return read_seqretry(&zone->span_seqlock, iv);
+}
+static inline void zone_span_writelock(struct zone *zone)
+{
+        write_seqlock(&zone->span_seqlock);
+}
+static inline void zone_span_writeunlock(struct zone *zone)
+{
+        write_sequnlock(&zone->span_seqlock);
+}
+static inline void zone_seqlock_init(struct zone *zone)
+{
+        seqlock_init(&zone->span_seqlock);
+}
+extern int zone_grow_free_lists(struct zone *zone, unsigned long new_nr_pages);
+extern int zone_grow_waitqueues(struct zone *zone, unsigned long nr_pages);
+extern int add_one_highpage(struct page *page, int pfn, int bad_ppro);
+/* need some defines for these for archs that don't support it */
+extern void online_page(struct page *page);
+/* VM interface that may be used by firmware interface */
+extern int add_memory(u64 start, u64 size);
+extern int remove_memory(u64 start, u64 size);
+extern int online_pages(unsigned long, unsigned long);
+/* reasonably generic interface to expand the physical pages in a zone  */
+extern int __add_pages(struct zone *zone, unsigned long start_pfn,
+        unsigned long nr_pages);
+#else /* ! CONFIG_MEMORY_HOTPLUG */
+/*
+ * Stub functions for when hotplug is off
+ */
+static inline void pgdat_resize_lock(struct pglist_data *p, unsigned long *f) {}
+static inline void pgdat_resize_unlock(struct pglist_data *p, unsigned long *f) {}
+static inline void pgdat_resize_init(struct pglist_data *pgdat) {}
+static inline unsigned zone_span_seqbegin(struct zone *zone)
+{
+        return 0;
+}
+static inline int zone_span_seqretry(struct zone *zone, unsigned iv)
+{
+        return 0;
+}
+static inline void zone_span_writelock(struct zone *zone) {}
+static inline void zone_span_writeunlock(struct zone *zone) {}
+static inline void zone_seqlock_init(struct zone *zone) {}
+static inline int mhp_notimplemented(const char *func)
+{
+        printk(KERN_WARNING "%s() called, with CONFIG_MEMORY_HOTPLUG disabled\n", func);
+        dump_stack();
+        return -ENOSYS;
+}
+static inline int __add_pages(struct zone *zone, unsigned long start_pfn,
+        unsigned long nr_pages)
+{
+        return mhp_notimplemented(__FUNCTION__);
+}
+#endif /* ! CONFIG_MEMORY_HOTPLUG */
+static inline int __remove_pages(struct zone *zone, unsigned long start_pfn,
+        unsigned long nr_pages)
+{
+        printk(KERN_WARNING "%s() called, not yet supported\n", __FUNCTION__);
+        dump_stack();
+        return -ENOSYS;
+}
+#endif /* __LINUX_MEMORY_HOTPLUG_H */
diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h
index 58385ee1c0ac..8b67cf837ca9 100644
--- a/include/linux/mempolicy.h
+++ b/include/linux/mempolicy.h
@@ -27,10 +27,10 @@
 #include <linux/config.h>
 #include <linux/mmzone.h>
-#include <linux/bitmap.h>
 #include <linux/slab.h>
 #include <linux/rbtree.h>
 #include <linux/spinlock.h>
+#include <linux/nodemask.h>
 struct vm_area_struct;
@@ -47,8 +47,7 @@ struct vm_area_struct;
 * Locking policy for interlave:
 * In process context there is no locking because only the process accesses
 * its own state. All vma manipulation is somewhat protected by a down_read on
- * mmap_sem. For allocating in the interleave policy the page_table_lock
+ * mmap_sem.
- * must be also aquired to protect il_next.
 *
 * Freeing policy:
 * When policy is MPOL_BIND v.zonelist is kmalloc'ed and must be kfree'd.
@@ -63,7 +62,7 @@ struct mempolicy {
        union {
                struct zonelist  *zonelist;     /* bind */
                short            preferred_node; /* preferred */
-                DECLARE_BITMAP(nodes, MAX_NUMNODES); /* interleave */
+                nodemask_t       nodes;         /* interleave */
                /* undefined for default */
        } v;
 };
@@ -155,6 +154,7 @@ struct mempolicy *get_vma_policy(struct task_struct *task,
 extern void numa_default_policy(void);
 extern void numa_policy_init(void);
+extern void numa_policy_rebind(const nodemask_t *old, const nodemask_t *new);
 extern struct mempolicy default_policy;
 #else
@@ -227,6 +227,11 @@ static inline void numa_default_policy(void)
 {
 }
+static inline void numa_policy_rebind(const nodemask_t *old,
+                                        const nodemask_t *new)
+{
+}
 #endif /* CONFIG_NUMA */
 #endif /* __KERNEL__ */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index e1649578fb0c..5c1fb0a2e806 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -157,7 +157,7 @@ extern unsigned int kobjsize(const void *objp);
 #define VM_DONTCOPY     0x00020000      /* Do not copy this vma on fork */
 #define VM_DONTEXPAND   0x00040000      /* Cannot expand with mremap() */
-#define VM_RESERVED     0x00080000      /* Don't unmap it from swap_out */
+#define VM_RESERVED     0x00080000      /* Pages managed in a special way */
 #define VM_ACCOUNT      0x00100000      /* Is a VM accounted object */
 #define VM_HUGETLB      0x00400000      /* Huge TLB Page VM */
 #define VM_NONLINEAR    0x00800000      /* Is non-linear (remap_file_pages) */
@@ -226,13 +226,18 @@ struct page {
                                         * to show when page is mapped
                                         * & limit reverse map searches.
                                         */
-        unsigned long private;          /* Mapping-private opaque data:
+        union {
+                unsigned long private;  /* Mapping-private opaque data:
                                         * usually used for buffer_heads
                                         * if PagePrivate set; used for
                                         * swp_entry_t if PageSwapCache
                                         * When page is free, this indicates
                                         * order in the buddy system.
                                         */
+#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+                spinlock_t ptl;
+#endif
+        } u;
        struct address_space *mapping;  /* If low bit clear, points to
                                         * inode address_space, or NULL.
                                         * If page mapped as anonymous
@@ -260,6 +265,9 @@ struct page {
 #endif /* WANT_PAGE_VIRTUAL */
 };
+#define page_private(page)              ((page)->u.private)
+#define set_page_private(page, v)       ((page)->u.private = (v))
 /*
 * FIXME: take this include out, include page-flags.h in
 * files which need it (119 of them)
@@ -311,17 +319,17 @@ extern void FASTCALL(__page_cache_release(struct page *));
 #ifdef CONFIG_HUGETLB_PAGE
-static inline int page_count(struct page *p)
+static inline int page_count(struct page *page)
 {
-        if (PageCompound(p))
+        if (PageCompound(page))
-                p = (struct page *)p->private;
+                page = (struct page *)page_private(page);
-        return atomic_read(&(p)->_count) + 1;
+        return atomic_read(&page->_count) + 1;
 }
 static inline void get_page(struct page *page)
 {
        if (unlikely(PageCompound(page)))
-                page = (struct page *)page->private;
+                page = (struct page *)page_private(page);
        atomic_inc(&page->_count);
 }
@@ -338,7 +346,7 @@ static inline void get_page(struct page *page)
 static inline void put_page(struct page *page)
 {
-        if (!PageReserved(page) && put_page_testzero(page))
+        if (put_page_testzero(page))
                __page_cache_release(page);
 }
@@ -587,7 +595,7 @@ static inline int PageAnon(struct page *page)
 static inline pgoff_t page_index(struct page *page)
 {
        if (unlikely(PageSwapCache(page)))
-                return page->private;
+                return page_private(page);
        return page->index;
 }
@@ -682,7 +690,7 @@ struct zap_details {
 unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address,
                unsigned long size, struct zap_details *);
-unsigned long unmap_vmas(struct mmu_gather **tlb, struct mm_struct *mm,
+unsigned long unmap_vmas(struct mmu_gather **tlb,
                struct vm_area_struct *start_vma, unsigned long start_addr,
                unsigned long end_addr, unsigned long *nr_accounted,
                struct zap_details *);
@@ -704,10 +712,6 @@ static inline void unmap_shared_mapping_range(struct address_space *mapping,
 }
 extern int vmtruncate(struct inode * inode, loff_t offset);
-extern pud_t *FASTCALL(__pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address));
-extern pmd_t *FASTCALL(__pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address));
-extern pte_t *FASTCALL(pte_alloc_kernel(struct mm_struct *mm, pmd_t *pmd, unsigned long address));
-extern pte_t *FASTCALL(pte_alloc_map(struct mm_struct *mm, pmd_t *pmd, unsigned long address));
 extern int install_page(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, struct page *page, pgprot_t prot);
 extern int install_file_pte(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long pgoff, pgprot_t prot);
 extern int __handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access);
@@ -723,6 +727,7 @@ void install_arg_page(struct vm_area_struct *, struct page *, unsigned long);
 int get_user_pages(struct task_struct *tsk, struct mm_struct *mm, unsigned long start,
                int len, int write, int force, struct page **pages, struct vm_area_struct **vmas);
+void print_bad_pte(struct vm_area_struct *, pte_t, unsigned long);
 int __set_page_dirty_buffers(struct page *page);
 int __set_page_dirty_nobuffers(struct page *page);
@@ -759,38 +764,83 @@ struct shrinker;
 extern struct shrinker *set_shrinker(int, shrinker_t);
 extern void remove_shrinker(struct shrinker *shrinker);
-/*
+int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address);
- * On a two-level or three-level page table, this ends up being trivial. Thus
+int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address);
- * the inlining and the symmetry break with pte_alloc_map() that does all
+int __pte_alloc(struct mm_struct *mm, pmd_t *pmd, unsigned long address);
- * of this out-of-line.
+int __pte_alloc_kernel(pmd_t *pmd, unsigned long address);
- */
 /*
 * The following ifdef needed to get the 4level-fixup.h header to work.
 * Remove it when 4level-fixup.h has been removed.
 */
-#ifdef CONFIG_MMU
+#if defined(CONFIG_MMU) && !defined(__ARCH_HAS_4LEVEL_HACK)
-#ifndef __ARCH_HAS_4LEVEL_HACK 
 static inline pud_t *pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address)
 {
-        if (pgd_none(*pgd))
+        return (unlikely(pgd_none(*pgd)) && __pud_alloc(mm, pgd, address))?
-                return __pud_alloc(mm, pgd, address);
+                NULL: pud_offset(pgd, address);
-        return pud_offset(pgd, address);
 }
 static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address)
 {
-        if (pud_none(*pud))
+        return (unlikely(pud_none(*pud)) && __pmd_alloc(mm, pud, address))?
-                return __pmd_alloc(mm, pud, address);
+                NULL: pmd_offset(pud, address);
-        return pmd_offset(pud, address);
 }
-#endif
+#endif /* CONFIG_MMU && !__ARCH_HAS_4LEVEL_HACK */
-#endif /* CONFIG_MMU */
+#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+/*
+ * We tuck a spinlock to guard each pagetable page into its struct page,
+ * at page->private, with BUILD_BUG_ON to make sure that this will not
+ * overflow into the next struct page (as it might with DEBUG_SPINLOCK).
+ * When freeing, reset page->mapping so free_pages_check won't complain.
+ */
+#define __pte_lockptr(page)     &((page)->u.ptl)
+#define pte_lock_init(_page)    do {                                    \
+        spin_lock_init(__pte_lockptr(_page));                           \
+} while (0)
+#define pte_lock_deinit(page)   ((page)->mapping = NULL)
+#define pte_lockptr(mm, pmd)    ({(void)(mm); __pte_lockptr(pmd_page(*(pmd)));})
+#else
+/*
+ * We use mm->page_table_lock to guard all pagetable pages of the mm.
+ */
+#define pte_lock_init(page)     do {} while (0)
+#define pte_lock_deinit(page)   do {} while (0)
+#define pte_lockptr(mm, pmd)    ({(void)(pmd); &(mm)->page_table_lock;})
+#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+#define pte_offset_map_lock(mm, pmd, address, ptlp)     \
+({                                                      \
+        spinlock_t *__ptl = pte_lockptr(mm, pmd);       \
+        pte_t *__pte = pte_offset_map(pmd, address);    \
+        *(ptlp) = __ptl;                                \
+        spin_lock(__ptl);                               \
+        __pte;                                          \
+})
+#define pte_unmap_unlock(pte, ptl)      do {            \
+        spin_unlock(ptl);                               \
+        pte_unmap(pte);                                 \
+} while (0)
+#define pte_alloc_map(mm, pmd, address)                 \
+        ((unlikely(!pmd_present(*(pmd))) && __pte_alloc(mm, pmd, address))? \
+                NULL: pte_offset_map(pmd, address))
+#define pte_alloc_map_lock(mm, pmd, address, ptlp)      \
+        ((unlikely(!pmd_present(*(pmd))) && __pte_alloc(mm, pmd, address))? \
+                NULL: pte_offset_map_lock(mm, pmd, address, ptlp))
+#define pte_alloc_kernel(pmd, address)                  \
+        ((unlikely(!pmd_present(*(pmd))) && __pte_alloc_kernel(pmd, address))? \
+                NULL: pte_offset_kernel(pmd, address))
 extern void free_area_init(unsigned long * zones_size);
 extern void free_area_init_node(int nid, pg_data_t *pgdat,
        unsigned long * zones_size, unsigned long zone_start_pfn, 
        unsigned long *zholes_size);
 extern void memmap_init_zone(unsigned long, int, unsigned long, unsigned long);
+extern void setup_per_zone_pages_min(void);
 extern void mem_init(void);
 extern void show_mem(void);
 extern void si_meminfo(struct sysinfo * val);
@@ -834,6 +884,7 @@ extern int split_vma(struct mm_struct *,
 extern int insert_vm_struct(struct mm_struct *, struct vm_area_struct *);
 extern void __vma_link_rb(struct mm_struct *, struct vm_area_struct *,
        struct rb_node **, struct rb_node *);
+extern void unlink_file_vma(struct vm_area_struct *);
 extern struct vm_area_struct *copy_vma(struct vm_area_struct **,
        unsigned long addr, unsigned long len, pgoff_t pgoff);
 extern void exit_mmap(struct mm_struct *);
@@ -894,7 +945,8 @@ void handle_ra_miss(struct address_space *mapping,
 unsigned long max_sane_readahead(unsigned long nr);
 /* Do stack extension */
-extern int expand_stack(struct vm_area_struct * vma, unsigned long address);
+extern int expand_stack(struct vm_area_struct *vma, unsigned long address);
+extern int expand_upwards(struct vm_area_struct *vma, unsigned long address);
 /* Look up the first VMA which satisfies  addr < vm_end,  NULL if none. */
 extern struct vm_area_struct * find_vma(struct mm_struct * mm, unsigned long addr);
@@ -917,40 +969,28 @@ static inline unsigned long vma_pages(struct vm_area_struct *vma)
        return (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
 }
-extern struct vm_area_struct *find_extend_vma(struct mm_struct *mm, unsigned long addr);
+struct vm_area_struct *find_extend_vma(struct mm_struct *, unsigned long addr);
+struct page *vmalloc_to_page(void *addr);
+unsigned long vmalloc_to_pfn(void *addr);
+int remap_pfn_range(struct vm_area_struct *, unsigned long addr,
+                        unsigned long pfn, unsigned long size, pgprot_t);
-extern struct page * vmalloc_to_page(void *addr);
+struct page *follow_page(struct mm_struct *, unsigned long address,
-extern unsigned long vmalloc_to_pfn(void *addr);
+                        unsigned int foll_flags);
-extern struct page * follow_page(struct mm_struct *mm, unsigned long address,
+#define FOLL_WRITE      0x01    /* check pte is writable */
-                int write);
+#define FOLL_TOUCH      0x02    /* mark page accessed */
-extern int check_user_page_readable(struct mm_struct *mm, unsigned long address);
+#define FOLL_GET        0x04    /* do get_page on page */
-int remap_pfn_range(struct vm_area_struct *, unsigned long,
+#define FOLL_ANON       0x08    /* give ZERO_PAGE if no pgtable */
-                unsigned long, unsigned long, pgprot_t);
 #ifdef CONFIG_PROC_FS
-void __vm_stat_account(struct mm_struct *, unsigned long, struct file *, long);
+void vm_stat_account(struct mm_struct *, unsigned long, struct file *, long);
 #else
-static inline void __vm_stat_account(struct mm_struct *mm,
+static inline void vm_stat_account(struct mm_struct *mm,
                        unsigned long flags, struct file *file, long pages)
 {
 }
 #endif /* CONFIG_PROC_FS */
-static inline void vm_stat_account(struct vm_area_struct *vma)
-{
-        __vm_stat_account(vma->vm_mm, vma->vm_flags, vma->vm_file,
-                                                        vma_pages(vma));
-}
-static inline void vm_stat_unaccount(struct vm_area_struct *vma)
-{
-        __vm_stat_account(vma->vm_mm, vma->vm_flags, vma->vm_file,
-                                                        -vma_pages(vma));
-}
-/* update per process rss and vm hiwater data */
-extern void update_mem_hiwater(struct task_struct *tsk);
 #ifndef CONFIG_DEBUG_PAGEALLOC
 static inline void
 kernel_map_pages(struct page *page, int numpages, int enable)
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 7519eb4191e7..f5fa3082fd6a 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -12,6 +12,7 @@
 #include <linux/threads.h>
 #include <linux/numa.h>
 #include <linux/init.h>
+#include <linux/seqlock.h>
 #include <asm/atomic.h>
 /* Free memory management - zoned buddy allocator.  */
@@ -137,6 +138,10 @@ struct zone {
         * free areas of different sizes
         */
        spinlock_t              lock;
+#ifdef CONFIG_MEMORY_HOTPLUG
+        /* see spanned/present_pages for more description */
+        seqlock_t               span_seqlock;
+#endif
        struct free_area        free_area[MAX_ORDER];
@@ -220,6 +225,16 @@ struct zone {
        /* zone_start_pfn == zone_start_paddr >> PAGE_SHIFT */
        unsigned long           zone_start_pfn;
+        /*
+         * zone_start_pfn, spanned_pages and present_pages are all
+         * protected by span_seqlock.  It is a seqlock because it has
+         * to be read outside of zone->lock, and it is done in the main
+         * allocator path.  But, it is written quite infrequently.
+         *
+         * The lock is declared along with zone->lock because it is
+         * frequently read in proximity to zone->lock.  It's good to
+         * give them a chance of being in the same cacheline.
+         */
        unsigned long           spanned_pages;  /* total size, including holes */
        unsigned long           present_pages;  /* amount of memory (excluding holes) */
@@ -273,6 +288,16 @@ typedef struct pglist_data {
        struct page *node_mem_map;
 #endif
        struct bootmem_data *bdata;
+#ifdef CONFIG_MEMORY_HOTPLUG
+        /*
+         * Must be held any time you expect node_start_pfn, node_present_pages
+         * or node_spanned_pages stay constant.  Holding this will also
+         * guarantee that any pfn_valid() stays that way.
+         *
+         * Nests above zone->lock and zone->size_seqlock.
+         */
+        spinlock_t node_size_lock;
+#endif
        unsigned long node_start_pfn;
        unsigned long node_present_pages; /* total number of physical pages */
        unsigned long node_spanned_pages; /* total size of physical page
@@ -293,6 +318,8 @@ typedef struct pglist_data {
 #endif
 #define nid_page_nr(nid, pagenr)        pgdat_page_nr(NODE_DATA(nid),(pagenr))
+#include <linux/memory_hotplug.h>
 extern struct pglist_data *pgdat_list;
 void __get_zone_counts(unsigned long *active, unsigned long *inactive,
@@ -509,6 +536,7 @@ static inline struct mem_section *__nr_to_section(unsigned long nr)
                return NULL;
        return &mem_section[SECTION_NR_TO_ROOT(nr)][nr & SECTION_ROOT_MASK];
 }
+extern int __section_nr(struct mem_section* ms);
 /*
 * We use the lower bits of the mem_map pointer to store
diff --git a/include/linux/module.h b/include/linux/module.h
index f05372b7fe77..84d75f3a8aca 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -554,7 +554,9 @@ static inline void MODULE_PARM_(void) { }
 #ifdef MODULE
 /* DEPRECATED: Do not use. */
 #define MODULE_PARM(var,type)                                               \
-struct obsolete_modparm __parm_##var __attribute__((section("__obsparm"))) = \
+extern struct obsolete_modparm __parm_##var \
+__attribute__((section("__obsparm"))); \
+struct obsolete_modparm __parm_##var = \
 { __stringify(var), type, &MODULE_PARM_ }; \
 __MODULE_PARM_TYPE(var, type);
 #else
diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h
index 9a3d27257984..941da5c016a0 100644
--- a/include/linux/msdos_fs.h
+++ b/include/linux/msdos_fs.h
@@ -282,6 +282,17 @@ static inline u8 fat_attr(struct inode *inode)
                MSDOS_I(inode)->i_attrs;
 }
+static inline unsigned char fat_checksum(const __u8 *name)
+{
+        unsigned char s = name[0];
+        s = (s<<7) + (s>>1) + name[1];  s = (s<<7) + (s>>1) + name[2];
+        s = (s<<7) + (s>>1) + name[3];  s = (s<<7) + (s>>1) + name[4];
+        s = (s<<7) + (s>>1) + name[5];  s = (s<<7) + (s>>1) + name[6];
+        s = (s<<7) + (s>>1) + name[7];  s = (s<<7) + (s>>1) + name[8];
+        s = (s<<7) + (s>>1) + name[9];  s = (s<<7) + (s>>1) + name[10];
+        return s;
+}
 static inline sector_t fat_clus_to_blknr(struct msdos_sb_info *sbi, int clus)
 {
        return ((sector_t)clus - FAT_START_ENT) * sbi->sec_per_clus
diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
index 142963f01d29..fc28841f3409 100644
--- a/include/linux/mtd/map.h
+++ b/include/linux/mtd/map.h
@@ -8,7 +8,10 @@
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/list.h>
+#include <linux/string.h>
 #include <linux/mtd/compatmac.h>
 #include <asm/unaligned.h>
 #include <asm/system.h>
 #include <asm/io.h>
diff --git a/include/linux/netfilter_arp/arp_tables.h b/include/linux/netfilter_arp/arp_tables.h
index d759a637bded..e98a870a20be 100644
--- a/include/linux/netfilter_arp/arp_tables.h
+++ b/include/linux/netfilter_arp/arp_tables.h
@@ -68,7 +68,8 @@ struct arpt_entry_target
                        u_int16_t target_size;
                        /* Used by userspace */
-                        char name[ARPT_FUNCTION_MAXNAMELEN];
+                        char name[ARPT_FUNCTION_MAXNAMELEN-1];
+                        u_int8_t revision;
                } user;
                struct {
                        u_int16_t target_size;
@@ -148,7 +149,9 @@ struct arpt_entry
 #define ARPT_SO_GET_INFO                (ARPT_BASE_CTL)
 #define ARPT_SO_GET_ENTRIES             (ARPT_BASE_CTL + 1)
-#define ARPT_SO_GET_MAX                 ARPT_SO_GET_ENTRIES
+/* #define ARPT_SO_GET_REVISION_MATCH   (ARPT_BASE_CTL + 2)*/
+#define ARPT_SO_GET_REVISION_TARGET     (ARPT_BASE_CTL + 3)
+#define ARPT_SO_GET_MAX                 ARPT_SO_GET_REVISION_TARGET
 /* CONTINUE verdict for targets */
 #define ARPT_CONTINUE 0xFFFFFFFF
@@ -236,6 +239,15 @@ struct arpt_get_entries
        struct arpt_entry entrytable[0];
 };
+/* The argument to ARPT_SO_GET_REVISION_*.  Returns highest revision
+ * kernel supports, if >= revision. */
+struct arpt_get_revision
+{
+        char name[ARPT_FUNCTION_MAXNAMELEN-1];
+        u_int8_t revision;
+};
 /* Standard return verdict, or do jump. */
 #define ARPT_STANDARD_TARGET ""
 /* Error verdict. */
@@ -274,7 +286,9 @@ struct arpt_target
 {
        struct list_head list;
-        const char name[ARPT_FUNCTION_MAXNAMELEN];
+        const char name[ARPT_FUNCTION_MAXNAMELEN-1];
+        u_int8_t revision;
        /* Returns verdict. */
        unsigned int (*target)(struct sk_buff **pskb,
diff --git a/include/linux/netfilter_ipv6/ip6_tables.h b/include/linux/netfilter_ipv6/ip6_tables.h
index 59f70b34e029..2efc046d9e94 100644
--- a/include/linux/netfilter_ipv6/ip6_tables.h
+++ b/include/linux/netfilter_ipv6/ip6_tables.h
@@ -57,7 +57,8 @@ struct ip6t_entry_match
                        u_int16_t match_size;
                        /* Used by userspace */
-                        char name[IP6T_FUNCTION_MAXNAMELEN];
+                        char name[IP6T_FUNCTION_MAXNAMELEN-1];
+                        u_int8_t revision;
                } user;
                struct {
                        u_int16_t match_size;
@@ -80,7 +81,8 @@ struct ip6t_entry_target
                        u_int16_t target_size;
                        /* Used by userspace */
-                        char name[IP6T_FUNCTION_MAXNAMELEN];
+                        char name[IP6T_FUNCTION_MAXNAMELEN-1];
+                        u_int8_t revision;
                } user;
                struct {
                        u_int16_t target_size;
@@ -161,7 +163,9 @@ struct ip6t_entry
 #define IP6T_SO_GET_INFO                (IP6T_BASE_CTL)
 #define IP6T_SO_GET_ENTRIES             (IP6T_BASE_CTL + 1)
-#define IP6T_SO_GET_MAX                 IP6T_SO_GET_ENTRIES
+#define IP6T_SO_GET_REVISION_MATCH      (IP6T_BASE_CTL + 2)
+#define IP6T_SO_GET_REVISION_TARGET     (IP6T_BASE_CTL + 3)
+#define IP6T_SO_GET_MAX                 IP6T_SO_GET_REVISION_TARGET
 /* CONTINUE verdict for targets */
 #define IP6T_CONTINUE 0xFFFFFFFF
@@ -291,6 +295,15 @@ struct ip6t_get_entries
        struct ip6t_entry entrytable[0];
 };
+/* The argument to IP6T_SO_GET_REVISION_*.  Returns highest revision
+ * kernel supports, if >= revision. */
+struct ip6t_get_revision
+{
+        char name[IP6T_FUNCTION_MAXNAMELEN-1];
+        u_int8_t revision;
+};
 /* Standard return verdict, or do jump. */
 #define IP6T_STANDARD_TARGET ""
 /* Error verdict. */
@@ -352,7 +365,9 @@ struct ip6t_match
 {
        struct list_head list;
-        const char name[IP6T_FUNCTION_MAXNAMELEN];
+        const char name[IP6T_FUNCTION_MAXNAMELEN-1];
+        u_int8_t revision;
        /* Return true or false: return FALSE and set *hotdrop = 1 to
           force immediate packet drop. */
@@ -387,7 +402,9 @@ struct ip6t_target
 {
        struct list_head list;
-        const char name[IP6T_FUNCTION_MAXNAMELEN];
+        const char name[IP6T_FUNCTION_MAXNAMELEN-1];
+        u_int8_t revision;
        /* Returns verdict. Argument order changed since 2.6.9, as this
           must now handle non-linear skbs, using skb_copy_bits and
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 325fe7ae49bb..12787a9b0259 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -316,7 +316,7 @@ extern struct nfs_open_context *alloc_nfs_open_context(struct dentry *dentry, st
 extern struct nfs_open_context *get_nfs_open_context(struct nfs_open_context *ctx);
 extern void put_nfs_open_context(struct nfs_open_context *ctx);
 extern void nfs_file_set_open_context(struct file *filp, struct nfs_open_context *ctx);
-extern struct nfs_open_context *nfs_find_open_context(struct inode *inode, int mode);
+extern struct nfs_open_context *nfs_find_open_context(struct inode *inode, struct rpc_cred *cred, int mode);
 extern void nfs_file_clear_open_context(struct file *filp);
 /* linux/net/ipv4/ipconfig.c: trims ip addr off front of name, too. */
diff --git a/include/linux/nodemask.h b/include/linux/nodemask.h
index e96fe9062500..4726ef7ba8e8 100644
--- a/include/linux/nodemask.h
+++ b/include/linux/nodemask.h
@@ -12,6 +12,8 @@
 * see bitmap_scnprintf() and bitmap_parse() in lib/bitmap.c.
 * For details of nodelist_scnprintf() and nodelist_parse(), see
 * bitmap_scnlistprintf() and bitmap_parselist(), also in bitmap.c.
+ * For details of node_remap(), see bitmap_bitremap in lib/bitmap.c.
+ * For details of nodes_remap(), see bitmap_remap in lib/bitmap.c.
 *
 * The available nodemask operations are:
 *
@@ -52,6 +54,8 @@
 * int nodemask_parse(ubuf, ulen, mask) Parse ascii string as nodemask
 * int nodelist_scnprintf(buf, len, mask) Format nodemask as list for printing
 * int nodelist_parse(buf, map)         Parse ascii string as nodelist
+ * int node_remap(oldbit, old, new)     newbit = map(old, new)(oldbit)
+ * int nodes_remap(dst, src, old, new)  *dst = map(old, new)(dst)
 *
 * for_each_node_mask(node, mask)       for-loop node over mask
 *
@@ -307,6 +311,22 @@ static inline int __nodelist_parse(const char *buf, nodemask_t *dstp, int nbits)
        return bitmap_parselist(buf, dstp->bits, nbits);
 }
+#define node_remap(oldbit, old, new) \
+                __node_remap((oldbit), &(old), &(new), MAX_NUMNODES)
+static inline int __node_remap(int oldbit,
+                const nodemask_t *oldp, const nodemask_t *newp, int nbits)
+{
+        return bitmap_bitremap(oldbit, oldp->bits, newp->bits, nbits);
+}
+#define nodes_remap(dst, src, old, new) \
+                __nodes_remap(&(dst), &(src), &(old), &(new), MAX_NUMNODES)
+static inline void __nodes_remap(nodemask_t *dstp, const nodemask_t *srcp,
+                const nodemask_t *oldp, const nodemask_t *newp, int nbits)
+{
+        bitmap_remap(dstp->bits, srcp->bits, oldp->bits, newp->bits, nbits);
+}
 #if MAX_NUMNODES > 1
 #define for_each_node_mask(node, mask)                  \
        for ((node) = first_node(mask);                 \
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 7d300f7469e3..56192005fa4d 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -96,6 +96,9 @@
 #define PCI_CLASS_SERIAL_ACCESS         0x0c01
 #define PCI_CLASS_SERIAL_SSA            0x0c02
 #define PCI_CLASS_SERIAL_USB            0x0c03
+#define PCI_CLASS_SERIAL_USB_UHCI       0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI       0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI       0x0c0320
 #define PCI_CLASS_SERIAL_FIBER          0x0c04
 #define PCI_CLASS_SERIAL_SMBUS          0x0c05
@@ -1785,11 +1788,13 @@
 #define PCI_DEVICE_ID_TIGON3_5721       0x1659
 #define PCI_DEVICE_ID_TIGON3_5705M      0x165d
 #define PCI_DEVICE_ID_TIGON3_5705M_2    0x165e
+#define PCI_DEVICE_ID_TIGON3_5714       0x1668
 #define PCI_DEVICE_ID_TIGON3_5780       0x166a
 #define PCI_DEVICE_ID_TIGON3_5780S      0x166b
 #define PCI_DEVICE_ID_TIGON3_5705F      0x166e
 #define PCI_DEVICE_ID_TIGON3_5750       0x1676
 #define PCI_DEVICE_ID_TIGON3_5751       0x1677
+#define PCI_DEVICE_ID_TIGON3_5715       0x1678
 #define PCI_DEVICE_ID_TIGON3_5750M      0x167c
 #define PCI_DEVICE_ID_TIGON3_5751M      0x167d
 #define PCI_DEVICE_ID_TIGON3_5751F      0x167e
diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
new file mode 100644
index 000000000000..a726225e0afe
--- /dev/null
+++ b/include/linux/platform_device.h
@@ -0,0 +1,40 @@
+/*
+ * platform_device.h - generic, centralized driver model
+ *
+ * Copyright (c) 2001-2003 Patrick Mochel <mochel@osdl.org>
+ *
+ * This file is released under the GPLv2
+ *
+ * See Documentation/driver-model/ for more information.
+ */
+#ifndef _PLATFORM_DEVICE_H_
+#define _PLATFORM_DEVICE_H_
+#include <linux/device.h>
+struct platform_device {
+        const char      * name;
+        u32             id;
+        struct device   dev;
+        u32             num_resources;
+        struct resource * resource;
+};
+#define to_platform_device(x) container_of((x), struct platform_device, dev)
+extern int platform_device_register(struct platform_device *);
+extern void platform_device_unregister(struct platform_device *);
+extern struct bus_type platform_bus_type;
+extern struct device platform_bus;
+extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int);
+extern int platform_get_irq(struct platform_device *, unsigned int);
+extern struct resource *platform_get_resource_byname(struct platform_device *, unsigned int, char *);
+extern int platform_get_irq_byname(struct platform_device *, char *);
+extern int platform_add_devices(struct platform_device **, int);
+extern struct platform_device *platform_device_register_simple(char *, unsigned int, struct resource *, unsigned int);
+#endif /* _PLATFORM_DEVICE_H_ */
diff --git a/include/linux/pm.h b/include/linux/pm.h
index 7897cf500c51..1514098d156d 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -170,6 +170,7 @@ typedef int __bitwise suspend_disk_method_t;
 struct pm_ops {
        suspend_disk_method_t pm_disk_mode;
+        int (*valid)(suspend_state_t state);
        int (*prepare)(suspend_state_t state);
        int (*enter)(suspend_state_t state);
        int (*finish)(suspend_state_t state);
@@ -224,7 +225,6 @@ struct dev_pm_info {
        unsigned                should_wakeup:1;
        pm_message_t            prev_state;
        void                    * saved_state;
-        atomic_t                pm_users;
        struct device           * pm_parent;
        struct list_head        entry;
 #endif
@@ -244,6 +244,9 @@ extern int device_suspend(pm_message_t state);
 #define device_may_wakeup(dev) \
        (device_can_wakeup(dev) && (dev)->power.should_wakeup)
+extern int dpm_runtime_suspend(struct device *, pm_message_t);
+extern void dpm_runtime_resume(struct device *);
 #else /* !CONFIG_PM */
 static inline int device_suspend(pm_message_t state)
@@ -254,6 +257,16 @@ static inline int device_suspend(pm_message_t state)
 #define device_set_wakeup_enable(dev,val)       do{}while(0)
 #define device_may_wakeup(dev)                  (0)
+static inline int dpm_runtime_suspend(struct device * dev, pm_message_t state)
+{
+        return 0;
+}
+static inline void dpm_runtime_resume(struct device * dev)
+{
+}
 #endif
 /* changes to device_may_wakeup take effect on the next pm state change.
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index 70191a5a148f..cce25591eec2 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -275,6 +275,7 @@ static inline int rcu_pending(int cpu)
 extern void rcu_init(void);
 extern void rcu_check_callbacks(int cpu, int user);
 extern void rcu_restart_cpu(int cpu);
+extern long rcu_batches_completed(void);
 /* Exported interfaces */
 extern void FASTCALL(call_rcu(struct rcu_head *head, 
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index e80fb7ee6efd..35b30e6c8cf8 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -95,8 +95,8 @@ int try_to_unmap(struct page *);
 /*
 * Called from mm/filemap_xip.c to unmap empty zero page
 */
-pte_t *page_check_address(struct page *, struct mm_struct *, unsigned long);
+pte_t *page_check_address(struct page *, struct mm_struct *,
+                                unsigned long, spinlock_t **);
 /*
 * Used by swapoff to help locate where page is expected in vma.
diff --git a/include/linux/rwsem-spinlock.h b/include/linux/rwsem-spinlock.h
index b52a2af25f1f..f30f805080ae 100644
--- a/include/linux/rwsem-spinlock.h
+++ b/include/linux/rwsem-spinlock.h
@@ -61,5 +61,10 @@ extern void FASTCALL(__up_read(struct rw_semaphore *sem));
 extern void FASTCALL(__up_write(struct rw_semaphore *sem));
 extern void FASTCALL(__downgrade_write(struct rw_semaphore *sem));
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->activity != 0);
+}
 #endif /* __KERNEL__ */
 #endif /* _LINUX_RWSEM_SPINLOCK_H */
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 7f717e95ae37..66ff545552f7 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -1,14 +1,23 @@
 #ifndef _LINUX_SCATTERLIST_H
 #define _LINUX_SCATTERLIST_H
-static inline void sg_init_one(struct scatterlist *sg,
+#include <asm/scatterlist.h>
-                               u8 *buf, unsigned int buflen)
+#include <linux/mm.h>
-{
+#include <linux/string.h>
-        memset(sg, 0, sizeof(*sg));
+static inline void sg_set_buf(struct scatterlist *sg, void *buf,
+                              unsigned int buflen)
+{
        sg->page = virt_to_page(buf);
        sg->offset = offset_in_page(buf);
        sg->length = buflen;
 }
+static inline void sg_init_one(struct scatterlist *sg, void *buf,
+                               unsigned int buflen)
+{
+        memset(sg, 0, sizeof(*sg));
+        sg_set_buf(sg, buf, buflen);
+}
 #endif /* _LINUX_SCATTERLIST_H */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 27519df0f987..03b68a7b4b82 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -249,6 +249,36 @@ arch_get_unmapped_area_topdown(struct file *filp, unsigned long addr,
 extern void arch_unmap_area(struct mm_struct *, unsigned long);
 extern void arch_unmap_area_topdown(struct mm_struct *, unsigned long);
+#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+/*
+ * The mm counters are not protected by its page_table_lock,
+ * so must be incremented atomically.
+ */
+#ifdef ATOMIC64_INIT
+#define set_mm_counter(mm, member, value) atomic64_set(&(mm)->_##member, value)
+#define get_mm_counter(mm, member) ((unsigned long)atomic64_read(&(mm)->_##member))
+#define add_mm_counter(mm, member, value) atomic64_add(value, &(mm)->_##member)
+#define inc_mm_counter(mm, member) atomic64_inc(&(mm)->_##member)
+#define dec_mm_counter(mm, member) atomic64_dec(&(mm)->_##member)
+typedef atomic64_t mm_counter_t;
+#else /* !ATOMIC64_INIT */
+/*
+ * The counters wrap back to 0 at 2^32 * PAGE_SIZE,
+ * that is, at 16TB if using 4kB page size.
+ */
+#define set_mm_counter(mm, member, value) atomic_set(&(mm)->_##member, value)
+#define get_mm_counter(mm, member) ((unsigned long)atomic_read(&(mm)->_##member))
+#define add_mm_counter(mm, member, value) atomic_add(value, &(mm)->_##member)
+#define inc_mm_counter(mm, member) atomic_inc(&(mm)->_##member)
+#define dec_mm_counter(mm, member) atomic_dec(&(mm)->_##member)
+typedef atomic_t mm_counter_t;
+#endif /* !ATOMIC64_INIT */
+#else  /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+/*
+ * The mm counters are protected by its page_table_lock,
+ * so can be incremented directly.
+ */
 #define set_mm_counter(mm, member, value) (mm)->_##member = (value)
 #define get_mm_counter(mm, member) ((mm)->_##member)
 #define add_mm_counter(mm, member, value) (mm)->_##member += (value)
@@ -256,6 +286,20 @@ extern void arch_unmap_area_topdown(struct mm_struct *, unsigned long);
 #define dec_mm_counter(mm, member) (mm)->_##member--
 typedef unsigned long mm_counter_t;
+#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+#define get_mm_rss(mm)                                  \
+        (get_mm_counter(mm, file_rss) + get_mm_counter(mm, anon_rss))
+#define update_hiwater_rss(mm)  do {                    \
+        unsigned long _rss = get_mm_rss(mm);            \
+        if ((mm)->hiwater_rss < _rss)                   \
+                (mm)->hiwater_rss = _rss;               \
+} while (0)
+#define update_hiwater_vm(mm)   do {                    \
+        if ((mm)->hiwater_vm < (mm)->total_vm)          \
+                (mm)->hiwater_vm = (mm)->total_vm;      \
+} while (0)
 struct mm_struct {
        struct vm_area_struct * mmap;           /* list of VMAs */
        struct rb_root mm_rb;
@@ -279,15 +323,20 @@ struct mm_struct {
                                                 * by mmlist_lock
                                                 */
+        /* Special counters, in some configurations protected by the
+         * page_table_lock, in other configurations by being atomic.
+         */
+        mm_counter_t _file_rss;
+        mm_counter_t _anon_rss;
+        unsigned long hiwater_rss;      /* High-watermark of RSS usage */
+        unsigned long hiwater_vm;       /* High-water virtual memory usage */
+        unsigned long total_vm, locked_vm, shared_vm, exec_vm;
+        unsigned long stack_vm, reserved_vm, def_flags, nr_ptes;
        unsigned long start_code, end_code, start_data, end_data;
        unsigned long start_brk, brk, start_stack;
        unsigned long arg_start, arg_end, env_start, env_end;
-        unsigned long total_vm, locked_vm, shared_vm;
-        unsigned long exec_vm, stack_vm, reserved_vm, def_flags, nr_ptes;
-        /* Special counters protected by the page_table_lock */
-        mm_counter_t _rss;
-        mm_counter_t _anon_rss;
        unsigned long saved_auxv[AT_VECTOR_SIZE]; /* for /proc/PID/auxv */
@@ -308,11 +357,7 @@ struct mm_struct {
        /* aio bits */
        rwlock_t                ioctx_list_lock;
        struct kioctx           *ioctx_list;
        struct kioctx           default_kioctx;
-        unsigned long hiwater_rss;      /* High-water RSS usage */
-        unsigned long hiwater_vm;       /* High-water virtual memory usage */
 };
 struct sighand_struct {
@@ -895,7 +940,7 @@ extern int set_cpus_allowed(task_t *p, cpumask_t new_mask);
 #else
 static inline int set_cpus_allowed(task_t *p, cpumask_t new_mask)
 {
-        if (!cpus_intersects(new_mask, cpu_online_map))
+        if (!cpu_isset(0, new_mask))
                return -EINVAL;
        return 0;
 }
@@ -1039,6 +1084,11 @@ extern int do_sigaltstack(const stack_t __user *, stack_t __user *, unsigned lon
 #define SEND_SIG_PRIV   ((struct siginfo *) 1)
 #define SEND_SIG_FORCED ((struct siginfo *) 2)
+static inline int is_si_special(const struct siginfo *info)
+{
+        return info <= SEND_SIG_FORCED;
+}
 /* True if we are on the alternate signal stack.  */
 static inline int on_sig_stack(unsigned long sp)
@@ -1166,7 +1216,7 @@ extern void unhash_process(struct task_struct *p);
 /*
 * Protects ->fs, ->files, ->mm, ->ptrace, ->group_info, ->comm, keyring
 * subscriptions and synchronises with wait4().  Also used in procfs.  Also
- * pins the final release of task.io_context.
+ * pins the final release of task.io_context.  Also protects ->cpuset.
 *
 * Nests both inside and outside of read_lock(&tasklist_lock).
 * It must not be nested with write_lock_irq(&tasklist_lock),
diff --git a/include/linux/security.h b/include/linux/security.h
index dac956ed98f0..f7e0ae018712 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -30,6 +30,7 @@
 #include <linux/shm.h>
 #include <linux/msg.h>
 #include <linux/sched.h>
+#include <linux/key.h>
 struct ctl_table;
@@ -385,6 +386,9 @@ struct swap_info_struct;
 *      NULL to request the size of the buffer required.  @size indicates
 *      the size of @buffer in bytes.  Note that @name is the remainder
 *      of the attribute name after the security. prefix has been removed.
+ *      @err is the return value from the preceding fs getxattr call,
+ *      and can be used by the security module to determine whether it
+ *      should try and canonicalize the attribute value.
 *      Return number of bytes used/required on success.
 * @inode_setsecurity:
 *      Set the security label associated with @name for @inode from the
@@ -785,6 +789,27 @@ struct swap_info_struct;
 * @sk_free_security:
 *      Deallocate security structure.
 *
+ * Security hooks affecting all Key Management operations
+ *
+ * @key_alloc:
+ *      Permit allocation of a key and assign security data. Note that key does
+ *      not have a serial number assigned at this point.
+ *      @key points to the key.
+ *      Return 0 if permission is granted, -ve error otherwise.
+ * @key_free:
+ *      Notification of destruction; free security data.
+ *      @key points to the key.
+ *      No return value.
+ * @key_permission:
+ *      See whether a specific operational right is granted to a process on a
+ *      key.
+ *      @key_ref refers to the key (key pointer + possession attribute bit).
+ *      @context points to the process to provide the context against which to
+ *       evaluate the security data on the key.
+ *      @perm describes the combination of permissions required of this key.
+ *      Return 1 if permission granted, 0 if permission denied and -ve it the
+ *      normal permissions model should be effected.
+ *
 * Security hooks affecting all System V IPC operations.
 *
 * @ipc_permission:
@@ -1091,7 +1116,7 @@ struct security_operations {
        int (*inode_getxattr) (struct dentry *dentry, char *name);
        int (*inode_listxattr) (struct dentry *dentry);
        int (*inode_removexattr) (struct dentry *dentry, char *name);
-        int (*inode_getsecurity)(struct inode *inode, const char *name, void *buffer, size_t size);
+        int (*inode_getsecurity)(struct inode *inode, const char *name, void *buffer, size_t size, int err);
        int (*inode_setsecurity)(struct inode *inode, const char *name, const void *value, size_t size, int flags);
        int (*inode_listsecurity)(struct inode *inode, char *buffer, size_t buffer_size);
@@ -1213,6 +1238,17 @@ struct security_operations {
        int (*sk_alloc_security) (struct sock *sk, int family, gfp_t priority);
        void (*sk_free_security) (struct sock *sk);
 #endif  /* CONFIG_SECURITY_NETWORK */
+        /* key management security hooks */
+#ifdef CONFIG_KEYS
+        int (*key_alloc)(struct key *key);
+        void (*key_free)(struct key *key);
+        int (*key_permission)(key_ref_t key_ref,
+                              struct task_struct *context,
+                              key_perm_t perm);
+#endif  /* CONFIG_KEYS */
 };
 /* global variables */
@@ -1580,11 +1616,11 @@ static inline int security_inode_removexattr (struct dentry *dentry, char *name)
        return security_ops->inode_removexattr (dentry, name);
 }
-static inline int security_inode_getsecurity(struct inode *inode, const char *name, void *buffer, size_t size)
+static inline int security_inode_getsecurity(struct inode *inode, const char *name, void *buffer, size_t size, int err)
 {
        if (unlikely (IS_PRIVATE (inode)))
                return 0;
-        return security_ops->inode_getsecurity(inode, name, buffer, size);
+        return security_ops->inode_getsecurity(inode, name, buffer, size, err);
 }
 static inline int security_inode_setsecurity(struct inode *inode, const char *name, const void *value, size_t size, int flags)
@@ -2222,7 +2258,7 @@ static inline int security_inode_removexattr (struct dentry *dentry, char *name)
        return cap_inode_removexattr(dentry, name);
 }
-static inline int security_inode_getsecurity(struct inode *inode, const char *name, void *buffer, size_t size)
+static inline int security_inode_getsecurity(struct inode *inode, const char *name, void *buffer, size_t size, int err)
 {
        return -EOPNOTSUPP;
 }
@@ -2761,5 +2797,45 @@ static inline void security_sk_free(struct sock *sk)
 }
 #endif  /* CONFIG_SECURITY_NETWORK */
+#ifdef CONFIG_KEYS
+#ifdef CONFIG_SECURITY
+static inline int security_key_alloc(struct key *key)
+{
+        return security_ops->key_alloc(key);
+}
+static inline void security_key_free(struct key *key)
+{
+        security_ops->key_free(key);
+}
+static inline int security_key_permission(key_ref_t key_ref,
+                                          struct task_struct *context,
+                                          key_perm_t perm)
+{
+        return security_ops->key_permission(key_ref, context, perm);
+}
+#else
+static inline int security_key_alloc(struct key *key)
+{
+        return 0;
+}
+static inline void security_key_free(struct key *key)
+{
+}
+static inline int security_key_permission(key_ref_t key_ref,
+                                          struct task_struct *context,
+                                          key_perm_t perm)
+{
+        return 0;
+}
+#endif
+#endif /* CONFIG_KEYS */
 #endif /* ! __LINUX_SECURITY_H */
diff --git a/include/linux/serial.h b/include/linux/serial.h
index 12cd9cf65e8f..33fc8cb8ddfb 100644
--- a/include/linux/serial.h
+++ b/include/linux/serial.h
@@ -11,6 +11,7 @@
 #define _LINUX_SERIAL_H
 #ifdef __KERNEL__
+#include <linux/types.h>
 #include <asm/page.h>
 /*
diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
index 317a979b24de..2b799d40d669 100644
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -12,7 +12,7 @@
 #define _LINUX_SERIAL_8250_H
 #include <linux/serial_core.h>
-#include <linux/device.h>
+#include <linux/platform_device.h>
 /*
 * This is the platform device platform_data structure
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 27db8da43aa4..9d2579230689 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -117,7 +117,9 @@
 #define PORT_M32R_SIO   68
 /*Digi jsm */
-#define PORT_JSM        65
+#define PORT_JSM        69
+#define PORT_IP3106     70
 #ifdef __KERNEL__
diff --git a/include/linux/serial_ip3106.h b/include/linux/serial_ip3106.h
new file mode 100644
index 000000000000..f500ac602c5c
--- /dev/null
+++ b/include/linux/serial_ip3106.h
@@ -0,0 +1,81 @@
+/*
+ * Embedded Alley Solutions, source@embeddedalley.com.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef _LINUX_SERIAL_IP3106_H
+#define _LINUX_SERIAL_IP3106_H
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#define IP3106_NR_PORTS         2
+struct ip3106_port {
+        struct uart_port        port;
+        struct timer_list       timer;
+        unsigned int            old_status;
+};
+/* register offsets */
+#define IP3106_LCR              0
+#define IP3106_MCR              0x004
+#define IP3106_BAUD             0x008
+#define IP3106_CFG              0x00c
+#define IP3106_FIFO             0x028
+#define IP3106_ISTAT            0xfe0
+#define IP3106_IEN              0xfe4
+#define IP3106_ICLR             0xfe8
+#define IP3106_ISET             0xfec
+#define IP3106_PD               0xff4
+#define IP3106_MID              0xffc
+#define IP3106_UART_LCR_TXBREAK         (1<<30)
+#define IP3106_UART_LCR_PAREVN          0x10000000
+#define IP3106_UART_LCR_PAREN           0x08000000
+#define IP3106_UART_LCR_2STOPB          0x04000000
+#define IP3106_UART_LCR_8BIT            0x01000000
+#define IP3106_UART_LCR_TX_RST          0x00040000
+#define IP3106_UART_LCR_RX_RST          0x00020000
+#define IP3106_UART_LCR_RX_NEXT         0x00010000
+#define IP3106_UART_MCR_SCR             0xFF000000
+#define IP3106_UART_MCR_DCD             0x00800000
+#define IP3106_UART_MCR_CTS             0x00100000
+#define IP3106_UART_MCR_LOOP            0x00000010
+#define IP3106_UART_MCR_RTS             0x00000002
+#define IP3106_UART_MCR_DTR             0x00000001
+#define IP3106_UART_INT_TX              0x00000080
+#define IP3106_UART_INT_EMPTY           0x00000040
+#define IP3106_UART_INT_RCVTO           0x00000020
+#define IP3106_UART_INT_RX              0x00000010
+#define IP3106_UART_INT_RXOVRN          0x00000008
+#define IP3106_UART_INT_FRERR           0x00000004
+#define IP3106_UART_INT_BREAK           0x00000002
+#define IP3106_UART_INT_PARITY          0x00000001
+#define IP3106_UART_INT_ALLRX           0x0000003F
+#define IP3106_UART_INT_ALLTX           0x000000C0
+#define IP3106_UART_FIFO_TXFIFO         0x001F0000
+#define IP3106_UART_FIFO_TXFIFO_STA     (0x1f<<16)
+#define IP3106_UART_FIFO_RXBRK          0x00008000
+#define IP3106_UART_FIFO_RXFE           0x00004000
+#define IP3106_UART_FIFO_RXPAR          0x00002000
+#define IP3106_UART_FIFO_RXFIFO         0x00001F00
+#define IP3106_UART_FIFO_RBRTHR         0x000000FF
+#endif
diff --git a/include/linux/signal.h b/include/linux/signal.h
index 7be18b5e2fb4..5dd5f02c5c5f 100644
--- a/include/linux/signal.h
+++ b/include/linux/signal.h
@@ -25,7 +25,6 @@
 struct sigqueue {
        struct list_head list;
-        spinlock_t *lock;
        int flags;
        siginfo_t info;
        struct user_struct *user;
diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h
index cdc99a27840d..0e9682c9def5 100644
--- a/include/linux/spinlock.h
+++ b/include/linux/spinlock.h
@@ -171,23 +171,42 @@ extern int __lockfunc generic__raw_read_trylock(raw_rwlock_t *lock);
 #define write_lock_irq(lock)            _write_lock_irq(lock)
 #define write_lock_bh(lock)             _write_lock_bh(lock)
-#define spin_unlock(lock)               _spin_unlock(lock)
+/*
-#define write_unlock(lock)              _write_unlock(lock)
+ * We inline the unlock functions in the nondebug case:
-#define read_unlock(lock)               _read_unlock(lock)
+ */
+#if defined(CONFIG_DEBUG_SPINLOCK) || defined(CONFIG_PREEMPT) || !defined(CONFIG_SMP)
+# define spin_unlock(lock)              _spin_unlock(lock)
+# define read_unlock(lock)              _read_unlock(lock)
+# define write_unlock(lock)             _write_unlock(lock)
+#else
+# define spin_unlock(lock)              __raw_spin_unlock(&(lock)->raw_lock)
+# define read_unlock(lock)              __raw_read_unlock(&(lock)->raw_lock)
+# define write_unlock(lock)             __raw_write_unlock(&(lock)->raw_lock)
+#endif
+#if defined(CONFIG_DEBUG_SPINLOCK) || defined(CONFIG_PREEMPT) || !defined(CONFIG_SMP)
+# define spin_unlock_irq(lock)          _spin_unlock_irq(lock)
+# define read_unlock_irq(lock)          _read_unlock_irq(lock)
+# define write_unlock_irq(lock)         _write_unlock_irq(lock)
+#else
+# define spin_unlock_irq(lock) \
+    do { __raw_spin_unlock(&(lock)->raw_lock); local_irq_enable(); } while (0)
+# define read_unlock_irq(lock) \
+    do { __raw_read_unlock(&(lock)->raw_lock); local_irq_enable(); } while (0)
+# define write_unlock_irq(lock) \
+    do { __raw_write_unlock(&(lock)->raw_lock); local_irq_enable(); } while (0)
+#endif
 #define spin_unlock_irqrestore(lock, flags) \
                                        _spin_unlock_irqrestore(lock, flags)
-#define spin_unlock_irq(lock)           _spin_unlock_irq(lock)
 #define spin_unlock_bh(lock)            _spin_unlock_bh(lock)
 #define read_unlock_irqrestore(lock, flags) \
                                        _read_unlock_irqrestore(lock, flags)
-#define read_unlock_irq(lock)           _read_unlock_irq(lock)
 #define read_unlock_bh(lock)            _read_unlock_bh(lock)
 #define write_unlock_irqrestore(lock, flags) \
                                        _write_unlock_irqrestore(lock, flags)
-#define write_unlock_irq(lock)          _write_unlock_irq(lock)
 #define write_unlock_bh(lock)           _write_unlock_bh(lock)
 #define spin_trylock_bh(lock)           __cond_lock(_spin_trylock_bh(lock))
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index ba448c760168..a61c04f804b2 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -71,7 +71,12 @@ void restore_processor_state(void);
 struct saved_context;
 void __save_processor_state(struct saved_context *ctxt);
 void __restore_processor_state(struct saved_context *ctxt);
-extern unsigned long get_usable_page(gfp_t gfp_mask);
+unsigned long get_safe_page(gfp_t gfp_mask);
-extern void free_eaten_memory(void);
+/*
+ * XXX: We try to keep some more pages free so that I/O operations succeed
+ * without paging. Might this be more?
+ */
+#define PAGES_FOR_IO    512
 #endif /* _LINUX_SWSUSP_H */
diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
index a6f03e473737..c7007b1db91d 100644
--- a/include/linux/syscalls.h
+++ b/include/linux/syscalls.h
@@ -491,6 +491,7 @@ asmlinkage long sys_nfsservctl(int cmd,
 asmlinkage long sys_syslog(int type, char __user *buf, int len);
 asmlinkage long sys_uselib(const char __user *library);
 asmlinkage long sys_ni_syscall(void);
+asmlinkage long sys_ptrace(long request, long pid, long addr, long data);
 asmlinkage long sys_add_key(const char __user *_type,
                            const char __user *_description,
diff --git a/include/linux/textsearch.h b/include/linux/textsearch.h
index fc5bb4e91a58..7dac8f04d28e 100644
--- a/include/linux/textsearch.h
+++ b/include/linux/textsearch.h
@@ -8,6 +8,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 struct ts_config;
diff --git a/include/linux/timer.h b/include/linux/timer.h
index 3340f3bd135d..72f3a7781106 100644
--- a/include/linux/timer.h
+++ b/include/linux/timer.h
@@ -12,16 +12,12 @@ struct timer_list {
        struct list_head entry;
        unsigned long expires;
-        unsigned long magic;
        void (*function)(unsigned long);
        unsigned long data;
        struct timer_base_s *base;
 };
-#define TIMER_MAGIC     0x4b87ad6e
 extern struct timer_base_s __init_timer_base;
 #define TIMER_INITIALIZER(_function, _expires, _data) {         \
@@ -29,7 +25,6 @@ extern struct timer_base_s __init_timer_base;
                .expires = (_expires),                          \
                .data = (_data),                                \
                .base = &__init_timer_base,                     \
-                .magic = TIMER_MAGIC,                           \
        }
 #define DEFINE_TIMER(_name, _function, _expires, _data)         \
@@ -38,6 +33,15 @@ extern struct timer_base_s __init_timer_base;
 void fastcall init_timer(struct timer_list * timer);
+static inline void setup_timer(struct timer_list * timer,
+                                void (*function)(unsigned long),
+                                unsigned long data)
+{
+        timer->function = function;
+        timer->data = data;
+        init_timer(timer);
+}
 /***
 * timer_pending - is a timer pending?
 * @timer: the timer in question
@@ -74,8 +78,9 @@ extern unsigned long next_timer_interrupt(void);
 * Timers with an ->expired field in the past will be executed in the next
 * timer tick.
 */
-static inline void add_timer(struct timer_list * timer)
+static inline void add_timer(struct timer_list *timer)
 {
+        BUG_ON(timer_pending(timer));
        __mod_timer(timer, timer->expires);
 }
diff --git a/include/linux/timex.h b/include/linux/timex.h
index 7e050a2cc35b..04a4a8cb4ed3 100644
--- a/include/linux/timex.h
+++ b/include/linux/timex.h
@@ -282,6 +282,13 @@ static inline int ntp_synced(void)
        return !(time_status & STA_UNSYNC);
 }
+/* Required to safely shift negative values */
+#define shift_right(x, s) ({    \
+        __typeof__(x) __x = (x);        \
+        __typeof__(s) __s = (s);        \
+        __x < 0 ? -(-__x >> __s) : __x >> __s;  \
+})
 #ifdef CONFIG_TIME_INTERPOLATION
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 8f731e8f2821..748d04385256 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -57,6 +57,7 @@ struct usb_host_endpoint {
        struct usb_endpoint_descriptor  desc;
        struct list_head                urb_list;
        void                            *hcpriv;
+        struct kobject                  *kobj;  /* For sysfs info */
        unsigned char *extra;   /* Extra descriptors */
        int extralen;
@@ -136,7 +137,8 @@ struct usb_interface {
                                         * active alternate setting */
        unsigned num_altsetting;        /* number of alternate settings */
-        int minor;                      /* minor number this interface is bound to */
+        int minor;                      /* minor number this interface is
+                                         * bound to */
        enum usb_interface_condition condition;         /* state of binding */
        struct device dev;              /* interface specific device info */
        struct class_device *class_dev;
@@ -229,7 +231,7 @@ struct usb_interface_cache {
 struct usb_host_config {
        struct usb_config_descriptor    desc;
-        char *string;
+        char *string;           /* iConfiguration string, if present */
        /* the interfaces associated with this configuration,
         * stored in no particular order */
        struct usb_interface *interface[USB_MAXINTERFACES];
@@ -248,7 +250,7 @@ int __usb_get_extra_descriptor(char *buffer, unsigned size,
        __usb_get_extra_descriptor((ifpoint)->extra,(ifpoint)->extralen,\
                type,(void**)ptr)
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 struct usb_operations;
@@ -268,7 +270,8 @@ struct usb_bus {
        unsigned is_b_host:1;           /* true during some HNP roleswitches */
        unsigned b_hnp_enable:1;        /* OTG: did A-Host enable HNP? */
-        int devnum_next;                /* Next open device number in round-robin allocation */
+        int devnum_next;                /* Next open device number in
+                                         * round-robin allocation */
        struct usb_devmap devmap;       /* device address allocation map */
        struct usb_operations *op;      /* Operations (specific to the HC) */
@@ -289,15 +292,16 @@ struct usb_bus {
        struct dentry *usbfs_dentry;    /* usbfs dentry entry for the bus */
        struct class_device *class_dev; /* class device for this bus */
-        struct kref kref;               /* handles reference counting this bus */
+        struct kref kref;               /* reference counting for this bus */
-        void (*release)(struct usb_bus *bus);   /* function to destroy this bus's memory */
+        void (*release)(struct usb_bus *bus);
 #if defined(CONFIG_USB_MON)
        struct mon_bus *mon_bus;        /* non-null when associated */
        int monitored;                  /* non-zero when monitored */
 #endif
 };
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 /* This is arbitrary.
 * From USB 2.0 spec Table 11-13, offset 7, a hub can
@@ -326,7 +330,8 @@ struct usb_device {
        struct semaphore serialize;
-        unsigned int toggle[2];         /* one bit for each endpoint ([0] = IN, [1] = OUT) */
+        unsigned int toggle[2];         /* one bit for each endpoint
+                                         * ([0] = IN, [1] = OUT) */
        struct usb_device *parent;      /* our hub, unless we're the root */
        struct usb_bus *bus;            /* Bus we're part of */
@@ -343,12 +348,14 @@ struct usb_device {
        char **rawdescriptors;          /* Raw descriptors for each config */
-        int have_langid;                /* whether string_langid is valid yet */
+        int have_langid;                /* whether string_langid is valid */
        int string_langid;              /* language ID for strings */
-        char *product;
+        /* static strings from the device */
-        char *manufacturer;
+        char *product;                  /* iProduct string, if present */
-        char *serial;                   /* static strings from the device */
+        char *manufacturer;             /* iManufacturer string, if present */
+        char *serial;                   /* iSerialNumber string, if present */
        struct list_head filelist;
        struct class_device *class_dev;
        struct dentry *usbfs_dentry;    /* usbfs dentry entry for the device */
@@ -440,22 +447,31 @@ extern struct usb_host_interface *usb_altnum_to_altsetting(
 * USB 2.0 root hubs (EHCI host controllers) will get one path ID if they are
 * high speed, and a different one if they are full or low speed.
 */
-static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
+static inline int usb_make_path (struct usb_device *dev, char *buf,
+                size_t size)
 {
        int actual;
-        actual = snprintf (buf, size, "usb-%s-%s", dev->bus->bus_name, dev->devpath);
+        actual = snprintf (buf, size, "usb-%s-%s", dev->bus->bus_name,
+                        dev->devpath);
        return (actual >= (int)size) ? -1 : actual;
 }
 /*-------------------------------------------------------------------------*/
-#define USB_DEVICE_ID_MATCH_DEVICE              (USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_PRODUCT)
+#define USB_DEVICE_ID_MATCH_DEVICE \
-#define USB_DEVICE_ID_MATCH_DEV_RANGE           (USB_DEVICE_ID_MATCH_DEV_LO | USB_DEVICE_ID_MATCH_DEV_HI)
+                (USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_PRODUCT)
-#define USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION  (USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_DEV_RANGE)
+#define USB_DEVICE_ID_MATCH_DEV_RANGE \
+                (USB_DEVICE_ID_MATCH_DEV_LO | USB_DEVICE_ID_MATCH_DEV_HI)
+#define USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION \
+                (USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_DEV_RANGE)
 #define USB_DEVICE_ID_MATCH_DEV_INFO \
-        (USB_DEVICE_ID_MATCH_DEV_CLASS | USB_DEVICE_ID_MATCH_DEV_SUBCLASS | USB_DEVICE_ID_MATCH_DEV_PROTOCOL)
+                (USB_DEVICE_ID_MATCH_DEV_CLASS | \
+                USB_DEVICE_ID_MATCH_DEV_SUBCLASS | \
+                USB_DEVICE_ID_MATCH_DEV_PROTOCOL)
 #define USB_DEVICE_ID_MATCH_INT_INFO \
-        (USB_DEVICE_ID_MATCH_INT_CLASS | USB_DEVICE_ID_MATCH_INT_SUBCLASS | USB_DEVICE_ID_MATCH_INT_PROTOCOL)
+                (USB_DEVICE_ID_MATCH_INT_CLASS | \
+                USB_DEVICE_ID_MATCH_INT_SUBCLASS | \
+                USB_DEVICE_ID_MATCH_INT_PROTOCOL)
 /**
 * USB_DEVICE - macro used to describe a specific usb device
@@ -466,9 +482,11 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
 * specific device.
 */
 #define USB_DEVICE(vend,prod) \
-        .match_flags = USB_DEVICE_ID_MATCH_DEVICE, .idVendor = (vend), .idProduct = (prod)
+        .match_flags = USB_DEVICE_ID_MATCH_DEVICE, .idVendor = (vend), \
+                        .idProduct = (prod)
 /**
- * USB_DEVICE_VER - macro used to describe a specific usb device with a version range
+ * USB_DEVICE_VER - macro used to describe a specific usb device with a
+ *              version range
 * @vend: the 16 bit USB Vendor ID
 * @prod: the 16 bit USB Product ID
 * @lo: the bcdDevice_lo value
@@ -478,7 +496,9 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
 * specific device, with a version range.
 */
 #define USB_DEVICE_VER(vend,prod,lo,hi) \
-        .match_flags = USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION, .idVendor = (vend), .idProduct = (prod), .bcdDevice_lo = (lo), .bcdDevice_hi = (hi)
+        .match_flags = USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION, \
+        .idVendor = (vend), .idProduct = (prod), \
+        .bcdDevice_lo = (lo), .bcdDevice_hi = (hi)
 /**
 * USB_DEVICE_INFO - macro used to describe a class of usb devices
@@ -490,7 +510,8 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
 * specific class of devices.
 */
 #define USB_DEVICE_INFO(cl,sc,pr) \
-        .match_flags = USB_DEVICE_ID_MATCH_DEV_INFO, .bDeviceClass = (cl), .bDeviceSubClass = (sc), .bDeviceProtocol = (pr)
+        .match_flags = USB_DEVICE_ID_MATCH_DEV_INFO, .bDeviceClass = (cl), \
+        .bDeviceSubClass = (sc), .bDeviceProtocol = (pr)
 /**
 * USB_INTERFACE_INFO - macro used to describe a class of usb interfaces 
@@ -502,9 +523,10 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, size_t size)
 * specific class of interfaces.
 */
 #define USB_INTERFACE_INFO(cl,sc,pr) \
-        .match_flags = USB_DEVICE_ID_MATCH_INT_INFO, .bInterfaceClass = (cl), .bInterfaceSubClass = (sc), .bInterfaceProtocol = (pr)
+        .match_flags = USB_DEVICE_ID_MATCH_INT_INFO, .bInterfaceClass = (cl), \
+        .bInterfaceSubClass = (sc), .bInterfaceProtocol = (pr)
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 /**
 * struct usb_driver - identifies USB driver to usbcore
@@ -557,7 +579,8 @@ struct usb_driver {
        void (*disconnect) (struct usb_interface *intf);
-        int (*ioctl) (struct usb_interface *intf, unsigned int code, void *buf);
+        int (*ioctl) (struct usb_interface *intf, unsigned int code,
+                        void *buf);
        int (*suspend) (struct usb_interface *intf, pm_message_t message);
        int (*resume) (struct usb_interface *intf);
@@ -572,10 +595,8 @@ extern struct bus_type usb_bus_type;
 /**
 * struct usb_class_driver - identifies a USB driver that wants to use the USB major number
- * @name: devfs name for this driver.  Will also be used by the driver
+ * @name: the usb class device name for this driver.  Will show up in sysfs.
- *      class code to create a usb class device.
 * @fops: pointer to the struct file_operations of this driver.
- * @mode: the mode for the devfs file to be created for this driver.
 * @minor_base: the start of the minor range for this driver.
 *
 * This structure is used for the usb_register_dev() and
@@ -585,8 +606,7 @@ extern struct bus_type usb_bus_type;
 struct usb_class_driver {
        char *name;
        struct file_operations *fops;
-        mode_t mode;
+        int minor_base;
-        int minor_base; 
 };
 /*
@@ -603,7 +623,7 @@ extern void usb_deregister_dev(struct usb_interface *intf,
 extern int usb_disabled(void);
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 /*
 * URB support, for asynchronous request completions
@@ -613,12 +633,14 @@ extern int usb_disabled(void);
 * urb->transfer_flags:
 */
 #define URB_SHORT_NOT_OK        0x0001  /* report short reads as errors */
-#define URB_ISO_ASAP            0x0002  /* iso-only, urb->start_frame ignored */
+#define URB_ISO_ASAP            0x0002  /* iso-only, urb->start_frame
+                                         * ignored */
 #define URB_NO_TRANSFER_DMA_MAP 0x0004  /* urb->transfer_dma valid on submit */
 #define URB_NO_SETUP_DMA_MAP    0x0008  /* urb->setup_dma valid on submit */
 #define URB_NO_FSBR             0x0020  /* UHCI-specific */
-#define URB_ZERO_PACKET         0x0040  /* Finish bulk OUTs with short packet */
+#define URB_ZERO_PACKET         0x0040  /* Finish bulk OUT with short packet */
-#define URB_NO_INTERRUPT        0x0080  /* HINT: no non-error interrupt needed */
+#define URB_NO_INTERRUPT        0x0080  /* HINT: no non-error interrupt
+                                         * needed */
 struct usb_iso_packet_descriptor {
        unsigned int offset;
@@ -806,7 +828,8 @@ struct urb
        u8 reject;                      /* submissions will fail */
        /* public, documented fields in the urb that can be used by drivers */
-        struct list_head urb_list;      /* list head for use by the urb owner */
+        struct list_head urb_list;      /* list head for use by the urb's
+                                         * current owner */
        struct usb_device *dev;         /* (in) pointer to associated device */
        unsigned int pipe;              /* (in) pipe information */
        int status;                     /* (return) non-ISO status */
@@ -819,14 +842,16 @@ struct urb
        dma_addr_t setup_dma;           /* (in) dma addr for setup_packet */
        int start_frame;                /* (modify) start frame (ISO) */
        int number_of_packets;          /* (in) number of ISO packets */
-        int interval;                   /* (modify) transfer interval (INT/ISO) */
+        int interval;                   /* (modify) transfer interval
+                                         * (INT/ISO) */
        int error_count;                /* (return) number of ISO errors */
        void *context;                  /* (in) context for completion */
        usb_complete_t complete;        /* (in) completion routine */
-        struct usb_iso_packet_descriptor iso_frame_desc[0];     /* (in) ISO ONLY */
+        struct usb_iso_packet_descriptor iso_frame_desc[0];
+                                        /* (in) ISO ONLY */
 };
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 /**
 * usb_fill_control_urb - initializes a control urb
@@ -974,11 +999,6 @@ extern int usb_bulk_msg(struct usb_device *usb_dev, unsigned int pipe,
        void *data, int len, int *actual_length,
        int timeout);
-/* selective suspend/resume */
-extern int usb_suspend_device(struct usb_device *dev, pm_message_t message);
-extern int usb_resume_device(struct usb_device *dev);
 /* wrappers around usb_control_msg() for the most common standard requests */
 extern int usb_get_descriptor(struct usb_device *dev, unsigned char desctype,
        unsigned char descindex, void *buf, int size);
@@ -1056,7 +1076,7 @@ void usb_sg_cancel (struct usb_sg_request *io);
 void usb_sg_wait (struct usb_sg_request *io);
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 /*
 * For various legacy reasons, Linux has a small cookie that's paired with
@@ -1097,23 +1117,34 @@ void usb_sg_wait (struct usb_sg_request *io);
 /* The D0/D1 toggle bits ... USE WITH CAUTION (they're almost hcd-internal) */
 #define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> (ep)) & 1)
 #define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << (ep)))
-#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << (ep))) | ((bit) << (ep)))
+#define usb_settoggle(dev, ep, out, bit) \
+                ((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << (ep))) | \
+                 ((bit) << (ep)))
-static inline unsigned int __create_pipe(struct usb_device *dev, unsigned int endpoint)
+static inline unsigned int __create_pipe(struct usb_device *dev,
+                unsigned int endpoint)
 {
        return (dev->devnum << 8) | (endpoint << 15);
 }
 /* Create various pipes... */
-#define usb_sndctrlpipe(dev,endpoint)   ((PIPE_CONTROL << 30) | __create_pipe(dev,endpoint))
+#define usb_sndctrlpipe(dev,endpoint)   \
-#define usb_rcvctrlpipe(dev,endpoint)   ((PIPE_CONTROL << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+        ((PIPE_CONTROL << 30) | __create_pipe(dev,endpoint))
-#define usb_sndisocpipe(dev,endpoint)   ((PIPE_ISOCHRONOUS << 30) | __create_pipe(dev,endpoint))
+#define usb_rcvctrlpipe(dev,endpoint)   \
-#define usb_rcvisocpipe(dev,endpoint)   ((PIPE_ISOCHRONOUS << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+        ((PIPE_CONTROL << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_sndbulkpipe(dev,endpoint)   ((PIPE_BULK << 30) | __create_pipe(dev,endpoint))
+#define usb_sndisocpipe(dev,endpoint)   \
-#define usb_rcvbulkpipe(dev,endpoint)   ((PIPE_BULK << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+        ((PIPE_ISOCHRONOUS << 30) | __create_pipe(dev,endpoint))
-#define usb_sndintpipe(dev,endpoint)    ((PIPE_INTERRUPT << 30) | __create_pipe(dev,endpoint))
+#define usb_rcvisocpipe(dev,endpoint)   \
-#define usb_rcvintpipe(dev,endpoint)    ((PIPE_INTERRUPT << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+        ((PIPE_ISOCHRONOUS << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndbulkpipe(dev,endpoint)   \
+        ((PIPE_BULK << 30) | __create_pipe(dev,endpoint))
+#define usb_rcvbulkpipe(dev,endpoint)   \
+        ((PIPE_BULK << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndintpipe(dev,endpoint)    \
+        ((PIPE_INTERRUPT << 30) | __create_pipe(dev,endpoint))
+#define usb_rcvintpipe(dev,endpoint)    \
+        ((PIPE_INTERRUPT << 30) | __create_pipe(dev,endpoint) | USB_DIR_IN)
 /*-------------------------------------------------------------------------*/
@@ -1137,17 +1168,29 @@ usb_maxpacket(struct usb_device *udev, int pipe, int is_out)
        return le16_to_cpu(ep->desc.wMaxPacketSize);
 }
-/* -------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
+/* Events from the usb core */
+#define USB_DEVICE_ADD          0x0001
+#define USB_DEVICE_REMOVE       0x0002
+#define USB_BUS_ADD             0x0003
+#define USB_BUS_REMOVE          0x0004
+extern void usb_register_notify(struct notifier_block *nb);
+extern void usb_unregister_notify(struct notifier_block *nb);
 #ifdef DEBUG
-#define dbg(format, arg...) printk(KERN_DEBUG "%s: " format "\n" , __FILE__ , ## arg)
+#define dbg(format, arg...) printk(KERN_DEBUG "%s: " format "\n" , \
+        __FILE__ , ## arg)
 #else
 #define dbg(format, arg...) do {} while (0)
 #endif
-#define err(format, arg...) printk(KERN_ERR "%s: " format "\n" , __FILE__ , ## arg)
+#define err(format, arg...) printk(KERN_ERR "%s: " format "\n" , \
-#define info(format, arg...) printk(KERN_INFO "%s: " format "\n" , __FILE__ , ## arg)
+        __FILE__ , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n" , __FILE__ , ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format "\n" , \
+        __FILE__ , ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n" , \
+        __FILE__ , ## arg)
 #endif  /* __KERNEL__ */
diff --git a/include/linux/usb_otg.h b/include/linux/usb_otg.h
index c6683146e9b0..f827f6e203c2 100644
--- a/include/linux/usb_otg.h
+++ b/include/linux/usb_otg.h
@@ -63,6 +63,10 @@ struct otg_transceiver {
        int     (*set_power)(struct otg_transceiver *otg,
                                unsigned mA);
+        /* for non-OTG B devices: set transceiver into suspend mode */
+        int     (*set_suspend)(struct otg_transceiver *otg,
+                                int suspend);
        /* for B devices only:  start session with A-Host */
        int     (*start_srp)(struct otg_transceiver *otg);
@@ -108,6 +112,15 @@ otg_set_power(struct otg_transceiver *otg, unsigned mA)
 }
 static inline int
+otg_set_suspend(struct otg_transceiver *otg, int suspend)
+{
+        if (otg->set_suspend != NULL)
+                return otg->set_suspend(otg, suspend);
+        else
+                return 0;
+}
+static inline int
 otg_start_srp(struct otg_transceiver *otg)
 {
        return otg->start_srp(otg);
diff --git a/include/linux/usbdevice_fs.h b/include/linux/usbdevice_fs.h
index 9facf733800c..8859f0b41543 100644
--- a/include/linux/usbdevice_fs.h
+++ b/include/linux/usbdevice_fs.h
@@ -140,6 +140,12 @@ struct usbdevfs_urb32 {
        compat_caddr_t usercontext; /* unused */
        struct usbdevfs_iso_packet_desc iso_frame_desc[0];
 };
+struct usbdevfs_ioctl32 {
+        s32 ifno;
+        s32 ioctl_code;
+        compat_caddr_t data;
+};
 #endif
 #define USBDEVFS_CONTROL           _IOWR('U', 0, struct usbdevfs_ctrltransfer)
@@ -160,6 +166,7 @@ struct usbdevfs_urb32 {
 #define USBDEVFS_RELEASEINTERFACE  _IOR('U', 16, unsigned int)
 #define USBDEVFS_CONNECTINFO       _IOW('U', 17, struct usbdevfs_connectinfo)
 #define USBDEVFS_IOCTL             _IOWR('U', 18, struct usbdevfs_ioctl)
+#define USBDEVFS_IOCTL32           _IOWR('U', 18, struct usbdevfs_ioctl32)
 #define USBDEVFS_HUB_PORTINFO      _IOR('U', 19, struct usbdevfs_hub_portinfo)
 #define USBDEVFS_RESET             _IO('U', 20)
 #define USBDEVFS_CLEAR_HALT        _IOR('U', 21, unsigned int)
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 3701a0673d2c..1d5577b2b752 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -32,10 +32,14 @@ struct vm_struct {
 *      Highlevel APIs for driver use
 */
 extern void *vmalloc(unsigned long size);
+extern void *vmalloc_node(unsigned long size, int node);
 extern void *vmalloc_exec(unsigned long size);
 extern void *vmalloc_32(unsigned long size);
 extern void *__vmalloc(unsigned long size, gfp_t gfp_mask, pgprot_t prot);
-extern void *__vmalloc_area(struct vm_struct *area, gfp_t gfp_mask, pgprot_t prot);
+extern void *__vmalloc_area(struct vm_struct *area, gfp_t gfp_mask,
+                                pgprot_t prot);
+extern void *__vmalloc_node(unsigned long size, gfp_t gfp_mask,
+                                pgprot_t prot, int node);
 extern void vfree(void *addr);
 extern void *vmap(struct page **pages, unsigned int count,
@@ -48,6 +52,8 @@ extern void vunmap(void *addr);
 extern struct vm_struct *get_vm_area(unsigned long size, unsigned long flags);
 extern struct vm_struct *__get_vm_area(unsigned long size, unsigned long flags,
                                        unsigned long start, unsigned long end);
+extern struct vm_struct *get_vm_area_node(unsigned long size,
+                                        unsigned long flags, int node);
 extern struct vm_struct *remove_vm_area(void *addr);
 extern struct vm_struct *__remove_vm_area(void *addr);
 extern int map_vm_area(struct vm_struct *area, pgprot_t prot,
diff --git a/include/linux/zutil.h b/include/linux/zutil.h
index fdfd5ed41ec4..ee0c59cf2136 100644
--- a/include/linux/zutil.h
+++ b/include/linux/zutil.h
@@ -15,7 +15,6 @@
 #include <linux/zlib.h>
 #include <linux/string.h>
-#include <linux/errno.h>
 #include <linux/kernel.h>
 typedef unsigned char  uch;
diff --git a/include/net/ax25.h b/include/net/ax25.h
index 30bb4a893237..2250a18b0cbb 100644
--- a/include/net/ax25.h
+++ b/include/net/ax25.h
@@ -237,8 +237,7 @@ typedef struct ax25_cb {
 static __inline__ void ax25_cb_put(ax25_cb *ax25)
 {
        if (atomic_dec_and_test(&ax25->refcount)) {
-                if (ax25->digipeat)
+                kfree(ax25->digipeat);
-                        kfree(ax25->digipeat);
                kfree(ax25);
        }
 }
diff --git a/include/net/netrom.h b/include/net/netrom.h
index a6bf6e0f606a..a5ee53bce62f 100644
--- a/include/net/netrom.h
+++ b/include/net/netrom.h
@@ -136,8 +136,7 @@ static __inline__ void nr_node_put(struct nr_node *nr_node)
 static __inline__ void nr_neigh_put(struct nr_neigh *nr_neigh)
 {
        if (atomic_dec_and_test(&nr_neigh->refcount)) {
-                if (nr_neigh->digipeat != NULL)
+                kfree(nr_neigh->digipeat);
-                        kfree(nr_neigh->digipeat);
                kfree(nr_neigh);
        }
 }
diff --git a/include/net/sctp/user.h b/include/net/sctp/user.h
index 1c5f19f995ad..f1c3bc54526a 100644
--- a/include/net/sctp/user.h
+++ b/include/net/sctp/user.h
@@ -171,10 +171,10 @@ struct sctp_sndrcvinfo {
 */
 enum sctp_sinfo_flags {
-        MSG_UNORDERED = 1,  /* Send/receive message unordered. */
+        SCTP_UNORDERED = 1,  /* Send/receive message unordered. */
-        MSG_ADDR_OVER = 2,  /* Override the primary destination. */
+        SCTP_ADDR_OVER = 2,  /* Override the primary destination. */
-        MSG_ABORT=4,        /* Send an ABORT message to the peer. */
+        SCTP_ABORT=4,        /* Send an ABORT message to the peer. */
-        /* MSG_EOF is already defined per socket.h */
+        SCTP_EOF=MSG_FIN,    /* Initiate graceful shutdown process. */  
 };
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
index c8592c7e8eaa..e788bbc5657d 100644
--- a/include/pcmcia/ss.h
+++ b/include/pcmcia/ss.h
@@ -17,6 +17,7 @@
 #include <linux/config.h>
 #include <linux/device.h>
+#include <linux/sched.h>        /* task_struct, completion */
 #include <pcmcia/cs_types.h>
 #include <pcmcia/cs.h>
diff --git a/include/rdma/ib_user_cm.h b/include/rdma/ib_user_cm.h
index 3037588b8464..19be116047f6 100644
--- a/include/rdma/ib_user_cm.h
+++ b/include/rdma/ib_user_cm.h
@@ -38,7 +38,7 @@
 #include <linux/types.h>
-#define IB_USER_CM_ABI_VERSION 3
+#define IB_USER_CM_ABI_VERSION 4
 enum {
        IB_USER_CM_CMD_CREATE_ID,
@@ -84,6 +84,7 @@ struct ib_ucm_create_id_resp {
 struct ib_ucm_destroy_id {
        __u64 response;
        __u32 id;
+        __u32 reserved;
 };
 struct ib_ucm_destroy_id_resp {
@@ -93,6 +94,7 @@ struct ib_ucm_destroy_id_resp {
 struct ib_ucm_attr_id {
        __u64 response;
        __u32 id;
+        __u32 reserved;
 };
 struct ib_ucm_attr_id_resp {
@@ -164,6 +166,7 @@ struct ib_ucm_listen {
        __be64 service_id;
        __be64 service_mask;
        __u32 id;
+        __u32 reserved;
 };
 struct ib_ucm_establish {
@@ -219,7 +222,7 @@ struct ib_ucm_req {
        __u8  rnr_retry_count;
        __u8  max_cm_retries;
        __u8  srq;
-        __u8  reserved[1];
+        __u8  reserved[5];
 };
 struct ib_ucm_rep {
@@ -236,6 +239,7 @@ struct ib_ucm_rep {
        __u8  flow_control;
        __u8  rnr_retry_count;
        __u8  srq;
+        __u8  reserved[4];
 };
 struct ib_ucm_info {
@@ -245,7 +249,7 @@ struct ib_ucm_info {
        __u64 data;
        __u8  info_len;
        __u8  data_len;
-        __u8  reserved[2];
+        __u8  reserved[6];
 };
 struct ib_ucm_mra {
@@ -273,6 +277,7 @@ struct ib_ucm_sidr_req {
        __u16 pkey;
        __u8  len;
        __u8  max_cm_retries;
+        __u8  reserved[4];
 };
 struct ib_ucm_sidr_rep {
@@ -284,7 +289,7 @@ struct ib_ucm_sidr_rep {
        __u64 data;
        __u8  info_len;
        __u8  data_len;
-        __u8  reserved[2];
+        __u8  reserved[6];
 };
 /*
 * event notification ABI structures.
@@ -295,7 +300,7 @@ struct ib_ucm_event_get {
        __u64 info;
        __u8  data_len;
        __u8  info_len;
-        __u8  reserved[2];
+        __u8  reserved[6];
 };
 struct ib_ucm_req_event_resp {
@@ -315,6 +320,7 @@ struct ib_ucm_req_event_resp {
        __u8  rnr_retry_count;
        __u8  srq;
        __u8  port;
+        __u8  reserved[7];
 };
 struct ib_ucm_rep_event_resp {
@@ -329,7 +335,7 @@ struct ib_ucm_rep_event_resp {
        __u8  flow_control;
        __u8  rnr_retry_count;
        __u8  srq;
-        __u8  reserved[1];
+        __u8  reserved[5];
 };
 struct ib_ucm_rej_event_resp {
@@ -374,6 +380,7 @@ struct ib_ucm_event_resp {
        __u32 id;
        __u32 event;
        __u32 present;
+        __u32 reserved;
        union {
                struct ib_ucm_req_event_resp req_resp;
                struct ib_ucm_rep_event_resp rep_resp;
diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h
index b361172b576c..6cb1e2788d8b 100644
--- a/include/scsi/scsi.h
+++ b/include/scsi/scsi.h
@@ -116,6 +116,9 @@ extern const char *const scsi_device_types[MAX_SCSI_DEVICE_CODE];
 /* values for service action in */
 #define SAI_READ_CAPACITY_16  0x10
+/* Values for T10/04-262r7 */
+#define ATA_16                0x85      /* 16-byte pass-thru */
+#define ATA_12                0xa1      /* 12-byte pass-thru */
 /*
 *  SCSI Architecture Model (SAM) Status codes. Taken from SAM-3 draft
diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h
index e6b61fab66dd..7529f4388bb4 100644
--- a/include/scsi/scsi_cmnd.h
+++ b/include/scsi/scsi_cmnd.h
@@ -4,6 +4,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/list.h>
 #include <linux/types.h>
+#include <linux/timer.h>
 struct request;
 struct scatterlist;
diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h
index b0d445437372..c04405bead2d 100644
--- a/include/scsi/scsi_transport_fc.h
+++ b/include/scsi/scsi_transport_fc.h
@@ -28,6 +28,7 @@
 #define SCSI_TRANSPORT_FC_H
 #include <linux/config.h>
+#include <linux/sched.h>
 struct scsi_transport_template;
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 14cb2718cb77..46e3c0bf3c94 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -1055,6 +1055,7 @@ typedef struct {
        unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
        unsigned char ca0102_chip;  /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
        unsigned char ca0108_chip;  /* Audigy 2 Value */
+        unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */
        unsigned char ca0151_chip;  /* P16V */
        unsigned char spk71;        /* Has 7.1 speakers */
        unsigned char sblive51;     /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */