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-rw-r--r--include/asm-i386/hw_irq.h3
-rw-r--r--include/asm-i386/hypertransport.h42
-rw-r--r--include/asm-i386/io_apic.h42
-rw-r--r--include/asm-i386/mach-default/irq_vectors_limits.h5
-rw-r--r--include/asm-i386/msi.h23
-rw-r--r--include/asm-i386/msidef.h47
-rw-r--r--include/asm-ia64/machvec.h21
-rw-r--r--include/asm-ia64/machvec_sn2.h9
-rw-r--r--include/asm-ia64/msi.h29
-rw-r--r--include/asm-parisc/agp.h25
-rw-r--r--include/asm-parisc/assembly.h6
-rw-r--r--include/asm-parisc/cacheflush.h30
-rw-r--r--include/asm-parisc/compat.h4
-rw-r--r--include/asm-parisc/dma.h7
-rw-r--r--include/asm-parisc/futex.h71
-rw-r--r--include/asm-parisc/io.h2
-rw-r--r--include/asm-parisc/iosapic.h53
-rw-r--r--include/asm-parisc/irq.h6
-rw-r--r--include/asm-parisc/mckinley.h9
-rw-r--r--include/asm-parisc/page.h22
-rw-r--r--include/asm-parisc/param.h10
-rw-r--r--include/asm-parisc/parisc-device.h5
-rw-r--r--include/asm-parisc/pci.h5
-rw-r--r--include/asm-parisc/prefetch.h39
-rw-r--r--include/asm-parisc/processor.h39
-rw-r--r--include/asm-parisc/ropes.h322
-rw-r--r--include/asm-parisc/serial.h16
-rw-r--r--include/asm-parisc/spinlock.h115
-rw-r--r--include/asm-powerpc/firmware.h67
-rw-r--r--include/asm-powerpc/immap_qe.h477
-rw-r--r--include/asm-powerpc/qe.h457
-rw-r--r--include/asm-powerpc/qe_ic.h64
-rw-r--r--include/asm-powerpc/system.h4
-rw-r--r--include/asm-powerpc/ucc.h84
-rw-r--r--include/asm-powerpc/ucc_fast.h243
-rw-r--r--include/asm-powerpc/ucc_slow.h289
-rw-r--r--include/asm-powerpc/xmon.h26
-rw-r--r--include/asm-x86_64/hardirq.h3
-rw-r--r--include/asm-x86_64/hw_irq.h8
-rw-r--r--include/asm-x86_64/hypertransport.h42
-rw-r--r--include/asm-x86_64/io_apic.h43
-rw-r--r--include/asm-x86_64/irq.h7
-rw-r--r--include/asm-x86_64/msi.h24
-rw-r--r--include/asm-x86_64/msidef.h47
-rw-r--r--include/linux/Kbuild7
-rw-r--r--include/linux/ac97_codec.h5
-rw-r--r--include/linux/audit.h3
-rw-r--r--include/linux/debug_locks.h2
-rw-r--r--include/linux/dlm.h302
-rw-r--r--include/linux/dlm_device.h86
-rw-r--r--include/linux/fs.h2
-rw-r--r--include/linux/fsl_devices.h65
-rw-r--r--include/linux/gfs2_ondisk.h443
-rw-r--r--include/linux/hardirq.h7
-rw-r--r--include/linux/htirq.h15
-rw-r--r--include/linux/in.h1
-rw-r--r--include/linux/ip.h9
-rw-r--r--include/linux/ipc.h3
-rw-r--r--include/linux/ipsec.h3
-rw-r--r--include/linux/irq.h57
-rw-r--r--include/linux/libata.h9
-rw-r--r--include/linux/lm_interface.h273
-rw-r--r--include/linux/lock_dlm_plock.h41
-rw-r--r--include/linux/lockd/lockd.h61
-rw-r--r--include/linux/lockd/share.h3
-rw-r--r--include/linux/lockd/sm_inter.h5
-rw-r--r--include/linux/msi.h49
-rw-r--r--include/linux/netfilter_bridge/ebt_mark_t.h12
-rw-r--r--include/linux/netfilter_ipv4.h2
-rw-r--r--include/linux/nfsd/const.h20
-rw-r--r--include/linux/nfsd/export.h21
-rw-r--r--include/linux/nfsd/nfsd.h5
-rw-r--r--include/linux/nfsd/xdr.h2
-rw-r--r--include/linux/nfsd/xdr3.h2
-rw-r--r--include/linux/nfsd/xdr4.h2
-rw-r--r--include/linux/notifier.h43
-rw-r--r--include/linux/pci.h7
-rw-r--r--include/linux/pci_regs.h21
-rw-r--r--include/linux/rcupdate.h7
-rw-r--r--include/linux/scx200.h2
-rw-r--r--include/linux/slab.h26
-rw-r--r--include/linux/sound.h2
-rw-r--r--include/linux/srcu.h53
-rw-r--r--include/linux/sunrpc/auth.h3
-rw-r--r--include/linux/sunrpc/cache.h11
-rw-r--r--include/linux/sunrpc/msg_prot.h40
-rw-r--r--include/linux/sunrpc/svc.h97
-rw-r--r--include/linux/sunrpc/svcauth.h1
-rw-r--r--include/linux/sunrpc/svcsock.h3
-rw-r--r--include/linux/sunrpc/xprt.h8
-rw-r--r--include/linux/tifm.h158
-rw-r--r--include/linux/utsname.h17
-rw-r--r--include/linux/wavefront.h675
-rw-r--r--include/linux/xfrm.h3
94 files changed, 4308 insertions, 1278 deletions
diff --git a/include/asm-i386/hw_irq.h b/include/asm-i386/hw_irq.h
index 87e5a351d881..88f02a073561 100644
--- a/include/asm-i386/hw_irq.h
+++ b/include/asm-i386/hw_irq.h
@@ -17,8 +17,6 @@
17#include <asm/irq.h> 17#include <asm/irq.h>
18#include <asm/sections.h> 18#include <asm/sections.h>
19 19
20struct hw_interrupt_type;
21
22#define NMI_VECTOR 0x02 20#define NMI_VECTOR 0x02
23 21
24/* 22/*
@@ -30,7 +28,6 @@ struct hw_interrupt_type;
30 28
31extern u8 irq_vector[NR_IRQ_VECTORS]; 29extern u8 irq_vector[NR_IRQ_VECTORS];
32#define IO_APIC_VECTOR(irq) (irq_vector[irq]) 30#define IO_APIC_VECTOR(irq) (irq_vector[irq])
33#define AUTO_ASSIGN -1
34 31
35extern void (*interrupt[NR_IRQS])(void); 32extern void (*interrupt[NR_IRQS])(void);
36 33
diff --git a/include/asm-i386/hypertransport.h b/include/asm-i386/hypertransport.h
new file mode 100644
index 000000000000..c16c6ff4bdd7
--- /dev/null
+++ b/include/asm-i386/hypertransport.h
@@ -0,0 +1,42 @@
1#ifndef ASM_HYPERTRANSPORT_H
2#define ASM_HYPERTRANSPORT_H
3
4/*
5 * Constants for x86 Hypertransport Interrupts.
6 */
7
8#define HT_IRQ_LOW_BASE 0xf8000000
9
10#define HT_IRQ_LOW_VECTOR_SHIFT 16
11#define HT_IRQ_LOW_VECTOR_MASK 0x00ff0000
12#define HT_IRQ_LOW_VECTOR(v) (((v) << HT_IRQ_LOW_VECTOR_SHIFT) & HT_IRQ_LOW_VECTOR_MASK)
13
14#define HT_IRQ_LOW_DEST_ID_SHIFT 8
15#define HT_IRQ_LOW_DEST_ID_MASK 0x0000ff00
16#define HT_IRQ_LOW_DEST_ID(v) (((v) << HT_IRQ_LOW_DEST_ID_SHIFT) & HT_IRQ_LOW_DEST_ID_MASK)
17
18#define HT_IRQ_LOW_DM_PHYSICAL 0x0000000
19#define HT_IRQ_LOW_DM_LOGICAL 0x0000040
20
21#define HT_IRQ_LOW_RQEOI_EDGE 0x0000000
22#define HT_IRQ_LOW_RQEOI_LEVEL 0x0000020
23
24
25#define HT_IRQ_LOW_MT_FIXED 0x0000000
26#define HT_IRQ_LOW_MT_ARBITRATED 0x0000004
27#define HT_IRQ_LOW_MT_SMI 0x0000008
28#define HT_IRQ_LOW_MT_NMI 0x000000c
29#define HT_IRQ_LOW_MT_INIT 0x0000010
30#define HT_IRQ_LOW_MT_STARTUP 0x0000014
31#define HT_IRQ_LOW_MT_EXTINT 0x0000018
32#define HT_IRQ_LOW_MT_LINT1 0x000008c
33#define HT_IRQ_LOW_MT_LINT0 0x0000098
34
35#define HT_IRQ_LOW_IRQ_MASKED 0x0000001
36
37
38#define HT_IRQ_HIGH_DEST_ID_SHIFT 0
39#define HT_IRQ_HIGH_DEST_ID_MASK 0x00ffffff
40#define HT_IRQ_HIGH_DEST_ID(v) ((((v) >> 8) << HT_IRQ_HIGH_DEST_ID_SHIFT) & HT_IRQ_HIGH_DEST_ID_MASK)
41
42#endif /* ASM_HYPERTRANSPORT_H */
diff --git a/include/asm-i386/io_apic.h b/include/asm-i386/io_apic.h
index 5d309275a1dc..276ea7e8144a 100644
--- a/include/asm-i386/io_apic.h
+++ b/include/asm-i386/io_apic.h
@@ -12,46 +12,6 @@
12 12
13#ifdef CONFIG_X86_IO_APIC 13#ifdef CONFIG_X86_IO_APIC
14 14
15#ifdef CONFIG_PCI_MSI
16static inline int use_pci_vector(void) {return 1;}
17static inline void disable_edge_ioapic_vector(unsigned int vector) { }
18static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { }
19static inline void end_edge_ioapic_vector (unsigned int vector) { }
20#define startup_level_ioapic startup_level_ioapic_vector
21#define shutdown_level_ioapic mask_IO_APIC_vector
22#define enable_level_ioapic unmask_IO_APIC_vector
23#define disable_level_ioapic mask_IO_APIC_vector
24#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
25#define end_level_ioapic end_level_ioapic_vector
26#define set_ioapic_affinity set_ioapic_affinity_vector
27
28#define startup_edge_ioapic startup_edge_ioapic_vector
29#define shutdown_edge_ioapic disable_edge_ioapic_vector
30#define enable_edge_ioapic unmask_IO_APIC_vector
31#define disable_edge_ioapic disable_edge_ioapic_vector
32#define ack_edge_ioapic ack_edge_ioapic_vector
33#define end_edge_ioapic end_edge_ioapic_vector
34#else
35static inline int use_pci_vector(void) {return 0;}
36static inline void disable_edge_ioapic_irq(unsigned int irq) { }
37static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { }
38static inline void end_edge_ioapic_irq (unsigned int irq) { }
39#define startup_level_ioapic startup_level_ioapic_irq
40#define shutdown_level_ioapic mask_IO_APIC_irq
41#define enable_level_ioapic unmask_IO_APIC_irq
42#define disable_level_ioapic mask_IO_APIC_irq
43#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
44#define end_level_ioapic end_level_ioapic_irq
45#define set_ioapic_affinity set_ioapic_affinity_irq
46
47#define startup_edge_ioapic startup_edge_ioapic_irq
48#define shutdown_edge_ioapic disable_edge_ioapic_irq
49#define enable_edge_ioapic unmask_IO_APIC_irq
50#define disable_edge_ioapic disable_edge_ioapic_irq
51#define ack_edge_ioapic ack_edge_ioapic_irq
52#define end_edge_ioapic end_edge_ioapic_irq
53#endif
54
55#define IO_APIC_BASE(idx) \ 15#define IO_APIC_BASE(idx) \
56 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \ 16 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
57 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK))) 17 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
@@ -219,6 +179,4 @@ extern int (*ioapic_renumber_irq)(int ioapic, int irq);
219static inline void disable_ioapic_setup(void) { } 179static inline void disable_ioapic_setup(void) { }
220#endif 180#endif
221 181
222extern int assign_irq_vector(int irq);
223
224#endif 182#endif
diff --git a/include/asm-i386/mach-default/irq_vectors_limits.h b/include/asm-i386/mach-default/irq_vectors_limits.h
index b330026e6f7f..7f161e760be6 100644
--- a/include/asm-i386/mach-default/irq_vectors_limits.h
+++ b/include/asm-i386/mach-default/irq_vectors_limits.h
@@ -1,10 +1,6 @@
1#ifndef _ASM_IRQ_VECTORS_LIMITS_H 1#ifndef _ASM_IRQ_VECTORS_LIMITS_H
2#define _ASM_IRQ_VECTORS_LIMITS_H 2#define _ASM_IRQ_VECTORS_LIMITS_H
3 3
4#ifdef CONFIG_PCI_MSI
5#define NR_IRQS FIRST_SYSTEM_VECTOR
6#define NR_IRQ_VECTORS NR_IRQS
7#else
8#ifdef CONFIG_X86_IO_APIC 4#ifdef CONFIG_X86_IO_APIC
9#define NR_IRQS 224 5#define NR_IRQS 224
10# if (224 >= 32 * NR_CPUS) 6# if (224 >= 32 * NR_CPUS)
@@ -16,6 +12,5 @@
16#define NR_IRQS 16 12#define NR_IRQS 16
17#define NR_IRQ_VECTORS NR_IRQS 13#define NR_IRQ_VECTORS NR_IRQS
18#endif 14#endif
19#endif
20 15
21#endif /* _ASM_IRQ_VECTORS_LIMITS_H */ 16#endif /* _ASM_IRQ_VECTORS_LIMITS_H */
diff --git a/include/asm-i386/msi.h b/include/asm-i386/msi.h
deleted file mode 100644
index b11c4b7dfaef..000000000000
--- a/include/asm-i386/msi.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
4 */
5
6#ifndef ASM_MSI_H
7#define ASM_MSI_H
8
9#include <asm/desc.h>
10#include <mach_apic.h>
11
12#define LAST_DEVICE_VECTOR (FIRST_SYSTEM_VECTOR - 1)
13#define MSI_TARGET_CPU_SHIFT 12
14
15extern struct msi_ops msi_apic_ops;
16
17static inline int msi_arch_init(void)
18{
19 msi_register(&msi_apic_ops);
20 return 0;
21}
22
23#endif /* ASM_MSI_H */
diff --git a/include/asm-i386/msidef.h b/include/asm-i386/msidef.h
new file mode 100644
index 000000000000..5b8acddb70fb
--- /dev/null
+++ b/include/asm-i386/msidef.h
@@ -0,0 +1,47 @@
1#ifndef ASM_MSIDEF_H
2#define ASM_MSIDEF_H
3
4/*
5 * Constants for Intel APIC based MSI messages.
6 */
7
8/*
9 * Shifts for MSI data
10 */
11
12#define MSI_DATA_VECTOR_SHIFT 0
13#define MSI_DATA_VECTOR_MASK 0x000000ff
14#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & MSI_DATA_VECTOR_MASK)
15
16#define MSI_DATA_DELIVERY_MODE_SHIFT 8
17#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
18#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
19
20#define MSI_DATA_LEVEL_SHIFT 14
21#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
22#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
23
24#define MSI_DATA_TRIGGER_SHIFT 15
25#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
26#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
27
28/*
29 * Shift/mask fields for msi address
30 */
31
32#define MSI_ADDR_BASE_HI 0
33#define MSI_ADDR_BASE_LO 0xfee00000
34
35#define MSI_ADDR_DEST_MODE_SHIFT 2
36#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
37#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
38
39#define MSI_ADDR_REDIRECTION_SHIFT 3
40#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) /* dedicated cpu */
41#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) /* lowest priority */
42
43#define MSI_ADDR_DEST_ID_SHIFT 12
44#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
45#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MSI_ADDR_DEST_ID_MASK)
46
47#endif /* ASM_MSIDEF_H */
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
index 15b545a897a4..90cba967df35 100644
--- a/include/asm-ia64/machvec.h
+++ b/include/asm-ia64/machvec.h
@@ -20,6 +20,7 @@ struct page;
20struct mm_struct; 20struct mm_struct;
21struct pci_bus; 21struct pci_bus;
22struct task_struct; 22struct task_struct;
23struct pci_dev;
23 24
24typedef void ia64_mv_setup_t (char **); 25typedef void ia64_mv_setup_t (char **);
25typedef void ia64_mv_cpu_init_t (void); 26typedef void ia64_mv_cpu_init_t (void);
@@ -75,7 +76,9 @@ typedef unsigned char ia64_mv_readb_relaxed_t (const volatile void __iomem *);
75typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *); 76typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *);
76typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *); 77typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *);
77typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *); 78typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *);
78typedef int ia64_mv_msi_init_t (void); 79
80typedef int ia64_mv_setup_msi_irq_t (unsigned int irq, struct pci_dev *pdev);
81typedef void ia64_mv_teardown_msi_irq_t (unsigned int irq);
79 82
80static inline void 83static inline void
81machvec_noop (void) 84machvec_noop (void)
@@ -154,7 +157,8 @@ extern void machvec_tlb_migrate_finish (struct mm_struct *);
154# define platform_readl_relaxed ia64_mv.readl_relaxed 157# define platform_readl_relaxed ia64_mv.readl_relaxed
155# define platform_readq_relaxed ia64_mv.readq_relaxed 158# define platform_readq_relaxed ia64_mv.readq_relaxed
156# define platform_migrate ia64_mv.migrate 159# define platform_migrate ia64_mv.migrate
157# define platform_msi_init ia64_mv.msi_init 160# define platform_setup_msi_irq ia64_mv.setup_msi_irq
161# define platform_teardown_msi_irq ia64_mv.teardown_msi_irq
158# endif 162# endif
159 163
160/* __attribute__((__aligned__(16))) is required to make size of the 164/* __attribute__((__aligned__(16))) is required to make size of the
@@ -204,7 +208,8 @@ struct ia64_machine_vector {
204 ia64_mv_readl_relaxed_t *readl_relaxed; 208 ia64_mv_readl_relaxed_t *readl_relaxed;
205 ia64_mv_readq_relaxed_t *readq_relaxed; 209 ia64_mv_readq_relaxed_t *readq_relaxed;
206 ia64_mv_migrate_t *migrate; 210 ia64_mv_migrate_t *migrate;
207 ia64_mv_msi_init_t *msi_init; 211 ia64_mv_setup_msi_irq_t *setup_msi_irq;
212 ia64_mv_teardown_msi_irq_t *teardown_msi_irq;
208} __attribute__((__aligned__(16))); /* align attrib? see above comment */ 213} __attribute__((__aligned__(16))); /* align attrib? see above comment */
209 214
210#define MACHVEC_INIT(name) \ 215#define MACHVEC_INIT(name) \
@@ -250,7 +255,8 @@ struct ia64_machine_vector {
250 platform_readl_relaxed, \ 255 platform_readl_relaxed, \
251 platform_readq_relaxed, \ 256 platform_readq_relaxed, \
252 platform_migrate, \ 257 platform_migrate, \
253 platform_msi_init, \ 258 platform_setup_msi_irq, \
259 platform_teardown_msi_irq, \
254} 260}
255 261
256extern struct ia64_machine_vector ia64_mv; 262extern struct ia64_machine_vector ia64_mv;
@@ -404,8 +410,11 @@ extern int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size
404#ifndef platform_migrate 410#ifndef platform_migrate
405# define platform_migrate machvec_noop_task 411# define platform_migrate machvec_noop_task
406#endif 412#endif
407#ifndef platform_msi_init 413#ifndef platform_setup_msi_irq
408# define platform_msi_init ((ia64_mv_msi_init_t*)NULL) 414# define platform_setup_msi_irq ((ia64_mv_setup_msi_irq_t*)NULL)
415#endif
416#ifndef platform_teardown_msi_irq
417# define platform_teardown_msi_irq ((ia64_mv_teardown_msi_irq_t*)NULL)
409#endif 418#endif
410 419
411#endif /* _ASM_IA64_MACHVEC_H */ 420#endif /* _ASM_IA64_MACHVEC_H */
diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h
index cf724dc79d8c..c54b165b1c17 100644
--- a/include/asm-ia64/machvec_sn2.h
+++ b/include/asm-ia64/machvec_sn2.h
@@ -67,7 +67,8 @@ extern ia64_mv_dma_sync_sg_for_device sn_dma_sync_sg_for_device;
67extern ia64_mv_dma_mapping_error sn_dma_mapping_error; 67extern ia64_mv_dma_mapping_error sn_dma_mapping_error;
68extern ia64_mv_dma_supported sn_dma_supported; 68extern ia64_mv_dma_supported sn_dma_supported;
69extern ia64_mv_migrate_t sn_migrate; 69extern ia64_mv_migrate_t sn_migrate;
70extern ia64_mv_msi_init_t sn_msi_init; 70extern ia64_mv_setup_msi_irq_t sn_setup_msi_irq;
71extern ia64_mv_teardown_msi_irq_t sn_teardown_msi_irq;
71 72
72 73
73/* 74/*
@@ -120,9 +121,11 @@ extern ia64_mv_msi_init_t sn_msi_init;
120#define platform_dma_supported sn_dma_supported 121#define platform_dma_supported sn_dma_supported
121#define platform_migrate sn_migrate 122#define platform_migrate sn_migrate
122#ifdef CONFIG_PCI_MSI 123#ifdef CONFIG_PCI_MSI
123#define platform_msi_init sn_msi_init 124#define platform_setup_msi_irq sn_setup_msi_irq
125#define platform_teardown_msi_irq sn_teardown_msi_irq
124#else 126#else
125#define platform_msi_init ((ia64_mv_msi_init_t*)NULL) 127#define platform_setup_msi_irq ((ia64_mv_setup_msi_irq_t*)NULL)
128#define platform_teardown_msi_irq ((ia64_mv_teardown_msi_irq_t*)NULL)
126#endif 129#endif
127 130
128#include <asm/sn/io.h> 131#include <asm/sn/io.h>
diff --git a/include/asm-ia64/msi.h b/include/asm-ia64/msi.h
deleted file mode 100644
index bb92b0dbde2f..000000000000
--- a/include/asm-ia64/msi.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
4 */
5
6#ifndef ASM_MSI_H
7#define ASM_MSI_H
8
9#define NR_VECTORS NR_IRQS
10#define FIRST_DEVICE_VECTOR IA64_FIRST_DEVICE_VECTOR
11#define LAST_DEVICE_VECTOR IA64_LAST_DEVICE_VECTOR
12static inline void set_intr_gate (int nr, void *func) {}
13#define IO_APIC_VECTOR(irq) (irq)
14#define ack_APIC_irq ia64_eoi
15#define MSI_TARGET_CPU_SHIFT 4
16
17extern struct msi_ops msi_apic_ops;
18
19static inline int msi_arch_init(void)
20{
21 if (platform_msi_init)
22 return platform_msi_init();
23
24 /* default ops for most ia64 platforms */
25 msi_register(&msi_apic_ops);
26 return 0;
27}
28
29#endif /* ASM_MSI_H */
diff --git a/include/asm-parisc/agp.h b/include/asm-parisc/agp.h
new file mode 100644
index 000000000000..9f61d4eb6c01
--- /dev/null
+++ b/include/asm-parisc/agp.h
@@ -0,0 +1,25 @@
1#ifndef _ASM_PARISC_AGP_H
2#define _ASM_PARISC_AGP_H
3
4/*
5 * PARISC specific AGP definitions.
6 * Copyright (c) 2006 Kyle McMartin <kyle@parisc-linux.org>
7 *
8 */
9
10#define map_page_into_agp(page) /* nothing */
11#define unmap_page_from_agp(page) /* nothing */
12#define flush_agp_mappings() /* nothing */
13#define flush_agp_cache() mb()
14
15/* Convert a physical address to an address suitable for the GART. */
16#define phys_to_gart(x) (x)
17#define gart_to_phys(x) (x)
18
19/* GATT allocation. Returns/accepts GATT kernel virtual address. */
20#define alloc_gatt_pages(order) \
21 ((char *)__get_free_pages(GFP_KERNEL, (order)))
22#define free_gatt_pages(table, order) \
23 free_pages((unsigned long)(table), (order))
24
25#endif /* _ASM_PARISC_AGP_H */
diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h
index 1a7bfe699e0c..5a1e0e8b1c32 100644
--- a/include/asm-parisc/assembly.h
+++ b/include/asm-parisc/assembly.h
@@ -29,7 +29,8 @@
29#define LDREGX ldd,s 29#define LDREGX ldd,s
30#define LDREGM ldd,mb 30#define LDREGM ldd,mb
31#define STREGM std,ma 31#define STREGM std,ma
32#define SHRREG shrd 32#define SHRREG shrd
33#define SHLREG shld
33#define RP_OFFSET 16 34#define RP_OFFSET 16
34#define FRAME_SIZE 128 35#define FRAME_SIZE 128
35#define CALLEE_REG_FRAME_SIZE 144 36#define CALLEE_REG_FRAME_SIZE 144
@@ -39,7 +40,8 @@
39#define LDREGX ldwx,s 40#define LDREGX ldwx,s
40#define LDREGM ldwm 41#define LDREGM ldwm
41#define STREGM stwm 42#define STREGM stwm
42#define SHRREG shr 43#define SHRREG shr
44#define SHLREG shlw
43#define RP_OFFSET 20 45#define RP_OFFSET 20
44#define FRAME_SIZE 64 46#define FRAME_SIZE 64
45#define CALLEE_REG_FRAME_SIZE 128 47#define CALLEE_REG_FRAME_SIZE 128
diff --git a/include/asm-parisc/cacheflush.h b/include/asm-parisc/cacheflush.h
index 0b459cdfbd6f..2bc41f2e0271 100644
--- a/include/asm-parisc/cacheflush.h
+++ b/include/asm-parisc/cacheflush.h
@@ -191,16 +191,38 @@ flush_anon_page(struct page *page, unsigned long vmaddr)
191} 191}
192#define ARCH_HAS_FLUSH_ANON_PAGE 192#define ARCH_HAS_FLUSH_ANON_PAGE
193 193
194static inline void 194#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
195flush_kernel_dcache_page(struct page *page) 195void flush_kernel_dcache_page_addr(void *addr);
196static inline void flush_kernel_dcache_page(struct page *page)
196{ 197{
197 flush_kernel_dcache_page_asm(page_address(page)); 198 flush_kernel_dcache_page_addr(page_address(page));
198} 199}
199#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
200 200
201#ifdef CONFIG_DEBUG_RODATA 201#ifdef CONFIG_DEBUG_RODATA
202void mark_rodata_ro(void); 202void mark_rodata_ro(void);
203#endif 203#endif
204 204
205#ifdef CONFIG_PA8X00
206/* Only pa8800, pa8900 needs this */
207#define ARCH_HAS_KMAP
208
209void kunmap_parisc(void *addr);
210
211static inline void *kmap(struct page *page)
212{
213 might_sleep();
214 return page_address(page);
215}
216
217#define kunmap(page) kunmap_parisc(page_address(page))
218
219#define kmap_atomic(page, idx) page_address(page)
220
221#define kunmap_atomic(addr, idx) kunmap_parisc(addr)
222
223#define kmap_atomic_pfn(pfn, idx) page_address(pfn_to_page(pfn))
224#define kmap_atomic_to_page(ptr) virt_to_page(ptr)
225#endif
226
205#endif /* _PARISC_CACHEFLUSH_H */ 227#endif /* _PARISC_CACHEFLUSH_H */
206 228
diff --git a/include/asm-parisc/compat.h b/include/asm-parisc/compat.h
index 71b4eeea205a..fe8579023531 100644
--- a/include/asm-parisc/compat.h
+++ b/include/asm-parisc/compat.h
@@ -5,7 +5,7 @@
5 */ 5 */
6#include <linux/types.h> 6#include <linux/types.h>
7#include <linux/sched.h> 7#include <linux/sched.h>
8#include <linux/personality.h> 8#include <linux/thread_info.h>
9 9
10#define COMPAT_USER_HZ 100 10#define COMPAT_USER_HZ 100
11 11
@@ -152,7 +152,7 @@ static __inline__ void __user *compat_alloc_user_space(long len)
152 152
153static inline int __is_compat_task(struct task_struct *t) 153static inline int __is_compat_task(struct task_struct *t)
154{ 154{
155 return personality(t->personality) == PER_LINUX32; 155 return test_ti_thread_flag(t->thread_info, TIF_32BIT);
156} 156}
157 157
158static inline int is_compat_task(void) 158static inline int is_compat_task(void)
diff --git a/include/asm-parisc/dma.h b/include/asm-parisc/dma.h
index 9979c3cb3745..da2cf373e31c 100644
--- a/include/asm-parisc/dma.h
+++ b/include/asm-parisc/dma.h
@@ -72,18 +72,13 @@
72#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 72#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
73#define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) 73#define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
74 74
75extern spinlock_t dma_spin_lock;
76
77static __inline__ unsigned long claim_dma_lock(void) 75static __inline__ unsigned long claim_dma_lock(void)
78{ 76{
79 unsigned long flags; 77 return 0;
80 spin_lock_irqsave(&dma_spin_lock, flags);
81 return flags;
82} 78}
83 79
84static __inline__ void release_dma_lock(unsigned long flags) 80static __inline__ void release_dma_lock(unsigned long flags)
85{ 81{
86 spin_unlock_irqrestore(&dma_spin_lock, flags);
87} 82}
88 83
89 84
diff --git a/include/asm-parisc/futex.h b/include/asm-parisc/futex.h
index 6a332a9f099c..d84bbb283fd1 100644
--- a/include/asm-parisc/futex.h
+++ b/include/asm-parisc/futex.h
@@ -1,6 +1,71 @@
1#ifndef _ASM_FUTEX_H 1#ifndef _ASM_PARISC_FUTEX_H
2#define _ASM_FUTEX_H 2#define _ASM_PARISC_FUTEX_H
3 3
4#include <asm-generic/futex.h> 4#ifdef __KERNEL__
5 5
6#include <linux/futex.h>
7#include <asm/errno.h>
8#include <asm/uaccess.h>
9
10static inline int
11futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
12{
13 int op = (encoded_op >> 28) & 7;
14 int cmp = (encoded_op >> 24) & 15;
15 int oparg = (encoded_op << 8) >> 20;
16 int cmparg = (encoded_op << 20) >> 20;
17 int oldval = 0, ret;
18 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
19 oparg = 1 << oparg;
20
21 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
22 return -EFAULT;
23
24 inc_preempt_count();
25
26 switch (op) {
27 case FUTEX_OP_SET:
28 case FUTEX_OP_ADD:
29 case FUTEX_OP_OR:
30 case FUTEX_OP_ANDN:
31 case FUTEX_OP_XOR:
32 default:
33 ret = -ENOSYS;
34 }
35
36 dec_preempt_count();
37
38 if (!ret) {
39 switch (cmp) {
40 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
41 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
42 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
43 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
44 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
45 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
46 default: ret = -ENOSYS;
47 }
48 }
49 return ret;
50}
51
52/* Non-atomic version */
53static inline int
54futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
55{
56 int err = 0;
57 int uval;
58
59 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
60 return -EFAULT;
61
62 err = get_user(uval, uaddr);
63 if (err) return -EFAULT;
64 if (uval == oldval)
65 err = put_user(newval, uaddr);
66 if (err) return -EFAULT;
67 return uval;
68}
69
70#endif
6#endif 71#endif
diff --git a/include/asm-parisc/io.h b/include/asm-parisc/io.h
index b9eb245b8874..c1963ce19dd2 100644
--- a/include/asm-parisc/io.h
+++ b/include/asm-parisc/io.h
@@ -134,7 +134,7 @@ extern inline void __iomem * ioremap(unsigned long offset, unsigned long size)
134} 134}
135#define ioremap_nocache(off, sz) ioremap((off), (sz)) 135#define ioremap_nocache(off, sz) ioremap((off), (sz))
136 136
137extern void iounmap(void __iomem *addr); 137extern void iounmap(const volatile void __iomem *addr);
138 138
139static inline unsigned char __raw_readb(const volatile void __iomem *addr) 139static inline unsigned char __raw_readb(const volatile void __iomem *addr)
140{ 140{
diff --git a/include/asm-parisc/iosapic.h b/include/asm-parisc/iosapic.h
deleted file mode 100644
index 613390e6805c..000000000000
--- a/include/asm-parisc/iosapic.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2** This file is private to iosapic driver.
3** If stuff needs to be used by another driver, move it to a common file.
4**
5** WARNING: fields most data structures here are ordered to make sure
6** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
7*/
8
9
10/*
11** I/O SAPIC init function
12** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
13** Call setup as part of per instance initialization.
14** (ie *not* init_module() function unless only one is present.)
15** fixup_irq is to initialize PCI IRQ line support and
16** virtualize pcidev->irq value. To be called by pci_fixup_bus().
17*/
18extern void *iosapic_register(unsigned long hpa);
19extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
20
21
22#ifdef __IA64__
23/*
24** PA: PIB (Processor Interrupt Block) is handled by Runway bus adapter.
25** and is hardcoded to 0xfeeNNNN0 where NNNN is id_eid field.
26**
27** IA64: PIB is handled by "Local SAPIC" (integrated in the processor).
28*/
29struct local_sapic_info {
30 struct local_sapic_info *lsi_next; /* point to next CPU info */
31 int *lsi_cpu_id; /* point to logical CPU id */
32 unsigned long *lsi_id_eid; /* point to IA-64 CPU id */
33 int *lsi_status; /* point to CPU status */
34 void *lsi_private; /* point to special info */
35};
36
37/*
38** "root" data structure which ties everything together.
39** Should always be able to start with sapic_root and locate
40** the desired information.
41*/
42struct sapic_info {
43 struct sapic_info *si_next; /* info is per cell */
44 int si_cellid; /* cell id */
45 unsigned int si_status; /* status */
46 char *si_pib_base; /* intr blk base address */
47 local_sapic_info_t *si_local_info;
48 io_sapic_info_t *si_io_info;
49 extint_info_t *si_extint_info;/* External Intr info */
50};
51
52#endif /* IA64 */
53
diff --git a/include/asm-parisc/irq.h b/include/asm-parisc/irq.h
index 5cae260615a2..399c81981ed5 100644
--- a/include/asm-parisc/irq.h
+++ b/include/asm-parisc/irq.h
@@ -31,7 +31,7 @@ static __inline__ int irq_canonicalize(int irq)
31 return (irq == 2) ? 9 : irq; 31 return (irq == 2) ? 9 : irq;
32} 32}
33 33
34struct hw_interrupt_type; 34struct irq_chip;
35 35
36/* 36/*
37 * Some useful "we don't have to do anything here" handlers. Should 37 * Some useful "we don't have to do anything here" handlers. Should
@@ -39,6 +39,8 @@ struct hw_interrupt_type;
39 */ 39 */
40void no_ack_irq(unsigned int irq); 40void no_ack_irq(unsigned int irq);
41void no_end_irq(unsigned int irq); 41void no_end_irq(unsigned int irq);
42void cpu_ack_irq(unsigned int irq);
43void cpu_end_irq(unsigned int irq);
42 44
43extern int txn_alloc_irq(unsigned int nbits); 45extern int txn_alloc_irq(unsigned int nbits);
44extern int txn_claim_irq(int); 46extern int txn_claim_irq(int);
@@ -46,7 +48,7 @@ extern unsigned int txn_alloc_data(unsigned int);
46extern unsigned long txn_alloc_addr(unsigned int); 48extern unsigned long txn_alloc_addr(unsigned int);
47extern unsigned long txn_affinity_addr(unsigned int irq, int cpu); 49extern unsigned long txn_affinity_addr(unsigned int irq, int cpu);
48 50
49extern int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type *, void *); 51extern int cpu_claim_irq(unsigned int irq, struct irq_chip *, void *);
50extern int cpu_check_affinity(unsigned int irq, cpumask_t *dest); 52extern int cpu_check_affinity(unsigned int irq, cpumask_t *dest);
51 53
52/* soft power switch support (power.c) */ 54/* soft power switch support (power.c) */
diff --git a/include/asm-parisc/mckinley.h b/include/asm-parisc/mckinley.h
new file mode 100644
index 000000000000..d1ea6f12915e
--- /dev/null
+++ b/include/asm-parisc/mckinley.h
@@ -0,0 +1,9 @@
1#ifndef ASM_PARISC_MCKINLEY_H
2#define ASM_PARISC_MCKINLEY_H
3#ifdef __KERNEL__
4
5/* declared in arch/parisc/kernel/setup.c */
6extern struct proc_dir_entry * proc_mckinley_root;
7
8#endif /*__KERNEL__*/
9#endif /*ASM_PARISC_MCKINLEY_H*/
diff --git a/include/asm-parisc/page.h b/include/asm-parisc/page.h
index 57d6d82756dd..3567208191e3 100644
--- a/include/asm-parisc/page.h
+++ b/include/asm-parisc/page.h
@@ -26,24 +26,10 @@
26 26
27struct page; 27struct page;
28 28
29extern void purge_kernel_dcache_page(unsigned long); 29void copy_user_page_asm(void *to, void *from);
30extern void copy_user_page_asm(void *to, void *from); 30void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
31extern void clear_user_page_asm(void *page, unsigned long vaddr); 31 struct page *pg);
32 32void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
33static inline void
34copy_user_page(void *vto, void *vfrom, unsigned long vaddr, struct page *pg)
35{
36 copy_user_page_asm(vto, vfrom);
37 flush_kernel_dcache_page_asm(vto);
38 /* XXX: ppc flushes icache too, should we? */
39}
40
41static inline void
42clear_user_page(void *page, unsigned long vaddr, struct page *pg)
43{
44 purge_kernel_dcache_page((unsigned long)page);
45 clear_user_page_asm(page, vaddr);
46}
47 33
48/* 34/*
49 * These are used to make use of C type-checking.. 35 * These are used to make use of C type-checking..
diff --git a/include/asm-parisc/param.h b/include/asm-parisc/param.h
index 07cb9b93cfe2..32e03d877858 100644
--- a/include/asm-parisc/param.h
+++ b/include/asm-parisc/param.h
@@ -2,13 +2,9 @@
2#define _ASMPARISC_PARAM_H 2#define _ASMPARISC_PARAM_H
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5# ifdef CONFIG_PA20 5#define HZ CONFIG_HZ
6# define HZ 1000 /* Faster machines */ 6#define USER_HZ 100 /* some user API use "ticks" */
7# else 7#define CLOCKS_PER_SEC (USER_HZ) /* like times() */
8# define HZ 100 /* Internal kernel timer frequency */
9# endif
10# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
11# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
12#endif 8#endif
13 9
14#ifndef HZ 10#ifndef HZ
diff --git a/include/asm-parisc/parisc-device.h b/include/asm-parisc/parisc-device.h
index 1d247e32a608..e12624d8941d 100644
--- a/include/asm-parisc/parisc-device.h
+++ b/include/asm-parisc/parisc-device.h
@@ -1,3 +1,6 @@
1#ifndef _ASM_PARISC_PARISC_DEVICE_H_
2#define _ASM_PARISC_PARISC_DEVICE_H_
3
1#include <linux/device.h> 4#include <linux/device.h>
2 5
3struct parisc_device { 6struct parisc_device {
@@ -57,3 +60,5 @@ parisc_get_drvdata(struct parisc_device *d)
57} 60}
58 61
59extern struct bus_type parisc_bus_type; 62extern struct bus_type parisc_bus_type;
63
64#endif /*_ASM_PARISC_PARISC_DEVICE_H_*/
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index 8b631f47eb25..7b8ad118d2fe 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -293,4 +293,9 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
293 /* We don't need to penalize isa irq's */ 293 /* We don't need to penalize isa irq's */
294} 294}
295 295
296static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
297{
298 return channel ? 15 : 14;
299}
300
296#endif /* __ASM_PARISC_PCI_H */ 301#endif /* __ASM_PARISC_PCI_H */
diff --git a/include/asm-parisc/prefetch.h b/include/asm-parisc/prefetch.h
new file mode 100644
index 000000000000..5d021726fa33
--- /dev/null
+++ b/include/asm-parisc/prefetch.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-parisc/prefetch.h
3 *
4 * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
5 * In addition, many implementations do hardware prefetching of both
6 * instructions and data.
7 *
8 * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
9 * to gr0 but not in a way that Linux can use. If the load would cause an
10 * interruption (eg due to prefetching 0), it is suppressed on PA2.0
11 * processors, but not on 7300LC.
12 *
13 */
14
15#ifndef __ASM_PARISC_PREFETCH_H
16#define __ASM_PARISC_PREFETCH_H
17
18#ifndef __ASSEMBLY__
19#ifdef CONFIG_PREFETCH
20
21#define ARCH_HAS_PREFETCH
22extern inline void prefetch(const void *addr)
23{
24 __asm__("ldw 0(%0), %%r0" : : "r" (addr));
25}
26
27/* LDD is a PA2.0 addition. */
28#ifdef CONFIG_PA20
29#define ARCH_HAS_PREFETCHW
30extern inline void prefetchw(const void *addr)
31{
32 __asm__("ldd 0(%0), %%r0" : : "r" (addr));
33}
34#endif /* CONFIG_PA20 */
35
36#endif /* CONFIG_PREFETCH */
37#endif /* __ASSEMBLY__ */
38
39#endif /* __ASM_PARISC_PROCESSOR_H */
diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h
index b73626f040da..fd7866dc8c83 100644
--- a/include/asm-parisc/processor.h
+++ b/include/asm-parisc/processor.h
@@ -9,6 +9,8 @@
9#define __ASM_PARISC_PROCESSOR_H 9#define __ASM_PARISC_PROCESSOR_H
10 10
11#ifndef __ASSEMBLY__ 11#ifndef __ASSEMBLY__
12#include <asm/prefetch.h> /* lockdep.h needs <linux/prefetch.h> */
13
12#include <linux/threads.h> 14#include <linux/threads.h>
13#include <linux/spinlock_types.h> 15#include <linux/spinlock_types.h>
14 16
@@ -276,7 +278,7 @@ on downward growing arches, it looks like this:
276 */ 278 */
277 279
278#ifdef __LP64__ 280#ifdef __LP64__
279#define USER_WIDE_MODE (personality(current->personality) == PER_LINUX) 281#define USER_WIDE_MODE (!test_thread_flag(TIF_32BIT))
280#else 282#else
281#define USER_WIDE_MODE 0 283#define USER_WIDE_MODE 0
282#endif 284#endif
@@ -328,33 +330,20 @@ extern unsigned long get_wchan(struct task_struct *p);
328#define KSTK_EIP(tsk) ((tsk)->thread.regs.iaoq[0]) 330#define KSTK_EIP(tsk) ((tsk)->thread.regs.iaoq[0])
329#define KSTK_ESP(tsk) ((tsk)->thread.regs.gr[30]) 331#define KSTK_ESP(tsk) ((tsk)->thread.regs.gr[30])
330 332
333#define cpu_relax() barrier()
331 334
332/* 335/* Used as a macro to identify the combined VIPT/PIPT cached
333 * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book. 336 * CPUs which require a guarantee of coherency (no inequivalent
334 * In addition, many implementations do hardware prefetching of both 337 * aliases with different data, whether clean or not) to operate */
335 * instructions and data. 338static inline int parisc_requires_coherency(void)
336 *
337 * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
338 * to gr0 but not in a way that Linux can use. If the load would cause an
339 * interruption (eg due to prefetching 0), it is suppressed on PA2.0
340 * processors, but not on 7300LC.
341 */
342#ifdef CONFIG_PREFETCH
343#define ARCH_HAS_PREFETCH
344#define ARCH_HAS_PREFETCHW
345
346extern inline void prefetch(const void *addr)
347{
348 __asm__("ldw 0(%0), %%r0" : : "r" (addr));
349}
350
351extern inline void prefetchw(const void *addr)
352{ 339{
353 __asm__("ldd 0(%0), %%r0" : : "r" (addr)); 340#ifdef CONFIG_PA8X00
354} 341 /* FIXME: also pa8900 - when we see one */
342 return boot_cpu_data.cpu_type == mako;
343#else
344 return 0;
355#endif 345#endif
356 346}
357#define cpu_relax() barrier()
358 347
359#endif /* __ASSEMBLY__ */ 348#endif /* __ASSEMBLY__ */
360 349
diff --git a/include/asm-parisc/ropes.h b/include/asm-parisc/ropes.h
new file mode 100644
index 000000000000..5542dd00472b
--- /dev/null
+++ b/include/asm-parisc/ropes.h
@@ -0,0 +1,322 @@
1#ifndef _ASM_PARISC_ROPES_H_
2#define _ASM_PARISC_ROPES_H_
3
4#include <asm-parisc/parisc-device.h>
5
6#ifdef CONFIG_64BIT
7/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
8#define ZX1_SUPPORT
9#endif
10
11#ifdef CONFIG_PROC_FS
12/* depends on proc fs support. But costs CPU performance */
13#undef SBA_COLLECT_STATS
14#endif
15
16/*
17** The number of pdir entries to "free" before issueing
18** a read to PCOM register to flush out PCOM writes.
19** Interacts with allocation granularity (ie 4 or 8 entries
20** allocated and free'd/purged at a time might make this
21** less interesting).
22*/
23#define DELAYED_RESOURCE_CNT 16
24
25#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
26#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
27
28struct ioc {
29 void __iomem *ioc_hpa; /* I/O MMU base address */
30 char *res_map; /* resource map, bit == pdir entry */
31 u64 *pdir_base; /* physical base address */
32 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
33 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
34#ifdef ZX1_SUPPORT
35 unsigned long iovp_mask; /* help convert IOVA to IOVP */
36#endif
37 unsigned long *res_hint; /* next avail IOVP - circular search */
38 spinlock_t res_lock;
39 unsigned int res_bitshift; /* from the LEFT! */
40 unsigned int res_size; /* size of resource map in bytes */
41#ifdef SBA_HINT_SUPPORT
42/* FIXME : DMA HINTs not used */
43 unsigned long hint_mask_pdir; /* bits used for DMA hints */
44 unsigned int hint_shift_pdir;
45#endif
46#if DELAYED_RESOURCE_CNT > 0
47 int saved_cnt;
48 struct sba_dma_pair {
49 dma_addr_t iova;
50 size_t size;
51 } saved[DELAYED_RESOURCE_CNT];
52#endif
53
54#ifdef SBA_COLLECT_STATS
55#define SBA_SEARCH_SAMPLE 0x100
56 unsigned long avg_search[SBA_SEARCH_SAMPLE];
57 unsigned long avg_idx; /* current index into avg_search */
58 unsigned long used_pages;
59 unsigned long msingle_calls;
60 unsigned long msingle_pages;
61 unsigned long msg_calls;
62 unsigned long msg_pages;
63 unsigned long usingle_calls;
64 unsigned long usingle_pages;
65 unsigned long usg_calls;
66 unsigned long usg_pages;
67#endif
68 /* STUFF We don't need in performance path */
69 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
70};
71
72struct sba_device {
73 struct sba_device *next; /* list of SBA's in system */
74 struct parisc_device *dev; /* dev found in bus walk */
75 const char *name;
76 void __iomem *sba_hpa; /* base address */
77 spinlock_t sba_lock;
78 unsigned int flags; /* state/functionality enabled */
79 unsigned int hw_rev; /* HW revision of chip */
80
81 struct resource chip_resv; /* MMIO reserved for chip */
82 struct resource iommu_resv; /* MMIO reserved for iommu */
83
84 unsigned int num_ioc; /* number of on-board IOC's */
85 struct ioc ioc[MAX_IOC];
86};
87
88#define ASTRO_RUNWAY_PORT 0x582
89#define IKE_MERCED_PORT 0x803
90#define REO_MERCED_PORT 0x804
91#define REOG_MERCED_PORT 0x805
92#define PLUTO_MCKINLEY_PORT 0x880
93
94static inline int IS_ASTRO(struct parisc_device *d) {
95 return d->id.hversion == ASTRO_RUNWAY_PORT;
96}
97
98static inline int IS_IKE(struct parisc_device *d) {
99 return d->id.hversion == IKE_MERCED_PORT;
100}
101
102static inline int IS_PLUTO(struct parisc_device *d) {
103 return d->id.hversion == PLUTO_MCKINLEY_PORT;
104}
105
106#define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */
107#define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */
108#define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2)
109
110#define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
111
112#define SBA_AGPGART_COOKIE 0x0000badbadc0ffeeULL
113
114#define SBA_FUNC_ID 0x0000 /* function id */
115#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
116
117#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
118
119#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
120#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
121/* Ike's IOC's occupy functions 2 and 3 */
122#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
123
124#define IOC_CTRL 0x8 /* IOC_CTRL offset */
125#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
126#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
127#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
128#define IOC_CTRL_RM (1 << 8) /* Real Mode */
129#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
130#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
131#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
132
133/*
134** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
135** Firmware programs this stuff. Don't touch it.
136*/
137#define LMMIO_DIRECT0_BASE 0x300
138#define LMMIO_DIRECT0_MASK 0x308
139#define LMMIO_DIRECT0_ROUTE 0x310
140
141#define LMMIO_DIST_BASE 0x360
142#define LMMIO_DIST_MASK 0x368
143#define LMMIO_DIST_ROUTE 0x370
144
145#define IOS_DIST_BASE 0x390
146#define IOS_DIST_MASK 0x398
147#define IOS_DIST_ROUTE 0x3A0
148
149#define IOS_DIRECT_BASE 0x3C0
150#define IOS_DIRECT_MASK 0x3C8
151#define IOS_DIRECT_ROUTE 0x3D0
152
153/*
154** Offsets into I/O TLB (Function 2 and 3 on Ike)
155*/
156#define ROPE0_CTL 0x200 /* "regbus pci0" */
157#define ROPE1_CTL 0x208
158#define ROPE2_CTL 0x210
159#define ROPE3_CTL 0x218
160#define ROPE4_CTL 0x220
161#define ROPE5_CTL 0x228
162#define ROPE6_CTL 0x230
163#define ROPE7_CTL 0x238
164
165#define IOC_ROPE0_CFG 0x500 /* pluto only */
166#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
167
168#define HF_ENABLE 0x40
169
170#define IOC_IBASE 0x300 /* IO TLB */
171#define IOC_IMASK 0x308
172#define IOC_PCOM 0x310
173#define IOC_TCNFG 0x318
174#define IOC_PDIR_BASE 0x320
175
176/*
177** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
178** It's safer (avoid memory corruption) to keep DMA page mappings
179** equivalently sized to VM PAGE_SIZE.
180**
181** We really can't avoid generating a new mapping for each
182** page since the Virtual Coherence Index has to be generated
183** and updated for each page.
184**
185** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
186*/
187#define IOVP_SIZE PAGE_SIZE
188#define IOVP_SHIFT PAGE_SHIFT
189#define IOVP_MASK PAGE_MASK
190
191#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
192#define SBA_PERF_MASK1 0x718
193#define SBA_PERF_MASK2 0x730
194
195/*
196** Offsets into PCI Performance Counters (functions 12 and 13)
197** Controlled by PERF registers in function 2 & 3 respectively.
198*/
199#define SBA_PERF_CNT1 0x200
200#define SBA_PERF_CNT2 0x208
201#define SBA_PERF_CNT3 0x210
202
203/*
204** lba_device: Per instance Elroy data structure
205*/
206struct lba_device {
207 struct pci_hba_data hba;
208
209 spinlock_t lba_lock;
210 void *iosapic_obj;
211
212#ifdef CONFIG_64BIT
213 void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */
214#endif
215
216 int flags; /* state/functionality enabled */
217 int hw_rev; /* HW revision of chip */
218};
219
220#define ELROY_HVERS 0x782
221#define MERCURY_HVERS 0x783
222#define QUICKSILVER_HVERS 0x784
223
224static inline int IS_ELROY(struct parisc_device *d) {
225 return (d->id.hversion == ELROY_HVERS);
226}
227
228static inline int IS_MERCURY(struct parisc_device *d) {
229 return (d->id.hversion == MERCURY_HVERS);
230}
231
232static inline int IS_QUICKSILVER(struct parisc_device *d) {
233 return (d->id.hversion == QUICKSILVER_HVERS);
234}
235
236static inline int agp_mode_mercury(void __iomem *hpa) {
237 u64 bus_mode;
238
239 bus_mode = readl(hpa + 0x0620);
240 if (bus_mode & 1)
241 return 1;
242
243 return 0;
244}
245
246/*
247** I/O SAPIC init function
248** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
249** Call setup as part of per instance initialization.
250** (ie *not* init_module() function unless only one is present.)
251** fixup_irq is to initialize PCI IRQ line support and
252** virtualize pcidev->irq value. To be called by pci_fixup_bus().
253*/
254extern void *iosapic_register(unsigned long hpa);
255extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
256
257#define LBA_FUNC_ID 0x0000 /* function id */
258#define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
259#define LBA_CAPABLE 0x0030 /* capabilities register */
260
261#define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
262#define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
263
264#define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
265#define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
266#define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
267
268#define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
269#define LBA_ARB_PRI 0x0088 /* firmware sets this. */
270#define LBA_ARB_MODE 0x0090 /* firmware sets this. */
271#define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
272
273#define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
274
275#define LBA_STAT_CTL 0x0108 /* Status & Control */
276#define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
277#define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
278#define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
279#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
280
281#define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
282#define LBA_LMMIO_MASK 0x0208
283
284#define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
285#define LBA_GMMIO_MASK 0x0218
286
287#define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
288#define LBA_WLMMIO_MASK 0x0228
289
290#define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
291#define LBA_WGMMIO_MASK 0x0238
292
293#define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
294#define LBA_IOS_MASK 0x0248
295
296#define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
297#define LBA_ELMMIO_MASK 0x0258
298
299#define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
300#define LBA_EIOS_MASK 0x0268
301
302#define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
303#define LBA_DMA_CTL 0x0278 /* firmware sets this */
304
305#define LBA_IBASE 0x0300 /* SBA DMA support */
306#define LBA_IMASK 0x0308
307
308/* FIXME: ignore DMA Hint stuff until we can measure performance */
309#define LBA_HINT_CFG 0x0310
310#define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
311
312#define LBA_BUS_MODE 0x0620
313
314/* ERROR regs are needed for config cycle kluges */
315#define LBA_ERROR_CONFIG 0x0680
316#define LBA_SMART_MODE 0x20
317#define LBA_ERROR_STATUS 0x0688
318#define LBA_ROPE_CTL 0x06A0
319
320#define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
321
322#endif /*_ASM_PARISC_ROPES_H_*/
diff --git a/include/asm-parisc/serial.h b/include/asm-parisc/serial.h
index 82fd820d684f..d7e3cc60dbc3 100644
--- a/include/asm-parisc/serial.h
+++ b/include/asm-parisc/serial.h
@@ -3,20 +3,8 @@
3 */ 3 */
4 4
5/* 5/*
6 * This assumes you have a 7.272727 MHz clock for your UART. 6 * This is used for 16550-compatible UARTs
7 * The documentation implies a 40Mhz clock, and elsewhere a 7Mhz clock
8 * Clarified: 7.2727MHz on LASI. Not yet clarified for DINO
9 */ 7 */
8#define BASE_BAUD ( 1843200 / 16 )
10 9
11#define LASI_BASE_BAUD ( 7272727 / 16 )
12#define BASE_BAUD LASI_BASE_BAUD
13
14/*
15 * We don't use the ISA probing code, so these entries are just to reserve
16 * space. Some example (maximal) configurations:
17 * - 712 w/ additional Lasi & RJ16 ports: 4
18 * - J5k w/ PCI serial cards: 2 + 4 * card ~= 34
19 * A500 w/ PCI serial cards: 5 + 4 * card ~= 17
20 */
21
22#define SERIAL_PORT_DFNS 10#define SERIAL_PORT_DFNS
diff --git a/include/asm-parisc/spinlock.h b/include/asm-parisc/spinlock.h
index e1825530365d..f3d2090a18dc 100644
--- a/include/asm-parisc/spinlock.h
+++ b/include/asm-parisc/spinlock.h
@@ -56,50 +56,79 @@ static inline int __raw_spin_trylock(raw_spinlock_t *x)
56} 56}
57 57
58/* 58/*
59 * Read-write spinlocks, allowing multiple readers 59 * Read-write spinlocks, allowing multiple readers but only one writer.
60 * but only one writer. 60 * Linux rwlocks are unfair to writers; they can be starved for an indefinite
61 * time by readers. With care, they can also be taken in interrupt context.
62 *
63 * In the PA-RISC implementation, we have a spinlock and a counter.
64 * Readers use the lock to serialise their access to the counter (which
65 * records how many readers currently hold the lock).
66 * Writers hold the spinlock, preventing any readers or other writers from
67 * grabbing the rwlock.
61 */ 68 */
62 69
63#define __raw_read_trylock(lock) generic__raw_read_trylock(lock) 70/* Note that we have to ensure interrupts are disabled in case we're
64 71 * interrupted by some other code that wants to grab the same read lock */
65/* read_lock, read_unlock are pretty straightforward. Of course it somehow
66 * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */
67
68static __inline__ void __raw_read_lock(raw_rwlock_t *rw) 72static __inline__ void __raw_read_lock(raw_rwlock_t *rw)
69{ 73{
70 __raw_spin_lock(&rw->lock); 74 unsigned long flags;
71 75 local_irq_save(flags);
76 __raw_spin_lock_flags(&rw->lock, flags);
72 rw->counter++; 77 rw->counter++;
73
74 __raw_spin_unlock(&rw->lock); 78 __raw_spin_unlock(&rw->lock);
79 local_irq_restore(flags);
75} 80}
76 81
82/* Note that we have to ensure interrupts are disabled in case we're
83 * interrupted by some other code that wants to grab the same read lock */
77static __inline__ void __raw_read_unlock(raw_rwlock_t *rw) 84static __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
78{ 85{
79 __raw_spin_lock(&rw->lock); 86 unsigned long flags;
80 87 local_irq_save(flags);
88 __raw_spin_lock_flags(&rw->lock, flags);
81 rw->counter--; 89 rw->counter--;
82
83 __raw_spin_unlock(&rw->lock); 90 __raw_spin_unlock(&rw->lock);
91 local_irq_restore(flags);
84} 92}
85 93
86/* write_lock is less trivial. We optimistically grab the lock and check 94/* Note that we have to ensure interrupts are disabled in case we're
87 * if we surprised any readers. If so we release the lock and wait till 95 * interrupted by some other code that wants to grab the same read lock */
88 * they're all gone before trying again 96static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
89 * 97{
90 * Also note that we don't use the _irqsave / _irqrestore suffixes here. 98 unsigned long flags;
91 * If we're called with interrupts enabled and we've got readers (or other 99 retry:
92 * writers) in interrupt handlers someone fucked up and we'd dead-lock 100 local_irq_save(flags);
93 * sooner or later anyway. prumpf */ 101 if (__raw_spin_trylock(&rw->lock)) {
102 rw->counter++;
103 __raw_spin_unlock(&rw->lock);
104 local_irq_restore(flags);
105 return 1;
106 }
94 107
95static __inline__ void __raw_write_lock(raw_rwlock_t *rw) 108 local_irq_restore(flags);
109 /* If write-locked, we fail to acquire the lock */
110 if (rw->counter < 0)
111 return 0;
112
113 /* Wait until we have a realistic chance at the lock */
114 while (__raw_spin_is_locked(&rw->lock) && rw->counter >= 0)
115 cpu_relax();
116
117 goto retry;
118}
119
120/* Note that we have to ensure interrupts are disabled in case we're
121 * interrupted by some other code that wants to read_trylock() this lock */
122static __inline__ void __raw_write_lock(raw_rwlock_t *rw)
96{ 123{
124 unsigned long flags;
97retry: 125retry:
98 __raw_spin_lock(&rw->lock); 126 local_irq_save(flags);
127 __raw_spin_lock_flags(&rw->lock, flags);
99 128
100 if(rw->counter != 0) { 129 if (rw->counter != 0) {
101 /* this basically never happens */
102 __raw_spin_unlock(&rw->lock); 130 __raw_spin_unlock(&rw->lock);
131 local_irq_restore(flags);
103 132
104 while (rw->counter != 0) 133 while (rw->counter != 0)
105 cpu_relax(); 134 cpu_relax();
@@ -107,31 +136,37 @@ retry:
107 goto retry; 136 goto retry;
108 } 137 }
109 138
110 /* got it. now leave without unlocking */ 139 rw->counter = -1; /* mark as write-locked */
111 rw->counter = -1; /* remember we are locked */ 140 mb();
141 local_irq_restore(flags);
112} 142}
113 143
114/* write_unlock is absolutely trivial - we don't have to wait for anything */ 144static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
115
116static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
117{ 145{
118 rw->counter = 0; 146 rw->counter = 0;
119 __raw_spin_unlock(&rw->lock); 147 __raw_spin_unlock(&rw->lock);
120} 148}
121 149
122static __inline__ int __raw_write_trylock(raw_rwlock_t *rw) 150/* Note that we have to ensure interrupts are disabled in case we're
151 * interrupted by some other code that wants to read_trylock() this lock */
152static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
123{ 153{
124 __raw_spin_lock(&rw->lock); 154 unsigned long flags;
125 if (rw->counter != 0) { 155 int result = 0;
126 /* this basically never happens */ 156
127 __raw_spin_unlock(&rw->lock); 157 local_irq_save(flags);
128 158 if (__raw_spin_trylock(&rw->lock)) {
129 return 0; 159 if (rw->counter == 0) {
160 rw->counter = -1;
161 result = 1;
162 } else {
163 /* Read-locked. Oh well. */
164 __raw_spin_unlock(&rw->lock);
165 }
130 } 166 }
167 local_irq_restore(flags);
131 168
132 /* got it. now leave without unlocking */ 169 return result;
133 rw->counter = -1; /* remember we are locked */
134 return 1;
135} 170}
136 171
137/* 172/*
diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h
index 77069df92bf8..1022737f4f34 100644
--- a/include/asm-powerpc/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -14,34 +14,36 @@
14 14
15#ifdef __KERNEL__ 15#ifdef __KERNEL__
16 16
17#ifndef __ASSEMBLY__ 17#include <asm/asm-compat.h>
18 18
19/* firmware feature bitmask values */ 19/* firmware feature bitmask values */
20#define FIRMWARE_MAX_FEATURES 63 20#define FIRMWARE_MAX_FEATURES 63
21 21
22#define FW_FEATURE_PFT (1UL<<0) 22#define FW_FEATURE_PFT ASM_CONST(0x0000000000000001)
23#define FW_FEATURE_TCE (1UL<<1) 23#define FW_FEATURE_TCE ASM_CONST(0x0000000000000002)
24#define FW_FEATURE_SPRG0 (1UL<<2) 24#define FW_FEATURE_SPRG0 ASM_CONST(0x0000000000000004)
25#define FW_FEATURE_DABR (1UL<<3) 25#define FW_FEATURE_DABR ASM_CONST(0x0000000000000008)
26#define FW_FEATURE_COPY (1UL<<4) 26#define FW_FEATURE_COPY ASM_CONST(0x0000000000000010)
27#define FW_FEATURE_ASR (1UL<<5) 27#define FW_FEATURE_ASR ASM_CONST(0x0000000000000020)
28#define FW_FEATURE_DEBUG (1UL<<6) 28#define FW_FEATURE_DEBUG ASM_CONST(0x0000000000000040)
29#define FW_FEATURE_TERM (1UL<<7) 29#define FW_FEATURE_TERM ASM_CONST(0x0000000000000080)
30#define FW_FEATURE_PERF (1UL<<8) 30#define FW_FEATURE_PERF ASM_CONST(0x0000000000000100)
31#define FW_FEATURE_DUMP (1UL<<9) 31#define FW_FEATURE_DUMP ASM_CONST(0x0000000000000200)
32#define FW_FEATURE_INTERRUPT (1UL<<10) 32#define FW_FEATURE_INTERRUPT ASM_CONST(0x0000000000000400)
33#define FW_FEATURE_MIGRATE (1UL<<11) 33#define FW_FEATURE_MIGRATE ASM_CONST(0x0000000000000800)
34#define FW_FEATURE_PERFMON (1UL<<12) 34#define FW_FEATURE_PERFMON ASM_CONST(0x0000000000001000)
35#define FW_FEATURE_CRQ (1UL<<13) 35#define FW_FEATURE_CRQ ASM_CONST(0x0000000000002000)
36#define FW_FEATURE_VIO (1UL<<14) 36#define FW_FEATURE_VIO ASM_CONST(0x0000000000004000)
37#define FW_FEATURE_RDMA (1UL<<15) 37#define FW_FEATURE_RDMA ASM_CONST(0x0000000000008000)
38#define FW_FEATURE_LLAN (1UL<<16) 38#define FW_FEATURE_LLAN ASM_CONST(0x0000000000010000)
39#define FW_FEATURE_BULK (1UL<<17) 39#define FW_FEATURE_BULK ASM_CONST(0x0000000000020000)
40#define FW_FEATURE_XDABR (1UL<<18) 40#define FW_FEATURE_XDABR ASM_CONST(0x0000000000040000)
41#define FW_FEATURE_MULTITCE (1UL<<19) 41#define FW_FEATURE_MULTITCE ASM_CONST(0x0000000000080000)
42#define FW_FEATURE_SPLPAR (1UL<<20) 42#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
43#define FW_FEATURE_ISERIES (1UL<<21) 43#define FW_FEATURE_ISERIES ASM_CONST(0x0000000000200000)
44#define FW_FEATURE_LPAR (1UL<<22) 44#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
45
46#ifndef __ASSEMBLY__
45 47
46enum { 48enum {
47#ifdef CONFIG_PPC64 49#ifdef CONFIG_PPC64
@@ -94,6 +96,23 @@ extern void machine_check_fwnmi(void);
94/* This is true if we are using the firmware NMI handler (typically LPAR) */ 96/* This is true if we are using the firmware NMI handler (typically LPAR) */
95extern int fwnmi_active; 97extern int fwnmi_active;
96 98
99#else /* __ASSEMBLY__ */
100
101#define BEGIN_FW_FTR_SECTION 96:
102
103#define END_FW_FTR_SECTION(msk, val) \
10497: \
105 .section __fw_ftr_fixup,"a"; \
106 .align 3; \
107 .llong msk; \
108 .llong val; \
109 .llong 96b; \
110 .llong 97b; \
111 .previous
112
113#define END_FW_FTR_SECTION_IFSET(msk) END_FW_FTR_SECTION((msk), (msk))
114#define END_FW_FTR_SECTION_IFCLR(msk) END_FW_FTR_SECTION((msk), 0)
115
97#endif /* __ASSEMBLY__ */ 116#endif /* __ASSEMBLY__ */
98#endif /* __KERNEL__ */ 117#endif /* __KERNEL__ */
99#endif /* __ASM_POWERPC_FIRMWARE_H */ 118#endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
new file mode 100644
index 000000000000..ce12f85fff9b
--- /dev/null
+++ b/include/asm-powerpc/immap_qe.h
@@ -0,0 +1,477 @@
1/*
2 * include/asm-powerpc/immap_qe.h
3 *
4 * QUICC Engine (QE) Internal Memory Map.
5 * The Internal Memory Map for devices with QE on them. This
6 * is the superset of all QE devices (8360, etc.).
7
8 * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
9 *
10 * Authors: Shlomi Gridish <gridish@freescale.com>
11 * Li Yang <leoli@freescale.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _ASM_POWERPC_IMMAP_QE_H
19#define _ASM_POWERPC_IMMAP_QE_H
20#ifdef __KERNEL__
21
22#include <linux/kernel.h>
23
24#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
25
26/* QE I-RAM */
27struct qe_iram {
28 __be32 iadd; /* I-RAM Address Register */
29 __be32 idata; /* I-RAM Data Register */
30 u8 res0[0x78];
31} __attribute__ ((packed));
32
33/* QE Interrupt Controller */
34struct qe_ic_regs {
35 __be32 qicr;
36 __be32 qivec;
37 __be32 qripnr;
38 __be32 qipnr;
39 __be32 qipxcc;
40 __be32 qipycc;
41 __be32 qipwcc;
42 __be32 qipzcc;
43 __be32 qimr;
44 __be32 qrimr;
45 __be32 qicnr;
46 u8 res0[0x4];
47 __be32 qiprta;
48 __be32 qiprtb;
49 u8 res1[0x4];
50 __be32 qricr;
51 u8 res2[0x20];
52 __be32 qhivec;
53 u8 res3[0x1C];
54} __attribute__ ((packed));
55
56/* Communications Processor */
57struct cp_qe {
58 __be32 cecr; /* QE command register */
59 __be32 ceccr; /* QE controller configuration register */
60 __be32 cecdr; /* QE command data register */
61 u8 res0[0xA];
62 __be16 ceter; /* QE timer event register */
63 u8 res1[0x2];
64 __be16 cetmr; /* QE timers mask register */
65 __be32 cetscr; /* QE time-stamp timer control register */
66 __be32 cetsr1; /* QE time-stamp register 1 */
67 __be32 cetsr2; /* QE time-stamp register 2 */
68 u8 res2[0x8];
69 __be32 cevter; /* QE virtual tasks event register */
70 __be32 cevtmr; /* QE virtual tasks mask register */
71 __be16 cercr; /* QE RAM control register */
72 u8 res3[0x2];
73 u8 res4[0x24];
74 __be16 ceexe1; /* QE external request 1 event register */
75 u8 res5[0x2];
76 __be16 ceexm1; /* QE external request 1 mask register */
77 u8 res6[0x2];
78 __be16 ceexe2; /* QE external request 2 event register */
79 u8 res7[0x2];
80 __be16 ceexm2; /* QE external request 2 mask register */
81 u8 res8[0x2];
82 __be16 ceexe3; /* QE external request 3 event register */
83 u8 res9[0x2];
84 __be16 ceexm3; /* QE external request 3 mask register */
85 u8 res10[0x2];
86 __be16 ceexe4; /* QE external request 4 event register */
87 u8 res11[0x2];
88 __be16 ceexm4; /* QE external request 4 mask register */
89 u8 res12[0x2];
90 u8 res13[0x280];
91} __attribute__ ((packed));
92
93/* QE Multiplexer */
94struct qe_mux {
95 __be32 cmxgcr; /* CMX general clock route register */
96 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
97 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
98 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
99 __be32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
100 __be32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
101 __be32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
102 __be32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
103 __be32 cmxupcr; /* CMX UPC clock route register */
104 u8 res0[0x1C];
105} __attribute__ ((packed));
106
107/* QE Timers */
108struct qe_timers {
109 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
110 u8 res0[0x3];
111 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
112 u8 res1[0xB];
113 __be16 gtmdr1; /* Timer 1 mode register */
114 __be16 gtmdr2; /* Timer 2 mode register */
115 __be16 gtrfr1; /* Timer 1 reference register */
116 __be16 gtrfr2; /* Timer 2 reference register */
117 __be16 gtcpr1; /* Timer 1 capture register */
118 __be16 gtcpr2; /* Timer 2 capture register */
119 __be16 gtcnr1; /* Timer 1 counter */
120 __be16 gtcnr2; /* Timer 2 counter */
121 __be16 gtmdr3; /* Timer 3 mode register */
122 __be16 gtmdr4; /* Timer 4 mode register */
123 __be16 gtrfr3; /* Timer 3 reference register */
124 __be16 gtrfr4; /* Timer 4 reference register */
125 __be16 gtcpr3; /* Timer 3 capture register */
126 __be16 gtcpr4; /* Timer 4 capture register */
127 __be16 gtcnr3; /* Timer 3 counter */
128 __be16 gtcnr4; /* Timer 4 counter */
129 __be16 gtevr1; /* Timer 1 event register */
130 __be16 gtevr2; /* Timer 2 event register */
131 __be16 gtevr3; /* Timer 3 event register */
132 __be16 gtevr4; /* Timer 4 event register */
133 __be16 gtps; /* Timer 1 prescale register */
134 u8 res2[0x46];
135} __attribute__ ((packed));
136
137/* BRG */
138struct qe_brg {
139 __be32 brgc1; /* BRG1 configuration register */
140 __be32 brgc2; /* BRG2 configuration register */
141 __be32 brgc3; /* BRG3 configuration register */
142 __be32 brgc4; /* BRG4 configuration register */
143 __be32 brgc5; /* BRG5 configuration register */
144 __be32 brgc6; /* BRG6 configuration register */
145 __be32 brgc7; /* BRG7 configuration register */
146 __be32 brgc8; /* BRG8 configuration register */
147 __be32 brgc9; /* BRG9 configuration register */
148 __be32 brgc10; /* BRG10 configuration register */
149 __be32 brgc11; /* BRG11 configuration register */
150 __be32 brgc12; /* BRG12 configuration register */
151 __be32 brgc13; /* BRG13 configuration register */
152 __be32 brgc14; /* BRG14 configuration register */
153 __be32 brgc15; /* BRG15 configuration register */
154 __be32 brgc16; /* BRG16 configuration register */
155 u8 res0[0x40];
156} __attribute__ ((packed));
157
158/* SPI */
159struct spi {
160 u8 res0[0x20];
161 __be32 spmode; /* SPI mode register */
162 u8 res1[0x2];
163 u8 spie; /* SPI event register */
164 u8 res2[0x1];
165 u8 res3[0x2];
166 u8 spim; /* SPI mask register */
167 u8 res4[0x1];
168 u8 res5[0x1];
169 u8 spcom; /* SPI command register */
170 u8 res6[0x2];
171 __be32 spitd; /* SPI transmit data register (cpu mode) */
172 __be32 spird; /* SPI receive data register (cpu mode) */
173 u8 res7[0x8];
174} __attribute__ ((packed));
175
176/* SI */
177struct si1 {
178 __be16 siamr1; /* SI1 TDMA mode register */
179 __be16 sibmr1; /* SI1 TDMB mode register */
180 __be16 sicmr1; /* SI1 TDMC mode register */
181 __be16 sidmr1; /* SI1 TDMD mode register */
182 u8 siglmr1_h; /* SI1 global mode register high */
183 u8 res0[0x1];
184 u8 sicmdr1_h; /* SI1 command register high */
185 u8 res2[0x1];
186 u8 sistr1_h; /* SI1 status register high */
187 u8 res3[0x1];
188 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
189 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
190 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
191 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
192 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
193 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
194 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
195 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
196 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
197 u8 res4[0x8];
198 __be16 siemr1; /* SI1 TDME mode register 16 bits */
199 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
200 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
201 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
202 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
203 u8 res5[0x1];
204 u8 sicmdr1_l; /* SI1 command register low 8 bits */
205 u8 res6[0x1];
206 u8 sistr1_l; /* SI1 status register low 8 bits */
207 u8 res7[0x1];
208 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
209 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
210 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
211 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
212 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
213 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
214 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
215 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
216 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
217 u8 res8[0x8];
218 __be32 siml1; /* SI1 multiframe limit register */
219 u8 siedm1; /* SI1 extended diagnostic mode register */
220 u8 res9[0xBB];
221} __attribute__ ((packed));
222
223/* SI Routing Tables */
224struct sir {
225 u8 tx[0x400];
226 u8 rx[0x400];
227 u8 res0[0x800];
228} __attribute__ ((packed));
229
230/* USB Controller */
231struct usb_ctlr {
232 u8 usb_usmod;
233 u8 usb_usadr;
234 u8 usb_uscom;
235 u8 res1[1];
236 __be16 usb_usep1;
237 __be16 usb_usep2;
238 __be16 usb_usep3;
239 __be16 usb_usep4;
240 u8 res2[4];
241 __be16 usb_usber;
242 u8 res3[2];
243 __be16 usb_usbmr;
244 u8 res4[1];
245 u8 usb_usbs;
246 __be16 usb_ussft;
247 u8 res5[2];
248 __be16 usb_usfrn;
249 u8 res6[0x22];
250} __attribute__ ((packed));
251
252/* MCC */
253struct mcc {
254 __be32 mcce; /* MCC event register */
255 __be32 mccm; /* MCC mask register */
256 __be32 mccf; /* MCC configuration register */
257 __be32 merl; /* MCC emergency request level register */
258 u8 res0[0xF0];
259} __attribute__ ((packed));
260
261/* QE UCC Slow */
262struct ucc_slow {
263 __be32 gumr_l; /* UCCx general mode register (low) */
264 __be32 gumr_h; /* UCCx general mode register (high) */
265 __be16 upsmr; /* UCCx protocol-specific mode register */
266 u8 res0[0x2];
267 __be16 utodr; /* UCCx transmit on demand register */
268 __be16 udsr; /* UCCx data synchronization register */
269 __be16 ucce; /* UCCx event register */
270 u8 res1[0x2];
271 __be16 uccm; /* UCCx mask register */
272 u8 res2[0x1];
273 u8 uccs; /* UCCx status register */
274 u8 res3[0x24];
275 __be16 utpt;
276 u8 guemr; /* UCC general extended mode register */
277 u8 res4[0x200 - 0x091];
278} __attribute__ ((packed));
279
280/* QE UCC Fast */
281struct ucc_fast {
282 __be32 gumr; /* UCCx general mode register */
283 __be32 upsmr; /* UCCx protocol-specific mode register */
284 __be16 utodr; /* UCCx transmit on demand register */
285 u8 res0[0x2];
286 __be16 udsr; /* UCCx data synchronization register */
287 u8 res1[0x2];
288 __be32 ucce; /* UCCx event register */
289 __be32 uccm; /* UCCx mask register */
290 u8 uccs; /* UCCx status register */
291 u8 res2[0x7];
292 __be32 urfb; /* UCC receive FIFO base */
293 __be16 urfs; /* UCC receive FIFO size */
294 u8 res3[0x2];
295 __be16 urfet; /* UCC receive FIFO emergency threshold */
296 __be16 urfset; /* UCC receive FIFO special emergency
297 threshold */
298 __be32 utfb; /* UCC transmit FIFO base */
299 __be16 utfs; /* UCC transmit FIFO size */
300 u8 res4[0x2];
301 __be16 utfet; /* UCC transmit FIFO emergency threshold */
302 u8 res5[0x2];
303 __be16 utftt; /* UCC transmit FIFO transmit threshold */
304 u8 res6[0x2];
305 __be16 utpt; /* UCC transmit polling timer */
306 u8 res7[0x2];
307 __be32 urtry; /* UCC retry counter register */
308 u8 res8[0x4C];
309 u8 guemr; /* UCC general extended mode register */
310 u8 res9[0x100 - 0x091];
311} __attribute__ ((packed));
312
313/* QE UCC */
314struct ucc_common {
315 u8 res1[0x90];
316 u8 guemr;
317 u8 res2[0x200 - 0x091];
318} __attribute__ ((packed));
319
320struct ucc {
321 union {
322 struct ucc_slow slow;
323 struct ucc_fast fast;
324 struct ucc_common common;
325 };
326} __attribute__ ((packed));
327
328/* MultiPHY UTOPIA POS Controllers (UPC) */
329struct upc {
330 __be32 upgcr; /* UTOPIA/POS general configuration register */
331 __be32 uplpa; /* UTOPIA/POS last PHY address */
332 __be32 uphec; /* ATM HEC register */
333 __be32 upuc; /* UTOPIA/POS UCC configuration */
334 __be32 updc1; /* UTOPIA/POS device 1 configuration */
335 __be32 updc2; /* UTOPIA/POS device 2 configuration */
336 __be32 updc3; /* UTOPIA/POS device 3 configuration */
337 __be32 updc4; /* UTOPIA/POS device 4 configuration */
338 __be32 upstpa; /* UTOPIA/POS STPA threshold */
339 u8 res0[0xC];
340 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
341 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
342 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
343 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
344 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
345 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
346 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
347 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
348 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
349 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
350 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
351 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
352 __be32 upde1; /* UTOPIA/POS device 1 event */
353 __be32 upde2; /* UTOPIA/POS device 2 event */
354 __be32 upde3; /* UTOPIA/POS device 3 event */
355 __be32 upde4; /* UTOPIA/POS device 4 event */
356 __be16 uprp1;
357 __be16 uprp2;
358 __be16 uprp3;
359 __be16 uprp4;
360 u8 res1[0x8];
361 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
362 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
363 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
364 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
365 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
366 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
367 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
368 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
369 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
370 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
371 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
372 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
373 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
374 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
375 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
376 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
377 __be32 uper1; /* Device 1 port enable register */
378 __be32 uper2; /* Device 2 port enable register */
379 __be32 uper3; /* Device 3 port enable register */
380 __be32 uper4; /* Device 4 port enable register */
381 u8 res2[0x150];
382} __attribute__ ((packed));
383
384/* SDMA */
385struct sdma {
386 __be32 sdsr; /* Serial DMA status register */
387 __be32 sdmr; /* Serial DMA mode register */
388 __be32 sdtr1; /* SDMA system bus threshold register */
389 __be32 sdtr2; /* SDMA secondary bus threshold register */
390 __be32 sdhy1; /* SDMA system bus hysteresis register */
391 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
392 __be32 sdta1; /* SDMA system bus address register */
393 __be32 sdta2; /* SDMA secondary bus address register */
394 __be32 sdtm1; /* SDMA system bus MSNUM register */
395 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
396 u8 res0[0x10];
397 __be32 sdaqr; /* SDMA address bus qualify register */
398 __be32 sdaqmr; /* SDMA address bus qualify mask register */
399 u8 res1[0x4];
400 __be32 sdebcr; /* SDMA CAM entries base register */
401 u8 res2[0x38];
402} __attribute__ ((packed));
403
404/* Debug Space */
405struct dbg {
406 __be32 bpdcr; /* Breakpoint debug command register */
407 __be32 bpdsr; /* Breakpoint debug status register */
408 __be32 bpdmr; /* Breakpoint debug mask register */
409 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
410 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
411 u8 res0[0x8];
412 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
413 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
414 u8 res1[0x8];
415 __be32 bprmir; /* Breakpoint request mode immediate register */
416 __be32 bprmsr; /* Breakpoint request mode serial register */
417 __be32 bpemr; /* Breakpoint exit mode register */
418 u8 res2[0x48];
419} __attribute__ ((packed));
420
421/* RISC Special Registers (Trap and Breakpoint) */
422struct rsp {
423 u8 fixme[0x100];
424} __attribute__ ((packed));
425
426struct qe_immap {
427 struct qe_iram iram; /* I-RAM */
428 struct qe_ic_regs ic; /* Interrupt Controller */
429 struct cp_qe cp; /* Communications Processor */
430 struct qe_mux qmx; /* QE Multiplexer */
431 struct qe_timers qet; /* QE Timers */
432 struct spi spi[0x2]; /* spi */
433 struct mcc mcc; /* mcc */
434 struct qe_brg brg; /* brg */
435 struct usb_ctlr usb; /* USB */
436 struct si1 si1; /* SI */
437 u8 res11[0x800];
438 struct sir sir; /* SI Routing Tables */
439 struct ucc ucc1; /* ucc1 */
440 struct ucc ucc3; /* ucc3 */
441 struct ucc ucc5; /* ucc5 */
442 struct ucc ucc7; /* ucc7 */
443 u8 res12[0x600];
444 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
445 struct ucc ucc2; /* ucc2 */
446 struct ucc ucc4; /* ucc4 */
447 struct ucc ucc6; /* ucc6 */
448 struct ucc ucc8; /* ucc8 */
449 u8 res13[0x600];
450 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
451 struct sdma sdma; /* SDMA */
452 struct dbg dbg; /* Debug Space */
453 struct rsp rsp[0x2]; /* RISC Special Registers
454 (Trap and Breakpoint) */
455 u8 res14[0x300];
456 u8 res15[0x3A00];
457 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
458 u8 muram[0xC000]; /* 0x110000 - 0x11C000
459 Multi-user RAM */
460 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
461 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
462} __attribute__ ((packed));
463
464extern struct qe_immap *qe_immr;
465extern phys_addr_t get_qe_base(void);
466
467static inline unsigned long immrbar_virt_to_phys(volatile void * address)
468{
469 if ( ((u32)address >= (u32)qe_immr) &&
470 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
471 return (unsigned long)(address - (u32)qe_immr +
472 (u32)get_qe_base());
473 return (unsigned long)virt_to_phys(address);
474}
475
476#endif /* __KERNEL__ */
477#endif /* _ASM_POWERPC_IMMAP_QE_H */
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
new file mode 100644
index 000000000000..a62168ec535f
--- /dev/null
+++ b/include/asm-powerpc/qe.h
@@ -0,0 +1,457 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QUICC Engine (QE) external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_H
16#define _ASM_POWERPC_QE_H
17#ifdef __KERNEL__
18
19#include <asm/immap_qe.h>
20
21#define QE_NUM_OF_SNUM 28
22#define QE_NUM_OF_BRGS 16
23#define QE_NUM_OF_PORTS 1024
24
25/* Memory partitions
26*/
27#define MEM_PART_SYSTEM 0
28#define MEM_PART_SECONDARY 1
29#define MEM_PART_MURAM 2
30
31/* Export QE common operations */
32extern void qe_reset(void);
33extern int par_io_init(struct device_node *np);
34extern int par_io_of_config(struct device_node *np);
35
36/* QE internal API */
37int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
38void qe_setbrg(u32 brg, u32 rate);
39int qe_get_snum(void);
40void qe_put_snum(u8 snum);
41u32 qe_muram_alloc(u32 size, u32 align);
42int qe_muram_free(u32 offset);
43u32 qe_muram_alloc_fixed(u32 offset, u32 size);
44void qe_muram_dump(void);
45void *qe_muram_addr(u32 offset);
46
47/* Buffer descriptors */
48struct qe_bd {
49 u16 status;
50 u16 length;
51 u32 buf;
52} __attribute__ ((packed));
53
54#define BD_STATUS_MASK 0xffff0000
55#define BD_LENGTH_MASK 0x0000ffff
56
57/* Alignment */
58#define QE_INTR_TABLE_ALIGN 16 /* ??? */
59#define QE_ALIGNMENT_OF_BD 8
60#define QE_ALIGNMENT_OF_PRAM 64
61
62/* RISC allocation */
63enum qe_risc_allocation {
64 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
65 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
66 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
67 RISC 1 or RISC 2 */
68};
69
70/* QE extended filtering Table Lookup Key Size */
71enum qe_fltr_tbl_lookup_key_size {
72 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
73 = 0x3f, /* LookupKey parsed by the Generate LookupKey
74 CMD is truncated to 8 bytes */
75 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
76 = 0x5f, /* LookupKey parsed by the Generate LookupKey
77 CMD is truncated to 16 bytes */
78};
79
80/* QE FLTR extended filtering Largest External Table Lookup Key Size */
81enum qe_fltr_largest_external_tbl_lookup_key_size {
82 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
83 = 0x0,/* not used */
84 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
85 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
86 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
87 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
88};
89
90/* structure representing QE parameter RAM */
91struct qe_timer_tables {
92 u16 tm_base; /* QE timer table base adr */
93 u16 tm_ptr; /* QE timer table pointer */
94 u16 r_tmr; /* QE timer mode register */
95 u16 r_tmv; /* QE timer valid register */
96 u32 tm_cmd; /* QE timer cmd register */
97 u32 tm_cnt; /* QE timer internal cnt */
98} __attribute__ ((packed));
99
100#define QE_FLTR_TAD_SIZE 8
101
102/* QE extended filtering Termination Action Descriptor (TAD) */
103struct qe_fltr_tad {
104 u8 serialized[QE_FLTR_TAD_SIZE];
105} __attribute__ ((packed));
106
107/* Communication Direction */
108enum comm_dir {
109 COMM_DIR_NONE = 0,
110 COMM_DIR_RX = 1,
111 COMM_DIR_TX = 2,
112 COMM_DIR_RX_AND_TX = 3
113};
114
115/* Clocks and BRGs */
116enum qe_clock {
117 QE_CLK_NONE = 0,
118 QE_BRG1, /* Baud Rate Generator 1 */
119 QE_BRG2, /* Baud Rate Generator 2 */
120 QE_BRG3, /* Baud Rate Generator 3 */
121 QE_BRG4, /* Baud Rate Generator 4 */
122 QE_BRG5, /* Baud Rate Generator 5 */
123 QE_BRG6, /* Baud Rate Generator 6 */
124 QE_BRG7, /* Baud Rate Generator 7 */
125 QE_BRG8, /* Baud Rate Generator 8 */
126 QE_BRG9, /* Baud Rate Generator 9 */
127 QE_BRG10, /* Baud Rate Generator 10 */
128 QE_BRG11, /* Baud Rate Generator 11 */
129 QE_BRG12, /* Baud Rate Generator 12 */
130 QE_BRG13, /* Baud Rate Generator 13 */
131 QE_BRG14, /* Baud Rate Generator 14 */
132 QE_BRG15, /* Baud Rate Generator 15 */
133 QE_BRG16, /* Baud Rate Generator 16 */
134 QE_CLK1, /* Clock 1 */
135 QE_CLK2, /* Clock 2 */
136 QE_CLK3, /* Clock 3 */
137 QE_CLK4, /* Clock 4 */
138 QE_CLK5, /* Clock 5 */
139 QE_CLK6, /* Clock 6 */
140 QE_CLK7, /* Clock 7 */
141 QE_CLK8, /* Clock 8 */
142 QE_CLK9, /* Clock 9 */
143 QE_CLK10, /* Clock 10 */
144 QE_CLK11, /* Clock 11 */
145 QE_CLK12, /* Clock 12 */
146 QE_CLK13, /* Clock 13 */
147 QE_CLK14, /* Clock 14 */
148 QE_CLK15, /* Clock 15 */
149 QE_CLK16, /* Clock 16 */
150 QE_CLK17, /* Clock 17 */
151 QE_CLK18, /* Clock 18 */
152 QE_CLK19, /* Clock 19 */
153 QE_CLK20, /* Clock 20 */
154 QE_CLK21, /* Clock 21 */
155 QE_CLK22, /* Clock 22 */
156 QE_CLK23, /* Clock 23 */
157 QE_CLK24, /* Clock 24 */
158 QE_CLK_DUMMY,
159};
160
161/* QE CMXUCR Registers.
162 * There are two UCCs represented in each of the four CMXUCR registers.
163 * These values are for the UCC in the LSBs
164 */
165#define QE_CMXUCR_MII_ENET_MNG 0x00007000
166#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
167#define QE_CMXUCR_GRANT 0x00008000
168#define QE_CMXUCR_TSA 0x00004000
169#define QE_CMXUCR_BKPT 0x00000100
170#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
171
172/* QE CMXGCR Registers.
173*/
174#define QE_CMXGCR_MII_ENET_MNG 0x00007000
175#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
176#define QE_CMXGCR_USBCS 0x0000000f
177
178/* QE CECR Commands.
179*/
180#define QE_CR_FLG 0x00010000
181#define QE_RESET 0x80000000
182#define QE_INIT_TX_RX 0x00000000
183#define QE_INIT_RX 0x00000001
184#define QE_INIT_TX 0x00000002
185#define QE_ENTER_HUNT_MODE 0x00000003
186#define QE_STOP_TX 0x00000004
187#define QE_GRACEFUL_STOP_TX 0x00000005
188#define QE_RESTART_TX 0x00000006
189#define QE_CLOSE_RX_BD 0x00000007
190#define QE_SWITCH_COMMAND 0x00000007
191#define QE_SET_GROUP_ADDRESS 0x00000008
192#define QE_START_IDMA 0x00000009
193#define QE_MCC_STOP_RX 0x00000009
194#define QE_ATM_TRANSMIT 0x0000000a
195#define QE_HPAC_CLEAR_ALL 0x0000000b
196#define QE_GRACEFUL_STOP_RX 0x0000001a
197#define QE_RESTART_RX 0x0000001b
198#define QE_HPAC_SET_PRIORITY 0x0000010b
199#define QE_HPAC_STOP_TX 0x0000020b
200#define QE_HPAC_STOP_RX 0x0000030b
201#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
202#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
203#define QE_HPAC_START_TX 0x0000060b
204#define QE_HPAC_START_RX 0x0000070b
205#define QE_USB_STOP_TX 0x0000000a
206#define QE_USB_RESTART_TX 0x0000000b
207#define QE_QMC_STOP_TX 0x0000000c
208#define QE_QMC_STOP_RX 0x0000000d
209#define QE_SS7_SU_FIL_RESET 0x0000000e
210/* jonathbr added from here down for 83xx */
211#define QE_RESET_BCS 0x0000000a
212#define QE_MCC_INIT_TX_RX_16 0x00000003
213#define QE_MCC_STOP_TX 0x00000004
214#define QE_MCC_INIT_TX_1 0x00000005
215#define QE_MCC_INIT_RX_1 0x00000006
216#define QE_MCC_RESET 0x00000007
217#define QE_SET_TIMER 0x00000008
218#define QE_RANDOM_NUMBER 0x0000000c
219#define QE_ATM_MULTI_THREAD_INIT 0x00000011
220#define QE_ASSIGN_PAGE 0x00000012
221#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
222#define QE_START_FLOW_CONTROL 0x00000014
223#define QE_STOP_FLOW_CONTROL 0x00000015
224#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
225
226#define QE_ASSIGN_RISC 0x00000010
227#define QE_CR_MCN_NORMAL_SHIFT 6
228#define QE_CR_MCN_USB_SHIFT 4
229#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
230#define QE_CR_SNUM_SHIFT 17
231
232/* QE CECR Sub Block - sub block of QE command.
233*/
234#define QE_CR_SUBBLOCK_INVALID 0x00000000
235#define QE_CR_SUBBLOCK_USB 0x03200000
236#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
237#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
238#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
239#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
240#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
241#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
242#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
243#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
244#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
245#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
246#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
247#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
248#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
249#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
250#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
251#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
252#define QE_CR_SUBBLOCK_MCC1 0x03800000
253#define QE_CR_SUBBLOCK_MCC2 0x03a00000
254#define QE_CR_SUBBLOCK_MCC3 0x03000000
255#define QE_CR_SUBBLOCK_IDMA1 0x02800000
256#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
257#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
258#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
259#define QE_CR_SUBBLOCK_HPAC 0x01e00000
260#define QE_CR_SUBBLOCK_SPI1 0x01400000
261#define QE_CR_SUBBLOCK_SPI2 0x01600000
262#define QE_CR_SUBBLOCK_RAND 0x01c00000
263#define QE_CR_SUBBLOCK_TIMER 0x01e00000
264#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
265
266/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
267#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
268#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
269#define QE_CR_PROTOCOL_ATM_POS 0x0A
270#define QE_CR_PROTOCOL_ETHERNET 0x0C
271#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
272
273/* BMR byte order */
274#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */
275#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */
276#define QE_BMR_BYTE_ORDER_BO_MAX 0x18
277
278/* BRG configuration register */
279#define QE_BRGC_ENABLE 0x00010000
280#define QE_BRGC_DIVISOR_SHIFT 1
281#define QE_BRGC_DIVISOR_MAX 0xFFF
282#define QE_BRGC_DIV16 1
283
284/* QE Timers registers */
285#define QE_GTCFR1_PCAS 0x80
286#define QE_GTCFR1_STP2 0x20
287#define QE_GTCFR1_RST2 0x10
288#define QE_GTCFR1_GM2 0x08
289#define QE_GTCFR1_GM1 0x04
290#define QE_GTCFR1_STP1 0x02
291#define QE_GTCFR1_RST1 0x01
292
293/* SDMA registers */
294#define QE_SDSR_BER1 0x02000000
295#define QE_SDSR_BER2 0x01000000
296
297#define QE_SDMR_GLB_1_MSK 0x80000000
298#define QE_SDMR_ADR_SEL 0x20000000
299#define QE_SDMR_BER1_MSK 0x02000000
300#define QE_SDMR_BER2_MSK 0x01000000
301#define QE_SDMR_EB1_MSK 0x00800000
302#define QE_SDMR_ER1_MSK 0x00080000
303#define QE_SDMR_ER2_MSK 0x00040000
304#define QE_SDMR_CEN_MASK 0x0000E000
305#define QE_SDMR_SBER_1 0x00000200
306#define QE_SDMR_SBER_2 0x00000200
307#define QE_SDMR_EB1_PR_MASK 0x000000C0
308#define QE_SDMR_ER1_PR 0x00000008
309
310#define QE_SDMR_CEN_SHIFT 13
311#define QE_SDMR_EB1_PR_SHIFT 6
312
313#define QE_SDTM_MSNUM_SHIFT 24
314
315#define QE_SDEBCR_BA_MASK 0x01FFFFFF
316
317/* UPC */
318#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
319#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
320#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
321#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
322#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
323
324/* UCC */
325#define UCC_GUEMR_MODE_MASK_RX 0x02
326#define UCC_GUEMR_MODE_MASK_TX 0x01
327#define UCC_GUEMR_MODE_FAST_RX 0x02
328#define UCC_GUEMR_MODE_FAST_TX 0x01
329#define UCC_GUEMR_MODE_SLOW_RX 0x00
330#define UCC_GUEMR_MODE_SLOW_TX 0x00
331#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
332 must be set 1 */
333
334/* structure representing UCC SLOW parameter RAM */
335struct ucc_slow_pram {
336 u16 rbase; /* RX BD base address */
337 u16 tbase; /* TX BD base address */
338 u8 rfcr; /* Rx function code */
339 u8 tfcr; /* Tx function code */
340 u16 mrblr; /* Rx buffer length */
341 u32 rstate; /* Rx internal state */
342 u32 rptr; /* Rx internal data pointer */
343 u16 rbptr; /* rb BD Pointer */
344 u16 rcount; /* Rx internal byte count */
345 u32 rtemp; /* Rx temp */
346 u32 tstate; /* Tx internal state */
347 u32 tptr; /* Tx internal data pointer */
348 u16 tbptr; /* Tx BD pointer */
349 u16 tcount; /* Tx byte count */
350 u32 ttemp; /* Tx temp */
351 u32 rcrc; /* temp receive CRC */
352 u32 tcrc; /* temp transmit CRC */
353} __attribute__ ((packed));
354
355/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
356#define UCC_SLOW_GUMR_H_CRC16 0x00004000
357#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000
358#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000
359#define UCC_SLOW_GUMR_H_REVD 0x00002000
360#define UCC_SLOW_GUMR_H_TRX 0x00001000
361#define UCC_SLOW_GUMR_H_TTX 0x00000800
362#define UCC_SLOW_GUMR_H_CDP 0x00000400
363#define UCC_SLOW_GUMR_H_CTSP 0x00000200
364#define UCC_SLOW_GUMR_H_CDS 0x00000100
365#define UCC_SLOW_GUMR_H_CTSS 0x00000080
366#define UCC_SLOW_GUMR_H_TFL 0x00000040
367#define UCC_SLOW_GUMR_H_RFW 0x00000020
368#define UCC_SLOW_GUMR_H_TXSY 0x00000010
369#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
370#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
371#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
372#define UCC_SLOW_GUMR_H_RTSM 0x00000002
373#define UCC_SLOW_GUMR_H_RSYN 0x00000001
374
375#define UCC_SLOW_GUMR_L_TCI 0x10000000
376#define UCC_SLOW_GUMR_L_RINV 0x02000000
377#define UCC_SLOW_GUMR_L_TINV 0x01000000
378#define UCC_SLOW_GUMR_L_TEND 0x00020000
379#define UCC_SLOW_GUMR_L_ENR 0x00000020
380#define UCC_SLOW_GUMR_L_ENT 0x00000010
381
382/* General UCC FAST Mode Register */
383#define UCC_FAST_GUMR_TCI 0x20000000
384#define UCC_FAST_GUMR_TRX 0x10000000
385#define UCC_FAST_GUMR_TTX 0x08000000
386#define UCC_FAST_GUMR_CDP 0x04000000
387#define UCC_FAST_GUMR_CTSP 0x02000000
388#define UCC_FAST_GUMR_CDS 0x01000000
389#define UCC_FAST_GUMR_CTSS 0x00800000
390#define UCC_FAST_GUMR_TXSY 0x00020000
391#define UCC_FAST_GUMR_RSYN 0x00010000
392#define UCC_FAST_GUMR_RTSM 0x00002000
393#define UCC_FAST_GUMR_REVD 0x00000400
394#define UCC_FAST_GUMR_ENR 0x00000020
395#define UCC_FAST_GUMR_ENT 0x00000010
396
397/* Slow UCC Event Register (UCCE) */
398#define UCC_SLOW_UCCE_GLR 0x1000
399#define UCC_SLOW_UCCE_GLT 0x0800
400#define UCC_SLOW_UCCE_DCC 0x0400
401#define UCC_SLOW_UCCE_FLG 0x0200
402#define UCC_SLOW_UCCE_AB 0x0200
403#define UCC_SLOW_UCCE_IDLE 0x0100
404#define UCC_SLOW_UCCE_GRA 0x0080
405#define UCC_SLOW_UCCE_TXE 0x0010
406#define UCC_SLOW_UCCE_RXF 0x0008
407#define UCC_SLOW_UCCE_CCR 0x0008
408#define UCC_SLOW_UCCE_RCH 0x0008
409#define UCC_SLOW_UCCE_BSY 0x0004
410#define UCC_SLOW_UCCE_TXB 0x0002
411#define UCC_SLOW_UCCE_TX 0x0002
412#define UCC_SLOW_UCCE_RX 0x0001
413#define UCC_SLOW_UCCE_GOV 0x0001
414#define UCC_SLOW_UCCE_GUN 0x0002
415#define UCC_SLOW_UCCE_GINT 0x0004
416#define UCC_SLOW_UCCE_IQOV 0x0008
417
418#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
419 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF | \
420 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
421#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
422 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF)
423#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
424 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
425 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
426#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY | UCC_SLOW_UCCE_GRA | \
427 UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
428 UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
429#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV | UCC_SLOW_UCCE_GINT | \
430 UCC_SLOW_UCCE_GUN | UCC_SLOW_UCCE_GOV)
431
432#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
433 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | \
434 UCC_SLOW_UCCE_GLR)
435
436#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB
437#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX)
438#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX)
439
440/* UCC Transmit On Demand Register (UTODR) */
441#define UCC_SLOW_TOD 0x8000
442#define UCC_FAST_TOD 0x8000
443
444/* Function code masks */
445#define FC_GBL 0x20
446#define FC_DTB_LCL 0x02
447#define UCC_FAST_FUNCTION_CODE_GBL 0x20
448#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
449#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
450
451static inline long IS_MURAM_ERR(const u32 offset)
452{
453 return offset > (u32) - 1000L;
454}
455
456#endif /* __KERNEL__ */
457#endif /* _ASM_POWERPC_QE_H */
diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h
new file mode 100644
index 000000000000..e386fb7e44b0
--- /dev/null
+++ b/include/asm-powerpc/qe_ic.h
@@ -0,0 +1,64 @@
1/*
2 * include/asm-powerpc/qe_ic.h
3 *
4 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
5 *
6 * Authors: Shlomi Gridish <gridish@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Description:
10 * QE IC external definitions and structure.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef _ASM_POWERPC_QE_IC_H
18#define _ASM_POWERPC_QE_IC_H
19
20#include <linux/irq.h>
21
22#define NUM_OF_QE_IC_GROUPS 6
23
24/* Flags when we init the QE IC */
25#define QE_IC_SPREADMODE_GRP_W 0x00000001
26#define QE_IC_SPREADMODE_GRP_X 0x00000002
27#define QE_IC_SPREADMODE_GRP_Y 0x00000004
28#define QE_IC_SPREADMODE_GRP_Z 0x00000008
29#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
30#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
31
32#define QE_IC_LOW_SIGNAL 0x00000100
33#define QE_IC_HIGH_SIGNAL 0x00000200
34
35#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
36#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
37#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
38#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
39#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
40#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
41#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
42#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
43#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
44#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
45#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
46#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
47#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
48
49/* QE interrupt sources groups */
50enum qe_ic_grp_id {
51 QE_IC_GRP_W = 0, /* QE interrupt controller group W */
52 QE_IC_GRP_X, /* QE interrupt controller group X */
53 QE_IC_GRP_Y, /* QE interrupt controller group Y */
54 QE_IC_GRP_Z, /* QE interrupt controller group Z */
55 QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
56 QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
57};
58
59void qe_ic_init(struct device_node *node, unsigned int flags);
60void qe_ic_set_highest_priority(unsigned int virq, int high);
61int qe_ic_set_priority(unsigned int virq, unsigned int priority);
62int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
63
64#endif /* _ASM_POWERPC_QE_IC_H */
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 4b41deaa8d8d..43627596003b 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -91,10 +91,6 @@ DEBUGGER_BOILERPLATE(debugger_iabr_match)
91DEBUGGER_BOILERPLATE(debugger_dabr_match) 91DEBUGGER_BOILERPLATE(debugger_dabr_match)
92DEBUGGER_BOILERPLATE(debugger_fault_handler) 92DEBUGGER_BOILERPLATE(debugger_fault_handler)
93 93
94#ifdef CONFIG_XMON
95extern void xmon_init(int enable);
96#endif
97
98#else 94#else
99static inline int debugger(struct pt_regs *regs) { return 0; } 95static inline int debugger(struct pt_regs *regs) { return 0; }
100static inline int debugger_ipi(struct pt_regs *regs) { return 0; } 96static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h
new file mode 100644
index 000000000000..afe3076bdc03
--- /dev/null
+++ b/include/asm-powerpc/ucc.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * Internal header file for UCC unit routines.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __UCC_H__
16#define __UCC_H__
17
18#include <asm/immap_qe.h>
19#include <asm/qe.h>
20
21#define STATISTICS
22
23#define UCC_MAX_NUM 8
24
25/* Slow or fast type for UCCs.
26*/
27enum ucc_speed_type {
28 UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW
29};
30
31/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
32*/
33enum ucc_pram_initial_offset {
34 UCC_PRAM_OFFSET_UCC1 = 0x8400,
35 UCC_PRAM_OFFSET_UCC2 = 0x8500,
36 UCC_PRAM_OFFSET_UCC3 = 0x8600,
37 UCC_PRAM_OFFSET_UCC4 = 0x9000,
38 UCC_PRAM_OFFSET_UCC5 = 0x8000,
39 UCC_PRAM_OFFSET_UCC6 = 0x8100,
40 UCC_PRAM_OFFSET_UCC7 = 0x8200,
41 UCC_PRAM_OFFSET_UCC8 = 0x8300
42};
43
44/* ucc_set_type
45 * Sets UCC to slow or fast mode.
46 *
47 * ucc_num - (In) number of UCC (0-7).
48 * regs - (In) pointer to registers base for the UCC.
49 * speed - (In) slow or fast mode for UCC.
50 */
51int ucc_set_type(int ucc_num, struct ucc_common *regs,
52 enum ucc_speed_type speed);
53
54/* ucc_init_guemr
55 * Init the Guemr register.
56 *
57 * regs - (In) pointer to registers base for the UCC.
58 */
59int ucc_init_guemr(struct ucc_common *regs);
60
61int ucc_set_qe_mux_mii_mng(int ucc_num);
62
63int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode);
64
65int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask);
66
67/* QE MUX clock routing for UCC
68*/
69static inline int ucc_set_qe_mux_grant(int ucc_num, int set)
70{
71 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
72}
73
74static inline int ucc_set_qe_mux_tsa(int ucc_num, int set)
75{
76 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
77}
78
79static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set)
80{
81 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
82}
83
84#endif /* __UCC_H__ */
diff --git a/include/asm-powerpc/ucc_fast.h b/include/asm-powerpc/ucc_fast.h
new file mode 100644
index 000000000000..39d1c90fd2ca
--- /dev/null
+++ b/include/asm-powerpc/ucc_fast.h
@@ -0,0 +1,243 @@
1/*
2 * include/asm-powerpc/ucc_fast.h
3 *
4 * Internal header file for UCC FAST unit routines.
5 *
6 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
7 *
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#ifndef __UCC_FAST_H__
17#define __UCC_FAST_H__
18
19#include <linux/kernel.h>
20
21#include <asm/immap_qe.h>
22#include <asm/qe.h>
23
24#include "ucc.h"
25
26/* Receive BD's status */
27#define R_E 0x80000000 /* buffer empty */
28#define R_W 0x20000000 /* wrap bit */
29#define R_I 0x10000000 /* interrupt on reception */
30#define R_L 0x08000000 /* last */
31#define R_F 0x04000000 /* first */
32
33/* transmit BD's status */
34#define T_R 0x80000000 /* ready bit */
35#define T_W 0x20000000 /* wrap bit */
36#define T_I 0x10000000 /* interrupt on completion */
37#define T_L 0x08000000 /* last */
38
39/* Rx Data buffer must be 4 bytes aligned in most cases */
40#define UCC_FAST_RX_ALIGN 4
41#define UCC_FAST_MRBLR_ALIGNMENT 4
42#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
43
44/* Sizes */
45#define UCC_FAST_URFS_MIN_VAL 0x88
46#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
47
48/* ucc_fast_channel_protocol_mode - UCC FAST mode */
49enum ucc_fast_channel_protocol_mode {
50 UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
51 UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
52 UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
53 UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
54 UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
55 UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
56 UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
57 UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
58 UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
59 UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
60 UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
61 UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
62 UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
63 UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
64 UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
65 UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
66};
67
68/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
69enum ucc_fast_transparent_txrx {
70 UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
71 UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
72};
73
74/* UCC fast diagnostic mode */
75enum ucc_fast_diag_mode {
76 UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
77 UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
78 UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
79 UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
80};
81
82/* UCC fast Sync length (transparent mode only) */
83enum ucc_fast_sync_len {
84 UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
85 UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
86 UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
87 UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
88};
89
90/* UCC fast RTS mode */
91enum ucc_fast_ready_to_send {
92 UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
93 UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
94};
95
96/* UCC fast receiver decoding mode */
97enum ucc_fast_rx_decoding_method {
98 UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
99 UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
100 UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
101 UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
102};
103
104/* UCC fast transmitter encoding mode */
105enum ucc_fast_tx_encoding_method {
106 UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
107 UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
108 UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
109 UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
110};
111
112/* UCC fast CRC length */
113enum ucc_fast_transparent_tcrc {
114 UCC_FAST_16_BIT_CRC = 0x00000000,
115 UCC_FAST_CRC_RESERVED0 = 0x00000040,
116 UCC_FAST_32_BIT_CRC = 0x00000080,
117 UCC_FAST_CRC_RESERVED1 = 0x000000C0
118};
119
120/* Fast UCC initialization structure */
121struct ucc_fast_info {
122 int ucc_num;
123 enum qe_clock rx_clock;
124 enum qe_clock tx_clock;
125 u32 regs;
126 int irq;
127 u32 uccm_mask;
128 int bd_mem_part;
129 int brkpt_support;
130 int grant_support;
131 int tsa;
132 int cdp;
133 int cds;
134 int ctsp;
135 int ctss;
136 int tci;
137 int txsy;
138 int rtsm;
139 int revd;
140 int rsyn;
141 u16 max_rx_buf_length;
142 u16 urfs;
143 u16 urfet;
144 u16 urfset;
145 u16 utfs;
146 u16 utfet;
147 u16 utftt;
148 u16 ufpt;
149 enum ucc_fast_channel_protocol_mode mode;
150 enum ucc_fast_transparent_txrx ttx_trx;
151 enum ucc_fast_tx_encoding_method tenc;
152 enum ucc_fast_rx_decoding_method renc;
153 enum ucc_fast_transparent_tcrc tcrc;
154 enum ucc_fast_sync_len synl;
155};
156
157struct ucc_fast_private {
158 struct ucc_fast_info *uf_info;
159 struct ucc_fast *uf_regs; /* a pointer to memory map of UCC regs. */
160 u32 *p_ucce; /* a pointer to the event register in memory. */
161 u32 *p_uccm; /* a pointer to the mask register in memory. */
162 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
163 int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
164 int stopped_tx; /* Whether channel has been stopped for Tx
165 (STOP_TX, etc.) */
166 int stopped_rx; /* Whether channel has been stopped for Rx */
167 u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
168 virtual fifo */
169 u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
170 virtual fifo */
171#ifdef STATISTICS
172 u32 tx_frames; /* Transmitted frames counter. */
173 u32 rx_frames; /* Received frames counter (only frames
174 passed to application). */
175 u32 tx_discarded; /* Discarded tx frames counter (frames that
176 were discarded by the driver due to errors).
177 */
178 u32 rx_discarded; /* Discarded rx frames counter (frames that
179 were discarded by the driver due to errors).
180 */
181#endif /* STATISTICS */
182 u16 mrblr; /* maximum receive buffer length */
183};
184
185/* ucc_fast_init
186 * Initializes Fast UCC according to user provided parameters.
187 *
188 * uf_info - (In) pointer to the fast UCC info structure.
189 * uccf_ret - (Out) pointer to the fast UCC structure.
190 */
191int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
192
193/* ucc_fast_free
194 * Frees all resources for fast UCC.
195 *
196 * uccf - (In) pointer to the fast UCC structure.
197 */
198void ucc_fast_free(struct ucc_fast_private * uccf);
199
200/* ucc_fast_enable
201 * Enables a fast UCC port.
202 * This routine enables Tx and/or Rx through the General UCC Mode Register.
203 *
204 * uccf - (In) pointer to the fast UCC structure.
205 * mode - (In) TX, RX, or both.
206 */
207void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
208
209/* ucc_fast_disable
210 * Disables a fast UCC port.
211 * This routine disables Tx and/or Rx through the General UCC Mode Register.
212 *
213 * uccf - (In) pointer to the fast UCC structure.
214 * mode - (In) TX, RX, or both.
215 */
216void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
217
218/* ucc_fast_irq
219 * Handles interrupts on fast UCC.
220 * Called from the general interrupt routine to handle interrupts on fast UCC.
221 *
222 * uccf - (In) pointer to the fast UCC structure.
223 */
224void ucc_fast_irq(struct ucc_fast_private * uccf);
225
226/* ucc_fast_transmit_on_demand
227 * Immediately forces a poll of the transmitter for data to be sent.
228 * Typically, the hardware performs a periodic poll for data that the
229 * transmit routine has set up to be transmitted. In cases where
230 * this polling cycle is not soon enough, this optional routine can
231 * be invoked to force a poll right away, instead. Proper use for
232 * each transmission for which this functionality is desired is to
233 * call the transmit routine and then this routine right after.
234 *
235 * uccf - (In) pointer to the fast UCC structure.
236 */
237void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
238
239u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
240
241void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
242
243#endif /* __UCC_FAST_H__ */
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
new file mode 100644
index 000000000000..ca93bc99237e
--- /dev/null
+++ b/include/asm-powerpc/ucc_slow.h
@@ -0,0 +1,289 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * Internal header file for UCC SLOW unit routines.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __UCC_SLOW_H__
16#define __UCC_SLOW_H__
17
18#include <linux/kernel.h>
19
20#include <asm/immap_qe.h>
21#include <asm/qe.h>
22
23#include "ucc.h"
24
25/* transmit BD's status */
26#define T_R 0x80000000 /* ready bit */
27#define T_PAD 0x40000000 /* add pads to short frames */
28#define T_W 0x20000000 /* wrap bit */
29#define T_I 0x10000000 /* interrupt on completion */
30#define T_L 0x08000000 /* last */
31
32#define T_A 0x04000000 /* Address - the data transmitted as address
33 chars */
34#define T_TC 0x04000000 /* transmit CRC */
35#define T_CM 0x02000000 /* continuous mode */
36#define T_DEF 0x02000000 /* collision on previous attempt to transmit */
37#define T_P 0x01000000 /* Preamble - send Preamble sequence before
38 data */
39#define T_HB 0x01000000 /* heartbeat */
40#define T_NS 0x00800000 /* No Stop */
41#define T_LC 0x00800000 /* late collision */
42#define T_RL 0x00400000 /* retransmission limit */
43#define T_UN 0x00020000 /* underrun */
44#define T_CT 0x00010000 /* CTS lost */
45#define T_CSL 0x00010000 /* carrier sense lost */
46#define T_RC 0x003c0000 /* retry count */
47
48/* Receive BD's status */
49#define R_E 0x80000000 /* buffer empty */
50#define R_W 0x20000000 /* wrap bit */
51#define R_I 0x10000000 /* interrupt on reception */
52#define R_L 0x08000000 /* last */
53#define R_C 0x08000000 /* the last byte in this buffer is a cntl
54 char */
55#define R_F 0x04000000 /* first */
56#define R_A 0x04000000 /* the first byte in this buffer is address
57 byte */
58#define R_CM 0x02000000 /* continuous mode */
59#define R_ID 0x01000000 /* buffer close on reception of idles */
60#define R_M 0x01000000 /* Frame received because of promiscuous
61 mode */
62#define R_AM 0x00800000 /* Address match */
63#define R_DE 0x00800000 /* Address match */
64#define R_LG 0x00200000 /* Break received */
65#define R_BR 0x00200000 /* Frame length violation */
66#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
67#define R_FR 0x00100000 /* Framing Error (no stop bit) character
68 received */
69#define R_PR 0x00080000 /* Parity Error character received */
70#define R_AB 0x00080000 /* Frame Aborted */
71#define R_SH 0x00080000 /* frame is too short */
72#define R_CR 0x00040000 /* CRC Error */
73#define R_OV 0x00020000 /* Overrun */
74#define R_CD 0x00010000 /* CD lost */
75#define R_CL 0x00010000 /* this frame is closed because of a
76 collision */
77
78/* Rx Data buffer must be 4 bytes aligned in most cases.*/
79#define UCC_SLOW_RX_ALIGN 4
80#define UCC_SLOW_MRBLR_ALIGNMENT 4
81#define UCC_SLOW_PRAM_SIZE 0x100
82#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
83
84/* UCC Slow Channel Protocol Mode */
85enum ucc_slow_channel_protocol_mode {
86 UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
87 UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
88 UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
89};
90
91/* UCC Slow Transparent Transmit CRC (TCRC) */
92enum ucc_slow_transparent_tcrc {
93 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
94 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
95 /* CRC16 (BISYNC). (X16 + X15 + X2 + 1) */
96 UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
97 /* 32-bit CCITT CRC (Ethernet and HDLC) */
98 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
99};
100
101/* UCC Slow oversampling rate for transmitter (TDCR) */
102enum ucc_slow_tx_oversampling_rate {
103 /* 1x clock mode */
104 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
105 /* 8x clock mode */
106 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
107 /* 16x clock mode */
108 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
109 /* 32x clock mode */
110 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
111};
112
113/* UCC Slow Oversampling rate for receiver (RDCR)
114*/
115enum ucc_slow_rx_oversampling_rate {
116 /* 1x clock mode */
117 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
118 /* 8x clock mode */
119 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
120 /* 16x clock mode */
121 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
122 /* 32x clock mode */
123 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
124};
125
126/* UCC Slow Transmitter encoding method (TENC)
127*/
128enum ucc_slow_tx_encoding_method {
129 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
130 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
131};
132
133/* UCC Slow Receiver decoding method (RENC)
134*/
135enum ucc_slow_rx_decoding_method {
136 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
137 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
138};
139
140/* UCC Slow Diagnostic mode (DIAG)
141*/
142enum ucc_slow_diag_mode {
143 UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
144 UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
145 UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
146 UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
147};
148
149struct ucc_slow_info {
150 int ucc_num;
151 enum qe_clock rx_clock;
152 enum qe_clock tx_clock;
153 struct ucc_slow *us_regs;
154 int irq;
155 u16 uccm_mask;
156 int data_mem_part;
157 int init_tx;
158 int init_rx;
159 u32 tx_bd_ring_len;
160 u32 rx_bd_ring_len;
161 int rx_interrupts;
162 int brkpt_support;
163 int grant_support;
164 int tsa;
165 int cdp;
166 int cds;
167 int ctsp;
168 int ctss;
169 int rinv;
170 int tinv;
171 int rtsm;
172 int rfw;
173 int tci;
174 int tend;
175 int tfl;
176 int txsy;
177 u16 max_rx_buf_length;
178 enum ucc_slow_transparent_tcrc tcrc;
179 enum ucc_slow_channel_protocol_mode mode;
180 enum ucc_slow_diag_mode diag;
181 enum ucc_slow_tx_oversampling_rate tdcr;
182 enum ucc_slow_rx_oversampling_rate rdcr;
183 enum ucc_slow_tx_encoding_method tenc;
184 enum ucc_slow_rx_decoding_method renc;
185};
186
187struct ucc_slow_private {
188 struct ucc_slow_info *us_info;
189 struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs */
190 struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
191 u32 us_pram_offset;
192 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
193 int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
194 int stopped_tx; /* Whether channel has been stopped for Tx
195 (STOP_TX, etc.) */
196 int stopped_rx; /* Whether channel has been stopped for Rx */
197 struct list_head confQ; /* frames passed to chip waiting for tx */
198 u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
199 and length for first BD in a frame */
200 u32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
201 u32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
202 u8 *confBd; /* next BD for confirm after Tx */
203 u8 *tx_bd; /* next BD for new Tx request */
204 u8 *rx_bd; /* next BD to collect after Rx */
205 void *p_rx_frame; /* accumulating receive frame */
206 u16 *p_ucce; /* a pointer to the event register in memory.
207 */
208 u16 *p_uccm; /* a pointer to the mask register in memory */
209 u16 saved_uccm; /* a saved mask for the RX Interrupt bits */
210#ifdef STATISTICS
211 u32 tx_frames; /* Transmitted frames counters */
212 u32 rx_frames; /* Received frames counters (only frames
213 passed to application) */
214 u32 rx_discarded; /* Discarded frames counters (frames that
215 were discarded by the driver due to
216 errors) */
217#endif /* STATISTICS */
218};
219
220/* ucc_slow_init
221 * Initializes Slow UCC according to provided parameters.
222 *
223 * us_info - (In) pointer to the slow UCC info structure.
224 * uccs_ret - (Out) pointer to the slow UCC structure.
225 */
226int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
227
228/* ucc_slow_free
229 * Frees all resources for slow UCC.
230 *
231 * uccs - (In) pointer to the slow UCC structure.
232 */
233void ucc_slow_free(struct ucc_slow_private * uccs);
234
235/* ucc_slow_enable
236 * Enables a fast UCC port.
237 * This routine enables Tx and/or Rx through the General UCC Mode Register.
238 *
239 * uccs - (In) pointer to the slow UCC structure.
240 * mode - (In) TX, RX, or both.
241 */
242void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
243
244/* ucc_slow_disable
245 * Disables a fast UCC port.
246 * This routine disables Tx and/or Rx through the General UCC Mode Register.
247 *
248 * uccs - (In) pointer to the slow UCC structure.
249 * mode - (In) TX, RX, or both.
250 */
251void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
252
253/* ucc_slow_poll_transmitter_now
254 * Immediately forces a poll of the transmitter for data to be sent.
255 * Typically, the hardware performs a periodic poll for data that the
256 * transmit routine has set up to be transmitted. In cases where
257 * this polling cycle is not soon enough, this optional routine can
258 * be invoked to force a poll right away, instead. Proper use for
259 * each transmission for which this functionality is desired is to
260 * call the transmit routine and then this routine right after.
261 *
262 * uccs - (In) pointer to the slow UCC structure.
263 */
264void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
265
266/* ucc_slow_graceful_stop_tx
267 * Smoothly stops transmission on a specified slow UCC.
268 *
269 * uccs - (In) pointer to the slow UCC structure.
270 */
271void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
272
273/* ucc_slow_stop_tx
274 * Stops transmission on a specified slow UCC.
275 *
276 * uccs - (In) pointer to the slow UCC structure.
277 */
278void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
279
280/* ucc_slow_restart_x
281 * Restarts transmitting on a specified slow UCC.
282 *
283 * uccs - (In) pointer to the slow UCC structure.
284 */
285void ucc_slow_restart_x(struct ucc_slow_private * uccs);
286
287u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
288
289#endif /* __UCC_SLOW_H__ */
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
index 43f7129984c7..f1d337ed68d5 100644
--- a/include/asm-powerpc/xmon.h
+++ b/include/asm-powerpc/xmon.h
@@ -1,12 +1,22 @@
1#ifndef __PPC_XMON_H 1#ifndef __ASM_POWERPC_XMON_H
2#define __PPC_XMON_H 2#define __ASM_POWERPC_XMON_H
3#ifdef __KERNEL__
4 3
5struct pt_regs; 4/*
5 * Copyrignt (C) 2006 IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
6 12
7extern int xmon(struct pt_regs *excp); 13#ifdef __KERNEL__
8extern void xmon_printf(const char *fmt, ...);
9extern void xmon_init(int);
10 14
15#ifdef CONFIG_XMON
16extern void xmon_setup(void);
17#else
18static inline void xmon_setup(void) { };
11#endif 19#endif
12#endif 20
21#endif /* __KERNEL __ */
22#endif /* __ASM_POWERPC_XMON_H */
diff --git a/include/asm-x86_64/hardirq.h b/include/asm-x86_64/hardirq.h
index 64a65ce2f41f..95d5e090ed89 100644
--- a/include/asm-x86_64/hardirq.h
+++ b/include/asm-x86_64/hardirq.h
@@ -6,6 +6,9 @@
6#include <asm/pda.h> 6#include <asm/pda.h>
7#include <asm/apic.h> 7#include <asm/apic.h>
8 8
9/* We can have at most NR_VECTORS irqs routed to a cpu at a time */
10#define MAX_HARDIRQS_PER_CPU NR_VECTORS
11
9#define __ARCH_IRQ_STAT 1 12#define __ARCH_IRQ_STAT 1
10 13
11#define local_softirq_pending() read_pda(__softirq_pending) 14#define local_softirq_pending() read_pda(__softirq_pending)
diff --git a/include/asm-x86_64/hw_irq.h b/include/asm-x86_64/hw_irq.h
index 48a4a5364e85..53d0d9fd10d6 100644
--- a/include/asm-x86_64/hw_irq.h
+++ b/include/asm-x86_64/hw_irq.h
@@ -19,8 +19,7 @@
19#include <asm/irq.h> 19#include <asm/irq.h>
20#include <linux/profile.h> 20#include <linux/profile.h>
21#include <linux/smp.h> 21#include <linux/smp.h>
22 22#include <linux/percpu.h>
23struct hw_interrupt_type;
24#endif 23#endif
25 24
26#define NMI_VECTOR 0x02 25#define NMI_VECTOR 0x02
@@ -75,9 +74,10 @@ struct hw_interrupt_type;
75 74
76 75
77#ifndef __ASSEMBLY__ 76#ifndef __ASSEMBLY__
78extern u8 irq_vector[NR_IRQ_VECTORS]; 77extern unsigned int irq_vector[NR_IRQ_VECTORS];
78typedef int vector_irq_t[NR_VECTORS];
79DECLARE_PER_CPU(vector_irq_t, vector_irq);
79#define IO_APIC_VECTOR(irq) (irq_vector[irq]) 80#define IO_APIC_VECTOR(irq) (irq_vector[irq])
80#define AUTO_ASSIGN -1
81 81
82/* 82/*
83 * Various low-level irq details needed by irq.c, process.c, 83 * Various low-level irq details needed by irq.c, process.c,
diff --git a/include/asm-x86_64/hypertransport.h b/include/asm-x86_64/hypertransport.h
new file mode 100644
index 000000000000..c16c6ff4bdd7
--- /dev/null
+++ b/include/asm-x86_64/hypertransport.h
@@ -0,0 +1,42 @@
1#ifndef ASM_HYPERTRANSPORT_H
2#define ASM_HYPERTRANSPORT_H
3
4/*
5 * Constants for x86 Hypertransport Interrupts.
6 */
7
8#define HT_IRQ_LOW_BASE 0xf8000000
9
10#define HT_IRQ_LOW_VECTOR_SHIFT 16
11#define HT_IRQ_LOW_VECTOR_MASK 0x00ff0000
12#define HT_IRQ_LOW_VECTOR(v) (((v) << HT_IRQ_LOW_VECTOR_SHIFT) & HT_IRQ_LOW_VECTOR_MASK)
13
14#define HT_IRQ_LOW_DEST_ID_SHIFT 8
15#define HT_IRQ_LOW_DEST_ID_MASK 0x0000ff00
16#define HT_IRQ_LOW_DEST_ID(v) (((v) << HT_IRQ_LOW_DEST_ID_SHIFT) & HT_IRQ_LOW_DEST_ID_MASK)
17
18#define HT_IRQ_LOW_DM_PHYSICAL 0x0000000
19#define HT_IRQ_LOW_DM_LOGICAL 0x0000040
20
21#define HT_IRQ_LOW_RQEOI_EDGE 0x0000000
22#define HT_IRQ_LOW_RQEOI_LEVEL 0x0000020
23
24
25#define HT_IRQ_LOW_MT_FIXED 0x0000000
26#define HT_IRQ_LOW_MT_ARBITRATED 0x0000004
27#define HT_IRQ_LOW_MT_SMI 0x0000008
28#define HT_IRQ_LOW_MT_NMI 0x000000c
29#define HT_IRQ_LOW_MT_INIT 0x0000010
30#define HT_IRQ_LOW_MT_STARTUP 0x0000014
31#define HT_IRQ_LOW_MT_EXTINT 0x0000018
32#define HT_IRQ_LOW_MT_LINT1 0x000008c
33#define HT_IRQ_LOW_MT_LINT0 0x0000098
34
35#define HT_IRQ_LOW_IRQ_MASKED 0x0000001
36
37
38#define HT_IRQ_HIGH_DEST_ID_SHIFT 0
39#define HT_IRQ_HIGH_DEST_ID_MASK 0x00ffffff
40#define HT_IRQ_HIGH_DEST_ID(v) ((((v) >> 8) << HT_IRQ_HIGH_DEST_ID_SHIFT) & HT_IRQ_HIGH_DEST_ID_MASK)
41
42#endif /* ASM_HYPERTRANSPORT_H */
diff --git a/include/asm-x86_64/io_apic.h b/include/asm-x86_64/io_apic.h
index 5d1b5c68e36e..171ec2dc8c04 100644
--- a/include/asm-x86_64/io_apic.h
+++ b/include/asm-x86_64/io_apic.h
@@ -10,46 +10,6 @@
10 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar 10 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
11 */ 11 */
12 12
13#ifdef CONFIG_PCI_MSI
14static inline int use_pci_vector(void) {return 1;}
15static inline void disable_edge_ioapic_vector(unsigned int vector) { }
16static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { }
17static inline void end_edge_ioapic_vector (unsigned int vector) { }
18#define startup_level_ioapic startup_level_ioapic_vector
19#define shutdown_level_ioapic mask_IO_APIC_vector
20#define enable_level_ioapic unmask_IO_APIC_vector
21#define disable_level_ioapic mask_IO_APIC_vector
22#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
23#define end_level_ioapic end_level_ioapic_vector
24#define set_ioapic_affinity set_ioapic_affinity_vector
25
26#define startup_edge_ioapic startup_edge_ioapic_vector
27#define shutdown_edge_ioapic disable_edge_ioapic_vector
28#define enable_edge_ioapic unmask_IO_APIC_vector
29#define disable_edge_ioapic disable_edge_ioapic_vector
30#define ack_edge_ioapic ack_edge_ioapic_vector
31#define end_edge_ioapic end_edge_ioapic_vector
32#else
33static inline int use_pci_vector(void) {return 0;}
34static inline void disable_edge_ioapic_irq(unsigned int irq) { }
35static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { }
36static inline void end_edge_ioapic_irq (unsigned int irq) { }
37#define startup_level_ioapic startup_level_ioapic_irq
38#define shutdown_level_ioapic mask_IO_APIC_irq
39#define enable_level_ioapic unmask_IO_APIC_irq
40#define disable_level_ioapic mask_IO_APIC_irq
41#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
42#define end_level_ioapic end_level_ioapic_irq
43#define set_ioapic_affinity set_ioapic_affinity_irq
44
45#define startup_edge_ioapic startup_edge_ioapic_irq
46#define shutdown_edge_ioapic disable_edge_ioapic_irq
47#define enable_edge_ioapic unmask_IO_APIC_irq
48#define disable_edge_ioapic disable_edge_ioapic_irq
49#define ack_edge_ioapic ack_edge_ioapic_irq
50#define end_edge_ioapic end_edge_ioapic_irq
51#endif
52
53#define APIC_MISMATCH_DEBUG 13#define APIC_MISMATCH_DEBUG
54 14
55#define IO_APIC_BASE(idx) \ 15#define IO_APIC_BASE(idx) \
@@ -202,13 +162,10 @@ extern int skip_ioapic_setup;
202extern int io_apic_get_version (int ioapic); 162extern int io_apic_get_version (int ioapic);
203extern int io_apic_get_redir_entries (int ioapic); 163extern int io_apic_get_redir_entries (int ioapic);
204extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int); 164extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
205extern int timer_uses_ioapic_pin_0;
206#endif 165#endif
207 166
208extern int sis_apic_bug; /* dummy */ 167extern int sis_apic_bug; /* dummy */
209 168
210extern int assign_irq_vector(int irq);
211
212void enable_NMI_through_LVT0 (void * dummy); 169void enable_NMI_through_LVT0 (void * dummy);
213 170
214extern spinlock_t i8259A_lock; 171extern spinlock_t i8259A_lock;
diff --git a/include/asm-x86_64/irq.h b/include/asm-x86_64/irq.h
index 43469d8ab71a..5006c6e75656 100644
--- a/include/asm-x86_64/irq.h
+++ b/include/asm-x86_64/irq.h
@@ -31,13 +31,8 @@
31 31
32#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */ 32#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */
33 33
34#ifdef CONFIG_PCI_MSI 34#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
35#define NR_IRQS FIRST_SYSTEM_VECTOR
36#define NR_IRQ_VECTORS NR_IRQS 35#define NR_IRQ_VECTORS NR_IRQS
37#else
38#define NR_IRQS 224
39#define NR_IRQ_VECTORS (32 * NR_CPUS)
40#endif
41 36
42static __inline__ int irq_canonicalize(int irq) 37static __inline__ int irq_canonicalize(int irq)
43{ 38{
diff --git a/include/asm-x86_64/msi.h b/include/asm-x86_64/msi.h
deleted file mode 100644
index 3ad2346624b2..000000000000
--- a/include/asm-x86_64/msi.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
4 */
5
6#ifndef ASM_MSI_H
7#define ASM_MSI_H
8
9#include <asm/desc.h>
10#include <asm/mach_apic.h>
11#include <asm/smp.h>
12
13#define LAST_DEVICE_VECTOR (FIRST_SYSTEM_VECTOR - 1)
14#define MSI_TARGET_CPU_SHIFT 12
15
16extern struct msi_ops msi_apic_ops;
17
18static inline int msi_arch_init(void)
19{
20 msi_register(&msi_apic_ops);
21 return 0;
22}
23
24#endif /* ASM_MSI_H */
diff --git a/include/asm-x86_64/msidef.h b/include/asm-x86_64/msidef.h
new file mode 100644
index 000000000000..5b8acddb70fb
--- /dev/null
+++ b/include/asm-x86_64/msidef.h
@@ -0,0 +1,47 @@
1#ifndef ASM_MSIDEF_H
2#define ASM_MSIDEF_H
3
4/*
5 * Constants for Intel APIC based MSI messages.
6 */
7
8/*
9 * Shifts for MSI data
10 */
11
12#define MSI_DATA_VECTOR_SHIFT 0
13#define MSI_DATA_VECTOR_MASK 0x000000ff
14#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & MSI_DATA_VECTOR_MASK)
15
16#define MSI_DATA_DELIVERY_MODE_SHIFT 8
17#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
18#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
19
20#define MSI_DATA_LEVEL_SHIFT 14
21#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
22#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
23
24#define MSI_DATA_TRIGGER_SHIFT 15
25#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
26#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
27
28/*
29 * Shift/mask fields for msi address
30 */
31
32#define MSI_ADDR_BASE_HI 0
33#define MSI_ADDR_BASE_LO 0xfee00000
34
35#define MSI_ADDR_DEST_MODE_SHIFT 2
36#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
37#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
38
39#define MSI_ADDR_REDIRECTION_SHIFT 3
40#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) /* dedicated cpu */
41#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) /* lowest priority */
42
43#define MSI_ADDR_DEST_ID_SHIFT 12
44#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
45#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MSI_ADDR_DEST_ID_MASK)
46
47#endif /* ASM_MSIDEF_H */
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index f7a52e19b4be..ea005c0a79fd 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -46,6 +46,7 @@ header-y += coff.h
46header-y += comstats.h 46header-y += comstats.h
47header-y += consolemap.h 47header-y += consolemap.h
48header-y += cycx_cfm.h 48header-y += cycx_cfm.h
49header-y += dlm_device.h
49header-y += dm-ioctl.h 50header-y += dm-ioctl.h
50header-y += dn.h 51header-y += dn.h
51header-y += dqblk_v1.h 52header-y += dqblk_v1.h
@@ -104,6 +105,7 @@ header-y += ixjuser.h
104header-y += jffs2.h 105header-y += jffs2.h
105header-y += keyctl.h 106header-y += keyctl.h
106header-y += limits.h 107header-y += limits.h
108header-y += lock_dlm_plock.h
107header-y += magic.h 109header-y += magic.h
108header-y += major.h 110header-y += major.h
109header-y += matroxfb.h 111header-y += matroxfb.h
@@ -156,12 +158,10 @@ header-y += toshiba.h
156header-y += ultrasound.h 158header-y += ultrasound.h
157header-y += un.h 159header-y += un.h
158header-y += utime.h 160header-y += utime.h
159header-y += utsname.h
160header-y += video_decoder.h 161header-y += video_decoder.h
161header-y += video_encoder.h 162header-y += video_encoder.h
162header-y += videotext.h 163header-y += videotext.h
163header-y += vt.h 164header-y += vt.h
164header-y += wavefront.h
165header-y += wireless.h 165header-y += wireless.h
166header-y += xattr.h 166header-y += xattr.h
167header-y += x25.h 167header-y += x25.h
@@ -194,6 +194,7 @@ unifdef-y += cyclades.h
194unifdef-y += dccp.h 194unifdef-y += dccp.h
195unifdef-y += dirent.h 195unifdef-y += dirent.h
196unifdef-y += divert.h 196unifdef-y += divert.h
197unifdef-y += dlm.h
197unifdef-y += elfcore.h 198unifdef-y += elfcore.h
198unifdef-y += errno.h 199unifdef-y += errno.h
199unifdef-y += errqueue.h 200unifdef-y += errqueue.h
@@ -210,6 +211,7 @@ unifdef-y += ftape.h
210unifdef-y += gameport.h 211unifdef-y += gameport.h
211unifdef-y += generic_serial.h 212unifdef-y += generic_serial.h
212unifdef-y += genhd.h 213unifdef-y += genhd.h
214unifdef-y += gfs2_ondisk.h
213unifdef-y += hayesesp.h 215unifdef-y += hayesesp.h
214unifdef-y += hdlcdrv.h 216unifdef-y += hdlcdrv.h
215unifdef-y += hdlc.h 217unifdef-y += hdlc.h
@@ -333,6 +335,7 @@ unifdef-y += unistd.h
333unifdef-y += usb_ch9.h 335unifdef-y += usb_ch9.h
334unifdef-y += usbdevice_fs.h 336unifdef-y += usbdevice_fs.h
335unifdef-y += user.h 337unifdef-y += user.h
338unifdef-y += utsname.h
336unifdef-y += videodev2.h 339unifdef-y += videodev2.h
337unifdef-y += videodev.h 340unifdef-y += videodev.h
338unifdef-y += wait.h 341unifdef-y += wait.h
diff --git a/include/linux/ac97_codec.h b/include/linux/ac97_codec.h
index 2ed2fd855133..22eb9367235a 100644
--- a/include/linux/ac97_codec.h
+++ b/include/linux/ac97_codec.h
@@ -331,8 +331,6 @@ extern int ac97_read_proc (char *page_out, char **start, off_t off,
331extern int ac97_probe_codec(struct ac97_codec *); 331extern int ac97_probe_codec(struct ac97_codec *);
332extern unsigned int ac97_set_adc_rate(struct ac97_codec *codec, unsigned int rate); 332extern unsigned int ac97_set_adc_rate(struct ac97_codec *codec, unsigned int rate);
333extern unsigned int ac97_set_dac_rate(struct ac97_codec *codec, unsigned int rate); 333extern unsigned int ac97_set_dac_rate(struct ac97_codec *codec, unsigned int rate);
334extern int ac97_save_state(struct ac97_codec *codec);
335extern int ac97_restore_state(struct ac97_codec *codec);
336 334
337extern struct ac97_codec *ac97_alloc_codec(void); 335extern struct ac97_codec *ac97_alloc_codec(void);
338extern void ac97_release_codec(struct ac97_codec *codec); 336extern void ac97_release_codec(struct ac97_codec *codec);
@@ -346,9 +344,6 @@ struct ac97_driver {
346 void (*remove) (struct ac97_codec *codec, struct ac97_driver *driver); 344 void (*remove) (struct ac97_codec *codec, struct ac97_driver *driver);
347}; 345};
348 346
349extern int ac97_register_driver(struct ac97_driver *driver);
350extern void ac97_unregister_driver(struct ac97_driver *driver);
351
352/* quirk types */ 347/* quirk types */
353enum { 348enum {
354 AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */ 349 AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */
diff --git a/include/linux/audit.h b/include/linux/audit.h
index c3aa09751814..b2ca666d9997 100644
--- a/include/linux/audit.h
+++ b/include/linux/audit.h
@@ -75,7 +75,7 @@
75#define AUDIT_DAEMON_CONFIG 1203 /* Daemon config change */ 75#define AUDIT_DAEMON_CONFIG 1203 /* Daemon config change */
76 76
77#define AUDIT_SYSCALL 1300 /* Syscall event */ 77#define AUDIT_SYSCALL 1300 /* Syscall event */
78#define AUDIT_FS_WATCH 1301 /* Filesystem watch event */ 78/* #define AUDIT_FS_WATCH 1301 * Deprecated */
79#define AUDIT_PATH 1302 /* Filename path information */ 79#define AUDIT_PATH 1302 /* Filename path information */
80#define AUDIT_IPC 1303 /* IPC record */ 80#define AUDIT_IPC 1303 /* IPC record */
81#define AUDIT_SOCKETCALL 1304 /* sys_socketcall arguments */ 81#define AUDIT_SOCKETCALL 1304 /* sys_socketcall arguments */
@@ -88,6 +88,7 @@
88#define AUDIT_MQ_SENDRECV 1313 /* POSIX MQ send/receive record type */ 88#define AUDIT_MQ_SENDRECV 1313 /* POSIX MQ send/receive record type */
89#define AUDIT_MQ_NOTIFY 1314 /* POSIX MQ notify record type */ 89#define AUDIT_MQ_NOTIFY 1314 /* POSIX MQ notify record type */
90#define AUDIT_MQ_GETSETATTR 1315 /* POSIX MQ get/set attribute record type */ 90#define AUDIT_MQ_GETSETATTR 1315 /* POSIX MQ get/set attribute record type */
91#define AUDIT_KERNEL_OTHER 1316 /* For use by 3rd party modules */
91 92
92#define AUDIT_AVC 1400 /* SE Linux avc denial or grant */ 93#define AUDIT_AVC 1400 /* SE Linux avc denial or grant */
93#define AUDIT_SELINUX_ERR 1401 /* Internal SE Linux Errors */ 94#define AUDIT_SELINUX_ERR 1401 /* Internal SE Linux Errors */
diff --git a/include/linux/debug_locks.h b/include/linux/debug_locks.h
index 88dafa246d87..952bee79a8f3 100644
--- a/include/linux/debug_locks.h
+++ b/include/linux/debug_locks.h
@@ -43,6 +43,8 @@ extern int debug_locks_off(void);
43# define locking_selftest() do { } while (0) 43# define locking_selftest() do { } while (0)
44#endif 44#endif
45 45
46struct task_struct;
47
46#ifdef CONFIG_LOCKDEP 48#ifdef CONFIG_LOCKDEP
47extern void debug_show_all_locks(void); 49extern void debug_show_all_locks(void);
48extern void debug_show_held_locks(struct task_struct *task); 50extern void debug_show_held_locks(struct task_struct *task);
diff --git a/include/linux/dlm.h b/include/linux/dlm.h
new file mode 100644
index 000000000000..1b1dcb9a40bb
--- /dev/null
+++ b/include/linux/dlm.h
@@ -0,0 +1,302 @@
1/******************************************************************************
2*******************************************************************************
3**
4** Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved.
5** Copyright (C) 2004-2005 Red Hat, Inc. All rights reserved.
6**
7** This copyrighted material is made available to anyone wishing to use,
8** modify, copy, or redistribute it subject to the terms and conditions
9** of the GNU General Public License v.2.
10**
11*******************************************************************************
12******************************************************************************/
13
14#ifndef __DLM_DOT_H__
15#define __DLM_DOT_H__
16
17/*
18 * Interface to Distributed Lock Manager (DLM)
19 * routines and structures to use DLM lockspaces
20 */
21
22/*
23 * Lock Modes
24 */
25
26#define DLM_LOCK_IV -1 /* invalid */
27#define DLM_LOCK_NL 0 /* null */
28#define DLM_LOCK_CR 1 /* concurrent read */
29#define DLM_LOCK_CW 2 /* concurrent write */
30#define DLM_LOCK_PR 3 /* protected read */
31#define DLM_LOCK_PW 4 /* protected write */
32#define DLM_LOCK_EX 5 /* exclusive */
33
34/*
35 * Maximum size in bytes of a dlm_lock name
36 */
37
38#define DLM_RESNAME_MAXLEN 64
39
40/*
41 * Flags to dlm_lock
42 *
43 * DLM_LKF_NOQUEUE
44 *
45 * Do not queue the lock request on the wait queue if it cannot be granted
46 * immediately. If the lock cannot be granted because of this flag, DLM will
47 * either return -EAGAIN from the dlm_lock call or will return 0 from
48 * dlm_lock and -EAGAIN in the lock status block when the AST is executed.
49 *
50 * DLM_LKF_CANCEL
51 *
52 * Used to cancel a pending lock request or conversion. A converting lock is
53 * returned to its previously granted mode.
54 *
55 * DLM_LKF_CONVERT
56 *
57 * Indicates a lock conversion request. For conversions the name and namelen
58 * are ignored and the lock ID in the LKSB is used to identify the lock.
59 *
60 * DLM_LKF_VALBLK
61 *
62 * Requests DLM to return the current contents of the lock value block in the
63 * lock status block. When this flag is set in a lock conversion from PW or EX
64 * modes, DLM assigns the value specified in the lock status block to the lock
65 * value block of the lock resource. The LVB is a DLM_LVB_LEN size array
66 * containing application-specific information.
67 *
68 * DLM_LKF_QUECVT
69 *
70 * Force a conversion request to be queued, even if it is compatible with
71 * the granted modes of other locks on the same resource.
72 *
73 * DLM_LKF_IVVALBLK
74 *
75 * Invalidate the lock value block.
76 *
77 * DLM_LKF_CONVDEADLK
78 *
79 * Allows the dlm to resolve conversion deadlocks internally by demoting the
80 * granted mode of a converting lock to NL. The DLM_SBF_DEMOTED flag is
81 * returned for a conversion that's been effected by this.
82 *
83 * DLM_LKF_PERSISTENT
84 *
85 * Only relevant to locks originating in userspace. A persistent lock will not
86 * be removed if the process holding the lock exits.
87 *
88 * DLM_LKF_NODLKWT
89 * DLM_LKF_NODLCKBLK
90 *
91 * net yet implemented
92 *
93 * DLM_LKF_EXPEDITE
94 *
95 * Used only with new requests for NL mode locks. Tells the lock manager
96 * to grant the lock, ignoring other locks in convert and wait queues.
97 *
98 * DLM_LKF_NOQUEUEBAST
99 *
100 * Send blocking AST's before returning -EAGAIN to the caller. It is only
101 * used along with the NOQUEUE flag. Blocking AST's are not sent for failed
102 * NOQUEUE requests otherwise.
103 *
104 * DLM_LKF_HEADQUE
105 *
106 * Add a lock to the head of the convert or wait queue rather than the tail.
107 *
108 * DLM_LKF_NOORDER
109 *
110 * Disregard the standard grant order rules and grant a lock as soon as it
111 * is compatible with other granted locks.
112 *
113 * DLM_LKF_ORPHAN
114 *
115 * not yet implemented
116 *
117 * DLM_LKF_ALTPR
118 *
119 * If the requested mode cannot be granted immediately, try to grant the lock
120 * in PR mode instead. If this alternate mode is granted instead of the
121 * requested mode, DLM_SBF_ALTMODE is returned in the lksb.
122 *
123 * DLM_LKF_ALTCW
124 *
125 * The same as ALTPR, but the alternate mode is CW.
126 *
127 * DLM_LKF_FORCEUNLOCK
128 *
129 * Unlock the lock even if it is converting or waiting or has sublocks.
130 * Only really for use by the userland device.c code.
131 *
132 */
133
134#define DLM_LKF_NOQUEUE 0x00000001
135#define DLM_LKF_CANCEL 0x00000002
136#define DLM_LKF_CONVERT 0x00000004
137#define DLM_LKF_VALBLK 0x00000008
138#define DLM_LKF_QUECVT 0x00000010
139#define DLM_LKF_IVVALBLK 0x00000020
140#define DLM_LKF_CONVDEADLK 0x00000040
141#define DLM_LKF_PERSISTENT 0x00000080
142#define DLM_LKF_NODLCKWT 0x00000100
143#define DLM_LKF_NODLCKBLK 0x00000200
144#define DLM_LKF_EXPEDITE 0x00000400
145#define DLM_LKF_NOQUEUEBAST 0x00000800
146#define DLM_LKF_HEADQUE 0x00001000
147#define DLM_LKF_NOORDER 0x00002000
148#define DLM_LKF_ORPHAN 0x00004000
149#define DLM_LKF_ALTPR 0x00008000
150#define DLM_LKF_ALTCW 0x00010000
151#define DLM_LKF_FORCEUNLOCK 0x00020000
152
153/*
154 * Some return codes that are not in errno.h
155 */
156
157#define DLM_ECANCEL 0x10001
158#define DLM_EUNLOCK 0x10002
159
160typedef void dlm_lockspace_t;
161
162/*
163 * Lock status block
164 *
165 * Use this structure to specify the contents of the lock value block. For a
166 * conversion request, this structure is used to specify the lock ID of the
167 * lock. DLM writes the status of the lock request and the lock ID assigned
168 * to the request in the lock status block.
169 *
170 * sb_lkid: the returned lock ID. It is set on new (non-conversion) requests.
171 * It is available when dlm_lock returns.
172 *
173 * sb_lvbptr: saves or returns the contents of the lock's LVB according to rules
174 * shown for the DLM_LKF_VALBLK flag.
175 *
176 * sb_flags: DLM_SBF_DEMOTED is returned if in the process of promoting a lock,
177 * it was first demoted to NL to avoid conversion deadlock.
178 * DLM_SBF_VALNOTVALID is returned if the resource's LVB is marked invalid.
179 *
180 * sb_status: the returned status of the lock request set prior to AST
181 * execution. Possible return values:
182 *
183 * 0 if lock request was successful
184 * -EAGAIN if request would block and is flagged DLM_LKF_NOQUEUE
185 * -ENOMEM if there is no memory to process request
186 * -EINVAL if there are invalid parameters
187 * -DLM_EUNLOCK if unlock request was successful
188 * -DLM_ECANCEL if a cancel completed successfully
189 */
190
191#define DLM_SBF_DEMOTED 0x01
192#define DLM_SBF_VALNOTVALID 0x02
193#define DLM_SBF_ALTMODE 0x04
194
195struct dlm_lksb {
196 int sb_status;
197 uint32_t sb_lkid;
198 char sb_flags;
199 char * sb_lvbptr;
200};
201
202
203#ifdef __KERNEL__
204
205#define DLM_LSFL_NODIR 0x00000001
206
207/*
208 * dlm_new_lockspace
209 *
210 * Starts a lockspace with the given name. If the named lockspace exists in
211 * the cluster, the calling node joins it.
212 */
213
214int dlm_new_lockspace(char *name, int namelen, dlm_lockspace_t **lockspace,
215 uint32_t flags, int lvblen);
216
217/*
218 * dlm_release_lockspace
219 *
220 * Stop a lockspace.
221 */
222
223int dlm_release_lockspace(dlm_lockspace_t *lockspace, int force);
224
225/*
226 * dlm_lock
227 *
228 * Make an asyncronous request to acquire or convert a lock on a named
229 * resource.
230 *
231 * lockspace: context for the request
232 * mode: the requested mode of the lock (DLM_LOCK_)
233 * lksb: lock status block for input and async return values
234 * flags: input flags (DLM_LKF_)
235 * name: name of the resource to lock, can be binary
236 * namelen: the length in bytes of the resource name (MAX_RESNAME_LEN)
237 * parent: the lock ID of a parent lock or 0 if none
238 * lockast: function DLM executes when it completes processing the request
239 * astarg: argument passed to lockast and bast functions
240 * bast: function DLM executes when this lock later blocks another request
241 *
242 * Returns:
243 * 0 if request is successfully queued for processing
244 * -EINVAL if any input parameters are invalid
245 * -EAGAIN if request would block and is flagged DLM_LKF_NOQUEUE
246 * -ENOMEM if there is no memory to process request
247 * -ENOTCONN if there is a communication error
248 *
249 * If the call to dlm_lock returns an error then the operation has failed and
250 * the AST routine will not be called. If dlm_lock returns 0 it is still
251 * possible that the lock operation will fail. The AST routine will be called
252 * when the locking is complete and the status is returned in the lksb.
253 *
254 * If the AST routines or parameter are passed to a conversion operation then
255 * they will overwrite those values that were passed to a previous dlm_lock
256 * call.
257 *
258 * AST routines should not block (at least not for long), but may make
259 * any locking calls they please.
260 */
261
262int dlm_lock(dlm_lockspace_t *lockspace,
263 int mode,
264 struct dlm_lksb *lksb,
265 uint32_t flags,
266 void *name,
267 unsigned int namelen,
268 uint32_t parent_lkid,
269 void (*lockast) (void *astarg),
270 void *astarg,
271 void (*bast) (void *astarg, int mode));
272
273/*
274 * dlm_unlock
275 *
276 * Asynchronously release a lock on a resource. The AST routine is called
277 * when the resource is successfully unlocked.
278 *
279 * lockspace: context for the request
280 * lkid: the lock ID as returned in the lksb
281 * flags: input flags (DLM_LKF_)
282 * lksb: if NULL the lksb parameter passed to last lock request is used
283 * astarg: the arg used with the completion ast for the unlock
284 *
285 * Returns:
286 * 0 if request is successfully queued for processing
287 * -EINVAL if any input parameters are invalid
288 * -ENOTEMPTY if the lock still has sublocks
289 * -EBUSY if the lock is waiting for a remote lock operation
290 * -ENOTCONN if there is a communication error
291 */
292
293int dlm_unlock(dlm_lockspace_t *lockspace,
294 uint32_t lkid,
295 uint32_t flags,
296 struct dlm_lksb *lksb,
297 void *astarg);
298
299#endif /* __KERNEL__ */
300
301#endif /* __DLM_DOT_H__ */
302
diff --git a/include/linux/dlm_device.h b/include/linux/dlm_device.h
new file mode 100644
index 000000000000..2a2dd189b9fd
--- /dev/null
+++ b/include/linux/dlm_device.h
@@ -0,0 +1,86 @@
1/******************************************************************************
2*******************************************************************************
3**
4** Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved.
5** Copyright (C) 2004-2005 Red Hat, Inc. All rights reserved.
6**
7** This copyrighted material is made available to anyone wishing to use,
8** modify, copy, or redistribute it subject to the terms and conditions
9** of the GNU General Public License v.2.
10**
11*******************************************************************************
12******************************************************************************/
13
14/* This is the device interface for dlm, most users will use a library
15 * interface.
16 */
17
18#define DLM_USER_LVB_LEN 32
19
20/* Version of the device interface */
21#define DLM_DEVICE_VERSION_MAJOR 5
22#define DLM_DEVICE_VERSION_MINOR 0
23#define DLM_DEVICE_VERSION_PATCH 0
24
25/* struct passed to the lock write */
26struct dlm_lock_params {
27 __u8 mode;
28 __u8 namelen;
29 __u16 flags;
30 __u32 lkid;
31 __u32 parent;
32 void __user *castparam;
33 void __user *castaddr;
34 void __user *bastparam;
35 void __user *bastaddr;
36 struct dlm_lksb __user *lksb;
37 char lvb[DLM_USER_LVB_LEN];
38 char name[0];
39};
40
41struct dlm_lspace_params {
42 __u32 flags;
43 __u32 minor;
44 char name[0];
45};
46
47struct dlm_write_request {
48 __u32 version[3];
49 __u8 cmd;
50 __u8 is64bit;
51 __u8 unused[2];
52
53 union {
54 struct dlm_lock_params lock;
55 struct dlm_lspace_params lspace;
56 } i;
57};
58
59/* struct read from the "device" fd,
60 consists mainly of userspace pointers for the library to use */
61struct dlm_lock_result {
62 __u32 length;
63 void __user * user_astaddr;
64 void __user * user_astparam;
65 struct dlm_lksb __user * user_lksb;
66 struct dlm_lksb lksb;
67 __u8 bast_mode;
68 __u8 unused[3];
69 /* Offsets may be zero if no data is present */
70 __u32 lvb_offset;
71};
72
73/* Commands passed to the device */
74#define DLM_USER_LOCK 1
75#define DLM_USER_UNLOCK 2
76#define DLM_USER_QUERY 3
77#define DLM_USER_CREATE_LOCKSPACE 4
78#define DLM_USER_REMOVE_LOCKSPACE 5
79
80/* Arbitrary length restriction */
81#define MAX_LS_NAME_LEN 64
82
83/* Lockspace flags */
84#define DLM_USER_LSFLG_AUTOFREE 1
85#define DLM_USER_LSFLG_FORCEFREE 2
86
diff --git a/include/linux/fs.h b/include/linux/fs.h
index f53bf4ff1955..34406ed467c3 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -250,6 +250,8 @@ extern int dir_notify_enable;
250#define FS_NOTAIL_FL 0x00008000 /* file tail should not be merged */ 250#define FS_NOTAIL_FL 0x00008000 /* file tail should not be merged */
251#define FS_DIRSYNC_FL 0x00010000 /* dirsync behaviour (directories only) */ 251#define FS_DIRSYNC_FL 0x00010000 /* dirsync behaviour (directories only) */
252#define FS_TOPDIR_FL 0x00020000 /* Top of directory hierarchies*/ 252#define FS_TOPDIR_FL 0x00020000 /* Top of directory hierarchies*/
253#define FS_EXTENT_FL 0x00080000 /* Extents */
254#define FS_DIRECTIO_FL 0x00100000 /* Use direct i/o */
253#define FS_RESERVED_FL 0x80000000 /* reserved for ext2 lib */ 255#define FS_RESERVED_FL 0x80000000 /* reserved for ext2 lib */
254 256
255#define FS_FL_USER_VISIBLE 0x0003DFFF /* User visible flags */ 257#define FS_FL_USER_VISIBLE 0x0003DFFF /* User visible flags */
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 16fbe59edeb1..3da29e2d524a 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -46,18 +46,17 @@
46 46
47struct gianfar_platform_data { 47struct gianfar_platform_data {
48 /* device specific information */ 48 /* device specific information */
49 u32 device_flags; 49 u32 device_flags;
50
51 /* board specific information */ 50 /* board specific information */
52 u32 board_flags; 51 u32 board_flags;
53 u32 bus_id; 52 u32 bus_id;
54 u32 phy_id; 53 u32 phy_id;
55 u8 mac_addr[6]; 54 u8 mac_addr[6];
56}; 55};
57 56
58struct gianfar_mdio_data { 57struct gianfar_mdio_data {
59 /* board specific information */ 58 /* board specific information */
60 int irq[32]; 59 int irq[32];
61}; 60};
62 61
63/* Flags related to gianfar device features */ 62/* Flags related to gianfar device features */
@@ -76,14 +75,13 @@ struct gianfar_mdio_data {
76 75
77struct fsl_i2c_platform_data { 76struct fsl_i2c_platform_data {
78 /* device specific information */ 77 /* device specific information */
79 u32 device_flags; 78 u32 device_flags;
80}; 79};
81 80
82/* Flags related to I2C device features */ 81/* Flags related to I2C device features */
83#define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001 82#define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001
84#define FSL_I2C_DEV_CLOCK_5200 0x00000002 83#define FSL_I2C_DEV_CLOCK_5200 0x00000002
85 84
86
87enum fsl_usb2_operating_modes { 85enum fsl_usb2_operating_modes {
88 FSL_USB2_MPH_HOST, 86 FSL_USB2_MPH_HOST,
89 FSL_USB2_DR_HOST, 87 FSL_USB2_DR_HOST,
@@ -101,9 +99,9 @@ enum fsl_usb2_phy_modes {
101 99
102struct fsl_usb2_platform_data { 100struct fsl_usb2_platform_data {
103 /* board specific information */ 101 /* board specific information */
104 enum fsl_usb2_operating_modes operating_mode; 102 enum fsl_usb2_operating_modes operating_mode;
105 enum fsl_usb2_phy_modes phy_mode; 103 enum fsl_usb2_phy_modes phy_mode;
106 unsigned int port_enables; 104 unsigned int port_enables;
107}; 105};
108 106
109/* Flags in fsl_usb2_mph_platform_data */ 107/* Flags in fsl_usb2_mph_platform_data */
@@ -121,5 +119,44 @@ struct fsl_spi_platform_data {
121 u32 sysclk; 119 u32 sysclk;
122}; 120};
123 121
124#endif /* _FSL_DEVICE_H_ */ 122/* Ethernet interface (phy management and speed)
125#endif /* __KERNEL__ */ 123*/
124enum enet_interface {
125 ENET_10_MII, /* 10 Base T, MII interface */
126 ENET_10_RMII, /* 10 Base T, RMII interface */
127 ENET_10_RGMII, /* 10 Base T, RGMII interface */
128 ENET_100_MII, /* 100 Base T, MII interface */
129 ENET_100_RMII, /* 100 Base T, RMII interface */
130 ENET_100_RGMII, /* 100 Base T, RGMII interface */
131 ENET_1000_GMII, /* 1000 Base T, GMII interface */
132 ENET_1000_RGMII, /* 1000 Base T, RGMII interface */
133 ENET_1000_TBI, /* 1000 Base T, TBI interface */
134 ENET_1000_RTBI /* 1000 Base T, RTBI interface */
135};
136
137struct ucc_geth_platform_data {
138 /* device specific information */
139 u32 device_flags;
140 u32 phy_reg_addr;
141
142 /* board specific information */
143 u32 board_flags;
144 u8 rx_clock;
145 u8 tx_clock;
146 u32 phy_id;
147 enum enet_interface phy_interface;
148 u32 phy_interrupt;
149 u8 mac_addr[6];
150};
151
152/* Flags related to UCC Gigabit Ethernet device features */
153#define FSL_UGETH_DEV_HAS_GIGABIT 0x00000001
154#define FSL_UGETH_DEV_HAS_COALESCE 0x00000002
155#define FSL_UGETH_DEV_HAS_RMON 0x00000004
156
157/* Flags in ucc_geth_platform_data */
158#define FSL_UGETH_BRD_HAS_PHY_INTR 0x00000001
159 /* if not set use a timer */
160
161#endif /* _FSL_DEVICE_H_ */
162#endif /* __KERNEL__ */
diff --git a/include/linux/gfs2_ondisk.h b/include/linux/gfs2_ondisk.h
new file mode 100644
index 000000000000..a7ae7c177cac
--- /dev/null
+++ b/include/linux/gfs2_ondisk.h
@@ -0,0 +1,443 @@
1/*
2 * Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved.
3 * Copyright (C) 2004-2006 Red Hat, Inc. All rights reserved.
4 *
5 * This copyrighted material is made available to anyone wishing to use,
6 * modify, copy, or redistribute it subject to the terms and conditions
7 * of the GNU General Public License v.2.
8 */
9
10#ifndef __GFS2_ONDISK_DOT_H__
11#define __GFS2_ONDISK_DOT_H__
12
13#define GFS2_MAGIC 0x01161970
14#define GFS2_BASIC_BLOCK 512
15#define GFS2_BASIC_BLOCK_SHIFT 9
16
17/* Lock numbers of the LM_TYPE_NONDISK type */
18
19#define GFS2_MOUNT_LOCK 0
20#define GFS2_LIVE_LOCK 1
21#define GFS2_TRANS_LOCK 2
22#define GFS2_RENAME_LOCK 3
23
24/* Format numbers for various metadata types */
25
26#define GFS2_FORMAT_NONE 0
27#define GFS2_FORMAT_SB 100
28#define GFS2_FORMAT_RG 200
29#define GFS2_FORMAT_RB 300
30#define GFS2_FORMAT_DI 400
31#define GFS2_FORMAT_IN 500
32#define GFS2_FORMAT_LF 600
33#define GFS2_FORMAT_JD 700
34#define GFS2_FORMAT_LH 800
35#define GFS2_FORMAT_LD 900
36#define GFS2_FORMAT_LB 1000
37#define GFS2_FORMAT_EA 1600
38#define GFS2_FORMAT_ED 1700
39#define GFS2_FORMAT_QC 1400
40/* These are format numbers for entities contained in files */
41#define GFS2_FORMAT_RI 1100
42#define GFS2_FORMAT_DE 1200
43#define GFS2_FORMAT_QU 1500
44/* These are part of the superblock */
45#define GFS2_FORMAT_FS 1801
46#define GFS2_FORMAT_MULTI 1900
47
48/*
49 * An on-disk inode number
50 */
51
52struct gfs2_inum {
53 __be64 no_formal_ino;
54 __be64 no_addr;
55};
56
57static inline int gfs2_inum_equal(const struct gfs2_inum *ino1,
58 const struct gfs2_inum *ino2)
59{
60 return ino1->no_formal_ino == ino2->no_formal_ino &&
61 ino1->no_addr == ino2->no_addr;
62}
63
64/*
65 * Generic metadata head structure
66 * Every inplace buffer logged in the journal must start with this.
67 */
68
69#define GFS2_METATYPE_NONE 0
70#define GFS2_METATYPE_SB 1
71#define GFS2_METATYPE_RG 2
72#define GFS2_METATYPE_RB 3
73#define GFS2_METATYPE_DI 4
74#define GFS2_METATYPE_IN 5
75#define GFS2_METATYPE_LF 6
76#define GFS2_METATYPE_JD 7
77#define GFS2_METATYPE_LH 8
78#define GFS2_METATYPE_LD 9
79#define GFS2_METATYPE_LB 12
80#define GFS2_METATYPE_EA 10
81#define GFS2_METATYPE_ED 11
82#define GFS2_METATYPE_QC 14
83
84struct gfs2_meta_header {
85 __be32 mh_magic;
86 __be32 mh_type;
87 __be64 __pad0; /* Was generation number in gfs1 */
88 __be32 mh_format;
89 __be32 __pad1; /* Was incarnation number in gfs1 */
90};
91
92/*
93 * super-block structure
94 *
95 * It's probably good if SIZEOF_SB <= GFS2_BASIC_BLOCK (512 bytes)
96 *
97 * Order is important, need to be able to read old superblocks to do on-disk
98 * version upgrades.
99 */
100
101/* Address of superblock in GFS2 basic blocks */
102#define GFS2_SB_ADDR 128
103
104/* The lock number for the superblock (must be zero) */
105#define GFS2_SB_LOCK 0
106
107/* Requirement: GFS2_LOCKNAME_LEN % 8 == 0
108 Includes: the fencing zero at the end */
109#define GFS2_LOCKNAME_LEN 64
110
111struct gfs2_sb {
112 struct gfs2_meta_header sb_header;
113
114 __be32 sb_fs_format;
115 __be32 sb_multihost_format;
116 __u32 __pad0; /* Was superblock flags in gfs1 */
117
118 __be32 sb_bsize;
119 __be32 sb_bsize_shift;
120 __u32 __pad1; /* Was journal segment size in gfs1 */
121
122 struct gfs2_inum sb_master_dir; /* Was jindex dinode in gfs1 */
123 struct gfs2_inum __pad2; /* Was rindex dinode in gfs1 */
124 struct gfs2_inum sb_root_dir;
125
126 char sb_lockproto[GFS2_LOCKNAME_LEN];
127 char sb_locktable[GFS2_LOCKNAME_LEN];
128 /* In gfs1, quota and license dinodes followed */
129};
130
131/*
132 * resource index structure
133 */
134
135struct gfs2_rindex {
136 __be64 ri_addr; /* grp block disk address */
137 __be32 ri_length; /* length of rgrp header in fs blocks */
138 __u32 __pad;
139
140 __be64 ri_data0; /* first data location */
141 __be32 ri_data; /* num of data blocks in rgrp */
142
143 __be32 ri_bitbytes; /* number of bytes in data bitmaps */
144
145 __u8 ri_reserved[64];
146};
147
148/*
149 * resource group header structure
150 */
151
152/* Number of blocks per byte in rgrp */
153#define GFS2_NBBY 4
154#define GFS2_BIT_SIZE 2
155#define GFS2_BIT_MASK 0x00000003
156
157#define GFS2_BLKST_FREE 0
158#define GFS2_BLKST_USED 1
159#define GFS2_BLKST_UNLINKED 2
160#define GFS2_BLKST_DINODE 3
161
162#define GFS2_RGF_JOURNAL 0x00000001
163#define GFS2_RGF_METAONLY 0x00000002
164#define GFS2_RGF_DATAONLY 0x00000004
165#define GFS2_RGF_NOALLOC 0x00000008
166
167struct gfs2_rgrp {
168 struct gfs2_meta_header rg_header;
169
170 __be32 rg_flags;
171 __be32 rg_free;
172 __be32 rg_dinodes;
173 __be32 __pad;
174 __be64 rg_igeneration;
175
176 __u8 rg_reserved[80]; /* Several fields from gfs1 now reserved */
177};
178
179/*
180 * quota structure
181 */
182
183struct gfs2_quota {
184 __be64 qu_limit;
185 __be64 qu_warn;
186 __be64 qu_value;
187 __u8 qu_reserved[64];
188};
189
190/*
191 * dinode structure
192 */
193
194#define GFS2_MAX_META_HEIGHT 10
195#define GFS2_DIR_MAX_DEPTH 17
196
197#define DT2IF(dt) (((dt) << 12) & S_IFMT)
198#define IF2DT(sif) (((sif) & S_IFMT) >> 12)
199
200enum {
201 gfs2fl_Jdata = 0,
202 gfs2fl_ExHash = 1,
203 gfs2fl_Unused = 2,
204 gfs2fl_EaIndirect = 3,
205 gfs2fl_Directio = 4,
206 gfs2fl_Immutable = 5,
207 gfs2fl_AppendOnly = 6,
208 gfs2fl_NoAtime = 7,
209 gfs2fl_Sync = 8,
210 gfs2fl_System = 9,
211 gfs2fl_TruncInProg = 29,
212 gfs2fl_InheritDirectio = 30,
213 gfs2fl_InheritJdata = 31,
214};
215
216/* Dinode flags */
217#define GFS2_DIF_JDATA 0x00000001
218#define GFS2_DIF_EXHASH 0x00000002
219#define GFS2_DIF_UNUSED 0x00000004 /* only in gfs1 */
220#define GFS2_DIF_EA_INDIRECT 0x00000008
221#define GFS2_DIF_DIRECTIO 0x00000010
222#define GFS2_DIF_IMMUTABLE 0x00000020
223#define GFS2_DIF_APPENDONLY 0x00000040
224#define GFS2_DIF_NOATIME 0x00000080
225#define GFS2_DIF_SYNC 0x00000100
226#define GFS2_DIF_SYSTEM 0x00000200 /* New in gfs2 */
227#define GFS2_DIF_TRUNC_IN_PROG 0x20000000 /* New in gfs2 */
228#define GFS2_DIF_INHERIT_DIRECTIO 0x40000000
229#define GFS2_DIF_INHERIT_JDATA 0x80000000
230
231struct gfs2_dinode {
232 struct gfs2_meta_header di_header;
233
234 struct gfs2_inum di_num;
235
236 __be32 di_mode; /* mode of file */
237 __be32 di_uid; /* owner's user id */
238 __be32 di_gid; /* owner's group id */
239 __be32 di_nlink; /* number of links to this file */
240 __be64 di_size; /* number of bytes in file */
241 __be64 di_blocks; /* number of blocks in file */
242 __be64 di_atime; /* time last accessed */
243 __be64 di_mtime; /* time last modified */
244 __be64 di_ctime; /* time last changed */
245 __be32 di_major; /* device major number */
246 __be32 di_minor; /* device minor number */
247
248 /* This section varies from gfs1. Padding added to align with
249 * remainder of dinode
250 */
251 __be64 di_goal_meta; /* rgrp to alloc from next */
252 __be64 di_goal_data; /* data block goal */
253 __be64 di_generation; /* generation number for NFS */
254
255 __be32 di_flags; /* GFS2_DIF_... */
256 __be32 di_payload_format; /* GFS2_FORMAT_... */
257 __u16 __pad1; /* Was ditype in gfs1 */
258 __be16 di_height; /* height of metadata */
259 __u32 __pad2; /* Unused incarnation number from gfs1 */
260
261 /* These only apply to directories */
262 __u16 __pad3; /* Padding */
263 __be16 di_depth; /* Number of bits in the table */
264 __be32 di_entries; /* The number of entries in the directory */
265
266 struct gfs2_inum __pad4; /* Unused even in current gfs1 */
267
268 __be64 di_eattr; /* extended attribute block number */
269
270 __u8 di_reserved[56];
271};
272
273/*
274 * directory structure - many of these per directory file
275 */
276
277#define GFS2_FNAMESIZE 255
278#define GFS2_DIRENT_SIZE(name_len) ((sizeof(struct gfs2_dirent) + (name_len) + 7) & ~7)
279
280struct gfs2_dirent {
281 struct gfs2_inum de_inum;
282 __be32 de_hash;
283 __be16 de_rec_len;
284 __be16 de_name_len;
285 __be16 de_type;
286 __u8 __pad[14];
287};
288
289/*
290 * Header of leaf directory nodes
291 */
292
293struct gfs2_leaf {
294 struct gfs2_meta_header lf_header;
295
296 __be16 lf_depth; /* Depth of leaf */
297 __be16 lf_entries; /* Number of dirents in leaf */
298 __be32 lf_dirent_format; /* Format of the dirents */
299 __be64 lf_next; /* Next leaf, if overflow */
300
301 __u8 lf_reserved[64];
302};
303
304/*
305 * Extended attribute header format
306 */
307
308#define GFS2_EA_MAX_NAME_LEN 255
309#define GFS2_EA_MAX_DATA_LEN 65536
310
311#define GFS2_EATYPE_UNUSED 0
312#define GFS2_EATYPE_USR 1
313#define GFS2_EATYPE_SYS 2
314#define GFS2_EATYPE_SECURITY 3
315
316#define GFS2_EATYPE_LAST 3
317#define GFS2_EATYPE_VALID(x) ((x) <= GFS2_EATYPE_LAST)
318
319#define GFS2_EAFLAG_LAST 0x01 /* last ea in block */
320
321struct gfs2_ea_header {
322 __be32 ea_rec_len;
323 __be32 ea_data_len;
324 __u8 ea_name_len; /* no NULL pointer after the string */
325 __u8 ea_type; /* GFS2_EATYPE_... */
326 __u8 ea_flags; /* GFS2_EAFLAG_... */
327 __u8 ea_num_ptrs;
328 __u32 __pad;
329};
330
331/*
332 * Log header structure
333 */
334
335#define GFS2_LOG_HEAD_UNMOUNT 0x00000001 /* log is clean */
336
337struct gfs2_log_header {
338 struct gfs2_meta_header lh_header;
339
340 __be64 lh_sequence; /* Sequence number of this transaction */
341 __be32 lh_flags; /* GFS2_LOG_HEAD_... */
342 __be32 lh_tail; /* Block number of log tail */
343 __be32 lh_blkno;
344 __be32 lh_hash;
345};
346
347/*
348 * Log type descriptor
349 */
350
351#define GFS2_LOG_DESC_METADATA 300
352/* ld_data1 is the number of metadata blocks in the descriptor.
353 ld_data2 is unused. */
354
355#define GFS2_LOG_DESC_REVOKE 301
356/* ld_data1 is the number of revoke blocks in the descriptor.
357 ld_data2 is unused. */
358
359#define GFS2_LOG_DESC_JDATA 302
360/* ld_data1 is the number of data blocks in the descriptor.
361 ld_data2 is unused. */
362
363struct gfs2_log_descriptor {
364 struct gfs2_meta_header ld_header;
365
366 __be32 ld_type; /* GFS2_LOG_DESC_... */
367 __be32 ld_length; /* Number of buffers in this chunk */
368 __be32 ld_data1; /* descriptor-specific field */
369 __be32 ld_data2; /* descriptor-specific field */
370
371 __u8 ld_reserved[32];
372};
373
374/*
375 * Inum Range
376 * Describe a range of formal inode numbers allocated to
377 * one machine to assign to inodes.
378 */
379
380#define GFS2_INUM_QUANTUM 1048576
381
382struct gfs2_inum_range {
383 __be64 ir_start;
384 __be64 ir_length;
385};
386
387/*
388 * Statfs change
389 * Describes an change to the pool of free and allocated
390 * blocks.
391 */
392
393struct gfs2_statfs_change {
394 __be64 sc_total;
395 __be64 sc_free;
396 __be64 sc_dinodes;
397};
398
399/*
400 * Quota change
401 * Describes an allocation change for a particular
402 * user or group.
403 */
404
405#define GFS2_QCF_USER 0x00000001
406
407struct gfs2_quota_change {
408 __be64 qc_change;
409 __be32 qc_flags; /* GFS2_QCF_... */
410 __be32 qc_id;
411};
412
413#ifdef __KERNEL__
414/* Translation functions */
415
416extern void gfs2_inum_in(struct gfs2_inum *no, const void *buf);
417extern void gfs2_inum_out(const struct gfs2_inum *no, void *buf);
418extern void gfs2_sb_in(struct gfs2_sb *sb, const void *buf);
419extern void gfs2_rindex_in(struct gfs2_rindex *ri, const void *buf);
420extern void gfs2_rindex_out(const struct gfs2_rindex *ri, void *buf);
421extern void gfs2_rgrp_in(struct gfs2_rgrp *rg, const void *buf);
422extern void gfs2_rgrp_out(const struct gfs2_rgrp *rg, void *buf);
423extern void gfs2_quota_in(struct gfs2_quota *qu, const void *buf);
424extern void gfs2_quota_out(const struct gfs2_quota *qu, void *buf);
425extern void gfs2_dinode_in(struct gfs2_dinode *di, const void *buf);
426extern void gfs2_dinode_out(const struct gfs2_dinode *di, void *buf);
427extern void gfs2_ea_header_in(struct gfs2_ea_header *ea, const void *buf);
428extern void gfs2_ea_header_out(const struct gfs2_ea_header *ea, void *buf);
429extern void gfs2_log_header_in(struct gfs2_log_header *lh, const void *buf);
430extern void gfs2_inum_range_in(struct gfs2_inum_range *ir, const void *buf);
431extern void gfs2_inum_range_out(const struct gfs2_inum_range *ir, void *buf);
432extern void gfs2_statfs_change_in(struct gfs2_statfs_change *sc, const void *buf);
433extern void gfs2_statfs_change_out(const struct gfs2_statfs_change *sc, void *buf);
434extern void gfs2_quota_change_in(struct gfs2_quota_change *qc, const void *buf);
435
436/* Printing functions */
437
438extern void gfs2_rindex_print(const struct gfs2_rindex *ri);
439extern void gfs2_dinode_print(const struct gfs2_dinode *di);
440
441#endif /* __KERNEL__ */
442
443#endif /* __GFS2_ONDISK_DOT_H__ */
diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h
index 50d8b5744cf6..612472aaa79c 100644
--- a/include/linux/hardirq.h
+++ b/include/linux/hardirq.h
@@ -28,11 +28,16 @@
28 28
29#ifndef HARDIRQ_BITS 29#ifndef HARDIRQ_BITS
30#define HARDIRQ_BITS 12 30#define HARDIRQ_BITS 12
31
32#ifndef MAX_HARDIRQS_PER_CPU
33#define MAX_HARDIRQS_PER_CPU NR_IRQS
34#endif
35
31/* 36/*
32 * The hardirq mask has to be large enough to have space for potentially 37 * The hardirq mask has to be large enough to have space for potentially
33 * all IRQ sources in the system nesting on a single CPU. 38 * all IRQ sources in the system nesting on a single CPU.
34 */ 39 */
35#if (1 << HARDIRQ_BITS) < NR_IRQS 40#if (1 << HARDIRQ_BITS) < MAX_HARDIRQS_PER_CPU
36# error HARDIRQ_BITS is too low! 41# error HARDIRQ_BITS is too low!
37#endif 42#endif
38#endif 43#endif
diff --git a/include/linux/htirq.h b/include/linux/htirq.h
new file mode 100644
index 000000000000..1f15ce279a23
--- /dev/null
+++ b/include/linux/htirq.h
@@ -0,0 +1,15 @@
1#ifndef LINUX_HTIRQ_H
2#define LINUX_HTIRQ_H
3
4/* Helper functions.. */
5void write_ht_irq_low(unsigned int irq, u32 data);
6void write_ht_irq_high(unsigned int irq, u32 data);
7u32 read_ht_irq_low(unsigned int irq);
8u32 read_ht_irq_high(unsigned int irq);
9void mask_ht_irq(unsigned int irq);
10void unmask_ht_irq(unsigned int irq);
11
12/* The arch hook for getting things started */
13int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev);
14
15#endif /* LINUX_HTIRQ_H */
diff --git a/include/linux/in.h b/include/linux/in.h
index d79fc75fa7c2..2619859f6e1b 100644
--- a/include/linux/in.h
+++ b/include/linux/in.h
@@ -40,6 +40,7 @@ enum {
40 40
41 IPPROTO_ESP = 50, /* Encapsulation Security Payload protocol */ 41 IPPROTO_ESP = 50, /* Encapsulation Security Payload protocol */
42 IPPROTO_AH = 51, /* Authentication Header protocol */ 42 IPPROTO_AH = 51, /* Authentication Header protocol */
43 IPPROTO_BEETPH = 94, /* IP option pseudo header for BEET */
43 IPPROTO_PIM = 103, /* Protocol Independent Multicast */ 44 IPPROTO_PIM = 103, /* Protocol Independent Multicast */
44 45
45 IPPROTO_COMP = 108, /* Compression Header protocol */ 46 IPPROTO_COMP = 108, /* Compression Header protocol */
diff --git a/include/linux/ip.h b/include/linux/ip.h
index 6b25d36fc54c..ecee9bb27d0e 100644
--- a/include/linux/ip.h
+++ b/include/linux/ip.h
@@ -80,6 +80,8 @@
80#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */ 80#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */
81#define IPOPT_TS_PRESPEC 3 /* specified modules only */ 81#define IPOPT_TS_PRESPEC 3 /* specified modules only */
82 82
83#define IPV4_BEET_PHMAXLEN 8
84
83struct iphdr { 85struct iphdr {
84#if defined(__LITTLE_ENDIAN_BITFIELD) 86#if defined(__LITTLE_ENDIAN_BITFIELD)
85 __u8 ihl:4, 87 __u8 ihl:4,
@@ -123,4 +125,11 @@ struct ip_comp_hdr {
123 __be16 cpi; 125 __be16 cpi;
124}; 126};
125 127
128struct ip_beet_phdr {
129 __u8 nexthdr;
130 __u8 hdrlen;
131 __u8 padlen;
132 __u8 reserved;
133};
134
126#endif /* _LINUX_IP_H */ 135#endif /* _LINUX_IP_H */
diff --git a/include/linux/ipc.h b/include/linux/ipc.h
index d9e2b3f36c35..636094c29b16 100644
--- a/include/linux/ipc.h
+++ b/include/linux/ipc.h
@@ -2,7 +2,6 @@
2#define _LINUX_IPC_H 2#define _LINUX_IPC_H
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5#include <linux/kref.h>
6 5
7#define IPC_PRIVATE ((__kernel_key_t) 0) 6#define IPC_PRIVATE ((__kernel_key_t) 0)
8 7
@@ -52,6 +51,8 @@ struct ipc_perm
52 51
53#ifdef __KERNEL__ 52#ifdef __KERNEL__
54 53
54#include <linux/kref.h>
55
55#define IPCMNI 32768 /* <= MAX_INT limit for ipc arrays (including sysctl changes) */ 56#define IPCMNI 32768 /* <= MAX_INT limit for ipc arrays (including sysctl changes) */
56 57
57/* used by in-kernel data structures */ 58/* used by in-kernel data structures */
diff --git a/include/linux/ipsec.h b/include/linux/ipsec.h
index d3c527616b5e..d17a6302a0e9 100644
--- a/include/linux/ipsec.h
+++ b/include/linux/ipsec.h
@@ -12,7 +12,8 @@
12enum { 12enum {
13 IPSEC_MODE_ANY = 0, /* We do not support this for SA */ 13 IPSEC_MODE_ANY = 0, /* We do not support this for SA */
14 IPSEC_MODE_TRANSPORT = 1, 14 IPSEC_MODE_TRANSPORT = 1,
15 IPSEC_MODE_TUNNEL = 2 15 IPSEC_MODE_TUNNEL = 2,
16 IPSEC_MODE_BEET = 3
16}; 17};
17 18
18enum { 19enum {
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 48d3cb3b6a47..6f463606c318 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -59,6 +59,7 @@
59#define IRQ_NOAUTOEN 0x08000000 /* IRQ will not be enabled on request irq */ 59#define IRQ_NOAUTOEN 0x08000000 /* IRQ will not be enabled on request irq */
60#define IRQ_DELAYED_DISABLE 0x10000000 /* IRQ disable (masking) happens delayed. */ 60#define IRQ_DELAYED_DISABLE 0x10000000 /* IRQ disable (masking) happens delayed. */
61#define IRQ_WAKEUP 0x20000000 /* IRQ triggers system wakeup */ 61#define IRQ_WAKEUP 0x20000000 /* IRQ triggers system wakeup */
62#define IRQ_MOVE_PENDING 0x40000000 /* need to re-target IRQ destination */
62 63
63struct proc_dir_entry; 64struct proc_dir_entry;
64 65
@@ -132,7 +133,6 @@ struct irq_chip {
132 * @affinity: IRQ affinity on SMP 133 * @affinity: IRQ affinity on SMP
133 * @cpu: cpu index useful for balancing 134 * @cpu: cpu index useful for balancing
134 * @pending_mask: pending rebalanced interrupts 135 * @pending_mask: pending rebalanced interrupts
135 * @move_irq: need to re-target IRQ destination
136 * @dir: /proc/irq/ procfs entry 136 * @dir: /proc/irq/ procfs entry
137 * @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP 137 * @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP
138 * 138 *
@@ -159,7 +159,6 @@ struct irq_desc {
159#endif 159#endif
160#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE) 160#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
161 cpumask_t pending_mask; 161 cpumask_t pending_mask;
162 unsigned int move_irq; /* need to re-target IRQ dest */
163#endif 162#endif
164#ifdef CONFIG_PROC_FS 163#ifdef CONFIG_PROC_FS
165 struct proc_dir_entry *dir; 164 struct proc_dir_entry *dir;
@@ -206,36 +205,7 @@ static inline void set_native_irq_info(int irq, cpumask_t mask)
206 205
207void set_pending_irq(unsigned int irq, cpumask_t mask); 206void set_pending_irq(unsigned int irq, cpumask_t mask);
208void move_native_irq(int irq); 207void move_native_irq(int irq);
209 208void move_masked_irq(int irq);
210#ifdef CONFIG_PCI_MSI
211/*
212 * Wonder why these are dummies?
213 * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
214 * counter part after translating the vector to irq info. We need to perform
215 * this operation on the real irq, when we dont use vector, i.e when
216 * pci_use_vector() is false.
217 */
218static inline void move_irq(int irq)
219{
220}
221
222static inline void set_irq_info(int irq, cpumask_t mask)
223{
224}
225
226#else /* CONFIG_PCI_MSI */
227
228static inline void move_irq(int irq)
229{
230 move_native_irq(irq);
231}
232
233static inline void set_irq_info(int irq, cpumask_t mask)
234{
235 set_native_irq_info(irq, mask);
236}
237
238#endif /* CONFIG_PCI_MSI */
239 209
240#else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */ 210#else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */
241 211
@@ -247,21 +217,20 @@ static inline void move_native_irq(int irq)
247{ 217{
248} 218}
249 219
250static inline void set_pending_irq(unsigned int irq, cpumask_t mask) 220static inline void move_masked_irq(int irq)
251{ 221{
252} 222}
253 223
254static inline void set_irq_info(int irq, cpumask_t mask) 224static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
255{ 225{
256 set_native_irq_info(irq, mask);
257} 226}
258 227
259#endif /* CONFIG_GENERIC_PENDING_IRQ */ 228#endif /* CONFIG_GENERIC_PENDING_IRQ */
260 229
261#else /* CONFIG_SMP */ 230#else /* CONFIG_SMP */
262 231
263#define move_irq(x)
264#define move_native_irq(x) 232#define move_native_irq(x)
233#define move_masked_irq(x)
265 234
266#endif /* CONFIG_SMP */ 235#endif /* CONFIG_SMP */
267 236
@@ -399,8 +368,22 @@ set_irq_chained_handler(unsigned int irq,
399 __set_irq_handler(irq, handle, 1); 368 __set_irq_handler(irq, handle, 1);
400} 369}
401 370
402/* Set/get chip/data for an IRQ: */ 371/* Handle dynamic irq creation and destruction */
372extern int create_irq(void);
373extern void destroy_irq(unsigned int irq);
403 374
375/* Test to see if a driver has successfully requested an irq */
376static inline int irq_has_action(unsigned int irq)
377{
378 struct irq_desc *desc = irq_desc + irq;
379 return desc->action != NULL;
380}
381
382/* Dynamic irq helper functions */
383extern void dynamic_irq_init(unsigned int irq);
384extern void dynamic_irq_cleanup(unsigned int irq);
385
386/* Set/get chip/data for an IRQ: */
404extern int set_irq_chip(unsigned int irq, struct irq_chip *chip); 387extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
405extern int set_irq_data(unsigned int irq, void *data); 388extern int set_irq_data(unsigned int irq, void *data);
406extern int set_irq_chip_data(unsigned int irq, void *data); 389extern int set_irq_chip_data(unsigned int irq, void *data);
diff --git a/include/linux/libata.h b/include/linux/libata.h
index d6a3d4b345fc..d1af1dbeaeb4 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -109,6 +109,10 @@ static inline u32 ata_msg_init(int dval, int default_msg_enable_bits)
109#define ATA_TAG_POISON 0xfafbfcfdU 109#define ATA_TAG_POISON 0xfafbfcfdU
110 110
111/* move to PCI layer? */ 111/* move to PCI layer? */
112#define PCI_VDEVICE(vendor, device) \
113 PCI_VENDOR_ID_##vendor, (device), \
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0
115
112static inline struct device *pci_dev_to_dev(struct pci_dev *pdev) 116static inline struct device *pci_dev_to_dev(struct pci_dev *pdev)
113{ 117{
114 return &pdev->dev; 118 return &pdev->dev;
@@ -138,8 +142,9 @@ enum {
138 ATA_DFLAG_NCQ = (1 << 3), /* device supports NCQ */ 142 ATA_DFLAG_NCQ = (1 << 3), /* device supports NCQ */
139 ATA_DFLAG_CFG_MASK = (1 << 8) - 1, 143 ATA_DFLAG_CFG_MASK = (1 << 8) - 1,
140 144
141 ATA_DFLAG_PIO = (1 << 8), /* device currently in PIO mode */ 145 ATA_DFLAG_PIO = (1 << 8), /* device limited to PIO mode */
142 ATA_DFLAG_SUSPENDED = (1 << 9), /* device suspended */ 146 ATA_DFLAG_NCQ_OFF = (1 << 9), /* devied limited to non-NCQ mode */
147 ATA_DFLAG_SUSPENDED = (1 << 10), /* device suspended */
143 ATA_DFLAG_INIT_MASK = (1 << 16) - 1, 148 ATA_DFLAG_INIT_MASK = (1 << 16) - 1,
144 149
145 ATA_DFLAG_DETACH = (1 << 16), 150 ATA_DFLAG_DETACH = (1 << 16),
diff --git a/include/linux/lm_interface.h b/include/linux/lm_interface.h
new file mode 100644
index 000000000000..1418fdc9ac02
--- /dev/null
+++ b/include/linux/lm_interface.h
@@ -0,0 +1,273 @@
1/*
2 * Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved.
3 * Copyright (C) 2004-2006 Red Hat, Inc. All rights reserved.
4 *
5 * This copyrighted material is made available to anyone wishing to use,
6 * modify, copy, or redistribute it subject to the terms and conditions
7 * of the GNU General Public License version 2.
8 */
9
10#ifndef __LM_INTERFACE_DOT_H__
11#define __LM_INTERFACE_DOT_H__
12
13
14typedef void (*lm_callback_t) (void *ptr, unsigned int type, void *data);
15
16/*
17 * lm_mount() flags
18 *
19 * LM_MFLAG_SPECTATOR
20 * GFS is asking to join the filesystem's lockspace, but it doesn't want to
21 * modify the filesystem. The lock module shouldn't assign a journal to the FS
22 * mount. It shouldn't send recovery callbacks to the FS mount. If the node
23 * dies or withdraws, all locks can be wiped immediately.
24 */
25
26#define LM_MFLAG_SPECTATOR 0x00000001
27
28/*
29 * lm_lockstruct flags
30 *
31 * LM_LSFLAG_LOCAL
32 * The lock_nolock module returns LM_LSFLAG_LOCAL to GFS, indicating that GFS
33 * can make single-node optimizations.
34 */
35
36#define LM_LSFLAG_LOCAL 0x00000001
37
38/*
39 * lm_lockname types
40 */
41
42#define LM_TYPE_RESERVED 0x00
43#define LM_TYPE_NONDISK 0x01
44#define LM_TYPE_INODE 0x02
45#define LM_TYPE_RGRP 0x03
46#define LM_TYPE_META 0x04
47#define LM_TYPE_IOPEN 0x05
48#define LM_TYPE_FLOCK 0x06
49#define LM_TYPE_PLOCK 0x07
50#define LM_TYPE_QUOTA 0x08
51#define LM_TYPE_JOURNAL 0x09
52
53/*
54 * lm_lock() states
55 *
56 * SHARED is compatible with SHARED, not with DEFERRED or EX.
57 * DEFERRED is compatible with DEFERRED, not with SHARED or EX.
58 */
59
60#define LM_ST_UNLOCKED 0
61#define LM_ST_EXCLUSIVE 1
62#define LM_ST_DEFERRED 2
63#define LM_ST_SHARED 3
64
65/*
66 * lm_lock() flags
67 *
68 * LM_FLAG_TRY
69 * Don't wait to acquire the lock if it can't be granted immediately.
70 *
71 * LM_FLAG_TRY_1CB
72 * Send one blocking callback if TRY is set and the lock is not granted.
73 *
74 * LM_FLAG_NOEXP
75 * GFS sets this flag on lock requests it makes while doing journal recovery.
76 * These special requests should not be blocked due to the recovery like
77 * ordinary locks would be.
78 *
79 * LM_FLAG_ANY
80 * A SHARED request may also be granted in DEFERRED, or a DEFERRED request may
81 * also be granted in SHARED. The preferred state is whichever is compatible
82 * with other granted locks, or the specified state if no other locks exist.
83 *
84 * LM_FLAG_PRIORITY
85 * Override fairness considerations. Suppose a lock is held in a shared state
86 * and there is a pending request for the deferred state. A shared lock
87 * request with the priority flag would be allowed to bypass the deferred
88 * request and directly join the other shared lock. A shared lock request
89 * without the priority flag might be forced to wait until the deferred
90 * requested had acquired and released the lock.
91 */
92
93#define LM_FLAG_TRY 0x00000001
94#define LM_FLAG_TRY_1CB 0x00000002
95#define LM_FLAG_NOEXP 0x00000004
96#define LM_FLAG_ANY 0x00000008
97#define LM_FLAG_PRIORITY 0x00000010
98
99/*
100 * lm_lock() and lm_async_cb return flags
101 *
102 * LM_OUT_ST_MASK
103 * Masks the lower two bits of lock state in the returned value.
104 *
105 * LM_OUT_CACHEABLE
106 * The lock hasn't been released so GFS can continue to cache data for it.
107 *
108 * LM_OUT_CANCELED
109 * The lock request was canceled.
110 *
111 * LM_OUT_ASYNC
112 * The result of the request will be returned in an LM_CB_ASYNC callback.
113 */
114
115#define LM_OUT_ST_MASK 0x00000003
116#define LM_OUT_CACHEABLE 0x00000004
117#define LM_OUT_CANCELED 0x00000008
118#define LM_OUT_ASYNC 0x00000080
119#define LM_OUT_ERROR 0x00000100
120
121/*
122 * lm_callback_t types
123 *
124 * LM_CB_NEED_E LM_CB_NEED_D LM_CB_NEED_S
125 * Blocking callback, a remote node is requesting the given lock in
126 * EXCLUSIVE, DEFERRED, or SHARED.
127 *
128 * LM_CB_NEED_RECOVERY
129 * The given journal needs to be recovered.
130 *
131 * LM_CB_DROPLOCKS
132 * Reduce the number of cached locks.
133 *
134 * LM_CB_ASYNC
135 * The given lock has been granted.
136 */
137
138#define LM_CB_NEED_E 257
139#define LM_CB_NEED_D 258
140#define LM_CB_NEED_S 259
141#define LM_CB_NEED_RECOVERY 260
142#define LM_CB_DROPLOCKS 261
143#define LM_CB_ASYNC 262
144
145/*
146 * lm_recovery_done() messages
147 */
148
149#define LM_RD_GAVEUP 308
150#define LM_RD_SUCCESS 309
151
152
153struct lm_lockname {
154 u64 ln_number;
155 unsigned int ln_type;
156};
157
158#define lm_name_equal(name1, name2) \
159 (((name1)->ln_number == (name2)->ln_number) && \
160 ((name1)->ln_type == (name2)->ln_type)) \
161
162struct lm_async_cb {
163 struct lm_lockname lc_name;
164 int lc_ret;
165};
166
167struct lm_lockstruct;
168
169struct lm_lockops {
170 const char *lm_proto_name;
171
172 /*
173 * Mount/Unmount
174 */
175
176 int (*lm_mount) (char *table_name, char *host_data,
177 lm_callback_t cb, void *cb_data,
178 unsigned int min_lvb_size, int flags,
179 struct lm_lockstruct *lockstruct,
180 struct kobject *fskobj);
181
182 void (*lm_others_may_mount) (void *lockspace);
183
184 void (*lm_unmount) (void *lockspace);
185
186 void (*lm_withdraw) (void *lockspace);
187
188 /*
189 * Lock oriented operations
190 */
191
192 int (*lm_get_lock) (void *lockspace, struct lm_lockname *name, void **lockp);
193
194 void (*lm_put_lock) (void *lock);
195
196 unsigned int (*lm_lock) (void *lock, unsigned int cur_state,
197 unsigned int req_state, unsigned int flags);
198
199 unsigned int (*lm_unlock) (void *lock, unsigned int cur_state);
200
201 void (*lm_cancel) (void *lock);
202
203 int (*lm_hold_lvb) (void *lock, char **lvbp);
204 void (*lm_unhold_lvb) (void *lock, char *lvb);
205
206 /*
207 * Posix Lock oriented operations
208 */
209
210 int (*lm_plock_get) (void *lockspace, struct lm_lockname *name,
211 struct file *file, struct file_lock *fl);
212
213 int (*lm_plock) (void *lockspace, struct lm_lockname *name,
214 struct file *file, int cmd, struct file_lock *fl);
215
216 int (*lm_punlock) (void *lockspace, struct lm_lockname *name,
217 struct file *file, struct file_lock *fl);
218
219 /*
220 * Client oriented operations
221 */
222
223 void (*lm_recovery_done) (void *lockspace, unsigned int jid,
224 unsigned int message);
225
226 struct module *lm_owner;
227};
228
229/*
230 * lm_mount() return values
231 *
232 * ls_jid - the journal ID this node should use
233 * ls_first - this node is the first to mount the file system
234 * ls_lvb_size - size in bytes of lock value blocks
235 * ls_lockspace - lock module's context for this file system
236 * ls_ops - lock module's functions
237 * ls_flags - lock module features
238 */
239
240struct lm_lockstruct {
241 unsigned int ls_jid;
242 unsigned int ls_first;
243 unsigned int ls_lvb_size;
244 void *ls_lockspace;
245 const struct lm_lockops *ls_ops;
246 int ls_flags;
247};
248
249/*
250 * Lock module bottom interface. A lock module makes itself available to GFS
251 * with these functions.
252 */
253
254int gfs2_register_lockproto(const struct lm_lockops *proto);
255void gfs2_unregister_lockproto(const struct lm_lockops *proto);
256
257/*
258 * Lock module top interface. GFS calls these functions when mounting or
259 * unmounting a file system.
260 */
261
262int gfs2_mount_lockproto(char *proto_name, char *table_name, char *host_data,
263 lm_callback_t cb, void *cb_data,
264 unsigned int min_lvb_size, int flags,
265 struct lm_lockstruct *lockstruct,
266 struct kobject *fskobj);
267
268void gfs2_unmount_lockproto(struct lm_lockstruct *lockstruct);
269
270void gfs2_withdraw_lockproto(struct lm_lockstruct *lockstruct);
271
272#endif /* __LM_INTERFACE_DOT_H__ */
273
diff --git a/include/linux/lock_dlm_plock.h b/include/linux/lock_dlm_plock.h
new file mode 100644
index 000000000000..fc3415113973
--- /dev/null
+++ b/include/linux/lock_dlm_plock.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2005 Red Hat, Inc. All rights reserved.
3 *
4 * This copyrighted material is made available to anyone wishing to use,
5 * modify, copy, or redistribute it subject to the terms and conditions
6 * of the GNU General Public License v.2.
7 */
8
9#ifndef __LOCK_DLM_PLOCK_DOT_H__
10#define __LOCK_DLM_PLOCK_DOT_H__
11
12#define GDLM_PLOCK_MISC_NAME "lock_dlm_plock"
13
14#define GDLM_PLOCK_VERSION_MAJOR 1
15#define GDLM_PLOCK_VERSION_MINOR 1
16#define GDLM_PLOCK_VERSION_PATCH 0
17
18enum {
19 GDLM_PLOCK_OP_LOCK = 1,
20 GDLM_PLOCK_OP_UNLOCK,
21 GDLM_PLOCK_OP_GET,
22};
23
24struct gdlm_plock_info {
25 __u32 version[3];
26 __u8 optype;
27 __u8 ex;
28 __u8 wait;
29 __u8 pad;
30 __u32 pid;
31 __s32 nodeid;
32 __s32 rv;
33 __u32 fsid;
34 __u64 number;
35 __u64 start;
36 __u64 end;
37 __u64 owner;
38};
39
40#endif
41
diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h
index 47b7dbd647a6..2909619c0295 100644
--- a/include/linux/lockd/lockd.h
+++ b/include/linux/lockd/lockd.h
@@ -37,17 +37,15 @@
37 * Lockd host handle (used both by the client and server personality). 37 * Lockd host handle (used both by the client and server personality).
38 */ 38 */
39struct nlm_host { 39struct nlm_host {
40 struct nlm_host * h_next; /* linked list (hash table) */ 40 struct hlist_node h_hash; /* doubly linked list */
41 struct sockaddr_in h_addr; /* peer address */ 41 struct sockaddr_in h_addr; /* peer address */
42 struct rpc_clnt * h_rpcclnt; /* RPC client to talk to peer */ 42 struct rpc_clnt * h_rpcclnt; /* RPC client to talk to peer */
43 char h_name[20]; /* remote hostname */ 43 char * h_name; /* remote hostname */
44 u32 h_version; /* interface version */ 44 u32 h_version; /* interface version */
45 unsigned short h_proto; /* transport proto */ 45 unsigned short h_proto; /* transport proto */
46 unsigned short h_reclaiming : 1, 46 unsigned short h_reclaiming : 1,
47 h_server : 1, /* server side, not client side */ 47 h_server : 1, /* server side, not client side */
48 h_inuse : 1, 48 h_inuse : 1;
49 h_killed : 1,
50 h_monitored : 1;
51 wait_queue_head_t h_gracewait; /* wait while reclaiming */ 49 wait_queue_head_t h_gracewait; /* wait while reclaiming */
52 struct rw_semaphore h_rwsem; /* Reboot recovery lock */ 50 struct rw_semaphore h_rwsem; /* Reboot recovery lock */
53 u32 h_state; /* pseudo-state counter */ 51 u32 h_state; /* pseudo-state counter */
@@ -61,6 +59,16 @@ struct nlm_host {
61 spinlock_t h_lock; 59 spinlock_t h_lock;
62 struct list_head h_granted; /* Locks in GRANTED state */ 60 struct list_head h_granted; /* Locks in GRANTED state */
63 struct list_head h_reclaim; /* Locks in RECLAIM state */ 61 struct list_head h_reclaim; /* Locks in RECLAIM state */
62 struct nsm_handle * h_nsmhandle; /* NSM status handle */
63};
64
65struct nsm_handle {
66 struct list_head sm_link;
67 atomic_t sm_count;
68 char * sm_name;
69 struct sockaddr_in sm_addr;
70 unsigned int sm_monitored : 1,
71 sm_sticky : 1; /* don't unmonitor */
64}; 72};
65 73
66/* 74/*
@@ -96,15 +104,14 @@ struct nlm_rqst {
96 * an NFS client. 104 * an NFS client.
97 */ 105 */
98struct nlm_file { 106struct nlm_file {
99 struct nlm_file * f_next; /* linked list */ 107 struct hlist_node f_list; /* linked list */
100 struct nfs_fh f_handle; /* NFS file handle */ 108 struct nfs_fh f_handle; /* NFS file handle */
101 struct file * f_file; /* VFS file pointer */ 109 struct file * f_file; /* VFS file pointer */
102 struct nlm_share * f_shares; /* DOS shares */ 110 struct nlm_share * f_shares; /* DOS shares */
103 struct nlm_block * f_blocks; /* blocked locks */ 111 struct list_head f_blocks; /* blocked locks */
104 unsigned int f_locks; /* guesstimate # of locks */ 112 unsigned int f_locks; /* guesstimate # of locks */
105 unsigned int f_count; /* reference count */ 113 unsigned int f_count; /* reference count */
106 struct semaphore f_sema; /* avoid concurrent access */ 114 struct mutex f_mutex; /* avoid concurrent access */
107 int f_hash; /* hash of f_handle */
108}; 115};
109 116
110/* 117/*
@@ -114,26 +121,18 @@ struct nlm_file {
114#define NLM_NEVER (~(unsigned long) 0) 121#define NLM_NEVER (~(unsigned long) 0)
115struct nlm_block { 122struct nlm_block {
116 struct kref b_count; /* Reference count */ 123 struct kref b_count; /* Reference count */
117 struct nlm_block * b_next; /* linked list (all blocks) */ 124 struct list_head b_list; /* linked list of all blocks */
118 struct nlm_block * b_fnext; /* linked list (per file) */ 125 struct list_head b_flist; /* linked list (per file) */
119 struct nlm_rqst * b_call; /* RPC args & callback info */ 126 struct nlm_rqst * b_call; /* RPC args & callback info */
120 struct svc_serv * b_daemon; /* NLM service */ 127 struct svc_serv * b_daemon; /* NLM service */
121 struct nlm_host * b_host; /* host handle for RPC clnt */ 128 struct nlm_host * b_host; /* host handle for RPC clnt */
122 unsigned long b_when; /* next re-xmit */ 129 unsigned long b_when; /* next re-xmit */
123 unsigned int b_id; /* block id */ 130 unsigned int b_id; /* block id */
124 unsigned char b_queued; /* re-queued */
125 unsigned char b_granted; /* VFS granted lock */ 131 unsigned char b_granted; /* VFS granted lock */
126 struct nlm_file * b_file; /* file in question */ 132 struct nlm_file * b_file; /* file in question */
127}; 133};
128 134
129/* 135/*
130 * Valid actions for nlmsvc_traverse_files
131 */
132#define NLM_ACT_CHECK 0 /* check for locks */
133#define NLM_ACT_MARK 1 /* mark & sweep */
134#define NLM_ACT_UNLOCK 2 /* release all locks */
135
136/*
137 * Global variables 136 * Global variables
138 */ 137 */
139extern struct rpc_program nlm_program; 138extern struct rpc_program nlm_program;
@@ -143,6 +142,7 @@ extern struct svc_procedure nlmsvc_procedures4[];
143#endif 142#endif
144extern int nlmsvc_grace_period; 143extern int nlmsvc_grace_period;
145extern unsigned long nlmsvc_timeout; 144extern unsigned long nlmsvc_timeout;
145extern int nsm_use_hostnames;
146 146
147/* 147/*
148 * Lockd client functions 148 * Lockd client functions
@@ -155,22 +155,31 @@ struct nlm_wait * nlmclnt_prepare_block(struct nlm_host *host, struct file_lock
155void nlmclnt_finish_block(struct nlm_wait *block); 155void nlmclnt_finish_block(struct nlm_wait *block);
156int nlmclnt_block(struct nlm_wait *block, struct nlm_rqst *req, long timeout); 156int nlmclnt_block(struct nlm_wait *block, struct nlm_rqst *req, long timeout);
157u32 nlmclnt_grant(const struct sockaddr_in *addr, const struct nlm_lock *); 157u32 nlmclnt_grant(const struct sockaddr_in *addr, const struct nlm_lock *);
158void nlmclnt_recovery(struct nlm_host *, u32); 158void nlmclnt_recovery(struct nlm_host *);
159int nlmclnt_reclaim(struct nlm_host *, struct file_lock *); 159int nlmclnt_reclaim(struct nlm_host *, struct file_lock *);
160void nlmclnt_next_cookie(struct nlm_cookie *);
160 161
161/* 162/*
162 * Host cache 163 * Host cache
163 */ 164 */
164struct nlm_host * nlmclnt_lookup_host(struct sockaddr_in *, int, int); 165struct nlm_host * nlmclnt_lookup_host(const struct sockaddr_in *, int, int, const char *, int);
165struct nlm_host * nlmsvc_lookup_host(struct svc_rqst *); 166struct nlm_host * nlmsvc_lookup_host(struct svc_rqst *, const char *, int);
166struct nlm_host * nlm_lookup_host(int server, struct sockaddr_in *, int, int); 167struct nlm_host * nlm_lookup_host(int server, const struct sockaddr_in *, int, int, const char *, int);
167struct rpc_clnt * nlm_bind_host(struct nlm_host *); 168struct rpc_clnt * nlm_bind_host(struct nlm_host *);
168void nlm_rebind_host(struct nlm_host *); 169void nlm_rebind_host(struct nlm_host *);
169struct nlm_host * nlm_get_host(struct nlm_host *); 170struct nlm_host * nlm_get_host(struct nlm_host *);
170void nlm_release_host(struct nlm_host *); 171void nlm_release_host(struct nlm_host *);
171void nlm_shutdown_hosts(void); 172void nlm_shutdown_hosts(void);
172extern struct nlm_host *nlm_find_client(void); 173extern void nlm_host_rebooted(const struct sockaddr_in *, const char *, int, u32);
174struct nsm_handle *nsm_find(const struct sockaddr_in *, const char *, int);
175void nsm_release(struct nsm_handle *);
176
173 177
178/*
179 * This is used in garbage collection and resource reclaim
180 * A return value != 0 means destroy the lock/block/share
181 */
182typedef int (*nlm_host_match_fn_t)(struct nlm_host *cur, struct nlm_host *ref);
174 183
175/* 184/*
176 * Server-side lock handling 185 * Server-side lock handling
@@ -183,8 +192,8 @@ u32 nlmsvc_testlock(struct nlm_file *, struct nlm_lock *,
183u32 nlmsvc_cancel_blocked(struct nlm_file *, struct nlm_lock *); 192u32 nlmsvc_cancel_blocked(struct nlm_file *, struct nlm_lock *);
184unsigned long nlmsvc_retry_blocked(void); 193unsigned long nlmsvc_retry_blocked(void);
185void nlmsvc_traverse_blocks(struct nlm_host *, struct nlm_file *, 194void nlmsvc_traverse_blocks(struct nlm_host *, struct nlm_file *,
186 int action); 195 nlm_host_match_fn_t match);
187void nlmsvc_grant_reply(struct svc_rqst *, struct nlm_cookie *, u32); 196void nlmsvc_grant_reply(struct nlm_cookie *, u32);
188 197
189/* 198/*
190 * File handling for the server personality 199 * File handling for the server personality
diff --git a/include/linux/lockd/share.h b/include/linux/lockd/share.h
index c75a424ebe4c..cd7816e74c05 100644
--- a/include/linux/lockd/share.h
+++ b/include/linux/lockd/share.h
@@ -25,6 +25,7 @@ u32 nlmsvc_share_file(struct nlm_host *, struct nlm_file *,
25 struct nlm_args *); 25 struct nlm_args *);
26u32 nlmsvc_unshare_file(struct nlm_host *, struct nlm_file *, 26u32 nlmsvc_unshare_file(struct nlm_host *, struct nlm_file *,
27 struct nlm_args *); 27 struct nlm_args *);
28void nlmsvc_traverse_shares(struct nlm_host *, struct nlm_file *, int); 28void nlmsvc_traverse_shares(struct nlm_host *, struct nlm_file *,
29 nlm_host_match_fn_t);
29 30
30#endif /* LINUX_LOCKD_SHARE_H */ 31#endif /* LINUX_LOCKD_SHARE_H */
diff --git a/include/linux/lockd/sm_inter.h b/include/linux/lockd/sm_inter.h
index 1080bb6ae315..fc61d40964da 100644
--- a/include/linux/lockd/sm_inter.h
+++ b/include/linux/lockd/sm_inter.h
@@ -28,7 +28,8 @@ struct nsm_args {
28 u32 prog; /* RPC callback info */ 28 u32 prog; /* RPC callback info */
29 u32 vers; 29 u32 vers;
30 u32 proc; 30 u32 proc;
31 u32 proto; /* protocol (udp/tcp) plus server/client flag */ 31
32 char * mon_name;
32}; 33};
33 34
34/* 35/*
@@ -41,6 +42,6 @@ struct nsm_res {
41 42
42int nsm_monitor(struct nlm_host *); 43int nsm_monitor(struct nlm_host *);
43int nsm_unmonitor(struct nlm_host *); 44int nsm_unmonitor(struct nlm_host *);
44extern u32 nsm_local_state; 45extern int nsm_local_state;
45 46
46#endif /* LINUX_LOCKD_SM_INTER_H */ 47#endif /* LINUX_LOCKD_SM_INTER_H */
diff --git a/include/linux/msi.h b/include/linux/msi.h
new file mode 100644
index 000000000000..c7ef94343673
--- /dev/null
+++ b/include/linux/msi.h
@@ -0,0 +1,49 @@
1#ifndef LINUX_MSI_H
2#define LINUX_MSI_H
3
4struct msi_msg {
5 u32 address_lo; /* low 32 bits of msi message address */
6 u32 address_hi; /* high 32 bits of msi message address */
7 u32 data; /* 16 bits of msi message data */
8};
9
10/* Heper functions */
11extern void mask_msi_irq(unsigned int irq);
12extern void unmask_msi_irq(unsigned int irq);
13extern void read_msi_msg(unsigned int irq, struct msi_msg *msg);
14
15extern void write_msi_msg(unsigned int irq, struct msi_msg *msg);
16
17struct msi_desc {
18 struct {
19 __u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
20 __u8 maskbit : 1; /* mask-pending bit supported ? */
21 __u8 unused : 1;
22 __u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
23 __u8 pos; /* Location of the msi capability */
24 __u16 entry_nr; /* specific enabled entry */
25 unsigned default_irq; /* default pre-assigned irq */
26 }msi_attrib;
27
28 struct {
29 __u16 head;
30 __u16 tail;
31 }link;
32
33 void __iomem *mask_base;
34 struct pci_dev *dev;
35
36#ifdef CONFIG_PM
37 /* PM save area for MSIX address/data */
38 struct msi_msg msg_save;
39#endif
40};
41
42/*
43 * The arch hook for setup up msi irqs
44 */
45int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev);
46void arch_teardown_msi_irq(unsigned int irq);
47
48
49#endif /* LINUX_MSI_H */
diff --git a/include/linux/netfilter_bridge/ebt_mark_t.h b/include/linux/netfilter_bridge/ebt_mark_t.h
index 110fec6a40a2..6270f6f33693 100644
--- a/include/linux/netfilter_bridge/ebt_mark_t.h
+++ b/include/linux/netfilter_bridge/ebt_mark_t.h
@@ -1,6 +1,18 @@
1#ifndef __LINUX_BRIDGE_EBT_MARK_T_H 1#ifndef __LINUX_BRIDGE_EBT_MARK_T_H
2#define __LINUX_BRIDGE_EBT_MARK_T_H 2#define __LINUX_BRIDGE_EBT_MARK_T_H
3 3
4/* The target member is reused for adding new actions, the
5 * value of the real target is -1 to -NUM_STANDARD_TARGETS.
6 * For backward compatibility, the 4 lsb (2 would be enough,
7 * but let's play it safe) are kept to designate this target.
8 * The remaining bits designate the action. By making the set
9 * action 0xfffffff0, the result will look ok for older
10 * versions. [September 2006] */
11#define MARK_SET_VALUE (0xfffffff0)
12#define MARK_OR_VALUE (0xffffffe0)
13#define MARK_AND_VALUE (0xffffffd0)
14#define MARK_XOR_VALUE (0xffffffc0)
15
4struct ebt_mark_t_info 16struct ebt_mark_t_info
5{ 17{
6 unsigned long mark; 18 unsigned long mark;
diff --git a/include/linux/netfilter_ipv4.h b/include/linux/netfilter_ipv4.h
index ce02c984f3ba..5b63a231a76b 100644
--- a/include/linux/netfilter_ipv4.h
+++ b/include/linux/netfilter_ipv4.h
@@ -77,7 +77,7 @@ enum nf_ip_hook_priorities {
77#define SO_ORIGINAL_DST 80 77#define SO_ORIGINAL_DST 80
78 78
79#ifdef __KERNEL__ 79#ifdef __KERNEL__
80extern int ip_route_me_harder(struct sk_buff **pskb); 80extern int ip_route_me_harder(struct sk_buff **pskb, unsigned addr_type);
81extern int ip_xfrm_me_harder(struct sk_buff **pskb); 81extern int ip_xfrm_me_harder(struct sk_buff **pskb);
82extern unsigned int nf_ip_checksum(struct sk_buff *skb, unsigned int hook, 82extern unsigned int nf_ip_checksum(struct sk_buff *skb, unsigned int hook,
83 unsigned int dataoff, u_int8_t protocol); 83 unsigned int dataoff, u_int8_t protocol);
diff --git a/include/linux/nfsd/const.h b/include/linux/nfsd/const.h
index b75bb1b38d09..f0cc77790527 100644
--- a/include/linux/nfsd/const.h
+++ b/include/linux/nfsd/const.h
@@ -20,17 +20,31 @@
20#define NFSSVC_MAXVERS 3 20#define NFSSVC_MAXVERS 3
21 21
22/* 22/*
23 * Maximum blocksize supported by daemon currently at 32K 23 * Maximum blocksizes supported by daemon under various circumstances.
24 */ 24 */
25#define NFSSVC_MAXBLKSIZE (32*1024) 25#define NFSSVC_MAXBLKSIZE RPCSVC_MAXPAYLOAD
26/* NFSv2 is limited by the protocol specification, see RFC 1094 */
27#define NFSSVC_MAXBLKSIZE_V2 (8*1024)
26 28
27#ifdef __KERNEL__ 29#ifdef __KERNEL__
28 30
31#include <linux/sunrpc/msg_prot.h>
32
29#ifndef NFS_SUPER_MAGIC 33#ifndef NFS_SUPER_MAGIC
30# define NFS_SUPER_MAGIC 0x6969 34# define NFS_SUPER_MAGIC 0x6969
31#endif 35#endif
32 36
33#define NFSD_BUFSIZE (1024 + NFSSVC_MAXBLKSIZE) 37/*
38 * Largest number of bytes we need to allocate for an NFS
39 * call or reply. Used to control buffer sizes. We use
40 * the length of v3 WRITE, READDIR and READDIR replies
41 * which are an RPC header, up to 26 XDR units of reply
42 * data, and some page data.
43 *
44 * Note that accuracy here doesn't matter too much as the
45 * size is rounded up to a page size when allocating space.
46 */
47#define NFSD_BUFSIZE ((RPC_MAX_HEADER_WITH_AUTH+26)*XDR_UNIT + NFSSVC_MAXBLKSIZE)
34 48
35#ifdef CONFIG_NFSD_V4 49#ifdef CONFIG_NFSD_V4
36# define NFSSVC_XDRSIZE NFS4_SVC_XDRSIZE 50# define NFSSVC_XDRSIZE NFS4_SVC_XDRSIZE
diff --git a/include/linux/nfsd/export.h b/include/linux/nfsd/export.h
index d2a8abb5011a..6e78ea969f49 100644
--- a/include/linux/nfsd/export.h
+++ b/include/linux/nfsd/export.h
@@ -45,15 +45,36 @@
45 45
46#ifdef __KERNEL__ 46#ifdef __KERNEL__
47 47
48/*
49 * FS Locations
50 */
51
52#define MAX_FS_LOCATIONS 128
53
54struct nfsd4_fs_location {
55 char *hosts; /* colon separated list of hosts */
56 char *path; /* slash separated list of path components */
57};
58
59struct nfsd4_fs_locations {
60 uint32_t locations_count;
61 struct nfsd4_fs_location *locations;
62/* If we're not actually serving this data ourselves (only providing a
63 * list of replicas that do serve it) then we set "migrated": */
64 int migrated;
65};
66
48struct svc_export { 67struct svc_export {
49 struct cache_head h; 68 struct cache_head h;
50 struct auth_domain * ex_client; 69 struct auth_domain * ex_client;
51 int ex_flags; 70 int ex_flags;
52 struct vfsmount * ex_mnt; 71 struct vfsmount * ex_mnt;
53 struct dentry * ex_dentry; 72 struct dentry * ex_dentry;
73 char * ex_path;
54 uid_t ex_anon_uid; 74 uid_t ex_anon_uid;
55 gid_t ex_anon_gid; 75 gid_t ex_anon_gid;
56 int ex_fsid; 76 int ex_fsid;
77 struct nfsd4_fs_locations ex_fslocs;
57}; 78};
58 79
59/* an "export key" (expkey) maps a filehandlefragement to an 80/* an "export key" (expkey) maps a filehandlefragement to an
diff --git a/include/linux/nfsd/nfsd.h b/include/linux/nfsd/nfsd.h
index e1dbc86c270b..d0d4aae7085f 100644
--- a/include/linux/nfsd/nfsd.h
+++ b/include/linux/nfsd/nfsd.h
@@ -145,6 +145,7 @@ int nfsd_vers(int vers, enum vers_op change);
145void nfsd_reset_versions(void); 145void nfsd_reset_versions(void);
146int nfsd_create_serv(void); 146int nfsd_create_serv(void);
147 147
148extern int nfsd_max_blksize;
148 149
149/* 150/*
150 * NFSv4 State 151 * NFSv4 State
@@ -215,6 +216,7 @@ void nfsd_lockd_shutdown(void);
215#define nfserr_clid_inuse __constant_htonl(NFSERR_CLID_INUSE) 216#define nfserr_clid_inuse __constant_htonl(NFSERR_CLID_INUSE)
216#define nfserr_stale_clientid __constant_htonl(NFSERR_STALE_CLIENTID) 217#define nfserr_stale_clientid __constant_htonl(NFSERR_STALE_CLIENTID)
217#define nfserr_resource __constant_htonl(NFSERR_RESOURCE) 218#define nfserr_resource __constant_htonl(NFSERR_RESOURCE)
219#define nfserr_moved __constant_htonl(NFSERR_MOVED)
218#define nfserr_nofilehandle __constant_htonl(NFSERR_NOFILEHANDLE) 220#define nfserr_nofilehandle __constant_htonl(NFSERR_NOFILEHANDLE)
219#define nfserr_minor_vers_mismatch __constant_htonl(NFSERR_MINOR_VERS_MISMATCH) 221#define nfserr_minor_vers_mismatch __constant_htonl(NFSERR_MINOR_VERS_MISMATCH)
220#define nfserr_share_denied __constant_htonl(NFSERR_SHARE_DENIED) 222#define nfserr_share_denied __constant_htonl(NFSERR_SHARE_DENIED)
@@ -291,7 +293,6 @@ static inline int is_fsid(struct svc_fh *fh, struct knfsd_fh *reffh)
291/* 293/*
292 * The following attributes are currently not supported by the NFSv4 server: 294 * The following attributes are currently not supported by the NFSv4 server:
293 * ARCHIVE (deprecated anyway) 295 * ARCHIVE (deprecated anyway)
294 * FS_LOCATIONS (will be supported eventually)
295 * HIDDEN (unlikely to be supported any time soon) 296 * HIDDEN (unlikely to be supported any time soon)
296 * MIMETYPE (unlikely to be supported any time soon) 297 * MIMETYPE (unlikely to be supported any time soon)
297 * QUOTA_* (will be supported in a forthcoming patch) 298 * QUOTA_* (will be supported in a forthcoming patch)
@@ -307,7 +308,7 @@ static inline int is_fsid(struct svc_fh *fh, struct knfsd_fh *reffh)
307 | FATTR4_WORD0_ACLSUPPORT | FATTR4_WORD0_CANSETTIME | FATTR4_WORD0_CASE_INSENSITIVE \ 308 | FATTR4_WORD0_ACLSUPPORT | FATTR4_WORD0_CANSETTIME | FATTR4_WORD0_CASE_INSENSITIVE \
308 | FATTR4_WORD0_CASE_PRESERVING | FATTR4_WORD0_CHOWN_RESTRICTED \ 309 | FATTR4_WORD0_CASE_PRESERVING | FATTR4_WORD0_CHOWN_RESTRICTED \
309 | FATTR4_WORD0_FILEHANDLE | FATTR4_WORD0_FILEID | FATTR4_WORD0_FILES_AVAIL \ 310 | FATTR4_WORD0_FILEHANDLE | FATTR4_WORD0_FILEID | FATTR4_WORD0_FILES_AVAIL \
310 | FATTR4_WORD0_FILES_FREE | FATTR4_WORD0_FILES_TOTAL | FATTR4_WORD0_HOMOGENEOUS \ 311 | FATTR4_WORD0_FILES_FREE | FATTR4_WORD0_FILES_TOTAL | FATTR4_WORD0_FS_LOCATIONS | FATTR4_WORD0_HOMOGENEOUS \
311 | FATTR4_WORD0_MAXFILESIZE | FATTR4_WORD0_MAXLINK | FATTR4_WORD0_MAXNAME \ 312 | FATTR4_WORD0_MAXFILESIZE | FATTR4_WORD0_MAXLINK | FATTR4_WORD0_MAXNAME \
312 | FATTR4_WORD0_MAXREAD | FATTR4_WORD0_MAXWRITE | FATTR4_WORD0_ACL) 313 | FATTR4_WORD0_MAXREAD | FATTR4_WORD0_MAXWRITE | FATTR4_WORD0_ACL)
313 314
diff --git a/include/linux/nfsd/xdr.h b/include/linux/nfsd/xdr.h
index a38f9d776de9..0e53de87d886 100644
--- a/include/linux/nfsd/xdr.h
+++ b/include/linux/nfsd/xdr.h
@@ -30,7 +30,6 @@ struct nfsd_readargs {
30 struct svc_fh fh; 30 struct svc_fh fh;
31 __u32 offset; 31 __u32 offset;
32 __u32 count; 32 __u32 count;
33 struct kvec vec[RPCSVC_MAXPAGES];
34 int vlen; 33 int vlen;
35}; 34};
36 35
@@ -38,7 +37,6 @@ struct nfsd_writeargs {
38 svc_fh fh; 37 svc_fh fh;
39 __u32 offset; 38 __u32 offset;
40 int len; 39 int len;
41 struct kvec vec[RPCSVC_MAXPAGES];
42 int vlen; 40 int vlen;
43}; 41};
44 42
diff --git a/include/linux/nfsd/xdr3.h b/include/linux/nfsd/xdr3.h
index a4322741f8b9..474d882dc2f3 100644
--- a/include/linux/nfsd/xdr3.h
+++ b/include/linux/nfsd/xdr3.h
@@ -33,7 +33,6 @@ struct nfsd3_readargs {
33 struct svc_fh fh; 33 struct svc_fh fh;
34 __u64 offset; 34 __u64 offset;
35 __u32 count; 35 __u32 count;
36 struct kvec vec[RPCSVC_MAXPAGES];
37 int vlen; 36 int vlen;
38}; 37};
39 38
@@ -43,7 +42,6 @@ struct nfsd3_writeargs {
43 __u32 count; 42 __u32 count;
44 int stable; 43 int stable;
45 __u32 len; 44 __u32 len;
46 struct kvec vec[RPCSVC_MAXPAGES];
47 int vlen; 45 int vlen;
48}; 46};
49 47
diff --git a/include/linux/nfsd/xdr4.h b/include/linux/nfsd/xdr4.h
index 77adba7d2281..66e642762a07 100644
--- a/include/linux/nfsd/xdr4.h
+++ b/include/linux/nfsd/xdr4.h
@@ -241,7 +241,6 @@ struct nfsd4_read {
241 stateid_t rd_stateid; /* request */ 241 stateid_t rd_stateid; /* request */
242 u64 rd_offset; /* request */ 242 u64 rd_offset; /* request */
243 u32 rd_length; /* request */ 243 u32 rd_length; /* request */
244 struct kvec rd_iov[RPCSVC_MAXPAGES];
245 int rd_vlen; 244 int rd_vlen;
246 struct file *rd_filp; 245 struct file *rd_filp;
247 246
@@ -326,7 +325,6 @@ struct nfsd4_write {
326 u64 wr_offset; /* request */ 325 u64 wr_offset; /* request */
327 u32 wr_stable_how; /* request */ 326 u32 wr_stable_how; /* request */
328 u32 wr_buflen; /* request */ 327 u32 wr_buflen; /* request */
329 struct kvec wr_vec[RPCSVC_MAXPAGES]; /* request */
330 int wr_vlen; 328 int wr_vlen;
331 329
332 u32 wr_bytes_written; /* response */ 330 u32 wr_bytes_written; /* response */
diff --git a/include/linux/notifier.h b/include/linux/notifier.h
index 7ff386a6ae87..10a43ed0527e 100644
--- a/include/linux/notifier.h
+++ b/include/linux/notifier.h
@@ -12,9 +12,10 @@
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/mutex.h> 13#include <linux/mutex.h>
14#include <linux/rwsem.h> 14#include <linux/rwsem.h>
15#include <linux/srcu.h>
15 16
16/* 17/*
17 * Notifier chains are of three types: 18 * Notifier chains are of four types:
18 * 19 *
19 * Atomic notifier chains: Chain callbacks run in interrupt/atomic 20 * Atomic notifier chains: Chain callbacks run in interrupt/atomic
20 * context. Callouts are not allowed to block. 21 * context. Callouts are not allowed to block.
@@ -23,13 +24,27 @@
23 * Raw notifier chains: There are no restrictions on callbacks, 24 * Raw notifier chains: There are no restrictions on callbacks,
24 * registration, or unregistration. All locking and protection 25 * registration, or unregistration. All locking and protection
25 * must be provided by the caller. 26 * must be provided by the caller.
27 * SRCU notifier chains: A variant of blocking notifier chains, with
28 * the same restrictions.
26 * 29 *
27 * atomic_notifier_chain_register() may be called from an atomic context, 30 * atomic_notifier_chain_register() may be called from an atomic context,
28 * but blocking_notifier_chain_register() must be called from a process 31 * but blocking_notifier_chain_register() and srcu_notifier_chain_register()
29 * context. Ditto for the corresponding _unregister() routines. 32 * must be called from a process context. Ditto for the corresponding
33 * _unregister() routines.
30 * 34 *
31 * atomic_notifier_chain_unregister() and blocking_notifier_chain_unregister() 35 * atomic_notifier_chain_unregister(), blocking_notifier_chain_unregister(),
32 * _must not_ be called from within the call chain. 36 * and srcu_notifier_chain_unregister() _must not_ be called from within
37 * the call chain.
38 *
39 * SRCU notifier chains are an alternative form of blocking notifier chains.
40 * They use SRCU (Sleepable Read-Copy Update) instead of rw-semaphores for
41 * protection of the chain links. This means there is _very_ low overhead
42 * in srcu_notifier_call_chain(): no cache bounces and no memory barriers.
43 * As compensation, srcu_notifier_chain_unregister() is rather expensive.
44 * SRCU notifier chains should be used when the chain will be called very
45 * often but notifier_blocks will seldom be removed. Also, SRCU notifier
46 * chains are slightly more difficult to use because they require special
47 * runtime initialization.
33 */ 48 */
34 49
35struct notifier_block { 50struct notifier_block {
@@ -52,6 +67,12 @@ struct raw_notifier_head {
52 struct notifier_block *head; 67 struct notifier_block *head;
53}; 68};
54 69
70struct srcu_notifier_head {
71 struct mutex mutex;
72 struct srcu_struct srcu;
73 struct notifier_block *head;
74};
75
55#define ATOMIC_INIT_NOTIFIER_HEAD(name) do { \ 76#define ATOMIC_INIT_NOTIFIER_HEAD(name) do { \
56 spin_lock_init(&(name)->lock); \ 77 spin_lock_init(&(name)->lock); \
57 (name)->head = NULL; \ 78 (name)->head = NULL; \
@@ -64,6 +85,11 @@ struct raw_notifier_head {
64 (name)->head = NULL; \ 85 (name)->head = NULL; \
65 } while (0) 86 } while (0)
66 87
88/* srcu_notifier_heads must be initialized and cleaned up dynamically */
89extern void srcu_init_notifier_head(struct srcu_notifier_head *nh);
90#define srcu_cleanup_notifier_head(name) \
91 cleanup_srcu_struct(&(name)->srcu);
92
67#define ATOMIC_NOTIFIER_INIT(name) { \ 93#define ATOMIC_NOTIFIER_INIT(name) { \
68 .lock = __SPIN_LOCK_UNLOCKED(name.lock), \ 94 .lock = __SPIN_LOCK_UNLOCKED(name.lock), \
69 .head = NULL } 95 .head = NULL }
@@ -72,6 +98,7 @@ struct raw_notifier_head {
72 .head = NULL } 98 .head = NULL }
73#define RAW_NOTIFIER_INIT(name) { \ 99#define RAW_NOTIFIER_INIT(name) { \
74 .head = NULL } 100 .head = NULL }
101/* srcu_notifier_heads cannot be initialized statically */
75 102
76#define ATOMIC_NOTIFIER_HEAD(name) \ 103#define ATOMIC_NOTIFIER_HEAD(name) \
77 struct atomic_notifier_head name = \ 104 struct atomic_notifier_head name = \
@@ -91,6 +118,8 @@ extern int blocking_notifier_chain_register(struct blocking_notifier_head *,
91 struct notifier_block *); 118 struct notifier_block *);
92extern int raw_notifier_chain_register(struct raw_notifier_head *, 119extern int raw_notifier_chain_register(struct raw_notifier_head *,
93 struct notifier_block *); 120 struct notifier_block *);
121extern int srcu_notifier_chain_register(struct srcu_notifier_head *,
122 struct notifier_block *);
94 123
95extern int atomic_notifier_chain_unregister(struct atomic_notifier_head *, 124extern int atomic_notifier_chain_unregister(struct atomic_notifier_head *,
96 struct notifier_block *); 125 struct notifier_block *);
@@ -98,6 +127,8 @@ extern int blocking_notifier_chain_unregister(struct blocking_notifier_head *,
98 struct notifier_block *); 127 struct notifier_block *);
99extern int raw_notifier_chain_unregister(struct raw_notifier_head *, 128extern int raw_notifier_chain_unregister(struct raw_notifier_head *,
100 struct notifier_block *); 129 struct notifier_block *);
130extern int srcu_notifier_chain_unregister(struct srcu_notifier_head *,
131 struct notifier_block *);
101 132
102extern int atomic_notifier_call_chain(struct atomic_notifier_head *, 133extern int atomic_notifier_call_chain(struct atomic_notifier_head *,
103 unsigned long val, void *v); 134 unsigned long val, void *v);
@@ -105,6 +136,8 @@ extern int blocking_notifier_call_chain(struct blocking_notifier_head *,
105 unsigned long val, void *v); 136 unsigned long val, void *v);
106extern int raw_notifier_call_chain(struct raw_notifier_head *, 137extern int raw_notifier_call_chain(struct raw_notifier_head *,
107 unsigned long val, void *v); 138 unsigned long val, void *v);
139extern int srcu_notifier_call_chain(struct srcu_notifier_head *,
140 unsigned long val, void *v);
108 141
109#define NOTIFY_DONE 0x0000 /* Don't care */ 142#define NOTIFY_DONE 0x0000 /* Don't care */
110#define NOTIFY_OK 0x0001 /* Suits me */ 143#define NOTIFY_OK 0x0001 /* Suits me */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 4431ce4e1e6f..5c604f5fad67 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -595,6 +595,7 @@ struct msix_entry {
595 u16 entry; /* driver uses to specify entry, OS writes */ 595 u16 entry; /* driver uses to specify entry, OS writes */
596}; 596};
597 597
598
598#ifndef CONFIG_PCI_MSI 599#ifndef CONFIG_PCI_MSI
599static inline void pci_scan_msi_device(struct pci_dev *dev) {} 600static inline void pci_scan_msi_device(struct pci_dev *dev) {}
600static inline int pci_enable_msi(struct pci_dev *dev) {return -1;} 601static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
@@ -613,6 +614,12 @@ extern void pci_disable_msix(struct pci_dev *dev);
613extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); 614extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
614#endif 615#endif
615 616
617#ifdef CONFIG_HT_IRQ
618/* The functions a driver should call */
619int ht_create_irq(struct pci_dev *dev, int idx);
620void ht_destroy_irq(unsigned int irq);
621#endif /* CONFIG_HT_IRQ */
622
616extern void pci_block_user_cfg_access(struct pci_dev *dev); 623extern void pci_block_user_cfg_access(struct pci_dev *dev);
617extern void pci_unblock_user_cfg_access(struct pci_dev *dev); 624extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
618 625
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 7d0e26cba420..c312a12ad2d6 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -12,6 +12,11 @@
12 * PCI Local Bus Specification 12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification 13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide 14 * PCI System Design Guide
15 *
16 * For hypertransport information, please consult the following manuals
17 * from http://www.hypertransport.org
18 *
19 * The Hypertransport I/O Link Specification
15 */ 20 */
16 21
17#ifndef LINUX_PCI_REGS_H 22#ifndef LINUX_PCI_REGS_H
@@ -463,4 +468,20 @@
463#define PCI_PWR_CAP 12 /* Capability */ 468#define PCI_PWR_CAP 12 /* Capability */
464#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 469#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
465 470
471/* Hypertransport sub capability types */
472#define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */
473#define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */
474#define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */
475#define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */
476#define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */
477#define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */
478#define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */
479#define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */
480#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */
481#define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */
482#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
483#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */
484#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */
485
486
466#endif /* LINUX_PCI_REGS_H */ 487#endif /* LINUX_PCI_REGS_H */
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index b4ca73d65891..c6b7485eac7c 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -19,7 +19,7 @@
19 * 19 *
20 * Author: Dipankar Sarma <dipankar@in.ibm.com> 20 * Author: Dipankar Sarma <dipankar@in.ibm.com>
21 * 21 *
22 * Based on the original work by Paul McKenney <paul.mckenney@us.ibm.com> 22 * Based on the original work by Paul McKenney <paulmck@us.ibm.com>
23 * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen. 23 * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen.
24 * Papers: 24 * Papers:
25 * http://www.rdrop.com/users/paulmck/paper/rclockpdcsproof.pdf 25 * http://www.rdrop.com/users/paulmck/paper/rclockpdcsproof.pdf
@@ -66,6 +66,8 @@ struct rcu_ctrlblk {
66 long completed; /* Number of the last completed batch */ 66 long completed; /* Number of the last completed batch */
67 int next_pending; /* Is the next batch already waiting? */ 67 int next_pending; /* Is the next batch already waiting? */
68 68
69 int signaled;
70
69 spinlock_t lock ____cacheline_internodealigned_in_smp; 71 spinlock_t lock ____cacheline_internodealigned_in_smp;
70 cpumask_t cpumask; /* CPUs that need to switch in order */ 72 cpumask_t cpumask; /* CPUs that need to switch in order */
71 /* for current batch to proceed. */ 73 /* for current batch to proceed. */
@@ -106,9 +108,6 @@ struct rcu_data {
106 long blimit; /* Upper limit on a processed batch */ 108 long blimit; /* Upper limit on a processed batch */
107 int cpu; 109 int cpu;
108 struct rcu_head barrier; 110 struct rcu_head barrier;
109#ifdef CONFIG_SMP
110 long last_rs_qlen; /* qlen during the last resched */
111#endif
112}; 111};
113 112
114DECLARE_PER_CPU(struct rcu_data, rcu_data); 113DECLARE_PER_CPU(struct rcu_data, rcu_data);
diff --git a/include/linux/scx200.h b/include/linux/scx200.h
index 693c0557e70b..de466e11e271 100644
--- a/include/linux/scx200.h
+++ b/include/linux/scx200.h
@@ -32,7 +32,7 @@ extern unsigned scx200_cb_base;
32 32
33/* High Resolution Timer */ 33/* High Resolution Timer */
34#define SCx200_TIMER_OFFSET 0x08 34#define SCx200_TIMER_OFFSET 0x08
35#define SCx200_TIMER_SIZE 0x05 35#define SCx200_TIMER_SIZE 0x06
36 36
37/* Clock Generators */ 37/* Clock Generators */
38#define SCx200_CLOCKGEN_OFFSET 0x10 38#define SCx200_CLOCKGEN_OFFSET 0x10
diff --git a/include/linux/slab.h b/include/linux/slab.h
index 70be57d8ae0d..c4947b8a2c03 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -77,13 +77,6 @@ struct cache_sizes {
77extern struct cache_sizes malloc_sizes[]; 77extern struct cache_sizes malloc_sizes[];
78 78
79extern void *__kmalloc(size_t, gfp_t); 79extern void *__kmalloc(size_t, gfp_t);
80#ifndef CONFIG_DEBUG_SLAB
81#define ____kmalloc(size, flags) __kmalloc(size, flags)
82#else
83extern void *__kmalloc_track_caller(size_t, gfp_t, void*);
84#define ____kmalloc(size, flags) \
85 __kmalloc_track_caller(size, flags, __builtin_return_address(0))
86#endif
87 80
88/** 81/**
89 * kmalloc - allocate memory 82 * kmalloc - allocate memory
@@ -153,6 +146,23 @@ found:
153 return __kmalloc(size, flags); 146 return __kmalloc(size, flags);
154} 147}
155 148
149/*
150 * kmalloc_track_caller is a special version of kmalloc that records the
151 * calling function of the routine calling it for slab leak tracking instead
152 * of just the calling function (confusing, eh?).
153 * It's useful when the call to kmalloc comes from a widely-used standard
154 * allocator where we care about the real place the memory allocation
155 * request comes from.
156 */
157#ifndef CONFIG_DEBUG_SLAB
158#define kmalloc_track_caller(size, flags) \
159 __kmalloc(size, flags)
160#else
161extern void *__kmalloc_track_caller(size_t, gfp_t, void*);
162#define kmalloc_track_caller(size, flags) \
163 __kmalloc_track_caller(size, flags, __builtin_return_address(0))
164#endif
165
156extern void *__kzalloc(size_t, gfp_t); 166extern void *__kzalloc(size_t, gfp_t);
157 167
158/** 168/**
@@ -271,7 +281,7 @@ static inline void *kcalloc(size_t n, size_t size, gfp_t flags)
271#define kmem_cache_alloc_node(c, f, n) kmem_cache_alloc(c, f) 281#define kmem_cache_alloc_node(c, f, n) kmem_cache_alloc(c, f)
272#define kmalloc_node(s, f, n) kmalloc(s, f) 282#define kmalloc_node(s, f, n) kmalloc(s, f)
273#define kzalloc(s, f) __kzalloc(s, f) 283#define kzalloc(s, f) __kzalloc(s, f)
274#define ____kmalloc kmalloc 284#define kmalloc_track_caller kmalloc
275 285
276#endif /* CONFIG_SLOB */ 286#endif /* CONFIG_SLOB */
277 287
diff --git a/include/linux/sound.h b/include/linux/sound.h
index f63d8342ffa3..9e2a94feed6b 100644
--- a/include/linux/sound.h
+++ b/include/linux/sound.h
@@ -35,10 +35,8 @@ extern int register_sound_special_device(const struct file_operations *fops, int
35extern int register_sound_mixer(const struct file_operations *fops, int dev); 35extern int register_sound_mixer(const struct file_operations *fops, int dev);
36extern int register_sound_midi(const struct file_operations *fops, int dev); 36extern int register_sound_midi(const struct file_operations *fops, int dev);
37extern int register_sound_dsp(const struct file_operations *fops, int dev); 37extern int register_sound_dsp(const struct file_operations *fops, int dev);
38extern int register_sound_synth(const struct file_operations *fops, int dev);
39 38
40extern void unregister_sound_special(int unit); 39extern void unregister_sound_special(int unit);
41extern void unregister_sound_mixer(int unit); 40extern void unregister_sound_mixer(int unit);
42extern void unregister_sound_midi(int unit); 41extern void unregister_sound_midi(int unit);
43extern void unregister_sound_dsp(int unit); 42extern void unregister_sound_dsp(int unit);
44extern void unregister_sound_synth(int unit);
diff --git a/include/linux/srcu.h b/include/linux/srcu.h
new file mode 100644
index 000000000000..aca0eee53930
--- /dev/null
+++ b/include/linux/srcu.h
@@ -0,0 +1,53 @@
1/*
2 * Sleepable Read-Copy Update mechanism for mutual exclusion
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright (C) IBM Corporation, 2006
19 *
20 * Author: Paul McKenney <paulmck@us.ibm.com>
21 *
22 * For detailed explanation of Read-Copy Update mechanism see -
23 * Documentation/RCU/ *.txt
24 *
25 */
26
27#ifndef _LINUX_SRCU_H
28#define _LINUX_SRCU_H
29
30struct srcu_struct_array {
31 int c[2];
32};
33
34struct srcu_struct {
35 int completed;
36 struct srcu_struct_array *per_cpu_ref;
37 struct mutex mutex;
38};
39
40#ifndef CONFIG_PREEMPT
41#define srcu_barrier() barrier()
42#else /* #ifndef CONFIG_PREEMPT */
43#define srcu_barrier()
44#endif /* #else #ifndef CONFIG_PREEMPT */
45
46int init_srcu_struct(struct srcu_struct *sp);
47void cleanup_srcu_struct(struct srcu_struct *sp);
48int srcu_read_lock(struct srcu_struct *sp) __acquires(sp);
49void srcu_read_unlock(struct srcu_struct *sp, int idx) __releases(sp);
50void synchronize_srcu(struct srcu_struct *sp);
51long srcu_batches_completed(struct srcu_struct *sp);
52
53#endif
diff --git a/include/linux/sunrpc/auth.h b/include/linux/sunrpc/auth.h
index 862c0d8c8381..534cdc7be58d 100644
--- a/include/linux/sunrpc/auth.h
+++ b/include/linux/sunrpc/auth.h
@@ -20,9 +20,6 @@
20/* size of the nodename buffer */ 20/* size of the nodename buffer */
21#define UNX_MAXNODENAME 32 21#define UNX_MAXNODENAME 32
22 22
23/* Maximum size (in bytes) of an rpc credential or verifier */
24#define RPC_MAX_AUTH_SIZE (400)
25
26/* Work around the lack of a VFS credential */ 23/* Work around the lack of a VFS credential */
27struct auth_cred { 24struct auth_cred {
28 uid_t uid; 25 uid_t uid;
diff --git a/include/linux/sunrpc/cache.h b/include/linux/sunrpc/cache.h
index b5612c958cce..3699dff7db8f 100644
--- a/include/linux/sunrpc/cache.h
+++ b/include/linux/sunrpc/cache.h
@@ -163,6 +163,17 @@ static inline void cache_put(struct cache_head *h, struct cache_detail *cd)
163 kref_put(&h->ref, cd->cache_put); 163 kref_put(&h->ref, cd->cache_put);
164} 164}
165 165
166static inline int cache_valid(struct cache_head *h)
167{
168 /* If an item has been unhashed pending removal when
169 * the refcount drops to 0, the expiry_time will be
170 * set to 0. We don't want to consider such items
171 * valid in this context even though CACHE_VALID is
172 * set.
173 */
174 return (h->expiry_time != 0 && test_bit(CACHE_VALID, &h->flags));
175}
176
166extern int cache_check(struct cache_detail *detail, 177extern int cache_check(struct cache_detail *detail,
167 struct cache_head *h, struct cache_req *rqstp); 178 struct cache_head *h, struct cache_req *rqstp);
168extern void cache_flush(void); 179extern void cache_flush(void);
diff --git a/include/linux/sunrpc/msg_prot.h b/include/linux/sunrpc/msg_prot.h
index 8d10d148834e..1e65f2dd80e5 100644
--- a/include/linux/sunrpc/msg_prot.h
+++ b/include/linux/sunrpc/msg_prot.h
@@ -11,6 +11,9 @@
11 11
12#define RPC_VERSION 2 12#define RPC_VERSION 2
13 13
14/* size of an XDR encoding unit in bytes, i.e. 32bit */
15#define XDR_UNIT (4)
16
14/* spec defines authentication flavor as an unsigned 32 bit integer */ 17/* spec defines authentication flavor as an unsigned 32 bit integer */
15typedef u32 rpc_authflavor_t; 18typedef u32 rpc_authflavor_t;
16 19
@@ -34,6 +37,9 @@ enum rpc_auth_flavors {
34 RPC_AUTH_GSS_SPKMP = 390011, 37 RPC_AUTH_GSS_SPKMP = 390011,
35}; 38};
36 39
40/* Maximum size (in bytes) of an rpc credential or verifier */
41#define RPC_MAX_AUTH_SIZE (400)
42
37enum rpc_msg_type { 43enum rpc_msg_type {
38 RPC_CALL = 0, 44 RPC_CALL = 0,
39 RPC_REPLY = 1 45 RPC_REPLY = 1
@@ -101,5 +107,39 @@ typedef __be32 rpc_fraghdr;
101#define RPC_FRAGMENT_SIZE_MASK (~RPC_LAST_STREAM_FRAGMENT) 107#define RPC_FRAGMENT_SIZE_MASK (~RPC_LAST_STREAM_FRAGMENT)
102#define RPC_MAX_FRAGMENT_SIZE ((1U << 31) - 1) 108#define RPC_MAX_FRAGMENT_SIZE ((1U << 31) - 1)
103 109
110/*
111 * RPC call and reply header size as number of 32bit words (verifier
112 * size computed separately, see below)
113 */
114#define RPC_CALLHDRSIZE (6)
115#define RPC_REPHDRSIZE (4)
116
117
118/*
119 * Maximum RPC header size, including authentication,
120 * as number of 32bit words (see RFCs 1831, 1832).
121 *
122 * xid 1 xdr unit = 4 bytes
123 * mtype 1
124 * rpc_version 1
125 * program 1
126 * prog_version 1
127 * procedure 1
128 * cred {
129 * flavor 1
130 * length 1
131 * body<RPC_MAX_AUTH_SIZE> 100 xdr units = 400 bytes
132 * }
133 * verf {
134 * flavor 1
135 * length 1
136 * body<RPC_MAX_AUTH_SIZE> 100 xdr units = 400 bytes
137 * }
138 * TOTAL 210 xdr units = 840 bytes
139 */
140#define RPC_MAX_HEADER_WITH_AUTH \
141 (RPC_CALLHDRSIZE + 2*(2+RPC_MAX_AUTH_SIZE/4))
142
143
104#endif /* __KERNEL__ */ 144#endif /* __KERNEL__ */
105#endif /* _LINUX_SUNRPC_MSGPROT_H_ */ 145#endif /* _LINUX_SUNRPC_MSGPROT_H_ */
diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
index 4ebcdf91f3b3..d6288e89fd9d 100644
--- a/include/linux/sunrpc/svc.h
+++ b/include/linux/sunrpc/svc.h
@@ -13,6 +13,7 @@
13#include <linux/in.h> 13#include <linux/in.h>
14#include <linux/sunrpc/types.h> 14#include <linux/sunrpc/types.h>
15#include <linux/sunrpc/xdr.h> 15#include <linux/sunrpc/xdr.h>
16#include <linux/sunrpc/auth.h>
16#include <linux/sunrpc/svcauth.h> 17#include <linux/sunrpc/svcauth.h>
17#include <linux/wait.h> 18#include <linux/wait.h>
18#include <linux/mm.h> 19#include <linux/mm.h>
@@ -95,8 +96,28 @@ static inline void svc_get(struct svc_serv *serv)
95 * Maximum payload size supported by a kernel RPC server. 96 * Maximum payload size supported by a kernel RPC server.
96 * This is use to determine the max number of pages nfsd is 97 * This is use to determine the max number of pages nfsd is
97 * willing to return in a single READ operation. 98 * willing to return in a single READ operation.
99 *
100 * These happen to all be powers of 2, which is not strictly
101 * necessary but helps enforce the real limitation, which is
102 * that they should be multiples of PAGE_CACHE_SIZE.
103 *
104 * For UDP transports, a block plus NFS,RPC, and UDP headers
105 * has to fit into the IP datagram limit of 64K. The largest
106 * feasible number for all known page sizes is probably 48K,
107 * but we choose 32K here. This is the same as the historical
108 * Linux limit; someone who cares more about NFS/UDP performance
109 * can test a larger number.
110 *
111 * For TCP transports we have more freedom. A size of 1MB is
112 * chosen to match the client limit. Other OSes are known to
113 * have larger limits, but those numbers are probably beyond
114 * the point of diminishing returns.
98 */ 115 */
99#define RPCSVC_MAXPAYLOAD (64*1024u) 116#define RPCSVC_MAXPAYLOAD (1*1024*1024u)
117#define RPCSVC_MAXPAYLOAD_TCP RPCSVC_MAXPAYLOAD
118#define RPCSVC_MAXPAYLOAD_UDP (32*1024u)
119
120extern u32 svc_max_payload(const struct svc_rqst *rqstp);
100 121
101/* 122/*
102 * RPC Requsts and replies are stored in one or more pages. 123 * RPC Requsts and replies are stored in one or more pages.
@@ -170,7 +191,6 @@ static inline void svc_putu32(struct kvec *iov, __be32 val)
170/* 191/*
171 * The context of a single thread, including the request currently being 192 * The context of a single thread, including the request currently being
172 * processed. 193 * processed.
173 * NOTE: First two items must be prev/next.
174 */ 194 */
175struct svc_rqst { 195struct svc_rqst {
176 struct list_head rq_list; /* idle list */ 196 struct list_head rq_list; /* idle list */
@@ -189,12 +209,11 @@ struct svc_rqst {
189 209
190 struct xdr_buf rq_arg; 210 struct xdr_buf rq_arg;
191 struct xdr_buf rq_res; 211 struct xdr_buf rq_res;
192 struct page * rq_argpages[RPCSVC_MAXPAGES]; 212 struct page * rq_pages[RPCSVC_MAXPAGES];
193 struct page * rq_respages[RPCSVC_MAXPAGES]; 213 struct page * *rq_respages; /* points into rq_pages */
194 int rq_restailpage; 214 int rq_resused; /* number of pages used for result */
195 short rq_argused; /* pages used for argument */ 215
196 short rq_arghi; /* pages available in argument page list */ 216 struct kvec rq_vec[RPCSVC_MAXPAGES]; /* generally useful.. */
197 short rq_resused; /* pages used for result */
198 217
199 __be32 rq_xid; /* transmission id */ 218 __be32 rq_xid; /* transmission id */
200 u32 rq_prog; /* program number */ 219 u32 rq_prog; /* program number */
@@ -255,63 +274,18 @@ xdr_ressize_check(struct svc_rqst *rqstp, __be32 *p)
255 return vec->iov_len <= PAGE_SIZE; 274 return vec->iov_len <= PAGE_SIZE;
256} 275}
257 276
258static inline struct page * 277static inline void svc_free_res_pages(struct svc_rqst *rqstp)
259svc_take_res_page(struct svc_rqst *rqstp)
260{
261 if (rqstp->rq_arghi <= rqstp->rq_argused)
262 return NULL;
263 rqstp->rq_arghi--;
264 rqstp->rq_respages[rqstp->rq_resused] =
265 rqstp->rq_argpages[rqstp->rq_arghi];
266 return rqstp->rq_respages[rqstp->rq_resused++];
267}
268
269static inline void svc_take_page(struct svc_rqst *rqstp)
270{
271 if (rqstp->rq_arghi <= rqstp->rq_argused) {
272 WARN_ON(1);
273 return;
274 }
275 rqstp->rq_arghi--;
276 rqstp->rq_respages[rqstp->rq_resused] =
277 rqstp->rq_argpages[rqstp->rq_arghi];
278 rqstp->rq_resused++;
279}
280
281static inline void svc_pushback_allpages(struct svc_rqst *rqstp)
282{
283 while (rqstp->rq_resused) {
284 if (rqstp->rq_respages[--rqstp->rq_resused] == NULL)
285 continue;
286 rqstp->rq_argpages[rqstp->rq_arghi++] =
287 rqstp->rq_respages[rqstp->rq_resused];
288 rqstp->rq_respages[rqstp->rq_resused] = NULL;
289 }
290}
291
292static inline void svc_pushback_unused_pages(struct svc_rqst *rqstp)
293{ 278{
294 while (rqstp->rq_resused && 279 while (rqstp->rq_resused) {
295 rqstp->rq_res.pages != &rqstp->rq_respages[rqstp->rq_resused]) { 280 struct page **pp = (rqstp->rq_respages +
296 281 --rqstp->rq_resused);
297 if (rqstp->rq_respages[--rqstp->rq_resused] != NULL) { 282 if (*pp) {
298 rqstp->rq_argpages[rqstp->rq_arghi++] = 283 put_page(*pp);
299 rqstp->rq_respages[rqstp->rq_resused]; 284 *pp = NULL;
300 rqstp->rq_respages[rqstp->rq_resused] = NULL;
301 } 285 }
302 } 286 }
303} 287}
304 288
305static inline void svc_free_allpages(struct svc_rqst *rqstp)
306{
307 while (rqstp->rq_resused) {
308 if (rqstp->rq_respages[--rqstp->rq_resused] == NULL)
309 continue;
310 put_page(rqstp->rq_respages[rqstp->rq_resused]);
311 rqstp->rq_respages[rqstp->rq_resused] = NULL;
312 }
313}
314
315struct svc_deferred_req { 289struct svc_deferred_req {
316 u32 prot; /* protocol (UDP or TCP) */ 290 u32 prot; /* protocol (UDP or TCP) */
317 struct sockaddr_in addr; 291 struct sockaddr_in addr;
@@ -347,6 +321,9 @@ struct svc_version {
347 struct svc_procedure * vs_proc; /* per-procedure info */ 321 struct svc_procedure * vs_proc; /* per-procedure info */
348 u32 vs_xdrsize; /* xdrsize needed for this version */ 322 u32 vs_xdrsize; /* xdrsize needed for this version */
349 323
324 unsigned int vs_hidden : 1; /* Don't register with portmapper.
325 * Only used for nfsacl so far. */
326
350 /* Override dispatch function (e.g. when caching replies). 327 /* Override dispatch function (e.g. when caching replies).
351 * A return value of 0 means drop the request. 328 * A return value of 0 means drop the request.
352 * vs_dispatch == NULL means use default dispatcher. 329 * vs_dispatch == NULL means use default dispatcher.
diff --git a/include/linux/sunrpc/svcauth.h b/include/linux/sunrpc/svcauth.h
index a6601650deeb..de92619b0826 100644
--- a/include/linux/sunrpc/svcauth.h
+++ b/include/linux/sunrpc/svcauth.h
@@ -126,6 +126,7 @@ extern struct auth_domain *auth_domain_find(char *name);
126extern struct auth_domain *auth_unix_lookup(struct in_addr addr); 126extern struct auth_domain *auth_unix_lookup(struct in_addr addr);
127extern int auth_unix_forget_old(struct auth_domain *dom); 127extern int auth_unix_forget_old(struct auth_domain *dom);
128extern void svcauth_unix_purge(void); 128extern void svcauth_unix_purge(void);
129extern void svcauth_unix_info_release(void *);
129 130
130static inline unsigned long hash_str(char *name, int bits) 131static inline unsigned long hash_str(char *name, int bits)
131{ 132{
diff --git a/include/linux/sunrpc/svcsock.h b/include/linux/sunrpc/svcsock.h
index 4c296152cbfa..98b21ad370fd 100644
--- a/include/linux/sunrpc/svcsock.h
+++ b/include/linux/sunrpc/svcsock.h
@@ -54,6 +54,9 @@ struct svc_sock {
54 int sk_reclen; /* length of record */ 54 int sk_reclen; /* length of record */
55 int sk_tcplen; /* current read length */ 55 int sk_tcplen; /* current read length */
56 time_t sk_lastrecv; /* time of last received request */ 56 time_t sk_lastrecv; /* time of last received request */
57
58 /* cache of various info for TCP sockets */
59 void *sk_info_authunix;
57}; 60};
58 61
59/* 62/*
diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h
index 6cf626580752..60394fbc4c70 100644
--- a/include/linux/sunrpc/xprt.h
+++ b/include/linux/sunrpc/xprt.h
@@ -15,6 +15,7 @@
15#include <linux/kref.h> 15#include <linux/kref.h>
16#include <linux/sunrpc/sched.h> 16#include <linux/sunrpc/sched.h>
17#include <linux/sunrpc/xdr.h> 17#include <linux/sunrpc/xdr.h>
18#include <linux/sunrpc/msg_prot.h>
18 19
19extern unsigned int xprt_udp_slot_table_entries; 20extern unsigned int xprt_udp_slot_table_entries;
20extern unsigned int xprt_tcp_slot_table_entries; 21extern unsigned int xprt_tcp_slot_table_entries;
@@ -24,13 +25,6 @@ extern unsigned int xprt_tcp_slot_table_entries;
24#define RPC_MAX_SLOT_TABLE (128U) 25#define RPC_MAX_SLOT_TABLE (128U)
25 26
26/* 27/*
27 * RPC call and reply header size as number of 32bit words (verifier
28 * size computed separately)
29 */
30#define RPC_CALLHDRSIZE 6
31#define RPC_REPHDRSIZE 4
32
33/*
34 * Parameters for choosing a free port 28 * Parameters for choosing a free port
35 */ 29 */
36extern unsigned int xprt_min_resvport; 30extern unsigned int xprt_min_resvport;
diff --git a/include/linux/tifm.h b/include/linux/tifm.h
new file mode 100644
index 000000000000..203dd5e11ecb
--- /dev/null
+++ b/include/linux/tifm.h
@@ -0,0 +1,158 @@
1/*
2 * tifm.h - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef _TIFM_H
13#define _TIFM_H
14
15#include <linux/spinlock.h>
16#include <linux/interrupt.h>
17#include <linux/wait.h>
18#include <linux/delay.h>
19#include <linux/pci.h>
20
21/* Host registers (relative to pci base address): */
22enum {
23 FM_SET_INTERRUPT_ENABLE = 0x008,
24 FM_CLEAR_INTERRUPT_ENABLE = 0x00c,
25 FM_INTERRUPT_STATUS = 0x014 };
26
27/* Socket registers (relative to socket base address): */
28enum {
29 SOCK_CONTROL = 0x004,
30 SOCK_PRESENT_STATE = 0x008,
31 SOCK_DMA_ADDRESS = 0x00c,
32 SOCK_DMA_CONTROL = 0x010,
33 SOCK_DMA_FIFO_INT_ENABLE_SET = 0x014,
34 SOCK_DMA_FIFO_INT_ENABLE_CLEAR = 0x018,
35 SOCK_DMA_FIFO_STATUS = 0x020,
36 SOCK_FIFO_CONTROL = 0x024,
37 SOCK_FIFO_PAGE_SIZE = 0x028,
38 SOCK_MMCSD_COMMAND = 0x104,
39 SOCK_MMCSD_ARG_LOW = 0x108,
40 SOCK_MMCSD_ARG_HIGH = 0x10c,
41 SOCK_MMCSD_CONFIG = 0x110,
42 SOCK_MMCSD_STATUS = 0x114,
43 SOCK_MMCSD_INT_ENABLE = 0x118,
44 SOCK_MMCSD_COMMAND_TO = 0x11c,
45 SOCK_MMCSD_DATA_TO = 0x120,
46 SOCK_MMCSD_DATA = 0x124,
47 SOCK_MMCSD_BLOCK_LEN = 0x128,
48 SOCK_MMCSD_NUM_BLOCKS = 0x12c,
49 SOCK_MMCSD_BUFFER_CONFIG = 0x130,
50 SOCK_MMCSD_SPI_CONFIG = 0x134,
51 SOCK_MMCSD_SDIO_MODE_CONFIG = 0x138,
52 SOCK_MMCSD_RESPONSE = 0x144,
53 SOCK_MMCSD_SDIO_SR = 0x164,
54 SOCK_MMCSD_SYSTEM_CONTROL = 0x168,
55 SOCK_MMCSD_SYSTEM_STATUS = 0x16c,
56 SOCK_MS_COMMAND = 0x184,
57 SOCK_MS_DATA = 0x188,
58 SOCK_MS_STATUS = 0x18c,
59 SOCK_MS_SYSTEM = 0x190,
60 SOCK_FIFO_ACCESS = 0x200 };
61
62
63#define TIFM_IRQ_ENABLE 0x80000000
64#define TIFM_IRQ_SOCKMASK 0x00000001
65#define TIFM_IRQ_CARDMASK 0x00000100
66#define TIFM_IRQ_FIFOMASK 0x00010000
67#define TIFM_IRQ_SETALL 0xffffffff
68#define TIFM_IRQ_SETALLSOCK 0x0000000f
69
70#define TIFM_CTRL_LED 0x00000040
71#define TIFM_CTRL_FAST_CLK 0x00000100
72
73#define TIFM_SOCK_STATE_OCCUPIED 0x00000008
74#define TIFM_SOCK_STATE_POWERED 0x00000080
75
76#define TIFM_FIFO_ENABLE 0x00000001 /* Meaning of this constant is unverified */
77#define TIFM_FIFO_INT_SETALL 0x0000ffff
78#define TIFM_FIFO_INTMASK 0x00000005 /* Meaning of this constant is unverified */
79
80#define TIFM_DMA_RESET 0x00000002 /* Meaning of this constant is unverified */
81#define TIFM_DMA_TX 0x00008000 /* Meaning of this constant is unverified */
82#define TIFM_DMA_EN 0x00000001 /* Meaning of this constant is unverified */
83
84typedef enum {FM_NULL = 0, FM_XD = 0x01, FM_MS = 0x02, FM_SD = 0x03} tifm_media_id;
85
86struct tifm_driver;
87struct tifm_dev {
88 char __iomem *addr;
89 spinlock_t lock;
90 tifm_media_id media_id;
91 char wq_name[KOBJ_NAME_LEN];
92 struct workqueue_struct *wq;
93
94 unsigned int (*signal_irq)(struct tifm_dev *sock,
95 unsigned int sock_irq_status);
96
97 struct tifm_driver *drv;
98 struct device dev;
99};
100
101struct tifm_driver {
102 tifm_media_id *id_table;
103 int (*probe)(struct tifm_dev *dev);
104 void (*remove)(struct tifm_dev *dev);
105
106 struct device_driver driver;
107};
108
109struct tifm_adapter {
110 char __iomem *addr;
111 unsigned int irq_status;
112 unsigned int insert_mask;
113 unsigned int remove_mask;
114 spinlock_t lock;
115 unsigned int id;
116 unsigned int max_sockets;
117 char wq_name[KOBJ_NAME_LEN];
118 unsigned int inhibit_new_cards;
119 struct workqueue_struct *wq;
120 struct work_struct media_inserter;
121 struct work_struct media_remover;
122 struct tifm_dev **sockets;
123 struct class_device cdev;
124 struct device *dev;
125
126 void (*eject)(struct tifm_adapter *fm, struct tifm_dev *sock);
127};
128
129struct tifm_adapter *tifm_alloc_adapter(void);
130void tifm_free_device(struct device *dev);
131void tifm_free_adapter(struct tifm_adapter *fm);
132int tifm_add_adapter(struct tifm_adapter *fm);
133void tifm_remove_adapter(struct tifm_adapter *fm);
134struct tifm_dev *tifm_alloc_device(struct tifm_adapter *fm, unsigned int id);
135int tifm_register_driver(struct tifm_driver *drv);
136void tifm_unregister_driver(struct tifm_driver *drv);
137void tifm_eject(struct tifm_dev *sock);
138int tifm_map_sg(struct tifm_dev *sock, struct scatterlist *sg, int nents,
139 int direction);
140void tifm_unmap_sg(struct tifm_dev *sock, struct scatterlist *sg, int nents,
141 int direction);
142
143
144static inline void *tifm_get_drvdata(struct tifm_dev *dev)
145{
146 return dev_get_drvdata(&dev->dev);
147}
148
149static inline void tifm_set_drvdata(struct tifm_dev *dev, void *data)
150{
151 dev_set_drvdata(&dev->dev, data);
152}
153
154struct tifm_device_id {
155 tifm_media_id media_id;
156};
157
158#endif
diff --git a/include/linux/utsname.h b/include/linux/utsname.h
index 02e4b6972064..a4555fe3754c 100644
--- a/include/linux/utsname.h
+++ b/include/linux/utsname.h
@@ -1,11 +1,6 @@
1#ifndef _LINUX_UTSNAME_H 1#ifndef _LINUX_UTSNAME_H
2#define _LINUX_UTSNAME_H 2#define _LINUX_UTSNAME_H
3 3
4#include <linux/sched.h>
5#include <linux/kref.h>
6#include <linux/nsproxy.h>
7#include <asm/atomic.h>
8
9#define __OLD_UTS_LEN 8 4#define __OLD_UTS_LEN 8
10 5
11struct oldold_utsname { 6struct oldold_utsname {
@@ -35,6 +30,13 @@ struct new_utsname {
35 char domainname[65]; 30 char domainname[65];
36}; 31};
37 32
33#ifdef __KERNEL__
34
35#include <linux/sched.h>
36#include <linux/kref.h>
37#include <linux/nsproxy.h>
38#include <asm/atomic.h>
39
38struct uts_namespace { 40struct uts_namespace {
39 struct kref kref; 41 struct kref kref;
40 struct new_utsname name; 42 struct new_utsname name;
@@ -86,4 +88,7 @@ static inline struct new_utsname *init_utsname(void)
86} 88}
87 89
88extern struct rw_semaphore uts_sem; 90extern struct rw_semaphore uts_sem;
89#endif 91
92#endif /* __KERNEL__ */
93
94#endif /* _LINUX_UTSNAME_H */
diff --git a/include/linux/wavefront.h b/include/linux/wavefront.h
deleted file mode 100644
index 51ab3c933acd..000000000000
--- a/include/linux/wavefront.h
+++ /dev/null
@@ -1,675 +0,0 @@
1#ifndef __wavefront_h__
2#define __wavefront_h__
3
4/* WaveFront header file.
5 *
6 * Copyright (C) by Paul Barton-Davis 1998
7 *
8 * This program is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
9 * Version 2 (June 1991). See the "COPYING" file distributed with this software
10 * for more info.
11 */
12
13#if (!defined(__GNUC__) && !defined(__GNUG__))
14
15 You will not be able to compile this file correctly without gcc, because
16 it is necessary to pack the "wavefront_alias" structure to a size
17 of 22 bytes, corresponding to 16-bit alignment (as would have been
18 the case on the original platform, MS-DOS). If this is not done,
19 then WavePatch-format files cannot be read/written correctly.
20 The method used to do this here ("__attribute__((packed)") is
21 completely compiler dependent.
22
23 All other wavefront_* types end up aligned to 32 bit values and
24 still have the same (correct) size.
25
26#else
27
28 /* However, note that as of G++ 2.7.3.2, g++ was unable to
29 correctly parse *type* __attribute__ tags. It will do the
30 right thing if we use the "packed" attribute on each struct
31 member, which has the same semantics anyway.
32 */
33
34#endif /* __GNUC__ */
35
36/***************************** WARNING ********************************
37 PLEASE DO NOT MODIFY THIS FILE IN ANY WAY THAT AFFECTS ITS ABILITY TO
38 BE USED WITH EITHER C *OR* C++.
39 **********************************************************************/
40
41#ifndef NUM_MIDIKEYS
42#define NUM_MIDIKEYS 128
43#endif /* NUM_MIDIKEYS */
44
45#ifndef NUM_MIDICHANNELS
46#define NUM_MIDICHANNELS 16
47#endif /* NUM_MIDICHANNELS */
48
49/* These are very useful/important. the original wavefront interface
50 was developed on a 16 bit system, where sizeof(int) = 2
51 bytes. Defining things like this makes the code much more portable, and
52 easier to understand without having to toggle back and forth
53 between a 16-bit view of the world and a 32-bit one.
54 */
55
56typedef short INT16;
57typedef unsigned short UINT16;
58typedef int INT32;
59typedef unsigned int UINT32;
60typedef char CHAR8;
61typedef unsigned char UCHAR8;
62
63/* Pseudo-commands not part of the WaveFront command set.
64 These are used for various driver controls and direct
65 hardware control.
66 */
67
68#define WFC_DEBUG_DRIVER 0
69#define WFC_FX_IOCTL 1
70#define WFC_PATCH_STATUS 2
71#define WFC_PROGRAM_STATUS 3
72#define WFC_SAMPLE_STATUS 4
73#define WFC_DISABLE_INTERRUPTS 5
74#define WFC_ENABLE_INTERRUPTS 6
75#define WFC_INTERRUPT_STATUS 7
76#define WFC_ROMSAMPLES_RDONLY 8
77#define WFC_IDENTIFY_SLOT_TYPE 9
78
79/* Wavefront synth commands
80 */
81
82#define WFC_DOWNLOAD_SAMPLE 0x80
83#define WFC_DOWNLOAD_BLOCK 0x81
84#define WFC_DOWNLOAD_MULTISAMPLE 0x82
85#define WFC_DOWNLOAD_SAMPLE_ALIAS 0x83
86#define WFC_DELETE_SAMPLE 0x84
87#define WFC_REPORT_FREE_MEMORY 0x85
88#define WFC_DOWNLOAD_PATCH 0x86
89#define WFC_DOWNLOAD_PROGRAM 0x87
90#define WFC_SET_SYNTHVOL 0x89
91#define WFC_SET_NVOICES 0x8B
92#define WFC_DOWNLOAD_DRUM 0x90
93#define WFC_GET_SYNTHVOL 0x92
94#define WFC_GET_NVOICES 0x94
95#define WFC_DISABLE_CHANNEL 0x9A
96#define WFC_ENABLE_CHANNEL 0x9B
97#define WFC_MISYNTH_OFF 0x9D
98#define WFC_MISYNTH_ON 0x9E
99#define WFC_FIRMWARE_VERSION 0x9F
100#define WFC_GET_NSAMPLES 0xA0
101#define WFC_DISABLE_DRUM_PROGRAM 0xA2
102#define WFC_UPLOAD_PATCH 0xA3
103#define WFC_UPLOAD_PROGRAM 0xA4
104#define WFC_SET_TUNING 0xA6
105#define WFC_GET_TUNING 0xA7
106#define WFC_VMIDI_ON 0xA8
107#define WFC_VMIDI_OFF 0xA9
108#define WFC_MIDI_STATUS 0xAA
109#define WFC_GET_CHANNEL_STATUS 0xAB
110#define WFC_DOWNLOAD_SAMPLE_HEADER 0xAC
111#define WFC_UPLOAD_SAMPLE_HEADER 0xAD
112#define WFC_UPLOAD_MULTISAMPLE 0xAE
113#define WFC_UPLOAD_SAMPLE_ALIAS 0xAF
114#define WFC_IDENTIFY_SAMPLE_TYPE 0xB0
115#define WFC_DOWNLOAD_EDRUM_PROGRAM 0xB1
116#define WFC_UPLOAD_EDRUM_PROGRAM 0xB2
117#define WFC_SET_EDRUM_CHANNEL 0xB3
118#define WFC_INSTOUT_LEVELS 0xB4
119#define WFC_PEAKOUT_LEVELS 0xB5
120#define WFC_REPORT_CHANNEL_PROGRAMS 0xB6
121#define WFC_HARDWARE_VERSION 0xCF
122#define WFC_UPLOAD_SAMPLE_PARAMS 0xD7
123#define WFC_DOWNLOAD_OS 0xF1
124#define WFC_NOOP 0xFF
125
126#define WF_MAX_SAMPLE 512
127#define WF_MAX_PATCH 256
128#define WF_MAX_PROGRAM 128
129
130#define WF_SECTION_MAX 44 /* longest OS section length */
131
132/* # of bytes we send to the board when sending it various kinds of
133 substantive data, such as samples, patches and programs.
134*/
135
136#define WF_PROGRAM_BYTES 32
137#define WF_PATCH_BYTES 132
138#define WF_SAMPLE_BYTES 27
139#define WF_SAMPLE_HDR_BYTES 25
140#define WF_ALIAS_BYTES 25
141#define WF_DRUM_BYTES 9
142#define WF_MSAMPLE_BYTES 259 /* (MIDI_KEYS * 2) + 3 */
143
144#define WF_ACK 0x80
145#define WF_DMA_ACK 0x81
146
147/* OR-values for MIDI status bits */
148
149#define WF_MIDI_VIRTUAL_ENABLED 0x1
150#define WF_MIDI_VIRTUAL_IS_EXTERNAL 0x2
151#define WF_MIDI_IN_TO_SYNTH_DISABLED 0x4
152
153/* slot indexes for struct address_info: makes code a little more mnemonic */
154
155#define WF_SYNTH_SLOT 0
156#define WF_INTERNAL_MIDI_SLOT 1
157#define WF_EXTERNAL_MIDI_SLOT 2
158
159/* Magic MIDI bytes used to switch I/O streams on the ICS2115 MPU401
160 emulation. Note these NEVER show up in output from the device and
161 should NEVER be used in input unless Virtual MIDI mode has been
162 disabled. If they do show up as input, the results are unpredictable.
163*/
164
165#define WF_EXTERNAL_SWITCH 0xFD
166#define WF_INTERNAL_SWITCH 0xF9
167
168/* Debugging flags */
169
170#define WF_DEBUG_CMD 0x1
171#define WF_DEBUG_DATA 0x2
172#define WF_DEBUG_LOAD_PATCH 0x4
173#define WF_DEBUG_IO 0x8
174
175/* WavePatch file format stuff */
176
177#define WF_WAVEPATCH_VERSION 120; /* Current version number (1.2) */
178#define WF_MAX_COMMENT 64 /* Comment length */
179#define WF_NUM_LAYERS 4
180#define WF_NAME_LENGTH 32
181#define WF_SOURCE_LENGTH 260
182
183#define BankFileID "Bank"
184#define DrumkitFileID "DrumKit"
185#define ProgramFileID "Program"
186
187struct wf_envelope
188{
189 UCHAR8 attack_time:7;
190 UCHAR8 Unused1:1;
191
192 UCHAR8 decay1_time:7;
193 UCHAR8 Unused2:1;
194
195 UCHAR8 decay2_time:7;
196 UCHAR8 Unused3:1;
197
198 UCHAR8 sustain_time:7;
199 UCHAR8 Unused4:1;
200
201 UCHAR8 release_time:7;
202 UCHAR8 Unused5:1;
203
204 UCHAR8 release2_time:7;
205 UCHAR8 Unused6:1;
206
207 CHAR8 attack_level;
208 CHAR8 decay1_level;
209 CHAR8 decay2_level;
210 CHAR8 sustain_level;
211 CHAR8 release_level;
212
213 UCHAR8 attack_velocity:7;
214 UCHAR8 Unused7:1;
215
216 UCHAR8 volume_velocity:7;
217 UCHAR8 Unused8:1;
218
219 UCHAR8 keyboard_scaling:7;
220 UCHAR8 Unused9:1;
221};
222typedef struct wf_envelope wavefront_envelope;
223
224struct wf_lfo
225{
226 UCHAR8 sample_number;
227
228 UCHAR8 frequency:7;
229 UCHAR8 Unused1:1;
230
231 UCHAR8 am_src:4;
232 UCHAR8 fm_src:4;
233
234 CHAR8 fm_amount;
235 CHAR8 am_amount;
236 CHAR8 start_level;
237 CHAR8 end_level;
238
239 UCHAR8 ramp_delay:7;
240 UCHAR8 wave_restart:1; /* for LFO2 only */
241
242 UCHAR8 ramp_time:7;
243 UCHAR8 Unused2:1;
244};
245typedef struct wf_lfo wavefront_lfo;
246
247struct wf_patch
248{
249 INT16 frequency_bias; /* ** THIS IS IN MOTOROLA FORMAT!! ** */
250
251 UCHAR8 amplitude_bias:7;
252 UCHAR8 Unused1:1;
253
254 UCHAR8 portamento:7;
255 UCHAR8 Unused2:1;
256
257 UCHAR8 sample_number;
258
259 UCHAR8 pitch_bend:4;
260 UCHAR8 sample_msb:1;
261 UCHAR8 Unused3:3;
262
263 UCHAR8 mono:1;
264 UCHAR8 retrigger:1;
265 UCHAR8 nohold:1;
266 UCHAR8 restart:1;
267 UCHAR8 filterconfig:2; /* SDK says "not used" */
268 UCHAR8 reuse:1;
269 UCHAR8 reset_lfo:1;
270
271 UCHAR8 fm_src2:4;
272 UCHAR8 fm_src1:4;
273
274 CHAR8 fm_amount1;
275 CHAR8 fm_amount2;
276
277 UCHAR8 am_src:4;
278 UCHAR8 Unused4:4;
279
280 CHAR8 am_amount;
281
282 UCHAR8 fc1_mode:4;
283 UCHAR8 fc2_mode:4;
284
285 CHAR8 fc1_mod_amount;
286 CHAR8 fc1_keyboard_scaling;
287 CHAR8 fc1_bias;
288 CHAR8 fc2_mod_amount;
289 CHAR8 fc2_keyboard_scaling;
290 CHAR8 fc2_bias;
291
292 UCHAR8 randomizer:7;
293 UCHAR8 Unused5:1;
294
295 struct wf_envelope envelope1;
296 struct wf_envelope envelope2;
297 struct wf_lfo lfo1;
298 struct wf_lfo lfo2;
299};
300typedef struct wf_patch wavefront_patch;
301
302struct wf_layer
303{
304 UCHAR8 patch_number;
305
306 UCHAR8 mix_level:7;
307 UCHAR8 mute:1;
308
309 UCHAR8 split_point:7;
310 UCHAR8 play_below:1;
311
312 UCHAR8 pan_mod_src:2;
313 UCHAR8 pan_or_mod:1;
314 UCHAR8 pan:4;
315 UCHAR8 split_type:1;
316};
317typedef struct wf_layer wavefront_layer;
318
319struct wf_program
320{
321 struct wf_layer layer[WF_NUM_LAYERS];
322};
323typedef struct wf_program wavefront_program;
324
325struct wf_sample_offset
326{
327 INT32 Fraction:4;
328 INT32 Integer:20;
329 INT32 Unused:8;
330};
331typedef struct wf_sample_offset wavefront_sample_offset;
332
333/* Sample slot types */
334
335#define WF_ST_SAMPLE 0
336#define WF_ST_MULTISAMPLE 1
337#define WF_ST_ALIAS 2
338#define WF_ST_EMPTY 3
339
340/* pseudo's */
341
342#define WF_ST_DRUM 4
343#define WF_ST_PROGRAM 5
344#define WF_ST_PATCH 6
345#define WF_ST_SAMPLEHDR 7
346
347#define WF_ST_MASK 0xf
348
349/* Flags for slot status. These occupy the upper bits of the same byte
350 as a sample type.
351*/
352
353#define WF_SLOT_USED 0x80 /* XXX don't rely on this being accurate */
354#define WF_SLOT_FILLED 0x40
355#define WF_SLOT_ROM 0x20
356
357#define WF_SLOT_MASK 0xf0
358
359/* channel constants */
360
361#define WF_CH_MONO 0
362#define WF_CH_LEFT 1
363#define WF_CH_RIGHT 2
364
365/* Sample formats */
366
367#define LINEAR_16BIT 0
368#define WHITE_NOISE 1
369#define LINEAR_8BIT 2
370#define MULAW_8BIT 3
371
372#define WF_SAMPLE_IS_8BIT(smpl) ((smpl)->SampleResolution&2)
373
374
375/*
376
377 Because most/all of the sample data we pass in via pointers has
378 never been copied (just mmap-ed into user space straight from the
379 disk), it would be nice to allow handling of multi-channel sample
380 data without forcing user-level extraction of the relevant bytes.
381
382 So, we need a way of specifying which channel to use (the WaveFront
383 only handles mono samples in a given slot), and the only way to do
384 this without using some struct other than wavefront_sample as the
385 interface is the awful hack of using the unused bits in a
386 wavefront_sample:
387
388 Val Meaning
389 --- -------
390 0 no channel selection (use channel 1, sample is MONO)
391 1 use first channel, and skip one
392 2 use second channel, and skip one
393 3 use third channel, and skip two
394 4 use fourth channel, skip three
395 5 use fifth channel, skip four
396 6 use six channel, skip five
397
398
399 This can handle up to 4 channels, and anyone downloading >4 channels
400 of sample data just to select one of them needs to find some tools
401 like sox ...
402
403 NOTE: values 0, 1 and 2 correspond to WF_CH_* above. This is
404 important.
405
406*/
407
408#define WF_SET_CHANNEL(samp,chn) \
409 (samp)->Unused1 = chn & 0x1; \
410 (samp)->Unused2 = chn & 0x2; \
411 (samp)->Unused3 = chn & 0x4
412
413#define WF_GET_CHANNEL(samp) \
414 (((samp)->Unused3 << 2)|((samp)->Unused2<<1)|(samp)->Unused1)
415
416typedef struct wf_sample {
417 struct wf_sample_offset sampleStartOffset;
418 struct wf_sample_offset loopStartOffset;
419 struct wf_sample_offset loopEndOffset;
420 struct wf_sample_offset sampleEndOffset;
421 INT16 FrequencyBias;
422 UCHAR8 SampleResolution:2; /* sample_format */
423 UCHAR8 Unused1:1;
424 UCHAR8 Loop:1;
425 UCHAR8 Bidirectional:1;
426 UCHAR8 Unused2:1;
427 UCHAR8 Reverse:1;
428 UCHAR8 Unused3:1;
429} wavefront_sample;
430
431typedef struct wf_multisample {
432 INT16 NumberOfSamples; /* log2 of the number of samples */
433 INT16 SampleNumber[NUM_MIDIKEYS];
434} wavefront_multisample;
435
436typedef struct wf_alias {
437 INT16 OriginalSample;
438
439 struct wf_sample_offset sampleStartOffset;
440 struct wf_sample_offset loopStartOffset;
441 struct wf_sample_offset sampleEndOffset;
442 struct wf_sample_offset loopEndOffset;
443
444 INT16 FrequencyBias;
445
446 UCHAR8 SampleResolution:2;
447 UCHAR8 Unused1:1;
448 UCHAR8 Loop:1;
449 UCHAR8 Bidirectional:1;
450 UCHAR8 Unused2:1;
451 UCHAR8 Reverse:1;
452 UCHAR8 Unused3:1;
453
454 /* This structure is meant to be padded only to 16 bits on their
455 original. Of course, whoever wrote their documentation didn't
456 realize that sizeof(struct) can be >=
457 sum(sizeof(struct-fields)) and so thought that giving a C level
458 description of the structs used in WavePatch files was
459 sufficient. I suppose it was, as long as you remember the
460 standard 16->32 bit issues.
461 */
462
463 UCHAR8 sixteen_bit_padding;
464} __attribute__((packed)) wavefront_alias;
465
466typedef struct wf_drum {
467 UCHAR8 PatchNumber;
468 UCHAR8 MixLevel:7;
469 UCHAR8 Unmute:1;
470 UCHAR8 Group:4;
471 UCHAR8 Unused1:4;
472 UCHAR8 PanModSource:2;
473 UCHAR8 PanModulated:1;
474 UCHAR8 PanAmount:4;
475 UCHAR8 Unused2:1;
476} wavefront_drum;
477
478typedef struct wf_drumkit {
479 struct wf_drum drum[NUM_MIDIKEYS];
480} wavefront_drumkit;
481
482typedef struct wf_channel_programs {
483 UCHAR8 Program[NUM_MIDICHANNELS];
484} wavefront_channel_programs;
485
486/* How to get MIDI channel status from the data returned by
487 a WFC_GET_CHANNEL_STATUS command (a struct wf_channel_programs)
488*/
489
490#define WF_CHANNEL_STATUS(ch,wcp) (wcp)[(ch/7)] & (1<<((ch)%7))
491
492typedef union wf_any {
493 wavefront_sample s;
494 wavefront_multisample ms;
495 wavefront_alias a;
496 wavefront_program pr;
497 wavefront_patch p;
498 wavefront_drum d;
499} wavefront_any;
500
501/* Hannu Solvainen hoped that his "patch_info" struct in soundcard.h
502 might work for other wave-table based patch loading situations.
503 Alas, his fears were correct. The WaveFront doesn't even come with
504 just "patches", but several different kind of structures that
505 control the sound generation process.
506 */
507
508typedef struct wf_patch_info {
509
510 /* the first two fields are used by the OSS "patch loading" interface
511 only, and are unused by the current user-level library.
512 */
513
514 INT16 key; /* Use WAVEFRONT_PATCH here */
515 UINT16 devno; /* fill in when sending */
516 UCHAR8 subkey; /* WF_ST_{SAMPLE,ALIAS,etc.} */
517
518#define WAVEFRONT_FIND_FREE_SAMPLE_SLOT 999
519
520 UINT16 number; /* patch/sample/prog number */
521
522 UINT32 size; /* size of any data included in
523 one of the fields in `hdrptr', or
524 as `dataptr'.
525
526 NOTE: for actual samples, this is
527 the size of the *SELECTED CHANNEL*
528 even if more data is actually available.
529
530 So, a stereo sample (2 channels) of
531 6000 bytes total has `size' = 3000.
532
533 See the macros and comments for
534 WF_{GET,SET}_CHANNEL above.
535
536 */
537 wavefront_any __user *hdrptr; /* user-space ptr to hdr bytes */
538 UINT16 __user *dataptr; /* actual sample data */
539
540 wavefront_any hdr; /* kernel-space copy of hdr bytes */
541} wavefront_patch_info;
542
543/* The maximum number of bytes we will ever move to or from user space
544 in response to a WFC_* command. This obviously doesn't cover
545 actual sample data.
546*/
547
548#define WF_MAX_READ sizeof(wavefront_multisample)
549#define WF_MAX_WRITE sizeof(wavefront_multisample)
550
551/*
552 This allows us to execute any WF command except the download/upload
553 ones, which are handled differently due to copyin/copyout issues as
554 well as data-nybbling to/from the card.
555 */
556
557typedef struct wavefront_control {
558 int cmd; /* WFC_* */
559 char status; /* return status to user-space */
560 unsigned char rbuf[WF_MAX_READ]; /* bytes read from card */
561 unsigned char wbuf[WF_MAX_WRITE]; /* bytes written to card */
562} wavefront_control;
563
564#define WFCTL_WFCMD 0x1
565#define WFCTL_LOAD_SPP 0x2
566
567/* Modulator table */
568
569#define WF_MOD_LFO1 0
570#define WF_MOD_LFO2 1
571#define WF_MOD_ENV1 2
572#define WF_MOD_ENV2 3
573#define WF_MOD_KEYBOARD 4
574#define WF_MOD_LOGKEY 5
575#define WF_MOD_VELOCITY 6
576#define WF_MOD_LOGVEL 7
577#define WF_MOD_RANDOM 8
578#define WF_MOD_PRESSURE 9
579#define WF_MOD_MOD_WHEEL 10
580#define WF_MOD_1 WF_MOD_MOD_WHEEL
581#define WF_MOD_BREATH 11
582#define WF_MOD_2 WF_MOD_BREATH
583#define WF_MOD_FOOT 12
584#define WF_MOD_4 WF_MOD_FOOT
585#define WF_MOD_VOLUME 13
586#define WF_MOD_7 WF_MOD_VOLUME
587#define WF_MOD_PAN 14
588#define WF_MOD_10 WF_MOD_PAN
589#define WF_MOD_EXPR 15
590#define WF_MOD_11 WF_MOD_EXPR
591
592/* FX-related material */
593
594typedef struct wf_fx_info {
595 int request; /* see list below */
596 int data[4]; /* we don't need much */
597} wavefront_fx_info;
598
599/* support for each of these will be forthcoming once I or someone
600 else has figured out which of the addresses on page 6 and page 7 of
601 the YSS225 control each parameter. Incidentally, these come from
602 the Windows driver interface, but again, Turtle Beach didn't
603 document the API to use them.
604*/
605
606#define WFFX_SETOUTGAIN 0
607#define WFFX_SETSTEREOOUTGAIN 1
608#define WFFX_SETREVERBIN1GAIN 2
609#define WFFX_SETREVERBIN2GAIN 3
610#define WFFX_SETREVERBIN3GAIN 4
611#define WFFX_SETCHORUSINPORT 5
612#define WFFX_SETREVERBIN1PORT 6
613#define WFFX_SETREVERBIN2PORT 7
614#define WFFX_SETREVERBIN3PORT 8
615#define WFFX_SETEFFECTPORT 9
616#define WFFX_SETAUXPORT 10
617#define WFFX_SETREVERBTYPE 11
618#define WFFX_SETREVERBDELAY 12
619#define WFFX_SETCHORUSLFO 13
620#define WFFX_SETCHORUSPMD 14
621#define WFFX_SETCHORUSAMD 15
622#define WFFX_SETEFFECT 16
623#define WFFX_SETBASEALL 17
624#define WFFX_SETREVERBALL 18
625#define WFFX_SETCHORUSALL 20
626#define WFFX_SETREVERBDEF 22
627#define WFFX_SETCHORUSDEF 23
628#define WFFX_DELAYSETINGAIN 24
629#define WFFX_DELAYSETFBGAIN 25
630#define WFFX_DELAYSETFBLPF 26
631#define WFFX_DELAYSETGAIN 27
632#define WFFX_DELAYSETTIME 28
633#define WFFX_DELAYSETFBTIME 29
634#define WFFX_DELAYSETALL 30
635#define WFFX_DELAYSETDEF 32
636#define WFFX_SDELAYSETINGAIN 33
637#define WFFX_SDELAYSETFBGAIN 34
638#define WFFX_SDELAYSETFBLPF 35
639#define WFFX_SDELAYSETGAIN 36
640#define WFFX_SDELAYSETTIME 37
641#define WFFX_SDELAYSETFBTIME 38
642#define WFFX_SDELAYSETALL 39
643#define WFFX_SDELAYSETDEF 41
644#define WFFX_DEQSETINGAIN 42
645#define WFFX_DEQSETFILTER 43
646#define WFFX_DEQSETALL 44
647#define WFFX_DEQSETDEF 46
648#define WFFX_MUTE 47
649#define WFFX_FLANGESETBALANCE 48
650#define WFFX_FLANGESETDELAY 49
651#define WFFX_FLANGESETDWFFX_TH 50
652#define WFFX_FLANGESETFBGAIN 51
653#define WFFX_FLANGESETINGAIN 52
654#define WFFX_FLANGESETLFO 53
655#define WFFX_FLANGESETALL 54
656#define WFFX_FLANGESETDEF 56
657#define WFFX_PITCHSETSHIFT 57
658#define WFFX_PITCHSETBALANCE 58
659#define WFFX_PITCHSETALL 59
660#define WFFX_PITCHSETDEF 61
661#define WFFX_SRSSETINGAIN 62
662#define WFFX_SRSSETSPACE 63
663#define WFFX_SRSSETCENTER 64
664#define WFFX_SRSSETGAIN 65
665#define WFFX_SRSSETMODE 66
666#define WFFX_SRSSETDEF 68
667
668/* Allow direct user-space control over FX memory/coefficient data.
669 In theory this could be used to download the FX microprogram,
670 but it would be a little slower, and involve some weird code.
671 */
672
673#define WFFX_MEMSET 69
674
675#endif /* __wavefront_h__ */
diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h
index 430afd058269..8ae7f744917b 100644
--- a/include/linux/xfrm.h
+++ b/include/linux/xfrm.h
@@ -129,7 +129,8 @@ enum
129#define XFRM_MODE_TUNNEL 1 129#define XFRM_MODE_TUNNEL 1
130#define XFRM_MODE_ROUTEOPTIMIZATION 2 130#define XFRM_MODE_ROUTEOPTIMIZATION 2
131#define XFRM_MODE_IN_TRIGGER 3 131#define XFRM_MODE_IN_TRIGGER 3
132#define XFRM_MODE_MAX 4 132#define XFRM_MODE_BEET 4
133#define XFRM_MODE_MAX 5
133 134
134/* Netlink configuration messages. */ 135/* Netlink configuration messages. */
135enum { 136enum {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-06 09:58:00 -0500