5 files changed, 67 insertions, 3 deletions

diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index b9c3299c6a55..31ebb59cbd2f 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -517,6 +517,7 @@ struct kvm_assigned_dev_kernel {
         struct kvm *kvm;
         spinlock_t intx_lock;
         char irq_name[32];
+        struct pci_saved_state *pci_saved_state;
 };
 
 struct kvm_irq_mask_notifier {
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
index 67cb3ae38016..7cea7b6c1413 100644
--- a/include/linux/pci-aspm.h
+++ b/include/linux/pci-aspm.h
@@ -28,6 +28,7 @@ extern void pcie_aspm_exit_link_state(struct pci_dev *pdev);
 extern void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 extern void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 extern void pci_disable_link_state(struct pci_dev *pdev, int state);
+extern void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
 extern void pcie_clear_aspm(void);
 extern void pcie_no_aspm(void);
 #else
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 96f70d7e058d..4604d1d5514d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -214,12 +214,17 @@ enum pci_bus_speed {
         PCI_SPEED_UNKNOWN               = 0xff,
 };
 
-struct pci_cap_saved_state {
-        struct hlist_node next;
+struct pci_cap_saved_data {
         char cap_nr;
+        unsigned int size;
         u32 data[0];
 };
 
+struct pci_cap_saved_state {
+        struct hlist_node next;
+        struct pci_cap_saved_data cap;
+};
+
 struct pcie_link_state;
 struct pci_vpd;
 struct pci_sriov;
@@ -366,7 +371,7 @@ static inline struct pci_cap_saved_state *pci_find_saved_cap(
         struct hlist_node *pos;
 
         hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
-                if (tmp->cap_nr == cap)
+                if (tmp->cap.cap_nr == cap)
                         return tmp;
         }
         return NULL;
@@ -807,6 +812,10 @@ size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
 /* Power management related routines */
 int pci_save_state(struct pci_dev *dev);
 void pci_restore_state(struct pci_dev *dev);
+struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
+int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
+int pci_load_and_free_saved_state(struct pci_dev *dev,
+                                  struct pci_saved_state **state);
 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
@@ -828,6 +837,23 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
         return __pci_enable_wake(dev, state, false, enable);
 }
 
+#define PCI_EXP_IDO_REQUEST     (1<<0)
+#define PCI_EXP_IDO_COMPLETION  (1<<1)
+void pci_enable_ido(struct pci_dev *dev, unsigned long type);
+void pci_disable_ido(struct pci_dev *dev, unsigned long type);
+
+enum pci_obff_signal_type {
+        PCI_EXP_OBFF_SIGNAL_L0,
+        PCI_EXP_OBFF_SIGNAL_ALWAYS,
+};
+int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
+void pci_disable_obff(struct pci_dev *dev);
+
+bool pci_ltr_supported(struct pci_dev *dev);
+int pci_enable_ltr(struct pci_dev *dev);
+void pci_disable_ltr(struct pci_dev *dev);
+int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
+
 /* For use by arch with custom probe code */
 void set_pcie_port_type(struct pci_dev *pdev);
 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
@@ -1207,6 +1233,23 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
         return 0;
 }
 
+static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
+{
+}
+
+static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
+{
+}
+
+static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
+{
+        return 0;
+}
+
+static inline void pci_disable_obff(struct pci_dev *dev)
+{
+}
+
 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
 {
         return -EIO;
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 8652a4fa3fe2..24787b751286 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2483,6 +2483,8 @@
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0      0x1d40
 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1      0x1d41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN        0x1e40
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX        0x1e5f
 #define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN    0x2310
 #define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX    0x231f
 #define PCI_DEVICE_ID_INTEL_82801AA_0   0x2410
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index be01380f798a..e8840964aca1 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -508,8 +508,18 @@
 #define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */
 #define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
 #define  PCI_EXP_DEVCAP2_ARI    0x20    /* Alternative Routing-ID */
+#define  PCI_EXP_DEVCAP2_LTR    0x800   /* Latency tolerance reporting */
+#define  PCI_EXP_OBFF_MASK      0xc0000 /* OBFF support mechanism */
+#define  PCI_EXP_OBFF_MSG       0x40000 /* New message signaling */
+#define  PCI_EXP_OBFF_WAKE      0x80000 /* Re-use WAKE# for OBFF */
 #define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
 #define  PCI_EXP_DEVCTL2_ARI    0x20    /* Alternative Routing-ID */
+#define  PCI_EXP_IDO_REQ_EN     0x100   /* ID-based ordering request enable */
+#define  PCI_EXP_IDO_CMP_EN     0x200   /* ID-based ordering completion enable */
+#define  PCI_EXP_LTR_EN         0x400   /* Latency tolerance reporting */
+#define  PCI_EXP_OBFF_MSGA_EN   0x2000  /* OBFF enable with Message type A */
+#define  PCI_EXP_OBFF_MSGB_EN   0x4000  /* OBFF enable with Message type B */
+#define  PCI_EXP_OBFF_WAKE_EN   0x6000  /* OBFF using WAKE# signaling */
 #define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
 #define PCI_EXP_SLTCTL2         56      /* Slot Control 2 */
 
@@ -527,6 +537,7 @@
 #define PCI_EXT_CAP_ID_ARI      14
 #define PCI_EXT_CAP_ID_ATS      15
 #define PCI_EXT_CAP_ID_SRIOV    16
+#define PCI_EXT_CAP_ID_LTR      24
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
@@ -683,6 +694,12 @@
 #define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
 #define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
 
+#define PCI_LTR_MAX_SNOOP_LAT   0x4
+#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
+#define  PCI_LTR_VALUE_MASK     0x000003ff
+#define  PCI_LTR_SCALE_MASK     0x00001c00
+#define  PCI_LTR_SCALE_SHIFT    10
+
 /* Access Control Service */
 #define PCI_ACS_CAP             0x04    /* ACS Capability Register */
 #define  PCI_ACS_SV             0x01    /* Source Validation */