aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-aaec2000/uncompress.h23
-rw-r--r--include/asm-arm/arch-at91rm9200/uncompress.h23
-rw-r--r--include/asm-arm/arch-cl7500/uncompress.h18
-rw-r--r--include/asm-arm/arch-clps711x/uncompress.h21
-rw-r--r--include/asm-arm/arch-ebsa110/uncompress.h47
-rw-r--r--include/asm-arm/arch-ebsa285/uncompress.h16
-rw-r--r--include/asm-arm/arch-ep93xx/uncompress.h50
-rw-r--r--include/asm-arm/arch-h720x/uncompress.h24
-rw-r--r--include/asm-arm/arch-imx/uncompress.h21
-rw-r--r--include/asm-arm/arch-integrator/uncompress.h21
-rw-r--r--include/asm-arm/arch-iop3xx/uncompress.h16
-rw-r--r--include/asm-arm/arch-ixp2000/uncompress.h15
-rw-r--r--include/asm-arm/arch-ixp23xx/debug-macro.S23
-rw-r--r--include/asm-arm/arch-ixp23xx/dma.h3
-rw-r--r--include/asm-arm/arch-ixp23xx/entry-macro.S31
-rw-r--r--include/asm-arm/arch-ixp23xx/hardware.h37
-rw-r--r--include/asm-arm/arch-ixp23xx/io.h54
-rw-r--r--include/asm-arm/arch-ixp23xx/irqs.h223
-rw-r--r--include/asm-arm/arch-ixp23xx/ixdp2351.h89
-rw-r--r--include/asm-arm/arch-ixp23xx/ixp23xx.h306
-rw-r--r--include/asm-arm/arch-ixp23xx/memory.h46
-rw-r--r--include/asm-arm/arch-ixp23xx/platform.h31
-rw-r--r--include/asm-arm/arch-ixp23xx/system.h33
-rw-r--r--include/asm-arm/arch-ixp23xx/time.h3
-rw-r--r--include/asm-arm/arch-ixp23xx/timex.h7
-rw-r--r--include/asm-arm/arch-ixp23xx/uncompress.h45
-rw-r--r--include/asm-arm/arch-ixp23xx/vmalloc.h10
-rw-r--r--include/asm-arm/arch-ixp4xx/uncompress.h18
-rw-r--r--include/asm-arm/arch-l7200/uncompress.h15
-rw-r--r--include/asm-arm/arch-lh7a40x/uncompress.h11
-rw-r--r--include/asm-arm/arch-omap/uncompress.h20
-rw-r--r--include/asm-arm/arch-pxa/irqs.h6
-rw-r--r--include/asm-arm/arch-pxa/lpd270.h38
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h13
-rw-r--r--include/asm-arm/arch-realview/uncompress.h20
-rw-r--r--include/asm-arm/arch-rpc/uncompress.h27
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h15
-rw-r--r--include/asm-arm/arch-sa1100/uncompress.h21
-rw-r--r--include/asm-arm/arch-shark/uncompress.h13
-rw-r--r--include/asm-arm/arch-versatile/uncompress.h20
-rw-r--r--include/asm-arm/cacheflush.h8
-rw-r--r--include/asm-arm/domain.h18
-rw-r--r--include/asm-arm/page.h9
-rw-r--r--include/asm-arm/proc-fns.h8
-rw-r--r--include/asm-arm/system.h19
45 files changed, 1255 insertions, 280 deletions
diff --git a/include/asm-arm/arch-aaec2000/uncompress.h b/include/asm-arm/arch-aaec2000/uncompress.h
index fff0c94b75c4..300f4bf3bc74 100644
--- a/include/asm-arm/arch-aaec2000/uncompress.h
+++ b/include/asm-arm/arch-aaec2000/uncompress.h
@@ -15,7 +15,7 @@
15 15
16#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) 16#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
17 17
18static void putstr( const char *s ) 18static void putc(int c)
19{ 19{
20 unsigned long serial_port; 20 unsigned long serial_port;
21 do { 21 do {
@@ -28,17 +28,16 @@ static void putstr( const char *s )
28 return; 28 return;
29 } while (0); 29 } while (0);
30 30
31 for (; *s; s++) { 31 /* wait for space in the UART's transmitter */
32 /* wait for space in the UART's transmitter */ 32 while ((UART(UART_SR) & UART_SR_TxFF))
33 while ((UART(UART_SR) & UART_SR_TxFF)); 33 barrier();
34 /* send the character out. */ 34
35 UART(UART_DR) = *s; 35 /* send the character out. */
36 /* if a LF, also do CR... */ 36 UART(UART_DR) = c;
37 if (*s == 10) { 37}
38 while ((UART(UART_SR) & UART_SR_TxFF)); 38
39 UART(UART_DR) = 13; 39static inline void flush(void)
40 } 40{
41 }
42} 41}
43 42
44#define arch_decomp_setup() 43#define arch_decomp_setup()
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
index b30dd5520713..7b38497c24b5 100644
--- a/include/asm-arm/arch-at91rm9200/uncompress.h
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -31,21 +31,22 @@
31 * 31 *
32 * This does not append a newline 32 * This does not append a newline
33 */ 33 */
34static void putstr(const char *s) 34static void putc(int c)
35{
36 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
37
38 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY))
39 barrier();
40 __raw_writel(c, sys + AT91_DBGU_THR);
41}
42
43static inline void flush(void)
35{ 44{
36 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 45 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
37 46
38 while (*s) {
39 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
40 __raw_writel(*s, sys + AT91_DBGU_THR);
41 if (*s == '\n') {
42 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
43 __raw_writel('\r', sys + AT91_DBGU_THR);
44 }
45 s++;
46 }
47 /* wait for transmission to complete */ 47 /* wait for transmission to complete */
48 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) { barrier(); } 48 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY))
49 barrier();
49} 50}
50 51
51#define arch_decomp_setup() 52#define arch_decomp_setup()
diff --git a/include/asm-arm/arch-cl7500/uncompress.h b/include/asm-arm/arch-cl7500/uncompress.h
index 68601b3e3b95..c437e0c88c3f 100644
--- a/include/asm-arm/arch-cl7500/uncompress.h
+++ b/include/asm-arm/arch-cl7500/uncompress.h
@@ -3,27 +3,19 @@
3 * 3 *
4 * Copyright (C) 1999, 2000 Nexus Electronics Ltd. 4 * Copyright (C) 1999, 2000 Nexus Electronics Ltd.
5 */ 5 */
6
7#define BASE 0x03010000 6#define BASE 0x03010000
8#define SERBASE (BASE + (0x2f8 << 2)) 7#define SERBASE (BASE + (0x2f8 << 2))
9 8
10static __inline__ void putc(char c) 9static inline void putc(char c)
11{ 10{
12 while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20)); 11 while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20))
12 barrier();
13
13 *((volatile unsigned int *)(SERBASE)) = c; 14 *((volatile unsigned int *)(SERBASE)) = c;
14} 15}
15 16
16/* 17static inline void flush(void)
17 * This does not append a newline
18 */
19static void putstr(const char *s)
20{ 18{
21 while (*s) {
22 putc(*s);
23 if (*s == '\n')
24 putc('\r');
25 s++;
26 }
27} 19}
28 20
29static __inline__ void arch_decomp_setup(void) 21static __inline__ void arch_decomp_setup(void)
diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h
index 9fc4bcfa1681..07157b7e4b20 100644
--- a/include/asm-arm/arch-clps711x/uncompress.h
+++ b/include/asm-arm/arch-clps711x/uncompress.h
@@ -25,7 +25,6 @@
25#undef CLPS7111_BASE 25#undef CLPS7111_BASE
26#define CLPS7111_BASE CLPS7111_PHYS_BASE 26#define CLPS7111_BASE CLPS7111_PHYS_BASE
27 27
28#define barrier() __asm__ __volatile__("": : :"memory")
29#define __raw_readl(p) (*(unsigned long *)(p)) 28#define __raw_readl(p) (*(unsigned long *)(p))
30#define __raw_writel(v,p) (*(unsigned long *)(p) = (v)) 29#define __raw_writel(v,p) (*(unsigned long *)(p) = (v))
31 30
@@ -40,21 +39,15 @@
40/* 39/*
41 * This does not append a newline 40 * This does not append a newline
42 */ 41 */
43static void putstr(const char *s) 42static inline void putc(int c)
44{ 43{
45 char c; 44 while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
46 45 barrier();
47 while ((c = *s++) != '\0') { 46 clps_writel(c, UARTDRx);
48 while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) 47}
49 barrier();
50 clps_writel(c, UARTDRx);
51 48
52 if (c == '\n') { 49static inline void flush(void)
53 while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) 50{
54 barrier();
55 clps_writel('\r', UARTDRx);
56 }
57 }
58 while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) 51 while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
59 barrier(); 52 barrier();
60} 53}
diff --git a/include/asm-arm/arch-ebsa110/uncompress.h b/include/asm-arm/arch-ebsa110/uncompress.h
index eee95581a923..66b19c7fd908 100644
--- a/include/asm-arm/arch-ebsa110/uncompress.h
+++ b/include/asm-arm/arch-ebsa110/uncompress.h
@@ -8,33 +8,34 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <linux/serial_reg.h>
12
13#define SERIAL_BASE ((unsigned char *)0xfe000be0)
14
11/* 15/*
12 * This does not append a newline 16 * This does not append a newline
13 */ 17 */
14static void putstr(const char *s) 18static inline void putc(int c)
19{
20 unsigned char v, *base = SERIAL_BASE;
21
22 do {
23 v = base[UART_LSR << 2];
24 barrier();
25 } while (!(v & UART_LSR_THRE));
26
27 base[UART_TX << 2] = c;
28}
29
30static inline void flush(void)
15{ 31{
16 unsigned long tmp1, tmp2; 32 unsigned char v, *base = SERIAL_BASE;
17 __asm__ __volatile__( 33
18 "ldrb %0, [%2], #1\n" 34 do {
19" teq %0, #0\n" 35 v = base[UART_LSR << 2];
20" beq 3f\n" 36 barrier();
21"1: strb %0, [%3]\n" 37 } while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) !=
22"2: ldrb %1, [%3, #0x14]\n" 38 (UART_LSR_TEMT|UART_LSR_THRE));
23" and %1, %1, #0x60\n"
24" teq %1, #0x60\n"
25" bne 2b\n"
26" teq %0, #'\n'\n"
27" moveq %0, #'\r'\n"
28" beq 1b\n"
29" ldrb %0, [%2], #1\n"
30" teq %0, #0\n"
31" bne 1b\n"
32"3: ldrb %1, [%3, #0x14]\n"
33" and %1, %1, #0x60\n"
34" teq %1, #0x60\n"
35" bne 3b"
36 : "=&r" (tmp1), "=&r" (tmp2)
37 : "r" (s), "r" (0xf0000be0) : "cc");
38} 39}
39 40
40/* 41/*
diff --git a/include/asm-arm/arch-ebsa285/uncompress.h b/include/asm-arm/arch-ebsa285/uncompress.h
index c2fd84e2d90e..86142c882b3a 100644
--- a/include/asm-arm/arch-ebsa285/uncompress.h
+++ b/include/asm-arm/arch-ebsa285/uncompress.h
@@ -15,10 +15,11 @@
15#define DC21285_BASE ((volatile unsigned int *)0x42000160) 15#define DC21285_BASE ((volatile unsigned int *)0x42000160)
16#define SER0_BASE ((volatile unsigned char *)0x7c0003f8) 16#define SER0_BASE ((volatile unsigned char *)0x7c0003f8)
17 17
18static __inline__ void putc(char c) 18static inline void putc(char c)
19{ 19{
20 if (machine_is_netwinder()) { 20 if (machine_is_netwinder()) {
21 while ((SER0_BASE[5] & 0x60) != 0x60); 21 while ((SER0_BASE[5] & 0x60) != 0x60)
22 barrier();
22 SER0_BASE[0] = c; 23 SER0_BASE[0] = c;
23 } else { 24 } else {
24 while (DC21285_BASE[6] & 8); 25 while (DC21285_BASE[6] & 8);
@@ -26,17 +27,8 @@ static __inline__ void putc(char c)
26 } 27 }
27} 28}
28 29
29/* 30static inline void flush(void)
30 * This does not append a newline
31 */
32static void putstr(const char *s)
33{ 31{
34 while (*s) {
35 putc(*s);
36 if (*s == '\n')
37 putc('\r');
38 s++;
39 }
40} 32}
41 33
42/* 34/*
diff --git a/include/asm-arm/arch-ep93xx/uncompress.h b/include/asm-arm/arch-ep93xx/uncompress.h
index 4410d217077e..c15274c85d5d 100644
--- a/include/asm-arm/arch-ep93xx/uncompress.h
+++ b/include/asm-arm/arch-ep93xx/uncompress.h
@@ -16,17 +16,27 @@ static unsigned char __raw_readb(unsigned int ptr)
16 return *((volatile unsigned char *)ptr); 16 return *((volatile unsigned char *)ptr);
17} 17}
18 18
19static unsigned int __raw_readl(unsigned int ptr)
20{
21 return *((volatile unsigned int *)ptr);
22}
23
19static void __raw_writeb(unsigned char value, unsigned int ptr) 24static void __raw_writeb(unsigned char value, unsigned int ptr)
20{ 25{
21 *((volatile unsigned char *)ptr) = value; 26 *((volatile unsigned char *)ptr) = value;
22} 27}
23 28
29static void __raw_writel(unsigned int value, unsigned int ptr)
30{
31 *((volatile unsigned int *)ptr) = value;
32}
33
24 34
25#define PHYS_UART1_DATA 0x808c0000 35#define PHYS_UART1_DATA 0x808c0000
26#define PHYS_UART1_FLAG 0x808c0018 36#define PHYS_UART1_FLAG 0x808c0018
27#define UART1_FLAG_TXFF 0x20 37#define UART1_FLAG_TXFF 0x20
28 38
29static __inline__ void putc(char c) 39static inline void putc(int c)
30{ 40{
31 int i; 41 int i;
32 42
@@ -39,15 +49,37 @@ static __inline__ void putc(char c)
39 __raw_writeb(c, PHYS_UART1_DATA); 49 __raw_writeb(c, PHYS_UART1_DATA);
40} 50}
41 51
42static void putstr(const char *s) 52static inline void flush(void)
43{ 53{
44 while (*s) {
45 putc(*s);
46 if (*s == '\n')
47 putc('\r');
48 s++;
49 }
50} 54}
51 55
52#define arch_decomp_setup() 56
57/*
58 * Some bootloaders don't turn off DMA from the ethernet MAC before
59 * jumping to linux, which means that we might end up with bits of RX
60 * status and packet data scribbled over the uncompressed kernel image.
61 * Work around this by resetting the ethernet MAC before we uncompress.
62 */
63#define PHYS_ETH_SELF_CTL 0x80010020
64#define ETH_SELF_CTL_RESET 0x00000001
65
66static void ethernet_reset(void)
67{
68 unsigned int v;
69
70 /* Reset the ethernet MAC. */
71 v = __raw_readl(PHYS_ETH_SELF_CTL);
72 __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
73
74 /* Wait for reset to finish. */
75 while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
76 ;
77}
78
79
80static void arch_decomp_setup(void)
81{
82 ethernet_reset();
83}
84
53#define arch_decomp_wdog() 85#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-h720x/uncompress.h b/include/asm-arm/arch-h720x/uncompress.h
index 9535764bcc71..18c69e0f3585 100644
--- a/include/asm-arm/arch-h720x/uncompress.h
+++ b/include/asm-arm/arch-h720x/uncompress.h
@@ -12,22 +12,20 @@
12#define LSR 0x14 12#define LSR 0x14
13#define TEMPTY 0x40 13#define TEMPTY 0x40
14 14
15static void putstr(const char *s) 15static inline void putc(int c)
16{ 16{
17 char c;
18 volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000); 17 volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
19 18
20 while ( (c = *s++) != '\0') { 19 /* wait until transmit buffer is empty */
21 /* wait until transmit buffer is empty */ 20 while((p[LSR] & TEMPTY) == 0x0)
22 while((p[LSR] & TEMPTY) == 0x0); 21 barrier();
23 /* write next character */ 22
24 *p = c; 23 /* write next character */
25 24 *p = c;
26 if(c == '\n') { 25}
27 while((p[LSR] & TEMPTY) == 0x0); 26
28 *p = '\r'; 27static inline void flush(void)
29 } 28{
30 }
31} 29}
32 30
33/* 31/*
diff --git a/include/asm-arm/arch-imx/uncompress.h b/include/asm-arm/arch-imx/uncompress.h
index 096077f2750b..da333f69136f 100644
--- a/include/asm-arm/arch-imx/uncompress.h
+++ b/include/asm-arm/arch-imx/uncompress.h
@@ -39,8 +39,7 @@
39 * 39 *
40 * This does not append a newline 40 * This does not append a newline
41 */ 41 */
42static void 42static void putc(int c)
43putstr(const char *s)
44{ 43{
45 unsigned long serial_port; 44 unsigned long serial_port;
46 45
@@ -54,20 +53,14 @@ putstr(const char *s)
54 return; 53 return;
55 } while(0); 54 } while(0);
56 55
57 while (*s) { 56 while (!(UART(USR2) & USR2_TXFE))
58 while ( !(UART(USR2) & USR2_TXFE) ) 57 barrier();
59 barrier();
60 58
61 UART(TXR) = *s; 59 UART(TXR) = c;
62 60}
63 if (*s == '\n') {
64 while ( !(UART(USR2) & USR2_TXFE) )
65 barrier();
66 61
67 UART(TXR) = '\r'; 62static inline void flush(void)
68 } 63{
69 s++;
70 }
71} 64}
72 65
73/* 66/*
diff --git a/include/asm-arm/arch-integrator/uncompress.h b/include/asm-arm/arch-integrator/uncompress.h
index 3957402741d3..f61825c4d901 100644
--- a/include/asm-arm/arch-integrator/uncompress.h
+++ b/include/asm-arm/arch-integrator/uncompress.h
@@ -28,21 +28,18 @@
28/* 28/*
29 * This does not append a newline 29 * This does not append a newline
30 */ 30 */
31static void putstr(const char *s) 31static void putc(int c)
32{ 32{
33 while (*s) { 33 while (AMBA_UART_FR & (1 << 5))
34 while (AMBA_UART_FR & (1 << 5)); 34 barrier();
35 35
36 AMBA_UART_DR = *s; 36 AMBA_UART_DR = c;
37 37}
38 if (*s == '\n') {
39 while (AMBA_UART_FR & (1 << 5));
40 38
41 AMBA_UART_DR = '\r'; 39static inline void flush(void)
42 } 40{
43 s++; 41 while (AMBA_UART_FR & (1 << 3))
44 } 42 barrier();
45 while (AMBA_UART_FR & (1 << 3));
46} 43}
47 44
48/* 45/*
diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h
index 82b88762c3cc..c98eb6254b1f 100644
--- a/include/asm-arm/arch-iop3xx/uncompress.h
+++ b/include/asm-arm/arch-iop3xx/uncompress.h
@@ -19,23 +19,15 @@ static volatile UTYPE uart_base;
19 19
20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) 20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
21 21
22static __inline__ void putc(char c) 22static inline void putc(char c)
23{ 23{
24 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE); 24 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
25 barrier();
25 *uart_base = c; 26 *uart_base = c;
26} 27}
27 28
28/* 29static inline void flush(void)
29 * This does not append a newline
30 */
31static void putstr(const char *s)
32{ 30{
33 while (*s) {
34 putc(*s);
35 if (*s == '\n')
36 putc('\r');
37 s++;
38 }
39} 31}
40 32
41static __inline__ void __arch_decomp_setup(unsigned long arch_id) 33static __inline__ void __arch_decomp_setup(unsigned long arch_id)
diff --git a/include/asm-arm/arch-ixp2000/uncompress.h b/include/asm-arm/arch-ixp2000/uncompress.h
index 3d3d5b2ed6e9..f66b408f363e 100644
--- a/include/asm-arm/arch-ixp2000/uncompress.h
+++ b/include/asm-arm/arch-ixp2000/uncompress.h
@@ -29,23 +29,18 @@
29#define UARTSR PHYS(0x14) /* Status reg */ 29#define UARTSR PHYS(0x14) /* Status reg */
30 30
31 31
32static __inline__ void putc(char c) 32static inline void putc(int c)
33{ 33{
34 int j = 0x1000; 34 int j = 0x1000;
35 35
36 while (--j && !(*UARTSR & UART_LSR_THRE)); 36 while (--j && !(*UARTSR & UART_LSR_THRE))
37 barrier();
38
37 *UARTDR = c; 39 *UARTDR = c;
38} 40}
39 41
40static void putstr(const char *s) 42static inline void flush(void)
41{ 43{
42 while (*s)
43 {
44 putc(*s);
45 if (*s == '\n')
46 putc('\r');
47 s++;
48 }
49} 44}
50 45
51#define arch_decomp_setup() 46#define arch_decomp_setup()
diff --git a/include/asm-arm/arch-ixp23xx/debug-macro.S b/include/asm-arm/arch-ixp23xx/debug-macro.S
new file mode 100644
index 000000000000..eb99fd69fd24
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/debug-macro.S
@@ -0,0 +1,23 @@
1/*
2 * include/asm-arm/arch-ixp23xx/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <asm/arch/ixp23xx.h>
14
15 .macro addruart,rx
16 mrc p15, 0, \rx, c1, c0
17 tst \rx, #1 @ mmu enabled?
18 ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical
19 ldrne \rx, =IXP23XX_PERIPHERAL_VIRT @ virtual
20 .endm
21
22#define UART_SHIFT 2
23#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ixp23xx/dma.h b/include/asm-arm/arch-ixp23xx/dma.h
new file mode 100644
index 000000000000..2f4335e3b836
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/dma.h
@@ -0,0 +1,3 @@
1/*
2 * include/asm-arm/arch-ixp23xx/dma.h
3 */
diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S
new file mode 100644
index 000000000000..0ef4e6016ac4
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/entry-macro.S
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-ixp23xx/entry-macro.S
3 */
4
5 .macro disable_fiq
6 .endm
7
8 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
9 ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
10 ldr \irqnr, [\irqnr] @ get interrupt number
11 cmp \irqnr, #0x0 @ suprious interrupt ?
12 movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits
13 subne \irqnr, \irqnr, #1 @ convert to 0 based
14
15#if 0
16 cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
17 bne 1001f
18 mov \irqnr, #IRQ_IXP23XX_INTA
19
20 ldr \irqnr, =0xf5000030
21
22 mov \tmp, #(1<<26)
23 tst \irqnr, \tmp
24 movne \irqnr, #IRQ_IXP23XX_INTB
25
26 mov \tmp, #(1<<27)
27 tst \irqnr, \tmp
28 movne \irqnr, #IRQ_IXP23XX_INTA
291001:
30#endif
31 .endm
diff --git a/include/asm-arm/arch-ixp23xx/hardware.h b/include/asm-arm/arch-ixp23xx/hardware.h
new file mode 100644
index 000000000000..c0010d21a684
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/hardware.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-ixp23xx/hardware.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 * Copyricht (C) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Hardware definitions for IXP23XX based systems
12 */
13
14#ifndef __ASM_ARCH_HARDWARE_H
15#define __ASM_ARCH_HARDWARE_H
16
17/* PCI IO info */
18#define PCIO_BASE IXP23XX_PCI_IO_VIRT
19#define PCIBIOS_MIN_IO 0x00000000
20#define PCIBIOS_MIN_MEM 0xe0000000
21
22#include "ixp23xx.h"
23
24#define pcibios_assign_all_busses() 0
25
26/*
27 * Platform helper functions
28 */
29#include "platform.h"
30
31/*
32 * Platform-specific headers
33 */
34#include "ixdp2351.h"
35
36
37#endif
diff --git a/include/asm-arm/arch-ixp23xx/io.h b/include/asm-arm/arch-ixp23xx/io.h
new file mode 100644
index 000000000000..18415a81ac74
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/io.h
@@ -0,0 +1,54 @@
1/*
2 * include/asm-arm/arch-ixp23xx/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2003-2005 Intel Corp.
8 * Copyright (C) 2005 MontaVista Software, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IO_H
16#define __ASM_ARCH_IO_H
17
18#define IO_SPACE_LIMIT 0xffffffff
19
20#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
21#define __mem_pci(a) (a)
22
23#include <linux/kernel.h> /* For BUG */
24
25static inline void __iomem *
26ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned long flags)
27{
28 if (addr >= IXP23XX_PCI_MEM_START &&
29 addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
30 if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
31 return NULL;
32
33 return (void __iomem *)
34 ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
35 }
36
37 return __ioremap(addr, size, flags);
38}
39
40static inline void
41ixp23xx_iounmap(void __iomem *addr)
42{
43 if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
44 (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
45 return;
46
47 __iounmap(addr);
48}
49
50#define __arch_ioremap(a,s,f) ixp23xx_ioremap(a,s,f)
51#define __arch_iounmap(a) ixp23xx_iounmap(a)
52
53
54#endif
diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h
new file mode 100644
index 000000000000..e69639585721
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/irqs.h
@@ -0,0 +1,223 @@
1/*
2 * include/asm-arm/arch-ixp23xx/irqs.h
3 *
4 * IRQ definitions for IXP23XX based systems
5 *
6 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Copyright (C) 2003-2004 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IRQS_H
16#define __ASM_ARCH_IRQS_H
17
18#define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1
19#define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS
20
21
22#define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */
23#define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */
24#define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */
25#define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */
26#define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */
27#define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */
28#define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */
29#define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */
30#define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */
31#define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */
32#define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */
33#define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */
34#define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */
35#define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */
36#define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */
37#define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */
38#define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */
39#define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */
40#define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */
41#define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */
42#define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */
43#define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */
44#define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */
45#define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */
46#define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */
47#define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */
48#define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */
49#define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */
50#define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */
51#define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */
52#define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */
53#define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */
54#define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */
55#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */
56#define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */
57#define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */
58#define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */
59#define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */
60#define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */
61#define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */
62#define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */
63#define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */
64#define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */
65#define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */
66#define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */
67#define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */
68#define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */
69#define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */
70#define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */
71#define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */
72#define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */
73#define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */
74#define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */
75#define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */
76#define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */
77#define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */
78#define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */
79#define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */
80#define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */
81#define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */
82#define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */
83#define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */
84#define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */
85#define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */
86#define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */
87#define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */
88#define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */
89#define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */
90#define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */
91#define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */
92#define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */
93#define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */
94#define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */
95#define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */
96#define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */
97#define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */
98#define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */
99#define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */
100#define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */
101#define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */
102#define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */
103#define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */
104#define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */
105#define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */
106#define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */
107#define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */
108#define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */
109#define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */
110#define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */
111#define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */
112#define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */
113#define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */
114#define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */
115#define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */
116#define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */
117#define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */
118#define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */
119#define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */
120#define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */
121#define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */
122#define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */
123#define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */
124#define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */
125#define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */
126#define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */
127#define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */
128#define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */
129#define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */
130#define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */
131#define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */
132#define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */
133#define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */
134#define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */
135#define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */
136#define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */
137#define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */
138#define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */
139#define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */
140#define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */
141#define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */
142
143#define NUM_IXP23XX_RAW_IRQS 120
144
145#define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */
146#define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */
147
148#define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1)
149
150/*
151 * We default to 32 per-board IRQs. Increase this number if you need
152 * more, but keep it realistic.
153 */
154#define NR_IXP23XX_MACH_IRQS 32
155
156#define NR_IRQS NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS
157
158#define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq))
159
160
161/*
162 * IXDP2351-specific interrupts
163 */
164
165/*
166 * External PCI interrupts signaled through INTB
167 *
168 */
169#define IXDP2351_INTB_IRQ_BASE 0
170#define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0)
171#define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1)
172#define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2)
173#define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3)
174#define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4)
175#define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5)
176#define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6)
177#define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7)
178#define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8)
179
180#define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0))
181#define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq))
182#define IXDP2351_INTB_IRQ_VALID 0x01FF
183#define IXDP2351_INTB_IRQ_NUM 16
184
185/*
186 * Other external interrupts signaled through INTA
187 */
188#define IXDP2351_INTA_IRQ_BASE 16
189#define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16)
190#define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17)
191#define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18)
192#define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19)
193#define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20)
194#define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21)
195#define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24)
196#define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25)
197#define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26)
198#define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27)
199#define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28)
200#define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29)
201#define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30)
202#define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31)
203
204#define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16))
205#define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq))
206#define IXDP2351_INTA_IRQ_VALID 0xFF3F
207#define IXDP2351_INTA_IRQ_NUM 16
208
209
210/*
211 * ADI RoadRunner IRQs
212 */
213#define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA
214#define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB
215#define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11
216#define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12
217
218/*
219 * Put new board definitions here
220 */
221
222
223#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixdp2351.h b/include/asm-arm/arch-ixp23xx/ixdp2351.h
new file mode 100644
index 000000000000..4a24f8f15655
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/ixdp2351.h
@@ -0,0 +1,89 @@
1/*
2 * include/asm-arm/arch-ixp23xx/ixdp2351.h
3 *
4 * Register and other defines for IXDP2351
5 *
6 * Copyright (c) 2002-2004 Intel Corp.
7 * Copytight (c) 2005 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#ifndef __ASM_ARCH_IXDP2351_H
16#define __ASM_ARCH_IXDP2351_H
17
18/*
19 * NP module memory map
20 */
21#define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE)
22#define IXDP2351_NP_PHYS_SIZE 0x00100000
23#define IXDP2351_NP_VIRT_BASE 0xeff00000
24
25#define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE)
26#define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16)
27
28#define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
29
30#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
31
32#define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00)
33#define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02)
34#define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04)
35
36/*
37 * Base board module memory map
38 */
39
40#define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE)
41#define IXDP2351_BB_SIZE 0x01000000
42#define IXDP2351_BB_BASE_VIRT (0xee000000)
43
44#define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset)
45
46#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0)
47#define IXDP2351_NVRAM_SIZE (0x20000)
48
49#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP3251_BB_AREA_BASE(0x00020000)
50#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0)
51#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000)
52#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000)
53#define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000)
54#define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000)
55
56/*
57 * On board CPLD registers
58 */
59#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
60
61#define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00)
62#define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04)
63
64#define IXDP2351_CPLD_RESET1_MAGIC 0x55AA
65#define IXDP2351_CPLD_RESET1_ENABLE 0x8000
66
67#define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08)
68#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10)
69#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14)
70#define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18)
71#define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C)
72#define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */
73#define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */
74#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */
75#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */
76#define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28)
77#define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C)
78 /* Interrupt bits are defined in irqs.h */
79#define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30)
80#define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34)
81
82/* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */
83/* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */
84/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */
85/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */
86/* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */
87
88
89#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixp23xx.h b/include/asm-arm/arch-ixp23xx/ixp23xx.h
new file mode 100644
index 000000000000..e49e1ca61b1a
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/ixp23xx.h
@@ -0,0 +1,306 @@
1/*
2 * include/asm-arm/arch-ixp23xx/ixp23xx.h
3 *
4 * Register definitions for IXP23XX
5 *
6 * Copyright (C) 2003-2005 Intel Corporation.
7 * Copyright (C) 2005 MontaVista Software, Inc.
8 *
9 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_IXP23XX_H
17#define __ASM_ARCH_IXP23XX_H
18
19/*
20 * IXP2300 linux memory map:
21 *
22 * virt phys size
23 * fffd0000 a0000000 64K XSI2CPP_CSR
24 * fffc0000 c4000000 4K EXP_CFG
25 * fff00000 c8000000 64K PERIPHERAL
26 * fe000000 1c0000000 16M CAP_CSR
27 * fd000000 1c8000000 16M MSF_CSR
28 * fb000000 16M ---
29 * fa000000 1d8000000 32M PCI_IO
30 * f8000000 1da000000 32M PCI_CFG
31 * f6000000 1de000000 32M PCI_CREG
32 * f4000000 32M ---
33 * f0000000 1e0000000 64M PCI_MEM
34 * e[c-f]000000 per-platform mappings
35 */
36
37
38/****************************************************************************
39 * Static mappings.
40 ****************************************************************************/
41#define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000
42#define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000
43#define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000
44
45#define IXP23XX_EXP_CFG_PHYS 0xc4000000
46#define IXP23XX_EXP_CFG_VIRT 0xfffc0000
47#define IXP23XX_EXP_CFG_SIZE 0x00001000
48
49#define IXP23XX_PERIPHERAL_PHYS 0xc8000000
50#define IXP23XX_PERIPHERAL_VIRT 0xfff00000
51#define IXP23XX_PERIPHERAL_SIZE 0x00010000
52
53#define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL
54#define IXP23XX_CAP_CSR_VIRT 0xfe000000
55#define IXP23XX_CAP_CSR_SIZE 0x01000000
56
57#define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL
58#define IXP23XX_MSF_CSR_VIRT 0xfd000000
59#define IXP23XX_MSF_CSR_SIZE 0x01000000
60
61#define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL
62#define IXP23XX_PCI_IO_VIRT 0xfa000000
63#define IXP23XX_PCI_IO_SIZE 0x02000000
64
65#define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL
66#define IXP23XX_PCI_CFG_VIRT 0xf8000000
67#define IXP23XX_PCI_CFG_SIZE 0x02000000
68#define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT
69#define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000)
70
71#define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL
72#define IXP23XX_PCI_CREG_VIRT 0xf6000000
73#define IXP23XX_PCI_CREG_SIZE 0x02000000
74#define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000)
75
76#define IXP23XX_PCI_MEM_START 0xe0000000
77#define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL
78#define IXP23XX_PCI_MEM_VIRT 0xf0000000
79#define IXP23XX_PCI_MEM_SIZE 0x04000000
80
81
82/****************************************************************************
83 * XSI2CPP CSRs.
84 ****************************************************************************/
85#define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
86#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8)
87#define IXP23XX_CPP2XSI_ADDR_31 (1 << 19)
88#define IXP23XX_CPP2XSI_PSH_OFF (1 << 20)
89#define IXP23XX_CPP2XSI_COH_OFF (1 << 21)
90
91
92/****************************************************************************
93 * Expansion Bus Config.
94 ****************************************************************************/
95#define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
96#define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00)
97#define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04)
98#define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08)
99#define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c)
100#define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10)
101#define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14)
102#define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18)
103#define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c)
104#define IXP23XX_FLASH_WRITABLE (0x2)
105#define IXP23XX_FLASH_BUS8 (0x1)
106
107#define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20)
108#define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24)
109#define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31)
110#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22)
111#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21)
112#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19)
113#define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18)
114#define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16)
115#define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14)
116#define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13)
117#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12)
118#define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5)
119#define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4)
120#define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3)
121#define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2)
122#define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1)
123#define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0)
124
125#define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28)
126#define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30)
127
128#define IXP23XX_EXP_BUS_PHYS 0x90000000
129#define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000
130
131#define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000)
132#define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000)
133#define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000)
134#define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000)
135#define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000)
136#define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000)
137#define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000)
138#define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000)
139
140
141/****************************************************************************
142 * Peripherals.
143 ****************************************************************************/
144#define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000)
145#define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000)
146#define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000)
147#define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000)
148#define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000)
149#define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000)
150#define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000)
151#define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000)
152#define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000)
153#define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000)
154#define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000)
155#define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000)
156#define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000)
157#define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000)
158
159#define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000)
160#define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000)
161#define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000)
162#define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000)
163#define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000)
164#define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000)
165#define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000)
166#define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000)
167#define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000)
168#define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000)
169#define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000)
170#define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000)
171#define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000)
172#define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000)
173
174
175/****************************************************************************
176 * Interrupt controller.
177 ****************************************************************************/
178#define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
179#define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00)
180#define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04)
181#define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08)
182#define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c)
183#define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10)
184#define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14)
185#define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18)
186#define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c)
187#define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20)
188#define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24)
189#define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28)
190#define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c)
191#define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30)
192#define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34)
193#define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38)
194#define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c)
195#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54
196
197
198/****************************************************************************
199 * GPIO.
200 ****************************************************************************/
201#define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
202#define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00)
203#define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04)
204#define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08)
205#define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c)
206#define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10)
207#define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14)
208#define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18)
209#define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c)
210
211#define IXP23XX_GPIO_STYLE_MASK 0x7
212#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0
213#define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1
214#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2
215#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3
216#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4
217
218#define IXP23XX_GPIO_STYLE_SIZE 3
219
220
221/****************************************************************************
222 * Timer.
223 ****************************************************************************/
224#define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
225#define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00)
226#define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04)
227#define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08)
228#define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c)
229#define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10)
230#define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14)
231#define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18)
232#define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c)
233#define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e
234#define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20)
235#define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24)
236#define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28)
237
238#define IXP23XX_TIMER_ENABLE (1 << 0)
239#define IXP23XX_TIMER_ONE_SHOT (1 << 1)
240/* Low order bits of reload value ignored */
241#define IXP23XX_TIMER_RELOAD_MASK (0x3)
242#define IXP23XX_TIMER_DISABLED (0x0)
243#define IXP23XX_TIMER1_INT_PEND (1 << 0)
244#define IXP23XX_TIMER2_INT_PEND (1 << 1)
245#define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2)
246#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3)
247#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4)
248
249
250/****************************************************************************
251 * CAP CSRs.
252 ****************************************************************************/
253#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
254#define IXP23XX_PROD_IDG IXP23XX_GLOBAL_REG(0x00)
255#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04)
256#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08)
257#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c)
258#define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10)
259#define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18)
260
261#define IXP23XX_ENABLE_WATCHDOG (1 << 24)
262#define IXP23XX_SHPC_INIT_COMP (1 << 21)
263#define IXP23XX_RST_ALL (1 << 16)
264#define IXP23XX_RESET_PCI (1 << 2)
265#define IXP23XX_PCI_UNIT_RESET (1 << 1)
266#define IXP23XX_XSCALE_RESET (1 << 0)
267
268
269/****************************************************************************
270 * PCI CSRs.
271 ****************************************************************************/
272#define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
273#define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04)
274#define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14)
275#define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18)
276
277
278#define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
279#define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030)
280#define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034)
281#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
282#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
283#define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c)
284#define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140)
285#define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148)
286#define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c)
287#define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150)
288#define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150)
289#define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154)
290#define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158)
291#define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c)
292#define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160)
293
294
295#ifndef __ASSEMBLY__
296/*
297 * Is system memory on the XSI or CPP bus?
298 */
299static inline unsigned ixp23xx_cpp_boot(void)
300{
301 return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
302}
303#endif
304
305
306#endif
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h
new file mode 100644
index 000000000000..bebcf0aa0d72
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/memory.h
@@ -0,0 +1,46 @@
1/*
2 * include/asm-arm/arch-ixp23xx/memory.h
3 *
4 * Copyright (c) 2003-2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15#include <asm/hardware.h>
16
17/*
18 * Physical DRAM offset.
19 */
20#define PHYS_OFFSET (0x00000000)
21
22
23/*
24 * Virtual view <-> DMA view memory address translations
25 * virt_to_bus: Used to translate the virtual address to an
26 * address suitable to be passed to set_dma_addr
27 * bus_to_virt: Used to convert an address for DMA operations
28 * to an address that the kernel can use.
29 */
30#ifndef __ASSEMBLY__
31
32#define __virt_to_bus(v) \
33 ({ unsigned int ret; \
34 ret = ((__virt_to_phys(v) - 0x00000000) + \
35 (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)); \
36 ret; })
37
38#define __bus_to_virt(b) \
39 ({ unsigned int data; \
40 data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \
41 __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
42
43#endif
44
45
46#endif
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h
new file mode 100644
index 000000000000..f85b4685a491
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/platform.h
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-ixp23xx/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASSEMBLY__
16
17struct pci_sys_data;
18
19void ixp23xx_map_io(void);
20void ixp23xx_init_irq(void);
21void ixp23xx_sys_init(void);
22int ixp23xx_pci_setup(int, struct pci_sys_data *);
23void ixp23xx_pci_preinit(void);
24struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
25
26extern struct sys_timer ixp23xx_timer;
27
28#define IXP23XX_UART_XTAL 14745600
29
30
31#endif
diff --git a/include/asm-arm/arch-ixp23xx/system.h b/include/asm-arm/arch-ixp23xx/system.h
new file mode 100644
index 000000000000..925e6b0c338b
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/system.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-ixp23xx/system.h
3 *
4 * Copyright (C) 2003 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <asm/hardware.h>
12#include <asm/mach-types.h>
13
14static inline void arch_idle(void)
15{
16#if 0
17 if (!hlt_counter)
18 cpu_do_idle();
19#endif
20}
21
22static inline void arch_reset(char mode)
23{
24 /* First try machine specific support */
25 if (machine_is_ixdp2351()) {
26 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
27 (void) *IXDP2351_CPLD_RESET1_REG;
28 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
29 }
30
31 /* Use on-chip reset capability */
32 *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
33}
diff --git a/include/asm-arm/arch-ixp23xx/time.h b/include/asm-arm/arch-ixp23xx/time.h
new file mode 100644
index 000000000000..f6828fdd2883
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/time.h
@@ -0,0 +1,3 @@
1/*
2 * include/asm-arm/arch-ixp23xx/time.h
3 */
diff --git a/include/asm-arm/arch-ixp23xx/timex.h b/include/asm-arm/arch-ixp23xx/timex.h
new file mode 100644
index 000000000000..516f72fe6082
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/timex.h
@@ -0,0 +1,7 @@
1/*
2 * include/asm-arm/arch-ixp23xx/timex.h
3 *
4 * XScale architecture timex specifications
5 */
6
7#define CLOCK_TICK_RATE 75000000
diff --git a/include/asm-arm/arch-ixp23xx/uncompress.h b/include/asm-arm/arch-ixp23xx/uncompress.h
new file mode 100644
index 000000000000..62623fa9b2f7
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/uncompress.h
@@ -0,0 +1,45 @@
1/*
2 * include/asm-arm/arch-ixp23xx/uncompress.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_UNCOMPRESS_H
12#define __ASM_ARCH_UNCOMPRESS_H
13
14#include <asm/hardware.h>
15#include <linux/serial_reg.h>
16
17#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS)
18
19static __inline__ void putc(char c)
20{
21 int j;
22
23 for (j = 0; j < 0x1000; j++) {
24 if (UART_BASE[UART_LSR] & UART_LSR_THRE)
25 break;
26 }
27
28 UART_BASE[UART_TX] = c;
29}
30
31static void putstr(const char *s)
32{
33 while (*s) {
34 putc(*s);
35 if (*s == '\n')
36 putc('\r');
37 s++;
38 }
39}
40
41#define arch_decomp_setup()
42#define arch_decomp_wdog()
43
44
45#endif
diff --git a/include/asm-arm/arch-ixp23xx/vmalloc.h b/include/asm-arm/arch-ixp23xx/vmalloc.h
new file mode 100644
index 000000000000..9f2566658541
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/vmalloc.h
@@ -0,0 +1,10 @@
1/*
2 * include/asm-arm/arch-ixp23xx/vmalloc.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc.
5 *
6 * NPU mappings end at 0xf0000000 and we allocate 64MB for board
7 * specific static I/O.
8 */
9
10#define VMALLOC_END (0xec000000)
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
index 960c35810a22..09ae6c91be60 100644
--- a/include/asm-arm/arch-ixp4xx/uncompress.h
+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
@@ -21,26 +21,18 @@
21 21
22static volatile u32* uart_base; 22static volatile u32* uart_base;
23 23
24static __inline__ void putc(char c) 24static inline void putc(int c)
25{ 25{
26 /* Check THRE and TEMT bits before we transmit the character. 26 /* Check THRE and TEMT bits before we transmit the character.
27 */ 27 */
28 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE); 28 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
29 barrier();
30
29 *uart_base = c; 31 *uart_base = c;
30} 32}
31 33
32/* 34static void flush(void)
33 * This does not append a newline
34 */
35static void putstr(const char *s)
36{ 35{
37 while (*s)
38 {
39 putc(*s);
40 if (*s == '\n')
41 putc('\r');
42 s++;
43 }
44} 36}
45 37
46static __inline__ void __arch_decomp_setup(unsigned long arch_id) 38static __inline__ void __arch_decomp_setup(unsigned long arch_id)
diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h
index 1caa2b560f53..9fcd40aee3e3 100644
--- a/include/asm-arm/arch-l7200/uncompress.h
+++ b/include/asm-arm/arch-l7200/uncompress.h
@@ -16,22 +16,17 @@
16#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v)) 16#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v))
17#define __raw_readb(p) (*(volatile unsigned char *)(p)) 17#define __raw_readb(p) (*(volatile unsigned char *)(p))
18 18
19static __inline__ void putc(char c) 19static inline void putc(int c)
20{ 20{
21 while(__raw_readb(IO_UART + 0x18) & 0x20 || 21 while(__raw_readb(IO_UART + 0x18) & 0x20 ||
22 __raw_readb(IO_UART + 0x18) & 0x08); 22 __raw_readb(IO_UART + 0x18) & 0x08)
23 barrier();
24
23 __raw_writeb(c, IO_UART + 0x00); 25 __raw_writeb(c, IO_UART + 0x00);
24} 26}
25 27
26static void putstr(const char *s) 28static inline void flush(void)
27{ 29{
28 while (*s) {
29 if (*s == 10) { /* If a LF, add CR */
30 putc(10);
31 putc(13);
32 }
33 putc(*(s++));
34 }
35} 30}
36 31
37static __inline__ void arch_decomp_setup(void) 32static __inline__ void arch_decomp_setup(void)
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
index ec8ab67122f3..f8053346f608 100644
--- a/include/asm-arm/arch-lh7a40x/uncompress.h
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -22,20 +22,15 @@
22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) 22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
23#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA)) 23#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
24 24
25static __inline__ void putc (char ch) 25static inline void putc(int ch)
26{ 26{
27 while (UART_STATUS & nTxRdy) 27 while (UART_STATUS & nTxRdy)
28 ; 28 barrier();
29 UART_DATA = ch; 29 UART_DATA = ch;
30} 30}
31 31
32static void putstr (const char* sz) 32static inline void flush(void)
33{ 33{
34 for (; *sz; ++sz) {
35 putc (*sz);
36 if (*sz == '\n')
37 putc ('\r');
38 }
39} 34}
40 35
41 /* NULL functions; we don't presently need them */ 36 /* NULL functions; we don't presently need them */
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
index c718264affbd..ca2c8bec82e7 100644
--- a/include/asm-arm/arch-omap/uncompress.h
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -30,8 +30,7 @@ unsigned int system_rev;
30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) 30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK 31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
32 32
33static void 33static void putc(int c)
34putstr(const char *s)
35{ 34{
36 volatile u8 * uart = 0; 35 volatile u8 * uart = 0;
37 int shift = 2; 36 int shift = 2;
@@ -69,16 +68,13 @@ putstr(const char *s)
69 /* 68 /*
70 * Now, xmit each character 69 * Now, xmit each character
71 */ 70 */
72 while (*s) { 71 while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
73 while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) 72 barrier();
74 barrier(); 73 uart[UART_TX << shift] = c;
75 uart[UART_TX << shift] = *s; 74}
76 if (*s++ == '\n') { 75
77 while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) 76static inline void flush(void)
78 barrier(); 77{
79 uart[UART_TX << shift] = '\r';
80 }
81 }
82} 78}
83 79
84/* 80/*
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index 05c4b7027592..67af238a8f8e 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -176,6 +176,7 @@
176#elif defined(CONFIG_SHARP_LOCOMO) 176#elif defined(CONFIG_SHARP_LOCOMO)
177#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) 177#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
178#elif defined(CONFIG_ARCH_LUBBOCK) || \ 178#elif defined(CONFIG_ARCH_LUBBOCK) || \
179 defined(CONFIG_MACH_LOGICPD_PXA270) || \
179 defined(CONFIG_MACH_MAINSTONE) 180 defined(CONFIG_MACH_MAINSTONE)
180#define NR_IRQS (IRQ_BOARD_END) 181#define NR_IRQS (IRQ_BOARD_END)
181#else 182#else
@@ -196,6 +197,11 @@
196#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ 197#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
197#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) 198#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
198 199
200#define LPD270_IRQ(x) (IRQ_BOARD_START + (x))
201#define LPD270_USBC_IRQ LPD270_IRQ(2)
202#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
203#define LPD270_AC97_IRQ LPD270_IRQ(4)
204
199#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) 205#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
200#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) 206#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
201#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) 207#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
diff --git a/include/asm-arm/arch-pxa/lpd270.h b/include/asm-arm/arch-pxa/lpd270.h
new file mode 100644
index 000000000000..501d240ac120
--- /dev/null
+++ b/include/asm-arm/arch-pxa/lpd270.h
@@ -0,0 +1,38 @@
1/*
2 * include/asm-arm/arch-pxa/lpd270.h
3 *
4 * Author: Lennert Buytenhek
5 * Created: Feb 10, 2006
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_LPD270_H
13#define __ASM_ARCH_LPD270_H
14
15#define LPD270_CPLD_PHYS PXA_CS2_PHYS
16#define LPD270_CPLD_VIRT 0xf0000000
17#define LPD270_CPLD_SIZE 0x00100000
18
19#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000)
20
21/* CPLD registers */
22#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x)))
23#define LPD270_CONTROL LPD270_CPLD_REG(0x00)
24#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04)
25#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08)
26#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14)
27#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20)
28#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24)
29#define LPD270_EGPIO LPD270_CPLD_REG(0x30)
30#define LPD270_INT_MASK LPD270_CPLD_REG(0x40)
31#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50)
32
33#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */
34#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
35#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */
36
37
38#endif
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index fe38090444e0..178aa2e073ac 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -17,23 +17,18 @@
17#define UART FFUART 17#define UART FFUART
18 18
19 19
20static __inline__ void putc(char c) 20static inline void putc(char c)
21{ 21{
22 while (!(UART[5] & 0x20)); 22 while (!(UART[5] & 0x20))
23 barrier();
23 UART[0] = c; 24 UART[0] = c;
24} 25}
25 26
26/* 27/*
27 * This does not append a newline 28 * This does not append a newline
28 */ 29 */
29static void putstr(const char *s) 30static inline void flush(void)
30{ 31{
31 while (*s) {
32 putc(*s);
33 if (*s == '\n')
34 putc('\r');
35 s++;
36 }
37} 32}
38 33
39/* 34/*
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
index b5e4d360665b..f05631d76743 100644
--- a/include/asm-arm/arch-realview/uncompress.h
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -27,22 +27,16 @@
27/* 27/*
28 * This does not append a newline 28 * This does not append a newline
29 */ 29 */
30static void putstr(const char *s) 30static inline void putc(int c)
31{ 31{
32 while (*s) { 32 while (AMBA_UART_FR & (1 << 5))
33 while (AMBA_UART_FR & (1 << 5)) 33 barrier();
34 barrier();
35
36 AMBA_UART_DR = *s;
37 34
38 if (*s == '\n') { 35 AMBA_UART_DR = c;
39 while (AMBA_UART_FR & (1 << 5)) 36}
40 barrier();
41 37
42 AMBA_UART_DR = '\r'; 38static inline void flush(void)
43 } 39{
44 s++;
45 }
46 while (AMBA_UART_FR & (1 << 3)) 40 while (AMBA_UART_FR & (1 << 3))
47 barrier(); 41 barrier();
48} 42}
diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h
index 43035fec64d2..06231ede54e5 100644
--- a/include/asm-arm/arch-rpc/uncompress.h
+++ b/include/asm-arm/arch-rpc/uncompress.h
@@ -67,31 +67,28 @@ extern __attribute__((pure)) struct param_struct *params(void);
67/* 67/*
68 * This does not append a newline 68 * This does not append a newline
69 */ 69 */
70static void putstr(const char *s) 70static void putc(int c)
71{ 71{
72 extern void ll_write_char(char *, char c, char white); 72 extern void ll_write_char(char *, char c, char white);
73 int x,y; 73 int x,y;
74 unsigned char c;
75 char *ptr; 74 char *ptr;
76 75
77 x = params->video_x; 76 x = params->video_x;
78 y = params->video_y; 77 y = params->video_y;
79 78
80 while ( ( c = *(unsigned char *)s++ ) != '\0' ) { 79 if (c == '\n') {
81 if ( c == '\n' ) { 80 if (++y >= video_num_lines)
81 y--;
82 } else if (c == '\r') {
83 x = 0;
84 } else {
85 ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h);
86 ll_write_char(ptr, c, white);
87 if (++x >= video_num_columns) {
82 x = 0; 88 x = 0;
83 if ( ++y >= video_num_lines ) { 89 if ( ++y >= video_num_lines ) {
84 y--; 90 y--;
85 } 91 }
86 } else {
87 ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h);
88 ll_write_char(ptr, c, white);
89 if ( ++x >= video_num_columns ) {
90 x = 0;
91 if ( ++y >= video_num_lines ) {
92 y--;
93 }
94 }
95 } 92 }
96 } 93 }
97 94
@@ -99,6 +96,10 @@ static void putstr(const char *s)
99 params->video_y = y; 96 params->video_y = y;
100} 97}
101 98
99static inline void flush(void)
100{
101}
102
102static void error(char *x); 103static void error(char *x);
103 104
104/* 105/*
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index 4367ec054b51..a6f6a0e44afa 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -67,8 +67,7 @@ uart_rd(unsigned int reg)
67 * waiting for tx to happen... 67 * waiting for tx to happen...
68*/ 68*/
69 69
70static void 70static void putc(int ch)
71putc(char ch)
72{ 71{
73 int cpuid = S3C2410_GSTATUS1_2410; 72 int cpuid = S3C2410_GSTATUS1_2410;
74 73
@@ -77,9 +76,6 @@ putc(char ch)
77 cpuid &= S3C2410_GSTATUS1_IDMASK; 76 cpuid &= S3C2410_GSTATUS1_IDMASK;
78#endif 77#endif
79 78
80 if (ch == '\n')
81 putc('\r'); /* expand newline to \r\n */
82
83 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { 79 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
84 int level; 80 int level;
85 81
@@ -101,19 +97,16 @@ putc(char ch)
101 } else { 97 } else {
102 /* not using fifos */ 98 /* not using fifos */
103 99
104 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE); 100 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
101 barrier();
105 } 102 }
106 103
107 /* write byte to transmission register */ 104 /* write byte to transmission register */
108 uart_wr(S3C2410_UTXH, ch); 105 uart_wr(S3C2410_UTXH, ch);
109} 106}
110 107
111static void 108static inline void flush(void)
112putstr(const char *ptr)
113{ 109{
114 for (; *ptr != '\0'; ptr++) {
115 putc(*ptr);
116 }
117} 110}
118 111
119#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) 112#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
diff --git a/include/asm-arm/arch-sa1100/uncompress.h b/include/asm-arm/arch-sa1100/uncompress.h
index 43453501ee66..2601a77a6dda 100644
--- a/include/asm-arm/arch-sa1100/uncompress.h
+++ b/include/asm-arm/arch-sa1100/uncompress.h
@@ -17,7 +17,7 @@
17 17
18#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) 18#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
19 19
20static void putstr( const char *s ) 20static void putc(int c)
21{ 21{
22 unsigned long serial_port; 22 unsigned long serial_port;
23 23
@@ -31,19 +31,16 @@ static void putstr( const char *s )
31 return; 31 return;
32 } while (0); 32 } while (0);
33 33
34 for (; *s; s++) { 34 /* wait for space in the UART's transmitter */
35 /* wait for space in the UART's transmitter */ 35 while (!(UART(UTSR1) & UTSR1_TNF))
36 while (!(UART(UTSR1) & UTSR1_TNF)); 36 barrier();
37 37
38 /* send the character out. */ 38 /* send the character out. */
39 UART(UTDR) = *s; 39 UART(UTDR) = c;
40}
40 41
41 /* if a LF, also do CR... */ 42static inline void flush(void)
42 if (*s == 10) { 43{
43 while (!(UART(UTSR1) & UTSR1_TNF));
44 UART(UTDR) = 13;
45 }
46 }
47} 44}
48 45
49/* 46/*
diff --git a/include/asm-arm/arch-shark/uncompress.h b/include/asm-arm/arch-shark/uncompress.h
index 910a8e0a0ca5..7eca6534f1bb 100644
--- a/include/asm-arm/arch-shark/uncompress.h
+++ b/include/asm-arm/arch-shark/uncompress.h
@@ -9,7 +9,7 @@
9 9
10#define SERIAL_BASE ((volatile unsigned char *)0x400003f8) 10#define SERIAL_BASE ((volatile unsigned char *)0x400003f8)
11 11
12static __inline__ void putc(char c) 12static inline void putc(int c)
13{ 13{
14 int t; 14 int t;
15 15
@@ -18,17 +18,8 @@ static __inline__ void putc(char c)
18 while (t--); 18 while (t--);
19} 19}
20 20
21/* 21static inline void flush(void)
22 * This does not append a newline
23 */
24static void putstr(const char *s)
25{ 22{
26 while (*s) {
27 putc(*s);
28 if (*s == '\n')
29 putc('\r');
30 s++;
31 }
32} 23}
33 24
34#ifdef DEBUG 25#ifdef DEBUG
diff --git a/include/asm-arm/arch-versatile/uncompress.h b/include/asm-arm/arch-versatile/uncompress.h
index 2f57499c7b92..7215133d0514 100644
--- a/include/asm-arm/arch-versatile/uncompress.h
+++ b/include/asm-arm/arch-versatile/uncompress.h
@@ -25,22 +25,16 @@
25/* 25/*
26 * This does not append a newline 26 * This does not append a newline
27 */ 27 */
28static void putstr(const char *s) 28static inline void putc(int c)
29{ 29{
30 while (*s) { 30 while (AMBA_UART_FR & (1 << 5))
31 while (AMBA_UART_FR & (1 << 5)) 31 barrier();
32 barrier();
33
34 AMBA_UART_DR = *s;
35 32
36 if (*s == '\n') { 33 AMBA_UART_DR = c;
37 while (AMBA_UART_FR & (1 << 5)) 34}
38 barrier();
39 35
40 AMBA_UART_DR = '\r'; 36static inline void flush(void)
41 } 37{
42 s++;
43 }
44 while (AMBA_UART_FR & (1 << 3)) 38 while (AMBA_UART_FR & (1 << 3))
45 barrier(); 39 barrier();
46} 40}
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 09e19a783a51..746be56b1b70 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -71,6 +71,14 @@
71# endif 71# endif
72#endif 72#endif
73 73
74#if defined(CONFIG_CPU_XSC3)
75# ifdef _CACHE
76# define MULTI_CACHE 1
77# else
78# define _CACHE xsc3
79# endif
80#endif
81
74#if defined(CONFIG_CPU_V6) 82#if defined(CONFIG_CPU_V6)
75//# ifdef _CACHE 83//# ifdef _CACHE
76# define MULTI_CACHE 1 84# define MULTI_CACHE 1
diff --git a/include/asm-arm/domain.h b/include/asm-arm/domain.h
index da1d960387d9..f8ea2de4848e 100644
--- a/include/asm-arm/domain.h
+++ b/include/asm-arm/domain.h
@@ -16,11 +16,29 @@
16 * DOMAIN_IO - domain 2 includes all IO only 16 * DOMAIN_IO - domain 2 includes all IO only
17 * DOMAIN_USER - domain 1 includes all user memory only 17 * DOMAIN_USER - domain 1 includes all user memory only
18 * DOMAIN_KERNEL - domain 0 includes all kernel memory only 18 * DOMAIN_KERNEL - domain 0 includes all kernel memory only
19 *
20 * The domain numbering depends on whether we support 36 physical
21 * address for I/O or not. Addresses above the 32 bit boundary can
22 * only be mapped using supersections and supersections can only
23 * be set for domain 0. We could just default to DOMAIN_IO as zero,
24 * but there may be systems with supersection support and no 36-bit
25 * addressing. In such cases, we want to map system memory with
26 * supersections to reduce TLB misses and footprint.
27 *
28 * 36-bit addressing and supersections are only available on
29 * CPUs based on ARMv6+ or the Intel XSC3 core.
19 */ 30 */
31#ifndef CONFIG_IO_36
20#define DOMAIN_KERNEL 0 32#define DOMAIN_KERNEL 0
21#define DOMAIN_TABLE 0 33#define DOMAIN_TABLE 0
22#define DOMAIN_USER 1 34#define DOMAIN_USER 1
23#define DOMAIN_IO 2 35#define DOMAIN_IO 2
36#else
37#define DOMAIN_KERNEL 2
38#define DOMAIN_TABLE 2
39#define DOMAIN_USER 1
40#define DOMAIN_IO 0
41#endif
24 42
25/* 43/*
26 * Domain types 44 * Domain types
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 416320d95419..a404d2bf0c68 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -40,6 +40,7 @@
40 * v4wb - ARMv4 with writeback cache, without minicache 40 * v4wb - ARMv4 with writeback cache, without minicache
41 * v4_mc - ARMv4 with minicache 41 * v4_mc - ARMv4 with minicache
42 * xscale - Xscale 42 * xscale - Xscale
43 * xsc3 - XScalev3
43 */ 44 */
44#undef _USER 45#undef _USER
45#undef MULTI_USER 46#undef MULTI_USER
@@ -84,6 +85,14 @@
84# endif 85# endif
85#endif 86#endif
86 87
88#ifdef CONFIG_CPU_XSC3
89# ifdef _USER
90# define MULTI_USER 1
91# else
92# define _USER xsc3_mc
93# endif
94#endif
95
87#ifdef CONFIG_CPU_COPY_V6 96#ifdef CONFIG_CPU_COPY_V6
88# define MULTI_USER 1 97# define MULTI_USER 1
89#endif 98#endif
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 7bef2bf6be51..106045edb862 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -138,6 +138,14 @@
138# define CPU_NAME cpu_xscale 138# define CPU_NAME cpu_xscale
139# endif 139# endif
140# endif 140# endif
141# ifdef CONFIG_CPU_XSC3
142# ifdef CPU_NAME
143# undef MULTI_CPU
144# define MULTI_CPU
145# else
146# define CPU_NAME cpu_xsc3
147# endif
148# endif
141# ifdef CONFIG_CPU_V6 149# ifdef CONFIG_CPU_V6
142# ifdef CPU_NAME 150# ifdef CPU_NAME
143# undef MULTI_CPU 151# undef MULTI_CPU
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index ec91d1ff032a..95b3abf4851b 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -108,6 +108,25 @@ extern void __show_regs(struct pt_regs *);
108extern int cpu_architecture(void); 108extern int cpu_architecture(void);
109extern void cpu_init(void); 109extern void cpu_init(void);
110 110
111/*
112 * Intel's XScale3 core supports some v6 features (supersections, L2)
113 * but advertises itself as v5 as it does not support the v6 ISA. For
114 * this reason, we need a way to explicitly test for this type of CPU.
115 */
116#ifndef CONFIG_CPU_XSC3
117#define cpu_is_xsc3() 0
118#else
119static inline int cpu_is_xsc3(void)
120{
121 extern unsigned int processor_id;
122
123 if ((processor_id & 0xffffe000) == 0x69056000)
124 return 1;
125
126 return 0;
127}
128#endif
129
111#define set_cr(x) \ 130#define set_cr(x) \
112 __asm__ __volatile__( \ 131 __asm__ __volatile__( \
113 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ 132 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 10:33:39 -0500