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-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h11
-rw-r--r--include/asm-arm/arch-pxa/pxafb.h7
2 files changed, 17 insertions, 1 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 67f53e07db86..bb68b598c436 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1823,6 +1823,7 @@
1823#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ 1823#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
1824#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ 1824#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
1825#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ 1825#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
1826#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 3 */
1826#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ 1827#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1827#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ 1828#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1828#define LCSR __REG(0x44000038) /* LCD Controller Status Register */ 1829#define LCSR __REG(0x44000038) /* LCD Controller Status Register */
@@ -1836,6 +1837,16 @@
1836#define LCCR3_8BPP (3 << 24) 1837#define LCCR3_8BPP (3 << 24)
1837#define LCCR3_16BPP (4 << 24) 1838#define LCCR3_16BPP (4 << 24)
1838 1839
1840#define LCCR3_PDFOR_0 (0 << 30)
1841#define LCCR3_PDFOR_1 (1 << 30)
1842#define LCCR3_PDFOR_2 (2 << 30)
1843#define LCCR3_PDFOR_3 (3 << 30)
1844
1845#define LCCR4_PAL_FOR_0 (0 << 15)
1846#define LCCR4_PAL_FOR_1 (1 << 15)
1847#define LCCR4_PAL_FOR_2 (2 << 15)
1848#define LCCR4_PAL_FOR_MASK (3 << 15)
1849
1839#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ 1850#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1840#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ 1851#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1841#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ 1852#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
index 81c3928d608c..ea2336aa70e4 100644
--- a/include/asm-arm/arch-pxa/pxafb.h
+++ b/include/asm-arm/arch-pxa/pxafb.h
@@ -70,7 +70,12 @@ struct pxafb_mach_info {
70 * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp 70 * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
71 */ 71 */
72 u_int lccr3; 72 u_int lccr3;
73 73 /* The following should be defined in LCCR4
74 * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
75 *
76 * All other bits in LCCR4 should be left alone.
77 */
78 u_int lccr4;
74 void (*pxafb_backlight_power)(int); 79 void (*pxafb_backlight_power)(int);
75 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); 80 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
76 81