aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200.h261
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_sys.h328
-rw-r--r--include/asm-arm/arch-at91rm9200/board.h80
-rw-r--r--include/asm-arm/arch-at91rm9200/debug-macro.S38
-rw-r--r--include/asm-arm/arch-at91rm9200/dma.h27
-rw-r--r--include/asm-arm/arch-at91rm9200/entry-macro.S25
-rw-r--r--include/asm-arm/arch-at91rm9200/gpio.h193
-rw-r--r--include/asm-arm/arch-at91rm9200/hardware.h92
-rw-r--r--include/asm-arm/arch-at91rm9200/io.h33
-rw-r--r--include/asm-arm/arch-at91rm9200/irqs.h52
-rw-r--r--include/asm-arm/arch-at91rm9200/memory.h41
-rw-r--r--include/asm-arm/arch-at91rm9200/param.h28
-rw-r--r--include/asm-arm/arch-at91rm9200/pio.h115
-rw-r--r--include/asm-arm/arch-at91rm9200/system.h51
-rw-r--r--include/asm-arm/arch-at91rm9200/timex.h28
-rw-r--r--include/asm-arm/arch-at91rm9200/uncompress.h55
-rw-r--r--include/asm-arm/arch-at91rm9200/vmalloc.h26
17 files changed, 1473 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
new file mode 100644
index 000000000000..58f40931a5c1
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -0,0 +1,261 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Common definitions.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_H
17#define AT91RM9200_H
18
19/*
20 * Peripheral identifiers/interrupts.
21 */
22#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23#define AT91_ID_SYS 1 /* System Peripheral */
24#define AT91_ID_PIOA 2 /* Parallel IO Controller A */
25#define AT91_ID_PIOB 3 /* Parallel IO Controller B */
26#define AT91_ID_PIOC 4 /* Parallel IO Controller C */
27#define AT91_ID_PIOD 5 /* Parallel IO Controller D */
28#define AT91_ID_US0 6 /* USART 0 */
29#define AT91_ID_US1 7 /* USART 1 */
30#define AT91_ID_US2 8 /* USART 2 */
31#define AT91_ID_US3 9 /* USART 3 */
32#define AT91_ID_MCI 10 /* Multimedia Card Interface */
33#define AT91_ID_UDP 11 /* USB Device Port */
34#define AT91_ID_TWI 12 /* Two-Wire Interface */
35#define AT91_ID_SPI 13 /* Serial Peripheral Interface */
36#define AT91_ID_SSC0 14 /* Serial Synchronous Controller 0 */
37#define AT91_ID_SSC1 15 /* Serial Synchronous Controller 1 */
38#define AT91_ID_SSC2 16 /* Serial Synchronous Controller 2 */
39#define AT91_ID_TC0 17 /* Timer Counter 0 */
40#define AT91_ID_TC1 18 /* Timer Counter 1 */
41#define AT91_ID_TC2 19 /* Timer Counter 2 */
42#define AT91_ID_TC3 20 /* Timer Counter 3 */
43#define AT91_ID_TC4 21 /* Timer Counter 4 */
44#define AT91_ID_TC5 22 /* Timer Counter 5 */
45#define AT91_ID_UHP 23 /* USB Host port */
46#define AT91_ID_EMAC 24 /* Ethernet MAC */
47#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
48#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
49#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
50#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
51#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
52#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
53#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
54
55
56/*
57 * Peripheral physical base addresses.
58 */
59#define AT91_BASE_TCB0 0xfffa0000
60#define AT91_BASE_TC0 0xfffa0000
61#define AT91_BASE_TC1 0xfffa0040
62#define AT91_BASE_TC2 0xfffa0080
63#define AT91_BASE_TCB1 0xfffa4000
64#define AT91_BASE_TC3 0xfffa4000
65#define AT91_BASE_TC4 0xfffa4040
66#define AT91_BASE_TC5 0xfffa4080
67#define AT91_BASE_UDP 0xfffb0000
68#define AT91_BASE_MCI 0xfffb4000
69#define AT91_BASE_TWI 0xfffb8000
70#define AT91_BASE_EMAC 0xfffbc000
71#define AT91_BASE_US0 0xfffc0000
72#define AT91_BASE_US1 0xfffc4000
73#define AT91_BASE_US2 0xfffc8000
74#define AT91_BASE_US3 0xfffcc000
75#define AT91_BASE_SSC0 0xfffd0000
76#define AT91_BASE_SSC1 0xfffd4000
77#define AT91_BASE_SSC2 0xfffd8000
78#define AT91_BASE_SPI 0xfffe0000
79#define AT91_BASE_SYS 0xfffff000
80
81
82/*
83 * PIO pin definitions (peripheral A/B multiplexing).
84 */
85#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */
86#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */
87#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */
88#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */
89#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */
90#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */
91#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */
92#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */
93#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */
94#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */
95#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */
96#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */
97#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */
98#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */
99#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */
100#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */
101#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */
102#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */
103#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */
104#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */
105#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */
106#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */
107#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */
108#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */
109#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */
110#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */
111#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */
112#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */
113#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */
114#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */
115#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */
116#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */
117#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */
118#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */
119#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */
120#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */
121#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */
122#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */
123#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */
124#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */
125#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */
126#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */
127#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
128#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */
129#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */
130#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */
131#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */
132#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */
133#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */
134#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */
135#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */
136#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */
137#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */
138#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */
139#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */
140#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */
141#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */
142#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */
143#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */
144#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */
145#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */
146#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */
147#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */
148#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */
149
150#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */
151#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */
152#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */
153#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */
154#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */
155#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */
156#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */
157#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */
158#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */
159#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */
160#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */
161#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */
162#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */
163#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */
164#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */
165#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */
166#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */
167#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */
168#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */
169#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */
170#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */
171#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */
172#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */
173#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */
174#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */
175#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */
176#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */
177#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */
178#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */
179#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */
180#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */
181#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */
182#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */
183#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */
184#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */
185#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */
186#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */
187#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */
188#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */
189#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */
190#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */
191#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */
192#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */
193#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */
194#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */
195#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */
196#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */
197#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */
198#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */
199#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */
200#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */
201
202#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */
203#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */
204#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */
205#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */
206#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */
207#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */
208#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */
209#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */
210#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */
211#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */
212#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */
213#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
214#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
215#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */
216
217#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */
218#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */
219#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */
220#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */
221#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */
222#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */
223#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */
224#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */
225#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */
226#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */
227#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */
228#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */
229#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */
230#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */
231#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */
232#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */
233#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */
234#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */
235#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */
236#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */
237#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */
238#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */
239#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */
240#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */
241#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */
242#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */
243#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */
244#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */
245#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */
246#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */
247#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */
248#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
249#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */
250#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */
251#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */
252#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */
253#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */
254#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */
255#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */
256#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */
257#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
258#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
259#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
260
261#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
new file mode 100644
index 000000000000..9bfffdbf1e0b
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -0,0 +1,328 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_SYS_H
17#define AT91RM9200_SYS_H
18
19/*
20 * Advanced Interrupt Controller.
21 */
22#define AT91_AIC 0x000
23
24#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
25#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
26#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
27#define AT91_AIC_SRCTYPE_LOW (0 << 5)
28#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
29#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
30#define AT91_AIC_SRCTYPE_RISING (3 << 5)
31
32#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
33#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
34#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
35#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
36#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
37
38#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
39#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
40#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
41#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
42#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
43
44#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
45#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
46#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
47#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
48#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
49#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
50#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
51#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
52#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
53
54
55/*
56 * Debug Unit.
57 */
58#define AT91_DBGU 0x200
59
60#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
61#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
62#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
63#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
64#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
65#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
66#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
67#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
68#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
69#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
70#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
71#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
72#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
73
74
75/*
76 * PIO Controllers.
77 */
78#define AT91_PIOA 0x400
79#define AT91_PIOB 0x600
80#define AT91_PIOC 0x800
81#define AT91_PIOD 0xa00
82
83#define PIO_PER 0x00 /* Enable Register */
84#define PIO_PDR 0x04 /* Disable Register */
85#define PIO_PSR 0x08 /* Status Register */
86#define PIO_OER 0x10 /* Output Enable Register */
87#define PIO_ODR 0x14 /* Output Disable Register */
88#define PIO_OSR 0x18 /* Output Status Register */
89#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
90#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
91#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
92#define PIO_SODR 0x30 /* Set Output Data Register */
93#define PIO_CODR 0x34 /* Clear Output Data Register */
94#define PIO_ODSR 0x38 /* Output Data Status Register */
95#define PIO_PDSR 0x3c /* Pin Data Status Register */
96#define PIO_IER 0x40 /* Interrupt Enable Register */
97#define PIO_IDR 0x44 /* Interrupt Disable Register */
98#define PIO_IMR 0x48 /* Interrupt Mask Register */
99#define PIO_ISR 0x4c /* Interrupt Status Register */
100#define PIO_MDER 0x50 /* Multi-driver Enable Register */
101#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
102#define PIO_MDSR 0x58 /* Multi-driver Status Register */
103#define PIO_PUDR 0x60 /* Pull-up Disable Register */
104#define PIO_PUER 0x64 /* Pull-up Enable Register */
105#define PIO_PUSR 0x68 /* Pull-up Status Register */
106#define PIO_ASR 0x70 /* Peripheral A Select Register */
107#define PIO_BSR 0x74 /* Peripheral B Select Register */
108#define PIO_ABSR 0x78 /* AB Status Register */
109#define PIO_OWER 0xa0 /* Output Write Enable Register */
110#define PIO_OWDR 0xa4 /* Output Write Disable Register */
111#define PIO_OWSR 0xa8 /* Output Write Status Register */
112
113#define AT91_PIO_P(n) (1 << (n))
114
115
116/*
117 * Power Management Controller.
118 */
119#define AT91_PMC 0xc00
120
121#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
122#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
123
124#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
125#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
126#define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */
127#define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */
128#define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */
129#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
130#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
131#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
132#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
133
134#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
135#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
136#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
137
138#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
139#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
140#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
141
142#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
143#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
144#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
145
146#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
147#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
148#define AT91_PMC_DIV (0xff << 0) /* Divider */
149#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
150#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
151#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
152#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
153
154#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
155#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
156#define AT91_PMC_CSS_SLOW (0 << 0)
157#define AT91_PMC_CSS_MAIN (1 << 0)
158#define AT91_PMC_CSS_PLLA (2 << 0)
159#define AT91_PMC_CSS_PLLB (3 << 0)
160#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
161#define AT91_PMC_PRES_1 (0 << 2)
162#define AT91_PMC_PRES_2 (1 << 2)
163#define AT91_PMC_PRES_4 (2 << 2)
164#define AT91_PMC_PRES_8 (3 << 2)
165#define AT91_PMC_PRES_16 (4 << 2)
166#define AT91_PMC_PRES_32 (5 << 2)
167#define AT91_PMC_PRES_64 (6 << 2)
168#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
169#define AT91_PMC_MDIV_1 (0 << 8)
170#define AT91_PMC_MDIV_2 (1 << 8)
171#define AT91_PMC_MDIV_3 (2 << 8)
172#define AT91_PMC_MDIV_4 (3 << 8)
173
174#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
175#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
176#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
177#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
178#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
179#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
180#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
181#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
182#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
183#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
184#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
185#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
186#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
187
188
189/*
190 * System Timer.
191 */
192#define AT91_ST 0xd00
193
194#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
195#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
196#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
197#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
198#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
199#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
200#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
201#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
202#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
203#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
204#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
205#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
206#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
207#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
208#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
209#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
210#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
211#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
212#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
213#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
214#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
215#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
216
217
218/*
219 * Real-time Clock.
220 */
221#define AT91_RTC 0xe00
222
223#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
224#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
225#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
226#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
227#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
228#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
229#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
230#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
231#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
232#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
233#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
234#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
235
236#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
237#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
238
239#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
240#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
241#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
242#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
243#define At91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
244
245#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
246#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
247#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
248#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
249#define AT91_RTC_DAY (7 << 21) /* Current Day */
250#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
251
252#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
253#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
254#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
255#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
256
257#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
258#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
259#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
260
261#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
262#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
263#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
264#define AT91_RTC_SECEV (1 << 2) /* Second Event */
265#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
266#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
267
268#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
269#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
270#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
271#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
272
273#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
274#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
275#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
276#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
277#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
278
279
280/*
281 * Memory Controller.
282 */
283#define AT91_MC 0xf00
284
285#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
286#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
287
288#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
289#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
290#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
291
292/* External Bus Interface (EBI) registers */
293#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
294#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
295#define AT91_EBI_CS0A_SMC (0 << 0)
296#define AT91_EBI_CS0A_BFC (1 << 0)
297#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
298#define AT91_EBI_CS1A_SMC (0 << 1)
299#define AT91_EBI_CS1A_SDRAMC (1 << 1)
300#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
301#define AT91_EBI_CS3A_SMC (0 << 3)
302#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
303#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
304#define AT91_EBI_CS4A_SMC (0 << 4)
305#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
306#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
307#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
308
309/* Static Memory Controller (SMC) registers */
310#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
311#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
312#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
313#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
314#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
315#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
316#define AT91_SMC_DBW_16 (1 << 13)
317#define AT91_SMC_DBW_8 (2 << 13)
318#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
319#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
320#define AT91_SMC_ACSS_STD (0 << 16)
321#define AT91_SMC_ACSS_1 (1 << 16)
322#define AT91_SMC_ACSS_2 (2 << 16)
323#define AT91_SMC_ACSS_3 (3 << 16)
324#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
325#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
326
327
328#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
new file mode 100644
index 000000000000..2e7d1139a799
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -0,0 +1,80 @@
1/*
2 * include/asm-arm/arch-at91rm9200/board.h
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * These are data structures found in platform_device.dev.platform_data,
23 * and describing board-specfic data needed by drivers. For example,
24 * which pin is used for a given GPIO role.
25 *
26 * In 2.6, drivers should strongly avoid board-specific knowledge so
27 * that supporting new boards normally won't require driver patches.
28 * Most board-specific knowledge should be in arch/.../board-*.c files.
29 */
30
31#ifndef __ASM_ARCH_BOARD_H
32#define __ASM_ARCH_BOARD_H
33
34 /* Clocks */
35extern unsigned long at91_master_clock;
36
37 /* Serial Port */
38extern int at91_serial_map[AT91_NR_UART];
39extern int at91_console_port;
40
41 /* USB Device */
42struct at91_udc_data {
43 u8 vbus_pin; /* high == host powering us */
44 u8 pullup_pin; /* high == D+ pulled up */
45};
46extern void __init at91_add_device_udc(struct at91_udc_data *data);
47
48 /* Compact Flash */
49struct at91_cf_data {
50 u8 irq_pin; /* I/O IRQ */
51 u8 det_pin; /* Card detect */
52 u8 vcc_pin; /* power switching */
53 u8 rst_pin; /* card reset */
54};
55extern void __init at91_add_device_cf(struct at91_cf_data *data);
56
57 /* MMC / SD */
58struct at91_mmc_data {
59 u8 det_pin; /* card detect IRQ */
60 unsigned is_b:1; /* uses B side (vs A) */
61 unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
62 u8 wp_pin; /* (SD) writeprotect detect */
63 u8 vcc_pin; /* power switching (high == on) */
64};
65extern void __init at91_add_device_mmc(struct at91_mmc_data *data);
66
67 /* Ethernet */
68struct at91_eth_data {
69 u8 phy_irq_pin; /* PHY IRQ */
70 u8 is_rmii; /* using RMII interface? */
71};
72extern void __init at91_add_device_eth(struct at91_eth_data *data);
73
74 /* USB Host */
75struct at91_usbh_data {
76 u8 ports; /* number of ports on root hub */
77};
78extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
79
80#endif
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S
new file mode 100644
index 000000000000..f496b54c4c3e
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/debug-macro.S
@@ -0,0 +1,38 @@
1/*
2 * include/asm-arm/arch-at91rm9200/debug-macro.S
3 *
4 * Copyright (C) 2003-2005 SAN People
5 *
6 * Debugging macro include header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <asm/hardware.h>
15
16 .macro addruart,rx
17 mrc p15, 0, \rx, c1, c0
18 tst \rx, #1 @ MMU enabled?
19 ldreq \rx, =AT91_BASE_SYS @ System peripherals (phys address)
20 ldrne \rx, =AT91_VA_BASE_SYS @ System peripherals (virt address)
21 .endm
22
23 .macro senduart,rd,rx
24 strb \rd, [\rx, #AT91_DBGU_THR] @ Write to Transmitter Holding Register
25 .endm
26
27 .macro waituart,rd,rx
281001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register
29 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
30 beq 1001b
31 .endm
32
33 .macro busyuart,rd,rx
341001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register
35 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
36 beq 1001b
37 .endm
38
diff --git a/include/asm-arm/arch-at91rm9200/dma.h b/include/asm-arm/arch-at91rm9200/dma.h
new file mode 100644
index 000000000000..6738bdd74b22
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/dma.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-arm/arch-at91rm9200/dma.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24#define MAX_DMA_ADDRESS 0xffffffff
25#define MAX_DMA_CHANNELS 0
26
27#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S
new file mode 100644
index 000000000000..61a326e94909
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/entry-macro.S
@@ -0,0 +1,25 @@
1/*
2 * include/asm-arm/arch-at91rm9200/entry-macro.S
3 *
4 * Copyright (C) 2003-2005 SAN People
5 *
6 * Low-level IRQ helper macros for AT91RM9200 platforms
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <asm/hardware.h>
14
15 .macro disable_fiq
16 .endm
17
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals
20 ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
21 ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number
22 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
23 streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now.
24 .endm
25
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
new file mode 100644
index 000000000000..0f0a61e2f129
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -0,0 +1,193 @@
1/*
2 * include/asm-arm/arch-at91rm9200/gpio.h
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
14#define __ASM_ARCH_AT91RM9200_GPIO_H
15
16#define PIN_BASE NR_AIC_IRQS
17
18#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */
19#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */
20
21/* these pin numbers double as IRQ numbers, like AT91_ID_* values */
22
23#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
24#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
25#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
26#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
27#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
28
29#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
30#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
31#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
32#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
33#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
34
35#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
36#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
37#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
38#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
39#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
40
41#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
42#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
43#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
44#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
45#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
46
47#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
48#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
49#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
50#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
51#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
52
53#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
54#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
55#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
56#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
57#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
58
59#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
60#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
61
62#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
63#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
64#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
65#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
66#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
67
68#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
69#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
70#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
71#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
72#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
73
74#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
75#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
76#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
77#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
78#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
79
80#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
81#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
82#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
83#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
84#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
85
86#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
87#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
88#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
89#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
90#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
91
92#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
93#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
94#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
95#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
96#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
97
98#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
99#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
100
101#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
102#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
103#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
104#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
105#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
106
107#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
108#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
109#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
110#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
111#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
112
113#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
114#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
115#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
116#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
117#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
118
119#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
120#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
121#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
122#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
123#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
124
125#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
126#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
127#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
128#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
129#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
130
131#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
132#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
133#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
134#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
135#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
136
137#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
138#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
139
140#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
141#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
142#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
143#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
144#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
145
146#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
147#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
148#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
149#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
150#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
151
152#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
153#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
154#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
155#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
156#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
157
158#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
159#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
160#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
161#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
162#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
163
164#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
165#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
166#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
167#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
168#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
169
170#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
171#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
172#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
173#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
174#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
175
176#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
177#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
178
179#ifndef __ASSEMBLY__
180/* setup setup routines, called from board init or driver probe() */
181extern int at91_set_A_periph(unsigned pin, int use_pullup);
182extern int at91_set_B_periph(unsigned pin, int use_pullup);
183extern int at91_set_gpio_input(unsigned pin, int use_pullup);
184extern int at91_set_gpio_output(unsigned pin, int value);
185extern int at91_set_deglitch(unsigned pin, int is_on);
186
187/* callable at any time */
188extern int at91_set_gpio_value(unsigned pin, int value);
189extern int at91_get_gpio_value(unsigned pin);
190#endif
191
192#endif
193
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
new file mode 100644
index 000000000000..2646c01f8e97
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -0,0 +1,92 @@
1/*
2 * include/asm-arm/arch-at91rm9200/hardware.h
3 *
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#ifndef __ASM_ARCH_HARDWARE_H
15#define __ASM_ARCH_HARDWARE_H
16
17#include <asm/sizes.h>
18
19#include <asm/arch/at91rm9200.h>
20#include <asm/arch/at91rm9200_sys.h>
21
22/*
23 * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
24 * to 0xFEFA0000 .. 0xFF000000. (384Kb)
25 */
26#define AT91_IO_PHYS_BASE 0xFFFA0000
27#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
28#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
29
30 /* Convert a physical IO address to virtual IO address */
31#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
32
33/*
34 * Virtual to Physical Address mapping for IO devices.
35 */
36#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
37#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91_BASE_SPI)
38#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91_BASE_SSC2)
39#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91_BASE_SSC1)
40#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91_BASE_SSC0)
41#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91_BASE_US3)
42#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91_BASE_US2)
43#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91_BASE_US1)
44#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91_BASE_US0)
45#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91_BASE_EMAC)
46#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91_BASE_TWI)
47#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91_BASE_MCI)
48#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91_BASE_UDP)
49#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91_BASE_TCB1)
50#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0)
51
52/* Internal SRAM */
53#define AT91_BASE_SRAM 0x00200000 /* Internal SRAM base address */
54#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */
55
56/* Serial ports */
57#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */
58
59/* FLASH */
60#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */
61
62/* SDRAM */
63#define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */
64
65/* SmartMedia */
66#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */
67
68/* Multi-Master Memory controller */
69#define AT91_UHP_BASE 0x00300000 /* USB Host controller */
70
71/* Clocks */
72#define AT91_SLOW_CLOCK 32768 /* slow clock */
73
74#ifndef __ASSEMBLY__
75#include <asm/io.h>
76
77static inline unsigned int at91_sys_read(unsigned int reg_offset)
78{
79 void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
80
81 return readl(addr + reg_offset);
82}
83
84static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
85{
86 void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
87
88 writel(value, addr + reg_offset);
89}
90#endif
91
92#endif
diff --git a/include/asm-arm/arch-at91rm9200/io.h b/include/asm-arm/arch-at91rm9200/io.h
new file mode 100644
index 000000000000..23e670d85c9d
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/io.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-at91rm9200/io.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_IO_H
22#define __ASM_ARCH_IO_H
23
24#include <asm/arch/at91rm9200.h>
25#include <asm/io.h>
26
27#define IO_SPACE_LIMIT 0xFFFFFFFF
28
29#define __io(a) ((void __iomem *)(a))
30#define __mem_pci(a) (a)
31
32
33#endif
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
new file mode 100644
index 000000000000..27b0497f1b36
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -0,0 +1,52 @@
1/*
2 * include/asm-arm/arch-at91rm9200/irqs.h
3 *
4 * Copyright (C) 2004 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_IRQS_H
22#define __ASM_ARCH_IRQS_H
23
24#define NR_AIC_IRQS 32
25
26
27/*
28 * Acknowledge interrupt with AIC after interrupt has been handled.
29 * (by kernel/irq.c)
30 */
31#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
32
33
34/*
35 * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h
36 * for IRQs handled directly through the AIC, or else the AT91_PIN_*
37 * symbols in gpio.h for ones handled indirectly as GPIOs.
38 * We make provision for 4 banks of GPIO.
39 */
40#include <asm/arch/gpio.h>
41
42#define NR_IRQS (NR_AIC_IRQS + (4 * 32))
43
44
45#ifndef __ASSEMBLY__
46/*
47 * Initialize the IRQ controller.
48 */
49extern void at91rm9200_init_irq(unsigned int priority[]);
50#endif
51
52#endif
diff --git a/include/asm-arm/arch-at91rm9200/memory.h b/include/asm-arm/arch-at91rm9200/memory.h
new file mode 100644
index 000000000000..462f1f0ad67c
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/memory.h
@@ -0,0 +1,41 @@
1/*
2 * include/asm-arm/arch-at91rm9200/memory.h
3 *
4 * Copyright (C) 2004 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_MEMORY_H
22#define __ASM_ARCH_MEMORY_H
23
24#include <asm/arch/hardware.h>
25
26#define PHYS_OFFSET (AT91_SDRAM_BASE)
27
28
29/*
30 * Virtual view <-> DMA view memory address translations
31 * virt_to_bus: Used to translate the virtual address to an
32 * address suitable to be passed to set_dma_addr
33 * bus_to_virt: Used to convert an address for DMA operations
34 * to an address that the kernel can use.
35 */
36#define __virt_to_bus__is_a_macro
37#define __virt_to_bus(x) __virt_to_phys(x)
38#define __bus_to_virt__is_a_macro
39#define __bus_to_virt(x) __phys_to_virt(x)
40
41#endif
diff --git a/include/asm-arm/arch-at91rm9200/param.h b/include/asm-arm/arch-at91rm9200/param.h
new file mode 100644
index 000000000000..9480f8446852
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/param.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-arm/arch-at91rm9200/param.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_PARAM_H
22#define __ASM_ARCH_PARAM_H
23
24/*
25 * We use default params
26 */
27
28#endif
diff --git a/include/asm-arm/arch-at91rm9200/pio.h b/include/asm-arm/arch-at91rm9200/pio.h
new file mode 100644
index 000000000000..a89501b4a703
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/pio.h
@@ -0,0 +1,115 @@
1/*
2 * include/asm-arm/arch-at91rm9200/pio.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#ifndef __ASM_ARCH_PIO_H
14#define __ASM_ARCH_PIO_H
15
16#include <asm/arch/hardware.h>
17
18static inline void AT91_CfgPIO_USART0(void) {
19 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA17_TXD0 | AT91_PA18_RXD0 | AT91_PA20_CTS0);
20
21 /*
22 * Errata #39 - RTS0 is not internally connected to PA21. We need to drive
23 * the pin manually. Default is off (RTS is active low).
24 */
25 at91_sys_write(AT91_PIOA + PIO_PER, AT91_PA21_RTS0);
26 at91_sys_write(AT91_PIOA + PIO_OER, AT91_PA21_RTS0);
27 at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
28}
29
30static inline void AT91_CfgPIO_USART1(void) {
31 at91_sys_write(AT91_PIOB + PIO_PDR, AT91_PB18_RI1 | AT91_PB19_DTR1
32 | AT91_PB20_TXD1 | AT91_PB21_RXD1 | AT91_PB23_DCD1
33 | AT91_PB24_CTS1 | AT91_PB25_DSR1 | AT91_PB26_RTS1);
34}
35
36static inline void AT91_CfgPIO_USART2(void) {
37 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA22_RXD2 | AT91_PA23_TXD2);
38}
39
40static inline void AT91_CfgPIO_USART3(void) {
41 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
42 at91_sys_write(AT91_PIOA + PIO_BSR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
43}
44
45static inline void AT91_CfgPIO_DBGU(void) {
46 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA31_DTXD | AT91_PA30_DRXD);
47}
48
49/*
50 * Enable the Two-Wire interface.
51 */
52static inline void AT91_CfgPIO_TWI(void) {
53 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA25_TWD | AT91_PA26_TWCK);
54 at91_sys_write(AT91_PIOA + PIO_ASR, AT91_PA25_TWD | AT91_PA26_TWCK);
55 at91_sys_write(AT91_PIOA + PIO_MDER, AT91_PA25_TWD | AT91_PA26_TWCK); /* open drain */
56}
57
58/*
59 * Enable the Serial Peripheral Interface.
60 */
61static inline void AT91_CfgPIO_SPI(void) {
62 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA0_MISO | AT91_PA1_MOSI | AT91_PA2_SPCK);
63}
64
65static inline void AT91_CfgPIO_SPI_CS0(void) {
66 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA3_NPCS0);
67}
68
69static inline void AT91_CfgPIO_SPI_CS1(void) {
70 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA4_NPCS1);
71}
72
73static inline void AT91_CfgPIO_SPI_CS2(void) {
74 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_NPCS2);
75}
76
77static inline void AT91_CfgPIO_SPI_CS3(void) {
78 at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA6_NPCS3);
79}
80
81/*
82 * Select the DataFlash card.
83 */
84static inline void AT91_CfgPIO_DataFlashCard(void) {
85 at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(7));
86 at91_sys_write(AT91_PIOB + PIO_OER, AT91_PIO_P(7));
87 at91_sys_write(AT91_PIOB + PIO_CODR, AT91_PIO_P(7));
88}
89
90/*
91 * Enable NAND Flash (SmartMedia) interface.
92 */
93static inline void AT91_CfgPIO_SmartMedia(void) {
94 /* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */
95 at91_sys_write(AT91_PIOC + PIO_ASR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
96 at91_sys_write(AT91_PIOC + PIO_PDR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
97
98 /* Configure PC2 as input (signal READY of the SmartMedia) */
99 at91_sys_write(AT91_PIOC + PIO_PER, AT91_PC2_BFAVD); /* enable direct output enable */
100 at91_sys_write(AT91_PIOC + PIO_ODR, AT91_PC2_BFAVD); /* disable output */
101
102 /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
103 at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(1)); /* enable direct output enable */
104 at91_sys_write(AT91_PIOB + PIO_ODR, AT91_PIO_P(1)); /* disable output */
105}
106
107static inline int AT91_PIO_SmartMedia_RDY(void) {
108 return (at91_sys_read(AT91_PIOC + PIO_PDSR) & AT91_PIO_P(2)) ? 1 : 0;
109}
110
111static inline int AT91_PIO_SmartMedia_CardDetect(void) {
112 return (at91_sys_read(AT91_PIOB + PIO_PDSR) & AT91_PIO_P(1)) ? 1 : 0;
113}
114
115#endif
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h
new file mode 100644
index 000000000000..29c42655f05c
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/system.h
@@ -0,0 +1,51 @@
1/*
2 * include/asm-arm/arch-at91rm9200/system.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24#include <asm/arch/hardware.h>
25
26static inline void arch_idle(void)
27{
28 /*
29 * Disable the processor clock. The processor will be automatically
30 * re-enabled by an interrupt or by a reset.
31 */
32// at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
33
34 /*
35 * Set the processor (CP15) into 'Wait for Interrupt' mode.
36 * Unlike disabling the processor clock via the PMC (above)
37 * this allows the processor to be woken via JTAG.
38 */
39 cpu_do_idle();
40}
41
42static inline void arch_reset(char mode)
43{
44 /*
45 * Perform a hardware reset with the use of the Watchdog timer.
46 */
47 at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
48 at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
49}
50
51#endif
diff --git a/include/asm-arm/arch-at91rm9200/timex.h b/include/asm-arm/arch-at91rm9200/timex.h
new file mode 100644
index 000000000000..3f112dd12587
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/timex.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-arm/arch-at91rm9200/timex.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_TIMEX_H
22#define __ASM_ARCH_TIMEX_H
23
24#include <asm/arch/hardware.h>
25
26#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
27
28#endif
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
new file mode 100644
index 000000000000..b30dd5520713
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -0,0 +1,55 @@
1/*
2 * include/asm-arm/arch-at91rm9200/uncompress.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_UNCOMPRESS_H
22#define __ASM_ARCH_UNCOMPRESS_H
23
24#include <asm/arch/hardware.h>
25
26/*
27 * The following code assumes the serial port has already been
28 * initialized by the bootloader. We search for the first enabled
29 * port in the most probable order. If you didn't setup a port in
30 * your bootloader then nothing will appear (which might be desired).
31 *
32 * This does not append a newline
33 */
34static void putstr(const char *s)
35{
36 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
37
38 while (*s) {
39 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
40 __raw_writel(*s, sys + AT91_DBGU_THR);
41 if (*s == '\n') {
42 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
43 __raw_writel('\r', sys + AT91_DBGU_THR);
44 }
45 s++;
46 }
47 /* wait for transmission to complete */
48 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) { barrier(); }
49}
50
51#define arch_decomp_setup()
52
53#define arch_decomp_wdog()
54
55#endif
diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h
new file mode 100644
index 000000000000..34d9718feb90
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/vmalloc.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-at91rm9200/vmalloc.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_VMALLOC_H
22#define __ASM_ARCH_VMALLOC_H
23
24#define VMALLOC_END (AT91_IO_VIRT_BASE & PGDIR_MASK)
25
26#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 10:32:16 -0500