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-rw-r--r--include/asm-avr32/arch-at32ap/at32ap700x.h49
-rw-r--r--include/asm-avr32/arch-at32ap/board.h121
-rw-r--r--include/asm-avr32/arch-at32ap/cpu.h35
-rw-r--r--include/asm-avr32/arch-at32ap/gpio.h45
-rw-r--r--include/asm-avr32/arch-at32ap/init.h18
-rw-r--r--include/asm-avr32/arch-at32ap/io.h39
-rw-r--r--include/asm-avr32/arch-at32ap/irq.h14
-rw-r--r--include/asm-avr32/arch-at32ap/pm.h51
-rw-r--r--include/asm-avr32/arch-at32ap/portmux.h29
-rw-r--r--include/asm-avr32/arch-at32ap/smc.h113
-rw-r--r--include/asm-avr32/arch-at32ap/sram.h30
-rw-r--r--include/asm-m68k/unistd.h8
-rw-r--r--include/linux/harrier_defs.h212
-rw-r--r--include/linux/pci.h11
-rw-r--r--include/linux/pci_ids.h2
-rw-r--r--include/linux/slub_def.h1
16 files changed, 15 insertions, 763 deletions
diff --git a/include/asm-avr32/arch-at32ap/at32ap700x.h b/include/asm-avr32/arch-at32ap/at32ap700x.h
deleted file mode 100644
index d18a3053be0d..000000000000
--- a/include/asm-avr32/arch-at32ap/at32ap700x.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Pin definitions for AT32AP7000.
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARCH_AT32AP700X_H__
11#define __ASM_ARCH_AT32AP700X_H__
12
13#define GPIO_PERIPH_A 0
14#define GPIO_PERIPH_B 1
15
16/*
17 * Pin numbers identifying specific GPIO pins on the chip. They can
18 * also be converted to IRQ numbers by passing them through
19 * gpio_to_irq().
20 */
21#define GPIO_PIOA_BASE (0)
22#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
23#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
24#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
25#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
26
27#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
28#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
29#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
30#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
31#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
32
33
34/*
35 * DMAC peripheral hardware handshaking interfaces, used with dw_dmac
36 */
37#define DMAC_MCI_RX 0
38#define DMAC_MCI_TX 1
39#define DMAC_DAC_TX 2
40#define DMAC_AC97_A_RX 3
41#define DMAC_AC97_A_TX 4
42#define DMAC_AC97_B_RX 5
43#define DMAC_AC97_B_TX 6
44#define DMAC_DMAREQ_0 7
45#define DMAC_DMAREQ_1 8
46#define DMAC_DMAREQ_2 9
47#define DMAC_DMAREQ_3 10
48
49#endif /* __ASM_ARCH_AT32AP700X_H__ */
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
deleted file mode 100644
index e60e9076544d..000000000000
--- a/include/asm-avr32/arch-at32ap/board.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Platform data definitions.
3 */
4#ifndef __ASM_ARCH_BOARD_H
5#define __ASM_ARCH_BOARD_H
6
7#include <linux/types.h>
8
9#define GPIO_PIN_NONE (-1)
10
11/*
12 * Clock rates for various on-board oscillators. The number of entries
13 * in this array is chip-dependent.
14 */
15extern unsigned long at32_board_osc_rates[];
16
17/* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
18void at32_add_system_devices(void);
19
20#define ATMEL_MAX_UART 4
21extern struct platform_device *atmel_default_console_device;
22
23struct atmel_uart_data {
24 short use_dma_tx; /* use transmit DMA? */
25 short use_dma_rx; /* use receive DMA? */
26 void __iomem *regs; /* virtual base address, if any */
27};
28void at32_map_usart(unsigned int hw_id, unsigned int line);
29struct platform_device *at32_add_device_usart(unsigned int id);
30
31struct eth_platform_data {
32 u32 phy_mask;
33 u8 is_rmii;
34};
35struct platform_device *
36at32_add_device_eth(unsigned int id, struct eth_platform_data *data);
37
38struct spi_board_info;
39struct platform_device *
40at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
41
42struct atmel_lcdfb_info;
43struct platform_device *
44at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
45 unsigned long fbmem_start, unsigned long fbmem_len,
46 unsigned int pin_config);
47
48struct usba_platform_data;
49struct platform_device *
50at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
51
52struct ide_platform_data {
53 u8 cs;
54};
55struct platform_device *
56at32_add_device_ide(unsigned int id, unsigned int extint,
57 struct ide_platform_data *data);
58
59/* mask says which PWM channels to mux */
60struct platform_device *at32_add_device_pwm(u32 mask);
61
62/* depending on what's hooked up, not all SSC pins will be used */
63#define ATMEL_SSC_TK 0x01
64#define ATMEL_SSC_TF 0x02
65#define ATMEL_SSC_TD 0x04
66#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
67
68#define ATMEL_SSC_RK 0x10
69#define ATMEL_SSC_RF 0x20
70#define ATMEL_SSC_RD 0x40
71#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
72
73struct platform_device *
74at32_add_device_ssc(unsigned int id, unsigned int flags);
75
76struct i2c_board_info;
77struct platform_device *at32_add_device_twi(unsigned int id,
78 struct i2c_board_info *b,
79 unsigned int n);
80
81struct mci_platform_data;
82struct platform_device *
83at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
84
85struct ac97c_platform_data {
86 unsigned short dma_rx_periph_id;
87 unsigned short dma_tx_periph_id;
88 unsigned short dma_controller_id;
89 int reset_pin;
90};
91struct platform_device *
92at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data);
93
94struct platform_device *at32_add_device_abdac(unsigned int id);
95struct platform_device *at32_add_device_psif(unsigned int id);
96
97struct cf_platform_data {
98 int detect_pin;
99 int reset_pin;
100 int vcc_pin;
101 int ready_pin;
102 u8 cs;
103};
104struct platform_device *
105at32_add_device_cf(unsigned int id, unsigned int extint,
106 struct cf_platform_data *data);
107
108/* NAND / SmartMedia */
109struct atmel_nand_data {
110 int enable_pin; /* chip enable */
111 int det_pin; /* card detect */
112 int rdy_pin; /* ready/busy */
113 u8 ale; /* address line number connected to ALE */
114 u8 cle; /* address line number connected to CLE */
115 u8 bus_width_16; /* buswidth is 16 bit */
116 struct mtd_partition *(*partition_info)(int size, int *num_partitions);
117};
118struct platform_device *
119at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
120
121#endif /* __ASM_ARCH_BOARD_H */
diff --git a/include/asm-avr32/arch-at32ap/cpu.h b/include/asm-avr32/arch-at32ap/cpu.h
deleted file mode 100644
index 44d0bfa1f409..000000000000
--- a/include/asm-avr32/arch-at32ap/cpu.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * AVR32 and (fake) AT91 CPU identification
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARCH_CPU_H
11#define __ASM_ARCH_CPU_H
12
13/*
14 * Only AT32AP7000 is defined for now. We can identify the specific
15 * chip at runtime, but I'm not sure if it's really worth it.
16 */
17#ifdef CONFIG_CPU_AT32AP700X
18# define cpu_is_at32ap7000() (1)
19#else
20# define cpu_is_at32ap7000() (0)
21#endif
22
23/*
24 * Since this is AVR32, we will never run on any AT91 CPU. But these
25 * definitions may reduce clutter in common drivers.
26 */
27#define cpu_is_at91rm9200() (0)
28#define cpu_is_at91sam9xe() (0)
29#define cpu_is_at91sam9260() (0)
30#define cpu_is_at91sam9261() (0)
31#define cpu_is_at91sam9263() (0)
32#define cpu_is_at91sam9rl() (0)
33#define cpu_is_at91cap9() (0)
34
35#endif /* __ASM_ARCH_CPU_H */
diff --git a/include/asm-avr32/arch-at32ap/gpio.h b/include/asm-avr32/arch-at32ap/gpio.h
deleted file mode 100644
index 0180f584ef03..000000000000
--- a/include/asm-avr32/arch-at32ap/gpio.h
+++ /dev/null
@@ -1,45 +0,0 @@
1#ifndef __ASM_AVR32_ARCH_GPIO_H
2#define __ASM_AVR32_ARCH_GPIO_H
3
4#include <linux/compiler.h>
5#include <asm/irq.h>
6
7
8/* Some GPIO chips can manage IRQs; some can't. The exact numbers can
9 * be changed if needed, but for the moment they're not configurable.
10 */
11#define ARCH_NR_GPIOS (NR_GPIO_IRQS + 2 * 32)
12
13
14/* Arch-neutral GPIO API, supporting both "native" and external GPIOs. */
15#include <asm-generic/gpio.h>
16
17static inline int gpio_get_value(unsigned int gpio)
18{
19 return __gpio_get_value(gpio);
20}
21
22static inline void gpio_set_value(unsigned int gpio, int value)
23{
24 __gpio_set_value(gpio, value);
25}
26
27static inline int gpio_cansleep(unsigned int gpio)
28{
29 return __gpio_cansleep(gpio);
30}
31
32
33static inline int gpio_to_irq(unsigned int gpio)
34{
35 if (gpio < NR_GPIO_IRQS)
36 return gpio + GPIO_IRQ_BASE;
37 return -EINVAL;
38}
39
40static inline int irq_to_gpio(unsigned int irq)
41{
42 return irq - GPIO_IRQ_BASE;
43}
44
45#endif /* __ASM_AVR32_ARCH_GPIO_H */
diff --git a/include/asm-avr32/arch-at32ap/init.h b/include/asm-avr32/arch-at32ap/init.h
deleted file mode 100644
index bc40e3d46150..000000000000
--- a/include/asm-avr32/arch-at32ap/init.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * AT32AP platform initialization calls.
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_AVR32_AT32AP_INIT_H__
11#define __ASM_AVR32_AT32AP_INIT_H__
12
13void setup_platform(void);
14void setup_board(void);
15
16void at32_setup_serial_console(unsigned int usart_id);
17
18#endif /* __ASM_AVR32_AT32AP_INIT_H__ */
diff --git a/include/asm-avr32/arch-at32ap/io.h b/include/asm-avr32/arch-at32ap/io.h
deleted file mode 100644
index 4ec6abc68ea3..000000000000
--- a/include/asm-avr32/arch-at32ap/io.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
2#define __ASM_AVR32_ARCH_AT32AP_IO_H
3
4/* For "bizarre" halfword swapping */
5#include <linux/byteorder/swabb.h>
6
7#if defined(CONFIG_AP700X_32_BIT_SMC)
8# define __swizzle_addr_b(addr) (addr ^ 3UL)
9# define __swizzle_addr_w(addr) (addr ^ 2UL)
10# define __swizzle_addr_l(addr) (addr)
11# define ioswabb(a, x) (x)
12# define ioswabw(a, x) (x)
13# define ioswabl(a, x) (x)
14# define __mem_ioswabb(a, x) (x)
15# define __mem_ioswabw(a, x) swab16(x)
16# define __mem_ioswabl(a, x) swab32(x)
17#elif defined(CONFIG_AP700X_16_BIT_SMC)
18# define __swizzle_addr_b(addr) (addr ^ 1UL)
19# define __swizzle_addr_w(addr) (addr)
20# define __swizzle_addr_l(addr) (addr)
21# define ioswabb(a, x) (x)
22# define ioswabw(a, x) (x)
23# define ioswabl(a, x) swahw32(x)
24# define __mem_ioswabb(a, x) (x)
25# define __mem_ioswabw(a, x) swab16(x)
26# define __mem_ioswabl(a, x) swahb32(x)
27#else
28# define __swizzle_addr_b(addr) (addr)
29# define __swizzle_addr_w(addr) (addr)
30# define __swizzle_addr_l(addr) (addr)
31# define ioswabb(a, x) (x)
32# define ioswabw(a, x) swab16(x)
33# define ioswabl(a, x) swab32(x)
34# define __mem_ioswabb(a, x) (x)
35# define __mem_ioswabw(a, x) (x)
36# define __mem_ioswabl(a, x) (x)
37#endif
38
39#endif /* __ASM_AVR32_ARCH_AT32AP_IO_H */
diff --git a/include/asm-avr32/arch-at32ap/irq.h b/include/asm-avr32/arch-at32ap/irq.h
deleted file mode 100644
index 608e350368c7..000000000000
--- a/include/asm-avr32/arch-at32ap/irq.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef __ASM_AVR32_ARCH_IRQ_H
2#define __ASM_AVR32_ARCH_IRQ_H
3
4#define EIM_IRQ_BASE NR_INTERNAL_IRQS
5#define NR_EIM_IRQS 32
6#define AT32_EXTINT(n) (EIM_IRQ_BASE + (n))
7
8#define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS)
9#define NR_GPIO_CTLR (5 /*internal*/ + 1 /*external*/)
10#define NR_GPIO_IRQS (NR_GPIO_CTLR * 32)
11
12#define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS)
13
14#endif /* __ASM_AVR32_ARCH_IRQ_H */
diff --git a/include/asm-avr32/arch-at32ap/pm.h b/include/asm-avr32/arch-at32ap/pm.h
deleted file mode 100644
index 979b355b77b6..000000000000
--- a/include/asm-avr32/arch-at32ap/pm.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * AVR32 AP Power Management.
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_AVR32_ARCH_PM_H
11#define __ASM_AVR32_ARCH_PM_H
12
13/* Possible arguments to the "sleep" instruction */
14#define CPU_SLEEP_IDLE 0
15#define CPU_SLEEP_FROZEN 1
16#define CPU_SLEEP_STANDBY 2
17#define CPU_SLEEP_STOP 3
18#define CPU_SLEEP_STATIC 5
19
20#ifndef __ASSEMBLY__
21extern void cpu_enter_idle(void);
22extern void cpu_enter_standby(unsigned long sdramc_base);
23
24extern bool disable_idle_sleep;
25
26static inline void cpu_disable_idle_sleep(void)
27{
28 disable_idle_sleep = true;
29}
30
31static inline void cpu_enable_idle_sleep(void)
32{
33 disable_idle_sleep = false;
34}
35
36static inline void cpu_idle_sleep(void)
37{
38 /*
39 * If we're using the COUNT and COMPARE registers for
40 * timekeeping, we can't use the IDLE state.
41 */
42 if (disable_idle_sleep)
43 cpu_relax();
44 else
45 cpu_enter_idle();
46}
47
48void intc_set_suspend_handler(unsigned long offset);
49#endif
50
51#endif /* __ASM_AVR32_ARCH_PM_H */
diff --git a/include/asm-avr32/arch-at32ap/portmux.h b/include/asm-avr32/arch-at32ap/portmux.h
deleted file mode 100644
index b1abe6b4e4ef..000000000000
--- a/include/asm-avr32/arch-at32ap/portmux.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * AT32 portmux interface.
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARCH_PORTMUX_H__
11#define __ASM_ARCH_PORTMUX_H__
12
13/*
14 * Set up pin multiplexing, called from board init only.
15 *
16 * The following flags determine the initial state of the pin.
17 */
18#define AT32_GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */
19#define AT32_GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */
20#define AT32_GPIOF_HIGH 0x00000004 /* (OUT) Set output high */
21#define AT32_GPIOF_DEGLITCH 0x00000008 /* (IN) Filter glitches */
22#define AT32_GPIOF_MULTIDRV 0x00000010 /* Enable multidriver option */
23
24void at32_select_periph(unsigned int pin, unsigned int periph,
25 unsigned long flags);
26void at32_select_gpio(unsigned int pin, unsigned long flags);
27void at32_reserve_pin(unsigned int pin);
28
29#endif /* __ASM_ARCH_PORTMUX_H__ */
diff --git a/include/asm-avr32/arch-at32ap/smc.h b/include/asm-avr32/arch-at32ap/smc.h
deleted file mode 100644
index c98eea44a70a..000000000000
--- a/include/asm-avr32/arch-at32ap/smc.h
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * Static Memory Controller for AT32 chips
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * Inspired by the OMAP2 General-Purpose Memory Controller interface
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef __ARCH_AT32AP_SMC_H
13#define __ARCH_AT32AP_SMC_H
14
15/*
16 * All timing parameters are in nanoseconds.
17 */
18struct smc_timing {
19 /* Delay from address valid to assertion of given strobe */
20 int ncs_read_setup;
21 int nrd_setup;
22 int ncs_write_setup;
23 int nwe_setup;
24
25 /* Pulse length of given strobe */
26 int ncs_read_pulse;
27 int nrd_pulse;
28 int ncs_write_pulse;
29 int nwe_pulse;
30
31 /* Total cycle length of given operation */
32 int read_cycle;
33 int write_cycle;
34
35 /* Minimal recovery times, will extend cycle if needed */
36 int ncs_read_recover;
37 int nrd_recover;
38 int ncs_write_recover;
39 int nwe_recover;
40};
41
42/*
43 * All timing parameters are in clock cycles.
44 */
45struct smc_config {
46
47 /* Delay from address valid to assertion of given strobe */
48 u8 ncs_read_setup;
49 u8 nrd_setup;
50 u8 ncs_write_setup;
51 u8 nwe_setup;
52
53 /* Pulse length of given strobe */
54 u8 ncs_read_pulse;
55 u8 nrd_pulse;
56 u8 ncs_write_pulse;
57 u8 nwe_pulse;
58
59 /* Total cycle length of given operation */
60 u8 read_cycle;
61 u8 write_cycle;
62
63 /* Bus width in bytes */
64 u8 bus_width;
65
66 /*
67 * 0: Data is sampled on rising edge of NCS
68 * 1: Data is sampled on rising edge of NRD
69 */
70 unsigned int nrd_controlled:1;
71
72 /*
73 * 0: Data is driven on falling edge of NCS
74 * 1: Data is driven on falling edge of NWR
75 */
76 unsigned int nwe_controlled:1;
77
78 /*
79 * 0: NWAIT is disabled
80 * 1: Reserved
81 * 2: NWAIT is frozen mode
82 * 3: NWAIT in ready mode
83 */
84 unsigned int nwait_mode:2;
85
86 /*
87 * 0: Byte select access type
88 * 1: Byte write access type
89 */
90 unsigned int byte_write:1;
91
92 /*
93 * Number of clock cycles before data is released after
94 * the rising edge of the read controlling signal
95 *
96 * Total cycles from SMC is tdf_cycles + 1
97 */
98 unsigned int tdf_cycles:4;
99
100 /*
101 * 0: TDF optimization disabled
102 * 1: TDF optimization enabled
103 */
104 unsigned int tdf_mode:1;
105};
106
107extern void smc_set_timing(struct smc_config *config,
108 const struct smc_timing *timing);
109
110extern int smc_set_configuration(int cs, const struct smc_config *config);
111extern struct smc_config *smc_get_configuration(int cs);
112
113#endif /* __ARCH_AT32AP_SMC_H */
diff --git a/include/asm-avr32/arch-at32ap/sram.h b/include/asm-avr32/arch-at32ap/sram.h
deleted file mode 100644
index 4838dae7601a..000000000000
--- a/include/asm-avr32/arch-at32ap/sram.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Simple SRAM allocator
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_AVR32_ARCH_SRAM_H
11#define __ASM_AVR32_ARCH_SRAM_H
12
13#include <linux/genalloc.h>
14
15extern struct gen_pool *sram_pool;
16
17static inline unsigned long sram_alloc(size_t len)
18{
19 if (!sram_pool)
20 return 0UL;
21
22 return gen_pool_alloc(sram_pool, len);
23}
24
25static inline void sram_free(unsigned long addr, size_t len)
26{
27 return gen_pool_free(sram_pool, addr, len);
28}
29
30#endif /* __ASM_AVR32_ARCH_SRAM_H */
diff --git a/include/asm-m68k/unistd.h b/include/asm-m68k/unistd.h
index e72ba563f102..965abb8bc7ff 100644
--- a/include/asm-m68k/unistd.h
+++ b/include/asm-m68k/unistd.h
@@ -325,10 +325,16 @@
325#define __NR_fallocate 320 325#define __NR_fallocate 320
326#define __NR_timerfd_settime 321 326#define __NR_timerfd_settime 321
327#define __NR_timerfd_gettime 322 327#define __NR_timerfd_gettime 322
328#define __NR_signalfd4 323
329#define __NR_eventfd2 324
330#define __NR_epoll_create1 325
331#define __NR_dup3 326
332#define __NR_pipe2 327
333#define __NR_inotify_init1 328
328 334
329#ifdef __KERNEL__ 335#ifdef __KERNEL__
330 336
331#define NR_syscalls 323 337#define NR_syscalls 329
332 338
333#define __ARCH_WANT_IPC_PARSE_VERSION 339#define __ARCH_WANT_IPC_PARSE_VERSION
334#define __ARCH_WANT_OLD_READDIR 340#define __ARCH_WANT_OLD_READDIR
diff --git a/include/linux/harrier_defs.h b/include/linux/harrier_defs.h
deleted file mode 100644
index efef11db790f..000000000000
--- a/include/linux/harrier_defs.h
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 * include/linux/harrier_defs.h
3 *
4 * Definitions for Motorola MCG Harrier North Bridge & Memory controller
5 *
6 * Author: Dale Farnsworth
7 * dale.farnsworth@mvista.com
8 *
9 * Extracted from asm-ppc/harrier.h by:
10 * Randy Vinson
11 * rvinson@mvista.com
12 *
13 * Copyright 2001-2002 MontaVista Software Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef __ASMPPC_HARRIER_DEFS_H
22#define __ASMPPC_HARRIER_DEFS_H
23
24#define HARRIER_DEFAULT_XCSR_BASE 0xfeff0000
25
26#define HARRIER_VEND_DEV_ID 0x1057480b
27
28#define HARRIER_VENI_OFF 0x00
29
30#define HARRIER_REVI_OFF 0x05
31#define HARRIER_UCTL_OFF 0xd0
32#define HARRIER_XTAL64_MASK 0x02
33
34#define HARRIER_MISC_CSR_OFF 0x1c
35#define HARRIER_RSTOUT 0x01000000
36#define HARRIER_SYSCON 0x08000000
37#define HARRIER_EREADY 0x10000000
38#define HARRIER_ERDYS 0x20000000
39
40/* Function exception registers */
41#define HARRIER_FEEN_OFF 0x40 /* enable */
42#define HARRIER_FEST_OFF 0x44 /* status */
43#define HARRIER_FEMA_OFF 0x48 /* mask */
44#define HARRIER_FECL_OFF 0x4c /* clear */
45
46#define HARRIER_FE_DMA 0x80
47#define HARRIER_FE_MIDB 0x40
48#define HARRIER_FE_MIM0 0x20
49#define HARRIER_FE_MIM1 0x10
50#define HARRIER_FE_MIP 0x08
51#define HARRIER_FE_UA0 0x04
52#define HARRIER_FE_UA1 0x02
53#define HARRIER_FE_ABT 0x01
54
55#define HARRIER_SERIAL_0_OFF 0xc0
56
57#define HARRIER_MBAR_OFF 0xe0
58#define HARRIER_MBAR_MSK 0xfffc0000
59#define HARRIER_MPIC_CSR_OFF 0xe4
60#define HARRIER_MPIC_OPI_ENABLE 0x40
61#define HARRIER_MPIC_IFEVP_OFF 0x10200
62#define HARRIER_MPIC_IFEVP_VECT_MSK 0xff
63#define HARRIER_MPIC_IFEDE_OFF 0x10210
64
65/*
66 * Define the Memory Controller register offsets.
67 */
68#define HARRIER_SDBA_OFF 0x110
69#define HARRIER_SDBB_OFF 0x114
70#define HARRIER_SDBC_OFF 0x118
71#define HARRIER_SDBD_OFF 0x11c
72#define HARRIER_SDBE_OFF 0x120
73#define HARRIER_SDBF_OFF 0x124
74#define HARRIER_SDBG_OFF 0x128
75#define HARRIER_SDBH_OFF 0x12c
76
77#define HARRIER_SDB_ENABLE 0x00000100
78#define HARRIER_SDB_SIZE_MASK 0xf
79#define HARRIER_SDB_SIZE_SHIFT 16
80#define HARRIER_SDB_BASE_MASK 0xff
81#define HARRIER_SDB_BASE_SHIFT 24
82
83/*
84 * Define outbound register offsets.
85 */
86#define HARRIER_OTAD0_OFF 0x220
87#define HARRIER_OTOF0_OFF 0x224
88#define HARRIER_OTAD1_OFF 0x228
89#define HARRIER_OTOF1_OFF 0x22c
90#define HARRIER_OTAD2_OFF 0x230
91#define HARRIER_OTOF2_OFF 0x234
92#define HARRIER_OTAD3_OFF 0x238
93#define HARRIER_OTOF3_OFF 0x23c
94
95#define HARRIER_OTADX_START_MSK 0xffff0000UL
96#define HARRIER_OTADX_END_MSK 0x0000ffffUL
97
98#define HARRIER_OTOFX_OFF_MSK 0xffff0000UL
99#define HARRIER_OTOFX_ENA 0x80UL
100#define HARRIER_OTOFX_WPE 0x10UL
101#define HARRIER_OTOFX_SGE 0x08UL
102#define HARRIER_OTOFX_RAE 0x04UL
103#define HARRIER_OTOFX_MEM 0x02UL
104#define HARRIER_OTOFX_IOM 0x01UL
105
106/*
107 * Define generic message passing register offsets
108 */
109/* Mirrored registers (visible from both PowerPC and PCI space) */
110#define HARRIER_XCSR_MP_BASE_OFF 0x290 /* base offset in XCSR space */
111#define HARRIER_PMEP_MP_BASE_OFF 0x100 /* base offset in PMEM space */
112#define HARRIER_MGOM0_OFF 0x00 /* outbound msg 0 */
113#define HARRIER_MGOM1_OFF 0x04 /* outbound msg 1 */
114#define HARRIER_MGOD_OFF 0x08 /* outbound doorbells */
115
116#define HARRIER_MGIM0_OFF 0x10 /* inbound msg 0 */
117#define HARRIER_MGIM1_OFF 0x14 /* inbound msg 1 */
118#define HARRIER_MGID_OFF 0x18 /* inbound doorbells */
119
120/* PowerPC-only registers */
121#define HARRIER_MGIDM_OFF 0x20 /* inbound doorbell mask */
122
123/* PCI-only registers */
124#define HARRIER_PMEP_MGST_OFF 0x20 /* (outbound) interrupt status */
125#define HARRIER_PMEP_MGMS_OFF 0x24 /* (outbound) interrupt mask */
126#define HARRIER_MG_OMI0 (1<<4)
127#define HARRIER_MG_OMI1 (1<<5)
128
129#define HARRIER_PMEP_MGODM_OFF 0x28 /* outbound doorbell mask */
130
131/*
132 * Define PCI configuration space register offsets
133 */
134#define HARRIER_XCSR_TO_PCFS_OFF 0x300
135
136/*
137 * Define message passing attribute register offset
138 */
139#define HARRIER_MPAT_OFF 0x44
140
141/*
142 * Define inbound attribute register offsets.
143 */
144#define HARRIER_ITSZ0_OFF 0x48
145#define HARRIER_ITAT0_OFF 0x4c
146
147#define HARRIER_ITSZ1_OFF 0x50
148#define HARRIER_ITAT1_OFF 0x54
149
150#define HARRIER_ITSZ2_OFF 0x58
151#define HARRIER_ITAT2_OFF 0x5c
152
153#define HARRIER_ITSZ3_OFF 0x60
154#define HARRIER_ITAT3_OFF 0x64
155
156/* inbound translation size constants */
157#define HARRIER_ITSZ_MSK 0xff
158#define HARRIER_ITSZ_4KB 0x00
159#define HARRIER_ITSZ_8KB 0x01
160#define HARRIER_ITSZ_16KB 0x02
161#define HARRIER_ITSZ_32KB 0x03
162#define HARRIER_ITSZ_64KB 0x04
163#define HARRIER_ITSZ_128KB 0x05
164#define HARRIER_ITSZ_256KB 0x06
165#define HARRIER_ITSZ_512KB 0x07
166#define HARRIER_ITSZ_1MB 0x08
167#define HARRIER_ITSZ_2MB 0x09
168#define HARRIER_ITSZ_4MB 0x0A
169#define HARRIER_ITSZ_8MB 0x0B
170#define HARRIER_ITSZ_16MB 0x0C
171#define HARRIER_ITSZ_32MB 0x0D
172#define HARRIER_ITSZ_64MB 0x0E
173#define HARRIER_ITSZ_128MB 0x0F
174#define HARRIER_ITSZ_256MB 0x10
175#define HARRIER_ITSZ_512MB 0x11
176#define HARRIER_ITSZ_1GB 0x12
177#define HARRIER_ITSZ_2GB 0x13
178
179/* inbound translation offset */
180#define HARRIER_ITOF_SHIFT 0x10
181#define HARRIER_ITOF_MSK 0xffff
182
183/* inbound translation atttributes */
184#define HARRIER_ITAT_PRE (1<<3)
185#define HARRIER_ITAT_RAE (1<<4)
186#define HARRIER_ITAT_WPE (1<<5)
187#define HARRIER_ITAT_MEM (1<<6)
188#define HARRIER_ITAT_ENA (1<<7)
189#define HARRIER_ITAT_GBL (1<<16)
190
191#define HARRIER_LBA_OFF 0x80
192#define HARRIER_LBA_MSK (1<<31)
193
194#define HARRIER_XCSR_SIZE 1024
195
196/* macros to calculate message passing register offsets */
197#define HARRIER_MP_XCSR(x) ((u32)HARRIER_XCSR_MP_BASE_OFF + (u32)x)
198
199#define HARRIER_MP_PMEP(x) ((u32)HARRIER_PMEP_MP_BASE_OFF + (u32)x)
200
201/*
202 * Define PCI configuration space register offsets
203 */
204#define HARRIER_MPBAR_OFF PCI_BASE_ADDRESS_0
205#define HARRIER_ITBAR0_OFF PCI_BASE_ADDRESS_1
206#define HARRIER_ITBAR1_OFF PCI_BASE_ADDRESS_2
207#define HARRIER_ITBAR2_OFF PCI_BASE_ADDRESS_3
208#define HARRIER_ITBAR3_OFF PCI_BASE_ADDRESS_4
209
210#define HARRIER_XCSR_CONFIG(x) ((u32)HARRIER_XCSR_TO_PCFS_OFF + (u32)x)
211
212#endif /* __ASMPPC_HARRIER_DEFS_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 825be3878f68..c0e14008a3c2 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -641,6 +641,7 @@ int pci_restore_state(struct pci_dev *dev);
641int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 641int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
642pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 642pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
643bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 643bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
644void pci_pme_active(struct pci_dev *dev, bool enable);
644int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); 645int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
645pci_power_t pci_target_state(struct pci_dev *dev); 646pci_power_t pci_target_state(struct pci_dev *dev);
646int pci_prepare_to_sleep(struct pci_dev *dev); 647int pci_prepare_to_sleep(struct pci_dev *dev);
@@ -680,10 +681,12 @@ void pci_enable_bridges(struct pci_bus *bus);
680/* Proper probing supporting hot-pluggable devices */ 681/* Proper probing supporting hot-pluggable devices */
681int __must_check __pci_register_driver(struct pci_driver *, struct module *, 682int __must_check __pci_register_driver(struct pci_driver *, struct module *,
682 const char *mod_name); 683 const char *mod_name);
683static inline int __must_check pci_register_driver(struct pci_driver *driver) 684
684{ 685/*
685 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME); 686 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
686} 687 */
688#define pci_register_driver(driver) \
689 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
687 690
688void pci_unregister_driver(struct pci_driver *dev); 691void pci_unregister_driver(struct pci_driver *dev);
689void pci_remove_behind_bridge(struct pci_dev *dev); 692void pci_remove_behind_bridge(struct pci_dev *dev);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 35a78415accc..9ec2bcce8e83 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2177,8 +2177,6 @@
2177#define PCI_DEVICE_ID_HERC_WIN 0x5732 2177#define PCI_DEVICE_ID_HERC_WIN 0x5732
2178#define PCI_DEVICE_ID_HERC_UNI 0x5832 2178#define PCI_DEVICE_ID_HERC_UNI 0x5832
2179 2179
2180#define PCI_VENDOR_ID_RDC 0x17f3
2181
2182#define PCI_VENDOR_ID_SITECOM 0x182d 2180#define PCI_VENDOR_ID_SITECOM 0x182d
2183#define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069 2181#define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069
2184 2182
diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h
index 5bad61a93f65..2f5c16b1aacd 100644
--- a/include/linux/slub_def.h
+++ b/include/linux/slub_def.h
@@ -46,6 +46,7 @@ struct kmem_cache_cpu {
46struct kmem_cache_node { 46struct kmem_cache_node {
47 spinlock_t list_lock; /* Protect partial list and nr_partial */ 47 spinlock_t list_lock; /* Protect partial list and nr_partial */
48 unsigned long nr_partial; 48 unsigned long nr_partial;
49 unsigned long min_partial;
49 struct list_head partial; 50 struct list_head partial;
50#ifdef CONFIG_SLUB_DEBUG 51#ifdef CONFIG_SLUB_DEBUG
51 atomic_long_t nr_slabs; 52 atomic_long_t nr_slabs;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 19:59:54 -0500