diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/pci-aspm.h | 56 | ||||
-rw-r--r-- | include/linux/pci.h | 5 | ||||
-rw-r--r-- | include/linux/pci_regs.h | 8 |
3 files changed, 69 insertions, 0 deletions
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h new file mode 100644 index 000000000000..a1a1e618e996 --- /dev/null +++ b/include/linux/pci-aspm.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * aspm.h | ||
3 | * | ||
4 | * PCI Express ASPM defines and function prototypes | ||
5 | * | ||
6 | * Copyright (C) 2007 Intel Corp. | ||
7 | * Zhang Yanmin (yanmin.zhang@intel.com) | ||
8 | * Shaohua Li (shaohua.li@intel.com) | ||
9 | * | ||
10 | * For more information, please consult the following manuals (look at | ||
11 | * http://www.pcisig.com/ for how to get them): | ||
12 | * | ||
13 | * PCI Express Specification | ||
14 | */ | ||
15 | |||
16 | #ifndef LINUX_ASPM_H | ||
17 | #define LINUX_ASPM_H | ||
18 | |||
19 | #include <linux/pci.h> | ||
20 | |||
21 | #define PCIE_LINK_STATE_L0S 1 | ||
22 | #define PCIE_LINK_STATE_L1 2 | ||
23 | #define PCIE_LINK_STATE_CLKPM 4 | ||
24 | |||
25 | #ifdef CONFIG_PCIEASPM | ||
26 | extern void pcie_aspm_init_link_state(struct pci_dev *pdev); | ||
27 | extern void pcie_aspm_exit_link_state(struct pci_dev *pdev); | ||
28 | extern void pcie_aspm_pm_state_change(struct pci_dev *pdev); | ||
29 | extern void pci_disable_link_state(struct pci_dev *pdev, int state); | ||
30 | #else | ||
31 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) | ||
32 | { | ||
33 | } | ||
34 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) | ||
35 | { | ||
36 | } | ||
37 | static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) | ||
38 | { | ||
39 | } | ||
40 | static inline void pci_disable_link_state(struct pci_dev *pdev, int state) | ||
41 | { | ||
42 | } | ||
43 | #endif | ||
44 | |||
45 | #ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */ | ||
46 | extern void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); | ||
47 | extern void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); | ||
48 | #else | ||
49 | static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | ||
50 | { | ||
51 | } | ||
52 | static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | ||
53 | { | ||
54 | } | ||
55 | #endif | ||
56 | #endif /* LINUX_ASPM_H */ | ||
diff --git a/include/linux/pci.h b/include/linux/pci.h index 3b8a4e17052f..14bf3d236d19 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h | |||
@@ -128,6 +128,7 @@ struct pci_cap_saved_state { | |||
128 | u32 data[0]; | 128 | u32 data[0]; |
129 | }; | 129 | }; |
130 | 130 | ||
131 | struct pcie_link_state; | ||
131 | /* | 132 | /* |
132 | * The pci_dev structure is used to describe PCI devices. | 133 | * The pci_dev structure is used to describe PCI devices. |
133 | */ | 134 | */ |
@@ -164,6 +165,10 @@ struct pci_dev { | |||
164 | this is D0-D3, D0 being fully functional, | 165 | this is D0-D3, D0 being fully functional, |
165 | and D3 being off. */ | 166 | and D3 being off. */ |
166 | 167 | ||
168 | #ifdef CONFIG_PCIEASPM | ||
169 | struct pcie_link_state *link_state; /* ASPM link state. */ | ||
170 | #endif | ||
171 | |||
167 | pci_channel_state_t error_state; /* current connectivity state */ | 172 | pci_channel_state_t error_state; /* current connectivity state */ |
168 | struct device dev; /* Generic device interface */ | 173 | struct device dev; /* Generic device interface */ |
169 | 174 | ||
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index c1914a8b94a9..c0c1223c9194 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h | |||
@@ -395,9 +395,17 @@ | |||
395 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ | 395 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
396 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ | 396 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
397 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ | 397 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
398 | #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ | ||
399 | #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ | ||
400 | #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ | ||
401 | #define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */ | ||
398 | #define PCI_EXP_LNKCTL 16 /* Link Control */ | 402 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
403 | #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ | ||
404 | #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ | ||
399 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ | 405 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ |
400 | #define PCI_EXP_LNKSTA 18 /* Link Status */ | 406 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
407 | #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ | ||
408 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ | ||
401 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ | 409 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
402 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ | 410 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ |
403 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ | 411 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ |