311 files changed, 8494 insertions, 8214 deletions

diff --git a/include/asm-alpha/termbits.h b/include/asm-alpha/termbits.h
index 5541101b58ae..ad854a4a3af6 100644
--- a/include/asm-alpha/termbits.h
+++ b/include/asm-alpha/termbits.h
@@ -25,6 +25,19 @@ struct termios {
         speed_t c_ospeed;               /* output speed */
 };
 
+/* Alpha has matching termios and ktermios */
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t c_line;                    /* line discipline (== c_cc[19]) */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VEOF 0
 #define VEOL 1
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 24b51cccde8f..9eceb4148922 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -17,8 +17,6 @@
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
 
-#ifdef CONFIG_DISCONTIGMEM
-
 /*
  * The nodes are the followings:
  *
@@ -27,42 +25,6 @@
  *   node 2: 0xf800.0000 - 0xfbff.ffff
  *   node 3: 0xfc00.0000 - 0xffff.ffff
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- *  Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- *  and returns the index corresponding to the appropriate page in the
- *  node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
-
-#define NODE_MAX_MEM_SHIFT      26
-#define NODE_MAX_MEM_SIZE       (1 << NODE_MAX_MEM_SHIFT)
-
-#endif /* CONFIG_DISCONTIGMEM */
+#define NODE_MEM_SIZE_BITS      26
 
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-at91rm9200/at91_aic.h b/include/asm-arm/arch-at91rm9200/at91_aic.h
new file mode 100644
index 000000000000..267e69812e26
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_aic.h
@@ -0,0 +1,53 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_aic.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Advanced Interrupt Controller (AIC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_AIC_H
+#define AT91_AIC_H
+
+#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
+#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
+#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
+#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
+#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
+#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
+
+#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
+#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
+#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
+
+#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
+#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
+#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
+#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
+#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
+
+#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
+#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
+#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
+#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
+#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
+
+#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_dbgu.h b/include/asm-arm/arch-at91rm9200/at91_dbgu.h
new file mode 100644
index 000000000000..e4b8b27acfca
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_dbgu.h
@@ -0,0 +1,45 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_dbgu.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Debug Unit (DBGU) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_DBGU_H
+#define AT91_DBGU_H
+
+#define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
+#define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
+#define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
+#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
+#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
+#define AT91_DBGU_IDR           (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
+#define AT91_DBGU_IMR           (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
+#define AT91_DBGU_SR            (AT91_DBGU + 0x14)      /* Status Register */
+#define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
+#define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
+#define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
+
+#define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
+#define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
+#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
+#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
+#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
+#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
+#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
+#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
+#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
+#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
+
+#define AT91_DBGU_FNR           (AT91_DBGU + 0x48)      /* Force NTRST Register [SAM9 only] */
+#define         AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h
new file mode 100644
index 000000000000..fddf256a98d3
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_ecc.h
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_ecc.h
+ *
+ * Error Corrected Code Controller (ECC) - System peripherals regsters.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef AT91_ECC_H
+#define AT91_ECC_H
+
+#define AT91_ECC_CR             (AT91_ECC + 0x00)       /* Control register */
+#define         AT91_ECC_RST            (1 << 0)                /* Reset parity */
+
+#define AT91_ECC_MR             (AT91_ECC + 0x04)       /* Mode register */
+#define         AT91_ECC_PAGESIZE       (3 << 0)                /* Page Size */
+#define                 AT91_ECC_PAGESIZE_528           (0)
+#define                 AT91_ECC_PAGESIZE_1056          (1)
+#define                 AT91_ECC_PAGESIZE_2112          (2)
+#define                 AT91_ECC_PAGESIZE_4224          (3)
+
+#define AT91_ECC_SR             (AT91_ECC + 0x08)       /* Status register */
+#define         AT91_ECC_RECERR         (1 << 0)                /* Recoverable Error */
+#define         AT91_ECC_ECCERR         (1 << 1)                /* ECC Single Bit Error */
+#define         AT91_ECC_MULERR         (1 << 2)                /* Multiple Errors */
+
+#define AT91_ECC_PR             (AT91_ECC + 0x0c)       /* Parity register */
+#define         AT91_ECC_BITADDR        (0xf << 0)              /* Bit Error Address */
+#define         AT91_ECC_WORDADDR       (0xfff << 4)            /* Word Error Address */
+
+#define AT91_ECC_NPR            (AT91_ECC + 0x10)       /* NParity register */
+#define         AT91_ECC_NPARITY        (0xffff << 0)           /* NParity */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_lcdc.h b/include/asm-arm/arch-at91rm9200/at91_lcdc.h
new file mode 100644
index 000000000000..9cbfcdd3c471
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_lcdc.h
@@ -0,0 +1,148 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_lcdc.h
+ *
+ * LCD Controller (LCDC).
+ * Based on AT91SAM9261 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_LCDC_H
+#define AT91_LCDC_H
+
+#define AT91_LCDC_DMABADDR1     0x00            /* DMA Base Address Register 1 */
+#define AT91_LCDC_DMABADDR2     0x04            /* DMA Base Address Register 2 */
+#define AT91_LCDC_DMAFRMPT1     0x08            /* DMA Frame Pointer Register 1 */
+#define AT91_LCDC_DMAFRMPT2     0x0c            /* DMA Frame Pointer Register 2 */
+#define AT91_LCDC_DMAFRMADD1    0x10            /* DMA Frame Address Register 1 */
+#define AT91_LCDC_DMAFRMADD2    0x14            /* DMA Frame Address Register 2 */
+
+#define AT91_LCDC_DMAFRMCFG     0x18            /* DMA Frame Configuration Register */
+#define         AT91_LCDC_FRSIZE        (0x7fffff <<  0)        /* Frame Size */
+#define         AT91_LCDC_BLENGTH       (0x7f     << 24)        /* Burst Length */
+
+#define AT91_LCDC_DMACON        0x1c            /* DMA Control Register */
+#define         AT91_LCDC_DMAEN         (0x1 << 0)      /* DMA Enable */
+#define         AT91_LCDC_DMARST        (0x1 << 1)      /* DMA Reset */
+#define         AT91_LCDC_DMABUSY       (0x1 << 2)      /* DMA Busy */
+
+#define AT91_LCDC_LCDCON1       0x0800          /* LCD Control Register 1 */
+#define         AT91_LCDC_BYPASS        (1     <<  0)   /* Bypass lcd_dotck divider */
+#define         AT91_LCDC_CLKVAL        (0x1ff << 12)   /* Clock Divider */
+#define         AT91_LCDC_LINCNT        (0x7ff << 21)   /* Line Counter */
+
+#define AT91_LCDC_LCDCON2       0x0804          /* LCD Control Register 2 */
+#define         AT91_LCDC_DISTYPE       (3 << 0)        /* Display Type */
+#define                 AT91_LCDC_DISTYPE_STNMONO       (0 << 0)
+#define                 AT91_LCDC_DISTYPE_STNCOLOR      (1 << 0)
+#define                 AT91_LCDC_DISTYPE_TFT           (2 << 0)
+#define         AT91_LCDC_SCANMOD       (1 << 2)        /* Scan Mode */
+#define                 AT91_LCDC_SCANMOD_SINGLE        (0 << 2)
+#define                 AT91_LCDC_SCANMOD_DUAL          (1 << 2)
+#define         AT91_LCDC_IFWIDTH       (3 << 3)        /*Interface Width */
+#define                 AT91_LCDC_IFWIDTH_4             (0 << 3)
+#define                 AT91_LCDC_IFWIDTH_8             (1 << 3)
+#define                 AT91_LCDC_IFWIDTH_16            (2 << 3)
+#define         AT91_LCDC_PIXELSIZE     (7 << 5)        /* Bits per pixel */
+#define                 AT91_LCDC_PIXELSIZE_1           (0 << 5)
+#define                 AT91_LCDC_PIXELSIZE_2           (1 << 5)
+#define                 AT91_LCDC_PIXELSIZE_4           (2 << 5)
+#define                 AT91_LCDC_PIXELSIZE_8           (3 << 5)
+#define                 AT91_LCDC_PIXELSIZE_16          (4 << 5)
+#define                 AT91_LCDC_PIXELSIZE_24          (5 << 5)
+#define         AT91_LCDC_INVVD         (1 << 8)        /* LCD Data polarity */
+#define                 AT91_LCDC_INVVD_NORMAL          (0 << 8)
+#define                 AT91_LCDC_INVVD_INVERTED        (1 << 8)
+#define         AT91_LCDC_INVFRAME      (1 << 9 )       /* LCD VSync polarity */
+#define                 AT91_LCDC_INVFRAME_NORMAL       (0 << 9)
+#define                 AT91_LCDC_INVFRAME_INVERTED     (1 << 9)
+#define         AT91_LCDC_INVLINE       (1 << 10)       /* LCD HSync polarity */
+#define                 AT91_LCDC_INVLINE_NORMAL        (0 << 10)
+#define                 AT91_LCDC_INVLINE_INVERTED      (1 << 10)
+#define         AT91_LCDC_INVCLK        (1 << 11)       /* LCD dotclk polarity */
+#define                 AT91_LCDC_INVCLK_NORMAL         (0 << 11)
+#define                 AT91_LCDC_INVCLK_INVERTED       (1 << 11)
+#define         AT91_LCDC_INVDVAL       (1 << 12)       /* LCD dval polarity */
+#define                 AT91_LCDC_INVDVAL_NORMAL        (0 << 12)
+#define                 AT91_LCDC_INVDVAL_INVERTED      (1 << 12)
+#define         AT91_LCDC_CLKMOD        (1 << 15)       /* LCD dotclk mode */
+#define                 AT91_LCDC_CLKMOD_ACTIVEDISPLAY  (0 << 15)
+#define                 AT91_LCDC_CLKMOD_ALWAYSACTIVE   (1 << 15)
+#define         AT91_LCDC_MEMOR         (1 << 31)       /* Memory Ordering Format */
+#define                 AT91_LCDC_MEMOR_BIG             (0 << 31)
+#define                 AT91_LCDC_MEMOR_LITTLE          (1 << 31)
+
+#define AT91_LCDC_TIM1          0x0808          /* LCD Timing Register 1 */
+#define         AT91_LCDC_VFP           (0xff <<  0)    /* Vertical Front Porch */
+#define         AT91_LCDC_VBP           (0xff <<  8)    /* Vertical Back Porch */
+#define         AT91_LCDC_VPW           (0x3f << 16)    /* Vertical Synchronization Pulse Width */
+#define         AT91_LCDC_VHDLY         (0xf  << 24)    /* Vertical to Horizontal Delay */
+
+#define AT91_LCDC_TIM2          0x080c          /* LCD Timing Register 2 */
+#define         AT91_LCDC_HBP           (0xff  <<  0)   /* Horizontal Back Porch */
+#define         AT91_LCDC_HPW           (0x3f  <<  8)   /* Horizontal Synchronization Pulse Width */
+#define         AT91_LCDC_HFP           (0x7ff << 21)   /* Horizontal Front Porch */
+
+#define AT91_LCDC_LCDFRMCFG     0x0810          /* LCD Frame Configuration Register */
+#define         AT91_LCDC_LINEVAL       (0x7ff <<  0)   /* Vertical Size of LCD Module */
+#define         AT91_LCDC_HOZVAL        (0x7ff << 21)   /* Horizontal Size of LCD Module */
+
+#define AT91_LCDC_FIFO          0x0814          /* LCD FIFO Register */
+#define         AT91_LCDC_FIFOTH        (0xffff)        /* FIFO Threshold */
+
+#define AT91_LCDC_DP1_2         0x081c          /* Dithering Pattern DP1_2 Register */
+#define AT91_LCDC_DP4_7         0x0820          /* Dithering Pattern DP4_7 Register */
+#define AT91_LCDC_DP3_5         0x0824          /* Dithering Pattern DP3_5 Register */
+#define AT91_LCDC_DP2_3         0x0828          /* Dithering Pattern DP2_3 Register */
+#define AT91_LCDC_DP5_7         0x082c          /* Dithering Pattern DP5_7 Register */
+#define AT91_LCDC_DP3_4         0x0830          /* Dithering Pattern DP3_4 Register */
+#define AT91_LCDC_DP4_5         0x0834          /* Dithering Pattern DP4_5 Register */
+#define AT91_LCDC_DP6_7         0x0838          /* Dithering Pattern DP6_7 Register */
+#define         AT91_LCDC_DP1_2_VAL     (0xff)
+#define         AT91_LCDC_DP4_7_VAL     (0xfffffff)
+#define         AT91_LCDC_DP3_5_VAL     (0xfffff)
+#define         AT91_LCDC_DP2_3_VAL     (0xfff)
+#define         AT91_LCDC_DP5_7_VAL     (0xfffffff)
+#define         AT91_LCDC_DP3_4_VAL     (0xffff)
+#define         AT91_LCDC_DP4_5_VAL     (0xfffff)
+#define         AT91_LCDC_DP6_7_VAL     (0xfffffff)
+
+#define AT91_LCDC_PWRCON        0x083c          /* Power Control Register */
+#define         AT91_LCDC_PWR           (1    <<  0)    /* LCD Module Power Control */
+#define         AT91_LCDC_GUARDT        (0x7f <<  1)    /* Delay in Frame Period */
+#define         AT91_LCDC_BUSY          (1    << 31)    /* LCD Busy */
+
+#define AT91_LCDC_CONTRAST_CTR  0x0840          /* Contrast Control Register */
+#define         AT91_LCDC_PS            (3 << 0)        /* Contrast Counter Prescaler */
+#define                 AT91_LCDC_PS_DIV1               (0 << 0)
+#define                 AT91_LCDC_PS_DIV2               (1 << 0)
+#define                 AT91_LCDC_PS_DIV4               (2 << 0)
+#define                 AT91_LCDC_PS_DIV8               (3 << 0)
+#define         AT91_LCDC_POL           (1 << 2)        /* Polarity of output Pulse */
+#define                 AT91_LCDC_POL_NEGATIVE          (0 << 2)
+#define                 AT91_LCDC_POL_POSITIVE          (1 << 2)
+#define         AT91_LCDC_ENA           (1 << 3)        /* PWM generator Control */
+#define                 AT91_LCDC_ENA_PWMDISABLE        (0 << 3)
+#define                 AT91_LCDC_ENA_PWMENABLE         (1 << 3)
+
+#define AT91_LCDC_CONTRAST_VAL  0x0844          /* Contrast Value Register */
+#define         AT91_LCDC_CVAL          (0xff)          /* PWM compare value */
+
+#define AT91_LCDC_IER           0x0848          /* Interrupt Enable Register */
+#define AT91_LCDC_IDR           0x084c          /* Interrupt Disable Register */
+#define AT91_LCDC_IMR           0x0850          /* Interrupt Mask Register */
+#define AT91_LCDC_ISR           0x0854          /* Interrupt Enable Register */
+#define AT91_LCDC_ICR           0x0858          /* Interrupt Clear Register */
+#define         AT91_LCDC_LNI           (1 << 0)        /* Line Interrupt */
+#define         AT91_LCDC_LSTLNI        (1 << 1)        /* Last Line Interrupt */
+#define         AT91_LCDC_EOFI          (1 << 2)        /* DMA End Of Frame Interrupt */
+#define         AT91_LCDC_UFLWI         (1 << 4)        /* FIFO Underflow Interrupt */
+#define         AT91_LCDC_OWRI          (1 << 5)        /* FIFO Overwrite Interrupt */
+#define         AT91_LCDC_MERI          (1 << 6)        /* DMA Memory Error Interrupt */
+
+#define AT91_LCDC_LUT_(n)       (0x0c00 + ((n)*4))      /* Palette Entry 0..255 */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h b/include/asm-arm/arch-at91rm9200/at91_mci.h
index f28636d61e39..9a552cb743c0 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
+++ b/include/asm-arm/arch-at91rm9200/at91_mci.h
@@ -1,11 +1,11 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
+ * include/asm-arm/arch-at91rm9200/at91_mci.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
  *
  * MultiMedia Card Interface (MCI) registers.
- * Based on AT91RM9200 datasheet revision E.
+ * Based on AT91RM9200 datasheet revision F.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_MCI_H
-#define AT91RM9200_MCI_H
+#ifndef AT91_MCI_H
+#define AT91_MCI_H
 
 #define AT91_MCI_CR             0x00            /* Control Register */
 #define         AT91_MCI_MCIEN          (1 <<  0)       /* Multi-Media Interface Enable */
@@ -25,10 +25,10 @@
 
 #define AT91_MCI_MR             0x04            /* Mode Register */
 #define         AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
-#define         AT91_MCI_PWSDIV         (3     <<  8)   /* Power Saving Divider */
+#define         AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
 #define         AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
 #define         AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
-#define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
+#define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
 
 #define AT91_MCI_DTOR           0x08            /* Data Timeout Register */
 #define         AT91_MCI_DTOCYC         (0xf << 0)      /* Data Timeout Cycle Number */
@@ -43,8 +43,8 @@
 #define         AT91_MCI_DTOMUL_1M              (7 <<  4)
 
 #define AT91_MCI_SDCR           0x0c            /* SD Card Register */
-#define         AT91_MCI_SDCSEL         (0xf << 0)      /* SD Card Selector */
-#define         AT91_MCI_SDCBUS         (1   << 7)      /* 1-bit or 4-bit bus */
+#define         AT91_MCI_SDCSEL         (3 << 0)        /* SD Card Selector */
+#define         AT91_MCI_SDCBUS         (1 << 7)        /* 1-bit or 4-bit bus */
 
 #define AT91_MCI_ARGR           0x10            /* Argument Register */
 
@@ -78,18 +78,20 @@
 
 #define AT91_MCI_SR             0x40            /* Status Register */
 #define         AT91_MCI_CMDRDY         (1 <<  0)       /* Command Ready */
-#define         AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
+#define         AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
 #define         AT91_MCI_TXRDY          (1 <<  2)       /* Transmit Ready */
 #define         AT91_MCI_BLKE           (1 <<  3)       /* Data Block Ended */
 #define         AT91_MCI_DTIP           (1 <<  4)       /* Data Transfer in Progress */
 #define         AT91_MCI_NOTBUSY        (1 <<  5)       /* Data Not Busy */
 #define         AT91_MCI_ENDRX          (1 <<  6)       /* End of RX Buffer */
 #define         AT91_MCI_ENDTX          (1 <<  7)       /* End fo TX Buffer */
+#define         AT91_MCI_SDIOIRQA       (1 <<  8)       /* SDIO Interrupt for Slot A */
+#define         At91_MCI_SDIOIRQB       (1 <<  9)       /* SDIO Interrupt for Slot B [AT91RM9200 only] */
 #define         AT91_MCI_RXBUFF         (1 << 14)       /* RX Buffer Full */
 #define         AT91_MCI_TXBUFE         (1 << 15)       /* TX Buffer Empty */
-#define         AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
+#define         AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
 #define         AT91_MCI_RDIRE          (1 << 17)       /* Response Direction Error */
-#define         AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
+#define         AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
 #define         AT91_MCI_RENDE          (1 << 19)       /* Response End Bit Error */
 #define         AT91_MCI_RTOE           (1 << 20)       /* Reponse Time-out Error */
 #define         AT91_MCI_DCRCE          (1 << 21)       /* Data CRC Error */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91_pdc.h
index ce1150d4438d..79d6e02fa45e 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_pdc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+ * include/asm-arm/arch-at91rm9200/at91_pdc.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_PDC_H
-#define AT91RM9200_PDC_H
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
 
 #define AT91_PDC_RPR            0x100   /* Receive Pointer Register */
 #define AT91_PDC_RCR            0x104   /* Receive Counter Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91_pio.h b/include/asm-arm/arch-at91rm9200/at91_pio.h
new file mode 100644
index 000000000000..680eaa1f5915
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pio.h
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_pio.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Parallel I/O Controller (PIO) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIO_H
+#define AT91_PIO_H
+
+#define PIO_PER         0x00    /* Enable Register */
+#define PIO_PDR         0x04    /* Disable Register */
+#define PIO_PSR         0x08    /* Status Register */
+#define PIO_OER         0x10    /* Output Enable Register */
+#define PIO_ODR         0x14    /* Output Disable Register */
+#define PIO_OSR         0x18    /* Output Status Register */
+#define PIO_IFER        0x20    /* Glitch Input Filter Enable */
+#define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
+#define PIO_IFSR        0x28    /* Glitch Input Filter Status */
+#define PIO_SODR        0x30    /* Set Output Data Register */
+#define PIO_CODR        0x34    /* Clear Output Data Register */
+#define PIO_ODSR        0x38    /* Output Data Status Register */
+#define PIO_PDSR        0x3c    /* Pin Data Status Register */
+#define PIO_IER         0x40    /* Interrupt Enable Register */
+#define PIO_IDR         0x44    /* Interrupt Disable Register */
+#define PIO_IMR         0x48    /* Interrupt Mask Register */
+#define PIO_ISR         0x4c    /* Interrupt Status Register */
+#define PIO_MDER        0x50    /* Multi-driver Enable Register */
+#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
+#define PIO_MDSR        0x58    /* Multi-driver Status Register */
+#define PIO_PUDR        0x60    /* Pull-up Disable Register */
+#define PIO_PUER        0x64    /* Pull-up Enable Register */
+#define PIO_PUSR        0x68    /* Pull-up Status Register */
+#define PIO_ASR         0x70    /* Peripheral A Select Register */
+#define PIO_BSR         0x74    /* Peripheral B Select Register */
+#define PIO_ABSR        0x78    /* AB Status Register */
+#define PIO_OWER        0xa0    /* Output Write Enable Register */
+#define PIO_OWDR        0xa4    /* Output Write Disable Register */
+#define PIO_OWSR        0xa8    /* Output Write Status Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_pit.h b/include/asm-arm/arch-at91rm9200/at91_pit.h
new file mode 100644
index 000000000000..4a30d009c588
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pit.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_pit.h
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+#define AT91_PIT_MR             (AT91_PIT + 0x00)       /* Mode Register */
+#define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
+#define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
+#define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
+
+#define AT91_PIT_SR             (AT91_PIT + 0x04)       /* Status Register */
+#define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
+
+#define AT91_PIT_PIVR           (AT91_PIT + 0x08)       /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR           (AT91_PIT + 0x0c)       /* Periodic Interval Image Register */
+#define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
+#define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_pmc.h b/include/asm-arm/arch-at91rm9200/at91_pmc.h
new file mode 100644
index 000000000000..de8c3da74a01
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pmc.h
@@ -0,0 +1,92 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_pmc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Power Management Controller (PMC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PMC_H
+#define AT91_PMC_H
+
+#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
+#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
+#define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
+#define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
+#define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
+#define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
+#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
+#define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
+
+#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+
+#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
+#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
+#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
+#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
+
+#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
+#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
+
+#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
+#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
+#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
+#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
+#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
+
+#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
+#define                 AT91_PMC_CSS_SLOW               (0 << 0)
+#define                 AT91_PMC_CSS_MAIN               (1 << 0)
+#define                 AT91_PMC_CSS_PLLA               (2 << 0)
+#define                 AT91_PMC_CSS_PLLB               (3 << 0)
+#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
+#define                 AT91_PMC_PRES_1                 (0 << 2)
+#define                 AT91_PMC_PRES_2                 (1 << 2)
+#define                 AT91_PMC_PRES_4                 (2 << 2)
+#define                 AT91_PMC_PRES_8                 (3 << 2)
+#define                 AT91_PMC_PRES_16                (4 << 2)
+#define                 AT91_PMC_PRES_32                (5 << 2)
+#define                 AT91_PMC_PRES_64                (6 << 2)
+#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
+#define                 AT91_PMC_MDIV_1                 (0 << 8)
+#define                 AT91_PMC_MDIV_2                 (1 << 8)
+#define                 AT91_PMC_MDIV_3                 (2 << 8)
+#define                 AT91_PMC_MDIV_4                 (3 << 8)
+
+#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
+
+#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
+#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
+#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
+#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
+#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
+#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
+#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
+#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h
new file mode 100644
index 000000000000..ccdc52da973d
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rstc.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_rstc.h
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_RSTC_CR            (AT91_RSTC + 0x00)      /* Reset Controller Control Register */
+#define         AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
+#define         AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
+#define         AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
+#define         AT01_RSTC_KEY           (0xff << 24)            /* KEY Password */
+
+#define AT91_RSTC_SR            (AT91_RSTC + 0x04)      /* Reset Controller Status Register */
+#define         AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
+#define         AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
+#define                 AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
+#define                 AT91_RSTC_RSTTYP_WAKEUP         (1 << 8)
+#define                 AT91_RSTC_RSTTYP_WATCHDOG       (2 << 8)
+#define                 AT91_RSTC_RSTTYP_SOFTWARE       (3 << 8)
+#define                 AT91_RSTC_RSTTYP_USER   (4 << 8)
+#define         AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
+#define         AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR            (AT91_RSTC + 0x08)      /* Reset Controller Mode Register */
+#define         AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
+#define         AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
+#define         AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
+#define         AT91_RSTC_KEY           (0xff << 24)            /* KEY Password */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtc.h b/include/asm-arm/arch-at91rm9200/at91_rtc.h
new file mode 100644
index 000000000000..6e5065d56260
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rtc.h
@@ -0,0 +1,75 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_rtc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Real Time Clock (RTC) - System peripheral registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RTC_H
+#define AT91_RTC_H
+
+#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
+#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
+#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
+#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
+#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
+#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
+#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
+#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
+#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
+#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
+
+#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
+#define         AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
+
+#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
+#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
+#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
+#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
+#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
+
+#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
+#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
+#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
+#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
+#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
+#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
+
+#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
+#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
+#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
+#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
+
+#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
+#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
+#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
+
+#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
+#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
+#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
+#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
+#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
+#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
+
+#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
+#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
+#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
+#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
+
+#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
+#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
+#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
+#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
+#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtt.h b/include/asm-arm/arch-at91rm9200/at91_rtt.h
new file mode 100644
index 000000000000..c6751ba3cccc
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rtt.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_rtt.h
+ *
+ * Real-time Timer (RTT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RTT_H
+#define AT91_RTT_H
+
+#define AT91_RTT_MR             (AT91_RTT + 0x00)       /* Real-time Mode Register */
+#define         AT91_RTT_RTPRES         (0xffff << 0)           /* Real-time Timer Prescaler Value */
+#define         AT91_RTT_ALMIEN         (1 << 16)               /* Alarm Interrupt Enable */
+#define         AT91_RTT_RTTINCIEN      (1 << 17)               /* Real Time Timer Increment Interrupt Enable */
+#define         AT91_RTT_RTTRST         (1 << 18)               /* Real Time Timer Restart */
+
+#define AT91_RTT_AR             (AT91_RTT + 0x04)       /* Real-time Alarm Register */
+#define         AT91_RTT_ALMV           (0xffffffff)            /* Alarm Value */
+
+#define AT91_RTT_VR             (AT91_RTT + 0x08)       /* Real-time Value Register */
+#define         AT91_RTT_CRTV           (0xffffffff)            /* Current Real-time Value */
+
+#define AT91_RTT_SR             (AT91_RTT + 0x0c)       /* Real-time Status Register */
+#define         AT91_RTT_ALMS           (1 << 0)                /* Real-time Alarm Status */
+#define         AT91_RTT_RTTINC         (1 << 1)                /* Real-time Timer Increment */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_shdwc.h b/include/asm-arm/arch-at91rm9200/at91_shdwc.h
new file mode 100644
index 000000000000..0439250553c9
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_shdwc.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_shdwc.h
+ *
+ * Shutdown Controller (SHDWC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_SHDWC_H
+#define AT91_SHDWC_H
+
+#define AT91_SHDW_CR            (AT91_SHDWC + 0x00)     /* Shut Down Control Register */
+#define         AT91_SHDW_SHDW          (1    << 0)             /* Processor Reset */
+#define         AT91_SHDW_KEY           (0xff << 24)            /* KEY Password */
+
+#define AT91_SHDW_MR            (AT91_SHDWC + 0x04)     /* Shut Down Mode Register */
+#define         AT91_SHDW_WKMODE0       (3 << 0)                /* Wake-up 0 Mode Selection */
+#define                 AT91_SHDW_WKMODE0_NONE          0
+#define                 AT91_SHDW_WKMODE0_HIGH          1
+#define                 AT91_SHDW_WKMODE0_LOW           2
+#define                 AT91_SHDW_WKMODE0_ANYLEVEL      3
+#define         AT91_SHDW_CPTWK0        (0xf << 4)              /* Counter On Wake Up 0 */
+#define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
+
+#define AT91_SHDW_SR            (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
+#define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
+#define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91_spi.h
index bff5ea45f604..bec48ca89bba 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+++ b/include/asm-arm/arch-at91rm9200/at91_spi.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+ * include/asm-arm/arch-at91rm9200/at91_spi.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_SPI_H
-#define AT91RM9200_SPI_H
+#ifndef AT91_SPI_H
+#define AT91_SPI_H
 
 #define AT91_SPI_CR                     0x00            /* Control Register */
 #define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
@@ -28,7 +28,7 @@
 #define                 AT91_SPI_PS_FIXED       (0 << 1)
 #define                 AT91_SPI_PS_VARIABLE    (1 << 1)
 #define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
-#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection */
+#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
 #define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
 #define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
 #define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91_ssc.h
index ac880227147f..694bcaa8f7c2 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_ssc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+ * include/asm-arm/arch-at91rm9200/at91_ssc.h
  *
  * Copyright (C) SAN People
  *
@@ -12,8 +12,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_SSC_H
-#define AT91RM9200_SSC_H
+#ifndef AT91_SSC_H
+#define AT91_SSC_H
 
 #define AT91_SSC_CR             0x00    /* Control Register */
 #define         AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
@@ -36,6 +36,10 @@
 #define         AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
 #define                 AT91_SSC_CKI_FALLING            (0 << 5)
 #define                 AT91_SSC_CK_RISING              (1 << 5)
+#define         AT91_SSC_CKG            (1    <<  6)    /* Receive Clock Gating Selection [AT91SAM9261 only] */
+#define                 AT91_SSC_CKG_NONE               (0 << 6)
+#define                 AT91_SSC_CKG_RFLOW              (1 << 6)
+#define                 AT91_SSC_CKG_RFHIGH             (2 << 6)
 #define         AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
 #define                 AT91_SSC_START_CONTINUOUS       (0 << 8)
 #define                 AT91_SSC_START_TX_RX            (1 << 8)
@@ -45,6 +49,7 @@
 #define                 AT91_SSC_START_RISING_RF        (5 << 8)
 #define                 AT91_SSC_START_LEVEL_RF         (6 << 8)
 #define                 AT91_SSC_START_EDGE_RF          (7 << 8)
+#define         AT91_SSC_STOP           (1    << 12)    /* Receive Stop Selection [AT91SAM9261 only] */
 #define         AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
 #define         AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
 
@@ -75,6 +80,9 @@
 #define AT91_SSC_RSHR           0x30    /* Receive Sync Holding Register */
 #define AT91_SSC_TSHR           0x34    /* Transmit Sync Holding Register */
 
+#define AT91_SSC_RC0R           0x38    /* Receive Compare 0 Register [AT91SAM9261 only] */
+#define AT91_SSC_RC1R           0x3c    /* Receive Compare 1 Register [AT91SAM9261 only] */
+
 #define AT91_SSC_SR             0x40    /* Status Register */
 #define         AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
 #define         AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
@@ -84,6 +92,8 @@
 #define         AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
 #define         AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
 #define         AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
+#define         AT91_SSC_CP0            (1 <<  8)       /* Compare 0 [AT91SAM9261 only] */
+#define         AT91_SSC_CP1            (1 <<  9)       /* Compare 1 [AT91SAM9261 only] */
 #define         AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
 #define         AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
 #define         AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
diff --git a/include/asm-arm/arch-at91rm9200/at91_st.h b/include/asm-arm/arch-at91rm9200/at91_st.h
new file mode 100644
index 000000000000..2432ddfc6c47
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_st.h
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_st.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * System Timer (ST) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_ST_H
+#define AT91_ST_H
+
+#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
+
+#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
+
+#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
+#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
+#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
+
+#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
+
+#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
+#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
+#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
+#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
+
+#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
+#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
+#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+
+#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
+
+#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91_tc.h
index f4da752bb0c8..8d06eb078e1d 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_tc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+ * include/asm-arm/arch-at91rm9200/at91_tc.h
  *
  * Copyright (C) SAN People
  *
@@ -12,8 +12,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_TC_H
-#define AT91RM9200_TC_H
+#ifndef AT91_TC_H
+#define AT91_TC_H
 
 #define AT91_TC_BCR             0xc0            /* TC Block Control Register */
 #define         AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91_twi.h
index 93547d7482bd..cda914f1e740 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+++ b/include/asm-arm/arch-at91rm9200/at91_twi.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+ * include/asm-arm/arch-at91rm9200/at91_twi.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_TWI_H
-#define AT91RM9200_TWI_H
+#ifndef AT91_TWI_H
+#define AT91_TWI_H
 
 #define AT91_TWI_CR             0x00            /* Control Register */
 #define         AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
@@ -43,8 +43,8 @@
 #define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
 #define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
 #define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
-#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error */
-#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error */
+#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
+#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
 #define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
 
 #define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91_wdt.h b/include/asm-arm/arch-at91rm9200/at91_wdt.h
new file mode 100644
index 000000000000..ac63e775772c
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_wdt.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_wdt.h
+ *
+ * Watchdog Timer (WDT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_WDT_H
+#define AT91_WDT_H
+
+#define AT91_WDT_CR             (AT91_WDT + 0x00)       /* Watchdog Control Register */
+#define         AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
+#define         AT91_WDT_KEY            (0xff << 24)            /* KEY Password */
+
+#define AT91_WDT_MR             (AT91_WDT + 0x04)       /* Watchdog Mode Register */
+#define         AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
+#define         AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
+#define         AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
+#define         AT91_WDT_WDRPROC        (1     << 14)           /* Timer Restart */
+#define         AT91_WDT_WDDIS          (1     << 15)           /* Watchdog Disable */
+#define         AT91_WDT_WDD            (0xfff << 16)           /* Delta Value */
+#define         AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
+#define         AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
+
+#define AT91_WDT_SR             (AT91_WDT + 0x08)       /* Watchdog Status Register */
+#define         AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
+#define         AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index a5a86b1ff886..4d51177efddd 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -80,6 +80,22 @@
 
 
 /*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)    /* Debug Unit */
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)    /* PIO Controller A */
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)    /* PIO Controller B */
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)    /* PIO Controller C */
+#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)    /* PIO Controller D */
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
+#define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
+#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)    /* Real-Time Clock */
+#define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
+
+#define AT91_MATRIX     0       /* not supported */
+
+/*
  * Internal Memory.
  */
 #define AT91RM9200_ROM_BASE     0x00100000      /* Internal ROM base address */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
new file mode 100644
index 000000000000..0c0d81480b3a
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
@@ -0,0 +1,160 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_MC_H
+#define AT91RM9200_MC_H
+
+/* Memory Controller */
+#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
+#define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
+
+#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
+#define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
+#define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
+#define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
+#define                 AT91_MC_ABTSZ_BYTE              (0 << 8)
+#define                 AT91_MC_ABTSZ_HALFWORD          (1 << 8)
+#define                 AT91_MC_ABTSZ_WORD              (2 << 8)
+#define         AT91_MC_ABTTYP          (3 << 10)               /* Abort Type Status */
+#define                 AT91_MC_ABTTYP_DATAREAD         (0 << 10)
+#define                 AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
+#define                 AT91_MC_ABTTYP_FETCH            (2 << 10)
+#define         AT91_MC_MST0            (1 << 16)               /* ARM920T Abort Source */
+#define         AT91_MC_MST1            (1 << 17)               /* PDC Abort Source */
+#define         AT91_MC_MST2            (1 << 18)               /* UHP Abort Source */
+#define         AT91_MC_MST3            (1 << 19)               /* EMAC Abort Source */
+#define         AT91_MC_SVMST0          (1 << 24)               /* Saved ARM920T Abort Source */
+#define         AT91_MC_SVMST1          (1 << 25)               /* Saved PDC Abort Source */
+#define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
+#define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
+
+#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
+
+#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
+#define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
+#define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
+#define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
+#define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
+
+/* External Bus Interface (EBI) registers */
+#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
+#define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
+#define                 AT91_EBI_CS0A_SMC               (0 << 0)
+#define                 AT91_EBI_CS0A_BFC               (1 << 0)
+#define         AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
+#define                 AT91_EBI_CS1A_SMC               (0 << 1)
+#define                 AT91_EBI_CS1A_SDRAMC            (1 << 1)
+#define         AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
+#define                 AT91_EBI_CS3A_SMC               (0 << 3)
+#define                 AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
+#define         AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
+#define                 AT91_EBI_CS4A_SMC               (0 << 4)
+#define                 AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
+#define AT91_EBI_CFGR           (AT91_MC + 0x64)        /* Configuration Register */
+#define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
+#define                 AT91_SMC_NWS_(x)        ((x) << 0)
+#define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
+#define         AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
+#define                 AT91_SMC_TDF_(x)        ((x) << 8)
+#define         AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
+#define         AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
+#define                 AT91_SMC_DBW_16         (1 << 13)
+#define                 AT91_SMC_DBW_8          (2 << 13)
+#define         AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
+#define         AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
+#define                 AT91_SMC_ACSS_STD       (0 << 16)
+#define                 AT91_SMC_ACSS_1         (1 << 16)
+#define                 AT91_SMC_ACSS_2         (2 << 16)
+#define                 AT91_SMC_ACSS_3         (3 << 16)
+#define         AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
+#define                 AT91_SMC_RWSETUP_(x)    ((x) << 24)
+#define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
+#define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
+
+/* SDRAM Controller registers */
+#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
+#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
+#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
+#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
+#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
+#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
+#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
+#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
+#define                 AT91_SDRAMC_DBW_32      (0 << 4)
+#define                 AT91_SDRAMC_DBW_16      (1 << 4)
+
+#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
+#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
+
+#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
+#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
+#define                 AT91_SDRAMC_NC_8        (0 << 0)
+#define                 AT91_SDRAMC_NC_9        (1 << 0)
+#define                 AT91_SDRAMC_NC_10       (2 << 0)
+#define                 AT91_SDRAMC_NC_11       (3 << 0)
+#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
+#define                 AT91_SDRAMC_NR_11       (0 << 2)
+#define                 AT91_SDRAMC_NR_12       (1 << 2)
+#define                 AT91_SDRAMC_NR_13       (2 << 2)
+#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
+#define                 AT91_SDRAMC_NB_2        (0 << 4)
+#define                 AT91_SDRAMC_NB_4        (1 << 4)
+#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
+#define                 AT91_SDRAMC_CAS_2       (2 << 5)
+#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
+#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
+#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
+#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
+#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
+#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
+#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
+#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
+
+/* Burst Flash Controller register */
+#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
+#define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
+#define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
+#define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
+#define                 AT91_BFC_BFCOM_BURST    (2 << 0)
+#define         AT91_BFC_BFCC           (3   <<  2)             /* Burst Flash Controller Clock */
+#define                 AT91_BFC_BFCC_MCK       (1 << 2)
+#define                 AT91_BFC_BFCC_DIV2      (2 << 2)
+#define                 AT91_BFC_BFCC_DIV4      (3 << 2)
+#define         AT91_BFC_AVL            (0xf <<  4)             /* Address Valid Latency */
+#define         AT91_BFC_PAGES          (7   <<  8)             /* Page Size */
+#define                 AT91_BFC_PAGES_NO_PAGE  (0 << 8)
+#define                 AT91_BFC_PAGES_16       (1 << 8)
+#define                 AT91_BFC_PAGES_32       (2 << 8)
+#define                 AT91_BFC_PAGES_64       (3 << 8)
+#define                 AT91_BFC_PAGES_128      (4 << 8)
+#define                 AT91_BFC_PAGES_256      (5 << 8)
+#define                 AT91_BFC_PAGES_512      (6 << 8)
+#define                 AT91_BFC_PAGES_1024     (7 << 8)
+#define         AT91_BFC_OEL            (3   << 12)             /* Output Enable Latency */
+#define         AT91_BFC_BAAEN          (1   << 16)             /* Burst Address Advance Enable */
+#define         AT91_BFC_BFOEH          (1   << 17)             /* Burst Flash Output Enable Handling */
+#define         AT91_BFC_MUXEN          (1   << 18)             /* Multiplexed Bus Enable */
+#define         AT91_BFC_RDYEN          (1   << 19)             /* Ready Enable Mode */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
deleted file mode 100644
index 73693fea76a2..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_SYS_H
-#define AT91RM9200_SYS_H
-
-/*
- * Advanced Interrupt Controller.
- */
-#define AT91_AIC        0x000
-
-#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
-#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
-#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
-#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
-#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
-#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
-#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
-
-#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
-#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
-#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
-#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
-#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
-
-#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
-#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
-#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
-#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
-#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
-
-#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
-#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
-#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
-#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
-#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
-#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
-#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
-#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
-#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
-
-
-/*
- * Debug Unit.
- */
-#define AT91_DBGU       0x200
-
-#define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
-#define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
-#define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
-#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
-#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
-#define AT91_DBGU_IDR           (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
-#define AT91_DBGU_IMR           (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
-#define AT91_DBGU_SR            (AT91_DBGU + 0x14)      /* Status Register */
-#define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
-#define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
-#define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
-
-#define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
-#define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
-#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
-#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
-#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
-#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
-#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
-#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
-#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
-#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
-
-#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
-
-/*
- * PIO Controllers.
- */
-#define AT91_PIOA       0x400
-#define AT91_PIOB       0x600
-#define AT91_PIOC       0x800
-#define AT91_PIOD       0xa00
-
-#define PIO_PER         0x00    /* Enable Register */
-#define PIO_PDR         0x04    /* Disable Register */
-#define PIO_PSR         0x08    /* Status Register */
-#define PIO_OER         0x10    /* Output Enable Register */
-#define PIO_ODR         0x14    /* Output Disable Register */
-#define PIO_OSR         0x18    /* Output Status Register */
-#define PIO_IFER        0x20    /* Glitch Input Filter Enable */
-#define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
-#define PIO_IFSR        0x28    /* Glitch Input Filter Status */
-#define PIO_SODR        0x30    /* Set Output Data Register */
-#define PIO_CODR        0x34    /* Clear Output Data Register */
-#define PIO_ODSR        0x38    /* Output Data Status Register */
-#define PIO_PDSR        0x3c    /* Pin Data Status Register */
-#define PIO_IER         0x40    /* Interrupt Enable Register */
-#define PIO_IDR         0x44    /* Interrupt Disable Register */
-#define PIO_IMR         0x48    /* Interrupt Mask Register */
-#define PIO_ISR         0x4c    /* Interrupt Status Register */
-#define PIO_MDER        0x50    /* Multi-driver Enable Register */
-#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
-#define PIO_MDSR        0x58    /* Multi-driver Status Register */
-#define PIO_PUDR        0x60    /* Pull-up Disable Register */
-#define PIO_PUER        0x64    /* Pull-up Enable Register */
-#define PIO_PUSR        0x68    /* Pull-up Status Register */
-#define PIO_ASR         0x70    /* Peripheral A Select Register */
-#define PIO_BSR         0x74    /* Peripheral B Select Register */
-#define PIO_ABSR        0x78    /* AB Status Register */
-#define PIO_OWER        0xa0    /* Output Write Enable Register */
-#define PIO_OWDR        0xa4    /* Output Write Disable Register */
-#define PIO_OWSR        0xa8    /* Output Write Status Register */
-
-#define AT91_PIO_P(n)   (1 << (n))
-
-
-/*
- * Power Management Controller.
- */
-#define AT91_PMC        0xc00
-
-#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
-#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
-
-#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
-#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
-#define         AT91_PMC_UDP            (1 <<  1)               /* USB Devcice Port Clock */
-#define         AT91_PMC_MCKUDP         (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend */
-#define         AT91_PMC_UHP            (1 <<  4)               /* USB Host Port Clock */
-#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
-#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
-#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
-#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
-
-#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
-#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
-#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
-
-#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
-#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
-
-#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
-#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
-#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
-
-#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
-#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
-#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
-#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
-#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
-#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
-#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
-
-#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
-#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
-#define                 AT91_PMC_CSS_SLOW               (0 << 0)
-#define                 AT91_PMC_CSS_MAIN               (1 << 0)
-#define                 AT91_PMC_CSS_PLLA               (2 << 0)
-#define                 AT91_PMC_CSS_PLLB               (3 << 0)
-#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
-#define                 AT91_PMC_PRES_1                 (0 << 2)
-#define                 AT91_PMC_PRES_2                 (1 << 2)
-#define                 AT91_PMC_PRES_4                 (2 << 2)
-#define                 AT91_PMC_PRES_8                 (3 << 2)
-#define                 AT91_PMC_PRES_16                (4 << 2)
-#define                 AT91_PMC_PRES_32                (5 << 2)
-#define                 AT91_PMC_PRES_64                (6 << 2)
-#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
-#define                 AT91_PMC_MDIV_1                 (0 << 8)
-#define                 AT91_PMC_MDIV_2                 (1 << 8)
-#define                 AT91_PMC_MDIV_3                 (2 << 8)
-#define                 AT91_PMC_MDIV_4                 (3 << 8)
-
-#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
-
-#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
-#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
-#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
-#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
-#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
-#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
-#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
-#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
-#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
-#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
-#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
-#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
-
-
-/*
- * System Timer.
- */
-#define AT91_ST         0xd00
-
-#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
-#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
-#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
-#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
-#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
-#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
-#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
-#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
-#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
-#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
-#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
-#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
-#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
-#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
-#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
-#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
-#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
-#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
-#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
-#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
-#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
-#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
-
-
-/*
- * Real-time Clock.
- */
-#define AT91_RTC        0xe00
-
-#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
-#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
-#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
-#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
-#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
-#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
-#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
-#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
-#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
-#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
-#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
-#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
-
-#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
-#define         AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
-
-#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
-#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
-#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
-#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
-#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
-
-#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
-#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
-#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
-#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
-#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
-#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
-
-#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
-#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
-#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
-#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
-
-#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
-#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
-#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
-
-#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
-#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
-#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
-#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
-#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
-#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
-
-#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
-#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
-#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
-#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
-
-#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
-#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
-#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
-#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
-#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
-
-
-/*
- * Memory Controller.
- */
-#define AT91_MC         0xf00
-
-#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
-#define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
-
-#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
-#define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
-#define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
-#define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
-#define                 AT91_MC_ABTSZ_BYTE              (0 << 8)
-#define                 AT91_MC_ABTSZ_HALFWORD          (1 << 8)
-#define                 AT91_MC_ABTSZ_WORD              (2 << 8)
-#define         AT91_MC_ABTTYP          (3 << 10)               /* Abort Type Status */
-#define                 AT91_MC_ABTTYP_DATAREAD         (0 << 10)
-#define                 AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
-#define                 AT91_MC_ABTTYP_FETCH            (2 << 10)
-#define         AT91_MC_MST0            (1 << 16)               /* ARM920T Abort Source */
-#define         AT91_MC_MST1            (1 << 17)               /* PDC Abort Source */
-#define         AT91_MC_MST2            (1 << 18)               /* UHP Abort Source */
-#define         AT91_MC_MST3            (1 << 19)               /* EMAC Abort Source */
-#define         AT91_MC_SVMST0          (1 << 24)               /* Saved ARM920T Abort Source */
-#define         AT91_MC_SVMST1          (1 << 25)               /* Saved PDC Abort Source */
-#define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
-#define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
-
-#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
-
-#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
-#define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
-#define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
-#define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
-#define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
-
-/* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
-#define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
-#define                 AT91_EBI_CS0A_SMC               (0 << 0)
-#define                 AT91_EBI_CS0A_BFC               (1 << 0)
-#define         AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
-#define                 AT91_EBI_CS1A_SMC               (0 << 1)
-#define                 AT91_EBI_CS1A_SDRAMC            (1 << 1)
-#define         AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
-#define                 AT91_EBI_CS3A_SMC               (0 << 3)
-#define                 AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
-#define         AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
-#define                 AT91_EBI_CS4A_SMC               (0 << 4)
-#define                 AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
-#define AT91_EBI_CFGR           (AT91_MC + 0x64)        /* Configuration Register */
-#define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
-
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
-#define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
-#define                 AT91_SMC_NWS_(x)        ((x) << 0)
-#define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
-#define         AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
-#define                 AT91_SMC_TDF_(x)        ((x) << 8)
-#define         AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
-#define         AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
-#define                 AT91_SMC_DBW_16         (1 << 13)
-#define                 AT91_SMC_DBW_8          (2 << 13)
-#define         AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
-#define         AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
-#define                 AT91_SMC_ACSS_STD       (0 << 16)
-#define                 AT91_SMC_ACSS_1         (1 << 16)
-#define                 AT91_SMC_ACSS_2         (2 << 16)
-#define                 AT91_SMC_ACSS_3         (3 << 16)
-#define         AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
-#define                 AT91_SMC_RWSETUP_(x)    ((x) << 24)
-#define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
-#define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
-
-/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
-#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
-#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
-#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
-#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
-#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
-#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
-#define                 AT91_SDRAMC_DBW_32      (0 << 4)
-#define                 AT91_SDRAMC_DBW_16      (1 << 4)
-
-#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
-#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
-
-#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
-#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
-#define                 AT91_SDRAMC_NC_8        (0 << 0)
-#define                 AT91_SDRAMC_NC_9        (1 << 0)
-#define                 AT91_SDRAMC_NC_10       (2 << 0)
-#define                 AT91_SDRAMC_NC_11       (3 << 0)
-#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
-#define                 AT91_SDRAMC_NR_11       (0 << 2)
-#define                 AT91_SDRAMC_NR_12       (1 << 2)
-#define                 AT91_SDRAMC_NR_13       (2 << 2)
-#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
-#define                 AT91_SDRAMC_NB_2        (0 << 4)
-#define                 AT91_SDRAMC_NB_4        (1 << 4)
-#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
-#define                 AT91_SDRAMC_CAS_2       (2 << 5)
-#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
-#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
-#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
-#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
-#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
-#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
-#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
-#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
-
-/* Burst Flash Controller register */
-#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
-#define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
-#define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
-#define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
-#define                 AT91_BFC_BFCOM_BURST    (2 << 0)
-#define         AT91_BFC_BFCC           (3   <<  2)             /* Burst Flash Controller Clock */
-#define                 AT91_BFC_BFCC_MCK       (1 << 2)
-#define                 AT91_BFC_BFCC_DIV2      (2 << 2)
-#define                 AT91_BFC_BFCC_DIV4      (3 << 2)
-#define         AT91_BFC_AVL            (0xf <<  4)             /* Address Valid Latency */
-#define         AT91_BFC_PAGES          (7   <<  8)             /* Page Size */
-#define                 AT91_BFC_PAGES_NO_PAGE  (0 << 8)
-#define                 AT91_BFC_PAGES_16       (1 << 8)
-#define                 AT91_BFC_PAGES_32       (2 << 8)
-#define                 AT91_BFC_PAGES_64       (3 << 8)
-#define                 AT91_BFC_PAGES_128      (4 << 8)
-#define                 AT91_BFC_PAGES_256      (5 << 8)
-#define                 AT91_BFC_PAGES_512      (6 << 8)
-#define                 AT91_BFC_PAGES_1024     (7 << 8)
-#define         AT91_BFC_OEL            (3   << 12)             /* Output Enable Latency */
-#define         AT91_BFC_BAAEN          (1   << 16)             /* Burst Address Advance Enable */
-#define         AT91_BFC_BFOEH          (1   << 17)             /* Burst Flash Output Enable Handling */
-#define         AT91_BFC_MUXEN          (1   << 18)             /* Multiplexed Bus Enable */
-#define         AT91_BFC_RDYEN          (1   << 19)             /* Ready Enable Mode */
-
-#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
deleted file mode 100644
index 951e3f61cef4..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * USB Device Port (UDP) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_UDP_H
-#define AT91RM9200_UDP_H
-
-#define AT91_UDP_FRM_NUM        0x00            /* Frame Number Register */
-#define         AT91_UDP_NUM            (0x7ff <<  0)           /* Frame Number */
-#define         AT91_UDP_FRM_ERR        (1     << 16)           /* Frame Error */
-#define         AT91_UDP_FRM_OK         (1     << 17)           /* Frame OK */
-
-#define AT91_UDP_GLB_STAT       0x04            /* Global State Register */
-#define         AT91_UDP_FADDEN         (1 <<  0)               /* Function Address Enable */
-#define         AT91_UDP_CONFG          (1 <<  1)               /* Configured */
-#define         AT91_UDP_ESR            (1 <<  2)               /* Enable Send Resume */
-#define         AT91_UDP_RSMINPR        (1 <<  3)               /* Resume has been sent */
-#define         AT91_UDP_RMWUPE         (1 <<  4)               /* Remote Wake Up Enable */
-
-#define AT91_UDP_FADDR          0x08            /* Function Address Register */
-#define         AT91_UDP_FADD           (0x7f << 0)             /* Function Address Value */
-#define         AT91_UDP_FEN            (1    << 8)             /* Function Enable */
-
-#define AT91_UDP_IER            0x10            /* Interrupt Enable Register */
-#define AT91_UDP_IDR            0x14            /* Interrupt Disable Register */
-#define AT91_UDP_IMR            0x18            /* Interrupt Mask Register */
-
-#define AT91_UDP_ISR            0x1c            /* Interrupt Status Register */
-#define         AT91_UDP_EP(n)          (1 << (n))              /* Endpoint Interrupt Status */
-#define         AT91_UDP_RXSUSP         (1 <<  8)               /* USB Suspend Interrupt Status */
-#define         AT91_UDP_RXRSM          (1 <<  9)               /* USB Resume Interrupt Status */
-#define         AT91_UDP_EXTRSM         (1 << 10)               /* External Resume Interrupt Status */
-#define         AT91_UDP_SOFINT         (1 << 11)               /* Start of Frame Interrupt Status */
-#define         AT91_UDP_ENDBUSRES      (1 << 12)               /* End of Bus Reset Interrpt Status */
-#define         AT91_UDP_WAKEUP         (1 << 13)               /* USB Wakeup Interrupt Status */
-
-#define AT91_UDP_ICR            0x20            /* Interrupt Clear Register */
-#define AT91_UDP_RST_EP         0x28            /* Reset Endpoint Register */
-
-#define AT91_UDP_CSR(n)         (0x30 + ((n) * 4))      /* Endpoint Control/Status Registers 0-7 */
-#define         AT91_UDP_TXCOMP         (1 <<  0)               /* Generates IN packet with data previously written in DPR */
-#define         AT91_UDP_RX_DATA_BK0    (1 <<  1)               /* Receive Data Bank 0 */
-#define         AT91_UDP_RXSETUP        (1 <<  2)               /* Send STALL to the host */
-#define         AT91_UDP_STALLSENT      (1 <<  3)               /* Stall Sent / Isochronous error (Isochronous endpoints) */
-#define         AT91_UDP_TXPKTRDY       (1 <<  4)               /* Transmit Packet Ready */
-#define         AT91_UDP_FORCESTALL     (1 <<  5)               /* Force Stall */
-#define         AT91_UDP_RX_DATA_BK1    (1 <<  6)               /* Receive Data Bank 1 */
-#define         AT91_UDP_DIR            (1 <<  7)               /* Transfer Direction */
-#define         AT91_UDP_EPTYPE         (7 <<  8)               /* Endpoint Type */
-#define                 AT91_UDP_EPTYPE_CTRL            (0 <<  8)
-#define                 AT91_UDP_EPTYPE_ISO_OUT         (1 <<  8)
-#define                 AT91_UDP_EPTYPE_BULK_OUT        (2 <<  8)
-#define                 AT91_UDP_EPTYPE_INT_OUT         (3 <<  8)
-#define                 AT91_UDP_EPTYPE_ISO_IN          (5 <<  8)
-#define                 AT91_UDP_EPTYPE_BULK_IN         (6 <<  8)
-#define                 AT91_UDP_EPTYPE_INT_IN          (7 <<  8)
-#define         AT91_UDP_DTGLE          (1 << 11)               /* Data Toggle */
-#define         AT91_UDP_EPEDS          (1 << 15)               /* Endpoint Enable/Disable */
-#define         AT91_UDP_RXBYTECNT      (0x7ff << 16)           /* Number of bytes in FIFO */
-
-#define AT91_UDP_FDR(n)         (0x50 + ((n) * 4))      /* Endpoint FIFO Data Registers 0-7 */
-
-#define AT91_UDP_TXVC           0x74            /* Transceiver Control Register */
-#define         AT91_UDP_TXVC_TXVDIS    (1 << 8)                /* Transceiver Disable */
-
-#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260.h b/include/asm-arm/arch-at91rm9200/at91sam9260.h
new file mode 100644
index 000000000000..46f4dd65c035
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260.h
@@ -0,0 +1,125 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam9260.h
+ *
+ * (C) 2006 Andrew Victor
+ *
+ * Common definitions.
+ * Based on AT91SAM9260 datasheet revision A (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9260_H
+#define AT91SAM9260_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91SAM9260_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT91SAM9260_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT91SAM9260_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT91SAM9260_ID_ADC      5       /* Analog-to-Digital Converter */
+#define AT91SAM9260_ID_US0      6       /* USART 0 */
+#define AT91SAM9260_ID_US1      7       /* USART 1 */
+#define AT91SAM9260_ID_US2      8       /* USART 2 */
+#define AT91SAM9260_ID_MCI      9       /* Multimedia Card Interface */
+#define AT91SAM9260_ID_UDP      10      /* USB Device Port */
+#define AT91SAM9260_ID_TWI      11      /* Two-Wire Interface */
+#define AT91SAM9260_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT91SAM9260_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT91SAM9260_ID_SSC      14      /* Serial Synchronous Controller */
+#define AT91SAM9260_ID_TC0      17      /* Timer Counter 0 */
+#define AT91SAM9260_ID_TC1      18      /* Timer Counter 1 */
+#define AT91SAM9260_ID_TC2      19      /* Timer Counter 2 */
+#define AT91SAM9260_ID_UHP      20      /* USB Host port */
+#define AT91SAM9260_ID_EMAC     21      /* Ethernet */
+#define AT91SAM9260_ID_ISI      22      /* Image Sensor Interface */
+#define AT91SAM9260_ID_US3      23      /* USART 3 */
+#define AT91SAM9260_ID_US4      24      /* USART 4 */
+#define AT91SAM9260_ID_US5      25      /* USART 5 */
+#define AT91SAM9260_ID_TC3      26      /* Timer Counter 3 */
+#define AT91SAM9260_ID_TC4      27      /* Timer Counter 4 */
+#define AT91SAM9260_ID_TC5      28      /* Timer Counter 5 */
+#define AT91SAM9260_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9260_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9260_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9260_BASE_TCB0           0xfffa0000
+#define AT91SAM9260_BASE_TC0            0xfffa0000
+#define AT91SAM9260_BASE_TC1            0xfffa0040
+#define AT91SAM9260_BASE_TC2            0xfffa0080
+#define AT91SAM9260_BASE_UDP            0xfffa4000
+#define AT91SAM9260_BASE_MCI            0xfffa8000
+#define AT91SAM9260_BASE_TWI            0xfffac000
+#define AT91SAM9260_BASE_US0            0xfffb0000
+#define AT91SAM9260_BASE_US1            0xfffb4000
+#define AT91SAM9260_BASE_US2            0xfffb8000
+#define AT91SAM9260_BASE_SSC            0xfffbc000
+#define AT91SAM9260_BASE_ISI            0xfffc0000
+#define AT91SAM9260_BASE_EMAC           0xfffc4000
+#define AT91SAM9260_BASE_SPI0           0xfffc8000
+#define AT91SAM9260_BASE_SPI1           0xfffcc000
+#define AT91SAM9260_BASE_US3            0xfffd0000
+#define AT91SAM9260_BASE_US4            0xfffd4000
+#define AT91SAM9260_BASE_US5            0xfffd8000
+#define AT91SAM9260_BASE_TCB1           0xfffdc000
+#define AT91SAM9260_BASE_TC3            0xfffdc000
+#define AT91SAM9260_BASE_TC4            0xfffdc040
+#define AT91SAM9260_BASE_TC5            0xfffdc080
+#define AT91SAM9260_BASE_ADC            0xfffe0000
+#define AT91_BASE_SYS                   0xffffe800
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9260_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9260_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9260_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
+#define AT91SAM9260_SRAM0_SIZE  SZ_4K           /* Internal SRAM 0 size (4Kb) */
+#define AT91SAM9260_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
+#define AT91SAM9260_SRAM1_SIZE  SZ_4K           /* Internal SRAM 1 size (4Kb) */
+
+#define AT91SAM9260_UHP_BASE    0x00500000      /* USB Host controller */
+
+#if 0
+/*
+ * PIO pin definitions (peripheral A/B multiplexing).
+ */
+
+// TODO: Add
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
new file mode 100644
index 000000000000..746d973705bf
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
@@ -0,0 +1,78 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9260_MATRIX_H
+#define AT91SAM9260_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x04)    /* Master Configuration Register 5 */
+#define         AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)         /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5 )       /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
+#define                 AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261.h b/include/asm-arm/arch-at91rm9200/at91sam9261.h
new file mode 100644
index 000000000000..8d39672d5b82
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261.h
@@ -0,0 +1,292 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam9261.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91SAM9261 datasheet revision E. (Preliminary)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_H
+#define AT91SAM9261_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91SAM9261_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT91SAM9261_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT91SAM9261_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT91SAM9261_ID_US0      6       /* USART 0 */
+#define AT91SAM9261_ID_US1      7       /* USART 1 */
+#define AT91SAM9261_ID_US2      8       /* USART 2 */
+#define AT91SAM9261_ID_MCI      9       /* Multimedia Card Interface */
+#define AT91SAM9261_ID_UDP      10      /* USB Device Port */
+#define AT91SAM9261_ID_TWI      11      /* Two-Wire Interface */
+#define AT91SAM9261_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT91SAM9261_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT91SAM9261_ID_SSC0     14      /* Serial Synchronous Controller 0 */
+#define AT91SAM9261_ID_SSC1     15      /* Serial Synchronous Controller 1 */
+#define AT91SAM9261_ID_SSC2     16      /* Serial Synchronous Controller 2 */
+#define AT91SAM9261_ID_TC0      17      /* Timer Counter 0 */
+#define AT91SAM9261_ID_TC1      18      /* Timer Counter 1 */
+#define AT91SAM9261_ID_TC2      19      /* Timer Counter 2 */
+#define AT91SAM9261_ID_UHP      20      /* USB Host port */
+#define AT91SAM9261_ID_LCDC     21      /* LDC Controller */
+#define AT91SAM9261_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9261_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9261_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9261_BASE_TCB0           0xfffa0000
+#define AT91SAM9261_BASE_TC0            0xfffa0000
+#define AT91SAM9261_BASE_TC1            0xfffa0040
+#define AT91SAM9261_BASE_TC2            0xfffa0080
+#define AT91SAM9261_BASE_UDP            0xfffa4000
+#define AT91SAM9261_BASE_MCI            0xfffa8000
+#define AT91SAM9261_BASE_TWI            0xfffac000
+#define AT91SAM9261_BASE_US0            0xfffb0000
+#define AT91SAM9261_BASE_US1            0xfffb4000
+#define AT91SAM9261_BASE_US2            0xfffb8000
+#define AT91SAM9261_BASE_SSC0           0xfffbc000
+#define AT91SAM9261_BASE_SSC1           0xfffc0000
+#define AT91SAM9261_BASE_SSC2           0xfffc4000
+#define AT91SAM9261_BASE_SPI0           0xfffc8000
+#define AT91SAM9261_BASE_SPI1           0xfffcc000
+#define AT91_BASE_SYS                   0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9261_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT91SAM9261_SRAM_SIZE   0x00028000      /* Internal SRAM size (160Kb) */
+
+#define AT91SAM9261_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT91SAM9261_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9261_UHP_BASE    0x00500000      /* USB Host controller */
+#define AT91SAM9261_LCDC_BASE   0x00600000      /* LDC controller */
+
+
+#if 0
+/*
+ * PIO pin definitions (peripheral A/B multiplexing).
+ */
+#define AT91_PA0_SPI0_MISO      (1 <<  0)       /* A: SPI0 Master In Slave */
+#define AT91_PA0_MCDA0          (1 <<  0)       /* B: Multimedia Card A Data 0 */
+#define AT91_PA1_SPI0_MOSI      (1 <<  1)       /* A: SPI0 Master Out Slave */
+#define AT91_PA1_MCCDA          (1 <<  1)       /* B: Multimedia Card A Command */
+#define AT91_PA2_SPI0_SPCK      (1 <<  2)       /* A: SPI0 Serial Clock */
+#define AT91_PA2_MCCK           (1 <<  2)       /* B: Multimedia Card Clock */
+#define AT91_PA3_SPI0_NPCS0     (1 <<  3)       /* A: SPI0 Peripheral Chip Select 0 */
+#define AT91_PA4_SPI0_NPCS1     (1 <<  4)       /* A: SPI0 Peripheral Chip Select 1 */
+#define AT91_PA4_MCDA1          (1 <<  4)       /* B: Multimedia Card A Data 1 */
+#define AT91_PA5_SPI0_NPCS2     (1 <<  5)       /* A: SPI0 Peripheral Chip Select 2 */
+#define AT91_PA5_MCDA2          (1 <<  5)       /* B: Multimedia Card A Data 2 */
+#define AT91_PA6_SPI0_NPCS3     (1 <<  6)       /* A: SPI0 Peripheral Chip Select 3 */
+#define AT91_PA6_MCDA3          (1 <<  6)       /* B: Multimedia Card A Data 3 */
+#define AT91_PA7_TWD            (1 <<  7)       /* A: TWI Two-wire Serial Data */
+#define AT91_PA7_PCK0           (1 <<  7)       /* B: PMC Programmable clock Output 0 */
+#define AT91_PA8_TWCK           (1 <<  8)       /* A: TWI Two-wire Serial Clock */
+#define AT91_PA8_PCK1           (1 <<  8)       /* B: PMC Programmable clock Output 1 */
+#define AT91_PA9_DRXD           (1 <<  9)       /* A: DBGU Debug Receive Data */
+#define AT91_PA9_PCK2           (1 <<  9)       /* B: PMC Programmable clock Output 2 */
+#define AT91_PA10_DTXD          (1 << 10)       /* A: DBGU Debug Transmit Data */
+#define AT91_PA10_PCK3          (1 << 10)       /* B: PMC Programmable clock Output 3 */
+#define AT91_PA11_TSYNC         (1 << 11)       /* A: Trace Synchronization Signal */
+#define AT91_PA11_SCK1          (1 << 11)       /* B: USART1 Serial Clock */
+#define AT91_PA12_TCLK          (1 << 12)       /* A: Trace Clock */
+#define AT91_PA12_RTS1          (1 << 12)       /* B: USART1 Ready To Send */
+#define AT91_PA13_TPS0          (1 << 13)       /* A: Trace ARM Pipeline Status 0 */
+#define AT91_PA13_CTS1          (1 << 13)       /* B: USART1 Clear To Send */
+#define AT91_PA14_TPS1          (1 << 14)       /* A: Trace ARM Pipeline Status 1 */
+#define AT91_PA14_SCK2          (1 << 14)       /* B: USART2 Serial Clock */
+#define AT91_PA15_TPS2          (1 << 15)       /* A: Trace ARM Pipeline Status 2 */
+#define AT91_PA15_RTS2          (1 << 15)       /* B: USART2 Ready To Send */
+#define AT91_PA16_TPK0          (1 << 16)       /* A: Trace Packet Port 0 */
+#define AT91_PA16_CTS2          (1 << 16)       /* B: USART2 Clear To Send */
+#define AT91_PA17_TPK1          (1 << 17)       /* A: Trace Packet Port 1 */
+#define AT91_PA17_TF1           (1 << 17)       /* B: SSC1 Transmit Frame Sync */
+#define AT91_PA18_TPK2          (1 << 18)       /* A: Trace Packet Port 2 */
+#define AT91_PA18_TK1           (1 << 18)       /* B: SSC1 Transmit Clock */
+#define AT91_PA19_TPK3          (1 << 19)       /* A: Trace Packet Port 3 */
+#define AT91_PA19_TD1           (1 << 19)       /* B: SSC1 Transmit Data */
+#define AT91_PA20_TPK4          (1 << 20)       /* A: Trace Packet Port 4 */
+#define AT91_PA20_RD1           (1 << 20)       /* B: SSC1 Receive Data */
+#define AT91_PA21_TPK5          (1 << 21)       /* A: Trace Packet Port 5 */
+#define AT91_PA21_RK1           (1 << 21)       /* B: SSC1 Receive Clock */
+#define AT91_PA22_TPK6          (1 << 22)       /* A: Trace Packet Port 6 */
+#define AT91_PA22_RF1           (1 << 22)       /* B: SSC1 Receive Frame Sync */
+#define AT91_PA23_TPK7          (1 << 23)       /* A: Trace Packet Port 7 */
+#define AT91_PA23_RTS0          (1 << 23)       /* B: USART0 Ready To Send */
+#define AT91_PA24_TPK8          (1 << 24)       /* A: Trace Packet Port 8 */
+#define AT91_PA24_SPI1_NPCS1    (1 << 24)       /* B: SPI1 Peripheral Chip Select 1 */
+#define AT91_PA25_TPK9          (1 << 25)       /* A: Trace Packet Port 9 */
+#define AT91_PA25_SPI1_NPCS2    (1 << 25)       /* B: SPI1 Peripheral Chip Select 2 */
+#define AT91_PA26_TPK10         (1 << 26)       /* A: Trace Packet Port 10 */
+#define AT91_PA26_SPI1_NPCS3    (1 << 26)       /* B: SPI1 Peripheral Chip Select 3 */
+#define AT91_PA27_TPK11         (1 << 27)       /* A: Trace Packet Port 11 */
+#define AT91_PA27_SPI0_NPCS1    (1 << 27)       /* B: SPI0 Peripheral Chip Select 1 */
+#define AT91_PA28_TPK12         (1 << 28)       /* A: Trace Packet Port 12 */
+#define AT91_PA28_SPI0_NPCS2    (1 << 28)       /* B: SPI0 Peripheral Chip Select 2 */
+#define AT91_PA29_TPK13         (1 << 29)       /* A: Trace Packet Port 13 */
+#define AT91_PA29_SPI0_NPCS3    (1 << 29)       /* B: SPI0 Peripheral Chip Select 3 */
+#define AT91_PA30_TPK14         (1 << 30)       /* A: Trace Packet Port 14 */
+#define AT91_PA30_A23           (1 << 30)       /* B: Address Bus bit 23 */
+#define AT91_PA31_TPK15         (1 << 31)       /* A: Trace Packet Port 15 */
+#define AT91_PA31_A24           (1 << 31)       /* B: Address Bus bit 24 */
+
+#define AT91_PB0_LCDVSYNC       (1 <<  0)       /* A: LCD Vertical Synchronization */
+#define AT91_PB1_LCDHSYNC       (1 <<  1)       /* A: LCD Horizontal Synchronization */
+#define AT91_PB2_LCDDOTCK       (1 <<  2)       /* A: LCD Dot Clock */
+#define AT91_PB2_PCK0           (1 <<  2)       /* B: PMC Programmable clock Output 0 */
+#define AT91_PB3_LCDDEN         (1 <<  3)       /* A: LCD Data Enable */
+#define AT91_PB4_LCDCC          (1 <<  4)       /* A: LCD Contrast Control */
+#define AT91_PB4_LCDD2          (1 <<  4)       /* B: LCD Data Bus Bit 2 */
+#define AT91_PB5_LCDD0          (1 <<  5)       /* A: LCD Data Bus Bit 0 */
+#define AT91_PB5_LCDD3          (1 <<  5)       /* B: LCD Data Bus Bit 3 */
+#define AT91_PB6_LCDD1          (1 <<  6)       /* A: LCD Data Bus Bit 1 */
+#define AT91_PB6_LCDD4          (1 <<  6)       /* B: LCD Data Bus Bit 4 */
+#define AT91_PB7_LCDD2          (1 <<  7)       /* A: LCD Data Bus Bit 2 */
+#define AT91_PB7_LCDD5          (1 <<  7)       /* B: LCD Data Bus Bit 5 */
+#define AT91_PB8_LCDD3          (1 <<  8)       /* A: LCD Data Bus Bit 3 */
+#define AT91_PB8_LCDD6          (1 <<  8)       /* B: LCD Data Bus Bit 6 */
+#define AT91_PB9_LCDD4          (1 <<  9)       /* A: LCD Data Bus Bit 4 */
+#define AT91_PB9_LCDD7          (1 <<  9)       /* B: LCD Data Bus Bit 7 */
+#define AT91_PB10_LCDD5         (1 << 10)       /* A: LCD Data Bus Bit 5 */
+#define AT91_PB10_LCDD10        (1 << 10)       /* B: LCD Data Bus Bit 10 */
+#define AT91_PB11_LCDD6         (1 << 11)       /* A: LCD Data Bus Bit 6 */
+#define AT91_PB11_LCDD11        (1 << 11)       /* B: LCD Data Bus Bit 11 */
+#define AT91_PB12_LCDD7         (1 << 12)       /* A: LCD Data Bus Bit 7 */
+#define AT91_PB12_LCDD12        (1 << 12)       /* B: LCD Data Bus Bit 12 */
+#define AT91_PB13_LCDD8         (1 << 13)       /* A: LCD Data Bus Bit 8 */
+#define AT91_PB13_LCDD13        (1 << 13)       /* B: LCD Data Bus Bit 13 */
+#define AT91_PB14_LCDD9         (1 << 14)       /* A: LCD Data Bus Bit 9 */
+#define AT91_PB14_LCDD14        (1 << 14)       /* B: LCD Data Bus Bit 14 */
+#define AT91_PB15_LCDD10        (1 << 15)       /* A: LCD Data Bus Bit 10 */
+#define AT91_PB15_LCDD15        (1 << 15)       /* B: LCD Data Bus Bit 15 */
+#define AT91_PB16_LCDD11        (1 << 16)       /* A: LCD Data Bus Bit 11 */
+#define AT91_PB16_LCDD19        (1 << 16)       /* B: LCD Data Bus Bit 19 */
+#define AT91_PB17_LCDD12        (1 << 17)       /* A: LCD Data Bus Bit 12 */
+#define AT91_PB17_LCDD20        (1 << 17)       /* B: LCD Data Bus Bit 20 */
+#define AT91_PB18_LCDD13        (1 << 18)       /* A: LCD Data Bus Bit 13 */
+#define AT91_PB18_LCDD21        (1 << 18)       /* B: LCD Data Bus Bit 21 */
+#define AT91_PB19_LCDD14        (1 << 19)       /* A: LCD Data Bus Bit 14 */
+#define AT91_PB19_LCDD22        (1 << 19)       /* B: LCD Data Bus Bit 22 */
+#define AT91_PB20_LCDD15        (1 << 20)       /* A: LCD Data Bus Bit 15 */
+#define AT91_PB20_LCDD23        (1 << 20)       /* B: LCD Data Bus Bit 23 */
+#define AT91_PB21_TF0           (1 << 21)       /* A: SSC0 Transmit Frame Sync */
+#define AT91_PB21_LCDD16        (1 << 21)       /* B: LCD Data Bus Bit 16 */
+#define AT91_PB22_TK0           (1 << 22)       /* A: SSC0 Transmit Clock */
+#define AT91_PB22_LCDD17        (1 << 22)       /* B: LCD Data Bus Bit 17 */
+#define AT91_PB23_TD0           (1 << 23)       /* A: SSC0 Transmit Data */
+#define AT91_PB23_LCDD18        (1 << 23)       /* B: LCD Data Bus Bit 18 */
+#define AT91_PB24_RD0           (1 << 24)       /* A: SSC0 Receive Data */
+#define AT91_PB24_LCDD19        (1 << 24)       /* B: LCD Data Bus Bit 19 */
+#define AT91_PB25_RK0           (1 << 25)       /* A: SSC0 Receive Clock */
+#define AT91_PB25_LCDD20        (1 << 25)       /* B: LCD Data Bus Bit 20 */
+#define AT91_PB26_RF0           (1 << 26)       /* A: SSC0 Receive Frame Sync */
+#define AT91_PB26_LCDD21        (1 << 26)       /* B: LCD Data Bus Bit 21 */
+#define AT91_PB27_SPI1_NPCS1    (1 << 27)       /* A: SPI1 Peripheral Chip Select 1 */
+#define AT91_PB27_LCDD22        (1 << 27)       /* B: LCD Data Bus Bit 22 */
+#define AT91_PB28_SPI1_NPCS0    (1 << 28)       /* A: SPI1 Peripheral Chip Select 0 */
+#define AT91_PB28_LCDD23        (1 << 28)       /* B: LCD Data Bus Bit 23 */
+#define AT91_PB29_SPI1_SPCK     (1 << 29)       /* A: SPI1 Serial Clock */
+#define AT91_PB29_IRQ2          (1 << 29)       /* B: Interrupt input 2 */
+#define AT91_PB30_SPI1_MISO     (1 << 30)       /* A: SPI1 Master In Slave */
+#define AT91_PB30_IRQ1          (1 << 30)       /* B: Interrupt input 1 */
+#define AT91_PB31_SPI1_MOSI     (1 << 31)       /* A: SPI1 Master Out Slave */
+#define AT91_PB31_PCK2          (1 << 31)       /* B: PMC Programmable clock Output 2 */
+
+#define AT91_PC0_SMOE           (1 << 0)        /* A: SmartMedia Output Enable */
+#define AT91_PC0_NCS6           (1 << 0)        /* B: Chip Select 6 */
+#define AT91_PC1_SMWE           (1 << 1)        /* A: SmartMedia Write Enable */
+#define AT91_PC1_NCS7           (1 << 1)        /* B: Chip Select 7 */
+#define AT91_PC2_NWAIT          (1 << 2)        /* A: NWAIT */
+#define AT91_PC2_IRQ0           (1 << 2)        /* B: Interrupt input 0 */
+#define AT91_PC3_A25_CFRNW      (1 << 3)        /* A: Address Bus[25] / Compact Flash Read Not Write */
+#define AT91_PC4_NCS4_CFCS0     (1 << 4)        /* A: Chip Select 4 / CompactFlash Chip Select 0 */
+#define AT91_PC5_NCS5_CFCS1     (1 << 5)        /* A: Chip Select 5 / CompactFlash Chip Select 1 */
+#define AT91_PC6_CFCE1          (1 << 6)        /* A: CompactFlash Chip Enable 1 */
+#define AT91_PC7_CFCE2          (1 << 7)        /* A: CompactFlash Chip Enable 2 */
+#define AT91_PC8_TXD0           (1 << 8)        /* A: USART0 Transmit Data */
+#define AT91_PC8_PCK2           (1 << 8)        /* B: PMC Programmable clock Output 2 */
+#define AT91_PC9_RXD0           (1 << 9)        /* A: USART0 Receive Data */
+#define AT91_PC9_PCK3           (1 << 9)        /* B: PMC Programmable clock Output 3 */
+#define AT91_PC10_RTS0          (1 << 10)       /* A: USART0 Ready To Send */
+#define AT91_PC10_SCK0          (1 << 10)       /* B: USART0 Serial Clock */
+#define AT91_PC11_CTS0          (1 << 11)       /* A: USART0 Clear To Send */
+#define AT91_PC11_FIQ           (1 << 11)       /* B: AIC Fast Interrupt Input */
+#define AT91_PC12_TXD1          (1 << 12)       /* A: USART1 Transmit Data */
+#define AT91_PC12_NCS6          (1 << 12)       /* B: Chip Select 6 */
+#define AT91_PC13_RXD1          (1 << 13)       /* A: USART1 Receive Data */
+#define AT91_PC13_NCS7          (1 << 13)       /* B: Chip Select 7 */
+#define AT91_PC14_TXD2          (1 << 14)       /* A: USART2 Transmit Data */
+#define AT91_PC14_SPI1_NPCS2    (1 << 14)       /* B: SPI1 Peripheral Chip Select 2 */
+#define AT91_PC15_RXD2          (1 << 15)       /* A: USART2 Receive Data */
+#define AT91_PC15_SPI1_NPCS3    (1 << 15)       /* B: SPI1 Peripheral Chip Select 3 */
+#define AT91_PC16_D16           (1 << 16)       /* A: Data Bus [16] */
+#define AT91_PC16_TCLK0         (1 << 16)       /* B: Timer Counter 0 external clock input */
+#define AT91_PC17_D17           (1 << 17)       /* A: Data Bus [17] */
+#define AT91_PC17_TCLK1         (1 << 17)       /* B: Timer Counter 1 external clock input */
+#define AT91_PC18_D18           (1 << 18)       /* A: Data Bus [18] */
+#define AT91_PC18_TCLK2         (1 << 18)       /* B: Timer Counter 2 external clock input */
+#define AT91_PC19_D19           (1 << 19)       /* A: Data Bus [19] */
+#define AT91_PC19_TIOA0         (1 << 19)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91_PC20_D20           (1 << 20)       /* A: Data Bus [20] */
+#define AT91_PC20_TIOB0         (1 << 20)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91_PC21_D21           (1 << 21)       /* A: Data Bus [21] */
+#define AT91_PC21_TIOA1         (1 << 21)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91_PC22_D22           (1 << 22)       /* A: Data Bus [22] */
+#define AT91_PC22_TIOB1         (1 << 22)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91_PC23_D23           (1 << 23)       /* A: Data Bus [23] */
+#define AT91_PC23_TIOA2         (1 << 23)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91_PC24_D24           (1 << 24)       /* A: Data Bus [24] */
+#define AT91_PC24_TIOB2         (1 << 24)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91_PC25_D25           (1 << 25)       /* A: Data Bus [25] */
+#define AT91_PC25_TF2           (1 << 25)       /* B: SSC2 Transmit Frame Sync */
+#define AT91_PC26_D26           (1 << 26)       /* A: Data Bus [26] */
+#define AT91_PC26_TK2           (1 << 26)       /* B: SSC2 Transmit Clock */
+#define AT91_PC27_D27           (1 << 27)       /* A: Data Bus [27] */
+#define AT91_PC27_TD2           (1 << 27)       /* B: SSC2 Transmit Data */
+#define AT91_PC28_D28           (1 << 28)       /* A: Data Bus [28] */
+#define AT91_PC28_RD2           (1 << 28)       /* B: SSC2 Receive Data */
+#define AT91_PC29_D29           (1 << 29)       /* A: Data Bus [29] */
+#define AT91_PC29_RK2           (1 << 29)       /* B: SSC2 Receive Clock */
+#define AT91_PC30_D30           (1 << 30)       /* A: Data Bus [30] */
+#define AT91_PC30_RF2           (1 << 30)       /* B: SSC2 Receive Frame Sync */
+#define AT91_PC31_D31           (1 << 31)       /* A: Data Bus [31] */
+#define AT91_PC31_PCK1          (1 << 31)       /* B: PMC Programmable clock Output 1 */
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
new file mode 100644
index 000000000000..270a5dcdf1cd
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
@@ -0,0 +1,62 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_MATRIX_H
+#define AT91SAM9261_MATRIX_H
+
+#define AT91_MATRIX_MCFG        (AT91_MATRIX + 0x00)    /* Master Configuration Register */
+#define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT01_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+
+#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define                 AT91_MATRIX_ITCM_64             (7 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+
+#define AT91_MATRIX_USBPUCR     (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
+#define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
new file mode 100644
index 000000000000..7d94968b5d57
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
@@ -0,0 +1,134 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
+ *
+ * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM926x_MC_H
+#define AT91SAM926x_MC_H
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
+#define                 AT91_SDRAMC_MODE_NORMAL         0
+#define                 AT91_SDRAMC_MODE_NOP            1
+#define                 AT91_SDRAMC_MODE_PRECHARGE      2
+#define                 AT91_SDRAMC_MODE_LMR            3
+#define                 AT91_SDRAMC_MODE_REFRESH        4
+#define                 AT91_SDRAMC_MODE_EXT_LMR        5
+#define                 AT91_SDRAMC_MODE_DEEP           6
+
+#define AT91_SDRAMC_TR          (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR          (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
+#define                 AT91_SDRAMC_NC_8        (0 << 0)
+#define                 AT91_SDRAMC_NC_9        (1 << 0)
+#define                 AT91_SDRAMC_NC_10       (2 << 0)
+#define                 AT91_SDRAMC_NC_11       (3 << 0)
+#define         AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
+#define                 AT91_SDRAMC_NR_11       (0 << 2)
+#define                 AT91_SDRAMC_NR_12       (1 << 2)
+#define                 AT91_SDRAMC_NR_13       (2 << 2)
+#define         AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
+#define                 AT91_SDRAMC_NB_2        (0 << 4)
+#define                 AT91_SDRAMC_NB_4        (1 << 4)
+#define         AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
+#define                 AT91_SDRAMC_CAS_1       (1 << 5)
+#define                 AT91_SDRAMC_CAS_2       (2 << 5)
+#define                 AT91_SDRAMC_CAS_3       (3 << 5)
+#define         AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
+#define                 AT91_SDRAMC_DBW_32      (0 << 7)
+#define                 AT91_SDRAMC_DBW_16      (1 << 7)
+#define         AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
+#define         AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
+#define         AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
+#define         AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
+#define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
+#define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR         (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
+#define                 AT91_SDRAMC_LPCB_DISABLE                0
+#define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
+#define                 AT91_SDRAMC_LPCB_POWER_DOWN             2
+#define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
+#define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strenght */
+#define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
+
+#define AT91_SDRAMC_IER         (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR         (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
+#define                 AT91_SDRAMC_MD_SDRAM            0
+#define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
+
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
+#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
+#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
+#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
+#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
+#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
+
+#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
+#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
+#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
+#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
+#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
+#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
+#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
+#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
+
+#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
+#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
+#define         AT91_SMC_EXNWMODE       (3 <<  5)                       /* NWAIT Mode */
+#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 5)
+#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 5)
+#define                 AT91_SMC_EXNWMODE_READY         (3 << 5)
+#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
+#define                 AT91_SMC_BAT_SELECT             (0 << 8)
+#define                 AT91_SMC_BAT_WRITE              (1 << 8)
+#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
+#define                 AT91_SMC_DBW_8                  (0 << 12)
+#define                 AT91_SMC_DBW_16                 (1 << 12)
+#define                 AT91_SMC_DBW_32                 (2 << 12)
+#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
+#define                 AT91_SMC_TDF_(x)                ((x) << 16)
+#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
+#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
+#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
+#define                 AT91_SMC_PS_4                   (0 << 28)
+#define                 AT91_SMC_PS_8                   (1 << 28)
+#define                 AT91_SMC_PS_16                  (2 << 28)
+#define                 AT91_SMC_PS_32                  (3 << 28)
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
index 3cc9aec80f9d..768e0fc6aa2f 100644
--- a/include/asm-arm/arch-at91rm9200/board.h
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -48,13 +48,14 @@ struct at91_cf_data {
         u8      det_pin;                /* Card detect */
         u8      vcc_pin;                /* power switching */
         u8      rst_pin;                /* card reset */
+        u8      chipselect;             /* EBI Chip Select number */
 };
 extern void __init at91_add_device_cf(struct at91_cf_data *data);
 
  /* MMC / SD */
 struct at91_mmc_data {
         u8              det_pin;        /* card detect IRQ */
-        unsigned        is_b:1;         /* uses B side (vs A) */
+        unsigned        slot_b:1;       /* uses Slot B */
         unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
         u8              wp_pin;         /* (SD) writeprotect detect */
         u8              vcc_pin;        /* power switching (high == on) */
@@ -81,7 +82,8 @@ struct at91_nand_data {
         u8              rdy_pin;        /* ready/busy */
         u8              ale;            /* address line number connected to ALE */
         u8              cle;            /* address line number connected to CLE */
-        struct mtd_partition* (*partition_info)(int, int*);
+        u8              bus_width_16;   /* buswidth is 16 bit */
+        struct mtd_partition* (*partition_info)(int, int*);
 };
 extern void __init at91_add_device_nand(struct at91_nand_data *data);
 
diff --git a/include/asm-arm/arch-at91rm9200/cpu.h b/include/asm-arm/arch-at91rm9200/cpu.h
new file mode 100644
index 000000000000..6f8d09b08692
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/cpu.h
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-at91rm9200/cpu.h
+ *
+ *  Copyright (C) 2006 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_CPU_H
+#define __ASM_ARCH_CPU_H
+
+#include <asm/hardware.h>
+#include <asm/arch/at91_dbgu.h>
+
+
+#define ARCH_ID_AT91RM9200      0x09290780
+#define ARCH_ID_AT91SAM9260     0x019803a0
+#define ARCH_ID_AT91SAM9261     0x019703a0
+
+
+static inline unsigned long at91_cpu_identify(void)
+{
+        return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
+}
+
+
+#ifdef CONFIG_ARCH_AT91RM9200
+#define cpu_is_at91rm9200()     (at91_cpu_identify() == ARCH_ID_AT91RM9200)
+#else
+#define cpu_is_at91rm9200()     (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9260
+#define cpu_is_at91sam9260()    (at91_cpu_identify() == ARCH_ID_AT91SAM9260)
+#else
+#define cpu_is_at91sam9260()    (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9261
+#define cpu_is_at91sam9261()    (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
+#else
+#define cpu_is_at91sam9261()    (0)
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S
index f496b54c4c3e..85cdadf26634 100644
--- a/include/asm-arm/arch-at91rm9200/debug-macro.S
+++ b/include/asm-arm/arch-at91rm9200/debug-macro.S
@@ -12,6 +12,7 @@
 */
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_dbgu.h>
 
         .macro  addruart,rx
         mrc     p15, 0, \rx, c1, c0
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S
index 61a326e94909..57248a796472 100644
--- a/include/asm-arm/arch-at91rm9200/entry-macro.S
+++ b/include/asm-arm/arch-at91rm9200/entry-macro.S
@@ -11,6 +11,7 @@
  */
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_aic.h>
 
         .macro  disable_fiq
         .endm
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 9ca4cc9c0b2e..9ea5bfe06320 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -16,8 +16,16 @@
 
 #include <asm/sizes.h>
 
+#if defined(CONFIG_ARCH_AT91RM9200)
 #include <asm/arch/at91rm9200.h>
-#include <asm/arch/at91rm9200_sys.h>
+#elif defined(CONFIG_ARCH_AT91SAM9260)
+#include <asm/arch/at91sam9260.h>
+#elif defined(CONFIG_ARCH_AT91SAM9261)
+#include <asm/arch/at91sam9261.h>
+#else
+#error "Unsupported AT91 processor"
+#endif
+
 
 /*
  * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
@@ -34,29 +42,27 @@
  * Virtual to Physical Address mapping for IO devices.
  */
 #define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91RM9200_BASE_SPI)
 #define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91RM9200_BASE_EMAC)
-#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91RM9200_BASE_TWI)
-#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91RM9200_BASE_MCI)
-#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91RM9200_BASE_UDP)
 
  /* Internal SRAM is mapped below the IO devices */
-#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
+#define AT91_SRAM_MAX           SZ_1M
+#define AT91_VIRT_BASE          (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
 
 /* Serial ports */
-#define ATMEL_MAX_UART          5               /* 4 USART3's and one DBGU port */
-
-/* FLASH */
-#define AT91_FLASH_BASE         0x10000000      /* NCS0: Flash physical base address */
+#define ATMEL_MAX_UART          7               /* 6 USART3's and one DBGU port (SAM9260) */
+
+/* External Memory Map */
+#define AT91_CHIPSELECT_0       0x10000000
+#define AT91_CHIPSELECT_1       0x20000000
+#define AT91_CHIPSELECT_2       0x30000000
+#define AT91_CHIPSELECT_3       0x40000000
+#define AT91_CHIPSELECT_4       0x50000000
+#define AT91_CHIPSELECT_5       0x60000000
+#define AT91_CHIPSELECT_6       0x70000000
+#define AT91_CHIPSELECT_7       0x80000000
 
 /* SDRAM */
-#define AT91_SDRAM_BASE         0x20000000      /* NCS1: SDRAM physical base address */
-
-/* SmartMedia */
-#define AT91_SMARTMEDIA_BASE    0x40000000      /* NCS3: Smartmedia physical base address */
-
-/* Compact Flash */
-#define AT91_CF_BASE            0x50000000      /* NCS4-NCS6: Compact Flash physical base address */
+#define AT91_SDRAM_BASE         AT91_CHIPSELECT_1
 
 /* Clocks */
 #define AT91_SLOW_CLOCK         32768           /* slow clock */
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index 763cb96c418b..c0679eaefaf2 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -21,6 +21,8 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
 
+#include <asm/arch/at91_aic.h>
+
 #define NR_AIC_IRQS 32
 
 
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h
index 8a2ff472e4cf..9c67130603b2 100644
--- a/include/asm-arm/arch-at91rm9200/system.h
+++ b/include/asm-arm/arch-at91rm9200/system.h
@@ -22,6 +22,8 @@
 #define __ASM_ARCH_SYSTEM_H
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_st.h>
+#include <asm/arch/at91_dbgu.h>
 
 static inline void arch_idle(void)
 {
@@ -39,21 +41,13 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
-{
-        /*
-         * Perform a hardware reset with the use of the Watchdog timer.
-         */
-        at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
-        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
-}
-
-#define ARCH_ID_AT91RM9200      0x09200080
-#define ARCH_ID_AT91SAM9261     0x019000a0
+void (*at91_arch_reset)(void);
 
-static inline unsigned long arch_identify(void)
+static inline void arch_reset(char mode)
 {
-        return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH);
+        /* call the CPU-specific reset function */
+        if (at91_arch_reset)
+                (at91_arch_reset)();
 }
 
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/timex.h b/include/asm-arm/arch-at91rm9200/timex.h
index 88687cefe6eb..faeca45a8d44 100644
--- a/include/asm-arm/arch-at91rm9200/timex.h
+++ b/include/asm-arm/arch-at91rm9200/timex.h
@@ -23,6 +23,15 @@
 
 #include <asm/hardware.h>
 
+#if defined(CONFIG_ARCH_AT91RM9200)
+
 #define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
 
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
+
+#define AT91SAM9_MASTER_CLOCK   99300000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#endif
+
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
index ec7811ab0a52..34b4b93fa015 100644
--- a/include/asm-arm/arch-at91rm9200/uncompress.h
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -22,11 +22,11 @@
 #define __ASM_ARCH_UNCOMPRESS_H
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_dbgu.h>
 
 /*
  * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
+ * initialized by the bootloader.  If you didn't setup a port in
  * your bootloader then nothing will appear (which might be desired).
  *
  * This does not append a newline
diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h
index 4c367eb57f47..0a23b8c562b9 100644
--- a/include/asm-arm/arch-at91rm9200/vmalloc.h
+++ b/include/asm-arm/arch-at91rm9200/vmalloc.h
@@ -21,6 +21,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END             (AT91_SRAM_VIRT_BASE & PGDIR_MASK)
+#define VMALLOC_END             (AT91_VIRT_BASE & PGDIR_MASK)
 
 #endif
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index c6e8dcf674de..42768cc8bfb4 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -62,7 +62,15 @@
  * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
  */
 
-#ifdef CONFIG_DISCONTIGMEM
+/*
+ * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
+ * uses only one of the two banks (bank #1).  However, even within
+ * bank #1, memory is discontiguous.
+ *
+ * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
+ * them, so we use 24 for the node max shift to get 16MB node sizes.
+ */
+
 /*
  * Because of the wide memory address space between physical RAM banks on the 
  * SA1100, it's much more convenient to use Linux's NUMA support to implement
@@ -80,48 +88,7 @@
  *      node 2:  0xd0000000 - 0xd7ffffff
  *      node 3:  0xd8000000 - 0xdfffffff
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-                (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr) \
-                        NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
-
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
-
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1).  However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-#define NODE_MAX_MEM_SHIFT      24
-#define NODE_MAX_MEM_SIZE       (1<<NODE_MAX_MEM_SHIFT)
-
-#endif /* CONFIG_DISCONTIGMEM */
+#define NODE_MEM_SIZE_BITS      24
 
 #endif
 
diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h
index 8c91674706b1..e22ba789546c 100644
--- a/include/asm-arm/arch-imx/timex.h
+++ b/include/asm-arm/arch-imx/timex.h
@@ -21,7 +21,6 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
 
-#include <asm/hardware.h>
-#define CLOCK_TICK_RATE         (CLK32)
+#define CLOCK_TICK_RATE         (16000000)
 
 #endif
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S
new file mode 100644
index 000000000000..788b4e386c16
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/debug-macro.S
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-iop13xx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+        .macro  addruart, rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                 @ mmu enabled?
+        moveq   \rx, #0xff000000        @ physical
+        orreq   \rx, \rx, #0x00d80000
+        movne   \rx, #0xfe000000        @ virtual
+        orrne   \rx, \rx, #0x00e80000
+        orr     \rx, \rx, #0x00002300
+        orr     \rx, \rx, #0x00000040
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
new file mode 100644
index 000000000000..2e15da53ff79
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -0,0 +1,3 @@
+#ifndef _IOP13XX_DMA_H
+#define _IOP13XX_DMA_H_
+#endif
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
new file mode 100644
index 000000000000..94c50283dc56
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * iop13xx low level irq macros
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+        .macro  disable_fiq
+        .endm
+
+        /*
+         * Note: a 1-cycle window exists where iintvec will return the value
+         * of iintbase, so we explicitly check for "bad zeros"
+         */
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        mrc     p15, 0, \tmp, c15, c1, 0
+        orr     \tmp, \tmp, #(1 << 6)
+        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
+
+        mrc     p6, 0, \irqnr, c3, c2, 0        @ Read IINTVEC
+        cmp     \irqnr, #0
+        mrceq   p6, 0, \irqnr, c3, c2, 0        @ Re-read on potentially bad zero
+        adds    \irqstat, \irqnr, #1            @ Check for 0xffffffff
+        movne   \irqnr, \irqnr, lsr #2          @ Convert to irqnr
+
+        biceq   \tmp, \tmp, #(1 << 6)
+        mcreq   p15, 0, \tmp, c15, c1, 0        @ Disable cp6 access if no more interrupts
+        .endm
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h
new file mode 100644
index 000000000000..8e1d56289846
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/hardware.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/types.h>
+
+#define pcibios_assign_all_busses() 1
+
+#ifndef __ASSEMBLY__
+extern unsigned long iop13xx_pcibios_min_io;
+extern unsigned long iop13xx_pcibios_min_mem;
+extern u16 iop13xx_dev_id(void);
+extern void iop13xx_set_atu_mmr_bases(void);
+#endif
+
+#define PCIBIOS_MIN_IO      (iop13xx_pcibios_min_io)
+#define PCIBIOS_MIN_MEM     (iop13xx_pcibios_min_mem)
+
+/*
+ * Generic chipset bits
+ *
+ */
+#include "iop13xx.h"
+
+/*
+ * Board specific bits
+ */
+#include "iq81340.h"
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h
new file mode 100644
index 000000000000..db6de2480a24
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/io.h
@@ -0,0 +1,41 @@
+/*
+ * iop13xx custom ioremap implementation
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)      (a)
+#define __mem_pci(a) (a)
+#define __mem_isa(a) (a)
+
+extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
+extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
+        unsigned long flags);
+extern void __iop13xx_iounmap(void __iomem *addr);
+
+extern u32 iop13xx_atue_mem_base;
+extern u32 iop13xx_atux_mem_base;
+extern size_t iop13xx_atue_mem_size;
+extern size_t iop13xx_atux_mem_size;
+
+#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
+#define __arch_iounmap(a)        __iop13xx_iounmap(a)
+
+#endif
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
new file mode 100644
index 000000000000..a88522a0ff8e
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -0,0 +1,492 @@
+#ifndef _IOP13XX_HW_H_
+#define _IOP13XX_HW_H_
+
+#ifndef __ASSEMBLY__
+/* The ATU offsets can change based on the strapping */
+extern u32 iop13xx_atux_pmmr_offset;
+extern u32 iop13xx_atue_pmmr_offset;
+void iop13xx_init_irq(void);
+void iop13xx_map_io(void);
+void iop13xx_platform_init(void);
+void iop13xx_init_irq(void);
+void iop13xx_init_time(unsigned long tickrate);
+unsigned long iop13xx_gettimeoffset(void);
+
+/* handle cp6 access
+ * to do: handle access in entry-armv5.S and unify with
+ * the iop3xx implementation
+ * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
+ * when interrupts are enabled
+ */
+static inline unsigned long iop13xx_cp6_save(void)
+{
+        u32 temp, cp_flags;
+
+        asm volatile (
+                "mrc    p15, 0, %1, c15, c1, 0\n\t"
+                "orr    %0, %1, #(1 << 6)\n\t"
+                "mcr    p15, 0, %0, c15, c1, 0\n\t"
+                : "=r" (temp), "=r"(cp_flags));
+
+        return cp_flags;
+}
+
+static inline void iop13xx_cp6_restore(unsigned long cp_flags)
+{
+        asm volatile (
+                "mcr    p15, 0, %0, c15, c1, 0\n\t"
+                : : "r" (cp_flags) );
+}
+
+/* CPUID CP6 R0 Page 0 */
+static inline int iop13xx_cpu_id(void)
+{
+        int id;
+        asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
+        return id;
+}
+
+#endif
+
+/*
+ * IOP13XX I/O and Mem space regions for PCI autoconfiguration
+ */
+#define IOP13XX_MAX_RAM_SIZE    0x80000000UL  /* 2GB */
+#define IOP13XX_PCI_OFFSET       IOP13XX_MAX_RAM_SIZE
+
+/* PCI MAP
+ * 0x0000.0000 - 0x8000.0000           1:1 mapping with Physical RAM
+ * 0x8000.0000 - 0x8800.0000           PCIX/PCIE memory window (128MB)
+*/
+#define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
+#define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
+#define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
+#define IOP13XX_PCIX_LOWER_IO_BA      0x0fff0000UL
+#define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
+                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
+                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_IO_OFFSET        (IOP13XX_PCIX_LOWER_IO_VA -\
+                                       IOP13XX_PCIX_LOWER_IO_BA)
+#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
+                                           (IOP13XX_PCIX_LOWER_IO_PA\
+                                           - IOP13XX_PCIX_LOWER_IO_VA))
+
+#define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
+#define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
+#define IOP13XX_PCIX_LOWER_MEM_BA     (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
+#define IOP13XX_PCIX_LOWER_MEM_PA     (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
+                                       IOP13XX_PCIX_LOWER_MEM_BA)
+#define IOP13XX_PCIX_UPPER_MEM_PA     (IOP13XX_PCIX_LOWER_MEM_PA +\
+                                       IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_UPPER_MEM_BA     (IOP13XX_PCIX_LOWER_MEM_BA +\
+                                       IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+
+#define IOP13XX_PCIX_MEM_COOKIE        0x80000000UL
+#define IOP13XX_PCIX_LOWER_MEM_RA      IOP13XX_PCIX_MEM_COOKIE
+#define IOP13XX_PCIX_UPPER_MEM_RA      (IOP13XX_PCIX_LOWER_MEM_RA +\
+                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_MEM_OFFSET        (IOP13XX_PCIX_MEM_COOKIE -\
+                                        IOP13XX_PCIX_LOWER_MEM_BA)
+
+/* PCI-E ranges */
+#define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
+#define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
+#define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
+#define IOP13XX_PCIE_LOWER_IO_BA         0x0fff0000UL
+#define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_IO_OFFSET           (IOP13XX_PCIE_LOWER_IO_VA -\
+                                         IOP13XX_PCIE_LOWER_IO_BA)
+#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
+                                           (IOP13XX_PCIE_LOWER_IO_PA\
+                                           - IOP13XX_PCIE_LOWER_IO_VA))
+
+#define IOP13XX_PCIE_MEM_PHYS_OFFSET     0x200000000ULL
+#define IOP13XX_PCIE_MEM_WINDOW_SIZE     0x3a000000UL
+#define IOP13XX_PCIE_LOWER_MEM_BA        (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
+#define IOP13XX_PCIE_LOWER_MEM_PA        (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
+                                         IOP13XX_PCIE_LOWER_MEM_BA)
+#define IOP13XX_PCIE_UPPER_MEM_PA        (IOP13XX_PCIE_LOWER_MEM_PA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_MEM_BA        (IOP13XX_PCIE_LOWER_MEM_BA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+
+/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
+#define IOP13XX_PCIE_MEM_COOKIE          0xc0000000UL
+#define IOP13XX_PCIE_LOWER_MEM_RA        IOP13XX_PCIE_MEM_COOKIE
+#define IOP13XX_PCIE_UPPER_MEM_RA        (IOP13XX_PCIE_LOWER_MEM_RA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_MEM_OFFSET          (IOP13XX_PCIE_MEM_COOKIE -\
+                                         IOP13XX_PCIE_LOWER_MEM_BA)
+
+/* PBI Ranges */
+#define IOP13XX_PBI_LOWER_MEM_PA          0xf0000000UL
+#define IOP13XX_PBI_MEM_WINDOW_SIZE       0x04000000UL
+#define IOP13XX_PBI_MEM_COOKIE            0xfa000000UL
+#define IOP13XX_PBI_LOWER_MEM_RA          IOP13XX_PBI_MEM_COOKIE
+#define IOP13XX_PBI_UPPER_MEM_RA          (IOP13XX_PBI_LOWER_MEM_RA +\
+                                          IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
+
+/*
+ * IOP13XX chipset registers
+ */
+#define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
+#define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
+                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
+                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
+                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
+                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
+                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
+                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR32_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR16_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR8_PHYS(reg)       (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_PMMR_SIZE                  0x00080000
+
+/*=================== Defines for Platform Devices =====================*/
+#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
+#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
+#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
+#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
+
+#define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
+#define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
+#define IOP13XX_I2C2_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
+#define IOP13XX_I2C0_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
+#define IOP13XX_I2C1_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
+#define IOP13XX_I2C2_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
+
+/* ATU selection flags */
+/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
+#define IOP13XX_INIT_ATU_DEFAULT     (0)
+#define IOP13XX_INIT_ATU_ATUX         (1 << 0)
+#define IOP13XX_INIT_ATU_ATUE         (1 << 1)
+#define IOP13XX_INIT_ATU_NONE         (1 << 2)
+
+/* UART selection flags */
+/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
+#define IOP13XX_INIT_UART_DEFAULT    (0)
+#define IOP13XX_INIT_UART_0           (1 << 0)
+#define IOP13XX_INIT_UART_1           (1 << 1)
+
+/* I2C selection flags */
+/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
+#define IOP13XX_INIT_I2C_DEFAULT     (0)
+#define IOP13XX_INIT_I2C_0            (1 << 0)
+#define IOP13XX_INIT_I2C_1            (1 << 1)
+#define IOP13XX_INIT_I2C_2            (1 << 2)
+
+#define IQ81340_NUM_UART     2
+#define IQ81340_NUM_I2C      3
+#define IQ81340_NUM_PHYS_MAP_FLASH 1
+#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
+                                IQ81340_NUM_I2C +\
+                                IQ81340_NUM_PHYS_MAP_FLASH)
+
+/*========================== PMMR offsets for key registers ============*/
+#define IOP13XX_ATU0_PMMR_OFFSET        0x00048000
+#define IOP13XX_ATU1_PMMR_OFFSET        0x0004c000
+#define IOP13XX_ATU2_PMMR_OFFSET        0x0004d000
+#define IOP13XX_ADMA0_PMMR_OFFSET       0x00000000
+#define IOP13XX_ADMA1_PMMR_OFFSET       0x00000200
+#define IOP13XX_ADMA2_PMMR_OFFSET       0x00000400
+#define IOP13XX_PBI_PMMR_OFFSET         0x00001580
+#define IOP13XX_ESSR0_PMMR_OFFSET       0x00002188
+#define IOP13XX_ESSR0                   IOP13XX_REG_ADDR32(0x00002188)
+
+#define IOP13XX_ESSR0_IFACE_MASK        0x00004000  /* Interface PCI-X / PCI-E */
+#define IOP13XX_CONTROLLER_ONLY         (1 << 14)
+#define IOP13XX_INTERFACE_SEL_PCIX      (1 << 15)
+
+#define IOP13XX_PMON_PMMR_OFFSET        0x0001A000
+#define IOP13XX_PMON_BASE               (IOP13XX_PMMR_VIRT_MEM_BASE +\
+                                        IOP13XX_PMON_PMMR_OFFSET)
+#define IOP13XX_PMON_PHYSBASE           (IOP13XX_PMMR_PHYS_MEM_BASE +\
+                                        IOP13XX_PMON_PMMR_OFFSET)
+
+#define IOP13XX_PMON_CMD0               (IOP13XX_PMON_BASE + 0x0)
+#define IOP13XX_PMON_EVR0               (IOP13XX_PMON_BASE + 0x4)
+#define IOP13XX_PMON_STS0               (IOP13XX_PMON_BASE + 0x8)
+#define IOP13XX_PMON_DATA0              (IOP13XX_PMON_BASE + 0xC)
+
+#define IOP13XX_PMON_CMD3               (IOP13XX_PMON_BASE + 0x30)
+#define IOP13XX_PMON_EVR3               (IOP13XX_PMON_BASE + 0x34)
+#define IOP13XX_PMON_STS3               (IOP13XX_PMON_BASE + 0x38)
+#define IOP13XX_PMON_DATA3              (IOP13XX_PMON_BASE + 0x3C)
+
+#define IOP13XX_PMON_CMD7               (IOP13XX_PMON_BASE + 0x70)
+#define IOP13XX_PMON_EVR7               (IOP13XX_PMON_BASE + 0x74)
+#define IOP13XX_PMON_STS7               (IOP13XX_PMON_BASE + 0x78)
+#define IOP13XX_PMON_DATA7              (IOP13XX_PMON_BASE + 0x7C)
+
+#define IOP13XX_PMONEN                  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
+#define IOP13XX_PMONSTAT                (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
+
+/*================================ATU===================================*/
+#define IOP13XX_ATUX_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
+                                        iop13xx_atux_pmmr_offset + (ofs))
+
+#define IOP13XX_ATUX_DID                IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x2)
+
+#define IOP13XX_ATUX_ATUCMD             IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x4)
+#define IOP13XX_ATUX_ATUSR              IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x6)
+
+#define IOP13XX_ATUX_IABAR0             IOP13XX_ATUX_OFFSET(0x10)
+#define IOP13XX_ATUX_IAUBAR0            IOP13XX_ATUX_OFFSET(0x14)
+#define IOP13XX_ATUX_IABAR1             IOP13XX_ATUX_OFFSET(0x18)
+#define IOP13XX_ATUX_IAUBAR1            IOP13XX_ATUX_OFFSET(0x1c)
+#define IOP13XX_ATUX_IABAR2             IOP13XX_ATUX_OFFSET(0x20)
+#define IOP13XX_ATUX_IAUBAR2            IOP13XX_ATUX_OFFSET(0x24)
+#define IOP13XX_ATUX_IALR0              IOP13XX_ATUX_OFFSET(0x40)
+#define IOP13XX_ATUX_IATVR0             IOP13XX_ATUX_OFFSET(0x44)
+#define IOP13XX_ATUX_IAUTVR0            IOP13XX_ATUX_OFFSET(0x48)
+#define IOP13XX_ATUX_IALR1              IOP13XX_ATUX_OFFSET(0x4c)
+#define IOP13XX_ATUX_IATVR1             IOP13XX_ATUX_OFFSET(0x50)
+#define IOP13XX_ATUX_IAUTVR1            IOP13XX_ATUX_OFFSET(0x54)
+#define IOP13XX_ATUX_IALR2              IOP13XX_ATUX_OFFSET(0x58)
+#define IOP13XX_ATUX_IATVR2             IOP13XX_ATUX_OFFSET(0x5c)
+#define IOP13XX_ATUX_IAUTVR2            IOP13XX_ATUX_OFFSET(0x60)
+#define IOP13XX_ATUX_ATUCR              IOP13XX_ATUX_OFFSET(0x70)
+#define IOP13XX_ATUX_PCSR               IOP13XX_ATUX_OFFSET(0x74)
+#define IOP13XX_ATUX_ATUISR             IOP13XX_ATUX_OFFSET(0x78)
+#define IOP13XX_ATUX_PCIXSR             IOP13XX_ATUX_OFFSET(0xD4)
+#define IOP13XX_ATUX_IABAR3             IOP13XX_ATUX_OFFSET(0x200)
+#define IOP13XX_ATUX_IAUBAR3            IOP13XX_ATUX_OFFSET(0x204)
+#define IOP13XX_ATUX_IALR3              IOP13XX_ATUX_OFFSET(0x208)
+#define IOP13XX_ATUX_IATVR3             IOP13XX_ATUX_OFFSET(0x20c)
+#define IOP13XX_ATUX_IAUTVR3            IOP13XX_ATUX_OFFSET(0x210)
+
+#define IOP13XX_ATUX_OIOBAR             IOP13XX_ATUX_OFFSET(0x300)
+#define IOP13XX_ATUX_OIOWTVR            IOP13XX_ATUX_OFFSET(0x304)
+#define IOP13XX_ATUX_OUMBAR0            IOP13XX_ATUX_OFFSET(0x308)
+#define IOP13XX_ATUX_OUMWTVR0           IOP13XX_ATUX_OFFSET(0x30c)
+#define IOP13XX_ATUX_OUMBAR1            IOP13XX_ATUX_OFFSET(0x310)
+#define IOP13XX_ATUX_OUMWTVR1           IOP13XX_ATUX_OFFSET(0x314)
+#define IOP13XX_ATUX_OUMBAR2            IOP13XX_ATUX_OFFSET(0x318)
+#define IOP13XX_ATUX_OUMWTVR2           IOP13XX_ATUX_OFFSET(0x31c)
+#define IOP13XX_ATUX_OUMBAR3            IOP13XX_ATUX_OFFSET(0x320)
+#define IOP13XX_ATUX_OUMWTVR3           IOP13XX_ATUX_OFFSET(0x324)
+#define IOP13XX_ATUX_OUDMABAR           IOP13XX_ATUX_OFFSET(0x328)
+#define IOP13XX_ATUX_OUMSIBAR           IOP13XX_ATUX_OFFSET(0x32c)
+#define IOP13XX_ATUX_OCCAR              IOP13XX_ATUX_OFFSET(0x330)
+#define IOP13XX_ATUX_OCCDR              IOP13XX_ATUX_OFFSET(0x334)
+
+#define IOP13XX_ATUX_ATUCR_OUT_EN               (1 << 1)
+#define IOP13XX_ATUX_PCSR_CENTRAL_RES           (1 << 25)
+#define IOP13XX_ATUX_PCSR_P_RSTOUT              (1 << 21)
+#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY            (1 << 15)
+#define IOP13XX_ATUX_PCSR_IN_Q_BUSY             (1 << 14)
+#define IOP13XX_ATUX_PCSR_FREQ_OFFSET           (16)
+
+#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
+#define IOP13XX_ATUX_STAT_VPD_ADDR              (1 << 17)
+#define IOP13XX_ATUX_STAT_INT_PAR_ERR           (1 << 16)
+#define IOP13XX_ATUX_STAT_CFG_WRITE             (1 << 15)
+#define IOP13XX_ATUX_STAT_ERR_COR               (1 << 14)
+#define IOP13XX_ATUX_STAT_TX_SCEM               (1 << 13)
+#define IOP13XX_ATUX_STAT_REC_SCEM              (1 << 12)
+#define IOP13XX_ATUX_STAT_POWER_TRAN            (1 << 11)
+#define IOP13XX_ATUX_STAT_TX_SERR               (1 << 10)
+#define IOP13XX_ATUX_STAT_DET_PAR_ERR           (1 << 9 )
+#define IOP13XX_ATUX_STAT_BIST                  (1 << 8 )
+#define IOP13XX_ATUX_STAT_INT_REC_MABORT        (1 << 7 )
+#define IOP13XX_ATUX_STAT_REC_SERR              (1 << 4 )
+#define IOP13XX_ATUX_STAT_EXT_REC_MABORT        (1 << 3 )
+#define IOP13XX_ATUX_STAT_EXT_REC_TABORT        (1 << 2 )
+#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT        (1 << 1 )
+#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR       (1 << 0 )
+
+#define IOP13XX_ATUX_PCIXSR_BUS_NUM     (8)
+#define IOP13XX_ATUX_PCIXSR_DEV_NUM     (3)
+#define IOP13XX_ATUX_PCIXSR_FUNC_NUM    (0)
+
+#define IOP13XX_ATUX_IALR_DISABLE       0x00000001
+#define IOP13XX_ATUX_OUMBAR_ENABLE      0x80000000
+
+#define IOP13XX_ATUE_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
+                                        iop13xx_atue_pmmr_offset + (ofs))
+
+#define IOP13XX_ATUE_DID                IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x2)
+#define IOP13XX_ATUE_ATUCMD             IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x4)
+#define IOP13XX_ATUE_ATUSR              IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x6)
+
+#define IOP13XX_ATUE_IABAR0             IOP13XX_ATUE_OFFSET(0x10)
+#define IOP13XX_ATUE_IAUBAR0            IOP13XX_ATUE_OFFSET(0x14)
+#define IOP13XX_ATUE_IABAR1             IOP13XX_ATUE_OFFSET(0x18)
+#define IOP13XX_ATUE_IAUBAR1            IOP13XX_ATUE_OFFSET(0x1c)
+#define IOP13XX_ATUE_IABAR2             IOP13XX_ATUE_OFFSET(0x20)
+#define IOP13XX_ATUE_IAUBAR2            IOP13XX_ATUE_OFFSET(0x24)
+#define IOP13XX_ATUE_IALR0              IOP13XX_ATUE_OFFSET(0x40)
+#define IOP13XX_ATUE_IATVR0             IOP13XX_ATUE_OFFSET(0x44)
+#define IOP13XX_ATUE_IAUTVR0            IOP13XX_ATUE_OFFSET(0x48)
+#define IOP13XX_ATUE_IALR1              IOP13XX_ATUE_OFFSET(0x4c)
+#define IOP13XX_ATUE_IATVR1             IOP13XX_ATUE_OFFSET(0x50)
+#define IOP13XX_ATUE_IAUTVR1            IOP13XX_ATUE_OFFSET(0x54)
+#define IOP13XX_ATUE_IALR2              IOP13XX_ATUE_OFFSET(0x58)
+#define IOP13XX_ATUE_IATVR2             IOP13XX_ATUE_OFFSET(0x5c)
+#define IOP13XX_ATUE_IAUTVR2            IOP13XX_ATUE_OFFSET(0x60)
+#define IOP13XX_ATUE_PE_LSTS            IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0xe2)
+#define IOP13XX_ATUE_OIOWTVR            IOP13XX_ATUE_OFFSET(0x304)
+#define IOP13XX_ATUE_OUMBAR0            IOP13XX_ATUE_OFFSET(0x308)
+#define IOP13XX_ATUE_OUMWTVR0           IOP13XX_ATUE_OFFSET(0x30c)
+#define IOP13XX_ATUE_OUMBAR1            IOP13XX_ATUE_OFFSET(0x310)
+#define IOP13XX_ATUE_OUMWTVR1           IOP13XX_ATUE_OFFSET(0x314)
+#define IOP13XX_ATUE_OUMBAR2            IOP13XX_ATUE_OFFSET(0x318)
+#define IOP13XX_ATUE_OUMWTVR2           IOP13XX_ATUE_OFFSET(0x31c)
+#define IOP13XX_ATUE_OUMBAR3            IOP13XX_ATUE_OFFSET(0x320)
+#define IOP13XX_ATUE_OUMWTVR3           IOP13XX_ATUE_OFFSET(0x324)
+
+#define IOP13XX_ATUE_ATUCR              IOP13XX_ATUE_OFFSET(0x70)
+#define IOP13XX_ATUE_PCSR               IOP13XX_ATUE_OFFSET(0x74)
+#define IOP13XX_ATUE_ATUISR             IOP13XX_ATUE_OFFSET(0x78)
+#define IOP13XX_ATUE_OIOBAR             IOP13XX_ATUE_OFFSET(0x300)
+#define IOP13XX_ATUE_OCCAR              IOP13XX_ATUE_OFFSET(0x32c)
+#define IOP13XX_ATUE_OCCDR              IOP13XX_ATUE_OFFSET(0x330)
+
+#define IOP13XX_ATUE_PIE_STS            IOP13XX_ATUE_OFFSET(0x384)
+#define IOP13XX_ATUE_PIE_MSK            IOP13XX_ATUE_OFFSET(0x388)
+
+#define IOP13XX_ATUE_ATUCR_IVM          (1 << 6)
+#define IOP13XX_ATUE_ATUCR_OUT_EN       (1 << 1)
+#define IOP13XX_ATUE_OCCAR_BUS_NUM      (24)
+#define IOP13XX_ATUE_OCCAR_DEV_NUM      (19)
+#define IOP13XX_ATUE_OCCAR_FUNC_NUM     (16)
+#define IOP13XX_ATUE_OCCAR_EXT_REG      (8)
+#define IOP13XX_ATUE_OCCAR_REG          (2)
+
+#define IOP13XX_ATUE_PCSR_BUS_NUM       (24)
+#define IOP13XX_ATUE_PCSR_DEV_NUM       (19)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM      (16)
+#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY    (1 << 15)
+#define IOP13XX_ATUE_PCSR_IN_Q_BUSY     (1 << 14)
+#define IOP13XX_ATUE_PCSR_END_POINT     (1 << 13)
+#define IOP13XX_ATUE_PCSR_LLRB_BUSY     (1 << 12)
+
+#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK          (0xff)
+#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK          (0x1f)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
+
+#define IOP13XX_ATUE_PCSR_CORE_RESET            (8)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM              (16)
+
+#define IOP13XX_ATUE_LSTS_TRAINING              (1 << 11)
+#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG          (1 << 28)
+#define IOP13XX_ATUE_STAT_PME                   (1 << 27)
+#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG          (1 << 26)
+#define IOP13XX_ATUE_STAT_IVM                   (1 << 25)
+#define IOP13XX_ATUE_STAT_BIST                  (1 << 24)
+#define IOP13XX_ATUE_STAT_CFG_WRITE             (1 << 18)
+#define IOP13XX_ATUE_STAT_VPD_ADDR              (1 << 17)
+#define IOP13XX_ATUE_STAT_POWER_TRAN            (1 << 16)
+#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
+#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR          (1 << 12)
+#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG          (1 << 11)
+#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
+#define IOP13XX_ATUE_STAT_ERR_COR               (1 << 9 )
+#define IOP13XX_ATUE_STAT_ERR_UNCOR             (1 << 8 )
+#define IOP13XX_ATUE_STAT_CRS                   (1 << 7 )
+#define IOP13XX_ATUE_STAT_LNK_DWN               (1 << 6 )
+#define IOP13XX_ATUE_STAT_INT_REC_MABORT        (1 << 5 )
+#define IOP13XX_ATUE_STAT_DET_PAR_ERR           (1 << 4 )
+#define IOP13XX_ATUE_STAT_EXT_REC_MABORT        (1 << 3 )
+#define IOP13XX_ATUE_STAT_SIG_TABORT            (1 << 2 )
+#define IOP13XX_ATUE_STAT_EXT_REC_TABORT        (1 << 1 )
+#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR       (1 << 0 )
+
+#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ     (1 << 31)
+#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT          (1 << 30)
+#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP              (1 << 29)
+#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR                   (1 << 28)
+#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ          (1 << 20)
+#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR         (1 << 19)
+#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP            (1 << 18)
+#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
+#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP          (1 << 16)
+#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT               (1 << 15)
+#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT         (1 << 14)
+#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR             (1 << 13)
+#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP             (1 << 12)
+#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR         (1 << 4 )
+#define IOP13XX_ATUE_ESTAT_TRAINING_ERR         (1 << 0 )
+
+#define IOP13XX_ATUE_IALR_DISABLE               (0x00000001)
+#define IOP13XX_ATUE_OUMBAR_ENABLE              (0x80000000)
+#define IOP13XX_ATU_OUMBAR_FUNC_NUM             (28)
+#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK        (0x7)
+/*=======================================================================*/
+
+/*==============================ADMA UNITS===============================*/
+#define IOP13XX_ADMA_PHYS_BASE(chan)    IOP13XX_REG_ADDR32_PHYS((chan << 9))
+#define IOP13XX_ADMA_UPPER_PA(chan)     (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
+#define IOP13XX_ADMA_OFFSET(chan, ofs)  IOP13XX_REG_ADDR32((chan << 9) + (ofs))
+
+#define IOP13XX_ADMA_ACCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x0)
+#define IOP13XX_ADMA_ACSR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x4)
+#define IOP13XX_ADMA_ADAR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x8)
+#define IOP13XX_ADMA_IIPCR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x18)
+#define IOP13XX_ADMA_IIPAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x1c)
+#define IOP13XX_ADMA_IIPUAR(chan)    IOP13XX_ADMA_OFFSET(chan, 0x20)
+#define IOP13XX_ADMA_ANDAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x24)
+#define IOP13XX_ADMA_ADCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x28)
+#define IOP13XX_ADMA_CARMD(chan)     IOP13XX_ADMA_OFFSET(chan, 0x2c)
+#define IOP13XX_ADMA_ABCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x30)
+#define IOP13XX_ADMA_DLADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x34)
+#define IOP13XX_ADMA_DUADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x38)
+#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
+#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
+
+/*==============================XSI BRIDGE===============================*/
+#define IOP13XX_XBG_BECSR               IOP13XX_REG_ADDR32(0x178c)
+#define IOP13XX_XBG_BERAR               IOP13XX_REG_ADDR32(0x1790)
+#define IOP13XX_XBG_BERUAR              IOP13XX_REG_ADDR32(0x1794)
+#define is_atue_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
+                                        IOP13XX_PMMR_VIRT_TO_PHYS(\
+                                        IOP13XX_ATUE_OCCDR))\
+                                        && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
+#define is_atux_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
+                                        IOP13XX_PMMR_VIRT_TO_PHYS(\
+                                        IOP13XX_ATUX_OCCDR))\
+                                        && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
+/*=======================================================================*/
+
+#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
+                                                        (ofs))
+
+#define IOP13XX_PBI_CR                  IOP13XX_PBI_OFFSET(0x0)
+#define IOP13XX_PBI_SR                  IOP13XX_PBI_OFFSET(0x4)
+#define IOP13XX_PBI_BAR0                IOP13XX_PBI_OFFSET(0x8)
+#define IOP13XX_PBI_LR0                 IOP13XX_PBI_OFFSET(0xc)
+#define IOP13XX_PBI_BAR1                IOP13XX_PBI_OFFSET(0x10)
+#define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
+
+#define IOP13XX_TMR_TC                  0x01
+#define IOP13XX_TMR_EN                  0x02
+#define IOP13XX_TMR_RELOAD              0x04
+#define IOP13XX_TMR_PRIVILEGED          0x08
+
+#define IOP13XX_TMR_RATIO_1_1           0x00
+#define IOP13XX_TMR_RATIO_4_1           0x10
+#define IOP13XX_TMR_RATIO_8_1           0x20
+#define IOP13XX_TMR_RATIO_16_1          0x30
+
+#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h
new file mode 100644
index 000000000000..b98f8f109c22
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iq81340.h
@@ -0,0 +1,31 @@
+#ifndef _IQ81340_H_
+#define _IQ81340_H_
+
+#define IQ81340_PCE_BAR0    IOP13XX_PBI_LOWER_MEM_RA
+#define IQ81340_PCE_BAR1    (IQ81340_PCE_BAR0 + 0x02000000)
+
+#define IQ81340_FLASHBASE   IQ81340_PCE_BAR0    /* Flash */
+
+#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
+
+#define IQ81340_PRD_CODE    IQ81340_PCE_BAR1_OFFSET(0)
+#define IQ81340_BRD_STEP    IQ81340_PCE_BAR1_OFFSET(0x10000)
+#define IQ81340_CPLD_REV    IQ81340_PCE_BAR1_OFFSET(0x20000)
+#define IQ81340_LED          IQ81340_PCE_BAR1_OFFSET(0x30000)
+#define IQ81340_LHEX         IQ81340_PCE_BAR1_OFFSET(0x40000)
+#define IQ81340_RHEX         IQ81340_PCE_BAR1_OFFSET(0x50000)
+#define IQ81340_BUZZER       IQ81340_PCE_BAR1_OFFSET(0x60000)
+#define IQ81340_32K_NVRAM   IQ81340_PCE_BAR1_OFFSET(0x70000)
+#define IQ81340_256K_NVRAM  IQ81340_PCE_BAR1_OFFSET(0x80000)
+#define IQ81340_ROTARY_SW   IQ81340_PCE_BAR1_OFFSET(0xd0000)
+#define IQ81340_BATT_STAT   IQ81340_PCE_BAR1_OFFSET(0xf0000)
+#define IQ81340_CMP_FLSH    IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
+
+#define PBI_CF_IDE_BASE     (IQ81340_CMP_FLSH)
+#define PBI_CF_BAR_ADDR     (IOP13XX_PBI_BAR1)
+
+/* These are the values used in the Machine description */
+#define PHYS_IO         0xfeffff00
+#define IO_PG_OFFSET    0xffffff00
+#define BOOT_PARAM_OFFSET  0x00000100
+#endif  /* _IQ81340_H_ */
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
new file mode 100644
index 000000000000..442e35a40359
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -0,0 +1,207 @@
+#ifndef _IOP13XX_IRQS_H_
+#define _IOP13XX_IRQS_H_
+
+#ifndef __ASSEMBLER__
+#include <linux/types.h>
+#include <asm/system.h> /* local_irq_save */
+#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
+
+/* INTPND0 CP6 R0 Page 3
+ */
+static inline u32 read_intpnd_0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
+        return val;
+}
+
+/* INTPND1 CP6 R1 Page 3
+ */
+static inline u32 read_intpnd_1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
+        return val;
+}
+
+/* INTPND2 CP6 R2 Page 3
+ */
+static inline u32 read_intpnd_2(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
+        return val;
+}
+
+/* INTPND3 CP6 R3 Page 3
+ */
+static inline u32 read_intpnd_3(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
+        return val;
+}
+
+static inline void
+iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
+{
+        local_irq_save(*irq_flags);
+        *cp_flags = iop13xx_cp6_save();
+}
+
+static inline void
+iop13xx_cp6_irq_restore(unsigned long *cp_flags,
+        unsigned long *irq_flags)
+{
+        iop13xx_cp6_restore(*cp_flags);
+        local_irq_restore(*irq_flags);
+}
+#endif
+
+#define INTBASE 0
+#define INTSIZE_4 1
+
+/*
+ * iop34x chipset interrupts
+ */
+#define IOP13XX_IRQ(x)          (IOP13XX_IRQ_OFS + (x))
+
+/*
+ * On IRQ or FIQ register
+ */
+#define IRQ_IOP13XX_ADMA0_EOT   (0)
+#define IRQ_IOP13XX_ADMA0_EOC   (1)
+#define IRQ_IOP13XX_ADMA1_EOT   (2)
+#define IRQ_IOP13XX_ADMA1_EOC   (3)
+#define IRQ_IOP13XX_ADMA2_EOT   (4)
+#define IRQ_IOP13XX_ADMA2_EOC   (5)
+#define IRQ_IOP134_WATCHDOG     (6)
+#define IRQ_IOP13XX_RSVD_7      (7)
+#define IRQ_IOP13XX_TIMER0      (8)
+#define IRQ_IOP13XX_TIMER1      (9)
+#define IRQ_IOP13XX_I2C_0       (10)
+#define IRQ_IOP13XX_I2C_1       (11)
+#define IRQ_IOP13XX_MSG (12)
+#define IRQ_IOP13XX_MSGIBQ      (13)
+#define IRQ_IOP13XX_ATU_IM      (14)
+#define IRQ_IOP13XX_ATU_BIST    (15)
+#define IRQ_IOP13XX_PPMU        (16)
+#define IRQ_IOP13XX_COREPMU     (17)
+#define IRQ_IOP13XX_CORECACHE   (18)
+#define IRQ_IOP13XX_RSVD_19     (19)
+#define IRQ_IOP13XX_RSVD_20     (20)
+#define IRQ_IOP13XX_RSVD_21     (21)
+#define IRQ_IOP13XX_RSVD_22     (22)
+#define IRQ_IOP13XX_RSVD_23     (23)
+#define IRQ_IOP13XX_XINT0       (24)
+#define IRQ_IOP13XX_XINT1       (25)
+#define IRQ_IOP13XX_XINT2       (26)
+#define IRQ_IOP13XX_XINT3       (27)
+#define IRQ_IOP13XX_XINT4       (28)
+#define IRQ_IOP13XX_XINT5       (29)
+#define IRQ_IOP13XX_XINT6       (30)
+#define IRQ_IOP13XX_XINT7       (31)
+                                      /* IINTSRC1 bit */
+#define IRQ_IOP13XX_XINT8       (32)  /* 0  */
+#define IRQ_IOP13XX_XINT9       (33)  /* 1  */
+#define IRQ_IOP13XX_XINT10      (34)  /* 2  */
+#define IRQ_IOP13XX_XINT11      (35)  /* 3  */
+#define IRQ_IOP13XX_XINT12      (36)  /* 4  */
+#define IRQ_IOP13XX_XINT13      (37)  /* 5  */
+#define IRQ_IOP13XX_XINT14      (38)  /* 6  */
+#define IRQ_IOP13XX_XINT15      (39)  /* 7  */
+#define IRQ_IOP13XX_RSVD_40     (40)  /* 8  */
+#define IRQ_IOP13XX_RSVD_41     (41)  /* 9  */
+#define IRQ_IOP13XX_RSVD_42     (42)  /* 10 */
+#define IRQ_IOP13XX_RSVD_43     (43)  /* 11 */
+#define IRQ_IOP13XX_RSVD_44     (44)  /* 12 */
+#define IRQ_IOP13XX_RSVD_45     (45)  /* 13 */
+#define IRQ_IOP13XX_RSVD_46     (46)  /* 14 */
+#define IRQ_IOP13XX_RSVD_47     (47)  /* 15 */
+#define IRQ_IOP13XX_RSVD_48     (48)  /* 16 */
+#define IRQ_IOP13XX_RSVD_49     (49)  /* 17 */
+#define IRQ_IOP13XX_RSVD_50     (50)  /* 18 */
+#define IRQ_IOP13XX_UART0       (51)  /* 19 */
+#define IRQ_IOP13XX_UART1       (52)  /* 20 */
+#define IRQ_IOP13XX_PBIE        (53)  /* 21 */
+#define IRQ_IOP13XX_ATU_CRW     (54)  /* 22 */
+#define IRQ_IOP13XX_ATU_ERR     (55)  /* 23 */
+#define IRQ_IOP13XX_MCU_ERR     (56)  /* 24 */
+#define IRQ_IOP13XX_ADMA0_ERR   (57)  /* 25 */
+#define IRQ_IOP13XX_ADMA1_ERR   (58)  /* 26 */
+#define IRQ_IOP13XX_ADMA2_ERR   (59)  /* 27 */
+#define IRQ_IOP13XX_RSVD_60     (60)  /* 28 */
+#define IRQ_IOP13XX_RSVD_61     (61)  /* 29 */
+#define IRQ_IOP13XX_MSG_ERR     (62)  /* 30 */
+#define IRQ_IOP13XX_RSVD_63     (63)  /* 31 */
+                                      /* IINTSRC2 bit */
+#define IRQ_IOP13XX_INTERPROC   (64)  /* 0  */
+#define IRQ_IOP13XX_RSVD_65     (65)  /* 1  */
+#define IRQ_IOP13XX_RSVD_66     (66)  /* 2  */
+#define IRQ_IOP13XX_RSVD_67     (67)  /* 3  */
+#define IRQ_IOP13XX_RSVD_68     (68)  /* 4  */
+#define IRQ_IOP13XX_RSVD_69     (69)  /* 5  */
+#define IRQ_IOP13XX_RSVD_70     (70)  /* 6  */
+#define IRQ_IOP13XX_RSVD_71     (71)  /* 7  */
+#define IRQ_IOP13XX_RSVD_72     (72)  /* 8  */
+#define IRQ_IOP13XX_RSVD_73     (73)  /* 9  */
+#define IRQ_IOP13XX_RSVD_74     (74)  /* 10 */
+#define IRQ_IOP13XX_RSVD_75     (75)  /* 11 */
+#define IRQ_IOP13XX_RSVD_76     (76)  /* 12 */
+#define IRQ_IOP13XX_RSVD_77     (77)  /* 13 */
+#define IRQ_IOP13XX_RSVD_78     (78)  /* 14 */
+#define IRQ_IOP13XX_RSVD_79     (79)  /* 15 */
+#define IRQ_IOP13XX_RSVD_80     (80)  /* 16 */
+#define IRQ_IOP13XX_RSVD_81     (81)  /* 17 */
+#define IRQ_IOP13XX_RSVD_82     (82)  /* 18 */
+#define IRQ_IOP13XX_RSVD_83     (83)  /* 19 */
+#define IRQ_IOP13XX_RSVD_84     (84)  /* 20 */
+#define IRQ_IOP13XX_RSVD_85     (85)  /* 21 */
+#define IRQ_IOP13XX_RSVD_86     (86)  /* 22 */
+#define IRQ_IOP13XX_RSVD_87     (87)  /* 23 */
+#define IRQ_IOP13XX_RSVD_88     (88)  /* 24 */
+#define IRQ_IOP13XX_RSVD_89     (89)  /* 25 */
+#define IRQ_IOP13XX_RSVD_90     (90)  /* 26 */
+#define IRQ_IOP13XX_RSVD_91     (91)  /* 27 */
+#define IRQ_IOP13XX_RSVD_92     (92)  /* 28 */
+#define IRQ_IOP13XX_RSVD_93     (93)  /* 29 */
+#define IRQ_IOP13XX_SIB_ERR     (94)  /* 30 */
+#define IRQ_IOP13XX_SRAM_ERR    (95)  /* 31 */
+                                      /* IINTSRC3 bit */
+#define IRQ_IOP13XX_I2C_2       (96)  /* 0  */
+#define IRQ_IOP13XX_ATUE_BIST   (97)  /* 1  */
+#define IRQ_IOP13XX_ATUE_CRW    (98)  /* 2  */
+#define IRQ_IOP13XX_ATUE_ERR    (99)  /* 3  */
+#define IRQ_IOP13XX_IMU (100) /* 4  */
+#define IRQ_IOP13XX_RSVD_101    (101) /* 5  */
+#define IRQ_IOP13XX_RSVD_102    (102) /* 6  */
+#define IRQ_IOP13XX_TPMI0_OUT   (103) /* 7  */
+#define IRQ_IOP13XX_TPMI1_OUT   (104) /* 8  */
+#define IRQ_IOP13XX_TPMI2_OUT   (105) /* 9  */
+#define IRQ_IOP13XX_TPMI3_OUT   (106) /* 10 */
+#define IRQ_IOP13XX_ATUE_IMA    (107) /* 11 */
+#define IRQ_IOP13XX_ATUE_IMB    (108) /* 12 */
+#define IRQ_IOP13XX_ATUE_IMC    (109) /* 13 */
+#define IRQ_IOP13XX_ATUE_IMD    (110) /* 14 */
+#define IRQ_IOP13XX_MU_MSI_TB   (111) /* 15 */
+#define IRQ_IOP13XX_RSVD_112    (112) /* 16 */
+#define IRQ_IOP13XX_RSVD_113    (113) /* 17 */
+#define IRQ_IOP13XX_RSVD_114    (114) /* 18 */
+#define IRQ_IOP13XX_RSVD_115    (115) /* 19 */
+#define IRQ_IOP13XX_RSVD_116    (116) /* 20 */
+#define IRQ_IOP13XX_RSVD_117    (117) /* 21 */
+#define IRQ_IOP13XX_RSVD_118    (118) /* 22 */
+#define IRQ_IOP13XX_RSVD_119    (119) /* 23 */
+#define IRQ_IOP13XX_RSVD_120    (120) /* 24 */
+#define IRQ_IOP13XX_RSVD_121    (121) /* 25 */
+#define IRQ_IOP13XX_RSVD_122    (122) /* 26 */
+#define IRQ_IOP13XX_RSVD_123    (123) /* 27 */
+#define IRQ_IOP13XX_RSVD_124    (124) /* 28 */
+#define IRQ_IOP13XX_RSVD_125    (125) /* 29 */
+#define IRQ_IOP13XX_RSVD_126    (126) /* 30 */
+#define IRQ_IOP13XX_HPI (127) /* 31 */
+
+#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
+#define NR_IRQS         NR_IOP13XX_IRQS
+
+#endif /* _IOP13XX_IRQ_H_ */
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h
new file mode 100644
index 000000000000..031a0fa78eff
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/memory.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/arch/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+#define TASK_SIZE       UL(0x3f000000)
+#define PAGE_OFFSET     UL(0x40000000)
+#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_ARCH_IOP13XX)
+#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
+#define IOP13XX_PMMR_V_END   (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
+#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
+#define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
+
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+/* RAM has 1:1 mapping on the PCIe/x Busses */
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)    (__phys_to_virt(x))
+
+#define virt_to_lbus(x)                                            \
+(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) &&                  \
+((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ?                       \
+((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
+((x) - PAGE_OFFSET + PHYS_OFFSET))
+
+#define lbus_to_virt(x)                                            \
+(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
+((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
+((x) - PHYS_OFFSET + PAGE_OFFSET))
+
+/* Device is an lbus device if it is on the platform bus of the IOP13XX */
+#define is_lbus_device(dev) (dev &&\
+                             (strncmp(dev->bus->name, "platform", 8) == 0))
+
+#define __arch_page_to_dma(dev, page)                                   \
+({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
+(dma_addr_t)__virt_to_bus(page_address(page));})
+
+#define __arch_dma_to_virt(dev, addr) \
+({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
+
+#define __arch_virt_to_dma(dev, addr) \
+({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
+
+#endif /* CONFIG_ARCH_IOP13XX */
+#endif /* !ASSEMBLY */
+
+#define PFN_TO_NID(addr)        (0)
+
+#endif
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h
new file mode 100644
index 000000000000..4041f30d4cd3
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/pci.h
@@ -0,0 +1,57 @@
+#ifndef _IOP13XX_PCI_H_
+#define _IOP13XX_PCI_H_
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+
+struct pci_sys_data;
+struct hw_pci;
+int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
+struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
+void iop13xx_atu_select(struct hw_pci *plat_pci);
+void iop13xx_pci_init(void);
+void iop13xx_map_pci_memory(void);
+
+#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY |            \
+                               PCI_STATUS_SIG_TARGET_ABORT | \
+                               PCI_STATUS_REC_TARGET_ABORT | \
+                               PCI_STATUS_REC_TARGET_ABORT | \
+                               PCI_STATUS_REC_MASTER_ABORT | \
+                               PCI_STATUS_SIG_SYSTEM_ERROR | \
+                               PCI_STATUS_DETECTED_PARITY)
+
+#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR |  \
+                                    IOP13XX_ATUE_STAT_ROOT_SYS_ERR |   \
+                                    IOP13XX_ATUE_STAT_PCI_IFACE_ERR |  \
+                                    IOP13XX_ATUE_STAT_ERR_COR |        \
+                                    IOP13XX_ATUE_STAT_ERR_UNCOR |      \
+                                    IOP13XX_ATUE_STAT_CRS |            \
+                                    IOP13XX_ATUE_STAT_DET_PAR_ERR |    \
+                                    IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
+                                    IOP13XX_ATUE_STAT_SIG_TABORT |     \
+                                    IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
+                                    IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
+
+#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM |        \
+                                    IOP13XX_ATUX_STAT_REC_SCEM |       \
+                                    IOP13XX_ATUX_STAT_TX_SERR |        \
+                                    IOP13XX_ATUX_STAT_DET_PAR_ERR |    \
+                                    IOP13XX_ATUX_STAT_INT_REC_MABORT | \
+                                    IOP13XX_ATUX_STAT_REC_SERR |       \
+                                    IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
+                                    IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
+                                    IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
+                                    IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
+
+/* PCI interrupts
+ */
+#define ATUX_INTA IRQ_IOP13XX_XINT0
+#define ATUX_INTB IRQ_IOP13XX_XINT1
+#define ATUX_INTC IRQ_IOP13XX_XINT2
+#define ATUX_INTD IRQ_IOP13XX_XINT3
+
+#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
+#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
+#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
+#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
+
+#endif /* _IOP13XX_PCI_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
new file mode 100644
index 000000000000..ee3a62530af2
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -0,0 +1,59 @@
+/*
+ * linux/include/asm-arm/arch-iop13xx/system.h
+ *
+ *  Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/arch/iop13xx.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+/* WDTCR CP6 R7 Page 9 */
+static inline u32 read_wdtcr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
+}
+
+/* WDTSR CP6 R8 Page 9 */
+static inline u32 read_wdtsr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtsr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
+}
+
+#define IOP13XX_WDTCR_EN_ARM    0x1e1e1e1e
+#define IOP13XX_WDTCR_EN        0xe1e1e1e1
+#define IOP13XX_WDTCR_DIS_ARM   0x1f1f1f1f
+#define IOP13XX_WDTCR_DIS       0xf1f1f1f1
+#define IOP13XX_WDTSR_WRITE_EN  (1 << 31)
+#define IOP13XX_WDTCR_IB_RESET  (1 << 0)
+static inline void arch_reset(char mode)
+{
+        /*
+         * Reset the internal bus (warning both cores are reset)
+         */
+        u32 cp_flags = iop13xx_cp6_save();
+        write_wdtcr(IOP13XX_WDTCR_EN_ARM);
+        write_wdtcr(IOP13XX_WDTCR_EN);
+        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
+        write_wdtcr(0x1000);
+        iop13xx_cp6_restore(cp_flags);
+
+        for(;;);
+}
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h
new file mode 100644
index 000000000000..f0c51dd97ed8
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/timex.h
@@ -0,0 +1,3 @@
+#include <asm/hardware.h>
+
+#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
new file mode 100644
index 000000000000..b9525d59b7ad
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -0,0 +1,24 @@
+#include <asm/types.h>
+#include <linux/serial_reg.h>
+#include <asm/hardware.h>
+#include <asm/processor.h>
+
+#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
+#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
+
+static inline void putc(char c)
+{
+        while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
+                cpu_relax();
+        UART_BASE[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h
new file mode 100644
index 000000000000..c53456740345
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/vmalloc.h
@@ -0,0 +1,4 @@
+#ifndef _VMALLOC_H_
+#define _VMALLOC_H_
+#define VMALLOC_END     0xfa000000UL
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
index 4281838873ef..6b437f7c9955 100644
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -76,6 +76,7 @@
 
 #define NSLU2_GPIO_BUZZ         4
 #define NSLU2_BZ_BM             (1L << NSLU2_GPIO_BUZZ)
+
 /* LEDs */
 
 #define NSLU2_LED_RED           NSLU2_GPIO0
@@ -84,8 +85,8 @@
 #define NSLU2_LED_RED_BM        (1L << NSLU2_LED_RED)
 #define NSLU2_LED_GRN_BM        (1L << NSLU2_LED_GRN)
 
-#define NSLU2_LED_DISK1         NSLU2_GPIO2
-#define NSLU2_LED_DISK2         NSLU2_GPIO3
+#define NSLU2_LED_DISK1         NSLU2_GPIO3
+#define NSLU2_LED_DISK2         NSLU2_GPIO2
 
 #define NSLU2_LED_DISK1_BM      (1L << NSLU2_GPIO2)
 #define NSLU2_LED_DISK2_BM      (1L << NSLU2_GPIO3)
diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h
new file mode 100644
index 000000000000..dbdec36ff0d1
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/udc.h
@@ -0,0 +1,8 @@
+/*
+ * linux/include/asm-arm/arch-ixp4xx/udc.h
+ *
+ */
+#include <asm/mach/udc_pxa2xx.h>
+
+extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
+
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index d744d97c18a5..645dbdfb3908 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -17,59 +17,11 @@
 /*
  * There are not real ISA nor PCI buses, so we fake it.
  */
-#define __io_pci(a)             ((void __iomem *)(PCIO_BASE + (a)))
-#define __mem_pci(a)            (a)
-
-#define __ioaddr(p)             __io_pci(p)
-
-/*
- * Generic virtual read/write
- */
-#define __arch_getb(a)          (*(volatile unsigned char *)(a))
-#define __arch_getl(a)          (*(volatile unsigned int  *)(a))
-
-static inline unsigned int __arch_getw(unsigned long a)
-{
-        unsigned int value;
-        __asm__ __volatile__("ldrh    %0, [%1, #0]    @ getw"
-                : "=&r" (value)
-                : "r" (a) : "cc");
-        return value;
-}
-
-#define __arch_putb(v,a)        (*(volatile unsigned char *)(a) = (v))
-#define __arch_putl(v,a)        (*(volatile unsigned int  *)(a) = (v))
-
-static inline void __arch_putw(unsigned int value, unsigned long a)
+static inline void __iomem *__io(unsigned long addr)
 {
-        __asm__ __volatile__("strh    %0, [%1, #0]    @ putw"
-                : : "r" (value), "r" (a) : "cc");
+        return (void __iomem *)addr;
 }
-
-/*
- * Translated address IO functions
- *
- * IO address has already been translated to a virtual address
- */
-#define outb_t(v,p)             (*(volatile unsigned char *)(p) = (v))
-#define inb_t(p)                (*(volatile unsigned char *)(p))
-#define outw_t(v,p)             (*(volatile unsigned int *)(p) = (v))
-#define inw_t(p)                (*(volatile unsigned int *)(p))
-#define outl_t(v,p)             (*(volatile unsigned long *)(p) = (v))
-#define inl_t(p)                (*(volatile unsigned long *)(p))
-
-/*
- * FIXME - These are to allow for linking. On all the other
- *         ARM platforms, the entire IO space is contiguous.
- *         The 7200 has three separate IO spaces. The below
- *         macros will eventually become more involved. Use
- *         with caution and don't be surprised by kernel oopses!!!
- */
-#define inb(p)                  inb_t(p)
-#define inw(p)                  inw_t(p)
-#define inl(p)                  inl_t(p)
-#define outb(v,p)               outb_t(v,p)
-#define outw(v,p)               outw_t(v,p)
-#define outl(v,p)               outl_t(v,p)
+#define __io(a) __io(a)
+#define __mem_pci(a)            (a)
 
 #endif
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index 9f1a58cbf407..9b0c8012e713 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -58,18 +58,6 @@
 #endif
 
 /*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-# define PFN_TO_MAPBASE(pfn)    NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
  * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
  * and returns the index corresponding to the appropriate page in the
  * node's mem_map.
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index eaf6d43939e9..e17f9881faf0 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -27,7 +27,6 @@
 #define __virt_to_bus(x)         __virt_to_phys(x)
 #define __bus_to_virt(x)         __phys_to_virt(x)
 
-#ifdef CONFIG_DISCONTIGMEM
 /*
  * The nodes are matched with the physical SDRAM banks as follows:
  *
@@ -35,38 +34,9 @@
  *      node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
  *      node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
  *      node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
+ *
+ * This needs a node mem size of 26 bits.
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
-
-#endif
+#define NODE_MEM_SIZE_BITS      26
 
 #endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index cff752f35230..083e03c5639f 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
 #define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
 #define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
 #define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_ENRINTR    (1 << 9)        /* The end of Receive */
+#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
 #endif
 #define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
 #define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
@@ -803,12 +803,11 @@
 #define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
 #define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
-#define UDCISR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
-#define UDCISR1_IERU    (1 << 29)       /* IntEn - Resume */
-#define UDCISR1_IESU    (1 << 28)       /* IntEn - Suspend */
-#define UDCISR1_IERS    (1 << 27)       /* IntEn - Reset */
-
+#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
+#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
+#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
+#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
+#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
 
 #define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
 #define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index 915590c391c8..acc7ec7a84a1 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -27,16 +27,13 @@
 #define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
 #define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
 #define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP_TIMEOUT_SCALE (2712)
 #elif defined(CONFIG_PXA27x)
 #define CLOCK_SPEED_HZ 13000000
 #define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
 #define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
 #define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP_TIMEOUT_SCALE (769)
 #endif
 
-#define SSP_TIMEOUT(x) ((x*10000)/SSP_TIMEOUT_SCALE)
 #define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
 #define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
 #define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
@@ -63,7 +60,7 @@ struct pxa2xx_spi_chip {
         u8 tx_threshold;
         u8 rx_threshold;
         u8 dma_burst_size;
-        u32 timeout_microsecs;
+        u32 timeout;
         u8 enable_loopback;
         void (*cs_control)(u32 command);
 };
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
index 90894214cace..93a58e7862b0 100644
--- a/include/asm-arm/arch-s3c2410/fb.h
+++ b/include/asm-arm/arch-s3c2410/fb.h
@@ -31,6 +31,9 @@ struct s3c2410fb_hw {
 struct s3c2410fb_mach_info {
         unsigned char   fixed_syncs;    /* do not update sync/border */
 
+        /* LCD types */
+        int             type;
+
         /* Screen size */
         int             width;
         int             height;
diff --git a/include/asm-arm/arch-s3c2410/h1940.h b/include/asm-arm/arch-s3c2410/h1940.h
new file mode 100644
index 000000000000..6135592e60f2
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/h1940.h
@@ -0,0 +1,21 @@
+/* linux/include/asm-arm/arch-s3c2410/h1940.h
+ *
+ * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
+ *
+ * H1940 definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_H1940_H
+#define __ASM_ARCH_H1940_H
+
+#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
+#define H1940_SUSPEND_RESUMEAT          (0x30081000)
+#define H1940_SUSPEND_CHECK             (0x30080000)
+
+extern void h1940_pm_return(void);
+
+#endif /* __ASM_ARCH_H1940_H */
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 718246d85952..4f72a853a5cf 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -71,7 +71,7 @@ arch_reset(char mode)
 
         /* set the watchdog to go and reset... */
         __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
-                     S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
 
         /* wait for reset to assert... */
         mdelay(5000);
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
deleted file mode 100644
index 3f37ca07806d..000000000000
--- a/include/asm-arm/arch-sa1100/jornada720.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/jornada720.h
- *
- * Created 2000/11/29 by John Ankcorn <jca@lcs.mit.edu>
- *
- * This file contains the hardware specific definitions for HP Jornada 720
- *
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "include <asm/hardware.h> instead"
-#endif
-
-#define SA1111_BASE             (0x40000000)
-
-#define GPIO_JORNADA720_KEYBOARD        GPIO_GPIO(0)
-#define GPIO_JORNADA720_MOUSE           GPIO_GPIO(9)
-
-#define GPIO_JORNADA720_KEYBOARD_IRQ    IRQ_GPIO0
-#define GPIO_JORNADA720_MOUSE_IRQ               IRQ_GPIO9
-
-/* MCU COMMANDS */
-#define MCU_GetBatteryData  0xc0
-#define MCU_GetScanKeyCode  0x90
-#define MCU_GetTouchSamples 0xa0
-#define MCU_GetContrast     0xD0
-#define MCU_SetContrast     0xD1
-#define MCU_GetBrightness   0xD2
-#define MCU_SetBrightness   0xD3
-#define MCU_ContrastOff     0xD8
-#define MCU_BrightnessOff   0xD9
-#define MCU_PWMOFF          0xDF
-#define MCU_TxDummy         0x11
-#define MCU_ErrorCode       0x00
-
-#ifndef __ASSEMBLY__
-
-void jornada720_mcu_init(void);
-void jornada_contrast(int arg_contrast);
-void jornada720_battery(void);
-int jornada720_getkey(unsigned char *data, int size);
-#endif
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 1ff172dc8e33..0e907fc6d42a 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -39,7 +39,6 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
 #define __virt_to_bus(x)         __virt_to_phys(x)
 #define __bus_to_virt(x)         __phys_to_virt(x)
 
-#ifdef CONFIG_DISCONTIGMEM
 /*
  * Because of the wide memory address space between physical RAM banks on the 
  * SA1100, it's much convenient to use Linux's NUMA support to implement our 
@@ -57,38 +56,7 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
  *      node 2:  0xd0000000 - 0xd7ffffff
  *      node 3:  0xd8000000 - 0xdfffffff
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT)
-
-#endif
+#define NODE_MEM_SIZE_BITS      27
 
 /*
  * Cache flushing area - SA1100 zero bank
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
index 0e36fd5d87df..7b62351f097d 100644
--- a/include/asm-arm/bug.h
+++ b/include/asm-arm/bug.h
@@ -4,10 +4,10 @@
 
 #ifdef CONFIG_BUG
 #ifdef CONFIG_DEBUG_BUGVERBOSE
-extern void __bug(const char *file, int line, void *data) __attribute__((noreturn));
+extern void __bug(const char *file, int line) __attribute__((noreturn));
 
 /* give file/line information */
-#define BUG()           __bug(__FILE__, __LINE__, NULL)
+#define BUG()           __bug(__FILE__, __LINE__)
 
 #else
 
diff --git a/include/asm-arm/cnt32_to_63.h b/include/asm-arm/cnt32_to_63.h
new file mode 100644
index 000000000000..480c873fa746
--- /dev/null
+++ b/include/asm-arm/cnt32_to_63.h
@@ -0,0 +1,78 @@
+/*
+ *  include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    December 3, 2006
+ *  Copyright:  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __INCLUDE_CNT32_TO_63_H__
+#define __INCLUDE_CNT32_TO_63_H__
+
+#include <linux/compiler.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+
+/*
+ * Prototype: u64 cnt32_to_63(u32 cnt)
+ * Many hardware clock counters are only 32 bits wide and therefore have
+ * a relatively short period making wrap-arounds rather frequent.  This
+ * is a problem when implementing sched_clock() for example, where a 64-bit
+ * non-wrapping monotonic value is expected to be returned.
+ *
+ * To overcome that limitation, let's extend a 32-bit counter to 63 bits
+ * in a completely lock free fashion. Bits 0 to 31 of the clock are provided
+ * by the hardware while bits 32 to 62 are stored in memory.  The top bit in
+ * memory is used to synchronize with the hardware clock half-period.  When
+ * the top bit of both counters (hardware and in memory) differ then the
+ * memory is updated with a new value, incrementing it when the hardware
+ * counter wraps around.
+ *
+ * Because a word store in memory is atomic then the incremented value will
+ * always be in synch with the top bit indicating to any potential concurrent
+ * reader if the value in memory is up to date or not with regards to the
+ * needed increment.  And any race in updating the value in memory is harmless
+ * as the same value would simply be stored more than once.
+ *
+ * The only restriction for the algorithm to work properly is that this
+ * code must be executed at least once per each half period of the 32-bit
+ * counter to properly update the state bit in memory. This is usually not a
+ * problem in practice, but if it is then a kernel timer could be scheduled
+ * to manage for this code to be executed often enough.
+ *
+ * Note that the top bit (bit 63) in the returned value should be considered
+ * as garbage.  It is not cleared here because callers are likely to use a
+ * multiplier on the returned value which can get rid of the top bit
+ * implicitly by making the multiplier even, therefore saving on a runtime
+ * clear-bit instruction. Otherwise caller must remember to clear the top
+ * bit explicitly.
+ */
+
+/* this is used only to give gcc a clue about good code generation */
+typedef union {
+        struct {
+#if defined(__LITTLE_ENDIAN)
+                u32 lo, hi;
+#elif defined(__BIG_ENDIAN)
+                u32 hi, lo;
+#endif
+        };
+        u64 val;
+} cnt32_to_63_t;
+
+#define cnt32_to_63(cnt_lo) \
+({ \
+        static volatile u32 __m_cnt_hi = 0; \
+        cnt32_to_63_t __x; \
+        __x.hi = __m_cnt_hi; \
+        __x.lo = (cnt_lo); \
+        if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
+                __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
+        __x.val; \
+})
+
+#endif
diff --git a/include/asm-arm/div64.h b/include/asm-arm/div64.h
index 3682616804ca..37e0a96e8789 100644
--- a/include/asm-arm/div64.h
+++ b/include/asm-arm/div64.h
@@ -27,7 +27,7 @@
 #define __xh "r1"
 #endif
 
-#define do_div(n,base)                                          \
+#define __do_div_asm(n, base)                                   \
 ({                                                              \
         register unsigned int __base      asm("r4") = base;     \
         register unsigned long long __n   asm("r0") = n;        \
@@ -45,4 +45,182 @@
         __rem;                                                  \
 })
 
+#if __GNUC__ < 4
+
+/*
+ * gcc versions earlier than 4.0 are simply too problematic for the
+ * optimized implementation below. First there is gcc PR 15089 that
+ * tend to trig on more complex constructs, spurious .global __udivsi3
+ * are inserted even if none of those symbols are referenced in the
+ * generated code, and those gcc versions are not able to do constant
+ * propagation on long long values anyway.
+ */
+#define do_div(n, base) __do_div_asm(n, base)
+
+#elif __GNUC__ >= 4
+
+#include <asm/bug.h>
+
+/*
+ * If the divisor happens to be constant, we determine the appropriate
+ * inverse at compile time to turn the division into a few inline
+ * multiplications instead which is much faster. And yet only if compiling
+ * for ARMv4 or higher (we need umull/umlal) and if the gcc version is
+ * sufficiently recent to perform proper long long constant propagation.
+ * (It is unfortunate that gcc doesn't perform all this internally.)
+ */
+#define do_div(n, base)                                                 \
+({                                                                      \
+        unsigned int __r, __b = (base);                                 \
+        if (!__builtin_constant_p(__b) || __b == 0 ||                   \
+            (__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) {       \
+                /* non-constant divisor (or zero): slow path */         \
+                __r = __do_div_asm(n, __b);                             \
+        } else if ((__b & (__b - 1)) == 0) {                            \
+                /* Trivial: __b is constant and a power of 2 */         \
+                /* gcc does the right thing with this code.  */         \
+                __r = n;                                                \
+                __r &= (__b - 1);                                       \
+                n /= __b;                                               \
+        } else {                                                        \
+                /* Multiply by inverse of __b: n/b = n*(p/b)/p       */ \
+                /* We rely on the fact that most of this code gets   */ \
+                /* optimized away at compile time due to constant    */ \
+                /* propagation and only a couple inline assembly     */ \
+                /* instructions should remain. Better avoid any      */ \
+                /* code construct that might prevent that.           */ \
+                unsigned long long __res, __x, __t, __m, __n = n;       \
+                unsigned int __c, __p, __z = 0;                         \
+                /* preserve low part of n for reminder computation */   \
+                __r = __n;                                              \
+                /* determine number of bits to represent __b */         \
+                __p = 1 << __div64_fls(__b);                            \
+                /* compute __m = ((__p << 64) + __b - 1) / __b */       \
+                __m = (~0ULL / __b) * __p;                              \
+                __m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b;     \
+                /* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \
+                __x = ~0ULL / __b * __b - 1;                            \
+                __res = (__m & 0xffffffff) * (__x & 0xffffffff);        \
+                __res >>= 32;                                           \
+                __res += (__m & 0xffffffff) * (__x >> 32);              \
+                __t = __res;                                            \
+                __res += (__x & 0xffffffff) * (__m >> 32);              \
+                __t = (__res < __t) ? (1ULL << 32) : 0;                 \
+                __res = (__res >> 32) + __t;                            \
+                __res += (__m >> 32) * (__x >> 32);                     \
+                __res /= __p;                                           \
+                /* Now sanitize and optimize what we've got. */         \
+                if (~0ULL % (__b / (__b & -__b)) == 0) {                \
+                        /* those cases can be simplified with: */       \
+                        __n /= (__b & -__b);                            \
+                        __m = ~0ULL / (__b / (__b & -__b));             \
+                        __p = 1;                                        \
+                        __c = 1;                                        \
+                } else if (__res != __x / __b) {                        \
+                        /* We can't get away without a correction    */ \
+                        /* to compensate for bit truncation errors.  */ \
+                        /* To avoid it we'd need an additional bit   */ \
+                        /* to represent __m which would overflow it. */ \
+                        /* Instead we do m=p/b and n/b=(n*m+m)/p.    */ \
+                        __c = 1;                                        \
+                        /* Compute __m = (__p << 64) / __b */           \
+                        __m = (~0ULL / __b) * __p;                      \
+                        __m += ((~0ULL % __b + 1) * __p) / __b;         \
+                } else {                                                \
+                        /* Reduce __m/__p, and try to clear bit 31   */ \
+                        /* of __m when possible otherwise that'll    */ \
+                        /* need extra overflow handling later.       */ \
+                        unsigned int __bits = -(__m & -__m);            \
+                        __bits |= __m >> 32;                            \
+                        __bits = (~__bits) << 1;                        \
+                        /* If __bits == 0 then setting bit 31 is     */ \
+                        /* unavoidable.  Simply apply the maximum    */ \
+                        /* possible reduction in that case.          */ \
+                        /* Otherwise the MSB of __bits indicates the */ \
+                        /* best reduction we should apply.           */ \
+                        if (!__bits) {                                  \
+                                __p /= (__m & -__m);                    \
+                                __m /= (__m & -__m);                    \
+                        } else {                                        \
+                                __p >>= __div64_fls(__bits);            \
+                                __m >>= __div64_fls(__bits);            \
+                        }                                               \
+                        /* No correction needed. */                     \
+                        __c = 0;                                        \
+                }                                                       \
+                /* Now we have a combination of 2 conditions:        */ \
+                /* 1) whether or not we need a correction (__c), and */ \
+                /* 2) whether or not there might be an overflow in   */ \
+                /*    the cross product (__m & ((1<<63) | (1<<31)))  */ \
+                /* Select the best insn combination to perform the   */ \
+                /* actual __m * __n / (__p << 64) operation.         */ \
+                if (!__c) {                                             \
+                        asm (   "umull  %Q0, %R0, %1, %Q2\n\t"          \
+                                "mov    %Q0, #0"                        \
+                                : "=&r" (__res)                         \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) {    \
+                        __res = __m;                                    \
+                        asm (   "umlal  %Q0, %R0, %Q1, %Q2\n\t"         \
+                                "mov    %Q0, #0"                        \
+                                : "+r" (__res)                          \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else {                                                \
+                        asm (   "umull  %Q0, %R0, %Q1, %Q2\n\t"         \
+                                "cmn    %Q0, %Q1\n\t"                   \
+                                "adcs   %R0, %R0, %R1\n\t"              \
+                                "adc    %Q0, %3, #0"                    \
+                                : "=&r" (__res)                         \
+                                : "r" (__m), "r" (__n), "r" (__z)       \
+                                : "cc" );                               \
+                }                                                       \
+                if (!(__m & ((1ULL << 63) | (1ULL << 31)))) {           \
+                        asm (   "umlal  %R0, %Q0, %R1, %Q2\n\t"         \
+                                "umlal  %R0, %Q0, %Q1, %R2\n\t"         \
+                                "mov    %R0, #0\n\t"                    \
+                                "umlal  %Q0, %R0, %R1, %R2"             \
+                                : "+r" (__res)                          \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else {                                                \
+                        asm (   "umlal  %R0, %Q0, %R2, %Q3\n\t"         \
+                                "umlal  %R0, %1, %Q2, %R3\n\t"          \
+                                "mov    %R0, #0\n\t"                    \
+                                "adds   %Q0, %1, %Q0\n\t"               \
+                                "adc    %R0, %R0, #0\n\t"               \
+                                "umlal  %Q0, %R0, %R2, %R3"             \
+                                : "+r" (__res), "+r" (__z)              \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                }                                                       \
+                __res /= __p;                                           \
+                /* The reminder can be computed with 32-bit regs     */ \
+                /* only, and gcc is good at that.                    */ \
+                {                                                       \
+                        unsigned int __res0 = __res;                    \
+                        unsigned int __b0 = __b;                        \
+                        __r -= __res0 * __b0;                           \
+                }                                                       \
+                /* BUG_ON(__r >= __b || __res * __b + __r != n); */     \
+                n = __res;                                              \
+        }                                                               \
+        __r;                                                            \
+})
+
+/* our own fls implementation to make sure constant propagation is fine */
+#define __div64_fls(bits)                                               \
+({                                                                      \
+        unsigned int __left = (bits), __nr = 0;                         \
+        if (__left & 0xffff0000) __nr += 16, __left >>= 16;             \
+        if (__left & 0x0000ff00) __nr +=  8, __left >>=  8;             \
+        if (__left & 0x000000f0) __nr +=  4, __left >>=  4;             \
+        if (__left & 0x0000000c) __nr +=  2, __left >>=  2;             \
+        if (__left & 0x00000002) __nr +=  1;                            \
+        __nr;                                                           \
+})
+
+#endif
+
 #endif
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index 17f0c656d272..642382d2c9f0 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,17 +1,22 @@
 #ifndef __ASMARM_ELF_H
 #define __ASMARM_ELF_H
 
-
+#ifndef __ASSEMBLY__
 /*
  * ELF register definitions..
  */
-
 #include <asm/ptrace.h>
 #include <asm/user.h>
 
 typedef unsigned long elf_greg_t;
 typedef unsigned long elf_freg_t[3];
 
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_fp elf_fpregset_t;
+#endif
+
 #define EM_ARM  40
 #define EF_ARM_APCS26 0x08
 #define EF_ARM_SOFT_FLOAT 0x200
@@ -23,11 +28,6 @@ typedef unsigned long elf_freg_t[3];
 #define R_ARM_CALL      28
 #define R_ARM_JUMP24    29
 
-#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_fp elf_fpregset_t;
-
 /*
  * These are used to set parameters in the core dumps.
  */
@@ -39,97 +39,99 @@ typedef struct user_fp elf_fpregset_t;
 #endif
 #define ELF_ARCH        EM_ARM
 
-#ifdef __KERNEL__
-#include <asm/procinfo.h>
-
 /*
- * This is used to ensure we don't load something for the wrong architecture.
+ * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
  */
-#define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && (ELF_PROC_OK((x))) )
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
-
-/* When the program starts, a1 contains a pointer to a function to be 
-   registered with atexit, as per the SVR4 ABI.  A value of 0 means we 
-   have no such handler.  */
-#define ELF_PLAT_INIT(_r, load_addr)    (_r)->ARM_r0 = 0
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports. */
+#define HWCAP_SWP       1
+#define HWCAP_HALF      2
+#define HWCAP_THUMB     4
+#define HWCAP_26BIT     8       /* Play it safe */
+#define HWCAP_FAST_MULT 16
+#define HWCAP_FPA       32
+#define HWCAP_VFP       64
+#define HWCAP_EDSP      128
+#define HWCAP_JAVA      256
+#define HWCAP_IWMMXT    512
 
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+/*
+ * This yields a mask that user programs can use to figure out what
+ * instruction set this cpu supports.
+ */
 #define ELF_HWCAP       (elf_hwcap)
+extern unsigned int elf_hwcap;
 
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo. */
-
-/* For now we just provide a fairly general string that describes the
-   processor family.  This could be made more specific later if someone
-   implemented optimisations that require it.  26-bit CPUs give you
-   "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
-   supported).  32-bit CPUs give you "v3[lb]" for anything based on an
-   ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
-   core.  */
-
+/*
+ * This yields a string that ld.so will use to load implementation
+ * specific libraries for optimization.  This is more specific in
+ * intent than poking at uname or /proc/cpuinfo.
+ *
+ * For now we just provide a fairly general string that describes the
+ * processor family.  This could be made more specific later if someone
+ * implemented optimisations that require it.  26-bit CPUs give you
+ * "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
+ * supported).  32-bit CPUs give you "v3[lb]" for anything based on an
+ * ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
+ * core.
+ */
 #define ELF_PLATFORM_SIZE 8
-extern char elf_platform[];
 #define ELF_PLATFORM    (elf_platform)
 
+extern char elf_platform[];
+#endif
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x))
+
 /*
  * 32-bit code is always OK.  Some cpus can do 26-bit, some can't.
  */
 #define ELF_PROC_OK(x)  (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
 
 #define ELF_THUMB_OK(x) \
-        (( (elf_hwcap & HWCAP_THUMB) && ((x)->e_entry & 1) == 1) || \
+        ((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \
          ((x)->e_entry & 3) == 0)
 
 #define ELF_26BIT_OK(x) \
-        (( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \
+        ((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \
           ((x)->e_flags & EF_ARM_APCS26) == 0)
 
-#ifndef CONFIG_IWMMXT
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       4096
 
-/* Old NetWinder binaries were compiled in such a way that the iBCS
-   heuristic always trips on them.  Until these binaries become uncommon
-   enough not to care, don't trust the `ibcs' flag here.  In any case
-   there is no other ELF system currently supported by iBCS.
-   @@ Could print a warning message to encourage users to upgrade.  */
-#define SET_PERSONALITY(ex,ibcs2) \
-        set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT))
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
 
-#else
+#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
+
+/* When the program starts, a1 contains a pointer to a function to be 
+   registered with atexit, as per the SVR4 ABI.  A value of 0 means we 
+   have no such handler.  */
+#define ELF_PLAT_INIT(_r, load_addr)    (_r)->ARM_r0 = 0
 
 /*
- * All iWMMXt capable CPUs don't support 26-bit mode.  Yet they can run
- * legacy binaries which used to contain FPA11 floating point instructions
- * that have always been emulated by the kernel.  PFA11 and iWMMXt overlap
- * on coprocessor 1 space though.  We therefore must decide if given task
- * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked
- * at all times for the prefetch exception handler to catch FPA11 opcodes
- * and emulate them.  The best indication to discriminate those two cases
- * is the SOFT_FLOAT flag in the ELF header.
+ * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
+ * and CP1, we only enable access to the iWMMXt coprocessor if the
+ * binary is EABI or softfloat (and thus, guaranteed not to use
+ * FPA instructions.)
  */
-
-#define SET_PERSONALITY(ex,ibcs2) \
-do { \
-        set_personality(PER_LINUX_32BIT); \
-        if (((ex).e_flags & EF_ARM_EABI_MASK) || \
-            ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \
-                set_thread_flag(TIF_USING_IWMMXT); \
-        else \
-                clear_thread_flag(TIF_USING_IWMMXT); \
-} while (0)
-
-#endif
+#define SET_PERSONALITY(ex, ibcs2)                                      \
+        do {                                                            \
+                if ((ex).e_flags & EF_ARM_APCS26) {                     \
+                        set_personality(PER_LINUX);                     \
+                } else {                                                \
+                        set_personality(PER_LINUX_32BIT);               \
+                        if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \
+                                set_thread_flag(TIF_USING_IWMMXT);      \
+                        else                                            \
+                                clear_thread_flag(TIF_USING_IWMMXT);    \
+                }                                                       \
+        } while (0)
 
 #endif
 
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index ae999fd5dc67..288f76b166d0 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -75,14 +75,6 @@ extern void __readwrite_bug(const char *fn);
  */
 #include <asm/arch/io.h>
 
-#ifdef __io_pci
-#warning machine class uses buggy __io_pci
-#endif
-#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
-    defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
-#warning machine class uses old __arch_putw or __arch_getw
-#endif
-
 /*
  *  IO port access primitives
  *  -------------------------
diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h
index 0e017ecf2096..eb0bfba6570d 100644
--- a/include/asm-arm/mach/irq.h
+++ b/include/asm-arm/mach/irq.h
@@ -22,12 +22,6 @@ extern void init_FIQ(void);
 extern int show_fiq_list(struct seq_file *, void *);
 
 /*
- * Function wrappers
- */
-#define set_irq_chipdata(irq, d)        set_irq_chip_data(irq, d)
-#define get_irq_chipdata(irq)           get_irq_chip_data(irq)
-
-/*
  * Obsolete inline function for calling irq descriptor handlers.
  */
 static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
@@ -44,12 +38,6 @@ void set_irq_flags(unsigned int irq, unsigned int flags);
 /*
  * This is for easy migration, but should be changed in the source
  */
-#define do_level_IRQ    handle_level_irq
-#define do_edge_IRQ     handle_edge_irq
-#define do_simple_IRQ   handle_simple_irq
-#define irqdesc         irq_desc
-#define irqchip         irq_chip
-
 #define do_bad_IRQ(irq,desc)                            \
 do {                                                    \
         spin_lock(&desc->lock);                         \
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 91d536c215d7..d9bfb39adabf 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -215,6 +215,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  *  virt_addr_valid(k)  indicates whether a virtual address is valid
  */
 #ifndef CONFIG_DISCONTIGMEM
+
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
 #define pfn_valid(pfn)          ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
 
@@ -230,6 +231,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  * around in memory.
  */
 #include <linux/numa.h>
+
 #define arch_pfn_to_nid(pfn)    PFN_TO_NID(pfn)
 #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
 
@@ -256,6 +258,43 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  */
 #define PHYS_TO_NID(addr)       PFN_TO_NID((addr) >> PAGE_SHIFT)
 
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+#ifdef NODE_MEM_SIZE_BITS
+#define NODE_MEM_SIZE_MASK      ((1 << NODE_MEM_SIZE_BITS) - 1)
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn) \
+        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+        (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
+
+#endif /* NODE_MEM_SIZE_BITS */
+
 #endif /* !CONFIG_DISCONTIGMEM */
 
 /*
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index c1b264dff287..7b1c9acdf79a 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -44,7 +44,6 @@
 #define PAGE_READONLY   __pgprot(0)
 #define PAGE_KERNEL     __pgprot(0)
 
-//extern void paging_init(struct meminfo *, struct machine_desc *);
 #define swapper_pg_dir ((pgd_t *) 0)
 
 #define __swp_type(x)           (0)
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index ed8cb5963e99..88cd5c784ef0 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -169,8 +169,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define L_PTE_WRITE             (1 << 5)
 #define L_PTE_EXEC              (1 << 6)
 #define L_PTE_DIRTY             (1 << 7)
-#define L_PTE_COHERENT          (1 << 9)        /* I/O coherent (xsc3) */
-#define L_PTE_SHARED            (1 << 10)       /* shared between CPUs (v6) */
+#define L_PTE_SHARED            (1 << 10)       /* shared(v6), coherent(xsc3) */
 #define L_PTE_ASID              (1 << 11)       /* non-global (use ASID, v6) */
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
index 04f4d34c6317..b442e8e2a809 100644
--- a/include/asm-arm/processor.h
+++ b/include/asm-arm/processor.h
@@ -20,7 +20,6 @@
 #ifdef __KERNEL__
 
 #include <asm/ptrace.h>
-#include <asm/procinfo.h>
 #include <asm/types.h>
 
 union debug_insn {
diff --git a/include/asm-arm/procinfo.h b/include/asm-arm/procinfo.h
index 91a31adfa8a8..4d3c685075e0 100644
--- a/include/asm-arm/procinfo.h
+++ b/include/asm-arm/procinfo.h
@@ -10,7 +10,7 @@
 #ifndef __ASM_PROCINFO_H
 #define __ASM_PROCINFO_H
 
-#ifndef __ASSEMBLY__
+#ifdef __KERNEL__
 
 struct cpu_tlb_fns;
 struct cpu_user_fns;
@@ -42,19 +42,8 @@ struct proc_info_list {
         struct cpu_cache_fns    *cache;
 };
 
-extern unsigned int elf_hwcap;
-
-#endif  /* __ASSEMBLY__ */
-
-#define HWCAP_SWP       1
-#define HWCAP_HALF      2
-#define HWCAP_THUMB     4
-#define HWCAP_26BIT     8       /* Play it safe */
-#define HWCAP_FAST_MULT 16
-#define HWCAP_FPA       32
-#define HWCAP_VFP       64
-#define HWCAP_EDSP      128
-#define HWCAP_JAVA      256
-#define HWCAP_IWMMXT    512
-
+#else   /* __KERNEL__ */
+#include <asm/elf.h>
+#warning "Please include asm/elf.h instead"
+#endif  /* __KERNEL__ */
 #endif
diff --git a/include/asm-arm/termbits.h b/include/asm-arm/termbits.h
index bbc6e1d24d3f..a3f4fe1742d0 100644
--- a/include/asm-arm/termbits.h
+++ b/include/asm-arm/termbits.h
@@ -15,6 +15,18 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index f28b236139ed..d9b8bddc8732 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -94,8 +94,18 @@ static inline struct thread_info *current_thread_info(void)
         return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
 }
 
-extern struct thread_info *alloc_thread_info(struct task_struct *task);
-extern void free_thread_info(struct thread_info *);
+/* thread information allocation */
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(tsk) \
+        ((struct thread_info *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, \
+                THREAD_SIZE_ORDER))
+#else
+#define alloc_thread_info(tsk) \
+        ((struct thread_info *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER))
+#endif
+
+#define free_thread_info(info) \
+        free_pages((unsigned long)info, THREAD_SIZE_ORDER);
 
 #define thread_saved_pc(tsk)    \
         ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc)))
diff --git a/include/asm-arm26/termbits.h b/include/asm-arm26/termbits.h
index bbc6e1d24d3f..a3f4fe1742d0 100644
--- a/include/asm-arm26/termbits.h
+++ b/include/asm-arm26/termbits.h
@@ -15,6 +15,18 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h b/include/asm-avr32/arch-at32ap/at91_pdc.h
index ce1150d4438d..79d6e02fa45e 100644
--- a/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h
+++ b/include/asm-avr32/arch-at32ap/at91_pdc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+ * include/asm-arm/arch-at91rm9200/at91_pdc.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_PDC_H
-#define AT91RM9200_PDC_H
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
 
 #define AT91_PDC_RPR            0x100   /* Receive Pointer Register */
 #define AT91_PDC_RCR            0x104   /* Receive Counter Register */
diff --git a/include/asm-avr32/termbits.h b/include/asm-avr32/termbits.h
index 9dc6eacafa33..c215fafdae4d 100644
--- a/include/asm-avr32/termbits.h
+++ b/include/asm-avr32/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h
index be0836d2f282..8d8cec225fe1 100644
--- a/include/asm-cris/termbits.h
+++ b/include/asm-cris/termbits.h
@@ -19,6 +19,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-frv/bitops.h b/include/asm-frv/bitops.h
index 1f70d47148bd..f8560edf59ff 100644
--- a/include/asm-frv/bitops.h
+++ b/include/asm-frv/bitops.h
@@ -256,6 +256,50 @@ int __ffs(unsigned long x)
         return 31 - bit;
 }
 
+/*
+ * special slimline version of fls() for calculating ilog2_u32()
+ * - note: no protection against n == 0
+ */
+#define ARCH_HAS_ILOG2_U32
+static inline __attribute__((const))
+int __ilog2_u32(u32 n)
+{
+        int bit;
+        asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
+        return 31 - bit;
+}
+
+/*
+ * special slimline version of fls64() for calculating ilog2_u64()
+ * - note: no protection against n == 0
+ */
+#define ARCH_HAS_ILOG2_U64
+static inline __attribute__((const))
+int __ilog2_u64(u64 n)
+{
+        union {
+                u64 ll;
+                struct { u32 h, l; };
+        } _;
+        int bit, x, y;
+
+        _.ll = n;
+
+        asm("   subcc           %3,gr0,gr0,icc0         \n"
+            "   ckeq            icc0,cc4                \n"
+            "   cscan.p         %3,gr0,%0       ,cc4,0  \n"
+            "   setlos          #63,%1                  \n"
+            "   cscan.p         %4,gr0,%0       ,cc4,1  \n"
+            "   setlos          #31,%2                  \n"
+            "   csub.p          %1,%0,%0        ,cc4,0  \n"
+            "   csub            %2,%0,%0        ,cc4,1  \n"
+            : "=&r"(bit), "=r"(x), "=r"(y)
+            : "0r"(_.h), "r"(_.l)
+            : "icc0", "cc4"
+            );
+        return bit;
+}
+
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/hweight.h>
 
diff --git a/include/asm-frv/termbits.h b/include/asm-frv/termbits.h
index 74f20d6e292f..2d6d389cff49 100644
--- a/include/asm-frv/termbits.h
+++ b/include/asm-frv/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index c92ae0f166ff..a06eecd48292 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -4,6 +4,22 @@
 #include <linux/compiler.h>
 
 #ifdef CONFIG_BUG
+
+#ifdef CONFIG_GENERIC_BUG
+#ifndef __ASSEMBLY__
+struct bug_entry {
+        unsigned long   bug_addr;
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+        const char      *file;
+        unsigned short  line;
+#endif
+        unsigned short  flags;
+};
+#endif          /* __ASSEMBLY__ */
+
+#define BUGFLAG_WARNING (1<<0)
+#endif  /* CONFIG_GENERIC_BUG */
+
 #ifndef HAVE_ARCH_BUG
 #define BUG() do { \
         printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
@@ -19,7 +35,7 @@
 #define WARN_ON(condition) ({                                           \
         typeof(condition) __ret_warn_on = (condition);                  \
         if (unlikely(__ret_warn_on)) {                                  \
-                printk("BUG: warning at %s:%d/%s()\n", __FILE__,        \
+                printk("WARNING at %s:%d %s()\n", __FILE__,     \
                         __LINE__, __FUNCTION__);                        \
                 dump_stack();                                           \
         }                                                               \
diff --git a/include/asm-generic/page.h b/include/asm-generic/page.h
index a96b5d986b6e..b55052ce2330 100644
--- a/include/asm-generic/page.h
+++ b/include/asm-generic/page.h
@@ -4,21 +4,51 @@
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 
-#include <linux/compiler.h>
+#include <linux/log2.h>
 
-/* Pure 2^n version of get_order */
-static __inline__ __attribute_const__ int get_order(unsigned long size)
+/*
+ * non-const pure 2^n version of get_order
+ * - the arch may override these in asm/bitops.h if they can be implemented
+ *   more efficiently than using the arch log2 routines
+ * - we use the non-const log2() instead if the arch has defined one suitable
+ */
+#ifndef ARCH_HAS_GET_ORDER
+static inline __attribute__((const))
+int __get_order(unsigned long size, int page_shift)
 {
+#if BITS_PER_LONG == 32 && defined(ARCH_HAS_ILOG2_U32)
+        int order = __ilog2_u32(size) - page_shift;
+        return order >= 0 ? order : 0;
+#elif BITS_PER_LONG == 64 && defined(ARCH_HAS_ILOG2_U64)
+        int order = __ilog2_u64(size) - page_shift;
+        return order >= 0 ? order : 0;
+#else
         int order;
 
-        size = (size - 1) >> (PAGE_SHIFT - 1);
+        size = (size - 1) >> (page_shift - 1);
         order = -1;
         do {
                 size >>= 1;
                 order++;
         } while (size);
         return order;
+#endif
 }
+#endif
+
+/**
+ * get_order - calculate log2(pages) to hold a block of the specified size
+ * @n - size
+ *
+ * calculate allocation order based on the current page size
+ * - this can be used to initialise global variables from constant data
+ */
+#define get_order(n)                                                    \
+(                                                                       \
+        __builtin_constant_p(n) ?                                       \
+        ((n < (1UL << PAGE_SHIFT)) ? 0 : ilog2(n) - PAGE_SHIFT) :       \
+        __get_order(n, PAGE_SHIFT)                                      \
+ )
 
 #endif  /* __ASSEMBLY__ */
 #endif  /* __KERNEL__ */
diff --git a/include/asm-generic/termios.h b/include/asm-generic/termios.h
index 1e58ca39592c..3769e6bd63b1 100644
--- a/include/asm-generic/termios.h
+++ b/include/asm-generic/termios.h
@@ -11,7 +11,7 @@
 /*
  * Translate a "termio" structure into a "termios". Ugh.
  */
-static inline int user_termio_to_kernel_termios(struct termios *termios,
+static inline int user_termio_to_kernel_termios(struct ktermios *termios,
                                                 struct termio __user *termio)
 {
         unsigned short tmp;
@@ -48,7 +48,7 @@ static inline int user_termio_to_kernel_termios(struct termios *termios,
  * Translate a "termios" structure into a "termio". Ugh.
  */
 static inline int kernel_termios_to_user_termio(struct termio __user *termio,
-                                                struct termios *termios)
+                                                struct ktermios *termios)
 {
         if (put_user(termios->c_iflag, &termio->c_iflag) < 0 ||
             put_user(termios->c_oflag, &termio->c_oflag) < 0 ||
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 4d4c62d11059..7437ccaada77 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -218,6 +218,14 @@
                 .stab.indexstr 0 : { *(.stab.indexstr) }                \
                 .comment 0 : { *(.comment) }
 
+#define BUG_TABLE                                                       \
+        . = ALIGN(8);                                                   \
+        __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) {             \
+                __start___bug_table = .;                                \
+                *(__bug_table)                                          \
+                __stop___bug_table = .;                                 \
+        }
+
 #define NOTES                                                           \
                 .notes : { *(.note.*) } :note
 
@@ -234,6 +242,7 @@
         *(.initcall4s.init)                                             \
         *(.initcall5.init)                                              \
         *(.initcall5s.init)                                             \
+        *(.initcallrootfs.init)                                         \
         *(.initcall6.init)                                              \
         *(.initcall6s.init)                                             \
         *(.initcall7.init)                                              \
diff --git a/include/asm-h8300/termbits.h b/include/asm-h8300/termbits.h
index fa69ae00eda3..6a1f4d3807b4 100644
--- a/include/asm-h8300/termbits.h
+++ b/include/asm-h8300/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-i386/bug.h b/include/asm-i386/bug.h
index 8062cdbf2587..b0fd78ca2619 100644
--- a/include/asm-i386/bug.h
+++ b/include/asm-i386/bug.h
@@ -4,20 +4,32 @@
 
 /*
  * Tell the user there is some problem.
- * The offending file and line are encoded after the "officially
- * undefined" opcode for parsing in the trap handler.
+ * The offending file and line are encoded encoded in the __bug_table section.
  */
 
 #ifdef CONFIG_BUG
 #define HAVE_ARCH_BUG
+
 #ifdef CONFIG_DEBUG_BUGVERBOSE
-#define BUG()                           \
- __asm__ __volatile__(  "ud2\n"         \
-                        "\t.word %c0\n" \
-                        "\t.long %c1\n" \
-                         : : "i" (__LINE__), "i" (__FILE__))
+#define BUG()                                                           \
+        do {                                                            \
+                asm volatile("1:\tud2\n"                                \
+                             ".pushsection __bug_table,\"a\"\n"         \
+                             "2:\t.long 1b, %c0\n"                      \
+                             "\t.word %c1, 0\n"                         \
+                             "\t.org 2b+%c2\n"                          \
+                             ".popsection"                              \
+                             : : "i" (__FILE__), "i" (__LINE__),        \
+                             "i" (sizeof(struct bug_entry)));           \
+                for(;;) ;                                               \
+        } while(0)
+
 #else
-#define BUG() __asm__ __volatile__("ud2\n")
+#define BUG()                                                           \
+        do {                                                            \
+                asm volatile("ud2");                                    \
+                for(;;) ;                                               \
+        } while(0)
 #endif
 #endif
 
diff --git a/include/asm-i386/ide.h b/include/asm-i386/ide.h
index 73465d2892b9..0fc240c80f49 100644
--- a/include/asm-i386/ide.h
+++ b/include/asm-i386/ide.h
@@ -40,13 +40,14 @@ static __inline__ int ide_default_irq(unsigned long base)
 
 static __inline__ unsigned long ide_default_io_base(int index)
 {
+        struct pci_dev *pdev;
         /*
          *      If PCI is present then it is not safe to poke around
          *      the other legacy IDE ports. Only 0x1f0 and 0x170 are
          *      defined compatibility mode ports for PCI. A user can 
          *      override this using ide= but we must default safe.
          */
-        if (pci_find_device(PCI_ANY_ID, PCI_ANY_ID, NULL) == NULL) {
+        if ((pdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL)) == NULL) {
                 switch(index) {
                         case 2: return 0x1e8;
                         case 3: return 0x168;
@@ -54,6 +55,7 @@ static __inline__ unsigned long ide_default_io_base(int index)
                         case 5: return 0x160;
                 }
         }
+        pci_dev_put(pdev);
         switch (index) {
                 case 0: return 0x1f0;
                 case 1: return 0x170;
diff --git a/include/asm-i386/termbits.h b/include/asm-i386/termbits.h
index 72c10e3190f8..12baf1d6343f 100644
--- a/include/asm-i386/termbits.h
+++ b/include/asm-i386/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-i386/topology.h b/include/asm-i386/topology.h
index 978d09596130..ac58580ad664 100644
--- a/include/asm-i386/topology.h
+++ b/include/asm-i386/topology.h
@@ -89,6 +89,7 @@ static inline int node_to_first_cpu(int node)
         .flags                  = SD_LOAD_BALANCE       \
                                 | SD_BALANCE_EXEC       \
                                 | SD_BALANCE_FORK       \
+                                | SD_SERIALIZE          \
                                 | SD_WAKE_BALANCE,      \
         .last_balance           = jiffies,              \
         .balance_interval       = 1,                    \
diff --git a/include/asm-ia64/checksum.h b/include/asm-ia64/checksum.h
index bd40f4756ce1..2b78582cbd61 100644
--- a/include/asm-ia64/checksum.h
+++ b/include/asm-ia64/checksum.h
@@ -70,4 +70,10 @@ static inline __sum16 csum_fold(__wsum csum)
         return (__force __sum16)~sum;
 }
 
+#define _HAVE_ARCH_IPV6_CSUM    1
+struct in6_addr;
+extern unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
+        struct in6_addr *daddr, __u32 len, unsigned short proto,
+        unsigned int csum);
+
 #endif /* _ASM_IA64_CHECKSUM_H */
diff --git a/include/asm-ia64/kexec.h b/include/asm-ia64/kexec.h
new file mode 100644
index 000000000000..01c36b004747
--- /dev/null
+++ b/include/asm-ia64/kexec.h
@@ -0,0 +1,47 @@
+#ifndef _ASM_IA64_KEXEC_H
+#define _ASM_IA64_KEXEC_H
+
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+
+#define KEXEC_CONTROL_CODE_SIZE (8192 + 8192 + 4096)
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_IA_64
+
+#define MAX_NOTE_BYTES 1024
+
+#define kexec_flush_icache_page(page) do { \
+                unsigned long page_addr = (unsigned long)page_address(page); \
+                flush_icache_range(page_addr, page_addr + PAGE_SIZE); \
+        } while(0)
+
+extern struct kimage *ia64_kimage;
+DECLARE_PER_CPU(u64, ia64_mca_pal_base);
+const extern unsigned int relocate_new_kernel_size;
+extern void relocate_new_kernel(unsigned long, unsigned long,
+                struct ia64_boot_param *, unsigned long);
+static inline void
+crash_setup_regs(struct pt_regs *newregs, struct pt_regs *oldregs)
+{
+}
+extern struct resource efi_memmap_res;
+extern struct resource boot_param_res;
+extern void kdump_smp_send_stop(void);
+extern void kdump_smp_send_init(void);
+extern void kexec_disable_iosapic(void);
+extern void crash_save_this_cpu(void);
+struct rsvd_region;
+extern unsigned long kdump_find_rsvd_region(unsigned long size,
+                struct rsvd_region *rsvd_regions, int n);
+extern void kdump_cpu_freeze(struct unw_frame_info *info, void *arg);
+extern int kdump_status[];
+extern atomic_t kdump_cpu_freezed;
+extern atomic_t kdump_in_progress;
+
+#endif /* _ASM_IA64_KEXEC_H */
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
index 8f784f8e45b0..a3891eb3f217 100644
--- a/include/asm-ia64/machvec.h
+++ b/include/asm-ia64/machvec.h
@@ -37,6 +37,7 @@ typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
                                         u8 size);
 typedef void ia64_mv_migrate_t(struct task_struct * task);
 typedef void ia64_mv_pci_fixup_bus_t (struct pci_bus *);
+typedef void ia64_mv_kernel_launch_event_t(void);
 
 /* DMA-mapping interface: */
 typedef void ia64_mv_dma_init (void);
@@ -218,6 +219,7 @@ struct ia64_machine_vector {
         ia64_mv_setup_msi_irq_t *setup_msi_irq;
         ia64_mv_teardown_msi_irq_t *teardown_msi_irq;
         ia64_mv_pci_fixup_bus_t *pci_fixup_bus;
+        ia64_mv_kernel_launch_event_t *kernel_launch_event;
 } __attribute__((__aligned__(16))); /* align attrib? see above comment */
 
 #define MACHVEC_INIT(name)                      \
@@ -318,6 +320,9 @@ extern ia64_mv_dma_supported		swiotlb_dma_supported;
 #ifndef platform_tlb_migrate_finish
 # define platform_tlb_migrate_finish    machvec_noop_mm
 #endif
+#ifndef platform_kernel_launch_event
+# define platform_kernel_launch_event   machvec_noop
+#endif
 #ifndef platform_dma_init
 # define platform_dma_init              swiotlb_init
 #endif
diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h
index 83325f6db03e..eaa2fce0fecd 100644
--- a/include/asm-ia64/machvec_sn2.h
+++ b/include/asm-ia64/machvec_sn2.h
@@ -67,6 +67,7 @@ extern ia64_mv_dma_sync_sg_for_device	sn_dma_sync_sg_for_device;
 extern ia64_mv_dma_mapping_error        sn_dma_mapping_error;
 extern ia64_mv_dma_supported            sn_dma_supported;
 extern ia64_mv_migrate_t                sn_migrate;
+extern ia64_mv_kernel_launch_event_t    sn_kernel_launch_event;
 extern ia64_mv_setup_msi_irq_t          sn_setup_msi_irq;
 extern ia64_mv_teardown_msi_irq_t       sn_teardown_msi_irq;
 extern ia64_mv_pci_fixup_bus_t          sn_pci_fixup_bus;
@@ -121,6 +122,7 @@ extern ia64_mv_pci_fixup_bus_t		sn_pci_fixup_bus;
 #define platform_dma_mapping_error              sn_dma_mapping_error
 #define platform_dma_supported          sn_dma_supported
 #define platform_migrate                sn_migrate
+#define platform_kernel_launch_event    sn_kernel_launch_event
 #ifdef CONFIG_PCI_MSI
 #define platform_setup_msi_irq          sn_setup_msi_irq
 #define platform_teardown_msi_irq       sn_teardown_msi_irq
diff --git a/include/asm-ia64/meminit.h b/include/asm-ia64/meminit.h
index c3b1f862e6e7..c8df75901083 100644
--- a/include/asm-ia64/meminit.h
+++ b/include/asm-ia64/meminit.h
@@ -15,11 +15,12 @@
  *      - initrd (optional)
  *      - command line string
  *      - kernel code & data
+ *      - crash dumping code reserved region
  *      - Kernel memory map built from EFI memory map
  *
  * More could be added if necessary
  */
-#define IA64_MAX_RSVD_REGIONS 6
+#define IA64_MAX_RSVD_REGIONS 7
 
 struct rsvd_region {
         unsigned long start;    /* virtual address of beginning of element */
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
index 947cb72b520e..485759ba9e36 100644
--- a/include/asm-ia64/page.h
+++ b/include/asm-ia64/page.h
@@ -101,7 +101,7 @@ do {						\
 
 #ifdef CONFIG_VIRTUAL_MEM_MAP
 extern int ia64_pfn_valid (unsigned long pfn);
-#elif defined(CONFIG_FLATMEM)
+#else
 # define ia64_pfn_valid(pfn) 1
 #endif
 
@@ -110,12 +110,11 @@ extern struct page *vmem_map;
 #ifdef CONFIG_DISCONTIGMEM
 # define page_to_pfn(page)      ((unsigned long) (page - vmem_map))
 # define pfn_to_page(pfn)       (vmem_map + (pfn))
+#else
+# include <asm-generic/memory_model.h>
 #endif
-#endif
-
-#if defined(CONFIG_FLATMEM) || defined(CONFIG_SPARSEMEM)
-/* FLATMEM always configures mem_map (mem_map = vmem_map if necessary) */
-#include <asm-generic/memory_model.h>
+#else
+# include <asm-generic/memory_model.h>
 #endif
 
 #ifdef CONFIG_FLATMEM
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 4283ddcc25fb..bc768153f3c9 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -20,6 +20,8 @@
  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
  * 00/05/25     eranian Support for stack calls, and static physical calls
  * 00/06/18     eranian Support for stacked physical calls
+ * 06/10/26     rja     Support for Intel Itanium Architecture Software Developer's
+ *                      Manual Rev 2.2 (Jan 2006)
  */
 
 /*
@@ -69,6 +71,8 @@
 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
+#define PAL_GET_HW_POLICY       48      /* Get current hardware resource sharing policy */
+#define PAL_SET_HW_POLICY       49      /* Set current hardware resource sharing policy */
 
 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
@@ -80,6 +84,11 @@
 #define PAL_SET_PSTATE          263     /* set the P-state */
 #define PAL_BRAND_INFO          274     /* Processor branding information */
 
+#define PAL_GET_PSTATE_TYPE_LASTSET     0
+#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
+#define PAL_GET_PSTATE_TYPE_AVGNORESET  2
+#define PAL_GET_PSTATE_TYPE_INSTANT     3
+
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
@@ -102,6 +111,7 @@ typedef s64				pal_status_t;
                                                  * cache without sideeffects
                                                  * and "restrict" was 1
                                                  */
+#define PAL_STATUS_REQUIRES_MEMORY      (-9)    /* Call requires PAL memory buffer */
 
 /* Processor cache level in the heirarchy */
 typedef u64                             pal_cache_level_t;
@@ -456,7 +466,9 @@ typedef struct pal_process_state_info_s {
                                                  * by the processor
                                                  */
 
-                        reserved2       : 11,
+                        se              : 1,    /* Shared error.  MCA in a
+                                                   shared structure */
+                        reserved2       : 10,
                         cc              : 1,    /* Cache check */
                         tc              : 1,    /* TLB check */
                         bc              : 1,    /* Bus check */
@@ -487,10 +499,12 @@ typedef struct pal_cache_check_info_s {
                                                  * error occurred
                                                  */
                         wiv             : 1,    /* Way field valid */
-                        reserved2       : 10,
+                        reserved2       : 1,
+                        dp              : 1,    /* Data poisoned on MBE */
+                        reserved3       : 8,
 
                         index           : 20,   /* Cache line index */
-                        reserved3       : 2,
+                        reserved4       : 2,
 
                         is              : 1,    /* instruction set (1 == ia32) */
                         iv              : 1,    /* instruction set field valid */
@@ -557,7 +571,7 @@ typedef struct pal_bus_check_info_s {
                         type            : 8,    /* Bus xaction type*/
                         sev             : 5,    /* Bus error severity*/
                         hier            : 2,    /* Bus hierarchy level */
-                        reserved1       : 1,
+                        dp              : 1,    /* Data poisoned on MBE */
                         bsi             : 8,    /* Bus error status
                                                  * info
                                                  */
@@ -834,7 +848,9 @@ typedef union pal_bus_features_u {
                 u64     pbf_req_bus_parking                     :       1;
                 u64     pbf_bus_lock_mask                       :       1;
                 u64     pbf_enable_half_xfer_rate               :       1;
-                u64     pbf_reserved2                           :       22;
+                u64     pbf_reserved2                           :       20;
+                u64     pbf_enable_shared_line_replace          :       1;
+                u64     pbf_enable_exclusive_line_replace       :       1;
                 u64     pbf_disable_xaction_queueing            :       1;
                 u64     pbf_disable_resp_err_check              :       1;
                 u64     pbf_disable_berr_check                  :       1;
@@ -1077,6 +1093,24 @@ ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *
         return iprv.status;
 }
 
+/*
+ * Get the current hardware resource sharing policy of the processor
+ */
+static inline s64
+ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
+                        u64 *la)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
+        if (cur_policy)
+                *cur_policy = iprv.v0;
+        if (num_impacted)
+                *num_impacted = iprv.v1;
+        if (la)
+                *la = iprv.v2;
+        return iprv.status;
+}
+
 /* Make the processor enter HALT or one of the implementation dependent low
  * power states where prefetching and execution are suspended and cache and
  * TLB coherency is not maintained.
@@ -1112,10 +1146,10 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
 
 /* Get the current P-state information */
 static inline s64
-ia64_pal_get_pstate (u64 *pstate_index)
+ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
 {
         struct ia64_pal_retval iprv;
-        PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
+        PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
         *pstate_index = iprv.v0;
         return iprv.status;
 }
@@ -1401,6 +1435,17 @@ ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
         return iprv.status;
 }
 
+/*
+ * Set the current hardware resource sharing policy of the processor
+ */
+static inline s64
+ia64_pal_set_hw_policy (u64 policy)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
+        return iprv.status;
+}
+
 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
  * suspended, but cause cache and TLB coherency to be maintained.
  * This is usually called in IA-32 mode.
@@ -1524,12 +1569,15 @@ typedef union pal_vm_info_1_u {
         } pal_vm_info_1_s;
 } pal_vm_info_1_u_t;
 
+#define PAL_MAX_PURGES          0xFFFF          /* all ones is means unlimited */
+
 typedef union pal_vm_info_2_u {
         u64                     pvi2_val;
         struct {
                 u64             impl_va_msb     : 8,
                                 rid_size        : 8,
-                                reserved        : 48;
+                                max_purges      : 16,
+                                reserved        : 32;
         } pal_vm_info_2_s;
 } pal_vm_info_2_u_t;
 
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index be5d83ad7cb1..2c4004eb5a68 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -88,6 +88,8 @@
 #define  SN_SAL_INJECT_ERROR                       0x02000067
 #define  SN_SAL_SET_CPU_NUMBER                     0x02000068
 
+#define  SN_SAL_KERNEL_LAUNCH_EVENT                0x02000069
+
 /*
  * Service-specific constants
  */
@@ -1155,4 +1157,11 @@ ia64_sn_set_cpu_number(int cpu)
         SAL_CALL_NOLOCK(rv, SN_SAL_SET_CPU_NUMBER, cpu, 0, 0, 0, 0, 0, 0);
         return rv.status;
 }
+static inline int
+ia64_sn_kernel_launch_event(void)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_KERNEL_LAUNCH_EVENT, 0, 0, 0, 0, 0, 0, 0);
+        return rv.status;
+}
 #endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/termbits.h b/include/asm-ia64/termbits.h
index b9e843f7dc42..4531a511bde5 100644
--- a/include/asm-ia64/termbits.h
+++ b/include/asm-ia64/termbits.h
@@ -26,6 +26,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-ia64/topology.h b/include/asm-ia64/topology.h
index a6e38565ab4c..22ed6749557e 100644
--- a/include/asm-ia64/topology.h
+++ b/include/asm-ia64/topology.h
@@ -101,6 +101,7 @@ void build_cpu_to_node_map(void);
         .flags                  = SD_LOAD_BALANCE       \
                                 | SD_BALANCE_EXEC       \
                                 | SD_BALANCE_FORK       \
+                                | SD_SERIALIZE          \
                                 | SD_WAKE_BALANCE,      \
         .last_balance           = jiffies,              \
         .balance_interval       = 64,                   \
diff --git a/include/asm-m32r/ide.h b/include/asm-m32r/ide.h
index 219a0f74eff3..c82ebe8f250d 100644
--- a/include/asm-m32r/ide.h
+++ b/include/asm-m32r/ide.h
@@ -32,7 +32,8 @@
 static __inline__ int ide_default_irq(unsigned long base)
 {
         switch (base) {
-#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2)
+#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) \
+        || defined(CONFIG_PLAT_OPSPUT)
                 case 0x1f0: return PLD_IRQ_CFIREQ;
                 default:
                         return 0;
diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h
index a1f0d1fe9eb8..52807f8db166 100644
--- a/include/asm-m32r/m32102.h
+++ b/include/asm-m32r/m32102.h
@@ -104,7 +104,8 @@
 #define M32R_MFT5RLD_PORTL     (0x0C+M32R_MFT5_OFFSET)  /* MFT4 reload */
 #define M32R_MFT5CMPRLD_PORTL  (0x10+M32R_MFT5_OFFSET)  /* MFT4 compare reload */
 
-#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32104)
+#if (defined(CONFIG_CHIP_M32700) && !defined(CONFIG_PLAT_MAPPI2)) \
+        || defined(CONFIG_CHIP_M32104)
 #define M32R_MFTCR_MFT0MSK  (1UL<<31)  /* b0 */
 #define M32R_MFTCR_MFT1MSK  (1UL<<30)  /* b1 */
 #define M32R_MFTCR_MFT2MSK  (1UL<<29)  /* b2 */
@@ -117,7 +118,7 @@
 #define M32R_MFTCR_MFT3EN   (1UL<<20)  /* b11 */
 #define M32R_MFTCR_MFT4EN   (1UL<<19)  /* b12 */
 #define M32R_MFTCR_MFT5EN   (1UL<<18)  /* b13 */
-#else   /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */
+#else
 #define M32R_MFTCR_MFT0MSK  (1UL<<15)  /* b16 */
 #define M32R_MFTCR_MFT1MSK  (1UL<<14)  /* b17 */
 #define M32R_MFTCR_MFT2MSK  (1UL<<13)  /* b18 */
@@ -130,7 +131,7 @@
 #define M32R_MFTCR_MFT3EN   (1UL<<4)   /* b27 */
 #define M32R_MFTCR_MFT4EN   (1UL<<3)   /* b28 */
 #define M32R_MFTCR_MFT5EN   (1UL<<2)   /* b29 */
-#endif  /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */
+#endif
 
 #define M32R_MFTMOD_CC_MASK    (1UL<<15)  /* b16 */
 #define M32R_MFTMOD_TCCR       (1UL<<13)  /* b18 */
diff --git a/include/asm-m32r/ptrace.h b/include/asm-m32r/ptrace.h
index 2d2a6c97331e..632b4ce4269a 100644
--- a/include/asm-m32r/ptrace.h
+++ b/include/asm-m32r/ptrace.h
@@ -33,21 +33,10 @@
 #define PT_R15          PT_SP
 
 /* processor status and miscellaneous context registers.  */
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
 #define PT_ACC0H        15
 #define PT_ACC0L        16
-#define PT_ACC1H        17
-#define PT_ACC1L        18
-#define PT_ACCH         PT_ACC0H
-#define PT_ACCL         PT_ACC0L
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
-#define PT_ACCH         15
-#define PT_ACCL         16
-#define PT_DUMMY_ACC1H  17
-#define PT_DUMMY_ACC1L  18
-#else
-#error unknown isa conifiguration
-#endif
+#define PT_ACC1H        17      /* ISA_DSP_LEVEL2 only */
+#define PT_ACC1L        18      /* ISA_DSP_LEVEL2 only */
 #define PT_PSW          19
 #define PT_BPC          20
 #define PT_BBPSW        21
@@ -103,19 +92,10 @@ struct pt_regs {
         long syscall_nr;
 
         /* Saved main processor status and miscellaneous context registers. */
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
         unsigned long acc0h;
         unsigned long acc0l;
-        unsigned long acc1h;
-        unsigned long acc1l;
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
-        unsigned long acch;
-        unsigned long accl;
-        unsigned long dummy_acc1h;
-        unsigned long dummy_acc1l;
-#else
-#error unknown isa configuration
-#endif
+        unsigned long acc1h;    /* ISA_DSP_LEVEL2 only */
+        unsigned long acc1l;    /* ISA_DSP_LEVEL2 only */
         unsigned long psw;
         unsigned long bpc;              /* saved PC for TRAP syscalls */
         unsigned long bbpsw;
diff --git a/include/asm-m32r/sigcontext.h b/include/asm-m32r/sigcontext.h
index 73025c0c41a1..62537dc4dec9 100644
--- a/include/asm-m32r/sigcontext.h
+++ b/include/asm-m32r/sigcontext.h
@@ -23,19 +23,10 @@ struct sigcontext {
         unsigned long sc_r12;
 
         /* Saved main processor status and miscellaneous context registers. */
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
         unsigned long sc_acc0h;
         unsigned long sc_acc0l;
-        unsigned long sc_acc1h;
-        unsigned long sc_acc1l;
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
-        unsigned long sc_acch;
-        unsigned long sc_accl;
-        unsigned long sc_dummy_acc1h;
-        unsigned long sc_dummy_acc1l;
-#else
-#error unknown isa configuration
-#endif
+        unsigned long sc_acc1h; /* ISA_DSP_LEVEL2 only */
+        unsigned long sc_acc1l; /* ISA_DSP_LEVEL2 only */
         unsigned long sc_psw;
         unsigned long sc_bpc;           /* saved PC for TRAP syscalls */
         unsigned long sc_bbpsw;
diff --git a/include/asm-m32r/termbits.h b/include/asm-m32r/termbits.h
index 5ace3702df75..faf2bd0504c1 100644
--- a/include/asm-m32r/termbits.h
+++ b/include/asm-m32r/termbits.h
@@ -19,6 +19,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-m68k/sun3-head.h b/include/asm-m68k/sun3-head.h
index f799d95bad53..e74f384e269f 100644
--- a/include/asm-m68k/sun3-head.h
+++ b/include/asm-m68k/sun3-head.h
@@ -4,7 +4,6 @@
 
 #define KERNBASE        0xE000000  /* First address the kernel will eventually be */
 #define LOAD_ADDR       0x4000      /* prom jumps to us here unless this is elf /boot */
-#define BI_START (KERNBASE + 0x3000) /* beginning of the bootinfo records */
 #define FC_CONTROL  3
 #define FC_SUPERD    5
 #define FC_CPU      7
diff --git a/include/asm-m68k/sun3ints.h b/include/asm-m68k/sun3ints.h
index de91fa071b99..309d6e6a1374 100644
--- a/include/asm-m68k/sun3ints.h
+++ b/include/asm-m68k/sun3ints.h
@@ -16,6 +16,7 @@
 #include <asm/intersil.h>
 #include <asm/oplib.h>
 #include <asm/traps.h>
+#include <asm/irq.h>
 
 #define SUN3_INT_VECS 192
 
diff --git a/include/asm-m68k/termbits.h b/include/asm-m68k/termbits.h
index e9eec3eb0718..a194092240fb 100644
--- a/include/asm-m68k/termbits.h
+++ b/include/asm-m68k/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 1e5ccdad3b02..8e321f53a382 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -131,6 +131,7 @@
 #define  MACH_PHILIPS_NINO      0       /* Nino */
 #define  MACH_PHILIPS_VELO      1       /* Velo */
 #define  MACH_PHILIPS_JBS       2       /* JBS */
+#define  MACH_PHILIPS_STB810    3       /* STB810 */
 
 /*
  * Valid machtype for group SIBYTE
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
index 55a0152feb08..432653d7ae09 100644
--- a/include/asm-mips/compat.h
+++ b/include/asm-mips/compat.h
@@ -5,6 +5,7 @@
  */
 #include <linux/types.h>
 #include <asm/page.h>
+#include <asm/ptrace.h>
 
 #define COMPAT_USER_HZ  100
 
diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h
index 806213ce31b6..25f0c3f39adf 100644
--- a/include/asm-mips/mach-ip27/irq.h
+++ b/include/asm-mips/mach-ip27/irq.h
@@ -10,8 +10,6 @@
 #ifndef __ASM_MACH_IP27_IRQ_H
 #define __ASM_MACH_IP27_IRQ_H
 
-#include <asm/sn/arch.h>
-
 /*
  * A hardwired interrupt number is completly stupid for this system - a
  * large configuration might have thousands if not tenthousands of
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
index a13b715fd9ca..44790fdc5d00 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_MACH_TOPOLOGY_H
 #define _ASM_MACH_TOPOLOGY_H    1
 
-#include <asm/sn/arch.h>
 #include <asm/sn/hub.h>
 #include <asm/mmzone.h>
 
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h
index 11410ae10d36..11410ae10d36 100644
--- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-rm200/mc146818rtc.h b/include/asm-mips/mach-rm/mc146818rtc.h
index d37ae68dc6a3..d37ae68dc6a3 100644
--- a/include/asm-mips/mach-rm200/mc146818rtc.h
+++ b/include/asm-mips/mach-rm/mc146818rtc.h
diff --git a/include/asm-mips/mach-rm200/timex.h b/include/asm-mips/mach-rm/timex.h
index 11ff6cb0f214..11ff6cb0f214 100644
--- a/include/asm-mips/mach-rm200/timex.h
+++ b/include/asm-mips/mach-rm/timex.h
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c4d68bebdca6..7f0f120ca07c 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -187,4 +187,10 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 /* Do platform specific device initialization at pci_enable_device() time */
 extern int pcibios_plat_dev_init(struct pci_dev *dev);
 
+/* Chances are this interrupt is wired PC-style ...  */
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+        return channel ? 15 : 14;
+}
+
 #endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 30bf555faeaa..8a1f2b6f04ac 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -82,6 +82,14 @@ struct pt_regs {
 
 extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
 
+extern NORET_TYPE void die(const char *, struct pt_regs *);
+
+static inline void die_if_kernel(const char *str, struct pt_regs *regs)
+{
+        if (unlikely(!user_mode(regs)))
+                die(str, regs);
+}
+
 #endif
 
 #endif /* _ASM_PTRACE_H */
diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h
index 51174af6ac52..da523de628be 100644
--- a/include/asm-mips/sn/arch.h
+++ b/include/asm-mips/sn/arch.h
@@ -18,7 +18,6 @@
 #endif
 
 typedef u64     hubreg_t;
-typedef u64     nic_t;
 
 #define cputonasid(cpu)                 (cpu_data[(cpu)].p_nasid)
 #define cputoslice(cpu)                 (cpu_data[(cpu)].p_slice)
diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h
index 15d70ca56187..82aeb9e322db 100644
--- a/include/asm-mips/sn/klconfig.h
+++ b/include/asm-mips/sn/klconfig.h
@@ -61,6 +61,8 @@
 #endif /* CONFIG_SGI_IP35 */
 #endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
 
+typedef u64  nic_t;
+
 #define KLCFGINFO_MAGIC 0xbeedbabe
 
 typedef s32 klconf_off_t;
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 9428057a50cf..5e1289c85ed9 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -19,7 +19,6 @@
 #include <asm/barrier.h>
 #include <asm/cpu-features.h>
 #include <asm/dsp.h>
-#include <asm/ptrace.h>
 #include <asm/war.h>
 
 
@@ -336,14 +335,6 @@ extern void *set_except_vector(int n, void *addr);
 extern unsigned long ebase;
 extern void per_cpu_trap_init(void);
 
-extern NORET_TYPE void die(const char *, struct pt_regs *);
-
-static inline void die_if_kernel(const char *str, struct pt_regs *regs)
-{
-        if (unlikely(!user_mode(regs)))
-                die(str, regs);
-}
-
 extern int stop_a_enabled;
 
 /*
diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h
index b62ec7c521cc..0bbe07b42a07 100644
--- a/include/asm-mips/termbits.h
+++ b/include/asm-mips/termbits.h
@@ -30,6 +30,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR            0              /* Interrupt character [ISIG].  */
 #define VQUIT            1              /* Quit character [ISIG].  */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index 3ac146c019c9..13a3502eef44 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -76,7 +76,7 @@
 /*
  * But the RM200C seems to have been shipped only with V2.0 R4600s
  */
-#ifdef CONFIG_SNI_RM200_PCI
+#ifdef CONFIG_SNI_RM
 
 #define R4600_V2_HIT_CACHEOP_WAR        1
 
diff --git a/include/asm-parisc/termbits.h b/include/asm-parisc/termbits.h
index 372b634892c9..a46e299a9391 100644
--- a/include/asm-parisc/termbits.h
+++ b/include/asm-parisc/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild
index 1e637381c118..703970fb0ec0 100644
--- a/include/asm-powerpc/Kbuild
+++ b/include/asm-powerpc/Kbuild
@@ -17,7 +17,6 @@ header-y += ipc.h
 header-y += poll.h
 header-y += shmparam.h
 header-y += sockios.h
-header-y += spu_info.h
 header-y += ucontext.h
 header-y += ioctl.h
 header-y += linkage.h
@@ -37,6 +36,7 @@ unifdef-y += posix_types.h
 unifdef-y += ptrace.h
 unifdef-y += seccomp.h
 unifdef-y += signal.h
+unifdef-y += spu_info.h
 unifdef-y += termios.h
 unifdef-y += types.h
 unifdef-y += unistd.h
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
index c341063d0804..8f757f6246e4 100644
--- a/include/asm-powerpc/bitops.h
+++ b/include/asm-powerpc/bitops.h
@@ -190,7 +190,8 @@ static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
  * Return the zero-based bit position (LE, not IBM bit numbering) of
  * the most significant 1-bit in a double word.
  */
-static __inline__ int __ilog2(unsigned long x)
+static __inline__ __attribute__((const))
+int __ilog2(unsigned long x)
 {
         int lz;
 
@@ -198,6 +199,24 @@ static __inline__ int __ilog2(unsigned long x)
         return BITS_PER_LONG - 1 - lz;
 }
 
+static inline __attribute__((const))
+int __ilog2_u32(u32 n)
+{
+        int bit;
+        asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
+        return 31 - bit;
+}
+
+#ifdef __powerpc64__
+static inline __attribute__((const))
+int __ilog2_u64(u64 n)
+{
+        int bit;
+        asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
+        return 63 - bit;
+}
+#endif
+
 /*
  * Determines the bit position of the least significant 0 bit in the
  * specified double word. The returned bit position will be
diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h
index 978b2c7e84ea..709568879f73 100644
--- a/include/asm-powerpc/bug.h
+++ b/include/asm-powerpc/bug.h
@@ -13,36 +13,39 @@
 
 #ifndef __ASSEMBLY__
 
-struct bug_entry {
-        unsigned long   bug_addr;
-        long            line;
-        const char      *file;
-        const char      *function;
-};
-
-struct bug_entry *find_bug(unsigned long bugaddr);
-
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP        0x1000000
-
 #ifdef CONFIG_BUG
 
+/* _EMIT_BUG_ENTRY expects args %0,%1,%2,%3 to be FILE, LINE, flags and
+   sizeof(struct bug_entry), respectively */
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+#define _EMIT_BUG_ENTRY                         \
+        ".section __bug_table,\"a\"\n"          \
+        "2:\t" PPC_LONG "1b, %0\n"              \
+        "\t.short %1, %2\n"                     \
+        ".org 2b+%3\n"                          \
+        ".previous\n"
+#else
+#define _EMIT_BUG_ENTRY                         \
+        ".section __bug_table,\"a\"\n"          \
+        "2:\t" PPC_LONG "1b\n"                  \
+        "\t.short %2\n"                         \
+        ".org 2b+%3\n"                          \
+        ".previous\n"
+#endif
+
 /*
  * BUG_ON() and WARN_ON() do their best to cooperate with compile-time
  * optimisations. However depending on the complexity of the condition
  * some compiler versions may not produce optimal results.
  */
 
-#define BUG() do {                                                       \
-        __asm__ __volatile__(                                            \
-                "1:     twi 31,0,0\n"                                    \
-                ".section __bug_table,\"a\"\n"                           \
-                "\t"PPC_LONG"   1b,%0,%1,%2\n"                           \
-                ".previous"                                              \
-                : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
+#define BUG() do {                                              \
+        __asm__ __volatile__(                                   \
+                "1:     twi 31,0,0\n"                           \
+                _EMIT_BUG_ENTRY                                 \
+                : : "i" (__FILE__), "i" (__LINE__),             \
+                    "i" (0), "i"  (sizeof(struct bug_entry)));  \
+        for(;;) ;                                               \
 } while (0)
 
 #define BUG_ON(x) do {                                          \
@@ -51,23 +54,21 @@ struct bug_entry *find_bug(unsigned long bugaddr);
                         BUG();                                  \
         } else {                                                \
                 __asm__ __volatile__(                           \
-                "1:     "PPC_TLNEI"     %0,0\n"                 \
-                ".section __bug_table,\"a\"\n"                  \
-                "\t"PPC_LONG"   1b,%1,%2,%3\n"                  \
-                ".previous"                                     \
-                : : "r" ((long)(x)), "i" (__LINE__),            \
-                    "i" (__FILE__), "i" (__FUNCTION__));        \
+                "1:     "PPC_TLNEI"     %4,0\n"                 \
+                _EMIT_BUG_ENTRY                                 \
+                : : "i" (__FILE__), "i" (__LINE__), "i" (0),    \
+                  "i" (sizeof(struct bug_entry)),               \
+                  "r" ((long)(x)));                             \
         }                                                       \
 } while (0)
 
 #define __WARN() do {                                           \
         __asm__ __volatile__(                                   \
                 "1:     twi 31,0,0\n"                           \
-                ".section __bug_table,\"a\"\n"                  \
-                "\t"PPC_LONG"   1b,%0,%1,%2\n"                  \
-                ".previous"                                     \
-                : : "i" (__LINE__ + BUG_WARNING_TRAP),          \
-                    "i" (__FILE__), "i" (__FUNCTION__));        \
+                _EMIT_BUG_ENTRY                                 \
+                : : "i" (__FILE__), "i" (__LINE__),             \
+                  "i" (BUGFLAG_WARNING),                        \
+                  "i" (sizeof(struct bug_entry)));              \
 } while (0)
 
 #define WARN_ON(x) ({                                           \
@@ -77,13 +78,12 @@ struct bug_entry *find_bug(unsigned long bugaddr);
                         __WARN();                               \
         } else {                                                \
                 __asm__ __volatile__(                           \
-                "1:     "PPC_TLNEI"     %0,0\n"                 \
-                ".section __bug_table,\"a\"\n"                  \
-                "\t"PPC_LONG"   1b,%1,%2,%3\n"                  \
-                ".previous"                                     \
-                : : "r" (__ret_warn_on),                        \
-                    "i" (__LINE__ + BUG_WARNING_TRAP),          \
-                    "i" (__FILE__), "i" (__FUNCTION__));        \
+                "1:     "PPC_TLNEI"     %4,0\n"                 \
+                _EMIT_BUG_ENTRY                                 \
+                : : "i" (__FILE__), "i" (__LINE__),             \
+                  "i" (BUGFLAG_WARNING),                        \
+                  "i" (sizeof(struct bug_entry)),               \
+                  "r" (__ret_warn_on));                         \
         }                                                       \
         unlikely(__ret_warn_on);                                \
 })
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 6fe5c9d4ca3b..7384b8086b75 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -126,6 +126,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 #define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
 #define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
+#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
 
 /*
  * Add the 64-bit processor unique features in the top half of the word;
@@ -152,6 +153,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
+#define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -295,6 +297,9 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTRS_E300   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
             CPU_FTR_COMMON)
+#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
 #define CPU_FTRS_8XX    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
@@ -330,13 +335,14 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE)
+            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
+            CPU_FTR_DSCR)
 #define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
             CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
-            CPU_FTR_SPURR | CPU_FTR_REAL_LE)
+            CPU_FTR_SPURR | CPU_FTR_REAL_LE | CPU_FTR_DSCR)
 #define CPU_FTRS_CELL   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -364,7 +370,8 @@ enum {
             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
-            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
+            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
+            CPU_FTRS_CLASSIC32 |
 #else
             CPU_FTRS_GENERIC_32 |
 #endif
@@ -403,7 +410,8 @@ enum {
             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
-            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
+            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
+            CPU_FTRS_CLASSIC32 &
 #else
             CPU_FTRS_GENERIC_32 &
 #endif
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
index fd4a5f5e33d1..d7a1bc1551c6 100644
--- a/include/asm-powerpc/dcr-native.h
+++ b/include/asm-powerpc/dcr-native.h
@@ -20,8 +20,7 @@
 #ifndef _ASM_POWERPC_DCR_NATIVE_H
 #define _ASM_POWERPC_DCR_NATIVE_H
 #ifdef __KERNEL__
-
-#include <asm/reg.h>
+#ifndef __ASSEMBLY__
 
 typedef struct {} dcr_host_t;
 
@@ -32,7 +31,41 @@ typedef struct {} dcr_host_t;
 #define dcr_read(host, dcr_n)           mfdcr(dcr_n)
 #define dcr_write(host, dcr_n, value)   mtdcr(dcr_n, value)
 
+/* Device Control Registers */
+void __mtdcr(int reg, unsigned int val);
+unsigned int __mfdcr(int reg);
+#define mfdcr(rn)                                               \
+        ({unsigned int rval;                                    \
+        if (__builtin_constant_p(rn))                           \
+                asm volatile("mfdcr %0," __stringify(rn)        \
+                              : "=r" (rval));                   \
+        else                                                    \
+                rval = __mfdcr(rn);                             \
+        rval;})
+
+#define mtdcr(rn, v)                                            \
+do {                                                            \
+        if (__builtin_constant_p(rn))                           \
+                asm volatile("mtdcr " __stringify(rn) ",%0"     \
+                              : : "r" (v));                     \
+        else                                                    \
+                __mtdcr(rn, v);                                 \
+} while (0)
+
+/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
+#define mfdcri(base, reg)                       \
+({                                              \
+        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
+        mfdcr(base ## _CFGDATA);                        \
+})
+
+#define mtdcri(base, reg, data)                 \
+do {                                            \
+        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
+        mtdcr(base ## _CFGDATA, data);          \
+} while (0)
 
+#endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_DCR_NATIVE_H */
 
diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
index 473f2c7fd892..b66c5e6941f0 100644
--- a/include/asm-powerpc/dcr.h
+++ b/include/asm-powerpc/dcr.h
@@ -20,6 +20,7 @@
 #ifndef _ASM_POWERPC_DCR_H
 #define _ASM_POWERPC_DCR_H
 #ifdef __KERNEL__
+#ifdef CONFIG_PPC_DCR
 
 #ifdef CONFIG_PPC_DCR_NATIVE
 #include <asm/dcr-native.h>
@@ -38,5 +39,6 @@ extern unsigned int dcr_resource_len(struct device_node *np,
                                      unsigned int index);
 #endif /* CONFIG_PPC_MERGE */
 
+#endif /* CONFIG_PPC_DCR */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_DCR_H */
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index d604863d72fb..9e4dd98eb220 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -107,25 +107,6 @@ static inline void local_irq_save_ptr(unsigned long *flags)
 
 #endif /* CONFIG_PPC64 */
 
-#define mask_irq(irq)                                           \
-        ({                                                      \
-                irq_desc_t *desc = get_irq_desc(irq);           \
-                if (desc->chip && desc->chip->disable)  \
-                        desc->chip->disable(irq);               \
-        })
-#define unmask_irq(irq)                                         \
-        ({                                                      \
-                irq_desc_t *desc = get_irq_desc(irq);           \
-                if (desc->chip && desc->chip->enable)   \
-                        desc->chip->enable(irq);                \
-        })
-#define ack_irq(irq)                                            \
-        ({                                                      \
-                irq_desc_t *desc = get_irq_desc(irq);           \
-                if (desc->chip && desc->chip->ack)      \
-                        desc->chip->ack(irq);           \
-        })
-
 /*
  * interrupt-retrigger: should we handle this via lost interrupts and IPIs
  * or should we not care like we do now ? --BenH.
diff --git a/include/asm-powerpc/module.h b/include/asm-powerpc/module.h
index 584fabfb4f08..e5f14b13ccf0 100644
--- a/include/asm-powerpc/module.h
+++ b/include/asm-powerpc/module.h
@@ -46,8 +46,6 @@ struct mod_arch_specific {
         unsigned int num_bugs;
 };
 
-extern struct bug_entry *module_find_bug(unsigned long bugaddr);
-
 /*
  * Select ELF headers.
  * Make empty section for module_frob_arch_sections to expand.
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
index 2677bad70f40..07f6d3cf5e5a 100644
--- a/include/asm-powerpc/page_32.h
+++ b/include/asm-powerpc/page_32.h
@@ -26,15 +26,7 @@ extern void clear_pages(void *page, int order);
 static inline void clear_page(void *page) { clear_pages(page, 0); }
 extern void copy_page(void *to, void *from);
 
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int lz;
-
-        size = (size-1) >> PAGE_SHIFT;
-        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
-        return 32 - lz;
-}
+#include <asm-generic/page.h>
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index 7bb7f9009806..cb02c9d1ef93 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -31,12 +31,12 @@ struct pci_controller {
         int last_busno;
 
         void __iomem *io_base_virt;
-        unsigned long io_base_phys;
+        resource_size_t io_base_phys;
 
         /* Some machines have a non 1:1 mapping of
          * the PCI memory space in the CPU bus space
          */
-        unsigned long pci_mem_offset;
+        resource_size_t pci_mem_offset;
         unsigned long pci_io_size;
 
         struct pci_ops *ops;
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index 16f13319c769..ac656ee6bb19 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -143,8 +143,13 @@ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
 #define HAVE_PCI_MMAP   1
 
-#ifdef CONFIG_PPC64
-/* pci_unmap_{single,page} is not a nop, thus... */
+#if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
+/*
+ * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
+ * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
+ * so on are not nops.
+ * and thus...
+ */
 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
         dma_addr_t ADDR_NAME;
 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
@@ -158,6 +163,20 @@ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
         (((PTR)->LEN_NAME) = (VAL))
 
+#else /* 32-bit && coherent */
+
+/* pci_unmap_{page,single} is a nop so... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)            (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+
+#endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */
+
+#ifdef CONFIG_PPC64
+
 /* The PCI address space does not equal the physical memory address
  * space (we have an IOMMU).  The IDE and SCSI device layers use
  * this boolean for bounce buffer decisions.
@@ -172,16 +191,8 @@ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
  */
 #define PCI_DMA_BUS_IS_PHYS     (1)
 
-/* pci_unmap_{page,single} is a nop so... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
-#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
-#define pci_unmap_len(PTR, LEN_NAME)            (0)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
-
 #endif /* CONFIG_PPC64 */
-        
+
 extern void pcibios_resource_to_bus(struct pci_dev *dev,
                         struct pci_bus_region *region,
                         struct resource *res);
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 6faae7b14d55..a3631b15754c 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -143,6 +143,7 @@
 
 /* Special Purpose Registers (SPRNs)*/
 #define SPRN_CTR        0x009   /* Count Register */
+#define SPRN_DSCR       0x11
 #define SPRN_CTRLF      0x088
 #define SPRN_CTRLT      0x098
 #define   CTRL_CT       0xc0000000      /* current thread */
@@ -163,6 +164,7 @@
 #define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
 #define SPRN_TBWU       0x11D   /* Time Base Upper Register (super, R/W) */
+#define SPRN_SPURR      0x134   /* Scaled PURR */
 #define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
 #define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
 #define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
index 5a0c136c0416..8eaa7b28d9d0 100644
--- a/include/asm-powerpc/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -159,6 +159,7 @@ extern struct rtas_t rtas;
 
 extern void enter_rtas(unsigned long);
 extern int rtas_token(const char *service);
+extern int rtas_service_present(const char *service);
 extern int rtas_call(int token, int, int, int *, ...);
 extern void rtas_restart(char *cmd);
 extern void rtas_power_off(void);
@@ -221,8 +222,6 @@ extern int rtas_get_error_log_max(void);
 extern spinlock_t rtas_data_buf_lock;
 extern char rtas_data_buf[RTAS_DATA_BUF_SIZE];
 
-extern void rtas_stop_self(void);
-
 /* RMO buffer reserved for user-space RTAS use */
 extern unsigned long rtas_rmo_buf;
 
diff --git a/include/asm-powerpc/termbits.h b/include/asm-powerpc/termbits.h
index 6d533b07aaf5..5e79198f7d18 100644
--- a/include/asm-powerpc/termbits.h
+++ b/include/asm-powerpc/termbits.h
@@ -30,6 +30,19 @@ struct termios {
         speed_t c_ospeed;               /* output speed */
 };
 
+/* For PowerPC the termios and ktermios are the same */
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t c_line;                    /* line discipline (== c_cc[19]) */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR            0
 #define VQUIT            1
diff --git a/include/asm-powerpc/topology.h b/include/asm-powerpc/topology.h
index 50c014007de7..6610495f5f16 100644
--- a/include/asm-powerpc/topology.h
+++ b/include/asm-powerpc/topology.h
@@ -66,6 +66,7 @@ static inline int pcibus_to_node(struct pci_bus *bus)
                                 | SD_BALANCE_EXEC       \
                                 | SD_BALANCE_NEWIDLE    \
                                 | SD_WAKE_IDLE          \
+                                | SD_SERIALIZE          \
                                 | SD_WAKE_BALANCE,      \
         .last_balance           = jiffies,              \
         .balance_interval       = 1,                    \
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
index 6c955d0c1ef0..4d35b844bc58 100644
--- a/include/asm-ppc/pci-bridge.h
+++ b/include/asm-ppc/pci-bridge.h
@@ -20,8 +20,8 @@ extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
 extern struct pci_controller* pcibios_alloc_controller(void);
 
 /* Helper function for setting up resources */
-extern void pci_init_resource(struct resource *res, unsigned long start,
-                              unsigned long end, int flags, char *name);
+extern void pci_init_resource(struct resource *res, resource_size_t start,
+                              resource_size_t end, int flags, char *name);
 
 /* Get the PCI host controller for a bus */
 extern struct pci_controller* pci_bus_to_hose(int bus);
@@ -50,12 +50,12 @@ struct pci_controller {
         int bus_offset;
 
         void __iomem *io_base_virt;
-        unsigned long io_base_phys;
+        resource_size_t io_base_phys;
 
         /* Some machines (PReP) have a non 1:1 mapping of
          * the PCI memory space in the CPU bus space
          */
-        unsigned long pci_mem_offset;
+        resource_size_t pci_mem_offset;
 
         struct pci_ops *ops;
         volatile unsigned int __iomem *cfg_addr;
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index 11ffaaa5da16..9d162028dab9 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -61,6 +61,27 @@ extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
  */
 #define PCI_DMA_BUS_IS_PHYS     (1)
 
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/*
+ * pci_unmap_{page,single} are NOPs but pci_dma_sync_single_for_cpu()
+ * and so on are not, so...
+ */
+
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
+        dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
+        __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)                  \
+        ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
+        (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)                    \
+        ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
+        (((PTR)->LEN_NAME) = (VAL))
+
+#else /* coherent */
+
 /* pci_unmap_{page,single} is a nop so... */
 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
@@ -69,6 +90,8 @@ extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
 #define pci_unmap_len(PTR, LEN_NAME)            (0)
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
 
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+
 #ifdef CONFIG_PCI
 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
                                         enum pci_dma_burst_strategy *strat,
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 602fbadeaf48..a263fc1e65c4 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -9,41 +9,9 @@
 #ifndef __ASM_PPC_REG_BOOKE_H__
 #define __ASM_PPC_REG_BOOKE_H__
 
-#ifndef __ASSEMBLY__
-/* Device Control Registers */
-void __mtdcr(int reg, unsigned int val);
-unsigned int __mfdcr(int reg);
-#define mfdcr(rn)                                               \
-        ({unsigned int rval;                                    \
-        if (__builtin_constant_p(rn))                           \
-                asm volatile("mfdcr %0," __stringify(rn)        \
-                              : "=r" (rval));                   \
-        else                                                    \
-                rval = __mfdcr(rn);                             \
-        rval;})
-
-#define mtdcr(rn, v)                                            \
-do {                                                            \
-        if (__builtin_constant_p(rn))                           \
-                asm volatile("mtdcr " __stringify(rn) ",%0"     \
-                              : : "r" (v));                     \
-        else                                                    \
-                __mtdcr(rn, v);                                 \
-} while (0)
-
-/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
-#define mfdcri(base, reg)                       \
-({                                              \
-        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
-        mfdcr(base ## _CFGDATA);                        \
-})
-
-#define mtdcri(base, reg, data)                 \
-do {                                            \
-        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
-        mtdcr(base ## _CFGDATA, data);          \
-} while (0)
+#include <asm/dcr.h>
 
+#ifndef __ASSEMBLY__
 /* Performance Monitor Registers */
 #define mfpmr(rn)       ({unsigned int rval; \
                         asm volatile("mfpmr %0," __stringify(rn) \
diff --git a/include/asm-s390/dasd.h b/include/asm-s390/dasd.h
index c042f9578081..604f68fa6f56 100644
--- a/include/asm-s390/dasd.h
+++ b/include/asm-s390/dasd.h
@@ -69,11 +69,13 @@ typedef struct dasd_information2_t {
  * 0x01: readonly (ro)
  * 0x02: use diag discipline (diag)
  * 0x04: set the device initially online (internal use only)
+ * 0x08: enable ERP related logging
  */
 #define DASD_FEATURE_DEFAULT         0x00
 #define DASD_FEATURE_READONLY        0x01
 #define DASD_FEATURE_USEDIAG         0x02
 #define DASD_FEATURE_INITIAL_ONLINE  0x04
+#define DASD_FEATURE_ERPLOG          0x08
 
 #define DASD_PARTN_BITS 2
 
diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h
index 363ea761d5ee..05ea6f172786 100644
--- a/include/asm-s390/page.h
+++ b/include/asm-s390/page.h
@@ -127,6 +127,26 @@ page_get_storage_key(unsigned long addr)
         return skey;
 }
 
+extern unsigned long max_pfn;
+
+static inline int pfn_valid(unsigned long pfn)
+{
+        unsigned long dummy;
+        int ccode;
+
+        if (pfn >= max_pfn)
+                return 0;
+
+        asm volatile(
+                "       lra     %0,0(%2)\n"
+                "       ipm     %1\n"
+                "       srl     %1,28\n"
+                : "=d" (dummy), "=d" (ccode)
+                : "a" (pfn << PAGE_SHIFT)
+                : "cc");
+        return !ccode;
+}
+
 #endif /* !__ASSEMBLY__ */
 
 /* to align the pointer to the (next) page boundary */
@@ -138,8 +158,6 @@ page_get_storage_key(unsigned long addr)
 #define __va(x)                 (void *)(unsigned long)(x)
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
-
-#define pfn_valid(pfn)          ((pfn) < max_mapnr)
 #define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
 
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
diff --git a/include/asm-s390/pgalloc.h b/include/asm-s390/pgalloc.h
index 28619de5ecae..0707a7e2fc16 100644
--- a/include/asm-s390/pgalloc.h
+++ b/include/asm-s390/pgalloc.h
@@ -25,8 +25,11 @@ extern void diag10(unsigned long addr);
  * Page allocation orders.
  */
 #ifndef __s390x__
+# define PTE_ALLOC_ORDER        0
+# define PMD_ALLOC_ORDER        0
 # define PGD_ALLOC_ORDER        1
 #else /* __s390x__ */
+# define PTE_ALLOC_ORDER        0
 # define PMD_ALLOC_ORDER        2
 # define PGD_ALLOC_ORDER        2
 #endif /* __s390x__ */
diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h
index 2d968a69ed1f..ae61aca5d483 100644
--- a/include/asm-s390/pgtable.h
+++ b/include/asm-s390/pgtable.h
@@ -107,23 +107,25 @@ extern char empty_zero_page[PAGE_SIZE];
  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  * area for the same reason. ;)
  */
+extern unsigned long vmalloc_end;
 #define VMALLOC_OFFSET  (8*1024*1024)
 #define VMALLOC_START   (((unsigned long) high_memory + VMALLOC_OFFSET) \
                          & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END     vmalloc_end
 
 /*
  * We need some free virtual space to be able to do vmalloc.
  * VMALLOC_MIN_SIZE defines the minimum size of the vmalloc
  * area. On a machine with 2GB memory we make sure that we
  * have at least 128MB free space for vmalloc. On a machine
- * with 4TB we make sure we have at least 1GB.
+ * with 4TB we make sure we have at least 128GB.
  */
 #ifndef __s390x__
 #define VMALLOC_MIN_SIZE        0x8000000UL
-#define VMALLOC_END             0x80000000UL
+#define VMALLOC_END_INIT        0x80000000UL
 #else /* __s390x__ */
-#define VMALLOC_MIN_SIZE        0x40000000UL
-#define VMALLOC_END             0x40000000000UL
+#define VMALLOC_MIN_SIZE        0x2000000000UL
+#define VMALLOC_END_INIT        0x40000000000UL
 #endif /* __s390x__ */
 
 /*
@@ -815,11 +817,17 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 
 #define kern_addr_valid(addr)   (1)
 
+extern int add_shared_memory(unsigned long start, unsigned long size);
+extern int remove_shared_memory(unsigned long start, unsigned long size);
+
 /*
  * No page table caches to initialise
  */
 #define pgtable_cache_init()    do { } while (0)
 
+#define __HAVE_ARCH_MEMMAP_INIT
+extern void memmap_init(unsigned long, int, unsigned long, unsigned long);
+
 #define __HAVE_ARCH_PTEP_ESTABLISH
 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
diff --git a/include/asm-s390/termbits.h b/include/asm-s390/termbits.h
index eb3f8bfabf61..585c78a6e407 100644
--- a/include/asm-s390/termbits.h
+++ b/include/asm-s390/termbits.h
@@ -25,6 +25,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-sh/termbits.h b/include/asm-sh/termbits.h
index 4f9822a8e7b4..f1b7b46f4e9a 100644
--- a/include/asm-sh/termbits.h
+++ b/include/asm-sh/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-sparc/termbits.h b/include/asm-sparc/termbits.h
index 1794d71134b7..5eb00a105d7c 100644
--- a/include/asm-sparc/termbits.h
+++ b/include/asm-sparc/termbits.h
@@ -31,6 +31,18 @@ struct termios {
 #endif
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t _x_cc[2];                  /* We need them to hold vmin/vtime */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR    0
 #define VQUIT    1
diff --git a/include/asm-sparc64/dma.h b/include/asm-sparc64/dma.h
index 27f65972b3bb..93e5a062df88 100644
--- a/include/asm-sparc64/dma.h
+++ b/include/asm-sparc64/dma.h
@@ -152,9 +152,9 @@ extern void dvma_init(struct sbus_bus *);
 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
 
 /* Yes, I hack a lot of elisp in my spare time... */
-#define DMA_ERROR_P(regs)  (((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
-#define DMA_IRQ_P(regs)    (((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
-#define DMA_WRITE_P(regs)  (((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
+#define DMA_ERROR_P(regs)  ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
+#define DMA_IRQ_P(regs)    ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
+#define DMA_WRITE_P(regs)  ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
 #define DMA_OFF(__regs)         \
 do {    u32 tmp = sbus_readl((__regs) + DMA_CSR); \
         tmp &= ~DMA_ENABLE; \
diff --git a/include/asm-sparc64/irqflags.h b/include/asm-sparc64/irqflags.h
new file mode 100644
index 000000000000..024fc54d0682
--- /dev/null
+++ b/include/asm-sparc64/irqflags.h
@@ -0,0 +1,89 @@
+/*
+ * include/asm-sparc64/irqflags.h
+ *
+ * IRQ flags handling
+ *
+ * This file gets included from lowlevel asm headers too, to provide
+ * wrapped versions of the local_irq_*() APIs, based on the
+ * raw_local_irq_*() functions from the lowlevel headers.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long flags;
+
+        __asm__ __volatile__(
+                "rdpr   %%pil, %0"
+                : "=r" (flags)
+        );
+
+        return flags;
+}
+
+#define raw_local_save_flags(flags) \
+                do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        __asm__ __volatile__(
+                "wrpr   %0, %%pil"
+                : /* no output */
+                : "r" (flags)
+                : "memory"
+        );
+}
+
+static inline void raw_local_irq_disable(void)
+{
+        __asm__ __volatile__(
+                "wrpr   15, %%pil"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory"
+        );
+}
+
+static inline void raw_local_irq_enable(void)
+{
+        __asm__ __volatile__(
+                "wrpr   0, %%pil"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory"
+        );
+}
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags > 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+
+        return raw_irqs_disabled_flags(flags);
+}
+
+/*
+ * For spinlocks, etc:
+ */
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+
+        raw_local_irq_disable();
+
+        return flags;
+}
+
+#define raw_local_irq_save(flags) \
+                do { (flags) = __raw_local_irq_save(); } while (0)
+
+#endif /* (__ASSEMBLY__) */
+
+#endif /* !(_ASM_IRQFLAGS_H) */
diff --git a/include/asm-sparc64/kprobes.h b/include/asm-sparc64/kprobes.h
index c9f5c34d318c..becc38fa06c5 100644
--- a/include/asm-sparc64/kprobes.h
+++ b/include/asm-sparc64/kprobes.h
@@ -13,7 +13,11 @@ typedef u32 kprobe_opcode_t;
 #define JPROBE_ENTRY(pentry)    (kprobe_opcode_t *)pentry
 #define arch_remove_kprobe(p)   do {} while (0)
 #define  ARCH_INACTIVE_KPROBE_COUNT 0
-#define flush_insn_slot(p)      do { } while (0)
+
+#define flush_insn_slot(p)              \
+do {    flushi(&(p)->ainsn.insn[0]);    \
+        flushi(&(p)->ainsn.insn[1]);    \
+} while (0)
 
 /* Architecture specific copy of original instruction*/
 struct arch_specific_insn {
@@ -23,7 +27,7 @@ struct arch_specific_insn {
 
 struct prev_kprobe {
         struct kprobe *kp;
-        unsigned int status;
+        unsigned long status;
         unsigned long orig_tnpc;
         unsigned long orig_tstate_pil;
 };
@@ -33,10 +37,7 @@ struct kprobe_ctlblk {
         unsigned long kprobe_status;
         unsigned long kprobe_orig_tnpc;
         unsigned long kprobe_orig_tstate_pil;
-        long *jprobe_saved_esp;
         struct pt_regs jprobe_saved_regs;
-        struct pt_regs *jprobe_saved_regs_location;
-        struct sparc_stackf jprobe_saved_stack;
         struct prev_kprobe prev_kprobe;
 };
 
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
index cef5e8270421..1294b7ce5d06 100644
--- a/include/asm-sparc64/rwsem.h
+++ b/include/asm-sparc64/rwsem.h
@@ -23,20 +23,33 @@ struct rw_semaphore {
         signed int count;
         spinlock_t              wait_lock;
         struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
 };
 
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
 #define __RWSEM_INITIALIZER(name) \
-{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) }
+{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) \
+  __RWSEM_DEP_MAP_INIT(name) }
 
 #define DECLARE_RWSEM(name) \
         struct rw_semaphore name = __RWSEM_INITIALIZER(name)
 
-static __inline__ void init_rwsem(struct rw_semaphore *sem)
-{
-        sem->count = RWSEM_UNLOCKED_VALUE;
-        spin_lock_init(&sem->wait_lock);
-        INIT_LIST_HEAD(&sem->wait_list);
-}
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+
+#define init_rwsem(sem)                                         \
+do {                                                            \
+        static struct lock_class_key __key;                     \
+                                                                \
+        __init_rwsem((sem), #sem, &__key);                      \
+} while (0)
 
 extern void __down_read(struct rw_semaphore *sem);
 extern int __down_read_trylock(struct rw_semaphore *sem);
@@ -46,6 +59,11 @@ extern void __up_read(struct rw_semaphore *sem);
 extern void __up_write(struct rw_semaphore *sem);
 extern void __downgrade_write(struct rw_semaphore *sem);
 
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        __down_write(sem);
+}
+
 static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
 {
         return atomic_add_return(delta, (atomic_t *)(&sem->count));
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index a8b7432c9a70..32281acb878b 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -7,6 +7,9 @@
 #include <asm/visasm.h>
 
 #ifndef __ASSEMBLY__
+
+#include <linux/irqflags.h>
+
 /*
  * Sparc (general) CPU types
  */
@@ -72,52 +75,6 @@ do {	__asm__ __volatile__("ba,pt	%%xcc, 1f\n\t" \
 
 #endif
 
-#define setipl(__new_ipl) \
-        __asm__ __volatile__("wrpr      %0, %%pil"  : : "r" (__new_ipl) : "memory")
-
-#define local_irq_disable() \
-        __asm__ __volatile__("wrpr      15, %%pil" : : : "memory")
-
-#define local_irq_enable() \
-        __asm__ __volatile__("wrpr      0, %%pil" : : : "memory")
-
-#define getipl() \
-({ unsigned long retval; __asm__ __volatile__("rdpr     %%pil, %0" : "=r" (retval)); retval; })
-
-#define swap_pil(__new_pil) \
-({      unsigned long retval; \
-        __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
-                             "wrpr      %1, %%pil" \
-                             : "=&r" (retval) \
-                             : "r" (__new_pil) \
-                             : "memory"); \
-        retval; \
-})
-
-#define read_pil_and_cli() \
-({      unsigned long retval; \
-        __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
-                             "wrpr      15, %%pil" \
-                             : "=r" (retval) \
-                             : : "memory"); \
-        retval; \
-})
-
-#define local_save_flags(flags)         ((flags) = getipl())
-#define local_irq_save(flags)           ((flags) = read_pil_and_cli())
-#define local_irq_restore(flags)                setipl((flags))
-
-/* On sparc64 IRQ flags are the PIL register.  A value of zero
- * means all interrupt levels are enabled, any other value means
- * only IRQ levels greater than that value will be received.
- * Consequently this means that the lowest IRQ level is one.
- */
-#define irqs_disabled()         \
-({      unsigned long flags;    \
-        local_save_flags(flags);\
-        (flags > 0);            \
-})
-
 #define nop()           __asm__ __volatile__ ("nop")
 
 #define read_barrier_depends()          do { } while(0)
diff --git a/include/asm-sparc64/termbits.h b/include/asm-sparc64/termbits.h
index b07715273ed4..705cd44b4173 100644
--- a/include/asm-sparc64/termbits.h
+++ b/include/asm-sparc64/termbits.h
@@ -33,6 +33,18 @@ struct termios {
 #endif
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t _x_cc[2];                  /* We need them to hold vmin/vtime */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR    0
 #define VQUIT    1
diff --git a/include/asm-sparc64/ttable.h b/include/asm-sparc64/ttable.h
index f2352606a79f..c2a16e188499 100644
--- a/include/asm-sparc64/ttable.h
+++ b/include/asm-sparc64/ttable.h
@@ -137,10 +137,49 @@
 #endif
 #define BREAKPOINT_TRAP TRAP(breakpoint_trap)
 
+#ifdef CONFIG_TRACE_IRQFLAGS
+
+#define TRAP_IRQ(routine, level)                        \
+        rdpr    %pil, %g2;                              \
+        wrpr    %g0, 15, %pil;                          \
+        sethi   %hi(1f-4), %g7;                         \
+        ba,pt   %xcc, etrap_irq;                        \
+         or     %g7, %lo(1f-4), %g7;                    \
+        nop;                                            \
+        nop;                                            \
+        nop;                                            \
+        .subsection     2;                              \
+1:      call    trace_hardirqs_off;                     \
+         nop;                                           \
+        mov     level, %o0;                             \
+        call    routine;                                \
+         add    %sp, PTREGS_OFF, %o1;                   \
+        ba,a,pt %xcc, rtrap_irq;                        \
+        .previous;
+
+#define TICK_SMP_IRQ                                    \
+        rdpr    %pil, %g2;                              \
+        wrpr    %g0, 15, %pil;                          \
+        sethi   %hi(1f-4), %g7;                         \
+        ba,pt   %xcc, etrap_irq;                        \
+         or     %g7, %lo(1f-4), %g7;                    \
+        nop;                                            \
+        nop;                                            \
+        nop;                                            \
+        .subsection     2;                              \
+1:      call    trace_hardirqs_off;                     \
+         nop;                                           \
+        call    smp_percpu_timer_interrupt;             \
+         add    %sp, PTREGS_OFF, %o0;                   \
+        ba,a,pt %xcc, rtrap_irq;                        \
+        .previous;
+
+#else
+
 #define TRAP_IRQ(routine, level)                        \
         rdpr    %pil, %g2;                              \
         wrpr    %g0, 15, %pil;                          \
-        b,pt    %xcc, etrap_irq;                        \
+        ba,pt   %xcc, etrap_irq;                        \
          rd     %pc, %g7;                               \
         mov     level, %o0;                             \
         call    routine;                                \
@@ -151,12 +190,14 @@
         rdpr    %pil, %g2;                              \
         wrpr    %g0, 15, %pil;                          \
         sethi   %hi(109f), %g7;                         \
-        b,pt    %xcc, etrap_irq;                        \
+        ba,pt   %xcc, etrap_irq;                        \
 109:     or     %g7, %lo(109b), %g7;                    \
         call    smp_percpu_timer_interrupt;             \
          add    %sp, PTREGS_OFF, %o0;                   \
         ba,a,pt %xcc, rtrap_irq;
 
+#endif
+
 #define TRAP_IVEC TRAP_NOSAVE(do_ivec)
 
 #define BTRAP(lvl) TRAP_ARG(bad_trap, lvl)
diff --git a/include/asm-um/bug.h b/include/asm-um/bug.h
index 1e22fa26ff06..3357c5e2468e 100644
--- a/include/asm-um/bug.h
+++ b/include/asm-um/bug.h
@@ -1,4 +1,6 @@
 #ifndef __UM_BUG_H
 #define __UM_BUG_H
-#include <asm-generic/bug.h>
+
+#include <asm/arch/bug.h>
+
 #endif
diff --git a/include/asm-v850/termbits.h b/include/asm-v850/termbits.h
index 212d4e279263..f3b433032089 100644
--- a/include/asm-v850/termbits.h
+++ b/include/asm-v850/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
diff --git a/include/asm-x86_64/bug.h b/include/asm-x86_64/bug.h
index 80ac1fe966ac..682606414913 100644
--- a/include/asm-x86_64/bug.h
+++ b/include/asm-x86_64/bug.h
@@ -1,30 +1,30 @@
 #ifndef __ASM_X8664_BUG_H
 #define __ASM_X8664_BUG_H 1
 
-#include <linux/stringify.h>
-
-/*
- * Tell the user there is some problem.  The exception handler decodes 
- * this frame.
- */
-struct bug_frame {
-        unsigned char ud2[2];
-        unsigned char push;
-        signed int filename;
-        unsigned char ret;
-        unsigned short line;
-} __attribute__((packed));
-
 #ifdef CONFIG_BUG
 #define HAVE_ARCH_BUG
-/* We turn the bug frame into valid instructions to not confuse
-   the disassembler. Thanks to Jan Beulich & Suresh Siddha
-   for nice instruction selection.
-   The magic numbers generate mov $64bitimm,%eax ; ret $offset. */
-#define BUG()                                                           \
-        asm volatile(                                                   \
-        "ud2 ; pushq $%c1 ; ret $%c0" ::                                \
-                     "i"(__LINE__), "i" (__FILE__))
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+#define BUG()                                                           \
+        do {                                                            \
+                asm volatile("1:\tud2\n"                                \
+                             ".pushsection __bug_table,\"a\"\n"         \
+                             "2:\t.quad 1b, %c0\n"                      \
+                             "\t.word %c1, 0\n"                         \
+                             "\t.org 2b+%c2\n"                          \
+                             ".popsection"                              \
+                             : : "i" (__FILE__), "i" (__LINE__),        \
+                                "i" (sizeof(struct bug_entry)));        \
+                for(;;) ;                                               \
+        } while(0)
+#else
+#define BUG()                                                           \
+        do {                                                            \
+                asm volatile("ud2");                                    \
+                for(;;) ;                                               \
+        } while(0)
+#endif
+
 void out_of_line_bug(void);
 #else
 static inline void out_of_line_bug(void) { }
diff --git a/include/asm-x86_64/ioctls.h b/include/asm-x86_64/ioctls.h
index 62caf8b6e4e1..3fc0b15a0d7e 100644
--- a/include/asm-x86_64/ioctls.h
+++ b/include/asm-x86_64/ioctls.h
@@ -46,6 +46,10 @@
 #define TIOCSBRK        0x5427  /* BSD compatibility */
 #define TIOCCBRK        0x5428  /* BSD compatibility */
 #define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TCGETS2         _IOR('T',0x2A, struct termios2)
+#define TCSETS2         _IOW('T',0x2B, struct termios2)
+#define TCSETSW2        _IOW('T',0x2C, struct termios2)
+#define TCSETSF2        _IOW('T',0x2D, struct termios2)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
 
diff --git a/include/asm-x86_64/termbits.h b/include/asm-x86_64/termbits.h
index bd950946e52c..6cfc3bb10c1a 100644
--- a/include/asm-x86_64/termbits.h
+++ b/include/asm-x86_64/termbits.h
@@ -17,6 +17,28 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 /* c_cc characters */
 #define VINTR 0
 #define VQUIT 1
@@ -118,6 +140,7 @@ struct termios {
 #define HUPCL   0002000
 #define CLOCAL  0004000
 #define CBAUDEX 0010000
+#define    BOTHER 0010000               /* non standard rate */
 #define    B57600 0010001
 #define   B115200 0010002
 #define   B230400 0010003
@@ -133,10 +156,12 @@ struct termios {
 #define  B3000000 0010015
 #define  B3500000 0010016
 #define  B4000000 0010017
-#define CIBAUD    002003600000  /* input baud rate (not used) */
+#define CIBAUD    002003600000  /* input baud rate */
 #define CMSPAR    010000000000          /* mark or space (stick) parity */
 #define CRTSCTS   020000000000          /* flow control */
 
+#define IBSHIFT   8             /* Shift from CBAUD to CIBAUD */
+
 /* c_lflag bits */
 #define ISIG    0000001
 #define ICANON  0000002
diff --git a/include/asm-x86_64/termios.h b/include/asm-x86_64/termios.h
index 041a91f7ddfb..443b225537f0 100644
--- a/include/asm-x86_64/termios.h
+++ b/include/asm-x86_64/termios.h
@@ -98,8 +98,10 @@ struct termio {
         copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
 })
 
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
 
 #endif  /* __KERNEL__ */
 
diff --git a/include/asm-x86_64/topology.h b/include/asm-x86_64/topology.h
index 5c8f49280dbc..2facec5914d2 100644
--- a/include/asm-x86_64/topology.h
+++ b/include/asm-x86_64/topology.h
@@ -47,6 +47,7 @@ extern int __node_distance(int, int);
         .flags                  = SD_LOAD_BALANCE       \
                                 | SD_BALANCE_FORK       \
                                 | SD_BALANCE_EXEC       \
+                                | SD_SERIALIZE          \
                                 | SD_WAKE_BALANCE,      \
         .last_balance           = jiffies,              \
         .balance_interval       = 1,                    \
diff --git a/include/asm-xtensa/asmmacro.h b/include/asm-xtensa/asmmacro.h
new file mode 100644
index 000000000000..76915cabad17
--- /dev/null
+++ b/include/asm-xtensa/asmmacro.h
@@ -0,0 +1,153 @@
+/*
+ * include/asm-xtensa/asmmacro.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_ASMMACRO_H
+#define _XTENSA_ASMMACRO_H
+
+#include <asm/variant/core.h>
+
+/*
+ * Some little helpers for loops. Use zero-overhead-loops
+ * where applicable and if supported by the processor.
+ *
+ * __loopi ar, at, size, inc
+ *         ar   register initialized with the start address
+ *         at   scratch register used by macro
+ *         size size immediate value
+ *         inc  increment
+ *
+ * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
+ *         ar   register initialized with the start address
+ *         as   register initialized with the size
+ *         at   scratch register use by macro
+ *         inc_log2     increment [in log2]
+ *         mask_log2    mask [in log2]
+ *         cond         true condition (used in loop'cond')
+ *         ncond        false condition (used in b'ncond')
+ *
+ * __loop  as
+ *         restart loop. 'as' register must not have been modified!
+ *
+ * __endla ar, at, incr
+ *         ar   start address (modified)
+ *         as   scratch register used by macro
+ *         inc  increment
+ */
+
+/*
+ * loop for given size as immediate
+ */
+
+        .macro  __loopi ar, at, size, incr
+
+#if XCHAL_HAVE_LOOPS
+                movi    \at, ((\size + \incr - 1) / (\incr))
+                loop    \at, 99f
+#else
+                addi    \at, \ar, \size
+                98:
+#endif
+
+        .endm
+
+/*
+ * loop for given size in register
+ */
+
+        .macro  __loops ar, as, at, incr_log2, mask_log2, cond, ncond
+
+#if XCHAL_HAVE_LOOPS
+                .ifgt \incr_log2 - 1
+                        addi    \at, \as, (1 << \incr_log2) - 1
+                        .ifnc \mask_log2,
+                                extui   \at, \at, \incr_log2, \mask_log2
+                        .else
+                                srli    \at, \at, \incr_log2
+                        .endif
+                .endif
+                loop\cond       \at, 99f
+#else
+                .ifnc \mask_log2,
+                        extui   \at, \as, \incr_log2, \mask_log2
+                .else
+                        .ifnc \ncond,
+                                srli    \at, \as, \incr_log2
+                        .endif
+                .endif
+                .ifnc \ncond,
+                        b\ncond \at, 99f
+
+                .endif
+                .ifnc \mask_log2,
+                        slli    \at, \at, \incr_log2
+                        add     \at, \ar, \at
+                .else
+                        add     \at, \ar, \as
+                .endif
+#endif
+                98:
+
+        .endm
+
+/*
+ * loop from ar to ax
+ */
+
+        .macro  __loopt ar, as, at, incr_log2
+
+#if XCHAL_HAVE_LOOPS
+                sub     \at, \as, \ar
+                .ifgt   \incr_log2 - 1
+                        addi    \at, \at, (1 << \incr_log2) - 1
+                        srli    \at, \at, \incr_log2
+                .endif
+                loop    \at, 99f
+#else
+                98:
+#endif
+
+        .endm
+
+/*
+ * restart loop. registers must be unchanged
+ */
+
+        .macro  __loop  as
+
+#if XCHAL_HAVE_LOOPS
+                loop    \as, 99f
+#else
+                98:
+#endif
+
+        .endm
+
+/*
+ * end of loop with no increment of the address.
+ */
+
+        .macro  __endl  ar, as
+#if !XCHAL_HAVE_LOOPS
+                bltu    \ar, \as, 98b
+#endif
+                99:
+        .endm
+
+/*
+ * end of loop with increment of the address.
+ */
+
+        .macro  __endla ar, as, incr
+                addi    \ar, \ar, \incr
+                __endl  \ar \as
+        .endm
+
+
+#endif /* _XTENSA_ASMMACRO_H */
diff --git a/include/asm-xtensa/bug.h b/include/asm-xtensa/bug.h
index 56703659b204..3e52d72712f1 100644
--- a/include/asm-xtensa/bug.h
+++ b/include/asm-xtensa/bug.h
@@ -13,29 +13,6 @@
 #ifndef _XTENSA_BUG_H
 #define _XTENSA_BUG_H
 
-#include <linux/stringify.h>
-
-#define ILL     __asm__ __volatile__ (".byte 0,0,0\n")
-
-#ifdef CONFIG_KALLSYMS
-# define BUG() do {                                                     \
-        printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__);           \
-        ILL;                                                            \
-} while (0)
-#else
-# define BUG() do {                                                     \
-        printk("kernel BUG!\n");                                        \
-        ILL;                                                            \
-} while (0)
-#endif
-
-#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
-#define PAGE_BUG(page) do {  BUG(); } while (0)
-#define WARN_ON(condition) do {                                            \
-  if (unlikely((condition)!=0)) {                                          \
-    printk ("Warning in %s at %s:%d\n", __FUNCTION__, __FILE__, __LINE__); \
-      dump_stack();                                                        \
-  }                                                                        \
-} while (0)
+#include <asm-generic/bug.h>
 
 #endif  /* _XTENSA_BUG_H */
diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h
index 0b1552569aae..0f540a5f4c01 100644
--- a/include/asm-xtensa/byteorder.h
+++ b/include/asm-xtensa/byteorder.h
@@ -11,10 +11,9 @@
 #ifndef _XTENSA_BYTEORDER_H
 #define _XTENSA_BYTEORDER_H
 
-#include <asm/processor.h>
 #include <asm/types.h>
 
-static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
 {
     __u32 res;
     /* instruction sequence from Xtensa ISA release 2/2000 */
@@ -29,7 +28,7 @@ static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
     return res;
 }
 
-static __inline__ __const__ __u16 ___arch__swab16(__u16 x)
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
 {
     /* Given that 'short' values are signed (i.e., can be negative),
      * we cannot assume that the upper 16-bits of the register are
diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h
index 1e79c0e27460..1c4a78f29ae2 100644
--- a/include/asm-xtensa/cache.h
+++ b/include/asm-xtensa/cache.h
@@ -4,7 +4,6 @@
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
- * 2 of the License, or (at your option) any later version.
  *
  * (C) 2001 - 2005 Tensilica Inc.
  */
@@ -12,21 +11,14 @@
 #ifndef _XTENSA_CACHE_H
 #define _XTENSA_CACHE_H
 
-#include <xtensa/config/core.h>
+#include <asm/variant/core.h>
 
-#if XCHAL_ICACHE_SIZE > 0
-# if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0
-#  error cache configuration outside expected/supported range!
-# endif
-#endif
+#define L1_CACHE_SHIFT  XCHAL_DCACHE_LINEWIDTH
+#define L1_CACHE_BYTES  XCHAL_DCACHE_LINESIZE
+#define SMP_CACHE_BYTES L1_CACHE_BYTES
 
-#if XCHAL_DCACHE_SIZE > 0
-# if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0
-#  error cache configuration outside expected/supported range!
-# endif
-#endif
+#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
+#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
 
-#define L1_CACHE_SHIFT          XCHAL_CACHE_LINEWIDTH_MAX
-#define L1_CACHE_BYTES          XCHAL_CACHE_LINESIZE_MAX
 
 #endif  /* _XTENSA_CACHE_H */
diff --git a/include/asm-xtensa/cacheasm.h b/include/asm-xtensa/cacheasm.h
new file mode 100644
index 000000000000..2c20a58f94cd
--- /dev/null
+++ b/include/asm-xtensa/cacheasm.h
@@ -0,0 +1,177 @@
+/*
+ * include/asm-xtensa/cacheasm.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Tensilica Inc.
+ */
+
+#include <asm/cache.h>
+#include <asm/asmmacro.h>
+#include <linux/stringify.h>
+
+/*
+ * Define cache functions as macros here so that they can be used
+ * by the kernel and boot loader. We should consider moving them to a
+ * library that can be linked by both.
+ *
+ * Locking
+ *
+ *   ___unlock_dcache_all
+ *   ___unlock_icache_all
+ *
+ * Flush and invaldating
+ *
+ *   ___flush_invalidate_dcache_{all|range|page}
+ *   ___flush_dcache_{all|range|page}
+ *   ___invalidate_dcache_{all|range|page}
+ *   ___invalidate_icache_{all|range|page}
+ *
+ */
+
+        .macro  __loop_cache_all ar at insn size line_width
+
+        movi    \ar, 0
+
+        __loopi \ar, \at, \size, (4 << (\line_width))
+        \insn   \ar, 0 << (\line_width)
+        \insn   \ar, 1 << (\line_width)
+        \insn   \ar, 2 << (\line_width)
+        \insn   \ar, 3 << (\line_width)
+        __endla \ar, \at, 4 << (\line_width)
+
+        .endm
+
+
+        .macro  __loop_cache_range ar as at insn line_width
+
+        extui   \at, \ar, 0, \line_width
+        add     \as, \as, \at
+
+        __loops \ar, \as, \at, \line_width
+        \insn   \ar, 0
+        __endla \ar, \at, (1 << (\line_width))
+
+        .endm
+
+
+        .macro  __loop_cache_page ar at insn line_width
+
+        __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
+        \insn   \ar, 0 << (\line_width)
+        \insn   \ar, 1 << (\line_width)
+        \insn   \ar, 2 << (\line_width)
+        \insn   \ar, 3 << (\line_width)
+        __endla \ar, \at, 4 << (\line_width)
+
+        .endm
+
+
+#if XCHAL_DCACHE_LINE_LOCKABLE
+
+        .macro  ___unlock_dcache_all ar at
+
+        __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+#endif
+
+#if XCHAL_ICACHE_LINE_LOCKABLE
+
+        .macro  ___unlock_icache_all ar at
+
+        __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
+
+        .endm
+#endif
+
+        .macro  ___flush_invalidate_dcache_all ar at
+
+        __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro  ___flush_dcache_all ar at
+
+        __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro  ___invalidate_dcache_all ar at
+
+        __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
+                         XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro  ___invalidate_icache_all ar at
+
+        __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
+                         XCHAL_ICACHE_LINEWIDTH
+
+        .endm
+
+
+
+        .macro  ___flush_invalidate_dcache_range ar as at
+
+        __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro  ___flush_dcache_range ar as at
+
+        __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro  ___invalidate_dcache_range ar as at
+
+        __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro  ___invalidate_icache_range ar as at
+
+        __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
+
+        .endm
+
+
+
+        .macro  ___flush_invalidate_dcache_page ar as
+
+        __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro ___flush_dcache_page ar as
+
+        __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro  ___invalidate_dcache_page ar as
+
+        __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
+
+        .endm
+
+
+        .macro  ___invalidate_icache_page ar as
+
+        __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
+
+        .endm
+
diff --git a/include/asm-xtensa/cacheflush.h b/include/asm-xtensa/cacheflush.h
index 44a36e087844..337765b629de 100644
--- a/include/asm-xtensa/cacheflush.h
+++ b/include/asm-xtensa/cacheflush.h
@@ -5,7 +5,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * (C) 2001 - 2005 Tensilica Inc.
+ * (C) 2001 - 2006 Tensilica Inc.
  */
 
 #ifndef _XTENSA_CACHEFLUSH_H
diff --git a/include/asm-xtensa/checksum.h b/include/asm-xtensa/checksum.h
index 5435aff9a4b7..23534c60b3a4 100644
--- a/include/asm-xtensa/checksum.h
+++ b/include/asm-xtensa/checksum.h
@@ -12,7 +12,7 @@
 #define _XTENSA_CHECKSUM_H
 
 #include <linux/in6.h>
-#include <xtensa/config/core.h>
+#include <asm/variant/core.h>
 
 /*
  * computes the checksum of a memory block at buff, length len,
diff --git a/include/asm-xtensa/coprocessor.h b/include/asm-xtensa/coprocessor.h
index 5093034723be..bd09ec02d57f 100644
--- a/include/asm-xtensa/coprocessor.h
+++ b/include/asm-xtensa/coprocessor.h
@@ -11,7 +11,16 @@
 #ifndef _XTENSA_COPROCESSOR_H
 #define _XTENSA_COPROCESSOR_H
 
-#include <xtensa/config/core.h>
+#include <asm/variant/core.h>
+#include <asm/variant/tie.h>
+
+#if !XCHAL_HAVE_CP
+
+#define XTENSA_CP_EXTRA_OFFSET  0
+#define XTENSA_CP_EXTRA_ALIGN   1       /* must be a power of 2 */
+#define XTENSA_CP_EXTRA_SIZE    0
+
+#else
 
 #define XTOFS(last_start,last_size,align) \
         ((last_start+last_size+align-1) & -align)
@@ -67,4 +76,6 @@ extern void save_coprocessor_registers(void*, int);
 # endif
 #endif
 
+#endif
+
 #endif  /* _XTENSA_COPROCESSOR_H */
diff --git a/include/asm-xtensa/dma.h b/include/asm-xtensa/dma.h
index db2633f67789..e30f3abf48f0 100644
--- a/include/asm-xtensa/dma.h
+++ b/include/asm-xtensa/dma.h
@@ -12,7 +12,6 @@
 #define _XTENSA_DMA_H
 
 #include <asm/io.h>             /* need byte IO */
-#include <xtensa/config/core.h>
 
 /*
  * This is only to be defined if we have PC-like DMA.
@@ -44,7 +43,9 @@
  *      enters another area, and virt_to_phys() may not return
  *      the value desired).
  */
-#define MAX_DMA_ADDRESS         (PAGE_OFFSET + XCHAL_KSEG_CACHED_SIZE - 1)
+
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
+
 
 /* Reserve and release a DMA channel */
 extern int request_dma(unsigned int dmanr, const char * device_id);
diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h
index de0667453b2e..f0f9fd8560a5 100644
--- a/include/asm-xtensa/elf.h
+++ b/include/asm-xtensa/elf.h
@@ -13,9 +13,8 @@
 #ifndef _XTENSA_ELF_H
 #define _XTENSA_ELF_H
 
+#include <asm/variant/core.h>
 #include <asm/ptrace.h>
-#include <asm/coprocessor.h>
-#include <xtensa/config/core.h>
 
 /* Xtensa processor ELF architecture-magic number */
 
@@ -118,11 +117,15 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
  * using memcpy().  But we do allow space for such alignment,
  * to allow optimizations of layout and copying.
  */
-
+#if 0
 #define TOTAL_FPREGS_SIZE                                               \
         (4 + XTENSA_CPE_LTABLE_SIZE + XTENSA_CP_EXTRA_SIZE)
 #define ELF_NFPREG                                                      \
         ((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t))
+#else
+#define TOTAL_FPREGS_SIZE       0
+#define ELF_NFPREG              0
+#endif
 
 typedef unsigned int elf_fpreg_t;
 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
diff --git a/include/asm-xtensa/fcntl.h b/include/asm-xtensa/fcntl.h
index ec066ae96caf..0609fc691b72 100644
--- a/include/asm-xtensa/fcntl.h
+++ b/include/asm-xtensa/fcntl.h
@@ -14,48 +14,86 @@
 
 /* open/fcntl - O_SYNC is only implemented on blocks devices and on files
    located on an ext2 file system */
-#define O_APPEND        0x0008
-#define O_SYNC          0x0010
-#define O_NONBLOCK      0x0080
-#define O_CREAT         0x0100  /* not fcntl */
-#define O_EXCL          0x0400  /* not fcntl */
-#define O_NOCTTY        0x0800  /* not fcntl */
-#define FASYNC          0x1000  /* fcntl, for BSD compatibility */
-#define O_LARGEFILE     0x2000  /* allow large file opens - currently ignored */
-#define O_DIRECT        0x8000  /* direct disk access hint - currently ignored*/
-#define O_NOATIME       0x100000
-
-#define F_GETLK         14
-#define F_GETLK64       15
+#define O_ACCMODE          0003
+#define O_RDONLY             00
+#define O_WRONLY             01
+#define O_RDWR               02
+#define O_CREAT            0100 /* not fcntl */
+#define O_EXCL             0200 /* not fcntl */
+#define O_NOCTTY           0400 /* not fcntl */
+#define O_TRUNC           01000 /* not fcntl */
+#define O_APPEND          02000
+#define O_NONBLOCK        04000
+#define O_NDELAY        O_NONBLOCK
+#define O_SYNC           010000
+#define FASYNC           020000 /* fcntl, for BSD compatibility */
+#define O_DIRECT         040000 /* direct disk access hint */
+#define O_LARGEFILE     0100000
+#define O_DIRECTORY     0200000 /* must be a directory */
+#define O_NOFOLLOW      0400000 /* don't follow links */
+#define O_NOATIME       01000000
+
+#define F_DUPFD         0       /* dup */
+#define F_GETFD         1       /* get close_on_exec */
+#define F_SETFD         2       /* set/clear close_on_exec */
+#define F_GETFL         3       /* get file->f_flags */
+#define F_SETFL         4       /* set file->f_flags */
+#define F_GETLK         5
 #define F_SETLK         6
 #define F_SETLKW        7
-#define F_SETLK64       16
-#define F_SETLKW64      17
 
-#define F_SETOWN        24      /*  for sockets. */
-#define F_GETOWN        23      /*  for sockets. */
+#define F_SETOWN        8       /*  for sockets. */
+#define F_GETOWN        9       /*  for sockets. */
+#define F_SETSIG        10      /*  for sockets. */
+#define F_GETSIG        11      /*  for sockets. */
+
+#define F_GETLK64       12      /*  using 'struct flock64' */
+#define F_SETLK64       13
+#define F_SETLKW64      14
+
+/* for F_[GET|SET]FL */
+#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
+
+/* for posix fcntl() and lockf() */
+#define F_RDLCK         0
+#define F_WRLCK         1
+#define F_UNLCK         2
+
+/* for old implementation of bsd flock () */
+#define F_EXLCK         4       /* or 3 */
+#define F_SHLCK         8       /* or 4 */
 
-typedef struct flock {
+/* for leases */
+#define F_INPROGRESS    16
+
+/* operations for bsd flock(), also used by the kernel implementation */
+#define LOCK_SH         1       /* shared lock */
+#define LOCK_EX         2       /* exclusive lock */
+#define LOCK_NB         4       /* or'd with one of the above to prevent
+                                   blocking */
+#define LOCK_UN         8       /* remove lock */
+
+#define LOCK_MAND       32      /* This is a mandatory flock */
+#define LOCK_READ       64      /* ... Which allows concurrent read operations */
+#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
+#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
+
+struct flock {
         short l_type;
         short l_whence;
-        __kernel_off_t l_start;
-        __kernel_off_t l_len;
-        long  l_sysid;
-        __kernel_pid_t l_pid;
-        long  pad[4];
-} flock_t;
+        off_t l_start;
+        off_t l_len;
+        pid_t l_pid;
+};
 
 struct flock64 {
         short  l_type;
         short  l_whence;
-        __kernel_off_t l_start;
-        __kernel_off_t l_len;
+        loff_t l_start;
+        loff_t l_len;
         pid_t  l_pid;
 };
 
-#define HAVE_ARCH_STRUCT_FLOCK
-#define HAVE_ARCH_STRUCT_FLOCK64
-
-#include <asm-generic/fcntl.h>
+#define F_LINUX_SPECIFIC_BASE   1024
 
 #endif /* _XTENSA_FCNTL_H */
diff --git a/include/asm-xtensa/fixmap.h b/include/asm-xtensa/fixmap.h
deleted file mode 100644
index 4423b8ad4954..000000000000
--- a/include/asm-xtensa/fixmap.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * include/asm-xtensa/fixmap.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
- */
-
-#ifndef _XTENSA_FIXMAP_H
-#define _XTENSA_FIXMAP_H
-
-#include <asm/processor.h>
-
-#ifdef CONFIG_MMU
-
-/*
- * Here we define all the compile-time virtual addresses.
- */
-
-#if XCHAL_SEG_MAPPABLE_VADDR != 0
-# error "Current port requires virtual user space starting at 0"
-#endif
-#if XCHAL_SEG_MAPPABLE_SIZE < 0x80000000
-# error "Current port requires at least 0x8000000 bytes for user space"
-#endif
-
-/* Verify instruction/data ram/rom and xlmi don't overlay vmalloc space. */
-
-#define __IN_VMALLOC(addr)                                              \
-        (((addr) >= VMALLOC_START) && ((addr) < VMALLOC_END))
-#define __SPAN_VMALLOC(start,end)                                       \
-        (((start) < VMALLOC_START) && ((end) >= VMALLOC_END))
-#define INSIDE_VMALLOC(start,end)                                       \
-        (__IN_VMALLOC((start)) || __IN_VMALLOC(end) || __SPAN_VMALLOC((start),(end)))
-
-#if XCHAL_NUM_INSTROM
-# if XCHAL_NUM_INSTROM == 1
-#  if INSIDE_VMALLOC(XCHAL_INSTROM0_VADDR,XCHAL_INSTROM0_VADDR+XCHAL_INSTROM0_SIZE)
-#   error vmalloc range conflicts with instrom0
-#  endif
-# endif
-# if XCHAL_NUM_INSTROM == 2
-#  if INSIDE_VMALLOC(XCHAL_INSTROM1_VADDR,XCHAL_INSTROM1_VADDR+XCHAL_INSTROM1_SIZE)
-#   error vmalloc range conflicts with instrom1
-#  endif
-# endif
-#endif
-
-#if XCHAL_NUM_INSTRAM
-# if XCHAL_NUM_INSTRAM == 1
-#  if INSIDE_VMALLOC(XCHAL_INSTRAM0_VADDR,XCHAL_INSTRAM0_VADDR+XCHAL_INSTRAM0_SIZE)
-#   error vmalloc range conflicts with instram0
-#  endif
-# endif
-# if XCHAL_NUM_INSTRAM == 2
-#  if INSIDE_VMALLOC(XCHAL_INSTRAM1_VADDR,XCHAL_INSTRAM1_VADDR+XCHAL_INSTRAM1_SIZE)
-#   error vmalloc range conflicts with instram1
-#  endif
-# endif
-#endif
-
-#if XCHAL_NUM_DATAROM
-# if XCHAL_NUM_DATAROM == 1
-#  if INSIDE_VMALLOC(XCHAL_DATAROM0_VADDR,XCHAL_DATAROM0_VADDR+XCHAL_DATAROM0_SIZE)
-#   error vmalloc range conflicts with datarom0
-#  endif
-# endif
-# if XCHAL_NUM_DATAROM == 2
-#  if INSIDE_VMALLOC(XCHAL_DATAROM1_VADDR,XCHAL_DATAROM1_VADDR+XCHAL_DATAROM1_SIZE)
-#   error vmalloc range conflicts with datarom1
-#  endif
-# endif
-#endif
-
-#if XCHAL_NUM_DATARAM
-# if XCHAL_NUM_DATARAM == 1
-#  if INSIDE_VMALLOC(XCHAL_DATARAM0_VADDR,XCHAL_DATARAM0_VADDR+XCHAL_DATARAM0_SIZE)
-#   error vmalloc range conflicts with dataram0
-#  endif
-# endif
-# if XCHAL_NUM_DATARAM == 2
-#  if INSIDE_VMALLOC(XCHAL_DATARAM1_VADDR,XCHAL_DATARAM1_VADDR+XCHAL_DATARAM1_SIZE)
-#   error vmalloc range conflicts with dataram1
-#  endif
-# endif
-#endif
-
-#if XCHAL_NUM_XLMI
-# if XCHAL_NUM_XLMI == 1
-#  if INSIDE_VMALLOC(XCHAL_XLMI0_VADDR,XCHAL_XLMI0_VADDR+XCHAL_XLMI0_SIZE)
-#   error vmalloc range conflicts with xlmi0
-#  endif
-# endif
-# if XCHAL_NUM_XLMI == 2
-#  if INSIDE_VMALLOC(XCHAL_XLMI1_VADDR,XCHAL_XLMI1_VADDR+XCHAL_XLMI1_SIZE)
-#   error vmalloc range conflicts with xlmi1
-#  endif
-# endif
-#endif
-
-#if (XCHAL_NUM_INSTROM > 2) || \
-    (XCHAL_NUM_INSTRAM > 2) || \
-    (XCHAL_NUM_DATARAM > 2) || \
-    (XCHAL_NUM_DATAROM > 2) || \
-    (XCHAL_NUM_XLMI    > 2)
-# error Insufficient checks on vmalloc above for more than 2 devices
-#endif
-
-/*
- * USER_VM_SIZE does not necessarily equal TASK_SIZE.  We bumped
- * TASK_SIZE down to 0x4000000 to simplify the handling of windowed
- * call instructions (currently limited to a range of 1 GByte).  User
- * tasks may very well reclaim the VM space from 0x40000000 to
- * 0x7fffffff in the future, so we do not want the kernel becoming
- * accustomed to having any of its stuff (e.g., page tables) in this
- * region.  This VM region is no-man's land for now.
- */
-
-#define USER_VM_START           XCHAL_SEG_MAPPABLE_VADDR
-#define USER_VM_SIZE            0x80000000
-
-/*  Size of page table:  */
-
-#define PGTABLE_SIZE_BITS       (32 - XCHAL_MMU_MIN_PTE_PAGE_SIZE + 2)
-#define PGTABLE_SIZE            (1L << PGTABLE_SIZE_BITS)
-
-/*  All kernel-mappable space:  */
-
-#define KERNEL_ALLMAP_START     (USER_VM_START + USER_VM_SIZE)
-#define KERNEL_ALLMAP_SIZE      (XCHAL_SEG_MAPPABLE_SIZE - KERNEL_ALLMAP_START)
-
-/*  Carve out page table at start of kernel-mappable area:  */
-
-#if KERNEL_ALLMAP_SIZE < PGTABLE_SIZE
-#error "Gimme some space for page table!"
-#endif
-#define PGTABLE_START           KERNEL_ALLMAP_START
-
-/*  Remaining kernel-mappable space:  */
-
-#define KERNEL_MAPPED_START     (KERNEL_ALLMAP_START + PGTABLE_SIZE)
-#define KERNEL_MAPPED_SIZE      (KERNEL_ALLMAP_SIZE - PGTABLE_SIZE)
-
-#if KERNEL_MAPPED_SIZE < 0x01000000     /* 16 MB is arbitrary for now */
-# error "Shouldn't the kernel have at least *some* mappable space?"
-#endif
-
-#define MAX_LOW_MEMORY          XCHAL_KSEG_CACHED_SIZE
-
-#endif
-
-/*
- *  Some constants used elsewhere, but perhaps only in Xtensa header
- *  files, so maybe we can get rid of some and access compile-time HAL
- *  directly...
- *
- *  Note:  We assume that system RAM is located at the very start of the
- *         kernel segments !!
- */
-#define KERNEL_VM_LOW           XCHAL_KSEG_CACHED_VADDR
-#define KERNEL_VM_HIGH          XCHAL_KSEG_BYPASS_VADDR
-#define KERNEL_SPACE            XCHAL_KSEG_CACHED_VADDR
-
-/*
- * Returns the physical/virtual addresses of the kernel space
- * (works with the cached kernel segment only, which is the
- *  one normally used for kernel operation).
- */
-
-/*                      PHYSICAL        BYPASS          CACHED
- *
- *  bypass vaddr        bypass paddr    *               cached vaddr
- *  cached vaddr        cached paddr    bypass vaddr    *
- *  bypass paddr        *               bypass vaddr    cached vaddr
- *  cached paddr        *               bypass vaddr    cached vaddr
- *  other               *               *               *
- */
-
-#define PHYSADDR(a)                                                           \
-(((unsigned)(a) >= XCHAL_KSEG_BYPASS_VADDR                                    \
-  && (unsigned)(a) < XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_BYPASS_SIZE) ?      \
-    (unsigned)(a) - XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_BYPASS_PADDR :       \
-    ((unsigned)(a) >= XCHAL_KSEG_CACHED_VADDR                                 \
-     && (unsigned)(a) < XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_CACHED_SIZE) ?   \
-        (unsigned)(a) - XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_CACHED_PADDR :   \
-        (unsigned)(a))
-
-#define BYPASS_ADDR(a)                                                        \
-(((unsigned)(a) >= XCHAL_KSEG_BYPASS_PADDR                                    \
-  && (unsigned)(a) < XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_SIZE) ?      \
-    (unsigned)(a) - XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_VADDR :       \
-    ((unsigned)(a) >= XCHAL_KSEG_CACHED_PADDR                                 \
-     && (unsigned)(a) < XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_SIZE) ?   \
-        (unsigned)(a) - XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_BYPASS_VADDR :   \
-        ((unsigned)(a) >= XCHAL_KSEG_CACHED_VADDR                             \
-         && (unsigned)(a) < XCHAL_KSEG_CACHED_VADDR+XCHAL_KSEG_CACHED_SIZE)?  \
-            (unsigned)(a) - XCHAL_KSEG_CACHED_VADDR+XCHAL_KSEG_BYPASS_VADDR:  \
-            (unsigned)(a))
-
-#define CACHED_ADDR(a)                                                        \
-(((unsigned)(a) >= XCHAL_KSEG_BYPASS_PADDR                                    \
-  && (unsigned)(a) < XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_SIZE) ?      \
-    (unsigned)(a) - XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_CACHED_VADDR :       \
-    ((unsigned)(a) >= XCHAL_KSEG_CACHED_PADDR                                 \
-     && (unsigned)(a) < XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_SIZE) ?   \
-        (unsigned)(a) - XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_VADDR :   \
-        ((unsigned)(a) >= XCHAL_KSEG_BYPASS_VADDR                             \
-         && (unsigned)(a) < XCHAL_KSEG_BYPASS_VADDR+XCHAL_KSEG_BYPASS_SIZE) ? \
-            (unsigned)(a) - XCHAL_KSEG_BYPASS_VADDR+XCHAL_KSEG_CACHED_VADDR : \
-            (unsigned)(a))
-
-#define PHYSADDR_IO(a)                                                        \
-(((unsigned)(a) >= XCHAL_KIO_BYPASS_VADDR                                     \
-  && (unsigned)(a) < XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_SIZE) ?        \
-    (unsigned)(a) - XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_PADDR :         \
-    ((unsigned)(a) >= XCHAL_KIO_CACHED_VADDR                                  \
-     && (unsigned)(a) < XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_SIZE) ?     \
-        (unsigned)(a) - XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_PADDR :     \
-        (unsigned)(a))
-
-#define BYPASS_ADDR_IO(a)                                                     \
-(((unsigned)(a) >= XCHAL_KIO_BYPASS_PADDR                                     \
-  && (unsigned)(a) < XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_SIZE) ?        \
-    (unsigned)(a) - XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_VADDR :         \
-    ((unsigned)(a) >= XCHAL_KIO_CACHED_PADDR                                  \
-     && (unsigned)(a) < XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_SIZE) ?     \
-        (unsigned)(a) - XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_BYPASS_VADDR :     \
-        ((unsigned)(a) >= XCHAL_KIO_CACHED_VADDR                              \
-         && (unsigned)(a) < XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_SIZE) ? \
-            (unsigned)(a) - XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_BYPASS_VADDR : \
-            (unsigned)(a))
-
-#define CACHED_ADDR_IO(a)                                                     \
-(((unsigned)(a) >= XCHAL_KIO_BYPASS_PADDR                                     \
-  && (unsigned)(a) < XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_SIZE) ?        \
-    (unsigned)(a) - XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_CACHED_VADDR :         \
-    ((unsigned)(a) >= XCHAL_KIO_CACHED_PADDR                                  \
-     && (unsigned)(a) < XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_SIZE) ?     \
-        (unsigned)(a) - XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_VADDR :     \
-        ((unsigned)(a) >= XCHAL_KIO_BYPASS_VADDR                              \
-         && (unsigned)(a) < XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_SIZE) ? \
-            (unsigned)(a) - XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_CACHED_VADDR : \
-            (unsigned)(a))
-
-#endif /* _XTENSA_ADDRSPACE_H */
-
-
-
-
-
diff --git a/include/asm-xtensa/io.h b/include/asm-xtensa/io.h
index 556e5eed34f5..31ffc3f119c1 100644
--- a/include/asm-xtensa/io.h
+++ b/include/asm-xtensa/io.h
@@ -1,5 +1,5 @@
 /*
- * linux/include/asm-xtensa/io.h
+ * include/asm-xtensa/io.h
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -15,10 +15,11 @@
 #include <asm/byteorder.h>
 
 #include <linux/types.h>
-#include <asm/fixmap.h>
-
-#define _IO_BASE 0
 
+#define XCHAL_KIO_CACHED_VADDR  0xf0000000
+#define XCHAL_KIO_BYPASS_VADDR  0xf8000000
+#define XCHAL_KIO_PADDR         0xf0000000
+#define XCHAL_KIO_SIZE          0x08000000
 
 /*
  * swap functions to change byte order from little-endian to big-endian and
@@ -42,40 +43,43 @@ static inline unsigned int _swapl (unsigned int v)
 
 static inline unsigned long virt_to_phys(volatile void * address)
 {
-        return PHYSADDR((unsigned long)address);
+        return __pa(address);
 }
 
 static inline void * phys_to_virt(unsigned long address)
 {
-        return (void*) CACHED_ADDR(address);
+        return __va(address);
 }
 
 /*
- * IO bus memory addresses are also 1:1 with the physical address
+ * virt_to_bus and bus_to_virt are deprecated.
  */
 
-static inline unsigned long virt_to_bus(volatile void * address)
-{
-        return PHYSADDR((unsigned long)address);
-}
-
-static inline void * bus_to_virt (unsigned long address)
-{
-        return (void *) CACHED_ADDR(address);
-}
+#define virt_to_bus(x)  virt_to_phys(x)
+#define bus_to_virt(x)  phys_to_virt(x)
 
 /*
- * Change "struct page" to physical address.
+ * Return the virtual (cached) address for the specified bus memory.
+ * Note that we currently don't support any address outside the KIO segment.
  */
 
 static inline void *ioremap(unsigned long offset, unsigned long size)
 {
-        return (void *) CACHED_ADDR_IO(offset);
+        if (offset >= XCHAL_KIO_PADDR
+            && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE)
+                return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR);
+
+        else
+                BUG();
 }
 
 static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
 {
-        return (void *) BYPASS_ADDR_IO(offset);
+        if (offset >= XCHAL_KIO_PADDR
+            && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE)
+                return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR);
+        else
+                BUG();
 }
 
 static inline void iounmap(void *addr)
@@ -121,9 +125,6 @@ static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
           *(__force volatile __u32 *)(addr) = b;
 }
 
-
-
-
 /* These are the definitions for the x86 IO instructions
  * inb/inw/inl/outb/outw/outl, the "string" versions
  * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
@@ -131,11 +132,11 @@ static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
  * The macros don't do byte-swapping.
  */
 
-#define inb(port)               readb((u8 *)((port)+_IO_BASE))
-#define outb(val, port)         writeb((val),(u8 *)((unsigned long)(port)+_IO_BASE))
-#define inw(port)               readw((u16 *)((port)+_IO_BASE))
-#define outw(val, port)         writew((val),(u16 *)((unsigned long)(port)+_IO_BASE))
-#define inl(port)               readl((u32 *)((port)+_IO_BASE))
+#define inb(port)               readb((u8 *)((port)))
+#define outb(val, port)         writeb((val),(u8 *)((unsigned long)(port)))
+#define inw(port)               readw((u16 *)((port)))
+#define outw(val, port)         writew((val),(u16 *)((unsigned long)(port)))
+#define inl(port)               readl((u32 *)((port)))
 #define outl(val, port)         writel((val),(u32 *)((unsigned long)(port)))
 
 #define inb_p(port)             inb((port))
@@ -180,14 +181,13 @@ extern void outsl (unsigned long port, const void *src, unsigned long count);
 
 
 /*
- *  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- *   * access
- *    */
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem access
+ */
 #define xlate_dev_mem_ptr(p)    __va(p)
 
 /*
- *  * Convert a virtual cached pointer to an uncached pointer
- *   */
+ * Convert a virtual cached pointer to an uncached pointer
+ */
 #define xlate_dev_kmem_ptr(p)   p
 
 
diff --git a/include/asm-xtensa/irq.h b/include/asm-xtensa/irq.h
index 049fde7e752d..fc73b7f11aff 100644
--- a/include/asm-xtensa/irq.h
+++ b/include/asm-xtensa/irq.h
@@ -12,8 +12,7 @@
 #define _XTENSA_IRQ_H
 
 #include <asm/platform/hardware.h>
-
-#include <xtensa/config/core.h>
+#include <asm/variant/core.h>
 
 #ifndef PLATFORM_NR_IRQS
 # define PLATFORM_NR_IRQS 0
@@ -27,10 +26,5 @@ static __inline__ int irq_canonicalize(int irq)
 }
 
 struct irqaction;
-#if 0 // FIXME
-extern void disable_irq_nosync(unsigned int);
-extern void disable_irq(unsigned int);
-extern void enable_irq(unsigned int);
-#endif
 
 #endif  /* _XTENSA_IRQ_H */
diff --git a/include/asm-xtensa/irq_regs.h b/include/asm-xtensa/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/include/asm-xtensa/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/include/asm-xtensa/mmu_context.h b/include/asm-xtensa/mmu_context.h
index af683a74a4ec..f14851f086c3 100644
--- a/include/asm-xtensa/mmu_context.h
+++ b/include/asm-xtensa/mmu_context.h
@@ -16,187 +16,32 @@
 #include <linux/stringify.h>
 
 #include <asm/pgtable.h>
-#include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 
-/*
- * Linux was ported to Xtensa assuming all auto-refill ways in set 0
- * had the same properties (a very likely assumption).  Multiple sets
- * of auto-refill ways will still work properly, but not as optimally
- * as the Xtensa designer may have assumed.
- *
- * We make this case a hard #error, killing the kernel build, to alert
- * the developer to this condition (which is more likely an error).
- * You super-duper clever developers can change it to a warning or
- * remove it altogether if you think you know what you're doing.  :)
- */
+#define XCHAL_MMU_ASID_BITS     8
 
 #if (XCHAL_HAVE_TLBS != 1)
 # error "Linux must have an MMU!"
 #endif
 
-#if ((XCHAL_ITLB_ARF_WAYS == 0) || (XCHAL_DTLB_ARF_WAYS == 0))
-# error "MMU must have auto-refill ways"
-#endif
-
-#if ((XCHAL_ITLB_ARF_SETS != 1) || (XCHAL_DTLB_ARF_SETS != 1))
-# error Linux may not use all auto-refill ways as efficiently as you think
-#endif
-
-#if (XCHAL_MMU_MAX_PTE_PAGE_SIZE != XCHAL_MMU_MIN_PTE_PAGE_SIZE)
-# error Only one page size allowed!
-#endif
-
 extern unsigned long asid_cache;
-extern pgd_t *current_pgd;
-
-/*
- * Define the number of entries per auto-refill way in set 0 of both I and D
- * TLBs.  We deal only with set 0 here (an assumption further explained in
- * assertions.h).  Also, define the total number of ARF entries in both TLBs.
- */
-
-#define ITLB_ENTRIES_PER_ARF_WAY  (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES))
-#define DTLB_ENTRIES_PER_ARF_WAY  (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES))
-
-#define ITLB_ENTRIES                                                    \
-        (ITLB_ENTRIES_PER_ARF_WAY * (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,WAYS)))
-#define DTLB_ENTRIES                                                    \
-        (DTLB_ENTRIES_PER_ARF_WAY * (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,WAYS)))
-
-
-/*
- * SMALLEST_NTLB_ENTRIES is the smaller of ITLB_ENTRIES and DTLB_ENTRIES.
- * In practice, they are probably equal.  This macro simplifies function
- * flush_tlb_range().
- */
-
-#if (DTLB_ENTRIES < ITLB_ENTRIES)
-# define SMALLEST_NTLB_ENTRIES  DTLB_ENTRIES
-#else
-# define SMALLEST_NTLB_ENTRIES  ITLB_ENTRIES
-#endif
-
-
-/*
- * asid_cache tracks only the ASID[USER_RING] field of the RASID special
- * register, which is the current user-task asid allocation value.
- * mm->context has the same meaning.  When it comes time to write the
- * asid_cache or mm->context values to the RASID special register, we first
- * shift the value left by 8, then insert the value.
- * ASID[0] always contains the kernel's asid value, and we reserve three
- * other asid values that we never assign to user tasks.
- */
-
-#define ASID_INC        0x1
-#define ASID_MASK       ((1 << XCHAL_MMU_ASID_BITS) - 1)
-
-/*
- * XCHAL_MMU_ASID_INVALID is a configurable Xtensa processor constant
- * indicating invalid address space.  XCHAL_MMU_ASID_KERNEL is a configurable
- * Xtensa processor constant indicating the kernel address space.  They can
- * be arbitrary values.
- *
- * We identify three more unique, reserved ASID values to use in the unused
- * ring positions.  No other user process will be assigned these reserved
- * ASID values.
- *
- * For example, given that
- *
- *      XCHAL_MMU_ASID_INVALID == 0
- *      XCHAL_MMU_ASID_KERNEL  == 1
- *
- * the following maze of #if statements would generate
- *
- *      ASID_RESERVED_1        == 2
- *      ASID_RESERVED_2        == 3
- *      ASID_RESERVED_3        == 4
- *      ASID_FIRST_NONRESERVED == 5
- */
-
-#if (XCHAL_MMU_ASID_INVALID != XCHAL_MMU_ASID_KERNEL + 1)
-# define ASID_RESERVED_1         ((XCHAL_MMU_ASID_KERNEL + 1) & ASID_MASK)
-#else
-# define ASID_RESERVED_1         ((XCHAL_MMU_ASID_KERNEL + 2) & ASID_MASK)
-#endif
-
-#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_1 + 1)
-# define ASID_RESERVED_2         ((ASID_RESERVED_1 + 1) & ASID_MASK)
-#else
-# define ASID_RESERVED_2         ((ASID_RESERVED_1 + 2) & ASID_MASK)
-#endif
-
-#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_2 + 1)
-# define ASID_RESERVED_3         ((ASID_RESERVED_2 + 1) & ASID_MASK)
-#else
-# define ASID_RESERVED_3         ((ASID_RESERVED_2 + 2) & ASID_MASK)
-#endif
-
-#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_3 + 1)
-# define ASID_FIRST_NONRESERVED  ((ASID_RESERVED_3 + 1) & ASID_MASK)
-#else
-# define ASID_FIRST_NONRESERVED  ((ASID_RESERVED_3 + 2) & ASID_MASK)
-#endif
-
-#define ASID_ALL_RESERVED ( ((ASID_RESERVED_1) << 24) + \
-                            ((ASID_RESERVED_2) << 16) + \
-                            ((ASID_RESERVED_3) <<  8) + \
-                            ((XCHAL_MMU_ASID_KERNEL))   )
-
 
 /*
  * NO_CONTEXT is the invalid ASID value that we don't ever assign to
- * any user or kernel context.  NO_CONTEXT is a better mnemonic than
- * XCHAL_MMU_ASID_INVALID, so we use it in code instead.
- */
-
-#define NO_CONTEXT   XCHAL_MMU_ASID_INVALID
-
-#if (KERNEL_RING != 0)
-# error The KERNEL_RING really should be zero.
-#endif
-
-#if (USER_RING >= XCHAL_MMU_RINGS)
-# error USER_RING cannot be greater than the highest numbered ring.
-#endif
-
-#if (USER_RING == KERNEL_RING)
-# error The user and kernel rings really should not be equal.
-#endif
-
-#if (USER_RING == 1)
-#define ASID_INSERT(x) ( ((ASID_RESERVED_1)   << 24) + \
-                         ((ASID_RESERVED_2)   << 16) + \
-                         (((x) & (ASID_MASK)) <<  8) + \
-                         ((XCHAL_MMU_ASID_KERNEL))   )
-
-#elif (USER_RING == 2)
-#define ASID_INSERT(x) ( ((ASID_RESERVED_1)   << 24) + \
-                         (((x) & (ASID_MASK)) << 16) + \
-                         ((ASID_RESERVED_2)   <<  8) + \
-                         ((XCHAL_MMU_ASID_KERNEL))   )
-
-#elif (USER_RING == 3)
-#define ASID_INSERT(x) ( (((x) & (ASID_MASK)) << 24) + \
-                         ((ASID_RESERVED_1)   << 16) + \
-                         ((ASID_RESERVED_2)   <<  8) + \
-                         ((XCHAL_MMU_ASID_KERNEL))   )
-
-#else
-#error Goofy value for USER_RING
-
-#endif /* USER_RING == 1 */
-
-
-/*
- *  All unused by hardware upper bits will be considered
- *  as a software asid extension.
+ * any user or kernel context.
+ *
+ * 0 invalid
+ * 1 kernel
+ * 2 reserved
+ * 3 reserved
+ * 4...255 available
  */
 
-#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
-#define ASID_FIRST_VERSION                                              \
-        ((unsigned long)(~ASID_VERSION_MASK) + 1 + ASID_FIRST_NONRESERVED)
+#define NO_CONTEXT      0
+#define ASID_USER_FIRST 4
+#define ASID_MASK       ((1 << XCHAL_MMU_ASID_BITS) - 1)
+#define ASID_INSERT(x)  (0x03020001 | (((x) & ASID_MASK) << 8))
 
 static inline void set_rasid_register (unsigned long val)
 {
@@ -207,67 +52,28 @@ static inline void set_rasid_register (unsigned long val)
 static inline unsigned long get_rasid_register (void)
 {
         unsigned long tmp;
-        __asm__ __volatile__ (" rsr %0, "__stringify(RASID)"\n\t" : "=a" (tmp));
+        __asm__ __volatile__ (" rsr %0,"__stringify(RASID)"\n\t" : "=a" (tmp));
         return tmp;
 }
 
-
-#if ((XCHAL_MMU_ASID_INVALID == 0) && (XCHAL_MMU_ASID_KERNEL == 1))
-
 static inline void
-get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
+__get_new_mmu_context(struct mm_struct *mm)
 {
         extern void flush_tlb_all(void);
-        if (! ((asid += ASID_INC) & ASID_MASK) ) {
+        if (! (++asid_cache & ASID_MASK) ) {
                 flush_tlb_all(); /* start new asid cycle */
-                if (!asid)      /* fix version if needed */
-                        asid = ASID_FIRST_VERSION - ASID_FIRST_NONRESERVED;
-                asid += ASID_FIRST_NONRESERVED;
+                asid_cache += ASID_USER_FIRST;
         }
-        mm->context = asid_cache = asid;
-}
-
-#else
-#warning ASID_{INVALID,KERNEL} values impose non-optimal get_new_mmu_context implementation
-
-/* XCHAL_MMU_ASID_INVALID == 0 and XCHAL_MMU_ASID_KERNEL ==1 are
-   really the best, but if you insist... */
-
-static inline int validate_asid (unsigned long asid)
-{
-        switch (asid) {
-        case XCHAL_MMU_ASID_INVALID:
-        case XCHAL_MMU_ASID_KERNEL:
-        case ASID_RESERVED_1:
-        case ASID_RESERVED_2:
-        case ASID_RESERVED_3:
-                return 0; /* can't use these values as ASIDs */
-        }
-        return 1; /* valid */
+        mm->context = asid_cache;
 }
 
 static inline void
-get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
+__load_mmu_context(struct mm_struct *mm)
 {
-        extern void flush_tlb_all(void);
-        while (1) {
-                asid += ASID_INC;
-                if ( ! (asid & ASID_MASK) ) {
-                        flush_tlb_all(); /* start new asid cycle */
-                        if (!asid)      /* fix version if needed */
-                                asid = ASID_FIRST_VERSION - ASID_FIRST_NONRESERVED;
-                        asid += ASID_FIRST_NONRESERVED;
-                        break; /* no need to validate here */
-                }
-                if (validate_asid (asid & ASID_MASK))
-                        break;
-        }
-        mm->context = asid_cache = asid;
+        set_rasid_register(ASID_INSERT(mm->context));
+        invalidate_page_directory();
 }
 
-#endif
-
-
 /*
  * Initialize the context related info for a new mm_struct
  * instance.
@@ -280,6 +86,20 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
         return 0;
 }
 
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static inline void
+activate_mm(struct mm_struct *prev, struct mm_struct *next)
+{
+        /* Unconditionally get a new ASID.  */
+
+        __get_new_mmu_context(next);
+        __load_mmu_context(next);
+}
+
+
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                              struct task_struct *tsk)
 {
@@ -287,11 +107,10 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 
         /* Check if our ASID is of an older version and thus invalid */
 
-        if ((next->context ^ asid) & ASID_VERSION_MASK)
-                get_new_mmu_context(next, asid);
+        if (next->context == NO_CONTEXT || ((next->context^asid) & ~ASID_MASK))
+                __get_new_mmu_context(next);
 
-        set_rasid_register (ASID_INSERT(next->context));
-        invalidate_page_directory();
+        __load_mmu_context(next);
 }
 
 #define deactivate_mm(tsk, mm)  do { } while(0)
@@ -302,20 +121,6 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
  */
 static inline void destroy_context(struct mm_struct *mm)
 {
-        /* Nothing to do. */
-}
-
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-static inline void
-activate_mm(struct mm_struct *prev, struct mm_struct *next)
-{
-        /* Unconditionally get a new ASID.  */
-
-        get_new_mmu_context(next, asid_cache);
-        set_rasid_register (ASID_INSERT(next->context));
         invalidate_page_directory();
 }
 
diff --git a/include/asm-xtensa/page.h b/include/asm-xtensa/page.h
index 40f4c6c3f580..c631d006194b 100644
--- a/include/asm-xtensa/page.h
+++ b/include/asm-xtensa/page.h
@@ -15,18 +15,24 @@
 
 #include <asm/processor.h>
 
+#define XCHAL_KSEG_CACHED_VADDR 0xd0000000
+#define XCHAL_KSEG_BYPASS_VADDR 0xd8000000
+#define XCHAL_KSEG_PADDR        0x00000000
+#define XCHAL_KSEG_SIZE         0x08000000
+
 /*
  * PAGE_SHIFT determines the page size
  * PAGE_ALIGN(x) aligns the pointer to the (next) page boundary
  */
 
-#define PAGE_SHIFT              XCHAL_MMU_MIN_PTE_PAGE_SIZE
+#define PAGE_SHIFT              12
 #define PAGE_SIZE               (1 << PAGE_SHIFT)
 #define PAGE_MASK               (~(PAGE_SIZE-1))
 #define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE - 1) & PAGE_MASK)
 
-#define DCACHE_WAY_SIZE         (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
 #define PAGE_OFFSET             XCHAL_KSEG_CACHED_VADDR
+#define MAX_MEM_PFN             XCHAL_KSEG_SIZE
+#define PGTABLE_START           0x80000000
 
 #ifdef __ASSEMBLY__
 
diff --git a/include/asm-xtensa/param.h b/include/asm-xtensa/param.h
index c0eec8260b0e..6f281392e3f8 100644
--- a/include/asm-xtensa/param.h
+++ b/include/asm-xtensa/param.h
@@ -11,7 +11,7 @@
 #ifndef _XTENSA_PARAM_H
 #define _XTENSA_PARAM_H
 
-#include <xtensa/config/core.h>
+#include <asm/variant/core.h>
 
 #ifdef __KERNEL__
 # define HZ             100             /* internal timer frequency */
diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h
index b4318934b10d..2d4b5db6ea63 100644
--- a/include/asm-xtensa/pgtable.h
+++ b/include/asm-xtensa/pgtable.h
@@ -14,45 +14,6 @@
 #include <asm-generic/pgtable-nopmd.h>
 #include <asm/page.h>
 
-/* Assertions. */
-
-#ifdef CONFIG_MMU
-
-
-#if (XCHAL_MMU_RINGS < 2)
-# error Linux build assumes at least 2 ring levels.
-#endif
-
-#if (XCHAL_MMU_CA_BITS != 4)
-# error We assume exactly four bits for CA.
-#endif
-
-#if (XCHAL_MMU_SR_BITS != 0)
-# error We have no room for SR bits.
-#endif
-
-/*
- * Use the first min-wired way for mapping page-table pages.
- * Page coloring requires a second min-wired way.
- */
-
-#if (XCHAL_DTLB_MINWIRED_SETS == 0)
-# error Need a min-wired way for mapping page-table pages
-#endif
-
-#define DTLB_WAY_PGTABLE XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAY)
-
-#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
-# if XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAYS) >= 2
-#  define DTLB_WAY_DCACHE_ALIAS0 (DTLB_WAY_PGTABLE + 1)
-#  define DTLB_WAY_DCACHE_ALIAS1 (DTLB_WAY_PGTABLE + 2)
-# else
-#  error Page coloring requires its own wired dtlb way!
-# endif
-#endif
-
-#endif /* CONFIG_MMU */
-
 /*
  * We only use two ring levels, user and kernel space.
  */
@@ -97,7 +58,7 @@
 #define PGD_ORDER               0
 #define PMD_ORDER               0
 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
-#define FIRST_USER_ADDRESS      XCHAL_SEG_MAPPABLE_VADDR
+#define FIRST_USER_ADDRESS      0
 #define FIRST_USER_PGD_NR       (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
 
 /* virtual memory area. We keep a distance to other memory regions to be
diff --git a/include/asm-xtensa/platform-iss/hardware.h b/include/asm-xtensa/platform-iss/hardware.h
index 22240f001803..6930c12adc16 100644
--- a/include/asm-xtensa/platform-iss/hardware.h
+++ b/include/asm-xtensa/platform-iss/hardware.h
@@ -12,18 +12,18 @@
  * This file contains the default configuration of ISS.
  */
 
-#ifndef __ASM_XTENSA_ISS_HARDWARE
-#define __ASM_XTENSA_ISS_HARDWARE
+#ifndef _XTENSA_PLATFORM_ISS_HARDWARE_H
+#define _XTENSA_PLATFORM_ISS_HARDWARE_H
 
 /*
  * Memory configuration.
  */
 
-#define PLATFORM_DEFAULT_MEM_START XSHAL_RAM_PADDR
-#define PLATFORM_DEFAULT_MEM_SIZE XSHAL_RAM_VSIZE
+#define PLATFORM_DEFAULT_MEM_START      0x00000000
+#define PLATFORM_DEFAULT_MEM_SIZE       0x08000000
 
 /*
  * Interrupt configuration.
  */
 
-#endif /* __ASM_XTENSA_ISS_HARDWARE */
+#endif /* _XTENSA_PLATFORM_ISS_HARDWARE_H */
diff --git a/include/asm-xtensa/platform-iss/simcall.h b/include/asm-xtensa/platform-iss/simcall.h
new file mode 100644
index 000000000000..6acb572759a6
--- /dev/null
+++ b/include/asm-xtensa/platform-iss/simcall.h
@@ -0,0 +1,62 @@
+/*
+ * include/asm-xtensa/platform-iss/hardware.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PLATFORM_ISS_SIMCALL_H
+#define _XTENSA_PLATFORM_ISS_SIMCALL_H
+
+
+/*
+ *  System call like services offered by the simulator host.
+ */
+
+#define SYS_nop         0       /* unused */
+#define SYS_exit        1       /*x*/
+#define SYS_fork        2
+#define SYS_read        3       /*x*/
+#define SYS_write       4       /*x*/
+#define SYS_open        5       /*x*/
+#define SYS_close       6       /*x*/
+#define SYS_rename      7       /*x 38 - waitpid */
+#define SYS_creat       8       /*x*/
+#define SYS_link        9       /*x (not implemented on WIN32) */
+#define SYS_unlink      10      /*x*/
+#define SYS_execv       11      /* n/a - execve */
+#define SYS_execve      12      /* 11 - chdir */
+#define SYS_pipe        13      /* 42 - time */
+#define SYS_stat        14      /* 106 - mknod */
+#define SYS_chmod       15
+#define SYS_chown       16      /* 202 - lchown */
+#define SYS_utime       17      /* 30 - break */
+#define SYS_wait        18      /* n/a - oldstat */
+#define SYS_lseek       19      /*x*/
+#define SYS_getpid      20
+#define SYS_isatty      21      /* n/a - mount */
+#define SYS_fstat       22      /* 108 - oldumount */
+#define SYS_time        23      /* 13 - setuid */
+#define SYS_gettimeofday 24     /*x 78 - getuid (not implemented on WIN32) */
+#define SYS_times       25      /*X 43 - stime (Xtensa-specific implementation) */
+#define SYS_socket      26
+#define SYS_sendto      27
+#define SYS_recvfrom    28
+#define SYS_select_one  29      /* not compitible select, one file descriptor at the time */
+#define SYS_bind        30
+#define SYS_ioctl       31
+
+/*
+ * SYS_select_one specifiers
+ */
+
+#define  XTISS_SELECT_ONE_READ    1
+#define  XTISS_SELECT_ONE_WRITE   2
+#define  XTISS_SELECT_ONE_EXCEPT  3
+
+
+#endif /* _XTENSA_PLATFORM_ISS_SIMCALL_H */
+
diff --git a/include/asm-xtensa/posix_types.h b/include/asm-xtensa/posix_types.h
index 2c816b0e7762..3470b44c12ce 100644
--- a/include/asm-xtensa/posix_types.h
+++ b/include/asm-xtensa/posix_types.h
@@ -21,7 +21,7 @@
 
 typedef unsigned long   __kernel_ino_t;
 typedef unsigned int    __kernel_mode_t;
-typedef unsigned short  __kernel_nlink_t;
+typedef unsigned long   __kernel_nlink_t;
 typedef long            __kernel_off_t;
 typedef int             __kernel_pid_t;
 typedef unsigned short  __kernel_ipc_pid_t;
diff --git a/include/asm-xtensa/processor.h b/include/asm-xtensa/processor.h
index 8b96e77c9d82..4feb9f7f35a6 100644
--- a/include/asm-xtensa/processor.h
+++ b/include/asm-xtensa/processor.h
@@ -11,24 +11,18 @@
 #ifndef _XTENSA_PROCESSOR_H
 #define _XTENSA_PROCESSOR_H
 
-#ifdef __ASSEMBLY__
-#define _ASMLANGUAGE
-#endif
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/config/tie.h>
-#include <xtensa/config/system.h>
+#include <asm/variant/core.h>
+#include <asm/coprocessor.h>
 
 #include <linux/compiler.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
-#include <asm/coprocessor.h>
+#include <asm/regs.h>
 
 /* Assertions. */
 
 #if (XCHAL_HAVE_WINDOWED != 1)
-#error Linux requires the Xtensa Windowed Registers Option.
+# error Linux requires the Xtensa Windowed Registers Option.
 #endif
 
 /*
@@ -145,11 +139,11 @@ struct thread_struct {
  * Note: We set-up ps as if we did a call4 to the new pc.
  *       set_thread_state in signal.c depends on it.
  */
-#define USER_PS_VALUE ( (1 << XCHAL_PS_WOE_SHIFT) + \
-                        (1 << XCHAL_PS_CALLINC_SHIFT) + \
-                        (USER_RING << XCHAL_PS_RING_SHIFT) + \
-                        (1 << XCHAL_PS_PROGSTACK_SHIFT) + \
-                        (1 << XCHAL_PS_EXCM_SHIFT) )
+#define USER_PS_VALUE ((1 << PS_WOE_BIT) |                              \
+                       (1 << PS_CALLINC_SHIFT) |                        \
+                       (USER_RING << PS_RING_SHIFT) |                   \
+                       (1 << PS_UM_BIT) |                               \
+                       (1 << PS_EXCM_BIT))
 
 /* Clearing a0 terminates the backtrace. */
 #define start_thread(regs, new_pc, new_sp) \
diff --git a/include/asm-xtensa/ptrace.h b/include/asm-xtensa/ptrace.h
index a5ac71a5205c..1b7fe363fad1 100644
--- a/include/asm-xtensa/ptrace.h
+++ b/include/asm-xtensa/ptrace.h
@@ -11,7 +11,7 @@
 #ifndef _XTENSA_PTRACE_H
 #define _XTENSA_PTRACE_H
 
-#include <xtensa/config/core.h>
+#include <asm/variant/core.h>
 
 /*
  * Kernel stack
diff --git a/include/asm-xtensa/regs.h b/include/asm-xtensa/regs.h
new file mode 100644
index 000000000000..c913d259faaa
--- /dev/null
+++ b/include/asm-xtensa/regs.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2006 Tensilica, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2.1 of the GNU Lesser General Public
+ * License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Further, this software is distributed without any warranty that it is
+ * free of the rightful claim of any third person regarding infringement
+ * or the like.  Any license provided herein, whether implied or
+ * otherwise, applies only to this software file.  Patent licenses, if
+ * any, provided herein do not apply to combinations of this program with
+ * other software, or any other product whatsoever.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this program; if not, write the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
+ * USA.
+ */
+
+#ifndef _XTENSA_REGS_H
+#define _XTENSA_REGS_H
+
+/*  Special registers.  */
+
+#define LBEG            0
+#define LEND            1
+#define LCOUNT          2
+#define SAR             3
+#define BR              4
+#define SCOMPARE1       12
+#define ACCHI           16
+#define ACCLO           17
+#define MR              32
+#define WINDOWBASE      72
+#define WINDOWSTART     73
+#define PTEVADDR        83
+#define RASID           90
+#define ITLBCFG         91
+#define DTLBCFG         92
+#define IBREAKENABLE    96
+#define DDR             104
+#define IBREAKA         128
+#define DBREAKA         144
+#define DBREAKC         160
+#define EPC             176
+#define EPC_1           177
+#define DEPC            192
+#define EPS             192
+#define EPS_1           193
+#define EXCSAVE         208
+#define EXCSAVE_1       209
+#define INTERRUPT       226
+#define INTENABLE       228
+#define PS              230
+#define THREADPTR       231
+#define EXCCAUSE        232
+#define DEBUGCAUSE      233
+#define CCOUNT          234
+#define PRID            235
+#define ICOUNT          236
+#define ICOUNTLEVEL     237
+#define EXCVADDR        238
+#define CCOMPARE        240
+#define MISC            244
+
+/*  Special names for read-only and write-only interrupt registers.  */
+
+#define INTREAD         226
+#define INTSET          226
+#define INTCLEAR        227
+
+/*  EXCCAUSE register fields  */
+
+#define EXCCAUSE_EXCCAUSE_SHIFT 0
+#define EXCCAUSE_EXCCAUSE_MASK  0x3F
+
+#define EXCCAUSE_ILLEGAL_INSTRUCTION            0
+#define EXCCAUSE_SYSTEM_CALL                    1
+#define EXCCAUSE_INSTRUCTION_FETCH_ERROR        2
+#define EXCCAUSE_LOAD_STORE_ERROR               3
+#define EXCCAUSE_LEVEL1_INTERRUPT               4
+#define EXCCAUSE_ALLOCA                         5
+#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO         6
+#define EXCCAUSE_SPECULATION                    7
+#define EXCCAUSE_PRIVILEGED                     8
+#define EXCCAUSE_UNALIGNED                      9
+#define EXCCAUSE_ITLB_MISS                      16
+#define EXCCAUSE_ITLB_MULTIHIT                  17
+#define EXCCAUSE_ITLB_PRIVILEGE                 18
+#define EXCCAUSE_ITLB_SIZE_RESTRICTION          19
+#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE          20
+#define EXCCAUSE_DTLB_MISS                      24
+#define EXCCAUSE_DTLB_MULTIHIT                  25
+#define EXCCAUSE_DTLB_PRIVILEGE                 26
+#define EXCCAUSE_DTLB_SIZE_RESTRICTION          27
+#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE           28
+#define EXCCAUSE_STORE_CACHE_ATTRIBUTE          29
+#define EXCCAUSE_FLOATING_POINT                 40
+
+/*  PS register fields.  */
+
+#define PS_WOE_BIT              18
+#define PS_CALLINC_SHIFT        16
+#define PS_CALLINC_MASK         0x00030000
+#define PS_OWB_SHIFT            8
+#define PS_OWB_MASK             0x00000F00
+#define PS_RING_SHIFT           6
+#define PS_RING_MASK            0x000000C0
+#define PS_UM_BIT               5
+#define PS_EXCM_BIT             4
+#define PS_INTLEVEL_SHIFT       0
+#define PS_INTLEVEL_MASK        0x0000000F
+
+/*  DBREAKCn register fields.  */
+
+#define DBREAKC_MASK_BIT                0
+#define DBREAKC_MASK_MASK               0x0000003F
+#define DBREAKC_LOAD_BIT                30
+#define DBREAKC_LOAD_MASK               0x40000000
+#define DBREAKC_STOR_BIT                31
+#define DBREAKC_STOR_MASK               0x80000000
+
+/*  DEBUGCAUSE register fields.  */
+
+#define DEBUGCAUSE_DEBUGINT_BIT         5       /* External debug interrupt */
+#define DEBUGCAUSE_BREAKN_BIT           4       /* BREAK.N instruction */
+#define DEBUGCAUSE_BREAK_BIT            3       /* BREAK instruction */
+#define DEBUGCAUSE_DBREAK_BIT           2       /* DBREAK match */
+#define DEBUGCAUSE_IBREAK_BIT           1       /* IBREAK match */
+#define DEBUGCAUSE_ICOUNT_BIT           0       /* ICOUNT would incr. to zero */
+
+#endif /* _XTENSA_SPECREG_H */
+
diff --git a/include/asm-xtensa/sembuf.h b/include/asm-xtensa/sembuf.h
index 2d26c47666fe..c15870493b33 100644
--- a/include/asm-xtensa/sembuf.h
+++ b/include/asm-xtensa/sembuf.h
@@ -25,7 +25,7 @@
 
 struct semid64_ds {
         struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
-#if XCHAL_HAVE_LE
+#ifdef __XTENSA_EL__
         __kernel_time_t sem_otime;              /* last semop time */
         unsigned long   __unused1;
         __kernel_time_t sem_ctime;              /* last change time */
diff --git a/include/asm-xtensa/shmbuf.h b/include/asm-xtensa/shmbuf.h
index a30b81a4b933..ad4b0121782c 100644
--- a/include/asm-xtensa/shmbuf.h
+++ b/include/asm-xtensa/shmbuf.h
@@ -19,6 +19,7 @@
 #ifndef _XTENSA_SHMBUF_H
 #define _XTENSA_SHMBUF_H
 
+#if defined (__XTENSA_EL__)
 struct shmid64_ds {
         struct ipc64_perm       shm_perm;       /* operation perms */
         size_t                  shm_segsz;      /* size of segment (bytes) */
@@ -34,6 +35,26 @@ struct shmid64_ds {
         unsigned long           __unused4;
         unsigned long           __unused5;
 };
+#elif defined (__XTENSA_EB__)
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        unsigned long           __unused1;
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        unsigned long           __unused2;
+        __kernel_time_t         shm_ctime;      /* last change time */
+        unsigned long           __unused3;
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused4;
+        unsigned long           __unused5;
+};
+#else
+# error endian order not defined
+#endif
+
 
 struct shminfo64 {
         unsigned long   shmmax;
diff --git a/include/asm-xtensa/stat.h b/include/asm-xtensa/stat.h
index 2f4662ff6c3a..149f4bce092f 100644
--- a/include/asm-xtensa/stat.h
+++ b/include/asm-xtensa/stat.h
@@ -13,93 +13,57 @@
 
 #include <linux/types.h>
 
-struct __old_kernel_stat {
-        unsigned short st_dev;
-        unsigned short st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned short st_rdev;
-        unsigned long  st_size;
-        unsigned long  st_atime;
-        unsigned long  st_mtime;
-        unsigned long  st_ctime;
-};
-
 #define STAT_HAVE_NSEC 1
 
 struct stat {
-        unsigned short st_dev;
-        unsigned short __pad1;
-        unsigned long st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned short st_rdev;
-        unsigned short __pad2;
-        unsigned long  st_size;
-        unsigned long  st_blksize;
-        unsigned long  st_blocks;
-        unsigned long  st_atime;
-        unsigned long  st_atime_nsec;
-        unsigned long  st_mtime;
-        unsigned long  st_mtime_nsec;
-        unsigned long  st_ctime;
-        unsigned long  st_ctime_nsec;
-        unsigned long  __unused4;
-        unsigned long  __unused5;
+        unsigned long   st_dev;
+        ino_t           st_ino;
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+        uid_t           st_uid;
+        gid_t           st_gid;
+        unsigned int    st_rdev;
+        off_t           st_size;
+        unsigned long   st_blksize;
+        unsigned long   st_blocks;
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+        unsigned long   __unused4;
+        unsigned long   __unused5;
 };
 
-/* This matches struct stat64 in glibc-2.2.3. */
+/* This matches struct stat64 in glibc-2.3 */
 
 struct stat64  {
-#ifdef __XTENSA_EL__
-        unsigned short  st_dev;         /* Device */
-        unsigned char   __pad0[10];
-#else
-        unsigned char   __pad0[6];
-        unsigned short  st_dev;
-        unsigned char   __pad1[2];
-#endif
-
-#define STAT64_HAS_BROKEN_ST_INO        1
-        unsigned long __st_ino;         /* 32bit file serial number. */
-
+        unsigned long long st_dev;      /* Device */
+        unsigned long long st_ino;      /* File serial number */
         unsigned int  st_mode;          /* File mode. */
         unsigned int  st_nlink;         /* Link count. */
         unsigned int  st_uid;           /* User ID of the file's owner. */
         unsigned int  st_gid;           /* Group ID of the file's group. */
-
-#ifdef __XTENSA_EL__
-        unsigned short  st_rdev;        /* Device number, if device. */
-        unsigned char   __pad3[10];
-#else
-        unsigned char   __pad2[6];
-        unsigned short  st_rdev;
-        unsigned char   __pad3[2];
-#endif
-
-        long long int  st_size;         /* Size of file, in bytes. */
-        long int st_blksize;            /* Optimal block size for I/O. */
-
-#ifdef __XTENSA_EL__
-        unsigned long  st_blocks;       /* Number 512-byte blocks allocated. */
-        unsigned long  __pad4;
+        unsigned long long st_rdev;     /* Device number, if device. */
+        long long st_size;              /* Size of file, in bytes. */
+        long st_blksize;                /* Optimal block size for I/O. */
+        unsigned long __unused2;
+#ifdef __XTENSA_EB__
+        unsigned long __unused3;
+        long st_blocks;                 /* Number 512-byte blocks allocated. */
 #else
-        unsigned long  __pad4;
-        unsigned long  st_blocks;
+        long st_blocks;                 /* Number 512-byte blocks allocated. */
+        unsigned long __unused3;
 #endif
-
-        unsigned long  __pad5;
-        long int st_atime;              /* Time of last access. */
-        unsigned long  st_atime_nsec;
-        long int st_mtime;              /* Time of last modification. */
-        unsigned long  st_mtime_nsec;
-        long int  st_ctime;             /* Time of last status change. */
-        unsigned long  st_ctime_nsec;
-        unsigned long long int st_ino;  /* File serial number. */
+        long st_atime;                  /* Time of last access. */
+        unsigned long st_atime_nsec;
+        long st_mtime;                  /* Time of last modification. */
+        unsigned long st_mtime_nsec;
+        long st_ctime;                  /* Time of last status change. */
+        unsigned long st_ctime_nsec;
+        unsigned long __unused4;
+        unsigned long __unused5;
 };
 
 #endif  /* _XTENSA_STAT_H */
diff --git a/include/asm-xtensa/syscall.h b/include/asm-xtensa/syscall.h
new file mode 100644
index 000000000000..6cb0d42f11c8
--- /dev/null
+++ b/include/asm-xtensa/syscall.h
@@ -0,0 +1,20 @@
+struct pt_regs;
+struct sigaction;
+asmlinkage long xtensa_execve(char*, char**, char**, struct pt_regs*);
+asmlinkage long xtensa_clone(unsigned long, unsigned long, struct pt_regs*);
+asmlinkage long xtensa_pipe(int __user *);
+asmlinkage long xtensa_mmap2(unsigned long, unsigned long, unsigned long,
+                             unsigned long, unsigned long, unsigned long);
+asmlinkage long xtensa_ptrace(long, long, long, long);
+asmlinkage long xtensa_sigreturn(struct pt_regs*);
+asmlinkage long xtensa_rt_sigreturn(struct pt_regs*);
+asmlinkage long xtensa_sigsuspend(struct pt_regs*);
+asmlinkage long xtensa_rt_sigsuspend(struct pt_regs*);
+asmlinkage long xtensa_sigaction(int, const struct old_sigaction*,
+                                 struct old_sigaction*);
+asmlinkage long xtensa_sigaltstack(struct pt_regs *regs);
+asmlinkage long sys_rt_sigaction(int,
+                                 const struct sigaction __user *,
+                                 struct sigaction __user *,
+                                 size_t);
+asmlinkage long xtensa_shmat(int shmid, char __user *shmaddr, int shmflg);
diff --git a/include/asm-xtensa/system.h b/include/asm-xtensa/system.h
index 932bda92a21c..4aaed7fe6cfe 100644
--- a/include/asm-xtensa/system.h
+++ b/include/asm-xtensa/system.h
@@ -213,7 +213,7 @@ static inline void spill_registers(void)
         unsigned int a0, ps;
 
         __asm__ __volatile__ (
-                "movi   a14," __stringify (PS_EXCM_MASK) " | 1\n\t"
+                "movi   a14," __stringify (PS_EXCM_BIT) " | 1\n\t"
                 "mov    a12, a0\n\t"
                 "rsr    a13," __stringify(SAR) "\n\t"
                 "xsr    a14," __stringify(PS) "\n\t"
diff --git a/include/asm-xtensa/timex.h b/include/asm-xtensa/timex.h
index c7b705e66655..28c7985a4000 100644
--- a/include/asm-xtensa/timex.h
+++ b/include/asm-xtensa/timex.h
@@ -16,17 +16,22 @@
 #include <asm/processor.h>
 #include <linux/stringify.h>
 
-#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
+#define _INTLEVEL(x)    XCHAL_INT ## x ## _LEVEL
+#define INTLEVEL(x)     _INTLEVEL(x)
+
+#if INTLEVEL(XCHAL_TIMER0_INTERRUPT) == 1
 # define LINUX_TIMER     0
-#elif XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
+# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
+#elif INTLEVEL(XCHAL_TIMER1_INTERRUPT) == 1
 # define LINUX_TIMER     1
-#elif XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
+# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
+#elif INTLEVEL(XCHAL_TIMER2_INTERRUPT) == 1
 # define LINUX_TIMER     2
+# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
 #else
 # error "Bad timer number for Linux configurations!"
 #endif
 
-#define LINUX_TIMER_INT         XCHAL_TIMER_INTERRUPT(LINUX_TIMER)
 #define LINUX_TIMER_MASK        (1L << LINUX_TIMER_INT)
 
 #define CLOCK_TICK_RATE         1193180 /* (everyone is using this value) */
@@ -60,8 +65,8 @@ extern cycles_t cacheflush_time;
 
 #define WSR_CCOUNT(r)     __asm__("wsr %0,"__stringify(CCOUNT) :: "a" (r))
 #define RSR_CCOUNT(r)     __asm__("rsr %0,"__stringify(CCOUNT) : "=a" (r))
-#define WSR_CCOMPARE(x,r) __asm__("wsr %0,"__stringify(CCOMPARE_0)"+"__stringify(x) :: "a"(r))
-#define RSR_CCOMPARE(x,r) __asm__("rsr %0,"__stringify(CCOMPARE_0)"+"__stringify(x) : "=a"(r))
+#define WSR_CCOMPARE(x,r) __asm__("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))
+#define RSR_CCOMPARE(x,r) __asm__("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))
 
 static inline unsigned long get_ccount (void)
 {
diff --git a/include/asm-xtensa/tlbflush.h b/include/asm-xtensa/tlbflush.h
index 43f6ec859af9..7c637b3c352c 100644
--- a/include/asm-xtensa/tlbflush.h
+++ b/include/asm-xtensa/tlbflush.h
@@ -11,12 +11,20 @@
 #ifndef _XTENSA_TLBFLUSH_H
 #define _XTENSA_TLBFLUSH_H
 
-#define DEBUG_TLB
-
 #ifdef __KERNEL__
 
-#include <asm/processor.h>
 #include <linux/stringify.h>
+#include <asm/processor.h>
+
+#define DTLB_WAY_PGD    7
+
+#define ITLB_ARF_WAYS   4
+#define DTLB_ARF_WAYS   4
+
+#define ITLB_HIT_BIT    3
+#define DTLB_HIT_BIT    4
+
+#ifndef __ASSEMBLY__
 
 /* TLB flushing:
  *
@@ -46,11 +54,6 @@ static inline void flush_tlb_pgtables(struct mm_struct *mm,
 
 /* TLB operations. */
 
-#define ITLB_WAYS_LOG2      XCHAL_ITLB_WAY_BITS
-#define DTLB_WAYS_LOG2      XCHAL_DTLB_WAY_BITS
-#define ITLB_PROBE_SUCCESS  (1 << ITLB_WAYS_LOG2)
-#define DTLB_PROBE_SUCCESS  (1 << DTLB_WAYS_LOG2)
-
 static inline unsigned long itlb_probe(unsigned long addr)
 {
         unsigned long tmp;
@@ -131,29 +134,30 @@ static inline void write_itlb_entry (pte_t entry, int way)
 
 static inline void invalidate_page_directory (void)
 {
-        invalidate_dtlb_entry (DTLB_WAY_PGTABLE);
+        invalidate_dtlb_entry (DTLB_WAY_PGD);
+        invalidate_dtlb_entry (DTLB_WAY_PGD+1);
+        invalidate_dtlb_entry (DTLB_WAY_PGD+2);
 }
 
 static inline void invalidate_itlb_mapping (unsigned address)
 {
         unsigned long tlb_entry;
-        while ((tlb_entry = itlb_probe (address)) & ITLB_PROBE_SUCCESS)
-                invalidate_itlb_entry (tlb_entry);
+        if (((tlb_entry = itlb_probe(address)) & (1 << ITLB_HIT_BIT)) != 0)
+                invalidate_itlb_entry(tlb_entry);
 }
 
 static inline void invalidate_dtlb_mapping (unsigned address)
 {
         unsigned long tlb_entry;
-        while ((tlb_entry = dtlb_probe (address)) & DTLB_PROBE_SUCCESS)
-                invalidate_dtlb_entry (tlb_entry);
+        if (((tlb_entry = dtlb_probe(address)) & (1 << DTLB_HIT_BIT)) != 0)
+                invalidate_dtlb_entry(tlb_entry);
 }
 
 #define check_pgt_cache()       do { } while (0)
 
 
-#ifdef DEBUG_TLB
-
-/* DO NOT USE THESE FUNCTIONS.  These instructions aren't part of the Xtensa
+/*
+ * DO NOT USE THESE FUNCTIONS.  These instructions aren't part of the Xtensa
  * ISA and exist only for test purposes..
  * You may find it helpful for MMU debugging, however.
  *
@@ -193,8 +197,6 @@ static inline unsigned long read_itlb_translation (int way)
         return tmp;
 }
 
-#endif  /* DEBUG_TLB */
-
-
+#endif  /* __ASSEMBLY__ */
 #endif  /* __KERNEL__ */
-#endif  /* _XTENSA_PGALLOC_H */
+#endif  /* _XTENSA_TLBFLUSH_H */
diff --git a/include/asm-xtensa/unistd.h b/include/asm-xtensa/unistd.h
index 2e1a1b997e7d..8a7fb6964ce1 100644
--- a/include/asm-xtensa/unistd.h
+++ b/include/asm-xtensa/unistd.h
@@ -11,212 +11,593 @@
 #ifndef _XTENSA_UNISTD_H
 #define _XTENSA_UNISTD_H
 
-#define __NR_spill                0
-#define __NR_exit                 1
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_open                 5
-#define __NR_close                6
-#define __NR_creat                8
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_execve              11
-#define __NR_chdir               12
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_lchown              16
-#define __NR_break               17
-#define __NR_lseek               19
-#define __NR_getpid              20
-#define __NR_mount               21
-#define __NR_setuid              23
-#define __NR_getuid              24
-#define __NR_ptrace              26
-#define __NR_utime               30
-#define __NR_stty                31
-#define __NR_gtty                32
-#define __NR_access              33
-#define __NR_ftime               35
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_rename              38
-#define __NR_mkdir               39
-#define __NR_rmdir               40
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_times               43
-#define __NR_prof                44
-#define __NR_brk                 45
-#define __NR_setgid              46
-#define __NR_getgid              47
-#define __NR_signal              48
-#define __NR_geteuid             49
-#define __NR_getegid             50
-#define __NR_acct                51
-#define __NR_lock                53
-#define __NR_ioctl               54
-#define __NR_fcntl               55
-#define __NR_setpgid             57
-#define __NR_ulimit              58
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_ustat               62
-#define __NR_dup2                63
-#define __NR_getppid             64
-#define __NR_setsid              66
-#define __NR_sigaction           67
-#define __NR_setreuid            70
-#define __NR_setregid            71
-#define __NR_sigsuspend          72
-#define __NR_sigpending          73
-#define __NR_sethostname         74
-#define __NR_setrlimit           75
-#define __NR_getrlimit           76     /* Back compatible 2Gig limited rlimit */
-#define __NR_getrusage           77
-#define __NR_gettimeofday        78
-#define __NR_settimeofday        79
-#define __NR_getgroups           80
-#define __NR_setgroups           81
-#define __NR_select              82
-#define __NR_symlink             83
-#define __NR_readlink            85
-#define __NR_uselib              86
-#define __NR_swapon              87
-#define __NR_reboot              88
-#define __NR_munmap              91
-#define __NR_truncate            92
-#define __NR_ftruncate           93
-#define __NR_fchmod              94
-#define __NR_fchown              95
-#define __NR_getpriority         96
-#define __NR_setpriority         97
-#define __NR_profil              98
-#define __NR_statfs              99
-#define __NR_fstatfs            100
-#define __NR_ioperm             101
-#define __NR_syslog             103
-#define __NR_setitimer          104
-#define __NR_getitimer          105
-#define __NR_stat               106
-#define __NR_lstat              107
-#define __NR_fstat              108
-#define __NR_iopl               110
-#define __NR_vhangup            111
-#define __NR_idle               112
-#define __NR_wait4              114
-#define __NR_swapoff            115
-#define __NR_sysinfo            116
-#define __NR_fsync              118
-#define __NR_sigreturn          119
-#define __NR_clone              120
-#define __NR_setdomainname      121
-#define __NR_uname              122
-#define __NR_modify_ldt         123
-#define __NR_adjtimex           124
-#define __NR_mprotect           125
-#define __NR_create_module      127
-#define __NR_init_module        128
-#define __NR_delete_module      129
-#define __NR_quotactl           131
-#define __NR_getpgid            132
-#define __NR_fchdir             133
-#define __NR_bdflush            134
-#define __NR_sysfs              135
-#define __NR_personality        136
-#define __NR_setfsuid           138
-#define __NR_setfsgid           139
-#define __NR__llseek            140
-#define __NR_getdents           141
-#define __NR__newselect         142
-#define __NR_flock              143
-#define __NR_msync              144
-#define __NR_readv              145
-#define __NR_writev             146
-#define __NR_cacheflush         147
-#define __NR_cachectl           148
-#define __NR_sysxtensa          149
-#define __NR_sysdummy           150
-#define __NR_getsid             151
-#define __NR_fdatasync          152
-#define __NR__sysctl            153
-#define __NR_mlock              154
-#define __NR_munlock            155
-#define __NR_mlockall           156
-#define __NR_munlockall         157
-#define __NR_sched_setparam             158
-#define __NR_sched_getparam             159
-#define __NR_sched_setscheduler         160
-#define __NR_sched_getscheduler         161
-#define __NR_sched_yield                162
-#define __NR_sched_get_priority_max     163
-#define __NR_sched_get_priority_min     164
-#define __NR_sched_rr_get_interval      165
-#define __NR_nanosleep          166
-#define __NR_mremap             167
-#define __NR_accept             168
-#define __NR_bind               169
-#define __NR_connect            170
-#define __NR_getpeername        171
-#define __NR_getsockname        172
-#define __NR_getsockopt         173
-#define __NR_listen             174
-#define __NR_recv               175
-#define __NR_recvfrom           176
-#define __NR_recvmsg            177
-#define __NR_send               178
-#define __NR_sendmsg            179
-#define __NR_sendto             180
-#define __NR_setsockopt         181
-#define __NR_shutdown           182
-#define __NR_socket             183
-#define __NR_socketpair         184
-#define __NR_setresuid          185
-#define __NR_getresuid          186
-#define __NR_query_module       187
-#define __NR_poll               188
-#define __NR_nfsservctl         189
-#define __NR_setresgid          190
-#define __NR_getresgid          191
-#define __NR_prctl              192
-#define __NR_rt_sigreturn       193
-#define __NR_rt_sigaction       194
-#define __NR_rt_sigprocmask     195
-#define __NR_rt_sigpending      196
-#define __NR_rt_sigtimedwait    197
-#define __NR_rt_sigqueueinfo    198
-#define __NR_rt_sigsuspend      199
-#define __NR_pread              200
-#define __NR_pwrite             201
-#define __NR_chown              202
-#define __NR_getcwd             203
-#define __NR_capget             204
-#define __NR_capset             205
-#define __NR_sigaltstack        206
-#define __NR_sendfile           207
-#define __NR_mmap2              210
-#define __NR_truncate64         211
-#define __NR_ftruncate64        212
-#define __NR_stat64             213
-#define __NR_lstat64            214
-#define __NR_fstat64            215
-#define __NR_pivot_root         216
-#define __NR_mincore            217
-#define __NR_madvise            218
-#define __NR_getdents64         219
-
-/* Keep this last; should always equal the last valid call number. */
-#define __NR_Linux_syscalls     220
-
-/* user-visible error numbers are in the range -1 - -125: see
- * <asm-xtensa/errno.h> */
-
-#define SYSXTENSA_RESERVED         0    /* don't use this */
-#define SYSXTENSA_ATOMIC_SET       1    /* set variable */
-#define SYSXTENSA_ATOMIC_EXG_ADD   2    /* exchange memory and add */
-#define SYSXTENSA_ATOMIC_ADD       3    /* add to memory */
-#define SYSXTENSA_ATOMIC_CMP_SWP   4    /* compare and swap */
-
-#define SYSXTENSA_COUNT            5    /* count of syscall0 functions*/
+#ifndef __SYSCALL
+# define __SYSCALL(nr,func,nargs)
+#endif
+
+#define __NR_spill                                0
+__SYSCALL(  0, sys_ni_syscall, 0)
+#define __NR_xtensa                               1
+__SYSCALL(  1, sys_ni_syscall, 0)
+#define __NR_available4                           2
+__SYSCALL(  2, sys_ni_syscall, 0)
+#define __NR_available5                           3
+__SYSCALL(  3, sys_ni_syscall, 0)
+#define __NR_available6                           4
+__SYSCALL(  4, sys_ni_syscall, 0)
+#define __NR_available7                           5
+__SYSCALL(  5, sys_ni_syscall, 0)
+#define __NR_available8                           6
+__SYSCALL(  6, sys_ni_syscall, 0)
+#define __NR_available9                           7
+__SYSCALL(  7, sys_ni_syscall, 0)
+
+/* File Operations */
+
+#define __NR_open                                 8
+__SYSCALL(  8, sys_open, 3)
+#define __NR_close                                9
+__SYSCALL(  9, sys_close, 1)
+#define __NR_dup                                 10
+__SYSCALL( 10, sys_dup, 1)
+#define __NR_dup2                                11
+__SYSCALL( 11, sys_dup2, 2)
+#define __NR_read                                12
+__SYSCALL( 12, sys_read, 3)
+#define __NR_write                               13
+__SYSCALL( 13, sys_write, 3)
+#define __NR_select                              14
+__SYSCALL( 14, sys_select, 5)
+#define __NR_lseek                               15
+__SYSCALL( 15, sys_lseek, 3)
+#define __NR_poll                                16
+__SYSCALL( 16, sys_poll, 3)
+#define __NR__llseek                             17
+__SYSCALL( 17, sys_llseek, 5)
+#define __NR_epoll_wait                          18
+__SYSCALL( 18, sys_epoll_wait, 4)
+#define __NR_epoll_ctl                           19
+__SYSCALL( 19, sys_epoll_ctl, 4)
+#define __NR_epoll_create                        20
+__SYSCALL( 20, sys_epoll_create, 1)
+#define __NR_creat                               21
+__SYSCALL( 21, sys_creat, 2)
+#define __NR_truncate                            22
+__SYSCALL( 22, sys_truncate, 2)
+#define __NR_ftruncate                           23
+__SYSCALL( 23, sys_ftruncate, 2)
+#define __NR_readv                               24
+__SYSCALL( 24, sys_readv, 3)
+#define __NR_writev                              25
+__SYSCALL( 25, sys_writev, 3)
+#define __NR_fsync                               26
+__SYSCALL( 26, sys_fsync, 1)
+#define __NR_fdatasync                           27
+__SYSCALL( 27, sys_fdatasync, 1)
+#define __NR_truncate64                          28
+__SYSCALL( 28, sys_truncate64, 2)
+#define __NR_ftruncate64                         29
+__SYSCALL( 29, sys_ftruncate64, 2)
+#define __NR_pread64                             30
+__SYSCALL( 30, sys_pread64, 6)
+#define __NR_pwrite64                            31
+__SYSCALL( 31, sys_pwrite64, 6)
+
+#define __NR_link                                32
+__SYSCALL( 32, sys_link, 2)
+#define __NR_rename                              33
+__SYSCALL( 33, sys_rename, 2)
+#define __NR_symlink                             34
+__SYSCALL( 34, sys_symlink, 2)
+#define __NR_readlink                            35
+__SYSCALL( 35, sys_readlink, 3)
+#define __NR_mknod                               36
+__SYSCALL( 36, sys_mknod, 3)
+#define __NR_pipe                                37
+__SYSCALL( 37, xtensa_pipe, 1)
+#define __NR_unlink                              38
+__SYSCALL( 38, sys_unlink, 1)
+#define __NR_rmdir                               39
+__SYSCALL( 39, sys_rmdir, 1)
+
+#define __NR_mkdir                               40
+__SYSCALL( 40, sys_mkdir, 2)
+#define __NR_chdir                               41
+__SYSCALL( 41, sys_chdir, 1)
+#define __NR_fchdir                              42
+__SYSCALL( 42, sys_fchdir, 1)
+#define __NR_getcwd                              43
+__SYSCALL( 43, sys_getcwd, 2)
+
+#define __NR_chmod                               44
+__SYSCALL( 44, sys_chmod, 2)
+#define __NR_chown                               45
+__SYSCALL( 45, sys_chown, 3)
+#define __NR_stat                                46
+__SYSCALL( 46, sys_newstat, 2)
+#define __NR_stat64                              47
+__SYSCALL( 47, sys_stat64, 2)
+
+#define __NR_lchown                              48
+__SYSCALL( 48, sys_lchown, 3)
+#define __NR_lstat                               49
+__SYSCALL( 49, sys_newlstat, 2)
+#define __NR_lstat64                             50
+__SYSCALL( 50, sys_lstat64, 2)
+#define __NR_available51                         51
+__SYSCALL( 51, sys_ni_syscall, 0)
+
+#define __NR_fchmod                              52
+__SYSCALL( 52, sys_fchmod, 2)
+#define __NR_fchown                              53
+__SYSCALL( 53, sys_fchown, 3)
+#define __NR_fstat                               54
+__SYSCALL( 54, sys_newfstat, 2)
+#define __NR_fstat64                             55
+__SYSCALL( 55, sys_fstat64, 2)
+
+#define __NR_flock                               56
+__SYSCALL( 56, sys_flock, 2)
+#define __NR_access                              57
+__SYSCALL( 57, sys_access, 2)
+#define __NR_umask                               58
+__SYSCALL( 58, sys_umask, 1)
+#define __NR_getdents                            59
+__SYSCALL( 59, sys_getdents, 3)
+#define __NR_getdents64                          60
+__SYSCALL( 60, sys_getdents64, 3)
+#define __NR_fcntl64                             61
+__SYSCALL( 61, sys_fcntl64, 3)
+#define __NR_available62                         62
+__SYSCALL( 62, sys_ni_syscall, 0)
+#define __NR_fadvise64_64                        63
+__SYSCALL( 63, sys_fadvise64_64, 6)
+#define __NR_utime                               64     /* glibc 2.3.3 ?? */
+__SYSCALL( 64, sys_utime, 2)
+#define __NR_utimes                              65
+__SYSCALL( 65, sys_utimes, 2)
+#define __NR_ioctl                               66
+__SYSCALL( 66, sys_ioctl, 3)
+#define __NR_fcntl                               67
+__SYSCALL( 67, sys_fcntl, 3)
+
+#define __NR_setxattr                            68
+__SYSCALL( 68, sys_setxattr, 5)
+#define __NR_getxattr                            69
+__SYSCALL( 69, sys_getxattr, 4)
+#define __NR_listxattr                           70
+__SYSCALL( 70, sys_listxattr, 3)
+#define __NR_removexattr                         71
+__SYSCALL( 71, sys_removexattr, 2)
+#define __NR_lsetxattr                           72
+__SYSCALL( 72, sys_lsetxattr, 5)
+#define __NR_lgetxattr                           73
+__SYSCALL( 73, sys_lgetxattr, 4)
+#define __NR_llistxattr                          74
+__SYSCALL( 74, sys_llistxattr, 3)
+#define __NR_lremovexattr                        75
+__SYSCALL( 75, sys_lremovexattr, 2)
+#define __NR_fsetxattr                           76
+__SYSCALL( 76, sys_fsetxattr, 5)
+#define __NR_fgetxattr                           77
+__SYSCALL( 77, sys_fgetxattr, 4)
+#define __NR_flistxattr                          78
+__SYSCALL( 78, sys_flistxattr, 3)
+#define __NR_fremovexattr                        79
+__SYSCALL( 79, sys_fremovexattr, 2)
+
+/* File Map / Shared Memory Operations */
+
+#define __NR_mmap2                               80
+__SYSCALL( 80, xtensa_mmap2, 6)
+#define __NR_munmap                              81
+__SYSCALL( 81, sys_munmap, 2)
+#define __NR_mprotect                            82
+__SYSCALL( 82, sys_mprotect, 3)
+#define __NR_brk                                 83
+__SYSCALL( 83, sys_brk, 1)
+#define __NR_mlock                               84
+__SYSCALL( 84, sys_mlock, 2)
+#define __NR_munlock                             85
+__SYSCALL( 85, sys_munlock, 2)
+#define __NR_mlockall                            86
+__SYSCALL( 86, sys_mlockall, 1)
+#define __NR_munlockall                          87
+__SYSCALL( 87, sys_munlockall, 0)
+#define __NR_mremap                              88
+__SYSCALL( 88, sys_mremap, 4)
+#define __NR_msync                               89
+__SYSCALL( 89, sys_msync, 3)
+#define __NR_mincore                             90
+__SYSCALL( 90, sys_mincore, 3)
+#define __NR_madvise                             91
+__SYSCALL( 91, sys_madvise, 3)
+#define __NR_shmget                              92
+__SYSCALL( 92, sys_shmget, 4)
+#define __NR_shmat                               93
+__SYSCALL( 93, xtensa_shmat, 4)
+#define __NR_shmctl                              94
+__SYSCALL( 94, sys_shmctl, 4)
+#define __NR_shmdt                               95
+__SYSCALL( 95, sys_shmdt, 4)
+
+/* Socket Operations */
+
+#define __NR_socket                              96
+__SYSCALL( 96, sys_socket, 3)
+#define __NR_setsockopt                          97
+__SYSCALL( 97, sys_setsockopt, 5)
+#define __NR_getsockopt                          98
+__SYSCALL( 98, sys_getsockopt, 5)
+#define __NR_shutdown                            99
+__SYSCALL( 99, sys_shutdown, 2)
+
+#define __NR_bind                               100
+__SYSCALL(100, sys_bind, 3)
+#define __NR_connect                            101
+__SYSCALL(101, sys_connect, 3)
+#define __NR_listen                             102
+__SYSCALL(102, sys_listen, 2)
+#define __NR_accept                             103
+__SYSCALL(103, sys_accept, 3)
+
+#define __NR_getsockname                        104
+__SYSCALL(104, sys_getsockname, 3)
+#define __NR_getpeername                        105
+__SYSCALL(105, sys_getpeername, 3)
+#define __NR_sendmsg                            106
+__SYSCALL(106, sys_sendmsg, 3)
+#define __NR_recvmsg                            107
+__SYSCALL(107, sys_recvmsg, 3)
+#define __NR_send                               108
+__SYSCALL(108, sys_send, 4)
+#define __NR_recv                               109
+__SYSCALL(109, sys_recv, 4)
+#define __NR_sendto                             110
+__SYSCALL(110, sys_sendto, 6)
+#define __NR_recvfrom                           111
+__SYSCALL(111, sys_recvfrom, 6)
+
+#define __NR_socketpair                         112
+__SYSCALL(112, sys_socketpair, 4)
+#define __NR_sendfile                           113
+__SYSCALL(113, sys_sendfile, 4)
+#define __NR_sendfile64                         114
+__SYSCALL(114, sys_sendfile64, 4)
+#define __NR_available115                       115
+__SYSCALL(115, sys_ni_syscall, 0)
+
+/* Process Operations */
+
+#define __NR_clone                              116
+__SYSCALL(116, xtensa_clone, 5)
+#define __NR_execve                             117
+__SYSCALL(117, xtensa_execve, 3)
+#define __NR_exit                               118
+__SYSCALL(118, sys_exit, 1)
+#define __NR_exit_group                         119
+__SYSCALL(119, sys_exit_group, 1)
+#define __NR_getpid                             120
+__SYSCALL(120, sys_getpid, 0)
+#define __NR_wait4                              121
+__SYSCALL(121, sys_wait4, 4)
+#define __NR_waitid                             122
+__SYSCALL(122, sys_waitid, 5)
+#define __NR_kill                               123
+__SYSCALL(123, sys_kill, 2)
+#define __NR_tkill                              124
+__SYSCALL(124, sys_tkill, 2)
+#define __NR_tgkill                             125
+__SYSCALL(125, sys_tgkill, 3)
+#define __NR_set_tid_address                    126
+__SYSCALL(126, sys_set_tid_address, 1)
+#define __NR_gettid                             127
+__SYSCALL(127, sys_gettid, 0)
+#define __NR_setsid                             128
+__SYSCALL(128, sys_setsid, 0)
+#define __NR_getsid                             129
+__SYSCALL(129, sys_getsid, 1)
+#define __NR_prctl                              130
+__SYSCALL(130, sys_prctl, 5)
+#define __NR_personality                        131
+__SYSCALL(131, sys_personality, 1)
+#define __NR_getpriority                        132
+__SYSCALL(132, sys_getpriority, 2)
+#define __NR_setpriority                        133
+__SYSCALL(133, sys_setpriority, 3)
+#define __NR_setitimer                          134
+__SYSCALL(134, sys_setitimer, 3)
+#define __NR_getitimer                          135
+__SYSCALL(135, sys_getitimer, 2)
+#define __NR_setuid                             136
+__SYSCALL(136, sys_setuid, 1)
+#define __NR_getuid                             137
+__SYSCALL(137, sys_getuid, 0)
+#define __NR_setgid                             138
+__SYSCALL(138, sys_setgid, 1)
+#define __NR_getgid                             139
+__SYSCALL(139, sys_getgid, 0)
+#define __NR_geteuid                            140
+__SYSCALL(140, sys_geteuid, 0)
+#define __NR_getegid                            141
+__SYSCALL(141, sys_getegid, 0)
+#define __NR_setreuid                           142
+__SYSCALL(142, sys_setreuid, 2)
+#define __NR_setregid                           143
+__SYSCALL(143, sys_setregid, 2)
+#define __NR_setresuid                          144
+__SYSCALL(144, sys_setresuid, 3)
+#define __NR_getresuid                          145
+__SYSCALL(145, sys_getresuid, 3)
+#define __NR_setresgid                          146
+__SYSCALL(146, sys_setresgid, 3)
+#define __NR_getresgid                          147
+__SYSCALL(147, sys_getresgid, 3)
+#define __NR_setpgid                            148
+__SYSCALL(148, sys_setpgid, 2)
+#define __NR_getpgid                            149
+__SYSCALL(149, sys_getpgid, 1)
+#define __NR_getppid                            150
+__SYSCALL(150, sys_getppid, 0)
+#define __NR_available151                       151
+__SYSCALL(151, sys_ni_syscall, 0)
+
+#define __NR_reserved152                        152     /* set_thread_area */
+__SYSCALL(152, sys_ni_syscall, 0)
+#define __NR_reserved153                        153     /* get_thread_area */
+__SYSCALL(153, sys_ni_syscall, 0)
+#define __NR_times                              154
+__SYSCALL(154, sys_times, 1)
+#define __NR_acct                               155
+__SYSCALL(155, sys_acct, 1)
+#define __NR_sched_setaffinity                  156
+__SYSCALL(156, sys_sched_setaffinity, 3)
+#define __NR_sched_getaffinity                  157
+__SYSCALL(157, sys_sched_getaffinity, 3)
+#define __NR_capget                             158
+__SYSCALL(158, sys_capget, 2)
+#define __NR_capset                             159
+__SYSCALL(159, sys_capset, 2)
+#define __NR_ptrace                             160
+__SYSCALL(160, sys_ptrace, 4)
+#define __NR_semtimedop                         161
+__SYSCALL(161, sys_semtimedop, 5)
+#define __NR_semget                             162
+__SYSCALL(162, sys_semget, 4)
+#define __NR_semop                              163
+__SYSCALL(163, sys_semop, 4)
+#define __NR_semctl                             164
+__SYSCALL(164, sys_semctl, 4)
+#define __NR_available165                       165
+__SYSCALL(165, sys_ni_syscall, 0)
+#define __NR_msgget                             166
+__SYSCALL(166, sys_msgget, 4)
+#define __NR_msgsnd                             167
+__SYSCALL(167, sys_msgsnd, 4)
+#define __NR_msgrcv                             168
+__SYSCALL(168, sys_msgrcv, 4)
+#define __NR_msgctl                             169
+__SYSCALL(169, sys_msgctl, 4)
+#define __NR_available170                       170
+__SYSCALL(170, sys_ni_syscall, 0)
+#define __NR_available171                       171
+__SYSCALL(171, sys_ni_syscall, 0)
+
+/* File System */
+
+#define __NR_mount                              172
+__SYSCALL(172, sys_mount, 5)
+#define __NR_swapon                             173
+__SYSCALL(173, sys_swapon, 2)
+#define __NR_chroot                             174
+__SYSCALL(174, sys_chroot, 1)
+#define __NR_pivot_root                         175
+__SYSCALL(175, sys_pivot_root, 2)
+#define __NR_umount                             176
+__SYSCALL(176, sys_umount, 2)
+#define __NR_swapoff                            177
+__SYSCALL(177, sys_swapoff, 1)
+#define __NR_sync                               178
+__SYSCALL(178, sys_sync, 0)
+#define __NR_available179                       179
+__SYSCALL(179, sys_ni_syscall, 0)
+#define __NR_setfsuid                           180
+__SYSCALL(180, sys_setfsuid, 1)
+#define __NR_setfsgid                           181
+__SYSCALL(181, sys_setfsgid, 1)
+#define __NR_sysfs                              182
+__SYSCALL(182, sys_sysfs, 3)
+#define __NR_ustat                              183
+__SYSCALL(183, sys_ustat, 2)
+#define __NR_statfs                             184
+__SYSCALL(184, sys_statfs, 2)
+#define __NR_fstatfs                            185
+__SYSCALL(185, sys_fstatfs, 2)
+#define __NR_statfs64                           186
+__SYSCALL(186, sys_statfs64, 3)
+#define __NR_fstatfs64                          187
+__SYSCALL(187, sys_fstatfs64, 3)
+
+/* System */
+
+#define __NR_setrlimit                          188
+__SYSCALL(188, sys_setrlimit, 2)
+#define __NR_getrlimit                          189
+__SYSCALL(189, sys_getrlimit, 2)
+#define __NR_getrusage                          190
+__SYSCALL(190, sys_getrusage, 2)
+#define __NR_futex                              191
+__SYSCALL(191, sys_futex, 5)
+#define __NR_gettimeofday                       192
+__SYSCALL(192, sys_gettimeofday, 2)
+#define __NR_settimeofday                       193
+__SYSCALL(193, sys_settimeofday, 2)
+#define __NR_adjtimex                           194
+__SYSCALL(194, sys_adjtimex, 1)
+#define __NR_nanosleep                          195
+__SYSCALL(195, sys_nanosleep, 2)
+#define __NR_getgroups                          196
+__SYSCALL(196, sys_getgroups, 2)
+#define __NR_setgroups                          197
+__SYSCALL(197, sys_setgroups, 2)
+#define __NR_sethostname                        198
+__SYSCALL(198, sys_sethostname, 2)
+#define __NR_setdomainname                      199
+__SYSCALL(199, sys_setdomainname, 2)
+#define __NR_syslog                             200
+__SYSCALL(200, sys_syslog, 3)
+#define __NR_vhangup                            201
+__SYSCALL(201, sys_vhangup, 0)
+#define __NR_uselib                             202
+__SYSCALL(202, sys_uselib, 1)
+#define __NR_reboot                             203
+__SYSCALL(203, sys_reboot, 3)
+#define __NR_quotactl                           204
+__SYSCALL(204, sys_quotactl, 4)
+#define __NR_nfsservctl                         205
+__SYSCALL(205, sys_nfsservctl, 3)
+#define __NR__sysctl                            206
+__SYSCALL(206, sys_sysctl, 1)
+#define __NR_bdflush                            207
+__SYSCALL(207, sys_bdflush, 2)
+#define __NR_uname                              208
+__SYSCALL(208, sys_newuname, 1)
+#define __NR_sysinfo                            209
+__SYSCALL(209, sys_sysinfo, 1)
+#define __NR_init_module                        210
+__SYSCALL(210, sys_init_module, 2)
+#define __NR_delete_module                      211
+__SYSCALL(211, sys_delete_module, 1)
+
+#define __NR_sched_setparam                     212
+__SYSCALL(212, sys_sched_setparam, 2)
+#define __NR_sched_getparam                     213
+__SYSCALL(213, sys_sched_getparam, 2)
+#define __NR_sched_setscheduler                 214
+__SYSCALL(214, sys_sched_setscheduler, 3)
+#define __NR_sched_getscheduler                 215
+__SYSCALL(215, sys_sched_getscheduler, 1)
+#define __NR_sched_get_priority_max             216
+__SYSCALL(216, sys_sched_get_priority_max, 1)
+#define __NR_sched_get_priority_min             217
+__SYSCALL(217, sys_sched_get_priority_min, 1)
+#define __NR_sched_rr_get_interval              218
+__SYSCALL(218, sys_sched_rr_get_interval, 2)
+#define __NR_sched_yield                        219
+__SYSCALL(219, sys_sched_yield, 0)
+#define __NR_sigreturn                          222
+__SYSCALL(222, xtensa_sigreturn, 0)
+
+/* Signal Handling */
+
+#define __NR_restart_syscall                    223
+__SYSCALL(223, sys_restart_syscall, 0)
+#define __NR_sigaltstack                        224
+__SYSCALL(224, xtensa_sigaltstack, 2)
+#define __NR_rt_sigreturn                       225
+__SYSCALL(225, xtensa_rt_sigreturn, 1)
+#define __NR_rt_sigaction                       226
+__SYSCALL(226, sys_rt_sigaction, 4)
+#define __NR_rt_sigprocmask                     227
+__SYSCALL(227, sys_rt_sigprocmask, 4)
+#define __NR_rt_sigpending                      228
+__SYSCALL(228, sys_rt_sigpending, 2)
+#define __NR_rt_sigtimedwait                    229
+__SYSCALL(229, sys_rt_sigtimedwait, 4)
+#define __NR_rt_sigqueueinfo                    230
+__SYSCALL(230, sys_rt_sigqueueinfo, 3)
+#define __NR_rt_sigsuspend                      231
+__SYSCALL(231, xtensa_rt_sigsuspend, 2)
+
+/* Message */
+
+#define __NR_mq_open                            232
+__SYSCALL(232, sys_mq_open, 4)
+#define __NR_mq_unlink                          233
+__SYSCALL(233, sys_mq_unlink, 1)
+#define __NR_mq_timedsend                       234
+__SYSCALL(234, sys_mq_timedsend, 5)
+#define __NR_mq_timedreceive                    235
+__SYSCALL(235, sys_mq_timedreceive, 5)
+#define __NR_mq_notify                          236
+__SYSCALL(236, sys_mq_notify, 2)
+#define __NR_mq_getsetattr                      237
+__SYSCALL(237, sys_mq_getsetattr, 3)
+#define __NR_available238                       238
+__SYSCALL(238, sys_ni_syscall, 0)
+
+/* IO */
+
+#define __NR_io_setup                           239
+__SYSCALL(239, sys_io_setup, 2)
+#define __NR_io_destroy                         240
+__SYSCALL(240, sys_io_destroy, 1)
+#define __NR_io_submit                          241
+__SYSCALL(241, sys_io_submit, 3)
+#define __NR_io_getevents                       242
+__SYSCALL(242, sys_io_getevents, 5)
+#define __NR_io_cancel                          243
+__SYSCALL(243, sys_io_cancel, 3)
+#define __NR_clock_settime                      244
+__SYSCALL(244, sys_clock_settime, 2)
+#define __NR_clock_gettime                      245
+__SYSCALL(245, sys_clock_gettime, 2)
+#define __NR_clock_getres                       246
+__SYSCALL(246, sys_clock_getres, 2)
+#define __NR_clock_nanosleep                    247
+__SYSCALL(247, sys_clock_nanosleep, 4)
+
+/* Timer */
+
+#define __NR_timer_create                       248
+__SYSCALL(248, sys_timer_create, 3)
+#define __NR_timer_delete                       249
+__SYSCALL(249, sys_timer_delete, 1)
+#define __NR_timer_settime                      250
+__SYSCALL(250, sys_timer_settime, 4)
+#define __NR_timer_gettime                      251
+__SYSCALL(251, sys_timer_gettime, 2)
+#define __NR_timer_getoverrun                   252
+__SYSCALL(252, sys_timer_getoverrun, 1)
+
+/* System */
+
+#define __NR_reserved244                        253
+__SYSCALL(253, sys_ni_syscall, 0)
+#define __NR_lookup_dcookie                     254
+__SYSCALL(254, sys_lookup_dcookie, 4)
+#define __NR_available255                       255
+__SYSCALL(255, sys_ni_syscall, 0)
+#define __NR_add_key                            256
+__SYSCALL(256, sys_add_key, 5)
+#define __NR_request_key                        257
+__SYSCALL(257, sys_request_key, 5)
+#define __NR_keyctl                             258
+__SYSCALL(258, sys_keyctl, 5)
+#define __NR_available259                       259
+__SYSCALL(259, sys_ni_syscall, 0)
+
+#define __NR_syscall_count                      261
+
+/*
+ * sysxtensa syscall handler
+ *
+ * int sysxtensa (SYS_XTENSA_ATOMIC_SET,     ptr, val,    unused);
+ * int sysxtensa (SYS_XTENSA_ATOMIC_ADD,     ptr, val,    unused);
+ * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val,    unused);
+ * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
+ *        a2            a6                   a3    a4      a5
+ */
+
+#define SYS_XTENSA_RESERVED               0     /* don't use this */
+#define SYS_XTENSA_ATOMIC_SET             1     /* set variable */
+#define SYS_XTENSA_ATOMIC_EXG_ADD         2     /* exchange memory and add */
+#define SYS_XTENSA_ATOMIC_ADD             3     /* add to memory */
+#define SYS_XTENSA_ATOMIC_CMP_SWP         4     /* compare and swap */
+
+#define SYS_XTENSA_COUNT                  5     /* count */
+
+#ifdef __KERNEL__
 
 /*
  * "Conditional" syscalls
@@ -230,6 +611,9 @@
 #define __ARCH_WANT_SYS_UTIME
 #define __ARCH_WANT_SYS_LLSEEK
 #define __ARCH_WANT_SYS_RT_SIGACTION
-#endif /* __KERNEL__ */
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+
+#endif  /* __KERNEL__ */
 
 #endif  /* _XTENSA_UNISTD_H */
+
diff --git a/include/asm-xtensa/variant-fsf/core.h b/include/asm-xtensa/variant-fsf/core.h
new file mode 100644
index 000000000000..2f337605c744
--- /dev/null
+++ b/include/asm-xtensa/variant-fsf/core.h
@@ -0,0 +1,359 @@
+/*
+ * Xtensa processor core configuration information.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999-2006 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_H
+#define _XTENSA_CORE_H
+
+
+/****************************************************************************
+            Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+                                ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE                   1       /* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED             1       /* windowed registers option */
+#define XCHAL_NUM_AREGS                 64      /* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2            6       /* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE      3       /* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG                1       /* debug option */
+#define XCHAL_HAVE_DENSITY              1       /* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS                1       /* zero-overhead loops */
+#define XCHAL_HAVE_NSA                  1       /* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX               0       /* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT                 0       /* SEXT instruction */
+#define XCHAL_HAVE_CLAMPS               0       /* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16                0       /* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32                0       /* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH           0       /* MULUH/MULSH instructions */
+#define XCHAL_HAVE_L32R                 1       /* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS    1       /* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16              0       /* CONST16 instruction */
+#define XCHAL_HAVE_ADDX                 1       /* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES        0       /* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES   0       /* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12           1       /* (obsolete option) */
+#define XCHAL_HAVE_ABS                  1       /* ABS instruction */
+/*#define XCHAL_HAVE_POPC               0*/     /* POPC instruction */
+/*#define XCHAL_HAVE_CRC                0*/     /* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC         0       /* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I               0       /* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION          0       /* speculation */
+#define XCHAL_HAVE_FULL_RESET           1       /* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS              1       /* */
+#define XCHAL_NUM_MISC_REGS             2       /* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER           0       /* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID                 1       /* processor ID register */
+#define XCHAL_HAVE_THREADPTR            1       /* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS             0       /* boolean registers */
+#define XCHAL_HAVE_CP                   0       /* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG                 0       /* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16                0       /* MAC16 package */
+#define XCHAL_HAVE_VECTORFPU2005        0       /* vector floating-point pkg */
+#define XCHAL_HAVE_FP                   0       /* floating point pkg */
+#define XCHAL_HAVE_VECTRA1              0       /* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX             0       /* Vectra LX pkg */
+#define XCHAL_HAVE_HIFI2                0       /* HiFi2 Audio Engine pkg */
+
+
+/*----------------------------------------------------------------------
+                                MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES   4       /* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH          4       /* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH                4       /* data width in bytes */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION  1       /* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION 1       /* unaligned stores cause exc.*/
+
+#define XCHAL_CORE_ID                   "fsf"   /* alphanum core name
+                                                   (CoreID) set in the Xtensa
+                                                   Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID           0x00006700      /* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0              0xC103C3FF      /* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1              0x0C006700      /* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME           "LX2.0.0"       /* full version name */
+#define XCHAL_HW_VERSION_MAJOR          2200    /* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR          0       /* minor ver# of targeted hw */
+#define XTHAL_HW_REL_LX2                1
+#define XTHAL_HW_REL_LX2_0              1
+#define XTHAL_HW_REL_LX2_0_0            1
+#define XCHAL_HW_CONFIGID_RELIABLE      1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR      2200    /* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR      0       /* minor v of earliest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR      2200    /* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR      0       /* minor v of latest tgt hw */
+
+
+/*----------------------------------------------------------------------
+                                CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE           16      /* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE           16      /* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH          4       /* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH          4       /* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE               8192    /* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE               8192    /* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK       0       /* writeback feature */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+                                CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF                  1       /* any outbound PIF present */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH           8
+#define XCHAL_DCACHE_SETWIDTH           8
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS               2
+#define XCHAL_DCACHE_WAYS               2
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE      0
+#define XCHAL_DCACHE_LINE_LOCKABLE      0
+#define XCHAL_ICACHE_ECC_PARITY         0
+#define XCHAL_DCACHE_ECC_PARITY         0
+
+/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
+#define XCHAL_CA_BITS                   4
+
+
+/*----------------------------------------------------------------------
+                        INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM               0       /* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM               0       /* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM               0       /* number of core data ROMs */
+#define XCHAL_NUM_DATARAM               0       /* number of core data RAMs */
+#define XCHAL_NUM_URAM                  0       /* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI                  0       /* number of core XLMI ports */
+
+
+/*----------------------------------------------------------------------
+                        INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS           1       /* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS   1       /* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI                  0       /* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT               1       /* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS                3       /* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS            17      /* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2       5       /* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS         10      /* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS             4       /* number of interrupt levels
+                                                   (not including level zero) */
+#define XCHAL_EXCM_LEVEL                1       /* level masked by PS.EXCM */
+        /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK            0x000064F9
+#define XCHAL_INTLEVEL2_MASK            0x00008902
+#define XCHAL_INTLEVEL3_MASK            0x00011204
+#define XCHAL_INTLEVEL4_MASK            0x00000000
+#define XCHAL_INTLEVEL5_MASK            0x00000000
+#define XCHAL_INTLEVEL6_MASK            0x00000000
+#define XCHAL_INTLEVEL7_MASK            0x00000000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK   0x000064F9
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK   0x0000EDFB
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK   0x0001FFFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL                1
+#define XCHAL_INT1_LEVEL                2
+#define XCHAL_INT2_LEVEL                3
+#define XCHAL_INT3_LEVEL                1
+#define XCHAL_INT4_LEVEL                1
+#define XCHAL_INT5_LEVEL                1
+#define XCHAL_INT6_LEVEL                1
+#define XCHAL_INT7_LEVEL                1
+#define XCHAL_INT8_LEVEL                2
+#define XCHAL_INT9_LEVEL                3
+#define XCHAL_INT10_LEVEL               1
+#define XCHAL_INT11_LEVEL               2
+#define XCHAL_INT12_LEVEL               3
+#define XCHAL_INT13_LEVEL               1
+#define XCHAL_INT14_LEVEL               1
+#define XCHAL_INT15_LEVEL               2
+#define XCHAL_INT16_LEVEL               3
+#define XCHAL_DEBUGLEVEL                4       /* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT     0       /* OCD external db interrupt */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT7_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT8_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT9_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT10_TYPE        XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE        XTHAL_INTTYPE_TIMER
+#define XCHAL_INT12_TYPE        XTHAL_INTTYPE_TIMER
+#define XCHAL_INT13_TYPE        XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT14_TYPE        XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT15_TYPE        XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT16_TYPE        XTHAL_INTTYPE_SOFTWARE
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
+#define XCHAL_INTTYPE_MASK_SOFTWARE     0x0001E000
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE  0x00000380
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
+#define XCHAL_INTTYPE_MASK_TIMER        0x00001C00
+#define XCHAL_INTTYPE_MASK_NMI          0x00000000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR  0x00000000
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT          10      /* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT          11      /* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT          12      /* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT          XTHAL_TIMER_UNCONFIGURED
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+/*  (There are many interrupts each at level(s) 1, 2, 3.)  */
+
+
+/*
+ *  External interrupt vectors/levels.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
+#define XCHAL_EXTINT0_NUM               0       /* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM               1       /* (intlevel 2) */
+#define XCHAL_EXTINT2_NUM               2       /* (intlevel 3) */
+#define XCHAL_EXTINT3_NUM               3       /* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM               4       /* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM               5       /* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM               6       /* (intlevel 1) */
+#define XCHAL_EXTINT7_NUM               7       /* (intlevel 1) */
+#define XCHAL_EXTINT8_NUM               8       /* (intlevel 2) */
+#define XCHAL_EXTINT9_NUM               9       /* (intlevel 3) */
+
+
+/*----------------------------------------------------------------------
+                        EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION               2       /* Xtensa Exception Architecture
+                                                   number: 1 == XEA1 (old)
+                                                           2 == XEA2 (new)
+                                                           0 == XEAX (extern) */
+#define XCHAL_HAVE_XEA1                 0       /* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2                 1       /* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX                 0       /* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS           1       /* exception option */
+#define XCHAL_HAVE_MEM_ECC_PARITY       0       /* local memory ECC/parity */
+
+#define XCHAL_RESET_VECTOR_VADDR        0xFE000020
+#define XCHAL_RESET_VECTOR_PADDR        0xFE000020
+#define XCHAL_USER_VECTOR_VADDR         0xD0000220
+#define XCHAL_USER_VECTOR_PADDR         0x00000220
+#define XCHAL_KERNEL_VECTOR_VADDR       0xD0000200
+#define XCHAL_KERNEL_VECTOR_PADDR       0x00000200
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR    0xD0000290
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR    0x00000290
+#define XCHAL_WINDOW_VECTORS_VADDR      0xD0000000
+#define XCHAL_WINDOW_VECTORS_PADDR      0x00000000
+#define XCHAL_INTLEVEL2_VECTOR_VADDR    0xD0000240
+#define XCHAL_INTLEVEL2_VECTOR_PADDR    0x00000240
+#define XCHAL_INTLEVEL3_VECTOR_VADDR    0xD0000250
+#define XCHAL_INTLEVEL3_VECTOR_PADDR    0x00000250
+#define XCHAL_INTLEVEL4_VECTOR_VADDR    0xFE000520
+#define XCHAL_INTLEVEL4_VECTOR_PADDR    0xFE000520
+#define XCHAL_DEBUG_VECTOR_VADDR        XCHAL_INTLEVEL4_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR        XCHAL_INTLEVEL4_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+                                DEBUG
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_OCD                  1       /* OnChipDebug option */
+#define XCHAL_NUM_IBREAK                2       /* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK                2       /* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY        1       /* faster OCD option */
+
+
+/*----------------------------------------------------------------------
+                                MMU
+  ----------------------------------------------------------------------*/
+
+/*  See <xtensa/config/core-matmap.h> header file for more details.  */
+
+#define XCHAL_HAVE_TLBS                 1       /* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY         0       /* one way maps I+D 4GB vaddr */
+#define XCHAL_HAVE_IDENTITY_MAP         0       /* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR            0       /* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR      0       /* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR        0       /* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU              1       /* full MMU (with page table
+                                                   [autorefill] and protection)
+                                                   usable for an MMU-based OS */
+/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
+#define XCHAL_ITLB_ARF_ENTRIES_LOG2     2       /* log2(autorefill way size) */
+#define XCHAL_DTLB_ARF_ENTRIES_LOG2     2       /* log2(autorefill way size) */
+
+#define XCHAL_MMU_ASID_BITS             8       /* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS                 4       /* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS             2       /* num of bits in RING field */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+
diff --git a/include/asm-xtensa/variant-fsf/tie.h b/include/asm-xtensa/variant-fsf/tie.h
new file mode 100644
index 000000000000..a73c71664918
--- /dev/null
+++ b/include/asm-xtensa/variant-fsf/tie.h
@@ -0,0 +1,22 @@
+/*
+ * Xtensa processor core configuration information.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999-2006 Tensilica Inc.
+ */
+
+#ifndef XTENSA_TIE_H
+#define XTENSA_TIE_H
+
+/*----------------------------------------------------------------------
+                        COPROCESSORS and EXTRA STATE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_CP_NUM                    0       /* number of coprocessors */
+#define XCHAL_CP_MASK                   0x00
+
+#endif /*XTENSA_CONFIG_TIE_H*/
+
diff --git a/include/asm-xtensa/xtensa/cacheasm.h b/include/asm-xtensa/xtensa/cacheasm.h
deleted file mode 100644
index 0cdbb0bf180e..000000000000
--- a/include/asm-xtensa/xtensa/cacheasm.h
+++ /dev/null
@@ -1,708 +0,0 @@
-#ifndef XTENSA_CACHEASM_H
-#define XTENSA_CACHEASM_H
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- * include/asm-xtensa/xtensa/cacheasm.h -- assembler-specific cache
- * related definitions that depend on CORE configuration.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002 Tensilica Inc.
- */
-
-
-#include <xtensa/coreasm.h>
-
-
-/*
- *  This header file defines assembler macros of the form:
- *      <x>cache_<func>
- *  where <x> is 'i' or 'd' for instruction and data caches,
- *  and <func> indicates the function of the macro.
- *
- *  The following functions <func> are defined,
- *  and apply only to the specified cache (I or D):
- *
- *  reset
- *      Resets the cache.
- *
- *  sync
- *      Makes sure any previous cache instructions have been completed;
- *      ie. makes sure any previous cache control operations
- *      have had full effect and been synchronized to memory.
- *      Eg. any invalidate completed [so as not to generate a hit],
- *      any writebacks or other pipelined writes written to memory, etc.
- *
- *  invalidate_line             (single cache line)
- *  invalidate_region           (specified memory range)
- *  invalidate_all              (entire cache)
- *      Invalidates all cache entries that cache
- *      data from the specified memory range.
- *      NOTE: locked entries are not invalidated.
- *
- *  writeback_line              (single cache line)
- *  writeback_region            (specified memory range)
- *  writeback_all               (entire cache)
- *      Writes back to memory all dirty cache entries
- *      that cache data from the specified memory range,
- *      and marks these entries as clean.
- *      NOTE: on some future implementations, this might
- *              also invalidate.
- *      NOTE: locked entries are written back, but never invalidated.
- *      NOTE: instruction caches never implement writeback.
- *
- *  writeback_inv_line          (single cache line)
- *  writeback_inv_region        (specified memory range)
- *  writeback_inv_all           (entire cache)
- *      Writes back to memory all dirty cache entries
- *      that cache data from the specified memory range,
- *      and invalidates these entries (including all clean
- *      cache entries that cache data from that range).
- *      NOTE: locked entries are written back but not invalidated.
- *      NOTE: instruction caches never implement writeback.
- *
- *  lock_line                   (single cache line)
- *  lock_region                 (specified memory range)
- *      Prefetch and lock the specified memory range into cache.
- *      NOTE:  if any part of the specified memory range cannot
- *      be locked, a ??? exception occurs.  These macros don't
- *      do anything special (yet anyway) to handle this situation.
- *
- *  unlock_line                 (single cache line)
- *  unlock_region               (specified memory range)
- *  unlock_all                  (entire cache)
- *      Unlock cache entries that cache the specified memory range.
- *      Entries not already locked are unaffected.
- */
-
-
-
-/***************************   GENERIC -- ALL CACHES   ***************************/
-
-
-/*
- *  The following macros assume the following cache size/parameter limits
- *  in the current Xtensa core implementation:
- *      cache size:     1024 bytes minimum
- *      line size:      16 - 64 bytes
- *      way count:      1 - 4
- *
- *  Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
- *  Hence the assumption that each loop can execute four cache instructions.
- *
- *  Correspondingly, the offset range of instructions is assumed able to cover
- *  four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
- *  both hit and indexed cache instructions.  Ie. these offsets are all
- *  valid:  0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
- *  This is true of all original cache instructions
- *  (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
- *  of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
- *  This is also true of subsequent cache instructions
- *  (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
- *  of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
- *
- *  (Maximum cache size, currently 32k, doesn't affect the following macros.
- *  Cache ways > MMU min page size cause aliasing but that's another matter.)
- */
-
-
-
-/*
- *  Macro to apply an 'indexed' cache instruction to the entire cache.
- *
- *  Parameters:
- *      cainst          instruction/ that takes an address register parameter
- *                      and an offset parameter (in range 0 .. 3*linesize).
- *      size            size of cache in bytes
- *      linesize        size of cache line in bytes
- *      assoc_or1       number of associativities (ways/sets) in cache
- *                      if all sets affected by cainst,
- *                      or 1 if only one set (or not all sets) of the cache
- *                      is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
- *      aa, ab          unique address registers (temporaries)
- */
-
-        .macro  cache_index_all         cainst, size, linesize, assoc_or1, aa, ab
-
-        //  Sanity-check on cache parameters:
-        .ifne   (\size % (\linesize * \assoc_or1 * 4))
-        .err    //  cache configuration outside expected/supported range!
-        .endif
-
-        //  \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
-        movi    \aa, (\size / (\linesize * \assoc_or1 * 4))
-        // Possible improvement: need only loop if \aa > 1 ;
-        // however that particular condition is highly unlikely.
-        movi    \ab, 0          // to iterate over cache
-        floop           \aa, cachex\@
-        \cainst         \ab, 0*\linesize
-        \cainst         \ab, 1*\linesize
-        \cainst         \ab, 2*\linesize
-        \cainst         \ab, 3*\linesize
-        addi            \ab, \ab, 4*\linesize   // move to next line
-        floopend        \aa, cachex\@
-
-        .endm
-
-
-/*
- *  Macro to apply a 'hit' cache instruction to a memory region,
- *  ie. to any cache entries that cache a specified portion (region) of memory.
- *  Takes care of the unaligned cases, ie. may apply to one
- *  more cache line than $asize / lineSize if $aaddr is not aligned.
- *
- *
- *  Parameters are:
- *      cainst  instruction/macro that takes an address register parameter
- *              and an offset parameter (currently always zero)
- *              and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
- *      linesize_log2   log2(size of cache line in bytes)
- *      addr    register containing start address of region (clobbered)
- *      asize   register containing size of the region in bytes (clobbered)
- *      askew   unique register used as temporary
- *
- * !?!?! 2DO: optimization: iterate max(cache_size and \asize) / linesize
- */
-
-        .macro  cache_hit_region        cainst, linesize_log2, addr, asize, askew
-
-        //  Make \asize the number of iterations:
-        extui   \askew, \addr, 0, \linesize_log2        // get unalignment amount of \addr
-        add     \asize, \asize, \askew                  // ... and add it to \asize
-        addi    \asize, \asize, (1 << \linesize_log2) - 1       // round up!
-        srli    \asize, \asize, \linesize_log2
-
-        //  Iterate over region:
-        floopnez        \asize, cacheh\@
-        \cainst         \addr, 0
-        addi            \addr, \addr, (1 << \linesize_log2)     // move to next line
-        floopend        \asize, cacheh\@
-
-        .endm
-
-
-
-
-
-/***************************   INSTRUCTION CACHE   ***************************/
-
-
-/*
- *  Reset/initialize the instruction cache by simply invalidating it:
- *  (need to unlock first also, if cache locking implemented):
- *
- *  Parameters:
- *      aa, ab          unique address registers (temporaries)
- */
-        .macro  icache_reset    aa, ab
-        icache_unlock_all       \aa, \ab
-        icache_invalidate_all   \aa, \ab
-        .endm
-
-
-/*
- * Synchronize after an instruction cache operation,
- * to be sure everything is in sync with memory as to be
- * expected following any previous instruction cache control operations.
- *
- * Parameters are:
- *      ar      an address register (temporary) (currently unused, but may be used in future)
- */
-        .macro  icache_sync     ar
-#if XCHAL_ICACHE_SIZE > 0
-        isync
-#endif
-        .endm
-
-
-
-/*
- *  Invalidate a single line of the instruction cache.
- *  Parameters are:
- *      ar      address register that contains (virtual) address to invalidate
- *              (may get clobbered in a future implementation, but not currently)
- *      offset  (optional) offset to add to \ar to compute effective address to invalidate
- *              (note: some number of lsbits are ignored)
- */
-        .macro  icache_invalidate_line  ar, offset
-#if XCHAL_ICACHE_SIZE > 0
-        ihi     \ar, \offset            // invalidate icache line
-        /*
-         *  NOTE:  in some version of the silicon [!!!SHOULD HAVE BEEN DOCUMENTED!!!]
-         *  'ihi' doesn't work, so it had been replaced with 'iii'
-         *  (which would just invalidate more than it should,
-         *  which should be okay other than the performance hit
-         *  because cache locking did not exist in that version,
-         *  unless user somehow relies on something being cached).
-         *  [WHAT VERSION IS IT!!?!?
-         *  IS THERE ANY WAY TO TEST FOR THAT HERE, TO OUTPUT 'III' ONLY IF NEEDED!?!?].
-         *
-         *      iii     \ar, \offset
-         */
-        icache_sync     \ar
-#endif
-        .endm
-
-
-
-
-/*
- *  Invalidate instruction  cache entries that cache a specified portion of memory.
- *  Parameters are:
- *      astart  start address (register gets clobbered)
- *      asize   size of the region in bytes (register gets clobbered)
- *      ac      unique register used as temporary
- */
-        .macro  icache_invalidate_region        astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0
-        //  Instruction cache region invalidation:
-        cache_hit_region        ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
-        icache_sync     \ac
-        //  End of instruction cache region invalidation
-#endif
-        .endm
-
-
-
-/*
- *  Invalidate entire instruction cache.
- *
- *  Parameters:
- *      aa, ab          unique address registers (temporaries)
- */
-        .macro  icache_invalidate_all   aa, ab
-#if XCHAL_ICACHE_SIZE > 0
-        //  Instruction cache invalidation:
-        cache_index_all         iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab
-        icache_sync     \aa
-        //  End of instruction cache invalidation
-#endif
-        .endm
-
-
-
-/*
- *  Lock (prefetch & lock) a single line of the instruction cache.
- *
- *  Parameters are:
- *      ar      address register that contains (virtual) address to lock
- *              (may get clobbered in a future implementation, but not currently)
- *      offset  offset to add to \ar to compute effective address to lock
- *              (note: some number of lsbits are ignored)
- */
-        .macro  icache_lock_line        ar, offset
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-        ipfl    \ar, \offset    /* prefetch and lock icache line */
-        icache_sync     \ar
-#endif
-        .endm
-
-
-
-/*
- *  Lock (prefetch & lock) a specified portion of memory into the instruction cache.
- *  Parameters are:
- *      astart  start address (register gets clobbered)
- *      asize   size of the region in bytes (register gets clobbered)
- *      ac      unique register used as temporary
- */
-        .macro  icache_lock_region      astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-        //  Instruction cache region lock:
-        cache_hit_region        ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
-        icache_sync     \ac
-        //  End of instruction cache region lock
-#endif
-        .endm
-
-
-
-/*
- *  Unlock a single line of the instruction cache.
- *
- *  Parameters are:
- *      ar      address register that contains (virtual) address to unlock
- *              (may get clobbered in a future implementation, but not currently)
- *      offset  offset to add to \ar to compute effective address to unlock
- *              (note: some number of lsbits are ignored)
- */
-        .macro  icache_unlock_line      ar, offset
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-        ihu     \ar, \offset    /* unlock icache line */
-        icache_sync     \ar
-#endif
-        .endm
-
-
-
-/*
- *  Unlock a specified portion of memory from the instruction cache.
- *  Parameters are:
- *      astart  start address (register gets clobbered)
- *      asize   size of the region in bytes (register gets clobbered)
- *      ac      unique register used as temporary
- */
-        .macro  icache_unlock_region    astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-        //  Instruction cache region unlock:
-        cache_hit_region        ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
-        icache_sync     \ac
-        //  End of instruction cache region unlock
-#endif
-        .endm
-
-
-
-/*
- *  Unlock entire instruction cache.
- *
- *  Parameters:
- *      aa, ab          unique address registers (temporaries)
- */
-        .macro  icache_unlock_all       aa, ab
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-        //  Instruction cache unlock:
-        cache_index_all         iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab
-        icache_sync     \aa
-        //  End of instruction cache unlock
-#endif
-        .endm
-
-
-
-
-
-/***************************   DATA CACHE   ***************************/
-
-
-
-/*
- *  Reset/initialize the data cache by simply invalidating it
- *  (need to unlock first also, if cache locking implemented):
- *
- *  Parameters:
- *      aa, ab          unique address registers (temporaries)
- */
-        .macro  dcache_reset    aa, ab
-        dcache_unlock_all       \aa, \ab
-        dcache_invalidate_all   \aa, \ab
-        .endm
-
-
-
-
-/*
- * Synchronize after a data cache operation,
- * to be sure everything is in sync with memory as to be
- * expected following any previous data cache control operations.
- *
- * Parameters are:
- *      ar      an address register (temporary) (currently unused, but may be used in future)
- */
-        .macro  dcache_sync     ar
-#if XCHAL_DCACHE_SIZE > 0
-        //  This previous sequence errs on the conservative side (too much so); a DSYNC should be sufficient:
-        //memw          // synchronize data cache changes relative to subsequent memory accesses
-        //isync         // be conservative and ISYNC as well (just to be sure)
-
-        dsync
-#endif
-        .endm
-
-
-
-/*
- * Synchronize after a data store operation,
- * to be sure the stored data is completely off the processor
- * (and assuming there is no buffering outside the processor,
- *  that the data is in memory).  This may be required to
- * ensure that the processor's write buffers are emptied.
- * A MEMW followed by a read guarantees this, by definition.
- * We also try to make sure the read itself completes.
- *
- * Parameters are:
- *      ar      an address register (temporary)
- */
-        .macro  write_sync      ar
-        memw                    // ensure previous memory accesses are complete prior to subsequent memory accesses
-        l32i    \ar, sp, 0      // completing this read ensures any previous write has completed, because of MEMW
-        //slot
-        add     \ar, \ar, \ar   // use the result of the read to help ensure the read completes (in future architectures)
-        .endm
-
-
-/*
- *  Invalidate a single line of the data cache.
- *  Parameters are:
- *      ar      address register that contains (virtual) address to invalidate
- *              (may get clobbered in a future implementation, but not currently)
- *      offset  (optional) offset to add to \ar to compute effective address to invalidate
- *              (note: some number of lsbits are ignored)
- */
-        .macro  dcache_invalidate_line  ar, offset
-#if XCHAL_DCACHE_SIZE > 0
-        dhi     \ar, \offset
-        dcache_sync     \ar
-#endif
-        .endm
-
-
-
-
-
-/*
- *  Invalidate data cache entries that cache a specified portion of memory.
- *  Parameters are:
- *      astart  start address (register gets clobbered)
- *      asize   size of the region in bytes (register gets clobbered)
- *      ac      unique register used as temporary
- */
-        .macro  dcache_invalidate_region        astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0
-        //  Data cache region invalidation:
-        cache_hit_region        dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
-        dcache_sync     \ac
-        //  End of data cache region invalidation
-#endif
-        .endm
-
-
-
-#if 0
-/*
- *  This is a work-around for a bug in SiChip1 (???).
- *  There should be a proper mechanism for not outputting
- *  these instructions when not needed.
- *  To enable work-around, uncomment this and replace 'dii'
- *  with 'dii_s1' everywhere, eg. in dcache_invalidate_all
- *  macro below.
- */
-        .macro  dii_s1  ar, offset
-        dii     \ar, \offset
-        or      \ar, \ar, \ar
-        or      \ar, \ar, \ar
-        or      \ar, \ar, \ar
-        or      \ar, \ar, \ar
-        .endm
-#endif
-
-
-/*
- *  Invalidate entire data cache.
- *
- *  Parameters:
- *      aa, ab          unique address registers (temporaries)
- */
-        .macro  dcache_invalidate_all   aa, ab
-#if XCHAL_DCACHE_SIZE > 0
-        //  Data cache invalidation:
-        cache_index_all         dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab
-        dcache_sync     \aa
-        //  End of data cache invalidation
-#endif
-        .endm
-
-
-
-/*
- *  Writeback a single line of the data cache.
- *  Parameters are:
- *      ar      address register that contains (virtual) address to writeback
- *              (may get clobbered in a future implementation, but not currently)
- *      offset  offset to add to \ar to compute effective address to writeback
- *              (note: some number of lsbits are ignored)
- */
-        .macro  dcache_writeback_line   ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
-        dhwb    \ar, \offset
-        dcache_sync     \ar
-#endif
-        .endm
-
-
-
-/*
- *  Writeback dirty data cache entries that cache a specified portion of memory.
- *  Parameters are:
- *      astart  start address (register gets clobbered)
- *      asize   size of the region in bytes (register gets clobbered)
- *      ac      unique register used as temporary
- */
-        .macro  dcache_writeback_region         astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
-        //  Data cache region writeback:
-        cache_hit_region        dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
-        dcache_sync     \ac
-        //  End of data cache region writeback
-#endif
-        .endm
-
-
-
-/*
- *  Writeback entire data cache.
- *  Parameters:
- *      aa, ab          unique address registers (temporaries)
- */
-        .macro  dcache_writeback_all    aa, ab
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
-        //  Data cache writeback:
-        cache_index_all         diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
-        dcache_sync     \aa
-        //  End of data cache writeback
-#endif
-        .endm
-
-
-
-/*
- *  Writeback and invalidate a single line of the data cache.
- *  Parameters are:
- *      ar      address register that contains (virtual) address to writeback and invalidate
- *              (may get clobbered in a future implementation, but not currently)
- *      offset  offset to add to \ar to compute effective address to writeback and invalidate
- *              (note: some number of lsbits are ignored)
- */
-        .macro  dcache_writeback_inv_line       ar, offset
-#if XCHAL_DCACHE_SIZE > 0
-        dhwbi   \ar, \offset    /* writeback and invalidate dcache line */
-        dcache_sync     \ar
-#endif
-        .endm
-
-
-
-/*
- *  Writeback and invalidate data cache entries that cache a specified portion of memory.
- *  Parameters are:
- *      astart  start address (register gets clobbered)
- *      asize   size of the region in bytes (register gets clobbered)
- *      ac      unique register used as temporary
- */
-        .macro  dcache_writeback_inv_region     astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0
-        //  Data cache region writeback and invalidate:
-        cache_hit_region        dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
-        dcache_sync     \ac
-        //  End of data cache region writeback and invalidate
-#endif
-        .endm
-
-
-
-/*
- *  Writeback and invalidate entire data cache.
- *  Parameters:
- *      aa, ab          unique address registers (temporaries)
- */
-        .macro  dcache_writeback_inv_all        aa, ab
-#if XCHAL_DCACHE_SIZE > 0
-        //  Data cache writeback and invalidate:
-#if XCHAL_DCACHE_IS_WRITEBACK
-        cache_index_all         diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
-        dcache_sync     \aa
-#else /*writeback*/
-        //  Data cache does not support writeback, so just invalidate: */
-        dcache_invalidate_all   \aa, \ab
-#endif /*writeback*/
-        //  End of data cache writeback and invalidate
-#endif
-        .endm
-
-
-
-
-/*
- *  Lock (prefetch & lock) a single line of the data cache.
- *
- *  Parameters are:
- *      ar      address register that contains (virtual) address to lock
- *              (may get clobbered in a future implementation, but not currently)
- *      offset  offset to add to \ar to compute effective address to lock
- *              (note: some number of lsbits are ignored)
- */
-        .macro  dcache_lock_line        ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-        dpfl    \ar, \offset    /* prefetch and lock dcache line */
-        dcache_sync     \ar
-#endif
-        .endm
-
-
-
-/*
- *  Lock (prefetch & lock) a specified portion of memory into the data cache.
- *  Parameters are:
- *      astart  start address (register gets clobbered)
- *      asize   size of the region in bytes (register gets clobbered)
- *      ac      unique register used as temporary
- */
-        .macro  dcache_lock_region      astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-        //  Data cache region lock:
-        cache_hit_region        dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
-        dcache_sync     \ac
-        //  End of data cache region lock
-#endif
-        .endm
-
-
-
-/*
- *  Unlock a single line of the data cache.
- *
- *  Parameters are:
- *      ar      address register that contains (virtual) address to unlock
- *              (may get clobbered in a future implementation, but not currently)
- *      offset  offset to add to \ar to compute effective address to unlock
- *              (note: some number of lsbits are ignored)
- */
-        .macro  dcache_unlock_line      ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-        dhu     \ar, \offset    /* unlock dcache line */
-        dcache_sync     \ar
-#endif
-        .endm
-
-
-
-/*
- *  Unlock a specified portion of memory from the data cache.
- *  Parameters are:
- *      astart  start address (register gets clobbered)
- *      asize   size of the region in bytes (register gets clobbered)
- *      ac      unique register used as temporary
- */
-        .macro  dcache_unlock_region    astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-        //  Data cache region unlock:
-        cache_hit_region        dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
-        dcache_sync     \ac
-        //  End of data cache region unlock
-#endif
-        .endm
-
-
-
-/*
- *  Unlock entire data cache.
- *
- *  Parameters:
- *      aa, ab          unique address registers (temporaries)
- */
-        .macro  dcache_unlock_all       aa, ab
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-        //  Data cache unlock:
-        cache_index_all         diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
-        dcache_sync     \aa
-        //  End of data cache unlock
-#endif
-        .endm
-
-
-#endif /*XTENSA_CACHEASM_H*/
-
diff --git a/include/asm-xtensa/xtensa/cacheattrasm.h b/include/asm-xtensa/xtensa/cacheattrasm.h
deleted file mode 100644
index 1c3e117b3592..000000000000
--- a/include/asm-xtensa/xtensa/cacheattrasm.h
+++ /dev/null
@@ -1,432 +0,0 @@
-#ifndef XTENSA_CACHEATTRASM_H
-#define XTENSA_CACHEATTRASM_H
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- * include/asm-xtensa/xtensa/cacheattrasm.h -- assembler-specific
- * CACHEATTR register related definitions that depend on CORE
- * configuration.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002 Tensilica Inc.
- */
-
-
-#include <xtensa/coreasm.h>
-
-
-/*
- *  This header file defines assembler macros of the form:
- *      <x>cacheattr_<func>
- *  where:
- *      <x> is 'i', 'd' or absent for instruction, data
- *              or both caches; and
- *      <func> indicates the function of the macro.
- *
- *  The following functions are defined:
- *
- *  icacheattr_get
- *      Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
- *
- *  dcacheattr_get
- *      Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
- *      (Note:  for configs with a real CACHEATTR register, the
- *       above two macros are identical.)
- *
- *  cacheattr_set
- *      Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
- *      Works even when changing one's own code's attributes.
- *
- *  icacheattr_is_enabled  label
- *      Branches to \label if I-cache appears to have been enabled
- *      (eg. if CACHEATTR contains a cache-enabled attribute).
- *      (clobbers a2-a5,SAR)
- *
- *  dcacheattr_is_enabled  label
- *      Branches to \label if D-cache appears to have been enabled
- *      (eg. if CACHEATTR contains a cache-enabled attribute).
- *      (clobbers a2-a5,SAR)
- *
- *  cacheattr_is_enabled  label
- *      Branches to \label if either I-cache or D-cache appears to have been enabled
- *      (eg. if CACHEATTR contains a cache-enabled attribute).
- *      (clobbers a2-a5,SAR)
- *
- *  The following macros are only defined under certain conditions:
- *
- *  icacheattr_set      (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
- *      Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
- *
- *  dcacheattr_set      (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
- *      Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
- */
-
-
-
-/***************************   GENERIC -- ALL CACHES   ***************************/
-
-/*
- *  _cacheattr_get
- *
- *  (Internal macro.)
- *  Returns value of CACHEATTR register (or closest equivalent) in a2.
- *
- *  Entry:
- *      (none)
- *  Exit:
- *      a2      value read from CACHEATTR
- *      a3-a5   clobbered (temporaries)
- */
-        .macro  _cacheattr_get  tlb
-#if XCHAL_HAVE_CACHEATTR
-        rsr     a2, CACHEATTR
-#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-        //  We have a config that "mimics" CACHEATTR using a simplified
-        //  "MMU" composed of a single statically-mapped way.
-        //  DTLB and ITLB are independent, so there's no single
-        //  cache attribute that can describe both.  So for now
-        //  just return the DTLB state.
-        movi    a5, 0xE0000000
-        movi    a2, 0
-        movi    a3, 0
-1:      add     a3, a3, a5      // next segment
-        r&tlb&1 a4, a3          // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
-        dsync   // interlock???
-        slli    a2, a2, 4
-        extui   a4, a4, 0, 4    // extract CA
-        or      a2, a2, a4
-        bnez    a3, 1b
-#else
-        //  This macro isn't applicable to arbitrary MMU configurations.
-        //  Just return zero.
-        movi    a2, 0
-#endif
-        .endm
-
-        .macro  icacheattr_get
-        _cacheattr_get  itlb
-        .endm
-
-        .macro  dcacheattr_get
-        _cacheattr_get  dtlb
-        .endm
-
-
-#define XCHAL_CACHEATTR_ALL_BYPASS      0x22222222      /* default (powerup/reset) value of CACHEATTR, all BYPASS
-                                                           mode (ie. disabled/bypassed caches) */
-
-#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-
-#define XCHAL_FCA_ENAMASK       0x001A  /* bitmap of fetch attributes that require enabled icache */
-#define XCHAL_LCA_ENAMASK       0x0003  /* bitmap of load  attributes that require enabled dcache */
-#define XCHAL_SCA_ENAMASK       0x0003  /* bitmap of store attributes that require enabled dcache */
-#define XCHAL_LSCA_ENAMASK      (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK)   /* l/s attrs requiring enabled dcache */
-#define XCHAL_ALLCA_ENAMASK     (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK)  /* all attrs requiring enabled caches */
-
-/*
- *  _cacheattr_is_enabled
- *
- *  (Internal macro.)
- *  Branches to \label if CACHEATTR in a2 indicates an enabled
- *  cache, using mask in a3.
- *
- *  Parameters:
- *      label   where to branch to if cache is enabled
- *  Entry:
- *      a2      contains CACHEATTR value used to determine whether
- *              caches are enabled
- *      a3      16-bit constant where each bit correspond to
- *              one of the 16 possible CA values (in a CACHEATTR mask);
- *              CA values that indicate the cache is enabled
- *              have their corresponding bit set in this mask
- *              (eg. use XCHAL_xCA_ENAMASK , above)
- *  Exit:
- *      a2,a4,a5        clobbered
- *      SAR             clobbered
- */
-        .macro  _cacheattr_is_enabled   label
-        movi    a4, 8           // loop 8 times
-.Lcaife\@:
-        extui   a5, a2, 0, 4    // get CA nibble
-        ssr     a5              // index into mask according to CA...
-        srl     a5, a3          // ...and get CA's mask bit in a5 bit 0
-        bbsi.l  a5, 0, \label   // if CA indicates cache enabled, jump to label
-        srli    a2, a2, 4       // next nibble
-        addi    a4, a4, -1
-        bnez    a4, .Lcaife\@   // loop for each nibble
-        .endm
-
-#else /* XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
-        .macro  _cacheattr_is_enabled   label
-        j       \label          // macro not applicable, assume caches always enabled
-        .endm
-#endif /* XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
-
-
-
-/*
- *  icacheattr_is_enabled
- *
- *  Branches to \label if I-cache is enabled.
- *
- *  Parameters:
- *      label   where to branch to if icache is enabled
- *  Entry:
- *      (none)
- *  Exit:
- *      a2-a5, SAR      clobbered (temporaries)
- */
-        .macro  icacheattr_is_enabled   label
-#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-        icacheattr_get
-        movi    a3, XCHAL_FCA_ENAMASK
-#endif
-        _cacheattr_is_enabled   \label
-        .endm
-
-/*
- *  dcacheattr_is_enabled
- *
- *  Branches to \label if D-cache is enabled.
- *
- *  Parameters:
- *      label   where to branch to if dcache is enabled
- *  Entry:
- *      (none)
- *  Exit:
- *      a2-a5, SAR      clobbered (temporaries)
- */
-        .macro  dcacheattr_is_enabled   label
-#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-        dcacheattr_get
-        movi    a3, XCHAL_LSCA_ENAMASK
-#endif
-        _cacheattr_is_enabled   \label
-        .endm
-
-/*
- *  cacheattr_is_enabled
- *
- *  Branches to \label if either I-cache or D-cache is enabled.
- *
- *  Parameters:
- *      label   where to branch to if a cache is enabled
- *  Entry:
- *      (none)
- *  Exit:
- *      a2-a5, SAR      clobbered (temporaries)
- */
-        .macro  cacheattr_is_enabled    label
-#if XCHAL_HAVE_CACHEATTR
-        rsr     a2, CACHEATTR
-        movi    a3, XCHAL_ALLCA_ENAMASK
-#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-        icacheattr_get
-        movi    a3, XCHAL_FCA_ENAMASK
-        _cacheattr_is_enabled   \label
-        dcacheattr_get
-        movi    a3, XCHAL_LSCA_ENAMASK
-#endif
-        _cacheattr_is_enabled   \label
-        .endm
-
-
-
-/*
- *  The ISA does not have a defined way to change the
- *  instruction cache attributes of the running code,
- *  ie. of the memory area that encloses the current PC.
- *  However, each micro-architecture (or class of
- *  configurations within a micro-architecture)
- *  provides a way to deal with this issue.
- *
- *  Here are a few macros used to implement the relevant
- *  approach taken.
- */
-
-#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-        //  We have a config that "mimics" CACHEATTR using a simplified
-        //  "MMU" composed of a single statically-mapped way.
-
-/*
- *  icacheattr_set
- *
- *  Entry:
- *      a2              cacheattr value to set
- *  Exit:
- *      a2              unchanged
- *      a3-a8           clobbered (temporaries)
- */
-        .macro  icacheattr_set
-
-        movi    a5, 0xE0000000  // mask of upper 3 bits
-        movi    a6, 3f          // PC where ITLB is set
-        movi    a3, 0           // start at region 0 (0 .. 7)
-        and     a6, a6, a5      // upper 3 bits of local PC area
-        mov     a7, a2          // copy a2 so it doesn't get clobbered
-        j       3f
-
-# if XCHAL_HAVE_XLT_CACHEATTR
-        //  Can do translations, use generic method:
-1:      sub     a6, a3, a5      // address of some other segment
-        ritlb1  a8, a6          // save its PPN+CA
-        dsync   // interlock??
-        witlb   a4, a6          // make it translate to this code area
-        movi    a6, 5f          // where to jump into it
-        isync
-        sub     a6, a6, a5      // adjust jump address within that other segment
-        jx      a6
-
-        //  Note that in the following code snippet, which runs at a different virtual
-        //  address than it is assembled for, we avoid using literals (eg. via movi/l32r)
-        //  just in case literals end up in a different 512 MB segment, and we avoid
-        //  instructions that rely on the current PC being what is expected.
-        //
-        .align  4
-        _j      6f              // this is at label '5' minus 4 bytes
-        .align  4
-5:      witlb   a4, a3          // we're in other segment, now can write previous segment's CA
-        isync
-        add     a6, a6, a5      // back to previous segment
-        addi    a6, a6, -4      // next jump label
-        jx      a6
-
-6:      sub     a6, a3, a5      // address of some other segment
-        witlb   a8, a6          // restore PPN+CA of other segment
-        mov     a6, a3          // restore a6
-        isync
-# else /* XCHAL_HAVE_XLT_CACHEATTR */
-        //  Use micro-architecture specific method.
-        //  The following 4-instruction sequence is aligned such that
-        //  it all fits within a single I-cache line.  Sixteen byte
-        //  alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
-        //  actually causes problems because that can be greater than
-        //  the alignment of the reset vector, where this macro is often
-        //  invoked, which would cause the linker to align the reset
-        //  vector code away from the reset vector!!).
-        .align  16 /*XCHAL_ICACHE_LINESIZE*/
-1:      _witlb  a4, a3          // write wired PTE (CA, no PPN) of 512MB segment to ITLB
-        _isync
-        nop
-        nop
-# endif /* XCHAL_HAVE_XLT_CACHEATTR */
-        beq     a3, a5, 4f      // done?
-
-        //  Note that in the WITLB loop, we don't do any load/stores
-        //  (may not be an issue here, but it is important in the DTLB case).
-2:      srli    a7, a7, 4       // next CA
-        sub     a3, a3, a5      // next segment (add 0x20000000)
-3:
-# if XCHAL_HAVE_XLT_CACHEATTR   /* if have translation, preserve it */
-        ritlb1  a8, a3          // get current PPN+CA of segment
-        dsync   // interlock???
-        extui   a4, a7, 0, 4    // extract CA to set
-        srli    a8, a8, 4       // clear CA but keep PPN ...
-        slli    a8, a8, 4       // ...
-        add     a4, a4, a8      // combine new CA with PPN to preserve
-# else
-        extui   a4, a7, 0, 4    // extract CA
-# endif
-        beq     a3, a6, 1b      // current PC's region? if so, do it in a safe way
-        witlb   a4, a3          // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
-        bne     a3, a5, 2b
-        isync                   // make sure all ifetch changes take effect
-4:
-        .endm   // icacheattr_set
-
-
-/*
- *  dcacheattr_set
- *
- *  Entry:
- *      a2              cacheattr value to set
- *  Exit:
- *      a2              unchanged
- *      a3-a8           clobbered (temporaries)
- */
-
-        .macro  dcacheattr_set
-
-        movi    a5, 0xE0000000  // mask of upper 3 bits
-        movi    a3, 0           // start at region 0 (0 .. 7)
-        mov     a7, a2          // copy a2 so it doesn't get clobbered
-        j       3f
-        //  Note that in the WDTLB loop, we don't do any load/stores
-        //  (including implicit l32r via movi) because it isn't safe.
-2:      srli    a7, a7, 4       // next CA
-        sub     a3, a3, a5      // next segment (add 0x20000000)
-3:
-# if XCHAL_HAVE_XLT_CACHEATTR   /* if have translation, preserve it */
-        rdtlb1  a8, a3          // get current PPN+CA of segment
-        dsync   // interlock???
-        extui   a4, a7, 0, 4    // extract CA to set
-        srli    a8, a8, 4       // clear CA but keep PPN ...
-        slli    a8, a8, 4       // ...
-        add     a4, a4, a8      // combine new CA with PPN to preserve
-# else
-        extui   a4, a7, 0, 4    // extract CA to set
-# endif
-        wdtlb   a4, a3          // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
-        bne     a3, a5, 2b
-        dsync                   // make sure all data path changes take effect
-        .endm   // dcacheattr_set
-
-#endif /* XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
-
-
-
-/*
- *  cacheattr_set
- *
- *  Macro that sets the current CACHEATTR safely
- *  (both i and d) according to the current contents of a2.
- *  It works even when changing the cache attributes of
- *  the currently running code.
- *
- *  Entry:
- *      a2              cacheattr value to set
- *  Exit:
- *      a2              unchanged
- *      a3-a8           clobbered (temporaries)
- */
-        .macro  cacheattr_set
-
-#if XCHAL_HAVE_CACHEATTR
-# if XCHAL_ICACHE_LINESIZE < 4
-        //  No i-cache, so can always safely write to CACHEATTR:
-        wsr     a2, CACHEATTR
-# else
-        //  The Athens micro-architecture, when using the old
-        //  exception architecture option (ie. with the CACHEATTR register)
-        //  allows changing the cache attributes of the running code
-        //  using the following exact sequence aligned to be within
-        //  an instruction cache line.  (NOTE: using XCHAL_ICACHE_LINESIZE
-        //  alignment actually causes problems because that can be greater
-        //  than the alignment of the reset vector, where this macro is often
-        //  invoked, which would cause the linker to align the reset
-        //  vector code away from the reset vector!!).
-        j       1f
-        .align  16 /*XCHAL_ICACHE_LINESIZE*/    // align to within an I-cache line
-1:      _wsr    a2, CACHEATTR
-        _isync
-        nop
-        nop
-# endif
-#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-        //  DTLB and ITLB are independent, but to keep semantics
-        //  of this macro we simply write to both.
-        icacheattr_set
-        dcacheattr_set
-#else
-        //  This macro isn't applicable to arbitrary MMU configurations.
-        //  Do nothing in this case.
-#endif
-        .endm
-
-
-#endif /*XTENSA_CACHEATTRASM_H*/
-
diff --git a/include/asm-xtensa/xtensa/config-linux_be/core.h b/include/asm-xtensa/xtensa/config-linux_be/core.h
deleted file mode 100644
index d54fe5eb1064..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/core.h
+++ /dev/null
@@ -1,1270 +0,0 @@
-/*
- * xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
- *
- *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
- *  It was generated for a specific Xtensa processor configuration.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  It is perfectly normal, however, for the HAL source itself to include this file.
- */
-
-/*
- * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2.1 of the GNU Lesser General Public
- * License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it would be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Further, this software is distributed without any warranty that it is
- * free of the rightful claim of any third person regarding infringement
- * or the like.  Any license provided herein, whether implied or
- * otherwise, applies only to this software file.  Patent licenses, if
- * any, provided herein do not apply to combinations of this program with
- * other software, or any other product whatsoever.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this program; if not, write the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
- * USA.
- */
-
-
-#ifndef XTENSA_CONFIG_CORE_H
-#define XTENSA_CONFIG_CORE_H
-
-#include <xtensa/hal.h>
-
-
-/*----------------------------------------------------------------------
-                                GENERAL
-  ----------------------------------------------------------------------*/
-
-/*
- *  Separators for macros that expand into arrays.
- *  These can be predefined by files that #include this one,
- *  when different separators are required.
- */
-/*  Element separator for macros that expand into 1-dimensional arrays:  */
-#ifndef XCHAL_SEP
-#define XCHAL_SEP                       ,
-#endif
-/*  Array separator for macros that expand into 2-dimensional arrays:  */
-#ifndef XCHAL_SEP2
-#define XCHAL_SEP2                      },{
-#endif
-
-
-/*----------------------------------------------------------------------
-                                ENDIANNESS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE                   1
-#define XCHAL_HAVE_LE                   0
-#define XCHAL_MEMORY_ORDER              XTHAL_BIGENDIAN
-
-
-/*----------------------------------------------------------------------
-                                REGISTER WINDOWS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_WINDOWED             1       /* 1 if windowed registers option configured, 0 otherwise */
-#define XCHAL_NUM_AREGS                 64      /* number of physical address regs */
-#define XCHAL_NUM_AREGS_LOG2            6       /* log2(XCHAL_NUM_AREGS) */
-
-
-/*----------------------------------------------------------------------
-                                ADDRESS ALIGNMENT
-  ----------------------------------------------------------------------*/
-
-/*  These apply to a selected set of core load and store instructions only (see ISA):  */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION  1       /* 1 if unaligned loads cause an exception, 0 otherwise */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION 1       /* 1 if unaligned stores cause an exception, 0 otherwise */
-
-
-/*----------------------------------------------------------------------
-                                INTERRUPTS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS           1       /* 1 if interrupt option configured, 0 otherwise */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS   1       /* 1 if high-priority interrupt option configured, 0 otherwise */
-#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
-#define XCHAL_HAVE_NMI                  0       /* 1 if NMI option configured, 0 otherwise */
-#define XCHAL_NUM_INTERRUPTS            17      /* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2       5       /* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
-#define XCHAL_NUM_EXTINTERRUPTS         10      /* number of external interrupts */
-#define XCHAL_NUM_INTLEVELS             4       /* number of interrupt levels (not including level zero!) */
-#define XCHAL_NUM_LOWPRI_LEVELS         1                       /* number of low-priority interrupt levels (always 1) */
-#define XCHAL_FIRST_HIGHPRI_LEVEL       (XCHAL_NUM_LOWPRI_LEVELS+1)     /* level of first high-priority interrupt (always 2) */
-#define XCHAL_EXCM_LEVEL                1                       /* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
-                                                                   for XEA1, where there is no PS.EXCM, this is always 1;
-                                                                   interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
-                                                                   are termed "medium priority" interrupts (post T10xx only) */
-/*  Note:  1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15  */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL0_MASK            0x00000000
-#define XCHAL_INTLEVEL1_MASK            0x000064F9
-#define XCHAL_INTLEVEL2_MASK            0x00008902
-#define XCHAL_INTLEVEL3_MASK            0x00011204
-#define XCHAL_INTLEVEL4_MASK            0x00000000
-#define XCHAL_INTLEVEL5_MASK            0x00000000
-#define XCHAL_INTLEVEL6_MASK            0x00000000
-#define XCHAL_INTLEVEL7_MASK            0x00000000
-#define XCHAL_INTLEVEL8_MASK            0x00000000
-#define XCHAL_INTLEVEL9_MASK            0x00000000
-#define XCHAL_INTLEVEL10_MASK           0x00000000
-#define XCHAL_INTLEVEL11_MASK           0x00000000
-#define XCHAL_INTLEVEL12_MASK           0x00000000
-#define XCHAL_INTLEVEL13_MASK           0x00000000
-#define XCHAL_INTLEVEL14_MASK           0x00000000
-#define XCHAL_INTLEVEL15_MASK           0x00000000
-/*  As an array of entries (eg. for C constant arrays):  */
-#define XCHAL_INTLEVEL_MASKS            0x00000000      XCHAL_SEP \
-                                        0x000064F9      XCHAL_SEP \
-                                        0x00008902      XCHAL_SEP \
-                                        0x00011204      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000      XCHAL_SEP \
-                                        0x00000000
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL0_ANDBELOW_MASK   0x00000000
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK   0x000064F9
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK   0x0000EDFB
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK   0x0001FFFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK   0x0001FFFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK   0x0001FFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK   0x0001FFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK   0x0001FFFF
-#define XCHAL_INTLEVEL8_ANDBELOW_MASK   0x0001FFFF
-#define XCHAL_INTLEVEL9_ANDBELOW_MASK   0x0001FFFF
-#define XCHAL_INTLEVEL10_ANDBELOW_MASK  0x0001FFFF
-#define XCHAL_INTLEVEL11_ANDBELOW_MASK  0x0001FFFF
-#define XCHAL_INTLEVEL12_ANDBELOW_MASK  0x0001FFFF
-#define XCHAL_INTLEVEL13_ANDBELOW_MASK  0x0001FFFF
-#define XCHAL_INTLEVEL14_ANDBELOW_MASK  0x0001FFFF
-#define XCHAL_INTLEVEL15_ANDBELOW_MASK  0x0001FFFF
-#define XCHAL_LOWPRI_MASK               XCHAL_INTLEVEL1_ANDBELOW_MASK   /* mask of all low-priority interrupts */
-#define XCHAL_EXCM_MASK                 XCHAL_INTLEVEL1_ANDBELOW_MASK   /* mask of all interrupts masked by PS.EXCM (or CEXCM) */
-/*  As an array of entries (eg. for C constant arrays):  */
-#define XCHAL_INTLEVEL_ANDBELOW_MASKS   0x00000000      XCHAL_SEP \
-                                        0x000064F9      XCHAL_SEP \
-                                        0x0000EDFB      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF      XCHAL_SEP \
-                                        0x0001FFFF
-
-/*  Interrupt numbers for each interrupt level at which only one interrupt was configured:  */
-/*#define XCHAL_INTLEVEL1_NUM           ...more than one interrupt at this level...*/
-/*#define XCHAL_INTLEVEL2_NUM           ...more than one interrupt at this level...*/
-/*#define XCHAL_INTLEVEL3_NUM           ...more than one interrupt at this level...*/
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL                1
-#define XCHAL_INT1_LEVEL                2
-#define XCHAL_INT2_LEVEL                3
-#define XCHAL_INT3_LEVEL                1
-#define XCHAL_INT4_LEVEL                1
-#define XCHAL_INT5_LEVEL                1
-#define XCHAL_INT6_LEVEL                1
-#define XCHAL_INT7_LEVEL                1
-#define XCHAL_INT8_LEVEL                2
-#define XCHAL_INT9_LEVEL                3
-#define XCHAL_INT10_LEVEL               1
-#define XCHAL_INT11_LEVEL               2
-#define XCHAL_INT12_LEVEL               3
-#define XCHAL_INT13_LEVEL               1
-#define XCHAL_INT14_LEVEL               1
-#define XCHAL_INT15_LEVEL               2
-#define XCHAL_INT16_LEVEL               3
-#define XCHAL_INT17_LEVEL               0
-#define XCHAL_INT18_LEVEL               0
-#define XCHAL_INT19_LEVEL               0
-#define XCHAL_INT20_LEVEL               0
-#define XCHAL_INT21_LEVEL               0
-#define XCHAL_INT22_LEVEL               0
-#define XCHAL_INT23_LEVEL               0
-#define XCHAL_INT24_LEVEL               0
-#define XCHAL_INT25_LEVEL               0
-#define XCHAL_INT26_LEVEL               0
-#define XCHAL_INT27_LEVEL               0
-#define XCHAL_INT28_LEVEL               0
-#define XCHAL_INT29_LEVEL               0
-#define XCHAL_INT30_LEVEL               0
-#define XCHAL_INT31_LEVEL               0
-/*  As an array of entries (eg. for C constant arrays):  */
-#define XCHAL_INT_LEVELS                1       XCHAL_SEP \
-                                        2       XCHAL_SEP \
-                                        3       XCHAL_SEP \
-                                        1       XCHAL_SEP \
-                                        1       XCHAL_SEP \
-                                        1       XCHAL_SEP \
-                                        1       XCHAL_SEP \
-                                        1       XCHAL_SEP \
-                                        2       XCHAL_SEP \
-                                        3       XCHAL_SEP \
-                                        1       XCHAL_SEP \
-                                        2       XCHAL_SEP \
-                                        3       XCHAL_SEP \
-                                        1       XCHAL_SEP \
-                                        1       XCHAL_SEP \
-                                        2       XCHAL_SEP \
-                                        3       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0       XCHAL_SEP \
-                                        0
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT7_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT8_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT9_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT10_TYPE        XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE        XTHAL_INTTYPE_TIMER
-#define XCHAL_INT12_TYPE        XTHAL_INTTYPE_TIMER
-#define XCHAL_INT13_TYPE        XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT14_TYPE        XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT15_TYPE        XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT16_TYPE        XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT17_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT18_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT19_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT20_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT21_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT22_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT23_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT24_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT25_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT26_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT27_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT28_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT29_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT30_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-#define XCHAL_INT31_TYPE        XTHAL_INTTYPE_UNCONFIGURED
-/*  As an array of entries (eg. for C constant arrays):  */
-#define XCHAL_INT_TYPES         XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_EDGE       XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_EDGE       XCHAL_SEP \
-                                XTHAL_INTTYPE_EXTERN_EDGE       XCHAL_SEP \
-                                XTHAL_INTTYPE_TIMER             XCHAL_SEP \
-                                XTHAL_INTTYPE_TIMER             XCHAL_SEP \
-                                XTHAL_INTTYPE_TIMER             XCHAL_SEP \
-                                XTHAL_INTTYPE_SOFTWARE          XCHAL_SEP \
-                                XTHAL_INTTYPE_SOFTWARE          XCHAL_SEP \
-                                XTHAL_INTTYPE_SOFTWARE          XCHAL_SEP \
-                                XTHAL_INTTYPE_SOFTWARE          XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
-                                XTHAL_INTTYPE_UNCONFIGURED
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
-#define XCHAL_INTTYPE_MASK_SOFTWARE     0x0001E000
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE  0x00000380
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
-#define XCHAL_INTTYPE_MASK_TIMER        0x00001C00
-#define XCHAL_INTTYPE_MASK_NMI          0x00000000
-/*  As an array of entries (eg. for C constant arrays):  */
-#define XCHAL_INTTYPE_MASKS             0xFFFE0000      XCHAL_SEP \
-                                        0x0001E000      XCHAL_SEP \
-                                        0x00000380      XCHAL_SEP \
-                                        0x0000007F      XCHAL_SEP \
-                                        0x00001C00      XCHAL_SEP \
-                                        0x00000000
-
-/*  Interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned  */
-#define XCHAL_TIMER0_INTERRUPT  10
-#define XCHAL_TIMER1_INTERRUPT  11
-#define XCHAL_TIMER2_INTERRUPT  12
-#define XCHAL_TIMER3_INTERRUPT  XTHAL_TIMER_UNCONFIGURED
-/*  As an array of entries (eg. for C constant arrays):  */
-#define XCHAL_TIMER_INTERRUPTS  10      XCHAL_SEP \
-                                11      XCHAL_SEP \
-                                12      XCHAL_SEP \
-                                XTHAL_TIMER_UNCONFIGURED
-
-/*  Indexing macros:  */
-#define _XCHAL_INTLEVEL_MASK(n)         XCHAL_INTLEVEL ## n ## _MASK
-#define XCHAL_INTLEVEL_MASK(n)          _XCHAL_INTLEVEL_MASK(n)         /* n = 0 .. 15 */
-#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
-#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
-#define _XCHAL_INT_LEVEL(n)             XCHAL_INT ## n ## _LEVEL
-#define XCHAL_INT_LEVEL(n)              _XCHAL_INT_LEVEL(n)             /* n = 0 .. 31 */
-#define _XCHAL_INT_TYPE(n)              XCHAL_INT ## n ## _TYPE
-#define XCHAL_INT_TYPE(n)               _XCHAL_INT_TYPE(n)              /* n = 0 .. 31 */
-#define _XCHAL_TIMER_INTERRUPT(n)       XCHAL_TIMER ## n ## _INTERRUPT
-#define XCHAL_TIMER_INTERRUPT(n)        _XCHAL_TIMER_INTERRUPT(n)       /* n = 0 .. 3 */
-
-
-
-/*
- *  External interrupt vectors/levels.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
-#define XCHAL_EXTINT0_NUM               0       /* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM               1       /* (intlevel 2) */
-#define XCHAL_EXTINT2_NUM               2       /* (intlevel 3) */
-#define XCHAL_EXTINT3_NUM               3       /* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM               4       /* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM               5       /* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM               6       /* (intlevel 1) */
-#define XCHAL_EXTINT7_NUM               7       /* (intlevel 1) */
-#define XCHAL_EXTINT8_NUM               8       /* (intlevel 2) */
-#define XCHAL_EXTINT9_NUM               9       /* (intlevel 3) */
-
-/*  Corresponding interrupt masks:  */
-#define XCHAL_EXTINT0_MASK              0x00000001
-#define XCHAL_EXTINT1_MASK              0x00000002
-#define XCHAL_EXTINT2_MASK              0x00000004
-#define XCHAL_EXTINT3_MASK              0x00000008
-#define XCHAL_EXTINT4_MASK              0x00000010
-#define XCHAL_EXTINT5_MASK              0x00000020
-#define XCHAL_EXTINT6_MASK              0x00000040
-#define XCHAL_EXTINT7_MASK              0x00000080
-#define XCHAL_EXTINT8_MASK              0x00000100
-#define XCHAL_EXTINT9_MASK              0x00000200
-
-/*  Core config interrupt levels mapped to each external interrupt:  */
-#define XCHAL_EXTINT0_LEVEL             1       /* (int number 0) */
-#define XCHAL_EXTINT1_LEVEL             2       /* (int number 1) */
-#define XCHAL_EXTINT2_LEVEL             3       /* (int number 2) */
-#define XCHAL_EXTINT3_LEVEL             1       /* (int number 3) */
-#define XCHAL_EXTINT4_LEVEL             1       /* (int number 4) */
-#define XCHAL_EXTINT5_LEVEL             1       /* (int number 5) */
-#define XCHAL_EXTINT6_LEVEL             1       /* (int number 6) */
-#define XCHAL_EXTINT7_LEVEL             1       /* (int number 7) */
-#define XCHAL_EXTINT8_LEVEL             2       /* (int number 8) */
-#define XCHAL_EXTINT9_LEVEL             3       /* (int number 9) */
-
-
-/*----------------------------------------------------------------------
-                        EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_EXCEPTIONS           1       /* 1 if exception option configured, 0 otherwise */
-
-#define XCHAL_XEA_VERSION               2       /* Xtensa Exception Architecture number: 1 for XEA1 (old), 2 for XEA2 (new) */
-#define XCHAL_HAVE_XEA1                 0       /* 1 if XEA1, 0 otherwise */
-#define XCHAL_HAVE_XEA2                 1       /* 1 if XEA2, 0 otherwise */
-/*  For backward compatibility ONLY -- DO NOT USE (will be removed in future release):  */
-#define XCHAL_HAVE_OLD_EXC_ARCH         XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
-#define XCHAL_HAVE_EXCM                 XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
-
-#define XCHAL_RESET_VECTOR_VADDR        0xFE000020
-#define XCHAL_RESET_VECTOR_PADDR        0xFE000020
-#define XCHAL_USER_VECTOR_VADDR         0xD0000220
-#define XCHAL_PROGRAMEXC_VECTOR_VADDR   XCHAL_USER_VECTOR_VADDR         /* for backward compatibility */
-#define XCHAL_USEREXC_VECTOR_VADDR      XCHAL_USER_VECTOR_VADDR         /* for backward compatibility */
-#define XCHAL_USER_VECTOR_PADDR         0x00000220
-#define XCHAL_PROGRAMEXC_VECTOR_PADDR   XCHAL_USER_VECTOR_PADDR         /* for backward compatibility */
-#define XCHAL_USEREXC_VECTOR_PADDR      XCHAL_USER_VECTOR_PADDR         /* for backward compatibility */
-#define XCHAL_KERNEL_VECTOR_VADDR       0xD0000200
-#define XCHAL_STACKEDEXC_VECTOR_VADDR   XCHAL_KERNEL_VECTOR_VADDR       /* for backward compatibility */
-#define XCHAL_KERNELEXC_VECTOR_VADDR    XCHAL_KERNEL_VECTOR_VADDR       /* for backward compatibility */
-#define XCHAL_KERNEL_VECTOR_PADDR       0x00000200
-#define XCHAL_STACKEDEXC_VECTOR_PADDR   XCHAL_KERNEL_VECTOR_PADDR       /* for backward compatibility */
-#define XCHAL_KERNELEXC_VECTOR_PADDR    XCHAL_KERNEL_VECTOR_PADDR       /* for backward compatibility */
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR    0xD0000290
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR    0x00000290
-#define XCHAL_WINDOW_VECTORS_VADDR      0xD0000000
-#define XCHAL_WINDOW_VECTORS_PADDR      0x00000000
-#define XCHAL_INTLEVEL2_VECTOR_VADDR    0xD0000240
-#define XCHAL_INTLEVEL2_VECTOR_PADDR    0x00000240
-#define XCHAL_INTLEVEL3_VECTOR_VADDR    0xD0000250
-#define XCHAL_INTLEVEL3_VECTOR_PADDR    0x00000250
-#define XCHAL_INTLEVEL4_VECTOR_VADDR    0xFE000520
-#define XCHAL_INTLEVEL4_VECTOR_PADDR    0xFE000520
-#define XCHAL_DEBUG_VECTOR_VADDR        XCHAL_INTLEVEL4_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR        XCHAL_INTLEVEL4_VECTOR_PADDR
-
-/*  Indexing macros:  */
-#define _XCHAL_INTLEVEL_VECTOR_VADDR(n)         XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
-#define XCHAL_INTLEVEL_VECTOR_VADDR(n)          _XCHAL_INTLEVEL_VECTOR_VADDR(n)         /* n = 0 .. 15 */
-
-/*
- *  General Exception Causes
- *  (values of EXCCAUSE special register set by general exceptions,
- *   which vector to the user, kernel, or double-exception vectors):
- */
-#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION              0       /* Illegal Instruction (IllegalInstruction) */
-#define XCHAL_EXCCAUSE_SYSTEM_CALL                      1       /* System Call (SystemCall) */
-#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR          2       /* Instruction Fetch Error (InstructionFetchError) */
-#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR                 3       /* Load Store Error (LoadStoreError) */
-#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT                 4       /* Level 1 Interrupt (Level1Interrupt) */
-#define XCHAL_EXCCAUSE_ALLOCA                           5       /* Stack Extension Assist (Alloca) */
-#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO           6       /* Integer Divide by Zero (IntegerDivideByZero) */
-#define XCHAL_EXCCAUSE_SPECULATION                      7       /* Speculation (Speculation) */
-#define XCHAL_EXCCAUSE_PRIVILEGED                       8       /* Privileged Instruction (Privileged) */
-#define XCHAL_EXCCAUSE_UNALIGNED                        9       /* Unaligned Load Store (Unaligned) */
-#define XCHAL_EXCCAUSE_ITLB_MISS                        16      /* ITlb Miss Exception (ITlbMiss) */
-#define XCHAL_EXCCAUSE_ITLB_MULTIHIT                    17      /* ITlb Mutltihit Exception (ITlbMultihit) */
-#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE                   18      /* ITlb Privilege Exception (ITlbPrivilege) */
-#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION            19      /* ITlb Size Restriction Exception (ITlbSizeRestriction) */
-#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE            20      /* Fetch Cache Attribute Exception (FetchCacheAttribute) */
-#define XCHAL_EXCCAUSE_DTLB_MISS                        24      /* DTlb Miss Exception (DTlbMiss) */
-#define XCHAL_EXCCAUSE_DTLB_MULTIHIT                    25      /* DTlb Multihit Exception (DTlbMultihit) */
-#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE                   26      /* DTlb Privilege Exception (DTlbPrivilege) */
-#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION            27      /* DTlb Size Restriction Exception (DTlbSizeRestriction) */
-#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE             28      /* Load Cache Attribute Exception (LoadCacheAttribute) */
-#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE            29      /* Store Cache Attribute Exception (StoreCacheAttribute) */
-#define XCHAL_EXCCAUSE_FLOATING_POINT                   40      /* Floating Point Exception (FloatingPoint) */
-
-
-
-/*----------------------------------------------------------------------
-                                TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_CCOUNT               1       /* 1 if have CCOUNT, 0 otherwise */
-/*#define XCHAL_HAVE_TIMERS             XCHAL_HAVE_CCOUNT*/
-#define XCHAL_NUM_TIMERS                3       /* number of CCOMPAREn regs */
-
-
-
-/*----------------------------------------------------------------------
-                                DEBUG
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_DEBUG                1       /* 1 if debug option configured, 0 otherwise */
-#define XCHAL_HAVE_OCD                  1       /* 1 if OnChipDebug option configured, 0 otherwise */
-#define XCHAL_NUM_IBREAK                2       /* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK                2       /* number of DBREAKn regs */
-#define XCHAL_DEBUGLEVEL                4       /* debug interrupt level */
-/*DebugExternalInterrupt                0               0|1*/
-/*DebugUseDIRArray                      0               0|1*/
-
-
-
-
-/*----------------------------------------------------------------------
-                        COPROCESSORS and EXTRA STATE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_CP                   0       /* 1 if coprocessor option configured (CPENABLE present) */
-#define XCHAL_CP_MAXCFG                 0       /* max allowed cp id plus one (per cfg) */
-
-#include <xtensa/config/tie.h>
-
-
-
-
-/*----------------------------------------------------------------------
-                        INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM               0       /* number of core instruction ROMs configured */
-#define XCHAL_NUM_INSTRAM               0       /* number of core instruction RAMs configured */
-#define XCHAL_NUM_DATAROM               0       /* number of core data ROMs configured */
-#define XCHAL_NUM_DATARAM               0       /* number of core data RAMs configured */
-#define XCHAL_NUM_XLMI                  0       /* number of core XLMI ports configured */
-#define  XCHAL_NUM_IROM                 XCHAL_NUM_INSTROM       /* (DEPRECATED) */
-#define  XCHAL_NUM_IRAM                 XCHAL_NUM_INSTRAM       /* (DEPRECATED) */
-#define  XCHAL_NUM_DROM                 XCHAL_NUM_DATAROM       /* (DEPRECATED) */
-#define  XCHAL_NUM_DRAM                 XCHAL_NUM_DATARAM       /* (DEPRECATED) */
-
-
-
-/*----------------------------------------------------------------------
-                                CACHE
-  ----------------------------------------------------------------------*/
-
-/*  Size of the cache lines in log2(bytes):  */
-#define XCHAL_ICACHE_LINEWIDTH          4
-#define XCHAL_DCACHE_LINEWIDTH          4
-/*  Size of the cache lines in bytes:  */
-#define XCHAL_ICACHE_LINESIZE           16
-#define XCHAL_DCACHE_LINESIZE           16
-/*  Max for both I-cache and D-cache (used for general alignment):  */
-#define XCHAL_CACHE_LINEWIDTH_MAX       4
-#define XCHAL_CACHE_LINESIZE_MAX        16
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH           8
-#define XCHAL_DCACHE_SETWIDTH           8
-/*  Max for both I-cache and D-cache (used for general cache-coherency page alignment):  */
-#define XCHAL_CACHE_SETWIDTH_MAX        8
-#define XCHAL_CACHE_SETSIZE_MAX         256
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS               2
-#define XCHAL_DCACHE_WAYS               2
-
-/*  Size of the caches in bytes (ways * 2^(linewidth + setwidth)):  */
-#define XCHAL_ICACHE_SIZE               8192
-#define XCHAL_DCACHE_SIZE               8192
-
-/*  Cache features:  */
-#define XCHAL_DCACHE_IS_WRITEBACK       0
-/*  Whether cache locking feature is available:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE      0
-#define XCHAL_DCACHE_LINE_LOCKABLE      0
-
-/*  Number of (encoded) cache attribute bits:  */
-#define XCHAL_CA_BITS                   4       /* number of bits needed to hold cache attribute encoding */
-/*  (The number of access mode bits (decoded cache attribute bits) is defined by the architecture; see xtensa/hal.h?)  */
-
-
-/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
-#define XCHAL_FCA_LIST          XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_BYPASS        XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_BYPASS        XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_CACHED        XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_CACHED        XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_CACHED        XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_CACHED        XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST          XTHAL_LAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_LAM_BYPASSG       XCHAL_SEP \
-                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_LAM_BYPASSG       XCHAL_SEP \
-                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_LAM_CACHED        XCHAL_SEP \
-                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_LAM_CACHED        XCHAL_SEP \
-                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_LAM_NACACHED      XCHAL_SEP \
-                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_LAM_NACACHED      XCHAL_SEP \
-                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_LAM_ISOLATE       XCHAL_SEP \
-                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_LAM_CACHED
-#define XCHAL_SCA_LIST          XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_BYPASS        XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_WRITETHRU     XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_WRITETHRU     XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_ISOLATE       XCHAL_SEP \
-                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
-                                XTHAL_SAM_WRITETHRU
-
-/*  Test:
-        read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
-        read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
-        all:       0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
-        fault:     0 + 2 + 4 + 6 + 8 + 10 + 12 + 14
-        r/w/x cached:
-        r/w/x dcached:
-        I-bypass:  1 + 3
-
-        load guard bit set: 1 + 3
-        load guard bit clr: 0 + 2 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
-        hit-cache r/w/x: 7 + 11
-
-        fams: 5
-        fams: 0 / 6 / 18 / 1 / 2
-        fams: Bypass / Isolate / Cached / Exception / NACached
-
-        MMU okay:  yes
-*/
-
-
-/*----------------------------------------------------------------------
-                                MMU
-  ----------------------------------------------------------------------*/
-
-/*
- *  General notes on MMU parameters.
- *
- *  Terminology:
- *      ASID = address-space ID (acts as an "extension" of virtual addresses)
- *      VPN  = virtual page number
- *      PPN  = physical page number
- *      CA   = encoded cache attribute (access modes)
- *      TLB  = translation look-aside buffer (term is stretched somewhat here)
- *      I    = instruction (fetch accesses)
- *      D    = data (load and store accesses)
- *      way  = each TLB (ITLB and DTLB) consists of a number of "ways"
- *              that simultaneously match the virtual address of an access;
- *              a TLB successfully translates a virtual address if exactly
- *              one way matches the vaddr; if none match, it is a miss;
- *              if multiple match, one gets a "multihit" exception;
- *              each way can be independently configured in terms of number of
- *              entries, page sizes, which fields are writable or constant, etc.
- *      set  = group of contiguous ways with exactly identical parameters
- *      ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
- *              from the page table and storing it in one of the auto-refill ways;
- *              if this PTE load also misses, a miss exception is posted for s/w.
- *      min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- *              page arbitrarily under program control; it has a single entry,
- *              is non-auto-refill (some other way(s) must be auto-refill),
- *              all its fields (VPN, PPN, ASID, CA) are all writable, and it
- *              supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- *              restriction is that this be the only page size it supports).
- *
- *  TLB way entries are virtually indexed.
- *  TLB ways that support multiple page sizes:
- *      - must have all writable VPN and PPN fields;
- *      - can only use one page size at any given time (eg. setup at startup),
- *        selected by the respective ITLBCFG or DTLBCFG special register,
- *        whose bits n*4+3 .. n*4 index the list of page sizes for way n
- *        (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- *        this list may be sparse for auto-refill ways because auto-refill
- *        ways have independent lists of supported page sizes sharing a
- *        common encoding with PTE entries; the encoding is the index into
- *        this list; unsupported sizes for a given way are zero in the list;
- *        selecting unsupported sizes results in undefined hardware behaviour;
- *      - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_HAVE_CACHEATTR            0       /* 1 if CACHEATTR register present, 0 if TLBs present instead */
-#define XCHAL_HAVE_TLBS                 1       /* 1 if TLBs present, 0 if CACHEATTR present instead */
-#define XCHAL_HAVE_MMU                  XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
-#define XCHAL_HAVE_SPANNING_WAY         0       /* 1 if single way maps entire virtual address space in I+D */
-#define XCHAL_HAVE_IDENTITY_MAP         0       /* 1 if virtual addr == physical addr always, 0 otherwise */
-#define XCHAL_HAVE_MIMIC_CACHEATTR      0       /* 1 if have MMU that mimics a CACHEATTR config (CaMMU) */
-#define XCHAL_HAVE_XLT_CACHEATTR        0       /* 1 if have MMU that mimics a CACHEATTR config, but with translation (CaXltMMU) */
-
-#define XCHAL_MMU_ASID_BITS             8       /* number of bits in ASIDs (address space IDs) */
-#define XCHAL_MMU_ASID_INVALID          0       /* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL           1       /* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_RINGS                 4       /* number of rings supported (1..4) */
-#define XCHAL_MMU_RING_BITS             2       /* number of bits needed to hold ring number */
-#define XCHAL_MMU_SR_BITS               0       /* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS               4       /* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE     12      /* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE     12      /* min page size in a PTE structure (log2) */
-
-
-/***  Instruction TLB:  ***/
-
-#define XCHAL_ITLB_WAY_BITS             3       /* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS                 7       /* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS             4       /* number of auto-refill ways */
-#define XCHAL_ITLB_SETS                 4       /* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_ITLB_WAY0_SET             0
-#define XCHAL_ITLB_WAY1_SET             0
-#define XCHAL_ITLB_WAY2_SET             0
-#define XCHAL_ITLB_WAY3_SET             0
-#define XCHAL_ITLB_WAY4_SET             1
-#define XCHAL_ITLB_WAY5_SET             2
-#define XCHAL_ITLB_WAY6_SET             3
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_ITLB_ARF_SETS             1       /* number of auto-refill sets */
-#define XCHAL_ITLB_ARF_SET0             0       /* index of n'th auto-refill set */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_ITLB_MINWIRED_SETS        0       /* number of "min-wired" sets */
-
-
-/*  ITLB way set 0 (group of ways 0 thru 3):  */
-#define XCHAL_ITLB_SET0_WAY                     0       /* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS                    4       /* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2            2       /* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES                 4       /* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF                     1       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES               1       /* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS             0       /* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN         12      /* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX         12      /* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST        12      /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-
-/*  ITLB way set 1 (group of ways 4 thru 4):  */
-#define XCHAL_ITLB_SET1_WAY                     4       /* index of first way in this way set */
-#define XCHAL_ITLB_SET1_WAYS                    1       /* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET1_ENTRIES_LOG2            2       /* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET1_ENTRIES                 4       /* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET1_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET1_PAGESIZES               4       /* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET1_PAGESZ_BITS             2       /* number of bits to encode the page size */
-#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN         20      /* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX         26      /* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST        20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26       /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET1_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET1_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET1_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET1_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET1_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET1_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET1_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET1_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-
-/*  ITLB way set 2 (group of ways 5 thru 5):  */
-#define XCHAL_ITLB_SET2_WAY                     5       /* index of first way in this way set */
-#define XCHAL_ITLB_SET2_WAYS                    1       /* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET2_ENTRIES_LOG2            1       /* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET2_ENTRIES                 2       /* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET2_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET2_PAGESIZES               1       /* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET2_PAGESZ_BITS             0       /* number of bits to encode the page size */
-#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN         27      /* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX         27      /* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST        27      /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET2_ASID_CONSTMASK          0xFF    /* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET2_VPN_CONSTMASK           0xF0000000      /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET2_PPN_CONSTMASK           0xF8000000      /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET2_CA_CONSTMASK            0x0000000F      /* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET2_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET2_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET2_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET2_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant ASID values for each entry of ITLB way set 2 (because ASID_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET2_E0_ASID_CONST           0x01
-#define XCHAL_ITLB_SET2_E1_ASID_CONST           0x01
-/*  Constant VPN values for each entry of ITLB way set 2 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET2_E0_VPN_CONST            0xD0000000
-#define XCHAL_ITLB_SET2_E1_VPN_CONST            0xD8000000
-/*  Constant PPN values for each entry of ITLB way set 2 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET2_E0_PPN_CONST            0x00000000
-#define XCHAL_ITLB_SET2_E1_PPN_CONST            0x00000000
-/*  Constant CA values for each entry of ITLB way set 2 (because CA_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET2_E0_CA_CONST             0x07
-#define XCHAL_ITLB_SET2_E1_CA_CONST             0x03
-
-/*  ITLB way set 3 (group of ways 6 thru 6):  */
-#define XCHAL_ITLB_SET3_WAY                     6       /* index of first way in this way set */
-#define XCHAL_ITLB_SET3_WAYS                    1       /* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET3_ENTRIES_LOG2            1       /* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET3_ENTRIES                 2       /* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET3_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET3_PAGESIZES               1       /* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET3_PAGESZ_BITS             0       /* number of bits to encode the page size */
-#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN         28      /* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX         28      /* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST        28      /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET3_ASID_CONSTMASK          0xFF    /* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET3_VPN_CONSTMASK           0xE0000000      /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET3_PPN_CONSTMASK           0xF0000000      /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET3_CA_CONSTMASK            0x0000000F      /* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET3_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET3_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET3_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET3_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant ASID values for each entry of ITLB way set 3 (because ASID_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET3_E0_ASID_CONST           0x01
-#define XCHAL_ITLB_SET3_E1_ASID_CONST           0x01
-/*  Constant VPN values for each entry of ITLB way set 3 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET3_E0_VPN_CONST            0xE0000000
-#define XCHAL_ITLB_SET3_E1_VPN_CONST            0xF0000000
-/*  Constant PPN values for each entry of ITLB way set 3 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET3_E0_PPN_CONST            0xF0000000
-#define XCHAL_ITLB_SET3_E1_PPN_CONST            0xF0000000
-/*  Constant CA values for each entry of ITLB way set 3 (because CA_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET3_E0_CA_CONST             0x07
-#define XCHAL_ITLB_SET3_E1_CA_CONST             0x03
-
-/*  Indexing macros:  */
-#define _XCHAL_ITLB_SET(n,_what)        XCHAL_ITLB_SET ## n ## _what
-#define XCHAL_ITLB_SET(n,what)          _XCHAL_ITLB_SET(n, _ ## what )
-#define _XCHAL_ITLB_SET_E(n,i,_what)    XCHAL_ITLB_SET ## n ## _E ## i ## _what
-#define XCHAL_ITLB_SET_E(n,i,what)      _XCHAL_ITLB_SET_E(n,i, _ ## what )
-/*
- *  Example use:  XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
- *      to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
- */
-
-
-/***  Data TLB:  ***/
-
-#define XCHAL_DTLB_WAY_BITS             4       /* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS                 10      /* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS             4       /* number of auto-refill ways */
-#define XCHAL_DTLB_SETS                 5       /* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_DTLB_WAY0_SET             0
-#define XCHAL_DTLB_WAY1_SET             0
-#define XCHAL_DTLB_WAY2_SET             0
-#define XCHAL_DTLB_WAY3_SET             0
-#define XCHAL_DTLB_WAY4_SET             1
-#define XCHAL_DTLB_WAY5_SET             2
-#define XCHAL_DTLB_WAY6_SET             3
-#define XCHAL_DTLB_WAY7_SET             4
-#define XCHAL_DTLB_WAY8_SET             4
-#define XCHAL_DTLB_WAY9_SET             4
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_DTLB_ARF_SETS             1       /* number of auto-refill sets */
-#define XCHAL_DTLB_ARF_SET0             0       /* index of n'th auto-refill set */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_DTLB_MINWIRED_SETS        1       /* number of "min-wired" sets */
-#define XCHAL_DTLB_MINWIRED_SET0        4       /* index of n'th "min-wired" set */
-
-
-/*  DTLB way set 0 (group of ways 0 thru 3):  */
-#define XCHAL_DTLB_SET0_WAY                     0       /* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS                    4       /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2            2       /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES                 4       /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF                     1       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES               1       /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS             0       /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN         12      /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX         12      /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST        12      /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-
-/*  DTLB way set 1 (group of ways 4 thru 4):  */
-#define XCHAL_DTLB_SET1_WAY                     4       /* index of first way in this way set */
-#define XCHAL_DTLB_SET1_WAYS                    1       /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET1_ENTRIES_LOG2            2       /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET1_ENTRIES                 4       /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET1_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET1_PAGESIZES               4       /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET1_PAGESZ_BITS             2       /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN         20      /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX         26      /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST        20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26       /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET1_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET1_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET1_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET1_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET1_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET1_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET1_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET1_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-
-/*  DTLB way set 2 (group of ways 5 thru 5):  */
-#define XCHAL_DTLB_SET2_WAY                     5       /* index of first way in this way set */
-#define XCHAL_DTLB_SET2_WAYS                    1       /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET2_ENTRIES_LOG2            1       /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET2_ENTRIES                 2       /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET2_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET2_PAGESIZES               1       /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET2_PAGESZ_BITS             0       /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN         27      /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX         27      /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST        27      /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET2_ASID_CONSTMASK          0xFF    /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET2_VPN_CONSTMASK           0xF0000000      /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET2_PPN_CONSTMASK           0xF8000000      /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET2_CA_CONSTMASK            0x0000000F      /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET2_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET2_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET2_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET2_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant ASID values for each entry of DTLB way set 2 (because ASID_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET2_E0_ASID_CONST           0x01
-#define XCHAL_DTLB_SET2_E1_ASID_CONST           0x01
-/*  Constant VPN values for each entry of DTLB way set 2 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET2_E0_VPN_CONST            0xD0000000
-#define XCHAL_DTLB_SET2_E1_VPN_CONST            0xD8000000
-/*  Constant PPN values for each entry of DTLB way set 2 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET2_E0_PPN_CONST            0x00000000
-#define XCHAL_DTLB_SET2_E1_PPN_CONST            0x00000000
-/*  Constant CA values for each entry of DTLB way set 2 (because CA_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET2_E0_CA_CONST             0x07
-#define XCHAL_DTLB_SET2_E1_CA_CONST             0x03
-
-/*  DTLB way set 3 (group of ways 6 thru 6):  */
-#define XCHAL_DTLB_SET3_WAY                     6       /* index of first way in this way set */
-#define XCHAL_DTLB_SET3_WAYS                    1       /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET3_ENTRIES_LOG2            1       /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET3_ENTRIES                 2       /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET3_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET3_PAGESIZES               1       /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET3_PAGESZ_BITS             0       /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN         28      /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX         28      /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST        28      /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET3_ASID_CONSTMASK          0xFF    /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET3_VPN_CONSTMASK           0xE0000000      /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET3_PPN_CONSTMASK           0xF0000000      /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET3_CA_CONSTMASK            0x0000000F      /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET3_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET3_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET3_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET3_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant ASID values for each entry of DTLB way set 3 (because ASID_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET3_E0_ASID_CONST           0x01
-#define XCHAL_DTLB_SET3_E1_ASID_CONST           0x01
-/*  Constant VPN values for each entry of DTLB way set 3 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET3_E0_VPN_CONST            0xE0000000
-#define XCHAL_DTLB_SET3_E1_VPN_CONST            0xF0000000
-/*  Constant PPN values for each entry of DTLB way set 3 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET3_E0_PPN_CONST            0xF0000000
-#define XCHAL_DTLB_SET3_E1_PPN_CONST            0xF0000000
-/*  Constant CA values for each entry of DTLB way set 3 (because CA_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET3_E0_CA_CONST             0x07
-#define XCHAL_DTLB_SET3_E1_CA_CONST             0x03
-
-/*  DTLB way set 4 (group of ways 7 thru 9):  */
-#define XCHAL_DTLB_SET4_WAY                     7       /* index of first way in this way set */
-#define XCHAL_DTLB_SET4_WAYS                    3       /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET4_ENTRIES_LOG2            0       /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET4_ENTRIES                 1       /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET4_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET4_PAGESIZES               1       /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET4_PAGESZ_BITS             0       /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN         12      /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX         12      /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST        12      /* list of log2(page size)s, separated by XCHAL_SEP;
-                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET4_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET4_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET4_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET4_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET4_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET4_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET4_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET4_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
-
-/*  Indexing macros:  */
-#define _XCHAL_DTLB_SET(n,_what)        XCHAL_DTLB_SET ## n ## _what
-#define XCHAL_DTLB_SET(n,what)          _XCHAL_DTLB_SET(n, _ ## what )
-#define _XCHAL_DTLB_SET_E(n,i,_what)    XCHAL_DTLB_SET ## n ## _E ## i ## _what
-#define XCHAL_DTLB_SET_E(n,i,what)      _XCHAL_DTLB_SET_E(n,i, _ ## what )
-/*
- *  Example use:  XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES)
- *      to get the value of XCHAL_DTLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
- */
-
-
-/*
- *  Determine whether we have a full MMU (with Page Table and Protection)
- *  usable for an MMU-based OS:
- */
-#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
-# define XCHAL_HAVE_PTP_MMU             1       /* have full MMU (with page table [autorefill] and protection) */
-#else
-# define XCHAL_HAVE_PTP_MMU             0       /* don't have full MMU */
-#endif
-
-/*
- *  For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
- */
-#if XCHAL_HAVE_PTP_MMU
-#define XCHAL_KSEG_CACHED_VADDR         0xD0000000      /* virt.addr of kernel RAM cached static map */
-#define XCHAL_KSEG_CACHED_PADDR         0x00000000      /* phys.addr of kseg_cached */
-#define XCHAL_KSEG_CACHED_SIZE          0x08000000      /* size in bytes of kseg_cached (assumed power of 2!!!) */
-#define XCHAL_KSEG_BYPASS_VADDR         0xD8000000      /* virt.addr of kernel RAM bypass (uncached) static map */
-#define XCHAL_KSEG_BYPASS_PADDR         0x00000000      /* phys.addr of kseg_bypass */
-#define XCHAL_KSEG_BYPASS_SIZE          0x08000000      /* size in bytes of kseg_bypass (assumed power of 2!!!) */
-
-#define XCHAL_KIO_CACHED_VADDR          0xE0000000      /* virt.addr of kernel I/O cached static map */
-#define XCHAL_KIO_CACHED_PADDR          0xF0000000      /* phys.addr of kio_cached */
-#define XCHAL_KIO_CACHED_SIZE           0x10000000      /* size in bytes of kio_cached (assumed power of 2!!!) */
-#define XCHAL_KIO_BYPASS_VADDR          0xF0000000      /* virt.addr of kernel I/O bypass (uncached) static map */
-#define XCHAL_KIO_BYPASS_PADDR          0xF0000000      /* phys.addr of kio_bypass */
-#define XCHAL_KIO_BYPASS_SIZE           0x10000000      /* size in bytes of kio_bypass (assumed power of 2!!!) */
-
-#define XCHAL_SEG_MAPPABLE_VADDR        0x00000000      /* start of largest non-static-mapped virtual addr area */
-#define XCHAL_SEG_MAPPABLE_SIZE         0xD0000000      /* size in bytes of  "  */
-/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size.  */
-#endif
-
-
-/*----------------------------------------------------------------------
-                                MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES   4       /* number of write buffer entries */
-
-#define XCHAL_CORE_ID                   "linux_be"      /* configuration's alphanumeric core identifier
-                                                           (CoreID) set in the Xtensa Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID           0x00003256      /* software build-unique ID (22-bit) */
-
-/*  These definitions describe the hardware targeted by this software:  */
-#define XCHAL_HW_CONFIGID0              0xC103D1FF      /* config ID reg 0 value (upper 32 of 64 bits) */
-#define XCHAL_HW_CONFIGID1              0x00803256      /* config ID reg 1 value (lower 32 of 64 bits) */
-#define XCHAL_CONFIGID0                 XCHAL_HW_CONFIGID0      /* for backward compatibility only -- don't use! */
-#define XCHAL_CONFIGID1                 XCHAL_HW_CONFIGID1      /* for backward compatibility only -- don't use! */
-#define XCHAL_HW_RELEASE_MAJOR          1050    /* major release of targeted hardware */
-#define XCHAL_HW_RELEASE_MINOR          1       /* minor release of targeted hardware */
-#define XCHAL_HW_RELEASE_NAME           "T1050.1"       /* full release name of targeted hardware */
-#define XTHAL_HW_REL_T1050      1
-#define XTHAL_HW_REL_T1050_1    1
-#define XCHAL_HW_CONFIGID_RELIABLE      1
-
-
-/*
- *  Miscellaneous special register fields:
- */
-
-
-/*  DBREAKC (special register number 160):  */
-#define XCHAL_DBREAKC_VALIDMASK 0xC000003F      /* bits of DBREAKC that are defined */
-/*  MASK field:  */
-#define XCHAL_DBREAKC_MASK_BITS         6               /* number of bits in MASK field */
-#define XCHAL_DBREAKC_MASK_NUM          64              /* max number of possible causes (2^bits) */
-#define XCHAL_DBREAKC_MASK_SHIFT        0               /* position of MASK bits in DBREAKC, starting from lsbit */
-#define XCHAL_DBREAKC_MASK_MASK         0x0000003F      /* mask of bits in MASK field of DBREAKC */
-/*  LOADBREAK field:  */
-#define XCHAL_DBREAKC_LOADBREAK_BITS    1               /* number of bits in LOADBREAK field */
-#define XCHAL_DBREAKC_LOADBREAK_NUM     2               /* max number of possible causes (2^bits) */
-#define XCHAL_DBREAKC_LOADBREAK_SHIFT   30              /* position of LOADBREAK bits in DBREAKC, starting from lsbit */
-#define XCHAL_DBREAKC_LOADBREAK_MASK    0x40000000      /* mask of bits in LOADBREAK field of DBREAKC */
-/*  STOREBREAK field:  */
-#define XCHAL_DBREAKC_STOREBREAK_BITS   1               /* number of bits in STOREBREAK field */
-#define XCHAL_DBREAKC_STOREBREAK_NUM    2               /* max number of possible causes (2^bits) */
-#define XCHAL_DBREAKC_STOREBREAK_SHIFT  31              /* position of STOREBREAK bits in DBREAKC, starting from lsbit */
-#define XCHAL_DBREAKC_STOREBREAK_MASK   0x80000000      /* mask of bits in STOREBREAK field of DBREAKC */
-
-/*  PS (special register number 230):  */
-#define XCHAL_PS_VALIDMASK      0x00070FFF      /* bits of PS that are defined */
-/*  INTLEVEL field:  */
-#define XCHAL_PS_INTLEVEL_BITS  4               /* number of bits in INTLEVEL field */
-#define XCHAL_PS_INTLEVEL_NUM   16              /* max number of possible causes (2^bits) */
-#define XCHAL_PS_INTLEVEL_SHIFT 0               /* position of INTLEVEL bits in PS, starting from lsbit */
-#define XCHAL_PS_INTLEVEL_MASK  0x0000000F      /* mask of bits in INTLEVEL field of PS */
-/*  EXCM field:  */
-#define XCHAL_PS_EXCM_BITS      1               /* number of bits in EXCM field */
-#define XCHAL_PS_EXCM_NUM       2               /* max number of possible causes (2^bits) */
-#define XCHAL_PS_EXCM_SHIFT     4               /* position of EXCM bits in PS, starting from lsbit */
-#define XCHAL_PS_EXCM_MASK      0x00000010      /* mask of bits in EXCM field of PS */
-/*  PROGSTACK field:  */
-#define XCHAL_PS_PROGSTACK_BITS         1               /* number of bits in PROGSTACK field */
-#define XCHAL_PS_PROGSTACK_NUM          2               /* max number of possible causes (2^bits) */
-#define XCHAL_PS_PROGSTACK_SHIFT        5               /* position of PROGSTACK bits in PS, starting from lsbit */
-#define XCHAL_PS_PROGSTACK_MASK         0x00000020      /* mask of bits in PROGSTACK field of PS */
-/*  RING field:  */
-#define XCHAL_PS_RING_BITS      2               /* number of bits in RING field */
-#define XCHAL_PS_RING_NUM       4               /* max number of possible causes (2^bits) */
-#define XCHAL_PS_RING_SHIFT     6               /* position of RING bits in PS, starting from lsbit */
-#define XCHAL_PS_RING_MASK      0x000000C0      /* mask of bits in RING field of PS */
-/*  OWB field:  */
-#define XCHAL_PS_OWB_BITS       4               /* number of bits in OWB field */
-#define XCHAL_PS_OWB_NUM        16              /* max number of possible causes (2^bits) */
-#define XCHAL_PS_OWB_SHIFT      8               /* position of OWB bits in PS, starting from lsbit */
-#define XCHAL_PS_OWB_MASK       0x00000F00      /* mask of bits in OWB field of PS */
-/*  CALLINC field:  */
-#define XCHAL_PS_CALLINC_BITS   2               /* number of bits in CALLINC field */
-#define XCHAL_PS_CALLINC_NUM    4               /* max number of possible causes (2^bits) */
-#define XCHAL_PS_CALLINC_SHIFT  16              /* position of CALLINC bits in PS, starting from lsbit */
-#define XCHAL_PS_CALLINC_MASK   0x00030000      /* mask of bits in CALLINC field of PS */
-/*  WOE field:  */
-#define XCHAL_PS_WOE_BITS       1               /* number of bits in WOE field */
-#define XCHAL_PS_WOE_NUM        2               /* max number of possible causes (2^bits) */
-#define XCHAL_PS_WOE_SHIFT      18              /* position of WOE bits in PS, starting from lsbit */
-#define XCHAL_PS_WOE_MASK       0x00040000      /* mask of bits in WOE field of PS */
-
-/*  EXCCAUSE (special register number 232):  */
-#define XCHAL_EXCCAUSE_VALIDMASK        0x0000003F      /* bits of EXCCAUSE that are defined */
-/*  EXCCAUSE field:  */
-#define XCHAL_EXCCAUSE_BITS             6               /* number of bits in EXCCAUSE register */
-#define XCHAL_EXCCAUSE_NUM              64              /* max number of possible causes (2^bits) */
-#define XCHAL_EXCCAUSE_SHIFT            0               /* position of EXCCAUSE bits in register, starting from lsbit */
-#define XCHAL_EXCCAUSE_MASK             0x0000003F      /* mask of bits in EXCCAUSE register */
-
-/*  DEBUGCAUSE (special register number 233):  */
-#define XCHAL_DEBUGCAUSE_VALIDMASK      0x0000003F      /* bits of DEBUGCAUSE that are defined */
-/*  ICOUNT field:  */
-#define XCHAL_DEBUGCAUSE_ICOUNT_BITS    1               /* number of bits in ICOUNT field */
-#define XCHAL_DEBUGCAUSE_ICOUNT_NUM     2               /* max number of possible causes (2^bits) */
-#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT   0               /* position of ICOUNT bits in DEBUGCAUSE, starting from lsbit */
-#define XCHAL_DEBUGCAUSE_ICOUNT_MASK    0x00000001      /* mask of bits in ICOUNT field of DEBUGCAUSE */
-/*  IBREAK field:  */
-#define XCHAL_DEBUGCAUSE_IBREAK_BITS    1               /* number of bits in IBREAK field */
-#define XCHAL_DEBUGCAUSE_IBREAK_NUM     2               /* max number of possible causes (2^bits) */
-#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT   1               /* position of IBREAK bits in DEBUGCAUSE, starting from lsbit */
-#define XCHAL_DEBUGCAUSE_IBREAK_MASK    0x00000002      /* mask of bits in IBREAK field of DEBUGCAUSE */
-/*  DBREAK field:  */
-#define XCHAL_DEBUGCAUSE_DBREAK_BITS    1               /* number of bits in DBREAK field */
-#define XCHAL_DEBUGCAUSE_DBREAK_NUM     2               /* max number of possible causes (2^bits) */
-#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT   2               /* position of DBREAK bits in DEBUGCAUSE, starting from lsbit */
-#define XCHAL_DEBUGCAUSE_DBREAK_MASK    0x00000004      /* mask of bits in DBREAK field of DEBUGCAUSE */
-/*  BREAK field:  */
-#define XCHAL_DEBUGCAUSE_BREAK_BITS     1               /* number of bits in BREAK field */
-#define XCHAL_DEBUGCAUSE_BREAK_NUM      2               /* max number of possible causes (2^bits) */
-#define XCHAL_DEBUGCAUSE_BREAK_SHIFT    3               /* position of BREAK bits in DEBUGCAUSE, starting from lsbit */
-#define XCHAL_DEBUGCAUSE_BREAK_MASK     0x00000008      /* mask of bits in BREAK field of DEBUGCAUSE */
-/*  BREAKN field:  */
-#define XCHAL_DEBUGCAUSE_BREAKN_BITS    1               /* number of bits in BREAKN field */
-#define XCHAL_DEBUGCAUSE_BREAKN_NUM     2               /* max number of possible causes (2^bits) */
-#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT   4               /* position of BREAKN bits in DEBUGCAUSE, starting from lsbit */
-#define XCHAL_DEBUGCAUSE_BREAKN_MASK    0x00000010      /* mask of bits in BREAKN field of DEBUGCAUSE */
-/*  DEBUGINT field:  */
-#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS  1               /* number of bits in DEBUGINT field */
-#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM   2               /* max number of possible causes (2^bits) */
-#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5               /* position of DEBUGINT bits in DEBUGCAUSE, starting from lsbit */
-#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK  0x00000020      /* mask of bits in DEBUGINT field of DEBUGCAUSE */
-
-
-
-/*----------------------------------------------------------------------
-                                ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_DENSITY              1       /* 1 if density option configured, 0 otherwise */
-#define XCHAL_HAVE_LOOPS                1       /* 1 if zero-overhead loops option configured, 0 otherwise */
-/*  Misc instructions:  */
-#define XCHAL_HAVE_NSA                  0       /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
-#define XCHAL_HAVE_MINMAX               0       /* 1 if MIN/MAX instructions option configured, 0 otherwise */
-#define XCHAL_HAVE_SEXT                 0       /* 1 if sign-extend instruction option configured, 0 otherwise */
-#define XCHAL_HAVE_CLAMPS               0       /* 1 if CLAMPS instruction option configured, 0 otherwise */
-#define XCHAL_HAVE_MAC16                0       /* 1 if MAC16 option configured, 0 otherwise */
-#define XCHAL_HAVE_MUL16                0       /* 1 if 16-bit integer multiply option configured, 0 otherwise */
-/*#define XCHAL_HAVE_POPC               0*/     /* 1 if CRC instruction option configured, 0 otherwise */
-/*#define XCHAL_HAVE_CRC                0*/     /* 1 if POPC instruction option configured, 0 otherwise */
-
-#define XCHAL_HAVE_SPECULATION          0       /* 1 if speculation option configured, 0 otherwise */
-/*#define XCHAL_HAVE_MP_SYNC            0*/     /* 1 if multiprocessor sync. option configured, 0 otherwise */
-#define XCHAL_HAVE_PRID                 0       /* 1 if processor ID register configured, 0 otherwise */
-
-#define XCHAL_NUM_MISC_REGS             2       /* number of miscellaneous registers (0..4) */
-
-/*  These relate a bit more to TIE:  */
-#define XCHAL_HAVE_BOOLEANS             0       /* 1 if booleans option configured, 0 otherwise */
-#define XCHAL_HAVE_MUL32                0       /* 1 if 32-bit integer multiply option configured, 0 otherwise */
-#define XCHAL_HAVE_MUL32_HIGH           0       /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
-#define XCHAL_HAVE_FP                   0       /* 1 if floating point option configured, 0 otherwise */
-
-
-/*----------------------------------------------------------------------
-                                DERIVED
-  ----------------------------------------------------------------------*/
-
-#if XCHAL_HAVE_BE
-#define XCHAL_INST_ILLN                 0xD60F          /* 2-byte illegal instruction, msb-first */
-#define XCHAL_INST_ILLN_BYTE0           0xD6            /* 2-byte illegal instruction, 1st byte */
-#define XCHAL_INST_ILLN_BYTE1           0x0F            /* 2-byte illegal instruction, 2nd byte */
-#else
-#define XCHAL_INST_ILLN                 0xF06D          /* 2-byte illegal instruction, lsb-first */
-#define XCHAL_INST_ILLN_BYTE0           0x6D            /* 2-byte illegal instruction, 1st byte */
-#define XCHAL_INST_ILLN_BYTE1           0xF0            /* 2-byte illegal instruction, 2nd byte */
-#endif
-/*  Belongs in xtensa/hal.h:  */
-#define XTHAL_INST_ILL                  0x000000        /* 3-byte illegal instruction */
-
-
-/*
- *  Because information as to exactly which hardware release is targeted
- *  by a given software build is not always available, compile-time HAL
- *  Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
- */
-#ifndef XCHAL_HW_RELEASE_MAJOR
-# define XCHAL_HW_CONFIGID_RELIABLE     0
-#endif
-#if XCHAL_HW_CONFIGID_RELIABLE
-# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)      (XTHAL_REL_LE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)      (XTHAL_REL_GE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_AT(major,minor)               (XTHAL_REL_EQ( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_MAJOR_AT(major)               ((XCHAL_HW_RELEASE_MAJOR == (major)) ? 1 : 0)
-#else
-# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)      ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
-                                                        : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
-                                                        : XTHAL_MAYBE )
-# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)      ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
-                                                        : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
-                                                        : XTHAL_MAYBE )
-# define XCHAL_HW_RELEASE_AT(major,minor)               ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
-                                                           ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
-# define XCHAL_HW_RELEASE_MAJOR_AT(major)               XCHAL_HW_RELEASE_AT(major,0)
-#endif
-
-/*
- *  Specific errata:
- */
-
-/*
- *  Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
- *  relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
- */
-#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN  (XCHAL_HAVE_XEA1 && \
-                                         (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
-                                          || XCHAL_HW_RELEASE_AT(1050,0)))
-
-
-
-#endif /*XTENSA_CONFIG_CORE_H*/
-
diff --git a/include/asm-xtensa/xtensa/config-linux_be/defs.h b/include/asm-xtensa/xtensa/config-linux_be/defs.h
deleted file mode 100644
index f7c58b273371..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/defs.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/*
- * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2.1 of the GNU Lesser General Public
- * License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it would be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Further, this software is distributed without any warranty that it is
- * free of the rightful claim of any third person regarding infringement
- * or the like.  Any license provided herein, whether implied or
- * otherwise, applies only to this software file.  Patent licenses, if
- * any, provided herein do not apply to combinations of this program with
- * other software, or any other product whatsoever.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this program; if not, write the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
- * USA.
- */
-
-/* Do not modify. This is automatically generated.*/
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-#if defined(__GNUC__) && !defined(__XCC__)
-
-#define L8UI_ASM(arr, ars, imm) { \
-  __asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
-}
-
-#define XT_L8UI(ars, imm) \
-({ \
-  unsigned char _arr; \
-  const unsigned char *_ars = ars; \
-  L8UI_ASM(_arr, _ars, imm); \
-  _arr; \
-})
-
-#define L16UI_ASM(arr, ars, imm) { \
-  __asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
-}
-
-#define XT_L16UI(ars, imm) \
-({ \
-  unsigned short _arr; \
-  const unsigned short *_ars = ars; \
-  L16UI_ASM(_arr, _ars, imm); \
-  _arr; \
-})
-
-#define L16SI_ASM(arr, ars, imm) {\
-  __asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
-}
-
-#define XT_L16SI(ars, imm) \
-({ \
-  signed short _arr; \
-  const signed short *_ars = ars; \
-  L16SI_ASM(_arr, _ars, imm); \
-  _arr; \
-})
-
-#define L32I_ASM(arr, ars, imm) { \
-  __asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
-}
-
-#define XT_L32I(ars, imm) \
-({ \
-  unsigned _arr; \
-  const unsigned *_ars = ars; \
-  L32I_ASM(_arr, _ars, imm); \
-  _arr; \
-})
-
-#define S8I_ASM(arr, ars, imm) {\
-  __asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
-}
-
-#define XT_S8I(arr, ars, imm) \
-({ \
-  signed char _arr = arr; \
-  const signed char *_ars = ars; \
-  S8I_ASM(_arr, _ars, imm); \
-})
-
-#define S16I_ASM(arr, ars, imm) {\
-  __asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
-}
-
-#define XT_S16I(arr, ars, imm) \
-({ \
-  signed short _arr = arr; \
-  const signed short *_ars = ars; \
-  S16I_ASM(_arr, _ars, imm); \
-})
-
-#define S32I_ASM(arr, ars, imm) { \
-  __asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
-}
-
-#define XT_S32I(arr, ars, imm) \
-({ \
-  signed int _arr = arr; \
-  const signed int *_ars = ars; \
-  S32I_ASM(_arr, _ars, imm); \
-})
-
-#define ADDI_ASM(art, ars, imm) {\
-   __asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
-}
-
-#define XT_ADDI(ars, imm) \
-({ \
-   unsigned _art; \
-   unsigned _ars = ars; \
-   ADDI_ASM(_art, _ars, imm); \
-   _art; \
-})
-
-#define ABS_ASM(arr, art) {\
-   __asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
-}
-
-#define XT_ABS(art) \
-({ \
-   unsigned _arr; \
-   signed _art = art; \
-   ABS_ASM(_arr, _art); \
-   _arr; \
-})
-
-/* Note: In the following macros that reference SAR, the magic "state"
-   register is used to capture the dependency on SAR.  This is because
-   SAR is a 5-bit register and thus there are no C types that can be
-   used to represent it.  It doesn't appear that the SAR register is
-   even relevant to GCC, but it is marked as "clobbered" just in
-   case.  */
-
-#define SRC_ASM(arr, ars, art) {\
-   register int _xt_sar __asm__ ("state"); \
-   __asm__ ("src %0, %1, %2" \
-            : "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
-}
-
-#define XT_SRC(ars, art) \
-({ \
-   unsigned _arr; \
-   unsigned _ars = ars; \
-   unsigned _art = art; \
-   SRC_ASM(_arr, _ars, _art); \
-   _arr; \
-})
-
-#define SSR_ASM(ars) {\
-   register int _xt_sar __asm__ ("state"); \
-   __asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
-}
-
-#define XT_SSR(ars) \
-({ \
-   unsigned _ars = ars; \
-   SSR_ASM(_ars); \
-})
-
-#define SSL_ASM(ars) {\
-   register int _xt_sar __asm__ ("state"); \
-   __asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
-}
-
-#define XT_SSL(ars) \
-({ \
-   unsigned _ars = ars; \
-   SSL_ASM(_ars); \
-})
-
-#define SSA8B_ASM(ars) {\
-   register int _xt_sar __asm__ ("state"); \
-   __asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
-}
-
-#define XT_SSA8B(ars) \
-({ \
-   unsigned _ars = ars; \
-   SSA8B_ASM(_ars); \
-})
-
-#define SSA8L_ASM(ars) {\
-   register int _xt_sar __asm__ ("state"); \
-   __asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
-}
-
-#define XT_SSA8L(ars) \
-({ \
-   unsigned _ars = ars; \
-   SSA8L_ASM(_ars); \
-})
-
-#define SSAI_ASM(imm) {\
-   register int _xt_sar __asm__ ("state"); \
-   __asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
-}
-
-#define XT_SSAI(imm) \
-({ \
-   SSAI_ASM(imm); \
-})
-
-
-
-
-
-
-
-
-#endif /* __GNUC__ && !__XCC__ */
-
-#ifdef __XCC__
-
-/* Core load/store instructions */
-extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
-extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
-extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
-extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
-extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
-extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
-extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
-
-#define XT_L8UI  _TIE_L8UI
-#define XT_L16UI _TIE_L16UI
-#define XT_L16SI _TIE_L16SI
-#define XT_L32I  _TIE_L32I
-#define XT_S8I   _TIE_S8I
-#define XT_S16I  _TIE_S16I
-#define XT_S32I  _TIE_S32I
-
-/* Add-immediate instruction */
-extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
-#define XT_ADDI  _TIE_ADDI
-
-/* Absolute value instruction */
-extern unsigned _TIE_ABS(int art);
-#define XT_ABS _TIE_ABS
-
-/* funnel shift instructions */
-extern unsigned _TIE_SRC(unsigned ars, unsigned art);
-#define XT_SRC _TIE_SRC
-extern void _TIE_SSR(unsigned ars);
-#define XT_SSR _TIE_SSR
-extern void _TIE_SSL(unsigned ars);
-#define XT_SSL _TIE_SSL
-extern void _TIE_SSA8B(unsigned ars);
-#define XT_SSA8B _TIE_SSA8B
-extern void _TIE_SSA8L(unsigned ars);
-#define XT_SSA8L _TIE_SSA8L
-extern void _TIE_SSAI(immediate imm);
-#define XT_SSAI _TIE_SSAI
-
-
-#endif /* __XCC__ */
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/include/asm-xtensa/xtensa/config-linux_be/specreg.h b/include/asm-xtensa/xtensa/config-linux_be/specreg.h
deleted file mode 100644
index fa4106aa9a02..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/specreg.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: specreg.h,v 1.2 2003/03/07 19:15:18 joetaylor Exp $ */
-
-/*
- * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2.1 of the GNU Lesser General Public
- * License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it would be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Further, this software is distributed without any warranty that it is
- * free of the rightful claim of any third person regarding infringement
- * or the like.  Any license provided herein, whether implied or
- * otherwise, applies only to this software file.  Patent licenses, if
- * any, provided herein do not apply to combinations of this program with
- * other software, or any other product whatsoever.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this program; if not, write the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
- * USA.
- */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG            0
-#define LEND            1
-#define LCOUNT          2
-#define SAR             3
-#define WINDOWBASE      72
-#define WINDOWSTART     73
-#define PTEVADDR        83
-#define RASID           90
-#define ITLBCFG         91
-#define DTLBCFG         92
-#define IBREAKENABLE    96
-#define DDR             104
-#define IBREAKA_0       128
-#define IBREAKA_1       129
-#define DBREAKA_0       144
-#define DBREAKA_1       145
-#define DBREAKC_0       160
-#define DBREAKC_1       161
-#define EPC_1           177
-#define EPC_2           178
-#define EPC_3           179
-#define EPC_4           180
-#define DEPC            192
-#define EPS_2           194
-#define EPS_3           195
-#define EPS_4           196
-#define EXCSAVE_1       209
-#define EXCSAVE_2       210
-#define EXCSAVE_3       211
-#define EXCSAVE_4       212
-#define INTERRUPT       226
-#define INTENABLE       228
-#define PS              230
-#define EXCCAUSE        232
-#define DEBUGCAUSE      233
-#define CCOUNT          234
-#define ICOUNT          236
-#define ICOUNTLEVEL     237
-#define EXCVADDR        238
-#define CCOMPARE_0      240
-#define CCOMPARE_1      241
-#define CCOMPARE_2      242
-#define MISC_REG_0      244
-#define MISC_REG_1      245
-
-/*  Special cases (bases of special register series):  */
-#define IBREAKA         128
-#define DBREAKA         144
-#define DBREAKC         160
-#define EPC             176
-#define EPS             192
-#define EXCSAVE         208
-#define CCOMPARE        240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD         226
-#define INTSET          226
-#define INTCLEAR        227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/include/asm-xtensa/xtensa/config-linux_be/system.h b/include/asm-xtensa/xtensa/config-linux_be/system.h
deleted file mode 100644
index cf9d4d308e3a..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/system.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/*
- * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2.1 of the GNU Lesser General Public
- * License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it would be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Further, this software is distributed without any warranty that it is
- * free of the rightful claim of any third person regarding infringement
- * or the like.  Any license provided herein, whether implied or
- * otherwise, applies only to this software file.  Patent licenses, if
- * any, provided herein do not apply to combinations of this program with
- * other software, or any other product whatsoever.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this program; if not, write the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
- * USA.
- */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*#include <xtensa/hal.h>*/
-
-
-
-/*----------------------------------------------------------------------
-                                DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR      0xE0000000
-#define XSHAL_IOBLOCK_CACHED_PADDR      0xF0000000
-#define XSHAL_IOBLOCK_CACHED_SIZE       0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR      0xF0000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR      0xF0000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE       0x0E000000
-
-/*  System ROM:  */
-#define XSHAL_ROM_VADDR         0xEE000000
-#define XSHAL_ROM_PADDR         0xFE000000
-#define XSHAL_ROM_SIZE          0x00400000
-/*  Largest available area (free of vectors):  */
-#define XSHAL_ROM_AVAIL_VADDR   0xEE00052C
-#define XSHAL_ROM_AVAIL_VSIZE   0x003FFAD4
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR         0xD0000000
-#define XSHAL_RAM_PADDR         0x00000000
-#define XSHAL_RAM_VSIZE         0x08000000
-#define XSHAL_RAM_PSIZE         0x10000000
-#define XSHAL_RAM_SIZE          XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR   0xD0000370
-#define XSHAL_RAM_AVAIL_VSIZE   0x07FFFC90
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR          0xD8000000
-#define XSHAL_RAM_BYPASS_PADDR          0x00000000
-#define XSHAL_RAM_BYPASS_PSIZE          0x08000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-#define XSHAL_ALTRAM_VADDR              0xCEE00000
-#define XSHAL_ALTRAM_PADDR              0xC0000000
-#define XSHAL_ALTRAM_SIZE               0x00200000
-
-
-/*----------------------------------------------------------------------
- *                      DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-                        BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS          XSHAL_XT2000_CACHEATTR_BYPASS   /* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT         XSHAL_XT2000_CACHEATTR_DEFAULT  /* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-                        ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_ISS_CACHEATTR_WRITEBACK   0x1122222F      /* enable caches in write-back mode */
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC  0x1122222F      /* enable caches in write-allocate mode */
-#define XSHAL_ISS_CACHEATTR_WRITETHRU   0x1122222F      /* enable caches in write-through mode */
-#define XSHAL_ISS_CACHEATTR_BYPASS      0x2222222F      /* disable caches in bypass mode */
-#define XSHAL_ISS_CACHEATTR_DEFAULT     XSHAL_ISS_CACHEATTR_WRITEBACK   /* default setting to enable caches */
-
-/*  For Coware only:  */
-#define XSHAL_COWARE_CACHEATTR_WRITEBACK        0x11222222      /* enable caches in write-back mode */
-#define XSHAL_COWARE_CACHEATTR_WRITEALLOC       0x11222222      /* enable caches in write-allocate mode */
-#define XSHAL_COWARE_CACHEATTR_WRITETHRU        0x11222222      /* enable caches in write-through mode */
-#define XSHAL_COWARE_CACHEATTR_BYPASS           0x22222222      /* disable caches in bypass mode */
-#define XSHAL_COWARE_CACHEATTR_DEFAULT          XSHAL_COWARE_CACHEATTR_WRITEBACK        /* default setting to enable caches */
-
-/*  For BFM and other purposes:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK      0x11222222      /* enable caches without any invalid regions */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT        XSHAL_ALLVALID_CACHEATTR_WRITEBACK      /* default setting for caches without any invalid regions */
-
-#define XSHAL_ISS_PIPE_REGIONS  0
-#define XSHAL_ISS_SDRAM_REGIONS 0
-
-
-/*----------------------------------------------------------------------
-                        XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK        0x22FFFFFF      /* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC       0x22FFFFFF      /* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU        0x22FFFFFF      /* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS           0x22FFFFFF      /* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT          XSHAL_XT2000_CACHEATTR_WRITEBACK        /* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS       0x00001000      /* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS      0x00000005      /* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-                                VECTOR SIZES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
-#define XSHAL_RESET_VECTOR_ISROM        1
-#define XSHAL_USER_VECTOR_SIZE  0x0000001C
-#define XSHAL_USER_VECTOR_ISROM 0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE    XSHAL_USER_VECTOR_SIZE  /* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE       XSHAL_USER_VECTOR_SIZE  /* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE        0x0000001C
-#define XSHAL_KERNEL_VECTOR_ISROM       0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE    XSHAL_KERNEL_VECTOR_SIZE        /* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE     XSHAL_KERNEL_VECTOR_SIZE        /* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE     0x000000E0
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM    0
-#define XSHAL_WINDOW_VECTORS_SIZE       0x00000180
-#define XSHAL_WINDOW_VECTORS_ISROM      0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE     0x0000000C
-#define XSHAL_INTLEVEL2_VECTOR_ISROM    0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE     0x0000000C
-#define XSHAL_INTLEVEL3_VECTOR_ISROM    0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE     0x0000000C
-#define XSHAL_INTLEVEL4_VECTOR_ISROM    1
-#define XSHAL_DEBUG_VECTOR_SIZE         XSHAL_INTLEVEL4_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM        XSHAL_INTLEVEL4_VECTOR_ISROM
-
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/include/asm-xtensa/xtensa/config-linux_be/tie.h b/include/asm-xtensa/xtensa/config-linux_be/tie.h
deleted file mode 100644
index 3c2e514602f4..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/tie.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
- *
- *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
- *  It was generated for a specific Xtensa processor configuration,
- *  and furthermore for a specific set of TIE source files that extend
- *  basic core functionality.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  It is perfectly normal, however, for the HAL source itself to include this file.
- */
-
-/*
- * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2.1 of the GNU Lesser General Public
- * License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it would be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Further, this software is distributed without any warranty that it is
- * free of the rightful claim of any third person regarding infringement
- * or the like.  Any license provided herein, whether implied or
- * otherwise, applies only to this software file.  Patent licenses, if
- * any, provided herein do not apply to combinations of this program with
- * other software, or any other product whatsoever.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this program; if not, write the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
- * USA.
- */
-
-
-#ifndef XTENSA_CONFIG_TIE_H
-#define XTENSA_CONFIG_TIE_H
-
-#include <xtensa/hal.h>
-
-
-/*----------------------------------------------------------------------
-                                GENERAL
-  ----------------------------------------------------------------------*/
-
-/*
- *  Separators for macros that expand into arrays.
- *  These can be predefined by files that #include this one,
- *  when different separators are required.
- */
-/*  Element separator for macros that expand into 1-dimensional arrays:  */
-#ifndef XCHAL_SEP
-#define XCHAL_SEP                       ,
-#endif
-/*  Array separator for macros that expand into 2-dimensional arrays:  */
-#ifndef XCHAL_SEP2
-#define XCHAL_SEP2                      },{
-#endif
-
-
-
-
-
-
-/*----------------------------------------------------------------------
-                        COPROCESSORS and EXTRA STATE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_CP_NUM                    0       /* number of coprocessors */
-#define XCHAL_CP_MAX                    0       /* max coprocessor id plus one (0 if none) */
-#define XCHAL_CP_MASK                   0x00    /* bitmask of coprocessors by id */
-
-/*  Space for coprocessors' state save areas:  */
-#define XCHAL_CP0_SA_SIZE               0
-#define XCHAL_CP1_SA_SIZE               0
-#define XCHAL_CP2_SA_SIZE               0
-#define XCHAL_CP3_SA_SIZE               0
-#define XCHAL_CP4_SA_SIZE               0
-#define XCHAL_CP5_SA_SIZE               0
-#define XCHAL_CP6_SA_SIZE               0
-#define XCHAL_CP7_SA_SIZE               0
-/*  Minimum required alignments of CP state save areas:  */
-#define XCHAL_CP0_SA_ALIGN              1
-#define XCHAL_CP1_SA_ALIGN              1
-#define XCHAL_CP2_SA_ALIGN              1
-#define XCHAL_CP3_SA_ALIGN              1
-#define XCHAL_CP4_SA_ALIGN              1
-#define XCHAL_CP5_SA_ALIGN              1
-#define XCHAL_CP6_SA_ALIGN              1
-#define XCHAL_CP7_SA_ALIGN              1
-
-/*  Indexing macros:  */
-#define _XCHAL_CP_SA_SIZE(n)            XCHAL_CP ## n ## _SA_SIZE
-#define XCHAL_CP_SA_SIZE(n)             _XCHAL_CP_SA_SIZE(n)    /* n = 0 .. 7 */
-#define _XCHAL_CP_SA_ALIGN(n)           XCHAL_CP ## n ## _SA_ALIGN
-#define XCHAL_CP_SA_ALIGN(n)            _XCHAL_CP_SA_ALIGN(n)   /* n = 0 .. 7 */
-
-
-/*  Space for "extra" state (user special registers and non-cp TIE) save area:  */
-#define XCHAL_EXTRA_SA_SIZE             0
-#define XCHAL_EXTRA_SA_ALIGN            1
-
-/*  Total save area size (extra + all coprocessors)  */
-/*  (not useful until xthal_{save,restore}_all_extra() is implemented,  */
-/*   but included for Tor2 beta; doesn't account for alignment!):  */
-#define XCHAL_CPEXTRA_SA_SIZE_TOR2      0       /* Tor2Beta temporary definition -- do not use */
-
-/*  Combined required alignment for all CP and EXTRA state save areas  */
-/*  (does not include required alignment for any base config registers):  */
-#define XCHAL_CPEXTRA_SA_ALIGN          1
-
-/* ... */
-
-
-#ifdef _ASMLANGUAGE
-/*
- *  Assembly-language specific definitions (assembly macros, etc.).
- */
-#include <xtensa/config/specreg.h>
-
-/********************
- *  Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
- */
-
-/* (none) */
-
-
-/********************
- *  Macros to create functions that save and restore all EXTRA (non-coprocessor) state
- *  (does not include zero-overhead loop registers and non-optional registers).
- */
-
-        /*
-         *  Macro that expands to the body of a function that
-         *  stores the extra (non-coprocessor) optional/custom state.
-         *      Entry:  a2 = ptr to save area in which to save extra state
-         *      Exit:   any register a2-a15 (?) may have been clobbered.
-         */
-        .macro  xchal_extra_store_funcbody
-        .endm
-
-
-        /*
-         *  Macro that expands to the body of a function that
-         *  loads the extra (non-coprocessor) optional/custom state.
-         *      Entry:  a2 = ptr to save area from which to restore extra state
-         *      Exit:   any register a2-a15 (?) may have been clobbered.
-         */
-        .macro  xchal_extra_load_funcbody
-        .endm
-
-
-/********************
- *  Macros to save and restore the state of each TIE coprocessor.
- */
-
-
-
-/********************
- *  Macros to create functions that save and restore the state of *any* TIE coprocessor.
- */
-
-        /*
-         *  Macro that expands to the body of a function
-         *  that stores the selected coprocessor's state (registers etc).
-         *      Entry:  a2 = ptr to save area in which to save cp state
-         *              a3 = coprocessor number
-         *      Exit:   any register a2-a15 (?) may have been clobbered.
-         */
-        .macro  xchal_cpi_store_funcbody
-        .endm
-
-
-        /*
-         *  Macro that expands to the body of a function
-         *  that loads the selected coprocessor's state (registers etc).
-         *      Entry:  a2 = ptr to save area from which to restore cp state
-         *              a3 = coprocessor number
-         *      Exit:   any register a2-a15 (?) may have been clobbered.
-         */
-        .macro  xchal_cpi_load_funcbody
-        .endm
-
-#endif /*_ASMLANGUAGE*/
-
-
-/*
- *  Contents of save areas in terms of libdb register numbers.
- *  NOTE:  CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
- *  it is up to the user of this header file to define these macros
- *  usefully before each expansion of the CONTENTS_LIBDB macros.
- *  (Fields rsv[123] are reserved for future additions; they are currently
- *   set to zero but may be set to some useful values in the future.)
- *
- *      CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
- *      CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
- *      CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
- */
-
-#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM       0
-#define XCHAL_EXTRA_SA_CONTENTS_LIBDB   /* empty */
-
-#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
-#define XCHAL_CP0_SA_CONTENTS_LIBDB     /* empty */
-
-#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
-#define XCHAL_CP1_SA_CONTENTS_LIBDB     /* empty */
-
-#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
-#define XCHAL_CP2_SA_CONTENTS_LIBDB     /* empty */
-
-#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
-#define XCHAL_CP3_SA_CONTENTS_LIBDB     /* empty */
-
-#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
-#define XCHAL_CP4_SA_CONTENTS_LIBDB     /* empty */
-
-#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
-#define XCHAL_CP5_SA_CONTENTS_LIBDB     /* empty */
-
-#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
-#define XCHAL_CP6_SA_CONTENTS_LIBDB     /* empty */
-
-#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
-#define XCHAL_CP7_SA_CONTENTS_LIBDB     /* empty */
-
-
-
-
-
-
-/*----------------------------------------------------------------------
-                                MISC
-  ----------------------------------------------------------------------*/
-
-#if 0   /* is there something equivalent for user TIE? */
-#define XCHAL_CORE_ID                   "linux_be"      /* configuration's alphanumeric core identifier
-                                                           (CoreID) set in the Xtensa Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID           0x00003256      /* software build-unique ID (22-bit) */
-
-/*  These definitions describe the hardware targeted by this software:  */
-#define XCHAL_HW_CONFIGID0              0xC103D1FF      /* config ID reg 0 value (upper 32 of 64 bits) */
-#define XCHAL_HW_CONFIGID1              0x00803256      /* config ID reg 1 value (lower 32 of 64 bits) */
-#define XCHAL_CONFIGID0                 XCHAL_HW_CONFIGID0      /* for backward compatibility only -- don't use! */
-#define XCHAL_CONFIGID1                 XCHAL_HW_CONFIGID1      /* for backward compatibility only -- don't use! */
-#define XCHAL_HW_RELEASE_MAJOR          1050    /* major release of targeted hardware */
-#define XCHAL_HW_RELEASE_MINOR          1       /* minor release of targeted hardware */
-#define XCHAL_HW_RELEASE_NAME           "T1050.1"       /* full release name of targeted hardware */
-#define XTHAL_HW_REL_T1050      1
-#define XTHAL_HW_REL_T1050_1    1
-#define XCHAL_HW_CONFIGID_RELIABLE      1
-#endif /*0*/
-
-
-
-/*----------------------------------------------------------------------
-                                ISA
-  ----------------------------------------------------------------------*/
-
-#if 0   /* these probably don't belong here, but are related to or implemented using TIE */
-#define XCHAL_HAVE_BOOLEANS             0       /* 1 if booleans option configured, 0 otherwise */
-/*  Misc instructions:  */
-#define XCHAL_HAVE_MUL32                0       /* 1 if 32-bit integer multiply option configured, 0 otherwise */
-#define XCHAL_HAVE_MUL32_HIGH           0       /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
-
-#define XCHAL_HAVE_FP                   0       /* 1 if floating point option configured, 0 otherwise */
-#endif /*0*/
-
-
-#endif /*XTENSA_CONFIG_TIE_H*/
-
diff --git a/include/asm-xtensa/xtensa/coreasm.h b/include/asm-xtensa/xtensa/coreasm.h
deleted file mode 100644
index a8cfb54c20a1..000000000000
--- a/include/asm-xtensa/xtensa/coreasm.h
+++ /dev/null
@@ -1,526 +0,0 @@
-#ifndef XTENSA_COREASM_H
-#define XTENSA_COREASM_H
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- * include/asm-xtensa/xtensa/coreasm.h -- assembler-specific
- * definitions that depend on CORE configuration.
- *
- * Source for configuration-independent binaries (which link in a
- * configuration-specific HAL library) must NEVER include this file.
- * It is perfectly normal, however, for the HAL itself to include this
- * file.
- *
- * This file must NOT include xtensa/config/system.h.  Any assembler
- * header file that depends on system information should likely go in
- * a new systemasm.h (or sysasm.h) header file.
- *
- *  NOTE: macro beqi32 is NOT configuration-dependent, and is placed
- *        here til we will have configuration-independent header file.
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License.  See the file "COPYING" in the main directory of
- * this archive for more details.
- *
- * Copyright (C) 2002 Tensilica Inc.
- */
-
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-
-/*
- *  Assembly-language specific definitions (assembly macros, etc.).
- */
-
-/*----------------------------------------------------------------------
- *  find_ms_setbit
- *
- *  This macro finds the most significant bit that is set in <as>
- *  and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
- *  The index counts starting at zero for the lsbit, so the return
- *  value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
- *
- *  Parameters:
- *      <ad>    destination address register (any register)
- *      <as>    source address register
- *      <at>    temporary address register (must be different than <as>)
- *      <base>  constant value added to result (usually 0 or 1)
- *  On entry:
- *      <ad> = undefined if different than <as>
- *      <as> = value whose most significant set bit is to be found
- *      <at> = undefined
- *      no other registers are used by this macro.
- *  On exit:
- *      <ad> = <base> + index of msbit set in original <as>,
- *           = <base> - 1 if original <as> was zero.
- *      <as> clobbered (if not <ad>)
- *      <at> clobbered (if not <ad>)
- *  Example:
- *      find_ms_setbit a0, a4, a0, 0            -- return in a0 index of msbit set in a4
- */
-
-        .macro  find_ms_setbit ad, as, at, base
-#if XCHAL_HAVE_NSA
-        movi    \at, 31+\base
-        nsau    \as, \as        // get index of \as, numbered from msbit (32 if absent)
-        sub     \ad, \at, \as   // get numbering from lsbit (0..31, -1 if absent)
-#else /* XCHAL_HAVE_NSA */
-        movi    \at, \base      // start with result of 0 (point to lsbit of 32)
-
-        beqz    \as, 2f         // special case for zero argument: return -1
-        bltui   \as, 0x10000, 1f        // is it one of the 16 lsbits? (if so, check lower 16 bits)
-        addi    \at, \at, 16    // no, increment result to upper 16 bits (of 32)
-        //srli  \as, \as, 16    // check upper half (shift right 16 bits)
-        extui   \as, \as, 16, 16        // check upper half (shift right 16 bits)
-1:      bltui   \as, 0x100, 1f  // is it one of the 8 lsbits? (if so, check lower 8 bits)
-        addi    \at, \at, 8     // no, increment result to upper 8 bits (of 16)
-        srli    \as, \as, 8     // shift right to check upper 8 bits
-1:      bltui   \as, 0x10, 1f   // is it one of the 4 lsbits? (if so, check lower 4 bits)
-        addi    \at, \at, 4     // no, increment result to upper 4 bits (of 8)
-        srli    \as, \as, 4     // shift right 4 bits to check upper half
-1:      bltui   \as, 0x4, 1f    // is it one of the 2 lsbits? (if so, check lower 2 bits)
-        addi    \at, \at, 2     // no, increment result to upper 2 bits (of 4)
-        srli    \as, \as, 2     // shift right 2 bits to check upper half
-1:      bltui   \as, 0x2, 1f    // is it the lsbit?
-        addi    \at, \at, 2     // no, increment result to upper bit (of 2)
-2:      addi    \at, \at, -1    // (from just above: add 1;  from beqz: return -1)
-        //srli  \as, \as, 1
-1:                              // done! \at contains index of msbit set (or -1 if none set)
-        .if     0x\ad - 0x\at   // destination different than \at ? (works because regs are a0-a15)
-        mov     \ad, \at        // then move result to \ad
-        .endif
-#endif /* XCHAL_HAVE_NSA */
-        .endm   // find_ms_setbit
-
-/*----------------------------------------------------------------------
- *  find_ls_setbit
- *
- *  This macro finds the least significant bit that is set in <as>,
- *  and return its index in <ad>.
- *  Usage is the same as for the find_ms_setbit macro.
- *  Example:
- *      find_ls_setbit a0, a4, a0, 0    -- return in a0 index of lsbit set in a4
- */
-
-        .macro  find_ls_setbit ad, as, at, base
-        neg     \at, \as        // keep only the least-significant bit that is set...
-        and     \as, \at, \as   // ... in \as
-        find_ms_setbit  \ad, \as, \at, \base
-        .endm   // find_ls_setbit
-
-/*----------------------------------------------------------------------
- *  find_ls_one
- *
- *  Same as find_ls_setbit with base zero.
- *  Source (as) and destination (ad) registers must be different.
- *  Provided for backward compatibility.
- */
-
-        .macro  find_ls_one ad, as
-        find_ls_setbit  \ad, \as, \ad, 0
-        .endm   // find_ls_one
-
-/*----------------------------------------------------------------------
- *  floop, floopnez, floopgtz, floopend
- *
- *  These macros are used for fast inner loops that
- *  work whether or not the Loops options is configured.
- *  If the Loops option is configured, they simply use
- *  the zero-overhead LOOP instructions; otherwise
- *  they use explicit decrement and branch instructions.
- *
- *  They are used in pairs, with floop, floopnez or floopgtz
- *  at the beginning of the loop, and floopend at the end.
- *
- *  Each pair of loop macro calls must be given the loop count
- *  address register and a unique label for that loop.
- *
- *  Example:
- *
- *      movi     a3, 16     // loop 16 times
- *      floop    a3, myloop1
- *      :
- *      bnez     a7, end1       // exit loop if a7 != 0
- *      :
- *      floopend a3, myloop1
- *  end1:
- *
- *  Like the LOOP instructions, these macros cannot be
- *  nested, must include at least one instruction,
- *  cannot call functions inside the loop, etc.
- *  The loop can be exited by jumping to the instruction
- *  following floopend (or elsewhere outside the loop),
- *  or continued by jumping to a NOP instruction placed
- *  immediately before floopend.
- *
- *  Unlike LOOP instructions, the register passed to floop*
- *  cannot be used inside the loop, because it is used as
- *  the loop counter if the Loops option is not configured.
- *  And its value is undefined after exiting the loop.
- *  And because the loop counter register is active inside
- *  the loop, you can't easily use this construct to loop
- *  across a register file using ROTW as you might with LOOP
- *  instructions, unless you copy the loop register along.
- */
-
-        /*  Named label version of the macros:  */
-
-        .macro  floop           ar, endlabel
-        floop_          \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
-        .endm
-
-        .macro  floopnez        ar, endlabel
-        floopnez_       \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
-        .endm
-
-        .macro  floopgtz        ar, endlabel
-        floopgtz_       \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
-        .endm
-
-        .macro  floopend        ar, endlabel
-        floopend_       \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
-        .endm
-
-        /*  Numbered local label version of the macros:  */
-#if 0 /*UNTESTED*/
-        .macro  floop89         ar
-        floop_          \ar, 8, 9f
-        .endm
-
-        .macro  floopnez89      ar
-        floopnez_       \ar, 8, 9f
-        .endm
-
-        .macro  floopgtz89      ar
-        floopgtz_       \ar, 8, 9f
-        .endm
-
-        .macro  floopend89      ar
-        floopend_       \ar, 8b, 9
-        .endm
-#endif /*0*/
-
-        /*  Underlying version of the macros:  */
-
-        .macro  floop_  ar, startlabel, endlabelref
-        .ifdef  _infloop_
-        .if     _infloop_
-        .err    // Error: floop cannot be nested
-        .endif
-        .endif
-        .set    _infloop_, 1
-#if XCHAL_HAVE_LOOPS
-        loop    \ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
-\startlabel:
-        addi    \ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
-        .endm   // floop_
-
-        .macro  floopnez_       ar, startlabel, endlabelref
-        .ifdef  _infloop_
-        .if     _infloop_
-        .err    // Error: floopnez cannot be nested
-        .endif
-        .endif
-        .set    _infloop_, 1
-#if XCHAL_HAVE_LOOPS
-        loopnez \ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
-        beqz    \ar, \endlabelref
-\startlabel:
-        addi    \ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
-        .endm   // floopnez_
-
-        .macro  floopgtz_       ar, startlabel, endlabelref
-        .ifdef  _infloop_
-        .if     _infloop_
-        .err    // Error: floopgtz cannot be nested
-        .endif
-        .endif
-        .set    _infloop_, 1
-#if XCHAL_HAVE_LOOPS
-        loopgtz \ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
-        bltz    \ar, \endlabelref
-        beqz    \ar, \endlabelref
-\startlabel:
-        addi    \ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
-        .endm   // floopgtz_
-
-
-        .macro  floopend_       ar, startlabelref, endlabel
-        .ifndef _infloop_
-        .err    // Error: floopend without matching floopXXX
-        .endif
-        .ifeq   _infloop_
-        .err    // Error: floopend without matching floopXXX
-        .endif
-        .set    _infloop_, 0
-#if ! XCHAL_HAVE_LOOPS
-        bnez    \ar, \startlabelref
-#endif /* XCHAL_HAVE_LOOPS */
-\endlabel:
-        .endm   // floopend_
-
-/*----------------------------------------------------------------------
- *  crsil  --  conditional RSIL (read/set interrupt level)
- *
- *  Executes the RSIL instruction if it exists, else just reads PS.
- *  The RSIL instruction does not exist in the new exception architecture
- *  if the interrupt option is not selected.
- */
-
-        .macro  crsil   ar, newlevel
-#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
-        rsil    \ar, \newlevel
-#else
-        rsr     \ar, PS
-#endif
-        .endm   // crsil
-
-/*----------------------------------------------------------------------
- *  window_spill{4,8,12}
- *
- *  These macros spill callers' register windows to the stack.
- *  They work for both privileged and non-privileged tasks.
- *  Must be called from a windowed ABI context, eg. within
- *  a windowed ABI function (ie. valid stack frame, window
- *  exceptions enabled, not in exception mode, etc).
- *
- *  This macro requires a single invocation of the window_spill_common
- *  macro in the same assembly unit and section.
- *
- *  Note that using window_spill{4,8,12} macros is more efficient
- *  than calling a function implemented using window_spill_function,
- *  because the latter needs extra code to figure out the size of
- *  the call to the spilling function.
- *
- *  Example usage:
- *
- *              .text
- *              .align  4
- *              .global some_function
- *              .type   some_function,@function
- *      some_function:
- *              entry   a1, 16
- *              :
- *              :
- *
- *              window_spill4   // spill windows of some_function's callers; preserves a0..a3 only;
- *                              // to use window_spill{8,12} in this example function we'd have
- *                              // to increase space allocated by the entry instruction, because
- *                              // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
- *                              // for call8/window_spill8 or call12/window_spill12 respectively.
- *              :
- *
- *              retw
- *
- *              window_spill_common     // instantiates code used by window_spill4
- *
- *
- *  On entry:
- *      none (if window_spill4)
- *      stack frame has enough space allocated for call8 (if window_spill8)
- *      stack frame has enough space allocated for call12 (if window_spill12)
- *  On exit:
- *       a4..a15 clobbered (if window_spill4)
- *       a8..a15 clobbered (if window_spill8)
- *      a12..a15 clobbered (if window_spill12)
- *      no caller windows are in live registers
- */
-
-        .macro  window_spill4
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
-        movi    a15, 0                  // for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
-        call4   .L__wdwspill_assist28   // call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
-        call4   .L__wdwspill_assist60   // call deep enough to clear out any live callers
-# endif
-#endif
-        .endm   // window_spill4
-
-        .macro  window_spill8
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
-        movi    a15, 0                  // for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
-        call8   .L__wdwspill_assist24   // call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
-        call8   .L__wdwspill_assist56   // call deep enough to clear out any live callers
-# endif
-#endif
-        .endm   // window_spill8
-
-        .macro  window_spill12
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
-        movi    a15, 0                  // for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
-        call12  .L__wdwspill_assist20   // call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
-        call12  .L__wdwspill_assist52   // call deep enough to clear out any live callers
-# endif
-#endif
-        .endm   // window_spill12
-
-/*----------------------------------------------------------------------
- *  window_spill_function
- *
- *  This macro outputs a function that will spill its caller's callers'
- *  register windows to the stack.  Eg. it could be used to implement
- *  a version of xthal_window_spill() that works in non-privileged tasks.
- *  This works for both privileged and non-privileged tasks.
- *
- *  Typical usage:
- *
- *              .text
- *              .align  4
- *              .global my_spill_function
- *              .type   my_spill_function,@function
- *      my_spill_function:
- *              window_spill_function
- *
- *  On entry to resulting function:
- *      none
- *  On exit from resulting function:
- *      none (no caller windows are in live registers)
- */
-
-        .macro  window_spill_function
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 32
-        entry   sp, 48
-        bbci.l  a0, 31, 1f              // branch if called with call4
-        bbsi.l  a0, 30, 2f              // branch if called with call12
-        call8   .L__wdwspill_assist16   // called with call8, only need another 8
-        retw
-1:      call12  .L__wdwspill_assist16   // called with call4, only need another 12
-        retw
-2:      call4   .L__wdwspill_assist16   // called with call12, only need another 4
-        retw
-# elif XCHAL_NUM_AREGS == 64
-        entry   sp, 48
-        bbci.l  a0, 31, 1f              // branch if called with call4
-        bbsi.l  a0, 30, 2f              // branch if called with call12
-        call4   .L__wdwspill_assist52   // called with call8, only need a call4
-        retw
-1:      call8   .L__wdwspill_assist52   // called with call4, only need a call8
-        retw
-2:      call12  .L__wdwspill_assist40   // called with call12, can skip a call12
-        retw
-# elif XCHAL_NUM_AREGS == 16
-        entry   sp, 16
-        bbci.l  a0, 31, 1f      // branch if called with call4
-        bbsi.l  a0, 30, 2f      // branch if called with call12
-        movi    a7, 0           // called with call8
-        retw
-1:      movi    a11, 0          // called with call4
-2:      retw                    // if called with call12, everything already spilled
-
-//      movi    a15, 0          // trick to spill all but the direct caller
-//      j       1f
-//      //  The entry instruction is magical in the assembler (gets auto-aligned)
-//      //  so we have to jump to it to avoid falling through the padding.
-//      //  We need entry/retw to know where to return.
-//1:    entry   sp, 16
-//      retw
-# else
-#  error "unrecognized address register file size"
-# endif
-#endif /* XCHAL_HAVE_WINDOWED */
-        window_spill_common
-        .endm   // window_spill_function
-
-/*----------------------------------------------------------------------
- *  window_spill_common
- *
- *  Common code used by any number of invocations of the window_spill##
- *  and window_spill_function macros.
- *
- *  Must be instantiated exactly once within a given assembly unit,
- *  within call/j range of and same section as window_spill##
- *  macro invocations for that assembly unit.
- *  (Is automatically instantiated by the window_spill_function macro.)
- */
-
-        .macro  window_spill_common
-#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
-        .ifndef .L__wdwspill_defined
-# if XCHAL_NUM_AREGS >= 64
-.L__wdwspill_assist60:
-        entry   sp, 32
-        call8   .L__wdwspill_assist52
-        retw
-.L__wdwspill_assist56:
-        entry   sp, 16
-        call4   .L__wdwspill_assist52
-        retw
-.L__wdwspill_assist52:
-        entry   sp, 48
-        call12  .L__wdwspill_assist40
-        retw
-.L__wdwspill_assist40:
-        entry   sp, 48
-        call12  .L__wdwspill_assist28
-        retw
-# endif
-.L__wdwspill_assist28:
-        entry   sp, 48
-        call12  .L__wdwspill_assist16
-        retw
-.L__wdwspill_assist24:
-        entry   sp, 32
-        call8   .L__wdwspill_assist16
-        retw
-.L__wdwspill_assist20:
-        entry   sp, 16
-        call4   .L__wdwspill_assist16
-        retw
-.L__wdwspill_assist16:
-        entry   sp, 16
-        movi    a15, 0
-        retw
-        .set    .L__wdwspill_defined, 1
-        .endif
-#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
-        .endm   // window_spill_common
-
-/*----------------------------------------------------------------------
- *  beqi32
- *
- *  macro implements version of beqi for arbitrary 32-bit immidiate value
- *
- *     beqi32 ax, ay, imm32, label
- *
- *  Compares value in register ax with imm32 value and jumps to label if
- *  equal. Clobberes register ay if needed
- *
- */
-   .macro beqi32        ax, ay, imm, label
-    .ifeq ((\imm-1) & ~7)       // 1..8 ?
-                beqi    \ax, \imm, \label
-    .else
-      .ifeq (\imm+1)            // -1 ?
-                beqi    \ax, \imm, \label
-      .else
-        .ifeq (\imm)            // 0 ?
-                beqz    \ax, \label
-        .else
-                //  We could also handle immediates 10,12,16,32,64,128,256
-                //  but it would be a long macro...
-                movi    \ay, \imm
-                beq     \ax, \ay, \label
-        .endif
-      .endif
-    .endif
-   .endm // beqi32
-
-#endif /*XTENSA_COREASM_H*/
-
diff --git a/include/asm-xtensa/xtensa/corebits.h b/include/asm-xtensa/xtensa/corebits.h
deleted file mode 100644
index e578ade41632..000000000000
--- a/include/asm-xtensa/xtensa/corebits.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef XTENSA_COREBITS_H
-#define XTENSA_COREBITS_H
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- * xtensa/corebits.h - Xtensa Special Register field positions and masks.
- *
- * (In previous releases, these were defined in specreg.h, a generated file.
- *  This file is not generated, i.e. it is processor configuration independent.)
- */
-
-
-/*  EXCCAUSE register fields:  */
-#define EXCCAUSE_EXCCAUSE_SHIFT 0
-#define EXCCAUSE_EXCCAUSE_MASK  0x3F
-/*  Exception causes (mostly incomplete!):  */
-#define EXCCAUSE_ILLEGAL                0
-#define EXCCAUSE_SYSCALL                1
-#define EXCCAUSE_IFETCHERROR            2
-#define EXCCAUSE_LOADSTOREERROR         3
-#define EXCCAUSE_LEVEL1INTERRUPT        4
-#define EXCCAUSE_ALLOCA                 5
-
-/*  PS register fields:  */
-#define PS_WOE_SHIFT            18
-#define PS_WOE_MASK             0x00040000
-#define PS_WOE                  PS_WOE_MASK
-#define PS_CALLINC_SHIFT        16
-#define PS_CALLINC_MASK         0x00030000
-#define PS_CALLINC(n)           (((n)&3)<<PS_CALLINC_SHIFT)     /* n = 0..3 */
-#define PS_OWB_SHIFT            8
-#define PS_OWB_MASK             0x00000F00
-#define PS_OWB(n)               (((n)&15)<<PS_OWB_SHIFT)        /* n = 0..15 (or 0..7) */
-#define PS_RING_SHIFT           6
-#define PS_RING_MASK            0x000000C0
-#define PS_RING(n)              (((n)&3)<<PS_RING_SHIFT)        /* n = 0..3 */
-#define PS_UM_SHIFT             5
-#define PS_UM_MASK              0x00000020
-#define PS_UM                   PS_UM_MASK
-#define PS_EXCM_SHIFT           4
-#define PS_EXCM_MASK            0x00000010
-#define PS_EXCM                 PS_EXCM_MASK
-#define PS_INTLEVEL_SHIFT       0
-#define PS_INTLEVEL_MASK        0x0000000F
-#define PS_INTLEVEL(n)          ((n)&PS_INTLEVEL_MASK)          /* n = 0..15 */
-/*  Backward compatibility (deprecated):  */
-#define PS_PROGSTACK_SHIFT      PS_UM_SHIFT
-#define PS_PROGSTACK_MASK       PS_UM_MASK
-#define PS_PROG_SHIFT           PS_UM_SHIFT
-#define PS_PROG_MASK            PS_UM_MASK
-#define PS_PROG                 PS_UM
-
-/*  DBREAKCn register fields:  */
-#define DBREAKC_MASK_SHIFT              0
-#define DBREAKC_MASK_MASK               0x0000003F
-#define DBREAKC_LOADBREAK_SHIFT         30
-#define DBREAKC_LOADBREAK_MASK          0x40000000
-#define DBREAKC_STOREBREAK_SHIFT        31
-#define DBREAKC_STOREBREAK_MASK         0x80000000
-
-/*  DEBUGCAUSE register fields:  */
-#define DEBUGCAUSE_DEBUGINT_SHIFT       5
-#define DEBUGCAUSE_DEBUGINT_MASK        0x20    /* debug interrupt */
-#define DEBUGCAUSE_BREAKN_SHIFT         4
-#define DEBUGCAUSE_BREAKN_MASK          0x10    /* BREAK.N instruction */
-#define DEBUGCAUSE_BREAK_SHIFT          3
-#define DEBUGCAUSE_BREAK_MASK           0x08    /* BREAK instruction */
-#define DEBUGCAUSE_DBREAK_SHIFT         2
-#define DEBUGCAUSE_DBREAK_MASK          0x04    /* DBREAK match */
-#define DEBUGCAUSE_IBREAK_SHIFT         1
-#define DEBUGCAUSE_IBREAK_MASK          0x02    /* IBREAK match */
-#define DEBUGCAUSE_ICOUNT_SHIFT         0
-#define DEBUGCAUSE_ICOUNT_MASK          0x01    /* ICOUNT would increment to zero */
-
-#endif /*XTENSA_COREBITS_H*/
-
diff --git a/include/asm-xtensa/xtensa/hal.h b/include/asm-xtensa/xtensa/hal.h
deleted file mode 100644
index d10472505454..000000000000
--- a/include/asm-xtensa/xtensa/hal.h
+++ /dev/null
@@ -1,822 +0,0 @@
-#ifndef XTENSA_HAL_H
-#define XTENSA_HAL_H
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- * include/asm-xtensa/xtensa/hal.h -- contains a definition of the
- * Core HAL interface.
- *
- * All definitions in this header file are independent of any specific
- * Xtensa processor configuration.  Thus an OS or other software can
- * include this header file and be compiled into configuration-
- * independent objects that can be distributed and eventually linked
- * to the HAL library (libhal.a) to create a configuration-specific
- * final executable.
- *
- * Certain definitions, however, are release-specific -- such as the
- * XTHAL_RELEASE_xxx macros (or additions made in later releases).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002 Tensilica Inc.
- */
-
-
-/*----------------------------------------------------------------------
-                         Constant Definitions
-                        (shared with assembly)
-  ----------------------------------------------------------------------*/
-
-/*  Software release information (not configuration-specific!):  */
-#define XTHAL_RELEASE_MAJOR     1050
-#define XTHAL_RELEASE_MINOR     0
-#define XTHAL_RELEASE_NAME      "T1050.0-2002-08-06-eng0"
-#define XTHAL_RELEASE_INTERNAL  "2002-08-06-eng0"
-#define XTHAL_REL_T1050 1
-#define XTHAL_REL_T1050_0       1
-#define XTHAL_REL_T1050_0_2002  1
-#define XTHAL_REL_T1050_0_2002_08       1
-#define XTHAL_REL_T1050_0_2002_08_06    1
-#define XTHAL_REL_T1050_0_2002_08_06_ENG0       1
-
-/*  HAL version numbers (these names are for backward compatibility):  */
-#define XTHAL_MAJOR_REV         XTHAL_RELEASE_MAJOR
-#define XTHAL_MINOR_REV         XTHAL_RELEASE_MINOR
-/*
- *  A bit of software release history on values of XTHAL_{MAJOR,MINOR}_REV:
- *
- *      Release         MAJOR   MINOR           Comment
- *      =======         =====   =====           =======
- *      T1015.n         n/a     n/a             (HAL not yet available)
- *      T1020.{0,1,2}   0       1               (HAL beta)
- *      T1020.{3,4}     0       2               First release.
- *      T1020.n (n>4)   0       2 or >3         (TBD)
- *      T1030.0         0       1               (HAL beta)
- *      T1030.{1,2}     0       3               Equivalent to first release.
- *      T1030.n (n>=3)  0       >= 3            (TBD)
- *      T1040.n         1040    n               Full CHAL available from T1040.2
- *      T1050.n         1050    n               Current release.
- *
- *
- *  Note:  there is a distinction between the software release with
- *  which something is compiled (accessible using XTHAL_RELEASE_* macros)
- *  and the software release with which the HAL library was compiled
- *  (accessible using Xthal_release_* global variables).  This
- *  distinction is particularly relevant for vendors that distribute
- *  configuration-independent binaries (eg. an OS), where their customer
- *  might link it with a HAL of a different Xtensa software release.
- *  In this case, it may be appropriate for the OS to verify at run-time
- *  whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
- *  [Guidelines as to which release is compatible with which are not
- *  currently provided explicitly, but might be inferred from reading
- *  OSKit documentation for all releases -- compatibility is also highly
- *  dependent on which HAL features are used.  Each release is usually
- *  backward compatible, with very few exceptions if any.]
- *
- *  Notes:
- *      Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
- *      Tornado 2.0.2 supported in T1040.2+, and T1050.
- *      Compile-time HAL port of NucleusPlus supported by T1040.2+ and T1050.
- */
-
-
-/*
- *  Architectural limits, independent of configuration.
- *  Note that these are ISA-defined limits, not micro-architecture implementation
- *  limits enforced by the Xtensa Processor Generator (which may be stricter than
- *  these below).
- */
-#define XTHAL_MAX_CPS           8       /* max number of coprocessors (0..7) */
-#define XTHAL_MAX_INTERRUPTS    32      /* max number of interrupts (0..31) */
-#define XTHAL_MAX_INTLEVELS     16      /* max number of interrupt levels (0..15) */
-                                        /* (as of T1040, implementation limit is 7: 0..6) */
-#define XTHAL_MAX_TIMERS        4       /* max number of timers (CCOMPARE0..CCOMPARE3) */
-                                        /* (as of T1040, implementation limit is 3: 0..2) */
-
-/*  Misc:  */
-#define XTHAL_LITTLEENDIAN              0
-#define XTHAL_BIGENDIAN                 1
-
-
-/*  Interrupt types:  */
-#define XTHAL_INTTYPE_UNCONFIGURED      0
-#define XTHAL_INTTYPE_SOFTWARE          1
-#define XTHAL_INTTYPE_EXTERN_EDGE       2
-#define XTHAL_INTTYPE_EXTERN_LEVEL      3
-#define XTHAL_INTTYPE_TIMER             4
-#define XTHAL_INTTYPE_NMI               5
-#define XTHAL_MAX_INTTYPES              6       /* number of interrupt types */
-
-/*  Timer related:  */
-#define XTHAL_TIMER_UNCONFIGURED        -1      /* Xthal_timer_interrupt[] value for non-existent timers */
-#define XTHAL_TIMER_UNASSIGNED  XTHAL_TIMER_UNCONFIGURED        /* (for backwards compatibility only) */
-
-
-/*  Access Mode bits (tentative):  */   /* bit abbr unit short_name       PPC equ - Description */
-#define XTHAL_AMB_EXCEPTION     0       /* 001 E EX fls: EXception        none    - generate exception on any access (aka "illegal") */
-#define XTHAL_AMB_HITCACHE      1       /* 002 C CH fls: use Cache on Hit ~(I CI) - use cache on hit -- way from tag match [or H HC, or U UC] (ISA: same, except for Isolate case) */
-#define XTHAL_AMB_ALLOCATE      2       /* 004 A AL fl?: ALlocate         none    - refill cache on miss -- way from LRU [or F FI fill] (ISA: Read/Write Miss Refill) */
-#define XTHAL_AMB_WRITETHRU     3       /* 008 W WT --s: WriteThrough     W WT    - store immediately to memory (ISA: same) */
-#define XTHAL_AMB_ISOLATE       4       /* 010 I IS fls: ISolate          none    - use cache regardless of hit-vs-miss -- way from vaddr (ISA: use-cache-on-miss+hit) */
-#define XTHAL_AMB_GUARD         5       /* 020 G GU ?l?: GUard            G *     - non-speculative; spec/replay refs not permitted */
-#if 0
-#define XTHAL_AMB_ORDERED       x       /* 000 O OR fls: ORdered          G *     - mem accesses cannot be out of order */
-#define XTHAL_AMB_FUSEWRITES    x       /* 000 F FW --s: FuseWrites       none    - allow combining/merging multiple writes (to same datapath data unit) into one (implied by writeback) */
-#define XTHAL_AMB_COHERENT      x       /* 000 M MC fl?: Mem/MP Coherent  M       - on reads, other CPUs/bus-masters may need to supply data */
-#define XTHAL_AMB_TRUSTED       x       /* 000 T TR ?l?: TRusted          none    - memory will not bus error (if it does, handle as fatal imprecise interrupt) */
-#define XTHAL_AMB_PREFETCH      x       /* 000 P PR fl?: PRefetch         none    - on refill, read line+1 into prefetch buffers */
-#define XTHAL_AMB_STREAM        x       /* 000 S ST ???: STreaming        none    - access one of N stream buffers */
-#endif /*0*/
-
-#define XTHAL_AM_EXCEPTION      (1<<XTHAL_AMB_EXCEPTION)
-#define XTHAL_AM_HITCACHE       (1<<XTHAL_AMB_HITCACHE)
-#define XTHAL_AM_ALLOCATE       (1<<XTHAL_AMB_ALLOCATE)
-#define XTHAL_AM_WRITETHRU      (1<<XTHAL_AMB_WRITETHRU)
-#define XTHAL_AM_ISOLATE        (1<<XTHAL_AMB_ISOLATE)
-#define XTHAL_AM_GUARD          (1<<XTHAL_AMB_GUARD)
-#if 0
-#define XTHAL_AM_ORDERED        (1<<XTHAL_AMB_ORDERED)
-#define XTHAL_AM_FUSEWRITES     (1<<XTHAL_AMB_FUSEWRITES)
-#define XTHAL_AM_COHERENT       (1<<XTHAL_AMB_COHERENT)
-#define XTHAL_AM_TRUSTED        (1<<XTHAL_AMB_TRUSTED)
-#define XTHAL_AM_PREFETCH       (1<<XTHAL_AMB_PREFETCH)
-#define XTHAL_AM_STREAM         (1<<XTHAL_AMB_STREAM)
-#endif /*0*/
-
-/*
- *  Allowed Access Modes (bit combinations).
- *
- *  Columns are:
- *  "FOGIWACE"
- *      Access mode bits (see XTHAL_AMB_xxx above).
- *      <letter> = bit is set
- *      '-'      = bit is clear
- *      '.'      = bit is irrelevant / don't care, as follows:
- *                      E=1 makes all others irrelevant
- *                      W,F relevant only for stores
- *  "2345"
- *      Indicates which Xtensa releases support the corresponding
- *      access mode.  Releases for each character column are:
- *              2 = prior to T1020.2:   T1015 (V1.5), T1020.0, T1020.1
- *              3 = T1020.2 and later:  T1020.2+, T1030
- *              4 = T1040
- *              5 = T1050 (maybe)
- *      And the character column contents are:
- *              <number> = support by release(s)
- *              "." = unsupported by release(s)
- *              "?" = support unknown
- */
-                                        /* FOGIWACE 2345 */
-/*  For instruction fetch:  */
-#define XTHAL_FAM_EXCEPTION     0x001   /* .......E 2345 exception */
-#define XTHAL_FAM_ISOLATE       0x012   /* .--I.-C- .... isolate */
-#define XTHAL_FAM_BYPASS        0x000   /* .---.--- 2345 bypass */
-#define XTHAL_FAM_NACACHED      0x002   /* .---.-C- .... cached no-allocate (frozen) */
-#define XTHAL_FAM_CACHED        0x006   /* .---.AC- 2345 cached */
-/*  For data load:  */
-#define XTHAL_LAM_EXCEPTION     0x001   /* .......E 2345 exception */
-#define XTHAL_LAM_ISOLATE       0x012   /* .--I.-C- 2345 isolate */
-#define XTHAL_LAM_BYPASS        0x000   /* .O--.--- 2... bypass speculative */
-#define XTHAL_LAM_BYPASSG       0x020   /* .OG-.--- .345 bypass guarded */
-#define XTHAL_LAM_NACACHED      0x002   /* .O--.-C- 2... cached no-allocate speculative */
-#define XTHAL_LAM_NACACHEDG     0x022   /* .OG-.-C- .345 cached no-allocate guarded */
-#define XTHAL_LAM_CACHED        0x006   /* .---.AC- 2345 cached speculative */
-#define XTHAL_LAM_CACHEDG       0x026   /* .?G-.AC- .... cached guarded */
-/*  For data store:  */
-#define XTHAL_SAM_EXCEPTION     0x001   /* .......E 2345 exception */
-#define XTHAL_SAM_ISOLATE       0x032   /* .-GI--C- 2345 isolate */
-#define XTHAL_SAM_BYPASS        0x028   /* -OG-W--- 2345 bypass */
-/*efine XTHAL_SAM_BYPASSF       0x028*/ /* F-G-W--- ...? bypass write-combined */
-#define XTHAL_SAM_WRITETHRU     0x02A   /* -OG-W-C- 234? writethrough */
-/*efine XTHAL_SAM_WRITETHRUF    0x02A*/ /* F-G-W-C- ...5 writethrough write-combined */
-#define XTHAL_SAM_WRITEALLOC    0x02E   /* -OG-WAC- ...? writethrough-allocate */
-/*efine XTHAL_SAM_WRITEALLOCF   0x02E*/ /* F-G-WAC- ...? writethrough-allocate write-combined */
-#define XTHAL_SAM_WRITEBACK     0x026   /* F-G--AC- ...5 writeback */
-
-#if 0
-/*
-    Cache attribute encoding for CACHEATTR (per ISA):
-    (Note:  if this differs from ISA Ref Manual, ISA has precedence)
-
-        Inst-fetches    Loads           Stores
-        -------------   ------------    -------------
-0x0     FCA_EXCEPTION  ?LCA_NACACHED_G* SCA_WRITETHRU   "uncached"
-0x1     FCA_CACHED      LCA_CACHED      SCA_WRITETHRU   cached
-0x2     FCA_BYPASS      LCA_BYPASS_G*   SCA_BYPASS      bypass
-0x3     FCA_CACHED      LCA_CACHED      SCA_WRITEALLOCF write-allocate
-                     or LCA_EXCEPTION   SCA_EXCEPTION   (if unimplemented)
-0x4     FCA_CACHED      LCA_CACHED      SCA_WRITEBACK   write-back
-                     or LCA_EXCEPTION   SCA_EXCEPTION   (if unimplemented)
-0x5..D  FCA_EXCEPTION   LCA_EXCEPTION   SCA_EXCEPTION   (reserved)
-0xE     FCA_EXCEPTION   LCA_ISOLATE     SCA_ISOLATE     isolate
-0xF     FCA_EXCEPTION   LCA_EXCEPTION   SCA_EXCEPTION   illegal
-     *  Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
-*/
-#endif /*0*/
-
-
-#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------
-                             HAL
-  ----------------------------------------------------------------------*/
-
-/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
-extern const unsigned int Xthal_rev_no;
-
-
-/*----------------------------------------------------------------------
-                        Processor State
-  ----------------------------------------------------------------------*/
-/* save & restore the extra processor state */
-extern void xthal_save_extra(void *base);
-extern void xthal_restore_extra(void *base);
-
-extern void xthal_save_cpregs(void *base, int);
-extern void xthal_restore_cpregs(void *base, int);
-
-/*extern void xthal_save_all_extra(void *base);*/
-/*extern void xthal_restore_all_extra(void *base);*/
-
-/* space for processor state */
-extern const unsigned int Xthal_extra_size;
-extern const unsigned int Xthal_extra_align;
-/* space for TIE register files */
-extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
-extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
-
-/* total of space for the processor state (for Tor2) */
-extern const unsigned int Xthal_all_extra_size;
-extern const unsigned int Xthal_all_extra_align;
-
-/* initialize the extra processor */
-/*extern void xthal_init_extra(void);*/
-/* initialize the TIE coprocessor */
-/*extern void xthal_init_cp(int);*/
-
-/* initialize the extra processor */
-extern void xthal_init_mem_extra(void *);
-/* initialize the TIE coprocessor */
-extern void xthal_init_mem_cp(void *, int);
-
-/* validate & invalidate the TIE register file */
-extern void xthal_validate_cp(int);
-extern void xthal_invalidate_cp(int);
-
-/* the number of TIE coprocessors contiguous from zero (for Tor2) */
-extern const unsigned int Xthal_num_coprocessors;
-
-/* actual number of coprocessors */
-extern const unsigned char Xthal_cp_num;
-/* index of highest numbered coprocessor, plus one */
-extern const unsigned char Xthal_cp_max;
-/* index of highest allowed coprocessor number, per cfg, plus one */
-/*extern const unsigned char Xthal_cp_maxcfg;*/
-/* bitmask of which coprocessors are present */
-extern const unsigned int  Xthal_cp_mask;
-
-/* read and write cpenable register */
-extern void xthal_set_cpenable(unsigned);
-extern unsigned xthal_get_cpenable(void);
-
-/* read & write extra state register */
-/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
-/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
-
-/* read & write a TIE coprocessor register */
-/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
-/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
-
-/* return coprocessor number based on register */
-/*extern int xthal_which_cp(unsigned reg);*/
-
-/*----------------------------------------------------------------------
-                                Interrupts
-  ----------------------------------------------------------------------*/
-
-/* the number of interrupt levels */
-extern const unsigned char Xthal_num_intlevels;
-/* the number of interrupts */
-extern const unsigned char Xthal_num_interrupts;
-
-/* mask for level of interrupts */
-extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
-/* mask for level 0 to N interrupts */
-extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
-
-/* level of each interrupt */
-extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
-
-/* type per interrupt */
-extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
-
-/* masks of each type of interrupt */
-extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
-
-/* interrupt numbers assigned to each timer interrupt */
-extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
-
-/***  Virtual interrupt prioritization:  ***/
-
-/*  Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities:  */
-extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
-extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
-
-/*  Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints:  */
-extern unsigned xthal_int_enable(unsigned);
-extern unsigned xthal_int_disable(unsigned);
-
-/*  Set/get virtual priority of an interrupt:  */
-extern int      xthal_set_int_vpri(int intnum, int vpri);
-extern int      xthal_get_int_vpri(int intnum);
-
-/*  Set/get interrupt lockout level for exclusive access to virtual priority data structures:  */
-extern void     xthal_set_vpri_locklevel(unsigned intlevel);
-extern unsigned xthal_get_vpri_locklevel(void);
-
-/*  Set/get current virtual interrupt priority:  */
-extern unsigned xthal_set_vpri(unsigned vpri);
-extern unsigned xthal_get_vpri(unsigned vpri);
-extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
-extern unsigned xthal_set_vpri_lock(void);
-
-
-
-/*----------------------------------------------------------------------
-                        Generic Interrupt Trampolining Support
-  ----------------------------------------------------------------------*/
-
-typedef void (XtHalVoidFunc)(void);
-
-/*
- *  Bitmask of interrupts currently trampolining down:
- */
-extern unsigned Xthal_tram_pending;
-
-/*
- *  Bitmask of which interrupts currently trampolining down
- *  synchronously are actually enabled; this bitmask is necessary
- *  because INTENABLE cannot hold that state (sync-trampolining
- *  interrupts must be kept disabled while trampolining);
- *  in the current implementation, any bit set here is not set
- *  in INTENABLE, and vice-versa; once a sync-trampoline is
- *  handled (at level one), its enable bit must be moved from
- *  here to INTENABLE:
- */
-extern unsigned Xthal_tram_enabled;
-
-/*
- *  Bitmask of interrupts configured for sync trampolining:
- */
-extern unsigned Xthal_tram_sync;
-
-
-/*  Trampoline support functions:  */
-extern unsigned  xthal_tram_pending_to_service( void );
-extern void      xthal_tram_done( unsigned serviced_mask );
-extern int       xthal_tram_set_sync( int intnum, int sync );
-extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
-
-/*  INTENABLE,INTREAD,INTSET,INTCLEAR register access functions:  */
-extern unsigned  xthal_get_intenable( void );
-extern void      xthal_set_intenable( unsigned );
-extern unsigned  xthal_get_intread( void );
-extern void      xthal_set_intset( unsigned );
-extern void      xthal_set_intclear( unsigned );
-
-
-/*----------------------------------------------------------------------
-                                Register Windows
-  ----------------------------------------------------------------------*/
-
-/* number of registers in register window */
-extern const unsigned int  Xthal_num_aregs;
-extern const unsigned char Xthal_num_aregs_log2;
-
-/*  This spill any live register windows (other than the caller's):  */
-extern void      xthal_window_spill( void );
-
-
-/*----------------------------------------------------------------------
-                                Cache
-  ----------------------------------------------------------------------*/
-
-/* size of the cache lines in log2(bytes) */
-extern const unsigned char Xthal_icache_linewidth;
-extern const unsigned char Xthal_dcache_linewidth;
-/* size of the cache lines in bytes */
-extern const unsigned short Xthal_icache_linesize;
-extern const unsigned short Xthal_dcache_linesize;
-/* number of cache sets in log2(lines per way) */
-extern const unsigned char Xthal_icache_setwidth;
-extern const unsigned char Xthal_dcache_setwidth;
-/* cache set associativity (number of ways) */
-extern const unsigned int  Xthal_icache_ways;
-extern const unsigned int  Xthal_dcache_ways;
-/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
-extern const unsigned int  Xthal_icache_size;
-extern const unsigned int  Xthal_dcache_size;
-/* cache features */
-extern const unsigned char Xthal_dcache_is_writeback;
-extern const unsigned char Xthal_icache_line_lockable;
-extern const unsigned char Xthal_dcache_line_lockable;
-
-/* cache attribute register control (used by other HAL routines) */
-extern unsigned xthal_get_cacheattr( void );
-extern unsigned xthal_get_icacheattr( void );
-extern unsigned xthal_get_dcacheattr( void );
-extern void     xthal_set_cacheattr( unsigned );
-extern void     xthal_set_icacheattr( unsigned );
-extern void     xthal_set_dcacheattr( unsigned );
-
-/* initialize cache support (must be called once at startup, before all other cache calls) */
-/*extern void xthal_cache_startinit( void );*/
-/* reset caches */
-/*extern void xthal_icache_reset( void );*/
-/*extern void xthal_dcache_reset( void );*/
-/* enable caches */
-extern void xthal_icache_enable( void );        /* DEPRECATED */
-extern void xthal_dcache_enable( void );        /* DEPRECATED */
-/* disable caches */
-extern void xthal_icache_disable( void );       /* DEPRECATED */
-extern void xthal_dcache_disable( void );       /* DEPRECATED */
-
-/* invalidate the caches */
-extern void xthal_icache_all_invalidate( void );
-extern void xthal_dcache_all_invalidate( void );
-extern void xthal_icache_region_invalidate( void *addr, unsigned size );
-extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
-extern void xthal_icache_line_invalidate(void *addr);
-extern void xthal_dcache_line_invalidate(void *addr);
-/* write dirty data back */
-extern void xthal_dcache_all_writeback( void );
-extern void xthal_dcache_region_writeback( void *addr, unsigned size );
-extern void xthal_dcache_line_writeback(void *addr);
-/* write dirty data back and invalidate */
-extern void xthal_dcache_all_writeback_inv( void );
-extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
-extern void xthal_dcache_line_writeback_inv(void *addr);
-/* prefetch and lock specified memory range into cache */
-extern void xthal_icache_region_lock( void *addr, unsigned size );
-extern void xthal_dcache_region_lock( void *addr, unsigned size );
-extern void xthal_icache_line_lock(void *addr);
-extern void xthal_dcache_line_lock(void *addr);
-/* unlock from cache */
-extern void xthal_icache_all_unlock( void );
-extern void xthal_dcache_all_unlock( void );
-extern void xthal_icache_region_unlock( void *addr, unsigned size );
-extern void xthal_dcache_region_unlock( void *addr, unsigned size );
-extern void xthal_icache_line_unlock(void *addr);
-extern void xthal_dcache_line_unlock(void *addr);
-
-
-/* sync icache and memory */
-extern void xthal_icache_sync( void );
-/* sync dcache and memory */
-extern void xthal_dcache_sync( void );
-
-/*----------------------------------------------------------------------
-                                Debug
-  ----------------------------------------------------------------------*/
-
-/*  1 if debug option configured, 0 if not:  */
-extern const int Xthal_debug_configured;
-
-/*  Number of instruction and data break registers:  */
-extern const int Xthal_num_ibreak;
-extern const int Xthal_num_dbreak;
-
-/*  Set (plant) and remove software breakpoint, both synchronizing cache:  */
-extern unsigned int xthal_set_soft_break(void *addr);
-extern void         xthal_remove_soft_break(void *addr, unsigned int);
-
-
-/*----------------------------------------------------------------------
-                                Disassembler
-  ----------------------------------------------------------------------*/
-
-/*  Max expected size of the return buffer for a disassembled instruction (hint only):  */
-#define XTHAL_DISASM_BUFSIZE    80
-
-/*  Disassembly option bits for selecting what to return:  */
-#define XTHAL_DISASM_OPT_ADDR   0x0001  /* display address */
-#define XTHAL_DISASM_OPT_OPHEX  0x0002  /* display opcode bytes in hex */
-#define XTHAL_DISASM_OPT_OPCODE 0x0004  /* display opcode name (mnemonic) */
-#define XTHAL_DISASM_OPT_PARMS  0x0008  /* display parameters */
-#define XTHAL_DISASM_OPT_ALL    0x0FFF  /* display everything */
-
-/* routine to get a string for the disassembled instruction */
-extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
-                       char *buffer, unsigned buflen, unsigned options );
-
-/* routine to get the size of the next instruction. Returns 0 for
-   illegal instruction */
-extern int xthal_disassemble_size( unsigned char *instr_buf );
-
-
-/*----------------------------------------------------------------------
-                                Core Counter
-  ----------------------------------------------------------------------*/
-
-/* counter info */
-extern const unsigned char Xthal_have_ccount;   /* set if CCOUNT register present */
-extern const unsigned char Xthal_num_ccompare;  /* number of CCOMPAREn registers */
-
-/* get CCOUNT register (if not present return 0) */
-extern unsigned xthal_get_ccount(void);
-
-/* set and get CCOMPAREn registers (if not present, get returns 0) */
-extern void     xthal_set_ccompare(int, unsigned);
-extern unsigned xthal_get_ccompare(int);
-
-
-/*----------------------------------------------------------------------
-                        Instruction/Data RAM/ROM Access
-  ----------------------------------------------------------------------*/
-
-extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
-extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
-
-/*----------------------------------------------------------------------
-                           MP Synchronization
-  ----------------------------------------------------------------------*/
-extern int      xthal_compare_and_set( int *addr, int test_val, int compare_val );
-extern unsigned xthal_get_prid( void );
-
-/*extern const char  Xthal_have_s32c1i;*/
-extern const unsigned char Xthal_have_prid;
-
-
-/*----------------------------------------------------------------------
-                             Miscellaneous
-  ----------------------------------------------------------------------*/
-
-extern const unsigned int  Xthal_release_major;
-extern const unsigned int  Xthal_release_minor;
-extern const char * const  Xthal_release_name;
-extern const char * const  Xthal_release_internal;
-
-extern const unsigned char Xthal_memory_order;
-extern const unsigned char Xthal_have_windowed;
-extern const unsigned char Xthal_have_density;
-extern const unsigned char Xthal_have_booleans;
-extern const unsigned char Xthal_have_loops;
-extern const unsigned char Xthal_have_nsa;
-extern const unsigned char Xthal_have_minmax;
-extern const unsigned char Xthal_have_sext;
-extern const unsigned char Xthal_have_clamps;
-extern const unsigned char Xthal_have_mac16;
-extern const unsigned char Xthal_have_mul16;
-extern const unsigned char Xthal_have_fp;
-extern const unsigned char Xthal_have_speculation;
-extern const unsigned char Xthal_have_exceptions;
-extern const unsigned char Xthal_xea_version;
-extern const unsigned char Xthal_have_interrupts;
-extern const unsigned char Xthal_have_highlevel_interrupts;
-extern const unsigned char Xthal_have_nmi;
-
-extern const unsigned short Xthal_num_writebuffer_entries;
-
-extern const unsigned int  Xthal_build_unique_id;
-/*  Release info for hardware targeted by software upgrades:  */
-extern const unsigned int  Xthal_hw_configid0;
-extern const unsigned int  Xthal_hw_configid1;
-extern const unsigned int  Xthal_hw_release_major;
-extern const unsigned int  Xthal_hw_release_minor;
-extern const char * const  Xthal_hw_release_name;
-extern const char * const  Xthal_hw_release_internal;
-
-
-/*  Internal memories...  */
-
-extern const unsigned char Xthal_num_instrom;
-extern const unsigned char Xthal_num_instram;
-extern const unsigned char Xthal_num_datarom;
-extern const unsigned char Xthal_num_dataram;
-extern const unsigned char Xthal_num_xlmi;
-extern const unsigned int  Xthal_instrom_vaddr[1];
-extern const unsigned int  Xthal_instrom_paddr[1];
-extern const unsigned int  Xthal_instrom_size [1];
-extern const unsigned int  Xthal_instram_vaddr[1];
-extern const unsigned int  Xthal_instram_paddr[1];
-extern const unsigned int  Xthal_instram_size [1];
-extern const unsigned int  Xthal_datarom_vaddr[1];
-extern const unsigned int  Xthal_datarom_paddr[1];
-extern const unsigned int  Xthal_datarom_size [1];
-extern const unsigned int  Xthal_dataram_vaddr[1];
-extern const unsigned int  Xthal_dataram_paddr[1];
-extern const unsigned int  Xthal_dataram_size [1];
-extern const unsigned int  Xthal_xlmi_vaddr[1];
-extern const unsigned int  Xthal_xlmi_paddr[1];
-extern const unsigned int  Xthal_xlmi_size [1];
-
-
-
-/*----------------------------------------------------------------------
-                         Memory Management Unit
-  ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_have_spanning_way;
-extern const unsigned char Xthal_have_identity_map;
-extern const unsigned char Xthal_have_mimic_cacheattr;
-extern const unsigned char Xthal_have_xlt_cacheattr;
-extern const unsigned char Xthal_have_cacheattr;
-extern const unsigned char Xthal_have_tlbs;
-
-extern const unsigned char Xthal_mmu_asid_bits;         /* 0 .. 8 */
-extern const unsigned char Xthal_mmu_asid_kernel;
-extern const unsigned char Xthal_mmu_rings;             /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
-extern const unsigned char Xthal_mmu_ring_bits;
-extern const unsigned char Xthal_mmu_sr_bits;
-extern const unsigned char Xthal_mmu_ca_bits;
-extern const unsigned int  Xthal_mmu_max_pte_page_size;
-extern const unsigned int  Xthal_mmu_min_pte_page_size;
-
-extern const unsigned char Xthal_itlb_way_bits;
-extern const unsigned char Xthal_itlb_ways;
-extern const unsigned char Xthal_itlb_arf_ways;
-extern const unsigned char Xthal_dtlb_way_bits;
-extern const unsigned char Xthal_dtlb_ways;
-extern const unsigned char Xthal_dtlb_arf_ways;
-
-/*  Convert between virtual and physical addresses (through static maps only):  */
-/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
-extern int  xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
-extern int  xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
-
-#if 0
-/*******************   EXPERIMENTAL AND TENTATIVE ONLY   ********************/
-
-#define XTHAL_MMU_PAGESZ_COUNT_MAX      8       /* maximum number of different page sizes */
-extern const char       Xthal_mmu_pagesz_count;         /* 0 .. 8               number of different page sizes configured */
-
-/*  Note:  the following table doesn't necessarily have page sizes in increasing order: */
-extern const char       Xthal_mmu_pagesz_log2[XTHAL_MMU_PAGESZ_COUNT_MAX];      /* 10 .. 28 (0 past count) */
-
-/*  Sorted (increasing) table of page sizes, that indexes into the above table: */
-extern const char       Xthal_mmu_pagesz_sorted[XTHAL_MMU_PAGESZ_COUNT_MAX];    /* 0 .. 7 (0 past count) */
-
-/*u32   Xthal_virtual_exceptions;*/     /* bitmask of which exceptions execute in virtual mode... */
-
-extern const char       Xthal_mmu_pte_pagesz_log2_min;  /* ?? minimum page size in PTEs */
-extern const char       Xthal_mmu_pte_pagesz_log2_max;  /* ?? maximum page size in PTEs */
-
-/*  Cache Attribute Bits Implemented by the Cache (part of the cache abstraction) */
-extern const char       Xthal_icache_fca_bits_implemented;      /* ITLB/UTLB only! */
-extern const char       Xthal_dcache_lca_bits_implemented;      /* DTLB/UTLB only! */
-extern const char       Xthal_dcache_sca_bits_implemented;      /* DTLB/UTLB only! */
-
-/*  Per TLB Parameters (Instruction, Data, Unified)  */
-struct XtHalMmuTlb      Xthal_itlb;     /* description of MMU I-TLB generic features */
-struct XtHalMmuTlb      Xthal_dtlb;     /* description of MMU D-TLB generic features */
-struct XtHalMmuTlb      Xthal_utlb;     /* description of MMU U-TLB generic features */
-
-#define XTHAL_MMU_WAYS_MAX      8       /* maximum number of ways (associativities) for each TLB */
-
-/*  Structure for common information described for each possible TLB (instruction, data and unified): */
-typedef struct XtHalMmuTlb {
-    u8          va_bits;                /* 32           (number of virtual address bits) */
-    u8          pa_bits;                /* 32           (number of physical address bits) */
-    bool        tlb_va_indexed;         /* 1    (set if TLB is indexed by virtual address) */
-    bool        tlb_va_tagged;          /* 0    (set if TLB is tagged by virtual address) */
-    bool        cache_va_indexed;       /* 1    (set if cache is indexed by virtual address) */
-    bool        cache_va_tagged;        /* 0    (set if cache is tagged by virtual address) */
-    /*bool      (whether page tables are traversed in vaddr sorted order, paddr sorted order, ...) */
-    /*u8        (set of available page attribute bits, other than cache attribute bits defined above) */
-    /*u32       (various masks for pages, MMU table/TLB entries, etc.) */
-    u8          way_count;              /* 0 .. 8       (number of ways, a.k.a. associativities, for this TLB) */
-    XtHalMmuTlbWay *    ways[XTHAL_MMU_WAYS_MAX];       /* pointers to per-way parms for each way */
-} XtHalMmuTlb;
-
-/*  Per TLB Way (Per Associativity) Parameters  */
-typedef struct XtHalMmuTlbWay {
-     u32        index_count_log2;       /* 0 .. 4 */
-     u32        pagesz_mask;            /* 0 .. 2^pagesz_count - 1      (each bit corresponds to a size */
-                                        /*              defined in the Xthal_mmu_pagesz_log2[] table) */
-     u32        vpn_const_mask;
-     u32        vpn_const_value;
-     u64        ppn_const_mask;         /* future may support pa_bits > 32 */
-     u64        ppn_const_value;
-     u32        ppn_id_mask;            /* paddr bits taken directly from vaddr */
-     bool       backgnd_match;          /* 0 or 1 */
-     /*  These are defined in terms of the XTHAL_CACHE_xxx bits: */
-     u8         fca_const_mask;         /* ITLB/UTLB only! */
-     u8         fca_const_value;        /* ITLB/UTLB only! */
-     u8         lca_const_mask;         /* DTLB/UTLB only! */
-     u8         lca_const_value;        /* DTLB/UTLB only! */
-     u8         sca_const_mask;         /* DTLB/UTLB only! */
-     u8         sca_const_value;        /* DTLB/UTLB only! */
-     /*  These define an encoding that map 5 bits in TLB and PTE entries to */
-     /*  8 bits (FCA, ITLB), 16 bits (LCA+SCA, DTLB) or 24 bits (FCA+LCA+SCA, UTLB): */
-     /*  (they may be moved to struct XtHalMmuTlb) */
-     u8         ca_bits;                /* number of bits in TLB/PTE entries for cache attributes */
-     u32 *      ca_map;                 /* pointer to array of 2^ca_bits entries of FCA+LCA+SCA bits */
-} XtHalMmuTlbWay;
-
-/*
- *  The way to determine whether protection support is present in core
- *  is to [look at Xthal_mmu_rings ???].
- *  Give info on memory requirements for MMU tables and other in-memory
- *  data structures (globally, per task, base and per page, etc.) - whatever bounds can be calculated.
- */
-
-
-/*  Default vectors:  */
-xthal_immu_fetch_miss_vector
-xthal_dmmu_load_miss_vector
-xthal_dmmu_store_miss_vector
-
-/*  Functions called when a fault is detected:  */
-typedef void (XtHalMmuFaultFunc)( unsigned vaddr, ...context... );
-/*  Or, */
-/*      a? = vaddr */
-/*      a? = context... */
-/*      PS.xxx = xxx */
-XtHalMMuFaultFunc *Xthal_immu_fetch_fault_func;
-XtHalMMuFaultFunc *Xthal_dmmu_load_fault_func;
-XtHalMMuFaultFunc *Xthal_dmmu_store_fault_func;
-
-/*  Default Handlers:  */
-/*  The user and/or kernel exception handlers may jump to these handlers to handle the relevant exceptions,
- *  according to the value of EXCCAUSE.  The exact register state on entry to these handlers is TBD.  */
-/*  When multiple TLB entries match (hit) on the same access:  */
-xthal_immu_fetch_multihit_handler
-xthal_dmmu_load_multihit_handler
-xthal_dmmu_store_multihit_handler
-/*  Protection violations according to cache attributes, and other cache attribute mismatches:  */
-xthal_immu_fetch_attr_handler
-xthal_dmmu_load_attr_handler
-xthal_dmmu_store_attr_handler
-/*  Protection violations due to insufficient ring level:  */
-xthal_immu_fetch_priv_handler
-xthal_dmmu_load_priv_handler
-xthal_dmmu_store_priv_handler
-/*  Alignment exception handlers (if supported by the particular Xtensa MMU configuration):  */
-xthal_dmmu_load_align_handler
-xthal_dmmu_store_align_handler
-
-/*  Or, alternatively, the OS user and/or kernel exception handlers may simply jump to the
- *  following entry points which will handle any values of EXCCAUSE not handled by the OS:  */
-xthal_user_exc_default_handler
-xthal_kernel_exc_default_handler
-
-#endif /*0*/
-
-#ifdef INCLUDE_DEPRECATED_HAL_CODE
-extern const unsigned char Xthal_have_old_exc_arch;
-extern const unsigned char Xthal_have_mmu;
-extern const unsigned int  Xthal_num_regs;
-extern const unsigned char Xthal_num_iroms;
-extern const unsigned char Xthal_num_irams;
-extern const unsigned char Xthal_num_droms;
-extern const unsigned char Xthal_num_drams;
-extern const unsigned int  Xthal_configid0;
-extern const unsigned int  Xthal_configid1;
-#endif
-
-#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
-#define XTHAL_24_BIT_BREAK              0x80000000
-#define XTHAL_16_BIT_BREAK              0x40000000
-extern const unsigned short     Xthal_ill_inst_16[16];
-#define XTHAL_DEST_REG          0xf0000000      /* Mask for destination register */
-#define XTHAL_DEST_REG_INST     0x08000000      /* Branch address is in register */
-#define XTHAL_DEST_REL_INST     0x04000000      /* Branch address is relative */
-#define XTHAL_RFW_INST          0x00000800
-#define XTHAL_RFUE_INST         0x00000400
-#define XTHAL_RFI_INST          0x00000200
-#define XTHAL_RFE_INST          0x00000100
-#define XTHAL_RET_INST          0x00000080
-#define XTHAL_BREAK_INST        0x00000040
-#define XTHAL_SYSCALL_INST      0x00000020
-#define XTHAL_LOOP_END          0x00000010      /* Not set by xthal_inst_type */
-#define XTHAL_JUMP_INST         0x00000008      /* Call or jump instruction */
-#define XTHAL_BRANCH_INST       0x00000004      /* Branch instruction */
-#define XTHAL_24_BIT_INST       0x00000002
-#define XTHAL_16_BIT_INST   0x00000001
-typedef struct xthal_state {
-    unsigned    pc;
-    unsigned    ar[16];
-    unsigned    lbeg;
-    unsigned    lend;
-    unsigned    lcount;
-    unsigned    extra_ptr;
-    unsigned    cpregs_ptr[XTHAL_MAX_CPS];
-} XTHAL_STATE;
-extern unsigned int xthal_inst_type(void *addr);
-extern unsigned int xthal_branch_addr(void *addr);
-extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
-#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!__ASSEMBLY__ */
-
-#endif /*XTENSA_HAL_H*/
-
diff --git a/include/asm-xtensa/xtensa/simcall.h b/include/asm-xtensa/xtensa/simcall.h
deleted file mode 100644
index a2b868929a49..000000000000
--- a/include/asm-xtensa/xtensa/simcall.h
+++ /dev/null
@@ -1,130 +0,0 @@
-#ifndef SIMCALL_INCLUDED
-#define SIMCALL_INCLUDED
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- * include/asm-xtensa/xtensa/simcall.h  -  Simulator call numbers
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License.  See the file "COPYING" in the main directory of
- * this archive for more details.
- *
- * Copyright (C) 2002 Tensilica Inc.
- */
-
-
-/*
- *  System call like services offered by the simulator host.
- *  These are modeled after the Linux 2.4 kernel system calls
- *  for Xtensa processors.  However not all system calls and
- *  not all functionality of a given system call are implemented,
- *  or necessarily have well defined or equivalent semantics in
- *  the context of a simulation (as opposed to a Unix kernel).
- *
- *  These services behave largely as if they had been invoked
- *  as a task in the simulator host's operating system
- *  (eg. files accessed are those of the simulator host).
- *  However, these SIMCALLs model a virtual operating system
- *  so that various definitions, bit assignments etc
- *  (eg. open mode bits, errno values, etc) are independent
- *  of the host operating system used to run the simulation.
- *  Rather these definitions are specific to the Xtensa ISS.
- *  This way Xtensa ISA code written to use these SIMCALLs
- *  can (in principle) be simulated on any host.
- *
- *  Up to 6 parameters are passed in registers a3 to a8
- *  (note the 6th parameter isn't passed on the stack,
- *   unlike windowed function calling conventions).
- *  The return value is in a2.  A negative value in the
- *  range -4096 to -1 indicates a negated error code to be
- *  reported in errno with a return value of -1, otherwise
- *  the value in a2 is returned as is.
- */
-
-/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */
-
-#define SYS_nop         0       /* n/a - setup; used to flush register windows */
-#define SYS_exit        1       /*x*/
-#define SYS_fork        2
-#define SYS_read        3       /*x*/
-#define SYS_write       4       /*x*/
-#define SYS_open        5       /*x*/
-#define SYS_close       6       /*x*/
-#define SYS_rename      7       /*x 38 - waitpid */
-#define SYS_creat       8       /*x*/
-#define SYS_link        9       /*x (not implemented on WIN32) */
-#define SYS_unlink      10      /*x*/
-#define SYS_execv       11      /* n/a - execve */
-#define SYS_execve      12      /* 11 - chdir */
-#define SYS_pipe        13      /* 42 - time */
-#define SYS_stat        14      /* 106 - mknod */
-#define SYS_chmod       15
-#define SYS_chown       16      /* 202 - lchown */
-#define SYS_utime       17      /* 30 - break */
-#define SYS_wait        18      /* n/a - oldstat */
-#define SYS_lseek       19      /*x*/
-#define SYS_getpid      20
-#define SYS_isatty      21      /* n/a - mount */
-#define SYS_fstat       22      /* 108 - oldumount */
-#define SYS_time        23      /* 13 - setuid */
-#define SYS_gettimeofday 24     /*x 78 - getuid (not implemented on WIN32) */
-#define SYS_times       25      /*X 43 - stime (Xtensa-specific implementation) */
-#define SYS_socket      26
-#define SYS_sendto      27
-#define SYS_recvfrom    28
-#define SYS_select_one  29      /* not compitible select, one file descriptor at the time */
-#define SYS_bind        30
-#define SYS_ioctl       31
-
-/*
- *  Other...
- */
-#define SYS_iss_argc      1000  /* returns value of argc */
-#define SYS_iss_argv_size 1001  /* bytes needed for argv & arg strings */
-#define SYS_iss_set_argv  1002  /* saves argv & arg strings at given addr */
-
-/*
- * SIMCALLs for the ferret memory debugger. All are invoked by
- * libferret.a ...  ( Xtensa/Target-Libs/ferret )
- */
-#define SYS_ferret           1010
-#define SYS_malloc           1011
-#define SYS_free             1012
-#define SYS_more_heap        1013
-#define SYS_no_heap          1014
-
-
-/*
- *  Extra SIMCALLs for GDB:
- */
-#define SYS_gdb_break         -1        /* invoked by XTOS on user exceptions if EPC points
-                                           to a break.n/break, regardless of cause! */
-#define SYS_xmon_out          -2        /* invoked by XMON: ... */
-#define SYS_xmon_in           -3        /* invoked by XMON: ... */
-#define SYS_xmon_flush        -4        /* invoked by XMON: ... */
-#define SYS_gdb_abort         -5        /* invoked by XTOS in _xtos_panic() */
-#define SYS_gdb_illegal_inst  -6        /* invoked by XTOS for illegal instructions (too deeply) */
-#define SYS_xmon_init         -7        /* invoked by XMON: ... */
-#define SYS_gdb_enter_sktloop -8        /* invoked by XTOS on debug exceptions */
-
-/*
- *  SIMCALLs for vxWorks xtiss BSP:
- */
-#define SYS_setup_ppp_pipes   -83
-#define SYS_log_msg           -84
-
-/*
- *  Test SIMCALLs:
- */
-#define SYS_test_write_state  -100
-#define SYS_test_read_state   -101
-
-/*
- * SYS_select_one specifiers
- */
-#define  XTISS_SELECT_ONE_READ    1
-#define  XTISS_SELECT_ONE_WRITE   2
-#define  XTISS_SELECT_ONE_EXCEPT  3
-
-#endif /* !SIMCALL_INCLUDED */
diff --git a/include/asm-xtensa/xtensa/xt2000-uart.h b/include/asm-xtensa/xtensa/xt2000-uart.h
deleted file mode 100644
index 0154460f0ed8..000000000000
--- a/include/asm-xtensa/xtensa/xt2000-uart.h
+++ /dev/null
@@ -1,155 +0,0 @@
-#ifndef _uart_h_included_
-#define _uart_h_included_
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- * include/asm-xtensa/xtensa/xt2000-uart.h -- NatSemi PC16552D DUART
- * definitions
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002 Tensilica Inc.
- */
-
-
-#include <xtensa/xt2000.h>
-
-
-/* 16550 UART DEVICE REGISTERS
-   The XT2000 board aligns each register to a 32-bit word but the UART device only uses
-   one byte of the word, which is the least-significant byte regardless of the
-   endianness of the core (ie. byte offset 0 for little-endian and 3 for big-endian).
-   So if using word accesses then endianness doesn't matter.
-   The macros provided here do that.
-*/
-struct uart_dev_s {
-  union {
-    unsigned int rxb;   /* DLAB=0: receive buffer, read-only */
-    unsigned int txb;   /* DLAB=0: transmit buffer, write-only */
-    unsigned int dll;   /* DLAB=1: divisor, least-significant byte latch (was write-only?) */
-  } w0;
-  union {
-    unsigned int ier;   /* DLAB=0: interrupt-enable register (was write-only?) */
-    unsigned int dlm;   /* DLAB=1: divisor, most-significant byte latch (was write-only?) */
-  } w1;
-
-  union {
-    unsigned int isr;   /* DLAB=0: interrupt status register, read-only */
-    unsigned int fcr;   /* DLAB=0: FIFO control register, write-only */
-    unsigned int afr;   /* DLAB=1: alternate function register */
-  } w2;
-
-  unsigned int lcr;     /* line control-register, write-only */
-  unsigned int mcr;     /* modem control-regsiter, write-only */
-  unsigned int lsr;     /* line status register, read-only */
-  unsigned int msr;     /* modem status register, read-only */
-  unsigned int scr;     /* scratch regsiter, read/write */
-};
-
-#define _RXB(u) ((u)->w0.rxb)
-#define _TXB(u) ((u)->w0.txb)
-#define _DLL(u) ((u)->w0.dll)
-#define _IER(u) ((u)->w1.ier)
-#define _DLM(u) ((u)->w1.dlm)
-#define _ISR(u) ((u)->w2.isr)
-#define _FCR(u) ((u)->w2.fcr)
-#define _AFR(u) ((u)->w2.afr)
-#define _LCR(u) ((u)->lcr)
-#define _MCR(u) ((u)->mcr)
-#define _LSR(u) ((u)->lsr)
-#define _MSR(u) ((u)->msr)
-#define _SCR(u) ((u)->scr)
-
-typedef volatile struct uart_dev_s uart_dev_t;
-
-/* IER bits */
-#define RCVR_DATA_REG_INTENABLE 0x01
-#define XMIT_HOLD_REG_INTENABLE    0x02
-#define RCVR_STATUS_INTENABLE   0x04
-#define MODEM_STATUS_INTENABLE     0x08
-
-/* FCR bits */
-#define _FIFO_ENABLE      0x01
-#define RCVR_FIFO_RESET  0x02
-#define XMIT_FIFO_RESET  0x04
-#define DMA_MODE_SELECT  0x08
-#define RCVR_TRIGGER_LSB 0x40
-#define RCVR_TRIGGER_MSB 0x80
-
-/* AFR bits */
-#define AFR_CONC_WRITE  0x01
-#define AFR_BAUDOUT_SEL 0x02
-#define AFR_RXRDY_SEL   0x04
-
-/* ISR bits */
-#define INT_STATUS(r)   ((r)&1)
-#define INT_PRIORITY(r) (((r)>>1)&0x7)
-
-/* LCR bits */
-#define WORD_LENGTH(n)  (((n)-5)&0x3)
-#define STOP_BIT_ENABLE 0x04
-#define PARITY_ENABLE   0x08
-#define EVEN_PARITY     0x10
-#define FORCE_PARITY    0x20
-#define XMIT_BREAK      0x40
-#define DLAB_ENABLE     0x80
-
-/* MCR bits */
-#define _DTR 0x01
-#define _RTS 0x02
-#define _OP1 0x04
-#define _OP2 0x08
-#define LOOP_BACK 0x10
-
-/* LSR Bits */
-#define RCVR_DATA_READY 0x01
-#define OVERRUN_ERROR   0x02
-#define PARITY_ERROR    0x04
-#define FRAMING_ERROR   0x08
-#define BREAK_INTERRUPT 0x10
-#define XMIT_HOLD_EMPTY 0x20
-#define XMIT_EMPTY      0x40
-#define FIFO_ERROR      0x80
-#define RCVR_READY(u)   (_LSR(u)&RCVR_DATA_READY)
-#define XMIT_READY(u)   (_LSR(u)&XMIT_HOLD_EMPTY)
-
-/* MSR bits */
-#define _RDR       0x01
-#define DELTA_DSR 0x02
-#define DELTA_RI  0x04
-#define DELTA_CD  0x08
-#define _CTS       0x10
-#define _DSR       0x20
-#define _RI        0x40
-#define _CD        0x80
-
-/* prototypes */
-void uart_init( uart_dev_t *u, int bitrate );
-void uart_out( uart_dev_t *u, char c );
-void uart_puts( uart_dev_t *u, char *s );
-char uart_in( uart_dev_t *u );
-void uart_enable_rcvr_int( uart_dev_t *u );
-void uart_disable_rcvr_int( uart_dev_t *u );
-
-#ifdef DUART16552_1_VADDR
-/*  DUART present.  */
-#define DUART_1_BASE    (*(uart_dev_t*)DUART16552_1_VADDR)
-#define DUART_2_BASE    (*(uart_dev_t*)DUART16552_2_VADDR)
-#define UART1_PUTS(s)   uart_puts( &DUART_1_BASE, s )
-#define UART2_PUTS(s)   uart_puts( &DUART_2_BASE, s )
-#else
-/*  DUART not configured, use dummy placeholders to allow compiles to work.  */
-#define DUART_1_BASE    (*(uart_dev_t*)0)
-#define DUART_2_BASE    (*(uart_dev_t*)0)
-#define UART1_PUTS(s)
-#define UART2_PUTS(s)
-#endif
-
-/*  Compute 16-bit divisor for baudrate generator, with rounding:  */
-#define DUART_DIVISOR(crystal,speed)    (((crystal)/16 + (speed)/2)/(speed))
-
-#endif /*_uart_h_included_*/
-
diff --git a/include/asm-xtensa/xtensa/xt2000.h b/include/asm-xtensa/xtensa/xt2000.h
deleted file mode 100644
index 703a45002f8f..000000000000
--- a/include/asm-xtensa/xtensa/xt2000.h
+++ /dev/null
@@ -1,408 +0,0 @@
-#ifndef _INC_XT2000_H_
-#define _INC_XT2000_H_
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- * include/asm-xtensa/xtensa/xt2000.h - Definitions specific to the
- * Tensilica XT2000 Emulation Board
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002 Tensilica Inc.
- */
-
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/system.h>
-
-
-/*
- *  Default assignment of XT2000 devices to external interrupts.
- */
-
-/*  Ethernet interrupt:  */
-#ifdef XCHAL_EXTINT3_NUM
-#define SONIC83934_INTNUM       XCHAL_EXTINT3_NUM
-#define SONIC83934_INTLEVEL     XCHAL_EXTINT3_LEVEL
-#define SONIC83934_INTMASK      XCHAL_EXTINT3_MASK
-#else
-#define SONIC83934_INTMASK      0
-#endif
-
-/*  DUART channel 1 interrupt (P1 - console):  */
-#ifdef XCHAL_EXTINT4_NUM
-#define DUART16552_1_INTNUM     XCHAL_EXTINT4_NUM
-#define DUART16552_1_INTLEVEL   XCHAL_EXTINT4_LEVEL
-#define DUART16552_1_INTMASK    XCHAL_EXTINT4_MASK
-#else
-#define DUART16552_1_INTMASK    0
-#endif
-
-/*  DUART channel 2 interrupt (P2 - 2nd serial port):  */
-#ifdef XCHAL_EXTINT5_NUM
-#define DUART16552_2_INTNUM     XCHAL_EXTINT5_NUM
-#define DUART16552_2_INTLEVEL   XCHAL_EXTINT5_LEVEL
-#define DUART16552_2_INTMASK    XCHAL_EXTINT5_MASK
-#else
-#define DUART16552_2_INTMASK    0
-#endif
-
-/*  FPGA-combined PCI/etc interrupts:  */
-#ifdef XCHAL_EXTINT6_NUM
-#define XT2000_FPGAPCI_INTNUM   XCHAL_EXTINT6_NUM
-#define XT2000_FPGAPCI_INTLEVEL XCHAL_EXTINT6_LEVEL
-#define XT2000_FPGAPCI_INTMASK  XCHAL_EXTINT6_MASK
-#else
-#define XT2000_FPGAPCI_INTMASK  0
-#endif
-
-
-
-/*
- *  Device addresses.
- *
- *  Note:  for endianness-independence, use 32-bit loads and stores for all
- *  register accesses to Ethernet, DUART and LED devices.  Undefined bits
- *  may need to be masked out if needed when reading if the actual register
- *  size is smaller than 32 bits.
- *
- *  Note:  XT2000 bus byte lanes are defined in terms of msbyte and lsbyte
- *  relative to the processor.  So 32-bit registers are accessed consistently
- *  from both big and little endian processors.  However, this means byte
- *  sequences are not consistent between big and little endian processors.
- *  This is fine for RAM, and for ROM if ROM is created for a specific
- *  processor (and thus has correct byte sequences).  However this may be
- *  unexpected for Flash, which might contain a file-system that one wants
- *  to use for multiple processor configurations (eg. the Flash might contain
- *  the Ethernet card's address, endianness-independent application data, etc).
- *  That is, byte sequences written in Flash by a core of a given endianness
- *  will be byte-swapped when seen by a core of the other endianness.
- *  Someone implementing an endianness-independent Flash file system will
- *  likely handle this byte-swapping issue in the Flash driver software.
- */
-
-#define DUART16552_XTAL_FREQ    18432000        /* crystal frequency in Hz */
-#define XTBOARD_FLASH_MAXSIZE   0x4000000       /* 64 MB (max; depends on what is socketed!) */
-#define XTBOARD_EPROM_MAXSIZE   0x0400000       /* 4 MB (max; depends on what is socketed!) */
-#define XTBOARD_EEPROM_MAXSIZE  0x0080000       /* 512 kB (max; depends on what is socketed!) */
-#define XTBOARD_ASRAM_SIZE      0x0100000       /* 1 MB */
-#define XTBOARD_PCI_MEM_SIZE    0x8000000       /* 128 MB (allocated) */
-#define XTBOARD_PCI_IO_SIZE     0x1000000       /* 16 MB (allocated) */
-
-#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
-/*  PCI memory space:  */
-# define XTBOARD_PCI_MEM_PADDR  (XSHAL_IOBLOCK_BYPASS_PADDR+0x0000000)
-/*  Socketed Flash (eg. 2 x 16-bit devices):  */
-# define XTBOARD_FLASH_PADDR    (XSHAL_IOBLOCK_BYPASS_PADDR+0x8000000)
-/*  PCI I/O space:  */
-# define XTBOARD_PCI_IO_PADDR   (XSHAL_IOBLOCK_BYPASS_PADDR+0xC000000)
-/*  V3 PCI interface chip register/config space:  */
-# define XTBOARD_V3PCI_PADDR    (XSHAL_IOBLOCK_BYPASS_PADDR+0xD000000)
-/*  Bus Interface registers:  */
-# define XTBOARD_BUSINT_PADDR   (XSHAL_IOBLOCK_BYPASS_PADDR+0xD010000)
-/*  FPGA registers:  */
-# define XT2000_FPGAREGS_PADDR  (XSHAL_IOBLOCK_BYPASS_PADDR+0xD020000)
-/*  SONIC SN83934 Ethernet controller/transceiver:  */
-# define SONIC83934_PADDR       (XSHAL_IOBLOCK_BYPASS_PADDR+0xD030000)
-/*  8-character bitmapped LED display:  */
-# define XTBOARD_LED_PADDR      (XSHAL_IOBLOCK_BYPASS_PADDR+0xD040000)
-/*  National-Semi PC16552D DUART:  */
-# define DUART16552_1_PADDR     (XSHAL_IOBLOCK_BYPASS_PADDR+0xD050020)  /* channel 1 (P1 - console) */
-# define DUART16552_2_PADDR     (XSHAL_IOBLOCK_BYPASS_PADDR+0xD050000)  /* channel 2 (P2) */
-/*  Asynchronous Static RAM:  */
-# define XTBOARD_ASRAM_PADDR    (XSHAL_IOBLOCK_BYPASS_PADDR+0xD400000)
-/*  8-bit EEPROM:  */
-# define XTBOARD_EEPROM_PADDR   (XSHAL_IOBLOCK_BYPASS_PADDR+0xD600000)
-/*  2 x 16-bit EPROMs:  */
-# define XTBOARD_EPROM_PADDR    (XSHAL_IOBLOCK_BYPASS_PADDR+0xD800000)
-#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
-
-/*  These devices might be accessed cached:  */
-#ifdef XSHAL_IOBLOCK_CACHED_PADDR
-# define XTBOARD_PCI_MEM_CACHED_PADDR   (XSHAL_IOBLOCK_CACHED_PADDR+0x0000000)
-# define XTBOARD_FLASH_CACHED_PADDR     (XSHAL_IOBLOCK_CACHED_PADDR+0x8000000)
-# define XTBOARD_ASRAM_CACHED_PADDR     (XSHAL_IOBLOCK_CACHED_PADDR+0xD400000)
-# define XTBOARD_EEPROM_CACHED_PADDR    (XSHAL_IOBLOCK_CACHED_PADDR+0xD600000)
-# define XTBOARD_EPROM_CACHED_PADDR     (XSHAL_IOBLOCK_CACHED_PADDR+0xD800000)
-#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
-
-
-/***  Same thing over again, this time with virtual addresses:  ***/
-
-#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
-/*  PCI memory space:  */
-# define XTBOARD_PCI_MEM_VADDR  (XSHAL_IOBLOCK_BYPASS_VADDR+0x0000000)
-/*  Socketed Flash (eg. 2 x 16-bit devices):  */
-# define XTBOARD_FLASH_VADDR    (XSHAL_IOBLOCK_BYPASS_VADDR+0x8000000)
-/*  PCI I/O space:  */
-# define XTBOARD_PCI_IO_VADDR   (XSHAL_IOBLOCK_BYPASS_VADDR+0xC000000)
-/*  V3 PCI interface chip register/config space:  */
-# define XTBOARD_V3PCI_VADDR    (XSHAL_IOBLOCK_BYPASS_VADDR+0xD000000)
-/*  Bus Interface registers:  */
-# define XTBOARD_BUSINT_VADDR   (XSHAL_IOBLOCK_BYPASS_VADDR+0xD010000)
-/*  FPGA registers:  */
-# define XT2000_FPGAREGS_VADDR  (XSHAL_IOBLOCK_BYPASS_VADDR+0xD020000)
-/*  SONIC SN83934 Ethernet controller/transceiver:  */
-# define SONIC83934_VADDR       (XSHAL_IOBLOCK_BYPASS_VADDR+0xD030000)
-/*  8-character bitmapped LED display:  */
-# define XTBOARD_LED_VADDR      (XSHAL_IOBLOCK_BYPASS_VADDR+0xD040000)
-/*  National-Semi PC16552D DUART:  */
-# define DUART16552_1_VADDR     (XSHAL_IOBLOCK_BYPASS_VADDR+0xD050020)  /* channel 1 (P1 - console) */
-# define DUART16552_2_VADDR     (XSHAL_IOBLOCK_BYPASS_VADDR+0xD050000)  /* channel 2 (P2) */
-/*  Asynchronous Static RAM:  */
-# define XTBOARD_ASRAM_VADDR    (XSHAL_IOBLOCK_BYPASS_VADDR+0xD400000)
-/*  8-bit EEPROM:  */
-# define XTBOARD_EEPROM_VADDR   (XSHAL_IOBLOCK_BYPASS_VADDR+0xD600000)
-/*  2 x 16-bit EPROMs:  */
-# define XTBOARD_EPROM_VADDR    (XSHAL_IOBLOCK_BYPASS_VADDR+0xD800000)
-#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
-
-/*  These devices might be accessed cached:  */
-#ifdef XSHAL_IOBLOCK_CACHED_VADDR
-# define XTBOARD_PCI_MEM_CACHED_VADDR   (XSHAL_IOBLOCK_CACHED_VADDR+0x0000000)
-# define XTBOARD_FLASH_CACHED_VADDR     (XSHAL_IOBLOCK_CACHED_VADDR+0x8000000)
-# define XTBOARD_ASRAM_CACHED_VADDR     (XSHAL_IOBLOCK_CACHED_VADDR+0xD400000)
-# define XTBOARD_EEPROM_CACHED_VADDR    (XSHAL_IOBLOCK_CACHED_VADDR+0xD600000)
-# define XTBOARD_EPROM_CACHED_VADDR     (XSHAL_IOBLOCK_CACHED_VADDR+0xD800000)
-#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
-
-
-/*  System ROM:  */
-#define XTBOARD_ROM_SIZE                XSHAL_ROM_SIZE
-#ifdef XSHAL_ROM_VADDR
-#define XTBOARD_ROM_VADDR               XSHAL_ROM_VADDR
-#endif
-#ifdef XSHAL_ROM_PADDR
-#define XTBOARD_ROM_PADDR               XSHAL_ROM_PADDR
-#endif
-
-/*  System RAM:  */
-#define XTBOARD_RAM_SIZE                XSHAL_RAM_SIZE
-#ifdef XSHAL_RAM_VADDR
-#define XTBOARD_RAM_VADDR               XSHAL_RAM_VADDR
-#endif
-#ifdef XSHAL_RAM_PADDR
-#define XTBOARD_RAM_PADDR               XSHAL_RAM_PADDR
-#endif
-#define XTBOARD_RAM_BYPASS_VADDR        XSHAL_RAM_BYPASS_VADDR
-#define XTBOARD_RAM_BYPASS_PADDR        XSHAL_RAM_BYPASS_PADDR
-
-
-
-/*
- *  Things that depend on device addresses.
- */
-
-
-#define XTBOARD_CACHEATTR_WRITEBACK     XSHAL_XT2000_CACHEATTR_WRITEBACK
-#define XTBOARD_CACHEATTR_WRITEALLOC    XSHAL_XT2000_CACHEATTR_WRITEALLOC
-#define XTBOARD_CACHEATTR_WRITETHRU     XSHAL_XT2000_CACHEATTR_WRITETHRU
-#define XTBOARD_CACHEATTR_BYPASS        XSHAL_XT2000_CACHEATTR_BYPASS
-#define XTBOARD_CACHEATTR_DEFAULT       XSHAL_XT2000_CACHEATTR_DEFAULT
-
-#define XTBOARD_BUSINT_PIPE_REGIONS     XSHAL_XT2000_PIPE_REGIONS
-#define XTBOARD_BUSINT_SDRAM_REGIONS    XSHAL_XT2000_SDRAM_REGIONS
-
-
-
-/*
- *  BusLogic (FPGA) registers.
- *  All these registers are normally accessed using 32-bit loads/stores.
- */
-
-/*  Register offsets:  */
-#define XT2000_DATECD_OFS       0x00    /* date code (read-only) */
-#define XT2000_STSREG_OFS       0x04    /* status (read-only) */
-#define XT2000_SYSLED_OFS       0x08    /* system LED */
-#define XT2000_WRPROT_OFS       0x0C    /* write protect */
-#define XT2000_SWRST_OFS        0x10    /* software reset */
-#define XT2000_SYSRST_OFS       0x14    /* system (peripherals) reset */
-#define XT2000_IMASK_OFS        0x18    /* interrupt mask */
-#define XT2000_ISTAT_OFS        0x1C    /* interrupt status */
-#define XT2000_V3CFG_OFS        0x20    /* V3 config (V320 PCI) */
-
-/*  Physical register addresses:  */
-#ifdef XT2000_FPGAREGS_PADDR
-#define XT2000_DATECD_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_DATECD_OFS)
-#define XT2000_STSREG_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_STSREG_OFS)
-#define XT2000_SYSLED_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_SYSLED_OFS)
-#define XT2000_WRPROT_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_WRPROT_OFS)
-#define XT2000_SWRST_PADDR      (XT2000_FPGAREGS_PADDR+XT2000_SWRST_OFS)
-#define XT2000_SYSRST_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_SYSRST_OFS)
-#define XT2000_IMASK_PADDR      (XT2000_FPGAREGS_PADDR+XT2000_IMASK_OFS)
-#define XT2000_ISTAT_PADDR      (XT2000_FPGAREGS_PADDR+XT2000_ISTAT_OFS)
-#define XT2000_V3CFG_PADDR      (XT2000_FPGAREGS_PADDR+XT2000_V3CFG_OFS)
-#endif
-
-/*  Virtual register addresses:  */
-#ifdef XT2000_FPGAREGS_VADDR
-#define XT2000_DATECD_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_DATECD_OFS)
-#define XT2000_STSREG_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_STSREG_OFS)
-#define XT2000_SYSLED_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_SYSLED_OFS)
-#define XT2000_WRPROT_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_WRPROT_OFS)
-#define XT2000_SWRST_VADDR      (XT2000_FPGAREGS_VADDR+XT2000_SWRST_OFS)
-#define XT2000_SYSRST_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_SYSRST_OFS)
-#define XT2000_IMASK_VADDR      (XT2000_FPGAREGS_VADDR+XT2000_IMASK_OFS)
-#define XT2000_ISTAT_VADDR      (XT2000_FPGAREGS_VADDR+XT2000_ISTAT_OFS)
-#define XT2000_V3CFG_VADDR      (XT2000_FPGAREGS_VADDR+XT2000_V3CFG_OFS)
-/*  Register access (for C code):  */
-#define XT2000_DATECD_REG       (*(volatile unsigned*) XT2000_DATECD_VADDR)
-#define XT2000_STSREG_REG       (*(volatile unsigned*) XT2000_STSREG_VADDR)
-#define XT2000_SYSLED_REG       (*(volatile unsigned*) XT2000_SYSLED_VADDR)
-#define XT2000_WRPROT_REG       (*(volatile unsigned*) XT2000_WRPROT_VADDR)
-#define XT2000_SWRST_REG        (*(volatile unsigned*) XT2000_SWRST_VADDR)
-#define XT2000_SYSRST_REG       (*(volatile unsigned*) XT2000_SYSRST_VADDR)
-#define XT2000_IMASK_REG        (*(volatile unsigned*) XT2000_IMASK_VADDR)
-#define XT2000_ISTAT_REG        (*(volatile unsigned*) XT2000_ISTAT_VADDR)
-#define XT2000_V3CFG_REG        (*(volatile unsigned*) XT2000_V3CFG_VADDR)
-#endif
-
-/*  DATECD (date code) bit fields:  */
-
-/*  BCD-coded month (01..12):  */
-#define XT2000_DATECD_MONTH_SHIFT       24
-#define XT2000_DATECD_MONTH_BITS        8
-#define XT2000_DATECD_MONTH_MASK        0xFF000000
-/*  BCD-coded day (01..31):  */
-#define XT2000_DATECD_DAY_SHIFT         16
-#define XT2000_DATECD_DAY_BITS          8
-#define XT2000_DATECD_DAY_MASK          0x00FF0000
-/*  BCD-coded year (2001..9999):  */
-#define XT2000_DATECD_YEAR_SHIFT        0
-#define XT2000_DATECD_YEAR_BITS         16
-#define XT2000_DATECD_YEAR_MASK         0x0000FFFF
-
-/*  STSREG (status) bit fields:  */
-
-/*  Switch SW3 setting bit fields (0=off/up, 1=on/down):  */
-#define XT2000_STSREG_SW3_SHIFT         0
-#define XT2000_STSREG_SW3_BITS          4
-#define XT2000_STSREG_SW3_MASK          0x0000000F
-/*  Boot-select bits of switch SW3:  */
-#define XT2000_STSREG_BOOTSEL_SHIFT     0
-#define XT2000_STSREG_BOOTSEL_BITS      2
-#define XT2000_STSREG_BOOTSEL_MASK      0x00000003
-/*  Boot-select values:  */
-#define XT2000_STSREG_BOOTSEL_FLASH     0
-#define XT2000_STSREG_BOOTSEL_EPROM16   1
-#define XT2000_STSREG_BOOTSEL_PROM8     2
-#define XT2000_STSREG_BOOTSEL_ASRAM     3
-/*  User-defined bits of switch SW3:  */
-#define XT2000_STSREG_SW3_2_SHIFT       2
-#define XT2000_STSREG_SW3_2_MASK        0x00000004
-#define XT2000_STSREG_SW3_3_SHIFT       3
-#define XT2000_STSREG_SW3_3_MASK        0x00000008
-
-/*  SYSLED (system LED) bit fields:  */
-
-/*  LED control bit (0=off, 1=on):  */
-#define XT2000_SYSLED_LEDON_SHIFT       0
-#define XT2000_SYSLED_LEDON_MASK        0x00000001
-
-/*  WRPROT (write protect) bit fields (0=writable, 1=write-protected [default]):  */
-
-/*  Flash write protect:  */
-#define XT2000_WRPROT_FLWP_SHIFT        0
-#define XT2000_WRPROT_FLWP_MASK         0x00000001
-/*  Reserved but present write protect bits:  */
-#define XT2000_WRPROT_WRP_SHIFT         1
-#define XT2000_WRPROT_WRP_BITS          7
-#define XT2000_WRPROT_WRP_MASK          0x000000FE
-
-/*  SWRST (software reset; allows s/w to generate power-on equivalent reset):  */
-
-/*  Software reset bits:  */
-#define XT2000_SWRST_SWR_SHIFT          0
-#define XT2000_SWRST_SWR_BITS           16
-#define XT2000_SWRST_SWR_MASK           0x0000FFFF
-/*  Software reset value -- writing this value resets the board:  */
-#define XT2000_SWRST_RESETVALUE         0x0000DEAD
-
-/*  SYSRST (system reset; controls reset of individual peripherals):  */
-
-/*  All-device reset:  */
-#define XT2000_SYSRST_ALL_SHIFT         0
-#define XT2000_SYSRST_ALL_BITS          4
-#define XT2000_SYSRST_ALL_MASK          0x0000000F
-/*  HDSP-2534 LED display reset (1=reset, 0=nothing):  */
-#define XT2000_SYSRST_LED_SHIFT         0
-#define XT2000_SYSRST_LED_MASK          0x00000001
-/*  Sonic DP83934 Ethernet controller reset (1=reset, 0=nothing):  */
-#define XT2000_SYSRST_SONIC_SHIFT       1
-#define XT2000_SYSRST_SONIC_MASK        0x00000002
-/*  DP16552 DUART reset (1=reset, 0=nothing):  */
-#define XT2000_SYSRST_DUART_SHIFT       2
-#define XT2000_SYSRST_DUART_MASK        0x00000004
-/*  V3 V320 PCI bridge controller reset (1=reset, 0=nothing):  */
-#define XT2000_SYSRST_V3_SHIFT          3
-#define XT2000_SYSRST_V3_MASK           0x00000008
-
-/*  IMASK (interrupt mask; 0=disable, 1=enable):  */
-/*  ISTAT (interrupt status; 0=inactive, 1=pending):  */
-
-/*  PCI INTP interrupt:  */
-#define XT2000_INTMUX_PCI_INTP_SHIFT    2
-#define XT2000_INTMUX_PCI_INTP_MASK     0x00000004
-/*  PCI INTS interrupt:  */
-#define XT2000_INTMUX_PCI_INTS_SHIFT    3
-#define XT2000_INTMUX_PCI_INTS_MASK     0x00000008
-/*  PCI INTD interrupt:  */
-#define XT2000_INTMUX_PCI_INTD_SHIFT    4
-#define XT2000_INTMUX_PCI_INTD_MASK     0x00000010
-/*  V320 PCI controller interrupt:  */
-#define XT2000_INTMUX_V3_SHIFT          5
-#define XT2000_INTMUX_V3_MASK           0x00000020
-/*  PCI ENUM interrupt:  */
-#define XT2000_INTMUX_PCI_ENUM_SHIFT    6
-#define XT2000_INTMUX_PCI_ENUM_MASK     0x00000040
-/*  PCI DEG interrupt:  */
-#define XT2000_INTMUX_PCI_DEG_SHIFT     7
-#define XT2000_INTMUX_PCI_DEG_MASK      0x00000080
-
-/*  V3CFG (V3 config, V320 PCI controller):  */
-
-/*  V3 address control (0=pass-thru, 1=V3 address bits 31:28 set to 4'b0001 [default]):  */
-#define XT2000_V3CFG_V3ADC_SHIFT        0
-#define XT2000_V3CFG_V3ADC_MASK         0x00000001
-
-/* I2C Devices */
-
-#define XT2000_I2C_RTC_ID               0x68
-#define XT2000_I2C_NVRAM0_ID            0x56    /* 1st 256 byte block */
-#define XT2000_I2C_NVRAM1_ID            0x57    /* 2nd 256 byte block */
-
-/*  NVRAM Board Info structure:  */
-
-#define XT2000_NVRAM_SIZE               512
-
-#define XT2000_NVRAM_BINFO_START        0x100
-#define XT2000_NVRAM_BINFO_SIZE         0x20
-#define XT2000_NVRAM_BINFO_VERSION      0x10    /* version 1.0 */
-#if 0
-#define XT2000_NVRAM_BINFO_VERSION_OFFSET       0x00
-#define XT2000_NVRAM_BINFO_VERSION_SIZE                 0x1
-#define XT2000_NVRAM_BINFO_ETH_ADDR_OFFSET      0x02
-#define XT2000_NVRAM_BINFO_ETH_ADDR_SIZE                0x6
-#define XT2000_NVRAM_BINFO_SN_OFFSET            0x10
-#define XT2000_NVRAM_BINFO_SN_SIZE                      0xE
-#define XT2000_NVRAM_BINFO_CRC_OFFSET           0x1E
-#define XT2000_NVRAM_BINFO_CRC_SIZE                     0x2
-#endif /*0*/
-
-#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)
-typedef struct xt2000_nvram_binfo {
-    unsigned char       version;
-    unsigned char       reserved1;
-    unsigned char       eth_addr[6];
-    unsigned char       reserved8[8];
-    unsigned char       serialno[14];
-    unsigned char       crc[2];         /* 16-bit CRC */
-} xt2000_nvram_binfo;
-#endif /*!__ASSEMBLY__ && !_NOCLANGUAGE*/
-
-
-#endif /*_INC_XT2000_H_*/
-
diff --git a/include/asm-xtensa/xtensa/xtboard.h b/include/asm-xtensa/xtensa/xtboard.h
deleted file mode 100644
index 22469c175307..000000000000
--- a/include/asm-xtensa/xtensa/xtboard.h
+++ /dev/null
@@ -1,120 +0,0 @@
-#ifndef _xtboard_h_included_
-#define _xtboard_h_included_
-
-/*
- * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
- *
- *  xtboard.h  --  Routines for getting useful information from the board.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002 Tensilica Inc.
- */
-
-
-#include <xtensa/xt2000.h>
-
-#define XTBOARD_RTC_ERROR       -1
-#define XTBOARD_RTC_STOPPED     -2
-
-
-/*  xt2000-i2cdev.c:  */
-typedef void XtboardDelayFunc( unsigned );
-extern XtboardDelayFunc* xtboard_set_nsdelay_func( XtboardDelayFunc *delay_fn );
-extern int xtboard_i2c_read (unsigned id, unsigned char *buf, unsigned addr, unsigned size);
-extern int xtboard_i2c_write(unsigned id, unsigned char *buf, unsigned addr, unsigned size);
-extern int xtboard_i2c_wait_nvram_ack(unsigned id, unsigned swtimer);
-
-/*  xtboard.c:  */
-extern int xtboard_nvram_read (unsigned addr, unsigned len, unsigned char *buf);
-extern int xtboard_nvram_write(unsigned addr, unsigned len, unsigned char *buf);
-extern int xtboard_nvram_binfo_read (xt2000_nvram_binfo *buf);
-extern int xtboard_nvram_binfo_write(xt2000_nvram_binfo *buf);
-extern int xtboard_nvram_binfo_valid(xt2000_nvram_binfo *buf);
-extern int xtboard_ethermac_get(unsigned char *buf);
-extern int xtboard_ethermac_set(unsigned char *buf);
-
-/*+*----------------------------------------------------------------------------
-/ Function: xtboard_get_rtc_time
-/
-/ Description:  Get time stored in real-time clock.
-/
-/ Returns: time in seconds stored in real-time clock.
-/-**----------------------------------------------------------------------------*/
-
-extern unsigned xtboard_get_rtc_time(void);
-
-/*+*----------------------------------------------------------------------------
-/ Function: xtboard_set_rtc_time
-/
-/ Description:  Set time stored in real-time clock.
-/
-/ Parameters:   time -- time in seconds to store to real-time clock
-/
-/ Returns: 0 on success, xtboard_i2c_write() error code otherwise.
-/-**----------------------------------------------------------------------------*/
-
-extern int xtboard_set_rtc_time(unsigned time);
-
-
-/*  xtfreq.c:  */
-/*+*----------------------------------------------------------------------------
-/ Function: xtboard_measure_sys_clk
-/
-/ Description:  Get frequency of system clock.
-/
-/ Parameters:   none
-/
-/ Returns: frequency of system clock.
-/-**----------------------------------------------------------------------------*/
-
-extern unsigned xtboard_measure_sys_clk(void);
-
-
-#if 0   /* old stuff from xtboard.c: */
-
-/*+*----------------------------------------------------------------------------
-/ Function: xtboard_nvram valid
-/
-/ Description:  Determines if data in NVRAM is valid.
-/
-/ Parameters:   delay -- 10us delay function
-/
-/ Returns: 1 if NVRAM is valid, 0 otherwise
-/-**----------------------------------------------------------------------------*/
-
-extern unsigned xtboard_nvram_valid(void (*delay)( void ));
-
-/*+*----------------------------------------------------------------------------
-/ Function: xtboard_get_nvram_contents
-/
-/ Description:  Returns contents of NVRAM.
-/
-/ Parameters:   buf -- buffer to NVRAM contents.
-/               delay -- 10us delay function
-/
-/ Returns: 1 if NVRAM is valid, 0 otherwise
-/-**----------------------------------------------------------------------------*/
-
-extern unsigned xtboard_get_nvram_contents(unsigned char *buf, void (*delay)( void ));
-
-/*+*----------------------------------------------------------------------------
-/ Function: xtboard_get_ether_addr
-/
-/ Description:  Returns ethernet address of board.
-/
-/ Parameters:   buf -- buffer to store ethernet address
-/               delay -- 10us delay function
-/
-/ Returns: nothing.
-/-**----------------------------------------------------------------------------*/
-
-extern void xtboard_get_ether_addr(unsigned char *buf, void (*delay)( void ));
-
-#endif /*0*/
-
-
-#endif /*_xtboard_h_included_*/
-
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index e618b25b5add..a1b04d8a1d01 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -61,7 +61,6 @@ header-y += fd.h
 header-y += fdreg.h
 header-y += fib_rules.h
 header-y += fuse.h
-header-y += futex.h
 header-y += genetlink.h
 header-y += gen_stats.h
 header-y += gigaset_dev.h
@@ -203,6 +202,7 @@ unifdef-y += fb.h
 unifdef-y += fcntl.h
 unifdef-y += filter.h
 unifdef-y += flat.h
+unifdef-y += futex.h
 unifdef-y += fs.h
 unifdef-y += gameport.h
 unifdef-y += generic_serial.h
diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
new file mode 100644
index 000000000000..05e540d6963a
--- /dev/null
+++ b/include/linux/bitrev.h
@@ -0,0 +1,15 @@
+#ifndef _LINUX_BITREV_H
+#define _LINUX_BITREV_H
+
+#include <linux/types.h>
+
+extern u8 const byte_rev_table[256];
+
+static inline u8 bitrev8(u8 byte)
+{
+        return byte_rev_table[byte];
+}
+
+extern u32 bitrev32(u32 in);
+
+#endif /* _LINUX_BITREV_H */
diff --git a/include/linux/bug.h b/include/linux/bug.h
new file mode 100644
index 000000000000..42aa0a54b6f4
--- /dev/null
+++ b/include/linux/bug.h
@@ -0,0 +1,47 @@
+#ifndef _LINUX_BUG_H
+#define _LINUX_BUG_H
+
+#include <linux/module.h>
+#include <asm/bug.h>
+
+enum bug_trap_type {
+        BUG_TRAP_TYPE_NONE = 0,
+        BUG_TRAP_TYPE_WARN = 1,
+        BUG_TRAP_TYPE_BUG = 2,
+};
+
+#ifdef CONFIG_GENERIC_BUG
+#include <asm-generic/bug.h>
+
+static inline int is_warning_bug(const struct bug_entry *bug)
+{
+        return bug->flags & BUGFLAG_WARNING;
+}
+
+const struct bug_entry *find_bug(unsigned long bugaddr);
+
+enum bug_trap_type report_bug(unsigned long bug_addr);
+
+int  module_bug_finalize(const Elf_Ehdr *, const Elf_Shdr *,
+                         struct module *);
+void module_bug_cleanup(struct module *);
+
+/* These are defined by the architecture */
+int is_valid_bugaddr(unsigned long addr);
+
+#else   /* !CONFIG_GENERIC_BUG */
+
+static inline enum bug_trap_type report_bug(unsigned long bug_addr)
+{
+        return BUG_TRAP_TYPE_BUG;
+}
+static inline int  module_bug_finalize(const Elf_Ehdr *hdr,
+                                        const Elf_Shdr *sechdrs,
+                                        struct module *mod)
+{
+        return 0;
+}
+static inline void module_bug_cleanup(struct module *mod) {}
+
+#endif  /* CONFIG_GENERIC_BUG */
+#endif  /* _LINUX_BUG_H */
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index d852024ed095..1622d23a8dc3 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -159,7 +159,7 @@ static inline s64 cyc2ns(struct clocksource *cs, cycle_t cycles)
  * Unless you're the timekeeping code, you should not be using this!
  */
 static inline void clocksource_calculate_interval(struct clocksource *c,
-                                                unsigned long length_nsec)
+                                                  unsigned long length_nsec)
 {
         u64 tmp;
 
diff --git a/include/linux/crc32.h b/include/linux/crc32.h
index 56c0645789a9..e20dd1f9b40a 100644
--- a/include/linux/crc32.h
+++ b/include/linux/crc32.h
@@ -6,10 +6,10 @@
 #define _LINUX_CRC32_H
 
 #include <linux/types.h>
+#include <linux/bitrev.h>
 
 extern u32  crc32_le(u32 crc, unsigned char const *p, size_t len);
 extern u32  crc32_be(u32 crc, unsigned char const *p, size_t len);
-extern u32  bitreverse(u32 in);
 
 #define crc32(seed, data, length)  crc32_le(seed, (unsigned char const *)data, length)
 
@@ -21,7 +21,7 @@ extern u32  bitreverse(u32 in);
  * is in bit nr 0], thus it must be reversed before use. Except for
  * nics that bit swap the result internally...
  */
-#define ether_crc(length, data)    bitreverse(crc32_le(~0, data, length))
+#define ether_crc(length, data)    bitrev32(crc32_le(~0, data, length))
 #define ether_crc_le(length, data) crc32_le(~0, data, length)
 
 #endif /* _LINUX_CRC32_H */
diff --git a/include/linux/device-mapper.h b/include/linux/device-mapper.h
index 03ef41c1eaac..499f5373e213 100644
--- a/include/linux/device-mapper.h
+++ b/include/linux/device-mapper.h
@@ -39,7 +39,8 @@ typedef void (*dm_dtr_fn) (struct dm_target *ti);
  * The map function must return:
  * < 0: error
  * = 0: The target will handle the io by resubmitting it later
- * > 0: simple remap complete
+ * = 1: simple remap complete
+ * = 2: The target wants to push back the io
  */
 typedef int (*dm_map_fn) (struct dm_target *ti, struct bio *bio,
                           union map_info *map_context);
@@ -50,6 +51,7 @@ typedef int (*dm_map_fn) (struct dm_target *ti, struct bio *bio,
  * 0   : ended successfully
  * 1   : for some reason the io has still not completed (eg,
  *       multipath target might want to requeue a failed io).
+ * 2   : The target wants to push back the io
  */
 typedef int (*dm_endio_fn) (struct dm_target *ti,
                             struct bio *bio, int error,
@@ -173,7 +175,7 @@ void *dm_get_mdptr(struct mapped_device *md);
 /*
  * A device can still be used while suspended, but I/O is deferred.
  */
-int dm_suspend(struct mapped_device *md, int with_lockfs);
+int dm_suspend(struct mapped_device *md, unsigned suspend_flags);
 int dm_resume(struct mapped_device *md);
 
 /*
@@ -188,6 +190,7 @@ int dm_wait_event(struct mapped_device *md, int event_nr);
 const char *dm_device_name(struct mapped_device *md);
 struct gendisk *dm_disk(struct mapped_device *md);
 int dm_suspended(struct mapped_device *md);
+int dm_noflush_suspending(struct dm_target *ti);
 
 /*
  * Geometry functions.
diff --git a/include/linux/dm-ioctl.h b/include/linux/dm-ioctl.h
index 8853fc4d1c5e..b93486107821 100644
--- a/include/linux/dm-ioctl.h
+++ b/include/linux/dm-ioctl.h
@@ -285,9 +285,9 @@ typedef char ioctl_struct[308];
 #define DM_DEV_SET_GEOMETRY     _IOWR(DM_IOCTL, DM_DEV_SET_GEOMETRY_CMD, struct dm_ioctl)
 
 #define DM_VERSION_MAJOR        4
-#define DM_VERSION_MINOR        10
+#define DM_VERSION_MINOR        11
 #define DM_VERSION_PATCHLEVEL   0
-#define DM_VERSION_EXTRA        "-ioctl (2006-09-14)"
+#define DM_VERSION_EXTRA        "-ioctl (2006-10-12)"
 
 /* Status bits */
 #define DM_READONLY_FLAG        (1 << 0) /* In/Out */
@@ -323,4 +323,9 @@ typedef char ioctl_struct[308];
  */
 #define DM_SKIP_LOCKFS_FLAG     (1 << 10) /* In */
 
+/*
+ * Set this to suspend without flushing queued ios.
+ */
+#define DM_NOFLUSH_FLAG         (1 << 11) /* In */
+
 #endif                          /* _LINUX_DM_IOCTL_H */
diff --git a/include/linux/fault-inject.h b/include/linux/fault-inject.h
new file mode 100644
index 000000000000..32368c4f0326
--- /dev/null
+++ b/include/linux/fault-inject.h
@@ -0,0 +1,84 @@
+#ifndef _LINUX_FAULT_INJECT_H
+#define _LINUX_FAULT_INJECT_H
+
+#ifdef CONFIG_FAULT_INJECTION
+
+#include <linux/types.h>
+#include <linux/debugfs.h>
+#include <asm/atomic.h>
+
+/*
+ * For explanation of the elements of this struct, see
+ * Documentation/fault-injection/fault-injection.txt
+ */
+struct fault_attr {
+        unsigned long probability;
+        unsigned long interval;
+        atomic_t times;
+        atomic_t space;
+        unsigned long verbose;
+        u32 task_filter;
+        unsigned long stacktrace_depth;
+        unsigned long require_start;
+        unsigned long require_end;
+        unsigned long reject_start;
+        unsigned long reject_end;
+
+        unsigned long count;
+
+#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
+
+        struct {
+                struct dentry *dir;
+
+                struct dentry *probability_file;
+                struct dentry *interval_file;
+                struct dentry *times_file;
+                struct dentry *space_file;
+                struct dentry *verbose_file;
+                struct dentry *task_filter_file;
+                struct dentry *stacktrace_depth_file;
+                struct dentry *require_start_file;
+                struct dentry *require_end_file;
+                struct dentry *reject_start_file;
+                struct dentry *reject_end_file;
+        } dentries;
+
+#endif
+};
+
+#define FAULT_ATTR_INITIALIZER {                                \
+                .interval = 1,                                  \
+                .times = ATOMIC_INIT(1),                        \
+                .require_end = ULONG_MAX,                       \
+                .stacktrace_depth = 32,                         \
+                .verbose = 2,                                   \
+        }
+
+#define DECLARE_FAULT_ATTR(name) struct fault_attr name = FAULT_ATTR_INITIALIZER
+int setup_fault_attr(struct fault_attr *attr, char *str);
+void should_fail_srandom(unsigned long entropy);
+bool should_fail(struct fault_attr *attr, ssize_t size);
+
+#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
+
+int init_fault_attr_dentries(struct fault_attr *attr, const char *name);
+void cleanup_fault_attr_dentries(struct fault_attr *attr);
+
+#else /* CONFIG_FAULT_INJECTION_DEBUG_FS */
+
+static inline int init_fault_attr_dentries(struct fault_attr *attr,
+                                          const char *name)
+{
+        return -ENODEV;
+}
+
+static inline void cleanup_fault_attr_dentries(struct fault_attr *attr)
+{
+}
+
+#endif /* CONFIG_FAULT_INJECTION_DEBUG_FS */
+
+#endif /* CONFIG_FAULT_INJECTION */
+
+#endif /* _LINUX_FAULT_INJECT_H */
diff --git a/include/linux/fb.h b/include/linux/fb.h
index fa23e0671bb3..6fe56aaa6685 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -970,11 +970,11 @@ extern struct fb_videomode *fb_find_best_display(struct fb_monspecs *specs,
 /* drivers/video/fbcmap.c */
 extern int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp);
 extern void fb_dealloc_cmap(struct fb_cmap *cmap);
-extern int fb_copy_cmap(struct fb_cmap *from, struct fb_cmap *to);
-extern int fb_cmap_to_user(struct fb_cmap *from, struct fb_cmap_user *to);
+extern int fb_copy_cmap(const struct fb_cmap *from, struct fb_cmap *to);
+extern int fb_cmap_to_user(const struct fb_cmap *from, struct fb_cmap_user *to);
 extern int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *fb_info);
 extern int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *fb_info);
-extern struct fb_cmap *fb_default_cmap(int len);
+extern const struct fb_cmap *fb_default_cmap(int len);
 extern void fb_invert_cmaps(void);
 
 struct fb_videomode {
diff --git a/include/linux/file.h b/include/linux/file.h
index 6e77b9177f9e..edca361f2ab4 100644
--- a/include/linux/file.h
+++ b/include/linux/file.h
@@ -26,19 +26,12 @@ struct embedded_fd_set {
         unsigned long fds_bits[1];
 };
 
-/*
- * More than this number of fds: we use a separately allocated fd_set
- */
-#define EMBEDDED_FD_SET_SIZE (BITS_PER_BYTE * sizeof(struct embedded_fd_set))
-
 struct fdtable {
         unsigned int max_fds;
-        int max_fdset;
         struct file ** fd;      /* current fd array */
         fd_set *close_on_exec;
         fd_set *open_fds;
         struct rcu_head rcu;
-        struct files_struct *free_files;
         struct fdtable *next;
 };
 
@@ -83,14 +76,8 @@ extern int get_unused_fd(void);
 extern void FASTCALL(put_unused_fd(unsigned int fd));
 struct kmem_cache;
 
-extern struct file ** alloc_fd_array(int);
-extern void free_fd_array(struct file **, int);
-
-extern fd_set *alloc_fdset(int);
-extern void free_fdset(fd_set *, int);
-
 extern int expand_files(struct files_struct *, int nr);
-extern void free_fdtable(struct fdtable *fdt);
+extern void free_fdtable_rcu(struct rcu_head *rcu);
 extern void __init files_defer_init(void);
 
 static inline struct file * fcheck_files(struct files_struct *files, unsigned int fd)
diff --git a/include/linux/freezer.h b/include/linux/freezer.h
index 6e05e3e7ce39..393063096134 100644
--- a/include/linux/freezer.h
+++ b/include/linux/freezer.h
@@ -1,5 +1,7 @@
 /* Freezer declarations */
 
+#include <linux/sched.h>
+
 #ifdef CONFIG_PM
 /*
  * Check if a process has been frozen
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 70b99fbb560b..adce6e1d70c2 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -269,6 +269,7 @@ extern int dir_notify_enable;
 #include <linux/types.h>
 #include <linux/kdev_t.h>
 #include <linux/dcache.h>
+#include <linux/namei.h>
 #include <linux/stat.h>
 #include <linux/cache.h>
 #include <linux/kobject.h>
@@ -482,21 +483,6 @@ struct block_device {
 };
 
 /*
- * bdev->bd_mutex nesting subclasses for the lock validator:
- *
- * 0: normal
- * 1: 'whole'
- * 2: 'partition'
- */
-enum bdev_bd_mutex_lock_class
-{
-        BD_MUTEX_NORMAL,
-        BD_MUTEX_WHOLE,
-        BD_MUTEX_PARTITION
-};
-
-
-/*
  * Radix-tree tags, for tagging dirty and writeback pages within the pagecache
  * radix trees
  */
@@ -726,8 +712,9 @@ struct file {
                 struct list_head        fu_list;
                 struct rcu_head         fu_rcuhead;
         } f_u;
-        struct dentry           *f_dentry;
-        struct vfsmount         *f_vfsmnt;
+        struct path             f_path;
+#define f_dentry        f_path.dentry
+#define f_vfsmnt        f_path.mnt
         const struct file_operations    *f_op;
         atomic_t                f_count;
         unsigned int            f_flags;
@@ -1239,7 +1226,7 @@ extern void touch_atime(struct vfsmount *mnt, struct dentry *dentry);
 static inline void file_accessed(struct file *file)
 {
         if (!(file->f_flags & O_NOATIME))
-                touch_atime(file->f_vfsmnt, file->f_dentry);
+                touch_atime(file->f_path.mnt, file->f_path.dentry);
 }
 
 int sync_inode(struct inode *inode, struct writeback_control *wbc);
@@ -1499,7 +1486,6 @@ extern void bd_set_size(struct block_device *, loff_t size);
 extern void bd_forget(struct inode *inode);
 extern void bdput(struct block_device *);
 extern struct block_device *open_by_devnum(dev_t, unsigned);
-extern struct block_device *open_partition_by_devnum(dev_t, unsigned);
 extern const struct address_space_operations def_blk_aops;
 #else
 static inline void bd_forget(struct inode *inode) {}
@@ -1517,7 +1503,6 @@ extern int blkdev_driver_ioctl(struct inode *inode, struct file *file,
 extern long compat_blkdev_ioctl(struct file *, unsigned, unsigned long);
 extern int blkdev_get(struct block_device *, mode_t, unsigned);
 extern int blkdev_put(struct block_device *);
-extern int blkdev_put_partition(struct block_device *);
 extern int bd_claim(struct block_device *, void *);
 extern void bd_release(struct block_device *);
 #ifdef CONFIG_SYSFS
@@ -1632,7 +1617,7 @@ static inline void put_write_access(struct inode * inode)
 static inline void allow_write_access(struct file *file)
 {
         if (file)
-                atomic_inc(&file->f_dentry->d_inode->i_writecount);
+                atomic_inc(&file->f_path.dentry->d_inode->i_writecount);
 }
 extern int do_pipe(int *);
 extern struct file *create_read_pipe(struct file *f);
diff --git a/include/linux/fs_stack.h b/include/linux/fs_stack.h
new file mode 100644
index 000000000000..bb516ceeefc9
--- /dev/null
+++ b/include/linux/fs_stack.h
@@ -0,0 +1,31 @@
+#ifndef _LINUX_FS_STACK_H
+#define _LINUX_FS_STACK_H
+
+/* This file defines generic functions used primarily by stackable
+ * filesystems; none of these functions require i_mutex to be held.
+ */
+
+#include <linux/fs.h>
+
+/* externs for fs/stack.c */
+extern void fsstack_copy_attr_all(struct inode *dest, const struct inode *src,
+                                int (*get_nlinks)(struct inode *));
+
+extern void fsstack_copy_inode_size(struct inode *dst, const struct inode *src);
+
+/* inlines */
+static inline void fsstack_copy_attr_atime(struct inode *dest,
+                                           const struct inode *src)
+{
+        dest->i_atime = src->i_atime;
+}
+
+static inline void fsstack_copy_attr_times(struct inode *dest,
+                                           const struct inode *src)
+{
+        dest->i_atime = src->i_atime;
+        dest->i_mtime = src->i_mtime;
+        dest->i_ctime = src->i_ctime;
+}
+
+#endif /* _LINUX_FS_STACK_H */
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 3da29e2d524a..abb64c437f6f 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -19,6 +19,7 @@
 #define _FSL_DEVICE_H_
 
 #include <linux/types.h>
+#include <linux/phy.h>
 
 /*
  * Some conventions on how we handle peripherals on Freescale chips
diff --git a/include/linux/fsnotify.h b/include/linux/fsnotify.h
index d4f219ffaa5d..dfc4e4f68da4 100644
--- a/include/linux/fsnotify.h
+++ b/include/linux/fsnotify.h
@@ -164,7 +164,7 @@ static inline void fsnotify_open(struct dentry *dentry)
  */
 static inline void fsnotify_close(struct file *file)
 {
-        struct dentry *dentry = file->f_dentry;
+        struct dentry *dentry = file->f_path.dentry;
         struct inode *inode = dentry->d_inode;
         const char *name = dentry->d_name.name;
         mode_t mode = file->f_mode;
diff --git a/include/linux/futex.h b/include/linux/futex.h
index d097b5b72bc6..3f153b4e156c 100644
--- a/include/linux/futex.h
+++ b/include/linux/futex.h
@@ -93,6 +93,7 @@ struct robust_list_head {
  */
 #define ROBUST_LIST_LIMIT       2048
 
+#ifdef __KERNEL__
 long do_futex(u32 __user *uaddr, int op, u32 val, unsigned long timeout,
               u32 __user *uaddr2, u32 val2, u32 val3);
 
@@ -110,6 +111,7 @@ static inline void exit_pi_state_list(struct task_struct *curr)
 {
 }
 #endif
+#endif /* __KERNEL__ */
 
 #define FUTEX_OP_SET            0       /* *(int *)UADDR2 = OPARG; */
 #define FUTEX_OP_ADD            1       /* *(int *)UADDR2 += OPARG; */
diff --git a/include/linux/generic_serial.h b/include/linux/generic_serial.h
index e25384561955..5412da28fa47 100644
--- a/include/linux/generic_serial.h
+++ b/include/linux/generic_serial.h
@@ -91,7 +91,7 @@ void gs_hangup(struct tty_struct *tty);
 int  gs_block_til_ready(void *port, struct file *filp);
 void gs_close(struct tty_struct *tty, struct file *filp);
 void gs_set_termios (struct tty_struct * tty, 
-                     struct termios * old_termios);
+                     struct ktermios * old_termios);
 int  gs_init_port(struct gs_port *port);
 int  gs_setserial(struct gs_port *port, struct serial_struct __user *sp);
 int  gs_getserial(struct gs_port *port, struct serial_struct __user *sp);
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index 41f276fdd185..0a022b2f63fc 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -83,6 +83,9 @@ struct hd_struct {
         struct kobject *holder_dir;
         unsigned ios[2], sectors[2];    /* READs and WRITEs */
         int policy, partno;
+#ifdef CONFIG_FAIL_MAKE_REQUEST
+        int make_it_fail;
+#endif
 };
 
 #define GENHD_FL_REMOVABLE                      1
@@ -90,6 +93,7 @@ struct hd_struct {
 #define GENHD_FL_CD                             8
 #define GENHD_FL_UP                             16
 #define GENHD_FL_SUPPRESS_PARTITION_INFO        32
+#define GENHD_FL_FAIL                           64
 
 struct disk_stats {
         unsigned long sectors[2];       /* READs and WRITEs */
diff --git a/include/linux/hid-debug.h b/include/linux/hid-debug.h
new file mode 100644
index 000000000000..f04d6d75c098
--- /dev/null
+++ b/include/linux/hid-debug.h
@@ -0,0 +1,757 @@
+/*
+ * $Id: hid-debug.h,v 1.8 2001/09/25 09:37:57 vojtech Exp $
+ *
+ *  (c) 1999 Andreas Gal                <gal@cs.uni-magdeburg.de>
+ *  (c) 2000-2001 Vojtech Pavlik        <vojtech@ucw.cz>
+ *
+ *  Some debug stuff for the HID parser.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Should you need to contact me, the author, you can do so either by
+ * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
+ * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
+ */
+
+#include <linux/input.h>
+
+struct hid_usage_entry {
+        unsigned  page;
+        unsigned  usage;
+        char     *description;
+};
+
+static const struct hid_usage_entry hid_usage_table[] = {
+  {  0,      0, "Undefined" },
+  {  1,      0, "GenericDesktop" },
+    {0, 0x01, "Pointer"},
+    {0, 0x02, "Mouse"},
+    {0, 0x04, "Joystick"},
+    {0, 0x05, "GamePad"},
+    {0, 0x06, "Keyboard"},
+    {0, 0x07, "Keypad"},
+    {0, 0x08, "MultiAxis"},
+      {0, 0x30, "X"},
+      {0, 0x31, "Y"},
+      {0, 0x32, "Z"},
+      {0, 0x33, "Rx"},
+      {0, 0x34, "Ry"},
+      {0, 0x35, "Rz"},
+      {0, 0x36, "Slider"},
+      {0, 0x37, "Dial"},
+      {0, 0x38, "Wheel"},
+      {0, 0x39, "HatSwitch"},
+    {0, 0x3a, "CountedBuffer"},
+      {0, 0x3b, "ByteCount"},
+      {0, 0x3c, "MotionWakeup"},
+      {0, 0x3d, "Start"},
+      {0, 0x3e, "Select"},
+      {0, 0x40, "Vx"},
+      {0, 0x41, "Vy"},
+      {0, 0x42, "Vz"},
+      {0, 0x43, "Vbrx"},
+      {0, 0x44, "Vbry"},
+      {0, 0x45, "Vbrz"},
+      {0, 0x46, "Vno"},
+    {0, 0x80, "SystemControl"},
+      {0, 0x81, "SystemPowerDown"},
+      {0, 0x82, "SystemSleep"},
+      {0, 0x83, "SystemWakeUp"},
+      {0, 0x84, "SystemContextMenu"},
+      {0, 0x85, "SystemMainMenu"},
+      {0, 0x86, "SystemAppMenu"},
+      {0, 0x87, "SystemMenuHelp"},
+      {0, 0x88, "SystemMenuExit"},
+      {0, 0x89, "SystemMenuSelect"},
+      {0, 0x8a, "SystemMenuRight"},
+      {0, 0x8b, "SystemMenuLeft"},
+      {0, 0x8c, "SystemMenuUp"},
+      {0, 0x8d, "SystemMenuDown"},
+      {0, 0x90, "D-PadUp"},
+      {0, 0x91, "D-PadDown"},
+      {0, 0x92, "D-PadRight"},
+      {0, 0x93, "D-PadLeft"},
+  {  2, 0, "Simulation" },
+      {0, 0xb0, "Aileron"},
+      {0, 0xb1, "AileronTrim"},
+      {0, 0xb2, "Anti-Torque"},
+      {0, 0xb3, "Autopilot"},
+      {0, 0xb4, "Chaff"},
+      {0, 0xb5, "Collective"},
+      {0, 0xb6, "DiveBrake"},
+      {0, 0xb7, "ElectronicCountermeasures"},
+      {0, 0xb8, "Elevator"},
+      {0, 0xb9, "ElevatorTrim"},
+      {0, 0xba, "Rudder"},
+      {0, 0xbb, "Throttle"},
+      {0, 0xbc, "FlightCommunications"},
+      {0, 0xbd, "FlareRelease"},
+      {0, 0xbe, "LandingGear"},
+      {0, 0xbf, "ToeBrake"},
+  {  7, 0, "Keyboard" },
+  {  8, 0, "LED" },
+      {0, 0x01, "NumLock"},
+      {0, 0x02, "CapsLock"},
+      {0, 0x03, "ScrollLock"},
+      {0, 0x04, "Compose"},
+      {0, 0x05, "Kana"},
+      {0, 0x4b, "GenericIndicator"},
+  {  9, 0, "Button" },
+  { 10, 0, "Ordinal" },
+  { 12, 0, "Consumer" },
+      {0, 0x238, "HorizontalWheel"},
+  { 13, 0, "Digitizers" },
+    {0, 0x01, "Digitizer"},
+    {0, 0x02, "Pen"},
+    {0, 0x03, "LightPen"},
+    {0, 0x04, "TouchScreen"},
+    {0, 0x05, "TouchPad"},
+    {0, 0x20, "Stylus"},
+    {0, 0x21, "Puck"},
+    {0, 0x22, "Finger"},
+    {0, 0x30, "TipPressure"},
+    {0, 0x31, "BarrelPressure"},
+    {0, 0x32, "InRange"},
+    {0, 0x33, "Touch"},
+    {0, 0x34, "UnTouch"},
+    {0, 0x35, "Tap"},
+    {0, 0x39, "TabletFunctionKey"},
+    {0, 0x3a, "ProgramChangeKey"},
+    {0, 0x3c, "Invert"},
+    {0, 0x42, "TipSwitch"},
+    {0, 0x43, "SecondaryTipSwitch"},
+    {0, 0x44, "BarrelSwitch"},
+    {0, 0x45, "Eraser"},
+    {0, 0x46, "TabletPick"},
+  { 15, 0, "PhysicalInterfaceDevice" },
+    {0, 0x00, "Undefined"},
+    {0, 0x01, "Physical_Interface_Device"},
+      {0, 0x20, "Normal"},
+    {0, 0x21, "Set_Effect_Report"},
+      {0, 0x22, "Effect_Block_Index"},
+      {0, 0x23, "Parameter_Block_Offset"},
+      {0, 0x24, "ROM_Flag"},
+      {0, 0x25, "Effect_Type"},
+        {0, 0x26, "ET_Constant_Force"},
+        {0, 0x27, "ET_Ramp"},
+        {0, 0x28, "ET_Custom_Force_Data"},
+        {0, 0x30, "ET_Square"},
+        {0, 0x31, "ET_Sine"},
+        {0, 0x32, "ET_Triangle"},
+        {0, 0x33, "ET_Sawtooth_Up"},
+        {0, 0x34, "ET_Sawtooth_Down"},
+        {0, 0x40, "ET_Spring"},
+        {0, 0x41, "ET_Damper"},
+        {0, 0x42, "ET_Inertia"},
+        {0, 0x43, "ET_Friction"},
+      {0, 0x50, "Duration"},
+      {0, 0x51, "Sample_Period"},
+      {0, 0x52, "Gain"},
+      {0, 0x53, "Trigger_Button"},
+      {0, 0x54, "Trigger_Repeat_Interval"},
+      {0, 0x55, "Axes_Enable"},
+        {0, 0x56, "Direction_Enable"},
+      {0, 0x57, "Direction"},
+      {0, 0x58, "Type_Specific_Block_Offset"},
+        {0, 0x59, "Block_Type"},
+        {0, 0x5A, "Set_Envelope_Report"},
+          {0, 0x5B, "Attack_Level"},
+          {0, 0x5C, "Attack_Time"},
+          {0, 0x5D, "Fade_Level"},
+          {0, 0x5E, "Fade_Time"},
+        {0, 0x5F, "Set_Condition_Report"},
+        {0, 0x60, "CP_Offset"},
+        {0, 0x61, "Positive_Coefficient"},
+        {0, 0x62, "Negative_Coefficient"},
+        {0, 0x63, "Positive_Saturation"},
+        {0, 0x64, "Negative_Saturation"},
+        {0, 0x65, "Dead_Band"},
+      {0, 0x66, "Download_Force_Sample"},
+      {0, 0x67, "Isoch_Custom_Force_Enable"},
+      {0, 0x68, "Custom_Force_Data_Report"},
+        {0, 0x69, "Custom_Force_Data"},
+        {0, 0x6A, "Custom_Force_Vendor_Defined_Data"},
+      {0, 0x6B, "Set_Custom_Force_Report"},
+        {0, 0x6C, "Custom_Force_Data_Offset"},
+        {0, 0x6D, "Sample_Count"},
+      {0, 0x6E, "Set_Periodic_Report"},
+        {0, 0x6F, "Offset"},
+        {0, 0x70, "Magnitude"},
+        {0, 0x71, "Phase"},
+        {0, 0x72, "Period"},
+      {0, 0x73, "Set_Constant_Force_Report"},
+        {0, 0x74, "Set_Ramp_Force_Report"},
+        {0, 0x75, "Ramp_Start"},
+        {0, 0x76, "Ramp_End"},
+      {0, 0x77, "Effect_Operation_Report"},
+        {0, 0x78, "Effect_Operation"},
+          {0, 0x79, "Op_Effect_Start"},
+          {0, 0x7A, "Op_Effect_Start_Solo"},
+          {0, 0x7B, "Op_Effect_Stop"},
+          {0, 0x7C, "Loop_Count"},
+      {0, 0x7D, "Device_Gain_Report"},
+        {0, 0x7E, "Device_Gain"},
+    {0, 0x7F, "PID_Pool_Report"},
+      {0, 0x80, "RAM_Pool_Size"},
+      {0, 0x81, "ROM_Pool_Size"},
+      {0, 0x82, "ROM_Effect_Block_Count"},
+      {0, 0x83, "Simultaneous_Effects_Max"},
+      {0, 0x84, "Pool_Alignment"},
+    {0, 0x85, "PID_Pool_Move_Report"},
+      {0, 0x86, "Move_Source"},
+      {0, 0x87, "Move_Destination"},
+      {0, 0x88, "Move_Length"},
+    {0, 0x89, "PID_Block_Load_Report"},
+      {0, 0x8B, "Block_Load_Status"},
+      {0, 0x8C, "Block_Load_Success"},
+      {0, 0x8D, "Block_Load_Full"},
+      {0, 0x8E, "Block_Load_Error"},
+      {0, 0x8F, "Block_Handle"},
+      {0, 0x90, "PID_Block_Free_Report"},
+      {0, 0x91, "Type_Specific_Block_Handle"},
+    {0, 0x92, "PID_State_Report"},
+      {0, 0x94, "Effect_Playing"},
+      {0, 0x95, "PID_Device_Control_Report"},
+        {0, 0x96, "PID_Device_Control"},
+        {0, 0x97, "DC_Enable_Actuators"},
+        {0, 0x98, "DC_Disable_Actuators"},
+        {0, 0x99, "DC_Stop_All_Effects"},
+        {0, 0x9A, "DC_Device_Reset"},
+        {0, 0x9B, "DC_Device_Pause"},
+        {0, 0x9C, "DC_Device_Continue"},
+      {0, 0x9F, "Device_Paused"},
+      {0, 0xA0, "Actuators_Enabled"},
+      {0, 0xA4, "Safety_Switch"},
+      {0, 0xA5, "Actuator_Override_Switch"},
+      {0, 0xA6, "Actuator_Power"},
+    {0, 0xA7, "Start_Delay"},
+    {0, 0xA8, "Parameter_Block_Size"},
+    {0, 0xA9, "Device_Managed_Pool"},
+    {0, 0xAA, "Shared_Parameter_Blocks"},
+    {0, 0xAB, "Create_New_Effect_Report"},
+    {0, 0xAC, "RAM_Pool_Available"},
+  { 0x84, 0, "Power Device" },
+    { 0x84, 0x02, "PresentStatus" },
+    { 0x84, 0x03, "ChangeStatus" },
+    { 0x84, 0x04, "UPS" },
+    { 0x84, 0x05, "PowerSupply" },
+    { 0x84, 0x10, "BatterySystem" },
+    { 0x84, 0x11, "BatterySystemID" },
+    { 0x84, 0x12, "Battery" },
+    { 0x84, 0x13, "BatteryID" },
+    { 0x84, 0x14, "Charger" },
+    { 0x84, 0x15, "ChargerID" },
+    { 0x84, 0x16, "PowerConverter" },
+    { 0x84, 0x17, "PowerConverterID" },
+    { 0x84, 0x18, "OutletSystem" },
+    { 0x84, 0x19, "OutletSystemID" },
+    { 0x84, 0x1a, "Input" },
+    { 0x84, 0x1b, "InputID" },
+    { 0x84, 0x1c, "Output" },
+    { 0x84, 0x1d, "OutputID" },
+    { 0x84, 0x1e, "Flow" },
+    { 0x84, 0x1f, "FlowID" },
+    { 0x84, 0x20, "Outlet" },
+    { 0x84, 0x21, "OutletID" },
+    { 0x84, 0x22, "Gang" },
+    { 0x84, 0x24, "PowerSummary" },
+    { 0x84, 0x25, "PowerSummaryID" },
+    { 0x84, 0x30, "Voltage" },
+    { 0x84, 0x31, "Current" },
+    { 0x84, 0x32, "Frequency" },
+    { 0x84, 0x33, "ApparentPower" },
+    { 0x84, 0x35, "PercentLoad" },
+    { 0x84, 0x40, "ConfigVoltage" },
+    { 0x84, 0x41, "ConfigCurrent" },
+    { 0x84, 0x43, "ConfigApparentPower" },
+    { 0x84, 0x53, "LowVoltageTransfer" },
+    { 0x84, 0x54, "HighVoltageTransfer" },
+    { 0x84, 0x56, "DelayBeforeStartup" },
+    { 0x84, 0x57, "DelayBeforeShutdown" },
+    { 0x84, 0x58, "Test" },
+    { 0x84, 0x5a, "AudibleAlarmControl" },
+    { 0x84, 0x60, "Present" },
+    { 0x84, 0x61, "Good" },
+    { 0x84, 0x62, "InternalFailure" },
+    { 0x84, 0x65, "Overload" },
+    { 0x84, 0x66, "OverCharged" },
+    { 0x84, 0x67, "OverTemperature" },
+    { 0x84, 0x68, "ShutdownRequested" },
+    { 0x84, 0x69, "ShutdownImminent" },
+    { 0x84, 0x6b, "SwitchOn/Off" },
+    { 0x84, 0x6c, "Switchable" },
+    { 0x84, 0x6d, "Used" },
+    { 0x84, 0x6e, "Boost" },
+    { 0x84, 0x73, "CommunicationLost" },
+    { 0x84, 0xfd, "iManufacturer" },
+    { 0x84, 0xfe, "iProduct" },
+    { 0x84, 0xff, "iSerialNumber" },
+  { 0x85, 0, "Battery System" },
+    { 0x85, 0x01, "SMBBatteryMode" },
+    { 0x85, 0x02, "SMBBatteryStatus" },
+    { 0x85, 0x03, "SMBAlarmWarning" },
+    { 0x85, 0x04, "SMBChargerMode" },
+    { 0x85, 0x05, "SMBChargerStatus" },
+    { 0x85, 0x06, "SMBChargerSpecInfo" },
+    { 0x85, 0x07, "SMBSelectorState" },
+    { 0x85, 0x08, "SMBSelectorPresets" },
+    { 0x85, 0x09, "SMBSelectorInfo" },
+    { 0x85, 0x29, "RemainingCapacityLimit" },
+    { 0x85, 0x2c, "CapacityMode" },
+    { 0x85, 0x42, "BelowRemainingCapacityLimit" },
+    { 0x85, 0x44, "Charging" },
+    { 0x85, 0x45, "Discharging" },
+    { 0x85, 0x4b, "NeedReplacement" },
+    { 0x85, 0x66, "RemainingCapacity" },
+    { 0x85, 0x68, "RunTimeToEmpty" },
+    { 0x85, 0x6a, "AverageTimeToFull" },
+    { 0x85, 0x83, "DesignCapacity" },
+    { 0x85, 0x85, "ManufacturerDate" },
+    { 0x85, 0x89, "iDeviceChemistry" },
+    { 0x85, 0x8b, "Rechargable" },
+    { 0x85, 0x8f, "iOEMInformation" },
+    { 0x85, 0x8d, "CapacityGranularity1" },
+    { 0x85, 0xd0, "ACPresent" },
+  /* pages 0xff00 to 0xffff are vendor-specific */
+  { 0xffff, 0, "Vendor-specific-FF" },
+  { 0, 0, NULL }
+};
+
+static void resolv_usage_page(unsigned page) {
+        const struct hid_usage_entry *p;
+
+        for (p = hid_usage_table; p->description; p++)
+                if (p->page == page) {
+                        printk("%s", p->description);
+                        return;
+                }
+        printk("%04x", page);
+}
+
+static void resolv_usage(unsigned usage) {
+        const struct hid_usage_entry *p;
+
+        resolv_usage_page(usage >> 16);
+        printk(".");
+        for (p = hid_usage_table; p->description; p++)
+                if (p->page == (usage >> 16)) {
+                        for(++p; p->description && p->usage != 0; p++)
+                                if (p->usage == (usage & 0xffff)) {
+                                        printk("%s", p->description);
+                                        return;
+                                }
+                        break;
+                }
+        printk("%04x", usage & 0xffff);
+}
+
+__inline__ static void tab(int n) {
+        while (n--) printk(" ");
+}
+
+static void hid_dump_field(struct hid_field *field, int n) {
+        int j;
+
+        if (field->physical) {
+                tab(n);
+                printk("Physical(");
+                resolv_usage(field->physical); printk(")\n");
+        }
+        if (field->logical) {
+                tab(n);
+                printk("Logical(");
+                resolv_usage(field->logical); printk(")\n");
+        }
+        tab(n); printk("Usage(%d)\n", field->maxusage);
+        for (j = 0; j < field->maxusage; j++) {
+                tab(n+2);resolv_usage(field->usage[j].hid); printk("\n");
+        }
+        if (field->logical_minimum != field->logical_maximum) {
+                tab(n); printk("Logical Minimum(%d)\n", field->logical_minimum);
+                tab(n); printk("Logical Maximum(%d)\n", field->logical_maximum);
+        }
+        if (field->physical_minimum != field->physical_maximum) {
+                tab(n); printk("Physical Minimum(%d)\n", field->physical_minimum);
+                tab(n); printk("Physical Maximum(%d)\n", field->physical_maximum);
+        }
+        if (field->unit_exponent) {
+                tab(n); printk("Unit Exponent(%d)\n", field->unit_exponent);
+        }
+        if (field->unit) {
+                char *systems[5] = { "None", "SI Linear", "SI Rotation", "English Linear", "English Rotation" };
+                char *units[5][8] = {
+                        { "None", "None", "None", "None", "None", "None", "None", "None" },
+                        { "None", "Centimeter", "Gram", "Seconds", "Kelvin",     "Ampere", "Candela", "None" },
+                        { "None", "Radians",    "Gram", "Seconds", "Kelvin",     "Ampere", "Candela", "None" },
+                        { "None", "Inch",       "Slug", "Seconds", "Fahrenheit", "Ampere", "Candela", "None" },
+                        { "None", "Degrees",    "Slug", "Seconds", "Fahrenheit", "Ampere", "Candela", "None" }
+                };
+
+                int i;
+                int sys;
+                __u32 data = field->unit;
+
+                /* First nibble tells us which system we're in. */
+                sys = data & 0xf;
+                data >>= 4;
+
+                if(sys > 4) {
+                        tab(n); printk("Unit(Invalid)\n");
+                }
+                else {
+                        int earlier_unit = 0;
+
+                        tab(n); printk("Unit(%s : ", systems[sys]);
+
+                        for (i=1 ; i<sizeof(__u32)*2 ; i++) {
+                                char nibble = data & 0xf;
+                                data >>= 4;
+                                if (nibble != 0) {
+                                        if(earlier_unit++ > 0)
+                                                printk("*");
+                                        printk("%s", units[sys][i]);
+                                        if(nibble != 1) {
+                                                /* This is a _signed_ nibble(!) */
+
+                                                int val = nibble & 0x7;
+                                                if(nibble & 0x08)
+                                                        val = -((0x7 & ~val) +1);
+                                                printk("^%d", val);
+                                        }
+                                }
+                        }
+                        printk(")\n");
+                }
+        }
+        tab(n); printk("Report Size(%u)\n", field->report_size);
+        tab(n); printk("Report Count(%u)\n", field->report_count);
+        tab(n); printk("Report Offset(%u)\n", field->report_offset);
+
+        tab(n); printk("Flags( ");
+        j = field->flags;
+        printk("%s", HID_MAIN_ITEM_CONSTANT & j ? "Constant " : "");
+        printk("%s", HID_MAIN_ITEM_VARIABLE & j ? "Variable " : "Array ");
+        printk("%s", HID_MAIN_ITEM_RELATIVE & j ? "Relative " : "Absolute ");
+        printk("%s", HID_MAIN_ITEM_WRAP & j ? "Wrap " : "");
+        printk("%s", HID_MAIN_ITEM_NONLINEAR & j ? "NonLinear " : "");
+        printk("%s", HID_MAIN_ITEM_NO_PREFERRED & j ? "NoPrefferedState " : "");
+        printk("%s", HID_MAIN_ITEM_NULL_STATE & j ? "NullState " : "");
+        printk("%s", HID_MAIN_ITEM_VOLATILE & j ? "Volatile " : "");
+        printk("%s", HID_MAIN_ITEM_BUFFERED_BYTE & j ? "BufferedByte " : "");
+        printk(")\n");
+}
+
+static void __attribute__((unused)) hid_dump_device(struct hid_device *device) {
+        struct hid_report_enum *report_enum;
+        struct hid_report *report;
+        struct list_head *list;
+        unsigned i,k;
+        static char *table[] = {"INPUT", "OUTPUT", "FEATURE"};
+
+        for (i = 0; i < HID_REPORT_TYPES; i++) {
+                report_enum = device->report_enum + i;
+                list = report_enum->report_list.next;
+                while (list != &report_enum->report_list) {
+                        report = (struct hid_report *) list;
+                        tab(2);
+                        printk("%s", table[i]);
+                        if (report->id)
+                                printk("(%d)", report->id);
+                        printk("[%s]", table[report->type]);
+                        printk("\n");
+                        for (k = 0; k < report->maxfield; k++) {
+                                tab(4);
+                                printk("Field(%d)\n", k);
+                                hid_dump_field(report->field[k], 6);
+                        }
+                        list = list->next;
+                }
+        }
+}
+
+static void __attribute__((unused)) hid_dump_input(struct hid_usage *usage, __s32 value) {
+        printk("hid-debug: input ");
+        resolv_usage(usage->hid);
+        printk(" = %d\n", value);
+}
+
+
+static char *events[EV_MAX + 1] = {
+        [EV_SYN] = "Sync",                      [EV_KEY] = "Key",
+        [EV_REL] = "Relative",                  [EV_ABS] = "Absolute",
+        [EV_MSC] = "Misc",                      [EV_LED] = "LED",
+        [EV_SND] = "Sound",                     [EV_REP] = "Repeat",
+        [EV_FF] = "ForceFeedback",              [EV_PWR] = "Power",
+        [EV_FF_STATUS] = "ForceFeedbackStatus",
+};
+
+static char *syncs[2] = {
+        [SYN_REPORT] = "Report",                [SYN_CONFIG] = "Config",
+};
+static char *keys[KEY_MAX + 1] = {
+        [KEY_RESERVED] = "Reserved",            [KEY_ESC] = "Esc",
+        [KEY_1] = "1",                          [KEY_2] = "2",
+        [KEY_3] = "3",                          [KEY_4] = "4",
+        [KEY_5] = "5",                          [KEY_6] = "6",
+        [KEY_7] = "7",                          [KEY_8] = "8",
+        [KEY_9] = "9",                          [KEY_0] = "0",
+        [KEY_MINUS] = "Minus",                  [KEY_EQUAL] = "Equal",
+        [KEY_BACKSPACE] = "Backspace",          [KEY_TAB] = "Tab",
+        [KEY_Q] = "Q",                          [KEY_W] = "W",
+        [KEY_E] = "E",                          [KEY_R] = "R",
+        [KEY_T] = "T",                          [KEY_Y] = "Y",
+        [KEY_U] = "U",                          [KEY_I] = "I",
+        [KEY_O] = "O",                          [KEY_P] = "P",
+        [KEY_LEFTBRACE] = "LeftBrace",          [KEY_RIGHTBRACE] = "RightBrace",
+        [KEY_ENTER] = "Enter",                  [KEY_LEFTCTRL] = "LeftControl",
+        [KEY_A] = "A",                          [KEY_S] = "S",
+        [KEY_D] = "D",                          [KEY_F] = "F",
+        [KEY_G] = "G",                          [KEY_H] = "H",
+        [KEY_J] = "J",                          [KEY_K] = "K",
+        [KEY_L] = "L",                          [KEY_SEMICOLON] = "Semicolon",
+        [KEY_APOSTROPHE] = "Apostrophe",        [KEY_GRAVE] = "Grave",
+        [KEY_LEFTSHIFT] = "LeftShift",          [KEY_BACKSLASH] = "BackSlash",
+        [KEY_Z] = "Z",                          [KEY_X] = "X",
+        [KEY_C] = "C",                          [KEY_V] = "V",
+        [KEY_B] = "B",                          [KEY_N] = "N",
+        [KEY_M] = "M",                          [KEY_COMMA] = "Comma",
+        [KEY_DOT] = "Dot",                      [KEY_SLASH] = "Slash",
+        [KEY_RIGHTSHIFT] = "RightShift",        [KEY_KPASTERISK] = "KPAsterisk",
+        [KEY_LEFTALT] = "LeftAlt",              [KEY_SPACE] = "Space",
+        [KEY_CAPSLOCK] = "CapsLock",            [KEY_F1] = "F1",
+        [KEY_F2] = "F2",                        [KEY_F3] = "F3",
+        [KEY_F4] = "F4",                        [KEY_F5] = "F5",
+        [KEY_F6] = "F6",                        [KEY_F7] = "F7",
+        [KEY_F8] = "F8",                        [KEY_F9] = "F9",
+        [KEY_F10] = "F10",                      [KEY_NUMLOCK] = "NumLock",
+        [KEY_SCROLLLOCK] = "ScrollLock",        [KEY_KP7] = "KP7",
+        [KEY_KP8] = "KP8",                      [KEY_KP9] = "KP9",
+        [KEY_KPMINUS] = "KPMinus",              [KEY_KP4] = "KP4",
+        [KEY_KP5] = "KP5",                      [KEY_KP6] = "KP6",
+        [KEY_KPPLUS] = "KPPlus",                [KEY_KP1] = "KP1",
+        [KEY_KP2] = "KP2",                      [KEY_KP3] = "KP3",
+        [KEY_KP0] = "KP0",                      [KEY_KPDOT] = "KPDot",
+        [KEY_ZENKAKUHANKAKU] = "Zenkaku/Hankaku", [KEY_102ND] = "102nd",
+        [KEY_F11] = "F11",                      [KEY_F12] = "F12",
+        [KEY_RO] = "RO",                        [KEY_KATAKANA] = "Katakana",
+        [KEY_HIRAGANA] = "HIRAGANA",            [KEY_HENKAN] = "Henkan",
+        [KEY_KATAKANAHIRAGANA] = "Katakana/Hiragana", [KEY_MUHENKAN] = "Muhenkan",
+        [KEY_KPJPCOMMA] = "KPJpComma",          [KEY_KPENTER] = "KPEnter",
+        [KEY_RIGHTCTRL] = "RightCtrl",          [KEY_KPSLASH] = "KPSlash",
+        [KEY_SYSRQ] = "SysRq",                  [KEY_RIGHTALT] = "RightAlt",
+        [KEY_LINEFEED] = "LineFeed",            [KEY_HOME] = "Home",
+        [KEY_UP] = "Up",                        [KEY_PAGEUP] = "PageUp",
+        [KEY_LEFT] = "Left",                    [KEY_RIGHT] = "Right",
+        [KEY_END] = "End",                      [KEY_DOWN] = "Down",
+        [KEY_PAGEDOWN] = "PageDown",            [KEY_INSERT] = "Insert",
+        [KEY_DELETE] = "Delete",                [KEY_MACRO] = "Macro",
+        [KEY_MUTE] = "Mute",                    [KEY_VOLUMEDOWN] = "VolumeDown",
+        [KEY_VOLUMEUP] = "VolumeUp",            [KEY_POWER] = "Power",
+        [KEY_KPEQUAL] = "KPEqual",              [KEY_KPPLUSMINUS] = "KPPlusMinus",
+        [KEY_PAUSE] = "Pause",                  [KEY_KPCOMMA] = "KPComma",
+        [KEY_HANGUEL] = "Hangeul",              [KEY_HANJA] = "Hanja",
+        [KEY_YEN] = "Yen",                      [KEY_LEFTMETA] = "LeftMeta",
+        [KEY_RIGHTMETA] = "RightMeta",          [KEY_COMPOSE] = "Compose",
+        [KEY_STOP] = "Stop",                    [KEY_AGAIN] = "Again",
+        [KEY_PROPS] = "Props",                  [KEY_UNDO] = "Undo",
+        [KEY_FRONT] = "Front",                  [KEY_COPY] = "Copy",
+        [KEY_OPEN] = "Open",                    [KEY_PASTE] = "Paste",
+        [KEY_FIND] = "Find",                    [KEY_CUT] = "Cut",
+        [KEY_HELP] = "Help",                    [KEY_MENU] = "Menu",
+        [KEY_CALC] = "Calc",                    [KEY_SETUP] = "Setup",
+        [KEY_SLEEP] = "Sleep",                  [KEY_WAKEUP] = "WakeUp",
+        [KEY_FILE] = "File",                    [KEY_SENDFILE] = "SendFile",
+        [KEY_DELETEFILE] = "DeleteFile",        [KEY_XFER] = "X-fer",
+        [KEY_PROG1] = "Prog1",                  [KEY_PROG2] = "Prog2",
+        [KEY_WWW] = "WWW",                      [KEY_MSDOS] = "MSDOS",
+        [KEY_COFFEE] = "Coffee",                [KEY_DIRECTION] = "Direction",
+        [KEY_CYCLEWINDOWS] = "CycleWindows",    [KEY_MAIL] = "Mail",
+        [KEY_BOOKMARKS] = "Bookmarks",          [KEY_COMPUTER] = "Computer",
+        [KEY_BACK] = "Back",                    [KEY_FORWARD] = "Forward",
+        [KEY_CLOSECD] = "CloseCD",              [KEY_EJECTCD] = "EjectCD",
+        [KEY_EJECTCLOSECD] = "EjectCloseCD",    [KEY_NEXTSONG] = "NextSong",
+        [KEY_PLAYPAUSE] = "PlayPause",          [KEY_PREVIOUSSONG] = "PreviousSong",
+        [KEY_STOPCD] = "StopCD",                [KEY_RECORD] = "Record",
+        [KEY_REWIND] = "Rewind",                [KEY_PHONE] = "Phone",
+        [KEY_ISO] = "ISOKey",                   [KEY_CONFIG] = "Config",
+        [KEY_HOMEPAGE] = "HomePage",            [KEY_REFRESH] = "Refresh",
+        [KEY_EXIT] = "Exit",                    [KEY_MOVE] = "Move",
+        [KEY_EDIT] = "Edit",                    [KEY_SCROLLUP] = "ScrollUp",
+        [KEY_SCROLLDOWN] = "ScrollDown",        [KEY_KPLEFTPAREN] = "KPLeftParenthesis",
+        [KEY_KPRIGHTPAREN] = "KPRightParenthesis", [KEY_NEW] = "New",
+        [KEY_REDO] = "Redo",                    [KEY_F13] = "F13",
+        [KEY_F14] = "F14",                      [KEY_F15] = "F15",
+        [KEY_F16] = "F16",                      [KEY_F17] = "F17",
+        [KEY_F18] = "F18",                      [KEY_F19] = "F19",
+        [KEY_F20] = "F20",                      [KEY_F21] = "F21",
+        [KEY_F22] = "F22",                      [KEY_F23] = "F23",
+        [KEY_F24] = "F24",                      [KEY_PLAYCD] = "PlayCD",
+        [KEY_PAUSECD] = "PauseCD",              [KEY_PROG3] = "Prog3",
+        [KEY_PROG4] = "Prog4",                  [KEY_SUSPEND] = "Suspend",
+        [KEY_CLOSE] = "Close",                  [KEY_PLAY] = "Play",
+        [KEY_FASTFORWARD] = "FastForward",      [KEY_BASSBOOST] = "BassBoost",
+        [KEY_PRINT] = "Print",                  [KEY_HP] = "HP",
+        [KEY_CAMERA] = "Camera",                [KEY_SOUND] = "Sound",
+        [KEY_QUESTION] = "Question",            [KEY_EMAIL] = "Email",
+        [KEY_CHAT] = "Chat",                    [KEY_SEARCH] = "Search",
+        [KEY_CONNECT] = "Connect",              [KEY_FINANCE] = "Finance",
+        [KEY_SPORT] = "Sport",                  [KEY_SHOP] = "Shop",
+        [KEY_ALTERASE] = "AlternateErase",      [KEY_CANCEL] = "Cancel",
+        [KEY_BRIGHTNESSDOWN] = "BrightnessDown", [KEY_BRIGHTNESSUP] = "BrightnessUp",
+        [KEY_MEDIA] = "Media",                  [KEY_UNKNOWN] = "Unknown",
+        [BTN_0] = "Btn0",                       [BTN_1] = "Btn1",
+        [BTN_2] = "Btn2",                       [BTN_3] = "Btn3",
+        [BTN_4] = "Btn4",                       [BTN_5] = "Btn5",
+        [BTN_6] = "Btn6",                       [BTN_7] = "Btn7",
+        [BTN_8] = "Btn8",                       [BTN_9] = "Btn9",
+        [BTN_LEFT] = "LeftBtn",                 [BTN_RIGHT] = "RightBtn",
+        [BTN_MIDDLE] = "MiddleBtn",             [BTN_SIDE] = "SideBtn",
+        [BTN_EXTRA] = "ExtraBtn",               [BTN_FORWARD] = "ForwardBtn",
+        [BTN_BACK] = "BackBtn",                 [BTN_TASK] = "TaskBtn",
+        [BTN_TRIGGER] = "Trigger",              [BTN_THUMB] = "ThumbBtn",
+        [BTN_THUMB2] = "ThumbBtn2",             [BTN_TOP] = "TopBtn",
+        [BTN_TOP2] = "TopBtn2",                 [BTN_PINKIE] = "PinkieBtn",
+        [BTN_BASE] = "BaseBtn",                 [BTN_BASE2] = "BaseBtn2",
+        [BTN_BASE3] = "BaseBtn3",               [BTN_BASE4] = "BaseBtn4",
+        [BTN_BASE5] = "BaseBtn5",               [BTN_BASE6] = "BaseBtn6",
+        [BTN_DEAD] = "BtnDead",                 [BTN_A] = "BtnA",
+        [BTN_B] = "BtnB",                       [BTN_C] = "BtnC",
+        [BTN_X] = "BtnX",                       [BTN_Y] = "BtnY",
+        [BTN_Z] = "BtnZ",                       [BTN_TL] = "BtnTL",
+        [BTN_TR] = "BtnTR",                     [BTN_TL2] = "BtnTL2",
+        [BTN_TR2] = "BtnTR2",                   [BTN_SELECT] = "BtnSelect",
+        [BTN_START] = "BtnStart",               [BTN_MODE] = "BtnMode",
+        [BTN_THUMBL] = "BtnThumbL",             [BTN_THUMBR] = "BtnThumbR",
+        [BTN_TOOL_PEN] = "ToolPen",             [BTN_TOOL_RUBBER] = "ToolRubber",
+        [BTN_TOOL_BRUSH] = "ToolBrush",         [BTN_TOOL_PENCIL] = "ToolPencil",
+        [BTN_TOOL_AIRBRUSH] = "ToolAirbrush",   [BTN_TOOL_FINGER] = "ToolFinger",
+        [BTN_TOOL_MOUSE] = "ToolMouse",         [BTN_TOOL_LENS] = "ToolLens",
+        [BTN_TOUCH] = "Touch",                  [BTN_STYLUS] = "Stylus",
+        [BTN_STYLUS2] = "Stylus2",              [BTN_TOOL_DOUBLETAP] = "ToolDoubleTap",
+        [BTN_TOOL_TRIPLETAP] = "ToolTripleTap", [BTN_GEAR_DOWN] = "WheelBtn",
+        [BTN_GEAR_UP] = "Gear up",              [KEY_OK] = "Ok",
+        [KEY_SELECT] = "Select",                [KEY_GOTO] = "Goto",
+        [KEY_CLEAR] = "Clear",                  [KEY_POWER2] = "Power2",
+        [KEY_OPTION] = "Option",                [KEY_INFO] = "Info",
+        [KEY_TIME] = "Time",                    [KEY_VENDOR] = "Vendor",
+        [KEY_ARCHIVE] = "Archive",              [KEY_PROGRAM] = "Program",
+        [KEY_CHANNEL] = "Channel",              [KEY_FAVORITES] = "Favorites",
+        [KEY_EPG] = "EPG",                      [KEY_PVR] = "PVR",
+        [KEY_MHP] = "MHP",                      [KEY_LANGUAGE] = "Language",
+        [KEY_TITLE] = "Title",                  [KEY_SUBTITLE] = "Subtitle",
+        [KEY_ANGLE] = "Angle",                  [KEY_ZOOM] = "Zoom",
+        [KEY_MODE] = "Mode",                    [KEY_KEYBOARD] = "Keyboard",
+        [KEY_SCREEN] = "Screen",                [KEY_PC] = "PC",
+        [KEY_TV] = "TV",                        [KEY_TV2] = "TV2",
+        [KEY_VCR] = "VCR",                      [KEY_VCR2] = "VCR2",
+        [KEY_SAT] = "Sat",                      [KEY_SAT2] = "Sat2",
+        [KEY_CD] = "CD",                        [KEY_TAPE] = "Tape",
+        [KEY_RADIO] = "Radio",                  [KEY_TUNER] = "Tuner",
+        [KEY_PLAYER] = "Player",                [KEY_TEXT] = "Text",
+        [KEY_DVD] = "DVD",                      [KEY_AUX] = "Aux",
+        [KEY_MP3] = "MP3",                      [KEY_AUDIO] = "Audio",
+        [KEY_VIDEO] = "Video",                  [KEY_DIRECTORY] = "Directory",
+        [KEY_LIST] = "List",                    [KEY_MEMO] = "Memo",
+        [KEY_CALENDAR] = "Calendar",            [KEY_RED] = "Red",
+        [KEY_GREEN] = "Green",                  [KEY_YELLOW] = "Yellow",
+        [KEY_BLUE] = "Blue",                    [KEY_CHANNELUP] = "ChannelUp",
+        [KEY_CHANNELDOWN] = "ChannelDown",      [KEY_FIRST] = "First",
+        [KEY_LAST] = "Last",                    [KEY_AB] = "AB",
+        [KEY_NEXT] = "Next",                    [KEY_RESTART] = "Restart",
+        [KEY_SLOW] = "Slow",                    [KEY_SHUFFLE] = "Shuffle",
+        [KEY_BREAK] = "Break",                  [KEY_PREVIOUS] = "Previous",
+        [KEY_DIGITS] = "Digits",                [KEY_TEEN] = "TEEN",
+        [KEY_TWEN] = "TWEN",                    [KEY_DEL_EOL] = "DeleteEOL",
+        [KEY_DEL_EOS] = "DeleteEOS",            [KEY_INS_LINE] = "InsertLine",
+        [KEY_DEL_LINE] = "DeleteLine",
+        [KEY_SEND] = "Send",                    [KEY_REPLY] = "Reply",
+        [KEY_FORWARDMAIL] = "ForwardMail",      [KEY_SAVE] = "Save",
+        [KEY_DOCUMENTS] = "Documents",
+        [KEY_FN] = "Fn",                        [KEY_FN_ESC] = "Fn+ESC",
+        [KEY_FN_1] = "Fn+1",                    [KEY_FN_2] = "Fn+2",
+        [KEY_FN_B] = "Fn+B",                    [KEY_FN_D] = "Fn+D",
+        [KEY_FN_E] = "Fn+E",                    [KEY_FN_F] = "Fn+F",
+        [KEY_FN_S] = "Fn+S",
+        [KEY_FN_F1] = "Fn+F1",                  [KEY_FN_F2] = "Fn+F2",
+        [KEY_FN_F3] = "Fn+F3",                  [KEY_FN_F4] = "Fn+F4",
+        [KEY_FN_F5] = "Fn+F5",                  [KEY_FN_F6] = "Fn+F6",
+        [KEY_FN_F7] = "Fn+F7",                  [KEY_FN_F8] = "Fn+F8",
+        [KEY_FN_F9] = "Fn+F9",                  [KEY_FN_F10] = "Fn+F10",
+        [KEY_FN_F11] = "Fn+F11",                [KEY_FN_F12] = "Fn+F12",
+        [KEY_KBDILLUMTOGGLE] = "KbdIlluminationToggle",
+        [KEY_KBDILLUMDOWN] = "KbdIlluminationDown",
+        [KEY_KBDILLUMUP] = "KbdIlluminationUp",
+        [KEY_SWITCHVIDEOMODE] = "SwitchVideoMode",
+};
+
+static char *relatives[REL_MAX + 1] = {
+        [REL_X] = "X",                  [REL_Y] = "Y",
+        [REL_Z] = "Z",                  [REL_HWHEEL] = "HWheel",
+        [REL_DIAL] = "Dial",            [REL_WHEEL] = "Wheel",
+        [REL_MISC] = "Misc",
+};
+
+static char *absolutes[ABS_MAX + 1] = {
+        [ABS_X] = "X",                  [ABS_Y] = "Y",
+        [ABS_Z] = "Z",                  [ABS_RX] = "Rx",
+        [ABS_RY] = "Ry",                [ABS_RZ] = "Rz",
+        [ABS_THROTTLE] = "Throttle",    [ABS_RUDDER] = "Rudder",
+        [ABS_WHEEL] = "Wheel",          [ABS_GAS] = "Gas",
+        [ABS_BRAKE] = "Brake",          [ABS_HAT0X] = "Hat0X",
+        [ABS_HAT0Y] = "Hat0Y",          [ABS_HAT1X] = "Hat1X",
+        [ABS_HAT1Y] = "Hat1Y",          [ABS_HAT2X] = "Hat2X",
+        [ABS_HAT2Y] = "Hat2Y",          [ABS_HAT3X] = "Hat3X",
+        [ABS_HAT3Y] = "Hat 3Y",         [ABS_PRESSURE] = "Pressure",
+        [ABS_DISTANCE] = "Distance",    [ABS_TILT_X] = "XTilt",
+        [ABS_TILT_Y] = "YTilt",         [ABS_TOOL_WIDTH] = "Tool Width",
+        [ABS_VOLUME] = "Volume",        [ABS_MISC] = "Misc",
+};
+
+static char *misc[MSC_MAX + 1] = {
+        [MSC_SERIAL] = "Serial",        [MSC_PULSELED] = "Pulseled",
+        [MSC_GESTURE] = "Gesture",      [MSC_RAW] = "RawData"
+};
+
+static char *leds[LED_MAX + 1] = {
+        [LED_NUML] = "NumLock",         [LED_CAPSL] = "CapsLock",
+        [LED_SCROLLL] = "ScrollLock",   [LED_COMPOSE] = "Compose",
+        [LED_KANA] = "Kana",            [LED_SLEEP] = "Sleep",
+        [LED_SUSPEND] = "Suspend",      [LED_MUTE] = "Mute",
+        [LED_MISC] = "Misc",
+};
+
+static char *repeats[REP_MAX + 1] = {
+        [REP_DELAY] = "Delay",          [REP_PERIOD] = "Period"
+};
+
+static char *sounds[SND_MAX + 1] = {
+        [SND_CLICK] = "Click",          [SND_BELL] = "Bell",
+        [SND_TONE] = "Tone"
+};
+
+static char **names[EV_MAX + 1] = {
+        [EV_SYN] = syncs,                       [EV_KEY] = keys,
+        [EV_REL] = relatives,                   [EV_ABS] = absolutes,
+        [EV_MSC] = misc,                        [EV_LED] = leds,
+        [EV_SND] = sounds,                      [EV_REP] = repeats,
+};
+
+static void __attribute__((unused)) resolv_event(__u8 type, __u16 code) {
+
+        printk("%s.%s", events[type] ? events[type] : "?",
+                names[type] ? (names[type][code] ? names[type][code] : "?") : "?");
+}
diff --git a/include/linux/hid.h b/include/linux/hid.h
new file mode 100644
index 000000000000..770120add15a
--- /dev/null
+++ b/include/linux/hid.h
@@ -0,0 +1,528 @@
+#ifndef __HID_H
+#define __HID_H
+
+/*
+ * $Id: hid.h,v 1.24 2001/12/27 10:37:41 vojtech Exp $
+ *
+ *  Copyright (c) 1999 Andreas Gal
+ *  Copyright (c) 2000-2001 Vojtech Pavlik
+ *  Copyright (c) 2006 Jiri Kosina
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Should you need to contact me, the author, you can do so either by
+ * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
+ * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+#include <linux/input.h>
+
+/*
+ * USB HID (Human Interface Device) interface class code
+ */
+
+#define USB_INTERFACE_CLASS_HID         3
+
+/*
+ * USB HID interface subclass and protocol codes
+ */
+
+#define USB_INTERFACE_SUBCLASS_BOOT     1
+#define USB_INTERFACE_PROTOCOL_KEYBOARD 1
+#define USB_INTERFACE_PROTOCOL_MOUSE    2
+
+/*
+ * HID class requests
+ */
+
+#define HID_REQ_GET_REPORT              0x01
+#define HID_REQ_GET_IDLE                0x02
+#define HID_REQ_GET_PROTOCOL            0x03
+#define HID_REQ_SET_REPORT              0x09
+#define HID_REQ_SET_IDLE                0x0A
+#define HID_REQ_SET_PROTOCOL            0x0B
+
+/*
+ * HID class descriptor types
+ */
+
+#define HID_DT_HID                      (USB_TYPE_CLASS | 0x01)
+#define HID_DT_REPORT                   (USB_TYPE_CLASS | 0x02)
+#define HID_DT_PHYSICAL                 (USB_TYPE_CLASS | 0x03)
+
+/*
+ * We parse each description item into this structure. Short items data
+ * values are expanded to 32-bit signed int, long items contain a pointer
+ * into the data area.
+ */
+
+struct hid_item {
+        unsigned  format;
+        __u8      size;
+        __u8      type;
+        __u8      tag;
+        union {
+            __u8   u8;
+            __s8   s8;
+            __u16  u16;
+            __s16  s16;
+            __u32  u32;
+            __s32  s32;
+            __u8  *longdata;
+        } data;
+};
+
+/*
+ * HID report item format
+ */
+
+#define HID_ITEM_FORMAT_SHORT   0
+#define HID_ITEM_FORMAT_LONG    1
+
+/*
+ * Special tag indicating long items
+ */
+
+#define HID_ITEM_TAG_LONG       15
+
+/*
+ * HID report descriptor item type (prefix bit 2,3)
+ */
+
+#define HID_ITEM_TYPE_MAIN              0
+#define HID_ITEM_TYPE_GLOBAL            1
+#define HID_ITEM_TYPE_LOCAL             2
+#define HID_ITEM_TYPE_RESERVED          3
+
+/*
+ * HID report descriptor main item tags
+ */
+
+#define HID_MAIN_ITEM_TAG_INPUT                 8
+#define HID_MAIN_ITEM_TAG_OUTPUT                9
+#define HID_MAIN_ITEM_TAG_FEATURE               11
+#define HID_MAIN_ITEM_TAG_BEGIN_COLLECTION      10
+#define HID_MAIN_ITEM_TAG_END_COLLECTION        12
+
+/*
+ * HID report descriptor main item contents
+ */
+
+#define HID_MAIN_ITEM_CONSTANT          0x001
+#define HID_MAIN_ITEM_VARIABLE          0x002
+#define HID_MAIN_ITEM_RELATIVE          0x004
+#define HID_MAIN_ITEM_WRAP              0x008
+#define HID_MAIN_ITEM_NONLINEAR         0x010
+#define HID_MAIN_ITEM_NO_PREFERRED      0x020
+#define HID_MAIN_ITEM_NULL_STATE        0x040
+#define HID_MAIN_ITEM_VOLATILE          0x080
+#define HID_MAIN_ITEM_BUFFERED_BYTE     0x100
+
+/*
+ * HID report descriptor collection item types
+ */
+
+#define HID_COLLECTION_PHYSICAL         0
+#define HID_COLLECTION_APPLICATION      1
+#define HID_COLLECTION_LOGICAL          2
+
+/*
+ * HID report descriptor global item tags
+ */
+
+#define HID_GLOBAL_ITEM_TAG_USAGE_PAGE          0
+#define HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM     1
+#define HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM     2
+#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM    3
+#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM    4
+#define HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT       5
+#define HID_GLOBAL_ITEM_TAG_UNIT                6
+#define HID_GLOBAL_ITEM_TAG_REPORT_SIZE         7
+#define HID_GLOBAL_ITEM_TAG_REPORT_ID           8
+#define HID_GLOBAL_ITEM_TAG_REPORT_COUNT        9
+#define HID_GLOBAL_ITEM_TAG_PUSH                10
+#define HID_GLOBAL_ITEM_TAG_POP                 11
+
+/*
+ * HID report descriptor local item tags
+ */
+
+#define HID_LOCAL_ITEM_TAG_USAGE                0
+#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM        1
+#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM        2
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX     3
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM   4
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM   5
+#define HID_LOCAL_ITEM_TAG_STRING_INDEX         7
+#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM       8
+#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM       9
+#define HID_LOCAL_ITEM_TAG_DELIMITER            10
+
+/*
+ * HID usage tables
+ */
+
+#define HID_USAGE_PAGE          0xffff0000
+
+#define HID_UP_UNDEFINED        0x00000000
+#define HID_UP_GENDESK          0x00010000
+#define HID_UP_SIMULATION       0x00020000
+#define HID_UP_KEYBOARD         0x00070000
+#define HID_UP_LED              0x00080000
+#define HID_UP_BUTTON           0x00090000
+#define HID_UP_ORDINAL          0x000a0000
+#define HID_UP_CONSUMER         0x000c0000
+#define HID_UP_DIGITIZER        0x000d0000
+#define HID_UP_PID              0x000f0000
+#define HID_UP_HPVENDOR         0xff7f0000
+#define HID_UP_MSVENDOR         0xff000000
+#define HID_UP_CUSTOM           0x00ff0000
+#define HID_UP_LOGIVENDOR       0xffbc0000
+
+#define HID_USAGE               0x0000ffff
+
+#define HID_GD_POINTER          0x00010001
+#define HID_GD_MOUSE            0x00010002
+#define HID_GD_JOYSTICK         0x00010004
+#define HID_GD_GAMEPAD          0x00010005
+#define HID_GD_KEYBOARD         0x00010006
+#define HID_GD_KEYPAD           0x00010007
+#define HID_GD_MULTIAXIS        0x00010008
+#define HID_GD_X                0x00010030
+#define HID_GD_Y                0x00010031
+#define HID_GD_Z                0x00010032
+#define HID_GD_RX               0x00010033
+#define HID_GD_RY               0x00010034
+#define HID_GD_RZ               0x00010035
+#define HID_GD_SLIDER           0x00010036
+#define HID_GD_DIAL             0x00010037
+#define HID_GD_WHEEL            0x00010038
+#define HID_GD_HATSWITCH        0x00010039
+#define HID_GD_BUFFER           0x0001003a
+#define HID_GD_BYTECOUNT        0x0001003b
+#define HID_GD_MOTION           0x0001003c
+#define HID_GD_START            0x0001003d
+#define HID_GD_SELECT           0x0001003e
+#define HID_GD_VX               0x00010040
+#define HID_GD_VY               0x00010041
+#define HID_GD_VZ               0x00010042
+#define HID_GD_VBRX             0x00010043
+#define HID_GD_VBRY             0x00010044
+#define HID_GD_VBRZ             0x00010045
+#define HID_GD_VNO              0x00010046
+#define HID_GD_FEATURE          0x00010047
+#define HID_GD_UP               0x00010090
+#define HID_GD_DOWN             0x00010091
+#define HID_GD_RIGHT            0x00010092
+#define HID_GD_LEFT             0x00010093
+
+/*
+ * HID report types --- Ouch! HID spec says 1 2 3!
+ */
+
+#define HID_INPUT_REPORT        0
+#define HID_OUTPUT_REPORT       1
+#define HID_FEATURE_REPORT      2
+
+/*
+ * HID device quirks.
+ */
+
+#define HID_QUIRK_INVERT                        0x00000001
+#define HID_QUIRK_NOTOUCH                       0x00000002
+#define HID_QUIRK_IGNORE                        0x00000004
+#define HID_QUIRK_NOGET                         0x00000008
+#define HID_QUIRK_HIDDEV                        0x00000010
+#define HID_QUIRK_BADPAD                        0x00000020
+#define HID_QUIRK_MULTI_INPUT                   0x00000040
+#define HID_QUIRK_2WHEEL_MOUSE_HACK_7           0x00000080
+#define HID_QUIRK_2WHEEL_MOUSE_HACK_5           0x00000100
+#define HID_QUIRK_2WHEEL_MOUSE_HACK_ON          0x00000200
+#define HID_QUIRK_MIGHTYMOUSE                   0x00000400
+#define HID_QUIRK_CYMOTION                      0x00000800
+#define HID_QUIRK_POWERBOOK_HAS_FN              0x00001000
+#define HID_QUIRK_POWERBOOK_FN_ON               0x00002000
+#define HID_QUIRK_INVERT_HWHEEL                 0x00004000
+#define HID_QUIRK_POWERBOOK_ISO_KEYBOARD        0x00008000
+#define HID_QUIRK_BAD_RELATIVE_KEYS             0x00010000
+
+/*
+ * This is the global environment of the parser. This information is
+ * persistent for main-items. The global environment can be saved and
+ * restored with PUSH/POP statements.
+ */
+
+struct hid_global {
+        unsigned usage_page;
+        __s32    logical_minimum;
+        __s32    logical_maximum;
+        __s32    physical_minimum;
+        __s32    physical_maximum;
+        __s32    unit_exponent;
+        unsigned unit;
+        unsigned report_id;
+        unsigned report_size;
+        unsigned report_count;
+};
+
+/*
+ * This is the local environment. It is persistent up the next main-item.
+ */
+
+#define HID_MAX_DESCRIPTOR_SIZE         4096
+#define HID_MAX_USAGES                  1024
+#define HID_DEFAULT_NUM_COLLECTIONS     16
+
+struct hid_local {
+        unsigned usage[HID_MAX_USAGES]; /* usage array */
+        unsigned collection_index[HID_MAX_USAGES]; /* collection index array */
+        unsigned usage_index;
+        unsigned usage_minimum;
+        unsigned delimiter_depth;
+        unsigned delimiter_branch;
+};
+
+/*
+ * This is the collection stack. We climb up the stack to determine
+ * application and function of each field.
+ */
+
+struct hid_collection {
+        unsigned type;
+        unsigned usage;
+        unsigned level;
+};
+
+struct hid_usage {
+        unsigned  hid;                  /* hid usage code */
+        unsigned  collection_index;     /* index into collection array */
+        /* hidinput data */
+        __u16     code;                 /* input driver code */
+        __u8      type;                 /* input driver type */
+        __s8      hat_min;              /* hat switch fun */
+        __s8      hat_max;              /* ditto */
+        __s8      hat_dir;              /* ditto */
+};
+
+struct hid_input;
+
+struct hid_field {
+        unsigned  physical;             /* physical usage for this field */
+        unsigned  logical;              /* logical usage for this field */
+        unsigned  application;          /* application usage for this field */
+        struct hid_usage *usage;        /* usage table for this function */
+        unsigned  maxusage;             /* maximum usage index */
+        unsigned  flags;                /* main-item flags (i.e. volatile,array,constant) */
+        unsigned  report_offset;        /* bit offset in the report */
+        unsigned  report_size;          /* size of this field in the report */
+        unsigned  report_count;         /* number of this field in the report */
+        unsigned  report_type;          /* (input,output,feature) */
+        __s32    *value;                /* last known value(s) */
+        __s32     logical_minimum;
+        __s32     logical_maximum;
+        __s32     physical_minimum;
+        __s32     physical_maximum;
+        __s32     unit_exponent;
+        unsigned  unit;
+        struct hid_report *report;      /* associated report */
+        unsigned index;                 /* index into report->field[] */
+        /* hidinput data */
+        struct hid_input *hidinput;     /* associated input structure */
+        __u16 dpad;                     /* dpad input code */
+};
+
+#define HID_MAX_FIELDS 64
+
+struct hid_report {
+        struct list_head list;
+        unsigned id;                                    /* id of this report */
+        unsigned type;                                  /* report type */
+        struct hid_field *field[HID_MAX_FIELDS];        /* fields of the report */
+        unsigned maxfield;                              /* maximum valid field index */
+        unsigned size;                                  /* size of the report (bits) */
+        struct hid_device *device;                      /* associated device */
+};
+
+struct hid_report_enum {
+        unsigned numbered;
+        struct list_head report_list;
+        struct hid_report *report_id_hash[256];
+};
+
+#define HID_REPORT_TYPES 3
+
+#define HID_MIN_BUFFER_SIZE     64              /* make sure there is at least a packet size of space */
+#define HID_MAX_BUFFER_SIZE     4096            /* 4kb */
+#define HID_CONTROL_FIFO_SIZE   256             /* to init devices with >100 reports */
+#define HID_OUTPUT_FIFO_SIZE    64
+
+struct hid_control_fifo {
+        unsigned char dir;
+        struct hid_report *report;
+};
+
+#define HID_CLAIMED_INPUT       1
+#define HID_CLAIMED_HIDDEV      2
+
+#define HID_CTRL_RUNNING        1
+#define HID_OUT_RUNNING         2
+#define HID_IN_RUNNING          3
+#define HID_RESET_PENDING       4
+#define HID_SUSPENDED           5
+#define HID_CLEAR_HALT          6
+
+struct hid_input {
+        struct list_head list;
+        struct hid_report *report;
+        struct input_dev *input;
+};
+
+struct hid_device {                                                     /* device report descriptor */
+         __u8 *rdesc;
+        unsigned rsize;
+        struct hid_collection *collection;                              /* List of HID collections */
+        unsigned collection_size;                                       /* Number of allocated hid_collections */
+        unsigned maxcollection;                                         /* Number of parsed collections */
+        unsigned maxapplication;                                        /* Number of applications */
+        unsigned short bus;                                             /* BUS ID */
+        unsigned short vendor;                                          /* Vendor ID */
+        unsigned short product;                                         /* Product ID */
+        unsigned version;                                               /* HID version */
+        unsigned country;                                               /* HID country */
+        struct hid_report_enum report_enum[HID_REPORT_TYPES];
+
+        struct device *dev;                                             /* device */
+
+        unsigned claimed;                                               /* Claimed by hidinput, hiddev? */
+        unsigned quirks;                                                /* Various quirks the device can pull on us */
+
+        struct list_head inputs;                                        /* The list of inputs */
+        void *hiddev;                                                   /* The hiddev structure */
+        int minor;                                                      /* Hiddev minor number */
+
+        wait_queue_head_t wait;                                         /* For sleeping */
+
+        int open;                                                       /* is the device open by anyone? */
+        char name[128];                                                 /* Device name */
+        char phys[64];                                                  /* Device physical location */
+        char uniq[64];                                                  /* Device unique identifier (serial #) */
+
+        void *driver_data;
+
+        /* device-specific function pointers */
+        int (*hidinput_input_event) (struct input_dev *, unsigned int, unsigned int, int);
+        int (*hidinput_open) (struct input_dev *);
+        void (*hidinput_close) (struct input_dev *);
+
+        /* hiddev event handler */
+        void (*hiddev_hid_event) (struct hid_device *, struct hid_field *field,
+                                  struct hid_usage *, __s32);
+        void (*hiddev_report_event) (struct hid_device *, struct hid_report *);
+#ifdef CONFIG_USB_HIDINPUT_POWERBOOK
+        unsigned int  pb_fnmode;
+        unsigned long pb_pressed_fn[NBITS(KEY_MAX)];
+        unsigned long pb_pressed_numlock[NBITS(KEY_MAX)];
+#endif
+};
+
+#define HID_GLOBAL_STACK_SIZE 4
+#define HID_COLLECTION_STACK_SIZE 4
+
+struct hid_parser {
+        struct hid_global     global;
+        struct hid_global     global_stack[HID_GLOBAL_STACK_SIZE];
+        unsigned              global_stack_ptr;
+        struct hid_local      local;
+        unsigned              collection_stack[HID_COLLECTION_STACK_SIZE];
+        unsigned              collection_stack_ptr;
+        struct hid_device    *device;
+};
+
+struct hid_class_descriptor {
+        __u8  bDescriptorType;
+        __u16 wDescriptorLength;
+} __attribute__ ((packed));
+
+struct hid_descriptor {
+        __u8  bLength;
+        __u8  bDescriptorType;
+        __u16 bcdHID;
+        __u8  bCountryCode;
+        __u8  bNumDescriptors;
+
+        struct hid_class_descriptor desc[1];
+} __attribute__ ((packed));
+
+#ifdef DEBUG
+#include "hid-debug.h"
+#else
+#define hid_dump_input(a,b)     do { } while (0)
+#define hid_dump_device(c)      do { } while (0)
+#define hid_dump_field(a,b)     do { } while (0)
+#define resolv_usage(a)         do { } while (0)
+#define resolv_event(a,b)       do { } while (0)
+#endif
+
+/* Applications from HID Usage Tables 4/8/99 Version 1.1 */
+/* We ignore a few input applications that are not widely used */
+#define IS_INPUT_APPLICATION(a) (((a >= 0x00010000) && (a <= 0x00010008)) || (a == 0x00010080) || (a == 0x000c0001))
+
+/* HID core API */
+extern void hidinput_hid_event(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);
+extern void hidinput_report_event(struct hid_device *hid, struct hid_report *report);
+extern int hidinput_connect(struct hid_device *);
+extern void hidinput_disconnect(struct hid_device *);
+
+int hid_set_field(struct hid_field *, unsigned, __s32);
+int hid_input_report(struct hid_device *, int type, u8 *, int, int);
+int hidinput_find_field(struct hid_device *hid, unsigned int type, unsigned int code, struct hid_field **field);
+void hid_input_field(struct hid_device *hid, struct hid_field *field, __u8 *data, int interrupt);
+void hid_output_report(struct hid_report *report, __u8 *data);
+void hid_free_device(struct hid_device *device);
+struct hid_device *hid_parse_report(__u8 *start, unsigned size);
+
+#ifdef CONFIG_HID_FF
+int hid_ff_init(struct hid_device *hid);
+
+int hid_lgff_init(struct hid_device *hid);
+int hid_tmff_init(struct hid_device *hid);
+int hid_zpff_init(struct hid_device *hid);
+#ifdef CONFIG_HID_PID
+int hid_pidff_init(struct hid_device *hid);
+#else
+static inline int hid_pidff_init(struct hid_device *hid) { return -ENODEV; }
+#endif
+
+#else
+static inline int hid_ff_init(struct hid_device *hid) { return -1; }
+#endif
+#ifdef DEBUG
+#define dbg(format, arg...) printk(KERN_DEBUG "%s: " format "\n" , \
+                __FILE__ , ## arg)
+#else
+#define dbg(format, arg...) do {} while (0)
+#endif
+
+#define err(format, arg...) printk(KERN_ERR "%s: " format "\n" , \
+                __FILE__ , ## arg)
+#endif
+
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index 0a8f750cbede..0f4cf34b6fa2 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -159,6 +159,7 @@
 #define I2C_DRIVERID_ASB100 1043
 #define I2C_DRIVERID_FSCHER 1046
 #define I2C_DRIVERID_W83L785TS 1047
+#define I2C_DRIVERID_OV7670 1048        /* Omnivision 7670 camera */
 
 /*
  * ---- Adapter types ----------------------------------------------------
@@ -250,6 +251,7 @@
 #define I2C_HW_SMBUS_OV518      0x04000f /* OV518(+) USB 1.1 webcam ICs */
 #define I2C_HW_SMBUS_OV519      0x040010 /* OV519 USB 1.1 webcam IC */
 #define I2C_HW_SMBUS_OVFX2      0x040011 /* Cypress/OmniVision FX2 webcam */
+#define I2C_HW_SMBUS_CAFE       0x040012 /* Marvell 88ALP01 "CAFE" cam  */
 
 /* --- ISA pseudo-adapter                                               */
 #define I2C_HW_ISA              0x050000
diff --git a/include/linux/i2c-pxa.h b/include/linux/i2c-pxa.h
index 5f3eaf802223..41dcdfe7f625 100644
--- a/include/linux/i2c-pxa.h
+++ b/include/linux/i2c-pxa.h
@@ -1,29 +1,6 @@
 #ifndef _LINUX_I2C_ALGO_PXA_H
 #define _LINUX_I2C_ALGO_PXA_H
 
-struct i2c_eeprom_emu_watcher {
-        void (*write)(void *, unsigned int addr, unsigned char newval);
-};
-
-struct i2c_eeprom_emu_watch {
-        struct list_head node;
-        unsigned int start;
-        unsigned int end;
-        struct i2c_eeprom_emu_watcher *ops;
-        void *data;
-};
-
-#define I2C_EEPROM_EMU_SIZE (256)
-
-struct i2c_eeprom_emu {
-        unsigned int size;
-        unsigned int ptr;
-        unsigned int seen_start;
-        struct list_head watch;
-
-        unsigned char bytes[I2C_EEPROM_EMU_SIZE];
-};
-
 typedef enum i2c_slave_event_e {
         I2C_SLAVE_EVENT_START_READ,
         I2C_SLAVE_EVENT_START_WRITE,
@@ -37,12 +14,4 @@ struct i2c_slave_client {
         void (*write)(void *ptr, unsigned int val);
 };
 
-extern int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *, void *data,
-                                     unsigned int addr, unsigned int size,
-                                     struct i2c_eeprom_emu_watcher *);
-
-extern void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *, void *data, struct i2c_eeprom_emu_watcher *watcher);
-
-extern struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void);
-
 #endif /* _LINUX_I2C_ALGO_PXA_H */
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 9c2050293f17..64e070f62a87 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -796,6 +796,7 @@ typedef struct hwif_s {
         unsigned        sg_mapped  : 1; /* sg_table and sg_nents are ready */
         unsigned        no_io_32bit : 1; /* 1 = can not do 32-bit IO ops */
         unsigned        err_stops_fifo : 1; /* 1=data FIFO is cleared by an error */
+        unsigned        atapi_irq_bogon : 1; /* Generates spurious DMA interrupts in PIO mode */
 
         struct device   gendev;
         struct completion gendev_rel_comp; /* To deal with device release() */
diff --git a/include/linux/if_addr.h b/include/linux/if_addr.h
index dbe8f6120a40..d557e4ce9b6b 100644
--- a/include/linux/if_addr.h
+++ b/include/linux/if_addr.h
@@ -52,4 +52,10 @@ struct ifa_cacheinfo
         __u32   tstamp; /* updated timestamp, hundredths of seconds */
 };
 
+/* backwards compatibility for userspace */
+#ifndef __KERNEL__
+#define IFA_RTA(r)  ((struct rtattr*)(((char*)(r)) + NLMSG_ALIGN(sizeof(struct ifaddrmsg))))
+#define IFA_PAYLOAD(n) NLMSG_PAYLOAD(n,sizeof(struct ifaddrmsg))
+#endif
+
 #endif
diff --git a/include/linux/if_link.h b/include/linux/if_link.h
index e963a077e6f5..35ed3b5467f3 100644
--- a/include/linux/if_link.h
+++ b/include/linux/if_link.h
@@ -82,6 +82,12 @@ enum
 
 #define IFLA_MAX (__IFLA_MAX - 1)
 
+/* backwards compatibility for userspace */
+#ifndef __KERNEL__
+#define IFLA_RTA(r)  ((struct rtattr*)(((char*)(r)) + NLMSG_ALIGN(sizeof(struct ifinfomsg))))
+#define IFLA_PAYLOAD(n) NLMSG_PAYLOAD(n,sizeof(struct ifinfomsg))
+#endif
+
 /* ifi_flags.
 
    IFF_* flags.
diff --git a/include/linux/init.h b/include/linux/init.h
index 5eb5d24b7680..5a593a1dec1e 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -111,6 +111,7 @@ extern void setup_arch(char **);
 #define subsys_initcall_sync(fn)        __define_initcall("4s",fn,4s)
 #define fs_initcall(fn)                 __define_initcall("5",fn,5)
 #define fs_initcall_sync(fn)            __define_initcall("5s",fn,5s)
+#define rootfs_initcall(fn)             __define_initcall("rootfs",fn,rootfs)
 #define device_initcall(fn)             __define_initcall("6",fn,6)
 #define device_initcall_sync(fn)        __define_initcall("6s",fn,6s)
 #define late_initcall(fn)               __define_initcall("7",fn,7)
diff --git a/include/linux/init_task.h b/include/linux/init_task.h
index 733790d4f7db..b5315150199e 100644
--- a/include/linux/init_task.h
+++ b/include/linux/init_task.h
@@ -7,16 +7,15 @@
 #include <linux/utsname.h>
 #include <linux/lockdep.h>
 #include <linux/ipc.h>
+#include <linux/pid_namespace.h>
 
 #define INIT_FDTABLE \
 {                                                       \
         .max_fds        = NR_OPEN_DEFAULT,              \
-        .max_fdset      = EMBEDDED_FD_SET_SIZE,         \
         .fd             = &init_files.fd_array[0],      \
         .close_on_exec  = (fd_set *)&init_files.close_on_exec_init, \
         .open_fds       = (fd_set *)&init_files.open_fds_init,  \
         .rcu            = RCU_HEAD_INIT,                \
-        .free_files     = NULL,                         \
         .next           = NULL,                         \
 }
 
@@ -57,25 +56,28 @@
         .cpu_vm_mask    = CPU_MASK_ALL,                         \
 }
 
-#define INIT_SIGNALS(sig) {     \
-        .count          = ATOMIC_INIT(1),               \
+#define INIT_SIGNALS(sig) {                                             \
+        .count          = ATOMIC_INIT(1),                               \
         .wait_chldexit  = __WAIT_QUEUE_HEAD_INITIALIZER(sig.wait_chldexit),\
-        .shared_pending = {                             \
+        .shared_pending = {                                             \
                 .list = LIST_HEAD_INIT(sig.shared_pending.list),        \
-                .signal =  {{0}}}, \
+                .signal =  {{0}}},                                      \
         .posix_timers    = LIST_HEAD_INIT(sig.posix_timers),            \
         .cpu_timers     = INIT_CPU_TIMERS(sig.cpu_timers),              \
         .rlim           = INIT_RLIMITS,                                 \
         .pgrp           = 1,                                            \
-        .session        = 1,                                            \
+        .tty_old_pgrp   = 0,                                            \
+        { .__session      = 1},                                         \
 }
 
 extern struct nsproxy init_nsproxy;
 #define INIT_NSPROXY(nsproxy) {                                         \
+        .pid_ns         = &init_pid_ns,                                 \
         .count          = ATOMIC_INIT(1),                               \
         .nslock         = __SPIN_LOCK_UNLOCKED(nsproxy.nslock),         \
+        .id             = 0,                                            \
         .uts_ns         = &init_uts_ns,                                 \
-        .namespace      = NULL,                                         \
+        .mnt_ns         = NULL,                                         \
         INIT_IPC_NS(ipc_ns)                                             \
 }
 
diff --git a/include/linux/input.h b/include/linux/input.h
index c38507ba38b5..4e61158b06a0 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -663,7 +663,7 @@ struct input_absinfo {
 #define BUS_GSC                 0x1A
 
 /*
- * Values describing the status of an effect
+ * Values describing the status of a force-feedback effect
  */
 #define FF_STATUS_STOPPED       0x00
 #define FF_STATUS_PLAYING       0x01
@@ -680,7 +680,7 @@ struct input_absinfo {
  */
 
 /**
- * struct ff_replay - defines scheduling of the effect
+ * struct ff_replay - defines scheduling of the force-feedback effect
  * @length: duration of the effect
  * @delay: delay before effect should start playing
  */
@@ -690,7 +690,7 @@ struct ff_replay {
 };
 
 /**
- * struct ff_trigger - defines what triggers the effect
+ * struct ff_trigger - defines what triggers the force-feedback effect
  * @button: number of the button triggering the effect
  * @interval: controls how soon the effect can be re-triggered
  */
@@ -700,7 +700,7 @@ struct ff_trigger {
 };
 
 /**
- * struct ff_envelope - generic effect envelope
+ * struct ff_envelope - generic force-feedback effect envelope
  * @attack_length: duration of the attack (ms)
  * @attack_level: level at the beginning of the attack
  * @fade_length: duration of fade (ms)
@@ -719,7 +719,7 @@ struct ff_envelope {
 };
 
 /**
- * struct ff_constant_effect - defines parameters of a constant effect
+ * struct ff_constant_effect - defines parameters of a constant force-feedback effect
  * @level: strength of the effect; may be negative
  * @envelope: envelope data
  */
@@ -729,7 +729,7 @@ struct ff_constant_effect {
 };
 
 /**
- * struct ff_ramp_effect - defines parameters of a ramp effect
+ * struct ff_ramp_effect - defines parameters of a ramp force-feedback effect
  * @start_level: beginning strength of the effect; may be negative
  * @end_level: final strength of the effect; may be negative
  * @envelope: envelope data
@@ -741,7 +741,7 @@ struct ff_ramp_effect {
 };
 
 /**
- * struct ff_condition_effect - defines a spring or friction effect
+ * struct ff_condition_effect - defines a spring or friction force-feedback effect
  * @right_saturation: maximum level when joystick moved all way to the right
  * @left_saturation: same for the left side
  * @right_coeff: controls how fast the force grows when the joystick moves
@@ -762,7 +762,7 @@ struct ff_condition_effect {
 };
 
 /**
- * struct ff_periodic_effect - defines parameters of a periodic effect
+ * struct ff_periodic_effect - defines parameters of a periodic force-feedback effect
  * @waveform: kind of the effect (wave)
  * @period: period of the wave (ms)
  * @magnitude: peak value
@@ -793,7 +793,7 @@ struct ff_periodic_effect {
 };
 
 /**
- * struct ff_rumble_effect - defines parameters of a periodic effect
+ * struct ff_rumble_effect - defines parameters of a periodic force-feedback effect
  * @strong_magnitude: magnitude of the heavy motor
  * @weak_magnitude: magnitude of the light one
  *
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index de7593f4e895..e36e86c869fb 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -231,7 +231,8 @@ enum
         NET_TX_SOFTIRQ,
         NET_RX_SOFTIRQ,
         BLOCK_SOFTIRQ,
-        TASKLET_SOFTIRQ
+        TASKLET_SOFTIRQ,
+        SCHED_SOFTIRQ,
 };
 
 /* softirq mask and active fields moved to irq_cpustat_t in
diff --git a/include/linux/isdn.h b/include/linux/isdn.h
index 62991148d5a5..3c7875b7ab5b 100644
--- a/include/linux/isdn.h
+++ b/include/linux/isdn.h
@@ -511,8 +511,8 @@ typedef struct modem_info {
 #endif
   struct tty_struct     *tty;            /* Pointer to corresponding tty   */
   atemu                 emu;             /* AT-emulator data               */
-  struct termios        normal_termios;  /* For saving termios structs     */
-  struct termios        callout_termios;
+  struct ktermios       normal_termios;  /* For saving termios structs     */
+  struct ktermios       callout_termios;
   wait_queue_head_t     open_wait, close_wait;
   struct semaphore      write_sem;
   spinlock_t            readlock;
@@ -525,8 +525,8 @@ typedef struct _isdn_modem {
   int                refcount;                          /* Number of opens        */
   struct tty_driver  *tty_modem;                        /* tty-device             */
   struct tty_struct  *modem_table[ISDN_MAX_CHANNELS];   /* ?? copied from Orig    */
-  struct termios     *modem_termios[ISDN_MAX_CHANNELS];
-  struct termios     *modem_termios_locked[ISDN_MAX_CHANNELS];
+  struct ktermios     *modem_termios[ISDN_MAX_CHANNELS];
+  struct ktermios     *modem_termios_locked[ISDN_MAX_CHANNELS];
   modem_info         info[ISDN_MAX_CHANNELS];      /* Private data           */
 } isdn_modem_t;
 
diff --git a/include/linux/istallion.h b/include/linux/istallion.h
index b55e2a035605..106a5e85e5c4 100644
--- a/include/linux/istallion.h
+++ b/include/linux/istallion.h
@@ -49,13 +49,13 @@
  *      communication with the slave board will always be on a per port
  *      basis.
  */
-typedef struct {
+struct stliport {
         unsigned long           magic;
-        int                     portnr;
-        int                     panelnr;
-        int                     brdnr;
+        unsigned int            portnr;
+        unsigned int            panelnr;
+        unsigned int            brdnr;
         unsigned long           state;
-        int                     devnr;
+        unsigned int            devnr;
         int                     flags;
         int                     baud_base;
         int                     custom_divisor;
@@ -72,7 +72,7 @@ typedef struct {
         wait_queue_head_t       close_wait;
         wait_queue_head_t       raw_wait;
         struct work_struct      tqhangup;
-        asysigs_t               asig;
+        struct asysigs          asig;
         unsigned long           addr;
         unsigned long           rxoffset;
         unsigned long           txoffset;
@@ -83,31 +83,31 @@ typedef struct {
         unsigned char           reqbit;
         unsigned char           portidx;
         unsigned char           portbit;
-} stliport_t;
+};
 
 /*
  *      Use a structure of function pointers to do board level operations.
  *      These include, enable/disable, paging shared memory, interrupting, etc.
  */
-typedef struct stlibrd {
+struct stlibrd {
         unsigned long   magic;
-        int             brdnr;
-        int             brdtype;
-        int             state;
-        int             nrpanels;
-        int             nrports;
-        int             nrdevs;
+        unsigned int    brdnr;
+        unsigned int    brdtype;
+        unsigned int    state;
+        unsigned int    nrpanels;
+        unsigned int    nrports;
+        unsigned int    nrdevs;
         unsigned int    iobase;
         int             iosize;
         unsigned long   memaddr;
         void            __iomem *membase;
-        int             memsize;
+        unsigned long   memsize;
         int             pagesize;
         int             hostoffset;
         int             slaveoffset;
         int             bitsize;
         int             enabval;
-        int             panels[STL_MAXPANELS];
+        unsigned int    panels[STL_MAXPANELS];
         int             panelids[STL_MAXPANELS];
         void            (*init)(struct stlibrd *brdp);
         void            (*enable)(struct stlibrd *brdp);
@@ -116,8 +116,8 @@ typedef struct stlibrd {
         void            __iomem *(*getmemptr)(struct stlibrd *brdp, unsigned long offset, int line);
         void            (*intr)(struct stlibrd *brdp);
         void            (*reset)(struct stlibrd *brdp);
-        stliport_t      *ports[STL_MAXPORTS];
-} stlibrd_t;
+        struct stliport *ports[STL_MAXPORTS];
+};
 
 
 /*
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 6738283ac385..b0c4a05a4b0c 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -13,11 +13,10 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 #include <linux/bitops.h>
+#include <linux/log2.h>
 #include <asm/byteorder.h>
 #include <asm/bug.h>
 
-extern const char linux_banner[];
-
 #define INT_MAX         ((int)(~0U>>1))
 #define INT_MIN         (-INT_MAX - 1)
 #define UINT_MAX        (~0U)
@@ -157,20 +156,6 @@ static inline int printk(const char *s, ...) { return 0; }
 
 unsigned long int_sqrt(unsigned long);
 
-static inline int __attribute_pure__ long_log2(unsigned long x)
-{
-        int r = 0;
-        for (x >>= 1; x > 0; x >>= 1)
-                r++;
-        return r;
-}
-
-static inline unsigned long
-__attribute_const__ roundup_pow_of_two(unsigned long x)
-{
-        return 1UL << fls_long(x - 1);
-}
-
 extern int printk_ratelimit(void);
 extern int __printk_ratelimit(int ratelimit_jiffies, int ratelimit_burst);
 extern bool printk_timed_ratelimit(unsigned long *caller_jiffies,
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index e3abcec6c51c..d02425cdd801 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -109,6 +109,10 @@ void crash_save_cpu(struct pt_regs *regs, int cpu);
 extern struct kimage *kexec_image;
 extern struct kimage *kexec_crash_image;
 
+#ifndef kexec_flush_icache_page
+#define kexec_flush_icache_page(page)
+#endif
+
 #define KEXEC_ON_CRASH  0x00000001
 #define KEXEC_ARCH_MASK 0xffff0000
 
@@ -134,6 +138,7 @@ extern struct resource crashk_res;
 typedef u32 note_buf_t[MAX_NOTE_BYTES/4];
 extern note_buf_t *crash_notes;
 
+
 #else /* !CONFIG_KEXEC */
 struct pt_regs;
 struct task_struct;
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
new file mode 100644
index 000000000000..5bb2c3c585c1
--- /dev/null
+++ b/include/linux/kvm.h
@@ -0,0 +1,227 @@
+#ifndef __LINUX_KVM_H
+#define __LINUX_KVM_H
+
+/*
+ * Userspace interface for /dev/kvm - kernel based virtual machine
+ *
+ * Note: this interface is considered experimental and may change without
+ *       notice.
+ */
+
+#include <asm/types.h>
+#include <linux/ioctl.h>
+
+/*
+ * Architectural interrupt line count, and the size of the bitmap needed
+ * to hold them.
+ */
+#define KVM_NR_INTERRUPTS 256
+#define KVM_IRQ_BITMAP_SIZE_BYTES    ((KVM_NR_INTERRUPTS + 7) / 8)
+#define KVM_IRQ_BITMAP_SIZE(type)    (KVM_IRQ_BITMAP_SIZE_BYTES / sizeof(type))
+
+
+/* for KVM_CREATE_MEMORY_REGION */
+struct kvm_memory_region {
+        __u32 slot;
+        __u32 flags;
+        __u64 guest_phys_addr;
+        __u64 memory_size; /* bytes */
+};
+
+/* for kvm_memory_region::flags */
+#define KVM_MEM_LOG_DIRTY_PAGES  1UL
+
+
+#define KVM_EXIT_TYPE_FAIL_ENTRY 1
+#define KVM_EXIT_TYPE_VM_EXIT    2
+
+enum kvm_exit_reason {
+        KVM_EXIT_UNKNOWN          = 0,
+        KVM_EXIT_EXCEPTION        = 1,
+        KVM_EXIT_IO               = 2,
+        KVM_EXIT_CPUID            = 3,
+        KVM_EXIT_DEBUG            = 4,
+        KVM_EXIT_HLT              = 5,
+        KVM_EXIT_MMIO             = 6,
+};
+
+/* for KVM_RUN */
+struct kvm_run {
+        /* in */
+        __u32 vcpu;
+        __u32 emulated;  /* skip current instruction */
+        __u32 mmio_completed; /* mmio request completed */
+
+        /* out */
+        __u32 exit_type;
+        __u32 exit_reason;
+        __u32 instruction_length;
+        union {
+                /* KVM_EXIT_UNKNOWN */
+                struct {
+                        __u32 hardware_exit_reason;
+                } hw;
+                /* KVM_EXIT_EXCEPTION */
+                struct {
+                        __u32 exception;
+                        __u32 error_code;
+                } ex;
+                /* KVM_EXIT_IO */
+                struct {
+#define KVM_EXIT_IO_IN  0
+#define KVM_EXIT_IO_OUT 1
+                        __u8 direction;
+                        __u8 size; /* bytes */
+                        __u8 string;
+                        __u8 string_down;
+                        __u8 rep;
+                        __u8 pad;
+                        __u16 port;
+                        __u64 count;
+                        union {
+                                __u64 address;
+                                __u32 value;
+                        };
+                } io;
+                struct {
+                } debug;
+                /* KVM_EXIT_MMIO */
+                struct {
+                        __u64 phys_addr;
+                        __u8  data[8];
+                        __u32 len;
+                        __u8  is_write;
+                } mmio;
+        };
+};
+
+/* for KVM_GET_REGS and KVM_SET_REGS */
+struct kvm_regs {
+        /* in */
+        __u32 vcpu;
+        __u32 padding;
+
+        /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
+        __u64 rax, rbx, rcx, rdx;
+        __u64 rsi, rdi, rsp, rbp;
+        __u64 r8,  r9,  r10, r11;
+        __u64 r12, r13, r14, r15;
+        __u64 rip, rflags;
+};
+
+struct kvm_segment {
+        __u64 base;
+        __u32 limit;
+        __u16 selector;
+        __u8  type;
+        __u8  present, dpl, db, s, l, g, avl;
+        __u8  unusable;
+        __u8  padding;
+};
+
+struct kvm_dtable {
+        __u64 base;
+        __u16 limit;
+        __u16 padding[3];
+};
+
+/* for KVM_GET_SREGS and KVM_SET_SREGS */
+struct kvm_sregs {
+        /* in */
+        __u32 vcpu;
+        __u32 padding;
+
+        /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
+        struct kvm_segment cs, ds, es, fs, gs, ss;
+        struct kvm_segment tr, ldt;
+        struct kvm_dtable gdt, idt;
+        __u64 cr0, cr2, cr3, cr4, cr8;
+        __u64 efer;
+        __u64 apic_base;
+        __u64 interrupt_bitmap[KVM_IRQ_BITMAP_SIZE(__u64)];
+};
+
+struct kvm_msr_entry {
+        __u32 index;
+        __u32 reserved;
+        __u64 data;
+};
+
+/* for KVM_GET_MSRS and KVM_SET_MSRS */
+struct kvm_msrs {
+        __u32 vcpu;
+        __u32 nmsrs; /* number of msrs in entries */
+
+        struct kvm_msr_entry entries[0];
+};
+
+/* for KVM_GET_MSR_INDEX_LIST */
+struct kvm_msr_list {
+        __u32 nmsrs; /* number of msrs in entries */
+        __u32 indices[0];
+};
+
+/* for KVM_TRANSLATE */
+struct kvm_translation {
+        /* in */
+        __u64 linear_address;
+        __u32 vcpu;
+        __u32 padding;
+
+        /* out */
+        __u64 physical_address;
+        __u8  valid;
+        __u8  writeable;
+        __u8  usermode;
+};
+
+/* for KVM_INTERRUPT */
+struct kvm_interrupt {
+        /* in */
+        __u32 vcpu;
+        __u32 irq;
+};
+
+struct kvm_breakpoint {
+        __u32 enabled;
+        __u32 padding;
+        __u64 address;
+};
+
+/* for KVM_DEBUG_GUEST */
+struct kvm_debug_guest {
+        /* int */
+        __u32 vcpu;
+        __u32 enabled;
+        struct kvm_breakpoint breakpoints[4];
+        __u32 singlestep;
+};
+
+/* for KVM_GET_DIRTY_LOG */
+struct kvm_dirty_log {
+        __u32 slot;
+        __u32 padding;
+        union {
+                void __user *dirty_bitmap; /* one bit per page */
+                __u64 padding;
+        };
+};
+
+#define KVMIO 0xAE
+
+#define KVM_RUN                   _IOWR(KVMIO, 2, struct kvm_run)
+#define KVM_GET_REGS              _IOWR(KVMIO, 3, struct kvm_regs)
+#define KVM_SET_REGS              _IOW(KVMIO, 4, struct kvm_regs)
+#define KVM_GET_SREGS             _IOWR(KVMIO, 5, struct kvm_sregs)
+#define KVM_SET_SREGS             _IOW(KVMIO, 6, struct kvm_sregs)
+#define KVM_TRANSLATE             _IOWR(KVMIO, 7, struct kvm_translation)
+#define KVM_INTERRUPT             _IOW(KVMIO, 8, struct kvm_interrupt)
+#define KVM_DEBUG_GUEST           _IOW(KVMIO, 9, struct kvm_debug_guest)
+#define KVM_SET_MEMORY_REGION     _IOW(KVMIO, 10, struct kvm_memory_region)
+#define KVM_CREATE_VCPU           _IOW(KVMIO, 11, int /* vcpu_slot */)
+#define KVM_GET_DIRTY_LOG         _IOW(KVMIO, 12, struct kvm_dirty_log)
+#define KVM_GET_MSRS              _IOWR(KVMIO, 13, struct kvm_msrs)
+#define KVM_SET_MSRS              _IOWR(KVMIO, 14, struct kvm_msrs)
+#define KVM_GET_MSR_INDEX_LIST    _IOWR(KVMIO, 15, struct kvm_msr_list)
+
+#endif
diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h
index 8c39654549d8..0c962b82a9de 100644
--- a/include/linux/lockd/lockd.h
+++ b/include/linux/lockd/lockd.h
@@ -206,7 +206,7 @@ void		  nlmsvc_invalidate_all(void);
 static __inline__ struct inode *
 nlmsvc_file_inode(struct nlm_file *file)
 {
-        return file->f_file->f_dentry->d_inode;
+        return file->f_file->f_path.dentry->d_inode;
 }
 
 /*
diff --git a/include/linux/log2.h b/include/linux/log2.h
new file mode 100644
index 000000000000..d02e1a547a7e
--- /dev/null
+++ b/include/linux/log2.h
@@ -0,0 +1,157 @@
+/* Integer base 2 logarithm calculation
+ *
+ * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _LINUX_LOG2_H
+#define _LINUX_LOG2_H
+
+#include <linux/types.h>
+#include <linux/bitops.h>
+
+/*
+ * deal with unrepresentable constant logarithms
+ */
+extern __attribute__((const, noreturn))
+int ____ilog2_NaN(void);
+
+/*
+ * non-constant log of base 2 calculators
+ * - the arch may override these in asm/bitops.h if they can be implemented
+ *   more efficiently than using fls() and fls64()
+ * - the arch is not required to handle n==0 if implementing the fallback
+ */
+#ifndef CONFIG_ARCH_HAS_ILOG2_U32
+static inline __attribute__((const))
+int __ilog2_u32(u32 n)
+{
+        return fls(n) - 1;
+}
+#endif
+
+#ifndef CONFIG_ARCH_HAS_ILOG2_U64
+static inline __attribute__((const))
+int __ilog2_u64(u64 n)
+{
+        return fls64(n) - 1;
+}
+#endif
+
+/*
+ * round up to nearest power of two
+ */
+static inline __attribute__((const))
+unsigned long __roundup_pow_of_two(unsigned long n)
+{
+        return 1UL << fls_long(n - 1);
+}
+
+/**
+ * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value
+ * @n - parameter
+ *
+ * constant-capable log of base 2 calculation
+ * - this can be used to initialise global variables from constant data, hence
+ *   the massive ternary operator construction
+ *
+ * selects the appropriately-sized optimised version depending on sizeof(n)
+ */
+#define ilog2(n)                                \
+(                                               \
+        __builtin_constant_p(n) ? (             \
+                (n) < 1 ? ____ilog2_NaN() :     \
+                (n) & (1ULL << 63) ? 63 :       \
+                (n) & (1ULL << 62) ? 62 :       \
+                (n) & (1ULL << 61) ? 61 :       \
+                (n) & (1ULL << 60) ? 60 :       \
+                (n) & (1ULL << 59) ? 59 :       \
+                (n) & (1ULL << 58) ? 58 :       \
+                (n) & (1ULL << 57) ? 57 :       \
+                (n) & (1ULL << 56) ? 56 :       \
+                (n) & (1ULL << 55) ? 55 :       \
+                (n) & (1ULL << 54) ? 54 :       \
+                (n) & (1ULL << 53) ? 53 :       \
+                (n) & (1ULL << 52) ? 52 :       \
+                (n) & (1ULL << 51) ? 51 :       \
+                (n) & (1ULL << 50) ? 50 :       \
+                (n) & (1ULL << 49) ? 49 :       \
+                (n) & (1ULL << 48) ? 48 :       \
+                (n) & (1ULL << 47) ? 47 :       \
+                (n) & (1ULL << 46) ? 46 :       \
+                (n) & (1ULL << 45) ? 45 :       \
+                (n) & (1ULL << 44) ? 44 :       \
+                (n) & (1ULL << 43) ? 43 :       \
+                (n) & (1ULL << 42) ? 42 :       \
+                (n) & (1ULL << 41) ? 41 :       \
+                (n) & (1ULL << 40) ? 40 :       \
+                (n) & (1ULL << 39) ? 39 :       \
+                (n) & (1ULL << 38) ? 38 :       \
+                (n) & (1ULL << 37) ? 37 :       \
+                (n) & (1ULL << 36) ? 36 :       \
+                (n) & (1ULL << 35) ? 35 :       \
+                (n) & (1ULL << 34) ? 34 :       \
+                (n) & (1ULL << 33) ? 33 :       \
+                (n) & (1ULL << 32) ? 32 :       \
+                (n) & (1ULL << 31) ? 31 :       \
+                (n) & (1ULL << 30) ? 30 :       \
+                (n) & (1ULL << 29) ? 29 :       \
+                (n) & (1ULL << 28) ? 28 :       \
+                (n) & (1ULL << 27) ? 27 :       \
+                (n) & (1ULL << 26) ? 26 :       \
+                (n) & (1ULL << 25) ? 25 :       \
+                (n) & (1ULL << 24) ? 24 :       \
+                (n) & (1ULL << 23) ? 23 :       \
+                (n) & (1ULL << 22) ? 22 :       \
+                (n) & (1ULL << 21) ? 21 :       \
+                (n) & (1ULL << 20) ? 20 :       \
+                (n) & (1ULL << 19) ? 19 :       \
+                (n) & (1ULL << 18) ? 18 :       \
+                (n) & (1ULL << 17) ? 17 :       \
+                (n) & (1ULL << 16) ? 16 :       \
+                (n) & (1ULL << 15) ? 15 :       \
+                (n) & (1ULL << 14) ? 14 :       \
+                (n) & (1ULL << 13) ? 13 :       \
+                (n) & (1ULL << 12) ? 12 :       \
+                (n) & (1ULL << 11) ? 11 :       \
+                (n) & (1ULL << 10) ? 10 :       \
+                (n) & (1ULL <<  9) ?  9 :       \
+                (n) & (1ULL <<  8) ?  8 :       \
+                (n) & (1ULL <<  7) ?  7 :       \
+                (n) & (1ULL <<  6) ?  6 :       \
+                (n) & (1ULL <<  5) ?  5 :       \
+                (n) & (1ULL <<  4) ?  4 :       \
+                (n) & (1ULL <<  3) ?  3 :       \
+                (n) & (1ULL <<  2) ?  2 :       \
+                (n) & (1ULL <<  1) ?  1 :       \
+                (n) & (1ULL <<  0) ?  0 :       \
+                ____ilog2_NaN()                 \
+                                   ) :          \
+        (sizeof(n) <= 4) ?                      \
+        __ilog2_u32(n) :                        \
+        __ilog2_u64(n)                          \
+ )
+
+/**
+ * roundup_pow_of_two - round the given value up to nearest power of two
+ * @n - parameter
+ *
+ * round the given balue up to the nearest power of two
+ * - the result is undefined when n == 0
+ * - this can be used to initialise global variables from constant data
+ */
+#define roundup_pow_of_two(n)                   \
+(                                               \
+        __builtin_constant_p(n) ? (             \
+                (n == 1) ? 0 :                  \
+                (1UL << (ilog2((n) - 1) + 1))   \
+                                   ) :          \
+        __roundup_pow_of_two(n)                 \
+ )
+
+#endif /* _LINUX_LOG2_H */
diff --git a/include/linux/mnt_namespace.h b/include/linux/mnt_namespace.h
new file mode 100644
index 000000000000..4af0b1fc282a
--- /dev/null
+++ b/include/linux/mnt_namespace.h
@@ -0,0 +1,42 @@
+#ifndef _NAMESPACE_H_
+#define _NAMESPACE_H_
+#ifdef __KERNEL__
+
+#include <linux/mount.h>
+#include <linux/sched.h>
+#include <linux/nsproxy.h>
+
+struct mnt_namespace {
+        atomic_t                count;
+        struct vfsmount *       root;
+        struct list_head        list;
+        wait_queue_head_t poll;
+        int event;
+};
+
+extern int copy_mnt_ns(int, struct task_struct *);
+extern void __put_mnt_ns(struct mnt_namespace *ns);
+extern struct mnt_namespace *dup_mnt_ns(struct task_struct *,
+                struct fs_struct *);
+
+static inline void put_mnt_ns(struct mnt_namespace *ns)
+{
+        if (atomic_dec_and_lock(&ns->count, &vfsmount_lock))
+                /* releases vfsmount_lock */
+                __put_mnt_ns(ns);
+}
+
+static inline void exit_mnt_ns(struct task_struct *p)
+{
+        struct mnt_namespace *ns = p->nsproxy->mnt_ns;
+        if (ns)
+                put_mnt_ns(ns);
+}
+
+static inline void get_mnt_ns(struct mnt_namespace *ns)
+{
+        atomic_inc(&ns->count);
+}
+
+#endif
+#endif
diff --git a/include/linux/module.h b/include/linux/module.h
index d33df2408e05..10f771a49997 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -319,6 +319,13 @@ struct module
 
         unsigned int taints;    /* same bits as kernel:tainted */
 
+#ifdef CONFIG_GENERIC_BUG
+        /* Support for BUG */
+        struct list_head bug_list;
+        struct bug_entry *bug_table;
+        unsigned num_bugs;
+#endif
+
 #ifdef CONFIG_MODULE_UNLOAD
         /* Reference counts */
         struct module_ref ref[NR_CPUS];
diff --git a/include/linux/mount.h b/include/linux/mount.h
index 403d1a97c512..e357dc86a4de 100644
--- a/include/linux/mount.h
+++ b/include/linux/mount.h
@@ -20,7 +20,7 @@
 struct super_block;
 struct vfsmount;
 struct dentry;
-struct namespace;
+struct mnt_namespace;
 
 #define MNT_NOSUID      0x01
 #define MNT_NODEV       0x02
@@ -52,7 +52,7 @@ struct vfsmount {
         struct list_head mnt_slave_list;/* list of slave mounts */
         struct list_head mnt_slave;     /* slave list entry */
         struct vfsmount *mnt_master;    /* slave is on master->mnt_slave_list */
-        struct namespace *mnt_namespace; /* containing namespace */
+        struct mnt_namespace *mnt_ns;   /* containing namespace */
         int mnt_pinned;
 };
 
diff --git a/include/linux/mutex.h b/include/linux/mutex.h
index b2b91c477563..a7544afd7582 100644
--- a/include/linux/mutex.h
+++ b/include/linux/mutex.h
@@ -125,8 +125,10 @@ extern int fastcall mutex_lock_interruptible(struct mutex *lock);
 
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 extern void mutex_lock_nested(struct mutex *lock, unsigned int subclass);
+extern int mutex_lock_interruptible_nested(struct mutex *lock, unsigned int subclass);
 #else
 # define mutex_lock_nested(lock, subclass) mutex_lock(lock)
+# define mutex_lock_interruptible_nested(lock, subclass) mutex_lock_interruptible(lock)
 #endif
 
 /*
diff --git a/include/linux/namei.h b/include/linux/namei.h
index f5f19606effb..d39a5a67e979 100644
--- a/include/linux/namei.h
+++ b/include/linux/namei.h
@@ -29,6 +29,11 @@ struct nameidata {
         } intent;
 };
 
+struct path {
+        struct vfsmount *mnt;
+        struct dentry *dentry;
+};
+
 /*
  * Type of the last component on LOOKUP_PARENT
  */
diff --git a/include/linux/namespace.h b/include/linux/namespace.h
deleted file mode 100644
index d137009f0b2b..000000000000
--- a/include/linux/namespace.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _NAMESPACE_H_
-#define _NAMESPACE_H_
-#ifdef __KERNEL__
-
-#include <linux/mount.h>
-#include <linux/sched.h>
-#include <linux/nsproxy.h>
-
-struct namespace {
-        atomic_t                count;
-        struct vfsmount *       root;
-        struct list_head        list;
-        wait_queue_head_t poll;
-        int event;
-};
-
-extern int copy_namespace(int, struct task_struct *);
-extern void __put_namespace(struct namespace *namespace);
-extern struct namespace *dup_namespace(struct task_struct *, struct fs_struct *);
-
-static inline void put_namespace(struct namespace *namespace)
-{
-        if (atomic_dec_and_lock(&namespace->count, &vfsmount_lock))
-                /* releases vfsmount_lock */
-                __put_namespace(namespace);
-}
-
-static inline void exit_namespace(struct task_struct *p)
-{
-        struct namespace *namespace = p->nsproxy->namespace;
-        if (namespace) {
-                put_namespace(namespace);
-        }
-}
-
-static inline void get_namespace(struct namespace *namespace)
-{
-        atomic_inc(&namespace->count);
-}
-
-#endif
-#endif
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index c57088f575a3..6be767c76b37 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -193,13 +193,20 @@ struct hh_cache
 {
         struct hh_cache *hh_next;       /* Next entry                        */
         atomic_t        hh_refcnt;      /* number of users                   */
-        __be16          hh_type;        /* protocol identifier, f.e ETH_P_IP
+/*
+ * We want hh_output, hh_len, hh_lock and hh_data be a in a separate
+ * cache line on SMP.
+ * They are mostly read, but hh_refcnt may be changed quite frequently,
+ * incurring cache line ping pongs.
+ */
+        __be16          hh_type ____cacheline_aligned_in_smp;
+                                        /* protocol identifier, f.e ETH_P_IP
                                          *  NOTE:  For VLANs, this will be the
                                          *  encapuslated type. --BLG
                                          */
         u16             hh_len;         /* length of header */
         int             (*hh_output)(struct sk_buff *skb);
-        rwlock_t        hh_lock;
+        seqlock_t       hh_lock;
 
         /* cached hardware header; allow for machine alignment needs.        */
 #define HH_DATA_MOD     16
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 625ffea98561..04963063e620 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -33,6 +33,7 @@
 #define FLUSH_HIGHPRI           16      /* high priority memory reclaim flush */
 #define FLUSH_NOCOMMIT          32      /* Don't send the NFSv3/v4 COMMIT */
 #define FLUSH_INVALIDATE        64      /* Invalidate the page cache */
+#define FLUSH_NOWRITEPAGE       128     /* Don't call writepage() */
 
 #ifdef __KERNEL__
 
@@ -427,19 +428,21 @@ extern int  nfs_flush_incompatible(struct file *file, struct page *page);
 extern int  nfs_updatepage(struct file *, struct page *, unsigned int, unsigned int);
 extern int nfs_writeback_done(struct rpc_task *, struct nfs_write_data *);
 extern void nfs_writedata_release(void *);
-
-#if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4)
-struct nfs_write_data *nfs_commit_alloc(void);
-void nfs_commit_free(struct nfs_write_data *p);
-#endif
+extern int nfs_set_page_dirty(struct page *);
 
 /*
  * Try to write back everything synchronously (but check the
  * return value!)
  */
-extern int  nfs_sync_inode_wait(struct inode *, unsigned long, unsigned int, int);
+extern long nfs_sync_mapping_wait(struct address_space *, struct writeback_control *, int);
+extern int nfs_sync_mapping_range(struct address_space *, loff_t, loff_t, int);
+extern int nfs_wb_all(struct inode *inode);
+extern int nfs_wb_page(struct inode *inode, struct page* page);
+extern int nfs_wb_page_priority(struct inode *inode, struct page* page, int how);
 #if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4)
 extern int  nfs_commit_inode(struct inode *, int);
+extern struct nfs_write_data *nfs_commit_alloc(void);
+extern void nfs_commit_free(struct nfs_write_data *wdata);
 extern void nfs_commit_release(void *wdata);
 #else
 static inline int
@@ -455,28 +458,6 @@ nfs_have_writebacks(struct inode *inode)
         return NFS_I(inode)->npages != 0;
 }
 
-static inline int
-nfs_wb_all(struct inode *inode)
-{
-        int error = nfs_sync_inode_wait(inode, 0, 0, 0);
-        return (error < 0) ? error : 0;
-}
-
-/*
- * Write back all requests on one page - we do this before reading it.
- */
-static inline int nfs_wb_page_priority(struct inode *inode, struct page* page, int how)
-{
-        int error = nfs_sync_inode_wait(inode, page->index, 1,
-                        how | FLUSH_STABLE);
-        return (error < 0) ? error : 0;
-}
-
-static inline int nfs_wb_page(struct inode *inode, struct page* page)
-{
-        return nfs_wb_page_priority(inode, page, 0);
-}
-
 /*
  * Allocate nfs_write_data structures
  */
diff --git a/include/linux/nfs_page.h b/include/linux/nfs_page.h
index 1f7bd287c230..2e555d49c9b7 100644
--- a/include/linux/nfs_page.h
+++ b/include/linux/nfs_page.h
@@ -30,6 +30,8 @@
 #define PG_BUSY                 0
 #define PG_NEED_COMMIT          1
 #define PG_NEED_RESCHED         2
+#define PG_NEED_FLUSH           3
+#define PG_FLUSHING             4
 
 struct nfs_inode;
 struct nfs_page {
@@ -60,8 +62,9 @@ extern	void nfs_clear_request(struct nfs_page *req);
 extern  void nfs_release_request(struct nfs_page *req);
 
 
-extern  int nfs_scan_lock_dirty(struct nfs_inode *nfsi, struct list_head *dst,
-                                unsigned long idx_start, unsigned int npages);
+extern  long nfs_scan_dirty(struct address_space *mapping,
+                                struct writeback_control *wbc,
+                                struct list_head *dst);
 extern  int nfs_scan_list(struct nfs_inode *nfsi, struct list_head *head, struct list_head *dst,
                           unsigned long idx_start, unsigned int npages);
 extern  int nfs_coalesce_requests(struct list_head *, struct list_head *,
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index 768c1ad5ff6f..9ee9da5e1cc9 100644
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -785,8 +785,6 @@ struct nfs_rpc_ops {
         int     (*readlink)(struct inode *, struct page *, unsigned int,
                             unsigned int);
         int     (*read)    (struct nfs_read_data *);
-        int     (*write)   (struct nfs_write_data *);
-        int     (*commit)  (struct nfs_write_data *);
         int     (*create)  (struct inode *, struct dentry *,
                             struct iattr *, int, struct nameidata *);
         int     (*remove)  (struct inode *, struct qstr *);
diff --git a/include/linux/nsproxy.h b/include/linux/nsproxy.h
index 971d1c6dfc4b..fdfb0e44912f 100644
--- a/include/linux/nsproxy.h
+++ b/include/linux/nsproxy.h
@@ -4,9 +4,10 @@
 #include <linux/spinlock.h>
 #include <linux/sched.h>
 
-struct namespace;
+struct mnt_namespace;
 struct uts_namespace;
 struct ipc_namespace;
+struct pid_namespace;
 
 /*
  * A structure to contain pointers to all per-process
@@ -23,9 +24,11 @@ struct ipc_namespace;
 struct nsproxy {
         atomic_t count;
         spinlock_t nslock;
+        unsigned long id;
         struct uts_namespace *uts_ns;
         struct ipc_namespace *ipc_ns;
-        struct namespace *namespace;
+        struct mnt_namespace *mnt_ns;
+        struct pid_namespace *pid_ns;
 };
 extern struct nsproxy init_nsproxy;
 
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 4d972bbef316..51180dba9a98 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1785,14 +1785,17 @@
 #define PCI_DEVICE_ID_MOXA_C104         0x1040
 #define PCI_DEVICE_ID_MOXA_CP104U       0x1041
 #define PCI_DEVICE_ID_MOXA_CP104JU      0x1042
+#define PCI_DEVICE_ID_MOXA_CP104EL      0x1043
 #define PCI_DEVICE_ID_MOXA_CT114        0x1140
 #define PCI_DEVICE_ID_MOXA_CP114        0x1141
 #define PCI_DEVICE_ID_MOXA_CP118U       0x1180
+#define PCI_DEVICE_ID_MOXA_CP118EL      0x1181
 #define PCI_DEVICE_ID_MOXA_CP132        0x1320
 #define PCI_DEVICE_ID_MOXA_CP132U       0x1321
 #define PCI_DEVICE_ID_MOXA_CP134U       0x1340
 #define PCI_DEVICE_ID_MOXA_C168         0x1680
 #define PCI_DEVICE_ID_MOXA_CP168U       0x1681
+#define PCI_DEVICE_ID_MOXA_CP168EL      0x1682
 
 #define PCI_VENDOR_ID_CCD               0x1397
 #define PCI_DEVICE_ID_CCD_2BD0          0x2bd0
diff --git a/include/linux/pid.h b/include/linux/pid.h
index 2c0007d17218..4dec047b1837 100644
--- a/include/linux/pid.h
+++ b/include/linux/pid.h
@@ -35,8 +35,9 @@ enum pid_type
  *
  * Holding a reference to struct pid solves both of these problems.
  * It is small so holding a reference does not consume a lot of
- * resources, and since a new struct pid is allocated when the numeric
- * pid value is reused we don't mistakenly refer to new processes.
+ * resources, and since a new struct pid is allocated when the numeric pid
+ * value is reused (when pids wrap around) we don't mistakenly refer to new
+ * processes.
  */
 
 struct pid
diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h
new file mode 100644
index 000000000000..d2a9d419f01f
--- /dev/null
+++ b/include/linux/pid_namespace.h
@@ -0,0 +1,45 @@
+#ifndef _LINUX_PID_NS_H
+#define _LINUX_PID_NS_H
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/threads.h>
+#include <linux/pid.h>
+#include <linux/nsproxy.h>
+#include <linux/kref.h>
+
+struct pidmap {
+       atomic_t nr_free;
+       void *page;
+};
+
+#define PIDMAP_ENTRIES         ((PID_MAX_LIMIT + 8*PAGE_SIZE - 1)/PAGE_SIZE/8)
+
+struct pid_namespace {
+        struct kref kref;
+        struct pidmap pidmap[PIDMAP_ENTRIES];
+        int last_pid;
+        struct task_struct *child_reaper;
+};
+
+extern struct pid_namespace init_pid_ns;
+
+static inline void get_pid_ns(struct pid_namespace *ns)
+{
+        kref_get(&ns->kref);
+}
+
+extern int copy_pid_ns(int flags, struct task_struct *tsk);
+extern void free_pid_ns(struct kref *kref);
+
+static inline void put_pid_ns(struct pid_namespace *ns)
+{
+        kref_put(&ns->kref, free_pid_ns);
+}
+
+static inline struct task_struct *child_reaper(struct task_struct *tsk)
+{
+        return tsk->nsproxy->pid_ns->child_reaper;
+}
+
+#endif /* _LINUX_PID_NS_H */
diff --git a/include/linux/pktcdvd.h b/include/linux/pktcdvd.h
index 8a94c717c266..5ea4f05683f6 100644
--- a/include/linux/pktcdvd.h
+++ b/include/linux/pktcdvd.h
@@ -111,6 +111,13 @@ struct pkt_ctrl_command {
 #include <linux/blkdev.h>
 #include <linux/completion.h>
 #include <linux/cdrom.h>
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+/* default bio write queue congestion marks */
+#define PKT_WRITE_CONGESTION_ON    10000
+#define PKT_WRITE_CONGESTION_OFF   9000
+
 
 struct packet_settings
 {
@@ -241,6 +248,14 @@ struct packet_stacked_data
 };
 #define PSD_POOL_SIZE           64
 
+struct pktcdvd_kobj
+{
+        struct kobject          kobj;
+        struct pktcdvd_device   *pd;
+};
+#define to_pktcdvdkobj(_k) \
+  ((struct pktcdvd_kobj*)container_of(_k,struct pktcdvd_kobj,kobj))
+
 struct pktcdvd_device
 {
         struct block_device     *bdev;          /* dev attached */
@@ -271,6 +286,16 @@ struct pktcdvd_device
 
         struct packet_iosched   iosched;
         struct gendisk          *disk;
+
+        int                     write_congestion_off;
+        int                     write_congestion_on;
+
+        struct class_device     *clsdev;        /* sysfs pktcdvd[0-7] class dev */
+        struct pktcdvd_kobj     *kobj_stat;     /* sysfs pktcdvd[0-7]/stat/     */
+        struct pktcdvd_kobj     *kobj_wqueue;   /* sysfs pktcdvd[0-7]/write_queue/ */
+
+        struct dentry           *dfs_d_root;    /* debugfs: devname directory */
+        struct dentry           *dfs_f_info;    /* debugfs: info file */
 };
 
 #endif /* __KERNEL__ */
diff --git a/include/linux/pspace.h b/include/linux/pspace.h
deleted file mode 100644
index 91d48b8b2d99..000000000000
--- a/include/linux/pspace.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _LINUX_PSPACE_H
-#define _LINUX_PSPACE_H
-
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/threads.h>
-#include <linux/pid.h>
-
-struct pidmap {
-       atomic_t nr_free;
-       void *page;
-};
-
-#define PIDMAP_ENTRIES         ((PID_MAX_LIMIT + 8*PAGE_SIZE - 1)/PAGE_SIZE/8)
-
-struct pspace {
-       struct pidmap pidmap[PIDMAP_ENTRIES];
-       int last_pid;
-};
-
-extern struct pspace init_pspace;
-
-#endif /* _LINUX_PSPACE_H */
diff --git a/include/linux/raid/raid5.h b/include/linux/raid/raid5.h
index 03636d7918fe..d8286db60b96 100644
--- a/include/linux/raid/raid5.h
+++ b/include/linux/raid/raid5.h
@@ -227,7 +227,10 @@ struct raid5_private_data {
         struct list_head        handle_list; /* stripes needing handling */
         struct list_head        delayed_list; /* stripes that have plugged requests */
         struct list_head        bitmap_list; /* stripes delaying awaiting bitmap update */
+        struct bio              *retry_read_aligned; /* currently retrying aligned bios   */
+        struct bio              *retry_read_aligned_list; /* aligned bios retry list  */
         atomic_t                preread_active_stripes; /* stripes with scheduled io */
+        atomic_t                active_aligned_reads;
 
         atomic_t                reshape_stripes; /* stripes with pending writes for reshape */
         /* unfortunately we need two cache names as we temporarily have
diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h
index d0e4dce33ad5..c3fc6caaad3f 100644
--- a/include/linux/reiserfs_fs.h
+++ b/include/linux/reiserfs_fs.h
@@ -1159,7 +1159,7 @@ znodes are the way! */
 #define PATH_READA      0x1     /* do read ahead */
 #define PATH_READA_BACK 0x2     /* read backwards */
 
-struct path {
+struct treepath {
         int path_length;        /* Length of the array above.   */
         int reada;
         struct path_element path_elements[EXTENDED_MAX_HEIGHT]; /* Array of the path elements.  */
@@ -1169,7 +1169,7 @@ struct path {
 #define pos_in_item(path) ((path)->pos_in_item)
 
 #define INITIALIZE_PATH(var) \
-struct path var = {.path_length = ILLEGAL_PATH_ELEMENT_OFFSET, .reada = 0,}
+struct treepath var = {.path_length = ILLEGAL_PATH_ELEMENT_OFFSET, .reada = 0,}
 
 /* Get path element by path and path position. */
 #define PATH_OFFSET_PELEMENT(p_s_path,n_offset)  ((p_s_path)->path_elements +(n_offset))
@@ -1327,7 +1327,7 @@ struct tree_balance {
         int need_balance_dirty;
         struct super_block *tb_sb;
         struct reiserfs_transaction_handle *transaction_handle;
-        struct path *tb_path;
+        struct treepath *tb_path;
         struct buffer_head *L[MAX_HEIGHT];      /* array of left neighbors of nodes in the path */
         struct buffer_head *R[MAX_HEIGHT];      /* array of right neighbors of nodes in the path */
         struct buffer_head *FL[MAX_HEIGHT];     /* array of fathers of the left  neighbors      */
@@ -1793,41 +1793,41 @@ static inline void copy_key(struct reiserfs_key *to,
         memcpy(to, from, KEY_SIZE);
 }
 
-int comp_items(const struct item_head *stored_ih, const struct path *p_s_path);
-const struct reiserfs_key *get_rkey(const struct path *p_s_chk_path,
+int comp_items(const struct item_head *stored_ih, const struct treepath *p_s_path);
+const struct reiserfs_key *get_rkey(const struct treepath *p_s_chk_path,
                                     const struct super_block *p_s_sb);
 int search_by_key(struct super_block *, const struct cpu_key *,
-                  struct path *, int);
+                  struct treepath *, int);
 #define search_item(s,key,path) search_by_key (s, key, path, DISK_LEAF_NODE_LEVEL)
 int search_for_position_by_key(struct super_block *p_s_sb,
                                const struct cpu_key *p_s_cpu_key,
-                               struct path *p_s_search_path);
+                               struct treepath *p_s_search_path);
 extern void decrement_bcount(struct buffer_head *p_s_bh);
-void decrement_counters_in_path(struct path *p_s_search_path);
-void pathrelse(struct path *p_s_search_path);
-int reiserfs_check_path(struct path *p);
-void pathrelse_and_restore(struct super_block *s, struct path *p_s_search_path);
+void decrement_counters_in_path(struct treepath *p_s_search_path);
+void pathrelse(struct treepath *p_s_search_path);
+int reiserfs_check_path(struct treepath *p);
+void pathrelse_and_restore(struct super_block *s, struct treepath *p_s_search_path);
 
 int reiserfs_insert_item(struct reiserfs_transaction_handle *th,
-                         struct path *path,
+                         struct treepath *path,
                          const struct cpu_key *key,
                          struct item_head *ih,
                          struct inode *inode, const char *body);
 
 int reiserfs_paste_into_item(struct reiserfs_transaction_handle *th,
-                             struct path *path,
+                             struct treepath *path,
                              const struct cpu_key *key,
                              struct inode *inode,
                              const char *body, int paste_size);
 
 int reiserfs_cut_from_item(struct reiserfs_transaction_handle *th,
-                           struct path *path,
+                           struct treepath *path,
                            struct cpu_key *key,
                            struct inode *inode,
                            struct page *page, loff_t new_file_size);
 
 int reiserfs_delete_item(struct reiserfs_transaction_handle *th,
-                         struct path *path,
+                         struct treepath *path,
                          const struct cpu_key *key,
                          struct inode *inode, struct buffer_head *p_s_un_bh);
 
@@ -1858,7 +1858,7 @@ void padd_item(char *item, int total_length, int length);
 #define GET_BLOCK_NO_DANGLE   16        /* don't leave any transactions running */
 
 int restart_transaction(struct reiserfs_transaction_handle *th,
-                        struct inode *inode, struct path *path);
+                        struct inode *inode, struct treepath *path);
 void reiserfs_read_locked_inode(struct inode *inode,
                                 struct reiserfs_iget_args *args);
 int reiserfs_find_actor(struct inode *inode, void *p);
@@ -1905,7 +1905,7 @@ int reiserfs_setattr(struct dentry *dentry, struct iattr *attr);
 /* namei.c */
 void set_de_name_and_namelen(struct reiserfs_dir_entry *de);
 int search_by_entry_key(struct super_block *sb, const struct cpu_key *key,
-                        struct path *path, struct reiserfs_dir_entry *de);
+                        struct treepath *path, struct reiserfs_dir_entry *de);
 struct dentry *reiserfs_get_parent(struct dentry *);
 /* procfs.c */
 
@@ -1956,9 +1956,9 @@ extern const struct file_operations reiserfs_dir_operations;
 
 /* tail_conversion.c */
 int direct2indirect(struct reiserfs_transaction_handle *, struct inode *,
-                    struct path *, struct buffer_head *, loff_t);
+                    struct treepath *, struct buffer_head *, loff_t);
 int indirect2direct(struct reiserfs_transaction_handle *, struct inode *,
-                    struct page *, struct path *, const struct cpu_key *,
+                    struct page *, struct treepath *, const struct cpu_key *,
                     loff_t, char *);
 void reiserfs_unmap_buffer(struct buffer_head *);
 
@@ -2045,7 +2045,7 @@ struct __reiserfs_blocknr_hint {
         struct inode *inode;    /* inode passed to allocator, if we allocate unf. nodes */
         long block;             /* file offset, in blocks */
         struct in_core_key key;
-        struct path *path;      /* search path, used by allocator to deternine search_start by
+        struct treepath *path;  /* search path, used by allocator to deternine search_start by
                                  * various ways */
         struct reiserfs_transaction_handle *th; /* transaction handle is needed to log super blocks and
                                                  * bitmap blocks changes  */
@@ -2101,7 +2101,7 @@ static inline int reiserfs_new_form_blocknrs(struct tree_balance *tb,
 static inline int reiserfs_new_unf_blocknrs(struct reiserfs_transaction_handle
                                             *th, struct inode *inode,
                                             b_blocknr_t * new_blocknrs,
-                                            struct path *path, long block)
+                                            struct treepath *path, long block)
 {
         reiserfs_blocknr_hint_t hint = {
                 .th = th,
@@ -2118,7 +2118,7 @@ static inline int reiserfs_new_unf_blocknrs(struct reiserfs_transaction_handle
 static inline int reiserfs_new_unf_blocknrs2(struct reiserfs_transaction_handle
                                              *th, struct inode *inode,
                                              b_blocknr_t * new_blocknrs,
-                                             struct path *path, long block)
+                                             struct treepath *path, long block)
 {
         reiserfs_blocknr_hint_t hint = {
                 .th = th,
diff --git a/include/linux/rtc.h b/include/linux/rtc.h
index 09ff4c3e2713..5e22d4510d11 100644
--- a/include/linux/rtc.h
+++ b/include/linux/rtc.h
@@ -106,6 +106,7 @@ extern int rtc_year_days(unsigned int day, unsigned int month, unsigned int year
 extern int rtc_valid_tm(struct rtc_time *tm);
 extern int rtc_tm_to_time(struct rtc_time *tm, unsigned long *time);
 extern void rtc_time_to_tm(unsigned long time, struct rtc_time *tm);
+extern void rtc_merge_alarm(struct rtc_time *now, struct rtc_time *alarm);
 
 #include <linux/device.h>
 #include <linux/seq_file.h>
diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h
index 493297acdae8..4a629ea70cc4 100644
--- a/include/linux/rtnetlink.h
+++ b/include/linux/rtnetlink.h
@@ -3,6 +3,8 @@
 
 #include <linux/netlink.h>
 #include <linux/if_link.h>
+#include <linux/if_addr.h>
+#include <linux/neighbour.h>
 
 /****
  *              Routing/neighbour discovery messages.
diff --git a/include/linux/sched.h b/include/linux/sched.h
index dede82c63445..ea92e5c89089 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -82,6 +82,7 @@ struct sched_param {
 #include <linux/resource.h>
 #include <linux/timer.h>
 #include <linux/hrtimer.h>
+#include <linux/task_io_accounting.h>
 
 #include <asm/processor.h>
 
@@ -436,7 +437,12 @@ struct signal_struct {
         /* job control IDs */
         pid_t pgrp;
         pid_t tty_old_pgrp;
-        pid_t session;
+
+        union {
+                pid_t session __deprecated;
+                pid_t __session;
+        };
+
         /* boolean value for session group leader */
         int leader;
 
@@ -642,6 +648,7 @@ enum idle_type
 #define SD_SHARE_CPUPOWER       128     /* Domain members share cpu power */
 #define SD_POWERSAVINGS_BALANCE 256     /* Balance for power savings */
 #define SD_SHARE_PKG_RESOURCES  512     /* Domain members share cpu pkg resources */
+#define SD_SERIALIZE            1024    /* Only a single load balancing instance */
 
 #define BALANCE_FOR_MC_POWER    \
         (sched_smt_power_savings ? SD_POWERSAVINGS_BALANCE : 0)
@@ -1008,6 +1015,7 @@ struct task_struct {
         wait_queue_t *io_wait;
 /* i/o counters(bytes read/written, #syscalls */
         u64 rchar, wchar, syscr, syscw;
+        struct task_io_accounting ioac;
 #if defined(CONFIG_TASK_XACCT)
         u64 acct_rss_mem1;      /* accumulated rss usage */
         u64 acct_vm_mem1;       /* accumulated virtual memory usage */
@@ -1040,6 +1048,9 @@ struct task_struct {
 #ifdef  CONFIG_TASK_DELAY_ACCT
         struct task_delay_info *delays;
 #endif
+#ifdef CONFIG_FAULT_INJECTION
+        int make_it_fail;
+#endif
 };
 
 static inline pid_t process_group(struct task_struct *tsk)
@@ -1047,6 +1058,21 @@ static inline pid_t process_group(struct task_struct *tsk)
         return tsk->signal->pgrp;
 }
 
+static inline pid_t signal_session(struct signal_struct *sig)
+{
+        return sig->__session;
+}
+
+static inline pid_t process_session(struct task_struct *tsk)
+{
+        return signal_session(tsk->signal);
+}
+
+static inline void set_signal_session(struct signal_struct *sig, pid_t session)
+{
+        sig->__session = session;
+}
+
 static inline struct pid *task_pid(struct task_struct *task)
 {
         return task->pids[PIDTYPE_PID].pid;
@@ -1240,7 +1266,6 @@ extern struct   mm_struct init_mm;
 
 #define find_task_by_pid(nr)    find_task_by_pid_type(PIDTYPE_PID, nr)
 extern struct task_struct *find_task_by_pid_type(int type, int pid);
-extern void set_special_pids(pid_t session, pid_t pgrp);
 extern void __set_special_pids(pid_t session, pid_t pgrp);
 
 /* per-UID process charging. */
@@ -1381,7 +1406,6 @@ extern NORET_TYPE void do_group_exit(int);
 extern void daemonize(const char *, ...);
 extern int allow_signal(int);
 extern int disallow_signal(int);
-extern struct task_struct *child_reaper;
 
 extern int do_execve(char *, char __user * __user *, char __user * __user *, struct pt_regs *);
 extern long do_fork(unsigned long, unsigned long, struct pt_regs *, unsigned long, int __user *, int __user *);
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 827672136646..cf23813cbec2 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -166,8 +166,8 @@ struct uart_ops {
         void            (*break_ctl)(struct uart_port *, int ctl);
         int             (*startup)(struct uart_port *);
         void            (*shutdown)(struct uart_port *);
-        void            (*set_termios)(struct uart_port *, struct termios *new,
-                                       struct termios *old);
+        void            (*set_termios)(struct uart_port *, struct ktermios *new,
+                                       struct ktermios *old);
         void            (*pm)(struct uart_port *, unsigned int state,
                               unsigned int oldstate);
         int             (*set_wake)(struct uart_port *, unsigned int state);
@@ -361,8 +361,8 @@ void uart_write_wakeup(struct uart_port *port);
  */
 void uart_update_timeout(struct uart_port *port, unsigned int cflag,
                          unsigned int baud);
-unsigned int uart_get_baud_rate(struct uart_port *port, struct termios *termios,
-                                struct termios *old, unsigned int min,
+unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios,
+                                struct ktermios *old, unsigned int min,
                                 unsigned int max);
 unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);
 
diff --git a/include/linux/serio.h b/include/linux/serio.h
index b99c5ca9708d..0f478a8791a2 100644
--- a/include/linux/serio.h
+++ b/include/linux/serio.h
@@ -85,18 +85,8 @@ static inline void serio_register_port(struct serio *serio)
 
 void serio_unregister_port(struct serio *serio);
 void serio_unregister_child_port(struct serio *serio);
-void __serio_unregister_port_delayed(struct serio *serio, struct module *owner);
-static inline void serio_unregister_port_delayed(struct serio *serio)
-{
-        __serio_unregister_port_delayed(serio, THIS_MODULE);
-}
-
-void __serio_register_driver(struct serio_driver *drv, struct module *owner);
-static inline void serio_register_driver(struct serio_driver *drv)
-{
-        __serio_register_driver(drv, THIS_MODULE);
-}
 
+int serio_register_driver(struct serio_driver *drv);
 void serio_unregister_driver(struct serio_driver *drv);
 
 static inline int serio_write(struct serio *serio, unsigned char data)
diff --git a/include/linux/stallion.h b/include/linux/stallion.h
index 13a37f137ea2..4a0a329beafb 100644
--- a/include/linux/stallion.h
+++ b/include/linux/stallion.h
@@ -52,11 +52,11 @@
  *      protection - since "write" code only needs to change the head, and
  *      interrupt code only needs to change the tail.
  */
-typedef struct {
+struct stlrq {
         char    *buf;
         char    *head;
         char    *tail;
-} stlrq_t;
+};
 
 /*
  *      Port, panel and board structures to hold status info about each.
@@ -67,14 +67,14 @@ typedef struct {
  *      is associated with, this makes it (fairly) easy to get back to the
  *      board/panel info for a port.
  */
-typedef struct stlport {
+struct stlport {
         unsigned long           magic;
-        int                     portnr;
-        int                     panelnr;
-        int                     brdnr;
+        unsigned int            portnr;
+        unsigned int            panelnr;
+        unsigned int            brdnr;
         int                     ioaddr;
         int                     uartaddr;
-        int                     pagenr;
+        unsigned int            pagenr;
         long                    istate;
         int                     flags;
         int                     baud_base;
@@ -97,31 +97,31 @@ typedef struct stlport {
         wait_queue_head_t       close_wait;
         struct work_struct      tqueue;
         comstats_t              stats;
-        stlrq_t                 tx;
-} stlport_t;
+        struct stlrq            tx;
+};
 
-typedef struct stlpanel {
+struct stlpanel {
         unsigned long   magic;
-        int             panelnr;
-        int             brdnr;
-        int             pagenr;
-        int             nrports;
+        unsigned int    panelnr;
+        unsigned int    brdnr;
+        unsigned int    pagenr;
+        unsigned int    nrports;
         int             iobase;
         void            *uartp;
         void            (*isr)(struct stlpanel *panelp, unsigned int iobase);
         unsigned int    hwid;
         unsigned int    ackmask;
-        stlport_t       *ports[STL_PORTSPERPANEL];
-} stlpanel_t;
+        struct stlport  *ports[STL_PORTSPERPANEL];
+};
 
-typedef struct stlbrd {
+struct stlbrd {
         unsigned long   magic;
-        int             brdnr;
-        int             brdtype;
-        int             state;
-        int             nrpanels;
-        int             nrports;
-        int             nrbnks;
+        unsigned int    brdnr;
+        unsigned int    brdtype;
+        unsigned int    state;
+        unsigned int    nrpanels;
+        unsigned int    nrports;
+        unsigned int    nrbnks;
         int             irq;
         int             irqtype;
         int             (*isr)(struct stlbrd *brdp);
@@ -136,9 +136,9 @@ typedef struct stlbrd {
         unsigned long   clk;
         unsigned int    bnkpageaddr[STL_MAXBANKS];
         unsigned int    bnkstataddr[STL_MAXBANKS];
-        stlpanel_t      *bnk2panel[STL_MAXBANKS];
-        stlpanel_t      *panels[STL_MAXPANELS];
-} stlbrd_t;
+        struct stlpanel *bnk2panel[STL_MAXBANKS];
+        struct stlpanel *panels[STL_MAXPANELS];
+};
 
 
 /*
diff --git a/include/linux/sunrpc/auth_gss.h b/include/linux/sunrpc/auth_gss.h
index 97b62e97dd8d..2db2fbf34947 100644
--- a/include/linux/sunrpc/auth_gss.h
+++ b/include/linux/sunrpc/auth_gss.h
@@ -90,8 +90,6 @@ struct gss_cred {
 #define gc_flags                gc_base.cr_flags
 #define gc_expire               gc_base.cr_expire
 
-void print_hexl(u32 *p, u_int length, u_int offset);
-
 #endif /* __KERNEL__ */
 #endif /* _LINUX_SUNRPC_AUTH_GSS_H */
 
diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h
index f6d1d646ce05..a1be89deb3af 100644
--- a/include/linux/sunrpc/clnt.h
+++ b/include/linux/sunrpc/clnt.h
@@ -53,6 +53,7 @@ struct rpc_clnt {
         struct dentry *         cl_dentry;      /* inode */
         struct rpc_clnt *       cl_parent;      /* Points to parent of clones */
         struct rpc_rtt          cl_rtt_default;
+        struct rpc_program *    cl_program;
         char                    cl_inline_name[32];
 };
 
diff --git a/include/linux/sunrpc/debug.h b/include/linux/sunrpc/debug.h
index e4729aa67654..60fce3c92857 100644
--- a/include/linux/sunrpc/debug.h
+++ b/include/linux/sunrpc/debug.h
@@ -62,12 +62,6 @@ extern unsigned int		nlm_debug;
 # define RPC_IFDEBUG(x)
 #endif
 
-#ifdef RPC_PROFILE
-# define pprintk(args...)       printk(## args)
-#else
-# define pprintk(args...)       do ; while (0)
-#endif
-
 /*
  * Sysctl interface for RPC debugging
  */
diff --git a/include/linux/sunrpc/gss_krb5.h b/include/linux/sunrpc/gss_krb5.h
index e30ba201910a..5a4b1e0206e3 100644
--- a/include/linux/sunrpc/gss_krb5.h
+++ b/include/linux/sunrpc/gss_krb5.h
@@ -42,10 +42,6 @@
 
 struct krb5_ctx {
         int                     initiate; /* 1 = initiating, 0 = accepting */
-        int                     seed_init;
-        unsigned char           seed[16];
-        int                     signalg;
-        int                     sealalg;
         struct crypto_blkcipher *enc;
         struct crypto_blkcipher *seq;
         s32                     endtime;
@@ -117,7 +113,7 @@ enum seal_alg {
 #define ENCTYPE_UNKNOWN         0x01ff
 
 s32
-make_checksum(s32 cksumtype, char *header, int hdrlen, struct xdr_buf *body,
+make_checksum(char *, char *header, int hdrlen, struct xdr_buf *body,
                    int body_offset, struct xdr_netobj *cksum);
 
 u32 gss_get_mic_kerberos(struct gss_ctx *, struct xdr_buf *,
diff --git a/include/linux/sunrpc/gss_spkm3.h b/include/linux/sunrpc/gss_spkm3.h
index 2cf3fbb40b4f..e3e6a3437f8b 100644
--- a/include/linux/sunrpc/gss_spkm3.h
+++ b/include/linux/sunrpc/gss_spkm3.h
@@ -12,27 +12,19 @@
 #include <linux/sunrpc/gss_asn1.h>
 
 struct spkm3_ctx {
-        struct xdr_netobj       ctx_id; /* per message context id */
-        int                     qop;         /* negotiated qop */
+        struct xdr_netobj       ctx_id;  /* per message context id */
+        int                     endtime; /* endtime of the context */
         struct xdr_netobj       mech_used;
         unsigned int            ret_flags ;
-        unsigned int            req_flags ;
-        struct xdr_netobj       share_key;
-        int                     conf_alg;
-        struct crypto_blkcipher *derived_conf_key;
-        int                     intg_alg;
-        struct crypto_blkcipher *derived_integ_key;
-        int                     keyestb_alg;   /* alg used to get share_key */
-        int                     owf_alg;   /* one way function */
+        struct xdr_netobj       conf_alg;
+        struct xdr_netobj       derived_conf_key;
+        struct xdr_netobj       intg_alg;
+        struct xdr_netobj       derived_integ_key;
 };
 
-/* from openssl/objects.h */
-/* XXX need SEAL_ALG_NONE */
-#define NID_md5         4
-#define NID_dhKeyAgreement      28 
-#define NID_des_cbc             31 
-#define NID_sha1                64
-#define NID_cast5_cbc           108
+/* OIDs declarations for K-ALG, I-ALG, C-ALG, and OWF-ALG */
+extern const struct xdr_netobj hmac_md5_oid;
+extern const struct xdr_netobj cast5_cbc_oid;
 
 /* SPKM InnerContext Token types */
 
@@ -46,11 +38,13 @@ u32 spkm3_make_token(struct spkm3_ctx *ctx, struct xdr_buf * text, struct xdr_ne
 u32 spkm3_read_token(struct spkm3_ctx *ctx, struct xdr_netobj *read_token, struct xdr_buf *message_buffer, int toktype);
 
 #define CKSUMTYPE_RSA_MD5            0x0007
+#define CKSUMTYPE_HMAC_MD5           0x0008
 
-s32 make_checksum(s32 cksumtype, char *header, int hdrlen, struct xdr_buf *body,
-                   int body_offset, struct xdr_netobj *cksum);
+s32 make_spkm3_checksum(s32 cksumtype, struct xdr_netobj *key, char *header,
+                unsigned int hdrlen, struct xdr_buf *body,
+                unsigned int body_offset, struct xdr_netobj *cksum);
 void asn1_bitstring_len(struct xdr_netobj *in, int *enclen, int *zerobits);
-int decode_asn1_bitstring(struct xdr_netobj *out, char *in, int enclen, 
+int decode_asn1_bitstring(struct xdr_netobj *out, char *in, int enclen,
                    int explen);
 void spkm3_mic_header(unsigned char **hdrbuf, unsigned int *hdrlen, 
                    unsigned char *ctxhdr, int elen, int zbit);
diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h
index 0746c3b16f3a..97c761652581 100644
--- a/include/linux/sunrpc/sched.h
+++ b/include/linux/sunrpc/sched.h
@@ -11,6 +11,7 @@
 
 #include <linux/timer.h>
 #include <linux/sunrpc/types.h>
+#include <linux/rcupdate.h>
 #include <linux/spinlock.h>
 #include <linux/wait.h>
 #include <linux/workqueue.h>
@@ -85,6 +86,7 @@ struct rpc_task {
         union {
                 struct work_struct      tk_work;        /* Async task work queue */
                 struct rpc_wait         tk_wait;        /* RPC wait */
+                struct rcu_head         tk_rcu;         /* for task deletion */
         } u;
 
         unsigned short          tk_timeouts;    /* maj timeouts */
@@ -178,13 +180,6 @@ struct rpc_call_ops {
         } while (0)
 
 #define RPC_IS_ACTIVATED(t)     (test_bit(RPC_TASK_ACTIVE, &(t)->tk_runstate))
-#define rpc_set_active(t)       (set_bit(RPC_TASK_ACTIVE, &(t)->tk_runstate))
-#define rpc_clear_active(t)     \
-        do { \
-                smp_mb__before_clear_bit(); \
-                clear_bit(RPC_TASK_ACTIVE, &(t)->tk_runstate); \
-                smp_mb__after_clear_bit(); \
-        } while(0)
 
 /*
  * Task priorities.
@@ -254,8 +249,10 @@ struct rpc_task *rpc_run_task(struct rpc_clnt *clnt, int flags,
 void            rpc_init_task(struct rpc_task *task, struct rpc_clnt *clnt,
                                 int flags, const struct rpc_call_ops *ops,
                                 void *data);
+void            rpc_put_task(struct rpc_task *);
 void            rpc_release_task(struct rpc_task *);
 void            rpc_exit_task(struct rpc_task *);
+void            rpc_release_calldata(const struct rpc_call_ops *, void *);
 void            rpc_killall_tasks(struct rpc_clnt *);
 int             rpc_execute(struct rpc_task *);
 void            rpc_init_priority_wait_queue(struct rpc_wait_queue *, const char *);
diff --git a/include/linux/sunrpc/xdr.h b/include/linux/sunrpc/xdr.h
index 9a527c364394..9e340fa23c06 100644
--- a/include/linux/sunrpc/xdr.h
+++ b/include/linux/sunrpc/xdr.h
@@ -11,6 +11,7 @@
 
 #include <linux/uio.h>
 #include <asm/byteorder.h>
+#include <linux/scatterlist.h>
 
 /*
  * Buffer adjustment
@@ -139,29 +140,30 @@ xdr_adjust_iovec(struct kvec *iov, __be32 *p)
  */
 extern void xdr_shift_buf(struct xdr_buf *, size_t);
 extern void xdr_buf_from_iov(struct kvec *, struct xdr_buf *);
-extern int xdr_buf_subsegment(struct xdr_buf *, struct xdr_buf *, int, int);
-extern int xdr_buf_read_netobj(struct xdr_buf *, struct xdr_netobj *, int);
-extern int read_bytes_from_xdr_buf(struct xdr_buf *, int, void *, int);
-extern int write_bytes_to_xdr_buf(struct xdr_buf *, int, void *, int);
+extern int xdr_buf_subsegment(struct xdr_buf *, struct xdr_buf *, unsigned int, unsigned int);
+extern int xdr_buf_read_netobj(struct xdr_buf *, struct xdr_netobj *, unsigned int);
+extern int read_bytes_from_xdr_buf(struct xdr_buf *, unsigned int, void *, unsigned int);
+extern int write_bytes_to_xdr_buf(struct xdr_buf *, unsigned int, void *, unsigned int);
 
 /*
  * Helper structure for copying from an sk_buff.
  */
-typedef struct {
+struct xdr_skb_reader {
         struct sk_buff  *skb;
         unsigned int    offset;
         size_t          count;
         __wsum          csum;
-} skb_reader_t;
+};
 
-typedef size_t (*skb_read_actor_t)(skb_reader_t *desc, void *to, size_t len);
+typedef size_t (*xdr_skb_read_actor)(struct xdr_skb_reader *desc, void *to, size_t len);
 
+size_t xdr_skb_read_bits(struct xdr_skb_reader *desc, void *to, size_t len);
 extern int csum_partial_copy_to_xdr(struct xdr_buf *, struct sk_buff *);
 extern ssize_t xdr_partial_copy_from_skb(struct xdr_buf *, unsigned int,
-                skb_reader_t *, skb_read_actor_t);
+                struct xdr_skb_reader *, xdr_skb_read_actor);
 
-extern int xdr_encode_word(struct xdr_buf *, int, u32);
-extern int xdr_decode_word(struct xdr_buf *, int, u32 *);
+extern int xdr_encode_word(struct xdr_buf *, unsigned int, u32);
+extern int xdr_decode_word(struct xdr_buf *, unsigned int, u32 *);
 
 struct xdr_array2_desc;
 typedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *desc, void *elem);
@@ -196,6 +198,7 @@ extern void xdr_init_decode(struct xdr_stream *xdr, struct xdr_buf *buf, __be32
 extern __be32 *xdr_inline_decode(struct xdr_stream *xdr, size_t nbytes);
 extern void xdr_read_pages(struct xdr_stream *xdr, unsigned int len);
 extern void xdr_enter_page(struct xdr_stream *xdr, unsigned int len);
+extern int xdr_process_buf(struct xdr_buf *buf, unsigned int offset, unsigned int len, int (*actor)(struct scatterlist *, void *), void *data);
 
 #endif /* __KERNEL__ */
 
diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h
index 3e04c1512fc4..f780e72fc417 100644
--- a/include/linux/sunrpc/xprt.h
+++ b/include/linux/sunrpc/xprt.h
@@ -106,7 +106,6 @@ struct rpc_rqst {
 
 struct rpc_xprt_ops {
         void            (*set_buffer_size)(struct rpc_xprt *xprt, size_t sndsize, size_t rcvsize);
-        char *          (*print_addr)(struct rpc_xprt *xprt, enum rpc_display_format_t format);
         int             (*reserve_xprt)(struct rpc_task *task);
         void            (*release_xprt)(struct rpc_xprt *xprt, struct rpc_task *task);
         void            (*rpcbind)(struct rpc_task *task);
@@ -126,8 +125,6 @@ struct rpc_xprt_ops {
 struct rpc_xprt {
         struct kref             kref;           /* Reference count */
         struct rpc_xprt_ops *   ops;            /* transport methods */
-        struct socket *         sock;           /* BSD socket layer */
-        struct sock *           inet;           /* INET layer */
 
         struct rpc_timeout      timeout;        /* timeout parms */
         struct sockaddr_storage addr;           /* server address */
@@ -137,9 +134,6 @@ struct rpc_xprt {
         unsigned long           cong;           /* current congestion */
         unsigned long           cwnd;           /* congestion window */
 
-        size_t                  rcvsize,        /* transport rcv buffer size */
-                                sndsize;        /* transport send buffer size */
-
         size_t                  max_payload;    /* largest RPC payload size,
                                                    in bytes */
         unsigned int            tsh_size;       /* size of transport specific
@@ -158,27 +152,11 @@ struct rpc_xprt {
                                 resvport   : 1; /* use a reserved port */
 
         /*
-         * XID
-         */
-        __u32                   xid;            /* Next XID value to use */
-
-        /*
-         * State of TCP reply receive stuff
-         */
-        __be32                  tcp_recm,       /* Fragment header */
-                                tcp_xid;        /* Current XID */
-        u32                     tcp_reclen,     /* fragment length */
-                                tcp_offset;     /* fragment offset */
-        unsigned long           tcp_copied,     /* copied to request */
-                                tcp_flags;
-        /*
          * Connection of transports
          */
         unsigned long           connect_timeout,
                                 bind_timeout,
                                 reestablish_timeout;
-        struct delayed_work     connect_worker;
-        unsigned short          port;
 
         /*
          * Disconnection of idle transports
@@ -193,8 +171,8 @@ struct rpc_xprt {
          */
         spinlock_t              transport_lock; /* lock transport info */
         spinlock_t              reserve_lock;   /* lock slot table */
+        u32                     xid;            /* Next XID value to use */
         struct rpc_task *       snd_task;       /* Task blocked in send */
-
         struct list_head        recv;
 
         struct {
@@ -210,18 +188,9 @@ struct rpc_xprt {
                                         bklog_u;        /* backlog queue utilization */
         } stat;
 
-        void                    (*old_data_ready)(struct sock *, int);
-        void                    (*old_state_change)(struct sock *);
-        void                    (*old_write_space)(struct sock *);
-
         char *                  address_strings[RPC_DISPLAY_MAX];
 };
 
-#define XPRT_LAST_FRAG          (1 << 0)
-#define XPRT_COPY_RECM          (1 << 1)
-#define XPRT_COPY_XID           (1 << 2)
-#define XPRT_COPY_DATA          (1 << 3)
-
 #ifdef __KERNEL__
 
 /*
@@ -270,8 +239,8 @@ void			xprt_disconnect(struct rpc_xprt *xprt);
 /*
  * Socket transport setup operations
  */
-int                     xs_setup_udp(struct rpc_xprt *xprt, struct rpc_timeout *to);
-int                     xs_setup_tcp(struct rpc_xprt *xprt, struct rpc_timeout *to);
+struct rpc_xprt *       xs_setup_udp(struct sockaddr *addr, size_t addrlen, struct rpc_timeout *to);
+struct rpc_xprt *       xs_setup_tcp(struct sockaddr *addr, size_t addrlen, struct rpc_timeout *to);
 
 /*
  * Reserved bit positions in xprt->state
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index 94316a98e0d0..6d8846e7be6d 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -918,8 +918,7 @@ typedef struct ctl_table ctl_table;
 
 typedef int ctl_handler (ctl_table *table, int __user *name, int nlen,
                          void __user *oldval, size_t __user *oldlenp,
-                         void __user *newval, size_t newlen, 
-                         void **context);
+                         void __user *newval, size_t newlen);
 
 typedef int proc_handler (ctl_table *ctl, int write, struct file * filp,
                           void __user *buffer, size_t *lenp, loff_t *ppos);
@@ -950,7 +949,7 @@ extern int do_sysctl (int __user *name, int nlen,
 extern int do_sysctl_strategy (ctl_table *table, 
                                int __user *name, int nlen,
                                void __user *oldval, size_t __user *oldlenp,
-                               void __user *newval, size_t newlen, void ** context);
+                               void __user *newval, size_t newlen);
 
 extern ctl_handler sysctl_string;
 extern ctl_handler sysctl_intvec;
diff --git a/include/linux/task_io_accounting.h b/include/linux/task_io_accounting.h
new file mode 100644
index 000000000000..44d00e9cceea
--- /dev/null
+++ b/include/linux/task_io_accounting.h
@@ -0,0 +1,37 @@
+/*
+ * task_io_accounting: a structure which is used for recording a single task's
+ * IO statistics.
+ *
+ * Don't include this header file directly - it is designed to be dragged in via
+ * sched.h.
+ *
+ * Blame akpm@osdl.org for all this.
+ */
+
+#ifdef CONFIG_TASK_IO_ACCOUNTING
+struct task_io_accounting {
+        /*
+         * The number of bytes which this task has caused to be read from
+         * storage.
+         */
+        u64 read_bytes;
+
+        /*
+         * The number of bytes which this task has caused, or shall cause to be
+         * written to disk.
+         */
+        u64 write_bytes;
+
+        /*
+         * A task can cause "negative" IO too.  If this task truncates some
+         * dirty pagecache, some IO which another task has been accounted for
+         * (in its write_bytes) will not be happening.  We _could_ just
+         * subtract that from the truncating task's write_bytes, but there is
+         * information loss in doing that.
+         */
+        u64 cancelled_write_bytes;
+};
+#else
+struct task_io_accounting {
+};
+#endif
diff --git a/include/linux/task_io_accounting_ops.h b/include/linux/task_io_accounting_ops.h
new file mode 100644
index 000000000000..df2a319106b2
--- /dev/null
+++ b/include/linux/task_io_accounting_ops.h
@@ -0,0 +1,47 @@
+/*
+ * Task I/O accounting operations
+ */
+#ifndef __TASK_IO_ACCOUNTING_OPS_INCLUDED
+#define __TASK_IO_ACCOUNTING_OPS_INCLUDED
+
+#ifdef CONFIG_TASK_IO_ACCOUNTING
+static inline void task_io_account_read(size_t bytes)
+{
+        current->ioac.read_bytes += bytes;
+}
+
+static inline void task_io_account_write(size_t bytes)
+{
+        current->ioac.write_bytes += bytes;
+}
+
+static inline void task_io_account_cancelled_write(size_t bytes)
+{
+        current->ioac.cancelled_write_bytes += bytes;
+}
+
+static inline void task_io_accounting_init(struct task_struct *tsk)
+{
+        memset(&tsk->ioac, 0, sizeof(tsk->ioac));
+}
+
+#else
+
+static inline void task_io_account_read(size_t bytes)
+{
+}
+
+static inline void task_io_account_write(size_t bytes)
+{
+}
+
+static inline void task_io_account_cancelled_write(size_t bytes)
+{
+}
+
+static inline void task_io_accounting_init(struct task_struct *tsk)
+{
+}
+
+#endif          /* CONFIG_TASK_IO_ACCOUNTING */
+#endif          /* __TASK_IO_ACCOUNTING_OPS_INCLUDED */
diff --git a/include/linux/taskstats.h b/include/linux/taskstats.h
index 45248806ae9c..3fced4798255 100644
--- a/include/linux/taskstats.h
+++ b/include/linux/taskstats.h
@@ -31,7 +31,7 @@
  */
 
 
-#define TASKSTATS_VERSION       2
+#define TASKSTATS_VERSION       3
 #define TS_COMM_LEN             32      /* should be >= TASK_COMM_LEN
                                          * in linux/sched.h */
 
@@ -115,31 +115,37 @@ struct taskstats {
         __u64   ac_majflt;              /* Major Page Fault Count */
         /* Basic Accounting Fields end */
 
-        /* Extended accounting fields start */
+        /* Extended accounting fields start */
         /* Accumulated RSS usage in duration of a task, in MBytes-usecs.
          * The current rss usage is added to this counter every time
          * a tick is charged to a task's system time. So, at the end we
          * will have memory usage multiplied by system time. Thus an
          * average usage per system time unit can be calculated.
          */
-        __u64   coremem;                /* accumulated RSS usage in MB-usec */
+        __u64   coremem;                /* accumulated RSS usage in MB-usec */
         /* Accumulated virtual memory usage in duration of a task.
          * Same as acct_rss_mem1 above except that we keep track of VM usage.
          */
-        __u64   virtmem;                /* accumulated VM  usage in MB-usec */
+        __u64   virtmem;                /* accumulated VM  usage in MB-usec */
 
         /* High watermark of RSS and virtual memory usage in duration of
          * a task, in KBytes.
          */
-        __u64   hiwater_rss;            /* High-watermark of RSS usage, in KB */
-        __u64   hiwater_vm;             /* High-water VM usage, in KB */
+        __u64   hiwater_rss;            /* High-watermark of RSS usage, in KB */
+        __u64   hiwater_vm;             /* High-water VM usage, in KB */
 
         /* The following four fields are I/O statistics of a task. */
-        __u64   read_char;              /* bytes read */
-        __u64   write_char;             /* bytes written */
-        __u64   read_syscalls;          /* read syscalls */
-        __u64   write_syscalls;         /* write syscalls */
-        /* Extended accounting fields end */
+        __u64   read_char;              /* bytes read */
+        __u64   write_char;             /* bytes written */
+        __u64   read_syscalls;          /* read syscalls */
+        __u64   write_syscalls;         /* write syscalls */
+        /* Extended accounting fields end */
+
+#define TASKSTATS_HAS_IO_ACCOUNTING
+        /* Per-task storage I/O accounting starts */
+        __u64   read_bytes;             /* bytes of read I/O */
+        __u64   write_bytes;            /* bytes of write I/O */
+        __u64   cancelled_write_bytes;  /* bytes of cancelled write I/O */
 };
 
 
diff --git a/include/linux/timer.h b/include/linux/timer.h
index c982304dbafd..eeef6643d4c6 100644
--- a/include/linux/timer.h
+++ b/include/linux/timer.h
@@ -98,4 +98,10 @@ extern void run_local_timers(void);
 struct hrtimer;
 extern int it_real_fn(struct hrtimer *);
 
+unsigned long __round_jiffies(unsigned long j, int cpu);
+unsigned long __round_jiffies_relative(unsigned long j, int cpu);
+unsigned long round_jiffies(unsigned long j);
+unsigned long round_jiffies_relative(unsigned long j);
+
+
 #endif
diff --git a/include/linux/topology.h b/include/linux/topology.h
index da508d1998e4..6c5a6e6e813b 100644
--- a/include/linux/topology.h
+++ b/include/linux/topology.h
@@ -93,7 +93,7 @@
         .groups                 = NULL,                 \
         .min_interval           = 1,                    \
         .max_interval           = 2,                    \
-        .busy_factor            = 8,                    \
+        .busy_factor            = 64,                   \
         .imbalance_pct          = 110,                  \
         .cache_nice_tries       = 0,                    \
         .per_cpu_gain           = 25,                   \
@@ -194,7 +194,8 @@
         .wake_idx               = 0, /* unused */       \
         .forkexec_idx           = 0, /* unused */       \
         .per_cpu_gain           = 100,                  \
-        .flags                  = SD_LOAD_BALANCE,      \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_SERIALIZE, \
         .last_balance           = jiffies,              \
         .balance_interval       = 64,                   \
         .nr_balance_failed      = 0,                    \
diff --git a/include/linux/tty.h b/include/linux/tty.h
index f717f0898238..65cbcf22c31e 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -175,7 +175,7 @@ struct tty_struct {
         int index;
         struct tty_ldisc ldisc;
         struct mutex termios_mutex;
-        struct termios *termios, *termios_locked;
+        struct ktermios *termios, *termios_locked;
         char name[64];
         int pgrp;
         int session;
@@ -258,7 +258,7 @@ struct tty_struct {
 
 extern void tty_write_flush(struct tty_struct *);
 
-extern struct termios tty_std_termios;
+extern struct ktermios tty_std_termios;
 
 extern int kmsg_redirect;
 
@@ -293,8 +293,9 @@ extern int tty_hung_up_p(struct file * filp);
 extern void do_SAK(struct tty_struct *tty);
 extern void disassociate_ctty(int priv);
 extern void tty_flip_buffer_push(struct tty_struct *tty);
-extern int tty_get_baud_rate(struct tty_struct *tty);
-extern int tty_termios_baud_rate(struct termios *termios);
+extern speed_t tty_get_baud_rate(struct tty_struct *tty);
+extern speed_t tty_termios_baud_rate(struct ktermios *termios);
+extern speed_t tty_termios_input_baud_rate(struct ktermios *termios);
 
 extern struct tty_ldisc *tty_ldisc_ref(struct tty_struct *);
 extern void tty_ldisc_deref(struct tty_ldisc *);
@@ -309,6 +310,12 @@ extern void tty_ldisc_flush(struct tty_struct *tty);
 extern int tty_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
                      unsigned long arg);
 
+extern dev_t tty_devnum(struct tty_struct *tty);
+extern void proc_clear_tty(struct task_struct *p);
+extern void __proc_set_tty(struct task_struct *tsk, struct tty_struct *tty);
+extern void proc_set_tty(struct task_struct *tsk, struct tty_struct *tty);
+extern struct tty_struct *get_current_tty(void);
+
 extern struct mutex tty_mutex;
 
 /* n_tty.c */
@@ -335,10 +342,5 @@ extern void console_print(const char *);
 extern int vt_ioctl(struct tty_struct *tty, struct file * file,
                     unsigned int cmd, unsigned long arg);
 
-static inline dev_t tty_devnum(struct tty_struct *tty)
-{
-        return MKDEV(tty->driver->major, tty->driver->minor_start) + tty->index;
-}
-
 #endif /* __KERNEL__ */
 #endif
diff --git a/include/linux/tty_driver.h b/include/linux/tty_driver.h
index 5c8473bb6882..659487e3ebeb 100644
--- a/include/linux/tty_driver.h
+++ b/include/linux/tty_driver.h
@@ -53,7 +53,7 @@
  *      device-specific ioctl's.  If the ioctl number passed in cmd
  *      is not recognized by the driver, it should return ENOIOCTLCMD.
  * 
- * void (*set_termios)(struct tty_struct *tty, struct termios * old);
+ * void (*set_termios)(struct tty_struct *tty, struct ktermios * old);
  *
  *      This routine allows the tty driver to be notified when
  *      device's termios settings have changed.  Note that a
@@ -132,7 +132,7 @@ struct tty_operations {
         int  (*chars_in_buffer)(struct tty_struct *tty);
         int  (*ioctl)(struct tty_struct *tty, struct file * file,
                     unsigned int cmd, unsigned long arg);
-        void (*set_termios)(struct tty_struct *tty, struct termios * old);
+        void (*set_termios)(struct tty_struct *tty, struct ktermios * old);
         void (*throttle)(struct tty_struct * tty);
         void (*unthrottle)(struct tty_struct * tty);
         void (*stop)(struct tty_struct *tty);
@@ -165,7 +165,7 @@ struct tty_driver {
         int     num;            /* number of devices allocated */
         short   type;           /* type of tty driver */
         short   subtype;        /* subtype of tty driver */
-        struct termios init_termios; /* Initial termios */
+        struct ktermios init_termios; /* Initial termios */
         int     flags;          /* tty driver flags */
         int     refcount;       /* for loadable tty drivers */
         struct proc_dir_entry *proc_entry; /* /proc fs entry */
@@ -175,8 +175,8 @@ struct tty_driver {
          * Pointer to the tty data structures
          */
         struct tty_struct **ttys;
-        struct termios **termios;
-        struct termios **termios_locked;
+        struct ktermios **termios;
+        struct ktermios **termios_locked;
         void *driver_state;     /* only used for the PTY driver */
         
         /*
@@ -193,7 +193,7 @@ struct tty_driver {
         int  (*chars_in_buffer)(struct tty_struct *tty);
         int  (*ioctl)(struct tty_struct *tty, struct file * file,
                     unsigned int cmd, unsigned long arg);
-        void (*set_termios)(struct tty_struct *tty, struct termios * old);
+        void (*set_termios)(struct tty_struct *tty, struct ktermios * old);
         void (*throttle)(struct tty_struct * tty);
         void (*unthrottle)(struct tty_struct * tty);
         void (*stop)(struct tty_struct *tty);
diff --git a/include/linux/tty_ldisc.h b/include/linux/tty_ldisc.h
index 83c6e6c10ebb..d75932e27710 100644
--- a/include/linux/tty_ldisc.h
+++ b/include/linux/tty_ldisc.h
@@ -59,7 +59,7 @@
  *      low-level driver can "grab" an ioctl request before the line
  *      discpline has a chance to see it.
  * 
- * void (*set_termios)(struct tty_struct *tty, struct termios * old);
+ * void (*set_termios)(struct tty_struct *tty, struct ktermios * old);
  *
  *      This function notifies the line discpline that a change has
  *      been made to the termios structure.
@@ -118,7 +118,7 @@ struct tty_ldisc {
                          const unsigned char * buf, size_t nr); 
         int     (*ioctl)(struct tty_struct * tty, struct file * file,
                          unsigned int cmd, unsigned long arg);
-        void    (*set_termios)(struct tty_struct *tty, struct termios * old);
+        void    (*set_termios)(struct tty_struct *tty, struct ktermios * old);
         unsigned int (*poll)(struct tty_struct *, struct file *,
                              struct poll_table_struct *);
         int     (*hangup)(struct tty_struct *tty);
diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h
index 91b3ea2bbb14..10f99e5f1a97 100644
--- a/include/linux/usb/serial.h
+++ b/include/linux/usb/serial.h
@@ -218,7 +218,7 @@ struct usb_serial_driver {
         int  (*write)           (struct usb_serial_port *port, const unsigned char *buf, int count);
         int  (*write_room)      (struct usb_serial_port *port);
         int  (*ioctl)           (struct usb_serial_port *port, struct file * file, unsigned int cmd, unsigned long arg);
-        void (*set_termios)     (struct usb_serial_port *port, struct termios * old);
+        void (*set_termios)     (struct usb_serial_port *port, struct ktermios * old);
         void (*break_ctl)       (struct usb_serial_port *port, int break_state);
         int  (*chars_in_buffer) (struct usb_serial_port *port);
         void (*throttle)        (struct usb_serial_port *port);
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index df5c4654360d..5cb380a559fd 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -244,6 +244,7 @@ struct v4l2_pix_format
 #define V4L2_PIX_FMT_YYUV    v4l2_fourcc('Y','Y','U','V') /* 16  YUV 4:2:2     */
 #define V4L2_PIX_FMT_HI240   v4l2_fourcc('H','I','2','4') /*  8  8-bit color   */
 #define V4L2_PIX_FMT_HM12    v4l2_fourcc('H','M','1','2') /*  8  YUV 4:2:0 16x16 macroblocks */
+#define V4L2_PIX_FMT_RGB444  v4l2_fourcc('R','4','4','4') /* 16  xxxxrrrr ggggbbbb */
 
 /* see http://www.siliconimaging.com/RGB%20Bayer.htm */
 #define V4L2_PIX_FMT_SBGGR8  v4l2_fourcc('B','A','8','1') /*  8  BGBG.. GRGR.. */
diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h
index 088ba8113f7e..9529ea1ae392 100644
--- a/include/linux/xfrm.h
+++ b/include/linux/xfrm.h
@@ -357,7 +357,7 @@ struct xfrm_user_report {
 #define XFRMGRP_EXPIRE          2
 #define XFRMGRP_SA              4
 #define XFRMGRP_POLICY          8
-#define XFRMGRP_REPORT          0x10
+#define XFRMGRP_REPORT          0x20
 #endif
 
 enum xfrm_nlgroups {
diff --git a/include/media/ir-common.h b/include/media/ir-common.h
index 8f58406533c6..2b25f5c95006 100644
--- a/include/media/ir-common.h
+++ b/include/media/ir-common.h
@@ -92,6 +92,7 @@ extern IR_KEYTAB_TYPE ir_codes_hauppauge_new[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_npgtech[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_norwood[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_proteus_2309[IR_KEYTAB_SIZE];
+extern IR_KEYTAB_TYPE ir_codes_budget_ci_old[IR_KEYTAB_SIZE];
 
 #endif
 
diff --git a/include/media/saa7146.h b/include/media/saa7146.h
index fee579f10b32..796bcf151a3a 100644
--- a/include/media/saa7146.h
+++ b/include/media/saa7146.h
@@ -42,10 +42,6 @@ extern unsigned int saa7146_debug;
 #define DEB_INT(x)  if (0!=(DEBUG_VARIABLE&0x20)) { DEBUG_PROLOG; printk x; } /* interrupt debug messages */
 #define DEB_CAP(x)  if (0!=(DEBUG_VARIABLE&0x40)) { DEBUG_PROLOG; printk x; } /* capture debug messages */
 
-#define SAA7146_IER_DISABLE(x,y) \
-        saa7146_write(x, IER, saa7146_read(x, IER) & ~(y));
-#define SAA7146_IER_ENABLE(x,y) \
-        saa7146_write(x, IER, saa7146_read(x, IER) | (y));
 #define SAA7146_ISR_CLEAR(x,y) \
         saa7146_write(x, ISR, (y));
 
@@ -441,4 +437,20 @@ int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop);
 #define SAA7146_I2C_BUS_BIT_RATE_80     (0x200)
 #define SAA7146_I2C_BUS_BIT_RATE_60     (0x300)
 
+static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&x->int_slock, flags);
+        saa7146_write(x, IER, saa7146_read(x, IER) & ~y);
+        spin_unlock_irqrestore(&x->int_slock, flags);
+}
+
+static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&x->int_slock, flags);
+        saa7146_write(x, IER, saa7146_read(x, IER) | y);
+        spin_unlock_irqrestore(&x->int_slock, flags);
+}
+
 #endif
diff --git a/include/media/tuner-types.h b/include/media/tuner-types.h
index 37dad07a8439..e5ad3fcfe984 100644
--- a/include/media/tuner-types.h
+++ b/include/media/tuner-types.h
@@ -50,6 +50,10 @@ struct tuner_params {
            sensitivity. If this setting is 1, then set PORT2 to 1 to
            get proper FM reception. */
         unsigned int port2_fm_high_sensitivity:1;
+        /* Some Philips tuners use tda9887 cGainNormal to select the FM radio
+           sensitivity. If this setting is 1, e register will use cGainNormal
+           instead of cGainLow. */
+        unsigned int fm_gain_normal:1;
         /* Most tuners with a tda9887 use QSS mode. Some (cheaper) tuners
            use Intercarrier mode. If this setting is 1, then the tuner
            needs to be set to intercarrier mode. */
diff --git a/include/media/tuner.h b/include/media/tuner.h
index 3116e750132f..99acf847365c 100644
--- a/include/media/tuner.h
+++ b/include/media/tuner.h
@@ -145,6 +145,7 @@ extern int tuner_debug;
 #define TDA9887_DEEMPHASIS_75           (3<<16)
 #define TDA9887_AUTOMUTE                (1<<18)
 #define TDA9887_GATING_18               (1<<19)
+#define TDA9887_GAIN_NORMAL             (1<<20)
 
 #ifdef __KERNEL__
 
diff --git a/include/media/tveeprom.h b/include/media/tveeprom.h
index e9fc1a785497..5660ea24996b 100644
--- a/include/media/tveeprom.h
+++ b/include/media/tveeprom.h
@@ -3,7 +3,7 @@
 
 struct tveeprom {
         u32 has_radio;
-        u32 has_ir;     /* 0: no IR, 1: IR present, 2: unknown */
+        u32 has_ir;     /* bit 0: IR receiver present, bit 1: IR transmitter (blaster) present. -1 == unknown */
         u32 has_MAC_address; /* 0: no MAC, 1: MAC present, 2: unknown */
 
         u32 tuner_type;
diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h
index aecc946980a3..91b19921f958 100644
--- a/include/media/v4l2-common.h
+++ b/include/media/v4l2-common.h
@@ -144,6 +144,9 @@ enum v4l2_chip_ident {
         V4L2_IDENT_CX25841 = 241,
         V4L2_IDENT_CX25842 = 242,
         V4L2_IDENT_CX25843 = 243,
+
+        /* OmniVision sensors - range 250-299 */
+        V4L2_IDENT_OV7670 = 250,
 };
 
 /* audio ioctls */
@@ -251,4 +254,8 @@ struct v4l2_crystal_freq {
    If the frequency is not supported, then -EINVAL is returned. */
 #define VIDIOC_INT_S_CRYSTAL_FREQ       _IOW ('d', 113, struct v4l2_crystal_freq)
 
+/* Initialize the sensor registors to some sort of reasonable
+   default values. */
+#define VIDIOC_INT_INIT                 _IOW ('d', 114, u32)
+
 #endif /* V4L2_COMMON_H_ */
diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h
index 6a11d772700f..fb96472a1bd3 100644
--- a/include/media/v4l2-dev.h
+++ b/include/media/v4l2-dev.h
@@ -43,6 +43,7 @@
 
 /*  Video standard functions  */
 extern unsigned int v4l2_video_std_fps(struct v4l2_standard *vs);
+extern char *v4l2_norm_to_name(v4l2_std_id id);
 extern int v4l2_video_std_construct(struct v4l2_standard *vs,
                                     int id, char *name);
 
@@ -81,12 +82,6 @@ extern long v4l_compat_ioctl32(struct file *file, unsigned int cmd,
  *      This version moves redundant code from video device code to
  *      the common handler
  */
-struct v4l2_tvnorm {
-        char          *name;
-        v4l2_std_id   id;
-
-        void          *priv_data;
-};
 
 struct video_device
 {
@@ -104,9 +99,8 @@ struct video_device
         int debug;      /* Activates debug level*/
 
         /* Video standard vars */
-        int tvnormsize; /* Size of tvnorm array */
-        v4l2_std_id current_norm; /* Current tvnorm */
-        struct v4l2_tvnorm *tvnorms;
+        v4l2_std_id tvnorms;            /* Supported tv norms */
+        v4l2_std_id current_norm;       /* Current tvnorm */
 
         /* callbacks */
         void (*release)(struct video_device *vfd);
@@ -211,7 +205,7 @@ struct video_device
                 /* Standard handling
                         G_STD and ENUMSTD are handled by videodev.c
                  */
-        int (*vidioc_s_std)    (struct file *file, void *fh, v4l2_std_id a);
+        int (*vidioc_s_std) (struct file *file, void *fh, v4l2_std_id *norm);
         int (*vidioc_querystd) (struct file *file, void *fh, v4l2_std_id *a);
 
                 /* Input handling */
diff --git a/include/net/ax25.h b/include/net/ax25.h
index 69374cd1a857..e1d116f11923 100644
--- a/include/net/ax25.h
+++ b/include/net/ax25.h
@@ -282,15 +282,17 @@ extern void ax25_fillin_cb(ax25_cb *, ax25_dev *);
 extern struct sock *ax25_make_new(struct sock *, struct ax25_dev *);
 
 /* ax25_addr.c */
-extern ax25_address null_ax25_address;
-extern char *ax2asc(char *buf, ax25_address *);
-extern void asc2ax(ax25_address *addr, char *callsign);
-extern int  ax25cmp(ax25_address *, ax25_address *);
-extern int  ax25digicmp(ax25_digi *, ax25_digi *);
-extern unsigned char *ax25_addr_parse(unsigned char *, int, ax25_address *, ax25_address *, ax25_digi *, int *, int *);
-extern int  ax25_addr_build(unsigned char *, ax25_address *, ax25_address *, ax25_digi *, int, int);
-extern int  ax25_addr_size(ax25_digi *);
-extern void ax25_digi_invert(ax25_digi *, ax25_digi *);
+extern const ax25_address ax25_bcast;
+extern const ax25_address ax25_defaddr;
+extern const ax25_address null_ax25_address;
+extern int ax25cmp(const ax25_address *, const ax25_address *);
+extern int ax25digicmp(const ax25_digi *, const ax25_digi *);
+extern const unsigned char *ax25_addr_parse(const unsigned char *, int,
+        ax25_address *, ax25_address *, ax25_digi *, int *, int *);
+extern int  ax25_addr_build(unsigned char *, const ax25_address *,
+        const ax25_address *, const ax25_digi *, int, int);
+extern int  ax25_addr_size(const ax25_digi *);
+extern void ax25_digi_invert(const ax25_digi *, ax25_digi *);
 
 /* ax25_dev.c */
 extern ax25_dev *ax25_dev_list;
diff --git a/include/net/ip.h b/include/net/ip.h
index 83cb9ac5554e..053f02b5cb89 100644
--- a/include/net/ip.h
+++ b/include/net/ip.h
@@ -376,8 +376,7 @@ int ipv4_doint_and_flush(ctl_table *ctl, int write,
                          size_t *lenp, loff_t *ppos);
 int ipv4_doint_and_flush_strategy(ctl_table *table, int __user *name, int nlen,
                                   void __user *oldval, size_t __user *oldlenp,
-                                  void __user *newval, size_t newlen, 
-                                  void **context);
+                                  void __user *newval, size_t newlen);
 #ifdef CONFIG_PROC_FS
 extern int ip_misc_proc_init(void);
 #endif
diff --git a/include/net/irda/ircomm_tty.h b/include/net/irda/ircomm_tty.h
index 87699cb4ef8c..8dabdd603fe1 100644
--- a/include/net/irda/ircomm_tty.h
+++ b/include/net/irda/ircomm_tty.h
@@ -126,7 +126,7 @@ extern int ircomm_tty_tiocmset(struct tty_struct *tty, struct file *file,
 extern int ircomm_tty_ioctl(struct tty_struct *tty, struct file *file, 
                             unsigned int cmd, unsigned long arg);
 extern void ircomm_tty_set_termios(struct tty_struct *tty, 
-                                   struct termios *old_termios);
+                                   struct ktermios *old_termios);
 extern hashbin_t *ircomm_tty;
 
 #endif
diff --git a/include/net/neighbour.h b/include/net/neighbour.h
index 23967031ddb7..3725b93c52f3 100644
--- a/include/net/neighbour.h
+++ b/include/net/neighbour.h
@@ -309,6 +309,24 @@ static inline int neigh_event_send(struct neighbour *neigh, struct sk_buff *skb)
         return 0;
 }
 
+static inline int neigh_hh_output(struct hh_cache *hh, struct sk_buff *skb)
+{
+        unsigned seq;
+        int hh_len;
+
+        do {
+                int hh_alen;
+
+                seq = read_seqbegin(&hh->hh_lock);
+                hh_len = hh->hh_len;
+                hh_alen = HH_DATA_ALIGN(hh_len);
+                memcpy(skb->data - hh_alen, hh->hh_data, hh_alen);
+        } while (read_seqretry(&hh->hh_lock, seq));
+
+        skb_push(skb, hh_len);
+        return hh->hh_output(skb);
+}
+
 static inline struct neighbour *
 __neigh_lookup(struct neigh_table *tbl, const void *pkey, struct net_device *dev, int creat)
 {
diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h
index 215461f18db1..c818f87122af 100644
--- a/include/net/sctp/sctp.h
+++ b/include/net/sctp/sctp.h
@@ -368,7 +368,7 @@ static inline void sctp_sysctl_register(void) { return; }
 static inline void sctp_sysctl_unregister(void) { return; }
 static inline int sctp_sysctl_jiffies_ms(ctl_table *table, int __user *name, int nlen,
                 void __user *oldval, size_t __user *oldlenp,
-                void __user *newval, size_t newlen, void **context) {
+                void __user *newval, size_t newlen) {
         return -ENOSYS;
 }
 #endif
diff --git a/include/video/mbxfb.h b/include/video/mbxfb.h
index 3bde0f5cd55c..20b9002712ef 100644
--- a/include/video/mbxfb.h
+++ b/include/video/mbxfb.h
@@ -1,6 +1,9 @@
 #ifndef __MBX_FB_H
 #define __MBX_FB_H
 
+#include <asm/ioctl.h>
+#include <asm/types.h>
+
 struct mbxfb_val {
         unsigned int    defval;
         unsigned int    min;
@@ -25,4 +28,32 @@ struct mbxfb_platform_data {
                 int (*remove)(struct fb_info *fb);
 };
 
+/* planar */
+#define MBXFB_FMT_YUV12         0
+
+/* packed */
+#define MBXFB_FMT_UY0VY1        1
+#define MBXFB_FMT_VY0UY1        2
+#define MBXFB_FMT_Y0UY1V        3
+#define MBXFB_FMT_Y0VY1U        4
+struct mbxfb_overlaySetup {
+        __u32 enable;
+        __u32 x, y;
+        __u32 width, height;
+        __u32 alpha;
+        __u32 fmt;
+        __u32 mem_offset;
+        __u32 scaled_width;
+        __u32 scaled_height;
+
+        /* Filled by the driver */
+        __u32 U_offset;
+        __u32 V_offset;
+
+        __u16 Y_stride;
+        __u16 UV_stride;
+};
+
+#define MBXFB_IOCX_OVERLAY      _IOWR(0xF4, 0x00,struct mbxfb_overlaySetup)
+
 #endif /* __MBX_FB_H */
diff --git a/include/video/pm3fb.h b/include/video/pm3fb.h
index ac021379ac40..94c7d2da90ea 100644
--- a/include/video/pm3fb.h
+++ b/include/video/pm3fb.h
@@ -607,16 +607,16 @@
 #define PM3FBDestReadModeOr                                     0xac98
         #define PM3FBDestReadMode_ReadDisable                   0<<0
         #define PM3FBDestReadMode_ReadEnable                    1<<0
-        #define PM3FBDestReadMode_StripePitch(sp)       (((sp)&0x7)<<2
-        #define PM3FBDestReadMode_StripeHeight(sh)      (((sh)&0x7)<<7
+        #define PM3FBDestReadMode_StripePitch(sp)       (((sp)&0x7)<<2)
+        #define PM3FBDestReadMode_StripeHeight(sh)      (((sh)&0x7)<<7)
         #define PM3FBDestReadMode_Enable0                       1<<8
         #define PM3FBDestReadMode_Enable1                       1<<9
         #define PM3FBDestReadMode_Enable2                       1<<10
         #define PM3FBDestReadMode_Enable3                       1<<11
-        #define PM3FBDestReadMode_Layout0(l)            (((l)&0x3)<<12
-        #define PM3FBDestReadMode_Layout1(l)            (((l)&0x3)<<14
-        #define PM3FBDestReadMode_Layout2(l)            (((l)&0x3)<<16
-        #define PM3FBDestReadMode_Layout3(l)            (((l)&0x3)<<18
+        #define PM3FBDestReadMode_Layout0(l)            (((l)&0x3)<<12)
+        #define PM3FBDestReadMode_Layout1(l)            (((l)&0x3)<<14)
+        #define PM3FBDestReadMode_Layout2(l)            (((l)&0x3)<<16)
+        #define PM3FBDestReadMode_Layout3(l)            (((l)&0x3)<<18)
         #define PM3FBDestReadMode_Origin0                       1<<20
         #define PM3FBDestReadMode_Origin1                       1<<21
         #define PM3FBDestReadMode_Origin2                       1<<22
@@ -640,16 +640,16 @@
 #define PM3FBSourceReadModeOr                                   0xaca8
         #define PM3FBSourceReadMode_ReadDisable                 (0<<0)
         #define PM3FBSourceReadMode_ReadEnable                  (1<<0)
-        #define PM3FBSourceReadMode_StripePitch(sp)     (((sp)&0x7)<<2
-        #define PM3FBSourceReadMode_StripeHeight(sh)    (((sh)&0x7)<<7
-        #define PM3FBSourceReadMode_Layout(l)           (((l)&0x3)<<8
+        #define PM3FBSourceReadMode_StripePitch(sp)     (((sp)&0x7)<<2)
+        #define PM3FBSourceReadMode_StripeHeight(sh)    (((sh)&0x7)<<7)
+        #define PM3FBSourceReadMode_Layout(l)           (((l)&0x3)<<8)
         #define PM3FBSourceReadMode_Origin                      1<<10
         #define PM3FBSourceReadMode_Blocking                    1<<11
         #define PM3FBSourceReadMode_UserTexelCoord              1<<13
         #define PM3FBSourceReadMode_WrapXEnable                 1<<14
         #define PM3FBSourceReadMode_WrapYEnable                 1<<15
-        #define PM3FBSourceReadMode_WrapX(w)            (((w)&0xf)<<16
-        #define PM3FBSourceReadMode_WrapY(w)            (((w)&0xf)<<20
+        #define PM3FBSourceReadMode_WrapX(w)            (((w)&0xf)<<16)
+        #define PM3FBSourceReadMode_WrapY(w)            (((w)&0xf)<<20)
         #define PM3FBSourceReadMode_ExternalSourceData          1<<24
 #define PM3FBWriteBufferAddr0                                   0xb000
 #define PM3FBWriteBufferAddr1                                   0xb008
@@ -942,7 +942,7 @@
 #define PM3Window                                               0x8980
         #define PM3Window_ForceLBUpdate                         1<<3
         #define PM3Window_LBUpdateSource                        1<<4
-        #define PM3Window_FrameCount(c)                         (((c)&0xff)<<9
+        #define PM3Window_FrameCount(c)                         (((c)&0xff)<<9)
         #define PM3Window_StencilFCP                            1<<17
         #define PM3Window_DepthFCP                              1<<18
         #define PM3Window_OverrideWriteFiltering                1<<19