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-rw-r--r--include/asm-arm/arch-imx/hardware.h8
-rw-r--r--include/asm-arm/arch-imx/imx-uart.h2
-rw-r--r--include/asm-arm/arch-mxc/board-mx27ads.h354
-rw-r--r--include/asm-arm/arch-mxc/board-mx31ads.h5
-rw-r--r--include/asm-arm/arch-mxc/board-mx31lite.h38
-rw-r--r--include/asm-arm/arch-mxc/board-pcm037.h27
-rw-r--r--include/asm-arm/arch-mxc/board-pcm038.h41
-rw-r--r--include/asm-arm/arch-mxc/clock.h67
-rw-r--r--include/asm-arm/arch-mxc/common.h6
-rw-r--r--include/asm-arm/arch-mxc/debug-macro.S49
-rw-r--r--include/asm-arm/arch-mxc/gpio.h42
-rw-r--r--include/asm-arm/arch-mxc/hardware.h38
-rw-r--r--include/asm-arm/arch-mxc/iim.h77
-rw-r--r--include/asm-arm/arch-mxc/imx-uart.h32
-rw-r--r--include/asm-arm/arch-mxc/iomux-mx1-mx2.h372
-rw-r--r--include/asm-arm/arch-mxc/iomux-mx3.h501
-rw-r--r--include/asm-arm/arch-mxc/irqs.h13
-rw-r--r--include/asm-arm/arch-mxc/mx27.h302
-rw-r--r--include/asm-arm/arch-mxc/mx31.h21
-rw-r--r--include/asm-arm/arch-mxc/mxc.h152
-rw-r--r--include/asm-arm/arch-mxc/mxc_timer.h158
21 files changed, 2131 insertions, 174 deletions
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
index adffb6acf42a..6542ca5e8c33 100644
--- a/include/asm-arm/arch-imx/hardware.h
+++ b/include/asm-arm/arch-imx/hardware.h
@@ -73,14 +73,6 @@
73 */ 73 */
74extern void imx_gpio_mode( int gpio_mode ); 74extern void imx_gpio_mode( int gpio_mode );
75 75
76/* get frequencies in Hz */
77extern unsigned int imx_get_system_clk(void);
78extern unsigned int imx_get_mcu_clk(void);
79extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
80extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12] */
81extern unsigned int imx_get_perclk3(void); /* SSI */
82extern unsigned int imx_get_hclk(void); /* SDRAM, CSI, Memory Stick,*/
83 /* I2C, DMA */
84#endif 76#endif
85 77
86#define MAXIRQNUM 62 78#define MAXIRQNUM 62
diff --git a/include/asm-arm/arch-imx/imx-uart.h b/include/asm-arm/arch-imx/imx-uart.h
index 3a685e1780ea..d54eb1d48026 100644
--- a/include/asm-arm/arch-imx/imx-uart.h
+++ b/include/asm-arm/arch-imx/imx-uart.h
@@ -4,6 +4,8 @@
4#define IMXUART_HAVE_RTSCTS (1<<0) 4#define IMXUART_HAVE_RTSCTS (1<<0)
5 5
6struct imxuart_platform_data { 6struct imxuart_platform_data {
7 int (*init)(struct platform_device *pdev);
8 void (*exit)(struct platform_device *pdev);
7 unsigned int flags; 9 unsigned int flags;
8}; 10};
9 11
diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/include/asm-arm/arch-mxc/board-mx27ads.h
new file mode 100644
index 000000000000..61e66dac90ef
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx27ads.h
@@ -0,0 +1,354 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
16
17/* external interrupt multiplexer */
18#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
19
20#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
21#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
22#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
23#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
24
25#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
26 MXC_MAX_VIRTUAL_INTS)
27
28/*
29 * MXC UART EVB board level configurations
30 */
31
32#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
33#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
34#define MXC_LL_EXTUART_16BIT_BUS
35
36#define MXC_LL_UART_PADDR UART1_BASE_ADDR
37#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
38
39/*
40 * @name Memory Size parameters
41 */
42
43/*
44 * Size of SDRAM memory
45 */
46#define SDRAM_MEM_SIZE SZ_128M
47
48/*
49 * PBC Controller parameters
50 */
51
52/*
53 * Base address of PBC controller, CS4
54 */
55#define PBC_BASE_ADDRESS 0xEB000000
56#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset))
57
58/*
59 * PBC Interupt name definitions
60 */
61#define PBC_GPIO1_0 0
62#define PBC_GPIO1_1 1
63#define PBC_GPIO1_2 2
64#define PBC_GPIO1_3 3
65#define PBC_GPIO1_4 4
66#define PBC_GPIO1_5 5
67
68#define PBC_INTR_MAX_NUM 6
69#define PBC_INTR_SHARED_MAX_NUM 8
70
71/* When the PBC address connection is fixed in h/w, defined as 1 */
72#define PBC_ADDR_SH 0
73
74/* Offsets for the PBC Controller register */
75/*
76 * PBC Board version register offset
77 */
78#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
79/*
80 * PBC Board control register 1 set address.
81 */
82#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
83/*
84 * PBC Board control register 1 clear address.
85 */
86#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
87/*
88 * PBC Board control register 2 set address.
89 */
90#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
91/*
92 * PBC Board control register 2 clear address.
93 */
94#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
95/*
96 * PBC Board control register 3 set address.
97 */
98#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
99/*
100 * PBC Board control register 3 clear address.
101 */
102#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
103/*
104 * PBC Board control register 3 set address.
105 */
106#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
107/*
108 * PBC Board control register 4 clear address.
109 */
110#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
111/*PBC_ADDR_SH
112 * PBC Board status register 1.
113 */
114#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
115/*
116 * PBC Board interrupt status register.
117 */
118#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
119/*
120 * PBC Board interrupt current status register.
121 */
122#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
123/*
124 * PBC Interrupt mask register set address.
125 */
126#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
127/*
128 * PBC Interrupt mask register clear address.
129 */
130#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
131/*
132 * External UART A.
133 */
134#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
135/*
136 * UART 4 Expanding Signal Status.
137 */
138#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
139/*
140 * UART 4 Expanding Signal Control Set.
141 */
142#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
143/*
144 * UART 4 Expanding Signal Control Clear.
145 */
146#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
147/*
148 * Ethernet Controller IO base address.
149 */
150#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
151/*
152 * Ethernet Controller Memory base address.
153 */
154#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
155/*
156 * Ethernet Controller DMA base address.
157 */
158#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
159
160/* PBC Board Version Register bit definition */
161#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
162#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
163
164/* PBC Board Control Register 1 bit definitions */
165#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
166#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
167#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
168#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
169#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
170
171/* PBC Board Control Register 2 bit definitions */
172#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
173#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
174#define PBC_BCTRL2_ATAFEC_EN 0X0010
175#define PBC_BCTRL2_ATAFEC_SEL 0X0020
176#define PBC_BCTRL2_ATA_EN 0X0040
177#define PBC_BCTRL2_IRDA_SD 0X0080
178#define PBC_BCTRL2_IRDA_EN 0X0100
179#define PBC_BCTRL2_CCTL10 0X0200
180#define PBC_BCTRL2_CCTL11 0X0400
181
182/* PBC Board Control Register 3 bit definitions */
183#define PBC_BCTRL3_HSH_EN 0X0020
184#define PBC_BCTRL3_FSH_MOD 0X0040
185#define PBC_BCTRL3_OTG_HS_EN 0X0080
186#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
187#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
188#define PBC_BCTRL3_USB_OTG_ON 0X0800
189#define PBC_BCTRL3_USB_FSH_ON 0X1000
190
191/* PBC Board Control Register 4 bit definitions */
192#define PBC_BCTRL4_REGEN_SEL 0X0001
193#define PBC_BCTRL4_USER_OFF 0X0002
194#define PBC_BCTRL4_VIB_EN 0X0004
195#define PBC_BCTRL4_PWRGT1_EN 0X0008
196#define PBC_BCTRL4_PWRGT2_EN 0X0010
197#define PBC_BCTRL4_STDBY_PRI 0X0020
198
199#ifndef __ASSEMBLY__
200/*
201 * Enumerations for SD cards and memory stick card. This corresponds to
202 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
203 */
204enum mxc_card_no {
205 MXC_CARD_SD2 = 0,
206 MXC_CARD_SD3,
207 MXC_CARD_MS,
208 MXC_CARD_SD1,
209 MXC_CARD_MIN = MXC_CARD_SD2,
210 MXC_CARD_MAX = MXC_CARD_SD1,
211};
212#endif
213
214#define MXC_CPLD_VER_1_50 0x01
215
216/*
217 * PBC BSTAT Register bit definitions
218 */
219#define PBC_BSTAT_PRI_INT 0X0001
220#define PBC_BSTAT_USB_BYP 0X0002
221#define PBC_BSTAT_ATA_IOCS16 0X0004
222#define PBC_BSTAT_ATA_CBLID 0X0008
223#define PBC_BSTAT_ATA_DASP 0X0010
224#define PBC_BSTAT_PWR_RDY 0X0020
225#define PBC_BSTAT_SD3_WP 0X0100
226#define PBC_BSTAT_SD2_WP 0X0200
227#define PBC_BSTAT_SD1_WP 0X0400
228#define PBC_BSTAT_SD3_DET 0X0800
229#define PBC_BSTAT_SD2_DET 0X1000
230#define PBC_BSTAT_SD1_DET 0X2000
231#define PBC_BSTAT_MS_DET 0X4000
232#define PBC_BSTAT_SD3_DET_BIT 11
233#define PBC_BSTAT_SD2_DET_BIT 12
234#define PBC_BSTAT_SD1_DET_BIT 13
235#define PBC_BSTAT_MS_DET_BIT 14
236#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
237 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
238 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
239 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
240 0x0))))
241
242/*
243 * PBC UART Control Register bit definitions
244 */
245#define PBC_UCTRL_DCE_DCD 0X0001
246#define PBC_UCTRL_DCE_DSR 0X0002
247#define PBC_UCTRL_DCE_RI 0X0004
248#define PBC_UCTRL_DTE_DTR 0X0100
249
250/*
251 * PBC UART Status Register bit definitions
252 */
253#define PBC_USTAT_DTE_DCD 0X0001
254#define PBC_USTAT_DTE_DSR 0X0002
255#define PBC_USTAT_DTE_RI 0X0004
256#define PBC_USTAT_DCE_DTR 0X0100
257
258/*
259 * PBC Interupt mask register bit definitions
260 */
261#define PBC_INTR_SD3_R_EN_BIT 4
262#define PBC_INTR_SD2_R_EN_BIT 0
263#define PBC_INTR_SD1_R_EN_BIT 6
264#define PBC_INTR_MS_R_EN_BIT 5
265#define PBC_INTR_SD3_EN_BIT 13
266#define PBC_INTR_SD2_EN_BIT 12
267#define PBC_INTR_MS_EN_BIT 14
268#define PBC_INTR_SD1_EN_BIT 15
269
270#define PBC_INTR_SD2_R_EN 0x0001
271#define PBC_INTR_LOW_BAT 0X0002
272#define PBC_INTR_OTG_FSOVER 0X0004
273#define PBC_INTR_FSH_OVER 0X0008
274#define PBC_INTR_SD3_R_EN 0x0010
275#define PBC_INTR_MS_R_EN 0x0020
276#define PBC_INTR_SD1_R_EN 0x0040
277#define PBC_INTR_FEC_INT 0X0080
278#define PBC_INTR_ENET_INT 0X0100
279#define PBC_INTR_OTGFS_INT 0X0200
280#define PBC_INTR_XUART_INT 0X0400
281#define PBC_INTR_CCTL12 0X0800
282#define PBC_INTR_SD2_EN 0x1000
283#define PBC_INTR_SD3_EN 0x2000
284#define PBC_INTR_MS_EN 0x4000
285#define PBC_INTR_SD1_EN 0x8000
286
287
288
289/* For interrupts like xuart, enet etc */
290#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
291#define MXC_MAX_EXP_IO_LINES 16
292
293/*
294 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
295 *
296 */
297#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
298#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
299#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
300#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
301#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
302#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
303#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
304#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
305#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
306#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
307#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
308#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
309#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
310#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
311#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
312
313/*
314 * This is System IRQ used by CS8900A for interrupt generation
315 * taken from platform.h
316 */
317#define CS8900AIRQ EXPIO_INT_ENET_INT
318/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
319#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
320
321#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
322
323/*
324* This is used to detect if the CPLD version is for mx27 evb board rev-a
325*/
326#define PBC_CPLD_VERSION_IS_REVA() \
327 ((__raw_readw(PBC_VERSION_REG) & \
328 (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
329 == 0)
330
331/* This is used to active or inactive ata signal in CPLD .
332 * It is dependent with hardware
333 */
334#define PBC_ATA_SIGNAL_ACTIVE() \
335 __raw_writew( \
336 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
337 PBC_BCTRL2_CLEAR_REG)
338
339#define PBC_ATA_SIGNAL_INACTIVE() \
340 __raw_writew( \
341 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
342 PBC_BCTRL2_SET_REG)
343
344#define MXC_BD_LED1 (1 << 5)
345#define MXC_BD_LED2 (1 << 6)
346#define MXC_BD_LED_ON(led) \
347 __raw_writew(led, PBC_BCTRL1_SET_REG)
348#define MXC_BD_LED_OFF(led) \
349 __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
350
351/* to determine the correct external crystal reference */
352#define CKIH_27MHZ_BIT_SET (1 << 3)
353
354#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index 8590127760a8..1bc6fb0f9a83 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -109,4 +109,9 @@
109 109
110#define MXC_MAX_EXP_IO_LINES 16 110#define MXC_MAX_EXP_IO_LINES 16
111 111
112/* mandatory for CONFIG_LL_DEBUG */
113
114#define MXC_LL_UART_PADDR UART1_BASE_ADDR
115#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
116
112#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ 117#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31lite.h b/include/asm-arm/arch-mxc/board-mx31lite.h
new file mode 100644
index 000000000000..e4e5cf5ad7db
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31lite.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
12#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
13
14#define MXC_MAX_EXP_IO_LINES 16
15
16
17/*
18 * Memory Size parameters
19 */
20
21/*
22 * Size of SDRAM memory
23 */
24#define SDRAM_MEM_SIZE SZ_128M
25/*
26 * Size of MBX buffer memory
27 */
28#define MXC_MBX_MEM_SIZE SZ_16M
29/*
30 * Size of memory available to kernel
31 */
32#define MEM_SIZE (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
33
34#define MXC_LL_UART_PADDR UART1_BASE_ADDR
35#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
36
37#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
38
diff --git a/include/asm-arm/arch-mxc/board-pcm037.h b/include/asm-arm/arch-mxc/board-pcm037.h
new file mode 100644
index 000000000000..82232ba3c8fc
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm037.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
20#define __ASM_ARCH_MXC_BOARD_PCM037_H__
21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
26
27#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/include/asm-arm/arch-mxc/board-pcm038.h b/include/asm-arm/arch-mxc/board-pcm038.h
new file mode 100644
index 000000000000..750c62afd90f
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm038.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
20#define __ASM_ARCH_MXC_BOARD_PCM038_H__
21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
26
27#ifndef __ASSEMBLY__
28/*
29 * This CPU module needs a baseboard to work. After basic initializing
30 * its own devices, it calls baseboard's init function.
31 * TODO: Add your own baseboard init function and call it from
32 * inside pcm038_init().
33 *
34 * This example here is for the development board. Refer pcm970-baseboard.c
35 */
36
37extern void pcm970_baseboard_init(void);
38
39#endif
40
41#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/include/asm-arm/arch-mxc/clock.h b/include/asm-arm/arch-mxc/clock.h
new file mode 100644
index 000000000000..24caa2b7c91d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/clock.h
@@ -0,0 +1,67 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_CLOCK_H__
21#define __ASM_ARCH_MXC_CLOCK_H__
22
23#ifndef __ASSEMBLY__
24#include <linux/list.h>
25
26struct module;
27
28struct clk {
29 struct list_head node;
30 struct module *owner;
31 const char *name;
32 int id;
33 /* Source clock this clk depends on */
34 struct clk *parent;
35 /* Secondary clock to enable/disable with this clock */
36 struct clk *secondary;
37 /* Reference count of clock enable/disable */
38 __s8 usecount;
39 /* Register bit position for clock's enable/disable control. */
40 u8 enable_shift;
41 /* Register address for clock's enable/disable control. */
42 u32 enable_reg;
43 u32 flags;
44 /* get the current clock rate (always a fresh value) */
45 unsigned long (*get_rate) (struct clk *);
46 /* Function ptr to set the clock to a new rate. The rate must match a
47 supported rate returned from round_rate. Leave blank if clock is not
48 programmable */
49 int (*set_rate) (struct clk *, unsigned long);
50 /* Function ptr to round the requested clock rate to the nearest
51 supported rate that is less than or equal to the requested rate. */
52 unsigned long (*round_rate) (struct clk *, unsigned long);
53 /* Function ptr to enable the clock. Leave blank if clock can not
54 be gated. */
55 int (*enable) (struct clk *);
56 /* Function ptr to disable the clock. Leave blank if clock can not
57 be gated. */
58 void (*disable) (struct clk *);
59 /* Function ptr to set the parent clock of the clock. */
60 int (*set_parent) (struct clk *, struct clk *);
61};
62
63int clk_register(struct clk *clk);
64void clk_unregister(struct clk *clk);
65
66#endif /* __ASSEMBLY__ */
67#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
index 23b4350edbd6..a6d2e24aab15 100644
--- a/include/asm-arm/arch-mxc/common.h
+++ b/include/asm-arm/arch-mxc/common.h
@@ -11,10 +11,10 @@
11#ifndef __ASM_ARCH_MXC_COMMON_H__ 11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__ 12#define __ASM_ARCH_MXC_COMMON_H__
13 13
14struct sys_timer;
15
16extern void mxc_map_io(void); 14extern void mxc_map_io(void);
17extern void mxc_init_irq(void); 15extern void mxc_init_irq(void);
18extern struct sys_timer mxc_timer; 16extern void mxc_timer_init(const char *clk_timer);
17extern int mxc_clocks_init(unsigned long fref);
18extern int mxc_register_gpios(void);
19 19
20#endif 20#endif
diff --git a/include/asm-arm/arch-mxc/debug-macro.S b/include/asm-arm/arch-mxc/debug-macro.S
new file mode 100644
index 000000000000..575087f8561a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/debug-macro.S
@@ -0,0 +1,49 @@
1/* linux/include/asm-arm/arch-imx/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <asm/arch/hardware.h>
15
16#ifdef CONFIG_MACH_MX31ADS
17#include <asm/arch/board-mx31ads.h>
18#endif
19#ifdef CONFIG_MACH_PCM037
20#include <asm/arch/board-pcm037.h>
21#endif
22#ifdef CONFIG_MACH_MX31LITE
23#include <asm/arch/board-mx31lite.h>
24#endif
25#ifdef CONFIG_MACH_MX27ADS
26#include <asm/arch/board-mx27ads.h>
27#endif
28#ifdef CONFIG_MACH_PCM038
29#include <asm/arch/board-pcm038.h>
30#endif
31 .macro addruart,rx
32 mrc p15, 0, \rx, c1, c0
33 tst \rx, #1 @ MMU enabled?
34 ldreq \rx, =MXC_LL_UART_PADDR @ physical
35 ldrne \rx, =MXC_LL_UART_VADDR @ virtual
36 .endm
37
38 .macro senduart,rd,rx
39 str \rd, [\rx, #0x40] @ TXDATA
40 .endm
41
42 .macro waituart,rd,rx
43 .endm
44
45 .macro busyuart,rd,rx
461002: ldr \rd, [\rx, #0x98] @ SR2
47 tst \rd, #1 << 3 @ TXDC
48 beq 1002b @ wait until transmit done
49 .endm
diff --git a/include/asm-arm/arch-mxc/gpio.h b/include/asm-arm/arch-mxc/gpio.h
new file mode 100644
index 000000000000..d393e15f5a6b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/gpio.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_GPIO_H__
20#define __ASM_ARCH_MXC_GPIO_H__
21
22#include <asm/hardware.h>
23#include <asm-generic/gpio.h>
24
25/* use gpiolib dispatchers */
26#define gpio_get_value __gpio_get_value
27#define gpio_set_value __gpio_set_value
28#define gpio_cansleep __gpio_cansleep
29
30#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio))
31#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES)
32
33struct mxc_gpio_port {
34 void __iomem *base;
35 int irq;
36 int virtual_irq_start;
37 struct gpio_chip chip;
38};
39
40int mxc_gpio_init(struct mxc_gpio_port*, int);
41
42#endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index e87ff0679d5e..37cddbaaade7 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -1,11 +1,20 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 4 *
5/* 5 * This program is free software; you can redistribute it and/or
6 * This program is free software; you can redistribute it and/or modify 6 * modify it under the terms of the GNU General Public License
7 * it under the terms of the GNU General Public License version 2 as 7 * as published by the Free Software Foundation; either version 2
8 * published by the Free Software Foundation. 8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
9 */ 18 */
10 19
11#ifndef __ASM_ARCH_MXC_HARDWARE_H__ 20#ifndef __ASM_ARCH_MXC_HARDWARE_H__
@@ -17,15 +26,12 @@
17# include <asm/arch/mx31.h> 26# include <asm/arch/mx31.h>
18#endif 27#endif
19 28
20#include <asm/arch/mxc.h> 29#ifdef CONFIG_ARCH_MX2
21 30# ifdef CONFIG_MACH_MX27
22/* 31# include <asm/arch/mx27.h>
23 * --------------------------------------------------------------------------- 32# endif
24 * Board specific defines
25 * ---------------------------------------------------------------------------
26 */
27#ifdef CONFIG_MACH_MX31ADS
28# include <asm/arch/board-mx31ads.h>
29#endif 33#endif
30 34
35#include <asm/arch/mxc.h>
36
31#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 37#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/iim.h b/include/asm-arm/arch-mxc/iim.h
new file mode 100644
index 000000000000..315bffadafda
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iim.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_IIM_H__
21#define __ASM_ARCH_MXC_IIM_H__
22
23/* Register offsets */
24#define MXC_IIMSTAT 0x0000
25#define MXC_IIMSTATM 0x0004
26#define MXC_IIMERR 0x0008
27#define MXC_IIMEMASK 0x000C
28#define MXC_IIMFCTL 0x0010
29#define MXC_IIMUA 0x0014
30#define MXC_IIMLA 0x0018
31#define MXC_IIMSDAT 0x001C
32#define MXC_IIMPREV 0x0020
33#define MXC_IIMSREV 0x0024
34#define MXC_IIMPRG_P 0x0028
35#define MXC_IIMSCS0 0x002C
36#define MXC_IIMSCS1 0x0030
37#define MXC_IIMSCS2 0x0034
38#define MXC_IIMSCS3 0x0038
39#define MXC_IIMFBAC0 0x0800
40#define MXC_IIMJAC 0x0804
41#define MXC_IIMHWV1 0x0808
42#define MXC_IIMHWV2 0x080C
43#define MXC_IIMHAB0 0x0810
44#define MXC_IIMHAB1 0x0814
45/* Definitions for i.MX27 TO2 */
46#define MXC_IIMMAC 0x0814
47#define MXC_IIMPREV_FUSE 0x0818
48#define MXC_IIMSREV_FUSE 0x081C
49#define MXC_IIMSJC_CHALL_0 0x0820
50#define MXC_IIMSJC_CHALL_7 0x083C
51#define MXC_IIMFB0UC17 0x0840
52#define MXC_IIMFB0UC255 0x0BFC
53#define MXC_IIMFBAC1 0x0C00
54/* Definitions for i.MX27 TO2 */
55#define MXC_IIMSUID 0x0C04
56#define MXC_IIMKEY0 0x0C04
57#define MXC_IIMKEY20 0x0C54
58#define MXC_IIMSJC_RESP_0 0x0C58
59#define MXC_IIMSJC_RESP_7 0x0C74
60#define MXC_IIMFB1UC30 0x0C78
61#define MXC_IIMFB1UC255 0x0FFC
62
63/* Bit definitions */
64
65#define MXC_IIMHWV1_WLOCK (0x1 << 7)
66#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6)
67#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5)
68#define MXC_IIMHWV1_BOOT_INT (0x1 << 4)
69#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3)
70#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2)
71#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1)
72
73#define MXC_IIMHWV2_WLOCK (0x1 << 7)
74#define MXC_IIMHWV2_BP_SDMA (0x1 << 6)
75#define MXC_IIMHWV2_SCM_DCM (0x1 << 5)
76
77#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/include/asm-arm/arch-mxc/imx-uart.h b/include/asm-arm/arch-mxc/imx-uart.h
new file mode 100644
index 000000000000..83fb72c4048a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/imx-uart.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef ASMARM_ARCH_UART_H
20#define ASMARM_ARCH_UART_H
21
22#define IMXUART_HAVE_RTSCTS (1<<0)
23
24struct imxuart_platform_data {
25 int (*init)(struct platform_device *pdev);
26 int (*exit)(struct platform_device *pdev);
27 unsigned int flags;
28};
29
30int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
31
32#endif
diff --git a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
new file mode 100644
index 000000000000..076d37b38eb2
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
@@ -0,0 +1,372 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef _MXC_GPIO_MX1_MX2_H
20#define _MXC_GPIO_MX1_MX2_H
21
22#include <linux/io.h>
23
24#define MXC_GPIO_ALLOC_MODE_NORMAL 0
25#define MXC_GPIO_ALLOC_MODE_NO_ALLOC 1
26#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC 2
27#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY 4
28#define MXC_GPIO_ALLOC_MODE_RELEASE 8
29
30/*
31 * GPIO Module and I/O Multiplexer
32 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
33 */
34#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
35#define MXC_DDIR(x) (0x00 + ((x) << 8))
36#define MXC_OCR1(x) (0x04 + ((x) << 8))
37#define MXC_OCR2(x) (0x08 + ((x) << 8))
38#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
39#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
40#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
41#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
42#define MXC_DR(x) (0x1c + ((x) << 8))
43#define MXC_GIUS(x) (0x20 + ((x) << 8))
44#define MXC_SSR(x) (0x24 + ((x) << 8))
45#define MXC_ICR1(x) (0x28 + ((x) << 8))
46#define MXC_ICR2(x) (0x2c + ((x) << 8))
47#define MXC_IMR(x) (0x30 + ((x) << 8))
48#define MXC_ISR(x) (0x34 + ((x) << 8))
49#define MXC_GPR(x) (0x38 + ((x) << 8))
50#define MXC_SWR(x) (0x3c + ((x) << 8))
51#define MXC_PUEN(x) (0x40 + ((x) << 8))
52
53#ifdef CONFIG_ARCH_MX1
54# define GPIO_PORT_MAX 3
55#endif
56#ifdef CONFIG_ARCH_MX2
57# define GPIO_PORT_MAX 5
58#endif
59
60#ifndef GPIO_PORT_MAX
61# error "GPIO config port count unknown!"
62#endif
63
64#define GPIO_PIN_MASK 0x1f
65
66#define GPIO_PORT_SHIFT 5
67#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
68
69#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
70#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
71#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
72#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
73#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
74#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
75
76#define GPIO_OUT (1 << 8)
77#define GPIO_IN (0 << 8)
78#define GPIO_PUEN (1 << 9)
79
80#define GPIO_PF (1 << 10)
81#define GPIO_AF (1 << 11)
82
83#define GPIO_OCR_SHIFT 12
84#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
85#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
86#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
87#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
88#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
89
90#define GPIO_AOUT_SHIFT 14
91#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
92#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
93#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
94#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
95#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
96
97#define GPIO_BOUT_SHIFT 16
98#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
99#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
100#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
101#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
102#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
103
104extern void mxc_gpio_mode(int gpio_mode);
105extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
106 int alloc_mode, const char *label);
107
108/*-------------------------------------------------------------------------*/
109
110/* assignements for GPIO alternate/primary functions */
111
112/* FIXME: This list is not completed. The correct directions are
113 * missing on some (many) pins
114 */
115#ifdef CONFIG_ARCH_MX1
116#define PA0_AIN_SPI2_CLK (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0)
117#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
118#define PA1_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1)
119#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
120#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
121#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
122#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
123#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
124#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
125#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
126#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
127#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
128#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
129#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
130#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
131#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
132#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
133#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
134#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
135#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
136#define PA17_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17)
137#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
138#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
139#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
140#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
141#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
142#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
143#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
144#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
145#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
146#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
147#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
148#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
149#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
150#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
151#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
152#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
153#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
154#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
155#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
156#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
157#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
158#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
159#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
160#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
161#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
162#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
163#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
164#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
165#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
166#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
167#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
168#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
169#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
170#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
171#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
172#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
173#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
174#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
175#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
176#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
177#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
178#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
179#define PB22_PFUSBD_RCV (GPIO_PORTB | GPIO_PF | 22)
180#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
181#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
182#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
183#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
184#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
185#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
186#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
187#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
188#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
189#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
190#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
191#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
192#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
193#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
194#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
195#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
196#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
197#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
198#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
199#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
200#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
201#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
202#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
203#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
204#define PC24_BIN_UART3_RI (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
205#define PC25_BIN_UART3_DSR (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
206#define PC26_AOUT_UART3_DTR (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26)
207#define PC27_BIN_UART3_DCD (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
208#define PC28_BIN_UART3_CTS (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
209#define PC29_AOUT_UART3_RTS (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29)
210#define PC30_BIN_UART3_TX (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30)
211#define PC31_AOUT_UART3_RX (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
212#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
213#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
214#define PD7_AF_UART2_DTR (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
215#define PD7_AIN_SPI2_SCLK (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7)
216#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
217#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
218#define PD8_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8)
219#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
220#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
221#define PD9_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9)
222#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
223#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
224#define PD10_AIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10)
225#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
226#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
227#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
228#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
229#define PD15_PF_LD0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
230#define PD16_PF_LD1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
231#define PD17_PF_LD2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
232#define PD18_PF_LD3 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
233#define PD19_PF_LD4 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
234#define PD20_PF_LD5 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
235#define PD21_PF_LD6 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
236#define PD22_PF_LD7 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
237#define PD23_PF_LD8 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
238#define PD24_PF_LD9 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
239#define PD25_PF_LD10 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
240#define PD26_PF_LD11 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
241#define PD27_PF_LD12 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
242#define PD28_PF_LD13 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
243#define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
244#define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
245#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
246#define PD31_BIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31)
247#endif
248
249#ifdef CONFIG_ARCH_MX2
250#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
251#define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
252#define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
253#define PA8_PF_LD2 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
254#define PA9_PF_LD3 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
255#define PA10_PF_LD4 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
256#define PA11_PF_LD5 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
257#define PA12_PF_LD6 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
258#define PA13_PF_LD7 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
259#define PA14_PF_LD8 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
260#define PA15_PF_LD9 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
261#define PA16_PF_LD10 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
262#define PA17_PF_LD11 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
263#define PA18_PF_LD12 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
264#define PA19_PF_LD13 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
265#define PA20_PF_LD14 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
266#define PA21_PF_LD15 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
267#define PA22_PF_LD16 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
268#define PA23_PF_LD17 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
269#define PA24_PF_REV (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
270#define PA25_PF_CLS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
271#define PA26_PF_PS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
272#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
273#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
274#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
275#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
276#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
277#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
278#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
279#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
280#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 11)
281#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
282#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
283#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
284#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 13)
285#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
286#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
287#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
288#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
289#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
290#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
291#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
292#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 19)
293#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
294#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
295#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
296#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21)
297#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26)
298#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
299#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
300#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31)
301#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
302#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6)
303#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16)
304#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17)
305#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18)
306#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 19)
307#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 20)
308#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 21)
309#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 22)
310#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 23)
311#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 24)
312#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 25)
313#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 26)
314#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 27)
315#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 28)
316#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 29)
317#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 30)
318#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 31)
319#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
320#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
321#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
322#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
323#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
324#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
325#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
326#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
327#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
328#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
329#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
330#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
331#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
332#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
333#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
334#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
335#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
336#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
337#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
338#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
339#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
340#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
341#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
342#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
343#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30)
344#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31)
345#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
346#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
347#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
348#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
349#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
350#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
351#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
352#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
353#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
354#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
355#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
356#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
357#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
358#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18)
359#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
360#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
361#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
362#endif
363
364/* decode irq number to use with IMR(x), ISR(x) and friends */
365#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
366
367#define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x)
368#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
369#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
370#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
371
372#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/include/asm-arm/arch-mxc/iomux-mx3.h
new file mode 100644
index 000000000000..7509e7692f08
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx3.h
@@ -0,0 +1,501 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_MX31_IOMUX_H__
21#define __MACH_MX31_IOMUX_H__
22
23#include <linux/types.h>
24
25/*
26 * various IOMUX output functions
27 */
28
29#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
30#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
31#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
32#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
33#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
34#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
35#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
36#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
37#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
38#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
39#define IOMUX_ICONFIG_FUNC 2 /* used as function */
40#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
41#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
42
43#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
44#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
45#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
46#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
47
48/*
49 * various IOMUX pad functions
50 */
51enum iomux_pad_config {
52 PAD_CTL_NOLOOPBACK = 0x0 << 9,
53 PAD_CTL_LOOPBACK = 0x1 << 9,
54 PAD_CTL_PKE_NONE = 0x0 << 8,
55 PAD_CTL_PKE_ENABLE = 0x1 << 8,
56 PAD_CTL_PUE_KEEPER = 0x0 << 7,
57 PAD_CTL_PUE_PUD = 0x1 << 7,
58 PAD_CTL_100K_PD = 0x0 << 5,
59 PAD_CTL_100K_PU = 0x1 << 5,
60 PAD_CTL_47K_PU = 0x2 << 5,
61 PAD_CTL_22K_PU = 0x3 << 5,
62 PAD_CTL_HYS_CMOS = 0x0 << 4,
63 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
64 PAD_CTL_ODE_CMOS = 0x0 << 3,
65 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
66 PAD_CTL_DRV_NORMAL = 0x0 << 1,
67 PAD_CTL_DRV_HIGH = 0x1 << 1,
68 PAD_CTL_DRV_MAX = 0x2 << 1,
69 PAD_CTL_SRE_SLOW = 0x0 << 0,
70 PAD_CTL_SRE_FAST = 0x1 << 0
71};
72
73/*
74 * various IOMUX general purpose functions
75 */
76enum iomux_gp_func {
77 MUX_PGP_FIRI = 1 << 0,
78 MUX_DDR_MODE = 1 << 1,
79 MUX_PGP_CSPI_BB = 1 << 2,
80 MUX_PGP_ATA_1 = 1 << 3,
81 MUX_PGP_ATA_2 = 1 << 4,
82 MUX_PGP_ATA_3 = 1 << 5,
83 MUX_PGP_ATA_4 = 1 << 6,
84 MUX_PGP_ATA_5 = 1 << 7,
85 MUX_PGP_ATA_6 = 1 << 8,
86 MUX_PGP_ATA_7 = 1 << 9,
87 MUX_PGP_ATA_8 = 1 << 10,
88 MUX_PGP_UH2 = 1 << 11,
89 MUX_SDCTL_CSD0_SEL = 1 << 12,
90 MUX_SDCTL_CSD1_SEL = 1 << 13,
91 MUX_CSPI1_UART3 = 1 << 14,
92 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
93 MUX_TAMPER_DETECT_EN = 1 << 16,
94 MUX_PGP_USB_4WIRE = 1 << 17,
95 MUX_PGB_USB_COMMON = 1 << 18,
96 MUX_SDHC_MEMSTICK1 = 1 << 19,
97 MUX_SDHC_MEMSTICK2 = 1 << 20,
98 MUX_PGP_SPLL_BYP = 1 << 21,
99 MUX_PGP_UPLL_BYP = 1 << 22,
100 MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
101 MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
102 MUX_CSPI3_UART5_SEL = 1 << 25,
103 MUX_PGP_ATA_9 = 1 << 26,
104 MUX_PGP_USB_SUSPEND = 1 << 27,
105 MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
106 MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
107 MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
108 MUX_CLKO_DDR_MODE = 1 << 31,
109};
110
111/*
112 * This function enables/disables the general purpose function for a particular
113 * signal.
114 */
115void iomux_config_gpr(enum iomux_gp_func , bool);
116
117/*
118 * set the mode for a IOMUX pin.
119 */
120int mxc_iomux_mode(unsigned int);
121
122/*
123 * This function enables/disables the general purpose function for a particular
124 * signal.
125 */
126void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
127
128#define IOMUX_PADNUM_MASK 0x1ff
129#define IOMUX_GPIONUM_SHIFT 9
130#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
131#define IOMUX_MODE_SHIFT 17
132#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
133
134#define IOMUX_PIN(gpionum, padnum) \
135 (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
136 (padnum & IOMUX_PADNUM_MASK))
137
138#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
139
140#define IOMUX_TO_GPIO(iomux_pin) \
141 ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
142#define IOMUX_TO_IRQ(iomux_pin) \
143 (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
144 MXC_GPIO_INT_BASE)
145
146/*
147 * This enumeration is constructed based on the Section
148 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
149 * value is constructed based on the rules described above.
150 */
151
152enum iomux_pins {
153 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
154 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
155 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
156 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
157 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
158 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
159 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
160 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
161 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
162 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
163 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
164 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
165 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
166 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
167 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
168 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
169 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
170 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
171 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
172 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
173 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
174 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
175 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
176 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
177 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
178 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
179 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
180 MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
181 MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
182 MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
183 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
184 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
185 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
186 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
187 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
188 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
189 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
190 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
191 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
192 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
193 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
194 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
195 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
196 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
197 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
198 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
199 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
200 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
201 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
202 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
203 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
204 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
205 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
206 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
207 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
208 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
209 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
210 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
211 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
212 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
213 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
214 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
215 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
216 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
217 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
218 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
219 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
220 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
221 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
222 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
223 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
224 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
225 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
226 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
227 MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
228 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
229 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
230 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
231 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
232 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
233 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
234 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
235 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
236 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
237 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
238 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
239 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
240 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
241 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
242 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
243 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
244 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
245 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
246 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
247 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
248 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
249 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
250 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
251 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
252 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
253 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
254 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
255 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
256 MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
257 MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
258 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
259 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
260 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
261 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
262 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
263 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
264 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
265 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
266 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
267 MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
268 MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
269 MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
270 MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
271 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
272 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
273 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
274 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
275 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
276 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
277 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
278 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
279 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
280 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
281 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
282 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
283 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
284 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
285 MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
286 MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
287 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
288 MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
289 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
290 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
291 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
292 MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
293 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
294 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
295 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
296 MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
297 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
298 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
299 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
300 MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
301 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
302 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
303 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
304 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
305 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
306 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
307 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
308 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
309 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
310 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
311 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
312 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
313 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
314 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
315 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
316 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
317 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
318 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
319 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
320 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
321 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
322 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
323 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
324 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
325 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
326 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
327 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
328 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
329 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
330 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
331 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
332 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
333 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
334 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
335 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
336 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
337 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
338 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
339 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
340 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
341 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
342 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
343 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
344 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
345 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
346 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
347 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
348 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
349 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
350 MX31_PIN_NFRB = IOMUX_PIN(16, 197),
351 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
352 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
353 MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
354 MX31_PIN_NFALE = IOMUX_PIN(12, 201),
355 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
356 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
357 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
358 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
359 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
360 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
361 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
362 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
363 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
364 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
365 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
366 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
367 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
368 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
369 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
370 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
371 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
372 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
373 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
374 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
375 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
376 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
377 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
378 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
379 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
380 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
381 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
382 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
383 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
384 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
385 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
386 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
387 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
388 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
389 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
390 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
391 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
392 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
393 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
394 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
395 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
396 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
397 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
398 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
399 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
400 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
401 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
402 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
403 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
404 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
405 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
406 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
407 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
408 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
409 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
410 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
411 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
412 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
413 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
414 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
415 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
416 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
417 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
418 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
419 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
420 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
421 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
422 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
423 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
424 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
425 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
426 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
427 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
428 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
429 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
430 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
431 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
432 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
433 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
434 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
435 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
436 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
437 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
438 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
439 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
440 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
441 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
442 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
443 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
444 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
445 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
446 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
447 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
448 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
449 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
450 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
451 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
452 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
453 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
454 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
455 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
456 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
457 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
458 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
459 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
460 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
461 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
462 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
463 MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
464 MX31_PIN_STX0 = IOMUX_PIN(33, 311),
465 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
466 MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
467 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
468 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
469 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
470 MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317),
471 MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318),
472 MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319),
473 MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320),
474 MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321),
475 MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322),
476 MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323),
477 MX31_PIN_PWMO = IOMUX_PIN( 9, 324),
478 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
479 MX31_PIN_COMPARE = IOMUX_PIN( 8, 326),
480 MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327),
481};
482
483/*
484 * Convenience values for use with mxc_iomux_mode()
485 *
486 * Format here is MX31_PIN_(pin name)__(function)
487 */
488#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
489#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
490#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
491#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
492#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
493#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
494
495/*
496 * This function configures the pad value for a IOMUX pin.
497 */
498void mxc_iomux_set_pad(enum iomux_pins, u32);
499
500#endif
501
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index b2c5205e1962..f416130718cf 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,17 +13,4 @@
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
17
18#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
19#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
20
21/* Number of normal interrupts */
22#define NR_IRQS (MXC_MAX_INT_LINES + \
23 MXC_MAX_GPIO_LINES + \
24 MXC_MAX_VIRTUAL_INTS)
25
26/* Number of fast interrupts */
27#define NR_FIQS MXC_MAX_INTS
28
29#endif /* __ASM_ARCH_MXC_IRQS_H__ */ 16#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/mx27.h b/include/asm-arm/arch-mxc/mx27.h
new file mode 100644
index 000000000000..212ecc246626
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx27.h
@@ -0,0 +1,302 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_MX27_H__
21#define __ASM_ARCH_MXC_MX27_H__
22
23#ifndef __ASM_ARCH_MXC_HARDWARE_H__
24#error "Do not include directly."
25#endif
26
27/* IRAM */
28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
29
30/* Register offests */
31#define AIPI_BASE_ADDR 0x10000000
32#define AIPI_BASE_ADDR_VIRT 0xF4000000
33#define AIPI_SIZE SZ_1M
34
35#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
36#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
37#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
38#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
39#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
40#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
41#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
42#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
43#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
44#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
45#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
46#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
47#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
48#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
49#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
50#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
51#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
52#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
53#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
54#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
55#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
56#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
57
58#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
59#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
60#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
61#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
62#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000)
63#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000)
64#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
65#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
66#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
67
68#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
69#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
70#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
71#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
72/* for mx27*/
73#define OTG_BASE_ADDR USBOTG_BASE_ADDR
74#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
75#define EMMA_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
76#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
77#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
78#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
79
80#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
81#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
82#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
83#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
84#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
85
86#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
87#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
88
89/* ROMP and AVIC */
90#define ROMP_BASE_ADDR 0x10041000
91
92#define AVIC_BASE_ADDR 0x10040000
93
94#define SAHB1_BASE_ADDR 0x80000000
95#define SAHB1_BASE_ADDR_VIRT 0xF4100000
96#define SAHB1_SIZE SZ_1M
97
98#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
99#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
100
101/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
102#define X_MEMC_BASE_ADDR 0xD8000000
103#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
104#define X_MEMC_SIZE SZ_1M
105
106#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
107#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
108#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
109#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
110#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
111
112/* Memory regions and CS */
113#define SDRAM_BASE_ADDR 0xA0000000
114#define CSD1_BASE_ADDR 0xB0000000
115
116#define CS0_BASE_ADDR 0xC0000000
117#define CS1_BASE_ADDR 0xC8000000
118#define CS2_BASE_ADDR 0xD0000000
119#define CS3_BASE_ADDR 0xD2000000
120#define CS4_BASE_ADDR 0xD4000000
121#define CS5_BASE_ADDR 0xD6000000
122#define PCMCIA_MEM_BASE_ADDR 0xDC000000
123
124/*
125 * This macro defines the physical to virtual address mapping for all the
126 * peripheral modules. It is used by passing in the physical address as x
127 * and returning the virtual address. If the physical address is not mapped,
128 * it returns 0xDEADBEEF
129 */
130#define IO_ADDRESS(x) \
131 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
132 AIPI_IO_ADDRESS(x) : \
133 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
134 SAHB1_IO_ADDRESS(x) : \
135 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
136 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
137
138/* define the address mapping macros: in physical address order */
139#define AIPI_IO_ADDRESS(x) \
140 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
141
142#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
143
144#define SAHB1_IO_ADDRESS(x) \
145 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
146
147#define CS4_IO_ADDRESS(x) \
148 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
149
150#define X_MEMC_IO_ADDRESS(x) \
151 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
152
153#define PCMCIA_IO_ADDRESS(x) \
154 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
155
156/* fixed interrput numbers */
157#define MXC_INT_CCM 63
158#define MXC_INT_IIM 62
159#define MXC_INT_LCDC 61
160#define MXC_INT_SLCDC 60
161#define MXC_INT_SAHARA 59
162#define MXC_INT_SCC_SCM 58
163#define MXC_INT_SCC_SMN 57
164#define MXC_INT_USB3 56
165#define MXC_INT_USB2 55
166#define MXC_INT_USB1 54
167#define MXC_INT_VPU 53
168#define MXC_INT_EMMAPP 52
169#define MXC_INT_EMMAPRP 51
170#define MXC_INT_FEC 50
171#define MXC_INT_UART5 49
172#define MXC_INT_UART6 48
173#define MXC_INT_DMACH15 47
174#define MXC_INT_DMACH14 46
175#define MXC_INT_DMACH13 45
176#define MXC_INT_DMACH12 44
177#define MXC_INT_DMACH11 43
178#define MXC_INT_DMACH10 42
179#define MXC_INT_DMACH9 41
180#define MXC_INT_DMACH8 40
181#define MXC_INT_DMACH7 39
182#define MXC_INT_DMACH6 38
183#define MXC_INT_DMACH5 37
184#define MXC_INT_DMACH4 36
185#define MXC_INT_DMACH3 35
186#define MXC_INT_DMACH2 34
187#define MXC_INT_DMACH1 33
188#define MXC_INT_DMACH0 32
189#define MXC_INT_CSI 31
190#define MXC_INT_ATA 30
191#define MXC_INT_NANDFC 29
192#define MXC_INT_PCMCIA 28
193#define MXC_INT_WDOG 27
194#define MXC_INT_GPT1 26
195#define MXC_INT_GPT2 25
196#define MXC_INT_GPT3 24
197#define MXC_INT_GPT INT_GPT1
198#define MXC_INT_PWM 23
199#define MXC_INT_RTC 22
200#define MXC_INT_KPP 21
201#define MXC_INT_UART1 20
202#define MXC_INT_UART2 19
203#define MXC_INT_UART3 18
204#define MXC_INT_UART4 17
205#define MXC_INT_CSPI1 16
206#define MXC_INT_CSPI2 15
207#define MXC_INT_SSI1 14
208#define MXC_INT_SSI2 13
209#define MXC_INT_I2C 12
210#define MXC_INT_SDHC1 11
211#define MXC_INT_SDHC2 10
212#define MXC_INT_SDHC3 9
213#define MXC_INT_GPIO 8
214#define MXC_INT_SDHC 7
215#define MXC_INT_CSPI3 6
216#define MXC_INT_RTIC 5
217#define MXC_INT_GPT4 4
218#define MXC_INT_GPT5 3
219#define MXC_INT_GPT6 2
220#define MXC_INT_I2C2 1
221
222/* fixed DMA request numbers */
223#define DMA_REQ_NFC 37
224#define DMA_REQ_SDHC3 36
225#define DMA_REQ_UART6_RX 35
226#define DMA_REQ_UART6_TX 34
227#define DMA_REQ_UART5_RX 33
228#define DMA_REQ_UART5_TX 32
229#define DMA_REQ_CSI_RX 31
230#define DMA_REQ_CSI_STAT 30
231#define DMA_REQ_ATA_RCV 29
232#define DMA_REQ_ATA_TX 28
233#define DMA_REQ_UART1_TX 27
234#define DMA_REQ_UART1_RX 26
235#define DMA_REQ_UART2_TX 25
236#define DMA_REQ_UART2_RX 24
237#define DMA_REQ_UART3_TX 23
238#define DMA_REQ_UART3_RX 22
239#define DMA_REQ_UART4_TX 21
240#define DMA_REQ_UART4_RX 20
241#define DMA_REQ_CSPI1_TX 19
242#define DMA_REQ_CSPI1_RX 18
243#define DMA_REQ_CSPI2_TX 17
244#define DMA_REQ_CSPI2_RX 16
245#define DMA_REQ_SSI1_TX1 15
246#define DMA_REQ_SSI1_RX1 14
247#define DMA_REQ_SSI1_TX0 13
248#define DMA_REQ_SSI1_RX0 12
249#define DMA_REQ_SSI2_TX1 11
250#define DMA_REQ_SSI2_RX1 10
251#define DMA_REQ_SSI2_TX0 9
252#define DMA_REQ_SSI2_RX0 8
253#define DMA_REQ_SDHC1 7
254#define DMA_REQ_SDHC2 6
255#define DMA_REQ_MSHC 4
256#define DMA_REQ_EXT 3
257#define DMA_REQ_CSPI3_TX 2
258#define DMA_REQ_CSPI3_RX 1
259
260/* silicon revisions specific to i.MX27 */
261#define CHIP_REV_1_0 0x00
262#define CHIP_REV_2_0 0x01
263
264#ifndef __ASSEMBLY__
265extern int mx27_revision(void);
266#endif
267
268/* gpio and gpio based interrupt handling */
269#define GPIO_DR 0x1C
270#define GPIO_GDIR 0x00
271#define GPIO_PSR 0x24
272#define GPIO_ICR1 0x28
273#define GPIO_ICR2 0x2C
274#define GPIO_IMR 0x30
275#define GPIO_ISR 0x34
276#define GPIO_INT_LOW_LEV 0x3
277#define GPIO_INT_HIGH_LEV 0x2
278#define GPIO_INT_RISE_EDGE 0x0
279#define GPIO_INT_FALL_EDGE 0x1
280#define GPIO_INT_NONE 0x4
281
282/* Mandatory defines used globally */
283
284/* this is an i.MX27 CPU */
285#define cpu_is_mx27() (1)
286
287/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
288#define ARCH_NR_GPIOS (192 + 16)
289
290/* OS clock tick rate */
291#define CLOCK_TICK_RATE 13300000
292
293/* Start of RAM */
294#define PHYS_OFFSET SDRAM_BASE_ADDR
295
296/* max interrupt lines count */
297#define NR_IRQS 256
298
299/* count of internal interrupt sources */
300#define MXC_MAX_INT_LINES 64
301
302#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 36a1af495bb3..a7373e4a56cb 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -320,6 +320,8 @@
320#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) 320#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
321#define MXC_MAX_VIRTUAL_INTS 16 321#define MXC_MAX_VIRTUAL_INTS 16
322 322
323#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
324
323/*! 325/*!
324 * Number of GPIO port as defined in the IC Spec 326 * Number of GPIO port as defined in the IC Spec
325 */ 327 */
@@ -347,6 +349,25 @@
347#define SYSTEM_REV_MIN CHIP_REV_1_0 349#define SYSTEM_REV_MIN CHIP_REV_1_0
348#define SYSTEM_REV_NUM 3 350#define SYSTEM_REV_NUM 3
349 351
352/* gpio and gpio based interrupt handling */
353#define GPIO_DR 0x00
354#define GPIO_GDIR 0x04
355#define GPIO_PSR 0x08
356#define GPIO_ICR1 0x0C
357#define GPIO_ICR2 0x10
358#define GPIO_IMR 0x14
359#define GPIO_ISR 0x18
360#define GPIO_INT_LOW_LEV 0x0
361#define GPIO_INT_HIGH_LEV 0x1
362#define GPIO_INT_RISE_EDGE 0x2
363#define GPIO_INT_FALL_EDGE 0x3
364#define GPIO_INT_NONE 0x4
365
366/* Mandatory defines used globally */
367
368/* this CPU supports up to 96 GPIOs */
369#define ARCH_NR_GPIOS 96
370
350#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 371#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
351 372
352/* this is a i.MX31 CPU */ 373/* this is a i.MX31 CPU */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a..332eda4dbd3b 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 4 *
5/* 5 * This program is free software; you can redistribute it and/or
6 * This program is free software; you can redistribute it and/or modify 6 * modify it under the terms of the GNU General Public License
7 * it under the terms of the GNU General Public License version 2 as 7 * as published by the Free Software Foundation; either version 2
8 * published by the Free Software Foundation. 8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
9 */ 18 */
10 19
11#ifndef __ASM_ARCH_MXC_H__ 20#ifndef __ASM_ARCH_MXC_H__
@@ -20,133 +29,8 @@
20# define cpu_is_mx31() (0) 29# define cpu_is_mx31() (0)
21#endif 30#endif
22 31
23/* 32#ifndef CONFIG_MACH_MX27
24 ***************************************** 33# define cpu_is_mx27() (0)
25 * GPT Register definitions * 34#endif
26 *****************************************
27 */
28#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
29#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
30#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
31#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
32#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
33#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
34#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
35#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
36#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
37#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
38
39/* GPT Control register bit definitions */
40#define GPTCR_FO3 (1 << 31)
41#define GPTCR_FO2 (1 << 30)
42#define GPTCR_FO1 (1 << 29)
43
44#define GPTCR_OM3_SHIFT 26
45#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
46#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
47#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
48#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
49#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
50#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
51
52#define GPTCR_OM2_SHIFT 23
53#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
54#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
55#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
56#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
57#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
58#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
59
60#define GPTCR_OM1_SHIFT 20
61#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
62#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
63#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
64#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
65#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
66#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
67
68#define GPTCR_IM2_SHIFT 18
69#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
70#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
71#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
72#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
73#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
74
75#define GPTCR_IM1_SHIFT 16
76#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
77#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
78#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
79#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
80#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
81
82#define GPTCR_SWR (1 << 15)
83#define GPTCR_FRR (1 << 9)
84
85#define GPTCR_CLKSRC_SHIFT 6
86#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
87#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
88#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
89#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
90#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
91
92#define GPTCR_STOPEN (1 << 5)
93#define GPTCR_DOZEN (1 << 4)
94#define GPTCR_WAITEN (1 << 3)
95#define GPTCR_DBGEN (1 << 2)
96
97#define GPTCR_ENMOD (1 << 1)
98#define GPTCR_ENABLE (1 << 0)
99
100#define GPTSR_OF1 (1 << 0)
101#define GPTSR_OF2 (1 << 1)
102#define GPTSR_OF3 (1 << 2)
103#define GPTSR_IF1 (1 << 3)
104#define GPTSR_IF2 (1 << 4)
105#define GPTSR_ROV (1 << 5)
106
107#define GPTIR_OF1IE GPTSR_OF1
108#define GPTIR_OF2IE GPTSR_OF2
109#define GPTIR_OF3IE GPTSR_OF3
110#define GPTIR_IF1IE GPTSR_IF1
111#define GPTIR_IF2IE GPTSR_IF2
112#define GPTIR_ROVIE GPTSR_ROV
113
114/*
115 *****************************************
116 * AVIC Registers *
117 *****************************************
118 */
119#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
120#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
121#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
122#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
123#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
124#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
125#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
126#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
127#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
128#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
129#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
130#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
131#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
132#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
133#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
134#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
135#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
136#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
137#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
138#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
139#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
140#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
141#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
142#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
143#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
144#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
145#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
146
147#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
148#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
149#define IIM_PROD_REV_SH 3
150#define IIM_PROD_REV_LEN 5
151 35
152#endif /* __ASM_ARCH_MXC_H__ */ 36#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
new file mode 100644
index 000000000000..6cb11f4f1a06
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc_timer.h
@@ -0,0 +1,158 @@
1/*
2 * mxc_timer.h
3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 *
6 * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 * Boston, MA 02110-1301, USA.
21 */
22
23#ifndef __PLAT_MXC_TIMER_H
24#define __PLAT_MXC_TIMER_H
25
26#include <linux/clk.h>
27#include <asm/hardware.h>
28
29#ifdef CONFIG_ARCH_IMX
30#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
31#define TIMER_INTERRUPT TIM1_INT
32
33#define TCTL_VAL TCTL_CLK_PCLK1
34#define TCTL_IRQEN (1<<4)
35#define TCTL_FRR (1<<8)
36#define TCTL_CLK_PCLK1 (1<<1)
37#define TCTL_CLK_PCLK1_4 (2<<1)
38#define TCTL_CLK_TIN (3<<1)
39#define TCTL_CLK_32 (4<<1)
40
41#define MXC_TCTL 0x00
42#define MXC_TPRER 0x04
43#define MXC_TCMP 0x08
44#define MXC_TCR 0x0c
45#define MXC_TCN 0x10
46#define MXC_TSTAT 0x14
47#define TSTAT_CAPT (1<<1)
48#define TSTAT_COMP (1<<0)
49
50static inline void gpt_irq_disable(void)
51{
52 unsigned int tmp;
53
54 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
55 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
56}
57
58static inline void gpt_irq_enable(void)
59{
60 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
61 TIMER_BASE + MXC_TCTL);
62}
63
64static void gpt_irq_acknowledge(void)
65{
66 __raw_writel(0, TIMER_BASE + MXC_TSTAT);
67}
68#endif /* CONFIG_ARCH_IMX */
69
70#ifdef CONFIG_ARCH_MX2
71#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
72#define TIMER_INTERRUPT MXC_INT_GPT1
73
74#define MXC_TCTL 0x00
75#define TCTL_VAL TCTL_CLK_PCLK1
76#define TCTL_CLK_PCLK1 (1<<1)
77#define TCTL_CLK_PCLK1_4 (2<<1)
78#define TCTL_IRQEN (1<<4)
79#define TCTL_FRR (1<<8)
80#define MXC_TPRER 0x04
81#define MXC_TCMP 0x08
82#define MXC_TCR 0x0c
83#define MXC_TCN 0x10
84#define MXC_TSTAT 0x14
85#define TSTAT_CAPT (1<<1)
86#define TSTAT_COMP (1<<0)
87
88static inline void gpt_irq_disable(void)
89{
90 unsigned int tmp;
91
92 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
93 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
94}
95
96static inline void gpt_irq_enable(void)
97{
98 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
99 TIMER_BASE + MXC_TCTL);
100}
101
102static void gpt_irq_acknowledge(void)
103{
104 __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
105}
106#endif /* CONFIG_ARCH_MX2 */
107
108#ifdef CONFIG_ARCH_MX3
109#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
110#define TIMER_INTERRUPT MXC_INT_GPT
111
112#define MXC_TCTL 0x00
113#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN)
114#define TCTL_CLK_IPG (1<<6)
115#define TCTL_FRR (1<<9)
116#define TCTL_WAITEN (1<<3)
117
118#define MXC_TPRER 0x04
119#define MXC_TSTAT 0x08
120#define TSTAT_OF1 (1<<0)
121#define TSTAT_OF2 (1<<1)
122#define TSTAT_OF3 (1<<2)
123#define TSTAT_IF1 (1<<3)
124#define TSTAT_IF2 (1<<4)
125#define TSTAT_ROV (1<<5)
126#define MXC_IR 0x0c
127#define MXC_TCMP 0x10
128#define MXC_TCMP2 0x14
129#define MXC_TCMP3 0x18
130#define MXC_TCR 0x1c
131#define MXC_TCN 0x24
132
133static inline void gpt_irq_disable(void)
134{
135 __raw_writel(0, TIMER_BASE + MXC_IR);
136}
137
138static inline void gpt_irq_enable(void)
139{
140 __raw_writel(1<<0, TIMER_BASE + MXC_IR);
141}
142
143static inline void gpt_irq_acknowledge(void)
144{
145 __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
146}
147#endif /* CONFIG_ARCH_MX3 */
148
149#define TCTL_SWR (1<<15)
150#define TCTL_CC (1<<10)
151#define TCTL_OM (1<<9)
152#define TCTL_CAP_RIS (1<<6)
153#define TCTL_CAP_FAL (2<<6)
154#define TCTL_CAP_RIS_FAL (3<<6)
155#define TCTL_CAP_ENA (1<<5)
156#define TCTL_TEN (1<<0)
157
158#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 13:04:36 -0500