diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/acpi/actbl.h | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h index c55939e344a0..aed49a5d5838 100644 --- a/include/acpi/actbl.h +++ b/include/acpi/actbl.h | |||
| @@ -56,7 +56,7 @@ | |||
| 56 | #define ACPI_SIG_RSDT "RSDT" /* Root System Description Table */ | 56 | #define ACPI_SIG_RSDT "RSDT" /* Root System Description Table */ |
| 57 | #define ACPI_SIG_XSDT "XSDT" /* Extended System Description Table */ | 57 | #define ACPI_SIG_XSDT "XSDT" /* Extended System Description Table */ |
| 58 | #define ACPI_SIG_SSDT "SSDT" /* Secondary System Description Table */ | 58 | #define ACPI_SIG_SSDT "SSDT" /* Secondary System Description Table */ |
| 59 | #define ACPI_RSDP_NAME "RSDP" | 59 | #define ACPI_RSDP_NAME "RSDP" /* Short name for RSDP, not signature */ |
| 60 | 60 | ||
| 61 | /* | 61 | /* |
| 62 | * All tables and structures must be byte-packed to match the ACPI | 62 | * All tables and structures must be byte-packed to match the ACPI |
| @@ -185,55 +185,55 @@ struct acpi_table_fadt { | |||
| 185 | struct acpi_table_header header; /* Common ACPI table header */ | 185 | struct acpi_table_header header; /* Common ACPI table header */ |
| 186 | u32 facs; /* 32-bit physical address of FACS */ | 186 | u32 facs; /* 32-bit physical address of FACS */ |
| 187 | u32 dsdt; /* 32-bit physical address of DSDT */ | 187 | u32 dsdt; /* 32-bit physical address of DSDT */ |
| 188 | u8 model; /* System Interrupt Model (ACPI 1.0) not used in ACPI 2.0+ */ | 188 | u8 model; /* System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */ |
| 189 | u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */ | 189 | u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */ |
| 190 | u16 sci_interrupt; /* System vector of SCI interrupt */ | 190 | u16 sci_interrupt; /* System vector of SCI interrupt */ |
| 191 | u32 smi_command; /* Port address of SMI command port */ | 191 | u32 smi_command; /* 32-bit Port address of SMI command port */ |
| 192 | u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */ | 192 | u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */ |
| 193 | u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */ | 193 | u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */ |
| 194 | u8 S4bios_request; /* Value to write to SMI CMD to enter S4BIOS state */ | 194 | u8 S4bios_request; /* Value to write to SMI CMD to enter S4BIOS state */ |
| 195 | u8 pstate_control; /* Processor performance state control */ | 195 | u8 pstate_control; /* Processor performance state control */ |
| 196 | u32 pm1a_event_block; /* Port address of Power Mgt 1a Event Reg Blk */ | 196 | u32 pm1a_event_block; /* 32-bit Port address of Power Mgt 1a Event Reg Blk */ |
| 197 | u32 pm1b_event_block; /* Port address of Power Mgt 1b Event Reg Blk */ | 197 | u32 pm1b_event_block; /* 32-bit Port address of Power Mgt 1b Event Reg Blk */ |
| 198 | u32 pm1a_control_block; /* Port address of Power Mgt 1a Control Reg Blk */ | 198 | u32 pm1a_control_block; /* 32-bit Port address of Power Mgt 1a Control Reg Blk */ |
| 199 | u32 pm1b_control_block; /* Port address of Power Mgt 1b Control Reg Blk */ | 199 | u32 pm1b_control_block; /* 32-bit Port address of Power Mgt 1b Control Reg Blk */ |
| 200 | u32 pm2_control_block; /* Port address of Power Mgt 2 Control Reg Blk */ | 200 | u32 pm2_control_block; /* 32-bit Port address of Power Mgt 2 Control Reg Blk */ |
| 201 | u32 pm_timer_block; /* Port address of Power Mgt Timer Ctrl Reg Blk */ | 201 | u32 pm_timer_block; /* 32-bit Port address of Power Mgt Timer Ctrl Reg Blk */ |
| 202 | u32 gpe0_block; /* Port addr of General Purpose Event 0 Reg Blk */ | 202 | u32 gpe0_block; /* 32-bit Port address of General Purpose Event 0 Reg Blk */ |
| 203 | u32 gpe1_block; /* Port addr of General Purpose Event 1 Reg Blk */ | 203 | u32 gpe1_block; /* 32-bit Port address of General Purpose Event 1 Reg Blk */ |
| 204 | u8 pm1_event_length; /* Byte Length of ports at pm1_x_evt_blk */ | 204 | u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */ |
| 205 | u8 pm1_control_length; /* Byte Length of ports at pm1_x_cnt_blk */ | 205 | u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */ |
| 206 | u8 pm2_control_length; /* Byte Length of ports at pm2_cnt_blk */ | 206 | u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */ |
| 207 | u8 pm_timer_length; /* Byte Length of ports at pm_tmr_blk */ | 207 | u8 pm_timer_length; /* Byte Length of ports at pm_timer_block */ |
| 208 | u8 gpe0_block_length; /* Byte Length of ports at gpe0_blk */ | 208 | u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */ |
| 209 | u8 gpe1_block_length; /* Byte Length of ports at gpe1_blk */ | 209 | u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */ |
| 210 | u8 gpe1_base; /* Offset in gpe model where gpe1 events start */ | 210 | u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */ |
| 211 | u8 cst_control; /* Support for the _CST object and C States change notification. */ | 211 | u8 cst_control; /* Support for the _CST object and C States change notification */ |
| 212 | u16 C2latency; /* Worst case HW latency to enter/exit C2 state */ | 212 | u16 C2latency; /* Worst case HW latency to enter/exit C2 state */ |
| 213 | u16 C3latency; /* Worst case HW latency to enter/exit C3 state */ | 213 | u16 C3latency; /* Worst case HW latency to enter/exit C3 state */ |
| 214 | u16 flush_size; /* Processor's memory cache line width, in bytes */ | 214 | u16 flush_size; /* Processor's memory cache line width, in bytes */ |
| 215 | u16 flush_stride; /* Number of flush strides that need to be read */ | 215 | u16 flush_stride; /* Number of flush strides that need to be read */ |
| 216 | u8 duty_offset; /* Processor's duty cycle index in processor's P_CNT reg */ | 216 | u8 duty_offset; /* Processor duty cycle index in processor's P_CNT reg */ |
| 217 | u8 duty_width; /* Processor's duty cycle value bit width in P_CNT register. */ | 217 | u8 duty_width; /* Processor duty cycle value bit width in P_CNT register. */ |
| 218 | u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */ | 218 | u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */ |
| 219 | u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */ | 219 | u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */ |
| 220 | u8 century; /* Index to century in RTC CMOS RAM */ | 220 | u8 century; /* Index to century in RTC CMOS RAM */ |
| 221 | u16 boot_flags; /* IA-PC Boot Architecture Flags. See Table 5-10 for description */ | 221 | u16 boot_flags; /* IA-PC Boot Architecture Flags. See Table 5-10 for description */ |
| 222 | u8 reserved; /* Reserved, must be zero */ | 222 | u8 reserved; /* Reserved, must be zero */ |
| 223 | u32 flags; /* Miscellaneous flag bits */ | 223 | u32 flags; /* Miscellaneous flag bits (see below for individual flags) */ |
| 224 | struct acpi_generic_address reset_register; /* Reset register address in GAS format */ | 224 | struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */ |
| 225 | u8 reset_value; /* Value to write to the reset_register port to reset the system */ | 225 | u8 reset_value; /* Value to write to the reset_register port to reset the system */ |
| 226 | u8 reserved4[3]; /* These three bytes must be zero */ | 226 | u8 reserved4[3]; /* Reserved, must be zero */ |
| 227 | u64 Xfacs; /* 64-bit physical address of FACS */ | 227 | u64 Xfacs; /* 64-bit physical address of FACS */ |
| 228 | u64 Xdsdt; /* 64-bit physical address of DSDT */ | 228 | u64 Xdsdt; /* 64-bit physical address of DSDT */ |
| 229 | struct acpi_generic_address xpm1a_event_block; /* Extended Power Mgt 1a Event Reg Blk address */ | 229 | struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ |
| 230 | struct acpi_generic_address xpm1b_event_block; /* Extended Power Mgt 1b Event Reg Blk address */ | 230 | struct acpi_generic_address xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */ |
| 231 | struct acpi_generic_address xpm1a_control_block; /* Extended Power Mgt 1a Control Reg Blk address */ | 231 | struct acpi_generic_address xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */ |
| 232 | struct acpi_generic_address xpm1b_control_block; /* Extended Power Mgt 1b Control Reg Blk address */ | 232 | struct acpi_generic_address xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */ |
| 233 | struct acpi_generic_address xpm2_control_block; /* Extended Power Mgt 2 Control Reg Blk address */ | 233 | struct acpi_generic_address xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */ |
| 234 | struct acpi_generic_address xpm_timer_block; /* Extended Power Mgt Timer Ctrl Reg Blk address */ | 234 | struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ |
| 235 | struct acpi_generic_address xgpe0_block; /* Extended General Purpose Event 0 Reg Blk address */ | 235 | struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */ |
| 236 | struct acpi_generic_address xgpe1_block; /* Extended General Purpose Event 1 Reg Blk address */ | 236 | struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */ |
| 237 | }; | 237 | }; |
| 238 | 238 | ||
| 239 | /* FADT flags */ | 239 | /* FADT flags */ |