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-rw-r--r--include/video/radeon.h23
1 files changed, 17 insertions, 6 deletions
diff --git a/include/video/radeon.h b/include/video/radeon.h
index 099ffa5e5bee..d5dcaf154ba4 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -386,7 +386,7 @@
386#define SC_BOTTOM_RIGHT 0x16F0 386#define SC_BOTTOM_RIGHT 0x16F0
387#define SRC_SC_BOTTOM_RIGHT 0x16F4 387#define SRC_SC_BOTTOM_RIGHT 0x16F4
388#define RB2D_DSTCACHE_MODE 0x3428 388#define RB2D_DSTCACHE_MODE 0x3428
389#define RB2D_DSTCACHE_CTLSTAT 0x342C 389#define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */
390#define LVDS_GEN_CNTL 0x02d0 390#define LVDS_GEN_CNTL 0x02d0
391#define LVDS_PLL_CNTL 0x02d4 391#define LVDS_PLL_CNTL 0x02d4
392#define FP2_GEN_CNTL 0x0288 392#define FP2_GEN_CNTL 0x0288
@@ -525,6 +525,9 @@
525#define CRTC_DISPLAY_DIS (1 << 10) 525#define CRTC_DISPLAY_DIS (1 << 10)
526#define CRTC_CRT_ON (1 << 15) 526#define CRTC_CRT_ON (1 << 15)
527 527
528/* DSTCACHE_MODE bits constants */
529#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8)
530#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17)
528 531
529/* DSTCACHE_CTLSTAT bit constants */ 532/* DSTCACHE_CTLSTAT bit constants */
530#define RB2D_DC_FLUSH_2D (1 << 0) 533#define RB2D_DC_FLUSH_2D (1 << 0)
@@ -532,6 +535,9 @@
532#define RB2D_DC_FLUSH_ALL (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D) 535#define RB2D_DC_FLUSH_ALL (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D)
533#define RB2D_DC_BUSY (1 << 31) 536#define RB2D_DC_BUSY (1 << 31)
534 537
538/* DSTCACHE_MODE bits constants */
539#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8)
540#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17)
535 541
536/* CRTC_GEN_CNTL bit constants */ 542/* CRTC_GEN_CNTL bit constants */
537#define CRTC_DBL_SCAN_EN 0x00000001 543#define CRTC_DBL_SCAN_EN 0x00000001
@@ -863,15 +869,10 @@
863#define GMC_DST_16BPP_YVYU422 0x00000c00 869#define GMC_DST_16BPP_YVYU422 0x00000c00
864#define GMC_DST_32BPP_AYUV444 0x00000e00 870#define GMC_DST_32BPP_AYUV444 0x00000e00
865#define GMC_DST_16BPP_ARGB4444 0x00000f00 871#define GMC_DST_16BPP_ARGB4444 0x00000f00
866#define GMC_SRC_MONO 0x00000000
867#define GMC_SRC_MONO_LBKGD 0x00001000
868#define GMC_SRC_DSTCOLOR 0x00003000
869#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 872#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
870#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 873#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
871#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 874#define GMC_DP_CONVERSION_TEMP_9300 0x00008000
872#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 875#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
873#define GMC_DP_SRC_RECT 0x02000000
874#define GMC_DP_SRC_HOST 0x03000000
875#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 876#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
876#define GMC_3D_FCN_EN_CLR 0x00000000 877#define GMC_3D_FCN_EN_CLR 0x00000000
877#define GMC_3D_FCN_EN_SET 0x08000000 878#define GMC_3D_FCN_EN_SET 0x08000000
@@ -882,6 +883,9 @@
882#define GMC_WRITE_MASK_LEAVE 0x00000000 883#define GMC_WRITE_MASK_LEAVE 0x00000000
883#define GMC_WRITE_MASK_SET 0x40000000 884#define GMC_WRITE_MASK_SET 0x40000000
884#define GMC_CLR_CMP_CNTL_DIS (1 << 28) 885#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
886#define GMC_SRC_DATATYPE_MASK (3 << 12)
887#define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
888#define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
885#define GMC_SRC_DATATYPE_COLOR (3 << 12) 889#define GMC_SRC_DATATYPE_COLOR (3 << 12)
886#define ROP3_S 0x00cc0000 890#define ROP3_S 0x00cc0000
887#define ROP3_SRCCOPY 0x00cc0000 891#define ROP3_SRCCOPY 0x00cc0000
@@ -890,6 +894,7 @@
890#define DP_SRC_SOURCE_MASK (7 << 24) 894#define DP_SRC_SOURCE_MASK (7 << 24)
891#define GMC_BRUSH_NONE (15 << 4) 895#define GMC_BRUSH_NONE (15 << 4)
892#define DP_SRC_SOURCE_MEMORY (2 << 24) 896#define DP_SRC_SOURCE_MEMORY (2 << 24)
897#define DP_SRC_SOURCE_HOST_DATA (3 << 24)
893#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 898#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
894 899
895/* DP_MIX bit constants */ 900/* DP_MIX bit constants */
@@ -975,6 +980,12 @@
975#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) 980#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
976#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) 981#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
977 982
983/* RBBM_GUICNTL constants */
984#define RBBM_GUICNTL_HOST_DATA_SWAP_NONE (0 << 0)
985#define RBBM_GUICNTL_HOST_DATA_SWAP_16BIT (1 << 0)
986#define RBBM_GUICNTL_HOST_DATA_SWAP_32BIT (2 << 0)
987#define RBBM_GUICNTL_HOST_DATA_SWAP_HDW (3 << 0)
988
978/* masks */ 989/* masks */
979 990
980#define CONFIG_MEMSIZE_MASK 0x1f000000 991#define CONFIG_MEMSIZE_MASK 0x1f000000