5 files changed, 126 insertions, 38 deletions

diff --git a/include/uapi/drm/armada_drm.h b/include/uapi/drm/armada_drm.h
new file mode 100644
index 000000000000..8dec3fdc99c7
--- /dev/null
+++ b/include/uapi/drm/armada_drm.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2012 Russell King
+ *  With inspiration from the i915 driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DRM_ARMADA_IOCTL_H
+#define DRM_ARMADA_IOCTL_H
+
+#define DRM_ARMADA_GEM_CREATE           0x00
+#define DRM_ARMADA_GEM_MMAP             0x02
+#define DRM_ARMADA_GEM_PWRITE           0x03
+
+#define ARMADA_IOCTL(dir, name, str) \
+        DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str)
+
+struct drm_armada_gem_create {
+        uint32_t handle;
+        uint32_t size;
+};
+#define DRM_IOCTL_ARMADA_GEM_CREATE \
+        ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create)
+
+struct drm_armada_gem_mmap {
+        uint32_t handle;
+        uint32_t pad;
+        uint64_t offset;
+        uint64_t size;
+        uint64_t addr;
+};
+#define DRM_IOCTL_ARMADA_GEM_MMAP \
+        ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap)
+
+struct drm_armada_gem_pwrite {
+        uint64_t ptr;
+        uint32_t handle;
+        uint32_t offset;
+        uint32_t size;
+};
+#define DRM_IOCTL_ARMADA_GEM_PWRITE \
+        ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite)
+
+#endif
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index ece867889cc7..9b24d65fed72 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -611,12 +611,37 @@ struct drm_gem_open {
         __u64 size;
 };
 
+#define DRM_CAP_DUMB_BUFFER             0x1
+#define DRM_CAP_VBLANK_HIGH_CRTC        0x2
+#define DRM_CAP_DUMB_PREFERRED_DEPTH    0x3
+#define DRM_CAP_DUMB_PREFER_SHADOW      0x4
+#define DRM_CAP_PRIME                   0x5
+#define  DRM_PRIME_CAP_IMPORT           0x1
+#define  DRM_PRIME_CAP_EXPORT           0x2
+#define DRM_CAP_TIMESTAMP_MONOTONIC     0x6
+#define DRM_CAP_ASYNC_PAGE_FLIP         0x7
+
 /** DRM_IOCTL_GET_CAP ioctl argument type */
 struct drm_get_cap {
         __u64 capability;
         __u64 value;
 };
 
+/**
+ * DRM_CLIENT_CAP_STEREO_3D
+ *
+ * if set to 1, the DRM core will expose the stereo 3D capabilities of the
+ * monitor by advertising the supported 3D layouts in the flags of struct
+ * drm_mode_modeinfo.
+ */
+#define DRM_CLIENT_CAP_STEREO_3D        1
+
+/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
+struct drm_set_client_cap {
+        __u64 capability;
+        __u64 value;
+};
+
 #define DRM_CLOEXEC O_CLOEXEC
 struct drm_prime_handle {
         __u32 handle;
@@ -649,6 +674,7 @@ struct drm_prime_handle {
 #define DRM_IOCTL_GEM_FLINK             DRM_IOWR(0x0a, struct drm_gem_flink)
 #define DRM_IOCTL_GEM_OPEN              DRM_IOWR(0x0b, struct drm_gem_open)
 #define DRM_IOCTL_GET_CAP               DRM_IOWR(0x0c, struct drm_get_cap)
+#define DRM_IOCTL_SET_CLIENT_CAP        DRM_IOW( 0x0d, struct drm_set_client_cap)
 
 #define DRM_IOCTL_SET_UNIQUE            DRM_IOW( 0x10, struct drm_unique)
 #define DRM_IOCTL_AUTH_MAGIC            DRM_IOW( 0x11, struct drm_auth)
@@ -774,17 +800,6 @@ struct drm_event_vblank {
         __u32 reserved;
 };
 
-#define DRM_CAP_DUMB_BUFFER 0x1
-#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
-#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
-#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
-#define DRM_CAP_PRIME 0x5
-#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
-#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
-
-#define DRM_PRIME_CAP_IMPORT 0x1
-#define DRM_PRIME_CAP_EXPORT 0x2
-
 /* typedef area */
 #ifndef __KERNEL__
 typedef struct drm_clip_rect drm_clip_rect_t;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 28acbaf4a81e..f104c2603ebe 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -44,20 +44,35 @@
 
 /* Video mode flags */
 /* bit compatible with the xorg definitions. */
-#define DRM_MODE_FLAG_PHSYNC    (1<<0)
-#define DRM_MODE_FLAG_NHSYNC    (1<<1)
-#define DRM_MODE_FLAG_PVSYNC    (1<<2)
-#define DRM_MODE_FLAG_NVSYNC    (1<<3)
-#define DRM_MODE_FLAG_INTERLACE (1<<4)
-#define DRM_MODE_FLAG_DBLSCAN   (1<<5)
-#define DRM_MODE_FLAG_CSYNC     (1<<6)
-#define DRM_MODE_FLAG_PCSYNC    (1<<7)
-#define DRM_MODE_FLAG_NCSYNC    (1<<8)
-#define DRM_MODE_FLAG_HSKEW     (1<<9) /* hskew provided */
-#define DRM_MODE_FLAG_BCAST     (1<<10)
-#define DRM_MODE_FLAG_PIXMUX    (1<<11)
-#define DRM_MODE_FLAG_DBLCLK    (1<<12)
-#define DRM_MODE_FLAG_CLKDIV2   (1<<13)
+#define DRM_MODE_FLAG_PHSYNC                    (1<<0)
+#define DRM_MODE_FLAG_NHSYNC                    (1<<1)
+#define DRM_MODE_FLAG_PVSYNC                    (1<<2)
+#define DRM_MODE_FLAG_NVSYNC                    (1<<3)
+#define DRM_MODE_FLAG_INTERLACE                 (1<<4)
+#define DRM_MODE_FLAG_DBLSCAN                   (1<<5)
+#define DRM_MODE_FLAG_CSYNC                     (1<<6)
+#define DRM_MODE_FLAG_PCSYNC                    (1<<7)
+#define DRM_MODE_FLAG_NCSYNC                    (1<<8)
+#define DRM_MODE_FLAG_HSKEW                     (1<<9) /* hskew provided */
+#define DRM_MODE_FLAG_BCAST                     (1<<10)
+#define DRM_MODE_FLAG_PIXMUX                    (1<<11)
+#define DRM_MODE_FLAG_DBLCLK                    (1<<12)
+#define DRM_MODE_FLAG_CLKDIV2                   (1<<13)
+ /*
+  * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
+  * (define not exposed to user space).
+  */
+#define DRM_MODE_FLAG_3D_MASK                   (0x1f<<14)
+#define  DRM_MODE_FLAG_3D_NONE                  (0<<14)
+#define  DRM_MODE_FLAG_3D_FRAME_PACKING         (1<<14)
+#define  DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE     (2<<14)
+#define  DRM_MODE_FLAG_3D_LINE_ALTERNATIVE      (3<<14)
+#define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL     (4<<14)
+#define  DRM_MODE_FLAG_3D_L_DEPTH               (5<<14)
+#define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
+#define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM        (7<<14)
+#define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF     (8<<14)
+
 
 /* DPMS flags */
 /* bit compatible with the xorg definitions. */
@@ -165,6 +180,7 @@ struct drm_mode_get_plane_res {
 #define DRM_MODE_ENCODER_LVDS   3
 #define DRM_MODE_ENCODER_TVDAC  4
 #define DRM_MODE_ENCODER_VIRTUAL 5
+#define DRM_MODE_ENCODER_DSI    6
 
 struct drm_mode_get_encoder {
         __u32 encoder_id;
@@ -203,6 +219,7 @@ struct drm_mode_get_encoder {
 #define DRM_MODE_CONNECTOR_TV           13
 #define DRM_MODE_CONNECTOR_eDP          14
 #define DRM_MODE_CONNECTOR_VIRTUAL      15
+#define DRM_MODE_CONNECTOR_DSI          16
 
 struct drm_mode_get_connector {
 
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 55bb5729bd78..3a4e97bd8607 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -38,10 +38,10 @@
  *
  * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
  *      event from the gpu l3 cache. Additional information supplied is ROW,
- *      BANK, SUBBANK of the affected cacheline. Userspace should keep track of
- *      these events and if a specific cache-line seems to have a persistent
- *      error remap it with the l3 remapping tool supplied in intel-gpu-tools.
- *      The value supplied with the event is always 1.
+ *      BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
+ *      track of these events and if a specific cache-line seems to have a
+ *      persistent error remap it with the l3 remapping tool supplied in
+ *      intel-gpu-tools.  The value supplied with the event is always 1.
  *
  * I915_ERROR_UEVENT - Generated upon error detection, currently only via
  *      hangcheck. The error detection event is a good indicator of when things
diff --git a/include/uapi/drm/tegra_drm.h b/include/uapi/drm/tegra_drm.h
index 73bde4eaf16c..5e1ab552cbed 100644
--- a/include/uapi/drm/tegra_drm.h
+++ b/include/uapi/drm/tegra_drm.h
@@ -19,6 +19,9 @@
 
 #include <drm/drm.h>
 
+#define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
+#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
+
 struct drm_tegra_gem_create {
         __u64 size;
         __u32 flags;
@@ -65,6 +68,12 @@ struct drm_tegra_get_syncpt {
         __u32 id;
 };
 
+struct drm_tegra_get_syncpt_base {
+        __u64 context;
+        __u32 syncpt;
+        __u32 id;
+};
+
 struct drm_tegra_syncpt {
         __u32 id;
         __u32 incrs;
@@ -115,15 +124,16 @@ struct drm_tegra_submit {
         __u32 reserved[5];      /* future expansion */
 };
 
-#define DRM_TEGRA_GEM_CREATE    0x00
-#define DRM_TEGRA_GEM_MMAP      0x01
-#define DRM_TEGRA_SYNCPT_READ   0x02
-#define DRM_TEGRA_SYNCPT_INCR   0x03
-#define DRM_TEGRA_SYNCPT_WAIT   0x04
-#define DRM_TEGRA_OPEN_CHANNEL  0x05
-#define DRM_TEGRA_CLOSE_CHANNEL 0x06
-#define DRM_TEGRA_GET_SYNCPT    0x07
-#define DRM_TEGRA_SUBMIT        0x08
+#define DRM_TEGRA_GEM_CREATE            0x00
+#define DRM_TEGRA_GEM_MMAP              0x01
+#define DRM_TEGRA_SYNCPT_READ           0x02
+#define DRM_TEGRA_SYNCPT_INCR           0x03
+#define DRM_TEGRA_SYNCPT_WAIT           0x04
+#define DRM_TEGRA_OPEN_CHANNEL          0x05
+#define DRM_TEGRA_CLOSE_CHANNEL         0x06
+#define DRM_TEGRA_GET_SYNCPT            0x07
+#define DRM_TEGRA_SUBMIT                0x08
+#define DRM_TEGRA_GET_SYNCPT_BASE       0x09
 
 #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
 #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
@@ -134,5 +144,6 @@ struct drm_tegra_submit {
 #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
 #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
+#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
 
 #endif