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-rw-r--r--include/sound/ac97_codec.h598
-rw-r--r--include/sound/ad1816a.h174
-rw-r--r--include/sound/ad1848.h206
-rw-r--r--include/sound/ainstr_fm.h130
-rw-r--r--include/sound/ainstr_gf1.h225
-rw-r--r--include/sound/ainstr_iw.h373
-rw-r--r--include/sound/ainstr_simple.h156
-rw-r--r--include/sound/ak4114.h205
-rw-r--r--include/sound/ak4117.h191
-rw-r--r--include/sound/ak4531_codec.h80
-rw-r--r--include/sound/ak4xxx-adda.h69
-rw-r--r--include/sound/asequencer.h908
-rw-r--r--include/sound/asound.h927
-rw-r--r--include/sound/asound_fm.h115
-rw-r--r--include/sound/asoundef.h227
-rw-r--r--include/sound/control.h162
-rw-r--r--include/sound/core.h502
-rw-r--r--include/sound/cs4231.h366
-rw-r--r--include/sound/cs46xx.h1756
-rw-r--r--include/sound/cs46xx_dsp_scb_types.h1216
-rw-r--r--include/sound/cs46xx_dsp_spos.h233
-rw-r--r--include/sound/cs46xx_dsp_task_types.h253
-rw-r--r--include/sound/cs8403.h257
-rw-r--r--include/sound/cs8427.h196
-rw-r--r--include/sound/driver.h64
-rw-r--r--include/sound/emu10k1.h1544
-rw-r--r--include/sound/emu10k1_synth.h39
-rw-r--r--include/sound/emu8000.h120
-rw-r--r--include/sound/emu8000_reg.h207
-rw-r--r--include/sound/emux_legacy.h146
-rw-r--r--include/sound/emux_synth.h243
-rw-r--r--include/sound/es1688.h123
-rw-r--r--include/sound/gus.h718
-rw-r--r--include/sound/hdsp.h110
-rw-r--r--include/sound/hwdep.h73
-rw-r--r--include/sound/i2c.h102
-rw-r--r--include/sound/info.h193
-rw-r--r--include/sound/initval.h103
-rw-r--r--include/sound/memalloc.h118
-rw-r--r--include/sound/minors.h89
-rw-r--r--include/sound/mixer_oss.h76
-rw-r--r--include/sound/mpu401.h115
-rw-r--r--include/sound/opl3.h339
-rw-r--r--include/sound/opl4.h32
-rw-r--r--include/sound/pcm-indirect.h177
-rw-r--r--include/sound/pcm.h1040
-rw-r--r--include/sound/pcm_oss.h87
-rw-r--r--include/sound/pcm_params.h366
-rw-r--r--include/sound/rawmidi.h180
-rw-r--r--include/sound/sb.h360
-rw-r--r--include/sound/sb16_csp.h167
-rw-r--r--include/sound/seq_device.h88
-rw-r--r--include/sound/seq_instr.h112
-rw-r--r--include/sound/seq_kernel.h191
-rw-r--r--include/sound/seq_midi_emul.h195
-rw-r--r--include/sound/seq_midi_event.h56
-rw-r--r--include/sound/seq_oss.h102
-rw-r--r--include/sound/seq_oss_legacy.h31
-rw-r--r--include/sound/seq_virmidi.h84
-rw-r--r--include/sound/sfnt_info.h214
-rw-r--r--include/sound/snd_wavefront.h141
-rw-r--r--include/sound/soundfont.h130
-rw-r--r--include/sound/sscape_ioctl.h21
-rw-r--r--include/sound/tea575x-tuner.h53
-rw-r--r--include/sound/tea6330t.h42
-rw-r--r--include/sound/timer.h157
-rw-r--r--include/sound/trident.h479
-rw-r--r--include/sound/uda1341.h233
-rw-r--r--include/sound/util_mem.h64
-rw-r--r--include/sound/version.h3
-rw-r--r--include/sound/vx_core.h562
-rw-r--r--include/sound/wavefront.h695
-rw-r--r--include/sound/wavefront_fx.h9
-rw-r--r--include/sound/ymfpci.h396
74 files changed, 20514 insertions, 0 deletions
diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h
new file mode 100644
index 000000000000..2433e279e071
--- /dev/null
+++ b/include/sound/ac97_codec.h
@@ -0,0 +1,598 @@
1#ifndef __SOUND_AC97_CODEC_H
2#define __SOUND_AC97_CODEC_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Universal interface for Audio Codec '97
7 *
8 * For more details look to AC '97 component specification revision 2.1
9 * by Intel Corporation (http://developer.intel.com).
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28#include <linux/bitops.h>
29#include "pcm.h"
30#include "control.h"
31#include "info.h"
32
33/*
34 * AC'97 codec registers
35 */
36
37#define AC97_RESET 0x00 /* Reset */
38#define AC97_MASTER 0x02 /* Master Volume */
39#define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
40#define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
41#define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
42#define AC97_PC_BEEP 0x0a /* PC Beep Volume (optinal) */
43#define AC97_PHONE 0x0c /* Phone Volume (optional) */
44#define AC97_MIC 0x0e /* MIC Volume */
45#define AC97_LINE 0x10 /* Line In Volume */
46#define AC97_CD 0x12 /* CD Volume */
47#define AC97_VIDEO 0x14 /* Video Volume (optional) */
48#define AC97_AUX 0x16 /* AUX Volume (optional) */
49#define AC97_PCM 0x18 /* PCM Volume */
50#define AC97_REC_SEL 0x1a /* Record Select */
51#define AC97_REC_GAIN 0x1c /* Record Gain */
52#define AC97_REC_GAIN_MIC 0x1e /* Record Gain MIC (optional) */
53#define AC97_GENERAL_PURPOSE 0x20 /* General Purpose (optional) */
54#define AC97_3D_CONTROL 0x22 /* 3D Control (optional) */
55#define AC97_INT_PAGING 0x24 /* Audio Interrupt & Paging (AC'97 2.3) */
56#define AC97_POWERDOWN 0x26 /* Powerdown control / status */
57/* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */
58#define AC97_EXTENDED_ID 0x28 /* Extended Audio ID */
59#define AC97_EXTENDED_STATUS 0x2a /* Extended Audio Status and Control */
60#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
61#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
62#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
63#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
64#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
65#define AC97_CENTER_LFE_MASTER 0x36 /* Center + LFE Master Volume */
66#define AC97_SURROUND_MASTER 0x38 /* Surround (Rear) Master Volume */
67#define AC97_SPDIF 0x3a /* S/PDIF control */
68/* range 0x3c-0x58 - MODEM */
69#define AC97_EXTENDED_MID 0x3c /* Extended Modem ID */
70#define AC97_EXTENDED_MSTATUS 0x3e /* Extended Modem Status and Control */
71#define AC97_LINE1_RATE 0x40 /* Line1 DAC/ADC Rate */
72#define AC97_LINE2_RATE 0x42 /* Line2 DAC/ADC Rate */
73#define AC97_HANDSET_RATE 0x44 /* Handset DAC/ADC Rate */
74#define AC97_LINE1_LEVEL 0x46 /* Line1 DAC/ADC Level */
75#define AC97_LINE2_LEVEL 0x48 /* Line2 DAC/ADC Level */
76#define AC97_HANDSET_LEVEL 0x4a /* Handset DAC/ADC Level */
77#define AC97_GPIO_CFG 0x4c /* GPIO Configuration */
78#define AC97_GPIO_POLARITY 0x4e /* GPIO Pin Polarity/Type, 0=low, 1=high active */
79#define AC97_GPIO_STICKY 0x50 /* GPIO Pin Sticky, 0=not, 1=sticky */
80#define AC97_GPIO_WAKEUP 0x52 /* GPIO Pin Wakeup, 0=no int, 1=yes int */
81#define AC97_GPIO_STATUS 0x54 /* GPIO Pin Status, slot 12 */
82#define AC97_MISC_AFE 0x56 /* Miscellaneous Modem AFE Status and Control */
83/* range 0x5a-0x7b - Vendor Specific */
84#define AC97_VENDOR_ID1 0x7c /* Vendor ID1 */
85#define AC97_VENDOR_ID2 0x7e /* Vendor ID2 / revision */
86/* range 0x60-0x6f (page 1) - extended codec registers */
87#define AC97_CODEC_CLASS_REV 0x60 /* Codec Class/Revision */
88#define AC97_PCI_SVID 0x62 /* PCI Subsystem Vendor ID */
89#define AC97_PCI_SID 0x64 /* PCI Subsystem ID */
90#define AC97_FUNC_SELECT 0x66 /* Function Select */
91#define AC97_FUNC_INFO 0x68 /* Function Information */
92#define AC97_SENSE_INFO 0x6a /* Sense Details */
93
94/* slot allocation */
95#define AC97_SLOT_TAG 0
96#define AC97_SLOT_CMD_ADDR 1
97#define AC97_SLOT_CMD_DATA 2
98#define AC97_SLOT_PCM_LEFT 3
99#define AC97_SLOT_PCM_RIGHT 4
100#define AC97_SLOT_MODEM_LINE1 5
101#define AC97_SLOT_PCM_CENTER 6
102#define AC97_SLOT_MIC 6 /* input */
103#define AC97_SLOT_SPDIF_LEFT1 6
104#define AC97_SLOT_PCM_SLEFT 7 /* surround left */
105#define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */
106#define AC97_SLOT_SPDIF_LEFT 7
107#define AC97_SLOT_PCM_SRIGHT 8 /* surround right */
108#define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */
109#define AC97_SLOT_SPDIF_RIGHT 8
110#define AC97_SLOT_LFE 9
111#define AC97_SLOT_SPDIF_RIGHT1 9
112#define AC97_SLOT_MODEM_LINE2 10
113#define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */
114#define AC97_SLOT_SPDIF_LEFT2 10
115#define AC97_SLOT_HANDSET 11 /* output */
116#define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */
117#define AC97_SLOT_SPDIF_RIGHT2 11
118#define AC97_SLOT_MODEM_GPIO 12 /* modem GPIO */
119#define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */
120
121/* basic capabilities (reset register) */
122#define AC97_BC_DEDICATED_MIC 0x0001 /* Dedicated Mic PCM In Channel */
123#define AC97_BC_RESERVED1 0x0002 /* Reserved (was Modem Line Codec support) */
124#define AC97_BC_BASS_TREBLE 0x0004 /* Bass & Treble Control */
125#define AC97_BC_SIM_STEREO 0x0008 /* Simulated stereo */
126#define AC97_BC_HEADPHONE 0x0010 /* Headphone Out Support */
127#define AC97_BC_LOUDNESS 0x0020 /* Loudness (bass boost) Support */
128#define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */
129#define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */
130#define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */
131#define AC97_BC_DAC_MASK 0x00c0
132#define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */
133#define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */
134#define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */
135#define AC97_BC_ADC_MASK 0x0300
136
137/* general purpose */
138#define AC97_GP_DRSS_MASK 0x0c00 /* double rate slot select */
139#define AC97_GP_DRSS_1011 0x0000 /* LR(C) 10+11(+12) */
140#define AC97_GP_DRSS_78 0x0400 /* LR 7+8 */
141
142/* extended audio ID bit defines */
143#define AC97_EI_VRA 0x0001 /* Variable bit rate supported */
144#define AC97_EI_DRA 0x0002 /* Double rate supported */
145#define AC97_EI_SPDIF 0x0004 /* S/PDIF out supported */
146#define AC97_EI_VRM 0x0008 /* Variable bit rate supported for MIC */
147#define AC97_EI_DACS_SLOT_MASK 0x0030 /* DACs slot assignment */
148#define AC97_EI_DACS_SLOT_SHIFT 4
149#define AC97_EI_CDAC 0x0040 /* PCM Center DAC available */
150#define AC97_EI_SDAC 0x0080 /* PCM Surround DACs available */
151#define AC97_EI_LDAC 0x0100 /* PCM LFE DAC available */
152#define AC97_EI_AMAP 0x0200 /* indicates optional slot/DAC mapping based on codec ID */
153#define AC97_EI_REV_MASK 0x0c00 /* AC'97 revision mask */
154#define AC97_EI_REV_22 0x0400 /* AC'97 revision 2.2 */
155#define AC97_EI_REV_23 0x0800 /* AC'97 revision 2.3 */
156#define AC97_EI_REV_SHIFT 10
157#define AC97_EI_ADDR_MASK 0xc000 /* physical codec ID (address) */
158#define AC97_EI_ADDR_SHIFT 14
159
160/* extended audio status and control bit defines */
161#define AC97_EA_VRA 0x0001 /* Variable bit rate enable bit */
162#define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */
163#define AC97_EA_SPDIF 0x0004 /* S/PDIF out enable bit */
164#define AC97_EA_VRM 0x0008 /* Variable bit rate for MIC enable bit */
165#define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */
166#define AC97_EA_SPSA_SLOT_SHIFT 4
167#define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */
168#define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */
169#define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */
170#define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */
171#define AC97_EA_CDAC 0x0040 /* PCM Center DAC is ready (Read only) */
172#define AC97_EA_SDAC 0x0080 /* PCM Surround DACs are ready (Read only) */
173#define AC97_EA_LDAC 0x0100 /* PCM LFE DAC is ready (Read only) */
174#define AC97_EA_MDAC 0x0200 /* MIC ADC is ready (Read only) */
175#define AC97_EA_SPCV 0x0400 /* S/PDIF configuration valid (Read only) */
176#define AC97_EA_PRI 0x0800 /* Turns the PCM Center DAC off */
177#define AC97_EA_PRJ 0x1000 /* Turns the PCM Surround DACs off */
178#define AC97_EA_PRK 0x2000 /* Turns the PCM LFE DAC off */
179#define AC97_EA_PRL 0x4000 /* Turns the MIC ADC off */
180
181/* S/PDIF control bit defines */
182#define AC97_SC_PRO 0x0001 /* Professional status */
183#define AC97_SC_NAUDIO 0x0002 /* Non audio stream */
184#define AC97_SC_COPY 0x0004 /* Copyright status */
185#define AC97_SC_PRE 0x0008 /* Preemphasis status */
186#define AC97_SC_CC_MASK 0x07f0 /* Category Code mask */
187#define AC97_SC_CC_SHIFT 4
188#define AC97_SC_L 0x0800 /* Generation Level status */
189#define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */
190#define AC97_SC_SPSR_SHIFT 12
191#define AC97_SC_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
192#define AC97_SC_SPSR_48K 0x2000 /* Use 48kHz Sample rate */
193#define AC97_SC_SPSR_32K 0x3000 /* Use 32kHz Sample rate */
194#define AC97_SC_DRS 0x4000 /* Double Rate S/PDIF */
195#define AC97_SC_V 0x8000 /* Validity status */
196
197/* Interrupt and Paging bit defines (AC'97 2.3) */
198#define AC97_PAGE_MASK 0x000f /* Page Selector */
199#define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */
200#define AC97_PAGE_1 1 /* Extended Codec Registers page 1 */
201#define AC97_INT_ENABLE 0x0800 /* Interrupt Enable */
202#define AC97_INT_SENSE 0x1000 /* Sense Cycle */
203#define AC97_INT_CAUSE_SENSE 0x2000 /* Sense Cycle Completed (RO) */
204#define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */
205#define AC97_INT_STATUS 0x8000 /* Interrupt Status */
206
207/* extended modem ID bit defines */
208#define AC97_MEI_LINE1 0x0001 /* Line1 present */
209#define AC97_MEI_LINE2 0x0002 /* Line2 present */
210#define AC97_MEI_HANDSET 0x0004 /* Handset present */
211#define AC97_MEI_CID1 0x0008 /* caller ID decode for Line1 is supported */
212#define AC97_MEI_CID2 0x0010 /* caller ID decode for Line2 is supported */
213#define AC97_MEI_ADDR_MASK 0xc000 /* physical codec ID (address) */
214#define AC97_MEI_ADDR_SHIFT 14
215
216/* extended modem status and control bit defines */
217#define AC97_MEA_GPIO 0x0001 /* GPIO is ready (ro) */
218#define AC97_MEA_MREF 0x0002 /* Vref is up to nominal level (ro) */
219#define AC97_MEA_ADC1 0x0004 /* ADC1 operational (ro) */
220#define AC97_MEA_DAC1 0x0008 /* DAC1 operational (ro) */
221#define AC97_MEA_ADC2 0x0010 /* ADC2 operational (ro) */
222#define AC97_MEA_DAC2 0x0020 /* DAC2 operational (ro) */
223#define AC97_MEA_HADC 0x0040 /* HADC operational (ro) */
224#define AC97_MEA_HDAC 0x0080 /* HDAC operational (ro) */
225#define AC97_MEA_PRA 0x0100 /* GPIO power down (high) */
226#define AC97_MEA_PRB 0x0200 /* reserved */
227#define AC97_MEA_PRC 0x0400 /* ADC1 power down (high) */
228#define AC97_MEA_PRD 0x0800 /* DAC1 power down (high) */
229#define AC97_MEA_PRE 0x1000 /* ADC2 power down (high) */
230#define AC97_MEA_PRF 0x2000 /* DAC2 power down (high) */
231#define AC97_MEA_PRG 0x4000 /* HADC power down (high) */
232#define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */
233
234/* modem gpio status defines */
235#define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */
236#define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */
237#define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */
238#define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */
239#define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */
240#define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */
241#define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */
242#define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */
243#define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */
244#define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */
245#define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */
246#define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */
247#define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */
248#define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */
249#define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */
250#define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */
251
252/* specific - SigmaTel */
253#define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */
254#define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */
255#define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */
256#define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */
257#define AC97_SIGMATEL_DAC2INVERT 0x6e
258#define AC97_SIGMATEL_BIAS1 0x70
259#define AC97_SIGMATEL_BIAS2 0x72
260#define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */
261#define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */
262#define AC97_SIGMATEL_CIC1 0x76
263#define AC97_SIGMATEL_CIC2 0x78
264
265/* specific - Analog Devices */
266#define AC97_AD_TEST 0x5a /* test register */
267#define AC97_AD_CODEC_CFG 0x70 /* codec configuration */
268#define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */
269#define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */
270#define AC97_AD_MISC 0x76 /* Misc Control Bits */
271
272/* specific - Cirrus Logic */
273#define AC97_CSR_ACMODE 0x5e /* AC Mode Register */
274#define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */
275#define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */
276#define AC97_CSR_SERIAL 0x6a /* Serial Port Control */
277#define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */
278#define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */
279#define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */
280
281/* specific - Conexant */
282#define AC97_CXR_AUDIO_MISC 0x5c
283#define AC97_CXR_SPDIFEN (1<<3)
284#define AC97_CXR_COPYRGT (1<<2)
285#define AC97_CXR_SPDIF_MASK (3<<0)
286#define AC97_CXR_SPDIF_PCM 0x0
287#define AC97_CXR_SPDIF_AC3 0x2
288
289/* specific - ALC */
290#define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60
291/* S/PDIF input status 1 bit defines */
292#define AC97_ALC650_PRO 0x0001 /* Professional status */
293#define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */
294#define AC97_ALC650_COPY 0x0004 /* Copyright status */
295#define AC97_ALC650_PRE 0x0038 /* Preemphasis status */
296#define AC97_ALC650_PRE_SHIFT 3
297#define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */
298#define AC97_ALC650_MODE_SHIFT 6
299#define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */
300#define AC97_ALC650_CC_SHIFT 8
301#define AC97_ALC650_L 0x8000 /* Generation Level status */
302
303#define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62
304/* S/PDIF input status 2 bit defines */
305#define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */
306#define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */
307#define AC97_ALC650_CHANNEL_SHIFT 4
308#define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */
309#define AC97_ALC650_SPSR_SHIFT 8
310#define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
311#define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */
312#define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */
313#define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */
314#define AC97_ALC650_CLOCK_SHIFT 12
315#define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */
316#define AC97_ALC650_V 0x8000 /* Validity status */
317
318#define AC97_ALC650_SURR_DAC_VOL 0x64
319#define AC97_ALC650_LFE_DAC_VOL 0x66
320#define AC97_ALC650_UNKNOWN1 0x68
321#define AC97_ALC650_MULTICH 0x6a
322#define AC97_ALC650_UNKNOWN2 0x6c
323#define AC97_ALC650_REVISION 0x6e
324#define AC97_ALC650_UNKNOWN3 0x70
325#define AC97_ALC650_UNKNOWN4 0x72
326#define AC97_ALC650_MISC 0x74
327#define AC97_ALC650_GPIO_SETUP 0x76
328#define AC97_ALC650_GPIO_STATUS 0x78
329#define AC97_ALC650_CLOCK 0x7a
330
331/* specific - Yamaha YMF753 */
332#define AC97_YMF753_DIT_CTRL2 0x66 /* DIT Control 2 */
333#define AC97_YMF753_3D_MODE_SEL 0x68 /* 3D Mode Select */
334
335/* specific - C-Media */
336#define AC97_CM9738_VENDOR_CTRL 0x5a
337#define AC97_CM9739_MULTI_CHAN 0x64
338#define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */
339#define AC97_CM9739_SPDIF_CTRL 0x6c
340
341/* specific - wolfson */
342#define AC97_WM97XX_FMIXER_VOL 0x72
343#define AC97_WM9704_RMIXER_VOL 0x74
344#define AC97_WM9704_TEST 0x5a
345#define AC97_WM9704_RPCM_VOL 0x70
346#define AC97_WM9711_OUT3VOL 0x16
347
348
349/* ac97->scaps */
350#define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */
351#define AC97_SCAP_MODEM (1<<1) /* modem codec 97 */
352#define AC97_SCAP_SURROUND_DAC (1<<2) /* surround L&R DACs are present */
353#define AC97_SCAP_CENTER_LFE_DAC (1<<3) /* center and LFE DACs are present */
354#define AC97_SCAP_SKIP_AUDIO (1<<4) /* skip audio part of codec */
355#define AC97_SCAP_SKIP_MODEM (1<<5) /* skip modem part of codec */
356#define AC97_SCAP_INDEP_SDIN (1<<6) /* independent SDIN */
357#define AC97_SCAP_INV_EAPD (1<<7) /* inverted EAPD */
358#define AC97_SCAP_DETECT_BY_VENDOR (1<<8) /* use vendor registers for read tests */
359#define AC97_SCAP_NO_SPDIF (1<<9) /* don't build SPDIF controls */
360
361/* ac97->flags */
362#define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */
363#define AC97_AD_MULTI (1<<1) /* Analog Devices - multi codecs */
364#define AC97_CS_SPDIF (1<<2) /* Cirrus Logic uses funky SPDIF */
365#define AC97_CX_SPDIF (1<<3) /* Conexant's spdif interface */
366#define AC97_STEREO_MUTES (1<<4) /* has stereo mute bits */
367#define AC97_DOUBLE_RATE (1<<5) /* supports double rate playback */
368#define AC97_HAS_NO_MASTER_VOL (1<<6) /* no Master volume */
369#define AC97_HAS_NO_PCM_VOL (1<<7) /* no PCM volume */
370#define AC97_DEFAULT_POWER_OFF (1<<8) /* no RESET write */
371#define AC97_MODEM_PATCH (1<<9) /* modem patch */
372#define AC97_HAS_NO_REC_GAIN (1<<10) /* no Record gain */
373#define AC97_HAS_NO_PHONE (1<<11) /* no PHONE volume */
374#define AC97_HAS_NO_PC_BEEP (1<<12) /* no PC Beep volume */
375#define AC97_HAS_NO_VIDEO (1<<13) /* no Video volume */
376#define AC97_HAS_NO_CD (1<<14) /* no CD volume */
377
378/* rates indexes */
379#define AC97_RATES_FRONT_DAC 0
380#define AC97_RATES_SURR_DAC 1
381#define AC97_RATES_LFE_DAC 2
382#define AC97_RATES_ADC 3
383#define AC97_RATES_MIC_ADC 4
384#define AC97_RATES_SPDIF 5
385
386/* shared controllers */
387enum {
388 AC97_SHARED_TYPE_NONE,
389 AC97_SHARED_TYPE_ICH,
390 AC97_SHARED_TYPE_ATIIXP,
391 AC97_SHARED_TYPE_VIA,
392 AC97_SHARED_TYPES
393};
394
395/*
396 *
397 */
398
399typedef struct _snd_ac97_bus ac97_bus_t;
400typedef struct _snd_ac97_bus_ops ac97_bus_ops_t;
401typedef struct _snd_ac97_template ac97_template_t;
402typedef struct _snd_ac97 ac97_t;
403
404enum ac97_pcm_cfg {
405 AC97_PCM_CFG_FRONT = 2,
406 AC97_PCM_CFG_REAR = 10, /* alias surround */
407 AC97_PCM_CFG_LFE = 11, /* center + lfe */
408 AC97_PCM_CFG_40 = 4, /* front + rear */
409 AC97_PCM_CFG_51 = 6, /* front + rear + center/lfe */
410 AC97_PCM_CFG_SPDIF = 20
411};
412
413/* PCM allocation */
414struct ac97_pcm {
415 ac97_bus_t *bus;
416 unsigned int stream: 1, /* stream type: 1 = capture */
417 exclusive: 1, /* exclusive mode, don't override with other pcms */
418 copy_flag: 1, /* lowlevel driver must fill all entries */
419 spdif: 1; /* spdif pcm */
420 unsigned short aslots; /* active slots */
421 unsigned int rates; /* available rates */
422 struct {
423 unsigned short slots; /* driver input: requested AC97 slot numbers */
424 unsigned short rslots[4]; /* allocated slots per codecs */
425 unsigned char rate_table[4];
426 ac97_t *codec[4]; /* allocated codecs */
427 } r[2]; /* 0 = standard rates, 1 = double rates */
428 unsigned long private_value; /* used by the hardware driver */
429};
430
431struct snd_ac97_build_ops {
432 int (*build_3d) (ac97_t *ac97);
433 int (*build_specific) (ac97_t *ac97);
434 int (*build_spdif) (ac97_t *ac97);
435 int (*build_post_spdif) (ac97_t *ac97);
436#ifdef CONFIG_PM
437 void (*suspend) (ac97_t *ac97);
438 void (*resume) (ac97_t *ac97);
439#endif
440};
441
442struct _snd_ac97_bus_ops {
443 void (*reset) (ac97_t *ac97);
444 void (*write) (ac97_t *ac97, unsigned short reg, unsigned short val);
445 unsigned short (*read) (ac97_t *ac97, unsigned short reg);
446 void (*wait) (ac97_t *ac97);
447 void (*init) (ac97_t *ac97);
448};
449
450struct _snd_ac97_bus {
451 /* -- lowlevel (hardware) driver specific -- */
452 ac97_bus_ops_t *ops;
453 void *private_data;
454 void (*private_free) (ac97_bus_t *bus);
455 /* --- */
456 snd_card_t *card;
457 unsigned short num; /* bus number */
458 unsigned short no_vra: 1, /* bridge doesn't support VRA */
459 dra: 1, /* bridge supports double rate */
460 isdin: 1;/* independent SDIN */
461 unsigned int clock; /* AC'97 base clock (usually 48000Hz) */
462 spinlock_t bus_lock; /* used mainly for slot allocation */
463 unsigned short used_slots[2][4]; /* actually used PCM slots */
464 unsigned short pcms_count; /* count of PCMs */
465 struct ac97_pcm *pcms;
466 unsigned int shared_type; /* type of shared controller betwen audio and modem */
467 ac97_t *codec[4];
468 snd_info_entry_t *proc;
469};
470
471struct _snd_ac97_template {
472 void *private_data;
473 void (*private_free) (ac97_t *ac97);
474 struct pci_dev *pci; /* assigned PCI device - used for quirks */
475 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
476 unsigned short addr; /* physical address of codec [0-3] */
477 unsigned int scaps; /* driver capabilities */
478 unsigned int limited_regs; /* allow limited registers only */
479 DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
480};
481
482struct _snd_ac97 {
483 /* -- lowlevel (hardware) driver specific -- */
484 struct snd_ac97_build_ops * build_ops;
485 void *private_data;
486 void (*private_free) (ac97_t *ac97);
487 /* --- */
488 ac97_bus_t *bus;
489 struct pci_dev *pci; /* assigned PCI device - used for quirks */
490 snd_info_entry_t *proc;
491 snd_info_entry_t *proc_regs;
492 unsigned short subsystem_vendor;
493 unsigned short subsystem_device;
494 struct semaphore reg_mutex;
495 struct semaphore page_mutex; /* mutex for AD18xx multi-codecs and paging (2.3) */
496 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
497 unsigned short addr; /* physical address of codec [0-3] */
498 unsigned int id; /* identification of codec */
499 unsigned short caps; /* capabilities (register 0) */
500 unsigned short ext_id; /* extended feature identification (register 28) */
501 unsigned short ext_mid; /* extended modem ID (register 3C) */
502 unsigned int scaps; /* driver capabilities */
503 unsigned int flags; /* specific code */
504 unsigned int rates[6]; /* see AC97_RATES_* defines */
505 unsigned int spdif_status;
506 unsigned short regs[0x80]; /* register cache */
507 unsigned int limited_regs; /* allow limited registers only */
508 DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
509 union { /* vendor specific code */
510 struct {
511 unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69
512 unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69
513 unsigned short id[3]; // codec IDs (lower 16-bit word)
514 unsigned short pcmreg[3]; // PCM registers
515 unsigned short codec_cfg[3]; // CODEC_CFG bits
516 } ad18xx;
517 unsigned int dev_flags; /* device specific */
518 } spec;
519};
520
521/* conditions */
522static inline int ac97_is_audio(ac97_t * ac97)
523{
524 return (ac97->scaps & AC97_SCAP_AUDIO);
525}
526static inline int ac97_is_modem(ac97_t * ac97)
527{
528 return (ac97->scaps & AC97_SCAP_MODEM);
529}
530static inline int ac97_is_rev22(ac97_t * ac97)
531{
532 return (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_22;
533}
534static inline int ac97_can_amap(ac97_t * ac97)
535{
536 return (ac97->ext_id & AC97_EI_AMAP) != 0;
537}
538static inline int ac97_can_spdif(ac97_t * ac97)
539{
540 return (ac97->ext_id & AC97_EI_SPDIF) != 0;
541}
542
543/* functions */
544int snd_ac97_bus(snd_card_t *card, int num, ac97_bus_ops_t *ops, void *private_data, ac97_bus_t **rbus); /* create new AC97 bus */
545int snd_ac97_mixer(ac97_bus_t *bus, ac97_template_t *template, ac97_t **rac97); /* create mixer controls */
546const char *snd_ac97_get_short_name(ac97_t *ac97);
547
548void snd_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short value);
549unsigned short snd_ac97_read(ac97_t *ac97, unsigned short reg);
550void snd_ac97_write_cache(ac97_t *ac97, unsigned short reg, unsigned short value);
551int snd_ac97_update(ac97_t *ac97, unsigned short reg, unsigned short value);
552int snd_ac97_update_bits(ac97_t *ac97, unsigned short reg, unsigned short mask, unsigned short value);
553#ifdef CONFIG_PM
554void snd_ac97_suspend(ac97_t *ac97);
555void snd_ac97_resume(ac97_t *ac97);
556#endif
557
558/* quirk types */
559enum {
560 AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */
561 AC97_TUNE_NONE = 0, /* nothing extra to do */
562 AC97_TUNE_HP_ONLY, /* headphone (true line-out) control as master only */
563 AC97_TUNE_SWAP_HP, /* swap headphone and master controls */
564 AC97_TUNE_SWAP_SURROUND, /* swap master and surround controls */
565 AC97_TUNE_AD_SHARING, /* for AD1985, turn on OMS bit and use headphone */
566 AC97_TUNE_ALC_JACK, /* for Realtek, enable JACK detection */
567 AC97_TUNE_INV_EAPD, /* inverted EAPD implementation */
568 AC97_TUNE_MUTE_LED, /* EAPD bit works as mute LED */
569};
570
571struct ac97_quirk {
572 unsigned short vendor; /* PCI vendor id */
573 unsigned short device; /* PCI device id */
574 unsigned short mask; /* device id bit mask, 0 = accept all */
575 unsigned int codec_id; /* codec id (if any), 0 = accept all */
576 const char *name; /* name shown as info */
577 int type; /* quirk type above */
578};
579
580int snd_ac97_tune_hardware(ac97_t *ac97, struct ac97_quirk *quirk, const char *override);
581int snd_ac97_set_rate(ac97_t *ac97, int reg, unsigned int rate);
582
583int snd_ac97_pcm_assign(ac97_bus_t *ac97,
584 unsigned short pcms_count,
585 const struct ac97_pcm *pcms);
586int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate,
587 enum ac97_pcm_cfg cfg, unsigned short slots);
588int snd_ac97_pcm_close(struct ac97_pcm *pcm);
589int snd_ac97_pcm_double_rate_rules(snd_pcm_runtime_t *runtime);
590
591struct ac97_enum {
592 unsigned char reg;
593 unsigned char shift_l;
594 unsigned char shift_r;
595 unsigned short mask;
596 const char **texts;
597};
598#endif /* __SOUND_AC97_CODEC_H */
diff --git a/include/sound/ad1816a.h b/include/sound/ad1816a.h
new file mode 100644
index 000000000000..395978e375cf
--- /dev/null
+++ b/include/sound/ad1816a.h
@@ -0,0 +1,174 @@
1#ifndef __SOUND_AD1816A_H
2#define __SOUND_AD1816A_H
3
4/*
5 ad1816a.h - definitions for ADI SoundPort AD1816A chip.
6 Copyright (C) 1999-2000 by Massimo Piccioni <dafastidio@libero.it>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include "control.h"
24#include "pcm.h"
25#include "timer.h"
26
27#define AD1816A_REG(r) (chip->port + r)
28
29#define AD1816A_CHIP_STATUS 0x00
30#define AD1816A_INDIR_ADDR 0x00
31#define AD1816A_INTERRUPT_STATUS 0x01
32#define AD1816A_INDIR_DATA_LOW 0x02
33#define AD1816A_INDIR_DATA_HIGH 0x03
34#define AD1816A_PIO_DEBUG 0x04
35#define AD1816A_PIO_STATUS 0x05
36#define AD1816A_PIO_DATA 0x06
37#define AD1816A_RESERVED_7 0x07
38#define AD1816A_PLAYBACK_CONFIG 0x08
39#define AD1816A_CAPTURE_CONFIG 0x09
40#define AD1816A_RESERVED_10 0x0a
41#define AD1816A_RESERVED_11 0x0b
42#define AD1816A_JOYSTICK_RAW_DATA 0x0c
43#define AD1816A_JOYSTICK_CTRL 0x0d
44#define AD1816A_JOY_POS_DATA_LOW 0x0e
45#define AD1816A_JOY_POS_DATA_HIGH 0x0f
46
47#define AD1816A_LOW_BYTE_TMP 0x00
48#define AD1816A_INTERRUPT_ENABLE 0x01
49#define AD1816A_EXTERNAL_CTRL 0x01
50#define AD1816A_PLAYBACK_SAMPLE_RATE 0x02
51#define AD1816A_CAPTURE_SAMPLE_RATE 0x03
52#define AD1816A_VOICE_ATT 0x04
53#define AD1816A_FM_ATT 0x05
54#define AD1816A_I2S_1_ATT 0x06
55#define AD1816A_I2S_0_ATT 0x07
56#define AD1816A_PLAYBACK_BASE_COUNT 0x08
57#define AD1816A_PLAYBACK_CURR_COUNT 0x09
58#define AD1816A_CAPTURE_BASE_COUNT 0x0a
59#define AD1816A_CAPTURE_CURR_COUNT 0x0b
60#define AD1816A_TIMER_BASE_COUNT 0x0c
61#define AD1816A_TIMER_CURR_COUNT 0x0d
62#define AD1816A_MASTER_ATT 0x0e
63#define AD1816A_CD_GAIN_ATT 0x0f
64#define AD1816A_SYNTH_GAIN_ATT 0x10
65#define AD1816A_VID_GAIN_ATT 0x11
66#define AD1816A_LINE_GAIN_ATT 0x12
67#define AD1816A_MIC_GAIN_ATT 0x13
68#define AD1816A_PHONE_IN_GAIN_ATT 0x13
69#define AD1816A_ADC_SOURCE_SEL 0x14
70#define AD1816A_ADC_PGA 0x14
71#define AD1816A_CHIP_CONFIG 0x20
72#define AD1816A_DSP_CONFIG 0x21
73#define AD1816A_FM_SAMPLE_RATE 0x22
74#define AD1816A_I2S_1_SAMPLE_RATE 0x23
75#define AD1816A_I2S_0_SAMPLE_RATE 0x24
76#define AD1816A_RESERVED_37 0x25
77#define AD1816A_PROGRAM_CLOCK_RATE 0x26
78#define AD1816A_3D_PHAT_CTRL 0x27
79#define AD1816A_PHONE_OUT_ATT 0x27
80#define AD1816A_RESERVED_40 0x28
81#define AD1816A_HW_VOL_BUT 0x29
82#define AD1816A_DSP_MAILBOX_0 0x2a
83#define AD1816A_DSP_MAILBOX_1 0x2b
84#define AD1816A_POWERDOWN_CTRL 0x2c
85#define AD1816A_TIMER_CTRL 0x2c
86#define AD1816A_VERSION_ID 0x2d
87#define AD1816A_RESERVED_46 0x2e
88
89#define AD1816A_READY 0x80
90
91#define AD1816A_PLAYBACK_IRQ_PENDING 0x80
92#define AD1816A_CAPTURE_IRQ_PENDING 0x40
93#define AD1816A_TIMER_IRQ_PENDING 0x20
94
95#define AD1816A_PLAYBACK_ENABLE 0x01
96#define AD1816A_PLAYBACK_PIO 0x02
97#define AD1816A_CAPTURE_ENABLE 0x01
98#define AD1816A_CAPTURE_PIO 0x02
99
100#define AD1816A_FMT_LINEAR_8 0x00
101#define AD1816A_FMT_ULAW_8 0x08
102#define AD1816A_FMT_LINEAR_16_LIT 0x10
103#define AD1816A_FMT_ALAW_8 0x18
104#define AD1816A_FMT_LINEAR_16_BIG 0x30
105#define AD1816A_FMT_ALL 0x38
106#define AD1816A_FMT_STEREO 0x04
107
108#define AD1816A_PLAYBACK_IRQ_ENABLE 0x8000
109#define AD1816A_CAPTURE_IRQ_ENABLE 0x4000
110#define AD1816A_TIMER_IRQ_ENABLE 0x2000
111#define AD1816A_TIMER_ENABLE 0x0080
112
113#define AD1816A_SRC_LINE 0x00
114#define AD1816A_SRC_OUT 0x10
115#define AD1816A_SRC_CD 0x20
116#define AD1816A_SRC_SYNTH 0x30
117#define AD1816A_SRC_VIDEO 0x40
118#define AD1816A_SRC_MIC 0x50
119#define AD1816A_SRC_MONO 0x50
120#define AD1816A_SRC_PHONE_IN 0x60
121#define AD1816A_SRC_MASK 0x70
122
123#define AD1816A_CAPTURE_NOT_EQUAL 0x1000
124#define AD1816A_WSS_ENABLE 0x8000
125
126typedef struct _snd_ad1816a ad1816a_t;
127
128struct _snd_ad1816a {
129 unsigned long port;
130 struct resource *res_port;
131 int irq;
132 int dma1;
133 int dma2;
134
135 unsigned short hardware;
136 unsigned short version;
137
138 spinlock_t lock;
139
140 unsigned short mode;
141
142 snd_card_t *card;
143 snd_pcm_t *pcm;
144
145 snd_pcm_substream_t *playback_substream;
146 snd_pcm_substream_t *capture_substream;
147 unsigned int p_dma_size;
148 unsigned int c_dma_size;
149
150 snd_timer_t *timer;
151};
152
153
154#define AD1816A_HW_AUTO 0
155#define AD1816A_HW_AD1816A 1
156#define AD1816A_HW_AD1815 2
157#define AD1816A_HW_AD18MAX10 3
158
159#define AD1816A_MODE_PLAYBACK 0x01
160#define AD1816A_MODE_CAPTURE 0x02
161#define AD1816A_MODE_TIMER 0x04
162#define AD1816A_MODE_OPEN (AD1816A_MODE_PLAYBACK | \
163 AD1816A_MODE_CAPTURE | \
164 AD1816A_MODE_TIMER)
165
166
167extern int snd_ad1816a_create(snd_card_t *card, unsigned long port,
168 int irq, int dma1, int dma2,
169 ad1816a_t **chip);
170
171extern int snd_ad1816a_pcm(ad1816a_t *chip, int device, snd_pcm_t **rpcm);
172extern int snd_ad1816a_mixer(ad1816a_t *chip);
173
174#endif /* __SOUND_AD1816A_H */
diff --git a/include/sound/ad1848.h b/include/sound/ad1848.h
new file mode 100644
index 000000000000..7e33b11037f2
--- /dev/null
+++ b/include/sound/ad1848.h
@@ -0,0 +1,206 @@
1#ifndef __SOUND_AD1848_H
2#define __SOUND_AD1848_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Definitions for AD1847/AD1848/CS4248 chips
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "pcm.h"
26#include <linux/interrupt.h>
27
28/* IO ports */
29
30#define AD1848P( codec, x ) ( (chip) -> port + c_d_c_AD1848##x )
31
32#define c_d_c_AD1848REGSEL 0
33#define c_d_c_AD1848REG 1
34#define c_d_c_AD1848STATUS 2
35#define c_d_c_AD1848PIO 3
36
37/* codec registers */
38
39#define AD1848_LEFT_INPUT 0x00 /* left input control */
40#define AD1848_RIGHT_INPUT 0x01 /* right input control */
41#define AD1848_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
42#define AD1848_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
43#define AD1848_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
44#define AD1848_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
45#define AD1848_LEFT_OUTPUT 0x06 /* left output control register */
46#define AD1848_RIGHT_OUTPUT 0x07 /* right output control register */
47#define AD1848_DATA_FORMAT 0x08 /* clock and data format - playback/capture - bits 7-0 MCE */
48#define AD1848_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
49#define AD1848_PIN_CTRL 0x0a /* pin control */
50#define AD1848_TEST_INIT 0x0b /* test and initialization */
51#define AD1848_MISC_INFO 0x0c /* miscellaneaous information */
52#define AD1848_LOOPBACK 0x0d /* loopback control */
53#define AD1848_DATA_UPR_CNT 0x0e /* playback/capture upper base count */
54#define AD1848_DATA_LWR_CNT 0x0f /* playback/capture lower base count */
55
56/* definitions for codec register select port - CODECP( REGSEL ) */
57
58#define AD1848_INIT 0x80 /* CODEC is initializing */
59#define AD1848_MCE 0x40 /* mode change enable */
60#define AD1848_TRD 0x20 /* transfer request disable */
61
62/* definitions for codec status register - CODECP( STATUS ) */
63
64#define AD1848_GLOBALIRQ 0x01 /* IRQ is active */
65
66/* definitions for AD1848_LEFT_INPUT and AD1848_RIGHT_INPUT registers */
67
68#define AD1848_ENABLE_MIC_GAIN 0x20
69
70#define AD1848_MIXS_LINE1 0x00
71#define AD1848_MIXS_AUX1 0x40
72#define AD1848_MIXS_LINE2 0x80
73#define AD1848_MIXS_ALL 0xc0
74
75/* definitions for clock and data format register - AD1848_PLAYBK_FORMAT */
76
77#define AD1848_LINEAR_8 0x00 /* 8-bit unsigned data */
78#define AD1848_ALAW_8 0x60 /* 8-bit A-law companded */
79#define AD1848_ULAW_8 0x20 /* 8-bit U-law companded */
80#define AD1848_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
81#define AD1848_STEREO 0x10 /* stereo mode */
82/* bits 3-1 define frequency divisor */
83#define AD1848_XTAL1 0x00 /* 24.576 crystal */
84#define AD1848_XTAL2 0x01 /* 16.9344 crystal */
85
86/* definitions for interface control register - AD1848_IFACE_CTRL */
87
88#define AD1848_CAPTURE_PIO 0x80 /* capture PIO enable */
89#define AD1848_PLAYBACK_PIO 0x40 /* playback PIO enable */
90#define AD1848_CALIB_MODE 0x18 /* calibration mode bits */
91#define AD1848_AUTOCALIB 0x08 /* auto calibrate */
92#define AD1848_SINGLE_DMA 0x04 /* use single DMA channel */
93#define AD1848_CAPTURE_ENABLE 0x02 /* capture enable */
94#define AD1848_PLAYBACK_ENABLE 0x01 /* playback enable */
95
96/* definitions for pin control register - AD1848_PIN_CTRL */
97
98#define AD1848_IRQ_ENABLE 0x02 /* enable IRQ */
99#define AD1848_XCTL1 0x40 /* external control #1 */
100#define AD1848_XCTL0 0x80 /* external control #0 */
101
102/* definitions for test and init register - AD1848_TEST_INIT */
103
104#define AD1848_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
105#define AD1848_DMA_REQUEST 0x10 /* DMA request in progress */
106
107/* defines for codec.mode */
108
109#define AD1848_MODE_NONE 0x0000
110#define AD1848_MODE_PLAY 0x0001
111#define AD1848_MODE_CAPTURE 0x0002
112#define AD1848_MODE_TIMER 0x0004
113#define AD1848_MODE_OPEN (AD1848_MODE_PLAY|AD1848_MODE_CAPTURE|AD1848_MODE_TIMER)
114#define AD1848_MODE_RUNNING 0x0010
115
116/* defines for codec.hardware */
117
118#define AD1848_HW_DETECT 0x0000 /* let AD1848 driver detect chip */
119#define AD1848_HW_AD1847 0x0001 /* AD1847 chip */
120#define AD1848_HW_AD1848 0x0002 /* AD1848 chip */
121#define AD1848_HW_CS4248 0x0003 /* CS4248 chip */
122#define AD1848_HW_CMI8330 0x0004 /* CMI8330 chip */
123#define AD1848_HW_THINKPAD 0x0005 /* Thinkpad 360/750/755 */
124
125/* IBM Thinkpad specific stuff */
126#define AD1848_THINKPAD_CTL_PORT1 0x15e8
127#define AD1848_THINKPAD_CTL_PORT2 0x15e9
128#define AD1848_THINKPAD_CS4248_ENABLE_BIT 0x02
129
130struct _snd_ad1848 {
131 unsigned long port; /* i/o port */
132 struct resource *res_port;
133 int irq; /* IRQ line */
134 int dma; /* data DMA */
135 unsigned short version; /* version of CODEC chip */
136 unsigned short mode; /* see to AD1848_MODE_XXXX */
137 unsigned short hardware; /* see to AD1848_HW_XXXX */
138 unsigned short single_dma:1; /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
139
140 snd_pcm_t *pcm;
141 snd_pcm_substream_t *playback_substream;
142 snd_pcm_substream_t *capture_substream;
143 snd_card_t *card;
144
145 unsigned char image[32]; /* SGalaxy needs an access to extended registers */
146 int mce_bit;
147 int calibrate_mute;
148 int dma_size;
149 int thinkpad_flag; /* Thinkpad CS4248 needs some extra help */
150
151 spinlock_t reg_lock;
152 struct semaphore open_mutex;
153};
154
155typedef struct _snd_ad1848 ad1848_t;
156
157/* exported functions */
158
159void snd_ad1848_out(ad1848_t *chip, unsigned char reg, unsigned char value);
160
161int snd_ad1848_create(snd_card_t * card,
162 unsigned long port,
163 int irq, int dma,
164 unsigned short hardware,
165 ad1848_t ** chip);
166
167int snd_ad1848_pcm(ad1848_t * chip, int device, snd_pcm_t **rpcm);
168const snd_pcm_ops_t *snd_ad1848_get_pcm_ops(int direction);
169int snd_ad1848_mixer(ad1848_t * chip);
170
171/* exported mixer stuffs */
172enum { AD1848_MIX_SINGLE, AD1848_MIX_DOUBLE, AD1848_MIX_CAPTURE };
173
174#define AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) \
175 ((reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24))
176#define AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) \
177 ((left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22))
178
179int snd_ad1848_add_ctl(ad1848_t *chip, const char *name, int index, int type, unsigned long value);
180
181/* for ease of use */
182struct ad1848_mix_elem {
183 const char *name;
184 int index;
185 int type;
186 unsigned long private_value;
187};
188
189#define AD1848_SINGLE(xname, xindex, reg, shift, mask, invert) \
190{ .name = xname, \
191 .index = xindex, \
192 .type = AD1848_MIX_SINGLE, \
193 .private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) }
194
195#define AD1848_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
196{ .name = xname, \
197 .index = xindex, \
198 .type = AD1848_MIX_DOUBLE, \
199 .private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) }
200
201static inline int snd_ad1848_add_ctl_elem(ad1848_t *chip, const struct ad1848_mix_elem *c)
202{
203 return snd_ad1848_add_ctl(chip, c->name, c->index, c->type, c->private_value);
204}
205
206#endif /* __SOUND_AD1848_H */
diff --git a/include/sound/ainstr_fm.h b/include/sound/ainstr_fm.h
new file mode 100644
index 000000000000..0ec02953815a
--- /dev/null
+++ b/include/sound/ainstr_fm.h
@@ -0,0 +1,130 @@
1/*
2 * Advanced Linux Sound Architecture
3 *
4 * FM (OPL2/3) Instrument Format
5 * Copyright (c) 2000 Uros Bizjak <uros@kss-loka.si>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __SOUND_AINSTR_FM_H
25#define __SOUND_AINSTR_FM_H
26
27#ifndef __KERNEL__
28#include <asm/types.h>
29#include <asm/byteorder.h>
30#endif
31
32/*
33 * share types (share ID 1)
34 */
35
36#define FM_SHARE_FILE 0
37
38/*
39 * FM operator
40 */
41
42typedef struct fm_operator {
43 unsigned char am_vib;
44 unsigned char ksl_level;
45 unsigned char attack_decay;
46 unsigned char sustain_release;
47 unsigned char wave_select;
48} fm_operator_t;
49
50/*
51 * Instrument
52 */
53
54#define FM_PATCH_OPL2 0x01 /* OPL2 2 operators FM instrument */
55#define FM_PATCH_OPL3 0x02 /* OPL3 4 operators FM instrument */
56
57typedef struct {
58 unsigned int share_id[4]; /* share id - zero = no sharing */
59 unsigned char type; /* instrument type */
60
61 fm_operator_t op[4];
62 unsigned char feedback_connection[2];
63
64 unsigned char echo_delay;
65 unsigned char echo_atten;
66 unsigned char chorus_spread;
67 unsigned char trnsps;
68 unsigned char fix_dur;
69 unsigned char modes;
70 unsigned char fix_key;
71} fm_instrument_t;
72
73/*
74 *
75 * Kernel <-> user space
76 * Hardware (CPU) independent section
77 *
78 * * = zero or more
79 * + = one or more
80 *
81 * fm_xinstrument FM_STRU_INSTR
82 *
83 */
84
85#define FM_STRU_INSTR __cpu_to_be32(('I'<<24)|('N'<<16)|('S'<<8)|'T')
86
87/*
88 * FM operator
89 */
90
91typedef struct fm_xoperator {
92 __u8 am_vib;
93 __u8 ksl_level;
94 __u8 attack_decay;
95 __u8 sustain_release;
96 __u8 wave_select;
97} fm_xoperator_t;
98
99/*
100 * Instrument
101 */
102
103typedef struct fm_xinstrument {
104 __u32 stype; /* structure type */
105
106 __u32 share_id[4]; /* share id - zero = no sharing */
107 __u8 type; /* instrument type */
108
109 fm_xoperator_t op[4]; /* fm operators */
110 __u8 feedback_connection[2];
111
112 __u8 echo_delay;
113 __u8 echo_atten;
114 __u8 chorus_spread;
115 __u8 trnsps;
116 __u8 fix_dur;
117 __u8 modes;
118 __u8 fix_key;
119} fm_xinstrument_t;
120
121#ifdef __KERNEL__
122
123#include "seq_instr.h"
124
125int snd_seq_fm_init(snd_seq_kinstr_ops_t * ops,
126 snd_seq_kinstr_ops_t * next);
127
128#endif
129
130#endif /* __SOUND_AINSTR_FM_H */
diff --git a/include/sound/ainstr_gf1.h b/include/sound/ainstr_gf1.h
new file mode 100644
index 000000000000..ae2ddda63971
--- /dev/null
+++ b/include/sound/ainstr_gf1.h
@@ -0,0 +1,225 @@
1/*
2 * Advanced Linux Sound Architecture
3 *
4 * GF1 (GUS) Patch Instrument Format
5 * Copyright (c) 1994-99 by Jaroslav Kysela <perex@suse.cz>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __SOUND_AINSTR_GF1_H
25#define __SOUND_AINSTR_GF1_H
26
27#ifndef __KERNEL__
28#include <asm/types.h>
29#include <asm/byteorder.h>
30#endif
31
32/*
33 * share types (share ID 1)
34 */
35
36#define GF1_SHARE_FILE 0
37
38/*
39 * wave formats
40 */
41
42#define GF1_WAVE_16BIT 0x0001 /* 16-bit wave */
43#define GF1_WAVE_UNSIGNED 0x0002 /* unsigned wave */
44#define GF1_WAVE_INVERT 0x0002 /* same as unsigned wave */
45#define GF1_WAVE_BACKWARD 0x0004 /* backward mode (maybe used for reverb or ping-ping loop) */
46#define GF1_WAVE_LOOP 0x0008 /* loop mode */
47#define GF1_WAVE_BIDIR 0x0010 /* bidirectional mode */
48#define GF1_WAVE_STEREO 0x0100 /* stereo mode */
49#define GF1_WAVE_ULAW 0x0200 /* uLaw compression mode */
50
51/*
52 * Wavetable definitions
53 */
54
55typedef struct gf1_wave {
56 unsigned int share_id[4]; /* share id - zero = no sharing */
57 unsigned int format; /* wave format */
58
59 struct {
60 unsigned int number; /* some other ID for this instrument */
61 unsigned int memory; /* begin of waveform in onboard memory */
62 unsigned char *ptr; /* pointer to waveform in system memory */
63 } address;
64
65 unsigned int size; /* size of waveform in samples */
66 unsigned int start; /* start offset in samples * 16 (lowest 4 bits - fraction) */
67 unsigned int loop_start; /* bits loop start offset in samples * 16 (lowest 4 bits - fraction) */
68 unsigned int loop_end; /* loop start offset in samples * 16 (lowest 4 bits - fraction) */
69 unsigned short loop_repeat; /* loop repeat - 0 = forever */
70
71 unsigned char flags; /* GF1 patch flags */
72 unsigned char pad;
73 unsigned int sample_rate; /* sample rate in Hz */
74 unsigned int low_frequency; /* low frequency range */
75 unsigned int high_frequency; /* high frequency range */
76 unsigned int root_frequency; /* root frequency range */
77 signed short tune;
78 unsigned char balance;
79 unsigned char envelope_rate[6];
80 unsigned char envelope_offset[6];
81 unsigned char tremolo_sweep;
82 unsigned char tremolo_rate;
83 unsigned char tremolo_depth;
84 unsigned char vibrato_sweep;
85 unsigned char vibrato_rate;
86 unsigned char vibrato_depth;
87 unsigned short scale_frequency;
88 unsigned short scale_factor; /* 0-2048 or 0-2 */
89
90 struct gf1_wave *next;
91} gf1_wave_t;
92
93/*
94 * Instrument
95 */
96
97#define IWFFFF_EXCLUDE_NONE 0x0000 /* exclusion mode - none */
98#define IWFFFF_EXCLUDE_SINGLE 0x0001 /* exclude single - single note from the instrument group */
99#define IWFFFF_EXCLUDE_MULTIPLE 0x0002 /* exclude multiple - stop only same note from this instrument */
100
101#define IWFFFF_EFFECT_NONE 0
102#define IWFFFF_EFFECT_REVERB 1
103#define IWFFFF_EFFECT_CHORUS 2
104#define IWFFFF_EFFECT_ECHO 3
105
106typedef struct {
107 unsigned short exclusion;
108 unsigned short exclusion_group; /* 0 - none, 1-65535 */
109
110 unsigned char effect1; /* effect 1 */
111 unsigned char effect1_depth; /* 0-127 */
112 unsigned char effect2; /* effect 2 */
113 unsigned char effect2_depth; /* 0-127 */
114
115 gf1_wave_t *wave; /* first waveform */
116} gf1_instrument_t;
117
118/*
119 *
120 * Kernel <-> user space
121 * Hardware (CPU) independent section
122 *
123 * * = zero or more
124 * + = one or more
125 *
126 * gf1_xinstrument IWFFFF_STRU_INSTR
127 * +gf1_xwave IWFFFF_STRU_WAVE
128 *
129 */
130
131#define GF1_STRU_WAVE __cpu_to_be32(('W'<<24)|('A'<<16)|('V'<<8)|'E')
132#define GF1_STRU_INSTR __cpu_to_be32(('I'<<24)|('N'<<16)|('S'<<8)|'T')
133
134/*
135 * Wavetable definitions
136 */
137
138typedef struct gf1_xwave {
139 __u32 stype; /* structure type */
140
141 __u32 share_id[4]; /* share id - zero = no sharing */
142 __u32 format; /* wave format */
143
144 __u32 size; /* size of waveform in samples */
145 __u32 start; /* start offset in samples * 16 (lowest 4 bits - fraction) */
146 __u32 loop_start; /* bits loop start offset in samples * 16 (lowest 4 bits - fraction) */
147 __u32 loop_end; /* loop start offset in samples * 16 (lowest 4 bits - fraction) */
148 __u16 loop_repeat; /* loop repeat - 0 = forever */
149
150 __u8 flags; /* GF1 patch flags */
151 __u8 pad;
152 __u32 sample_rate; /* sample rate in Hz */
153 __u32 low_frequency; /* low frequency range */
154 __u32 high_frequency; /* high frequency range */
155 __u32 root_frequency; /* root frequency range */
156 __s16 tune;
157 __u8 balance;
158 __u8 envelope_rate[6];
159 __u8 envelope_offset[6];
160 __u8 tremolo_sweep;
161 __u8 tremolo_rate;
162 __u8 tremolo_depth;
163 __u8 vibrato_sweep;
164 __u8 vibrato_rate;
165 __u8 vibrato_depth;
166 __u16 scale_frequency;
167 __u16 scale_factor; /* 0-2048 or 0-2 */
168} gf1_xwave_t;
169
170/*
171 * Instrument
172 */
173
174typedef struct gf1_xinstrument {
175 __u32 stype;
176
177 __u16 exclusion;
178 __u16 exclusion_group; /* 0 - none, 1-65535 */
179
180 __u8 effect1; /* effect 1 */
181 __u8 effect1_depth; /* 0-127 */
182 __u8 effect2; /* effect 2 */
183 __u8 effect2_depth; /* 0-127 */
184} gf1_xinstrument_t;
185
186/*
187 * Instrument info
188 */
189
190#define GF1_INFO_ENVELOPE (1<<0)
191#define GF1_INFO_TREMOLO (1<<1)
192#define GF1_INFO_VIBRATO (1<<2)
193
194typedef struct gf1_info {
195 unsigned char flags; /* supported wave flags */
196 unsigned char pad[3];
197 unsigned int features; /* supported features */
198 unsigned int max8_len; /* maximum 8-bit wave length */
199 unsigned int max16_len; /* maximum 16-bit wave length */
200} gf1_info_t;
201
202#ifdef __KERNEL__
203
204#include "seq_instr.h"
205
206typedef struct {
207 void *private_data;
208 int (*info)(void *private_data, gf1_info_t *info);
209 int (*put_sample)(void *private_data, gf1_wave_t *wave,
210 char __user *data, long len, int atomic);
211 int (*get_sample)(void *private_data, gf1_wave_t *wave,
212 char __user *data, long len, int atomic);
213 int (*remove_sample)(void *private_data, gf1_wave_t *wave,
214 int atomic);
215 void (*notify)(void *private_data, snd_seq_kinstr_t *instr, int what);
216 snd_seq_kinstr_ops_t kops;
217} snd_gf1_ops_t;
218
219int snd_seq_gf1_init(snd_gf1_ops_t *ops,
220 void *private_data,
221 snd_seq_kinstr_ops_t *next);
222
223#endif
224
225#endif /* __SOUND_AINSTR_GF1_H */
diff --git a/include/sound/ainstr_iw.h b/include/sound/ainstr_iw.h
new file mode 100644
index 000000000000..8adf744926ff
--- /dev/null
+++ b/include/sound/ainstr_iw.h
@@ -0,0 +1,373 @@
1/*
2 * Advanced Linux Sound Architecture
3 *
4 * InterWave FFFF Instrument Format
5 * Copyright (c) 1994-99 by Jaroslav Kysela <perex@suse.cz>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __SOUND_AINSTR_IW_H
25#define __SOUND_AINSTR_IW_H
26
27#ifndef __KERNEL__
28#include <asm/types.h>
29#include <asm/byteorder.h>
30#endif
31
32/*
33 * share types (share ID 1)
34 */
35
36#define IWFFFF_SHARE_FILE 0
37
38/*
39 * wave formats
40 */
41
42#define IWFFFF_WAVE_16BIT 0x0001 /* 16-bit wave */
43#define IWFFFF_WAVE_UNSIGNED 0x0002 /* unsigned wave */
44#define IWFFFF_WAVE_INVERT 0x0002 /* same as unsigned wave */
45#define IWFFFF_WAVE_BACKWARD 0x0004 /* backward mode (maybe used for reverb or ping-ping loop) */
46#define IWFFFF_WAVE_LOOP 0x0008 /* loop mode */
47#define IWFFFF_WAVE_BIDIR 0x0010 /* bidirectional mode */
48#define IWFFFF_WAVE_ULAW 0x0020 /* uLaw compressed wave */
49#define IWFFFF_WAVE_RAM 0x0040 /* wave is _preloaded_ in RAM (it is used for ROM simulation) */
50#define IWFFFF_WAVE_ROM 0x0080 /* wave is in ROM */
51#define IWFFFF_WAVE_STEREO 0x0100 /* wave is stereo */
52
53/*
54 * Wavetable definitions
55 */
56
57typedef struct iwffff_wave {
58 unsigned int share_id[4]; /* share id - zero = no sharing */
59 unsigned int format; /* wave format */
60
61 struct {
62 unsigned int number; /* some other ID for this wave */
63 unsigned int memory; /* begin of waveform in onboard memory */
64 unsigned char *ptr; /* pointer to waveform in system memory */
65 } address;
66
67 unsigned int size; /* size of waveform in samples */
68 unsigned int start; /* start offset in samples * 16 (lowest 4 bits - fraction) */
69 unsigned int loop_start; /* bits loop start offset in samples * 16 (lowest 4 bits - fraction) */
70 unsigned int loop_end; /* loop start offset in samples * 16 (lowest 4 bits - fraction) */
71 unsigned short loop_repeat; /* loop repeat - 0 = forever */
72 unsigned int sample_ratio; /* sample ratio (44100 * 1024 / rate) */
73 unsigned char attenuation; /* 0 - 127 (no corresponding midi controller) */
74 unsigned char low_note; /* lower frequency range for this waveform */
75 unsigned char high_note; /* higher frequency range for this waveform */
76 unsigned char pad;
77
78 struct iwffff_wave *next;
79} iwffff_wave_t;
80
81/*
82 * Layer
83 */
84
85#define IWFFFF_LFO_SHAPE_TRIANGLE 0
86#define IWFFFF_LFO_SHAPE_POSTRIANGLE 1
87
88typedef struct iwffff_lfo {
89 unsigned short freq; /* (0-2047) 0.01Hz - 21.5Hz */
90 signed short depth; /* volume +- (0-255) 0.48675dB/step */
91 signed short sweep; /* 0 - 950 deciseconds */
92 unsigned char shape; /* see to IWFFFF_LFO_SHAPE_XXXX */
93 unsigned char delay; /* 0 - 255 deciseconds */
94} iwffff_lfo_t;
95
96#define IWFFFF_ENV_FLAG_RETRIGGER 0x0001 /* flag - retrigger */
97
98#define IWFFFF_ENV_MODE_ONE_SHOT 0x0001 /* mode - one shot */
99#define IWFFFF_ENV_MODE_SUSTAIN 0x0002 /* mode - sustain */
100#define IWFFFF_ENV_MODE_NO_SUSTAIN 0x0003 /* mode - no sustain */
101
102#define IWFFFF_ENV_INDEX_VELOCITY 0x0001 /* index - velocity */
103#define IWFFFF_ENV_INDEX_FREQUENCY 0x0002 /* index - frequency */
104
105typedef struct iwffff_env_point {
106 unsigned short offset;
107 unsigned short rate;
108} iwffff_env_point_t;
109
110typedef struct iwffff_env_record {
111 unsigned short nattack;
112 unsigned short nrelease;
113 unsigned short sustain_offset;
114 unsigned short sustain_rate;
115 unsigned short release_rate;
116 unsigned char hirange;
117 unsigned char pad;
118 struct iwffff_env_record *next;
119 /* points are stored here */
120 /* count of points = nattack + nrelease */
121} iwffff_env_record_t;
122
123typedef struct iwffff_env {
124 unsigned char flags;
125 unsigned char mode;
126 unsigned char index;
127 unsigned char pad;
128 struct iwffff_env_record *record;
129} iwffff_env_t;
130
131#define IWFFFF_LAYER_FLAG_RETRIGGER 0x0001 /* retrigger */
132
133#define IWFFFF_LAYER_VELOCITY_TIME 0x0000 /* velocity mode = time */
134#define IWFFFF_LAYER_VELOCITY_RATE 0x0001 /* velocity mode = rate */
135
136#define IWFFFF_LAYER_EVENT_KUP 0x0000 /* layer event - key up */
137#define IWFFFF_LAYER_EVENT_KDOWN 0x0001 /* layer event - key down */
138#define IWFFFF_LAYER_EVENT_RETRIG 0x0002 /* layer event - retrigger */
139#define IWFFFF_LAYER_EVENT_LEGATO 0x0003 /* layer event - legato */
140
141typedef struct iwffff_layer {
142 unsigned char flags;
143 unsigned char velocity_mode;
144 unsigned char layer_event;
145 unsigned char low_range; /* range for layer based */
146 unsigned char high_range; /* on either velocity or frequency */
147 unsigned char pan; /* pan offset from CC1 (0 left - 127 right) */
148 unsigned char pan_freq_scale; /* position based on frequency (0-127) */
149 unsigned char attenuation; /* 0-127 (no corresponding midi controller) */
150 iwffff_lfo_t tremolo; /* tremolo effect */
151 iwffff_lfo_t vibrato; /* vibrato effect */
152 unsigned short freq_scale; /* 0-2048, 1024 is equal to semitone scaling */
153 unsigned char freq_center; /* center for keyboard frequency scaling */
154 unsigned char pad;
155 iwffff_env_t penv; /* pitch envelope */
156 iwffff_env_t venv; /* volume envelope */
157
158 iwffff_wave_t *wave;
159 struct iwffff_layer *next;
160} iwffff_layer_t;
161
162/*
163 * Instrument
164 */
165
166#define IWFFFF_EXCLUDE_NONE 0x0000 /* exclusion mode - none */
167#define IWFFFF_EXCLUDE_SINGLE 0x0001 /* exclude single - single note from the instrument group */
168#define IWFFFF_EXCLUDE_MULTIPLE 0x0002 /* exclude multiple - stop only same note from this instrument */
169
170#define IWFFFF_LAYER_NONE 0x0000 /* not layered */
171#define IWFFFF_LAYER_ON 0x0001 /* layered */
172#define IWFFFF_LAYER_VELOCITY 0x0002 /* layered by velocity */
173#define IWFFFF_LAYER_FREQUENCY 0x0003 /* layered by frequency */
174
175#define IWFFFF_EFFECT_NONE 0
176#define IWFFFF_EFFECT_REVERB 1
177#define IWFFFF_EFFECT_CHORUS 2
178#define IWFFFF_EFFECT_ECHO 3
179
180typedef struct {
181 unsigned short exclusion;
182 unsigned short layer_type;
183 unsigned short exclusion_group; /* 0 - none, 1-65535 */
184
185 unsigned char effect1; /* effect 1 */
186 unsigned char effect1_depth; /* 0-127 */
187 unsigned char effect2; /* effect 2 */
188 unsigned char effect2_depth; /* 0-127 */
189
190 iwffff_layer_t *layer; /* first layer */
191} iwffff_instrument_t;
192
193/*
194 *
195 * Kernel <-> user space
196 * Hardware (CPU) independent section
197 *
198 * * = zero or more
199 * + = one or more
200 *
201 * iwffff_xinstrument IWFFFF_STRU_INSTR
202 * +iwffff_xlayer IWFFFF_STRU_LAYER
203 * *iwffff_xenv_record IWFFFF_STRU_ENV_RECT (tremolo)
204 * *iwffff_xenv_record IWFFFF_STRU_EVN_RECT (vibrato)
205 * +iwffff_xwave IWFFFF_STRU_WAVE
206 *
207 */
208
209#define IWFFFF_STRU_WAVE __cpu_to_be32(('W'<<24)|('A'<<16)|('V'<<8)|'E')
210#define IWFFFF_STRU_ENV_RECP __cpu_to_be32(('E'<<24)|('N'<<16)|('R'<<8)|'P')
211#define IWFFFF_STRU_ENV_RECV __cpu_to_be32(('E'<<24)|('N'<<16)|('R'<<8)|'V')
212#define IWFFFF_STRU_LAYER __cpu_to_be32(('L'<<24)|('A'<<16)|('Y'<<8)|'R')
213#define IWFFFF_STRU_INSTR __cpu_to_be32(('I'<<24)|('N'<<16)|('S'<<8)|'T')
214
215/*
216 * Wavetable definitions
217 */
218
219typedef struct iwffff_xwave {
220 __u32 stype; /* structure type */
221
222 __u32 share_id[4]; /* share id - zero = no sharing */
223
224 __u32 format; /* wave format */
225 __u32 offset; /* offset to ROM (address) */
226
227 __u32 size; /* size of waveform in samples */
228 __u32 start; /* start offset in samples * 16 (lowest 4 bits - fraction) */
229 __u32 loop_start; /* bits loop start offset in samples * 16 (lowest 4 bits - fraction) */
230 __u32 loop_end; /* loop start offset in samples * 16 (lowest 4 bits - fraction) */
231 __u16 loop_repeat; /* loop repeat - 0 = forever */
232 __u32 sample_ratio; /* sample ratio (44100 * 1024 / rate) */
233 __u8 attenuation; /* 0 - 127 (no corresponding midi controller) */
234 __u8 low_note; /* lower frequency range for this waveform */
235 __u8 high_note; /* higher frequency range for this waveform */
236 __u8 pad;
237} iwffff_xwave_t;
238
239/*
240 * Layer
241 */
242
243typedef struct iwffff_xlfo {
244 __u16 freq; /* (0-2047) 0.01Hz - 21.5Hz */
245 __s16 depth; /* volume +- (0-255) 0.48675dB/step */
246 __s16 sweep; /* 0 - 950 deciseconds */
247 __u8 shape; /* see to ULTRA_IW_LFO_SHAPE_XXXX */
248 __u8 delay; /* 0 - 255 deciseconds */
249} iwffff_xlfo_t;
250
251typedef struct iwffff_xenv_point {
252 __u16 offset;
253 __u16 rate;
254} iwffff_xenv_point_t;
255
256typedef struct iwffff_xenv_record {
257 __u32 stype;
258 __u16 nattack;
259 __u16 nrelease;
260 __u16 sustain_offset;
261 __u16 sustain_rate;
262 __u16 release_rate;
263 __u8 hirange;
264 __u8 pad;
265 /* points are stored here.. */
266 /* count of points = nattack + nrelease */
267} iwffff_xenv_record_t;
268
269typedef struct iwffff_xenv {
270 __u8 flags;
271 __u8 mode;
272 __u8 index;
273 __u8 pad;
274} iwffff_xenv_t;
275
276typedef struct iwffff_xlayer {
277 __u32 stype;
278 __u8 flags;
279 __u8 velocity_mode;
280 __u8 layer_event;
281 __u8 low_range; /* range for layer based */
282 __u8 high_range; /* on either velocity or frequency */
283 __u8 pan; /* pan offset from CC1 (0 left - 127 right) */
284 __u8 pan_freq_scale; /* position based on frequency (0-127) */
285 __u8 attenuation; /* 0-127 (no corresponding midi controller) */
286 iwffff_xlfo_t tremolo; /* tremolo effect */
287 iwffff_xlfo_t vibrato; /* vibrato effect */
288 __u16 freq_scale; /* 0-2048, 1024 is equal to semitone scaling */
289 __u8 freq_center; /* center for keyboard frequency scaling */
290 __u8 pad;
291 iwffff_xenv_t penv; /* pitch envelope */
292 iwffff_xenv_t venv; /* volume envelope */
293} iwffff_xlayer_t;
294
295/*
296 * Instrument
297 */
298
299typedef struct iwffff_xinstrument {
300 __u32 stype;
301
302 __u16 exclusion;
303 __u16 layer_type;
304 __u16 exclusion_group; /* 0 - none, 1-65535 */
305
306 __u8 effect1; /* effect 1 */
307 __u8 effect1_depth; /* 0-127 */
308 __u8 effect2; /* effect 2 */
309 __u8 effect2_depth; /* 0-127 */
310} iwffff_xinstrument_t;
311
312/*
313 * ROM support
314 * InterWave ROMs are Little-Endian (x86)
315 */
316
317#define IWFFFF_ROM_HDR_SIZE 512
318
319typedef struct {
320 __u8 iwave[8];
321 __u8 revision;
322 __u8 series_number;
323 __u8 series_name[16];
324 __u8 date[10];
325 __u16 vendor_revision_major;
326 __u16 vendor_revision_minor;
327 __u32 rom_size;
328 __u8 copyright[128];
329 __u8 vendor_name[64];
330 __u8 description[128];
331} iwffff_rom_header_t;
332
333/*
334 * Instrument info
335 */
336
337#define IWFFFF_INFO_LFO_VIBRATO (1<<0)
338#define IWFFFF_INFO_LFO_VIBRATO_SHAPE (1<<1)
339#define IWFFFF_INFO_LFO_TREMOLO (1<<2)
340#define IWFFFF_INFO_LFO_TREMOLO_SHAPE (1<<3)
341
342typedef struct iwffff_info {
343 unsigned int format; /* supported format bits */
344 unsigned int effects; /* supported effects (1 << IWFFFF_EFFECT*) */
345 unsigned int lfos; /* LFO effects */
346 unsigned int max8_len; /* maximum 8-bit wave length */
347 unsigned int max16_len; /* maximum 16-bit wave length */
348} iwffff_info_t;
349
350#ifdef __KERNEL__
351
352#include "seq_instr.h"
353
354typedef struct {
355 void *private_data;
356 int (*info)(void *private_data, iwffff_info_t *info);
357 int (*put_sample)(void *private_data, iwffff_wave_t *wave,
358 char __user *data, long len, int atomic);
359 int (*get_sample)(void *private_data, iwffff_wave_t *wave,
360 char __user *data, long len, int atomic);
361 int (*remove_sample)(void *private_data, iwffff_wave_t *wave,
362 int atomic);
363 void (*notify)(void *private_data, snd_seq_kinstr_t *instr, int what);
364 snd_seq_kinstr_ops_t kops;
365} snd_iwffff_ops_t;
366
367int snd_seq_iwffff_init(snd_iwffff_ops_t *ops,
368 void *private_data,
369 snd_seq_kinstr_ops_t *next);
370
371#endif
372
373#endif /* __SOUND_AINSTR_IW_H */
diff --git a/include/sound/ainstr_simple.h b/include/sound/ainstr_simple.h
new file mode 100644
index 000000000000..40824b4ab23d
--- /dev/null
+++ b/include/sound/ainstr_simple.h
@@ -0,0 +1,156 @@
1/*
2 * Advanced Linux Sound Architecture
3 *
4 * Simple (MOD player) Instrument Format
5 * Copyright (c) 1994-99 by Jaroslav Kysela <perex@suse.cz>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __SOUND_AINSTR_SIMPLE_H
25#define __SOUND_AINSTR_SIMPLE_H
26
27#ifndef __KERNEL__
28#include <asm/types.h>
29#include <asm/byteorder.h>
30#endif
31
32/*
33 * share types (share ID 1)
34 */
35
36#define SIMPLE_SHARE_FILE 0
37
38/*
39 * wave formats
40 */
41
42#define SIMPLE_WAVE_16BIT 0x0001 /* 16-bit wave */
43#define SIMPLE_WAVE_UNSIGNED 0x0002 /* unsigned wave */
44#define SIMPLE_WAVE_INVERT 0x0002 /* same as unsigned wave */
45#define SIMPLE_WAVE_BACKWARD 0x0004 /* backward mode (maybe used for reverb or ping-ping loop) */
46#define SIMPLE_WAVE_LOOP 0x0008 /* loop mode */
47#define SIMPLE_WAVE_BIDIR 0x0010 /* bidirectional mode */
48#define SIMPLE_WAVE_STEREO 0x0100 /* stereo wave */
49#define SIMPLE_WAVE_ULAW 0x0200 /* uLaw compression mode */
50
51/*
52 * instrument effects
53 */
54
55#define SIMPLE_EFFECT_NONE 0
56#define SIMPLE_EFFECT_REVERB 1
57#define SIMPLE_EFFECT_CHORUS 2
58#define SIMPLE_EFFECT_ECHO 3
59
60/*
61 * instrument info
62 */
63
64typedef struct simple_instrument_info {
65 unsigned int format; /* supported format bits */
66 unsigned int effects; /* supported effects (1 << SIMPLE_EFFECT_*) */
67 unsigned int max8_len; /* maximum 8-bit wave length */
68 unsigned int max16_len; /* maximum 16-bit wave length */
69} simple_instrument_info_t;
70
71/*
72 * Instrument
73 */
74
75typedef struct {
76 unsigned int share_id[4]; /* share id - zero = no sharing */
77 unsigned int format; /* wave format */
78
79 struct {
80 unsigned int number; /* some other ID for this instrument */
81 unsigned int memory; /* begin of waveform in onboard memory */
82 unsigned char *ptr; /* pointer to waveform in system memory */
83 } address;
84
85 unsigned int size; /* size of waveform in samples */
86 unsigned int start; /* start offset in samples * 16 (lowest 4 bits - fraction) */
87 unsigned int loop_start; /* loop start offset in samples * 16 (lowest 4 bits - fraction) */
88 unsigned int loop_end; /* loop end offset in samples * 16 (lowest 4 bits - fraction) */
89 unsigned short loop_repeat; /* loop repeat - 0 = forever */
90
91 unsigned char effect1; /* effect 1 */
92 unsigned char effect1_depth; /* 0-127 */
93 unsigned char effect2; /* effect 2 */
94 unsigned char effect2_depth; /* 0-127 */
95} simple_instrument_t;
96
97/*
98 *
99 * Kernel <-> user space
100 * Hardware (CPU) independent section
101 *
102 * * = zero or more
103 * + = one or more
104 *
105 * simple_xinstrument SIMPLE_STRU_INSTR
106 *
107 */
108
109#define SIMPLE_STRU_INSTR __cpu_to_be32(('I'<<24)|('N'<<16)|('S'<<8)|'T')
110
111/*
112 * Instrument
113 */
114
115typedef struct simple_xinstrument {
116 __u32 stype;
117
118 __u32 share_id[4]; /* share id - zero = no sharing */
119 __u32 format; /* wave format */
120
121 __u32 size; /* size of waveform in samples */
122 __u32 start; /* start offset in samples * 16 (lowest 4 bits - fraction) */
123 __u32 loop_start; /* bits loop start offset in samples * 16 (lowest 4 bits - fraction) */
124 __u32 loop_end; /* loop start offset in samples * 16 (lowest 4 bits - fraction) */
125 __u16 loop_repeat; /* loop repeat - 0 = forever */
126
127 __u8 effect1; /* effect 1 */
128 __u8 effect1_depth; /* 0-127 */
129 __u8 effect2; /* effect 2 */
130 __u8 effect2_depth; /* 0-127 */
131} simple_xinstrument_t;
132
133#ifdef __KERNEL__
134
135#include "seq_instr.h"
136
137typedef struct {
138 void *private_data;
139 int (*info)(void *private_data, simple_instrument_info_t *info);
140 int (*put_sample)(void *private_data, simple_instrument_t *instr,
141 char __user *data, long len, int atomic);
142 int (*get_sample)(void *private_data, simple_instrument_t *instr,
143 char __user *data, long len, int atomic);
144 int (*remove_sample)(void *private_data, simple_instrument_t *instr,
145 int atomic);
146 void (*notify)(void *private_data, snd_seq_kinstr_t *instr, int what);
147 snd_seq_kinstr_ops_t kops;
148} snd_simple_ops_t;
149
150int snd_seq_simple_init(snd_simple_ops_t *ops,
151 void *private_data,
152 snd_seq_kinstr_ops_t *next);
153
154#endif
155
156#endif /* __SOUND_AINSTR_SIMPLE_H */
diff --git a/include/sound/ak4114.h b/include/sound/ak4114.h
new file mode 100644
index 000000000000..f3f2c3e5ae51
--- /dev/null
+++ b/include/sound/ak4114.h
@@ -0,0 +1,205 @@
1#ifndef __SOUND_AK4114_H
2#define __SOUND_AK4114_H
3
4/*
5 * Routines for Asahi Kasei AK4114
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25/* AK4114 registers */
26#define AK4114_REG_PWRDN 0x00 /* power down */
27#define AK4114_REG_FORMAT 0x01 /* format control */
28#define AK4114_REG_IO0 0x02 /* input/output control */
29#define AK4114_REG_IO1 0x03 /* input/output control */
30#define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */
31#define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */
32#define AK4114_REG_RCS0 0x06 /* receiver status 0 */
33#define AK4114_REG_RCS1 0x07 /* receiver status 1 */
34#define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
35#define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */
36#define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */
37#define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */
38#define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */
39#define AK4114_REG_TXCSB0 0x0d /* TX channel status byte 0 */
40#define AK4114_REG_TXCSB1 0x0e /* TX channel status byte 1 */
41#define AK4114_REG_TXCSB2 0x0f /* TX channel status byte 2 */
42#define AK4114_REG_TXCSB3 0x10 /* TX channel status byte 3 */
43#define AK4114_REG_TXCSB4 0x11 /* TX channel status byte 4 */
44#define AK4114_REG_Pc0 0x12 /* burst preamble Pc byte 0 */
45#define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */
46#define AK4114_REG_Pd0 0x14 /* burst preamble Pd byte 0 */
47#define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */
48#define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
49#define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
50#define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
51#define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
52#define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
53#define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
54#define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
55#define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
56#define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
57#define AK4114_REG_QSUB_ABSFRM 0x1f /* Q-subcode absolute frame */
58
59/* sizes */
60#define AK4114_REG_RXCSB_SIZE ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1)
61#define AK4114_REG_TXCSB_SIZE ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1)
62#define AK4114_REG_QSUB_SIZE ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1)
63
64/* AK4117_REG_PWRDN bits */
65#define AK4114_CS12 (1<<7) /* Channel Status Select */
66#define AK4114_BCU (1<<6) /* Block Start & C/U Output Mode */
67#define AK4114_CM1 (1<<5) /* Master Clock Operation Select */
68#define AK4114_CM0 (1<<4) /* Master Clock Operation Select */
69#define AK4114_OCKS1 (1<<3) /* Master Clock Frequency Select */
70#define AK4114_OCKS0 (1<<2) /* Master Clock Frequency Select */
71#define AK4114_PWN (1<<1) /* 0 = power down, 1 = normal operation */
72#define AK4114_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */
73
74/* AK4114_REQ_FORMAT bits */
75#define AK4114_MONO (1<<7) /* Double Sampling Frequency Mode: 0 = stereo, 1 = mono */
76#define AK4114_DIF2 (1<<5) /* Audio Data Control */
77#define AK4114_DIF1 (1<<5) /* Audio Data Control */
78#define AK4114_DIF0 (1<<4) /* Audio Data Control */
79#define AK4114_DIF_16R (0) /* STDO: 16-bit, right justified */
80#define AK4114_DIF_18R (AK4114_DIF0) /* STDO: 18-bit, right justified */
81#define AK4114_DIF_20R (AK4114_DIF1) /* STDO: 20-bit, right justified */
82#define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */
83#define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */
84#define AK4114_DIF_24I2S (AK4114_DIF2|AK4114_DIF0) /* STDO: I2S */
85#define AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = Input */
86#define AK4114_DIF_I24I2S (AK4114_DIF2|AK4114_DIF1|AK4114_DIF0) /* STDO: I2S; LRCLK, BICK = Input */
87#define AK4114_DEAU (1<<3) /* Deemphasis Autodetect Enable (1 = enable) */
88#define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */
89#define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis Control */
90#define AK4114_DEM_44KHZ (0)
91#define AK4114_DEM_48KHZ (AK4114_DEM1)
92#define AK4114_DEM_32KHZ (AK4114_DEM0|AK4114_DEM1)
93#define AK4114_DEM_96KHZ (AK4114_DEM1) /* DFS must be set */
94#define AK4114_DFS (1<<0) /* 96kHz Deemphasis Control */
95
96/* AK4114_REG_IO0 */
97#define AK4114_TX1E (1<<7) /* TX1 Output Enable (1 = enable) */
98#define AK4114_OPS12 (1<<2) /* Output Though Data Selector for TX1 pin */
99#define AK4114_OPS11 (1<<1) /* Output Though Data Selector for TX1 pin */
100#define AK4114_OPS10 (1<<0) /* Output Though Data Selector for TX1 pin */
101#define AK4114_TX0E (1<<3) /* TX0 Output Enable (1 = enable) */
102#define AK4114_OPS02 (1<<2) /* Output Though Data Selector for TX0 pin */
103#define AK4114_OPS01 (1<<1) /* Output Though Data Selector for TX0 pin */
104#define AK4114_OPS00 (1<<0) /* Output Though Data Selector for TX0 pin */
105
106/* AK4114_REG_IO1 */
107#define AK4114_EFH1 (1<<7) /* Interrupt 0 pin Hold */
108#define AK4114_EFH0 (1<<6) /* Interrupt 0 pin Hold */
109#define AK4114_EFH_512 (0)
110#define AK4114_EFH_1024 (AK4114_EFH0)
111#define AK4114_EFH_2048 (AK4114_EFH1)
112#define AK4114_EFH_4096 (AK4114_EFH1|AK4114_EFH0)
113#define AK4114_UDIT (1<<5) /* U-bit Control for DIT (0 = fixed '0', 1 = recovered) */
114#define AK4114_TLR (1<<4) /* Double Sampling Frequency Select for DIT (0 = L channel, 1 = R channel) */
115#define AK4114_DIT (1<<3) /* TX1 out: 0 = Through Data (RX data), 1 = Transmit Data (DAUX data) */
116#define AK4114_IPS2 (1<<2) /* Input Recovery Data Select */
117#define AK4114_IPS1 (1<<1) /* Input Recovery Data Select */
118#define AK4114_IPS0 (1<<0) /* Input Recovery Data Select */
119#define AK4114_IPS(x) ((x)&7)
120
121/* AK4114_REG_INT0_MASK && AK4114_REG_INT1_MASK*/
122#define AK4117_MQI (1<<7) /* mask enable for QINT bit */
123#define AK4117_MAT (1<<6) /* mask enable for AUTO bit */
124#define AK4117_MCI (1<<5) /* mask enable for CINT bit */
125#define AK4117_MUL (1<<4) /* mask enable for UNLOCK bit */
126#define AK4117_MDTS (1<<3) /* mask enable for DTSCD bit */
127#define AK4117_MPE (1<<2) /* mask enable for PEM bit */
128#define AK4117_MAN (1<<1) /* mask enable for AUDN bit */
129#define AK4117_MPR (1<<0) /* mask enable for PAR bit */
130
131/* AK4114_REG_RCS0 */
132#define AK4114_QINT (1<<7) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
133#define AK4114_AUTO (1<<6) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
134#define AK4114_CINT (1<<5) /* channel status buffer interrupt, 0 = no change, 1 = change */
135#define AK4114_UNLCK (1<<4) /* PLL lock status, 0 = lock, 1 = unlock */
136#define AK4114_DTSCD (1<<3) /* DTS-CD Detect, 0 = No detect, 1 = Detect */
137#define AK4114_PEM (1<<2) /* Pre-emphasis Detect, 0 = OFF, 1 = ON */
138#define AK4114_AUDION (1<<1) /* audio bit output, 0 = audio, 1 = non-audio */
139#define AK4114_PAR (1<<0) /* parity error or biphase error status, 0 = no error, 1 = error */
140
141/* AK4114_REG_RCS1 */
142#define AK4114_FS3 (1<<7) /* sampling frequency detection */
143#define AK4114_FS2 (1<<6)
144#define AK4114_FS1 (1<<5)
145#define AK4114_FS0 (1<<4)
146#define AK4114_FS_44100HZ (0)
147#define AK4114_FS_48000HZ (AK4114_FS1)
148#define AK4114_FS_32000HZ (AK4114_FS1|AK4114_FS0)
149#define AK4114_FS_88200HZ (AK4114_FS3)
150#define AK4114_FS_96000HZ (AK4114_FS3|AK4114_FS1)
151#define AK4114_FS_176400HZ (AK4114_FS3|AK4114_FS2)
152#define AK4114_FS_192000HZ (AK4114_FS3|AK4114_FS2|AK4114_FS1)
153#define AK4114_V (1<<3) /* Validity of Channel Status, 0 = Valid, 1 = Invalid */
154#define AK4114_QCRC (1<<1) /* CRC for Q-subcode, 0 = no error, 1 = error */
155#define AK4114_CCRC (1<<0) /* CRC for channel status, 0 = no error, 1 = error */
156
157/* flags for snd_ak4114_check_rate_and_errors() */
158#define AK4114_CHECK_NO_STAT (1<<0) /* no statistics */
159#define AK4114_CHECK_NO_RATE (1<<1) /* no rate check */
160
161#define AK4114_CONTROLS 14
162
163typedef void (ak4114_write_t)(void *private_data, unsigned char addr, unsigned char data);
164typedef unsigned char (ak4114_read_t)(void *private_data, unsigned char addr);
165
166typedef struct ak4114 ak4114_t;
167
168struct ak4114 {
169 snd_card_t * card;
170 ak4114_write_t * write;
171 ak4114_read_t * read;
172 void * private_data;
173 unsigned int init: 1;
174 spinlock_t lock;
175 unsigned char regmap[7];
176 unsigned char txcsb[5];
177 snd_kcontrol_t *kctls[AK4114_CONTROLS];
178 snd_pcm_substream_t *playback_substream;
179 snd_pcm_substream_t *capture_substream;
180 unsigned long parity_errors;
181 unsigned long v_bit_errors;
182 unsigned long qcrc_errors;
183 unsigned long ccrc_errors;
184 unsigned char rcs0;
185 unsigned char rcs1;
186 struct workqueue_struct *workqueue;
187 struct work_struct work;
188 void *change_callback_private;
189 void (*change_callback)(ak4114_t *ak4114, unsigned char c0, unsigned char c1);
190};
191
192int snd_ak4114_create(snd_card_t *card,
193 ak4114_read_t *read, ak4114_write_t *write,
194 unsigned char pgm[7], unsigned char txcsb[5],
195 void *private_data, ak4114_t **r_ak4114);
196void snd_ak4114_reg_write(ak4114_t *ak4114, unsigned char reg, unsigned char mask, unsigned char val);
197void snd_ak4114_reinit(ak4114_t *ak4114);
198int snd_ak4114_build(ak4114_t *ak4114,
199 snd_pcm_substream_t *playback_substream,
200 snd_pcm_substream_t *capture_substream);
201int snd_ak4114_external_rate(ak4114_t *ak4114);
202int snd_ak4114_check_rate_and_errors(ak4114_t *ak4114, unsigned int flags);
203
204#endif /* __SOUND_AK4114_H */
205
diff --git a/include/sound/ak4117.h b/include/sound/ak4117.h
new file mode 100644
index 000000000000..9e1dab17c33e
--- /dev/null
+++ b/include/sound/ak4117.h
@@ -0,0 +1,191 @@
1#ifndef __SOUND_AK4117_H
2#define __SOUND_AK4117_H
3
4/*
5 * Routines for Asahi Kasei AK4117
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#define AK4117_REG_PWRDN 0x00 /* power down */
26#define AK4117_REG_CLOCK 0x01 /* clock control */
27#define AK4117_REG_IO 0x02 /* input/output control */
28#define AK4117_REG_INT0_MASK 0x03 /* interrupt0 mask */
29#define AK4117_REG_INT1_MASK 0x04 /* interrupt1 mask */
30#define AK4117_REG_RCS0 0x05 /* receiver status 0 */
31#define AK4117_REG_RCS1 0x06 /* receiver status 1 */
32#define AK4117_REG_RCS2 0x07 /* receiver status 2 */
33#define AK4117_REG_RXCSB0 0x08 /* RX channel status byte 0 */
34#define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */
35#define AK4117_REG_RXCSB2 0x0a /* RX channel status byte 2 */
36#define AK4117_REG_RXCSB3 0x0b /* RX channel status byte 3 */
37#define AK4117_REG_RXCSB4 0x0c /* RX channel status byte 4 */
38#define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */
39#define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */
40#define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */
41#define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */
42#define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
43#define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
44#define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
45#define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
46#define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
47#define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
48#define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
49#define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
50#define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
51#define AK4117_REG_QSUB_ABSFRM 0x1a /* Q-subcode absolute frame */
52
53/* sizes */
54#define AK4117_REG_RXCSB_SIZE ((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1)
55#define AK4117_REG_QSUB_SIZE ((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1)
56
57/* AK4117_REG_PWRDN bits */
58#define AK4117_EXCT (1<<4) /* 0 = X'tal mode, 1 = external clock mode */
59#define AK4117_XTL1 (1<<3) /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
60#define AK4117_XTL0 (1<<2) /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
61#define AK4117_XTL_11_2896M (0)
62#define AK4117_XTL_12_288M AK4117_XTL0
63#define AK4117_XTL_24_576M AK4117_XTL1
64#define AK4117_XTL_EXT (AK4117_XTL1|AK4117_XTL0)
65#define AK4117_PWN (1<<1) /* 0 = power down, 1 = normal operation */
66#define AK4117_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */
67
68/* AK4117_REQ_CLOCK bits */
69#define AK4117_LP (1<<7) /* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */
70#define AK4117_PKCS1 (1<<6) /* master clock frequency at PLL mode (when LP == 0) */
71#define AK4117_PKCS0 (1<<5)
72#define AK4117_PKCS_512fs (0)
73#define AK4117_PKCS_256fs AK4117_PKCS0
74#define AK4117_PKCS_128fs AK4117_PKCS1
75#define AK4117_DIV (1<<4) /* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */
76#define AK4117_XCKS1 (1<<3) /* master clock frequency at X'tal mode */
77#define AK4117_XCKS0 (1<<2)
78#define AK4117_XCKS_128fs (0)
79#define AK4117_XCKS_256fs AK4117_XCKS0
80#define AK4117_XCKS_512fs AK4117_XCKS1
81#define AK4117_XCKS_1024fs (AK4117_XCKS1|AK4117_XCKS0)
82#define AK4117_CM1 (1<<1) /* MCKO operation mode select */
83#define AK4117_CM0 (1<<0)
84#define AK4117_CM_PLL (0) /* use RX input as master clock */
85#define AK4117_CM_XTAL (AK4117_CM0) /* use X'tal as master clock */
86#define AK4117_CM_PLL_XTAL (AK4117_CM1) /* use Rx input but X'tal when PLL loses lock */
87#define AK4117_CM_MONITOR (AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for monitoring */
88
89/* AK4117_REG_IO */
90#define AK4117_IPS (1<<7) /* Input Recovery Data Select, 0 = RX0, 1 = RX1 */
91#define AK4117_UOUTE (1<<6) /* U-bit output enable to UOUT, 0 = disable, 1 = enable */
92#define AK4117_CS12 (1<<5) /* channel status select, 0 = channel1, 1 = channel2 */
93#define AK4117_EFH2 (1<<4) /* INT0 pin hold count select */
94#define AK4117_EFH1 (1<<3)
95#define AK4117_EFH_512LRCLK (0)
96#define AK4117_EFH_1024LRCLK (AK4117_EFH1)
97#define AK4117_EFH_2048LRCLK (AK4117_EFH2)
98#define AK4117_EFH_4096LRCLK (AK4117_EFH1|AK4117_EFH2)
99#define AK4117_DIF2 (1<<2) /* audio data format control */
100#define AK4117_DIF1 (1<<1)
101#define AK4117_DIF0 (1<<0)
102#define AK4117_DIF_16R (0) /* STDO: 16-bit, right justified */
103#define AK4117_DIF_18R (AK4117_DIF0) /* STDO: 18-bit, right justified */
104#define AK4117_DIF_20R (AK4117_DIF1) /* STDO: 20-bit, right justified */
105#define AK4117_DIF_24R (AK4117_DIF1|AK4117_DIF0) /* STDO: 24-bit, right justified */
106#define AK4117_DIF_24L (AK4117_DIF2) /* STDO: 24-bit, left justified */
107#define AK4117_DIF_24I2S (AK4117_DIF2|AK4117_DIF0) /* STDO: I2S */
108
109/* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK */
110#define AK4117_MULK (1<<7) /* mask enable for UNLOCK bit */
111#define AK4117_MPAR (1<<6) /* mask enable for PAR bit */
112#define AK4117_MAUTO (1<<5) /* mask enable for AUTO bit */
113#define AK4117_MV (1<<4) /* mask enable for V bit */
114#define AK4117_MAUD (1<<3) /* mask enable for AUDION bit */
115#define AK4117_MSTC (1<<2) /* mask enable for STC bit */
116#define AK4117_MCIT (1<<1) /* mask enable for CINT bit */
117#define AK4117_MQIT (1<<0) /* mask enable for QINT bit */
118
119/* AK4117_REG_RCS0 */
120#define AK4117_UNLCK (1<<7) /* PLL lock status, 0 = lock, 1 = unlock */
121#define AK4117_PAR (1<<6) /* parity error or biphase error status, 0 = no error, 1 = error */
122#define AK4117_AUTO (1<<5) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
123#define AK4117_V (1<<4) /* Validity bit, 0 = valid, 1 = invalid */
124#define AK4117_AUDION (1<<3) /* audio bit output, 0 = audio, 1 = non-audio */
125#define AK4117_STC (1<<2) /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
126#define AK4117_CINT (1<<1) /* channel status buffer interrupt, 0 = no change, 1 = change */
127#define AK4117_QINT (1<<0) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
128
129/* AK4117_REG_RCS1 */
130#define AK4117_DTSCD (1<<6) /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
131#define AK4117_NPCM (1<<5) /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
132#define AK4117_PEM (1<<4) /* Pre-emphasis detect, 0 = OFF, 1 = ON */
133#define AK4117_FS3 (1<<3) /* sampling frequency detection */
134#define AK4117_FS2 (1<<2)
135#define AK4117_FS1 (1<<1)
136#define AK4117_FS0 (1<<0)
137#define AK4117_FS_44100HZ (0)
138#define AK4117_FS_48000HZ (AK4117_FS1)
139#define AK4117_FS_32000HZ (AK4117_FS1|AK4117_FS0)
140#define AK4117_FS_88200HZ (AK4117_FS3)
141#define AK4117_FS_96000HZ (AK4117_FS3|AK4117_FS1)
142#define AK4117_FS_176400HZ (AK4117_FS3|AK4117_FS2)
143#define AK4117_FS_192000HZ (AK4117_FS3|AK4117_FS2|AK4117_FS1)
144
145/* AK4117_REG_RCS2 */
146#define AK4117_CCRC (1<<1) /* CRC for channel status, 0 = no error, 1 = error */
147#define AK4117_QCRC (1<<0) /* CRC for Q-subcode, 0 = no error, 1 = error */
148
149/* flags for snd_ak4117_check_rate_and_errors() */
150#define AK4117_CHECK_NO_STAT (1<<0) /* no statistics */
151#define AK4117_CHECK_NO_RATE (1<<1) /* no rate check */
152
153#define AK4117_CONTROLS 13
154
155typedef void (ak4117_write_t)(void *private_data, unsigned char addr, unsigned char data);
156typedef unsigned char (ak4117_read_t)(void *private_data, unsigned char addr);
157
158typedef struct ak4117 ak4117_t;
159
160struct ak4117 {
161 snd_card_t * card;
162 ak4117_write_t * write;
163 ak4117_read_t * read;
164 void * private_data;
165 unsigned int init: 1;
166 spinlock_t lock;
167 unsigned char regmap[5];
168 snd_kcontrol_t *kctls[AK4117_CONTROLS];
169 snd_pcm_substream_t *substream;
170 unsigned long parity_errors;
171 unsigned long v_bit_errors;
172 unsigned long qcrc_errors;
173 unsigned long ccrc_errors;
174 unsigned char rcs0;
175 unsigned char rcs1;
176 unsigned char rcs2;
177 struct timer_list timer; /* statistic timer */
178 void *change_callback_private;
179 void (*change_callback)(ak4117_t *ak4117, unsigned char c0, unsigned char c1);
180};
181
182int snd_ak4117_create(snd_card_t *card, ak4117_read_t *read, ak4117_write_t *write,
183 unsigned char pgm[5], void *private_data, ak4117_t **r_ak4117);
184void snd_ak4117_reg_write(ak4117_t *ak4117, unsigned char reg, unsigned char mask, unsigned char val);
185void snd_ak4117_reinit(ak4117_t *ak4117);
186int snd_ak4117_build(ak4117_t *ak4117, snd_pcm_substream_t *capture_substream);
187int snd_ak4117_external_rate(ak4117_t *ak4117);
188int snd_ak4117_check_rate_and_errors(ak4117_t *ak4117, unsigned int flags);
189
190#endif /* __SOUND_AK4117_H */
191
diff --git a/include/sound/ak4531_codec.h b/include/sound/ak4531_codec.h
new file mode 100644
index 000000000000..8b18992376d5
--- /dev/null
+++ b/include/sound/ak4531_codec.h
@@ -0,0 +1,80 @@
1#ifndef __SOUND_AK4531_CODEC_H
2#define __SOUND_AK4531_CODEC_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Universal interface for Audio Codec '97
7 *
8 * For more details look to AC '97 component specification revision 2.1
9 * by Intel Corporation (http://developer.intel.com).
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28#include "info.h"
29#include "control.h"
30
31/*
32 * ASAHI KASEI - AK4531 codec
33 * - not really AC'97 codec, but it uses very similar interface as AC'97
34 */
35
36/*
37 * AK4531 codec registers
38 */
39
40#define AK4531_LMASTER 0x00 /* master volume left */
41#define AK4531_RMASTER 0x01 /* master volume right */
42#define AK4531_LVOICE 0x02 /* channel volume left */
43#define AK4531_RVOICE 0x03 /* channel volume right */
44#define AK4531_LFM 0x04 /* FM volume left */
45#define AK4531_RFM 0x05 /* FM volume right */
46#define AK4531_LCD 0x06 /* CD volume left */
47#define AK4531_RCD 0x07 /* CD volume right */
48#define AK4531_LLINE 0x08 /* LINE volume left */
49#define AK4531_RLINE 0x09 /* LINE volume right */
50#define AK4531_LAUXA 0x0a /* AUXA volume left */
51#define AK4531_RAUXA 0x0b /* AUXA volume right */
52#define AK4531_MONO1 0x0c /* MONO1 volume left */
53#define AK4531_MONO2 0x0d /* MONO1 volume right */
54#define AK4531_MIC 0x0e /* MIC volume */
55#define AK4531_MONO_OUT 0x0f /* Mono-out volume */
56#define AK4531_OUT_SW1 0x10 /* Output mixer switch 1 */
57#define AK4531_OUT_SW2 0x11 /* Output mixer switch 2 */
58#define AK4531_LIN_SW1 0x12 /* Input left mixer switch 1 */
59#define AK4531_RIN_SW1 0x13 /* Input right mixer switch 1 */
60#define AK4531_LIN_SW2 0x14 /* Input left mixer switch 2 */
61#define AK4531_RIN_SW2 0x15 /* Input right mixer switch 2 */
62#define AK4531_RESET 0x16 /* Reset & power down */
63#define AK4531_CLOCK 0x17 /* Clock select */
64#define AK4531_AD_IN 0x18 /* AD input select */
65#define AK4531_MIC_GAIN 0x19 /* MIC amplified gain */
66
67typedef struct _snd_ak4531 ak4531_t;
68
69struct _snd_ak4531 {
70 void (*write) (ak4531_t *ak4531, unsigned short reg, unsigned short val);
71 void *private_data;
72 void (*private_free) (ak4531_t *ak4531);
73 /* --- */
74 unsigned char regs[0x20];
75 struct semaphore reg_mutex;
76};
77
78int snd_ak4531_mixer(snd_card_t * card, ak4531_t * _ak4531, ak4531_t ** rak4531);
79
80#endif /* __SOUND_AK4531_CODEC_H */
diff --git a/include/sound/ak4xxx-adda.h b/include/sound/ak4xxx-adda.h
new file mode 100644
index 000000000000..e94ac0282318
--- /dev/null
+++ b/include/sound/ak4xxx-adda.h
@@ -0,0 +1,69 @@
1#ifndef __SOUND_AK4XXX_ADDA_H
2#define __SOUND_AK4XXX_ADDA_H
3
4/*
5 * ALSA driver for AK4524 / AK4528 / AK4529 / AK4355 / AK4381
6 * AD and DA converters
7 *
8 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef AK4XXX_MAX_CHIPS
27#define AK4XXX_MAX_CHIPS 4
28#endif
29
30typedef struct snd_akm4xxx akm4xxx_t;
31
32struct snd_ak4xxx_ops {
33 void (*lock)(akm4xxx_t *ak, int chip);
34 void (*unlock)(akm4xxx_t *ak, int chip);
35 void (*write)(akm4xxx_t *ak, int chip, unsigned char reg, unsigned char val);
36 // unsigned char (*read)(akm4xxx_t *ak, int chip, unsigned char reg);
37 void (*set_rate_val)(akm4xxx_t *ak, unsigned int rate);
38};
39
40#define AK4XXX_IMAGE_SIZE (AK4XXX_MAX_CHIPS * 16) /* 64 bytes */
41
42struct snd_akm4xxx {
43 snd_card_t *card;
44 unsigned int num_adcs; /* AK4524 or AK4528 ADCs */
45 unsigned int num_dacs; /* AK4524 or AK4528 DACs */
46 unsigned char images[AK4XXX_IMAGE_SIZE]; /* saved register image */
47 unsigned char ipga_gain[AK4XXX_MAX_CHIPS][2]; /* saved register image for IPGA (AK4528) */
48 unsigned long private_value[AK4XXX_MAX_CHIPS]; /* helper for driver */
49 void *private_data[AK4XXX_MAX_CHIPS]; /* helper for driver */
50 /* template should fill the following fields */
51 unsigned int idx_offset; /* control index offset */
52 enum {
53 SND_AK4524, SND_AK4528, SND_AK4529,
54 SND_AK4355, SND_AK4358, SND_AK4381
55 } type;
56 struct snd_ak4xxx_ops ops;
57};
58
59void snd_akm4xxx_write(akm4xxx_t *ak, int chip, unsigned char reg, unsigned char val);
60void snd_akm4xxx_reset(akm4xxx_t *ak, int state);
61void snd_akm4xxx_init(akm4xxx_t *ak);
62int snd_akm4xxx_build_controls(akm4xxx_t *ak);
63
64#define snd_akm4xxx_get(ak,chip,reg) (ak)->images[(chip) * 16 + (reg)]
65#define snd_akm4xxx_set(ak,chip,reg,val) ((ak)->images[(chip) * 16 + (reg)] = (val))
66#define snd_akm4xxx_get_ipga(ak,chip,reg) (ak)->ipga_gain[chip][(reg)-4]
67#define snd_akm4xxx_set_ipga(ak,chip,reg,val) ((ak)->ipga_gain[chip][(reg)-4] = (val))
68
69#endif /* __SOUND_AK4XXX_ADDA_H */
diff --git a/include/sound/asequencer.h b/include/sound/asequencer.h
new file mode 100644
index 000000000000..728efd504262
--- /dev/null
+++ b/include/sound/asequencer.h
@@ -0,0 +1,908 @@
1/*
2 * Main header file for the ALSA sequencer
3 * Copyright (c) 1998-1999 by Frank van de Pol <fvdpol@coil.demon.nl>
4 * (c) 1998-1999 by Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22#ifndef __SOUND_ASEQUENCER_H
23#define __SOUND_ASEQUENCER_H
24
25#ifndef __KERNEL__
26#include <linux/ioctl.h>
27#endif
28
29#include <sound/asound.h>
30
31/** version of the sequencer */
32#define SNDRV_SEQ_VERSION SNDRV_PROTOCOL_VERSION (1, 0, 1)
33
34/**
35 * definition of sequencer event types
36 */
37
38/** system messages
39 * event data type = #sndrv_seq_result_t
40 */
41#define SNDRV_SEQ_EVENT_SYSTEM 0
42#define SNDRV_SEQ_EVENT_RESULT 1
43
44/** note messages (channel specific)
45 * event data type = #sndrv_seq_ev_note
46 */
47#define SNDRV_SEQ_EVENT_NOTE 5
48#define SNDRV_SEQ_EVENT_NOTEON 6
49#define SNDRV_SEQ_EVENT_NOTEOFF 7
50#define SNDRV_SEQ_EVENT_KEYPRESS 8
51
52/** control messages (channel specific)
53 * event data type = #sndrv_seq_ev_ctrl
54 */
55#define SNDRV_SEQ_EVENT_CONTROLLER 10
56#define SNDRV_SEQ_EVENT_PGMCHANGE 11
57#define SNDRV_SEQ_EVENT_CHANPRESS 12
58#define SNDRV_SEQ_EVENT_PITCHBEND 13 /**< from -8192 to 8191 */
59#define SNDRV_SEQ_EVENT_CONTROL14 14 /**< 14 bit controller value */
60#define SNDRV_SEQ_EVENT_NONREGPARAM 15 /**< 14 bit NRPN address + 14 bit unsigned value */
61#define SNDRV_SEQ_EVENT_REGPARAM 16 /**< 14 bit RPN address + 14 bit unsigned value */
62
63/** synchronisation messages
64 * event data type = #sndrv_seq_ev_ctrl
65 */
66#define SNDRV_SEQ_EVENT_SONGPOS 20 /* Song Position Pointer with LSB and MSB values */
67#define SNDRV_SEQ_EVENT_SONGSEL 21 /* Song Select with song ID number */
68#define SNDRV_SEQ_EVENT_QFRAME 22 /* midi time code quarter frame */
69#define SNDRV_SEQ_EVENT_TIMESIGN 23 /* SMF Time Signature event */
70#define SNDRV_SEQ_EVENT_KEYSIGN 24 /* SMF Key Signature event */
71
72/** timer messages
73 * event data type = sndrv_seq_ev_queue_control_t
74 */
75#define SNDRV_SEQ_EVENT_START 30 /* midi Real Time Start message */
76#define SNDRV_SEQ_EVENT_CONTINUE 31 /* midi Real Time Continue message */
77#define SNDRV_SEQ_EVENT_STOP 32 /* midi Real Time Stop message */
78#define SNDRV_SEQ_EVENT_SETPOS_TICK 33 /* set tick queue position */
79#define SNDRV_SEQ_EVENT_SETPOS_TIME 34 /* set realtime queue position */
80#define SNDRV_SEQ_EVENT_TEMPO 35 /* (SMF) Tempo event */
81#define SNDRV_SEQ_EVENT_CLOCK 36 /* midi Real Time Clock message */
82#define SNDRV_SEQ_EVENT_TICK 37 /* midi Real Time Tick message */
83#define SNDRV_SEQ_EVENT_QUEUE_SKEW 38 /* skew queue tempo */
84
85/** others
86 * event data type = none
87 */
88#define SNDRV_SEQ_EVENT_TUNE_REQUEST 40 /* tune request */
89#define SNDRV_SEQ_EVENT_RESET 41 /* reset to power-on state */
90#define SNDRV_SEQ_EVENT_SENSING 42 /* "active sensing" event */
91
92/** echo back, kernel private messages
93 * event data type = any type
94 */
95#define SNDRV_SEQ_EVENT_ECHO 50 /* echo event */
96#define SNDRV_SEQ_EVENT_OSS 51 /* OSS raw event */
97
98/** system status messages (broadcast for subscribers)
99 * event data type = sndrv_seq_addr_t
100 */
101#define SNDRV_SEQ_EVENT_CLIENT_START 60 /* new client has connected */
102#define SNDRV_SEQ_EVENT_CLIENT_EXIT 61 /* client has left the system */
103#define SNDRV_SEQ_EVENT_CLIENT_CHANGE 62 /* client status/info has changed */
104#define SNDRV_SEQ_EVENT_PORT_START 63 /* new port was created */
105#define SNDRV_SEQ_EVENT_PORT_EXIT 64 /* port was deleted from system */
106#define SNDRV_SEQ_EVENT_PORT_CHANGE 65 /* port status/info has changed */
107
108/** port connection changes
109 * event data type = sndrv_seq_connect_t
110 */
111#define SNDRV_SEQ_EVENT_PORT_SUBSCRIBED 66 /* ports connected */
112#define SNDRV_SEQ_EVENT_PORT_UNSUBSCRIBED 67 /* ports disconnected */
113
114/** synthesizer events
115 * event data type = sndrv_seq_eve_sample_control_t
116 */
117#define SNDRV_SEQ_EVENT_SAMPLE 70 /* sample select */
118#define SNDRV_SEQ_EVENT_SAMPLE_CLUSTER 71 /* sample cluster select */
119#define SNDRV_SEQ_EVENT_SAMPLE_START 72 /* voice start */
120#define SNDRV_SEQ_EVENT_SAMPLE_STOP 73 /* voice stop */
121#define SNDRV_SEQ_EVENT_SAMPLE_FREQ 74 /* playback frequency */
122#define SNDRV_SEQ_EVENT_SAMPLE_VOLUME 75 /* volume and balance */
123#define SNDRV_SEQ_EVENT_SAMPLE_LOOP 76 /* sample loop */
124#define SNDRV_SEQ_EVENT_SAMPLE_POSITION 77 /* sample position */
125#define SNDRV_SEQ_EVENT_SAMPLE_PRIVATE1 78 /* private (hardware dependent) event */
126
127/** user-defined events with fixed length
128 * event data type = any
129 */
130#define SNDRV_SEQ_EVENT_USR0 90
131#define SNDRV_SEQ_EVENT_USR1 91
132#define SNDRV_SEQ_EVENT_USR2 92
133#define SNDRV_SEQ_EVENT_USR3 93
134#define SNDRV_SEQ_EVENT_USR4 94
135#define SNDRV_SEQ_EVENT_USR5 95
136#define SNDRV_SEQ_EVENT_USR6 96
137#define SNDRV_SEQ_EVENT_USR7 97
138#define SNDRV_SEQ_EVENT_USR8 98
139#define SNDRV_SEQ_EVENT_USR9 99
140
141/** instrument layer
142 * variable length data can be passed directly to the driver
143 */
144#define SNDRV_SEQ_EVENT_INSTR_BEGIN 100 /* begin of instrument management */
145#define SNDRV_SEQ_EVENT_INSTR_END 101 /* end of instrument management */
146#define SNDRV_SEQ_EVENT_INSTR_INFO 102 /* instrument interface info */
147#define SNDRV_SEQ_EVENT_INSTR_INFO_RESULT 103 /* result */
148#define SNDRV_SEQ_EVENT_INSTR_FINFO 104 /* get format info */
149#define SNDRV_SEQ_EVENT_INSTR_FINFO_RESULT 105 /* get format info */
150#define SNDRV_SEQ_EVENT_INSTR_RESET 106 /* reset instrument memory */
151#define SNDRV_SEQ_EVENT_INSTR_STATUS 107 /* instrument interface status */
152#define SNDRV_SEQ_EVENT_INSTR_STATUS_RESULT 108 /* result */
153#define SNDRV_SEQ_EVENT_INSTR_PUT 109 /* put instrument to port */
154#define SNDRV_SEQ_EVENT_INSTR_GET 110 /* get instrument from port */
155#define SNDRV_SEQ_EVENT_INSTR_GET_RESULT 111 /* result */
156#define SNDRV_SEQ_EVENT_INSTR_FREE 112 /* free instrument(s) */
157#define SNDRV_SEQ_EVENT_INSTR_LIST 113 /* instrument list */
158#define SNDRV_SEQ_EVENT_INSTR_LIST_RESULT 114 /* result */
159#define SNDRV_SEQ_EVENT_INSTR_CLUSTER 115 /* cluster parameters */
160#define SNDRV_SEQ_EVENT_INSTR_CLUSTER_GET 116 /* get cluster parameters */
161#define SNDRV_SEQ_EVENT_INSTR_CLUSTER_RESULT 117 /* result */
162#define SNDRV_SEQ_EVENT_INSTR_CHANGE 118 /* instrument change */
163/* 119-129: reserved */
164
165/* 130-139: variable length events
166 * event data type = sndrv_seq_ev_ext
167 * (SNDRV_SEQ_EVENT_LENGTH_VARIABLE must be set)
168 */
169#define SNDRV_SEQ_EVENT_SYSEX 130 /* system exclusive data (variable length) */
170#define SNDRV_SEQ_EVENT_BOUNCE 131 /* error event */
171/* 132-134: reserved */
172#define SNDRV_SEQ_EVENT_USR_VAR0 135
173#define SNDRV_SEQ_EVENT_USR_VAR1 136
174#define SNDRV_SEQ_EVENT_USR_VAR2 137
175#define SNDRV_SEQ_EVENT_USR_VAR3 138
176#define SNDRV_SEQ_EVENT_USR_VAR4 139
177
178/* 150-151: kernel events with quote - DO NOT use in user clients */
179#define SNDRV_SEQ_EVENT_KERNEL_ERROR 150
180#define SNDRV_SEQ_EVENT_KERNEL_QUOTE 151 /* obsolete */
181
182/* 152-191: reserved */
183
184/* 192-254: hardware specific events */
185
186/* 255: special event */
187#define SNDRV_SEQ_EVENT_NONE 255
188
189
190typedef unsigned char sndrv_seq_event_type_t;
191
192/** event address */
193struct sndrv_seq_addr {
194 unsigned char client; /**< Client number: 0..255, 255 = broadcast to all clients */
195 unsigned char port; /**< Port within client: 0..255, 255 = broadcast to all ports */
196};
197
198/** port connection */
199struct sndrv_seq_connect {
200 struct sndrv_seq_addr sender;
201 struct sndrv_seq_addr dest;
202};
203
204
205#define SNDRV_SEQ_ADDRESS_UNKNOWN 253 /* unknown source */
206#define SNDRV_SEQ_ADDRESS_SUBSCRIBERS 254 /* send event to all subscribed ports */
207#define SNDRV_SEQ_ADDRESS_BROADCAST 255 /* send event to all queues/clients/ports/channels */
208#define SNDRV_SEQ_QUEUE_DIRECT 253 /* direct dispatch */
209
210 /* event mode flag - NOTE: only 8 bits available! */
211#define SNDRV_SEQ_TIME_STAMP_TICK (0<<0) /* timestamp in clock ticks */
212#define SNDRV_SEQ_TIME_STAMP_REAL (1<<0) /* timestamp in real time */
213#define SNDRV_SEQ_TIME_STAMP_MASK (1<<0)
214
215#define SNDRV_SEQ_TIME_MODE_ABS (0<<1) /* absolute timestamp */
216#define SNDRV_SEQ_TIME_MODE_REL (1<<1) /* relative to current time */
217#define SNDRV_SEQ_TIME_MODE_MASK (1<<1)
218
219#define SNDRV_SEQ_EVENT_LENGTH_FIXED (0<<2) /* fixed event size */
220#define SNDRV_SEQ_EVENT_LENGTH_VARIABLE (1<<2) /* variable event size */
221#define SNDRV_SEQ_EVENT_LENGTH_VARUSR (2<<2) /* variable event size - user memory space */
222#define SNDRV_SEQ_EVENT_LENGTH_MASK (3<<2)
223
224#define SNDRV_SEQ_PRIORITY_NORMAL (0<<4) /* normal priority */
225#define SNDRV_SEQ_PRIORITY_HIGH (1<<4) /* event should be processed before others */
226#define SNDRV_SEQ_PRIORITY_MASK (1<<4)
227
228
229 /* note event */
230struct sndrv_seq_ev_note {
231 unsigned char channel;
232 unsigned char note;
233 unsigned char velocity;
234 unsigned char off_velocity; /* only for SNDRV_SEQ_EVENT_NOTE */
235 unsigned int duration; /* only for SNDRV_SEQ_EVENT_NOTE */
236};
237
238 /* controller event */
239struct sndrv_seq_ev_ctrl {
240 unsigned char channel;
241 unsigned char unused1, unused2, unused3; /* pad */
242 unsigned int param;
243 signed int value;
244};
245
246 /* generic set of bytes (12x8 bit) */
247struct sndrv_seq_ev_raw8 {
248 unsigned char d[12]; /* 8 bit value */
249};
250
251 /* generic set of integers (3x32 bit) */
252struct sndrv_seq_ev_raw32 {
253 unsigned int d[3]; /* 32 bit value */
254};
255
256 /* external stored data */
257struct sndrv_seq_ev_ext {
258 unsigned int len; /* length of data */
259 void *ptr; /* pointer to data (note: maybe 64-bit) */
260} __attribute__((packed));
261
262/* Instrument cluster type */
263typedef unsigned int sndrv_seq_instr_cluster_t;
264
265/* Instrument type */
266struct sndrv_seq_instr {
267 sndrv_seq_instr_cluster_t cluster;
268 unsigned int std; /* the upper byte means a private instrument (owner - client #) */
269 unsigned short bank;
270 unsigned short prg;
271};
272
273 /* sample number */
274struct sndrv_seq_ev_sample {
275 unsigned int std;
276 unsigned short bank;
277 unsigned short prg;
278};
279
280 /* sample cluster */
281struct sndrv_seq_ev_cluster {
282 sndrv_seq_instr_cluster_t cluster;
283};
284
285 /* sample position */
286typedef unsigned int sndrv_seq_position_t; /* playback position (in samples) * 16 */
287
288 /* sample stop mode */
289enum sndrv_seq_stop_mode {
290 SAMPLE_STOP_IMMEDIATELY = 0, /* terminate playing immediately */
291 SAMPLE_STOP_VENVELOPE = 1, /* finish volume envelope */
292 SAMPLE_STOP_LOOP = 2 /* terminate loop and finish wave */
293};
294
295 /* sample frequency */
296typedef int sndrv_seq_frequency_t; /* playback frequency in HZ * 16 */
297
298 /* sample volume control; if any value is set to -1 == do not change */
299struct sndrv_seq_ev_volume {
300 signed short volume; /* range: 0-16383 */
301 signed short lr; /* left-right balance; range: 0-16383 */
302 signed short fr; /* front-rear balance; range: 0-16383 */
303 signed short du; /* down-up balance; range: 0-16383 */
304};
305
306 /* simple loop redefinition */
307struct sndrv_seq_ev_loop {
308 unsigned int start; /* loop start (in samples) * 16 */
309 unsigned int end; /* loop end (in samples) * 16 */
310};
311
312struct sndrv_seq_ev_sample_control {
313 unsigned char channel;
314 unsigned char unused1, unused2, unused3; /* pad */
315 union {
316 struct sndrv_seq_ev_sample sample;
317 struct sndrv_seq_ev_cluster cluster;
318 sndrv_seq_position_t position;
319 enum sndrv_seq_stop_mode stop_mode;
320 sndrv_seq_frequency_t frequency;
321 struct sndrv_seq_ev_volume volume;
322 struct sndrv_seq_ev_loop loop;
323 unsigned char raw8[8];
324 } param;
325};
326
327
328
329/* INSTR_BEGIN event */
330struct sndrv_seq_ev_instr_begin {
331 int timeout; /* zero = forever, otherwise timeout in ms */
332};
333
334struct sndrv_seq_result {
335 int event; /* processed event type */
336 int result;
337};
338
339
340struct sndrv_seq_real_time {
341 unsigned int tv_sec; /* seconds */
342 unsigned int tv_nsec; /* nanoseconds */
343};
344
345typedef unsigned int sndrv_seq_tick_time_t; /* midi ticks */
346
347union sndrv_seq_timestamp {
348 sndrv_seq_tick_time_t tick;
349 struct sndrv_seq_real_time time;
350};
351
352struct sndrv_seq_queue_skew {
353 unsigned int value;
354 unsigned int base;
355};
356
357 /* queue timer control */
358struct sndrv_seq_ev_queue_control {
359 unsigned char queue; /* affected queue */
360 unsigned char pad[3]; /* reserved */
361 union {
362 signed int value; /* affected value (e.g. tempo) */
363 union sndrv_seq_timestamp time; /* time */
364 unsigned int position; /* sync position */
365 struct sndrv_seq_queue_skew skew;
366 unsigned int d32[2];
367 unsigned char d8[8];
368 } param;
369};
370
371 /* quoted event - inside the kernel only */
372struct sndrv_seq_ev_quote {
373 struct sndrv_seq_addr origin; /* original sender */
374 unsigned short value; /* optional data */
375 struct sndrv_seq_event *event; /* quoted event */
376} __attribute__((packed));
377
378
379 /* sequencer event */
380struct sndrv_seq_event {
381 sndrv_seq_event_type_t type; /* event type */
382 unsigned char flags; /* event flags */
383 char tag;
384
385 unsigned char queue; /* schedule queue */
386 union sndrv_seq_timestamp time; /* schedule time */
387
388
389 struct sndrv_seq_addr source; /* source address */
390 struct sndrv_seq_addr dest; /* destination address */
391
392 union { /* event data... */
393 struct sndrv_seq_ev_note note;
394 struct sndrv_seq_ev_ctrl control;
395 struct sndrv_seq_ev_raw8 raw8;
396 struct sndrv_seq_ev_raw32 raw32;
397 struct sndrv_seq_ev_ext ext;
398 struct sndrv_seq_ev_queue_control queue;
399 union sndrv_seq_timestamp time;
400 struct sndrv_seq_addr addr;
401 struct sndrv_seq_connect connect;
402 struct sndrv_seq_result result;
403 struct sndrv_seq_ev_instr_begin instr_begin;
404 struct sndrv_seq_ev_sample_control sample;
405 struct sndrv_seq_ev_quote quote;
406 } data;
407};
408
409
410/*
411 * bounce event - stored as variable size data
412 */
413struct sndrv_seq_event_bounce {
414 int err;
415 struct sndrv_seq_event event;
416 /* external data follows here. */
417};
418
419#define sndrv_seq_event_bounce_ext_data(ev) ((void*)((char *)(ev)->data.ext.ptr + sizeof(sndrv_seq_event_bounce_t)))
420
421/*
422 * type check macros
423 */
424/* result events: 0-4 */
425#define sndrv_seq_ev_is_result_type(ev) ((ev)->type < 5)
426/* channel specific events: 5-19 */
427#define sndrv_seq_ev_is_channel_type(ev) ((ev)->type >= 5 && (ev)->type < 20)
428/* note events: 5-9 */
429#define sndrv_seq_ev_is_note_type(ev) ((ev)->type >= 5 && (ev)->type < 10)
430/* control events: 10-19 */
431#define sndrv_seq_ev_is_control_type(ev) ((ev)->type >= 10 && (ev)->type < 20)
432/* queue control events: 30-39 */
433#define sndrv_seq_ev_is_queue_type(ev) ((ev)->type >= 30 && (ev)->type < 40)
434/* system status messages */
435#define sndrv_seq_ev_is_message_type(ev) ((ev)->type >= 60 && (ev)->type < 69)
436/* sample messages */
437#define sndrv_seq_ev_is_sample_type(ev) ((ev)->type >= 70 && (ev)->type < 79)
438/* user-defined messages */
439#define sndrv_seq_ev_is_user_type(ev) ((ev)->type >= 90 && (ev)->type < 99)
440/* fixed length events: 0-99 */
441#define sndrv_seq_ev_is_fixed_type(ev) ((ev)->type < 100)
442/* instrument layer events: 100-129 */
443#define sndrv_seq_ev_is_instr_type(ev) ((ev)->type >= 100 && (ev)->type < 130)
444/* variable length events: 130-139 */
445#define sndrv_seq_ev_is_variable_type(ev) ((ev)->type >= 130 && (ev)->type < 140)
446/* reserved for kernel */
447#define sndrv_seq_ev_is_reserved(ev) ((ev)->type >= 150)
448
449/* direct dispatched events */
450#define sndrv_seq_ev_is_direct(ev) ((ev)->queue == SNDRV_SEQ_QUEUE_DIRECT)
451
452/*
453 * macros to check event flags
454 */
455/* prior events */
456#define sndrv_seq_ev_is_prior(ev) (((ev)->flags & SNDRV_SEQ_PRIORITY_MASK) == SNDRV_SEQ_PRIORITY_HIGH)
457
458/* event length type */
459#define sndrv_seq_ev_length_type(ev) ((ev)->flags & SNDRV_SEQ_EVENT_LENGTH_MASK)
460#define sndrv_seq_ev_is_fixed(ev) (sndrv_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_FIXED)
461#define sndrv_seq_ev_is_variable(ev) (sndrv_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_VARIABLE)
462#define sndrv_seq_ev_is_varusr(ev) (sndrv_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_VARUSR)
463
464/* time-stamp type */
465#define sndrv_seq_ev_timestamp_type(ev) ((ev)->flags & SNDRV_SEQ_TIME_STAMP_MASK)
466#define sndrv_seq_ev_is_tick(ev) (sndrv_seq_ev_timestamp_type(ev) == SNDRV_SEQ_TIME_STAMP_TICK)
467#define sndrv_seq_ev_is_real(ev) (sndrv_seq_ev_timestamp_type(ev) == SNDRV_SEQ_TIME_STAMP_REAL)
468
469/* time-mode type */
470#define sndrv_seq_ev_timemode_type(ev) ((ev)->flags & SNDRV_SEQ_TIME_MODE_MASK)
471#define sndrv_seq_ev_is_abstime(ev) (sndrv_seq_ev_timemode_type(ev) == SNDRV_SEQ_TIME_MODE_ABS)
472#define sndrv_seq_ev_is_reltime(ev) (sndrv_seq_ev_timemode_type(ev) == SNDRV_SEQ_TIME_MODE_REL)
473
474/* queue sync port */
475#define sndrv_seq_queue_sync_port(q) ((q) + 16)
476
477 /* system information */
478struct sndrv_seq_system_info {
479 int queues; /* maximum queues count */
480 int clients; /* maximum clients count */
481 int ports; /* maximum ports per client */
482 int channels; /* maximum channels per port */
483 int cur_clients; /* current clients */
484 int cur_queues; /* current queues */
485 char reserved[24];
486};
487
488
489 /* system running information */
490struct sndrv_seq_running_info {
491 unsigned char client; /* client id */
492 unsigned char big_endian; /* 1 = big-endian */
493 unsigned char cpu_mode; /* 4 = 32bit, 8 = 64bit */
494 unsigned char pad; /* reserved */
495 unsigned char reserved[12];
496};
497
498
499 /* known client numbers */
500#define SNDRV_SEQ_CLIENT_SYSTEM 0
501#define SNDRV_SEQ_CLIENT_DUMMY 62 /* dummy ports */
502#define SNDRV_SEQ_CLIENT_OSS 63 /* oss sequencer emulator */
503
504
505 /* client types */
506enum sndrv_seq_client_type {
507 NO_CLIENT = 0,
508 USER_CLIENT = 1,
509 KERNEL_CLIENT = 2
510};
511
512 /* event filter flags */
513#define SNDRV_SEQ_FILTER_BROADCAST (1<<0) /* accept broadcast messages */
514#define SNDRV_SEQ_FILTER_MULTICAST (1<<1) /* accept multicast messages */
515#define SNDRV_SEQ_FILTER_BOUNCE (1<<2) /* accept bounce event in error */
516#define SNDRV_SEQ_FILTER_USE_EVENT (1<<31) /* use event filter */
517
518struct sndrv_seq_client_info {
519 int client; /* client number to inquire */
520 enum sndrv_seq_client_type type; /* client type */
521 char name[64]; /* client name */
522 unsigned int filter; /* filter flags */
523 unsigned char multicast_filter[8]; /* multicast filter bitmap */
524 unsigned char event_filter[32]; /* event filter bitmap */
525 int num_ports; /* RO: number of ports */
526 int event_lost; /* number of lost events */
527 char reserved[64]; /* for future use */
528};
529
530
531/* client pool size */
532struct sndrv_seq_client_pool {
533 int client; /* client number to inquire */
534 int output_pool; /* outgoing (write) pool size */
535 int input_pool; /* incoming (read) pool size */
536 int output_room; /* minimum free pool size for select/blocking mode */
537 int output_free; /* unused size */
538 int input_free; /* unused size */
539 char reserved[64];
540};
541
542
543/* Remove events by specified criteria */
544
545#define SNDRV_SEQ_REMOVE_INPUT (1<<0) /* Flush input queues */
546#define SNDRV_SEQ_REMOVE_OUTPUT (1<<1) /* Flush output queues */
547#define SNDRV_SEQ_REMOVE_DEST (1<<2) /* Restrict by destination q:client:port */
548#define SNDRV_SEQ_REMOVE_DEST_CHANNEL (1<<3) /* Restrict by channel */
549#define SNDRV_SEQ_REMOVE_TIME_BEFORE (1<<4) /* Restrict to before time */
550#define SNDRV_SEQ_REMOVE_TIME_AFTER (1<<5) /* Restrict to time or after */
551#define SNDRV_SEQ_REMOVE_TIME_TICK (1<<6) /* Time is in ticks */
552#define SNDRV_SEQ_REMOVE_EVENT_TYPE (1<<7) /* Restrict to event type */
553#define SNDRV_SEQ_REMOVE_IGNORE_OFF (1<<8) /* Do not flush off events */
554#define SNDRV_SEQ_REMOVE_TAG_MATCH (1<<9) /* Restrict to events with given tag */
555
556struct sndrv_seq_remove_events {
557 unsigned int remove_mode; /* Flags that determine what gets removed */
558
559 union sndrv_seq_timestamp time;
560
561 unsigned char queue; /* Queue for REMOVE_DEST */
562 struct sndrv_seq_addr dest; /* Address for REMOVE_DEST */
563 unsigned char channel; /* Channel for REMOVE_DEST */
564
565 int type; /* For REMOVE_EVENT_TYPE */
566 char tag; /* Tag for REMOVE_TAG */
567
568 int reserved[10]; /* To allow for future binary compatibility */
569
570};
571
572
573 /* known port numbers */
574#define SNDRV_SEQ_PORT_SYSTEM_TIMER 0
575#define SNDRV_SEQ_PORT_SYSTEM_ANNOUNCE 1
576
577 /* port capabilities (32 bits) */
578#define SNDRV_SEQ_PORT_CAP_READ (1<<0) /* readable from this port */
579#define SNDRV_SEQ_PORT_CAP_WRITE (1<<1) /* writable to this port */
580
581#define SNDRV_SEQ_PORT_CAP_SYNC_READ (1<<2)
582#define SNDRV_SEQ_PORT_CAP_SYNC_WRITE (1<<3)
583
584#define SNDRV_SEQ_PORT_CAP_DUPLEX (1<<4)
585
586#define SNDRV_SEQ_PORT_CAP_SUBS_READ (1<<5) /* allow read subscription */
587#define SNDRV_SEQ_PORT_CAP_SUBS_WRITE (1<<6) /* allow write subscription */
588#define SNDRV_SEQ_PORT_CAP_NO_EXPORT (1<<7) /* routing not allowed */
589
590 /* port type */
591#define SNDRV_SEQ_PORT_TYPE_SPECIFIC (1<<0) /* hardware specific */
592#define SNDRV_SEQ_PORT_TYPE_MIDI_GENERIC (1<<1) /* generic MIDI device */
593#define SNDRV_SEQ_PORT_TYPE_MIDI_GM (1<<2) /* General MIDI compatible device */
594#define SNDRV_SEQ_PORT_TYPE_MIDI_GS (1<<3) /* GS compatible device */
595#define SNDRV_SEQ_PORT_TYPE_MIDI_XG (1<<4) /* XG compatible device */
596#define SNDRV_SEQ_PORT_TYPE_MIDI_MT32 (1<<5) /* MT-32 compatible device */
597#define SNDRV_SEQ_PORT_TYPE_MIDI_GM2 (1<<6) /* General MIDI 2 compatible device */
598
599/* other standards...*/
600#define SNDRV_SEQ_PORT_TYPE_SYNTH (1<<10) /* Synth device (no MIDI compatible - direct wavetable) */
601#define SNDRV_SEQ_PORT_TYPE_DIRECT_SAMPLE (1<<11) /* Sampling device (support sample download) */
602#define SNDRV_SEQ_PORT_TYPE_SAMPLE (1<<12) /* Sampling device (sample can be downloaded at any time) */
603/*...*/
604#define SNDRV_SEQ_PORT_TYPE_APPLICATION (1<<20) /* application (sequencer/editor) */
605
606/* misc. conditioning flags */
607#define SNDRV_SEQ_PORT_FLG_GIVEN_PORT (1<<0)
608#define SNDRV_SEQ_PORT_FLG_TIMESTAMP (1<<1)
609#define SNDRV_SEQ_PORT_FLG_TIME_REAL (1<<2)
610
611struct sndrv_seq_port_info {
612 struct sndrv_seq_addr addr; /* client/port numbers */
613 char name[64]; /* port name */
614
615 unsigned int capability; /* port capability bits */
616 unsigned int type; /* port type bits */
617 int midi_channels; /* channels per MIDI port */
618 int midi_voices; /* voices per MIDI port */
619 int synth_voices; /* voices per SYNTH port */
620
621 int read_use; /* R/O: subscribers for output (from this port) */
622 int write_use; /* R/O: subscribers for input (to this port) */
623
624 void *kernel; /* reserved for kernel use (must be NULL) */
625 unsigned int flags; /* misc. conditioning */
626 unsigned char time_queue; /* queue # for timestamping */
627 char reserved[59]; /* for future use */
628};
629
630
631/* queue flags */
632#define SNDRV_SEQ_QUEUE_FLG_SYNC (1<<0) /* sync enabled */
633
634/* queue information */
635struct sndrv_seq_queue_info {
636 int queue; /* queue id */
637
638 /*
639 * security settings, only owner of this queue can start/stop timer
640 * etc. if the queue is locked for other clients
641 */
642 int owner; /* client id for owner of the queue */
643 unsigned locked:1; /* timing queue locked for other queues */
644 char name[64]; /* name of this queue */
645 unsigned int flags; /* flags */
646 char reserved[60]; /* for future use */
647
648};
649
650/* queue info/status */
651struct sndrv_seq_queue_status {
652 int queue; /* queue id */
653 int events; /* read-only - queue size */
654 sndrv_seq_tick_time_t tick; /* current tick */
655 struct sndrv_seq_real_time time; /* current time */
656 int running; /* running state of queue */
657 int flags; /* various flags */
658 char reserved[64]; /* for the future */
659};
660
661
662/* queue tempo */
663struct sndrv_seq_queue_tempo {
664 int queue; /* sequencer queue */
665 unsigned int tempo; /* current tempo, us/tick */
666 int ppq; /* time resolution, ticks/quarter */
667 unsigned int skew_value; /* queue skew */
668 unsigned int skew_base; /* queue skew base */
669 char reserved[24]; /* for the future */
670};
671
672
673/* sequencer timer sources */
674#define SNDRV_SEQ_TIMER_ALSA 0 /* ALSA timer */
675#define SNDRV_SEQ_TIMER_MIDI_CLOCK 1 /* Midi Clock (CLOCK event) */
676#define SNDRV_SEQ_TIMER_MIDI_TICK 2 /* Midi Timer Tick (TICK event) */
677
678/* queue timer info */
679struct sndrv_seq_queue_timer {
680 int queue; /* sequencer queue */
681 int type; /* source timer type */
682 union {
683 struct {
684 struct sndrv_timer_id id; /* ALSA's timer ID */
685 unsigned int resolution; /* resolution in Hz */
686 } alsa;
687 } u;
688 char reserved[64]; /* for the future use */
689};
690
691
692struct sndrv_seq_queue_client {
693 int queue; /* sequencer queue */
694 int client; /* sequencer client */
695 int used; /* queue is used with this client
696 (must be set for accepting events) */
697 /* per client watermarks */
698 char reserved[64]; /* for future use */
699};
700
701
702#define SNDRV_SEQ_PORT_SUBS_EXCLUSIVE (1<<0) /* exclusive connection */
703#define SNDRV_SEQ_PORT_SUBS_TIMESTAMP (1<<1)
704#define SNDRV_SEQ_PORT_SUBS_TIME_REAL (1<<2)
705
706struct sndrv_seq_port_subscribe {
707 struct sndrv_seq_addr sender; /* sender address */
708 struct sndrv_seq_addr dest; /* destination address */
709 unsigned int voices; /* number of voices to be allocated (0 = don't care) */
710 unsigned int flags; /* modes */
711 unsigned char queue; /* input time-stamp queue (optional) */
712 unsigned char pad[3]; /* reserved */
713 char reserved[64];
714};
715
716/* type of query subscription */
717#define SNDRV_SEQ_QUERY_SUBS_READ 0
718#define SNDRV_SEQ_QUERY_SUBS_WRITE 1
719
720struct sndrv_seq_query_subs {
721 struct sndrv_seq_addr root; /* client/port id to be searched */
722 int type; /* READ or WRITE */
723 int index; /* 0..N-1 */
724 int num_subs; /* R/O: number of subscriptions on this port */
725 struct sndrv_seq_addr addr; /* R/O: result */
726 unsigned char queue; /* R/O: result */
727 unsigned int flags; /* R/O: result */
728 char reserved[64]; /* for future use */
729};
730
731
732/*
733 * Instrument abstraction layer
734 * - based on events
735 */
736
737/* instrument types */
738#define SNDRV_SEQ_INSTR_ATYPE_DATA 0 /* instrument data */
739#define SNDRV_SEQ_INSTR_ATYPE_ALIAS 1 /* instrument alias */
740
741/* instrument ASCII identifiers */
742#define SNDRV_SEQ_INSTR_ID_DLS1 "DLS1"
743#define SNDRV_SEQ_INSTR_ID_DLS2 "DLS2"
744#define SNDRV_SEQ_INSTR_ID_SIMPLE "Simple Wave"
745#define SNDRV_SEQ_INSTR_ID_SOUNDFONT "SoundFont"
746#define SNDRV_SEQ_INSTR_ID_GUS_PATCH "GUS Patch"
747#define SNDRV_SEQ_INSTR_ID_INTERWAVE "InterWave FFFF"
748#define SNDRV_SEQ_INSTR_ID_OPL2_3 "OPL2/3 FM"
749#define SNDRV_SEQ_INSTR_ID_OPL4 "OPL4"
750
751/* instrument types */
752#define SNDRV_SEQ_INSTR_TYPE0_DLS1 (1<<0) /* MIDI DLS v1 */
753#define SNDRV_SEQ_INSTR_TYPE0_DLS2 (1<<1) /* MIDI DLS v2 */
754#define SNDRV_SEQ_INSTR_TYPE1_SIMPLE (1<<0) /* Simple Wave */
755#define SNDRV_SEQ_INSTR_TYPE1_SOUNDFONT (1<<1) /* EMU SoundFont */
756#define SNDRV_SEQ_INSTR_TYPE1_GUS_PATCH (1<<2) /* Gravis UltraSound Patch */
757#define SNDRV_SEQ_INSTR_TYPE1_INTERWAVE (1<<3) /* InterWave FFFF */
758#define SNDRV_SEQ_INSTR_TYPE2_OPL2_3 (1<<0) /* Yamaha OPL2/3 FM */
759#define SNDRV_SEQ_INSTR_TYPE2_OPL4 (1<<1) /* Yamaha OPL4 */
760
761/* put commands */
762#define SNDRV_SEQ_INSTR_PUT_CMD_CREATE 0
763#define SNDRV_SEQ_INSTR_PUT_CMD_REPLACE 1
764#define SNDRV_SEQ_INSTR_PUT_CMD_MODIFY 2
765#define SNDRV_SEQ_INSTR_PUT_CMD_ADD 3
766#define SNDRV_SEQ_INSTR_PUT_CMD_REMOVE 4
767
768/* get commands */
769#define SNDRV_SEQ_INSTR_GET_CMD_FULL 0
770#define SNDRV_SEQ_INSTR_GET_CMD_PARTIAL 1
771
772/* query flags */
773#define SNDRV_SEQ_INSTR_QUERY_FOLLOW_ALIAS (1<<0)
774
775/* free commands */
776#define SNDRV_SEQ_INSTR_FREE_CMD_ALL 0
777#define SNDRV_SEQ_INSTR_FREE_CMD_PRIVATE 1
778#define SNDRV_SEQ_INSTR_FREE_CMD_CLUSTER 2
779#define SNDRV_SEQ_INSTR_FREE_CMD_SINGLE 3
780
781/* size of ROM/RAM */
782typedef unsigned int sndrv_seq_instr_size_t;
783
784/* INSTR_INFO */
785
786struct sndrv_seq_instr_info {
787 int result; /* operation result */
788 unsigned int formats[8]; /* bitmap of supported formats */
789 int ram_count; /* count of RAM banks */
790 sndrv_seq_instr_size_t ram_sizes[16]; /* size of RAM banks */
791 int rom_count; /* count of ROM banks */
792 sndrv_seq_instr_size_t rom_sizes[8]; /* size of ROM banks */
793 char reserved[128];
794};
795
796/* INSTR_STATUS */
797
798struct sndrv_seq_instr_status {
799 int result; /* operation result */
800 sndrv_seq_instr_size_t free_ram[16]; /* free RAM in banks */
801 int instrument_count; /* count of downloaded instruments */
802 char reserved[128];
803};
804
805/* INSTR_FORMAT_INFO */
806
807struct sndrv_seq_instr_format_info {
808 char format[16]; /* format identifier - SNDRV_SEQ_INSTR_ID_* */
809 unsigned int len; /* max data length (without this structure) */
810};
811
812struct sndrv_seq_instr_format_info_result {
813 int result; /* operation result */
814 char format[16]; /* format identifier */
815 unsigned int len; /* filled data length (without this structure) */
816};
817
818/* instrument data */
819struct sndrv_seq_instr_data {
820 char name[32]; /* instrument name */
821 char reserved[16]; /* for the future use */
822 int type; /* instrument type */
823 union {
824 char format[16]; /* format identifier */
825 struct sndrv_seq_instr alias;
826 } data;
827};
828
829/* INSTR_PUT/GET, data are stored in one block (extended), header + data */
830
831struct sndrv_seq_instr_header {
832 union {
833 struct sndrv_seq_instr instr;
834 sndrv_seq_instr_cluster_t cluster;
835 } id; /* instrument identifier */
836 unsigned int cmd; /* get/put/free command */
837 unsigned int flags; /* query flags (only for get) */
838 unsigned int len; /* real instrument data length (without header) */
839 int result; /* operation result */
840 char reserved[16]; /* for the future */
841 struct sndrv_seq_instr_data data; /* instrument data (for put/get result) */
842};
843
844/* INSTR_CLUSTER_SET */
845
846struct sndrv_seq_instr_cluster_set {
847 sndrv_seq_instr_cluster_t cluster; /* cluster identifier */
848 char name[32]; /* cluster name */
849 int priority; /* cluster priority */
850 char reserved[64]; /* for the future use */
851};
852
853/* INSTR_CLUSTER_GET */
854
855struct sndrv_seq_instr_cluster_get {
856 sndrv_seq_instr_cluster_t cluster; /* cluster identifier */
857 char name[32]; /* cluster name */
858 int priority; /* cluster priority */
859 char reserved[64]; /* for the future use */
860};
861
862/*
863 * IOCTL commands
864 */
865
866#define SNDRV_SEQ_IOCTL_PVERSION _IOR ('S', 0x00, int)
867#define SNDRV_SEQ_IOCTL_CLIENT_ID _IOR ('S', 0x01, int)
868#define SNDRV_SEQ_IOCTL_SYSTEM_INFO _IOWR('S', 0x02, struct sndrv_seq_system_info)
869#define SNDRV_SEQ_IOCTL_RUNNING_MODE _IOWR('S', 0x03, struct sndrv_seq_running_info)
870
871#define SNDRV_SEQ_IOCTL_GET_CLIENT_INFO _IOWR('S', 0x10, struct sndrv_seq_client_info)
872#define SNDRV_SEQ_IOCTL_SET_CLIENT_INFO _IOW ('S', 0x11, struct sndrv_seq_client_info)
873
874#define SNDRV_SEQ_IOCTL_CREATE_PORT _IOWR('S', 0x20, struct sndrv_seq_port_info)
875#define SNDRV_SEQ_IOCTL_DELETE_PORT _IOW ('S', 0x21, struct sndrv_seq_port_info)
876#define SNDRV_SEQ_IOCTL_GET_PORT_INFO _IOWR('S', 0x22, struct sndrv_seq_port_info)
877#define SNDRV_SEQ_IOCTL_SET_PORT_INFO _IOW ('S', 0x23, struct sndrv_seq_port_info)
878
879#define SNDRV_SEQ_IOCTL_SUBSCRIBE_PORT _IOW ('S', 0x30, struct sndrv_seq_port_subscribe)
880#define SNDRV_SEQ_IOCTL_UNSUBSCRIBE_PORT _IOW ('S', 0x31, struct sndrv_seq_port_subscribe)
881
882#define SNDRV_SEQ_IOCTL_CREATE_QUEUE _IOWR('S', 0x32, struct sndrv_seq_queue_info)
883#define SNDRV_SEQ_IOCTL_DELETE_QUEUE _IOW ('S', 0x33, struct sndrv_seq_queue_info)
884#define SNDRV_SEQ_IOCTL_GET_QUEUE_INFO _IOWR('S', 0x34, struct sndrv_seq_queue_info)
885#define SNDRV_SEQ_IOCTL_SET_QUEUE_INFO _IOWR('S', 0x35, struct sndrv_seq_queue_info)
886#define SNDRV_SEQ_IOCTL_GET_NAMED_QUEUE _IOWR('S', 0x36, struct sndrv_seq_queue_info)
887#define SNDRV_SEQ_IOCTL_GET_QUEUE_STATUS _IOWR('S', 0x40, struct sndrv_seq_queue_status)
888#define SNDRV_SEQ_IOCTL_GET_QUEUE_TEMPO _IOWR('S', 0x41, struct sndrv_seq_queue_tempo)
889#define SNDRV_SEQ_IOCTL_SET_QUEUE_TEMPO _IOW ('S', 0x42, struct sndrv_seq_queue_tempo)
890#define SNDRV_SEQ_IOCTL_GET_QUEUE_OWNER _IOWR('S', 0x43, struct sndrv_seq_queue_owner)
891#define SNDRV_SEQ_IOCTL_SET_QUEUE_OWNER _IOW ('S', 0x44, struct sndrv_seq_queue_owner)
892#define SNDRV_SEQ_IOCTL_GET_QUEUE_TIMER _IOWR('S', 0x45, struct sndrv_seq_queue_timer)
893#define SNDRV_SEQ_IOCTL_SET_QUEUE_TIMER _IOW ('S', 0x46, struct sndrv_seq_queue_timer)
894/* XXX
895#define SNDRV_SEQ_IOCTL_GET_QUEUE_SYNC _IOWR('S', 0x53, struct sndrv_seq_queue_sync)
896#define SNDRV_SEQ_IOCTL_SET_QUEUE_SYNC _IOW ('S', 0x54, struct sndrv_seq_queue_sync)
897*/
898#define SNDRV_SEQ_IOCTL_GET_QUEUE_CLIENT _IOWR('S', 0x49, struct sndrv_seq_queue_client)
899#define SNDRV_SEQ_IOCTL_SET_QUEUE_CLIENT _IOW ('S', 0x4a, struct sndrv_seq_queue_client)
900#define SNDRV_SEQ_IOCTL_GET_CLIENT_POOL _IOWR('S', 0x4b, struct sndrv_seq_client_pool)
901#define SNDRV_SEQ_IOCTL_SET_CLIENT_POOL _IOW ('S', 0x4c, struct sndrv_seq_client_pool)
902#define SNDRV_SEQ_IOCTL_REMOVE_EVENTS _IOW ('S', 0x4e, struct sndrv_seq_remove_events)
903#define SNDRV_SEQ_IOCTL_QUERY_SUBS _IOWR('S', 0x4f, struct sndrv_seq_query_subs)
904#define SNDRV_SEQ_IOCTL_GET_SUBSCRIPTION _IOWR('S', 0x50, struct sndrv_seq_port_subscribe)
905#define SNDRV_SEQ_IOCTL_QUERY_NEXT_CLIENT _IOWR('S', 0x51, struct sndrv_seq_client_info)
906#define SNDRV_SEQ_IOCTL_QUERY_NEXT_PORT _IOWR('S', 0x52, struct sndrv_seq_port_info)
907
908#endif /* __SOUND_ASEQUENCER_H */
diff --git a/include/sound/asound.h b/include/sound/asound.h
new file mode 100644
index 000000000000..a4d149f34541
--- /dev/null
+++ b/include/sound/asound.h
@@ -0,0 +1,927 @@
1/*
2 * Advanced Linux Sound Architecture - ALSA - Driver
3 * Copyright (c) 1994-2003 by Jaroslav Kysela <perex@suse.cz>,
4 * Abramo Bagnara <abramo@alsa-project.org>
5 *
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#ifndef __SOUND_ASOUND_H
24#define __SOUND_ASOUND_H
25
26#if defined(LINUX) || defined(__LINUX__) || defined(__linux__)
27
28#include <linux/ioctl.h>
29
30#ifdef __KERNEL__
31
32#include <linux/types.h>
33#include <linux/time.h>
34#include <asm/byteorder.h>
35
36#ifdef __LITTLE_ENDIAN
37#define SNDRV_LITTLE_ENDIAN
38#else
39#ifdef __BIG_ENDIAN
40#define SNDRV_BIG_ENDIAN
41#else
42#error "Unsupported endian..."
43#endif
44#endif
45
46#else /* !__KERNEL__ */
47
48#include <endian.h>
49#if __BYTE_ORDER == __LITTLE_ENDIAN
50#define SNDRV_LITTLE_ENDIAN
51#elif __BYTE_ORDER == __BIG_ENDIAN
52#define SNDRV_BIG_ENDIAN
53#else
54#error "Unsupported endian..."
55#endif
56
57#endif /* __KERNEL **/
58
59#endif /* LINUX */
60
61#ifndef __KERNEL__
62#include <sys/time.h>
63#include <sys/types.h>
64#endif
65
66/*
67 * protocol version
68 */
69
70#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor))
71#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff)
72#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff)
73#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff)
74#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \
75 (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \
76 (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \
77 SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion)))
78
79/****************************************************************************
80 * *
81 * Digital audio interface *
82 * *
83 ****************************************************************************/
84
85struct sndrv_aes_iec958 {
86 unsigned char status[24]; /* AES/IEC958 channel status bits */
87 unsigned char subcode[147]; /* AES/IEC958 subcode bits */
88 unsigned char pad; /* nothing */
89 unsigned char dig_subframe[4]; /* AES/IEC958 subframe bits */
90};
91
92/****************************************************************************
93 * *
94 * Section for driver hardware dependent interface - /dev/snd/hw? *
95 * *
96 ****************************************************************************/
97
98#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
99
100enum sndrv_hwdep_iface {
101 SNDRV_HWDEP_IFACE_OPL2 = 0,
102 SNDRV_HWDEP_IFACE_OPL3,
103 SNDRV_HWDEP_IFACE_OPL4,
104 SNDRV_HWDEP_IFACE_SB16CSP, /* Creative Signal Processor */
105 SNDRV_HWDEP_IFACE_EMU10K1, /* FX8010 processor in EMU10K1 chip */
106 SNDRV_HWDEP_IFACE_YSS225, /* Yamaha FX processor */
107 SNDRV_HWDEP_IFACE_ICS2115, /* Wavetable synth */
108 SNDRV_HWDEP_IFACE_SSCAPE, /* Ensoniq SoundScape ISA card (MC68EC000) */
109 SNDRV_HWDEP_IFACE_VX, /* Digigram VX cards */
110 SNDRV_HWDEP_IFACE_MIXART, /* Digigram miXart cards */
111 SNDRV_HWDEP_IFACE_USX2Y, /* Tascam US122, US224 & US428 usb */
112 SNDRV_HWDEP_IFACE_EMUX_WAVETABLE, /* EmuX wavetable */
113 SNDRV_HWDEP_IFACE_BLUETOOTH, /* Bluetooth audio */
114 SNDRV_HWDEP_IFACE_USX2Y_PCM, /* Tascam US122, US224 & US428 rawusb pcm */
115 SNDRV_HWDEP_IFACE_PCXHR, /* Digigram PCXHR */
116
117 /* Don't forget to change the following: */
118 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_PCXHR
119};
120
121struct sndrv_hwdep_info {
122 unsigned int device; /* WR: device number */
123 int card; /* R: card number */
124 unsigned char id[64]; /* ID (user selectable) */
125 unsigned char name[80]; /* hwdep name */
126 enum sndrv_hwdep_iface iface; /* hwdep interface */
127 unsigned char reserved[64]; /* reserved for future */
128};
129
130/* generic DSP loader */
131struct sndrv_hwdep_dsp_status {
132 unsigned int version; /* R: driver-specific version */
133 unsigned char id[32]; /* R: driver-specific ID string */
134 unsigned int num_dsps; /* R: number of DSP images to transfer */
135 unsigned int dsp_loaded; /* R: bit flags indicating the loaded DSPs */
136 unsigned int chip_ready; /* R: 1 = initialization finished */
137 unsigned char reserved[16]; /* reserved for future use */
138};
139
140struct sndrv_hwdep_dsp_image {
141 unsigned int index; /* W: DSP index */
142 unsigned char name[64]; /* W: ID (e.g. file name) */
143 unsigned char __user *image; /* W: binary image */
144 size_t length; /* W: size of image in bytes */
145 unsigned long driver_data; /* W: driver-specific data */
146};
147
148enum {
149 SNDRV_HWDEP_IOCTL_PVERSION = _IOR ('H', 0x00, int),
150 SNDRV_HWDEP_IOCTL_INFO = _IOR ('H', 0x01, struct sndrv_hwdep_info),
151 SNDRV_HWDEP_IOCTL_DSP_STATUS = _IOR('H', 0x02, struct sndrv_hwdep_dsp_status),
152 SNDRV_HWDEP_IOCTL_DSP_LOAD = _IOW('H', 0x03, struct sndrv_hwdep_dsp_image)
153};
154
155/*****************************************************************************
156 * *
157 * Digital Audio (PCM) interface - /dev/snd/pcm?? *
158 * *
159 *****************************************************************************/
160
161#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7)
162
163typedef unsigned long sndrv_pcm_uframes_t;
164typedef long sndrv_pcm_sframes_t;
165
166enum sndrv_pcm_class {
167 SNDRV_PCM_CLASS_GENERIC = 0, /* standard mono or stereo device */
168 SNDRV_PCM_CLASS_MULTI, /* multichannel device */
169 SNDRV_PCM_CLASS_MODEM, /* software modem class */
170 SNDRV_PCM_CLASS_DIGITIZER, /* digitizer class */
171 /* Don't forget to change the following: */
172 SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER,
173};
174
175enum sndrv_pcm_subclass {
176 SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0, /* mono or stereo subdevices are mixed together */
177 SNDRV_PCM_SUBCLASS_MULTI_MIX, /* multichannel subdevices are mixed together */
178 /* Don't forget to change the following: */
179 SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX,
180};
181
182enum sndrv_pcm_stream {
183 SNDRV_PCM_STREAM_PLAYBACK = 0,
184 SNDRV_PCM_STREAM_CAPTURE,
185 SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE,
186};
187
188enum sndrv_pcm_access {
189 SNDRV_PCM_ACCESS_MMAP_INTERLEAVED = 0, /* interleaved mmap */
190 SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED, /* noninterleaved mmap */
191 SNDRV_PCM_ACCESS_MMAP_COMPLEX, /* complex mmap */
192 SNDRV_PCM_ACCESS_RW_INTERLEAVED, /* readi/writei */
193 SNDRV_PCM_ACCESS_RW_NONINTERLEAVED, /* readn/writen */
194 SNDRV_PCM_ACCESS_LAST = SNDRV_PCM_ACCESS_RW_NONINTERLEAVED,
195};
196
197enum sndrv_pcm_format {
198 SNDRV_PCM_FORMAT_S8 = 0,
199 SNDRV_PCM_FORMAT_U8,
200 SNDRV_PCM_FORMAT_S16_LE,
201 SNDRV_PCM_FORMAT_S16_BE,
202 SNDRV_PCM_FORMAT_U16_LE,
203 SNDRV_PCM_FORMAT_U16_BE,
204 SNDRV_PCM_FORMAT_S24_LE, /* low three bytes */
205 SNDRV_PCM_FORMAT_S24_BE, /* low three bytes */
206 SNDRV_PCM_FORMAT_U24_LE, /* low three bytes */
207 SNDRV_PCM_FORMAT_U24_BE, /* low three bytes */
208 SNDRV_PCM_FORMAT_S32_LE,
209 SNDRV_PCM_FORMAT_S32_BE,
210 SNDRV_PCM_FORMAT_U32_LE,
211 SNDRV_PCM_FORMAT_U32_BE,
212 SNDRV_PCM_FORMAT_FLOAT_LE, /* 4-byte float, IEEE-754 32-bit, range -1.0 to 1.0 */
213 SNDRV_PCM_FORMAT_FLOAT_BE, /* 4-byte float, IEEE-754 32-bit, range -1.0 to 1.0 */
214 SNDRV_PCM_FORMAT_FLOAT64_LE, /* 8-byte float, IEEE-754 64-bit, range -1.0 to 1.0 */
215 SNDRV_PCM_FORMAT_FLOAT64_BE, /* 8-byte float, IEEE-754 64-bit, range -1.0 to 1.0 */
216 SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE, /* IEC-958 subframe, Little Endian */
217 SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE, /* IEC-958 subframe, Big Endian */
218 SNDRV_PCM_FORMAT_MU_LAW,
219 SNDRV_PCM_FORMAT_A_LAW,
220 SNDRV_PCM_FORMAT_IMA_ADPCM,
221 SNDRV_PCM_FORMAT_MPEG,
222 SNDRV_PCM_FORMAT_GSM,
223 SNDRV_PCM_FORMAT_SPECIAL = 31,
224 SNDRV_PCM_FORMAT_S24_3LE = 32, /* in three bytes */
225 SNDRV_PCM_FORMAT_S24_3BE, /* in three bytes */
226 SNDRV_PCM_FORMAT_U24_3LE, /* in three bytes */
227 SNDRV_PCM_FORMAT_U24_3BE, /* in three bytes */
228 SNDRV_PCM_FORMAT_S20_3LE, /* in three bytes */
229 SNDRV_PCM_FORMAT_S20_3BE, /* in three bytes */
230 SNDRV_PCM_FORMAT_U20_3LE, /* in three bytes */
231 SNDRV_PCM_FORMAT_U20_3BE, /* in three bytes */
232 SNDRV_PCM_FORMAT_S18_3LE, /* in three bytes */
233 SNDRV_PCM_FORMAT_S18_3BE, /* in three bytes */
234 SNDRV_PCM_FORMAT_U18_3LE, /* in three bytes */
235 SNDRV_PCM_FORMAT_U18_3BE, /* in three bytes */
236 SNDRV_PCM_FORMAT_LAST = SNDRV_PCM_FORMAT_U18_3BE,
237
238#ifdef SNDRV_LITTLE_ENDIAN
239 SNDRV_PCM_FORMAT_S16 = SNDRV_PCM_FORMAT_S16_LE,
240 SNDRV_PCM_FORMAT_U16 = SNDRV_PCM_FORMAT_U16_LE,
241 SNDRV_PCM_FORMAT_S24 = SNDRV_PCM_FORMAT_S24_LE,
242 SNDRV_PCM_FORMAT_U24 = SNDRV_PCM_FORMAT_U24_LE,
243 SNDRV_PCM_FORMAT_S32 = SNDRV_PCM_FORMAT_S32_LE,
244 SNDRV_PCM_FORMAT_U32 = SNDRV_PCM_FORMAT_U32_LE,
245 SNDRV_PCM_FORMAT_FLOAT = SNDRV_PCM_FORMAT_FLOAT_LE,
246 SNDRV_PCM_FORMAT_FLOAT64 = SNDRV_PCM_FORMAT_FLOAT64_LE,
247 SNDRV_PCM_FORMAT_IEC958_SUBFRAME = SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE,
248#endif
249#ifdef SNDRV_BIG_ENDIAN
250 SNDRV_PCM_FORMAT_S16 = SNDRV_PCM_FORMAT_S16_BE,
251 SNDRV_PCM_FORMAT_U16 = SNDRV_PCM_FORMAT_U16_BE,
252 SNDRV_PCM_FORMAT_S24 = SNDRV_PCM_FORMAT_S24_BE,
253 SNDRV_PCM_FORMAT_U24 = SNDRV_PCM_FORMAT_U24_BE,
254 SNDRV_PCM_FORMAT_S32 = SNDRV_PCM_FORMAT_S32_BE,
255 SNDRV_PCM_FORMAT_U32 = SNDRV_PCM_FORMAT_U32_BE,
256 SNDRV_PCM_FORMAT_FLOAT = SNDRV_PCM_FORMAT_FLOAT_BE,
257 SNDRV_PCM_FORMAT_FLOAT64 = SNDRV_PCM_FORMAT_FLOAT64_BE,
258 SNDRV_PCM_FORMAT_IEC958_SUBFRAME = SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE,
259#endif
260};
261
262enum sndrv_pcm_subformat {
263 SNDRV_PCM_SUBFORMAT_STD = 0,
264 SNDRV_PCM_SUBFORMAT_LAST = SNDRV_PCM_SUBFORMAT_STD,
265};
266
267#define SNDRV_PCM_INFO_MMAP 0x00000001 /* hardware supports mmap */
268#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002 /* period data are valid during transfer */
269#define SNDRV_PCM_INFO_DOUBLE 0x00000004 /* Double buffering needed for PCM start/stop */
270#define SNDRV_PCM_INFO_BATCH 0x00000010 /* double buffering */
271#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100 /* channels are interleaved */
272#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200 /* channels are not interleaved */
273#define SNDRV_PCM_INFO_COMPLEX 0x00000400 /* complex frame organization (mmap only) */
274#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000 /* hardware transfer block of samples */
275#define SNDRV_PCM_INFO_OVERRANGE 0x00020000 /* hardware supports ADC (capture) overrange detection */
276#define SNDRV_PCM_INFO_RESUME 0x00040000 /* hardware supports stream resume after suspend */
277#define SNDRV_PCM_INFO_PAUSE 0x00080000 /* pause ioctl is supported */
278#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000 /* only half duplex */
279#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000 /* playback and capture stream are somewhat correlated */
280#define SNDRV_PCM_INFO_SYNC_START 0x00400000 /* pcm support some kind of sync go */
281
282enum sndrv_pcm_state {
283 SNDRV_PCM_STATE_OPEN = 0, /* stream is open */
284 SNDRV_PCM_STATE_SETUP, /* stream has a setup */
285 SNDRV_PCM_STATE_PREPARED, /* stream is ready to start */
286 SNDRV_PCM_STATE_RUNNING, /* stream is running */
287 SNDRV_PCM_STATE_XRUN, /* stream reached an xrun */
288 SNDRV_PCM_STATE_DRAINING, /* stream is draining */
289 SNDRV_PCM_STATE_PAUSED, /* stream is paused */
290 SNDRV_PCM_STATE_SUSPENDED, /* hardware is suspended */
291 SNDRV_PCM_STATE_DISCONNECTED, /* hardware is disconnected */
292 SNDRV_PCM_STATE_LAST = SNDRV_PCM_STATE_DISCONNECTED,
293};
294
295enum {
296 SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000,
297 SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000,
298 SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000,
299};
300
301union sndrv_pcm_sync_id {
302 unsigned char id[16];
303 unsigned short id16[8];
304 unsigned int id32[4];
305};
306
307struct sndrv_pcm_info {
308 unsigned int device; /* RO/WR (control): device number */
309 unsigned int subdevice; /* RO/WR (control): subdevice number */
310 enum sndrv_pcm_stream stream; /* RO/WR (control): stream number */
311 int card; /* R: card number */
312 unsigned char id[64]; /* ID (user selectable) */
313 unsigned char name[80]; /* name of this device */
314 unsigned char subname[32]; /* subdevice name */
315 enum sndrv_pcm_class dev_class; /* SNDRV_PCM_CLASS_* */
316 enum sndrv_pcm_subclass dev_subclass; /* SNDRV_PCM_SUBCLASS_* */
317 unsigned int subdevices_count;
318 unsigned int subdevices_avail;
319 union sndrv_pcm_sync_id sync; /* hardware synchronization ID */
320 unsigned char reserved[64]; /* reserved for future... */
321};
322
323enum sndrv_pcm_hw_param {
324 SNDRV_PCM_HW_PARAM_ACCESS = 0, /* Access type */
325 SNDRV_PCM_HW_PARAM_FIRST_MASK = SNDRV_PCM_HW_PARAM_ACCESS,
326 SNDRV_PCM_HW_PARAM_FORMAT, /* Format */
327 SNDRV_PCM_HW_PARAM_SUBFORMAT, /* Subformat */
328 SNDRV_PCM_HW_PARAM_LAST_MASK = SNDRV_PCM_HW_PARAM_SUBFORMAT,
329
330 SNDRV_PCM_HW_PARAM_SAMPLE_BITS = 8, /* Bits per sample */
331 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL = SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
332 SNDRV_PCM_HW_PARAM_FRAME_BITS, /* Bits per frame */
333 SNDRV_PCM_HW_PARAM_CHANNELS, /* Channels */
334 SNDRV_PCM_HW_PARAM_RATE, /* Approx rate */
335 SNDRV_PCM_HW_PARAM_PERIOD_TIME, /* Approx distance between interrupts
336 in us */
337 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, /* Approx frames between interrupts */
338 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, /* Approx bytes between interrupts */
339 SNDRV_PCM_HW_PARAM_PERIODS, /* Approx interrupts per buffer */
340 SNDRV_PCM_HW_PARAM_BUFFER_TIME, /* Approx duration of buffer in us */
341 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, /* Size of buffer in frames */
342 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, /* Size of buffer in bytes */
343 SNDRV_PCM_HW_PARAM_TICK_TIME, /* Approx tick duration in us */
344 SNDRV_PCM_HW_PARAM_LAST_INTERVAL = SNDRV_PCM_HW_PARAM_TICK_TIME
345};
346
347#define SNDRV_PCM_HW_PARAMS_RUNTIME (1<<0)
348
349struct sndrv_interval {
350 unsigned int min, max;
351 unsigned int openmin:1,
352 openmax:1,
353 integer:1,
354 empty:1;
355};
356
357#define SNDRV_MASK_MAX 256
358
359struct sndrv_mask {
360 u_int32_t bits[(SNDRV_MASK_MAX+31)/32];
361};
362
363struct sndrv_pcm_hw_params {
364 unsigned int flags;
365 struct sndrv_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK -
366 SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
367 struct sndrv_mask mres[5]; /* reserved masks */
368 struct sndrv_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL -
369 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
370 struct sndrv_interval ires[9]; /* reserved intervals */
371 unsigned int rmask; /* W: requested masks */
372 unsigned int cmask; /* R: changed masks */
373 unsigned int info; /* R: Info flags for returned setup */
374 unsigned int msbits; /* R: used most significant bits */
375 unsigned int rate_num; /* R: rate numerator */
376 unsigned int rate_den; /* R: rate denominator */
377 sndrv_pcm_uframes_t fifo_size; /* R: chip FIFO size in frames */
378 unsigned char reserved[64]; /* reserved for future */
379};
380
381enum sndrv_pcm_tstamp {
382 SNDRV_PCM_TSTAMP_NONE = 0,
383 SNDRV_PCM_TSTAMP_MMAP,
384 SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_MMAP,
385};
386
387struct sndrv_pcm_sw_params {
388 enum sndrv_pcm_tstamp tstamp_mode; /* timestamp mode */
389 unsigned int period_step;
390 unsigned int sleep_min; /* min ticks to sleep */
391 sndrv_pcm_uframes_t avail_min; /* min avail frames for wakeup */
392 sndrv_pcm_uframes_t xfer_align; /* xfer size need to be a multiple */
393 sndrv_pcm_uframes_t start_threshold; /* min hw_avail frames for automatic start */
394 sndrv_pcm_uframes_t stop_threshold; /* min avail frames for automatic stop */
395 sndrv_pcm_uframes_t silence_threshold; /* min distance from noise for silence filling */
396 sndrv_pcm_uframes_t silence_size; /* silence block size */
397 sndrv_pcm_uframes_t boundary; /* pointers wrap point */
398 unsigned char reserved[64]; /* reserved for future */
399};
400
401struct sndrv_pcm_channel_info {
402 unsigned int channel;
403 off_t offset; /* mmap offset */
404 unsigned int first; /* offset to first sample in bits */
405 unsigned int step; /* samples distance in bits */
406};
407
408struct sndrv_pcm_status {
409 enum sndrv_pcm_state state; /* stream state */
410 struct timespec trigger_tstamp; /* time when stream was started/stopped/paused */
411 struct timespec tstamp; /* reference timestamp */
412 sndrv_pcm_uframes_t appl_ptr; /* appl ptr */
413 sndrv_pcm_uframes_t hw_ptr; /* hw ptr */
414 sndrv_pcm_sframes_t delay; /* current delay in frames */
415 sndrv_pcm_uframes_t avail; /* number of frames available */
416 sndrv_pcm_uframes_t avail_max; /* max frames available on hw since last status */
417 sndrv_pcm_uframes_t overrange; /* count of ADC (capture) overrange detections from last status */
418 enum sndrv_pcm_state suspended_state; /* suspended stream state */
419 unsigned char reserved[60]; /* must be filled with zero */
420};
421
422struct sndrv_pcm_mmap_status {
423 enum sndrv_pcm_state state; /* RO: state - SNDRV_PCM_STATE_XXXX */
424 int pad1; /* Needed for 64 bit alignment */
425 sndrv_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */
426 struct timespec tstamp; /* Timestamp */
427 enum sndrv_pcm_state suspended_state; /* RO: suspended stream state */
428};
429
430struct sndrv_pcm_mmap_control {
431 sndrv_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */
432 sndrv_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */
433};
434
435#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0) /* execute hwsync */
436#define SNDRV_PCM_SYNC_PTR_APPL (1<<1) /* get appl_ptr from driver (r/w op) */
437#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2) /* get avail_min from driver */
438
439struct sndrv_pcm_sync_ptr {
440 unsigned int flags;
441 union {
442 struct sndrv_pcm_mmap_status status;
443 unsigned char reserved[64];
444 } s;
445 union {
446 struct sndrv_pcm_mmap_control control;
447 unsigned char reserved[64];
448 } c;
449};
450
451struct sndrv_xferi {
452 sndrv_pcm_sframes_t result;
453 void __user *buf;
454 sndrv_pcm_uframes_t frames;
455};
456
457struct sndrv_xfern {
458 sndrv_pcm_sframes_t result;
459 void __user * __user *bufs;
460 sndrv_pcm_uframes_t frames;
461};
462
463enum {
464 SNDRV_PCM_IOCTL_PVERSION = _IOR('A', 0x00, int),
465 SNDRV_PCM_IOCTL_INFO = _IOR('A', 0x01, struct sndrv_pcm_info),
466 SNDRV_PCM_IOCTL_TSTAMP = _IOW('A', 0x02, int),
467 SNDRV_PCM_IOCTL_HW_REFINE = _IOWR('A', 0x10, struct sndrv_pcm_hw_params),
468 SNDRV_PCM_IOCTL_HW_PARAMS = _IOWR('A', 0x11, struct sndrv_pcm_hw_params),
469 SNDRV_PCM_IOCTL_HW_FREE = _IO('A', 0x12),
470 SNDRV_PCM_IOCTL_SW_PARAMS = _IOWR('A', 0x13, struct sndrv_pcm_sw_params),
471 SNDRV_PCM_IOCTL_STATUS = _IOR('A', 0x20, struct sndrv_pcm_status),
472 SNDRV_PCM_IOCTL_DELAY = _IOR('A', 0x21, sndrv_pcm_sframes_t),
473 SNDRV_PCM_IOCTL_HWSYNC = _IO('A', 0x22),
474 SNDRV_PCM_IOCTL_SYNC_PTR = _IOWR('A', 0x23, struct sndrv_pcm_sync_ptr),
475 SNDRV_PCM_IOCTL_CHANNEL_INFO = _IOR('A', 0x32, struct sndrv_pcm_channel_info),
476 SNDRV_PCM_IOCTL_PREPARE = _IO('A', 0x40),
477 SNDRV_PCM_IOCTL_RESET = _IO('A', 0x41),
478 SNDRV_PCM_IOCTL_START = _IO('A', 0x42),
479 SNDRV_PCM_IOCTL_DROP = _IO('A', 0x43),
480 SNDRV_PCM_IOCTL_DRAIN = _IO('A', 0x44),
481 SNDRV_PCM_IOCTL_PAUSE = _IOW('A', 0x45, int),
482 SNDRV_PCM_IOCTL_REWIND = _IOW('A', 0x46, sndrv_pcm_uframes_t),
483 SNDRV_PCM_IOCTL_RESUME = _IO('A', 0x47),
484 SNDRV_PCM_IOCTL_XRUN = _IO('A', 0x48),
485 SNDRV_PCM_IOCTL_FORWARD = _IOW('A', 0x49, sndrv_pcm_uframes_t),
486 SNDRV_PCM_IOCTL_WRITEI_FRAMES = _IOW('A', 0x50, struct sndrv_xferi),
487 SNDRV_PCM_IOCTL_READI_FRAMES = _IOR('A', 0x51, struct sndrv_xferi),
488 SNDRV_PCM_IOCTL_WRITEN_FRAMES = _IOW('A', 0x52, struct sndrv_xfern),
489 SNDRV_PCM_IOCTL_READN_FRAMES = _IOR('A', 0x53, struct sndrv_xfern),
490 SNDRV_PCM_IOCTL_LINK = _IOW('A', 0x60, int),
491 SNDRV_PCM_IOCTL_UNLINK = _IO('A', 0x61),
492};
493
494/* Trick to make alsa-lib/acinclude.m4 happy */
495#define SNDRV_PCM_IOCTL_REWIND SNDRV_PCM_IOCTL_REWIND
496
497/*****************************************************************************
498 * *
499 * MIDI v1.0 interface *
500 * *
501 *****************************************************************************/
502
503/*
504 * Raw MIDI section - /dev/snd/midi??
505 */
506
507#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0)
508
509enum sndrv_rawmidi_stream {
510 SNDRV_RAWMIDI_STREAM_OUTPUT = 0,
511 SNDRV_RAWMIDI_STREAM_INPUT,
512 SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT,
513};
514
515#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001
516#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002
517#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004
518
519struct sndrv_rawmidi_info {
520 unsigned int device; /* RO/WR (control): device number */
521 unsigned int subdevice; /* RO/WR (control): subdevice number */
522 enum sndrv_rawmidi_stream stream; /* WR: stream */
523 int card; /* R: card number */
524 unsigned int flags; /* SNDRV_RAWMIDI_INFO_XXXX */
525 unsigned char id[64]; /* ID (user selectable) */
526 unsigned char name[80]; /* name of device */
527 unsigned char subname[32]; /* name of active or selected subdevice */
528 unsigned int subdevices_count;
529 unsigned int subdevices_avail;
530 unsigned char reserved[64]; /* reserved for future use */
531};
532
533struct sndrv_rawmidi_params {
534 enum sndrv_rawmidi_stream stream;
535 size_t buffer_size; /* queue size in bytes */
536 size_t avail_min; /* minimum avail bytes for wakeup */
537 unsigned int no_active_sensing: 1; /* do not send active sensing byte in close() */
538 unsigned char reserved[16]; /* reserved for future use */
539};
540
541struct sndrv_rawmidi_status {
542 enum sndrv_rawmidi_stream stream;
543 struct timespec tstamp; /* Timestamp */
544 size_t avail; /* available bytes */
545 size_t xruns; /* count of overruns since last status (in bytes) */
546 unsigned char reserved[16]; /* reserved for future use */
547};
548
549enum {
550 SNDRV_RAWMIDI_IOCTL_PVERSION = _IOR('W', 0x00, int),
551 SNDRV_RAWMIDI_IOCTL_INFO = _IOR('W', 0x01, struct sndrv_rawmidi_info),
552 SNDRV_RAWMIDI_IOCTL_PARAMS = _IOWR('W', 0x10, struct sndrv_rawmidi_params),
553 SNDRV_RAWMIDI_IOCTL_STATUS = _IOWR('W', 0x20, struct sndrv_rawmidi_status),
554 SNDRV_RAWMIDI_IOCTL_DROP = _IOW('W', 0x30, int),
555 SNDRV_RAWMIDI_IOCTL_DRAIN = _IOW('W', 0x31, int),
556};
557
558/*
559 * Timer section - /dev/snd/timer
560 */
561
562#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 2)
563
564enum sndrv_timer_class {
565 SNDRV_TIMER_CLASS_NONE = -1,
566 SNDRV_TIMER_CLASS_SLAVE = 0,
567 SNDRV_TIMER_CLASS_GLOBAL,
568 SNDRV_TIMER_CLASS_CARD,
569 SNDRV_TIMER_CLASS_PCM,
570 SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM,
571};
572
573/* slave timer classes */
574enum sndrv_timer_slave_class {
575 SNDRV_TIMER_SCLASS_NONE = 0,
576 SNDRV_TIMER_SCLASS_APPLICATION,
577 SNDRV_TIMER_SCLASS_SEQUENCER, /* alias */
578 SNDRV_TIMER_SCLASS_OSS_SEQUENCER, /* alias */
579 SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
580};
581
582/* global timers (device member) */
583#define SNDRV_TIMER_GLOBAL_SYSTEM 0
584#define SNDRV_TIMER_GLOBAL_RTC 1
585#define SNDRV_TIMER_GLOBAL_HPET 2
586
587/* info flags */
588#define SNDRV_TIMER_FLG_SLAVE (1<<0) /* cannot be controlled */
589
590struct sndrv_timer_id {
591 enum sndrv_timer_class dev_class;
592 enum sndrv_timer_slave_class dev_sclass;
593 int card;
594 int device;
595 int subdevice;
596};
597
598struct sndrv_timer_ginfo {
599 struct sndrv_timer_id tid; /* requested timer ID */
600 unsigned int flags; /* timer flags - SNDRV_TIMER_FLG_* */
601 int card; /* card number */
602 unsigned char id[64]; /* timer identification */
603 unsigned char name[80]; /* timer name */
604 unsigned long reserved0; /* reserved for future use */
605 unsigned long resolution; /* average period resolution in ns */
606 unsigned long resolution_min; /* minimal period resolution in ns */
607 unsigned long resolution_max; /* maximal period resolution in ns */
608 unsigned int clients; /* active timer clients */
609 unsigned char reserved[32];
610};
611
612struct sndrv_timer_gparams {
613 struct sndrv_timer_id tid; /* requested timer ID */
614 unsigned long period_num; /* requested precise period duration (in seconds) - numerator */
615 unsigned long period_den; /* requested precise period duration (in seconds) - denominator */
616 unsigned char reserved[32];
617};
618
619struct sndrv_timer_gstatus {
620 struct sndrv_timer_id tid; /* requested timer ID */
621 unsigned long resolution; /* current period resolution in ns */
622 unsigned long resolution_num; /* precise current period resolution (in seconds) - numerator */
623 unsigned long resolution_den; /* precise current period resolution (in seconds) - denominator */
624 unsigned char reserved[32];
625};
626
627struct sndrv_timer_select {
628 struct sndrv_timer_id id; /* bind to timer ID */
629 unsigned char reserved[32]; /* reserved */
630};
631
632struct sndrv_timer_info {
633 unsigned int flags; /* timer flags - SNDRV_TIMER_FLG_* */
634 int card; /* card number */
635 unsigned char id[64]; /* timer identificator */
636 unsigned char name[80]; /* timer name */
637 unsigned long reserved0; /* reserved for future use */
638 unsigned long resolution; /* average period resolution in ns */
639 unsigned char reserved[64]; /* reserved */
640};
641
642#define SNDRV_TIMER_PSFLG_AUTO (1<<0) /* auto start, otherwise one-shot */
643#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1) /* exclusive use, precise start/stop/pause/continue */
644#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2) /* write early event to the poll queue */
645
646struct sndrv_timer_params {
647 unsigned int flags; /* flags - SNDRV_MIXER_PSFLG_* */
648 unsigned int ticks; /* requested resolution in ticks */
649 unsigned int queue_size; /* total size of queue (32-1024) */
650 unsigned int reserved0; /* reserved, was: failure locations */
651 unsigned int filter; /* event filter (bitmask of SNDRV_TIMER_EVENT_*) */
652 unsigned char reserved[60]; /* reserved */
653};
654
655struct sndrv_timer_status {
656 struct timespec tstamp; /* Timestamp - last update */
657 unsigned int resolution; /* current period resolution in ns */
658 unsigned int lost; /* counter of master tick lost */
659 unsigned int overrun; /* count of read queue overruns */
660 unsigned int queue; /* used queue size */
661 unsigned char reserved[64]; /* reserved */
662};
663
664enum {
665 SNDRV_TIMER_IOCTL_PVERSION = _IOR('T', 0x00, int),
666 SNDRV_TIMER_IOCTL_NEXT_DEVICE = _IOWR('T', 0x01, struct sndrv_timer_id),
667 SNDRV_TIMER_IOCTL_TREAD = _IOW('T', 0x02, int),
668 SNDRV_TIMER_IOCTL_GINFO = _IOWR('T', 0x03, struct sndrv_timer_ginfo),
669 SNDRV_TIMER_IOCTL_GPARAMS = _IOW('T', 0x04, struct sndrv_timer_gparams),
670 SNDRV_TIMER_IOCTL_GSTATUS = _IOWR('T', 0x05, struct sndrv_timer_gstatus),
671 SNDRV_TIMER_IOCTL_SELECT = _IOW('T', 0x10, struct sndrv_timer_select),
672 SNDRV_TIMER_IOCTL_INFO = _IOR('T', 0x11, struct sndrv_timer_info),
673 SNDRV_TIMER_IOCTL_PARAMS = _IOW('T', 0x12, struct sndrv_timer_params),
674 SNDRV_TIMER_IOCTL_STATUS = _IOR('T', 0x14, struct sndrv_timer_status),
675 SNDRV_TIMER_IOCTL_START = _IO('T', 0x20),
676 SNDRV_TIMER_IOCTL_STOP = _IO('T', 0x21),
677 SNDRV_TIMER_IOCTL_CONTINUE = _IO('T', 0x22),
678 SNDRV_TIMER_IOCTL_PAUSE = _IO('T', 0x23),
679};
680
681struct sndrv_timer_read {
682 unsigned int resolution;
683 unsigned int ticks;
684};
685
686enum sndrv_timer_event {
687 SNDRV_TIMER_EVENT_RESOLUTION = 0, /* val = resolution in ns */
688 SNDRV_TIMER_EVENT_TICK, /* val = ticks */
689 SNDRV_TIMER_EVENT_START, /* val = resolution in ns */
690 SNDRV_TIMER_EVENT_STOP, /* val = 0 */
691 SNDRV_TIMER_EVENT_CONTINUE, /* val = resolution in ns */
692 SNDRV_TIMER_EVENT_PAUSE, /* val = 0 */
693 SNDRV_TIMER_EVENT_EARLY, /* val = 0, early event */
694 /* master timer events for slave timer instances */
695 SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
696 SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
697 SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
698 SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
699};
700
701struct sndrv_timer_tread {
702 enum sndrv_timer_event event;
703 struct timespec tstamp;
704 unsigned int val;
705};
706
707/****************************************************************************
708 * *
709 * Section for driver control interface - /dev/snd/control? *
710 * *
711 ****************************************************************************/
712
713#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 3)
714
715struct sndrv_ctl_card_info {
716 int card; /* card number */
717 int pad; /* reserved for future (was type) */
718 unsigned char id[16]; /* ID of card (user selectable) */
719 unsigned char driver[16]; /* Driver name */
720 unsigned char name[32]; /* Short name of soundcard */
721 unsigned char longname[80]; /* name + info text about soundcard */
722 unsigned char reserved_[16]; /* reserved for future (was ID of mixer) */
723 unsigned char mixername[80]; /* visual mixer identification */
724 unsigned char components[80]; /* card components / fine identification, delimited with one space (AC97 etc..) */
725 unsigned char reserved[48]; /* reserved for future */
726};
727
728enum sndrv_ctl_elem_type {
729 SNDRV_CTL_ELEM_TYPE_NONE = 0, /* invalid */
730 SNDRV_CTL_ELEM_TYPE_BOOLEAN, /* boolean type */
731 SNDRV_CTL_ELEM_TYPE_INTEGER, /* integer type */
732 SNDRV_CTL_ELEM_TYPE_ENUMERATED, /* enumerated type */
733 SNDRV_CTL_ELEM_TYPE_BYTES, /* byte array */
734 SNDRV_CTL_ELEM_TYPE_IEC958, /* IEC958 (S/PDIF) setup */
735 SNDRV_CTL_ELEM_TYPE_INTEGER64, /* 64-bit integer type */
736 SNDRV_CTL_ELEM_TYPE_LAST = SNDRV_CTL_ELEM_TYPE_INTEGER64,
737};
738
739enum sndrv_ctl_elem_iface {
740 SNDRV_CTL_ELEM_IFACE_CARD = 0, /* global control */
741 SNDRV_CTL_ELEM_IFACE_HWDEP, /* hardware dependent device */
742 SNDRV_CTL_ELEM_IFACE_MIXER, /* virtual mixer device */
743 SNDRV_CTL_ELEM_IFACE_PCM, /* PCM device */
744 SNDRV_CTL_ELEM_IFACE_RAWMIDI, /* RawMidi device */
745 SNDRV_CTL_ELEM_IFACE_TIMER, /* timer device */
746 SNDRV_CTL_ELEM_IFACE_SEQUENCER, /* sequencer client */
747 SNDRV_CTL_ELEM_IFACE_LAST = SNDRV_CTL_ELEM_IFACE_SEQUENCER,
748};
749
750#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0)
751#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1)
752#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE)
753#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2) /* control value may be changed without a notification */
754#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<2) /* when was control changed */
755#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8) /* control does actually nothing, but may be updated */
756#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9) /* write lock */
757#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10) /* write lock owner */
758#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29) /* user space element */
759#define SNDRV_CTL_ELEM_ACCESS_DINDIRECT (1<<30) /* indirect access for matrix dimensions in the info structure */
760#define SNDRV_CTL_ELEM_ACCESS_INDIRECT (1<<31) /* indirect access for element value in the value structure */
761
762/* for further details see the ACPI and PCI power management specification */
763#define SNDRV_CTL_POWER_D0 0x0000 /* full On */
764#define SNDRV_CTL_POWER_D1 0x0100 /* partial On */
765#define SNDRV_CTL_POWER_D2 0x0200 /* partial On */
766#define SNDRV_CTL_POWER_D3 0x0300 /* Off */
767#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000) /* Off, with power */
768#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001) /* Off, without power */
769
770struct sndrv_ctl_elem_id {
771 unsigned int numid; /* numeric identifier, zero = invalid */
772 enum sndrv_ctl_elem_iface iface; /* interface identifier */
773 unsigned int device; /* device/client number */
774 unsigned int subdevice; /* subdevice (substream) number */
775 unsigned char name[44]; /* ASCII name of item */
776 unsigned int index; /* index of item */
777};
778
779struct sndrv_ctl_elem_list {
780 unsigned int offset; /* W: first element ID to get */
781 unsigned int space; /* W: count of element IDs to get */
782 unsigned int used; /* R: count of element IDs set */
783 unsigned int count; /* R: count of all elements */
784 struct sndrv_ctl_elem_id __user *pids; /* R: IDs */
785 unsigned char reserved[50];
786};
787
788struct sndrv_ctl_elem_info {
789 struct sndrv_ctl_elem_id id; /* W: element ID */
790 enum sndrv_ctl_elem_type type; /* R: value type - SNDRV_CTL_ELEM_TYPE_* */
791 unsigned int access; /* R: value access (bitmask) - SNDRV_CTL_ELEM_ACCESS_* */
792 unsigned int count; /* count of values */
793 pid_t owner; /* owner's PID of this control */
794 union {
795 struct {
796 long min; /* R: minimum value */
797 long max; /* R: maximum value */
798 long step; /* R: step (0 variable) */
799 } integer;
800 struct {
801 long long min; /* R: minimum value */
802 long long max; /* R: maximum value */
803 long long step; /* R: step (0 variable) */
804 } integer64;
805 struct {
806 unsigned int items; /* R: number of items */
807 unsigned int item; /* W: item number */
808 char name[64]; /* R: value name */
809 } enumerated;
810 unsigned char reserved[128];
811 } value;
812 union {
813 unsigned short d[4]; /* dimensions */
814 unsigned short *d_ptr; /* indirect */
815 } dimen;
816 unsigned char reserved[64-4*sizeof(unsigned short)];
817};
818
819struct sndrv_ctl_elem_value {
820 struct sndrv_ctl_elem_id id; /* W: element ID */
821 unsigned int indirect: 1; /* W: use indirect pointer (xxx_ptr member) */
822 union {
823 union {
824 long value[128];
825 long *value_ptr;
826 } integer;
827 union {
828 long long value[64];
829 long long *value_ptr;
830 } integer64;
831 union {
832 unsigned int item[128];
833 unsigned int *item_ptr;
834 } enumerated;
835 union {
836 unsigned char data[512];
837 unsigned char *data_ptr;
838 } bytes;
839 struct sndrv_aes_iec958 iec958;
840 } value; /* RO */
841 struct timespec tstamp;
842 unsigned char reserved[128-sizeof(struct timespec)];
843};
844
845enum {
846 SNDRV_CTL_IOCTL_PVERSION = _IOR('U', 0x00, int),
847 SNDRV_CTL_IOCTL_CARD_INFO = _IOR('U', 0x01, struct sndrv_ctl_card_info),
848 SNDRV_CTL_IOCTL_ELEM_LIST = _IOWR('U', 0x10, struct sndrv_ctl_elem_list),
849 SNDRV_CTL_IOCTL_ELEM_INFO = _IOWR('U', 0x11, struct sndrv_ctl_elem_info),
850 SNDRV_CTL_IOCTL_ELEM_READ = _IOWR('U', 0x12, struct sndrv_ctl_elem_value),
851 SNDRV_CTL_IOCTL_ELEM_WRITE = _IOWR('U', 0x13, struct sndrv_ctl_elem_value),
852 SNDRV_CTL_IOCTL_ELEM_LOCK = _IOW('U', 0x14, struct sndrv_ctl_elem_id),
853 SNDRV_CTL_IOCTL_ELEM_UNLOCK = _IOW('U', 0x15, struct sndrv_ctl_elem_id),
854 SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS = _IOWR('U', 0x16, int),
855 SNDRV_CTL_IOCTL_ELEM_ADD = _IOWR('U', 0x17, struct sndrv_ctl_elem_info),
856 SNDRV_CTL_IOCTL_ELEM_REPLACE = _IOWR('U', 0x18, struct sndrv_ctl_elem_info),
857 SNDRV_CTL_IOCTL_ELEM_REMOVE = _IOWR('U', 0x19, struct sndrv_ctl_elem_id),
858 SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE = _IOWR('U', 0x20, int),
859 SNDRV_CTL_IOCTL_HWDEP_INFO = _IOR('U', 0x21, struct sndrv_hwdep_info),
860 SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE = _IOR('U', 0x30, int),
861 SNDRV_CTL_IOCTL_PCM_INFO = _IOWR('U', 0x31, struct sndrv_pcm_info),
862 SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE = _IOW('U', 0x32, int),
863 SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE = _IOWR('U', 0x40, int),
864 SNDRV_CTL_IOCTL_RAWMIDI_INFO = _IOWR('U', 0x41, struct sndrv_rawmidi_info),
865 SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE = _IOW('U', 0x42, int),
866 SNDRV_CTL_IOCTL_POWER = _IOWR('U', 0xd0, int),
867 SNDRV_CTL_IOCTL_POWER_STATE = _IOR('U', 0xd1, int),
868};
869
870/*
871 * Read interface.
872 */
873
874enum sndrv_ctl_event_type {
875 SNDRV_CTL_EVENT_ELEM = 0,
876 SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM,
877};
878
879#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0) /* element value was changed */
880#define SNDRV_CTL_EVENT_MASK_INFO (1<<1) /* element info was changed */
881#define SNDRV_CTL_EVENT_MASK_ADD (1<<2) /* element was added */
882#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U) /* element was removed */
883
884struct sndrv_ctl_event {
885 enum sndrv_ctl_event_type type; /* event type - SNDRV_CTL_EVENT_* */
886 union {
887 struct {
888 unsigned int mask;
889 struct sndrv_ctl_elem_id id;
890 } elem;
891 unsigned char data8[60];
892 } data;
893};
894
895/*
896 * Control names
897 */
898
899#define SNDRV_CTL_NAME_NONE ""
900#define SNDRV_CTL_NAME_PLAYBACK "Playback "
901#define SNDRV_CTL_NAME_CAPTURE "Capture "
902
903#define SNDRV_CTL_NAME_IEC958_NONE ""
904#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch"
905#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume"
906#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default"
907#define SNDRV_CTL_NAME_IEC958_MASK "Mask"
908#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask"
909#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask"
910#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream"
911#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what
912
913/*
914 *
915 */
916
917struct sndrv_xferv {
918 const struct iovec *vector;
919 unsigned long count;
920};
921
922enum {
923 SNDRV_IOCTL_READV = _IOW('K', 0x00, struct sndrv_xferv),
924 SNDRV_IOCTL_WRITEV = _IOW('K', 0x01, struct sndrv_xferv),
925};
926
927#endif /* __SOUND_ASOUND_H */
diff --git a/include/sound/asound_fm.h b/include/sound/asound_fm.h
new file mode 100644
index 000000000000..b0da677f8f75
--- /dev/null
+++ b/include/sound/asound_fm.h
@@ -0,0 +1,115 @@
1#ifndef __SOUND_ASOUND_FM_H
2#define __SOUND_ASOUND_FM_H
3
4/*
5 * Advanced Linux Sound Architecture - ALSA
6 *
7 * Interface file between ALSA driver & user space
8 * Copyright (c) 1994-98 by Jaroslav Kysela <perex@suse.cz>,
9 * 4Front Technologies
10 *
11 * Direct FM control
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29#define SNDRV_DM_FM_MODE_OPL2 0x00
30#define SNDRV_DM_FM_MODE_OPL3 0x01
31
32typedef struct snd_dm_fm_info {
33 unsigned char fm_mode; /* OPL mode, see SNDRV_DM_FM_MODE_XXX */
34 unsigned char rhythm; /* percussion mode flag */
35} snd_dm_fm_info_t;
36
37/*
38 * Data structure composing an FM "note" or sound event.
39 */
40
41typedef struct snd_dm_fm_voice {
42 unsigned char op; /* operator cell (0 or 1) */
43 unsigned char voice; /* FM voice (0 to 17) */
44
45 unsigned char am; /* amplitude modulation */
46 unsigned char vibrato; /* vibrato effect */
47 unsigned char do_sustain; /* sustain phase */
48 unsigned char kbd_scale; /* keyboard scaling */
49 unsigned char harmonic; /* 4 bits: harmonic and multiplier */
50 unsigned char scale_level; /* 2 bits: decrease output freq rises */
51 unsigned char volume; /* 6 bits: volume */
52
53 unsigned char attack; /* 4 bits: attack rate */
54 unsigned char decay; /* 4 bits: decay rate */
55 unsigned char sustain; /* 4 bits: sustain level */
56 unsigned char release; /* 4 bits: release rate */
57
58 unsigned char feedback; /* 3 bits: feedback for op0 */
59 unsigned char connection; /* 0 for serial, 1 for parallel */
60 unsigned char left; /* stereo left */
61 unsigned char right; /* stereo right */
62 unsigned char waveform; /* 3 bits: waveform shape */
63} snd_dm_fm_voice_t;
64
65/*
66 * This describes an FM note by its voice, octave, frequency number (10bit)
67 * and key on/off.
68 */
69
70typedef struct snd_dm_fm_note {
71 unsigned char voice; /* 0-17 voice channel */
72 unsigned char octave; /* 3 bits: what octave to play */
73 unsigned int fnum; /* 10 bits: frequency number */
74 unsigned char key_on; /* set for active, clear for silent */
75} snd_dm_fm_note_t;
76
77/*
78 * FM parameters that apply globally to all voices, and thus are not "notes"
79 */
80
81typedef struct snd_dm_fm_params {
82 unsigned char am_depth; /* amplitude modulation depth (1=hi) */
83 unsigned char vib_depth; /* vibrato depth (1=hi) */
84 unsigned char kbd_split; /* keyboard split */
85 unsigned char rhythm; /* percussion mode select */
86
87 /* This block is the percussion instrument data */
88 unsigned char bass;
89 unsigned char snare;
90 unsigned char tomtom;
91 unsigned char cymbal;
92 unsigned char hihat;
93} snd_dm_fm_params_t;
94
95/*
96 * FM mode ioctl settings
97 */
98
99#define SNDRV_DM_FM_IOCTL_INFO _IOR('H', 0x20, snd_dm_fm_info_t)
100#define SNDRV_DM_FM_IOCTL_RESET _IO ('H', 0x21)
101#define SNDRV_DM_FM_IOCTL_PLAY_NOTE _IOW('H', 0x22, snd_dm_fm_note_t)
102#define SNDRV_DM_FM_IOCTL_SET_VOICE _IOW('H', 0x23, snd_dm_fm_voice_t)
103#define SNDRV_DM_FM_IOCTL_SET_PARAMS _IOW('H', 0x24, snd_dm_fm_params_t)
104#define SNDRV_DM_FM_IOCTL_SET_MODE _IOW('H', 0x25, int)
105/* for OPL3 only */
106#define SNDRV_DM_FM_IOCTL_SET_CONNECTION _IOW('H', 0x26, int)
107
108#define SNDRV_DM_FM_OSS_IOCTL_RESET 0x20
109#define SNDRV_DM_FM_OSS_IOCTL_PLAY_NOTE 0x21
110#define SNDRV_DM_FM_OSS_IOCTL_SET_VOICE 0x22
111#define SNDRV_DM_FM_OSS_IOCTL_SET_PARAMS 0x23
112#define SNDRV_DM_FM_OSS_IOCTL_SET_MODE 0x24
113#define SNDRV_DM_FM_OSS_IOCTL_SET_OPL 0x25
114
115#endif /* __SOUND_ASOUND_FM_H */
diff --git a/include/sound/asoundef.h b/include/sound/asoundef.h
new file mode 100644
index 000000000000..58c9ef3d1825
--- /dev/null
+++ b/include/sound/asoundef.h
@@ -0,0 +1,227 @@
1#ifndef __SOUND_ASOUNDEF_H
2#define __SOUND_ASOUNDEF_H
3
4/*
5 * Advanced Linux Sound Architecture - ALSA - Driver
6 * Copyright (c) 1994-2000 by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25/****************************************************************************
26 * *
27 * Digital audio interface *
28 * *
29 ****************************************************************************/
30
31/* AES/IEC958 channel status bits */
32#define IEC958_AES0_PROFESSIONAL (1<<0) /* 0 = consumer, 1 = professional */
33#define IEC958_AES0_NONAUDIO (1<<1) /* 0 = audio, 1 = non-audio */
34#define IEC958_AES0_PRO_EMPHASIS (7<<2) /* mask - emphasis */
35#define IEC958_AES0_PRO_EMPHASIS_NOTID (0<<2) /* emphasis not indicated */
36#define IEC958_AES0_PRO_EMPHASIS_NONE (1<<2) /* none emphasis */
37#define IEC958_AES0_PRO_EMPHASIS_5015 (3<<2) /* 50/15us emphasis */
38#define IEC958_AES0_PRO_EMPHASIS_CCITT (7<<2) /* CCITT J.17 emphasis */
39#define IEC958_AES0_PRO_FREQ_UNLOCKED (1<<5) /* source sample frequency: 0 = locked, 1 = unlocked */
40#define IEC958_AES0_PRO_FS (3<<6) /* mask - sample frequency */
41#define IEC958_AES0_PRO_FS_NOTID (0<<6) /* fs not indicated */
42#define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
43#define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
44#define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
45#define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */
46#define IEC958_AES0_CON_EMPHASIS (7<<3) /* mask - emphasis */
47#define IEC958_AES0_CON_EMPHASIS_NONE (0<<3) /* none emphasis */
48#define IEC958_AES0_CON_EMPHASIS_5015 (1<<3) /* 50/15us emphasis */
49#define IEC958_AES0_CON_MODE (3<<6) /* mask - mode */
50#define IEC958_AES1_PRO_MODE (15<<0) /* mask - channel mode */
51#define IEC958_AES1_PRO_MODE_NOTID (0<<0) /* not indicated */
52#define IEC958_AES1_PRO_MODE_STEREOPHONIC (2<<0) /* stereophonic - ch A is left */
53#define IEC958_AES1_PRO_MODE_SINGLE (4<<0) /* single channel */
54#define IEC958_AES1_PRO_MODE_TWO (8<<0) /* two channels */
55#define IEC958_AES1_PRO_MODE_PRIMARY (12<<0) /* primary/secondary */
56#define IEC958_AES1_PRO_MODE_BYTE3 (15<<0) /* vector to byte 3 */
57#define IEC958_AES1_PRO_USERBITS (15<<4) /* mask - user bits */
58#define IEC958_AES1_PRO_USERBITS_NOTID (0<<4) /* not indicated */
59#define IEC958_AES1_PRO_USERBITS_192 (8<<4) /* 192-bit structure */
60#define IEC958_AES1_PRO_USERBITS_UDEF (12<<4) /* user defined application */
61#define IEC958_AES1_CON_CATEGORY 0x7f
62#define IEC958_AES1_CON_GENERAL 0x00
63#define IEC958_AES1_CON_EXPERIMENTAL 0x40
64#define IEC958_AES1_CON_SOLIDMEM_MASK 0x0f
65#define IEC958_AES1_CON_SOLIDMEM_ID 0x08
66#define IEC958_AES1_CON_BROADCAST1_MASK 0x07
67#define IEC958_AES1_CON_BROADCAST1_ID 0x04
68#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07
69#define IEC958_AES1_CON_DIGDIGCONV_ID 0x02
70#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f
71#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x06
72#define IEC958_AES1_CON_ADC_MASK 0x1f
73#define IEC958_AES1_CON_ADC_ID 0x16
74#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f
75#define IEC958_AES1_CON_BROADCAST2_ID 0x0e
76#define IEC958_AES1_CON_LASEROPT_MASK 0x07
77#define IEC958_AES1_CON_LASEROPT_ID 0x01
78#define IEC958_AES1_CON_MUSICAL_MASK 0x07
79#define IEC958_AES1_CON_MUSICAL_ID 0x05
80#define IEC958_AES1_CON_MAGNETIC_MASK 0x07
81#define IEC958_AES1_CON_MAGNETIC_ID 0x03
82#define IEC958_AES1_CON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x00)
83#define IEC958_AES1_CON_NON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x08)
84#define IEC958_AES1_CON_PCM_CODER (IEC958_AES1_CON_DIGDIGCONV_ID|0x00)
85#define IEC958_AES1_CON_SAMPLER (IEC958_AES1_CON_DIGDIGCONV_ID|0x20)
86#define IEC958_AES1_CON_MIXER (IEC958_AES1_CON_DIGDIGCONV_ID|0x10)
87#define IEC958_AES1_CON_RATE_CONVERTER (IEC958_AES1_CON_DIGDIGCONV_ID|0x18)
88#define IEC958_AES1_CON_SYNTHESIZER (IEC958_AES1_CON_MUSICAL_ID|0x00)
89#define IEC958_AES1_CON_MICROPHONE (IEC958_AES1_CON_MUSICAL_ID|0x08)
90#define IEC958_AES1_CON_DAT (IEC958_AES1_CON_MAGNETIC_ID|0x00)
91#define IEC958_AES1_CON_VCR (IEC958_AES1_CON_MAGNETIC_ID|0x08)
92#define IEC958_AES1_CON_ORIGINAL (1<<7) /* this bits depends on the category code */
93#define IEC958_AES2_PRO_SBITS (7<<0) /* mask - sample bits */
94#define IEC958_AES2_PRO_SBITS_20 (2<<0) /* 20-bit - coordination */
95#define IEC958_AES2_PRO_SBITS_24 (4<<0) /* 24-bit - main audio */
96#define IEC958_AES2_PRO_SBITS_UDEF (6<<0) /* user defined application */
97#define IEC958_AES2_PRO_WORDLEN (7<<3) /* mask - source word length */
98#define IEC958_AES2_PRO_WORDLEN_NOTID (0<<3) /* not indicated */
99#define IEC958_AES2_PRO_WORDLEN_22_18 (2<<3) /* 22-bit or 18-bit */
100#define IEC958_AES2_PRO_WORDLEN_23_19 (4<<3) /* 23-bit or 19-bit */
101#define IEC958_AES2_PRO_WORDLEN_24_20 (5<<3) /* 24-bit or 20-bit */
102#define IEC958_AES2_PRO_WORDLEN_20_16 (6<<3) /* 20-bit or 16-bit */
103#define IEC958_AES2_CON_SOURCE (15<<0) /* mask - source number */
104#define IEC958_AES2_CON_SOURCE_UNSPEC (0<<0) /* unspecified */
105#define IEC958_AES2_CON_CHANNEL (15<<4) /* mask - channel number */
106#define IEC958_AES2_CON_CHANNEL_UNSPEC (0<<4) /* unspecified */
107#define IEC958_AES3_CON_FS (15<<0) /* mask - sample frequency */
108#define IEC958_AES3_CON_FS_44100 (0<<0) /* 44.1kHz */
109#define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */
110#define IEC958_AES3_CON_FS_32000 (3<<0) /* 32kHz */
111#define IEC958_AES3_CON_CLOCK (3<<4) /* mask - clock accuracy */
112#define IEC958_AES3_CON_CLOCK_1000PPM (0<<4) /* 1000 ppm */
113#define IEC958_AES3_CON_CLOCK_50PPM (1<<4) /* 50 ppm */
114#define IEC958_AES3_CON_CLOCK_VARIABLE (2<<4) /* variable pitch */
115
116/*****************************************************************************
117 * *
118 * MIDI v1.0 interface *
119 * *
120 *****************************************************************************/
121
122#define MIDI_CHANNELS 16
123#define MIDI_GM_DRUM_CHANNEL (10-1)
124
125/*
126 * MIDI commands
127 */
128
129#define MIDI_CMD_NOTE_OFF 0x80
130#define MIDI_CMD_NOTE_ON 0x90
131#define MIDI_CMD_NOTE_PRESSURE 0xa0
132#define MIDI_CMD_CONTROL 0xb0
133#define MIDI_CMD_PGM_CHANGE 0xc0
134#define MIDI_CMD_CHANNEL_PRESSURE 0xd0
135#define MIDI_CMD_BENDER 0xe0
136
137#define MIDI_CMD_COMMON_SYSEX 0xf0
138#define MIDI_CMD_COMMON_MTC_QUARTER 0xf1
139#define MIDI_CMD_COMMON_SONG_POS 0xf2
140#define MIDI_CMD_COMMON_SONG_SELECT 0xf3
141#define MIDI_CMD_COMMON_TUNE_REQUEST 0xf6
142#define MIDI_CMD_COMMON_SYSEX_END 0xf7
143#define MIDI_CMD_COMMON_CLOCK 0xf8
144#define MIDI_CMD_COMMON_START 0xfa
145#define MIDI_CMD_COMMON_CONTINUE 0xfb
146#define MIDI_CMD_COMMON_STOP 0xfc
147#define MIDI_CMD_COMMON_SENSING 0xfe
148#define MIDI_CMD_COMMON_RESET 0xff
149
150/*
151 * MIDI controllers
152 */
153
154#define MIDI_CTL_MSB_BANK 0x00
155#define MIDI_CTL_MSB_MODWHEEL 0x01
156#define MIDI_CTL_MSB_BREATH 0x02
157#define MIDI_CTL_MSB_FOOT 0x04
158#define MIDI_CTL_MSB_PORTAMENTO_TIME 0x05
159#define MIDI_CTL_MSB_DATA_ENTRY 0x06
160#define MIDI_CTL_MSB_MAIN_VOLUME 0x07
161#define MIDI_CTL_MSB_BALANCE 0x08
162#define MIDI_CTL_MSB_PAN 0x0a
163#define MIDI_CTL_MSB_EXPRESSION 0x0b
164#define MIDI_CTL_MSB_EFFECT1 0x0c
165#define MIDI_CTL_MSB_EFFECT2 0x0d
166#define MIDI_CTL_MSB_GENERAL_PURPOSE1 0x10
167#define MIDI_CTL_MSB_GENERAL_PURPOSE2 0x11
168#define MIDI_CTL_MSB_GENERAL_PURPOSE3 0x12
169#define MIDI_CTL_MSB_GENERAL_PURPOSE4 0x13
170#define MIDI_CTL_LSB_BANK 0x20
171#define MIDI_CTL_LSB_MODWHEEL 0x21
172#define MIDI_CTL_LSB_BREATH 0x22
173#define MIDI_CTL_LSB_FOOT 0x24
174#define MIDI_CTL_LSB_PORTAMENTO_TIME 0x25
175#define MIDI_CTL_LSB_DATA_ENTRY 0x26
176#define MIDI_CTL_LSB_MAIN_VOLUME 0x27
177#define MIDI_CTL_LSB_BALANCE 0x28
178#define MIDI_CTL_LSB_PAN 0x2a
179#define MIDI_CTL_LSB_EXPRESSION 0x2b
180#define MIDI_CTL_LSB_EFFECT1 0x2c
181#define MIDI_CTL_LSB_EFFECT2 0x2d
182#define MIDI_CTL_LSB_GENERAL_PURPOSE1 0x30
183#define MIDI_CTL_LSB_GENERAL_PURPOSE2 0x31
184#define MIDI_CTL_LSB_GENERAL_PURPOSE3 0x32
185#define MIDI_CTL_LSB_GENERAL_PURPOSE4 0x33
186#define MIDI_CTL_SUSTAIN 0x40
187#define MIDI_CTL_PORTAMENTO 0x41
188#define MIDI_CTL_SOSTENUTO 0x42
189#define MIDI_CTL_SOFT_PEDAL 0x43
190#define MIDI_CTL_LEGATO_FOOTSWITCH 0x44
191#define MIDI_CTL_HOLD2 0x45
192#define MIDI_CTL_SC1_SOUND_VARIATION 0x46
193#define MIDI_CTL_SC2_TIMBRE 0x47
194#define MIDI_CTL_SC3_RELEASE_TIME 0x48
195#define MIDI_CTL_SC4_ATTACK_TIME 0x49
196#define MIDI_CTL_SC5_BRIGHTNESS 0x4a
197#define MIDI_CTL_SC6 0x4b
198#define MIDI_CTL_SC7 0x4c
199#define MIDI_CTL_SC8 0x4d
200#define MIDI_CTL_SC9 0x4e
201#define MIDI_CTL_SC10 0x4f
202#define MIDI_CTL_GENERAL_PURPOSE5 0x50
203#define MIDI_CTL_GENERAL_PURPOSE6 0x51
204#define MIDI_CTL_GENERAL_PURPOSE7 0x52
205#define MIDI_CTL_GENERAL_PURPOSE8 0x53
206#define MIDI_CTL_PORTAMENTO_CONTROL 0x54
207#define MIDI_CTL_E1_REVERB_DEPTH 0x5b
208#define MIDI_CTL_E2_TREMOLO_DEPTH 0x5c
209#define MIDI_CTL_E3_CHORUS_DEPTH 0x5d
210#define MIDI_CTL_E4_DETUNE_DEPTH 0x5e
211#define MIDI_CTL_E5_PHASER_DEPTH 0x5f
212#define MIDI_CTL_DATA_INCREMENT 0x60
213#define MIDI_CTL_DATA_DECREMENT 0x61
214#define MIDI_CTL_NONREG_PARM_NUM_LSB 0x62
215#define MIDI_CTL_NONREG_PARM_NUM_MSB 0x63
216#define MIDI_CTL_REGIST_PARM_NUM_LSB 0x64
217#define MIDI_CTL_REGIST_PARM_NUM_MSB 0x65
218#define MIDI_CTL_ALL_SOUNDS_OFF 0x78
219#define MIDI_CTL_RESET_CONTROLLERS 0x79
220#define MIDI_CTL_LOCAL_CONTROL_SWITCH 0x7a
221#define MIDI_CTL_ALL_NOTES_OFF 0x7b
222#define MIDI_CTL_OMNI_OFF 0x7c
223#define MIDI_CTL_OMNI_ON 0x7d
224#define MIDI_CTL_MONO1 0x7e
225#define MIDI_CTL_MONO2 0x7f
226
227#endif /* __SOUND_ASOUNDEF_H */
diff --git a/include/sound/control.h b/include/sound/control.h
new file mode 100644
index 000000000000..7b9444cd02f4
--- /dev/null
+++ b/include/sound/control.h
@@ -0,0 +1,162 @@
1#ifndef __SOUND_CONTROL_H
2#define __SOUND_CONTROL_H
3
4/*
5 * Header file for control interface
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <sound/asound.h>
26
27typedef struct sndrv_aes_iec958 snd_aes_iec958_t;
28typedef struct sndrv_ctl_card_info snd_ctl_card_info_t;
29typedef enum sndrv_ctl_elem_type snd_ctl_elem_type_t;
30typedef enum sndrv_ctl_elem_iface snd_ctl_elem_iface_t;
31typedef struct sndrv_ctl_elem_id snd_ctl_elem_id_t;
32typedef struct sndrv_ctl_elem_list snd_ctl_elem_list_t;
33typedef struct sndrv_ctl_elem_info snd_ctl_elem_info_t;
34typedef struct sndrv_ctl_elem_value snd_ctl_elem_value_t;
35typedef enum sndrv_ctl_event_type snd_ctl_event_type_t;
36typedef struct sndrv_ctl_event snd_ctl_event_t;
37
38#define snd_kcontrol_chip(kcontrol) ((kcontrol)->private_data)
39
40typedef int (snd_kcontrol_info_t) (snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo);
41typedef int (snd_kcontrol_get_t) (snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
42typedef int (snd_kcontrol_put_t) (snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
43
44typedef struct _snd_kcontrol_new {
45 snd_ctl_elem_iface_t iface; /* interface identifier */
46 unsigned int device; /* device/client number */
47 unsigned int subdevice; /* subdevice (substream) number */
48 unsigned char *name; /* ASCII name of item */
49 unsigned int index; /* index of item */
50 unsigned int access; /* access rights */
51 unsigned int count; /* count of same elements */
52 snd_kcontrol_info_t *info;
53 snd_kcontrol_get_t *get;
54 snd_kcontrol_put_t *put;
55 unsigned long private_value;
56} snd_kcontrol_new_t;
57
58typedef struct _snd_kcontrol_volatile {
59 snd_ctl_file_t *owner; /* locked */
60 pid_t owner_pid;
61 unsigned int access; /* access rights */
62} snd_kcontrol_volatile_t;
63
64struct _snd_kcontrol {
65 struct list_head list; /* list of controls */
66 snd_ctl_elem_id_t id;
67 unsigned int count; /* count of same elements */
68 snd_kcontrol_info_t *info;
69 snd_kcontrol_get_t *get;
70 snd_kcontrol_put_t *put;
71 unsigned long private_value;
72 void *private_data;
73 void (*private_free)(snd_kcontrol_t *kcontrol);
74 snd_kcontrol_volatile_t vd[0]; /* volatile data */
75};
76
77#define snd_kcontrol(n) list_entry(n, snd_kcontrol_t, list)
78
79typedef struct _snd_kctl_event {
80 struct list_head list; /* list of events */
81 snd_ctl_elem_id_t id;
82 unsigned int mask;
83} snd_kctl_event_t;
84
85#define snd_kctl_event(n) list_entry(n, snd_kctl_event_t, list)
86
87struct _snd_ctl_file {
88 struct list_head list; /* list of all control files */
89 snd_card_t *card;
90 pid_t pid;
91 int prefer_pcm_subdevice;
92 int prefer_rawmidi_subdevice;
93 wait_queue_head_t change_sleep;
94 spinlock_t read_lock;
95 struct fasync_struct *fasync;
96 int subscribed; /* read interface is activated */
97 struct list_head events; /* waiting events for read */
98};
99
100#define snd_ctl_file(n) list_entry(n, snd_ctl_file_t, list)
101
102typedef int (*snd_kctl_ioctl_func_t) (snd_card_t * card,
103 snd_ctl_file_t * control,
104 unsigned int cmd, unsigned long arg);
105
106void snd_ctl_notify(snd_card_t * card, unsigned int mask, snd_ctl_elem_id_t * id);
107
108snd_kcontrol_t *snd_ctl_new(snd_kcontrol_t * kcontrol, unsigned int access);
109snd_kcontrol_t *snd_ctl_new1(snd_kcontrol_new_t * kcontrolnew, void * private_data);
110void snd_ctl_free_one(snd_kcontrol_t * kcontrol);
111int snd_ctl_add(snd_card_t * card, snd_kcontrol_t * kcontrol);
112int snd_ctl_remove(snd_card_t * card, snd_kcontrol_t * kcontrol);
113int snd_ctl_remove_id(snd_card_t * card, snd_ctl_elem_id_t *id);
114int snd_ctl_rename_id(snd_card_t * card, snd_ctl_elem_id_t *src_id, snd_ctl_elem_id_t *dst_id);
115snd_kcontrol_t *snd_ctl_find_numid(snd_card_t * card, unsigned int numid);
116snd_kcontrol_t *snd_ctl_find_id(snd_card_t * card, snd_ctl_elem_id_t *id);
117
118int snd_ctl_create(snd_card_t *card);
119
120int snd_ctl_register_ioctl(snd_kctl_ioctl_func_t fcn);
121int snd_ctl_unregister_ioctl(snd_kctl_ioctl_func_t fcn);
122#ifdef CONFIG_COMPAT
123int snd_ctl_register_ioctl_compat(snd_kctl_ioctl_func_t fcn);
124int snd_ctl_unregister_ioctl_compat(snd_kctl_ioctl_func_t fcn);
125#else
126#define snd_ctl_register_ioctl_compat(fcn)
127#define snd_ctl_unregister_ioctl_compat(fcn)
128#endif
129
130int snd_ctl_elem_read(snd_card_t *card, snd_ctl_elem_value_t *control);
131int snd_ctl_elem_write(snd_card_t *card, snd_ctl_file_t *file, snd_ctl_elem_value_t *control);
132
133static inline unsigned int snd_ctl_get_ioffnum(snd_kcontrol_t *kctl, snd_ctl_elem_id_t *id)
134{
135 return id->numid - kctl->id.numid;
136}
137
138static inline unsigned int snd_ctl_get_ioffidx(snd_kcontrol_t *kctl, snd_ctl_elem_id_t *id)
139{
140 return id->index - kctl->id.index;
141}
142
143static inline unsigned int snd_ctl_get_ioff(snd_kcontrol_t *kctl, snd_ctl_elem_id_t *id)
144{
145 if (id->numid) {
146 return snd_ctl_get_ioffnum(kctl, id);
147 } else {
148 return snd_ctl_get_ioffidx(kctl, id);
149 }
150}
151
152static inline snd_ctl_elem_id_t *snd_ctl_build_ioff(snd_ctl_elem_id_t *dst_id,
153 snd_kcontrol_t *src_kctl,
154 unsigned int offset)
155{
156 *dst_id = src_kctl->id;
157 dst_id->index += offset;
158 dst_id->numid += offset;
159 return dst_id;
160}
161
162#endif /* __SOUND_CONTROL_H */
diff --git a/include/sound/core.h b/include/sound/core.h
new file mode 100644
index 000000000000..9117c23e3a01
--- /dev/null
+++ b/include/sound/core.h
@@ -0,0 +1,502 @@
1#ifndef __SOUND_CORE_H
2#define __SOUND_CORE_H
3
4/*
5 * Main header file for the ALSA driver
6 * Copyright (c) 1994-2001 by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/sched.h> /* wake_up() */
26#include <asm/semaphore.h> /* struct semaphore */
27#include <linux/rwsem.h> /* struct rw_semaphore */
28#include <linux/workqueue.h> /* struct workqueue_struct */
29#include <linux/pm.h> /* pm_message_t */
30
31/* Typedef's */
32typedef struct timespec snd_timestamp_t;
33typedef struct sndrv_interval snd_interval_t;
34typedef enum sndrv_card_type snd_card_type;
35typedef struct sndrv_xferi snd_xferi_t;
36typedef struct sndrv_xfern snd_xfern_t;
37typedef struct sndrv_xferv snd_xferv_t;
38
39/* forward declarations */
40#ifdef CONFIG_PCI
41struct pci_dev;
42#endif
43#ifdef CONFIG_SBUS
44struct sbus_dev;
45#endif
46
47/* device allocation stuff */
48
49#define SNDRV_DEV_TYPE_RANGE_SIZE 0x1000
50
51typedef enum {
52 SNDRV_DEV_TOPLEVEL = (0*SNDRV_DEV_TYPE_RANGE_SIZE),
53 SNDRV_DEV_CONTROL,
54 SNDRV_DEV_LOWLEVEL_PRE,
55 SNDRV_DEV_LOWLEVEL_NORMAL = (1*SNDRV_DEV_TYPE_RANGE_SIZE),
56 SNDRV_DEV_PCM,
57 SNDRV_DEV_RAWMIDI,
58 SNDRV_DEV_TIMER,
59 SNDRV_DEV_SEQUENCER,
60 SNDRV_DEV_HWDEP,
61 SNDRV_DEV_INFO,
62 SNDRV_DEV_BUS,
63 SNDRV_DEV_CODEC,
64 SNDRV_DEV_LOWLEVEL = (2*SNDRV_DEV_TYPE_RANGE_SIZE)
65} snd_device_type_t;
66
67typedef enum {
68 SNDRV_DEV_BUILD,
69 SNDRV_DEV_REGISTERED,
70 SNDRV_DEV_DISCONNECTED
71} snd_device_state_t;
72
73typedef enum {
74 SNDRV_DEV_CMD_PRE = 0,
75 SNDRV_DEV_CMD_NORMAL = 1,
76 SNDRV_DEV_CMD_POST = 2
77} snd_device_cmd_t;
78
79typedef struct _snd_card snd_card_t;
80typedef struct _snd_device snd_device_t;
81
82typedef int (snd_dev_free_t)(snd_device_t *device);
83typedef int (snd_dev_register_t)(snd_device_t *device);
84typedef int (snd_dev_disconnect_t)(snd_device_t *device);
85typedef int (snd_dev_unregister_t)(snd_device_t *device);
86
87typedef struct {
88 snd_dev_free_t *dev_free;
89 snd_dev_register_t *dev_register;
90 snd_dev_disconnect_t *dev_disconnect;
91 snd_dev_unregister_t *dev_unregister;
92} snd_device_ops_t;
93
94struct _snd_device {
95 struct list_head list; /* list of registered devices */
96 snd_card_t *card; /* card which holds this device */
97 snd_device_state_t state; /* state of the device */
98 snd_device_type_t type; /* device type */
99 void *device_data; /* device structure */
100 snd_device_ops_t *ops; /* operations */
101};
102
103#define snd_device(n) list_entry(n, snd_device_t, list)
104
105/* various typedefs */
106
107typedef struct snd_info_entry snd_info_entry_t;
108typedef struct _snd_pcm snd_pcm_t;
109typedef struct _snd_pcm_str snd_pcm_str_t;
110typedef struct _snd_pcm_substream snd_pcm_substream_t;
111typedef struct _snd_mixer snd_kmixer_t;
112typedef struct _snd_rawmidi snd_rawmidi_t;
113typedef struct _snd_ctl_file snd_ctl_file_t;
114typedef struct _snd_kcontrol snd_kcontrol_t;
115typedef struct _snd_timer snd_timer_t;
116typedef struct _snd_timer_instance snd_timer_instance_t;
117typedef struct _snd_hwdep snd_hwdep_t;
118#if defined(CONFIG_SND_MIXER_OSS) || defined(CONFIG_SND_MIXER_OSS_MODULE)
119typedef struct _snd_oss_mixer snd_mixer_oss_t;
120#endif
121
122/* monitor files for graceful shutdown (hotplug) */
123
124struct snd_monitor_file {
125 struct file *file;
126 struct snd_monitor_file *next;
127};
128
129struct snd_shutdown_f_ops; /* define it later */
130
131/* main structure for soundcard */
132
133struct _snd_card {
134 int number; /* number of soundcard (index to snd_cards) */
135
136 char id[16]; /* id string of this card */
137 char driver[16]; /* driver name */
138 char shortname[32]; /* short name of this soundcard */
139 char longname[80]; /* name of this soundcard */
140 char mixername[80]; /* mixer name */
141 char components[80]; /* card components delimited with space */
142
143 struct module *module; /* top-level module */
144
145 void *private_data; /* private data for soundcard */
146 void (*private_free) (snd_card_t *card); /* callback for freeing of private data */
147
148 struct list_head devices; /* devices */
149
150 unsigned int last_numid; /* last used numeric ID */
151 struct rw_semaphore controls_rwsem; /* controls list lock */
152 rwlock_t ctl_files_rwlock; /* ctl_files list lock */
153 int controls_count; /* count of all controls */
154 int user_ctl_count; /* count of all user controls */
155 struct list_head controls; /* all controls for this card */
156 struct list_head ctl_files; /* active control files */
157
158 snd_info_entry_t *proc_root; /* root for soundcard specific files */
159 snd_info_entry_t *proc_id; /* the card id */
160 struct proc_dir_entry *proc_root_link; /* number link to real id */
161
162 struct snd_monitor_file *files; /* all files associated to this card */
163 struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown state */
164 spinlock_t files_lock; /* lock the files for this card */
165 int shutdown; /* this card is going down */
166 wait_queue_head_t shutdown_sleep;
167 struct work_struct free_workq; /* for free in workqueue */
168 struct device *dev;
169
170#ifdef CONFIG_PM
171 int (*pm_suspend)(snd_card_t *card, pm_message_t state);
172 int (*pm_resume)(snd_card_t *card);
173 void *pm_private_data;
174 unsigned int power_state; /* power state */
175 struct semaphore power_lock; /* power lock */
176 wait_queue_head_t power_sleep;
177#ifdef CONFIG_SND_GENERIC_PM
178 struct snd_generic_device *pm_dev; /* for ISA */
179#endif
180#endif
181
182#if defined(CONFIG_SND_MIXER_OSS) || defined(CONFIG_SND_MIXER_OSS_MODULE)
183 snd_mixer_oss_t *mixer_oss;
184 int mixer_oss_change_count;
185#endif
186};
187
188#ifdef CONFIG_PM
189static inline void snd_power_lock(snd_card_t *card)
190{
191 down(&card->power_lock);
192}
193
194static inline void snd_power_unlock(snd_card_t *card)
195{
196 up(&card->power_lock);
197}
198
199int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file);
200
201static inline unsigned int snd_power_get_state(snd_card_t *card)
202{
203 return card->power_state;
204}
205
206static inline void snd_power_change_state(snd_card_t *card, unsigned int state)
207{
208 card->power_state = state;
209 wake_up(&card->power_sleep);
210}
211int snd_card_set_pm_callback(snd_card_t *card,
212 int (*suspend)(snd_card_t *, pm_message_t),
213 int (*resume)(snd_card_t *),
214 void *private_data);
215int snd_card_set_generic_pm_callback(snd_card_t *card,
216 int (*suspend)(snd_card_t *, pm_message_t),
217 int (*resume)(snd_card_t *),
218 void *private_data);
219#define snd_card_set_isa_pm_callback(card,suspend,resume,data) \
220 snd_card_set_generic_pm_callback(card, suspend, resume, data)
221struct pci_dev;
222int snd_card_pci_suspend(struct pci_dev *dev, pm_message_t state);
223int snd_card_pci_resume(struct pci_dev *dev);
224#define SND_PCI_PM_CALLBACKS \
225 .suspend = snd_card_pci_suspend, .resume = snd_card_pci_resume
226
227#else /* ! CONFIG_PM */
228
229#define snd_power_lock(card) do { (void)(card); } while (0)
230#define snd_power_unlock(card) do { (void)(card); } while (0)
231static inline int snd_power_wait(snd_card_t *card, unsigned int state, struct file *file) { return 0; }
232#define snd_power_get_state(card) SNDRV_CTL_POWER_D0
233#define snd_power_change_state(card, state) do { (void)(card); } while (0)
234#define snd_card_set_pm_callback(card,suspend,resume,data)
235#define snd_card_set_generic_pm_callback(card,suspend,resume,data)
236#define snd_card_set_isa_pm_callback(card,suspend,resume,data)
237#define SND_PCI_PM_CALLBACKS
238
239#endif /* CONFIG_PM */
240
241/* device.c */
242
243struct _snd_minor {
244 struct list_head list; /* list of all minors per card */
245 int number; /* minor number */
246 int device; /* device number */
247 const char *comment; /* for /proc/asound/devices */
248 struct file_operations *f_ops; /* file operations */
249 char name[0]; /* device name (keep at the end of structure) */
250};
251
252typedef struct _snd_minor snd_minor_t;
253
254/* sound.c */
255
256extern int snd_ecards_limit;
257
258void snd_request_card(int card);
259
260int snd_register_device(int type, snd_card_t *card, int dev, snd_minor_t *reg, const char *name);
261int snd_unregister_device(int type, snd_card_t *card, int dev);
262
263#ifdef CONFIG_SND_OSSEMUL
264int snd_register_oss_device(int type, snd_card_t *card, int dev, snd_minor_t *reg, const char *name);
265int snd_unregister_oss_device(int type, snd_card_t *card, int dev);
266#endif
267
268int snd_minor_info_init(void);
269int snd_minor_info_done(void);
270
271/* sound_oss.c */
272
273#ifdef CONFIG_SND_OSSEMUL
274int snd_minor_info_oss_init(void);
275int snd_minor_info_oss_done(void);
276int snd_oss_init_module(void);
277#else
278#define snd_minor_info_oss_init() /*NOP*/
279#define snd_minor_info_oss_done() /*NOP*/
280#define snd_oss_init_module() 0
281#endif
282
283/* memory.c */
284
285#ifdef CONFIG_SND_DEBUG_MEMORY
286void snd_memory_init(void);
287void snd_memory_done(void);
288int snd_memory_info_init(void);
289int snd_memory_info_done(void);
290void *snd_hidden_kmalloc(size_t size, int flags);
291void *snd_hidden_kcalloc(size_t n, size_t size, int flags);
292void snd_hidden_kfree(const void *obj);
293void *snd_hidden_vmalloc(unsigned long size);
294void snd_hidden_vfree(void *obj);
295#define kmalloc(size, flags) snd_hidden_kmalloc(size, flags)
296#define kcalloc(n, size, flags) snd_hidden_kcalloc(n, size, flags)
297#define kfree(obj) snd_hidden_kfree(obj)
298#define vmalloc(size) snd_hidden_vmalloc(size)
299#define vfree(obj) snd_hidden_vfree(obj)
300#define kmalloc_nocheck(size, flags) snd_wrapper_kmalloc(size, flags)
301#define vmalloc_nocheck(size) snd_wrapper_vmalloc(size)
302#define kfree_nocheck(obj) snd_wrapper_kfree(obj)
303#define vfree_nocheck(obj) snd_wrapper_vfree(obj)
304#else
305#define snd_memory_init() /*NOP*/
306#define snd_memory_done() /*NOP*/
307#define snd_memory_info_init() /*NOP*/
308#define snd_memory_info_done() /*NOP*/
309#define kmalloc_nocheck(size, flags) kmalloc(size, flags)
310#define vmalloc_nocheck(size) vmalloc(size)
311#define kfree_nocheck(obj) kfree(obj)
312#define vfree_nocheck(obj) vfree(obj)
313#endif
314char *snd_kmalloc_strdup(const char *string, int flags);
315int copy_to_user_fromio(void __user *dst, const volatile void __iomem *src, size_t count);
316int copy_from_user_toio(volatile void __iomem *dst, const void __user *src, size_t count);
317
318/* init.c */
319
320extern unsigned int snd_cards_lock;
321extern snd_card_t *snd_cards[SNDRV_CARDS];
322extern rwlock_t snd_card_rwlock;
323#if defined(CONFIG_SND_MIXER_OSS) || defined(CONFIG_SND_MIXER_OSS_MODULE)
324#define SND_MIXER_OSS_NOTIFY_REGISTER 0
325#define SND_MIXER_OSS_NOTIFY_DISCONNECT 1
326#define SND_MIXER_OSS_NOTIFY_FREE 2
327extern int (*snd_mixer_oss_notify_callback)(snd_card_t *card, int cmd);
328#endif
329
330snd_card_t *snd_card_new(int idx, const char *id,
331 struct module *module, int extra_size);
332int snd_card_disconnect(snd_card_t *card);
333int snd_card_free(snd_card_t *card);
334int snd_card_free_in_thread(snd_card_t *card);
335int snd_card_register(snd_card_t *card);
336int snd_card_info_init(void);
337int snd_card_info_done(void);
338int snd_component_add(snd_card_t *card, const char *component);
339int snd_card_file_add(snd_card_t *card, struct file *file);
340int snd_card_file_remove(snd_card_t *card, struct file *file);
341
342#ifndef snd_card_set_dev
343#define snd_card_set_dev(card,devptr) ((card)->dev = (devptr))
344#endif
345
346/* device.c */
347
348int snd_device_new(snd_card_t *card, snd_device_type_t type,
349 void *device_data, snd_device_ops_t *ops);
350int snd_device_register(snd_card_t *card, void *device_data);
351int snd_device_register_all(snd_card_t *card);
352int snd_device_disconnect(snd_card_t *card, void *device_data);
353int snd_device_disconnect_all(snd_card_t *card);
354int snd_device_free(snd_card_t *card, void *device_data);
355int snd_device_free_all(snd_card_t *card, snd_device_cmd_t cmd);
356
357/* isadma.c */
358
359#define DMA_MODE_NO_ENABLE 0x0100
360
361void snd_dma_program(unsigned long dma, unsigned long addr, unsigned int size, unsigned short mode);
362void snd_dma_disable(unsigned long dma);
363unsigned int snd_dma_pointer(unsigned long dma, unsigned int size);
364
365/* misc.c */
366
367int snd_task_name(struct task_struct *task, char *name, size_t size);
368#ifdef CONFIG_SND_VERBOSE_PRINTK
369void snd_verbose_printk(const char *file, int line, const char *format, ...)
370 __attribute__ ((format (printf, 3, 4)));
371#endif
372#if defined(CONFIG_SND_DEBUG) && defined(CONFIG_SND_VERBOSE_PRINTK)
373void snd_verbose_printd(const char *file, int line, const char *format, ...)
374 __attribute__ ((format (printf, 3, 4)));
375#endif
376
377/* --- */
378
379#ifdef CONFIG_SND_VERBOSE_PRINTK
380/**
381 * snd_printk - printk wrapper
382 * @fmt: format string
383 *
384 * Works like print() but prints the file and the line of the caller
385 * when configured with CONFIG_SND_VERBOSE_PRINTK.
386 */
387#define snd_printk(fmt, args...) \
388 snd_verbose_printk(__FILE__, __LINE__, fmt ,##args)
389#else
390#define snd_printk(fmt, args...) \
391 printk(fmt ,##args)
392#endif
393
394#ifdef CONFIG_SND_DEBUG
395
396#define __ASTRING__(x) #x
397
398#ifdef CONFIG_SND_VERBOSE_PRINTK
399/**
400 * snd_printd - debug printk
401 * @format: format string
402 *
403 * Compiled only when Works like snd_printk() for debugging purpose.
404 * Ignored when CONFIG_SND_DEBUG is not set.
405 */
406#define snd_printd(fmt, args...) \
407 snd_verbose_printd(__FILE__, __LINE__, fmt ,##args)
408#else
409#define snd_printd(fmt, args...) \
410 printk(fmt ,##args)
411#endif
412/**
413 * snd_assert - run-time assersion macro
414 * @expr: expression
415 * @args...: the action
416 *
417 * This macro checks the expression in run-time and invokes the commands
418 * given in the rest arguments if the assertion is failed.
419 * When CONFIG_SND_DEBUG is not set, the expression is executed but
420 * not checked.
421 */
422#define snd_assert(expr, args...) do {\
423 if (unlikely(!(expr))) { \
424 snd_printk(KERN_ERR "BUG? (%s) (called from %p)\n", __ASTRING__(expr), __builtin_return_address(0));\
425 args;\
426 }\
427} while (0)
428/**
429 * snd_runtime_check - run-time assersion macro
430 * @expr: expression
431 * @args...: the action
432 *
433 * This macro checks the expression in run-time and invokes the commands
434 * given in the rest arguments if the assertion is failed.
435 * Unlike snd_assert(), the action commands are executed even if
436 * CONFIG_SND_DEBUG is not set but without any error messages.
437 */
438#define snd_runtime_check(expr, args...) do {\
439 if (unlikely(!(expr))) { \
440 snd_printk(KERN_ERR "ERROR (%s) (called from %p)\n", __ASTRING__(expr), __builtin_return_address(0));\
441 args;\
442 }\
443} while (0)
444
445#else /* !CONFIG_SND_DEBUG */
446
447#define snd_printd(fmt, args...) /* nothing */
448#define snd_assert(expr, args...) (void)(expr)
449#define snd_runtime_check(expr, args...) do { if (!(expr)) { args; } } while (0)
450
451#endif /* CONFIG_SND_DEBUG */
452
453#ifdef CONFIG_SND_DEBUG_DETECT
454/**
455 * snd_printdd - debug printk
456 * @format: format string
457 *
458 * Compiled only when Works like snd_printk() for debugging purpose.
459 * Ignored when CONFIG_SND_DEBUG_DETECT is not set.
460 */
461#define snd_printdd(format, args...) snd_printk(format, ##args)
462#else
463#define snd_printdd(format, args...) /* nothing */
464#endif
465
466#define snd_BUG() snd_assert(0, )
467
468
469static inline void snd_timestamp_now(struct timespec *tstamp, int timespec)
470{
471 struct timeval val;
472 /* FIXME: use a linear time source */
473 do_gettimeofday(&val);
474 tstamp->tv_sec = val.tv_sec;
475 tstamp->tv_nsec = val.tv_usec;
476 if (timespec)
477 tstamp->tv_nsec *= 1000L;
478}
479
480static inline void snd_timestamp_zero(struct timespec *tstamp)
481{
482 tstamp->tv_sec = 0;
483 tstamp->tv_nsec = 0;
484}
485
486static inline int snd_timestamp_null(struct timespec *tstamp)
487{
488 return tstamp->tv_sec == 0 && tstamp->tv_nsec == 0;
489}
490
491#define SNDRV_OSS_VERSION ((3<<16)|(8<<8)|(1<<4)|(0)) /* 3.8.1a */
492
493/* for easier backward-porting */
494#if defined(CONFIG_GAMEPORT) || defined(CONFIG_GAMEPORT_MODULE)
495#ifndef gameport_set_dev_parent
496#define gameport_set_dev_parent(gp,xdev) ((gp)->dev.parent = (xdev))
497#define gameport_set_port_data(gp,r) ((gp)->port_data = (r))
498#define gameport_get_port_data(gp) (gp)->port_data
499#endif
500#endif
501
502#endif /* __SOUND_CORE_H */
diff --git a/include/sound/cs4231.h b/include/sound/cs4231.h
new file mode 100644
index 000000000000..d7f90823778a
--- /dev/null
+++ b/include/sound/cs4231.h
@@ -0,0 +1,366 @@
1#ifndef __SOUND_CS4231_H
2#define __SOUND_CS4231_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Definitions for CS4231 & InterWave chips & compatible chips
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "control.h"
26#include "pcm.h"
27#include "timer.h"
28
29#ifdef CONFIG_SBUS
30#define SBUS_SUPPORT
31#include <asm/sbus.h>
32#endif
33
34#if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
35#define EBUS_SUPPORT
36#include <linux/pci.h>
37#include <asm/ebus.h>
38#endif
39
40#if !defined(SBUS_SUPPORT) && !defined(EBUS_SUPPORT)
41#define LEGACY_SUPPORT
42#endif
43
44/* IO ports */
45
46#define CS4231P(x) (c_d_c_CS4231##x)
47
48#define c_d_c_CS4231REGSEL 0
49#define c_d_c_CS4231REG 1
50#define c_d_c_CS4231STATUS 2
51#define c_d_c_CS4231PIO 3
52
53/* codec registers */
54
55#define CS4231_LEFT_INPUT 0x00 /* left input control */
56#define CS4231_RIGHT_INPUT 0x01 /* right input control */
57#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
58#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
59#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
60#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
61#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
62#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
63#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
64#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
65#define CS4231_PIN_CTRL 0x0a /* pin control */
66#define CS4231_TEST_INIT 0x0b /* test and initialization */
67#define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
68#define CS4231_LOOPBACK 0x0d /* loopback control */
69#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
70#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
71#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
72#define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */
73#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
74#define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */
75#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
76#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
77#define CS4231_TIMER_LOW 0x14 /* timer low byte */
78#define CS4231_TIMER_HIGH 0x15 /* timer high byte */
79#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
80#define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */
81#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
82#define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */
83#define CS4236_EXT_REG 0x17 /* extended register access */
84#define CS4231_IRQ_STATUS 0x18 /* irq status register */
85#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
86#define CS4231_VERSION 0x19 /* CS4231(A) - version values */
87#define CS4231_MONO_CTRL 0x1a /* mono input/output control */
88#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
89#define AD1845_PWR_DOWN 0x1b /* power down control */
90#define CS4235_LEFT_MASTER 0x1b /* left master output control */
91#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
92#define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
93#define AD1845_CLOCK 0x1d /* crystal clock select and total power down */
94#define CS4235_RIGHT_MASTER 0x1d /* right master output control */
95#define CS4231_REC_UPR_CNT 0x1e /* record upper count */
96#define CS4231_REC_LWR_CNT 0x1f /* record lower count */
97
98/* definitions for codec register select port - CODECP( REGSEL ) */
99
100#define CS4231_INIT 0x80 /* CODEC is initializing */
101#define CS4231_MCE 0x40 /* mode change enable */
102#define CS4231_TRD 0x20 /* transfer request disable */
103
104/* definitions for codec status register - CODECP( STATUS ) */
105
106#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
107
108/* definitions for codec irq status */
109
110#define CS4231_PLAYBACK_IRQ 0x10
111#define CS4231_RECORD_IRQ 0x20
112#define CS4231_TIMER_IRQ 0x40
113#define CS4231_ALL_IRQS 0x70
114#define CS4231_REC_UNDERRUN 0x08
115#define CS4231_REC_OVERRUN 0x04
116#define CS4231_PLY_OVERRUN 0x02
117#define CS4231_PLY_UNDERRUN 0x01
118
119/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
120
121#define CS4231_ENABLE_MIC_GAIN 0x20
122
123#define CS4231_MIXS_LINE 0x00
124#define CS4231_MIXS_AUX1 0x40
125#define CS4231_MIXS_MIC 0x80
126#define CS4231_MIXS_ALL 0xc0
127
128/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
129
130#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
131#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
132#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
133#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
134#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
135#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
136#define CS4231_STEREO 0x10 /* stereo mode */
137/* bits 3-1 define frequency divisor */
138#define CS4231_XTAL1 0x00 /* 24.576 crystal */
139#define CS4231_XTAL2 0x01 /* 16.9344 crystal */
140
141/* definitions for interface control register - CS4231_IFACE_CTRL */
142
143#define CS4231_RECORD_PIO 0x80 /* record PIO enable */
144#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
145#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
146#define CS4231_AUTOCALIB 0x08 /* auto calibrate */
147#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
148#define CS4231_RECORD_ENABLE 0x02 /* record enable */
149#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
150
151/* definitions for pin control register - CS4231_PIN_CTRL */
152
153#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
154#define CS4231_XCTL1 0x40 /* external control #1 */
155#define CS4231_XCTL0 0x80 /* external control #0 */
156
157/* definitions for test and init register - CS4231_TEST_INIT */
158
159#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
160#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
161
162/* definitions for misc control register - CS4231_MISC_INFO */
163
164#define CS4231_MODE2 0x40 /* MODE 2 */
165#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
166#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
167
168/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
169
170#define CS4231_DACZ 0x01 /* zero DAC when underrun */
171#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
172#define CS4231_OLB 0x80 /* output level bit */
173
174/* definitions for Extended Registers - CS4236+ */
175
176#define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))
177#define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)
178
179#define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */
180#define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */
181#define CS4236_LEFT_MIC 0x28 /* left MIC volume */
182#define CS4236_RIGHT_MIC 0x38 /* right MIC volume */
183#define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */
184#define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */
185#define CS4236_LEFT_FM 0x68 /* left FM volume */
186#define CS4236_RIGHT_FM 0x78 /* right FM volume */
187#define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */
188#define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */
189#define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */
190#define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */
191#define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */
192#define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */
193#define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */
194#define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */
195#define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */
196#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */
197#define CS4236_VERSION 0x9c /* chip version and ID */
198
199/* defines for codec.mode */
200
201#define CS4231_MODE_NONE 0x0000
202#define CS4231_MODE_PLAY 0x0001
203#define CS4231_MODE_RECORD 0x0002
204#define CS4231_MODE_TIMER 0x0004
205#define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
206
207/* defines for codec.hardware */
208
209#define CS4231_HW_DETECT 0x0000 /* let CS4231 driver detect chip */
210#define CS4231_HW_DETECT3 0x0001 /* allow mode 3 */
211#define CS4231_HW_TYPE_MASK 0xff00 /* type mask */
212#define CS4231_HW_CS4231_MASK 0x0100 /* CS4231 serie */
213#define CS4231_HW_CS4231 0x0100 /* CS4231 chip */
214#define CS4231_HW_CS4231A 0x0101 /* CS4231A chip */
215#define CS4231_HW_AD1845 0x0102 /* AD1845 chip */
216#define CS4231_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */
217#define CS4231_HW_CS4232 0x0200 /* CS4232 */
218#define CS4231_HW_CS4232A 0x0201 /* CS4232A */
219#define CS4231_HW_CS4236 0x0202 /* CS4236 */
220#define CS4231_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */
221#define CS4231_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */
222#define CS4231_HW_CS4236B 0x0401 /* CS4236B */
223#define CS4231_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */
224#define CS4231_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */
225#define CS4231_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */
226/* compatible, but clones */
227#define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */
228#define CS4231_HW_OPL3SA2 0x1001 /* OPL3-SA2 chip */
229
230/* defines for codec.hwshare */
231#define CS4231_HWSHARE_IRQ (1<<0)
232#define CS4231_HWSHARE_DMA1 (1<<1)
233#define CS4231_HWSHARE_DMA2 (1<<2)
234
235typedef struct _snd_cs4231 cs4231_t;
236
237struct _snd_cs4231 {
238 unsigned long port; /* base i/o port */
239#ifdef LEGACY_SUPPORT
240 struct resource *res_port;
241 unsigned long cport; /* control base i/o port (CS4236) */
242 struct resource *res_cport;
243 int irq; /* IRQ line */
244 int dma1; /* playback DMA */
245 int dma2; /* record DMA */
246#endif
247 unsigned short version; /* version of CODEC chip */
248 unsigned short mode; /* see to CS4231_MODE_XXXX */
249 unsigned short hardware; /* see to CS4231_HW_XXXX */
250 unsigned short hwshare; /* shared resources */
251 unsigned short single_dma:1, /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
252 ebus_flag:1; /* SPARC: EBUS present */
253
254#ifdef EBUS_SUPPORT
255 struct ebus_dma_info eb2c;
256 struct ebus_dma_info eb2p;
257#endif
258
259#if defined(SBUS_SUPPORT) || defined(EBUS_SUPPORT)
260 union {
261#ifdef SBUS_SUPPORT
262 struct sbus_dev *sdev;
263#endif
264#ifdef EBUS_SUPPORT
265 struct pci_dev *pdev;
266#endif
267 } dev_u;
268 unsigned int p_periods_sent;
269 unsigned int c_periods_sent;
270#endif
271
272 snd_card_t *card;
273 snd_pcm_t *pcm;
274 snd_pcm_substream_t *playback_substream;
275 snd_pcm_substream_t *capture_substream;
276 snd_timer_t *timer;
277
278 unsigned char image[32]; /* registers image */
279 unsigned char eimage[32]; /* extended registers image */
280 unsigned char cimage[16]; /* control registers image */
281 int mce_bit;
282 int calibrate_mute;
283 int sw_3d_bit;
284#ifdef LEGACY_SUPPORT
285 unsigned int p_dma_size;
286 unsigned int c_dma_size;
287#endif
288
289 spinlock_t reg_lock;
290 struct semaphore mce_mutex;
291 struct semaphore open_mutex;
292
293 int (*rate_constraint) (snd_pcm_runtime_t *runtime);
294 void (*set_playback_format) (cs4231_t *chip, snd_pcm_hw_params_t *hw_params, unsigned char pdfr);
295 void (*set_capture_format) (cs4231_t *chip, snd_pcm_hw_params_t *hw_params, unsigned char cdfr);
296 void (*trigger) (cs4231_t *chip, unsigned int what, int start);
297#ifdef CONFIG_PM
298 void (*suspend) (cs4231_t *chip);
299 void (*resume) (cs4231_t *chip);
300#endif
301 void *dma_private_data;
302#ifdef LEGACY_SUPPORT
303 int (*claim_dma) (cs4231_t *chip, void *dma_private_data, int dma);
304 int (*release_dma) (cs4231_t *chip, void *dma_private_data, int dma);
305#endif
306};
307
308/* exported functions */
309
310void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char val);
311unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg);
312void snd_cs4236_ext_out(cs4231_t *chip, unsigned char reg, unsigned char val);
313unsigned char snd_cs4236_ext_in(cs4231_t *chip, unsigned char reg);
314void snd_cs4231_mce_up(cs4231_t *chip);
315void snd_cs4231_mce_down(cs4231_t *chip);
316
317irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id, struct pt_regs *regs);
318
319const char *snd_cs4231_chip_id(cs4231_t *chip);
320
321int snd_cs4231_create(snd_card_t * card,
322 unsigned long port,
323 unsigned long cport,
324 int irq, int dma1, int dma2,
325 unsigned short hardware,
326 unsigned short hwshare,
327 cs4231_t ** rchip);
328int snd_cs4231_pcm(cs4231_t * chip, int device, snd_pcm_t **rpcm);
329int snd_cs4231_timer(cs4231_t * chip, int device, snd_timer_t **rtimer);
330int snd_cs4231_mixer(cs4231_t * chip);
331
332int snd_cs4236_create(snd_card_t * card,
333 unsigned long port,
334 unsigned long cport,
335 int irq, int dma1, int dma2,
336 unsigned short hardware,
337 unsigned short hwshare,
338 cs4231_t ** rchip);
339int snd_cs4236_pcm(cs4231_t * chip, int device, snd_pcm_t **rpcm);
340int snd_cs4236_mixer(cs4231_t * chip);
341
342/*
343 * mixer library
344 */
345
346#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
347{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
348 .info = snd_cs4231_info_single, \
349 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
350 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
351
352int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
353int snd_cs4231_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
354int snd_cs4231_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
355
356#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
357{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
358 .info = snd_cs4231_info_double, \
359 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
360 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
361
362int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
363int snd_cs4231_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
364int snd_cs4231_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
365
366#endif /* __SOUND_CS4231_H */
diff --git a/include/sound/cs46xx.h b/include/sound/cs46xx.h
new file mode 100644
index 000000000000..182dd276ee74
--- /dev/null
+++ b/include/sound/cs46xx.h
@@ -0,0 +1,1756 @@
1#ifndef __SOUND_CS46XX_H
2#define __SOUND_CS46XX_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
6 * Cirrus Logic, Inc.
7 * Definitions for Cirrus Logic CS46xx chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include "pcm.h"
27#include "pcm-indirect.h"
28#include "rawmidi.h"
29#include "ac97_codec.h"
30#include "cs46xx_dsp_spos.h"
31
32#ifndef PCI_VENDOR_ID_CIRRUS
33#define PCI_VENDOR_ID_CIRRUS 0x1013
34#endif
35#ifndef PCI_DEVICE_ID_CIRRUS_4610
36#define PCI_DEVICE_ID_CIRRUS_4610 0x6001
37#endif
38#ifndef PCI_DEVICE_ID_CIRRUS_4612
39#define PCI_DEVICE_ID_CIRRUS_4612 0x6003
40#endif
41#ifndef PCI_DEVICE_ID_CIRRUS_4615
42#define PCI_DEVICE_ID_CIRRUS_4615 0x6004
43#endif
44
45/*
46 * Direct registers
47 */
48
49/*
50 * The following define the offsets of the registers accessed via base address
51 * register zero on the CS46xx part.
52 */
53#define BA0_HISR 0x00000000
54#define BA0_HSR0 0x00000004
55#define BA0_HICR 0x00000008
56#define BA0_DMSR 0x00000100
57#define BA0_HSAR 0x00000110
58#define BA0_HDAR 0x00000114
59#define BA0_HDMR 0x00000118
60#define BA0_HDCR 0x0000011C
61#define BA0_PFMC 0x00000200
62#define BA0_PFCV1 0x00000204
63#define BA0_PFCV2 0x00000208
64#define BA0_PCICFG00 0x00000300
65#define BA0_PCICFG04 0x00000304
66#define BA0_PCICFG08 0x00000308
67#define BA0_PCICFG0C 0x0000030C
68#define BA0_PCICFG10 0x00000310
69#define BA0_PCICFG14 0x00000314
70#define BA0_PCICFG18 0x00000318
71#define BA0_PCICFG1C 0x0000031C
72#define BA0_PCICFG20 0x00000320
73#define BA0_PCICFG24 0x00000324
74#define BA0_PCICFG28 0x00000328
75#define BA0_PCICFG2C 0x0000032C
76#define BA0_PCICFG30 0x00000330
77#define BA0_PCICFG34 0x00000334
78#define BA0_PCICFG38 0x00000338
79#define BA0_PCICFG3C 0x0000033C
80#define BA0_CLKCR1 0x00000400
81#define BA0_CLKCR2 0x00000404
82#define BA0_PLLM 0x00000408
83#define BA0_PLLCC 0x0000040C
84#define BA0_FRR 0x00000410
85#define BA0_CFL1 0x00000414
86#define BA0_CFL2 0x00000418
87#define BA0_SERMC1 0x00000420
88#define BA0_SERMC2 0x00000424
89#define BA0_SERC1 0x00000428
90#define BA0_SERC2 0x0000042C
91#define BA0_SERC3 0x00000430
92#define BA0_SERC4 0x00000434
93#define BA0_SERC5 0x00000438
94#define BA0_SERBSP 0x0000043C
95#define BA0_SERBST 0x00000440
96#define BA0_SERBCM 0x00000444
97#define BA0_SERBAD 0x00000448
98#define BA0_SERBCF 0x0000044C
99#define BA0_SERBWP 0x00000450
100#define BA0_SERBRP 0x00000454
101#ifndef NO_CS4612
102#define BA0_ASER_FADDR 0x00000458
103#endif
104#define BA0_ACCTL 0x00000460
105#define BA0_ACSTS 0x00000464
106#define BA0_ACOSV 0x00000468
107#define BA0_ACCAD 0x0000046C
108#define BA0_ACCDA 0x00000470
109#define BA0_ACISV 0x00000474
110#define BA0_ACSAD 0x00000478
111#define BA0_ACSDA 0x0000047C
112#define BA0_JSPT 0x00000480
113#define BA0_JSCTL 0x00000484
114#define BA0_JSC1 0x00000488
115#define BA0_JSC2 0x0000048C
116#define BA0_MIDCR 0x00000490
117#define BA0_MIDSR 0x00000494
118#define BA0_MIDWP 0x00000498
119#define BA0_MIDRP 0x0000049C
120#define BA0_JSIO 0x000004A0
121#ifndef NO_CS4612
122#define BA0_ASER_MASTER 0x000004A4
123#endif
124#define BA0_CFGI 0x000004B0
125#define BA0_SSVID 0x000004B4
126#define BA0_GPIOR 0x000004B8
127#ifndef NO_CS4612
128#define BA0_EGPIODR 0x000004BC
129#define BA0_EGPIOPTR 0x000004C0
130#define BA0_EGPIOTR 0x000004C4
131#define BA0_EGPIOWR 0x000004C8
132#define BA0_EGPIOSR 0x000004CC
133#define BA0_SERC6 0x000004D0
134#define BA0_SERC7 0x000004D4
135#define BA0_SERACC 0x000004D8
136#define BA0_ACCTL2 0x000004E0
137#define BA0_ACSTS2 0x000004E4
138#define BA0_ACOSV2 0x000004E8
139#define BA0_ACCAD2 0x000004EC
140#define BA0_ACCDA2 0x000004F0
141#define BA0_ACISV2 0x000004F4
142#define BA0_ACSAD2 0x000004F8
143#define BA0_ACSDA2 0x000004FC
144#define BA0_IOTAC0 0x00000500
145#define BA0_IOTAC1 0x00000504
146#define BA0_IOTAC2 0x00000508
147#define BA0_IOTAC3 0x0000050C
148#define BA0_IOTAC4 0x00000510
149#define BA0_IOTAC5 0x00000514
150#define BA0_IOTAC6 0x00000518
151#define BA0_IOTAC7 0x0000051C
152#define BA0_IOTAC8 0x00000520
153#define BA0_IOTAC9 0x00000524
154#define BA0_IOTAC10 0x00000528
155#define BA0_IOTAC11 0x0000052C
156#define BA0_IOTFR0 0x00000540
157#define BA0_IOTFR1 0x00000544
158#define BA0_IOTFR2 0x00000548
159#define BA0_IOTFR3 0x0000054C
160#define BA0_IOTFR4 0x00000550
161#define BA0_IOTFR5 0x00000554
162#define BA0_IOTFR6 0x00000558
163#define BA0_IOTFR7 0x0000055C
164#define BA0_IOTFIFO 0x00000580
165#define BA0_IOTRRD 0x00000584
166#define BA0_IOTFP 0x00000588
167#define BA0_IOTCR 0x0000058C
168#define BA0_DPCID 0x00000590
169#define BA0_DPCIA 0x00000594
170#define BA0_DPCIC 0x00000598
171#define BA0_PCPCIR 0x00000600
172#define BA0_PCPCIG 0x00000604
173#define BA0_PCPCIEN 0x00000608
174#define BA0_EPCIPMC 0x00000610
175#endif
176
177/*
178 * The following define the offsets of the registers and memories accessed via
179 * base address register one on the CS46xx part.
180 */
181#define BA1_SP_DMEM0 0x00000000
182#define BA1_SP_DMEM1 0x00010000
183#define BA1_SP_PMEM 0x00020000
184#define BA1_SP_REG 0x00030000
185#define BA1_SPCR 0x00030000
186#define BA1_DREG 0x00030004
187#define BA1_DSRWP 0x00030008
188#define BA1_TWPR 0x0003000C
189#define BA1_SPWR 0x00030010
190#define BA1_SPIR 0x00030014
191#define BA1_FGR1 0x00030020
192#define BA1_SPCS 0x00030028
193#define BA1_SDSR 0x0003002C
194#define BA1_FRMT 0x00030030
195#define BA1_FRCC 0x00030034
196#define BA1_FRSC 0x00030038
197#define BA1_OMNI_MEM 0x000E0000
198
199
200/*
201 * The following defines are for the flags in the host interrupt status
202 * register.
203 */
204#define HISR_VC_MASK 0x0000FFFF
205#define HISR_VC0 0x00000001
206#define HISR_VC1 0x00000002
207#define HISR_VC2 0x00000004
208#define HISR_VC3 0x00000008
209#define HISR_VC4 0x00000010
210#define HISR_VC5 0x00000020
211#define HISR_VC6 0x00000040
212#define HISR_VC7 0x00000080
213#define HISR_VC8 0x00000100
214#define HISR_VC9 0x00000200
215#define HISR_VC10 0x00000400
216#define HISR_VC11 0x00000800
217#define HISR_VC12 0x00001000
218#define HISR_VC13 0x00002000
219#define HISR_VC14 0x00004000
220#define HISR_VC15 0x00008000
221#define HISR_INT0 0x00010000
222#define HISR_INT1 0x00020000
223#define HISR_DMAI 0x00040000
224#define HISR_FROVR 0x00080000
225#define HISR_MIDI 0x00100000
226#ifdef NO_CS4612
227#define HISR_RESERVED 0x0FE00000
228#else
229#define HISR_SBINT 0x00200000
230#define HISR_RESERVED 0x0FC00000
231#endif
232#define HISR_H0P 0x40000000
233#define HISR_INTENA 0x80000000
234
235/*
236 * The following defines are for the flags in the host signal register 0.
237 */
238#define HSR0_VC_MASK 0xFFFFFFFF
239#define HSR0_VC16 0x00000001
240#define HSR0_VC17 0x00000002
241#define HSR0_VC18 0x00000004
242#define HSR0_VC19 0x00000008
243#define HSR0_VC20 0x00000010
244#define HSR0_VC21 0x00000020
245#define HSR0_VC22 0x00000040
246#define HSR0_VC23 0x00000080
247#define HSR0_VC24 0x00000100
248#define HSR0_VC25 0x00000200
249#define HSR0_VC26 0x00000400
250#define HSR0_VC27 0x00000800
251#define HSR0_VC28 0x00001000
252#define HSR0_VC29 0x00002000
253#define HSR0_VC30 0x00004000
254#define HSR0_VC31 0x00008000
255#define HSR0_VC32 0x00010000
256#define HSR0_VC33 0x00020000
257#define HSR0_VC34 0x00040000
258#define HSR0_VC35 0x00080000
259#define HSR0_VC36 0x00100000
260#define HSR0_VC37 0x00200000
261#define HSR0_VC38 0x00400000
262#define HSR0_VC39 0x00800000
263#define HSR0_VC40 0x01000000
264#define HSR0_VC41 0x02000000
265#define HSR0_VC42 0x04000000
266#define HSR0_VC43 0x08000000
267#define HSR0_VC44 0x10000000
268#define HSR0_VC45 0x20000000
269#define HSR0_VC46 0x40000000
270#define HSR0_VC47 0x80000000
271
272/*
273 * The following defines are for the flags in the host interrupt control
274 * register.
275 */
276#define HICR_IEV 0x00000001
277#define HICR_CHGM 0x00000002
278
279/*
280 * The following defines are for the flags in the DMA status register.
281 */
282#define DMSR_HP 0x00000001
283#define DMSR_HR 0x00000002
284#define DMSR_SP 0x00000004
285#define DMSR_SR 0x00000008
286
287/*
288 * The following defines are for the flags in the host DMA source address
289 * register.
290 */
291#define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
292#define HSAR_DSP_ADDR_MASK 0x0000FFFF
293#define HSAR_MEMID_MASK 0x000F0000
294#define HSAR_MEMID_SP_DMEM0 0x00000000
295#define HSAR_MEMID_SP_DMEM1 0x00010000
296#define HSAR_MEMID_SP_PMEM 0x00020000
297#define HSAR_MEMID_SP_DEBUG 0x00030000
298#define HSAR_MEMID_OMNI_MEM 0x000E0000
299#define HSAR_END 0x40000000
300#define HSAR_ERR 0x80000000
301
302/*
303 * The following defines are for the flags in the host DMA destination address
304 * register.
305 */
306#define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
307#define HDAR_DSP_ADDR_MASK 0x0000FFFF
308#define HDAR_MEMID_MASK 0x000F0000
309#define HDAR_MEMID_SP_DMEM0 0x00000000
310#define HDAR_MEMID_SP_DMEM1 0x00010000
311#define HDAR_MEMID_SP_PMEM 0x00020000
312#define HDAR_MEMID_SP_DEBUG 0x00030000
313#define HDAR_MEMID_OMNI_MEM 0x000E0000
314#define HDAR_END 0x40000000
315#define HDAR_ERR 0x80000000
316
317/*
318 * The following defines are for the flags in the host DMA control register.
319 */
320#define HDMR_AC_MASK 0x0000F000
321#define HDMR_AC_8_16 0x00001000
322#define HDMR_AC_M_S 0x00002000
323#define HDMR_AC_B_L 0x00004000
324#define HDMR_AC_S_U 0x00008000
325
326/*
327 * The following defines are for the flags in the host DMA control register.
328 */
329#define HDCR_COUNT_MASK 0x000003FF
330#define HDCR_DONE 0x00004000
331#define HDCR_OPT 0x00008000
332#define HDCR_WBD 0x00400000
333#define HDCR_WBS 0x00800000
334#define HDCR_DMS_MASK 0x07000000
335#define HDCR_DMS_LINEAR 0x00000000
336#define HDCR_DMS_16_DWORDS 0x01000000
337#define HDCR_DMS_32_DWORDS 0x02000000
338#define HDCR_DMS_64_DWORDS 0x03000000
339#define HDCR_DMS_128_DWORDS 0x04000000
340#define HDCR_DMS_256_DWORDS 0x05000000
341#define HDCR_DMS_512_DWORDS 0x06000000
342#define HDCR_DMS_1024_DWORDS 0x07000000
343#define HDCR_DH 0x08000000
344#define HDCR_SMS_MASK 0x70000000
345#define HDCR_SMS_LINEAR 0x00000000
346#define HDCR_SMS_16_DWORDS 0x10000000
347#define HDCR_SMS_32_DWORDS 0x20000000
348#define HDCR_SMS_64_DWORDS 0x30000000
349#define HDCR_SMS_128_DWORDS 0x40000000
350#define HDCR_SMS_256_DWORDS 0x50000000
351#define HDCR_SMS_512_DWORDS 0x60000000
352#define HDCR_SMS_1024_DWORDS 0x70000000
353#define HDCR_SH 0x80000000
354#define HDCR_COUNT_SHIFT 0
355
356/*
357 * The following defines are for the flags in the performance monitor control
358 * register.
359 */
360#define PFMC_C1SS_MASK 0x0000001F
361#define PFMC_C1EV 0x00000020
362#define PFMC_C1RS 0x00008000
363#define PFMC_C2SS_MASK 0x001F0000
364#define PFMC_C2EV 0x00200000
365#define PFMC_C2RS 0x80000000
366#define PFMC_C1SS_SHIFT 0
367#define PFMC_C2SS_SHIFT 16
368#define PFMC_BUS_GRANT 0
369#define PFMC_GRANT_AFTER_REQ 1
370#define PFMC_TRANSACTION 2
371#define PFMC_DWORD_TRANSFER 3
372#define PFMC_SLAVE_READ 4
373#define PFMC_SLAVE_WRITE 5
374#define PFMC_PREEMPTION 6
375#define PFMC_DISCONNECT_RETRY 7
376#define PFMC_INTERRUPT 8
377#define PFMC_BUS_OWNERSHIP 9
378#define PFMC_TRANSACTION_LAG 10
379#define PFMC_PCI_CLOCK 11
380#define PFMC_SERIAL_CLOCK 12
381#define PFMC_SP_CLOCK 13
382
383/*
384 * The following defines are for the flags in the performance counter value 1
385 * register.
386 */
387#define PFCV1_PC1V_MASK 0xFFFFFFFF
388#define PFCV1_PC1V_SHIFT 0
389
390/*
391 * The following defines are for the flags in the performance counter value 2
392 * register.
393 */
394#define PFCV2_PC2V_MASK 0xFFFFFFFF
395#define PFCV2_PC2V_SHIFT 0
396
397/*
398 * The following defines are for the flags in the clock control register 1.
399 */
400#define CLKCR1_OSCS 0x00000001
401#define CLKCR1_OSCP 0x00000002
402#define CLKCR1_PLLSS_MASK 0x0000000C
403#define CLKCR1_PLLSS_SERIAL 0x00000000
404#define CLKCR1_PLLSS_CRYSTAL 0x00000004
405#define CLKCR1_PLLSS_PCI 0x00000008
406#define CLKCR1_PLLSS_RESERVED 0x0000000C
407#define CLKCR1_PLLP 0x00000010
408#define CLKCR1_SWCE 0x00000020
409#define CLKCR1_PLLOS 0x00000040
410
411/*
412 * The following defines are for the flags in the clock control register 2.
413 */
414#define CLKCR2_PDIVS_MASK 0x0000000F
415#define CLKCR2_PDIVS_1 0x00000001
416#define CLKCR2_PDIVS_2 0x00000002
417#define CLKCR2_PDIVS_4 0x00000004
418#define CLKCR2_PDIVS_7 0x00000007
419#define CLKCR2_PDIVS_8 0x00000008
420#define CLKCR2_PDIVS_16 0x00000000
421
422/*
423 * The following defines are for the flags in the PLL multiplier register.
424 */
425#define PLLM_MASK 0x000000FF
426#define PLLM_SHIFT 0
427
428/*
429 * The following defines are for the flags in the PLL capacitor coefficient
430 * register.
431 */
432#define PLLCC_CDR_MASK 0x00000007
433#ifndef NO_CS4610
434#define PLLCC_CDR_240_350_MHZ 0x00000000
435#define PLLCC_CDR_184_265_MHZ 0x00000001
436#define PLLCC_CDR_144_205_MHZ 0x00000002
437#define PLLCC_CDR_111_160_MHZ 0x00000003
438#define PLLCC_CDR_87_123_MHZ 0x00000004
439#define PLLCC_CDR_67_96_MHZ 0x00000005
440#define PLLCC_CDR_52_74_MHZ 0x00000006
441#define PLLCC_CDR_45_58_MHZ 0x00000007
442#endif
443#ifndef NO_CS4612
444#define PLLCC_CDR_271_398_MHZ 0x00000000
445#define PLLCC_CDR_227_330_MHZ 0x00000001
446#define PLLCC_CDR_167_239_MHZ 0x00000002
447#define PLLCC_CDR_150_215_MHZ 0x00000003
448#define PLLCC_CDR_107_154_MHZ 0x00000004
449#define PLLCC_CDR_98_140_MHZ 0x00000005
450#define PLLCC_CDR_73_104_MHZ 0x00000006
451#define PLLCC_CDR_63_90_MHZ 0x00000007
452#endif
453#define PLLCC_LPF_MASK 0x000000F8
454#ifndef NO_CS4610
455#define PLLCC_LPF_23850_60000_KHZ 0x00000000
456#define PLLCC_LPF_7960_26290_KHZ 0x00000008
457#define PLLCC_LPF_4160_10980_KHZ 0x00000018
458#define PLLCC_LPF_1740_4580_KHZ 0x00000038
459#define PLLCC_LPF_724_1910_KHZ 0x00000078
460#define PLLCC_LPF_317_798_KHZ 0x000000F8
461#endif
462#ifndef NO_CS4612
463#define PLLCC_LPF_25580_64530_KHZ 0x00000000
464#define PLLCC_LPF_14360_37270_KHZ 0x00000008
465#define PLLCC_LPF_6100_16020_KHZ 0x00000018
466#define PLLCC_LPF_2540_6690_KHZ 0x00000038
467#define PLLCC_LPF_1050_2780_KHZ 0x00000078
468#define PLLCC_LPF_450_1160_KHZ 0x000000F8
469#endif
470
471/*
472 * The following defines are for the flags in the feature reporting register.
473 */
474#define FRR_FAB_MASK 0x00000003
475#define FRR_MASK_MASK 0x0000001C
476#ifdef NO_CS4612
477#define FRR_CFOP_MASK 0x000000E0
478#else
479#define FRR_CFOP_MASK 0x00000FE0
480#endif
481#define FRR_CFOP_NOT_DVD 0x00000020
482#define FRR_CFOP_A3D 0x00000040
483#define FRR_CFOP_128_PIN 0x00000080
484#ifndef NO_CS4612
485#define FRR_CFOP_CS4280 0x00000800
486#endif
487#define FRR_FAB_SHIFT 0
488#define FRR_MASK_SHIFT 2
489#define FRR_CFOP_SHIFT 5
490
491/*
492 * The following defines are for the flags in the configuration load 1
493 * register.
494 */
495#define CFL1_CLOCK_SOURCE_MASK 0x00000003
496#define CFL1_CLOCK_SOURCE_CS423X 0x00000000
497#define CFL1_CLOCK_SOURCE_AC97 0x00000001
498#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
499#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
500#define CFL1_VALID_DATA_MASK 0x000000FF
501
502/*
503 * The following defines are for the flags in the configuration load 2
504 * register.
505 */
506#define CFL2_VALID_DATA_MASK 0x000000FF
507
508/*
509 * The following defines are for the flags in the serial port master control
510 * register 1.
511 */
512#define SERMC1_MSPE 0x00000001
513#define SERMC1_PTC_MASK 0x0000000E
514#define SERMC1_PTC_CS423X 0x00000000
515#define SERMC1_PTC_AC97 0x00000002
516#define SERMC1_PTC_DAC 0x00000004
517#define SERMC1_PLB 0x00000010
518#define SERMC1_XLB 0x00000020
519
520/*
521 * The following defines are for the flags in the serial port master control
522 * register 2.
523 */
524#define SERMC2_LROE 0x00000001
525#define SERMC2_MCOE 0x00000002
526#define SERMC2_MCDIV 0x00000004
527
528/*
529 * The following defines are for the flags in the serial port 1 configuration
530 * register.
531 */
532#define SERC1_SO1EN 0x00000001
533#define SERC1_SO1F_MASK 0x0000000E
534#define SERC1_SO1F_CS423X 0x00000000
535#define SERC1_SO1F_AC97 0x00000002
536#define SERC1_SO1F_DAC 0x00000004
537#define SERC1_SO1F_SPDIF 0x00000006
538
539/*
540 * The following defines are for the flags in the serial port 2 configuration
541 * register.
542 */
543#define SERC2_SI1EN 0x00000001
544#define SERC2_SI1F_MASK 0x0000000E
545#define SERC2_SI1F_CS423X 0x00000000
546#define SERC2_SI1F_AC97 0x00000002
547#define SERC2_SI1F_ADC 0x00000004
548#define SERC2_SI1F_SPDIF 0x00000006
549
550/*
551 * The following defines are for the flags in the serial port 3 configuration
552 * register.
553 */
554#define SERC3_SO2EN 0x00000001
555#define SERC3_SO2F_MASK 0x00000006
556#define SERC3_SO2F_DAC 0x00000000
557#define SERC3_SO2F_SPDIF 0x00000002
558
559/*
560 * The following defines are for the flags in the serial port 4 configuration
561 * register.
562 */
563#define SERC4_SO3EN 0x00000001
564#define SERC4_SO3F_MASK 0x00000006
565#define SERC4_SO3F_DAC 0x00000000
566#define SERC4_SO3F_SPDIF 0x00000002
567
568/*
569 * The following defines are for the flags in the serial port 5 configuration
570 * register.
571 */
572#define SERC5_SI2EN 0x00000001
573#define SERC5_SI2F_MASK 0x00000006
574#define SERC5_SI2F_ADC 0x00000000
575#define SERC5_SI2F_SPDIF 0x00000002
576
577/*
578 * The following defines are for the flags in the serial port backdoor sample
579 * pointer register.
580 */
581#define SERBSP_FSP_MASK 0x0000000F
582#define SERBSP_FSP_SHIFT 0
583
584/*
585 * The following defines are for the flags in the serial port backdoor status
586 * register.
587 */
588#define SERBST_RRDY 0x00000001
589#define SERBST_WBSY 0x00000002
590
591/*
592 * The following defines are for the flags in the serial port backdoor command
593 * register.
594 */
595#define SERBCM_RDC 0x00000001
596#define SERBCM_WRC 0x00000002
597
598/*
599 * The following defines are for the flags in the serial port backdoor address
600 * register.
601 */
602#ifdef NO_CS4612
603#define SERBAD_FAD_MASK 0x000000FF
604#else
605#define SERBAD_FAD_MASK 0x000001FF
606#endif
607#define SERBAD_FAD_SHIFT 0
608
609/*
610 * The following defines are for the flags in the serial port backdoor
611 * configuration register.
612 */
613#define SERBCF_HBP 0x00000001
614
615/*
616 * The following defines are for the flags in the serial port backdoor write
617 * port register.
618 */
619#define SERBWP_FWD_MASK 0x000FFFFF
620#define SERBWP_FWD_SHIFT 0
621
622/*
623 * The following defines are for the flags in the serial port backdoor read
624 * port register.
625 */
626#define SERBRP_FRD_MASK 0x000FFFFF
627#define SERBRP_FRD_SHIFT 0
628
629/*
630 * The following defines are for the flags in the async FIFO address register.
631 */
632#ifndef NO_CS4612
633#define ASER_FADDR_A1_MASK 0x000001FF
634#define ASER_FADDR_EN1 0x00008000
635#define ASER_FADDR_A2_MASK 0x01FF0000
636#define ASER_FADDR_EN2 0x80000000
637#define ASER_FADDR_A1_SHIFT 0
638#define ASER_FADDR_A2_SHIFT 16
639#endif
640
641/*
642 * The following defines are for the flags in the AC97 control register.
643 */
644#define ACCTL_RSTN 0x00000001
645#define ACCTL_ESYN 0x00000002
646#define ACCTL_VFRM 0x00000004
647#define ACCTL_DCV 0x00000008
648#define ACCTL_CRW 0x00000010
649#define ACCTL_ASYN 0x00000020
650#ifndef NO_CS4612
651#define ACCTL_TC 0x00000040
652#endif
653
654/*
655 * The following defines are for the flags in the AC97 status register.
656 */
657#define ACSTS_CRDY 0x00000001
658#define ACSTS_VSTS 0x00000002
659#ifndef NO_CS4612
660#define ACSTS_WKUP 0x00000004
661#endif
662
663/*
664 * The following defines are for the flags in the AC97 output slot valid
665 * register.
666 */
667#define ACOSV_SLV3 0x00000001
668#define ACOSV_SLV4 0x00000002
669#define ACOSV_SLV5 0x00000004
670#define ACOSV_SLV6 0x00000008
671#define ACOSV_SLV7 0x00000010
672#define ACOSV_SLV8 0x00000020
673#define ACOSV_SLV9 0x00000040
674#define ACOSV_SLV10 0x00000080
675#define ACOSV_SLV11 0x00000100
676#define ACOSV_SLV12 0x00000200
677
678/*
679 * The following defines are for the flags in the AC97 command address
680 * register.
681 */
682#define ACCAD_CI_MASK 0x0000007F
683#define ACCAD_CI_SHIFT 0
684
685/*
686 * The following defines are for the flags in the AC97 command data register.
687 */
688#define ACCDA_CD_MASK 0x0000FFFF
689#define ACCDA_CD_SHIFT 0
690
691/*
692 * The following defines are for the flags in the AC97 input slot valid
693 * register.
694 */
695#define ACISV_ISV3 0x00000001
696#define ACISV_ISV4 0x00000002
697#define ACISV_ISV5 0x00000004
698#define ACISV_ISV6 0x00000008
699#define ACISV_ISV7 0x00000010
700#define ACISV_ISV8 0x00000020
701#define ACISV_ISV9 0x00000040
702#define ACISV_ISV10 0x00000080
703#define ACISV_ISV11 0x00000100
704#define ACISV_ISV12 0x00000200
705
706/*
707 * The following defines are for the flags in the AC97 status address
708 * register.
709 */
710#define ACSAD_SI_MASK 0x0000007F
711#define ACSAD_SI_SHIFT 0
712
713/*
714 * The following defines are for the flags in the AC97 status data register.
715 */
716#define ACSDA_SD_MASK 0x0000FFFF
717#define ACSDA_SD_SHIFT 0
718
719/*
720 * The following defines are for the flags in the joystick poll/trigger
721 * register.
722 */
723#define JSPT_CAX 0x00000001
724#define JSPT_CAY 0x00000002
725#define JSPT_CBX 0x00000004
726#define JSPT_CBY 0x00000008
727#define JSPT_BA1 0x00000010
728#define JSPT_BA2 0x00000020
729#define JSPT_BB1 0x00000040
730#define JSPT_BB2 0x00000080
731
732/*
733 * The following defines are for the flags in the joystick control register.
734 */
735#define JSCTL_SP_MASK 0x00000003
736#define JSCTL_SP_SLOW 0x00000000
737#define JSCTL_SP_MEDIUM_SLOW 0x00000001
738#define JSCTL_SP_MEDIUM_FAST 0x00000002
739#define JSCTL_SP_FAST 0x00000003
740#define JSCTL_ARE 0x00000004
741
742/*
743 * The following defines are for the flags in the joystick coordinate pair 1
744 * readback register.
745 */
746#define JSC1_Y1V_MASK 0x0000FFFF
747#define JSC1_X1V_MASK 0xFFFF0000
748#define JSC1_Y1V_SHIFT 0
749#define JSC1_X1V_SHIFT 16
750
751/*
752 * The following defines are for the flags in the joystick coordinate pair 2
753 * readback register.
754 */
755#define JSC2_Y2V_MASK 0x0000FFFF
756#define JSC2_X2V_MASK 0xFFFF0000
757#define JSC2_Y2V_SHIFT 0
758#define JSC2_X2V_SHIFT 16
759
760/*
761 * The following defines are for the flags in the MIDI control register.
762 */
763#define MIDCR_TXE 0x00000001 /* Enable transmitting. */
764#define MIDCR_RXE 0x00000002 /* Enable receiving. */
765#define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
766#define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
767#define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
768#define MIDCR_MRST 0x00000020 /* Reset interface. */
769
770/*
771 * The following defines are for the flags in the MIDI status register.
772 */
773#define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
774#define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
775
776/*
777 * The following defines are for the flags in the MIDI write port register.
778 */
779#define MIDWP_MWD_MASK 0x000000FF
780#define MIDWP_MWD_SHIFT 0
781
782/*
783 * The following defines are for the flags in the MIDI read port register.
784 */
785#define MIDRP_MRD_MASK 0x000000FF
786#define MIDRP_MRD_SHIFT 0
787
788/*
789 * The following defines are for the flags in the joystick GPIO register.
790 */
791#define JSIO_DAX 0x00000001
792#define JSIO_DAY 0x00000002
793#define JSIO_DBX 0x00000004
794#define JSIO_DBY 0x00000008
795#define JSIO_AXOE 0x00000010
796#define JSIO_AYOE 0x00000020
797#define JSIO_BXOE 0x00000040
798#define JSIO_BYOE 0x00000080
799
800/*
801 * The following defines are for the flags in the master async/sync serial
802 * port enable register.
803 */
804#ifndef NO_CS4612
805#define ASER_MASTER_ME 0x00000001
806#endif
807
808/*
809 * The following defines are for the flags in the configuration interface
810 * register.
811 */
812#define CFGI_CLK 0x00000001
813#define CFGI_DOUT 0x00000002
814#define CFGI_DIN_EEN 0x00000004
815#define CFGI_EELD 0x00000008
816
817/*
818 * The following defines are for the flags in the subsystem ID and vendor ID
819 * register.
820 */
821#define SSVID_VID_MASK 0x0000FFFF
822#define SSVID_SID_MASK 0xFFFF0000
823#define SSVID_VID_SHIFT 0
824#define SSVID_SID_SHIFT 16
825
826/*
827 * The following defines are for the flags in the GPIO pin interface register.
828 */
829#define GPIOR_VOLDN 0x00000001
830#define GPIOR_VOLUP 0x00000002
831#define GPIOR_SI2D 0x00000004
832#define GPIOR_SI2OE 0x00000008
833
834/*
835 * The following defines are for the flags in the extended GPIO pin direction
836 * register.
837 */
838#ifndef NO_CS4612
839#define EGPIODR_GPOE0 0x00000001
840#define EGPIODR_GPOE1 0x00000002
841#define EGPIODR_GPOE2 0x00000004
842#define EGPIODR_GPOE3 0x00000008
843#define EGPIODR_GPOE4 0x00000010
844#define EGPIODR_GPOE5 0x00000020
845#define EGPIODR_GPOE6 0x00000040
846#define EGPIODR_GPOE7 0x00000080
847#define EGPIODR_GPOE8 0x00000100
848#endif
849
850/*
851 * The following defines are for the flags in the extended GPIO pin polarity/
852 * type register.
853 */
854#ifndef NO_CS4612
855#define EGPIOPTR_GPPT0 0x00000001
856#define EGPIOPTR_GPPT1 0x00000002
857#define EGPIOPTR_GPPT2 0x00000004
858#define EGPIOPTR_GPPT3 0x00000008
859#define EGPIOPTR_GPPT4 0x00000010
860#define EGPIOPTR_GPPT5 0x00000020
861#define EGPIOPTR_GPPT6 0x00000040
862#define EGPIOPTR_GPPT7 0x00000080
863#define EGPIOPTR_GPPT8 0x00000100
864#endif
865
866/*
867 * The following defines are for the flags in the extended GPIO pin sticky
868 * register.
869 */
870#ifndef NO_CS4612
871#define EGPIOTR_GPS0 0x00000001
872#define EGPIOTR_GPS1 0x00000002
873#define EGPIOTR_GPS2 0x00000004
874#define EGPIOTR_GPS3 0x00000008
875#define EGPIOTR_GPS4 0x00000010
876#define EGPIOTR_GPS5 0x00000020
877#define EGPIOTR_GPS6 0x00000040
878#define EGPIOTR_GPS7 0x00000080
879#define EGPIOTR_GPS8 0x00000100
880#endif
881
882/*
883 * The following defines are for the flags in the extended GPIO ping wakeup
884 * register.
885 */
886#ifndef NO_CS4612
887#define EGPIOWR_GPW0 0x00000001
888#define EGPIOWR_GPW1 0x00000002
889#define EGPIOWR_GPW2 0x00000004
890#define EGPIOWR_GPW3 0x00000008
891#define EGPIOWR_GPW4 0x00000010
892#define EGPIOWR_GPW5 0x00000020
893#define EGPIOWR_GPW6 0x00000040
894#define EGPIOWR_GPW7 0x00000080
895#define EGPIOWR_GPW8 0x00000100
896#endif
897
898/*
899 * The following defines are for the flags in the extended GPIO pin status
900 * register.
901 */
902#ifndef NO_CS4612
903#define EGPIOSR_GPS0 0x00000001
904#define EGPIOSR_GPS1 0x00000002
905#define EGPIOSR_GPS2 0x00000004
906#define EGPIOSR_GPS3 0x00000008
907#define EGPIOSR_GPS4 0x00000010
908#define EGPIOSR_GPS5 0x00000020
909#define EGPIOSR_GPS6 0x00000040
910#define EGPIOSR_GPS7 0x00000080
911#define EGPIOSR_GPS8 0x00000100
912#endif
913
914/*
915 * The following defines are for the flags in the serial port 6 configuration
916 * register.
917 */
918#ifndef NO_CS4612
919#define SERC6_ASDO2EN 0x00000001
920#endif
921
922/*
923 * The following defines are for the flags in the serial port 7 configuration
924 * register.
925 */
926#ifndef NO_CS4612
927#define SERC7_ASDI2EN 0x00000001
928#define SERC7_POSILB 0x00000002
929#define SERC7_SIPOLB 0x00000004
930#define SERC7_SOSILB 0x00000008
931#define SERC7_SISOLB 0x00000010
932#endif
933
934/*
935 * The following defines are for the flags in the serial port AC link
936 * configuration register.
937 */
938#ifndef NO_CS4612
939#define SERACC_CHIP_TYPE_MASK 0x00000001
940#define SERACC_CHIP_TYPE_1_03 0x00000000
941#define SERACC_CHIP_TYPE_2_0 0x00000001
942#define SERACC_TWO_CODECS 0x00000002
943#define SERACC_MDM 0x00000004
944#define SERACC_HSP 0x00000008
945#define SERACC_ODT 0x00000010 /* only CS4630 */
946#endif
947
948/*
949 * The following defines are for the flags in the AC97 control register 2.
950 */
951#ifndef NO_CS4612
952#define ACCTL2_RSTN 0x00000001
953#define ACCTL2_ESYN 0x00000002
954#define ACCTL2_VFRM 0x00000004
955#define ACCTL2_DCV 0x00000008
956#define ACCTL2_CRW 0x00000010
957#define ACCTL2_ASYN 0x00000020
958#endif
959
960/*
961 * The following defines are for the flags in the AC97 status register 2.
962 */
963#ifndef NO_CS4612
964#define ACSTS2_CRDY 0x00000001
965#define ACSTS2_VSTS 0x00000002
966#endif
967
968/*
969 * The following defines are for the flags in the AC97 output slot valid
970 * register 2.
971 */
972#ifndef NO_CS4612
973#define ACOSV2_SLV3 0x00000001
974#define ACOSV2_SLV4 0x00000002
975#define ACOSV2_SLV5 0x00000004
976#define ACOSV2_SLV6 0x00000008
977#define ACOSV2_SLV7 0x00000010
978#define ACOSV2_SLV8 0x00000020
979#define ACOSV2_SLV9 0x00000040
980#define ACOSV2_SLV10 0x00000080
981#define ACOSV2_SLV11 0x00000100
982#define ACOSV2_SLV12 0x00000200
983#endif
984
985/*
986 * The following defines are for the flags in the AC97 command address
987 * register 2.
988 */
989#ifndef NO_CS4612
990#define ACCAD2_CI_MASK 0x0000007F
991#define ACCAD2_CI_SHIFT 0
992#endif
993
994/*
995 * The following defines are for the flags in the AC97 command data register
996 * 2.
997 */
998#ifndef NO_CS4612
999#define ACCDA2_CD_MASK 0x0000FFFF
1000#define ACCDA2_CD_SHIFT 0
1001#endif
1002
1003/*
1004 * The following defines are for the flags in the AC97 input slot valid
1005 * register 2.
1006 */
1007#ifndef NO_CS4612
1008#define ACISV2_ISV3 0x00000001
1009#define ACISV2_ISV4 0x00000002
1010#define ACISV2_ISV5 0x00000004
1011#define ACISV2_ISV6 0x00000008
1012#define ACISV2_ISV7 0x00000010
1013#define ACISV2_ISV8 0x00000020
1014#define ACISV2_ISV9 0x00000040
1015#define ACISV2_ISV10 0x00000080
1016#define ACISV2_ISV11 0x00000100
1017#define ACISV2_ISV12 0x00000200
1018#endif
1019
1020/*
1021 * The following defines are for the flags in the AC97 status address
1022 * register 2.
1023 */
1024#ifndef NO_CS4612
1025#define ACSAD2_SI_MASK 0x0000007F
1026#define ACSAD2_SI_SHIFT 0
1027#endif
1028
1029/*
1030 * The following defines are for the flags in the AC97 status data register 2.
1031 */
1032#ifndef NO_CS4612
1033#define ACSDA2_SD_MASK 0x0000FFFF
1034#define ACSDA2_SD_SHIFT 0
1035#endif
1036
1037/*
1038 * The following defines are for the flags in the I/O trap address and control
1039 * registers (all 12).
1040 */
1041#ifndef NO_CS4612
1042#define IOTAC_SA_MASK 0x0000FFFF
1043#define IOTAC_MSK_MASK 0x000F0000
1044#define IOTAC_IODC_MASK 0x06000000
1045#define IOTAC_IODC_16_BIT 0x00000000
1046#define IOTAC_IODC_10_BIT 0x02000000
1047#define IOTAC_IODC_12_BIT 0x04000000
1048#define IOTAC_WSPI 0x08000000
1049#define IOTAC_RSPI 0x10000000
1050#define IOTAC_WSE 0x20000000
1051#define IOTAC_WE 0x40000000
1052#define IOTAC_RE 0x80000000
1053#define IOTAC_SA_SHIFT 0
1054#define IOTAC_MSK_SHIFT 16
1055#endif
1056
1057/*
1058 * The following defines are for the flags in the I/O trap fast read registers
1059 * (all 8).
1060 */
1061#ifndef NO_CS4612
1062#define IOTFR_D_MASK 0x0000FFFF
1063#define IOTFR_A_MASK 0x000F0000
1064#define IOTFR_R_MASK 0x0F000000
1065#define IOTFR_ALL 0x40000000
1066#define IOTFR_VL 0x80000000
1067#define IOTFR_D_SHIFT 0
1068#define IOTFR_A_SHIFT 16
1069#define IOTFR_R_SHIFT 24
1070#endif
1071
1072/*
1073 * The following defines are for the flags in the I/O trap FIFO register.
1074 */
1075#ifndef NO_CS4612
1076#define IOTFIFO_BA_MASK 0x00003FFF
1077#define IOTFIFO_S_MASK 0x00FF0000
1078#define IOTFIFO_OF 0x40000000
1079#define IOTFIFO_SPIOF 0x80000000
1080#define IOTFIFO_BA_SHIFT 0
1081#define IOTFIFO_S_SHIFT 16
1082#endif
1083
1084/*
1085 * The following defines are for the flags in the I/O trap retry read data
1086 * register.
1087 */
1088#ifndef NO_CS4612
1089#define IOTRRD_D_MASK 0x0000FFFF
1090#define IOTRRD_RDV 0x80000000
1091#define IOTRRD_D_SHIFT 0
1092#endif
1093
1094/*
1095 * The following defines are for the flags in the I/O trap FIFO pointer
1096 * register.
1097 */
1098#ifndef NO_CS4612
1099#define IOTFP_CA_MASK 0x00003FFF
1100#define IOTFP_PA_MASK 0x3FFF0000
1101#define IOTFP_CA_SHIFT 0
1102#define IOTFP_PA_SHIFT 16
1103#endif
1104
1105/*
1106 * The following defines are for the flags in the I/O trap control register.
1107 */
1108#ifndef NO_CS4612
1109#define IOTCR_ITD 0x00000001
1110#define IOTCR_HRV 0x00000002
1111#define IOTCR_SRV 0x00000004
1112#define IOTCR_DTI 0x00000008
1113#define IOTCR_DFI 0x00000010
1114#define IOTCR_DDP 0x00000020
1115#define IOTCR_JTE 0x00000040
1116#define IOTCR_PPE 0x00000080
1117#endif
1118
1119/*
1120 * The following defines are for the flags in the direct PCI data register.
1121 */
1122#ifndef NO_CS4612
1123#define DPCID_D_MASK 0xFFFFFFFF
1124#define DPCID_D_SHIFT 0
1125#endif
1126
1127/*
1128 * The following defines are for the flags in the direct PCI address register.
1129 */
1130#ifndef NO_CS4612
1131#define DPCIA_A_MASK 0xFFFFFFFF
1132#define DPCIA_A_SHIFT 0
1133#endif
1134
1135/*
1136 * The following defines are for the flags in the direct PCI command register.
1137 */
1138#ifndef NO_CS4612
1139#define DPCIC_C_MASK 0x0000000F
1140#define DPCIC_C_IOREAD 0x00000002
1141#define DPCIC_C_IOWRITE 0x00000003
1142#define DPCIC_BE_MASK 0x000000F0
1143#endif
1144
1145/*
1146 * The following defines are for the flags in the PC/PCI request register.
1147 */
1148#ifndef NO_CS4612
1149#define PCPCIR_RDC_MASK 0x00000007
1150#define PCPCIR_C_MASK 0x00007000
1151#define PCPCIR_REQ 0x00008000
1152#define PCPCIR_RDC_SHIFT 0
1153#define PCPCIR_C_SHIFT 12
1154#endif
1155
1156/*
1157 * The following defines are for the flags in the PC/PCI grant register.
1158 */
1159#ifndef NO_CS4612
1160#define PCPCIG_GDC_MASK 0x00000007
1161#define PCPCIG_VL 0x00008000
1162#define PCPCIG_GDC_SHIFT 0
1163#endif
1164
1165/*
1166 * The following defines are for the flags in the PC/PCI master enable
1167 * register.
1168 */
1169#ifndef NO_CS4612
1170#define PCPCIEN_EN 0x00000001
1171#endif
1172
1173/*
1174 * The following defines are for the flags in the extended PCI power
1175 * management control register.
1176 */
1177#ifndef NO_CS4612
1178#define EPCIPMC_GWU 0x00000001
1179#define EPCIPMC_FSPC 0x00000002
1180#endif
1181
1182/*
1183 * The following defines are for the flags in the SP control register.
1184 */
1185#define SPCR_RUN 0x00000001
1186#define SPCR_STPFR 0x00000002
1187#define SPCR_RUNFR 0x00000004
1188#define SPCR_TICK 0x00000008
1189#define SPCR_DRQEN 0x00000020
1190#define SPCR_RSTSP 0x00000040
1191#define SPCR_OREN 0x00000080
1192#ifndef NO_CS4612
1193#define SPCR_PCIINT 0x00000100
1194#define SPCR_OINTD 0x00000200
1195#define SPCR_CRE 0x00008000
1196#endif
1197
1198/*
1199 * The following defines are for the flags in the debug index register.
1200 */
1201#define DREG_REGID_MASK 0x0000007F
1202#define DREG_DEBUG 0x00000080
1203#define DREG_RGBK_MASK 0x00000700
1204#define DREG_TRAP 0x00000800
1205#if !defined(NO_CS4612)
1206#if !defined(NO_CS4615)
1207#define DREG_TRAPX 0x00001000
1208#endif
1209#endif
1210#define DREG_REGID_SHIFT 0
1211#define DREG_RGBK_SHIFT 8
1212#define DREG_RGBK_REGID_MASK 0x0000077F
1213#define DREG_REGID_R0 0x00000010
1214#define DREG_REGID_R1 0x00000011
1215#define DREG_REGID_R2 0x00000012
1216#define DREG_REGID_R3 0x00000013
1217#define DREG_REGID_R4 0x00000014
1218#define DREG_REGID_R5 0x00000015
1219#define DREG_REGID_R6 0x00000016
1220#define DREG_REGID_R7 0x00000017
1221#define DREG_REGID_R8 0x00000018
1222#define DREG_REGID_R9 0x00000019
1223#define DREG_REGID_RA 0x0000001A
1224#define DREG_REGID_RB 0x0000001B
1225#define DREG_REGID_RC 0x0000001C
1226#define DREG_REGID_RD 0x0000001D
1227#define DREG_REGID_RE 0x0000001E
1228#define DREG_REGID_RF 0x0000001F
1229#define DREG_REGID_RA_BUS_LOW 0x00000020
1230#define DREG_REGID_RA_BUS_HIGH 0x00000038
1231#define DREG_REGID_YBUS_LOW 0x00000050
1232#define DREG_REGID_YBUS_HIGH 0x00000058
1233#define DREG_REGID_TRAP_0 0x00000100
1234#define DREG_REGID_TRAP_1 0x00000101
1235#define DREG_REGID_TRAP_2 0x00000102
1236#define DREG_REGID_TRAP_3 0x00000103
1237#define DREG_REGID_TRAP_4 0x00000104
1238#define DREG_REGID_TRAP_5 0x00000105
1239#define DREG_REGID_TRAP_6 0x00000106
1240#define DREG_REGID_TRAP_7 0x00000107
1241#define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
1242#define DREG_REGID_TOP_OF_STACK 0x0000010F
1243#if !defined(NO_CS4612)
1244#if !defined(NO_CS4615)
1245#define DREG_REGID_TRAP_8 0x00000110
1246#define DREG_REGID_TRAP_9 0x00000111
1247#define DREG_REGID_TRAP_10 0x00000112
1248#define DREG_REGID_TRAP_11 0x00000113
1249#define DREG_REGID_TRAP_12 0x00000114
1250#define DREG_REGID_TRAP_13 0x00000115
1251#define DREG_REGID_TRAP_14 0x00000116
1252#define DREG_REGID_TRAP_15 0x00000117
1253#define DREG_REGID_TRAP_16 0x00000118
1254#define DREG_REGID_TRAP_17 0x00000119
1255#define DREG_REGID_TRAP_18 0x0000011A
1256#define DREG_REGID_TRAP_19 0x0000011B
1257#define DREG_REGID_TRAP_20 0x0000011C
1258#define DREG_REGID_TRAP_21 0x0000011D
1259#define DREG_REGID_TRAP_22 0x0000011E
1260#define DREG_REGID_TRAP_23 0x0000011F
1261#endif
1262#endif
1263#define DREG_REGID_RSA0_LOW 0x00000200
1264#define DREG_REGID_RSA0_HIGH 0x00000201
1265#define DREG_REGID_RSA1_LOW 0x00000202
1266#define DREG_REGID_RSA1_HIGH 0x00000203
1267#define DREG_REGID_RSA2 0x00000204
1268#define DREG_REGID_RSA3 0x00000205
1269#define DREG_REGID_RSI0_LOW 0x00000206
1270#define DREG_REGID_RSI0_HIGH 0x00000207
1271#define DREG_REGID_RSI1 0x00000208
1272#define DREG_REGID_RSI2 0x00000209
1273#define DREG_REGID_SAGUSTATUS 0x0000020A
1274#define DREG_REGID_RSCONFIG01_LOW 0x0000020B
1275#define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
1276#define DREG_REGID_RSCONFIG23_LOW 0x0000020D
1277#define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
1278#define DREG_REGID_RSDMA01E 0x0000020F
1279#define DREG_REGID_RSDMA23E 0x00000210
1280#define DREG_REGID_RSD0_LOW 0x00000211
1281#define DREG_REGID_RSD0_HIGH 0x00000212
1282#define DREG_REGID_RSD1_LOW 0x00000213
1283#define DREG_REGID_RSD1_HIGH 0x00000214
1284#define DREG_REGID_RSD2_LOW 0x00000215
1285#define DREG_REGID_RSD2_HIGH 0x00000216
1286#define DREG_REGID_RSD3_LOW 0x00000217
1287#define DREG_REGID_RSD3_HIGH 0x00000218
1288#define DREG_REGID_SRAR_HIGH 0x0000021A
1289#define DREG_REGID_SRAR_LOW 0x0000021B
1290#define DREG_REGID_DMA_STATE 0x0000021C
1291#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
1292#define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
1293#define DREG_REGID_CPU_STATUS 0x00000300
1294#define DREG_REGID_MAC_MODE 0x00000301
1295#define DREG_REGID_STACK_AND_REPEAT 0x00000302
1296#define DREG_REGID_INDEX0 0x00000304
1297#define DREG_REGID_INDEX1 0x00000305
1298#define DREG_REGID_DMA_STATE_0_3 0x00000400
1299#define DREG_REGID_DMA_STATE_4_7 0x00000404
1300#define DREG_REGID_DMA_STATE_8_11 0x00000408
1301#define DREG_REGID_DMA_STATE_12_15 0x0000040C
1302#define DREG_REGID_DMA_STATE_16_19 0x00000410
1303#define DREG_REGID_DMA_STATE_20_23 0x00000414
1304#define DREG_REGID_DMA_STATE_24_27 0x00000418
1305#define DREG_REGID_DMA_STATE_28_31 0x0000041C
1306#define DREG_REGID_DMA_STATE_32_35 0x00000420
1307#define DREG_REGID_DMA_STATE_36_39 0x00000424
1308#define DREG_REGID_DMA_STATE_40_43 0x00000428
1309#define DREG_REGID_DMA_STATE_44_47 0x0000042C
1310#define DREG_REGID_DMA_STATE_48_51 0x00000430
1311#define DREG_REGID_DMA_STATE_52_55 0x00000434
1312#define DREG_REGID_DMA_STATE_56_59 0x00000438
1313#define DREG_REGID_DMA_STATE_60_63 0x0000043C
1314#define DREG_REGID_DMA_STATE_64_67 0x00000440
1315#define DREG_REGID_DMA_STATE_68_71 0x00000444
1316#define DREG_REGID_DMA_STATE_72_75 0x00000448
1317#define DREG_REGID_DMA_STATE_76_79 0x0000044C
1318#define DREG_REGID_DMA_STATE_80_83 0x00000450
1319#define DREG_REGID_DMA_STATE_84_87 0x00000454
1320#define DREG_REGID_DMA_STATE_88_91 0x00000458
1321#define DREG_REGID_DMA_STATE_92_95 0x0000045C
1322#define DREG_REGID_TRAP_SELECT 0x00000500
1323#define DREG_REGID_TRAP_WRITE_0 0x00000500
1324#define DREG_REGID_TRAP_WRITE_1 0x00000501
1325#define DREG_REGID_TRAP_WRITE_2 0x00000502
1326#define DREG_REGID_TRAP_WRITE_3 0x00000503
1327#define DREG_REGID_TRAP_WRITE_4 0x00000504
1328#define DREG_REGID_TRAP_WRITE_5 0x00000505
1329#define DREG_REGID_TRAP_WRITE_6 0x00000506
1330#define DREG_REGID_TRAP_WRITE_7 0x00000507
1331#if !defined(NO_CS4612)
1332#if !defined(NO_CS4615)
1333#define DREG_REGID_TRAP_WRITE_8 0x00000510
1334#define DREG_REGID_TRAP_WRITE_9 0x00000511
1335#define DREG_REGID_TRAP_WRITE_10 0x00000512
1336#define DREG_REGID_TRAP_WRITE_11 0x00000513
1337#define DREG_REGID_TRAP_WRITE_12 0x00000514
1338#define DREG_REGID_TRAP_WRITE_13 0x00000515
1339#define DREG_REGID_TRAP_WRITE_14 0x00000516
1340#define DREG_REGID_TRAP_WRITE_15 0x00000517
1341#define DREG_REGID_TRAP_WRITE_16 0x00000518
1342#define DREG_REGID_TRAP_WRITE_17 0x00000519
1343#define DREG_REGID_TRAP_WRITE_18 0x0000051A
1344#define DREG_REGID_TRAP_WRITE_19 0x0000051B
1345#define DREG_REGID_TRAP_WRITE_20 0x0000051C
1346#define DREG_REGID_TRAP_WRITE_21 0x0000051D
1347#define DREG_REGID_TRAP_WRITE_22 0x0000051E
1348#define DREG_REGID_TRAP_WRITE_23 0x0000051F
1349#endif
1350#endif
1351#define DREG_REGID_MAC0_ACC0_LOW 0x00000600
1352#define DREG_REGID_MAC0_ACC1_LOW 0x00000601
1353#define DREG_REGID_MAC0_ACC2_LOW 0x00000602
1354#define DREG_REGID_MAC0_ACC3_LOW 0x00000603
1355#define DREG_REGID_MAC1_ACC0_LOW 0x00000604
1356#define DREG_REGID_MAC1_ACC1_LOW 0x00000605
1357#define DREG_REGID_MAC1_ACC2_LOW 0x00000606
1358#define DREG_REGID_MAC1_ACC3_LOW 0x00000607
1359#define DREG_REGID_MAC0_ACC0_MID 0x00000608
1360#define DREG_REGID_MAC0_ACC1_MID 0x00000609
1361#define DREG_REGID_MAC0_ACC2_MID 0x0000060A
1362#define DREG_REGID_MAC0_ACC3_MID 0x0000060B
1363#define DREG_REGID_MAC1_ACC0_MID 0x0000060C
1364#define DREG_REGID_MAC1_ACC1_MID 0x0000060D
1365#define DREG_REGID_MAC1_ACC2_MID 0x0000060E
1366#define DREG_REGID_MAC1_ACC3_MID 0x0000060F
1367#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
1368#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
1369#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
1370#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
1371#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
1372#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
1373#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
1374#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
1375#define DREG_REGID_RSHOUT_LOW 0x00000620
1376#define DREG_REGID_RSHOUT_MID 0x00000628
1377#define DREG_REGID_RSHOUT_HIGH 0x00000630
1378
1379/*
1380 * The following defines are for the flags in the DMA stream requestor write
1381 */
1382#define DSRWP_DSR_MASK 0x0000000F
1383#define DSRWP_DSR_BG_RQ 0x00000001
1384#define DSRWP_DSR_PRIORITY_MASK 0x00000006
1385#define DSRWP_DSR_PRIORITY_0 0x00000000
1386#define DSRWP_DSR_PRIORITY_1 0x00000002
1387#define DSRWP_DSR_PRIORITY_2 0x00000004
1388#define DSRWP_DSR_PRIORITY_3 0x00000006
1389#define DSRWP_DSR_RQ_PENDING 0x00000008
1390
1391/*
1392 * The following defines are for the flags in the trap write port register.
1393 */
1394#define TWPR_TW_MASK 0x0000FFFF
1395#define TWPR_TW_SHIFT 0
1396
1397/*
1398 * The following defines are for the flags in the stack pointer write
1399 * register.
1400 */
1401#define SPWR_STKP_MASK 0x0000000F
1402#define SPWR_STKP_SHIFT 0
1403
1404/*
1405 * The following defines are for the flags in the SP interrupt register.
1406 */
1407#define SPIR_FRI 0x00000001
1408#define SPIR_DOI 0x00000002
1409#define SPIR_GPI2 0x00000004
1410#define SPIR_GPI3 0x00000008
1411#define SPIR_IP0 0x00000010
1412#define SPIR_IP1 0x00000020
1413#define SPIR_IP2 0x00000040
1414#define SPIR_IP3 0x00000080
1415
1416/*
1417 * The following defines are for the flags in the functional group 1 register.
1418 */
1419#define FGR1_F1S_MASK 0x0000FFFF
1420#define FGR1_F1S_SHIFT 0
1421
1422/*
1423 * The following defines are for the flags in the SP clock status register.
1424 */
1425#define SPCS_FRI 0x00000001
1426#define SPCS_DOI 0x00000002
1427#define SPCS_GPI2 0x00000004
1428#define SPCS_GPI3 0x00000008
1429#define SPCS_IP0 0x00000010
1430#define SPCS_IP1 0x00000020
1431#define SPCS_IP2 0x00000040
1432#define SPCS_IP3 0x00000080
1433#define SPCS_SPRUN 0x00000100
1434#define SPCS_SLEEP 0x00000200
1435#define SPCS_FG 0x00000400
1436#define SPCS_ORUN 0x00000800
1437#define SPCS_IRQ 0x00001000
1438#define SPCS_FGN_MASK 0x0000E000
1439#define SPCS_FGN_SHIFT 13
1440
1441/*
1442 * The following defines are for the flags in the SP DMA requestor status
1443 * register.
1444 */
1445#define SDSR_DCS_MASK 0x000000FF
1446#define SDSR_DCS_SHIFT 0
1447#define SDSR_DCS_NONE 0x00000007
1448
1449/*
1450 * The following defines are for the flags in the frame timer register.
1451 */
1452#define FRMT_FTV_MASK 0x0000FFFF
1453#define FRMT_FTV_SHIFT 0
1454
1455/*
1456 * The following defines are for the flags in the frame timer current count
1457 * register.
1458 */
1459#define FRCC_FCC_MASK 0x0000FFFF
1460#define FRCC_FCC_SHIFT 0
1461
1462/*
1463 * The following defines are for the flags in the frame timer save count
1464 * register.
1465 */
1466#define FRSC_FCS_MASK 0x0000FFFF
1467#define FRSC_FCS_SHIFT 0
1468
1469/*
1470 * The following define the various flags stored in the scatter/gather
1471 * descriptors.
1472 */
1473#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
1474#define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
1475#define DMA_SG_SAMPLE_END_FLAG 0x10000000
1476#define DMA_SG_LOOP_END_FLAG 0x20000000
1477#define DMA_SG_SIGNAL_END_FLAG 0x40000000
1478#define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
1479#define DMA_SG_NEXT_ENTRY_SHIFT 3
1480#define DMA_SG_SAMPLE_END_SHIFT 16
1481
1482/*
1483 * The following define the offsets of the fields within the on-chip generic
1484 * DMA requestor.
1485 */
1486#define DMA_RQ_CONTROL1 0x00000000
1487#define DMA_RQ_CONTROL2 0x00000004
1488#define DMA_RQ_SOURCE_ADDR 0x00000008
1489#define DMA_RQ_DESTINATION_ADDR 0x0000000C
1490#define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
1491#define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
1492#define DMA_RQ_LOOP_START_ADDR 0x00000018
1493#define DMA_RQ_POST_LOOP_ADDR 0x0000001C
1494#define DMA_RQ_PAGE_MAP_ADDR 0x00000020
1495
1496/*
1497 * The following defines are for the flags in the first control word of the
1498 * on-chip generic DMA requestor.
1499 */
1500#define DMA_RQ_C1_COUNT_MASK 0x000003FF
1501#define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
1502#define DMA_RQ_C1_SOURCE_GATHER 0x00002000
1503#define DMA_RQ_C1_DONE_FLAG 0x00004000
1504#define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
1505#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
1506#define DMA_RQ_C1_FULL_PAGE 0x00000000
1507#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
1508#define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
1509#define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
1510#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
1511#define DMA_RQ_C1_NOT_LOOP_END 0x00000000
1512#define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
1513#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
1514#define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
1515#define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
1516#define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
1517#define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
1518#define DMA_RQ_C1_PM_RESERVED 0x00200000
1519#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
1520#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
1521#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
1522#define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
1523#define DMA_RQ_C1_DEST_LINEAR 0x00000000
1524#define DMA_RQ_C1_DEST_MOD16 0x01000000
1525#define DMA_RQ_C1_DEST_MOD32 0x02000000
1526#define DMA_RQ_C1_DEST_MOD64 0x03000000
1527#define DMA_RQ_C1_DEST_MOD128 0x04000000
1528#define DMA_RQ_C1_DEST_MOD256 0x05000000
1529#define DMA_RQ_C1_DEST_MOD512 0x06000000
1530#define DMA_RQ_C1_DEST_MOD1024 0x07000000
1531#define DMA_RQ_C1_DEST_ON_HOST 0x08000000
1532#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
1533#define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
1534#define DMA_RQ_C1_SOURCE_MOD16 0x10000000
1535#define DMA_RQ_C1_SOURCE_MOD32 0x20000000
1536#define DMA_RQ_C1_SOURCE_MOD64 0x30000000
1537#define DMA_RQ_C1_SOURCE_MOD128 0x40000000
1538#define DMA_RQ_C1_SOURCE_MOD256 0x50000000
1539#define DMA_RQ_C1_SOURCE_MOD512 0x60000000
1540#define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
1541#define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
1542#define DMA_RQ_C1_COUNT_SHIFT 0
1543
1544/*
1545 * The following defines are for the flags in the second control word of the
1546 * on-chip generic DMA requestor.
1547 */
1548#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
1549#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
1550#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
1551#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
1552#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
1553#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
1554#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
1555#define DMA_RQ_C2_AC_NONE 0x00000000
1556#define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
1557#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
1558#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
1559#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
1560#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
1561#define DMA_RQ_C2_LOOP_MASK 0x30000000
1562#define DMA_RQ_C2_NO_LOOP 0x00000000
1563#define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
1564#define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
1565#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
1566#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
1567#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
1568#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
1569#define DMA_RQ_C2_LOOP_END_SHIFT 16
1570
1571/*
1572 * The following defines are for the flags in the source and destination words
1573 * of the on-chip generic DMA requestor.
1574 */
1575#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
1576#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
1577#define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
1578#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
1579#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
1580#define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
1581#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
1582#define DMA_RQ_SD_END_FLAG 0x40000000
1583#define DMA_RQ_SD_ERROR_FLAG 0x80000000
1584#define DMA_RQ_SD_ADDRESS_SHIFT 0
1585
1586/*
1587 * The following defines are for the flags in the page map address word of the
1588 * on-chip generic DMA requestor.
1589 */
1590#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
1591#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
1592#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
1593#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
1594
1595#define BA1_VARIDEC_BUF_1 0x000
1596
1597#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
1598#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
1599#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
1600#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
1601#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
1602#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
1603#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
1604
1605#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
1606#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
1607#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
1608#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
1609#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
1610#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
1611#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
1612#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
1613
1614#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
1615#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
1616#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
1617#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
1618
1619/*
1620 *
1621 */
1622
1623#define CS46XX_MODE_OUTPUT (1<<0) /* MIDI UART - output */
1624#define CS46XX_MODE_INPUT (1<<1) /* MIDI UART - input */
1625
1626/*
1627 *
1628 */
1629
1630#define SAVE_REG_MAX 0x10
1631#define POWER_DOWN_ALL 0x7f0f
1632
1633/* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
1634#define MAX_NR_AC97 4
1635#define CS46XX_PRIMARY_CODEC_INDEX 0
1636#define CS46XX_SECONDARY_CODEC_INDEX 1
1637#define CS46XX_SECONDARY_CODEC_OFFSET 0x80
1638#define CS46XX_DSP_CAPTURE_CHANNEL 1
1639
1640/* capture */
1641#define CS46XX_DSP_CAPTURE_CHANNEL 1
1642
1643/* mixer */
1644#define CS46XX_MIXER_SPDIF_INPUT_ELEMENT 1
1645#define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT 2
1646
1647typedef struct _snd_cs46xx cs46xx_t;
1648
1649typedef struct _snd_cs46xx_pcm_t {
1650 struct snd_dma_buffer hw_buf;
1651
1652 unsigned int ctl;
1653 unsigned int shift; /* Shift count to trasform frames in bytes */
1654 snd_pcm_indirect_t pcm_rec;
1655 snd_pcm_substream_t *substream;
1656
1657 pcm_channel_descriptor_t * pcm_channel;
1658
1659 int pcm_channel_id; /* Fron Rear, Center Lfe ... */
1660} cs46xx_pcm_t;
1661
1662typedef struct {
1663 char name[24];
1664 unsigned long base;
1665 void __iomem *remap_addr;
1666 unsigned long size;
1667 struct resource *resource;
1668} snd_cs46xx_region_t;
1669
1670struct _snd_cs46xx {
1671 int irq;
1672 unsigned long ba0_addr;
1673 unsigned long ba1_addr;
1674 union {
1675 struct {
1676 snd_cs46xx_region_t ba0;
1677 snd_cs46xx_region_t data0;
1678 snd_cs46xx_region_t data1;
1679 snd_cs46xx_region_t pmem;
1680 snd_cs46xx_region_t reg;
1681 } name;
1682 snd_cs46xx_region_t idx[5];
1683 } region;
1684
1685 unsigned int mode;
1686
1687 struct {
1688 struct snd_dma_buffer hw_buf;
1689
1690 unsigned int ctl;
1691 unsigned int shift; /* Shift count to trasform frames in bytes */
1692 snd_pcm_indirect_t pcm_rec;
1693 snd_pcm_substream_t *substream;
1694 } capt;
1695
1696
1697 int nr_ac97_codecs;
1698 ac97_bus_t *ac97_bus;
1699 ac97_t *ac97[MAX_NR_AC97];
1700
1701 struct pci_dev *pci;
1702 snd_card_t *card;
1703 snd_pcm_t *pcm;
1704
1705 snd_rawmidi_t *rmidi;
1706 snd_rawmidi_substream_t *midi_input;
1707 snd_rawmidi_substream_t *midi_output;
1708
1709 spinlock_t reg_lock;
1710 unsigned int midcr;
1711 unsigned int uartm;
1712
1713 int amplifier;
1714 void (*amplifier_ctrl)(cs46xx_t *, int);
1715 void (*active_ctrl)(cs46xx_t *, int);
1716 void (*mixer_init)(cs46xx_t *);
1717
1718 struct pci_dev *acpi_dev;
1719 int acpi_port;
1720 snd_kcontrol_t *eapd_switch; /* for amplifier hack */
1721 int accept_valid; /* accept mmap valid (for OSS) */
1722
1723 struct gameport *gameport;
1724
1725#ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
1726 int current_gpio;
1727#endif
1728#ifdef CONFIG_SND_CS46XX_NEW_DSP
1729 struct semaphore spos_mutex;
1730
1731 dsp_spos_instance_t * dsp_spos_instance;
1732
1733 snd_pcm_t *pcm_rear;
1734 snd_pcm_t *pcm_center_lfe;
1735 snd_pcm_t *pcm_iec958;
1736#else /* for compatibility */
1737 cs46xx_pcm_t *playback_pcm;
1738 unsigned int play_ctl;
1739#endif
1740};
1741
1742int snd_cs46xx_create(snd_card_t *card,
1743 struct pci_dev *pci,
1744 int external_amp, int thinkpad,
1745 cs46xx_t **rcodec);
1746
1747int snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
1748int snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
1749int snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
1750int snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
1751int snd_cs46xx_mixer(cs46xx_t *chip);
1752int snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rmidi);
1753int snd_cs46xx_start_dsp(cs46xx_t *chip);
1754int snd_cs46xx_gameport(cs46xx_t *chip);
1755
1756#endif /* __SOUND_CS46XX_H */
diff --git a/include/sound/cs46xx_dsp_scb_types.h b/include/sound/cs46xx_dsp_scb_types.h
new file mode 100644
index 000000000000..3f990a3a6903
--- /dev/null
+++ b/include/sound/cs46xx_dsp_scb_types.h
@@ -0,0 +1,1216 @@
1/*
2 * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 *
21 * NOTE: comments are copy/paste from cwcemb80.lst
22 * provided by Tom Woller at Cirrus (my only
23 * documentation about the SP OS running inside
24 * the DSP)
25 */
26
27#ifndef __CS46XX_DSP_SCB_TYPES_H__
28#define __CS46XX_DSP_SCB_TYPES_H__
29
30#include <asm/byteorder.h>
31
32#ifndef ___DSP_DUAL_16BIT_ALLOC
33#if defined(__LITTLE_ENDIAN)
34#define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 a; u16 b;
35#elif defined(__BIG_ENDIAN)
36#define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 b; u16 a;
37#else
38#error Not __LITTLE_ENDIAN and not __BIG_ENDIAN, then what ???
39#endif
40#endif
41
42/* This structs are used internally by the SP */
43
44typedef struct _basic_dma_req_t {
45 /* DMA Requestor Word 0 (DCW) fields:
46
47 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0]
48 _______________________________________________________________________________________
49 |S| SBT |D| DBT |wb|wb| | | LS | SS |Opt|Do|SSG|DSG| | | | | | | Dword |
50 |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1|
51 */
52 u32 dcw; /* DMA Control Word */
53 u32 dmw; /* DMA Mode Word */
54 u32 saw; /* Source Address Word */
55 u32 daw; /* Destination Address Word */
56} basic_dma_req_t;
57
58typedef struct _scatter_gather_ext_t {
59 u32 npaw; /* Next-Page Address Word */
60
61 /* DMA Requestor Word 5 (NPCW) fields:
62
63 31-30 29 28 [27:16] [15:12] [11:3] [2:0]
64 _________________________________________________________________________________________
65 |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | |
66 |page|__|__| ___________________________|_________|__page, if !sample-end___________|____|
67 */
68 u32 npcw; /* Next-Page Control Word */
69 u32 lbaw; /* Loop-Begin Address Word */
70 u32 nplbaw; /* Next-Page after Loop-Begin Address Word */
71 u32 sgaw; /* Scatter/Gather Address Word */
72} scatter_gather_ext_t;
73
74typedef struct _volume_control_t {
75 ___DSP_DUAL_16BIT_ALLOC(
76 rightTarg, /* Target volume for left & right channels */
77 leftTarg
78 )
79 ___DSP_DUAL_16BIT_ALLOC(
80 rightVol, /* Current left & right channel volumes */
81 leftVol
82 )
83} volume_control_t;
84
85/* Generic stream control block (SCB) structure definition */
86typedef struct _generic_scb_t {
87 /* For streaming I/O, the DSP should never alter any words in the DMA
88 requestor or the scatter/gather extension. Only ad hoc DMA request
89 streams are free to alter the requestor (currently only occur in the
90 DOS-based MIDI controller and in debugger-inserted code).
91
92 If an SCB does not have any associated DMA requestor, these 9 ints
93 may be freed for use by other tasks, but the pointer to the SCB must
94 still be such that the insOrd:nextSCB appear at offset 9 from the
95 SCB pointer.
96
97 Basic (non scatter/gather) DMA requestor (4 ints)
98 */
99
100 /* Initialized by the host, only modified by DMA
101 R/O for the DSP task */
102 basic_dma_req_t basic_req; /* Optional */
103
104 /* Scatter/gather DMA requestor extension (5 ints)
105 Initialized by the host, only modified by DMA
106 DSP task never needs to even read these.
107 */
108 scatter_gather_ext_t sg_ext; /* Optional */
109
110 /* Sublist pointer & next stream control block (SCB) link.
111 Initialized & modified by the host R/O for the DSP task
112 */
113 ___DSP_DUAL_16BIT_ALLOC(
114 next_scb, /* REQUIRED */
115 sub_list_ptr /* REQUIRED */
116 )
117
118 /* Pointer to this tasks parameter block & stream function pointer
119 Initialized by the host R/O for the DSP task */
120 ___DSP_DUAL_16BIT_ALLOC(
121 entry_point, /* REQUIRED */
122 this_spb /* REQUIRED */
123 )
124
125 /* rsConfig register for stream buffer (rsDMA reg.
126 is loaded from basicReq.daw for incoming streams, or
127 basicReq.saw, for outgoing streams)
128
129 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0]
130 ______________________________________________________________________________
131 |DMA |D|maxDMAsize| streamNum|dir|p| | | | | | |ds |shr 1|rev Cy | mod |
132 |prio |_|__________|__________|___|_|__|__|__|__|_|_|___|_____|_______|_______|
133 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0]
134
135
136 Initialized by the host R/O for the DSP task
137 */
138 u32 strm_rs_config; /* REQUIRED */
139 //
140 /* On mixer input streams: indicates mixer input stream configuration
141 On Tees, this is copied from the stream being snooped
142
143 Stream sample pointer & MAC-unit mode for this stream
144
145 Initialized by the host Updated by the DSP task
146 */
147 u32 strm_buf_ptr; /* REQUIRED */
148
149 /* On mixer input streams: points to next mixer input and is updated by the
150 mixer subroutine in the "parent" DSP task
151 (least-significant 16 bits are preserved, unused)
152
153 On Tees, the pointer is copied from the stream being snooped on
154 initialization, and, subsequently, it is copied into the
155 stream being snooped.
156
157 On wavetable/3D voices: the strmBufPtr will use all 32 bits to allow for
158 fractional phase accumulation
159
160 Fractional increment per output sample in the input sample buffer
161
162 (Not used on mixer input streams & redefined on Tees)
163 On wavetable/3D voices: this 32-bit word specifies the integer.fractional
164 increment per output sample.
165 */
166 u32 strmPhiIncr;
167
168
169 /* Standard stereo volume control
170 Initialized by the host (host updates target volumes)
171
172 Current volumes update by the DSP task
173 On mixer input streams: required & updated by the mixer subroutine in the
174 "parent" DSP task
175
176 On Tees, both current & target volumes are copied up on initialization,
177 and, subsequently, the target volume is copied up while the current
178 volume is copied down.
179
180 These two 32-bit words are redefined for wavetable & 3-D voices.
181 */
182 volume_control_t vol_ctrl_t; /* Optional */
183} generic_scb_t;
184
185
186typedef struct _spos_control_block_t {
187 /* WARNING: Certain items in this structure are modified by the host
188 Any dword that can be modified by the host, must not be
189 modified by the SP as the host can only do atomic dword
190 writes, and to do otherwise, even a read modify write,
191 may lead to corrupted data on the SP.
192
193 This rule does not apply to one off boot time initialisation prior to starting the SP
194 */
195
196
197 ___DSP_DUAL_16BIT_ALLOC(
198 /* First element on the Hyper forground task tree */
199 hfg_tree_root_ptr, /* HOST */
200 /* First 3 dwords are written by the host and read-only on the DSP */
201 hfg_stack_base /* HOST */
202 )
203
204 ___DSP_DUAL_16BIT_ALLOC(
205 /* Point to this data structure to enable easy access */
206 spos_cb_ptr, /* SP */
207 prev_task_tree_ptr /* SP && HOST */
208 )
209
210 ___DSP_DUAL_16BIT_ALLOC(
211 /* Currently Unused */
212 xxinterval_timer_period,
213 /* Enable extension of SPOS data structure */
214 HFGSPB_ptr
215 )
216
217
218 ___DSP_DUAL_16BIT_ALLOC(
219 xxnum_HFG_ticks_thisInterval,
220 /* Modified by the DSP */
221 xxnum_tntervals
222 )
223
224
225 /* Set by DSP upon encountering a trap (breakpoint) or a spurious
226 interrupt. The host must clear this dword after reading it
227 upon receiving spInt1. */
228 ___DSP_DUAL_16BIT_ALLOC(
229 spurious_int_flag, /* (Host & SP) Nature of the spurious interrupt */
230 trap_flag /* (Host & SP) Nature of detected Trap */
231 )
232
233 ___DSP_DUAL_16BIT_ALLOC(
234 unused2,
235 invalid_IP_flag /* (Host & SP ) Indicate detection of invalid instruction pointer */
236 )
237
238 ___DSP_DUAL_16BIT_ALLOC(
239 /* pointer to forground task tree header for use in next task search */
240 fg_task_tree_hdr_ptr, /* HOST */
241 /* Data structure for controlling synchronous link update */
242 hfg_sync_update_ptr /* HOST */
243 )
244
245 ___DSP_DUAL_16BIT_ALLOC(
246 begin_foreground_FCNT, /* SP */
247 /* Place holder for holding sleep timing */
248 last_FCNT_before_sleep /* SP */
249 )
250
251 ___DSP_DUAL_16BIT_ALLOC(
252 unused7, /* SP */
253 next_task_treePtr /* SP */
254 )
255
256 u32 unused5;
257
258 ___DSP_DUAL_16BIT_ALLOC(
259 active_flags, /* SP */
260 /* State flags, used to assist control of execution of Hyper Forground */
261 HFG_flags /* SP */
262 )
263
264 ___DSP_DUAL_16BIT_ALLOC(
265 unused9,
266 unused8
267 )
268
269 /* Space for saving enough context so that we can set up enough
270 to save some more context.
271 */
272 u32 rFE_save_for_invalid_IP;
273 u32 r32_save_for_spurious_int;
274 u32 r32_save_for_trap;
275 u32 r32_save_for_HFG;
276} spos_control_block_t;
277
278/* SPB for MIX_TO_OSTREAM algorithm family */
279typedef struct _mix2_ostream_spb_t
280{
281 /* 16b.16b integer.frac approximation to the
282 number of 3 sample triplets to output each
283 frame. (approximation must be floor, to
284 insure that the fractional error is always
285 positive)
286 */
287 u32 outTripletsPerFrame;
288
289 /* 16b.16b integer.frac accumulated number of
290 output triplets since the start of group
291 */
292 u32 accumOutTriplets;
293} mix2_ostream_spb_t;
294
295/* SCB for Timing master algorithm */
296typedef struct _timing_master_scb_t {
297 /* First 12 dwords from generic_scb_t */
298 basic_dma_req_t basic_req; /* Optional */
299 scatter_gather_ext_t sg_ext; /* Optional */
300 ___DSP_DUAL_16BIT_ALLOC(
301 next_scb, /* REQUIRED */
302 sub_list_ptr /* REQUIRED */
303 )
304
305 ___DSP_DUAL_16BIT_ALLOC(
306 entry_point, /* REQUIRED */
307 this_spb /* REQUIRED */
308 )
309
310 ___DSP_DUAL_16BIT_ALLOC(
311 /* Initial values are 0000:xxxx */
312 reserved,
313 extra_sample_accum
314 )
315
316
317 /* Initial values are xxxx:0000
318 hi: Current CODEC output FIFO pointer
319 (0 to 0x0f)
320 lo: Flag indicating that the CODEC
321 FIFO is sync'd (host clears to
322 resynchronize the FIFO pointer
323 upon start/restart)
324 */
325 ___DSP_DUAL_16BIT_ALLOC(
326 codec_FIFO_syncd,
327 codec_FIFO_ptr
328 )
329
330 /* Init. 8000:0005 for 44.1k
331 8000:0001 for 48k
332 hi: Fractional sample accumulator 0.16b
333 lo: Number of frames remaining to be
334 processed in the current group of
335 frames
336 */
337 ___DSP_DUAL_16BIT_ALLOC(
338 frac_samp_accum_qm1,
339 TM_frms_left_in_group
340 )
341
342 /* Init. 0001:0005 for 44.1k
343 0000:0001 for 48k
344 hi: Fractional sample correction factor 0.16b
345 to be added every frameGroupLength frames
346 to correct for truncation error in
347 nsamp_per_frm_q15
348 lo: Number of frames in the group
349 */
350 ___DSP_DUAL_16BIT_ALLOC(
351 frac_samp_correction_qm1,
352 TM_frm_group_length
353 )
354
355 /* Init. 44.1k*65536/8k = 0x00058333 for 44.1k
356 48k*65536/8k = 0x00060000 for 48k
357 16b.16b integer.frac approximation to the
358 number of samples to output each frame.
359 (approximation must be floor, to insure */
360 u32 nsamp_per_frm_q15;
361} timing_master_scb_t;
362
363/* SCB for CODEC output algorithm */
364typedef struct _codec_output_scb_t {
365 /* First 13 dwords from generic_scb_t */
366 basic_dma_req_t basic_req; /* Optional */
367 scatter_gather_ext_t sg_ext; /* Optional */
368 ___DSP_DUAL_16BIT_ALLOC(
369 next_scb, /* REQUIRED */
370 sub_list_ptr /* REQUIRED */
371 )
372
373 ___DSP_DUAL_16BIT_ALLOC(
374 entry_point, /* REQUIRED */
375 this_spb /* REQUIRED */
376 )
377
378 u32 strm_rs_config; /* REQUIRED */
379
380 u32 strm_buf_ptr; /* REQUIRED */
381
382 /* NOTE: The CODEC output task reads samples from the first task on its
383 sublist at the stream buffer pointer (init. to lag DMA destination
384 address word). After the required number of samples is transferred,
385 the CODEC output task advances sub_list_ptr->strm_buf_ptr past the samples
386 consumed.
387 */
388
389 /* Init. 0000:0010 for SDout
390 0060:0010 for SDout2
391 0080:0010 for SDout3
392 hi: Base IO address of FIFO to which
393 the left-channel samples are to
394 be written.
395 lo: Displacement for the base IO
396 address for left-channel to obtain
397 the base IO address for the FIFO
398 to which the right-channel samples
399 are to be written.
400 */
401 ___DSP_DUAL_16BIT_ALLOC(
402 left_chan_base_IO_addr,
403 right_chan_IO_disp
404 )
405
406
407 /* Init: 0x0080:0004 for non-AC-97
408 Init: 0x0080:0000 for AC-97
409 hi: Exponential volume change rate
410 for input stream
411 lo: Positive shift count to shift the
412 16-bit input sample to obtain the
413 32-bit output word
414 */
415 ___DSP_DUAL_16BIT_ALLOC(
416 CO_scale_shift_count,
417 CO_exp_vol_change_rate
418 )
419
420 /* Pointer to SCB at end of input chain */
421 ___DSP_DUAL_16BIT_ALLOC(
422 reserved,
423 last_sub_ptr
424 )
425} codec_output_scb_t;
426
427/* SCB for CODEC input algorithm */
428typedef struct _codec_input_scb_t {
429 /* First 13 dwords from generic_scb_t */
430 basic_dma_req_t basic_req; /* Optional */
431 scatter_gather_ext_t sg_ext; /* Optional */
432 ___DSP_DUAL_16BIT_ALLOC(
433 next_scb, /* REQUIRED */
434 sub_list_ptr /* REQUIRED */
435 )
436
437 ___DSP_DUAL_16BIT_ALLOC(
438 entry_point, /* REQUIRED */
439 this_spb /* REQUIRED */
440 )
441
442 u32 strm_rs_config; /* REQUIRED */
443 u32 strm_buf_ptr; /* REQUIRED */
444
445 /* NOTE: The CODEC input task reads samples from the hardware FIFO
446 sublist at the DMA source address word (sub_list_ptr->basic_req.saw).
447 After the required number of samples is transferred, the CODEC
448 output task advances sub_list_ptr->basic_req.saw past the samples
449 consumed. SPuD must initialize the sub_list_ptr->basic_req.saw
450 to point half-way around from the initial sub_list_ptr->strm_nuf_ptr
451 to allow for lag/lead.
452 */
453
454 /* Init. 0000:0010 for SDout
455 0060:0010 for SDout2
456 0080:0010 for SDout3
457 hi: Base IO address of FIFO to which
458 the left-channel samples are to
459 be written.
460 lo: Displacement for the base IO
461 address for left-channel to obtain
462 the base IO address for the FIFO
463 to which the right-channel samples
464 are to be written.
465 */
466 ___DSP_DUAL_16BIT_ALLOC(
467 rightChanINdisp,
468 left_chan_base_IN_addr
469 )
470 /* Init. ?:fffc
471 lo: Negative shift count to shift the
472 32-bit input dword to obtain the
473 16-bit sample msb-aligned (count
474 is negative to shift left)
475 */
476 ___DSP_DUAL_16BIT_ALLOC(
477 scaleShiftCount,
478 reserver1
479 )
480
481 u32 reserved2;
482} codec_input_scb_t;
483
484
485typedef struct _pcm_serial_input_scb_t {
486 /* First 13 dwords from generic_scb_t */
487 basic_dma_req_t basic_req; /* Optional */
488 scatter_gather_ext_t sg_ext; /* Optional */
489 ___DSP_DUAL_16BIT_ALLOC(
490 next_scb, /* REQUIRED */
491 sub_list_ptr /* REQUIRED */
492 )
493
494 ___DSP_DUAL_16BIT_ALLOC(
495 entry_point, /* REQUIRED */
496 this_spb /* REQUIRED */
497 )
498
499 u32 strm_buf_ptr; /* REQUIRED */
500 u32 strm_rs_config; /* REQUIRED */
501
502 /* Init. Ptr to CODEC input SCB
503 hi: Pointer to the SCB containing the
504 input buffer to which CODEC input
505 samples are written
506 lo: Flag indicating the link to the CODEC
507 input task is to be initialized
508 */
509 ___DSP_DUAL_16BIT_ALLOC(
510 init_codec_input_link,
511 codec_input_buf_scb
512 )
513
514 /* Initialized by the host (host updates target volumes) */
515 volume_control_t psi_vol_ctrl;
516
517} pcm_serial_input_scb_t;
518
519typedef struct _src_task_scb_t {
520 ___DSP_DUAL_16BIT_ALLOC(
521 frames_left_in_gof,
522 gofs_left_in_sec
523 )
524
525 ___DSP_DUAL_16BIT_ALLOC(
526 const2_thirds,
527 num_extra_tnput_samples
528 )
529
530 ___DSP_DUAL_16BIT_ALLOC(
531 cor_per_gof,
532 correction_per_sec
533 )
534
535 ___DSP_DUAL_16BIT_ALLOC(
536 output_buf_producer_ptr,
537 junk_DMA_MID
538 )
539
540 ___DSP_DUAL_16BIT_ALLOC(
541 gof_length,
542 gofs_per_sec
543 )
544
545 u32 input_buf_strm_config;
546
547 ___DSP_DUAL_16BIT_ALLOC(
548 reserved_for_SRC_use,
549 input_buf_consumer_ptr
550 )
551
552 u32 accum_phi;
553
554 ___DSP_DUAL_16BIT_ALLOC(
555 exp_src_vol_change_rate,
556 input_buf_producer_ptr
557 )
558
559 ___DSP_DUAL_16BIT_ALLOC(
560 src_next_scb,
561 src_sub_list_ptr
562 )
563
564 ___DSP_DUAL_16BIT_ALLOC(
565 src_entry_point,
566 src_this_sbp
567 )
568
569 u32 src_strm_rs_config;
570 u32 src_strm_buf_ptr;
571
572 u32 phiIncr6int_26frac;
573
574 volume_control_t src_vol_ctrl;
575} src_task_scb_t;
576
577typedef struct _decimate_by_pow2_scb_t {
578 /* decimationFactor = 2, 4, or 8 (larger factors waste too much memory
579 when compared to cascading decimators)
580 */
581 ___DSP_DUAL_16BIT_ALLOC(
582 dec2_coef_base_ptr,
583 dec2_coef_increment
584 )
585
586 /* coefIncrement = 128 / decimationFactor (for our ROM filter)
587 coefBasePtr = 0x8000 (for our ROM filter)
588 */
589 ___DSP_DUAL_16BIT_ALLOC(
590 dec2_in_samples_per_out_triplet,
591 dec2_extra_in_samples
592 )
593 /* extraInSamples: # of accumulated, unused input samples (init. to 0)
594 inSamplesPerOutTriplet = 3 * decimationFactor
595 */
596
597 ___DSP_DUAL_16BIT_ALLOC(
598 dec2_const2_thirds,
599 dec2_half_num_taps_mp5
600 )
601 /* halfNumTapsM5: (1/2 number of taps in decimation filter) minus 5
602 const2thirds: constant 2/3 in 16Q0 format (sign.15)
603 */
604
605 ___DSP_DUAL_16BIT_ALLOC(
606 dec2_output_buf_producer_ptr,
607 dec2_junkdma_mid
608 )
609
610 u32 dec2_reserved2;
611
612 u32 dec2_input_nuf_strm_config;
613 /* inputBufStrmConfig: rsConfig for the input buffer to the decimator
614 (buffer size = decimationFactor * 32 dwords)
615 */
616
617 ___DSP_DUAL_16BIT_ALLOC(
618 dec2_phi_incr,
619 dec2_input_buf_consumer_ptr
620 )
621 /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter)
622 phiIncr = decimationFactor * 4
623 */
624
625 u32 dec2_reserved3;
626
627 ___DSP_DUAL_16BIT_ALLOC(
628 dec2_exp_vol_change_rate,
629 dec2_input_buf_producer_ptr
630 )
631 /* inputBufProducerPtr: Input buffer write pointer
632 expVolChangeRate: Exponential volume change rate for possible
633 future mixer on input streams
634 */
635
636 ___DSP_DUAL_16BIT_ALLOC(
637 dec2_next_scb,
638 dec2_sub_list_ptr
639 )
640
641 ___DSP_DUAL_16BIT_ALLOC(
642 dec2_entry_point,
643 dec2_this_spb
644 )
645
646 u32 dec2_strm_rs_config;
647 u32 dec2_strm_buf_ptr;
648
649 u32 dec2_reserved4;
650
651 volume_control_t dec2_vol_ctrl; /* Not used! */
652} decimate_by_pow2_scb_t;
653
654typedef struct _vari_decimate_scb_t {
655 ___DSP_DUAL_16BIT_ALLOC(
656 vdec_frames_left_in_gof,
657 vdec_gofs_left_in_sec
658 )
659
660 ___DSP_DUAL_16BIT_ALLOC(
661 vdec_const2_thirds,
662 vdec_extra_in_samples
663 )
664 /* extraInSamples: # of accumulated, unused input samples (init. to 0)
665 const2thirds: constant 2/3 in 16Q0 format (sign.15) */
666
667 ___DSP_DUAL_16BIT_ALLOC(
668 vdec_cor_per_gof,
669 vdec_correction_per_sec
670 )
671
672 ___DSP_DUAL_16BIT_ALLOC(
673 vdec_output_buf_producer_ptr,
674 vdec_input_buf_consumer_ptr
675 )
676 /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter) */
677 ___DSP_DUAL_16BIT_ALLOC(
678 vdec_gof_length,
679 vdec_gofs_per_sec
680 )
681
682 u32 vdec_input_buf_strm_config;
683 /* inputBufStrmConfig: rsConfig for the input buffer to the decimator
684 (buffer size = 64 dwords) */
685 u32 vdec_coef_increment;
686 /* coefIncrement = - 128.0 / decimationFactor (as a 32Q15 number) */
687
688 u32 vdec_accumphi;
689 /* accumPhi: accumulated fractional phase increment (6.26) */
690
691 ___DSP_DUAL_16BIT_ALLOC(
692 vdec_exp_vol_change_rate,
693 vdec_input_buf_producer_ptr
694 )
695 /* inputBufProducerPtr: Input buffer write pointer
696 expVolChangeRate: Exponential volume change rate for possible
697 future mixer on input streams */
698
699 ___DSP_DUAL_16BIT_ALLOC(
700 vdec_next_scb,
701 vdec_sub_list_ptr
702 )
703
704 ___DSP_DUAL_16BIT_ALLOC(
705 vdec_entry_point,
706 vdec_this_spb
707 )
708
709 u32 vdec_strm_rs_config;
710 u32 vdec_strm_buf_ptr;
711
712 u32 vdec_phi_incr_6int_26frac;
713
714 volume_control_t vdec_vol_ctrl;
715} vari_decimate_scb_t;
716
717
718/* SCB for MIX_TO_OSTREAM algorithm family */
719typedef struct _mix2_ostream_scb_t {
720 /* First 13 dwords from generic_scb_t */
721 basic_dma_req_t basic_req; /* Optional */
722 scatter_gather_ext_t sg_ext; /* Optional */
723 ___DSP_DUAL_16BIT_ALLOC(
724 next_scb, /* REQUIRED */
725 sub_list_ptr /* REQUIRED */
726 )
727
728 ___DSP_DUAL_16BIT_ALLOC(
729 entry_point, /* REQUIRED */
730 this_spb /* REQUIRED */
731 )
732
733 u32 strm_rs_config; /* REQUIRED */
734 u32 strm_buf_ptr; /* REQUIRED */
735
736
737 /* hi: Number of mixed-down input triplets
738 computed since start of group
739 lo: Number of frames remaining to be
740 processed in the current group of
741 frames
742 */
743 ___DSP_DUAL_16BIT_ALLOC(
744 frames_left_in_group,
745 accum_input_triplets
746 )
747
748 /* hi: Exponential volume change rate
749 for mixer on input streams
750 lo: Number of frames in the group
751 */
752 ___DSP_DUAL_16BIT_ALLOC(
753 frame_group_length,
754 exp_vol_change_rate
755 )
756
757 ___DSP_DUAL_16BIT_ALLOC(
758 const_FFFF,
759 const_zero
760 )
761} mix2_ostream_scb_t;
762
763
764/* SCB for S16_MIX algorithm */
765typedef struct _mix_only_scb_t {
766 /* First 13 dwords from generic_scb_t */
767 basic_dma_req_t basic_req; /* Optional */
768 scatter_gather_ext_t sg_ext; /* Optional */
769 ___DSP_DUAL_16BIT_ALLOC(
770 next_scb, /* REQUIRED */
771 sub_list_ptr /* REQUIRED */
772 )
773
774 ___DSP_DUAL_16BIT_ALLOC(
775 entry_point, /* REQUIRED */
776 this_spb /* REQUIRED */
777 )
778
779 u32 strm_rs_config; /* REQUIRED */
780 u32 strm_buf_ptr; /* REQUIRED */
781
782 u32 reserved;
783 volume_control_t vol_ctrl;
784} mix_only_scb_t;
785
786/* SCB for the async. CODEC input algorithm */
787typedef struct _async_codec_input_scb_t {
788 u32 io_free2;
789
790 u32 io_current_total;
791 u32 io_previous_total;
792
793 u16 io_count;
794 u16 io_count_limit;
795
796 u16 o_fifo_base_addr;
797 u16 ost_mo_format;
798 /* 1 = stereo; 0 = mono
799 xxx for ASER 1 (not allowed); 118 for ASER2 */
800
801 u32 ostrm_rs_config;
802 u32 ostrm_buf_ptr;
803
804 ___DSP_DUAL_16BIT_ALLOC(
805 io_sclks_per_lr_clk,
806 io_io_enable
807 )
808
809 u32 io_free4;
810
811 ___DSP_DUAL_16BIT_ALLOC(
812 io_next_scb,
813 io_sub_list_ptr
814 )
815
816 ___DSP_DUAL_16BIT_ALLOC(
817 io_entry_point,
818 io_this_spb
819 )
820
821 u32 istrm_rs_config;
822 u32 istrm_buf_ptr;
823
824 /* Init. 0000:8042: for ASER1
825 0000:8044: for ASER2 */
826 ___DSP_DUAL_16BIT_ALLOC(
827 io_stat_reg_addr,
828 iofifo_pointer
829 )
830
831 /* Init 1 stero:100 ASER1
832 Init 0 mono:110 ASER2
833 */
834 ___DSP_DUAL_16BIT_ALLOC(
835 ififo_base_addr,
836 ist_mo_format
837 )
838
839 u32 i_free;
840} async_codec_input_scb_t;
841
842
843/* SCB for the SP/DIF CODEC input and output */
844typedef struct _spdifiscb_t {
845 ___DSP_DUAL_16BIT_ALLOC(
846 status_ptr,
847 status_start_ptr
848 )
849
850 u32 current_total;
851 u32 previous_total;
852
853 ___DSP_DUAL_16BIT_ALLOC(
854 count,
855 count_limit
856 )
857
858 u32 status_data;
859
860 ___DSP_DUAL_16BIT_ALLOC(
861 status,
862 free4
863 )
864
865 u32 free3;
866
867 ___DSP_DUAL_16BIT_ALLOC(
868 free2,
869 bit_count
870 )
871
872 u32 temp_status;
873
874 ___DSP_DUAL_16BIT_ALLOC(
875 next_SCB,
876 sub_list_ptr
877 )
878
879 ___DSP_DUAL_16BIT_ALLOC(
880 entry_point,
881 this_spb
882 )
883
884 u32 strm_rs_config;
885 u32 strm_buf_ptr;
886
887 ___DSP_DUAL_16BIT_ALLOC(
888 stat_reg_addr,
889 fifo_pointer
890 )
891
892 ___DSP_DUAL_16BIT_ALLOC(
893 fifo_base_addr,
894 st_mo_format
895 )
896
897 u32 free1;
898} spdifiscb_t;
899
900
901/* SCB for the SP/DIF CODEC input and output */
902typedef struct _spdifoscb_t {
903
904
905 u32 free2;
906
907 u32 free3[4];
908
909 /* Need to be here for compatibility with AsynchFGTxCode */
910 u32 strm_rs_config;
911
912 u32 strm_buf_ptr;
913
914 ___DSP_DUAL_16BIT_ALLOC(
915 status,
916 free5
917 )
918
919 u32 free4;
920
921 ___DSP_DUAL_16BIT_ALLOC(
922 next_scb,
923 sub_list_ptr
924 )
925
926 ___DSP_DUAL_16BIT_ALLOC(
927 entry_point,
928 this_spb
929 )
930
931 u32 free6[2];
932
933 ___DSP_DUAL_16BIT_ALLOC(
934 stat_reg_addr,
935 fifo_pointer
936 )
937
938 ___DSP_DUAL_16BIT_ALLOC(
939 fifo_base_addr,
940 st_mo_format
941 )
942
943 u32 free1;
944} spdifoscb_t;
945
946
947
948typedef struct _asynch_fg_rx_scb_t {
949 ___DSP_DUAL_16BIT_ALLOC(
950 bot_buf_mask,
951 buf_Mask
952 )
953
954 ___DSP_DUAL_16BIT_ALLOC(
955 max,
956 min
957 )
958
959 ___DSP_DUAL_16BIT_ALLOC(
960 old_producer_pointer,
961 hfg_scb_ptr
962 )
963
964 ___DSP_DUAL_16BIT_ALLOC(
965 delta,
966 adjust_count
967 )
968
969 u32 unused2[5];
970
971 ___DSP_DUAL_16BIT_ALLOC(
972 sibling_ptr,
973 child_ptr
974 )
975
976 ___DSP_DUAL_16BIT_ALLOC(
977 code_ptr,
978 this_ptr
979 )
980
981 u32 strm_rs_config;
982
983 u32 strm_buf_ptr;
984
985 u32 unused_phi_incr;
986
987 ___DSP_DUAL_16BIT_ALLOC(
988 right_targ,
989 left_targ
990 )
991
992 ___DSP_DUAL_16BIT_ALLOC(
993 right_vol,
994 left_vol
995 )
996} asynch_fg_rx_scb_t;
997
998
999
1000typedef struct _asynch_fg_tx_scb_t {
1001 ___DSP_DUAL_16BIT_ALLOC(
1002 not_buf_mask,
1003 buf_mask
1004 )
1005
1006 ___DSP_DUAL_16BIT_ALLOC(
1007 max,
1008 min
1009 )
1010
1011 ___DSP_DUAL_16BIT_ALLOC(
1012 unused1,
1013 hfg_scb_ptr
1014 )
1015
1016 ___DSP_DUAL_16BIT_ALLOC(
1017 delta,
1018 adjust_count
1019 )
1020
1021 u32 accum_phi;
1022
1023 ___DSP_DUAL_16BIT_ALLOC(
1024 unused2,
1025 const_one_third
1026 )
1027
1028 u32 unused3[3];
1029
1030 ___DSP_DUAL_16BIT_ALLOC(
1031 sibling_ptr,
1032 child_ptr
1033 )
1034
1035 ___DSP_DUAL_16BIT_ALLOC(
1036 codePtr,
1037 this_ptr
1038 )
1039
1040 u32 strm_rs_config;
1041
1042 u32 strm_buf_ptr;
1043
1044 u32 phi_incr;
1045
1046 ___DSP_DUAL_16BIT_ALLOC(
1047 unused_right_targ,
1048 unused_left_targ
1049 )
1050
1051 ___DSP_DUAL_16BIT_ALLOC(
1052 unused_right_vol,
1053 unused_left_vol
1054 )
1055} asynch_fg_tx_scb_t;
1056
1057
1058typedef struct _output_snoop_scb_t {
1059 /* First 13 dwords from generic_scb_t */
1060 basic_dma_req_t basic_req; /* Optional */
1061 scatter_gather_ext_t sg_ext; /* Optional */
1062 ___DSP_DUAL_16BIT_ALLOC(
1063 next_scb, /* REQUIRED */
1064 sub_list_ptr /* REQUIRED */
1065 )
1066
1067 ___DSP_DUAL_16BIT_ALLOC(
1068 entry_point, /* REQUIRED */
1069 this_spb /* REQUIRED */
1070 )
1071
1072 u32 strm_rs_config; /* REQUIRED */
1073 u32 strm_buf_ptr; /* REQUIRED */
1074
1075 ___DSP_DUAL_16BIT_ALLOC(
1076 init_snoop_input_link,
1077 snoop_child_input_scb
1078 )
1079
1080 u32 snoop_input_buf_ptr;
1081
1082 ___DSP_DUAL_16BIT_ALLOC(
1083 reserved,
1084 input_scb
1085 )
1086} output_snoop_scb_t;
1087
1088typedef struct _spio_write_scb_t {
1089 ___DSP_DUAL_16BIT_ALLOC(
1090 address1,
1091 address2
1092 )
1093
1094 u32 data1;
1095
1096 u32 data2;
1097
1098 ___DSP_DUAL_16BIT_ALLOC(
1099 address3,
1100 address4
1101 )
1102
1103 u32 data3;
1104
1105 u32 data4;
1106
1107 ___DSP_DUAL_16BIT_ALLOC(
1108 unused1,
1109 data_ptr
1110 )
1111
1112 u32 unused2[2];
1113
1114 ___DSP_DUAL_16BIT_ALLOC(
1115 sibling_ptr,
1116 child_ptr
1117 )
1118
1119 ___DSP_DUAL_16BIT_ALLOC(
1120 entry_point,
1121 this_ptr
1122 )
1123
1124 u32 unused3[5];
1125} spio_write_scb_t;
1126
1127typedef struct _magic_snoop_task_t {
1128 u32 i0;
1129 u32 i1;
1130
1131 u32 strm_buf_ptr1;
1132
1133 u16 i2;
1134 u16 snoop_scb;
1135
1136 u32 i3;
1137 u32 i4;
1138 u32 i5;
1139 u32 i6;
1140
1141 u32 i7;
1142
1143 ___DSP_DUAL_16BIT_ALLOC(
1144 next_scb,
1145 sub_list_ptr
1146 )
1147
1148 ___DSP_DUAL_16BIT_ALLOC(
1149 entry_point,
1150 this_ptr
1151 )
1152
1153 u32 strm_buf_config;
1154 u32 strm_buf_ptr2;
1155
1156 u32 i8;
1157
1158 volume_control_t vdec_vol_ctrl;
1159} magic_snoop_task_t;
1160
1161
1162typedef struct _filter_scb_t {
1163 ___DSP_DUAL_16BIT_ALLOC(
1164 a0_right, /* 0x00 */
1165 a0_left
1166 )
1167 ___DSP_DUAL_16BIT_ALLOC(
1168 a1_right, /* 0x01 */
1169 a1_left
1170 )
1171 ___DSP_DUAL_16BIT_ALLOC(
1172 a2_right, /* 0x02 */
1173 a2_left
1174 )
1175 ___DSP_DUAL_16BIT_ALLOC(
1176 output_buf_ptr, /* 0x03 */
1177 init
1178 )
1179
1180 ___DSP_DUAL_16BIT_ALLOC(
1181 filter_unused3, /* 0x04 */
1182 filter_unused2
1183 )
1184
1185 u32 prev_sample_output1; /* 0x05 */
1186 u32 prev_sample_output2; /* 0x06 */
1187 u32 prev_sample_input1; /* 0x07 */
1188 u32 prev_sample_input2; /* 0x08 */
1189
1190 ___DSP_DUAL_16BIT_ALLOC(
1191 next_scb_ptr, /* 0x09 */
1192 sub_list_ptr
1193 )
1194
1195 ___DSP_DUAL_16BIT_ALLOC(
1196 entry_point, /* 0x0A */
1197 spb_ptr
1198 )
1199
1200 u32 strm_rs_config; /* 0x0B */
1201 u32 strm_buf_ptr; /* 0x0C */
1202
1203 ___DSP_DUAL_16BIT_ALLOC(
1204 b0_right, /* 0x0D */
1205 b0_left
1206 )
1207 ___DSP_DUAL_16BIT_ALLOC(
1208 b1_right, /* 0x0E */
1209 b1_left
1210 )
1211 ___DSP_DUAL_16BIT_ALLOC(
1212 b2_right, /* 0x0F */
1213 b2_left
1214 )
1215} filter_scb_t;
1216#endif /* __DSP_SCB_TYPES_H__ */
diff --git a/include/sound/cs46xx_dsp_spos.h b/include/sound/cs46xx_dsp_spos.h
new file mode 100644
index 000000000000..10014cb62423
--- /dev/null
+++ b/include/sound/cs46xx_dsp_spos.h
@@ -0,0 +1,233 @@
1/*
2 * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#ifndef __CS46XX_DSP_SPOS_H__
23#define __CS46XX_DSP_SPOS_H__
24
25#include "cs46xx_dsp_scb_types.h"
26#include "cs46xx_dsp_task_types.h"
27
28#define SYMBOL_CONSTANT 0x0
29#define SYMBOL_SAMPLE 0x1
30#define SYMBOL_PARAMETER 0x2
31#define SYMBOL_CODE 0x3
32
33#define SEGTYPE_SP_PROGRAM 0x00000001
34#define SEGTYPE_SP_PARAMETER 0x00000002
35#define SEGTYPE_SP_SAMPLE 0x00000003
36#define SEGTYPE_SP_COEFFICIENT 0x00000004
37
38#define DSP_SPOS_UU 0x0deadul /* unused */
39#define DSP_SPOS_DC 0x0badul /* don't care */
40#define DSP_SPOS_DC_DC 0x0bad0badul /* don't care */
41#define DSP_SPOS_UUUU 0xdeadc0edul /* unused */
42#define DSP_SPOS_UUHI 0xdeadul
43#define DSP_SPOS_UULO 0xc0edul
44#define DSP_SPOS_DCDC 0x0badf1d0ul /* don't care */
45#define DSP_SPOS_DCDCHI 0x0badul
46#define DSP_SPOS_DCDCLO 0xf1d0ul
47
48#define DSP_MAX_TASK_NAME 60
49#define DSP_MAX_SYMBOL_NAME 100
50#define DSP_MAX_SCB_NAME 60
51#define DSP_MAX_SCB_DESC 200
52#define DSP_MAX_TASK_DESC 50
53
54#define DSP_MAX_PCM_CHANNELS 32
55#define DSP_MAX_SRC_NR 14
56
57#define DSP_PCM_MAIN_CHANNEL 1
58#define DSP_PCM_REAR_CHANNEL 2
59#define DSP_PCM_CENTER_LFE_CHANNEL 3
60#define DSP_PCM_S71_CHANNEL 4 /* surround 7.1 */
61#define DSP_IEC958_CHANNEL 5
62
63#define DSP_SPDIF_STATUS_OUTPUT_ENABLED 1
64#define DSP_SPDIF_STATUS_PLAYBACK_OPEN 2
65#define DSP_SPDIF_STATUS_HW_ENABLED 4
66#define DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED 8
67
68struct _dsp_module_desc_t;
69
70typedef struct _symbol_entry_t {
71 u32 address;
72 char symbol_name[DSP_MAX_SYMBOL_NAME];
73 int symbol_type;
74
75 /* initialized by driver */
76 struct _dsp_module_desc_t * module;
77 int deleted;
78} symbol_entry_t;
79
80typedef struct _symbol_desc_t {
81 int nsymbols;
82
83 symbol_entry_t * symbols;
84
85 /* initialized by driver */
86 int highest_frag_index;
87} symbol_desc_t;
88
89
90typedef struct _segment_desc_t {
91 int segment_type;
92 u32 offset;
93 u32 size;
94 u32 * data;
95} segment_desc_t;
96
97typedef struct _dsp_module_desc_t {
98 char * module_name;
99 symbol_desc_t symbol_table;
100 int nsegments;
101 segment_desc_t * segments;
102
103 /* initialized by driver */
104 u32 overlay_begin_address;
105 u32 load_address;
106 int nfixups;
107} dsp_module_desc_t;
108
109typedef struct _dsp_scb_descriptor_t {
110 char scb_name[DSP_MAX_SCB_NAME];
111 u32 address;
112 int index;
113
114 struct _dsp_scb_descriptor_t * sub_list_ptr;
115 struct _dsp_scb_descriptor_t * next_scb_ptr;
116 struct _dsp_scb_descriptor_t * parent_scb_ptr;
117
118 symbol_entry_t * task_entry;
119 symbol_entry_t * scb_symbol;
120
121 snd_info_entry_t *proc_info;
122 int ref_count;
123 spinlock_t lock;
124
125 int deleted;
126} dsp_scb_descriptor_t;
127
128typedef struct _dsp_task_descriptor_t {
129 char task_name[DSP_MAX_TASK_NAME];
130 int size;
131 u32 address;
132 int index;
133} dsp_task_descriptor_t;
134
135typedef struct _pcm_channel_descriptor_t {
136 int active;
137 int src_slot;
138 int pcm_slot;
139 u32 sample_rate;
140 u32 unlinked;
141 dsp_scb_descriptor_t * pcm_reader_scb;
142 dsp_scb_descriptor_t * src_scb;
143 dsp_scb_descriptor_t * mixer_scb;
144
145 void * private_data;
146} pcm_channel_descriptor_t;
147
148typedef struct _dsp_spos_instance_t {
149 symbol_desc_t symbol_table; /* currently availble loaded symbols in SP */
150
151 int nmodules;
152 dsp_module_desc_t * modules; /* modules loaded into SP */
153
154 segment_desc_t code;
155
156 /* Main PCM playback mixer */
157 dsp_scb_descriptor_t * master_mix_scb;
158 u16 dac_volume_right;
159 u16 dac_volume_left;
160
161 /* Rear/surround PCM playback mixer */
162 dsp_scb_descriptor_t * rear_mix_scb;
163
164 /* Center/LFE mixer */
165 dsp_scb_descriptor_t * center_lfe_mix_scb;
166
167 int npcm_channels;
168 int nsrc_scb;
169 pcm_channel_descriptor_t pcm_channels[DSP_MAX_PCM_CHANNELS];
170 int src_scb_slots[DSP_MAX_SRC_NR];
171
172 /* cache this symbols */
173 symbol_entry_t * null_algorithm; /* used by PCMreaderSCB's */
174 symbol_entry_t * s16_up; /* used by SRCtaskSCB's */
175
176 /* proc fs */
177 snd_card_t * snd_card;
178 snd_info_entry_t * proc_dsp_dir;
179 snd_info_entry_t * proc_sym_info_entry;
180 snd_info_entry_t * proc_modules_info_entry;
181 snd_info_entry_t * proc_parameter_dump_info_entry;
182 snd_info_entry_t * proc_sample_dump_info_entry;
183
184 /* SCB's descriptors */
185 int nscb;
186 int scb_highest_frag_index;
187 dsp_scb_descriptor_t scbs[DSP_MAX_SCB_DESC];
188 snd_info_entry_t * proc_scb_info_entry;
189 dsp_scb_descriptor_t * the_null_scb;
190
191 /* Task's descriptors */
192 int ntask;
193 dsp_task_descriptor_t tasks[DSP_MAX_TASK_DESC];
194 snd_info_entry_t * proc_task_info_entry;
195
196 /* SPDIF status */
197 int spdif_status_out;
198 int spdif_status_in;
199 u16 spdif_input_volume_right;
200 u16 spdif_input_volume_left;
201 /* spdif channel status,
202 left right and user validity bits */
203 unsigned int spdif_csuv_default;
204 unsigned int spdif_csuv_stream;
205
206 /* SPDIF input sample rate converter */
207 dsp_scb_descriptor_t * spdif_in_src;
208 /* SPDIF input asynch. receiver */
209 dsp_scb_descriptor_t * asynch_rx_scb;
210
211 /* Capture record mixer SCB */
212 dsp_scb_descriptor_t * record_mixer_scb;
213
214 /* CODEC input SCB */
215 dsp_scb_descriptor_t * codec_in_scb;
216
217 /* reference snooper */
218 dsp_scb_descriptor_t * ref_snoop_scb;
219
220 /* SPDIF output PCM reference */
221 dsp_scb_descriptor_t * spdif_pcm_input_scb;
222
223 /* asynch TX task */
224 dsp_scb_descriptor_t * asynch_tx_scb;
225
226 /* record sources */
227 dsp_scb_descriptor_t * pcm_input;
228 dsp_scb_descriptor_t * adc_input;
229
230 int spdif_in_sample_rate;
231} dsp_spos_instance_t;
232
233#endif /* __DSP_SPOS_H__ */
diff --git a/include/sound/cs46xx_dsp_task_types.h b/include/sound/cs46xx_dsp_task_types.h
new file mode 100644
index 000000000000..5dd3bf69cb03
--- /dev/null
+++ b/include/sound/cs46xx_dsp_task_types.h
@@ -0,0 +1,253 @@
1/*
2 * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 *
21 * NOTE: comments are copy/paste from cwcemb80.lst
22 * provided by Tom Woller at Cirrus (my only
23 * documentation about the SP OS running inside
24 * the DSP)
25 */
26
27#ifndef __CS46XX_DSP_TASK_TYPES_H__
28#define __CS46XX_DSP_TASK_TYPES_H__
29
30#include "cs46xx_dsp_scb_types.h"
31
32/*********************************************************************************************
33Example hierarchy of stream control blocks in the SP
34
35hfgTree
36Ptr____Call (c)
37 \
38 -------+------ ------------- ------------- ------------- -----
39| SBlaster IF |______\| Foreground |___\| Middlegr'nd |___\| Background |___\| Nul |
40| |Goto /| tree header |g /| tree header |g /| tree header |g /| SCB |r
41 -------------- (g) ------------- ------------- ------------- -----
42 |c |c |c |c
43 | | | |
44 \/ ------------- ------------- -------------
45 | Foreground |_\ | Middlegr'nd |_\ | Background |_\
46 | tree |g/ | tree |g/ | tree |g/
47 ------------- ------------- -------------
48 |c |c |c
49 | | |
50 \/ \/ \/
51
52*********************************************************************************************/
53
54#define HFG_FIRST_EXECUTE_MODE 0x0001
55#define HFG_FIRST_EXECUTE_MODE_BIT 0
56#define HFG_CONTEXT_SWITCH_MODE 0x0002
57#define HFG_CONTEXT_SWITCH_MODE_BIT 1
58
59#define MAX_FG_STACK_SIZE 32 /* THESE NEED TO BE COMPUTED PROPERLY */
60#define MAX_MG_STACK_SIZE 16
61#define MAX_BG_STACK_SIZE 9
62#define MAX_HFG_STACK_SIZE 4
63
64#define SLEEP_ACTIVE_INCREMENT 0 /* Enable task tree thread to go to sleep
65 This should only ever be used on the Background thread */
66#define STANDARD_ACTIVE_INCREMENT 1 /* Task tree thread normal operation */
67#define SUSPEND_ACTIVE_INCREMENT 2 /* Cause execution to suspend in the task tree thread
68 This should only ever be used on the Background thread */
69
70#define HOSTFLAGS_DISABLE_BG_SLEEP 0 /* Host-controlled flag that determines whether we go to sleep
71 at the end of BG */
72
73/* Minimal context save area for Hyper Forground */
74typedef struct _hf_save_area_t {
75 u32 r10_save;
76 u32 r54_save;
77 u32 r98_save;
78
79 ___DSP_DUAL_16BIT_ALLOC(
80 status_save,
81 ind_save
82 )
83
84 ___DSP_DUAL_16BIT_ALLOC(
85 rci1_save,
86 rci0_save
87 )
88
89 u32 r32_save;
90 u32 r76_save;
91 u32 rsd2_save;
92
93 ___DSP_DUAL_16BIT_ALLOC(
94 rsi2_save, /* See TaskTreeParameterBlock for
95 remainder of registers */
96 rsa2Save
97 )
98 /* saved as part of HFG context */
99} hf_save_area_t;
100
101
102/* Task link data structure */
103typedef struct _tree_link_t {
104 ___DSP_DUAL_16BIT_ALLOC(
105 /* Pointer to sibling task control block */
106 next_scb,
107 /* Pointer to child task control block */
108 sub_ptr
109 )
110
111 ___DSP_DUAL_16BIT_ALLOC(
112 /* Pointer to code entry point */
113 entry_point,
114 /* Pointer to local data */
115 this_spb
116 )
117} tree_link_t;
118
119
120typedef struct _task_tree_data_t {
121 ___DSP_DUAL_16BIT_ALLOC(
122 /* Initial tock count; controls task tree execution rate */
123 tock_count_limit,
124 /* Tock down counter */
125 tock_count
126 )
127
128 /* Add to ActiveCount when TockCountLimit reached:
129 Subtract on task tree termination */
130 ___DSP_DUAL_16BIT_ALLOC(
131 active_tncrement,
132 /* Number of pending activations for task tree */
133 active_count
134 )
135
136 ___DSP_DUAL_16BIT_ALLOC(
137 /* BitNumber to enable modification of correct bit in ActiveTaskFlags */
138 active_bit,
139 /* Pointer to OS location for indicating current activity on task level */
140 active_task_flags_ptr
141 )
142
143 /* Data structure for controlling movement of memory blocks:-
144 currently unused */
145 ___DSP_DUAL_16BIT_ALLOC(
146 mem_upd_ptr,
147 /* Data structure for controlling synchronous link update */
148 link_upd_ptr
149 )
150
151 ___DSP_DUAL_16BIT_ALLOC(
152 /* Save area for remainder of full context. */
153 save_area,
154 /* Address of start of local stack for data storage */
155 data_stack_base_ptr
156 )
157
158} task_tree_data_t;
159
160
161
162typedef struct _interval_timer_data_t
163{
164 /* These data items have the same relative locations to those */
165 ___DSP_DUAL_16BIT_ALLOC(
166 interval_timer_period,
167 itd_unused
168 )
169
170 /* used for this data in the SPOS control block for SPOS 1.0 */
171 ___DSP_DUAL_16BIT_ALLOC(
172 num_FG_ticks_this_interval,
173 num_intervals
174 )
175} interval_timer_data_t;
176
177
178/* This structure contains extra storage for the task tree
179 Currently, this additional data is related only to a full context save */
180typedef struct _task_tree_context_block_t {
181 /* Up to 10 values are saved onto the stack. 8 for the task tree, 1 for
182 The access to the context switch (call or interrupt), and 1 spare that
183 users should never use. This last may be required by the system */
184 ___DSP_DUAL_16BIT_ALLOC(
185 stack1,
186 stack0
187 )
188 ___DSP_DUAL_16BIT_ALLOC(
189 stack3,
190 stack2
191 )
192 ___DSP_DUAL_16BIT_ALLOC(
193 stack5,
194 stack4
195 )
196 ___DSP_DUAL_16BIT_ALLOC(
197 stack7,
198 stack6
199 )
200 ___DSP_DUAL_16BIT_ALLOC(
201 stack9,
202 stack8
203 )
204
205 u32 saverfe;
206
207 /* Value may be overwriten by stack save algorithm.
208 Retain the size of the stack data saved here if used */
209 ___DSP_DUAL_16BIT_ALLOC(
210 reserved1,
211 stack_size
212 )
213 u32 saverba; /* (HFG) */
214 u32 saverdc;
215 u32 savers_config_23; /* (HFG) */
216 u32 savers_DMA23; /* (HFG) */
217 u32 saversa0;
218 u32 saversi0;
219 u32 saversa1;
220 u32 saversi1;
221 u32 saversa3;
222 u32 saversd0;
223 u32 saversd1;
224 u32 saversd3;
225 u32 savers_config01;
226 u32 savers_DMA01;
227 u32 saveacc0hl;
228 u32 saveacc1hl;
229 u32 saveacc0xacc1x;
230 u32 saveacc2hl;
231 u32 saveacc3hl;
232 u32 saveacc2xacc3x;
233 u32 saveaux0hl;
234 u32 saveaux1hl;
235 u32 saveaux0xaux1x;
236 u32 saveaux2hl;
237 u32 saveaux3hl;
238 u32 saveaux2xaux3x;
239 u32 savershouthl;
240 u32 savershoutxmacmode;
241} task_tree_context_block_t;
242
243
244typedef struct _task_tree_control_block_t {
245 hf_save_area_t context;
246 tree_link_t links;
247 task_tree_data_t data;
248 task_tree_context_block_t context_blk;
249 interval_timer_data_t int_timer;
250} task_tree_control_block_t;
251
252
253#endif /* __DSP_TASK_TYPES_H__ */
diff --git a/include/sound/cs8403.h b/include/sound/cs8403.h
new file mode 100644
index 000000000000..0b7d216e24f1
--- /dev/null
+++ b/include/sound/cs8403.h
@@ -0,0 +1,257 @@
1#ifndef __SOUND_CS8403_H
2#define __SOUND_CS8403_H
3
4/*
5 * Routines for Cirrus Logic CS8403/CS8404A IEC958 (S/PDIF) Transmitter
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
7 * Takashi Iwai <tiwai@suse.de>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifdef SND_CS8403
27
28#ifndef SND_CS8403_DECL
29#define SND_CS8403_DECL static
30#endif
31#ifndef SND_CS8403_DECODE
32#define SND_CS8403_DECODE snd_cs8403_decode_spdif_bits
33#endif
34#ifndef SND_CS8403_ENCODE
35#define SND_CS8403_ENCODE snd_cs8403_encode_spdif_bits
36#endif
37
38
39SND_CS8403_DECL void SND_CS8403_DECODE(snd_aes_iec958_t *diga, unsigned char bits)
40{
41 if (bits & 0x01) { /* consumer */
42 if (!(bits & 0x02))
43 diga->status[0] |= IEC958_AES0_NONAUDIO;
44 if (!(bits & 0x08))
45 diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT;
46 switch (bits & 0x10) {
47 case 0x10: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_NONE; break;
48 case 0x00: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015; break;
49 }
50 if (!(bits & 0x80))
51 diga->status[1] |= IEC958_AES1_CON_ORIGINAL;
52 switch (bits & 0x60) {
53 case 0x00: diga->status[1] |= IEC958_AES1_CON_MAGNETIC_ID; break;
54 case 0x20: diga->status[1] |= IEC958_AES1_CON_DIGDIGCONV_ID; break;
55 case 0x40: diga->status[1] |= IEC958_AES1_CON_LASEROPT_ID; break;
56 case 0x60: diga->status[1] |= IEC958_AES1_CON_GENERAL; break;
57 }
58 switch (bits & 0x06) {
59 case 0x00: diga->status[3] |= IEC958_AES3_CON_FS_44100; break;
60 case 0x02: diga->status[3] |= IEC958_AES3_CON_FS_48000; break;
61 case 0x04: diga->status[3] |= IEC958_AES3_CON_FS_32000; break;
62 }
63 } else {
64 diga->status[0] = IEC958_AES0_PROFESSIONAL;
65 switch (bits & 0x18) {
66 case 0x00: diga->status[0] |= IEC958_AES0_PRO_FS_32000; break;
67 case 0x10: diga->status[0] |= IEC958_AES0_PRO_FS_44100; break;
68 case 0x08: diga->status[0] |= IEC958_AES0_PRO_FS_48000; break;
69 case 0x18: diga->status[0] |= IEC958_AES0_PRO_FS_NOTID; break;
70 }
71 switch (bits & 0x60) {
72 case 0x20: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NONE; break;
73 case 0x40: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015; break;
74 case 0x00: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_CCITT; break;
75 case 0x60: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NOTID; break;
76 }
77 if (bits & 0x80)
78 diga->status[1] |= IEC958_AES1_PRO_MODE_STEREOPHONIC;
79 }
80}
81
82SND_CS8403_DECL unsigned char SND_CS8403_ENCODE(snd_aes_iec958_t *diga)
83{
84 unsigned char bits;
85
86 if (!(diga->status[0] & IEC958_AES0_PROFESSIONAL)) {
87 bits = 0x01; /* consumer mode */
88 if (diga->status[0] & IEC958_AES0_NONAUDIO)
89 bits &= ~0x02;
90 else
91 bits |= 0x02;
92 if (diga->status[0] & IEC958_AES0_CON_NOT_COPYRIGHT)
93 bits &= ~0x08;
94 else
95 bits |= 0x08;
96 switch (diga->status[0] & IEC958_AES0_CON_EMPHASIS) {
97 default:
98 case IEC958_AES0_CON_EMPHASIS_NONE: bits |= 0x10; break;
99 case IEC958_AES0_CON_EMPHASIS_5015: bits |= 0x00; break;
100 }
101 if (diga->status[1] & IEC958_AES1_CON_ORIGINAL)
102 bits &= ~0x80;
103 else
104 bits |= 0x80;
105 if ((diga->status[1] & IEC958_AES1_CON_CATEGORY) == IEC958_AES1_CON_GENERAL)
106 bits |= 0x60;
107 else {
108 switch(diga->status[1] & IEC958_AES1_CON_MAGNETIC_MASK) {
109 case IEC958_AES1_CON_MAGNETIC_ID:
110 bits |= 0x00; break;
111 case IEC958_AES1_CON_DIGDIGCONV_ID:
112 bits |= 0x20; break;
113 default:
114 case IEC958_AES1_CON_LASEROPT_ID:
115 bits |= 0x40; break;
116 }
117 }
118 switch (diga->status[3] & IEC958_AES3_CON_FS) {
119 default:
120 case IEC958_AES3_CON_FS_44100: bits |= 0x00; break;
121 case IEC958_AES3_CON_FS_48000: bits |= 0x02; break;
122 case IEC958_AES3_CON_FS_32000: bits |= 0x04; break;
123 }
124 } else {
125 bits = 0x00; /* professional mode */
126 if (diga->status[0] & IEC958_AES0_NONAUDIO)
127 bits &= ~0x02;
128 else
129 bits |= 0x02;
130 /* CHECKME: I'm not sure about the bit order in val here */
131 switch (diga->status[0] & IEC958_AES0_PRO_FS) {
132 case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break;
133 case IEC958_AES0_PRO_FS_44100: bits |= 0x10; break; /* 44.1kHz */
134 case IEC958_AES0_PRO_FS_48000: bits |= 0x08; break; /* 48kHz */
135 default:
136 case IEC958_AES0_PRO_FS_NOTID: bits |= 0x18; break;
137 }
138 switch (diga->status[0] & IEC958_AES0_PRO_EMPHASIS) {
139 case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x20; break;
140 case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x40; break;
141 case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break;
142 default:
143 case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x60; break;
144 }
145 switch (diga->status[1] & IEC958_AES1_PRO_MODE) {
146 case IEC958_AES1_PRO_MODE_TWO:
147 case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break;
148 default: bits |= 0x80; break;
149 }
150 }
151 return bits;
152}
153
154#endif /* SND_CS8403 */
155
156#ifdef SND_CS8404
157
158#ifndef SND_CS8404_DECL
159#define SND_CS8404_DECL static
160#endif
161#ifndef SND_CS8404_DECODE
162#define SND_CS8404_DECODE snd_cs8404_decode_spdif_bits
163#endif
164#ifndef SND_CS8404_ENCODE
165#define SND_CS8404_ENCODE snd_cs8404_encode_spdif_bits
166#endif
167
168
169SND_CS8404_DECL void SND_CS8404_DECODE(snd_aes_iec958_t *diga, unsigned char bits)
170{
171 if (bits & 0x10) { /* consumer */
172 if (!(bits & 0x20))
173 diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT;
174 if (!(bits & 0x40))
175 diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
176 if (!(bits & 0x80))
177 diga->status[1] |= IEC958_AES1_CON_ORIGINAL;
178 switch (bits & 0x03) {
179 case 0x00: diga->status[1] |= IEC958_AES1_CON_DAT; break;
180 case 0x03: diga->status[1] |= IEC958_AES1_CON_GENERAL; break;
181 }
182 switch (bits & 0x06) {
183 case 0x02: diga->status[3] |= IEC958_AES3_CON_FS_32000; break;
184 case 0x04: diga->status[3] |= IEC958_AES3_CON_FS_48000; break;
185 case 0x06: diga->status[3] |= IEC958_AES3_CON_FS_44100; break;
186 }
187 } else {
188 diga->status[0] = IEC958_AES0_PROFESSIONAL;
189 if (!(bits & 0x04))
190 diga->status[0] |= IEC958_AES0_NONAUDIO;
191 switch (bits & 0x60) {
192 case 0x00: diga->status[0] |= IEC958_AES0_PRO_FS_32000; break;
193 case 0x40: diga->status[0] |= IEC958_AES0_PRO_FS_44100; break;
194 case 0x20: diga->status[0] |= IEC958_AES0_PRO_FS_48000; break;
195 case 0x60: diga->status[0] |= IEC958_AES0_PRO_FS_NOTID; break;
196 }
197 switch (bits & 0x03) {
198 case 0x02: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NONE; break;
199 case 0x01: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015; break;
200 case 0x00: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_CCITT; break;
201 case 0x03: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NOTID; break;
202 }
203 if (!(bits & 0x80))
204 diga->status[1] |= IEC958_AES1_PRO_MODE_STEREOPHONIC;
205 }
206}
207
208SND_CS8404_DECL unsigned char SND_CS8404_ENCODE(snd_aes_iec958_t *diga)
209{
210 unsigned char bits;
211
212 if (!(diga->status[0] & IEC958_AES0_PROFESSIONAL)) {
213 bits = 0x10; /* consumer mode */
214 if (!(diga->status[0] & IEC958_AES0_CON_NOT_COPYRIGHT))
215 bits |= 0x20;
216 if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) == IEC958_AES0_CON_EMPHASIS_NONE)
217 bits |= 0x40;
218 if (!(diga->status[1] & IEC958_AES1_CON_ORIGINAL))
219 bits |= 0x80;
220 if ((diga->status[1] & IEC958_AES1_CON_CATEGORY) == IEC958_AES1_CON_GENERAL)
221 bits |= 0x03;
222 switch (diga->status[3] & IEC958_AES3_CON_FS) {
223 default:
224 case IEC958_AES3_CON_FS_44100: bits |= 0x06; break;
225 case IEC958_AES3_CON_FS_48000: bits |= 0x04; break;
226 case IEC958_AES3_CON_FS_32000: bits |= 0x02; break;
227 }
228 } else {
229 bits = 0x00; /* professional mode */
230 if (!(diga->status[0] & IEC958_AES0_NONAUDIO))
231 bits |= 0x04;
232 switch (diga->status[0] & IEC958_AES0_PRO_FS) {
233 case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break;
234 case IEC958_AES0_PRO_FS_44100: bits |= 0x40; break; /* 44.1kHz */
235 case IEC958_AES0_PRO_FS_48000: bits |= 0x20; break; /* 48kHz */
236 default:
237 case IEC958_AES0_PRO_FS_NOTID: bits |= 0x00; break;
238 }
239 switch (diga->status[0] & IEC958_AES0_PRO_EMPHASIS) {
240 case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x02; break;
241 case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x01; break;
242 case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break;
243 default:
244 case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x03; break;
245 }
246 switch (diga->status[1] & IEC958_AES1_PRO_MODE) {
247 case IEC958_AES1_PRO_MODE_TWO:
248 case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break;
249 default: bits |= 0x80; break;
250 }
251 }
252 return bits;
253}
254
255#endif /* SND_CS8404 */
256
257#endif /* __SOUND_CS8403_H */
diff --git a/include/sound/cs8427.h b/include/sound/cs8427.h
new file mode 100644
index 000000000000..e725b7049a53
--- /dev/null
+++ b/include/sound/cs8427.h
@@ -0,0 +1,196 @@
1#ifndef __SOUND_CS8427_H
2#define __SOUND_CS8427_H
3
4/*
5 * Routines for Cirrus Logic CS8427
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <sound/i2c.h>
26
27#define CS8427_BASE_ADDR 0x10 /* base I2C address */
28
29#define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */
30#define CS8427_REG_CONTROL1 0x01
31#define CS8427_REG_CONTROL2 0x02
32#define CS8427_REG_DATAFLOW 0x03
33#define CS8427_REG_CLOCKSOURCE 0x04
34#define CS8427_REG_SERIALINPUT 0x05
35#define CS8427_REG_SERIALOUTPUT 0x06
36#define CS8427_REG_INT1STATUS 0x07
37#define CS8427_REG_INT2STATUS 0x08
38#define CS8427_REG_INT1MASK 0x09
39#define CS8427_REG_INT1MODEMSB 0x0a
40#define CS8427_REG_INT1MODELSB 0x0b
41#define CS8427_REG_INT2MASK 0x0c
42#define CS8427_REG_INT2MODEMSB 0x0d
43#define CS8427_REG_INT2MODELSB 0x0e
44#define CS8427_REG_RECVCSDATA 0x0f
45#define CS8427_REG_RECVERRORS 0x10
46#define CS8427_REG_RECVERRMASK 0x11
47#define CS8427_REG_CSDATABUF 0x12
48#define CS8427_REG_UDATABUF 0x13
49#define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */
50#define CS8427_REG_OMCKRMCKRATIO 0x1e
51#define CS8427_REG_CORU_DATABUF 0x20 /* 24 byte buffer area */
52#define CS8427_REG_ID_AND_VER 0x7f
53
54/* CS8427_REG_CONTROL1 bits */
55#define CS8427_SWCLK (1<<7) /* 0 = RMCK default, 1 = OMCK output on RMCK pin */
56#define CS8427_VSET (1<<6) /* 0 = valid PCM data, 1 = invalid PCM data */
57#define CS8427_MUTESAO (1<<5) /* mute control for the serial audio output port, 0 = disabled, 1 = enabled */
58#define CS8427_MUTEAES (1<<4) /* mute control for the AES transmitter output, 0 = disabled, 1 = enabled */
59#define CS8427_INTMASK (3<<1) /* interrupt output pin setup mask */
60#define CS8427_INTACTHIGH (0<<1) /* active high */
61#define CS8427_INTACTLOW (1<<1) /* active low */
62#define CS8427_INTOPENDRAIN (2<<1) /* open drain, active low */
63#define CS8427_TCBLDIR (1<<0) /* 0 = TCBL is an input, 1 = TCBL is an output */
64
65/* CS8427_REQ_CONTROL2 bits */
66#define CS8427_HOLDMASK (3<<5) /* action when a receiver error occurs */
67#define CS8427_HOLDLASTSAMPLE (0<<5) /* hold the last valid sample */
68#define CS8427_HOLDZERO (1<<5) /* replace the current audio sample with zero (mute) */
69#define CS8427_HOLDNOCHANGE (2<<5) /* do not change the received audio sample */
70#define CS8427_RMCKF (1<<4) /* 0 = 256*Fsi, 1 = 128*Fsi */
71#define CS8427_MMR (1<<3) /* AES3 receiver operation, 0 = stereo, 1 = mono */
72#define CS8427_MMT (1<<2) /* AES3 transmitter operation, 0 = stereo, 1 = mono */
73#define CS8427_MMTCS (1<<1) /* 0 = use A + B CS data, 1 = use MMTLR CS data */
74#define CS8427_MMTLR (1<<0) /* 0 = use A CS data, 1 = use B CS data */
75
76/* CS8427_REG_DATAFLOW */
77#define CS8427_TXOFF (1<<6) /* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */
78#define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
79#define CS8427_TXDMASK (3<<3) /* AES3 Transmitter Data Source Mask */
80#define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */
81#define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
82#define CS8427_SPDMASK (3<<1) /* Serial Audio Output Port Data Source Mask */
83#define CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */
84#define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */
85
86/* CS8427_REG_CLOCKSOURCE */
87#define CS8427_RUN (1<<6) /* 0 = clock off, 1 = clock on */
88#define CS8427_CLKMASK (3<<4) /* OMCK frequency mask */
89#define CS8427_CLK256 (0<<4) /* 256*Fso */
90#define CS8427_CLK384 (1<<4) /* 384*Fso */
91#define CS8427_CLK512 (2<<4) /* 512*Fso */
92#define CS8427_OUTC (1<<3) /* Output Time Base, 0 = OMCK, 1 = recovered input clock */
93#define CS8427_INC (1<<2) /* Input Time Base Clock Source, 0 = recoverd input clock, 1 = OMCK input pin */
94#define CS8427_RXDMASK (3<<0) /* Recovered Input Clock Source Mask */
95#define CS8427_RXDILRCK (0<<0) /* 256*Fsi from ILRCK pin */
96#define CS8427_RXDAES3INPUT (1<<0) /* 256*Fsi from AES3 input */
97#define CS8427_EXTCLOCKRESET (2<<0) /* bypass PLL, 256*Fsi clock, synchronous reset */
98#define CS8427_EXTCLOCK (3<<0) /* bypass PLL, 256*Fsi clock */
99
100/* CS8427_REG_SERIALINPUT */
101#define CS8427_SIMS (1<<7) /* 0 = slave, 1 = master mode */
102#define CS8427_SISF (1<<6) /* ISCLK freq, 0 = 64*Fsi, 1 = 128*Fsi */
103#define CS8427_SIRESMASK (3<<4) /* Resolution of the input data for right justified formats */
104#define CS8427_SIRES24 (0<<4) /* SIRES 24-bit */
105#define CS8427_SIRES20 (1<<4) /* SIRES 20-bit */
106#define CS8427_SIRES16 (2<<4) /* SIRES 16-bit */
107#define CS8427_SIJUST (1<<3) /* Justification of SDIN data relative to ILRCK, 0 = left-justified, 1 = right-justified */
108#define CS8427_SIDEL (1<<2) /* Delay of SDIN data relative to ILRCK for left-justified data formats, 0 = first ISCLK period, 1 = second ISCLK period */
109#define CS8427_SISPOL (1<<1) /* ICLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */
110#define CS8427_SILRPOL (1<<0) /* ILRCK clock polarity, 0 = SDIN data left channel when ILRCK is high, 1 = SDIN right when ILRCK is high */
111
112/* CS8427_REG_SERIALOUTPUT */
113#define CS8427_SOMS (1<<7) /* 0 = slave, 1 = master mode */
114#define CS8427_SOSF (1<<6) /* OSCLK freq, 0 = 64*Fso, 1 = 128*Fso */
115#define CS8427_SORESMASK (3<<4) /* Resolution of the output data on SDOUT and AES3 output */
116#define CS8427_SORES24 (0<<4) /* SIRES 24-bit */
117#define CS8427_SORES20 (1<<4) /* SIRES 20-bit */
118#define CS8427_SORES16 (2<<4) /* SIRES 16-bit */
119#define CS8427_SORESDIRECT (2<<4) /* SIRES direct copy from AES3 receiver */
120#define CS8427_SOJUST (1<<3) /* Justification of SDOUT data relative to OLRCK, 0 = left-justified, 1 = right-justified */
121#define CS8427_SODEL (1<<2) /* Delay of SDOUT data relative to OLRCK for left-justified data formats, 0 = first OSCLK period, 1 = second OSCLK period */
122#define CS8427_SOSPOL (1<<1) /* OSCLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */
123#define CS8427_SOLRPOL (1<<0) /* OLRCK clock polarity, 0 = SDOUT data left channel when OLRCK is high, 1 = SDOUT right when OLRCK is high */
124
125/* CS8427_REG_INT1STATUS */
126#define CS8427_TSLIP (1<<7) /* AES3 transmitter source data slip interrupt */
127#define CS8427_OSLIP (1<<6) /* Serial audio output port data slip interrupt */
128#define CS8427_DETC (1<<2) /* D to E C-buffer transfer interrupt */
129#define CS8427_EFTC (1<<1) /* E to F C-buffer transfer interrupt */
130#define CS8427_RERR (1<<0) /* A receiver error has occurred */
131
132/* CS8427_REG_INT2STATUS */
133#define CS8427_DETU (1<<3) /* D to E U-buffer transfer interrupt */
134#define CS8427_EFTU (1<<2) /* E to F U-buffer transfer interrupt */
135#define CS8427_QCH (1<<1) /* A new block of Q-subcode data is available for reading */
136
137/* CS8427_REG_INT1MODEMSB && CS8427_REG_INT1MODELSB */
138/* bits are defined in CS8427_REG_INT1STATUS */
139/* CS8427_REG_INT2MODEMSB && CS8427_REG_INT2MODELSB */
140/* bits are defined in CS8427_REG_INT2STATUS */
141#define CS8427_INTMODERISINGMSB 0
142#define CS8427_INTMODERESINGLSB 0
143#define CS8427_INTMODEFALLINGMSB 0
144#define CS8427_INTMODEFALLINGLSB 1
145#define CS8427_INTMODELEVELMSB 1
146#define CS8427_INTMODELEVELLSB 0
147
148/* CS8427_REG_RECVCSDATA */
149#define CS8427_AUXMASK (15<<4) /* auxiliary data field width */
150#define CS8427_AUXSHIFT 4
151#define CS8427_PRO (1<<3) /* Channel status block format indicator */
152#define CS8427_AUDIO (1<<2) /* Audio indicator (0 = audio, 1 = nonaudio */
153#define CS8427_COPY (1<<1) /* 0 = copyright asserted, 1 = copyright not asserted */
154#define CS8427_ORIG (1<<0) /* SCMS generation indicator, 0 = 1st generation or highter, 1 = original */
155
156/* CS8427_REG_RECVERRORS */
157/* CS8427_REG_RECVERRMASK for CS8427_RERR */
158#define CS8427_QCRC (1<<6) /* Q-subcode data CRC error indicator */
159#define CS8427_CCRC (1<<5) /* Chancnel Status Block Cyclick Redundancy Check Bit */
160#define CS8427_UNLOCK (1<<4) /* PLL lock status bit */
161#define CS8427_V (1<<3) /* 0 = valid data */
162#define CS8427_CONF (1<<2) /* Confidence bit */
163#define CS8427_BIP (1<<1) /* Bi-phase error bit */
164#define CS8427_PAR (1<<0) /* Parity error */
165
166/* CS8427_REG_CSDATABUF */
167#define CS8427_BSEL (1<<5) /* 0 = CS data, 1 = U data */
168#define CS8427_CBMR (1<<4) /* 0 = overwrite first 5 bytes for CS D to E buffer, 1 = prevent */
169#define CS8427_DETCI (1<<3) /* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
170#define CS8427_EFTCI (1<<2) /* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
171#define CS8427_CAM (1<<1) /* CS data buffer control port access mode bit, 0 = one byte, 1 = two byte */
172#define CS8427_CHS (1<<0) /* Channel select bit, 0 = Channel A, 1 = Channel B */
173
174/* CS8427_REG_UDATABUF */
175#define CS8427_UD (1<<4) /* User data pin (U) direction, 0 = input, 1 = output */
176#define CS8427_UBMMASK (3<<2) /* Operating mode of the AES3 U bit manager */
177#define CS8427_UBMZEROS (0<<2) /* transmit all zeros mode */
178#define CS8427_UBMBLOCK (1<<2) /* block mode */
179#define CS8427_DETUI (1<<1) /* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
180#define CS8427_EFTUI (1<<1) /* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
181
182/* CS8427_REG_ID_AND_VER */
183#define CS8427_IDMASK (15<<4)
184#define CS8427_IDSHIFT 4
185#define CS8427_VERMASK (15<<0)
186#define CS8427_VERSHIFT 0
187#define CS8427_VER8427A 0x71
188
189int snd_cs8427_create(snd_i2c_bus_t *bus, unsigned char addr,
190 unsigned int reset_timeout, snd_i2c_device_t **r_cs8427);
191int snd_cs8427_reg_write(snd_i2c_device_t *device, unsigned char reg, unsigned char val);
192int snd_cs8427_iec958_build(snd_i2c_device_t *cs8427, snd_pcm_substream_t *playback_substream, snd_pcm_substream_t *capture_substream);
193int snd_cs8427_iec958_active(snd_i2c_device_t *cs8427, int active);
194int snd_cs8427_iec958_pcm(snd_i2c_device_t *cs8427, unsigned int rate);
195
196#endif /* __SOUND_CS8427_H */
diff --git a/include/sound/driver.h b/include/sound/driver.h
new file mode 100644
index 000000000000..948e9a1aebef
--- /dev/null
+++ b/include/sound/driver.h
@@ -0,0 +1,64 @@
1#ifndef __SOUND_DRIVER_H
2#define __SOUND_DRIVER_H
3
4/*
5 * Main header file for the ALSA driver
6 * Copyright (c) 1994-2000 by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#ifdef ALSA_BUILD
26#include "config.h"
27#endif
28
29#include <linux/config.h>
30
31#define SNDRV_CARDS 8 /* number of supported soundcards - don't change - minor numbers */
32
33#ifndef CONFIG_SND_MAJOR /* standard configuration */
34#define CONFIG_SND_MAJOR 116
35#endif
36
37#ifndef CONFIG_SND_DEBUG
38#undef CONFIG_SND_DEBUG_MEMORY
39#endif
40
41#ifdef ALSA_BUILD
42#include "adriver.h"
43#endif
44
45#include <linux/module.h>
46
47/*
48 * ==========================================================================
49 */
50
51#ifdef CONFIG_SND_DEBUG_MEMORY
52#include <linux/slab.h>
53#include <linux/vmalloc.h>
54void *snd_wrapper_kmalloc(size_t, int);
55#undef kmalloc
56void snd_wrapper_kfree(const void *);
57#undef kfree
58void *snd_wrapper_vmalloc(size_t);
59#undef vmalloc
60void snd_wrapper_vfree(void *);
61#undef vfree
62#endif
63
64#endif /* __SOUND_DRIVER_H */
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
new file mode 100644
index 000000000000..43b6786abae5
--- /dev/null
+++ b/include/sound/emu10k1.h
@@ -0,0 +1,1544 @@
1#ifndef __SOUND_EMU10K1_H
2#define __SOUND_EMU10K1_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
6 * Creative Labs, Inc.
7 * Definitions for EMU10K1 (SB Live!) chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifdef __KERNEL__
27
28#include <sound/pcm.h>
29#include <sound/rawmidi.h>
30#include <sound/hwdep.h>
31#include <sound/ac97_codec.h>
32#include <sound/util_mem.h>
33#include <sound/pcm-indirect.h>
34#include <sound/timer.h>
35#include <linux/interrupt.h>
36#include <asm/io.h>
37
38#ifndef PCI_VENDOR_ID_CREATIVE
39#define PCI_VENDOR_ID_CREATIVE 0x1102
40#endif
41#ifndef PCI_DEVICE_ID_CREATIVE_EMU10K1
42#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
43#endif
44
45/* ------------------- DEFINES -------------------- */
46
47#define EMUPAGESIZE 4096
48#define MAXREQVOICES 8
49#define MAXPAGES 8192
50#define RESERVED 0
51#define NUM_MIDI 16
52#define NUM_G 64 /* use all channels */
53#define NUM_FXSENDS 4
54#define NUM_EFX_PLAYBACK 16
55
56/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
57#define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
58#define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit */
59
60#define TMEMSIZE 256*1024
61#define TMEMSIZEREG 4
62
63#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
64
65// Audigy specify registers are prefixed with 'A_'
66
67/************************************************************************************************/
68/* PCI function 0 registers, address = <val> + PCIBASE0 */
69/************************************************************************************************/
70
71#define PTR 0x00 /* Indexed register set pointer register */
72 /* NOTE: The CHANNELNUM and ADDRESS words can */
73 /* be modified independently of each other. */
74#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
75 /* channel number of the register to be */
76 /* accessed. For non per-channel registers the */
77 /* value should be set to zero. */
78#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
79#define A_PTR_ADDRESS_MASK 0x0fff0000
80
81#define DATA 0x04 /* Indexed register set data register */
82
83#define IPR 0x08 /* Global interrupt pending register */
84 /* Clear pending interrupts by writing a 1 to */
85 /* the relevant bits and zero to the other bits */
86
87#define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
88 which INTE bits enable it) */
89
90/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
91#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
92#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
93
94#define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
95#define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
96
97#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
98#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
99#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
100#define IPR_PCIERROR 0x00200000 /* PCI bus error */
101#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
102#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
103#define IPR_MUTE 0x00040000 /* Mute button pressed */
104#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
105#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
106#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
107#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
108#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
109#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
110#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
111#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
112#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
113#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
114#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
115#define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
116#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
117 /* highest set channel in CLIPL, CLIPH, HLIPL, */
118 /* or HLIPH. When IP is written with CL set, */
119 /* the bit in H/CLIPL or H/CLIPH corresponding */
120 /* to the CIN value written will be cleared. */
121
122#define INTE 0x0c /* Interrupt enable register */
123#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
124#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
125#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
126#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
127#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
128#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
129#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
130#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
131#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
132#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
133#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
134#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
135#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
136#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
137#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
138#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
139#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
140#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
141
142#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
143 /* NOTE: There is no reason to use this under */
144 /* Linux, and it will cause odd hardware */
145 /* behavior and possibly random segfaults and */
146 /* lockups if enabled. */
147
148/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
149#define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
150#define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
151
152
153#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
154 /* NOTE: This bit must always be enabled */
155#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
156#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
157#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
158#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
159#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
160#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
161#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
162#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
163#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
164#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
165#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
166#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
167#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
168
169#define WC 0x10 /* Wall Clock register */
170#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
171#define WC_SAMPLECOUNTER 0x14060010
172#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
173 /* NOTE: Each channel takes 1/64th of a sample */
174 /* period to be serviced. */
175
176#define HCFG 0x14 /* Hardware config register */
177 /* NOTE: There is no reason to use the legacy */
178 /* SoundBlaster emulation stuff described below */
179 /* under Linux, and all kinds of weird hardware */
180 /* behavior can result if you try. Don't. */
181#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
182#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
183#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
184#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
185#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
186#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
187#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
188#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
189#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
190#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
191#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
192#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
193 /* NOTE: The rest of the bits in this register */
194 /* _are_ relevant under Linux. */
195#define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
196#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
197#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
198#define HCFG_GPINPUT0 0x00004000 /* External pin112 */
199#define HCFG_GPINPUT1 0x00002000 /* External pin110 */
200#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
201#define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
202#define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
203#define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
204#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
205#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
206 /* 1 = Force all 3 async digital inputs to use */
207 /* the same async sample rate tracker (ZVIDEO) */
208#define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
209#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
210#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
211#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
212#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
213 /* will automatically mute their output when */
214 /* they are not rate-locked to the external */
215 /* async audio source */
216#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
217 /* NOTE: This should generally never be used. */
218#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
219 /* NOTE: This should generally never be used. */
220#define HCFG_LOCKTANKCACHE 0x01020014
221#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
222 /* NOTE: This is a 'cheap' way to implement a */
223 /* master mute function on the mute button, and */
224 /* in general should not be used unless a more */
225 /* sophisticated master mute function has not */
226 /* been written. */
227#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
228 /* Should be set to 1 when the EMU10K1 is */
229 /* completely initialized. */
230
231//For Audigy, MPU port move to 0x70-0x74 ptr register
232
233#define MUDATA 0x18 /* MPU401 data register (8 bits) */
234
235#define MUCMD 0x19 /* MPU401 command register (8 bits) */
236#define MUCMD_RESET 0xff /* RESET command */
237#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
238 /* NOTE: All other commands are ignored */
239
240#define MUSTAT MUCMD /* MPU401 status register (8 bits) */
241#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
242#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
243
244#define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
245#define A_GPINPUT_MASK 0xff00
246#define A_GPOUTPUT_MASK 0x00ff
247
248// Audigy output/GPIO stuff taken from the kX drivers
249#define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
250#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
251#define A_IOCFG_ENABLE_DIGITAL 0x0004
252#define A_IOCFG_UNKNOWN_20 0x0020
253#define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
254#define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
255#define A_IOCFG_GPOUT2 0x0001 /* IR */
256#define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
257 /* + digital for generic 10k2 */
258#define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
259#define A_IOCFG_FRONT_JACK 0x4000
260#define A_IOCFG_REAR_JACK 0x8000
261#define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
262
263/* outputs:
264 * for audigy2 platinum: 0xa00
265 * for a2 platinum ex: 0x1c00
266 * for a1 platinum: 0x0
267 */
268
269#define TIMER 0x1a /* Timer terminal count register */
270 /* NOTE: After the rate is changed, a maximum */
271 /* of 1024 sample periods should be allowed */
272 /* before the new rate is guaranteed accurate. */
273#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
274 /* 0 == 1024 periods, [1..4] are not useful */
275#define TIMER_RATE 0x0a00001a
276
277#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
278
279#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
280#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
281#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
282
283/* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
284#define PTR2 0x20 /* Indexed register set pointer register */
285#define DATA2 0x24 /* Indexed register set data register */
286#define IPR2 0x28 /* P16V interrupt pending register */
287#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
288#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
289#define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
290#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
291 /* 0x00000100 Playback. Only in once per period.
292 * 0x00110000 Capture. Int on half buffer.
293 */
294#define INTE2 0x2c /* P16V Interrupt enable register. */
295#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
296#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
297#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
298#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
299#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
300#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
301#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
302#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
303#define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
304#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
305#define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
306 /* 0x00000000 2-channel output. */
307 /* 0x00000200 8-channel output. */
308 /* 0x00000004 pauses stream/irq fail. */
309 /* Rest of bits no nothing to sound output */
310 /* bit 0: Enable P16V audio.
311 * bit 1: Lock P16V record memory cache.
312 * bit 2: Lock P16V playback memory cache.
313 * bit 3: Dummy record insert zero samples.
314 * bit 8: Record 8-channel in phase.
315 * bit 9: Playback 8-channel in phase.
316 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
317 * bit 13: Playback mixer enable.
318 * bit 14: Route SRC48 mixer output to fx engine.
319 * bit 15: Enable IEEE 1394 chip.
320 */
321#define IPR3 0x38 /* Cdif interrupt pending register */
322#define INTE3 0x3c /* Cdif interrupt enable register. */
323/************************************************************************************************/
324/* PCI function 1 registers, address = <val> + PCIBASE1 */
325/************************************************************************************************/
326
327#define JOYSTICK1 0x00 /* Analog joystick port register */
328#define JOYSTICK2 0x01 /* Analog joystick port register */
329#define JOYSTICK3 0x02 /* Analog joystick port register */
330#define JOYSTICK4 0x03 /* Analog joystick port register */
331#define JOYSTICK5 0x04 /* Analog joystick port register */
332#define JOYSTICK6 0x05 /* Analog joystick port register */
333#define JOYSTICK7 0x06 /* Analog joystick port register */
334#define JOYSTICK8 0x07 /* Analog joystick port register */
335
336/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
337/* When reading, use these bitfields: */
338#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
339#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
340
341
342/********************************************************************************************************/
343/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
344/********************************************************************************************************/
345
346#define CPF 0x00 /* Current pitch and fraction register */
347#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
348#define CPF_CURRENTPITCH 0x10100000
349#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
350#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
351#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
352
353#define PTRX 0x01 /* Pitch target and send A/B amounts register */
354#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
355#define PTRX_PITCHTARGET 0x10100001
356#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
357#define PTRX_FXSENDAMOUNT_A 0x08080001
358#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
359#define PTRX_FXSENDAMOUNT_B 0x08000001
360
361#define CVCF 0x02 /* Current volume and filter cutoff register */
362#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
363#define CVCF_CURRENTVOL 0x10100002
364#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
365#define CVCF_CURRENTFILTER 0x10000002
366
367#define VTFT 0x03 /* Volume target and filter cutoff target register */
368#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
369#define VTFT_VOLUMETARGET 0x10100003
370#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
371#define VTFT_FILTERTARGET 0x10000003
372
373#define Z1 0x05 /* Filter delay memory 1 register */
374
375#define Z2 0x04 /* Filter delay memory 2 register */
376
377#define PSST 0x06 /* Send C amount and loop start address register */
378#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
379
380#define PSST_FXSENDAMOUNT_C 0x08180006
381
382#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
383#define PSST_LOOPSTARTADDR 0x18000006
384
385#define DSL 0x07 /* Send D amount and loop start address register */
386#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
387
388#define DSL_FXSENDAMOUNT_D 0x08180007
389
390#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
391#define DSL_LOOPENDADDR 0x18000007
392
393#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
394#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
395#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
396 /* 1 == full band, 7 == lowpass */
397 /* ROM 0 is used when pitch shifting downward or less */
398 /* then 3 semitones upward. Increasingly higher ROM */
399 /* numbers are used, typically in steps of 3 semitones, */
400 /* as upward pitch shifting is performed. */
401#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
402#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
403#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
404#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
405#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
406#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
407#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
408#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
409#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
410#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
411#define CCCA_CURRADDR 0x18000008
412
413#define CCR 0x09 /* Cache control register */
414#define CCR_CACHEINVALIDSIZE 0x07190009
415#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
416#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
417#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
418#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
419#define CCR_READADDRESS 0x06100009
420#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
421#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
422 /* NOTE: This is valid only if CACHELOOPFLAG is set */
423#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
424#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
425
426#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
427 /* NOTE: This register is normally not used */
428#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
429
430#define FXRT 0x0b /* Effects send routing register */
431 /* NOTE: It is illegal to assign the same routing to */
432 /* two effects sends. */
433#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
434#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
435#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
436#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
437
438#define MAPA 0x0c /* Cache map A */
439
440#define MAPB 0x0d /* Cache map B */
441
442#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
443#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
444
445#define ENVVOL 0x10 /* Volume envelope register */
446#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
447 /* 0x8000-n == 666*n usec delay */
448
449#define ATKHLDV 0x11 /* Volume envelope hold and attack register */
450#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
451#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
452#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
453 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
454
455#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
456#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
457#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
458#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
459 /* this channel and from writing to pitch, filter and */
460 /* volume targets. */
461#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
462 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
463
464#define LFOVAL1 0x13 /* Modulation LFO value */
465#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
466 /* 0x8000-n == 666*n usec delay */
467
468#define ENVVAL 0x14 /* Modulation envelope register */
469#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
470 /* 0x8000-n == 666*n usec delay */
471
472#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
473#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
474#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
475#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
476 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
477
478#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
479#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
480#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
481#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
482 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
483
484#define LFOVAL2 0x17 /* Vibrato LFO register */
485#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
486 /* 0x8000-n == 666*n usec delay */
487
488#define IP 0x18 /* Initial pitch register */
489#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
490 /* 4 bits of octave, 12 bits of fractional octave */
491#define IP_UNITY 0x0000e000 /* Unity pitch shift */
492
493#define IFATN 0x19 /* Initial filter cutoff and attenuation register */
494#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
495 /* 6 most significant bits are semitones */
496 /* 2 least significant bits are fractions */
497#define IFATN_FILTERCUTOFF 0x08080019
498#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
499#define IFATN_ATTENUATION 0x08000019
500
501
502#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
503#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
504 /* Signed 2's complement, +/- one octave peak extremes */
505#define PEFE_PITCHAMOUNT 0x0808001a
506#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
507 /* Signed 2's complement, +/- six octaves peak extremes */
508#define PEFE_FILTERAMOUNT 0x0800001a
509#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
510#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
511 /* Signed 2's complement, +/- one octave extremes */
512#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
513 /* Signed 2's complement, +/- three octave extremes */
514
515
516#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
517#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
518 /* Signed 2's complement, with +/- 12dB extremes */
519
520#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
521 /* ??Hz steps, maximum of ?? Hz. */
522#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
523#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
524 /* Signed 2's complement, +/- one octave extremes */
525#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
526 /* 0.039Hz steps, maximum of 9.85 Hz. */
527
528#define TEMPENV 0x1e /* Tempory envelope register */
529#define TEMPENV_MASK 0x0000ffff /* 16-bit value */
530 /* NOTE: All channels contain internal variables; do */
531 /* not write to these locations. */
532
533/* 1f something */
534
535#define CD0 0x20 /* Cache data 0 register */
536#define CD1 0x21 /* Cache data 1 register */
537#define CD2 0x22 /* Cache data 2 register */
538#define CD3 0x23 /* Cache data 3 register */
539#define CD4 0x24 /* Cache data 4 register */
540#define CD5 0x25 /* Cache data 5 register */
541#define CD6 0x26 /* Cache data 6 register */
542#define CD7 0x27 /* Cache data 7 register */
543#define CD8 0x28 /* Cache data 8 register */
544#define CD9 0x29 /* Cache data 9 register */
545#define CDA 0x2a /* Cache data A register */
546#define CDB 0x2b /* Cache data B register */
547#define CDC 0x2c /* Cache data C register */
548#define CDD 0x2d /* Cache data D register */
549#define CDE 0x2e /* Cache data E register */
550#define CDF 0x2f /* Cache data F register */
551
552/* 0x30-3f seem to be the same as 0x20-2f */
553
554#define PTB 0x40 /* Page table base register */
555#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
556
557#define TCB 0x41 /* Tank cache base register */
558#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
559
560#define ADCCR 0x42 /* ADC sample rate/stereo control register */
561#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
562#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
563 /* NOTE: To guarantee phase coherency, both channels */
564 /* must be disabled prior to enabling both channels. */
565#define A_ADCCR_RCHANENABLE 0x00000020
566#define A_ADCCR_LCHANENABLE 0x00000010
567
568#define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
569#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
570#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
571#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
572#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
573#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
574#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
575#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
576#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
577#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
578#define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
579#define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
580#define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
581
582#define FXWC 0x43 /* FX output write channels register */
583 /* When set, each bit enables the writing of the */
584 /* corresponding FX output channel (internal registers */
585 /* 0x20-0x3f) to host memory. This mode of recording */
586 /* is 16bit, 48KHz only. All 32 channels can be enabled */
587 /* simultaneously. */
588
589#define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
590#define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
591#define FXWC_DEFAULTROUTE_A (1<<12)
592#define FXWC_DEFAULTROUTE_D (1<<13)
593#define FXWC_ADCLEFT (1<<18)
594#define FXWC_CDROMSPDIFLEFT (1<<18)
595#define FXWC_ADCRIGHT (1<<19)
596#define FXWC_CDROMSPDIFRIGHT (1<<19)
597#define FXWC_MIC (1<<20)
598#define FXWC_ZOOMLEFT (1<<20)
599#define FXWC_ZOOMRIGHT (1<<21)
600#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
601#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
602
603#define TCBS 0x44 /* Tank cache buffer size register */
604#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
605#define TCBS_BUFFSIZE_16K 0x00000000
606#define TCBS_BUFFSIZE_32K 0x00000001
607#define TCBS_BUFFSIZE_64K 0x00000002
608#define TCBS_BUFFSIZE_128K 0x00000003
609#define TCBS_BUFFSIZE_256K 0x00000004
610#define TCBS_BUFFSIZE_512K 0x00000005
611#define TCBS_BUFFSIZE_1024K 0x00000006
612#define TCBS_BUFFSIZE_2048K 0x00000007
613
614#define MICBA 0x45 /* AC97 microphone buffer address register */
615#define MICBA_MASK 0xfffff000 /* 20 bit base address */
616
617#define ADCBA 0x46 /* ADC buffer address register */
618#define ADCBA_MASK 0xfffff000 /* 20 bit base address */
619
620#define FXBA 0x47 /* FX Buffer Address */
621#define FXBA_MASK 0xfffff000 /* 20 bit base address */
622
623/* 0x48 something - word access, defaults to 3f */
624
625#define MICBS 0x49 /* Microphone buffer size register */
626
627#define ADCBS 0x4a /* ADC buffer size register */
628
629#define FXBS 0x4b /* FX buffer size register */
630
631/* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
632
633/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
634#define ADCBS_BUFSIZE_NONE 0x00000000
635#define ADCBS_BUFSIZE_384 0x00000001
636#define ADCBS_BUFSIZE_448 0x00000002
637#define ADCBS_BUFSIZE_512 0x00000003
638#define ADCBS_BUFSIZE_640 0x00000004
639#define ADCBS_BUFSIZE_768 0x00000005
640#define ADCBS_BUFSIZE_896 0x00000006
641#define ADCBS_BUFSIZE_1024 0x00000007
642#define ADCBS_BUFSIZE_1280 0x00000008
643#define ADCBS_BUFSIZE_1536 0x00000009
644#define ADCBS_BUFSIZE_1792 0x0000000a
645#define ADCBS_BUFSIZE_2048 0x0000000b
646#define ADCBS_BUFSIZE_2560 0x0000000c
647#define ADCBS_BUFSIZE_3072 0x0000000d
648#define ADCBS_BUFSIZE_3584 0x0000000e
649#define ADCBS_BUFSIZE_4096 0x0000000f
650#define ADCBS_BUFSIZE_5120 0x00000010
651#define ADCBS_BUFSIZE_6144 0x00000011
652#define ADCBS_BUFSIZE_7168 0x00000012
653#define ADCBS_BUFSIZE_8192 0x00000013
654#define ADCBS_BUFSIZE_10240 0x00000014
655#define ADCBS_BUFSIZE_12288 0x00000015
656#define ADCBS_BUFSIZE_14366 0x00000016
657#define ADCBS_BUFSIZE_16384 0x00000017
658#define ADCBS_BUFSIZE_20480 0x00000018
659#define ADCBS_BUFSIZE_24576 0x00000019
660#define ADCBS_BUFSIZE_28672 0x0000001a
661#define ADCBS_BUFSIZE_32768 0x0000001b
662#define ADCBS_BUFSIZE_40960 0x0000001c
663#define ADCBS_BUFSIZE_49152 0x0000001d
664#define ADCBS_BUFSIZE_57344 0x0000001e
665#define ADCBS_BUFSIZE_65536 0x0000001f
666
667
668#define CDCS 0x50 /* CD-ROM digital channel status register */
669
670#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
671
672#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
673
674#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
675
676#define A_DBG 0x53
677#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
678#define A_DBG_ZC 0x40000000 /* zero tram counter */
679#define A_DBG_STEP_ADDR 0x000003ff
680#define A_DBG_SATURATION_OCCURED 0x20000000
681#define A_DBG_SATURATION_ADDR 0x0ffc0000
682
683// NOTE: 0x54,55,56: 64-bit
684#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
685
686#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
687
688#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
689
690#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
691#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
692#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
693#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
694#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
695#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
696#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
697#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
698#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
699#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
700#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
701#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
702#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
703#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
704#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
705#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
706#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
707#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
708#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
709#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
710#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
711#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
712#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
713
714/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
715#define CLIEL 0x58 /* Channel loop interrupt enable low register */
716
717#define CLIEH 0x59 /* Channel loop interrupt enable high register */
718
719#define CLIPL 0x5a /* Channel loop interrupt pending low register */
720
721#define CLIPH 0x5b /* Channel loop interrupt pending high register */
722
723#define SOLEL 0x5c /* Stop on loop enable low register */
724
725#define SOLEH 0x5d /* Stop on loop enable high register */
726
727#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
728#define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
729#define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
730/* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
731#define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
732
733#define AC97SLOT 0x5f /* additional AC97 slots enable bits */
734#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
735#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
736#define AC97SLOT_CNTR 0x10 /* Center enable */
737#define AC97SLOT_LFE 0x20 /* LFE enable */
738
739// NOTE: 0x60,61,62: 64-bit
740#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
741
742#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
743
744#define ZVSRCS 0x62 /* ZVideo sample rate converter status */
745 /* NOTE: This one has no SPDIFLOCKED field */
746 /* Assumes sample lock */
747
748/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
749#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
750#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
751#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
752
753/* Note that these values can vary +/- by a small amount */
754#define SRCS_SPDIFRATE_44 0x0003acd9
755#define SRCS_SPDIFRATE_48 0x00040000
756#define SRCS_SPDIFRATE_96 0x00080000
757
758#define MICIDX 0x63 /* Microphone recording buffer index register */
759#define MICIDX_MASK 0x0000ffff /* 16-bit value */
760#define MICIDX_IDX 0x10000063
761
762#define ADCIDX 0x64 /* ADC recording buffer index register */
763#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
764#define ADCIDX_IDX 0x10000064
765
766#define A_ADCIDX 0x63
767#define A_ADCIDX_IDX 0x10000063
768
769#define A_MICIDX 0x64
770#define A_MICIDX_IDX 0x10000064
771
772#define FXIDX 0x65 /* FX recording buffer index register */
773#define FXIDX_MASK 0x0000ffff /* 16-bit value */
774#define FXIDX_IDX 0x10000065
775
776/* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
777#define HLIEL 0x66 /* Channel half loop interrupt enable low register */
778
779#define HLIEH 0x67 /* Channel half loop interrupt enable high register */
780
781#define HLIPL 0x68 /* Channel half loop interrupt pending low register */
782
783#define HLIPH 0x69 /* Channel half loop interrupt pending high register */
784
785// 0x6a,6b,6c used for some recording
786// 0x6d unused
787// 0x6e,6f - tanktable base / offset
788
789/* This is the MPU port on the card (via the game port) */
790#define A_MUDATA1 0x70
791#define A_MUCMD1 0x71
792#define A_MUSTAT1 A_MUCMD1
793
794/* This is the MPU port on the Audigy Drive */
795#define A_MUDATA2 0x72
796#define A_MUCMD2 0x73
797#define A_MUSTAT2 A_MUCMD2
798
799/* The next two are the Audigy equivalent of FXWC */
800/* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
801/* Each bit selects a channel for recording */
802#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
803#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
804
805#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
806#define A_SPDIF_RATE_MASK 0x000000c0
807#define A_SPDIF_48000 0x00000000
808#define A_SPDIF_44100 0x00000080
809#define A_SPDIF_96000 0x00000040
810
811/* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */
812/* 0x7a, 0x7b - lookup tables */
813
814#define A_FXRT2 0x7c
815#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
816#define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
817#define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
818#define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
819
820#define A_SENDAMOUNTS 0x7d
821#define A_FXSENDAMOUNT_E_MASK 0xFF000000
822#define A_FXSENDAMOUNT_F_MASK 0x00FF0000
823#define A_FXSENDAMOUNT_G_MASK 0x0000FF00
824#define A_FXSENDAMOUNT_H_MASK 0x000000FF
825/* 0x7c, 0x7e "high bit is used for filtering" */
826
827/* The send amounts for this one are the same as used with the emu10k1 */
828#define A_FXRT1 0x7e
829#define A_FXRT_CHANNELA 0x0000003f
830#define A_FXRT_CHANNELB 0x00003f00
831#define A_FXRT_CHANNELC 0x003f0000
832#define A_FXRT_CHANNELD 0x3f000000
833
834
835/* Each FX general purpose register is 32 bits in length, all bits are used */
836#define FXGPREGBASE 0x100 /* FX general purpose registers base */
837#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
838
839#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
840#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
841
842/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
843/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
844/* locations are for external TRAM. */
845#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
846#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
847
848/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
849#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
850#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
851#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
852#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
853#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
854#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
855
856#define MICROCODEBASE 0x400 /* Microcode data base address */
857
858/* Each DSP microcode instruction is mapped into 2 doublewords */
859/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
860#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
861#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
862#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
863#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
864#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
865
866
867/* Audigy Soundcard have a different instruction format */
868#define A_MICROCODEBASE 0x600
869#define A_LOWORD_OPY_MASK 0x000007ff
870#define A_LOWORD_OPX_MASK 0x007ff000
871#define A_HIWORD_OPCODE_MASK 0x0f000000
872#define A_HIWORD_RESULT_MASK 0x007ff000
873#define A_HIWORD_OPA_MASK 0x000007ff
874
875
876/* ------------------- STRUCTURES -------------------- */
877
878typedef struct _snd_emu10k1 emu10k1_t;
879typedef struct _snd_emu10k1_voice emu10k1_voice_t;
880typedef struct _snd_emu10k1_pcm emu10k1_pcm_t;
881
882typedef enum {
883 EMU10K1_EFX,
884 EMU10K1_PCM,
885 EMU10K1_SYNTH,
886 EMU10K1_MIDI
887} emu10k1_voice_type_t;
888
889struct _snd_emu10k1_voice {
890 emu10k1_t *emu;
891 int number;
892 unsigned int use: 1,
893 pcm: 1,
894 efx: 1,
895 synth: 1,
896 midi: 1;
897 void (*interrupt)(emu10k1_t *emu, emu10k1_voice_t *pvoice);
898
899 emu10k1_pcm_t *epcm;
900};
901
902typedef enum {
903 PLAYBACK_EMUVOICE,
904 PLAYBACK_EFX,
905 CAPTURE_AC97ADC,
906 CAPTURE_AC97MIC,
907 CAPTURE_EFX
908} snd_emu10k1_pcm_type_t;
909
910struct _snd_emu10k1_pcm {
911 emu10k1_t *emu;
912 snd_emu10k1_pcm_type_t type;
913 snd_pcm_substream_t *substream;
914 emu10k1_voice_t *voices[NUM_EFX_PLAYBACK];
915 emu10k1_voice_t *extra;
916 unsigned short running;
917 unsigned short first_ptr;
918 snd_util_memblk_t *memblk;
919 unsigned int start_addr;
920 unsigned int ccca_start_addr;
921 unsigned int capture_ipr; /* interrupt acknowledge mask */
922 unsigned int capture_inte; /* interrupt enable mask */
923 unsigned int capture_ba_reg; /* buffer address register */
924 unsigned int capture_bs_reg; /* buffer size register */
925 unsigned int capture_idx_reg; /* buffer index register */
926 unsigned int capture_cr_val; /* control value */
927 unsigned int capture_cr_val2; /* control value2 (for audigy) */
928 unsigned int capture_bs_val; /* buffer size value */
929 unsigned int capture_bufsize; /* buffer size in bytes */
930};
931
932typedef struct {
933 /* mono, left, right x 8 sends (4 on emu10k1) */
934 unsigned char send_routing[3][8];
935 unsigned char send_volume[3][8];
936 unsigned short attn[3];
937 emu10k1_pcm_t *epcm;
938} emu10k1_pcm_mixer_t;
939
940#define snd_emu10k1_compose_send_routing(route) \
941((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
942
943#define snd_emu10k1_compose_audigy_fxrt1(route) \
944((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
945
946#define snd_emu10k1_compose_audigy_fxrt2(route) \
947((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
948
949typedef struct snd_emu10k1_memblk {
950 snd_util_memblk_t mem;
951 /* private part */
952 int first_page, last_page, pages, mapped_page;
953 unsigned int map_locked;
954 struct list_head mapped_link;
955 struct list_head mapped_order_link;
956} emu10k1_memblk_t;
957
958#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
959
960#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
961
962typedef struct {
963 struct list_head list; /* list link container */
964 unsigned int vcount;
965 unsigned int count; /* count of GPR (1..16) */
966 unsigned short gpr[32]; /* GPR number(s) */
967 unsigned int value[32];
968 unsigned int min; /* minimum range */
969 unsigned int max; /* maximum range */
970 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
971 snd_kcontrol_t *kcontrol;
972} snd_emu10k1_fx8010_ctl_t;
973
974typedef void (snd_fx8010_irq_handler_t)(emu10k1_t *emu, void *private_data);
975
976typedef struct _snd_emu10k1_fx8010_irq {
977 struct _snd_emu10k1_fx8010_irq *next;
978 snd_fx8010_irq_handler_t *handler;
979 unsigned short gpr_running;
980 void *private_data;
981} snd_emu10k1_fx8010_irq_t;
982
983typedef struct {
984 unsigned int valid: 1,
985 opened: 1,
986 active: 1;
987 unsigned int channels; /* 16-bit channels count */
988 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
989 unsigned int buffer_size; /* count of buffered samples */
990 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
991 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
992 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
993 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
994 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
995 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
996 unsigned char etram[32]; /* external TRAM address & data */
997 snd_pcm_indirect_t pcm_rec;
998 unsigned int tram_pos;
999 unsigned int tram_shift;
1000 snd_emu10k1_fx8010_irq_t *irq;
1001} snd_emu10k1_fx8010_pcm_t;
1002
1003typedef struct {
1004 unsigned short fxbus_mask; /* used FX buses (bitmask) */
1005 unsigned short extin_mask; /* used external inputs (bitmask) */
1006 unsigned short extout_mask; /* used external outputs (bitmask) */
1007 unsigned short pad1;
1008 unsigned int itram_size; /* internal TRAM size in samples */
1009 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1010 unsigned int dbg; /* FX debugger register */
1011 unsigned char name[128];
1012 int gpr_size; /* size of allocated GPR controls */
1013 int gpr_count; /* count of used kcontrols */
1014 struct list_head gpr_ctl; /* GPR controls */
1015 struct semaphore lock;
1016 snd_emu10k1_fx8010_pcm_t pcm[8];
1017 spinlock_t irq_lock;
1018 snd_emu10k1_fx8010_irq_t *irq_handlers;
1019} snd_emu10k1_fx8010_t;
1020
1021#define emu10k1_gpr_ctl(n) list_entry(n, snd_emu10k1_fx8010_ctl_t, list)
1022
1023typedef struct {
1024 struct _snd_emu10k1 *emu;
1025 snd_rawmidi_t *rmidi;
1026 snd_rawmidi_substream_t *substream_input;
1027 snd_rawmidi_substream_t *substream_output;
1028 unsigned int midi_mode;
1029 spinlock_t input_lock;
1030 spinlock_t output_lock;
1031 spinlock_t open_lock;
1032 int tx_enable, rx_enable;
1033 int port;
1034 int ipr_tx, ipr_rx;
1035 void (*interrupt)(emu10k1_t *emu, unsigned int status);
1036} emu10k1_midi_t;
1037
1038typedef struct {
1039 u32 vendor;
1040 u32 device;
1041 u32 subsystem;
1042 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1043 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1044 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1045 unsigned char ca0108_chip; /* Audigy 2 Value */
1046 unsigned char ca0151_chip; /* P16V */
1047 unsigned char spk71; /* Has 7.1 speakers */
1048 unsigned char spdif_bug; /* Has Spdif phasing bug */
1049 unsigned char ac97_chip; /* Has an AC97 chip */
1050 unsigned char ecard; /* APS EEPROM */
1051 char * driver;
1052 char * name;
1053} emu_chip_details_t;
1054
1055struct _snd_emu10k1 {
1056 int irq;
1057
1058 unsigned long port; /* I/O port number */
1059 unsigned int APS: 1, /* APS flag */
1060 no_ac97: 1, /* no AC'97 */
1061 tos_link: 1, /* tos link detected */
1062 rear_ac97: 1, /* rear channels are on AC'97 */
1063 spk71:1; /* 7.1 configuration (Audigy 2 ZS) */
1064 const emu_chip_details_t *card_capabilities; /* Contains profile of card capabilities */
1065 unsigned int audigy; /* is Audigy? */
1066 unsigned int revision; /* chip revision */
1067 unsigned int serial; /* serial number */
1068 unsigned short model; /* subsystem id */
1069 unsigned int card_type; /* EMU10K1_CARD_* */
1070 unsigned int ecard_ctrl; /* ecard control bits */
1071 unsigned long dma_mask; /* PCI DMA mask */
1072 int max_cache_pages; /* max memory size / PAGE_SIZE */
1073 struct snd_dma_buffer silent_page; /* silent page */
1074 struct snd_dma_buffer ptb_pages; /* page table pages */
1075 struct snd_dma_device p16v_dma_dev;
1076 struct snd_dma_buffer p16v_buffer;
1077
1078 snd_util_memhdr_t *memhdr; /* page allocation list */
1079 emu10k1_memblk_t *reserved_page; /* reserved page */
1080
1081 struct list_head mapped_link_head;
1082 struct list_head mapped_order_link_head;
1083 void **page_ptr_table;
1084 unsigned long *page_addr_table;
1085 spinlock_t memblk_lock;
1086
1087 unsigned int spdif_bits[3]; /* s/pdif out setup */
1088
1089 snd_emu10k1_fx8010_t fx8010; /* FX8010 info */
1090 int gpr_base;
1091
1092 ac97_t *ac97;
1093
1094 struct pci_dev *pci;
1095 snd_card_t *card;
1096 snd_pcm_t *pcm;
1097 snd_pcm_t *pcm_mic;
1098 snd_pcm_t *pcm_efx;
1099 snd_pcm_t *pcm_p16v;
1100
1101 spinlock_t synth_lock;
1102 void *synth;
1103 int (*get_synth_voice)(emu10k1_t *emu);
1104
1105 spinlock_t reg_lock;
1106 spinlock_t emu_lock;
1107 spinlock_t voice_lock;
1108 struct semaphore ptb_lock;
1109
1110 emu10k1_voice_t voices[NUM_G];
1111 emu10k1_voice_t p16v_voices[4];
1112 int p16v_device_offset;
1113 emu10k1_pcm_mixer_t pcm_mixer[32];
1114 emu10k1_pcm_mixer_t efx_pcm_mixer[NUM_EFX_PLAYBACK];
1115 snd_kcontrol_t *ctl_send_routing;
1116 snd_kcontrol_t *ctl_send_volume;
1117 snd_kcontrol_t *ctl_attn;
1118 snd_kcontrol_t *ctl_efx_send_routing;
1119 snd_kcontrol_t *ctl_efx_send_volume;
1120 snd_kcontrol_t *ctl_efx_attn;
1121
1122 void (*hwvol_interrupt)(emu10k1_t *emu, unsigned int status);
1123 void (*capture_interrupt)(emu10k1_t *emu, unsigned int status);
1124 void (*capture_mic_interrupt)(emu10k1_t *emu, unsigned int status);
1125 void (*capture_efx_interrupt)(emu10k1_t *emu, unsigned int status);
1126 void (*spdif_interrupt)(emu10k1_t *emu, unsigned int status);
1127 void (*dsp_interrupt)(emu10k1_t *emu);
1128
1129 snd_pcm_substream_t *pcm_capture_substream;
1130 snd_pcm_substream_t *pcm_capture_mic_substream;
1131 snd_pcm_substream_t *pcm_capture_efx_substream;
1132 snd_pcm_substream_t *pcm_playback_efx_substream;
1133
1134 snd_timer_t *timer;
1135
1136 emu10k1_midi_t midi;
1137 emu10k1_midi_t midi2; /* for audigy */
1138
1139 unsigned int efx_voices_mask[2];
1140 unsigned int next_free_voice;
1141};
1142
1143int snd_emu10k1_create(snd_card_t * card,
1144 struct pci_dev *pci,
1145 unsigned short extin_mask,
1146 unsigned short extout_mask,
1147 long max_cache_bytes,
1148 int enable_ir,
1149 emu10k1_t ** remu);
1150
1151int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1152int snd_emu10k1_pcm_mic(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1153int snd_emu10k1_pcm_efx(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1154int snd_p16v_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1155int snd_p16v_free(emu10k1_t * emu);
1156int snd_p16v_mixer(emu10k1_t * emu);
1157int snd_emu10k1_pcm_multi(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1158int snd_emu10k1_fx8010_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1159int snd_emu10k1_mixer(emu10k1_t * emu);
1160int snd_emu10k1_timer(emu10k1_t * emu, int device);
1161int snd_emu10k1_fx8010_new(emu10k1_t *emu, int device, snd_hwdep_t ** rhwdep);
1162
1163irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1164
1165/* initialization */
1166void snd_emu10k1_voice_init(emu10k1_t * emu, int voice);
1167int snd_emu10k1_init_efx(emu10k1_t *emu);
1168void snd_emu10k1_free_efx(emu10k1_t *emu);
1169int snd_emu10k1_fx8010_tram_setup(emu10k1_t *emu, u32 size);
1170
1171/* I/O functions */
1172unsigned int snd_emu10k1_ptr_read(emu10k1_t * emu, unsigned int reg, unsigned int chn);
1173void snd_emu10k1_ptr_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data);
1174unsigned int snd_emu10k1_ptr20_read(emu10k1_t * emu, unsigned int reg, unsigned int chn);
1175void snd_emu10k1_ptr20_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data);
1176unsigned int snd_emu10k1_efx_read(emu10k1_t *emu, unsigned int pc);
1177void snd_emu10k1_intr_enable(emu10k1_t *emu, unsigned int intrenb);
1178void snd_emu10k1_intr_disable(emu10k1_t *emu, unsigned int intrenb);
1179void snd_emu10k1_voice_intr_enable(emu10k1_t *emu, unsigned int voicenum);
1180void snd_emu10k1_voice_intr_disable(emu10k1_t *emu, unsigned int voicenum);
1181void snd_emu10k1_voice_intr_ack(emu10k1_t *emu, unsigned int voicenum);
1182void snd_emu10k1_voice_half_loop_intr_enable(emu10k1_t *emu, unsigned int voicenum);
1183void snd_emu10k1_voice_half_loop_intr_disable(emu10k1_t *emu, unsigned int voicenum);
1184void snd_emu10k1_voice_half_loop_intr_ack(emu10k1_t *emu, unsigned int voicenum);
1185void snd_emu10k1_voice_set_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1186void snd_emu10k1_voice_clear_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1187void snd_emu10k1_wait(emu10k1_t *emu, unsigned int wait);
1188static inline unsigned int snd_emu10k1_wc(emu10k1_t *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1189unsigned short snd_emu10k1_ac97_read(ac97_t *ac97, unsigned short reg);
1190void snd_emu10k1_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short data);
1191unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1192
1193/* memory allocation */
1194snd_util_memblk_t *snd_emu10k1_alloc_pages(emu10k1_t *emu, snd_pcm_substream_t *substream);
1195int snd_emu10k1_free_pages(emu10k1_t *emu, snd_util_memblk_t *blk);
1196snd_util_memblk_t *snd_emu10k1_synth_alloc(emu10k1_t *emu, unsigned int size);
1197int snd_emu10k1_synth_free(emu10k1_t *emu, snd_util_memblk_t *blk);
1198int snd_emu10k1_synth_bzero(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, int size);
1199int snd_emu10k1_synth_copy_from_user(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, const char __user *data, int size);
1200int snd_emu10k1_memblk_map(emu10k1_t *emu, emu10k1_memblk_t *blk);
1201
1202/* voice allocation */
1203int snd_emu10k1_voice_alloc(emu10k1_t *emu, emu10k1_voice_type_t type, int pair, emu10k1_voice_t **rvoice);
1204int snd_emu10k1_voice_free(emu10k1_t *emu, emu10k1_voice_t *pvoice);
1205
1206/* MIDI uart */
1207int snd_emu10k1_midi(emu10k1_t * emu);
1208int snd_emu10k1_audigy_midi(emu10k1_t * emu);
1209
1210/* proc interface */
1211int snd_emu10k1_proc_init(emu10k1_t * emu);
1212
1213/* fx8010 irq handler */
1214int snd_emu10k1_fx8010_register_irq_handler(emu10k1_t *emu,
1215 snd_fx8010_irq_handler_t *handler,
1216 unsigned char gpr_running,
1217 void *private_data,
1218 snd_emu10k1_fx8010_irq_t **r_irq);
1219int snd_emu10k1_fx8010_unregister_irq_handler(emu10k1_t *emu,
1220 snd_emu10k1_fx8010_irq_t *irq);
1221
1222#endif /* __KERNEL__ */
1223
1224/*
1225 * ---- FX8010 ----
1226 */
1227
1228#define EMU10K1_CARD_CREATIVE 0x00000000
1229#define EMU10K1_CARD_EMUAPS 0x00000001
1230
1231#define EMU10K1_FX8010_PCM_COUNT 8
1232
1233/* instruction set */
1234#define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
1235#define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
1236#define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
1237#define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
1238#define iMACINT0 0x04 /* R = A + X * Y ; saturation */
1239#define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
1240#define iACC3 0x06 /* R = A + X + Y ; saturation */
1241#define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
1242#define iANDXOR 0x08 /* R = (A & X) ^ Y */
1243#define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
1244#define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
1245#define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
1246#define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
1247#define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
1248#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
1249#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
1250
1251/* GPRs */
1252#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
1253#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
1254#define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
1255#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
1256 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
1257
1258#define C_00000000 0x40
1259#define C_00000001 0x41
1260#define C_00000002 0x42
1261#define C_00000003 0x43
1262#define C_00000004 0x44
1263#define C_00000008 0x45
1264#define C_00000010 0x46
1265#define C_00000020 0x47
1266#define C_00000100 0x48
1267#define C_00010000 0x49
1268#define C_00080000 0x4a
1269#define C_10000000 0x4b
1270#define C_20000000 0x4c
1271#define C_40000000 0x4d
1272#define C_80000000 0x4e
1273#define C_7fffffff 0x4f
1274#define C_ffffffff 0x50
1275#define C_fffffffe 0x51
1276#define C_c0000000 0x52
1277#define C_4f1bbcdc 0x53
1278#define C_5a7ef9db 0x54
1279#define C_00100000 0x55 /* ?? */
1280#define GPR_ACCU 0x56 /* ACCUM, accumulator */
1281#define GPR_COND 0x57 /* CCR, condition register */
1282#define GPR_NOISE0 0x58 /* noise source */
1283#define GPR_NOISE1 0x59 /* noise source */
1284#define GPR_IRQ 0x5a /* IRQ register */
1285#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
1286#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
1287#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1288#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1289#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1290#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1291
1292#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1293#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1294#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1295#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1296#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1297#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1298
1299#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
1300#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
1301#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
1302#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
1303#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
1304#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
1305#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
1306#define A_GPR(x) (A_FXGPREGBASE + (x))
1307
1308/* cc_reg constants */
1309#define CC_REG_NORMALIZED C_00000001
1310#define CC_REG_BORROW C_00000002
1311#define CC_REG_MINUS C_00000004
1312#define CC_REG_ZERO C_00000008
1313#define CC_REG_SATURATE C_00000010
1314#define CC_REG_NONZERO C_00000100
1315
1316/* FX buses */
1317#define FXBUS_PCM_LEFT 0x00
1318#define FXBUS_PCM_RIGHT 0x01
1319#define FXBUS_PCM_LEFT_REAR 0x02
1320#define FXBUS_PCM_RIGHT_REAR 0x03
1321#define FXBUS_MIDI_LEFT 0x04
1322#define FXBUS_MIDI_RIGHT 0x05
1323#define FXBUS_PCM_CENTER 0x06
1324#define FXBUS_PCM_LFE 0x07
1325#define FXBUS_PCM_LEFT_FRONT 0x08
1326#define FXBUS_PCM_RIGHT_FRONT 0x09
1327#define FXBUS_MIDI_REVERB 0x0c
1328#define FXBUS_MIDI_CHORUS 0x0d
1329#define FXBUS_PCM_LEFT_SIDE 0x0e
1330#define FXBUS_PCM_RIGHT_SIDE 0x0f
1331#define FXBUS_PT_LEFT 0x14
1332#define FXBUS_PT_RIGHT 0x15
1333
1334/* Inputs */
1335#define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1336#define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1337#define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
1338#define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
1339#define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
1340#define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
1341#define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
1342#define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
1343#define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
1344#define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
1345#define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
1346#define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
1347#define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
1348#define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
1349
1350/* Outputs */
1351#define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
1352#define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
1353#define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
1354#define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
1355#define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
1356#define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
1357#define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
1358#define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
1359#define EXTOUT_REAR_L 0x08 /* Rear channel - left */
1360#define EXTOUT_REAR_R 0x09 /* Rear channel - right */
1361#define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
1362#define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
1363#define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
1364#define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
1365#define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
1366#define EXTOUT_ACENTER 0x11 /* Analog Center */
1367#define EXTOUT_ALFE 0x12 /* Analog LFE */
1368
1369/* Audigy Inputs */
1370#define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1371#define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1372#define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
1373#define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
1374#define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
1375#define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
1376#define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
1377#define A_EXTIN_LINE2_R 0x09 /* right */
1378#define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
1379#define A_EXTIN_ADC_R 0x0b /* right */
1380#define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
1381#define A_EXTIN_AUX2_R 0x0d /* - right */
1382
1383/* Audigiy Outputs */
1384#define A_EXTOUT_FRONT_L 0x00 /* digital front left */
1385#define A_EXTOUT_FRONT_R 0x01 /* right */
1386#define A_EXTOUT_CENTER 0x02 /* digital front center */
1387#define A_EXTOUT_LFE 0x03 /* digital front lfe */
1388#define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
1389#define A_EXTOUT_HEADPHONE_R 0x05 /* right */
1390#define A_EXTOUT_REAR_L 0x06 /* digital rear left */
1391#define A_EXTOUT_REAR_R 0x07 /* right */
1392#define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
1393#define A_EXTOUT_AFRONT_R 0x09 /* right */
1394#define A_EXTOUT_ACENTER 0x0a /* analog center */
1395#define A_EXTOUT_ALFE 0x0b /* analog LFE */
1396#define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
1397#define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
1398#define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
1399#define A_EXTOUT_AREAR_R 0x0f /* right */
1400#define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
1401#define A_EXTOUT_AC97_R 0x11 /* right */
1402#define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
1403#define A_EXTOUT_ADC_CAP_R 0x17 /* right */
1404#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
1405
1406/* Audigy constants */
1407#define A_C_00000000 0xc0
1408#define A_C_00000001 0xc1
1409#define A_C_00000002 0xc2
1410#define A_C_00000003 0xc3
1411#define A_C_00000004 0xc4
1412#define A_C_00000008 0xc5
1413#define A_C_00000010 0xc6
1414#define A_C_00000020 0xc7
1415#define A_C_00000100 0xc8
1416#define A_C_00010000 0xc9
1417#define A_C_00000800 0xca
1418#define A_C_10000000 0xcb
1419#define A_C_20000000 0xcc
1420#define A_C_40000000 0xcd
1421#define A_C_80000000 0xce
1422#define A_C_7fffffff 0xcf
1423#define A_C_ffffffff 0xd0
1424#define A_C_fffffffe 0xd1
1425#define A_C_c0000000 0xd2
1426#define A_C_4f1bbcdc 0xd3
1427#define A_C_5a7ef9db 0xd4
1428#define A_C_00100000 0xd5
1429#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
1430#define A_GPR_COND 0xd7 /* CCR, condition register */
1431#define A_GPR_NOISE0 0xd8 /* noise source */
1432#define A_GPR_NOISE1 0xd9 /* noise source */
1433#define A_GPR_IRQ 0xda /* IRQ register */
1434#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
1435#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
1436
1437/* definitions for debug register */
1438#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
1439#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
1440#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
1441#define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
1442#define EMU10K1_DBG_STEP 0x00004000 /* start single step */
1443#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
1444#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
1445
1446/* tank memory address line */
1447#ifndef __KERNEL__
1448#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
1449#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
1450#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
1451#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
1452#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
1453#endif
1454
1455typedef struct {
1456 unsigned int card; /* card type */
1457 unsigned int internal_tram_size; /* in samples */
1458 unsigned int external_tram_size; /* in samples */
1459 char fxbus_names[16][32]; /* names of FXBUSes */
1460 char extin_names[16][32]; /* names of external inputs */
1461 char extout_names[32][32]; /* names of external outputs */
1462 unsigned int gpr_controls; /* count of GPR controls */
1463} emu10k1_fx8010_info_t;
1464
1465#define EMU10K1_GPR_TRANSLATION_NONE 0
1466#define EMU10K1_GPR_TRANSLATION_TABLE100 1
1467#define EMU10K1_GPR_TRANSLATION_BASS 2
1468#define EMU10K1_GPR_TRANSLATION_TREBLE 3
1469#define EMU10K1_GPR_TRANSLATION_ONOFF 4
1470
1471typedef struct {
1472 snd_ctl_elem_id_t id; /* full control ID definition */
1473 unsigned int vcount; /* visible count */
1474 unsigned int count; /* count of GPR (1..16) */
1475 unsigned short gpr[32]; /* GPR number(s) */
1476 unsigned int value[32]; /* initial values */
1477 unsigned int min; /* minimum range */
1478 unsigned int max; /* maximum range */
1479 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1480} emu10k1_fx8010_control_gpr_t;
1481
1482typedef struct {
1483 char name[128];
1484
1485 DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
1486 u_int32_t __user *gpr_map; /* initializers */
1487
1488 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
1489 emu10k1_fx8010_control_gpr_t __user *gpr_add_controls; /* GPR controls to add/replace */
1490
1491 unsigned int gpr_del_control_count; /* count of GPR controls to remove */
1492 snd_ctl_elem_id_t __user *gpr_del_controls; /* IDs of GPR controls to remove */
1493
1494 unsigned int gpr_list_control_count; /* count of GPR controls to list */
1495 unsigned int gpr_list_control_total; /* total count of GPR controls */
1496 emu10k1_fx8010_control_gpr_t __user *gpr_list_controls; /* listed GPR controls */
1497
1498 DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
1499 u_int32_t __user *tram_data_map; /* data initializers */
1500 u_int32_t __user *tram_addr_map; /* map initializers */
1501
1502 DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
1503 u_int32_t __user *code; /* one instruction - 64 bits */
1504} emu10k1_fx8010_code_t;
1505
1506typedef struct {
1507 unsigned int address; /* 31.bit == 1 -> external TRAM */
1508 unsigned int size; /* size in samples (4 bytes) */
1509 unsigned int *samples; /* pointer to samples (20-bit) */
1510 /* NULL->clear memory */
1511} emu10k1_fx8010_tram_t;
1512
1513typedef struct {
1514 unsigned int substream; /* substream number */
1515 unsigned int res1; /* reserved */
1516 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
1517 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
1518 unsigned int buffer_size; /* count of buffered samples */
1519 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
1520 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1521 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1522 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1523 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1524 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1525 unsigned char pad; /* reserved */
1526 unsigned char etram[32]; /* external TRAM address & data (one per channel) */
1527 unsigned int res2; /* reserved */
1528} emu10k1_fx8010_pcm_t;
1529
1530#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, emu10k1_fx8010_info_t)
1531#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, emu10k1_fx8010_code_t)
1532#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, emu10k1_fx8010_code_t)
1533#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
1534#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, emu10k1_fx8010_tram_t)
1535#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, emu10k1_fx8010_tram_t)
1536#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, emu10k1_fx8010_pcm_t)
1537#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, emu10k1_fx8010_pcm_t)
1538#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
1539#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
1540#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
1541#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
1542#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
1543
1544#endif /* __SOUND_EMU10K1_H */
diff --git a/include/sound/emu10k1_synth.h b/include/sound/emu10k1_synth.h
new file mode 100644
index 000000000000..df0df1d09552
--- /dev/null
+++ b/include/sound/emu10k1_synth.h
@@ -0,0 +1,39 @@
1#ifndef __EMU10K1_SYNTH_H
2#define __EMU10K1_SYNTH_H
3/*
4 * Defines for the Emu10k1 WaveTable synth
5 *
6 * Copyright (C) 2000 Takashi Iwai <tiwai@suse.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include "emu10k1.h"
24#include "emux_synth.h"
25
26/* sequencer device id */
27#define SNDRV_SEQ_DEV_ID_EMU10K1_SYNTH "emu10k1-synth"
28
29/* argument for snd_seq_device_new */
30typedef struct snd_emu10k1_synth_arg {
31 emu10k1_t *hwptr; /* chip */
32 int index; /* sequencer client index */
33 int seq_ports; /* number of sequencer ports to be created */
34 int max_voices; /* maximum number of voices for wavetable */
35} snd_emu10k1_synth_arg_t;
36
37#define EMU10K1_MAX_MEMSIZE (32 * 1024 * 1024) /* 32MB */
38
39#endif
diff --git a/include/sound/emu8000.h b/include/sound/emu8000.h
new file mode 100644
index 000000000000..4362c54e09d0
--- /dev/null
+++ b/include/sound/emu8000.h
@@ -0,0 +1,120 @@
1#ifndef __SOUND_EMU8000_H
2#define __SOUND_EMU8000_H
3/*
4 * Defines for the emu8000 (AWE32/64)
5 *
6 * Copyright (C) 1999 Steve Ratcliffe
7 * Copyright (C) 1999-2000 Takashi Iwai <tiwai@suse.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include "emux_synth.h"
25#include "seq_kernel.h"
26
27/*
28 * Hardware parameters.
29 */
30#define EMU8000_MAX_DRAM (28 * 1024 * 1024) /* Max on-board mem is 28Mb ???*/
31#define EMU8000_DRAM_OFFSET 0x200000 /* Beginning of on board ram */
32#define EMU8000_CHANNELS 32 /* Number of hardware channels */
33#define EMU8000_DRAM_VOICES 30 /* number of normal voices */
34
35/* Flags to set a dma channel to read or write */
36#define EMU8000_RAM_READ 0
37#define EMU8000_RAM_WRITE 1
38#define EMU8000_RAM_CLOSE 2
39#define EMU8000_RAM_MODE_MASK 0x03
40#define EMU8000_RAM_RIGHT 0x10 /* use 'right' DMA channel */
41
42enum {
43 EMU8000_CONTROL_BASS = 0,
44 EMU8000_CONTROL_TREBLE,
45 EMU8000_CONTROL_CHORUS_MODE,
46 EMU8000_CONTROL_REVERB_MODE,
47 EMU8000_CONTROL_FM_CHORUS_DEPTH,
48 EMU8000_CONTROL_FM_REVERB_DEPTH,
49 EMU8000_NUM_CONTROLS,
50};
51
52/*
53 * Structure to hold all state information for the emu8000 driver.
54 *
55 * Note 1: The chip supports 32 channels in hardware this is max_channels
56 * some of the channels may be used for other things so max_channels is
57 * the number in use for wave voices.
58 */
59typedef struct snd_emu8000 {
60
61 snd_emux_t *emu;
62
63 int index; /* sequencer client index */
64 int seq_ports; /* number of sequencer ports */
65 int fm_chorus_depth; /* FM OPL3 chorus depth */
66 int fm_reverb_depth; /* FM OPL3 reverb depth */
67
68 int mem_size; /* memory size */
69 unsigned long port1; /* Port usually base+0 */
70 unsigned long port2; /* Port usually at base+0x400 */
71 unsigned long port3; /* Port usually at base+0x800 */
72 struct resource *res_port1;
73 struct resource *res_port2;
74 struct resource *res_port3;
75 unsigned short last_reg;/* Last register command */
76 spinlock_t reg_lock;
77
78 int dram_checked;
79
80 snd_card_t *card; /* The card that this belongs to */
81
82 int chorus_mode;
83 int reverb_mode;
84 int bass_level;
85 int treble_level;
86
87 snd_util_memhdr_t *memhdr;
88
89 spinlock_t control_lock;
90 snd_kcontrol_t *controls[EMU8000_NUM_CONTROLS];
91
92 snd_pcm_t *pcm; /* pcm on emu8000 wavetable */
93
94} emu8000_t;
95
96/* sequencer device id */
97#define SNDRV_SEQ_DEV_ID_EMU8000 "emu8000-synth"
98
99
100/* exported functions */
101int snd_emu8000_new(snd_card_t *card, int device, long port, int seq_ports, snd_seq_device_t **ret);
102void snd_emu8000_poke(emu8000_t *emu, unsigned int port, unsigned int reg,
103 unsigned int val);
104unsigned short snd_emu8000_peek(emu8000_t *emu, unsigned int port,
105 unsigned int reg);
106void snd_emu8000_poke_dw(emu8000_t *emu, unsigned int port, unsigned int reg,
107 unsigned int val);
108unsigned int snd_emu8000_peek_dw(emu8000_t *emu, unsigned int port,
109 unsigned int reg);
110void snd_emu8000_dma_chan(emu8000_t *emu, int ch, int mode);
111
112void snd_emu8000_init_fm(emu8000_t *emu);
113
114void snd_emu8000_update_chorus_mode(emu8000_t *emu);
115void snd_emu8000_update_reverb_mode(emu8000_t *emu);
116void snd_emu8000_update_equalizer(emu8000_t *emu);
117int snd_emu8000_load_chorus_fx(emu8000_t *emu, int mode, const void __user *buf, long len);
118int snd_emu8000_load_reverb_fx(emu8000_t *emu, int mode, const void __user *buf, long len);
119
120#endif /* __SOUND_EMU8000_H */
diff --git a/include/sound/emu8000_reg.h b/include/sound/emu8000_reg.h
new file mode 100644
index 000000000000..4b9827ac4960
--- /dev/null
+++ b/include/sound/emu8000_reg.h
@@ -0,0 +1,207 @@
1#ifndef __SOUND_EMU8000_REG_H
2#define __SOUND_EMU8000_REG_H
3/*
4 * Register operations for the EMU8000
5 *
6 * Copyright (C) 1999 Steve Ratcliffe
7 *
8 * Based on awe_wave.c by Takashi Iwai
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26/*
27 * Data port addresses relative to the EMU base.
28 */
29#define EMU8000_DATA0(e) ((e)->port1)
30#define EMU8000_DATA1(e) ((e)->port2)
31#define EMU8000_DATA2(e) ((e)->port2+2)
32#define EMU8000_DATA3(e) ((e)->port3)
33#define EMU8000_PTR(e) ((e)->port3+2)
34
35/*
36 * Make a command from a register and channel.
37 */
38#define EMU8000_CMD(reg, chan) ((reg)<<5 | (chan))
39
40/*
41 * Commands to read and write the EMU8000 registers.
42 * These macros should be used for all register accesses.
43 */
44#define EMU8000_CPF_READ(emu, chan) \
45 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)))
46#define EMU8000_PTRX_READ(emu, chan) \
47 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)))
48#define EMU8000_CVCF_READ(emu, chan) \
49 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)))
50#define EMU8000_VTFT_READ(emu, chan) \
51 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)))
52#define EMU8000_PSST_READ(emu, chan) \
53 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)))
54#define EMU8000_CSL_READ(emu, chan) \
55 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan)))
56#define EMU8000_CCCA_READ(emu, chan) \
57 snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan)))
58#define EMU8000_HWCF4_READ(emu) \
59 snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9))
60#define EMU8000_HWCF5_READ(emu) \
61 snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10))
62#define EMU8000_HWCF6_READ(emu) \
63 snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13))
64#define EMU8000_SMALR_READ(emu) \
65 snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20))
66#define EMU8000_SMARR_READ(emu) \
67 snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21))
68#define EMU8000_SMALW_READ(emu) \
69 snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22))
70#define EMU8000_SMARW_READ(emu) \
71 snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23))
72#define EMU8000_SMLD_READ(emu) \
73 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26))
74#define EMU8000_SMRD_READ(emu) \
75 snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26))
76#define EMU8000_WC_READ(emu) \
77 snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27))
78#define EMU8000_HWCF1_READ(emu) \
79 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29))
80#define EMU8000_HWCF2_READ(emu) \
81 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30))
82#define EMU8000_HWCF3_READ(emu) \
83 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31))
84#define EMU8000_INIT1_READ(emu, chan) \
85 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan)))
86#define EMU8000_INIT2_READ(emu, chan) \
87 snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan)))
88#define EMU8000_INIT3_READ(emu, chan) \
89 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan)))
90#define EMU8000_INIT4_READ(emu, chan) \
91 snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan)))
92#define EMU8000_ENVVOL_READ(emu, chan) \
93 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan)))
94#define EMU8000_DCYSUSV_READ(emu, chan) \
95 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan)))
96#define EMU8000_ENVVAL_READ(emu, chan) \
97 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan)))
98#define EMU8000_DCYSUS_READ(emu, chan) \
99 snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan)))
100#define EMU8000_ATKHLDV_READ(emu, chan) \
101 snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan)))
102#define EMU8000_LFO1VAL_READ(emu, chan) \
103 snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan)))
104#define EMU8000_ATKHLD_READ(emu, chan) \
105 snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan)))
106#define EMU8000_LFO2VAL_READ(emu, chan) \
107 snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan)))
108#define EMU8000_IP_READ(emu, chan) \
109 snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan)))
110#define EMU8000_IFATN_READ(emu, chan) \
111 snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan)))
112#define EMU8000_PEFE_READ(emu, chan) \
113 snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan)))
114#define EMU8000_FMMOD_READ(emu, chan) \
115 snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan)))
116#define EMU8000_TREMFRQ_READ(emu, chan) \
117 snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan)))
118#define EMU8000_FM2FRQ2_READ(emu, chan) \
119 snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan)))
120
121
122#define EMU8000_CPF_WRITE(emu, chan, val) \
123 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val))
124#define EMU8000_PTRX_WRITE(emu, chan, val) \
125 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val))
126#define EMU8000_CVCF_WRITE(emu, chan, val) \
127 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val))
128#define EMU8000_VTFT_WRITE(emu, chan, val) \
129 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val))
130#define EMU8000_PSST_WRITE(emu, chan, val) \
131 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val))
132#define EMU8000_CSL_WRITE(emu, chan, val) \
133 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan)), (val))
134#define EMU8000_CCCA_WRITE(emu, chan, val) \
135 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan)), (val))
136#define EMU8000_HWCF4_WRITE(emu, val) \
137 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9), (val))
138#define EMU8000_HWCF5_WRITE(emu, val) \
139 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10), (val))
140#define EMU8000_HWCF6_WRITE(emu, val) \
141 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13), (val))
142/* this register is not documented */
143#define EMU8000_HWCF7_WRITE(emu, val) \
144 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 14), (val))
145#define EMU8000_SMALR_WRITE(emu, val) \
146 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20), (val))
147#define EMU8000_SMARR_WRITE(emu, val) \
148 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21), (val))
149#define EMU8000_SMALW_WRITE(emu, val) \
150 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22), (val))
151#define EMU8000_SMARW_WRITE(emu, val) \
152 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23), (val))
153#define EMU8000_SMLD_WRITE(emu, val) \
154 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26), (val))
155#define EMU8000_SMRD_WRITE(emu, val) \
156 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26), (val))
157#define EMU8000_WC_WRITE(emu, val) \
158 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27), (val))
159#define EMU8000_HWCF1_WRITE(emu, val) \
160 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29), (val))
161#define EMU8000_HWCF2_WRITE(emu, val) \
162 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30), (val))
163#define EMU8000_HWCF3_WRITE(emu, val) \
164 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31), (val))
165#define EMU8000_INIT1_WRITE(emu, chan, val) \
166 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan)), (val))
167#define EMU8000_INIT2_WRITE(emu, chan, val) \
168 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan)), (val))
169#define EMU8000_INIT3_WRITE(emu, chan, val) \
170 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan)), (val))
171#define EMU8000_INIT4_WRITE(emu, chan, val) \
172 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan)), (val))
173#define EMU8000_ENVVOL_WRITE(emu, chan, val) \
174 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan)), (val))
175#define EMU8000_DCYSUSV_WRITE(emu, chan, val) \
176 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan)), (val))
177#define EMU8000_ENVVAL_WRITE(emu, chan, val) \
178 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan)), (val))
179#define EMU8000_DCYSUS_WRITE(emu, chan, val) \
180 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan)), (val))
181#define EMU8000_ATKHLDV_WRITE(emu, chan, val) \
182 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan)), (val))
183#define EMU8000_LFO1VAL_WRITE(emu, chan, val) \
184 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan)), (val))
185#define EMU8000_ATKHLD_WRITE(emu, chan, val) \
186 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan)), (val))
187#define EMU8000_LFO2VAL_WRITE(emu, chan, val) \
188 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan)), (val))
189#define EMU8000_IP_WRITE(emu, chan, val) \
190 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan)), (val))
191#define EMU8000_IFATN_WRITE(emu, chan, val) \
192 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan)), (val))
193#define EMU8000_PEFE_WRITE(emu, chan, val) \
194 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan)), (val))
195#define EMU8000_FMMOD_WRITE(emu, chan, val) \
196 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan)), (val))
197#define EMU8000_TREMFRQ_WRITE(emu, chan, val) \
198 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan)), (val))
199#define EMU8000_FM2FRQ2_WRITE(emu, chan, val) \
200 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan)), (val))
201
202#define EMU8000_0080_WRITE(emu, chan, val) \
203 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(4, (chan)), (val))
204#define EMU8000_00A0_WRITE(emu, chan, val) \
205 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(5, (chan)), (val))
206
207#endif /* __SOUND_EMU8000_REG_H */
diff --git a/include/sound/emux_legacy.h b/include/sound/emux_legacy.h
new file mode 100644
index 000000000000..6fe3da2a5e15
--- /dev/null
+++ b/include/sound/emux_legacy.h
@@ -0,0 +1,146 @@
1#ifndef __SOUND_EMUX_LEGACY_H
2#define __SOUND_EMUX_LEGACY_H
3
4/*
5 * Copyright (c) 1999-2000 Takashi Iwai <tiwai@suse.de>
6 *
7 * Definitions of OSS compatible headers for Emu8000 device informations
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "seq_oss_legacy.h"
26
27/*
28 * awe hardware controls
29 */
30
31#define _EMUX_OSS_DEBUG_MODE 0x00
32#define _EMUX_OSS_REVERB_MODE 0x01
33#define _EMUX_OSS_CHORUS_MODE 0x02
34#define _EMUX_OSS_REMOVE_LAST_SAMPLES 0x03
35#define _EMUX_OSS_INITIALIZE_CHIP 0x04
36#define _EMUX_OSS_SEND_EFFECT 0x05
37#define _EMUX_OSS_TERMINATE_CHANNEL 0x06
38#define _EMUX_OSS_TERMINATE_ALL 0x07
39#define _EMUX_OSS_INITIAL_VOLUME 0x08
40#define _EMUX_OSS_INITIAL_ATTEN _EMUX_OSS_INITIAL_VOLUME
41#define _EMUX_OSS_RESET_CHANNEL 0x09
42#define _EMUX_OSS_CHANNEL_MODE 0x0a
43#define _EMUX_OSS_DRUM_CHANNELS 0x0b
44#define _EMUX_OSS_MISC_MODE 0x0c
45#define _EMUX_OSS_RELEASE_ALL 0x0d
46#define _EMUX_OSS_NOTEOFF_ALL 0x0e
47#define _EMUX_OSS_CHN_PRESSURE 0x0f
48#define _EMUX_OSS_EQUALIZER 0x11
49
50#define _EMUX_OSS_MODE_FLAG 0x80
51#define _EMUX_OSS_COOKED_FLAG 0x40 /* not supported */
52#define _EMUX_OSS_MODE_VALUE_MASK 0x3F
53
54
55/*
56 * mode type definitions
57 */
58enum {
59/* 0*/ EMUX_MD_EXCLUSIVE_OFF, /* obsolete */
60/* 1*/ EMUX_MD_EXCLUSIVE_ON, /* obsolete */
61/* 2*/ EMUX_MD_VERSION, /* read only */
62/* 3*/ EMUX_MD_EXCLUSIVE_SOUND, /* 0/1: exclusive note on (default=1) */
63/* 4*/ EMUX_MD_REALTIME_PAN, /* 0/1: do realtime pan change (default=1) */
64/* 5*/ EMUX_MD_GUS_BANK, /* bank number for GUS patches (default=0) */
65/* 6*/ EMUX_MD_KEEP_EFFECT, /* 0/1: keep effect values, (default=0) */
66/* 7*/ EMUX_MD_ZERO_ATTEN, /* attenuation of max volume (default=32) */
67/* 8*/ EMUX_MD_CHN_PRIOR, /* 0/1: set MIDI channel priority mode (default=1) */
68/* 9*/ EMUX_MD_MOD_SENSE, /* integer: modwheel sensitivity (def=18) */
69/*10*/ EMUX_MD_DEF_PRESET, /* integer: default preset number (def=0) */
70/*11*/ EMUX_MD_DEF_BANK, /* integer: default bank number (def=0) */
71/*12*/ EMUX_MD_DEF_DRUM, /* integer: default drumset number (def=0) */
72/*13*/ EMUX_MD_TOGGLE_DRUM_BANK, /* 0/1: toggle drum flag with bank# (def=0) */
73/*14*/ EMUX_MD_NEW_VOLUME_CALC, /* 0/1: volume calculation mode (def=1) */
74/*15*/ EMUX_MD_CHORUS_MODE, /* integer: chorus mode (def=2) */
75/*16*/ EMUX_MD_REVERB_MODE, /* integer: chorus mode (def=4) */
76/*17*/ EMUX_MD_BASS_LEVEL, /* integer: bass level (def=5) */
77/*18*/ EMUX_MD_TREBLE_LEVEL, /* integer: treble level (def=9) */
78/*19*/ EMUX_MD_DEBUG_MODE, /* integer: debug level (def=0) */
79/*20*/ EMUX_MD_PAN_EXCHANGE, /* 0/1: exchange panning direction (def=0) */
80 EMUX_MD_END,
81};
82
83
84/*
85 * effect parameters
86 */
87enum {
88
89/* modulation envelope parameters */
90/* 0*/ EMUX_FX_ENV1_DELAY, /* WORD: ENVVAL */
91/* 1*/ EMUX_FX_ENV1_ATTACK, /* BYTE: up ATKHLD */
92/* 2*/ EMUX_FX_ENV1_HOLD, /* BYTE: lw ATKHLD */
93/* 3*/ EMUX_FX_ENV1_DECAY, /* BYTE: lw DCYSUS */
94/* 4*/ EMUX_FX_ENV1_RELEASE, /* BYTE: lw DCYSUS */
95/* 5*/ EMUX_FX_ENV1_SUSTAIN, /* BYTE: up DCYSUS */
96/* 6*/ EMUX_FX_ENV1_PITCH, /* BYTE: up PEFE */
97/* 7*/ EMUX_FX_ENV1_CUTOFF, /* BYTE: lw PEFE */
98
99/* volume envelope parameters */
100/* 8*/ EMUX_FX_ENV2_DELAY, /* WORD: ENVVOL */
101/* 9*/ EMUX_FX_ENV2_ATTACK, /* BYTE: up ATKHLDV */
102/*10*/ EMUX_FX_ENV2_HOLD, /* BYTE: lw ATKHLDV */
103/*11*/ EMUX_FX_ENV2_DECAY, /* BYTE: lw DCYSUSV */
104/*12*/ EMUX_FX_ENV2_RELEASE, /* BYTE: lw DCYSUSV */
105/*13*/ EMUX_FX_ENV2_SUSTAIN, /* BYTE: up DCYSUSV */
106
107/* LFO1 (tremolo & vibrato) parameters */
108/*14*/ EMUX_FX_LFO1_DELAY, /* WORD: LFO1VAL */
109/*15*/ EMUX_FX_LFO1_FREQ, /* BYTE: lo TREMFRQ */
110/*16*/ EMUX_FX_LFO1_VOLUME, /* BYTE: up TREMFRQ */
111/*17*/ EMUX_FX_LFO1_PITCH, /* BYTE: up FMMOD */
112/*18*/ EMUX_FX_LFO1_CUTOFF, /* BYTE: lo FMMOD */
113
114/* LFO2 (vibrato) parameters */
115/*19*/ EMUX_FX_LFO2_DELAY, /* WORD: LFO2VAL */
116/*20*/ EMUX_FX_LFO2_FREQ, /* BYTE: lo FM2FRQ2 */
117/*21*/ EMUX_FX_LFO2_PITCH, /* BYTE: up FM2FRQ2 */
118
119/* Other overall effect parameters */
120/*22*/ EMUX_FX_INIT_PITCH, /* SHORT: pitch offset */
121/*23*/ EMUX_FX_CHORUS, /* BYTE: chorus effects send (0-255) */
122/*24*/ EMUX_FX_REVERB, /* BYTE: reverb effects send (0-255) */
123/*25*/ EMUX_FX_CUTOFF, /* BYTE: up IFATN */
124/*26*/ EMUX_FX_FILTERQ, /* BYTE: up CCCA */
125
126/* Sample / loop offset changes */
127/*27*/ EMUX_FX_SAMPLE_START, /* SHORT: offset */
128/*28*/ EMUX_FX_LOOP_START, /* SHORT: offset */
129/*29*/ EMUX_FX_LOOP_END, /* SHORT: offset */
130/*30*/ EMUX_FX_COARSE_SAMPLE_START, /* SHORT: upper word offset */
131/*31*/ EMUX_FX_COARSE_LOOP_START, /* SHORT: upper word offset */
132/*32*/ EMUX_FX_COARSE_LOOP_END, /* SHORT: upper word offset */
133/*33*/ EMUX_FX_ATTEN, /* BYTE: lo IFATN */
134
135 EMUX_FX_END,
136};
137/* number of effects */
138#define EMUX_NUM_EFFECTS EMUX_FX_END
139
140/* effect flag values */
141#define EMUX_FX_FLAG_OFF 0
142#define EMUX_FX_FLAG_SET 1
143#define EMUX_FX_FLAG_ADD 2
144
145
146#endif /* __SOUND_EMUX_LEGACY_H */
diff --git a/include/sound/emux_synth.h b/include/sound/emux_synth.h
new file mode 100644
index 000000000000..c6970aac9bdc
--- /dev/null
+++ b/include/sound/emux_synth.h
@@ -0,0 +1,243 @@
1#ifndef __SOUND_EMUX_SYNTH_H
2#define __SOUND_EMUX_SYNTH_H
3
4/*
5 * Defines for the Emu-series WaveTable chip
6 *
7 * Copyright (C) 2000 Takashi Iwai <tiwai@suse.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include "seq_kernel.h"
25#include "seq_device.h"
26#include "soundfont.h"
27#include "seq_midi_emul.h"
28#ifdef CONFIG_SND_SEQUENCER_OSS
29#include "seq_oss.h"
30#endif
31#include "emux_legacy.h"
32#include "seq_virmidi.h"
33
34/*
35 * compile flags
36 */
37#define SNDRV_EMUX_USE_RAW_EFFECT
38
39
40/*
41 * typedefs
42 */
43typedef struct snd_emux_effect_table snd_emux_effect_table_t;
44typedef struct snd_emux_port snd_emux_port_t;
45typedef struct snd_emux_voice snd_emux_voice_t;
46typedef struct snd_emux snd_emux_t;
47
48
49/*
50 * operators
51 */
52typedef struct snd_emux_operators {
53 struct module *owner;
54 snd_emux_voice_t *(*get_voice)(snd_emux_t *emu, snd_emux_port_t *port);
55 int (*prepare)(snd_emux_voice_t *vp);
56 void (*trigger)(snd_emux_voice_t *vp);
57 void (*release)(snd_emux_voice_t *vp);
58 void (*update)(snd_emux_voice_t *vp, int update);
59 void (*terminate)(snd_emux_voice_t *vp);
60 void (*free_voice)(snd_emux_voice_t *vp);
61 void (*reset)(snd_emux_t *emu, int ch);
62 /* the first parameters are snd_emux_t */
63 int (*sample_new)(snd_emux_t *emu, snd_sf_sample_t *sp, snd_util_memhdr_t *hdr, const void __user *data, long count);
64 int (*sample_free)(snd_emux_t *emu, snd_sf_sample_t *sp, snd_util_memhdr_t *hdr);
65 void (*sample_reset)(snd_emux_t *emu);
66 int (*load_fx)(snd_emux_t *emu, int type, int arg, const void __user *data, long count);
67 void (*sysex)(snd_emux_t *emu, char *buf, int len, int parsed, snd_midi_channel_set_t *chset);
68#ifdef CONFIG_SND_SEQUENCER_OSS
69 int (*oss_ioctl)(snd_emux_t *emu, int cmd, int p1, int p2);
70#endif
71} snd_emux_operators_t;
72
73
74/*
75 * constant values
76 */
77#define SNDRV_EMUX_MAX_PORTS 32 /* max # of sequencer ports */
78#define SNDRV_EMUX_MAX_VOICES 64 /* max # of voices */
79#define SNDRV_EMUX_MAX_MULTI_VOICES 16 /* max # of playable voices
80 * simultineously
81 */
82
83/*
84 * flags
85 */
86#define SNDRV_EMUX_ACCEPT_ROM (1<<0)
87
88/*
89 * emuX wavetable
90 */
91struct snd_emux {
92
93 snd_card_t *card; /* assigned card */
94
95 /* following should be initialized before registration */
96 int max_voices; /* Number of voices */
97 int mem_size; /* memory size (in byte) */
98 int num_ports; /* number of ports to be created */
99 int pitch_shift; /* pitch shift value (for Emu10k1) */
100 snd_emux_operators_t ops; /* operators */
101 void *hw; /* hardware */
102 unsigned long flags; /* other conditions */
103 int midi_ports; /* number of virtual midi devices */
104 int midi_devidx; /* device offset of virtual midi */
105 unsigned int linear_panning: 1; /* panning is linear (sbawe = 1, emu10k1 = 0) */
106 int hwdep_idx; /* hwdep device index */
107 snd_hwdep_t *hwdep; /* hwdep device */
108
109 /* private */
110 int num_voices; /* current number of voices */
111 snd_sf_list_t *sflist; /* root of SoundFont list */
112 snd_emux_voice_t *voices; /* Voices (EMU 'channel') */
113 int use_time; /* allocation counter */
114 spinlock_t voice_lock; /* Lock for voice access */
115 struct semaphore register_mutex;
116 int client; /* For the sequencer client */
117 int ports[SNDRV_EMUX_MAX_PORTS]; /* The ports for this device */
118 snd_emux_port_t *portptrs[SNDRV_EMUX_MAX_PORTS];
119 int used; /* use counter */
120 char *name; /* name of the device (internal) */
121 snd_rawmidi_t **vmidi;
122 struct timer_list tlist; /* for pending note-offs */
123 int timer_active;
124
125 snd_util_memhdr_t *memhdr; /* memory chunk information */
126
127#ifdef CONFIG_PROC_FS
128 snd_info_entry_t *proc;
129#endif
130
131#ifdef CONFIG_SND_SEQUENCER_OSS
132 snd_seq_device_t *oss_synth;
133#endif
134};
135
136
137/*
138 * sequencer port information
139 */
140struct snd_emux_port {
141
142 snd_midi_channel_set_t chset;
143 snd_emux_t *emu;
144
145 char port_mode; /* operation mode */
146 int volume_atten; /* emuX raw attenuation */
147 unsigned long drum_flags; /* drum bitmaps */
148 int ctrls[EMUX_MD_END]; /* control parameters */
149#ifdef SNDRV_EMUX_USE_RAW_EFFECT
150 snd_emux_effect_table_t *effect;
151#endif
152#ifdef CONFIG_SND_SEQUENCER_OSS
153 snd_seq_oss_arg_t *oss_arg;
154#endif
155};
156
157/* port_mode */
158#define SNDRV_EMUX_PORT_MODE_MIDI 0 /* normal MIDI port */
159#define SNDRV_EMUX_PORT_MODE_OSS_SYNTH 1 /* OSS synth port */
160#define SNDRV_EMUX_PORT_MODE_OSS_MIDI 2 /* OSS multi channel synth port */
161
162/*
163 * A structure to keep track of each hardware voice
164 */
165struct snd_emux_voice {
166 int ch; /* Hardware channel number */
167
168 int state; /* status */
169#define SNDRV_EMUX_ST_OFF 0x00 /* Not playing, and inactive */
170#define SNDRV_EMUX_ST_ON 0x01 /* Note on */
171#define SNDRV_EMUX_ST_RELEASED (0x02|SNDRV_EMUX_ST_ON) /* Note released */
172#define SNDRV_EMUX_ST_SUSTAINED (0x04|SNDRV_EMUX_ST_ON) /* Note sustained */
173#define SNDRV_EMUX_ST_STANDBY (0x08|SNDRV_EMUX_ST_ON) /* Waiting to be triggered */
174#define SNDRV_EMUX_ST_PENDING (0x10|SNDRV_EMUX_ST_ON) /* Note will be released */
175#define SNDRV_EMUX_ST_LOCKED 0x100 /* Not accessible */
176
177 unsigned int time; /* An allocation time */
178 unsigned char note; /* Note currently assigned to this voice */
179 unsigned char key;
180 unsigned char velocity; /* Velocity of current note */
181
182 snd_sf_zone_t *zone; /* Zone assigned to this note */
183 void *block; /* sample block pointer (optional) */
184 snd_midi_channel_t *chan; /* Midi channel for this note */
185 snd_emux_port_t *port; /* associated port */
186 snd_emux_t *emu; /* assigned root info */
187 void *hw; /* hardware pointer (emu8000_t or emu10k1_t) */
188 unsigned long ontime; /* jiffies at note triggered */
189
190 /* Emu8k/Emu10k1 registers */
191 soundfont_voice_info_t reg;
192
193 /* additional registers */
194 int avol; /* volume attenuation */
195 int acutoff; /* cutoff target */
196 int apitch; /* pitch offset */
197 int apan; /* pan/aux pair */
198 int aaux;
199 int ptarget; /* pitch target */
200 int vtarget; /* volume target */
201 int ftarget; /* filter target */
202
203};
204
205/*
206 * update flags (can be combined)
207 */
208#define SNDRV_EMUX_UPDATE_VOLUME (1<<0)
209#define SNDRV_EMUX_UPDATE_PITCH (1<<1)
210#define SNDRV_EMUX_UPDATE_PAN (1<<2)
211#define SNDRV_EMUX_UPDATE_FMMOD (1<<3)
212#define SNDRV_EMUX_UPDATE_TREMFREQ (1<<4)
213#define SNDRV_EMUX_UPDATE_FM2FRQ2 (1<<5)
214#define SNDRV_EMUX_UPDATE_Q (1<<6)
215
216
217#ifdef SNDRV_EMUX_USE_RAW_EFFECT
218/*
219 * effect table
220 */
221struct snd_emux_effect_table {
222 /* Emu8000 specific effects */
223 short val[EMUX_NUM_EFFECTS];
224 unsigned char flag[EMUX_NUM_EFFECTS];
225};
226#endif /* SNDRV_EMUX_USE_RAW_EFFECT */
227
228
229/*
230 * prototypes - interface to Emu10k1 and Emu8k routines
231 */
232int snd_emux_new(snd_emux_t **remu);
233int snd_emux_register(snd_emux_t *emu, snd_card_t *card, int index, char *name);
234int snd_emux_free(snd_emux_t *emu);
235
236/*
237 * exported functions
238 */
239void snd_emux_terminate_all(snd_emux_t *emu);
240void snd_emux_lock_voice(snd_emux_t *emu, int voice);
241void snd_emux_unlock_voice(snd_emux_t *emu, int voice);
242
243#endif /* __SOUND_EMUX_SYNTH_H */
diff --git a/include/sound/es1688.h b/include/sound/es1688.h
new file mode 100644
index 000000000000..604f495bc8b1
--- /dev/null
+++ b/include/sound/es1688.h
@@ -0,0 +1,123 @@
1#ifndef __SOUND_ES1688_H
2#define __SOUND_ES1688_H
3
4/*
5 * Header file for ES488/ES1688
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "control.h"
26#include "pcm.h"
27#include <linux/interrupt.h>
28
29#define ES1688_HW_AUTO 0x0000
30#define ES1688_HW_688 0x0001
31#define ES1688_HW_1688 0x0002
32
33struct _snd_es1688 {
34 unsigned long port; /* port of ESS chip */
35 struct resource *res_port;
36 unsigned long mpu_port; /* MPU-401 port of ESS chip */
37 int irq; /* IRQ number of ESS chip */
38 int mpu_irq; /* MPU IRQ */
39 int dma8; /* 8-bit DMA */
40 unsigned short version; /* version of ESS chip */
41 unsigned short hardware; /* see to ES1688_HW_XXXX */
42
43 unsigned short trigger_value;
44 unsigned char pad;
45 unsigned int dma_size;
46
47 snd_card_t *card;
48 snd_pcm_t *pcm;
49 snd_pcm_substream_t *playback_substream;
50 snd_pcm_substream_t *capture_substream;
51
52 spinlock_t reg_lock;
53 spinlock_t mixer_lock;
54};
55
56typedef struct _snd_es1688 es1688_t;
57
58/* I/O ports */
59
60#define ES1688P(codec, x) ((codec)->port + e_s_s_ESS1688##x)
61
62#define e_s_s_ESS1688RESET 0x6
63#define e_s_s_ESS1688READ 0xa
64#define e_s_s_ESS1688WRITE 0xc
65#define e_s_s_ESS1688COMMAND 0xc
66#define e_s_s_ESS1688STATUS 0xc
67#define e_s_s_ESS1688DATA_AVAIL 0xe
68#define e_s_s_ESS1688DATA_AVAIL_16 0xf
69#define e_s_s_ESS1688MIXER_ADDR 0x4
70#define e_s_s_ESS1688MIXER_DATA 0x5
71#define e_s_s_ESS1688OPL3_LEFT 0x0
72#define e_s_s_ESS1688OPL3_RIGHT 0x2
73#define e_s_s_ESS1688OPL3_BOTH 0x8
74#define e_s_s_ESS1688ENABLE0 0x0
75#define e_s_s_ESS1688ENABLE1 0x9
76#define e_s_s_ESS1688ENABLE2 0xb
77#define e_s_s_ESS1688INIT1 0x7
78
79#define ES1688_DSP_CMD_DMAOFF 0xd0
80#define ES1688_DSP_CMD_SPKON 0xd1
81#define ES1688_DSP_CMD_SPKOFF 0xd3
82#define ES1688_DSP_CMD_DMAON 0xd4
83
84#define ES1688_PCM_DEV 0x14
85#define ES1688_MIC_DEV 0x1a
86#define ES1688_REC_DEV 0x1c
87#define ES1688_MASTER_DEV 0x32
88#define ES1688_FM_DEV 0x36
89#define ES1688_CD_DEV 0x38
90#define ES1688_AUX_DEV 0x3a
91#define ES1688_SPEAKER_DEV 0x3c
92#define ES1688_LINE_DEV 0x3e
93#define ES1688_RECLEV_DEV 0xb4
94
95#define ES1688_MIXS_MASK 0x17
96#define ES1688_MIXS_MIC 0x00
97#define ES1688_MIXS_MIC_MASTER 0x01
98#define ES1688_MIXS_CD 0x02
99#define ES1688_MIXS_AOUT 0x03
100#define ES1688_MIXS_MIC1 0x04
101#define ES1688_MIXS_REC_MIX 0x05
102#define ES1688_MIXS_LINE 0x06
103#define ES1688_MIXS_MASTER 0x07
104#define ES1688_MIXS_MUTE 0x10
105
106/*
107
108 */
109
110void snd_es1688_mixer_write(es1688_t *chip, unsigned char reg, unsigned char data);
111
112int snd_es1688_create(snd_card_t * card,
113 unsigned long port,
114 unsigned long mpu_port,
115 int irq,
116 int mpu_irq,
117 int dma8,
118 unsigned short hardware,
119 es1688_t ** rchip);
120int snd_es1688_pcm(es1688_t *chip, int device, snd_pcm_t ** rpcm);
121int snd_es1688_mixer(es1688_t *chip);
122
123#endif /* __SOUND_ES1688_H */
diff --git a/include/sound/gus.h b/include/sound/gus.h
new file mode 100644
index 000000000000..8b6287a6fff5
--- /dev/null
+++ b/include/sound/gus.h
@@ -0,0 +1,718 @@
1#ifndef __SOUND_GUS_H
2#define __SOUND_GUS_H
3
4/*
5 * Global structures used for GUS part of ALSA driver
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "pcm.h"
26#include "rawmidi.h"
27#include "timer.h"
28#include "seq_midi_emul.h"
29#include "seq_device.h"
30#include "ainstr_iw.h"
31#include "ainstr_gf1.h"
32#include "ainstr_simple.h"
33#include <asm/io.h>
34
35#define SNDRV_SEQ_DEV_ID_GUS "gus-synth"
36
37/* IO ports */
38
39#define GUSP(gus, x) ((gus)->gf1.port + SNDRV_g_u_s_##x)
40
41#define SNDRV_g_u_s_MIDICTRL (0x320-0x220)
42#define SNDRV_g_u_s_MIDISTAT (0x320-0x220)
43#define SNDRV_g_u_s_MIDIDATA (0x321-0x220)
44
45#define SNDRV_g_u_s_GF1PAGE (0x322-0x220)
46#define SNDRV_g_u_s_GF1REGSEL (0x323-0x220)
47#define SNDRV_g_u_s_GF1DATALOW (0x324-0x220)
48#define SNDRV_g_u_s_GF1DATAHIGH (0x325-0x220)
49#define SNDRV_g_u_s_IRQSTAT (0x226-0x220)
50#define SNDRV_g_u_s_TIMERCNTRL (0x228-0x220)
51#define SNDRV_g_u_s_TIMERDATA (0x229-0x220)
52#define SNDRV_g_u_s_DRAM (0x327-0x220)
53#define SNDRV_g_u_s_MIXCNTRLREG (0x220-0x220)
54#define SNDRV_g_u_s_IRQDMACNTRLREG (0x22b-0x220)
55#define SNDRV_g_u_s_REGCNTRLS (0x22f-0x220)
56#define SNDRV_g_u_s_BOARDVERSION (0x726-0x220)
57#define SNDRV_g_u_s_MIXCNTRLPORT (0x726-0x220)
58#define SNDRV_g_u_s_IVER (0x325-0x220)
59#define SNDRV_g_u_s_MIXDATAPORT (0x326-0x220)
60#define SNDRV_g_u_s_MAXCNTRLPORT (0x326-0x220)
61
62/* GF1 registers */
63
64/* global registers */
65#define SNDRV_GF1_GB_ACTIVE_VOICES 0x0e
66#define SNDRV_GF1_GB_VOICES_IRQ 0x0f
67#define SNDRV_GF1_GB_GLOBAL_MODE 0x19
68#define SNDRV_GF1_GW_LFO_BASE 0x1a
69#define SNDRV_GF1_GB_VOICES_IRQ_READ 0x1f
70#define SNDRV_GF1_GB_DRAM_DMA_CONTROL 0x41
71#define SNDRV_GF1_GW_DRAM_DMA_LOW 0x42
72#define SNDRV_GF1_GW_DRAM_IO_LOW 0x43
73#define SNDRV_GF1_GB_DRAM_IO_HIGH 0x44
74#define SNDRV_GF1_GB_SOUND_BLASTER_CONTROL 0x45
75#define SNDRV_GF1_GB_ADLIB_TIMER_1 0x46
76#define SNDRV_GF1_GB_ADLIB_TIMER_2 0x47
77#define SNDRV_GF1_GB_RECORD_RATE 0x48
78#define SNDRV_GF1_GB_REC_DMA_CONTROL 0x49
79#define SNDRV_GF1_GB_JOYSTICK_DAC_LEVEL 0x4b
80#define SNDRV_GF1_GB_RESET 0x4c
81#define SNDRV_GF1_GB_DRAM_DMA_HIGH 0x50
82#define SNDRV_GF1_GW_DRAM_IO16 0x51
83#define SNDRV_GF1_GW_MEMORY_CONFIG 0x52
84#define SNDRV_GF1_GB_MEMORY_CONTROL 0x53
85#define SNDRV_GF1_GW_FIFO_RECORD_BASE_ADDR 0x54
86#define SNDRV_GF1_GW_FIFO_PLAY_BASE_ADDR 0x55
87#define SNDRV_GF1_GW_FIFO_SIZE 0x56
88#define SNDRV_GF1_GW_INTERLEAVE 0x57
89#define SNDRV_GF1_GB_COMPATIBILITY 0x59
90#define SNDRV_GF1_GB_DECODE_CONTROL 0x5a
91#define SNDRV_GF1_GB_VERSION_NUMBER 0x5b
92#define SNDRV_GF1_GB_MPU401_CONTROL_A 0x5c
93#define SNDRV_GF1_GB_MPU401_CONTROL_B 0x5d
94#define SNDRV_GF1_GB_EMULATION_IRQ 0x60
95/* voice specific registers */
96#define SNDRV_GF1_VB_ADDRESS_CONTROL 0x00
97#define SNDRV_GF1_VW_FREQUENCY 0x01
98#define SNDRV_GF1_VW_START_HIGH 0x02
99#define SNDRV_GF1_VW_START_LOW 0x03
100#define SNDRV_GF1_VA_START SNDRV_GF1_VW_START_HIGH
101#define SNDRV_GF1_VW_END_HIGH 0x04
102#define SNDRV_GF1_VW_END_LOW 0x05
103#define SNDRV_GF1_VA_END SNDRV_GF1_VW_END_HIGH
104#define SNDRV_GF1_VB_VOLUME_RATE 0x06
105#define SNDRV_GF1_VB_VOLUME_START 0x07
106#define SNDRV_GF1_VB_VOLUME_END 0x08
107#define SNDRV_GF1_VW_VOLUME 0x09
108#define SNDRV_GF1_VW_CURRENT_HIGH 0x0a
109#define SNDRV_GF1_VW_CURRENT_LOW 0x0b
110#define SNDRV_GF1_VA_CURRENT SNDRV_GF1_VW_CURRENT_HIGH
111#define SNDRV_GF1_VB_PAN 0x0c
112#define SNDRV_GF1_VW_OFFSET_RIGHT 0x0c
113#define SNDRV_GF1_VB_VOLUME_CONTROL 0x0d
114#define SNDRV_GF1_VB_UPPER_ADDRESS 0x10
115#define SNDRV_GF1_VW_EFFECT_HIGH 0x11
116#define SNDRV_GF1_VW_EFFECT_LOW 0x12
117#define SNDRV_GF1_VA_EFFECT SNDRV_GF1_VW_EFFECT_HIGH
118#define SNDRV_GF1_VW_OFFSET_LEFT 0x13
119#define SNDRV_GF1_VB_ACCUMULATOR 0x14
120#define SNDRV_GF1_VB_MODE 0x15
121#define SNDRV_GF1_VW_EFFECT_VOLUME 0x16
122#define SNDRV_GF1_VB_FREQUENCY_LFO 0x17
123#define SNDRV_GF1_VB_VOLUME_LFO 0x18
124#define SNDRV_GF1_VW_OFFSET_RIGHT_FINAL 0x1b
125#define SNDRV_GF1_VW_OFFSET_LEFT_FINAL 0x1c
126#define SNDRV_GF1_VW_EFFECT_VOLUME_FINAL 0x1d
127
128/* ICS registers */
129
130#define SNDRV_ICS_MIC_DEV 0
131#define SNDRV_ICS_LINE_DEV 1
132#define SNDRV_ICS_CD_DEV 2
133#define SNDRV_ICS_GF1_DEV 3
134#define SNDRV_ICS_NONE_DEV 4
135#define SNDRV_ICS_MASTER_DEV 5
136
137/* LFO */
138
139#define SNDRV_LFO_TREMOLO 0
140#define SNDRV_LFO_VIBRATO 1
141
142/* misc */
143
144#define SNDRV_GF1_DMA_UNSIGNED 0x80
145#define SNDRV_GF1_DMA_16BIT 0x40
146#define SNDRV_GF1_DMA_IRQ 0x20
147#define SNDRV_GF1_DMA_WIDTH16 0x04
148#define SNDRV_GF1_DMA_READ 0x02 /* read from GUS's DRAM */
149#define SNDRV_GF1_DMA_ENABLE 0x01
150
151/* ramp ranges */
152
153#define SNDRV_GF1_ATTEN(x) (snd_gf1_atten_table[x])
154#define SNDRV_GF1_MIN_VOLUME 1800
155#define SNDRV_GF1_MAX_VOLUME 4095
156#define SNDRV_GF1_MIN_OFFSET (SNDRV_GF1_MIN_VOLUME>>4)
157#define SNDRV_GF1_MAX_OFFSET 255
158#define SNDRV_GF1_MAX_TDEPTH 90
159
160/* defines for memory manager */
161
162#define SNDRV_GF1_MEM_BLOCK_16BIT 0x0001
163
164#define SNDRV_GF1_MEM_OWNER_DRIVER 0x0001
165#define SNDRV_GF1_MEM_OWNER_WAVE_SIMPLE 0x0002
166#define SNDRV_GF1_MEM_OWNER_WAVE_GF1 0x0003
167#define SNDRV_GF1_MEM_OWNER_WAVE_IWFFFF 0x0004
168
169/* constants for interrupt handlers */
170
171#define SNDRV_GF1_HANDLER_MIDI_OUT 0x00010000
172#define SNDRV_GF1_HANDLER_MIDI_IN 0x00020000
173#define SNDRV_GF1_HANDLER_TIMER1 0x00040000
174#define SNDRV_GF1_HANDLER_TIMER2 0x00080000
175#define SNDRV_GF1_HANDLER_VOICE 0x00100000
176#define SNDRV_GF1_HANDLER_DMA_WRITE 0x00200000
177#define SNDRV_GF1_HANDLER_DMA_READ 0x00400000
178#define SNDRV_GF1_HANDLER_ALL (0xffff0000&~SNDRV_GF1_HANDLER_VOICE)
179
180/* constants for DMA flags */
181
182#define SNDRV_GF1_DMA_TRIGGER 1
183
184/* --- */
185
186struct _snd_gus_card;
187typedef struct _snd_gus_card snd_gus_card_t;
188
189/* GF1 specific structure */
190
191typedef struct _snd_gf1_bank_info {
192 unsigned int address;
193 unsigned int size;
194} snd_gf1_bank_info_t;
195
196typedef struct _snd_gf1_mem_block {
197 unsigned short flags; /* flags - SNDRV_GF1_MEM_BLOCK_XXXX */
198 unsigned short owner; /* owner - SNDRV_GF1_MEM_OWNER_XXXX */
199 unsigned int share; /* share count */
200 unsigned int share_id[4]; /* share ID */
201 unsigned int ptr;
202 unsigned int size;
203 char *name;
204 struct _snd_gf1_mem_block *next;
205 struct _snd_gf1_mem_block *prev;
206} snd_gf1_mem_block_t;
207
208typedef struct _snd_gf1_mem {
209 snd_gf1_bank_info_t banks_8[4];
210 snd_gf1_bank_info_t banks_16[4];
211 snd_gf1_mem_block_t *first;
212 snd_gf1_mem_block_t *last;
213 struct semaphore memory_mutex;
214} snd_gf1_mem_t;
215
216typedef struct snd_gf1_dma_block {
217 void *buffer; /* buffer in computer's RAM */
218 unsigned long buf_addr; /* buffer address */
219 unsigned int addr; /* address in onboard memory */
220 unsigned int count; /* count in bytes */
221 unsigned int cmd; /* DMA command (format) */
222 void (*ack)(snd_gus_card_t * gus, void *private_data);
223 void *private_data;
224 struct snd_gf1_dma_block *next;
225} snd_gf1_dma_block_t;
226
227typedef struct {
228 snd_midi_channel_set_t * chset;
229 snd_gus_card_t * gus;
230 int mode; /* operation mode */
231 int client; /* sequencer client number */
232 int port; /* sequencer port number */
233 unsigned int midi_has_voices: 1;
234} snd_gus_port_t;
235
236typedef struct _snd_gus_voice snd_gus_voice_t;
237
238typedef struct {
239 void (*sample_start)(snd_gus_card_t *gus, snd_gus_voice_t *voice, snd_seq_position_t position);
240 void (*sample_stop)(snd_gus_card_t *gus, snd_gus_voice_t *voice, snd_seq_stop_mode_t mode);
241 void (*sample_freq)(snd_gus_card_t *gus, snd_gus_voice_t *voice, snd_seq_frequency_t freq);
242 void (*sample_volume)(snd_gus_card_t *gus, snd_gus_voice_t *voice, snd_seq_ev_volume_t *volume);
243 void (*sample_loop)(snd_gus_card_t *card, snd_gus_voice_t *voice, snd_seq_ev_loop_t *loop);
244 void (*sample_pos)(snd_gus_card_t *card, snd_gus_voice_t *voice, snd_seq_position_t position);
245 void (*sample_private1)(snd_gus_card_t *card, snd_gus_voice_t *voice, unsigned char *data);
246} snd_gus_sample_ops_t;
247
248#define SNDRV_GF1_VOICE_TYPE_PCM 0
249#define SNDRV_GF1_VOICE_TYPE_SYNTH 1
250#define SNDRV_GF1_VOICE_TYPE_MIDI 2
251
252#define SNDRV_GF1_VFLG_RUNNING (1<<0)
253#define SNDRV_GF1_VFLG_EFFECT_TIMER1 (1<<1)
254#define SNDRV_GF1_VFLG_PAN (1<<2)
255
256typedef enum {
257 VENV_BEFORE,
258 VENV_ATTACK,
259 VENV_SUSTAIN,
260 VENV_RELEASE,
261 VENV_DONE,
262 VENV_VOLUME
263} snd_gus_volume_state_t;
264
265struct _snd_gus_voice {
266 int number;
267 unsigned int use: 1,
268 pcm: 1,
269 synth:1,
270 midi: 1;
271 unsigned int flags;
272 unsigned char client;
273 unsigned char port;
274 unsigned char index;
275 unsigned char pad;
276
277#ifdef CONFIG_SND_DEBUG
278 unsigned int interrupt_stat_wave;
279 unsigned int interrupt_stat_volume;
280#endif
281 void (*handler_wave) (snd_gus_card_t * gus, snd_gus_voice_t * voice);
282 void (*handler_volume) (snd_gus_card_t * gus, snd_gus_voice_t * voice);
283 void (*handler_effect) (snd_gus_card_t * gus, snd_gus_voice_t * voice);
284 void (*volume_change) (snd_gus_card_t * gus);
285
286 snd_gus_sample_ops_t *sample_ops;
287
288 snd_seq_instr_t instr;
289
290 /* running status / registers */
291
292 snd_seq_ev_volume_t sample_volume;
293
294 unsigned short fc_register;
295 unsigned short fc_lfo;
296 unsigned short gf1_volume;
297 unsigned char control;
298 unsigned char mode;
299 unsigned char gf1_pan;
300 unsigned char effect_accumulator;
301 unsigned char volume_control;
302 unsigned char venv_value_next;
303 snd_gus_volume_state_t venv_state;
304 snd_gus_volume_state_t venv_state_prev;
305 unsigned short vlo;
306 unsigned short vro;
307 unsigned short gf1_effect_volume;
308
309 /* --- */
310
311 void *private_data;
312 void (*private_free)(snd_gus_voice_t *voice);
313};
314
315struct _snd_gf1 {
316
317 unsigned int enh_mode:1, /* enhanced mode (GFA1) */
318 hw_lfo:1, /* use hardware LFO */
319 sw_lfo:1, /* use software LFO */
320 effect:1; /* use effect voices */
321
322 unsigned long port; /* port of GF1 chip */
323 struct resource *res_port1;
324 struct resource *res_port2;
325 int irq; /* IRQ number */
326 int dma1; /* DMA1 number */
327 int dma2; /* DMA2 number */
328 unsigned int memory; /* GUS's DRAM size in bytes */
329 unsigned int rom_memory; /* GUS's ROM size in bytes */
330 unsigned int rom_present; /* bitmask */
331 unsigned int rom_banks; /* GUS's ROM banks */
332
333 snd_gf1_mem_t mem_alloc;
334
335 /* registers */
336 unsigned short reg_page;
337 unsigned short reg_regsel;
338 unsigned short reg_data8;
339 unsigned short reg_data16;
340 unsigned short reg_irqstat;
341 unsigned short reg_dram;
342 unsigned short reg_timerctrl;
343 unsigned short reg_timerdata;
344 unsigned char ics_regs[6][2];
345 /* --------- */
346
347 unsigned char active_voices; /* active voices */
348 unsigned char active_voice; /* selected voice (GF1PAGE register) */
349
350 snd_gus_voice_t voices[32]; /* GF1 voices */
351
352 unsigned int default_voice_address;
353
354 unsigned short playback_freq; /* GF1 playback (mixing) frequency */
355 unsigned short mode; /* see to SNDRV_GF1_MODE_XXXX */
356 unsigned char volume_ramp;
357 unsigned char smooth_pan;
358 unsigned char full_range_pan;
359 unsigned char pad0;
360
361 unsigned char *lfos;
362
363 /* interrupt handlers */
364
365 void (*interrupt_handler_midi_out) (snd_gus_card_t * gus);
366 void (*interrupt_handler_midi_in) (snd_gus_card_t * gus);
367 void (*interrupt_handler_timer1) (snd_gus_card_t * gus);
368 void (*interrupt_handler_timer2) (snd_gus_card_t * gus);
369 void (*interrupt_handler_dma_write) (snd_gus_card_t * gus);
370 void (*interrupt_handler_dma_read) (snd_gus_card_t * gus);
371
372#ifdef CONFIG_SND_DEBUG
373 unsigned int interrupt_stat_midi_out;
374 unsigned int interrupt_stat_midi_in;
375 unsigned int interrupt_stat_timer1;
376 unsigned int interrupt_stat_timer2;
377 unsigned int interrupt_stat_dma_write;
378 unsigned int interrupt_stat_dma_read;
379 unsigned int interrupt_stat_voice_lost;
380#endif
381
382 /* synthesizer */
383
384 int seq_client;
385 snd_gus_port_t seq_ports[4];
386 snd_seq_kinstr_list_t *ilist;
387 snd_iwffff_ops_t iwffff_ops;
388 snd_gf1_ops_t gf1_ops;
389 snd_simple_ops_t simple_ops;
390
391 /* timer */
392
393 unsigned short timer_enabled;
394 snd_timer_t *timer1;
395 snd_timer_t *timer2;
396
397 /* midi */
398
399 unsigned short uart_cmd;
400 unsigned int uart_framing;
401 unsigned int uart_overrun;
402
403 /* dma operations */
404
405 unsigned int dma_flags;
406 unsigned int dma_shared;
407 snd_gf1_dma_block_t *dma_data_pcm;
408 snd_gf1_dma_block_t *dma_data_pcm_last;
409 snd_gf1_dma_block_t *dma_data_synth;
410 snd_gf1_dma_block_t *dma_data_synth_last;
411 void (*dma_ack)(snd_gus_card_t * gus, void *private_data);
412 void *dma_private_data;
413
414 /* pcm */
415 int pcm_channels;
416 int pcm_alloc_voices;
417 unsigned short pcm_volume_level_left;
418 unsigned short pcm_volume_level_right;
419 unsigned short pcm_volume_level_left1;
420 unsigned short pcm_volume_level_right1;
421
422 unsigned char pcm_rcntrl_reg;
423 unsigned char pad_end;
424};
425
426/* main structure for GUS card */
427
428struct _snd_gus_card {
429 snd_card_t *card;
430
431 unsigned int
432 initialized: 1, /* resources were initialized */
433 equal_irq:1, /* GF1 and CODEC shares IRQ (GUS MAX only) */
434 equal_dma:1, /* if dma channels are equal (not valid for daughter board) */
435 ics_flag:1, /* have we ICS mixer chip */
436 ics_flipped:1, /* ICS mixer have flipped some channels? */
437 codec_flag:1, /* have we CODEC chip? */
438 max_flag:1, /* have we GUS MAX card? */
439 max_ctrl_flag:1, /* have we original GUS MAX card? */
440 daughter_flag:1, /* have we daughter board? */
441 interwave:1, /* hey - we have InterWave card */
442 ess_flag:1, /* ESS chip found... GUS Extreme */
443 ace_flag:1, /* GUS ACE detected */
444 uart_enable:1; /* enable MIDI UART */
445 unsigned short revision; /* revision of chip */
446 unsigned short max_cntrl_val; /* GUS MAX control value */
447 unsigned short mix_cntrl_reg; /* mixer control register */
448 unsigned short joystick_dac; /* joystick DAC level */
449 int timer_dev; /* timer device */
450
451 struct _snd_gf1 gf1; /* gf1 specific variables */
452 snd_pcm_t *pcm;
453 snd_pcm_substream_t *pcm_cap_substream;
454 unsigned int c_dma_size;
455 unsigned int c_period_size;
456 unsigned int c_pos;
457
458 snd_rawmidi_t *midi_uart;
459 snd_rawmidi_substream_t *midi_substream_output;
460 snd_rawmidi_substream_t *midi_substream_input;
461
462 snd_seq_device_t *seq_dev;
463
464 spinlock_t reg_lock;
465 spinlock_t voice_alloc;
466 spinlock_t active_voice_lock;
467 spinlock_t event_lock;
468 spinlock_t dma_lock;
469 spinlock_t pcm_volume_level_lock;
470 spinlock_t uart_cmd_lock;
471 struct semaphore dma_mutex;
472 struct semaphore register_mutex;
473};
474
475/* I/O functions for GF1/InterWave chip - gus_io.c */
476
477static inline void snd_gf1_select_voice(snd_gus_card_t * gus, int voice)
478{
479 unsigned long flags;
480
481 spin_lock_irqsave(&gus->active_voice_lock, flags);
482 if (voice != gus->gf1.active_voice) {
483 gus->gf1.active_voice = voice;
484 outb(voice, GUSP(gus, GF1PAGE));
485 }
486 spin_unlock_irqrestore(&gus->active_voice_lock, flags);
487}
488
489static inline void snd_gf1_uart_cmd(snd_gus_card_t * gus, unsigned char b)
490{
491 outb(gus->gf1.uart_cmd = b, GUSP(gus, MIDICTRL));
492}
493
494static inline unsigned char snd_gf1_uart_stat(snd_gus_card_t * gus)
495{
496 return inb(GUSP(gus, MIDISTAT));
497}
498
499static inline void snd_gf1_uart_put(snd_gus_card_t * gus, unsigned char b)
500{
501 outb(b, GUSP(gus, MIDIDATA));
502}
503
504static inline unsigned char snd_gf1_uart_get(snd_gus_card_t * gus)
505{
506 return inb(GUSP(gus, MIDIDATA));
507}
508
509extern void snd_gf1_delay(snd_gus_card_t * gus);
510
511extern void snd_gf1_ctrl_stop(snd_gus_card_t * gus, unsigned char reg);
512
513extern void snd_gf1_write8(snd_gus_card_t * gus, unsigned char reg, unsigned char data);
514extern unsigned char snd_gf1_look8(snd_gus_card_t * gus, unsigned char reg);
515extern inline unsigned char snd_gf1_read8(snd_gus_card_t * gus, unsigned char reg)
516{
517 return snd_gf1_look8(gus, reg | 0x80);
518}
519extern void snd_gf1_write16(snd_gus_card_t * gus, unsigned char reg, unsigned int data);
520extern unsigned short snd_gf1_look16(snd_gus_card_t * gus, unsigned char reg);
521extern inline unsigned short snd_gf1_read16(snd_gus_card_t * gus, unsigned char reg)
522{
523 return snd_gf1_look16(gus, reg | 0x80);
524}
525extern void snd_gf1_adlib_write(snd_gus_card_t * gus, unsigned char reg, unsigned char data);
526extern void snd_gf1_dram_addr(snd_gus_card_t * gus, unsigned int addr);
527extern void snd_gf1_poke(snd_gus_card_t * gus, unsigned int addr, unsigned char data);
528extern unsigned char snd_gf1_peek(snd_gus_card_t * gus, unsigned int addr);
529extern void snd_gf1_pokew(snd_gus_card_t * gus, unsigned int addr, unsigned short data);
530extern unsigned short snd_gf1_peekw(snd_gus_card_t * gus, unsigned int addr);
531extern void snd_gf1_dram_setmem(snd_gus_card_t * gus, unsigned int addr, unsigned short value, unsigned int count);
532extern void snd_gf1_write_addr(snd_gus_card_t * gus, unsigned char reg, unsigned int addr, short w_16bit);
533extern unsigned int snd_gf1_read_addr(snd_gus_card_t * gus, unsigned char reg, short w_16bit);
534extern void snd_gf1_i_ctrl_stop(snd_gus_card_t * gus, unsigned char reg);
535extern void snd_gf1_i_write8(snd_gus_card_t * gus, unsigned char reg, unsigned char data);
536extern unsigned char snd_gf1_i_look8(snd_gus_card_t * gus, unsigned char reg);
537extern void snd_gf1_i_write16(snd_gus_card_t * gus, unsigned char reg, unsigned int data);
538extern inline unsigned char snd_gf1_i_read8(snd_gus_card_t * gus, unsigned char reg)
539{
540 return snd_gf1_i_look8(gus, reg | 0x80);
541}
542extern unsigned short snd_gf1_i_look16(snd_gus_card_t * gus, unsigned char reg);
543extern inline unsigned short snd_gf1_i_read16(snd_gus_card_t * gus, unsigned char reg)
544{
545 return snd_gf1_i_look16(gus, reg | 0x80);
546}
547extern void snd_gf1_i_adlib_write(snd_gus_card_t * gus, unsigned char reg, unsigned char data);
548extern void snd_gf1_i_write_addr(snd_gus_card_t * gus, unsigned char reg, unsigned int addr, short w_16bit);
549extern unsigned int snd_gf1_i_read_addr(snd_gus_card_t * gus, unsigned char reg, short w_16bit);
550
551extern void snd_gf1_select_active_voices(snd_gus_card_t * gus);
552
553/* gus_lfo.c */
554
555struct _SND_IW_LFO_PROGRAM {
556 unsigned short freq_and_control;
557 unsigned char depth_final;
558 unsigned char depth_inc;
559 unsigned short twave;
560 unsigned short depth;
561};
562
563#if 0
564extern irqreturn_t snd_gf1_lfo_effect_interrupt(snd_gus_card_t * gus, snd_gf1_voice_t * voice);
565#endif
566extern void snd_gf1_lfo_init(snd_gus_card_t * gus);
567extern void snd_gf1_lfo_done(snd_gus_card_t * gus);
568extern void snd_gf1_lfo_program(snd_gus_card_t * gus, int voice, int lfo_type, struct _SND_IW_LFO_PROGRAM *program);
569extern void snd_gf1_lfo_enable(snd_gus_card_t * gus, int voice, int lfo_type);
570extern void snd_gf1_lfo_disable(snd_gus_card_t * gus, int voice, int lfo_type);
571extern void snd_gf1_lfo_change_freq(snd_gus_card_t * gus, int voice, int lfo_type, int freq);
572extern void snd_gf1_lfo_change_depth(snd_gus_card_t * gus, int voice, int lfo_type, int depth);
573extern void snd_gf1_lfo_setup(snd_gus_card_t * gus, int voice, int lfo_type, int freq, int current_depth, int depth, int sweep, int shape);
574extern void snd_gf1_lfo_shutdown(snd_gus_card_t * gus, int voice, int lfo_type);
575#if 0
576extern void snd_gf1_lfo_command(snd_gus_card_t * gus, int voice, unsigned char *command);
577#endif
578
579/* gus_mem.c */
580
581void snd_gf1_mem_lock(snd_gf1_mem_t * alloc, int xup);
582int snd_gf1_mem_xfree(snd_gf1_mem_t * alloc, snd_gf1_mem_block_t * block);
583snd_gf1_mem_block_t *snd_gf1_mem_look(snd_gf1_mem_t * alloc,
584 unsigned int address);
585snd_gf1_mem_block_t *snd_gf1_mem_share(snd_gf1_mem_t * alloc,
586 unsigned int *share_id);
587snd_gf1_mem_block_t *snd_gf1_mem_alloc(snd_gf1_mem_t * alloc, int owner,
588 char *name, int size, int w_16,
589 int align, unsigned int *share_id);
590int snd_gf1_mem_free(snd_gf1_mem_t * alloc, unsigned int address);
591int snd_gf1_mem_free_owner(snd_gf1_mem_t * alloc, int owner);
592int snd_gf1_mem_init(snd_gus_card_t * gus);
593int snd_gf1_mem_done(snd_gus_card_t * gus);
594
595/* gus_mem_proc.c */
596
597int snd_gf1_mem_proc_init(snd_gus_card_t * gus);
598
599/* gus_dma.c */
600
601int snd_gf1_dma_init(snd_gus_card_t * gus);
602int snd_gf1_dma_done(snd_gus_card_t * gus);
603int snd_gf1_dma_transfer_block(snd_gus_card_t * gus,
604 snd_gf1_dma_block_t * block,
605 int atomic,
606 int synth);
607
608/* gus_volume.c */
609
610unsigned short snd_gf1_lvol_to_gvol_raw(unsigned int vol);
611unsigned int snd_gf1_gvol_to_lvol_raw(unsigned short gf1_vol);
612unsigned int snd_gf1_calc_ramp_rate(snd_gus_card_t * gus,
613 unsigned short start,
614 unsigned short end,
615 unsigned int us);
616unsigned short snd_gf1_translate_freq(snd_gus_card_t * gus, unsigned int freq2);
617unsigned short snd_gf1_compute_pitchbend(unsigned short pitchbend, unsigned short sens);
618unsigned short snd_gf1_compute_freq(unsigned int freq,
619 unsigned int rate,
620 unsigned short mix_rate);
621
622/* gus_reset.c */
623
624void snd_gf1_set_default_handlers(snd_gus_card_t * gus, unsigned int what);
625void snd_gf1_smart_stop_voice(snd_gus_card_t * gus, unsigned short voice);
626void snd_gf1_stop_voice(snd_gus_card_t * gus, unsigned short voice);
627void snd_gf1_clear_voices(snd_gus_card_t * gus, unsigned short v_min, unsigned short v_max);
628void snd_gf1_stop_voices(snd_gus_card_t * gus, unsigned short v_min, unsigned short v_max);
629snd_gus_voice_t *snd_gf1_alloc_voice(snd_gus_card_t * gus, int type, int client, int port);
630void snd_gf1_free_voice(snd_gus_card_t * gus, snd_gus_voice_t *voice);
631int snd_gf1_start(snd_gus_card_t * gus);
632int snd_gf1_stop(snd_gus_card_t * gus);
633
634/* gus_mixer.c */
635
636int snd_gf1_new_mixer(snd_gus_card_t * gus);
637
638/* gus_pcm.c */
639
640int snd_gf1_pcm_new(snd_gus_card_t * gus, int pcm_dev, int control_index, snd_pcm_t ** rpcm);
641
642#ifdef CONFIG_SND_DEBUG
643extern void snd_gf1_print_voice_registers(snd_gus_card_t * gus);
644extern void snd_gf1_print_global_registers(snd_gus_card_t * gus);
645extern void snd_gf1_print_setup_registers(snd_gus_card_t * gus);
646extern void snd_gf1_peek_print_block(snd_gus_card_t * gus, unsigned int addr, int count, int w_16bit);
647#endif
648
649/* gus.c */
650
651int snd_gus_use_inc(snd_gus_card_t * gus);
652void snd_gus_use_dec(snd_gus_card_t * gus);
653int snd_gus_create(snd_card_t * card,
654 unsigned long port,
655 int irq, int dma1, int dma2,
656 int timer_dev,
657 int voices,
658 int pcm_channels,
659 int effect,
660 snd_gus_card_t ** rgus);
661int snd_gus_initialize(snd_gus_card_t * gus);
662
663/* gus_irq.c */
664
665irqreturn_t snd_gus_interrupt(int irq, void *dev_id, struct pt_regs *regs);
666#ifdef CONFIG_SND_DEBUG
667void snd_gus_irq_profile_init(snd_gus_card_t *gus);
668#endif
669
670/* gus_uart.c */
671
672int snd_gf1_rawmidi_new(snd_gus_card_t * gus, int device, snd_rawmidi_t **rrawmidi);
673
674#if 0
675extern void snd_engine_instrument_register(unsigned short mode,
676 struct _SND_INSTRUMENT_VOICE_COMMANDS *voice_cmds,
677 struct _SND_INSTRUMENT_NOTE_COMMANDS *note_cmds,
678 struct _SND_INSTRUMENT_CHANNEL_COMMANDS *channel_cmds);
679extern int snd_engine_instrument_register_ask(unsigned short mode);
680#endif
681
682/* gus_dram.c */
683int snd_gus_dram_write(snd_gus_card_t *gus, char __user *ptr,
684 unsigned int addr, unsigned int size);
685int snd_gus_dram_read(snd_gus_card_t *gus, char __user *ptr,
686 unsigned int addr, unsigned int size, int rom);
687
688#if defined(CONFIG_SND_SEQUENCER) || defined(CONFIG_SND_SEQUENCER_MODULE)
689
690/* gus_sample.c */
691void snd_gus_sample_event(snd_seq_event_t *ev, snd_gus_port_t *p);
692
693/* gus_simple.c */
694void snd_gf1_simple_init(snd_gus_voice_t *voice);
695
696/* gus_instr.c */
697int snd_gus_iwffff_put_sample(void *private_data, iwffff_wave_t *wave,
698 char __user *data, long len, int atomic);
699int snd_gus_iwffff_get_sample(void *private_data, iwffff_wave_t *wave,
700 char __user *data, long len, int atomic);
701int snd_gus_iwffff_remove_sample(void *private_data, iwffff_wave_t *wave,
702 int atomic);
703int snd_gus_gf1_put_sample(void *private_data, gf1_wave_t *wave,
704 char __user *data, long len, int atomic);
705int snd_gus_gf1_get_sample(void *private_data, gf1_wave_t *wave,
706 char __user *data, long len, int atomic);
707int snd_gus_gf1_remove_sample(void *private_data, gf1_wave_t *wave,
708 int atomic);
709int snd_gus_simple_put_sample(void *private_data, simple_instrument_t *instr,
710 char __user *data, long len, int atomic);
711int snd_gus_simple_get_sample(void *private_data, simple_instrument_t *instr,
712 char __user *data, long len, int atomic);
713int snd_gus_simple_remove_sample(void *private_data, simple_instrument_t *instr,
714 int atomic);
715
716#endif /* CONFIG_SND_SEQUENCER */
717
718#endif /* __SOUND_GUS_H */
diff --git a/include/sound/hdsp.h b/include/sound/hdsp.h
new file mode 100644
index 000000000000..7ce3aa67e5d6
--- /dev/null
+++ b/include/sound/hdsp.h
@@ -0,0 +1,110 @@
1#ifndef __SOUND_HDSP_H
2#define __SOUND_HDSP_H
3
4/*
5 * Copyright (C) 2003 Thomas Charbonnel (thomas@undata.org)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#define HDSP_MATRIX_MIXER_SIZE 2048
23
24typedef enum {
25 Digiface,
26 Multiface,
27 H9652,
28 H9632,
29 Undefined,
30} HDSP_IO_Type;
31
32typedef struct _snd_hdsp_peak_rms hdsp_peak_rms_t;
33
34struct _snd_hdsp_peak_rms {
35 u32 input_peaks[26];
36 u32 playback_peaks[26];
37 u32 output_peaks[28];
38 u64 input_rms[26];
39 u64 playback_rms[26];
40 /* These are only used for H96xx cards */
41 u64 output_rms[26];
42};
43
44#define SNDRV_HDSP_IOCTL_GET_PEAK_RMS _IOR('H', 0x40, hdsp_peak_rms_t)
45
46typedef struct _snd_hdsp_config_info hdsp_config_info_t;
47
48struct _snd_hdsp_config_info {
49 unsigned char pref_sync_ref;
50 unsigned char wordclock_sync_check;
51 unsigned char spdif_sync_check;
52 unsigned char adatsync_sync_check;
53 unsigned char adat_sync_check[3];
54 unsigned char spdif_in;
55 unsigned char spdif_out;
56 unsigned char spdif_professional;
57 unsigned char spdif_emphasis;
58 unsigned char spdif_nonaudio;
59 unsigned int spdif_sample_rate;
60 unsigned int system_sample_rate;
61 unsigned int autosync_sample_rate;
62 unsigned char system_clock_mode;
63 unsigned char clock_source;
64 unsigned char autosync_ref;
65 unsigned char line_out;
66 unsigned char passthru;
67 unsigned char da_gain;
68 unsigned char ad_gain;
69 unsigned char phone_gain;
70 unsigned char xlr_breakout_cable;
71 unsigned char analog_extension_board;
72};
73
74#define SNDRV_HDSP_IOCTL_GET_CONFIG_INFO _IOR('H', 0x41, hdsp_config_info_t)
75
76typedef struct _snd_hdsp_firmware hdsp_firmware_t;
77
78struct _snd_hdsp_firmware {
79 void __user *firmware_data; /* 24413 x 4 bytes */
80};
81
82#define SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE _IOW('H', 0x42, hdsp_firmware_t)
83
84typedef struct _snd_hdsp_version hdsp_version_t;
85
86struct _snd_hdsp_version {
87 HDSP_IO_Type io_type;
88 unsigned short firmware_rev;
89};
90
91#define SNDRV_HDSP_IOCTL_GET_VERSION _IOR('H', 0x43, hdsp_version_t)
92
93typedef struct _snd_hdsp_mixer hdsp_mixer_t;
94
95struct _snd_hdsp_mixer {
96 unsigned short matrix[HDSP_MATRIX_MIXER_SIZE];
97};
98
99#define SNDRV_HDSP_IOCTL_GET_MIXER _IOR('H', 0x44, hdsp_mixer_t)
100
101typedef struct _snd_hdsp_9632_aeb hdsp_9632_aeb_t;
102
103struct _snd_hdsp_9632_aeb {
104 int aebi;
105 int aebo;
106};
107
108#define SNDRV_HDSP_IOCTL_GET_9632_AEB _IOR('H', 0x45, hdsp_9632_aeb_t)
109
110#endif /* __SOUND_HDSP_H */
diff --git a/include/sound/hwdep.h b/include/sound/hwdep.h
new file mode 100644
index 000000000000..043876348fa1
--- /dev/null
+++ b/include/sound/hwdep.h
@@ -0,0 +1,73 @@
1#ifndef __SOUND_HWDEP_H
2#define __SOUND_HWDEP_H
3
4/*
5 * Hardware dependent layer
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <sound/asound.h>
26#include <linux/poll.h>
27
28typedef enum sndrv_hwdep_iface snd_hwdep_iface_t;
29typedef struct sndrv_hwdep_info snd_hwdep_info_t;
30typedef struct sndrv_hwdep_dsp_status snd_hwdep_dsp_status_t;
31typedef struct sndrv_hwdep_dsp_image snd_hwdep_dsp_image_t;
32
33typedef struct _snd_hwdep_ops {
34 long long (*llseek) (snd_hwdep_t *hw, struct file * file, long long offset, int orig);
35 long (*read) (snd_hwdep_t * hw, char __user *buf, long count, loff_t *offset);
36 long (*write) (snd_hwdep_t * hw, const char __user *buf, long count, loff_t *offset);
37 int (*open) (snd_hwdep_t * hw, struct file * file);
38 int (*release) (snd_hwdep_t * hw, struct file * file);
39 unsigned int (*poll) (snd_hwdep_t * hw, struct file * file, poll_table * wait);
40 int (*ioctl) (snd_hwdep_t * hw, struct file * file, unsigned int cmd, unsigned long arg);
41 int (*ioctl_compat) (snd_hwdep_t * hw, struct file * file, unsigned int cmd, unsigned long arg);
42 int (*mmap) (snd_hwdep_t * hw, struct file * file, struct vm_area_struct * vma);
43 int (*dsp_status) (snd_hwdep_t * hw, snd_hwdep_dsp_status_t * status);
44 int (*dsp_load) (snd_hwdep_t * hw, snd_hwdep_dsp_image_t * image);
45} snd_hwdep_ops_t;
46
47struct _snd_hwdep {
48 snd_card_t *card;
49 int device;
50 char id[32];
51 char name[80];
52 int iface;
53
54#ifdef CONFIG_SND_OSSEMUL
55 char oss_dev[32];
56 int oss_type;
57 int ossreg;
58#endif
59
60 snd_hwdep_ops_t ops;
61 wait_queue_head_t open_wait;
62 void *private_data;
63 void (*private_free) (snd_hwdep_t *hwdep);
64
65 struct semaphore open_mutex;
66 int used;
67 unsigned int dsp_loaded;
68 unsigned int exclusive: 1;
69};
70
71extern int snd_hwdep_new(snd_card_t * card, char *id, int device, snd_hwdep_t ** rhwdep);
72
73#endif /* __SOUND_HWDEP_H */
diff --git a/include/sound/i2c.h b/include/sound/i2c.h
new file mode 100644
index 000000000000..a665ddf9c146
--- /dev/null
+++ b/include/sound/i2c.h
@@ -0,0 +1,102 @@
1#ifndef __SOUND_I2C_H
2#define __SOUND_I2C_H
3
4/*
5 *
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 *
22 */
23
24typedef struct _snd_i2c_device snd_i2c_device_t;
25typedef struct _snd_i2c_bus snd_i2c_bus_t;
26
27#define SND_I2C_DEVICE_ADDRTEN (1<<0) /* 10-bit I2C address */
28
29struct _snd_i2c_device {
30 struct list_head list;
31 snd_i2c_bus_t *bus; /* I2C bus */
32 char name[32]; /* some useful device name */
33 unsigned short flags; /* device flags */
34 unsigned short addr; /* device address (might be 10-bit) */
35 unsigned long private_value;
36 void *private_data;
37 void (*private_free)(snd_i2c_device_t *device);
38};
39
40#define snd_i2c_device(n) list_entry(n, snd_i2c_device_t, list)
41
42typedef struct _snd_i2c_bit_ops {
43 void (*start)(snd_i2c_bus_t *bus); /* transfer start */
44 void (*stop)(snd_i2c_bus_t *bus); /* transfer stop */
45 void (*direction)(snd_i2c_bus_t *bus, int clock, int data); /* set line direction (0 = write, 1 = read) */
46 void (*setlines)(snd_i2c_bus_t *bus, int clock, int data);
47 int (*getclock)(snd_i2c_bus_t *bus);
48 int (*getdata)(snd_i2c_bus_t *bus, int ack);
49} snd_i2c_bit_ops_t;
50
51typedef struct _snd_i2c_ops {
52 int (*sendbytes)(snd_i2c_device_t *device, unsigned char *bytes, int count);
53 int (*readbytes)(snd_i2c_device_t *device, unsigned char *bytes, int count);
54 int (*probeaddr)(snd_i2c_bus_t *bus, unsigned short addr);
55} snd_i2c_ops_t;
56
57struct _snd_i2c_bus {
58 snd_card_t *card; /* card which I2C belongs to */
59 char name[32]; /* some useful label */
60
61 struct semaphore lock_mutex;
62
63 snd_i2c_bus_t *master; /* master bus when SCK/SCL is shared */
64 struct list_head buses; /* master: slave buses sharing SCK/SCL, slave: link list */
65
66 struct list_head devices; /* attached devices to this bus */
67
68 union {
69 snd_i2c_bit_ops_t *bit;
70 void *ops;
71 } hw_ops; /* lowlevel operations */
72 snd_i2c_ops_t *ops; /* midlevel operations */
73
74 unsigned long private_value;
75 void *private_data;
76 void (*private_free)(snd_i2c_bus_t *bus);
77};
78
79#define snd_i2c_slave_bus(n) list_entry(n, snd_i2c_bus_t, buses)
80
81int snd_i2c_bus_create(snd_card_t *card, const char *name, snd_i2c_bus_t *master, snd_i2c_bus_t **ri2c);
82int snd_i2c_device_create(snd_i2c_bus_t *bus, const char *name, unsigned char addr, snd_i2c_device_t **rdevice);
83int snd_i2c_device_free(snd_i2c_device_t *device);
84
85static inline void snd_i2c_lock(snd_i2c_bus_t *bus) {
86 if (bus->master)
87 down(&bus->master->lock_mutex);
88 else
89 down(&bus->lock_mutex);
90}
91static inline void snd_i2c_unlock(snd_i2c_bus_t *bus) {
92 if (bus->master)
93 up(&bus->master->lock_mutex);
94 else
95 up(&bus->lock_mutex);
96}
97
98int snd_i2c_sendbytes(snd_i2c_device_t *device, unsigned char *bytes, int count);
99int snd_i2c_readbytes(snd_i2c_device_t *device, unsigned char *bytes, int count);
100int snd_i2c_probeaddr(snd_i2c_bus_t *bus, unsigned short addr);
101
102#endif /* __SOUND_I2C_H */
diff --git a/include/sound/info.h b/include/sound/info.h
new file mode 100644
index 000000000000..1d76bf3cb05e
--- /dev/null
+++ b/include/sound/info.h
@@ -0,0 +1,193 @@
1#ifndef __SOUND_INFO_H
2#define __SOUND_INFO_H
3
4/*
5 * Header file for info interface
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/poll.h>
26
27/* buffer for information */
28struct snd_info_buffer {
29 char *buffer; /* pointer to begin of buffer */
30 char *curr; /* current position in buffer */
31 unsigned long size; /* current size */
32 unsigned long len; /* total length of buffer */
33 int stop; /* stop flag */
34 int error; /* error code */
35};
36
37typedef struct snd_info_buffer snd_info_buffer_t;
38
39#define SNDRV_INFO_CONTENT_TEXT 0
40#define SNDRV_INFO_CONTENT_DATA 1
41
42struct snd_info_entry;
43
44struct snd_info_entry_text {
45 unsigned long read_size;
46 unsigned long write_size;
47 void (*read) (snd_info_entry_t *entry, snd_info_buffer_t * buffer);
48 void (*write) (snd_info_entry_t *entry, snd_info_buffer_t * buffer);
49};
50
51struct snd_info_entry_ops {
52 int (*open) (snd_info_entry_t *entry,
53 unsigned short mode, void **file_private_data);
54 int (*release) (snd_info_entry_t * entry,
55 unsigned short mode, void *file_private_data);
56 long (*read) (snd_info_entry_t *entry, void *file_private_data,
57 struct file * file, char __user *buf,
58 unsigned long count, unsigned long pos);
59 long (*write) (snd_info_entry_t *entry, void *file_private_data,
60 struct file * file, const char __user *buf,
61 unsigned long count, unsigned long pos);
62 long long (*llseek) (snd_info_entry_t *entry, void *file_private_data,
63 struct file * file, long long offset, int orig);
64 unsigned int (*poll) (snd_info_entry_t *entry, void *file_private_data,
65 struct file * file, poll_table * wait);
66 int (*ioctl) (snd_info_entry_t *entry, void *file_private_data,
67 struct file * file, unsigned int cmd, unsigned long arg);
68 int (*mmap) (snd_info_entry_t *entry, void *file_private_data,
69 struct inode * inode, struct file * file,
70 struct vm_area_struct * vma);
71};
72
73struct snd_info_entry {
74 const char *name;
75 mode_t mode;
76 long size;
77 unsigned short content;
78 unsigned short disconnected: 1;
79 union {
80 struct snd_info_entry_text text;
81 struct snd_info_entry_ops *ops;
82 } c;
83 snd_info_entry_t *parent;
84 snd_card_t *card;
85 struct module *module;
86 void *private_data;
87 void (*private_free)(snd_info_entry_t *entry);
88 struct proc_dir_entry *p;
89 struct semaphore access;
90};
91
92extern int snd_info_check_reserved_words(const char *str);
93
94#if defined(CONFIG_SND_OSSEMUL) && defined(CONFIG_PROC_FS)
95extern int snd_info_minor_register(void);
96extern int snd_info_minor_unregister(void);
97#else
98#define snd_info_minor_register() /* NOP */
99#define snd_info_minor_unregister() /* NOP */
100#endif
101
102
103#ifdef CONFIG_PROC_FS
104
105extern snd_info_entry_t *snd_seq_root;
106#ifdef CONFIG_SND_OSSEMUL
107extern snd_info_entry_t *snd_oss_root;
108#else
109#define snd_oss_root NULL
110#endif
111
112int snd_iprintf(snd_info_buffer_t * buffer, char *fmt,...) __attribute__ ((format (printf, 2, 3)));
113int snd_info_init(void);
114int snd_info_done(void);
115
116int snd_info_get_line(snd_info_buffer_t * buffer, char *line, int len);
117char *snd_info_get_str(char *dest, char *src, int len);
118snd_info_entry_t *snd_info_create_module_entry(struct module * module,
119 const char *name,
120 snd_info_entry_t * parent);
121snd_info_entry_t *snd_info_create_card_entry(snd_card_t * card,
122 const char *name,
123 snd_info_entry_t * parent);
124void snd_info_free_entry(snd_info_entry_t * entry);
125int snd_info_store_text(snd_info_entry_t * entry);
126int snd_info_restore_text(snd_info_entry_t * entry);
127
128int snd_info_card_create(snd_card_t * card);
129int snd_info_card_register(snd_card_t * card);
130int snd_info_card_free(snd_card_t * card);
131int snd_info_register(snd_info_entry_t * entry);
132int snd_info_unregister(snd_info_entry_t * entry);
133
134/* for card drivers */
135int snd_card_proc_new(snd_card_t *card, const char *name, snd_info_entry_t **entryp);
136
137static inline void snd_info_set_text_ops(snd_info_entry_t *entry,
138 void *private_data,
139 long read_size,
140 void (*read)(snd_info_entry_t *, snd_info_buffer_t *))
141{
142 entry->private_data = private_data;
143 entry->c.text.read_size = read_size;
144 entry->c.text.read = read;
145}
146
147
148#else
149
150#define snd_seq_root NULL
151#define snd_oss_root NULL
152
153static inline int snd_iprintf(snd_info_buffer_t * buffer, char *fmt,...) { return 0; }
154static inline int snd_info_init(void) { return 0; }
155static inline int snd_info_done(void) { return 0; }
156
157static inline int snd_info_get_line(snd_info_buffer_t * buffer, char *line, int len) { return 0; }
158static inline char *snd_info_get_str(char *dest, char *src, int len) { return NULL; }
159static inline snd_info_entry_t *snd_info_create_module_entry(struct module * module, const char *name, snd_info_entry_t * parent) { return NULL; }
160static inline snd_info_entry_t *snd_info_create_card_entry(snd_card_t * card, const char *name, snd_info_entry_t * parent) { return NULL; }
161static inline void snd_info_free_entry(snd_info_entry_t * entry) { ; }
162
163static inline int snd_info_card_create(snd_card_t * card) { return 0; }
164static inline int snd_info_card_register(snd_card_t * card) { return 0; }
165static inline int snd_info_card_free(snd_card_t * card) { return 0; }
166static inline int snd_info_register(snd_info_entry_t * entry) { return 0; }
167static inline int snd_info_unregister(snd_info_entry_t * entry) { return 0; }
168
169#define snd_card_proc_new(card,name,entryp) 0 /* always success */
170#define snd_info_set_text_ops(entry,private_data,read_size,read) /*NOP*/
171
172#endif
173
174/*
175 * OSS info part
176 */
177
178#if defined(CONFIG_SND_OSSEMUL) && defined(CONFIG_PROC_FS)
179
180#define SNDRV_OSS_INFO_DEV_AUDIO 0
181#define SNDRV_OSS_INFO_DEV_SYNTH 1
182#define SNDRV_OSS_INFO_DEV_MIDI 2
183#define SNDRV_OSS_INFO_DEV_TIMERS 4
184#define SNDRV_OSS_INFO_DEV_MIXERS 5
185
186#define SNDRV_OSS_INFO_DEV_COUNT 6
187
188extern int snd_oss_info_register(int dev, int num, char *string);
189#define snd_oss_info_unregister(dev, num) snd_oss_info_register(dev, num, NULL)
190
191#endif /* CONFIG_SND_OSSEMUL && CONFIG_PROC_FS */
192
193#endif /* __SOUND_INFO_H */
diff --git a/include/sound/initval.h b/include/sound/initval.h
new file mode 100644
index 000000000000..2bf1508825a4
--- /dev/null
+++ b/include/sound/initval.h
@@ -0,0 +1,103 @@
1#ifndef __SOUND_INITVAL_H
2#define __SOUND_INITVAL_H
3
4/*
5 * Init values for soundcard modules
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#define SNDRV_AUTO_PORT 1
25#define SNDRV_AUTO_IRQ 0xffff
26#define SNDRV_AUTO_DMA 0xffff
27#define SNDRV_AUTO_DMA_SIZE (0x7fffffff)
28
29#define SNDRV_DEFAULT_IDX1 (-1)
30#define SNDRV_DEFAULT_STR1 NULL
31#define SNDRV_DEFAULT_ENABLE1 1
32#define SNDRV_DEFAULT_PORT1 SNDRV_AUTO_PORT
33#define SNDRV_DEFAULT_IRQ1 SNDRV_AUTO_IRQ
34#define SNDRV_DEFAULT_DMA1 SNDRV_AUTO_DMA
35#define SNDRV_DEFAULT_DMA_SIZE1 SNDRV_AUTO_DMA_SIZE
36#define SNDRV_DEFAULT_PTR1 SNDRV_DEFAULT_STR1
37
38#define SNDRV_DEFAULT_IDX { [0 ... (SNDRV_CARDS-1)] = -1 }
39#define SNDRV_DEFAULT_STR { [0 ... (SNDRV_CARDS-1)] = NULL }
40#define SNDRV_DEFAULT_ENABLE { 1, [1 ... (SNDRV_CARDS-1)] = 0 }
41#define SNDRV_DEFAULT_ENABLE_PNP { [0 ... (SNDRV_CARDS-1)] = 1 }
42#ifdef CONFIG_PNP
43#define SNDRV_DEFAULT_ENABLE_ISAPNP SNDRV_DEFAULT_ENABLE_PNP
44#else
45#define SNDRV_DEFAULT_ENABLE_ISAPNP SNDRV_DEFAULT_ENABLE
46#endif
47#define SNDRV_DEFAULT_PORT { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_PORT }
48#define SNDRV_DEFAULT_IRQ { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_IRQ }
49#define SNDRV_DEFAULT_DMA { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_DMA }
50#define SNDRV_DEFAULT_DMA_SIZE { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_DMA_SIZE }
51#define SNDRV_DEFAULT_PTR SNDRV_DEFAULT_STR
52
53#ifdef SNDRV_LEGACY_AUTO_PROBE
54static int snd_legacy_auto_probe(unsigned long *ports, int (*probe)(unsigned long port))
55{
56 int result = 0; /* number of detected cards */
57
58 while ((signed long)*ports != -1) {
59 if (probe(*ports) >= 0)
60 result++;
61 ports++;
62 }
63 return result;
64}
65#endif
66
67#ifdef SNDRV_LEGACY_FIND_FREE_IRQ
68#include <linux/interrupt.h>
69
70static irqreturn_t snd_legacy_empty_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
71{
72 return IRQ_HANDLED;
73}
74
75static int snd_legacy_find_free_irq(int *irq_table)
76{
77 while (*irq_table != -1) {
78 if (!request_irq(*irq_table, snd_legacy_empty_irq_handler,
79 SA_INTERRUPT, "ALSA Test IRQ", (void *) irq_table)) {
80 free_irq(*irq_table, (void *) irq_table);
81 return *irq_table;
82 }
83 irq_table++;
84 }
85 return -1;
86}
87#endif
88
89#ifdef SNDRV_LEGACY_FIND_FREE_DMA
90static int snd_legacy_find_free_dma(int *dma_table)
91{
92 while (*dma_table != -1) {
93 if (!request_dma(*dma_table, "ALSA Test DMA")) {
94 free_dma(*dma_table);
95 return *dma_table;
96 }
97 dma_table++;
98 }
99 return -1;
100}
101#endif
102
103#endif /* __SOUND_INITVAL_H */
diff --git a/include/sound/memalloc.h b/include/sound/memalloc.h
new file mode 100644
index 000000000000..3a2fd2cc9f19
--- /dev/null
+++ b/include/sound/memalloc.h
@@ -0,0 +1,118 @@
1/*
2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
3 * Takashi Iwai <tiwai@suse.de>
4 *
5 * Generic memory allocators
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __SOUND_MEMALLOC_H
25#define __SOUND_MEMALLOC_H
26
27struct device;
28
29/*
30 * buffer device info
31 */
32struct snd_dma_device {
33 int type; /* SNDRV_DMA_TYPE_XXX */
34 struct device *dev; /* generic device */
35};
36
37#ifndef snd_dma_pci_data
38#define snd_dma_pci_data(pci) (&(pci)->dev)
39#define snd_dma_isa_data() NULL
40#define snd_dma_sbus_data(sbus) ((struct device *)(sbus))
41#define snd_dma_continuous_data(x) ((struct device *)(unsigned long)(x))
42#endif
43
44
45/*
46 * buffer types
47 */
48#define SNDRV_DMA_TYPE_UNKNOWN 0 /* not defined */
49#define SNDRV_DMA_TYPE_CONTINUOUS 1 /* continuous no-DMA memory */
50#define SNDRV_DMA_TYPE_DEV 2 /* generic device continuous */
51#define SNDRV_DMA_TYPE_DEV_SG 3 /* generic device SG-buffer */
52#define SNDRV_DMA_TYPE_SBUS 4 /* SBUS continuous */
53
54/*
55 * info for buffer allocation
56 */
57struct snd_dma_buffer {
58 struct snd_dma_device dev; /* device type */
59 unsigned char *area; /* virtual pointer */
60 dma_addr_t addr; /* physical address */
61 size_t bytes; /* buffer size in bytes */
62 void *private_data; /* private for allocator; don't touch */
63};
64
65/*
66 * Scatter-Gather generic device pages
67 */
68struct snd_sg_page {
69 void *buf;
70 dma_addr_t addr;
71};
72
73struct snd_sg_buf {
74 int size; /* allocated byte size */
75 int pages; /* allocated pages */
76 int tblsize; /* allocated table size */
77 struct snd_sg_page *table; /* address table */
78 struct page **page_table; /* page table (for vmap/vunmap) */
79 struct device *dev;
80};
81
82/*
83 * return the pages matching with the given byte size
84 */
85static inline unsigned int snd_sgbuf_aligned_pages(size_t size)
86{
87 return (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
88}
89
90/*
91 * return the physical address at the corresponding offset
92 */
93static inline dma_addr_t snd_sgbuf_get_addr(struct snd_sg_buf *sgbuf, size_t offset)
94{
95 return sgbuf->table[offset >> PAGE_SHIFT].addr + offset % PAGE_SIZE;
96}
97
98
99/* allocate/release a buffer */
100int snd_dma_alloc_pages(int type, struct device *dev, size_t size,
101 struct snd_dma_buffer *dmab);
102int snd_dma_alloc_pages_fallback(int type, struct device *dev, size_t size,
103 struct snd_dma_buffer *dmab);
104void snd_dma_free_pages(struct snd_dma_buffer *dmab);
105
106/* buffer-preservation managements */
107
108#define snd_dma_pci_buf_id(pci) (((unsigned int)(pci)->vendor << 16) | (pci)->device)
109
110size_t snd_dma_get_reserved_buf(struct snd_dma_buffer *dmab, unsigned int id);
111int snd_dma_reserve_buf(struct snd_dma_buffer *dmab, unsigned int id);
112
113/* basic memory allocation functions */
114void *snd_malloc_pages(size_t size, unsigned int gfp_flags);
115void snd_free_pages(void *ptr, size_t size);
116
117#endif /* __SOUND_MEMALLOC_H */
118
diff --git a/include/sound/minors.h b/include/sound/minors.h
new file mode 100644
index 000000000000..b7b0d8309449
--- /dev/null
+++ b/include/sound/minors.h
@@ -0,0 +1,89 @@
1#ifndef __SOUND_MINORS_H
2#define __SOUND_MINORS_H
3
4/*
5 * MINOR numbers
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#define SNDRV_MINOR_DEVICES 32
25#define SNDRV_MINOR_CARD(minor) ((minor) >> 5)
26#define SNDRV_MINOR_DEVICE(minor) ((minor) & 0x001f)
27#define SNDRV_MINOR(card, dev) (((card) << 5) | (dev))
28
29#define SNDRV_MINOR_CONTROL 0 /* 0 - 0 */
30#define SNDRV_MINOR_SEQUENCER 1
31#define SNDRV_MINOR_TIMER (1+32)
32#define SNDRV_MINOR_HWDEP 4 /* 4 - 7 */
33#define SNDRV_MINOR_HWDEPS 4
34#define SNDRV_MINOR_RAWMIDI 8 /* 8 - 15 */
35#define SNDRV_MINOR_RAWMIDIS 8
36#define SNDRV_MINOR_PCM_PLAYBACK 16 /* 16 - 23 */
37#define SNDRV_MINOR_PCM_CAPTURE 24 /* 24 - 31 */
38#define SNDRV_MINOR_PCMS 8
39
40#define SNDRV_DEVICE_TYPE_CONTROL SNDRV_MINOR_CONTROL
41#define SNDRV_DEVICE_TYPE_HWDEP SNDRV_MINOR_HWDEP
42#define SNDRV_DEVICE_TYPE_MIXER SNDRV_MINOR_MIXER
43#define SNDRV_DEVICE_TYPE_RAWMIDI SNDRV_MINOR_RAWMIDI
44#define SNDRV_DEVICE_TYPE_PCM_PLAYBACK SNDRV_MINOR_PCM_PLAYBACK
45#define SNDRV_DEVICE_TYPE_PCM_PLOOP SNDRV_MINOR_PCM_PLOOP
46#define SNDRV_DEVICE_TYPE_PCM_CAPTURE SNDRV_MINOR_PCM_CAPTURE
47#define SNDRV_DEVICE_TYPE_PCM_CLOOP SNDRV_MINOR_PCM_CLOOP
48#define SNDRV_DEVICE_TYPE_SEQUENCER SNDRV_MINOR_SEQUENCER
49#define SNDRV_DEVICE_TYPE_TIMER SNDRV_MINOR_TIMER
50
51#ifdef CONFIG_SND_OSSEMUL
52
53#define SNDRV_MINOR_OSS_DEVICES 16
54#define SNDRV_MINOR_OSS_CARD(minor) ((minor) >> 4)
55#define SNDRV_MINOR_OSS_DEVICE(minor) ((minor) & 0x000f)
56#define SNDRV_MINOR_OSS(card, dev) (((card) << 4) | (dev))
57
58#define SNDRV_MINOR_OSS_MIXER 0 /* /dev/mixer - OSS 3.XX compatible */
59#define SNDRV_MINOR_OSS_SEQUENCER 1 /* /dev/sequencer - OSS 3.XX compatible */
60#define SNDRV_MINOR_OSS_MIDI 2 /* /dev/midi - native midi interface - OSS 3.XX compatible - UART */
61#define SNDRV_MINOR_OSS_PCM 3 /* alias */
62#define SNDRV_MINOR_OSS_PCM_8 3 /* /dev/dsp - 8bit PCM - OSS 3.XX compatible */
63#define SNDRV_MINOR_OSS_AUDIO 4 /* /dev/audio - SunSparc compatible */
64#define SNDRV_MINOR_OSS_PCM_16 5 /* /dev/dsp16 - 16bit PCM - OSS 3.XX compatible */
65#define SNDRV_MINOR_OSS_SNDSTAT 6 /* /dev/sndstat - for compatibility with OSS */
66#define SNDRV_MINOR_OSS_RESERVED7 7 /* reserved for future use */
67#define SNDRV_MINOR_OSS_MUSIC 8 /* /dev/music - OSS 3.XX compatible */
68#define SNDRV_MINOR_OSS_DMMIDI 9 /* /dev/dmmidi0 - this device can have another minor # with OSS */
69#define SNDRV_MINOR_OSS_DMFM 10 /* /dev/dmfm0 - this device can have another minor # with OSS */
70#define SNDRV_MINOR_OSS_MIXER1 11 /* alternate mixer */
71#define SNDRV_MINOR_OSS_PCM1 12 /* alternate PCM (GF-A-1) */
72#define SNDRV_MINOR_OSS_MIDI1 13 /* alternate midi - SYNTH */
73#define SNDRV_MINOR_OSS_DMMIDI1 14 /* alternate dmmidi - SYNTH */
74#define SNDRV_MINOR_OSS_RESERVED15 15 /* reserved for future use */
75
76#define SNDRV_OSS_DEVICE_TYPE_MIXER 0
77#define SNDRV_OSS_DEVICE_TYPE_SEQUENCER 1
78#define SNDRV_OSS_DEVICE_TYPE_PCM 2
79#define SNDRV_OSS_DEVICE_TYPE_MIDI 3
80#define SNDRV_OSS_DEVICE_TYPE_DMFM 4
81#define SNDRV_OSS_DEVICE_TYPE_SNDSTAT 5
82#define SNDRV_OSS_DEVICE_TYPE_MUSIC 6
83
84#define MODULE_ALIAS_SNDRV_MINOR(type) \
85 MODULE_ALIAS("sound-service-?-" __stringify(type))
86
87#endif
88
89#endif /* __SOUND_MINORS_H */
diff --git a/include/sound/mixer_oss.h b/include/sound/mixer_oss.h
new file mode 100644
index 000000000000..ed75b2fb00ab
--- /dev/null
+++ b/include/sound/mixer_oss.h
@@ -0,0 +1,76 @@
1#ifndef __SOUND_MIXER_OSS_H
2#define __SOUND_MIXER_OSS_H
3
4/*
5 * OSS MIXER API
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#if defined(CONFIG_SND_MIXER_OSS) || defined(CONFIG_SND_MIXER_OSS_MODULE)
26
27typedef struct _snd_oss_mixer_slot snd_mixer_oss_slot_t;
28typedef struct _snd_oss_file snd_mixer_oss_file_t;
29
30typedef int (*snd_mixer_oss_get_volume_t)(snd_mixer_oss_file_t *fmixer, snd_mixer_oss_slot_t *chn, int *left, int *right);
31typedef int (*snd_mixer_oss_put_volume_t)(snd_mixer_oss_file_t *fmixer, snd_mixer_oss_slot_t *chn, int left, int right);
32typedef int (*snd_mixer_oss_get_recsrc_t)(snd_mixer_oss_file_t *fmixer, snd_mixer_oss_slot_t *chn, int *active);
33typedef int (*snd_mixer_oss_put_recsrc_t)(snd_mixer_oss_file_t *fmixer, snd_mixer_oss_slot_t *chn, int active);
34typedef int (*snd_mixer_oss_get_recsrce_t)(snd_mixer_oss_file_t *fmixer, unsigned int *active_index);
35typedef int (*snd_mixer_oss_put_recsrce_t)(snd_mixer_oss_file_t *fmixer, unsigned int active_index);
36
37#define SNDRV_OSS_MAX_MIXERS 32
38
39struct _snd_oss_mixer_slot {
40 int number;
41 unsigned int stereo: 1;
42 snd_mixer_oss_get_volume_t get_volume;
43 snd_mixer_oss_put_volume_t put_volume;
44 snd_mixer_oss_get_recsrc_t get_recsrc;
45 snd_mixer_oss_put_recsrc_t put_recsrc;
46 unsigned long private_value;
47 void *private_data;
48 void (*private_free)(snd_mixer_oss_slot_t *slot);
49 int volume[2];
50};
51
52struct _snd_oss_mixer {
53 snd_card_t *card;
54 char id[16];
55 char name[32];
56 snd_mixer_oss_slot_t slots[SNDRV_OSS_MAX_MIXERS]; /* OSS mixer slots */
57 unsigned int mask_recsrc; /* exclusive recsrc mask */
58 snd_mixer_oss_get_recsrce_t get_recsrc;
59 snd_mixer_oss_put_recsrce_t put_recsrc;
60 void *private_data_recsrc;
61 void (*private_free_recsrc)(snd_mixer_oss_t *mixer);
62 struct semaphore reg_mutex;
63 snd_info_entry_t *proc_entry;
64 int oss_dev_alloc;
65 /* --- */
66 int oss_recsrc;
67};
68
69struct _snd_oss_file {
70 snd_card_t *card;
71 snd_mixer_oss_t *mixer;
72};
73
74#endif /* CONFIG_SND_MIXER_OSS */
75
76#endif /* __SOUND_MIXER_OSS_H */
diff --git a/include/sound/mpu401.h b/include/sound/mpu401.h
new file mode 100644
index 000000000000..ae39e38bf996
--- /dev/null
+++ b/include/sound/mpu401.h
@@ -0,0 +1,115 @@
1#ifndef __SOUND_MPU401_H
2#define __SOUND_MPU401_H
3
4/*
5 * Header file for MPU-401 and compatible cards
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "rawmidi.h"
26#include <linux/interrupt.h>
27
28#define MPU401_HW_MPU401 1 /* native MPU401 */
29#define MPU401_HW_SB 2 /* SoundBlaster MPU-401 UART */
30#define MPU401_HW_ES1688 3 /* AudioDrive ES1688 MPU-401 UART */
31#define MPU401_HW_OPL3SA2 4 /* Yamaha OPL3-SA2 */
32#define MPU401_HW_SONICVIBES 5 /* S3 SonicVibes */
33#define MPU401_HW_CS4232 6 /* CS4232 */
34#define MPU401_HW_ES18XX 7 /* AudioDrive ES18XX MPU-401 UART */
35#define MPU401_HW_FM801 8 /* ForteMedia FM801 */
36#define MPU401_HW_TRID4DWAVE 9 /* Trident 4DWave */
37#define MPU401_HW_AZT2320 10 /* Aztech AZT2320 */
38#define MPU401_HW_ALS100 11 /* Avance Logic ALS100 */
39#define MPU401_HW_ICE1712 12 /* Envy24 */
40#define MPU401_HW_VIA686A 13 /* VIA 82C686A */
41#define MPU401_HW_YMFPCI 14 /* YMF DS-XG PCI */
42#define MPU401_HW_CMIPCI 15 /* CMIPCI MPU-401 UART */
43#define MPU401_HW_ALS4000 16 /* Avance Logic ALS4000 */
44#define MPU401_HW_INTEL8X0 17 /* Intel8x0 driver */
45#define MPU401_HW_PC98II 18 /* Roland PC98II */
46#define MPU401_HW_AUREAL 19 /* Aureal Vortex */
47
48#define MPU401_MODE_BIT_INPUT 0
49#define MPU401_MODE_BIT_OUTPUT 1
50#define MPU401_MODE_BIT_INPUT_TRIGGER 2
51#define MPU401_MODE_BIT_OUTPUT_TRIGGER 3
52
53#define MPU401_MODE_INPUT (1<<MPU401_MODE_BIT_INPUT)
54#define MPU401_MODE_OUTPUT (1<<MPU401_MODE_BIT_OUTPUT)
55#define MPU401_MODE_INPUT_TRIGGER (1<<MPU401_MODE_BIT_INPUT_TRIGGER)
56#define MPU401_MODE_OUTPUT_TRIGGER (1<<MPU401_MODE_BIT_OUTPUT_TRIGGER)
57
58#define MPU401_MODE_INPUT_TIMER (1<<0)
59#define MPU401_MODE_OUTPUT_TIMER (1<<1)
60
61typedef struct _snd_mpu401 mpu401_t;
62
63struct _snd_mpu401 {
64 snd_rawmidi_t *rmidi;
65
66 unsigned short hardware; /* MPU401_HW_XXXX */
67 unsigned long port; /* base port of MPU-401 chip */
68 unsigned long cport; /* port + 1 (usually) */
69 struct resource *res; /* port resource */
70 int irq; /* IRQ number of MPU-401 chip (-1 = poll) */
71 int irq_flags;
72
73 unsigned long mode; /* MPU401_MODE_XXXX */
74 int timer_invoked;
75
76 int (*open_input) (mpu401_t * mpu);
77 void (*close_input) (mpu401_t * mpu);
78 int (*open_output) (mpu401_t * mpu);
79 void (*close_output) (mpu401_t * mpu);
80 void *private_data;
81
82 snd_rawmidi_substream_t *substream_input;
83 snd_rawmidi_substream_t *substream_output;
84
85 spinlock_t input_lock;
86 spinlock_t output_lock;
87 spinlock_t timer_lock;
88
89 struct timer_list timer;
90
91 void (*write) (mpu401_t * mpu, unsigned char data, unsigned long addr);
92 unsigned char (*read) (mpu401_t * mpu, unsigned long addr);
93};
94
95/* I/O ports */
96
97#define MPU401C(mpu) (mpu)->cport
98#define MPU401D(mpu) (mpu)->port
99
100/*
101
102 */
103
104irqreturn_t snd_mpu401_uart_interrupt(int irq, void *dev_id, struct pt_regs *regs);
105
106int snd_mpu401_uart_new(snd_card_t * card,
107 int device,
108 unsigned short hardware,
109 unsigned long port,
110 int integrated,
111 int irq,
112 int irq_flags,
113 snd_rawmidi_t ** rrawmidi);
114
115#endif /* __SOUND_MPU401_H */
diff --git a/include/sound/opl3.h b/include/sound/opl3.h
new file mode 100644
index 000000000000..19f657d4fc06
--- /dev/null
+++ b/include/sound/opl3.h
@@ -0,0 +1,339 @@
1#ifndef __SOUND_OPL3_H
2#define __SOUND_OPL3_H
3
4/*
5 * Definitions of the OPL-3 registers.
6 *
7 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
8 * Hannu Savolainen 1993-1996
9 *
10 *
11 * The OPL-3 mode is switched on by writing 0x01, to the offset 5
12 * of the right side.
13 *
14 * Another special register at the right side is at offset 4. It contains
15 * a bit mask defining which voices are used as 4 OP voices.
16 *
17 * The percussive mode is implemented in the left side only.
18 *
19 * With the above exceptions the both sides can be operated independently.
20 *
21 * A 4 OP voice can be created by setting the corresponding
22 * bit at offset 4 of the right side.
23 *
24 * For example setting the rightmost bit (0x01) changes the
25 * first voice on the right side to the 4 OP mode. The fourth
26 * voice is made inaccessible.
27 *
28 * If a voice is set to the 2 OP mode, it works like 2 OP modes
29 * of the original YM3812 (AdLib). In addition the voice can
30 * be connected the left, right or both stereo channels. It can
31 * even be left unconnected. This works with 4 OP voices also.
32 *
33 * The stereo connection bits are located in the FEEDBACK_CONNECTION
34 * register of the voice (0xC0-0xC8). In 4 OP voices these bits are
35 * in the second half of the voice.
36 *
37 *
38 * This program is free software; you can redistribute it and/or modify
39 * it under the terms of the GNU General Public License as published by
40 * the Free Software Foundation; either version 2 of the License, or
41 * (at your option) any later version.
42 *
43 * This program is distributed in the hope that it will be useful,
44 * but WITHOUT ANY WARRANTY; without even the implied warranty of
45 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46 * GNU General Public License for more details.
47 *
48 * You should have received a copy of the GNU General Public License
49 * along with this program; if not, write to the Free Software
50 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
51 *
52 */
53
54#include "driver.h"
55#include <linux/time.h>
56#include "core.h"
57#include "hwdep.h"
58#include "timer.h"
59#include "seq_midi_emul.h"
60#ifdef CONFIG_SND_SEQUENCER_OSS
61#include "seq_oss.h"
62#include "seq_oss_legacy.h"
63#endif
64#include "seq_device.h"
65#include "ainstr_fm.h"
66
67/*
68 * Register numbers for the global registers
69 */
70
71#define OPL3_REG_TEST 0x01
72#define OPL3_ENABLE_WAVE_SELECT 0x20
73
74#define OPL3_REG_TIMER1 0x02
75#define OPL3_REG_TIMER2 0x03
76#define OPL3_REG_TIMER_CONTROL 0x04 /* Left side */
77#define OPL3_IRQ_RESET 0x80
78#define OPL3_TIMER1_MASK 0x40
79#define OPL3_TIMER2_MASK 0x20
80#define OPL3_TIMER1_START 0x01
81#define OPL3_TIMER2_START 0x02
82
83#define OPL3_REG_CONNECTION_SELECT 0x04 /* Right side */
84#define OPL3_LEFT_4OP_0 0x01
85#define OPL3_LEFT_4OP_1 0x02
86#define OPL3_LEFT_4OP_2 0x04
87#define OPL3_RIGHT_4OP_0 0x08
88#define OPL3_RIGHT_4OP_1 0x10
89#define OPL3_RIGHT_4OP_2 0x20
90
91#define OPL3_REG_MODE 0x05 /* Right side */
92#define OPL3_OPL3_ENABLE 0x01 /* OPL3 mode */
93#define OPL3_OPL4_ENABLE 0x02 /* OPL4 mode */
94
95#define OPL3_REG_KBD_SPLIT 0x08 /* Left side */
96#define OPL3_COMPOSITE_SINE_WAVE_MODE 0x80 /* Don't use with OPL-3? */
97#define OPL3_KEYBOARD_SPLIT 0x40
98
99#define OPL3_REG_PERCUSSION 0xbd /* Left side only */
100#define OPL3_TREMOLO_DEPTH 0x80
101#define OPL3_VIBRATO_DEPTH 0x40
102#define OPL3_PERCUSSION_ENABLE 0x20
103#define OPL3_BASSDRUM_ON 0x10
104#define OPL3_SNAREDRUM_ON 0x08
105#define OPL3_TOMTOM_ON 0x04
106#define OPL3_CYMBAL_ON 0x02
107#define OPL3_HIHAT_ON 0x01
108
109/*
110 * Offsets to the register banks for operators. To get the
111 * register number just add the operator offset to the bank offset
112 *
113 * AM/VIB/EG/KSR/Multiple (0x20 to 0x35)
114 */
115#define OPL3_REG_AM_VIB 0x20
116#define OPL3_TREMOLO_ON 0x80
117#define OPL3_VIBRATO_ON 0x40
118#define OPL3_SUSTAIN_ON 0x20
119#define OPL3_KSR 0x10 /* Key scaling rate */
120#define OPL3_MULTIPLE_MASK 0x0f /* Frequency multiplier */
121
122 /*
123 * KSL/Total level (0x40 to 0x55)
124 */
125#define OPL3_REG_KSL_LEVEL 0x40
126#define OPL3_KSL_MASK 0xc0 /* Envelope scaling bits */
127#define OPL3_TOTAL_LEVEL_MASK 0x3f /* Strength (volume) of OP */
128
129/*
130 * Attack / Decay rate (0x60 to 0x75)
131 */
132#define OPL3_REG_ATTACK_DECAY 0x60
133#define OPL3_ATTACK_MASK 0xf0
134#define OPL3_DECAY_MASK 0x0f
135
136/*
137 * Sustain level / Release rate (0x80 to 0x95)
138 */
139#define OPL3_REG_SUSTAIN_RELEASE 0x80
140#define OPL3_SUSTAIN_MASK 0xf0
141#define OPL3_RELEASE_MASK 0x0f
142
143/*
144 * Wave select (0xE0 to 0xF5)
145 */
146#define OPL3_REG_WAVE_SELECT 0xe0
147#define OPL3_WAVE_SELECT_MASK 0x07
148
149/*
150 * Offsets to the register banks for voices. Just add to the
151 * voice number to get the register number.
152 *
153 * F-Number low bits (0xA0 to 0xA8).
154 */
155#define OPL3_REG_FNUM_LOW 0xa0
156
157/*
158 * F-number high bits / Key on / Block (octave) (0xB0 to 0xB8)
159 */
160#define OPL3_REG_KEYON_BLOCK 0xb0
161#define OPL3_KEYON_BIT 0x20
162#define OPL3_BLOCKNUM_MASK 0x1c
163#define OPL3_FNUM_HIGH_MASK 0x03
164
165/*
166 * Feedback / Connection (0xc0 to 0xc8)
167 *
168 * These registers have two new bits when the OPL-3 mode
169 * is selected. These bits controls connecting the voice
170 * to the stereo channels. For 4 OP voices this bit is
171 * defined in the second half of the voice (add 3 to the
172 * register offset).
173 *
174 * For 4 OP voices the connection bit is used in the
175 * both halves (gives 4 ways to connect the operators).
176 */
177#define OPL3_REG_FEEDBACK_CONNECTION 0xc0
178#define OPL3_FEEDBACK_MASK 0x0e /* Valid just for 1st OP of a voice */
179#define OPL3_CONNECTION_BIT 0x01
180/*
181 * In the 4 OP mode there is four possible configurations how the
182 * operators can be connected together (in 2 OP modes there is just
183 * AM or FM). The 4 OP connection mode is defined by the rightmost
184 * bit of the FEEDBACK_CONNECTION (0xC0-0xC8) on the both halves.
185 *
186 * First half Second half Mode
187 *
188 * +---+
189 * v |
190 * 0 0 >+-1-+--2--3--4-->
191 *
192 *
193 *
194 * +---+
195 * | |
196 * 0 1 >+-1-+--2-+
197 * |->
198 * >--3----4-+
199 *
200 * +---+
201 * | |
202 * 1 0 >+-1-+-----+
203 * |->
204 * >--2--3--4-+
205 *
206 * +---+
207 * | |
208 * 1 1 >+-1-+--+
209 * |
210 * >--2--3-+->
211 * |
212 * >--4----+
213 */
214#define OPL3_STEREO_BITS 0x30 /* OPL-3 only */
215#define OPL3_VOICE_TO_LEFT 0x10
216#define OPL3_VOICE_TO_RIGHT 0x20
217
218/*
219
220 */
221
222#define OPL3_LEFT 0x0000
223#define OPL3_RIGHT 0x0100
224
225#define OPL3_HW_AUTO 0x0000
226#define OPL3_HW_OPL2 0x0200
227#define OPL3_HW_OPL3 0x0300
228#define OPL3_HW_OPL3_SV 0x0301 /* S3 SonicVibes */
229#define OPL3_HW_OPL3_CS 0x0302 /* CS4232/CS4236+ */
230#define OPL3_HW_OPL3_FM801 0x0303 /* FM801 */
231#define OPL3_HW_OPL3_CS4281 0x0304 /* CS4281 */
232#define OPL3_HW_OPL3_PC98 0x0305 /* PC9800 */
233#define OPL3_HW_OPL4 0x0400 /* YMF278B/YMF295 */
234#define OPL3_HW_OPL4_ML 0x0401 /* YMF704/YMF721 */
235#define OPL3_HW_MASK 0xff00
236
237#define MAX_OPL2_VOICES 9
238#define MAX_OPL3_VOICES 18
239
240typedef struct snd_opl3 opl3_t;
241
242/*
243 * A structure to keep track of each hardware voice
244 */
245typedef struct snd_opl3_voice {
246 int state; /* status */
247#define SNDRV_OPL3_ST_OFF 0 /* Not playing */
248#define SNDRV_OPL3_ST_ON_2OP 1 /* 2op voice is allocated */
249#define SNDRV_OPL3_ST_ON_4OP 2 /* 4op voice is allocated */
250#define SNDRV_OPL3_ST_NOT_AVAIL -1 /* voice is not available */
251
252 unsigned int time; /* An allocation time */
253 unsigned char note; /* Note currently assigned to this voice */
254
255 unsigned long note_off; /* note-off time */
256 int note_off_check; /* check note-off time */
257
258 unsigned char keyon_reg; /* KON register shadow */
259
260 snd_midi_channel_t *chan; /* Midi channel for this note */
261} snd_opl3_voice_t;
262
263struct snd_opl3 {
264 unsigned long l_port;
265 unsigned long r_port;
266 struct resource *res_l_port;
267 struct resource *res_r_port;
268 unsigned short hardware;
269 /* hardware access */
270 void (*command) (opl3_t * opl3, unsigned short cmd, unsigned char val);
271 unsigned short timer_enable;
272 int seq_dev_num; /* sequencer device number */
273 snd_timer_t *timer1;
274 snd_timer_t *timer2;
275 spinlock_t timer_lock;
276
277 void *private_data;
278 void (*private_free)(opl3_t *);
279
280 spinlock_t reg_lock;
281 snd_card_t *card; /* The card that this belongs to */
282 int used; /* usage flag - exclusive */
283 unsigned char fm_mode; /* OPL mode, see SNDRV_DM_FM_MODE_XXX */
284 unsigned char rhythm; /* percussion mode flag */
285 unsigned char max_voices; /* max number of voices */
286#if defined(CONFIG_SND_SEQUENCER) || defined(CONFIG_SND_SEQUENCER_MODULE)
287#define SNDRV_OPL3_MODE_SYNTH 0 /* OSS - voices allocated by application */
288#define SNDRV_OPL3_MODE_SEQ 1 /* ALSA - driver handles voice allocation */
289 int synth_mode; /* synth mode */
290 int seq_client;
291
292 snd_seq_device_t *seq_dev; /* sequencer device */
293 snd_midi_channel_set_t * chset;
294
295#ifdef CONFIG_SND_SEQUENCER_OSS
296 snd_seq_device_t *oss_seq_dev; /* OSS sequencer device */
297 snd_midi_channel_set_t * oss_chset;
298#endif
299
300 snd_seq_kinstr_ops_t fm_ops;
301 snd_seq_kinstr_list_t *ilist;
302
303 snd_opl3_voice_t voices[MAX_OPL3_VOICES]; /* Voices (OPL3 'channel') */
304 int use_time; /* allocation counter */
305
306 unsigned short connection_reg; /* connection reg shadow */
307 unsigned char drum_reg; /* percussion reg shadow */
308
309 spinlock_t voice_lock; /* Lock for voice access */
310
311 struct timer_list tlist; /* timer for note-offs and effects */
312 int sys_timer_status; /* system timer run status */
313 spinlock_t sys_timer_lock; /* Lock for system timer access */
314#endif
315 struct semaphore access_mutex; /* locking */
316};
317
318/* opl3.c */
319void snd_opl3_interrupt(snd_hwdep_t * hw);
320int snd_opl3_new(snd_card_t *card, unsigned short hardware, opl3_t **ropl3);
321int snd_opl3_init(opl3_t *opl3);
322int snd_opl3_create(snd_card_t * card,
323 unsigned long l_port, unsigned long r_port,
324 unsigned short hardware,
325 int integrated,
326 opl3_t ** opl3);
327int snd_opl3_timer_new(opl3_t * opl3, int timer1_dev, int timer2_dev);
328int snd_opl3_hwdep_new(opl3_t * opl3, int device, int seq_device,
329 snd_hwdep_t ** rhwdep);
330
331/* opl3_synth */
332int snd_opl3_open(snd_hwdep_t * hw, struct file *file);
333int snd_opl3_ioctl(snd_hwdep_t * hw, struct file *file,
334 unsigned int cmd, unsigned long arg);
335int snd_opl3_release(snd_hwdep_t * hw, struct file *file);
336
337void snd_opl3_reset(opl3_t * opl3);
338
339#endif /* __SOUND_OPL3_H */
diff --git a/include/sound/opl4.h b/include/sound/opl4.h
new file mode 100644
index 000000000000..20c04428b139
--- /dev/null
+++ b/include/sound/opl4.h
@@ -0,0 +1,32 @@
1#ifndef __SOUND_OPL4_H
2#define __SOUND_OPL4_H
3
4/*
5 * Global definitions for the OPL4 driver
6 * Copyright (c) 2003 by Clemens Ladisch <clemens@ladisch.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <sound/opl3.h>
24
25typedef struct opl4 opl4_t;
26
27extern int snd_opl4_create(snd_card_t *card,
28 unsigned long fm_port, unsigned long pcm_port,
29 int seq_device,
30 opl3_t **opl3, opl4_t **opl4);
31
32#endif /* __SOUND_OPL4_H */
diff --git a/include/sound/pcm-indirect.h b/include/sound/pcm-indirect.h
new file mode 100644
index 000000000000..31fa7a54508a
--- /dev/null
+++ b/include/sound/pcm-indirect.h
@@ -0,0 +1,177 @@
1/*
2 * Helper functions for indirect PCM data transfer
3 *
4 * Copyright (c) by Takashi Iwai <tiwai@suse.de>
5 * Jaroslav Kysela <perex@suse.cz>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __SOUND_PCM_INDIRECT_H
23#define __SOUND_PCM_INDIRECT_H
24
25#include <sound/pcm.h>
26
27typedef struct sndrv_pcm_indirect {
28 unsigned int hw_buffer_size; /* Byte size of hardware buffer */
29 unsigned int hw_queue_size; /* Max queue size of hw buffer (0 = buffer size) */
30 unsigned int hw_data; /* Offset to next dst (or src) in hw ring buffer */
31 unsigned int hw_io; /* Ring buffer hw pointer */
32 int hw_ready; /* Bytes ready for play (or captured) in hw ring buffer */
33 unsigned int sw_buffer_size; /* Byte size of software buffer */
34 unsigned int sw_data; /* Offset to next dst (or src) in sw ring buffer */
35 unsigned int sw_io; /* Current software pointer in bytes */
36 int sw_ready; /* Bytes ready to be transferred to/from hw */
37 snd_pcm_uframes_t appl_ptr; /* Last seen appl_ptr */
38} snd_pcm_indirect_t;
39
40typedef void (*snd_pcm_indirect_copy_t)(snd_pcm_substream_t *substream,
41 snd_pcm_indirect_t *rec, size_t bytes);
42
43/*
44 * helper function for playback ack callback
45 */
46static inline void
47snd_pcm_indirect_playback_transfer(snd_pcm_substream_t *substream,
48 snd_pcm_indirect_t *rec,
49 snd_pcm_indirect_copy_t copy)
50{
51 snd_pcm_runtime_t *runtime = substream->runtime;
52 snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr;
53 snd_pcm_sframes_t diff = appl_ptr - rec->appl_ptr;
54 int qsize;
55
56 if (diff) {
57 if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2))
58 diff += runtime->boundary;
59 rec->sw_ready += (int)frames_to_bytes(runtime, diff);
60 rec->appl_ptr = appl_ptr;
61 }
62 qsize = rec->hw_queue_size ? rec->hw_queue_size : rec->hw_buffer_size;
63 while (rec->hw_ready < qsize && rec->sw_ready > 0) {
64 unsigned int hw_to_end = rec->hw_buffer_size - rec->hw_data;
65 unsigned int sw_to_end = rec->sw_buffer_size - rec->sw_data;
66 unsigned int bytes = qsize - rec->hw_ready;
67 if (rec->sw_ready < (int)bytes)
68 bytes = rec->sw_ready;
69 if (hw_to_end < bytes)
70 bytes = hw_to_end;
71 if (sw_to_end < bytes)
72 bytes = sw_to_end;
73 if (! bytes)
74 break;
75 copy(substream, rec, bytes);
76 rec->hw_data += bytes;
77 if (rec->hw_data == rec->hw_buffer_size)
78 rec->hw_data = 0;
79 rec->sw_data += bytes;
80 if (rec->sw_data == rec->sw_buffer_size)
81 rec->sw_data = 0;
82 rec->hw_ready += bytes;
83 rec->sw_ready -= bytes;
84 }
85}
86
87/*
88 * helper function for playback pointer callback
89 * ptr = current byte pointer
90 */
91static inline snd_pcm_uframes_t
92snd_pcm_indirect_playback_pointer(snd_pcm_substream_t *substream,
93 snd_pcm_indirect_t *rec, unsigned int ptr)
94{
95 int bytes = ptr - rec->hw_io;
96 if (bytes < 0)
97 bytes += rec->hw_buffer_size;
98 rec->hw_io = ptr;
99 rec->hw_ready -= bytes;
100 rec->sw_io += bytes;
101 if (rec->sw_io >= rec->sw_buffer_size)
102 rec->sw_io -= rec->sw_buffer_size;
103 if (substream->ops->ack)
104 substream->ops->ack(substream);
105 return bytes_to_frames(substream->runtime, rec->sw_io);
106}
107
108
109/*
110 * helper function for capture ack callback
111 */
112static inline void
113snd_pcm_indirect_capture_transfer(snd_pcm_substream_t *substream,
114 snd_pcm_indirect_t *rec,
115 snd_pcm_indirect_copy_t copy)
116{
117 snd_pcm_runtime_t *runtime = substream->runtime;
118 snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr;
119 snd_pcm_sframes_t diff = appl_ptr - rec->appl_ptr;
120
121 if (diff) {
122 if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2))
123 diff += runtime->boundary;
124 rec->sw_ready -= frames_to_bytes(runtime, diff);
125 rec->appl_ptr = appl_ptr;
126 }
127 while (rec->hw_ready > 0 &&
128 rec->sw_ready < (int)rec->sw_buffer_size) {
129 size_t hw_to_end = rec->hw_buffer_size - rec->hw_data;
130 size_t sw_to_end = rec->sw_buffer_size - rec->sw_data;
131 size_t bytes = rec->sw_buffer_size - rec->sw_ready;
132 if (rec->hw_ready < (int)bytes)
133 bytes = rec->hw_ready;
134 if (hw_to_end < bytes)
135 bytes = hw_to_end;
136 if (sw_to_end < bytes)
137 bytes = sw_to_end;
138 if (! bytes)
139 break;
140 copy(substream, rec, bytes);
141 rec->hw_data += bytes;
142 if ((int)rec->hw_data == rec->hw_buffer_size)
143 rec->hw_data = 0;
144 rec->sw_data += bytes;
145 if (rec->sw_data == rec->sw_buffer_size)
146 rec->sw_data = 0;
147 rec->hw_ready -= bytes;
148 rec->sw_ready += bytes;
149 }
150}
151
152/*
153 * helper function for capture pointer callback,
154 * ptr = current byte pointer
155 */
156static inline snd_pcm_uframes_t
157snd_pcm_indirect_capture_pointer(snd_pcm_substream_t *substream,
158 snd_pcm_indirect_t *rec, unsigned int ptr)
159{
160 int qsize;
161 int bytes = ptr - rec->hw_io;
162 if (bytes < 0)
163 bytes += rec->hw_buffer_size;
164 rec->hw_io = ptr;
165 rec->hw_ready += bytes;
166 qsize = rec->hw_queue_size ? rec->hw_queue_size : rec->hw_buffer_size;
167 if (rec->hw_ready > qsize)
168 return SNDRV_PCM_POS_XRUN;
169 rec->sw_io += bytes;
170 if (rec->sw_io >= rec->sw_buffer_size)
171 rec->sw_io -= rec->sw_buffer_size;
172 if (substream->ops->ack)
173 substream->ops->ack(substream);
174 return bytes_to_frames(substream->runtime, rec->sw_io);
175}
176
177#endif /* __SOUND_PCM_INDIRECT_H */
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
new file mode 100644
index 000000000000..53fc04d75bad
--- /dev/null
+++ b/include/sound/pcm.h
@@ -0,0 +1,1040 @@
1#ifndef __SOUND_PCM_H
2#define __SOUND_PCM_H
3
4/*
5 * Digital Audio (PCM) abstract layer
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 * Abramo Bagnara <abramo@alsa-project.org>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include <sound/asound.h>
27#include <sound/memalloc.h>
28#include <linux/poll.h>
29#include <linux/bitops.h>
30
31typedef sndrv_pcm_uframes_t snd_pcm_uframes_t;
32typedef sndrv_pcm_sframes_t snd_pcm_sframes_t;
33typedef enum sndrv_pcm_class snd_pcm_class_t;
34typedef enum sndrv_pcm_subclass snd_pcm_subclass_t;
35typedef enum sndrv_pcm_stream snd_pcm_stream_t;
36typedef enum sndrv_pcm_access snd_pcm_access_t;
37typedef enum sndrv_pcm_format snd_pcm_format_t;
38typedef enum sndrv_pcm_subformat snd_pcm_subformat_t;
39typedef enum sndrv_pcm_state snd_pcm_state_t;
40typedef union sndrv_pcm_sync_id snd_pcm_sync_id_t;
41typedef struct sndrv_pcm_info snd_pcm_info_t;
42typedef enum sndrv_pcm_hw_param snd_pcm_hw_param_t;
43typedef struct sndrv_pcm_hw_params snd_pcm_hw_params_t;
44typedef enum sndrv_pcm_start snd_pcm_start_t;
45typedef enum sndrv_pcm_xrun snd_pcm_xrun_t;
46typedef enum sndrv_pcm_tstamp snd_pcm_tstamp_t;
47typedef struct sndrv_pcm_sw_params snd_pcm_sw_params_t;
48typedef struct sndrv_pcm_channel_info snd_pcm_channel_info_t;
49typedef struct sndrv_pcm_status snd_pcm_status_t;
50typedef struct sndrv_pcm_mmap_status snd_pcm_mmap_status_t;
51typedef struct sndrv_pcm_mmap_control snd_pcm_mmap_control_t;
52typedef struct sndrv_mask snd_mask_t;
53typedef struct snd_sg_buf snd_pcm_sgbuf_t;
54
55#define snd_pcm_substream_chip(substream) ((substream)->private_data)
56#define snd_pcm_chip(pcm) ((pcm)->private_data)
57
58typedef struct _snd_pcm_file snd_pcm_file_t;
59typedef struct _snd_pcm_runtime snd_pcm_runtime_t;
60
61#if defined(CONFIG_SND_PCM_OSS) || defined(CONFIG_SND_PCM_OSS_MODULE)
62#include "pcm_oss.h"
63#endif
64
65/*
66 * Hardware (lowlevel) section
67 */
68
69typedef struct _snd_pcm_hardware {
70 unsigned int info; /* SNDRV_PCM_INFO_* */
71 u64 formats; /* SNDRV_PCM_FMTBIT_* */
72 unsigned int rates; /* SNDRV_PCM_RATE_* */
73 unsigned int rate_min; /* min rate */
74 unsigned int rate_max; /* max rate */
75 unsigned int channels_min; /* min channels */
76 unsigned int channels_max; /* max channels */
77 size_t buffer_bytes_max; /* max buffer size */
78 size_t period_bytes_min; /* min period size */
79 size_t period_bytes_max; /* max period size */
80 unsigned int periods_min; /* min # of periods */
81 unsigned int periods_max; /* max # of periods */
82 size_t fifo_size; /* fifo size in bytes */
83} snd_pcm_hardware_t;
84
85typedef struct _snd_pcm_ops {
86 int (*open)(snd_pcm_substream_t *substream);
87 int (*close)(snd_pcm_substream_t *substream);
88 int (*ioctl)(snd_pcm_substream_t * substream,
89 unsigned int cmd, void *arg);
90 int (*hw_params)(snd_pcm_substream_t * substream, snd_pcm_hw_params_t * params);
91 int (*hw_free)(snd_pcm_substream_t *substream);
92 int (*prepare)(snd_pcm_substream_t * substream);
93 int (*trigger)(snd_pcm_substream_t * substream, int cmd);
94 snd_pcm_uframes_t (*pointer)(snd_pcm_substream_t * substream);
95 int (*copy)(snd_pcm_substream_t *substream, int channel, snd_pcm_uframes_t pos,
96 void __user *buf, snd_pcm_uframes_t count);
97 int (*silence)(snd_pcm_substream_t *substream, int channel,
98 snd_pcm_uframes_t pos, snd_pcm_uframes_t count);
99 struct page *(*page)(snd_pcm_substream_t *substream, unsigned long offset);
100 int (*mmap)(snd_pcm_substream_t *substream, struct vm_area_struct *vma);
101 int (*ack)(snd_pcm_substream_t *substream);
102} snd_pcm_ops_t;
103
104/*
105 *
106 */
107
108#define SNDRV_PCM_DEVICES 8
109
110#define SNDRV_PCM_IOCTL1_FALSE ((void *)0)
111#define SNDRV_PCM_IOCTL1_TRUE ((void *)1)
112
113#define SNDRV_PCM_IOCTL1_RESET 0
114#define SNDRV_PCM_IOCTL1_INFO 1
115#define SNDRV_PCM_IOCTL1_CHANNEL_INFO 2
116#define SNDRV_PCM_IOCTL1_GSTATE 3
117
118#define SNDRV_PCM_TRIGGER_STOP 0
119#define SNDRV_PCM_TRIGGER_START 1
120#define SNDRV_PCM_TRIGGER_PAUSE_PUSH 3
121#define SNDRV_PCM_TRIGGER_PAUSE_RELEASE 4
122#define SNDRV_PCM_TRIGGER_SUSPEND 5
123#define SNDRV_PCM_TRIGGER_RESUME 6
124
125#define SNDRV_PCM_POS_XRUN ((snd_pcm_uframes_t)-1)
126
127/* If you change this don't forget to change rates[] table in pcm_native.c */
128#define SNDRV_PCM_RATE_5512 (1<<0) /* 5512Hz */
129#define SNDRV_PCM_RATE_8000 (1<<1) /* 8000Hz */
130#define SNDRV_PCM_RATE_11025 (1<<2) /* 11025Hz */
131#define SNDRV_PCM_RATE_16000 (1<<3) /* 16000Hz */
132#define SNDRV_PCM_RATE_22050 (1<<4) /* 22050Hz */
133#define SNDRV_PCM_RATE_32000 (1<<5) /* 32000Hz */
134#define SNDRV_PCM_RATE_44100 (1<<6) /* 44100Hz */
135#define SNDRV_PCM_RATE_48000 (1<<7) /* 48000Hz */
136#define SNDRV_PCM_RATE_64000 (1<<8) /* 64000Hz */
137#define SNDRV_PCM_RATE_88200 (1<<9) /* 88200Hz */
138#define SNDRV_PCM_RATE_96000 (1<<10) /* 96000Hz */
139#define SNDRV_PCM_RATE_176400 (1<<11) /* 176400Hz */
140#define SNDRV_PCM_RATE_192000 (1<<12) /* 192000Hz */
141
142#define SNDRV_PCM_RATE_CONTINUOUS (1<<30) /* continuous range */
143#define SNDRV_PCM_RATE_KNOT (1<<31) /* supports more non-continuos rates */
144
145#define SNDRV_PCM_RATE_8000_44100 (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_11025|\
146 SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_22050|\
147 SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100)
148#define SNDRV_PCM_RATE_8000_48000 (SNDRV_PCM_RATE_8000_44100|SNDRV_PCM_RATE_48000)
149#define SNDRV_PCM_RATE_8000_96000 (SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_64000|\
150 SNDRV_PCM_RATE_88200|SNDRV_PCM_RATE_96000)
151#define SNDRV_PCM_RATE_8000_192000 (SNDRV_PCM_RATE_8000_96000|SNDRV_PCM_RATE_176400|\
152 SNDRV_PCM_RATE_192000)
153#define SNDRV_PCM_FMTBIT_S8 (1ULL << SNDRV_PCM_FORMAT_S8)
154#define SNDRV_PCM_FMTBIT_U8 (1ULL << SNDRV_PCM_FORMAT_U8)
155#define SNDRV_PCM_FMTBIT_S16_LE (1ULL << SNDRV_PCM_FORMAT_S16_LE)
156#define SNDRV_PCM_FMTBIT_S16_BE (1ULL << SNDRV_PCM_FORMAT_S16_BE)
157#define SNDRV_PCM_FMTBIT_U16_LE (1ULL << SNDRV_PCM_FORMAT_U16_LE)
158#define SNDRV_PCM_FMTBIT_U16_BE (1ULL << SNDRV_PCM_FORMAT_U16_BE)
159#define SNDRV_PCM_FMTBIT_S24_LE (1ULL << SNDRV_PCM_FORMAT_S24_LE)
160#define SNDRV_PCM_FMTBIT_S24_BE (1ULL << SNDRV_PCM_FORMAT_S24_BE)
161#define SNDRV_PCM_FMTBIT_U24_LE (1ULL << SNDRV_PCM_FORMAT_U24_LE)
162#define SNDRV_PCM_FMTBIT_U24_BE (1ULL << SNDRV_PCM_FORMAT_U24_BE)
163#define SNDRV_PCM_FMTBIT_S32_LE (1ULL << SNDRV_PCM_FORMAT_S32_LE)
164#define SNDRV_PCM_FMTBIT_S32_BE (1ULL << SNDRV_PCM_FORMAT_S32_BE)
165#define SNDRV_PCM_FMTBIT_U32_LE (1ULL << SNDRV_PCM_FORMAT_U32_LE)
166#define SNDRV_PCM_FMTBIT_U32_BE (1ULL << SNDRV_PCM_FORMAT_U32_BE)
167#define SNDRV_PCM_FMTBIT_FLOAT_LE (1ULL << SNDRV_PCM_FORMAT_FLOAT_LE)
168#define SNDRV_PCM_FMTBIT_FLOAT_BE (1ULL << SNDRV_PCM_FORMAT_FLOAT_BE)
169#define SNDRV_PCM_FMTBIT_FLOAT64_LE (1ULL << SNDRV_PCM_FORMAT_FLOAT64_LE)
170#define SNDRV_PCM_FMTBIT_FLOAT64_BE (1ULL << SNDRV_PCM_FORMAT_FLOAT64_BE)
171#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE (1ULL << SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE)
172#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE (1ULL << SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE)
173#define SNDRV_PCM_FMTBIT_MU_LAW (1ULL << SNDRV_PCM_FORMAT_MU_LAW)
174#define SNDRV_PCM_FMTBIT_A_LAW (1ULL << SNDRV_PCM_FORMAT_A_LAW)
175#define SNDRV_PCM_FMTBIT_IMA_ADPCM (1ULL << SNDRV_PCM_FORMAT_IMA_ADPCM)
176#define SNDRV_PCM_FMTBIT_MPEG (1ULL << SNDRV_PCM_FORMAT_MPEG)
177#define SNDRV_PCM_FMTBIT_GSM (1ULL << SNDRV_PCM_FORMAT_GSM)
178#define SNDRV_PCM_FMTBIT_SPECIAL (1ULL << SNDRV_PCM_FORMAT_SPECIAL)
179#define SNDRV_PCM_FMTBIT_S24_3LE (1ULL << SNDRV_PCM_FORMAT_S24_3LE)
180#define SNDRV_PCM_FMTBIT_U24_3LE (1ULL << SNDRV_PCM_FORMAT_U24_3LE)
181#define SNDRV_PCM_FMTBIT_S24_3BE (1ULL << SNDRV_PCM_FORMAT_S24_3BE)
182#define SNDRV_PCM_FMTBIT_U24_3BE (1ULL << SNDRV_PCM_FORMAT_U24_3BE)
183#define SNDRV_PCM_FMTBIT_S20_3LE (1ULL << SNDRV_PCM_FORMAT_S20_3LE)
184#define SNDRV_PCM_FMTBIT_U20_3LE (1ULL << SNDRV_PCM_FORMAT_U20_3LE)
185#define SNDRV_PCM_FMTBIT_S20_3BE (1ULL << SNDRV_PCM_FORMAT_S20_3BE)
186#define SNDRV_PCM_FMTBIT_U20_3BE (1ULL << SNDRV_PCM_FORMAT_U20_3BE)
187#define SNDRV_PCM_FMTBIT_S18_3LE (1ULL << SNDRV_PCM_FORMAT_S18_3LE)
188#define SNDRV_PCM_FMTBIT_U18_3LE (1ULL << SNDRV_PCM_FORMAT_U18_3LE)
189#define SNDRV_PCM_FMTBIT_S18_3BE (1ULL << SNDRV_PCM_FORMAT_S18_3BE)
190#define SNDRV_PCM_FMTBIT_U18_3BE (1ULL << SNDRV_PCM_FORMAT_U18_3BE)
191
192#ifdef SNDRV_LITTLE_ENDIAN
193#define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_LE
194#define SNDRV_PCM_FMTBIT_U16 SNDRV_PCM_FMTBIT_U16_LE
195#define SNDRV_PCM_FMTBIT_S24 SNDRV_PCM_FMTBIT_S24_LE
196#define SNDRV_PCM_FMTBIT_U24 SNDRV_PCM_FMTBIT_U24_LE
197#define SNDRV_PCM_FMTBIT_S32 SNDRV_PCM_FMTBIT_S32_LE
198#define SNDRV_PCM_FMTBIT_U32 SNDRV_PCM_FMTBIT_U32_LE
199#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_LE
200#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_LE
201#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
202#endif
203#ifdef SNDRV_BIG_ENDIAN
204#define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_BE
205#define SNDRV_PCM_FMTBIT_U16 SNDRV_PCM_FMTBIT_U16_BE
206#define SNDRV_PCM_FMTBIT_S24 SNDRV_PCM_FMTBIT_S24_BE
207#define SNDRV_PCM_FMTBIT_U24 SNDRV_PCM_FMTBIT_U24_BE
208#define SNDRV_PCM_FMTBIT_S32 SNDRV_PCM_FMTBIT_S32_BE
209#define SNDRV_PCM_FMTBIT_U32 SNDRV_PCM_FMTBIT_U32_BE
210#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_BE
211#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_BE
212#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE
213#endif
214
215struct _snd_pcm_file {
216 snd_pcm_substream_t * substream;
217 struct _snd_pcm_file * next;
218};
219
220typedef struct _snd_pcm_hw_rule snd_pcm_hw_rule_t;
221
222typedef int (*snd_pcm_hw_rule_func_t)(snd_pcm_hw_params_t *params,
223 snd_pcm_hw_rule_t *rule);
224
225struct _snd_pcm_hw_rule {
226 unsigned int cond;
227 snd_pcm_hw_rule_func_t func;
228 int var;
229 int deps[4];
230 void *private;
231};
232
233typedef struct _snd_pcm_hw_constraints {
234 snd_mask_t masks[SNDRV_PCM_HW_PARAM_LAST_MASK -
235 SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
236 snd_interval_t intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL -
237 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
238 unsigned int rules_num;
239 unsigned int rules_all;
240 snd_pcm_hw_rule_t *rules;
241} snd_pcm_hw_constraints_t;
242
243static inline snd_mask_t *constrs_mask(snd_pcm_hw_constraints_t *constrs,
244 snd_pcm_hw_param_t var)
245{
246 return &constrs->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK];
247}
248
249static inline snd_interval_t *constrs_interval(snd_pcm_hw_constraints_t *constrs,
250 snd_pcm_hw_param_t var)
251{
252 return &constrs->intervals[var - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL];
253}
254
255typedef struct {
256 unsigned int num;
257 unsigned int den_min, den_max, den_step;
258} ratnum_t;
259
260typedef struct {
261 unsigned int num_min, num_max, num_step;
262 unsigned int den;
263} ratden_t;
264
265typedef struct {
266 int nrats;
267 ratnum_t *rats;
268} snd_pcm_hw_constraint_ratnums_t;
269
270typedef struct {
271 int nrats;
272 ratden_t *rats;
273} snd_pcm_hw_constraint_ratdens_t;
274
275typedef struct {
276 unsigned int count;
277 unsigned int *list;
278 unsigned int mask;
279} snd_pcm_hw_constraint_list_t;
280
281struct _snd_pcm_runtime {
282 /* -- Status -- */
283 snd_pcm_substream_t *trigger_master;
284 snd_timestamp_t trigger_tstamp; /* trigger timestamp */
285 int overrange;
286 snd_pcm_uframes_t avail_max;
287 snd_pcm_uframes_t hw_ptr_base; /* Position at buffer restart */
288 snd_pcm_uframes_t hw_ptr_interrupt; /* Position at interrupt time*/
289
290 /* -- HW params -- */
291 snd_pcm_access_t access; /* access mode */
292 snd_pcm_format_t format; /* SNDRV_PCM_FORMAT_* */
293 snd_pcm_subformat_t subformat; /* subformat */
294 unsigned int rate; /* rate in Hz */
295 unsigned int channels; /* channels */
296 snd_pcm_uframes_t period_size; /* period size */
297 unsigned int periods; /* periods */
298 snd_pcm_uframes_t buffer_size; /* buffer size */
299 unsigned int tick_time; /* tick time */
300 snd_pcm_uframes_t min_align; /* Min alignment for the format */
301 size_t byte_align;
302 unsigned int frame_bits;
303 unsigned int sample_bits;
304 unsigned int info;
305 unsigned int rate_num;
306 unsigned int rate_den;
307
308 /* -- SW params -- */
309 int tstamp_timespec; /* use timeval (0) or timespec (1) */
310 snd_pcm_tstamp_t tstamp_mode; /* mmap timestamp is updated */
311 unsigned int period_step;
312 unsigned int sleep_min; /* min ticks to sleep */
313 snd_pcm_uframes_t xfer_align; /* xfer size need to be a multiple */
314 snd_pcm_uframes_t start_threshold;
315 snd_pcm_uframes_t stop_threshold;
316 snd_pcm_uframes_t silence_threshold; /* Silence filling happens when
317 noise is nearest than this */
318 snd_pcm_uframes_t silence_size; /* Silence filling size */
319 snd_pcm_uframes_t boundary; /* pointers wrap point */
320
321 snd_pcm_uframes_t silence_start; /* starting pointer to silence area */
322 snd_pcm_uframes_t silence_filled; /* size filled with silence */
323
324 snd_pcm_sync_id_t sync; /* hardware synchronization ID */
325
326 /* -- mmap -- */
327 volatile snd_pcm_mmap_status_t *status;
328 volatile snd_pcm_mmap_control_t *control;
329 atomic_t mmap_count;
330
331 /* -- locking / scheduling -- */
332 wait_queue_head_t sleep;
333 struct timer_list tick_timer;
334 struct fasync_struct *fasync;
335
336 /* -- private section -- */
337 void *private_data;
338 void (*private_free)(snd_pcm_runtime_t *runtime);
339
340 /* -- hardware description -- */
341 snd_pcm_hardware_t hw;
342 snd_pcm_hw_constraints_t hw_constraints;
343
344 /* -- interrupt callbacks -- */
345 void (*transfer_ack_begin)(snd_pcm_substream_t *substream);
346 void (*transfer_ack_end)(snd_pcm_substream_t *substream);
347
348 /* -- timer -- */
349 unsigned int timer_resolution; /* timer resolution */
350
351 /* -- DMA -- */
352 unsigned char *dma_area; /* DMA area */
353 dma_addr_t dma_addr; /* physical bus address (not accessible from main CPU) */
354 size_t dma_bytes; /* size of DMA area */
355
356 struct snd_dma_buffer *dma_buffer_p; /* allocated buffer */
357
358#if defined(CONFIG_SND_PCM_OSS) || defined(CONFIG_SND_PCM_OSS_MODULE)
359 /* -- OSS things -- */
360 snd_pcm_oss_runtime_t oss;
361#endif
362};
363
364typedef struct _snd_pcm_group { /* keep linked substreams */
365 spinlock_t lock;
366 struct list_head substreams;
367 int count;
368} snd_pcm_group_t;
369
370struct _snd_pcm_substream {
371 snd_pcm_t *pcm;
372 snd_pcm_str_t *pstr;
373 void *private_data; /* copied from pcm->private_data */
374 int number;
375 char name[32]; /* substream name */
376 int stream; /* stream (direction) */
377 size_t buffer_bytes_max; /* limit ring buffer size */
378 struct snd_dma_buffer dma_buffer;
379 unsigned int dma_buf_id;
380 size_t dma_max;
381 /* -- hardware operations -- */
382 unsigned int open_flag: 1; /* lowlevel device has been opened */
383 snd_pcm_ops_t *ops;
384 /* -- runtime information -- */
385 snd_pcm_runtime_t *runtime;
386 /* -- timer section -- */
387 snd_timer_t *timer; /* timer */
388 unsigned timer_running: 1; /* time is running */
389 spinlock_t timer_lock;
390 /* -- next substream -- */
391 snd_pcm_substream_t *next;
392 /* -- linked substreams -- */
393 struct list_head link_list; /* linked list member */
394 snd_pcm_group_t self_group; /* fake group for non linked substream (with substream lock inside) */
395 snd_pcm_group_t *group; /* pointer to current group */
396 /* -- assigned files -- */
397 snd_pcm_file_t *file;
398 struct file *ffile;
399#if defined(CONFIG_SND_PCM_OSS) || defined(CONFIG_SND_PCM_OSS_MODULE)
400 /* -- OSS things -- */
401 snd_pcm_oss_substream_t oss;
402#endif
403 snd_info_entry_t *proc_root;
404 snd_info_entry_t *proc_info_entry;
405 snd_info_entry_t *proc_hw_params_entry;
406 snd_info_entry_t *proc_sw_params_entry;
407 snd_info_entry_t *proc_status_entry;
408 snd_info_entry_t *proc_prealloc_entry;
409 /* misc flags */
410 unsigned int no_mmap_ctrl: 1;
411};
412
413#if defined(CONFIG_SND_PCM_OSS) || defined(CONFIG_SND_PCM_OSS_MODULE)
414#define SUBSTREAM_BUSY(substream) ((substream)->file != NULL || ((substream)->oss.file != NULL))
415#else
416#define SUBSTREAM_BUSY(substream) ((substream)->file != NULL)
417#endif
418
419
420struct _snd_pcm_str {
421 int stream; /* stream (direction) */
422 snd_pcm_t *pcm;
423 /* -- substreams -- */
424 unsigned int substream_count;
425 unsigned int substream_opened;
426 snd_pcm_substream_t *substream;
427#if defined(CONFIG_SND_PCM_OSS) || defined(CONFIG_SND_PCM_OSS_MODULE)
428 /* -- OSS things -- */
429 snd_pcm_oss_stream_t oss;
430#endif
431 snd_pcm_file_t *files;
432 snd_minor_t *reg;
433 snd_info_entry_t *proc_root;
434 snd_info_entry_t *proc_info_entry;
435#ifdef CONFIG_SND_DEBUG
436 unsigned int xrun_debug; /* 0 = disabled, 1 = verbose, 2 = stacktrace */
437 snd_info_entry_t *proc_xrun_debug_entry;
438#endif
439};
440
441struct _snd_pcm {
442 snd_card_t *card;
443 unsigned int device; /* device number */
444 unsigned int info_flags;
445 unsigned short dev_class;
446 unsigned short dev_subclass;
447 char id[64];
448 char name[80];
449 snd_pcm_str_t streams[2];
450 struct semaphore open_mutex;
451 wait_queue_head_t open_wait;
452 void *private_data;
453 void (*private_free) (snd_pcm_t *pcm);
454#if defined(CONFIG_SND_PCM_OSS) || defined(CONFIG_SND_PCM_OSS_MODULE)
455 snd_pcm_oss_t oss;
456#endif
457};
458
459typedef struct _snd_pcm_notify {
460 int (*n_register) (snd_pcm_t * pcm);
461 int (*n_disconnect) (snd_pcm_t * pcm);
462 int (*n_unregister) (snd_pcm_t * pcm);
463 struct list_head list;
464} snd_pcm_notify_t;
465
466/*
467 * Registering
468 */
469
470extern snd_pcm_t *snd_pcm_devices[];
471extern snd_minor_t snd_pcm_reg[2];
472
473int snd_pcm_new(snd_card_t * card, char *id, int device,
474 int playback_count, int capture_count,
475 snd_pcm_t **rpcm);
476int snd_pcm_new_stream(snd_pcm_t *pcm, int stream, int substream_count);
477
478int snd_pcm_notify(snd_pcm_notify_t *notify, int nfree);
479
480/*
481 * Native I/O
482 */
483
484extern rwlock_t snd_pcm_link_rwlock;
485
486int snd_pcm_info(snd_pcm_substream_t * substream, snd_pcm_info_t *info);
487int snd_pcm_info_user(snd_pcm_substream_t * substream, snd_pcm_info_t __user *info);
488int snd_pcm_status(snd_pcm_substream_t * substream, snd_pcm_status_t *status);
489int snd_pcm_prepare(snd_pcm_substream_t *substream);
490int snd_pcm_start(snd_pcm_substream_t *substream);
491int snd_pcm_stop(snd_pcm_substream_t *substream, int status);
492int snd_pcm_drain_done(snd_pcm_substream_t *substream);
493#ifdef CONFIG_PM
494int snd_pcm_suspend(snd_pcm_substream_t *substream);
495int snd_pcm_suspend_all(snd_pcm_t *pcm);
496#endif
497int snd_pcm_kernel_playback_ioctl(snd_pcm_substream_t *substream, unsigned int cmd, void *arg);
498int snd_pcm_kernel_capture_ioctl(snd_pcm_substream_t *substream, unsigned int cmd, void *arg);
499int snd_pcm_kernel_ioctl(snd_pcm_substream_t *substream, unsigned int cmd, void *arg);
500int snd_pcm_open_substream(snd_pcm_t *pcm, int stream, snd_pcm_substream_t **rsubstream);
501void snd_pcm_release_substream(snd_pcm_substream_t *substream);
502void snd_pcm_vma_notify_data(void *client, void *data);
503int snd_pcm_mmap_data(snd_pcm_substream_t *substream, struct file *file, struct vm_area_struct *area);
504
505#if BITS_PER_LONG >= 64
506
507static inline void div64_32(u_int64_t *n, u_int32_t div, u_int32_t *rem)
508{
509 *rem = *n % div;
510 *n /= div;
511}
512
513#elif defined(i386)
514
515static inline void div64_32(u_int64_t *n, u_int32_t div, u_int32_t *rem)
516{
517 u_int32_t low, high;
518 low = *n & 0xffffffff;
519 high = *n >> 32;
520 if (high) {
521 u_int32_t high1 = high % div;
522 high /= div;
523 asm("divl %2":"=a" (low), "=d" (*rem):"rm" (div), "a" (low), "d" (high1));
524 *n = (u_int64_t)high << 32 | low;
525 } else {
526 *n = low / div;
527 *rem = low % div;
528 }
529}
530#else
531
532static inline void divl(u_int32_t high, u_int32_t low,
533 u_int32_t div,
534 u_int32_t *q, u_int32_t *r)
535{
536 u_int64_t n = (u_int64_t)high << 32 | low;
537 u_int64_t d = (u_int64_t)div << 31;
538 u_int32_t q1 = 0;
539 int c = 32;
540 while (n > 0xffffffffU) {
541 q1 <<= 1;
542 if (n >= d) {
543 n -= d;
544 q1 |= 1;
545 }
546 d >>= 1;
547 c--;
548 }
549 q1 <<= c;
550 if (n) {
551 low = n;
552 *q = q1 | (low / div);
553 *r = low % div;
554 } else {
555 *r = 0;
556 *q = q1;
557 }
558 return;
559}
560
561static inline void div64_32(u_int64_t *n, u_int32_t div, u_int32_t *rem)
562{
563 u_int32_t low, high;
564 low = *n & 0xffffffff;
565 high = *n >> 32;
566 if (high) {
567 u_int32_t high1 = high % div;
568 u_int32_t low1 = low;
569 high /= div;
570 divl(high1, low1, div, &low, rem);
571 *n = (u_int64_t)high << 32 | low;
572 } else {
573 *n = low / div;
574 *rem = low % div;
575 }
576}
577#endif
578
579/*
580 * PCM library
581 */
582
583static inline int snd_pcm_stream_linked(snd_pcm_substream_t *substream)
584{
585 return substream->group != &substream->self_group;
586}
587
588static inline void snd_pcm_stream_lock(snd_pcm_substream_t *substream)
589{
590 read_lock(&snd_pcm_link_rwlock);
591 spin_lock(&substream->self_group.lock);
592}
593
594static inline void snd_pcm_stream_unlock(snd_pcm_substream_t *substream)
595{
596 spin_unlock(&substream->self_group.lock);
597 read_unlock(&snd_pcm_link_rwlock);
598}
599
600static inline void snd_pcm_stream_lock_irq(snd_pcm_substream_t *substream)
601{
602 read_lock_irq(&snd_pcm_link_rwlock);
603 spin_lock(&substream->self_group.lock);
604}
605
606static inline void snd_pcm_stream_unlock_irq(snd_pcm_substream_t *substream)
607{
608 spin_unlock(&substream->self_group.lock);
609 read_unlock_irq(&snd_pcm_link_rwlock);
610}
611
612#define snd_pcm_stream_lock_irqsave(substream, flags) \
613do { \
614 read_lock_irqsave(&snd_pcm_link_rwlock, (flags)); \
615 spin_lock(&substream->self_group.lock); \
616} while (0)
617
618#define snd_pcm_stream_unlock_irqrestore(substream, flags) \
619do { \
620 spin_unlock(&substream->self_group.lock); \
621 read_unlock_irqrestore(&snd_pcm_link_rwlock, (flags)); \
622} while (0)
623
624#define snd_pcm_group_for_each(pos, substream) \
625 list_for_each(pos, &substream->group->substreams)
626
627#define snd_pcm_group_substream_entry(pos) \
628 list_entry(pos, snd_pcm_substream_t, link_list)
629
630static inline int snd_pcm_running(snd_pcm_substream_t *substream)
631{
632 return (substream->runtime->status->state == SNDRV_PCM_STATE_RUNNING ||
633 (substream->runtime->status->state == SNDRV_PCM_STATE_DRAINING &&
634 substream->stream == SNDRV_PCM_STREAM_PLAYBACK));
635}
636
637static inline ssize_t bytes_to_samples(snd_pcm_runtime_t *runtime, ssize_t size)
638{
639 return size * 8 / runtime->sample_bits;
640}
641
642static inline snd_pcm_sframes_t bytes_to_frames(snd_pcm_runtime_t *runtime, ssize_t size)
643{
644 return size * 8 / runtime->frame_bits;
645}
646
647static inline ssize_t samples_to_bytes(snd_pcm_runtime_t *runtime, ssize_t size)
648{
649 return size * runtime->sample_bits / 8;
650}
651
652static inline ssize_t frames_to_bytes(snd_pcm_runtime_t *runtime, snd_pcm_sframes_t size)
653{
654 return size * runtime->frame_bits / 8;
655}
656
657static inline int frame_aligned(snd_pcm_runtime_t *runtime, ssize_t bytes)
658{
659 return bytes % runtime->byte_align == 0;
660}
661
662static inline size_t snd_pcm_lib_buffer_bytes(snd_pcm_substream_t *substream)
663{
664 snd_pcm_runtime_t *runtime = substream->runtime;
665 return frames_to_bytes(runtime, runtime->buffer_size);
666}
667
668static inline size_t snd_pcm_lib_period_bytes(snd_pcm_substream_t *substream)
669{
670 snd_pcm_runtime_t *runtime = substream->runtime;
671 return frames_to_bytes(runtime, runtime->period_size);
672}
673
674/*
675 * result is: 0 ... (boundary - 1)
676 */
677static inline snd_pcm_uframes_t snd_pcm_playback_avail(snd_pcm_runtime_t *runtime)
678{
679 snd_pcm_sframes_t avail = runtime->status->hw_ptr + runtime->buffer_size - runtime->control->appl_ptr;
680 if (avail < 0)
681 avail += runtime->boundary;
682 else if ((snd_pcm_uframes_t) avail >= runtime->boundary)
683 avail -= runtime->boundary;
684 return avail;
685}
686
687/*
688 * result is: 0 ... (boundary - 1)
689 */
690static inline snd_pcm_uframes_t snd_pcm_capture_avail(snd_pcm_runtime_t *runtime)
691{
692 snd_pcm_sframes_t avail = runtime->status->hw_ptr - runtime->control->appl_ptr;
693 if (avail < 0)
694 avail += runtime->boundary;
695 return avail;
696}
697
698static inline snd_pcm_sframes_t snd_pcm_playback_hw_avail(snd_pcm_runtime_t *runtime)
699{
700 return runtime->buffer_size - snd_pcm_playback_avail(runtime);
701}
702
703static inline snd_pcm_sframes_t snd_pcm_capture_hw_avail(snd_pcm_runtime_t *runtime)
704{
705 return runtime->buffer_size - snd_pcm_capture_avail(runtime);
706}
707
708/**
709 * snd_pcm_playback_ready - check whether the playback buffer is available
710 * @substream: the pcm substream instance
711 *
712 * Checks whether enough free space is available on the playback buffer.
713 *
714 * Returns non-zero if available, or zero if not.
715 */
716static inline int snd_pcm_playback_ready(snd_pcm_substream_t *substream)
717{
718 snd_pcm_runtime_t *runtime = substream->runtime;
719 return snd_pcm_playback_avail(runtime) >= runtime->control->avail_min;
720}
721
722/**
723 * snd_pcm_capture_ready - check whether the capture buffer is available
724 * @substream: the pcm substream instance
725 *
726 * Checks whether enough capture data is available on the capture buffer.
727 *
728 * Returns non-zero if available, or zero if not.
729 */
730static inline int snd_pcm_capture_ready(snd_pcm_substream_t *substream)
731{
732 snd_pcm_runtime_t *runtime = substream->runtime;
733 return snd_pcm_capture_avail(runtime) >= runtime->control->avail_min;
734}
735
736/**
737 * snd_pcm_playback_data - check whether any data exists on the playback buffer
738 * @substream: the pcm substream instance
739 *
740 * Checks whether any data exists on the playback buffer. If stop_threshold
741 * is bigger or equal to boundary, then this function returns always non-zero.
742 *
743 * Returns non-zero if exists, or zero if not.
744 */
745static inline int snd_pcm_playback_data(snd_pcm_substream_t *substream)
746{
747 snd_pcm_runtime_t *runtime = substream->runtime;
748
749 if (runtime->stop_threshold >= runtime->boundary)
750 return 1;
751 return snd_pcm_playback_avail(runtime) < runtime->buffer_size;
752}
753
754/**
755 * snd_pcm_playback_empty - check whether the playback buffer is empty
756 * @substream: the pcm substream instance
757 *
758 * Checks whether the playback buffer is empty.
759 *
760 * Returns non-zero if empty, or zero if not.
761 */
762static inline int snd_pcm_playback_empty(snd_pcm_substream_t *substream)
763{
764 snd_pcm_runtime_t *runtime = substream->runtime;
765 return snd_pcm_playback_avail(runtime) >= runtime->buffer_size;
766}
767
768/**
769 * snd_pcm_capture_empty - check whether the capture buffer is empty
770 * @substream: the pcm substream instance
771 *
772 * Checks whether the capture buffer is empty.
773 *
774 * Returns non-zero if empty, or zero if not.
775 */
776static inline int snd_pcm_capture_empty(snd_pcm_substream_t *substream)
777{
778 snd_pcm_runtime_t *runtime = substream->runtime;
779 return snd_pcm_capture_avail(runtime) == 0;
780}
781
782static inline void snd_pcm_trigger_done(snd_pcm_substream_t *substream,
783 snd_pcm_substream_t *master)
784{
785 substream->runtime->trigger_master = master;
786}
787
788static inline int hw_is_mask(int var)
789{
790 return var >= SNDRV_PCM_HW_PARAM_FIRST_MASK &&
791 var <= SNDRV_PCM_HW_PARAM_LAST_MASK;
792}
793
794static inline int hw_is_interval(int var)
795{
796 return var >= SNDRV_PCM_HW_PARAM_FIRST_INTERVAL &&
797 var <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL;
798}
799
800static inline snd_mask_t *hw_param_mask(snd_pcm_hw_params_t *params,
801 snd_pcm_hw_param_t var)
802{
803 return &params->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK];
804}
805
806static inline snd_interval_t *hw_param_interval(snd_pcm_hw_params_t *params,
807 snd_pcm_hw_param_t var)
808{
809 return &params->intervals[var - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL];
810}
811
812static inline const snd_mask_t *hw_param_mask_c(const snd_pcm_hw_params_t *params,
813 snd_pcm_hw_param_t var)
814{
815 return (const snd_mask_t *)hw_param_mask((snd_pcm_hw_params_t*) params, var);
816}
817
818static inline const snd_interval_t *hw_param_interval_c(const snd_pcm_hw_params_t *params,
819 snd_pcm_hw_param_t var)
820{
821 return (const snd_interval_t *)hw_param_interval((snd_pcm_hw_params_t*) params, var);
822}
823
824#define params_access(p) snd_mask_min(hw_param_mask((p), SNDRV_PCM_HW_PARAM_ACCESS))
825#define params_format(p) snd_mask_min(hw_param_mask((p), SNDRV_PCM_HW_PARAM_FORMAT))
826#define params_subformat(p) snd_mask_min(hw_param_mask((p), SNDRV_PCM_HW_PARAM_SUBFORMAT))
827#define params_channels(p) hw_param_interval((p), SNDRV_PCM_HW_PARAM_CHANNELS)->min
828#define params_rate(p) hw_param_interval((p), SNDRV_PCM_HW_PARAM_RATE)->min
829#define params_period_size(p) hw_param_interval((p), SNDRV_PCM_HW_PARAM_PERIOD_SIZE)->min
830#define params_period_bytes(p) ((params_period_size(p)*snd_pcm_format_physical_width(params_format(p))*params_channels(p))/8)
831#define params_periods(p) hw_param_interval((p), SNDRV_PCM_HW_PARAM_PERIODS)->min
832#define params_buffer_size(p) hw_param_interval((p), SNDRV_PCM_HW_PARAM_BUFFER_SIZE)->min
833#define params_buffer_bytes(p) hw_param_interval((p), SNDRV_PCM_HW_PARAM_BUFFER_BYTES)->min
834#define params_tick_time(p) hw_param_interval((p), SNDRV_PCM_HW_PARAM_TICK_TIME)->min
835
836
837int snd_interval_refine(snd_interval_t *i, const snd_interval_t *v);
838void snd_interval_mul(const snd_interval_t *a, const snd_interval_t *b, snd_interval_t *c);
839void snd_interval_div(const snd_interval_t *a, const snd_interval_t *b, snd_interval_t *c);
840void snd_interval_muldivk(const snd_interval_t *a, const snd_interval_t *b,
841 unsigned int k, snd_interval_t *c);
842void snd_interval_mulkdiv(const snd_interval_t *a, unsigned int k,
843 const snd_interval_t *b, snd_interval_t *c);
844int snd_interval_list(snd_interval_t *i, unsigned int count, unsigned int *list, unsigned int mask);
845int snd_interval_ratnum(snd_interval_t *i,
846 unsigned int rats_count, ratnum_t *rats,
847 unsigned int *nump, unsigned int *denp);
848
849void _snd_pcm_hw_params_any(snd_pcm_hw_params_t *params);
850void _snd_pcm_hw_param_setempty(snd_pcm_hw_params_t *params, snd_pcm_hw_param_t var);
851int snd_pcm_hw_param_min(snd_pcm_substream_t *substream,
852 snd_pcm_hw_params_t *params,
853 snd_pcm_hw_param_t var,
854 unsigned int val, int *dir);
855int snd_pcm_hw_param_max(snd_pcm_substream_t *substream,
856 snd_pcm_hw_params_t *params,
857 snd_pcm_hw_param_t var,
858 unsigned int val, int *dir);
859int snd_pcm_hw_param_setinteger(snd_pcm_substream_t *substream,
860 snd_pcm_hw_params_t *params,
861 snd_pcm_hw_param_t var);
862int snd_pcm_hw_param_first(snd_pcm_substream_t *substream,
863 snd_pcm_hw_params_t *params,
864 snd_pcm_hw_param_t var, int *dir);
865int snd_pcm_hw_param_last(snd_pcm_substream_t *substream,
866 snd_pcm_hw_params_t *params,
867 snd_pcm_hw_param_t var, int *dir);
868int snd_pcm_hw_param_near(snd_pcm_substream_t *substream,
869 snd_pcm_hw_params_t *params,
870 snd_pcm_hw_param_t var,
871 unsigned int val, int *dir);
872int snd_pcm_hw_param_set(snd_pcm_substream_t *pcm,
873 snd_pcm_hw_params_t *params,
874 snd_pcm_hw_param_t var,
875 unsigned int val, int dir);
876int snd_pcm_hw_params_choose(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *params);
877
878int snd_pcm_hw_refine(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *params);
879int snd_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *params);
880
881int snd_pcm_hw_constraints_init(snd_pcm_substream_t *substream);
882int snd_pcm_hw_constraints_complete(snd_pcm_substream_t *substream);
883
884int snd_pcm_hw_constraint_mask(snd_pcm_runtime_t *runtime, snd_pcm_hw_param_t var,
885 u_int32_t mask);
886int snd_pcm_hw_constraint_mask64(snd_pcm_runtime_t *runtime, snd_pcm_hw_param_t var,
887 u_int64_t mask);
888int snd_pcm_hw_constraint_minmax(snd_pcm_runtime_t *runtime, snd_pcm_hw_param_t var,
889 unsigned int min, unsigned int max);
890int snd_pcm_hw_constraint_integer(snd_pcm_runtime_t *runtime, snd_pcm_hw_param_t var);
891int snd_pcm_hw_constraint_list(snd_pcm_runtime_t *runtime,
892 unsigned int cond,
893 snd_pcm_hw_param_t var,
894 snd_pcm_hw_constraint_list_t *l);
895int snd_pcm_hw_constraint_ratnums(snd_pcm_runtime_t *runtime,
896 unsigned int cond,
897 snd_pcm_hw_param_t var,
898 snd_pcm_hw_constraint_ratnums_t *r);
899int snd_pcm_hw_constraint_ratdens(snd_pcm_runtime_t *runtime,
900 unsigned int cond,
901 snd_pcm_hw_param_t var,
902 snd_pcm_hw_constraint_ratdens_t *r);
903int snd_pcm_hw_constraint_msbits(snd_pcm_runtime_t *runtime,
904 unsigned int cond,
905 unsigned int width,
906 unsigned int msbits);
907int snd_pcm_hw_constraint_step(snd_pcm_runtime_t *runtime,
908 unsigned int cond,
909 snd_pcm_hw_param_t var,
910 unsigned long step);
911int snd_pcm_hw_constraint_pow2(snd_pcm_runtime_t *runtime,
912 unsigned int cond,
913 snd_pcm_hw_param_t var);
914int snd_pcm_hw_rule_add(snd_pcm_runtime_t *runtime,
915 unsigned int cond,
916 int var,
917 snd_pcm_hw_rule_func_t func, void *private,
918 int dep, ...);
919
920int snd_pcm_format_signed(snd_pcm_format_t format);
921int snd_pcm_format_unsigned(snd_pcm_format_t format);
922int snd_pcm_format_linear(snd_pcm_format_t format);
923int snd_pcm_format_little_endian(snd_pcm_format_t format);
924int snd_pcm_format_big_endian(snd_pcm_format_t format);
925int snd_pcm_format_width(snd_pcm_format_t format); /* in bits */
926int snd_pcm_format_physical_width(snd_pcm_format_t format); /* in bits */
927const unsigned char *snd_pcm_format_silence_64(snd_pcm_format_t format);
928int snd_pcm_format_set_silence(snd_pcm_format_t format, void *buf, unsigned int frames);
929snd_pcm_format_t snd_pcm_build_linear_format(int width, int unsignd, int big_endian);
930const char *snd_pcm_format_name(snd_pcm_format_t format);
931
932void snd_pcm_set_ops(snd_pcm_t * pcm, int direction, snd_pcm_ops_t *ops);
933void snd_pcm_set_sync(snd_pcm_substream_t * substream);
934int snd_pcm_lib_interleave_len(snd_pcm_substream_t *substream);
935int snd_pcm_lib_ioctl(snd_pcm_substream_t *substream,
936 unsigned int cmd, void *arg);
937int snd_pcm_update_hw_ptr(snd_pcm_substream_t *substream);
938int snd_pcm_playback_xrun_check(snd_pcm_substream_t *substream);
939int snd_pcm_capture_xrun_check(snd_pcm_substream_t *substream);
940int snd_pcm_playback_xrun_asap(snd_pcm_substream_t *substream);
941int snd_pcm_capture_xrun_asap(snd_pcm_substream_t *substream);
942void snd_pcm_playback_silence(snd_pcm_substream_t *substream, snd_pcm_uframes_t new_hw_ptr);
943void snd_pcm_tick_prepare(snd_pcm_substream_t *substream);
944void snd_pcm_tick_set(snd_pcm_substream_t *substream, unsigned long ticks);
945void snd_pcm_tick_elapsed(snd_pcm_substream_t *substream);
946void snd_pcm_period_elapsed(snd_pcm_substream_t *substream);
947snd_pcm_sframes_t snd_pcm_lib_write(snd_pcm_substream_t *substream,
948 const void __user *buf,
949 snd_pcm_uframes_t frames);
950snd_pcm_sframes_t snd_pcm_lib_read(snd_pcm_substream_t *substream,
951 void __user *buf, snd_pcm_uframes_t frames);
952snd_pcm_sframes_t snd_pcm_lib_writev(snd_pcm_substream_t *substream,
953 void __user **bufs, snd_pcm_uframes_t frames);
954snd_pcm_sframes_t snd_pcm_lib_readv(snd_pcm_substream_t *substream,
955 void __user **bufs, snd_pcm_uframes_t frames);
956
957int snd_pcm_limit_hw_rates(snd_pcm_runtime_t *runtime);
958
959static inline void snd_pcm_set_runtime_buffer(snd_pcm_substream_t *substream,
960 struct snd_dma_buffer *bufp)
961{
962 snd_pcm_runtime_t *runtime = substream->runtime;
963 if (bufp) {
964 runtime->dma_buffer_p = bufp;
965 runtime->dma_area = bufp->area;
966 runtime->dma_addr = bufp->addr;
967 runtime->dma_bytes = bufp->bytes;
968 } else {
969 runtime->dma_buffer_p = NULL;
970 runtime->dma_area = NULL;
971 runtime->dma_addr = 0;
972 runtime->dma_bytes = 0;
973 }
974}
975
976/*
977 * Timer interface
978 */
979
980void snd_pcm_timer_resolution_change(snd_pcm_substream_t *substream);
981void snd_pcm_timer_init(snd_pcm_substream_t * substream);
982void snd_pcm_timer_done(snd_pcm_substream_t * substream);
983
984/*
985 * Memory
986 */
987
988int snd_pcm_lib_preallocate_free(snd_pcm_substream_t *substream);
989int snd_pcm_lib_preallocate_free_for_all(snd_pcm_t *pcm);
990int snd_pcm_lib_preallocate_pages(snd_pcm_substream_t *substream,
991 int type, struct device *data,
992 size_t size, size_t max);
993int snd_pcm_lib_preallocate_pages_for_all(snd_pcm_t *pcm,
994 int type, void *data,
995 size_t size, size_t max);
996int snd_pcm_lib_malloc_pages(snd_pcm_substream_t *substream, size_t size);
997int snd_pcm_lib_free_pages(snd_pcm_substream_t *substream);
998
999#define snd_pcm_substream_sgbuf(substream) ((substream)->runtime->dma_buffer_p->private_data)
1000#define snd_pcm_sgbuf_pages(size) snd_sgbuf_aligned_pages(size)
1001#define snd_pcm_sgbuf_get_addr(sgbuf,ofs) snd_sgbuf_get_addr(sgbuf,ofs)
1002struct page *snd_pcm_sgbuf_ops_page(snd_pcm_substream_t *substream, unsigned long offset);
1003
1004/* handle mmap counter - PCM mmap callback should handle this counter properly */
1005static inline void snd_pcm_mmap_data_open(struct vm_area_struct *area)
1006{
1007 snd_pcm_substream_t *substream = (snd_pcm_substream_t *)area->vm_private_data;
1008 atomic_inc(&substream->runtime->mmap_count);
1009}
1010
1011static inline void snd_pcm_mmap_data_close(struct vm_area_struct *area)
1012{
1013 snd_pcm_substream_t *substream = (snd_pcm_substream_t *)area->vm_private_data;
1014 atomic_dec(&substream->runtime->mmap_count);
1015}
1016
1017/* mmap for io-memory area */
1018#if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_ALPHA)
1019#define SNDRV_PCM_INFO_MMAP_IOMEM SNDRV_PCM_INFO_MMAP
1020int snd_pcm_lib_mmap_iomem(snd_pcm_substream_t *substream, struct vm_area_struct *area);
1021#else
1022#define SNDRV_PCM_INFO_MMAP_IOMEM 0
1023#define snd_pcm_lib_mmap_iomem NULL
1024#endif
1025
1026static inline void snd_pcm_limit_isa_dma_size(int dma, size_t *max)
1027{
1028 *max = dma < 4 ? 64 * 1024 : 128 * 1024;
1029}
1030
1031/*
1032 * Misc
1033 */
1034
1035#define SNDRV_PCM_DEFAULT_CON_SPDIF (IEC958_AES0_CON_EMPHASIS_NONE|\
1036 (IEC958_AES1_CON_ORIGINAL<<8)|\
1037 (IEC958_AES1_CON_PCM_CODER<<8)|\
1038 (IEC958_AES3_CON_FS_48000<<24))
1039
1040#endif /* __SOUND_PCM_H */
diff --git a/include/sound/pcm_oss.h b/include/sound/pcm_oss.h
new file mode 100644
index 000000000000..518728536bc6
--- /dev/null
+++ b/include/sound/pcm_oss.h
@@ -0,0 +1,87 @@
1#ifndef __SOUND_PCM_OSS_H
2#define __SOUND_PCM_OSS_H
3
4/*
5 * Digital Audio (PCM) - OSS compatibility abstract layer
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25typedef struct _snd_pcm_plugin snd_pcm_plugin_t;
26typedef struct _snd_pcm_oss_setup snd_pcm_oss_setup_t;
27
28struct _snd_pcm_oss_setup {
29 char *task_name;
30 unsigned int disable:1,
31 direct:1,
32 block:1,
33 nonblock:1,
34 partialfrag:1,
35 nosilence:1;
36 unsigned int periods;
37 unsigned int period_size;
38 snd_pcm_oss_setup_t *next;
39};
40
41typedef struct _snd_pcm_oss_runtime {
42 unsigned params: 1, /* format/parameter change */
43 prepare: 1, /* need to prepare the operation */
44 trigger: 1, /* trigger flag */
45 sync_trigger: 1; /* sync trigger flag */
46 int rate; /* requested rate */
47 int format; /* requested OSS format */
48 unsigned int channels; /* requested channels */
49 unsigned int fragshift;
50 unsigned int maxfrags;
51 unsigned int subdivision; /* requested subdivision */
52 size_t period_bytes; /* requested period size */
53 size_t period_frames; /* period frames for poll */
54 size_t period_ptr; /* actual write pointer to period */
55 unsigned int periods;
56 size_t buffer_bytes; /* requested buffer size */
57 size_t bytes; /* total # bytes processed */
58 size_t mmap_bytes;
59 char *buffer; /* vmallocated period */
60 size_t buffer_used; /* used length from period buffer */
61 snd_pcm_plugin_t *plugin_first;
62 snd_pcm_plugin_t *plugin_last;
63 unsigned int prev_hw_ptr_interrupt;
64} snd_pcm_oss_runtime_t;
65
66typedef struct _snd_pcm_oss_file {
67 snd_pcm_substream_t *streams[2];
68} snd_pcm_oss_file_t;
69
70typedef struct _snd_pcm_oss_substream {
71 unsigned oss: 1; /* oss mode */
72 snd_pcm_oss_setup_t *setup; /* active setup */
73 snd_pcm_oss_file_t *file;
74} snd_pcm_oss_substream_t;
75
76typedef struct _snd_pcm_oss_stream {
77 snd_pcm_oss_setup_t *setup_list; /* setup list */
78 struct semaphore setup_mutex;
79 snd_info_entry_t *proc_entry;
80} snd_pcm_oss_stream_t;
81
82typedef struct _snd_pcm_oss {
83 int reg;
84 unsigned int reg_mask;
85} snd_pcm_oss_t;
86
87#endif /* __SOUND_PCM_OSS_H */
diff --git a/include/sound/pcm_params.h b/include/sound/pcm_params.h
new file mode 100644
index 000000000000..60b0e92e26f3
--- /dev/null
+++ b/include/sound/pcm_params.h
@@ -0,0 +1,366 @@
1#ifndef __SOUND_PCM_PARAMS_H
2#define __SOUND_PCM_PARAMS_H
3
4/*
5 * PCM params helpers
6 * Copyright (c) by Abramo Bagnara <abramo@alsa-project.org>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25extern int snd_pcm_hw_param_mask(snd_pcm_substream_t *pcm, snd_pcm_hw_params_t *params,
26 snd_pcm_hw_param_t var, const snd_mask_t *val);
27extern unsigned int snd_pcm_hw_param_value_min(const snd_pcm_hw_params_t *params,
28 snd_pcm_hw_param_t var, int *dir);
29extern unsigned int snd_pcm_hw_param_value_max(const snd_pcm_hw_params_t *params,
30 snd_pcm_hw_param_t var, int *dir);
31extern int _snd_pcm_hw_param_min(snd_pcm_hw_params_t *params,
32 snd_pcm_hw_param_t var, unsigned int val, int dir);
33extern int _snd_pcm_hw_param_setinteger(snd_pcm_hw_params_t *params,
34 snd_pcm_hw_param_t var);
35extern int _snd_pcm_hw_param_set(snd_pcm_hw_params_t *params,
36 snd_pcm_hw_param_t var, unsigned int val, int dir);
37
38/* To share the same code we have alsa-lib */
39#define INLINE static inline
40#define assert(a) (void)(a)
41
42#define SNDRV_MASK_BITS 64 /* we use so far 64bits only */
43#define SNDRV_MASK_SIZE (SNDRV_MASK_BITS / 32)
44#define MASK_OFS(i) ((i) >> 5)
45#define MASK_BIT(i) (1U << ((i) & 31))
46
47INLINE unsigned int ld2(u_int32_t v)
48{
49 unsigned r = 0;
50
51 if (v >= 0x10000) {
52 v >>= 16;
53 r += 16;
54 }
55 if (v >= 0x100) {
56 v >>= 8;
57 r += 8;
58 }
59 if (v >= 0x10) {
60 v >>= 4;
61 r += 4;
62 }
63 if (v >= 4) {
64 v >>= 2;
65 r += 2;
66 }
67 if (v >= 2)
68 r++;
69 return r;
70}
71
72INLINE size_t snd_mask_sizeof(void)
73{
74 return sizeof(snd_mask_t);
75}
76
77INLINE void snd_mask_none(snd_mask_t *mask)
78{
79 memset(mask, 0, sizeof(*mask));
80}
81
82INLINE void snd_mask_any(snd_mask_t *mask)
83{
84 memset(mask, 0xff, SNDRV_MASK_SIZE * sizeof(u_int32_t));
85}
86
87INLINE int snd_mask_empty(const snd_mask_t *mask)
88{
89 int i;
90 for (i = 0; i < SNDRV_MASK_SIZE; i++)
91 if (mask->bits[i])
92 return 0;
93 return 1;
94}
95
96INLINE unsigned int snd_mask_min(const snd_mask_t *mask)
97{
98 int i;
99 assert(!snd_mask_empty(mask));
100 for (i = 0; i < SNDRV_MASK_SIZE; i++) {
101 if (mask->bits[i])
102 return ffs(mask->bits[i]) - 1 + (i << 5);
103 }
104 return 0;
105}
106
107INLINE unsigned int snd_mask_max(const snd_mask_t *mask)
108{
109 int i;
110 assert(!snd_mask_empty(mask));
111 for (i = SNDRV_MASK_SIZE - 1; i >= 0; i--) {
112 if (mask->bits[i])
113 return ld2(mask->bits[i]) + (i << 5);
114 }
115 return 0;
116}
117
118INLINE void snd_mask_set(snd_mask_t *mask, unsigned int val)
119{
120 assert(val <= SNDRV_MASK_BITS);
121 mask->bits[MASK_OFS(val)] |= MASK_BIT(val);
122}
123
124INLINE void snd_mask_reset(snd_mask_t *mask, unsigned int val)
125{
126 assert(val <= SNDRV_MASK_BITS);
127 mask->bits[MASK_OFS(val)] &= ~MASK_BIT(val);
128}
129
130INLINE void snd_mask_set_range(snd_mask_t *mask, unsigned int from, unsigned int to)
131{
132 unsigned int i;
133 assert(to <= SNDRV_MASK_BITS && from <= to);
134 for (i = from; i <= to; i++)
135 mask->bits[MASK_OFS(i)] |= MASK_BIT(i);
136}
137
138INLINE void snd_mask_reset_range(snd_mask_t *mask, unsigned int from, unsigned int to)
139{
140 unsigned int i;
141 assert(to <= SNDRV_MASK_BITS && from <= to);
142 for (i = from; i <= to; i++)
143 mask->bits[MASK_OFS(i)] &= ~MASK_BIT(i);
144}
145
146INLINE void snd_mask_leave(snd_mask_t *mask, unsigned int val)
147{
148 unsigned int v;
149 assert(val <= SNDRV_MASK_BITS);
150 v = mask->bits[MASK_OFS(val)] & MASK_BIT(val);
151 snd_mask_none(mask);
152 mask->bits[MASK_OFS(val)] = v;
153}
154
155INLINE void snd_mask_intersect(snd_mask_t *mask, const snd_mask_t *v)
156{
157 int i;
158 for (i = 0; i < SNDRV_MASK_SIZE; i++)
159 mask->bits[i] &= v->bits[i];
160}
161
162INLINE int snd_mask_eq(const snd_mask_t *mask, const snd_mask_t *v)
163{
164 return ! memcmp(mask, v, SNDRV_MASK_SIZE * sizeof(u_int32_t));
165}
166
167INLINE void snd_mask_copy(snd_mask_t *mask, const snd_mask_t *v)
168{
169 *mask = *v;
170}
171
172INLINE int snd_mask_test(const snd_mask_t *mask, unsigned int val)
173{
174 assert(val <= SNDRV_MASK_BITS);
175 return mask->bits[MASK_OFS(val)] & MASK_BIT(val);
176}
177
178INLINE int snd_mask_single(const snd_mask_t *mask)
179{
180 int i, c = 0;
181 assert(!snd_mask_empty(mask));
182 for (i = 0; i < SNDRV_MASK_SIZE; i++) {
183 if (! mask->bits[i])
184 continue;
185 if (mask->bits[i] & (mask->bits[i] - 1))
186 return 0;
187 if (c)
188 return 0;
189 c++;
190 }
191 return 1;
192}
193
194INLINE int snd_mask_refine(snd_mask_t *mask, const snd_mask_t *v)
195{
196 snd_mask_t old;
197 assert(!snd_mask_empty(mask));
198 snd_mask_copy(&old, mask);
199 snd_mask_intersect(mask, v);
200 if (snd_mask_empty(mask))
201 return -EINVAL;
202 return !snd_mask_eq(mask, &old);
203}
204
205INLINE int snd_mask_refine_first(snd_mask_t *mask)
206{
207 assert(!snd_mask_empty(mask));
208 if (snd_mask_single(mask))
209 return 0;
210 snd_mask_leave(mask, snd_mask_min(mask));
211 return 1;
212}
213
214INLINE int snd_mask_refine_last(snd_mask_t *mask)
215{
216 assert(!snd_mask_empty(mask));
217 if (snd_mask_single(mask))
218 return 0;
219 snd_mask_leave(mask, snd_mask_max(mask));
220 return 1;
221}
222
223INLINE int snd_mask_refine_min(snd_mask_t *mask, unsigned int val)
224{
225 assert(!snd_mask_empty(mask));
226 if (snd_mask_min(mask) >= val)
227 return 0;
228 snd_mask_reset_range(mask, 0, val - 1);
229 if (snd_mask_empty(mask))
230 return -EINVAL;
231 return 1;
232}
233
234INLINE int snd_mask_refine_max(snd_mask_t *mask, unsigned int val)
235{
236 assert(!snd_mask_empty(mask));
237 if (snd_mask_max(mask) <= val)
238 return 0;
239 snd_mask_reset_range(mask, val + 1, SNDRV_MASK_BITS);
240 if (snd_mask_empty(mask))
241 return -EINVAL;
242 return 1;
243}
244
245INLINE int snd_mask_refine_set(snd_mask_t *mask, unsigned int val)
246{
247 int changed;
248 assert(!snd_mask_empty(mask));
249 changed = !snd_mask_single(mask);
250 snd_mask_leave(mask, val);
251 if (snd_mask_empty(mask))
252 return -EINVAL;
253 return changed;
254}
255
256INLINE int snd_mask_value(const snd_mask_t *mask)
257{
258 assert(!snd_mask_empty(mask));
259 return snd_mask_min(mask);
260}
261
262INLINE void snd_interval_any(snd_interval_t *i)
263{
264 i->min = 0;
265 i->openmin = 0;
266 i->max = UINT_MAX;
267 i->openmax = 0;
268 i->integer = 0;
269 i->empty = 0;
270}
271
272INLINE void snd_interval_none(snd_interval_t *i)
273{
274 i->empty = 1;
275}
276
277INLINE int snd_interval_checkempty(const snd_interval_t *i)
278{
279 return (i->min > i->max ||
280 (i->min == i->max && (i->openmin || i->openmax)));
281}
282
283INLINE int snd_interval_empty(const snd_interval_t *i)
284{
285 return i->empty;
286}
287
288INLINE int snd_interval_single(const snd_interval_t *i)
289{
290 assert(!snd_interval_empty(i));
291 return (i->min == i->max ||
292 (i->min + 1 == i->max && i->openmax));
293}
294
295INLINE int snd_interval_value(const snd_interval_t *i)
296{
297 assert(snd_interval_single(i));
298 return i->min;
299}
300
301INLINE int snd_interval_min(const snd_interval_t *i)
302{
303 assert(!snd_interval_empty(i));
304 return i->min;
305}
306
307INLINE int snd_interval_max(const snd_interval_t *i)
308{
309 unsigned int v;
310 assert(!snd_interval_empty(i));
311 v = i->max;
312 if (i->openmax)
313 v--;
314 return v;
315}
316
317INLINE int snd_interval_test(const snd_interval_t *i, unsigned int val)
318{
319 return !((i->min > val || (i->min == val && i->openmin) ||
320 i->max < val || (i->max == val && i->openmax)));
321}
322
323INLINE void snd_interval_copy(snd_interval_t *d, const snd_interval_t *s)
324{
325 *d = *s;
326}
327
328INLINE int snd_interval_setinteger(snd_interval_t *i)
329{
330 if (i->integer)
331 return 0;
332 if (i->openmin && i->openmax && i->min == i->max)
333 return -EINVAL;
334 i->integer = 1;
335 return 1;
336}
337
338INLINE int snd_interval_eq(const snd_interval_t *i1, const snd_interval_t *i2)
339{
340 if (i1->empty)
341 return i2->empty;
342 if (i2->empty)
343 return i1->empty;
344 return i1->min == i2->min && i1->openmin == i2->openmin &&
345 i1->max == i2->max && i1->openmax == i2->openmax;
346}
347
348static inline unsigned int add(unsigned int a, unsigned int b)
349{
350 if (a >= UINT_MAX - b)
351 return UINT_MAX;
352 return a + b;
353}
354
355static inline unsigned int sub(unsigned int a, unsigned int b)
356{
357 if (a > b)
358 return a - b;
359 return 0;
360}
361
362#undef INLINE
363#undef assert
364
365#endif /* __SOUND_PCM_PARAMS_H */
366
diff --git a/include/sound/rawmidi.h b/include/sound/rawmidi.h
new file mode 100644
index 000000000000..3f9db510dee3
--- /dev/null
+++ b/include/sound/rawmidi.h
@@ -0,0 +1,180 @@
1#ifndef __SOUND_RAWMIDI_H
2#define __SOUND_RAWMIDI_H
3
4/*
5 * Abstract layer for MIDI v1.0 stream
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <sound/asound.h>
26#include <linux/interrupt.h>
27#include <linux/spinlock.h>
28#include <linux/wait.h>
29#include <asm/semaphore.h>
30
31#if defined(CONFIG_SND_SEQUENCER) || defined(CONFIG_SND_SEQUENCER_MODULE)
32#include "seq_device.h"
33#endif
34
35/*
36 * Raw MIDI interface
37 */
38
39typedef enum sndrv_rawmidi_stream snd_rawmidi_stream_t;
40typedef struct sndrv_rawmidi_info snd_rawmidi_info_t;
41typedef struct sndrv_rawmidi_params snd_rawmidi_params_t;
42typedef struct sndrv_rawmidi_status snd_rawmidi_status_t;
43
44#define SNDRV_RAWMIDI_DEVICES 8
45
46#define SNDRV_RAWMIDI_LFLG_OUTPUT (1<<0)
47#define SNDRV_RAWMIDI_LFLG_INPUT (1<<1)
48#define SNDRV_RAWMIDI_LFLG_OPEN (3<<0)
49#define SNDRV_RAWMIDI_LFLG_APPEND (1<<2)
50#define SNDRV_RAWMIDI_LFLG_NOOPENLOCK (1<<3)
51
52typedef struct _snd_rawmidi_runtime snd_rawmidi_runtime_t;
53typedef struct _snd_rawmidi_substream snd_rawmidi_substream_t;
54typedef struct _snd_rawmidi_str snd_rawmidi_str_t;
55
56typedef struct _snd_rawmidi_ops {
57 int (*open) (snd_rawmidi_substream_t * substream);
58 int (*close) (snd_rawmidi_substream_t * substream);
59 void (*trigger) (snd_rawmidi_substream_t * substream, int up);
60 void (*drain) (snd_rawmidi_substream_t * substream);
61} snd_rawmidi_ops_t;
62
63typedef struct _snd_rawmidi_global_ops {
64 int (*dev_register) (snd_rawmidi_t * rmidi);
65 int (*dev_unregister) (snd_rawmidi_t * rmidi);
66} snd_rawmidi_global_ops_t;
67
68struct _snd_rawmidi_runtime {
69 unsigned int drain: 1, /* drain stage */
70 oss: 1; /* OSS compatible mode */
71 /* midi stream buffer */
72 unsigned char *buffer; /* buffer for MIDI data */
73 size_t buffer_size; /* size of buffer */
74 size_t appl_ptr; /* application pointer */
75 size_t hw_ptr; /* hardware pointer */
76 size_t avail_min; /* min avail for wakeup */
77 size_t avail; /* max used buffer for wakeup */
78 size_t xruns; /* over/underruns counter */
79 /* misc */
80 spinlock_t lock;
81 wait_queue_head_t sleep;
82 /* event handler (new bytes, input only) */
83 void (*event)(snd_rawmidi_substream_t *substream);
84 /* defers calls to event [input] or ops->trigger [output] */
85 struct tasklet_struct tasklet;
86 /* private data */
87 void *private_data;
88 void (*private_free)(snd_rawmidi_substream_t *substream);
89};
90
91struct _snd_rawmidi_substream {
92 struct list_head list; /* list of all substream for given stream */
93 int stream; /* direction */
94 int number; /* substream number */
95 unsigned int opened: 1, /* open flag */
96 append: 1, /* append flag (merge more streams) */
97 active_sensing: 1; /* send active sensing when close */
98 int use_count; /* use counter (for output) */
99 size_t bytes;
100 snd_rawmidi_t *rmidi;
101 snd_rawmidi_str_t *pstr;
102 char name[32];
103 snd_rawmidi_runtime_t *runtime;
104 /* hardware layer */
105 snd_rawmidi_ops_t *ops;
106};
107
108typedef struct _snd_rawmidi_file {
109 snd_rawmidi_t *rmidi;
110 snd_rawmidi_substream_t *input;
111 snd_rawmidi_substream_t *output;
112} snd_rawmidi_file_t;
113
114struct _snd_rawmidi_str {
115 unsigned int substream_count;
116 unsigned int substream_opened;
117 struct list_head substreams;
118};
119
120struct _snd_rawmidi {
121 snd_card_t *card;
122
123 unsigned int device; /* device number */
124 unsigned int info_flags; /* SNDRV_RAWMIDI_INFO_XXXX */
125 char id[64];
126 char name[80];
127
128#ifdef CONFIG_SND_OSSEMUL
129 int ossreg;
130#endif
131
132 snd_rawmidi_global_ops_t *ops;
133
134 snd_rawmidi_str_t streams[2];
135
136 void *private_data;
137 void (*private_free) (snd_rawmidi_t *rmidi);
138
139 struct semaphore open_mutex;
140 wait_queue_head_t open_wait;
141
142 snd_info_entry_t *dev;
143 snd_info_entry_t *proc_entry;
144
145#if defined(CONFIG_SND_SEQUENCER) || defined(CONFIG_SND_SEQUENCER_MODULE)
146 snd_seq_device_t *seq_dev;
147#endif
148};
149
150/* main rawmidi functions */
151
152int snd_rawmidi_new(snd_card_t * card, char *id, int device,
153 int output_count, int input_count,
154 snd_rawmidi_t ** rmidi);
155void snd_rawmidi_set_ops(snd_rawmidi_t * rmidi, int stream, snd_rawmidi_ops_t * ops);
156
157/* callbacks */
158
159void snd_rawmidi_receive_reset(snd_rawmidi_substream_t * substream);
160int snd_rawmidi_receive(snd_rawmidi_substream_t * substream, const unsigned char *buffer, int count);
161void snd_rawmidi_transmit_reset(snd_rawmidi_substream_t * substream);
162int snd_rawmidi_transmit_empty(snd_rawmidi_substream_t * substream);
163int snd_rawmidi_transmit_peek(snd_rawmidi_substream_t * substream, unsigned char *buffer, int count);
164int snd_rawmidi_transmit_ack(snd_rawmidi_substream_t * substream, int count);
165int snd_rawmidi_transmit(snd_rawmidi_substream_t * substream, unsigned char *buffer, int count);
166
167/* main midi functions */
168
169int snd_rawmidi_info_select(snd_card_t *card, snd_rawmidi_info_t *info);
170int snd_rawmidi_kernel_open(int cardnum, int device, int subdevice, int mode, snd_rawmidi_file_t * rfile);
171int snd_rawmidi_kernel_release(snd_rawmidi_file_t * rfile);
172int snd_rawmidi_output_params(snd_rawmidi_substream_t * substream, snd_rawmidi_params_t * params);
173int snd_rawmidi_input_params(snd_rawmidi_substream_t * substream, snd_rawmidi_params_t * params);
174int snd_rawmidi_drop_output(snd_rawmidi_substream_t * substream);
175int snd_rawmidi_drain_output(snd_rawmidi_substream_t * substream);
176int snd_rawmidi_drain_input(snd_rawmidi_substream_t * substream);
177long snd_rawmidi_kernel_read(snd_rawmidi_substream_t * substream, unsigned char *buf, long count);
178long snd_rawmidi_kernel_write(snd_rawmidi_substream_t * substream, const unsigned char *buf, long count);
179
180#endif /* __SOUND_RAWMIDI_H */
diff --git a/include/sound/sb.h b/include/sound/sb.h
new file mode 100644
index 000000000000..7960452445e6
--- /dev/null
+++ b/include/sound/sb.h
@@ -0,0 +1,360 @@
1#ifndef __SOUND_SB_H
2#define __SOUND_SB_H
3
4/*
5 * Header file for SoundBlaster cards
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "pcm.h"
26#include "rawmidi.h"
27#include <linux/interrupt.h>
28#include <asm/io.h>
29
30enum sb_hw_type {
31 SB_HW_AUTO,
32 SB_HW_10,
33 SB_HW_20,
34 SB_HW_201,
35 SB_HW_PRO,
36 SB_HW_16,
37 SB_HW_16CSP, /* SB16 with CSP chip */
38 SB_HW_ALS100, /* Avance Logic ALS100 chip */
39 SB_HW_ALS4000, /* Avance Logic ALS4000 chip */
40 SB_HW_DT019X, /* Diamond Tech. DT-019X / Avance Logic ALS-007 */
41};
42
43#define SB_OPEN_PCM 0x01
44#define SB_OPEN_MIDI_INPUT 0x02
45#define SB_OPEN_MIDI_OUTPUT 0x04
46#define SB_OPEN_MIDI_INPUT_TRIGGER 0x08
47#define SB_OPEN_MIDI_OUTPUT_TRIGGER 0x10
48
49#define SB_MODE_HALT 0x00
50#define SB_MODE_PLAYBACK_8 0x01
51#define SB_MODE_PLAYBACK_16 0x02
52#define SB_MODE_PLAYBACK (SB_MODE_PLAYBACK_8 | SB_MODE_PLAYBACK_16)
53#define SB_MODE_CAPTURE_8 0x04
54#define SB_MODE_CAPTURE_16 0x08
55#define SB_MODE_CAPTURE (SB_MODE_CAPTURE_8 | SB_MODE_CAPTURE_16)
56
57#define SB_RATE_LOCK_PLAYBACK 0x10
58#define SB_RATE_LOCK_CAPTURE 0x20
59#define SB_RATE_LOCK (SB_RATE_LOCK_PLAYBACK | SB_RATE_LOCK_CAPTURE)
60
61#define SB_MPU_INPUT 1
62
63struct _snd_sb {
64 unsigned long port; /* base port of DSP chip */
65 struct resource *res_port;
66 unsigned long mpu_port; /* MPU port for SB DSP 4.0+ */
67 int irq; /* IRQ number of DSP chip */
68 int dma8; /* 8-bit DMA */
69 int dma16; /* 16-bit DMA */
70 unsigned short version; /* version of DSP chip */
71 enum sb_hw_type hardware; /* see to SB_HW_XXXX */
72
73 unsigned long alt_port; /* alternate port (ALS4000) */
74 struct pci_dev *pci; /* ALS4000 */
75
76 unsigned int open; /* see to SB_OPEN_XXXX for sb8 */
77 /* also SNDRV_SB_CSP_MODE_XXX for sb16_csp */
78 unsigned int mode; /* current mode of stream */
79 unsigned int force_mode16; /* force 16-bit mode of streams */
80 unsigned int locked_rate; /* sb16 duplex */
81 unsigned int playback_format;
82 unsigned int capture_format;
83 struct timer_list midi_timer;
84 unsigned int p_dma_size;
85 unsigned int p_period_size;
86 unsigned int c_dma_size;
87 unsigned int c_period_size;
88
89 spinlock_t mixer_lock;
90
91 char name[32];
92
93 void *csp; /* used only when CONFIG_SND_SB16_CSP is set */
94
95 snd_card_t *card;
96 snd_pcm_t *pcm;
97 snd_pcm_substream_t *playback_substream;
98 snd_pcm_substream_t *capture_substream;
99
100 snd_rawmidi_t *rmidi;
101 snd_rawmidi_substream_t *midi_substream_input;
102 snd_rawmidi_substream_t *midi_substream_output;
103 irqreturn_t (*rmidi_callback)(int irq, void *dev_id, struct pt_regs *regs);
104
105 spinlock_t reg_lock;
106 spinlock_t open_lock;
107 spinlock_t midi_input_lock;
108
109 snd_info_entry_t *proc_entry;
110};
111
112typedef struct _snd_sb sb_t;
113
114/* I/O ports */
115
116#define SBP(chip, x) ((chip)->port + s_b_SB_##x)
117#define SBP1(port, x) ((port) + s_b_SB_##x)
118
119#define s_b_SB_RESET 0x6
120#define s_b_SB_READ 0xa
121#define s_b_SB_WRITE 0xc
122#define s_b_SB_COMMAND 0xc
123#define s_b_SB_STATUS 0xc
124#define s_b_SB_DATA_AVAIL 0xe
125#define s_b_SB_DATA_AVAIL_16 0xf
126#define s_b_SB_MIXER_ADDR 0x4
127#define s_b_SB_MIXER_DATA 0x5
128#define s_b_SB_OPL3_LEFT 0x0
129#define s_b_SB_OPL3_RIGHT 0x2
130#define s_b_SB_OPL3_BOTH 0x8
131
132#define SB_DSP_OUTPUT 0x14
133#define SB_DSP_INPUT 0x24
134#define SB_DSP_BLOCK_SIZE 0x48
135#define SB_DSP_HI_OUTPUT 0x91
136#define SB_DSP_HI_INPUT 0x99
137#define SB_DSP_LO_OUTPUT_AUTO 0x1c
138#define SB_DSP_LO_INPUT_AUTO 0x2c
139#define SB_DSP_HI_OUTPUT_AUTO 0x90
140#define SB_DSP_HI_INPUT_AUTO 0x98
141#define SB_DSP_IMMED_INT 0xf2
142#define SB_DSP_GET_VERSION 0xe1
143#define SB_DSP_SPEAKER_ON 0xd1
144#define SB_DSP_SPEAKER_OFF 0xd3
145#define SB_DSP_DMA8_OFF 0xd0
146#define SB_DSP_DMA8_ON 0xd4
147#define SB_DSP_DMA8_EXIT 0xda
148#define SB_DSP_DMA16_OFF 0xd5
149#define SB_DSP_DMA16_ON 0xd6
150#define SB_DSP_DMA16_EXIT 0xd9
151#define SB_DSP_SAMPLE_RATE 0x40
152#define SB_DSP_SAMPLE_RATE_OUT 0x41
153#define SB_DSP_SAMPLE_RATE_IN 0x42
154#define SB_DSP_MONO_8BIT 0xa0
155#define SB_DSP_MONO_16BIT 0xa4
156#define SB_DSP_STEREO_8BIT 0xa8
157#define SB_DSP_STEREO_16BIT 0xac
158
159#define SB_DSP_MIDI_INPUT_IRQ 0x31
160#define SB_DSP_MIDI_UART_IRQ 0x35
161#define SB_DSP_MIDI_OUTPUT 0x38
162
163#define SB_DSP4_OUT8_AI 0xc6
164#define SB_DSP4_IN8_AI 0xce
165#define SB_DSP4_OUT16_AI 0xb6
166#define SB_DSP4_IN16_AI 0xbe
167#define SB_DSP4_MODE_UNS_MONO 0x00
168#define SB_DSP4_MODE_SIGN_MONO 0x10
169#define SB_DSP4_MODE_UNS_STEREO 0x20
170#define SB_DSP4_MODE_SIGN_STEREO 0x30
171
172#define SB_DSP4_OUTPUT 0x3c
173#define SB_DSP4_INPUT_LEFT 0x3d
174#define SB_DSP4_INPUT_RIGHT 0x3e
175
176/* registers for SB 2.0 mixer */
177#define SB_DSP20_MASTER_DEV 0x02
178#define SB_DSP20_PCM_DEV 0x0A
179#define SB_DSP20_CD_DEV 0x08
180#define SB_DSP20_FM_DEV 0x06
181
182/* registers for SB PRO mixer */
183#define SB_DSP_MASTER_DEV 0x22
184#define SB_DSP_PCM_DEV 0x04
185#define SB_DSP_LINE_DEV 0x2e
186#define SB_DSP_CD_DEV 0x28
187#define SB_DSP_FM_DEV 0x26
188#define SB_DSP_MIC_DEV 0x0a
189#define SB_DSP_CAPTURE_SOURCE 0x0c
190#define SB_DSP_CAPTURE_FILT 0x0c
191#define SB_DSP_PLAYBACK_FILT 0x0e
192#define SB_DSP_STEREO_SW 0x0e
193
194#define SB_DSP_MIXS_MIC0 0x00 /* same as MIC */
195#define SB_DSP_MIXS_CD 0x01
196#define SB_DSP_MIXS_MIC 0x02
197#define SB_DSP_MIXS_LINE 0x03
198
199/* registers (only for left channel) for SB 16 mixer */
200#define SB_DSP4_MASTER_DEV 0x30
201#define SB_DSP4_BASS_DEV 0x46
202#define SB_DSP4_TREBLE_DEV 0x44
203#define SB_DSP4_SYNTH_DEV 0x34
204#define SB_DSP4_PCM_DEV 0x32
205#define SB_DSP4_SPEAKER_DEV 0x3b
206#define SB_DSP4_LINE_DEV 0x38
207#define SB_DSP4_MIC_DEV 0x3a
208#define SB_DSP4_OUTPUT_SW 0x3c
209#define SB_DSP4_CD_DEV 0x36
210#define SB_DSP4_IGAIN_DEV 0x3f
211#define SB_DSP4_OGAIN_DEV 0x41
212#define SB_DSP4_MIC_AGC 0x43
213
214/* additional registers for SB 16 mixer */
215#define SB_DSP4_IRQSETUP 0x80
216#define SB_DSP4_DMASETUP 0x81
217#define SB_DSP4_IRQSTATUS 0x82
218#define SB_DSP4_MPUSETUP 0x84
219
220#define SB_DSP4_3DSE 0x90
221
222/* Registers for DT-019x / ALS-007 mixer */
223#define SB_DT019X_MASTER_DEV 0x62
224#define SB_DT019X_PCM_DEV 0x64
225#define SB_DT019X_SYNTH_DEV 0x66
226#define SB_DT019X_CD_DEV 0x68
227#define SB_DT019X_MIC_DEV 0x6a
228#define SB_DT019X_SPKR_DEV 0x6a
229#define SB_DT019X_LINE_DEV 0x6e
230#define SB_DT019X_OUTPUT_SW2 0x4c
231#define SB_DT019X_CAPTURE_SW 0x6c
232
233#define SB_DT019X_CAP_CD 0x02
234#define SB_DT019X_CAP_MIC 0x04
235#define SB_DT019X_CAP_LINE 0x06
236#define SB_DT019X_CAP_SYNTH 0x07
237#define SB_DT019X_CAP_MAIN 0x07
238
239#define SB_ALS4000_MONO_IO_CTRL 0x4b
240#define SB_ALS4000_MIC_IN_GAIN 0x4d
241#define SB_ALS4000_FMDAC 0x4f
242#define SB_ALS4000_3D_SND_FX 0x50
243#define SB_ALS4000_3D_TIME_DELAY 0x51
244#define SB_ALS4000_3D_AUTO_MUTE 0x52
245#define SB_ALS4000_QSOUND 0xdb
246
247/* IRQ setting bitmap */
248#define SB_IRQSETUP_IRQ9 0x01
249#define SB_IRQSETUP_IRQ5 0x02
250#define SB_IRQSETUP_IRQ7 0x04
251#define SB_IRQSETUP_IRQ10 0x08
252
253/* IRQ types */
254#define SB_IRQTYPE_8BIT 0x01
255#define SB_IRQTYPE_16BIT 0x02
256#define SB_IRQTYPE_MPUIN 0x04
257
258/* DMA setting bitmap */
259#define SB_DMASETUP_DMA0 0x01
260#define SB_DMASETUP_DMA1 0x02
261#define SB_DMASETUP_DMA3 0x08
262#define SB_DMASETUP_DMA5 0x20
263#define SB_DMASETUP_DMA6 0x40
264#define SB_DMASETUP_DMA7 0x80
265
266/*
267 *
268 */
269
270static inline void snd_sb_ack_8bit(sb_t *chip)
271{
272 inb(SBP(chip, DATA_AVAIL));
273}
274
275static inline void snd_sb_ack_16bit(sb_t *chip)
276{
277 inb(SBP(chip, DATA_AVAIL_16));
278}
279
280/* sb_common.c */
281int snd_sbdsp_command(sb_t *chip, unsigned char val);
282int snd_sbdsp_get_byte(sb_t *chip);
283int snd_sbdsp_reset(sb_t *chip);
284int snd_sbdsp_create(snd_card_t *card,
285 unsigned long port,
286 int irq,
287 irqreturn_t (*irq_handler)(int, void *, struct pt_regs *),
288 int dma8, int dma16,
289 unsigned short hardware,
290 sb_t **r_chip);
291/* sb_mixer.c */
292void snd_sbmixer_write(sb_t *chip, unsigned char reg, unsigned char data);
293unsigned char snd_sbmixer_read(sb_t *chip, unsigned char reg);
294int snd_sbmixer_new(sb_t *chip);
295
296/* sb8_init.c */
297int snd_sb8dsp_pcm(sb_t *chip, int device, snd_pcm_t ** rpcm);
298/* sb8.c */
299irqreturn_t snd_sb8dsp_interrupt(sb_t *chip);
300int snd_sb8_playback_open(snd_pcm_substream_t *substream);
301int snd_sb8_capture_open(snd_pcm_substream_t *substream);
302int snd_sb8_playback_close(snd_pcm_substream_t *substream);
303int snd_sb8_capture_close(snd_pcm_substream_t *substream);
304/* midi8.c */
305irqreturn_t snd_sb8dsp_midi_interrupt(sb_t *chip);
306int snd_sb8dsp_midi(sb_t *chip, int device, snd_rawmidi_t ** rrawmidi);
307
308/* sb16_init.c */
309int snd_sb16dsp_pcm(sb_t *chip, int device, snd_pcm_t ** rpcm);
310const snd_pcm_ops_t *snd_sb16dsp_get_pcm_ops(int direction);
311int snd_sb16dsp_configure(sb_t *chip);
312/* sb16.c */
313irqreturn_t snd_sb16dsp_interrupt(int irq, void *dev_id, struct pt_regs *regs);
314
315/* exported mixer stuffs */
316enum {
317 SB_MIX_SINGLE,
318 SB_MIX_DOUBLE,
319 SB_MIX_INPUT_SW,
320 SB_MIX_CAPTURE_PRO,
321 SB_MIX_CAPTURE_DT019X
322};
323
324#define SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) \
325 ((left_reg) | ((right_reg) << 8) | ((left_shift) << 16) | ((right_shift) << 19) | ((mask) << 24))
326#define SB_MIXVAL_SINGLE(reg, shift, mask) \
327 ((reg) | ((shift) << 16) | ((mask) << 24))
328#define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
329 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
330
331int snd_sbmixer_add_ctl(sb_t *chip, const char *name, int index, int type, unsigned long value);
332
333/* for ease of use */
334struct sbmix_elem {
335 const char *name;
336 int type;
337 unsigned long private_value;
338};
339
340#define SB_SINGLE(xname, reg, shift, mask) \
341{ .name = xname, \
342 .type = SB_MIX_SINGLE, \
343 .private_value = SB_MIXVAL_SINGLE(reg, shift, mask) }
344
345#define SB_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask) \
346{ .name = xname, \
347 .type = SB_MIX_DOUBLE, \
348 .private_value = SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) }
349
350#define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
351{ .name = xname, \
352 .type = SB_MIX_INPUT_SW, \
353 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
354
355static inline int snd_sbmixer_add_ctl_elem(sb_t *chip, const struct sbmix_elem *c)
356{
357 return snd_sbmixer_add_ctl(chip, c->name, 0, c->type, c->private_value);
358}
359
360#endif /* __SOUND_SB_H */
diff --git a/include/sound/sb16_csp.h b/include/sound/sb16_csp.h
new file mode 100644
index 000000000000..eb8368b56b16
--- /dev/null
+++ b/include/sound/sb16_csp.h
@@ -0,0 +1,167 @@
1#ifndef __SOUND_SB16_CSP_H
2#define __SOUND_SB16_CSP_H
3
4/*
5 * Copyright (c) 1999 by Uros Bizjak <uros@kss-loka.si>
6 * Takashi Iwai <tiwai@suse.de>
7 *
8 * SB16ASP/AWE32 CSP control
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26/* CSP modes */
27#define SNDRV_SB_CSP_MODE_NONE 0x00
28#define SNDRV_SB_CSP_MODE_DSP_READ 0x01 /* Record from DSP */
29#define SNDRV_SB_CSP_MODE_DSP_WRITE 0x02 /* Play to DSP */
30#define SNDRV_SB_CSP_MODE_QSOUND 0x04 /* QSound */
31
32/* CSP load flags */
33#define SNDRV_SB_CSP_LOAD_FROMUSER 0x01
34#define SNDRV_SB_CSP_LOAD_INITBLOCK 0x02
35
36/* CSP sample width */
37#define SNDRV_SB_CSP_SAMPLE_8BIT 0x01
38#define SNDRV_SB_CSP_SAMPLE_16BIT 0x02
39
40/* CSP channels */
41#define SNDRV_SB_CSP_MONO 0x01
42#define SNDRV_SB_CSP_STEREO 0x02
43
44/* CSP rates */
45#define SNDRV_SB_CSP_RATE_8000 0x01
46#define SNDRV_SB_CSP_RATE_11025 0x02
47#define SNDRV_SB_CSP_RATE_22050 0x04
48#define SNDRV_SB_CSP_RATE_44100 0x08
49#define SNDRV_SB_CSP_RATE_ALL 0x0f
50
51/* CSP running state */
52#define SNDRV_SB_CSP_ST_IDLE 0x00
53#define SNDRV_SB_CSP_ST_LOADED 0x01
54#define SNDRV_SB_CSP_ST_RUNNING 0x02
55#define SNDRV_SB_CSP_ST_PAUSED 0x04
56#define SNDRV_SB_CSP_ST_AUTO 0x08
57#define SNDRV_SB_CSP_ST_QSOUND 0x10
58
59/* maximum QSound value (180 degrees right) */
60#define SNDRV_SB_CSP_QSOUND_MAX_RIGHT 0x20
61
62/* maximum microcode RIFF file size */
63#define SNDRV_SB_CSP_MAX_MICROCODE_FILE_SIZE 0x3000
64
65/* microcode header */
66typedef struct snd_sb_csp_mc_header {
67 char codec_name[16]; /* id name of codec */
68 unsigned short func_req; /* requested function */
69} snd_sb_csp_mc_header_t;
70
71/* microcode to be loaded */
72typedef struct snd_sb_csp_microcode {
73 snd_sb_csp_mc_header_t info;
74 unsigned char data[SNDRV_SB_CSP_MAX_MICROCODE_FILE_SIZE];
75} snd_sb_csp_microcode_t;
76
77/* start CSP with sample_width in mono/stereo */
78typedef struct snd_sb_csp_start {
79 int sample_width; /* sample width, look above */
80 int channels; /* channels, look above */
81} snd_sb_csp_start_t;
82
83/* CSP information */
84typedef struct snd_sb_csp_info {
85 char codec_name[16]; /* id name of codec */
86 unsigned short func_nr; /* function number */
87 unsigned int acc_format; /* accepted PCM formats */
88 unsigned short acc_channels; /* accepted channels */
89 unsigned short acc_width; /* accepted sample width */
90 unsigned short acc_rates; /* accepted sample rates */
91 unsigned short csp_mode; /* CSP mode, see above */
92 unsigned short run_channels; /* current channels */
93 unsigned short run_width; /* current sample width */
94 unsigned short version; /* version id: 0x10 - 0x1f */
95 unsigned short state; /* state bits */
96} snd_sb_csp_info_t;
97
98/* HWDEP controls */
99/* get CSP information */
100#define SNDRV_SB_CSP_IOCTL_INFO _IOR('H', 0x10, snd_sb_csp_info_t)
101/* load microcode to CSP */
102#define SNDRV_SB_CSP_IOCTL_LOAD_CODE _IOW('H', 0x11, snd_sb_csp_microcode_t)
103/* unload microcode from CSP */
104#define SNDRV_SB_CSP_IOCTL_UNLOAD_CODE _IO('H', 0x12)
105/* start CSP */
106#define SNDRV_SB_CSP_IOCTL_START _IOW('H', 0x13, snd_sb_csp_start_t)
107/* stop CSP */
108#define SNDRV_SB_CSP_IOCTL_STOP _IO('H', 0x14)
109/* pause CSP and DMA transfer */
110#define SNDRV_SB_CSP_IOCTL_PAUSE _IO('H', 0x15)
111/* restart CSP and DMA transfer */
112#define SNDRV_SB_CSP_IOCTL_RESTART _IO('H', 0x16)
113
114#ifdef __KERNEL__
115#include "sb.h"
116#include "hwdep.h"
117
118typedef struct snd_sb_csp snd_sb_csp_t;
119
120/*
121 * CSP operators
122 */
123typedef struct {
124 int (*csp_use) (snd_sb_csp_t * p);
125 int (*csp_unuse) (snd_sb_csp_t * p);
126 int (*csp_autoload) (snd_sb_csp_t * p, int pcm_sfmt, int play_rec_mode);
127 int (*csp_start) (snd_sb_csp_t * p, int sample_width, int channels);
128 int (*csp_stop) (snd_sb_csp_t * p);
129 int (*csp_qsound_transfer) (snd_sb_csp_t * p);
130} snd_sb_csp_ops_t;
131
132/*
133 * CSP private data
134 */
135struct snd_sb_csp {
136 sb_t *chip; /* SB16 DSP */
137 int used; /* usage flag - exclusive */
138 char codec_name[16]; /* name of codec */
139 unsigned short func_nr; /* function number */
140 unsigned int acc_format; /* accepted PCM formats */
141 int acc_channels; /* accepted channels */
142 int acc_width; /* accepted sample width */
143 int acc_rates; /* accepted sample rates */
144 int mode; /* MODE */
145 int run_channels; /* current CSP channels */
146 int run_width; /* current sample width */
147 int version; /* CSP version (0x10 - 0x1f) */
148 int running; /* running state */
149
150 snd_sb_csp_ops_t ops; /* operators */
151
152 spinlock_t q_lock; /* locking */
153 int q_enabled; /* enabled flag */
154 int qpos_left; /* left position */
155 int qpos_right; /* right position */
156 int qpos_changed; /* position changed flag */
157
158 snd_kcontrol_t *qsound_switch;
159 snd_kcontrol_t *qsound_space;
160
161 struct semaphore access_mutex; /* locking */
162};
163
164int snd_sb_csp_new(sb_t *chip, int device, snd_hwdep_t ** rhwdep);
165#endif
166
167#endif /* __SOUND_SB16_CSP */
diff --git a/include/sound/seq_device.h b/include/sound/seq_device.h
new file mode 100644
index 000000000000..204ca540c28e
--- /dev/null
+++ b/include/sound/seq_device.h
@@ -0,0 +1,88 @@
1#ifndef __SOUND_SEQ_DEVICE_H
2#define __SOUND_SEQ_DEVICE_H
3
4/*
5 * ALSA sequencer device management
6 * Copyright (c) 1999 by Takashi Iwai <tiwai@suse.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24typedef struct snd_seq_device snd_seq_device_t;
25typedef struct snd_seq_dev_ops snd_seq_dev_ops_t;
26
27/*
28 * registered device information
29 */
30
31#define ID_LEN 32
32
33/* status flag */
34#define SNDRV_SEQ_DEVICE_FREE 0
35#define SNDRV_SEQ_DEVICE_REGISTERED 1
36
37struct snd_seq_device {
38 /* device info */
39 snd_card_t *card; /* sound card */
40 int device; /* device number */
41 char id[ID_LEN]; /* driver id */
42 char name[80]; /* device name */
43 int argsize; /* size of the argument */
44 void *driver_data; /* private data for driver */
45 int status; /* flag - read only */
46 void *private_data; /* private data for the caller */
47 void (*private_free)(snd_seq_device_t *device);
48 struct list_head list; /* link to next device */
49};
50
51
52/* driver operators
53 * init_device:
54 * Initialize the device with given parameters.
55 * Typically,
56 * 1. call snd_hwdep_new
57 * 2. allocate private data and initialize it
58 * 3. call snd_hwdep_register
59 * 4. store the instance to dev->driver_data pointer.
60 *
61 * free_device:
62 * Release the private data.
63 * Typically, call snd_device_free(dev->card, dev->driver_data)
64 */
65struct snd_seq_dev_ops {
66 int (*init_device)(snd_seq_device_t *dev);
67 int (*free_device)(snd_seq_device_t *dev);
68};
69
70/*
71 * prototypes
72 */
73void snd_seq_device_load_drivers(void);
74int snd_seq_device_new(snd_card_t *card, int device, char *id, int argsize, snd_seq_device_t **result);
75int snd_seq_device_register_driver(char *id, snd_seq_dev_ops_t *entry, int argsize);
76int snd_seq_device_unregister_driver(char *id);
77
78#define SNDRV_SEQ_DEVICE_ARGPTR(dev) (void *)((char *)(dev) + sizeof(snd_seq_device_t))
79
80
81/*
82 * id strings for generic devices
83 */
84#define SNDRV_SEQ_DEV_ID_MIDISYNTH "seq-midi"
85#define SNDRV_SEQ_DEV_ID_OPL3 "opl3-synth"
86
87
88#endif /* __SOUND_SEQ_DEVICE_H */
diff --git a/include/sound/seq_instr.h b/include/sound/seq_instr.h
new file mode 100644
index 000000000000..1a654df4aa97
--- /dev/null
+++ b/include/sound/seq_instr.h
@@ -0,0 +1,112 @@
1#ifndef __SOUND_SEQ_INSTR_H
2#define __SOUND_SEQ_INSTR_H
3
4/*
5 * Main kernel header file for the ALSA sequencer
6 * Copyright (c) 1999 by Jaroslav Kysela <perex@suse.cz>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#include "seq_kernel.h"
25
26/* Instrument cluster */
27typedef struct _snd_seq_kcluster {
28 snd_seq_instr_cluster_t cluster;
29 char name[32];
30 int priority;
31 struct _snd_seq_kcluster *next;
32} snd_seq_kcluster_t;
33
34/* return pointer to private data */
35#define KINSTR_DATA(kinstr) (void *)(((char *)kinstr) + sizeof(snd_seq_kinstr_t))
36
37typedef struct snd_seq_kinstr_ops snd_seq_kinstr_ops_t;
38
39/* Instrument structure */
40typedef struct _snd_seq_kinstr {
41 snd_seq_instr_t instr;
42 char name[32];
43 int type; /* instrument type */
44 int use; /* use count */
45 int busy; /* not useable */
46 int add_len; /* additional length */
47 snd_seq_kinstr_ops_t *ops; /* operations */
48 struct _snd_seq_kinstr *next;
49} snd_seq_kinstr_t;
50
51#define SNDRV_SEQ_INSTR_HASH_SIZE 32
52
53/* Instrument flags */
54#define SNDRV_SEQ_INSTR_FLG_DIRECT (1<<0) /* accept only direct events */
55
56/* List of all instruments */
57typedef struct {
58 snd_seq_kinstr_t *hash[SNDRV_SEQ_INSTR_HASH_SIZE];
59 int count; /* count of all instruments */
60
61 snd_seq_kcluster_t *chash[SNDRV_SEQ_INSTR_HASH_SIZE];
62 int ccount; /* count of all clusters */
63
64 int owner; /* current owner of the instrument list */
65 unsigned int flags;
66
67 spinlock_t lock;
68 spinlock_t ops_lock;
69 struct semaphore ops_mutex;
70 unsigned long ops_flags;
71} snd_seq_kinstr_list_t;
72
73#define SNDRV_SEQ_INSTR_NOTIFY_REMOVE 0
74#define SNDRV_SEQ_INSTR_NOTIFY_CHANGE 1
75
76struct snd_seq_kinstr_ops {
77 void *private_data;
78 long add_len; /* additional length */
79 char *instr_type;
80 int (*info)(void *private_data, char *info_data, long len);
81 int (*put)(void *private_data, snd_seq_kinstr_t *kinstr,
82 char __user *instr_data, long len, int atomic, int cmd);
83 int (*get)(void *private_data, snd_seq_kinstr_t *kinstr,
84 char __user *instr_data, long len, int atomic, int cmd);
85 int (*get_size)(void *private_data, snd_seq_kinstr_t *kinstr, long *size);
86 int (*remove)(void *private_data, snd_seq_kinstr_t *kinstr, int atomic);
87 void (*notify)(void *private_data, snd_seq_kinstr_t *kinstr, int what);
88 struct snd_seq_kinstr_ops *next;
89};
90
91
92/* instrument operations */
93snd_seq_kinstr_list_t *snd_seq_instr_list_new(void);
94void snd_seq_instr_list_free(snd_seq_kinstr_list_t **list);
95int snd_seq_instr_list_free_cond(snd_seq_kinstr_list_t *list,
96 snd_seq_instr_header_t *ifree,
97 int client,
98 int atomic);
99snd_seq_kinstr_t *snd_seq_instr_find(snd_seq_kinstr_list_t *list,
100 snd_seq_instr_t *instr,
101 int exact,
102 int follow_alias);
103void snd_seq_instr_free_use(snd_seq_kinstr_list_t *list,
104 snd_seq_kinstr_t *instr);
105int snd_seq_instr_event(snd_seq_kinstr_ops_t *ops,
106 snd_seq_kinstr_list_t *list,
107 snd_seq_event_t *ev,
108 int client,
109 int atomic,
110 int hop);
111
112#endif /* __SOUND_SEQ_INSTR_H */
diff --git a/include/sound/seq_kernel.h b/include/sound/seq_kernel.h
new file mode 100644
index 000000000000..4beca1952c76
--- /dev/null
+++ b/include/sound/seq_kernel.h
@@ -0,0 +1,191 @@
1#ifndef __SOUND_SEQ_KERNEL_H
2#define __SOUND_SEQ_KERNEL_H
3
4/*
5 * Main kernel header file for the ALSA sequencer
6 * Copyright (c) 1998 by Frank van de Pol <fvdpol@coil.demon.nl>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#include <linux/time.h>
25#include "asequencer.h"
26
27typedef sndrv_seq_tick_time_t snd_seq_tick_time_t;
28typedef sndrv_seq_position_t snd_seq_position_t;
29typedef sndrv_seq_frequency_t snd_seq_frequency_t;
30typedef sndrv_seq_instr_cluster_t snd_seq_instr_cluster_t;
31typedef enum sndrv_seq_client_type snd_seq_client_type_t;
32typedef enum sndrv_seq_stop_mode snd_seq_stop_mode_t;
33typedef struct sndrv_seq_port_info snd_seq_port_info_t;
34typedef struct sndrv_seq_port_subscribe snd_seq_port_subscribe_t;
35typedef struct sndrv_seq_event snd_seq_event_t;
36typedef struct sndrv_seq_addr snd_seq_addr_t;
37typedef struct sndrv_seq_ev_volume snd_seq_ev_volume_t;
38typedef struct sndrv_seq_ev_loop snd_seq_ev_loop_t;
39typedef struct sndrv_seq_remove_events snd_seq_remove_events_t;
40typedef struct sndrv_seq_query_subs snd_seq_query_subs_t;
41typedef struct sndrv_seq_real_time snd_seq_real_time_t;
42typedef struct sndrv_seq_system_info snd_seq_system_info_t;
43typedef struct sndrv_seq_client_info snd_seq_client_info_t;
44typedef struct sndrv_seq_queue_info snd_seq_queue_info_t;
45typedef struct sndrv_seq_queue_status snd_seq_queue_status_t;
46typedef struct sndrv_seq_queue_tempo snd_seq_queue_tempo_t;
47typedef struct sndrv_seq_queue_owner snd_seq_queue_owner_t;
48typedef struct sndrv_seq_queue_timer snd_seq_queue_timer_t;
49typedef struct sndrv_seq_queue_client snd_seq_queue_client_t;
50typedef struct sndrv_seq_client_pool snd_seq_client_pool_t;
51typedef struct sndrv_seq_instr snd_seq_instr_t;
52typedef struct sndrv_seq_instr_data snd_seq_instr_data_t;
53typedef struct sndrv_seq_instr_header snd_seq_instr_header_t;
54typedef union sndrv_seq_timestamp snd_seq_timestamp_t;
55
56#define snd_seq_event_bounce_ext_data sndrv_seq_event_bounce_ext_data
57#define snd_seq_ev_is_result_type sndrv_seq_ev_is_result_type
58#define snd_seq_ev_is_channel_type sndrv_seq_ev_is_channel_type
59#define snd_seq_ev_is_note_type sndrv_seq_ev_is_note_type
60#define snd_seq_ev_is_control_type sndrv_seq_ev_is_control_type
61#define snd_seq_ev_is_queue_type sndrv_seq_ev_is_queue_type
62#define snd_seq_ev_is_message_type sndrv_seq_ev_is_message_type
63#define snd_seq_ev_is_sample_type sndrv_seq_ev_is_sample_type
64#define snd_seq_ev_is_user_type sndrv_seq_ev_is_user_type
65#define snd_seq_ev_is_fixed_type sndrv_seq_ev_is_fixed_type
66#define snd_seq_ev_is_instr_type sndrv_seq_ev_is_instr_type
67#define snd_seq_ev_is_variable_type sndrv_seq_ev_is_variable_type
68#define snd_seq_ev_is_reserved sndrv_seq_ev_is_reserved
69#define snd_seq_ev_is_direct sndrv_seq_ev_is_direct
70#define snd_seq_ev_is_prior sndrv_seq_ev_is_prior
71#define snd_seq_ev_length_type sndrv_seq_ev_length_type
72#define snd_seq_ev_is_fixed sndrv_seq_ev_is_fixed
73#define snd_seq_ev_is_variable sndrv_seq_ev_is_variable
74#define snd_seq_ev_is_varusr sndrv_seq_ev_is_varusr
75#define snd_seq_ev_timestamp_type sndrv_seq_ev_timestamp_type
76#define snd_seq_ev_is_tick sndrv_seq_ev_is_tick
77#define snd_seq_ev_is_real sndrv_seq_ev_is_real
78#define snd_seq_ev_timemode_type sndrv_seq_ev_timemode_type
79#define snd_seq_ev_is_abstime sndrv_seq_ev_is_abstime
80#define snd_seq_ev_is_reltime sndrv_seq_ev_is_reltime
81#define snd_seq_queue_sync_port sndrv_seq_queue_sync_port
82#define snd_seq_queue_owner sndrv_seq_queue_owner
83
84/* maximum number of events dequeued per schedule interval */
85#define SNDRV_SEQ_MAX_DEQUEUE 50
86
87/* maximum number of queues */
88#define SNDRV_SEQ_MAX_QUEUES 8
89
90/* max number of concurrent clients */
91#define SNDRV_SEQ_MAX_CLIENTS 192
92
93/* max number of concurrent ports */
94#define SNDRV_SEQ_MAX_PORTS 254
95
96/* max number of events in memory pool */
97#define SNDRV_SEQ_MAX_EVENTS 2000
98
99/* default number of events in memory chunk */
100#define SNDRV_SEQ_DEFAULT_CHUNK_EVENTS 64
101
102/* default number of events in memory pool */
103#define SNDRV_SEQ_DEFAULT_EVENTS 500
104
105/* max number of events in memory pool for one client (outqueue) */
106#define SNDRV_SEQ_MAX_CLIENT_EVENTS 2000
107
108/* default number of events in memory pool for one client (outqueue) */
109#define SNDRV_SEQ_DEFAULT_CLIENT_EVENTS 200
110
111/* max delivery path length */
112#define SNDRV_SEQ_MAX_HOPS 10
113
114/* max size of event size */
115#define SNDRV_SEQ_MAX_EVENT_LEN 0x3fffffff
116
117/* typedefs */
118struct _snd_seq_user_client;
119struct _snd_seq_kernel_client;
120struct _snd_seq_client;
121struct _snd_seq_queue;
122
123typedef struct _snd_seq_user_client user_client_t;
124typedef struct _snd_seq_kernel_client kernel_client_t;
125typedef struct _snd_seq_client client_t;
126typedef struct _snd_seq_queue queue_t;
127
128/* call-backs for kernel client */
129
130typedef struct {
131 void *private_data;
132 unsigned allow_input: 1,
133 allow_output: 1;
134 /*...*/
135} snd_seq_client_callback_t;
136
137/* call-backs for kernel port */
138typedef int (snd_seq_kernel_port_open_t)(void *private_data, snd_seq_port_subscribe_t *info);
139typedef int (snd_seq_kernel_port_close_t)(void *private_data, snd_seq_port_subscribe_t *info);
140typedef int (snd_seq_kernel_port_input_t)(snd_seq_event_t *ev, int direct, void *private_data, int atomic, int hop);
141typedef void (snd_seq_kernel_port_private_free_t)(void *private_data);
142
143typedef struct {
144 struct module *owner;
145 void *private_data;
146 snd_seq_kernel_port_open_t *subscribe;
147 snd_seq_kernel_port_close_t *unsubscribe;
148 snd_seq_kernel_port_open_t *use;
149 snd_seq_kernel_port_close_t *unuse;
150 snd_seq_kernel_port_input_t *event_input;
151 snd_seq_kernel_port_private_free_t *private_free;
152 unsigned int callback_all; /* call subscribe callbacks at each connection/disconnection */
153 /*...*/
154} snd_seq_port_callback_t;
155
156/* interface for kernel client */
157extern int snd_seq_create_kernel_client(snd_card_t *card, int client_index, snd_seq_client_callback_t *callback);
158extern int snd_seq_delete_kernel_client(int client);
159extern int snd_seq_kernel_client_enqueue(int client, snd_seq_event_t *ev, int atomic, int hop);
160extern int snd_seq_kernel_client_dispatch(int client, snd_seq_event_t *ev, int atomic, int hop);
161extern int snd_seq_kernel_client_ctl(int client, unsigned int cmd, void *arg);
162
163#define SNDRV_SEQ_EXT_MASK 0xc0000000
164#define SNDRV_SEQ_EXT_USRPTR 0x80000000
165#define SNDRV_SEQ_EXT_CHAINED 0x40000000
166
167typedef int (*snd_seq_dump_func_t)(void *ptr, void *buf, int count);
168int snd_seq_expand_var_event(const snd_seq_event_t *event, int count, char *buf, int in_kernel, int size_aligned);
169int snd_seq_dump_var_event(const snd_seq_event_t *event, snd_seq_dump_func_t func, void *private_data);
170
171/* interface for OSS emulation */
172int snd_seq_set_queue_tempo(int client, snd_seq_queue_tempo_t *tempo);
173
174/* port callback routines */
175void snd_port_init_callback(snd_seq_port_callback_t *p);
176snd_seq_port_callback_t *snd_port_alloc_callback(void);
177
178/* port attach/detach */
179int snd_seq_event_port_attach(int client, snd_seq_port_callback_t *pcbp,
180 int cap, int type, int midi_channels, int midi_voices, char *portname);
181int snd_seq_event_port_detach(int client, int port);
182
183#ifdef CONFIG_KMOD
184void snd_seq_autoload_lock(void);
185void snd_seq_autoload_unlock(void);
186#else
187#define snd_seq_autoload_lock()
188#define snd_seq_autoload_unlock()
189#endif
190
191#endif /* __SOUND_SEQ_KERNEL_H */
diff --git a/include/sound/seq_midi_emul.h b/include/sound/seq_midi_emul.h
new file mode 100644
index 000000000000..e58ca45bc73b
--- /dev/null
+++ b/include/sound/seq_midi_emul.h
@@ -0,0 +1,195 @@
1#ifndef __SOUND_SEQ_MIDI_EMUL_H
2#define __SOUND_SEQ_MIDI_EMUL_H
3
4/*
5 * Midi channel definition for optional channel management.
6 *
7 * Copyright (C) 1999 Steve Ratcliffe
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "seq_kernel.h"
26
27/*
28 * This structure is used to keep track of the current state on each
29 * channel. All drivers for hardware that does not understand midi
30 * directly will probably need to use this structure.
31 */
32typedef struct snd_midi_channel {
33 void *private; /* A back pointer to driver data */
34 int number; /* The channel number */
35 int client; /* The client associated with this channel */
36 int port; /* The port associated with this channel */
37
38 unsigned char midi_mode; /* GM, GS, XG etc */
39 unsigned int
40 drum_channel:1, /* Drum channel */
41 param_type:1 /* RPN/NRPN */
42 ;
43
44 unsigned char midi_aftertouch; /* Aftertouch (key pressure) */
45 unsigned char midi_pressure; /* Channel pressure */
46 unsigned char midi_program; /* Instrument number */
47 short midi_pitchbend; /* Pitch bend amount */
48
49 unsigned char control[128]; /* Current value of all controls */
50 unsigned char note[128]; /* Current status for all notes */
51
52 short gm_rpn_pitch_bend_range; /* Pitch bend range */
53 short gm_rpn_fine_tuning; /* Master fine tuning */
54 short gm_rpn_coarse_tuning; /* Master coarse tuning */
55
56} snd_midi_channel_t;
57
58/*
59 * A structure that represets a set of channels bound to a port. There
60 * would usually be 16 channels per port. But fewer could be used for
61 * particular cases.
62 * The channel set consists of information describing the client and
63 * port for this midi synth and an array of snd_midi_channel_t structures.
64 * A driver that had no need for snd_midi_channel_t could still use the
65 * channel set type if it wished with the channel array null.
66 */
67typedef struct snd_midi_channel_set {
68 void *private_data; /* Driver data */
69 int client; /* Client for this port */
70 int port; /* The port number */
71
72 int max_channels; /* Size of the channels array */
73 snd_midi_channel_t *channels;
74
75 unsigned char midi_mode; /* MIDI operating mode */
76 unsigned char gs_master_volume; /* SYSEX master volume: 0-127 */
77 unsigned char gs_chorus_mode;
78 unsigned char gs_reverb_mode;
79
80} snd_midi_channel_set_t;
81
82typedef struct snd_seq_midi_op {
83 void (*note_on)(void *private_data, int note, int vel, snd_midi_channel_t *chan);
84 void (*note_off)(void *private_data,int note, int vel, snd_midi_channel_t *chan); /* release note */
85 void (*key_press)(void *private_data, int note, int vel, snd_midi_channel_t *chan);
86 void (*note_terminate)(void *private_data, int note, snd_midi_channel_t *chan); /* terminate note immediately */
87 void (*control)(void *private_data, int type, snd_midi_channel_t *chan);
88 void (*nrpn)(void *private_data, snd_midi_channel_t *chan, snd_midi_channel_set_t *chset);
89 void (*sysex)(void *private_data, unsigned char *buf, int len, int parsed, snd_midi_channel_set_t *chset);
90} snd_midi_op_t;
91
92/*
93 * These defines are used so that pitchbend, aftertouch etc, can be
94 * distinguished from controller values.
95 */
96/* 0-127 controller values */
97#define MIDI_CTL_PITCHBEND 0x80
98#define MIDI_CTL_AFTERTOUCH 0x81
99#define MIDI_CTL_CHAN_PRESSURE 0x82
100
101/*
102 * These names exist to allow symbolic access to the controls array.
103 * The usage is eg: chan->gm_bank_select. Another implementation would
104 * be really have these members in the struct, and not the array.
105 */
106#define gm_bank_select control[0]
107#define gm_modulation control[1]
108#define gm_breath control[2]
109#define gm_foot_pedal control[4]
110#define gm_portamento_time control[5]
111#define gm_data_entry control[6]
112#define gm_volume control[7]
113#define gm_balance control[8]
114#define gm_pan control[10]
115#define gm_expression control[11]
116#define gm_effect_control1 control[12]
117#define gm_effect_control2 control[13]
118#define gm_slider1 control[16]
119#define gm_slider2 control[17]
120#define gm_slider3 control[18]
121#define gm_slider4 control[19]
122
123#define gm_bank_select_lsb control[32]
124#define gm_modulation_wheel_lsb control[33]
125#define gm_breath_lsb control[34]
126#define gm_foot_pedal_lsb control[36]
127#define gm_portamento_time_lsb control[37]
128#define gm_data_entry_lsb control[38]
129#define gm_volume_lsb control[39]
130#define gm_balance_lsb control[40]
131#define gm_pan_lsb control[42]
132#define gm_expression_lsb control[43]
133#define gm_effect_control1_lsb control[44]
134#define gm_effect_control2_lsb control[45]
135
136#define gm_sustain control[MIDI_CTL_SUSTAIN]
137#define gm_hold gm_sustain
138#define gm_portamento control[MIDI_CTL_PORTAMENTO]
139#define gm_sostenuto control[MIDI_CTL_SOSTENUTO]
140
141/*
142 * These macros give the complete value of the controls that consist
143 * of coarse and fine pairs. Of course the fine controls are seldom used
144 * but there is no harm in being complete.
145 */
146#define SNDRV_GM_BANK_SELECT(cp) (((cp)->control[0]<<7)|((cp)->control[32]))
147#define SNDRV_GM_MODULATION_WHEEL(cp) (((cp)->control[1]<<7)|((cp)->control[33]))
148#define SNDRV_GM_BREATH(cp) (((cp)->control[2]<<7)|((cp)->control[34]))
149#define SNDRV_GM_FOOT_PEDAL(cp) (((cp)->control[4]<<7)|((cp)->control[36]))
150#define SNDRV_GM_PORTAMENTO_TIME(cp) (((cp)->control[5]<<7)|((cp)->control[37]))
151#define SNDRV_GM_DATA_ENTRY(cp) (((cp)->control[6]<<7)|((cp)->control[38]))
152#define SNDRV_GM_VOLUME(cp) (((cp)->control[7]<<7)|((cp)->control[39]))
153#define SNDRV_GM_BALANCE(cp) (((cp)->control[8]<<7)|((cp)->control[40]))
154#define SNDRV_GM_PAN(cp) (((cp)->control[10]<<7)|((cp)->control[42]))
155#define SNDRV_GM_EXPRESSION(cp) (((cp)->control[11]<<7)|((cp)->control[43]))
156
157
158/* MIDI mode */
159#define SNDRV_MIDI_MODE_NONE 0 /* Generic midi */
160#define SNDRV_MIDI_MODE_GM 1
161#define SNDRV_MIDI_MODE_GS 2
162#define SNDRV_MIDI_MODE_XG 3
163#define SNDRV_MIDI_MODE_MT32 4
164
165/* MIDI note state */
166#define SNDRV_MIDI_NOTE_OFF 0x00
167#define SNDRV_MIDI_NOTE_ON 0x01
168#define SNDRV_MIDI_NOTE_RELEASED 0x02
169#define SNDRV_MIDI_NOTE_SOSTENUTO 0x04
170
171#define SNDRV_MIDI_PARAM_TYPE_REGISTERED 0
172#define SNDRV_MIDI_PARAM_TYPE_NONREGISTERED 1
173
174/* SYSEX parse flag */
175enum {
176 SNDRV_MIDI_SYSEX_NOT_PARSED = 0,
177 SNDRV_MIDI_SYSEX_GM_ON,
178 SNDRV_MIDI_SYSEX_GS_ON,
179 SNDRV_MIDI_SYSEX_GS_RESET,
180 SNDRV_MIDI_SYSEX_GS_CHORUS_MODE,
181 SNDRV_MIDI_SYSEX_GS_REVERB_MODE,
182 SNDRV_MIDI_SYSEX_GS_MASTER_VOLUME,
183 SNDRV_MIDI_SYSEX_GS_PROGRAM,
184 SNDRV_MIDI_SYSEX_GS_DRUM_CHANNEL,
185 SNDRV_MIDI_SYSEX_XG_ON,
186};
187
188/* Prototypes for midi_process.c */
189void snd_midi_process_event(snd_midi_op_t *ops, snd_seq_event_t *ev,
190 snd_midi_channel_set_t *chanset);
191void snd_midi_channel_set_clear(snd_midi_channel_set_t *chset);
192snd_midi_channel_set_t *snd_midi_channel_alloc_set(int n);
193void snd_midi_channel_free_set(snd_midi_channel_set_t *chset);
194
195#endif /* __SOUND_SEQ_MIDI_EMUL_H */
diff --git a/include/sound/seq_midi_event.h b/include/sound/seq_midi_event.h
new file mode 100644
index 000000000000..4357cac07500
--- /dev/null
+++ b/include/sound/seq_midi_event.h
@@ -0,0 +1,56 @@
1#ifndef __SOUND_SEQ_MIDI_EVENT_H
2#define __SOUND_SEQ_MIDI_EVENT_H
3
4/*
5 * MIDI byte <-> sequencer event coder
6 *
7 * Copyright (C) 1998,99 Takashi Iwai <tiwai@suse.de>,
8 * Jaroslav Kysela <perex@suse.cz>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#include "asequencer.h"
26
27#define MAX_MIDI_EVENT_BUF 256
28
29typedef struct snd_midi_event_t snd_midi_event_t;
30
31/* midi status */
32struct snd_midi_event_t {
33 int qlen; /* queue length */
34 int read; /* chars read */
35 int type; /* current event type */
36 unsigned char lastcmd; /* last command (for MIDI state handling) */
37 unsigned char nostat; /* no state flag */
38 int bufsize; /* allocated buffer size */
39 unsigned char *buf; /* input buffer */
40 spinlock_t lock;
41};
42
43int snd_midi_event_new(int bufsize, snd_midi_event_t **rdev);
44int snd_midi_event_resize_buffer(snd_midi_event_t *dev, int bufsize);
45void snd_midi_event_free(snd_midi_event_t *dev);
46void snd_midi_event_init(snd_midi_event_t *dev);
47void snd_midi_event_reset_encode(snd_midi_event_t *dev);
48void snd_midi_event_reset_decode(snd_midi_event_t *dev);
49void snd_midi_event_no_status(snd_midi_event_t *dev, int on);
50/* encode from byte stream - return number of written bytes if success */
51long snd_midi_event_encode(snd_midi_event_t *dev, unsigned char *buf, long count, snd_seq_event_t *ev);
52int snd_midi_event_encode_byte(snd_midi_event_t *dev, int c, snd_seq_event_t *ev);
53/* decode from event to bytes - return number of written bytes if success */
54long snd_midi_event_decode(snd_midi_event_t *dev, unsigned char *buf, long count, snd_seq_event_t *ev);
55
56#endif /* __SOUND_SEQ_MIDI_EVENT_H */
diff --git a/include/sound/seq_oss.h b/include/sound/seq_oss.h
new file mode 100644
index 000000000000..bd7e57322ab6
--- /dev/null
+++ b/include/sound/seq_oss.h
@@ -0,0 +1,102 @@
1#ifndef __SOUND_SEQ_OSS_H
2#define __SOUND_SEQ_OSS_H
3
4/*
5 * OSS compatible sequencer driver
6 *
7 * Copyright (C) 1998,99 Takashi Iwai
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include "asequencer.h"
25#include "seq_kernel.h"
26
27/*
28 * type definitions
29 */
30typedef struct snd_seq_oss_arg_t snd_seq_oss_arg_t;
31typedef struct snd_seq_oss_callback_t snd_seq_oss_callback_t;
32
33/*
34 * argument structure for synthesizer operations
35 */
36struct snd_seq_oss_arg_t {
37 /* given by OSS sequencer */
38 int app_index; /* application unique index */
39 int file_mode; /* file mode - see below */
40 int seq_mode; /* sequencer mode - see below */
41
42 /* following must be initialized in open callback */
43 snd_seq_addr_t addr; /* opened port address */
44 void *private_data; /* private data for lowlevel drivers */
45
46 /* note-on event passing mode: initially given by OSS seq,
47 * but configurable by drivers - see below
48 */
49 int event_passing;
50};
51
52
53/*
54 * synthesizer operation callbacks
55 */
56struct snd_seq_oss_callback_t {
57 struct module *owner;
58 int (*open)(snd_seq_oss_arg_t *p, void *closure);
59 int (*close)(snd_seq_oss_arg_t *p);
60 int (*ioctl)(snd_seq_oss_arg_t *p, unsigned int cmd, unsigned long arg);
61 int (*load_patch)(snd_seq_oss_arg_t *p, int format, const char __user *buf, int offs, int count);
62 int (*reset)(snd_seq_oss_arg_t *p);
63 int (*raw_event)(snd_seq_oss_arg_t *p, unsigned char *data);
64};
65
66/* flag: file_mode */
67#define SNDRV_SEQ_OSS_FILE_ACMODE 3
68#define SNDRV_SEQ_OSS_FILE_READ 1
69#define SNDRV_SEQ_OSS_FILE_WRITE 2
70#define SNDRV_SEQ_OSS_FILE_NONBLOCK 4
71
72/* flag: seq_mode */
73#define SNDRV_SEQ_OSS_MODE_SYNTH 0
74#define SNDRV_SEQ_OSS_MODE_MUSIC 1
75
76/* flag: event_passing */
77#define SNDRV_SEQ_OSS_PROCESS_EVENTS 0 /* key == 255 is processed as velocity change */
78#define SNDRV_SEQ_OSS_PASS_EVENTS 1 /* pass all events to callback */
79#define SNDRV_SEQ_OSS_PROCESS_KEYPRESS 2 /* key >= 128 will be processed as key-pressure */
80
81/* default control rate: fixed */
82#define SNDRV_SEQ_OSS_CTRLRATE 100
83
84/* default max queue length: configurable by module option */
85#define SNDRV_SEQ_OSS_MAX_QLEN 1024
86
87
88/*
89 * data pointer to snd_seq_register_device
90 */
91typedef struct snd_seq_oss_reg {
92 int type;
93 int subtype;
94 int nvoices;
95 snd_seq_oss_callback_t oper;
96 void *private_data;
97} snd_seq_oss_reg_t;
98
99/* device id */
100#define SNDRV_SEQ_DEV_ID_OSS "seq-oss"
101
102#endif /* __SOUND_SEQ_OSS_H */
diff --git a/include/sound/seq_oss_legacy.h b/include/sound/seq_oss_legacy.h
new file mode 100644
index 000000000000..e66269ff9a44
--- /dev/null
+++ b/include/sound/seq_oss_legacy.h
@@ -0,0 +1,31 @@
1#ifndef __SOUND_SEQ_OSS_LEGACY_H
2#define __SOUND_SEQ_OSS_LEGACY_H
3
4/*
5 * OSS compatible macro definitions
6 *
7 * Copyright (C) 2000 Abramo Bagnara <abramo@alsa-project.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/soundcard.h>
25
26#ifndef SAMPLE_TYPE_AWE32
27#define SAMPLE_TYPE_AWE32 0x20
28#endif
29
30#endif /* __SOUND_SEQ_OSS_LEGACY_H */
31
diff --git a/include/sound/seq_virmidi.h b/include/sound/seq_virmidi.h
new file mode 100644
index 000000000000..cf4e2388103f
--- /dev/null
+++ b/include/sound/seq_virmidi.h
@@ -0,0 +1,84 @@
1#ifndef __SOUND_SEQ_VIRMIDI_H
2#define __SOUND_SEQ_VIRMIDI_H
3
4/*
5 * Virtual Raw MIDI client on Sequencer
6 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>,
7 * Jaroslav Kysela <perex@suse.cz>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "rawmidi.h"
26#include "seq_midi_event.h"
27
28typedef struct _snd_virmidi_dev snd_virmidi_dev_t;
29
30/*
31 * device file instance:
32 * This instance is created at each time the midi device file is
33 * opened. Each instance has its own input buffer and MIDI parser
34 * (buffer), and is associated with the device instance.
35 */
36typedef struct _snd_virmidi {
37 struct list_head list;
38 int seq_mode;
39 int client;
40 int port;
41 unsigned int trigger: 1;
42 snd_midi_event_t *parser;
43 snd_seq_event_t event;
44 snd_virmidi_dev_t *rdev;
45 snd_rawmidi_substream_t *substream;
46} snd_virmidi_t;
47
48#define SNDRV_VIRMIDI_SUBSCRIBE (1<<0)
49#define SNDRV_VIRMIDI_USE (1<<1)
50
51/*
52 * device record:
53 * Each virtual midi device has one device instance. It contains
54 * common information and the linked-list of opened files,
55 */
56struct _snd_virmidi_dev {
57 snd_card_t *card; /* associated card */
58 snd_rawmidi_t *rmidi; /* rawmidi device */
59 int seq_mode; /* SNDRV_VIRMIDI_XXX */
60 int device; /* sequencer device */
61 int client; /* created/attached client */
62 int port; /* created/attached port */
63 unsigned int flags; /* SNDRV_VIRMIDI_* */
64 rwlock_t filelist_lock;
65 struct list_head filelist;
66};
67
68/* sequencer mode:
69 * ATTACH = input/output events from midi device are routed to the
70 * attached sequencer port. sequencer port is not created
71 * by virmidi itself.
72 * the input to rawmidi must be processed by passing the
73 * incoming events via snd_virmidi_receive()
74 * DISPATCH = input/output events are routed to subscribers.
75 * sequencer port is created in virmidi.
76 */
77#define SNDRV_VIRMIDI_SEQ_NONE 0
78#define SNDRV_VIRMIDI_SEQ_ATTACH 1
79#define SNDRV_VIRMIDI_SEQ_DISPATCH 2
80
81int snd_virmidi_new(snd_card_t *card, int device, snd_rawmidi_t **rrmidi);
82int snd_virmidi_receive(snd_rawmidi_t *rmidi, snd_seq_event_t *ev);
83
84#endif /* __SOUND_SEQ_VIRMIDI */
diff --git a/include/sound/sfnt_info.h b/include/sound/sfnt_info.h
new file mode 100644
index 000000000000..674585f88a31
--- /dev/null
+++ b/include/sound/sfnt_info.h
@@ -0,0 +1,214 @@
1#ifndef __SOUND_SFNT_INFO_H
2#define __SOUND_SFNT_INFO_H
3
4/*
5 * Patch record compatible with AWE driver on OSS
6 *
7 * Copyright (C) 1999-2000 Takashi Iwai
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <sound/asound.h>
26
27/*
28 * patch information record
29 */
30
31#ifdef SNDRV_BIG_ENDIAN
32#define SNDRV_OSS_PATCHKEY(id) (0xfd00|id)
33#else
34#define SNDRV_OSS_PATCHKEY(id) ((id<<8)|0xfd)
35#endif
36
37/* patch interface header: 16 bytes */
38typedef struct soundfont_patch_info_t {
39 unsigned short key; /* use the key below */
40#define SNDRV_OSS_SOUNDFONT_PATCH SNDRV_OSS_PATCHKEY(0x07)
41
42 short device_no; /* synthesizer number */
43 unsigned short sf_id; /* file id (should be zero) */
44 short optarg; /* optional argument */
45 int len; /* data length (without this header) */
46
47 short type; /* patch operation type */
48#define SNDRV_SFNT_LOAD_INFO 0 /* awe_voice_rec */
49#define SNDRV_SFNT_LOAD_DATA 1 /* awe_sample_info */
50#define SNDRV_SFNT_OPEN_PATCH 2 /* awe_open_parm */
51#define SNDRV_SFNT_CLOSE_PATCH 3 /* none */
52 /* 4 is obsolete */
53#define SNDRV_SFNT_REPLACE_DATA 5 /* awe_sample_info (optarg=#channels)*/
54#define SNDRV_SFNT_MAP_PRESET 6 /* awe_voice_map */
55 /* 7 is not used */
56#define SNDRV_SFNT_PROBE_DATA 8 /* optarg=sample */
57#define SNDRV_SFNT_REMOVE_INFO 9 /* optarg=(bank<<8)|instr */
58
59 short reserved; /* word alignment data */
60
61 /* the actual patch data begins after this */
62} soundfont_patch_info_t;
63
64
65/*
66 * open patch
67 */
68
69#define SNDRV_SFNT_PATCH_NAME_LEN 32
70
71typedef struct soundfont_open_parm_t {
72 unsigned short type; /* sample type */
73#define SNDRV_SFNT_PAT_TYPE_MISC 0
74#define SNDRV_SFNT_PAT_TYPE_GUS 6
75#define SNDRV_SFNT_PAT_TYPE_MAP 7
76#define SNDRV_SFNT_PAT_LOCKED 0x100 /* lock the samples */
77#define SNDRV_SFNT_PAT_SHARED 0x200 /* sample is shared */
78
79 short reserved;
80 char name[SNDRV_SFNT_PATCH_NAME_LEN];
81} soundfont_open_parm_t;
82
83
84/*
85 * raw voice information record
86 */
87
88/* wave table envelope & effect parameters to control EMU8000 */
89typedef struct soundfont_voice_parm_t {
90 unsigned short moddelay; /* modulation delay (0x8000) */
91 unsigned short modatkhld; /* modulation attack & hold time (0x7f7f) */
92 unsigned short moddcysus; /* modulation decay & sustain (0x7f7f) */
93 unsigned short modrelease; /* modulation release time (0x807f) */
94 short modkeyhold, modkeydecay; /* envelope change per key (not used) */
95 unsigned short voldelay; /* volume delay (0x8000) */
96 unsigned short volatkhld; /* volume attack & hold time (0x7f7f) */
97 unsigned short voldcysus; /* volume decay & sustain (0x7f7f) */
98 unsigned short volrelease; /* volume release time (0x807f) */
99 short volkeyhold, volkeydecay; /* envelope change per key (not used) */
100 unsigned short lfo1delay; /* LFO1 delay (0x8000) */
101 unsigned short lfo2delay; /* LFO2 delay (0x8000) */
102 unsigned short pefe; /* modulation pitch & cutoff (0x0000) */
103 unsigned short fmmod; /* LFO1 pitch & cutoff (0x0000) */
104 unsigned short tremfrq; /* LFO1 volume & freq (0x0000) */
105 unsigned short fm2frq2; /* LFO2 pitch & freq (0x0000) */
106 unsigned char cutoff; /* initial cutoff (0xff) */
107 unsigned char filterQ; /* initial filter Q [0-15] (0x0) */
108 unsigned char chorus; /* chorus send (0x00) */
109 unsigned char reverb; /* reverb send (0x00) */
110 unsigned short reserved[4]; /* not used */
111} soundfont_voice_parm_t;
112
113
114/* wave table parameters: 92 bytes */
115typedef struct soundfont_voice_info_t {
116 unsigned short sf_id; /* file id (should be zero) */
117 unsigned short sample; /* sample id */
118 int start, end; /* sample offset correction */
119 int loopstart, loopend; /* loop offset correction */
120 short rate_offset; /* sample rate pitch offset */
121 unsigned short mode; /* sample mode */
122#define SNDRV_SFNT_MODE_ROMSOUND 0x8000
123#define SNDRV_SFNT_MODE_STEREO 1
124#define SNDRV_SFNT_MODE_LOOPING 2
125#define SNDRV_SFNT_MODE_NORELEASE 4 /* obsolete */
126#define SNDRV_SFNT_MODE_INIT_PARM 8
127
128 short root; /* midi root key */
129 short tune; /* pitch tuning (in cents) */
130 unsigned char low, high; /* key note range */
131 unsigned char vellow, velhigh; /* velocity range */
132 signed char fixkey, fixvel; /* fixed key, velocity */
133 signed char pan, fixpan; /* panning, fixed panning */
134 short exclusiveClass; /* exclusive class (0 = none) */
135 unsigned char amplitude; /* sample volume (127 max) */
136 unsigned char attenuation; /* attenuation (0.375dB) */
137 short scaleTuning; /* pitch scale tuning(%), normally 100 */
138 soundfont_voice_parm_t parm; /* voice envelope parameters */
139 unsigned short sample_mode; /* sample mode_flag (set by driver) */
140} soundfont_voice_info_t;
141
142
143/* instrument info header: 4 bytes */
144typedef struct soundfont_voice_rec_hdr_t {
145 unsigned char bank; /* midi bank number */
146 unsigned char instr; /* midi preset number */
147 char nvoices; /* number of voices */
148 char write_mode; /* write mode; normally 0 */
149#define SNDRV_SFNT_WR_APPEND 0 /* append anyway */
150#define SNDRV_SFNT_WR_EXCLUSIVE 1 /* skip if already exists */
151#define SNDRV_SFNT_WR_REPLACE 2 /* replace if already exists */
152} soundfont_voice_rec_hdr_t;
153
154
155/*
156 * sample wave information
157 */
158
159/* wave table sample header: 32 bytes */
160typedef struct soundfont_sample_info_t {
161 unsigned short sf_id; /* file id (should be zero) */
162 unsigned short sample; /* sample id */
163 int start, end; /* start & end offset */
164 int loopstart, loopend; /* loop start & end offset */
165 int size; /* size (0 = ROM) */
166 short dummy; /* not used */
167 unsigned short mode_flags; /* mode flags */
168#define SNDRV_SFNT_SAMPLE_8BITS 1 /* wave data is 8bits */
169#define SNDRV_SFNT_SAMPLE_UNSIGNED 2 /* wave data is unsigned */
170#define SNDRV_SFNT_SAMPLE_NO_BLANK 4 /* no blank loop is attached */
171#define SNDRV_SFNT_SAMPLE_SINGLESHOT 8 /* single-shot w/o loop */
172#define SNDRV_SFNT_SAMPLE_BIDIR_LOOP 16 /* bidirectional looping */
173#define SNDRV_SFNT_SAMPLE_STEREO_LEFT 32 /* stereo left sound */
174#define SNDRV_SFNT_SAMPLE_STEREO_RIGHT 64 /* stereo right sound */
175#define SNDRV_SFNT_SAMPLE_REVERSE_LOOP 128 /* reverse looping */
176 unsigned int truesize; /* used memory size (set by driver) */
177} soundfont_sample_info_t;
178
179
180/*
181 * voice preset mapping (aliasing)
182 */
183
184typedef struct soundfont_voice_map_t {
185 int map_bank, map_instr, map_key; /* key = -1 means all keys */
186 int src_bank, src_instr, src_key;
187} soundfont_voice_map_t;
188
189
190/*
191 * ioctls for hwdep
192 */
193
194#define SNDRV_EMUX_HWDEP_NAME "Emux WaveTable"
195
196#define SNDRV_EMUX_VERSION ((1 << 16) | (0 << 8) | 0) /* 1.0.0 */
197
198struct sndrv_emux_misc_mode {
199 int port; /* -1 = all */
200 int mode;
201 int value;
202 int value2; /* reserved */
203};
204
205enum {
206 SNDRV_EMUX_IOCTL_VERSION = _IOR('H', 0x80, unsigned int),
207 SNDRV_EMUX_IOCTL_LOAD_PATCH = _IOWR('H', 0x81, soundfont_patch_info_t),
208 SNDRV_EMUX_IOCTL_RESET_SAMPLES = _IO('H', 0x82),
209 SNDRV_EMUX_IOCTL_REMOVE_LAST_SAMPLES = _IO('H', 0x83),
210 SNDRV_EMUX_IOCTL_MEM_AVAIL = _IOW('H', 0x84, int),
211 SNDRV_EMUX_IOCTL_MISC_MODE = _IOWR('H', 0x84, struct sndrv_emux_misc_mode),
212};
213
214#endif /* __SOUND_SFNT_INFO_H */
diff --git a/include/sound/snd_wavefront.h b/include/sound/snd_wavefront.h
new file mode 100644
index 000000000000..4b0b2b9370b9
--- /dev/null
+++ b/include/sound/snd_wavefront.h
@@ -0,0 +1,141 @@
1#ifndef __SOUND_SND_WAVEFRONT_H__
2#define __SOUND_SND_WAVEFRONT_H__
3
4#include "cs4231.h"
5#include "mpu401.h"
6#include "hwdep.h"
7#include "rawmidi.h"
8#include "wavefront.h" /* generic OSS/ALSA/user-level wavefront header */
9
10/* MIDI interface */
11
12struct _snd_wavefront_midi;
13struct _snd_wavefront_card;
14struct _snd_wavefront;
15
16typedef struct _snd_wavefront_midi snd_wavefront_midi_t;
17typedef struct _snd_wavefront_card snd_wavefront_card_t;
18typedef struct _snd_wavefront snd_wavefront_t;
19
20typedef enum { internal_mpu = 0, external_mpu = 1 } snd_wavefront_mpu_id;
21
22struct _snd_wavefront_midi {
23 unsigned long base; /* I/O port address */
24 char isvirtual; /* doing virtual MIDI stuff ? */
25 char istimer; /* timer is used */
26 snd_wavefront_mpu_id output_mpu; /* most-recently-used */
27 snd_wavefront_mpu_id input_mpu; /* most-recently-used */
28 unsigned int mode[2]; /* MPU401_MODE_XXX */
29 snd_rawmidi_substream_t *substream_output[2];
30 snd_rawmidi_substream_t *substream_input[2];
31 struct timer_list timer;
32 spinlock_t open;
33 spinlock_t virtual; /* protects isvirtual */
34};
35
36#define OUTPUT_READY 0x40
37#define INPUT_AVAIL 0x80
38#define MPU_ACK 0xFE
39#define UART_MODE_ON 0x3F
40
41extern snd_rawmidi_ops_t snd_wavefront_midi_output;
42extern snd_rawmidi_ops_t snd_wavefront_midi_input;
43
44extern void snd_wavefront_midi_enable_virtual (snd_wavefront_card_t *);
45extern void snd_wavefront_midi_disable_virtual (snd_wavefront_card_t *);
46extern void snd_wavefront_midi_interrupt (snd_wavefront_card_t *);
47extern int snd_wavefront_midi_start (snd_wavefront_card_t *);
48
49struct _snd_wavefront {
50 unsigned long irq; /* "you were one, one of the few ..." */
51 unsigned long base; /* low i/o port address */
52 struct resource *res_base; /* i/o port resource allocation */
53
54#define mpu_data_port base
55#define mpu_command_port base + 1 /* write semantics */
56#define mpu_status_port base + 1 /* read semantics */
57#define data_port base + 2
58#define status_port base + 3 /* read semantics */
59#define control_port base + 3 /* write semantics */
60#define block_port base + 4 /* 16 bit, writeonly */
61#define last_block_port base + 6 /* 16 bit, writeonly */
62
63 /* FX ports. These are mapped through the ICS2115 to the YS225.
64 The ICS2115 takes care of flipping the relevant pins on the
65 YS225 so that access to each of these ports does the right
66 thing. Note: these are NOT documented by Turtle Beach.
67 */
68
69#define fx_status base + 8
70#define fx_op base + 8
71#define fx_lcr base + 9
72#define fx_dsp_addr base + 0xa
73#define fx_dsp_page base + 0xb
74#define fx_dsp_lsb base + 0xc
75#define fx_dsp_msb base + 0xd
76#define fx_mod_addr base + 0xe
77#define fx_mod_data base + 0xf
78
79 volatile int irq_ok; /* set by interrupt handler */
80 volatile int irq_cnt; /* ditto */
81 char debug; /* debugging flags */
82 int freemem; /* installed RAM, in bytes */
83
84 char fw_version[2]; /* major = [0], minor = [1] */
85 char hw_version[2]; /* major = [0], minor = [1] */
86 char israw; /* needs Motorola microcode */
87 char has_fx; /* has FX processor (Tropez+) */
88 char prog_status[WF_MAX_PROGRAM]; /* WF_SLOT_* */
89 char patch_status[WF_MAX_PATCH]; /* WF_SLOT_* */
90 char sample_status[WF_MAX_SAMPLE]; /* WF_ST_* | WF_SLOT_* */
91 int samples_used; /* how many */
92 char interrupts_are_midi; /* h/w MPU interrupts enabled ? */
93 char rom_samples_rdonly; /* can we write on ROM samples */
94 spinlock_t irq_lock;
95 wait_queue_head_t interrupt_sleeper;
96 snd_wavefront_midi_t midi; /* ICS2115 MIDI interface */
97};
98
99struct _snd_wavefront_card {
100 snd_wavefront_t wavefront;
101#ifdef CONFIG_PNP
102 struct pnp_dev *wss;
103 struct pnp_dev *ctrl;
104 struct pnp_dev *mpu;
105 struct pnp_dev *synth;
106#endif /* CONFIG_PNP */
107};
108
109extern void snd_wavefront_internal_interrupt (snd_wavefront_card_t *card);
110extern int snd_wavefront_detect_irq (snd_wavefront_t *dev) ;
111extern int snd_wavefront_check_irq (snd_wavefront_t *dev, int irq);
112extern int snd_wavefront_restart (snd_wavefront_t *dev);
113extern int snd_wavefront_start (snd_wavefront_t *dev);
114extern int snd_wavefront_detect (snd_wavefront_card_t *card);
115extern int snd_wavefront_config_midi (snd_wavefront_t *dev) ;
116extern int snd_wavefront_cmd (snd_wavefront_t *, int, unsigned char *,
117 unsigned char *);
118
119extern int snd_wavefront_synth_ioctl (snd_hwdep_t *,
120 struct file *,
121 unsigned int cmd,
122 unsigned long arg);
123extern int snd_wavefront_synth_open (snd_hwdep_t *, struct file *);
124extern int snd_wavefront_synth_release (snd_hwdep_t *, struct file *);
125
126/* FX processor - see also yss225.[ch] */
127
128extern int snd_wavefront_fx_start (snd_wavefront_t *);
129extern int snd_wavefront_fx_detect (snd_wavefront_t *);
130extern int snd_wavefront_fx_ioctl (snd_hwdep_t *,
131 struct file *,
132 unsigned int cmd,
133 unsigned long arg);
134extern int snd_wavefront_fx_open (snd_hwdep_t *, struct file *);
135extern int snd_wavefront_fx_release (snd_hwdep_t *, struct file *);
136
137/* prefix in all snd_printk() delivered messages */
138
139#define LOGNAME "WaveFront: "
140
141#endif /* __SOUND_SND_WAVEFRONT_H__ */
diff --git a/include/sound/soundfont.h b/include/sound/soundfont.h
new file mode 100644
index 000000000000..c992958f5e3c
--- /dev/null
+++ b/include/sound/soundfont.h
@@ -0,0 +1,130 @@
1#ifndef __SOUND_SOUNDFONT_H
2#define __SOUND_SOUNDFONT_H
3
4/*
5 * Soundfont defines and definitions.
6 *
7 * Copyright (C) 1999 Steve Ratcliffe
8 * Copyright (c) 1999-2000 Takashi iwai <tiwai@suse.de>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#include "sfnt_info.h"
26#include "util_mem.h"
27
28#define SF_MAX_INSTRUMENTS 128 /* maximum instrument number */
29#define SF_MAX_PRESETS 256 /* drums are mapped from 128 to 256 */
30#define SF_IS_DRUM_BANK(z) ((z) == 128)
31
32typedef struct snd_sf_zone {
33 struct snd_sf_zone *next; /* Link to next */
34 unsigned char bank; /* Midi bank for this zone */
35 unsigned char instr; /* Midi program for this zone */
36 unsigned char mapped; /* True if mapped to something else */
37
38 soundfont_voice_info_t v; /* All the soundfont parameters */
39 int counter;
40 struct snd_sf_sample *sample; /* Link to sample */
41
42 /* The following deals with preset numbers (programs) */
43 struct snd_sf_zone *next_instr; /* Next zone of this instrument */
44 struct snd_sf_zone *next_zone; /* Next zone in play list */
45} snd_sf_zone_t;
46
47typedef struct snd_sf_sample {
48 soundfont_sample_info_t v;
49 int counter;
50 snd_util_memblk_t *block; /* allocated data block */
51 struct snd_sf_sample *next;
52} snd_sf_sample_t;
53
54/*
55 * This represents all the information relating to a soundfont.
56 */
57typedef struct snd_soundfont {
58 struct snd_soundfont *next; /* Link to next */
59 /*struct snd_soundfont *prev;*/ /* Link to previous */
60 short id; /* file id */
61 short type; /* font type */
62 unsigned char name[SNDRV_SFNT_PATCH_NAME_LEN]; /* identifier */
63 snd_sf_zone_t *zones; /* Font information */
64 snd_sf_sample_t *samples; /* The sample headers */
65} snd_soundfont_t;
66
67/*
68 * Type of the sample access callback
69 */
70typedef int (*snd_sf_sample_new_t)(void *private_data, snd_sf_sample_t *sp,
71 snd_util_memhdr_t *hdr, const void __user *buf, long count);
72typedef int (*snd_sf_sample_free_t)(void *private_data, snd_sf_sample_t *sp,
73 snd_util_memhdr_t *hdr);
74typedef void (*snd_sf_sample_reset_t)(void *private);
75
76typedef struct snd_sf_callback {
77 void *private_data;
78 snd_sf_sample_new_t sample_new;
79 snd_sf_sample_free_t sample_free;
80 snd_sf_sample_reset_t sample_reset;
81} snd_sf_callback_t;
82
83/*
84 * List of soundfonts.
85 */
86typedef struct snd_sf_list {
87 snd_soundfont_t *currsf; /* The currently open soundfont */
88 int open_client; /* client pointer for lock */
89 int mem_used; /* used memory size */
90 snd_sf_zone_t *presets[SF_MAX_PRESETS];
91 snd_soundfont_t *fonts; /* The list of soundfonts */
92 int fonts_size; /* number of fonts allocated */
93 int zone_counter; /* last allocated time for zone */
94 int sample_counter; /* last allocated time for sample */
95 int zone_locked; /* locked time for zone */
96 int sample_locked; /* locked time for sample */
97 snd_sf_callback_t callback; /* callback functions */
98 int presets_locked;
99 struct semaphore presets_mutex;
100 spinlock_t lock;
101 snd_util_memhdr_t *memhdr;
102} snd_sf_list_t;
103
104/* Prototypes for soundfont.c */
105int snd_soundfont_load(snd_sf_list_t *sflist, const void __user *data, long count, int client);
106int snd_soundfont_load_guspatch(snd_sf_list_t *sflist, const char __user *data,
107 long count, int client);
108int snd_soundfont_close_check(snd_sf_list_t *sflist, int client);
109
110snd_sf_list_t *snd_sf_new(snd_sf_callback_t *callback, snd_util_memhdr_t *hdr);
111void snd_sf_free(snd_sf_list_t *sflist);
112
113int snd_soundfont_remove_samples(snd_sf_list_t *sflist);
114int snd_soundfont_remove_unlocked(snd_sf_list_t *sflist);
115
116int snd_soundfont_search_zone(snd_sf_list_t *sflist, int *notep, int vel,
117 int preset, int bank,
118 int def_preset, int def_bank,
119 snd_sf_zone_t **table, int max_layers);
120
121/* Parameter conversions */
122int snd_sf_calc_parm_hold(int msec);
123int snd_sf_calc_parm_attack(int msec);
124int snd_sf_calc_parm_decay(int msec);
125#define snd_sf_calc_parm_delay(msec) (0x8000 - (msec) * 1000 / 725);
126extern int snd_sf_vol_table[128];
127int snd_sf_linear_to_log(unsigned int amount, int offset, int ratio);
128
129
130#endif /* __SOUND_SOUNDFONT_H */
diff --git a/include/sound/sscape_ioctl.h b/include/sound/sscape_ioctl.h
new file mode 100644
index 000000000000..0d8885969c64
--- /dev/null
+++ b/include/sound/sscape_ioctl.h
@@ -0,0 +1,21 @@
1#ifndef SSCAPE_IOCTL_H
2#define SSCAPE_IOCTL_H
3
4
5struct sscape_bootblock
6{
7 unsigned char code[256];
8 unsigned version;
9};
10
11#define SSCAPE_MICROCODE_SIZE 65536
12
13struct sscape_microcode
14{
15 unsigned char __user *code;
16};
17
18#define SND_SSCAPE_LOAD_BOOTB _IOWR('P', 100, struct sscape_bootblock)
19#define SND_SSCAPE_LOAD_MCODE _IOW ('P', 101, struct sscape_microcode)
20
21#endif
diff --git a/include/sound/tea575x-tuner.h b/include/sound/tea575x-tuner.h
new file mode 100644
index 000000000000..ad3c3be33c03
--- /dev/null
+++ b/include/sound/tea575x-tuner.h
@@ -0,0 +1,53 @@
1#ifndef __SOUND_TEA575X_TUNER_H
2#define __SOUND_TEA575X_TUNER_H
3
4/*
5 * ALSA driver for TEA5757/5759 Philips AM/FM tuner chips
6 *
7 * Copyright (c) 2004 Jaroslav Kysela <perex@suse.cz>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/videodev.h>
26
27typedef struct snd_tea575x tea575x_t;
28
29struct snd_tea575x_ops {
30 void (*write)(tea575x_t *tea, unsigned int val);
31 unsigned int (*read)(tea575x_t *tea);
32};
33
34struct snd_tea575x {
35 snd_card_t *card;
36 struct video_device vd; /* video device */
37#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
38 struct file_operations fops;
39#endif
40 int dev_nr; /* requested device number + 1 */
41 int vd_registered; /* video device is registered */
42 int tea5759; /* 5759 chip is present */
43 unsigned int freq_fixup; /* crystal onboard */
44 unsigned int val; /* hw value */
45 unsigned long freq; /* frequency */
46 struct snd_tea575x_ops *ops;
47 void *private_data;
48};
49
50void snd_tea575x_init(tea575x_t *tea);
51void snd_tea575x_exit(tea575x_t *tea);
52
53#endif /* __SOUND_TEA575X_TUNER_H */
diff --git a/include/sound/tea6330t.h b/include/sound/tea6330t.h
new file mode 100644
index 000000000000..3896c0a50907
--- /dev/null
+++ b/include/sound/tea6330t.h
@@ -0,0 +1,42 @@
1#ifndef __SOUND_TEA6330T_H
2#define __SOUND_TEA6330T_H
3
4/*
5 * Routines for control of TEA6330T circuit.
6 * Sound fader control circuit for car radios.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 */
24
25#include "control.h"
26#include "i2c.h" /* generic i2c support */
27
28typedef struct {
29 snd_i2c_device_t *device;
30 snd_i2c_bus_t *bus;
31 int equalizer;
32 int fader;
33 unsigned char regs[8];
34 unsigned char mleft, mright;
35 unsigned char bass, treble;
36 unsigned char max_bass, max_treble;
37} tea6330t_t;
38
39extern int snd_tea6330t_detect(snd_i2c_bus_t *bus, int equalizer);
40extern int snd_tea6330t_update_mixer(snd_card_t * card, snd_i2c_bus_t * bus, int equalizer, int fader);
41
42#endif /* __SOUND_TEA6330T_H */
diff --git a/include/sound/timer.h b/include/sound/timer.h
new file mode 100644
index 000000000000..57fde990606e
--- /dev/null
+++ b/include/sound/timer.h
@@ -0,0 +1,157 @@
1#ifndef __SOUND_TIMER_H
2#define __SOUND_TIMER_H
3
4/*
5 * Timer abstract layer
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
7 * Abramo Bagnara <abramo@alsa-project.org>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include <sound/asound.h>
27#include <linux/interrupt.h>
28
29typedef enum sndrv_timer_class snd_timer_class_t;
30typedef enum sndrv_timer_slave_class snd_timer_slave_class_t;
31typedef enum sndrv_timer_global snd_timer_global_t;
32typedef struct sndrv_timer_id snd_timer_id_t;
33typedef struct sndrv_timer_ginfo snd_timer_ginfo_t;
34typedef struct sndrv_timer_gparams snd_timer_gparams_t;
35typedef struct sndrv_timer_gstatus snd_timer_gstatus_t;
36typedef struct sndrv_timer_select snd_timer_select_t;
37typedef struct sndrv_timer_info snd_timer_info_t;
38typedef struct sndrv_timer_params snd_timer_params_t;
39typedef struct sndrv_timer_status snd_timer_status_t;
40typedef struct sndrv_timer_read snd_timer_read_t;
41typedef struct sndrv_timer_tread snd_timer_tread_t;
42
43#define snd_timer_chip(timer) ((timer)->private_data)
44
45#define SNDRV_TIMER_DEVICES 16
46
47#define SNDRV_TIMER_DEV_FLG_PCM 0x10000000
48
49#define SNDRV_TIMER_HW_AUTO 0x00000001 /* auto trigger is supported */
50#define SNDRV_TIMER_HW_STOP 0x00000002 /* call stop before start */
51#define SNDRV_TIMER_HW_SLAVE 0x00000004 /* only slave timer (variable resolution) */
52#define SNDRV_TIMER_HW_FIRST 0x00000008 /* first tick can be incomplete */
53#define SNDRV_TIMER_HW_TASKLET 0x00000010 /* timer is called from tasklet */
54
55#define SNDRV_TIMER_IFLG_SLAVE 0x00000001
56#define SNDRV_TIMER_IFLG_RUNNING 0x00000002
57#define SNDRV_TIMER_IFLG_START 0x00000004
58#define SNDRV_TIMER_IFLG_AUTO 0x00000008 /* auto restart */
59#define SNDRV_TIMER_IFLG_FAST 0x00000010 /* fast callback (do not use tasklet) */
60#define SNDRV_TIMER_IFLG_CALLBACK 0x00000020 /* timer callback is active */
61#define SNDRV_TIMER_IFLG_EXCLUSIVE 0x00000040 /* exclusive owner - no more instances */
62#define SNDRV_TIMER_IFLG_EARLY_EVENT 0x00000080 /* write early event to the poll queue */
63
64#define SNDRV_TIMER_FLG_CHANGE 0x00000001
65#define SNDRV_TIMER_FLG_RESCHED 0x00000002 /* need reschedule */
66
67typedef void (*snd_timer_callback_t) (snd_timer_instance_t * timeri, unsigned long ticks, unsigned long resolution);
68typedef void (*snd_timer_ccallback_t) (snd_timer_instance_t * timeri, enum sndrv_timer_event event,
69 struct timespec * tstamp, unsigned long resolution);
70
71struct _snd_timer_hardware {
72 /* -- must be filled with low-level driver */
73 unsigned int flags; /* various flags */
74 unsigned long resolution; /* average timer resolution for one tick in nsec */
75 unsigned long resolution_min; /* minimal resolution */
76 unsigned long resolution_max; /* maximal resolution */
77 unsigned long ticks; /* max timer ticks per interrupt */
78 /* -- low-level functions -- */
79 int (*open) (snd_timer_t * timer);
80 int (*close) (snd_timer_t * timer);
81 unsigned long (*c_resolution) (snd_timer_t * timer);
82 int (*start) (snd_timer_t * timer);
83 int (*stop) (snd_timer_t * timer);
84 int (*set_period) (snd_timer_t * timer, unsigned long period_num, unsigned long period_den);
85 int (*precise_resolution) (snd_timer_t * timer, unsigned long *num, unsigned long *den);
86};
87
88struct _snd_timer {
89 snd_timer_class_t tmr_class;
90 snd_card_t *card;
91 int tmr_device;
92 int tmr_subdevice;
93 char id[64];
94 char name[80];
95 unsigned int flags;
96 int running; /* running instances */
97 unsigned long sticks; /* schedule ticks */
98 void *private_data;
99 void (*private_free) (snd_timer_t *timer);
100 struct _snd_timer_hardware hw;
101 spinlock_t lock;
102 struct list_head device_list;
103 struct list_head open_list_head;
104 struct list_head active_list_head;
105 struct list_head ack_list_head;
106 struct list_head sack_list_head; /* slow ack list head */
107 struct tasklet_struct task_queue;
108};
109
110struct _snd_timer_instance {
111 snd_timer_t * timer;
112 char *owner;
113 unsigned int flags;
114 void *private_data;
115 void (*private_free) (snd_timer_instance_t *ti);
116 snd_timer_callback_t callback;
117 snd_timer_ccallback_t ccallback;
118 void *callback_data;
119 unsigned long ticks; /* auto-load ticks when expired */
120 unsigned long cticks; /* current ticks */
121 unsigned long pticks; /* accumulated ticks for callback */
122 unsigned long resolution; /* current resolution for tasklet */
123 unsigned long lost; /* lost ticks */
124 snd_timer_slave_class_t slave_class;
125 unsigned int slave_id;
126 struct list_head open_list;
127 struct list_head active_list;
128 struct list_head ack_list;
129 struct list_head slave_list_head;
130 struct list_head slave_active_head;
131 snd_timer_instance_t *master;
132};
133
134/*
135 * Registering
136 */
137
138extern int snd_timer_new(snd_card_t *card, char *id, snd_timer_id_t *tid, snd_timer_t ** rtimer);
139extern void snd_timer_notify(snd_timer_t *timer, enum sndrv_timer_event event, struct timespec *tstamp);
140extern int snd_timer_global_new(char *id, int device, snd_timer_t **rtimer);
141extern int snd_timer_global_free(snd_timer_t *timer);
142extern int snd_timer_global_register(snd_timer_t *timer);
143extern int snd_timer_global_unregister(snd_timer_t *timer);
144
145extern int snd_timer_open(snd_timer_instance_t ** ti, char *owner, snd_timer_id_t *tid, unsigned int slave_id);
146extern int snd_timer_close(snd_timer_instance_t * timeri);
147extern unsigned long snd_timer_resolution(snd_timer_instance_t * timeri);
148extern int snd_timer_start(snd_timer_instance_t * timeri, unsigned int ticks);
149extern int snd_timer_stop(snd_timer_instance_t * timeri);
150extern int snd_timer_continue(snd_timer_instance_t * timeri);
151extern int snd_timer_pause(snd_timer_instance_t * timeri);
152
153extern void snd_timer_interrupt(snd_timer_t * timer, unsigned long ticks_left);
154
155extern unsigned int snd_timer_system_resolution(void);
156
157#endif /* __SOUND_TIMER_H */
diff --git a/include/sound/trident.h b/include/sound/trident.h
new file mode 100644
index 000000000000..f5254ec36e6a
--- /dev/null
+++ b/include/sound/trident.h
@@ -0,0 +1,479 @@
1#ifndef __SOUND_TRIDENT_H
2#define __SOUND_TRIDENT_H
3
4/*
5 * audio@tridentmicro.com
6 * Fri Feb 19 15:55:28 MST 1999
7 * Definitions for Trident 4DWave DX/NX chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include "pcm.h"
27#include "mpu401.h"
28#include "ac97_codec.h"
29#include "seq_midi_emul.h"
30#include "seq_device.h"
31#include "util_mem.h"
32//#include "ainstr_iw.h"
33//#include "ainstr_gf1.h"
34#include "ainstr_simple.h"
35
36#ifndef PCI_VENDOR_ID_TRIDENT
37#define PCI_VENDOR_ID_TRIDENT 0x1023
38#endif
39#ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_DX
40#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
41#endif
42#ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_NX
43#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
44#endif
45
46#ifndef PCI_VENDOR_ID_SI
47#define PCI_VENDOR_ID_SI 0x1039
48#endif
49#ifndef PCI_DEVICE_ID_SI_7018
50#define PCI_DEVICE_ID_SI_7018 0x7018
51#endif
52
53#define TRIDENT_DEVICE_ID_DX ((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_DX)
54#define TRIDENT_DEVICE_ID_NX ((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_NX)
55#define TRIDENT_DEVICE_ID_SI7018 ((PCI_VENDOR_ID_SI<<16)|PCI_DEVICE_ID_SI_7018)
56
57#define SNDRV_SEQ_DEV_ID_TRIDENT "trident-synth"
58
59#define SNDRV_TRIDENT_VOICE_TYPE_PCM 0
60#define SNDRV_TRIDENT_VOICE_TYPE_SYNTH 1
61#define SNDRV_TRIDENT_VOICE_TYPE_MIDI 2
62
63#define SNDRV_TRIDENT_VFLG_RUNNING (1<<0)
64
65/* TLB code constants */
66#define SNDRV_TRIDENT_PAGE_SIZE 4096
67#define SNDRV_TRIDENT_PAGE_SHIFT 12
68#define SNDRV_TRIDENT_PAGE_MASK ((1<<SNDRV_TRIDENT_PAGE_SHIFT)-1)
69#define SNDRV_TRIDENT_MAX_PAGES 4096
70
71/*
72 * Direct registers
73 */
74
75#define TRID_REG(trident, x) ((trident)->port + (x))
76
77#define ID_4DWAVE_DX 0x2000
78#define ID_4DWAVE_NX 0x2001
79
80/* Bank definitions */
81
82#define T4D_BANK_A 0
83#define T4D_BANK_B 1
84#define T4D_NUM_BANKS 2
85
86/* Register definitions */
87
88/* Global registers */
89
90enum global_control_bits {
91 CHANNEL_IDX = 0x0000003f,
92 OVERRUN_IE = 0x00000400, /* interrupt enable: capture overrun */
93 UNDERRUN_IE = 0x00000800, /* interrupt enable: playback underrun */
94 ENDLP_IE = 0x00001000, /* interrupt enable: end of buffer */
95 MIDLP_IE = 0x00002000, /* interrupt enable: middle buffer */
96 ETOG_IE = 0x00004000, /* interrupt enable: envelope toggling */
97 EDROP_IE = 0x00008000, /* interrupt enable: envelope drop */
98 BANK_B_EN = 0x00010000, /* SiS: enable bank B (64 channels) */
99 PCMIN_B_MIX = 0x00020000, /* SiS: PCM IN B mixing enable */
100 I2S_OUT_ASSIGN = 0x00040000, /* SiS: I2S Out contains surround PCM */
101 SPDIF_OUT_ASSIGN= 0x00080000, /* SiS: 0=S/PDIF L/R | 1=PCM Out FIFO */
102 MAIN_OUT_ASSIGN = 0x00100000, /* SiS: 0=PCM Out FIFO | 1=MMC Out buffer */
103};
104
105enum miscint_bits {
106 PB_UNDERRUN_IRQ = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
107 SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008,
108 OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020,
109 ENVELOPE_IRQ = 0x00000040, PB_UNDERRUN = 0x00000100,
110 REC_OVERRUN = 0x00000200, MIXER_UNDERFLOW = 0x00000400,
111 MIXER_OVERFLOW = 0x00000800, NX_SB_IRQ_DISABLE = 0x00001000,
112 ST_TARGET_REACHED = 0x00008000,
113 PB_24K_MODE = 0x00010000, ST_IRQ_EN = 0x00800000,
114 ACGPIO_IRQ = 0x01000000
115};
116
117/* T2 legacy dma control registers. */
118#define LEGACY_DMAR0 0x00 // ADR0
119#define LEGACY_DMAR4 0x04 // CNT0
120#define LEGACY_DMAR6 0x06 // CNT0 - High bits
121#define LEGACY_DMAR11 0x0b // MOD
122#define LEGACY_DMAR15 0x0f // MMR
123
124#define T4D_START_A 0x80
125#define T4D_STOP_A 0x84
126#define T4D_DLY_A 0x88
127#define T4D_SIGN_CSO_A 0x8c
128#define T4D_CSPF_A 0x90
129#define T4D_CSPF_B 0xbc
130#define T4D_CEBC_A 0x94
131#define T4D_AINT_A 0x98
132#define T4D_AINTEN_A 0x9c
133#define T4D_LFO_GC_CIR 0xa0
134#define T4D_MUSICVOL_WAVEVOL 0xa8
135#define T4D_SBDELTA_DELTA_R 0xac
136#define T4D_MISCINT 0xb0
137#define T4D_START_B 0xb4
138#define T4D_STOP_B 0xb8
139#define T4D_SBBL_SBCL 0xc0
140#define T4D_SBCTRL_SBE2R_SBDD 0xc4
141#define T4D_STIMER 0xc8
142#define T4D_AINT_B 0xd8
143#define T4D_AINTEN_B 0xdc
144#define T4D_RCI 0x70
145
146/* MPU-401 UART */
147#define T4D_MPU401_BASE 0x20
148#define T4D_MPUR0 0x20
149#define T4D_MPUR1 0x21
150#define T4D_MPUR2 0x22
151#define T4D_MPUR3 0x23
152
153/* S/PDIF Registers */
154#define NX_SPCTRL_SPCSO 0x24
155#define NX_SPLBA 0x28
156#define NX_SPESO 0x2c
157#define NX_SPCSTATUS 0x64
158
159/* Joystick */
160#define GAMEPORT_GCR 0x30
161#define GAMEPORT_MODE_ADC 0x80
162#define GAMEPORT_LEGACY 0x31
163#define GAMEPORT_AXES 0x34
164
165/* NX Specific Registers */
166#define NX_TLBC 0x6c
167
168/* Channel Registers */
169
170#define CH_START 0xe0
171
172#define CH_DX_CSO_ALPHA_FMS 0xe0
173#define CH_DX_ESO_DELTA 0xe8
174#define CH_DX_FMC_RVOL_CVOL 0xec
175
176#define CH_NX_DELTA_CSO 0xe0
177#define CH_NX_DELTA_ESO 0xe8
178#define CH_NX_ALPHA_FMS_FMC_RVOL_CVOL 0xec
179
180#define CH_LBA 0xe4
181#define CH_GVSEL_PAN_VOL_CTRL_EC 0xf0
182#define CH_EBUF1 0xf4
183#define CH_EBUF2 0xf8
184
185/* AC-97 Registers */
186
187#define DX_ACR0_AC97_W 0x40
188#define DX_ACR1_AC97_R 0x44
189#define DX_ACR2_AC97_COM_STAT 0x48
190
191#define NX_ACR0_AC97_COM_STAT 0x40
192#define NX_ACR1_AC97_W 0x44
193#define NX_ACR2_AC97_R_PRIMARY 0x48
194#define NX_ACR3_AC97_R_SECONDARY 0x4c
195
196#define SI_AC97_WRITE 0x40
197#define SI_AC97_READ 0x44
198#define SI_SERIAL_INTF_CTRL 0x48
199#define SI_AC97_GPIO 0x4c
200#define SI_ASR0 0x50
201#define SI_SPDIF_CS 0x70
202#define SI_GPIO 0x7c
203
204enum trident_nx_ac97_bits {
205 /* ACR1-3 */
206 NX_AC97_BUSY_WRITE = 0x0800,
207 NX_AC97_BUSY_READ = 0x0800,
208 NX_AC97_BUSY_DATA = 0x0400,
209 NX_AC97_WRITE_SECONDARY = 0x0100,
210 /* ACR0 */
211 NX_AC97_SECONDARY_READY = 0x0040,
212 NX_AC97_SECONDARY_RECORD = 0x0020,
213 NX_AC97_SURROUND_OUTPUT = 0x0010,
214 NX_AC97_PRIMARY_READY = 0x0008,
215 NX_AC97_PRIMARY_RECORD = 0x0004,
216 NX_AC97_PCM_OUTPUT = 0x0002,
217 NX_AC97_WARM_RESET = 0x0001
218};
219
220enum trident_dx_ac97_bits {
221 DX_AC97_BUSY_WRITE = 0x8000,
222 DX_AC97_BUSY_READ = 0x8000,
223 DX_AC97_READY = 0x0010,
224 DX_AC97_RECORD = 0x0008,
225 DX_AC97_PLAYBACK = 0x0002
226};
227
228enum sis7018_ac97_bits {
229 SI_AC97_BUSY_WRITE = 0x00008000,
230 SI_AC97_AUDIO_BUSY = 0x00004000,
231 SI_AC97_MODEM_BUSY = 0x00002000,
232 SI_AC97_BUSY_READ = 0x00008000,
233 SI_AC97_SECONDARY = 0x00000080,
234};
235
236enum serial_intf_ctrl_bits {
237 WARM_RESET = 0x00000001,
238 COLD_RESET = 0x00000002,
239 I2S_CLOCK = 0x00000004,
240 PCM_SEC_AC97 = 0x00000008,
241 AC97_DBL_RATE = 0x00000010,
242 SPDIF_EN = 0x00000020,
243 I2S_OUTPUT_EN = 0x00000040,
244 I2S_INPUT_EN = 0x00000080,
245 PCMIN = 0x00000100,
246 LINE1IN = 0x00000200,
247 MICIN = 0x00000400,
248 LINE2IN = 0x00000800,
249 HEAD_SET_IN = 0x00001000,
250 GPIOIN = 0x00002000,
251 /* 7018 spec says id = 01 but the demo board routed to 10
252 SECONDARY_ID= 0x00004000, */
253 SECONDARY_ID = 0x00004000,
254 PCMOUT = 0x00010000,
255 SURROUT = 0x00020000,
256 CENTEROUT = 0x00040000,
257 LFEOUT = 0x00080000,
258 LINE1OUT = 0x00100000,
259 LINE2OUT = 0x00200000,
260 GPIOOUT = 0x00400000,
261 SI_AC97_PRIMARY_READY = 0x01000000,
262 SI_AC97_SECONDARY_READY = 0x02000000,
263 SI_AC97_POWERDOWN = 0x04000000,
264};
265
266/* PCM defaults */
267
268#define T4D_DEFAULT_PCM_VOL 10 /* 0 - 255 */
269#define T4D_DEFAULT_PCM_PAN 0 /* 0 - 127 */
270#define T4D_DEFAULT_PCM_RVOL 127 /* 0 - 127 */
271#define T4D_DEFAULT_PCM_CVOL 127 /* 0 - 127 */
272
273typedef struct _snd_trident trident_t;
274typedef struct _snd_trident_voice snd_trident_voice_t;
275typedef struct _snd_trident_pcm_mixer snd_trident_pcm_mixer_t;
276
277typedef struct {
278 void (*sample_start)(trident_t *gus, snd_trident_voice_t *voice, snd_seq_position_t position);
279 void (*sample_stop)(trident_t *gus, snd_trident_voice_t *voice, snd_seq_stop_mode_t mode);
280 void (*sample_freq)(trident_t *gus, snd_trident_voice_t *voice, snd_seq_frequency_t freq);
281 void (*sample_volume)(trident_t *gus, snd_trident_voice_t *voice, snd_seq_ev_volume_t *volume);
282 void (*sample_loop)(trident_t *card, snd_trident_voice_t *voice, snd_seq_ev_loop_t *loop);
283 void (*sample_pos)(trident_t *card, snd_trident_voice_t *voice, snd_seq_position_t position);
284 void (*sample_private1)(trident_t *card, snd_trident_voice_t *voice, unsigned char *data);
285} snd_trident_sample_ops_t;
286
287typedef struct {
288 snd_midi_channel_set_t * chset;
289 trident_t * trident;
290 int mode; /* operation mode */
291 int client; /* sequencer client number */
292 int port; /* sequencer port number */
293 unsigned int midi_has_voices: 1;
294} snd_trident_port_t;
295
296typedef struct snd_trident_memblk_arg {
297 short first_page, last_page;
298} snd_trident_memblk_arg_t;
299
300typedef struct {
301 unsigned int * entries; /* 16k-aligned TLB table */
302 dma_addr_t entries_dmaaddr; /* 16k-aligned PCI address to TLB table */
303 unsigned long * shadow_entries; /* shadow entries with virtual addresses */
304 struct snd_dma_buffer buffer;
305 snd_util_memhdr_t * memhdr; /* page allocation list */
306 struct snd_dma_buffer silent_page;
307} snd_trident_tlb_t;
308
309struct _snd_trident_voice {
310 unsigned int number;
311 unsigned int use: 1,
312 pcm: 1,
313 synth:1,
314 midi: 1;
315 unsigned int flags;
316 unsigned char client;
317 unsigned char port;
318 unsigned char index;
319
320 snd_seq_instr_t instr;
321 snd_trident_sample_ops_t *sample_ops;
322
323 /* channel parameters */
324 unsigned int CSO; /* 24 bits (16 on DX) */
325 unsigned int ESO; /* 24 bits (16 on DX) */
326 unsigned int LBA; /* 30 bits */
327 unsigned short EC; /* 12 bits */
328 unsigned short Alpha; /* 12 bits */
329 unsigned short Delta; /* 16 bits */
330 unsigned short Attribute; /* 16 bits - SiS 7018 */
331 unsigned short Vol; /* 12 bits (6.6) */
332 unsigned char Pan; /* 7 bits (1.4.2) */
333 unsigned char GVSel; /* 1 bit */
334 unsigned char RVol; /* 7 bits (5.2) */
335 unsigned char CVol; /* 7 bits (5.2) */
336 unsigned char FMC; /* 2 bits */
337 unsigned char CTRL; /* 4 bits */
338 unsigned char FMS; /* 4 bits */
339 unsigned char LFO; /* 8 bits */
340
341 unsigned int negCSO; /* nonzero - use negative CSO */
342
343 snd_util_memblk_t *memblk; /* memory block if TLB enabled */
344
345 /* PCM data */
346
347 trident_t *trident;
348 snd_pcm_substream_t *substream;
349 snd_trident_voice_t *extra; /* extra PCM voice (acts as interrupt generator) */
350 unsigned int running: 1,
351 capture: 1,
352 spdif: 1,
353 foldback: 1,
354 isync: 1,
355 isync2: 1,
356 isync3: 1;
357 int foldback_chan; /* foldback subdevice number */
358 unsigned int stimer; /* global sample timer (to detect spurious interrupts) */
359 unsigned int spurious_threshold; /* spurious threshold */
360 unsigned int isync_mark;
361 unsigned int isync_max;
362 unsigned int isync_ESO;
363
364 /* --- */
365
366 void *private_data;
367 void (*private_free)(snd_trident_voice_t *voice);
368};
369
370struct _snd_4dwave {
371 int seq_client;
372
373 snd_trident_port_t seq_ports[4];
374 snd_simple_ops_t simple_ops;
375 snd_seq_kinstr_list_t *ilist;
376
377 snd_trident_voice_t voices[64];
378
379 int ChanSynthCount; /* number of allocated synth channels */
380 int max_size; /* maximum synth memory size in bytes */
381 int current_size; /* current allocated synth mem in bytes */
382};
383
384struct _snd_trident_pcm_mixer {
385 snd_trident_voice_t *voice; /* active voice */
386 unsigned short vol; /* front volume */
387 unsigned char pan; /* pan control */
388 unsigned char rvol; /* rear volume */
389 unsigned char cvol; /* center volume */
390 unsigned char pad;
391};
392
393struct _snd_trident {
394 int irq;
395
396 unsigned int device; /* device ID */
397
398 unsigned char bDMAStart;
399
400 unsigned long port;
401 unsigned long midi_port;
402
403 unsigned int spurious_irq_count;
404 unsigned int spurious_irq_max_delta;
405
406 snd_trident_tlb_t tlb; /* TLB entries for NX cards */
407
408 unsigned char spdif_ctrl;
409 unsigned char spdif_pcm_ctrl;
410 unsigned int spdif_bits;
411 unsigned int spdif_pcm_bits;
412 snd_kcontrol_t *spdif_pcm_ctl; /* S/PDIF settings */
413 unsigned int ac97_ctrl;
414
415 unsigned int ChanMap[2]; /* allocation map for hardware channels */
416
417 int ChanPCM; /* max number of PCM channels */
418 int ChanPCMcnt; /* actual number of PCM channels */
419
420 unsigned int ac97_detect: 1; /* 1 = AC97 in detection phase */
421 unsigned int in_suspend: 1; /* 1 during suspend/resume */
422
423 struct _snd_4dwave synth; /* synth specific variables */
424
425 spinlock_t event_lock;
426 spinlock_t voice_alloc;
427
428 struct snd_dma_device dma_dev;
429
430 struct pci_dev *pci;
431 snd_card_t *card;
432 snd_pcm_t *pcm; /* ADC/DAC PCM */
433 snd_pcm_t *foldback; /* Foldback PCM */
434 snd_pcm_t *spdif; /* SPDIF PCM */
435 snd_rawmidi_t *rmidi;
436 snd_seq_device_t *seq_dev;
437
438 ac97_bus_t *ac97_bus;
439 ac97_t *ac97;
440 ac97_t *ac97_sec;
441
442 unsigned int musicvol_wavevol;
443 snd_trident_pcm_mixer_t pcm_mixer[32];
444 snd_kcontrol_t *ctl_vol; /* front volume */
445 snd_kcontrol_t *ctl_pan; /* pan */
446 snd_kcontrol_t *ctl_rvol; /* rear volume */
447 snd_kcontrol_t *ctl_cvol; /* center volume */
448
449 spinlock_t reg_lock;
450
451 struct gameport *gameport;
452};
453
454int snd_trident_create(snd_card_t * card,
455 struct pci_dev *pci,
456 int pcm_streams,
457 int pcm_spdif_device,
458 int max_wavetable_size,
459 trident_t ** rtrident);
460int snd_trident_create_gameport(trident_t *trident);
461
462int snd_trident_pcm(trident_t * trident, int device, snd_pcm_t **rpcm);
463int snd_trident_foldback_pcm(trident_t * trident, int device, snd_pcm_t **rpcm);
464int snd_trident_spdif_pcm(trident_t * trident, int device, snd_pcm_t **rpcm);
465int snd_trident_attach_synthesizer(trident_t * trident);
466snd_trident_voice_t *snd_trident_alloc_voice(trident_t * trident, int type, int client, int port);
467void snd_trident_free_voice(trident_t * trident, snd_trident_voice_t *voice);
468void snd_trident_start_voice(trident_t * trident, unsigned int voice);
469void snd_trident_stop_voice(trident_t * trident, unsigned int voice);
470void snd_trident_write_voice_regs(trident_t * trident, snd_trident_voice_t *voice);
471
472/* TLB memory allocation */
473snd_util_memblk_t *snd_trident_alloc_pages(trident_t *trident, snd_pcm_substream_t *substream);
474int snd_trident_free_pages(trident_t *trident, snd_util_memblk_t *blk);
475snd_util_memblk_t *snd_trident_synth_alloc(trident_t *trident, unsigned int size);
476int snd_trident_synth_free(trident_t *trident, snd_util_memblk_t *blk);
477int snd_trident_synth_copy_from_user(trident_t *trident, snd_util_memblk_t *blk, int offset, const char __user *data, int size);
478
479#endif /* __SOUND_TRIDENT_H */
diff --git a/include/sound/uda1341.h b/include/sound/uda1341.h
new file mode 100644
index 000000000000..61ff65a628bc
--- /dev/null
+++ b/include/sound/uda1341.h
@@ -0,0 +1,233 @@
1/*
2 * linux/include/linux/l3/uda1341.h
3 *
4 * Philips UDA1341 mixer device driver for ALSA
5 *
6 * Copyright (c) 2002 Tomas Kasparek <tomas.kasparek@seznam.cz>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License.
10 *
11 * History:
12 *
13 * 2002-03-13 Tomas Kasparek Initial release - based on uda1341.h from OSS
14 * 2002-03-30 Tomas Kasparek Proc filesystem support, complete mixer and DSP
15 * features support
16 */
17
18/* $Id: uda1341.h,v 1.6 2004/05/03 17:36:50 tiwai Exp $ */
19
20#define UDA1341_ALSA_NAME "snd-uda1341"
21
22/*
23 * Default rate set after inicialization
24 */
25#define AUDIO_RATE_DEFAULT 44100
26
27/*
28 * UDA1341 L3 address and command types
29 */
30#define UDA1341_L3ADDR 5
31#define UDA1341_DATA0 (UDA1341_L3ADDR << 2 | 0)
32#define UDA1341_DATA1 (UDA1341_L3ADDR << 2 | 1)
33#define UDA1341_STATUS (UDA1341_L3ADDR << 2 | 2)
34
35enum uda1341_onoff {
36 OFF=0,
37 ON,
38};
39
40const char *onoff_names[] = {
41 "Off",
42 "On",
43};
44
45enum uda1341_format {
46 I2S=0,
47 LSB16,
48 LSB18,
49 LSB20,
50 MSB,
51 LSB16MSB,
52 LSB18MSB,
53 LSB20MSB,
54};
55
56const char *format_names[] = {
57 "I2S-bus",
58 "LSB 16bits",
59 "LSB 18bits",
60 "LSB 20bits",
61 "MSB",
62 "in LSB 16bits/out MSB",
63 "in LSB 18bits/out MSB",
64 "in LSB 20bits/out MSB",
65};
66
67enum uda1341_fs {
68 F512=0,
69 F384,
70 F256,
71 Funused,
72};
73
74const char *fs_names[] = {
75 "512*fs",
76 "384*fs",
77 "256*fs",
78 "Unused - bad value!",
79};
80
81enum uda1341_peak {
82 BEFORE=0,
83 AFTER,
84};
85
86const char *peak_names[] = {
87 "before",
88 "after",
89};
90
91enum uda1341_filter {
92 FLAT=0,
93 MIN,
94 MIN2,
95 MAX,
96};
97
98const char *filter_names[] = {
99 "flat",
100 "min",
101 "min",
102 "max",
103};
104
105const char*bass_values[][16] = {
106 {"0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB",
107 "0 dB", "0 dB", "0 dB", "0 dB", "undefined", }, //flat
108 {"0 dB", "2 dB", "4 dB", "6 dB", "8 dB", "10 dB", "12 dB", "14 dB", "16 dB", "18 dB", "18 dB",
109 "18 dB", "18 dB", "18 dB", "18 dB", "undefined",}, // min
110 {"0 dB", "2 dB", "4 dB", "6 dB", "8 dB", "10 dB", "12 dB", "14 dB", "16 dB", "18 dB", "18 dB",
111 "18 dB", "18 dB", "18 dB", "18 dB", "undefined",}, // min
112 {"0 dB", "2 dB", "4 dB", "6 dB", "8 dB", "10 dB", "12 dB", "14 dB", "16 dB", "18 dB", "20 dB",
113 "22 dB", "24 dB", "24 dB", "24 dB", "undefined",}, // max
114};
115
116enum uda1341_mixer {
117 DOUBLE,
118 LINE,
119 MIC,
120 MIXER,
121};
122
123const char *mixer_names[] = {
124 "double differential",
125 "input channel 1 (line in)",
126 "input channel 2 (microphone)",
127 "digital mixer",
128};
129
130enum uda1341_deemp {
131 NONE,
132 D32,
133 D44,
134 D48,
135};
136
137const char *deemp_names[] = {
138 "none",
139 "32 kHz",
140 "44.1 kHz",
141 "48 kHz",
142};
143
144const char *mic_sens_value[] = {
145 "-3 dB", "0 dB", "3 dB", "9 dB", "15 dB", "21 dB", "27 dB", "not used",
146};
147
148const unsigned short AGC_atime[] = {
149 11, 16, 11, 16, 21, 11, 16, 21,
150};
151
152const unsigned short AGC_dtime[] = {
153 100, 100, 200, 200, 200, 400, 400, 400,
154};
155
156const char *AGC_level[] = {
157 "-9.0", "-11.5", "-15.0", "-17.5",
158};
159
160const char *ig_small_value[] = {
161 "-3.0", "-2.5", "-2.0", "-1.5", "-1.0", "-0.5",
162};
163
164/*
165 * this was computed as peak_value[i] = pow((63-i)*1.42,1.013)
166 *
167 * UDA1341 datasheet on page 21: Peak value (dB) = (Peak level - 63.5)*5*log2
168 * There is an table with these values [level]=value: [3]=-90.31, [7]=-84.29
169 * [61]=-2.78, [62] = -1.48, [63] = 0.0
170 * I tried to compute it, but using but even using logarithm with base either 10 or 2
171 * i was'n able to get values in the table from the formula. So I constructed another
172 * formula (see above) to interpolate the values as good as possible. If there is some
173 * mistake, please contact me on tomas.kasparek@seznam.cz. Thanks.
174 * UDA1341TS datasheet is available at:
175 * http://www-us9.semiconductors.com/acrobat/datasheets/UDA1341TS_3.pdf
176 */
177const char *peak_value[] = {
178 "-INF dB", "N.A.", "N.A", "90.31 dB", "N.A.", "N.A.", "N.A.", "-84.29 dB",
179 "-82.65 dB", "-81.13 dB", "-79.61 dB", "-78.09 dB", "-76.57 dB", "-75.05 dB", "-73.53 dB",
180 "-72.01 dB", "-70.49 dB", "-68.97 dB", "-67.45 dB", "-65.93 dB", "-64.41 dB", "-62.90 dB",
181 "-61.38 dB", "-59.86 dB", "-58.35 dB", "-56.83 dB", "-55.32 dB", "-53.80 dB", "-52.29 dB",
182 "-50.78 dB", "-49.26 dB", "-47.75 dB", "-46.24 dB", "-44.73 dB", "-43.22 dB", "-41.71 dB",
183 "-40.20 dB", "-38.69 dB", "-37.19 dB", "-35.68 dB", "-34.17 dB", "-32.67 dB", "-31.17 dB",
184 "-29.66 dB", "-28.16 dB", "-26.66 dB", "-25.16 dB", "-23.66 dB", "-22.16 dB", "-20.67 dB",
185 "-19.17 dB", "-17.68 dB", "-16.19 dB", "-14.70 dB", "-13.21 dB", "-11.72 dB", "-10.24 dB",
186 "-8.76 dB", "-7.28 dB", "-5.81 dB", "-4.34 dB", "-2.88 dB", "-1.43 dB", "0.00 dB",
187};
188
189enum uda1341_config {
190 CMD_READ_REG = 0,
191 CMD_RESET,
192 CMD_FS,
193 CMD_FORMAT,
194 CMD_OGAIN,
195 CMD_IGAIN,
196 CMD_DAC,
197 CMD_ADC,
198 CMD_VOLUME,
199 CMD_BASS,
200 CMD_TREBBLE,
201 CMD_PEAK,
202 CMD_DEEMP,
203 CMD_MUTE,
204 CMD_FILTER,
205 CMD_CH1,
206 CMD_CH2,
207 CMD_MIC,
208 CMD_MIXER,
209 CMD_AGC,
210 CMD_IG,
211 CMD_AGC_TIME,
212 CMD_AGC_LEVEL,
213#ifdef CONFIG_PM
214 CMD_SUSPEND,
215 CMD_RESUME,
216#endif
217 CMD_LAST,
218};
219
220enum write_through {
221 //used in update_bits (write_cfg) to avoid l3_write - just update local copy of regs.
222 REGS_ONLY=0,
223 //update local regs and write value to uda1341 - do l3_write
224 FLUSH,
225};
226
227int __init snd_chip_uda1341_mixer_new(snd_card_t *card, struct l3_client **clnt);
228
229/*
230 * Local variables:
231 * indent-tabs-mode: t
232 * End:
233 */
diff --git a/include/sound/util_mem.h b/include/sound/util_mem.h
new file mode 100644
index 000000000000..9d2cdfa0c42a
--- /dev/null
+++ b/include/sound/util_mem.h
@@ -0,0 +1,64 @@
1#ifndef __SOUND_UTIL_MEM_H
2#define __SOUND_UTIL_MEM_H
3/*
4 * Copyright (C) 2000 Takashi Iwai <tiwai@suse.de>
5 *
6 * Generic memory management routines for soundcard memory allocation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23typedef struct snd_util_memblk snd_util_memblk_t;
24typedef struct snd_util_memhdr snd_util_memhdr_t;
25typedef unsigned int snd_util_unit_t;
26
27/*
28 * memory block
29 */
30struct snd_util_memblk {
31 snd_util_unit_t size; /* size of this block */
32 snd_util_unit_t offset; /* zero-offset of this block */
33 struct list_head list; /* link */
34};
35
36#define snd_util_memblk_argptr(blk) (void*)((char*)(blk) + sizeof(snd_util_memblk_t))
37
38/*
39 * memory management information
40 */
41struct snd_util_memhdr {
42 snd_util_unit_t size; /* size of whole data */
43 struct list_head block; /* block linked-list header */
44 int nblocks; /* # of allocated blocks */
45 snd_util_unit_t used; /* used memory size */
46 int block_extra_size; /* extra data size of chunk */
47 struct semaphore block_mutex; /* lock */
48};
49
50/*
51 * prototypes
52 */
53snd_util_memhdr_t *snd_util_memhdr_new(int memsize);
54void snd_util_memhdr_free(snd_util_memhdr_t *hdr);
55snd_util_memblk_t *snd_util_mem_alloc(snd_util_memhdr_t *hdr, int size);
56int snd_util_mem_free(snd_util_memhdr_t *hdr, snd_util_memblk_t *blk);
57int snd_util_mem_avail(snd_util_memhdr_t *hdr);
58
59/* functions without mutex */
60snd_util_memblk_t *__snd_util_mem_alloc(snd_util_memhdr_t *hdr, int size);
61void __snd_util_mem_free(snd_util_memhdr_t *hdr, snd_util_memblk_t *blk);
62snd_util_memblk_t *__snd_util_memblk_new(snd_util_memhdr_t *hdr, snd_util_unit_t units, struct list_head *prev);
63
64#endif /* __SOUND_UTIL_MEM_H */
diff --git a/include/sound/version.h b/include/sound/version.h
new file mode 100644
index 000000000000..98b4230778ed
--- /dev/null
+++ b/include/sound/version.h
@@ -0,0 +1,3 @@
1/* include/version.h. Generated by configure. */
2#define CONFIG_SND_VERSION "1.0.9rc2"
3#define CONFIG_SND_DATE " (Thu Mar 24 10:33:39 2005 UTC)"
diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h
new file mode 100644
index 000000000000..a7e29933f2d0
--- /dev/null
+++ b/include/sound/vx_core.h
@@ -0,0 +1,562 @@
1/*
2 * Driver for Digigram VX soundcards
3 *
4 * Hardware core part
5 *
6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __SOUND_VX_COMMON_H
24#define __SOUND_VX_COMMON_H
25
26#include <sound/pcm.h>
27#include <sound/hwdep.h>
28#include <linux/interrupt.h>
29
30#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
31#if !defined(CONFIG_USE_VXLOADER) && !defined(CONFIG_SND_VX_LIB) /* built-in kernel */
32#define SND_VX_FW_LOADER /* use the standard firmware loader */
33#endif
34#endif
35
36struct firmware;
37struct device;
38
39typedef struct snd_vx_core vx_core_t;
40typedef struct vx_pipe vx_pipe_t;
41
42#define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */
43
44/*
45 */
46#define SIZE_MAX_CMD 0x10
47#define SIZE_MAX_STATUS 0x10
48
49struct vx_rmh {
50 u16 LgCmd; /* length of the command to send (WORDs) */
51 u16 LgStat; /* length of the status received (WORDs) */
52 u32 Cmd[SIZE_MAX_CMD];
53 u32 Stat[SIZE_MAX_STATUS];
54 u16 DspStat; /* status type, RMP_SSIZE_XXX */
55};
56
57typedef u64 pcx_time_t;
58
59#define VX_MAX_PIPES 16
60#define VX_MAX_PERIODS 32
61#define VX_MAX_CODECS 2
62
63struct vx_ibl_info {
64 int size; /* the current IBL size (0 = query) in bytes */
65 int max_size; /* max. IBL size in bytes */
66 int min_size; /* min. IBL size in bytes */
67 int granularity; /* granularity */
68};
69
70struct vx_pipe {
71 int number;
72 unsigned int is_capture: 1;
73 unsigned int data_mode: 1;
74 unsigned int running: 1;
75 unsigned int prepared: 1;
76 int channels;
77 unsigned int differed_type;
78 pcx_time_t pcx_time;
79 snd_pcm_substream_t *substream;
80
81 int hbuf_size; /* H-buffer size in bytes */
82 int buffer_bytes; /* the ALSA pcm buffer size in bytes */
83 int period_bytes; /* the ALSA pcm period size in bytes */
84 int hw_ptr; /* the current hardware pointer in bytes */
85 int position; /* the current position in frames (playback only) */
86 int transferred; /* the transferred size (per period) in frames */
87 int align; /* size of alignment */
88 u64 cur_count; /* current sample position (for playback) */
89
90 unsigned int references; /* an output pipe may be used for monitoring and/or playback */
91 vx_pipe_t *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/
92
93 struct tasklet_struct start_tq;
94};
95
96struct snd_vx_ops {
97 /* low-level i/o */
98 unsigned char (*in8)(vx_core_t *chip, int reg);
99 unsigned int (*in32)(vx_core_t *chip, int reg);
100 void (*out8)(vx_core_t *chip, int reg, unsigned char val);
101 void (*out32)(vx_core_t *chip, int reg, unsigned int val);
102 /* irq */
103 int (*test_and_ack)(vx_core_t *chip);
104 void (*validate_irq)(vx_core_t *chip, int enable);
105 /* codec */
106 void (*write_codec)(vx_core_t *chip, int codec, unsigned int data);
107 void (*akm_write)(vx_core_t *chip, int reg, unsigned int data);
108 void (*reset_codec)(vx_core_t *chip);
109 void (*change_audio_source)(vx_core_t *chip, int src);
110 void (*set_clock_source)(vx_core_t *chp, int src);
111 /* chip init */
112 int (*load_dsp)(vx_core_t *chip, int idx, const struct firmware *fw);
113 void (*reset_dsp)(vx_core_t *chip);
114 void (*reset_board)(vx_core_t *chip, int cold_reset);
115 int (*add_controls)(vx_core_t *chip);
116 /* pcm */
117 void (*dma_write)(vx_core_t *chip, snd_pcm_runtime_t *runtime,
118 vx_pipe_t *pipe, int count);
119 void (*dma_read)(vx_core_t *chip, snd_pcm_runtime_t *runtime,
120 vx_pipe_t *pipe, int count);
121};
122
123struct snd_vx_hardware {
124 const char *name;
125 int type; /* VX_TYPE_XXX */
126
127 /* hardware specs */
128 unsigned int num_codecs;
129 unsigned int num_ins;
130 unsigned int num_outs;
131 unsigned int output_level_max;
132};
133
134/* hwdep id string */
135#define SND_VX_HWDEP_ID "VX Loader"
136
137/* hardware type */
138enum {
139 /* VX222 PCI */
140 VX_TYPE_BOARD, /* old VX222 PCI */
141 VX_TYPE_V2, /* VX222 V2 PCI */
142 VX_TYPE_MIC, /* VX222 Mic PCI */
143 /* VX-pocket */
144 VX_TYPE_VXPOCKET, /* VXpocket V2 */
145 VX_TYPE_VXP440, /* VXpocket 440 */
146 VX_TYPE_NUMS
147};
148
149/* chip status */
150enum {
151 VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */
152 VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */
153 VX_STAT_CHIP_INIT = (1 << 2), /* all operational */
154 VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */
155 VX_STAT_IS_STALE = (1 << 15) /* device is stale */
156};
157
158/* min/max values for analog output for old codecs */
159#define VX_ANALOG_OUT_LEVEL_MAX 0xe3
160
161struct snd_vx_core {
162 /* ALSA stuff */
163 snd_card_t *card;
164 snd_pcm_t *pcm[VX_MAX_CODECS];
165 int type; /* VX_TYPE_XXX */
166
167 int irq;
168 /* ports are defined externally */
169
170 /* low-level functions */
171 struct snd_vx_hardware *hw;
172 struct snd_vx_ops *ops;
173
174 spinlock_t lock;
175 spinlock_t irq_lock;
176 struct tasklet_struct tq;
177
178 unsigned int chip_status;
179 unsigned int pcm_running;
180
181 struct device *dev;
182 snd_hwdep_t *hwdep;
183
184 struct vx_rmh irq_rmh; /* RMH used in interrupts */
185
186 unsigned int audio_info; /* see VX_AUDIO_INFO */
187 unsigned int audio_ins;
188 unsigned int audio_outs;
189 struct vx_pipe **playback_pipes;
190 struct vx_pipe **capture_pipes;
191
192 /* clock and audio sources */
193 unsigned int audio_source; /* current audio input source */
194 unsigned int audio_source_target;
195 unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */
196 unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */
197 unsigned int freq; /* current frequency */
198 unsigned int freq_detected; /* detected frequency from digital in */
199 unsigned int uer_detected; /* VX_UER_MODE_XXX */
200 unsigned int uer_bits; /* IEC958 status bits */
201 struct vx_ibl_info ibl; /* IBL information */
202
203 /* mixer setting */
204 int output_level[VX_MAX_CODECS][2]; /* analog output level */
205 int audio_gain[2][4]; /* digital audio level (playback/capture) */
206 unsigned char audio_active[4]; /* mute/unmute on digital playback */
207 int audio_monitor[4]; /* playback hw-monitor level */
208 unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */
209
210 struct semaphore mixer_mutex;
211
212 const struct firmware *firmware[4]; /* loaded firmware data */
213};
214
215
216/*
217 * constructor
218 */
219vx_core_t *snd_vx_create(snd_card_t *card, struct snd_vx_hardware *hw,
220 struct snd_vx_ops *ops, int extra_size);
221int snd_vx_setup_firmware(vx_core_t *chip);
222int snd_vx_load_boot_image(vx_core_t *chip, const struct firmware *dsp);
223int snd_vx_dsp_boot(vx_core_t *chip, const struct firmware *dsp);
224int snd_vx_dsp_load(vx_core_t *chip, const struct firmware *dsp);
225
226void snd_vx_free_firmware(vx_core_t *chip);
227
228/*
229 * interrupt handler; exported for pcmcia
230 */
231irqreturn_t snd_vx_irq_handler(int irq, void *dev, struct pt_regs *regs);
232
233/*
234 * lowlevel functions
235 */
236inline static int vx_test_and_ack(vx_core_t *chip)
237{
238 snd_assert(chip->ops->test_and_ack, return -ENXIO);
239 return chip->ops->test_and_ack(chip);
240}
241
242inline static void vx_validate_irq(vx_core_t *chip, int enable)
243{
244 snd_assert(chip->ops->validate_irq, return);
245 chip->ops->validate_irq(chip, enable);
246}
247
248inline static unsigned char snd_vx_inb(vx_core_t *chip, int reg)
249{
250 snd_assert(chip->ops->in8, return 0);
251 return chip->ops->in8(chip, reg);
252}
253
254inline static unsigned int snd_vx_inl(vx_core_t *chip, int reg)
255{
256 snd_assert(chip->ops->in32, return 0);
257 return chip->ops->in32(chip, reg);
258}
259
260inline static void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val)
261{
262 snd_assert(chip->ops->out8, return);
263 chip->ops->out8(chip, reg, val);
264}
265
266inline static void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val)
267{
268 snd_assert(chip->ops->out32, return);
269 chip->ops->out32(chip, reg, val);
270}
271
272#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg)
273#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val)
274#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg)
275#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val)
276
277void snd_vx_delay(vx_core_t *chip, int msec);
278
279static inline void vx_reset_dsp(vx_core_t *chip)
280{
281 snd_assert(chip->ops->reset_dsp, return);
282 chip->ops->reset_dsp(chip);
283}
284
285int vx_send_msg(vx_core_t *chip, struct vx_rmh *rmh);
286int vx_send_msg_nolock(vx_core_t *chip, struct vx_rmh *rmh);
287int vx_send_rih(vx_core_t *chip, int cmd);
288int vx_send_rih_nolock(vx_core_t *chip, int cmd);
289
290void vx_reset_codec(vx_core_t *chip, int cold_reset);
291
292/*
293 * check the bit on the specified register
294 * returns zero if a bit matches, or a negative error code.
295 * exported for vxpocket driver
296 */
297int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time);
298#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
299#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
300#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
301
302
303/*
304 * pseudo-DMA transfer
305 */
306inline static void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
307 vx_pipe_t *pipe, int count)
308{
309 snd_assert(chip->ops->dma_write, return);
310 chip->ops->dma_write(chip, runtime, pipe, count);
311}
312
313inline static void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
314 vx_pipe_t *pipe, int count)
315{
316 snd_assert(chip->ops->dma_read, return);
317 chip->ops->dma_read(chip, runtime, pipe, count);
318}
319
320
321
322/* error with hardware code,
323 * the return value is -(VX_ERR_MASK | actual-hw-error-code)
324 */
325#define VX_ERR_MASK 0x1000000
326#define vx_get_error(err) (-(err) & ~VX_ERR_MASK)
327
328
329/*
330 * pcm stuff
331 */
332int snd_vx_pcm_new(vx_core_t *chip);
333void vx_pcm_update_intr(vx_core_t *chip, unsigned int events);
334
335/*
336 * mixer stuff
337 */
338int snd_vx_mixer_new(vx_core_t *chip);
339void vx_toggle_dac_mute(vx_core_t *chip, int mute);
340int vx_sync_audio_source(vx_core_t *chip);
341int vx_set_monitor_level(vx_core_t *chip, int audio, int level, int active);
342
343/*
344 * IEC958 & clock stuff
345 */
346void vx_set_iec958_status(vx_core_t *chip, unsigned int bits);
347int vx_set_clock(vx_core_t *chip, unsigned int freq);
348void vx_set_internal_clock(vx_core_t *chip, unsigned int freq);
349int vx_change_frequency(vx_core_t *chip);
350
351
352/*
353 * hardware constants
354 */
355
356#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD)
357#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET)
358
359/* audio input source */
360enum {
361 VX_AUDIO_SRC_DIGITAL,
362 VX_AUDIO_SRC_LINE,
363 VX_AUDIO_SRC_MIC
364};
365
366/* clock source */
367enum {
368 INTERNAL_QUARTZ,
369 UER_SYNC
370};
371
372/* clock mode */
373enum {
374 VX_CLOCK_MODE_AUTO, /* depending on the current audio source */
375 VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */
376 VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */
377};
378
379/* SPDIF/UER type */
380enum {
381 VX_UER_MODE_CONSUMER,
382 VX_UER_MODE_PROFESSIONAL,
383 VX_UER_MODE_NOT_PRESENT,
384};
385
386/* register indices */
387enum {
388 VX_ICR,
389 VX_CVR,
390 VX_ISR,
391 VX_IVR,
392 VX_RXH,
393 VX_TXH = VX_RXH,
394 VX_RXM,
395 VX_TXM = VX_RXM,
396 VX_RXL,
397 VX_TXL = VX_RXL,
398 VX_DMA,
399 VX_CDSP,
400 VX_RFREQ,
401 VX_RUER_V2,
402 VX_GAIN,
403 VX_DATA = VX_GAIN,
404 VX_MEMIRQ,
405 VX_ACQ,
406 VX_BIT0,
407 VX_BIT1,
408 VX_MIC0,
409 VX_MIC1,
410 VX_MIC2,
411 VX_MIC3,
412 VX_PLX0,
413 VX_PLX1,
414 VX_PLX2,
415
416 VX_LOFREQ, // V2: ACQ, VP: RFREQ
417 VX_HIFREQ, // V2: BIT0, VP: RUER_V2
418 VX_CSUER, // V2: BIT1, VP: BIT0
419 VX_RUER, // V2: RUER_V2, VP: BIT1
420
421 VX_REG_MAX,
422
423 /* aliases for VX board */
424 VX_RESET_DMA = VX_ISR,
425 VX_CFG = VX_RFREQ,
426 VX_STATUS = VX_MEMIRQ,
427 VX_SELMIC = VX_MIC0,
428 VX_COMPOT = VX_MIC1,
429 VX_SCOMPR = VX_MIC2,
430 VX_GLIMIT = VX_MIC3,
431 VX_INTCSR = VX_PLX0,
432 VX_CNTRL = VX_PLX1,
433 VX_GPIOC = VX_PLX2,
434
435 /* aliases for VXPOCKET board */
436 VX_MICRO = VX_MEMIRQ,
437 VX_CODEC2 = VX_MEMIRQ,
438 VX_DIALOG = VX_ACQ,
439
440};
441
442/* RMH status type */
443enum {
444 RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */
445 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */
446 RMH_SSIZE_MASK = 2, /* status size given in bitmask */
447};
448
449
450/* bits for ICR register */
451#define ICR_HF1 0x10
452#define ICR_HF0 0x08
453#define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */
454#define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */
455
456/* bits for CVR register */
457#define CVR_HC 0x80
458
459/* bits for ISR register */
460#define ISR_HF3 0x10
461#define ISR_HF2 0x08
462#define ISR_CHK 0x10
463#define ISR_ERR 0x08
464#define ISR_TX_READY 0x04
465#define ISR_TX_EMPTY 0x02
466#define ISR_RX_FULL 0x01
467
468/* Constants used to access the DATA register */
469#define VX_DATA_CODEC_MASK 0x80
470#define VX_DATA_XICOR_MASK 0x80
471
472/* Constants used to access the CSUER register (both for VX2 and VXP) */
473#define VX_SUER_FREQ_MASK 0x0c
474#define VX_SUER_FREQ_32KHz_MASK 0x0c
475#define VX_SUER_FREQ_44KHz_MASK 0x00
476#define VX_SUER_FREQ_48KHz_MASK 0x04
477#define VX_SUER_DATA_PRESENT_MASK 0x02
478#define VX_SUER_CLOCK_PRESENT_MASK 0x01
479
480#define VX_CUER_HH_BITC_SEL_MASK 0x08
481#define VX_CUER_MH_BITC_SEL_MASK 0x04
482#define VX_CUER_ML_BITC_SEL_MASK 0x02
483#define VX_CUER_LL_BITC_SEL_MASK 0x01
484
485#define XX_UER_CBITS_OFFSET_MASK 0x1f
486
487
488/* bits for audio_info */
489#define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */
490#define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */
491#define VX_AUDIO_INFO_MPEG1 (1<<5)
492#define VX_AUDIO_INFO_MPEG2 (1<<6)
493#define VX_AUDIO_INFO_LINEAR_8 (1<<7)
494#define VX_AUDIO_INFO_LINEAR_16 (1<<8)
495#define VX_AUDIO_INFO_LINEAR_24 (1<<9)
496
497/* DSP Interrupt Request values */
498#define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */
499/* call with vx_send_irq_dsp() */
500#define IRQ_MESS_WRITE_END 0x30
501#define IRQ_MESS_WRITE_NEXT 0x32
502#define IRQ_MESS_READ_NEXT 0x34
503#define IRQ_MESS_READ_END 0x36
504#define IRQ_MESSAGE 0x38
505#define IRQ_RESET_CHK 0x3A
506#define IRQ_CONNECT_STREAM_NEXT 0x26
507#define IRQ_CONNECT_STREAM_END 0x28
508#define IRQ_PAUSE_START_CONNECT 0x2A
509#define IRQ_END_CONNECTION 0x2C
510
511/* Is there async. events pending ( IT Source Test ) */
512#define ASYNC_EVENTS_PENDING 0x008000
513#define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate
514#define NOTIF_EVENTS_PENDING 0x002000
515#define TIME_CODE_EVENT_PENDING 0x001000
516#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800
517#define END_OF_BUFFER_EVENTS_PENDING 0x000400
518#define FATAL_DSP_ERROR 0xff0000
519
520/* Stream Format Header Defines */
521#define HEADER_FMT_BASE 0xFED00000
522#define HEADER_FMT_MONO 0x000000C0
523#define HEADER_FMT_INTEL 0x00008000
524#define HEADER_FMT_16BITS 0x00002000
525#define HEADER_FMT_24BITS 0x00004000
526#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/
527#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/
528
529/* Constants used to access the Codec */
530#define XX_CODEC_SELECTOR 0x20
531/* codec commands */
532#define XX_CODEC_ADC_CONTROL_REGISTER 0x01
533#define XX_CODEC_DAC_CONTROL_REGISTER 0x02
534#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03
535#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04
536#define XX_CODEC_PORT_MODE_REGISTER 0x05
537#define XX_CODEC_STATUS_REPORT_REGISTER 0x06
538#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
539
540/*
541 * Audio-level control values
542 */
543#define CVAL_M110DB 0x000 /* -110dB */
544#define CVAL_M99DB 0x02C
545#define CVAL_M21DB 0x163
546#define CVAL_M18DB 0x16F
547#define CVAL_M10DB 0x18F
548#define CVAL_0DB 0x1B7
549#define CVAL_18DB 0x1FF /* +18dB */
550#define CVAL_MAX 0x1FF
551
552#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000
553#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000
554#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000
555#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01
556#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02
557#define VALID_AUDIO_IO_MUTE_LEVEL 0x04
558#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08
559#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10
560
561
562#endif /* __SOUND_VX_COMMON_H */
diff --git a/include/sound/wavefront.h b/include/sound/wavefront.h
new file mode 100644
index 000000000000..9e572aed2435
--- /dev/null
+++ b/include/sound/wavefront.h
@@ -0,0 +1,695 @@
1#ifndef __SOUND_WAVEFRONT_H__
2#define __SOUND_WAVEFRONT_H__
3
4/*
5 * Driver for Turtle Beach Wavefront cards (Maui,Tropez,Tropez+)
6 *
7 * Copyright (c) by Paul Barton-Davis <pbd@op.net>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#if (!defined(__GNUC__) && !defined(__GNUG__))
25
26 You will not be able to compile this file correctly without gcc, because
27 it is necessary to pack the "wavefront_alias" structure to a size
28 of 22 bytes, corresponding to 16-bit alignment (as would have been
29 the case on the original platform, MS-DOS). If this is not done,
30 then WavePatch-format files cannot be read/written correctly.
31 The method used to do this here ("__attribute__((packed)") is
32 completely compiler dependent.
33
34 All other wavefront_* types end up aligned to 32 bit values and
35 still have the same (correct) size.
36
37#else
38
39 /* However, note that as of G++ 2.7.3.2, g++ was unable to
40 correctly parse *type* __attribute__ tags. It will do the
41 right thing if we use the "packed" attribute on each struct
42 member, which has the same semantics anyway.
43 */
44
45#endif /* __GNUC__ */
46
47/***************************** WARNING ********************************
48 PLEASE DO NOT MODIFY THIS FILE IN ANY WAY THAT AFFECTS ITS ABILITY TO
49 BE USED WITH EITHER C *OR* C++.
50 **********************************************************************/
51
52#ifndef NUM_MIDIKEYS
53#define NUM_MIDIKEYS 128
54#endif /* NUM_MIDIKEYS */
55
56#ifndef NUM_MIDICHANNELS
57#define NUM_MIDICHANNELS 16
58#endif /* NUM_MIDICHANNELS */
59
60/* These are very useful/important. the original wavefront interface
61 was developed on a 16 bit system, where sizeof(int) = 2
62 bytes. Defining things like this makes the code much more portable, and
63 easier to understand without having to toggle back and forth
64 between a 16-bit view of the world and a 32-bit one.
65 */
66
67#ifndef __KERNEL__
68/* keep them for compatibility */
69typedef short s16;
70typedef unsigned short u16;
71typedef int s32;
72typedef unsigned int u32;
73typedef char s8;
74typedef unsigned char u8;
75typedef s16 INT16;
76typedef u16 UINT16;
77typedef s32 INT32;
78typedef u32 UINT32;
79typedef s8 CHAR8;
80typedef u8 UCHAR8;
81#endif
82
83/* Pseudo-commands not part of the WaveFront command set.
84 These are used for various driver controls and direct
85 hardware control.
86 */
87
88#define WFC_DEBUG_DRIVER 0
89#define WFC_FX_IOCTL 1
90#define WFC_PATCH_STATUS 2
91#define WFC_PROGRAM_STATUS 3
92#define WFC_SAMPLE_STATUS 4
93#define WFC_DISABLE_INTERRUPTS 5
94#define WFC_ENABLE_INTERRUPTS 6
95#define WFC_INTERRUPT_STATUS 7
96#define WFC_ROMSAMPLES_RDONLY 8
97#define WFC_IDENTIFY_SLOT_TYPE 9
98
99/* Wavefront synth commands
100 */
101
102#define WFC_DOWNLOAD_SAMPLE 0x80
103#define WFC_DOWNLOAD_BLOCK 0x81
104#define WFC_DOWNLOAD_MULTISAMPLE 0x82
105#define WFC_DOWNLOAD_SAMPLE_ALIAS 0x83
106#define WFC_DELETE_SAMPLE 0x84
107#define WFC_REPORT_FREE_MEMORY 0x85
108#define WFC_DOWNLOAD_PATCH 0x86
109#define WFC_DOWNLOAD_PROGRAM 0x87
110#define WFC_SET_SYNTHVOL 0x89
111#define WFC_SET_NVOICES 0x8B
112#define WFC_DOWNLOAD_DRUM 0x90
113#define WFC_GET_SYNTHVOL 0x92
114#define WFC_GET_NVOICES 0x94
115#define WFC_DISABLE_CHANNEL 0x9A
116#define WFC_ENABLE_CHANNEL 0x9B
117#define WFC_MISYNTH_OFF 0x9D
118#define WFC_MISYNTH_ON 0x9E
119#define WFC_FIRMWARE_VERSION 0x9F
120#define WFC_GET_NSAMPLES 0xA0
121#define WFC_DISABLE_DRUM_PROGRAM 0xA2
122#define WFC_UPLOAD_PATCH 0xA3
123#define WFC_UPLOAD_PROGRAM 0xA4
124#define WFC_SET_TUNING 0xA6
125#define WFC_GET_TUNING 0xA7
126#define WFC_VMIDI_ON 0xA8
127#define WFC_VMIDI_OFF 0xA9
128#define WFC_MIDI_STATUS 0xAA
129#define WFC_GET_CHANNEL_STATUS 0xAB
130#define WFC_DOWNLOAD_SAMPLE_HEADER 0xAC
131#define WFC_UPLOAD_SAMPLE_HEADER 0xAD
132#define WFC_UPLOAD_MULTISAMPLE 0xAE
133#define WFC_UPLOAD_SAMPLE_ALIAS 0xAF
134#define WFC_IDENTIFY_SAMPLE_TYPE 0xB0
135#define WFC_DOWNLOAD_EDRUM_PROGRAM 0xB1
136#define WFC_UPLOAD_EDRUM_PROGRAM 0xB2
137#define WFC_SET_EDRUM_CHANNEL 0xB3
138#define WFC_INSTOUT_LEVELS 0xB4
139#define WFC_PEAKOUT_LEVELS 0xB5
140#define WFC_REPORT_CHANNEL_PROGRAMS 0xB6
141#define WFC_HARDWARE_VERSION 0xCF
142#define WFC_UPLOAD_SAMPLE_PARAMS 0xD7
143#define WFC_DOWNLOAD_OS 0xF1
144#define WFC_NOOP 0xFF
145
146#define WF_MAX_SAMPLE 512
147#define WF_MAX_PATCH 256
148#define WF_MAX_PROGRAM 128
149
150#define WF_SECTION_MAX 44 /* longest OS section length */
151
152/* # of bytes we send to the board when sending it various kinds of
153 substantive data, such as samples, patches and programs.
154*/
155
156#define WF_PROGRAM_BYTES 32
157#define WF_PATCH_BYTES 132
158#define WF_SAMPLE_BYTES 27
159#define WF_SAMPLE_HDR_BYTES 25
160#define WF_ALIAS_BYTES 25
161#define WF_DRUM_BYTES 9
162#define WF_MSAMPLE_BYTES 259 /* (MIDI_KEYS * 2) + 3 */
163
164#define WF_ACK 0x80
165#define WF_DMA_ACK 0x81
166
167/* OR-values for MIDI status bits */
168
169#define WF_MIDI_VIRTUAL_ENABLED 0x1
170#define WF_MIDI_VIRTUAL_IS_EXTERNAL 0x2
171#define WF_MIDI_IN_TO_SYNTH_DISABLED 0x4
172
173/* slot indexes for struct address_info: makes code a little more mnemonic */
174
175#define WF_SYNTH_SLOT 0
176#define WF_INTERNAL_MIDI_SLOT 1
177#define WF_EXTERNAL_MIDI_SLOT 2
178
179/* Magic MIDI bytes used to switch I/O streams on the ICS2115 MPU401
180 emulation. Note these NEVER show up in output from the device and
181 should NEVER be used in input unless Virtual MIDI mode has been
182 disabled. If they do show up as input, the results are unpredictable.
183*/
184
185#define WF_EXTERNAL_SWITCH 0xFD
186#define WF_INTERNAL_SWITCH 0xF9
187
188/* Debugging flags */
189
190#define WF_DEBUG_CMD 0x1
191#define WF_DEBUG_DATA 0x2
192#define WF_DEBUG_LOAD_PATCH 0x4
193#define WF_DEBUG_IO 0x8
194
195/* WavePatch file format stuff */
196
197#define WF_WAVEPATCH_VERSION 120; /* Current version number (1.2) */
198#define WF_MAX_COMMENT 64 /* Comment length */
199#define WF_NUM_LAYERS 4
200#define WF_NAME_LENGTH 32
201#define WF_SOURCE_LENGTH 260
202
203#define BankFileID "Bank"
204#define DrumkitFileID "DrumKit"
205#define ProgramFileID "Program"
206
207struct wf_envelope
208{
209 u8 attack_time:7;
210 u8 Unused1:1;
211
212 u8 decay1_time:7;
213 u8 Unused2:1;
214
215 u8 decay2_time:7;
216 u8 Unused3:1;
217
218 u8 sustain_time:7;
219 u8 Unused4:1;
220
221 u8 release_time:7;
222 u8 Unused5:1;
223
224 u8 release2_time:7;
225 u8 Unused6:1;
226
227 s8 attack_level;
228 s8 decay1_level;
229 s8 decay2_level;
230 s8 sustain_level;
231 s8 release_level;
232
233 u8 attack_velocity:7;
234 u8 Unused7:1;
235
236 u8 volume_velocity:7;
237 u8 Unused8:1;
238
239 u8 keyboard_scaling:7;
240 u8 Unused9:1;
241};
242typedef struct wf_envelope wavefront_envelope;
243
244struct wf_lfo
245{
246 u8 sample_number;
247
248 u8 frequency:7;
249 u8 Unused1:1;
250
251 u8 am_src:4;
252 u8 fm_src:4;
253
254 s8 fm_amount;
255 s8 am_amount;
256 s8 start_level;
257 s8 end_level;
258
259 u8 ramp_delay:7;
260 u8 wave_restart:1; /* for LFO2 only */
261
262 u8 ramp_time:7;
263 u8 Unused2:1;
264};
265typedef struct wf_lfo wavefront_lfo;
266
267struct wf_patch
268{
269 s16 frequency_bias; /* ** THIS IS IN MOTOROLA FORMAT!! ** */
270
271 u8 amplitude_bias:7;
272 u8 Unused1:1;
273
274 u8 portamento:7;
275 u8 Unused2:1;
276
277 u8 sample_number;
278
279 u8 pitch_bend:4;
280 u8 sample_msb:1;
281 u8 Unused3:3;
282
283 u8 mono:1;
284 u8 retrigger:1;
285 u8 nohold:1;
286 u8 restart:1;
287 u8 filterconfig:2; /* SDK says "not used" */
288 u8 reuse:1;
289 u8 reset_lfo:1;
290
291 u8 fm_src2:4;
292 u8 fm_src1:4;
293
294 s8 fm_amount1;
295 s8 fm_amount2;
296
297 u8 am_src:4;
298 u8 Unused4:4;
299
300 s8 am_amount;
301
302 u8 fc1_mode:4;
303 u8 fc2_mode:4;
304
305 s8 fc1_mod_amount;
306 s8 fc1_keyboard_scaling;
307 s8 fc1_bias;
308 s8 fc2_mod_amount;
309 s8 fc2_keyboard_scaling;
310 s8 fc2_bias;
311
312 u8 randomizer:7;
313 u8 Unused5:1;
314
315 struct wf_envelope envelope1;
316 struct wf_envelope envelope2;
317 struct wf_lfo lfo1;
318 struct wf_lfo lfo2;
319};
320typedef struct wf_patch wavefront_patch;
321
322struct wf_layer
323{
324 u8 patch_number;
325
326 u8 mix_level:7;
327 u8 mute:1;
328
329 u8 split_point:7;
330 u8 play_below:1;
331
332 u8 pan_mod_src:2;
333 u8 pan_or_mod:1;
334 u8 pan:4;
335 u8 split_type:1;
336};
337typedef struct wf_layer wavefront_layer;
338
339struct wf_program
340{
341 struct wf_layer layer[WF_NUM_LAYERS];
342};
343typedef struct wf_program wavefront_program;
344
345struct wf_sample_offset
346{
347 s32 Fraction:4;
348 s32 Integer:20;
349 s32 Unused:8;
350};
351typedef struct wf_sample_offset wavefront_sample_offset;
352
353/* Sample slot types */
354
355#define WF_ST_SAMPLE 0
356#define WF_ST_MULTISAMPLE 1
357#define WF_ST_ALIAS 2
358#define WF_ST_EMPTY 3
359
360/* pseudo's */
361
362#define WF_ST_DRUM 4
363#define WF_ST_PROGRAM 5
364#define WF_ST_PATCH 6
365#define WF_ST_SAMPLEHDR 7
366
367#define WF_ST_MASK 0xf
368
369/* Flags for slot status. These occupy the upper bits of the same byte
370 as a sample type.
371*/
372
373#define WF_SLOT_USED 0x80 /* XXX don't rely on this being accurate */
374#define WF_SLOT_FILLED 0x40
375#define WF_SLOT_ROM 0x20
376
377#define WF_SLOT_MASK 0xf0
378
379/* channel constants */
380
381#define WF_CH_MONO 0
382#define WF_CH_LEFT 1
383#define WF_CH_RIGHT 2
384
385/* Sample formats */
386
387#define LINEAR_16BIT 0
388#define WHITE_NOISE 1
389#define LINEAR_8BIT 2
390#define MULAW_8BIT 3
391
392#define WF_SAMPLE_IS_8BIT(smpl) ((smpl)->SampleResolution&2)
393
394
395/*
396
397 Because most/all of the sample data we pass in via pointers has
398 never been copied (just mmap-ed into user space straight from the
399 disk), it would be nice to allow handling of multi-channel sample
400 data without forcing user-level extraction of the relevant bytes.
401
402 So, we need a way of specifying which channel to use (the WaveFront
403 only handles mono samples in a given slot), and the only way to do
404 this without using some struct other than wavefront_sample as the
405 interface is the awful hack of using the unused bits in a
406 wavefront_sample:
407
408 Val Meaning
409 --- -------
410 0 no channel selection (use channel 1, sample is MONO)
411 1 use first channel, and skip one
412 2 use second channel, and skip one
413 3 use third channel, and skip two
414 4 use fourth channel, skip three
415 5 use fifth channel, skip four
416 6 use six channel, skip five
417
418
419 This can handle up to 4 channels, and anyone downloading >4 channels
420 of sample data just to select one of them needs to find some tools
421 like sox ...
422
423 NOTE: values 0, 1 and 2 correspond to WF_CH_* above. This is
424 important.
425
426*/
427
428#define WF_SET_CHANNEL(samp,chn) \
429 (samp)->Unused1 = chn & 0x1; \
430 (samp)->Unused2 = chn & 0x2; \
431 (samp)->Unused3 = chn & 0x4
432
433#define WF_GET_CHANNEL(samp) \
434 (((samp)->Unused3 << 2)|((samp)->Unused2<<1)|(samp)->Unused1)
435
436typedef struct wf_sample {
437 struct wf_sample_offset sampleStartOffset;
438 struct wf_sample_offset loopStartOffset;
439 struct wf_sample_offset loopEndOffset;
440 struct wf_sample_offset sampleEndOffset;
441 s16 FrequencyBias;
442 u8 SampleResolution:2; /* sample_format */
443 u8 Unused1:1;
444 u8 Loop:1;
445 u8 Bidirectional:1;
446 u8 Unused2:1;
447 u8 Reverse:1;
448 u8 Unused3:1;
449} wavefront_sample;
450
451typedef struct wf_multisample {
452 s16 NumberOfSamples; /* log2 of the number of samples */
453 s16 SampleNumber[NUM_MIDIKEYS];
454} wavefront_multisample;
455
456typedef struct wf_alias {
457 s16 OriginalSample __attribute__ ((packed));
458
459 struct wf_sample_offset sampleStartOffset __attribute__ ((packed));
460 struct wf_sample_offset loopStartOffset __attribute__ ((packed));
461 struct wf_sample_offset sampleEndOffset __attribute__ ((packed));
462 struct wf_sample_offset loopEndOffset __attribute__ ((packed));
463
464 s16 FrequencyBias __attribute__ ((packed));
465
466 u8 SampleResolution:2 __attribute__ ((packed));
467 u8 Unused1:1 __attribute__ ((packed));
468 u8 Loop:1 __attribute__ ((packed));
469 u8 Bidirectional:1 __attribute__ ((packed));
470 u8 Unused2:1 __attribute__ ((packed));
471 u8 Reverse:1 __attribute__ ((packed));
472 u8 Unused3:1 __attribute__ ((packed));
473
474 /* This structure is meant to be padded only to 16 bits on their
475 original. Of course, whoever wrote their documentation didn't
476 realize that sizeof(struct) can be >=
477 sum(sizeof(struct-fields)) and so thought that giving a C level
478 description of the structs used in WavePatch files was
479 sufficient. I suppose it was, as long as you remember the
480 standard 16->32 bit issues.
481 */
482
483 u8 sixteen_bit_padding __attribute__ ((packed));
484} wavefront_alias;
485
486typedef struct wf_drum {
487 u8 PatchNumber;
488 u8 MixLevel:7;
489 u8 Unmute:1;
490 u8 Group:4;
491 u8 Unused1:4;
492 u8 PanModSource:2;
493 u8 PanModulated:1;
494 u8 PanAmount:4;
495 u8 Unused2:1;
496} wavefront_drum;
497
498typedef struct wf_drumkit {
499 struct wf_drum drum[NUM_MIDIKEYS];
500} wavefront_drumkit;
501
502typedef struct wf_channel_programs {
503 u8 Program[NUM_MIDICHANNELS];
504} wavefront_channel_programs;
505
506/* How to get MIDI channel status from the data returned by
507 a WFC_GET_CHANNEL_STATUS command (a struct wf_channel_programs)
508*/
509
510#define WF_CHANNEL_STATUS(ch,wcp) (wcp)[(ch/7)] & (1<<((ch)%7))
511
512typedef union wf_any {
513 wavefront_sample s;
514 wavefront_multisample ms;
515 wavefront_alias a;
516 wavefront_program pr;
517 wavefront_patch p;
518 wavefront_drum d;
519} wavefront_any;
520
521/* Hannu Solvainen hoped that his "patch_info" struct in soundcard.h
522 might work for other wave-table based patch loading situations.
523 Alas, his fears were correct. The WaveFront doesn't even come with
524 just "patches", but several different kind of structures that
525 control the sound generation process.
526 */
527
528typedef struct wf_patch_info {
529
530 /* the first two fields are used by the OSS "patch loading" interface
531 only, and are unused by the current user-level library.
532 */
533
534 s16 key; /* Use WAVEFRONT_PATCH here */
535 u16 devno; /* fill in when sending */
536 u8 subkey; /* WF_ST_{SAMPLE,ALIAS,etc.} */
537
538#define WAVEFRONT_FIND_FREE_SAMPLE_SLOT 999
539
540 u16 number; /* patch/sample/prog number */
541
542 u32 size; /* size of any data included in
543 one of the fields in `hdrptr', or
544 as `dataptr'.
545
546 NOTE: for actual samples, this is
547 the size of the *SELECTED CHANNEL*
548 even if more data is actually available.
549
550 So, a stereo sample (2 channels) of
551 6000 bytes total has `size' = 3000.
552
553 See the macros and comments for
554 WF_{GET,SET}_CHANNEL above.
555
556 */
557 wavefront_any __user *hdrptr; /* user-space ptr to hdr bytes */
558 u16 __user *dataptr; /* actual sample data */
559
560 wavefront_any hdr; /* kernel-space copy of hdr bytes */
561} wavefront_patch_info;
562
563/* The maximum number of bytes we will ever move to or from user space
564 in response to a WFC_* command. This obviously doesn't cover
565 actual sample data.
566*/
567
568#define WF_MAX_READ sizeof(wavefront_multisample)
569#define WF_MAX_WRITE sizeof(wavefront_multisample)
570
571/*
572 This allows us to execute any WF command except the download/upload
573 ones, which are handled differently due to copyin/copyout issues as
574 well as data-nybbling to/from the card.
575 */
576
577typedef struct wavefront_control {
578 int cmd; /* WFC_* */
579 char status; /* return status to user-space */
580 unsigned char rbuf[WF_MAX_READ]; /* bytes read from card */
581 unsigned char wbuf[WF_MAX_WRITE]; /* bytes written to card */
582} wavefront_control;
583
584#define WFCTL_WFCMD 0x1
585#define WFCTL_LOAD_SPP 0x2
586
587/* Modulator table */
588
589#define WF_MOD_LFO1 0
590#define WF_MOD_LFO2 1
591#define WF_MOD_ENV1 2
592#define WF_MOD_ENV2 3
593#define WF_MOD_KEYBOARD 4
594#define WF_MOD_LOGKEY 5
595#define WF_MOD_VELOCITY 6
596#define WF_MOD_LOGVEL 7
597#define WF_MOD_RANDOM 8
598#define WF_MOD_PRESSURE 9
599#define WF_MOD_MOD_WHEEL 10
600#define WF_MOD_1 WF_MOD_MOD_WHEEL
601#define WF_MOD_BREATH 11
602#define WF_MOD_2 WF_MOD_BREATH
603#define WF_MOD_FOOT 12
604#define WF_MOD_4 WF_MOD_FOOT
605#define WF_MOD_VOLUME 13
606#define WF_MOD_7 WF_MOD_VOLUME
607#define WF_MOD_PAN 14
608#define WF_MOD_10 WF_MOD_PAN
609#define WF_MOD_EXPR 15
610#define WF_MOD_11 WF_MOD_EXPR
611
612/* FX-related material */
613
614typedef struct wf_fx_info {
615 int request; /* see list below */
616 long data[4]; /* we don't need much */
617} wavefront_fx_info;
618
619/* support for each of these will be forthcoming once I or someone
620 else has figured out which of the addresses on page 6 and page 7 of
621 the YSS225 control each parameter. Incidentally, these come from
622 the Windows driver interface, but again, Turtle Beach didn't
623 document the API to use them.
624*/
625
626#define WFFX_SETOUTGAIN 0
627#define WFFX_SETSTEREOOUTGAIN 1
628#define WFFX_SETREVERBIN1GAIN 2
629#define WFFX_SETREVERBIN2GAIN 3
630#define WFFX_SETREVERBIN3GAIN 4
631#define WFFX_SETCHORUSINPORT 5
632#define WFFX_SETREVERBIN1PORT 6
633#define WFFX_SETREVERBIN2PORT 7
634#define WFFX_SETREVERBIN3PORT 8
635#define WFFX_SETEFFECTPORT 9
636#define WFFX_SETAUXPORT 10
637#define WFFX_SETREVERBTYPE 11
638#define WFFX_SETREVERBDELAY 12
639#define WFFX_SETCHORUSLFO 13
640#define WFFX_SETCHORUSPMD 14
641#define WFFX_SETCHORUSAMD 15
642#define WFFX_SETEFFECT 16
643#define WFFX_SETBASEALL 17
644#define WFFX_SETREVERBALL 18
645#define WFFX_SETCHORUSALL 20
646#define WFFX_SETREVERBDEF 22
647#define WFFX_SETCHORUSDEF 23
648#define WFFX_DELAYSETINGAIN 24
649#define WFFX_DELAYSETFBGAIN 25
650#define WFFX_DELAYSETFBLPF 26
651#define WFFX_DELAYSETGAIN 27
652#define WFFX_DELAYSETTIME 28
653#define WFFX_DELAYSETFBTIME 29
654#define WFFX_DELAYSETALL 30
655#define WFFX_DELAYSETDEF 32
656#define WFFX_SDELAYSETINGAIN 33
657#define WFFX_SDELAYSETFBGAIN 34
658#define WFFX_SDELAYSETFBLPF 35
659#define WFFX_SDELAYSETGAIN 36
660#define WFFX_SDELAYSETTIME 37
661#define WFFX_SDELAYSETFBTIME 38
662#define WFFX_SDELAYSETALL 39
663#define WFFX_SDELAYSETDEF 41
664#define WFFX_DEQSETINGAIN 42
665#define WFFX_DEQSETFILTER 43
666#define WFFX_DEQSETALL 44
667#define WFFX_DEQSETDEF 46
668#define WFFX_MUTE 47
669#define WFFX_FLANGESETBALANCE 48
670#define WFFX_FLANGESETDELAY 49
671#define WFFX_FLANGESETDWFFX_TH 50
672#define WFFX_FLANGESETFBGAIN 51
673#define WFFX_FLANGESETINGAIN 52
674#define WFFX_FLANGESETLFO 53
675#define WFFX_FLANGESETALL 54
676#define WFFX_FLANGESETDEF 56
677#define WFFX_PITCHSETSHIFT 57
678#define WFFX_PITCHSETBALANCE 58
679#define WFFX_PITCHSETALL 59
680#define WFFX_PITCHSETDEF 61
681#define WFFX_SRSSETINGAIN 62
682#define WFFX_SRSSETSPACE 63
683#define WFFX_SRSSETCENTER 64
684#define WFFX_SRSSETGAIN 65
685#define WFFX_SRSSETMODE 66
686#define WFFX_SRSSETDEF 68
687
688/* Allow direct user-space control over FX memory/coefficient data.
689 In theory this could be used to download the FX microprogram,
690 but it would be a little slower, and involve some weird code.
691 */
692
693#define WFFX_MEMSET 69
694
695#endif /* __SOUND_WAVEFRONT_H__ */
diff --git a/include/sound/wavefront_fx.h b/include/sound/wavefront_fx.h
new file mode 100644
index 000000000000..cec92b141796
--- /dev/null
+++ b/include/sound/wavefront_fx.h
@@ -0,0 +1,9 @@
1#ifndef __SOUND_WAVEFRONT_FX_H
2#define __SOUND_WAVEFRONT_FX_H
3
4extern int snd_wavefront_fx_detect (snd_wavefront_t *);
5extern void snd_wavefront_fx_ioctl (snd_synth_t *sdev,
6 unsigned int cmd,
7 unsigned long arg);
8
9#endif __SOUND_WAVEFRONT_FX_H
diff --git a/include/sound/ymfpci.h b/include/sound/ymfpci.h
new file mode 100644
index 000000000000..4b570684a6aa
--- /dev/null
+++ b/include/sound/ymfpci.h
@@ -0,0 +1,396 @@
1#ifndef __SOUND_YMFPCI_H
2#define __SOUND_YMFPCI_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Definitions for Yahama YMF724/740/744/754 chips
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include "pcm.h"
26#include "rawmidi.h"
27#include "ac97_codec.h"
28#include "timer.h"
29#include <linux/gameport.h>
30
31#ifndef PCI_VENDOR_ID_YAMAHA
32#define PCI_VENDOR_ID_YAMAHA 0x1073
33#endif
34#ifndef PCI_DEVICE_ID_YAMAHA_724
35#define PCI_DEVICE_ID_YAMAHA_724 0x0004
36#endif
37#ifndef PCI_DEVICE_ID_YAMAHA_724F
38#define PCI_DEVICE_ID_YAMAHA_724F 0x000d
39#endif
40#ifndef PCI_DEVICE_ID_YAMAHA_740
41#define PCI_DEVICE_ID_YAMAHA_740 0x000a
42#endif
43#ifndef PCI_DEVICE_ID_YAMAHA_740C
44#define PCI_DEVICE_ID_YAMAHA_740C 0x000c
45#endif
46#ifndef PCI_DEVICE_ID_YAMAHA_744
47#define PCI_DEVICE_ID_YAMAHA_744 0x0010
48#endif
49#ifndef PCI_DEVICE_ID_YAMAHA_754
50#define PCI_DEVICE_ID_YAMAHA_754 0x0012
51#endif
52
53/*
54 * Direct registers
55 */
56
57#define YMFREG(chip, reg) (chip->port + YDSXGR_##reg)
58
59#define YDSXGR_INTFLAG 0x0004
60#define YDSXGR_ACTIVITY 0x0006
61#define YDSXGR_GLOBALCTRL 0x0008
62#define YDSXGR_ZVCTRL 0x000A
63#define YDSXGR_TIMERCTRL 0x0010
64#define YDSXGR_TIMERCOUNT 0x0012
65#define YDSXGR_SPDIFOUTCTRL 0x0018
66#define YDSXGR_SPDIFOUTSTATUS 0x001C
67#define YDSXGR_EEPROMCTRL 0x0020
68#define YDSXGR_SPDIFINCTRL 0x0034
69#define YDSXGR_SPDIFINSTATUS 0x0038
70#define YDSXGR_DSPPROGRAMDL 0x0048
71#define YDSXGR_DLCNTRL 0x004C
72#define YDSXGR_GPIOININTFLAG 0x0050
73#define YDSXGR_GPIOININTENABLE 0x0052
74#define YDSXGR_GPIOINSTATUS 0x0054
75#define YDSXGR_GPIOOUTCTRL 0x0056
76#define YDSXGR_GPIOFUNCENABLE 0x0058
77#define YDSXGR_GPIOTYPECONFIG 0x005A
78#define YDSXGR_AC97CMDDATA 0x0060
79#define YDSXGR_AC97CMDADR 0x0062
80#define YDSXGR_PRISTATUSDATA 0x0064
81#define YDSXGR_PRISTATUSADR 0x0066
82#define YDSXGR_SECSTATUSDATA 0x0068
83#define YDSXGR_SECSTATUSADR 0x006A
84#define YDSXGR_SECCONFIG 0x0070
85#define YDSXGR_LEGACYOUTVOL 0x0080
86#define YDSXGR_LEGACYOUTVOLL 0x0080
87#define YDSXGR_LEGACYOUTVOLR 0x0082
88#define YDSXGR_NATIVEDACOUTVOL 0x0084
89#define YDSXGR_NATIVEDACOUTVOLL 0x0084
90#define YDSXGR_NATIVEDACOUTVOLR 0x0086
91#define YDSXGR_ZVOUTVOL 0x0088
92#define YDSXGR_ZVOUTVOLL 0x0088
93#define YDSXGR_ZVOUTVOLR 0x008A
94#define YDSXGR_SECADCOUTVOL 0x008C
95#define YDSXGR_SECADCOUTVOLL 0x008C
96#define YDSXGR_SECADCOUTVOLR 0x008E
97#define YDSXGR_PRIADCOUTVOL 0x0090
98#define YDSXGR_PRIADCOUTVOLL 0x0090
99#define YDSXGR_PRIADCOUTVOLR 0x0092
100#define YDSXGR_LEGACYLOOPVOL 0x0094
101#define YDSXGR_LEGACYLOOPVOLL 0x0094
102#define YDSXGR_LEGACYLOOPVOLR 0x0096
103#define YDSXGR_NATIVEDACLOOPVOL 0x0098
104#define YDSXGR_NATIVEDACLOOPVOLL 0x0098
105#define YDSXGR_NATIVEDACLOOPVOLR 0x009A
106#define YDSXGR_ZVLOOPVOL 0x009C
107#define YDSXGR_ZVLOOPVOLL 0x009E
108#define YDSXGR_ZVLOOPVOLR 0x009E
109#define YDSXGR_SECADCLOOPVOL 0x00A0
110#define YDSXGR_SECADCLOOPVOLL 0x00A0
111#define YDSXGR_SECADCLOOPVOLR 0x00A2
112#define YDSXGR_PRIADCLOOPVOL 0x00A4
113#define YDSXGR_PRIADCLOOPVOLL 0x00A4
114#define YDSXGR_PRIADCLOOPVOLR 0x00A6
115#define YDSXGR_NATIVEADCINVOL 0x00A8
116#define YDSXGR_NATIVEADCINVOLL 0x00A8
117#define YDSXGR_NATIVEADCINVOLR 0x00AA
118#define YDSXGR_NATIVEDACINVOL 0x00AC
119#define YDSXGR_NATIVEDACINVOLL 0x00AC
120#define YDSXGR_NATIVEDACINVOLR 0x00AE
121#define YDSXGR_BUF441OUTVOL 0x00B0
122#define YDSXGR_BUF441OUTVOLL 0x00B0
123#define YDSXGR_BUF441OUTVOLR 0x00B2
124#define YDSXGR_BUF441LOOPVOL 0x00B4
125#define YDSXGR_BUF441LOOPVOLL 0x00B4
126#define YDSXGR_BUF441LOOPVOLR 0x00B6
127#define YDSXGR_SPDIFOUTVOL 0x00B8
128#define YDSXGR_SPDIFOUTVOLL 0x00B8
129#define YDSXGR_SPDIFOUTVOLR 0x00BA
130#define YDSXGR_SPDIFLOOPVOL 0x00BC
131#define YDSXGR_SPDIFLOOPVOLL 0x00BC
132#define YDSXGR_SPDIFLOOPVOLR 0x00BE
133#define YDSXGR_ADCSLOTSR 0x00C0
134#define YDSXGR_RECSLOTSR 0x00C4
135#define YDSXGR_ADCFORMAT 0x00C8
136#define YDSXGR_RECFORMAT 0x00CC
137#define YDSXGR_P44SLOTSR 0x00D0
138#define YDSXGR_STATUS 0x0100
139#define YDSXGR_CTRLSELECT 0x0104
140#define YDSXGR_MODE 0x0108
141#define YDSXGR_SAMPLECOUNT 0x010C
142#define YDSXGR_NUMOFSAMPLES 0x0110
143#define YDSXGR_CONFIG 0x0114
144#define YDSXGR_PLAYCTRLSIZE 0x0140
145#define YDSXGR_RECCTRLSIZE 0x0144
146#define YDSXGR_EFFCTRLSIZE 0x0148
147#define YDSXGR_WORKSIZE 0x014C
148#define YDSXGR_MAPOFREC 0x0150
149#define YDSXGR_MAPOFEFFECT 0x0154
150#define YDSXGR_PLAYCTRLBASE 0x0158
151#define YDSXGR_RECCTRLBASE 0x015C
152#define YDSXGR_EFFCTRLBASE 0x0160
153#define YDSXGR_WORKBASE 0x0164
154#define YDSXGR_DSPINSTRAM 0x1000
155#define YDSXGR_CTRLINSTRAM 0x4000
156
157#define YDSXG_AC97READCMD 0x8000
158#define YDSXG_AC97WRITECMD 0x0000
159
160#define PCIR_DSXG_LEGACY 0x40
161#define PCIR_DSXG_ELEGACY 0x42
162#define PCIR_DSXG_CTRL 0x48
163#define PCIR_DSXG_PWRCTRL1 0x4a
164#define PCIR_DSXG_PWRCTRL2 0x4e
165#define PCIR_DSXG_FMBASE 0x60
166#define PCIR_DSXG_SBBASE 0x62
167#define PCIR_DSXG_MPU401BASE 0x64
168#define PCIR_DSXG_JOYBASE 0x66
169
170#define YDSXG_DSPLENGTH 0x0080
171#define YDSXG_CTRLLENGTH 0x3000
172
173#define YDSXG_DEFAULT_WORK_SIZE 0x0400
174
175#define YDSXG_PLAYBACK_VOICES 64
176#define YDSXG_CAPTURE_VOICES 2
177#define YDSXG_EFFECT_VOICES 5
178
179#define YMFPCI_LEGACY_SBEN (1 << 0) /* soundblaster enable */
180#define YMFPCI_LEGACY_FMEN (1 << 1) /* OPL3 enable */
181#define YMFPCI_LEGACY_JPEN (1 << 2) /* joystick enable */
182#define YMFPCI_LEGACY_MEN (1 << 3) /* MPU401 enable */
183#define YMFPCI_LEGACY_MIEN (1 << 4) /* MPU RX irq enable */
184#define YMFPCI_LEGACY_IOBITS (1 << 5) /* i/o bits range, 0 = 16bit, 1 =10bit */
185#define YMFPCI_LEGACY_SDMA (3 << 6) /* SB DMA select */
186#define YMFPCI_LEGACY_SBIRQ (7 << 8) /* SB IRQ select */
187#define YMFPCI_LEGACY_MPUIRQ (7 << 11) /* MPU IRQ select */
188#define YMFPCI_LEGACY_SIEN (1 << 14) /* serialized IRQ */
189#define YMFPCI_LEGACY_LAD (1 << 15) /* legacy audio disable */
190
191#define YMFPCI_LEGACY2_FMIO (3 << 0) /* OPL3 i/o address (724/740) */
192#define YMFPCI_LEGACY2_SBIO (3 << 2) /* SB i/o address (724/740) */
193#define YMFPCI_LEGACY2_MPUIO (3 << 4) /* MPU401 i/o address (724/740) */
194#define YMFPCI_LEGACY2_JSIO (3 << 6) /* joystick i/o address (724/740) */
195#define YMFPCI_LEGACY2_MAIM (1 << 8) /* MPU401 ack intr mask */
196#define YMFPCI_LEGACY2_SMOD (3 << 11) /* SB DMA mode */
197#define YMFPCI_LEGACY2_SBVER (3 << 13) /* SB version select */
198#define YMFPCI_LEGACY2_IMOD (1 << 15) /* legacy IRQ mode */
199/* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
200
201#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
202#define SUPPORT_JOYSTICK
203#endif
204
205/*
206 *
207 */
208
209typedef struct _snd_ymfpci_playback_bank {
210 u32 format;
211 u32 loop_default;
212 u32 base; /* 32-bit address */
213 u32 loop_start; /* 32-bit offset */
214 u32 loop_end; /* 32-bit offset */
215 u32 loop_frac; /* 8-bit fraction - loop_start */
216 u32 delta_end; /* pitch delta end */
217 u32 lpfK_end;
218 u32 eg_gain_end;
219 u32 left_gain_end;
220 u32 right_gain_end;
221 u32 eff1_gain_end;
222 u32 eff2_gain_end;
223 u32 eff3_gain_end;
224 u32 lpfQ;
225 u32 status;
226 u32 num_of_frames;
227 u32 loop_count;
228 u32 start;
229 u32 start_frac;
230 u32 delta;
231 u32 lpfK;
232 u32 eg_gain;
233 u32 left_gain;
234 u32 right_gain;
235 u32 eff1_gain;
236 u32 eff2_gain;
237 u32 eff3_gain;
238 u32 lpfD1;
239 u32 lpfD2;
240} snd_ymfpci_playback_bank_t;
241
242typedef struct _snd_ymfpci_capture_bank {
243 u32 base; /* 32-bit address */
244 u32 loop_end; /* 32-bit offset */
245 u32 start; /* 32-bit offset */
246 u32 num_of_loops; /* counter */
247} snd_ymfpci_capture_bank_t;
248
249typedef struct _snd_ymfpci_effect_bank {
250 u32 base; /* 32-bit address */
251 u32 loop_end; /* 32-bit offset */
252 u32 start; /* 32-bit offset */
253 u32 temp;
254} snd_ymfpci_effect_bank_t;
255
256typedef struct _snd_ymfpci_voice ymfpci_voice_t;
257typedef struct _snd_ymfpci_pcm ymfpci_pcm_t;
258typedef struct _snd_ymfpci ymfpci_t;
259
260typedef enum {
261 YMFPCI_PCM,
262 YMFPCI_SYNTH,
263 YMFPCI_MIDI
264} ymfpci_voice_type_t;
265
266struct _snd_ymfpci_voice {
267 ymfpci_t *chip;
268 int number;
269 unsigned int use: 1,
270 pcm: 1,
271 synth: 1,
272 midi: 1;
273 snd_ymfpci_playback_bank_t *bank;
274 dma_addr_t bank_addr;
275 void (*interrupt)(ymfpci_t *chip, ymfpci_voice_t *voice);
276 ymfpci_pcm_t *ypcm;
277};
278
279typedef enum {
280 PLAYBACK_VOICE,
281 CAPTURE_REC,
282 CAPTURE_AC97,
283 EFFECT_DRY_LEFT,
284 EFFECT_DRY_RIGHT,
285 EFFECT_EFF1,
286 EFFECT_EFF2,
287 EFFECT_EFF3
288} snd_ymfpci_pcm_type_t;
289
290struct _snd_ymfpci_pcm {
291 ymfpci_t *chip;
292 snd_ymfpci_pcm_type_t type;
293 snd_pcm_substream_t *substream;
294 ymfpci_voice_t *voices[2]; /* playback only */
295 unsigned int running: 1;
296 unsigned int output_front: 1;
297 unsigned int output_rear: 1;
298 u32 period_size; /* cached from runtime->period_size */
299 u32 buffer_size; /* cached from runtime->buffer_size */
300 u32 period_pos;
301 u32 last_pos;
302 u32 capture_bank_number;
303 u32 shift;
304};
305
306struct _snd_ymfpci {
307 int irq;
308
309 unsigned int device_id; /* PCI device ID */
310 unsigned int rev; /* PCI revision */
311 unsigned long reg_area_phys;
312 void __iomem *reg_area_virt;
313 struct resource *res_reg_area;
314 struct resource *fm_res;
315 struct resource *mpu_res;
316
317 unsigned short old_legacy_ctrl;
318#ifdef SUPPORT_JOYSTICK
319 struct gameport *gameport;
320#endif
321
322 struct snd_dma_buffer work_ptr;
323
324 unsigned int bank_size_playback;
325 unsigned int bank_size_capture;
326 unsigned int bank_size_effect;
327 unsigned int work_size;
328
329 void *bank_base_playback;
330 void *bank_base_capture;
331 void *bank_base_effect;
332 void *work_base;
333 dma_addr_t bank_base_playback_addr;
334 dma_addr_t bank_base_capture_addr;
335 dma_addr_t bank_base_effect_addr;
336 dma_addr_t work_base_addr;
337 struct snd_dma_buffer ac3_tmp_base;
338
339 u32 *ctrl_playback;
340 snd_ymfpci_playback_bank_t *bank_playback[YDSXG_PLAYBACK_VOICES][2];
341 snd_ymfpci_capture_bank_t *bank_capture[YDSXG_CAPTURE_VOICES][2];
342 snd_ymfpci_effect_bank_t *bank_effect[YDSXG_EFFECT_VOICES][2];
343
344 int start_count;
345
346 u32 active_bank;
347 ymfpci_voice_t voices[64];
348
349 ac97_bus_t *ac97_bus;
350 ac97_t *ac97;
351 snd_rawmidi_t *rawmidi;
352 snd_timer_t *timer;
353
354 struct pci_dev *pci;
355 snd_card_t *card;
356 snd_pcm_t *pcm;
357 snd_pcm_t *pcm2;
358 snd_pcm_t *pcm_spdif;
359 snd_pcm_t *pcm_4ch;
360 snd_pcm_substream_t *capture_substream[YDSXG_CAPTURE_VOICES];
361 snd_pcm_substream_t *effect_substream[YDSXG_EFFECT_VOICES];
362 snd_kcontrol_t *ctl_vol_recsrc;
363 snd_kcontrol_t *ctl_vol_adcrec;
364 snd_kcontrol_t *ctl_vol_spdifrec;
365 unsigned short spdif_bits, spdif_pcm_bits;
366 snd_kcontrol_t *spdif_pcm_ctl;
367 int mode_dup4ch;
368 int rear_opened;
369 int spdif_opened;
370
371 spinlock_t reg_lock;
372 spinlock_t voice_lock;
373 wait_queue_head_t interrupt_sleep;
374 atomic_t interrupt_sleep_count;
375 snd_info_entry_t *proc_entry;
376
377#ifdef CONFIG_PM
378 u32 *saved_regs;
379 u32 saved_ydsxgr_mode;
380#endif
381};
382
383int snd_ymfpci_create(snd_card_t * card,
384 struct pci_dev *pci,
385 unsigned short old_legacy_ctrl,
386 ymfpci_t ** rcodec);
387void snd_ymfpci_free_gameport(ymfpci_t *chip);
388
389int snd_ymfpci_pcm(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
390int snd_ymfpci_pcm2(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
391int snd_ymfpci_pcm_spdif(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
392int snd_ymfpci_pcm_4ch(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
393int snd_ymfpci_mixer(ymfpci_t *chip, int rear_switch);
394int snd_ymfpci_timer(ymfpci_t *chip, int device);
395
396#endif /* __SOUND_YMFPCI_H */