12 files changed, 127 insertions, 104 deletions

diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 6ad72f92469c..353ba256f368 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -191,7 +191,6 @@ extern bool wmi_has_guid(const char *guid);
 #define ACPI_VIDEO_BACKLIGHT_DMI_VIDEO                  0x0200
 #define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VENDOR          0x0400
 #define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VIDEO           0x0800
-#define ACPI_VIDEO_SKIP_BACKLIGHT                       0x1000
 
 #if defined(CONFIG_ACPI_VIDEO) || defined(CONFIG_ACPI_VIDEO_MODULE)
 
diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h
index 297462b9f41a..e9ac882868c0 100644
--- a/include/linux/cgroup.h
+++ b/include/linux/cgroup.h
@@ -542,8 +542,7 @@ int cgroup_rm_cftypes(struct cgroup_subsys *ss, struct cftype *cfts);
 bool cgroup_is_descendant(struct cgroup *cgrp, struct cgroup *ancestor);
 
 int cgroup_path(const struct cgroup *cgrp, char *buf, int buflen);
-int task_cgroup_path_from_hierarchy(struct task_struct *task, int hierarchy_id,
-                                    char *buf, size_t buflen);
+int task_cgroup_path(struct task_struct *task, char *buf, size_t buflen);
 
 int cgroup_task_count(const struct cgroup *cgrp);
 
diff --git a/include/linux/cgroup_subsys.h b/include/linux/cgroup_subsys.h
index 6e7ec64b69ab..b613ffd402d1 100644
--- a/include/linux/cgroup_subsys.h
+++ b/include/linux/cgroup_subsys.h
@@ -1,86 +1,55 @@
-/* Add subsystem definitions of the form SUBSYS(<name>) in this
- * file. Surround each one by a line of comment markers so that
- * patches don't collide
+/*
+ * List of cgroup subsystems.
+ *
+ * DO NOT ADD ANY SUBSYSTEM WITHOUT EXPLICIT ACKS FROM CGROUP MAINTAINERS.
  */
-
-/* */
-
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_CPUSETS)
 SUBSYS(cpuset)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_CGROUP_DEBUG)
 SUBSYS(debug)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_CGROUP_SCHED)
 SUBSYS(cpu_cgroup)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_CGROUP_CPUACCT)
 SUBSYS(cpuacct)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_MEMCG)
 SUBSYS(mem_cgroup)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_CGROUP_DEVICE)
 SUBSYS(devices)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_CGROUP_FREEZER)
 SUBSYS(freezer)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_NET_CLS_CGROUP)
 SUBSYS(net_cls)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_BLK_CGROUP)
 SUBSYS(blkio)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_CGROUP_PERF)
 SUBSYS(perf)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_NETPRIO_CGROUP)
 SUBSYS(net_prio)
 #endif
 
-/* */
-
 #if IS_SUBSYS_ENABLED(CONFIG_CGROUP_HUGETLB)
 SUBSYS(hugetlb)
 #endif
-
-/* */
-
-#ifdef CONFIG_CGROUP_BCACHE
-SUBSYS(bcache)
-#endif
-
-/* */
+/*
+ * DO NOT ADD ANY SUBSYSTEM WITHOUT EXPLICIT ACKS FROM CGROUP MAINTAINERS.
+ */
diff --git a/include/linux/crc-t10dif.h b/include/linux/crc-t10dif.h
index b3cb71f0d3b0..a9c96d865ee7 100644
--- a/include/linux/crc-t10dif.h
+++ b/include/linux/crc-t10dif.h
@@ -3,10 +3,6 @@
 
 #include <linux/types.h>
 
-#define CRC_T10DIF_DIGEST_SIZE 2
-#define CRC_T10DIF_BLOCK_SIZE 1
-
-__u16 crc_t10dif_generic(__u16 crc, const unsigned char *buffer, size_t len);
 __u16 crc_t10dif(unsigned char const *, size_t);
 
 #endif
diff --git a/include/linux/drbd.h b/include/linux/drbd.h
index 1b4d4ee1168f..de7d74ab3de6 100644
--- a/include/linux/drbd.h
+++ b/include/linux/drbd.h
@@ -177,7 +177,11 @@ enum drbd_ret_code {
         ERR_NEED_APV_100        = 163,
         ERR_NEED_ALLOW_TWO_PRI  = 164,
         ERR_MD_UNCLEAN          = 165,
-
+        ERR_MD_LAYOUT_CONNECTED = 166,
+        ERR_MD_LAYOUT_TOO_BIG   = 167,
+        ERR_MD_LAYOUT_TOO_SMALL = 168,
+        ERR_MD_LAYOUT_NO_FIT    = 169,
+        ERR_IMPLICIT_SHRINK     = 170,
         /* insert new ones above this line */
         AFTER_LAST_ERR_CODE
 };
diff --git a/include/linux/drbd_genl.h b/include/linux/drbd_genl.h
index d0d8fac8a6e4..e8c44572b8cb 100644
--- a/include/linux/drbd_genl.h
+++ b/include/linux/drbd_genl.h
@@ -181,6 +181,8 @@ GENL_struct(DRBD_NLA_RESIZE_PARMS, 7, resize_parms,
         __u64_field(1, DRBD_GENLA_F_MANDATORY,  resize_size)
         __flg_field(2, DRBD_GENLA_F_MANDATORY,  resize_force)
         __flg_field(3, DRBD_GENLA_F_MANDATORY,  no_resync)
+        __u32_field_def(4, 0 /* OPTIONAL */, al_stripes, DRBD_AL_STRIPES_DEF)
+        __u32_field_def(5, 0 /* OPTIONAL */, al_stripe_size, DRBD_AL_STRIPE_SIZE_DEF)
 )
 
 GENL_struct(DRBD_NLA_STATE_INFO, 8, state_info,
diff --git a/include/linux/drbd_limits.h b/include/linux/drbd_limits.h
index 1fedf2b17cc8..17e50bb00521 100644
--- a/include/linux/drbd_limits.h
+++ b/include/linux/drbd_limits.h
@@ -215,4 +215,13 @@
 #define DRBD_ALWAYS_ASBP_DEF    0
 #define DRBD_USE_RLE_DEF        1
 
+#define DRBD_AL_STRIPES_MIN     1
+#define DRBD_AL_STRIPES_MAX     1024
+#define DRBD_AL_STRIPES_DEF     1
+#define DRBD_AL_STRIPES_SCALE   '1'
+
+#define DRBD_AL_STRIPE_SIZE_MIN   4
+#define DRBD_AL_STRIPE_SIZE_MAX   16777216
+#define DRBD_AL_STRIPE_SIZE_DEF   32
+#define DRBD_AL_STRIPE_SIZE_SCALE 'k' /* kilobytes */
 #endif
diff --git a/include/linux/edac.h b/include/linux/edac.h
index 0b763276f619..5c6d7fbaf89e 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -622,7 +622,7 @@ struct edac_raw_error_desc {
  */
 struct mem_ctl_info {
         struct device                   dev;
-        struct bus_type                 bus;
+        struct bus_type                 *bus;
 
         struct list_head link;  /* for global list of mem_ctl_info structs */
 
@@ -742,4 +742,9 @@ struct mem_ctl_info {
 #endif
 };
 
+/*
+ * Maximum number of memory controllers in the coherent fabric.
+ */
+#define EDAC_MAX_MCS    16
+
 #endif
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index dab34a1deb2c..b6bdcd66c07d 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -103,15 +103,15 @@
 #define IMX6Q_GPR1_EXC_MON_MASK                 BIT(22)
 #define IMX6Q_GPR1_EXC_MON_OKAY                 0x0
 #define IMX6Q_GPR1_EXC_MON_SLVE                 BIT(22)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK           BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX          BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK           BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX          BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK           BIT(19)
+#define IMX6Q_GPR1_ENET_CLK_SEL_MASK            BIT(21)
+#define IMX6Q_GPR1_ENET_CLK_SEL_PAD             0
+#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP          BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK           BIT(20)
 #define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX          BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX          BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK           BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET         0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX          BIT(19)
 #define IMX6Q_GPR1_PCIE_TEST_PD                 BIT(18)
 #define IMX6Q_GPR1_IPU_VPU_MUX_MASK             BIT(17)
 #define IMX6Q_GPR1_IPU_VPU_MUX_IPU1             0x0
@@ -279,41 +279,88 @@
 #define IMX6Q_GPR13_CAN2_STOP_REQ               BIT(29)
 #define IMX6Q_GPR13_CAN1_STOP_REQ               BIT(28)
 #define IMX6Q_GPR13_ENET_STOP_REQ               BIT(27)
-#define IMX6Q_GPR13_SATA_PHY_8_MASK             (0x7 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB           (0x0 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB           (0x1 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB           (0x2 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB           (0x3 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB           (0x4 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB           (0x5 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB           (0x6 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB           (0x7 << 24)
-#define IMX6Q_GPR13_SATA_PHY_7_MASK             (0x1f << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1I           (0x10 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1M           (0x10 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1X           (0x1a << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2I           (0x12 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2M           (0x12 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2X           (0x1a << 19)
-#define IMX6Q_GPR13_SATA_PHY_6_MASK             (0x7 << 16)
-#define IMX6Q_GPR13_SATA_SPEED_MASK             BIT(15)
-#define IMX6Q_GPR13_SATA_SPEED_1P5G             0x0
-#define IMX6Q_GPR13_SATA_SPEED_3P0G             BIT(15)
-#define IMX6Q_GPR13_SATA_PHY_5                  BIT(14)
-#define IMX6Q_GPR13_SATA_PHY_4_MASK             (0x7 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_16_16            (0x0 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_14_16            (0x1 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_12_16            (0x2 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_10_16            (0x3 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_9_16             (0x4 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_8_16             (0x5 << 11)
-#define IMX6Q_GPR13_SATA_PHY_3_MASK             (0xf << 7)
-#define IMX6Q_GPR13_SATA_PHY_3_OFF              0x7
-#define IMX6Q_GPR13_SATA_PHY_2_MASK             (0x1f << 2)
-#define IMX6Q_GPR13_SATA_PHY_2_OFF              0x2
-#define IMX6Q_GPR13_SATA_PHY_1_MASK             (0x3 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_FAST             (0x0 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_MED              (0x1 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_SLOW             (0x2 << 0)
-
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK         (0x7 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB       (0x0 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB       (0x1 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB       (0x2 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB       (0x3 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB       (0x4 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB       (0x5 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB       (0x6 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB       (0x7 << 24)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK        (0x1f << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I      (0x10 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M      (0x10 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X      (0x1a << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I      (0x12 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M      (0x12 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X      (0x1a << 19)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK      (0x7 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F     (0x0 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F     (0x1 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F     (0x2 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F     (0x3 << 16)
+#define IMX6Q_GPR13_SATA_SPD_MODE_MASK          BIT(15)
+#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G          0x0
+#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G          BIT(15)
+#define IMX6Q_GPR13_SATA_MPLL_SS_EN             BIT(14)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK          (0x7 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16         (0x0 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16         (0x1 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16         (0x2 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16         (0x3 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16          (0x4 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16          (0x5 << 11)
+#define IMX6Q_GPR13_SATA_TX_BOOST_MASK          (0xf << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB       (0x0 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB       (0x1 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB       (0x2 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB       (0x3 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB       (0x4 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB       (0x5 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB       (0x6 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB       (0x7 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB       (0x8 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB       (0x9 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB       (0xa << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB       (0xb << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB       (0xc << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB       (0xd << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB       (0xe << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB       (0xf << 7)
+#define IMX6Q_GPR13_SATA_TX_LVL_MASK            (0x1f << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V         (0x00 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V         (0x01 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V         (0x02 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V         (0x03 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V         (0x04 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V         (0x05 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V         (0x06 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V         (0x07 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V         (0x08 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V         (0x09 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V         (0x0a << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V         (0x0b << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V         (0x0c << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V         (0x0d << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V         (0x0e << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V         (0x0f << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V         (0x10 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V         (0x11 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V         (0x12 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V         (0x13 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V         (0x14 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V         (0x15 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V         (0x16 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V         (0x17 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V         (0x18 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V         (0x19 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V         (0x1a << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V         (0x1b << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V         (0x1c << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V         (0x1d << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V         (0x1e << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V         (0x1f << 2)
+#define IMX6Q_GPR13_SATA_MPLL_CLK_EN            BIT(1)
+#define IMX6Q_GPR13_SATA_TX_EDGE_RATE           BIT(0)
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
diff --git a/include/linux/platform_data/mmc-pxamci.h b/include/linux/platform_data/mmc-pxamci.h
index 9eb515bb799d..1706b3597ce0 100644
--- a/include/linux/platform_data/mmc-pxamci.h
+++ b/include/linux/platform_data/mmc-pxamci.h
@@ -12,7 +12,7 @@ struct pxamci_platform_data {
         unsigned long detect_delay_ms;          /* delay in millisecond before detecting cards after interrupt */
         int (*init)(struct device *, irq_handler_t , void *);
         int (*get_ro)(struct device *);
-        void (*setpower)(struct device *, unsigned int);
+        int (*setpower)(struct device *, unsigned int);
         void (*exit)(struct device *, void *);
         int gpio_card_detect;                   /* gpio detecting card insertion */
         int gpio_card_ro;                       /* gpio detecting read only toggle */
diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h
index 382cf710ca9a..5b1c9848124c 100644
--- a/include/linux/shdma-base.h
+++ b/include/linux/shdma-base.h
@@ -124,6 +124,10 @@ void shdma_chan_remove(struct shdma_chan *schan);
 int shdma_init(struct device *dev, struct shdma_dev *sdev,
                     int chan_num);
 void shdma_cleanup(struct shdma_dev *sdev);
+#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
 bool shdma_chan_filter(struct dma_chan *chan, void *arg);
+#else
+#define shdma_chan_filter NULL
+#endif
 
 #endif
diff --git a/include/linux/usb.h b/include/linux/usb.h
index a232b7ece1f6..0eec2689b955 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -367,17 +367,6 @@ struct usb_bus {
 
 /* ----------------------------------------------------------------------- */
 
-/* This is arbitrary.
- * From USB 2.0 spec Table 11-13, offset 7, a hub can
- * have up to 255 ports. The most yet reported is 10.
- *
- * Current Wireless USB host hardware (Intel i1480 for example) allows
- * up to 22 devices to connect. Upcoming hardware might raise that
- * limit. Because the arrays need to add a bit for hub status data, we
- * do 31, so plus one evens out to four bytes.
- */
-#define USB_MAXCHILDREN         (31)
-
 struct usb_tt;
 
 enum usb_device_removable {