diff options
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/mfd/wm8994/core.h | 8 | ||||
-rw-r--r-- | include/linux/mfd/wm8994/pdata.h | 17 | ||||
-rw-r--r-- | include/linux/mfd/wm8994/registers.h | 302 |
3 files changed, 327 insertions, 0 deletions
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h index de79baee4925..3fd36845ca45 100644 --- a/include/linux/mfd/wm8994/core.h +++ b/include/linux/mfd/wm8994/core.h | |||
@@ -17,6 +17,11 @@ | |||
17 | 17 | ||
18 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
19 | 19 | ||
20 | enum wm8994_type { | ||
21 | WM8994 = 0, | ||
22 | WM8958 = 1, | ||
23 | }; | ||
24 | |||
20 | struct regulator_dev; | 25 | struct regulator_dev; |
21 | struct regulator_bulk_data; | 26 | struct regulator_bulk_data; |
22 | 27 | ||
@@ -48,6 +53,8 @@ struct wm8994 { | |||
48 | struct mutex io_lock; | 53 | struct mutex io_lock; |
49 | struct mutex irq_lock; | 54 | struct mutex irq_lock; |
50 | 55 | ||
56 | enum wm8994_type type; | ||
57 | |||
51 | struct device *dev; | 58 | struct device *dev; |
52 | int (*read_dev)(struct wm8994 *wm8994, unsigned short reg, | 59 | int (*read_dev)(struct wm8994 *wm8994, unsigned short reg, |
53 | int bytes, void *dest); | 60 | int bytes, void *dest); |
@@ -68,6 +75,7 @@ struct wm8994 { | |||
68 | u16 gpio_regs[WM8994_NUM_GPIO_REGS]; | 75 | u16 gpio_regs[WM8994_NUM_GPIO_REGS]; |
69 | 76 | ||
70 | struct regulator_dev *dbvdd; | 77 | struct regulator_dev *dbvdd; |
78 | int num_supplies; | ||
71 | struct regulator_bulk_data *supplies; | 79 | struct regulator_bulk_data *supplies; |
72 | }; | 80 | }; |
73 | 81 | ||
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h index add8a1b8bcf0..9eab263658be 100644 --- a/include/linux/mfd/wm8994/pdata.h +++ b/include/linux/mfd/wm8994/pdata.h | |||
@@ -30,6 +30,8 @@ struct wm8994_ldo_pdata { | |||
30 | 30 | ||
31 | #define WM8994_DRC_REGS 5 | 31 | #define WM8994_DRC_REGS 5 |
32 | #define WM8994_EQ_REGS 20 | 32 | #define WM8994_EQ_REGS 20 |
33 | #define WM8958_MBC_CUTOFF_REGS 20 | ||
34 | #define WM8958_MBC_COEFF_REGS 48 | ||
33 | 35 | ||
34 | /** | 36 | /** |
35 | * DRC configurations are specified with a label and a set of register | 37 | * DRC configurations are specified with a label and a set of register |
@@ -59,6 +61,18 @@ struct wm8994_retune_mobile_cfg { | |||
59 | u16 regs[WM8994_EQ_REGS]; | 61 | u16 regs[WM8994_EQ_REGS]; |
60 | }; | 62 | }; |
61 | 63 | ||
64 | /** | ||
65 | * Multiband compressor configurations are specified with a label and | ||
66 | * two sets of values to write. Configurations are expected to be | ||
67 | * generated using the multiband compressor configuration panel in | ||
68 | * WISCE - see http://www.wolfsonmicro.com/wisce/ | ||
69 | */ | ||
70 | struct wm8958_mbc_cfg { | ||
71 | const char *name; | ||
72 | u16 cutoff_regs[WM8958_MBC_CUTOFF_REGS]; | ||
73 | u16 coeff_regs[WM8958_MBC_COEFF_REGS]; | ||
74 | }; | ||
75 | |||
62 | struct wm8994_pdata { | 76 | struct wm8994_pdata { |
63 | int gpio_base; | 77 | int gpio_base; |
64 | 78 | ||
@@ -78,6 +92,9 @@ struct wm8994_pdata { | |||
78 | int num_retune_mobile_cfgs; | 92 | int num_retune_mobile_cfgs; |
79 | struct wm8994_retune_mobile_cfg *retune_mobile_cfgs; | 93 | struct wm8994_retune_mobile_cfg *retune_mobile_cfgs; |
80 | 94 | ||
95 | int num_mbc_cfgs; | ||
96 | struct wm8958_mbc_cfg *mbc_cfgs; | ||
97 | |||
81 | /* LINEOUT can be differential or single ended */ | 98 | /* LINEOUT can be differential or single ended */ |
82 | unsigned int lineout1_diff:1; | 99 | unsigned int lineout1_diff:1; |
83 | unsigned int lineout2_diff:1; | 100 | unsigned int lineout2_diff:1; |
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h index 967f62f54159..be072faec6f0 100644 --- a/include/linux/mfd/wm8994/registers.h +++ b/include/linux/mfd/wm8994/registers.h | |||
@@ -64,12 +64,16 @@ | |||
64 | #define WM8994_LDO_1 0x3B | 64 | #define WM8994_LDO_1 0x3B |
65 | #define WM8994_LDO_2 0x3C | 65 | #define WM8994_LDO_2 0x3C |
66 | #define WM8994_CHARGE_PUMP_1 0x4C | 66 | #define WM8994_CHARGE_PUMP_1 0x4C |
67 | #define WM8958_CHARGE_PUMP_2 0x4D | ||
67 | #define WM8994_CLASS_W_1 0x51 | 68 | #define WM8994_CLASS_W_1 0x51 |
68 | #define WM8994_DC_SERVO_1 0x54 | 69 | #define WM8994_DC_SERVO_1 0x54 |
69 | #define WM8994_DC_SERVO_2 0x55 | 70 | #define WM8994_DC_SERVO_2 0x55 |
70 | #define WM8994_DC_SERVO_4 0x57 | 71 | #define WM8994_DC_SERVO_4 0x57 |
71 | #define WM8994_DC_SERVO_READBACK 0x58 | 72 | #define WM8994_DC_SERVO_READBACK 0x58 |
72 | #define WM8994_ANALOGUE_HP_1 0x60 | 73 | #define WM8994_ANALOGUE_HP_1 0x60 |
74 | #define WM8958_MIC_DETECT_1 0xD0 | ||
75 | #define WM8958_MIC_DETECT_2 0xD1 | ||
76 | #define WM8958_MIC_DETECT_3 0xD2 | ||
73 | #define WM8994_CHIP_REVISION 0x100 | 77 | #define WM8994_CHIP_REVISION 0x100 |
74 | #define WM8994_CONTROL_INTERFACE 0x101 | 78 | #define WM8994_CONTROL_INTERFACE 0x101 |
75 | #define WM8994_WRITE_SEQUENCER_CTRL_1 0x110 | 79 | #define WM8994_WRITE_SEQUENCER_CTRL_1 0x110 |
@@ -109,6 +113,10 @@ | |||
109 | #define WM8994_AIF2DAC_LRCLK 0x315 | 113 | #define WM8994_AIF2DAC_LRCLK 0x315 |
110 | #define WM8994_AIF2DAC_DATA 0x316 | 114 | #define WM8994_AIF2DAC_DATA 0x316 |
111 | #define WM8994_AIF2ADC_DATA 0x317 | 115 | #define WM8994_AIF2ADC_DATA 0x317 |
116 | #define WM8958_AIF3_CONTROL_1 0x320 | ||
117 | #define WM8958_AIF3_CONTROL_2 0x321 | ||
118 | #define WM8958_AIF3DAC_DATA 0x322 | ||
119 | #define WM8958_AIF3ADC_DATA 0x323 | ||
112 | #define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400 | 120 | #define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400 |
113 | #define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401 | 121 | #define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401 |
114 | #define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402 | 122 | #define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402 |
@@ -242,6 +250,83 @@ | |||
242 | #define WM8994_INTERRUPT_STATUS_2_MASK 0x739 | 250 | #define WM8994_INTERRUPT_STATUS_2_MASK 0x739 |
243 | #define WM8994_INTERRUPT_CONTROL 0x740 | 251 | #define WM8994_INTERRUPT_CONTROL 0x740 |
244 | #define WM8994_IRQ_DEBOUNCE 0x748 | 252 | #define WM8994_IRQ_DEBOUNCE 0x748 |
253 | #define WM8958_DSP2_PROGRAM 0x900 | ||
254 | #define WM8958_DSP2_CONFIG 0x901 | ||
255 | #define WM8958_DSP2_MAGICNUM 0xA00 | ||
256 | #define WM8958_DSP2_RELEASEYEAR 0xA01 | ||
257 | #define WM8958_DSP2_RELEASEMONTHDAY 0xA02 | ||
258 | #define WM8958_DSP2_RELEASETIME 0xA03 | ||
259 | #define WM8958_DSP2_VERMAJMIN 0xA04 | ||
260 | #define WM8958_DSP2_VERBUILD 0xA05 | ||
261 | #define WM8958_DSP2_EXECCONTROL 0xA0D | ||
262 | #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200 | ||
263 | #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201 | ||
264 | #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202 | ||
265 | #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2 0x2203 | ||
266 | #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1 0x2204 | ||
267 | #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2 0x2205 | ||
268 | #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1 0x2206 | ||
269 | #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2 0x2207 | ||
270 | #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1 0x2208 | ||
271 | #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2 0x2209 | ||
272 | #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1 0x220A | ||
273 | #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2 0x220B | ||
274 | #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1 0x220C | ||
275 | #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2 0x220D | ||
276 | #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1 0x220E | ||
277 | #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2 0x220F | ||
278 | #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1 0x2210 | ||
279 | #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2 0x2211 | ||
280 | #define WM8958_MBC_BAND_1_LOWER_CUTOFF_1 0x2212 | ||
281 | #define WM8958_MBC_BAND_1_LOWER_CUTOFF_2 0x2213 | ||
282 | #define WM8958_MBC_BAND_1_K_1 0x2400 | ||
283 | #define WM8958_MBC_BAND_1_K_2 0x2401 | ||
284 | #define WM8958_MBC_BAND_1_N1_1 0x2402 | ||
285 | #define WM8958_MBC_BAND_1_N1_2 0x2403 | ||
286 | #define WM8958_MBC_BAND_1_N2_1 0x2404 | ||
287 | #define WM8958_MBC_BAND_1_N2_2 0x2405 | ||
288 | #define WM8958_MBC_BAND_1_N3_1 0x2406 | ||
289 | #define WM8958_MBC_BAND_1_N3_2 0x2407 | ||
290 | #define WM8958_MBC_BAND_1_N4_1 0x2408 | ||
291 | #define WM8958_MBC_BAND_1_N4_2 0x2409 | ||
292 | #define WM8958_MBC_BAND_1_N5_1 0x240A | ||
293 | #define WM8958_MBC_BAND_1_N5_2 0x240B | ||
294 | #define WM8958_MBC_BAND_1_X1_1 0x240C | ||
295 | #define WM8958_MBC_BAND_1_X1_2 0x240D | ||
296 | #define WM8958_MBC_BAND_1_X2_1 0x240E | ||
297 | #define WM8958_MBC_BAND_1_X2_2 0x240F | ||
298 | #define WM8958_MBC_BAND_1_X3_1 0x2410 | ||
299 | #define WM8958_MBC_BAND_1_X3_2 0x2411 | ||
300 | #define WM8958_MBC_BAND_1_ATTACK_1 0x2412 | ||
301 | #define WM8958_MBC_BAND_1_ATTACK_2 0x2413 | ||
302 | #define WM8958_MBC_BAND_1_DECAY_1 0x2414 | ||
303 | #define WM8958_MBC_BAND_1_DECAY_2 0x2415 | ||
304 | #define WM8958_MBC_BAND_2_K_1 0x2416 | ||
305 | #define WM8958_MBC_BAND_2_K_2 0x2417 | ||
306 | #define WM8958_MBC_BAND_2_N1_1 0x2418 | ||
307 | #define WM8958_MBC_BAND_2_N1_2 0x2419 | ||
308 | #define WM8958_MBC_BAND_2_N2_1 0x241A | ||
309 | #define WM8958_MBC_BAND_2_N2_2 0x241B | ||
310 | #define WM8958_MBC_BAND_2_N3_1 0x241C | ||
311 | #define WM8958_MBC_BAND_2_N3_2 0x241D | ||
312 | #define WM8958_MBC_BAND_2_N4_1 0x241E | ||
313 | #define WM8958_MBC_BAND_2_N4_2 0x241F | ||
314 | #define WM8958_MBC_BAND_2_N5_1 0x2420 | ||
315 | #define WM8958_MBC_BAND_2_N5_2 0x2421 | ||
316 | #define WM8958_MBC_BAND_2_X1_1 0x2422 | ||
317 | #define WM8958_MBC_BAND_2_X1_2 0x2423 | ||
318 | #define WM8958_MBC_BAND_2_X2_1 0x2424 | ||
319 | #define WM8958_MBC_BAND_2_X2_2 0x2425 | ||
320 | #define WM8958_MBC_BAND_2_X3_1 0x2426 | ||
321 | #define WM8958_MBC_BAND_2_X3_2 0x2427 | ||
322 | #define WM8958_MBC_BAND_2_ATTACK_1 0x2428 | ||
323 | #define WM8958_MBC_BAND_2_ATTACK_2 0x2429 | ||
324 | #define WM8958_MBC_BAND_2_DECAY_1 0x242A | ||
325 | #define WM8958_MBC_BAND_2_DECAY_2 0x242B | ||
326 | #define WM8958_MBC_B2_PG2_1 0x242C | ||
327 | #define WM8958_MBC_B2_PG2_2 0x242D | ||
328 | #define WM8958_MBC_B1_PG2_1 0x242E | ||
329 | #define WM8958_MBC_B1_PG2_2 0x242F | ||
245 | #define WM8994_WRITE_SEQUENCER_0 0x3000 | 330 | #define WM8994_WRITE_SEQUENCER_0 0x3000 |
246 | #define WM8994_WRITE_SEQUENCER_1 0x3001 | 331 | #define WM8994_WRITE_SEQUENCER_1 0x3001 |
247 | #define WM8994_WRITE_SEQUENCER_2 0x3002 | 332 | #define WM8994_WRITE_SEQUENCER_2 0x3002 |
@@ -992,6 +1077,12 @@ | |||
992 | /* | 1077 | /* |
993 | * R6 (0x06) - Power Management (6) | 1078 | * R6 (0x06) - Power Management (6) |
994 | */ | 1079 | */ |
1080 | #define WM8958_AIF3ADC_SRC_MASK 0x0600 /* AIF3ADC_SRC - [10:9] */ | ||
1081 | #define WM8958_AIF3ADC_SRC_SHIFT 9 /* AIF3ADC_SRC - [10:9] */ | ||
1082 | #define WM8958_AIF3ADC_SRC_WIDTH 2 /* AIF3ADC_SRC - [10:9] */ | ||
1083 | #define WM8958_AIF2DAC_SRC_MASK 0x0180 /* AIF2DAC_SRC - [8:7] */ | ||
1084 | #define WM8958_AIF2DAC_SRC_SHIFT 7 /* AIF2DAC_SRC - [8:7] */ | ||
1085 | #define WM8958_AIF2DAC_SRC_WIDTH 2 /* AIF2DAC_SRC - [8:7] */ | ||
995 | #define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */ | 1086 | #define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */ |
996 | #define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ | 1087 | #define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ |
997 | #define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ | 1088 | #define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ |
@@ -1836,6 +1927,14 @@ | |||
1836 | #define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */ | 1927 | #define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */ |
1837 | 1928 | ||
1838 | /* | 1929 | /* |
1930 | * R77 (0x4D) - Charge Pump (2) | ||
1931 | */ | ||
1932 | #define WM8958_CP_DISCH 0x8000 /* CP_DISCH */ | ||
1933 | #define WM8958_CP_DISCH_MASK 0x8000 /* CP_DISCH */ | ||
1934 | #define WM8958_CP_DISCH_SHIFT 15 /* CP_DISCH */ | ||
1935 | #define WM8958_CP_DISCH_WIDTH 1 /* CP_DISCH */ | ||
1936 | |||
1937 | /* | ||
1839 | * R81 (0x51) - Class W (1) | 1938 | * R81 (0x51) - Class W (1) |
1840 | */ | 1939 | */ |
1841 | #define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ | 1940 | #define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ |
@@ -1952,6 +2051,46 @@ | |||
1952 | #define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ | 2051 | #define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ |
1953 | 2052 | ||
1954 | /* | 2053 | /* |
2054 | * R208 (0xD0) - Mic Detect 1 | ||
2055 | */ | ||
2056 | #define WM8958_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */ | ||
2057 | #define WM8958_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */ | ||
2058 | #define WM8958_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */ | ||
2059 | #define WM8958_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */ | ||
2060 | #define WM8958_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */ | ||
2061 | #define WM8958_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */ | ||
2062 | #define WM8958_MICD_DBTIME 0x0002 /* MICD_DBTIME */ | ||
2063 | #define WM8958_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ | ||
2064 | #define WM8958_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ | ||
2065 | #define WM8958_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ | ||
2066 | #define WM8958_MICD_ENA 0x0001 /* MICD_ENA */ | ||
2067 | #define WM8958_MICD_ENA_MASK 0x0001 /* MICD_ENA */ | ||
2068 | #define WM8958_MICD_ENA_SHIFT 0 /* MICD_ENA */ | ||
2069 | #define WM8958_MICD_ENA_WIDTH 1 /* MICD_ENA */ | ||
2070 | |||
2071 | /* | ||
2072 | * R209 (0xD1) - Mic Detect 2 | ||
2073 | */ | ||
2074 | #define WM8958_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */ | ||
2075 | #define WM8958_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */ | ||
2076 | #define WM8958_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */ | ||
2077 | |||
2078 | /* | ||
2079 | * R210 (0xD2) - Mic Detect 3 | ||
2080 | */ | ||
2081 | #define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ | ||
2082 | #define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ | ||
2083 | #define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ | ||
2084 | #define WM8958_MICD_VALID 0x0002 /* MICD_VALID */ | ||
2085 | #define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */ | ||
2086 | #define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */ | ||
2087 | #define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */ | ||
2088 | #define WM8958_MICD_STS 0x0001 /* MICD_STS */ | ||
2089 | #define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */ | ||
2090 | #define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */ | ||
2091 | #define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */ | ||
2092 | |||
2093 | /* | ||
1955 | * R256 (0x100) - Chip Revision | 2094 | * R256 (0x100) - Chip Revision |
1956 | */ | 2095 | */ |
1957 | #define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ | 2096 | #define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ |
@@ -2069,6 +2208,14 @@ | |||
2069 | /* | 2208 | /* |
2070 | * R520 (0x208) - Clocking (1) | 2209 | * R520 (0x208) - Clocking (1) |
2071 | */ | 2210 | */ |
2211 | #define WM8958_DSP2CLK_ENA 0x4000 /* DSP2CLK_ENA */ | ||
2212 | #define WM8958_DSP2CLK_ENA_MASK 0x4000 /* DSP2CLK_ENA */ | ||
2213 | #define WM8958_DSP2CLK_ENA_SHIFT 14 /* DSP2CLK_ENA */ | ||
2214 | #define WM8958_DSP2CLK_ENA_WIDTH 1 /* DSP2CLK_ENA */ | ||
2215 | #define WM8958_DSP2CLK_SRC 0x1000 /* DSP2CLK_SRC */ | ||
2216 | #define WM8958_DSP2CLK_SRC_MASK 0x1000 /* DSP2CLK_SRC */ | ||
2217 | #define WM8958_DSP2CLK_SRC_SHIFT 12 /* DSP2CLK_SRC */ | ||
2218 | #define WM8958_DSP2CLK_SRC_WIDTH 1 /* DSP2CLK_SRC */ | ||
2072 | #define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */ | 2219 | #define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */ |
2073 | #define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ | 2220 | #define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ |
2074 | #define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ | 2221 | #define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ |
@@ -2553,6 +2700,63 @@ | |||
2553 | #define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ | 2700 | #define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ |
2554 | 2701 | ||
2555 | /* | 2702 | /* |
2703 | * R800 (0x320) - AIF3 Control (1) | ||
2704 | */ | ||
2705 | #define WM8958_AIF3_LRCLK_INV 0x0080 /* AIF3_LRCLK_INV */ | ||
2706 | #define WM8958_AIF3_LRCLK_INV_MASK 0x0080 /* AIF3_LRCLK_INV */ | ||
2707 | #define WM8958_AIF3_LRCLK_INV_SHIFT 7 /* AIF3_LRCLK_INV */ | ||
2708 | #define WM8958_AIF3_LRCLK_INV_WIDTH 1 /* AIF3_LRCLK_INV */ | ||
2709 | #define WM8958_AIF3_WL_MASK 0x0060 /* AIF3_WL - [6:5] */ | ||
2710 | #define WM8958_AIF3_WL_SHIFT 5 /* AIF3_WL - [6:5] */ | ||
2711 | #define WM8958_AIF3_WL_WIDTH 2 /* AIF3_WL - [6:5] */ | ||
2712 | #define WM8958_AIF3_FMT_MASK 0x0018 /* AIF3_FMT - [4:3] */ | ||
2713 | #define WM8958_AIF3_FMT_SHIFT 3 /* AIF3_FMT - [4:3] */ | ||
2714 | #define WM8958_AIF3_FMT_WIDTH 2 /* AIF3_FMT - [4:3] */ | ||
2715 | |||
2716 | /* | ||
2717 | * R801 (0x321) - AIF3 Control (2) | ||
2718 | */ | ||
2719 | #define WM8958_AIF3DAC_BOOST_MASK 0x0C00 /* AIF3DAC_BOOST - [11:10] */ | ||
2720 | #define WM8958_AIF3DAC_BOOST_SHIFT 10 /* AIF3DAC_BOOST - [11:10] */ | ||
2721 | #define WM8958_AIF3DAC_BOOST_WIDTH 2 /* AIF3DAC_BOOST - [11:10] */ | ||
2722 | #define WM8958_AIF3DAC_COMP 0x0010 /* AIF3DAC_COMP */ | ||
2723 | #define WM8958_AIF3DAC_COMP_MASK 0x0010 /* AIF3DAC_COMP */ | ||
2724 | #define WM8958_AIF3DAC_COMP_SHIFT 4 /* AIF3DAC_COMP */ | ||
2725 | #define WM8958_AIF3DAC_COMP_WIDTH 1 /* AIF3DAC_COMP */ | ||
2726 | #define WM8958_AIF3DAC_COMPMODE 0x0008 /* AIF3DAC_COMPMODE */ | ||
2727 | #define WM8958_AIF3DAC_COMPMODE_MASK 0x0008 /* AIF3DAC_COMPMODE */ | ||
2728 | #define WM8958_AIF3DAC_COMPMODE_SHIFT 3 /* AIF3DAC_COMPMODE */ | ||
2729 | #define WM8958_AIF3DAC_COMPMODE_WIDTH 1 /* AIF3DAC_COMPMODE */ | ||
2730 | #define WM8958_AIF3ADC_COMP 0x0004 /* AIF3ADC_COMP */ | ||
2731 | #define WM8958_AIF3ADC_COMP_MASK 0x0004 /* AIF3ADC_COMP */ | ||
2732 | #define WM8958_AIF3ADC_COMP_SHIFT 2 /* AIF3ADC_COMP */ | ||
2733 | #define WM8958_AIF3ADC_COMP_WIDTH 1 /* AIF3ADC_COMP */ | ||
2734 | #define WM8958_AIF3ADC_COMPMODE 0x0002 /* AIF3ADC_COMPMODE */ | ||
2735 | #define WM8958_AIF3ADC_COMPMODE_MASK 0x0002 /* AIF3ADC_COMPMODE */ | ||
2736 | #define WM8958_AIF3ADC_COMPMODE_SHIFT 1 /* AIF3ADC_COMPMODE */ | ||
2737 | #define WM8958_AIF3ADC_COMPMODE_WIDTH 1 /* AIF3ADC_COMPMODE */ | ||
2738 | #define WM8958_AIF3_LOOPBACK 0x0001 /* AIF3_LOOPBACK */ | ||
2739 | #define WM8958_AIF3_LOOPBACK_MASK 0x0001 /* AIF3_LOOPBACK */ | ||
2740 | #define WM8958_AIF3_LOOPBACK_SHIFT 0 /* AIF3_LOOPBACK */ | ||
2741 | #define WM8958_AIF3_LOOPBACK_WIDTH 1 /* AIF3_LOOPBACK */ | ||
2742 | |||
2743 | /* | ||
2744 | * R802 (0x322) - AIF3DAC Data | ||
2745 | */ | ||
2746 | #define WM8958_AIF3DAC_DAT_INV 0x0001 /* AIF3DAC_DAT_INV */ | ||
2747 | #define WM8958_AIF3DAC_DAT_INV_MASK 0x0001 /* AIF3DAC_DAT_INV */ | ||
2748 | #define WM8958_AIF3DAC_DAT_INV_SHIFT 0 /* AIF3DAC_DAT_INV */ | ||
2749 | #define WM8958_AIF3DAC_DAT_INV_WIDTH 1 /* AIF3DAC_DAT_INV */ | ||
2750 | |||
2751 | /* | ||
2752 | * R803 (0x323) - AIF3ADC Data | ||
2753 | */ | ||
2754 | #define WM8958_AIF3ADC_DAT_INV 0x0001 /* AIF3ADC_DAT_INV */ | ||
2755 | #define WM8958_AIF3ADC_DAT_INV_MASK 0x0001 /* AIF3ADC_DAT_INV */ | ||
2756 | #define WM8958_AIF3ADC_DAT_INV_SHIFT 0 /* AIF3ADC_DAT_INV */ | ||
2757 | #define WM8958_AIF3ADC_DAT_INV_WIDTH 1 /* AIF3ADC_DAT_INV */ | ||
2758 | |||
2759 | /* | ||
2556 | * R1024 (0x400) - AIF1 ADC1 Left Volume | 2760 | * R1024 (0x400) - AIF1 ADC1 Left Volume |
2557 | */ | 2761 | */ |
2558 | #define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ | 2762 | #define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ |
@@ -4289,4 +4493,102 @@ | |||
4289 | #define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */ | 4493 | #define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */ |
4290 | #define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */ | 4494 | #define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */ |
4291 | 4495 | ||
4496 | /* | ||
4497 | * R2304 (0x900) - DSP2_Program | ||
4498 | */ | ||
4499 | #define WM8958_DSP2_ENA 0x0001 /* DSP2_ENA */ | ||
4500 | #define WM8958_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */ | ||
4501 | #define WM8958_DSP2_ENA_SHIFT 0 /* DSP2_ENA */ | ||
4502 | #define WM8958_DSP2_ENA_WIDTH 1 /* DSP2_ENA */ | ||
4503 | |||
4504 | /* | ||
4505 | * R2305 (0x901) - DSP2_Config | ||
4506 | */ | ||
4507 | #define WM8958_MBC_SEL_MASK 0x0030 /* MBC_SEL - [5:4] */ | ||
4508 | #define WM8958_MBC_SEL_SHIFT 4 /* MBC_SEL - [5:4] */ | ||
4509 | #define WM8958_MBC_SEL_WIDTH 2 /* MBC_SEL - [5:4] */ | ||
4510 | #define WM8958_MBC_ENA 0x0001 /* MBC_ENA */ | ||
4511 | #define WM8958_MBC_ENA_MASK 0x0001 /* MBC_ENA */ | ||
4512 | #define WM8958_MBC_ENA_SHIFT 0 /* MBC_ENA */ | ||
4513 | #define WM8958_MBC_ENA_WIDTH 1 /* MBC_ENA */ | ||
4514 | |||
4515 | /* | ||
4516 | * R2560 (0xA00) - DSP2_MagicNum | ||
4517 | */ | ||
4518 | #define WM8958_DSP2_MAGIC_NUM_MASK 0xFFFF /* DSP2_MAGIC_NUM - [15:0] */ | ||
4519 | #define WM8958_DSP2_MAGIC_NUM_SHIFT 0 /* DSP2_MAGIC_NUM - [15:0] */ | ||
4520 | #define WM8958_DSP2_MAGIC_NUM_WIDTH 16 /* DSP2_MAGIC_NUM - [15:0] */ | ||
4521 | |||
4522 | /* | ||
4523 | * R2561 (0xA01) - DSP2_ReleaseYear | ||
4524 | */ | ||
4525 | #define WM8958_DSP2_RELEASE_YEAR_MASK 0xFFFF /* DSP2_RELEASE_YEAR - [15:0] */ | ||
4526 | #define WM8958_DSP2_RELEASE_YEAR_SHIFT 0 /* DSP2_RELEASE_YEAR - [15:0] */ | ||
4527 | #define WM8958_DSP2_RELEASE_YEAR_WIDTH 16 /* DSP2_RELEASE_YEAR - [15:0] */ | ||
4528 | |||
4529 | /* | ||
4530 | * R2562 (0xA02) - DSP2_ReleaseMonthDay | ||
4531 | */ | ||
4532 | #define WM8958_DSP2_RELEASE_MONTH_MASK 0xFF00 /* DSP2_RELEASE_MONTH - [15:8] */ | ||
4533 | #define WM8958_DSP2_RELEASE_MONTH_SHIFT 8 /* DSP2_RELEASE_MONTH - [15:8] */ | ||
4534 | #define WM8958_DSP2_RELEASE_MONTH_WIDTH 8 /* DSP2_RELEASE_MONTH - [15:8] */ | ||
4535 | #define WM8958_DSP2_RELEASE_DAY_MASK 0x00FF /* DSP2_RELEASE_DAY - [7:0] */ | ||
4536 | #define WM8958_DSP2_RELEASE_DAY_SHIFT 0 /* DSP2_RELEASE_DAY - [7:0] */ | ||
4537 | #define WM8958_DSP2_RELEASE_DAY_WIDTH 8 /* DSP2_RELEASE_DAY - [7:0] */ | ||
4538 | |||
4539 | /* | ||
4540 | * R2563 (0xA03) - DSP2_ReleaseTime | ||
4541 | */ | ||
4542 | #define WM8958_DSP2_RELEASE_HOURS_MASK 0xFF00 /* DSP2_RELEASE_HOURS - [15:8] */ | ||
4543 | #define WM8958_DSP2_RELEASE_HOURS_SHIFT 8 /* DSP2_RELEASE_HOURS - [15:8] */ | ||
4544 | #define WM8958_DSP2_RELEASE_HOURS_WIDTH 8 /* DSP2_RELEASE_HOURS - [15:8] */ | ||
4545 | #define WM8958_DSP2_RELEASE_MINS_MASK 0x00FF /* DSP2_RELEASE_MINS - [7:0] */ | ||
4546 | #define WM8958_DSP2_RELEASE_MINS_SHIFT 0 /* DSP2_RELEASE_MINS - [7:0] */ | ||
4547 | #define WM8958_DSP2_RELEASE_MINS_WIDTH 8 /* DSP2_RELEASE_MINS - [7:0] */ | ||
4548 | |||
4549 | /* | ||
4550 | * R2564 (0xA04) - DSP2_VerMajMin | ||
4551 | */ | ||
4552 | #define WM8958_DSP2_MAJOR_VER_MASK 0xFF00 /* DSP2_MAJOR_VER - [15:8] */ | ||
4553 | #define WM8958_DSP2_MAJOR_VER_SHIFT 8 /* DSP2_MAJOR_VER - [15:8] */ | ||
4554 | #define WM8958_DSP2_MAJOR_VER_WIDTH 8 /* DSP2_MAJOR_VER - [15:8] */ | ||
4555 | #define WM8958_DSP2_MINOR_VER_MASK 0x00FF /* DSP2_MINOR_VER - [7:0] */ | ||
4556 | #define WM8958_DSP2_MINOR_VER_SHIFT 0 /* DSP2_MINOR_VER - [7:0] */ | ||
4557 | #define WM8958_DSP2_MINOR_VER_WIDTH 8 /* DSP2_MINOR_VER - [7:0] */ | ||
4558 | |||
4559 | /* | ||
4560 | * R2565 (0xA05) - DSP2_VerBuild | ||
4561 | */ | ||
4562 | #define WM8958_DSP2_BUILD_VER_MASK 0xFFFF /* DSP2_BUILD_VER - [15:0] */ | ||
4563 | #define WM8958_DSP2_BUILD_VER_SHIFT 0 /* DSP2_BUILD_VER - [15:0] */ | ||
4564 | #define WM8958_DSP2_BUILD_VER_WIDTH 16 /* DSP2_BUILD_VER - [15:0] */ | ||
4565 | |||
4566 | /* | ||
4567 | * R2573 (0xA0D) - DSP2_ExecControl | ||
4568 | */ | ||
4569 | #define WM8958_DSP2_STOPC 0x0020 /* DSP2_STOPC */ | ||
4570 | #define WM8958_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */ | ||
4571 | #define WM8958_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */ | ||
4572 | #define WM8958_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */ | ||
4573 | #define WM8958_DSP2_STOPS 0x0010 /* DSP2_STOPS */ | ||
4574 | #define WM8958_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */ | ||
4575 | #define WM8958_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */ | ||
4576 | #define WM8958_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */ | ||
4577 | #define WM8958_DSP2_STOPI 0x0008 /* DSP2_STOPI */ | ||
4578 | #define WM8958_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */ | ||
4579 | #define WM8958_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */ | ||
4580 | #define WM8958_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */ | ||
4581 | #define WM8958_DSP2_STOP 0x0004 /* DSP2_STOP */ | ||
4582 | #define WM8958_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */ | ||
4583 | #define WM8958_DSP2_STOP_SHIFT 2 /* DSP2_STOP */ | ||
4584 | #define WM8958_DSP2_STOP_WIDTH 1 /* DSP2_STOP */ | ||
4585 | #define WM8958_DSP2_RUNR 0x0002 /* DSP2_RUNR */ | ||
4586 | #define WM8958_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */ | ||
4587 | #define WM8958_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */ | ||
4588 | #define WM8958_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */ | ||
4589 | #define WM8958_DSP2_RUN 0x0001 /* DSP2_RUN */ | ||
4590 | #define WM8958_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */ | ||
4591 | #define WM8958_DSP2_RUN_SHIFT 0 /* DSP2_RUN */ | ||
4592 | #define WM8958_DSP2_RUN_WIDTH 1 /* DSP2_RUN */ | ||
4593 | |||
4292 | #endif | 4594 | #endif |