1 files changed, 25 insertions, 7 deletions

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 03f48d936f66..8588e5efe577 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -20,6 +20,7 @@
 #include <linux/errno.h>
 #include <linux/topology.h>
 #include <linux/wait.h>
+#include <linux/io.h>
 
 #include <asm/irq.h>
 #include <asm/ptrace.h>
@@ -639,13 +640,6 @@ void arch_teardown_hwirq(unsigned int irq);
 void irq_init_desc(unsigned int irq);
 #endif
 
-#ifndef irq_reg_writel
-# define irq_reg_writel(val, addr)      writel(val, addr)
-#endif
-#ifndef irq_reg_readl
-# define irq_reg_readl(addr)            readl(addr)
-#endif
-
 /**
  * struct irq_chip_regs - register offsets for struct irq_gci
  * @enable:     Enable register offset to reg_base
@@ -692,6 +686,8 @@ struct irq_chip_type {
  * struct irq_chip_generic - Generic irq chip data structure
  * @lock:               Lock to protect register and cache data access
  * @reg_base:           Register base address (virtual)
+ * @reg_readl:          Alternate I/O accessor (defaults to readl if NULL)
+ * @reg_writel:         Alternate I/O accessor (defaults to writel if NULL)
  * @irq_base:           Interrupt base nr for this chip
  * @irq_cnt:            Number of interrupts handled by this chip
  * @mask_cache:         Cached mask register shared between all chip types
@@ -716,6 +712,8 @@ struct irq_chip_type {
 struct irq_chip_generic {
         raw_spinlock_t          lock;
         void __iomem            *reg_base;
+        u32                     (*reg_readl)(void __iomem *addr);
+        void                    (*reg_writel)(u32 val, void __iomem *addr);
         unsigned int            irq_base;
         unsigned int            irq_cnt;
         u32                     mask_cache;
@@ -740,12 +738,14 @@ struct irq_chip_generic {
  *                              the parent irq. Usually GPIO implementations
  * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
  * @IRQ_GC_NO_MASK:             Do not calculate irq_data->mask
+ * @IRQ_GC_BE_IO:               Use big-endian register accesses (default: LE)
  */
 enum irq_gc_flags {
         IRQ_GC_INIT_MASK_CACHE          = 1 << 0,
         IRQ_GC_INIT_NESTED_LOCK         = 1 << 1,
         IRQ_GC_MASK_CACHE_PER_TYPE      = 1 << 2,
         IRQ_GC_NO_MASK                  = 1 << 3,
+        IRQ_GC_BE_IO                    = 1 << 4,
 };
 
 /*
@@ -821,4 +821,22 @@ static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
 #endif
 
+static inline void irq_reg_writel(struct irq_chip_generic *gc,
+                                  u32 val, int reg_offset)
+{
+        if (gc->reg_writel)
+                gc->reg_writel(val, gc->reg_base + reg_offset);
+        else
+                writel(val, gc->reg_base + reg_offset);
+}
+
+static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
+                                int reg_offset)
+{
+        if (gc->reg_readl)
+                return gc->reg_readl(gc->reg_base + reg_offset);
+        else
+                return readl(gc->reg_base + reg_offset);
+}
+
 #endif /* _LINUX_IRQ_H */