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-rw-r--r--include/linux/i2o.h975
1 files changed, 552 insertions, 423 deletions
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index d79c8a4bc4f8..9e359a981221 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -30,6 +30,7 @@
30#include <linux/string.h> 30#include <linux/string.h>
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/workqueue.h> /* work_struct */ 32#include <linux/workqueue.h> /* work_struct */
33#include <linux/mempool.h>
33 34
34#include <asm/io.h> 35#include <asm/io.h>
35#include <asm/semaphore.h> /* Needed for MUTEX init macros */ 36#include <asm/semaphore.h> /* Needed for MUTEX init macros */
@@ -38,6 +39,355 @@
38#define I2O_QUEUE_EMPTY 0xffffffff 39#define I2O_QUEUE_EMPTY 0xffffffff
39 40
40/* 41/*
42 * Cache strategies
43 */
44
45/* The NULL strategy leaves everything up to the controller. This tends to be a
46 * pessimal but functional choice.
47 */
48#define CACHE_NULL 0
49/* Prefetch data when reading. We continually attempt to load the next 32 sectors
50 * into the controller cache.
51 */
52#define CACHE_PREFETCH 1
53/* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
54 * into the controller cache. When an I/O is less <= 8K we assume its probably
55 * not sequential and don't prefetch (default)
56 */
57#define CACHE_SMARTFETCH 2
58/* Data is written to the cache and then out on to the disk. The I/O must be
59 * physically on the medium before the write is acknowledged (default without
60 * NVRAM)
61 */
62#define CACHE_WRITETHROUGH 17
63/* Data is written to the cache and then out on to the disk. The controller
64 * is permitted to write back the cache any way it wants. (default if battery
65 * backed NVRAM is present). It can be useful to set this for swap regardless of
66 * battery state.
67 */
68#define CACHE_WRITEBACK 18
69/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
70 * write large I/O's directly to disk bypassing the cache to avoid the extra
71 * memory copy hits. Small writes are writeback cached
72 */
73#define CACHE_SMARTBACK 19
74/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
75 * write large I/O's directly to disk bypassing the cache to avoid the extra
76 * memory copy hits. Small writes are writethrough cached. Suitable for devices
77 * lacking battery backup
78 */
79#define CACHE_SMARTTHROUGH 20
80
81/*
82 * Ioctl structures
83 */
84
85#define BLKI2OGRSTRAT _IOR('2', 1, int)
86#define BLKI2OGWSTRAT _IOR('2', 2, int)
87#define BLKI2OSRSTRAT _IOW('2', 3, int)
88#define BLKI2OSWSTRAT _IOW('2', 4, int)
89
90/*
91 * I2O Function codes
92 */
93
94/*
95 * Executive Class
96 */
97#define I2O_CMD_ADAPTER_ASSIGN 0xB3
98#define I2O_CMD_ADAPTER_READ 0xB2
99#define I2O_CMD_ADAPTER_RELEASE 0xB5
100#define I2O_CMD_BIOS_INFO_SET 0xA5
101#define I2O_CMD_BOOT_DEVICE_SET 0xA7
102#define I2O_CMD_CONFIG_VALIDATE 0xBB
103#define I2O_CMD_CONN_SETUP 0xCA
104#define I2O_CMD_DDM_DESTROY 0xB1
105#define I2O_CMD_DDM_ENABLE 0xD5
106#define I2O_CMD_DDM_QUIESCE 0xC7
107#define I2O_CMD_DDM_RESET 0xD9
108#define I2O_CMD_DDM_SUSPEND 0xAF
109#define I2O_CMD_DEVICE_ASSIGN 0xB7
110#define I2O_CMD_DEVICE_RELEASE 0xB9
111#define I2O_CMD_HRT_GET 0xA8
112#define I2O_CMD_ADAPTER_CLEAR 0xBE
113#define I2O_CMD_ADAPTER_CONNECT 0xC9
114#define I2O_CMD_ADAPTER_RESET 0xBD
115#define I2O_CMD_LCT_NOTIFY 0xA2
116#define I2O_CMD_OUTBOUND_INIT 0xA1
117#define I2O_CMD_PATH_ENABLE 0xD3
118#define I2O_CMD_PATH_QUIESCE 0xC5
119#define I2O_CMD_PATH_RESET 0xD7
120#define I2O_CMD_STATIC_MF_CREATE 0xDD
121#define I2O_CMD_STATIC_MF_RELEASE 0xDF
122#define I2O_CMD_STATUS_GET 0xA0
123#define I2O_CMD_SW_DOWNLOAD 0xA9
124#define I2O_CMD_SW_UPLOAD 0xAB
125#define I2O_CMD_SW_REMOVE 0xAD
126#define I2O_CMD_SYS_ENABLE 0xD1
127#define I2O_CMD_SYS_MODIFY 0xC1
128#define I2O_CMD_SYS_QUIESCE 0xC3
129#define I2O_CMD_SYS_TAB_SET 0xA3
130
131/*
132 * Utility Class
133 */
134#define I2O_CMD_UTIL_NOP 0x00
135#define I2O_CMD_UTIL_ABORT 0x01
136#define I2O_CMD_UTIL_CLAIM 0x09
137#define I2O_CMD_UTIL_RELEASE 0x0B
138#define I2O_CMD_UTIL_PARAMS_GET 0x06
139#define I2O_CMD_UTIL_PARAMS_SET 0x05
140#define I2O_CMD_UTIL_EVT_REGISTER 0x13
141#define I2O_CMD_UTIL_EVT_ACK 0x14
142#define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
143#define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
144#define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
145#define I2O_CMD_UTIL_LOCK 0x17
146#define I2O_CMD_UTIL_LOCK_RELEASE 0x19
147#define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
148
149/*
150 * SCSI Host Bus Adapter Class
151 */
152#define I2O_CMD_SCSI_EXEC 0x81
153#define I2O_CMD_SCSI_ABORT 0x83
154#define I2O_CMD_SCSI_BUSRESET 0x27
155
156/*
157 * Bus Adapter Class
158 */
159#define I2O_CMD_BUS_ADAPTER_RESET 0x85
160#define I2O_CMD_BUS_RESET 0x87
161#define I2O_CMD_BUS_SCAN 0x89
162#define I2O_CMD_BUS_QUIESCE 0x8b
163
164/*
165 * Random Block Storage Class
166 */
167#define I2O_CMD_BLOCK_READ 0x30
168#define I2O_CMD_BLOCK_WRITE 0x31
169#define I2O_CMD_BLOCK_CFLUSH 0x37
170#define I2O_CMD_BLOCK_MLOCK 0x49
171#define I2O_CMD_BLOCK_MUNLOCK 0x4B
172#define I2O_CMD_BLOCK_MMOUNT 0x41
173#define I2O_CMD_BLOCK_MEJECT 0x43
174#define I2O_CMD_BLOCK_POWER 0x70
175
176#define I2O_CMD_PRIVATE 0xFF
177
178/* Command status values */
179
180#define I2O_CMD_IN_PROGRESS 0x01
181#define I2O_CMD_REJECTED 0x02
182#define I2O_CMD_FAILED 0x03
183#define I2O_CMD_COMPLETED 0x04
184
185/* I2O API function return values */
186
187#define I2O_RTN_NO_ERROR 0
188#define I2O_RTN_NOT_INIT 1
189#define I2O_RTN_FREE_Q_EMPTY 2
190#define I2O_RTN_TCB_ERROR 3
191#define I2O_RTN_TRANSACTION_ERROR 4
192#define I2O_RTN_ADAPTER_ALREADY_INIT 5
193#define I2O_RTN_MALLOC_ERROR 6
194#define I2O_RTN_ADPTR_NOT_REGISTERED 7
195#define I2O_RTN_MSG_REPLY_TIMEOUT 8
196#define I2O_RTN_NO_STATUS 9
197#define I2O_RTN_NO_FIRM_VER 10
198#define I2O_RTN_NO_LINK_SPEED 11
199
200/* Reply message status defines for all messages */
201
202#define I2O_REPLY_STATUS_SUCCESS 0x00
203#define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
204#define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
205#define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
206#define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
207#define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
208#define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
209#define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
210#define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
211#define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
212#define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
213#define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
214
215/* Status codes and Error Information for Parameter functions */
216
217#define I2O_PARAMS_STATUS_SUCCESS 0x00
218#define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
219#define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
220#define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
221#define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
222#define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
223#define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
224#define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
225#define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
226#define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
227#define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
228#define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
229#define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
230#define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
231#define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
232#define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
233#define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
234
235/* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
236 * messages: Table 3-2 Detailed Status Codes.*/
237
238#define I2O_DSC_SUCCESS 0x0000
239#define I2O_DSC_BAD_KEY 0x0002
240#define I2O_DSC_TCL_ERROR 0x0003
241#define I2O_DSC_REPLY_BUFFER_FULL 0x0004
242#define I2O_DSC_NO_SUCH_PAGE 0x0005
243#define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
244#define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
245#define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
246#define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
247#define I2O_DSC_DEVICE_LOCKED 0x000B
248#define I2O_DSC_DEVICE_RESET 0x000C
249#define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
250#define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
251#define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
252#define I2O_DSC_INVALID_OFFSET 0x0010
253#define I2O_DSC_INVALID_PARAMETER 0x0011
254#define I2O_DSC_INVALID_REQUEST 0x0012
255#define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
256#define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
257#define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
258#define I2O_DSC_MISSING_PARAMETER 0x0016
259#define I2O_DSC_TIMEOUT 0x0017
260#define I2O_DSC_UNKNOWN_ERROR 0x0018
261#define I2O_DSC_UNKNOWN_FUNCTION 0x0019
262#define I2O_DSC_UNSUPPORTED_VERSION 0x001A
263#define I2O_DSC_DEVICE_BUSY 0x001B
264#define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
265
266/* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
267 Status Codes.*/
268
269#define I2O_BSA_DSC_SUCCESS 0x0000
270#define I2O_BSA_DSC_MEDIA_ERROR 0x0001
271#define I2O_BSA_DSC_ACCESS_ERROR 0x0002
272#define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
273#define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
274#define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
275#define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
276#define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
277#define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
278#define I2O_BSA_DSC_BUS_FAILURE 0x0009
279#define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
280#define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
281#define I2O_BSA_DSC_DEVICE_RESET 0x000C
282#define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
283#define I2O_BSA_DSC_TIMEOUT 0x000E
284
285/* FailureStatusCodes, Table 3-3 Message Failure Codes */
286
287#define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
288#define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
289#define I2O_FSC_TRANSPORT_CONGESTION 0x83
290#define I2O_FSC_TRANSPORT_FAILURE 0x84
291#define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
292#define I2O_FSC_TRANSPORT_TIME_OUT 0x86
293#define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
294#define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
295#define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
296#define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
297#define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
298#define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
299#define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
300#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
301#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
302#define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
303
304/* Device Claim Types */
305#define I2O_CLAIM_PRIMARY 0x01000000
306#define I2O_CLAIM_MANAGEMENT 0x02000000
307#define I2O_CLAIM_AUTHORIZED 0x03000000
308#define I2O_CLAIM_SECONDARY 0x04000000
309
310/* Message header defines for VersionOffset */
311#define I2OVER15 0x0001
312#define I2OVER20 0x0002
313
314/* Default is 1.5 */
315#define I2OVERSION I2OVER15
316
317#define SGL_OFFSET_0 I2OVERSION
318#define SGL_OFFSET_4 (0x0040 | I2OVERSION)
319#define SGL_OFFSET_5 (0x0050 | I2OVERSION)
320#define SGL_OFFSET_6 (0x0060 | I2OVERSION)
321#define SGL_OFFSET_7 (0x0070 | I2OVERSION)
322#define SGL_OFFSET_8 (0x0080 | I2OVERSION)
323#define SGL_OFFSET_9 (0x0090 | I2OVERSION)
324#define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
325#define SGL_OFFSET_11 (0x00B0 | I2OVERSION)
326#define SGL_OFFSET_12 (0x00C0 | I2OVERSION)
327#define SGL_OFFSET(x) (((x)<<4) | I2OVERSION)
328
329/* Transaction Reply Lists (TRL) Control Word structure */
330#define TRL_SINGLE_FIXED_LENGTH 0x00
331#define TRL_SINGLE_VARIABLE_LENGTH 0x40
332#define TRL_MULTIPLE_FIXED_LENGTH 0x80
333
334 /* msg header defines for MsgFlags */
335#define MSG_STATIC 0x0100
336#define MSG_64BIT_CNTXT 0x0200
337#define MSG_MULTI_TRANS 0x1000
338#define MSG_FAIL 0x2000
339#define MSG_FINAL 0x4000
340#define MSG_REPLY 0x8000
341
342 /* minimum size msg */
343#define THREE_WORD_MSG_SIZE 0x00030000
344#define FOUR_WORD_MSG_SIZE 0x00040000
345#define FIVE_WORD_MSG_SIZE 0x00050000
346#define SIX_WORD_MSG_SIZE 0x00060000
347#define SEVEN_WORD_MSG_SIZE 0x00070000
348#define EIGHT_WORD_MSG_SIZE 0x00080000
349#define NINE_WORD_MSG_SIZE 0x00090000
350#define TEN_WORD_MSG_SIZE 0x000A0000
351#define ELEVEN_WORD_MSG_SIZE 0x000B0000
352#define I2O_MESSAGE_SIZE(x) ((x)<<16)
353
354/* special TID assignments */
355#define ADAPTER_TID 0
356#define HOST_TID 1
357
358/* outbound queue defines */
359#define I2O_MAX_OUTBOUND_MSG_FRAMES 128
360#define I2O_OUTBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
361
362/* inbound queue definitions */
363#define I2O_MSG_INPOOL_MIN 32
364#define I2O_INBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
365
366#define I2O_POST_WAIT_OK 0
367#define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
368
369#define I2O_CONTEXT_LIST_MIN_LENGTH 15
370#define I2O_CONTEXT_LIST_USED 0x01
371#define I2O_CONTEXT_LIST_DELETED 0x02
372
373/* timeouts */
374#define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
375#define I2O_TIMEOUT_MESSAGE_GET 5
376#define I2O_TIMEOUT_RESET 30
377#define I2O_TIMEOUT_STATUS_GET 5
378#define I2O_TIMEOUT_LCT_GET 360
379#define I2O_TIMEOUT_SCSI_SCB_ABORT 240
380
381/* retries */
382#define I2O_HRT_GET_TRIES 3
383#define I2O_LCT_GET_TRIES 3
384
385/* defines for max_sectors and max_phys_segments */
386#define I2O_MAX_SECTORS 1024
387#define I2O_MAX_SECTORS_LIMITED 256
388#define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
389
390/*
41 * Message structures 391 * Message structures
42 */ 392 */
43struct i2o_message { 393struct i2o_message {
@@ -58,6 +408,12 @@ struct i2o_message {
58 u32 body[0]; 408 u32 body[0];
59}; 409};
60 410
411/* MFA and I2O message used by mempool */
412struct i2o_msg_mfa {
413 u32 mfa; /* MFA returned by the controller */
414 struct i2o_message msg; /* I2O message */
415};
416
61/* 417/*
62 * Each I2O device entity has one of these. There is one per device. 418 * Each I2O device entity has one of these. There is one per device.
63 */ 419 */
@@ -130,6 +486,15 @@ struct i2o_dma {
130}; 486};
131 487
132/* 488/*
489 * Contains slab cache and mempool information
490 */
491struct i2o_pool {
492 char *name;
493 kmem_cache_t *slab;
494 mempool_t *mempool;
495};
496
497/*
133 * Contains IO mapped address information 498 * Contains IO mapped address information
134 */ 499 */
135struct i2o_io { 500struct i2o_io {
@@ -174,8 +539,6 @@ struct i2o_controller {
174 void __iomem *irq_status; /* Interrupt status register address */ 539 void __iomem *irq_status; /* Interrupt status register address */
175 void __iomem *irq_mask; /* Interrupt mask register address */ 540 void __iomem *irq_mask; /* Interrupt mask register address */
176 541
177 /* Dynamic LCT related data */
178
179 struct i2o_dma status; /* IOP status block */ 542 struct i2o_dma status; /* IOP status block */
180 543
181 struct i2o_dma hrt; /* HW Resource Table */ 544 struct i2o_dma hrt; /* HW Resource Table */
@@ -188,6 +551,8 @@ struct i2o_controller {
188 struct i2o_io in_queue; /* inbound message queue Host->IOP */ 551 struct i2o_io in_queue; /* inbound message queue Host->IOP */
189 struct i2o_dma out_queue; /* outbound message queue IOP->Host */ 552 struct i2o_dma out_queue; /* outbound message queue IOP->Host */
190 553
554 struct i2o_pool in_msg; /* mempool for inbound messages */
555
191 unsigned int battery:1; /* Has a battery backup */ 556 unsigned int battery:1; /* Has a battery backup */
192 unsigned int io_alloc:1; /* An I/O resource was allocated */ 557 unsigned int io_alloc:1; /* An I/O resource was allocated */
193 unsigned int mem_alloc:1; /* A memory resource was allocated */ 558 unsigned int mem_alloc:1; /* A memory resource was allocated */
@@ -247,16 +612,13 @@ struct i2o_sys_tbl {
247extern struct list_head i2o_controllers; 612extern struct list_head i2o_controllers;
248 613
249/* Message functions */ 614/* Message functions */
250static inline u32 i2o_msg_get(struct i2o_controller *, 615static inline struct i2o_message *i2o_msg_get(struct i2o_controller *);
251 struct i2o_message __iomem **); 616extern struct i2o_message *i2o_msg_get_wait(struct i2o_controller *, int);
252extern u32 i2o_msg_get_wait(struct i2o_controller *, 617static inline void i2o_msg_post(struct i2o_controller *, struct i2o_message *);
253 struct i2o_message __iomem **, int); 618static inline int i2o_msg_post_wait(struct i2o_controller *,
254static inline void i2o_msg_post(struct i2o_controller *, u32); 619 struct i2o_message *, unsigned long);
255static inline int i2o_msg_post_wait(struct i2o_controller *, u32, 620extern int i2o_msg_post_wait_mem(struct i2o_controller *, struct i2o_message *,
256 unsigned long); 621 unsigned long, struct i2o_dma *);
257extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long,
258 struct i2o_dma *);
259extern void i2o_msg_nop(struct i2o_controller *, u32);
260static inline void i2o_flush_reply(struct i2o_controller *, u32); 622static inline void i2o_flush_reply(struct i2o_controller *, u32);
261 623
262/* IOP functions */ 624/* IOP functions */
@@ -384,10 +746,10 @@ static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
384static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr, 746static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
385 size_t size, 747 size_t size,
386 enum dma_data_direction direction, 748 enum dma_data_direction direction,
387 u32 __iomem ** sg_ptr) 749 u32 ** sg_ptr)
388{ 750{
389 u32 sg_flags; 751 u32 sg_flags;
390 u32 __iomem *mptr = *sg_ptr; 752 u32 *mptr = *sg_ptr;
391 dma_addr_t dma_addr; 753 dma_addr_t dma_addr;
392 754
393 switch (direction) { 755 switch (direction) {
@@ -405,16 +767,16 @@ static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
405 if (!dma_mapping_error(dma_addr)) { 767 if (!dma_mapping_error(dma_addr)) {
406#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64 768#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
407 if ((sizeof(dma_addr_t) > 4) && c->pae_support) { 769 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
408 writel(0x7C020002, mptr++); 770 *mptr++ = cpu_to_le32(0x7C020002);
409 writel(PAGE_SIZE, mptr++); 771 *mptr++ = cpu_to_le32(PAGE_SIZE);
410 } 772 }
411#endif 773#endif
412 774
413 writel(sg_flags | size, mptr++); 775 *mptr++ = cpu_to_le32(sg_flags | size);
414 writel(i2o_dma_low(dma_addr), mptr++); 776 *mptr++ = cpu_to_le32(i2o_dma_low(dma_addr));
415#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64 777#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
416 if ((sizeof(dma_addr_t) > 4) && c->pae_support) 778 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
417 writel(i2o_dma_high(dma_addr), mptr++); 779 *mptr++ = cpu_to_le32(i2o_dma_high(dma_addr));
418#endif 780#endif
419 *sg_ptr = mptr; 781 *sg_ptr = mptr;
420 } 782 }
@@ -439,10 +801,10 @@ static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
439static inline int i2o_dma_map_sg(struct i2o_controller *c, 801static inline int i2o_dma_map_sg(struct i2o_controller *c,
440 struct scatterlist *sg, int sg_count, 802 struct scatterlist *sg, int sg_count,
441 enum dma_data_direction direction, 803 enum dma_data_direction direction,
442 u32 __iomem ** sg_ptr) 804 u32 ** sg_ptr)
443{ 805{
444 u32 sg_flags; 806 u32 sg_flags;
445 u32 __iomem *mptr = *sg_ptr; 807 u32 *mptr = *sg_ptr;
446 808
447 switch (direction) { 809 switch (direction) {
448 case DMA_TO_DEVICE: 810 case DMA_TO_DEVICE:
@@ -461,19 +823,19 @@ static inline int i2o_dma_map_sg(struct i2o_controller *c,
461 823
462#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64 824#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
463 if ((sizeof(dma_addr_t) > 4) && c->pae_support) { 825 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
464 writel(0x7C020002, mptr++); 826 *mptr++ = cpu_to_le32(0x7C020002);
465 writel(PAGE_SIZE, mptr++); 827 *mptr++ = cpu_to_le32(PAGE_SIZE);
466 } 828 }
467#endif 829#endif
468 830
469 while (sg_count-- > 0) { 831 while (sg_count-- > 0) {
470 if (!sg_count) 832 if (!sg_count)
471 sg_flags |= 0xC0000000; 833 sg_flags |= 0xC0000000;
472 writel(sg_flags | sg_dma_len(sg), mptr++); 834 *mptr++ = cpu_to_le32(sg_flags | sg_dma_len(sg));
473 writel(i2o_dma_low(sg_dma_address(sg)), mptr++); 835 *mptr++ = cpu_to_le32(i2o_dma_low(sg_dma_address(sg)));
474#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64 836#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
475 if ((sizeof(dma_addr_t) > 4) && c->pae_support) 837 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
476 writel(i2o_dma_high(sg_dma_address(sg)), mptr++); 838 *mptr++ = cpu_to_le32(i2o_dma_high(sg_dma_address(sg)));
477#endif 839#endif
478 sg++; 840 sg++;
479 } 841 }
@@ -563,6 +925,64 @@ static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
563 return 0; 925 return 0;
564}; 926};
565 927
928/*
929 * i2o_pool_alloc - Allocate an slab cache and mempool
930 * @mempool: pointer to struct i2o_pool to write data into.
931 * @name: name which is used to identify cache
932 * @size: size of each object
933 * @min_nr: minimum number of objects
934 *
935 * First allocates a slab cache with name and size. Then allocates a
936 * mempool which uses the slab cache for allocation and freeing.
937 *
938 * Returns 0 on success or negative error code on failure.
939 */
940static inline int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
941 size_t size, int min_nr)
942{
943 pool->name = kmalloc(strlen(name) + 1, GFP_KERNEL);
944 if (!pool->name)
945 goto exit;
946 strcpy(pool->name, name);
947
948 pool->slab =
949 kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL,
950 NULL);
951 if (!pool->slab)
952 goto free_name;
953
954 pool->mempool =
955 mempool_create(min_nr, mempool_alloc_slab, mempool_free_slab,
956 pool->slab);
957 if (!pool->mempool)
958 goto free_slab;
959
960 return 0;
961
962 free_slab:
963 kmem_cache_destroy(pool->slab);
964
965 free_name:
966 kfree(pool->name);
967
968 exit:
969 return -ENOMEM;
970};
971
972/*
973 * i2o_pool_free - Free slab cache and mempool again
974 * @mempool: pointer to struct i2o_pool which should be freed
975 *
976 * Note that you have to return all objects to the mempool again before
977 * calling i2o_pool_free().
978 */
979static inline void i2o_pool_free(struct i2o_pool *pool)
980{
981 mempool_destroy(pool->mempool);
982 kmem_cache_destroy(pool->slab);
983 kfree(pool->name);
984};
985
566/* I2O driver (OSM) functions */ 986/* I2O driver (OSM) functions */
567extern int i2o_driver_register(struct i2o_driver *); 987extern int i2o_driver_register(struct i2o_driver *);
568extern void i2o_driver_unregister(struct i2o_driver *); 988extern void i2o_driver_unregister(struct i2o_driver *);
@@ -638,39 +1058,89 @@ extern int i2o_exec_lct_get(struct i2o_controller *);
638#define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj)) 1058#define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
639 1059
640/** 1060/**
1061 * i2o_out_to_virt - Turn an I2O message to a virtual address
1062 * @c: controller
1063 * @m: message engine value
1064 *
1065 * Turn a receive message from an I2O controller bus address into
1066 * a Linux virtual address. The shared page frame is a linear block
1067 * so we simply have to shift the offset. This function does not
1068 * work for sender side messages as they are ioremap objects
1069 * provided by the I2O controller.
1070 */
1071static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
1072 u32 m)
1073{
1074 BUG_ON(m < c->out_queue.phys
1075 || m >= c->out_queue.phys + c->out_queue.len);
1076
1077 return c->out_queue.virt + (m - c->out_queue.phys);
1078};
1079
1080/**
1081 * i2o_msg_in_to_virt - Turn an I2O message to a virtual address
1082 * @c: controller
1083 * @m: message engine value
1084 *
1085 * Turn a send message from an I2O controller bus address into
1086 * a Linux virtual address. The shared page frame is a linear block
1087 * so we simply have to shift the offset. This function does not
1088 * work for receive side messages as they are kmalloc objects
1089 * in a different pool.
1090 */
1091static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
1092 i2o_controller *c,
1093 u32 m)
1094{
1095 return c->in_queue.virt + m;
1096};
1097
1098/**
641 * i2o_msg_get - obtain an I2O message from the IOP 1099 * i2o_msg_get - obtain an I2O message from the IOP
642 * @c: I2O controller 1100 * @c: I2O controller
643 * @msg: pointer to a I2O message pointer
644 * 1101 *
645 * This function tries to get a message slot. If no message slot is 1102 * This function tries to get a message frame. If no message frame is
646 * available do not wait until one is availabe (see also i2o_msg_get_wait). 1103 * available do not wait until one is availabe (see also i2o_msg_get_wait).
1104 * The returned pointer to the message frame is not in I/O memory, it is
1105 * allocated from a mempool. But because a MFA is allocated from the
1106 * controller too it is guaranteed that i2o_msg_post() will never fail.
647 * 1107 *
648 * On a success the message is returned and the pointer to the message is 1108 * On a success a pointer to the message frame is returned. If the message
649 * set in msg. The returned message is the physical page frame offset 1109 * queue is empty -EBUSY is returned and if no memory is available -ENOMEM
650 * address from the read port (see the i2o spec). If no message is 1110 * is returned.
651 * available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
652 */ 1111 */
653static inline u32 i2o_msg_get(struct i2o_controller *c, 1112static inline struct i2o_message *i2o_msg_get(struct i2o_controller *c)
654 struct i2o_message __iomem ** msg)
655{ 1113{
656 u32 m = readl(c->in_port); 1114 struct i2o_msg_mfa *mmsg = mempool_alloc(c->in_msg.mempool, GFP_ATOMIC);
657 1115 if (!mmsg)
658 if (m != I2O_QUEUE_EMPTY) 1116 return ERR_PTR(-ENOMEM);
659 *msg = c->in_queue.virt + m; 1117
1118 mmsg->mfa = readl(c->in_port);
1119 if (mmsg->mfa == I2O_QUEUE_EMPTY) {
1120 mempool_free(mmsg, c->in_msg.mempool);
1121 return ERR_PTR(-EBUSY);
1122 }
660 1123
661 return m; 1124 return &mmsg->msg;
662}; 1125};
663 1126
664/** 1127/**
665 * i2o_msg_post - Post I2O message to I2O controller 1128 * i2o_msg_post - Post I2O message to I2O controller
666 * @c: I2O controller to which the message should be send 1129 * @c: I2O controller to which the message should be send
667 * @m: the message identifier 1130 * @msg: message returned by i2o_msg_get()
668 * 1131 *
669 * Post the message to the I2O controller. 1132 * Post the message to the I2O controller and return immediately.
670 */ 1133 */
671static inline void i2o_msg_post(struct i2o_controller *c, u32 m) 1134static inline void i2o_msg_post(struct i2o_controller *c,
1135 struct i2o_message *msg)
672{ 1136{
673 writel(m, c->in_port); 1137 struct i2o_msg_mfa *mmsg;
1138
1139 mmsg = container_of(msg, struct i2o_msg_mfa, msg);
1140 memcpy_toio(i2o_msg_in_to_virt(c, mmsg->mfa), msg,
1141 (le32_to_cpu(msg->u.head[0]) >> 16) << 2);
1142 writel(mmsg->mfa, c->in_port);
1143 mempool_free(mmsg, c->in_msg.mempool);
674}; 1144};
675 1145
676/** 1146/**
@@ -685,62 +1155,66 @@ static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
685 * 1155 *
686 * Returns 0 on success or negative error code on failure. 1156 * Returns 0 on success or negative error code on failure.
687 */ 1157 */
688static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m, 1158static inline int i2o_msg_post_wait(struct i2o_controller *c,
1159 struct i2o_message *msg,
689 unsigned long timeout) 1160 unsigned long timeout)
690{ 1161{
691 return i2o_msg_post_wait_mem(c, m, timeout, NULL); 1162 return i2o_msg_post_wait_mem(c, msg, timeout, NULL);
692}; 1163};
693 1164
694/** 1165/**
695 * i2o_flush_reply - Flush reply from I2O controller 1166 * i2o_msg_nop_mfa - Returns a fetched MFA back to the controller
696 * @c: I2O controller 1167 * @c: I2O controller from which the MFA was fetched
697 * @m: the message identifier 1168 * @mfa: MFA which should be returned
698 * 1169 *
699 * The I2O controller must be informed that the reply message is not needed 1170 * This function must be used for preserved messages, because i2o_msg_nop()
700 * anymore. If you forget to flush the reply, the message frame can't be 1171 * also returns the allocated memory back to the msg_pool mempool.
701 * used by the controller anymore and is therefore lost.
702 */ 1172 */
703static inline void i2o_flush_reply(struct i2o_controller *c, u32 m) 1173static inline void i2o_msg_nop_mfa(struct i2o_controller *c, u32 mfa)
704{ 1174{
705 writel(m, c->out_port); 1175 struct i2o_message __iomem *msg;
1176 u32 nop[3] = {
1177 THREE_WORD_MSG_SIZE | SGL_OFFSET_0,
1178 I2O_CMD_UTIL_NOP << 24 | HOST_TID << 12 | ADAPTER_TID,
1179 0x00000000
1180 };
1181
1182 msg = i2o_msg_in_to_virt(c, mfa);
1183 memcpy_toio(msg, nop, sizeof(nop));
1184 writel(mfa, c->in_port);
706}; 1185};
707 1186
708/** 1187/**
709 * i2o_out_to_virt - Turn an I2O message to a virtual address 1188 * i2o_msg_nop - Returns a message which is not used
710 * @c: controller 1189 * @c: I2O controller from which the message was created
711 * @m: message engine value 1190 * @msg: message which should be returned
712 * 1191 *
713 * Turn a receive message from an I2O controller bus address into 1192 * If you fetch a message via i2o_msg_get, and can't use it, you must
714 * a Linux virtual address. The shared page frame is a linear block 1193 * return the message with this function. Otherwise the MFA is lost as well
715 * so we simply have to shift the offset. This function does not 1194 * as the allocated memory from the mempool.
716 * work for sender side messages as they are ioremap objects
717 * provided by the I2O controller.
718 */ 1195 */
719static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c, 1196static inline void i2o_msg_nop(struct i2o_controller *c,
720 u32 m) 1197 struct i2o_message *msg)
721{ 1198{
722 BUG_ON(m < c->out_queue.phys 1199 struct i2o_msg_mfa *mmsg;
723 || m >= c->out_queue.phys + c->out_queue.len); 1200 mmsg = container_of(msg, struct i2o_msg_mfa, msg);
724 1201
725 return c->out_queue.virt + (m - c->out_queue.phys); 1202 i2o_msg_nop_mfa(c, mmsg->mfa);
1203 mempool_free(mmsg, c->in_msg.mempool);
726}; 1204};
727 1205
728/** 1206/**
729 * i2o_msg_in_to_virt - Turn an I2O message to a virtual address 1207 * i2o_flush_reply - Flush reply from I2O controller
730 * @c: controller 1208 * @c: I2O controller
731 * @m: message engine value 1209 * @m: the message identifier
732 * 1210 *
733 * Turn a send message from an I2O controller bus address into 1211 * The I2O controller must be informed that the reply message is not needed
734 * a Linux virtual address. The shared page frame is a linear block 1212 * anymore. If you forget to flush the reply, the message frame can't be
735 * so we simply have to shift the offset. This function does not 1213 * used by the controller anymore and is therefore lost.
736 * work for receive side messages as they are kmalloc objects
737 * in a different pool.
738 */ 1214 */
739static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct 1215static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
740 i2o_controller *c,
741 u32 m)
742{ 1216{
743 return c->in_queue.virt + m; 1217 writel(m, c->out_port);
744}; 1218};
745 1219
746/* 1220/*
@@ -779,350 +1253,5 @@ extern void i2o_dump_message(struct i2o_message *);
779extern void i2o_dump_hrt(struct i2o_controller *c); 1253extern void i2o_dump_hrt(struct i2o_controller *c);
780extern void i2o_debug_state(struct i2o_controller *c); 1254extern void i2o_debug_state(struct i2o_controller *c);
781 1255
782/*
783 * Cache strategies
784 */
785
786/* The NULL strategy leaves everything up to the controller. This tends to be a
787 * pessimal but functional choice.
788 */
789#define CACHE_NULL 0
790/* Prefetch data when reading. We continually attempt to load the next 32 sectors
791 * into the controller cache.
792 */
793#define CACHE_PREFETCH 1
794/* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
795 * into the controller cache. When an I/O is less <= 8K we assume its probably
796 * not sequential and don't prefetch (default)
797 */
798#define CACHE_SMARTFETCH 2
799/* Data is written to the cache and then out on to the disk. The I/O must be
800 * physically on the medium before the write is acknowledged (default without
801 * NVRAM)
802 */
803#define CACHE_WRITETHROUGH 17
804/* Data is written to the cache and then out on to the disk. The controller
805 * is permitted to write back the cache any way it wants. (default if battery
806 * backed NVRAM is present). It can be useful to set this for swap regardless of
807 * battery state.
808 */
809#define CACHE_WRITEBACK 18
810/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
811 * write large I/O's directly to disk bypassing the cache to avoid the extra
812 * memory copy hits. Small writes are writeback cached
813 */
814#define CACHE_SMARTBACK 19
815/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
816 * write large I/O's directly to disk bypassing the cache to avoid the extra
817 * memory copy hits. Small writes are writethrough cached. Suitable for devices
818 * lacking battery backup
819 */
820#define CACHE_SMARTTHROUGH 20
821
822/*
823 * Ioctl structures
824 */
825
826#define BLKI2OGRSTRAT _IOR('2', 1, int)
827#define BLKI2OGWSTRAT _IOR('2', 2, int)
828#define BLKI2OSRSTRAT _IOW('2', 3, int)
829#define BLKI2OSWSTRAT _IOW('2', 4, int)
830
831/*
832 * I2O Function codes
833 */
834
835/*
836 * Executive Class
837 */
838#define I2O_CMD_ADAPTER_ASSIGN 0xB3
839#define I2O_CMD_ADAPTER_READ 0xB2
840#define I2O_CMD_ADAPTER_RELEASE 0xB5
841#define I2O_CMD_BIOS_INFO_SET 0xA5
842#define I2O_CMD_BOOT_DEVICE_SET 0xA7
843#define I2O_CMD_CONFIG_VALIDATE 0xBB
844#define I2O_CMD_CONN_SETUP 0xCA
845#define I2O_CMD_DDM_DESTROY 0xB1
846#define I2O_CMD_DDM_ENABLE 0xD5
847#define I2O_CMD_DDM_QUIESCE 0xC7
848#define I2O_CMD_DDM_RESET 0xD9
849#define I2O_CMD_DDM_SUSPEND 0xAF
850#define I2O_CMD_DEVICE_ASSIGN 0xB7
851#define I2O_CMD_DEVICE_RELEASE 0xB9
852#define I2O_CMD_HRT_GET 0xA8
853#define I2O_CMD_ADAPTER_CLEAR 0xBE
854#define I2O_CMD_ADAPTER_CONNECT 0xC9
855#define I2O_CMD_ADAPTER_RESET 0xBD
856#define I2O_CMD_LCT_NOTIFY 0xA2
857#define I2O_CMD_OUTBOUND_INIT 0xA1
858#define I2O_CMD_PATH_ENABLE 0xD3
859#define I2O_CMD_PATH_QUIESCE 0xC5
860#define I2O_CMD_PATH_RESET 0xD7
861#define I2O_CMD_STATIC_MF_CREATE 0xDD
862#define I2O_CMD_STATIC_MF_RELEASE 0xDF
863#define I2O_CMD_STATUS_GET 0xA0
864#define I2O_CMD_SW_DOWNLOAD 0xA9
865#define I2O_CMD_SW_UPLOAD 0xAB
866#define I2O_CMD_SW_REMOVE 0xAD
867#define I2O_CMD_SYS_ENABLE 0xD1
868#define I2O_CMD_SYS_MODIFY 0xC1
869#define I2O_CMD_SYS_QUIESCE 0xC3
870#define I2O_CMD_SYS_TAB_SET 0xA3
871
872/*
873 * Utility Class
874 */
875#define I2O_CMD_UTIL_NOP 0x00
876#define I2O_CMD_UTIL_ABORT 0x01
877#define I2O_CMD_UTIL_CLAIM 0x09
878#define I2O_CMD_UTIL_RELEASE 0x0B
879#define I2O_CMD_UTIL_PARAMS_GET 0x06
880#define I2O_CMD_UTIL_PARAMS_SET 0x05
881#define I2O_CMD_UTIL_EVT_REGISTER 0x13
882#define I2O_CMD_UTIL_EVT_ACK 0x14
883#define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
884#define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
885#define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
886#define I2O_CMD_UTIL_LOCK 0x17
887#define I2O_CMD_UTIL_LOCK_RELEASE 0x19
888#define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
889
890/*
891 * SCSI Host Bus Adapter Class
892 */
893#define I2O_CMD_SCSI_EXEC 0x81
894#define I2O_CMD_SCSI_ABORT 0x83
895#define I2O_CMD_SCSI_BUSRESET 0x27
896
897/*
898 * Bus Adapter Class
899 */
900#define I2O_CMD_BUS_ADAPTER_RESET 0x85
901#define I2O_CMD_BUS_RESET 0x87
902#define I2O_CMD_BUS_SCAN 0x89
903#define I2O_CMD_BUS_QUIESCE 0x8b
904
905/*
906 * Random Block Storage Class
907 */
908#define I2O_CMD_BLOCK_READ 0x30
909#define I2O_CMD_BLOCK_WRITE 0x31
910#define I2O_CMD_BLOCK_CFLUSH 0x37
911#define I2O_CMD_BLOCK_MLOCK 0x49
912#define I2O_CMD_BLOCK_MUNLOCK 0x4B
913#define I2O_CMD_BLOCK_MMOUNT 0x41
914#define I2O_CMD_BLOCK_MEJECT 0x43
915#define I2O_CMD_BLOCK_POWER 0x70
916
917#define I2O_CMD_PRIVATE 0xFF
918
919/* Command status values */
920
921#define I2O_CMD_IN_PROGRESS 0x01
922#define I2O_CMD_REJECTED 0x02
923#define I2O_CMD_FAILED 0x03
924#define I2O_CMD_COMPLETED 0x04
925
926/* I2O API function return values */
927
928#define I2O_RTN_NO_ERROR 0
929#define I2O_RTN_NOT_INIT 1
930#define I2O_RTN_FREE_Q_EMPTY 2
931#define I2O_RTN_TCB_ERROR 3
932#define I2O_RTN_TRANSACTION_ERROR 4
933#define I2O_RTN_ADAPTER_ALREADY_INIT 5
934#define I2O_RTN_MALLOC_ERROR 6
935#define I2O_RTN_ADPTR_NOT_REGISTERED 7
936#define I2O_RTN_MSG_REPLY_TIMEOUT 8
937#define I2O_RTN_NO_STATUS 9
938#define I2O_RTN_NO_FIRM_VER 10
939#define I2O_RTN_NO_LINK_SPEED 11
940
941/* Reply message status defines for all messages */
942
943#define I2O_REPLY_STATUS_SUCCESS 0x00
944#define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
945#define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
946#define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
947#define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
948#define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
949#define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
950#define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
951#define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
952#define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
953#define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
954#define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
955
956/* Status codes and Error Information for Parameter functions */
957
958#define I2O_PARAMS_STATUS_SUCCESS 0x00
959#define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
960#define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
961#define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
962#define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
963#define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
964#define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
965#define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
966#define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
967#define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
968#define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
969#define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
970#define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
971#define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
972#define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
973#define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
974#define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
975
976/* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
977 * messages: Table 3-2 Detailed Status Codes.*/
978
979#define I2O_DSC_SUCCESS 0x0000
980#define I2O_DSC_BAD_KEY 0x0002
981#define I2O_DSC_TCL_ERROR 0x0003
982#define I2O_DSC_REPLY_BUFFER_FULL 0x0004
983#define I2O_DSC_NO_SUCH_PAGE 0x0005
984#define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
985#define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
986#define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
987#define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
988#define I2O_DSC_DEVICE_LOCKED 0x000B
989#define I2O_DSC_DEVICE_RESET 0x000C
990#define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
991#define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
992#define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
993#define I2O_DSC_INVALID_OFFSET 0x0010
994#define I2O_DSC_INVALID_PARAMETER 0x0011
995#define I2O_DSC_INVALID_REQUEST 0x0012
996#define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
997#define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
998#define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
999#define I2O_DSC_MISSING_PARAMETER 0x0016
1000#define I2O_DSC_TIMEOUT 0x0017
1001#define I2O_DSC_UNKNOWN_ERROR 0x0018
1002#define I2O_DSC_UNKNOWN_FUNCTION 0x0019
1003#define I2O_DSC_UNSUPPORTED_VERSION 0x001A
1004#define I2O_DSC_DEVICE_BUSY 0x001B
1005#define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
1006
1007/* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
1008 Status Codes.*/
1009
1010#define I2O_BSA_DSC_SUCCESS 0x0000
1011#define I2O_BSA_DSC_MEDIA_ERROR 0x0001
1012#define I2O_BSA_DSC_ACCESS_ERROR 0x0002
1013#define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
1014#define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
1015#define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
1016#define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
1017#define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
1018#define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
1019#define I2O_BSA_DSC_BUS_FAILURE 0x0009
1020#define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
1021#define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
1022#define I2O_BSA_DSC_DEVICE_RESET 0x000C
1023#define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
1024#define I2O_BSA_DSC_TIMEOUT 0x000E
1025
1026/* FailureStatusCodes, Table 3-3 Message Failure Codes */
1027
1028#define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
1029#define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
1030#define I2O_FSC_TRANSPORT_CONGESTION 0x83
1031#define I2O_FSC_TRANSPORT_FAILURE 0x84
1032#define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
1033#define I2O_FSC_TRANSPORT_TIME_OUT 0x86
1034#define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
1035#define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
1036#define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
1037#define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
1038#define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
1039#define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
1040#define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
1041#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
1042#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
1043#define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
1044
1045/* Device Claim Types */
1046#define I2O_CLAIM_PRIMARY 0x01000000
1047#define I2O_CLAIM_MANAGEMENT 0x02000000
1048#define I2O_CLAIM_AUTHORIZED 0x03000000
1049#define I2O_CLAIM_SECONDARY 0x04000000
1050
1051/* Message header defines for VersionOffset */
1052#define I2OVER15 0x0001
1053#define I2OVER20 0x0002
1054
1055/* Default is 1.5 */
1056#define I2OVERSION I2OVER15
1057
1058#define SGL_OFFSET_0 I2OVERSION
1059#define SGL_OFFSET_4 (0x0040 | I2OVERSION)
1060#define SGL_OFFSET_5 (0x0050 | I2OVERSION)
1061#define SGL_OFFSET_6 (0x0060 | I2OVERSION)
1062#define SGL_OFFSET_7 (0x0070 | I2OVERSION)
1063#define SGL_OFFSET_8 (0x0080 | I2OVERSION)
1064#define SGL_OFFSET_9 (0x0090 | I2OVERSION)
1065#define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
1066#define SGL_OFFSET_11 (0x00B0 | I2OVERSION)
1067#define SGL_OFFSET_12 (0x00C0 | I2OVERSION)
1068#define SGL_OFFSET(x) (((x)<<4) | I2OVERSION)
1069
1070/* Transaction Reply Lists (TRL) Control Word structure */
1071#define TRL_SINGLE_FIXED_LENGTH 0x00
1072#define TRL_SINGLE_VARIABLE_LENGTH 0x40
1073#define TRL_MULTIPLE_FIXED_LENGTH 0x80
1074
1075 /* msg header defines for MsgFlags */
1076#define MSG_STATIC 0x0100
1077#define MSG_64BIT_CNTXT 0x0200
1078#define MSG_MULTI_TRANS 0x1000
1079#define MSG_FAIL 0x2000
1080#define MSG_FINAL 0x4000
1081#define MSG_REPLY 0x8000
1082
1083 /* minimum size msg */
1084#define THREE_WORD_MSG_SIZE 0x00030000
1085#define FOUR_WORD_MSG_SIZE 0x00040000
1086#define FIVE_WORD_MSG_SIZE 0x00050000
1087#define SIX_WORD_MSG_SIZE 0x00060000
1088#define SEVEN_WORD_MSG_SIZE 0x00070000
1089#define EIGHT_WORD_MSG_SIZE 0x00080000
1090#define NINE_WORD_MSG_SIZE 0x00090000
1091#define TEN_WORD_MSG_SIZE 0x000A0000
1092#define ELEVEN_WORD_MSG_SIZE 0x000B0000
1093#define I2O_MESSAGE_SIZE(x) ((x)<<16)
1094
1095/* special TID assignments */
1096#define ADAPTER_TID 0
1097#define HOST_TID 1
1098
1099/* outbound queue defines */
1100#define I2O_MAX_OUTBOUND_MSG_FRAMES 128
1101#define I2O_OUTBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
1102
1103#define I2O_POST_WAIT_OK 0
1104#define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
1105
1106#define I2O_CONTEXT_LIST_MIN_LENGTH 15
1107#define I2O_CONTEXT_LIST_USED 0x01
1108#define I2O_CONTEXT_LIST_DELETED 0x02
1109
1110/* timeouts */
1111#define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
1112#define I2O_TIMEOUT_MESSAGE_GET 5
1113#define I2O_TIMEOUT_RESET 30
1114#define I2O_TIMEOUT_STATUS_GET 5
1115#define I2O_TIMEOUT_LCT_GET 360
1116#define I2O_TIMEOUT_SCSI_SCB_ABORT 240
1117
1118/* retries */
1119#define I2O_HRT_GET_TRIES 3
1120#define I2O_LCT_GET_TRIES 3
1121
1122/* defines for max_sectors and max_phys_segments */
1123#define I2O_MAX_SECTORS 1024
1124#define I2O_MAX_SECTORS_LIMITED 256
1125#define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
1126
1127#endif /* __KERNEL__ */ 1256#endif /* __KERNEL__ */
1128#endif /* _I2O_H */ 1257#endif /* _I2O_H */