7 files changed, 192 insertions, 25 deletions

diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 6001b4da39dd..627a3a42e4d8 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -302,6 +302,10 @@ extern bool osc_sb_apei_support_acked;
                                 OSC_PCI_EXPRESS_PME_CONTROL |           \
                                 OSC_PCI_EXPRESS_AER_CONTROL |           \
                                 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL)
+
+#define OSC_PCI_NATIVE_HOTPLUG  (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL |    \
+                                OSC_SHPC_NATIVE_HP_CONTROL)
+
 extern acpi_status acpi_pci_osc_control_set(acpi_handle handle,
                                              u32 *mask, u32 req);
 extern void acpi_early_init(void);
diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h
index a6863a2dec1f..ef00610837d4 100644
--- a/include/linux/amd-iommu.h
+++ b/include/linux/amd-iommu.h
@@ -20,12 +20,148 @@
 #ifndef _ASM_X86_AMD_IOMMU_H
 #define _ASM_X86_AMD_IOMMU_H
 
-#include <linux/irqreturn.h>
+#include <linux/types.h>
 
 #ifdef CONFIG_AMD_IOMMU
 
+struct task_struct;
+struct pci_dev;
+
 extern int amd_iommu_detect(void);
 
+
+/**
+ * amd_iommu_enable_device_erratum() - Enable erratum workaround for device
+ *                                     in the IOMMUv2 driver
+ * @pdev: The PCI device the workaround is necessary for
+ * @erratum: The erratum workaround to enable
+ *
+ * The function needs to be called before amd_iommu_init_device().
+ * Possible values for the erratum number are for now:
+ * - AMD_PRI_DEV_ERRATUM_ENABLE_RESET - Reset PRI capability when PRI
+ *                                      is enabled
+ * - AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE - Limit number of outstanding PRI
+ *                                       requests to one
+ */
+#define AMD_PRI_DEV_ERRATUM_ENABLE_RESET                0
+#define AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE               1
+
+extern void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum);
+
+/**
+ * amd_iommu_init_device() - Init device for use with IOMMUv2 driver
+ * @pdev: The PCI device to initialize
+ * @pasids: Number of PASIDs to support for this device
+ *
+ * This function does all setup for the device pdev so that it can be
+ * used with IOMMUv2.
+ * Returns 0 on success or negative value on error.
+ */
+extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
+
+/**
+ * amd_iommu_free_device() - Free all IOMMUv2 related device resources
+ *                           and disable IOMMUv2 usage for this device
+ * @pdev: The PCI device to disable IOMMUv2 usage for'
+ */
+extern void amd_iommu_free_device(struct pci_dev *pdev);
+
+/**
+ * amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
+ * @pdev: The PCI device to bind the task to
+ * @pasid: The PASID on the device the task should be bound to
+ * @task: the task to bind
+ *
+ * The function returns 0 on success or a negative value on error.
+ */
+extern int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
+                                struct task_struct *task);
+
+/**
+ * amd_iommu_unbind_pasid() - Unbind a PASID from its task on
+ *                            a device
+ * @pdev: The device of the PASID
+ * @pasid: The PASID to unbind
+ *
+ * When this function returns the device is no longer using the PASID
+ * and the PASID is no longer bound to its task.
+ */
+extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid);
+
+/**
+ * amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
+ *                                  PRI requests
+ * @pdev: The PCI device the call-back should be registered for
+ * @cb: The call-back function
+ *
+ * The IOMMUv2 driver invokes this call-back when it is unable to
+ * successfully handle a PRI request. The device driver can then decide
+ * which PRI response the device should see. Possible return values for
+ * the call-back are:
+ *
+ * - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
+ * - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
+ * - AMD_IOMMU_INV_PRI_RSP_FAIL    - Send Failure back to the device,
+ *                                   the device is required to disable
+ *                                   PRI when it receives this response
+ *
+ * The function returns 0 on success or negative value on error.
+ */
+#define AMD_IOMMU_INV_PRI_RSP_SUCCESS   0
+#define AMD_IOMMU_INV_PRI_RSP_INVALID   1
+#define AMD_IOMMU_INV_PRI_RSP_FAIL      2
+
+typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
+                                        int pasid,
+                                        unsigned long address,
+                                        u16);
+
+extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
+                                        amd_iommu_invalid_ppr_cb cb);
+
+/**
+ * amd_iommu_device_info() - Get information about IOMMUv2 support of a
+ *                           PCI device
+ * @pdev: PCI device to query information from
+ * @info: A pointer to an amd_iommu_device_info structure which will contain
+ *        the information about the PCI device
+ *
+ * Returns 0 on success, negative value on error
+ */
+
+#define AMD_IOMMU_DEVICE_FLAG_ATS_SUP     0x1    /* ATS feature supported */
+#define AMD_IOMMU_DEVICE_FLAG_PRI_SUP     0x2    /* PRI feature supported */
+#define AMD_IOMMU_DEVICE_FLAG_PASID_SUP   0x4    /* PASID context supported */
+#define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP    0x8    /* Device may request execution
+                                                    on memory pages */
+#define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP   0x10    /* Device may request
+                                                    super-user privileges */
+
+struct amd_iommu_device_info {
+        int max_pasids;
+        u32 flags;
+};
+
+extern int amd_iommu_device_info(struct pci_dev *pdev,
+                                 struct amd_iommu_device_info *info);
+
+/**
+ * amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
+ *                                     a pasid context. This call-back is
+ *                                     invoked when the IOMMUv2 driver needs to
+ *                                     invalidate a PASID context, for example
+ *                                     because the task that is bound to that
+ *                                     context is about to exit.
+ *
+ * @pdev: The PCI device the call-back should be registered for
+ * @cb: The call-back function
+ */
+
+typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, int pasid);
+
+extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
+                                           amd_iommu_invalidate_ctx cb);
+
 #else
 
 static inline int amd_iommu_detect(void) { return -ENODEV; }
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 432acc4c054d..d937580417ba 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -48,19 +48,34 @@ struct iommu_domain {
 
 #ifdef CONFIG_IOMMU_API
 
+/**
+ * struct iommu_ops - iommu ops and capabilities
+ * @domain_init: init iommu domain
+ * @domain_destroy: destroy iommu domain
+ * @attach_dev: attach device to an iommu domain
+ * @detach_dev: detach device from an iommu domain
+ * @map: map a physically contiguous memory region to an iommu domain
+ * @unmap: unmap a physically contiguous memory region from an iommu domain
+ * @iova_to_phys: translate iova to physical address
+ * @domain_has_cap: domain capabilities query
+ * @commit: commit iommu domain
+ * @pgsize_bitmap: bitmap of supported page sizes
+ */
 struct iommu_ops {
         int (*domain_init)(struct iommu_domain *domain);
         void (*domain_destroy)(struct iommu_domain *domain);
         int (*attach_dev)(struct iommu_domain *domain, struct device *dev);
         void (*detach_dev)(struct iommu_domain *domain, struct device *dev);
         int (*map)(struct iommu_domain *domain, unsigned long iova,
-                   phys_addr_t paddr, int gfp_order, int prot);
-        int (*unmap)(struct iommu_domain *domain, unsigned long iova,
-                     int gfp_order);
+                   phys_addr_t paddr, size_t size, int prot);
+        size_t (*unmap)(struct iommu_domain *domain, unsigned long iova,
+                     size_t size);
         phys_addr_t (*iova_to_phys)(struct iommu_domain *domain,
                                     unsigned long iova);
         int (*domain_has_cap)(struct iommu_domain *domain,
                               unsigned long cap);
+        int (*device_group)(struct device *dev, unsigned int *groupid);
+        unsigned long pgsize_bitmap;
 };
 
 extern int bus_set_iommu(struct bus_type *bus, struct iommu_ops *ops);
@@ -72,15 +87,16 @@ extern int iommu_attach_device(struct iommu_domain *domain,
 extern void iommu_detach_device(struct iommu_domain *domain,
                                 struct device *dev);
 extern int iommu_map(struct iommu_domain *domain, unsigned long iova,
-                     phys_addr_t paddr, int gfp_order, int prot);
-extern int iommu_unmap(struct iommu_domain *domain, unsigned long iova,
-                       int gfp_order);
+                     phys_addr_t paddr, size_t size, int prot);
+extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova,
+                       size_t size);
 extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain,
                                       unsigned long iova);
 extern int iommu_domain_has_cap(struct iommu_domain *domain,
                                 unsigned long cap);
 extern void iommu_set_fault_handler(struct iommu_domain *domain,
                                         iommu_fault_handler_t handler);
+extern int iommu_device_group(struct device *dev, unsigned int *groupid);
 
 /**
  * report_iommu_fault() - report about an IOMMU fault to the IOMMU framework
@@ -179,6 +195,11 @@ static inline void iommu_set_fault_handler(struct iommu_domain *domain,
 {
 }
 
+static inline int iommu_device_group(struct device *dev, unsigned int *groupid)
+{
+        return -ENODEV;
+}
+
 #endif /* CONFIG_IOMMU_API */
 
 #endif /* __LINUX_IOMMU_H */
diff --git a/include/linux/msi.h b/include/linux/msi.h
index 05acced439a3..ce93a341337d 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -1,6 +1,7 @@
 #ifndef LINUX_MSI_H
 #define LINUX_MSI_H
 
+#include <linux/kobject.h>
 #include <linux/list.h>
 
 struct msi_msg {
@@ -44,6 +45,8 @@ struct msi_desc {
 
         /* Last set MSI message */
         struct msi_msg msg;
+
+        struct kobject kobj;
 };
 
 /*
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
index 7cea7b6c1413..c8320144fe79 100644
--- a/include/linux/pci-aspm.h
+++ b/include/linux/pci-aspm.h
@@ -29,7 +29,7 @@ extern void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 extern void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 extern void pci_disable_link_state(struct pci_dev *pdev, int state);
 extern void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
-extern void pcie_clear_aspm(void);
+extern void pcie_clear_aspm(struct pci_bus *bus);
 extern void pcie_no_aspm(void);
 #else
 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
@@ -47,7 +47,7 @@ static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
 static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
 {
 }
-static inline void pcie_clear_aspm(void)
+static inline void pcie_clear_aspm(struct pci_bus *bus)
 {
 }
 static inline void pcie_no_aspm(void)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 7cda65b5f798..84225c756bd1 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -336,6 +336,7 @@ struct pci_dev {
         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
 #ifdef CONFIG_PCI_MSI
         struct list_head msi_list;
+        struct kset *msi_kset;
 #endif
         struct pci_vpd *vpd;
 #ifdef CONFIG_PCI_ATS
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index b5d9657f3100..28fe380cb19d 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -537,7 +537,9 @@
 #define PCI_EXT_CAP_ID_ARI      14
 #define PCI_EXT_CAP_ID_ATS      15
 #define PCI_EXT_CAP_ID_SRIOV    16
+#define PCI_EXT_CAP_ID_PRI      19
 #define PCI_EXT_CAP_ID_LTR      24
+#define PCI_EXT_CAP_ID_PASID    27
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
@@ -664,24 +666,24 @@
 #define  PCI_ATS_MIN_STU        12      /* shift of minimum STU block */
 
 /* Page Request Interface */
-#define PCI_PRI_CAP             0x13    /* PRI capability ID */
-#define PCI_PRI_CONTROL_OFF     0x04    /* Offset of control register */
-#define PCI_PRI_STATUS_OFF      0x06    /* Offset of status register */
-#define PCI_PRI_ENABLE          0x0001  /* Enable mask */
-#define PCI_PRI_RESET           0x0002  /* Reset bit mask */
-#define PCI_PRI_STATUS_RF       0x0001  /* Request Failure */
-#define PCI_PRI_STATUS_UPRGI    0x0002  /* Unexpected PRG index */
-#define PCI_PRI_STATUS_STOPPED  0x0100  /* PRI Stopped */
-#define PCI_PRI_MAX_REQ_OFF     0x08    /* Cap offset for max reqs supported */
-#define PCI_PRI_ALLOC_REQ_OFF   0x0c    /* Cap offset for max reqs allowed */
+#define PCI_PRI_CTRL            0x04    /* PRI control register */
+#define  PCI_PRI_CTRL_ENABLE    0x01    /* Enable */
+#define  PCI_PRI_CTRL_RESET     0x02    /* Reset */
+#define PCI_PRI_STATUS          0x06    /* PRI status register */
+#define  PCI_PRI_STATUS_RF      0x001   /* Response Failure */
+#define  PCI_PRI_STATUS_UPRGI   0x002   /* Unexpected PRG index */
+#define  PCI_PRI_STATUS_STOPPED 0x100   /* PRI Stopped */
+#define PCI_PRI_MAX_REQ         0x08    /* PRI max reqs supported */
+#define PCI_PRI_ALLOC_REQ       0x0c    /* PRI max reqs allowed */
 
 /* PASID capability */
-#define PCI_PASID_CAP           0x1b    /* PASID capability ID */
-#define PCI_PASID_CAP_OFF       0x04    /* PASID feature register */
-#define PCI_PASID_CONTROL_OFF   0x06    /* PASID control register */
-#define PCI_PASID_ENABLE        0x01    /* Enable/Supported bit */
-#define PCI_PASID_EXEC          0x02    /* Exec permissions Enable/Supported */
-#define PCI_PASID_PRIV          0x04    /* Priviledge Mode Enable/Support */
+#define PCI_PASID_CAP           0x04    /* PASID feature register */
+#define  PCI_PASID_CAP_EXEC     0x02    /* Exec permissions Supported */
+#define  PCI_PASID_CAP_PRIV     0x04    /* Priviledge Mode Supported */
+#define PCI_PASID_CTRL          0x06    /* PASID control register */
+#define  PCI_PASID_CTRL_ENABLE  0x01    /* Enable bit */
+#define  PCI_PASID_CTRL_EXEC    0x02    /* Exec permissions Enable */
+#define  PCI_PASID_CTRL_PRIV    0x04    /* Priviledge Mode Enable */
 
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */