aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/spi/dw_spi.h233
-rw-r--r--include/linux/spi/mcp23s08.h15
-rw-r--r--include/linux/spi/spi_oc_tiny.h20
3 files changed, 29 insertions, 239 deletions
diff --git a/include/linux/spi/dw_spi.h b/include/linux/spi/dw_spi.h
deleted file mode 100644
index 6cd10f6ad472..000000000000
--- a/include/linux/spi/dw_spi.h
+++ /dev/null
@@ -1,233 +0,0 @@
1#ifndef DW_SPI_HEADER_H
2#define DW_SPI_HEADER_H
3
4#include <linux/io.h>
5
6/* Bit fields in CTRLR0 */
7#define SPI_DFS_OFFSET 0
8
9#define SPI_FRF_OFFSET 4
10#define SPI_FRF_SPI 0x0
11#define SPI_FRF_SSP 0x1
12#define SPI_FRF_MICROWIRE 0x2
13#define SPI_FRF_RESV 0x3
14
15#define SPI_MODE_OFFSET 6
16#define SPI_SCPH_OFFSET 6
17#define SPI_SCOL_OFFSET 7
18
19#define SPI_TMOD_OFFSET 8
20#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
21#define SPI_TMOD_TR 0x0 /* xmit & recv */
22#define SPI_TMOD_TO 0x1 /* xmit only */
23#define SPI_TMOD_RO 0x2 /* recv only */
24#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
25
26#define SPI_SLVOE_OFFSET 10
27#define SPI_SRL_OFFSET 11
28#define SPI_CFS_OFFSET 12
29
30/* Bit fields in SR, 7 bits */
31#define SR_MASK 0x7f /* cover 7 bits */
32#define SR_BUSY (1 << 0)
33#define SR_TF_NOT_FULL (1 << 1)
34#define SR_TF_EMPT (1 << 2)
35#define SR_RF_NOT_EMPT (1 << 3)
36#define SR_RF_FULL (1 << 4)
37#define SR_TX_ERR (1 << 5)
38#define SR_DCOL (1 << 6)
39
40/* Bit fields in ISR, IMR, RISR, 7 bits */
41#define SPI_INT_TXEI (1 << 0)
42#define SPI_INT_TXOI (1 << 1)
43#define SPI_INT_RXUI (1 << 2)
44#define SPI_INT_RXOI (1 << 3)
45#define SPI_INT_RXFI (1 << 4)
46#define SPI_INT_MSTI (1 << 5)
47
48/* TX RX interrupt level threshhold, max can be 256 */
49#define SPI_INT_THRESHOLD 32
50
51enum dw_ssi_type {
52 SSI_MOTO_SPI = 0,
53 SSI_TI_SSP,
54 SSI_NS_MICROWIRE,
55};
56
57struct dw_spi_reg {
58 u32 ctrl0;
59 u32 ctrl1;
60 u32 ssienr;
61 u32 mwcr;
62 u32 ser;
63 u32 baudr;
64 u32 txfltr;
65 u32 rxfltr;
66 u32 txflr;
67 u32 rxflr;
68 u32 sr;
69 u32 imr;
70 u32 isr;
71 u32 risr;
72 u32 txoicr;
73 u32 rxoicr;
74 u32 rxuicr;
75 u32 msticr;
76 u32 icr;
77 u32 dmacr;
78 u32 dmatdlr;
79 u32 dmardlr;
80 u32 idr;
81 u32 version;
82 u32 dr; /* Currently oper as 32 bits,
83 though only low 16 bits matters */
84} __packed;
85
86struct dw_spi;
87struct dw_spi_dma_ops {
88 int (*dma_init)(struct dw_spi *dws);
89 void (*dma_exit)(struct dw_spi *dws);
90 int (*dma_transfer)(struct dw_spi *dws, int cs_change);
91};
92
93struct dw_spi {
94 struct spi_master *master;
95 struct spi_device *cur_dev;
96 struct device *parent_dev;
97 enum dw_ssi_type type;
98
99 void __iomem *regs;
100 unsigned long paddr;
101 u32 iolen;
102 int irq;
103 u32 fifo_len; /* depth of the FIFO buffer */
104 u32 max_freq; /* max bus freq supported */
105
106 u16 bus_num;
107 u16 num_cs; /* supported slave numbers */
108
109 /* Driver message queue */
110 struct workqueue_struct *workqueue;
111 struct work_struct pump_messages;
112 spinlock_t lock;
113 struct list_head queue;
114 int busy;
115 int run;
116
117 /* Message Transfer pump */
118 struct tasklet_struct pump_transfers;
119
120 /* Current message transfer state info */
121 struct spi_message *cur_msg;
122 struct spi_transfer *cur_transfer;
123 struct chip_data *cur_chip;
124 struct chip_data *prev_chip;
125 size_t len;
126 void *tx;
127 void *tx_end;
128 void *rx;
129 void *rx_end;
130 int dma_mapped;
131 dma_addr_t rx_dma;
132 dma_addr_t tx_dma;
133 size_t rx_map_len;
134 size_t tx_map_len;
135 u8 n_bytes; /* current is a 1/2 bytes op */
136 u8 max_bits_per_word; /* maxim is 16b */
137 u32 dma_width;
138 int cs_change;
139 int (*write)(struct dw_spi *dws);
140 int (*read)(struct dw_spi *dws);
141 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
142 void (*cs_control)(u32 command);
143
144 /* Dma info */
145 int dma_inited;
146 struct dma_chan *txchan;
147 struct scatterlist tx_sgl;
148 struct dma_chan *rxchan;
149 struct scatterlist rx_sgl;
150 int dma_chan_done;
151 struct device *dma_dev;
152 dma_addr_t dma_addr; /* phy address of the Data register */
153 struct dw_spi_dma_ops *dma_ops;
154 void *dma_priv; /* platform relate info */
155 struct pci_dev *dmac;
156
157 /* Bus interface info */
158 void *priv;
159#ifdef CONFIG_DEBUG_FS
160 struct dentry *debugfs;
161#endif
162};
163
164#define dw_readl(dw, name) \
165 __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
166#define dw_writel(dw, name, val) \
167 __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
168#define dw_readw(dw, name) \
169 __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
170#define dw_writew(dw, name, val) \
171 __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
172
173static inline void spi_enable_chip(struct dw_spi *dws, int enable)
174{
175 dw_writel(dws, ssienr, (enable ? 1 : 0));
176}
177
178static inline void spi_set_clk(struct dw_spi *dws, u16 div)
179{
180 dw_writel(dws, baudr, div);
181}
182
183static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
184{
185 if (cs > dws->num_cs)
186 return;
187
188 if (dws->cs_control)
189 dws->cs_control(1);
190
191 dw_writel(dws, ser, 1 << cs);
192}
193
194/* Disable IRQ bits */
195static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
196{
197 u32 new_mask;
198
199 new_mask = dw_readl(dws, imr) & ~mask;
200 dw_writel(dws, imr, new_mask);
201}
202
203/* Enable IRQ bits */
204static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
205{
206 u32 new_mask;
207
208 new_mask = dw_readl(dws, imr) | mask;
209 dw_writel(dws, imr, new_mask);
210}
211
212/*
213 * Each SPI slave device to work with dw_api controller should
214 * has such a structure claiming its working mode (PIO/DMA etc),
215 * which can be save in the "controller_data" member of the
216 * struct spi_device
217 */
218struct dw_spi_chip {
219 u8 poll_mode; /* 0 for contoller polling mode */
220 u8 type; /* SPI/SSP/Micrwire */
221 u8 enable_dma;
222 void (*cs_control)(u32 command);
223};
224
225extern int dw_spi_add_host(struct dw_spi *dws);
226extern void dw_spi_remove_host(struct dw_spi *dws);
227extern int dw_spi_suspend_host(struct dw_spi *dws);
228extern int dw_spi_resume_host(struct dw_spi *dws);
229extern void dw_spi_xfer_done(struct dw_spi *dws);
230
231/* platform related setup */
232extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
233#endif /* DW_SPI_HEADER_H */
diff --git a/include/linux/spi/mcp23s08.h b/include/linux/spi/mcp23s08.h
index 22ef107d7704..c42cff8ca191 100644
--- a/include/linux/spi/mcp23s08.h
+++ b/include/linux/spi/mcp23s08.h
@@ -2,21 +2,24 @@
2/* FIXME driver should be able to handle IRQs... */ 2/* FIXME driver should be able to handle IRQs... */
3 3
4struct mcp23s08_chip_info { 4struct mcp23s08_chip_info {
5 bool is_present; /* true iff populated */ 5 bool is_present; /* true if populated */
6 u8 pullups; /* BIT(x) means enable pullup x */ 6 unsigned pullups; /* BIT(x) means enable pullup x */
7}; 7};
8 8
9struct mcp23s08_platform_data { 9struct mcp23s08_platform_data {
10 /* Four slaves (numbered 0..3) can share one SPI chipselect, and 10 /* For mcp23s08, up to 4 slaves (numbered 0..3) can share one SPI
11 * will provide 8..32 GPIOs using 1..4 gpio_chip instances. 11 * chipselect, each providing 1 gpio_chip instance with 8 gpios.
12 * For mpc23s17, up to 8 slaves (numbered 0..7) can share one SPI
13 * chipselect, each providing 1 gpio_chip (port A + port B) with
14 * 16 gpios.
12 */ 15 */
13 struct mcp23s08_chip_info chip[4]; 16 struct mcp23s08_chip_info chip[8];
14 17
15 /* "base" is the number of the first GPIO. Dynamic assignment is 18 /* "base" is the number of the first GPIO. Dynamic assignment is
16 * not currently supported, and even if there are gaps in chip 19 * not currently supported, and even if there are gaps in chip
17 * addressing the GPIO numbers are sequential .. so for example 20 * addressing the GPIO numbers are sequential .. so for example
18 * if only slaves 0 and 3 are present, their GPIOs range from 21 * if only slaves 0 and 3 are present, their GPIOs range from
19 * base to base+15. 22 * base to base+15 (or base+31 for s17 variant).
20 */ 23 */
21 unsigned base; 24 unsigned base;
22 25
diff --git a/include/linux/spi/spi_oc_tiny.h b/include/linux/spi/spi_oc_tiny.h
new file mode 100644
index 000000000000..1ac529cf4f06
--- /dev/null
+++ b/include/linux/spi/spi_oc_tiny.h
@@ -0,0 +1,20 @@
1#ifndef _LINUX_SPI_SPI_OC_TINY_H
2#define _LINUX_SPI_SPI_OC_TINY_H
3
4/**
5 * struct tiny_spi_platform_data - platform data of the OpenCores tiny SPI
6 * @freq: input clock freq to the core.
7 * @baudwidth: baud rate divider width of the core.
8 * @gpio_cs_count: number of gpio pins used for chipselect.
9 * @gpio_cs: array of gpio pins used for chipselect.
10 *
11 * freq and baudwidth are used only if the divider is programmable.
12 */
13struct tiny_spi_platform_data {
14 unsigned int freq;
15 unsigned int baudwidth;
16 unsigned int gpio_cs_count;
17 int *gpio_cs;
18};
19
20#endif /* _LINUX_SPI_SPI_OC_TINY_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 03:08:13 -0500