4 files changed, 62 insertions, 48 deletions

diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 74c5a8e467e8..b0972c4ce81c 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -294,59 +294,52 @@ void __init acpi_nvs_nosave_s3(void);
 #endif /* CONFIG_PM_SLEEP */
 
 struct acpi_osc_context {
-        char *uuid_str; /* uuid string */
+        char *uuid_str;                 /* UUID string */
         int rev;
-        struct acpi_buffer cap; /* arg2/arg3 */
-        struct acpi_buffer ret; /* free by caller if success */
+        struct acpi_buffer cap;         /* list of DWORD capabilities */
+        struct acpi_buffer ret;         /* free by caller if success */
 };
 
-#define OSC_QUERY_TYPE                  0
-#define OSC_SUPPORT_TYPE                1
-#define OSC_CONTROL_TYPE                2
-
-/* _OSC DW0 Definition */
-#define OSC_QUERY_ENABLE                1
-#define OSC_REQUEST_ERROR               2
-#define OSC_INVALID_UUID_ERROR          4
-#define OSC_INVALID_REVISION_ERROR      8
-#define OSC_CAPABILITIES_MASK_ERROR     16
-
 acpi_status acpi_str_to_uuid(char *str, u8 *uuid);
 acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
 
-/* platform-wide _OSC bits */
-#define OSC_SB_PAD_SUPPORT              1
-#define OSC_SB_PPC_OST_SUPPORT          2
-#define OSC_SB_PR3_SUPPORT              4
-#define OSC_SB_HOTPLUG_OST_SUPPORT      8
-#define OSC_SB_APEI_SUPPORT             16
+/* Indexes into _OSC Capabilities Buffer (DWORDs 2 & 3 are device-specific) */
+#define OSC_QUERY_DWORD                         0       /* DWORD 1 */
+#define OSC_SUPPORT_DWORD                       1       /* DWORD 2 */
+#define OSC_CONTROL_DWORD                       2       /* DWORD 3 */
+
+/* _OSC Capabilities DWORD 1: Query/Control and Error Returns (generic) */
+#define OSC_QUERY_ENABLE                        0x00000001  /* input */
+#define OSC_REQUEST_ERROR                       0x00000002  /* return */
+#define OSC_INVALID_UUID_ERROR                  0x00000004  /* return */
+#define OSC_INVALID_REVISION_ERROR              0x00000008  /* return */
+#define OSC_CAPABILITIES_MASK_ERROR             0x00000010  /* return */
+
+/* Platform-Wide Capabilities _OSC: Capabilities DWORD 2: Support Field */
+#define OSC_SB_PAD_SUPPORT                      0x00000001
+#define OSC_SB_PPC_OST_SUPPORT                  0x00000002
+#define OSC_SB_PR3_SUPPORT                      0x00000004
+#define OSC_SB_HOTPLUG_OST_SUPPORT              0x00000008
+#define OSC_SB_APEI_SUPPORT                     0x00000010
+#define OSC_SB_CPC_SUPPORT                      0x00000020
 
 extern bool osc_sb_apei_support_acked;
 
-/* PCI defined _OSC bits */
-/* _OSC DW1 Definition (OS Support Fields) */
-#define OSC_EXT_PCI_CONFIG_SUPPORT              1
-#define OSC_ACTIVE_STATE_PWR_SUPPORT            2
-#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT        4
-#define OSC_PCI_SEGMENT_GROUPS_SUPPORT          8
-#define OSC_MSI_SUPPORT                         16
-#define OSC_PCI_SUPPORT_MASKS                   0x1f
-
-/* _OSC DW1 Definition (OS Control Fields) */
-#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL       1
-#define OSC_SHPC_NATIVE_HP_CONTROL              2
-#define OSC_PCI_EXPRESS_PME_CONTROL             4
-#define OSC_PCI_EXPRESS_AER_CONTROL             8
-#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL   16
-
-#define OSC_PCI_CONTROL_MASKS   (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL |    \
-                                OSC_SHPC_NATIVE_HP_CONTROL |            \
-                                OSC_PCI_EXPRESS_PME_CONTROL |           \
-                                OSC_PCI_EXPRESS_AER_CONTROL |           \
-                                OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL)
-
-#define OSC_PCI_NATIVE_HOTPLUG  (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL |    \
-                                OSC_SHPC_NATIVE_HP_CONTROL)
+/* PCI Host Bridge _OSC: Capabilities DWORD 2: Support Field */
+#define OSC_PCI_EXT_CONFIG_SUPPORT              0x00000001
+#define OSC_PCI_ASPM_SUPPORT                    0x00000002
+#define OSC_PCI_CLOCK_PM_SUPPORT                0x00000004
+#define OSC_PCI_SEGMENT_GROUPS_SUPPORT          0x00000008
+#define OSC_PCI_MSI_SUPPORT                     0x00000010
+#define OSC_PCI_SUPPORT_MASKS                   0x0000001f
+
+/* PCI Host Bridge _OSC: Capabilities DWORD 3: Control Field */
+#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL       0x00000001
+#define OSC_PCI_SHPC_NATIVE_HP_CONTROL          0x00000002
+#define OSC_PCI_EXPRESS_PME_CONTROL             0x00000004
+#define OSC_PCI_EXPRESS_AER_CONTROL             0x00000008
+#define OSC_PCI_EXPRESS_CAPABILITY_CONTROL      0x00000010
+#define OSC_PCI_CONTROL_MASKS                   0x0000001f
 
 extern acpi_status acpi_pci_osc_control_set(acpi_handle handle,
                                              u32 *mask, u32 req);
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index 7086b2248c8f..b6d36b38b99c 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -241,6 +241,12 @@
 
 #define IMX6Q_GPR5_L2_CLK_STOP                  BIT(8)
 
+#define IMX6Q_GPR8_TX_SWING_LOW                 (0x7f << 25)
+#define IMX6Q_GPR8_TX_SWING_FULL                (0x7f << 18)
+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB           (0x3f << 12)
+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB         (0x3f << 6)
+#define IMX6Q_GPR8_TX_DEEMPH_GEN1               (0x3f << 0)
+
 #define IMX6Q_GPR9_TZASC2_BYP                   BIT(1)
 #define IMX6Q_GPR9_TZASC1_BYP                   BIT(0)
 
@@ -273,7 +279,9 @@
 #define IMX6Q_GPR12_ARMP_AHB_CLK_EN             BIT(26)
 #define IMX6Q_GPR12_ARMP_ATB_CLK_EN             BIT(25)
 #define IMX6Q_GPR12_ARMP_APB_CLK_EN             BIT(24)
+#define IMX6Q_GPR12_DEVICE_TYPE                 (0xf << 12)
 #define IMX6Q_GPR12_PCIE_CTL_2                  BIT(10)
+#define IMX6Q_GPR12_LOS_LEVEL                   (0x1f << 4)
 
 #define IMX6Q_GPR13_SDMA_STOP_REQ               BIT(30)
 #define IMX6Q_GPR13_CAN2_STOP_REQ               BIT(29)
diff --git a/include/linux/msi.h b/include/linux/msi.h
index b17ead818aec..87cce50bd121 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -64,6 +64,8 @@ void arch_restore_msi_irqs(struct pci_dev *dev, int irq);
 
 void default_teardown_msi_irqs(struct pci_dev *dev);
 void default_restore_msi_irqs(struct pci_dev *dev, int irq);
+u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
+u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag);
 
 struct msi_chip {
         struct module *owner;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index da172f956ad6..835ec7bf6c05 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -330,8 +330,6 @@ struct pci_dev {
         unsigned int    msix_enabled:1;
         unsigned int    ari_enabled:1;  /* ARI forwarding */
         unsigned int    is_managed:1;
-        unsigned int    is_pcie:1;      /* Obsolete. Will be removed.
-                                           Use pci_is_pcie() instead */
         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
         unsigned int    state_saved:1;
         unsigned int    is_physfn:1;
@@ -472,12 +470,25 @@ struct pci_bus {
 /*
  * Returns true if the pci bus is root (behind host-pci bridge),
  * false otherwise
+ *
+ * Some code assumes that "bus->self == NULL" means that bus is a root bus.
+ * This is incorrect because "virtual" buses added for SR-IOV (via
+ * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
  */
 static inline bool pci_is_root_bus(struct pci_bus *pbus)
 {
         return !(pbus->parent);
 }
 
+static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
+{
+        dev = pci_physfn(dev);
+        if (pci_is_root_bus(dev->bus))
+                return NULL;
+
+        return dev->bus->self;
+}
+
 #ifdef CONFIG_PCI_MSI
 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
 {
@@ -1749,11 +1760,11 @@ static inline int pci_pcie_cap(struct pci_dev *dev)
  * pci_is_pcie - check if the PCI device is PCI Express capable
  * @dev: PCI device
  *
- * Retrun true if the PCI device is PCI Express capable, false otherwise.
+ * Returns: true if the PCI device is PCI Express capable, false otherwise.
  */
 static inline bool pci_is_pcie(struct pci_dev *dev)
 {
-        return !!pci_pcie_cap(dev);
+        return pci_pcie_cap(dev);
 }
 
 /**