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-rw-r--r--include/linux/Kbuild1
-rw-r--r--include/linux/v4l2-dv-timings.h816
2 files changed, 817 insertions, 0 deletions
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 3c9b616c834a..d38b3a8fb380 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -382,6 +382,7 @@ header-y += usbdevice_fs.h
382header-y += utime.h 382header-y += utime.h
383header-y += utsname.h 383header-y += utsname.h
384header-y += uvcvideo.h 384header-y += uvcvideo.h
385header-y += v4l2-dv-timings.h
385header-y += v4l2-mediabus.h 386header-y += v4l2-mediabus.h
386header-y += v4l2-subdev.h 387header-y += v4l2-subdev.h
387header-y += veth.h 388header-y += veth.h
diff --git a/include/linux/v4l2-dv-timings.h b/include/linux/v4l2-dv-timings.h
new file mode 100644
index 000000000000..9ef8172e5ed0
--- /dev/null
+++ b/include/linux/v4l2-dv-timings.h
@@ -0,0 +1,816 @@
1/*
2 * V4L2 DV timings header.
3 *
4 * Copyright (C) 2012 Hans Verkuil <hans.verkuil@cisco.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 */
20
21#ifndef _V4L2_DV_TIMINGS_H
22#define _V4L2_DV_TIMINGS_H
23
24#if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
25/* Sadly gcc versions older than 4.6 have a bug in how they initialize
26 anonymous unions where they require additional curly brackets.
27 This violates the C1x standard. This workaround adds the curly brackets
28 if needed. */
29#define V4L2_INIT_BT_TIMINGS(_width, args...) \
30 { .bt = { _width , ## args } }
31#else
32#define V4L2_INIT_BT_TIMINGS(_width, args...) \
33 .bt = { _width , ## args }
34#endif
35
36/* CEA-861-E timings (i.e. standard HDTV timings) */
37
38#define V4L2_DV_BT_CEA_640X480P59_94 { \
39 .type = V4L2_DV_BT_656_1120, \
40 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
41 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
42 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
43}
44
45#define V4L2_DV_BT_CEA_720X480P59_94 { \
46 .type = V4L2_DV_BT_656_1120, \
47 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
48 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
49 V4L2_DV_BT_STD_CEA861, 0) \
50}
51
52#define V4L2_DV_BT_CEA_720X576P50 { \
53 .type = V4L2_DV_BT_656_1120, \
54 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
55 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
56 V4L2_DV_BT_STD_CEA861, 0) \
57}
58
59#define V4L2_DV_BT_CEA_1280X720P24 { \
60 .type = V4L2_DV_BT_656_1120, \
61 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
62 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
63 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
64 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
65 V4L2_DV_FL_CAN_REDUCE_FPS) \
66}
67
68#define V4L2_DV_BT_CEA_1280X720P25 { \
69 .type = V4L2_DV_BT_656_1120, \
70 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
71 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
72 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
73 V4L2_DV_BT_STD_CEA861, 0) \
74}
75
76#define V4L2_DV_BT_CEA_1280X720P30 { \
77 .type = V4L2_DV_BT_656_1120, \
78 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
79 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
80 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
81 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
82}
83
84#define V4L2_DV_BT_CEA_1280X720P50 { \
85 .type = V4L2_DV_BT_656_1120, \
86 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
87 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
88 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
89 V4L2_DV_BT_STD_CEA861, 0) \
90}
91
92#define V4L2_DV_BT_CEA_1280X720P60 { \
93 .type = V4L2_DV_BT_656_1120, \
94 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
95 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
96 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
97 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
98}
99
100#define V4L2_DV_BT_CEA_1920X1080P24 { \
101 .type = V4L2_DV_BT_656_1120, \
102 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
103 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
104 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
105 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
106}
107
108#define V4L2_DV_BT_CEA_1920X1080P25 { \
109 .type = V4L2_DV_BT_656_1120, \
110 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
111 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
112 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
113 V4L2_DV_BT_STD_CEA861, 0) \
114}
115
116#define V4L2_DV_BT_CEA_1920X1080P30 { \
117 .type = V4L2_DV_BT_656_1120, \
118 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
119 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
120 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
121 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
122}
123
124#define V4L2_DV_BT_CEA_1920X1080I50 { \
125 .type = V4L2_DV_BT_656_1120, \
126 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
127 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
128 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
129 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
130}
131
132#define V4L2_DV_BT_CEA_1920X1080P50 { \
133 .type = V4L2_DV_BT_656_1120, \
134 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
135 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
136 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
137 V4L2_DV_BT_STD_CEA861, 0) \
138}
139
140#define V4L2_DV_BT_CEA_1920X1080I60 { \
141 .type = V4L2_DV_BT_656_1120, \
142 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
143 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
144 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
145 V4L2_DV_BT_STD_CEA861, \
146 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
147}
148
149#define V4L2_DV_BT_CEA_1920X1080P60 { \
150 .type = V4L2_DV_BT_656_1120, \
151 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
152 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
153 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
154 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
155 V4L2_DV_FL_CAN_REDUCE_FPS) \
156}
157
158
159/* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
160
161#define V4L2_DV_BT_DMT_640X350P85 { \
162 .type = V4L2_DV_BT_656_1120, \
163 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
164 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
165 V4L2_DV_BT_STD_DMT, 0) \
166}
167
168#define V4L2_DV_BT_DMT_640X400P85 { \
169 .type = V4L2_DV_BT_656_1120, \
170 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
171 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
172 V4L2_DV_BT_STD_DMT, 0) \
173}
174
175#define V4L2_DV_BT_DMT_720X400P85 { \
176 .type = V4L2_DV_BT_656_1120, \
177 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
178 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
179 V4L2_DV_BT_STD_DMT, 0) \
180}
181
182/* VGA resolutions */