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-rw-r--r--include/linux/hil.h483
-rw-r--r--include/linux/hil_mlc.h168
-rw-r--r--include/linux/hp_sdc.h300
-rw-r--r--include/linux/input.h1
4 files changed, 952 insertions, 0 deletions
diff --git a/include/linux/hil.h b/include/linux/hil.h
new file mode 100644
index 000000000000..13352d7d0caf
--- /dev/null
+++ b/include/linux/hil.h
@@ -0,0 +1,483 @@
1#ifndef _HIL_H_
2#define _HIL_H_
3
4/*
5 * Hewlett Packard Human Interface Loop (HP-HIL) Protocol -- header.
6 *
7 * Copyright (c) 2001 Brian S. Julin
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL").
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 *
32 * References:
33 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
34 *
35 * A note of thanks to HP for providing and shipping reference materials
36 * free of charge to help in the development of HIL support for Linux.
37 *
38 */
39
40#include <asm/types.h>
41
42/* Physical constants relevant to raw loop/device timing.
43 */
44
45#define HIL_CLOCK 8MHZ
46#define HIL_EK1_CLOCK 30HZ
47#define HIL_EK2_CLOCK 60HZ
48
49#define HIL_TIMEOUT_DEV 5 /* ms */
50#define HIL_TIMEOUT_DEVS 10 /* ms */
51#define HIL_TIMEOUT_NORESP 10 /* ms */
52#define HIL_TIMEOUT_DEVS_DATA 16 /* ms */
53#define HIL_TIMEOUT_SELFTEST 200 /* ms */
54
55
56/* Actual wire line coding. These will only be useful if someone is
57 * implementing a software MLC to run HIL devices on a non-parisc machine.
58 */
59
60#define HIL_WIRE_PACKET_LEN 15
61enum hil_wire_bitpos {
62 HIL_WIRE_START = 0,
63 HIL_WIRE_ADDR2,
64 HIL_WIRE_ADDR1,
65 HIL_WIRE_ADDR0,
66 HIL_WIRE_COMMAND,
67 HIL_WIRE_DATA7,
68 HIL_WIRE_DATA6,
69 HIL_WIRE_DATA5,
70 HIL_WIRE_DATA4,
71 HIL_WIRE_DATA3,
72 HIL_WIRE_DATA2,
73 HIL_WIRE_DATA1,
74 HIL_WIRE_DATA0,
75 HIL_WIRE_PARITY,
76 HIL_WIRE_STOP
77};
78
79/* HP documentation uses these bit positions to refer to commands;
80 * we will call these "packets".
81 */
82enum hil_pkt_bitpos {
83 HIL_PKT_CMD = 0x00000800,
84 HIL_PKT_ADDR2 = 0x00000400,
85 HIL_PKT_ADDR1 = 0x00000200,
86 HIL_PKT_ADDR0 = 0x00000100,
87 HIL_PKT_ADDR_MASK = 0x00000700,
88 HIL_PKT_ADDR_SHIFT = 8,
89 HIL_PKT_DATA7 = 0x00000080,
90 HIL_PKT_DATA6 = 0x00000040,
91 HIL_PKT_DATA5 = 0x00000020,
92 HIL_PKT_DATA4 = 0x00000010,
93 HIL_PKT_DATA3 = 0x00000008,
94 HIL_PKT_DATA2 = 0x00000004,
95 HIL_PKT_DATA1 = 0x00000002,
96 HIL_PKT_DATA0 = 0x00000001,
97 HIL_PKT_DATA_MASK = 0x000000FF,
98 HIL_PKT_DATA_SHIFT = 0
99};
100
101/* The HIL MLC also has several error/status/control bits. We extend the
102 * "packet" to include these when direct access to the MLC is available,
103 * or emulate them in cases where they are not available.
104 *
105 * This way the device driver knows that the underlying MLC driver
106 * has had to deal with loop errors.
107 */
108enum hil_error_bitpos {
109 HIL_ERR_OB = 0x00000800, /* MLC is busy sending an auto-poll,
110 or we have filled up the output
111 buffer and must wait. */
112 HIL_ERR_INT = 0x00010000, /* A normal interrupt has occurred. */
113 HIL_ERR_NMI = 0x00020000, /* An NMI has occurred. */
114 HIL_ERR_LERR = 0x00040000, /* A poll didn't come back. */
115 HIL_ERR_PERR = 0x01000000, /* There was a Parity Error. */
116 HIL_ERR_FERR = 0x02000000, /* There was a Framing Error. */
117 HIL_ERR_FOF = 0x04000000 /* Input FIFO Overflowed. */
118};
119
120enum hil_control_bitpos {
121 HIL_CTRL_TEST = 0x00010000,
122 HIL_CTRL_IPF = 0x00040000,
123 HIL_CTRL_APE = 0x02000000
124};
125
126/* Bits 30,31 are unused, we use them to control write behavior. */
127#define HIL_DO_ALTER_CTRL 0x40000000 /* Write MSW of packet to control
128 before writing LSW to loop */
129#define HIL_CTRL_ONLY 0xc0000000 /* *Only* alter the control registers */
130
131/* This gives us a 32-bit "packet"
132 */
133typedef u32 hil_packet;
134
135
136/* HIL Loop commands
137 */
138enum hil_command {
139 HIL_CMD_IFC = 0x00, /* Interface Clear */
140 HIL_CMD_EPT = 0x01, /* Enter Pass-Thru Mode */
141 HIL_CMD_ELB = 0x02, /* Enter Loop-Back Mode */
142 HIL_CMD_IDD = 0x03, /* Identify and Describe */
143 HIL_CMD_DSR = 0x04, /* Device Soft Reset */
144 HIL_CMD_PST = 0x05, /* Perform Self Test */
145 HIL_CMD_RRG = 0x06, /* Read Register */
146 HIL_CMD_WRG = 0x07, /* Write Register */
147 HIL_CMD_ACF = 0x08, /* Auto Configure */
148 HIL_CMDID_ACF = 0x07, /* Auto Configure bits with incremented ID */
149 HIL_CMD_POL = 0x10, /* Poll */
150 HIL_CMDCT_POL = 0x0f, /* Poll command bits with item count */
151 HIL_CMD_RPL = 0x20, /* RePoll */
152 HIL_CMDCT_RPL = 0x0f, /* RePoll command bits with item count */
153 HIL_CMD_RNM = 0x30, /* Report Name */
154 HIL_CMD_RST = 0x31, /* Report Status */
155 HIL_CMD_EXD = 0x32, /* Extended Describe */
156 HIL_CMD_RSC = 0x33, /* Report Security Code */
157
158 /* 0x34 to 0x3c reserved for future use */
159
160 HIL_CMD_DKA = 0x3d, /* Disable Keyswitch Autorepeat */
161 HIL_CMD_EK1 = 0x3e, /* Enable Keyswitch Autorepeat 1 */
162 HIL_CMD_EK2 = 0x3f, /* Enable Keyswitch Autorepeat 2 */
163 HIL_CMD_PR1 = 0x40, /* Prompt1 */
164 HIL_CMD_PR2 = 0x41, /* Prompt2 */
165 HIL_CMD_PR3 = 0x42, /* Prompt3 */
166 HIL_CMD_PR4 = 0x43, /* Prompt4 */
167 HIL_CMD_PR5 = 0x44, /* Prompt5 */
168 HIL_CMD_PR6 = 0x45, /* Prompt6 */
169 HIL_CMD_PR7 = 0x46, /* Prompt7 */
170 HIL_CMD_PRM = 0x47, /* Prompt (General Purpose) */
171 HIL_CMD_AK1 = 0x48, /* Acknowlege1 */
172 HIL_CMD_AK2 = 0x49, /* Acknowlege2 */
173 HIL_CMD_AK3 = 0x4a, /* Acknowlege3 */
174 HIL_CMD_AK4 = 0x4b, /* Acknowlege4 */
175 HIL_CMD_AK5 = 0x4c, /* Acknowlege5 */
176 HIL_CMD_AK6 = 0x4d, /* Acknowlege6 */
177 HIL_CMD_AK7 = 0x4e, /* Acknowlege7 */
178 HIL_CMD_ACK = 0x4f, /* Acknowlege (General Purpose) */
179
180 /* 0x50 to 0x78 reserved for future use */
181 /* 0x80 to 0xEF device-specific commands */
182 /* 0xf0 to 0xf9 reserved for future use */
183
184 HIL_CMD_RIO = 0xfa, /* Register I/O Error */
185 HIL_CMD_SHR = 0xfb, /* System Hard Reset */
186 HIL_CMD_TER = 0xfc, /* Transmission Error */
187 HIL_CMD_CAE = 0xfd, /* Configuration Address Error */
188 HIL_CMD_DHR = 0xfe, /* Device Hard Reset */
189
190 /* 0xff is prohibited from use. */
191};
192
193
194/*
195 * Response "records" to HIL commands
196 */
197
198/* Device ID byte
199 */
200#define HIL_IDD_DID_TYPE_MASK 0xe0 /* Primary type bits */
201#define HIL_IDD_DID_TYPE_KB_INTEGRAL 0xa0 /* Integral keyboard */
202#define HIL_IDD_DID_TYPE_KB_ITF 0xc0 /* ITD keyboard */
203#define HIL_IDD_DID_TYPE_KB_RSVD 0xe0 /* Reserved keyboard type */
204#define HIL_IDD_DID_TYPE_KB_LANG_MASK 0x1f /* Keyboard locale bits */
205#define HIL_IDD_DID_KBLANG_USE_ESD 0x00 /* Use ESD Locale instead */
206#define HIL_IDD_DID_TYPE_ABS 0x80 /* Absolute Positioners */
207#define HIL_IDD_DID_ABS_RSVD1_MASK 0xf8 /* Reserved */
208#define HIL_IDD_DID_ABS_RSVD1 0x98
209#define HIL_IDD_DID_ABS_TABLET_MASK 0xf8 /* Tablets and digitizers */
210#define HIL_IDD_DID_ABS_TABLET 0x90
211#define HIL_IDD_DID_ABS_TSCREEN_MASK 0xfc /* Touch screens */
212#define HIL_IDD_DID_ABS_TSCREEN 0x8c
213#define HIL_IDD_DID_ABS_RSVD2_MASK 0xfc /* Reserved */
214#define HIL_IDD_DID_ABS_RSVD2 0x88
215#define HIL_IDD_DID_ABS_RSVD3_MASK 0xfc /* Reserved */
216#define HIL_IDD_DID_ABS_RSVD3 0x80
217#define HIL_IDD_DID_TYPE_REL 0x60 /* Relative Positioners */
218#define HIL_IDD_DID_REL_RSVD1_MASK 0xf0 /* Reserved */
219#define HIL_IDD_DID_REL_RSVD1 0x70
220#define HIL_IDD_DID_REL_RSVD2_MASK 0xfc /* Reserved */
221#define HIL_IDD_DID_REL_RSVD2 0x6c
222#define HIL_IDD_DID_REL_MOUSE_MASK 0xfc /* Mouse */
223#define HIL_IDD_DID_REL_MOUSE 0x68
224#define HIL_IDD_DID_REL_QUAD_MASK 0xf8 /* Other Quadrature Devices */
225#define HIL_IDD_DID_REL_QUAD 0x60
226#define HIL_IDD_DID_TYPE_CHAR 0x40 /* Character Entry */
227#define HIL_IDD_DID_CHAR_BARCODE_MASK 0xfc /* Barcode Reader */
228#define HIL_IDD_DID_CHAR_BARCODE 0x5c
229#define HIL_IDD_DID_CHAR_RSVD1_MASK 0xfc /* Reserved */
230#define HIL_IDD_DID_CHAR_RSVD1 0x58
231#define HIL_IDD_DID_CHAR_RSVD2_MASK 0xf8 /* Reserved */
232#define HIL_IDD_DID_CHAR_RSVD2 0x50
233#define HIL_IDD_DID_CHAR_RSVD3_MASK 0xf0 /* Reserved */
234#define HIL_IDD_DID_CHAR_RSVD3 0x40
235#define HIL_IDD_DID_TYPE_OTHER 0x20 /* Miscellaneous */
236#define HIL_IDD_DID_OTHER_RSVD1_MASK 0xf0 /* Reserved */
237#define HIL_IDD_DID_OTHER_RSVD1 0x30
238#define HIL_IDD_DID_OTHER_BARCODE_MASK 0xfc /* Tone Generator */
239#define HIL_IDD_DID_OTHER_BARCODE 0x2c
240#define HIL_IDD_DID_OTHER_RSVD2_MASK 0xfc /* Reserved */
241#define HIL_IDD_DID_OTHER_RSVD2 0x28
242#define HIL_IDD_DID_OTHER_RSVD3_MASK 0xf8 /* Reserved */
243#define HIL_IDD_DID_OTHER_RSVD3 0x20
244#define HIL_IDD_DID_TYPE_KEYPAD 0x00 /* Vectra Keyboard */
245
246/* IDD record header
247 */
248#define HIL_IDD_HEADER_AXSET_MASK 0x03 /* Number of axis in a set */
249#define HIL_IDD_HEADER_RSC 0x04 /* Supports RSC command */
250#define HIL_IDD_HEADER_EXD 0x08 /* Supports EXD command */
251#define HIL_IDD_HEADER_IOD 0x10 /* IOD byte to follow */
252#define HIL_IDD_HEADER_16BIT 0x20 /* 16 (vs. 8) bit resolution */
253#define HIL_IDD_HEADER_ABS 0x40 /* Reports Absolute Position */
254#define HIL_IDD_HEADER_2X_AXIS 0x80 /* Two sets of 1-3 axis */
255
256/* I/O Descriptor
257 */
258#define HIL_IDD_IOD_NBUTTON_MASK 0x07 /* Number of buttons */
259#define HIL_IDD_IOD_PROXIMITY 0x08 /* Proximity in/out events */
260#define HIL_IDD_IOD_PROMPT_MASK 0x70 /* Number of prompts/acks */
261#define HIL_IDD_IOD_PROMPT_SHIFT 4
262#define HIL_IDD_IOD_PROMPT 0x80 /* Generic prompt/ack */
263
264#define HIL_IDD_NUM_AXES_PER_SET(header_packet) \
265((header_packet) & HIL_IDD_HEADER_AXSET_MASK)
266
267#define HIL_IDD_NUM_AXSETS(header_packet) \
268(2 - !((header_packet) & HIL_IDD_HEADER_2X_AXIS))
269
270#define HIL_IDD_LEN(header_packet) \
271((4 - !(header_packet & HIL_IDD_HEADER_IOD) - \
272 2 * !(HIL_IDD_NUM_AXES_PER_SET(header_packet))) + \
273 2 * HIL_IDD_NUM_AXES_PER_SET(header_packet) * \
274 !!((header_packet) & HIL_IDD_HEADER_ABS))
275
276/* The following HIL_IDD_* macros assume you have an array of
277 * packets and/or unpacked 8-bit data in the order that they
278 * were received.
279 */
280
281#define HIL_IDD_AXIS_COUNTS_PER_M(header_ptr) \
282(!(HIL_IDD_NUM_AXSETS(*(header_ptr))) ? -1 : \
283(((*(header_ptr + 1) & HIL_PKT_DATA_MASK) + \
284 ((*(header_ptr + 2) & HIL_PKT_DATA_MASK)) << 8) \
285* ((*(header_ptr) & HIL_IDD_HEADER_16BIT) ? 100 : 1)))
286
287#define HIL_IDD_AXIS_MAX(header_ptr, __axnum) \
288((!(*(header_ptr) & HIL_IDD_HEADER_ABS) || \
289 (HIL_IDD_NUM_AXES_PER_SET(*(header_ptr)) <= __axnum)) ? 0 : \
290 ((HIL_PKT_DATA_MASK & *((header_ptr) + 3 + 2 * __axnum)) + \
291 ((HIL_PKT_DATA_MASK & *((header_ptr) + 4 + 2 * __axnum)) << 8)))
292
293#define HIL_IDD_IOD(header_ptr) \
294(*(header_ptr + HIL_IDD_LEN((*header_ptr)) - 1))
295
296#define HIL_IDD_HAS_GEN_PROMPT(header_ptr) \
297((*header_ptr & HIL_IDD_HEADER_IOD) && \
298 (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_PROMPT))
299
300#define HIL_IDD_HAS_GEN_PROXIMITY(header_ptr) \
301((*header_ptr & HIL_IDD_HEADER_IOD) && \
302 (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_PROXIMITY))
303
304#define HIL_IDD_NUM_BUTTONS(header_ptr) \
305((*header_ptr & HIL_IDD_HEADER_IOD) ? \
306 (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_NBUTTON_MASK) : 0)
307
308#define HIL_IDD_NUM_PROMPTS(header_ptr) \
309((*header_ptr & HIL_IDD_HEADER_IOD) ? \
310 ((HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_NPROMPT_MASK) \
311 >> HIL_IDD_IOD_PROMPT_SHIFT) : 0)
312
313/* The response to HIL EXD commands -- the "extended describe record" */
314#define HIL_EXD_HEADER_WRG 0x03 /* Supports type2 WRG */
315#define HIL_EXD_HEADER_WRG_TYPE1 0x01 /* Supports type1 WRG */
316#define HIL_EXD_HEADER_WRG_TYPE2 0x02 /* Supports type2 WRG */
317#define HIL_EXD_HEADER_RRG 0x04 /* Supports RRG command */
318#define HIL_EXD_HEADER_RNM 0x10 /* Supports RNM command */
319#define HIL_EXD_HEADER_RST 0x20 /* Supports RST command */
320#define HIL_EXD_HEADER_LOCALE 0x40 /* Contains locale code */
321
322#define HIL_EXD_NUM_RRG(header_ptr) \
323((*header_ptr & HIL_EXD_HEADER_RRG) ? \
324 (*(header_ptr + 1) & HIL_PKT_DATA_MASK) : 0)
325
326#define HIL_EXD_NUM_WWG(header_ptr) \
327((*header_ptr & HIL_EXD_HEADER_WRG) ? \
328 (*(header_ptr + 2 - !(*header_ptr & HIL_EXD_HEADER_RRG)) & \
329 HIL_PKT_DATA_MASK) : 0)
330
331#define HIL_EXD_LEN(header_ptr) \
332(!!(*header_ptr & HIL_EXD_HEADER_RRG) + \
333 !!(*header_ptr & HIL_EXD_HEADER_WRG) + \
334 !!(*header_ptr & HIL_EXD_HEADER_LOCALE) + \
335 2 * !!(*header_ptr & HIL_EXD_HEADER_WRG_TYPE2) + 1)
336
337#define HIL_EXD_LOCALE(header_ptr) \
338(!(*header_ptr & HIL_EXD_HEADER_LOCALE) ? -1 : \
339 (*(header_ptr + HIL_EXD_LEN(header_ptr) - 1) & HIL_PKT_DATA_MASK))
340
341#define HIL_EXD_WRG_TYPE2_LEN(header_ptr) \
342(!(*header_ptr & HIL_EXD_HEADER_WRG_TYPE2) ? -1 : \
343 (*(header_ptr + HIL_EXD_LEN(header_ptr) - 2 - \
344 !!(*header_ptr & HIL_EXD_HEADER_LOCALE)) & HIL_PKT_DATA_MASK) + \
345 ((*(header_ptr + HIL_EXD_LEN(header_ptr) - 1 - \
346 !!(*header_ptr & HIL_EXD_HEADER_LOCALE)) & HIL_PKT_DATA_MASK) << 8))
347
348/* Device locale codes. */
349
350/* Last defined locale code. Everything above this is "Reserved",
351 and note that this same table applies to the Device ID Byte where
352 keyboards may have a nationality code which is only 5 bits. */
353#define HIL_LOCALE_MAX 0x1f
354
355/* Map to hopefully useful strings. I was trying to make these look
356 like locale.aliases strings do; maybe that isn't the right table to
357 emulate. In either case, I didn't have much to work on. */
358#define HIL_LOCALE_MAP \
359"", /* 0x00 Reserved */ \
360"", /* 0x01 Reserved */ \
361"", /* 0x02 Reserved */ \
362"swiss.french", /* 0x03 Swiss/French */ \
363"portuguese", /* 0x04 Portuguese */ \
364"arabic", /* 0x05 Arabic */ \
365"hebrew", /* 0x06 Hebrew */ \
366"english.canadian", /* 0x07 Canadian English */ \
367"turkish", /* 0x08 Turkish */ \
368"greek", /* 0x09 Greek */ \
369"thai", /* 0x0a Thai (Thailand) */ \
370"italian", /* 0x0b Italian */ \
371"korean", /* 0x0c Hangul (Korea) */ \
372"dutch", /* 0x0d Dutch */ \
373"swedish", /* 0x0e Swedish */ \
374"german", /* 0x0f German */ \
375"chinese", /* 0x10 Chinese-PRC */ \
376"chinese", /* 0x11 Chinese-ROC */ \
377"swiss.french", /* 0x12 Swiss/French II */ \
378"spanish", /* 0x13 Spanish */ \
379"swiss.german", /* 0x14 Swiss/German II */ \
380"flemish", /* 0x15 Belgian (Flemish) */ \
381"finnish", /* 0x16 Finnish */ \
382"english.uk", /* 0x17 United Kingdom */ \
383"french.canadian", /* 0x18 French/Canadian */ \
384"swiss.german", /* 0x19 Swiss/German */ \
385"norwegian", /* 0x1a Norwegian */ \
386"french", /* 0x1b French */ \
387"danish", /* 0x1c Danish */ \
388"japanese", /* 0x1d Katakana */ \
389"spanish", /* 0x1e Latin American/Spanish*/\
390"english.us" /* 0x1f United States */ \
391
392
393/* HIL keycodes */
394#define HIL_KEYCODES_SET1_TBLSIZE 128
395#define HIL_KEYCODES_SET1 \
396 KEY_5, KEY_RESERVED, KEY_RIGHTALT, KEY_LEFTALT, \
397 KEY_RIGHTSHIFT, KEY_LEFTSHIFT, KEY_LEFTCTRL, KEY_SYSRQ, \
398 KEY_KP4, KEY_KP8, KEY_KP5, KEY_KP9, \
399 KEY_KP6, KEY_KP7, KEY_KPCOMMA, KEY_KPENTER, \
400 KEY_KP1, KEY_KPSLASH, KEY_KP2, KEY_KPPLUS, \
401 KEY_KP3, KEY_KPASTERISK, KEY_KP0, KEY_KPMINUS, \
402 KEY_B, KEY_V, KEY_C, KEY_X, \
403 KEY_Z, KEY_RESERVED, KEY_RESERVED, KEY_ESC, \
404 KEY_6, KEY_F10, KEY_3, KEY_F11, \
405 KEY_KPDOT, KEY_F9, KEY_TAB /*KP*/, KEY_F12, \
406 KEY_H, KEY_G, KEY_F, KEY_D, \
407 KEY_S, KEY_A, KEY_RESERVED, KEY_CAPSLOCK, \
408 KEY_U, KEY_Y, KEY_T, KEY_R, \
409 KEY_E, KEY_W, KEY_Q, KEY_TAB, \
410 KEY_7, KEY_6, KEY_5, KEY_4, \
411 KEY_3, KEY_2, KEY_1, KEY_GRAVE, \
412 KEY_F13, KEY_F14, KEY_F15, KEY_F16, \
413 KEY_F17, KEY_F18, KEY_F19, KEY_F20, \
414 KEY_MENU, KEY_F4, KEY_F3, KEY_F2, \
415 KEY_F1, KEY_VOLUMEUP, KEY_STOP, KEY_SENDFILE, \
416 KEY_SYSRQ, KEY_F5, KEY_F6, KEY_F7, \
417 KEY_F8, KEY_VOLUMEDOWN, KEY_DEL_EOL, KEY_DEL_EOS, \
418 KEY_8, KEY_9, KEY_0, KEY_MINUS, \
419 KEY_EQUAL, KEY_BACKSPACE, KEY_INS_LINE, KEY_DEL_LINE, \
420 KEY_I, KEY_O, KEY_P, KEY_LEFTBRACE, \
421 KEY_RIGHTBRACE, KEY_BACKSLASH, KEY_INSERT, KEY_DELETE, \
422 KEY_J, KEY_K, KEY_L, KEY_SEMICOLON, \
423 KEY_APOSTROPHE, KEY_ENTER, KEY_HOME, KEY_PAGEUP, \
424 KEY_M, KEY_COMMA, KEY_DOT, KEY_SLASH, \
425 KEY_BACKSLASH, KEY_SELECT, KEY_102ND, KEY_PAGEDOWN, \
426 KEY_N, KEY_SPACE, KEY_NEXT, KEY_RESERVED, \
427 KEY_LEFT, KEY_DOWN, KEY_UP, KEY_RIGHT
428
429
430#define HIL_KEYCODES_SET3_TBLSIZE 128
431#define HIL_KEYCODES_SET3 \
432 KEY_RESERVED, KEY_ESC, KEY_1, KEY_2, \
433 KEY_3, KEY_4, KEY_5, KEY_6, \
434 KEY_7, KEY_8, KEY_9, KEY_0, \
435 KEY_MINUS, KEY_EQUAL, KEY_BACKSPACE, KEY_TAB, \
436 KEY_Q, KEY_W, KEY_E, KEY_R, \
437 KEY_T, KEY_Y, KEY_U, KEY_I, \
438 KEY_O, KEY_P, KEY_LEFTBRACE, KEY_RIGHTBRACE, \
439 KEY_ENTER, KEY_LEFTCTRL, KEY_A, KEY_S, \
440 KEY_D, KEY_F, KEY_G, KEY_H, \
441 KEY_J, KEY_K, KEY_L, KEY_SEMICOLON, \
442 KEY_APOSTROPHE,KEY_GRAVE, KEY_LEFTSHIFT, KEY_BACKSLASH, \
443 KEY_Z, KEY_X, KEY_C, KEY_V, \
444 KEY_B, KEY_N, KEY_M, KEY_COMMA, \
445 KEY_DOT, KEY_SLASH, KEY_RIGHTSHIFT, KEY_KPASTERISK, \
446 KEY_LEFTALT, KEY_SPACE, KEY_CAPSLOCK, KEY_F1, \
447 KEY_F2, KEY_F3, KEY_F4, KEY_F5, \
448 KEY_F6, KEY_F7, KEY_F8, KEY_F9, \
449 KEY_F10, KEY_NUMLOCK, KEY_SCROLLLOCK, KEY_KP7, \
450 KEY_KP8, KEY_KP9, KEY_KPMINUS, KEY_KP4, \
451 KEY_KP5, KEY_KP6, KEY_KPPLUS, KEY_KP1, \
452 KEY_KP2, KEY_KP3, KEY_KP0, KEY_KPDOT, \
453 KEY_SYSRQ, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
454 KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
455 KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
456 KEY_UP, KEY_LEFT, KEY_DOWN, KEY_RIGHT, \
457 KEY_HOME, KEY_PAGEUP, KEY_END, KEY_PAGEDOWN, \
458 KEY_INSERT, KEY_DELETE, KEY_102ND, KEY_RESERVED, \
459 KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
460 KEY_F1, KEY_F2, KEY_F3, KEY_F4, \
461 KEY_F5, KEY_F6, KEY_F7, KEY_F8, \
462 KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
463 KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED
464
465
466/* Response to POL command, the "poll record header" */
467
468#define HIL_POL_NUM_AXES_MASK 0x03 /* Number of axis reported */
469#define HIL_POL_CTS 0x04 /* Device ready to receive data */
470#define HIL_POL_STATUS_PENDING 0x08 /* Device has status to report */
471#define HIL_POL_CHARTYPE_MASK 0x70 /* Type of character data to follow */
472#define HIL_POL_CHARTYPE_NONE 0x00 /* No character data to follow */
473#define HIL_POL_CHARTYPE_RSVD1 0x10 /* Reserved Set 1 */
474#define HIL_POL_CHARTYPE_ASCII 0x20 /* U.S. ASCII */
475#define HIL_POL_CHARTYPE_BINARY 0x30 /* Binary data */
476#define HIL_POL_CHARTYPE_SET1 0x40 /* Keycode Set 1 */
477#define HIL_POL_CHARTYPE_RSVD2 0x50 /* Reserved Set 2 */
478#define HIL_POL_CHARTYPE_SET2 0x60 /* Keycode Set 2 */
479#define HIL_POL_CHARTYPE_SET3 0x70 /* Keycode Set 3 */
480#define HIL_POL_AXIS_ALT 0x80 /* Data is from axis set 2 */
481
482
483#endif /* _HIL_H_ */
diff --git a/include/linux/hil_mlc.h b/include/linux/hil_mlc.h
new file mode 100644
index 000000000000..8df29ca48a13
--- /dev/null
+++ b/include/linux/hil_mlc.h
@@ -0,0 +1,168 @@
1/*
2 * HP Human Interface Loop Master Link Controller driver.
3 *
4 * Copyright (c) 2001 Brian S. Julin
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL").
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 *
29 * References:
30 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
31 *
32 */
33
34#include <linux/hil.h>
35#include <linux/time.h>
36#include <linux/interrupt.h>
37#include <asm/semaphore.h>
38#include <linux/serio.h>
39#include <linux/list.h>
40
41typedef struct hil_mlc hil_mlc;
42
43/* The HIL has a complicated state engine.
44 * We define the structure of nodes in the state engine here.
45 */
46enum hilse_act {
47 /* HILSE_OUT prepares to receive input if the next node
48 * is an IN or EXPECT, and then sends the given packet.
49 */
50 HILSE_OUT = 0,
51
52 /* HILSE_CTS checks if the loop is busy. */
53 HILSE_CTS,
54
55 /* HILSE_OUT_LAST sends the given command packet to
56 * the last configured/running device on the loop.
57 */
58 HILSE_OUT_LAST,
59
60 /* HILSE_OUT_DISC sends the given command packet to
61 * the next device past the last configured/running one.
62 */
63 HILSE_OUT_DISC,
64
65 /* HILSE_FUNC runs a callback function with given arguments.
66 * a positive return value causes the "ugly" branch to be taken.
67 */
68 HILSE_FUNC,
69
70 /* HILSE_IN simply expects any non-errored packet to arrive
71 * within arg usecs.
72 */
73 HILSE_IN = 0x100,
74
75 /* HILSE_EXPECT expects a particular packet to arrive
76 * within arg usecs, any other packet is considered an error.
77 */
78 HILSE_EXPECT,
79
80 /* HILSE_EXPECT_LAST as above but dev field should be last
81 * discovered/operational device.
82 */
83 HILSE_EXPECT_LAST,
84
85 /* HILSE_EXPECT_LAST as above but dev field should be first
86 * undiscovered/inoperational device.
87 */
88 HILSE_EXPECT_DISC
89};
90
91typedef int (hilse_func) (hil_mlc *mlc, int arg);
92struct hilse_node {
93 enum hilse_act act; /* How to process this node */
94 union {
95 hilse_func *func; /* Function to call if HILSE_FUNC */
96 hil_packet packet; /* Packet to send or to compare */
97 } object;
98 int arg; /* Timeout in usec or parm for func */
99 int good; /* Node to jump to on success */
100 int bad; /* Node to jump to on error */
101 int ugly; /* Node to jump to on timeout */
102};
103
104/* Methods for back-end drivers, e.g. hp_sdc_mlc */
105typedef int (hil_mlc_cts) (hil_mlc *mlc);
106typedef void (hil_mlc_out) (hil_mlc *mlc);
107typedef int (hil_mlc_in) (hil_mlc *mlc, suseconds_t timeout);
108
109struct hil_mlc_devinfo {
110 uint8_t idd[16]; /* Device ID Byte and Describe Record */
111 uint8_t rsc[16]; /* Security Code Header and Record */
112 uint8_t exd[16]; /* Extended Describe Record */
113 uint8_t rnm[16]; /* Device name as returned by RNM command */
114};
115
116struct hil_mlc_serio_map {
117 hil_mlc *mlc;
118 int di_revmap;
119 int didx;
120};
121
122/* How many (possibly old/detached) devices the we try to keep track of */
123#define HIL_MLC_DEVMEM 16
124
125struct hil_mlc {
126 struct list_head list; /* hil_mlc is organized as linked list */
127
128 rwlock_t lock;
129
130 void *priv; /* Data specific to a particular type of MLC */
131
132 int seidx; /* Current node in state engine */
133 int istarted, ostarted;
134
135 hil_mlc_cts *cts;
136 struct semaphore csem; /* Raised when loop idle */
137
138 hil_mlc_out *out;
139 struct semaphore osem; /* Raised when outpacket dispatched */
140 hil_packet opacket;
141
142 hil_mlc_in *in;
143 struct semaphore isem; /* Raised when a packet arrives */
144 hil_packet ipacket[16];
145 hil_packet imatch;
146 int icount;
147 struct timeval instart;
148 suseconds_t intimeout;
149
150 int ddi; /* Last operational device id */
151 int lcv; /* LCV to throttle loops */
152 struct timeval lcv_tv; /* Time loop was started */
153
154 int di_map[7]; /* Maps below items to live devs */
155 struct hil_mlc_devinfo di[HIL_MLC_DEVMEM];
156 struct serio *serio[HIL_MLC_DEVMEM];
157 struct hil_mlc_serio_map serio_map[HIL_MLC_DEVMEM];
158 hil_packet serio_opacket[HIL_MLC_DEVMEM];
159 int serio_oidx[HIL_MLC_DEVMEM];
160 struct hil_mlc_devinfo di_scratch; /* Temporary area */
161
162 int opercnt;
163
164 struct tasklet_struct *tasklet;
165};
166
167int hil_mlc_register(hil_mlc *mlc);
168int hil_mlc_unregister(hil_mlc *mlc);
diff --git a/include/linux/hp_sdc.h b/include/linux/hp_sdc.h
new file mode 100644
index 000000000000..debd71515312
--- /dev/null
+++ b/include/linux/hp_sdc.h
@@ -0,0 +1,300 @@
1/*
2 * HP i8042 System Device Controller -- header
3 *
4 * Copyright (c) 2001 Brian S. Julin
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL").
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 *
29 * References:
30 *
31 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
32 *
33 * System Device Controller Microprocessor Firmware Theory of Operation
34 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
35 *
36 */
37
38#ifndef _LINUX_HP_SDC_H
39#define _LINUX_HP_SDC_H
40
41#include <linux/interrupt.h>
42#include <linux/types.h>
43#include <linux/time.h>
44#include <linux/timer.h>
45#if defined(__hppa__)
46#include <asm/hardware.h>
47#endif
48
49
50/* No 4X status reads take longer than this (in usec).
51 */
52#define HP_SDC_MAX_REG_DELAY 20000
53
54typedef void (hp_sdc_irqhook) (int irq, void *dev_id,
55 uint8_t status, uint8_t data);
56
57int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback);
58int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback);
59int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback);
60int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback);
61int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback);
62int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback);
63
64typedef struct {
65 int actidx; /* Start of act. Acts are atomic WRT I/O to SDC */
66 int idx; /* Index within the act */
67 int endidx; /* transaction is over and done if idx == endidx */
68 uint8_t *seq; /* commands/data for the transaction */
69 union {
70 hp_sdc_irqhook *irqhook; /* Callback, isr or tasklet context */
71 struct semaphore *semaphore; /* Semaphore to sleep on. */
72 } act;
73} hp_sdc_transaction;
74int hp_sdc_enqueue_transaction(hp_sdc_transaction *this);
75int hp_sdc_dequeue_transaction(hp_sdc_transaction *this);
76
77/* The HP_SDC_ACT* values are peculiar to this driver.
78 * Nuance: never HP_SDC_ACT_DATAIN | HP_SDC_ACT_DEALLOC, use another
79 * act to perform the dealloc.
80 */
81#define HP_SDC_ACT_PRECMD 0x01 /* Send a command first */
82#define HP_SDC_ACT_DATAREG 0x02 /* Set data registers */
83#define HP_SDC_ACT_DATAOUT 0x04 /* Send data bytes */
84#define HP_SDC_ACT_POSTCMD 0x08 /* Send command after */
85#define HP_SDC_ACT_DATAIN 0x10 /* Collect data after */
86#define HP_SDC_ACT_DURING 0x1f
87#define HP_SDC_ACT_SEMAPHORE 0x20 /* Raise semaphore after */
88#define HP_SDC_ACT_CALLBACK 0x40 /* Pass data to IRQ handler */
89#define HP_SDC_ACT_DEALLOC 0x80 /* Destroy transaction after */
90#define HP_SDC_ACT_AFTER 0xe0
91#define HP_SDC_ACT_DEAD 0x60 /* Act timed out. */
92
93/* Rest of the flags are straightforward representation of the SDC interface */
94#define HP_SDC_STATUS_IBF 0x02 /* Input buffer full */
95
96#define HP_SDC_STATUS_IRQMASK 0xf0 /* Bits containing "level 1" irq */
97#define HP_SDC_STATUS_PERIODIC 0x10 /* Periodic 10ms timer */
98#define HP_SDC_STATUS_USERTIMER 0x20 /* "Special purpose" timer */
99#define HP_SDC_STATUS_TIMER 0x30 /* Both PERIODIC and USERTIMER */
100#define HP_SDC_STATUS_REG 0x40 /* Data from an i8042 register */
101#define HP_SDC_STATUS_HILCMD 0x50 /* Command from HIL MLC */
102#define HP_SDC_STATUS_HILDATA 0x60 /* Data from HIL MLC */
103#define HP_SDC_STATUS_PUP 0x70 /* Sucessful power-up self test */
104#define HP_SDC_STATUS_KCOOKED 0x80 /* Key from cooked kbd */
105#define HP_SDC_STATUS_KRPG 0xc0 /* Key from Repeat Gen */
106#define HP_SDC_STATUS_KMOD_SUP 0x10 /* Shift key is up */
107#define HP_SDC_STATUS_KMOD_CUP 0x20 /* Control key is up */
108
109#define HP_SDC_NMISTATUS_FHS 0x40 /* NMI is a fast handshake irq */
110
111/* Internal i8042 registers (there are more, but they are not too useful). */
112
113#define HP_SDC_USE 0x02 /* Resource usage (including OB bit) */
114#define HP_SDC_IM 0x04 /* Interrupt mask */
115#define HP_SDC_CFG 0x11 /* Configuration register */
116#define HP_SDC_KBLANGUAGE 0x12 /* Keyboard language */
117
118#define HP_SDC_D0 0x70 /* General purpose data buffer 0 */
119#define HP_SDC_D1 0x71 /* General purpose data buffer 1 */
120#define HP_SDC_D2 0x72 /* General purpose data buffer 2 */
121#define HP_SDC_D3 0x73 /* General purpose data buffer 3 */
122#define HP_SDC_VT1 0x74 /* Timer for voice 1 */
123#define HP_SDC_VT2 0x75 /* Timer for voice 2 */
124#define HP_SDC_VT3 0x76 /* Timer for voice 3 */
125#define HP_SDC_VT4 0x77 /* Timer for voice 4 */
126#define HP_SDC_KBN 0x78 /* Which HIL devs are Nimitz */
127#define HP_SDC_KBC 0x79 /* Which HIL devs are cooked kbds */
128#define HP_SDC_LPS 0x7a /* i8042's view of HIL status */
129#define HP_SDC_LPC 0x7b /* i8042's view of HIL "control" */
130#define HP_SDC_RSV 0x7c /* Reserved "for testing" */
131#define HP_SDC_LPR 0x7d /* i8042 count of HIL reconfigs */
132#define HP_SDC_XTD 0x7e /* "Extended Configuration" register */
133#define HP_SDC_STR 0x7f /* i8042 self-test result */
134
135/* Bitfields for above registers */
136#define HP_SDC_USE_LOOP 0x04 /* Command is currently on the loop. */
137
138#define HP_SDC_IM_MASK 0x1f /* these bits not part of cmd/status */
139#define HP_SDC_IM_FH 0x10 /* Mask the fast handshake irq */
140#define HP_SDC_IM_PT 0x08 /* Mask the periodic timer irq */
141#define HP_SDC_IM_TIMERS 0x04 /* Mask the MT/DT/CT irq */
142#define HP_SDC_IM_RESET 0x02 /* Mask the reset key irq */
143#define HP_SDC_IM_HIL 0x01 /* Mask the HIL MLC irq */
144
145#define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */
146#define HP_SDC_CFG_KBD 0x10 /* There is a keyboard */
147#define HP_SDC_CFG_NEW 0x20 /* Supports/uses HIL MLC */
148#define HP_SDC_CFG_KBD_OLD 0x03 /* keyboard code for non-HIL */
149#define HP_SDC_CFG_KBD_NEW 0x07 /* keyboard code from HIL autoconfig */
150#define HP_SDC_CFG_REV 0x40 /* Code revision bit */
151#define HP_SDC_CFG_IDPROM 0x80 /* IDPROM present in kbd (not HIL) */
152
153#define HP_SDC_LPS_NDEV 0x07 /* # devices autoconfigured on HIL */
154#define HP_SDC_LPS_ACSUCC 0x08 /* loop autoconfigured successfully */
155#define HP_SDC_LPS_ACFAIL 0x80 /* last loop autoconfigure failed */
156
157#define HP_SDC_LPC_APE_IPF 0x01 /* HIL MLC APE/IPF (autopoll) set */
158#define HP_SDC_LPC_ARCONERR 0x02 /* i8042 autoreconfigs loop on err */
159#define HP_SDC_LPC_ARCQUIET 0x03 /* i8042 doesn't report autoreconfigs*/
160#define HP_SDC_LPC_COOK 0x10 /* i8042 cooks devices in _KBN */
161#define HP_SDC_LPC_RC 0x80 /* causes autoreconfig */
162
163#define HP_SDC_XTD_REV 0x07 /* contains revision code */
164#define HP_SDC_XTD_REV_STRINGS(val, str) \
165switch (val) { \
166 case 0x1: str = "1820-3712"; break; \
167 case 0x2: str = "1820-4379"; break; \
168 case 0x3: str = "1820-4784"; break; \
169 default: str = "unknown"; \
170};
171#define HP_SDC_XTD_BEEPER 0x08 /* TI SN76494 beeper available */
172#define HP_SDC_XTD_BBRTC 0x20 /* OKI MSM-58321 BBRTC present */
173
174#define HP_SDC_CMD_LOAD_RT 0x31 /* Load real time (from 8042) */
175#define HP_SDC_CMD_LOAD_FHS 0x36 /* Load the fast handshake timer */
176#define HP_SDC_CMD_LOAD_MT 0x38 /* Load the match timer */
177#define HP_SDC_CMD_LOAD_DT 0x3B /* Load the delay timer */
178#define HP_SDC_CMD_LOAD_CT 0x3E /* Load the cycle timer */
179
180#define HP_SDC_CMD_SET_IM 0x40 /* 010xxxxx == set irq mask */
181
182/* The documents provided do not explicitly state that all registers betweem
183 * 0x01 and 0x1f inclusive can be read by sending their register index as a
184 * command, but this is implied and appears to be the case.
185 */
186#define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */
187#define HP_SDC_CMD_READ_USE 0x02 /* Undocumented! Load from usage reg */
188#define HP_SDC_CMD_READ_IM 0x04 /* Load current interrupt mask */
189#define HP_SDC_CMD_READ_KCC 0x11 /* Load primary kbd config code */
190#define HP_SDC_CMD_READ_KLC 0x12 /* Load primary kbd language code */
191#define HP_SDC_CMD_READ_T1 0x13 /* Load timer output buffer byte 1 */
192#define HP_SDC_CMD_READ_T2 0x14 /* Load timer output buffer byte 1 */
193#define HP_SDC_CMD_READ_T3 0x15 /* Load timer output buffer byte 1 */
194#define HP_SDC_CMD_READ_T4 0x16 /* Load timer output buffer byte 1 */
195#define HP_SDC_CMD_READ_T5 0x17 /* Load timer output buffer byte 1 */
196#define HP_SDC_CMD_READ_D0 0xf0 /* Load from i8042 RAM location 0x70 */
197#define HP_SDC_CMD_READ_D1 0xf1 /* Load from i8042 RAM location 0x71 */
198#define HP_SDC_CMD_READ_D2 0xf2 /* Load from i8042 RAM location 0x72 */
199#define HP_SDC_CMD_READ_D3 0xf3 /* Load from i8042 RAM location 0x73 */
200#define HP_SDC_CMD_READ_VT1 0xf4 /* Load from i8042 RAM location 0x74 */
201#define HP_SDC_CMD_READ_VT2 0xf5 /* Load from i8042 RAM location 0x75 */
202#define HP_SDC_CMD_READ_VT3 0xf6 /* Load from i8042 RAM location 0x76 */
203#define HP_SDC_CMD_READ_VT4 0xf7 /* Load from i8042 RAM location 0x77 */
204#define HP_SDC_CMD_READ_KBN 0xf8 /* Load from i8042 RAM location 0x78 */
205#define HP_SDC_CMD_READ_KBC 0xf9 /* Load from i8042 RAM location 0x79 */
206#define HP_SDC_CMD_READ_LPS 0xfa /* Load from i8042 RAM location 0x7a */
207#define HP_SDC_CMD_READ_LPC 0xfb /* Load from i8042 RAM location 0x7b */
208#define HP_SDC_CMD_READ_RSV 0xfc /* Load from i8042 RAM location 0x7c */
209#define HP_SDC_CMD_READ_LPR 0xfd /* Load from i8042 RAM location 0x7d */
210#define HP_SDC_CMD_READ_XTD 0xfe /* Load from i8042 RAM location 0x7e */
211#define HP_SDC_CMD_READ_STR 0xff /* Load from i8042 RAM location 0x7f */
212
213#define HP_SDC_CMD_SET_ARD 0xA0 /* Set emulated autorepeat delay */
214#define HP_SDC_CMD_SET_ARR 0xA2 /* Set emulated autorepeat rate */
215#define HP_SDC_CMD_SET_BELL 0xA3 /* Set voice 3 params for "beep" cmd */
216#define HP_SDC_CMD_SET_RPGR 0xA6 /* Set "RPG" irq rate (doesn't work) */
217#define HP_SDC_CMD_SET_RTMS 0xAD /* Set the RTC time (milliseconds) */
218#define HP_SDC_CMD_SET_RTD 0xAF /* Set the RTC time (days) */
219#define HP_SDC_CMD_SET_FHS 0xB2 /* Set fast handshake timer */
220#define HP_SDC_CMD_SET_MT 0xB4 /* Set match timer */
221#define HP_SDC_CMD_SET_DT 0xB7 /* Set delay timer */
222#define HP_SDC_CMD_SET_CT 0xBA /* Set cycle timer */
223#define HP_SDC_CMD_SET_RAMP 0xC1 /* Reset READ_RAM autoinc counter */
224#define HP_SDC_CMD_SET_D0 0xe0 /* Load to i8042 RAM location 0x70 */
225#define HP_SDC_CMD_SET_D1 0xe1 /* Load to i8042 RAM location 0x71 */
226#define HP_SDC_CMD_SET_D2 0xe2 /* Load to i8042 RAM location 0x72 */
227#define HP_SDC_CMD_SET_D3 0xe3 /* Load to i8042 RAM location 0x73 */
228#define HP_SDC_CMD_SET_VT1 0xe4 /* Load to i8042 RAM location 0x74 */
229#define HP_SDC_CMD_SET_VT2 0xe5 /* Load to i8042 RAM location 0x75 */
230#define HP_SDC_CMD_SET_VT3 0xe6 /* Load to i8042 RAM location 0x76 */
231#define HP_SDC_CMD_SET_VT4 0xe7 /* Load to i8042 RAM location 0x77 */
232#define HP_SDC_CMD_SET_KBN 0xe8 /* Load to i8042 RAM location 0x78 */
233#define HP_SDC_CMD_SET_KBC 0xe9 /* Load to i8042 RAM location 0x79 */
234#define HP_SDC_CMD_SET_LPS 0xea /* Load to i8042 RAM location 0x7a */
235#define HP_SDC_CMD_SET_LPC 0xeb /* Load to i8042 RAM location 0x7b */
236#define HP_SDC_CMD_SET_RSV 0xec /* Load to i8042 RAM location 0x7c */
237#define HP_SDC_CMD_SET_LPR 0xed /* Load to i8042 RAM location 0x7d */
238#define HP_SDC_CMD_SET_XTD 0xee /* Load to i8042 RAM location 0x7e */
239#define HP_SDC_CMD_SET_STR 0xef /* Load to i8042 RAM location 0x7f */
240
241#define HP_SDC_CMD_DO_RTCW 0xc2 /* i8042 RAM 0x70 --> RTC */
242#define HP_SDC_CMD_DO_RTCR 0xc3 /* RTC[0x70 0:3] --> irq/status/data */
243#define HP_SDC_CMD_DO_BEEP 0xc4 /* i8042 RAM 0x70-74 --> beeper,VT3 */
244#define HP_SDC_CMD_DO_HIL 0xc5 /* i8042 RAM 0x70-73 -->
245 HIL MLC R0,R1 i8042 HIL watchdog */
246
247/* Values used to (de)mangle input/output to/from the HIL MLC */
248#define HP_SDC_DATA 0x40 /* Data from an 8042 register */
249#define HP_SDC_HIL_CMD 0x50 /* Data from HIL MLC R1/8042 */
250#define HP_SDC_HIL_R1MASK 0x0f /* Contents of HIL MLC R1 0:3 */
251#define HP_SDC_HIL_AUTO 0x10 /* Set if POL results from i8042 */
252#define HP_SDC_HIL_ISERR 0x80 /* Has meaning as in next 4 values */
253#define HP_SDC_HIL_RC_DONE 0x80 /* i8042 auto-configured loop */
254#define HP_SDC_HIL_ERR 0x81 /* HIL MLC R2 had a bit set */
255#define HP_SDC_HIL_TO 0x82 /* i8042 HIL watchdog expired */
256#define HP_SDC_HIL_RC 0x84 /* i8042 is auto-configuring loop */
257#define HP_SDC_HIL_DAT 0x60 /* Data from HIL MLC R0 */
258
259
260typedef struct {
261 rwlock_t ibf_lock;
262 rwlock_t lock; /* user/tasklet lock */
263 rwlock_t rtq_lock; /* isr/tasklet lock */
264 rwlock_t hook_lock; /* isr/user lock for handler add/del */
265
266 unsigned int irq, nmi; /* Our IRQ lines */
267 unsigned long base_io, status_io, data_io; /* Our IO ports */
268
269 uint8_t im; /* Interrupt mask */
270 int set_im; /* Interrupt mask needs to be set. */
271
272 int ibf; /* Last known status of IBF flag */
273 uint8_t wi; /* current i8042 write index */
274 uint8_t r7[4]; /* current i8042[0x70 - 0x74] values */
275 uint8_t r11, r7e; /* Values from version/revision regs */
276
277 hp_sdc_irqhook *timer, *reg, *hil, *pup, *cooked;
278
279#define HP_SDC_QUEUE_LEN 16
280 hp_sdc_transaction *tq[HP_SDC_QUEUE_LEN]; /* All pending read/writes */
281
282 int rcurr, rqty; /* Current read transact in process */
283 struct timeval rtv; /* Time when current read started */
284 int wcurr; /* Current write transact in process */
285
286 int dev_err; /* carries status from registration */
287#if defined(__hppa__)
288 struct parisc_device *dev;
289#elif defined(__mc68000__)
290 void *dev;
291#else
292#error No support for device registration on this arch yet.
293#endif
294
295 struct timer_list kicker; /* Keeps below task alive */
296 struct tasklet_struct task;
297
298} hp_i8042_sdc;
299
300#endif /* _LINUX_HP_SDC_H */
diff --git a/include/linux/input.h b/include/linux/input.h
index e8c296ff6257..d7836311ada9 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -644,6 +644,7 @@ struct input_absinfo {
644#define BUS_ADB 0x17 644#define BUS_ADB 0x17
645#define BUS_I2C 0x18 645#define BUS_I2C 0x18
646#define BUS_HOST 0x19 646#define BUS_HOST 0x19
647#define BUS_GSC 0x1A
647 648
648/* 649/*
649 * Values describing the status of an effect 650 * Values describing the status of an effect
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 11:29:05 -0500