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-rw-r--r--include/linux/usb/langwell_otg.h177
-rw-r--r--include/linux/usb/m66592.h44
-rw-r--r--include/linux/usb/r8a66597.h375
-rw-r--r--include/linux/usb/rndis_host.h13
-rw-r--r--include/linux/usb/serial.h13
-rw-r--r--include/linux/usb/usbnet.h19
-rw-r--r--include/linux/usb/video.h164
7 files changed, 610 insertions, 195 deletions
diff --git a/include/linux/usb/langwell_otg.h b/include/linux/usb/langwell_otg.h
deleted file mode 100644
index e115ae6df1da..000000000000
--- a/include/linux/usb/langwell_otg.h
+++ /dev/null
@@ -1,177 +0,0 @@
1/*
2 * Intel Langwell USB OTG transceiver driver
3 * Copyright (C) 2008, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#ifndef __LANGWELL_OTG_H__
21#define __LANGWELL_OTG_H__
22
23/* notify transceiver driver about OTG events */
24extern void langwell_update_transceiver(void);
25/* HCD register bus driver */
26extern int langwell_register_host(struct pci_driver *host_driver);
27/* HCD unregister bus driver */
28extern void langwell_unregister_host(struct pci_driver *host_driver);
29/* DCD register bus driver */
30extern int langwell_register_peripheral(struct pci_driver *client_driver);
31/* DCD unregister bus driver */
32extern void langwell_unregister_peripheral(struct pci_driver *client_driver);
33/* No silent failure, output warning message */
34extern void langwell_otg_nsf_msg(unsigned long message);
35
36#define CI_USBCMD 0x30
37# define USBCMD_RST BIT(1)
38# define USBCMD_RS BIT(0)
39#define CI_USBSTS 0x34
40# define USBSTS_SLI BIT(8)
41# define USBSTS_URI BIT(6)
42# define USBSTS_PCI BIT(2)
43#define CI_PORTSC1 0x74
44# define PORTSC_PP BIT(12)
45# define PORTSC_LS (BIT(11) | BIT(10))
46# define PORTSC_SUSP BIT(7)
47# define PORTSC_CCS BIT(0)
48#define CI_HOSTPC1 0xb4
49# define HOSTPC1_PHCD BIT(22)
50#define CI_OTGSC 0xf4
51# define OTGSC_DPIE BIT(30)
52# define OTGSC_1MSE BIT(29)
53# define OTGSC_BSEIE BIT(28)
54# define OTGSC_BSVIE BIT(27)
55# define OTGSC_ASVIE BIT(26)
56# define OTGSC_AVVIE BIT(25)
57# define OTGSC_IDIE BIT(24)
58# define OTGSC_DPIS BIT(22)
59# define OTGSC_1MSS BIT(21)
60# define OTGSC_BSEIS BIT(20)
61# define OTGSC_BSVIS BIT(19)
62# define OTGSC_ASVIS BIT(18)
63# define OTGSC_AVVIS BIT(17)
64# define OTGSC_IDIS BIT(16)
65# define OTGSC_DPS BIT(14)
66# define OTGSC_1MST BIT(13)
67# define OTGSC_BSE BIT(12)
68# define OTGSC_BSV BIT(11)
69# define OTGSC_ASV BIT(10)
70# define OTGSC_AVV BIT(9)
71# define OTGSC_ID BIT(8)
72# define OTGSC_HABA BIT(7)
73# define OTGSC_HADP BIT(6)
74# define OTGSC_IDPU BIT(5)
75# define OTGSC_DP BIT(4)
76# define OTGSC_OT BIT(3)
77# define OTGSC_HAAR BIT(2)
78# define OTGSC_VC BIT(1)
79# define OTGSC_VD BIT(0)
80# define OTGSC_INTEN_MASK (0x7f << 24)
81# define OTGSC_INTSTS_MASK (0x7f << 16)
82#define CI_USBMODE 0xf8
83# define USBMODE_CM (BIT(1) | BIT(0))
84# define USBMODE_IDLE 0
85# define USBMODE_DEVICE 0x2
86# define USBMODE_HOST 0x3
87
88#define INTR_DUMMY_MASK (USBSTS_SLI | USBSTS_URI | USBSTS_PCI)
89
90struct otg_hsm {
91 /* Input */
92 int a_bus_resume;
93 int a_bus_suspend;
94 int a_conn;
95 int a_sess_vld;
96 int a_srp_det;
97 int a_vbus_vld;
98 int b_bus_resume;
99 int b_bus_suspend;
100 int b_conn;
101 int b_se0_srp;
102 int b_sess_end;
103 int b_sess_vld;
104 int id;
105
106 /* Internal variables */
107 int a_set_b_hnp_en;
108 int b_srp_done;
109 int b_hnp_enable;
110
111 /* Timeout indicator for timers */
112 int a_wait_vrise_tmout;
113 int a_wait_bcon_tmout;
114 int a_aidl_bdis_tmout;
115 int b_ase0_brst_tmout;
116 int b_bus_suspend_tmout;
117 int b_srp_res_tmout;
118
119 /* Informative variables */
120 int a_bus_drop;
121 int a_bus_req;
122 int a_clr_err;
123 int a_suspend_req;
124 int b_bus_req;
125
126 /* Output */
127 int drv_vbus;
128 int loc_conn;
129 int loc_sof;
130
131 /* Others */
132 int b_bus_suspend_vld;
133};
134
135#define TA_WAIT_VRISE 100
136#define TA_WAIT_BCON 30000
137#define TA_AIDL_BDIS 15000
138#define TB_ASE0_BRST 5000
139#define TB_SE0_SRP 2
140#define TB_SRP_RES 100
141#define TB_BUS_SUSPEND 500
142
143struct langwell_otg_timer {
144 unsigned long expires; /* Number of count increase to timeout */
145 unsigned long count; /* Tick counter */
146 void (*function)(unsigned long); /* Timeout function */
147 unsigned long data; /* Data passed to function */
148 struct list_head list;
149};
150
151struct langwell_otg {
152 struct otg_transceiver otg;
153 struct otg_hsm hsm;
154 void __iomem *regs;
155 unsigned region;
156 struct pci_driver *host_ops;
157 struct pci_driver *client_ops;
158 struct pci_dev *pdev;
159 struct work_struct work;
160 struct workqueue_struct *qwork;
161 spinlock_t lock;
162 spinlock_t wq_lock;
163};
164
165static inline struct langwell_otg *otg_to_langwell(struct otg_transceiver *otg)
166{
167 return container_of(otg, struct langwell_otg, otg);
168}
169
170#ifdef DEBUG
171#define otg_dbg(fmt, args...) \
172 printk(KERN_DEBUG fmt , ## args)
173#else
174#define otg_dbg(fmt, args...) \
175 do { } while (0)
176#endif /* DEBUG */
177#endif /* __LANGWELL_OTG_H__ */
diff --git a/include/linux/usb/m66592.h b/include/linux/usb/m66592.h
new file mode 100644
index 000000000000..cda9625e7df0
--- /dev/null
+++ b/include/linux/usb/m66592.h
@@ -0,0 +1,44 @@
1/*
2 * M66592 driver platform data
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 *
19 */
20
21#ifndef __LINUX_USB_M66592_H
22#define __LINUX_USB_M66592_H
23
24#define M66592_PLATDATA_XTAL_12MHZ 0x01
25#define M66592_PLATDATA_XTAL_24MHZ 0x02
26#define M66592_PLATDATA_XTAL_48MHZ 0x03
27
28struct m66592_platdata {
29 /* one = on chip controller, zero = external controller */
30 unsigned on_chip:1;
31
32 /* one = big endian, zero = little endian */
33 unsigned endian:1;
34
35 /* (external controller only) M66592_PLATDATA_XTAL_nnMHZ */
36 unsigned xtal:2;
37
38 /* (external controller only) one = 3.3V, zero = 1.5V */
39 unsigned vif:1;
40
41};
42
43#endif /* __LINUX_USB_M66592_H */
44
diff --git a/include/linux/usb/r8a66597.h b/include/linux/usb/r8a66597.h
index e9f0384fa20c..26d216734057 100644
--- a/include/linux/usb/r8a66597.h
+++ b/include/linux/usb/r8a66597.h
@@ -28,9 +28,12 @@
28#define R8A66597_PLATDATA_XTAL_48MHZ 0x03 28#define R8A66597_PLATDATA_XTAL_48MHZ 0x03
29 29
30struct r8a66597_platdata { 30struct r8a66597_platdata {
31 /* This ops can controll port power instead of DVSTCTR register. */ 31 /* This callback can control port power instead of DVSTCTR register. */
32 void (*port_power)(int port, int power); 32 void (*port_power)(int port, int power);
33 33
34 /* set one = on chip controller, set zero = external controller */
35 unsigned on_chip:1;
36
34 /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */ 37 /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
35 unsigned xtal:2; 38 unsigned xtal:2;
36 39
@@ -40,5 +43,373 @@ struct r8a66597_platdata {
40 /* set one = big endian, set zero = little endian */ 43 /* set one = big endian, set zero = little endian */
41 unsigned endian:1; 44 unsigned endian:1;
42}; 45};
43#endif 46
47/* Register definitions */
48#define SYSCFG0 0x00
49#define SYSCFG1 0x02
50#define SYSSTS0 0x04
51#define SYSSTS1 0x06
52#define DVSTCTR0 0x08
53#define DVSTCTR1 0x0A
54#define TESTMODE 0x0C
55#define PINCFG 0x0E
56#define DMA0CFG 0x10
57#define DMA1CFG 0x12
58#define CFIFO 0x14
59#define D0FIFO 0x18
60#define D1FIFO 0x1C
61#define CFIFOSEL 0x20
62#define CFIFOCTR 0x22
63#define CFIFOSIE 0x24
64#define D0FIFOSEL 0x28
65#define D0FIFOCTR 0x2A
66#define D1FIFOSEL 0x2C
67#define D1FIFOCTR 0x2E
68#define INTENB0 0x30
69#define INTENB1 0x32
70#define INTENB2 0x34
71#define BRDYENB 0x36
72#define NRDYENB 0x38
73#define BEMPENB 0x3A
74#define SOFCFG 0x3C
75#define INTSTS0 0x40
76#define INTSTS1 0x42
77#define INTSTS2 0x44
78#define BRDYSTS 0x46
79#define NRDYSTS 0x48
80#define BEMPSTS 0x4A
81#define FRMNUM 0x4C
82#define UFRMNUM 0x4E
83#define USBADDR 0x50
84#define USBREQ 0x54
85#define USBVAL 0x56
86#define USBINDX 0x58
87#define USBLENG 0x5A
88#define DCPCFG 0x5C
89#define DCPMAXP 0x5E
90#define DCPCTR 0x60
91#define PIPESEL 0x64
92#define PIPECFG 0x68
93#define PIPEBUF 0x6A
94#define PIPEMAXP 0x6C
95#define PIPEPERI 0x6E
96#define PIPE1CTR 0x70
97#define PIPE2CTR 0x72
98#define PIPE3CTR 0x74
99#define PIPE4CTR 0x76
100#define PIPE5CTR 0x78
101#define PIPE6CTR 0x7A
102#define PIPE7CTR 0x7C
103#define PIPE8CTR 0x7E
104#define PIPE9CTR 0x80
105#define PIPE1TRE 0x90
106#define PIPE1TRN 0x92
107#define PIPE2TRE 0x94
108#define PIPE2TRN 0x96
109#define PIPE3TRE 0x98
110#define PIPE3TRN 0x9A
111#define PIPE4TRE 0x9C
112#define PIPE4TRN 0x9E
113#define PIPE5TRE 0xA0
114#define PIPE5TRN 0xA2
115#define DEVADD0 0xD0
116#define DEVADD1 0xD2
117#define DEVADD2 0xD4
118#define DEVADD3 0xD6
119#define DEVADD4 0xD8
120#define DEVADD5 0xDA
121#define DEVADD6 0xDC
122#define DEVADD7 0xDE
123#define DEVADD8 0xE0
124#define DEVADD9 0xE2
125#define DEVADDA 0xE4
126
127/* System Configuration Control Register */
128#define XTAL 0xC000 /* b15-14: Crystal selection */
129#define XTAL48 0x8000 /* 48MHz */
130#define XTAL24 0x4000 /* 24MHz */
131#define XTAL12 0x0000 /* 12MHz */
132#define XCKE 0x2000 /* b13: External clock enable */
133#define PLLC 0x0800 /* b11: PLL control */
134#define SCKE 0x0400 /* b10: USB clock enable */
135#define PCSDIS 0x0200 /* b9: not CS wakeup */
136#define LPSME 0x0100 /* b8: Low power sleep mode */
137#define HSE 0x0080 /* b7: Hi-speed enable */
138#define DCFM 0x0040 /* b6: Controller function select */
139#define DRPD 0x0020 /* b5: D+/- pull down control */
140#define DPRPU 0x0010 /* b4: D+ pull up control */
141#define USBE 0x0001 /* b0: USB module operation enable */
142
143/* System Configuration Status Register */
144#define OVCBIT 0x8000 /* b15-14: Over-current bit */
145#define OVCMON 0xC000 /* b15-14: Over-current monitor */
146#define SOFEA 0x0020 /* b5: SOF monitor */
147#define IDMON 0x0004 /* b3: ID-pin monitor */
148#define LNST 0x0003 /* b1-0: D+, D- line status */
149#define SE1 0x0003 /* SE1 */
150#define FS_KSTS 0x0002 /* Full-Speed K State */
151#define FS_JSTS 0x0001 /* Full-Speed J State */
152#define LS_JSTS 0x0002 /* Low-Speed J State */
153#define LS_KSTS 0x0001 /* Low-Speed K State */
154#define SE0 0x0000 /* SE0 */
155
156/* Device State Control Register */
157#define EXTLP0 0x0400 /* b10: External port */
158#define VBOUT 0x0200 /* b9: VBUS output */
159#define WKUP 0x0100 /* b8: Remote wakeup */
160#define RWUPE 0x0080 /* b7: Remote wakeup sense */
161#define USBRST 0x0040 /* b6: USB reset enable */
162#define RESUME 0x0020 /* b5: Resume enable */
163#define UACT 0x0010 /* b4: USB bus enable */
164#define RHST 0x0007 /* b1-0: Reset handshake status */
165#define HSPROC 0x0004 /* HS handshake is processing */
166#define HSMODE 0x0003 /* Hi-Speed mode */
167#define FSMODE 0x0002 /* Full-Speed mode */
168#define LSMODE 0x0001 /* Low-Speed mode */
169#define UNDECID 0x0000 /* Undecided */
170
171/* Test Mode Register */
172#define UTST 0x000F /* b3-0: Test select */
173#define H_TST_PACKET 0x000C /* HOST TEST Packet */
174#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
175#define H_TST_K 0x000A /* HOST TEST K */
176#define H_TST_J 0x0009 /* HOST TEST J */
177#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
178#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
179#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
180#define P_TST_K 0x0002 /* PERI TEST K */
181#define P_TST_J 0x0001 /* PERI TEST J */
182#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
183
184/* Data Pin Configuration Register */
185#define LDRV 0x8000 /* b15: Drive Current Adjust */
186#define VIF1 0x0000 /* VIF = 1.8V */
187#define VIF3 0x8000 /* VIF = 3.3V */
188#define INTA 0x0001 /* b1: USB INT-pin active */
189
190/* DMAx Pin Configuration Register */
191#define DREQA 0x4000 /* b14: Dreq active select */
192#define BURST 0x2000 /* b13: Burst mode */
193#define DACKA 0x0400 /* b10: Dack active select */
194#define DFORM 0x0380 /* b9-7: DMA mode select */
195#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
196#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
197#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
198#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
199#define DENDA 0x0040 /* b6: Dend active select */
200#define PKTM 0x0020 /* b5: Packet mode */
201#define DENDE 0x0010 /* b4: Dend enable */
202#define OBUS 0x0004 /* b2: OUTbus mode */
203
204/* CFIFO/DxFIFO Port Select Register */
205#define RCNT 0x8000 /* b15: Read count mode */
206#define REW 0x4000 /* b14: Buffer rewind */
207#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
208#define DREQE 0x1000 /* b12: DREQ output enable */
209#define MBW_8 0x0000 /* 8bit */
210#define MBW_16 0x0400 /* 16bit */
211#define MBW_32 0x0800 /* 32bit */
212#define BIGEND 0x0100 /* b8: Big endian mode */
213#define BYTE_LITTLE 0x0000 /* little dendian */
214#define BYTE_BIG 0x0100 /* big endifan */
215#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
216#define CURPIPE 0x000F /* b2-0: PIPE select */
217
218/* CFIFO/DxFIFO Port Control Register */
219#define BVAL 0x8000 /* b15: Buffer valid flag */
220#define BCLR 0x4000 /* b14: Buffer clear */
221#define FRDY 0x2000 /* b13: FIFO ready */
222#define DTLN 0x0FFF /* b11-0: FIFO received data length */
223
224/* Interrupt Enable Register 0 */
225#define VBSE 0x8000 /* b15: VBUS interrupt */
226#define RSME 0x4000 /* b14: Resume interrupt */
227#define SOFE 0x2000 /* b13: Frame update interrupt */
228#define DVSE 0x1000 /* b12: Device state transition interrupt */
229#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
230#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
231#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
232#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
233
234/* Interrupt Enable Register 1 */
235#define OVRCRE 0x8000 /* b15: Over-current interrupt */
236#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
237#define DTCHE 0x1000 /* b12: Detach sense interrupt */
238#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
239#define EOFERRE 0x0040 /* b6: EOF error interrupt */
240#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
241#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
242
243/* BRDY Interrupt Enable/Status Register */
244#define BRDY9 0x0200 /* b9: PIPE9 */
245#define BRDY8 0x0100 /* b8: PIPE8 */
246#define BRDY7 0x0080 /* b7: PIPE7 */
247#define BRDY6 0x0040 /* b6: PIPE6 */
248#define BRDY5 0x0020 /* b5: PIPE5 */
249#define BRDY4 0x0010 /* b4: PIPE4 */
250#define BRDY3 0x0008 /* b3: PIPE3 */
251#define BRDY2 0x0004 /* b2: PIPE2 */
252#define BRDY1 0x0002 /* b1: PIPE1 */
253#define BRDY0 0x0001 /* b1: PIPE0 */
254
255/* NRDY Interrupt Enable/Status Register */
256#define NRDY9 0x0200 /* b9: PIPE9 */
257#define NRDY8 0x0100 /* b8: PIPE8 */
258#define NRDY7 0x0080 /* b7: PIPE7 */
259#define NRDY6 0x0040 /* b6: PIPE6 */
260#define NRDY5 0x0020 /* b5: PIPE5 */
261#define NRDY4 0x0010 /* b4: PIPE4 */
262#define NRDY3 0x0008 /* b3: PIPE3 */
263#define NRDY2 0x0004 /* b2: PIPE2 */
264#define NRDY1 0x0002 /* b1: PIPE1 */
265#define NRDY0 0x0001 /* b1: PIPE0 */
266
267/* BEMP Interrupt Enable/Status Register */
268#define BEMP9 0x0200 /* b9: PIPE9 */
269#define BEMP8 0x0100 /* b8: PIPE8 */
270#define BEMP7 0x0080 /* b7: PIPE7 */
271#define BEMP6 0x0040 /* b6: PIPE6 */
272#define BEMP5 0x0020 /* b5: PIPE5 */
273#define BEMP4 0x0010 /* b4: PIPE4 */
274#define BEMP3 0x0008 /* b3: PIPE3 */
275#define BEMP2 0x0004 /* b2: PIPE2 */
276#define BEMP1 0x0002 /* b1: PIPE1 */
277#define BEMP0 0x0001 /* b0: PIPE0 */
278
279/* SOF Pin Configuration Register */
280#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
281#define BRDYM 0x0040 /* b6: BRDY clear timing */
282#define INTL 0x0020 /* b5: Interrupt sense select */
283#define EDGESTS 0x0010 /* b4: */
284#define SOFMODE 0x000C /* b3-2: SOF pin select */
285#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
286#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
287#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
288
289/* Interrupt Status Register 0 */
290#define VBINT 0x8000 /* b15: VBUS interrupt */
291#define RESM 0x4000 /* b14: Resume interrupt */
292#define SOFR 0x2000 /* b13: SOF frame update interrupt */
293#define DVST 0x1000 /* b12: Device state transition interrupt */
294#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
295#define BEMP 0x0400 /* b10: Buffer empty interrupt */
296#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
297#define BRDY 0x0100 /* b8: Buffer ready interrupt */
298#define VBSTS 0x0080 /* b7: VBUS input port */
299#define DVSQ 0x0070 /* b6-4: Device state */
300#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
301#define DS_SPD_ADDR 0x0060 /* Suspend Address */
302#define DS_SPD_DFLT 0x0050 /* Suspend Default */
303#define DS_SPD_POWR 0x0040 /* Suspend Powered */
304#define DS_SUSP 0x0040 /* Suspend */
305#define DS_CNFG 0x0030 /* Configured */
306#define DS_ADDS 0x0020 /* Address */
307#define DS_DFLT 0x0010 /* Default */
308#define DS_POWR 0x0000 /* Powered */
309#define DVSQS 0x0030 /* b5-4: Device state */
310#define VALID 0x0008 /* b3: Setup packet detected flag */
311#define CTSQ 0x0007 /* b2-0: Control transfer stage */
312#define CS_SQER 0x0006 /* Sequence error */
313#define CS_WRND 0x0005 /* Control write nodata status stage */
314#define CS_WRSS 0x0004 /* Control write status stage */
315#define CS_WRDS 0x0003 /* Control write data stage */
316#define CS_RDSS 0x0002 /* Control read status stage */
317#define CS_RDDS 0x0001 /* Control read data stage */
318#define CS_IDST 0x0000 /* Idle or setup stage */
319
320/* Interrupt Status Register 1 */
321#define OVRCR 0x8000 /* b15: Over-current interrupt */
322#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
323#define DTCH 0x1000 /* b12: Detach sense interrupt */
324#define ATTCH 0x0800 /* b11: Attach sense interrupt */
325#define EOFERR 0x0040 /* b6: EOF-error interrupt */
326#define SIGN 0x0020 /* b5: Setup ignore interrupt */
327#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
328
329/* Frame Number Register */
330#define OVRN 0x8000 /* b15: Overrun error */
331#define CRCE 0x4000 /* b14: Received data error */
332#define FRNM 0x07FF /* b10-0: Frame number */
333
334/* Micro Frame Number Register */
335#define UFRNM 0x0007 /* b2-0: Micro frame number */
336
337/* Default Control Pipe Maxpacket Size Register */
338/* Pipe Maxpacket Size Register */
339#define DEVSEL 0xF000 /* b15-14: Device address select */
340#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
341
342/* Default Control Pipe Control Register */
343#define BSTS 0x8000 /* b15: Buffer status */
344#define SUREQ 0x4000 /* b14: Send USB request */
345#define CSCLR 0x2000 /* b13: complete-split status clear */
346#define CSSTS 0x1000 /* b12: complete-split status */
347#define SUREQCLR 0x0800 /* b11: stop setup request */
348#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
349#define SQSET 0x0080 /* b7: Sequence toggle bit set */
350#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
351#define PBUSY 0x0020 /* b5: pipe busy */
352#define PINGE 0x0010 /* b4: ping enable */
353#define CCPL 0x0004 /* b2: Enable control transfer complete */
354#define PID 0x0003 /* b1-0: Response PID */
355#define PID_STALL11 0x0003 /* STALL */
356#define PID_STALL 0x0002 /* STALL */
357#define PID_BUF 0x0001 /* BUF */
358#define PID_NAK 0x0000 /* NAK */
359
360/* Pipe Window Select Register */
361#define PIPENM 0x0007 /* b2-0: Pipe select */
362
363/* Pipe Configuration Register */
364#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
365#define R8A66597_ISO 0xC000 /* Isochronous */
366#define R8A66597_INT 0x8000 /* Interrupt */
367#define R8A66597_BULK 0x4000 /* Bulk */
368#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
369#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
370#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
371#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
372#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
373#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
374
375/* Pipe Buffer Configuration Register */
376#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
377#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
378#define PIPE0BUF 256
379#define PIPExBUF 64
380
381/* Pipe Maxpacket Size Register */
382#define MXPS 0x07FF /* b10-0: Maxpacket size */
383
384/* Pipe Cycle Configuration Register */
385#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
386#define IITV 0x0007 /* b2-0: Isochronous interval */
387
388/* Pipex Control Register */
389#define BSTS 0x8000 /* b15: Buffer status */
390#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
391#define CSCLR 0x2000 /* b13: complete-split status clear */
392#define CSSTS 0x1000 /* b12: complete-split status */
393#define ATREPM 0x0400 /* b10: Auto repeat mode */
394#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
395#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
396#define SQSET 0x0080 /* b7: Sequence toggle bit set */
397#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
398#define PBUSY 0x0020 /* b5: pipe busy */
399#define PID 0x0003 /* b1-0: Response PID */
400
401/* PIPExTRE */
402#define TRENB 0x0200 /* b9: Transaction counter enable */
403#define TRCLR 0x0100 /* b8: Transaction counter clear */
404
405/* PIPExTRN */
406#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
407
408/* DEVADDx */
409#define UPPHUB 0x7800
410#define HUBPORT 0x0700
411#define USBSPD 0x00C0
412#define RTPORT 0x0001
413
414#endif /* __LINUX_USB_R8A66597_H */
44 415
diff --git a/include/linux/usb/rndis_host.h b/include/linux/usb/rndis_host.h
index 37836b937d97..1ef1ebc2b04f 100644
--- a/include/linux/usb/rndis_host.h
+++ b/include/linux/usb/rndis_host.h
@@ -70,12 +70,13 @@ struct rndis_msg_hdr {
70#define RNDIS_MSG_KEEPALIVE_C (RNDIS_MSG_KEEPALIVE|RNDIS_MSG_COMPLETION) 70#define RNDIS_MSG_KEEPALIVE_C (RNDIS_MSG_KEEPALIVE|RNDIS_MSG_COMPLETION)
71 71
72/* codes for "status" field of completion messages */ 72/* codes for "status" field of completion messages */
73#define RNDIS_STATUS_SUCCESS cpu_to_le32(0x00000000) 73#define RNDIS_STATUS_SUCCESS cpu_to_le32(0x00000000)
74#define RNDIS_STATUS_FAILURE cpu_to_le32(0xc0000001) 74#define RNDIS_STATUS_FAILURE cpu_to_le32(0xc0000001)
75#define RNDIS_STATUS_INVALID_DATA cpu_to_le32(0xc0010015) 75#define RNDIS_STATUS_INVALID_DATA cpu_to_le32(0xc0010015)
76#define RNDIS_STATUS_NOT_SUPPORTED cpu_to_le32(0xc00000bb) 76#define RNDIS_STATUS_NOT_SUPPORTED cpu_to_le32(0xc00000bb)
77#define RNDIS_STATUS_MEDIA_CONNECT cpu_to_le32(0x4001000b) 77#define RNDIS_STATUS_MEDIA_CONNECT cpu_to_le32(0x4001000b)
78#define RNDIS_STATUS_MEDIA_DISCONNECT cpu_to_le32(0x4001000c) 78#define RNDIS_STATUS_MEDIA_DISCONNECT cpu_to_le32(0x4001000c)
79#define RNDIS_STATUS_MEDIA_SPECIFIC_INDICATION cpu_to_le32(0x40010012)
79 80
80/* codes for OID_GEN_PHYSICAL_MEDIUM */ 81/* codes for OID_GEN_PHYSICAL_MEDIUM */
81#define RNDIS_PHYSICAL_MEDIUM_UNSPECIFIED cpu_to_le32(0x00000000) 82#define RNDIS_PHYSICAL_MEDIUM_UNSPECIFIED cpu_to_le32(0x00000000)
diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h
index 44801d26a37a..7b85e327af91 100644
--- a/include/linux/usb/serial.h
+++ b/include/linux/usb/serial.h
@@ -238,9 +238,8 @@ struct usb_serial_driver {
238 int (*resume)(struct usb_serial *serial); 238 int (*resume)(struct usb_serial *serial);
239 239
240 /* serial function calls */ 240 /* serial function calls */
241 /* Called by console with tty = NULL and by tty */ 241 /* Called by console and by the tty layer */
242 int (*open)(struct tty_struct *tty, 242 int (*open)(struct tty_struct *tty, struct usb_serial_port *port);
243 struct usb_serial_port *port, struct file *filp);
244 void (*close)(struct usb_serial_port *port); 243 void (*close)(struct usb_serial_port *port);
245 int (*write)(struct tty_struct *tty, struct usb_serial_port *port, 244 int (*write)(struct tty_struct *tty, struct usb_serial_port *port,
246 const unsigned char *buf, int count); 245 const unsigned char *buf, int count);
@@ -261,6 +260,9 @@ struct usb_serial_driver {
261 be an attached tty at this point */ 260 be an attached tty at this point */
262 void (*dtr_rts)(struct usb_serial_port *port, int on); 261 void (*dtr_rts)(struct usb_serial_port *port, int on);
263 int (*carrier_raised)(struct usb_serial_port *port); 262 int (*carrier_raised)(struct usb_serial_port *port);
263 /* Called by the usb serial hooks to allow the user to rework the
264 termios state */
265 void (*init_termios)(struct tty_struct *tty);
264 /* USB events */ 266 /* USB events */
265 void (*read_int_callback)(struct urb *urb); 267 void (*read_int_callback)(struct urb *urb);
266 void (*write_int_callback)(struct urb *urb); 268 void (*write_int_callback)(struct urb *urb);
@@ -300,7 +302,7 @@ static inline void usb_serial_console_disconnect(struct usb_serial *serial) {}
300extern struct usb_serial *usb_serial_get_by_index(unsigned int minor); 302extern struct usb_serial *usb_serial_get_by_index(unsigned int minor);
301extern void usb_serial_put(struct usb_serial *serial); 303extern void usb_serial_put(struct usb_serial *serial);
302extern int usb_serial_generic_open(struct tty_struct *tty, 304extern int usb_serial_generic_open(struct tty_struct *tty,
303 struct usb_serial_port *port, struct file *filp); 305 struct usb_serial_port *port);
304extern int usb_serial_generic_write(struct tty_struct *tty, 306extern int usb_serial_generic_write(struct tty_struct *tty,
305 struct usb_serial_port *port, const unsigned char *buf, int count); 307 struct usb_serial_port *port, const unsigned char *buf, int count);
306extern void usb_serial_generic_close(struct usb_serial_port *port); 308extern void usb_serial_generic_close(struct usb_serial_port *port);
@@ -317,7 +319,8 @@ extern int usb_serial_generic_register(int debug);
317extern void usb_serial_generic_deregister(void); 319extern void usb_serial_generic_deregister(void);
318extern void usb_serial_generic_resubmit_read_urb(struct usb_serial_port *port, 320extern void usb_serial_generic_resubmit_read_urb(struct usb_serial_port *port,
319 gfp_t mem_flags); 321 gfp_t mem_flags);
320extern int usb_serial_handle_sysrq_char(struct usb_serial_port *port, 322extern int usb_serial_handle_sysrq_char(struct tty_struct *tty,
323 struct usb_serial_port *port,
321 unsigned int ch); 324 unsigned int ch);
322extern int usb_serial_handle_break(struct usb_serial_port *port); 325extern int usb_serial_handle_break(struct usb_serial_port *port);
323 326
diff --git a/include/linux/usb/usbnet.h b/include/linux/usb/usbnet.h
index 5d44059f6d63..bb69e256cd16 100644
--- a/include/linux/usb/usbnet.h
+++ b/include/linux/usb/usbnet.h
@@ -42,7 +42,6 @@ struct usbnet {
42 42
43 /* protocol/interface state */ 43 /* protocol/interface state */
44 struct net_device *net; 44 struct net_device *net;
45 struct net_device_stats stats;
46 int msg_enable; 45 int msg_enable;
47 unsigned long data [5]; 46 unsigned long data [5];
48 u32 xid; 47 u32 xid;
@@ -54,6 +53,7 @@ struct usbnet {
54 struct sk_buff_head rxq; 53 struct sk_buff_head rxq;
55 struct sk_buff_head txq; 54 struct sk_buff_head txq;
56 struct sk_buff_head done; 55 struct sk_buff_head done;
56 struct sk_buff_head rxq_pause;
57 struct urb *interrupt; 57 struct urb *interrupt;
58 struct tasklet_struct bh; 58 struct tasklet_struct bh;
59 59
@@ -64,6 +64,7 @@ struct usbnet {
64# define EVENT_RX_MEMORY 2 64# define EVENT_RX_MEMORY 2
65# define EVENT_STS_SPLIT 3 65# define EVENT_STS_SPLIT 3
66# define EVENT_LINK_RESET 4 66# define EVENT_LINK_RESET 4
67# define EVENT_RX_PAUSED 5
67}; 68};
68 69
69static inline struct usb_driver *driver_of(struct usb_interface *intf) 70static inline struct usb_driver *driver_of(struct usb_interface *intf)
@@ -87,6 +88,7 @@ struct driver_info {
87 88
88#define FLAG_FRAMING_AX 0x0040 /* AX88772/178 packets */ 89#define FLAG_FRAMING_AX 0x0040 /* AX88772/178 packets */
89#define FLAG_WLAN 0x0080 /* use "wlan%d" names */ 90#define FLAG_WLAN 0x0080 /* use "wlan%d" names */
91#define FLAG_AVOID_UNLINK_URBS 0x0100 /* don't unlink urbs at usbnet_stop() */
90 92
91 93
92 /* init device ... can sleep, or cause probe() failure */ 94 /* init device ... can sleep, or cause probe() failure */
@@ -98,6 +100,9 @@ struct driver_info {
98 /* reset device ... can sleep */ 100 /* reset device ... can sleep */
99 int (*reset)(struct usbnet *); 101 int (*reset)(struct usbnet *);
100 102
103 /* stop device ... can sleep */
104 int (*stop)(struct usbnet *);
105
101 /* see if peer is connected ... can sleep */ 106 /* see if peer is connected ... can sleep */
102 int (*check_connect)(struct usbnet *); 107 int (*check_connect)(struct usbnet *);
103 108
@@ -119,9 +124,8 @@ struct driver_info {
119 * right after minidriver have initialized hardware. */ 124 * right after minidriver have initialized hardware. */
120 int (*early_init)(struct usbnet *dev); 125 int (*early_init)(struct usbnet *dev);
121 126
122 /* called by minidriver when link state changes, state: 0=disconnect, 127 /* called by minidriver when receiving indication */
123 * 1=connect */ 128 void (*indication)(struct usbnet *dev, void *ind, int indlen);
124 void (*link_change)(struct usbnet *dev, int state);
125 129
126 /* for new devices, use the descriptor-reading code instead */ 130 /* for new devices, use the descriptor-reading code instead */
127 int in; /* rx endpoint */ 131 int in; /* rx endpoint */
@@ -178,7 +182,8 @@ struct skb_data { /* skb->cb is one of these */
178 182
179extern int usbnet_open (struct net_device *net); 183extern int usbnet_open (struct net_device *net);
180extern int usbnet_stop (struct net_device *net); 184extern int usbnet_stop (struct net_device *net);
181extern int usbnet_start_xmit (struct sk_buff *skb, struct net_device *net); 185extern netdev_tx_t usbnet_start_xmit (struct sk_buff *skb,
186 struct net_device *net);
182extern void usbnet_tx_timeout (struct net_device *net); 187extern void usbnet_tx_timeout (struct net_device *net);
183extern int usbnet_change_mtu (struct net_device *net, int new_mtu); 188extern int usbnet_change_mtu (struct net_device *net, int new_mtu);
184 189
@@ -188,6 +193,10 @@ extern void usbnet_defer_kevent (struct usbnet *, int);
188extern void usbnet_skb_return (struct usbnet *, struct sk_buff *); 193extern void usbnet_skb_return (struct usbnet *, struct sk_buff *);
189extern void usbnet_unlink_rx_urbs(struct usbnet *); 194extern void usbnet_unlink_rx_urbs(struct usbnet *);
190 195
196extern void usbnet_pause_rx(struct usbnet *);
197extern void usbnet_resume_rx(struct usbnet *);
198extern void usbnet_purge_paused_rxq(struct usbnet *);
199
191extern int usbnet_get_settings (struct net_device *net, struct ethtool_cmd *cmd); 200extern int usbnet_get_settings (struct net_device *net, struct ethtool_cmd *cmd);
192extern int usbnet_set_settings (struct net_device *net, struct ethtool_cmd *cmd); 201extern int usbnet_set_settings (struct net_device *net, struct ethtool_cmd *cmd);
193extern u32 usbnet_get_link (struct net_device *net); 202extern u32 usbnet_get_link (struct net_device *net);
diff --git a/include/linux/usb/video.h b/include/linux/usb/video.h
new file mode 100644
index 000000000000..be436d9ee479
--- /dev/null
+++ b/include/linux/usb/video.h
@@ -0,0 +1,164 @@
1/*
2 * USB Video Class definitions.
3 *
4 * Copyright (C) 2009 Laurent Pinchart <laurent.pinchart@skynet.be>
5 *
6 * This file holds USB constants and structures defined by the USB Device
7 * Class Definition for Video Devices. Unless otherwise stated, comments
8 * below reference relevant sections of the USB Video Class 1.1 specification
9 * available at
10 *
11 * http://www.usb.org/developers/devclass_docs/USB_Video_Class_1_1.zip
12 */
13
14#ifndef __LINUX_USB_VIDEO_H
15#define __LINUX_USB_VIDEO_H
16
17#include <linux/types.h>
18
19/* --------------------------------------------------------------------------
20 * UVC constants
21 */
22
23/* A.2. Video Interface Subclass Codes */
24#define UVC_SC_UNDEFINED 0x00
25#define UVC_SC_VIDEOCONTROL 0x01
26#define UVC_SC_VIDEOSTREAMING 0x02
27#define UVC_SC_VIDEO_INTERFACE_COLLECTION 0x03
28
29/* A.3. Video Interface Protocol Codes */
30#define UVC_PC_PROTOCOL_UNDEFINED 0x00
31
32/* A.5. Video Class-Specific VC Interface Descriptor Subtypes */
33#define UVC_VC_DESCRIPTOR_UNDEFINED 0x00
34#define UVC_VC_HEADER 0x01
35#define UVC_VC_INPUT_TERMINAL 0x02
36#define UVC_VC_OUTPUT_TERMINAL 0x03
37#define UVC_VC_SELECTOR_UNIT 0x04
38#define UVC_VC_PROCESSING_UNIT 0x05
39#define UVC_VC_EXTENSION_UNIT 0x06
40
41/* A.6. Video Class-Specific VS Interface Descriptor Subtypes */
42#define UVC_VS_UNDEFINED 0x00
43#define UVC_VS_INPUT_HEADER 0x01
44#define UVC_VS_OUTPUT_HEADER 0x02
45#define UVC_VS_STILL_IMAGE_FRAME 0x03
46#define UVC_VS_FORMAT_UNCOMPRESSED 0x04
47#define UVC_VS_FRAME_UNCOMPRESSED 0x05
48#define UVC_VS_FORMAT_MJPEG 0x06
49#define UVC_VS_FRAME_MJPEG 0x07
50#define UVC_VS_FORMAT_MPEG2TS 0x0a
51#define UVC_VS_FORMAT_DV 0x0c
52#define UVC_VS_COLORFORMAT 0x0d
53#define UVC_VS_FORMAT_FRAME_BASED 0x10
54#define UVC_VS_FRAME_FRAME_BASED 0x11
55#define UVC_VS_FORMAT_STREAM_BASED 0x12
56
57/* A.7. Video Class-Specific Endpoint Descriptor Subtypes */
58#define UVC_EP_UNDEFINED 0x00
59#define UVC_EP_GENERAL 0x01
60#define UVC_EP_ENDPOINT 0x02
61#define UVC_EP_INTERRUPT 0x03
62
63/* A.8. Video Class-Specific Request Codes */
64#define UVC_RC_UNDEFINED 0x00
65#define UVC_SET_CUR 0x01
66#define UVC_GET_CUR 0x81
67#define UVC_GET_MIN 0x82
68#define UVC_GET_MAX 0x83
69#define UVC_GET_RES 0x84
70#define UVC_GET_LEN 0x85
71#define UVC_GET_INFO 0x86
72#define UVC_GET_DEF 0x87
73
74/* A.9.1. VideoControl Interface Control Selectors */
75#define UVC_VC_CONTROL_UNDEFINED 0x00
76#define UVC_VC_VIDEO_POWER_MODE_CONTROL 0x01
77#define UVC_VC_REQUEST_ERROR_CODE_CONTROL 0x02
78
79/* A.9.2. Terminal Control Selectors */
80#define UVC_TE_CONTROL_UNDEFINED 0x00
81
82/* A.9.3. Selector Unit Control Selectors */
83#define UVC_SU_CONTROL_UNDEFINED 0x00
84#define UVC_SU_INPUT_SELECT_CONTROL 0x01
85
86/* A.9.4. Camera Terminal Control Selectors */
87#define UVC_CT_CONTROL_UNDEFINED 0x00
88#define UVC_CT_SCANNING_MODE_CONTROL 0x01
89#define UVC_CT_AE_MODE_CONTROL 0x02
90#define UVC_CT_AE_PRIORITY_CONTROL 0x03
91#define UVC_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04
92#define UVC_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05
93#define UVC_CT_FOCUS_ABSOLUTE_CONTROL 0x06
94#define UVC_CT_FOCUS_RELATIVE_CONTROL 0x07
95#define UVC_CT_FOCUS_AUTO_CONTROL 0x08
96#define UVC_CT_IRIS_ABSOLUTE_CONTROL 0x09
97#define UVC_CT_IRIS_RELATIVE_CONTROL 0x0a
98#define UVC_CT_ZOOM_ABSOLUTE_CONTROL 0x0b
99#define UVC_CT_ZOOM_RELATIVE_CONTROL 0x0c
100#define UVC_CT_PANTILT_ABSOLUTE_CONTROL 0x0d
101#define UVC_CT_PANTILT_RELATIVE_CONTROL 0x0e
102#define UVC_CT_ROLL_ABSOLUTE_CONTROL 0x0f
103#define UVC_CT_ROLL_RELATIVE_CONTROL 0x10
104#define UVC_CT_PRIVACY_CONTROL 0x11
105
106/* A.9.5. Processing Unit Control Selectors */
107#define UVC_PU_CONTROL_UNDEFINED 0x00
108#define UVC_PU_BACKLIGHT_COMPENSATION_CONTROL 0x01
109#define UVC_PU_BRIGHTNESS_CONTROL 0x02
110#define UVC_PU_CONTRAST_CONTROL 0x03
111#define UVC_PU_GAIN_CONTROL 0x04
112#define UVC_PU_POWER_LINE_FREQUENCY_CONTROL 0x05
113#define UVC_PU_HUE_CONTROL 0x06
114#define UVC_PU_SATURATION_CONTROL 0x07
115#define UVC_PU_SHARPNESS_CONTROL 0x08
116#define UVC_PU_GAMMA_CONTROL 0x09
117#define UVC_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x0a
118#define UVC_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0b
119#define UVC_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x0c
120#define UVC_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x0d
121#define UVC_PU_DIGITAL_MULTIPLIER_CONTROL 0x0e
122#define UVC_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x0f
123#define UVC_PU_HUE_AUTO_CONTROL 0x10
124#define UVC_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x11
125#define UVC_PU_ANALOG_LOCK_STATUS_CONTROL 0x12
126
127/* A.9.7. VideoStreaming Interface Control Selectors */
128#define UVC_VS_CONTROL_UNDEFINED 0x00
129#define UVC_VS_PROBE_CONTROL 0x01
130#define UVC_VS_COMMIT_CONTROL 0x02
131#define UVC_VS_STILL_PROBE_CONTROL 0x03
132#define UVC_VS_STILL_COMMIT_CONTROL 0x04
133#define UVC_VS_STILL_IMAGE_TRIGGER_CONTROL 0x05
134#define UVC_VS_STREAM_ERROR_CODE_CONTROL 0x06
135#define UVC_VS_GENERATE_KEY_FRAME_CONTROL 0x07
136#define UVC_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08
137#define UVC_VS_SYNC_DELAY_CONTROL 0x09
138
139/* B.1. USB Terminal Types */
140#define UVC_TT_VENDOR_SPECIFIC 0x0100
141#define UVC_TT_STREAMING 0x0101
142
143/* B.2. Input Terminal Types */
144#define UVC_ITT_VENDOR_SPECIFIC 0x0200
145#define UVC_ITT_CAMERA 0x0201
146#define UVC_ITT_MEDIA_TRANSPORT_INPUT 0x0202
147
148/* B.3. Output Terminal Types */
149#define UVC_OTT_VENDOR_SPECIFIC 0x0300
150#define UVC_OTT_DISPLAY 0x0301
151#define UVC_OTT_MEDIA_TRANSPORT_OUTPUT 0x0302
152
153/* B.4. External Terminal Types */
154#define UVC_EXTERNAL_VENDOR_SPECIFIC 0x0400
155#define UVC_COMPOSITE_CONNECTOR 0x0401
156#define UVC_SVIDEO_CONNECTOR 0x0402
157#define UVC_COMPONENT_CONNECTOR 0x0403
158
159/* 2.4.2.2. Status Packet Type */
160#define UVC_STATUS_TYPE_CONTROL 1
161#define UVC_STATUS_TYPE_STREAMING 2
162
163#endif /* __LINUX_USB_VIDEO_H */
164
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 03:38:54 -0500