aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/usb/langwell_udc.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux/usb/langwell_udc.h')
-rw-r--r--include/linux/usb/langwell_udc.h310
1 files changed, 310 insertions, 0 deletions
diff --git a/include/linux/usb/langwell_udc.h b/include/linux/usb/langwell_udc.h
new file mode 100644
index 000000000000..c949178a6530
--- /dev/null
+++ b/include/linux/usb/langwell_udc.h
@@ -0,0 +1,310 @@
1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#ifndef __LANGWELL_UDC_H
21#define __LANGWELL_UDC_H
22
23
24/* MACRO defines */
25#define CAP_REG_OFFSET 0x0
26#define OP_REG_OFFSET 0x28
27
28#define DMA_ADDR_INVALID (~(dma_addr_t)0)
29
30#define DQH_ALIGNMENT 2048
31#define DTD_ALIGNMENT 64
32#define DMA_BOUNDARY 4096
33
34#define EP0_MAX_PKT_SIZE 64
35#define EP_DIR_IN 1
36#define EP_DIR_OUT 0
37
38#define FLUSH_TIMEOUT 1000
39#define RESET_TIMEOUT 1000
40#define SETUPSTAT_TIMEOUT 100
41#define PRIME_TIMEOUT 100
42
43
44/* device memory space registers */
45
46/* Capability Registers, BAR0 + CAP_REG_OFFSET */
47struct langwell_cap_regs {
48 /* offset: 0x0 */
49 u8 caplength; /* offset of Operational Register */
50 u8 _reserved3;
51 u16 hciversion; /* H: BCD encoding of host version */
52 u32 hcsparams; /* H: host port steering logic capability */
53 u32 hccparams; /* H: host multiple mode control capability */
54#define HCC_LEN BIT(17) /* Link power management (LPM) capability */
55 u8 _reserved4[0x20-0xc];
56 /* offset: 0x20 */
57 u16 dciversion; /* BCD encoding of device version */
58 u8 _reserved5[0x24-0x22];
59 u32 dccparams; /* overall device controller capability */
60#define HOSTCAP BIT(8) /* host capable */
61#define DEVCAP BIT(7) /* device capable */
62#define DEN(d) \
63 (((d)>>0)&0x1f) /* bits 4:0, device endpoint number */
64} __attribute__ ((packed));
65
66
67/* Operational Registers, BAR0 + OP_REG_OFFSET */
68struct langwell_op_regs {
69 /* offset: 0x28 */
70 u32 extsts;
71#define EXTS_TI1 BIT(4) /* general purpose timer interrupt 1 */
72#define EXTS_TI1TI0 BIT(3) /* general purpose timer interrupt 0 */
73#define EXTS_TI1UPI BIT(2) /* USB host periodic interrupt */
74#define EXTS_TI1UAI BIT(1) /* USB host asynchronous interrupt */
75#define EXTS_TI1NAKI BIT(0) /* NAK interrupt */
76 u32 extintr;
77#define EXTI_TIE1 BIT(4) /* general purpose timer interrupt enable 1 */
78#define EXTI_TIE0 BIT(3) /* general purpose timer interrupt enable 0 */
79#define EXTI_UPIE BIT(2) /* USB host periodic interrupt enable */
80#define EXTI_UAIE BIT(1) /* USB host asynchronous interrupt enable */
81#define EXTI_NAKE BIT(0) /* NAK interrupt enable */
82 /* offset: 0x30 */
83 u32 usbcmd;
84#define CMD_HIRD(u) \
85 (((u)>>24)&0xf) /* bits 27:24, host init resume duration */
86#define CMD_ITC(u) \
87 (((u)>>16)&0xff) /* bits 23:16, interrupt threshold control */
88#define CMD_PPE BIT(15) /* per-port change events enable */
89#define CMD_ATDTW BIT(14) /* add dTD tripwire */
90#define CMD_SUTW BIT(13) /* setup tripwire */
91#define CMD_ASPE BIT(11) /* asynchronous schedule park mode enable */
92#define CMD_FS2 BIT(10) /* frame list size */
93#define CMD_ASP1 BIT(9) /* asynchronous schedule park mode count */
94#define CMD_ASP0 BIT(8)
95#define CMD_LR BIT(7) /* light host/device controller reset */
96#define CMD_IAA BIT(6) /* interrupt on async advance doorbell */
97#define CMD_ASE BIT(5) /* asynchronous schedule enable */
98#define CMD_PSE BIT(4) /* periodic schedule enable */
99#define CMD_FS1 BIT(3)
100#define CMD_FS0 BIT(2)
101#define CMD_RST BIT(1) /* controller reset */
102#define CMD_RUNSTOP BIT(0) /* run/stop */
103 u32 usbsts;
104#define STS_PPCI(u) \
105 (((u)>>16)&0xffff) /* bits 31:16, port-n change detect */
106#define STS_AS BIT(15) /* asynchronous schedule status */
107#define STS_PS BIT(14) /* periodic schedule status */
108#define STS_RCL BIT(13) /* reclamation */
109#define STS_HCH BIT(12) /* HC halted */
110#define STS_ULPII BIT(10) /* ULPI interrupt */
111#define STS_SLI BIT(8) /* DC suspend */
112#define STS_SRI BIT(7) /* SOF received */
113#define STS_URI BIT(6) /* USB reset received */
114#define STS_AAI BIT(5) /* interrupt on async advance */
115#define STS_SEI BIT(4) /* system error */
116#define STS_FRI BIT(3) /* frame list rollover */
117#define STS_PCI BIT(2) /* port change detect */
118#define STS_UEI BIT(1) /* USB error interrupt */
119#define STS_UI BIT(0) /* USB interrupt */
120 u32 usbintr;
121/* bits 31:16, per-port interrupt enable */
122#define INTR_PPCE(u) (((u)>>16)&0xffff)
123#define INTR_ULPIE BIT(10) /* ULPI enable */
124#define INTR_SLE BIT(8) /* DC sleep/suspend enable */
125#define INTR_SRE BIT(7) /* SOF received enable */
126#define INTR_URE BIT(6) /* USB reset enable */
127#define INTR_AAE BIT(5) /* interrupt on async advance enable */
128#define INTR_SEE BIT(4) /* system error enable */
129#define INTR_FRE BIT(3) /* frame list rollover enable */
130#define INTR_PCE BIT(2) /* port change detect enable */
131#define INTR_UEE BIT(1) /* USB error interrupt enable */
132#define INTR_UE BIT(0) /* USB interrupt enable */
133 u32 frindex; /* frame index */
134#define FRINDEX_MASK (0x3fff << 0)
135 u32 ctrldssegment; /* not used */
136 u32 deviceaddr;
137#define USBADR_SHIFT 25
138#define USBADR(d) \
139 (((d)>>25)&0x7f) /* bits 31:25, device address */
140#define USBADR_MASK (0x7f << 25)
141#define USBADRA BIT(24) /* device address advance */
142 u32 endpointlistaddr;/* endpoint list top memory address */
143/* bits 31:11, endpoint list pointer */
144#define EPBASE(d) (((d)>>11)&0x1fffff)
145#define ENDPOINTLISTADDR_MASK (0x1fffff << 11)
146 u32 ttctrl; /* H: TT operatin, not used */
147 /* offset: 0x50 */
148 u32 burstsize; /* burst size of data movement */
149#define TXPBURST(b) \
150 (((b)>>8)&0xff) /* bits 15:8, TX burst length */
151#define RXPBURST(b) \
152 (((b)>>0)&0xff) /* bits 7:0, RX burst length */
153 u32 txfilltuning; /* TX tuning */
154 u32 txttfilltuning; /* H: TX TT tuning */
155 u32 ic_usb; /* control the IC_USB FS/LS transceiver */
156 /* offset: 0x60 */
157 u32 ulpi_viewport; /* indirect access to ULPI PHY */
158#define ULPIWU BIT(31) /* ULPI wakeup */
159#define ULPIRUN BIT(30) /* ULPI read/write run */
160#define ULPIRW BIT(29) /* ULPI read/write control */
161#define ULPISS BIT(27) /* ULPI sync state */
162#define ULPIPORT(u) \
163 (((u)>>24)&7) /* bits 26:24, ULPI port number */
164#define ULPIADDR(u) \
165 (((u)>>16)&0xff) /* bits 23:16, ULPI data address */
166#define ULPIDATRD(u) \
167 (((u)>>8)&0xff) /* bits 15:8, ULPI data read */
168#define ULPIDATWR(u) \
169 (((u)>>0)&0xff) /* bits 7:0, ULPI date write */
170 u8 _reserved6[0x70-0x64];
171 /* offset: 0x70 */
172 u32 configflag; /* H: not used */
173 u32 portsc1; /* port status */
174#define DA(p) \
175 (((p)>>25)&0x7f) /* bits 31:25, device address */
176#define PORTS_SSTS (BIT(24) | BIT(23)) /* suspend status */
177#define PORTS_WKOC BIT(22) /* wake on over-current enable */
178#define PORTS_WKDS BIT(21) /* wake on disconnect enable */
179#define PORTS_WKCN BIT(20) /* wake on connect enable */
180#define PORTS_PTC(p) (((p)>>16)&0xf) /* bits 19:16, port test control */
181#define PORTS_PIC (BIT(15) | BIT(14)) /* port indicator control */
182#define PORTS_PO BIT(13) /* port owner */
183#define PORTS_PP BIT(12) /* port power */
184#define PORTS_LS (BIT(11) | BIT(10)) /* line status */
185#define PORTS_SLP BIT(9) /* suspend using L1 */
186#define PORTS_PR BIT(8) /* port reset */
187#define PORTS_SUSP BIT(7) /* suspend */
188#define PORTS_FPR BIT(6) /* force port resume */
189#define PORTS_OCC BIT(5) /* over-current change */
190#define PORTS_OCA BIT(4) /* over-current active */
191#define PORTS_PEC BIT(3) /* port enable/disable change */
192#define PORTS_PE BIT(2) /* port enable/disable */
193#define PORTS_CSC BIT(1) /* connect status change */
194#define PORTS_CCS BIT(0) /* current connect status */
195 u8 _reserved7[0xb4-0x78];
196 /* offset: 0xb4 */
197 u32 devlc; /* control LPM and each USB port behavior */
198/* bits 31:29, parallel transceiver select */
199#define LPM_PTS(d) (((d)>>29)&7)
200#define LPM_STS BIT(28) /* serial transceiver select */
201#define LPM_PTW BIT(27) /* parallel transceiver width */
202#define LPM_PSPD(d) (((d)>>25)&3) /* bits 26:25, port speed */
203#define LPM_PSPD_MASK (BIT(26) | BIT(25))
204#define LPM_SPEED_FULL 0
205#define LPM_SPEED_LOW 1
206#define LPM_SPEED_HIGH 2
207#define LPM_SRT BIT(24) /* shorten reset time */
208#define LPM_PFSC BIT(23) /* port force full speed connect */
209#define LPM_PHCD BIT(22) /* PHY low power suspend clock disable */
210#define LPM_STL BIT(16) /* STALL reply to LPM token */
211#define LPM_BA(d) \
212 (((d)>>1)&0x7ff) /* bits 11:1, BmAttributes */
213#define LPM_NYT_ACK BIT(0) /* NYET/ACK reply to LPM token */
214 u8 _reserved8[0xf4-0xb8];
215 /* offset: 0xf4 */
216 u32 otgsc; /* On-The-Go status and control */
217#define OTGSC_DPIE BIT(30) /* data pulse interrupt enable */
218#define OTGSC_MSE BIT(29) /* 1 ms timer interrupt enable */
219#define OTGSC_BSEIE BIT(28) /* B session end interrupt enable */
220#define OTGSC_BSVIE BIT(27) /* B session valid interrupt enable */
221#define OTGSC_ASVIE BIT(26) /* A session valid interrupt enable */
222#define OTGSC_AVVIE BIT(25) /* A VBUS valid interrupt enable */
223#define OTGSC_IDIE BIT(24) /* USB ID interrupt enable */
224#define OTGSC_DPIS BIT(22) /* data pulse interrupt status */
225#define OTGSC_MSS BIT(21) /* 1 ms timer interrupt status */
226#define OTGSC_BSEIS BIT(20) /* B session end interrupt status */
227#define OTGSC_BSVIS BIT(19) /* B session valid interrupt status */
228#define OTGSC_ASVIS BIT(18) /* A session valid interrupt status */
229#define OTGSC_AVVIS BIT(17) /* A VBUS valid interrupt status */
230#define OTGSC_IDIS BIT(16) /* USB ID interrupt status */
231#define OTGSC_DPS BIT(14) /* data bus pulsing status */
232#define OTGSC_MST BIT(13) /* 1 ms timer toggle */
233#define OTGSC_BSE BIT(12) /* B session end */
234#define OTGSC_BSV BIT(11) /* B session valid */
235#define OTGSC_ASV BIT(10) /* A session valid */
236#define OTGSC_AVV BIT(9) /* A VBUS valid */
237#define OTGSC_USBID BIT(8) /* USB ID */
238#define OTGSC_HABA BIT(7) /* hw assist B-disconnect to A-connect */
239#define OTGSC_HADP BIT(6) /* hw assist data pulse */
240#define OTGSC_IDPU BIT(5) /* ID pullup */
241#define OTGSC_DP BIT(4) /* data pulsing */
242#define OTGSC_OT BIT(3) /* OTG termination */
243#define OTGSC_HAAR BIT(2) /* hw assist auto reset */
244#define OTGSC_VC BIT(1) /* VBUS charge */
245#define OTGSC_VD BIT(0) /* VBUS discharge */
246 u32 usbmode;
247#define MODE_VBPS BIT(5) /* R/W VBUS power select */
248#define MODE_SDIS BIT(4) /* R/W stream disable mode */
249#define MODE_SLOM BIT(3) /* R/W setup lockout mode */
250#define MODE_ENSE BIT(2) /* endian select */
251#define MODE_CM(u) (((u)>>0)&3) /* bits 1:0, controller mode */
252#define MODE_IDLE 0
253#define MODE_DEVICE 2
254#define MODE_HOST 3
255 u8 _reserved9[0x100-0xfc];
256 /* offset: 0x100 */
257 u32 endptnak;
258#define EPTN(e) \
259 (((e)>>16)&0xffff) /* bits 31:16, TX endpoint NAK */
260#define EPRN(e) \
261 (((e)>>0)&0xffff) /* bits 15:0, RX endpoint NAK */
262 u32 endptnaken;
263#define EPTNE(e) \
264 (((e)>>16)&0xffff) /* bits 31:16, TX endpoint NAK enable */
265#define EPRNE(e) \
266 (((e)>>0)&0xffff) /* bits 15:0, RX endpoint NAK enable */
267 u32 endptsetupstat;
268#define SETUPSTAT_MASK (0xffff << 0) /* bits 15:0 */
269#define EP0SETUPSTAT_MASK 1
270 u32 endptprime;
271/* bits 31:16, prime endpoint transmit buffer */
272#define PETB(e) (((e)>>16)&0xffff)
273/* bits 15:0, prime endpoint receive buffer */
274#define PERB(e) (((e)>>0)&0xffff)
275 /* offset: 0x110 */
276 u32 endptflush;
277/* bits 31:16, flush endpoint transmit buffer */
278#define FETB(e) (((e)>>16)&0xffff)
279/* bits 15:0, flush endpoint receive buffer */
280#define FERB(e) (((e)>>0)&0xffff)
281 u32 endptstat;
282/* bits 31:16, endpoint transmit buffer ready */
283#define ETBR(e) (((e)>>16)&0xffff)
284/* bits 15:0, endpoint receive buffer ready */
285#define ERBR(e) (((e)>>0)&0xffff)
286 u32 endptcomplete;
287/* bits 31:16, endpoint transmit complete event */
288#define ETCE(e) (((e)>>16)&0xffff)
289/* bits 15:0, endpoint receive complete event */
290#define ERCE(e) (((e)>>0)&0xffff)
291 /* offset: 0x11c */
292 u32 endptctrl[16];
293#define EPCTRL_TXE BIT(23) /* TX endpoint enable */
294#define EPCTRL_TXR BIT(22) /* TX data toggle reset */
295#define EPCTRL_TXI BIT(21) /* TX data toggle inhibit */
296#define EPCTRL_TXT(e) (((e)>>18)&3) /* bits 19:18, TX endpoint type */
297#define EPCTRL_TXT_SHIFT 18
298#define EPCTRL_TXD BIT(17) /* TX endpoint data source */
299#define EPCTRL_TXS BIT(16) /* TX endpoint STALL */
300#define EPCTRL_RXE BIT(7) /* RX endpoint enable */
301#define EPCTRL_RXR BIT(6) /* RX data toggle reset */
302#define EPCTRL_RXI BIT(5) /* RX data toggle inhibit */
303#define EPCTRL_RXT(e) (((e)>>2)&3) /* bits 3:2, RX endpoint type */
304#define EPCTRL_RXT_SHIFT 2 /* bits 19:18, TX endpoint type */
305#define EPCTRL_RXD BIT(1) /* RX endpoint data sink */
306#define EPCTRL_RXS BIT(0) /* RX endpoint STALL */
307} __attribute__ ((packed));
308
309#endif /* __LANGWELL_UDC_H */
310
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 17:54:07 -0500