1 files changed, 56 insertions, 1 deletions

diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 0dddc9e42b6b..b69bdb1e08b6 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -28,6 +28,51 @@
 
 #include <linux/platform_device.h>
 
+#define STMMAC_RX_COE_NONE      0
+#define STMMAC_RX_COE_TYPE1     1
+#define STMMAC_RX_COE_TYPE2     2
+
+/* Define the macros for CSR clock range parameters to be passed by
+ * platform code.
+ * This could also be configured at run time using CPU freq framework. */
+
+/* MDC Clock Selection define*/
+#define STMMAC_CSR_60_100M      0x0     /* MDC = clk_scr_i/42 */
+#define STMMAC_CSR_100_150M     0x1     /* MDC = clk_scr_i/62 */
+#define STMMAC_CSR_20_35M       0x2     /* MDC = clk_scr_i/16 */
+#define STMMAC_CSR_35_60M       0x3     /* MDC = clk_scr_i/26 */
+#define STMMAC_CSR_150_250M     0x4     /* MDC = clk_scr_i/102 */
+#define STMMAC_CSR_250_300M     0x5     /* MDC = clk_scr_i/122 */
+
+/* The MDC clock could be set higher than the IEEE 802.3
+ * specified frequency limit 0f 2.5 MHz, by programming a clock divider
+ * of value different than the above defined values. The resultant MDIO
+ * clock frequency of 12.5 MHz is applicable for the interfacing chips
+ * supporting higher MDC clocks.
+ * The MDC clock selection macros need to be defined for MDC clock rate
+ * of 12.5 MHz, corresponding to the following selection.
+ */
+#define STMMAC_CSR_I_4          0x8     /* clk_csr_i/4 */
+#define STMMAC_CSR_I_6          0x9     /* clk_csr_i/6 */
+#define STMMAC_CSR_I_8          0xA     /* clk_csr_i/8 */
+#define STMMAC_CSR_I_10         0xB     /* clk_csr_i/10 */
+#define STMMAC_CSR_I_12         0xC     /* clk_csr_i/12 */
+#define STMMAC_CSR_I_14         0xD     /* clk_csr_i/14 */
+#define STMMAC_CSR_I_16         0xE     /* clk_csr_i/16 */
+#define STMMAC_CSR_I_18         0xF     /* clk_csr_i/18 */
+
+/* AXI DMA Burst length suported */
+#define DMA_AXI_BLEN_4          (1 << 1)
+#define DMA_AXI_BLEN_8          (1 << 2)
+#define DMA_AXI_BLEN_16         (1 << 3)
+#define DMA_AXI_BLEN_32         (1 << 4)
+#define DMA_AXI_BLEN_64         (1 << 5)
+#define DMA_AXI_BLEN_128        (1 << 6)
+#define DMA_AXI_BLEN_256        (1 << 7)
+#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
+                        | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
+                        | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
+
 /* Platfrom data for platform device structure's platform_data field */
 
 struct stmmac_mdio_bus_data {
@@ -38,16 +83,25 @@ struct stmmac_mdio_bus_data {
         int probed_phy_irq;
 };
 
+struct stmmac_dma_cfg {
+        int pbl;
+        int fixed_burst;
+        int mixed_burst;
+        int burst_len;
+};
+
 struct plat_stmmacenet_data {
+        char *phy_bus_name;
         int bus_id;
         int phy_addr;
         int interface;
         struct stmmac_mdio_bus_data *mdio_bus_data;
-        int pbl;
+        struct stmmac_dma_cfg *dma_cfg;
         int clk_csr;
         int has_gmac;
         int enh_desc;
         int tx_coe;
+        int rx_coe;
         int bugged_jumbo;
         int pmt;
         int force_sf_dma_mode;
@@ -56,6 +110,7 @@ struct plat_stmmacenet_data {
         int (*init)(struct platform_device *pdev);
         void (*exit)(struct platform_device *pdev);
         void *custom_cfg;
+        void *custom_data;
         void *bsp_priv;
 };
 #endif